SBE move import`

Change-Id: I726951318cdb19fd445af2f7910e0d6872eff18c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29086
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>

405 files changed, 378599 insertions, 0 deletions

diff --git a/src/import/.empty b/src/import/.empty
new file mode 100644
index 00000000..e69de29b
--- /dev/null
+++ b/src/import/.empty
diff --git a/src/import/chips/p9/common/include/p9_const_common.H b/src/import/chips/p9/common/include/p9_const_common.H
new file mode 100644
index 00000000..e71d288b
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_const_common.H
@@ -0,0 +1,114 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_const_common.H $            */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+
+/*! \brief These are macros used for the scom_addresses.H
+ *
+ *  Provides macro defintions for defining scom constants
+ *  for assembly and C
+ *
+ */
+
+// - HWP metadata
+
+///
+/// @file const_common.H
+/// @brief These are macros used for the scom_addresses.H
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SoA
+// *HWP Level: 1
+// *HWP Consumed by: XX:XX
+
+
+#ifndef __CONST_COMMON_H
+#define __CONST_COMMON_H
+
+#if defined __ASSEMBLER__
+
+//This probably won't work :(
+//  Not sure you can do .set for the same name.
+//  If so, it probably takes the last one, which would be the incorrect one
+//#define FIXREG8(name, expr, unit, meth, newexpr) .set name, (newexpr)
+//#define FIXREG32(name, expr, unit, meth, newexpr) .set name, (newexpr)
+//#define FIXREG64(name, expr, unit, meth, newexpr) .set name, (newexpr)
+//
+//#define CONST_UINT8_T(name, expr, unit, meth) .set name, (expr)
+//#define CONST_UINT32_T(name, expr, unit, meth) .set name, (expr)
+//#define CONST_UINT64_T(name, expr, unit, meth) .set name, (expr)
+
+#define RULL(x) x
+
+#elif defined __cplusplus
+
+#include <stdint.h>
+
+template <typename T, uint64_t UNIT, uint64_t METH, T REG >
+struct has_fixup
+{
+    static const T value = T(0);
+};
+
+template <typename T, uint64_t UNIT, uint64_t METH, T REG, uint64_t FLD >
+struct has_fixfld
+{
+    static const uint8_t value = 255;
+};
+
+
+#define FIXREG8(name, expr, unit, meth, newexpr) template<> struct has_fixup<uint8_t,unit,meth,expr> { static const uint8_t value = newexpr; };
+#define FIXREG32(name, expr, unit, meth, newexpr) template<> struct has_fixup<uint32_t,unit,meth,expr> { static const uint32_t value = newexpr; };
+#define FIXREG64(name, expr, unit, meth, newexpr) template<> struct has_fixup<uint64_t,unit,meth,expr> { static const uint64_t value = newexpr; };
+
+#define REG8(name, expr, unit, meth) static const uint8_t name = has_fixup<uint8_t,unit,meth,expr>::value ? has_fixup<uint8_t,unit,meth,expr>::value : expr;
+#define REG32(name, expr, unit, meth) static const uint32_t name = has_fixup<uint32_t,unit,meth,expr>::value ? has_fixup<uint32_t,unit,meth,expr>::value : expr;
+#define REG64(name, expr, unit, meth) static const uint64_t name = has_fixup<uint64_t,unit,meth,expr>::value ? has_fixup<uint64_t,unit,meth,expr>::value : expr;
+
+#define FIXREG8_FLD(name, expr, unit, meth, fld, newexpr) template<> struct has_fixfld<uint8_t,unit,meth,expr,fld> { static const uint8_t value = newexpr; };
+#define FIXREG32_FLD(name, expr, unit, meth, fld, newexpr) template<> struct has_fixfld<uint32_t,unit,meth,expr,fld> { static const uint32_t value = newexpr; };
+#define FIXREG64_FLD(name, expr, unit, meth, fld, newexpr) template<> struct has_fixfld<uint64_t,unit,meth,expr,fld> { static const uint64_t value = newexpr; };
+
+#define REG8_FLD(name, expr, unit, meth, fld) static const uint8_t name = has_fixfld<uint8_t,unit,meth,expr,fld>::value != 255 ? has_fixfld<uint8_t,unit,meth,expr,fld>::value : expr;
+#define REG32_FLD(name, expr, unit, meth, fld) static const uint8_t name = has_fixfld<uint32_t,unit,meth,expr,fld>::value != 255 ? has_fixfld<uint32_t,unit,meth,expr,fld>::value : expr;
+#define REG64_FLD(name, expr, unit, meth, fld) static const uint8_t name = has_fixfld<uint64_t,unit,meth,expr,fld>::value != 255 ? has_fixfld<uint64_t,unit,meth,expr,fld>::value : expr;
+
+#define RULL(x) x##ull
+
+//Remove the chiplet id from any register so that it can
+//be used with pu.perv target type
+#define FORCE_PERV(val) (RULL(0xFFFFFFFF00FFFFFF) & val)
+
+#else // C code
+
+// CONST_UINT[8,3,64]_T() can't be used in C code/headers; Use
+//
+//     #define <symbol> <value> [ or ULL(<value>) for 64-bit constants
+
+#define RULL(x) x##ull
+
+#endif  // __ASSEMBLER__
+
+#endif  // __CONST_COMMON_H
diff --git a/src/import/chips/p9/common/include/p9_mc_scom_addresses.H b/src/import/chips/p9/common/include/p9_mc_scom_addresses.H
new file mode 100644
index 00000000..e9c23ad4
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_mc_scom_addresses.H
@@ -0,0 +1,40518 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_mc_scom_addresses.H $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_mc_scom_addresses.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+/*---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ *
+ *  Issues:
+ *
+ * Closed
+ *    TOD reg same address.             HW323439
+ *       - Issue was closed with the explaination "same as p8"
+ *    IO0 registers need fixed.         HW320437
+ *    PHB registers need fixed.         HW320416  ( all regs commented out now )
+ *    OSC/perv regs same address.       HW323437
+ *    MC regs with same address.        HW323435 (matteo)
+ *         Duplicate IOM registers.          HW320456 (designers)
+ *    PEC Sat_id issue                  HW329652
+ *    PB.PB_PPE registers need fixed.   HW320435
+ *    EX05 registers need fixed.        HW320427  (9020) - L2 ring id's are incorrect
+ *    IOFPPE registers need fixed.      HW320424  (9020) - Investigate NULL scope
+ *    PEC addresses are wrong.          HW322598  (9020)
+ *    MC registers need fixed.          HW320433
+ *    VA.VA_NORTH registers need fixed. HW320436
+ *
+ * Format:
+ *
+ *  <UNIT>_<SUBUNIT>_<INSTANCE>_<REGISTER>_<ACCESS/TYPE>
+ *
+ *  Notes: Subunits are only added to make names unique when
+ *  there are name collisions.
+ *  Only units with more than one instance has instance numbers.
+ *  If there is only one, the instance number is omitted.
+ *
+ *  Instance numbers are chiplet id's for the PERV unit.  The
+ *  chiplet id's are mapped to their name and used instead of
+ *  instance numbers.  See bellow.
+ *
+ *  For registers with a single access type the type and access
+ *  methods are omitted.
+ *
+ *  For access types where all bits have the same access methods, the
+ *  access method is appended to the name.  If the access methods
+ *  are different for some bits, the access type is appended to the
+ *  name _SCOM instead of _RO.  The _RW(X) access method is omitted
+ *  and assumed to be default.
+ *
+ *  Valid units / subunits
+ *    PU                    : No unit chip level
+ *        MCD0[0..1]        : mcd subunit
+ *        PIB2OPB[0..1]     : PIB2OPB subunit
+ *        OTPROM[0..1]      : otprom subunit
+ *        NPU               : common npu subunit
+ *        NPU[0..2]         : Npu stacks 0 to 2
+ *          CTL             : Npu CTL subunit
+ *          DAT             : Npu DAT subunit
+ *          SM[0..3]        : Npu SM subunits
+ *          NTL[0..1]       : Npu NTL subunit
+ *    PERV                  : Pervasive
+ *        FSI2PIB           : subunit
+ *        FSISHIFT          : subunit
+ *        FSII2C            : subunit
+ *        FSB               : subunit
+ *    EX                    : Ex unit (1/2 quad, 2 cores)
+ *        L2                : L2 subunit
+ *        L3                : L3 subunit
+ *    PEC                   : PCI Pec unit
+ *        STACK0            : subunit
+ *        STACK1            : subunit
+ *        STACK2            : subunit
+ *    C                     : core
+ *    EQ                    : quad
+ *    OBUS                  : obus
+ *    CAPP                  : capp
+ *    MCBIST                : mcbist
+ *    MCA                   : mca
+ *    NVBUS                 : (not implemented yet)
+ *    PHB                   : (not implemented yet)
+ *    MI                    : (not implemented yet)
+ *    DMI                   : (not implemented yet)
+ *    MCS                   : (not implemented yet)
+ *    OCC                   : (not implemented yet)
+ *    PPE                   : (not implemented yet)
+ *    SBE                   : (not implemented yet)
+ *    XBUS                  : (not implemented yet)
+ *
+ * Pervasive instance names follow chiplet id.
+ *
+ * Instance/  | Chiplet
+ * Chiplet    | name
+ * -----------+-----------
+ * 0x00       | PIB
+ * 0x01       | TP
+ * 0x02       | N0
+ * 0x03       | N1
+ * 0x04       | N2
+ * 0x05       | N3
+ * 0x06       | XB
+ * 0x07       | MC01
+ * 0x08       | MC23
+ * 0x09       | OB0
+ * 0x0A       | OB1
+ * 0x0B       | OB2
+ * 0x0C       | OB3
+ * 0x0D       | PCI0
+ * 0x0E       | PCI1
+ * 0x0F       | PCI2
+ * 0x10       | EP00
+ * 0x11       | EP01
+ * 0x12       | EP02
+ * 0x13       | EP03
+ * 0x14       | EP04
+ * 0x15       | EP05
+ * 0x20       | EC00
+ * 0x21       | EC01
+ * 0x22       | EC02
+ * 0x23       | EC03
+ * 0x24       | EC04
+ * 0x25       | EC05
+ * 0x26       | EC06
+ * 0x27       | EC07
+ * 0x28       | EC08
+ * 0x29       | EC09
+ * 0x2A       | EC10
+ * 0x2B       | EC11
+ * 0x2C       | EC12
+ * 0x2D       | EC13
+ * 0x2E       | EC14
+ * 0x2F       | EC15
+ * 0x30       | EC16
+ * 0x31       | EC17
+ * 0x32       | EC18
+ * 0x33       | EC19
+ * 0x34       | EC20
+ * 0x35       | EC21
+ * 0x36       | EC22
+ * 0x37       | EC23
+ *
+ *
+ *---------------------------------------------------------------
+ *
+ * NOTES:
+ *
+ * there is a SPR ring that goes around the chip with an
+ * address(0:9)/tid(0:1) (thread id)/mfspr_data(0:63) and return mfspr_data_v/mfspr_data(0:63)
+ *
+ *    Add PU_<SUBUNITS>  (only if there are conflicts on these registers)
+ *       0x0001XXXX OTPROM
+ *       0x0002XXXX FSIM0
+ *       0x0003XXXX FSIM1
+ *       0x0004XXXX TOD
+ *       0x0005XXXX FSI_MBOX
+ *       0x0006XXXX OCI_BRIDGE
+ *       0x0007XXXX SPI_ADC
+ *       0x0008XXXX PIBMEM
+ *       0x0009XXXX ADU
+ *       0x000AXXXX I2CM
+ *       0x000BXXXX SBE_FIFO
+ *       0x000DXXXX PSU
+ *       0x000EXXXX SBE
+ *
+ * 0x0000100A for FSI2PIB  => PERV_FSI2PIB
+ * 0x00000Cxx for FSISHIFT =>  PERV_FSISHIFT
+ * 0x000018xx for FSI I2C =>  PERV_FSII2C
+ * 0x000024xx for FSI SBEFIFO => PERV_FSB
+ *
+ * 0x00000400 PEEK_TABLE
+ * 0x00000800 FSI_SLAVE
+ * 0x00000C00 FSI_SHIFT
+ * 0x00001000 FSI2PIB
+ * 0x00001400 FSI_SCRATCHPAD
+ * 0x00001800 FSI_I2CM
+ * 0x00002400 FSI_SBE_FIFO
+ *
+ * address fields
+ * 0xCCRPxxxx
+ *
+ * CC=chiplet
+ * R=always 0?
+ * P=port
+ *   0=gpregs
+ *   1=normal unit scom ring (exclude)
+ *   3=clock controller
+ *   4=firs
+ *   5=cpm
+ *
+ * =============================================================================
+ * Compiling
+ *
+ * Precompile the header to save time on subsquent compiles:
+ * g++ -I. -c scom_addresses.H
+ *
+ * Use these options to help reduce the binary size
+ * g++ -I. -Os -fdata-sections -ffunction-sections <file>.C -o <output> -Wl,--gc-sections
+ *
+ *
+ *---------------------------------------------------------------
+ */
+
+#include <p9_const_common.H>
+
+
+#ifndef __P9_MC_SCOM_ADDRESSES_H
+#define __P9_MC_SCOM_ADDRESSES_H
+
+
+#include <p9_scom_template_consts.H>
+#include <p9_mc_scom_addresses_fixes.H>
+
+
+REG64( MCA_0_WREITE_AACR                                       , RULL(0x07010A29), SH_UNT_MCA_0_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_1_WREITE_AACR                                       , RULL(0x07010A69), SH_UNT_MCA_1_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_2_WREITE_AACR                                       , RULL(0x07010AA9), SH_UNT_MCA_2_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_3_WREITE_AACR                                       , RULL(0x07010AE9), SH_UNT_MCA_3_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_WREITE_AACR                                       , RULL(0x08010A29), SH_UNT_MCA_4_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_WREITE_AACR                                       , RULL(0x08010A69), SH_UNT_MCA_5_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_WREITE_AACR                                       , RULL(0x08010AA9), SH_UNT_MCA_6_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_WREITE_AACR                                       , RULL(0x08010AE9), SH_UNT_MCA_7_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_WREITE_AACR                                         , RULL(0x07010A29), SH_UNT_MCA_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_0_PORT02_AACR                                       , RULL(0x0501082C), SH_UNT_MCS_0_PORT02,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_1_PORT02_AACR                                       , RULL(0x050108AC), SH_UNT_MCS_1_PORT02,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_2_PORT02_AACR                                       , RULL(0x0301082C), SH_UNT_MCS_2_PORT02,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_3_PORT02_AACR                                       , RULL(0x030108AC), SH_UNT_MCS_3_PORT02,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_PORT02_AACR                                         , RULL(0x0501082C), SH_UNT_MCS_PORT02,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_AADR                                                , RULL(0x07010A2A), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_AADR                                              , RULL(0x07010A2A), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_AADR                                              , RULL(0x07010A6A), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_AADR                                              , RULL(0x07010AAA), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_AADR                                              , RULL(0x07010AEA), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_AADR                                              , RULL(0x08010A2A), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_AADR                                              , RULL(0x08010A6A), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_AADR                                              , RULL(0x08010AAA), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_AADR                                              , RULL(0x08010AEA), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+REG64( MCS_0_PORT02_AADR                                       , RULL(0x0501082D), SH_UNT_MCS_0_PORT02,
+       SH_ACS_SCOM_RO   );
+REG64( MCS_1_PORT02_AADR                                       , RULL(0x050108AD), SH_UNT_MCS_1_PORT02,
+       SH_ACS_SCOM_RO   );
+REG64( MCS_2_PORT02_AADR                                       , RULL(0x0301082D), SH_UNT_MCS_2_PORT02,
+       SH_ACS_SCOM_RO   );
+REG64( MCS_3_PORT02_AADR                                       , RULL(0x030108AD), SH_UNT_MCS_3_PORT02,
+       SH_ACS_SCOM_RO   );
+REG64( MCS_PORT02_AADR                                         , RULL(0x0501082D), SH_UNT_MCS_PORT02,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_AAER                                                , RULL(0x07010A2B), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_AAER                                              , RULL(0x07010A2B), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_AAER                                              , RULL(0x07010A6B), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_AAER                                              , RULL(0x07010AAB), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_AAER                                              , RULL(0x07010AEB), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_AAER                                              , RULL(0x08010A2B), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_AAER                                              , RULL(0x08010A6B), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_AAER                                              , RULL(0x08010AAB), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_AAER                                              , RULL(0x08010AEB), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+REG64( MCS_0_PORT02_AAER                                       , RULL(0x0501082E), SH_UNT_MCS_0_PORT02,
+       SH_ACS_SCOM_RO   );
+REG64( MCS_1_PORT02_AAER                                       , RULL(0x050108AE), SH_UNT_MCS_1_PORT02,
+       SH_ACS_SCOM_RO   );
+REG64( MCS_2_PORT02_AAER                                       , RULL(0x0301082E), SH_UNT_MCS_2_PORT02,
+       SH_ACS_SCOM_RO   );
+REG64( MCS_3_PORT02_AAER                                       , RULL(0x030108AE), SH_UNT_MCS_3_PORT02,
+       SH_ACS_SCOM_RO   );
+REG64( MCS_PORT02_AAER                                         , RULL(0x0501082E), SH_UNT_MCS_PORT02,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_ACTION0                                             , RULL(0x07010A06), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_ACTION0                                           , RULL(0x07010A06), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_ACTION0                                           , RULL(0x07010A46), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_ACTION0                                           , RULL(0x07010A86), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_ACTION0                                           , RULL(0x07010AC6), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_ACTION0                                           , RULL(0x08010A06), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_ACTION0                                           , RULL(0x08010A46), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_ACTION0                                           , RULL(0x08010A86), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_ACTION0                                           , RULL(0x08010AC6), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_ACTION1                                             , RULL(0x07010A07), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_ACTION1                                           , RULL(0x07010A07), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_ACTION1                                           , RULL(0x07010A47), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_ACTION1                                           , RULL(0x07010A87), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_ACTION1                                           , RULL(0x07010AC7), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_ACTION1                                           , RULL(0x08010A07), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_ACTION1                                           , RULL(0x08010A47), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_ACTION1                                           , RULL(0x08010A87), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_ACTION1                                           , RULL(0x08010AC7), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_ADDR_TRAP_REG                                       , RULL(0x07010003), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_ADDR_TRAP_REG                                     , RULL(0x07010003), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+REG64( MCA_4_ADDR_TRAP_REG                                     , RULL(0x08010003), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCA_ATOMIC_LOCK_MASK_LATCH_REG                          , RULL(0x07010007), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_ATOMIC_LOCK_MASK_LATCH_REG                        , RULL(0x07010007), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+REG64( MCA_4_ATOMIC_LOCK_MASK_LATCH_REG                        , RULL(0x08010007), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCBIST_CCSARRERRINJQ                                    , RULL(0x070123DE), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCSARRERRINJQ                                  , RULL(0x070123DE), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCSARRERRINJQ                                  , RULL(0x080123DE), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_CNTLQ                                        , RULL(0x070123A5), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_CNTLQ                                      , RULL(0x070123A5), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_CNTLQ                                      , RULL(0x080123A5), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_FIXED_DATA0Q                                 , RULL(0x070123E5), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_FIXED_DATA0Q                               , RULL(0x070123E5), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_FIXED_DATA0Q                               , RULL(0x080123E5), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_FIXED_DATA1Q                                 , RULL(0x070123E6), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_FIXED_DATA1Q                               , RULL(0x070123E6), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_FIXED_DATA1Q                               , RULL(0x080123E6), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_00                                 , RULL(0x07012315), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_00                               , RULL(0x07012315), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_00                               , RULL(0x08012315), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_01                                 , RULL(0x07012316), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_01                               , RULL(0x07012316), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_01                               , RULL(0x08012316), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_02                                 , RULL(0x07012317), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_02                               , RULL(0x07012317), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_02                               , RULL(0x08012317), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_03                                 , RULL(0x07012318), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_03                               , RULL(0x07012318), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_03                               , RULL(0x08012318), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_04                                 , RULL(0x07012319), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_04                               , RULL(0x07012319), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_04                               , RULL(0x08012319), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_05                                 , RULL(0x0701231A), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_05                               , RULL(0x0701231A), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_05                               , RULL(0x0801231A), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_06                                 , RULL(0x0701231B), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_06                               , RULL(0x0701231B), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_06                               , RULL(0x0801231B), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_07                                 , RULL(0x0701231C), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_07                               , RULL(0x0701231C), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_07                               , RULL(0x0801231C), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_08                                 , RULL(0x0701231D), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_08                               , RULL(0x0701231D), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_08                               , RULL(0x0801231D), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_09                                 , RULL(0x0701231E), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_09                               , RULL(0x0701231E), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_09                               , RULL(0x0801231E), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_10                                 , RULL(0x0701231F), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_10                               , RULL(0x0701231F), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_10                               , RULL(0x0801231F), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_11                                 , RULL(0x07012320), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_11                               , RULL(0x07012320), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_11                               , RULL(0x08012320), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_12                                 , RULL(0x07012321), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_12                               , RULL(0x07012321), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_12                               , RULL(0x08012321), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_13                                 , RULL(0x07012322), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_13                               , RULL(0x07012322), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_13                               , RULL(0x08012322), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_14                                 , RULL(0x07012323), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_14                               , RULL(0x07012323), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_14                               , RULL(0x08012323), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_15                                 , RULL(0x07012324), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_15                               , RULL(0x07012324), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_15                               , RULL(0x08012324), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_16                                 , RULL(0x07012325), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_16                               , RULL(0x07012325), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_16                               , RULL(0x08012325), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_17                                 , RULL(0x07012326), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_17                               , RULL(0x07012326), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_17                               , RULL(0x08012326), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_18                                 , RULL(0x07012327), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_18                               , RULL(0x07012327), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_18                               , RULL(0x08012327), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_19                                 , RULL(0x07012328), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_19                               , RULL(0x07012328), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_19                               , RULL(0x08012328), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_20                                 , RULL(0x07012329), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_20                               , RULL(0x07012329), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_20                               , RULL(0x08012329), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_21                                 , RULL(0x0701232A), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_21                               , RULL(0x0701232A), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_21                               , RULL(0x0801232A), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_22                                 , RULL(0x0701232B), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_22                               , RULL(0x0701232B), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_22                               , RULL(0x0801232B), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_23                                 , RULL(0x0701232C), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_23                               , RULL(0x0701232C), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_23                               , RULL(0x0801232C), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_24                                 , RULL(0x0701232D), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_24                               , RULL(0x0701232D), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_24                               , RULL(0x0801232D), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_25                                 , RULL(0x0701232E), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_25                               , RULL(0x0701232E), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_25                               , RULL(0x0801232E), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_26                                 , RULL(0x0701232F), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_26                               , RULL(0x0701232F), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_26                               , RULL(0x0801232F), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_27                                 , RULL(0x07012330), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_27                               , RULL(0x07012330), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_27                               , RULL(0x08012330), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_28                                 , RULL(0x07012331), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_28                               , RULL(0x07012331), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_28                               , RULL(0x08012331), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_29                                 , RULL(0x07012332), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_29                               , RULL(0x07012332), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_29                               , RULL(0x08012332), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_30                                 , RULL(0x07012333), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_30                               , RULL(0x07012333), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_30                               , RULL(0x08012333), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR0_31                                 , RULL(0x07012334), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR0_31                               , RULL(0x07012334), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR0_31                               , RULL(0x08012334), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_00                                 , RULL(0x07012335), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_00                               , RULL(0x07012335), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_00                               , RULL(0x08012335), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_01                                 , RULL(0x07012336), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_01                               , RULL(0x07012336), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_01                               , RULL(0x08012336), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_02                                 , RULL(0x07012337), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_02                               , RULL(0x07012337), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_02                               , RULL(0x08012337), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_03                                 , RULL(0x07012338), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_03                               , RULL(0x07012338), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_03                               , RULL(0x08012338), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_04                                 , RULL(0x07012339), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_04                               , RULL(0x07012339), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_04                               , RULL(0x08012339), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_05                                 , RULL(0x0701233A), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_05                               , RULL(0x0701233A), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_05                               , RULL(0x0801233A), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_06                                 , RULL(0x0701233B), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_06                               , RULL(0x0701233B), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_06                               , RULL(0x0801233B), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_07                                 , RULL(0x0701233C), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_07                               , RULL(0x0701233C), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_07                               , RULL(0x0801233C), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_08                                 , RULL(0x0701233D), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_08                               , RULL(0x0701233D), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_08                               , RULL(0x0801233D), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_09                                 , RULL(0x0701233E), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_09                               , RULL(0x0701233E), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_09                               , RULL(0x0801233E), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_10                                 , RULL(0x0701233F), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_10                               , RULL(0x0701233F), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_10                               , RULL(0x0801233F), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_11                                 , RULL(0x07012340), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_11                               , RULL(0x07012340), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_11                               , RULL(0x08012340), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_12                                 , RULL(0x07012341), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_12                               , RULL(0x07012341), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_12                               , RULL(0x08012341), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_13                                 , RULL(0x07012342), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_13                               , RULL(0x07012342), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_13                               , RULL(0x08012342), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_14                                 , RULL(0x07012343), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_14                               , RULL(0x07012343), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_14                               , RULL(0x08012343), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_15                                 , RULL(0x07012344), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_15                               , RULL(0x07012344), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_15                               , RULL(0x08012344), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_16                                 , RULL(0x07012345), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_16                               , RULL(0x07012345), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_16                               , RULL(0x08012345), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_17                                 , RULL(0x07012346), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_17                               , RULL(0x07012346), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_17                               , RULL(0x08012346), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_18                                 , RULL(0x07012347), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_18                               , RULL(0x07012347), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_18                               , RULL(0x08012347), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_19                                 , RULL(0x07012348), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_19                               , RULL(0x07012348), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_19                               , RULL(0x08012348), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_20                                 , RULL(0x07012349), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_20                               , RULL(0x07012349), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_20                               , RULL(0x08012349), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_21                                 , RULL(0x0701234A), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_21                               , RULL(0x0701234A), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_21                               , RULL(0x0801234A), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_22                                 , RULL(0x0701234B), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_22                               , RULL(0x0701234B), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_22                               , RULL(0x0801234B), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_23                                 , RULL(0x0701234C), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_23                               , RULL(0x0701234C), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_23                               , RULL(0x0801234C), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_24                                 , RULL(0x0701234D), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_24                               , RULL(0x0701234D), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_24                               , RULL(0x0801234D), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_25                                 , RULL(0x0701234E), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_25                               , RULL(0x0701234E), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_25                               , RULL(0x0801234E), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_26                                 , RULL(0x0701234F), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_26                               , RULL(0x0701234F), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_26                               , RULL(0x0801234F), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_27                                 , RULL(0x07012350), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_27                               , RULL(0x07012350), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_27                               , RULL(0x08012350), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_28                                 , RULL(0x07012351), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_28                               , RULL(0x07012351), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_28                               , RULL(0x08012351), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_29                                 , RULL(0x07012352), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_29                               , RULL(0x07012352), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_29                               , RULL(0x08012352), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_30                                 , RULL(0x07012353), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_30                               , RULL(0x07012353), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_30                               , RULL(0x08012353), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_INST_ARR1_31                                 , RULL(0x07012354), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_INST_ARR1_31                               , RULL(0x07012354), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_INST_ARR1_31                               , RULL(0x08012354), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_MODEQ                                        , RULL(0x070123A7), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_MODEQ                                      , RULL(0x070123A7), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_MODEQ                                      , RULL(0x080123A7), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_CCS_STATQ                                        , RULL(0x070123A6), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_CCS_STATQ                                      , RULL(0x070123A6), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_CCS_STATQ                                      , RULL(0x080123A6), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCA_CERR0                                               , RULL(0x07010A0E), SH_UNT_MCA      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_0_CERR0                                             , RULL(0x07010A0E), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_1_CERR0                                             , RULL(0x07010A4E), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_2_CERR0                                             , RULL(0x07010A8E), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_3_CERR0                                             , RULL(0x07010ACE), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_4_CERR0                                             , RULL(0x08010A0E), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_5_CERR0                                             , RULL(0x08010A4E), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_6_CERR0                                             , RULL(0x08010A8E), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_7_CERR0                                             , RULL(0x08010ACE), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( MCA_CERR1                                               , RULL(0x07010A0F), SH_UNT_MCA      , SH_ACS_SCOM_RO   );
+REG64( MCA_0_CERR1                                             , RULL(0x07010A0F), SH_UNT_MCA_0    , SH_ACS_SCOM_RO   );
+REG64( MCA_1_CERR1                                             , RULL(0x07010A4F), SH_UNT_MCA_1    , SH_ACS_SCOM_RO   );
+REG64( MCA_2_CERR1                                             , RULL(0x07010A8F), SH_UNT_MCA_2    , SH_ACS_SCOM_RO   );
+REG64( MCA_3_CERR1                                             , RULL(0x07010ACF), SH_UNT_MCA_3    , SH_ACS_SCOM_RO   );
+REG64( MCA_4_CERR1                                             , RULL(0x08010A0F), SH_UNT_MCA_4    , SH_ACS_SCOM_RO   );
+REG64( MCA_5_CERR1                                             , RULL(0x08010A4F), SH_UNT_MCA_5    , SH_ACS_SCOM_RO   );
+REG64( MCA_6_CERR1                                             , RULL(0x08010A8F), SH_UNT_MCA_6    , SH_ACS_SCOM_RO   );
+REG64( MCA_7_CERR1                                             , RULL(0x08010ACF), SH_UNT_MCA_7    , SH_ACS_SCOM_RO   );
+
+REG64( MCBIST_CLKRATIO                                         , RULL(0x070123F0), SH_UNT_MCBIST   , SH_ACS_SCOM_RO   );
+REG64( MCBIST_0_CLKRATIO                                       , RULL(0x070123F0), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RO   );
+REG64( MCBIST_1_CLKRATIO                                       , RULL(0x080123F0), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RO   );
+
+REG64( MCBIST_DBGCFG0Q                                         , RULL(0x070123E8), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_DBGCFG0Q                                       , RULL(0x070123E8), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_DBGCFG0Q                                       , RULL(0x080123E8), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_DBGCFG1Q                                         , RULL(0x070123E9), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_DBGCFG1Q                                       , RULL(0x070123E9), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_DBGCFG1Q                                       , RULL(0x080123E9), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_DBGCFG2Q                                         , RULL(0x070123EA), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_DBGCFG2Q                                       , RULL(0x070123EA), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_DBGCFG2Q                                       , RULL(0x080123EA), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_DBGCFG3Q                                         , RULL(0x070123EB), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_DBGCFG3Q                                       , RULL(0x070123EB), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_DBGCFG3Q                                       , RULL(0x080123EB), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCA_DBGR                                                , RULL(0x07010A0B), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_DBGR                                              , RULL(0x07010A0B), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_DBGR                                              , RULL(0x07010A4B), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_DBGR                                              , RULL(0x07010A8B), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_DBGR                                              , RULL(0x07010ACB), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_DBGR                                              , RULL(0x08010A0B), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_DBGR                                              , RULL(0x08010A4B), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_DBGR                                              , RULL(0x08010A8B), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_DBGR                                              , RULL(0x08010ACB), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DBG_INST1_COND_REG_1                              , RULL(0x070107C1), SH_UNT_MCA_3    , SH_ACS_SCOM      );
+REG64( MCA_7_DBG_INST1_COND_REG_1                              , RULL(0x080107C1), SH_UNT_MCA_7    , SH_ACS_SCOM      );
+
+REG64( MCA_3_DBG_INST1_COND_REG_2                              , RULL(0x070107C2), SH_UNT_MCA_3    , SH_ACS_SCOM      );
+REG64( MCA_7_DBG_INST1_COND_REG_2                              , RULL(0x080107C2), SH_UNT_MCA_7    , SH_ACS_SCOM      );
+
+REG64( MCA_3_DBG_INST1_COND_REG_3                              , RULL(0x070107C3), SH_UNT_MCA_3    , SH_ACS_SCOM      );
+REG64( MCA_7_DBG_INST1_COND_REG_3                              , RULL(0x080107C3), SH_UNT_MCA_7    , SH_ACS_SCOM      );
+
+REG64( MCA_3_DBG_INST2_COND_REG_1                              , RULL(0x070107C4), SH_UNT_MCA_3    , SH_ACS_SCOM      );
+REG64( MCA_7_DBG_INST2_COND_REG_1                              , RULL(0x080107C4), SH_UNT_MCA_7    , SH_ACS_SCOM      );
+
+REG64( MCA_3_DBG_INST2_COND_REG_2                              , RULL(0x070107C5), SH_UNT_MCA_3    , SH_ACS_SCOM      );
+REG64( MCA_7_DBG_INST2_COND_REG_2                              , RULL(0x080107C5), SH_UNT_MCA_7    , SH_ACS_SCOM      );
+
+REG64( MCA_3_DBG_INST2_COND_REG_3                              , RULL(0x070107C6), SH_UNT_MCA_3    , SH_ACS_SCOM      );
+REG64( MCA_7_DBG_INST2_COND_REG_3                              , RULL(0x080107C6), SH_UNT_MCA_7    , SH_ACS_SCOM      );
+
+REG64( MCA_3_DBG_MODE_REG                                      , RULL(0x070107C0), SH_UNT_MCA_3    , SH_ACS_SCOM      );
+REG64( MCA_7_DBG_MODE_REG                                      , RULL(0x080107C0), SH_UNT_MCA_7    , SH_ACS_SCOM      );
+
+REG64( MCA_3_DBG_TRACE_MODE_REG_2                              , RULL(0x070107CF), SH_UNT_MCA_3    , SH_ACS_SCOM      );
+REG64( MCA_7_DBG_TRACE_MODE_REG_2                              , RULL(0x080107CF), SH_UNT_MCA_7    , SH_ACS_SCOM      );
+
+REG64( MCA_3_DBG_TRACE_REG_0                                   , RULL(0x070107CD), SH_UNT_MCA_3    , SH_ACS_SCOM      );
+REG64( MCA_7_DBG_TRACE_REG_0                                   , RULL(0x080107CD), SH_UNT_MCA_7    , SH_ACS_SCOM      );
+
+REG64( MCA_3_DBG_TRACE_REG_1                                   , RULL(0x070107CE), SH_UNT_MCA_3    , SH_ACS_SCOM      );
+REG64( MCA_7_DBG_TRACE_REG_1                                   , RULL(0x080107CE), SH_UNT_MCA_7    , SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0                       , RULL(0x800040000701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_BIT_ENABLE_P0_ADR0                     , RULL(0x800040000701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_BIT_ENABLE_P0_ADR0                     , RULL(0x800040000801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1                       , RULL(0x800044000701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_BIT_ENABLE_P0_ADR1                     , RULL(0x800044000701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_BIT_ENABLE_P0_ADR1                     , RULL(0x800044000801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2                       , RULL(0x800048000701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_BIT_ENABLE_P0_ADR2                     , RULL(0x800048000701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_BIT_ENABLE_P0_ADR2                     , RULL(0x800048000801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3                       , RULL(0x80004C000701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_BIT_ENABLE_P0_ADR3                     , RULL(0x80004C000701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_BIT_ENABLE_P0_ADR3                     , RULL(0x80004C000801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_BIT_ENABLE_P1_ADR0                     , RULL(0x800040000701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_BIT_ENABLE_P1_ADR0                     , RULL(0x800040000801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_BIT_ENABLE_P1_ADR1                     , RULL(0x800044000701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_BIT_ENABLE_P1_ADR1                     , RULL(0x800044000801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_BIT_ENABLE_P1_ADR2                     , RULL(0x800048000701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_BIT_ENABLE_P1_ADR2                     , RULL(0x800048000801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_BIT_ENABLE_P1_ADR3                     , RULL(0x80004C000701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_BIT_ENABLE_P1_ADR3                     , RULL(0x80004C000801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_BIT_ENABLE_P2_ADR0                     , RULL(0x800040000701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_BIT_ENABLE_P2_ADR0                     , RULL(0x800040000801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_BIT_ENABLE_P2_ADR1                     , RULL(0x800044000701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_BIT_ENABLE_P2_ADR1                     , RULL(0x800044000801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_BIT_ENABLE_P2_ADR2                     , RULL(0x800048000701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_BIT_ENABLE_P2_ADR2                     , RULL(0x800048000801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_BIT_ENABLE_P2_ADR3                     , RULL(0x80004C000701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_BIT_ENABLE_P2_ADR3                     , RULL(0x80004C000801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_BIT_ENABLE_P3_ADR0                     , RULL(0x8000400007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_BIT_ENABLE_P3_ADR0                     , RULL(0x8000400008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_BIT_ENABLE_P3_ADR1                     , RULL(0x8000440007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_BIT_ENABLE_P3_ADR1                     , RULL(0x8000440008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_BIT_ENABLE_P3_ADR2                     , RULL(0x8000480007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_BIT_ENABLE_P3_ADR2                     , RULL(0x8000480008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_BIT_ENABLE_P3_ADR3                     , RULL(0x80004C0007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_BIT_ENABLE_P3_ADR3                     , RULL(0x80004C0008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0                   , RULL(0x800080380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0                 , RULL(0x800080380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0                 , RULL(0x800080380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1                   , RULL(0x800084380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1                 , RULL(0x800084380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1                 , RULL(0x800084380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_ADR_DCD_CONTROL_P1_ADR32S0                 , RULL(0x800080380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_ADR_DCD_CONTROL_P1_ADR32S0                 , RULL(0x800080380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_ADR_DCD_CONTROL_P1_ADR32S1                 , RULL(0x800084380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_ADR_DCD_CONTROL_P1_ADR32S1                 , RULL(0x800084380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_ADR_DCD_CONTROL_P2_ADR32S0                 , RULL(0x800080380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_ADR_DCD_CONTROL_P2_ADR32S0                 , RULL(0x800080380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_ADR_DCD_CONTROL_P2_ADR32S1                 , RULL(0x800084380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_ADR_DCD_CONTROL_P2_ADR32S1                 , RULL(0x800084380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_ADR_DCD_CONTROL_P3_ADR32S0                 , RULL(0x8000803807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_ADR_DCD_CONTROL_P3_ADR32S0                 , RULL(0x8000803808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_ADR_DCD_CONTROL_P3_ADR32S1                 , RULL(0x8000843807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_ADR_DCD_CONTROL_P3_ADR32S1                 , RULL(0x8000843808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_ADR_DELAY0_P0_ADR0                           , RULL(0x800040040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY0_P0_ADR0                         , RULL(0x800040040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY0_P0_ADR0                         , RULL(0x800040040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY0_P0_ADR1                           , RULL(0x800044040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY0_P0_ADR1                         , RULL(0x800044040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY0_P0_ADR1                         , RULL(0x800044040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY0_P0_ADR2                           , RULL(0x800048040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY0_P0_ADR2                         , RULL(0x800048040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY0_P0_ADR2                         , RULL(0x800048040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY0_P0_ADR3                           , RULL(0x80004C040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY0_P0_ADR3                         , RULL(0x80004C040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY0_P0_ADR3                         , RULL(0x80004C040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY0_P1_ADR0                         , RULL(0x800040040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY0_P1_ADR0                         , RULL(0x800040040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY0_P1_ADR1                         , RULL(0x800044040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY0_P1_ADR1                         , RULL(0x800044040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY0_P1_ADR2                         , RULL(0x800048040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY0_P1_ADR2                         , RULL(0x800048040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY0_P1_ADR3                         , RULL(0x80004C040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY0_P1_ADR3                         , RULL(0x80004C040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY0_P2_ADR0                         , RULL(0x800040040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY0_P2_ADR0                         , RULL(0x800040040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY0_P2_ADR1                         , RULL(0x800044040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY0_P2_ADR1                         , RULL(0x800044040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY0_P2_ADR2                         , RULL(0x800048040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY0_P2_ADR2                         , RULL(0x800048040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY0_P2_ADR3                         , RULL(0x80004C040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY0_P2_ADR3                         , RULL(0x80004C040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY0_P3_ADR0                         , RULL(0x8000400407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY0_P3_ADR0                         , RULL(0x8000400408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY0_P3_ADR1                         , RULL(0x8000440407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY0_P3_ADR1                         , RULL(0x8000440408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY0_P3_ADR2                         , RULL(0x8000480407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY0_P3_ADR2                         , RULL(0x8000480408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY0_P3_ADR3                         , RULL(0x80004C0407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY0_P3_ADR3                         , RULL(0x80004C0408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY1_P0_ADR0                           , RULL(0x800040050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY1_P0_ADR0                         , RULL(0x800040050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY1_P0_ADR0                         , RULL(0x800040050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY1_P0_ADR1                           , RULL(0x800044050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY1_P0_ADR1                         , RULL(0x800044050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY1_P0_ADR1                         , RULL(0x800044050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY1_P0_ADR2                           , RULL(0x800048050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY1_P0_ADR2                         , RULL(0x800048050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY1_P0_ADR2                         , RULL(0x800048050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY1_P0_ADR3                           , RULL(0x80004C050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY1_P0_ADR3                         , RULL(0x80004C050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY1_P0_ADR3                         , RULL(0x80004C050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY1_P1_ADR0                         , RULL(0x800040050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY1_P1_ADR0                         , RULL(0x800040050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY1_P1_ADR1                         , RULL(0x800044050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY1_P1_ADR1                         , RULL(0x800044050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY1_P1_ADR2                         , RULL(0x800048050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY1_P1_ADR2                         , RULL(0x800048050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY1_P1_ADR3                         , RULL(0x80004C050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY1_P1_ADR3                         , RULL(0x80004C050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY1_P2_ADR0                         , RULL(0x800040050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY1_P2_ADR0                         , RULL(0x800040050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY1_P2_ADR1                         , RULL(0x800044050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY1_P2_ADR1                         , RULL(0x800044050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY1_P2_ADR2                         , RULL(0x800048050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY1_P2_ADR2                         , RULL(0x800048050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY1_P2_ADR3                         , RULL(0x80004C050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY1_P2_ADR3                         , RULL(0x80004C050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY1_P3_ADR0                         , RULL(0x8000400507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY1_P3_ADR0                         , RULL(0x8000400508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY1_P3_ADR1                         , RULL(0x8000440507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY1_P3_ADR1                         , RULL(0x8000440508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY1_P3_ADR2                         , RULL(0x8000480507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY1_P3_ADR2                         , RULL(0x8000480508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY1_P3_ADR3                         , RULL(0x80004C0507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY1_P3_ADR3                         , RULL(0x80004C0508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY2_P0_ADR0                           , RULL(0x800040060701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY2_P0_ADR0                         , RULL(0x800040060701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY2_P0_ADR0                         , RULL(0x800040060801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY2_P0_ADR1                           , RULL(0x800044060701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY2_P0_ADR1                         , RULL(0x800044060701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY2_P0_ADR1                         , RULL(0x800044060801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY2_P0_ADR2                           , RULL(0x800048060701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY2_P0_ADR2                         , RULL(0x800048060701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY2_P0_ADR2                         , RULL(0x800048060801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY2_P0_ADR3                           , RULL(0x80004C060701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY2_P0_ADR3                         , RULL(0x80004C060701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY2_P0_ADR3                         , RULL(0x80004C060801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY2_P1_ADR0                         , RULL(0x800040060701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY2_P1_ADR0                         , RULL(0x800040060801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY2_P1_ADR1                         , RULL(0x800044060701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY2_P1_ADR1                         , RULL(0x800044060801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY2_P1_ADR2                         , RULL(0x800048060701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY2_P1_ADR2                         , RULL(0x800048060801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY2_P1_ADR3                         , RULL(0x80004C060701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY2_P1_ADR3                         , RULL(0x80004C060801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY2_P2_ADR0                         , RULL(0x800040060701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY2_P2_ADR0                         , RULL(0x800040060801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY2_P2_ADR1                         , RULL(0x800044060701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY2_P2_ADR1                         , RULL(0x800044060801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY2_P2_ADR2                         , RULL(0x800048060701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY2_P2_ADR2                         , RULL(0x800048060801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY2_P2_ADR3                         , RULL(0x80004C060701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY2_P2_ADR3                         , RULL(0x80004C060801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY2_P3_ADR0                         , RULL(0x8000400607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY2_P3_ADR0                         , RULL(0x8000400608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY2_P3_ADR1                         , RULL(0x8000440607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY2_P3_ADR1                         , RULL(0x8000440608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY2_P3_ADR2                         , RULL(0x8000480607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY2_P3_ADR2                         , RULL(0x8000480608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY2_P3_ADR3                         , RULL(0x80004C0607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY2_P3_ADR3                         , RULL(0x80004C0608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY3_P0_ADR0                           , RULL(0x800040070701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY3_P0_ADR0                         , RULL(0x800040070701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY3_P0_ADR0                         , RULL(0x800040070801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY3_P0_ADR1                           , RULL(0x800044070701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY3_P0_ADR1                         , RULL(0x800044070701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY3_P0_ADR1                         , RULL(0x800044070801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY3_P0_ADR2                           , RULL(0x800048070701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY3_P0_ADR2                         , RULL(0x800048070701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY3_P0_ADR2                         , RULL(0x800048070801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY3_P0_ADR3                           , RULL(0x80004C070701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY3_P0_ADR3                         , RULL(0x80004C070701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY3_P0_ADR3                         , RULL(0x80004C070801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY3_P1_ADR0                         , RULL(0x800040070701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY3_P1_ADR0                         , RULL(0x800040070801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY3_P1_ADR1                         , RULL(0x800044070701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY3_P1_ADR1                         , RULL(0x800044070801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY3_P1_ADR2                         , RULL(0x800048070701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY3_P1_ADR2                         , RULL(0x800048070801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY3_P1_ADR3                         , RULL(0x80004C070701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY3_P1_ADR3                         , RULL(0x80004C070801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY3_P2_ADR0                         , RULL(0x800040070701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY3_P2_ADR0                         , RULL(0x800040070801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY3_P2_ADR1                         , RULL(0x800044070701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY3_P2_ADR1                         , RULL(0x800044070801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY3_P2_ADR2                         , RULL(0x800048070701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY3_P2_ADR2                         , RULL(0x800048070801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY3_P2_ADR3                         , RULL(0x80004C070701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY3_P2_ADR3                         , RULL(0x80004C070801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY3_P3_ADR0                         , RULL(0x8000400707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY3_P3_ADR0                         , RULL(0x8000400708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY3_P3_ADR1                         , RULL(0x8000440707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY3_P3_ADR1                         , RULL(0x8000440708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY3_P3_ADR2                         , RULL(0x8000480707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY3_P3_ADR2                         , RULL(0x8000480708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY3_P3_ADR3                         , RULL(0x80004C0707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY3_P3_ADR3                         , RULL(0x80004C0708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY4_P0_ADR0                           , RULL(0x800040080701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY4_P0_ADR0                         , RULL(0x800040080701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY4_P0_ADR0                         , RULL(0x800040080801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY4_P0_ADR1                           , RULL(0x800044080701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY4_P0_ADR1                         , RULL(0x800044080701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY4_P0_ADR1                         , RULL(0x800044080801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY4_P0_ADR2                           , RULL(0x800048080701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY4_P0_ADR2                         , RULL(0x800048080701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY4_P0_ADR2                         , RULL(0x800048080801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY4_P0_ADR3                           , RULL(0x80004C080701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY4_P0_ADR3                         , RULL(0x80004C080701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY4_P0_ADR3                         , RULL(0x80004C080801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY4_P1_ADR0                         , RULL(0x800040080701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY4_P1_ADR0                         , RULL(0x800040080801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY4_P1_ADR1                         , RULL(0x800044080701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY4_P1_ADR1                         , RULL(0x800044080801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY4_P1_ADR2                         , RULL(0x800048080701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY4_P1_ADR2                         , RULL(0x800048080801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY4_P1_ADR3                         , RULL(0x80004C080701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY4_P1_ADR3                         , RULL(0x80004C080801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY4_P2_ADR0                         , RULL(0x800040080701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY4_P2_ADR0                         , RULL(0x800040080801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY4_P2_ADR1                         , RULL(0x800044080701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY4_P2_ADR1                         , RULL(0x800044080801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY4_P2_ADR2                         , RULL(0x800048080701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY4_P2_ADR2                         , RULL(0x800048080801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY4_P2_ADR3                         , RULL(0x80004C080701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY4_P2_ADR3                         , RULL(0x80004C080801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY4_P3_ADR0                         , RULL(0x8000400807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY4_P3_ADR0                         , RULL(0x8000400808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY4_P3_ADR1                         , RULL(0x8000440807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY4_P3_ADR1                         , RULL(0x8000440808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY4_P3_ADR2                         , RULL(0x8000480807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY4_P3_ADR2                         , RULL(0x8000480808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY4_P3_ADR3                         , RULL(0x80004C0807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY4_P3_ADR3                         , RULL(0x80004C0808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY5_P0_ADR0                           , RULL(0x800040090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY5_P0_ADR0                         , RULL(0x800040090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY5_P0_ADR0                         , RULL(0x800040090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY5_P0_ADR1                           , RULL(0x800044090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY5_P0_ADR1                         , RULL(0x800044090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY5_P0_ADR1                         , RULL(0x800044090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY5_P0_ADR2                           , RULL(0x800048090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY5_P0_ADR2                         , RULL(0x800048090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY5_P0_ADR2                         , RULL(0x800048090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY5_P0_ADR3                           , RULL(0x80004C090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY5_P0_ADR3                         , RULL(0x80004C090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY5_P0_ADR3                         , RULL(0x80004C090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY5_P1_ADR0                         , RULL(0x800040090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY5_P1_ADR0                         , RULL(0x800040090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY5_P1_ADR1                         , RULL(0x800044090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY5_P1_ADR1                         , RULL(0x800044090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY5_P1_ADR2                         , RULL(0x800048090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY5_P1_ADR2                         , RULL(0x800048090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY5_P1_ADR3                         , RULL(0x80004C090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY5_P1_ADR3                         , RULL(0x80004C090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY5_P2_ADR0                         , RULL(0x800040090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY5_P2_ADR0                         , RULL(0x800040090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY5_P2_ADR1                         , RULL(0x800044090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY5_P2_ADR1                         , RULL(0x800044090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY5_P2_ADR2                         , RULL(0x800048090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY5_P2_ADR2                         , RULL(0x800048090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY5_P2_ADR3                         , RULL(0x80004C090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY5_P2_ADR3                         , RULL(0x80004C090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY5_P3_ADR0                         , RULL(0x8000400907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY5_P3_ADR0                         , RULL(0x8000400908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY5_P3_ADR1                         , RULL(0x8000440907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY5_P3_ADR1                         , RULL(0x8000440908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY5_P3_ADR2                         , RULL(0x8000480907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY5_P3_ADR2                         , RULL(0x8000480908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY5_P3_ADR3                         , RULL(0x80004C0907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY5_P3_ADR3                         , RULL(0x80004C0908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY6_P0_ADR0                           , RULL(0x8000400A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY6_P0_ADR0                         , RULL(0x8000400A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY6_P0_ADR0                         , RULL(0x8000400A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY6_P0_ADR1                           , RULL(0x8000440A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY6_P0_ADR1                         , RULL(0x8000440A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY6_P0_ADR1                         , RULL(0x8000440A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY6_P0_ADR2                           , RULL(0x8000480A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY6_P0_ADR2                         , RULL(0x8000480A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY6_P0_ADR2                         , RULL(0x8000480A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY6_P0_ADR3                           , RULL(0x80004C0A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY6_P0_ADR3                         , RULL(0x80004C0A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY6_P0_ADR3                         , RULL(0x80004C0A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY6_P1_ADR0                         , RULL(0x8000400A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY6_P1_ADR0                         , RULL(0x8000400A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY6_P1_ADR1                         , RULL(0x8000440A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY6_P1_ADR1                         , RULL(0x8000440A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY6_P1_ADR2                         , RULL(0x8000480A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY6_P1_ADR2                         , RULL(0x8000480A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY6_P1_ADR3                         , RULL(0x80004C0A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY6_P1_ADR3                         , RULL(0x80004C0A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY6_P2_ADR0                         , RULL(0x8000400A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY6_P2_ADR0                         , RULL(0x8000400A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY6_P2_ADR1                         , RULL(0x8000440A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY6_P2_ADR1                         , RULL(0x8000440A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY6_P2_ADR2                         , RULL(0x8000480A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY6_P2_ADR2                         , RULL(0x8000480A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY6_P2_ADR3                         , RULL(0x80004C0A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY6_P2_ADR3                         , RULL(0x80004C0A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY6_P3_ADR0                         , RULL(0x8000400A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY6_P3_ADR0                         , RULL(0x8000400A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY6_P3_ADR1                         , RULL(0x8000440A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY6_P3_ADR1                         , RULL(0x8000440A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY6_P3_ADR2                         , RULL(0x8000480A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY6_P3_ADR2                         , RULL(0x8000480A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY6_P3_ADR3                         , RULL(0x80004C0A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY6_P3_ADR3                         , RULL(0x80004C0A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY7_P0_ADR0                           , RULL(0x8000400B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY7_P0_ADR0                         , RULL(0x8000400B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY7_P0_ADR0                         , RULL(0x8000400B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY7_P0_ADR1                           , RULL(0x8000440B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY7_P0_ADR1                         , RULL(0x8000440B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY7_P0_ADR1                         , RULL(0x8000440B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY7_P0_ADR2                           , RULL(0x8000480B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY7_P0_ADR2                         , RULL(0x8000480B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY7_P0_ADR2                         , RULL(0x8000480B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DELAY7_P0_ADR3                           , RULL(0x80004C0B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DELAY7_P0_ADR3                         , RULL(0x80004C0B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DELAY7_P0_ADR3                         , RULL(0x80004C0B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY7_P1_ADR0                         , RULL(0x8000400B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY7_P1_ADR0                         , RULL(0x8000400B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY7_P1_ADR1                         , RULL(0x8000440B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY7_P1_ADR1                         , RULL(0x8000440B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY7_P1_ADR2                         , RULL(0x8000480B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY7_P1_ADR2                         , RULL(0x8000480B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DELAY7_P1_ADR3                         , RULL(0x80004C0B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DELAY7_P1_ADR3                         , RULL(0x80004C0B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY7_P2_ADR0                         , RULL(0x8000400B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY7_P2_ADR0                         , RULL(0x8000400B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY7_P2_ADR1                         , RULL(0x8000440B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY7_P2_ADR1                         , RULL(0x8000440B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY7_P2_ADR2                         , RULL(0x8000480B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY7_P2_ADR2                         , RULL(0x8000480B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DELAY7_P2_ADR3                         , RULL(0x80004C0B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DELAY7_P2_ADR3                         , RULL(0x80004C0B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY7_P3_ADR0                         , RULL(0x8000400B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY7_P3_ADR0                         , RULL(0x8000400B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY7_P3_ADR1                         , RULL(0x8000440B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY7_P3_ADR1                         , RULL(0x8000440B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY7_P3_ADR2                         , RULL(0x8000480B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY7_P3_ADR2                         , RULL(0x8000480B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DELAY7_P3_ADR3                         , RULL(0x80004C0B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DELAY7_P3_ADR3                         , RULL(0x80004C0B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0          , RULL(0x8000400C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0        , RULL(0x8000400C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0        , RULL(0x8000400C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1          , RULL(0x8000440C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1        , RULL(0x8000440C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1        , RULL(0x8000440C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2          , RULL(0x8000480C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2        , RULL(0x8000480C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2        , RULL(0x8000480C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3          , RULL(0x80004C0C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3        , RULL(0x80004C0C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3        , RULL(0x80004C0C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR0        , RULL(0x8000400C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR0        , RULL(0x8000400C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR1        , RULL(0x8000440C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR1        , RULL(0x8000440C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR2        , RULL(0x8000480C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR2        , RULL(0x8000480C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR3        , RULL(0x80004C0C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P1_ADR3        , RULL(0x80004C0C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR0        , RULL(0x8000400C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR0        , RULL(0x8000400C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR1        , RULL(0x8000440C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR1        , RULL(0x8000440C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR2        , RULL(0x8000480C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR2        , RULL(0x8000480C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR3        , RULL(0x80004C0C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P2_ADR3        , RULL(0x80004C0C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR0        , RULL(0x8000400C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR0        , RULL(0x8000400C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR1        , RULL(0x8000440C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR1        , RULL(0x8000440C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR2        , RULL(0x8000480C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR2        , RULL(0x8000480C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR3        , RULL(0x80004C0C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P3_ADR3        , RULL(0x80004C0C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0                  , RULL(0x800040010701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0                , RULL(0x800040010701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0                , RULL(0x800040010801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1                  , RULL(0x800044010701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1                , RULL(0x800044010701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1                , RULL(0x800044010801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2                  , RULL(0x800048010701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2                , RULL(0x800048010701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2                , RULL(0x800048010801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3                  , RULL(0x80004C010701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3                , RULL(0x80004C010701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3                , RULL(0x80004C010801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0                , RULL(0x800040010701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0                , RULL(0x800040010801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR1                , RULL(0x800044010701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR1                , RULL(0x800044010801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2                , RULL(0x800048010701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2                , RULL(0x800048010801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3                , RULL(0x80004C010701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3                , RULL(0x80004C010801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR0                , RULL(0x800040010701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR0                , RULL(0x800040010801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR1                , RULL(0x800044010701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR1                , RULL(0x800044010801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR2                , RULL(0x800048010701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR2                , RULL(0x800048010801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR3                , RULL(0x80004C010701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DIFFPAIR_ENABLE_P2_ADR3                , RULL(0x80004C010801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR0                , RULL(0x8000400107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR0                , RULL(0x8000400108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR1                , RULL(0x8000440107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR1                , RULL(0x8000440108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR2                , RULL(0x8000480107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR2                , RULL(0x8000480108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR3                , RULL(0x80004C0107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DIFFPAIR_ENABLE_P3_ADR3                , RULL(0x80004C0108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0                      , RULL(0x8000803A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0                    , RULL(0x8000803A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0                    , RULL(0x8000803A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1                      , RULL(0x8000843A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1                    , RULL(0x8000843A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1                    , RULL(0x8000843A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_CNTL_P1_ADR32S0                    , RULL(0x8000803A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_ADR_DLL_CNTL_P1_ADR32S0                    , RULL(0x8000803A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_CNTL_P1_ADR32S1                    , RULL(0x8000843A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_ADR_DLL_CNTL_P1_ADR32S1                    , RULL(0x8000843A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_CNTL_P2_ADR32S0                    , RULL(0x8000803A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_ADR_DLL_CNTL_P2_ADR32S0                    , RULL(0x8000803A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_CNTL_P2_ADR32S1                    , RULL(0x8000843A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_ADR_DLL_CNTL_P2_ADR32S1                    , RULL(0x8000843A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_CNTL_P3_ADR32S0                    , RULL(0x8000803A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_ADR_DLL_CNTL_P3_ADR32S0                    , RULL(0x8000803A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_CNTL_P3_ADR32S1                    , RULL(0x8000843A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_ADR_DLL_CNTL_P3_ADR32S1                    , RULL(0x8000843A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0                 , RULL(0x8000803B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0               , RULL(0x8000803B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0               , RULL(0x8000803B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1                 , RULL(0x8000843B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1               , RULL(0x8000843B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1               , RULL(0x8000843B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_DAC_LOWER_P1_ADR32S0               , RULL(0x8000803B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_DAC_LOWER_P1_ADR32S0               , RULL(0x8000803B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_DAC_LOWER_P1_ADR32S1               , RULL(0x8000843B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_DAC_LOWER_P1_ADR32S1               , RULL(0x8000843B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_DAC_LOWER_P2_ADR32S0               , RULL(0x8000803B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_DAC_LOWER_P2_ADR32S0               , RULL(0x8000803B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_DAC_LOWER_P2_ADR32S1               , RULL(0x8000843B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_DAC_LOWER_P2_ADR32S1               , RULL(0x8000843B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_DAC_LOWER_P3_ADR32S0               , RULL(0x8000803B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_DAC_LOWER_P3_ADR32S0               , RULL(0x8000803B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_DAC_LOWER_P3_ADR32S1               , RULL(0x8000843B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_DAC_LOWER_P3_ADR32S1               , RULL(0x8000843B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0                 , RULL(0x8000803C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0               , RULL(0x8000803C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0               , RULL(0x8000803C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1                 , RULL(0x8000843C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1               , RULL(0x8000843C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1               , RULL(0x8000843C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_DAC_UPPER_P1_ADR32S0               , RULL(0x8000803C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_DAC_UPPER_P1_ADR32S0               , RULL(0x8000803C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_DAC_UPPER_P1_ADR32S1               , RULL(0x8000843C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_DAC_UPPER_P1_ADR32S1               , RULL(0x8000843C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_DAC_UPPER_P2_ADR32S0               , RULL(0x8000803C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_DAC_UPPER_P2_ADR32S0               , RULL(0x8000803C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_DAC_UPPER_P2_ADR32S1               , RULL(0x8000843C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_DAC_UPPER_P2_ADR32S1               , RULL(0x8000843C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_DAC_UPPER_P3_ADR32S0               , RULL(0x8000803C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_DAC_UPPER_P3_ADR32S0               , RULL(0x8000803C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_DAC_UPPER_P3_ADR32S1               , RULL(0x8000843C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_DAC_UPPER_P3_ADR32S1               , RULL(0x8000843C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S0                     , RULL(0x8000802D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S0                   , RULL(0x8000802D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S0                   , RULL(0x8000802D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S1                     , RULL(0x8000842D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S1                   , RULL(0x8000842D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S1                   , RULL(0x8000842D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_EXTRA_P1_ADR32S0                   , RULL(0x8000802D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_EXTRA_P1_ADR32S0                   , RULL(0x8000802D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_EXTRA_P1_ADR32S1                   , RULL(0x8000842D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_EXTRA_P1_ADR32S1                   , RULL(0x8000842D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_EXTRA_P2_ADR32S0                   , RULL(0x8000802D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_EXTRA_P2_ADR32S0                   , RULL(0x8000802D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_EXTRA_P2_ADR32S1                   , RULL(0x8000842D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_EXTRA_P2_ADR32S1                   , RULL(0x8000842D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_EXTRA_P3_ADR32S0                   , RULL(0x8000802D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_EXTRA_P3_ADR32S0                   , RULL(0x8000802D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_EXTRA_P3_ADR32S1                   , RULL(0x8000842D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_EXTRA_P3_ADR32S1                   , RULL(0x8000842D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0          , RULL(0x8000802E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0        , RULL(0x8000802E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0        , RULL(0x8000802E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S1          , RULL(0x8000842E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S1        , RULL(0x8000842E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S1        , RULL(0x8000842E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P1_ADR32S0        , RULL(0x8000802E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P1_ADR32S0        , RULL(0x8000802E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P1_ADR32S1        , RULL(0x8000842E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P1_ADR32S1        , RULL(0x8000842E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P2_ADR32S0        , RULL(0x8000802E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P2_ADR32S0        , RULL(0x8000802E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P2_ADR32S1        , RULL(0x8000842E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P2_ADR32S1        , RULL(0x8000842E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P3_ADR32S0        , RULL(0x8000802E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P3_ADR32S0        , RULL(0x8000802E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P3_ADR32S1        , RULL(0x8000842E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P3_ADR32S1        , RULL(0x8000842E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S0          , RULL(0x8000802F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S0        , RULL(0x8000802F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S0        , RULL(0x8000802F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1          , RULL(0x8000842F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1        , RULL(0x8000842F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1        , RULL(0x8000842F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P1_ADR32S0        , RULL(0x8000802F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P1_ADR32S0        , RULL(0x8000802F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P1_ADR32S1        , RULL(0x8000842F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P1_ADR32S1        , RULL(0x8000842F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P2_ADR32S0        , RULL(0x8000802F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P2_ADR32S0        , RULL(0x8000802F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P2_ADR32S1        , RULL(0x8000842F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P2_ADR32S1        , RULL(0x8000842F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P3_ADR32S0        , RULL(0x8000802F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P3_ADR32S0        , RULL(0x8000802F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P3_ADR32S1        , RULL(0x8000842F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P3_ADR32S1        , RULL(0x8000842F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0                , RULL(0x800080300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0              , RULL(0x800080300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0              , RULL(0x800080300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1                , RULL(0x800084300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1              , RULL(0x800084300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1              , RULL(0x800084300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_SW_CONTROL_P1_ADR32S0              , RULL(0x800080300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_ADR_DLL_SW_CONTROL_P1_ADR32S0              , RULL(0x800080300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_SW_CONTROL_P1_ADR32S1              , RULL(0x800084300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_ADR_DLL_SW_CONTROL_P1_ADR32S1              , RULL(0x800084300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_SW_CONTROL_P2_ADR32S0              , RULL(0x800080300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_ADR_DLL_SW_CONTROL_P2_ADR32S0              , RULL(0x800080300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_SW_CONTROL_P2_ADR32S1              , RULL(0x800084300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_ADR_DLL_SW_CONTROL_P2_ADR32S1              , RULL(0x800084300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_SW_CONTROL_P3_ADR32S0              , RULL(0x8000803007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_ADR_DLL_SW_CONTROL_P3_ADR32S0              , RULL(0x8000803008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_SW_CONTROL_P3_ADR32S1              , RULL(0x8000843007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_ADR_DLL_SW_CONTROL_P3_ADR32S1              , RULL(0x8000843008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0               , RULL(0x8000803E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0             , RULL(0x8000803E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0             , RULL(0x8000803E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1               , RULL(0x8000843E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1             , RULL(0x8000843E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1             , RULL(0x8000843E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_VREG_COARSE_P1_ADR32S0             , RULL(0x8000803E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_VREG_COARSE_P1_ADR32S0             , RULL(0x8000803E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_VREG_COARSE_P1_ADR32S1             , RULL(0x8000843E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_VREG_COARSE_P1_ADR32S1             , RULL(0x8000843E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_VREG_COARSE_P2_ADR32S0             , RULL(0x8000803E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_VREG_COARSE_P2_ADR32S0             , RULL(0x8000803E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_VREG_COARSE_P2_ADR32S1             , RULL(0x8000843E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_VREG_COARSE_P2_ADR32S1             , RULL(0x8000843E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_VREG_COARSE_P3_ADR32S0             , RULL(0x8000803E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_VREG_COARSE_P3_ADR32S0             , RULL(0x8000803E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_VREG_COARSE_P3_ADR32S1             , RULL(0x8000843E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_VREG_COARSE_P3_ADR32S1             , RULL(0x8000843E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0             , RULL(0x800080310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0           , RULL(0x800080310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0           , RULL(0x800080310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1             , RULL(0x800084310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1           , RULL(0x800084310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1           , RULL(0x800084310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_VREG_CONFIG_1_P1_ADR32S0           , RULL(0x800080310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_VREG_CONFIG_1_P1_ADR32S0           , RULL(0x800080310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_VREG_CONFIG_1_P1_ADR32S1           , RULL(0x800084310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_VREG_CONFIG_1_P1_ADR32S1           , RULL(0x800084310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_VREG_CONFIG_1_P2_ADR32S0           , RULL(0x800080310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_VREG_CONFIG_1_P2_ADR32S0           , RULL(0x800080310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_VREG_CONFIG_1_P2_ADR32S1           , RULL(0x800084310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_VREG_CONFIG_1_P2_ADR32S1           , RULL(0x800084310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_VREG_CONFIG_1_P3_ADR32S0           , RULL(0x8000803107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_VREG_CONFIG_1_P3_ADR32S0           , RULL(0x8000803108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_VREG_CONFIG_1_P3_ADR32S1           , RULL(0x8000843107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_VREG_CONFIG_1_P3_ADR32S1           , RULL(0x8000843108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0              , RULL(0x8000803D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0            , RULL(0x8000803D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0            , RULL(0x8000803D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1              , RULL(0x8000843D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1            , RULL(0x8000843D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1            , RULL(0x8000843D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_VREG_CONTROL_P1_ADR32S0            , RULL(0x8000803D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_VREG_CONTROL_P1_ADR32S0            , RULL(0x8000803D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_DLL_VREG_CONTROL_P1_ADR32S1            , RULL(0x8000843D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_DLL_VREG_CONTROL_P1_ADR32S1            , RULL(0x8000843D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_VREG_CONTROL_P2_ADR32S0            , RULL(0x8000803D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_VREG_CONTROL_P2_ADR32S0            , RULL(0x8000803D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_DLL_VREG_CONTROL_P2_ADR32S1            , RULL(0x8000843D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_DLL_VREG_CONTROL_P2_ADR32S1            , RULL(0x8000843D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_VREG_CONTROL_P3_ADR32S0            , RULL(0x8000803D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_VREG_CONTROL_P3_ADR32S0            , RULL(0x8000803D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_DLL_VREG_CONTROL_P3_ADR32S1            , RULL(0x8000843D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_DLL_VREG_CONTROL_P3_ADR32S1            , RULL(0x8000843D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0             , RULL(0x800040200701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0           , RULL(0x800040200701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0           , RULL(0x800040200801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1             , RULL(0x800044200701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1           , RULL(0x800044200701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1           , RULL(0x800044200801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2             , RULL(0x800048200701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2           , RULL(0x800048200701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2           , RULL(0x800048200801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3             , RULL(0x80004C200701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3           , RULL(0x80004C200701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3           , RULL(0x80004C200801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0           , RULL(0x800040200701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0           , RULL(0x800040200801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1           , RULL(0x800044200701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1           , RULL(0x800044200801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2           , RULL(0x800048200701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2           , RULL(0x800048200801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3           , RULL(0x80004C200701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3           , RULL(0x80004C200801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR0           , RULL(0x800040200701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR0           , RULL(0x800040200801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR1           , RULL(0x800044200701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR1           , RULL(0x800044200801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR2           , RULL(0x800048200701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR2           , RULL(0x800048200801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR3           , RULL(0x80004C200701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P2_ADR3           , RULL(0x80004C200801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR0           , RULL(0x8000402007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR0           , RULL(0x8000402008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR1           , RULL(0x8000442007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR1           , RULL(0x8000442008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR2           , RULL(0x8000482007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR2           , RULL(0x8000482008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR3           , RULL(0x80004C2007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P3_ADR3           , RULL(0x80004C2008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0             , RULL(0x800040210701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0           , RULL(0x800040210701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0           , RULL(0x800040210801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1             , RULL(0x800044210701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1           , RULL(0x800044210701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1           , RULL(0x800044210801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2             , RULL(0x800048210701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2           , RULL(0x800048210701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2           , RULL(0x800048210801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3             , RULL(0x80004C210701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3           , RULL(0x80004C210701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3           , RULL(0x80004C210801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0           , RULL(0x800040210701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0           , RULL(0x800040210801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1           , RULL(0x800044210701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1           , RULL(0x800044210801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2           , RULL(0x800048210701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2           , RULL(0x800048210801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3           , RULL(0x80004C210701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3           , RULL(0x80004C210801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR0           , RULL(0x800040210701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR0           , RULL(0x800040210801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR1           , RULL(0x800044210701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR1           , RULL(0x800044210801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR2           , RULL(0x800048210701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR2           , RULL(0x800048210801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR3           , RULL(0x80004C210701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P2_ADR3           , RULL(0x80004C210801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR0           , RULL(0x8000402107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR0           , RULL(0x8000402108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR1           , RULL(0x8000442107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR1           , RULL(0x8000442108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR2           , RULL(0x8000482107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR2           , RULL(0x8000482108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR3           , RULL(0x80004C2107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P3_ADR3           , RULL(0x80004C2108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0           , RULL(0x8000402A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0         , RULL(0x8000402A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0         , RULL(0x8000402A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1           , RULL(0x8000442A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1         , RULL(0x8000442A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1         , RULL(0x8000442A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2           , RULL(0x8000482A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2         , RULL(0x8000482A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2         , RULL(0x8000482A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3           , RULL(0x80004C2A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3         , RULL(0x80004C2A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3         , RULL(0x80004C2A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0         , RULL(0x8000402A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0         , RULL(0x8000402A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1         , RULL(0x8000442A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1         , RULL(0x8000442A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2         , RULL(0x8000482A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2         , RULL(0x8000482A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3         , RULL(0x80004C2A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3         , RULL(0x80004C2A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P2_ADR0         , RULL(0x8000402A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P2_ADR0         , RULL(0x8000402A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P2_ADR1         , RULL(0x8000442A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P2_ADR1         , RULL(0x8000442A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P2_ADR2         , RULL(0x8000482A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P2_ADR2         , RULL(0x8000482A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P2_ADR3         , RULL(0x80004C2A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P2_ADR3         , RULL(0x80004C2A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P3_ADR0         , RULL(0x8000402A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P3_ADR0         , RULL(0x8000402A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P3_ADR1         , RULL(0x8000442A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P3_ADR1         , RULL(0x8000442A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P3_ADR2         , RULL(0x8000482A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P3_ADR2         , RULL(0x8000482A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P3_ADR3         , RULL(0x80004C2A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P3_ADR3         , RULL(0x80004C2A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0           , RULL(0x8000402B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0         , RULL(0x8000402B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0         , RULL(0x8000402B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1           , RULL(0x8000442B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1         , RULL(0x8000442B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1         , RULL(0x8000442B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2           , RULL(0x8000482B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2         , RULL(0x8000482B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2         , RULL(0x8000482B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3           , RULL(0x80004C2B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3         , RULL(0x80004C2B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3         , RULL(0x80004C2B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0         , RULL(0x8000402B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0         , RULL(0x8000402B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1         , RULL(0x8000442B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1         , RULL(0x8000442B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2         , RULL(0x8000482B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2         , RULL(0x8000482B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3         , RULL(0x80004C2B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3         , RULL(0x80004C2B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P2_ADR0         , RULL(0x8000402B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P2_ADR0         , RULL(0x8000402B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P2_ADR1         , RULL(0x8000442B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P2_ADR1         , RULL(0x8000442B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P2_ADR2         , RULL(0x8000482B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P2_ADR2         , RULL(0x8000482B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P2_ADR3         , RULL(0x80004C2B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P2_ADR3         , RULL(0x80004C2B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P3_ADR0         , RULL(0x8000402B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P3_ADR0         , RULL(0x8000402B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P3_ADR1         , RULL(0x8000442B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P3_ADR1         , RULL(0x8000442B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P3_ADR2         , RULL(0x8000482B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P3_ADR2         , RULL(0x8000482B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P3_ADR3         , RULL(0x80004C2B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P3_ADR3         , RULL(0x80004C2B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0  , RULL(0x800080330701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0 , RULL(0x800080330701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0 , RULL(0x800080330801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1  , RULL(0x800084330701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1 , RULL(0x800084330701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1 , RULL(0x800084330801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P1_ADR32S0 , RULL(0x800080330701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P1_ADR32S0 , RULL(0x800080330801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P1_ADR32S1 , RULL(0x800084330701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P1_ADR32S1 , RULL(0x800084330801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P2_ADR32S0 , RULL(0x800080330701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P2_ADR32S0 , RULL(0x800080330801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P2_ADR32S1 , RULL(0x800084330701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P2_ADR32S1 , RULL(0x800084330801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P3_ADR32S0 , RULL(0x8000803307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P3_ADR32S0 , RULL(0x8000803308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P3_ADR32S1 , RULL(0x8000843307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P3_ADR32S1 , RULL(0x8000843308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0    , RULL(0x800080360701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0  , RULL(0x800080360701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0  , RULL(0x800080360801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1    , RULL(0x800084360701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1  , RULL(0x800084360701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1  , RULL(0x800084360801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P1_ADR32S0  , RULL(0x800080360701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P1_ADR32S0  , RULL(0x800080360801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P1_ADR32S1  , RULL(0x800084360701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P1_ADR32S1  , RULL(0x800084360801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P2_ADR32S0  , RULL(0x800080360701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P2_ADR32S0  , RULL(0x800080360801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P2_ADR32S1  , RULL(0x800084360701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P2_ADR32S1  , RULL(0x800084360801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P3_ADR32S0  , RULL(0x8000803607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P3_ADR32S0  , RULL(0x8000803608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P3_ADR32S1  , RULL(0x8000843607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P3_ADR32S1  , RULL(0x8000843608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0    , RULL(0x800080370701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0  , RULL(0x800080370701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0  , RULL(0x800080370801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1    , RULL(0x800084370701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1  , RULL(0x800084370701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1  , RULL(0x800084370801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P1_ADR32S0  , RULL(0x800080370701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P1_ADR32S0  , RULL(0x800080370801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P1_ADR32S1  , RULL(0x800084370701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P1_ADR32S1  , RULL(0x800084370801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P2_ADR32S0  , RULL(0x800080370701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P2_ADR32S0  , RULL(0x800080370801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P2_ADR32S1  , RULL(0x800084370701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P2_ADR32S1  , RULL(0x800084370801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P3_ADR32S0  , RULL(0x8000803707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P3_ADR32S0  , RULL(0x8000803708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P3_ADR32S1  , RULL(0x8000843707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P3_ADR32S1  , RULL(0x8000843708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0       , RULL(0x800080350701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0     , RULL(0x800080350701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0     , RULL(0x800080350801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1       , RULL(0x800084350701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1     , RULL(0x800084350701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1     , RULL(0x800084350801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0     , RULL(0x800080350701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S0     , RULL(0x800080350801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1     , RULL(0x800084350701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P1_ADR32S1     , RULL(0x800084350801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P2_ADR32S0     , RULL(0x800080350701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P2_ADR32S0     , RULL(0x800080350801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P2_ADR32S1     , RULL(0x800084350701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P2_ADR32S1     , RULL(0x800084350801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P3_ADR32S0     , RULL(0x8000803507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P3_ADR32S0     , RULL(0x8000803508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P3_ADR32S1     , RULL(0x8000843507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P3_ADR32S1     , RULL(0x8000843508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0                      , RULL(0x8000402C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_POWERDOWN_2_P0_ADR0                    , RULL(0x8000402C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_POWERDOWN_2_P0_ADR0                    , RULL(0x8000402C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1                      , RULL(0x8000442C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_POWERDOWN_2_P0_ADR1                    , RULL(0x8000442C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_POWERDOWN_2_P0_ADR1                    , RULL(0x8000442C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2                      , RULL(0x8000482C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_POWERDOWN_2_P0_ADR2                    , RULL(0x8000482C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_POWERDOWN_2_P0_ADR2                    , RULL(0x8000482C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3                      , RULL(0x80004C2C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_POWERDOWN_2_P0_ADR3                    , RULL(0x80004C2C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_POWERDOWN_2_P0_ADR3                    , RULL(0x80004C2C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_POWERDOWN_2_P1_ADR0                    , RULL(0x8000402C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_POWERDOWN_2_P1_ADR0                    , RULL(0x8000402C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_POWERDOWN_2_P1_ADR1                    , RULL(0x8000442C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_POWERDOWN_2_P1_ADR1                    , RULL(0x8000442C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_POWERDOWN_2_P1_ADR2                    , RULL(0x8000482C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_POWERDOWN_2_P1_ADR2                    , RULL(0x8000482C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_POWERDOWN_2_P1_ADR3                    , RULL(0x80004C2C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_POWERDOWN_2_P1_ADR3                    , RULL(0x80004C2C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_POWERDOWN_2_P2_ADR0                    , RULL(0x8000402C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_POWERDOWN_2_P2_ADR0                    , RULL(0x8000402C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_POWERDOWN_2_P2_ADR1                    , RULL(0x8000442C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_POWERDOWN_2_P2_ADR1                    , RULL(0x8000442C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_POWERDOWN_2_P2_ADR2                    , RULL(0x8000482C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_POWERDOWN_2_P2_ADR2                    , RULL(0x8000482C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_POWERDOWN_2_P2_ADR3                    , RULL(0x80004C2C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_POWERDOWN_2_P2_ADR3                    , RULL(0x80004C2C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_POWERDOWN_2_P3_ADR0                    , RULL(0x8000402C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_POWERDOWN_2_P3_ADR0                    , RULL(0x8000402C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_POWERDOWN_2_P3_ADR1                    , RULL(0x8000442C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_POWERDOWN_2_P3_ADR1                    , RULL(0x8000442C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_POWERDOWN_2_P3_ADR2                    , RULL(0x8000482C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_POWERDOWN_2_P3_ADR2                    , RULL(0x8000482C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_POWERDOWN_2_P3_ADR3                    , RULL(0x80004C2C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_POWERDOWN_2_P3_ADR3                    , RULL(0x80004C2C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0                 , RULL(0x800080390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0               , RULL(0x800080390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0               , RULL(0x800080390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1                 , RULL(0x800084390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1               , RULL(0x800084390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1               , RULL(0x800084390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S0               , RULL(0x800080390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S0               , RULL(0x800080390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S1               , RULL(0x800084390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S1               , RULL(0x800084390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_SLEW_CAL_CNTL_P2_ADR32S0               , RULL(0x800080390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_SLEW_CAL_CNTL_P2_ADR32S0               , RULL(0x800080390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_SLEW_CAL_CNTL_P2_ADR32S1               , RULL(0x800084390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_SLEW_CAL_CNTL_P2_ADR32S1               , RULL(0x800084390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_SLEW_CAL_CNTL_P3_ADR32S0               , RULL(0x8000803907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_SLEW_CAL_CNTL_P3_ADR32S0               , RULL(0x8000803908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_SLEW_CAL_CNTL_P3_ADR32S1               , RULL(0x8000843907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_SLEW_CAL_CNTL_P3_ADR32S1               , RULL(0x8000843908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0                , RULL(0x800080320701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0              , RULL(0x800080320701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0              , RULL(0x800080320801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1                , RULL(0x800084320701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1              , RULL(0x800084320701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1              , RULL(0x800084320801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0              , RULL(0x800080320701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0              , RULL(0x800080320801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1              , RULL(0x800084320701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1              , RULL(0x800084320801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_SYSCLK_CNTL_PR_P2_ADR32S0              , RULL(0x800080320701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_SYSCLK_CNTL_PR_P2_ADR32S0              , RULL(0x800080320801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_ADR_SYSCLK_CNTL_PR_P2_ADR32S1              , RULL(0x800084320701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_ADR_SYSCLK_CNTL_PR_P2_ADR32S1              , RULL(0x800084320801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_SYSCLK_CNTL_PR_P3_ADR32S0              , RULL(0x8000803207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_SYSCLK_CNTL_PR_P3_ADR32S0              , RULL(0x8000803208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_ADR_SYSCLK_CNTL_PR_P3_ADR32S1              , RULL(0x8000843207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_ADR_SYSCLK_CNTL_PR_P3_ADR32S1              , RULL(0x8000843208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0            , RULL(0x800080340701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0          , RULL(0x800080340701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0          , RULL(0x800080340801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1            , RULL(0x800084340701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1          , RULL(0x800084340701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1          , RULL(0x800084340801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0          , RULL(0x800080340701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0          , RULL(0x800080340801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S1          , RULL(0x800084340701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S1          , RULL(0x800084340801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P2_ADR32S0          , RULL(0x800080340701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P2_ADR32S0          , RULL(0x800080340801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P2_ADR32S1          , RULL(0x800084340701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P2_ADR32S1          , RULL(0x800084340801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P3_ADR32S0          , RULL(0x8000803407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P3_ADR32S0          , RULL(0x8000803408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P3_ADR32S1          , RULL(0x8000843407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P3_ADR32S1          , RULL(0x8000843408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0                         , RULL(0x8000D0050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_APB_ATEST_MUX_SEL_P0                       , RULL(0x8000D0050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_APB_ATEST_MUX_SEL_P0                       , RULL(0x8000D0050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_APB_ATEST_MUX_SEL_P1                       , RULL(0x8000D0050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_APB_ATEST_MUX_SEL_P1                       , RULL(0x8000D0050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_APB_ATEST_MUX_SEL_P2                       , RULL(0x8000D0050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_APB_ATEST_MUX_SEL_P2                       , RULL(0x8000D0050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_APB_ATEST_MUX_SEL_P3                       , RULL(0x8000D00507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_APB_ATEST_MUX_SEL_P3                       , RULL(0x8000D00508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_APB_CONFIG0_P0                               , RULL(0x8000D0000701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_APB_CONFIG0_P0                             , RULL(0x8000D0000701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_APB_CONFIG0_P0                             , RULL(0x8000D0000801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_APB_CONFIG0_P1                             , RULL(0x8000D0000701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_APB_CONFIG0_P1                             , RULL(0x8000D0000801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_APB_CONFIG0_P2                             , RULL(0x8000D0000701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_APB_CONFIG0_P2                             , RULL(0x8000D0000801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_APB_CONFIG0_P3                             , RULL(0x8000D00007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_APB_CONFIG0_P3                             , RULL(0x8000D00008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_APB_ERROR_MASK0_P0                           , RULL(0x8000D0020701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_APB_ERROR_MASK0_P0                         , RULL(0x8000D0020701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_APB_ERROR_MASK0_P0                         , RULL(0x8000D0020801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_APB_ERROR_MASK0_P1                         , RULL(0x8000D0020701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_APB_ERROR_MASK0_P1                         , RULL(0x8000D0020801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_APB_ERROR_MASK0_P2                         , RULL(0x8000D0020701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_APB_ERROR_MASK0_P2                         , RULL(0x8000D0020801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_APB_ERROR_MASK0_P3                         , RULL(0x8000D00207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_APB_ERROR_MASK0_P3                         , RULL(0x8000D00208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_APB_ERROR_STATUS0_P0                         , RULL(0x8000D0010701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_APB_ERROR_STATUS0_P0                       , RULL(0x8000D0010701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_APB_ERROR_STATUS0_P0                       , RULL(0x8000D0010801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_APB_ERROR_STATUS0_P1                       , RULL(0x8000D0010701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_APB_ERROR_STATUS0_P1                       , RULL(0x8000D0010801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_APB_ERROR_STATUS0_P2                       , RULL(0x8000D0010701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_APB_ERROR_STATUS0_P2                       , RULL(0x8000D0010801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_APB_ERROR_STATUS0_P3                       , RULL(0x8000D00107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_APB_ERROR_STATUS0_P3                       , RULL(0x8000D00108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_APB_FIR_ERR0_P0                              , RULL(0x8000D0060701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_APB_FIR_ERR0_P0                            , RULL(0x8000D0060701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_APB_FIR_ERR0_P0                            , RULL(0x8000D0060801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_APB_FIR_ERR0_P1                            , RULL(0x8000D0060701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_APB_FIR_ERR0_P1                            , RULL(0x8000D0060801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_APB_FIR_ERR0_P2                            , RULL(0x8000D0060701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_APB_FIR_ERR0_P2                            , RULL(0x8000D0060801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_APB_FIR_ERR0_P3                            , RULL(0x8000D00607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_APB_FIR_ERR0_P3                            , RULL(0x8000D00608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_APB_FIR_ERR1_P0                              , RULL(0x8000D0070701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_APB_FIR_ERR1_P0                            , RULL(0x8000D0070701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_APB_FIR_ERR1_P0                            , RULL(0x8000D0070801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_APB_FIR_ERR1_P1                            , RULL(0x8000D0070701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_APB_FIR_ERR1_P1                            , RULL(0x8000D0070801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_APB_FIR_ERR1_P2                            , RULL(0x8000D0070701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_APB_FIR_ERR1_P2                            , RULL(0x8000D0070801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_APB_FIR_ERR1_P3                            , RULL(0x8000D00707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_APB_FIR_ERR1_P3                            , RULL(0x8000D00708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_APB_FIR_ERR2_P0                              , RULL(0x8000D0030701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_APB_FIR_ERR2_P0                            , RULL(0x8000D0030701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_APB_FIR_ERR2_P0                            , RULL(0x8000D0030801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_APB_FIR_ERR2_P1                            , RULL(0x8000D0030701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_APB_FIR_ERR2_P1                            , RULL(0x8000D0030801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_APB_FIR_ERR2_P2                            , RULL(0x8000D0030701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_APB_FIR_ERR2_P2                            , RULL(0x8000D0030801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_APB_FIR_ERR2_P3                            , RULL(0x8000D00307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_APB_FIR_ERR2_P3                            , RULL(0x8000D00308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_APB_FIR_ERR3_P0                              , RULL(0x8000D0040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_APB_FIR_ERR3_P0                            , RULL(0x8000D0040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_APB_FIR_ERR3_P0                            , RULL(0x8000D0040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_APB_FIR_ERR3_P1                            , RULL(0x8000D0040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_APB_FIR_ERR3_P1                            , RULL(0x8000D0040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_APB_FIR_ERR3_P2                            , RULL(0x8000D0040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_APB_FIR_ERR3_P2                            , RULL(0x8000D0040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_APB_FIR_ERR3_P3                            , RULL(0x8000D00407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_APB_FIR_ERR3_P3                            , RULL(0x8000D00408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_APB_LO_PROBE_SEL_P0                          , RULL(0x8000D0080701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_APB_LO_PROBE_SEL_P0                        , RULL(0x8000D0080701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_APB_LO_PROBE_SEL_P0                        , RULL(0x8000D0080801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_APB_LO_PROBE_SEL_P1                        , RULL(0x8000D0080701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_APB_LO_PROBE_SEL_P1                        , RULL(0x8000D0080801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_APB_LO_PROBE_SEL_P2                        , RULL(0x8000D0080701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_APB_LO_PROBE_SEL_P2                        , RULL(0x8000D0080801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_APB_LO_PROBE_SEL_P3                        , RULL(0x8000D00807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_APB_LO_PROBE_SEL_P3                        , RULL(0x8000D00808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0                  , RULL(0x800000220701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0                , RULL(0x800000220701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0                , RULL(0x800000220801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1                  , RULL(0x800004220701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1                , RULL(0x800004220701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1                , RULL(0x800004220801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2                  , RULL(0x800008220701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2                , RULL(0x800008220701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2                , RULL(0x800008220801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3                  , RULL(0x80000C220701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3                , RULL(0x80000C220701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3                , RULL(0x80000C220801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4                  , RULL(0x800010220701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4                , RULL(0x800010220701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4                , RULL(0x800010220801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_0                , RULL(0x800000220701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_0                , RULL(0x800000220801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_1                , RULL(0x800004220701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_1                , RULL(0x800004220801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_2                , RULL(0x800008220701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_2                , RULL(0x800008220801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_3                , RULL(0x80000C220701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_3                , RULL(0x80000C220801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_4                , RULL(0x800010220701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P1_4                , RULL(0x800010220801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_0                , RULL(0x800000220701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_0                , RULL(0x800000220801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_1                , RULL(0x800004220701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_1                , RULL(0x800004220801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_2                , RULL(0x800008220701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_2                , RULL(0x800008220801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_3                , RULL(0x80000C220701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_3                , RULL(0x80000C220801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_4                , RULL(0x800010220701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P2_4                , RULL(0x800010220801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_0                , RULL(0x8000002207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_0                , RULL(0x8000002208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_1                , RULL(0x8000042207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_1                , RULL(0x8000042208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_2                , RULL(0x8000082207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_2                , RULL(0x8000082208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_3                , RULL(0x80000C2207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_3                , RULL(0x80000C2208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_4                , RULL(0x8000102207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P3_4                , RULL(0x8000102208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0                  , RULL(0x800000230701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0                , RULL(0x800000230701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0                , RULL(0x800000230801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1                  , RULL(0x800004230701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1                , RULL(0x800004230701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1                , RULL(0x800004230801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2                  , RULL(0x800008230701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2                , RULL(0x800008230701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2                , RULL(0x800008230801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3                  , RULL(0x80000C230701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3                , RULL(0x80000C230701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3                , RULL(0x80000C230801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4                  , RULL(0x800010230701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4                , RULL(0x800010230701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4                , RULL(0x800010230801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_0                , RULL(0x800000230701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_0                , RULL(0x800000230801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_1                , RULL(0x800004230701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_1                , RULL(0x800004230801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_2                , RULL(0x800008230701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_2                , RULL(0x800008230801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_3                , RULL(0x80000C230701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_3                , RULL(0x80000C230801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_4                , RULL(0x800010230701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P1_4                , RULL(0x800010230801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_0                , RULL(0x800000230701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_0                , RULL(0x800000230801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_1                , RULL(0x800004230701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_1                , RULL(0x800004230801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_2                , RULL(0x800008230701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_2                , RULL(0x800008230801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_3                , RULL(0x80000C230701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_3                , RULL(0x80000C230801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_4                , RULL(0x800010230701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P2_4                , RULL(0x800010230801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_0                , RULL(0x8000002307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_0                , RULL(0x8000002308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_1                , RULL(0x8000042307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_1                , RULL(0x8000042308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_2                , RULL(0x8000082307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_2                , RULL(0x8000082308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_3                , RULL(0x80000C2307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_3                , RULL(0x80000C2308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_4                , RULL(0x8000102307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P3_4                , RULL(0x8000102308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0                     , RULL(0x800000200701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0                   , RULL(0x800000200701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0                   , RULL(0x800000200801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1                     , RULL(0x800004200701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1                   , RULL(0x800004200701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1                   , RULL(0x800004200801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2                     , RULL(0x800008200701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2                   , RULL(0x800008200701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2                   , RULL(0x800008200801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3                     , RULL(0x80000C200701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3                   , RULL(0x80000C200701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3                   , RULL(0x80000C200801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4                     , RULL(0x800010200701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4                   , RULL(0x800010200701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4                   , RULL(0x800010200801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_0                   , RULL(0x800000200701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_0                   , RULL(0x800000200801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_1                   , RULL(0x800004200701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_1                   , RULL(0x800004200801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_2                   , RULL(0x800008200701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_2                   , RULL(0x800008200801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_3                   , RULL(0x80000C200701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_3                   , RULL(0x80000C200801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_4                   , RULL(0x800010200701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE0_P1_4                   , RULL(0x800010200801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_0                   , RULL(0x800000200701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_0                   , RULL(0x800000200801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_1                   , RULL(0x800004200701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_1                   , RULL(0x800004200801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_2                   , RULL(0x800008200701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_2                   , RULL(0x800008200801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_3                   , RULL(0x80000C200701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_3                   , RULL(0x80000C200801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_4                   , RULL(0x800010200701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE0_P2_4                   , RULL(0x800010200801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_0                   , RULL(0x8000002007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_0                   , RULL(0x8000002008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_1                   , RULL(0x8000042007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_1                   , RULL(0x8000042008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_2                   , RULL(0x8000082007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_2                   , RULL(0x8000082008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_3                   , RULL(0x80000C2007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_3                   , RULL(0x80000C2008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_4                   , RULL(0x8000102007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE0_P3_4                   , RULL(0x8000102008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0                     , RULL(0x800000210701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0                   , RULL(0x800000210701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0                   , RULL(0x800000210801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1                     , RULL(0x800004210701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1                   , RULL(0x800004210701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1                   , RULL(0x800004210801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2                     , RULL(0x800008210701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2                   , RULL(0x800008210701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2                   , RULL(0x800008210801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3                     , RULL(0x80000C210701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3                   , RULL(0x80000C210701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3                   , RULL(0x80000C210801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4                     , RULL(0x800010210701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4                   , RULL(0x800010210701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4                   , RULL(0x800010210801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_0                   , RULL(0x800000210701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_0                   , RULL(0x800000210801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_1                   , RULL(0x800004210701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_1                   , RULL(0x800004210801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_2                   , RULL(0x800008210701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_2                   , RULL(0x800008210801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_3                   , RULL(0x80000C210701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_3                   , RULL(0x80000C210801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_4                   , RULL(0x800010210701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_CTLE_CTL_BYTE1_P1_4                   , RULL(0x800010210801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_0                   , RULL(0x800000210701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_0                   , RULL(0x800000210801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_1                   , RULL(0x800004210701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_1                   , RULL(0x800004210801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_2                   , RULL(0x800008210701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_2                   , RULL(0x800008210801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_3                   , RULL(0x80000C210701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_3                   , RULL(0x80000C210801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_4                   , RULL(0x800010210701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_CTLE_CTL_BYTE1_P2_4                   , RULL(0x800010210801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_0                   , RULL(0x8000002107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_0                   , RULL(0x8000002108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_1                   , RULL(0x8000042107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_1                   , RULL(0x8000042108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_2                   , RULL(0x8000082107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_2                   , RULL(0x8000082108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_3                   , RULL(0x80000C2107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_3                   , RULL(0x80000C2108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_4                   , RULL(0x8000102107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_CTLE_CTL_BYTE1_P3_4                   , RULL(0x8000102108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_0                      , RULL(0x800000020701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DIR0_P0_0                    , RULL(0x800000020701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DIR0_P0_0                    , RULL(0x800000020801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_1                      , RULL(0x800004020701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DIR0_P0_1                    , RULL(0x800004020701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DIR0_P0_1                    , RULL(0x800004020801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_2                      , RULL(0x800008020701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DIR0_P0_2                    , RULL(0x800008020701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DIR0_P0_2                    , RULL(0x800008020801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_3                      , RULL(0x80000C020701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DIR0_P0_3                    , RULL(0x80000C020701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DIR0_P0_3                    , RULL(0x80000C020801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_4                      , RULL(0x800010020701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DIR0_P0_4                    , RULL(0x800010020701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DIR0_P0_4                    , RULL(0x800010020801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DIR0_P1_0                    , RULL(0x800000020701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DIR0_P1_0                    , RULL(0x800000020801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DIR0_P1_1                    , RULL(0x800004020701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DIR0_P1_1                    , RULL(0x800004020801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DIR0_P1_2                    , RULL(0x800008020701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DIR0_P1_2                    , RULL(0x800008020801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DIR0_P1_3                    , RULL(0x80000C020701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DIR0_P1_3                    , RULL(0x80000C020801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DIR0_P1_4                    , RULL(0x800010020701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DIR0_P1_4                    , RULL(0x800010020801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DIR0_P2_0                    , RULL(0x800000020701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DIR0_P2_0                    , RULL(0x800000020801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DIR0_P2_1                    , RULL(0x800004020701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DIR0_P2_1                    , RULL(0x800004020801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DIR0_P2_2                    , RULL(0x800008020701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DIR0_P2_2                    , RULL(0x800008020801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DIR0_P2_3                    , RULL(0x80000C020701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DIR0_P2_3                    , RULL(0x80000C020801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DIR0_P2_4                    , RULL(0x800010020701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DIR0_P2_4                    , RULL(0x800010020801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DIR0_P3_0                    , RULL(0x8000000207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DIR0_P3_0                    , RULL(0x8000000208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DIR0_P3_1                    , RULL(0x8000040207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DIR0_P3_1                    , RULL(0x8000040208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DIR0_P3_2                    , RULL(0x8000080207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DIR0_P3_2                    , RULL(0x8000080208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DIR0_P3_3                    , RULL(0x80000C0207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DIR0_P3_3                    , RULL(0x80000C0208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DIR0_P3_4                    , RULL(0x8000100207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DIR0_P3_4                    , RULL(0x8000100208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0                      , RULL(0x800000030701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DIR1_P0_0                    , RULL(0x800000030701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DIR1_P0_0                    , RULL(0x800000030801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1                      , RULL(0x800004030701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DIR1_P0_1                    , RULL(0x800004030701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DIR1_P0_1                    , RULL(0x800004030801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2                      , RULL(0x800008030701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DIR1_P0_2                    , RULL(0x800008030701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DIR1_P0_2                    , RULL(0x800008030801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3                      , RULL(0x80000C030701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DIR1_P0_3                    , RULL(0x80000C030701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DIR1_P0_3                    , RULL(0x80000C030801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4                      , RULL(0x800010030701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DIR1_P0_4                    , RULL(0x800010030701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DIR1_P0_4                    , RULL(0x800010030801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DIR1_P1_0                    , RULL(0x800000030701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DIR1_P1_0                    , RULL(0x800000030801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DIR1_P1_1                    , RULL(0x800004030701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DIR1_P1_1                    , RULL(0x800004030801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DIR1_P1_2                    , RULL(0x800008030701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DIR1_P1_2                    , RULL(0x800008030801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DIR1_P1_3                    , RULL(0x80000C030701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DIR1_P1_3                    , RULL(0x80000C030801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DIR1_P1_4                    , RULL(0x800010030701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DIR1_P1_4                    , RULL(0x800010030801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DIR1_P2_0                    , RULL(0x800000030701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DIR1_P2_0                    , RULL(0x800000030801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DIR1_P2_1                    , RULL(0x800004030701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DIR1_P2_1                    , RULL(0x800004030801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DIR1_P2_2                    , RULL(0x800008030701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DIR1_P2_2                    , RULL(0x800008030801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DIR1_P2_3                    , RULL(0x80000C030701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DIR1_P2_3                    , RULL(0x80000C030801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DIR1_P2_4                    , RULL(0x800010030701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DIR1_P2_4                    , RULL(0x800010030801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DIR1_P3_0                    , RULL(0x8000000307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DIR1_P3_0                    , RULL(0x8000000308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DIR1_P3_1                    , RULL(0x8000040307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DIR1_P3_1                    , RULL(0x8000040308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DIR1_P3_2                    , RULL(0x8000080307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DIR1_P3_2                    , RULL(0x8000080308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DIR1_P3_3                    , RULL(0x80000C0307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DIR1_P3_3                    , RULL(0x80000C0308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DIR1_P3_4                    , RULL(0x8000100307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DIR1_P3_4                    , RULL(0x8000100308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_0              , RULL(0x8000007C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_0            , RULL(0x8000007C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_0            , RULL(0x8000007C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_1              , RULL(0x8000047C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_1            , RULL(0x8000047C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_1            , RULL(0x8000047C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_2              , RULL(0x8000087C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_2            , RULL(0x8000087C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_2            , RULL(0x8000087C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_3              , RULL(0x80000C7C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_3            , RULL(0x80000C7C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_3            , RULL(0x80000C7C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_4              , RULL(0x8000107C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_4            , RULL(0x8000107C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_4            , RULL(0x8000107C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_0            , RULL(0x8000007C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_0            , RULL(0x8000007C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_1            , RULL(0x8000047C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_1            , RULL(0x8000047C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_2            , RULL(0x8000087C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_2            , RULL(0x8000087C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_3            , RULL(0x80000C7C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_3            , RULL(0x80000C7C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_4            , RULL(0x8000107C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_4            , RULL(0x8000107C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P2_0            , RULL(0x8000007C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P2_0            , RULL(0x8000007C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P2_1            , RULL(0x8000047C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P2_1            , RULL(0x8000047C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P2_2            , RULL(0x8000087C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P2_2            , RULL(0x8000087C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P2_3            , RULL(0x80000C7C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P2_3            , RULL(0x80000C7C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P2_4            , RULL(0x8000107C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P2_4            , RULL(0x8000107C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P3_0            , RULL(0x8000007C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P3_0            , RULL(0x8000007C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P3_1            , RULL(0x8000047C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P3_1            , RULL(0x8000047C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P3_2            , RULL(0x8000087C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P3_2            , RULL(0x8000087C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P3_3            , RULL(0x80000C7C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P3_3            , RULL(0x80000C7C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P3_4            , RULL(0x8000107C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P3_4            , RULL(0x8000107C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_0              , RULL(0x8000017C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_0            , RULL(0x8000017C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_0            , RULL(0x8000017C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_1              , RULL(0x8000057C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_1            , RULL(0x8000057C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_1            , RULL(0x8000057C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_2              , RULL(0x8000097C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_2            , RULL(0x8000097C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_2            , RULL(0x8000097C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_3              , RULL(0x80000D7C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_3            , RULL(0x80000D7C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_3            , RULL(0x80000D7C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_4              , RULL(0x8000117C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_4            , RULL(0x8000117C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_4            , RULL(0x8000117C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_0            , RULL(0x8000017C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_0            , RULL(0x8000017C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_1            , RULL(0x8000057C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_1            , RULL(0x8000057C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_2            , RULL(0x8000097C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_2            , RULL(0x8000097C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_3            , RULL(0x80000D7C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_3            , RULL(0x80000D7C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_4            , RULL(0x8000117C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_4            , RULL(0x8000117C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P2_0            , RULL(0x8000017C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P2_0            , RULL(0x8000017C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P2_1            , RULL(0x8000057C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P2_1            , RULL(0x8000057C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P2_2            , RULL(0x8000097C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P2_2            , RULL(0x8000097C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P2_3            , RULL(0x80000D7C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P2_3            , RULL(0x80000D7C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P2_4            , RULL(0x8000117C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P2_4            , RULL(0x8000117C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P3_0            , RULL(0x8000017C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P3_0            , RULL(0x8000017C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P3_1            , RULL(0x8000057C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P3_1            , RULL(0x8000057C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P3_2            , RULL(0x8000097C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P3_2            , RULL(0x8000097C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P3_3            , RULL(0x80000D7C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P3_3            , RULL(0x80000D7C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P3_4            , RULL(0x8000117C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P3_4            , RULL(0x8000117C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_0              , RULL(0x8000027C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_0            , RULL(0x8000027C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_0            , RULL(0x8000027C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_1              , RULL(0x8000067C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_1            , RULL(0x8000067C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_1            , RULL(0x8000067C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_2              , RULL(0x80000A7C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_2            , RULL(0x80000A7C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_2            , RULL(0x80000A7C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_3              , RULL(0x80000E7C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_3            , RULL(0x80000E7C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_3            , RULL(0x80000E7C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_4              , RULL(0x8000127C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_4            , RULL(0x8000127C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_4            , RULL(0x8000127C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_0            , RULL(0x8000027C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_0            , RULL(0x8000027C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_1            , RULL(0x8000067C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_1            , RULL(0x8000067C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_2            , RULL(0x80000A7C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_2            , RULL(0x80000A7C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_3            , RULL(0x80000E7C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_3            , RULL(0x80000E7C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_4            , RULL(0x8000127C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_4            , RULL(0x8000127C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P2_0            , RULL(0x8000027C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P2_0            , RULL(0x8000027C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P2_1            , RULL(0x8000067C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P2_1            , RULL(0x8000067C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P2_2            , RULL(0x80000A7C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P2_2            , RULL(0x80000A7C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P2_3            , RULL(0x80000E7C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P2_3            , RULL(0x80000E7C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P2_4            , RULL(0x8000127C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P2_4            , RULL(0x8000127C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P3_0            , RULL(0x8000027C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P3_0            , RULL(0x8000027C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P3_1            , RULL(0x8000067C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P3_1            , RULL(0x8000067C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P3_2            , RULL(0x80000A7C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P3_2            , RULL(0x80000A7C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P3_3            , RULL(0x80000E7C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P3_3            , RULL(0x80000E7C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P3_4            , RULL(0x8000127C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P3_4            , RULL(0x8000127C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_0              , RULL(0x8000037C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_0            , RULL(0x8000037C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_0            , RULL(0x8000037C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_1              , RULL(0x8000077C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_1            , RULL(0x8000077C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_1            , RULL(0x8000077C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_2              , RULL(0x80000B7C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_2            , RULL(0x80000B7C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_2            , RULL(0x80000B7C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_3              , RULL(0x80000F7C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_3            , RULL(0x80000F7C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_3            , RULL(0x80000F7C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_4              , RULL(0x8000137C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_4            , RULL(0x8000137C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_4            , RULL(0x8000137C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_0            , RULL(0x8000037C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_0            , RULL(0x8000037C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_1            , RULL(0x8000077C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_1            , RULL(0x8000077C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_2            , RULL(0x80000B7C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_2            , RULL(0x80000B7C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_3            , RULL(0x80000F7C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_3            , RULL(0x80000F7C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_4            , RULL(0x8000137C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_4            , RULL(0x8000137C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P2_0            , RULL(0x8000037C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P2_0            , RULL(0x8000037C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P2_1            , RULL(0x8000077C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P2_1            , RULL(0x8000077C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P2_2            , RULL(0x80000B7C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P2_2            , RULL(0x80000B7C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P2_3            , RULL(0x80000F7C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P2_3            , RULL(0x80000F7C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P2_4            , RULL(0x8000137C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P2_4            , RULL(0x8000137C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P3_0            , RULL(0x8000037C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P3_0            , RULL(0x8000037C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P3_1            , RULL(0x8000077C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P3_1            , RULL(0x8000077C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P3_2            , RULL(0x80000B7C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P3_2            , RULL(0x80000B7C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P3_3            , RULL(0x80000F7C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P3_3            , RULL(0x80000F7C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P3_4            , RULL(0x8000137C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P3_4            , RULL(0x8000137C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_0              , RULL(0x8000007D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_0            , RULL(0x8000007D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_0            , RULL(0x8000007D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_1              , RULL(0x8000047D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_1            , RULL(0x8000047D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_1            , RULL(0x8000047D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_2              , RULL(0x8000087D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_2            , RULL(0x8000087D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_2            , RULL(0x8000087D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_3              , RULL(0x80000C7D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_3            , RULL(0x80000C7D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_3            , RULL(0x80000C7D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_4              , RULL(0x8000107D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_4            , RULL(0x8000107D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_4            , RULL(0x8000107D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P1_0            , RULL(0x8000007D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P1_0            , RULL(0x8000007D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P1_1            , RULL(0x8000047D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P1_1            , RULL(0x8000047D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P1_2            , RULL(0x8000087D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P1_2            , RULL(0x8000087D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P1_3            , RULL(0x80000C7D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P1_3            , RULL(0x80000C7D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P1_4            , RULL(0x8000107D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P1_4            , RULL(0x8000107D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P2_0            , RULL(0x8000007D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P2_0            , RULL(0x8000007D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P2_1            , RULL(0x8000047D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P2_1            , RULL(0x8000047D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P2_2            , RULL(0x8000087D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P2_2            , RULL(0x8000087D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P2_3            , RULL(0x80000C7D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P2_3            , RULL(0x80000C7D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P2_4            , RULL(0x8000107D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P2_4            , RULL(0x8000107D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P3_0            , RULL(0x8000007D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P3_0            , RULL(0x8000007D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P3_1            , RULL(0x8000047D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P3_1            , RULL(0x8000047D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P3_2            , RULL(0x8000087D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P3_2            , RULL(0x8000087D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P3_3            , RULL(0x80000C7D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P3_3            , RULL(0x80000C7D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P3_4            , RULL(0x8000107D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P3_4            , RULL(0x8000107D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_0              , RULL(0x8000017D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_0            , RULL(0x8000017D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_0            , RULL(0x8000017D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_1              , RULL(0x8000057D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_1            , RULL(0x8000057D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_1            , RULL(0x8000057D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_2              , RULL(0x8000097D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_2            , RULL(0x8000097D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_2            , RULL(0x8000097D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_3              , RULL(0x80000D7D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_3            , RULL(0x80000D7D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_3            , RULL(0x80000D7D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_4              , RULL(0x8000117D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_4            , RULL(0x8000117D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_4            , RULL(0x8000117D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P1_0            , RULL(0x8000017D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P1_0            , RULL(0x8000017D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P1_1            , RULL(0x8000057D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P1_1            , RULL(0x8000057D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P1_2            , RULL(0x8000097D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P1_2            , RULL(0x8000097D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P1_3            , RULL(0x80000D7D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P1_3            , RULL(0x80000D7D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P1_4            , RULL(0x8000117D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P1_4            , RULL(0x8000117D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P2_0            , RULL(0x8000017D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P2_0            , RULL(0x8000017D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P2_1            , RULL(0x8000057D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P2_1            , RULL(0x8000057D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P2_2            , RULL(0x8000097D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P2_2            , RULL(0x8000097D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P2_3            , RULL(0x80000D7D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P2_3            , RULL(0x80000D7D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P2_4            , RULL(0x8000117D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P2_4            , RULL(0x8000117D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P3_0            , RULL(0x8000017D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P3_0            , RULL(0x8000017D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P3_1            , RULL(0x8000057D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P3_1            , RULL(0x8000057D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P3_2            , RULL(0x8000097D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P3_2            , RULL(0x8000097D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P3_3            , RULL(0x80000D7D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P3_3            , RULL(0x80000D7D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P3_4            , RULL(0x8000117D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P3_4            , RULL(0x8000117D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_0              , RULL(0x8000027D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_0            , RULL(0x8000027D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_0            , RULL(0x8000027D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_1              , RULL(0x8000067D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_1            , RULL(0x8000067D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_1            , RULL(0x8000067D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_2              , RULL(0x80000A7D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_2            , RULL(0x80000A7D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_2            , RULL(0x80000A7D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_3              , RULL(0x80000E7D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_3            , RULL(0x80000E7D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_3            , RULL(0x80000E7D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_4              , RULL(0x8000127D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_4            , RULL(0x8000127D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_4            , RULL(0x8000127D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P1_0            , RULL(0x8000027D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P1_0            , RULL(0x8000027D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P1_1            , RULL(0x8000067D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P1_1            , RULL(0x8000067D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P1_2            , RULL(0x80000A7D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P1_2            , RULL(0x80000A7D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P1_3            , RULL(0x80000E7D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P1_3            , RULL(0x80000E7D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P1_4            , RULL(0x8000127D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P1_4            , RULL(0x8000127D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P2_0            , RULL(0x8000027D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P2_0            , RULL(0x8000027D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P2_1            , RULL(0x8000067D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P2_1            , RULL(0x8000067D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P2_2            , RULL(0x80000A7D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P2_2            , RULL(0x80000A7D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P2_3            , RULL(0x80000E7D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P2_3            , RULL(0x80000E7D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P2_4            , RULL(0x8000127D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P2_4            , RULL(0x8000127D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P3_0            , RULL(0x8000027D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P3_0            , RULL(0x8000027D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P3_1            , RULL(0x8000067D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P3_1            , RULL(0x8000067D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P3_2            , RULL(0x80000A7D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P3_2            , RULL(0x80000A7D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P3_3            , RULL(0x80000E7D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P3_3            , RULL(0x80000E7D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P3_4            , RULL(0x8000127D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P3_4            , RULL(0x8000127D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_0              , RULL(0x8000037D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_0            , RULL(0x8000037D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_0            , RULL(0x8000037D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_1              , RULL(0x8000077D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_1            , RULL(0x8000077D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_1            , RULL(0x8000077D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_2              , RULL(0x80000B7D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_2            , RULL(0x80000B7D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_2            , RULL(0x80000B7D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_3              , RULL(0x80000F7D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_3            , RULL(0x80000F7D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_3            , RULL(0x80000F7D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_4              , RULL(0x8000137D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_4            , RULL(0x8000137D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_4            , RULL(0x8000137D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P1_0            , RULL(0x8000037D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P1_0            , RULL(0x8000037D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P1_1            , RULL(0x8000077D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P1_1            , RULL(0x8000077D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P1_2            , RULL(0x80000B7D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P1_2            , RULL(0x80000B7D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P1_3            , RULL(0x80000F7D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P1_3            , RULL(0x80000F7D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P1_4            , RULL(0x8000137D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P1_4            , RULL(0x8000137D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P2_0            , RULL(0x8000037D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P2_0            , RULL(0x8000037D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P2_1            , RULL(0x8000077D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P2_1            , RULL(0x8000077D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P2_2            , RULL(0x80000B7D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P2_2            , RULL(0x80000B7D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P2_3            , RULL(0x80000F7D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P2_3            , RULL(0x80000F7D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P2_4            , RULL(0x8000137D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P2_4            , RULL(0x8000137D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P3_0            , RULL(0x8000037D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P3_0            , RULL(0x8000037D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P3_1            , RULL(0x8000077D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P3_1            , RULL(0x8000077D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P3_2            , RULL(0x80000B7D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P3_2            , RULL(0x80000B7D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P3_3            , RULL(0x80000F7D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P3_3            , RULL(0x80000F7D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P3_4            , RULL(0x8000137D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P3_4            , RULL(0x8000137D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_0                   , RULL(0x800000000701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_0                 , RULL(0x800000000701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_0                 , RULL(0x800000000801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_1                   , RULL(0x800004000701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_1                 , RULL(0x800004000701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_1                 , RULL(0x800004000801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_2                   , RULL(0x800008000701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_2                 , RULL(0x800008000701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_2                 , RULL(0x800008000801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_3                   , RULL(0x80000C000701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_3                 , RULL(0x80000C000701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_3                 , RULL(0x80000C000801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_4                   , RULL(0x800010000701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_4                 , RULL(0x800010000701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_4                 , RULL(0x800010000801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_ENABLE0_P1_0                 , RULL(0x800000000701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_ENABLE0_P1_0                 , RULL(0x800000000801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_ENABLE0_P1_1                 , RULL(0x800004000701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_ENABLE0_P1_1                 , RULL(0x800004000801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_ENABLE0_P1_2                 , RULL(0x800008000701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_ENABLE0_P1_2                 , RULL(0x800008000801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_ENABLE0_P1_3                 , RULL(0x80000C000701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_ENABLE0_P1_3                 , RULL(0x80000C000801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_ENABLE0_P1_4                 , RULL(0x800010000701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_ENABLE0_P1_4                 , RULL(0x800010000801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_ENABLE0_P2_0                 , RULL(0x800000000701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_ENABLE0_P2_0                 , RULL(0x800000000801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_ENABLE0_P2_1                 , RULL(0x800004000701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_ENABLE0_P2_1                 , RULL(0x800004000801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_ENABLE0_P2_2                 , RULL(0x800008000701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_ENABLE0_P2_2                 , RULL(0x800008000801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_ENABLE0_P2_3                 , RULL(0x80000C000701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_ENABLE0_P2_3                 , RULL(0x80000C000801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_ENABLE0_P2_4                 , RULL(0x800010000701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_ENABLE0_P2_4                 , RULL(0x800010000801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_ENABLE0_P3_0                 , RULL(0x8000000007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_ENABLE0_P3_0                 , RULL(0x8000000008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_ENABLE0_P3_1                 , RULL(0x8000040007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_ENABLE0_P3_1                 , RULL(0x8000040008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_ENABLE0_P3_2                 , RULL(0x8000080007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_ENABLE0_P3_2                 , RULL(0x8000080008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_ENABLE0_P3_3                 , RULL(0x80000C0007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_ENABLE0_P3_3                 , RULL(0x80000C0008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_ENABLE0_P3_4                 , RULL(0x8000100007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_ENABLE0_P3_4                 , RULL(0x8000100008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0                   , RULL(0x800000010701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0                 , RULL(0x800000010701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0                 , RULL(0x800000010801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1                   , RULL(0x800004010701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1                 , RULL(0x800004010701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1                 , RULL(0x800004010801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2                   , RULL(0x800008010701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2                 , RULL(0x800008010701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2                 , RULL(0x800008010801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3                   , RULL(0x80000C010701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3                 , RULL(0x80000C010701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3                 , RULL(0x80000C010801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4                   , RULL(0x800010010701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4                 , RULL(0x800010010701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4                 , RULL(0x800010010801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_ENABLE1_P1_0                 , RULL(0x800000010701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_ENABLE1_P1_0                 , RULL(0x800000010801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_ENABLE1_P1_1                 , RULL(0x800004010701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_ENABLE1_P1_1                 , RULL(0x800004010801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_ENABLE1_P1_2                 , RULL(0x800008010701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_ENABLE1_P1_2                 , RULL(0x800008010801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_ENABLE1_P1_3                 , RULL(0x80000C010701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_ENABLE1_P1_3                 , RULL(0x80000C010801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DATA_BIT_ENABLE1_P1_4                 , RULL(0x800010010701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DATA_BIT_ENABLE1_P1_4                 , RULL(0x800010010801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_ENABLE1_P2_0                 , RULL(0x800000010701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_ENABLE1_P2_0                 , RULL(0x800000010801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_ENABLE1_P2_1                 , RULL(0x800004010701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_ENABLE1_P2_1                 , RULL(0x800004010801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_ENABLE1_P2_2                 , RULL(0x800008010701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_ENABLE1_P2_2                 , RULL(0x800008010801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_ENABLE1_P2_3                 , RULL(0x80000C010701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_ENABLE1_P2_3                 , RULL(0x80000C010801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DATA_BIT_ENABLE1_P2_4                 , RULL(0x800010010701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DATA_BIT_ENABLE1_P2_4                 , RULL(0x800010010801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_ENABLE1_P3_0                 , RULL(0x8000000107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_ENABLE1_P3_0                 , RULL(0x8000000108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_ENABLE1_P3_1                 , RULL(0x8000040107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_ENABLE1_P3_1                 , RULL(0x8000040108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_ENABLE1_P3_2                 , RULL(0x8000080107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_ENABLE1_P3_2                 , RULL(0x8000080108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_ENABLE1_P3_3                 , RULL(0x80000C0107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_ENABLE1_P3_3                 , RULL(0x80000C0108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DATA_BIT_ENABLE1_P3_4                 , RULL(0x8000100107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DATA_BIT_ENABLE1_P3_4                 , RULL(0x8000100108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0                       , RULL(0x800000A40701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DCD_CONTROL0_P0_0                     , RULL(0x800000A40701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DCD_CONTROL0_P0_0                     , RULL(0x800000A40801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1                       , RULL(0x800004A40701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DCD_CONTROL0_P0_1                     , RULL(0x800004A40701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DCD_CONTROL0_P0_1                     , RULL(0x800004A40801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2                       , RULL(0x800008A40701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DCD_CONTROL0_P0_2                     , RULL(0x800008A40701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DCD_CONTROL0_P0_2                     , RULL(0x800008A40801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3                       , RULL(0x80000CA40701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DCD_CONTROL0_P0_3                     , RULL(0x80000CA40701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DCD_CONTROL0_P0_3                     , RULL(0x80000CA40801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4                       , RULL(0x800010A40701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DCD_CONTROL0_P0_4                     , RULL(0x800010A40701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DCD_CONTROL0_P0_4                     , RULL(0x800010A40801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DCD_CONTROL0_P1_0                     , RULL(0x800000A40701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DCD_CONTROL0_P1_0                     , RULL(0x800000A40801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DCD_CONTROL0_P1_1                     , RULL(0x800004A40701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DCD_CONTROL0_P1_1                     , RULL(0x800004A40801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DCD_CONTROL0_P1_2                     , RULL(0x800008A40701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DCD_CONTROL0_P1_2                     , RULL(0x800008A40801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DCD_CONTROL0_P1_3                     , RULL(0x80000CA40701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DCD_CONTROL0_P1_3                     , RULL(0x80000CA40801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DCD_CONTROL0_P1_4                     , RULL(0x800010A40701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DCD_CONTROL0_P1_4                     , RULL(0x800010A40801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DCD_CONTROL0_P2_0                     , RULL(0x800000A40701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DCD_CONTROL0_P2_0                     , RULL(0x800000A40801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DCD_CONTROL0_P2_1                     , RULL(0x800004A40701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DCD_CONTROL0_P2_1                     , RULL(0x800004A40801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DCD_CONTROL0_P2_2                     , RULL(0x800008A40701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DCD_CONTROL0_P2_2                     , RULL(0x800008A40801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DCD_CONTROL0_P2_3                     , RULL(0x80000CA40701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DCD_CONTROL0_P2_3                     , RULL(0x80000CA40801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DCD_CONTROL0_P2_4                     , RULL(0x800010A40701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DCD_CONTROL0_P2_4                     , RULL(0x800010A40801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DCD_CONTROL0_P3_0                     , RULL(0x800000A407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DCD_CONTROL0_P3_0                     , RULL(0x800000A408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DCD_CONTROL0_P3_1                     , RULL(0x800004A407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DCD_CONTROL0_P3_1                     , RULL(0x800004A408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DCD_CONTROL0_P3_2                     , RULL(0x800008A407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DCD_CONTROL0_P3_2                     , RULL(0x800008A408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DCD_CONTROL0_P3_3                     , RULL(0x80000CA407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DCD_CONTROL0_P3_3                     , RULL(0x80000CA408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DCD_CONTROL0_P3_4                     , RULL(0x800010A407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DCD_CONTROL0_P3_4                     , RULL(0x800010A408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0                       , RULL(0x800000A50701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DCD_CONTROL1_P0_0                     , RULL(0x800000A50701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DCD_CONTROL1_P0_0                     , RULL(0x800000A50801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1                       , RULL(0x800004A50701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DCD_CONTROL1_P0_1                     , RULL(0x800004A50701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DCD_CONTROL1_P0_1                     , RULL(0x800004A50801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2                       , RULL(0x800008A50701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DCD_CONTROL1_P0_2                     , RULL(0x800008A50701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DCD_CONTROL1_P0_2                     , RULL(0x800008A50801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3                       , RULL(0x80000CA50701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DCD_CONTROL1_P0_3                     , RULL(0x80000CA50701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DCD_CONTROL1_P0_3                     , RULL(0x80000CA50801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4                       , RULL(0x800010A50701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DCD_CONTROL1_P0_4                     , RULL(0x800010A50701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DCD_CONTROL1_P0_4                     , RULL(0x800010A50801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DCD_CONTROL1_P1_0                     , RULL(0x800000A50701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DCD_CONTROL1_P1_0                     , RULL(0x800000A50801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DCD_CONTROL1_P1_1                     , RULL(0x800004A50701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DCD_CONTROL1_P1_1                     , RULL(0x800004A50801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DCD_CONTROL1_P1_2                     , RULL(0x800008A50701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DCD_CONTROL1_P1_2                     , RULL(0x800008A50801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DCD_CONTROL1_P1_3                     , RULL(0x80000CA50701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DCD_CONTROL1_P1_3                     , RULL(0x80000CA50801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DCD_CONTROL1_P1_4                     , RULL(0x800010A50701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DCD_CONTROL1_P1_4                     , RULL(0x800010A50801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DCD_CONTROL1_P2_0                     , RULL(0x800000A50701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DCD_CONTROL1_P2_0                     , RULL(0x800000A50801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DCD_CONTROL1_P2_1                     , RULL(0x800004A50701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DCD_CONTROL1_P2_1                     , RULL(0x800004A50801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DCD_CONTROL1_P2_2                     , RULL(0x800008A50701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DCD_CONTROL1_P2_2                     , RULL(0x800008A50801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DCD_CONTROL1_P2_3                     , RULL(0x80000CA50701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DCD_CONTROL1_P2_3                     , RULL(0x80000CA50801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DCD_CONTROL1_P2_4                     , RULL(0x800010A50701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DCD_CONTROL1_P2_4                     , RULL(0x800010A50801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DCD_CONTROL1_P3_0                     , RULL(0x800000A507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DCD_CONTROL1_P3_0                     , RULL(0x800000A508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DCD_CONTROL1_P3_1                     , RULL(0x800004A507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DCD_CONTROL1_P3_1                     , RULL(0x800004A508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DCD_CONTROL1_P3_2                     , RULL(0x800008A507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DCD_CONTROL1_P3_2                     , RULL(0x800008A508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DCD_CONTROL1_P3_3                     , RULL(0x80000CA507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DCD_CONTROL1_P3_3                     , RULL(0x80000CA508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DCD_CONTROL1_P3_4                     , RULL(0x800010A507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DCD_CONTROL1_P3_4                     , RULL(0x800010A508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0                          , RULL(0x8000000B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DEBUG_SEL_P0_0                        , RULL(0x8000000B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DEBUG_SEL_P0_0                        , RULL(0x8000000B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1                          , RULL(0x8000040B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DEBUG_SEL_P0_1                        , RULL(0x8000040B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DEBUG_SEL_P0_1                        , RULL(0x8000040B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2                          , RULL(0x8000080B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DEBUG_SEL_P0_2                        , RULL(0x8000080B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DEBUG_SEL_P0_2                        , RULL(0x8000080B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3                          , RULL(0x80000C0B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DEBUG_SEL_P0_3                        , RULL(0x80000C0B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DEBUG_SEL_P0_3                        , RULL(0x80000C0B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4                          , RULL(0x8000100B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DEBUG_SEL_P0_4                        , RULL(0x8000100B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DEBUG_SEL_P0_4                        , RULL(0x8000100B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DEBUG_SEL_P1_0                        , RULL(0x8000000B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DEBUG_SEL_P1_0                        , RULL(0x8000000B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DEBUG_SEL_P1_1                        , RULL(0x8000040B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DEBUG_SEL_P1_1                        , RULL(0x8000040B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DEBUG_SEL_P1_2                        , RULL(0x8000080B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DEBUG_SEL_P1_2                        , RULL(0x8000080B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DEBUG_SEL_P1_3                        , RULL(0x80000C0B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DEBUG_SEL_P1_3                        , RULL(0x80000C0B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DEBUG_SEL_P1_4                        , RULL(0x8000100B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DEBUG_SEL_P1_4                        , RULL(0x8000100B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DEBUG_SEL_P2_0                        , RULL(0x8000000B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DEBUG_SEL_P2_0                        , RULL(0x8000000B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DEBUG_SEL_P2_1                        , RULL(0x8000040B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DEBUG_SEL_P2_1                        , RULL(0x8000040B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DEBUG_SEL_P2_2                        , RULL(0x8000080B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DEBUG_SEL_P2_2                        , RULL(0x8000080B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DEBUG_SEL_P2_3                        , RULL(0x80000C0B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DEBUG_SEL_P2_3                        , RULL(0x80000C0B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DEBUG_SEL_P2_4                        , RULL(0x8000100B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DEBUG_SEL_P2_4                        , RULL(0x8000100B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DEBUG_SEL_P3_0                        , RULL(0x8000000B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DEBUG_SEL_P3_0                        , RULL(0x8000000B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DEBUG_SEL_P3_1                        , RULL(0x8000040B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DEBUG_SEL_P3_1                        , RULL(0x8000040B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DEBUG_SEL_P3_2                        , RULL(0x8000080B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DEBUG_SEL_P3_2                        , RULL(0x8000080B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DEBUG_SEL_P3_3                        , RULL(0x80000C0B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DEBUG_SEL_P3_3                        , RULL(0x80000C0B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DEBUG_SEL_P3_4                        , RULL(0x8000100B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DEBUG_SEL_P3_4                        , RULL(0x8000100B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0                 , RULL(0x8000006F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0               , RULL(0x8000006F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0               , RULL(0x8000006F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1                 , RULL(0x8000046F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1               , RULL(0x8000046F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1               , RULL(0x8000046F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2                 , RULL(0x8000086F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2               , RULL(0x8000086F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2               , RULL(0x8000086F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3                 , RULL(0x80000C6F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3               , RULL(0x80000C6F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3               , RULL(0x80000C6F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4                 , RULL(0x8000106F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4               , RULL(0x8000106F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4               , RULL(0x8000106F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_0               , RULL(0x8000006F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_0               , RULL(0x8000006F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_1               , RULL(0x8000046F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_1               , RULL(0x8000046F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_2               , RULL(0x8000086F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_2               , RULL(0x8000086F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_3               , RULL(0x80000C6F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_3               , RULL(0x80000C6F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_4               , RULL(0x8000106F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P1_4               , RULL(0x8000106F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_0               , RULL(0x8000006F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_0               , RULL(0x8000006F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_1               , RULL(0x8000046F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_1               , RULL(0x8000046F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_2               , RULL(0x8000086F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_2               , RULL(0x8000086F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_3               , RULL(0x80000C6F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_3               , RULL(0x80000C6F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_4               , RULL(0x8000106F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P2_4               , RULL(0x8000106F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_0               , RULL(0x8000006F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_0               , RULL(0x8000006F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_1               , RULL(0x8000046F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_1               , RULL(0x8000046F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_2               , RULL(0x8000086F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_2               , RULL(0x8000086F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_3               , RULL(0x80000C6F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_3               , RULL(0x80000C6F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_4               , RULL(0x8000106F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P3_4               , RULL(0x8000106F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0                        , RULL(0x800000080701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DFT_DIG_EYE_P0_0                      , RULL(0x800000080701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DFT_DIG_EYE_P0_0                      , RULL(0x800000080801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1                        , RULL(0x800004080701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DFT_DIG_EYE_P0_1                      , RULL(0x800004080701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DFT_DIG_EYE_P0_1                      , RULL(0x800004080801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2                        , RULL(0x800008080701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DFT_DIG_EYE_P0_2                      , RULL(0x800008080701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DFT_DIG_EYE_P0_2                      , RULL(0x800008080801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3                        , RULL(0x80000C080701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DFT_DIG_EYE_P0_3                      , RULL(0x80000C080701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DFT_DIG_EYE_P0_3                      , RULL(0x80000C080801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4                        , RULL(0x800010080701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DFT_DIG_EYE_P0_4                      , RULL(0x800010080701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DFT_DIG_EYE_P0_4                      , RULL(0x800010080801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DFT_DIG_EYE_P1_0                      , RULL(0x800000080701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DFT_DIG_EYE_P1_0                      , RULL(0x800000080801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DFT_DIG_EYE_P1_1                      , RULL(0x800004080701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DFT_DIG_EYE_P1_1                      , RULL(0x800004080801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DFT_DIG_EYE_P1_2                      , RULL(0x800008080701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DFT_DIG_EYE_P1_2                      , RULL(0x800008080801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DFT_DIG_EYE_P1_3                      , RULL(0x80000C080701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DFT_DIG_EYE_P1_3                      , RULL(0x80000C080801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DFT_DIG_EYE_P1_4                      , RULL(0x800010080701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DFT_DIG_EYE_P1_4                      , RULL(0x800010080801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DFT_DIG_EYE_P2_0                      , RULL(0x800000080701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DFT_DIG_EYE_P2_0                      , RULL(0x800000080801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DFT_DIG_EYE_P2_1                      , RULL(0x800004080701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DFT_DIG_EYE_P2_1                      , RULL(0x800004080801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DFT_DIG_EYE_P2_2                      , RULL(0x800008080701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DFT_DIG_EYE_P2_2                      , RULL(0x800008080801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DFT_DIG_EYE_P2_3                      , RULL(0x80000C080701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DFT_DIG_EYE_P2_3                      , RULL(0x80000C080801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DFT_DIG_EYE_P2_4                      , RULL(0x800010080701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DFT_DIG_EYE_P2_4                      , RULL(0x800010080801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DFT_DIG_EYE_P3_0                      , RULL(0x8000000807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DFT_DIG_EYE_P3_0                      , RULL(0x8000000808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DFT_DIG_EYE_P3_1                      , RULL(0x8000040807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DFT_DIG_EYE_P3_1                      , RULL(0x8000040808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DFT_DIG_EYE_P3_2                      , RULL(0x8000080807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DFT_DIG_EYE_P3_2                      , RULL(0x8000080808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DFT_DIG_EYE_P3_3                      , RULL(0x80000C0807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DFT_DIG_EYE_P3_3                      , RULL(0x80000C0808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DFT_DIG_EYE_P3_4                      , RULL(0x8000100807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DFT_DIG_EYE_P3_4                      , RULL(0x8000100808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0                    , RULL(0x8000001D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0                  , RULL(0x8000001D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0                  , RULL(0x8000001D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1                    , RULL(0x8000041D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1                  , RULL(0x8000041D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1                  , RULL(0x8000041D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2                    , RULL(0x8000081D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2                  , RULL(0x8000081D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2                  , RULL(0x8000081D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3                    , RULL(0x80000C1D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3                  , RULL(0x80000C1D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3                  , RULL(0x80000C1D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4                    , RULL(0x8000101D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4                  , RULL(0x8000101D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4                  , RULL(0x8000101D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DFT_WRAP_STATUS_P1_0                  , RULL(0x8000001D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DFT_WRAP_STATUS_P1_0                  , RULL(0x8000001D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DFT_WRAP_STATUS_P1_1                  , RULL(0x8000041D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DFT_WRAP_STATUS_P1_1                  , RULL(0x8000041D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DFT_WRAP_STATUS_P1_2                  , RULL(0x8000081D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DFT_WRAP_STATUS_P1_2                  , RULL(0x8000081D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DFT_WRAP_STATUS_P1_3                  , RULL(0x80000C1D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DFT_WRAP_STATUS_P1_3                  , RULL(0x80000C1D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DFT_WRAP_STATUS_P1_4                  , RULL(0x8000101D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DFT_WRAP_STATUS_P1_4                  , RULL(0x8000101D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DFT_WRAP_STATUS_P2_0                  , RULL(0x8000001D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DFT_WRAP_STATUS_P2_0                  , RULL(0x8000001D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DFT_WRAP_STATUS_P2_1                  , RULL(0x8000041D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DFT_WRAP_STATUS_P2_1                  , RULL(0x8000041D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DFT_WRAP_STATUS_P2_2                  , RULL(0x8000081D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DFT_WRAP_STATUS_P2_2                  , RULL(0x8000081D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DFT_WRAP_STATUS_P2_3                  , RULL(0x80000C1D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DFT_WRAP_STATUS_P2_3                  , RULL(0x80000C1D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DFT_WRAP_STATUS_P2_4                  , RULL(0x8000101D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DFT_WRAP_STATUS_P2_4                  , RULL(0x8000101D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DFT_WRAP_STATUS_P3_0                  , RULL(0x8000001D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DFT_WRAP_STATUS_P3_0                  , RULL(0x8000001D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DFT_WRAP_STATUS_P3_1                  , RULL(0x8000041D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DFT_WRAP_STATUS_P3_1                  , RULL(0x8000041D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DFT_WRAP_STATUS_P3_2                  , RULL(0x8000081D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DFT_WRAP_STATUS_P3_2                  , RULL(0x8000081D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DFT_WRAP_STATUS_P3_3                  , RULL(0x80000C1D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DFT_WRAP_STATUS_P3_3                  , RULL(0x80000C1D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DFT_WRAP_STATUS_P3_4                  , RULL(0x8000101D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DFT_WRAP_STATUS_P3_4                  , RULL(0x8000101D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0                          , RULL(0x800000240701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_CNTL0_P0_0                        , RULL(0x800000240701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_CNTL0_P0_0                        , RULL(0x800000240801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1                          , RULL(0x800004240701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_CNTL0_P0_1                        , RULL(0x800004240701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_CNTL0_P0_1                        , RULL(0x800004240801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2                          , RULL(0x800008240701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_CNTL0_P0_2                        , RULL(0x800008240701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_CNTL0_P0_2                        , RULL(0x800008240801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3                          , RULL(0x80000C240701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_CNTL0_P0_3                        , RULL(0x80000C240701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_CNTL0_P0_3                        , RULL(0x80000C240801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4                          , RULL(0x800010240701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_CNTL0_P0_4                        , RULL(0x800010240701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_CNTL0_P0_4                        , RULL(0x800010240801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_CNTL0_P1_0                        , RULL(0x800000240701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_CNTL0_P1_0                        , RULL(0x800000240801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_CNTL0_P1_1                        , RULL(0x800004240701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_CNTL0_P1_1                        , RULL(0x800004240801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_CNTL0_P1_2                        , RULL(0x800008240701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_CNTL0_P1_2                        , RULL(0x800008240801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_CNTL0_P1_3                        , RULL(0x80000C240701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_CNTL0_P1_3                        , RULL(0x80000C240801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_CNTL0_P1_4                        , RULL(0x800010240701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_CNTL0_P1_4                        , RULL(0x800010240801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_CNTL0_P2_0                        , RULL(0x800000240701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_CNTL0_P2_0                        , RULL(0x800000240801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_CNTL0_P2_1                        , RULL(0x800004240701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_CNTL0_P2_1                        , RULL(0x800004240801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_CNTL0_P2_2                        , RULL(0x800008240701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_CNTL0_P2_2                        , RULL(0x800008240801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_CNTL0_P2_3                        , RULL(0x80000C240701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_CNTL0_P2_3                        , RULL(0x80000C240801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_CNTL0_P2_4                        , RULL(0x800010240701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_CNTL0_P2_4                        , RULL(0x800010240801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_CNTL0_P3_0                        , RULL(0x8000002407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_CNTL0_P3_0                        , RULL(0x8000002408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_CNTL0_P3_1                        , RULL(0x8000042407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_CNTL0_P3_1                        , RULL(0x8000042408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_CNTL0_P3_2                        , RULL(0x8000082407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_CNTL0_P3_2                        , RULL(0x8000082408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_CNTL0_P3_3                        , RULL(0x80000C2407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_CNTL0_P3_3                        , RULL(0x80000C2408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_CNTL0_P3_4                        , RULL(0x8000102407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_CNTL0_P3_4                        , RULL(0x8000102408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0                          , RULL(0x800000250701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_CNTL1_P0_0                        , RULL(0x800000250701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_CNTL1_P0_0                        , RULL(0x800000250801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1                          , RULL(0x800004250701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_CNTL1_P0_1                        , RULL(0x800004250701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_CNTL1_P0_1                        , RULL(0x800004250801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2                          , RULL(0x800008250701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_CNTL1_P0_2                        , RULL(0x800008250701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_CNTL1_P0_2                        , RULL(0x800008250801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3                          , RULL(0x80000C250701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_CNTL1_P0_3                        , RULL(0x80000C250701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_CNTL1_P0_3                        , RULL(0x80000C250801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4                          , RULL(0x800010250701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_CNTL1_P0_4                        , RULL(0x800010250701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_CNTL1_P0_4                        , RULL(0x800010250801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_CNTL1_P1_0                        , RULL(0x800000250701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_CNTL1_P1_0                        , RULL(0x800000250801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_CNTL1_P1_1                        , RULL(0x800004250701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_CNTL1_P1_1                        , RULL(0x800004250801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_CNTL1_P1_2                        , RULL(0x800008250701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_CNTL1_P1_2                        , RULL(0x800008250801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_CNTL1_P1_3                        , RULL(0x80000C250701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_CNTL1_P1_3                        , RULL(0x80000C250801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_CNTL1_P1_4                        , RULL(0x800010250701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_CNTL1_P1_4                        , RULL(0x800010250801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_CNTL1_P2_0                        , RULL(0x800000250701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_CNTL1_P2_0                        , RULL(0x800000250801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_CNTL1_P2_1                        , RULL(0x800004250701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_CNTL1_P2_1                        , RULL(0x800004250801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_CNTL1_P2_2                        , RULL(0x800008250701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_CNTL1_P2_2                        , RULL(0x800008250801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_CNTL1_P2_3                        , RULL(0x80000C250701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_CNTL1_P2_3                        , RULL(0x80000C250801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_CNTL1_P2_4                        , RULL(0x800010250701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_CNTL1_P2_4                        , RULL(0x800010250801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_CNTL1_P3_0                        , RULL(0x8000002507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_CNTL1_P3_0                        , RULL(0x8000002508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_CNTL1_P3_1                        , RULL(0x8000042507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_CNTL1_P3_1                        , RULL(0x8000042508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_CNTL1_P3_2                        , RULL(0x8000082507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_CNTL1_P3_2                        , RULL(0x8000082508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_CNTL1_P3_3                        , RULL(0x80000C2507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_CNTL1_P3_3                        , RULL(0x80000C2508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_CNTL1_P3_4                        , RULL(0x8000102507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_CNTL1_P3_4                        , RULL(0x8000102508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0                        , RULL(0x800000770701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_CONFIG1_P0_0                      , RULL(0x800000770701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_CONFIG1_P0_0                      , RULL(0x800000770801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1                        , RULL(0x800004770701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_CONFIG1_P0_1                      , RULL(0x800004770701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_CONFIG1_P0_1                      , RULL(0x800004770801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2                        , RULL(0x800008770701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_CONFIG1_P0_2                      , RULL(0x800008770701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_CONFIG1_P0_2                      , RULL(0x800008770801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3                        , RULL(0x80000C770701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_CONFIG1_P0_3                      , RULL(0x80000C770701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_CONFIG1_P0_3                      , RULL(0x80000C770801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4                        , RULL(0x800010770701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_CONFIG1_P0_4                      , RULL(0x800010770701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_CONFIG1_P0_4                      , RULL(0x800010770801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_CONFIG1_P1_0                      , RULL(0x800000770701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_CONFIG1_P1_0                      , RULL(0x800000770801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_CONFIG1_P1_1                      , RULL(0x800004770701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_CONFIG1_P1_1                      , RULL(0x800004770801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_CONFIG1_P1_2                      , RULL(0x800008770701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_CONFIG1_P1_2                      , RULL(0x800008770801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_CONFIG1_P1_3                      , RULL(0x80000C770701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_CONFIG1_P1_3                      , RULL(0x80000C770801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_CONFIG1_P1_4                      , RULL(0x800010770701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_CONFIG1_P1_4                      , RULL(0x800010770801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_CONFIG1_P2_0                      , RULL(0x800000770701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_CONFIG1_P2_0                      , RULL(0x800000770801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_CONFIG1_P2_1                      , RULL(0x800004770701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_CONFIG1_P2_1                      , RULL(0x800004770801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_CONFIG1_P2_2                      , RULL(0x800008770701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_CONFIG1_P2_2                      , RULL(0x800008770801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_CONFIG1_P2_3                      , RULL(0x80000C770701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_CONFIG1_P2_3                      , RULL(0x80000C770801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_CONFIG1_P2_4                      , RULL(0x800010770701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_CONFIG1_P2_4                      , RULL(0x800010770801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_CONFIG1_P3_0                      , RULL(0x8000007707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_CONFIG1_P3_0                      , RULL(0x8000007708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_CONFIG1_P3_1                      , RULL(0x8000047707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_CONFIG1_P3_1                      , RULL(0x8000047708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_CONFIG1_P3_2                      , RULL(0x8000087707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_CONFIG1_P3_2                      , RULL(0x8000087708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_CONFIG1_P3_3                      , RULL(0x80000C7707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_CONFIG1_P3_3                      , RULL(0x80000C7708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_CONFIG1_P3_4                      , RULL(0x8000107707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_CONFIG1_P3_4                      , RULL(0x8000107708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0                     , RULL(0x800000260701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0                   , RULL(0x800000260701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0                   , RULL(0x800000260801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1                     , RULL(0x800004260701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1                   , RULL(0x800004260701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1                   , RULL(0x800004260801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2                     , RULL(0x800008260701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2                   , RULL(0x800008260701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2                   , RULL(0x800008260801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3                     , RULL(0x80000C260701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3                   , RULL(0x80000C260701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3                   , RULL(0x80000C260801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4                     , RULL(0x800010260701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4                   , RULL(0x800010260701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4                   , RULL(0x800010260801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_LOWER0_P1_0                   , RULL(0x800000260701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_LOWER0_P1_0                   , RULL(0x800000260801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_LOWER0_P1_1                   , RULL(0x800004260701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_LOWER0_P1_1                   , RULL(0x800004260801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_LOWER0_P1_2                   , RULL(0x800008260701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_LOWER0_P1_2                   , RULL(0x800008260801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_LOWER0_P1_3                   , RULL(0x80000C260701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_LOWER0_P1_3                   , RULL(0x80000C260801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_LOWER0_P1_4                   , RULL(0x800010260701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_LOWER0_P1_4                   , RULL(0x800010260801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_LOWER0_P2_0                   , RULL(0x800000260701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_LOWER0_P2_0                   , RULL(0x800000260801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_LOWER0_P2_1                   , RULL(0x800004260701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_LOWER0_P2_1                   , RULL(0x800004260801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_LOWER0_P2_2                   , RULL(0x800008260701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_LOWER0_P2_2                   , RULL(0x800008260801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_LOWER0_P2_3                   , RULL(0x80000C260701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_LOWER0_P2_3                   , RULL(0x80000C260801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_LOWER0_P2_4                   , RULL(0x800010260701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_LOWER0_P2_4                   , RULL(0x800010260801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_LOWER0_P3_0                   , RULL(0x8000002607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_LOWER0_P3_0                   , RULL(0x8000002608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_LOWER0_P3_1                   , RULL(0x8000042607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_LOWER0_P3_1                   , RULL(0x8000042608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_LOWER0_P3_2                   , RULL(0x8000082607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_LOWER0_P3_2                   , RULL(0x8000082608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_LOWER0_P3_3                   , RULL(0x80000C2607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_LOWER0_P3_3                   , RULL(0x80000C2608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_LOWER0_P3_4                   , RULL(0x8000102607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_LOWER0_P3_4                   , RULL(0x8000102608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0                     , RULL(0x800000270701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0                   , RULL(0x800000270701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0                   , RULL(0x800000270801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1                     , RULL(0x800004270701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1                   , RULL(0x800004270701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1                   , RULL(0x800004270801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2                     , RULL(0x800008270701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2                   , RULL(0x800008270701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2                   , RULL(0x800008270801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3                     , RULL(0x80000C270701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3                   , RULL(0x80000C270701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3                   , RULL(0x80000C270801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4                     , RULL(0x800010270701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4                   , RULL(0x800010270701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4                   , RULL(0x800010270801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_LOWER1_P1_0                   , RULL(0x800000270701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_LOWER1_P1_0                   , RULL(0x800000270801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_LOWER1_P1_1                   , RULL(0x800004270701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_LOWER1_P1_1                   , RULL(0x800004270801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_LOWER1_P1_2                   , RULL(0x800008270701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_LOWER1_P1_2                   , RULL(0x800008270801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_LOWER1_P1_3                   , RULL(0x80000C270701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_LOWER1_P1_3                   , RULL(0x80000C270801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_LOWER1_P1_4                   , RULL(0x800010270701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_LOWER1_P1_4                   , RULL(0x800010270801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_LOWER1_P2_0                   , RULL(0x800000270701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_LOWER1_P2_0                   , RULL(0x800000270801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_LOWER1_P2_1                   , RULL(0x800004270701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_LOWER1_P2_1                   , RULL(0x800004270801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_LOWER1_P2_2                   , RULL(0x800008270701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_LOWER1_P2_2                   , RULL(0x800008270801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_LOWER1_P2_3                   , RULL(0x80000C270701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_LOWER1_P2_3                   , RULL(0x80000C270801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_LOWER1_P2_4                   , RULL(0x800010270701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_LOWER1_P2_4                   , RULL(0x800010270801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_LOWER1_P3_0                   , RULL(0x8000002707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_LOWER1_P3_0                   , RULL(0x8000002708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_LOWER1_P3_1                   , RULL(0x8000042707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_LOWER1_P3_1                   , RULL(0x8000042708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_LOWER1_P3_2                   , RULL(0x8000082707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_LOWER1_P3_2                   , RULL(0x8000082708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_LOWER1_P3_3                   , RULL(0x80000C2707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_LOWER1_P3_3                   , RULL(0x80000C2708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_LOWER1_P3_4                   , RULL(0x8000102707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_LOWER1_P3_4                   , RULL(0x8000102708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0                     , RULL(0x800000280701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0                   , RULL(0x800000280701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0                   , RULL(0x800000280801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1                     , RULL(0x800004280701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1                   , RULL(0x800004280701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1                   , RULL(0x800004280801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2                     , RULL(0x800008280701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2                   , RULL(0x800008280701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2                   , RULL(0x800008280801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3                     , RULL(0x80000C280701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3                   , RULL(0x80000C280701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3                   , RULL(0x80000C280801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4                     , RULL(0x800010280701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4                   , RULL(0x800010280701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4                   , RULL(0x800010280801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_UPPER0_P1_0                   , RULL(0x800000280701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_UPPER0_P1_0                   , RULL(0x800000280801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_UPPER0_P1_1                   , RULL(0x800004280701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_UPPER0_P1_1                   , RULL(0x800004280801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_UPPER0_P1_2                   , RULL(0x800008280701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_UPPER0_P1_2                   , RULL(0x800008280801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_UPPER0_P1_3                   , RULL(0x80000C280701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_UPPER0_P1_3                   , RULL(0x80000C280801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_UPPER0_P1_4                   , RULL(0x800010280701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_UPPER0_P1_4                   , RULL(0x800010280801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_UPPER0_P2_0                   , RULL(0x800000280701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_UPPER0_P2_0                   , RULL(0x800000280801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_UPPER0_P2_1                   , RULL(0x800004280701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_UPPER0_P2_1                   , RULL(0x800004280801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_UPPER0_P2_2                   , RULL(0x800008280701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_UPPER0_P2_2                   , RULL(0x800008280801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_UPPER0_P2_3                   , RULL(0x80000C280701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_UPPER0_P2_3                   , RULL(0x80000C280801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_UPPER0_P2_4                   , RULL(0x800010280701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_UPPER0_P2_4                   , RULL(0x800010280801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_UPPER0_P3_0                   , RULL(0x8000002807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_UPPER0_P3_0                   , RULL(0x8000002808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_UPPER0_P3_1                   , RULL(0x8000042807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_UPPER0_P3_1                   , RULL(0x8000042808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_UPPER0_P3_2                   , RULL(0x8000082807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_UPPER0_P3_2                   , RULL(0x8000082808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_UPPER0_P3_3                   , RULL(0x80000C2807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_UPPER0_P3_3                   , RULL(0x80000C2808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_UPPER0_P3_4                   , RULL(0x8000102807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_UPPER0_P3_4                   , RULL(0x8000102808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0                     , RULL(0x800000290701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0                   , RULL(0x800000290701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0                   , RULL(0x800000290801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1                     , RULL(0x800004290701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1                   , RULL(0x800004290701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1                   , RULL(0x800004290801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2                     , RULL(0x800008290701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2                   , RULL(0x800008290701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2                   , RULL(0x800008290801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3                     , RULL(0x80000C290701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3                   , RULL(0x80000C290701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3                   , RULL(0x80000C290801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4                     , RULL(0x800010290701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4                   , RULL(0x800010290701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4                   , RULL(0x800010290801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_UPPER1_P1_0                   , RULL(0x800000290701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_UPPER1_P1_0                   , RULL(0x800000290801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_UPPER1_P1_1                   , RULL(0x800004290701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_UPPER1_P1_1                   , RULL(0x800004290801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_UPPER1_P1_2                   , RULL(0x800008290701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_UPPER1_P1_2                   , RULL(0x800008290801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_UPPER1_P1_3                   , RULL(0x80000C290701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_UPPER1_P1_3                   , RULL(0x80000C290801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_DAC_UPPER1_P1_4                   , RULL(0x800010290701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_DAC_UPPER1_P1_4                   , RULL(0x800010290801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_UPPER1_P2_0                   , RULL(0x800000290701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_UPPER1_P2_0                   , RULL(0x800000290801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_UPPER1_P2_1                   , RULL(0x800004290701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_UPPER1_P2_1                   , RULL(0x800004290801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_UPPER1_P2_2                   , RULL(0x800008290701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_UPPER1_P2_2                   , RULL(0x800008290801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_UPPER1_P2_3                   , RULL(0x80000C290701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_UPPER1_P2_3                   , RULL(0x80000C290801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_DAC_UPPER1_P2_4                   , RULL(0x800010290701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_DAC_UPPER1_P2_4                   , RULL(0x800010290801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_UPPER1_P3_0                   , RULL(0x8000002907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_UPPER1_P3_0                   , RULL(0x8000002908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_UPPER1_P3_1                   , RULL(0x8000042907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_UPPER1_P3_1                   , RULL(0x8000042908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_UPPER1_P3_2                   , RULL(0x8000082907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_UPPER1_P3_2                   , RULL(0x8000082908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_UPPER1_P3_3                   , RULL(0x80000C2907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_UPPER1_P3_3                   , RULL(0x80000C2908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_DAC_UPPER1_P3_4                   , RULL(0x8000102907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_DAC_UPPER1_P3_4                   , RULL(0x8000102908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0                         , RULL(0x800000AC0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_EXTRA0_P0_0                       , RULL(0x800000AC0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_EXTRA0_P0_0                       , RULL(0x800000AC0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1                         , RULL(0x800004AC0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_EXTRA0_P0_1                       , RULL(0x800004AC0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_EXTRA0_P0_1                       , RULL(0x800004AC0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2                         , RULL(0x800008AC0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_EXTRA0_P0_2                       , RULL(0x800008AC0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_EXTRA0_P0_2                       , RULL(0x800008AC0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3                         , RULL(0x80000CAC0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_EXTRA0_P0_3                       , RULL(0x80000CAC0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_EXTRA0_P0_3                       , RULL(0x80000CAC0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4                         , RULL(0x800010AC0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_EXTRA0_P0_4                       , RULL(0x800010AC0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_EXTRA0_P0_4                       , RULL(0x800010AC0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_EXTRA0_P1_0                       , RULL(0x800000AC0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_EXTRA0_P1_0                       , RULL(0x800000AC0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_EXTRA0_P1_1                       , RULL(0x800004AC0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_EXTRA0_P1_1                       , RULL(0x800004AC0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_EXTRA0_P1_2                       , RULL(0x800008AC0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_EXTRA0_P1_2                       , RULL(0x800008AC0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_EXTRA0_P1_3                       , RULL(0x80000CAC0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_EXTRA0_P1_3                       , RULL(0x80000CAC0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_EXTRA0_P1_4                       , RULL(0x800010AC0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_EXTRA0_P1_4                       , RULL(0x800010AC0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_EXTRA0_P2_0                       , RULL(0x800000AC0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_EXTRA0_P2_0                       , RULL(0x800000AC0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_EXTRA0_P2_1                       , RULL(0x800004AC0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_EXTRA0_P2_1                       , RULL(0x800004AC0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_EXTRA0_P2_2                       , RULL(0x800008AC0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_EXTRA0_P2_2                       , RULL(0x800008AC0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_EXTRA0_P2_3                       , RULL(0x80000CAC0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_EXTRA0_P2_3                       , RULL(0x80000CAC0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_EXTRA0_P2_4                       , RULL(0x800010AC0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_EXTRA0_P2_4                       , RULL(0x800010AC0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_EXTRA0_P3_0                       , RULL(0x800000AC07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_EXTRA0_P3_0                       , RULL(0x800000AC08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_EXTRA0_P3_1                       , RULL(0x800004AC07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_EXTRA0_P3_1                       , RULL(0x800004AC08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_EXTRA0_P3_2                       , RULL(0x800008AC07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_EXTRA0_P3_2                       , RULL(0x800008AC08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_EXTRA0_P3_3                       , RULL(0x80000CAC07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_EXTRA0_P3_3                       , RULL(0x80000CAC08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_EXTRA0_P3_4                       , RULL(0x800010AC07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_EXTRA0_P3_4                       , RULL(0x800010AC08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0                         , RULL(0x800000AD0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_EXTRA1_P0_0                       , RULL(0x800000AD0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_EXTRA1_P0_0                       , RULL(0x800000AD0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1                         , RULL(0x800004AD0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_EXTRA1_P0_1                       , RULL(0x800004AD0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_EXTRA1_P0_1                       , RULL(0x800004AD0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2                         , RULL(0x800008AD0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_EXTRA1_P0_2                       , RULL(0x800008AD0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_EXTRA1_P0_2                       , RULL(0x800008AD0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3                         , RULL(0x80000CAD0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_EXTRA1_P0_3                       , RULL(0x80000CAD0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_EXTRA1_P0_3                       , RULL(0x80000CAD0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4                         , RULL(0x800010AD0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_EXTRA1_P0_4                       , RULL(0x800010AD0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_EXTRA1_P0_4                       , RULL(0x800010AD0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_EXTRA1_P1_0                       , RULL(0x800000AD0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_EXTRA1_P1_0                       , RULL(0x800000AD0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_EXTRA1_P1_1                       , RULL(0x800004AD0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_EXTRA1_P1_1                       , RULL(0x800004AD0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_EXTRA1_P1_2                       , RULL(0x800008AD0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_EXTRA1_P1_2                       , RULL(0x800008AD0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_EXTRA1_P1_3                       , RULL(0x80000CAD0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_EXTRA1_P1_3                       , RULL(0x80000CAD0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_EXTRA1_P1_4                       , RULL(0x800010AD0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_EXTRA1_P1_4                       , RULL(0x800010AD0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_EXTRA1_P2_0                       , RULL(0x800000AD0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_EXTRA1_P2_0                       , RULL(0x800000AD0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_EXTRA1_P2_1                       , RULL(0x800004AD0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_EXTRA1_P2_1                       , RULL(0x800004AD0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_EXTRA1_P2_2                       , RULL(0x800008AD0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_EXTRA1_P2_2                       , RULL(0x800008AD0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_EXTRA1_P2_3                       , RULL(0x80000CAD0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_EXTRA1_P2_3                       , RULL(0x80000CAD0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_EXTRA1_P2_4                       , RULL(0x800010AD0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_EXTRA1_P2_4                       , RULL(0x800010AD0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_EXTRA1_P3_0                       , RULL(0x800000AD07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_EXTRA1_P3_0                       , RULL(0x800000AD08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_EXTRA1_P3_1                       , RULL(0x800004AD07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_EXTRA1_P3_1                       , RULL(0x800004AD08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_EXTRA1_P3_2                       , RULL(0x800008AD07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_EXTRA1_P3_2                       , RULL(0x800008AD08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_EXTRA1_P3_3                       , RULL(0x80000CAD07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_EXTRA1_P3_3                       , RULL(0x80000CAD08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_EXTRA1_P3_4                       , RULL(0x800010AD07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_EXTRA1_P3_4                       , RULL(0x800010AD08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0              , RULL(0x800000A80701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0            , RULL(0x800000A80701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0            , RULL(0x800000A80801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1              , RULL(0x800004A80701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1            , RULL(0x800004A80701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1            , RULL(0x800004A80801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2              , RULL(0x800008A80701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2            , RULL(0x800008A80701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2            , RULL(0x800008A80801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3              , RULL(0x80000CA80701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3            , RULL(0x80000CA80701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3            , RULL(0x80000CA80801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4              , RULL(0x800010A80701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4            , RULL(0x800010A80701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4            , RULL(0x800010A80801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_0            , RULL(0x800000A80701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_0            , RULL(0x800000A80801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_1            , RULL(0x800004A80701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_1            , RULL(0x800004A80801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_2            , RULL(0x800008A80701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_2            , RULL(0x800008A80801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_3            , RULL(0x80000CA80701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_3            , RULL(0x80000CA80801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_4            , RULL(0x800010A80701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P1_4            , RULL(0x800010A80801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_0            , RULL(0x800000A80701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_0            , RULL(0x800000A80801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_1            , RULL(0x800004A80701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_1            , RULL(0x800004A80801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_2            , RULL(0x800008A80701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_2            , RULL(0x800008A80801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_3            , RULL(0x80000CA80701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_3            , RULL(0x80000CA80801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_4            , RULL(0x800010A80701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P2_4            , RULL(0x800010A80801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_0            , RULL(0x800000A807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_0            , RULL(0x800000A808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_1            , RULL(0x800004A807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_1            , RULL(0x800004A808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_2            , RULL(0x800008A807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_2            , RULL(0x800008A808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_3            , RULL(0x80000CA807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_3            , RULL(0x80000CA808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_4            , RULL(0x800010A807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P3_4            , RULL(0x800010A808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0              , RULL(0x800000A90701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0            , RULL(0x800000A90701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0            , RULL(0x800000A90801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1              , RULL(0x800004A90701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1            , RULL(0x800004A90701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1            , RULL(0x800004A90801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2              , RULL(0x800008A90701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2            , RULL(0x800008A90701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2            , RULL(0x800008A90801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3              , RULL(0x80000CA90701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3            , RULL(0x80000CA90701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3            , RULL(0x80000CA90801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4              , RULL(0x800010A90701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4            , RULL(0x800010A90701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4            , RULL(0x800010A90801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_0            , RULL(0x800000A90701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_0            , RULL(0x800000A90801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_1            , RULL(0x800004A90701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_1            , RULL(0x800004A90801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_2            , RULL(0x800008A90701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_2            , RULL(0x800008A90801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_3            , RULL(0x80000CA90701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_3            , RULL(0x80000CA90801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_4            , RULL(0x800010A90701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P1_4            , RULL(0x800010A90801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_0            , RULL(0x800000A90701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_0            , RULL(0x800000A90801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_1            , RULL(0x800004A90701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_1            , RULL(0x800004A90801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_2            , RULL(0x800008A90701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_2            , RULL(0x800008A90801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_3            , RULL(0x80000CA90701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_3            , RULL(0x80000CA90801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_4            , RULL(0x800010A90701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P2_4            , RULL(0x800010A90801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_0            , RULL(0x800000A907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_0            , RULL(0x800000A908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_1            , RULL(0x800004A907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_1            , RULL(0x800004A908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_2            , RULL(0x800008A907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_2            , RULL(0x800008A908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_3            , RULL(0x80000CA907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_3            , RULL(0x80000CA908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_4            , RULL(0x800010A907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P3_4            , RULL(0x800010A908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0              , RULL(0x800000AA0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0            , RULL(0x800000AA0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0            , RULL(0x800000AA0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1              , RULL(0x800004AA0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1            , RULL(0x800004AA0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1            , RULL(0x800004AA0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2              , RULL(0x800008AA0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2            , RULL(0x800008AA0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2            , RULL(0x800008AA0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3              , RULL(0x80000CAA0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3            , RULL(0x80000CAA0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3            , RULL(0x80000CAA0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4              , RULL(0x800010AA0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4            , RULL(0x800010AA0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4            , RULL(0x800010AA0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_0            , RULL(0x800000AA0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_0            , RULL(0x800000AA0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_1            , RULL(0x800004AA0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_1            , RULL(0x800004AA0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_2            , RULL(0x800008AA0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_2            , RULL(0x800008AA0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_3            , RULL(0x80000CAA0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_3            , RULL(0x80000CAA0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_4            , RULL(0x800010AA0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P1_4            , RULL(0x800010AA0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_0            , RULL(0x800000AA0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_0            , RULL(0x800000AA0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_1            , RULL(0x800004AA0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_1            , RULL(0x800004AA0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_2            , RULL(0x800008AA0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_2            , RULL(0x800008AA0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_3            , RULL(0x80000CAA0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_3            , RULL(0x80000CAA0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_4            , RULL(0x800010AA0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P2_4            , RULL(0x800010AA0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_0            , RULL(0x800000AA07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_0            , RULL(0x800000AA08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_1            , RULL(0x800004AA07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_1            , RULL(0x800004AA08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_2            , RULL(0x800008AA07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_2            , RULL(0x800008AA08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_3            , RULL(0x80000CAA07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_3            , RULL(0x80000CAA08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_4            , RULL(0x800010AA07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P3_4            , RULL(0x800010AA08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0              , RULL(0x800000AB0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0            , RULL(0x800000AB0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0            , RULL(0x800000AB0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1              , RULL(0x800004AB0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1            , RULL(0x800004AB0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1            , RULL(0x800004AB0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2              , RULL(0x800008AB0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2            , RULL(0x800008AB0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2            , RULL(0x800008AB0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3              , RULL(0x80000CAB0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3            , RULL(0x80000CAB0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3            , RULL(0x80000CAB0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4              , RULL(0x800010AB0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4            , RULL(0x800010AB0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4            , RULL(0x800010AB0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_0            , RULL(0x800000AB0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_0            , RULL(0x800000AB0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_1            , RULL(0x800004AB0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_1            , RULL(0x800004AB0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_2            , RULL(0x800008AB0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_2            , RULL(0x800008AB0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_3            , RULL(0x80000CAB0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_3            , RULL(0x80000CAB0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_4            , RULL(0x800010AB0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P1_4            , RULL(0x800010AB0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_0            , RULL(0x800000AB0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_0            , RULL(0x800000AB0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_1            , RULL(0x800004AB0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_1            , RULL(0x800004AB0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_2            , RULL(0x800008AB0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_2            , RULL(0x800008AB0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_3            , RULL(0x80000CAB0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_3            , RULL(0x80000CAB0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_4            , RULL(0x800010AB0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P2_4            , RULL(0x800010AB0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_0            , RULL(0x800000AB07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_0            , RULL(0x800000AB08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_1            , RULL(0x800004AB07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_1            , RULL(0x800004AB08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_2            , RULL(0x800008AB07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_2            , RULL(0x800008AB08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_3            , RULL(0x80000CAB07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_3            , RULL(0x80000CAB08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_4            , RULL(0x800010AB07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P3_4            , RULL(0x800010AB08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0                    , RULL(0x800000A60701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0                  , RULL(0x800000A60701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0                  , RULL(0x800000A60801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1                    , RULL(0x800004A60701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1                  , RULL(0x800004A60701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1                  , RULL(0x800004A60801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2                    , RULL(0x800008A60701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2                  , RULL(0x800008A60701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2                  , RULL(0x800008A60801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3                    , RULL(0x80000CA60701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3                  , RULL(0x80000CA60701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3                  , RULL(0x80000CA60801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4                    , RULL(0x800010A60701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4                  , RULL(0x800010A60701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4                  , RULL(0x800010A60801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SW_CONTROL0_P1_0                  , RULL(0x800000A60701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_SW_CONTROL0_P1_0                  , RULL(0x800000A60801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SW_CONTROL0_P1_1                  , RULL(0x800004A60701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_SW_CONTROL0_P1_1                  , RULL(0x800004A60801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SW_CONTROL0_P1_2                  , RULL(0x800008A60701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_SW_CONTROL0_P1_2                  , RULL(0x800008A60801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SW_CONTROL0_P1_3                  , RULL(0x80000CA60701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_SW_CONTROL0_P1_3                  , RULL(0x80000CA60801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SW_CONTROL0_P1_4                  , RULL(0x800010A60701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_SW_CONTROL0_P1_4                  , RULL(0x800010A60801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SW_CONTROL0_P2_0                  , RULL(0x800000A60701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_SW_CONTROL0_P2_0                  , RULL(0x800000A60801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SW_CONTROL0_P2_1                  , RULL(0x800004A60701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_SW_CONTROL0_P2_1                  , RULL(0x800004A60801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SW_CONTROL0_P2_2                  , RULL(0x800008A60701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_SW_CONTROL0_P2_2                  , RULL(0x800008A60801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SW_CONTROL0_P2_3                  , RULL(0x80000CA60701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_SW_CONTROL0_P2_3                  , RULL(0x80000CA60801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SW_CONTROL0_P2_4                  , RULL(0x800010A60701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_SW_CONTROL0_P2_4                  , RULL(0x800010A60801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SW_CONTROL0_P3_0                  , RULL(0x800000A607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_SW_CONTROL0_P3_0                  , RULL(0x800000A608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SW_CONTROL0_P3_1                  , RULL(0x800004A607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_SW_CONTROL0_P3_1                  , RULL(0x800004A608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SW_CONTROL0_P3_2                  , RULL(0x800008A607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_SW_CONTROL0_P3_2                  , RULL(0x800008A608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SW_CONTROL0_P3_3                  , RULL(0x80000CA607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_SW_CONTROL0_P3_3                  , RULL(0x80000CA608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SW_CONTROL0_P3_4                  , RULL(0x800010A607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_SW_CONTROL0_P3_4                  , RULL(0x800010A608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0                    , RULL(0x800000A70701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0                  , RULL(0x800000A70701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0                  , RULL(0x800000A70801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1                    , RULL(0x800004A70701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1                  , RULL(0x800004A70701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1                  , RULL(0x800004A70801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2                    , RULL(0x800008A70701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2                  , RULL(0x800008A70701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2                  , RULL(0x800008A70801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3                    , RULL(0x80000CA70701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3                  , RULL(0x80000CA70701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3                  , RULL(0x80000CA70801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4                    , RULL(0x800010A70701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4                  , RULL(0x800010A70701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4                  , RULL(0x800010A70801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SW_CONTROL1_P1_0                  , RULL(0x800000A70701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_SW_CONTROL1_P1_0                  , RULL(0x800000A70801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SW_CONTROL1_P1_1                  , RULL(0x800004A70701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_SW_CONTROL1_P1_1                  , RULL(0x800004A70801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SW_CONTROL1_P1_2                  , RULL(0x800008A70701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_SW_CONTROL1_P1_2                  , RULL(0x800008A70801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SW_CONTROL1_P1_3                  , RULL(0x80000CA70701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_SW_CONTROL1_P1_3                  , RULL(0x80000CA70801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_SW_CONTROL1_P1_4                  , RULL(0x800010A70701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_DLL_SW_CONTROL1_P1_4                  , RULL(0x800010A70801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SW_CONTROL1_P2_0                  , RULL(0x800000A70701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_SW_CONTROL1_P2_0                  , RULL(0x800000A70801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SW_CONTROL1_P2_1                  , RULL(0x800004A70701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_SW_CONTROL1_P2_1                  , RULL(0x800004A70801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SW_CONTROL1_P2_2                  , RULL(0x800008A70701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_SW_CONTROL1_P2_2                  , RULL(0x800008A70801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SW_CONTROL1_P2_3                  , RULL(0x80000CA70701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_SW_CONTROL1_P2_3                  , RULL(0x80000CA70801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_SW_CONTROL1_P2_4                  , RULL(0x800010A70701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_DLL_SW_CONTROL1_P2_4                  , RULL(0x800010A70801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SW_CONTROL1_P3_0                  , RULL(0x800000A707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_SW_CONTROL1_P3_0                  , RULL(0x800000A708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SW_CONTROL1_P3_1                  , RULL(0x800004A707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_SW_CONTROL1_P3_1                  , RULL(0x800004A708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SW_CONTROL1_P3_2                  , RULL(0x800008A707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_SW_CONTROL1_P3_2                  , RULL(0x800008A708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SW_CONTROL1_P3_3                  , RULL(0x80000CA707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_SW_CONTROL1_P3_3                  , RULL(0x80000CA708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_SW_CONTROL1_P3_4                  , RULL(0x800010A707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_DLL_SW_CONTROL1_P3_4                  , RULL(0x800010A708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0                   , RULL(0x8000002C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0                 , RULL(0x8000002C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0                 , RULL(0x8000002C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1                   , RULL(0x8000042C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1                 , RULL(0x8000042C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1                 , RULL(0x8000042C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2                   , RULL(0x8000082C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2                 , RULL(0x8000082C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2                 , RULL(0x8000082C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3                   , RULL(0x80000C2C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3                 , RULL(0x80000C2C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3                 , RULL(0x80000C2C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4                   , RULL(0x8000102C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4                 , RULL(0x8000102C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4                 , RULL(0x8000102C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_COARSE0_P1_0                 , RULL(0x8000002C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_COARSE0_P1_0                 , RULL(0x8000002C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_COARSE0_P1_1                 , RULL(0x8000042C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_COARSE0_P1_1                 , RULL(0x8000042C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_COARSE0_P1_2                 , RULL(0x8000082C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_COARSE0_P1_2                 , RULL(0x8000082C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_COARSE0_P1_3                 , RULL(0x80000C2C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_COARSE0_P1_3                 , RULL(0x80000C2C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_COARSE0_P1_4                 , RULL(0x8000102C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_COARSE0_P1_4                 , RULL(0x8000102C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_COARSE0_P2_0                 , RULL(0x8000002C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_COARSE0_P2_0                 , RULL(0x8000002C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_COARSE0_P2_1                 , RULL(0x8000042C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_COARSE0_P2_1                 , RULL(0x8000042C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_COARSE0_P2_2                 , RULL(0x8000082C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_COARSE0_P2_2                 , RULL(0x8000082C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_COARSE0_P2_3                 , RULL(0x80000C2C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_COARSE0_P2_3                 , RULL(0x80000C2C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_COARSE0_P2_4                 , RULL(0x8000102C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_COARSE0_P2_4                 , RULL(0x8000102C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_COARSE0_P3_0                 , RULL(0x8000002C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_COARSE0_P3_0                 , RULL(0x8000002C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_COARSE0_P3_1                 , RULL(0x8000042C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_COARSE0_P3_1                 , RULL(0x8000042C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_COARSE0_P3_2                 , RULL(0x8000082C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_COARSE0_P3_2                 , RULL(0x8000082C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_COARSE0_P3_3                 , RULL(0x80000C2C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_COARSE0_P3_3                 , RULL(0x80000C2C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_COARSE0_P3_4                 , RULL(0x8000102C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_COARSE0_P3_4                 , RULL(0x8000102C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0                   , RULL(0x8000002D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0                 , RULL(0x8000002D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0                 , RULL(0x8000002D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1                   , RULL(0x8000042D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1                 , RULL(0x8000042D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1                 , RULL(0x8000042D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2                   , RULL(0x8000082D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2                 , RULL(0x8000082D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2                 , RULL(0x8000082D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3                   , RULL(0x80000C2D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3                 , RULL(0x80000C2D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3                 , RULL(0x80000C2D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4                   , RULL(0x8000102D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4                 , RULL(0x8000102D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4                 , RULL(0x8000102D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_COARSE1_P1_0                 , RULL(0x8000002D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_COARSE1_P1_0                 , RULL(0x8000002D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_COARSE1_P1_1                 , RULL(0x8000042D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_COARSE1_P1_1                 , RULL(0x8000042D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_COARSE1_P1_2                 , RULL(0x8000082D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_COARSE1_P1_2                 , RULL(0x8000082D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_COARSE1_P1_3                 , RULL(0x80000C2D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_COARSE1_P1_3                 , RULL(0x80000C2D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_COARSE1_P1_4                 , RULL(0x8000102D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_COARSE1_P1_4                 , RULL(0x8000102D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_COARSE1_P2_0                 , RULL(0x8000002D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_COARSE1_P2_0                 , RULL(0x8000002D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_COARSE1_P2_1                 , RULL(0x8000042D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_COARSE1_P2_1                 , RULL(0x8000042D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_COARSE1_P2_2                 , RULL(0x8000082D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_COARSE1_P2_2                 , RULL(0x8000082D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_COARSE1_P2_3                 , RULL(0x80000C2D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_COARSE1_P2_3                 , RULL(0x80000C2D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_COARSE1_P2_4                 , RULL(0x8000102D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_COARSE1_P2_4                 , RULL(0x8000102D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_COARSE1_P3_0                 , RULL(0x8000002D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_COARSE1_P3_0                 , RULL(0x8000002D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_COARSE1_P3_1                 , RULL(0x8000042D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_COARSE1_P3_1                 , RULL(0x8000042D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_COARSE1_P3_2                 , RULL(0x8000082D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_COARSE1_P3_2                 , RULL(0x8000082D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_COARSE1_P3_3                 , RULL(0x80000C2D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_COARSE1_P3_3                 , RULL(0x80000C2D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_COARSE1_P3_4                 , RULL(0x8000102D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_COARSE1_P3_4                 , RULL(0x8000102D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0                  , RULL(0x8000002A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0                , RULL(0x8000002A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0                , RULL(0x8000002A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1                  , RULL(0x8000042A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1                , RULL(0x8000042A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1                , RULL(0x8000042A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2                  , RULL(0x8000082A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2                , RULL(0x8000082A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2                , RULL(0x8000082A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3                  , RULL(0x80000C2A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3                , RULL(0x80000C2A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3                , RULL(0x80000C2A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4                  , RULL(0x8000102A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4                , RULL(0x8000102A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4                , RULL(0x8000102A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_0                , RULL(0x8000002A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_0                , RULL(0x8000002A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_1                , RULL(0x8000042A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_1                , RULL(0x8000042A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_2                , RULL(0x8000082A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_2                , RULL(0x8000082A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_3                , RULL(0x80000C2A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_3                , RULL(0x80000C2A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_4                , RULL(0x8000102A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL0_P1_4                , RULL(0x8000102A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_0                , RULL(0x8000002A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_0                , RULL(0x8000002A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_1                , RULL(0x8000042A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_1                , RULL(0x8000042A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_2                , RULL(0x8000082A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_2                , RULL(0x8000082A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_3                , RULL(0x80000C2A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_3                , RULL(0x80000C2A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_4                , RULL(0x8000102A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL0_P2_4                , RULL(0x8000102A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_0                , RULL(0x8000002A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_0                , RULL(0x8000002A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_1                , RULL(0x8000042A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_1                , RULL(0x8000042A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_2                , RULL(0x8000082A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_2                , RULL(0x8000082A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_3                , RULL(0x80000C2A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_3                , RULL(0x80000C2A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_4                , RULL(0x8000102A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL0_P3_4                , RULL(0x8000102A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0                  , RULL(0x8000002B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0                , RULL(0x8000002B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0                , RULL(0x8000002B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1                  , RULL(0x8000042B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1                , RULL(0x8000042B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1                , RULL(0x8000042B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2                  , RULL(0x8000082B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2                , RULL(0x8000082B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2                , RULL(0x8000082B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3                  , RULL(0x80000C2B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3                , RULL(0x80000C2B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3                , RULL(0x80000C2B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4                  , RULL(0x8000102B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4                , RULL(0x8000102B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4                , RULL(0x8000102B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_0                , RULL(0x8000002B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_0                , RULL(0x8000002B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_1                , RULL(0x8000042B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_1                , RULL(0x8000042B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_2                , RULL(0x8000082B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_2                , RULL(0x8000082B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_3                , RULL(0x80000C2B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_3                , RULL(0x80000C2B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_4                , RULL(0x8000102B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DLL_VREG_CONTROL1_P1_4                , RULL(0x8000102B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_0                , RULL(0x8000002B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_0                , RULL(0x8000002B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_1                , RULL(0x8000042B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_1                , RULL(0x8000042B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_2                , RULL(0x8000082B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_2                , RULL(0x8000082B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_3                , RULL(0x80000C2B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_3                , RULL(0x80000C2B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_4                , RULL(0x8000102B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DLL_VREG_CONTROL1_P2_4                , RULL(0x8000102B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_0                , RULL(0x8000002B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_0                , RULL(0x8000002B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_1                , RULL(0x8000042B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_1                , RULL(0x8000042B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_2                , RULL(0x8000082B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_2                , RULL(0x8000082B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_3                , RULL(0x80000C2B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_3                , RULL(0x80000C2B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_4                , RULL(0x8000102B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DLL_VREG_CONTROL1_P3_4                , RULL(0x8000102B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_0                      , RULL(0x800000370701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_OFFSET_P0_0                    , RULL(0x800000370701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_OFFSET_P0_0                    , RULL(0x800000370801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_1                      , RULL(0x800004370701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_OFFSET_P0_1                    , RULL(0x800004370701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_OFFSET_P0_1                    , RULL(0x800004370801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_2                      , RULL(0x800008370701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_OFFSET_P0_2                    , RULL(0x800008370701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_OFFSET_P0_2                    , RULL(0x800008370801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_3                      , RULL(0x80000C370701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_OFFSET_P0_3                    , RULL(0x80000C370701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_OFFSET_P0_3                    , RULL(0x80000C370801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_4                      , RULL(0x800010370701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_OFFSET_P0_4                    , RULL(0x800010370701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_OFFSET_P0_4                    , RULL(0x800010370801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_OFFSET_P1_0                    , RULL(0x800000370701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_OFFSET_P1_0                    , RULL(0x800000370801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_OFFSET_P1_1                    , RULL(0x800004370701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_OFFSET_P1_1                    , RULL(0x800004370801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_OFFSET_P1_2                    , RULL(0x800008370701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_OFFSET_P1_2                    , RULL(0x800008370801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_OFFSET_P1_3                    , RULL(0x80000C370701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_OFFSET_P1_3                    , RULL(0x80000C370801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_OFFSET_P1_4                    , RULL(0x800010370701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_OFFSET_P1_4                    , RULL(0x800010370801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_OFFSET_P2_0                    , RULL(0x800000370701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_OFFSET_P2_0                    , RULL(0x800000370801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_OFFSET_P2_1                    , RULL(0x800004370701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_OFFSET_P2_1                    , RULL(0x800004370801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_OFFSET_P2_2                    , RULL(0x800008370701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_OFFSET_P2_2                    , RULL(0x800008370801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_OFFSET_P2_3                    , RULL(0x80000C370701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_OFFSET_P2_3                    , RULL(0x80000C370801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_OFFSET_P2_4                    , RULL(0x800010370701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_OFFSET_P2_4                    , RULL(0x800010370801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_OFFSET_P3_0                    , RULL(0x8000003707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_OFFSET_P3_0                    , RULL(0x8000003708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_OFFSET_P3_1                    , RULL(0x8000043707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_OFFSET_P3_1                    , RULL(0x8000043708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_OFFSET_P3_2                    , RULL(0x8000083707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_OFFSET_P3_2                    , RULL(0x8000083708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_OFFSET_P3_3                    , RULL(0x80000C3707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_OFFSET_P3_3                    , RULL(0x80000C3708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_OFFSET_P3_4                    , RULL(0x8000103707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_OFFSET_P3_4                    , RULL(0x8000103708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0              , RULL(0x800000300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0            , RULL(0x800000300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0            , RULL(0x800000300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1              , RULL(0x800004300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1            , RULL(0x800004300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1            , RULL(0x800004300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2              , RULL(0x800008300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2            , RULL(0x800008300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2            , RULL(0x800008300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3              , RULL(0x80000C300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3            , RULL(0x80000C300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3            , RULL(0x80000C300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4              , RULL(0x800010300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4            , RULL(0x800010300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4            , RULL(0x800010300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_0            , RULL(0x800000300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_0            , RULL(0x800000300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_1            , RULL(0x800004300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_1            , RULL(0x800004300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_2            , RULL(0x800008300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_2            , RULL(0x800008300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_3            , RULL(0x80000C300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_3            , RULL(0x80000C300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_4            , RULL(0x800010300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P1_4            , RULL(0x800010300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_0            , RULL(0x800000300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_0            , RULL(0x800000300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_1            , RULL(0x800004300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_1            , RULL(0x800004300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_2            , RULL(0x800008300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_2            , RULL(0x800008300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_3            , RULL(0x80000C300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_3            , RULL(0x80000C300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_4            , RULL(0x800010300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P2_4            , RULL(0x800010300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_0            , RULL(0x8000003007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_0            , RULL(0x8000003008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_1            , RULL(0x8000043007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_1            , RULL(0x8000043008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_2            , RULL(0x8000083007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_2            , RULL(0x8000083008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_3            , RULL(0x80000C3007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_3            , RULL(0x80000C3008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_4            , RULL(0x8000103007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P3_4            , RULL(0x8000103008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0              , RULL(0x800001300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0            , RULL(0x800001300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0            , RULL(0x800001300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1              , RULL(0x800005300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1            , RULL(0x800005300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1            , RULL(0x800005300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2              , RULL(0x800009300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2            , RULL(0x800009300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2            , RULL(0x800009300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3              , RULL(0x80000D300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3            , RULL(0x80000D300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3            , RULL(0x80000D300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4              , RULL(0x800011300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4            , RULL(0x800011300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4            , RULL(0x800011300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_0            , RULL(0x800001300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_0            , RULL(0x800001300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_1            , RULL(0x800005300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_1            , RULL(0x800005300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_2            , RULL(0x800009300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_2            , RULL(0x800009300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_3            , RULL(0x80000D300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_3            , RULL(0x80000D300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_4            , RULL(0x800011300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P1_4            , RULL(0x800011300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_0            , RULL(0x800001300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_0            , RULL(0x800001300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_1            , RULL(0x800005300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_1            , RULL(0x800005300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_2            , RULL(0x800009300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_2            , RULL(0x800009300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_3            , RULL(0x80000D300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_3            , RULL(0x80000D300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_4            , RULL(0x800011300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P2_4            , RULL(0x800011300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_0            , RULL(0x8000013007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_0            , RULL(0x8000013008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_1            , RULL(0x8000053007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_1            , RULL(0x8000053008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_2            , RULL(0x8000093007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_2            , RULL(0x8000093008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_3            , RULL(0x80000D3007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_3            , RULL(0x80000D3008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_4            , RULL(0x8000113007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P3_4            , RULL(0x8000113008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0              , RULL(0x800002300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0            , RULL(0x800002300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0            , RULL(0x800002300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1              , RULL(0x800006300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1            , RULL(0x800006300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1            , RULL(0x800006300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2              , RULL(0x80000A300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2            , RULL(0x80000A300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2            , RULL(0x80000A300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3              , RULL(0x80000E300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3            , RULL(0x80000E300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3            , RULL(0x80000E300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4              , RULL(0x800012300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4            , RULL(0x800012300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4            , RULL(0x800012300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_0            , RULL(0x800002300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_0            , RULL(0x800002300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_1            , RULL(0x800006300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_1            , RULL(0x800006300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_2            , RULL(0x80000A300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_2            , RULL(0x80000A300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_3            , RULL(0x80000E300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_3            , RULL(0x80000E300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_4            , RULL(0x800012300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P1_4            , RULL(0x800012300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_0            , RULL(0x800002300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_0            , RULL(0x800002300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_1            , RULL(0x800006300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_1            , RULL(0x800006300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_2            , RULL(0x80000A300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_2            , RULL(0x80000A300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_3            , RULL(0x80000E300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_3            , RULL(0x80000E300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_4            , RULL(0x800012300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P2_4            , RULL(0x800012300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_0            , RULL(0x8000023007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_0            , RULL(0x8000023008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_1            , RULL(0x8000063007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_1            , RULL(0x8000063008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_2            , RULL(0x80000A3007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_2            , RULL(0x80000A3008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_3            , RULL(0x80000E3007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_3            , RULL(0x80000E3008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_4            , RULL(0x8000123007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P3_4            , RULL(0x8000123008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0              , RULL(0x800003300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0            , RULL(0x800003300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0            , RULL(0x800003300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1              , RULL(0x800007300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1            , RULL(0x800007300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1            , RULL(0x800007300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2              , RULL(0x80000B300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2            , RULL(0x80000B300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2            , RULL(0x80000B300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3              , RULL(0x80000F300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3            , RULL(0x80000F300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3            , RULL(0x80000F300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4              , RULL(0x800013300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4            , RULL(0x800013300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4            , RULL(0x800013300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_0            , RULL(0x800003300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_0            , RULL(0x800003300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_1            , RULL(0x800007300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_1            , RULL(0x800007300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_2            , RULL(0x80000B300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_2            , RULL(0x80000B300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_3            , RULL(0x80000F300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_3            , RULL(0x80000F300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_4            , RULL(0x800013300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P1_4            , RULL(0x800013300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_0            , RULL(0x800003300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_0            , RULL(0x800003300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_1            , RULL(0x800007300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_1            , RULL(0x800007300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_2            , RULL(0x80000B300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_2            , RULL(0x80000B300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_3            , RULL(0x80000F300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_3            , RULL(0x80000F300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_4            , RULL(0x800013300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P2_4            , RULL(0x800013300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_0            , RULL(0x8000033007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_0            , RULL(0x8000033008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_1            , RULL(0x8000073007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_1            , RULL(0x8000073008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_2            , RULL(0x80000B3007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_2            , RULL(0x80000B3008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_3            , RULL(0x80000F3007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_3            , RULL(0x80000F3008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_4            , RULL(0x8000133007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P3_4            , RULL(0x8000133008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0              , RULL(0x800000310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0            , RULL(0x800000310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0            , RULL(0x800000310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1              , RULL(0x800004310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1            , RULL(0x800004310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1            , RULL(0x800004310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2              , RULL(0x800008310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2            , RULL(0x800008310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2            , RULL(0x800008310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3              , RULL(0x80000C310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3            , RULL(0x80000C310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3            , RULL(0x80000C310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4              , RULL(0x800010310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4            , RULL(0x800010310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4            , RULL(0x800010310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_0            , RULL(0x800000310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_0            , RULL(0x800000310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_1            , RULL(0x800004310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_1            , RULL(0x800004310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_2            , RULL(0x800008310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_2            , RULL(0x800008310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_3            , RULL(0x80000C310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_3            , RULL(0x80000C310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_4            , RULL(0x800010310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P1_4            , RULL(0x800010310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_0            , RULL(0x800000310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_0            , RULL(0x800000310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_1            , RULL(0x800004310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_1            , RULL(0x800004310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_2            , RULL(0x800008310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_2            , RULL(0x800008310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_3            , RULL(0x80000C310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_3            , RULL(0x80000C310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_4            , RULL(0x800010310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P2_4            , RULL(0x800010310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_0            , RULL(0x8000003107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_0            , RULL(0x8000003108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_1            , RULL(0x8000043107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_1            , RULL(0x8000043108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_2            , RULL(0x8000083107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_2            , RULL(0x8000083108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_3            , RULL(0x80000C3107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_3            , RULL(0x80000C3108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_4            , RULL(0x8000103107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P3_4            , RULL(0x8000103108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0              , RULL(0x800001310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0            , RULL(0x800001310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0            , RULL(0x800001310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1              , RULL(0x800005310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1            , RULL(0x800005310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1            , RULL(0x800005310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2              , RULL(0x800009310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2            , RULL(0x800009310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2            , RULL(0x800009310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3              , RULL(0x80000D310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3            , RULL(0x80000D310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3            , RULL(0x80000D310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4              , RULL(0x800011310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4            , RULL(0x800011310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4            , RULL(0x800011310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_0            , RULL(0x800001310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_0            , RULL(0x800001310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_1            , RULL(0x800005310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_1            , RULL(0x800005310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_2            , RULL(0x800009310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_2            , RULL(0x800009310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_3            , RULL(0x80000D310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_3            , RULL(0x80000D310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_4            , RULL(0x800011310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P1_4            , RULL(0x800011310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_0            , RULL(0x800001310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_0            , RULL(0x800001310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_1            , RULL(0x800005310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_1            , RULL(0x800005310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_2            , RULL(0x800009310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_2            , RULL(0x800009310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_3            , RULL(0x80000D310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_3            , RULL(0x80000D310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_4            , RULL(0x800011310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P2_4            , RULL(0x800011310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_0            , RULL(0x8000013107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_0            , RULL(0x8000013108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_1            , RULL(0x8000053107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_1            , RULL(0x8000053108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_2            , RULL(0x8000093107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_2            , RULL(0x8000093108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_3            , RULL(0x80000D3107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_3            , RULL(0x80000D3108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_4            , RULL(0x8000113107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P3_4            , RULL(0x8000113108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0              , RULL(0x800002310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0            , RULL(0x800002310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0            , RULL(0x800002310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1              , RULL(0x800006310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1            , RULL(0x800006310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1            , RULL(0x800006310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2              , RULL(0x80000A310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2            , RULL(0x80000A310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2            , RULL(0x80000A310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3              , RULL(0x80000E310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3            , RULL(0x80000E310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3            , RULL(0x80000E310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4              , RULL(0x800012310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4            , RULL(0x800012310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4            , RULL(0x800012310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_0            , RULL(0x800002310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_0            , RULL(0x800002310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_1            , RULL(0x800006310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_1            , RULL(0x800006310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_2            , RULL(0x80000A310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_2            , RULL(0x80000A310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_3            , RULL(0x80000E310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_3            , RULL(0x80000E310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_4            , RULL(0x800012310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P1_4            , RULL(0x800012310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_0            , RULL(0x800002310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_0            , RULL(0x800002310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_1            , RULL(0x800006310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_1            , RULL(0x800006310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_2            , RULL(0x80000A310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_2            , RULL(0x80000A310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_3            , RULL(0x80000E310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_3            , RULL(0x80000E310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_4            , RULL(0x800012310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P2_4            , RULL(0x800012310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_0            , RULL(0x8000023107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_0            , RULL(0x8000023108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_1            , RULL(0x8000063107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_1            , RULL(0x8000063108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_2            , RULL(0x80000A3107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_2            , RULL(0x80000A3108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_3            , RULL(0x80000E3107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_3            , RULL(0x80000E3108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_4            , RULL(0x8000123107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P3_4            , RULL(0x8000123108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0              , RULL(0x800003310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0            , RULL(0x800003310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0            , RULL(0x800003310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1              , RULL(0x800007310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1            , RULL(0x800007310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1            , RULL(0x800007310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2              , RULL(0x80000B310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2            , RULL(0x80000B310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2            , RULL(0x80000B310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3              , RULL(0x80000F310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3            , RULL(0x80000F310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3            , RULL(0x80000F310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4              , RULL(0x800013310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4            , RULL(0x800013310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4            , RULL(0x800013310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_0            , RULL(0x800003310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_0            , RULL(0x800003310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_1            , RULL(0x800007310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_1            , RULL(0x800007310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_2            , RULL(0x80000B310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_2            , RULL(0x80000B310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_3            , RULL(0x80000F310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_3            , RULL(0x80000F310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_4            , RULL(0x800013310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P1_4            , RULL(0x800013310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_0            , RULL(0x800003310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_0            , RULL(0x800003310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_1            , RULL(0x800007310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_1            , RULL(0x800007310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_2            , RULL(0x80000B310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_2            , RULL(0x80000B310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_3            , RULL(0x80000F310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_3            , RULL(0x80000F310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_4            , RULL(0x800013310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P2_4            , RULL(0x800013310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_0            , RULL(0x8000033107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_0            , RULL(0x8000033108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_1            , RULL(0x8000073107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_1            , RULL(0x8000073108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_2            , RULL(0x80000B3107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_2            , RULL(0x80000B3108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_3            , RULL(0x80000F3107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_3            , RULL(0x80000F3108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_4            , RULL(0x8000133107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P3_4            , RULL(0x8000133108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0                 , RULL(0x800000130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0               , RULL(0x800000130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0               , RULL(0x800000130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1                 , RULL(0x800004130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1               , RULL(0x800004130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1               , RULL(0x800004130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2                 , RULL(0x800008130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2               , RULL(0x800008130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2               , RULL(0x800008130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3                 , RULL(0x80000C130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3               , RULL(0x80000C130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3               , RULL(0x80000C130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4                 , RULL(0x800010130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4               , RULL(0x800010130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4               , RULL(0x800010130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_0               , RULL(0x800000130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_0               , RULL(0x800000130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_1               , RULL(0x800004130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_1               , RULL(0x800004130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_2               , RULL(0x800008130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_2               , RULL(0x800008130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_3               , RULL(0x80000C130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_3               , RULL(0x80000C130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_4               , RULL(0x800010130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P1_4               , RULL(0x800010130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_0               , RULL(0x800000130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_0               , RULL(0x800000130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_1               , RULL(0x800004130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_1               , RULL(0x800004130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_2               , RULL(0x800008130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_2               , RULL(0x800008130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_3               , RULL(0x80000C130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_3               , RULL(0x80000C130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_4               , RULL(0x800010130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P2_4               , RULL(0x800010130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_0               , RULL(0x8000001307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_0               , RULL(0x8000001308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_1               , RULL(0x8000041307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_1               , RULL(0x8000041308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_2               , RULL(0x8000081307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_2               , RULL(0x8000081308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_3               , RULL(0x80000C1307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_3               , RULL(0x80000C1308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_4               , RULL(0x8000101307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P3_4               , RULL(0x8000101308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0                 , RULL(0x800001130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0               , RULL(0x800001130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0               , RULL(0x800001130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1                 , RULL(0x800005130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1               , RULL(0x800005130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1               , RULL(0x800005130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2                 , RULL(0x800009130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2               , RULL(0x800009130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2               , RULL(0x800009130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3                 , RULL(0x80000D130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3               , RULL(0x80000D130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3               , RULL(0x80000D130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4                 , RULL(0x800011130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4               , RULL(0x800011130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4               , RULL(0x800011130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_0               , RULL(0x800001130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_0               , RULL(0x800001130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_1               , RULL(0x800005130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_1               , RULL(0x800005130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_2               , RULL(0x800009130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_2               , RULL(0x800009130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_3               , RULL(0x80000D130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_3               , RULL(0x80000D130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_4               , RULL(0x800011130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P1_4               , RULL(0x800011130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_0               , RULL(0x800001130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_0               , RULL(0x800001130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_1               , RULL(0x800005130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_1               , RULL(0x800005130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_2               , RULL(0x800009130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_2               , RULL(0x800009130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_3               , RULL(0x80000D130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_3               , RULL(0x80000D130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_4               , RULL(0x800011130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P2_4               , RULL(0x800011130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_0               , RULL(0x8000011307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_0               , RULL(0x8000011308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_1               , RULL(0x8000051307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_1               , RULL(0x8000051308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_2               , RULL(0x8000091307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_2               , RULL(0x8000091308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_3               , RULL(0x80000D1307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_3               , RULL(0x80000D1308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_4               , RULL(0x8000111307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P3_4               , RULL(0x8000111308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0                 , RULL(0x800002130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0               , RULL(0x800002130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0               , RULL(0x800002130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1                 , RULL(0x800006130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1               , RULL(0x800006130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1               , RULL(0x800006130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2                 , RULL(0x80000A130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2               , RULL(0x80000A130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2               , RULL(0x80000A130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3                 , RULL(0x80000E130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3               , RULL(0x80000E130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3               , RULL(0x80000E130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4                 , RULL(0x800012130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4               , RULL(0x800012130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4               , RULL(0x800012130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_0               , RULL(0x800002130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_0               , RULL(0x800002130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_1               , RULL(0x800006130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_1               , RULL(0x800006130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_2               , RULL(0x80000A130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_2               , RULL(0x80000A130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_3               , RULL(0x80000E130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_3               , RULL(0x80000E130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_4               , RULL(0x800012130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P1_4               , RULL(0x800012130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_0               , RULL(0x800002130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_0               , RULL(0x800002130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_1               , RULL(0x800006130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_1               , RULL(0x800006130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_2               , RULL(0x80000A130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_2               , RULL(0x80000A130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_3               , RULL(0x80000E130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_3               , RULL(0x80000E130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_4               , RULL(0x800012130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P2_4               , RULL(0x800012130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_0               , RULL(0x8000021307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_0               , RULL(0x8000021308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_1               , RULL(0x8000061307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_1               , RULL(0x8000061308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_2               , RULL(0x80000A1307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_2               , RULL(0x80000A1308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_3               , RULL(0x80000E1307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_3               , RULL(0x80000E1308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_4               , RULL(0x8000121307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P3_4               , RULL(0x8000121308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0                 , RULL(0x800003130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0               , RULL(0x800003130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0               , RULL(0x800003130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1                 , RULL(0x800007130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1               , RULL(0x800007130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1               , RULL(0x800007130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2                 , RULL(0x80000B130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2               , RULL(0x80000B130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2               , RULL(0x80000B130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3                 , RULL(0x80000F130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3               , RULL(0x80000F130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3               , RULL(0x80000F130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4                 , RULL(0x800013130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4               , RULL(0x800013130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4               , RULL(0x800013130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_0               , RULL(0x800003130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_0               , RULL(0x800003130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_1               , RULL(0x800007130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_1               , RULL(0x800007130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_2               , RULL(0x80000B130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_2               , RULL(0x80000B130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_3               , RULL(0x80000F130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_3               , RULL(0x80000F130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_4               , RULL(0x800013130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P1_4               , RULL(0x800013130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_0               , RULL(0x800003130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_0               , RULL(0x800003130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_1               , RULL(0x800007130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_1               , RULL(0x800007130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_2               , RULL(0x80000B130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_2               , RULL(0x80000B130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_3               , RULL(0x80000F130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_3               , RULL(0x80000F130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_4               , RULL(0x800013130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P2_4               , RULL(0x800013130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_0               , RULL(0x8000031307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_0               , RULL(0x8000031308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_1               , RULL(0x8000071307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_1               , RULL(0x8000071308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_2               , RULL(0x80000B1307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_2               , RULL(0x80000B1308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_3               , RULL(0x80000F1307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_3               , RULL(0x80000F1308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_4               , RULL(0x8000131307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P3_4               , RULL(0x8000131308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0     , RULL(0x800000090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0   , RULL(0x800000090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0   , RULL(0x800000090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1     , RULL(0x800004090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1   , RULL(0x800004090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1   , RULL(0x800004090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2     , RULL(0x800008090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2   , RULL(0x800008090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2   , RULL(0x800008090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3     , RULL(0x80000C090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3   , RULL(0x80000C090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3   , RULL(0x80000C090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4     , RULL(0x800010090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4   , RULL(0x800010090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4   , RULL(0x800010090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0   , RULL(0x800000090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0   , RULL(0x800000090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1   , RULL(0x800004090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1   , RULL(0x800004090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2   , RULL(0x800008090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2   , RULL(0x800008090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3   , RULL(0x80000C090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3   , RULL(0x80000C090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4   , RULL(0x800010090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4   , RULL(0x800010090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_0   , RULL(0x800000090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_0   , RULL(0x800000090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_1   , RULL(0x800004090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_1   , RULL(0x800004090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_2   , RULL(0x800008090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_2   , RULL(0x800008090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_3   , RULL(0x80000C090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_3   , RULL(0x80000C090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_4   , RULL(0x800010090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P2_4   , RULL(0x800010090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_0   , RULL(0x8000000907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_0   , RULL(0x8000000908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_1   , RULL(0x8000040907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_1   , RULL(0x8000040908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_2   , RULL(0x8000080907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_2   , RULL(0x8000080908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_3   , RULL(0x80000C0907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_3   , RULL(0x80000C0908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_4   , RULL(0x8000100907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P3_4   , RULL(0x8000100908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0     , RULL(0x800001090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0   , RULL(0x800001090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0   , RULL(0x800001090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1     , RULL(0x800005090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1   , RULL(0x800005090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1   , RULL(0x800005090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2     , RULL(0x800009090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2   , RULL(0x800009090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2   , RULL(0x800009090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3     , RULL(0x80000D090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3   , RULL(0x80000D090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3   , RULL(0x80000D090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4     , RULL(0x800011090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4   , RULL(0x800011090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4   , RULL(0x800011090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0   , RULL(0x800001090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0   , RULL(0x800001090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1   , RULL(0x800005090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1   , RULL(0x800005090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2   , RULL(0x800009090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2   , RULL(0x800009090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3   , RULL(0x80000D090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3   , RULL(0x80000D090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4   , RULL(0x800011090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4   , RULL(0x800011090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_0   , RULL(0x800001090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_0   , RULL(0x800001090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_1   , RULL(0x800005090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_1   , RULL(0x800005090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_2   , RULL(0x800009090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_2   , RULL(0x800009090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_3   , RULL(0x80000D090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_3   , RULL(0x80000D090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_4   , RULL(0x800011090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P2_4   , RULL(0x800011090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_0   , RULL(0x8000010907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_0   , RULL(0x8000010908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_1   , RULL(0x8000050907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_1   , RULL(0x8000050908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_2   , RULL(0x8000090907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_2   , RULL(0x8000090908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_3   , RULL(0x80000D0907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_3   , RULL(0x80000D0908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_4   , RULL(0x8000110907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P3_4   , RULL(0x8000110908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0     , RULL(0x800002090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0   , RULL(0x800002090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0   , RULL(0x800002090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1     , RULL(0x800006090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1   , RULL(0x800006090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1   , RULL(0x800006090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2     , RULL(0x80000A090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2   , RULL(0x80000A090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2   , RULL(0x80000A090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3     , RULL(0x80000E090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3   , RULL(0x80000E090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3   , RULL(0x80000E090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4     , RULL(0x800012090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4   , RULL(0x800012090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4   , RULL(0x800012090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0   , RULL(0x800002090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0   , RULL(0x800002090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1   , RULL(0x800006090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1   , RULL(0x800006090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2   , RULL(0x80000A090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2   , RULL(0x80000A090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3   , RULL(0x80000E090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3   , RULL(0x80000E090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4   , RULL(0x800012090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4   , RULL(0x800012090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_0   , RULL(0x800002090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_0   , RULL(0x800002090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_1   , RULL(0x800006090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_1   , RULL(0x800006090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_2   , RULL(0x80000A090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_2   , RULL(0x80000A090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_3   , RULL(0x80000E090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_3   , RULL(0x80000E090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_4   , RULL(0x800012090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P2_4   , RULL(0x800012090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_0   , RULL(0x8000020907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_0   , RULL(0x8000020908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_1   , RULL(0x8000060907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_1   , RULL(0x8000060908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_2   , RULL(0x80000A0907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_2   , RULL(0x80000A0908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_3   , RULL(0x80000E0907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_3   , RULL(0x80000E0908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_4   , RULL(0x8000120907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P3_4   , RULL(0x8000120908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0     , RULL(0x800003090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0   , RULL(0x800003090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0   , RULL(0x800003090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1     , RULL(0x800007090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1   , RULL(0x800007090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1   , RULL(0x800007090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2     , RULL(0x80000B090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2   , RULL(0x80000B090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2   , RULL(0x80000B090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3     , RULL(0x80000F090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3   , RULL(0x80000F090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3   , RULL(0x80000F090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4     , RULL(0x800013090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4   , RULL(0x800013090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4   , RULL(0x800013090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0   , RULL(0x800003090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0   , RULL(0x800003090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1   , RULL(0x800007090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1   , RULL(0x800007090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2   , RULL(0x80000B090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2   , RULL(0x80000B090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3   , RULL(0x80000F090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3   , RULL(0x80000F090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4   , RULL(0x800013090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4   , RULL(0x800013090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_0   , RULL(0x800003090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_0   , RULL(0x800003090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_1   , RULL(0x800007090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_1   , RULL(0x800007090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_2   , RULL(0x80000B090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_2   , RULL(0x80000B090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_3   , RULL(0x80000F090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_3   , RULL(0x80000F090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_4   , RULL(0x800013090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P2_4   , RULL(0x800013090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_0   , RULL(0x8000030907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_0   , RULL(0x8000030908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_1   , RULL(0x8000070907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_1   , RULL(0x8000070908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_2   , RULL(0x80000B0907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_2   , RULL(0x80000B0908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_3   , RULL(0x80000F0907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_3   , RULL(0x80000F0908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_4   , RULL(0x8000130907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P3_4   , RULL(0x8000130908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0                   , RULL(0x8000007E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0                 , RULL(0x8000007E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0                 , RULL(0x8000007E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1                   , RULL(0x8000047E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1                 , RULL(0x8000047E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1                 , RULL(0x8000047E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2                   , RULL(0x8000087E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2                 , RULL(0x8000087E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2                 , RULL(0x8000087E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3                   , RULL(0x80000C7E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3                 , RULL(0x80000C7E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3                 , RULL(0x80000C7E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4                   , RULL(0x8000107E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4                 , RULL(0x8000107E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4                 , RULL(0x8000107E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_0                 , RULL(0x8000007E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_0                 , RULL(0x8000007E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_1                 , RULL(0x8000047E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_1                 , RULL(0x8000047E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_2                 , RULL(0x8000087E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_2                 , RULL(0x8000087E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_3                 , RULL(0x80000C7E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_3                 , RULL(0x80000C7E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_4                 , RULL(0x8000107E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P1_4                 , RULL(0x8000107E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_0                 , RULL(0x8000007E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_0                 , RULL(0x8000007E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_1                 , RULL(0x8000047E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_1                 , RULL(0x8000047E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_2                 , RULL(0x8000087E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_2                 , RULL(0x8000087E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_3                 , RULL(0x80000C7E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_3                 , RULL(0x80000C7E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_4                 , RULL(0x8000107E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P2_4                 , RULL(0x8000107E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_0                 , RULL(0x8000007E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_0                 , RULL(0x8000007E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_1                 , RULL(0x8000047E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_1                 , RULL(0x8000047E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_2                 , RULL(0x8000087E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_2                 , RULL(0x8000087E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_3                 , RULL(0x80000C7E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_3                 , RULL(0x80000C7E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_4                 , RULL(0x8000107E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P3_4                 , RULL(0x8000107E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0                   , RULL(0x8000017E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0                 , RULL(0x8000017E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0                 , RULL(0x8000017E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1                   , RULL(0x8000057E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1                 , RULL(0x8000057E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1                 , RULL(0x8000057E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2                   , RULL(0x8000097E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2                 , RULL(0x8000097E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2                 , RULL(0x8000097E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3                   , RULL(0x80000D7E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3                 , RULL(0x80000D7E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3                 , RULL(0x80000D7E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4                   , RULL(0x8000117E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4                 , RULL(0x8000117E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4                 , RULL(0x8000117E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_0                 , RULL(0x8000017E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_0                 , RULL(0x8000017E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_1                 , RULL(0x8000057E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_1                 , RULL(0x8000057E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_2                 , RULL(0x8000097E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_2                 , RULL(0x8000097E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_3                 , RULL(0x80000D7E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_3                 , RULL(0x80000D7E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_4                 , RULL(0x8000117E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P1_4                 , RULL(0x8000117E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_0                 , RULL(0x8000017E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_0                 , RULL(0x8000017E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_1                 , RULL(0x8000057E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_1                 , RULL(0x8000057E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_2                 , RULL(0x8000097E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_2                 , RULL(0x8000097E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_3                 , RULL(0x80000D7E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_3                 , RULL(0x80000D7E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_4                 , RULL(0x8000117E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P2_4                 , RULL(0x8000117E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_0                 , RULL(0x8000017E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_0                 , RULL(0x8000017E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_1                 , RULL(0x8000057E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_1                 , RULL(0x8000057E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_2                 , RULL(0x8000097E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_2                 , RULL(0x8000097E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_3                 , RULL(0x80000D7E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_3                 , RULL(0x80000D7E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_4                 , RULL(0x8000117E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P3_4                 , RULL(0x8000117E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0                   , RULL(0x8000027E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0                 , RULL(0x8000027E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0                 , RULL(0x8000027E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1                   , RULL(0x8000067E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1                 , RULL(0x8000067E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1                 , RULL(0x8000067E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2                   , RULL(0x80000A7E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2                 , RULL(0x80000A7E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2                 , RULL(0x80000A7E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3                   , RULL(0x80000E7E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3                 , RULL(0x80000E7E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3                 , RULL(0x80000E7E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4                   , RULL(0x8000127E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4                 , RULL(0x8000127E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4                 , RULL(0x8000127E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_0                 , RULL(0x8000027E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_0                 , RULL(0x8000027E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_1                 , RULL(0x8000067E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_1                 , RULL(0x8000067E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_2                 , RULL(0x80000A7E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_2                 , RULL(0x80000A7E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_3                 , RULL(0x80000E7E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_3                 , RULL(0x80000E7E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_4                 , RULL(0x8000127E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P1_4                 , RULL(0x8000127E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_0                 , RULL(0x8000027E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_0                 , RULL(0x8000027E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_1                 , RULL(0x8000067E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_1                 , RULL(0x8000067E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_2                 , RULL(0x80000A7E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_2                 , RULL(0x80000A7E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_3                 , RULL(0x80000E7E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_3                 , RULL(0x80000E7E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_4                 , RULL(0x8000127E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P2_4                 , RULL(0x8000127E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_0                 , RULL(0x8000027E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_0                 , RULL(0x8000027E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_1                 , RULL(0x8000067E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_1                 , RULL(0x8000067E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_2                 , RULL(0x80000A7E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_2                 , RULL(0x80000A7E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_3                 , RULL(0x80000E7E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_3                 , RULL(0x80000E7E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_4                 , RULL(0x8000127E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P3_4                 , RULL(0x8000127E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0                   , RULL(0x8000037E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0                 , RULL(0x8000037E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0                 , RULL(0x8000037E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1                   , RULL(0x8000077E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1                 , RULL(0x8000077E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1                 , RULL(0x8000077E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2                   , RULL(0x80000B7E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2                 , RULL(0x80000B7E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2                 , RULL(0x80000B7E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3                   , RULL(0x80000F7E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3                 , RULL(0x80000F7E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3                 , RULL(0x80000F7E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4                   , RULL(0x8000137E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4                 , RULL(0x8000137E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4                 , RULL(0x8000137E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_0                 , RULL(0x8000037E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_0                 , RULL(0x8000037E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_1                 , RULL(0x8000077E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_1                 , RULL(0x8000077E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_2                 , RULL(0x80000B7E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_2                 , RULL(0x80000B7E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_3                 , RULL(0x80000F7E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_3                 , RULL(0x80000F7E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_4                 , RULL(0x8000137E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P1_4                 , RULL(0x8000137E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_0                 , RULL(0x8000037E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_0                 , RULL(0x8000037E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_1                 , RULL(0x8000077E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_1                 , RULL(0x8000077E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_2                 , RULL(0x80000B7E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_2                 , RULL(0x80000B7E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_3                 , RULL(0x80000F7E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_3                 , RULL(0x80000F7E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_4                 , RULL(0x8000137E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P2_4                 , RULL(0x8000137E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_0                 , RULL(0x8000037E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_0                 , RULL(0x8000037E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_1                 , RULL(0x8000077E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_1                 , RULL(0x8000077E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_2                 , RULL(0x80000B7E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_2                 , RULL(0x80000B7E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_3                 , RULL(0x80000F7E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_3                 , RULL(0x80000F7E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_4                 , RULL(0x8000137E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P3_4                 , RULL(0x8000137E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0                       , RULL(0x8000000A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DRIFT_LIMITS_P0_0                     , RULL(0x8000000A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DRIFT_LIMITS_P0_0                     , RULL(0x8000000A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1                       , RULL(0x8000040A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DRIFT_LIMITS_P0_1                     , RULL(0x8000040A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DRIFT_LIMITS_P0_1                     , RULL(0x8000040A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2                       , RULL(0x8000080A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DRIFT_LIMITS_P0_2                     , RULL(0x8000080A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DRIFT_LIMITS_P0_2                     , RULL(0x8000080A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3                       , RULL(0x80000C0A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DRIFT_LIMITS_P0_3                     , RULL(0x80000C0A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DRIFT_LIMITS_P0_3                     , RULL(0x80000C0A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4                       , RULL(0x8000100A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_DRIFT_LIMITS_P0_4                     , RULL(0x8000100A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_DRIFT_LIMITS_P0_4                     , RULL(0x8000100A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DRIFT_LIMITS_P1_0                     , RULL(0x8000000A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DRIFT_LIMITS_P1_0                     , RULL(0x8000000A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DRIFT_LIMITS_P1_1                     , RULL(0x8000040A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DRIFT_LIMITS_P1_1                     , RULL(0x8000040A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DRIFT_LIMITS_P1_2                     , RULL(0x8000080A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DRIFT_LIMITS_P1_2                     , RULL(0x8000080A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DRIFT_LIMITS_P1_3                     , RULL(0x80000C0A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DRIFT_LIMITS_P1_3                     , RULL(0x80000C0A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_DRIFT_LIMITS_P1_4                     , RULL(0x8000100A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_DRIFT_LIMITS_P1_4                     , RULL(0x8000100A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DRIFT_LIMITS_P2_0                     , RULL(0x8000000A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DRIFT_LIMITS_P2_0                     , RULL(0x8000000A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DRIFT_LIMITS_P2_1                     , RULL(0x8000040A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DRIFT_LIMITS_P2_1                     , RULL(0x8000040A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DRIFT_LIMITS_P2_2                     , RULL(0x8000080A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DRIFT_LIMITS_P2_2                     , RULL(0x8000080A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DRIFT_LIMITS_P2_3                     , RULL(0x80000C0A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DRIFT_LIMITS_P2_3                     , RULL(0x80000C0A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_DRIFT_LIMITS_P2_4                     , RULL(0x8000100A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_DRIFT_LIMITS_P2_4                     , RULL(0x8000100A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DRIFT_LIMITS_P3_0                     , RULL(0x8000000A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DRIFT_LIMITS_P3_0                     , RULL(0x8000000A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DRIFT_LIMITS_P3_1                     , RULL(0x8000040A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DRIFT_LIMITS_P3_1                     , RULL(0x8000040A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DRIFT_LIMITS_P3_2                     , RULL(0x8000080A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DRIFT_LIMITS_P3_2                     , RULL(0x8000080A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DRIFT_LIMITS_P3_3                     , RULL(0x80000C0A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DRIFT_LIMITS_P3_3                     , RULL(0x80000C0A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_DRIFT_LIMITS_P3_4                     , RULL(0x8000100A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_DRIFT_LIMITS_P3_4                     , RULL(0x8000100A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0      , RULL(0x8000005C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0    , RULL(0x8000005C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0    , RULL(0x8000005C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1      , RULL(0x8000045C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1    , RULL(0x8000045C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1    , RULL(0x8000045C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2      , RULL(0x8000085C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2    , RULL(0x8000085C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2    , RULL(0x8000085C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3      , RULL(0x80000C5C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3    , RULL(0x80000C5C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3    , RULL(0x80000C5C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4      , RULL(0x8000105C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4    , RULL(0x8000105C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4    , RULL(0x8000105C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_0    , RULL(0x8000005C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_0    , RULL(0x8000005C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_1    , RULL(0x8000045C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_1    , RULL(0x8000045C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_2    , RULL(0x8000085C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_2    , RULL(0x8000085C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_3    , RULL(0x80000C5C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_3    , RULL(0x80000C5C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_4    , RULL(0x8000105C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P1_4    , RULL(0x8000105C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_0    , RULL(0x8000005C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_0    , RULL(0x8000005C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_1    , RULL(0x8000045C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_1    , RULL(0x8000045C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_2    , RULL(0x8000085C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_2    , RULL(0x8000085C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_3    , RULL(0x80000C5C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_3    , RULL(0x80000C5C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_4    , RULL(0x8000105C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P2_4    , RULL(0x8000105C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_0    , RULL(0x8000005C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_0    , RULL(0x8000005C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_1    , RULL(0x8000045C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_1    , RULL(0x8000045C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_2    , RULL(0x8000085C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_2    , RULL(0x8000085C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_3    , RULL(0x80000C5C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_3    , RULL(0x80000C5C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_4    , RULL(0x8000105C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P3_4    , RULL(0x8000105C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0      , RULL(0x8000015C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0    , RULL(0x8000015C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0    , RULL(0x8000015C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1      , RULL(0x8000055C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1    , RULL(0x8000055C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1    , RULL(0x8000055C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2      , RULL(0x8000095C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2    , RULL(0x8000095C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2    , RULL(0x8000095C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3      , RULL(0x80000D5C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3    , RULL(0x80000D5C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3    , RULL(0x80000D5C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4      , RULL(0x8000115C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4    , RULL(0x8000115C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4    , RULL(0x8000115C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_0    , RULL(0x8000015C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_0    , RULL(0x8000015C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_1    , RULL(0x8000055C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_1    , RULL(0x8000055C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_2    , RULL(0x8000095C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_2    , RULL(0x8000095C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_3    , RULL(0x80000D5C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_3    , RULL(0x80000D5C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_4    , RULL(0x8000115C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P1_4    , RULL(0x8000115C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_0    , RULL(0x8000015C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_0    , RULL(0x8000015C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_1    , RULL(0x8000055C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_1    , RULL(0x8000055C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_2    , RULL(0x8000095C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_2    , RULL(0x8000095C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_3    , RULL(0x80000D5C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_3    , RULL(0x80000D5C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_4    , RULL(0x8000115C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P2_4    , RULL(0x8000115C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_0    , RULL(0x8000015C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_0    , RULL(0x8000015C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_1    , RULL(0x8000055C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_1    , RULL(0x8000055C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_2    , RULL(0x8000095C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_2    , RULL(0x8000095C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_3    , RULL(0x80000D5C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_3    , RULL(0x80000D5C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_4    , RULL(0x8000115C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P3_4    , RULL(0x8000115C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0      , RULL(0x8000025C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0    , RULL(0x8000025C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0    , RULL(0x8000025C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1      , RULL(0x8000065C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1    , RULL(0x8000065C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1    , RULL(0x8000065C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2      , RULL(0x80000A5C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2    , RULL(0x80000A5C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2    , RULL(0x80000A5C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3      , RULL(0x80000E5C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3    , RULL(0x80000E5C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3    , RULL(0x80000E5C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4      , RULL(0x8000125C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4    , RULL(0x8000125C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4    , RULL(0x8000125C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_0    , RULL(0x8000025C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_0    , RULL(0x8000025C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_1    , RULL(0x8000065C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_1    , RULL(0x8000065C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_2    , RULL(0x80000A5C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_2    , RULL(0x80000A5C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_3    , RULL(0x80000E5C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_3    , RULL(0x80000E5C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_4    , RULL(0x8000125C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P1_4    , RULL(0x8000125C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_0    , RULL(0x8000025C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_0    , RULL(0x8000025C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_1    , RULL(0x8000065C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_1    , RULL(0x8000065C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_2    , RULL(0x80000A5C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_2    , RULL(0x80000A5C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_3    , RULL(0x80000E5C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_3    , RULL(0x80000E5C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_4    , RULL(0x8000125C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P2_4    , RULL(0x8000125C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_0    , RULL(0x8000025C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_0    , RULL(0x8000025C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_1    , RULL(0x8000065C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_1    , RULL(0x8000065C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_2    , RULL(0x80000A5C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_2    , RULL(0x80000A5C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_3    , RULL(0x80000E5C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_3    , RULL(0x80000E5C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_4    , RULL(0x8000125C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P3_4    , RULL(0x8000125C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0      , RULL(0x8000035C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0    , RULL(0x8000035C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0    , RULL(0x8000035C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1      , RULL(0x8000075C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1    , RULL(0x8000075C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1    , RULL(0x8000075C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2      , RULL(0x80000B5C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2    , RULL(0x80000B5C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2    , RULL(0x80000B5C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3      , RULL(0x80000F5C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3    , RULL(0x80000F5C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3    , RULL(0x80000F5C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4      , RULL(0x8000135C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4    , RULL(0x8000135C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4    , RULL(0x8000135C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_0    , RULL(0x8000035C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_0    , RULL(0x8000035C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_1    , RULL(0x8000075C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_1    , RULL(0x8000075C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_2    , RULL(0x80000B5C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_2    , RULL(0x80000B5C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_3    , RULL(0x80000F5C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_3    , RULL(0x80000F5C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_4    , RULL(0x8000135C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P1_4    , RULL(0x8000135C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_0    , RULL(0x8000035C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_0    , RULL(0x8000035C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_1    , RULL(0x8000075C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_1    , RULL(0x8000075C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_2    , RULL(0x80000B5C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_2    , RULL(0x80000B5C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_3    , RULL(0x80000F5C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_3    , RULL(0x80000F5C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_4    , RULL(0x8000135C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P2_4    , RULL(0x8000135C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_0    , RULL(0x8000035C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_0    , RULL(0x8000035C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_1    , RULL(0x8000075C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_1    , RULL(0x8000075C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_2    , RULL(0x80000B5C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_2    , RULL(0x80000B5C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_3    , RULL(0x80000F5C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_3    , RULL(0x80000F5C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_4    , RULL(0x8000135C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P3_4    , RULL(0x8000135C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0      , RULL(0x8000005D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0    , RULL(0x8000005D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0    , RULL(0x8000005D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1      , RULL(0x8000045D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1    , RULL(0x8000045D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1    , RULL(0x8000045D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2      , RULL(0x8000085D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2    , RULL(0x8000085D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2    , RULL(0x8000085D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3      , RULL(0x80000C5D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3    , RULL(0x80000C5D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3    , RULL(0x80000C5D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4      , RULL(0x8000105D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4    , RULL(0x8000105D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4    , RULL(0x8000105D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_0    , RULL(0x8000005D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_0    , RULL(0x8000005D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_1    , RULL(0x8000045D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_1    , RULL(0x8000045D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_2    , RULL(0x8000085D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_2    , RULL(0x8000085D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_3    , RULL(0x80000C5D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_3    , RULL(0x80000C5D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_4    , RULL(0x8000105D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P1_4    , RULL(0x8000105D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_0    , RULL(0x8000005D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_0    , RULL(0x8000005D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_1    , RULL(0x8000045D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_1    , RULL(0x8000045D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_2    , RULL(0x8000085D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_2    , RULL(0x8000085D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_3    , RULL(0x80000C5D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_3    , RULL(0x80000C5D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_4    , RULL(0x8000105D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P2_4    , RULL(0x8000105D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_0    , RULL(0x8000005D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_0    , RULL(0x8000005D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_1    , RULL(0x8000045D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_1    , RULL(0x8000045D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_2    , RULL(0x8000085D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_2    , RULL(0x8000085D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_3    , RULL(0x80000C5D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_3    , RULL(0x80000C5D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_4    , RULL(0x8000105D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P3_4    , RULL(0x8000105D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0      , RULL(0x8000015D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0    , RULL(0x8000015D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0    , RULL(0x8000015D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1      , RULL(0x8000055D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1    , RULL(0x8000055D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1    , RULL(0x8000055D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2      , RULL(0x8000095D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2    , RULL(0x8000095D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2    , RULL(0x8000095D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3      , RULL(0x80000D5D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3    , RULL(0x80000D5D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3    , RULL(0x80000D5D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4      , RULL(0x8000115D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4    , RULL(0x8000115D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4    , RULL(0x8000115D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_0    , RULL(0x8000015D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_0    , RULL(0x8000015D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_1    , RULL(0x8000055D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_1    , RULL(0x8000055D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_2    , RULL(0x8000095D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_2    , RULL(0x8000095D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_3    , RULL(0x80000D5D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_3    , RULL(0x80000D5D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_4    , RULL(0x8000115D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P1_4    , RULL(0x8000115D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_0    , RULL(0x8000015D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_0    , RULL(0x8000015D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_1    , RULL(0x8000055D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_1    , RULL(0x8000055D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_2    , RULL(0x8000095D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_2    , RULL(0x8000095D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_3    , RULL(0x80000D5D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_3    , RULL(0x80000D5D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_4    , RULL(0x8000115D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P2_4    , RULL(0x8000115D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_0    , RULL(0x8000015D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_0    , RULL(0x8000015D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_1    , RULL(0x8000055D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_1    , RULL(0x8000055D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_2    , RULL(0x8000095D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_2    , RULL(0x8000095D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_3    , RULL(0x80000D5D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_3    , RULL(0x80000D5D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_4    , RULL(0x8000115D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P3_4    , RULL(0x8000115D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0      , RULL(0x8000025D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0    , RULL(0x8000025D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0    , RULL(0x8000025D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1      , RULL(0x8000065D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1    , RULL(0x8000065D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1    , RULL(0x8000065D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2      , RULL(0x80000A5D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2    , RULL(0x80000A5D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2    , RULL(0x80000A5D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3      , RULL(0x80000E5D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3    , RULL(0x80000E5D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3    , RULL(0x80000E5D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4      , RULL(0x8000125D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4    , RULL(0x8000125D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4    , RULL(0x8000125D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_0    , RULL(0x8000025D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_0    , RULL(0x8000025D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_1    , RULL(0x8000065D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_1    , RULL(0x8000065D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_2    , RULL(0x80000A5D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_2    , RULL(0x80000A5D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_3    , RULL(0x80000E5D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_3    , RULL(0x80000E5D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_4    , RULL(0x8000125D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P1_4    , RULL(0x8000125D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_0    , RULL(0x8000025D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_0    , RULL(0x8000025D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_1    , RULL(0x8000065D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_1    , RULL(0x8000065D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_2    , RULL(0x80000A5D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_2    , RULL(0x80000A5D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_3    , RULL(0x80000E5D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_3    , RULL(0x80000E5D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_4    , RULL(0x8000125D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P2_4    , RULL(0x8000125D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_0    , RULL(0x8000025D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_0    , RULL(0x8000025D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_1    , RULL(0x8000065D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_1    , RULL(0x8000065D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_2    , RULL(0x80000A5D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_2    , RULL(0x80000A5D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_3    , RULL(0x80000E5D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_3    , RULL(0x80000E5D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_4    , RULL(0x8000125D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P3_4    , RULL(0x8000125D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0      , RULL(0x8000035D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0    , RULL(0x8000035D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0    , RULL(0x8000035D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1      , RULL(0x8000075D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1    , RULL(0x8000075D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1    , RULL(0x8000075D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2      , RULL(0x80000B5D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2    , RULL(0x80000B5D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2    , RULL(0x80000B5D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3      , RULL(0x80000F5D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3    , RULL(0x80000F5D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3    , RULL(0x80000F5D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4      , RULL(0x8000135D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4    , RULL(0x8000135D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4    , RULL(0x8000135D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_0    , RULL(0x8000035D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_0    , RULL(0x8000035D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_1    , RULL(0x8000075D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_1    , RULL(0x8000075D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_2    , RULL(0x80000B5D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_2    , RULL(0x80000B5D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_3    , RULL(0x80000F5D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_3    , RULL(0x80000F5D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_4    , RULL(0x8000135D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P1_4    , RULL(0x8000135D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_0    , RULL(0x8000035D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_0    , RULL(0x8000035D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_1    , RULL(0x8000075D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_1    , RULL(0x8000075D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_2    , RULL(0x80000B5D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_2    , RULL(0x80000B5D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_3    , RULL(0x80000F5D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_3    , RULL(0x80000F5D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_4    , RULL(0x8000135D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P2_4    , RULL(0x8000135D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_0    , RULL(0x8000035D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_0    , RULL(0x8000035D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_1    , RULL(0x8000075D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_1    , RULL(0x8000075D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_2    , RULL(0x80000B5D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_2    , RULL(0x80000B5D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_3    , RULL(0x80000F5D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_3    , RULL(0x80000F5D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_4    , RULL(0x8000135D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P3_4    , RULL(0x8000135D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0                      , RULL(0x800000750701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_IO_TX_CONFIG0_P0_0                    , RULL(0x800000750701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_IO_TX_CONFIG0_P0_0                    , RULL(0x800000750801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1                      , RULL(0x800004750701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_IO_TX_CONFIG0_P0_1                    , RULL(0x800004750701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_IO_TX_CONFIG0_P0_1                    , RULL(0x800004750801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2                      , RULL(0x800008750701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_IO_TX_CONFIG0_P0_2                    , RULL(0x800008750701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_IO_TX_CONFIG0_P0_2                    , RULL(0x800008750801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3                      , RULL(0x80000C750701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_IO_TX_CONFIG0_P0_3                    , RULL(0x80000C750701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_IO_TX_CONFIG0_P0_3                    , RULL(0x80000C750801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4                      , RULL(0x800010750701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_IO_TX_CONFIG0_P0_4                    , RULL(0x800010750701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_IO_TX_CONFIG0_P0_4                    , RULL(0x800010750801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_IO_TX_CONFIG0_P1_0                    , RULL(0x800000750701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_IO_TX_CONFIG0_P1_0                    , RULL(0x800000750801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_IO_TX_CONFIG0_P1_1                    , RULL(0x800004750701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_IO_TX_CONFIG0_P1_1                    , RULL(0x800004750801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_IO_TX_CONFIG0_P1_2                    , RULL(0x800008750701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_IO_TX_CONFIG0_P1_2                    , RULL(0x800008750801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_IO_TX_CONFIG0_P1_3                    , RULL(0x80000C750701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_IO_TX_CONFIG0_P1_3                    , RULL(0x80000C750801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_IO_TX_CONFIG0_P1_4                    , RULL(0x800010750701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_IO_TX_CONFIG0_P1_4                    , RULL(0x800010750801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_IO_TX_CONFIG0_P2_0                    , RULL(0x800000750701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_IO_TX_CONFIG0_P2_0                    , RULL(0x800000750801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_IO_TX_CONFIG0_P2_1                    , RULL(0x800004750701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_IO_TX_CONFIG0_P2_1                    , RULL(0x800004750801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_IO_TX_CONFIG0_P2_2                    , RULL(0x800008750701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_IO_TX_CONFIG0_P2_2                    , RULL(0x800008750801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_IO_TX_CONFIG0_P2_3                    , RULL(0x80000C750701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_IO_TX_CONFIG0_P2_3                    , RULL(0x80000C750801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_IO_TX_CONFIG0_P2_4                    , RULL(0x800010750701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_IO_TX_CONFIG0_P2_4                    , RULL(0x800010750801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_IO_TX_CONFIG0_P3_0                    , RULL(0x8000007507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_IO_TX_CONFIG0_P3_0                    , RULL(0x8000007508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_IO_TX_CONFIG0_P3_1                    , RULL(0x8000047507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_IO_TX_CONFIG0_P3_1                    , RULL(0x8000047508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_IO_TX_CONFIG0_P3_2                    , RULL(0x8000087507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_IO_TX_CONFIG0_P3_2                    , RULL(0x8000087508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_IO_TX_CONFIG0_P3_3                    , RULL(0x80000C7507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_IO_TX_CONFIG0_P3_3                    , RULL(0x80000C7508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_IO_TX_CONFIG0_P3_4                    , RULL(0x8000107507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_IO_TX_CONFIG0_P3_4                    , RULL(0x8000107508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0                    , RULL(0x800000780701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0                  , RULL(0x800000780701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0                  , RULL(0x800000780801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1                    , RULL(0x800004780701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1                  , RULL(0x800004780701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1                  , RULL(0x800004780801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2                    , RULL(0x800008780701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2                  , RULL(0x800008780701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2                  , RULL(0x800008780801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3                    , RULL(0x80000C780701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3                  , RULL(0x80000C780701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3                  , RULL(0x80000C780801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4                    , RULL(0x800010780701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4                  , RULL(0x800010780701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4                  , RULL(0x800010780801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_IO_TX_FET_SLICE_P1_0                  , RULL(0x800000780701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_IO_TX_FET_SLICE_P1_0                  , RULL(0x800000780801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_IO_TX_FET_SLICE_P1_1                  , RULL(0x800004780701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_IO_TX_FET_SLICE_P1_1                  , RULL(0x800004780801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_IO_TX_FET_SLICE_P1_2                  , RULL(0x800008780701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_IO_TX_FET_SLICE_P1_2                  , RULL(0x800008780801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_IO_TX_FET_SLICE_P1_3                  , RULL(0x80000C780701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_IO_TX_FET_SLICE_P1_3                  , RULL(0x80000C780801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_IO_TX_FET_SLICE_P1_4                  , RULL(0x800010780701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_IO_TX_FET_SLICE_P1_4                  , RULL(0x800010780801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_IO_TX_FET_SLICE_P2_0                  , RULL(0x800000780701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_IO_TX_FET_SLICE_P2_0                  , RULL(0x800000780801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_IO_TX_FET_SLICE_P2_1                  , RULL(0x800004780701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_IO_TX_FET_SLICE_P2_1                  , RULL(0x800004780801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_IO_TX_FET_SLICE_P2_2                  , RULL(0x800008780701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_IO_TX_FET_SLICE_P2_2                  , RULL(0x800008780801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_IO_TX_FET_SLICE_P2_3                  , RULL(0x80000C780701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_IO_TX_FET_SLICE_P2_3                  , RULL(0x80000C780801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_IO_TX_FET_SLICE_P2_4                  , RULL(0x800010780701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_IO_TX_FET_SLICE_P2_4                  , RULL(0x800010780801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_IO_TX_FET_SLICE_P3_0                  , RULL(0x8000007807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_IO_TX_FET_SLICE_P3_0                  , RULL(0x8000007808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_IO_TX_FET_SLICE_P3_1                  , RULL(0x8000047807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_IO_TX_FET_SLICE_P3_1                  , RULL(0x8000047808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_IO_TX_FET_SLICE_P3_2                  , RULL(0x8000087807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_IO_TX_FET_SLICE_P3_2                  , RULL(0x8000087808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_IO_TX_FET_SLICE_P3_3                  , RULL(0x80000C7807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_IO_TX_FET_SLICE_P3_3                  , RULL(0x80000C7808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_IO_TX_FET_SLICE_P3_4                  , RULL(0x8000107807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_IO_TX_FET_SLICE_P3_4                  , RULL(0x8000107808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0                    , RULL(0x8000007B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0                  , RULL(0x8000007B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0                  , RULL(0x8000007B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1                    , RULL(0x8000047B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1                  , RULL(0x8000047B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1                  , RULL(0x8000047B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2                    , RULL(0x8000087B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2                  , RULL(0x8000087B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2                  , RULL(0x8000087B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3                    , RULL(0x80000C7B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3                  , RULL(0x80000C7B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3                  , RULL(0x80000C7B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4                    , RULL(0x8000107B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4                  , RULL(0x8000107B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4                  , RULL(0x8000107B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_IO_TX_PFET_TERM_P1_0                  , RULL(0x8000007B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_IO_TX_PFET_TERM_P1_0                  , RULL(0x8000007B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_IO_TX_PFET_TERM_P1_1                  , RULL(0x8000047B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_IO_TX_PFET_TERM_P1_1                  , RULL(0x8000047B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_IO_TX_PFET_TERM_P1_2                  , RULL(0x8000087B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_IO_TX_PFET_TERM_P1_2                  , RULL(0x8000087B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_IO_TX_PFET_TERM_P1_3                  , RULL(0x80000C7B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_IO_TX_PFET_TERM_P1_3                  , RULL(0x80000C7B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_IO_TX_PFET_TERM_P1_4                  , RULL(0x8000107B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_IO_TX_PFET_TERM_P1_4                  , RULL(0x8000107B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_IO_TX_PFET_TERM_P2_0                  , RULL(0x8000007B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_IO_TX_PFET_TERM_P2_0                  , RULL(0x8000007B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_IO_TX_PFET_TERM_P2_1                  , RULL(0x8000047B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_IO_TX_PFET_TERM_P2_1                  , RULL(0x8000047B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_IO_TX_PFET_TERM_P2_2                  , RULL(0x8000087B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_IO_TX_PFET_TERM_P2_2                  , RULL(0x8000087B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_IO_TX_PFET_TERM_P2_3                  , RULL(0x80000C7B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_IO_TX_PFET_TERM_P2_3                  , RULL(0x80000C7B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_IO_TX_PFET_TERM_P2_4                  , RULL(0x8000107B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_IO_TX_PFET_TERM_P2_4                  , RULL(0x8000107B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_IO_TX_PFET_TERM_P3_0                  , RULL(0x8000007B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_IO_TX_PFET_TERM_P3_0                  , RULL(0x8000007B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_IO_TX_PFET_TERM_P3_1                  , RULL(0x8000047B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_IO_TX_PFET_TERM_P3_1                  , RULL(0x8000047B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_IO_TX_PFET_TERM_P3_2                  , RULL(0x8000087B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_IO_TX_PFET_TERM_P3_2                  , RULL(0x8000087B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_IO_TX_PFET_TERM_P3_3                  , RULL(0x80000C7B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_IO_TX_PFET_TERM_P3_3                  , RULL(0x80000C7B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_IO_TX_PFET_TERM_P3_4                  , RULL(0x8000107B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_IO_TX_PFET_TERM_P3_4                  , RULL(0x8000107B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0                    , RULL(0x800000790701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_LO_PROBE_SELECT_P0_0                  , RULL(0x800000790701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_LO_PROBE_SELECT_P0_0                  , RULL(0x800000790801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1                    , RULL(0x800004790701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_LO_PROBE_SELECT_P0_1                  , RULL(0x800004790701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_LO_PROBE_SELECT_P0_1                  , RULL(0x800004790801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2                    , RULL(0x800008790701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_LO_PROBE_SELECT_P0_2                  , RULL(0x800008790701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_LO_PROBE_SELECT_P0_2                  , RULL(0x800008790801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3                    , RULL(0x80000C790701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_LO_PROBE_SELECT_P0_3                  , RULL(0x80000C790701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_LO_PROBE_SELECT_P0_3                  , RULL(0x80000C790801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4                    , RULL(0x800010790701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_LO_PROBE_SELECT_P0_4                  , RULL(0x800010790701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_LO_PROBE_SELECT_P0_4                  , RULL(0x800010790801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_LO_PROBE_SELECT_P1_0                  , RULL(0x800000790701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_LO_PROBE_SELECT_P1_0                  , RULL(0x800000790801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_LO_PROBE_SELECT_P1_1                  , RULL(0x800004790701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_LO_PROBE_SELECT_P1_1                  , RULL(0x800004790801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_LO_PROBE_SELECT_P1_2                  , RULL(0x800008790701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_LO_PROBE_SELECT_P1_2                  , RULL(0x800008790801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_LO_PROBE_SELECT_P1_3                  , RULL(0x80000C790701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_LO_PROBE_SELECT_P1_3                  , RULL(0x80000C790801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_LO_PROBE_SELECT_P1_4                  , RULL(0x800010790701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_LO_PROBE_SELECT_P1_4                  , RULL(0x800010790801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_LO_PROBE_SELECT_P2_0                  , RULL(0x800000790701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_LO_PROBE_SELECT_P2_0                  , RULL(0x800000790801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_LO_PROBE_SELECT_P2_1                  , RULL(0x800004790701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_LO_PROBE_SELECT_P2_1                  , RULL(0x800004790801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_LO_PROBE_SELECT_P2_2                  , RULL(0x800008790701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_LO_PROBE_SELECT_P2_2                  , RULL(0x800008790801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_LO_PROBE_SELECT_P2_3                  , RULL(0x80000C790701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_LO_PROBE_SELECT_P2_3                  , RULL(0x80000C790801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_LO_PROBE_SELECT_P2_4                  , RULL(0x800010790701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_LO_PROBE_SELECT_P2_4                  , RULL(0x800010790801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_LO_PROBE_SELECT_P3_0                  , RULL(0x8000007907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_LO_PROBE_SELECT_P3_0                  , RULL(0x8000007908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_LO_PROBE_SELECT_P3_1                  , RULL(0x8000047907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_LO_PROBE_SELECT_P3_1                  , RULL(0x8000047908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_LO_PROBE_SELECT_P3_2                  , RULL(0x8000087907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_LO_PROBE_SELECT_P3_2                  , RULL(0x8000087908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_LO_PROBE_SELECT_P3_3                  , RULL(0x80000C7907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_LO_PROBE_SELECT_P3_3                  , RULL(0x80000C7908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_LO_PROBE_SELECT_P3_4                  , RULL(0x8000107907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_LO_PROBE_SELECT_P3_4                  , RULL(0x8000107908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0                      , RULL(0x800000320701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_PATTERN_POS_0_P0_0                    , RULL(0x800000320701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_PATTERN_POS_0_P0_0                    , RULL(0x800000320801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1                      , RULL(0x800004320701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_PATTERN_POS_0_P0_1                    , RULL(0x800004320701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_PATTERN_POS_0_P0_1                    , RULL(0x800004320801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2                      , RULL(0x800008320701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_PATTERN_POS_0_P0_2                    , RULL(0x800008320701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_PATTERN_POS_0_P0_2                    , RULL(0x800008320801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3                      , RULL(0x80000C320701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_PATTERN_POS_0_P0_3                    , RULL(0x80000C320701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_PATTERN_POS_0_P0_3                    , RULL(0x80000C320801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4                      , RULL(0x800010320701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_PATTERN_POS_0_P0_4                    , RULL(0x800010320701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_PATTERN_POS_0_P0_4                    , RULL(0x800010320801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_PATTERN_POS_0_P1_0                    , RULL(0x800000320701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_PATTERN_POS_0_P1_0                    , RULL(0x800000320801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_PATTERN_POS_0_P1_1                    , RULL(0x800004320701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_PATTERN_POS_0_P1_1                    , RULL(0x800004320801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_PATTERN_POS_0_P1_2                    , RULL(0x800008320701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_PATTERN_POS_0_P1_2                    , RULL(0x800008320801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_PATTERN_POS_0_P1_3                    , RULL(0x80000C320701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_PATTERN_POS_0_P1_3                    , RULL(0x80000C320801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_PATTERN_POS_0_P1_4                    , RULL(0x800010320701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_PATTERN_POS_0_P1_4                    , RULL(0x800010320801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_PATTERN_POS_0_P2_0                    , RULL(0x800000320701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_PATTERN_POS_0_P2_0                    , RULL(0x800000320801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_PATTERN_POS_0_P2_1                    , RULL(0x800004320701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_PATTERN_POS_0_P2_1                    , RULL(0x800004320801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_PATTERN_POS_0_P2_2                    , RULL(0x800008320701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_PATTERN_POS_0_P2_2                    , RULL(0x800008320801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_PATTERN_POS_0_P2_3                    , RULL(0x80000C320701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_PATTERN_POS_0_P2_3                    , RULL(0x80000C320801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_PATTERN_POS_0_P2_4                    , RULL(0x800010320701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_PATTERN_POS_0_P2_4                    , RULL(0x800010320801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_PATTERN_POS_0_P3_0                    , RULL(0x8000003207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_PATTERN_POS_0_P3_0                    , RULL(0x8000003208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_PATTERN_POS_0_P3_1                    , RULL(0x8000043207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_PATTERN_POS_0_P3_1                    , RULL(0x8000043208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_PATTERN_POS_0_P3_2                    , RULL(0x8000083207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_PATTERN_POS_0_P3_2                    , RULL(0x8000083208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_PATTERN_POS_0_P3_3                    , RULL(0x80000C3207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_PATTERN_POS_0_P3_3                    , RULL(0x80000C3208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_PATTERN_POS_0_P3_4                    , RULL(0x8000103207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_PATTERN_POS_0_P3_4                    , RULL(0x8000103208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0                      , RULL(0x800000330701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_PATTERN_POS_1_P0_0                    , RULL(0x800000330701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_PATTERN_POS_1_P0_0                    , RULL(0x800000330801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1                      , RULL(0x800004330701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_PATTERN_POS_1_P0_1                    , RULL(0x800004330701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_PATTERN_POS_1_P0_1                    , RULL(0x800004330801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2                      , RULL(0x800008330701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_PATTERN_POS_1_P0_2                    , RULL(0x800008330701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_PATTERN_POS_1_P0_2                    , RULL(0x800008330801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3                      , RULL(0x80000C330701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_PATTERN_POS_1_P0_3                    , RULL(0x80000C330701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_PATTERN_POS_1_P0_3                    , RULL(0x80000C330801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4                      , RULL(0x800010330701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_PATTERN_POS_1_P0_4                    , RULL(0x800010330701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_PATTERN_POS_1_P0_4                    , RULL(0x800010330801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_PATTERN_POS_1_P1_0                    , RULL(0x800000330701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_PATTERN_POS_1_P1_0                    , RULL(0x800000330801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_PATTERN_POS_1_P1_1                    , RULL(0x800004330701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_PATTERN_POS_1_P1_1                    , RULL(0x800004330801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_PATTERN_POS_1_P1_2                    , RULL(0x800008330701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_PATTERN_POS_1_P1_2                    , RULL(0x800008330801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_PATTERN_POS_1_P1_3                    , RULL(0x80000C330701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_PATTERN_POS_1_P1_3                    , RULL(0x80000C330801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_PATTERN_POS_1_P1_4                    , RULL(0x800010330701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_PATTERN_POS_1_P1_4                    , RULL(0x800010330801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_PATTERN_POS_1_P2_0                    , RULL(0x800000330701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_PATTERN_POS_1_P2_0                    , RULL(0x800000330801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_PATTERN_POS_1_P2_1                    , RULL(0x800004330701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_PATTERN_POS_1_P2_1                    , RULL(0x800004330801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_PATTERN_POS_1_P2_2                    , RULL(0x800008330701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_PATTERN_POS_1_P2_2                    , RULL(0x800008330801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_PATTERN_POS_1_P2_3                    , RULL(0x80000C330701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_PATTERN_POS_1_P2_3                    , RULL(0x80000C330801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_PATTERN_POS_1_P2_4                    , RULL(0x800010330701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_PATTERN_POS_1_P2_4                    , RULL(0x800010330801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_PATTERN_POS_1_P3_0                    , RULL(0x8000003307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_PATTERN_POS_1_P3_0                    , RULL(0x8000003308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_PATTERN_POS_1_P3_1                    , RULL(0x8000043307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_PATTERN_POS_1_P3_1                    , RULL(0x8000043308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_PATTERN_POS_1_P3_2                    , RULL(0x8000083307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_PATTERN_POS_1_P3_2                    , RULL(0x8000083308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_PATTERN_POS_1_P3_3                    , RULL(0x80000C3307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_PATTERN_POS_1_P3_3                    , RULL(0x80000C3308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_PATTERN_POS_1_P3_4                    , RULL(0x8000103307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_PATTERN_POS_1_P3_4                    , RULL(0x8000103308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0                      , RULL(0x800000340701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_PATTERN_POS_2_P0_0                    , RULL(0x800000340701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_PATTERN_POS_2_P0_0                    , RULL(0x800000340801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1                      , RULL(0x800004340701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_PATTERN_POS_2_P0_1                    , RULL(0x800004340701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_PATTERN_POS_2_P0_1                    , RULL(0x800004340801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2                      , RULL(0x800008340701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_PATTERN_POS_2_P0_2                    , RULL(0x800008340701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_PATTERN_POS_2_P0_2                    , RULL(0x800008340801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3                      , RULL(0x80000C340701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_PATTERN_POS_2_P0_3                    , RULL(0x80000C340701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_PATTERN_POS_2_P0_3                    , RULL(0x80000C340801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4                      , RULL(0x800010340701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_PATTERN_POS_2_P0_4                    , RULL(0x800010340701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_PATTERN_POS_2_P0_4                    , RULL(0x800010340801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_PATTERN_POS_2_P1_0                    , RULL(0x800000340701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_PATTERN_POS_2_P1_0                    , RULL(0x800000340801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_PATTERN_POS_2_P1_1                    , RULL(0x800004340701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_PATTERN_POS_2_P1_1                    , RULL(0x800004340801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_PATTERN_POS_2_P1_2                    , RULL(0x800008340701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_PATTERN_POS_2_P1_2                    , RULL(0x800008340801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_PATTERN_POS_2_P1_3                    , RULL(0x80000C340701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_PATTERN_POS_2_P1_3                    , RULL(0x80000C340801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_PATTERN_POS_2_P1_4                    , RULL(0x800010340701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_PATTERN_POS_2_P1_4                    , RULL(0x800010340801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_PATTERN_POS_2_P2_0                    , RULL(0x800000340701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_PATTERN_POS_2_P2_0                    , RULL(0x800000340801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_PATTERN_POS_2_P2_1                    , RULL(0x800004340701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_PATTERN_POS_2_P2_1                    , RULL(0x800004340801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_PATTERN_POS_2_P2_2                    , RULL(0x800008340701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_PATTERN_POS_2_P2_2                    , RULL(0x800008340801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_PATTERN_POS_2_P2_3                    , RULL(0x80000C340701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_PATTERN_POS_2_P2_3                    , RULL(0x80000C340801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_PATTERN_POS_2_P2_4                    , RULL(0x800010340701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_PATTERN_POS_2_P2_4                    , RULL(0x800010340801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_PATTERN_POS_2_P3_0                    , RULL(0x8000003407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_PATTERN_POS_2_P3_0                    , RULL(0x8000003408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_PATTERN_POS_2_P3_1                    , RULL(0x8000043407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_PATTERN_POS_2_P3_1                    , RULL(0x8000043408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_PATTERN_POS_2_P3_2                    , RULL(0x8000083407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_PATTERN_POS_2_P3_2                    , RULL(0x8000083408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_PATTERN_POS_2_P3_3                    , RULL(0x80000C3407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_PATTERN_POS_2_P3_3                    , RULL(0x80000C3408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_PATTERN_POS_2_P3_4                    , RULL(0x8000103407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_PATTERN_POS_2_P3_4                    , RULL(0x8000103408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0                     , RULL(0x8000001E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0                   , RULL(0x8000001E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0                   , RULL(0x8000001E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1                     , RULL(0x8000041E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1                   , RULL(0x8000041E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1                   , RULL(0x8000041E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2                     , RULL(0x8000081E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2                   , RULL(0x8000081E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2                   , RULL(0x8000081E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3                     , RULL(0x80000C1E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3                   , RULL(0x80000C1E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3                   , RULL(0x80000C1E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4                     , RULL(0x8000101E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4                   , RULL(0x8000101E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4                   , RULL(0x8000101E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG0_P1_0                   , RULL(0x8000001E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG0_P1_0                   , RULL(0x8000001E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG0_P1_1                   , RULL(0x8000041E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG0_P1_1                   , RULL(0x8000041E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG0_P1_2                   , RULL(0x8000081E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG0_P1_2                   , RULL(0x8000081E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG0_P1_3                   , RULL(0x80000C1E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG0_P1_3                   , RULL(0x80000C1E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG0_P1_4                   , RULL(0x8000101E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG0_P1_4                   , RULL(0x8000101E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG0_P2_0                   , RULL(0x8000001E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG0_P2_0                   , RULL(0x8000001E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG0_P2_1                   , RULL(0x8000041E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG0_P2_1                   , RULL(0x8000041E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG0_P2_2                   , RULL(0x8000081E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG0_P2_2                   , RULL(0x8000081E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG0_P2_3                   , RULL(0x80000C1E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG0_P2_3                   , RULL(0x80000C1E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG0_P2_4                   , RULL(0x8000101E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG0_P2_4                   , RULL(0x8000101E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG0_P3_0                   , RULL(0x8000001E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG0_P3_0                   , RULL(0x8000001E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG0_P3_1                   , RULL(0x8000041E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG0_P3_1                   , RULL(0x8000041E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG0_P3_2                   , RULL(0x8000081E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG0_P3_2                   , RULL(0x8000081E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG0_P3_3                   , RULL(0x80000C1E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG0_P3_3                   , RULL(0x80000C1E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG0_P3_4                   , RULL(0x8000101E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG0_P3_4                   , RULL(0x8000101E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0                     , RULL(0x800000350701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0                   , RULL(0x800000350701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0                   , RULL(0x800000350801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1                     , RULL(0x800004350701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1                   , RULL(0x800004350701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1                   , RULL(0x800004350801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2                     , RULL(0x800008350701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2                   , RULL(0x800008350701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2                   , RULL(0x800008350801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3                     , RULL(0x80000C350701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3                   , RULL(0x80000C350701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3                   , RULL(0x80000C350801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4                     , RULL(0x800010350701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4                   , RULL(0x800010350701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4                   , RULL(0x800010350801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG1_P1_0                   , RULL(0x800000350701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG1_P1_0                   , RULL(0x800000350801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG1_P1_1                   , RULL(0x800004350701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG1_P1_1                   , RULL(0x800004350801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG1_P1_2                   , RULL(0x800008350701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG1_P1_2                   , RULL(0x800008350801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG1_P1_3                   , RULL(0x80000C350701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG1_P1_3                   , RULL(0x80000C350801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG1_P1_4                   , RULL(0x800010350701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG1_P1_4                   , RULL(0x800010350801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG1_P2_0                   , RULL(0x800000350701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG1_P2_0                   , RULL(0x800000350801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG1_P2_1                   , RULL(0x800004350701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG1_P2_1                   , RULL(0x800004350801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG1_P2_2                   , RULL(0x800008350701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG1_P2_2                   , RULL(0x800008350801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG1_P2_3                   , RULL(0x80000C350701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG1_P2_3                   , RULL(0x80000C350801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG1_P2_4                   , RULL(0x800010350701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG1_P2_4                   , RULL(0x800010350801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG1_P3_0                   , RULL(0x8000003507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG1_P3_0                   , RULL(0x8000003508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG1_P3_1                   , RULL(0x8000043507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG1_P3_1                   , RULL(0x8000043508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG1_P3_2                   , RULL(0x8000083507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG1_P3_2                   , RULL(0x8000083508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG1_P3_3                   , RULL(0x80000C3507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG1_P3_3                   , RULL(0x80000C3508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG1_P3_4                   , RULL(0x8000103507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG1_P3_4                   , RULL(0x8000103508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0                     , RULL(0x800000360701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0                   , RULL(0x800000360701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0                   , RULL(0x800000360801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1                     , RULL(0x800004360701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1                   , RULL(0x800004360701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1                   , RULL(0x800004360801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2                     , RULL(0x800008360701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2                   , RULL(0x800008360701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2                   , RULL(0x800008360801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3                     , RULL(0x80000C360701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3                   , RULL(0x80000C360701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3                   , RULL(0x80000C360801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4                     , RULL(0x800010360701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM      );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4                   , RULL(0x800010360701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM      );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4                   , RULL(0x800010360801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG2_P1_0                   , RULL(0x800000360701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG2_P1_0                   , RULL(0x800000360801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG2_P1_1                   , RULL(0x800004360701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG2_P1_1                   , RULL(0x800004360801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG2_P1_2                   , RULL(0x800008360701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG2_P1_2                   , RULL(0x800008360801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG2_P1_3                   , RULL(0x80000C360701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG2_P1_3                   , RULL(0x80000C360801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG2_P1_4                   , RULL(0x800010360701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM      );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG2_P1_4                   , RULL(0x800010360801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG2_P2_0                   , RULL(0x800000360701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG2_P2_0                   , RULL(0x800000360801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG2_P2_1                   , RULL(0x800004360701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG2_P2_1                   , RULL(0x800004360801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG2_P2_2                   , RULL(0x800008360701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG2_P2_2                   , RULL(0x800008360801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG2_P2_3                   , RULL(0x80000C360701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG2_P2_3                   , RULL(0x80000C360801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG2_P2_4                   , RULL(0x800010360701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM      );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG2_P2_4                   , RULL(0x800010360801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG2_P3_0                   , RULL(0x8000003607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG2_P3_0                   , RULL(0x8000003608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG2_P3_1                   , RULL(0x8000043607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG2_P3_1                   , RULL(0x8000043608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG2_P3_2                   , RULL(0x8000083607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG2_P3_2                   , RULL(0x8000083608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG2_P3_3                   , RULL(0x80000C3607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG2_P3_3                   , RULL(0x80000C3608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG2_P3_4                   , RULL(0x8000103607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM      );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG2_P3_4                   , RULL(0x8000103608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM      );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0                     , RULL(0x8000006D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0                   , RULL(0x8000006D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0                   , RULL(0x8000006D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1                     , RULL(0x8000046D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1                   , RULL(0x8000046D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1                   , RULL(0x8000046D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2                     , RULL(0x8000086D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2                   , RULL(0x8000086D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2                   , RULL(0x8000086D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3                     , RULL(0x80000C6D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3                   , RULL(0x80000C6D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3                   , RULL(0x80000C6D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4                     , RULL(0x8000106D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4                   , RULL(0x8000106D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4                   , RULL(0x8000106D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG3_P1_0                   , RULL(0x8000006D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG3_P1_0                   , RULL(0x8000006D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG3_P1_1                   , RULL(0x8000046D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG3_P1_1                   , RULL(0x8000046D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG3_P1_2                   , RULL(0x8000086D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG3_P1_2                   , RULL(0x8000086D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG3_P1_3                   , RULL(0x80000C6D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG3_P1_3                   , RULL(0x80000C6D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG3_P1_4                   , RULL(0x8000106D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG3_P1_4                   , RULL(0x8000106D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG3_P2_0                   , RULL(0x8000006D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG3_P2_0                   , RULL(0x8000006D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG3_P2_1                   , RULL(0x8000046D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG3_P2_1                   , RULL(0x8000046D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG3_P2_2                   , RULL(0x8000086D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG3_P2_2                   , RULL(0x8000086D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG3_P2_3                   , RULL(0x80000C6D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG3_P2_3                   , RULL(0x80000C6D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG3_P2_4                   , RULL(0x8000106D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG3_P2_4                   , RULL(0x8000106D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG3_P3_0                   , RULL(0x8000006D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG3_P3_0                   , RULL(0x8000006D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG3_P3_1                   , RULL(0x8000046D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG3_P3_1                   , RULL(0x8000046D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG3_P3_2                   , RULL(0x8000086D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG3_P3_2                   , RULL(0x8000086D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG3_P3_3                   , RULL(0x80000C6D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG3_P3_3                   , RULL(0x80000C6D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG3_P3_4                   , RULL(0x8000106D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG3_P3_4                   , RULL(0x8000106D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_0                     , RULL(0x8000006E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG4_P0_0                   , RULL(0x8000006E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG4_P0_0                   , RULL(0x8000006E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_1                     , RULL(0x8000046E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG4_P0_1                   , RULL(0x8000046E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG4_P0_1                   , RULL(0x8000046E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_2                     , RULL(0x8000086E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG4_P0_2                   , RULL(0x8000086E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG4_P0_2                   , RULL(0x8000086E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_3                     , RULL(0x80000C6E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG4_P0_3                   , RULL(0x80000C6E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG4_P0_3                   , RULL(0x80000C6E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_4                     , RULL(0x8000106E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG4_P0_4                   , RULL(0x8000106E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG4_P0_4                   , RULL(0x8000106E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG4_P1_0                   , RULL(0x8000006E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG4_P1_0                   , RULL(0x8000006E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG4_P1_1                   , RULL(0x8000046E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG4_P1_1                   , RULL(0x8000046E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG4_P1_2                   , RULL(0x8000086E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG4_P1_2                   , RULL(0x8000086E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG4_P1_3                   , RULL(0x80000C6E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG4_P1_3                   , RULL(0x80000C6E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG4_P1_4                   , RULL(0x8000106E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG4_P1_4                   , RULL(0x8000106E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG4_P2_0                   , RULL(0x8000006E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG4_P2_0                   , RULL(0x8000006E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG4_P2_1                   , RULL(0x8000046E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG4_P2_1                   , RULL(0x8000046E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG4_P2_2                   , RULL(0x8000086E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG4_P2_2                   , RULL(0x8000086E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG4_P2_3                   , RULL(0x80000C6E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG4_P2_3                   , RULL(0x80000C6E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG4_P2_4                   , RULL(0x8000106E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG4_P2_4                   , RULL(0x8000106E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG4_P3_0                   , RULL(0x8000006E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG4_P3_0                   , RULL(0x8000006E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG4_P3_1                   , RULL(0x8000046E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG4_P3_1                   , RULL(0x8000046E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG4_P3_2                   , RULL(0x8000086E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG4_P3_2                   , RULL(0x8000086E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG4_P3_3                   , RULL(0x80000C6E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG4_P3_3                   , RULL(0x80000C6E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG4_P3_4                   , RULL(0x8000106E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG4_P3_4                   , RULL(0x8000106E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0                     , RULL(0x800000120701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0                   , RULL(0x800000120701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0                   , RULL(0x800000120801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1                     , RULL(0x800004120701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1                   , RULL(0x800004120701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1                   , RULL(0x800004120801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2                     , RULL(0x800008120701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2                   , RULL(0x800008120701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2                   , RULL(0x800008120801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3                     , RULL(0x80000C120701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3                   , RULL(0x80000C120701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3                   , RULL(0x80000C120801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4                     , RULL(0x800010120701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4                   , RULL(0x800010120701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4                   , RULL(0x800010120801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG5_P1_0                   , RULL(0x800000120701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG5_P1_0                   , RULL(0x800000120801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG5_P1_1                   , RULL(0x800004120701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG5_P1_1                   , RULL(0x800004120801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG5_P1_2                   , RULL(0x800008120701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG5_P1_2                   , RULL(0x800008120801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG5_P1_3                   , RULL(0x80000C120701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG5_P1_3                   , RULL(0x80000C120801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_DIA_CONFIG5_P1_4                   , RULL(0x800010120701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_DIA_CONFIG5_P1_4                   , RULL(0x800010120801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG5_P2_0                   , RULL(0x800000120701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG5_P2_0                   , RULL(0x800000120801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG5_P2_1                   , RULL(0x800004120701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG5_P2_1                   , RULL(0x800004120801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG5_P2_2                   , RULL(0x800008120701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG5_P2_2                   , RULL(0x800008120801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG5_P2_3                   , RULL(0x80000C120701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG5_P2_3                   , RULL(0x80000C120801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_DIA_CONFIG5_P2_4                   , RULL(0x800010120701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_DIA_CONFIG5_P2_4                   , RULL(0x800010120801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG5_P3_0                   , RULL(0x8000001207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG5_P3_0                   , RULL(0x8000001208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG5_P3_1                   , RULL(0x8000041207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG5_P3_1                   , RULL(0x8000041208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG5_P3_2                   , RULL(0x8000081207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG5_P3_2                   , RULL(0x8000081208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG5_P3_3                   , RULL(0x80000C1207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG5_P3_3                   , RULL(0x80000C1208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_DIA_CONFIG5_P3_4                   , RULL(0x8000101207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_DIA_CONFIG5_P3_4                   , RULL(0x8000101208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0                     , RULL(0x800000150701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_ERROR_MASK0_P0_0                   , RULL(0x800000150701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_ERROR_MASK0_P0_0                   , RULL(0x800000150801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1                     , RULL(0x800004150701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_ERROR_MASK0_P0_1                   , RULL(0x800004150701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_ERROR_MASK0_P0_1                   , RULL(0x800004150801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2                     , RULL(0x800008150701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_ERROR_MASK0_P0_2                   , RULL(0x800008150701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_ERROR_MASK0_P0_2                   , RULL(0x800008150801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3                     , RULL(0x80000C150701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_ERROR_MASK0_P0_3                   , RULL(0x80000C150701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_ERROR_MASK0_P0_3                   , RULL(0x80000C150801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4                     , RULL(0x800010150701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_ERROR_MASK0_P0_4                   , RULL(0x800010150701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_ERROR_MASK0_P0_4                   , RULL(0x800010150801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_ERROR_MASK0_P1_0                   , RULL(0x800000150701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_ERROR_MASK0_P1_0                   , RULL(0x800000150801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_ERROR_MASK0_P1_1                   , RULL(0x800004150701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_ERROR_MASK0_P1_1                   , RULL(0x800004150801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_ERROR_MASK0_P1_2                   , RULL(0x800008150701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_ERROR_MASK0_P1_2                   , RULL(0x800008150801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_ERROR_MASK0_P1_3                   , RULL(0x80000C150701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_ERROR_MASK0_P1_3                   , RULL(0x80000C150801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_ERROR_MASK0_P1_4                   , RULL(0x800010150701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_ERROR_MASK0_P1_4                   , RULL(0x800010150801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_ERROR_MASK0_P2_0                   , RULL(0x800000150701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_ERROR_MASK0_P2_0                   , RULL(0x800000150801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_ERROR_MASK0_P2_1                   , RULL(0x800004150701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_ERROR_MASK0_P2_1                   , RULL(0x800004150801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_ERROR_MASK0_P2_2                   , RULL(0x800008150701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_ERROR_MASK0_P2_2                   , RULL(0x800008150801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_ERROR_MASK0_P2_3                   , RULL(0x80000C150701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_ERROR_MASK0_P2_3                   , RULL(0x80000C150801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_ERROR_MASK0_P2_4                   , RULL(0x800010150701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_ERROR_MASK0_P2_4                   , RULL(0x800010150801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_ERROR_MASK0_P3_0                   , RULL(0x8000001507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_ERROR_MASK0_P3_0                   , RULL(0x8000001508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_ERROR_MASK0_P3_1                   , RULL(0x8000041507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_ERROR_MASK0_P3_1                   , RULL(0x8000041508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_ERROR_MASK0_P3_2                   , RULL(0x8000081507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_ERROR_MASK0_P3_2                   , RULL(0x8000081508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_ERROR_MASK0_P3_3                   , RULL(0x80000C1507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_ERROR_MASK0_P3_3                   , RULL(0x80000C1508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_ERROR_MASK0_P3_4                   , RULL(0x8000101507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_ERROR_MASK0_P3_4                   , RULL(0x8000101508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_0                     , RULL(0x8000000E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS0_P0_0                   , RULL(0x8000000E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS0_P0_0                   , RULL(0x8000000E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_1                     , RULL(0x8000040E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS0_P0_1                   , RULL(0x8000040E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS0_P0_1                   , RULL(0x8000040E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_2                     , RULL(0x8000080E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS0_P0_2                   , RULL(0x8000080E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS0_P0_2                   , RULL(0x8000080E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_3                     , RULL(0x80000C0E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS0_P0_3                   , RULL(0x80000C0E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS0_P0_3                   , RULL(0x80000C0E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_4                     , RULL(0x8000100E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS0_P0_4                   , RULL(0x8000100E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS0_P0_4                   , RULL(0x8000100E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS0_P1_0                   , RULL(0x8000000E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS0_P1_0                   , RULL(0x8000000E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS0_P1_1                   , RULL(0x8000040E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS0_P1_1                   , RULL(0x8000040E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS0_P1_2                   , RULL(0x8000080E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS0_P1_2                   , RULL(0x8000080E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS0_P1_3                   , RULL(0x80000C0E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS0_P1_3                   , RULL(0x80000C0E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS0_P1_4                   , RULL(0x8000100E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS0_P1_4                   , RULL(0x8000100E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS0_P2_0                   , RULL(0x8000000E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS0_P2_0                   , RULL(0x8000000E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS0_P2_1                   , RULL(0x8000040E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS0_P2_1                   , RULL(0x8000040E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS0_P2_2                   , RULL(0x8000080E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS0_P2_2                   , RULL(0x8000080E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS0_P2_3                   , RULL(0x80000C0E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS0_P2_3                   , RULL(0x80000C0E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS0_P2_4                   , RULL(0x8000100E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS0_P2_4                   , RULL(0x8000100E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS0_P3_0                   , RULL(0x8000000E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS0_P3_0                   , RULL(0x8000000E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS0_P3_1                   , RULL(0x8000040E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS0_P3_1                   , RULL(0x8000040E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS0_P3_2                   , RULL(0x8000080E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS0_P3_2                   , RULL(0x8000080E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS0_P3_3                   , RULL(0x80000C0E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS0_P3_3                   , RULL(0x80000C0E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS0_P3_4                   , RULL(0x8000100E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS0_P3_4                   , RULL(0x8000100E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_0                     , RULL(0x8000000F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS1_P0_0                   , RULL(0x8000000F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS1_P0_0                   , RULL(0x8000000F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_1                     , RULL(0x8000040F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS1_P0_1                   , RULL(0x8000040F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS1_P0_1                   , RULL(0x8000040F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_2                     , RULL(0x8000080F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS1_P0_2                   , RULL(0x8000080F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS1_P0_2                   , RULL(0x8000080F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_3                     , RULL(0x80000C0F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS1_P0_3                   , RULL(0x80000C0F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS1_P0_3                   , RULL(0x80000C0F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_4                     , RULL(0x8000100F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS1_P0_4                   , RULL(0x8000100F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS1_P0_4                   , RULL(0x8000100F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS1_P1_0                   , RULL(0x8000000F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS1_P1_0                   , RULL(0x8000000F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS1_P1_1                   , RULL(0x8000040F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS1_P1_1                   , RULL(0x8000040F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS1_P1_2                   , RULL(0x8000080F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS1_P1_2                   , RULL(0x8000080F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS1_P1_3                   , RULL(0x80000C0F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS1_P1_3                   , RULL(0x80000C0F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS1_P1_4                   , RULL(0x8000100F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS1_P1_4                   , RULL(0x8000100F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS1_P2_0                   , RULL(0x8000000F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS1_P2_0                   , RULL(0x8000000F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS1_P2_1                   , RULL(0x8000040F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS1_P2_1                   , RULL(0x8000040F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS1_P2_2                   , RULL(0x8000080F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS1_P2_2                   , RULL(0x8000080F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS1_P2_3                   , RULL(0x80000C0F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS1_P2_3                   , RULL(0x80000C0F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS1_P2_4                   , RULL(0x8000100F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS1_P2_4                   , RULL(0x8000100F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS1_P3_0                   , RULL(0x8000000F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS1_P3_0                   , RULL(0x8000000F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS1_P3_1                   , RULL(0x8000040F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS1_P3_1                   , RULL(0x8000040F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS1_P3_2                   , RULL(0x8000080F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS1_P3_2                   , RULL(0x8000080F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS1_P3_3                   , RULL(0x80000C0F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS1_P3_3                   , RULL(0x80000C0F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS1_P3_4                   , RULL(0x8000100F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS1_P3_4                   , RULL(0x8000100F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_0                     , RULL(0x800000100701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS2_P0_0                   , RULL(0x800000100701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS2_P0_0                   , RULL(0x800000100801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_1                     , RULL(0x800004100701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS2_P0_1                   , RULL(0x800004100701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS2_P0_1                   , RULL(0x800004100801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_2                     , RULL(0x800008100701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS2_P0_2                   , RULL(0x800008100701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS2_P0_2                   , RULL(0x800008100801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_3                     , RULL(0x80000C100701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS2_P0_3                   , RULL(0x80000C100701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS2_P0_3                   , RULL(0x80000C100801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_4                     , RULL(0x800010100701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS2_P0_4                   , RULL(0x800010100701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS2_P0_4                   , RULL(0x800010100801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS2_P1_0                   , RULL(0x800000100701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS2_P1_0                   , RULL(0x800000100801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS2_P1_1                   , RULL(0x800004100701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS2_P1_1                   , RULL(0x800004100801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS2_P1_2                   , RULL(0x800008100701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS2_P1_2                   , RULL(0x800008100801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS2_P1_3                   , RULL(0x80000C100701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS2_P1_3                   , RULL(0x80000C100801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS2_P1_4                   , RULL(0x800010100701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS2_P1_4                   , RULL(0x800010100801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS2_P2_0                   , RULL(0x800000100701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS2_P2_0                   , RULL(0x800000100801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS2_P2_1                   , RULL(0x800004100701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS2_P2_1                   , RULL(0x800004100801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS2_P2_2                   , RULL(0x800008100701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS2_P2_2                   , RULL(0x800008100801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS2_P2_3                   , RULL(0x80000C100701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS2_P2_3                   , RULL(0x80000C100801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS2_P2_4                   , RULL(0x800010100701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS2_P2_4                   , RULL(0x800010100801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS2_P3_0                   , RULL(0x8000001007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS2_P3_0                   , RULL(0x8000001008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS2_P3_1                   , RULL(0x8000041007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS2_P3_1                   , RULL(0x8000041008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS2_P3_2                   , RULL(0x8000081007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS2_P3_2                   , RULL(0x8000081008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS2_P3_3                   , RULL(0x80000C1007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS2_P3_3                   , RULL(0x80000C1008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS2_P3_4                   , RULL(0x8000101007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS2_P3_4                   , RULL(0x8000101008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_0                     , RULL(0x800000110701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS3_P0_0                   , RULL(0x800000110701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS3_P0_0                   , RULL(0x800000110801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_1                     , RULL(0x800004110701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS3_P0_1                   , RULL(0x800004110701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS3_P0_1                   , RULL(0x800004110801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_2                     , RULL(0x800008110701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS3_P0_2                   , RULL(0x800008110701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS3_P0_2                   , RULL(0x800008110801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_3                     , RULL(0x80000C110701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS3_P0_3                   , RULL(0x80000C110701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS3_P0_3                   , RULL(0x80000C110801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_4                     , RULL(0x800010110701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_LVL_STATUS3_P0_4                   , RULL(0x800010110701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_LVL_STATUS3_P0_4                   , RULL(0x800010110801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS3_P1_0                   , RULL(0x800000110701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS3_P1_0                   , RULL(0x800000110801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS3_P1_1                   , RULL(0x800004110701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS3_P1_1                   , RULL(0x800004110801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS3_P1_2                   , RULL(0x800008110701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS3_P1_2                   , RULL(0x800008110801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS3_P1_3                   , RULL(0x80000C110701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS3_P1_3                   , RULL(0x80000C110801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_LVL_STATUS3_P1_4                   , RULL(0x800010110701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_LVL_STATUS3_P1_4                   , RULL(0x800010110801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS3_P2_0                   , RULL(0x800000110701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS3_P2_0                   , RULL(0x800000110801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS3_P2_1                   , RULL(0x800004110701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS3_P2_1                   , RULL(0x800004110801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS3_P2_2                   , RULL(0x800008110701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS3_P2_2                   , RULL(0x800008110801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS3_P2_3                   , RULL(0x80000C110701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS3_P2_3                   , RULL(0x80000C110801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_LVL_STATUS3_P2_4                   , RULL(0x800010110701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_LVL_STATUS3_P2_4                   , RULL(0x800010110801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS3_P3_0                   , RULL(0x8000001107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS3_P3_0                   , RULL(0x8000001108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS3_P3_1                   , RULL(0x8000041107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS3_P3_1                   , RULL(0x8000041108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS3_P3_2                   , RULL(0x8000081107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS3_P3_2                   , RULL(0x8000081108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS3_P3_3                   , RULL(0x80000C1107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS3_P3_3                   , RULL(0x80000C1108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_LVL_STATUS3_P3_4                   , RULL(0x8000101107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_LVL_STATUS3_P3_4                   , RULL(0x8000101108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_STATUS0_P0_0                         , RULL(0x800000140701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_STATUS0_P0_0                       , RULL(0x800000140701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_STATUS0_P0_0                       , RULL(0x800000140801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_STATUS0_P0_1                         , RULL(0x800004140701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_STATUS0_P0_1                       , RULL(0x800004140701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_STATUS0_P0_1                       , RULL(0x800004140801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_STATUS0_P0_2                         , RULL(0x800008140701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_STATUS0_P0_2                       , RULL(0x800008140701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_STATUS0_P0_2                       , RULL(0x800008140801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_STATUS0_P0_3                         , RULL(0x80000C140701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_STATUS0_P0_3                       , RULL(0x80000C140701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_STATUS0_P0_3                       , RULL(0x80000C140801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_STATUS0_P0_4                         , RULL(0x800010140701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_STATUS0_P0_4                       , RULL(0x800010140701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_STATUS0_P0_4                       , RULL(0x800010140801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_STATUS0_P1_0                       , RULL(0x800000140701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_STATUS0_P1_0                       , RULL(0x800000140801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_STATUS0_P1_1                       , RULL(0x800004140701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_STATUS0_P1_1                       , RULL(0x800004140801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_STATUS0_P1_2                       , RULL(0x800008140701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_STATUS0_P1_2                       , RULL(0x800008140801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_STATUS0_P1_3                       , RULL(0x80000C140701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_STATUS0_P1_3                       , RULL(0x80000C140801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_STATUS0_P1_4                       , RULL(0x800010140701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_STATUS0_P1_4                       , RULL(0x800010140801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_STATUS0_P2_0                       , RULL(0x800000140701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_STATUS0_P2_0                       , RULL(0x800000140801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_STATUS0_P2_1                       , RULL(0x800004140701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_STATUS0_P2_1                       , RULL(0x800004140801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_STATUS0_P2_2                       , RULL(0x800008140701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_STATUS0_P2_2                       , RULL(0x800008140801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_STATUS0_P2_3                       , RULL(0x80000C140701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_STATUS0_P2_3                       , RULL(0x80000C140801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_STATUS0_P2_4                       , RULL(0x800010140701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_STATUS0_P2_4                       , RULL(0x800010140801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_STATUS0_P3_0                       , RULL(0x8000001407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_STATUS0_P3_0                       , RULL(0x8000001408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_STATUS0_P3_1                       , RULL(0x8000041407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_STATUS0_P3_1                       , RULL(0x8000041408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_STATUS0_P3_2                       , RULL(0x8000081407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_STATUS0_P3_2                       , RULL(0x8000081408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_STATUS0_P3_3                       , RULL(0x80000C1407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_STATUS0_P3_3                       , RULL(0x80000C1408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_STATUS0_P3_4                       , RULL(0x8000101407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_STATUS0_P3_4                       , RULL(0x8000101408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0                  , RULL(0x800000160701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0                , RULL(0x800000160701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0                , RULL(0x800000160801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1                  , RULL(0x800004160701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1                , RULL(0x800004160701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1                , RULL(0x800004160801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2                  , RULL(0x800008160701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2                , RULL(0x800008160701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2                , RULL(0x800008160801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3                  , RULL(0x80000C160701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3                , RULL(0x80000C160701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3                , RULL(0x80000C160801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4                  , RULL(0x800010160701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4                , RULL(0x800010160701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4                , RULL(0x800010160801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P1_0                , RULL(0x800000160701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P1_0                , RULL(0x800000160801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P1_1                , RULL(0x800004160701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P1_1                , RULL(0x800004160801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P1_2                , RULL(0x800008160701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P1_2                , RULL(0x800008160801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P1_3                , RULL(0x80000C160701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P1_3                , RULL(0x80000C160801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P1_4                , RULL(0x800010160701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P1_4                , RULL(0x800010160801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P2_0                , RULL(0x800000160701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P2_0                , RULL(0x800000160801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P2_1                , RULL(0x800004160701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P2_1                , RULL(0x800004160801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P2_2                , RULL(0x800008160701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P2_2                , RULL(0x800008160801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P2_3                , RULL(0x80000C160701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P2_3                , RULL(0x80000C160801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P2_4                , RULL(0x800010160701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P2_4                , RULL(0x800010160801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P3_0                , RULL(0x8000001607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P3_0                , RULL(0x8000001608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P3_1                , RULL(0x8000041607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P3_1                , RULL(0x8000041608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P3_2                , RULL(0x8000081607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P3_2                , RULL(0x8000081608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P3_3                , RULL(0x80000C1607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P3_3                , RULL(0x80000C1608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P3_4                , RULL(0x8000101607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P3_4                , RULL(0x8000101608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0                  , RULL(0x8000001F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0                , RULL(0x8000001F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0                , RULL(0x8000001F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1                  , RULL(0x8000041F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1                , RULL(0x8000041F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1                , RULL(0x8000041F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2                  , RULL(0x8000081F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2                , RULL(0x8000081F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2                , RULL(0x8000081F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3                  , RULL(0x80000C1F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3                , RULL(0x80000C1F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3                , RULL(0x80000C1F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4                  , RULL(0x8000101F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4                , RULL(0x8000101F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4                , RULL(0x8000101F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P1_0                , RULL(0x8000001F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P1_0                , RULL(0x8000001F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P1_1                , RULL(0x8000041F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P1_1                , RULL(0x8000041F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P1_2                , RULL(0x8000081F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P1_2                , RULL(0x8000081F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P1_3                , RULL(0x80000C1F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P1_3                , RULL(0x80000C1F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P1_4                , RULL(0x8000101F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P1_4                , RULL(0x8000101F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P2_0                , RULL(0x8000001F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P2_0                , RULL(0x8000001F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P2_1                , RULL(0x8000041F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P2_1                , RULL(0x8000041F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P2_2                , RULL(0x8000081F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P2_2                , RULL(0x8000081F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P2_3                , RULL(0x80000C1F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P2_3                , RULL(0x80000C1F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P2_4                , RULL(0x8000101F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P2_4                , RULL(0x8000101F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P3_0                , RULL(0x8000001F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P3_0                , RULL(0x8000001F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P3_1                , RULL(0x8000041F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P3_1                , RULL(0x8000041F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P3_2                , RULL(0x8000081F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P3_2                , RULL(0x8000081F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P3_3                , RULL(0x80000C1F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P3_3                , RULL(0x80000C1F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P3_4                , RULL(0x8000101F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P3_4                , RULL(0x8000101F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0                     , RULL(0x800000760701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0                   , RULL(0x800000760701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0                   , RULL(0x800000760801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1                     , RULL(0x800004760701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1                   , RULL(0x800004760701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1                   , RULL(0x800004760801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2                     , RULL(0x800008760701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2                   , RULL(0x800008760701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2                   , RULL(0x800008760801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3                     , RULL(0x80000C760701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3                   , RULL(0x80000C760701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3                   , RULL(0x80000C760801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4                     , RULL(0x800010760701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4                   , RULL(0x800010760701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4                   , RULL(0x800010760801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_CAL_EN_P1_0                   , RULL(0x800000760701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_CAL_EN_P1_0                   , RULL(0x800000760801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_CAL_EN_P1_1                   , RULL(0x800004760701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_CAL_EN_P1_1                   , RULL(0x800004760801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_CAL_EN_P1_2                   , RULL(0x800008760701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_CAL_EN_P1_2                   , RULL(0x800008760801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_CAL_EN_P1_3                   , RULL(0x80000C760701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_CAL_EN_P1_3                   , RULL(0x80000C760801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_CAL_EN_P1_4                   , RULL(0x800010760701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_CAL_EN_P1_4                   , RULL(0x800010760801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_CAL_EN_P2_0                   , RULL(0x800000760701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_CAL_EN_P2_0                   , RULL(0x800000760801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_CAL_EN_P2_1                   , RULL(0x800004760701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_CAL_EN_P2_1                   , RULL(0x800004760801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_CAL_EN_P2_2                   , RULL(0x800008760701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_CAL_EN_P2_2                   , RULL(0x800008760801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_CAL_EN_P2_3                   , RULL(0x80000C760701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_CAL_EN_P2_3                   , RULL(0x80000C760801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_CAL_EN_P2_4                   , RULL(0x800010760701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_CAL_EN_P2_4                   , RULL(0x800010760801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_CAL_EN_P3_0                   , RULL(0x8000007607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_CAL_EN_P3_0                   , RULL(0x8000007608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_CAL_EN_P3_1                   , RULL(0x8000047607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_CAL_EN_P3_1                   , RULL(0x8000047608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_CAL_EN_P3_2                   , RULL(0x8000087607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_CAL_EN_P3_2                   , RULL(0x8000087608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_CAL_EN_P3_3                   , RULL(0x80000C7607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_CAL_EN_P3_3                   , RULL(0x80000C7608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_CAL_EN_P3_4                   , RULL(0x8000107607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_CAL_EN_P3_4                   , RULL(0x8000107608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0                  , RULL(0x8000007A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0                , RULL(0x8000007A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0                , RULL(0x8000007A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1                  , RULL(0x8000047A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1                , RULL(0x8000047A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1                , RULL(0x8000047A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2                  , RULL(0x8000087A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2                , RULL(0x8000087A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2                , RULL(0x8000087A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3                  , RULL(0x80000C7A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3                , RULL(0x80000C7A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3                , RULL(0x80000C7A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4                  , RULL(0x8000107A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4                , RULL(0x8000107A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4                , RULL(0x8000107A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_0                , RULL(0x8000007A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_0                , RULL(0x8000007A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_1                , RULL(0x8000047A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_1                , RULL(0x8000047A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_2                , RULL(0x8000087A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_2                , RULL(0x8000087A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_3                , RULL(0x80000C7A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_3                , RULL(0x80000C7A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_4                , RULL(0x8000107A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_CAL_ERROR_P1_4                , RULL(0x8000107A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_0                , RULL(0x8000007A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_0                , RULL(0x8000007A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_1                , RULL(0x8000047A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_1                , RULL(0x8000047A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_2                , RULL(0x8000087A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_2                , RULL(0x8000087A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_3                , RULL(0x80000C7A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_3                , RULL(0x80000C7A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_4                , RULL(0x8000107A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_CAL_ERROR_P2_4                , RULL(0x8000107A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_0                , RULL(0x8000007A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_0                , RULL(0x8000007A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_1                , RULL(0x8000047A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_1                , RULL(0x8000047A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_2                , RULL(0x8000087A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_2                , RULL(0x8000087A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_3                , RULL(0x80000C7A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_3                , RULL(0x80000C7A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_4                , RULL(0x8000107A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_CAL_ERROR_P3_4                , RULL(0x8000107A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_0               , RULL(0x800000F60701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_0             , RULL(0x800000F60701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_0             , RULL(0x800000F60801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_1               , RULL(0x800004F60701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_1             , RULL(0x800004F60701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_1             , RULL(0x800004F60801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_2               , RULL(0x800008F60701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_2             , RULL(0x800008F60701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_2             , RULL(0x800008F60801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_3               , RULL(0x80000CF60701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_3             , RULL(0x80000CF60701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_3             , RULL(0x80000CF60801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_4               , RULL(0x800010F60701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_4             , RULL(0x800010F60701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_4             , RULL(0x800010F60801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_0             , RULL(0x800000F60701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_0             , RULL(0x800000F60801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_1             , RULL(0x800004F60701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_1             , RULL(0x800004F60801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_2             , RULL(0x800008F60701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_2             , RULL(0x800008F60801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_3             , RULL(0x80000CF60701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_3             , RULL(0x80000CF60801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_4             , RULL(0x800010F60701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P1_4             , RULL(0x800010F60801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_0             , RULL(0x800000F60701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_0             , RULL(0x800000F60801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_1             , RULL(0x800004F60701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_1             , RULL(0x800004F60801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_2             , RULL(0x800008F60701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_2             , RULL(0x800008F60801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_3             , RULL(0x80000CF60701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_3             , RULL(0x80000CF60801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_4             , RULL(0x800010F60701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P2_4             , RULL(0x800010F60801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_0             , RULL(0x800000F607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_0             , RULL(0x800000F608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_1             , RULL(0x800004F607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_1             , RULL(0x800004F608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_2             , RULL(0x800008F607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_2             , RULL(0x800008F608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_3             , RULL(0x80000CF607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_3             , RULL(0x80000CF608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_4             , RULL(0x800010F607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P3_4             , RULL(0x800010F608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0              , RULL(0x800000040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0            , RULL(0x800000040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0            , RULL(0x800000040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1              , RULL(0x800004040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1            , RULL(0x800004040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1            , RULL(0x800004040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2              , RULL(0x800008040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2            , RULL(0x800008040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2            , RULL(0x800008040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3              , RULL(0x80000C040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3            , RULL(0x80000C040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3            , RULL(0x80000C040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4              , RULL(0x800010040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4            , RULL(0x800010040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4            , RULL(0x800010040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_0            , RULL(0x800000040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_0            , RULL(0x800000040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_1            , RULL(0x800004040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_1            , RULL(0x800004040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_2            , RULL(0x800008040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_2            , RULL(0x800008040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_3            , RULL(0x80000C040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_3            , RULL(0x80000C040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_4            , RULL(0x800010040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P1_4            , RULL(0x800010040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_0            , RULL(0x800000040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_0            , RULL(0x800000040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_1            , RULL(0x800004040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_1            , RULL(0x800004040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_2            , RULL(0x800008040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_2            , RULL(0x800008040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_3            , RULL(0x80000C040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_3            , RULL(0x80000C040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_4            , RULL(0x800010040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P2_4            , RULL(0x800010040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_0            , RULL(0x8000000407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_0            , RULL(0x8000000408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_1            , RULL(0x8000040407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_1            , RULL(0x8000040408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_2            , RULL(0x8000080407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_2            , RULL(0x8000080408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_3            , RULL(0x80000C0407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_3            , RULL(0x80000C0408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_4            , RULL(0x8000100407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P3_4            , RULL(0x8000100408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0              , RULL(0x800001040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0            , RULL(0x800001040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0            , RULL(0x800001040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1              , RULL(0x800005040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1            , RULL(0x800005040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1            , RULL(0x800005040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2              , RULL(0x800009040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2            , RULL(0x800009040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2            , RULL(0x800009040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3              , RULL(0x80000D040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3            , RULL(0x80000D040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3            , RULL(0x80000D040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4              , RULL(0x800011040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4            , RULL(0x800011040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4            , RULL(0x800011040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_0            , RULL(0x800001040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_0            , RULL(0x800001040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_1            , RULL(0x800005040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_1            , RULL(0x800005040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_2            , RULL(0x800009040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_2            , RULL(0x800009040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_3            , RULL(0x80000D040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_3            , RULL(0x80000D040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_4            , RULL(0x800011040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P1_4            , RULL(0x800011040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_0            , RULL(0x800001040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_0            , RULL(0x800001040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_1            , RULL(0x800005040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_1            , RULL(0x800005040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_2            , RULL(0x800009040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_2            , RULL(0x800009040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_3            , RULL(0x80000D040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_3            , RULL(0x80000D040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_4            , RULL(0x800011040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P2_4            , RULL(0x800011040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_0            , RULL(0x8000010407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_0            , RULL(0x8000010408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_1            , RULL(0x8000050407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_1            , RULL(0x8000050408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_2            , RULL(0x8000090407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_2            , RULL(0x8000090408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_3            , RULL(0x80000D0407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_3            , RULL(0x80000D0408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_4            , RULL(0x8000110407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P3_4            , RULL(0x8000110408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0              , RULL(0x800002040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0            , RULL(0x800002040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0            , RULL(0x800002040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1              , RULL(0x800006040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1            , RULL(0x800006040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1            , RULL(0x800006040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2              , RULL(0x80000A040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2            , RULL(0x80000A040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2            , RULL(0x80000A040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3              , RULL(0x80000E040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3            , RULL(0x80000E040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3            , RULL(0x80000E040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4              , RULL(0x800012040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4            , RULL(0x800012040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4            , RULL(0x800012040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_0            , RULL(0x800002040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_0            , RULL(0x800002040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_1            , RULL(0x800006040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_1            , RULL(0x800006040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_2            , RULL(0x80000A040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_2            , RULL(0x80000A040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_3            , RULL(0x80000E040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_3            , RULL(0x80000E040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_4            , RULL(0x800012040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P1_4            , RULL(0x800012040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_0            , RULL(0x800002040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_0            , RULL(0x800002040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_1            , RULL(0x800006040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_1            , RULL(0x800006040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_2            , RULL(0x80000A040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_2            , RULL(0x80000A040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_3            , RULL(0x80000E040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_3            , RULL(0x80000E040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_4            , RULL(0x800012040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P2_4            , RULL(0x800012040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_0            , RULL(0x8000020407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_0            , RULL(0x8000020408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_1            , RULL(0x8000060407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_1            , RULL(0x8000060408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_2            , RULL(0x80000A0407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_2            , RULL(0x80000A0408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_3            , RULL(0x80000E0407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_3            , RULL(0x80000E0408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_4            , RULL(0x8000120407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P3_4            , RULL(0x8000120408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0              , RULL(0x800003040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0            , RULL(0x800003040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0            , RULL(0x800003040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1              , RULL(0x800007040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1            , RULL(0x800007040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1            , RULL(0x800007040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2              , RULL(0x80000B040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2            , RULL(0x80000B040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2            , RULL(0x80000B040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3              , RULL(0x80000F040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3            , RULL(0x80000F040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3            , RULL(0x80000F040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4              , RULL(0x800013040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4            , RULL(0x800013040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4            , RULL(0x800013040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_0            , RULL(0x800003040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_0            , RULL(0x800003040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_1            , RULL(0x800007040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_1            , RULL(0x800007040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_2            , RULL(0x80000B040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_2            , RULL(0x80000B040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_3            , RULL(0x80000F040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_3            , RULL(0x80000F040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_4            , RULL(0x800013040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P1_4            , RULL(0x800013040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_0            , RULL(0x800003040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_0            , RULL(0x800003040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_1            , RULL(0x800007040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_1            , RULL(0x800007040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_2            , RULL(0x80000B040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_2            , RULL(0x80000B040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_3            , RULL(0x80000F040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_3            , RULL(0x80000F040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_4            , RULL(0x800013040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P2_4            , RULL(0x800013040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_0            , RULL(0x8000030407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_0            , RULL(0x8000030408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_1            , RULL(0x8000070407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_1            , RULL(0x8000070408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_2            , RULL(0x80000B0407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_2            , RULL(0x80000B0408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_3            , RULL(0x80000F0407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_3            , RULL(0x80000F0408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_4            , RULL(0x8000130407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P3_4            , RULL(0x8000130408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0             , RULL(0x800000500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0           , RULL(0x800000500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0           , RULL(0x800000500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1             , RULL(0x800004500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1           , RULL(0x800004500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1           , RULL(0x800004500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2             , RULL(0x800008500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2           , RULL(0x800008500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2           , RULL(0x800008500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3             , RULL(0x80000C500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3           , RULL(0x80000C500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3           , RULL(0x80000C500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4             , RULL(0x800010500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4           , RULL(0x800010500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4           , RULL(0x800010500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_0           , RULL(0x800000500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_0           , RULL(0x800000500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_1           , RULL(0x800004500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_1           , RULL(0x800004500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_2           , RULL(0x800008500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_2           , RULL(0x800008500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_3           , RULL(0x80000C500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_3           , RULL(0x80000C500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_4           , RULL(0x800010500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P1_4           , RULL(0x800010500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_0           , RULL(0x800000500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_0           , RULL(0x800000500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_1           , RULL(0x800004500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_1           , RULL(0x800004500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_2           , RULL(0x800008500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_2           , RULL(0x800008500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_3           , RULL(0x80000C500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_3           , RULL(0x80000C500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_4           , RULL(0x800010500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P2_4           , RULL(0x800010500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_0           , RULL(0x8000005007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_0           , RULL(0x8000005008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_1           , RULL(0x8000045007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_1           , RULL(0x8000045008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_2           , RULL(0x8000085007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_2           , RULL(0x8000085008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_3           , RULL(0x80000C5007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_3           , RULL(0x80000C5008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_4           , RULL(0x8000105007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P3_4           , RULL(0x8000105008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0             , RULL(0x800001500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0           , RULL(0x800001500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0           , RULL(0x800001500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1             , RULL(0x800005500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1           , RULL(0x800005500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1           , RULL(0x800005500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2             , RULL(0x800009500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2           , RULL(0x800009500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2           , RULL(0x800009500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3             , RULL(0x80000D500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3           , RULL(0x80000D500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3           , RULL(0x80000D500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4             , RULL(0x800011500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4           , RULL(0x800011500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4           , RULL(0x800011500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_0           , RULL(0x800001500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_0           , RULL(0x800001500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_1           , RULL(0x800005500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_1           , RULL(0x800005500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_2           , RULL(0x800009500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_2           , RULL(0x800009500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_3           , RULL(0x80000D500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_3           , RULL(0x80000D500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_4           , RULL(0x800011500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P1_4           , RULL(0x800011500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_0           , RULL(0x800001500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_0           , RULL(0x800001500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_1           , RULL(0x800005500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_1           , RULL(0x800005500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_2           , RULL(0x800009500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_2           , RULL(0x800009500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_3           , RULL(0x80000D500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_3           , RULL(0x80000D500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_4           , RULL(0x800011500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P2_4           , RULL(0x800011500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_0           , RULL(0x8000015007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_0           , RULL(0x8000015008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_1           , RULL(0x8000055007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_1           , RULL(0x8000055008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_2           , RULL(0x8000095007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_2           , RULL(0x8000095008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_3           , RULL(0x80000D5007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_3           , RULL(0x80000D5008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_4           , RULL(0x8000115007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P3_4           , RULL(0x8000115008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0             , RULL(0x800002500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0           , RULL(0x800002500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0           , RULL(0x800002500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1             , RULL(0x800006500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1           , RULL(0x800006500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1           , RULL(0x800006500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2             , RULL(0x80000A500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2           , RULL(0x80000A500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2           , RULL(0x80000A500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3             , RULL(0x80000E500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3           , RULL(0x80000E500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3           , RULL(0x80000E500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4             , RULL(0x800012500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4           , RULL(0x800012500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4           , RULL(0x800012500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_0           , RULL(0x800002500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_0           , RULL(0x800002500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_1           , RULL(0x800006500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_1           , RULL(0x800006500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_2           , RULL(0x80000A500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_2           , RULL(0x80000A500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_3           , RULL(0x80000E500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_3           , RULL(0x80000E500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_4           , RULL(0x800012500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P1_4           , RULL(0x800012500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_0           , RULL(0x800002500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_0           , RULL(0x800002500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_1           , RULL(0x800006500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_1           , RULL(0x800006500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_2           , RULL(0x80000A500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_2           , RULL(0x80000A500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_3           , RULL(0x80000E500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_3           , RULL(0x80000E500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_4           , RULL(0x800012500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P2_4           , RULL(0x800012500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_0           , RULL(0x8000025007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_0           , RULL(0x8000025008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_1           , RULL(0x8000065007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_1           , RULL(0x8000065008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_2           , RULL(0x80000A5007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_2           , RULL(0x80000A5008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_3           , RULL(0x80000E5007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_3           , RULL(0x80000E5008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_4           , RULL(0x8000125007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P3_4           , RULL(0x8000125008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0             , RULL(0x800003500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0           , RULL(0x800003500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0           , RULL(0x800003500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1             , RULL(0x800007500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1           , RULL(0x800007500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1           , RULL(0x800007500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2             , RULL(0x80000B500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2           , RULL(0x80000B500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2           , RULL(0x80000B500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3             , RULL(0x80000F500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3           , RULL(0x80000F500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3           , RULL(0x80000F500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4             , RULL(0x800013500701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4           , RULL(0x800013500701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4           , RULL(0x800013500801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_0           , RULL(0x800003500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_0           , RULL(0x800003500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_1           , RULL(0x800007500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_1           , RULL(0x800007500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_2           , RULL(0x80000B500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_2           , RULL(0x80000B500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_3           , RULL(0x80000F500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_3           , RULL(0x80000F500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_4           , RULL(0x800013500701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P1_4           , RULL(0x800013500801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_0           , RULL(0x800003500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_0           , RULL(0x800003500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_1           , RULL(0x800007500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_1           , RULL(0x800007500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_2           , RULL(0x80000B500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_2           , RULL(0x80000B500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_3           , RULL(0x80000F500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_3           , RULL(0x80000F500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_4           , RULL(0x800013500701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P2_4           , RULL(0x800013500801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_0           , RULL(0x8000035007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_0           , RULL(0x8000035008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_1           , RULL(0x8000075007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_1           , RULL(0x8000075008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_2           , RULL(0x80000B5007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_2           , RULL(0x80000B5008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_3           , RULL(0x80000F5007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_3           , RULL(0x80000F5008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_4           , RULL(0x8000135007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P3_4           , RULL(0x8000135008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0             , RULL(0x800000510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0           , RULL(0x800000510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0           , RULL(0x800000510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1             , RULL(0x800004510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1           , RULL(0x800004510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1           , RULL(0x800004510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2             , RULL(0x800008510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2           , RULL(0x800008510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2           , RULL(0x800008510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3             , RULL(0x80000C510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3           , RULL(0x80000C510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3           , RULL(0x80000C510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4             , RULL(0x800010510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4           , RULL(0x800010510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4           , RULL(0x800010510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_0           , RULL(0x800000510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_0           , RULL(0x800000510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_1           , RULL(0x800004510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_1           , RULL(0x800004510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_2           , RULL(0x800008510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_2           , RULL(0x800008510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_3           , RULL(0x80000C510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_3           , RULL(0x80000C510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_4           , RULL(0x800010510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P1_4           , RULL(0x800010510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_0           , RULL(0x800000510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_0           , RULL(0x800000510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_1           , RULL(0x800004510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_1           , RULL(0x800004510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_2           , RULL(0x800008510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_2           , RULL(0x800008510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_3           , RULL(0x80000C510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_3           , RULL(0x80000C510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_4           , RULL(0x800010510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P2_4           , RULL(0x800010510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_0           , RULL(0x8000005107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_0           , RULL(0x8000005108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_1           , RULL(0x8000045107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_1           , RULL(0x8000045108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_2           , RULL(0x8000085107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_2           , RULL(0x8000085108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_3           , RULL(0x80000C5107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_3           , RULL(0x80000C5108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_4           , RULL(0x8000105107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P3_4           , RULL(0x8000105108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0             , RULL(0x800001510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0           , RULL(0x800001510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0           , RULL(0x800001510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1             , RULL(0x800005510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1           , RULL(0x800005510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1           , RULL(0x800005510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2             , RULL(0x800009510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2           , RULL(0x800009510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2           , RULL(0x800009510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3             , RULL(0x80000D510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3           , RULL(0x80000D510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3           , RULL(0x80000D510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4             , RULL(0x800011510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4           , RULL(0x800011510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4           , RULL(0x800011510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_0           , RULL(0x800001510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_0           , RULL(0x800001510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_1           , RULL(0x800005510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_1           , RULL(0x800005510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_2           , RULL(0x800009510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_2           , RULL(0x800009510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_3           , RULL(0x80000D510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_3           , RULL(0x80000D510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_4           , RULL(0x800011510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P1_4           , RULL(0x800011510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_0           , RULL(0x800001510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_0           , RULL(0x800001510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_1           , RULL(0x800005510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_1           , RULL(0x800005510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_2           , RULL(0x800009510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_2           , RULL(0x800009510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_3           , RULL(0x80000D510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_3           , RULL(0x80000D510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_4           , RULL(0x800011510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P2_4           , RULL(0x800011510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_0           , RULL(0x8000015107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_0           , RULL(0x8000015108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_1           , RULL(0x8000055107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_1           , RULL(0x8000055108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_2           , RULL(0x8000095107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_2           , RULL(0x8000095108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_3           , RULL(0x80000D5107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_3           , RULL(0x80000D5108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_4           , RULL(0x8000115107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P3_4           , RULL(0x8000115108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0             , RULL(0x800002510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0           , RULL(0x800002510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0           , RULL(0x800002510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1             , RULL(0x800006510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1           , RULL(0x800006510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1           , RULL(0x800006510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2             , RULL(0x80000A510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2           , RULL(0x80000A510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2           , RULL(0x80000A510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3             , RULL(0x80000E510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3           , RULL(0x80000E510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3           , RULL(0x80000E510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4             , RULL(0x800012510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4           , RULL(0x800012510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4           , RULL(0x800012510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_0           , RULL(0x800002510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_0           , RULL(0x800002510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_1           , RULL(0x800006510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_1           , RULL(0x800006510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_2           , RULL(0x80000A510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_2           , RULL(0x80000A510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_3           , RULL(0x80000E510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_3           , RULL(0x80000E510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_4           , RULL(0x800012510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P1_4           , RULL(0x800012510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_0           , RULL(0x800002510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_0           , RULL(0x800002510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_1           , RULL(0x800006510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_1           , RULL(0x800006510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_2           , RULL(0x80000A510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_2           , RULL(0x80000A510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_3           , RULL(0x80000E510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_3           , RULL(0x80000E510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_4           , RULL(0x800012510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P2_4           , RULL(0x800012510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_0           , RULL(0x8000025107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_0           , RULL(0x8000025108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_1           , RULL(0x8000065107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_1           , RULL(0x8000065108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_2           , RULL(0x80000A5107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_2           , RULL(0x80000A5108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_3           , RULL(0x80000E5107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_3           , RULL(0x80000E5108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_4           , RULL(0x8000125107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P3_4           , RULL(0x8000125108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0             , RULL(0x800003510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0           , RULL(0x800003510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0           , RULL(0x800003510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1             , RULL(0x800007510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1           , RULL(0x800007510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1           , RULL(0x800007510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2             , RULL(0x80000B510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2           , RULL(0x80000B510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2           , RULL(0x80000B510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3             , RULL(0x80000F510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3           , RULL(0x80000F510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3           , RULL(0x80000F510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4             , RULL(0x800013510701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4           , RULL(0x800013510701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4           , RULL(0x800013510801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_0           , RULL(0x800003510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_0           , RULL(0x800003510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_1           , RULL(0x800007510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_1           , RULL(0x800007510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_2           , RULL(0x80000B510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_2           , RULL(0x80000B510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_3           , RULL(0x80000F510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_3           , RULL(0x80000F510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_4           , RULL(0x800013510701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P1_4           , RULL(0x800013510801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_0           , RULL(0x800003510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_0           , RULL(0x800003510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_1           , RULL(0x800007510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_1           , RULL(0x800007510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_2           , RULL(0x80000B510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_2           , RULL(0x80000B510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_3           , RULL(0x80000F510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_3           , RULL(0x80000F510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_4           , RULL(0x800013510701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P2_4           , RULL(0x800013510801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_0           , RULL(0x8000035107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_0           , RULL(0x8000035108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_1           , RULL(0x8000075107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_1           , RULL(0x8000075108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_2           , RULL(0x80000B5107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_2           , RULL(0x80000B5108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_3           , RULL(0x80000F5107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_3           , RULL(0x80000F5108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_4           , RULL(0x8000135107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P3_4           , RULL(0x8000135108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0             , RULL(0x800000520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0           , RULL(0x800000520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0           , RULL(0x800000520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1             , RULL(0x800004520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1           , RULL(0x800004520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1           , RULL(0x800004520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2             , RULL(0x800008520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2           , RULL(0x800008520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2           , RULL(0x800008520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3             , RULL(0x80000C520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3           , RULL(0x80000C520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3           , RULL(0x80000C520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4             , RULL(0x800010520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4           , RULL(0x800010520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4           , RULL(0x800010520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_0           , RULL(0x800000520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_0           , RULL(0x800000520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_1           , RULL(0x800004520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_1           , RULL(0x800004520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_2           , RULL(0x800008520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_2           , RULL(0x800008520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_3           , RULL(0x80000C520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_3           , RULL(0x80000C520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_4           , RULL(0x800010520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P1_4           , RULL(0x800010520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_0           , RULL(0x800000520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_0           , RULL(0x800000520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_1           , RULL(0x800004520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_1           , RULL(0x800004520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_2           , RULL(0x800008520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_2           , RULL(0x800008520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_3           , RULL(0x80000C520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_3           , RULL(0x80000C520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_4           , RULL(0x800010520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P2_4           , RULL(0x800010520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_0           , RULL(0x8000005207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_0           , RULL(0x8000005208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_1           , RULL(0x8000045207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_1           , RULL(0x8000045208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_2           , RULL(0x8000085207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_2           , RULL(0x8000085208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_3           , RULL(0x80000C5207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_3           , RULL(0x80000C5208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_4           , RULL(0x8000105207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P3_4           , RULL(0x8000105208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0             , RULL(0x800001520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0           , RULL(0x800001520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0           , RULL(0x800001520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1             , RULL(0x800005520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1           , RULL(0x800005520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1           , RULL(0x800005520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2             , RULL(0x800009520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2           , RULL(0x800009520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2           , RULL(0x800009520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3             , RULL(0x80000D520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3           , RULL(0x80000D520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3           , RULL(0x80000D520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4             , RULL(0x800011520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4           , RULL(0x800011520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4           , RULL(0x800011520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_0           , RULL(0x800001520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_0           , RULL(0x800001520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_1           , RULL(0x800005520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_1           , RULL(0x800005520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_2           , RULL(0x800009520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_2           , RULL(0x800009520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_3           , RULL(0x80000D520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_3           , RULL(0x80000D520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_4           , RULL(0x800011520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P1_4           , RULL(0x800011520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_0           , RULL(0x800001520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_0           , RULL(0x800001520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_1           , RULL(0x800005520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_1           , RULL(0x800005520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_2           , RULL(0x800009520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_2           , RULL(0x800009520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_3           , RULL(0x80000D520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_3           , RULL(0x80000D520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_4           , RULL(0x800011520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P2_4           , RULL(0x800011520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_0           , RULL(0x8000015207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_0           , RULL(0x8000015208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_1           , RULL(0x8000055207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_1           , RULL(0x8000055208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_2           , RULL(0x8000095207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_2           , RULL(0x8000095208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_3           , RULL(0x80000D5207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_3           , RULL(0x80000D5208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_4           , RULL(0x8000115207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P3_4           , RULL(0x8000115208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0             , RULL(0x800002520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0           , RULL(0x800002520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0           , RULL(0x800002520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1             , RULL(0x800006520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1           , RULL(0x800006520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1           , RULL(0x800006520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2             , RULL(0x80000A520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2           , RULL(0x80000A520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2           , RULL(0x80000A520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3             , RULL(0x80000E520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3           , RULL(0x80000E520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3           , RULL(0x80000E520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4             , RULL(0x800012520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4           , RULL(0x800012520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4           , RULL(0x800012520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_0           , RULL(0x800002520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_0           , RULL(0x800002520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_1           , RULL(0x800006520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_1           , RULL(0x800006520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_2           , RULL(0x80000A520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_2           , RULL(0x80000A520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_3           , RULL(0x80000E520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_3           , RULL(0x80000E520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_4           , RULL(0x800012520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P1_4           , RULL(0x800012520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_0           , RULL(0x800002520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_0           , RULL(0x800002520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_1           , RULL(0x800006520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_1           , RULL(0x800006520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_2           , RULL(0x80000A520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_2           , RULL(0x80000A520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_3           , RULL(0x80000E520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_3           , RULL(0x80000E520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_4           , RULL(0x800012520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P2_4           , RULL(0x800012520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_0           , RULL(0x8000025207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_0           , RULL(0x8000025208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_1           , RULL(0x8000065207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_1           , RULL(0x8000065208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_2           , RULL(0x80000A5207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_2           , RULL(0x80000A5208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_3           , RULL(0x80000E5207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_3           , RULL(0x80000E5208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_4           , RULL(0x8000125207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P3_4           , RULL(0x8000125208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0             , RULL(0x800003520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0           , RULL(0x800003520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0           , RULL(0x800003520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1             , RULL(0x800007520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1           , RULL(0x800007520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1           , RULL(0x800007520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2             , RULL(0x80000B520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2           , RULL(0x80000B520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2           , RULL(0x80000B520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3             , RULL(0x80000F520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3           , RULL(0x80000F520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3           , RULL(0x80000F520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4             , RULL(0x800013520701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4           , RULL(0x800013520701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4           , RULL(0x800013520801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_0           , RULL(0x800003520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_0           , RULL(0x800003520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_1           , RULL(0x800007520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_1           , RULL(0x800007520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_2           , RULL(0x80000B520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_2           , RULL(0x80000B520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_3           , RULL(0x80000F520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_3           , RULL(0x80000F520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_4           , RULL(0x800013520701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P1_4           , RULL(0x800013520801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_0           , RULL(0x800003520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_0           , RULL(0x800003520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_1           , RULL(0x800007520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_1           , RULL(0x800007520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_2           , RULL(0x80000B520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_2           , RULL(0x80000B520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_3           , RULL(0x80000F520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_3           , RULL(0x80000F520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_4           , RULL(0x800013520701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P2_4           , RULL(0x800013520801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_0           , RULL(0x8000035207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_0           , RULL(0x8000035208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_1           , RULL(0x8000075207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_1           , RULL(0x8000075208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_2           , RULL(0x80000B5207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_2           , RULL(0x80000B5208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_3           , RULL(0x80000F5207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_3           , RULL(0x80000F5208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_4           , RULL(0x8000135207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P3_4           , RULL(0x8000135208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0             , RULL(0x800000530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0           , RULL(0x800000530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0           , RULL(0x800000530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1             , RULL(0x800004530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1           , RULL(0x800004530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1           , RULL(0x800004530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2             , RULL(0x800008530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2           , RULL(0x800008530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2           , RULL(0x800008530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3             , RULL(0x80000C530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3           , RULL(0x80000C530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3           , RULL(0x80000C530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4             , RULL(0x800010530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4           , RULL(0x800010530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4           , RULL(0x800010530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_0           , RULL(0x800000530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_0           , RULL(0x800000530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_1           , RULL(0x800004530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_1           , RULL(0x800004530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_2           , RULL(0x800008530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_2           , RULL(0x800008530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_3           , RULL(0x80000C530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_3           , RULL(0x80000C530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_4           , RULL(0x800010530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P1_4           , RULL(0x800010530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_0           , RULL(0x800000530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_0           , RULL(0x800000530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_1           , RULL(0x800004530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_1           , RULL(0x800004530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_2           , RULL(0x800008530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_2           , RULL(0x800008530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_3           , RULL(0x80000C530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_3           , RULL(0x80000C530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_4           , RULL(0x800010530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P2_4           , RULL(0x800010530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_0           , RULL(0x8000005307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_0           , RULL(0x8000005308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_1           , RULL(0x8000045307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_1           , RULL(0x8000045308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_2           , RULL(0x8000085307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_2           , RULL(0x8000085308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_3           , RULL(0x80000C5307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_3           , RULL(0x80000C5308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_4           , RULL(0x8000105307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P3_4           , RULL(0x8000105308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0             , RULL(0x800001530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0           , RULL(0x800001530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0           , RULL(0x800001530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1             , RULL(0x800005530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1           , RULL(0x800005530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1           , RULL(0x800005530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2             , RULL(0x800009530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2           , RULL(0x800009530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2           , RULL(0x800009530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3             , RULL(0x80000D530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3           , RULL(0x80000D530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3           , RULL(0x80000D530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4             , RULL(0x800011530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4           , RULL(0x800011530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4           , RULL(0x800011530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_0           , RULL(0x800001530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_0           , RULL(0x800001530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_1           , RULL(0x800005530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_1           , RULL(0x800005530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_2           , RULL(0x800009530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_2           , RULL(0x800009530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_3           , RULL(0x80000D530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_3           , RULL(0x80000D530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_4           , RULL(0x800011530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P1_4           , RULL(0x800011530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_0           , RULL(0x800001530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_0           , RULL(0x800001530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_1           , RULL(0x800005530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_1           , RULL(0x800005530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_2           , RULL(0x800009530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_2           , RULL(0x800009530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_3           , RULL(0x80000D530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_3           , RULL(0x80000D530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_4           , RULL(0x800011530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P2_4           , RULL(0x800011530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_0           , RULL(0x8000015307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_0           , RULL(0x8000015308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_1           , RULL(0x8000055307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_1           , RULL(0x8000055308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_2           , RULL(0x8000095307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_2           , RULL(0x8000095308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_3           , RULL(0x80000D5307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_3           , RULL(0x80000D5308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_4           , RULL(0x8000115307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P3_4           , RULL(0x8000115308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0             , RULL(0x800002530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0           , RULL(0x800002530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0           , RULL(0x800002530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1             , RULL(0x800006530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1           , RULL(0x800006530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1           , RULL(0x800006530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2             , RULL(0x80000A530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2           , RULL(0x80000A530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2           , RULL(0x80000A530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3             , RULL(0x80000E530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3           , RULL(0x80000E530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3           , RULL(0x80000E530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4             , RULL(0x800012530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4           , RULL(0x800012530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4           , RULL(0x800012530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_0           , RULL(0x800002530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_0           , RULL(0x800002530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_1           , RULL(0x800006530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_1           , RULL(0x800006530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_2           , RULL(0x80000A530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_2           , RULL(0x80000A530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_3           , RULL(0x80000E530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_3           , RULL(0x80000E530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_4           , RULL(0x800012530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P1_4           , RULL(0x800012530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_0           , RULL(0x800002530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_0           , RULL(0x800002530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_1           , RULL(0x800006530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_1           , RULL(0x800006530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_2           , RULL(0x80000A530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_2           , RULL(0x80000A530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_3           , RULL(0x80000E530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_3           , RULL(0x80000E530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_4           , RULL(0x800012530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P2_4           , RULL(0x800012530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_0           , RULL(0x8000025307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_0           , RULL(0x8000025308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_1           , RULL(0x8000065307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_1           , RULL(0x8000065308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_2           , RULL(0x80000A5307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_2           , RULL(0x80000A5308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_3           , RULL(0x80000E5307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_3           , RULL(0x80000E5308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_4           , RULL(0x8000125307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P3_4           , RULL(0x8000125308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0             , RULL(0x800003530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0           , RULL(0x800003530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0           , RULL(0x800003530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1             , RULL(0x800007530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1           , RULL(0x800007530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1           , RULL(0x800007530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2             , RULL(0x80000B530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2           , RULL(0x80000B530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2           , RULL(0x80000B530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3             , RULL(0x80000F530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3           , RULL(0x80000F530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3           , RULL(0x80000F530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4             , RULL(0x800013530701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4           , RULL(0x800013530701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4           , RULL(0x800013530801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_0           , RULL(0x800003530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_0           , RULL(0x800003530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_1           , RULL(0x800007530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_1           , RULL(0x800007530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_2           , RULL(0x80000B530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_2           , RULL(0x80000B530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_3           , RULL(0x80000F530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_3           , RULL(0x80000F530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_4           , RULL(0x800013530701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P1_4           , RULL(0x800013530801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_0           , RULL(0x800003530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_0           , RULL(0x800003530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_1           , RULL(0x800007530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_1           , RULL(0x800007530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_2           , RULL(0x80000B530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_2           , RULL(0x80000B530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_3           , RULL(0x80000F530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_3           , RULL(0x80000F530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_4           , RULL(0x800013530701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P2_4           , RULL(0x800013530801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_0           , RULL(0x8000035307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_0           , RULL(0x8000035308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_1           , RULL(0x8000075307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_1           , RULL(0x8000075308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_2           , RULL(0x80000B5307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_2           , RULL(0x80000B5308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_3           , RULL(0x80000F5307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_3           , RULL(0x80000F5308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_4           , RULL(0x8000135307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P3_4           , RULL(0x8000135308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0             , RULL(0x800000540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0           , RULL(0x800000540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0           , RULL(0x800000540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1             , RULL(0x800004540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1           , RULL(0x800004540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1           , RULL(0x800004540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2             , RULL(0x800008540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2           , RULL(0x800008540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2           , RULL(0x800008540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3             , RULL(0x80000C540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3           , RULL(0x80000C540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3           , RULL(0x80000C540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4             , RULL(0x800010540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4           , RULL(0x800010540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4           , RULL(0x800010540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_0           , RULL(0x800000540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_0           , RULL(0x800000540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_1           , RULL(0x800004540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_1           , RULL(0x800004540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_2           , RULL(0x800008540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_2           , RULL(0x800008540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_3           , RULL(0x80000C540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_3           , RULL(0x80000C540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_4           , RULL(0x800010540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P1_4           , RULL(0x800010540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_0           , RULL(0x800000540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_0           , RULL(0x800000540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_1           , RULL(0x800004540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_1           , RULL(0x800004540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_2           , RULL(0x800008540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_2           , RULL(0x800008540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_3           , RULL(0x80000C540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_3           , RULL(0x80000C540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_4           , RULL(0x800010540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P2_4           , RULL(0x800010540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_0           , RULL(0x8000005407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_0           , RULL(0x8000005408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_1           , RULL(0x8000045407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_1           , RULL(0x8000045408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_2           , RULL(0x8000085407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_2           , RULL(0x8000085408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_3           , RULL(0x80000C5407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_3           , RULL(0x80000C5408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_4           , RULL(0x8000105407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P3_4           , RULL(0x8000105408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0             , RULL(0x800001540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0           , RULL(0x800001540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0           , RULL(0x800001540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1             , RULL(0x800005540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1           , RULL(0x800005540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1           , RULL(0x800005540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2             , RULL(0x800009540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2           , RULL(0x800009540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2           , RULL(0x800009540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3             , RULL(0x80000D540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3           , RULL(0x80000D540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3           , RULL(0x80000D540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4             , RULL(0x800011540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4           , RULL(0x800011540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4           , RULL(0x800011540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_0           , RULL(0x800001540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_0           , RULL(0x800001540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_1           , RULL(0x800005540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_1           , RULL(0x800005540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_2           , RULL(0x800009540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_2           , RULL(0x800009540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_3           , RULL(0x80000D540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_3           , RULL(0x80000D540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_4           , RULL(0x800011540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P1_4           , RULL(0x800011540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_0           , RULL(0x800001540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_0           , RULL(0x800001540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_1           , RULL(0x800005540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_1           , RULL(0x800005540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_2           , RULL(0x800009540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_2           , RULL(0x800009540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_3           , RULL(0x80000D540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_3           , RULL(0x80000D540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_4           , RULL(0x800011540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P2_4           , RULL(0x800011540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_0           , RULL(0x8000015407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_0           , RULL(0x8000015408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_1           , RULL(0x8000055407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_1           , RULL(0x8000055408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_2           , RULL(0x8000095407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_2           , RULL(0x8000095408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_3           , RULL(0x80000D5407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_3           , RULL(0x80000D5408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_4           , RULL(0x8000115407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P3_4           , RULL(0x8000115408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0             , RULL(0x800002540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0           , RULL(0x800002540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0           , RULL(0x800002540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1             , RULL(0x800006540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1           , RULL(0x800006540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1           , RULL(0x800006540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2             , RULL(0x80000A540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2           , RULL(0x80000A540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2           , RULL(0x80000A540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3             , RULL(0x80000E540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3           , RULL(0x80000E540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3           , RULL(0x80000E540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4             , RULL(0x800012540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4           , RULL(0x800012540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4           , RULL(0x800012540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_0           , RULL(0x800002540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_0           , RULL(0x800002540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_1           , RULL(0x800006540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_1           , RULL(0x800006540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_2           , RULL(0x80000A540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_2           , RULL(0x80000A540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_3           , RULL(0x80000E540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_3           , RULL(0x80000E540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_4           , RULL(0x800012540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P1_4           , RULL(0x800012540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_0           , RULL(0x800002540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_0           , RULL(0x800002540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_1           , RULL(0x800006540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_1           , RULL(0x800006540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_2           , RULL(0x80000A540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_2           , RULL(0x80000A540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_3           , RULL(0x80000E540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_3           , RULL(0x80000E540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_4           , RULL(0x800012540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P2_4           , RULL(0x800012540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_0           , RULL(0x8000025407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_0           , RULL(0x8000025408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_1           , RULL(0x8000065407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_1           , RULL(0x8000065408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_2           , RULL(0x80000A5407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_2           , RULL(0x80000A5408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_3           , RULL(0x80000E5407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_3           , RULL(0x80000E5408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_4           , RULL(0x8000125407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P3_4           , RULL(0x8000125408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0             , RULL(0x800003540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0           , RULL(0x800003540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0           , RULL(0x800003540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1             , RULL(0x800007540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1           , RULL(0x800007540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1           , RULL(0x800007540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2             , RULL(0x80000B540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2           , RULL(0x80000B540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2           , RULL(0x80000B540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3             , RULL(0x80000F540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3           , RULL(0x80000F540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3           , RULL(0x80000F540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4             , RULL(0x800013540701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4           , RULL(0x800013540701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4           , RULL(0x800013540801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_0           , RULL(0x800003540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_0           , RULL(0x800003540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_1           , RULL(0x800007540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_1           , RULL(0x800007540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_2           , RULL(0x80000B540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_2           , RULL(0x80000B540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_3           , RULL(0x80000F540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_3           , RULL(0x80000F540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_4           , RULL(0x800013540701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P1_4           , RULL(0x800013540801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_0           , RULL(0x800003540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_0           , RULL(0x800003540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_1           , RULL(0x800007540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_1           , RULL(0x800007540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_2           , RULL(0x80000B540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_2           , RULL(0x80000B540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_3           , RULL(0x80000F540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_3           , RULL(0x80000F540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_4           , RULL(0x800013540701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P2_4           , RULL(0x800013540801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_0           , RULL(0x8000035407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_0           , RULL(0x8000035408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_1           , RULL(0x8000075407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_1           , RULL(0x8000075408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_2           , RULL(0x80000B5407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_2           , RULL(0x80000B5408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_3           , RULL(0x80000F5407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_3           , RULL(0x80000F5408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_4           , RULL(0x8000135407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P3_4           , RULL(0x8000135408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0             , RULL(0x800000550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0           , RULL(0x800000550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0           , RULL(0x800000550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1             , RULL(0x800004550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1           , RULL(0x800004550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1           , RULL(0x800004550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2             , RULL(0x800008550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2           , RULL(0x800008550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2           , RULL(0x800008550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3             , RULL(0x80000C550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3           , RULL(0x80000C550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3           , RULL(0x80000C550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4             , RULL(0x800010550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4           , RULL(0x800010550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4           , RULL(0x800010550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_0           , RULL(0x800000550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_0           , RULL(0x800000550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_1           , RULL(0x800004550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_1           , RULL(0x800004550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_2           , RULL(0x800008550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_2           , RULL(0x800008550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_3           , RULL(0x80000C550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_3           , RULL(0x80000C550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_4           , RULL(0x800010550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P1_4           , RULL(0x800010550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_0           , RULL(0x800000550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_0           , RULL(0x800000550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_1           , RULL(0x800004550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_1           , RULL(0x800004550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_2           , RULL(0x800008550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_2           , RULL(0x800008550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_3           , RULL(0x80000C550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_3           , RULL(0x80000C550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_4           , RULL(0x800010550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P2_4           , RULL(0x800010550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_0           , RULL(0x8000005507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_0           , RULL(0x8000005508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_1           , RULL(0x8000045507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_1           , RULL(0x8000045508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_2           , RULL(0x8000085507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_2           , RULL(0x8000085508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_3           , RULL(0x80000C5507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_3           , RULL(0x80000C5508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_4           , RULL(0x8000105507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P3_4           , RULL(0x8000105508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0             , RULL(0x800001550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0           , RULL(0x800001550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0           , RULL(0x800001550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1             , RULL(0x800005550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1           , RULL(0x800005550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1           , RULL(0x800005550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2             , RULL(0x800009550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2           , RULL(0x800009550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2           , RULL(0x800009550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3             , RULL(0x80000D550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3           , RULL(0x80000D550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3           , RULL(0x80000D550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4             , RULL(0x800011550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4           , RULL(0x800011550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4           , RULL(0x800011550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_0           , RULL(0x800001550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_0           , RULL(0x800001550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_1           , RULL(0x800005550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_1           , RULL(0x800005550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_2           , RULL(0x800009550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_2           , RULL(0x800009550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_3           , RULL(0x80000D550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_3           , RULL(0x80000D550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_4           , RULL(0x800011550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P1_4           , RULL(0x800011550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_0           , RULL(0x800001550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_0           , RULL(0x800001550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_1           , RULL(0x800005550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_1           , RULL(0x800005550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_2           , RULL(0x800009550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_2           , RULL(0x800009550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_3           , RULL(0x80000D550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_3           , RULL(0x80000D550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_4           , RULL(0x800011550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P2_4           , RULL(0x800011550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_0           , RULL(0x8000015507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_0           , RULL(0x8000015508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_1           , RULL(0x8000055507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_1           , RULL(0x8000055508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_2           , RULL(0x8000095507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_2           , RULL(0x8000095508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_3           , RULL(0x80000D5507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_3           , RULL(0x80000D5508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_4           , RULL(0x8000115507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P3_4           , RULL(0x8000115508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0             , RULL(0x800002550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0           , RULL(0x800002550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0           , RULL(0x800002550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1             , RULL(0x800006550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1           , RULL(0x800006550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1           , RULL(0x800006550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2             , RULL(0x80000A550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2           , RULL(0x80000A550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2           , RULL(0x80000A550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3             , RULL(0x80000E550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3           , RULL(0x80000E550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3           , RULL(0x80000E550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4             , RULL(0x800012550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4           , RULL(0x800012550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4           , RULL(0x800012550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_0           , RULL(0x800002550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_0           , RULL(0x800002550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_1           , RULL(0x800006550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_1           , RULL(0x800006550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_2           , RULL(0x80000A550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_2           , RULL(0x80000A550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_3           , RULL(0x80000E550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_3           , RULL(0x80000E550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_4           , RULL(0x800012550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P1_4           , RULL(0x800012550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_0           , RULL(0x800002550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_0           , RULL(0x800002550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_1           , RULL(0x800006550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_1           , RULL(0x800006550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_2           , RULL(0x80000A550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_2           , RULL(0x80000A550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_3           , RULL(0x80000E550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_3           , RULL(0x80000E550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_4           , RULL(0x800012550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P2_4           , RULL(0x800012550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_0           , RULL(0x8000025507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_0           , RULL(0x8000025508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_1           , RULL(0x8000065507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_1           , RULL(0x8000065508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_2           , RULL(0x80000A5507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_2           , RULL(0x80000A5508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_3           , RULL(0x80000E5507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_3           , RULL(0x80000E5508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_4           , RULL(0x8000125507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P3_4           , RULL(0x8000125508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0             , RULL(0x800003550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0           , RULL(0x800003550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0           , RULL(0x800003550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1             , RULL(0x800007550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1           , RULL(0x800007550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1           , RULL(0x800007550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2             , RULL(0x80000B550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2           , RULL(0x80000B550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2           , RULL(0x80000B550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3             , RULL(0x80000F550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3           , RULL(0x80000F550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3           , RULL(0x80000F550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4             , RULL(0x800013550701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4           , RULL(0x800013550701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4           , RULL(0x800013550801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_0           , RULL(0x800003550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_0           , RULL(0x800003550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_1           , RULL(0x800007550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_1           , RULL(0x800007550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_2           , RULL(0x80000B550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_2           , RULL(0x80000B550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_3           , RULL(0x80000F550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_3           , RULL(0x80000F550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_4           , RULL(0x800013550701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P1_4           , RULL(0x800013550801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_0           , RULL(0x800003550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_0           , RULL(0x800003550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_1           , RULL(0x800007550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_1           , RULL(0x800007550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_2           , RULL(0x80000B550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_2           , RULL(0x80000B550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_3           , RULL(0x80000F550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_3           , RULL(0x80000F550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_4           , RULL(0x800013550701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P2_4           , RULL(0x800013550801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_0           , RULL(0x8000035507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_0           , RULL(0x8000035508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_1           , RULL(0x8000075507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_1           , RULL(0x8000075508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_2           , RULL(0x80000B5507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_2           , RULL(0x80000B5508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_3           , RULL(0x80000F5507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_3           , RULL(0x80000F5508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_4           , RULL(0x8000135507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P3_4           , RULL(0x8000135508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0             , RULL(0x800000560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0           , RULL(0x800000560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0           , RULL(0x800000560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1             , RULL(0x800004560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1           , RULL(0x800004560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1           , RULL(0x800004560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2             , RULL(0x800008560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2           , RULL(0x800008560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2           , RULL(0x800008560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3             , RULL(0x80000C560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3           , RULL(0x80000C560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3           , RULL(0x80000C560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4             , RULL(0x800010560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4           , RULL(0x800010560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4           , RULL(0x800010560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_0           , RULL(0x800000560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_0           , RULL(0x800000560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_1           , RULL(0x800004560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_1           , RULL(0x800004560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_2           , RULL(0x800008560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_2           , RULL(0x800008560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_3           , RULL(0x80000C560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_3           , RULL(0x80000C560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_4           , RULL(0x800010560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P1_4           , RULL(0x800010560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_0           , RULL(0x800000560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_0           , RULL(0x800000560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_1           , RULL(0x800004560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_1           , RULL(0x800004560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_2           , RULL(0x800008560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_2           , RULL(0x800008560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_3           , RULL(0x80000C560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_3           , RULL(0x80000C560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_4           , RULL(0x800010560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P2_4           , RULL(0x800010560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_0           , RULL(0x8000005607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_0           , RULL(0x8000005608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_1           , RULL(0x8000045607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_1           , RULL(0x8000045608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_2           , RULL(0x8000085607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_2           , RULL(0x8000085608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_3           , RULL(0x80000C5607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_3           , RULL(0x80000C5608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_4           , RULL(0x8000105607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P3_4           , RULL(0x8000105608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0             , RULL(0x800001560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0           , RULL(0x800001560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0           , RULL(0x800001560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1             , RULL(0x800005560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1           , RULL(0x800005560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1           , RULL(0x800005560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2             , RULL(0x800009560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2           , RULL(0x800009560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2           , RULL(0x800009560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3             , RULL(0x80000D560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3           , RULL(0x80000D560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3           , RULL(0x80000D560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4             , RULL(0x800011560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4           , RULL(0x800011560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4           , RULL(0x800011560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_0           , RULL(0x800001560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_0           , RULL(0x800001560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_1           , RULL(0x800005560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_1           , RULL(0x800005560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_2           , RULL(0x800009560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_2           , RULL(0x800009560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_3           , RULL(0x80000D560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_3           , RULL(0x80000D560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_4           , RULL(0x800011560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P1_4           , RULL(0x800011560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_0           , RULL(0x800001560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_0           , RULL(0x800001560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_1           , RULL(0x800005560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_1           , RULL(0x800005560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_2           , RULL(0x800009560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_2           , RULL(0x800009560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_3           , RULL(0x80000D560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_3           , RULL(0x80000D560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_4           , RULL(0x800011560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P2_4           , RULL(0x800011560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_0           , RULL(0x8000015607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_0           , RULL(0x8000015608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_1           , RULL(0x8000055607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_1           , RULL(0x8000055608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_2           , RULL(0x8000095607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_2           , RULL(0x8000095608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_3           , RULL(0x80000D5607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_3           , RULL(0x80000D5608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_4           , RULL(0x8000115607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P3_4           , RULL(0x8000115608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0             , RULL(0x800002560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0           , RULL(0x800002560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0           , RULL(0x800002560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1             , RULL(0x800006560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1           , RULL(0x800006560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1           , RULL(0x800006560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2             , RULL(0x80000A560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2           , RULL(0x80000A560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2           , RULL(0x80000A560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3             , RULL(0x80000E560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3           , RULL(0x80000E560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3           , RULL(0x80000E560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4             , RULL(0x800012560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4           , RULL(0x800012560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4           , RULL(0x800012560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_0           , RULL(0x800002560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_0           , RULL(0x800002560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_1           , RULL(0x800006560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_1           , RULL(0x800006560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_2           , RULL(0x80000A560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_2           , RULL(0x80000A560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_3           , RULL(0x80000E560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_3           , RULL(0x80000E560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_4           , RULL(0x800012560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P1_4           , RULL(0x800012560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_0           , RULL(0x800002560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_0           , RULL(0x800002560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_1           , RULL(0x800006560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_1           , RULL(0x800006560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_2           , RULL(0x80000A560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_2           , RULL(0x80000A560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_3           , RULL(0x80000E560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_3           , RULL(0x80000E560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_4           , RULL(0x800012560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P2_4           , RULL(0x800012560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_0           , RULL(0x8000025607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_0           , RULL(0x8000025608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_1           , RULL(0x8000065607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_1           , RULL(0x8000065608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_2           , RULL(0x80000A5607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_2           , RULL(0x80000A5608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_3           , RULL(0x80000E5607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_3           , RULL(0x80000E5608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_4           , RULL(0x8000125607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P3_4           , RULL(0x8000125608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0             , RULL(0x800003560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0           , RULL(0x800003560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0           , RULL(0x800003560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1             , RULL(0x800007560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1           , RULL(0x800007560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1           , RULL(0x800007560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2             , RULL(0x80000B560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2           , RULL(0x80000B560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2           , RULL(0x80000B560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3             , RULL(0x80000F560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3           , RULL(0x80000F560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3           , RULL(0x80000F560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4             , RULL(0x800013560701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4           , RULL(0x800013560701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4           , RULL(0x800013560801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_0           , RULL(0x800003560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_0           , RULL(0x800003560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_1           , RULL(0x800007560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_1           , RULL(0x800007560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_2           , RULL(0x80000B560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_2           , RULL(0x80000B560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_3           , RULL(0x80000F560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_3           , RULL(0x80000F560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_4           , RULL(0x800013560701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P1_4           , RULL(0x800013560801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_0           , RULL(0x800003560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_0           , RULL(0x800003560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_1           , RULL(0x800007560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_1           , RULL(0x800007560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_2           , RULL(0x80000B560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_2           , RULL(0x80000B560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_3           , RULL(0x80000F560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_3           , RULL(0x80000F560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_4           , RULL(0x800013560701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P2_4           , RULL(0x800013560801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_0           , RULL(0x8000035607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_0           , RULL(0x8000035608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_1           , RULL(0x8000075607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_1           , RULL(0x8000075608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_2           , RULL(0x80000B5607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_2           , RULL(0x80000B5608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_3           , RULL(0x80000F5607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_3           , RULL(0x80000F5608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_4           , RULL(0x8000135607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P3_4           , RULL(0x8000135608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0             , RULL(0x800000570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0           , RULL(0x800000570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0           , RULL(0x800000570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1             , RULL(0x800004570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1           , RULL(0x800004570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1           , RULL(0x800004570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2             , RULL(0x800008570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2           , RULL(0x800008570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2           , RULL(0x800008570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3             , RULL(0x80000C570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3           , RULL(0x80000C570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3           , RULL(0x80000C570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4             , RULL(0x800010570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4           , RULL(0x800010570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4           , RULL(0x800010570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_0           , RULL(0x800000570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_0           , RULL(0x800000570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_1           , RULL(0x800004570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_1           , RULL(0x800004570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_2           , RULL(0x800008570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_2           , RULL(0x800008570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_3           , RULL(0x80000C570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_3           , RULL(0x80000C570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_4           , RULL(0x800010570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P1_4           , RULL(0x800010570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_0           , RULL(0x800000570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_0           , RULL(0x800000570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_1           , RULL(0x800004570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_1           , RULL(0x800004570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_2           , RULL(0x800008570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_2           , RULL(0x800008570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_3           , RULL(0x80000C570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_3           , RULL(0x80000C570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_4           , RULL(0x800010570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P2_4           , RULL(0x800010570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_0           , RULL(0x8000005707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_0           , RULL(0x8000005708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_1           , RULL(0x8000045707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_1           , RULL(0x8000045708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_2           , RULL(0x8000085707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_2           , RULL(0x8000085708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_3           , RULL(0x80000C5707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_3           , RULL(0x80000C5708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_4           , RULL(0x8000105707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P3_4           , RULL(0x8000105708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0             , RULL(0x800001570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0           , RULL(0x800001570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0           , RULL(0x800001570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1             , RULL(0x800005570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1           , RULL(0x800005570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1           , RULL(0x800005570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2             , RULL(0x800009570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2           , RULL(0x800009570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2           , RULL(0x800009570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3             , RULL(0x80000D570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3           , RULL(0x80000D570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3           , RULL(0x80000D570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4             , RULL(0x800011570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4           , RULL(0x800011570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4           , RULL(0x800011570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_0           , RULL(0x800001570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_0           , RULL(0x800001570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_1           , RULL(0x800005570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_1           , RULL(0x800005570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_2           , RULL(0x800009570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_2           , RULL(0x800009570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_3           , RULL(0x80000D570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_3           , RULL(0x80000D570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_4           , RULL(0x800011570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P1_4           , RULL(0x800011570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_0           , RULL(0x800001570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_0           , RULL(0x800001570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_1           , RULL(0x800005570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_1           , RULL(0x800005570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_2           , RULL(0x800009570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_2           , RULL(0x800009570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_3           , RULL(0x80000D570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_3           , RULL(0x80000D570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_4           , RULL(0x800011570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P2_4           , RULL(0x800011570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_0           , RULL(0x8000015707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_0           , RULL(0x8000015708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_1           , RULL(0x8000055707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_1           , RULL(0x8000055708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_2           , RULL(0x8000095707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_2           , RULL(0x8000095708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_3           , RULL(0x80000D5707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_3           , RULL(0x80000D5708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_4           , RULL(0x8000115707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P3_4           , RULL(0x8000115708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0             , RULL(0x800002570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0           , RULL(0x800002570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0           , RULL(0x800002570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1             , RULL(0x800006570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1           , RULL(0x800006570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1           , RULL(0x800006570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2             , RULL(0x80000A570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2           , RULL(0x80000A570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2           , RULL(0x80000A570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3             , RULL(0x80000E570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3           , RULL(0x80000E570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3           , RULL(0x80000E570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4             , RULL(0x800012570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4           , RULL(0x800012570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4           , RULL(0x800012570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_0           , RULL(0x800002570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_0           , RULL(0x800002570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_1           , RULL(0x800006570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_1           , RULL(0x800006570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_2           , RULL(0x80000A570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_2           , RULL(0x80000A570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_3           , RULL(0x80000E570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_3           , RULL(0x80000E570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_4           , RULL(0x800012570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P1_4           , RULL(0x800012570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_0           , RULL(0x800002570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_0           , RULL(0x800002570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_1           , RULL(0x800006570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_1           , RULL(0x800006570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_2           , RULL(0x80000A570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_2           , RULL(0x80000A570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_3           , RULL(0x80000E570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_3           , RULL(0x80000E570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_4           , RULL(0x800012570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P2_4           , RULL(0x800012570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_0           , RULL(0x8000025707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_0           , RULL(0x8000025708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_1           , RULL(0x8000065707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_1           , RULL(0x8000065708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_2           , RULL(0x80000A5707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_2           , RULL(0x80000A5708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_3           , RULL(0x80000E5707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_3           , RULL(0x80000E5708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_4           , RULL(0x8000125707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P3_4           , RULL(0x8000125708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0             , RULL(0x800003570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0           , RULL(0x800003570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0           , RULL(0x800003570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1             , RULL(0x800007570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1           , RULL(0x800007570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1           , RULL(0x800007570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2             , RULL(0x80000B570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2           , RULL(0x80000B570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2           , RULL(0x80000B570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3             , RULL(0x80000F570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3           , RULL(0x80000F570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3           , RULL(0x80000F570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4             , RULL(0x800013570701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4           , RULL(0x800013570701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4           , RULL(0x800013570801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_0           , RULL(0x800003570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_0           , RULL(0x800003570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_1           , RULL(0x800007570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_1           , RULL(0x800007570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_2           , RULL(0x80000B570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_2           , RULL(0x80000B570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_3           , RULL(0x80000F570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_3           , RULL(0x80000F570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_4           , RULL(0x800013570701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P1_4           , RULL(0x800013570801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_0           , RULL(0x800003570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_0           , RULL(0x800003570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_1           , RULL(0x800007570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_1           , RULL(0x800007570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_2           , RULL(0x80000B570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_2           , RULL(0x80000B570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_3           , RULL(0x80000F570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_3           , RULL(0x80000F570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_4           , RULL(0x800013570701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P2_4           , RULL(0x800013570801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_0           , RULL(0x8000035707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_0           , RULL(0x8000035708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_1           , RULL(0x8000075707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_1           , RULL(0x8000075708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_2           , RULL(0x80000B5707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_2           , RULL(0x80000B5708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_3           , RULL(0x80000F5707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_3           , RULL(0x80000F5708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_4           , RULL(0x8000135707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P3_4           , RULL(0x8000135708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0      , RULL(0x8000000C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0    , RULL(0x8000000C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0    , RULL(0x8000000C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1      , RULL(0x8000040C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1    , RULL(0x8000040C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1    , RULL(0x8000040C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2      , RULL(0x8000080C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2    , RULL(0x8000080C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2    , RULL(0x8000080C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3      , RULL(0x80000C0C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3    , RULL(0x80000C0C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3    , RULL(0x80000C0C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4      , RULL(0x8000100C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4    , RULL(0x8000100C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4    , RULL(0x8000100C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_0    , RULL(0x8000000C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_0    , RULL(0x8000000C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_1    , RULL(0x8000040C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_1    , RULL(0x8000040C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_2    , RULL(0x8000080C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_2    , RULL(0x8000080C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_3    , RULL(0x80000C0C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_3    , RULL(0x80000C0C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_4    , RULL(0x8000100C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P1_4    , RULL(0x8000100C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_0    , RULL(0x8000000C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_0    , RULL(0x8000000C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_1    , RULL(0x8000040C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_1    , RULL(0x8000040C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_2    , RULL(0x8000080C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_2    , RULL(0x8000080C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_3    , RULL(0x80000C0C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_3    , RULL(0x80000C0C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_4    , RULL(0x8000100C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P2_4    , RULL(0x8000100C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_0    , RULL(0x8000000C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_0    , RULL(0x8000000C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_1    , RULL(0x8000040C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_1    , RULL(0x8000040C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_2    , RULL(0x8000080C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_2    , RULL(0x8000080C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_3    , RULL(0x80000C0C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_3    , RULL(0x80000C0C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_4    , RULL(0x8000100C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P3_4    , RULL(0x8000100C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0      , RULL(0x8000010C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0    , RULL(0x8000010C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0    , RULL(0x8000010C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1      , RULL(0x8000050C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1    , RULL(0x8000050C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1    , RULL(0x8000050C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2      , RULL(0x8000090C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2    , RULL(0x8000090C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2    , RULL(0x8000090C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3      , RULL(0x80000D0C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3    , RULL(0x80000D0C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3    , RULL(0x80000D0C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4      , RULL(0x8000110C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4    , RULL(0x8000110C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4    , RULL(0x8000110C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_0    , RULL(0x8000010C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_0    , RULL(0x8000010C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_1    , RULL(0x8000050C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_1    , RULL(0x8000050C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_2    , RULL(0x8000090C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_2    , RULL(0x8000090C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_3    , RULL(0x80000D0C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_3    , RULL(0x80000D0C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_4    , RULL(0x8000110C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P1_4    , RULL(0x8000110C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_0    , RULL(0x8000010C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_0    , RULL(0x8000010C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_1    , RULL(0x8000050C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_1    , RULL(0x8000050C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_2    , RULL(0x8000090C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_2    , RULL(0x8000090C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_3    , RULL(0x80000D0C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_3    , RULL(0x80000D0C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_4    , RULL(0x8000110C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P2_4    , RULL(0x8000110C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_0    , RULL(0x8000010C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_0    , RULL(0x8000010C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_1    , RULL(0x8000050C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_1    , RULL(0x8000050C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_2    , RULL(0x8000090C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_2    , RULL(0x8000090C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_3    , RULL(0x80000D0C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_3    , RULL(0x80000D0C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_4    , RULL(0x8000110C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P3_4    , RULL(0x8000110C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0      , RULL(0x8000020C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0    , RULL(0x8000020C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0    , RULL(0x8000020C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1      , RULL(0x8000060C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1    , RULL(0x8000060C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1    , RULL(0x8000060C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2      , RULL(0x80000A0C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2    , RULL(0x80000A0C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2    , RULL(0x80000A0C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3      , RULL(0x80000E0C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3    , RULL(0x80000E0C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3    , RULL(0x80000E0C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4      , RULL(0x8000120C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4    , RULL(0x8000120C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4    , RULL(0x8000120C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_0    , RULL(0x8000020C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_0    , RULL(0x8000020C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_1    , RULL(0x8000060C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_1    , RULL(0x8000060C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_2    , RULL(0x80000A0C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_2    , RULL(0x80000A0C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_3    , RULL(0x80000E0C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_3    , RULL(0x80000E0C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_4    , RULL(0x8000120C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P1_4    , RULL(0x8000120C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_0    , RULL(0x8000020C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_0    , RULL(0x8000020C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_1    , RULL(0x8000060C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_1    , RULL(0x8000060C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_2    , RULL(0x80000A0C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_2    , RULL(0x80000A0C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_3    , RULL(0x80000E0C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_3    , RULL(0x80000E0C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_4    , RULL(0x8000120C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P2_4    , RULL(0x8000120C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_0    , RULL(0x8000020C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_0    , RULL(0x8000020C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_1    , RULL(0x8000060C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_1    , RULL(0x8000060C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_2    , RULL(0x80000A0C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_2    , RULL(0x80000A0C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_3    , RULL(0x80000E0C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_3    , RULL(0x80000E0C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_4    , RULL(0x8000120C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P3_4    , RULL(0x8000120C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0      , RULL(0x8000030C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0    , RULL(0x8000030C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0    , RULL(0x8000030C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1      , RULL(0x8000070C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1    , RULL(0x8000070C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1    , RULL(0x8000070C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2      , RULL(0x80000B0C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2    , RULL(0x80000B0C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2    , RULL(0x80000B0C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3      , RULL(0x80000F0C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3    , RULL(0x80000F0C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3    , RULL(0x80000F0C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4      , RULL(0x8000130C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4    , RULL(0x8000130C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4    , RULL(0x8000130C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_0    , RULL(0x8000030C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_0    , RULL(0x8000030C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_1    , RULL(0x8000070C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_1    , RULL(0x8000070C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_2    , RULL(0x80000B0C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_2    , RULL(0x80000B0C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_3    , RULL(0x80000F0C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_3    , RULL(0x80000F0C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_4    , RULL(0x8000130C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P1_4    , RULL(0x8000130C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_0    , RULL(0x8000030C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_0    , RULL(0x8000030C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_1    , RULL(0x8000070C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_1    , RULL(0x8000070C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_2    , RULL(0x80000B0C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_2    , RULL(0x80000B0C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_3    , RULL(0x80000F0C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_3    , RULL(0x80000F0C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_4    , RULL(0x8000130C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P2_4    , RULL(0x8000130C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_0    , RULL(0x8000030C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_0    , RULL(0x8000030C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_1    , RULL(0x8000070C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_1    , RULL(0x8000070C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_2    , RULL(0x80000B0C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_2    , RULL(0x80000B0C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_3    , RULL(0x80000F0C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_3    , RULL(0x80000F0C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_4    , RULL(0x8000130C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P3_4    , RULL(0x8000130C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0      , RULL(0x8000000D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0    , RULL(0x8000000D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0    , RULL(0x8000000D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1      , RULL(0x8000040D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1    , RULL(0x8000040D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1    , RULL(0x8000040D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2      , RULL(0x8000080D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2    , RULL(0x8000080D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2    , RULL(0x8000080D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3      , RULL(0x80000C0D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3    , RULL(0x80000C0D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3    , RULL(0x80000C0D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4      , RULL(0x8000100D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4    , RULL(0x8000100D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4    , RULL(0x8000100D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_0    , RULL(0x8000000D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_0    , RULL(0x8000000D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_1    , RULL(0x8000040D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_1    , RULL(0x8000040D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_2    , RULL(0x8000080D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_2    , RULL(0x8000080D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_3    , RULL(0x80000C0D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_3    , RULL(0x80000C0D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_4    , RULL(0x8000100D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P1_4    , RULL(0x8000100D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_0    , RULL(0x8000000D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_0    , RULL(0x8000000D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_1    , RULL(0x8000040D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_1    , RULL(0x8000040D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_2    , RULL(0x8000080D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_2    , RULL(0x8000080D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_3    , RULL(0x80000C0D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_3    , RULL(0x80000C0D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_4    , RULL(0x8000100D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P2_4    , RULL(0x8000100D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_0    , RULL(0x8000000D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_0    , RULL(0x8000000D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_1    , RULL(0x8000040D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_1    , RULL(0x8000040D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_2    , RULL(0x8000080D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_2    , RULL(0x8000080D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_3    , RULL(0x80000C0D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_3    , RULL(0x80000C0D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_4    , RULL(0x8000100D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P3_4    , RULL(0x8000100D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0      , RULL(0x8000010D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0    , RULL(0x8000010D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0    , RULL(0x8000010D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1      , RULL(0x8000050D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1    , RULL(0x8000050D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1    , RULL(0x8000050D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2      , RULL(0x8000090D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2    , RULL(0x8000090D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2    , RULL(0x8000090D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3      , RULL(0x80000D0D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3    , RULL(0x80000D0D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3    , RULL(0x80000D0D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4      , RULL(0x8000110D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4    , RULL(0x8000110D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4    , RULL(0x8000110D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_0    , RULL(0x8000010D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_0    , RULL(0x8000010D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_1    , RULL(0x8000050D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_1    , RULL(0x8000050D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_2    , RULL(0x8000090D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_2    , RULL(0x8000090D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_3    , RULL(0x80000D0D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_3    , RULL(0x80000D0D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_4    , RULL(0x8000110D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P1_4    , RULL(0x8000110D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_0    , RULL(0x8000010D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_0    , RULL(0x8000010D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_1    , RULL(0x8000050D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_1    , RULL(0x8000050D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_2    , RULL(0x8000090D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_2    , RULL(0x8000090D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_3    , RULL(0x80000D0D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_3    , RULL(0x80000D0D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_4    , RULL(0x8000110D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P2_4    , RULL(0x8000110D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_0    , RULL(0x8000010D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_0    , RULL(0x8000010D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_1    , RULL(0x8000050D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_1    , RULL(0x8000050D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_2    , RULL(0x8000090D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_2    , RULL(0x8000090D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_3    , RULL(0x80000D0D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_3    , RULL(0x80000D0D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_4    , RULL(0x8000110D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P3_4    , RULL(0x8000110D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0      , RULL(0x8000020D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0    , RULL(0x8000020D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0    , RULL(0x8000020D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1      , RULL(0x8000060D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1    , RULL(0x8000060D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1    , RULL(0x8000060D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2      , RULL(0x80000A0D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2    , RULL(0x80000A0D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2    , RULL(0x80000A0D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3      , RULL(0x80000E0D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3    , RULL(0x80000E0D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3    , RULL(0x80000E0D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4      , RULL(0x8000120D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4    , RULL(0x8000120D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4    , RULL(0x8000120D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_0    , RULL(0x8000020D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_0    , RULL(0x8000020D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_1    , RULL(0x8000060D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_1    , RULL(0x8000060D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_2    , RULL(0x80000A0D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_2    , RULL(0x80000A0D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_3    , RULL(0x80000E0D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_3    , RULL(0x80000E0D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_4    , RULL(0x8000120D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P1_4    , RULL(0x8000120D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_0    , RULL(0x8000020D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_0    , RULL(0x8000020D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_1    , RULL(0x8000060D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_1    , RULL(0x8000060D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_2    , RULL(0x80000A0D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_2    , RULL(0x80000A0D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_3    , RULL(0x80000E0D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_3    , RULL(0x80000E0D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_4    , RULL(0x8000120D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P2_4    , RULL(0x8000120D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_0    , RULL(0x8000020D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_0    , RULL(0x8000020D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_1    , RULL(0x8000060D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_1    , RULL(0x8000060D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_2    , RULL(0x80000A0D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_2    , RULL(0x80000A0D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_3    , RULL(0x80000E0D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_3    , RULL(0x80000E0D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_4    , RULL(0x8000120D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P3_4    , RULL(0x8000120D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0      , RULL(0x8000030D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0    , RULL(0x8000030D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0    , RULL(0x8000030D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1      , RULL(0x8000070D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1    , RULL(0x8000070D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1    , RULL(0x8000070D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2      , RULL(0x80000B0D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2    , RULL(0x80000B0D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2    , RULL(0x80000B0D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3      , RULL(0x80000F0D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3    , RULL(0x80000F0D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3    , RULL(0x80000F0D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4      , RULL(0x8000130D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4    , RULL(0x8000130D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4    , RULL(0x8000130D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_0    , RULL(0x8000030D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_0    , RULL(0x8000030D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_1    , RULL(0x8000070D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_1    , RULL(0x8000070D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_2    , RULL(0x80000B0D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_2    , RULL(0x80000B0D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_3    , RULL(0x80000F0D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_3    , RULL(0x80000F0D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_4    , RULL(0x8000130D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P1_4    , RULL(0x8000130D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_0    , RULL(0x8000030D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_0    , RULL(0x8000030D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_1    , RULL(0x8000070D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_1    , RULL(0x8000070D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_2    , RULL(0x80000B0D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_2    , RULL(0x80000B0D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_3    , RULL(0x80000F0D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_3    , RULL(0x80000F0D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_4    , RULL(0x8000130D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P2_4    , RULL(0x8000130D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_0    , RULL(0x8000030D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_0    , RULL(0x8000030D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_1    , RULL(0x8000070D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_1    , RULL(0x8000070D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_2    , RULL(0x80000B0D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_2    , RULL(0x80000B0D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_3    , RULL(0x80000F0D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_3    , RULL(0x80000F0D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_4    , RULL(0x8000130D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P3_4    , RULL(0x8000130D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0          , RULL(0x800000720701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0        , RULL(0x800000720701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0        , RULL(0x800000720801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1          , RULL(0x800004720701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1        , RULL(0x800004720701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1        , RULL(0x800004720801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2          , RULL(0x800008720701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2        , RULL(0x800008720701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2        , RULL(0x800008720801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3          , RULL(0x80000C720701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3        , RULL(0x80000C720701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3        , RULL(0x80000C720801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4          , RULL(0x800010720701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4        , RULL(0x800010720701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4        , RULL(0x800010720801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_0        , RULL(0x800000720701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_0        , RULL(0x800000720801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_1        , RULL(0x800004720701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_1        , RULL(0x800004720801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_2        , RULL(0x800008720701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_2        , RULL(0x800008720801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_3        , RULL(0x80000C720701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_3        , RULL(0x80000C720801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_4        , RULL(0x800010720701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P1_4        , RULL(0x800010720801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_0        , RULL(0x800000720701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_0        , RULL(0x800000720801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_1        , RULL(0x800004720701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_1        , RULL(0x800004720801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_2        , RULL(0x800008720701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_2        , RULL(0x800008720801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_3        , RULL(0x80000C720701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_3        , RULL(0x80000C720801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_4        , RULL(0x800010720701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P2_4        , RULL(0x800010720801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_0        , RULL(0x8000007207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_0        , RULL(0x8000007208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_1        , RULL(0x8000047207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_1        , RULL(0x8000047208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_2        , RULL(0x8000087207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_2        , RULL(0x8000087208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_3        , RULL(0x80000C7207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_3        , RULL(0x80000C7208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_4        , RULL(0x8000107207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P3_4        , RULL(0x8000107208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0          , RULL(0x800000600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0        , RULL(0x800000600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0        , RULL(0x800000600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1          , RULL(0x800004600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1        , RULL(0x800004600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1        , RULL(0x800004600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2          , RULL(0x800008600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2        , RULL(0x800008600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2        , RULL(0x800008600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3          , RULL(0x80000C600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3        , RULL(0x80000C600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3        , RULL(0x80000C600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4          , RULL(0x800010600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4        , RULL(0x800010600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4        , RULL(0x800010600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_0        , RULL(0x800000600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_0        , RULL(0x800000600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_1        , RULL(0x800004600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_1        , RULL(0x800004600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_2        , RULL(0x800008600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_2        , RULL(0x800008600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_3        , RULL(0x80000C600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_3        , RULL(0x80000C600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_4        , RULL(0x800010600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P1_4        , RULL(0x800010600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_0        , RULL(0x800000600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_0        , RULL(0x800000600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_1        , RULL(0x800004600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_1        , RULL(0x800004600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_2        , RULL(0x800008600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_2        , RULL(0x800008600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_3        , RULL(0x80000C600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_3        , RULL(0x80000C600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_4        , RULL(0x800010600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P2_4        , RULL(0x800010600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_0        , RULL(0x8000006007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_0        , RULL(0x8000006008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_1        , RULL(0x8000046007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_1        , RULL(0x8000046008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_2        , RULL(0x8000086007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_2        , RULL(0x8000086008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_3        , RULL(0x80000C6007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_3        , RULL(0x80000C6008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_4        , RULL(0x8000106007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P3_4        , RULL(0x8000106008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0          , RULL(0x800001600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0        , RULL(0x800001600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0        , RULL(0x800001600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1          , RULL(0x800005600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1        , RULL(0x800005600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1        , RULL(0x800005600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2          , RULL(0x800009600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2        , RULL(0x800009600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2        , RULL(0x800009600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3          , RULL(0x80000D600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3        , RULL(0x80000D600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3        , RULL(0x80000D600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4          , RULL(0x800011600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4        , RULL(0x800011600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4        , RULL(0x800011600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_0        , RULL(0x800001600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_0        , RULL(0x800001600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_1        , RULL(0x800005600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_1        , RULL(0x800005600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_2        , RULL(0x800009600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_2        , RULL(0x800009600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_3        , RULL(0x80000D600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_3        , RULL(0x80000D600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_4        , RULL(0x800011600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P1_4        , RULL(0x800011600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_0        , RULL(0x800001600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_0        , RULL(0x800001600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_1        , RULL(0x800005600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_1        , RULL(0x800005600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_2        , RULL(0x800009600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_2        , RULL(0x800009600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_3        , RULL(0x80000D600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_3        , RULL(0x80000D600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_4        , RULL(0x800011600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P2_4        , RULL(0x800011600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_0        , RULL(0x8000016007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_0        , RULL(0x8000016008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_1        , RULL(0x8000056007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_1        , RULL(0x8000056008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_2        , RULL(0x8000096007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_2        , RULL(0x8000096008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_3        , RULL(0x80000D6007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_3        , RULL(0x80000D6008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_4        , RULL(0x8000116007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P3_4        , RULL(0x8000116008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0          , RULL(0x800002600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0        , RULL(0x800002600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0        , RULL(0x800002600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1          , RULL(0x800006600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1        , RULL(0x800006600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1        , RULL(0x800006600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2          , RULL(0x80000A600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2        , RULL(0x80000A600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2        , RULL(0x80000A600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3          , RULL(0x80000E600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3        , RULL(0x80000E600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3        , RULL(0x80000E600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4          , RULL(0x800012600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4        , RULL(0x800012600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4        , RULL(0x800012600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_0        , RULL(0x800002600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_0        , RULL(0x800002600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_1        , RULL(0x800006600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_1        , RULL(0x800006600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_2        , RULL(0x80000A600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_2        , RULL(0x80000A600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_3        , RULL(0x80000E600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_3        , RULL(0x80000E600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_4        , RULL(0x800012600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P1_4        , RULL(0x800012600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_0        , RULL(0x800002600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_0        , RULL(0x800002600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_1        , RULL(0x800006600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_1        , RULL(0x800006600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_2        , RULL(0x80000A600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_2        , RULL(0x80000A600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_3        , RULL(0x80000E600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_3        , RULL(0x80000E600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_4        , RULL(0x800012600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P2_4        , RULL(0x800012600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_0        , RULL(0x8000026007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_0        , RULL(0x8000026008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_1        , RULL(0x8000066007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_1        , RULL(0x8000066008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_2        , RULL(0x80000A6007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_2        , RULL(0x80000A6008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_3        , RULL(0x80000E6007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_3        , RULL(0x80000E6008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_4        , RULL(0x8000126007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P3_4        , RULL(0x8000126008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0          , RULL(0x800003600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0        , RULL(0x800003600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0        , RULL(0x800003600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1          , RULL(0x800007600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1        , RULL(0x800007600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1        , RULL(0x800007600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2          , RULL(0x80000B600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2        , RULL(0x80000B600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2        , RULL(0x80000B600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3          , RULL(0x80000F600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3        , RULL(0x80000F600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3        , RULL(0x80000F600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4          , RULL(0x800013600701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4        , RULL(0x800013600701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4        , RULL(0x800013600801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_0        , RULL(0x800003600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_0        , RULL(0x800003600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_1        , RULL(0x800007600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_1        , RULL(0x800007600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_2        , RULL(0x80000B600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_2        , RULL(0x80000B600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_3        , RULL(0x80000F600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_3        , RULL(0x80000F600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_4        , RULL(0x800013600701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P1_4        , RULL(0x800013600801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_0        , RULL(0x800003600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_0        , RULL(0x800003600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_1        , RULL(0x800007600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_1        , RULL(0x800007600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_2        , RULL(0x80000B600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_2        , RULL(0x80000B600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_3        , RULL(0x80000F600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_3        , RULL(0x80000F600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_4        , RULL(0x800013600701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P2_4        , RULL(0x800013600801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_0        , RULL(0x8000036007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_0        , RULL(0x8000036008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_1        , RULL(0x8000076007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_1        , RULL(0x8000076008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_2        , RULL(0x80000B6007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_2        , RULL(0x80000B6008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_3        , RULL(0x80000F6007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_3        , RULL(0x80000F6008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_4        , RULL(0x8000136007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P3_4        , RULL(0x8000136008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0         , RULL(0x8000006A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0       , RULL(0x8000006A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0       , RULL(0x8000006A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1         , RULL(0x8000046A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1       , RULL(0x8000046A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1       , RULL(0x8000046A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2         , RULL(0x8000086A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2       , RULL(0x8000086A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2       , RULL(0x8000086A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3         , RULL(0x80000C6A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3       , RULL(0x80000C6A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3       , RULL(0x80000C6A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4         , RULL(0x8000106A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4       , RULL(0x8000106A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4       , RULL(0x8000106A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_0       , RULL(0x8000006A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_0       , RULL(0x8000006A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_1       , RULL(0x8000046A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_1       , RULL(0x8000046A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_2       , RULL(0x8000086A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_2       , RULL(0x8000086A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_3       , RULL(0x80000C6A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_3       , RULL(0x80000C6A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_4       , RULL(0x8000106A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P1_4       , RULL(0x8000106A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_0       , RULL(0x8000006A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_0       , RULL(0x8000006A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_1       , RULL(0x8000046A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_1       , RULL(0x8000046A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_2       , RULL(0x8000086A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_2       , RULL(0x8000086A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_3       , RULL(0x80000C6A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_3       , RULL(0x80000C6A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_4       , RULL(0x8000106A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P2_4       , RULL(0x8000106A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_0       , RULL(0x8000006A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_0       , RULL(0x8000006A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_1       , RULL(0x8000046A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_1       , RULL(0x8000046A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_2       , RULL(0x8000086A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_2       , RULL(0x8000086A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_3       , RULL(0x80000C6A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_3       , RULL(0x80000C6A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_4       , RULL(0x8000106A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P3_4       , RULL(0x8000106A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0         , RULL(0x8000016A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0       , RULL(0x8000016A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0       , RULL(0x8000016A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1         , RULL(0x8000056A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1       , RULL(0x8000056A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1       , RULL(0x8000056A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2         , RULL(0x8000096A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2       , RULL(0x8000096A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2       , RULL(0x8000096A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3         , RULL(0x80000D6A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3       , RULL(0x80000D6A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3       , RULL(0x80000D6A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4         , RULL(0x8000116A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4       , RULL(0x8000116A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4       , RULL(0x8000116A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_0       , RULL(0x8000016A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_0       , RULL(0x8000016A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_1       , RULL(0x8000056A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_1       , RULL(0x8000056A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_2       , RULL(0x8000096A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_2       , RULL(0x8000096A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_3       , RULL(0x80000D6A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_3       , RULL(0x80000D6A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_4       , RULL(0x8000116A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P1_4       , RULL(0x8000116A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_0       , RULL(0x8000016A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_0       , RULL(0x8000016A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_1       , RULL(0x8000056A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_1       , RULL(0x8000056A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_2       , RULL(0x8000096A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_2       , RULL(0x8000096A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_3       , RULL(0x80000D6A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_3       , RULL(0x80000D6A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_4       , RULL(0x8000116A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P2_4       , RULL(0x8000116A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_0       , RULL(0x8000016A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_0       , RULL(0x8000016A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_1       , RULL(0x8000056A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_1       , RULL(0x8000056A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_2       , RULL(0x8000096A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_2       , RULL(0x8000096A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_3       , RULL(0x80000D6A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_3       , RULL(0x80000D6A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_4       , RULL(0x8000116A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P3_4       , RULL(0x8000116A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0         , RULL(0x8000026A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0       , RULL(0x8000026A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0       , RULL(0x8000026A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1         , RULL(0x8000066A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1       , RULL(0x8000066A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1       , RULL(0x8000066A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2         , RULL(0x80000A6A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2       , RULL(0x80000A6A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2       , RULL(0x80000A6A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3         , RULL(0x80000E6A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3       , RULL(0x80000E6A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3       , RULL(0x80000E6A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4         , RULL(0x8000126A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4       , RULL(0x8000126A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4       , RULL(0x8000126A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_0       , RULL(0x8000026A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_0       , RULL(0x8000026A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_1       , RULL(0x8000066A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_1       , RULL(0x8000066A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_2       , RULL(0x80000A6A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_2       , RULL(0x80000A6A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_3       , RULL(0x80000E6A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_3       , RULL(0x80000E6A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_4       , RULL(0x8000126A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P1_4       , RULL(0x8000126A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_0       , RULL(0x8000026A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_0       , RULL(0x8000026A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_1       , RULL(0x8000066A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_1       , RULL(0x8000066A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_2       , RULL(0x80000A6A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_2       , RULL(0x80000A6A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_3       , RULL(0x80000E6A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_3       , RULL(0x80000E6A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_4       , RULL(0x8000126A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P2_4       , RULL(0x8000126A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_0       , RULL(0x8000026A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_0       , RULL(0x8000026A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_1       , RULL(0x8000066A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_1       , RULL(0x8000066A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_2       , RULL(0x80000A6A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_2       , RULL(0x80000A6A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_3       , RULL(0x80000E6A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_3       , RULL(0x80000E6A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_4       , RULL(0x8000126A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P3_4       , RULL(0x8000126A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0         , RULL(0x8000036A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0       , RULL(0x8000036A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0       , RULL(0x8000036A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1         , RULL(0x8000076A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1       , RULL(0x8000076A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1       , RULL(0x8000076A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2         , RULL(0x80000B6A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2       , RULL(0x80000B6A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2       , RULL(0x80000B6A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3         , RULL(0x80000F6A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3       , RULL(0x80000F6A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3       , RULL(0x80000F6A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4         , RULL(0x8000136A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4       , RULL(0x8000136A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4       , RULL(0x8000136A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_0       , RULL(0x8000036A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_0       , RULL(0x8000036A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_1       , RULL(0x8000076A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_1       , RULL(0x8000076A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_2       , RULL(0x80000B6A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_2       , RULL(0x80000B6A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_3       , RULL(0x80000F6A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_3       , RULL(0x80000F6A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_4       , RULL(0x8000136A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P1_4       , RULL(0x8000136A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_0       , RULL(0x8000036A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_0       , RULL(0x8000036A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_1       , RULL(0x8000076A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_1       , RULL(0x8000076A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_2       , RULL(0x80000B6A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_2       , RULL(0x80000B6A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_3       , RULL(0x80000F6A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_3       , RULL(0x80000F6A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_4       , RULL(0x8000136A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P2_4       , RULL(0x8000136A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_0       , RULL(0x8000036A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_0       , RULL(0x8000036A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_1       , RULL(0x8000076A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_1       , RULL(0x8000076A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_2       , RULL(0x80000B6A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_2       , RULL(0x80000B6A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_3       , RULL(0x80000F6A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_3       , RULL(0x80000F6A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_4       , RULL(0x8000136A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P3_4       , RULL(0x8000136A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0         , RULL(0x8000006B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0       , RULL(0x8000006B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0       , RULL(0x8000006B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1         , RULL(0x8000046B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1       , RULL(0x8000046B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1       , RULL(0x8000046B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2         , RULL(0x8000086B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2       , RULL(0x8000086B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2       , RULL(0x8000086B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3         , RULL(0x80000C6B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3       , RULL(0x80000C6B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3       , RULL(0x80000C6B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4         , RULL(0x8000106B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4       , RULL(0x8000106B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4       , RULL(0x8000106B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_0       , RULL(0x8000006B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_0       , RULL(0x8000006B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_1       , RULL(0x8000046B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_1       , RULL(0x8000046B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_2       , RULL(0x8000086B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_2       , RULL(0x8000086B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_3       , RULL(0x80000C6B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_3       , RULL(0x80000C6B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_4       , RULL(0x8000106B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P1_4       , RULL(0x8000106B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_0       , RULL(0x8000006B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_0       , RULL(0x8000006B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_1       , RULL(0x8000046B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_1       , RULL(0x8000046B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_2       , RULL(0x8000086B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_2       , RULL(0x8000086B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_3       , RULL(0x80000C6B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_3       , RULL(0x80000C6B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_4       , RULL(0x8000106B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P2_4       , RULL(0x8000106B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_0       , RULL(0x8000006B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_0       , RULL(0x8000006B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_1       , RULL(0x8000046B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_1       , RULL(0x8000046B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_2       , RULL(0x8000086B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_2       , RULL(0x8000086B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_3       , RULL(0x80000C6B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_3       , RULL(0x80000C6B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_4       , RULL(0x8000106B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P3_4       , RULL(0x8000106B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0         , RULL(0x8000016B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0       , RULL(0x8000016B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0       , RULL(0x8000016B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1         , RULL(0x8000056B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1       , RULL(0x8000056B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1       , RULL(0x8000056B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2         , RULL(0x8000096B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2       , RULL(0x8000096B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2       , RULL(0x8000096B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3         , RULL(0x80000D6B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3       , RULL(0x80000D6B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3       , RULL(0x80000D6B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4         , RULL(0x8000116B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4       , RULL(0x8000116B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4       , RULL(0x8000116B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_0       , RULL(0x8000016B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_0       , RULL(0x8000016B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_1       , RULL(0x8000056B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_1       , RULL(0x8000056B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_2       , RULL(0x8000096B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_2       , RULL(0x8000096B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_3       , RULL(0x80000D6B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_3       , RULL(0x80000D6B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_4       , RULL(0x8000116B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P1_4       , RULL(0x8000116B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_0       , RULL(0x8000016B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_0       , RULL(0x8000016B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_1       , RULL(0x8000056B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_1       , RULL(0x8000056B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_2       , RULL(0x8000096B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_2       , RULL(0x8000096B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_3       , RULL(0x80000D6B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_3       , RULL(0x80000D6B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_4       , RULL(0x8000116B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P2_4       , RULL(0x8000116B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_0       , RULL(0x8000016B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_0       , RULL(0x8000016B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_1       , RULL(0x8000056B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_1       , RULL(0x8000056B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_2       , RULL(0x8000096B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_2       , RULL(0x8000096B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_3       , RULL(0x80000D6B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_3       , RULL(0x80000D6B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_4       , RULL(0x8000116B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P3_4       , RULL(0x8000116B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0         , RULL(0x8000026B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0       , RULL(0x8000026B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0       , RULL(0x8000026B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1         , RULL(0x8000066B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1       , RULL(0x8000066B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1       , RULL(0x8000066B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2         , RULL(0x80000A6B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2       , RULL(0x80000A6B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2       , RULL(0x80000A6B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3         , RULL(0x80000E6B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3       , RULL(0x80000E6B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3       , RULL(0x80000E6B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4         , RULL(0x8000126B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4       , RULL(0x8000126B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4       , RULL(0x8000126B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_0       , RULL(0x8000026B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_0       , RULL(0x8000026B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_1       , RULL(0x8000066B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_1       , RULL(0x8000066B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_2       , RULL(0x80000A6B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_2       , RULL(0x80000A6B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_3       , RULL(0x80000E6B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_3       , RULL(0x80000E6B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_4       , RULL(0x8000126B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P1_4       , RULL(0x8000126B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_0       , RULL(0x8000026B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_0       , RULL(0x8000026B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_1       , RULL(0x8000066B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_1       , RULL(0x8000066B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_2       , RULL(0x80000A6B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_2       , RULL(0x80000A6B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_3       , RULL(0x80000E6B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_3       , RULL(0x80000E6B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_4       , RULL(0x8000126B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P2_4       , RULL(0x8000126B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_0       , RULL(0x8000026B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_0       , RULL(0x8000026B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_1       , RULL(0x8000066B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_1       , RULL(0x8000066B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_2       , RULL(0x80000A6B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_2       , RULL(0x80000A6B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_3       , RULL(0x80000E6B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_3       , RULL(0x80000E6B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_4       , RULL(0x8000126B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P3_4       , RULL(0x8000126B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0         , RULL(0x8000036B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0       , RULL(0x8000036B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0       , RULL(0x8000036B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1         , RULL(0x8000076B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1       , RULL(0x8000076B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1       , RULL(0x8000076B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2         , RULL(0x80000B6B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2       , RULL(0x80000B6B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2       , RULL(0x80000B6B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3         , RULL(0x80000F6B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3       , RULL(0x80000F6B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3       , RULL(0x80000F6B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4         , RULL(0x8000136B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4       , RULL(0x8000136B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4       , RULL(0x8000136B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_0       , RULL(0x8000036B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_0       , RULL(0x8000036B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_1       , RULL(0x8000076B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_1       , RULL(0x8000076B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_2       , RULL(0x80000B6B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_2       , RULL(0x80000B6B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_3       , RULL(0x80000F6B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_3       , RULL(0x80000F6B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_4       , RULL(0x8000136B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P1_4       , RULL(0x8000136B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_0       , RULL(0x8000036B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_0       , RULL(0x8000036B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_1       , RULL(0x8000076B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_1       , RULL(0x8000076B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_2       , RULL(0x80000B6B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_2       , RULL(0x80000B6B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_3       , RULL(0x80000F6B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_3       , RULL(0x80000F6B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_4       , RULL(0x8000136B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P2_4       , RULL(0x8000136B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_0       , RULL(0x8000036B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_0       , RULL(0x8000036B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_1       , RULL(0x8000076B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_1       , RULL(0x8000076B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_2       , RULL(0x80000B6B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_2       , RULL(0x80000B6B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_3       , RULL(0x80000F6B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_3       , RULL(0x80000F6B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_4       , RULL(0x8000136B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P3_4       , RULL(0x8000136B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0          , RULL(0x800000610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0        , RULL(0x800000610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0        , RULL(0x800000610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1          , RULL(0x800004610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1        , RULL(0x800004610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1        , RULL(0x800004610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2          , RULL(0x800008610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2        , RULL(0x800008610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2        , RULL(0x800008610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3          , RULL(0x80000C610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3        , RULL(0x80000C610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3        , RULL(0x80000C610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4          , RULL(0x800010610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4        , RULL(0x800010610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4        , RULL(0x800010610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_0        , RULL(0x800000610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_0        , RULL(0x800000610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_1        , RULL(0x800004610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_1        , RULL(0x800004610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_2        , RULL(0x800008610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_2        , RULL(0x800008610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_3        , RULL(0x80000C610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_3        , RULL(0x80000C610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_4        , RULL(0x800010610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P1_4        , RULL(0x800010610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_0        , RULL(0x800000610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_0        , RULL(0x800000610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_1        , RULL(0x800004610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_1        , RULL(0x800004610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_2        , RULL(0x800008610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_2        , RULL(0x800008610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_3        , RULL(0x80000C610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_3        , RULL(0x80000C610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_4        , RULL(0x800010610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P2_4        , RULL(0x800010610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_0        , RULL(0x8000006107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_0        , RULL(0x8000006108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_1        , RULL(0x8000046107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_1        , RULL(0x8000046108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_2        , RULL(0x8000086107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_2        , RULL(0x8000086108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_3        , RULL(0x80000C6107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_3        , RULL(0x80000C6108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_4        , RULL(0x8000106107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P3_4        , RULL(0x8000106108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0          , RULL(0x800001610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0        , RULL(0x800001610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0        , RULL(0x800001610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1          , RULL(0x800005610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1        , RULL(0x800005610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1        , RULL(0x800005610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2          , RULL(0x800009610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2        , RULL(0x800009610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2        , RULL(0x800009610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3          , RULL(0x80000D610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3        , RULL(0x80000D610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3        , RULL(0x80000D610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4          , RULL(0x800011610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4        , RULL(0x800011610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4        , RULL(0x800011610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_0        , RULL(0x800001610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_0        , RULL(0x800001610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_1        , RULL(0x800005610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_1        , RULL(0x800005610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_2        , RULL(0x800009610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_2        , RULL(0x800009610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_3        , RULL(0x80000D610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_3        , RULL(0x80000D610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_4        , RULL(0x800011610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P1_4        , RULL(0x800011610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_0        , RULL(0x800001610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_0        , RULL(0x800001610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_1        , RULL(0x800005610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_1        , RULL(0x800005610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_2        , RULL(0x800009610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_2        , RULL(0x800009610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_3        , RULL(0x80000D610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_3        , RULL(0x80000D610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_4        , RULL(0x800011610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P2_4        , RULL(0x800011610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_0        , RULL(0x8000016107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_0        , RULL(0x8000016108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_1        , RULL(0x8000056107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_1        , RULL(0x8000056108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_2        , RULL(0x8000096107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_2        , RULL(0x8000096108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_3        , RULL(0x80000D6107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_3        , RULL(0x80000D6108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_4        , RULL(0x8000116107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P3_4        , RULL(0x8000116108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0          , RULL(0x800002610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0        , RULL(0x800002610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0        , RULL(0x800002610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1          , RULL(0x800006610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1        , RULL(0x800006610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1        , RULL(0x800006610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2          , RULL(0x80000A610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2        , RULL(0x80000A610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2        , RULL(0x80000A610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3          , RULL(0x80000E610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3        , RULL(0x80000E610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3        , RULL(0x80000E610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4          , RULL(0x800012610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4        , RULL(0x800012610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4        , RULL(0x800012610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_0        , RULL(0x800002610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_0        , RULL(0x800002610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_1        , RULL(0x800006610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_1        , RULL(0x800006610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_2        , RULL(0x80000A610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_2        , RULL(0x80000A610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_3        , RULL(0x80000E610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_3        , RULL(0x80000E610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_4        , RULL(0x800012610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P1_4        , RULL(0x800012610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_0        , RULL(0x800002610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_0        , RULL(0x800002610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_1        , RULL(0x800006610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_1        , RULL(0x800006610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_2        , RULL(0x80000A610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_2        , RULL(0x80000A610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_3        , RULL(0x80000E610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_3        , RULL(0x80000E610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_4        , RULL(0x800012610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P2_4        , RULL(0x800012610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_0        , RULL(0x8000026107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_0        , RULL(0x8000026108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_1        , RULL(0x8000066107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_1        , RULL(0x8000066108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_2        , RULL(0x80000A6107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_2        , RULL(0x80000A6108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_3        , RULL(0x80000E6107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_3        , RULL(0x80000E6108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_4        , RULL(0x8000126107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P3_4        , RULL(0x8000126108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0          , RULL(0x800003610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0        , RULL(0x800003610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0        , RULL(0x800003610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1          , RULL(0x800007610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1        , RULL(0x800007610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1        , RULL(0x800007610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2          , RULL(0x80000B610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2        , RULL(0x80000B610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2        , RULL(0x80000B610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3          , RULL(0x80000F610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3        , RULL(0x80000F610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3        , RULL(0x80000F610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4          , RULL(0x800013610701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4        , RULL(0x800013610701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4        , RULL(0x800013610801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_0        , RULL(0x800003610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_0        , RULL(0x800003610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_1        , RULL(0x800007610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_1        , RULL(0x800007610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_2        , RULL(0x80000B610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_2        , RULL(0x80000B610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_3        , RULL(0x80000F610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_3        , RULL(0x80000F610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_4        , RULL(0x800013610701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P1_4        , RULL(0x800013610801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_0        , RULL(0x800003610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_0        , RULL(0x800003610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_1        , RULL(0x800007610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_1        , RULL(0x800007610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_2        , RULL(0x80000B610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_2        , RULL(0x80000B610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_3        , RULL(0x80000F610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_3        , RULL(0x80000F610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_4        , RULL(0x800013610701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P2_4        , RULL(0x800013610801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_0        , RULL(0x8000036107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_0        , RULL(0x8000036108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_1        , RULL(0x8000076107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_1        , RULL(0x8000076108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_2        , RULL(0x80000B6107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_2        , RULL(0x80000B6108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_3        , RULL(0x80000F6107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_3        , RULL(0x80000F6108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_4        , RULL(0x8000136107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P3_4        , RULL(0x8000136108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0          , RULL(0x800000620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0        , RULL(0x800000620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0        , RULL(0x800000620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1          , RULL(0x800004620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1        , RULL(0x800004620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1        , RULL(0x800004620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2          , RULL(0x800008620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2        , RULL(0x800008620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2        , RULL(0x800008620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3          , RULL(0x80000C620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3        , RULL(0x80000C620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3        , RULL(0x80000C620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4          , RULL(0x800010620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4        , RULL(0x800010620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4        , RULL(0x800010620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_0        , RULL(0x800000620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_0        , RULL(0x800000620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_1        , RULL(0x800004620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_1        , RULL(0x800004620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_2        , RULL(0x800008620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_2        , RULL(0x800008620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_3        , RULL(0x80000C620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_3        , RULL(0x80000C620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_4        , RULL(0x800010620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P1_4        , RULL(0x800010620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_0        , RULL(0x800000620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_0        , RULL(0x800000620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_1        , RULL(0x800004620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_1        , RULL(0x800004620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_2        , RULL(0x800008620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_2        , RULL(0x800008620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_3        , RULL(0x80000C620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_3        , RULL(0x80000C620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_4        , RULL(0x800010620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P2_4        , RULL(0x800010620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_0        , RULL(0x8000006207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_0        , RULL(0x8000006208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_1        , RULL(0x8000046207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_1        , RULL(0x8000046208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_2        , RULL(0x8000086207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_2        , RULL(0x8000086208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_3        , RULL(0x80000C6207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_3        , RULL(0x80000C6208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_4        , RULL(0x8000106207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P3_4        , RULL(0x8000106208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0          , RULL(0x800001620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0        , RULL(0x800001620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0        , RULL(0x800001620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1          , RULL(0x800005620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1        , RULL(0x800005620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1        , RULL(0x800005620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2          , RULL(0x800009620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2        , RULL(0x800009620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2        , RULL(0x800009620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3          , RULL(0x80000D620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3        , RULL(0x80000D620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3        , RULL(0x80000D620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4          , RULL(0x800011620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4        , RULL(0x800011620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4        , RULL(0x800011620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_0        , RULL(0x800001620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_0        , RULL(0x800001620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_1        , RULL(0x800005620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_1        , RULL(0x800005620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_2        , RULL(0x800009620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_2        , RULL(0x800009620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_3        , RULL(0x80000D620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_3        , RULL(0x80000D620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_4        , RULL(0x800011620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P1_4        , RULL(0x800011620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_0        , RULL(0x800001620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_0        , RULL(0x800001620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_1        , RULL(0x800005620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_1        , RULL(0x800005620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_2        , RULL(0x800009620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_2        , RULL(0x800009620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_3        , RULL(0x80000D620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_3        , RULL(0x80000D620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_4        , RULL(0x800011620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P2_4        , RULL(0x800011620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_0        , RULL(0x8000016207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_0        , RULL(0x8000016208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_1        , RULL(0x8000056207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_1        , RULL(0x8000056208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_2        , RULL(0x8000096207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_2        , RULL(0x8000096208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_3        , RULL(0x80000D6207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_3        , RULL(0x80000D6208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_4        , RULL(0x8000116207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P3_4        , RULL(0x8000116208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0          , RULL(0x800002620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0        , RULL(0x800002620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0        , RULL(0x800002620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1          , RULL(0x800006620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1        , RULL(0x800006620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1        , RULL(0x800006620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2          , RULL(0x80000A620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2        , RULL(0x80000A620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2        , RULL(0x80000A620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3          , RULL(0x80000E620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3        , RULL(0x80000E620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3        , RULL(0x80000E620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4          , RULL(0x800012620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4        , RULL(0x800012620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4        , RULL(0x800012620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_0        , RULL(0x800002620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_0        , RULL(0x800002620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_1        , RULL(0x800006620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_1        , RULL(0x800006620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_2        , RULL(0x80000A620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_2        , RULL(0x80000A620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_3        , RULL(0x80000E620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_3        , RULL(0x80000E620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_4        , RULL(0x800012620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P1_4        , RULL(0x800012620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_0        , RULL(0x800002620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_0        , RULL(0x800002620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_1        , RULL(0x800006620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_1        , RULL(0x800006620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_2        , RULL(0x80000A620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_2        , RULL(0x80000A620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_3        , RULL(0x80000E620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_3        , RULL(0x80000E620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_4        , RULL(0x800012620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P2_4        , RULL(0x800012620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_0        , RULL(0x8000026207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_0        , RULL(0x8000026208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_1        , RULL(0x8000066207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_1        , RULL(0x8000066208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_2        , RULL(0x80000A6207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_2        , RULL(0x80000A6208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_3        , RULL(0x80000E6207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_3        , RULL(0x80000E6208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_4        , RULL(0x8000126207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P3_4        , RULL(0x8000126208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0          , RULL(0x800003620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0        , RULL(0x800003620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0        , RULL(0x800003620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1          , RULL(0x800007620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1        , RULL(0x800007620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1        , RULL(0x800007620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2          , RULL(0x80000B620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2        , RULL(0x80000B620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2        , RULL(0x80000B620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3          , RULL(0x80000F620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3        , RULL(0x80000F620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3        , RULL(0x80000F620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4          , RULL(0x800013620701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4        , RULL(0x800013620701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4        , RULL(0x800013620801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_0        , RULL(0x800003620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_0        , RULL(0x800003620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_1        , RULL(0x800007620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_1        , RULL(0x800007620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_2        , RULL(0x80000B620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_2        , RULL(0x80000B620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_3        , RULL(0x80000F620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_3        , RULL(0x80000F620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_4        , RULL(0x800013620701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P1_4        , RULL(0x800013620801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_0        , RULL(0x800003620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_0        , RULL(0x800003620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_1        , RULL(0x800007620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_1        , RULL(0x800007620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_2        , RULL(0x80000B620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_2        , RULL(0x80000B620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_3        , RULL(0x80000F620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_3        , RULL(0x80000F620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_4        , RULL(0x800013620701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P2_4        , RULL(0x800013620801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_0        , RULL(0x8000036207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_0        , RULL(0x8000036208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_1        , RULL(0x8000076207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_1        , RULL(0x8000076208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_2        , RULL(0x80000B6207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_2        , RULL(0x80000B6208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_3        , RULL(0x80000F6207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_3        , RULL(0x80000F6208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_4        , RULL(0x8000136207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P3_4        , RULL(0x8000136208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0          , RULL(0x800000630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0        , RULL(0x800000630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0        , RULL(0x800000630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1          , RULL(0x800004630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1        , RULL(0x800004630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1        , RULL(0x800004630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2          , RULL(0x800008630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2        , RULL(0x800008630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2        , RULL(0x800008630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3          , RULL(0x80000C630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3        , RULL(0x80000C630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3        , RULL(0x80000C630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4          , RULL(0x800010630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4        , RULL(0x800010630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4        , RULL(0x800010630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_0        , RULL(0x800000630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_0        , RULL(0x800000630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_1        , RULL(0x800004630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_1        , RULL(0x800004630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_2        , RULL(0x800008630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_2        , RULL(0x800008630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_3        , RULL(0x80000C630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_3        , RULL(0x80000C630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_4        , RULL(0x800010630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P1_4        , RULL(0x800010630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_0        , RULL(0x800000630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_0        , RULL(0x800000630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_1        , RULL(0x800004630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_1        , RULL(0x800004630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_2        , RULL(0x800008630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_2        , RULL(0x800008630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_3        , RULL(0x80000C630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_3        , RULL(0x80000C630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_4        , RULL(0x800010630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P2_4        , RULL(0x800010630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_0        , RULL(0x8000006307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_0        , RULL(0x8000006308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_1        , RULL(0x8000046307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_1        , RULL(0x8000046308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_2        , RULL(0x8000086307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_2        , RULL(0x8000086308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_3        , RULL(0x80000C6307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_3        , RULL(0x80000C6308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_4        , RULL(0x8000106307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P3_4        , RULL(0x8000106308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0          , RULL(0x800001630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0        , RULL(0x800001630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0        , RULL(0x800001630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1          , RULL(0x800005630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1        , RULL(0x800005630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1        , RULL(0x800005630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2          , RULL(0x800009630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2        , RULL(0x800009630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2        , RULL(0x800009630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3          , RULL(0x80000D630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3        , RULL(0x80000D630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3        , RULL(0x80000D630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4          , RULL(0x800011630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4        , RULL(0x800011630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4        , RULL(0x800011630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_0        , RULL(0x800001630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_0        , RULL(0x800001630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_1        , RULL(0x800005630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_1        , RULL(0x800005630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_2        , RULL(0x800009630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_2        , RULL(0x800009630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_3        , RULL(0x80000D630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_3        , RULL(0x80000D630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_4        , RULL(0x800011630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P1_4        , RULL(0x800011630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_0        , RULL(0x800001630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_0        , RULL(0x800001630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_1        , RULL(0x800005630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_1        , RULL(0x800005630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_2        , RULL(0x800009630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_2        , RULL(0x800009630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_3        , RULL(0x80000D630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_3        , RULL(0x80000D630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_4        , RULL(0x800011630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P2_4        , RULL(0x800011630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_0        , RULL(0x8000016307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_0        , RULL(0x8000016308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_1        , RULL(0x8000056307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_1        , RULL(0x8000056308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_2        , RULL(0x8000096307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_2        , RULL(0x8000096308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_3        , RULL(0x80000D6307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_3        , RULL(0x80000D6308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_4        , RULL(0x8000116307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P3_4        , RULL(0x8000116308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0          , RULL(0x800002630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0        , RULL(0x800002630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0        , RULL(0x800002630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1          , RULL(0x800006630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1        , RULL(0x800006630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1        , RULL(0x800006630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2          , RULL(0x80000A630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2        , RULL(0x80000A630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2        , RULL(0x80000A630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3          , RULL(0x80000E630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3        , RULL(0x80000E630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3        , RULL(0x80000E630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4          , RULL(0x800012630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4        , RULL(0x800012630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4        , RULL(0x800012630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_0        , RULL(0x800002630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_0        , RULL(0x800002630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_1        , RULL(0x800006630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_1        , RULL(0x800006630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_2        , RULL(0x80000A630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_2        , RULL(0x80000A630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_3        , RULL(0x80000E630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_3        , RULL(0x80000E630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_4        , RULL(0x800012630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P1_4        , RULL(0x800012630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_0        , RULL(0x800002630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_0        , RULL(0x800002630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_1        , RULL(0x800006630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_1        , RULL(0x800006630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_2        , RULL(0x80000A630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_2        , RULL(0x80000A630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_3        , RULL(0x80000E630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_3        , RULL(0x80000E630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_4        , RULL(0x800012630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P2_4        , RULL(0x800012630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_0        , RULL(0x8000026307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_0        , RULL(0x8000026308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_1        , RULL(0x8000066307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_1        , RULL(0x8000066308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_2        , RULL(0x80000A6307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_2        , RULL(0x80000A6308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_3        , RULL(0x80000E6307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_3        , RULL(0x80000E6308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_4        , RULL(0x8000126307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P3_4        , RULL(0x8000126308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0          , RULL(0x800003630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0        , RULL(0x800003630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0        , RULL(0x800003630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1          , RULL(0x800007630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1        , RULL(0x800007630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1        , RULL(0x800007630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2          , RULL(0x80000B630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2        , RULL(0x80000B630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2        , RULL(0x80000B630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3          , RULL(0x80000F630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3        , RULL(0x80000F630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3        , RULL(0x80000F630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4          , RULL(0x800013630701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4        , RULL(0x800013630701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4        , RULL(0x800013630801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_0        , RULL(0x800003630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_0        , RULL(0x800003630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_1        , RULL(0x800007630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_1        , RULL(0x800007630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_2        , RULL(0x80000B630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_2        , RULL(0x80000B630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_3        , RULL(0x80000F630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_3        , RULL(0x80000F630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_4        , RULL(0x800013630701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P1_4        , RULL(0x800013630801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_0        , RULL(0x800003630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_0        , RULL(0x800003630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_1        , RULL(0x800007630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_1        , RULL(0x800007630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_2        , RULL(0x80000B630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_2        , RULL(0x80000B630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_3        , RULL(0x80000F630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_3        , RULL(0x80000F630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_4        , RULL(0x800013630701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P2_4        , RULL(0x800013630801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_0        , RULL(0x8000036307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_0        , RULL(0x8000036308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_1        , RULL(0x8000076307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_1        , RULL(0x8000076308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_2        , RULL(0x80000B6307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_2        , RULL(0x80000B6308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_3        , RULL(0x80000F6307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_3        , RULL(0x80000F6308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_4        , RULL(0x8000136307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P3_4        , RULL(0x8000136308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0          , RULL(0x800000640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0        , RULL(0x800000640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0        , RULL(0x800000640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1          , RULL(0x800004640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1        , RULL(0x800004640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1        , RULL(0x800004640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2          , RULL(0x800008640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2        , RULL(0x800008640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2        , RULL(0x800008640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3          , RULL(0x80000C640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3        , RULL(0x80000C640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3        , RULL(0x80000C640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4          , RULL(0x800010640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4        , RULL(0x800010640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4        , RULL(0x800010640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_0        , RULL(0x800000640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_0        , RULL(0x800000640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_1        , RULL(0x800004640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_1        , RULL(0x800004640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_2        , RULL(0x800008640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_2        , RULL(0x800008640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_3        , RULL(0x80000C640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_3        , RULL(0x80000C640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_4        , RULL(0x800010640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P1_4        , RULL(0x800010640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_0        , RULL(0x800000640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_0        , RULL(0x800000640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_1        , RULL(0x800004640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_1        , RULL(0x800004640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_2        , RULL(0x800008640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_2        , RULL(0x800008640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_3        , RULL(0x80000C640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_3        , RULL(0x80000C640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_4        , RULL(0x800010640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P2_4        , RULL(0x800010640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_0        , RULL(0x8000006407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_0        , RULL(0x8000006408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_1        , RULL(0x8000046407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_1        , RULL(0x8000046408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_2        , RULL(0x8000086407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_2        , RULL(0x8000086408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_3        , RULL(0x80000C6407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_3        , RULL(0x80000C6408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_4        , RULL(0x8000106407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P3_4        , RULL(0x8000106408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0          , RULL(0x800001640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0        , RULL(0x800001640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0        , RULL(0x800001640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1          , RULL(0x800005640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1        , RULL(0x800005640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1        , RULL(0x800005640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2          , RULL(0x800009640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2        , RULL(0x800009640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2        , RULL(0x800009640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3          , RULL(0x80000D640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3        , RULL(0x80000D640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3        , RULL(0x80000D640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4          , RULL(0x800011640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4        , RULL(0x800011640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4        , RULL(0x800011640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_0        , RULL(0x800001640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_0        , RULL(0x800001640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_1        , RULL(0x800005640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_1        , RULL(0x800005640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_2        , RULL(0x800009640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_2        , RULL(0x800009640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_3        , RULL(0x80000D640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_3        , RULL(0x80000D640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_4        , RULL(0x800011640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P1_4        , RULL(0x800011640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_0        , RULL(0x800001640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_0        , RULL(0x800001640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_1        , RULL(0x800005640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_1        , RULL(0x800005640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_2        , RULL(0x800009640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_2        , RULL(0x800009640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_3        , RULL(0x80000D640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_3        , RULL(0x80000D640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_4        , RULL(0x800011640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P2_4        , RULL(0x800011640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_0        , RULL(0x8000016407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_0        , RULL(0x8000016408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_1        , RULL(0x8000056407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_1        , RULL(0x8000056408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_2        , RULL(0x8000096407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_2        , RULL(0x8000096408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_3        , RULL(0x80000D6407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_3        , RULL(0x80000D6408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_4        , RULL(0x8000116407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P3_4        , RULL(0x8000116408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0          , RULL(0x800002640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0        , RULL(0x800002640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0        , RULL(0x800002640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1          , RULL(0x800006640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1        , RULL(0x800006640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1        , RULL(0x800006640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2          , RULL(0x80000A640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2        , RULL(0x80000A640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2        , RULL(0x80000A640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3          , RULL(0x80000E640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3        , RULL(0x80000E640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3        , RULL(0x80000E640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4          , RULL(0x800012640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4        , RULL(0x800012640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4        , RULL(0x800012640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_0        , RULL(0x800002640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_0        , RULL(0x800002640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_1        , RULL(0x800006640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_1        , RULL(0x800006640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_2        , RULL(0x80000A640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_2        , RULL(0x80000A640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_3        , RULL(0x80000E640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_3        , RULL(0x80000E640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_4        , RULL(0x800012640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P1_4        , RULL(0x800012640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_0        , RULL(0x800002640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_0        , RULL(0x800002640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_1        , RULL(0x800006640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_1        , RULL(0x800006640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_2        , RULL(0x80000A640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_2        , RULL(0x80000A640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_3        , RULL(0x80000E640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_3        , RULL(0x80000E640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_4        , RULL(0x800012640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P2_4        , RULL(0x800012640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_0        , RULL(0x8000026407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_0        , RULL(0x8000026408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_1        , RULL(0x8000066407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_1        , RULL(0x8000066408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_2        , RULL(0x80000A6407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_2        , RULL(0x80000A6408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_3        , RULL(0x80000E6407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_3        , RULL(0x80000E6408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_4        , RULL(0x8000126407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P3_4        , RULL(0x8000126408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0          , RULL(0x800003640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0        , RULL(0x800003640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0        , RULL(0x800003640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1          , RULL(0x800007640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1        , RULL(0x800007640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1        , RULL(0x800007640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2          , RULL(0x80000B640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2        , RULL(0x80000B640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2        , RULL(0x80000B640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3          , RULL(0x80000F640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3        , RULL(0x80000F640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3        , RULL(0x80000F640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4          , RULL(0x800013640701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4        , RULL(0x800013640701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4        , RULL(0x800013640801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_0        , RULL(0x800003640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_0        , RULL(0x800003640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_1        , RULL(0x800007640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_1        , RULL(0x800007640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_2        , RULL(0x80000B640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_2        , RULL(0x80000B640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_3        , RULL(0x80000F640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_3        , RULL(0x80000F640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_4        , RULL(0x800013640701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P1_4        , RULL(0x800013640801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_0        , RULL(0x800003640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_0        , RULL(0x800003640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_1        , RULL(0x800007640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_1        , RULL(0x800007640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_2        , RULL(0x80000B640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_2        , RULL(0x80000B640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_3        , RULL(0x80000F640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_3        , RULL(0x80000F640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_4        , RULL(0x800013640701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P2_4        , RULL(0x800013640801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_0        , RULL(0x8000036407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_0        , RULL(0x8000036408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_1        , RULL(0x8000076407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_1        , RULL(0x8000076408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_2        , RULL(0x80000B6407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_2        , RULL(0x80000B6408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_3        , RULL(0x80000F6407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_3        , RULL(0x80000F6408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_4        , RULL(0x8000136407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P3_4        , RULL(0x8000136408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0          , RULL(0x800000650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0        , RULL(0x800000650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0        , RULL(0x800000650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1          , RULL(0x800004650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1        , RULL(0x800004650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1        , RULL(0x800004650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2          , RULL(0x800008650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2        , RULL(0x800008650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2        , RULL(0x800008650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3          , RULL(0x80000C650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3        , RULL(0x80000C650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3        , RULL(0x80000C650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4          , RULL(0x800010650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4        , RULL(0x800010650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4        , RULL(0x800010650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_0        , RULL(0x800000650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_0        , RULL(0x800000650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_1        , RULL(0x800004650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_1        , RULL(0x800004650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_2        , RULL(0x800008650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_2        , RULL(0x800008650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_3        , RULL(0x80000C650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_3        , RULL(0x80000C650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_4        , RULL(0x800010650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P1_4        , RULL(0x800010650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_0        , RULL(0x800000650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_0        , RULL(0x800000650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_1        , RULL(0x800004650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_1        , RULL(0x800004650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_2        , RULL(0x800008650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_2        , RULL(0x800008650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_3        , RULL(0x80000C650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_3        , RULL(0x80000C650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_4        , RULL(0x800010650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P2_4        , RULL(0x800010650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_0        , RULL(0x8000006507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_0        , RULL(0x8000006508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_1        , RULL(0x8000046507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_1        , RULL(0x8000046508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_2        , RULL(0x8000086507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_2        , RULL(0x8000086508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_3        , RULL(0x80000C6507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_3        , RULL(0x80000C6508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_4        , RULL(0x8000106507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P3_4        , RULL(0x8000106508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0          , RULL(0x800001650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0        , RULL(0x800001650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0        , RULL(0x800001650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1          , RULL(0x800005650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1        , RULL(0x800005650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1        , RULL(0x800005650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2          , RULL(0x800009650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2        , RULL(0x800009650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2        , RULL(0x800009650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3          , RULL(0x80000D650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3        , RULL(0x80000D650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3        , RULL(0x80000D650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4          , RULL(0x800011650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4        , RULL(0x800011650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4        , RULL(0x800011650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_0        , RULL(0x800001650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_0        , RULL(0x800001650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_1        , RULL(0x800005650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_1        , RULL(0x800005650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_2        , RULL(0x800009650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_2        , RULL(0x800009650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_3        , RULL(0x80000D650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_3        , RULL(0x80000D650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_4        , RULL(0x800011650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P1_4        , RULL(0x800011650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_0        , RULL(0x800001650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_0        , RULL(0x800001650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_1        , RULL(0x800005650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_1        , RULL(0x800005650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_2        , RULL(0x800009650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_2        , RULL(0x800009650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_3        , RULL(0x80000D650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_3        , RULL(0x80000D650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_4        , RULL(0x800011650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P2_4        , RULL(0x800011650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_0        , RULL(0x8000016507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_0        , RULL(0x8000016508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_1        , RULL(0x8000056507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_1        , RULL(0x8000056508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_2        , RULL(0x8000096507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_2        , RULL(0x8000096508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_3        , RULL(0x80000D6507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_3        , RULL(0x80000D6508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_4        , RULL(0x8000116507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P3_4        , RULL(0x8000116508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0          , RULL(0x800002650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0        , RULL(0x800002650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0        , RULL(0x800002650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1          , RULL(0x800006650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1        , RULL(0x800006650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1        , RULL(0x800006650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2          , RULL(0x80000A650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2        , RULL(0x80000A650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2        , RULL(0x80000A650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3          , RULL(0x80000E650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3        , RULL(0x80000E650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3        , RULL(0x80000E650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4          , RULL(0x800012650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4        , RULL(0x800012650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4        , RULL(0x800012650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_0        , RULL(0x800002650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_0        , RULL(0x800002650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_1        , RULL(0x800006650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_1        , RULL(0x800006650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_2        , RULL(0x80000A650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_2        , RULL(0x80000A650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_3        , RULL(0x80000E650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_3        , RULL(0x80000E650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_4        , RULL(0x800012650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P1_4        , RULL(0x800012650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_0        , RULL(0x800002650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_0        , RULL(0x800002650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_1        , RULL(0x800006650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_1        , RULL(0x800006650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_2        , RULL(0x80000A650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_2        , RULL(0x80000A650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_3        , RULL(0x80000E650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_3        , RULL(0x80000E650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_4        , RULL(0x800012650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P2_4        , RULL(0x800012650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_0        , RULL(0x8000026507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_0        , RULL(0x8000026508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_1        , RULL(0x8000066507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_1        , RULL(0x8000066508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_2        , RULL(0x80000A6507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_2        , RULL(0x80000A6508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_3        , RULL(0x80000E6507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_3        , RULL(0x80000E6508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_4        , RULL(0x8000126507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P3_4        , RULL(0x8000126508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0          , RULL(0x800003650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0        , RULL(0x800003650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0        , RULL(0x800003650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1          , RULL(0x800007650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1        , RULL(0x800007650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1        , RULL(0x800007650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2          , RULL(0x80000B650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2        , RULL(0x80000B650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2        , RULL(0x80000B650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3          , RULL(0x80000F650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3        , RULL(0x80000F650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3        , RULL(0x80000F650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4          , RULL(0x800013650701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4        , RULL(0x800013650701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4        , RULL(0x800013650801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_0        , RULL(0x800003650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_0        , RULL(0x800003650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_1        , RULL(0x800007650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_1        , RULL(0x800007650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_2        , RULL(0x80000B650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_2        , RULL(0x80000B650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_3        , RULL(0x80000F650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_3        , RULL(0x80000F650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_4        , RULL(0x800013650701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P1_4        , RULL(0x800013650801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_0        , RULL(0x800003650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_0        , RULL(0x800003650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_1        , RULL(0x800007650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_1        , RULL(0x800007650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_2        , RULL(0x80000B650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_2        , RULL(0x80000B650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_3        , RULL(0x80000F650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_3        , RULL(0x80000F650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_4        , RULL(0x800013650701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P2_4        , RULL(0x800013650801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_0        , RULL(0x8000036507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_0        , RULL(0x8000036508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_1        , RULL(0x8000076507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_1        , RULL(0x8000076508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_2        , RULL(0x80000B6507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_2        , RULL(0x80000B6508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_3        , RULL(0x80000F6507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_3        , RULL(0x80000F6508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_4        , RULL(0x8000136507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P3_4        , RULL(0x8000136508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0          , RULL(0x800000660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0        , RULL(0x800000660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0        , RULL(0x800000660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1          , RULL(0x800004660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1        , RULL(0x800004660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1        , RULL(0x800004660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2          , RULL(0x800008660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2        , RULL(0x800008660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2        , RULL(0x800008660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3          , RULL(0x80000C660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3        , RULL(0x80000C660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3        , RULL(0x80000C660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4          , RULL(0x800010660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4        , RULL(0x800010660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4        , RULL(0x800010660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_0        , RULL(0x800000660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_0        , RULL(0x800000660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_1        , RULL(0x800004660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_1        , RULL(0x800004660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_2        , RULL(0x800008660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_2        , RULL(0x800008660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_3        , RULL(0x80000C660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_3        , RULL(0x80000C660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_4        , RULL(0x800010660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P1_4        , RULL(0x800010660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_0        , RULL(0x800000660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_0        , RULL(0x800000660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_1        , RULL(0x800004660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_1        , RULL(0x800004660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_2        , RULL(0x800008660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_2        , RULL(0x800008660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_3        , RULL(0x80000C660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_3        , RULL(0x80000C660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_4        , RULL(0x800010660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P2_4        , RULL(0x800010660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_0        , RULL(0x8000006607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_0        , RULL(0x8000006608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_1        , RULL(0x8000046607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_1        , RULL(0x8000046608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_2        , RULL(0x8000086607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_2        , RULL(0x8000086608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_3        , RULL(0x80000C6607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_3        , RULL(0x80000C6608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_4        , RULL(0x8000106607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P3_4        , RULL(0x8000106608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0          , RULL(0x800001660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0        , RULL(0x800001660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0        , RULL(0x800001660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1          , RULL(0x800005660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1        , RULL(0x800005660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1        , RULL(0x800005660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2          , RULL(0x800009660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2        , RULL(0x800009660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2        , RULL(0x800009660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3          , RULL(0x80000D660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3        , RULL(0x80000D660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3        , RULL(0x80000D660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4          , RULL(0x800011660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4        , RULL(0x800011660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4        , RULL(0x800011660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_0        , RULL(0x800001660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_0        , RULL(0x800001660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_1        , RULL(0x800005660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_1        , RULL(0x800005660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_2        , RULL(0x800009660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_2        , RULL(0x800009660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_3        , RULL(0x80000D660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_3        , RULL(0x80000D660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_4        , RULL(0x800011660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P1_4        , RULL(0x800011660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_0        , RULL(0x800001660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_0        , RULL(0x800001660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_1        , RULL(0x800005660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_1        , RULL(0x800005660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_2        , RULL(0x800009660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_2        , RULL(0x800009660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_3        , RULL(0x80000D660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_3        , RULL(0x80000D660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_4        , RULL(0x800011660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P2_4        , RULL(0x800011660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_0        , RULL(0x8000016607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_0        , RULL(0x8000016608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_1        , RULL(0x8000056607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_1        , RULL(0x8000056608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_2        , RULL(0x8000096607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_2        , RULL(0x8000096608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_3        , RULL(0x80000D6607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_3        , RULL(0x80000D6608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_4        , RULL(0x8000116607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P3_4        , RULL(0x8000116608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0          , RULL(0x800002660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0        , RULL(0x800002660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0        , RULL(0x800002660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1          , RULL(0x800006660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1        , RULL(0x800006660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1        , RULL(0x800006660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2          , RULL(0x80000A660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2        , RULL(0x80000A660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2        , RULL(0x80000A660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3          , RULL(0x80000E660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3        , RULL(0x80000E660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3        , RULL(0x80000E660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4          , RULL(0x800012660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4        , RULL(0x800012660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4        , RULL(0x800012660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_0        , RULL(0x800002660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_0        , RULL(0x800002660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_1        , RULL(0x800006660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_1        , RULL(0x800006660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_2        , RULL(0x80000A660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_2        , RULL(0x80000A660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_3        , RULL(0x80000E660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_3        , RULL(0x80000E660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_4        , RULL(0x800012660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P1_4        , RULL(0x800012660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_0        , RULL(0x800002660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_0        , RULL(0x800002660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_1        , RULL(0x800006660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_1        , RULL(0x800006660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_2        , RULL(0x80000A660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_2        , RULL(0x80000A660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_3        , RULL(0x80000E660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_3        , RULL(0x80000E660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_4        , RULL(0x800012660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P2_4        , RULL(0x800012660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_0        , RULL(0x8000026607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_0        , RULL(0x8000026608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_1        , RULL(0x8000066607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_1        , RULL(0x8000066608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_2        , RULL(0x80000A6607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_2        , RULL(0x80000A6608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_3        , RULL(0x80000E6607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_3        , RULL(0x80000E6608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_4        , RULL(0x8000126607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P3_4        , RULL(0x8000126608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0          , RULL(0x800003660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0        , RULL(0x800003660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0        , RULL(0x800003660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1          , RULL(0x800007660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1        , RULL(0x800007660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1        , RULL(0x800007660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2          , RULL(0x80000B660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2        , RULL(0x80000B660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2        , RULL(0x80000B660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3          , RULL(0x80000F660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3        , RULL(0x80000F660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3        , RULL(0x80000F660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4          , RULL(0x800013660701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4        , RULL(0x800013660701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4        , RULL(0x800013660801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_0        , RULL(0x800003660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_0        , RULL(0x800003660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_1        , RULL(0x800007660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_1        , RULL(0x800007660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_2        , RULL(0x80000B660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_2        , RULL(0x80000B660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_3        , RULL(0x80000F660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_3        , RULL(0x80000F660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_4        , RULL(0x800013660701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P1_4        , RULL(0x800013660801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_0        , RULL(0x800003660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_0        , RULL(0x800003660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_1        , RULL(0x800007660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_1        , RULL(0x800007660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_2        , RULL(0x80000B660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_2        , RULL(0x80000B660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_3        , RULL(0x80000F660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_3        , RULL(0x80000F660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_4        , RULL(0x800013660701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P2_4        , RULL(0x800013660801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_0        , RULL(0x8000036607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_0        , RULL(0x8000036608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_1        , RULL(0x8000076607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_1        , RULL(0x8000076608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_2        , RULL(0x80000B6607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_2        , RULL(0x80000B6608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_3        , RULL(0x80000F6607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_3        , RULL(0x80000F6608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_4        , RULL(0x8000136607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P3_4        , RULL(0x8000136608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0          , RULL(0x800000670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0        , RULL(0x800000670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0        , RULL(0x800000670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1          , RULL(0x800004670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1        , RULL(0x800004670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1        , RULL(0x800004670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2          , RULL(0x800008670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2        , RULL(0x800008670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2        , RULL(0x800008670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3          , RULL(0x80000C670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3        , RULL(0x80000C670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3        , RULL(0x80000C670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4          , RULL(0x800010670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4        , RULL(0x800010670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4        , RULL(0x800010670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_0        , RULL(0x800000670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_0        , RULL(0x800000670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_1        , RULL(0x800004670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_1        , RULL(0x800004670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_2        , RULL(0x800008670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_2        , RULL(0x800008670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_3        , RULL(0x80000C670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_3        , RULL(0x80000C670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_4        , RULL(0x800010670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P1_4        , RULL(0x800010670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_0        , RULL(0x800000670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_0        , RULL(0x800000670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_1        , RULL(0x800004670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_1        , RULL(0x800004670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_2        , RULL(0x800008670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_2        , RULL(0x800008670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_3        , RULL(0x80000C670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_3        , RULL(0x80000C670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_4        , RULL(0x800010670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P2_4        , RULL(0x800010670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_0        , RULL(0x8000006707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_0        , RULL(0x8000006708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_1        , RULL(0x8000046707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_1        , RULL(0x8000046708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_2        , RULL(0x8000086707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_2        , RULL(0x8000086708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_3        , RULL(0x80000C6707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_3        , RULL(0x80000C6708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_4        , RULL(0x8000106707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P3_4        , RULL(0x8000106708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0          , RULL(0x800001670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0        , RULL(0x800001670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0        , RULL(0x800001670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1          , RULL(0x800005670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1        , RULL(0x800005670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1        , RULL(0x800005670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2          , RULL(0x800009670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2        , RULL(0x800009670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2        , RULL(0x800009670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3          , RULL(0x80000D670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3        , RULL(0x80000D670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3        , RULL(0x80000D670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4          , RULL(0x800011670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4        , RULL(0x800011670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4        , RULL(0x800011670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_0        , RULL(0x800001670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_0        , RULL(0x800001670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_1        , RULL(0x800005670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_1        , RULL(0x800005670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_2        , RULL(0x800009670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_2        , RULL(0x800009670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_3        , RULL(0x80000D670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_3        , RULL(0x80000D670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_4        , RULL(0x800011670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P1_4        , RULL(0x800011670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_0        , RULL(0x800001670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_0        , RULL(0x800001670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_1        , RULL(0x800005670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_1        , RULL(0x800005670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_2        , RULL(0x800009670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_2        , RULL(0x800009670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_3        , RULL(0x80000D670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_3        , RULL(0x80000D670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_4        , RULL(0x800011670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P2_4        , RULL(0x800011670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_0        , RULL(0x8000016707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_0        , RULL(0x8000016708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_1        , RULL(0x8000056707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_1        , RULL(0x8000056708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_2        , RULL(0x8000096707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_2        , RULL(0x8000096708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_3        , RULL(0x80000D6707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_3        , RULL(0x80000D6708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_4        , RULL(0x8000116707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P3_4        , RULL(0x8000116708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0          , RULL(0x800002670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0        , RULL(0x800002670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0        , RULL(0x800002670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1          , RULL(0x800006670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1        , RULL(0x800006670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1        , RULL(0x800006670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2          , RULL(0x80000A670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2        , RULL(0x80000A670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2        , RULL(0x80000A670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3          , RULL(0x80000E670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3        , RULL(0x80000E670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3        , RULL(0x80000E670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4          , RULL(0x800012670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4        , RULL(0x800012670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4        , RULL(0x800012670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_0        , RULL(0x800002670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_0        , RULL(0x800002670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_1        , RULL(0x800006670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_1        , RULL(0x800006670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_2        , RULL(0x80000A670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_2        , RULL(0x80000A670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_3        , RULL(0x80000E670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_3        , RULL(0x80000E670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_4        , RULL(0x800012670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P1_4        , RULL(0x800012670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_0        , RULL(0x800002670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_0        , RULL(0x800002670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_1        , RULL(0x800006670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_1        , RULL(0x800006670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_2        , RULL(0x80000A670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_2        , RULL(0x80000A670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_3        , RULL(0x80000E670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_3        , RULL(0x80000E670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_4        , RULL(0x800012670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P2_4        , RULL(0x800012670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_0        , RULL(0x8000026707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_0        , RULL(0x8000026708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_1        , RULL(0x8000066707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_1        , RULL(0x8000066708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_2        , RULL(0x80000A6707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_2        , RULL(0x80000A6708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_3        , RULL(0x80000E6707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_3        , RULL(0x80000E6708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_4        , RULL(0x8000126707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P3_4        , RULL(0x8000126708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0          , RULL(0x800003670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0        , RULL(0x800003670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0        , RULL(0x800003670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1          , RULL(0x800007670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1        , RULL(0x800007670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1        , RULL(0x800007670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2          , RULL(0x80000B670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2        , RULL(0x80000B670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2        , RULL(0x80000B670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3          , RULL(0x80000F670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3        , RULL(0x80000F670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3        , RULL(0x80000F670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4          , RULL(0x800013670701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4        , RULL(0x800013670701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4        , RULL(0x800013670801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_0        , RULL(0x800003670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_0        , RULL(0x800003670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_1        , RULL(0x800007670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_1        , RULL(0x800007670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_2        , RULL(0x80000B670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_2        , RULL(0x80000B670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_3        , RULL(0x80000F670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_3        , RULL(0x80000F670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_4        , RULL(0x800013670701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P1_4        , RULL(0x800013670801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_0        , RULL(0x800003670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_0        , RULL(0x800003670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_1        , RULL(0x800007670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_1        , RULL(0x800007670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_2        , RULL(0x80000B670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_2        , RULL(0x80000B670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_3        , RULL(0x80000F670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_3        , RULL(0x80000F670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_4        , RULL(0x800013670701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P2_4        , RULL(0x800013670801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_0        , RULL(0x8000036707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_0        , RULL(0x8000036708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_1        , RULL(0x8000076707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_1        , RULL(0x8000076708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_2        , RULL(0x80000B6707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_2        , RULL(0x80000B6708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_3        , RULL(0x80000F6707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_3        , RULL(0x80000F6708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_4        , RULL(0x8000136707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P3_4        , RULL(0x8000136708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0          , RULL(0x800000680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0        , RULL(0x800000680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0        , RULL(0x800000680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1          , RULL(0x800004680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1        , RULL(0x800004680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1        , RULL(0x800004680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2          , RULL(0x800008680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2        , RULL(0x800008680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2        , RULL(0x800008680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3          , RULL(0x80000C680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3        , RULL(0x80000C680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3        , RULL(0x80000C680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4          , RULL(0x800010680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4        , RULL(0x800010680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4        , RULL(0x800010680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_0        , RULL(0x800000680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_0        , RULL(0x800000680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_1        , RULL(0x800004680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_1        , RULL(0x800004680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_2        , RULL(0x800008680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_2        , RULL(0x800008680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_3        , RULL(0x80000C680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_3        , RULL(0x80000C680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_4        , RULL(0x800010680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P1_4        , RULL(0x800010680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_0        , RULL(0x800000680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_0        , RULL(0x800000680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_1        , RULL(0x800004680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_1        , RULL(0x800004680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_2        , RULL(0x800008680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_2        , RULL(0x800008680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_3        , RULL(0x80000C680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_3        , RULL(0x80000C680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_4        , RULL(0x800010680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P2_4        , RULL(0x800010680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_0        , RULL(0x8000006807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_0        , RULL(0x8000006808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_1        , RULL(0x8000046807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_1        , RULL(0x8000046808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_2        , RULL(0x8000086807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_2        , RULL(0x8000086808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_3        , RULL(0x80000C6807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_3        , RULL(0x80000C6808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_4        , RULL(0x8000106807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P3_4        , RULL(0x8000106808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0          , RULL(0x800001680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0        , RULL(0x800001680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0        , RULL(0x800001680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1          , RULL(0x800005680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1        , RULL(0x800005680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1        , RULL(0x800005680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2          , RULL(0x800009680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2        , RULL(0x800009680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2        , RULL(0x800009680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3          , RULL(0x80000D680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3        , RULL(0x80000D680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3        , RULL(0x80000D680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4          , RULL(0x800011680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4        , RULL(0x800011680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4        , RULL(0x800011680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_0        , RULL(0x800001680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_0        , RULL(0x800001680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_1        , RULL(0x800005680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_1        , RULL(0x800005680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_2        , RULL(0x800009680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_2        , RULL(0x800009680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_3        , RULL(0x80000D680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_3        , RULL(0x80000D680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_4        , RULL(0x800011680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P1_4        , RULL(0x800011680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_0        , RULL(0x800001680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_0        , RULL(0x800001680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_1        , RULL(0x800005680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_1        , RULL(0x800005680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_2        , RULL(0x800009680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_2        , RULL(0x800009680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_3        , RULL(0x80000D680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_3        , RULL(0x80000D680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_4        , RULL(0x800011680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P2_4        , RULL(0x800011680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_0        , RULL(0x8000016807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_0        , RULL(0x8000016808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_1        , RULL(0x8000056807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_1        , RULL(0x8000056808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_2        , RULL(0x8000096807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_2        , RULL(0x8000096808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_3        , RULL(0x80000D6807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_3        , RULL(0x80000D6808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_4        , RULL(0x8000116807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P3_4        , RULL(0x8000116808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0          , RULL(0x800002680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0        , RULL(0x800002680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0        , RULL(0x800002680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1          , RULL(0x800006680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1        , RULL(0x800006680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1        , RULL(0x800006680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2          , RULL(0x80000A680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2        , RULL(0x80000A680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2        , RULL(0x80000A680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3          , RULL(0x80000E680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3        , RULL(0x80000E680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3        , RULL(0x80000E680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4          , RULL(0x800012680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4        , RULL(0x800012680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4        , RULL(0x800012680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_0        , RULL(0x800002680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_0        , RULL(0x800002680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_1        , RULL(0x800006680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_1        , RULL(0x800006680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_2        , RULL(0x80000A680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_2        , RULL(0x80000A680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_3        , RULL(0x80000E680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_3        , RULL(0x80000E680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_4        , RULL(0x800012680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P1_4        , RULL(0x800012680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_0        , RULL(0x800002680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_0        , RULL(0x800002680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_1        , RULL(0x800006680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_1        , RULL(0x800006680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_2        , RULL(0x80000A680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_2        , RULL(0x80000A680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_3        , RULL(0x80000E680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_3        , RULL(0x80000E680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_4        , RULL(0x800012680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P2_4        , RULL(0x800012680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_0        , RULL(0x8000026807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_0        , RULL(0x8000026808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_1        , RULL(0x8000066807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_1        , RULL(0x8000066808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_2        , RULL(0x80000A6807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_2        , RULL(0x80000A6808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_3        , RULL(0x80000E6807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_3        , RULL(0x80000E6808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_4        , RULL(0x8000126807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P3_4        , RULL(0x8000126808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0          , RULL(0x800003680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0        , RULL(0x800003680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0        , RULL(0x800003680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1          , RULL(0x800007680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1        , RULL(0x800007680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1        , RULL(0x800007680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2          , RULL(0x80000B680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2        , RULL(0x80000B680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2        , RULL(0x80000B680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3          , RULL(0x80000F680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3        , RULL(0x80000F680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3        , RULL(0x80000F680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4          , RULL(0x800013680701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4        , RULL(0x800013680701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4        , RULL(0x800013680801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_0        , RULL(0x800003680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_0        , RULL(0x800003680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_1        , RULL(0x800007680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_1        , RULL(0x800007680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_2        , RULL(0x80000B680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_2        , RULL(0x80000B680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_3        , RULL(0x80000F680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_3        , RULL(0x80000F680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_4        , RULL(0x800013680701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P1_4        , RULL(0x800013680801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_0        , RULL(0x800003680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_0        , RULL(0x800003680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_1        , RULL(0x800007680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_1        , RULL(0x800007680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_2        , RULL(0x80000B680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_2        , RULL(0x80000B680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_3        , RULL(0x80000F680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_3        , RULL(0x80000F680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_4        , RULL(0x800013680701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P2_4        , RULL(0x800013680801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_0        , RULL(0x8000036807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_0        , RULL(0x8000036808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_1        , RULL(0x8000076807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_1        , RULL(0x8000076808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_2        , RULL(0x80000B6807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_2        , RULL(0x80000B6808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_3        , RULL(0x80000F6807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_3        , RULL(0x80000F6808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_4        , RULL(0x8000136807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P3_4        , RULL(0x8000136808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0          , RULL(0x800000690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0        , RULL(0x800000690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0        , RULL(0x800000690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1          , RULL(0x800004690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1        , RULL(0x800004690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1        , RULL(0x800004690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2          , RULL(0x800008690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2        , RULL(0x800008690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2        , RULL(0x800008690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3          , RULL(0x80000C690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3        , RULL(0x80000C690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3        , RULL(0x80000C690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4          , RULL(0x800010690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4        , RULL(0x800010690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4        , RULL(0x800010690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_0        , RULL(0x800000690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_0        , RULL(0x800000690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_1        , RULL(0x800004690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_1        , RULL(0x800004690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_2        , RULL(0x800008690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_2        , RULL(0x800008690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_3        , RULL(0x80000C690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_3        , RULL(0x80000C690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_4        , RULL(0x800010690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P1_4        , RULL(0x800010690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_0        , RULL(0x800000690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_0        , RULL(0x800000690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_1        , RULL(0x800004690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_1        , RULL(0x800004690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_2        , RULL(0x800008690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_2        , RULL(0x800008690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_3        , RULL(0x80000C690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_3        , RULL(0x80000C690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_4        , RULL(0x800010690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P2_4        , RULL(0x800010690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_0        , RULL(0x8000006907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_0        , RULL(0x8000006908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_1        , RULL(0x8000046907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_1        , RULL(0x8000046908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_2        , RULL(0x8000086907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_2        , RULL(0x8000086908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_3        , RULL(0x80000C6907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_3        , RULL(0x80000C6908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_4        , RULL(0x8000106907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P3_4        , RULL(0x8000106908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0          , RULL(0x800001690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0        , RULL(0x800001690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0        , RULL(0x800001690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1          , RULL(0x800005690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1        , RULL(0x800005690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1        , RULL(0x800005690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2          , RULL(0x800009690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2        , RULL(0x800009690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2        , RULL(0x800009690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3          , RULL(0x80000D690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3        , RULL(0x80000D690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3        , RULL(0x80000D690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4          , RULL(0x800011690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4        , RULL(0x800011690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4        , RULL(0x800011690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_0        , RULL(0x800001690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_0        , RULL(0x800001690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_1        , RULL(0x800005690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_1        , RULL(0x800005690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_2        , RULL(0x800009690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_2        , RULL(0x800009690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_3        , RULL(0x80000D690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_3        , RULL(0x80000D690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_4        , RULL(0x800011690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P1_4        , RULL(0x800011690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_0        , RULL(0x800001690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_0        , RULL(0x800001690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_1        , RULL(0x800005690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_1        , RULL(0x800005690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_2        , RULL(0x800009690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_2        , RULL(0x800009690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_3        , RULL(0x80000D690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_3        , RULL(0x80000D690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_4        , RULL(0x800011690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P2_4        , RULL(0x800011690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_0        , RULL(0x8000016907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_0        , RULL(0x8000016908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_1        , RULL(0x8000056907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_1        , RULL(0x8000056908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_2        , RULL(0x8000096907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_2        , RULL(0x8000096908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_3        , RULL(0x80000D6907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_3        , RULL(0x80000D6908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_4        , RULL(0x8000116907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P3_4        , RULL(0x8000116908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0          , RULL(0x800002690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0        , RULL(0x800002690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0        , RULL(0x800002690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1          , RULL(0x800006690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1        , RULL(0x800006690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1        , RULL(0x800006690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2          , RULL(0x80000A690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2        , RULL(0x80000A690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2        , RULL(0x80000A690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3          , RULL(0x80000E690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3        , RULL(0x80000E690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3        , RULL(0x80000E690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4          , RULL(0x800012690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4        , RULL(0x800012690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4        , RULL(0x800012690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_0        , RULL(0x800002690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_0        , RULL(0x800002690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_1        , RULL(0x800006690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_1        , RULL(0x800006690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_2        , RULL(0x80000A690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_2        , RULL(0x80000A690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_3        , RULL(0x80000E690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_3        , RULL(0x80000E690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_4        , RULL(0x800012690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P1_4        , RULL(0x800012690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_0        , RULL(0x800002690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_0        , RULL(0x800002690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_1        , RULL(0x800006690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_1        , RULL(0x800006690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_2        , RULL(0x80000A690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_2        , RULL(0x80000A690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_3        , RULL(0x80000E690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_3        , RULL(0x80000E690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_4        , RULL(0x800012690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P2_4        , RULL(0x800012690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_0        , RULL(0x8000026907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_0        , RULL(0x8000026908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_1        , RULL(0x8000066907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_1        , RULL(0x8000066908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_2        , RULL(0x80000A6907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_2        , RULL(0x80000A6908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_3        , RULL(0x80000E6907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_3        , RULL(0x80000E6908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_4        , RULL(0x8000126907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P3_4        , RULL(0x8000126908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0          , RULL(0x800003690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0        , RULL(0x800003690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0        , RULL(0x800003690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1          , RULL(0x800007690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1        , RULL(0x800007690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1        , RULL(0x800007690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2          , RULL(0x80000B690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2        , RULL(0x80000B690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2        , RULL(0x80000B690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3          , RULL(0x80000F690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3        , RULL(0x80000F690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3        , RULL(0x80000F690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4          , RULL(0x800013690701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4        , RULL(0x800013690701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4        , RULL(0x800013690801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_0        , RULL(0x800003690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_0        , RULL(0x800003690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_1        , RULL(0x800007690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_1        , RULL(0x800007690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_2        , RULL(0x80000B690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_2        , RULL(0x80000B690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_3        , RULL(0x80000F690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_3        , RULL(0x80000F690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_4        , RULL(0x800013690701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P1_4        , RULL(0x800013690801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_0        , RULL(0x800003690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_0        , RULL(0x800003690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_1        , RULL(0x800007690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_1        , RULL(0x800007690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_2        , RULL(0x80000B690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_2        , RULL(0x80000B690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_3        , RULL(0x80000F690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_3        , RULL(0x80000F690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_4        , RULL(0x800013690701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P2_4        , RULL(0x800013690801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_0        , RULL(0x8000036907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_0        , RULL(0x8000036908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_1        , RULL(0x8000076907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_1        , RULL(0x8000076908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_2        , RULL(0x80000B6907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_2        , RULL(0x80000B6908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_3        , RULL(0x80000F6907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_3        , RULL(0x80000F6908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_4        , RULL(0x8000136907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P3_4        , RULL(0x8000136908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0             , RULL(0x800000700701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0           , RULL(0x800000700701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0           , RULL(0x800000700801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1             , RULL(0x800004700701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1           , RULL(0x800004700701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1           , RULL(0x800004700801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2             , RULL(0x800008700701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2           , RULL(0x800008700701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2           , RULL(0x800008700801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3             , RULL(0x80000C700701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3           , RULL(0x80000C700701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3           , RULL(0x80000C700801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4             , RULL(0x800010700701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4           , RULL(0x800010700701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4           , RULL(0x800010700801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_0           , RULL(0x800000700701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_0           , RULL(0x800000700801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_1           , RULL(0x800004700701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_1           , RULL(0x800004700801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_2           , RULL(0x800008700701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_2           , RULL(0x800008700801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_3           , RULL(0x80000C700701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_3           , RULL(0x80000C700801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_4           , RULL(0x800010700701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE0_P1_4           , RULL(0x800010700801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_0           , RULL(0x800000700701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_0           , RULL(0x800000700801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_1           , RULL(0x800004700701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_1           , RULL(0x800004700801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_2           , RULL(0x800008700701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_2           , RULL(0x800008700801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_3           , RULL(0x80000C700701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_3           , RULL(0x80000C700801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_4           , RULL(0x800010700701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE0_P2_4           , RULL(0x800010700801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_0           , RULL(0x8000007007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_0           , RULL(0x8000007008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_1           , RULL(0x8000047007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_1           , RULL(0x8000047008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_2           , RULL(0x8000087007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_2           , RULL(0x8000087008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_3           , RULL(0x80000C7007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_3           , RULL(0x80000C7008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_4           , RULL(0x8000107007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE0_P3_4           , RULL(0x8000107008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0             , RULL(0x800000710701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0           , RULL(0x800000710701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0           , RULL(0x800000710801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1             , RULL(0x800004710701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1           , RULL(0x800004710701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1           , RULL(0x800004710801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2             , RULL(0x800008710701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2           , RULL(0x800008710701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2           , RULL(0x800008710801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3             , RULL(0x80000C710701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3           , RULL(0x80000C710701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3           , RULL(0x80000C710801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4             , RULL(0x800010710701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4           , RULL(0x800010710701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4           , RULL(0x800010710801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_0           , RULL(0x800000710701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_0           , RULL(0x800000710801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_1           , RULL(0x800004710701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_1           , RULL(0x800004710801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_2           , RULL(0x800008710701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_2           , RULL(0x800008710801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_3           , RULL(0x80000C710701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_3           , RULL(0x80000C710801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_4           , RULL(0x800010710701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_READ_TIMING_REFERENCE1_P1_4           , RULL(0x800010710801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_0           , RULL(0x800000710701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_0           , RULL(0x800000710801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_1           , RULL(0x800004710701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_1           , RULL(0x800004710801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_2           , RULL(0x800008710701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_2           , RULL(0x800008710801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_3           , RULL(0x80000C710701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_3           , RULL(0x80000C710801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_4           , RULL(0x800010710701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_READ_TIMING_REFERENCE1_P2_4           , RULL(0x800010710801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_0           , RULL(0x8000007107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_0           , RULL(0x8000007108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_1           , RULL(0x8000047107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_1           , RULL(0x8000047108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_2           , RULL(0x8000087107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_2           , RULL(0x8000087108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_3           , RULL(0x80000C7107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_3           , RULL(0x80000C7108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_4           , RULL(0x8000107107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_READ_TIMING_REFERENCE1_P3_4           , RULL(0x8000107108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0                        , RULL(0x800000060701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RX_PEAK_AMP_P0_0                      , RULL(0x800000060701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RX_PEAK_AMP_P0_0                      , RULL(0x800000060801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1                        , RULL(0x800004060701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RX_PEAK_AMP_P0_1                      , RULL(0x800004060701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RX_PEAK_AMP_P0_1                      , RULL(0x800004060801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2                        , RULL(0x800008060701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RX_PEAK_AMP_P0_2                      , RULL(0x800008060701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RX_PEAK_AMP_P0_2                      , RULL(0x800008060801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3                        , RULL(0x80000C060701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RX_PEAK_AMP_P0_3                      , RULL(0x80000C060701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RX_PEAK_AMP_P0_3                      , RULL(0x80000C060801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4                        , RULL(0x800010060701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_RX_PEAK_AMP_P0_4                      , RULL(0x800010060701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_RX_PEAK_AMP_P0_4                      , RULL(0x800010060801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RX_PEAK_AMP_P1_0                      , RULL(0x800000060701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RX_PEAK_AMP_P1_0                      , RULL(0x800000060801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RX_PEAK_AMP_P1_1                      , RULL(0x800004060701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RX_PEAK_AMP_P1_1                      , RULL(0x800004060801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RX_PEAK_AMP_P1_2                      , RULL(0x800008060701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RX_PEAK_AMP_P1_2                      , RULL(0x800008060801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RX_PEAK_AMP_P1_3                      , RULL(0x80000C060701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RX_PEAK_AMP_P1_3                      , RULL(0x80000C060801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_RX_PEAK_AMP_P1_4                      , RULL(0x800010060701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_RX_PEAK_AMP_P1_4                      , RULL(0x800010060801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RX_PEAK_AMP_P2_0                      , RULL(0x800000060701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RX_PEAK_AMP_P2_0                      , RULL(0x800000060801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RX_PEAK_AMP_P2_1                      , RULL(0x800004060701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RX_PEAK_AMP_P2_1                      , RULL(0x800004060801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RX_PEAK_AMP_P2_2                      , RULL(0x800008060701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RX_PEAK_AMP_P2_2                      , RULL(0x800008060801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RX_PEAK_AMP_P2_3                      , RULL(0x80000C060701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RX_PEAK_AMP_P2_3                      , RULL(0x80000C060801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_RX_PEAK_AMP_P2_4                      , RULL(0x800010060701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_RX_PEAK_AMP_P2_4                      , RULL(0x800010060801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RX_PEAK_AMP_P3_0                      , RULL(0x8000000607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RX_PEAK_AMP_P3_0                      , RULL(0x8000000608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RX_PEAK_AMP_P3_1                      , RULL(0x8000040607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RX_PEAK_AMP_P3_1                      , RULL(0x8000040608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RX_PEAK_AMP_P3_2                      , RULL(0x8000080607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RX_PEAK_AMP_P3_2                      , RULL(0x8000080608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RX_PEAK_AMP_P3_3                      , RULL(0x80000C0607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RX_PEAK_AMP_P3_3                      , RULL(0x80000C0608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_RX_PEAK_AMP_P3_4                      , RULL(0x8000100607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_RX_PEAK_AMP_P3_4                      , RULL(0x8000100608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0                         , RULL(0x800000070701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_SYSCLK_PR0_P0_0                       , RULL(0x800000070701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_SYSCLK_PR0_P0_0                       , RULL(0x800000070801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1                         , RULL(0x800004070701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_SYSCLK_PR0_P0_1                       , RULL(0x800004070701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_SYSCLK_PR0_P0_1                       , RULL(0x800004070801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2                         , RULL(0x800008070701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_SYSCLK_PR0_P0_2                       , RULL(0x800008070701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_SYSCLK_PR0_P0_2                       , RULL(0x800008070801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3                         , RULL(0x80000C070701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_SYSCLK_PR0_P0_3                       , RULL(0x80000C070701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_SYSCLK_PR0_P0_3                       , RULL(0x80000C070801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4                         , RULL(0x800010070701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_SYSCLK_PR0_P0_4                       , RULL(0x800010070701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_SYSCLK_PR0_P0_4                       , RULL(0x800010070801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_SYSCLK_PR0_P1_0                       , RULL(0x800000070701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_SYSCLK_PR0_P1_0                       , RULL(0x800000070801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_SYSCLK_PR0_P1_1                       , RULL(0x800004070701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_SYSCLK_PR0_P1_1                       , RULL(0x800004070801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_SYSCLK_PR0_P1_2                       , RULL(0x800008070701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_SYSCLK_PR0_P1_2                       , RULL(0x800008070801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_SYSCLK_PR0_P1_3                       , RULL(0x80000C070701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_SYSCLK_PR0_P1_3                       , RULL(0x80000C070801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_SYSCLK_PR0_P1_4                       , RULL(0x800010070701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_SYSCLK_PR0_P1_4                       , RULL(0x800010070801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_SYSCLK_PR0_P2_0                       , RULL(0x800000070701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_SYSCLK_PR0_P2_0                       , RULL(0x800000070801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_SYSCLK_PR0_P2_1                       , RULL(0x800004070701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_SYSCLK_PR0_P2_1                       , RULL(0x800004070801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_SYSCLK_PR0_P2_2                       , RULL(0x800008070701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_SYSCLK_PR0_P2_2                       , RULL(0x800008070801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_SYSCLK_PR0_P2_3                       , RULL(0x80000C070701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_SYSCLK_PR0_P2_3                       , RULL(0x80000C070801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_SYSCLK_PR0_P2_4                       , RULL(0x800010070701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_SYSCLK_PR0_P2_4                       , RULL(0x800010070801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_SYSCLK_PR0_P3_0                       , RULL(0x8000000707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_SYSCLK_PR0_P3_0                       , RULL(0x8000000708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_SYSCLK_PR0_P3_1                       , RULL(0x8000040707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_SYSCLK_PR0_P3_1                       , RULL(0x8000040708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_SYSCLK_PR0_P3_2                       , RULL(0x8000080707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_SYSCLK_PR0_P3_2                       , RULL(0x8000080708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_SYSCLK_PR0_P3_3                       , RULL(0x80000C0707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_SYSCLK_PR0_P3_3                       , RULL(0x80000C0708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_SYSCLK_PR0_P3_4                       , RULL(0x8000100707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_SYSCLK_PR0_P3_4                       , RULL(0x8000100708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0                         , RULL(0x8000007F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_SYSCLK_PR1_P0_0                       , RULL(0x8000007F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_SYSCLK_PR1_P0_0                       , RULL(0x8000007F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1                         , RULL(0x8000047F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_SYSCLK_PR1_P0_1                       , RULL(0x8000047F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_SYSCLK_PR1_P0_1                       , RULL(0x8000047F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2                         , RULL(0x8000087F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_SYSCLK_PR1_P0_2                       , RULL(0x8000087F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_SYSCLK_PR1_P0_2                       , RULL(0x8000087F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3                         , RULL(0x80000C7F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_SYSCLK_PR1_P0_3                       , RULL(0x80000C7F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_SYSCLK_PR1_P0_3                       , RULL(0x80000C7F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4                         , RULL(0x8000107F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_SYSCLK_PR1_P0_4                       , RULL(0x8000107F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_SYSCLK_PR1_P0_4                       , RULL(0x8000107F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_SYSCLK_PR1_P1_0                       , RULL(0x8000007F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_SYSCLK_PR1_P1_0                       , RULL(0x8000007F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_SYSCLK_PR1_P1_1                       , RULL(0x8000047F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_SYSCLK_PR1_P1_1                       , RULL(0x8000047F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_SYSCLK_PR1_P1_2                       , RULL(0x8000087F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_SYSCLK_PR1_P1_2                       , RULL(0x8000087F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_SYSCLK_PR1_P1_3                       , RULL(0x80000C7F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_SYSCLK_PR1_P1_3                       , RULL(0x80000C7F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_SYSCLK_PR1_P1_4                       , RULL(0x8000107F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_SYSCLK_PR1_P1_4                       , RULL(0x8000107F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_SYSCLK_PR1_P2_0                       , RULL(0x8000007F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_SYSCLK_PR1_P2_0                       , RULL(0x8000007F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_SYSCLK_PR1_P2_1                       , RULL(0x8000047F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_SYSCLK_PR1_P2_1                       , RULL(0x8000047F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_SYSCLK_PR1_P2_2                       , RULL(0x8000087F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_SYSCLK_PR1_P2_2                       , RULL(0x8000087F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_SYSCLK_PR1_P2_3                       , RULL(0x80000C7F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_SYSCLK_PR1_P2_3                       , RULL(0x80000C7F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_SYSCLK_PR1_P2_4                       , RULL(0x8000107F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_SYSCLK_PR1_P2_4                       , RULL(0x8000107F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_SYSCLK_PR1_P3_0                       , RULL(0x8000007F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_SYSCLK_PR1_P3_0                       , RULL(0x8000007F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_SYSCLK_PR1_P3_1                       , RULL(0x8000047F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_SYSCLK_PR1_P3_1                       , RULL(0x8000047F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_SYSCLK_PR1_P3_2                       , RULL(0x8000087F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_SYSCLK_PR1_P3_2                       , RULL(0x8000087F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_SYSCLK_PR1_P3_3                       , RULL(0x80000C7F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_SYSCLK_PR1_P3_3                       , RULL(0x80000C7F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_SYSCLK_PR1_P3_4                       , RULL(0x8000107F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_SYSCLK_PR1_P3_4                       , RULL(0x8000107F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0                    , RULL(0x800000730701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0                  , RULL(0x800000730701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0                  , RULL(0x800000730801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1                    , RULL(0x800004730701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1                  , RULL(0x800004730701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1                  , RULL(0x800004730801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2                    , RULL(0x800008730701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2                  , RULL(0x800008730701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2                  , RULL(0x800008730801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3                    , RULL(0x80000C730701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3                  , RULL(0x80000C730701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3                  , RULL(0x80000C730801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4                    , RULL(0x800010730701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4                  , RULL(0x800010730701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4                  , RULL(0x800010730801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_0                  , RULL(0x800000730701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_0                  , RULL(0x800000730801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_1                  , RULL(0x800004730701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_1                  , RULL(0x800004730801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_2                  , RULL(0x800008730701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_2                  , RULL(0x800008730801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_3                  , RULL(0x80000C730701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_3                  , RULL(0x80000C730801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_4                  , RULL(0x800010730701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_SYSCLK_PR_VALUE_P1_4                  , RULL(0x800010730801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_0                  , RULL(0x800000730701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_0                  , RULL(0x800000730801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_1                  , RULL(0x800004730701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_1                  , RULL(0x800004730801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_2                  , RULL(0x800008730701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_2                  , RULL(0x800008730801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_3                  , RULL(0x80000C730701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_3                  , RULL(0x80000C730801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_4                  , RULL(0x800010730701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_SYSCLK_PR_VALUE_P2_4                  , RULL(0x800010730801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_0                  , RULL(0x8000007307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_0                  , RULL(0x8000007308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_1                  , RULL(0x8000047307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_1                  , RULL(0x8000047308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_2                  , RULL(0x8000087307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_2                  , RULL(0x8000087308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_3                  , RULL(0x80000C7307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_3                  , RULL(0x80000C7308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_4                  , RULL(0x8000107307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_SYSCLK_PR_VALUE_P3_4                  , RULL(0x8000107308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0                       , RULL(0x800000050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP0_P0_0                     , RULL(0x800000050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP0_P0_0                     , RULL(0x800000050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1                       , RULL(0x800004050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP0_P0_1                     , RULL(0x800004050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP0_P0_1                     , RULL(0x800004050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2                       , RULL(0x800008050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP0_P0_2                     , RULL(0x800008050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP0_P0_2                     , RULL(0x800008050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3                       , RULL(0x80000C050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP0_P0_3                     , RULL(0x80000C050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP0_P0_3                     , RULL(0x80000C050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4                       , RULL(0x800010050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP0_P0_4                     , RULL(0x800010050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP0_P0_4                     , RULL(0x800010050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP0_P1_0                     , RULL(0x800000050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP0_P1_0                     , RULL(0x800000050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP0_P1_1                     , RULL(0x800004050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP0_P1_1                     , RULL(0x800004050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP0_P1_2                     , RULL(0x800008050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP0_P1_2                     , RULL(0x800008050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP0_P1_3                     , RULL(0x80000C050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP0_P1_3                     , RULL(0x80000C050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP0_P1_4                     , RULL(0x800010050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP0_P1_4                     , RULL(0x800010050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP0_P2_0                     , RULL(0x800000050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP0_P2_0                     , RULL(0x800000050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP0_P2_1                     , RULL(0x800004050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP0_P2_1                     , RULL(0x800004050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP0_P2_2                     , RULL(0x800008050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP0_P2_2                     , RULL(0x800008050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP0_P2_3                     , RULL(0x80000C050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP0_P2_3                     , RULL(0x80000C050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP0_P2_4                     , RULL(0x800010050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP0_P2_4                     , RULL(0x800010050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP0_P3_0                     , RULL(0x8000000507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP0_P3_0                     , RULL(0x8000000508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP0_P3_1                     , RULL(0x8000040507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP0_P3_1                     , RULL(0x8000040508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP0_P3_2                     , RULL(0x8000080507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP0_P3_2                     , RULL(0x8000080508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP0_P3_3                     , RULL(0x80000C0507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP0_P3_3                     , RULL(0x80000C0508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP0_P3_4                     , RULL(0x8000100507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP0_P3_4                     , RULL(0x8000100508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0                       , RULL(0x800001050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP1_P0_0                     , RULL(0x800001050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP1_P0_0                     , RULL(0x800001050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1                       , RULL(0x800005050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP1_P0_1                     , RULL(0x800005050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP1_P0_1                     , RULL(0x800005050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2                       , RULL(0x800009050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP1_P0_2                     , RULL(0x800009050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP1_P0_2                     , RULL(0x800009050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3                       , RULL(0x80000D050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP1_P0_3                     , RULL(0x80000D050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP1_P0_3                     , RULL(0x80000D050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4                       , RULL(0x800011050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP1_P0_4                     , RULL(0x800011050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP1_P0_4                     , RULL(0x800011050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP1_P1_0                     , RULL(0x800001050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP1_P1_0                     , RULL(0x800001050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP1_P1_1                     , RULL(0x800005050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP1_P1_1                     , RULL(0x800005050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP1_P1_2                     , RULL(0x800009050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP1_P1_2                     , RULL(0x800009050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP1_P1_3                     , RULL(0x80000D050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP1_P1_3                     , RULL(0x80000D050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP1_P1_4                     , RULL(0x800011050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP1_P1_4                     , RULL(0x800011050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP1_P2_0                     , RULL(0x800001050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP1_P2_0                     , RULL(0x800001050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP1_P2_1                     , RULL(0x800005050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP1_P2_1                     , RULL(0x800005050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP1_P2_2                     , RULL(0x800009050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP1_P2_2                     , RULL(0x800009050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP1_P2_3                     , RULL(0x80000D050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP1_P2_3                     , RULL(0x80000D050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP1_P2_4                     , RULL(0x800011050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP1_P2_4                     , RULL(0x800011050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP1_P3_0                     , RULL(0x8000010507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP1_P3_0                     , RULL(0x8000010508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP1_P3_1                     , RULL(0x8000050507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP1_P3_1                     , RULL(0x8000050508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP1_P3_2                     , RULL(0x8000090507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP1_P3_2                     , RULL(0x8000090508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP1_P3_3                     , RULL(0x80000D0507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP1_P3_3                     , RULL(0x80000D0508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP1_P3_4                     , RULL(0x8000110507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP1_P3_4                     , RULL(0x8000110508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0                       , RULL(0x800002050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP2_P0_0                     , RULL(0x800002050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP2_P0_0                     , RULL(0x800002050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1                       , RULL(0x800006050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP2_P0_1                     , RULL(0x800006050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP2_P0_1                     , RULL(0x800006050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2                       , RULL(0x80000A050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP2_P0_2                     , RULL(0x80000A050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP2_P0_2                     , RULL(0x80000A050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3                       , RULL(0x80000E050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP2_P0_3                     , RULL(0x80000E050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP2_P0_3                     , RULL(0x80000E050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4                       , RULL(0x800012050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP2_P0_4                     , RULL(0x800012050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP2_P0_4                     , RULL(0x800012050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP2_P1_0                     , RULL(0x800002050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP2_P1_0                     , RULL(0x800002050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP2_P1_1                     , RULL(0x800006050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP2_P1_1                     , RULL(0x800006050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP2_P1_2                     , RULL(0x80000A050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP2_P1_2                     , RULL(0x80000A050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP2_P1_3                     , RULL(0x80000E050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP2_P1_3                     , RULL(0x80000E050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP2_P1_4                     , RULL(0x800012050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP2_P1_4                     , RULL(0x800012050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP2_P2_0                     , RULL(0x800002050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP2_P2_0                     , RULL(0x800002050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP2_P2_1                     , RULL(0x800006050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP2_P2_1                     , RULL(0x800006050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP2_P2_2                     , RULL(0x80000A050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP2_P2_2                     , RULL(0x80000A050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP2_P2_3                     , RULL(0x80000E050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP2_P2_3                     , RULL(0x80000E050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP2_P2_4                     , RULL(0x800012050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP2_P2_4                     , RULL(0x800012050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP2_P3_0                     , RULL(0x8000020507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP2_P3_0                     , RULL(0x8000020508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP2_P3_1                     , RULL(0x8000060507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP2_P3_1                     , RULL(0x8000060508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP2_P3_2                     , RULL(0x80000A0507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP2_P3_2                     , RULL(0x80000A0508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP2_P3_3                     , RULL(0x80000E0507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP2_P3_3                     , RULL(0x80000E0508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP2_P3_4                     , RULL(0x8000120507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP2_P3_4                     , RULL(0x8000120508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0                       , RULL(0x800003050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP3_P0_0                     , RULL(0x800003050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP3_P0_0                     , RULL(0x800003050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1                       , RULL(0x800007050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP3_P0_1                     , RULL(0x800007050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP3_P0_1                     , RULL(0x800007050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2                       , RULL(0x80000B050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP3_P0_2                     , RULL(0x80000B050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP3_P0_2                     , RULL(0x80000B050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3                       , RULL(0x80000F050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP3_P0_3                     , RULL(0x80000F050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP3_P0_3                     , RULL(0x80000F050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4                       , RULL(0x800013050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_EN_RP3_P0_4                     , RULL(0x800013050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_EN_RP3_P0_4                     , RULL(0x800013050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP3_P1_0                     , RULL(0x800003050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP3_P1_0                     , RULL(0x800003050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP3_P1_1                     , RULL(0x800007050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP3_P1_1                     , RULL(0x800007050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP3_P1_2                     , RULL(0x80000B050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP3_P1_2                     , RULL(0x80000B050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP3_P1_3                     , RULL(0x80000F050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP3_P1_3                     , RULL(0x80000F050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_EN_RP3_P1_4                     , RULL(0x800013050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_EN_RP3_P1_4                     , RULL(0x800013050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP3_P2_0                     , RULL(0x800003050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP3_P2_0                     , RULL(0x800003050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP3_P2_1                     , RULL(0x800007050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP3_P2_1                     , RULL(0x800007050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP3_P2_2                     , RULL(0x80000B050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP3_P2_2                     , RULL(0x80000B050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP3_P2_3                     , RULL(0x80000F050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP3_P2_3                     , RULL(0x80000F050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_EN_RP3_P2_4                     , RULL(0x800013050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_EN_RP3_P2_4                     , RULL(0x800013050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP3_P3_0                     , RULL(0x8000030507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP3_P3_0                     , RULL(0x8000030508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP3_P3_1                     , RULL(0x8000070507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP3_P3_1                     , RULL(0x8000070508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP3_P3_2                     , RULL(0x80000B0507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP3_P3_2                     , RULL(0x80000B0508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP3_P3_3                     , RULL(0x80000F0507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP3_P3_3                     , RULL(0x80000F0508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_EN_RP3_P3_4                     , RULL(0x8000130507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_EN_RP3_P3_4                     , RULL(0x8000130508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_PR_P0_0                           , RULL(0x800000740701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_PR_P0_0                         , RULL(0x800000740701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_PR_P0_0                         , RULL(0x800000740801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_PR_P0_1                           , RULL(0x800004740701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_PR_P0_1                         , RULL(0x800004740701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_PR_P0_1                         , RULL(0x800004740801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_PR_P0_2                           , RULL(0x800008740701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_PR_P0_2                         , RULL(0x800008740701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_PR_P0_2                         , RULL(0x800008740801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_PR_P0_3                           , RULL(0x80000C740701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_PR_P0_3                         , RULL(0x80000C740701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_PR_P0_3                         , RULL(0x80000C740801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WRCLK_PR_P0_4                           , RULL(0x800010740701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WRCLK_PR_P0_4                         , RULL(0x800010740701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WRCLK_PR_P0_4                         , RULL(0x800010740801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_PR_P1_0                         , RULL(0x800000740701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_PR_P1_0                         , RULL(0x800000740801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_PR_P1_1                         , RULL(0x800004740701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_PR_P1_1                         , RULL(0x800004740801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_PR_P1_2                         , RULL(0x800008740701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_PR_P1_2                         , RULL(0x800008740801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_PR_P1_3                         , RULL(0x80000C740701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_PR_P1_3                         , RULL(0x80000C740801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WRCLK_PR_P1_4                         , RULL(0x800010740701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WRCLK_PR_P1_4                         , RULL(0x800010740801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_PR_P2_0                         , RULL(0x800000740701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_PR_P2_0                         , RULL(0x800000740801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_PR_P2_1                         , RULL(0x800004740701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_PR_P2_1                         , RULL(0x800004740801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_PR_P2_2                         , RULL(0x800008740701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_PR_P2_2                         , RULL(0x800008740801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_PR_P2_3                         , RULL(0x80000C740701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_PR_P2_3                         , RULL(0x80000C740801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WRCLK_PR_P2_4                         , RULL(0x800010740701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WRCLK_PR_P2_4                         , RULL(0x800010740801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_PR_P3_0                         , RULL(0x8000007407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_PR_P3_0                         , RULL(0x8000007408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_PR_P3_1                         , RULL(0x8000047407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_PR_P3_1                         , RULL(0x8000047408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_PR_P3_2                         , RULL(0x8000087407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_PR_P3_2                         , RULL(0x8000087408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_PR_P3_3                         , RULL(0x80000C7407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_PR_P3_3                         , RULL(0x80000C7408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WRCLK_PR_P3_4                         , RULL(0x8000107407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WRCLK_PR_P3_4                         , RULL(0x8000107408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0                    , RULL(0x800000180701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0                  , RULL(0x800000180701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0                  , RULL(0x800000180801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1                    , RULL(0x800004180701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1                  , RULL(0x800004180701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1                  , RULL(0x800004180801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2                    , RULL(0x800008180701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2                  , RULL(0x800008180701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2                  , RULL(0x800008180801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3                    , RULL(0x80000C180701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3                  , RULL(0x80000C180701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3                  , RULL(0x80000C180801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4                    , RULL(0x800010180701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4                  , RULL(0x800010180701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4                  , RULL(0x800010180801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_CNTR_STATUS0_P1_0                  , RULL(0x800000180701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_CNTR_STATUS0_P1_0                  , RULL(0x800000180801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_CNTR_STATUS0_P1_1                  , RULL(0x800004180701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_CNTR_STATUS0_P1_1                  , RULL(0x800004180801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_CNTR_STATUS0_P1_2                  , RULL(0x800008180701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_CNTR_STATUS0_P1_2                  , RULL(0x800008180801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_CNTR_STATUS0_P1_3                  , RULL(0x80000C180701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_CNTR_STATUS0_P1_3                  , RULL(0x80000C180801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_CNTR_STATUS0_P1_4                  , RULL(0x800010180701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_CNTR_STATUS0_P1_4                  , RULL(0x800010180801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_CNTR_STATUS0_P2_0                  , RULL(0x800000180701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_CNTR_STATUS0_P2_0                  , RULL(0x800000180801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_CNTR_STATUS0_P2_1                  , RULL(0x800004180701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_CNTR_STATUS0_P2_1                  , RULL(0x800004180801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_CNTR_STATUS0_P2_2                  , RULL(0x800008180701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_CNTR_STATUS0_P2_2                  , RULL(0x800008180801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_CNTR_STATUS0_P2_3                  , RULL(0x80000C180701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_CNTR_STATUS0_P2_3                  , RULL(0x80000C180801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_CNTR_STATUS0_P2_4                  , RULL(0x800010180701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_CNTR_STATUS0_P2_4                  , RULL(0x800010180801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_CNTR_STATUS0_P3_0                  , RULL(0x8000001807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_CNTR_STATUS0_P3_0                  , RULL(0x8000001808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_CNTR_STATUS0_P3_1                  , RULL(0x8000041807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_CNTR_STATUS0_P3_1                  , RULL(0x8000041808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_CNTR_STATUS0_P3_2                  , RULL(0x8000081807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_CNTR_STATUS0_P3_2                  , RULL(0x8000081808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_CNTR_STATUS0_P3_3                  , RULL(0x80000C1807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_CNTR_STATUS0_P3_3                  , RULL(0x80000C1808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_CNTR_STATUS0_P3_4                  , RULL(0x8000101807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_CNTR_STATUS0_P3_4                  , RULL(0x8000101808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0                    , RULL(0x800000190701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0                  , RULL(0x800000190701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0                  , RULL(0x800000190801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1                    , RULL(0x800004190701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1                  , RULL(0x800004190701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1                  , RULL(0x800004190801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2                    , RULL(0x800008190701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2                  , RULL(0x800008190701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2                  , RULL(0x800008190801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3                    , RULL(0x80000C190701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3                  , RULL(0x80000C190701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3                  , RULL(0x80000C190801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4                    , RULL(0x800010190701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4                  , RULL(0x800010190701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4                  , RULL(0x800010190801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_CNTR_STATUS1_P1_0                  , RULL(0x800000190701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_CNTR_STATUS1_P1_0                  , RULL(0x800000190801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_CNTR_STATUS1_P1_1                  , RULL(0x800004190701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_CNTR_STATUS1_P1_1                  , RULL(0x800004190801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_CNTR_STATUS1_P1_2                  , RULL(0x800008190701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_CNTR_STATUS1_P1_2                  , RULL(0x800008190801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_CNTR_STATUS1_P1_3                  , RULL(0x80000C190701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_CNTR_STATUS1_P1_3                  , RULL(0x80000C190801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_CNTR_STATUS1_P1_4                  , RULL(0x800010190701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_CNTR_STATUS1_P1_4                  , RULL(0x800010190801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_CNTR_STATUS1_P2_0                  , RULL(0x800000190701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_CNTR_STATUS1_P2_0                  , RULL(0x800000190801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_CNTR_STATUS1_P2_1                  , RULL(0x800004190701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_CNTR_STATUS1_P2_1                  , RULL(0x800004190801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_CNTR_STATUS1_P2_2                  , RULL(0x800008190701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_CNTR_STATUS1_P2_2                  , RULL(0x800008190801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_CNTR_STATUS1_P2_3                  , RULL(0x80000C190701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_CNTR_STATUS1_P2_3                  , RULL(0x80000C190801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_CNTR_STATUS1_P2_4                  , RULL(0x800010190701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_CNTR_STATUS1_P2_4                  , RULL(0x800010190801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_CNTR_STATUS1_P3_0                  , RULL(0x8000001907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_CNTR_STATUS1_P3_0                  , RULL(0x8000001908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_CNTR_STATUS1_P3_1                  , RULL(0x8000041907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_CNTR_STATUS1_P3_1                  , RULL(0x8000041908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_CNTR_STATUS1_P3_2                  , RULL(0x8000081907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_CNTR_STATUS1_P3_2                  , RULL(0x8000081908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_CNTR_STATUS1_P3_3                  , RULL(0x80000C1907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_CNTR_STATUS1_P3_3                  , RULL(0x80000C1908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_CNTR_STATUS1_P3_4                  , RULL(0x8000101907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_CNTR_STATUS1_P3_4                  , RULL(0x8000101908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0                    , RULL(0x8000001A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0                  , RULL(0x8000001A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0                  , RULL(0x8000001A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1                    , RULL(0x8000041A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1                  , RULL(0x8000041A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1                  , RULL(0x8000041A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2                    , RULL(0x8000081A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2                  , RULL(0x8000081A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2                  , RULL(0x8000081A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3                    , RULL(0x80000C1A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3                  , RULL(0x80000C1A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3                  , RULL(0x80000C1A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4                    , RULL(0x8000101A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4                  , RULL(0x8000101A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4                  , RULL(0x8000101A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_CNTR_STATUS2_P1_0                  , RULL(0x8000001A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_CNTR_STATUS2_P1_0                  , RULL(0x8000001A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_CNTR_STATUS2_P1_1                  , RULL(0x8000041A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_CNTR_STATUS2_P1_1                  , RULL(0x8000041A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_CNTR_STATUS2_P1_2                  , RULL(0x8000081A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_CNTR_STATUS2_P1_2                  , RULL(0x8000081A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_CNTR_STATUS2_P1_3                  , RULL(0x80000C1A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_CNTR_STATUS2_P1_3                  , RULL(0x80000C1A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_CNTR_STATUS2_P1_4                  , RULL(0x8000101A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_CNTR_STATUS2_P1_4                  , RULL(0x8000101A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_CNTR_STATUS2_P2_0                  , RULL(0x8000001A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_CNTR_STATUS2_P2_0                  , RULL(0x8000001A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_CNTR_STATUS2_P2_1                  , RULL(0x8000041A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_CNTR_STATUS2_P2_1                  , RULL(0x8000041A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_CNTR_STATUS2_P2_2                  , RULL(0x8000081A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_CNTR_STATUS2_P2_2                  , RULL(0x8000081A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_CNTR_STATUS2_P2_3                  , RULL(0x80000C1A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_CNTR_STATUS2_P2_3                  , RULL(0x80000C1A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_CNTR_STATUS2_P2_4                  , RULL(0x8000101A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_CNTR_STATUS2_P2_4                  , RULL(0x8000101A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_CNTR_STATUS2_P3_0                  , RULL(0x8000001A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_CNTR_STATUS2_P3_0                  , RULL(0x8000001A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_CNTR_STATUS2_P3_1                  , RULL(0x8000041A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_CNTR_STATUS2_P3_1                  , RULL(0x8000041A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_CNTR_STATUS2_P3_2                  , RULL(0x8000081A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_CNTR_STATUS2_P3_2                  , RULL(0x8000081A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_CNTR_STATUS2_P3_3                  , RULL(0x80000C1A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_CNTR_STATUS2_P3_3                  , RULL(0x80000C1A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_CNTR_STATUS2_P3_4                  , RULL(0x8000101A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_CNTR_STATUS2_P3_4                  , RULL(0x8000101A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_ERROR0_P0_0                          , RULL(0x8000001B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_0_DDRPHY_DP16_WR_ERROR0_P0_0                        , RULL(0x8000001B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_4_DDRPHY_DP16_WR_ERROR0_P0_0                        , RULL(0x8000001B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_DDRPHY_DP16_WR_ERROR0_P0_1                          , RULL(0x8000041B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_0_DDRPHY_DP16_WR_ERROR0_P0_1                        , RULL(0x8000041B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_4_DDRPHY_DP16_WR_ERROR0_P0_1                        , RULL(0x8000041B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_DDRPHY_DP16_WR_ERROR0_P0_2                          , RULL(0x8000081B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_0_DDRPHY_DP16_WR_ERROR0_P0_2                        , RULL(0x8000081B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_4_DDRPHY_DP16_WR_ERROR0_P0_2                        , RULL(0x8000081B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_DDRPHY_DP16_WR_ERROR0_P0_3                          , RULL(0x80000C1B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_0_DDRPHY_DP16_WR_ERROR0_P0_3                        , RULL(0x80000C1B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_4_DDRPHY_DP16_WR_ERROR0_P0_3                        , RULL(0x80000C1B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_DDRPHY_DP16_WR_ERROR0_P0_4                          , RULL(0x8000101B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_0_DDRPHY_DP16_WR_ERROR0_P0_4                        , RULL(0x8000101B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_4_DDRPHY_DP16_WR_ERROR0_P0_4                        , RULL(0x8000101B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_1_DDRPHY_DP16_WR_ERROR0_P1_0                        , RULL(0x8000001B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_5_DDRPHY_DP16_WR_ERROR0_P1_0                        , RULL(0x8000001B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_1_DDRPHY_DP16_WR_ERROR0_P1_1                        , RULL(0x8000041B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_5_DDRPHY_DP16_WR_ERROR0_P1_1                        , RULL(0x8000041B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_1_DDRPHY_DP16_WR_ERROR0_P1_2                        , RULL(0x8000081B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_5_DDRPHY_DP16_WR_ERROR0_P1_2                        , RULL(0x8000081B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_1_DDRPHY_DP16_WR_ERROR0_P1_3                        , RULL(0x80000C1B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_5_DDRPHY_DP16_WR_ERROR0_P1_3                        , RULL(0x80000C1B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_1_DDRPHY_DP16_WR_ERROR0_P1_4                        , RULL(0x8000101B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_5_DDRPHY_DP16_WR_ERROR0_P1_4                        , RULL(0x8000101B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_2_DDRPHY_DP16_WR_ERROR0_P2_0                        , RULL(0x8000001B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_6_DDRPHY_DP16_WR_ERROR0_P2_0                        , RULL(0x8000001B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_2_DDRPHY_DP16_WR_ERROR0_P2_1                        , RULL(0x8000041B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_6_DDRPHY_DP16_WR_ERROR0_P2_1                        , RULL(0x8000041B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_2_DDRPHY_DP16_WR_ERROR0_P2_2                        , RULL(0x8000081B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_6_DDRPHY_DP16_WR_ERROR0_P2_2                        , RULL(0x8000081B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_2_DDRPHY_DP16_WR_ERROR0_P2_3                        , RULL(0x80000C1B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_6_DDRPHY_DP16_WR_ERROR0_P2_3                        , RULL(0x80000C1B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_2_DDRPHY_DP16_WR_ERROR0_P2_4                        , RULL(0x8000101B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_6_DDRPHY_DP16_WR_ERROR0_P2_4                        , RULL(0x8000101B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_3_DDRPHY_DP16_WR_ERROR0_P3_0                        , RULL(0x8000001B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_7_DDRPHY_DP16_WR_ERROR0_P3_0                        , RULL(0x8000001B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_3_DDRPHY_DP16_WR_ERROR0_P3_1                        , RULL(0x8000041B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_7_DDRPHY_DP16_WR_ERROR0_P3_1                        , RULL(0x8000041B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_3_DDRPHY_DP16_WR_ERROR0_P3_2                        , RULL(0x8000081B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_7_DDRPHY_DP16_WR_ERROR0_P3_2                        , RULL(0x8000081B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_3_DDRPHY_DP16_WR_ERROR0_P3_3                        , RULL(0x80000C1B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_7_DDRPHY_DP16_WR_ERROR0_P3_3                        , RULL(0x80000C1B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_3_DDRPHY_DP16_WR_ERROR0_P3_4                        , RULL(0x8000101B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RCLRPART );
+REG64( MCA_7_DDRPHY_DP16_WR_ERROR0_P3_4                        , RULL(0x8000101B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RCLRPART );
+
+REG64( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0                     , RULL(0x8000001C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_ERROR_MASK0_P0_0                   , RULL(0x8000001C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_ERROR_MASK0_P0_0                   , RULL(0x8000001C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1                     , RULL(0x8000041C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_ERROR_MASK0_P0_1                   , RULL(0x8000041C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_ERROR_MASK0_P0_1                   , RULL(0x8000041C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2                     , RULL(0x8000081C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_ERROR_MASK0_P0_2                   , RULL(0x8000081C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_ERROR_MASK0_P0_2                   , RULL(0x8000081C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3                     , RULL(0x80000C1C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_ERROR_MASK0_P0_3                   , RULL(0x80000C1C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_ERROR_MASK0_P0_3                   , RULL(0x80000C1C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4                     , RULL(0x8000101C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_ERROR_MASK0_P0_4                   , RULL(0x8000101C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_ERROR_MASK0_P0_4                   , RULL(0x8000101C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_ERROR_MASK0_P1_0                   , RULL(0x8000001C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_ERROR_MASK0_P1_0                   , RULL(0x8000001C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_ERROR_MASK0_P1_1                   , RULL(0x8000041C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_ERROR_MASK0_P1_1                   , RULL(0x8000041C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_ERROR_MASK0_P1_2                   , RULL(0x8000081C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_ERROR_MASK0_P1_2                   , RULL(0x8000081C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_ERROR_MASK0_P1_3                   , RULL(0x80000C1C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_ERROR_MASK0_P1_3                   , RULL(0x80000C1C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_ERROR_MASK0_P1_4                   , RULL(0x8000101C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_ERROR_MASK0_P1_4                   , RULL(0x8000101C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_ERROR_MASK0_P2_0                   , RULL(0x8000001C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_ERROR_MASK0_P2_0                   , RULL(0x8000001C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_ERROR_MASK0_P2_1                   , RULL(0x8000041C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_ERROR_MASK0_P2_1                   , RULL(0x8000041C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_ERROR_MASK0_P2_2                   , RULL(0x8000081C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_ERROR_MASK0_P2_2                   , RULL(0x8000081C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_ERROR_MASK0_P2_3                   , RULL(0x80000C1C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_ERROR_MASK0_P2_3                   , RULL(0x80000C1C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_ERROR_MASK0_P2_4                   , RULL(0x8000101C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_ERROR_MASK0_P2_4                   , RULL(0x8000101C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_ERROR_MASK0_P3_0                   , RULL(0x8000001C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_ERROR_MASK0_P3_0                   , RULL(0x8000001C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_ERROR_MASK0_P3_1                   , RULL(0x8000041C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_ERROR_MASK0_P3_1                   , RULL(0x8000041C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_ERROR_MASK0_P3_2                   , RULL(0x8000081C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_ERROR_MASK0_P3_2                   , RULL(0x8000081C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_ERROR_MASK0_P3_3                   , RULL(0x80000C1C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_ERROR_MASK0_P3_3                   , RULL(0x80000C1C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_ERROR_MASK0_P3_4                   , RULL(0x8000101C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_ERROR_MASK0_P3_4                   , RULL(0x8000101C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0                     , RULL(0x800000170701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_LVL_STATUS0_P0_0                   , RULL(0x800000170701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_LVL_STATUS0_P0_0                   , RULL(0x800000170801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1                     , RULL(0x800004170701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_LVL_STATUS0_P0_1                   , RULL(0x800004170701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_LVL_STATUS0_P0_1                   , RULL(0x800004170801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2                     , RULL(0x800008170701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_LVL_STATUS0_P0_2                   , RULL(0x800008170701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_LVL_STATUS0_P0_2                   , RULL(0x800008170801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3                     , RULL(0x80000C170701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_LVL_STATUS0_P0_3                   , RULL(0x80000C170701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_LVL_STATUS0_P0_3                   , RULL(0x80000C170801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4                     , RULL(0x800010170701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_LVL_STATUS0_P0_4                   , RULL(0x800010170701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_LVL_STATUS0_P0_4                   , RULL(0x800010170801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_LVL_STATUS0_P1_0                   , RULL(0x800000170701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_LVL_STATUS0_P1_0                   , RULL(0x800000170801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_LVL_STATUS0_P1_1                   , RULL(0x800004170701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_LVL_STATUS0_P1_1                   , RULL(0x800004170801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_LVL_STATUS0_P1_2                   , RULL(0x800008170701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_LVL_STATUS0_P1_2                   , RULL(0x800008170801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_LVL_STATUS0_P1_3                   , RULL(0x80000C170701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_LVL_STATUS0_P1_3                   , RULL(0x80000C170801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_LVL_STATUS0_P1_4                   , RULL(0x800010170701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_LVL_STATUS0_P1_4                   , RULL(0x800010170801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_LVL_STATUS0_P2_0                   , RULL(0x800000170701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_LVL_STATUS0_P2_0                   , RULL(0x800000170801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_LVL_STATUS0_P2_1                   , RULL(0x800004170701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_LVL_STATUS0_P2_1                   , RULL(0x800004170801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_LVL_STATUS0_P2_2                   , RULL(0x800008170701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_LVL_STATUS0_P2_2                   , RULL(0x800008170801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_LVL_STATUS0_P2_3                   , RULL(0x80000C170701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_LVL_STATUS0_P2_3                   , RULL(0x80000C170801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_LVL_STATUS0_P2_4                   , RULL(0x800010170701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_LVL_STATUS0_P2_4                   , RULL(0x800010170801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_LVL_STATUS0_P3_0                   , RULL(0x8000001707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_LVL_STATUS0_P3_0                   , RULL(0x8000001708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_LVL_STATUS0_P3_1                   , RULL(0x8000041707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_LVL_STATUS0_P3_1                   , RULL(0x8000041708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_LVL_STATUS0_P3_2                   , RULL(0x8000081707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_LVL_STATUS0_P3_2                   , RULL(0x8000081708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_LVL_STATUS0_P3_3                   , RULL(0x80000C1707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_LVL_STATUS0_P3_3                   , RULL(0x80000C1708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_LVL_STATUS0_P3_4                   , RULL(0x8000101707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_LVL_STATUS0_P3_4                   , RULL(0x8000101708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0                    , RULL(0x8000006C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0                  , RULL(0x8000006C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0                  , RULL(0x8000006C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1                    , RULL(0x8000046C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1                  , RULL(0x8000046C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1                  , RULL(0x8000046C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2                    , RULL(0x8000086C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2                  , RULL(0x8000086C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2                  , RULL(0x8000086C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3                    , RULL(0x80000C6C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3                  , RULL(0x80000C6C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3                  , RULL(0x80000C6C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4                    , RULL(0x8000106C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4                  , RULL(0x8000106C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4                  , RULL(0x8000106C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_CONFIG0_P1_0                  , RULL(0x8000006C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_CONFIG0_P1_0                  , RULL(0x8000006C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_CONFIG0_P1_1                  , RULL(0x8000046C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_CONFIG0_P1_1                  , RULL(0x8000046C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_CONFIG0_P1_2                  , RULL(0x8000086C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_CONFIG0_P1_2                  , RULL(0x8000086C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_CONFIG0_P1_3                  , RULL(0x80000C6C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_CONFIG0_P1_3                  , RULL(0x80000C6C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_CONFIG0_P1_4                  , RULL(0x8000106C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_CONFIG0_P1_4                  , RULL(0x8000106C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_CONFIG0_P2_0                  , RULL(0x8000006C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_CONFIG0_P2_0                  , RULL(0x8000006C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_CONFIG0_P2_1                  , RULL(0x8000046C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_CONFIG0_P2_1                  , RULL(0x8000046C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_CONFIG0_P2_2                  , RULL(0x8000086C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_CONFIG0_P2_2                  , RULL(0x8000086C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_CONFIG0_P2_3                  , RULL(0x80000C6C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_CONFIG0_P2_3                  , RULL(0x80000C6C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_CONFIG0_P2_4                  , RULL(0x8000106C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_CONFIG0_P2_4                  , RULL(0x8000106C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_CONFIG0_P3_0                  , RULL(0x8000006C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_CONFIG0_P3_0                  , RULL(0x8000006C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_CONFIG0_P3_1                  , RULL(0x8000046C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_CONFIG0_P3_1                  , RULL(0x8000046C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_CONFIG0_P3_2                  , RULL(0x8000086C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_CONFIG0_P3_2                  , RULL(0x8000086C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_CONFIG0_P3_3                  , RULL(0x80000C6C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_CONFIG0_P3_3                  , RULL(0x80000C6C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_CONFIG0_P3_4                  , RULL(0x8000106C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_CONFIG0_P3_4                  , RULL(0x8000106C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0                    , RULL(0x800000EC0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0                  , RULL(0x800000EC0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0                  , RULL(0x800000EC0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1                    , RULL(0x800004EC0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1                  , RULL(0x800004EC0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1                  , RULL(0x800004EC0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2                    , RULL(0x800008EC0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2                  , RULL(0x800008EC0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2                  , RULL(0x800008EC0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3                    , RULL(0x80000CEC0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3                  , RULL(0x80000CEC0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3                  , RULL(0x80000CEC0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4                    , RULL(0x800010EC0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4                  , RULL(0x800010EC0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4                  , RULL(0x800010EC0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_CONFIG1_P1_0                  , RULL(0x800000EC0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_CONFIG1_P1_0                  , RULL(0x800000EC0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_CONFIG1_P1_1                  , RULL(0x800004EC0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_CONFIG1_P1_1                  , RULL(0x800004EC0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_CONFIG1_P1_2                  , RULL(0x800008EC0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_CONFIG1_P1_2                  , RULL(0x800008EC0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_CONFIG1_P1_3                  , RULL(0x80000CEC0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_CONFIG1_P1_3                  , RULL(0x80000CEC0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_CONFIG1_P1_4                  , RULL(0x800010EC0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_CONFIG1_P1_4                  , RULL(0x800010EC0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_CONFIG1_P2_0                  , RULL(0x800000EC0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_CONFIG1_P2_0                  , RULL(0x800000EC0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_CONFIG1_P2_1                  , RULL(0x800004EC0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_CONFIG1_P2_1                  , RULL(0x800004EC0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_CONFIG1_P2_2                  , RULL(0x800008EC0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_CONFIG1_P2_2                  , RULL(0x800008EC0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_CONFIG1_P2_3                  , RULL(0x80000CEC0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_CONFIG1_P2_3                  , RULL(0x80000CEC0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_CONFIG1_P2_4                  , RULL(0x800010EC0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_CONFIG1_P2_4                  , RULL(0x800010EC0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_CONFIG1_P3_0                  , RULL(0x800000EC07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_CONFIG1_P3_0                  , RULL(0x800000EC08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_CONFIG1_P3_1                  , RULL(0x800004EC07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_CONFIG1_P3_1                  , RULL(0x800004EC08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_CONFIG1_P3_2                  , RULL(0x800008EC07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_CONFIG1_P3_2                  , RULL(0x800008EC08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_CONFIG1_P3_3                  , RULL(0x80000CEC07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_CONFIG1_P3_3                  , RULL(0x80000CEC08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_CONFIG1_P3_4                  , RULL(0x800010EC07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_CONFIG1_P3_4                  , RULL(0x800010EC08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0                     , RULL(0x800000AE0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR0_P0_0                   , RULL(0x800000AE0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR0_P0_0                   , RULL(0x800000AE0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1                     , RULL(0x800004AE0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR0_P0_1                   , RULL(0x800004AE0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR0_P0_1                   , RULL(0x800004AE0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2                     , RULL(0x800008AE0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR0_P0_2                   , RULL(0x800008AE0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR0_P0_2                   , RULL(0x800008AE0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3                     , RULL(0x80000CAE0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR0_P0_3                   , RULL(0x80000CAE0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR0_P0_3                   , RULL(0x80000CAE0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4                     , RULL(0x800010AE0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR0_P0_4                   , RULL(0x800010AE0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR0_P0_4                   , RULL(0x800010AE0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR0_P1_0                   , RULL(0x800000AE0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR0_P1_0                   , RULL(0x800000AE0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR0_P1_1                   , RULL(0x800004AE0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR0_P1_1                   , RULL(0x800004AE0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR0_P1_2                   , RULL(0x800008AE0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR0_P1_2                   , RULL(0x800008AE0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR0_P1_3                   , RULL(0x80000CAE0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR0_P1_3                   , RULL(0x80000CAE0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR0_P1_4                   , RULL(0x800010AE0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR0_P1_4                   , RULL(0x800010AE0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR0_P2_0                   , RULL(0x800000AE0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR0_P2_0                   , RULL(0x800000AE0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR0_P2_1                   , RULL(0x800004AE0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR0_P2_1                   , RULL(0x800004AE0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR0_P2_2                   , RULL(0x800008AE0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR0_P2_2                   , RULL(0x800008AE0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR0_P2_3                   , RULL(0x80000CAE0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR0_P2_3                   , RULL(0x80000CAE0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR0_P2_4                   , RULL(0x800010AE0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR0_P2_4                   , RULL(0x800010AE0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR0_P3_0                   , RULL(0x800000AE07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR0_P3_0                   , RULL(0x800000AE08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR0_P3_1                   , RULL(0x800004AE07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR0_P3_1                   , RULL(0x800004AE08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR0_P3_2                   , RULL(0x800008AE07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR0_P3_2                   , RULL(0x800008AE08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR0_P3_3                   , RULL(0x80000CAE07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR0_P3_3                   , RULL(0x80000CAE08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR0_P3_4                   , RULL(0x800010AE07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR0_P3_4                   , RULL(0x800010AE08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0                     , RULL(0x800000AF0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR1_P0_0                   , RULL(0x800000AF0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR1_P0_0                   , RULL(0x800000AF0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1                     , RULL(0x800004AF0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR1_P0_1                   , RULL(0x800004AF0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR1_P0_1                   , RULL(0x800004AF0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2                     , RULL(0x800008AF0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR1_P0_2                   , RULL(0x800008AF0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR1_P0_2                   , RULL(0x800008AF0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3                     , RULL(0x80000CAF0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR1_P0_3                   , RULL(0x80000CAF0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR1_P0_3                   , RULL(0x80000CAF0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4                     , RULL(0x800010AF0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR1_P0_4                   , RULL(0x800010AF0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR1_P0_4                   , RULL(0x800010AF0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR1_P1_0                   , RULL(0x800000AF0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR1_P1_0                   , RULL(0x800000AF0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR1_P1_1                   , RULL(0x800004AF0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR1_P1_1                   , RULL(0x800004AF0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR1_P1_2                   , RULL(0x800008AF0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR1_P1_2                   , RULL(0x800008AF0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR1_P1_3                   , RULL(0x80000CAF0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR1_P1_3                   , RULL(0x80000CAF0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR1_P1_4                   , RULL(0x800010AF0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR1_P1_4                   , RULL(0x800010AF0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR1_P2_0                   , RULL(0x800000AF0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR1_P2_0                   , RULL(0x800000AF0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR1_P2_1                   , RULL(0x800004AF0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR1_P2_1                   , RULL(0x800004AF0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR1_P2_2                   , RULL(0x800008AF0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR1_P2_2                   , RULL(0x800008AF0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR1_P2_3                   , RULL(0x80000CAF0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR1_P2_3                   , RULL(0x80000CAF0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR1_P2_4                   , RULL(0x800010AF0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR1_P2_4                   , RULL(0x800010AF0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR1_P3_0                   , RULL(0x800000AF07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR1_P3_0                   , RULL(0x800000AF08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR1_P3_1                   , RULL(0x800004AF07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR1_P3_1                   , RULL(0x800004AF08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR1_P3_2                   , RULL(0x800008AF07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR1_P3_2                   , RULL(0x800008AF08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR1_P3_3                   , RULL(0x80000CAF07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR1_P3_3                   , RULL(0x80000CAF08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR1_P3_4                   , RULL(0x800010AF07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR1_P3_4                   , RULL(0x800010AF08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0                , RULL(0x800000FB0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0              , RULL(0x800000FB0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0              , RULL(0x800000FB0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1                , RULL(0x800004FB0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1              , RULL(0x800004FB0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1              , RULL(0x800004FB0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2                , RULL(0x800008FB0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2              , RULL(0x800008FB0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2              , RULL(0x800008FB0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3                , RULL(0x80000CFB0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3              , RULL(0x80000CFB0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3              , RULL(0x80000CFB0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4                , RULL(0x800010FB0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4              , RULL(0x800010FB0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4              , RULL(0x800010FB0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_0              , RULL(0x800000FB0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_0              , RULL(0x800000FB0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_1              , RULL(0x800004FB0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_1              , RULL(0x800004FB0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_2              , RULL(0x800008FB0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_2              , RULL(0x800008FB0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_3              , RULL(0x80000CFB0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_3              , RULL(0x80000CFB0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_4              , RULL(0x800010FB0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P1_4              , RULL(0x800010FB0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_0              , RULL(0x800000FB0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_0              , RULL(0x800000FB0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_1              , RULL(0x800004FB0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_1              , RULL(0x800004FB0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_2              , RULL(0x800008FB0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_2              , RULL(0x800008FB0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_3              , RULL(0x80000CFB0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_3              , RULL(0x80000CFB0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_4              , RULL(0x800010FB0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P2_4              , RULL(0x800010FB0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_0              , RULL(0x800000FB07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_0              , RULL(0x800000FB08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_1              , RULL(0x800004FB07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_1              , RULL(0x800004FB08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_2              , RULL(0x800008FB07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_2              , RULL(0x800008FB08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_3              , RULL(0x80000CFB07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_3              , RULL(0x80000CFB08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_4              , RULL(0x800010FB07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P3_4              , RULL(0x800010FB08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0                , RULL(0x800000FA0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0              , RULL(0x800000FA0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0              , RULL(0x800000FA0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1                , RULL(0x800004FA0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1              , RULL(0x800004FA0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1              , RULL(0x800004FA0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2                , RULL(0x800008FA0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2              , RULL(0x800008FA0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2              , RULL(0x800008FA0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3                , RULL(0x80000CFA0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3              , RULL(0x80000CFA0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3              , RULL(0x80000CFA0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4                , RULL(0x800010FA0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4              , RULL(0x800010FA0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4              , RULL(0x800010FA0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_0              , RULL(0x800000FA0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_0              , RULL(0x800000FA0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_1              , RULL(0x800004FA0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_1              , RULL(0x800004FA0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_2              , RULL(0x800008FA0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_2              , RULL(0x800008FA0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_3              , RULL(0x80000CFA0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_3              , RULL(0x80000CFA0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_4              , RULL(0x800010FA0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P1_4              , RULL(0x800010FA0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_0              , RULL(0x800000FA0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_0              , RULL(0x800000FA0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_1              , RULL(0x800004FA0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_1              , RULL(0x800004FA0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_2              , RULL(0x800008FA0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_2              , RULL(0x800008FA0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_3              , RULL(0x80000CFA0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_3              , RULL(0x80000CFA0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_4              , RULL(0x800010FA0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P2_4              , RULL(0x800010FA0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_0              , RULL(0x800000FA07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_0              , RULL(0x800000FA08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_1              , RULL(0x800004FA07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_1              , RULL(0x800004FA08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_2              , RULL(0x800008FA07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_2              , RULL(0x800008FA08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_3              , RULL(0x80000CFA07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_3              , RULL(0x80000CFA08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_4              , RULL(0x800010FA07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P3_4              , RULL(0x800010FA08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0                    , RULL(0x8000002E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_STATUS0_P0_0                  , RULL(0x8000002E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_STATUS0_P0_0                  , RULL(0x8000002E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_1                    , RULL(0x8000042E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_STATUS0_P0_1                  , RULL(0x8000042E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_STATUS0_P0_1                  , RULL(0x8000042E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_2                    , RULL(0x8000082E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_STATUS0_P0_2                  , RULL(0x8000082E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_STATUS0_P0_2                  , RULL(0x8000082E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_3                    , RULL(0x80000C2E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_STATUS0_P0_3                  , RULL(0x80000C2E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_STATUS0_P0_3                  , RULL(0x80000C2E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_4                    , RULL(0x8000102E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_STATUS0_P0_4                  , RULL(0x8000102E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_STATUS0_P0_4                  , RULL(0x8000102E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_STATUS0_P1_0                  , RULL(0x8000002E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_STATUS0_P1_0                  , RULL(0x8000002E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_STATUS0_P1_1                  , RULL(0x8000042E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_STATUS0_P1_1                  , RULL(0x8000042E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_STATUS0_P1_2                  , RULL(0x8000082E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_STATUS0_P1_2                  , RULL(0x8000082E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_STATUS0_P1_3                  , RULL(0x80000C2E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_STATUS0_P1_3                  , RULL(0x80000C2E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_STATUS0_P1_4                  , RULL(0x8000102E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_STATUS0_P1_4                  , RULL(0x8000102E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_STATUS0_P2_0                  , RULL(0x8000002E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_STATUS0_P2_0                  , RULL(0x8000002E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_STATUS0_P2_1                  , RULL(0x8000042E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_STATUS0_P2_1                  , RULL(0x8000042E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_STATUS0_P2_2                  , RULL(0x8000082E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_STATUS0_P2_2                  , RULL(0x8000082E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_STATUS0_P2_3                  , RULL(0x80000C2E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_STATUS0_P2_3                  , RULL(0x80000C2E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_STATUS0_P2_4                  , RULL(0x8000102E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_STATUS0_P2_4                  , RULL(0x8000102E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_STATUS0_P3_0                  , RULL(0x8000002E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_STATUS0_P3_0                  , RULL(0x8000002E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_STATUS0_P3_1                  , RULL(0x8000042E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_STATUS0_P3_1                  , RULL(0x8000042E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_STATUS0_P3_2                  , RULL(0x8000082E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_STATUS0_P3_2                  , RULL(0x8000082E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_STATUS0_P3_3                  , RULL(0x80000C2E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_STATUS0_P3_3                  , RULL(0x80000C2E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_STATUS0_P3_4                  , RULL(0x8000102E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_STATUS0_P3_4                  , RULL(0x8000102E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0                    , RULL(0x8000002F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_STATUS1_P0_0                  , RULL(0x8000002F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_STATUS1_P0_0                  , RULL(0x8000002F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1                    , RULL(0x8000042F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_STATUS1_P0_1                  , RULL(0x8000042F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_STATUS1_P0_1                  , RULL(0x8000042F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2                    , RULL(0x8000082F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_STATUS1_P0_2                  , RULL(0x8000082F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_STATUS1_P0_2                  , RULL(0x8000082F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3                    , RULL(0x80000C2F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_STATUS1_P0_3                  , RULL(0x80000C2F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_STATUS1_P0_3                  , RULL(0x80000C2F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4                    , RULL(0x8000102F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_STATUS1_P0_4                  , RULL(0x8000102F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_STATUS1_P0_4                  , RULL(0x8000102F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_STATUS1_P1_0                  , RULL(0x8000002F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_STATUS1_P1_0                  , RULL(0x8000002F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_STATUS1_P1_1                  , RULL(0x8000042F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_STATUS1_P1_1                  , RULL(0x8000042F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_STATUS1_P1_2                  , RULL(0x8000082F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_STATUS1_P1_2                  , RULL(0x8000082F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_STATUS1_P1_3                  , RULL(0x80000C2F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_STATUS1_P1_3                  , RULL(0x80000C2F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_STATUS1_P1_4                  , RULL(0x8000102F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_STATUS1_P1_4                  , RULL(0x8000102F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_STATUS1_P2_0                  , RULL(0x8000002F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_STATUS1_P2_0                  , RULL(0x8000002F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_STATUS1_P2_1                  , RULL(0x8000042F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_STATUS1_P2_1                  , RULL(0x8000042F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_STATUS1_P2_2                  , RULL(0x8000082F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_STATUS1_P2_2                  , RULL(0x8000082F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_STATUS1_P2_3                  , RULL(0x80000C2F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_STATUS1_P2_3                  , RULL(0x80000C2F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_STATUS1_P2_4                  , RULL(0x8000102F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_STATUS1_P2_4                  , RULL(0x8000102F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_STATUS1_P3_0                  , RULL(0x8000002F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_STATUS1_P3_0                  , RULL(0x8000002F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_STATUS1_P3_1                  , RULL(0x8000042F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_STATUS1_P3_1                  , RULL(0x8000042F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_STATUS1_P3_2                  , RULL(0x8000082F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_STATUS1_P3_2                  , RULL(0x8000082F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_STATUS1_P3_3                  , RULL(0x80000C2F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_STATUS1_P3_3                  , RULL(0x80000C2F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_STATUS1_P3_4                  , RULL(0x8000102F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_STATUS1_P3_4                  , RULL(0x8000102F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0          , RULL(0x8000005E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0        , RULL(0x8000005E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0        , RULL(0x8000005E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1          , RULL(0x8000045E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1        , RULL(0x8000045E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1        , RULL(0x8000045E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2          , RULL(0x8000085E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2        , RULL(0x8000085E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2        , RULL(0x8000085E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3          , RULL(0x80000C5E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3        , RULL(0x80000C5E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3        , RULL(0x80000C5E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4          , RULL(0x8000105E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4        , RULL(0x8000105E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4        , RULL(0x8000105E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_0        , RULL(0x8000005E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_0        , RULL(0x8000005E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_1        , RULL(0x8000045E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_1        , RULL(0x8000045E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_2        , RULL(0x8000085E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_2        , RULL(0x8000085E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_3        , RULL(0x80000C5E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_3        , RULL(0x80000C5E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_4        , RULL(0x8000105E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P1_4        , RULL(0x8000105E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_0        , RULL(0x8000005E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_0        , RULL(0x8000005E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_1        , RULL(0x8000045E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_1        , RULL(0x8000045E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_2        , RULL(0x8000085E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_2        , RULL(0x8000085E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_3        , RULL(0x80000C5E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_3        , RULL(0x80000C5E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_4        , RULL(0x8000105E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P2_4        , RULL(0x8000105E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_0        , RULL(0x8000005E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_0        , RULL(0x8000005E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_1        , RULL(0x8000045E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_1        , RULL(0x8000045E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_2        , RULL(0x8000085E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_2        , RULL(0x8000085E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_3        , RULL(0x80000C5E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_3        , RULL(0x80000C5E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_4        , RULL(0x8000105E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P3_4        , RULL(0x8000105E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0          , RULL(0x8000015E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0        , RULL(0x8000015E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0        , RULL(0x8000015E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1          , RULL(0x8000055E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1        , RULL(0x8000055E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1        , RULL(0x8000055E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2          , RULL(0x8000095E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2        , RULL(0x8000095E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2        , RULL(0x8000095E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3          , RULL(0x80000D5E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3        , RULL(0x80000D5E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3        , RULL(0x80000D5E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4          , RULL(0x8000115E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4        , RULL(0x8000115E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4        , RULL(0x8000115E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_0        , RULL(0x8000015E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_0        , RULL(0x8000015E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_1        , RULL(0x8000055E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_1        , RULL(0x8000055E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_2        , RULL(0x8000095E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_2        , RULL(0x8000095E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_3        , RULL(0x80000D5E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_3        , RULL(0x80000D5E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_4        , RULL(0x8000115E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P1_4        , RULL(0x8000115E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_0        , RULL(0x8000015E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_0        , RULL(0x8000015E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_1        , RULL(0x8000055E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_1        , RULL(0x8000055E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_2        , RULL(0x8000095E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_2        , RULL(0x8000095E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_3        , RULL(0x80000D5E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_3        , RULL(0x80000D5E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_4        , RULL(0x8000115E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P2_4        , RULL(0x8000115E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_0        , RULL(0x8000015E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_0        , RULL(0x8000015E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_1        , RULL(0x8000055E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_1        , RULL(0x8000055E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_2        , RULL(0x8000095E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_2        , RULL(0x8000095E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_3        , RULL(0x80000D5E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_3        , RULL(0x80000D5E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_4        , RULL(0x8000115E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P3_4        , RULL(0x8000115E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0          , RULL(0x8000025E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0        , RULL(0x8000025E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0        , RULL(0x8000025E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1          , RULL(0x8000065E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1        , RULL(0x8000065E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1        , RULL(0x8000065E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2          , RULL(0x80000A5E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2        , RULL(0x80000A5E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2        , RULL(0x80000A5E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3          , RULL(0x80000E5E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3        , RULL(0x80000E5E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3        , RULL(0x80000E5E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4          , RULL(0x8000125E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4        , RULL(0x8000125E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4        , RULL(0x8000125E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_0        , RULL(0x8000025E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_0        , RULL(0x8000025E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_1        , RULL(0x8000065E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_1        , RULL(0x8000065E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_2        , RULL(0x80000A5E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_2        , RULL(0x80000A5E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_3        , RULL(0x80000E5E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_3        , RULL(0x80000E5E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_4        , RULL(0x8000125E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P1_4        , RULL(0x8000125E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_0        , RULL(0x8000025E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_0        , RULL(0x8000025E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_1        , RULL(0x8000065E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_1        , RULL(0x8000065E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_2        , RULL(0x80000A5E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_2        , RULL(0x80000A5E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_3        , RULL(0x80000E5E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_3        , RULL(0x80000E5E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_4        , RULL(0x8000125E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P2_4        , RULL(0x8000125E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_0        , RULL(0x8000025E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_0        , RULL(0x8000025E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_1        , RULL(0x8000065E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_1        , RULL(0x8000065E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_2        , RULL(0x80000A5E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_2        , RULL(0x80000A5E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_3        , RULL(0x80000E5E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_3        , RULL(0x80000E5E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_4        , RULL(0x8000125E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P3_4        , RULL(0x8000125E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0          , RULL(0x8000035E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0        , RULL(0x8000035E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0        , RULL(0x8000035E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1          , RULL(0x8000075E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1        , RULL(0x8000075E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1        , RULL(0x8000075E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2          , RULL(0x80000B5E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2        , RULL(0x80000B5E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2        , RULL(0x80000B5E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3          , RULL(0x80000F5E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3        , RULL(0x80000F5E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3        , RULL(0x80000F5E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4          , RULL(0x8000135E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4        , RULL(0x8000135E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4        , RULL(0x8000135E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_0        , RULL(0x8000035E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_0        , RULL(0x8000035E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_1        , RULL(0x8000075E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_1        , RULL(0x8000075E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_2        , RULL(0x80000B5E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_2        , RULL(0x80000B5E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_3        , RULL(0x80000F5E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_3        , RULL(0x80000F5E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_4        , RULL(0x8000135E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P1_4        , RULL(0x8000135E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_0        , RULL(0x8000035E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_0        , RULL(0x8000035E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_1        , RULL(0x8000075E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_1        , RULL(0x8000075E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_2        , RULL(0x80000B5E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_2        , RULL(0x80000B5E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_3        , RULL(0x80000F5E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_3        , RULL(0x80000F5E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_4        , RULL(0x8000135E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P2_4        , RULL(0x8000135E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_0        , RULL(0x8000035E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_0        , RULL(0x8000035E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_1        , RULL(0x8000075E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_1        , RULL(0x8000075E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_2        , RULL(0x80000B5E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_2        , RULL(0x80000B5E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_3        , RULL(0x80000F5E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_3        , RULL(0x80000F5E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_4        , RULL(0x8000135E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P3_4        , RULL(0x8000135E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0          , RULL(0x8000005F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0        , RULL(0x8000005F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0        , RULL(0x8000005F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1          , RULL(0x8000045F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1        , RULL(0x8000045F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1        , RULL(0x8000045F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2          , RULL(0x8000085F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2        , RULL(0x8000085F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2        , RULL(0x8000085F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3          , RULL(0x80000C5F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3        , RULL(0x80000C5F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3        , RULL(0x80000C5F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4          , RULL(0x8000105F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4        , RULL(0x8000105F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4        , RULL(0x8000105F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_0        , RULL(0x8000005F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_0        , RULL(0x8000005F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_1        , RULL(0x8000045F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_1        , RULL(0x8000045F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_2        , RULL(0x8000085F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_2        , RULL(0x8000085F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_3        , RULL(0x80000C5F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_3        , RULL(0x80000C5F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_4        , RULL(0x8000105F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P1_4        , RULL(0x8000105F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_0        , RULL(0x8000005F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_0        , RULL(0x8000005F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_1        , RULL(0x8000045F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_1        , RULL(0x8000045F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_2        , RULL(0x8000085F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_2        , RULL(0x8000085F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_3        , RULL(0x80000C5F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_3        , RULL(0x80000C5F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_4        , RULL(0x8000105F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P2_4        , RULL(0x8000105F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_0        , RULL(0x8000005F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_0        , RULL(0x8000005F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_1        , RULL(0x8000045F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_1        , RULL(0x8000045F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_2        , RULL(0x8000085F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_2        , RULL(0x8000085F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_3        , RULL(0x80000C5F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_3        , RULL(0x80000C5F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_4        , RULL(0x8000105F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P3_4        , RULL(0x8000105F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0          , RULL(0x8000015F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0        , RULL(0x8000015F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0        , RULL(0x8000015F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1          , RULL(0x8000055F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1        , RULL(0x8000055F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1        , RULL(0x8000055F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2          , RULL(0x8000095F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2        , RULL(0x8000095F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2        , RULL(0x8000095F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3          , RULL(0x80000D5F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3        , RULL(0x80000D5F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3        , RULL(0x80000D5F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4          , RULL(0x8000115F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4        , RULL(0x8000115F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4        , RULL(0x8000115F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_0        , RULL(0x8000015F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_0        , RULL(0x8000015F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_1        , RULL(0x8000055F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_1        , RULL(0x8000055F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_2        , RULL(0x8000095F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_2        , RULL(0x8000095F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_3        , RULL(0x80000D5F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_3        , RULL(0x80000D5F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_4        , RULL(0x8000115F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P1_4        , RULL(0x8000115F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_0        , RULL(0x8000015F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_0        , RULL(0x8000015F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_1        , RULL(0x8000055F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_1        , RULL(0x8000055F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_2        , RULL(0x8000095F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_2        , RULL(0x8000095F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_3        , RULL(0x80000D5F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_3        , RULL(0x80000D5F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_4        , RULL(0x8000115F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P2_4        , RULL(0x8000115F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_0        , RULL(0x8000015F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_0        , RULL(0x8000015F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_1        , RULL(0x8000055F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_1        , RULL(0x8000055F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_2        , RULL(0x8000095F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_2        , RULL(0x8000095F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_3        , RULL(0x80000D5F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_3        , RULL(0x80000D5F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_4        , RULL(0x8000115F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P3_4        , RULL(0x8000115F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0          , RULL(0x8000025F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0        , RULL(0x8000025F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0        , RULL(0x8000025F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1          , RULL(0x8000065F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1        , RULL(0x8000065F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1        , RULL(0x8000065F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2          , RULL(0x80000A5F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2        , RULL(0x80000A5F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2        , RULL(0x80000A5F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3          , RULL(0x80000E5F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3        , RULL(0x80000E5F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3        , RULL(0x80000E5F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4          , RULL(0x8000125F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4        , RULL(0x8000125F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4        , RULL(0x8000125F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_0        , RULL(0x8000025F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_0        , RULL(0x8000025F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_1        , RULL(0x8000065F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_1        , RULL(0x8000065F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_2        , RULL(0x80000A5F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_2        , RULL(0x80000A5F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_3        , RULL(0x80000E5F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_3        , RULL(0x80000E5F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_4        , RULL(0x8000125F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P1_4        , RULL(0x8000125F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_0        , RULL(0x8000025F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_0        , RULL(0x8000025F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_1        , RULL(0x8000065F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_1        , RULL(0x8000065F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_2        , RULL(0x80000A5F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_2        , RULL(0x80000A5F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_3        , RULL(0x80000E5F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_3        , RULL(0x80000E5F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_4        , RULL(0x8000125F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P2_4        , RULL(0x8000125F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_0        , RULL(0x8000025F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_0        , RULL(0x8000025F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_1        , RULL(0x8000065F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_1        , RULL(0x8000065F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_2        , RULL(0x80000A5F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_2        , RULL(0x80000A5F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_3        , RULL(0x80000E5F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_3        , RULL(0x80000E5F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_4        , RULL(0x8000125F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P3_4        , RULL(0x8000125F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0          , RULL(0x8000035F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0        , RULL(0x8000035F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0        , RULL(0x8000035F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1          , RULL(0x8000075F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1        , RULL(0x8000075F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1        , RULL(0x8000075F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2          , RULL(0x80000B5F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2        , RULL(0x80000B5F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2        , RULL(0x80000B5F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3          , RULL(0x80000F5F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3        , RULL(0x80000F5F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3        , RULL(0x80000F5F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4          , RULL(0x8000135F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4        , RULL(0x8000135F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4        , RULL(0x8000135F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_0        , RULL(0x8000035F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_0        , RULL(0x8000035F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_1        , RULL(0x8000075F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_1        , RULL(0x8000075F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_2        , RULL(0x80000B5F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_2        , RULL(0x80000B5F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_3        , RULL(0x80000F5F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_3        , RULL(0x80000F5F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_4        , RULL(0x8000135F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P1_4        , RULL(0x8000135F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_0        , RULL(0x8000035F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_0        , RULL(0x8000035F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_1        , RULL(0x8000075F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_1        , RULL(0x8000075F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_2        , RULL(0x80000B5F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_2        , RULL(0x80000B5F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_3        , RULL(0x80000F5F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_3        , RULL(0x80000F5F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_4        , RULL(0x8000135F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P2_4        , RULL(0x8000135F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_0        , RULL(0x8000035F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_0        , RULL(0x8000035F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_1        , RULL(0x8000075F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_1        , RULL(0x8000075F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_2        , RULL(0x80000B5F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_2        , RULL(0x80000B5F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_3        , RULL(0x80000F5F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_3        , RULL(0x80000F5F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_4        , RULL(0x8000135F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P3_4        , RULL(0x8000135F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_BASE_CNTR0_P0                             , RULL(0x8000C0040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_PC_BASE_CNTR0_P0                           , RULL(0x8000C0040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_PC_BASE_CNTR0_P0                           , RULL(0x8000C0040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_PC_BASE_CNTR0_P1                           , RULL(0x8000C0040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_PC_BASE_CNTR0_P1                           , RULL(0x8000C0040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_PC_BASE_CNTR0_P2                           , RULL(0x8000C0040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_PC_BASE_CNTR0_P2                           , RULL(0x8000C0040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_PC_BASE_CNTR0_P3                           , RULL(0x8000C00407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_PC_BASE_CNTR0_P3                           , RULL(0x8000C00408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_PC_BASE_CNTR1_P0                             , RULL(0x8000C0060701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_PC_BASE_CNTR1_P0                           , RULL(0x8000C0060701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_PC_BASE_CNTR1_P0                           , RULL(0x8000C0060801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_PC_BASE_CNTR1_P1                           , RULL(0x8000C0060701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_PC_BASE_CNTR1_P1                           , RULL(0x8000C0060801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_PC_BASE_CNTR1_P2                           , RULL(0x8000C0060701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_PC_BASE_CNTR1_P2                           , RULL(0x8000C0060801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_PC_BASE_CNTR1_P3                           , RULL(0x8000C00607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_PC_BASE_CNTR1_P3                           , RULL(0x8000C00608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_PC_CAL_TIMER_P0                              , RULL(0x8000C0070701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_PC_CAL_TIMER_P0                            , RULL(0x8000C0070701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_PC_CAL_TIMER_P0                            , RULL(0x8000C0070801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_PC_CAL_TIMER_P1                            , RULL(0x8000C0070701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_PC_CAL_TIMER_P1                            , RULL(0x8000C0070801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_PC_CAL_TIMER_P2                            , RULL(0x8000C0070701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_PC_CAL_TIMER_P2                            , RULL(0x8000C0070801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_PC_CAL_TIMER_P3                            , RULL(0x8000C00707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_PC_CAL_TIMER_P3                            , RULL(0x8000C00708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0                 , RULL(0x8000C0080701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0               , RULL(0x8000C0080701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0               , RULL(0x8000C0080801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P1               , RULL(0x8000C0080701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P1               , RULL(0x8000C0080801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P2               , RULL(0x8000C0080701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P2               , RULL(0x8000C0080801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P3               , RULL(0x8000C00807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P3               , RULL(0x8000C00808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_CONFIG0_P0                                , RULL(0x8000C00C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_CONFIG0_P0                              , RULL(0x8000C00C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_CONFIG0_P0                              , RULL(0x8000C00C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_CONFIG0_P1                              , RULL(0x8000C00C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_CONFIG0_P1                              , RULL(0x8000C00C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_CONFIG0_P2                              , RULL(0x8000C00C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_CONFIG0_P2                              , RULL(0x8000C00C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_CONFIG0_P3                              , RULL(0x8000C00C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_CONFIG0_P3                              , RULL(0x8000C00C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_CONFIG1_P0                                , RULL(0x8000C00D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_CONFIG1_P0                              , RULL(0x8000C00D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_CONFIG1_P0                              , RULL(0x8000C00D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_CONFIG1_P1                              , RULL(0x8000C00D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_CONFIG1_P1                              , RULL(0x8000C00D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_CONFIG1_P2                              , RULL(0x8000C00D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_CONFIG1_P2                              , RULL(0x8000C00D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_CONFIG1_P3                              , RULL(0x8000C00D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_CONFIG1_P3                              , RULL(0x8000C00D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_CSID_CFG_P0                               , RULL(0x8000C0330701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_CSID_CFG_P0                             , RULL(0x8000C0330701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_CSID_CFG_P0                             , RULL(0x8000C0330801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_CSID_CFG_P1                             , RULL(0x8000C0330701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_CSID_CFG_P1                             , RULL(0x8000C0330801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_CSID_CFG_P2                             , RULL(0x8000C0330701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_CSID_CFG_P2                             , RULL(0x8000C0330801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_CSID_CFG_P3                             , RULL(0x8000C03307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_CSID_CFG_P3                             , RULL(0x8000C03308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0                    , RULL(0x8000C0000701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0                  , RULL(0x8000C0000701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0                  , RULL(0x8000C0000801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P1                  , RULL(0x8000C0000701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P1                  , RULL(0x8000C0000801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P2                  , RULL(0x8000C0000701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P2                  , RULL(0x8000C0000801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P3                  , RULL(0x8000C00007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P3                  , RULL(0x8000C00008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_PC_ERROR_MASK0_P0                            , RULL(0x8000C0130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_ERROR_MASK0_P0                          , RULL(0x8000C0130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_ERROR_MASK0_P0                          , RULL(0x8000C0130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_ERROR_MASK0_P1                          , RULL(0x8000C0130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_ERROR_MASK0_P1                          , RULL(0x8000C0130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_ERROR_MASK0_P2                          , RULL(0x8000C0130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_ERROR_MASK0_P2                          , RULL(0x8000C0130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_ERROR_MASK0_P3                          , RULL(0x8000C01307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_ERROR_MASK0_P3                          , RULL(0x8000C01308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_ERROR_STATUS0_P0                          , RULL(0x8000C0120701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_PC_ERROR_STATUS0_P0                        , RULL(0x8000C0120701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_PC_ERROR_STATUS0_P0                        , RULL(0x8000C0120801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_PC_ERROR_STATUS0_P1                        , RULL(0x8000C0120701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_PC_ERROR_STATUS0_P1                        , RULL(0x8000C0120801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_PC_ERROR_STATUS0_P2                        , RULL(0x8000C0120701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_PC_ERROR_STATUS0_P2                        , RULL(0x8000C0120801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_PC_ERROR_STATUS0_P3                        , RULL(0x8000C01207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_PC_ERROR_STATUS0_P3                        , RULL(0x8000C01208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0                       , RULL(0x8000C0160701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_INIT_CAL_CONFIG0_P0                     , RULL(0x8000C0160701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_INIT_CAL_CONFIG0_P0                     , RULL(0x8000C0160801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_INIT_CAL_CONFIG0_P1                     , RULL(0x8000C0160701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_INIT_CAL_CONFIG0_P1                     , RULL(0x8000C0160801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_INIT_CAL_CONFIG0_P2                     , RULL(0x8000C0160701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_INIT_CAL_CONFIG0_P2                     , RULL(0x8000C0160801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_INIT_CAL_CONFIG0_P3                     , RULL(0x8000C01607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_INIT_CAL_CONFIG0_P3                     , RULL(0x8000C01608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0                       , RULL(0x8000C0170701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_INIT_CAL_CONFIG1_P0                     , RULL(0x8000C0170701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_INIT_CAL_CONFIG1_P0                     , RULL(0x8000C0170801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_INIT_CAL_CONFIG1_P1                     , RULL(0x8000C0170701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_INIT_CAL_CONFIG1_P1                     , RULL(0x8000C0170801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_INIT_CAL_CONFIG1_P2                     , RULL(0x8000C0170701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_INIT_CAL_CONFIG1_P2                     , RULL(0x8000C0170801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_INIT_CAL_CONFIG1_P3                     , RULL(0x8000C01707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_INIT_CAL_CONFIG1_P3                     , RULL(0x8000C01708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0                         , RULL(0x8000C0180701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_PC_INIT_CAL_ERROR_P0                       , RULL(0x8000C0180701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_PC_INIT_CAL_ERROR_P0                       , RULL(0x8000C0180801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_PC_INIT_CAL_ERROR_P1                       , RULL(0x8000C0180701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_PC_INIT_CAL_ERROR_P1                       , RULL(0x8000C0180801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_PC_INIT_CAL_ERROR_P2                       , RULL(0x8000C0180701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_PC_INIT_CAL_ERROR_P2                       , RULL(0x8000C0180801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_PC_INIT_CAL_ERROR_P3                       , RULL(0x8000C01807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_PC_INIT_CAL_ERROR_P3                       , RULL(0x8000C01808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_PC_INIT_CAL_MASK_P0                          , RULL(0x8000C01A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_INIT_CAL_MASK_P0                        , RULL(0x8000C01A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_INIT_CAL_MASK_P0                        , RULL(0x8000C01A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_INIT_CAL_MASK_P1                        , RULL(0x8000C01A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_INIT_CAL_MASK_P1                        , RULL(0x8000C01A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_INIT_CAL_MASK_P2                        , RULL(0x8000C01A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_INIT_CAL_MASK_P2                        , RULL(0x8000C01A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_INIT_CAL_MASK_P3                        , RULL(0x8000C01A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_INIT_CAL_MASK_P3                        , RULL(0x8000C01A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_INIT_CAL_STATUS_P0                        , RULL(0x8000C0190701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_PC_INIT_CAL_STATUS_P0                      , RULL(0x8000C0190701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_PC_INIT_CAL_STATUS_P0                      , RULL(0x8000C0190801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_PC_INIT_CAL_STATUS_P1                      , RULL(0x8000C0190701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_PC_INIT_CAL_STATUS_P1                      , RULL(0x8000C0190801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_PC_INIT_CAL_STATUS_P2                      , RULL(0x8000C0190701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_PC_INIT_CAL_STATUS_P2                      , RULL(0x8000C0190801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_PC_INIT_CAL_STATUS_P3                      , RULL(0x8000C01907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_PC_INIT_CAL_STATUS_P3                      , RULL(0x8000C01908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0                     , RULL(0x8000C0140701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_IO_PVT_FET_CONTROL_P0                   , RULL(0x8000C0140701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_IO_PVT_FET_CONTROL_P0                   , RULL(0x8000C0140801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_IO_PVT_FET_CONTROL_P1                   , RULL(0x8000C0140701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_IO_PVT_FET_CONTROL_P1                   , RULL(0x8000C0140801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_IO_PVT_FET_CONTROL_P2                   , RULL(0x8000C0140701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_IO_PVT_FET_CONTROL_P2                   , RULL(0x8000C0140801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_IO_PVT_FET_CONTROL_P3                   , RULL(0x8000C01407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_IO_PVT_FET_CONTROL_P3                   , RULL(0x8000C01408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0                      , RULL(0x8000C01B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_PC_IO_PVT_FET_STATUS_P0                    , RULL(0x8000C01B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_PC_IO_PVT_FET_STATUS_P0                    , RULL(0x8000C01B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_PC_IO_PVT_FET_STATUS_P1                    , RULL(0x8000C01B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_PC_IO_PVT_FET_STATUS_P1                    , RULL(0x8000C01B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_PC_IO_PVT_FET_STATUS_P2                    , RULL(0x8000C01B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_PC_IO_PVT_FET_STATUS_P2                    , RULL(0x8000C01B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_PC_IO_PVT_FET_STATUS_P3                    , RULL(0x8000C01B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_PC_IO_PVT_FET_STATUS_P3                    , RULL(0x8000C01B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_PC_MR0_PRI_RP0_P0                            , RULL(0x8000C01C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR0_PRI_RP0_P0                          , RULL(0x8000C01C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR0_PRI_RP0_P0                          , RULL(0x8000C01C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR0_PRI_RP0_P1                          , RULL(0x8000C01C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR0_PRI_RP0_P1                          , RULL(0x8000C01C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR0_PRI_RP0_P2                          , RULL(0x8000C01C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR0_PRI_RP0_P2                          , RULL(0x8000C01C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR0_PRI_RP0_P3                          , RULL(0x8000C01C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR0_PRI_RP0_P3                          , RULL(0x8000C01C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR0_PRI_RP1_P0                            , RULL(0x8000C11C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR0_PRI_RP1_P0                          , RULL(0x8000C11C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR0_PRI_RP1_P0                          , RULL(0x8000C11C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR0_PRI_RP1_P1                          , RULL(0x8000C11C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR0_PRI_RP1_P1                          , RULL(0x8000C11C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR0_PRI_RP1_P2                          , RULL(0x8000C11C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR0_PRI_RP1_P2                          , RULL(0x8000C11C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR0_PRI_RP1_P3                          , RULL(0x8000C11C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR0_PRI_RP1_P3                          , RULL(0x8000C11C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR0_PRI_RP2_P0                            , RULL(0x8000C21C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR0_PRI_RP2_P0                          , RULL(0x8000C21C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR0_PRI_RP2_P0                          , RULL(0x8000C21C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR0_PRI_RP2_P1                          , RULL(0x8000C21C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR0_PRI_RP2_P1                          , RULL(0x8000C21C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR0_PRI_RP2_P2                          , RULL(0x8000C21C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR0_PRI_RP2_P2                          , RULL(0x8000C21C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR0_PRI_RP2_P3                          , RULL(0x8000C21C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR0_PRI_RP2_P3                          , RULL(0x8000C21C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR0_PRI_RP3_P0                            , RULL(0x8000C31C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR0_PRI_RP3_P0                          , RULL(0x8000C31C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR0_PRI_RP3_P0                          , RULL(0x8000C31C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR0_PRI_RP3_P1                          , RULL(0x8000C31C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR0_PRI_RP3_P1                          , RULL(0x8000C31C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR0_PRI_RP3_P2                          , RULL(0x8000C31C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR0_PRI_RP3_P2                          , RULL(0x8000C31C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR0_PRI_RP3_P3                          , RULL(0x8000C31C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR0_PRI_RP3_P3                          , RULL(0x8000C31C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR0_SEC_RP0_P0                            , RULL(0x8000C0200701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR0_SEC_RP0_P0                          , RULL(0x8000C0200701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR0_SEC_RP0_P0                          , RULL(0x8000C0200801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR0_SEC_RP0_P1                          , RULL(0x8000C0200701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR0_SEC_RP0_P1                          , RULL(0x8000C0200801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR0_SEC_RP0_P2                          , RULL(0x8000C0200701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR0_SEC_RP0_P2                          , RULL(0x8000C0200801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR0_SEC_RP0_P3                          , RULL(0x8000C02007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR0_SEC_RP0_P3                          , RULL(0x8000C02008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR0_SEC_RP1_P0                            , RULL(0x8000C1200701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR0_SEC_RP1_P0                          , RULL(0x8000C1200701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR0_SEC_RP1_P0                          , RULL(0x8000C1200801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR0_SEC_RP1_P1                          , RULL(0x8000C1200701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR0_SEC_RP1_P1                          , RULL(0x8000C1200801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR0_SEC_RP1_P2                          , RULL(0x8000C1200701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR0_SEC_RP1_P2                          , RULL(0x8000C1200801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR0_SEC_RP1_P3                          , RULL(0x8000C12007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR0_SEC_RP1_P3                          , RULL(0x8000C12008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR0_SEC_RP2_P0                            , RULL(0x8000C2200701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR0_SEC_RP2_P0                          , RULL(0x8000C2200701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR0_SEC_RP2_P0                          , RULL(0x8000C2200801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR0_SEC_RP2_P1                          , RULL(0x8000C2200701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR0_SEC_RP2_P1                          , RULL(0x8000C2200801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR0_SEC_RP2_P2                          , RULL(0x8000C2200701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR0_SEC_RP2_P2                          , RULL(0x8000C2200801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR0_SEC_RP2_P3                          , RULL(0x8000C22007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR0_SEC_RP2_P3                          , RULL(0x8000C22008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR0_SEC_RP3_P0                            , RULL(0x8000C3200701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR0_SEC_RP3_P0                          , RULL(0x8000C3200701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR0_SEC_RP3_P0                          , RULL(0x8000C3200801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR0_SEC_RP3_P1                          , RULL(0x8000C3200701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR0_SEC_RP3_P1                          , RULL(0x8000C3200801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR0_SEC_RP3_P2                          , RULL(0x8000C3200701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR0_SEC_RP3_P2                          , RULL(0x8000C3200801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR0_SEC_RP3_P3                          , RULL(0x8000C32007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR0_SEC_RP3_P3                          , RULL(0x8000C32008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR1_PRI_RP0_P0                            , RULL(0x8000C01D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR1_PRI_RP0_P0                          , RULL(0x8000C01D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR1_PRI_RP0_P0                          , RULL(0x8000C01D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR1_PRI_RP0_P1                          , RULL(0x8000C01D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR1_PRI_RP0_P1                          , RULL(0x8000C01D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR1_PRI_RP0_P2                          , RULL(0x8000C01D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR1_PRI_RP0_P2                          , RULL(0x8000C01D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR1_PRI_RP0_P3                          , RULL(0x8000C01D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR1_PRI_RP0_P3                          , RULL(0x8000C01D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR1_PRI_RP1_P0                            , RULL(0x8000C11D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR1_PRI_RP1_P0                          , RULL(0x8000C11D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR1_PRI_RP1_P0                          , RULL(0x8000C11D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR1_PRI_RP1_P1                          , RULL(0x8000C11D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR1_PRI_RP1_P1                          , RULL(0x8000C11D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR1_PRI_RP1_P2                          , RULL(0x8000C11D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR1_PRI_RP1_P2                          , RULL(0x8000C11D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR1_PRI_RP1_P3                          , RULL(0x8000C11D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR1_PRI_RP1_P3                          , RULL(0x8000C11D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR1_PRI_RP2_P0                            , RULL(0x8000C21D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR1_PRI_RP2_P0                          , RULL(0x8000C21D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR1_PRI_RP2_P0                          , RULL(0x8000C21D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR1_PRI_RP2_P1                          , RULL(0x8000C21D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR1_PRI_RP2_P1                          , RULL(0x8000C21D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR1_PRI_RP2_P2                          , RULL(0x8000C21D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR1_PRI_RP2_P2                          , RULL(0x8000C21D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR1_PRI_RP2_P3                          , RULL(0x8000C21D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR1_PRI_RP2_P3                          , RULL(0x8000C21D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR1_PRI_RP3_P0                            , RULL(0x8000C31D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR1_PRI_RP3_P0                          , RULL(0x8000C31D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR1_PRI_RP3_P0                          , RULL(0x8000C31D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR1_PRI_RP3_P1                          , RULL(0x8000C31D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR1_PRI_RP3_P1                          , RULL(0x8000C31D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR1_PRI_RP3_P2                          , RULL(0x8000C31D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR1_PRI_RP3_P2                          , RULL(0x8000C31D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR1_PRI_RP3_P3                          , RULL(0x8000C31D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR1_PRI_RP3_P3                          , RULL(0x8000C31D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR1_SEC_RP0_P0                            , RULL(0x8000C0210701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR1_SEC_RP0_P0                          , RULL(0x8000C0210701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR1_SEC_RP0_P0                          , RULL(0x8000C0210801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR1_SEC_RP0_P1                          , RULL(0x8000C0210701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR1_SEC_RP0_P1                          , RULL(0x8000C0210801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR1_SEC_RP0_P2                          , RULL(0x8000C0210701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR1_SEC_RP0_P2                          , RULL(0x8000C0210801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR1_SEC_RP0_P3                          , RULL(0x8000C02107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR1_SEC_RP0_P3                          , RULL(0x8000C02108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR1_SEC_RP1_P0                            , RULL(0x8000C1210701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR1_SEC_RP1_P0                          , RULL(0x8000C1210701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR1_SEC_RP1_P0                          , RULL(0x8000C1210801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR1_SEC_RP1_P1                          , RULL(0x8000C1210701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR1_SEC_RP1_P1                          , RULL(0x8000C1210801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR1_SEC_RP1_P2                          , RULL(0x8000C1210701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR1_SEC_RP1_P2                          , RULL(0x8000C1210801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR1_SEC_RP1_P3                          , RULL(0x8000C12107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR1_SEC_RP1_P3                          , RULL(0x8000C12108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR1_SEC_RP2_P0                            , RULL(0x8000C2210701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR1_SEC_RP2_P0                          , RULL(0x8000C2210701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR1_SEC_RP2_P0                          , RULL(0x8000C2210801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR1_SEC_RP2_P1                          , RULL(0x8000C2210701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR1_SEC_RP2_P1                          , RULL(0x8000C2210801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR1_SEC_RP2_P2                          , RULL(0x8000C2210701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR1_SEC_RP2_P2                          , RULL(0x8000C2210801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR1_SEC_RP2_P3                          , RULL(0x8000C22107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR1_SEC_RP2_P3                          , RULL(0x8000C22108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR1_SEC_RP3_P0                            , RULL(0x8000C3210701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR1_SEC_RP3_P0                          , RULL(0x8000C3210701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR1_SEC_RP3_P0                          , RULL(0x8000C3210801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR1_SEC_RP3_P1                          , RULL(0x8000C3210701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR1_SEC_RP3_P1                          , RULL(0x8000C3210801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR1_SEC_RP3_P2                          , RULL(0x8000C3210701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR1_SEC_RP3_P2                          , RULL(0x8000C3210801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR1_SEC_RP3_P3                          , RULL(0x8000C32107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR1_SEC_RP3_P3                          , RULL(0x8000C32108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR2_PRI_RP0_P0                            , RULL(0x8000C01E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR2_PRI_RP0_P0                          , RULL(0x8000C01E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR2_PRI_RP0_P0                          , RULL(0x8000C01E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR2_PRI_RP0_P1                          , RULL(0x8000C01E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR2_PRI_RP0_P1                          , RULL(0x8000C01E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR2_PRI_RP0_P2                          , RULL(0x8000C01E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR2_PRI_RP0_P2                          , RULL(0x8000C01E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR2_PRI_RP0_P3                          , RULL(0x8000C01E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR2_PRI_RP0_P3                          , RULL(0x8000C01E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR2_PRI_RP1_P0                            , RULL(0x8000C11E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR2_PRI_RP1_P0                          , RULL(0x8000C11E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR2_PRI_RP1_P0                          , RULL(0x8000C11E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR2_PRI_RP1_P1                          , RULL(0x8000C11E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR2_PRI_RP1_P1                          , RULL(0x8000C11E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR2_PRI_RP1_P2                          , RULL(0x8000C11E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR2_PRI_RP1_P2                          , RULL(0x8000C11E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR2_PRI_RP1_P3                          , RULL(0x8000C11E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR2_PRI_RP1_P3                          , RULL(0x8000C11E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR2_PRI_RP2_P0                            , RULL(0x8000C21E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR2_PRI_RP2_P0                          , RULL(0x8000C21E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR2_PRI_RP2_P0                          , RULL(0x8000C21E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR2_PRI_RP2_P1                          , RULL(0x8000C21E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR2_PRI_RP2_P1                          , RULL(0x8000C21E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR2_PRI_RP2_P2                          , RULL(0x8000C21E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR2_PRI_RP2_P2                          , RULL(0x8000C21E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR2_PRI_RP2_P3                          , RULL(0x8000C21E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR2_PRI_RP2_P3                          , RULL(0x8000C21E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR2_PRI_RP3_P0                            , RULL(0x8000C31E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR2_PRI_RP3_P0                          , RULL(0x8000C31E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR2_PRI_RP3_P0                          , RULL(0x8000C31E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR2_PRI_RP3_P1                          , RULL(0x8000C31E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR2_PRI_RP3_P1                          , RULL(0x8000C31E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR2_PRI_RP3_P2                          , RULL(0x8000C31E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR2_PRI_RP3_P2                          , RULL(0x8000C31E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR2_PRI_RP3_P3                          , RULL(0x8000C31E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR2_PRI_RP3_P3                          , RULL(0x8000C31E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR2_SEC_RP0_P0                            , RULL(0x8000C0220701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR2_SEC_RP0_P0                          , RULL(0x8000C0220701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR2_SEC_RP0_P0                          , RULL(0x8000C0220801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR2_SEC_RP0_P1                          , RULL(0x8000C0220701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR2_SEC_RP0_P1                          , RULL(0x8000C0220801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR2_SEC_RP0_P2                          , RULL(0x8000C0220701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR2_SEC_RP0_P2                          , RULL(0x8000C0220801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR2_SEC_RP0_P3                          , RULL(0x8000C02207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR2_SEC_RP0_P3                          , RULL(0x8000C02208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR2_SEC_RP1_P0                            , RULL(0x8000C1220701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR2_SEC_RP1_P0                          , RULL(0x8000C1220701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR2_SEC_RP1_P0                          , RULL(0x8000C1220801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR2_SEC_RP1_P1                          , RULL(0x8000C1220701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR2_SEC_RP1_P1                          , RULL(0x8000C1220801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR2_SEC_RP1_P2                          , RULL(0x8000C1220701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR2_SEC_RP1_P2                          , RULL(0x8000C1220801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR2_SEC_RP1_P3                          , RULL(0x8000C12207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR2_SEC_RP1_P3                          , RULL(0x8000C12208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR2_SEC_RP2_P0                            , RULL(0x8000C2220701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR2_SEC_RP2_P0                          , RULL(0x8000C2220701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR2_SEC_RP2_P0                          , RULL(0x8000C2220801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR2_SEC_RP2_P1                          , RULL(0x8000C2220701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR2_SEC_RP2_P1                          , RULL(0x8000C2220801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR2_SEC_RP2_P2                          , RULL(0x8000C2220701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR2_SEC_RP2_P2                          , RULL(0x8000C2220801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR2_SEC_RP2_P3                          , RULL(0x8000C22207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR2_SEC_RP2_P3                          , RULL(0x8000C22208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR2_SEC_RP3_P0                            , RULL(0x8000C3220701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR2_SEC_RP3_P0                          , RULL(0x8000C3220701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR2_SEC_RP3_P0                          , RULL(0x8000C3220801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR2_SEC_RP3_P1                          , RULL(0x8000C3220701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR2_SEC_RP3_P1                          , RULL(0x8000C3220801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR2_SEC_RP3_P2                          , RULL(0x8000C3220701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR2_SEC_RP3_P2                          , RULL(0x8000C3220801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR2_SEC_RP3_P3                          , RULL(0x8000C32207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR2_SEC_RP3_P3                          , RULL(0x8000C32208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR3_PRI_RP0_P0                            , RULL(0x8000C01F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR3_PRI_RP0_P0                          , RULL(0x8000C01F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR3_PRI_RP0_P0                          , RULL(0x8000C01F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR3_PRI_RP0_P1                          , RULL(0x8000C01F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR3_PRI_RP0_P1                          , RULL(0x8000C01F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR3_PRI_RP0_P2                          , RULL(0x8000C01F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR3_PRI_RP0_P2                          , RULL(0x8000C01F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR3_PRI_RP0_P3                          , RULL(0x8000C01F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR3_PRI_RP0_P3                          , RULL(0x8000C01F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR3_PRI_RP1_P0                            , RULL(0x8000C11F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR3_PRI_RP1_P0                          , RULL(0x8000C11F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR3_PRI_RP1_P0                          , RULL(0x8000C11F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR3_PRI_RP1_P1                          , RULL(0x8000C11F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR3_PRI_RP1_P1                          , RULL(0x8000C11F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR3_PRI_RP1_P2                          , RULL(0x8000C11F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR3_PRI_RP1_P2                          , RULL(0x8000C11F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR3_PRI_RP1_P3                          , RULL(0x8000C11F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR3_PRI_RP1_P3                          , RULL(0x8000C11F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR3_PRI_RP2_P0                            , RULL(0x8000C21F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR3_PRI_RP2_P0                          , RULL(0x8000C21F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR3_PRI_RP2_P0                          , RULL(0x8000C21F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR3_PRI_RP2_P1                          , RULL(0x8000C21F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR3_PRI_RP2_P1                          , RULL(0x8000C21F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR3_PRI_RP2_P2                          , RULL(0x8000C21F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR3_PRI_RP2_P2                          , RULL(0x8000C21F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR3_PRI_RP2_P3                          , RULL(0x8000C21F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR3_PRI_RP2_P3                          , RULL(0x8000C21F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR3_PRI_RP3_P0                            , RULL(0x8000C31F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR3_PRI_RP3_P0                          , RULL(0x8000C31F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR3_PRI_RP3_P0                          , RULL(0x8000C31F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR3_PRI_RP3_P1                          , RULL(0x8000C31F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR3_PRI_RP3_P1                          , RULL(0x8000C31F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR3_PRI_RP3_P2                          , RULL(0x8000C31F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR3_PRI_RP3_P2                          , RULL(0x8000C31F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR3_PRI_RP3_P3                          , RULL(0x8000C31F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR3_PRI_RP3_P3                          , RULL(0x8000C31F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR3_SEC_RP0_P0                            , RULL(0x8000C0230701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR3_SEC_RP0_P0                          , RULL(0x8000C0230701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR3_SEC_RP0_P0                          , RULL(0x8000C0230801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR3_SEC_RP0_P1                          , RULL(0x8000C0230701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR3_SEC_RP0_P1                          , RULL(0x8000C0230801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR3_SEC_RP0_P2                          , RULL(0x8000C0230701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR3_SEC_RP0_P2                          , RULL(0x8000C0230801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR3_SEC_RP0_P3                          , RULL(0x8000C02307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR3_SEC_RP0_P3                          , RULL(0x8000C02308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR3_SEC_RP1_P0                            , RULL(0x8000C1230701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR3_SEC_RP1_P0                          , RULL(0x8000C1230701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR3_SEC_RP1_P0                          , RULL(0x8000C1230801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR3_SEC_RP1_P1                          , RULL(0x8000C1230701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR3_SEC_RP1_P1                          , RULL(0x8000C1230801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR3_SEC_RP1_P2                          , RULL(0x8000C1230701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR3_SEC_RP1_P2                          , RULL(0x8000C1230801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR3_SEC_RP1_P3                          , RULL(0x8000C12307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR3_SEC_RP1_P3                          , RULL(0x8000C12308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR3_SEC_RP2_P0                            , RULL(0x8000C2230701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR3_SEC_RP2_P0                          , RULL(0x8000C2230701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR3_SEC_RP2_P0                          , RULL(0x8000C2230801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR3_SEC_RP2_P1                          , RULL(0x8000C2230701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR3_SEC_RP2_P1                          , RULL(0x8000C2230801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR3_SEC_RP2_P2                          , RULL(0x8000C2230701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR3_SEC_RP2_P2                          , RULL(0x8000C2230801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR3_SEC_RP2_P3                          , RULL(0x8000C22307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR3_SEC_RP2_P3                          , RULL(0x8000C22308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_MR3_SEC_RP3_P0                            , RULL(0x8000C3230701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_MR3_SEC_RP3_P0                          , RULL(0x8000C3230701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_MR3_SEC_RP3_P0                          , RULL(0x8000C3230801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_MR3_SEC_RP3_P1                          , RULL(0x8000C3230701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_MR3_SEC_RP3_P1                          , RULL(0x8000C3230801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_MR3_SEC_RP3_P2                          , RULL(0x8000C3230701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_MR3_SEC_RP3_P2                          , RULL(0x8000C3230801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_MR3_SEC_RP3_P3                          , RULL(0x8000C32307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_MR3_SEC_RP3_P3                          , RULL(0x8000C32308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0                         , RULL(0x8000C00B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_PER_CAL_CONFIG_P0                       , RULL(0x8000C00B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_PER_CAL_CONFIG_P0                       , RULL(0x8000C00B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_PER_CAL_CONFIG_P1                       , RULL(0x8000C00B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_PER_CAL_CONFIG_P1                       , RULL(0x8000C00B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_PER_CAL_CONFIG_P2                       , RULL(0x8000C00B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_PER_CAL_CONFIG_P2                       , RULL(0x8000C00B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_PER_CAL_CONFIG_P3                       , RULL(0x8000C00B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_PER_CAL_CONFIG_P3                       , RULL(0x8000C00B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0                        , RULL(0x8000C00F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_PER_ZCAL_CONFIG_P0                      , RULL(0x8000C00F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_PER_ZCAL_CONFIG_P0                      , RULL(0x8000C00F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_PER_ZCAL_CONFIG_P1                      , RULL(0x8000C00F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_PER_ZCAL_CONFIG_P1                      , RULL(0x8000C00F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_PER_ZCAL_CONFIG_P2                      , RULL(0x8000C00F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_PER_ZCAL_CONFIG_P2                      , RULL(0x8000C00F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_PER_ZCAL_CONFIG_P3                      , RULL(0x8000C00F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_PER_ZCAL_CONFIG_P3                      , RULL(0x8000C00F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_POWERDOWN_1_P0                            , RULL(0x8000C0100701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_POWERDOWN_1_P0                          , RULL(0x8000C0100701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_POWERDOWN_1_P0                          , RULL(0x8000C0100801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_POWERDOWN_1_P1                          , RULL(0x8000C0100701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_POWERDOWN_1_P1                          , RULL(0x8000C0100801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_POWERDOWN_1_P2                          , RULL(0x8000C0100701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_POWERDOWN_1_P2                          , RULL(0x8000C0100801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_POWERDOWN_1_P3                          , RULL(0x8000C01007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_POWERDOWN_1_P3                          , RULL(0x8000C01008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0                         , RULL(0x8000C0350701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_RANK_GROUP_EXT_P0                       , RULL(0x8000C0350701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_RANK_GROUP_EXT_P0                       , RULL(0x8000C0350801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_RANK_GROUP_EXT_P1                       , RULL(0x8000C0350701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_RANK_GROUP_EXT_P1                       , RULL(0x8000C0350801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_RANK_GROUP_EXT_P2                       , RULL(0x8000C0350701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_RANK_GROUP_EXT_P2                       , RULL(0x8000C0350801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_RANK_GROUP_EXT_P3                       , RULL(0x8000C03507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_RANK_GROUP_EXT_P3                       , RULL(0x8000C03508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_RANK_GROUP_P0                             , RULL(0x8000C0110701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_RANK_GROUP_P0                           , RULL(0x8000C0110701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_RANK_GROUP_P0                           , RULL(0x8000C0110801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_RANK_GROUP_P1                           , RULL(0x8000C0110701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_RANK_GROUP_P1                           , RULL(0x8000C0110801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_RANK_GROUP_P2                           , RULL(0x8000C0110701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_RANK_GROUP_P2                           , RULL(0x8000C0110801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_RANK_GROUP_P3                           , RULL(0x8000C01107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_RANK_GROUP_P3                           , RULL(0x8000C01108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_RANK_PAIR0_P0                             , RULL(0x8000C0020701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_RANK_PAIR0_P0                           , RULL(0x8000C0020701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_RANK_PAIR0_P0                           , RULL(0x8000C0020801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_RANK_PAIR0_P1                           , RULL(0x8000C0020701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_RANK_PAIR0_P1                           , RULL(0x8000C0020801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_RANK_PAIR0_P2                           , RULL(0x8000C0020701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_RANK_PAIR0_P2                           , RULL(0x8000C0020801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_RANK_PAIR0_P3                           , RULL(0x8000C00207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_RANK_PAIR0_P3                           , RULL(0x8000C00208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_RANK_PAIR1_P0                             , RULL(0x8000C0030701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_RANK_PAIR1_P0                           , RULL(0x8000C0030701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_RANK_PAIR1_P0                           , RULL(0x8000C0030801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_RANK_PAIR1_P1                           , RULL(0x8000C0030701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_RANK_PAIR1_P1                           , RULL(0x8000C0030801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_RANK_PAIR1_P2                           , RULL(0x8000C0030701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_RANK_PAIR1_P2                           , RULL(0x8000C0030801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_RANK_PAIR1_P3                           , RULL(0x8000C00307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_RANK_PAIR1_P3                           , RULL(0x8000C00308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_RANK_PAIR2_P0                             , RULL(0x8000C0300701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_RANK_PAIR2_P0                           , RULL(0x8000C0300701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_RANK_PAIR2_P0                           , RULL(0x8000C0300801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_RANK_PAIR2_P1                           , RULL(0x8000C0300701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_RANK_PAIR2_P1                           , RULL(0x8000C0300801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_RANK_PAIR2_P2                           , RULL(0x8000C0300701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_RANK_PAIR2_P2                           , RULL(0x8000C0300801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_RANK_PAIR2_P3                           , RULL(0x8000C03007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_RANK_PAIR2_P3                           , RULL(0x8000C03008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_RANK_PAIR3_P0                             , RULL(0x8000C0310701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_RANK_PAIR3_P0                           , RULL(0x8000C0310701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_RANK_PAIR3_P0                           , RULL(0x8000C0310801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_RANK_PAIR3_P1                           , RULL(0x8000C0310701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_RANK_PAIR3_P1                           , RULL(0x8000C0310801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_RANK_PAIR3_P2                           , RULL(0x8000C0310701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_RANK_PAIR3_P2                           , RULL(0x8000C0310801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_RANK_PAIR3_P3                           , RULL(0x8000C03107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_RANK_PAIR3_P3                           , RULL(0x8000C03108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_RELOAD_VALUE0_P0                          , RULL(0x8000C0050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_RELOAD_VALUE0_P0                        , RULL(0x8000C0050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_RELOAD_VALUE0_P0                        , RULL(0x8000C0050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_RELOAD_VALUE0_P1                        , RULL(0x8000C0050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_RELOAD_VALUE0_P1                        , RULL(0x8000C0050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_RELOAD_VALUE0_P2                        , RULL(0x8000C0050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_RELOAD_VALUE0_P2                        , RULL(0x8000C0050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_RELOAD_VALUE0_P3                        , RULL(0x8000C00507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_RELOAD_VALUE0_P3                        , RULL(0x8000C00508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_RESETS_P0                                 , RULL(0x8000C00E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_RESETS_P0                               , RULL(0x8000C00E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_RESETS_P0                               , RULL(0x8000C00E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_RESETS_P1                               , RULL(0x8000C00E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_RESETS_P1                               , RULL(0x8000C00E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_RESETS_P2                               , RULL(0x8000C00E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_RESETS_P2                               , RULL(0x8000C00E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_RESETS_P3                               , RULL(0x8000C00E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_RESETS_P3                               , RULL(0x8000C00E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_VREF_DRV_CONTROL_P0                       , RULL(0x8000C0150701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_VREF_DRV_CONTROL_P0                     , RULL(0x8000C0150701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_VREF_DRV_CONTROL_P0                     , RULL(0x8000C0150801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_VREF_DRV_CONTROL_P1                     , RULL(0x8000C0150701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_VREF_DRV_CONTROL_P1                     , RULL(0x8000C0150801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_VREF_DRV_CONTROL_P2                     , RULL(0x8000C0150701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_VREF_DRV_CONTROL_P2                     , RULL(0x8000C0150801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_VREF_DRV_CONTROL_P3                     , RULL(0x8000C01507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_VREF_DRV_CONTROL_P3                     , RULL(0x8000C01508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_PC_ZCAL_TIMER_P0                             , RULL(0x8000C0090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_PC_ZCAL_TIMER_P0                           , RULL(0x8000C0090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_PC_ZCAL_TIMER_P0                           , RULL(0x8000C0090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_PC_ZCAL_TIMER_P1                           , RULL(0x8000C0090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_PC_ZCAL_TIMER_P1                           , RULL(0x8000C0090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_PC_ZCAL_TIMER_P2                           , RULL(0x8000C0090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_PC_ZCAL_TIMER_P2                           , RULL(0x8000C0090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_PC_ZCAL_TIMER_P3                           , RULL(0x8000C00907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_PC_ZCAL_TIMER_P3                           , RULL(0x8000C00908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0                , RULL(0x8000C00A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0              , RULL(0x8000C00A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0              , RULL(0x8000C00A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P1              , RULL(0x8000C00A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P1              , RULL(0x8000C00A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P2              , RULL(0x8000C00A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P2              , RULL(0x8000C00A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P3              , RULL(0x8000C00A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P3              , RULL(0x8000C00A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_RC_CONFIG0_P0                                , RULL(0x8000C8000701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_RC_CONFIG0_P0                              , RULL(0x8000C8000701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_RC_CONFIG0_P0                              , RULL(0x8000C8000801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_RC_CONFIG0_P1                              , RULL(0x8000C8000701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_RC_CONFIG0_P1                              , RULL(0x8000C8000801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_RC_CONFIG0_P2                              , RULL(0x8000C8000701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_RC_CONFIG0_P2                              , RULL(0x8000C8000801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_RC_CONFIG0_P3                              , RULL(0x8000C80007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_RC_CONFIG0_P3                              , RULL(0x8000C80008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_RC_CONFIG1_P0                                , RULL(0x8000C8010701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_RC_CONFIG1_P0                              , RULL(0x8000C8010701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_RC_CONFIG1_P0                              , RULL(0x8000C8010801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_RC_CONFIG1_P1                              , RULL(0x8000C8010701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_RC_CONFIG1_P1                              , RULL(0x8000C8010801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_RC_CONFIG1_P2                              , RULL(0x8000C8010701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_RC_CONFIG1_P2                              , RULL(0x8000C8010801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_RC_CONFIG1_P3                              , RULL(0x8000C80107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_RC_CONFIG1_P3                              , RULL(0x8000C80108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_RC_CONFIG2_P0                                , RULL(0x8000C8020701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_RC_CONFIG2_P0                              , RULL(0x8000C8020701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_RC_CONFIG2_P0                              , RULL(0x8000C8020801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_RC_CONFIG2_P1                              , RULL(0x8000C8020701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_RC_CONFIG2_P1                              , RULL(0x8000C8020801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_RC_CONFIG2_P2                              , RULL(0x8000C8020701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_RC_CONFIG2_P2                              , RULL(0x8000C8020801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_RC_CONFIG2_P3                              , RULL(0x8000C80207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_RC_CONFIG2_P3                              , RULL(0x8000C80208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_RC_CONFIG3_P0                                , RULL(0x8000C8070701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_RC_CONFIG3_P0                              , RULL(0x8000C8070701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_RC_CONFIG3_P0                              , RULL(0x8000C8070801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_RC_CONFIG3_P1                              , RULL(0x8000C8070701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_RC_CONFIG3_P1                              , RULL(0x8000C8070801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_RC_CONFIG3_P2                              , RULL(0x8000C8070701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_RC_CONFIG3_P2                              , RULL(0x8000C8070801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_RC_CONFIG3_P3                              , RULL(0x8000C80707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_RC_CONFIG3_P3                              , RULL(0x8000C80708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_RC_ERROR_MASK0_P0                            , RULL(0x8000C8060701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_RC_ERROR_MASK0_P0                          , RULL(0x8000C8060701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_RC_ERROR_MASK0_P0                          , RULL(0x8000C8060801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_RC_ERROR_MASK0_P1                          , RULL(0x8000C8060701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_RC_ERROR_MASK0_P1                          , RULL(0x8000C8060801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_RC_ERROR_MASK0_P2                          , RULL(0x8000C8060701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_RC_ERROR_MASK0_P2                          , RULL(0x8000C8060801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_RC_ERROR_MASK0_P3                          , RULL(0x8000C80607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_RC_ERROR_MASK0_P3                          , RULL(0x8000C80608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_RC_ERROR_STATUS0_P0                          , RULL(0x8000C8050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_RC_ERROR_STATUS0_P0                        , RULL(0x8000C8050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_RC_ERROR_STATUS0_P0                        , RULL(0x8000C8050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_RC_ERROR_STATUS0_P1                        , RULL(0x8000C8050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_RC_ERROR_STATUS0_P1                        , RULL(0x8000C8050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_RC_ERROR_STATUS0_P2                        , RULL(0x8000C8050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_RC_ERROR_STATUS0_P2                        , RULL(0x8000C8050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_RC_ERROR_STATUS0_P3                        , RULL(0x8000C80507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_RC_ERROR_STATUS0_P3                        , RULL(0x8000C80508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_RC_RDVREF_CONFIG0_P0                         , RULL(0x8000C8090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_RC_RDVREF_CONFIG0_P0                       , RULL(0x8000C8090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_RC_RDVREF_CONFIG0_P0                       , RULL(0x8000C8090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_RC_RDVREF_CONFIG0_P1                       , RULL(0x8000C8090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_RC_RDVREF_CONFIG0_P1                       , RULL(0x8000C8090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_RC_RDVREF_CONFIG0_P2                       , RULL(0x8000C8090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_RC_RDVREF_CONFIG0_P2                       , RULL(0x8000C8090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_RC_RDVREF_CONFIG0_P3                       , RULL(0x8000C80907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_RC_RDVREF_CONFIG0_P3                       , RULL(0x8000C80908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_RC_RDVREF_CONFIG1_P0                         , RULL(0x8000C80A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_RC_RDVREF_CONFIG1_P0                       , RULL(0x8000C80A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_RC_RDVREF_CONFIG1_P0                       , RULL(0x8000C80A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_RC_RDVREF_CONFIG1_P1                       , RULL(0x8000C80A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_RC_RDVREF_CONFIG1_P1                       , RULL(0x8000C80A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_RC_RDVREF_CONFIG1_P2                       , RULL(0x8000C80A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_RC_RDVREF_CONFIG1_P2                       , RULL(0x8000C80A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_RC_RDVREF_CONFIG1_P3                       , RULL(0x8000C80A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_RC_RDVREF_CONFIG1_P3                       , RULL(0x8000C80A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_CONFIG0_P0                               , RULL(0x8000C4020701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_CONFIG0_P0                             , RULL(0x8000C4020701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_CONFIG0_P0                             , RULL(0x8000C4020801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_CONFIG0_P1                             , RULL(0x8000C4020701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_CONFIG0_P1                             , RULL(0x8000C4020801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_CONFIG0_P2                             , RULL(0x8000C4020701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_CONFIG0_P2                             , RULL(0x8000C4020801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_CONFIG0_P3                             , RULL(0x8000C40207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_CONFIG0_P3                             , RULL(0x8000C40208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_ERROR_MASK0_P0                           , RULL(0x8000C4090701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_ERROR_MASK0_P0                         , RULL(0x8000C4090701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_ERROR_MASK0_P0                         , RULL(0x8000C4090801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_ERROR_MASK0_P1                         , RULL(0x8000C4090701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_ERROR_MASK0_P1                         , RULL(0x8000C4090801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_ERROR_MASK0_P2                         , RULL(0x8000C4090701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_ERROR_MASK0_P2                         , RULL(0x8000C4090801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_ERROR_MASK0_P3                         , RULL(0x8000C40907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_ERROR_MASK0_P3                         , RULL(0x8000C40908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0                         , RULL(0x8000C4080701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_SEQ_ERROR_STATUS0_P0                       , RULL(0x8000C4080701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_SEQ_ERROR_STATUS0_P0                       , RULL(0x8000C4080801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_SEQ_ERROR_STATUS0_P1                       , RULL(0x8000C4080701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_SEQ_ERROR_STATUS0_P1                       , RULL(0x8000C4080801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_SEQ_ERROR_STATUS0_P2                       , RULL(0x8000C4080701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_SEQ_ERROR_STATUS0_P2                       , RULL(0x8000C4080801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_SEQ_ERROR_STATUS0_P3                       , RULL(0x8000C40807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_SEQ_ERROR_STATUS0_P3                       , RULL(0x8000C40808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_SEQ_LPT_ADDR2_P0                             , RULL(0x8000C4170701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_LPT_ADDR2_P0                           , RULL(0x8000C4170701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_LPT_ADDR2_P0                           , RULL(0x8000C4170801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_LPT_ADDR2_P1                           , RULL(0x8000C4170701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_LPT_ADDR2_P1                           , RULL(0x8000C4170801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_LPT_ADDR2_P2                           , RULL(0x8000C4170701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_LPT_ADDR2_P2                           , RULL(0x8000C4170801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_LPT_ADDR2_P3                           , RULL(0x8000C41707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_LPT_ADDR2_P3                           , RULL(0x8000C41708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_LPT_ADDR3_P0                             , RULL(0x8000C4180701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_LPT_ADDR3_P0                           , RULL(0x8000C4180701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_LPT_ADDR3_P0                           , RULL(0x8000C4180801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_LPT_ADDR3_P1                           , RULL(0x8000C4180701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_LPT_ADDR3_P1                           , RULL(0x8000C4180801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_LPT_ADDR3_P2                           , RULL(0x8000C4180701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_LPT_ADDR3_P2                           , RULL(0x8000C4180801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_LPT_ADDR3_P3                           , RULL(0x8000C41807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_LPT_ADDR3_P3                           , RULL(0x8000C41808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_LPT_ADDR4_P0                             , RULL(0x8000C4190701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_LPT_ADDR4_P0                           , RULL(0x8000C4190701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_LPT_ADDR4_P0                           , RULL(0x8000C4190801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_LPT_ADDR4_P1                           , RULL(0x8000C4190701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_LPT_ADDR4_P1                           , RULL(0x8000C4190801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_LPT_ADDR4_P2                           , RULL(0x8000C4190701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_LPT_ADDR4_P2                           , RULL(0x8000C4190801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_LPT_ADDR4_P3                           , RULL(0x8000C41907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_LPT_ADDR4_P3                           , RULL(0x8000C41908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0                     , RULL(0x8000C4120701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0                   , RULL(0x8000C4120701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0                   , RULL(0x8000C4120801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_MEM_TIMING_PARAM0_P1                   , RULL(0x8000C4120701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_MEM_TIMING_PARAM0_P1                   , RULL(0x8000C4120801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_MEM_TIMING_PARAM0_P2                   , RULL(0x8000C4120701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_MEM_TIMING_PARAM0_P2                   , RULL(0x8000C4120801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_MEM_TIMING_PARAM0_P3                   , RULL(0x8000C41207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_MEM_TIMING_PARAM0_P3                   , RULL(0x8000C41208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0                     , RULL(0x8000C4130701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0                   , RULL(0x8000C4130701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0                   , RULL(0x8000C4130801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_MEM_TIMING_PARAM1_P1                   , RULL(0x8000C4130701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_MEM_TIMING_PARAM1_P1                   , RULL(0x8000C4130801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_MEM_TIMING_PARAM1_P2                   , RULL(0x8000C4130701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_MEM_TIMING_PARAM1_P2                   , RULL(0x8000C4130801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_MEM_TIMING_PARAM1_P3                   , RULL(0x8000C41307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_MEM_TIMING_PARAM1_P3                   , RULL(0x8000C41308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0                     , RULL(0x8000C4140701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0                   , RULL(0x8000C4140701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0                   , RULL(0x8000C4140801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_MEM_TIMING_PARAM2_P1                   , RULL(0x8000C4140701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_MEM_TIMING_PARAM2_P1                   , RULL(0x8000C4140801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_MEM_TIMING_PARAM2_P2                   , RULL(0x8000C4140701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_MEM_TIMING_PARAM2_P2                   , RULL(0x8000C4140801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_MEM_TIMING_PARAM2_P3                   , RULL(0x8000C41407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_MEM_TIMING_PARAM2_P3                   , RULL(0x8000C41408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0                    , RULL(0x8000C4240701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0                  , RULL(0x8000C4240701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0                  , RULL(0x8000C4240801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P1                  , RULL(0x8000C4240701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P1                  , RULL(0x8000C4240801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P2                  , RULL(0x8000C4240701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P2                  , RULL(0x8000C4240801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P3                  , RULL(0x8000C42407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P3                  , RULL(0x8000C42408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0                        , RULL(0x8000C40E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_ODT_RD_CONFIG0_P0                      , RULL(0x8000C40E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_ODT_RD_CONFIG0_P0                      , RULL(0x8000C40E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_ODT_RD_CONFIG0_P1                      , RULL(0x8000C40E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_ODT_RD_CONFIG0_P1                      , RULL(0x8000C40E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_ODT_RD_CONFIG0_P2                      , RULL(0x8000C40E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_ODT_RD_CONFIG0_P2                      , RULL(0x8000C40E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_ODT_RD_CONFIG0_P3                      , RULL(0x8000C40E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_ODT_RD_CONFIG0_P3                      , RULL(0x8000C40E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0                        , RULL(0x8000C40F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_ODT_RD_CONFIG1_P0                      , RULL(0x8000C40F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_ODT_RD_CONFIG1_P0                      , RULL(0x8000C40F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_ODT_RD_CONFIG1_P1                      , RULL(0x8000C40F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_ODT_RD_CONFIG1_P1                      , RULL(0x8000C40F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_ODT_RD_CONFIG1_P2                      , RULL(0x8000C40F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_ODT_RD_CONFIG1_P2                      , RULL(0x8000C40F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_ODT_RD_CONFIG1_P3                      , RULL(0x8000C40F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_ODT_RD_CONFIG1_P3                      , RULL(0x8000C40F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0                        , RULL(0x8000C4100701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_ODT_RD_CONFIG2_P0                      , RULL(0x8000C4100701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_ODT_RD_CONFIG2_P0                      , RULL(0x8000C4100801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_ODT_RD_CONFIG2_P1                      , RULL(0x8000C4100701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_ODT_RD_CONFIG2_P1                      , RULL(0x8000C4100801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_ODT_RD_CONFIG2_P2                      , RULL(0x8000C4100701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_ODT_RD_CONFIG2_P2                      , RULL(0x8000C4100801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_ODT_RD_CONFIG2_P3                      , RULL(0x8000C41007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_ODT_RD_CONFIG2_P3                      , RULL(0x8000C41008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0                        , RULL(0x8000C4110701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_ODT_RD_CONFIG3_P0                      , RULL(0x8000C4110701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_ODT_RD_CONFIG3_P0                      , RULL(0x8000C4110801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_ODT_RD_CONFIG3_P1                      , RULL(0x8000C4110701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_ODT_RD_CONFIG3_P1                      , RULL(0x8000C4110801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_ODT_RD_CONFIG3_P2                      , RULL(0x8000C4110701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_ODT_RD_CONFIG3_P2                      , RULL(0x8000C4110801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_ODT_RD_CONFIG3_P3                      , RULL(0x8000C41107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_ODT_RD_CONFIG3_P3                      , RULL(0x8000C41108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0                        , RULL(0x8000C40A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_ODT_WR_CONFIG0_P0                      , RULL(0x8000C40A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_ODT_WR_CONFIG0_P0                      , RULL(0x8000C40A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_ODT_WR_CONFIG0_P1                      , RULL(0x8000C40A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_ODT_WR_CONFIG0_P1                      , RULL(0x8000C40A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_ODT_WR_CONFIG0_P2                      , RULL(0x8000C40A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_ODT_WR_CONFIG0_P2                      , RULL(0x8000C40A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_ODT_WR_CONFIG0_P3                      , RULL(0x8000C40A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_ODT_WR_CONFIG0_P3                      , RULL(0x8000C40A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0                        , RULL(0x8000C40B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_ODT_WR_CONFIG1_P0                      , RULL(0x8000C40B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_ODT_WR_CONFIG1_P0                      , RULL(0x8000C40B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_ODT_WR_CONFIG1_P1                      , RULL(0x8000C40B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_ODT_WR_CONFIG1_P1                      , RULL(0x8000C40B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_ODT_WR_CONFIG1_P2                      , RULL(0x8000C40B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_ODT_WR_CONFIG1_P2                      , RULL(0x8000C40B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_ODT_WR_CONFIG1_P3                      , RULL(0x8000C40B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_ODT_WR_CONFIG1_P3                      , RULL(0x8000C40B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0                        , RULL(0x8000C40C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_ODT_WR_CONFIG2_P0                      , RULL(0x8000C40C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_ODT_WR_CONFIG2_P0                      , RULL(0x8000C40C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_ODT_WR_CONFIG2_P1                      , RULL(0x8000C40C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_ODT_WR_CONFIG2_P1                      , RULL(0x8000C40C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_ODT_WR_CONFIG2_P2                      , RULL(0x8000C40C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_ODT_WR_CONFIG2_P2                      , RULL(0x8000C40C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_ODT_WR_CONFIG2_P3                      , RULL(0x8000C40C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_ODT_WR_CONFIG2_P3                      , RULL(0x8000C40C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0                        , RULL(0x8000C40D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_ODT_WR_CONFIG3_P0                      , RULL(0x8000C40D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_ODT_WR_CONFIG3_P0                      , RULL(0x8000C40D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_ODT_WR_CONFIG3_P1                      , RULL(0x8000C40D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_ODT_WR_CONFIG3_P1                      , RULL(0x8000C40D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_ODT_WR_CONFIG3_P2                      , RULL(0x8000C40D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_ODT_WR_CONFIG3_P2                      , RULL(0x8000C40D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_ODT_WR_CONFIG3_P3                      , RULL(0x8000C40D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_ODT_WR_CONFIG3_P3                      , RULL(0x8000C40D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_RD_WR_DATA0_P0                           , RULL(0x8000C4000701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_RD_WR_DATA0_P0                         , RULL(0x8000C4000701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_RD_WR_DATA0_P0                         , RULL(0x8000C4000801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_RD_WR_DATA0_P1                         , RULL(0x8000C4000701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_RD_WR_DATA0_P1                         , RULL(0x8000C4000801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_RD_WR_DATA0_P2                         , RULL(0x8000C4000701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_RD_WR_DATA0_P2                         , RULL(0x8000C4000801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_RD_WR_DATA0_P3                         , RULL(0x8000C40007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_RD_WR_DATA0_P3                         , RULL(0x8000C40008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_RD_WR_DATA1_P0                           , RULL(0x8000C4010701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_RD_WR_DATA1_P0                         , RULL(0x8000C4010701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_RD_WR_DATA1_P0                         , RULL(0x8000C4010801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_RD_WR_DATA1_P1                         , RULL(0x8000C4010701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_RD_WR_DATA1_P1                         , RULL(0x8000C4010801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_RD_WR_DATA1_P2                         , RULL(0x8000C4010701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_RD_WR_DATA1_P2                         , RULL(0x8000C4010801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_RD_WR_DATA1_P3                         , RULL(0x8000C40107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_RD_WR_DATA1_P3                         , RULL(0x8000C40108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_RESERVED_ADDR0_P0                        , RULL(0x8000C4030701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_RESERVED_ADDR0_P0                      , RULL(0x8000C4030701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_RESERVED_ADDR0_P0                      , RULL(0x8000C4030801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_RESERVED_ADDR0_P1                      , RULL(0x8000C4030701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_RESERVED_ADDR0_P1                      , RULL(0x8000C4030801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_RESERVED_ADDR0_P2                      , RULL(0x8000C4030701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_RESERVED_ADDR0_P2                      , RULL(0x8000C4030801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_RESERVED_ADDR0_P3                      , RULL(0x8000C40307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_RESERVED_ADDR0_P3                      , RULL(0x8000C40308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_RESERVED_ADDR1_P0                        , RULL(0x8000C4040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_RESERVED_ADDR1_P0                      , RULL(0x8000C4040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_RESERVED_ADDR1_P0                      , RULL(0x8000C4040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_RESERVED_ADDR1_P1                      , RULL(0x8000C4040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_RESERVED_ADDR1_P1                      , RULL(0x8000C4040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_RESERVED_ADDR1_P2                      , RULL(0x8000C4040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_RESERVED_ADDR1_P2                      , RULL(0x8000C4040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_RESERVED_ADDR1_P3                      , RULL(0x8000C40407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_RESERVED_ADDR1_P3                      , RULL(0x8000C40408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_RESERVED_ADDR2_P0                        , RULL(0x8000C4050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_RESERVED_ADDR2_P0                      , RULL(0x8000C4050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_RESERVED_ADDR2_P0                      , RULL(0x8000C4050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_RESERVED_ADDR2_P1                      , RULL(0x8000C4050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_RESERVED_ADDR2_P1                      , RULL(0x8000C4050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_RESERVED_ADDR2_P2                      , RULL(0x8000C4050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_RESERVED_ADDR2_P2                      , RULL(0x8000C4050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_RESERVED_ADDR2_P3                      , RULL(0x8000C40507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_RESERVED_ADDR2_P3                      , RULL(0x8000C40508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_RESERVED_ADDR3_P0                        , RULL(0x8000C4060701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_RESERVED_ADDR3_P0                      , RULL(0x8000C4060701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_RESERVED_ADDR3_P0                      , RULL(0x8000C4060801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_RESERVED_ADDR3_P1                      , RULL(0x8000C4060701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_RESERVED_ADDR3_P1                      , RULL(0x8000C4060801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_RESERVED_ADDR3_P2                      , RULL(0x8000C4060701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_RESERVED_ADDR3_P2                      , RULL(0x8000C4060801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_RESERVED_ADDR3_P3                      , RULL(0x8000C40607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_RESERVED_ADDR3_P3                      , RULL(0x8000C40608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_RESERVED_ADDR4_P0                        , RULL(0x8000C4070701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_RESERVED_ADDR4_P0                      , RULL(0x8000C4070701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_RESERVED_ADDR4_P0                      , RULL(0x8000C4070801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_RESERVED_ADDR4_P1                      , RULL(0x8000C4070701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_RESERVED_ADDR4_P1                      , RULL(0x8000C4070801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_RESERVED_ADDR4_P2                      , RULL(0x8000C4070701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_RESERVED_ADDR4_P2                      , RULL(0x8000C4070801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_RESERVED_ADDR4_P3                      , RULL(0x8000C40707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_RESERVED_ADDR4_P3                      , RULL(0x8000C40708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0                         , RULL(0x8000C41D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_WR_TERM_SWAP0_P0                       , RULL(0x8000C41D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_WR_TERM_SWAP0_P0                       , RULL(0x8000C41D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_WR_TERM_SWAP0_P1                       , RULL(0x8000C41D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_WR_TERM_SWAP0_P1                       , RULL(0x8000C41D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_WR_TERM_SWAP0_P2                       , RULL(0x8000C41D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_WR_TERM_SWAP0_P2                       , RULL(0x8000C41D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_WR_TERM_SWAP0_P3                       , RULL(0x8000C41D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_WR_TERM_SWAP0_P3                       , RULL(0x8000C41D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0                         , RULL(0x8000C41E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_WR_TERM_SWAP1_P0                       , RULL(0x8000C41E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_WR_TERM_SWAP1_P0                       , RULL(0x8000C41E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_WR_TERM_SWAP1_P1                       , RULL(0x8000C41E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_WR_TERM_SWAP1_P1                       , RULL(0x8000C41E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_WR_TERM_SWAP1_P2                       , RULL(0x8000C41E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_WR_TERM_SWAP1_P2                       , RULL(0x8000C41E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_WR_TERM_SWAP1_P3                       , RULL(0x8000C41E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_WR_TERM_SWAP1_P3                       , RULL(0x8000C41E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0               , RULL(0x8000C41A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0             , RULL(0x8000C41A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0             , RULL(0x8000C41A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P1             , RULL(0x8000C41A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P1             , RULL(0x8000C41A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P2             , RULL(0x8000C41A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P2             , RULL(0x8000C41A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P3             , RULL(0x8000C41A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P3             , RULL(0x8000C41A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0               , RULL(0x8000C41B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0             , RULL(0x8000C41B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0             , RULL(0x8000C41B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P1             , RULL(0x8000C41B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P1             , RULL(0x8000C41B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P2             , RULL(0x8000C41B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P2             , RULL(0x8000C41B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P3             , RULL(0x8000C41B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P3             , RULL(0x8000C41B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_WC_CONFIG0_P0                                , RULL(0x8000CC000701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_WC_CONFIG0_P0                              , RULL(0x8000CC000701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_WC_CONFIG0_P0                              , RULL(0x8000CC000801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_WC_CONFIG0_P1                              , RULL(0x8000CC000701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_WC_CONFIG0_P1                              , RULL(0x8000CC000801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_WC_CONFIG0_P2                              , RULL(0x8000CC000701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_WC_CONFIG0_P2                              , RULL(0x8000CC000801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_WC_CONFIG0_P3                              , RULL(0x8000CC0007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_WC_CONFIG0_P3                              , RULL(0x8000CC0008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_WC_CONFIG1_P0                                , RULL(0x8000CC010701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_WC_CONFIG1_P0                              , RULL(0x8000CC010701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_WC_CONFIG1_P0                              , RULL(0x8000CC010801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_WC_CONFIG1_P1                              , RULL(0x8000CC010701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_WC_CONFIG1_P1                              , RULL(0x8000CC010801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_WC_CONFIG1_P2                              , RULL(0x8000CC010701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_WC_CONFIG1_P2                              , RULL(0x8000CC010801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_WC_CONFIG1_P3                              , RULL(0x8000CC0107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_WC_CONFIG1_P3                              , RULL(0x8000CC0108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_WC_CONFIG2_P0                                , RULL(0x8000CC020701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_WC_CONFIG2_P0                              , RULL(0x8000CC020701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_WC_CONFIG2_P0                              , RULL(0x8000CC020801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_WC_CONFIG2_P1                              , RULL(0x8000CC020701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_WC_CONFIG2_P1                              , RULL(0x8000CC020801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_WC_CONFIG2_P2                              , RULL(0x8000CC020701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_WC_CONFIG2_P2                              , RULL(0x8000CC020801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_WC_CONFIG2_P3                              , RULL(0x8000CC0207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_WC_CONFIG2_P3                              , RULL(0x8000CC0208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_WC_CONFIG3_P0                                , RULL(0x8000CC050701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_WC_CONFIG3_P0                              , RULL(0x8000CC050701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_WC_CONFIG3_P0                              , RULL(0x8000CC050801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_WC_CONFIG3_P1                              , RULL(0x8000CC050701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_WC_CONFIG3_P1                              , RULL(0x8000CC050801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_WC_CONFIG3_P2                              , RULL(0x8000CC050701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_WC_CONFIG3_P2                              , RULL(0x8000CC050801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_WC_CONFIG3_P3                              , RULL(0x8000CC0507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_WC_CONFIG3_P3                              , RULL(0x8000CC0508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_WC_ERROR_MASK0_P0                            , RULL(0x8000CC040701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_WC_ERROR_MASK0_P0                          , RULL(0x8000CC040701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_WC_ERROR_MASK0_P0                          , RULL(0x8000CC040801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_WC_ERROR_MASK0_P1                          , RULL(0x8000CC040701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_WC_ERROR_MASK0_P1                          , RULL(0x8000CC040801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_WC_ERROR_MASK0_P2                          , RULL(0x8000CC040701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_WC_ERROR_MASK0_P2                          , RULL(0x8000CC040801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_WC_ERROR_MASK0_P3                          , RULL(0x8000CC0407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_WC_ERROR_MASK0_P3                          , RULL(0x8000CC0408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DDRPHY_WC_ERROR_STATUS0_P0                          , RULL(0x8000CC030701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_0_DDRPHY_WC_ERROR_STATUS0_P0                        , RULL(0x8000CC030701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_4_DDRPHY_WC_ERROR_STATUS0_P0                        , RULL(0x8000CC030801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_1_DDRPHY_WC_ERROR_STATUS0_P1                        , RULL(0x8000CC030701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_5_DDRPHY_WC_ERROR_STATUS0_P1                        , RULL(0x8000CC030801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_2_DDRPHY_WC_ERROR_STATUS0_P2                        , RULL(0x8000CC030701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_6_DDRPHY_WC_ERROR_STATUS0_P2                        , RULL(0x8000CC030801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_3_DDRPHY_WC_ERROR_STATUS0_P3                        , RULL(0x8000CC0307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RO   );
+REG64( MCA_7_DDRPHY_WC_ERROR_STATUS0_P3                        , RULL(0x8000CC0308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RO   );
+
+REG64( MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0                     , RULL(0x8000CC060701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0                   , RULL(0x8000CC060701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0                   , RULL(0x8000CC060801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P1                   , RULL(0x8000CC060701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P1                   , RULL(0x8000CC060801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P2                   , RULL(0x8000CC060701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P2                   , RULL(0x8000CC060801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P3                   , RULL(0x8000CC0607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P3                   , RULL(0x8000CC0608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DEBUG_TRACE_CONTROL                               , RULL(0x070107D0), SH_UNT_MCA_3    , SH_ACS_SCOM      );
+REG64( MCA_7_DEBUG_TRACE_CONTROL                               , RULL(0x080107D0), SH_UNT_MCA_7    , SH_ACS_SCOM      );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_0                  , RULL(0x800000380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_0                , RULL(0x800000380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_0                , RULL(0x800000380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_1                  , RULL(0x800004380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_1                , RULL(0x800004380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_1                , RULL(0x800004380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_2                  , RULL(0x800008380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_2                , RULL(0x800008380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_2                , RULL(0x800008380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_3                  , RULL(0x80000C380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_3                , RULL(0x80000C380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_3                , RULL(0x80000C380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_4                  , RULL(0x800010380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_4                , RULL(0x800010380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_4                , RULL(0x800010380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP0_REG_P1_0                , RULL(0x800000380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP0_REG_P1_0                , RULL(0x800000380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP0_REG_P1_1                , RULL(0x800004380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP0_REG_P1_1                , RULL(0x800004380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP0_REG_P1_2                , RULL(0x800008380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP0_REG_P1_2                , RULL(0x800008380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP0_REG_P1_3                , RULL(0x80000C380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP0_REG_P1_3                , RULL(0x80000C380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP0_REG_P1_4                , RULL(0x800010380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP0_REG_P1_4                , RULL(0x800010380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP0_REG_P2_0                , RULL(0x800000380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP0_REG_P2_0                , RULL(0x800000380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP0_REG_P2_1                , RULL(0x800004380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP0_REG_P2_1                , RULL(0x800004380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP0_REG_P2_2                , RULL(0x800008380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP0_REG_P2_2                , RULL(0x800008380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP0_REG_P2_3                , RULL(0x80000C380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP0_REG_P2_3                , RULL(0x80000C380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP0_REG_P2_4                , RULL(0x800010380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP0_REG_P2_4                , RULL(0x800010380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP0_REG_P3_0                , RULL(0x8000003807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP0_REG_P3_0                , RULL(0x8000003808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP0_REG_P3_1                , RULL(0x8000043807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP0_REG_P3_1                , RULL(0x8000043808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP0_REG_P3_2                , RULL(0x8000083807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP0_REG_P3_2                , RULL(0x8000083808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP0_REG_P3_3                , RULL(0x80000C3807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP0_REG_P3_3                , RULL(0x80000C3808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP0_REG_P3_4                , RULL(0x8000103807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP0_REG_P3_4                , RULL(0x8000103808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_0                  , RULL(0x800001380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_0                , RULL(0x800001380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_0                , RULL(0x800001380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_1                  , RULL(0x800005380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_1                , RULL(0x800005380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_1                , RULL(0x800005380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_2                  , RULL(0x800009380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_2                , RULL(0x800009380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_2                , RULL(0x800009380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_3                  , RULL(0x80000D380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_3                , RULL(0x80000D380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_3                , RULL(0x80000D380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_4                  , RULL(0x800011380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_4                , RULL(0x800011380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_4                , RULL(0x800011380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP1_REG_P1_0                , RULL(0x800001380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP1_REG_P1_0                , RULL(0x800001380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP1_REG_P1_1                , RULL(0x800005380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP1_REG_P1_1                , RULL(0x800005380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP1_REG_P1_2                , RULL(0x800009380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP1_REG_P1_2                , RULL(0x800009380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP1_REG_P1_3                , RULL(0x80000D380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP1_REG_P1_3                , RULL(0x80000D380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP1_REG_P1_4                , RULL(0x800011380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP1_REG_P1_4                , RULL(0x800011380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP1_REG_P2_0                , RULL(0x800001380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP1_REG_P2_0                , RULL(0x800001380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP1_REG_P2_1                , RULL(0x800005380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP1_REG_P2_1                , RULL(0x800005380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP1_REG_P2_2                , RULL(0x800009380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP1_REG_P2_2                , RULL(0x800009380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP1_REG_P2_3                , RULL(0x80000D380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP1_REG_P2_3                , RULL(0x80000D380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP1_REG_P2_4                , RULL(0x800011380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP1_REG_P2_4                , RULL(0x800011380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP1_REG_P3_0                , RULL(0x8000013807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP1_REG_P3_0                , RULL(0x8000013808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP1_REG_P3_1                , RULL(0x8000053807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP1_REG_P3_1                , RULL(0x8000053808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP1_REG_P3_2                , RULL(0x8000093807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP1_REG_P3_2                , RULL(0x8000093808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP1_REG_P3_3                , RULL(0x80000D3807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP1_REG_P3_3                , RULL(0x80000D3808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP1_REG_P3_4                , RULL(0x8000113807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP1_REG_P3_4                , RULL(0x8000113808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_0                  , RULL(0x800002380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_0                , RULL(0x800002380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_0                , RULL(0x800002380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_1                  , RULL(0x800006380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_1                , RULL(0x800006380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_1                , RULL(0x800006380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_2                  , RULL(0x80000A380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_2                , RULL(0x80000A380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_2                , RULL(0x80000A380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_3                  , RULL(0x80000E380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_3                , RULL(0x80000E380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_3                , RULL(0x80000E380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_4                  , RULL(0x800012380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_4                , RULL(0x800012380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_4                , RULL(0x800012380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP2_REG_P1_0                , RULL(0x800002380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP2_REG_P1_0                , RULL(0x800002380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP2_REG_P1_1                , RULL(0x800006380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP2_REG_P1_1                , RULL(0x800006380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP2_REG_P1_2                , RULL(0x80000A380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP2_REG_P1_2                , RULL(0x80000A380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP2_REG_P1_3                , RULL(0x80000E380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP2_REG_P1_3                , RULL(0x80000E380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP2_REG_P1_4                , RULL(0x800012380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP2_REG_P1_4                , RULL(0x800012380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP2_REG_P2_0                , RULL(0x800002380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP2_REG_P2_0                , RULL(0x800002380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP2_REG_P2_1                , RULL(0x800006380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP2_REG_P2_1                , RULL(0x800006380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP2_REG_P2_2                , RULL(0x80000A380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP2_REG_P2_2                , RULL(0x80000A380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP2_REG_P2_3                , RULL(0x80000E380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP2_REG_P2_3                , RULL(0x80000E380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP2_REG_P2_4                , RULL(0x800012380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP2_REG_P2_4                , RULL(0x800012380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP2_REG_P3_0                , RULL(0x8000023807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP2_REG_P3_0                , RULL(0x8000023808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP2_REG_P3_1                , RULL(0x8000063807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP2_REG_P3_1                , RULL(0x8000063808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP2_REG_P3_2                , RULL(0x80000A3807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP2_REG_P3_2                , RULL(0x80000A3808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP2_REG_P3_3                , RULL(0x80000E3807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP2_REG_P3_3                , RULL(0x80000E3808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP2_REG_P3_4                , RULL(0x8000123807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP2_REG_P3_4                , RULL(0x8000123808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_0                  , RULL(0x800003380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_0                , RULL(0x800003380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_0                , RULL(0x800003380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_1                  , RULL(0x800007380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_1                , RULL(0x800007380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_1                , RULL(0x800007380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_2                  , RULL(0x80000B380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_2                , RULL(0x80000B380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_2                , RULL(0x80000B380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_3                  , RULL(0x80000F380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_3                , RULL(0x80000F380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_3                , RULL(0x80000F380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_4                  , RULL(0x800013380701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_4                , RULL(0x800013380701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_4                , RULL(0x800013380801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP3_REG_P1_0                , RULL(0x800003380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP3_REG_P1_0                , RULL(0x800003380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP3_REG_P1_1                , RULL(0x800007380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP3_REG_P1_1                , RULL(0x800007380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP3_REG_P1_2                , RULL(0x80000B380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP3_REG_P1_2                , RULL(0x80000B380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP3_REG_P1_3                , RULL(0x80000F380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP3_REG_P1_3                , RULL(0x80000F380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_0_RP3_REG_P1_4                , RULL(0x800013380701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_0_RP3_REG_P1_4                , RULL(0x800013380801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP3_REG_P2_0                , RULL(0x800003380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP3_REG_P2_0                , RULL(0x800003380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP3_REG_P2_1                , RULL(0x800007380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP3_REG_P2_1                , RULL(0x800007380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP3_REG_P2_2                , RULL(0x80000B380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP3_REG_P2_2                , RULL(0x80000B380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP3_REG_P2_3                , RULL(0x80000F380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP3_REG_P2_3                , RULL(0x80000F380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_0_RP3_REG_P2_4                , RULL(0x800013380701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_0_RP3_REG_P2_4                , RULL(0x800013380801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP3_REG_P3_0                , RULL(0x8000033807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP3_REG_P3_0                , RULL(0x8000033808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP3_REG_P3_1                , RULL(0x8000073807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP3_REG_P3_1                , RULL(0x8000073808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP3_REG_P3_2                , RULL(0x80000B3807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP3_REG_P3_2                , RULL(0x80000B3808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP3_REG_P3_3                , RULL(0x80000F3807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP3_REG_P3_3                , RULL(0x80000F3808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_0_RP3_REG_P3_4                , RULL(0x8000133807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_0_RP3_REG_P3_4                , RULL(0x8000133808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_0                 , RULL(0x800000420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_0               , RULL(0x800000420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_0               , RULL(0x800000420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_1                 , RULL(0x800004420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_1               , RULL(0x800004420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_1               , RULL(0x800004420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_2                 , RULL(0x800008420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_2               , RULL(0x800008420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_2               , RULL(0x800008420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_3                 , RULL(0x80000C420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_3               , RULL(0x80000C420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_3               , RULL(0x80000C420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_4                 , RULL(0x800010420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_4               , RULL(0x800010420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_4               , RULL(0x800010420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP0_REG_P1_0               , RULL(0x800000420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP0_REG_P1_0               , RULL(0x800000420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP0_REG_P1_1               , RULL(0x800004420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP0_REG_P1_1               , RULL(0x800004420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP0_REG_P1_2               , RULL(0x800008420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP0_REG_P1_2               , RULL(0x800008420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP0_REG_P1_3               , RULL(0x80000C420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP0_REG_P1_3               , RULL(0x80000C420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP0_REG_P1_4               , RULL(0x800010420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP0_REG_P1_4               , RULL(0x800010420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP0_REG_P2_0               , RULL(0x800000420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP0_REG_P2_0               , RULL(0x800000420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP0_REG_P2_1               , RULL(0x800004420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP0_REG_P2_1               , RULL(0x800004420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP0_REG_P2_2               , RULL(0x800008420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP0_REG_P2_2               , RULL(0x800008420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP0_REG_P2_3               , RULL(0x80000C420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP0_REG_P2_3               , RULL(0x80000C420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP0_REG_P2_4               , RULL(0x800010420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP0_REG_P2_4               , RULL(0x800010420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP0_REG_P3_0               , RULL(0x8000004207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP0_REG_P3_0               , RULL(0x8000004208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP0_REG_P3_1               , RULL(0x8000044207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP0_REG_P3_1               , RULL(0x8000044208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP0_REG_P3_2               , RULL(0x8000084207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP0_REG_P3_2               , RULL(0x8000084208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP0_REG_P3_3               , RULL(0x80000C4207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP0_REG_P3_3               , RULL(0x80000C4208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP0_REG_P3_4               , RULL(0x8000104207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP0_REG_P3_4               , RULL(0x8000104208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_0                 , RULL(0x800001420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_0               , RULL(0x800001420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_0               , RULL(0x800001420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_1                 , RULL(0x800005420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_1               , RULL(0x800005420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_1               , RULL(0x800005420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_2                 , RULL(0x800009420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_2               , RULL(0x800009420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_2               , RULL(0x800009420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_3                 , RULL(0x80000D420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_3               , RULL(0x80000D420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_3               , RULL(0x80000D420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_4                 , RULL(0x800011420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_4               , RULL(0x800011420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_4               , RULL(0x800011420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP1_REG_P1_0               , RULL(0x800001420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP1_REG_P1_0               , RULL(0x800001420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP1_REG_P1_1               , RULL(0x800005420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP1_REG_P1_1               , RULL(0x800005420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP1_REG_P1_2               , RULL(0x800009420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP1_REG_P1_2               , RULL(0x800009420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP1_REG_P1_3               , RULL(0x80000D420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP1_REG_P1_3               , RULL(0x80000D420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP1_REG_P1_4               , RULL(0x800011420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP1_REG_P1_4               , RULL(0x800011420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP1_REG_P2_0               , RULL(0x800001420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP1_REG_P2_0               , RULL(0x800001420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP1_REG_P2_1               , RULL(0x800005420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP1_REG_P2_1               , RULL(0x800005420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP1_REG_P2_2               , RULL(0x800009420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP1_REG_P2_2               , RULL(0x800009420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP1_REG_P2_3               , RULL(0x80000D420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP1_REG_P2_3               , RULL(0x80000D420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP1_REG_P2_4               , RULL(0x800011420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP1_REG_P2_4               , RULL(0x800011420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP1_REG_P3_0               , RULL(0x8000014207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP1_REG_P3_0               , RULL(0x8000014208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP1_REG_P3_1               , RULL(0x8000054207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP1_REG_P3_1               , RULL(0x8000054208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP1_REG_P3_2               , RULL(0x8000094207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP1_REG_P3_2               , RULL(0x8000094208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP1_REG_P3_3               , RULL(0x80000D4207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP1_REG_P3_3               , RULL(0x80000D4208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP1_REG_P3_4               , RULL(0x8000114207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP1_REG_P3_4               , RULL(0x8000114208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_0                 , RULL(0x800002420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_0               , RULL(0x800002420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_0               , RULL(0x800002420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_1                 , RULL(0x800006420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_1               , RULL(0x800006420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_1               , RULL(0x800006420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_2                 , RULL(0x80000A420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_2               , RULL(0x80000A420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_2               , RULL(0x80000A420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_3                 , RULL(0x80000E420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_3               , RULL(0x80000E420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_3               , RULL(0x80000E420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_4                 , RULL(0x800012420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_4               , RULL(0x800012420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_4               , RULL(0x800012420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP2_REG_P1_0               , RULL(0x800002420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP2_REG_P1_0               , RULL(0x800002420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP2_REG_P1_1               , RULL(0x800006420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP2_REG_P1_1               , RULL(0x800006420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP2_REG_P1_2               , RULL(0x80000A420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP2_REG_P1_2               , RULL(0x80000A420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP2_REG_P1_3               , RULL(0x80000E420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP2_REG_P1_3               , RULL(0x80000E420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP2_REG_P1_4               , RULL(0x800012420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP2_REG_P1_4               , RULL(0x800012420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP2_REG_P2_0               , RULL(0x800002420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP2_REG_P2_0               , RULL(0x800002420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP2_REG_P2_1               , RULL(0x800006420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP2_REG_P2_1               , RULL(0x800006420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP2_REG_P2_2               , RULL(0x80000A420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP2_REG_P2_2               , RULL(0x80000A420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP2_REG_P2_3               , RULL(0x80000E420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP2_REG_P2_3               , RULL(0x80000E420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP2_REG_P2_4               , RULL(0x800012420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP2_REG_P2_4               , RULL(0x800012420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP2_REG_P3_0               , RULL(0x8000024207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP2_REG_P3_0               , RULL(0x8000024208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP2_REG_P3_1               , RULL(0x8000064207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP2_REG_P3_1               , RULL(0x8000064208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP2_REG_P3_2               , RULL(0x80000A4207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP2_REG_P3_2               , RULL(0x80000A4208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP2_REG_P3_3               , RULL(0x80000E4207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP2_REG_P3_3               , RULL(0x80000E4208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP2_REG_P3_4               , RULL(0x8000124207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP2_REG_P3_4               , RULL(0x8000124208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_0                 , RULL(0x800003420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_0               , RULL(0x800003420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_0               , RULL(0x800003420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_1                 , RULL(0x800007420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_1               , RULL(0x800007420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_1               , RULL(0x800007420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_2                 , RULL(0x80000B420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_2               , RULL(0x80000B420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_2               , RULL(0x80000B420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_3                 , RULL(0x80000F420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_3               , RULL(0x80000F420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_3               , RULL(0x80000F420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_4                 , RULL(0x800013420701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_4               , RULL(0x800013420701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_4               , RULL(0x800013420801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP3_REG_P1_0               , RULL(0x800003420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP3_REG_P1_0               , RULL(0x800003420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP3_REG_P1_1               , RULL(0x800007420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP3_REG_P1_1               , RULL(0x800007420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP3_REG_P1_2               , RULL(0x80000B420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP3_REG_P1_2               , RULL(0x80000B420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP3_REG_P1_3               , RULL(0x80000F420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP3_REG_P1_3               , RULL(0x80000F420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_10_RP3_REG_P1_4               , RULL(0x800013420701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_10_RP3_REG_P1_4               , RULL(0x800013420801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP3_REG_P2_0               , RULL(0x800003420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP3_REG_P2_0               , RULL(0x800003420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP3_REG_P2_1               , RULL(0x800007420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP3_REG_P2_1               , RULL(0x800007420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP3_REG_P2_2               , RULL(0x80000B420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP3_REG_P2_2               , RULL(0x80000B420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP3_REG_P2_3               , RULL(0x80000F420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP3_REG_P2_3               , RULL(0x80000F420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_10_RP3_REG_P2_4               , RULL(0x800013420701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_10_RP3_REG_P2_4               , RULL(0x800013420801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP3_REG_P3_0               , RULL(0x8000034207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP3_REG_P3_0               , RULL(0x8000034208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP3_REG_P3_1               , RULL(0x8000074207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP3_REG_P3_1               , RULL(0x8000074208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP3_REG_P3_2               , RULL(0x80000B4207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP3_REG_P3_2               , RULL(0x80000B4208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP3_REG_P3_3               , RULL(0x80000F4207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP3_REG_P3_3               , RULL(0x80000F4208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_10_RP3_REG_P3_4               , RULL(0x8000134207011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_10_RP3_REG_P3_4               , RULL(0x8000134208011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_0                 , RULL(0x800000430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_0               , RULL(0x800000430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_0               , RULL(0x800000430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_1                 , RULL(0x800004430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_1               , RULL(0x800004430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_1               , RULL(0x800004430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_2                 , RULL(0x800008430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_2               , RULL(0x800008430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_2               , RULL(0x800008430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_3                 , RULL(0x80000C430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_3               , RULL(0x80000C430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_3               , RULL(0x80000C430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_4                 , RULL(0x800010430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_4               , RULL(0x800010430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_4               , RULL(0x800010430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP0_REG_P1_0               , RULL(0x800000430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP0_REG_P1_0               , RULL(0x800000430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP0_REG_P1_1               , RULL(0x800004430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP0_REG_P1_1               , RULL(0x800004430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP0_REG_P1_2               , RULL(0x800008430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP0_REG_P1_2               , RULL(0x800008430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP0_REG_P1_3               , RULL(0x80000C430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP0_REG_P1_3               , RULL(0x80000C430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP0_REG_P1_4               , RULL(0x800010430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP0_REG_P1_4               , RULL(0x800010430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP0_REG_P2_0               , RULL(0x800000430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP0_REG_P2_0               , RULL(0x800000430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP0_REG_P2_1               , RULL(0x800004430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP0_REG_P2_1               , RULL(0x800004430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP0_REG_P2_2               , RULL(0x800008430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP0_REG_P2_2               , RULL(0x800008430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP0_REG_P2_3               , RULL(0x80000C430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP0_REG_P2_3               , RULL(0x80000C430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP0_REG_P2_4               , RULL(0x800010430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP0_REG_P2_4               , RULL(0x800010430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP0_REG_P3_0               , RULL(0x8000004307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP0_REG_P3_0               , RULL(0x8000004308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP0_REG_P3_1               , RULL(0x8000044307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP0_REG_P3_1               , RULL(0x8000044308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP0_REG_P3_2               , RULL(0x8000084307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP0_REG_P3_2               , RULL(0x8000084308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP0_REG_P3_3               , RULL(0x80000C4307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP0_REG_P3_3               , RULL(0x80000C4308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP0_REG_P3_4               , RULL(0x8000104307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP0_REG_P3_4               , RULL(0x8000104308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_0                 , RULL(0x800001430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_0               , RULL(0x800001430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_0               , RULL(0x800001430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_1                 , RULL(0x800005430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_1               , RULL(0x800005430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_1               , RULL(0x800005430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_2                 , RULL(0x800009430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_2               , RULL(0x800009430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_2               , RULL(0x800009430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_3                 , RULL(0x80000D430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_3               , RULL(0x80000D430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_3               , RULL(0x80000D430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_4                 , RULL(0x800011430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_4               , RULL(0x800011430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_4               , RULL(0x800011430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP1_REG_P1_0               , RULL(0x800001430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP1_REG_P1_0               , RULL(0x800001430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP1_REG_P1_1               , RULL(0x800005430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP1_REG_P1_1               , RULL(0x800005430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP1_REG_P1_2               , RULL(0x800009430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP1_REG_P1_2               , RULL(0x800009430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP1_REG_P1_3               , RULL(0x80000D430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP1_REG_P1_3               , RULL(0x80000D430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP1_REG_P1_4               , RULL(0x800011430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP1_REG_P1_4               , RULL(0x800011430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP1_REG_P2_0               , RULL(0x800001430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP1_REG_P2_0               , RULL(0x800001430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP1_REG_P2_1               , RULL(0x800005430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP1_REG_P2_1               , RULL(0x800005430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP1_REG_P2_2               , RULL(0x800009430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP1_REG_P2_2               , RULL(0x800009430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP1_REG_P2_3               , RULL(0x80000D430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP1_REG_P2_3               , RULL(0x80000D430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP1_REG_P2_4               , RULL(0x800011430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP1_REG_P2_4               , RULL(0x800011430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP1_REG_P3_0               , RULL(0x8000014307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP1_REG_P3_0               , RULL(0x8000014308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP1_REG_P3_1               , RULL(0x8000054307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP1_REG_P3_1               , RULL(0x8000054308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP1_REG_P3_2               , RULL(0x8000094307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP1_REG_P3_2               , RULL(0x8000094308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP1_REG_P3_3               , RULL(0x80000D4307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP1_REG_P3_3               , RULL(0x80000D4308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP1_REG_P3_4               , RULL(0x8000114307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP1_REG_P3_4               , RULL(0x8000114308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_0                 , RULL(0x800002430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_0               , RULL(0x800002430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_0               , RULL(0x800002430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_1                 , RULL(0x800006430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_1               , RULL(0x800006430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_1               , RULL(0x800006430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_2                 , RULL(0x80000A430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_2               , RULL(0x80000A430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_2               , RULL(0x80000A430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_3                 , RULL(0x80000E430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_3               , RULL(0x80000E430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_3               , RULL(0x80000E430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_4                 , RULL(0x800012430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_4               , RULL(0x800012430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_4               , RULL(0x800012430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP2_REG_P1_0               , RULL(0x800002430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP2_REG_P1_0               , RULL(0x800002430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP2_REG_P1_1               , RULL(0x800006430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP2_REG_P1_1               , RULL(0x800006430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP2_REG_P1_2               , RULL(0x80000A430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP2_REG_P1_2               , RULL(0x80000A430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP2_REG_P1_3               , RULL(0x80000E430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP2_REG_P1_3               , RULL(0x80000E430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP2_REG_P1_4               , RULL(0x800012430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP2_REG_P1_4               , RULL(0x800012430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP2_REG_P2_0               , RULL(0x800002430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP2_REG_P2_0               , RULL(0x800002430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP2_REG_P2_1               , RULL(0x800006430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP2_REG_P2_1               , RULL(0x800006430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP2_REG_P2_2               , RULL(0x80000A430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP2_REG_P2_2               , RULL(0x80000A430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP2_REG_P2_3               , RULL(0x80000E430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP2_REG_P2_3               , RULL(0x80000E430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP2_REG_P2_4               , RULL(0x800012430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP2_REG_P2_4               , RULL(0x800012430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP2_REG_P3_0               , RULL(0x8000024307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP2_REG_P3_0               , RULL(0x8000024308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP2_REG_P3_1               , RULL(0x8000064307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP2_REG_P3_1               , RULL(0x8000064308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP2_REG_P3_2               , RULL(0x80000A4307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP2_REG_P3_2               , RULL(0x80000A4308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP2_REG_P3_3               , RULL(0x80000E4307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP2_REG_P3_3               , RULL(0x80000E4308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP2_REG_P3_4               , RULL(0x8000124307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP2_REG_P3_4               , RULL(0x8000124308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_0                 , RULL(0x800003430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_0               , RULL(0x800003430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_0               , RULL(0x800003430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_1                 , RULL(0x800007430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_1               , RULL(0x800007430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_1               , RULL(0x800007430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_2                 , RULL(0x80000B430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_2               , RULL(0x80000B430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_2               , RULL(0x80000B430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_3                 , RULL(0x80000F430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_3               , RULL(0x80000F430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_3               , RULL(0x80000F430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_4                 , RULL(0x800013430701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_4               , RULL(0x800013430701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_4               , RULL(0x800013430801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP3_REG_P1_0               , RULL(0x800003430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP3_REG_P1_0               , RULL(0x800003430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP3_REG_P1_1               , RULL(0x800007430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP3_REG_P1_1               , RULL(0x800007430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP3_REG_P1_2               , RULL(0x80000B430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP3_REG_P1_2               , RULL(0x80000B430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP3_REG_P1_3               , RULL(0x80000F430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP3_REG_P1_3               , RULL(0x80000F430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_11_RP3_REG_P1_4               , RULL(0x800013430701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_11_RP3_REG_P1_4               , RULL(0x800013430801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP3_REG_P2_0               , RULL(0x800003430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP3_REG_P2_0               , RULL(0x800003430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP3_REG_P2_1               , RULL(0x800007430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP3_REG_P2_1               , RULL(0x800007430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP3_REG_P2_2               , RULL(0x80000B430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP3_REG_P2_2               , RULL(0x80000B430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP3_REG_P2_3               , RULL(0x80000F430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP3_REG_P2_3               , RULL(0x80000F430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_11_RP3_REG_P2_4               , RULL(0x800013430701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_11_RP3_REG_P2_4               , RULL(0x800013430801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP3_REG_P3_0               , RULL(0x8000034307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP3_REG_P3_0               , RULL(0x8000034308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP3_REG_P3_1               , RULL(0x8000074307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP3_REG_P3_1               , RULL(0x8000074308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP3_REG_P3_2               , RULL(0x80000B4307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP3_REG_P3_2               , RULL(0x80000B4308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP3_REG_P3_3               , RULL(0x80000F4307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP3_REG_P3_3               , RULL(0x80000F4308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_11_RP3_REG_P3_4               , RULL(0x8000134307011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_11_RP3_REG_P3_4               , RULL(0x8000134308011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_0                 , RULL(0x800000440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_0               , RULL(0x800000440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_0               , RULL(0x800000440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_1                 , RULL(0x800004440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_1               , RULL(0x800004440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_1               , RULL(0x800004440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_2                 , RULL(0x800008440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_2               , RULL(0x800008440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_2               , RULL(0x800008440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_3                 , RULL(0x80000C440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_3               , RULL(0x80000C440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_3               , RULL(0x80000C440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_4                 , RULL(0x800010440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_4               , RULL(0x800010440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_4               , RULL(0x800010440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP0_REG_P1_0               , RULL(0x800000440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP0_REG_P1_0               , RULL(0x800000440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP0_REG_P1_1               , RULL(0x800004440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP0_REG_P1_1               , RULL(0x800004440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP0_REG_P1_2               , RULL(0x800008440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP0_REG_P1_2               , RULL(0x800008440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP0_REG_P1_3               , RULL(0x80000C440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP0_REG_P1_3               , RULL(0x80000C440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP0_REG_P1_4               , RULL(0x800010440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP0_REG_P1_4               , RULL(0x800010440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP0_REG_P2_0               , RULL(0x800000440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP0_REG_P2_0               , RULL(0x800000440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP0_REG_P2_1               , RULL(0x800004440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP0_REG_P2_1               , RULL(0x800004440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP0_REG_P2_2               , RULL(0x800008440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP0_REG_P2_2               , RULL(0x800008440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP0_REG_P2_3               , RULL(0x80000C440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP0_REG_P2_3               , RULL(0x80000C440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP0_REG_P2_4               , RULL(0x800010440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP0_REG_P2_4               , RULL(0x800010440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP0_REG_P3_0               , RULL(0x8000004407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP0_REG_P3_0               , RULL(0x8000004408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP0_REG_P3_1               , RULL(0x8000044407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP0_REG_P3_1               , RULL(0x8000044408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP0_REG_P3_2               , RULL(0x8000084407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP0_REG_P3_2               , RULL(0x8000084408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP0_REG_P3_3               , RULL(0x80000C4407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP0_REG_P3_3               , RULL(0x80000C4408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP0_REG_P3_4               , RULL(0x8000104407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP0_REG_P3_4               , RULL(0x8000104408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_0                 , RULL(0x800001440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_0               , RULL(0x800001440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_0               , RULL(0x800001440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_1                 , RULL(0x800005440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_1               , RULL(0x800005440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_1               , RULL(0x800005440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_2                 , RULL(0x800009440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_2               , RULL(0x800009440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_2               , RULL(0x800009440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_3                 , RULL(0x80000D440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_3               , RULL(0x80000D440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_3               , RULL(0x80000D440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_4                 , RULL(0x800011440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_4               , RULL(0x800011440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_4               , RULL(0x800011440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP1_REG_P1_0               , RULL(0x800001440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP1_REG_P1_0               , RULL(0x800001440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP1_REG_P1_1               , RULL(0x800005440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP1_REG_P1_1               , RULL(0x800005440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP1_REG_P1_2               , RULL(0x800009440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP1_REG_P1_2               , RULL(0x800009440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP1_REG_P1_3               , RULL(0x80000D440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP1_REG_P1_3               , RULL(0x80000D440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP1_REG_P1_4               , RULL(0x800011440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP1_REG_P1_4               , RULL(0x800011440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP1_REG_P2_0               , RULL(0x800001440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP1_REG_P2_0               , RULL(0x800001440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP1_REG_P2_1               , RULL(0x800005440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP1_REG_P2_1               , RULL(0x800005440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP1_REG_P2_2               , RULL(0x800009440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP1_REG_P2_2               , RULL(0x800009440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP1_REG_P2_3               , RULL(0x80000D440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP1_REG_P2_3               , RULL(0x80000D440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP1_REG_P2_4               , RULL(0x800011440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP1_REG_P2_4               , RULL(0x800011440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP1_REG_P3_0               , RULL(0x8000014407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP1_REG_P3_0               , RULL(0x8000014408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP1_REG_P3_1               , RULL(0x8000054407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP1_REG_P3_1               , RULL(0x8000054408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP1_REG_P3_2               , RULL(0x8000094407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP1_REG_P3_2               , RULL(0x8000094408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP1_REG_P3_3               , RULL(0x80000D4407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP1_REG_P3_3               , RULL(0x80000D4408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP1_REG_P3_4               , RULL(0x8000114407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP1_REG_P3_4               , RULL(0x8000114408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_0                 , RULL(0x800002440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_0               , RULL(0x800002440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_0               , RULL(0x800002440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_1                 , RULL(0x800006440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_1               , RULL(0x800006440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_1               , RULL(0x800006440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_2                 , RULL(0x80000A440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_2               , RULL(0x80000A440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_2               , RULL(0x80000A440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_3                 , RULL(0x80000E440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_3               , RULL(0x80000E440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_3               , RULL(0x80000E440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_4                 , RULL(0x800012440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_4               , RULL(0x800012440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_4               , RULL(0x800012440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP2_REG_P1_0               , RULL(0x800002440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP2_REG_P1_0               , RULL(0x800002440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP2_REG_P1_1               , RULL(0x800006440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP2_REG_P1_1               , RULL(0x800006440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP2_REG_P1_2               , RULL(0x80000A440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP2_REG_P1_2               , RULL(0x80000A440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP2_REG_P1_3               , RULL(0x80000E440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP2_REG_P1_3               , RULL(0x80000E440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP2_REG_P1_4               , RULL(0x800012440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP2_REG_P1_4               , RULL(0x800012440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP2_REG_P2_0               , RULL(0x800002440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP2_REG_P2_0               , RULL(0x800002440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP2_REG_P2_1               , RULL(0x800006440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP2_REG_P2_1               , RULL(0x800006440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP2_REG_P2_2               , RULL(0x80000A440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP2_REG_P2_2               , RULL(0x80000A440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP2_REG_P2_3               , RULL(0x80000E440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP2_REG_P2_3               , RULL(0x80000E440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP2_REG_P2_4               , RULL(0x800012440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP2_REG_P2_4               , RULL(0x800012440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP2_REG_P3_0               , RULL(0x8000024407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP2_REG_P3_0               , RULL(0x8000024408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP2_REG_P3_1               , RULL(0x8000064407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP2_REG_P3_1               , RULL(0x8000064408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP2_REG_P3_2               , RULL(0x80000A4407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP2_REG_P3_2               , RULL(0x80000A4408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP2_REG_P3_3               , RULL(0x80000E4407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP2_REG_P3_3               , RULL(0x80000E4408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP2_REG_P3_4               , RULL(0x8000124407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP2_REG_P3_4               , RULL(0x8000124408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_0                 , RULL(0x800003440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_0               , RULL(0x800003440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_0               , RULL(0x800003440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_1                 , RULL(0x800007440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_1               , RULL(0x800007440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_1               , RULL(0x800007440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_2                 , RULL(0x80000B440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_2               , RULL(0x80000B440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_2               , RULL(0x80000B440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_3                 , RULL(0x80000F440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_3               , RULL(0x80000F440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_3               , RULL(0x80000F440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_4                 , RULL(0x800013440701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_4               , RULL(0x800013440701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_4               , RULL(0x800013440801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP3_REG_P1_0               , RULL(0x800003440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP3_REG_P1_0               , RULL(0x800003440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP3_REG_P1_1               , RULL(0x800007440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP3_REG_P1_1               , RULL(0x800007440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP3_REG_P1_2               , RULL(0x80000B440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP3_REG_P1_2               , RULL(0x80000B440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP3_REG_P1_3               , RULL(0x80000F440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP3_REG_P1_3               , RULL(0x80000F440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_12_RP3_REG_P1_4               , RULL(0x800013440701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_12_RP3_REG_P1_4               , RULL(0x800013440801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP3_REG_P2_0               , RULL(0x800003440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP3_REG_P2_0               , RULL(0x800003440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP3_REG_P2_1               , RULL(0x800007440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP3_REG_P2_1               , RULL(0x800007440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP3_REG_P2_2               , RULL(0x80000B440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP3_REG_P2_2               , RULL(0x80000B440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP3_REG_P2_3               , RULL(0x80000F440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP3_REG_P2_3               , RULL(0x80000F440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_12_RP3_REG_P2_4               , RULL(0x800013440701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_12_RP3_REG_P2_4               , RULL(0x800013440801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP3_REG_P3_0               , RULL(0x8000034407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP3_REG_P3_0               , RULL(0x8000034408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP3_REG_P3_1               , RULL(0x8000074407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP3_REG_P3_1               , RULL(0x8000074408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP3_REG_P3_2               , RULL(0x80000B4407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP3_REG_P3_2               , RULL(0x80000B4408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP3_REG_P3_3               , RULL(0x80000F4407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP3_REG_P3_3               , RULL(0x80000F4408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_12_RP3_REG_P3_4               , RULL(0x8000134407011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_12_RP3_REG_P3_4               , RULL(0x8000134408011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_0                 , RULL(0x800000450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_0               , RULL(0x800000450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_0               , RULL(0x800000450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_1                 , RULL(0x800004450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_1               , RULL(0x800004450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_1               , RULL(0x800004450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_2                 , RULL(0x800008450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_2               , RULL(0x800008450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_2               , RULL(0x800008450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_3                 , RULL(0x80000C450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_3               , RULL(0x80000C450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_3               , RULL(0x80000C450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_4                 , RULL(0x800010450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_4               , RULL(0x800010450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_4               , RULL(0x800010450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP0_REG_P1_0               , RULL(0x800000450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP0_REG_P1_0               , RULL(0x800000450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP0_REG_P1_1               , RULL(0x800004450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP0_REG_P1_1               , RULL(0x800004450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP0_REG_P1_2               , RULL(0x800008450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP0_REG_P1_2               , RULL(0x800008450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP0_REG_P1_3               , RULL(0x80000C450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP0_REG_P1_3               , RULL(0x80000C450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP0_REG_P1_4               , RULL(0x800010450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP0_REG_P1_4               , RULL(0x800010450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP0_REG_P2_0               , RULL(0x800000450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP0_REG_P2_0               , RULL(0x800000450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP0_REG_P2_1               , RULL(0x800004450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP0_REG_P2_1               , RULL(0x800004450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP0_REG_P2_2               , RULL(0x800008450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP0_REG_P2_2               , RULL(0x800008450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP0_REG_P2_3               , RULL(0x80000C450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP0_REG_P2_3               , RULL(0x80000C450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP0_REG_P2_4               , RULL(0x800010450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP0_REG_P2_4               , RULL(0x800010450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP0_REG_P3_0               , RULL(0x8000004507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP0_REG_P3_0               , RULL(0x8000004508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP0_REG_P3_1               , RULL(0x8000044507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP0_REG_P3_1               , RULL(0x8000044508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP0_REG_P3_2               , RULL(0x8000084507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP0_REG_P3_2               , RULL(0x8000084508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP0_REG_P3_3               , RULL(0x80000C4507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP0_REG_P3_3               , RULL(0x80000C4508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP0_REG_P3_4               , RULL(0x8000104507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP0_REG_P3_4               , RULL(0x8000104508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_0                 , RULL(0x800001450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_0               , RULL(0x800001450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_0               , RULL(0x800001450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_1                 , RULL(0x800005450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_1               , RULL(0x800005450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_1               , RULL(0x800005450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_2                 , RULL(0x800009450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_2               , RULL(0x800009450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_2               , RULL(0x800009450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_3                 , RULL(0x80000D450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_3               , RULL(0x80000D450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_3               , RULL(0x80000D450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_4                 , RULL(0x800011450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_4               , RULL(0x800011450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_4               , RULL(0x800011450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP1_REG_P1_0               , RULL(0x800001450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP1_REG_P1_0               , RULL(0x800001450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP1_REG_P1_1               , RULL(0x800005450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP1_REG_P1_1               , RULL(0x800005450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP1_REG_P1_2               , RULL(0x800009450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP1_REG_P1_2               , RULL(0x800009450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP1_REG_P1_3               , RULL(0x80000D450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP1_REG_P1_3               , RULL(0x80000D450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP1_REG_P1_4               , RULL(0x800011450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP1_REG_P1_4               , RULL(0x800011450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP1_REG_P2_0               , RULL(0x800001450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP1_REG_P2_0               , RULL(0x800001450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP1_REG_P2_1               , RULL(0x800005450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP1_REG_P2_1               , RULL(0x800005450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP1_REG_P2_2               , RULL(0x800009450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP1_REG_P2_2               , RULL(0x800009450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP1_REG_P2_3               , RULL(0x80000D450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP1_REG_P2_3               , RULL(0x80000D450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP1_REG_P2_4               , RULL(0x800011450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP1_REG_P2_4               , RULL(0x800011450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP1_REG_P3_0               , RULL(0x8000014507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP1_REG_P3_0               , RULL(0x8000014508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP1_REG_P3_1               , RULL(0x8000054507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP1_REG_P3_1               , RULL(0x8000054508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP1_REG_P3_2               , RULL(0x8000094507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP1_REG_P3_2               , RULL(0x8000094508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP1_REG_P3_3               , RULL(0x80000D4507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP1_REG_P3_3               , RULL(0x80000D4508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP1_REG_P3_4               , RULL(0x8000114507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP1_REG_P3_4               , RULL(0x8000114508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_0                 , RULL(0x800002450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_0               , RULL(0x800002450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_0               , RULL(0x800002450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_1                 , RULL(0x800006450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_1               , RULL(0x800006450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_1               , RULL(0x800006450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_2                 , RULL(0x80000A450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_2               , RULL(0x80000A450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_2               , RULL(0x80000A450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_3                 , RULL(0x80000E450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_3               , RULL(0x80000E450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_3               , RULL(0x80000E450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_4                 , RULL(0x800012450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_4               , RULL(0x800012450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_4               , RULL(0x800012450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP2_REG_P1_0               , RULL(0x800002450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP2_REG_P1_0               , RULL(0x800002450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP2_REG_P1_1               , RULL(0x800006450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP2_REG_P1_1               , RULL(0x800006450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP2_REG_P1_2               , RULL(0x80000A450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP2_REG_P1_2               , RULL(0x80000A450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP2_REG_P1_3               , RULL(0x80000E450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP2_REG_P1_3               , RULL(0x80000E450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP2_REG_P1_4               , RULL(0x800012450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP2_REG_P1_4               , RULL(0x800012450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP2_REG_P2_0               , RULL(0x800002450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP2_REG_P2_0               , RULL(0x800002450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP2_REG_P2_1               , RULL(0x800006450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP2_REG_P2_1               , RULL(0x800006450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP2_REG_P2_2               , RULL(0x80000A450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP2_REG_P2_2               , RULL(0x80000A450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP2_REG_P2_3               , RULL(0x80000E450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP2_REG_P2_3               , RULL(0x80000E450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP2_REG_P2_4               , RULL(0x800012450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP2_REG_P2_4               , RULL(0x800012450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP2_REG_P3_0               , RULL(0x8000024507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP2_REG_P3_0               , RULL(0x8000024508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP2_REG_P3_1               , RULL(0x8000064507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP2_REG_P3_1               , RULL(0x8000064508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP2_REG_P3_2               , RULL(0x80000A4507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP2_REG_P3_2               , RULL(0x80000A4508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP2_REG_P3_3               , RULL(0x80000E4507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP2_REG_P3_3               , RULL(0x80000E4508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP2_REG_P3_4               , RULL(0x8000124507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP2_REG_P3_4               , RULL(0x8000124508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_0                 , RULL(0x800003450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_0               , RULL(0x800003450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_0               , RULL(0x800003450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_1                 , RULL(0x800007450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_1               , RULL(0x800007450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_1               , RULL(0x800007450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_2                 , RULL(0x80000B450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_2               , RULL(0x80000B450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_2               , RULL(0x80000B450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_3                 , RULL(0x80000F450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_3               , RULL(0x80000F450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_3               , RULL(0x80000F450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_4                 , RULL(0x800013450701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_4               , RULL(0x800013450701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_4               , RULL(0x800013450801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP3_REG_P1_0               , RULL(0x800003450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP3_REG_P1_0               , RULL(0x800003450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP3_REG_P1_1               , RULL(0x800007450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP3_REG_P1_1               , RULL(0x800007450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP3_REG_P1_2               , RULL(0x80000B450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP3_REG_P1_2               , RULL(0x80000B450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP3_REG_P1_3               , RULL(0x80000F450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP3_REG_P1_3               , RULL(0x80000F450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_13_RP3_REG_P1_4               , RULL(0x800013450701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_13_RP3_REG_P1_4               , RULL(0x800013450801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP3_REG_P2_0               , RULL(0x800003450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP3_REG_P2_0               , RULL(0x800003450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP3_REG_P2_1               , RULL(0x800007450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP3_REG_P2_1               , RULL(0x800007450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP3_REG_P2_2               , RULL(0x80000B450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP3_REG_P2_2               , RULL(0x80000B450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP3_REG_P2_3               , RULL(0x80000F450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP3_REG_P2_3               , RULL(0x80000F450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_13_RP3_REG_P2_4               , RULL(0x800013450701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_13_RP3_REG_P2_4               , RULL(0x800013450801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP3_REG_P3_0               , RULL(0x8000034507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP3_REG_P3_0               , RULL(0x8000034508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP3_REG_P3_1               , RULL(0x8000074507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP3_REG_P3_1               , RULL(0x8000074508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP3_REG_P3_2               , RULL(0x80000B4507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP3_REG_P3_2               , RULL(0x80000B4508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP3_REG_P3_3               , RULL(0x80000F4507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP3_REG_P3_3               , RULL(0x80000F4508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_13_RP3_REG_P3_4               , RULL(0x8000134507011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_13_RP3_REG_P3_4               , RULL(0x8000134508011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_0                 , RULL(0x800000460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_0               , RULL(0x800000460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_0               , RULL(0x800000460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_1                 , RULL(0x800004460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_1               , RULL(0x800004460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_1               , RULL(0x800004460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_2                 , RULL(0x800008460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_2               , RULL(0x800008460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_2               , RULL(0x800008460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_3                 , RULL(0x80000C460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_3               , RULL(0x80000C460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_3               , RULL(0x80000C460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_4                 , RULL(0x800010460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_4               , RULL(0x800010460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_4               , RULL(0x800010460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP0_REG_P1_0               , RULL(0x800000460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP0_REG_P1_0               , RULL(0x800000460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP0_REG_P1_1               , RULL(0x800004460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP0_REG_P1_1               , RULL(0x800004460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP0_REG_P1_2               , RULL(0x800008460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP0_REG_P1_2               , RULL(0x800008460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP0_REG_P1_3               , RULL(0x80000C460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP0_REG_P1_3               , RULL(0x80000C460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP0_REG_P1_4               , RULL(0x800010460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP0_REG_P1_4               , RULL(0x800010460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP0_REG_P2_0               , RULL(0x800000460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP0_REG_P2_0               , RULL(0x800000460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP0_REG_P2_1               , RULL(0x800004460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP0_REG_P2_1               , RULL(0x800004460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP0_REG_P2_2               , RULL(0x800008460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP0_REG_P2_2               , RULL(0x800008460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP0_REG_P2_3               , RULL(0x80000C460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP0_REG_P2_3               , RULL(0x80000C460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP0_REG_P2_4               , RULL(0x800010460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP0_REG_P2_4               , RULL(0x800010460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP0_REG_P3_0               , RULL(0x8000004607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP0_REG_P3_0               , RULL(0x8000004608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP0_REG_P3_1               , RULL(0x8000044607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP0_REG_P3_1               , RULL(0x8000044608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP0_REG_P3_2               , RULL(0x8000084607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP0_REG_P3_2               , RULL(0x8000084608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP0_REG_P3_3               , RULL(0x80000C4607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP0_REG_P3_3               , RULL(0x80000C4608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP0_REG_P3_4               , RULL(0x8000104607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP0_REG_P3_4               , RULL(0x8000104608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_0                 , RULL(0x800001460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_0               , RULL(0x800001460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_0               , RULL(0x800001460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_1                 , RULL(0x800005460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_1               , RULL(0x800005460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_1               , RULL(0x800005460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_2                 , RULL(0x800009460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_2               , RULL(0x800009460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_2               , RULL(0x800009460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_3                 , RULL(0x80000D460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_3               , RULL(0x80000D460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_3               , RULL(0x80000D460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_4                 , RULL(0x800011460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_4               , RULL(0x800011460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_4               , RULL(0x800011460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP1_REG_P1_0               , RULL(0x800001460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP1_REG_P1_0               , RULL(0x800001460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP1_REG_P1_1               , RULL(0x800005460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP1_REG_P1_1               , RULL(0x800005460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP1_REG_P1_2               , RULL(0x800009460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP1_REG_P1_2               , RULL(0x800009460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP1_REG_P1_3               , RULL(0x80000D460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP1_REG_P1_3               , RULL(0x80000D460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP1_REG_P1_4               , RULL(0x800011460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP1_REG_P1_4               , RULL(0x800011460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP1_REG_P2_0               , RULL(0x800001460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP1_REG_P2_0               , RULL(0x800001460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP1_REG_P2_1               , RULL(0x800005460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP1_REG_P2_1               , RULL(0x800005460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP1_REG_P2_2               , RULL(0x800009460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP1_REG_P2_2               , RULL(0x800009460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP1_REG_P2_3               , RULL(0x80000D460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP1_REG_P2_3               , RULL(0x80000D460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP1_REG_P2_4               , RULL(0x800011460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP1_REG_P2_4               , RULL(0x800011460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP1_REG_P3_0               , RULL(0x8000014607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP1_REG_P3_0               , RULL(0x8000014608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP1_REG_P3_1               , RULL(0x8000054607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP1_REG_P3_1               , RULL(0x8000054608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP1_REG_P3_2               , RULL(0x8000094607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP1_REG_P3_2               , RULL(0x8000094608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP1_REG_P3_3               , RULL(0x80000D4607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP1_REG_P3_3               , RULL(0x80000D4608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP1_REG_P3_4               , RULL(0x8000114607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP1_REG_P3_4               , RULL(0x8000114608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_0                 , RULL(0x800002460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_0               , RULL(0x800002460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_0               , RULL(0x800002460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_1                 , RULL(0x800006460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_1               , RULL(0x800006460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_1               , RULL(0x800006460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_2                 , RULL(0x80000A460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_2               , RULL(0x80000A460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_2               , RULL(0x80000A460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_3                 , RULL(0x80000E460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_3               , RULL(0x80000E460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_3               , RULL(0x80000E460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_4                 , RULL(0x800012460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_4               , RULL(0x800012460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_4               , RULL(0x800012460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP2_REG_P1_0               , RULL(0x800002460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP2_REG_P1_0               , RULL(0x800002460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP2_REG_P1_1               , RULL(0x800006460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP2_REG_P1_1               , RULL(0x800006460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP2_REG_P1_2               , RULL(0x80000A460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP2_REG_P1_2               , RULL(0x80000A460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP2_REG_P1_3               , RULL(0x80000E460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP2_REG_P1_3               , RULL(0x80000E460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP2_REG_P1_4               , RULL(0x800012460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP2_REG_P1_4               , RULL(0x800012460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP2_REG_P2_0               , RULL(0x800002460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP2_REG_P2_0               , RULL(0x800002460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP2_REG_P2_1               , RULL(0x800006460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP2_REG_P2_1               , RULL(0x800006460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP2_REG_P2_2               , RULL(0x80000A460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP2_REG_P2_2               , RULL(0x80000A460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP2_REG_P2_3               , RULL(0x80000E460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP2_REG_P2_3               , RULL(0x80000E460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP2_REG_P2_4               , RULL(0x800012460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP2_REG_P2_4               , RULL(0x800012460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP2_REG_P3_0               , RULL(0x8000024607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP2_REG_P3_0               , RULL(0x8000024608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP2_REG_P3_1               , RULL(0x8000064607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP2_REG_P3_1               , RULL(0x8000064608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP2_REG_P3_2               , RULL(0x80000A4607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP2_REG_P3_2               , RULL(0x80000A4608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP2_REG_P3_3               , RULL(0x80000E4607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP2_REG_P3_3               , RULL(0x80000E4608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP2_REG_P3_4               , RULL(0x8000124607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP2_REG_P3_4               , RULL(0x8000124608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_0                 , RULL(0x800003460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_0               , RULL(0x800003460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_0               , RULL(0x800003460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_1                 , RULL(0x800007460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_1               , RULL(0x800007460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_1               , RULL(0x800007460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_2                 , RULL(0x80000B460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_2               , RULL(0x80000B460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_2               , RULL(0x80000B460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_3                 , RULL(0x80000F460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_3               , RULL(0x80000F460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_3               , RULL(0x80000F460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_4                 , RULL(0x800013460701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_4               , RULL(0x800013460701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_4               , RULL(0x800013460801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP3_REG_P1_0               , RULL(0x800003460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP3_REG_P1_0               , RULL(0x800003460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP3_REG_P1_1               , RULL(0x800007460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP3_REG_P1_1               , RULL(0x800007460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP3_REG_P1_2               , RULL(0x80000B460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP3_REG_P1_2               , RULL(0x80000B460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP3_REG_P1_3               , RULL(0x80000F460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP3_REG_P1_3               , RULL(0x80000F460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_14_RP3_REG_P1_4               , RULL(0x800013460701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_14_RP3_REG_P1_4               , RULL(0x800013460801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP3_REG_P2_0               , RULL(0x800003460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP3_REG_P2_0               , RULL(0x800003460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP3_REG_P2_1               , RULL(0x800007460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP3_REG_P2_1               , RULL(0x800007460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP3_REG_P2_2               , RULL(0x80000B460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP3_REG_P2_2               , RULL(0x80000B460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP3_REG_P2_3               , RULL(0x80000F460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP3_REG_P2_3               , RULL(0x80000F460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_14_RP3_REG_P2_4               , RULL(0x800013460701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_14_RP3_REG_P2_4               , RULL(0x800013460801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP3_REG_P3_0               , RULL(0x8000034607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP3_REG_P3_0               , RULL(0x8000034608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP3_REG_P3_1               , RULL(0x8000074607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP3_REG_P3_1               , RULL(0x8000074608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP3_REG_P3_2               , RULL(0x80000B4607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP3_REG_P3_2               , RULL(0x80000B4608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP3_REG_P3_3               , RULL(0x80000F4607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP3_REG_P3_3               , RULL(0x80000F4608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_14_RP3_REG_P3_4               , RULL(0x8000134607011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_14_RP3_REG_P3_4               , RULL(0x8000134608011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_0                 , RULL(0x800000470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_0               , RULL(0x800000470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_0               , RULL(0x800000470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_1                 , RULL(0x800004470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_1               , RULL(0x800004470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_1               , RULL(0x800004470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_2                 , RULL(0x800008470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_2               , RULL(0x800008470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_2               , RULL(0x800008470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_3                 , RULL(0x80000C470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_3               , RULL(0x80000C470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_3               , RULL(0x80000C470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_4                 , RULL(0x800010470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_4               , RULL(0x800010470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_4               , RULL(0x800010470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP0_REG_P1_0               , RULL(0x800000470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP0_REG_P1_0               , RULL(0x800000470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP0_REG_P1_1               , RULL(0x800004470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP0_REG_P1_1               , RULL(0x800004470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP0_REG_P1_2               , RULL(0x800008470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP0_REG_P1_2               , RULL(0x800008470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP0_REG_P1_3               , RULL(0x80000C470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP0_REG_P1_3               , RULL(0x80000C470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP0_REG_P1_4               , RULL(0x800010470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP0_REG_P1_4               , RULL(0x800010470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP0_REG_P2_0               , RULL(0x800000470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP0_REG_P2_0               , RULL(0x800000470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP0_REG_P2_1               , RULL(0x800004470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP0_REG_P2_1               , RULL(0x800004470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP0_REG_P2_2               , RULL(0x800008470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP0_REG_P2_2               , RULL(0x800008470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP0_REG_P2_3               , RULL(0x80000C470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP0_REG_P2_3               , RULL(0x80000C470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP0_REG_P2_4               , RULL(0x800010470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP0_REG_P2_4               , RULL(0x800010470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP0_REG_P3_0               , RULL(0x8000004707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP0_REG_P3_0               , RULL(0x8000004708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP0_REG_P3_1               , RULL(0x8000044707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP0_REG_P3_1               , RULL(0x8000044708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP0_REG_P3_2               , RULL(0x8000084707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP0_REG_P3_2               , RULL(0x8000084708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP0_REG_P3_3               , RULL(0x80000C4707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP0_REG_P3_3               , RULL(0x80000C4708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP0_REG_P3_4               , RULL(0x8000104707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP0_REG_P3_4               , RULL(0x8000104708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_0                 , RULL(0x800001470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_0               , RULL(0x800001470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_0               , RULL(0x800001470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_1                 , RULL(0x800005470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_1               , RULL(0x800005470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_1               , RULL(0x800005470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_2                 , RULL(0x800009470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_2               , RULL(0x800009470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_2               , RULL(0x800009470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_3                 , RULL(0x80000D470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_3               , RULL(0x80000D470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_3               , RULL(0x80000D470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_4                 , RULL(0x800011470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_4               , RULL(0x800011470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_4               , RULL(0x800011470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP1_REG_P1_0               , RULL(0x800001470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP1_REG_P1_0               , RULL(0x800001470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP1_REG_P1_1               , RULL(0x800005470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP1_REG_P1_1               , RULL(0x800005470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP1_REG_P1_2               , RULL(0x800009470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP1_REG_P1_2               , RULL(0x800009470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP1_REG_P1_3               , RULL(0x80000D470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP1_REG_P1_3               , RULL(0x80000D470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP1_REG_P1_4               , RULL(0x800011470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP1_REG_P1_4               , RULL(0x800011470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP1_REG_P2_0               , RULL(0x800001470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP1_REG_P2_0               , RULL(0x800001470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP1_REG_P2_1               , RULL(0x800005470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP1_REG_P2_1               , RULL(0x800005470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP1_REG_P2_2               , RULL(0x800009470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP1_REG_P2_2               , RULL(0x800009470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP1_REG_P2_3               , RULL(0x80000D470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP1_REG_P2_3               , RULL(0x80000D470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP1_REG_P2_4               , RULL(0x800011470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP1_REG_P2_4               , RULL(0x800011470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP1_REG_P3_0               , RULL(0x8000014707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP1_REG_P3_0               , RULL(0x8000014708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP1_REG_P3_1               , RULL(0x8000054707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP1_REG_P3_1               , RULL(0x8000054708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP1_REG_P3_2               , RULL(0x8000094707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP1_REG_P3_2               , RULL(0x8000094708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP1_REG_P3_3               , RULL(0x80000D4707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP1_REG_P3_3               , RULL(0x80000D4708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP1_REG_P3_4               , RULL(0x8000114707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP1_REG_P3_4               , RULL(0x8000114708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_0                 , RULL(0x800002470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_0               , RULL(0x800002470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_0               , RULL(0x800002470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_1                 , RULL(0x800006470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_1               , RULL(0x800006470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_1               , RULL(0x800006470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_2                 , RULL(0x80000A470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_2               , RULL(0x80000A470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_2               , RULL(0x80000A470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_3                 , RULL(0x80000E470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_3               , RULL(0x80000E470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_3               , RULL(0x80000E470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_4                 , RULL(0x800012470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_4               , RULL(0x800012470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_4               , RULL(0x800012470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP2_REG_P1_0               , RULL(0x800002470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP2_REG_P1_0               , RULL(0x800002470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP2_REG_P1_1               , RULL(0x800006470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP2_REG_P1_1               , RULL(0x800006470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP2_REG_P1_2               , RULL(0x80000A470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP2_REG_P1_2               , RULL(0x80000A470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP2_REG_P1_3               , RULL(0x80000E470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP2_REG_P1_3               , RULL(0x80000E470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP2_REG_P1_4               , RULL(0x800012470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP2_REG_P1_4               , RULL(0x800012470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP2_REG_P2_0               , RULL(0x800002470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP2_REG_P2_0               , RULL(0x800002470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP2_REG_P2_1               , RULL(0x800006470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP2_REG_P2_1               , RULL(0x800006470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP2_REG_P2_2               , RULL(0x80000A470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP2_REG_P2_2               , RULL(0x80000A470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP2_REG_P2_3               , RULL(0x80000E470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP2_REG_P2_3               , RULL(0x80000E470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP2_REG_P2_4               , RULL(0x800012470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP2_REG_P2_4               , RULL(0x800012470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP2_REG_P3_0               , RULL(0x8000024707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP2_REG_P3_0               , RULL(0x8000024708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP2_REG_P3_1               , RULL(0x8000064707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP2_REG_P3_1               , RULL(0x8000064708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP2_REG_P3_2               , RULL(0x80000A4707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP2_REG_P3_2               , RULL(0x80000A4708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP2_REG_P3_3               , RULL(0x80000E4707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP2_REG_P3_3               , RULL(0x80000E4708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP2_REG_P3_4               , RULL(0x8000124707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP2_REG_P3_4               , RULL(0x8000124708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_0                 , RULL(0x800003470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_0               , RULL(0x800003470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_0               , RULL(0x800003470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_1                 , RULL(0x800007470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_1               , RULL(0x800007470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_1               , RULL(0x800007470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_2                 , RULL(0x80000B470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_2               , RULL(0x80000B470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_2               , RULL(0x80000B470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_3                 , RULL(0x80000F470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_3               , RULL(0x80000F470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_3               , RULL(0x80000F470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_4                 , RULL(0x800013470701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_4               , RULL(0x800013470701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_4               , RULL(0x800013470801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP3_REG_P1_0               , RULL(0x800003470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP3_REG_P1_0               , RULL(0x800003470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP3_REG_P1_1               , RULL(0x800007470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP3_REG_P1_1               , RULL(0x800007470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP3_REG_P1_2               , RULL(0x80000B470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP3_REG_P1_2               , RULL(0x80000B470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP3_REG_P1_3               , RULL(0x80000F470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP3_REG_P1_3               , RULL(0x80000F470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_15_RP3_REG_P1_4               , RULL(0x800013470701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_15_RP3_REG_P1_4               , RULL(0x800013470801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP3_REG_P2_0               , RULL(0x800003470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP3_REG_P2_0               , RULL(0x800003470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP3_REG_P2_1               , RULL(0x800007470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP3_REG_P2_1               , RULL(0x800007470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP3_REG_P2_2               , RULL(0x80000B470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP3_REG_P2_2               , RULL(0x80000B470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP3_REG_P2_3               , RULL(0x80000F470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP3_REG_P2_3               , RULL(0x80000F470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_15_RP3_REG_P2_4               , RULL(0x800013470701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_15_RP3_REG_P2_4               , RULL(0x800013470801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP3_REG_P3_0               , RULL(0x8000034707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP3_REG_P3_0               , RULL(0x8000034708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP3_REG_P3_1               , RULL(0x8000074707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP3_REG_P3_1               , RULL(0x8000074708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP3_REG_P3_2               , RULL(0x80000B4707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP3_REG_P3_2               , RULL(0x80000B4708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP3_REG_P3_3               , RULL(0x80000F4707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP3_REG_P3_3               , RULL(0x80000F4708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_15_RP3_REG_P3_4               , RULL(0x8000134707011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_15_RP3_REG_P3_4               , RULL(0x8000134708011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_0                 , RULL(0x800000480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_0               , RULL(0x800000480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_0               , RULL(0x800000480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_1                 , RULL(0x800004480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_1               , RULL(0x800004480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_1               , RULL(0x800004480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_2                 , RULL(0x800008480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_2               , RULL(0x800008480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_2               , RULL(0x800008480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_3                 , RULL(0x80000C480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_3               , RULL(0x80000C480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_3               , RULL(0x80000C480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_4                 , RULL(0x800010480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_4               , RULL(0x800010480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_4               , RULL(0x800010480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP0_REG_P1_0               , RULL(0x800000480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP0_REG_P1_0               , RULL(0x800000480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP0_REG_P1_1               , RULL(0x800004480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP0_REG_P1_1               , RULL(0x800004480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP0_REG_P1_2               , RULL(0x800008480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP0_REG_P1_2               , RULL(0x800008480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP0_REG_P1_3               , RULL(0x80000C480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP0_REG_P1_3               , RULL(0x80000C480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP0_REG_P1_4               , RULL(0x800010480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP0_REG_P1_4               , RULL(0x800010480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP0_REG_P2_0               , RULL(0x800000480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP0_REG_P2_0               , RULL(0x800000480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP0_REG_P2_1               , RULL(0x800004480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP0_REG_P2_1               , RULL(0x800004480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP0_REG_P2_2               , RULL(0x800008480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP0_REG_P2_2               , RULL(0x800008480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP0_REG_P2_3               , RULL(0x80000C480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP0_REG_P2_3               , RULL(0x80000C480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP0_REG_P2_4               , RULL(0x800010480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP0_REG_P2_4               , RULL(0x800010480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP0_REG_P3_0               , RULL(0x8000004807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP0_REG_P3_0               , RULL(0x8000004808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP0_REG_P3_1               , RULL(0x8000044807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP0_REG_P3_1               , RULL(0x8000044808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP0_REG_P3_2               , RULL(0x8000084807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP0_REG_P3_2               , RULL(0x8000084808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP0_REG_P3_3               , RULL(0x80000C4807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP0_REG_P3_3               , RULL(0x80000C4808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP0_REG_P3_4               , RULL(0x8000104807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP0_REG_P3_4               , RULL(0x8000104808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_0                 , RULL(0x800001480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_0               , RULL(0x800001480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_0               , RULL(0x800001480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_1                 , RULL(0x800005480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_1               , RULL(0x800005480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_1               , RULL(0x800005480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_2                 , RULL(0x800009480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_2               , RULL(0x800009480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_2               , RULL(0x800009480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_3                 , RULL(0x80000D480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_3               , RULL(0x80000D480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_3               , RULL(0x80000D480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_4                 , RULL(0x800011480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_4               , RULL(0x800011480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_4               , RULL(0x800011480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP1_REG_P1_0               , RULL(0x800001480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP1_REG_P1_0               , RULL(0x800001480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP1_REG_P1_1               , RULL(0x800005480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP1_REG_P1_1               , RULL(0x800005480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP1_REG_P1_2               , RULL(0x800009480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP1_REG_P1_2               , RULL(0x800009480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP1_REG_P1_3               , RULL(0x80000D480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP1_REG_P1_3               , RULL(0x80000D480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP1_REG_P1_4               , RULL(0x800011480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP1_REG_P1_4               , RULL(0x800011480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP1_REG_P2_0               , RULL(0x800001480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP1_REG_P2_0               , RULL(0x800001480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP1_REG_P2_1               , RULL(0x800005480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP1_REG_P2_1               , RULL(0x800005480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP1_REG_P2_2               , RULL(0x800009480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP1_REG_P2_2               , RULL(0x800009480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP1_REG_P2_3               , RULL(0x80000D480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP1_REG_P2_3               , RULL(0x80000D480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP1_REG_P2_4               , RULL(0x800011480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP1_REG_P2_4               , RULL(0x800011480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP1_REG_P3_0               , RULL(0x8000014807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP1_REG_P3_0               , RULL(0x8000014808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP1_REG_P3_1               , RULL(0x8000054807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP1_REG_P3_1               , RULL(0x8000054808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP1_REG_P3_2               , RULL(0x8000094807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP1_REG_P3_2               , RULL(0x8000094808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP1_REG_P3_3               , RULL(0x80000D4807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP1_REG_P3_3               , RULL(0x80000D4808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP1_REG_P3_4               , RULL(0x8000114807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP1_REG_P3_4               , RULL(0x8000114808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_0                 , RULL(0x800002480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_0               , RULL(0x800002480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_0               , RULL(0x800002480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_1                 , RULL(0x800006480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_1               , RULL(0x800006480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_1               , RULL(0x800006480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_2                 , RULL(0x80000A480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_2               , RULL(0x80000A480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_2               , RULL(0x80000A480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_3                 , RULL(0x80000E480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_3               , RULL(0x80000E480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_3               , RULL(0x80000E480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_4                 , RULL(0x800012480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_4               , RULL(0x800012480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_4               , RULL(0x800012480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP2_REG_P1_0               , RULL(0x800002480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP2_REG_P1_0               , RULL(0x800002480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP2_REG_P1_1               , RULL(0x800006480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP2_REG_P1_1               , RULL(0x800006480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP2_REG_P1_2               , RULL(0x80000A480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP2_REG_P1_2               , RULL(0x80000A480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP2_REG_P1_3               , RULL(0x80000E480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP2_REG_P1_3               , RULL(0x80000E480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP2_REG_P1_4               , RULL(0x800012480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP2_REG_P1_4               , RULL(0x800012480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP2_REG_P2_0               , RULL(0x800002480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP2_REG_P2_0               , RULL(0x800002480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP2_REG_P2_1               , RULL(0x800006480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP2_REG_P2_1               , RULL(0x800006480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP2_REG_P2_2               , RULL(0x80000A480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP2_REG_P2_2               , RULL(0x80000A480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP2_REG_P2_3               , RULL(0x80000E480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP2_REG_P2_3               , RULL(0x80000E480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP2_REG_P2_4               , RULL(0x800012480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP2_REG_P2_4               , RULL(0x800012480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP2_REG_P3_0               , RULL(0x8000024807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP2_REG_P3_0               , RULL(0x8000024808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP2_REG_P3_1               , RULL(0x8000064807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP2_REG_P3_1               , RULL(0x8000064808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP2_REG_P3_2               , RULL(0x80000A4807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP2_REG_P3_2               , RULL(0x80000A4808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP2_REG_P3_3               , RULL(0x80000E4807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP2_REG_P3_3               , RULL(0x80000E4808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP2_REG_P3_4               , RULL(0x8000124807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP2_REG_P3_4               , RULL(0x8000124808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_0                 , RULL(0x800003480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_0               , RULL(0x800003480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_0               , RULL(0x800003480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_1                 , RULL(0x800007480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_1               , RULL(0x800007480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_1               , RULL(0x800007480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_2                 , RULL(0x80000B480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_2               , RULL(0x80000B480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_2               , RULL(0x80000B480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_3                 , RULL(0x80000F480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_3               , RULL(0x80000F480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_3               , RULL(0x80000F480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_4                 , RULL(0x800013480701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_4               , RULL(0x800013480701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_4               , RULL(0x800013480801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP3_REG_P1_0               , RULL(0x800003480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP3_REG_P1_0               , RULL(0x800003480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP3_REG_P1_1               , RULL(0x800007480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP3_REG_P1_1               , RULL(0x800007480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP3_REG_P1_2               , RULL(0x80000B480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP3_REG_P1_2               , RULL(0x80000B480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP3_REG_P1_3               , RULL(0x80000F480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP3_REG_P1_3               , RULL(0x80000F480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_16_RP3_REG_P1_4               , RULL(0x800013480701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_16_RP3_REG_P1_4               , RULL(0x800013480801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP3_REG_P2_0               , RULL(0x800003480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP3_REG_P2_0               , RULL(0x800003480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP3_REG_P2_1               , RULL(0x800007480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP3_REG_P2_1               , RULL(0x800007480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP3_REG_P2_2               , RULL(0x80000B480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP3_REG_P2_2               , RULL(0x80000B480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP3_REG_P2_3               , RULL(0x80000F480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP3_REG_P2_3               , RULL(0x80000F480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_16_RP3_REG_P2_4               , RULL(0x800013480701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_16_RP3_REG_P2_4               , RULL(0x800013480801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP3_REG_P3_0               , RULL(0x8000034807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP3_REG_P3_0               , RULL(0x8000034808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP3_REG_P3_1               , RULL(0x8000074807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP3_REG_P3_1               , RULL(0x8000074808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP3_REG_P3_2               , RULL(0x80000B4807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP3_REG_P3_2               , RULL(0x80000B4808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP3_REG_P3_3               , RULL(0x80000F4807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP3_REG_P3_3               , RULL(0x80000F4808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_16_RP3_REG_P3_4               , RULL(0x8000134807011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_16_RP3_REG_P3_4               , RULL(0x8000134808011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_0                 , RULL(0x8000004A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_0               , RULL(0x8000004A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_0               , RULL(0x8000004A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_1                 , RULL(0x8000044A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_1               , RULL(0x8000044A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_1               , RULL(0x8000044A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_2                 , RULL(0x8000084A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_2               , RULL(0x8000084A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_2               , RULL(0x8000084A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_3                 , RULL(0x80000C4A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_3               , RULL(0x80000C4A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_3               , RULL(0x80000C4A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_4                 , RULL(0x8000104A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_4               , RULL(0x8000104A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_4               , RULL(0x8000104A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP0_REG_P1_0               , RULL(0x8000004A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP0_REG_P1_0               , RULL(0x8000004A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP0_REG_P1_1               , RULL(0x8000044A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP0_REG_P1_1               , RULL(0x8000044A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP0_REG_P1_2               , RULL(0x8000084A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP0_REG_P1_2               , RULL(0x8000084A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP0_REG_P1_3               , RULL(0x80000C4A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP0_REG_P1_3               , RULL(0x80000C4A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP0_REG_P1_4               , RULL(0x8000104A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP0_REG_P1_4               , RULL(0x8000104A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP0_REG_P2_0               , RULL(0x8000004A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP0_REG_P2_0               , RULL(0x8000004A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP0_REG_P2_1               , RULL(0x8000044A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP0_REG_P2_1               , RULL(0x8000044A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP0_REG_P2_2               , RULL(0x8000084A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP0_REG_P2_2               , RULL(0x8000084A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP0_REG_P2_3               , RULL(0x80000C4A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP0_REG_P2_3               , RULL(0x80000C4A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP0_REG_P2_4               , RULL(0x8000104A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP0_REG_P2_4               , RULL(0x8000104A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP0_REG_P3_0               , RULL(0x8000004A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP0_REG_P3_0               , RULL(0x8000004A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP0_REG_P3_1               , RULL(0x8000044A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP0_REG_P3_1               , RULL(0x8000044A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP0_REG_P3_2               , RULL(0x8000084A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP0_REG_P3_2               , RULL(0x8000084A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP0_REG_P3_3               , RULL(0x80000C4A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP0_REG_P3_3               , RULL(0x80000C4A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP0_REG_P3_4               , RULL(0x8000104A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP0_REG_P3_4               , RULL(0x8000104A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_0                 , RULL(0x8000014A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_0               , RULL(0x8000014A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_0               , RULL(0x8000014A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_1                 , RULL(0x8000054A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_1               , RULL(0x8000054A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_1               , RULL(0x8000054A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_2                 , RULL(0x8000094A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_2               , RULL(0x8000094A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_2               , RULL(0x8000094A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_3                 , RULL(0x80000D4A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_3               , RULL(0x80000D4A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_3               , RULL(0x80000D4A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_4                 , RULL(0x8000114A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_4               , RULL(0x8000114A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_4               , RULL(0x8000114A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP1_REG_P1_0               , RULL(0x8000014A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP1_REG_P1_0               , RULL(0x8000014A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP1_REG_P1_1               , RULL(0x8000054A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP1_REG_P1_1               , RULL(0x8000054A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP1_REG_P1_2               , RULL(0x8000094A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP1_REG_P1_2               , RULL(0x8000094A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP1_REG_P1_3               , RULL(0x80000D4A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP1_REG_P1_3               , RULL(0x80000D4A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP1_REG_P1_4               , RULL(0x8000114A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP1_REG_P1_4               , RULL(0x8000114A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP1_REG_P2_0               , RULL(0x8000014A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP1_REG_P2_0               , RULL(0x8000014A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP1_REG_P2_1               , RULL(0x8000054A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP1_REG_P2_1               , RULL(0x8000054A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP1_REG_P2_2               , RULL(0x8000094A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP1_REG_P2_2               , RULL(0x8000094A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP1_REG_P2_3               , RULL(0x80000D4A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP1_REG_P2_3               , RULL(0x80000D4A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP1_REG_P2_4               , RULL(0x8000114A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP1_REG_P2_4               , RULL(0x8000114A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP1_REG_P3_0               , RULL(0x8000014A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP1_REG_P3_0               , RULL(0x8000014A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP1_REG_P3_1               , RULL(0x8000054A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP1_REG_P3_1               , RULL(0x8000054A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP1_REG_P3_2               , RULL(0x8000094A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP1_REG_P3_2               , RULL(0x8000094A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP1_REG_P3_3               , RULL(0x80000D4A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP1_REG_P3_3               , RULL(0x80000D4A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP1_REG_P3_4               , RULL(0x8000114A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP1_REG_P3_4               , RULL(0x8000114A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_0                 , RULL(0x8000024A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_0               , RULL(0x8000024A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_0               , RULL(0x8000024A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_1                 , RULL(0x8000064A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_1               , RULL(0x8000064A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_1               , RULL(0x8000064A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_2                 , RULL(0x80000A4A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_2               , RULL(0x80000A4A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_2               , RULL(0x80000A4A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_3                 , RULL(0x80000E4A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_3               , RULL(0x80000E4A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_3               , RULL(0x80000E4A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_4                 , RULL(0x8000124A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_4               , RULL(0x8000124A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_4               , RULL(0x8000124A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP2_REG_P1_0               , RULL(0x8000024A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP2_REG_P1_0               , RULL(0x8000024A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP2_REG_P1_1               , RULL(0x8000064A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP2_REG_P1_1               , RULL(0x8000064A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP2_REG_P1_2               , RULL(0x80000A4A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP2_REG_P1_2               , RULL(0x80000A4A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP2_REG_P1_3               , RULL(0x80000E4A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP2_REG_P1_3               , RULL(0x80000E4A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP2_REG_P1_4               , RULL(0x8000124A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP2_REG_P1_4               , RULL(0x8000124A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP2_REG_P2_0               , RULL(0x8000024A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP2_REG_P2_0               , RULL(0x8000024A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP2_REG_P2_1               , RULL(0x8000064A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP2_REG_P2_1               , RULL(0x8000064A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP2_REG_P2_2               , RULL(0x80000A4A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP2_REG_P2_2               , RULL(0x80000A4A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP2_REG_P2_3               , RULL(0x80000E4A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP2_REG_P2_3               , RULL(0x80000E4A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP2_REG_P2_4               , RULL(0x8000124A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP2_REG_P2_4               , RULL(0x8000124A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP2_REG_P3_0               , RULL(0x8000024A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP2_REG_P3_0               , RULL(0x8000024A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP2_REG_P3_1               , RULL(0x8000064A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP2_REG_P3_1               , RULL(0x8000064A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP2_REG_P3_2               , RULL(0x80000A4A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP2_REG_P3_2               , RULL(0x80000A4A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP2_REG_P3_3               , RULL(0x80000E4A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP2_REG_P3_3               , RULL(0x80000E4A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP2_REG_P3_4               , RULL(0x8000124A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP2_REG_P3_4               , RULL(0x8000124A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_0                 , RULL(0x8000034A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_0               , RULL(0x8000034A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_0               , RULL(0x8000034A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_1                 , RULL(0x8000074A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_1               , RULL(0x8000074A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_1               , RULL(0x8000074A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_2                 , RULL(0x80000B4A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_2               , RULL(0x80000B4A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_2               , RULL(0x80000B4A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_3                 , RULL(0x80000F4A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_3               , RULL(0x80000F4A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_3               , RULL(0x80000F4A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_4                 , RULL(0x8000134A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_4               , RULL(0x8000134A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_4               , RULL(0x8000134A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP3_REG_P1_0               , RULL(0x8000034A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP3_REG_P1_0               , RULL(0x8000034A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP3_REG_P1_1               , RULL(0x8000074A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP3_REG_P1_1               , RULL(0x8000074A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP3_REG_P1_2               , RULL(0x80000B4A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP3_REG_P1_2               , RULL(0x80000B4A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP3_REG_P1_3               , RULL(0x80000F4A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP3_REG_P1_3               , RULL(0x80000F4A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_18_RP3_REG_P1_4               , RULL(0x8000134A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_18_RP3_REG_P1_4               , RULL(0x8000134A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP3_REG_P2_0               , RULL(0x8000034A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP3_REG_P2_0               , RULL(0x8000034A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP3_REG_P2_1               , RULL(0x8000074A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP3_REG_P2_1               , RULL(0x8000074A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP3_REG_P2_2               , RULL(0x80000B4A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP3_REG_P2_2               , RULL(0x80000B4A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP3_REG_P2_3               , RULL(0x80000F4A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP3_REG_P2_3               , RULL(0x80000F4A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_18_RP3_REG_P2_4               , RULL(0x8000134A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_18_RP3_REG_P2_4               , RULL(0x8000134A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP3_REG_P3_0               , RULL(0x8000034A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP3_REG_P3_0               , RULL(0x8000034A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP3_REG_P3_1               , RULL(0x8000074A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP3_REG_P3_1               , RULL(0x8000074A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP3_REG_P3_2               , RULL(0x80000B4A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP3_REG_P3_2               , RULL(0x80000B4A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP3_REG_P3_3               , RULL(0x80000F4A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP3_REG_P3_3               , RULL(0x80000F4A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_18_RP3_REG_P3_4               , RULL(0x8000134A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_18_RP3_REG_P3_4               , RULL(0x8000134A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_0                  , RULL(0x800000390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_0                , RULL(0x800000390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_0                , RULL(0x800000390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_1                  , RULL(0x800004390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_1                , RULL(0x800004390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_1                , RULL(0x800004390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_2                  , RULL(0x800008390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_2                , RULL(0x800008390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_2                , RULL(0x800008390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_3                  , RULL(0x80000C390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_3                , RULL(0x80000C390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_3                , RULL(0x80000C390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_4                  , RULL(0x800010390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_4                , RULL(0x800010390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_4                , RULL(0x800010390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP0_REG_P1_0                , RULL(0x800000390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP0_REG_P1_0                , RULL(0x800000390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP0_REG_P1_1                , RULL(0x800004390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP0_REG_P1_1                , RULL(0x800004390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP0_REG_P1_2                , RULL(0x800008390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP0_REG_P1_2                , RULL(0x800008390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP0_REG_P1_3                , RULL(0x80000C390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP0_REG_P1_3                , RULL(0x80000C390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP0_REG_P1_4                , RULL(0x800010390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP0_REG_P1_4                , RULL(0x800010390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP0_REG_P2_0                , RULL(0x800000390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP0_REG_P2_0                , RULL(0x800000390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP0_REG_P2_1                , RULL(0x800004390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP0_REG_P2_1                , RULL(0x800004390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP0_REG_P2_2                , RULL(0x800008390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP0_REG_P2_2                , RULL(0x800008390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP0_REG_P2_3                , RULL(0x80000C390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP0_REG_P2_3                , RULL(0x80000C390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP0_REG_P2_4                , RULL(0x800010390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP0_REG_P2_4                , RULL(0x800010390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP0_REG_P3_0                , RULL(0x8000003907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP0_REG_P3_0                , RULL(0x8000003908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP0_REG_P3_1                , RULL(0x8000043907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP0_REG_P3_1                , RULL(0x8000043908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP0_REG_P3_2                , RULL(0x8000083907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP0_REG_P3_2                , RULL(0x8000083908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP0_REG_P3_3                , RULL(0x80000C3907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP0_REG_P3_3                , RULL(0x80000C3908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP0_REG_P3_4                , RULL(0x8000103907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP0_REG_P3_4                , RULL(0x8000103908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_0                  , RULL(0x800001390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_0                , RULL(0x800001390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_0                , RULL(0x800001390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_1                  , RULL(0x800005390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_1                , RULL(0x800005390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_1                , RULL(0x800005390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_2                  , RULL(0x800009390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_2                , RULL(0x800009390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_2                , RULL(0x800009390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_3                  , RULL(0x80000D390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_3                , RULL(0x80000D390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_3                , RULL(0x80000D390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_4                  , RULL(0x800011390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_4                , RULL(0x800011390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_4                , RULL(0x800011390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP1_REG_P1_0                , RULL(0x800001390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP1_REG_P1_0                , RULL(0x800001390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP1_REG_P1_1                , RULL(0x800005390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP1_REG_P1_1                , RULL(0x800005390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP1_REG_P1_2                , RULL(0x800009390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP1_REG_P1_2                , RULL(0x800009390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP1_REG_P1_3                , RULL(0x80000D390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP1_REG_P1_3                , RULL(0x80000D390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP1_REG_P1_4                , RULL(0x800011390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP1_REG_P1_4                , RULL(0x800011390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP1_REG_P2_0                , RULL(0x800001390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP1_REG_P2_0                , RULL(0x800001390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP1_REG_P2_1                , RULL(0x800005390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP1_REG_P2_1                , RULL(0x800005390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP1_REG_P2_2                , RULL(0x800009390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP1_REG_P2_2                , RULL(0x800009390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP1_REG_P2_3                , RULL(0x80000D390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP1_REG_P2_3                , RULL(0x80000D390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP1_REG_P2_4                , RULL(0x800011390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP1_REG_P2_4                , RULL(0x800011390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP1_REG_P3_0                , RULL(0x8000013907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP1_REG_P3_0                , RULL(0x8000013908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP1_REG_P3_1                , RULL(0x8000053907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP1_REG_P3_1                , RULL(0x8000053908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP1_REG_P3_2                , RULL(0x8000093907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP1_REG_P3_2                , RULL(0x8000093908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP1_REG_P3_3                , RULL(0x80000D3907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP1_REG_P3_3                , RULL(0x80000D3908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP1_REG_P3_4                , RULL(0x8000113907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP1_REG_P3_4                , RULL(0x8000113908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_0                  , RULL(0x800002390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_0                , RULL(0x800002390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_0                , RULL(0x800002390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_1                  , RULL(0x800006390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_1                , RULL(0x800006390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_1                , RULL(0x800006390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_2                  , RULL(0x80000A390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_2                , RULL(0x80000A390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_2                , RULL(0x80000A390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_3                  , RULL(0x80000E390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_3                , RULL(0x80000E390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_3                , RULL(0x80000E390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_4                  , RULL(0x800012390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_4                , RULL(0x800012390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_4                , RULL(0x800012390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP2_REG_P1_0                , RULL(0x800002390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP2_REG_P1_0                , RULL(0x800002390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP2_REG_P1_1                , RULL(0x800006390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP2_REG_P1_1                , RULL(0x800006390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP2_REG_P1_2                , RULL(0x80000A390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP2_REG_P1_2                , RULL(0x80000A390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP2_REG_P1_3                , RULL(0x80000E390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP2_REG_P1_3                , RULL(0x80000E390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP2_REG_P1_4                , RULL(0x800012390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP2_REG_P1_4                , RULL(0x800012390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP2_REG_P2_0                , RULL(0x800002390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP2_REG_P2_0                , RULL(0x800002390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP2_REG_P2_1                , RULL(0x800006390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP2_REG_P2_1                , RULL(0x800006390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP2_REG_P2_2                , RULL(0x80000A390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP2_REG_P2_2                , RULL(0x80000A390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP2_REG_P2_3                , RULL(0x80000E390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP2_REG_P2_3                , RULL(0x80000E390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP2_REG_P2_4                , RULL(0x800012390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP2_REG_P2_4                , RULL(0x800012390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP2_REG_P3_0                , RULL(0x8000023907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP2_REG_P3_0                , RULL(0x8000023908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP2_REG_P3_1                , RULL(0x8000063907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP2_REG_P3_1                , RULL(0x8000063908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP2_REG_P3_2                , RULL(0x80000A3907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP2_REG_P3_2                , RULL(0x80000A3908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP2_REG_P3_3                , RULL(0x80000E3907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP2_REG_P3_3                , RULL(0x80000E3908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP2_REG_P3_4                , RULL(0x8000123907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP2_REG_P3_4                , RULL(0x8000123908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_0                  , RULL(0x800003390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_0                , RULL(0x800003390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_0                , RULL(0x800003390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_1                  , RULL(0x800007390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_1                , RULL(0x800007390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_1                , RULL(0x800007390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_2                  , RULL(0x80000B390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_2                , RULL(0x80000B390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_2                , RULL(0x80000B390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_3                  , RULL(0x80000F390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_3                , RULL(0x80000F390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_3                , RULL(0x80000F390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_4                  , RULL(0x800013390701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_4                , RULL(0x800013390701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_4                , RULL(0x800013390801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP3_REG_P1_0                , RULL(0x800003390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP3_REG_P1_0                , RULL(0x800003390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP3_REG_P1_1                , RULL(0x800007390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP3_REG_P1_1                , RULL(0x800007390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP3_REG_P1_2                , RULL(0x80000B390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP3_REG_P1_2                , RULL(0x80000B390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP3_REG_P1_3                , RULL(0x80000F390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP3_REG_P1_3                , RULL(0x80000F390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_1_RP3_REG_P1_4                , RULL(0x800013390701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_1_RP3_REG_P1_4                , RULL(0x800013390801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP3_REG_P2_0                , RULL(0x800003390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP3_REG_P2_0                , RULL(0x800003390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP3_REG_P2_1                , RULL(0x800007390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP3_REG_P2_1                , RULL(0x800007390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP3_REG_P2_2                , RULL(0x80000B390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP3_REG_P2_2                , RULL(0x80000B390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP3_REG_P2_3                , RULL(0x80000F390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP3_REG_P2_3                , RULL(0x80000F390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_1_RP3_REG_P2_4                , RULL(0x800013390701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_1_RP3_REG_P2_4                , RULL(0x800013390801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP3_REG_P3_0                , RULL(0x8000033907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP3_REG_P3_0                , RULL(0x8000033908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP3_REG_P3_1                , RULL(0x8000073907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP3_REG_P3_1                , RULL(0x8000073908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP3_REG_P3_2                , RULL(0x80000B3907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP3_REG_P3_2                , RULL(0x80000B3908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP3_REG_P3_3                , RULL(0x80000F3907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP3_REG_P3_3                , RULL(0x80000F3908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_1_RP3_REG_P3_4                , RULL(0x8000133907011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_1_RP3_REG_P3_4                , RULL(0x8000133908011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_0                 , RULL(0x8000004C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_0               , RULL(0x8000004C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_0               , RULL(0x8000004C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_1                 , RULL(0x8000044C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_1               , RULL(0x8000044C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_1               , RULL(0x8000044C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_2                 , RULL(0x8000084C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_2               , RULL(0x8000084C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_2               , RULL(0x8000084C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_3                 , RULL(0x80000C4C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_3               , RULL(0x80000C4C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_3               , RULL(0x80000C4C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_4                 , RULL(0x8000104C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_4               , RULL(0x8000104C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_4               , RULL(0x8000104C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP0_REG_P1_0               , RULL(0x8000004C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP0_REG_P1_0               , RULL(0x8000004C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP0_REG_P1_1               , RULL(0x8000044C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP0_REG_P1_1               , RULL(0x8000044C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP0_REG_P1_2               , RULL(0x8000084C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP0_REG_P1_2               , RULL(0x8000084C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP0_REG_P1_3               , RULL(0x80000C4C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP0_REG_P1_3               , RULL(0x80000C4C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP0_REG_P1_4               , RULL(0x8000104C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP0_REG_P1_4               , RULL(0x8000104C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP0_REG_P2_0               , RULL(0x8000004C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP0_REG_P2_0               , RULL(0x8000004C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP0_REG_P2_1               , RULL(0x8000044C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP0_REG_P2_1               , RULL(0x8000044C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP0_REG_P2_2               , RULL(0x8000084C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP0_REG_P2_2               , RULL(0x8000084C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP0_REG_P2_3               , RULL(0x80000C4C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP0_REG_P2_3               , RULL(0x80000C4C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP0_REG_P2_4               , RULL(0x8000104C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP0_REG_P2_4               , RULL(0x8000104C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP0_REG_P3_0               , RULL(0x8000004C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP0_REG_P3_0               , RULL(0x8000004C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP0_REG_P3_1               , RULL(0x8000044C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP0_REG_P3_1               , RULL(0x8000044C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP0_REG_P3_2               , RULL(0x8000084C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP0_REG_P3_2               , RULL(0x8000084C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP0_REG_P3_3               , RULL(0x80000C4C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP0_REG_P3_3               , RULL(0x80000C4C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP0_REG_P3_4               , RULL(0x8000104C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP0_REG_P3_4               , RULL(0x8000104C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_0                 , RULL(0x8000014C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_0               , RULL(0x8000014C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_0               , RULL(0x8000014C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_1                 , RULL(0x8000054C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_1               , RULL(0x8000054C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_1               , RULL(0x8000054C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_2                 , RULL(0x8000094C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_2               , RULL(0x8000094C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_2               , RULL(0x8000094C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_3                 , RULL(0x80000D4C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_3               , RULL(0x80000D4C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_3               , RULL(0x80000D4C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_4                 , RULL(0x8000114C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_4               , RULL(0x8000114C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_4               , RULL(0x8000114C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP1_REG_P1_0               , RULL(0x8000014C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP1_REG_P1_0               , RULL(0x8000014C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP1_REG_P1_1               , RULL(0x8000054C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP1_REG_P1_1               , RULL(0x8000054C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP1_REG_P1_2               , RULL(0x8000094C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP1_REG_P1_2               , RULL(0x8000094C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP1_REG_P1_3               , RULL(0x80000D4C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP1_REG_P1_3               , RULL(0x80000D4C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP1_REG_P1_4               , RULL(0x8000114C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP1_REG_P1_4               , RULL(0x8000114C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP1_REG_P2_0               , RULL(0x8000014C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP1_REG_P2_0               , RULL(0x8000014C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP1_REG_P2_1               , RULL(0x8000054C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP1_REG_P2_1               , RULL(0x8000054C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP1_REG_P2_2               , RULL(0x8000094C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP1_REG_P2_2               , RULL(0x8000094C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP1_REG_P2_3               , RULL(0x80000D4C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP1_REG_P2_3               , RULL(0x80000D4C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP1_REG_P2_4               , RULL(0x8000114C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP1_REG_P2_4               , RULL(0x8000114C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP1_REG_P3_0               , RULL(0x8000014C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP1_REG_P3_0               , RULL(0x8000014C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP1_REG_P3_1               , RULL(0x8000054C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP1_REG_P3_1               , RULL(0x8000054C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP1_REG_P3_2               , RULL(0x8000094C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP1_REG_P3_2               , RULL(0x8000094C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP1_REG_P3_3               , RULL(0x80000D4C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP1_REG_P3_3               , RULL(0x80000D4C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP1_REG_P3_4               , RULL(0x8000114C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP1_REG_P3_4               , RULL(0x8000114C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_0                 , RULL(0x8000024C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_0               , RULL(0x8000024C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_0               , RULL(0x8000024C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_1                 , RULL(0x8000064C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_1               , RULL(0x8000064C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_1               , RULL(0x8000064C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_2                 , RULL(0x80000A4C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_2               , RULL(0x80000A4C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_2               , RULL(0x80000A4C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_3                 , RULL(0x80000E4C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_3               , RULL(0x80000E4C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_3               , RULL(0x80000E4C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_4                 , RULL(0x8000124C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_4               , RULL(0x8000124C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_4               , RULL(0x8000124C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP2_REG_P1_0               , RULL(0x8000024C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP2_REG_P1_0               , RULL(0x8000024C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP2_REG_P1_1               , RULL(0x8000064C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP2_REG_P1_1               , RULL(0x8000064C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP2_REG_P1_2               , RULL(0x80000A4C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP2_REG_P1_2               , RULL(0x80000A4C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP2_REG_P1_3               , RULL(0x80000E4C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP2_REG_P1_3               , RULL(0x80000E4C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP2_REG_P1_4               , RULL(0x8000124C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP2_REG_P1_4               , RULL(0x8000124C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP2_REG_P2_0               , RULL(0x8000024C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP2_REG_P2_0               , RULL(0x8000024C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP2_REG_P2_1               , RULL(0x8000064C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP2_REG_P2_1               , RULL(0x8000064C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP2_REG_P2_2               , RULL(0x80000A4C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP2_REG_P2_2               , RULL(0x80000A4C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP2_REG_P2_3               , RULL(0x80000E4C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP2_REG_P2_3               , RULL(0x80000E4C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP2_REG_P2_4               , RULL(0x8000124C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP2_REG_P2_4               , RULL(0x8000124C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP2_REG_P3_0               , RULL(0x8000024C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP2_REG_P3_0               , RULL(0x8000024C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP2_REG_P3_1               , RULL(0x8000064C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP2_REG_P3_1               , RULL(0x8000064C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP2_REG_P3_2               , RULL(0x80000A4C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP2_REG_P3_2               , RULL(0x80000A4C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP2_REG_P3_3               , RULL(0x80000E4C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP2_REG_P3_3               , RULL(0x80000E4C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP2_REG_P3_4               , RULL(0x8000124C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP2_REG_P3_4               , RULL(0x8000124C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_0                 , RULL(0x8000034C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_0               , RULL(0x8000034C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_0               , RULL(0x8000034C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_1                 , RULL(0x8000074C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_1               , RULL(0x8000074C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_1               , RULL(0x8000074C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_2                 , RULL(0x80000B4C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_2               , RULL(0x80000B4C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_2               , RULL(0x80000B4C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_3                 , RULL(0x80000F4C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_3               , RULL(0x80000F4C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_3               , RULL(0x80000F4C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_4                 , RULL(0x8000134C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_4               , RULL(0x8000134C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_4               , RULL(0x8000134C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP3_REG_P1_0               , RULL(0x8000034C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP3_REG_P1_0               , RULL(0x8000034C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP3_REG_P1_1               , RULL(0x8000074C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP3_REG_P1_1               , RULL(0x8000074C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP3_REG_P1_2               , RULL(0x80000B4C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP3_REG_P1_2               , RULL(0x80000B4C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP3_REG_P1_3               , RULL(0x80000F4C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP3_REG_P1_3               , RULL(0x80000F4C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_20_RP3_REG_P1_4               , RULL(0x8000134C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_20_RP3_REG_P1_4               , RULL(0x8000134C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP3_REG_P2_0               , RULL(0x8000034C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP3_REG_P2_0               , RULL(0x8000034C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP3_REG_P2_1               , RULL(0x8000074C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP3_REG_P2_1               , RULL(0x8000074C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP3_REG_P2_2               , RULL(0x80000B4C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP3_REG_P2_2               , RULL(0x80000B4C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP3_REG_P2_3               , RULL(0x80000F4C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP3_REG_P2_3               , RULL(0x80000F4C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_20_RP3_REG_P2_4               , RULL(0x8000134C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_20_RP3_REG_P2_4               , RULL(0x8000134C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP3_REG_P3_0               , RULL(0x8000034C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP3_REG_P3_0               , RULL(0x8000034C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP3_REG_P3_1               , RULL(0x8000074C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP3_REG_P3_1               , RULL(0x8000074C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP3_REG_P3_2               , RULL(0x80000B4C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP3_REG_P3_2               , RULL(0x80000B4C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP3_REG_P3_3               , RULL(0x80000F4C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP3_REG_P3_3               , RULL(0x80000F4C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_20_RP3_REG_P3_4               , RULL(0x8000134C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_20_RP3_REG_P3_4               , RULL(0x8000134C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_0                 , RULL(0x8000004E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_0               , RULL(0x8000004E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_0               , RULL(0x8000004E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_1                 , RULL(0x8000044E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_1               , RULL(0x8000044E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_1               , RULL(0x8000044E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_2                 , RULL(0x8000084E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_2               , RULL(0x8000084E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_2               , RULL(0x8000084E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_3                 , RULL(0x80000C4E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_3               , RULL(0x80000C4E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_3               , RULL(0x80000C4E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_4                 , RULL(0x8000104E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_4               , RULL(0x8000104E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_4               , RULL(0x8000104E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP0_REG_P1_0               , RULL(0x8000004E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP0_REG_P1_0               , RULL(0x8000004E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP0_REG_P1_1               , RULL(0x8000044E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP0_REG_P1_1               , RULL(0x8000044E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP0_REG_P1_2               , RULL(0x8000084E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP0_REG_P1_2               , RULL(0x8000084E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP0_REG_P1_3               , RULL(0x80000C4E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP0_REG_P1_3               , RULL(0x80000C4E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP0_REG_P1_4               , RULL(0x8000104E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP0_REG_P1_4               , RULL(0x8000104E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP0_REG_P2_0               , RULL(0x8000004E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP0_REG_P2_0               , RULL(0x8000004E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP0_REG_P2_1               , RULL(0x8000044E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP0_REG_P2_1               , RULL(0x8000044E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP0_REG_P2_2               , RULL(0x8000084E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP0_REG_P2_2               , RULL(0x8000084E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP0_REG_P2_3               , RULL(0x80000C4E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP0_REG_P2_3               , RULL(0x80000C4E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP0_REG_P2_4               , RULL(0x8000104E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP0_REG_P2_4               , RULL(0x8000104E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP0_REG_P3_0               , RULL(0x8000004E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP0_REG_P3_0               , RULL(0x8000004E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP0_REG_P3_1               , RULL(0x8000044E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP0_REG_P3_1               , RULL(0x8000044E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP0_REG_P3_2               , RULL(0x8000084E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP0_REG_P3_2               , RULL(0x8000084E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP0_REG_P3_3               , RULL(0x80000C4E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP0_REG_P3_3               , RULL(0x80000C4E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP0_REG_P3_4               , RULL(0x8000104E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP0_REG_P3_4               , RULL(0x8000104E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_0                 , RULL(0x8000014E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_0               , RULL(0x8000014E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_0               , RULL(0x8000014E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_1                 , RULL(0x8000054E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_1               , RULL(0x8000054E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_1               , RULL(0x8000054E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_2                 , RULL(0x8000094E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_2               , RULL(0x8000094E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_2               , RULL(0x8000094E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_3                 , RULL(0x80000D4E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_3               , RULL(0x80000D4E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_3               , RULL(0x80000D4E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_4                 , RULL(0x8000114E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_4               , RULL(0x8000114E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_4               , RULL(0x8000114E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP1_REG_P1_0               , RULL(0x8000014E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP1_REG_P1_0               , RULL(0x8000014E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP1_REG_P1_1               , RULL(0x8000054E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP1_REG_P1_1               , RULL(0x8000054E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP1_REG_P1_2               , RULL(0x8000094E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP1_REG_P1_2               , RULL(0x8000094E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP1_REG_P1_3               , RULL(0x80000D4E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP1_REG_P1_3               , RULL(0x80000D4E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP1_REG_P1_4               , RULL(0x8000114E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP1_REG_P1_4               , RULL(0x8000114E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP1_REG_P2_0               , RULL(0x8000014E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP1_REG_P2_0               , RULL(0x8000014E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP1_REG_P2_1               , RULL(0x8000054E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP1_REG_P2_1               , RULL(0x8000054E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP1_REG_P2_2               , RULL(0x8000094E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP1_REG_P2_2               , RULL(0x8000094E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP1_REG_P2_3               , RULL(0x80000D4E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP1_REG_P2_3               , RULL(0x80000D4E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP1_REG_P2_4               , RULL(0x8000114E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP1_REG_P2_4               , RULL(0x8000114E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP1_REG_P3_0               , RULL(0x8000014E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP1_REG_P3_0               , RULL(0x8000014E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP1_REG_P3_1               , RULL(0x8000054E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP1_REG_P3_1               , RULL(0x8000054E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP1_REG_P3_2               , RULL(0x8000094E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP1_REG_P3_2               , RULL(0x8000094E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP1_REG_P3_3               , RULL(0x80000D4E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP1_REG_P3_3               , RULL(0x80000D4E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP1_REG_P3_4               , RULL(0x8000114E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP1_REG_P3_4               , RULL(0x8000114E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_0                 , RULL(0x8000024E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_0               , RULL(0x8000024E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_0               , RULL(0x8000024E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_1                 , RULL(0x8000064E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_1               , RULL(0x8000064E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_1               , RULL(0x8000064E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_2                 , RULL(0x80000A4E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_2               , RULL(0x80000A4E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_2               , RULL(0x80000A4E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_3                 , RULL(0x80000E4E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_3               , RULL(0x80000E4E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_3               , RULL(0x80000E4E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_4                 , RULL(0x8000124E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_4               , RULL(0x8000124E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_4               , RULL(0x8000124E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP2_REG_P1_0               , RULL(0x8000024E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP2_REG_P1_0               , RULL(0x8000024E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP2_REG_P1_1               , RULL(0x8000064E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP2_REG_P1_1               , RULL(0x8000064E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP2_REG_P1_2               , RULL(0x80000A4E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP2_REG_P1_2               , RULL(0x80000A4E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP2_REG_P1_3               , RULL(0x80000E4E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP2_REG_P1_3               , RULL(0x80000E4E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP2_REG_P1_4               , RULL(0x8000124E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP2_REG_P1_4               , RULL(0x8000124E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP2_REG_P2_0               , RULL(0x8000024E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP2_REG_P2_0               , RULL(0x8000024E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP2_REG_P2_1               , RULL(0x8000064E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP2_REG_P2_1               , RULL(0x8000064E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP2_REG_P2_2               , RULL(0x80000A4E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP2_REG_P2_2               , RULL(0x80000A4E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP2_REG_P2_3               , RULL(0x80000E4E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP2_REG_P2_3               , RULL(0x80000E4E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP2_REG_P2_4               , RULL(0x8000124E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP2_REG_P2_4               , RULL(0x8000124E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP2_REG_P3_0               , RULL(0x8000024E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP2_REG_P3_0               , RULL(0x8000024E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP2_REG_P3_1               , RULL(0x8000064E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP2_REG_P3_1               , RULL(0x8000064E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP2_REG_P3_2               , RULL(0x80000A4E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP2_REG_P3_2               , RULL(0x80000A4E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP2_REG_P3_3               , RULL(0x80000E4E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP2_REG_P3_3               , RULL(0x80000E4E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP2_REG_P3_4               , RULL(0x8000124E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP2_REG_P3_4               , RULL(0x8000124E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_0                 , RULL(0x8000034E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_0               , RULL(0x8000034E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_0               , RULL(0x8000034E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_1                 , RULL(0x8000074E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_1               , RULL(0x8000074E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_1               , RULL(0x8000074E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_2                 , RULL(0x80000B4E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_2               , RULL(0x80000B4E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_2               , RULL(0x80000B4E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_3                 , RULL(0x80000F4E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_3               , RULL(0x80000F4E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_3               , RULL(0x80000F4E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_4                 , RULL(0x8000134E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_4               , RULL(0x8000134E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_4               , RULL(0x8000134E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP3_REG_P1_0               , RULL(0x8000034E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP3_REG_P1_0               , RULL(0x8000034E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP3_REG_P1_1               , RULL(0x8000074E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP3_REG_P1_1               , RULL(0x8000074E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP3_REG_P1_2               , RULL(0x80000B4E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP3_REG_P1_2               , RULL(0x80000B4E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP3_REG_P1_3               , RULL(0x80000F4E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP3_REG_P1_3               , RULL(0x80000F4E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_22_RP3_REG_P1_4               , RULL(0x8000134E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_22_RP3_REG_P1_4               , RULL(0x8000134E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP3_REG_P2_0               , RULL(0x8000034E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP3_REG_P2_0               , RULL(0x8000034E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP3_REG_P2_1               , RULL(0x8000074E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP3_REG_P2_1               , RULL(0x8000074E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP3_REG_P2_2               , RULL(0x80000B4E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP3_REG_P2_2               , RULL(0x80000B4E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP3_REG_P2_3               , RULL(0x80000F4E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP3_REG_P2_3               , RULL(0x80000F4E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_22_RP3_REG_P2_4               , RULL(0x8000134E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_22_RP3_REG_P2_4               , RULL(0x8000134E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP3_REG_P3_0               , RULL(0x8000034E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP3_REG_P3_0               , RULL(0x8000034E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP3_REG_P3_1               , RULL(0x8000074E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP3_REG_P3_1               , RULL(0x8000074E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP3_REG_P3_2               , RULL(0x80000B4E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP3_REG_P3_2               , RULL(0x80000B4E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP3_REG_P3_3               , RULL(0x80000F4E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP3_REG_P3_3               , RULL(0x80000F4E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_22_RP3_REG_P3_4               , RULL(0x8000134E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_22_RP3_REG_P3_4               , RULL(0x8000134E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_0                  , RULL(0x8000003A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_0                , RULL(0x8000003A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_0                , RULL(0x8000003A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_1                  , RULL(0x8000043A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_1                , RULL(0x8000043A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_1                , RULL(0x8000043A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_2                  , RULL(0x8000083A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_2                , RULL(0x8000083A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_2                , RULL(0x8000083A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_3                  , RULL(0x80000C3A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_3                , RULL(0x80000C3A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_3                , RULL(0x80000C3A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_4                  , RULL(0x8000103A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_4                , RULL(0x8000103A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_4                , RULL(0x8000103A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP0_REG_P1_0                , RULL(0x8000003A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP0_REG_P1_0                , RULL(0x8000003A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP0_REG_P1_1                , RULL(0x8000043A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP0_REG_P1_1                , RULL(0x8000043A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP0_REG_P1_2                , RULL(0x8000083A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP0_REG_P1_2                , RULL(0x8000083A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP0_REG_P1_3                , RULL(0x80000C3A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP0_REG_P1_3                , RULL(0x80000C3A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP0_REG_P1_4                , RULL(0x8000103A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP0_REG_P1_4                , RULL(0x8000103A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP0_REG_P2_0                , RULL(0x8000003A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP0_REG_P2_0                , RULL(0x8000003A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP0_REG_P2_1                , RULL(0x8000043A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP0_REG_P2_1                , RULL(0x8000043A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP0_REG_P2_2                , RULL(0x8000083A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP0_REG_P2_2                , RULL(0x8000083A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP0_REG_P2_3                , RULL(0x80000C3A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP0_REG_P2_3                , RULL(0x80000C3A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP0_REG_P2_4                , RULL(0x8000103A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP0_REG_P2_4                , RULL(0x8000103A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP0_REG_P3_0                , RULL(0x8000003A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP0_REG_P3_0                , RULL(0x8000003A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP0_REG_P3_1                , RULL(0x8000043A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP0_REG_P3_1                , RULL(0x8000043A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP0_REG_P3_2                , RULL(0x8000083A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP0_REG_P3_2                , RULL(0x8000083A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP0_REG_P3_3                , RULL(0x80000C3A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP0_REG_P3_3                , RULL(0x80000C3A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP0_REG_P3_4                , RULL(0x8000103A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP0_REG_P3_4                , RULL(0x8000103A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_0                  , RULL(0x8000013A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_0                , RULL(0x8000013A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_0                , RULL(0x8000013A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_1                  , RULL(0x8000053A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_1                , RULL(0x8000053A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_1                , RULL(0x8000053A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_2                  , RULL(0x8000093A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_2                , RULL(0x8000093A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_2                , RULL(0x8000093A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_3                  , RULL(0x80000D3A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_3                , RULL(0x80000D3A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_3                , RULL(0x80000D3A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_4                  , RULL(0x8000113A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_4                , RULL(0x8000113A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_4                , RULL(0x8000113A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP1_REG_P1_0                , RULL(0x8000013A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP1_REG_P1_0                , RULL(0x8000013A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP1_REG_P1_1                , RULL(0x8000053A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP1_REG_P1_1                , RULL(0x8000053A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP1_REG_P1_2                , RULL(0x8000093A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP1_REG_P1_2                , RULL(0x8000093A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP1_REG_P1_3                , RULL(0x80000D3A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP1_REG_P1_3                , RULL(0x80000D3A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP1_REG_P1_4                , RULL(0x8000113A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP1_REG_P1_4                , RULL(0x8000113A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP1_REG_P2_0                , RULL(0x8000013A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP1_REG_P2_0                , RULL(0x8000013A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP1_REG_P2_1                , RULL(0x8000053A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP1_REG_P2_1                , RULL(0x8000053A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP1_REG_P2_2                , RULL(0x8000093A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP1_REG_P2_2                , RULL(0x8000093A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP1_REG_P2_3                , RULL(0x80000D3A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP1_REG_P2_3                , RULL(0x80000D3A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP1_REG_P2_4                , RULL(0x8000113A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP1_REG_P2_4                , RULL(0x8000113A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP1_REG_P3_0                , RULL(0x8000013A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP1_REG_P3_0                , RULL(0x8000013A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP1_REG_P3_1                , RULL(0x8000053A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP1_REG_P3_1                , RULL(0x8000053A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP1_REG_P3_2                , RULL(0x8000093A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP1_REG_P3_2                , RULL(0x8000093A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP1_REG_P3_3                , RULL(0x80000D3A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP1_REG_P3_3                , RULL(0x80000D3A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP1_REG_P3_4                , RULL(0x8000113A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP1_REG_P3_4                , RULL(0x8000113A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_0                  , RULL(0x8000023A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_0                , RULL(0x8000023A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_0                , RULL(0x8000023A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_1                  , RULL(0x8000063A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_1                , RULL(0x8000063A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_1                , RULL(0x8000063A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_2                  , RULL(0x80000A3A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_2                , RULL(0x80000A3A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_2                , RULL(0x80000A3A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_3                  , RULL(0x80000E3A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_3                , RULL(0x80000E3A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_3                , RULL(0x80000E3A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_4                  , RULL(0x8000123A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_4                , RULL(0x8000123A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_4                , RULL(0x8000123A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP2_REG_P1_0                , RULL(0x8000023A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP2_REG_P1_0                , RULL(0x8000023A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP2_REG_P1_1                , RULL(0x8000063A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP2_REG_P1_1                , RULL(0x8000063A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP2_REG_P1_2                , RULL(0x80000A3A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP2_REG_P1_2                , RULL(0x80000A3A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP2_REG_P1_3                , RULL(0x80000E3A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP2_REG_P1_3                , RULL(0x80000E3A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP2_REG_P1_4                , RULL(0x8000123A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP2_REG_P1_4                , RULL(0x8000123A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP2_REG_P2_0                , RULL(0x8000023A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP2_REG_P2_0                , RULL(0x8000023A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP2_REG_P2_1                , RULL(0x8000063A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP2_REG_P2_1                , RULL(0x8000063A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP2_REG_P2_2                , RULL(0x80000A3A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP2_REG_P2_2                , RULL(0x80000A3A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP2_REG_P2_3                , RULL(0x80000E3A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP2_REG_P2_3                , RULL(0x80000E3A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP2_REG_P2_4                , RULL(0x8000123A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP2_REG_P2_4                , RULL(0x8000123A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP2_REG_P3_0                , RULL(0x8000023A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP2_REG_P3_0                , RULL(0x8000023A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP2_REG_P3_1                , RULL(0x8000063A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP2_REG_P3_1                , RULL(0x8000063A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP2_REG_P3_2                , RULL(0x80000A3A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP2_REG_P3_2                , RULL(0x80000A3A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP2_REG_P3_3                , RULL(0x80000E3A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP2_REG_P3_3                , RULL(0x80000E3A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP2_REG_P3_4                , RULL(0x8000123A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP2_REG_P3_4                , RULL(0x8000123A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_0                  , RULL(0x8000033A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_0                , RULL(0x8000033A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_0                , RULL(0x8000033A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_1                  , RULL(0x8000073A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_1                , RULL(0x8000073A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_1                , RULL(0x8000073A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_2                  , RULL(0x80000B3A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_2                , RULL(0x80000B3A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_2                , RULL(0x80000B3A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_3                  , RULL(0x80000F3A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_3                , RULL(0x80000F3A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_3                , RULL(0x80000F3A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_4                  , RULL(0x8000133A0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_4                , RULL(0x8000133A0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_4                , RULL(0x8000133A0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP3_REG_P1_0                , RULL(0x8000033A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP3_REG_P1_0                , RULL(0x8000033A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP3_REG_P1_1                , RULL(0x8000073A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP3_REG_P1_1                , RULL(0x8000073A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP3_REG_P1_2                , RULL(0x80000B3A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP3_REG_P1_2                , RULL(0x80000B3A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP3_REG_P1_3                , RULL(0x80000F3A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP3_REG_P1_3                , RULL(0x80000F3A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_2_RP3_REG_P1_4                , RULL(0x8000133A0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_2_RP3_REG_P1_4                , RULL(0x8000133A0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP3_REG_P2_0                , RULL(0x8000033A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP3_REG_P2_0                , RULL(0x8000033A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP3_REG_P2_1                , RULL(0x8000073A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP3_REG_P2_1                , RULL(0x8000073A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP3_REG_P2_2                , RULL(0x80000B3A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP3_REG_P2_2                , RULL(0x80000B3A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP3_REG_P2_3                , RULL(0x80000F3A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP3_REG_P2_3                , RULL(0x80000F3A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_2_RP3_REG_P2_4                , RULL(0x8000133A0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_2_RP3_REG_P2_4                , RULL(0x8000133A0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP3_REG_P3_0                , RULL(0x8000033A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP3_REG_P3_0                , RULL(0x8000033A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP3_REG_P3_1                , RULL(0x8000073A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP3_REG_P3_1                , RULL(0x8000073A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP3_REG_P3_2                , RULL(0x80000B3A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP3_REG_P3_2                , RULL(0x80000B3A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP3_REG_P3_3                , RULL(0x80000F3A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP3_REG_P3_3                , RULL(0x80000F3A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_2_RP3_REG_P3_4                , RULL(0x8000133A07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_2_RP3_REG_P3_4                , RULL(0x8000133A08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_0                  , RULL(0x8000003B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_0                , RULL(0x8000003B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_0                , RULL(0x8000003B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_1                  , RULL(0x8000043B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_1                , RULL(0x8000043B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_1                , RULL(0x8000043B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_2                  , RULL(0x8000083B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_2                , RULL(0x8000083B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_2                , RULL(0x8000083B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_3                  , RULL(0x80000C3B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_3                , RULL(0x80000C3B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_3                , RULL(0x80000C3B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_4                  , RULL(0x8000103B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_4                , RULL(0x8000103B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_4                , RULL(0x8000103B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP0_REG_P1_0                , RULL(0x8000003B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP0_REG_P1_0                , RULL(0x8000003B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP0_REG_P1_1                , RULL(0x8000043B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP0_REG_P1_1                , RULL(0x8000043B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP0_REG_P1_2                , RULL(0x8000083B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP0_REG_P1_2                , RULL(0x8000083B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP0_REG_P1_3                , RULL(0x80000C3B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP0_REG_P1_3                , RULL(0x80000C3B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP0_REG_P1_4                , RULL(0x8000103B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP0_REG_P1_4                , RULL(0x8000103B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP0_REG_P2_0                , RULL(0x8000003B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP0_REG_P2_0                , RULL(0x8000003B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP0_REG_P2_1                , RULL(0x8000043B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP0_REG_P2_1                , RULL(0x8000043B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP0_REG_P2_2                , RULL(0x8000083B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP0_REG_P2_2                , RULL(0x8000083B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP0_REG_P2_3                , RULL(0x80000C3B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP0_REG_P2_3                , RULL(0x80000C3B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP0_REG_P2_4                , RULL(0x8000103B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP0_REG_P2_4                , RULL(0x8000103B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP0_REG_P3_0                , RULL(0x8000003B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP0_REG_P3_0                , RULL(0x8000003B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP0_REG_P3_1                , RULL(0x8000043B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP0_REG_P3_1                , RULL(0x8000043B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP0_REG_P3_2                , RULL(0x8000083B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP0_REG_P3_2                , RULL(0x8000083B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP0_REG_P3_3                , RULL(0x80000C3B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP0_REG_P3_3                , RULL(0x80000C3B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP0_REG_P3_4                , RULL(0x8000103B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP0_REG_P3_4                , RULL(0x8000103B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_0                  , RULL(0x8000013B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_0                , RULL(0x8000013B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_0                , RULL(0x8000013B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_1                  , RULL(0x8000053B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_1                , RULL(0x8000053B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_1                , RULL(0x8000053B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_2                  , RULL(0x8000093B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_2                , RULL(0x8000093B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_2                , RULL(0x8000093B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_3                  , RULL(0x80000D3B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_3                , RULL(0x80000D3B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_3                , RULL(0x80000D3B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_4                  , RULL(0x8000113B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_4                , RULL(0x8000113B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_4                , RULL(0x8000113B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP1_REG_P1_0                , RULL(0x8000013B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP1_REG_P1_0                , RULL(0x8000013B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP1_REG_P1_1                , RULL(0x8000053B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP1_REG_P1_1                , RULL(0x8000053B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP1_REG_P1_2                , RULL(0x8000093B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP1_REG_P1_2                , RULL(0x8000093B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP1_REG_P1_3                , RULL(0x80000D3B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP1_REG_P1_3                , RULL(0x80000D3B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP1_REG_P1_4                , RULL(0x8000113B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP1_REG_P1_4                , RULL(0x8000113B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP1_REG_P2_0                , RULL(0x8000013B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP1_REG_P2_0                , RULL(0x8000013B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP1_REG_P2_1                , RULL(0x8000053B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP1_REG_P2_1                , RULL(0x8000053B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP1_REG_P2_2                , RULL(0x8000093B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP1_REG_P2_2                , RULL(0x8000093B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP1_REG_P2_3                , RULL(0x80000D3B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP1_REG_P2_3                , RULL(0x80000D3B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP1_REG_P2_4                , RULL(0x8000113B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP1_REG_P2_4                , RULL(0x8000113B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP1_REG_P3_0                , RULL(0x8000013B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP1_REG_P3_0                , RULL(0x8000013B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP1_REG_P3_1                , RULL(0x8000053B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP1_REG_P3_1                , RULL(0x8000053B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP1_REG_P3_2                , RULL(0x8000093B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP1_REG_P3_2                , RULL(0x8000093B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP1_REG_P3_3                , RULL(0x80000D3B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP1_REG_P3_3                , RULL(0x80000D3B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP1_REG_P3_4                , RULL(0x8000113B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP1_REG_P3_4                , RULL(0x8000113B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_0                  , RULL(0x8000023B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_0                , RULL(0x8000023B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_0                , RULL(0x8000023B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_1                  , RULL(0x8000063B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_1                , RULL(0x8000063B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_1                , RULL(0x8000063B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_2                  , RULL(0x80000A3B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_2                , RULL(0x80000A3B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_2                , RULL(0x80000A3B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_3                  , RULL(0x80000E3B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_3                , RULL(0x80000E3B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_3                , RULL(0x80000E3B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_4                  , RULL(0x8000123B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_4                , RULL(0x8000123B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_4                , RULL(0x8000123B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP2_REG_P1_0                , RULL(0x8000023B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP2_REG_P1_0                , RULL(0x8000023B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP2_REG_P1_1                , RULL(0x8000063B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP2_REG_P1_1                , RULL(0x8000063B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP2_REG_P1_2                , RULL(0x80000A3B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP2_REG_P1_2                , RULL(0x80000A3B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP2_REG_P1_3                , RULL(0x80000E3B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP2_REG_P1_3                , RULL(0x80000E3B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP2_REG_P1_4                , RULL(0x8000123B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP2_REG_P1_4                , RULL(0x8000123B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP2_REG_P2_0                , RULL(0x8000023B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP2_REG_P2_0                , RULL(0x8000023B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP2_REG_P2_1                , RULL(0x8000063B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP2_REG_P2_1                , RULL(0x8000063B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP2_REG_P2_2                , RULL(0x80000A3B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP2_REG_P2_2                , RULL(0x80000A3B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP2_REG_P2_3                , RULL(0x80000E3B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP2_REG_P2_3                , RULL(0x80000E3B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP2_REG_P2_4                , RULL(0x8000123B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP2_REG_P2_4                , RULL(0x8000123B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP2_REG_P3_0                , RULL(0x8000023B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP2_REG_P3_0                , RULL(0x8000023B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP2_REG_P3_1                , RULL(0x8000063B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP2_REG_P3_1                , RULL(0x8000063B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP2_REG_P3_2                , RULL(0x80000A3B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP2_REG_P3_2                , RULL(0x80000A3B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP2_REG_P3_3                , RULL(0x80000E3B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP2_REG_P3_3                , RULL(0x80000E3B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP2_REG_P3_4                , RULL(0x8000123B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP2_REG_P3_4                , RULL(0x8000123B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_0                  , RULL(0x8000033B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_0                , RULL(0x8000033B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_0                , RULL(0x8000033B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_1                  , RULL(0x8000073B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_1                , RULL(0x8000073B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_1                , RULL(0x8000073B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_2                  , RULL(0x80000B3B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_2                , RULL(0x80000B3B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_2                , RULL(0x80000B3B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_3                  , RULL(0x80000F3B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_3                , RULL(0x80000F3B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_3                , RULL(0x80000F3B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_4                  , RULL(0x8000133B0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_4                , RULL(0x8000133B0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_4                , RULL(0x8000133B0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP3_REG_P1_0                , RULL(0x8000033B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP3_REG_P1_0                , RULL(0x8000033B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP3_REG_P1_1                , RULL(0x8000073B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP3_REG_P1_1                , RULL(0x8000073B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP3_REG_P1_2                , RULL(0x80000B3B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP3_REG_P1_2                , RULL(0x80000B3B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP3_REG_P1_3                , RULL(0x80000F3B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP3_REG_P1_3                , RULL(0x80000F3B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_3_RP3_REG_P1_4                , RULL(0x8000133B0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_3_RP3_REG_P1_4                , RULL(0x8000133B0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP3_REG_P2_0                , RULL(0x8000033B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP3_REG_P2_0                , RULL(0x8000033B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP3_REG_P2_1                , RULL(0x8000073B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP3_REG_P2_1                , RULL(0x8000073B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP3_REG_P2_2                , RULL(0x80000B3B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP3_REG_P2_2                , RULL(0x80000B3B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP3_REG_P2_3                , RULL(0x80000F3B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP3_REG_P2_3                , RULL(0x80000F3B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_3_RP3_REG_P2_4                , RULL(0x8000133B0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_3_RP3_REG_P2_4                , RULL(0x8000133B0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP3_REG_P3_0                , RULL(0x8000033B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP3_REG_P3_0                , RULL(0x8000033B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP3_REG_P3_1                , RULL(0x8000073B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP3_REG_P3_1                , RULL(0x8000073B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP3_REG_P3_2                , RULL(0x80000B3B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP3_REG_P3_2                , RULL(0x80000B3B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP3_REG_P3_3                , RULL(0x80000F3B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP3_REG_P3_3                , RULL(0x80000F3B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_3_RP3_REG_P3_4                , RULL(0x8000133B07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_3_RP3_REG_P3_4                , RULL(0x8000133B08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_0                  , RULL(0x8000003C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_0                , RULL(0x8000003C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_0                , RULL(0x8000003C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_1                  , RULL(0x8000043C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_1                , RULL(0x8000043C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_1                , RULL(0x8000043C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_2                  , RULL(0x8000083C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_2                , RULL(0x8000083C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_2                , RULL(0x8000083C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_3                  , RULL(0x80000C3C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_3                , RULL(0x80000C3C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_3                , RULL(0x80000C3C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_4                  , RULL(0x8000103C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_4                , RULL(0x8000103C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_4                , RULL(0x8000103C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP0_REG_P1_0                , RULL(0x8000003C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP0_REG_P1_0                , RULL(0x8000003C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP0_REG_P1_1                , RULL(0x8000043C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP0_REG_P1_1                , RULL(0x8000043C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP0_REG_P1_2                , RULL(0x8000083C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP0_REG_P1_2                , RULL(0x8000083C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP0_REG_P1_3                , RULL(0x80000C3C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP0_REG_P1_3                , RULL(0x80000C3C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP0_REG_P1_4                , RULL(0x8000103C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP0_REG_P1_4                , RULL(0x8000103C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP0_REG_P2_0                , RULL(0x8000003C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP0_REG_P2_0                , RULL(0x8000003C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP0_REG_P2_1                , RULL(0x8000043C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP0_REG_P2_1                , RULL(0x8000043C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP0_REG_P2_2                , RULL(0x8000083C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP0_REG_P2_2                , RULL(0x8000083C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP0_REG_P2_3                , RULL(0x80000C3C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP0_REG_P2_3                , RULL(0x80000C3C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP0_REG_P2_4                , RULL(0x8000103C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP0_REG_P2_4                , RULL(0x8000103C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP0_REG_P3_0                , RULL(0x8000003C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP0_REG_P3_0                , RULL(0x8000003C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP0_REG_P3_1                , RULL(0x8000043C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP0_REG_P3_1                , RULL(0x8000043C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP0_REG_P3_2                , RULL(0x8000083C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP0_REG_P3_2                , RULL(0x8000083C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP0_REG_P3_3                , RULL(0x80000C3C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP0_REG_P3_3                , RULL(0x80000C3C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP0_REG_P3_4                , RULL(0x8000103C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP0_REG_P3_4                , RULL(0x8000103C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_0                  , RULL(0x8000013C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_0                , RULL(0x8000013C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_0                , RULL(0x8000013C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_1                  , RULL(0x8000053C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_1                , RULL(0x8000053C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_1                , RULL(0x8000053C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_2                  , RULL(0x8000093C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_2                , RULL(0x8000093C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_2                , RULL(0x8000093C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_3                  , RULL(0x80000D3C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_3                , RULL(0x80000D3C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_3                , RULL(0x80000D3C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_4                  , RULL(0x8000113C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_4                , RULL(0x8000113C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_4                , RULL(0x8000113C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP1_REG_P1_0                , RULL(0x8000013C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP1_REG_P1_0                , RULL(0x8000013C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP1_REG_P1_1                , RULL(0x8000053C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP1_REG_P1_1                , RULL(0x8000053C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP1_REG_P1_2                , RULL(0x8000093C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP1_REG_P1_2                , RULL(0x8000093C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP1_REG_P1_3                , RULL(0x80000D3C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP1_REG_P1_3                , RULL(0x80000D3C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP1_REG_P1_4                , RULL(0x8000113C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP1_REG_P1_4                , RULL(0x8000113C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP1_REG_P2_0                , RULL(0x8000013C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP1_REG_P2_0                , RULL(0x8000013C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP1_REG_P2_1                , RULL(0x8000053C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP1_REG_P2_1                , RULL(0x8000053C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP1_REG_P2_2                , RULL(0x8000093C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP1_REG_P2_2                , RULL(0x8000093C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP1_REG_P2_3                , RULL(0x80000D3C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP1_REG_P2_3                , RULL(0x80000D3C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP1_REG_P2_4                , RULL(0x8000113C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP1_REG_P2_4                , RULL(0x8000113C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP1_REG_P3_0                , RULL(0x8000013C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP1_REG_P3_0                , RULL(0x8000013C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP1_REG_P3_1                , RULL(0x8000053C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP1_REG_P3_1                , RULL(0x8000053C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP1_REG_P3_2                , RULL(0x8000093C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP1_REG_P3_2                , RULL(0x8000093C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP1_REG_P3_3                , RULL(0x80000D3C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP1_REG_P3_3                , RULL(0x80000D3C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP1_REG_P3_4                , RULL(0x8000113C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP1_REG_P3_4                , RULL(0x8000113C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_0                  , RULL(0x8000023C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_0                , RULL(0x8000023C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_0                , RULL(0x8000023C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_1                  , RULL(0x8000063C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_1                , RULL(0x8000063C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_1                , RULL(0x8000063C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_2                  , RULL(0x80000A3C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_2                , RULL(0x80000A3C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_2                , RULL(0x80000A3C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_3                  , RULL(0x80000E3C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_3                , RULL(0x80000E3C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_3                , RULL(0x80000E3C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_4                  , RULL(0x8000123C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_4                , RULL(0x8000123C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_4                , RULL(0x8000123C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP2_REG_P1_0                , RULL(0x8000023C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP2_REG_P1_0                , RULL(0x8000023C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP2_REG_P1_1                , RULL(0x8000063C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP2_REG_P1_1                , RULL(0x8000063C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP2_REG_P1_2                , RULL(0x80000A3C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP2_REG_P1_2                , RULL(0x80000A3C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP2_REG_P1_3                , RULL(0x80000E3C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP2_REG_P1_3                , RULL(0x80000E3C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP2_REG_P1_4                , RULL(0x8000123C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP2_REG_P1_4                , RULL(0x8000123C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP2_REG_P2_0                , RULL(0x8000023C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP2_REG_P2_0                , RULL(0x8000023C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP2_REG_P2_1                , RULL(0x8000063C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP2_REG_P2_1                , RULL(0x8000063C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP2_REG_P2_2                , RULL(0x80000A3C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP2_REG_P2_2                , RULL(0x80000A3C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP2_REG_P2_3                , RULL(0x80000E3C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP2_REG_P2_3                , RULL(0x80000E3C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP2_REG_P2_4                , RULL(0x8000123C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP2_REG_P2_4                , RULL(0x8000123C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP2_REG_P3_0                , RULL(0x8000023C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP2_REG_P3_0                , RULL(0x8000023C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP2_REG_P3_1                , RULL(0x8000063C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP2_REG_P3_1                , RULL(0x8000063C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP2_REG_P3_2                , RULL(0x80000A3C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP2_REG_P3_2                , RULL(0x80000A3C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP2_REG_P3_3                , RULL(0x80000E3C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP2_REG_P3_3                , RULL(0x80000E3C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP2_REG_P3_4                , RULL(0x8000123C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP2_REG_P3_4                , RULL(0x8000123C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_0                  , RULL(0x8000033C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_0                , RULL(0x8000033C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_0                , RULL(0x8000033C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_1                  , RULL(0x8000073C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_1                , RULL(0x8000073C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_1                , RULL(0x8000073C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_2                  , RULL(0x80000B3C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_2                , RULL(0x80000B3C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_2                , RULL(0x80000B3C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_3                  , RULL(0x80000F3C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_3                , RULL(0x80000F3C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_3                , RULL(0x80000F3C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_4                  , RULL(0x8000133C0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_4                , RULL(0x8000133C0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_4                , RULL(0x8000133C0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP3_REG_P1_0                , RULL(0x8000033C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP3_REG_P1_0                , RULL(0x8000033C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP3_REG_P1_1                , RULL(0x8000073C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP3_REG_P1_1                , RULL(0x8000073C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP3_REG_P1_2                , RULL(0x80000B3C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP3_REG_P1_2                , RULL(0x80000B3C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP3_REG_P1_3                , RULL(0x80000F3C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP3_REG_P1_3                , RULL(0x80000F3C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_4_RP3_REG_P1_4                , RULL(0x8000133C0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_4_RP3_REG_P1_4                , RULL(0x8000133C0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP3_REG_P2_0                , RULL(0x8000033C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP3_REG_P2_0                , RULL(0x8000033C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP3_REG_P2_1                , RULL(0x8000073C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP3_REG_P2_1                , RULL(0x8000073C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP3_REG_P2_2                , RULL(0x80000B3C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP3_REG_P2_2                , RULL(0x80000B3C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP3_REG_P2_3                , RULL(0x80000F3C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP3_REG_P2_3                , RULL(0x80000F3C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_4_RP3_REG_P2_4                , RULL(0x8000133C0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_4_RP3_REG_P2_4                , RULL(0x8000133C0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP3_REG_P3_0                , RULL(0x8000033C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP3_REG_P3_0                , RULL(0x8000033C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP3_REG_P3_1                , RULL(0x8000073C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP3_REG_P3_1                , RULL(0x8000073C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP3_REG_P3_2                , RULL(0x80000B3C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP3_REG_P3_2                , RULL(0x80000B3C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP3_REG_P3_3                , RULL(0x80000F3C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP3_REG_P3_3                , RULL(0x80000F3C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_4_RP3_REG_P3_4                , RULL(0x8000133C07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_4_RP3_REG_P3_4                , RULL(0x8000133C08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_0                  , RULL(0x8000003D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_0                , RULL(0x8000003D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_0                , RULL(0x8000003D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_1                  , RULL(0x8000043D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_1                , RULL(0x8000043D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_1                , RULL(0x8000043D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_2                  , RULL(0x8000083D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_2                , RULL(0x8000083D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_2                , RULL(0x8000083D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_3                  , RULL(0x80000C3D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_3                , RULL(0x80000C3D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_3                , RULL(0x80000C3D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_4                  , RULL(0x8000103D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_4                , RULL(0x8000103D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_4                , RULL(0x8000103D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP0_REG_P1_0                , RULL(0x8000003D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP0_REG_P1_0                , RULL(0x8000003D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP0_REG_P1_1                , RULL(0x8000043D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP0_REG_P1_1                , RULL(0x8000043D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP0_REG_P1_2                , RULL(0x8000083D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP0_REG_P1_2                , RULL(0x8000083D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP0_REG_P1_3                , RULL(0x80000C3D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP0_REG_P1_3                , RULL(0x80000C3D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP0_REG_P1_4                , RULL(0x8000103D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP0_REG_P1_4                , RULL(0x8000103D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP0_REG_P2_0                , RULL(0x8000003D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP0_REG_P2_0                , RULL(0x8000003D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP0_REG_P2_1                , RULL(0x8000043D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP0_REG_P2_1                , RULL(0x8000043D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP0_REG_P2_2                , RULL(0x8000083D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP0_REG_P2_2                , RULL(0x8000083D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP0_REG_P2_3                , RULL(0x80000C3D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP0_REG_P2_3                , RULL(0x80000C3D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP0_REG_P2_4                , RULL(0x8000103D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP0_REG_P2_4                , RULL(0x8000103D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP0_REG_P3_0                , RULL(0x8000003D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP0_REG_P3_0                , RULL(0x8000003D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP0_REG_P3_1                , RULL(0x8000043D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP0_REG_P3_1                , RULL(0x8000043D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP0_REG_P3_2                , RULL(0x8000083D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP0_REG_P3_2                , RULL(0x8000083D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP0_REG_P3_3                , RULL(0x80000C3D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP0_REG_P3_3                , RULL(0x80000C3D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP0_REG_P3_4                , RULL(0x8000103D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP0_REG_P3_4                , RULL(0x8000103D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_0                  , RULL(0x8000013D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_0                , RULL(0x8000013D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_0                , RULL(0x8000013D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_1                  , RULL(0x8000053D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_1                , RULL(0x8000053D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_1                , RULL(0x8000053D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_2                  , RULL(0x8000093D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_2                , RULL(0x8000093D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_2                , RULL(0x8000093D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_3                  , RULL(0x80000D3D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_3                , RULL(0x80000D3D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_3                , RULL(0x80000D3D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_4                  , RULL(0x8000113D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_4                , RULL(0x8000113D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_4                , RULL(0x8000113D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP1_REG_P1_0                , RULL(0x8000013D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP1_REG_P1_0                , RULL(0x8000013D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP1_REG_P1_1                , RULL(0x8000053D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP1_REG_P1_1                , RULL(0x8000053D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP1_REG_P1_2                , RULL(0x8000093D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP1_REG_P1_2                , RULL(0x8000093D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP1_REG_P1_3                , RULL(0x80000D3D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP1_REG_P1_3                , RULL(0x80000D3D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP1_REG_P1_4                , RULL(0x8000113D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP1_REG_P1_4                , RULL(0x8000113D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP1_REG_P2_0                , RULL(0x8000013D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP1_REG_P2_0                , RULL(0x8000013D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP1_REG_P2_1                , RULL(0x8000053D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP1_REG_P2_1                , RULL(0x8000053D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP1_REG_P2_2                , RULL(0x8000093D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP1_REG_P2_2                , RULL(0x8000093D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP1_REG_P2_3                , RULL(0x80000D3D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP1_REG_P2_3                , RULL(0x80000D3D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP1_REG_P2_4                , RULL(0x8000113D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP1_REG_P2_4                , RULL(0x8000113D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP1_REG_P3_0                , RULL(0x8000013D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP1_REG_P3_0                , RULL(0x8000013D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP1_REG_P3_1                , RULL(0x8000053D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP1_REG_P3_1                , RULL(0x8000053D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP1_REG_P3_2                , RULL(0x8000093D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP1_REG_P3_2                , RULL(0x8000093D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP1_REG_P3_3                , RULL(0x80000D3D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP1_REG_P3_3                , RULL(0x80000D3D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP1_REG_P3_4                , RULL(0x8000113D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP1_REG_P3_4                , RULL(0x8000113D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_0                  , RULL(0x8000023D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_0                , RULL(0x8000023D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_0                , RULL(0x8000023D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_1                  , RULL(0x8000063D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_1                , RULL(0x8000063D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_1                , RULL(0x8000063D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_2                  , RULL(0x80000A3D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_2                , RULL(0x80000A3D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_2                , RULL(0x80000A3D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_3                  , RULL(0x80000E3D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_3                , RULL(0x80000E3D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_3                , RULL(0x80000E3D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_4                  , RULL(0x8000123D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_4                , RULL(0x8000123D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_4                , RULL(0x8000123D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP2_REG_P1_0                , RULL(0x8000023D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP2_REG_P1_0                , RULL(0x8000023D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP2_REG_P1_1                , RULL(0x8000063D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP2_REG_P1_1                , RULL(0x8000063D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP2_REG_P1_2                , RULL(0x80000A3D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP2_REG_P1_2                , RULL(0x80000A3D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP2_REG_P1_3                , RULL(0x80000E3D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP2_REG_P1_3                , RULL(0x80000E3D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP2_REG_P1_4                , RULL(0x8000123D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP2_REG_P1_4                , RULL(0x8000123D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP2_REG_P2_0                , RULL(0x8000023D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP2_REG_P2_0                , RULL(0x8000023D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP2_REG_P2_1                , RULL(0x8000063D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP2_REG_P2_1                , RULL(0x8000063D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP2_REG_P2_2                , RULL(0x80000A3D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP2_REG_P2_2                , RULL(0x80000A3D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP2_REG_P2_3                , RULL(0x80000E3D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP2_REG_P2_3                , RULL(0x80000E3D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP2_REG_P2_4                , RULL(0x8000123D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP2_REG_P2_4                , RULL(0x8000123D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP2_REG_P3_0                , RULL(0x8000023D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP2_REG_P3_0                , RULL(0x8000023D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP2_REG_P3_1                , RULL(0x8000063D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP2_REG_P3_1                , RULL(0x8000063D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP2_REG_P3_2                , RULL(0x80000A3D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP2_REG_P3_2                , RULL(0x80000A3D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP2_REG_P3_3                , RULL(0x80000E3D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP2_REG_P3_3                , RULL(0x80000E3D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP2_REG_P3_4                , RULL(0x8000123D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP2_REG_P3_4                , RULL(0x8000123D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_0                  , RULL(0x8000033D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_0                , RULL(0x8000033D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_0                , RULL(0x8000033D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_1                  , RULL(0x8000073D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_1                , RULL(0x8000073D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_1                , RULL(0x8000073D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_2                  , RULL(0x80000B3D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_2                , RULL(0x80000B3D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_2                , RULL(0x80000B3D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_3                  , RULL(0x80000F3D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_3                , RULL(0x80000F3D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_3                , RULL(0x80000F3D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_4                  , RULL(0x8000133D0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_4                , RULL(0x8000133D0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_4                , RULL(0x8000133D0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP3_REG_P1_0                , RULL(0x8000033D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP3_REG_P1_0                , RULL(0x8000033D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP3_REG_P1_1                , RULL(0x8000073D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP3_REG_P1_1                , RULL(0x8000073D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP3_REG_P1_2                , RULL(0x80000B3D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP3_REG_P1_2                , RULL(0x80000B3D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP3_REG_P1_3                , RULL(0x80000F3D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP3_REG_P1_3                , RULL(0x80000F3D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_5_RP3_REG_P1_4                , RULL(0x8000133D0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_5_RP3_REG_P1_4                , RULL(0x8000133D0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP3_REG_P2_0                , RULL(0x8000033D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP3_REG_P2_0                , RULL(0x8000033D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP3_REG_P2_1                , RULL(0x8000073D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP3_REG_P2_1                , RULL(0x8000073D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP3_REG_P2_2                , RULL(0x80000B3D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP3_REG_P2_2                , RULL(0x80000B3D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP3_REG_P2_3                , RULL(0x80000F3D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP3_REG_P2_3                , RULL(0x80000F3D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_5_RP3_REG_P2_4                , RULL(0x8000133D0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_5_RP3_REG_P2_4                , RULL(0x8000133D0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP3_REG_P3_0                , RULL(0x8000033D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP3_REG_P3_0                , RULL(0x8000033D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP3_REG_P3_1                , RULL(0x8000073D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP3_REG_P3_1                , RULL(0x8000073D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP3_REG_P3_2                , RULL(0x80000B3D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP3_REG_P3_2                , RULL(0x80000B3D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP3_REG_P3_3                , RULL(0x80000F3D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP3_REG_P3_3                , RULL(0x80000F3D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_5_RP3_REG_P3_4                , RULL(0x8000133D07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_5_RP3_REG_P3_4                , RULL(0x8000133D08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_0                  , RULL(0x8000003E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_0                , RULL(0x8000003E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_0                , RULL(0x8000003E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_1                  , RULL(0x8000043E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_1                , RULL(0x8000043E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_1                , RULL(0x8000043E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_2                  , RULL(0x8000083E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_2                , RULL(0x8000083E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_2                , RULL(0x8000083E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_3                  , RULL(0x80000C3E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_3                , RULL(0x80000C3E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_3                , RULL(0x80000C3E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_4                  , RULL(0x8000103E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_4                , RULL(0x8000103E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_4                , RULL(0x8000103E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP0_REG_P1_0                , RULL(0x8000003E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP0_REG_P1_0                , RULL(0x8000003E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP0_REG_P1_1                , RULL(0x8000043E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP0_REG_P1_1                , RULL(0x8000043E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP0_REG_P1_2                , RULL(0x8000083E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP0_REG_P1_2                , RULL(0x8000083E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP0_REG_P1_3                , RULL(0x80000C3E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP0_REG_P1_3                , RULL(0x80000C3E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP0_REG_P1_4                , RULL(0x8000103E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP0_REG_P1_4                , RULL(0x8000103E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP0_REG_P2_0                , RULL(0x8000003E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP0_REG_P2_0                , RULL(0x8000003E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP0_REG_P2_1                , RULL(0x8000043E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP0_REG_P2_1                , RULL(0x8000043E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP0_REG_P2_2                , RULL(0x8000083E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP0_REG_P2_2                , RULL(0x8000083E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP0_REG_P2_3                , RULL(0x80000C3E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP0_REG_P2_3                , RULL(0x80000C3E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP0_REG_P2_4                , RULL(0x8000103E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP0_REG_P2_4                , RULL(0x8000103E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP0_REG_P3_0                , RULL(0x8000003E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP0_REG_P3_0                , RULL(0x8000003E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP0_REG_P3_1                , RULL(0x8000043E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP0_REG_P3_1                , RULL(0x8000043E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP0_REG_P3_2                , RULL(0x8000083E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP0_REG_P3_2                , RULL(0x8000083E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP0_REG_P3_3                , RULL(0x80000C3E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP0_REG_P3_3                , RULL(0x80000C3E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP0_REG_P3_4                , RULL(0x8000103E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP0_REG_P3_4                , RULL(0x8000103E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_0                  , RULL(0x8000013E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_0                , RULL(0x8000013E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_0                , RULL(0x8000013E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_1                  , RULL(0x8000053E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_1                , RULL(0x8000053E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_1                , RULL(0x8000053E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_2                  , RULL(0x8000093E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_2                , RULL(0x8000093E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_2                , RULL(0x8000093E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_3                  , RULL(0x80000D3E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_3                , RULL(0x80000D3E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_3                , RULL(0x80000D3E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_4                  , RULL(0x8000113E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_4                , RULL(0x8000113E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_4                , RULL(0x8000113E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP1_REG_P1_0                , RULL(0x8000013E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP1_REG_P1_0                , RULL(0x8000013E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP1_REG_P1_1                , RULL(0x8000053E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP1_REG_P1_1                , RULL(0x8000053E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP1_REG_P1_2                , RULL(0x8000093E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP1_REG_P1_2                , RULL(0x8000093E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP1_REG_P1_3                , RULL(0x80000D3E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP1_REG_P1_3                , RULL(0x80000D3E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP1_REG_P1_4                , RULL(0x8000113E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP1_REG_P1_4                , RULL(0x8000113E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP1_REG_P2_0                , RULL(0x8000013E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP1_REG_P2_0                , RULL(0x8000013E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP1_REG_P2_1                , RULL(0x8000053E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP1_REG_P2_1                , RULL(0x8000053E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP1_REG_P2_2                , RULL(0x8000093E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP1_REG_P2_2                , RULL(0x8000093E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP1_REG_P2_3                , RULL(0x80000D3E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP1_REG_P2_3                , RULL(0x80000D3E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP1_REG_P2_4                , RULL(0x8000113E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP1_REG_P2_4                , RULL(0x8000113E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP1_REG_P3_0                , RULL(0x8000013E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP1_REG_P3_0                , RULL(0x8000013E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP1_REG_P3_1                , RULL(0x8000053E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP1_REG_P3_1                , RULL(0x8000053E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP1_REG_P3_2                , RULL(0x8000093E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP1_REG_P3_2                , RULL(0x8000093E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP1_REG_P3_3                , RULL(0x80000D3E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP1_REG_P3_3                , RULL(0x80000D3E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP1_REG_P3_4                , RULL(0x8000113E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP1_REG_P3_4                , RULL(0x8000113E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_0                  , RULL(0x8000023E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_0                , RULL(0x8000023E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_0                , RULL(0x8000023E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_1                  , RULL(0x8000063E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_1                , RULL(0x8000063E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_1                , RULL(0x8000063E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_2                  , RULL(0x80000A3E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_2                , RULL(0x80000A3E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_2                , RULL(0x80000A3E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_3                  , RULL(0x80000E3E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_3                , RULL(0x80000E3E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_3                , RULL(0x80000E3E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_4                  , RULL(0x8000123E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_4                , RULL(0x8000123E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_4                , RULL(0x8000123E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP2_REG_P1_0                , RULL(0x8000023E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP2_REG_P1_0                , RULL(0x8000023E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP2_REG_P1_1                , RULL(0x8000063E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP2_REG_P1_1                , RULL(0x8000063E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP2_REG_P1_2                , RULL(0x80000A3E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP2_REG_P1_2                , RULL(0x80000A3E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP2_REG_P1_3                , RULL(0x80000E3E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP2_REG_P1_3                , RULL(0x80000E3E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP2_REG_P1_4                , RULL(0x8000123E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP2_REG_P1_4                , RULL(0x8000123E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP2_REG_P2_0                , RULL(0x8000023E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP2_REG_P2_0                , RULL(0x8000023E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP2_REG_P2_1                , RULL(0x8000063E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP2_REG_P2_1                , RULL(0x8000063E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP2_REG_P2_2                , RULL(0x80000A3E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP2_REG_P2_2                , RULL(0x80000A3E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP2_REG_P2_3                , RULL(0x80000E3E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP2_REG_P2_3                , RULL(0x80000E3E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP2_REG_P2_4                , RULL(0x8000123E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP2_REG_P2_4                , RULL(0x8000123E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP2_REG_P3_0                , RULL(0x8000023E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP2_REG_P3_0                , RULL(0x8000023E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP2_REG_P3_1                , RULL(0x8000063E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP2_REG_P3_1                , RULL(0x8000063E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP2_REG_P3_2                , RULL(0x80000A3E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP2_REG_P3_2                , RULL(0x80000A3E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP2_REG_P3_3                , RULL(0x80000E3E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP2_REG_P3_3                , RULL(0x80000E3E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP2_REG_P3_4                , RULL(0x8000123E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP2_REG_P3_4                , RULL(0x8000123E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_0                  , RULL(0x8000033E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_0                , RULL(0x8000033E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_0                , RULL(0x8000033E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_1                  , RULL(0x8000073E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_1                , RULL(0x8000073E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_1                , RULL(0x8000073E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_2                  , RULL(0x80000B3E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_2                , RULL(0x80000B3E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_2                , RULL(0x80000B3E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_3                  , RULL(0x80000F3E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_3                , RULL(0x80000F3E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_3                , RULL(0x80000F3E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_4                  , RULL(0x8000133E0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_4                , RULL(0x8000133E0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_4                , RULL(0x8000133E0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP3_REG_P1_0                , RULL(0x8000033E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP3_REG_P1_0                , RULL(0x8000033E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP3_REG_P1_1                , RULL(0x8000073E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP3_REG_P1_1                , RULL(0x8000073E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP3_REG_P1_2                , RULL(0x80000B3E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP3_REG_P1_2                , RULL(0x80000B3E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP3_REG_P1_3                , RULL(0x80000F3E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP3_REG_P1_3                , RULL(0x80000F3E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_6_RP3_REG_P1_4                , RULL(0x8000133E0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_6_RP3_REG_P1_4                , RULL(0x8000133E0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP3_REG_P2_0                , RULL(0x8000033E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP3_REG_P2_0                , RULL(0x8000033E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP3_REG_P2_1                , RULL(0x8000073E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP3_REG_P2_1                , RULL(0x8000073E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP3_REG_P2_2                , RULL(0x80000B3E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP3_REG_P2_2                , RULL(0x80000B3E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP3_REG_P2_3                , RULL(0x80000F3E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP3_REG_P2_3                , RULL(0x80000F3E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_6_RP3_REG_P2_4                , RULL(0x8000133E0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_6_RP3_REG_P2_4                , RULL(0x8000133E0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP3_REG_P3_0                , RULL(0x8000033E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP3_REG_P3_0                , RULL(0x8000033E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP3_REG_P3_1                , RULL(0x8000073E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP3_REG_P3_1                , RULL(0x8000073E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP3_REG_P3_2                , RULL(0x80000B3E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP3_REG_P3_2                , RULL(0x80000B3E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP3_REG_P3_3                , RULL(0x80000F3E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP3_REG_P3_3                , RULL(0x80000F3E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_6_RP3_REG_P3_4                , RULL(0x8000133E07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_6_RP3_REG_P3_4                , RULL(0x8000133E08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_0                  , RULL(0x8000003F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_0                , RULL(0x8000003F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_0                , RULL(0x8000003F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_1                  , RULL(0x8000043F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_1                , RULL(0x8000043F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_1                , RULL(0x8000043F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_2                  , RULL(0x8000083F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_2                , RULL(0x8000083F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_2                , RULL(0x8000083F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_3                  , RULL(0x80000C3F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_3                , RULL(0x80000C3F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_3                , RULL(0x80000C3F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_4                  , RULL(0x8000103F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_4                , RULL(0x8000103F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_4                , RULL(0x8000103F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP0_REG_P1_0                , RULL(0x8000003F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP0_REG_P1_0                , RULL(0x8000003F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP0_REG_P1_1                , RULL(0x8000043F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP0_REG_P1_1                , RULL(0x8000043F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP0_REG_P1_2                , RULL(0x8000083F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP0_REG_P1_2                , RULL(0x8000083F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP0_REG_P1_3                , RULL(0x80000C3F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP0_REG_P1_3                , RULL(0x80000C3F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP0_REG_P1_4                , RULL(0x8000103F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP0_REG_P1_4                , RULL(0x8000103F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP0_REG_P2_0                , RULL(0x8000003F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP0_REG_P2_0                , RULL(0x8000003F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP0_REG_P2_1                , RULL(0x8000043F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP0_REG_P2_1                , RULL(0x8000043F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP0_REG_P2_2                , RULL(0x8000083F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP0_REG_P2_2                , RULL(0x8000083F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP0_REG_P2_3                , RULL(0x80000C3F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP0_REG_P2_3                , RULL(0x80000C3F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP0_REG_P2_4                , RULL(0x8000103F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP0_REG_P2_4                , RULL(0x8000103F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP0_REG_P3_0                , RULL(0x8000003F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP0_REG_P3_0                , RULL(0x8000003F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP0_REG_P3_1                , RULL(0x8000043F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP0_REG_P3_1                , RULL(0x8000043F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP0_REG_P3_2                , RULL(0x8000083F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP0_REG_P3_2                , RULL(0x8000083F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP0_REG_P3_3                , RULL(0x80000C3F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP0_REG_P3_3                , RULL(0x80000C3F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP0_REG_P3_4                , RULL(0x8000103F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP0_REG_P3_4                , RULL(0x8000103F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_0                  , RULL(0x8000013F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_0                , RULL(0x8000013F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_0                , RULL(0x8000013F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_1                  , RULL(0x8000053F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_1                , RULL(0x8000053F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_1                , RULL(0x8000053F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_2                  , RULL(0x8000093F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_2                , RULL(0x8000093F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_2                , RULL(0x8000093F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_3                  , RULL(0x80000D3F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_3                , RULL(0x80000D3F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_3                , RULL(0x80000D3F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_4                  , RULL(0x8000113F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_4                , RULL(0x8000113F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_4                , RULL(0x8000113F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP1_REG_P1_0                , RULL(0x8000013F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP1_REG_P1_0                , RULL(0x8000013F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP1_REG_P1_1                , RULL(0x8000053F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP1_REG_P1_1                , RULL(0x8000053F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP1_REG_P1_2                , RULL(0x8000093F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP1_REG_P1_2                , RULL(0x8000093F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP1_REG_P1_3                , RULL(0x80000D3F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP1_REG_P1_3                , RULL(0x80000D3F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP1_REG_P1_4                , RULL(0x8000113F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP1_REG_P1_4                , RULL(0x8000113F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP1_REG_P2_0                , RULL(0x8000013F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP1_REG_P2_0                , RULL(0x8000013F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP1_REG_P2_1                , RULL(0x8000053F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP1_REG_P2_1                , RULL(0x8000053F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP1_REG_P2_2                , RULL(0x8000093F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP1_REG_P2_2                , RULL(0x8000093F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP1_REG_P2_3                , RULL(0x80000D3F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP1_REG_P2_3                , RULL(0x80000D3F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP1_REG_P2_4                , RULL(0x8000113F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP1_REG_P2_4                , RULL(0x8000113F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP1_REG_P3_0                , RULL(0x8000013F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP1_REG_P3_0                , RULL(0x8000013F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP1_REG_P3_1                , RULL(0x8000053F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP1_REG_P3_1                , RULL(0x8000053F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP1_REG_P3_2                , RULL(0x8000093F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP1_REG_P3_2                , RULL(0x8000093F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP1_REG_P3_3                , RULL(0x80000D3F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP1_REG_P3_3                , RULL(0x80000D3F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP1_REG_P3_4                , RULL(0x8000113F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP1_REG_P3_4                , RULL(0x8000113F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_0                  , RULL(0x8000023F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_0                , RULL(0x8000023F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_0                , RULL(0x8000023F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_1                  , RULL(0x8000063F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_1                , RULL(0x8000063F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_1                , RULL(0x8000063F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_2                  , RULL(0x80000A3F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_2                , RULL(0x80000A3F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_2                , RULL(0x80000A3F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_3                  , RULL(0x80000E3F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_3                , RULL(0x80000E3F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_3                , RULL(0x80000E3F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_4                  , RULL(0x8000123F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_4                , RULL(0x8000123F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_4                , RULL(0x8000123F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP2_REG_P1_0                , RULL(0x8000023F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP2_REG_P1_0                , RULL(0x8000023F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP2_REG_P1_1                , RULL(0x8000063F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP2_REG_P1_1                , RULL(0x8000063F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP2_REG_P1_2                , RULL(0x80000A3F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP2_REG_P1_2                , RULL(0x80000A3F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP2_REG_P1_3                , RULL(0x80000E3F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP2_REG_P1_3                , RULL(0x80000E3F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP2_REG_P1_4                , RULL(0x8000123F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP2_REG_P1_4                , RULL(0x8000123F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP2_REG_P2_0                , RULL(0x8000023F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP2_REG_P2_0                , RULL(0x8000023F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP2_REG_P2_1                , RULL(0x8000063F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP2_REG_P2_1                , RULL(0x8000063F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP2_REG_P2_2                , RULL(0x80000A3F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP2_REG_P2_2                , RULL(0x80000A3F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP2_REG_P2_3                , RULL(0x80000E3F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP2_REG_P2_3                , RULL(0x80000E3F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP2_REG_P2_4                , RULL(0x8000123F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP2_REG_P2_4                , RULL(0x8000123F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP2_REG_P3_0                , RULL(0x8000023F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP2_REG_P3_0                , RULL(0x8000023F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP2_REG_P3_1                , RULL(0x8000063F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP2_REG_P3_1                , RULL(0x8000063F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP2_REG_P3_2                , RULL(0x80000A3F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP2_REG_P3_2                , RULL(0x80000A3F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP2_REG_P3_3                , RULL(0x80000E3F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP2_REG_P3_3                , RULL(0x80000E3F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP2_REG_P3_4                , RULL(0x8000123F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP2_REG_P3_4                , RULL(0x8000123F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_0                  , RULL(0x8000033F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_0                , RULL(0x8000033F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_0                , RULL(0x8000033F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_1                  , RULL(0x8000073F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_1                , RULL(0x8000073F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_1                , RULL(0x8000073F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_2                  , RULL(0x80000B3F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_2                , RULL(0x80000B3F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_2                , RULL(0x80000B3F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_3                  , RULL(0x80000F3F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_3                , RULL(0x80000F3F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_3                , RULL(0x80000F3F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_4                  , RULL(0x8000133F0701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_4                , RULL(0x8000133F0701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_4                , RULL(0x8000133F0801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP3_REG_P1_0                , RULL(0x8000033F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP3_REG_P1_0                , RULL(0x8000033F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP3_REG_P1_1                , RULL(0x8000073F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP3_REG_P1_1                , RULL(0x8000073F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP3_REG_P1_2                , RULL(0x80000B3F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP3_REG_P1_2                , RULL(0x80000B3F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP3_REG_P1_3                , RULL(0x80000F3F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP3_REG_P1_3                , RULL(0x80000F3F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_7_RP3_REG_P1_4                , RULL(0x8000133F0701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_7_RP3_REG_P1_4                , RULL(0x8000133F0801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP3_REG_P2_0                , RULL(0x8000033F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP3_REG_P2_0                , RULL(0x8000033F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP3_REG_P2_1                , RULL(0x8000073F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP3_REG_P2_1                , RULL(0x8000073F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP3_REG_P2_2                , RULL(0x80000B3F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP3_REG_P2_2                , RULL(0x80000B3F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP3_REG_P2_3                , RULL(0x80000F3F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP3_REG_P2_3                , RULL(0x80000F3F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_7_RP3_REG_P2_4                , RULL(0x8000133F0701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_7_RP3_REG_P2_4                , RULL(0x8000133F0801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP3_REG_P3_0                , RULL(0x8000033F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP3_REG_P3_0                , RULL(0x8000033F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP3_REG_P3_1                , RULL(0x8000073F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP3_REG_P3_1                , RULL(0x8000073F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP3_REG_P3_2                , RULL(0x80000B3F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP3_REG_P3_2                , RULL(0x80000B3F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP3_REG_P3_3                , RULL(0x80000F3F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP3_REG_P3_3                , RULL(0x80000F3F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_7_RP3_REG_P3_4                , RULL(0x8000133F07011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_7_RP3_REG_P3_4                , RULL(0x8000133F08011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_0                  , RULL(0x800000400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_0                , RULL(0x800000400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_0                , RULL(0x800000400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_1                  , RULL(0x800004400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_1                , RULL(0x800004400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_1                , RULL(0x800004400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_2                  , RULL(0x800008400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_2                , RULL(0x800008400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_2                , RULL(0x800008400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_3                  , RULL(0x80000C400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_3                , RULL(0x80000C400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_3                , RULL(0x80000C400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_4                  , RULL(0x800010400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_4                , RULL(0x800010400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_4                , RULL(0x800010400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP0_REG_P1_0                , RULL(0x800000400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP0_REG_P1_0                , RULL(0x800000400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP0_REG_P1_1                , RULL(0x800004400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP0_REG_P1_1                , RULL(0x800004400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP0_REG_P1_2                , RULL(0x800008400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP0_REG_P1_2                , RULL(0x800008400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP0_REG_P1_3                , RULL(0x80000C400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP0_REG_P1_3                , RULL(0x80000C400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP0_REG_P1_4                , RULL(0x800010400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP0_REG_P1_4                , RULL(0x800010400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP0_REG_P2_0                , RULL(0x800000400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP0_REG_P2_0                , RULL(0x800000400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP0_REG_P2_1                , RULL(0x800004400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP0_REG_P2_1                , RULL(0x800004400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP0_REG_P2_2                , RULL(0x800008400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP0_REG_P2_2                , RULL(0x800008400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP0_REG_P2_3                , RULL(0x80000C400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP0_REG_P2_3                , RULL(0x80000C400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP0_REG_P2_4                , RULL(0x800010400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP0_REG_P2_4                , RULL(0x800010400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP0_REG_P3_0                , RULL(0x8000004007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP0_REG_P3_0                , RULL(0x8000004008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP0_REG_P3_1                , RULL(0x8000044007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP0_REG_P3_1                , RULL(0x8000044008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP0_REG_P3_2                , RULL(0x8000084007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP0_REG_P3_2                , RULL(0x8000084008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP0_REG_P3_3                , RULL(0x80000C4007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP0_REG_P3_3                , RULL(0x80000C4008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP0_REG_P3_4                , RULL(0x8000104007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP0_REG_P3_4                , RULL(0x8000104008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_0                  , RULL(0x800001400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_0                , RULL(0x800001400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_0                , RULL(0x800001400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_1                  , RULL(0x800005400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_1                , RULL(0x800005400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_1                , RULL(0x800005400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_2                  , RULL(0x800009400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_2                , RULL(0x800009400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_2                , RULL(0x800009400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_3                  , RULL(0x80000D400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_3                , RULL(0x80000D400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_3                , RULL(0x80000D400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_4                  , RULL(0x800011400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_4                , RULL(0x800011400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_4                , RULL(0x800011400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP1_REG_P1_0                , RULL(0x800001400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP1_REG_P1_0                , RULL(0x800001400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP1_REG_P1_1                , RULL(0x800005400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP1_REG_P1_1                , RULL(0x800005400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP1_REG_P1_2                , RULL(0x800009400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP1_REG_P1_2                , RULL(0x800009400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP1_REG_P1_3                , RULL(0x80000D400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP1_REG_P1_3                , RULL(0x80000D400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP1_REG_P1_4                , RULL(0x800011400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP1_REG_P1_4                , RULL(0x800011400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP1_REG_P2_0                , RULL(0x800001400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP1_REG_P2_0                , RULL(0x800001400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP1_REG_P2_1                , RULL(0x800005400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP1_REG_P2_1                , RULL(0x800005400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP1_REG_P2_2                , RULL(0x800009400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP1_REG_P2_2                , RULL(0x800009400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP1_REG_P2_3                , RULL(0x80000D400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP1_REG_P2_3                , RULL(0x80000D400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP1_REG_P2_4                , RULL(0x800011400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP1_REG_P2_4                , RULL(0x800011400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP1_REG_P3_0                , RULL(0x8000014007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP1_REG_P3_0                , RULL(0x8000014008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP1_REG_P3_1                , RULL(0x8000054007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP1_REG_P3_1                , RULL(0x8000054008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP1_REG_P3_2                , RULL(0x8000094007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP1_REG_P3_2                , RULL(0x8000094008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP1_REG_P3_3                , RULL(0x80000D4007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP1_REG_P3_3                , RULL(0x80000D4008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP1_REG_P3_4                , RULL(0x8000114007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP1_REG_P3_4                , RULL(0x8000114008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_0                  , RULL(0x800002400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_0                , RULL(0x800002400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_0                , RULL(0x800002400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_1                  , RULL(0x800006400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_1                , RULL(0x800006400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_1                , RULL(0x800006400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_2                  , RULL(0x80000A400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_2                , RULL(0x80000A400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_2                , RULL(0x80000A400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_3                  , RULL(0x80000E400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_3                , RULL(0x80000E400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_3                , RULL(0x80000E400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_4                  , RULL(0x800012400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_4                , RULL(0x800012400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_4                , RULL(0x800012400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP2_REG_P1_0                , RULL(0x800002400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP2_REG_P1_0                , RULL(0x800002400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP2_REG_P1_1                , RULL(0x800006400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP2_REG_P1_1                , RULL(0x800006400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP2_REG_P1_2                , RULL(0x80000A400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP2_REG_P1_2                , RULL(0x80000A400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP2_REG_P1_3                , RULL(0x80000E400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP2_REG_P1_3                , RULL(0x80000E400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP2_REG_P1_4                , RULL(0x800012400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP2_REG_P1_4                , RULL(0x800012400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP2_REG_P2_0                , RULL(0x800002400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP2_REG_P2_0                , RULL(0x800002400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP2_REG_P2_1                , RULL(0x800006400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP2_REG_P2_1                , RULL(0x800006400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP2_REG_P2_2                , RULL(0x80000A400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP2_REG_P2_2                , RULL(0x80000A400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP2_REG_P2_3                , RULL(0x80000E400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP2_REG_P2_3                , RULL(0x80000E400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP2_REG_P2_4                , RULL(0x800012400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP2_REG_P2_4                , RULL(0x800012400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP2_REG_P3_0                , RULL(0x8000024007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP2_REG_P3_0                , RULL(0x8000024008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP2_REG_P3_1                , RULL(0x8000064007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP2_REG_P3_1                , RULL(0x8000064008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP2_REG_P3_2                , RULL(0x80000A4007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP2_REG_P3_2                , RULL(0x80000A4008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP2_REG_P3_3                , RULL(0x80000E4007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP2_REG_P3_3                , RULL(0x80000E4008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP2_REG_P3_4                , RULL(0x8000124007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP2_REG_P3_4                , RULL(0x8000124008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_0                  , RULL(0x800003400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_0                , RULL(0x800003400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_0                , RULL(0x800003400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_1                  , RULL(0x800007400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_1                , RULL(0x800007400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_1                , RULL(0x800007400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_2                  , RULL(0x80000B400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_2                , RULL(0x80000B400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_2                , RULL(0x80000B400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_3                  , RULL(0x80000F400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_3                , RULL(0x80000F400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_3                , RULL(0x80000F400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_4                  , RULL(0x800013400701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_4                , RULL(0x800013400701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_4                , RULL(0x800013400801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP3_REG_P1_0                , RULL(0x800003400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP3_REG_P1_0                , RULL(0x800003400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP3_REG_P1_1                , RULL(0x800007400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP3_REG_P1_1                , RULL(0x800007400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP3_REG_P1_2                , RULL(0x80000B400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP3_REG_P1_2                , RULL(0x80000B400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP3_REG_P1_3                , RULL(0x80000F400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP3_REG_P1_3                , RULL(0x80000F400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_8_RP3_REG_P1_4                , RULL(0x800013400701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_8_RP3_REG_P1_4                , RULL(0x800013400801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP3_REG_P2_0                , RULL(0x800003400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP3_REG_P2_0                , RULL(0x800003400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP3_REG_P2_1                , RULL(0x800007400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP3_REG_P2_1                , RULL(0x800007400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP3_REG_P2_2                , RULL(0x80000B400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP3_REG_P2_2                , RULL(0x80000B400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP3_REG_P2_3                , RULL(0x80000F400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP3_REG_P2_3                , RULL(0x80000F400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_8_RP3_REG_P2_4                , RULL(0x800013400701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_8_RP3_REG_P2_4                , RULL(0x800013400801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP3_REG_P3_0                , RULL(0x8000034007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP3_REG_P3_0                , RULL(0x8000034008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP3_REG_P3_1                , RULL(0x8000074007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP3_REG_P3_1                , RULL(0x8000074008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP3_REG_P3_2                , RULL(0x80000B4007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP3_REG_P3_2                , RULL(0x80000B4008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP3_REG_P3_3                , RULL(0x80000F4007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP3_REG_P3_3                , RULL(0x80000F4008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_8_RP3_REG_P3_4                , RULL(0x8000134007011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_8_RP3_REG_P3_4                , RULL(0x8000134008011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_0                  , RULL(0x800000410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_0                , RULL(0x800000410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_0                , RULL(0x800000410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_1                  , RULL(0x800004410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_1                , RULL(0x800004410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_1                , RULL(0x800004410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_2                  , RULL(0x800008410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_2                , RULL(0x800008410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_2                , RULL(0x800008410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_3                  , RULL(0x80000C410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_3                , RULL(0x80000C410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_3                , RULL(0x80000C410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_4                  , RULL(0x800010410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_4                , RULL(0x800010410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_4                , RULL(0x800010410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP0_REG_P1_0                , RULL(0x800000410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP0_REG_P1_0                , RULL(0x800000410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP0_REG_P1_1                , RULL(0x800004410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP0_REG_P1_1                , RULL(0x800004410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP0_REG_P1_2                , RULL(0x800008410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP0_REG_P1_2                , RULL(0x800008410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP0_REG_P1_3                , RULL(0x80000C410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP0_REG_P1_3                , RULL(0x80000C410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP0_REG_P1_4                , RULL(0x800010410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP0_REG_P1_4                , RULL(0x800010410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP0_REG_P2_0                , RULL(0x800000410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP0_REG_P2_0                , RULL(0x800000410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP0_REG_P2_1                , RULL(0x800004410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP0_REG_P2_1                , RULL(0x800004410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP0_REG_P2_2                , RULL(0x800008410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP0_REG_P2_2                , RULL(0x800008410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP0_REG_P2_3                , RULL(0x80000C410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP0_REG_P2_3                , RULL(0x80000C410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP0_REG_P2_4                , RULL(0x800010410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP0_REG_P2_4                , RULL(0x800010410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP0_REG_P3_0                , RULL(0x8000004107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP0_REG_P3_0                , RULL(0x8000004108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP0_REG_P3_1                , RULL(0x8000044107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP0_REG_P3_1                , RULL(0x8000044108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP0_REG_P3_2                , RULL(0x8000084107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP0_REG_P3_2                , RULL(0x8000084108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP0_REG_P3_3                , RULL(0x80000C4107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP0_REG_P3_3                , RULL(0x80000C4108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP0_REG_P3_4                , RULL(0x8000104107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP0_REG_P3_4                , RULL(0x8000104108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_0                  , RULL(0x800001410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_0                , RULL(0x800001410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_0                , RULL(0x800001410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_1                  , RULL(0x800005410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_1                , RULL(0x800005410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_1                , RULL(0x800005410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_2                  , RULL(0x800009410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_2                , RULL(0x800009410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_2                , RULL(0x800009410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_3                  , RULL(0x80000D410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_3                , RULL(0x80000D410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_3                , RULL(0x80000D410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_4                  , RULL(0x800011410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_4                , RULL(0x800011410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_4                , RULL(0x800011410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP1_REG_P1_0                , RULL(0x800001410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP1_REG_P1_0                , RULL(0x800001410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP1_REG_P1_1                , RULL(0x800005410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP1_REG_P1_1                , RULL(0x800005410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP1_REG_P1_2                , RULL(0x800009410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP1_REG_P1_2                , RULL(0x800009410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP1_REG_P1_3                , RULL(0x80000D410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP1_REG_P1_3                , RULL(0x80000D410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP1_REG_P1_4                , RULL(0x800011410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP1_REG_P1_4                , RULL(0x800011410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP1_REG_P2_0                , RULL(0x800001410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP1_REG_P2_0                , RULL(0x800001410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP1_REG_P2_1                , RULL(0x800005410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP1_REG_P2_1                , RULL(0x800005410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP1_REG_P2_2                , RULL(0x800009410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP1_REG_P2_2                , RULL(0x800009410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP1_REG_P2_3                , RULL(0x80000D410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP1_REG_P2_3                , RULL(0x80000D410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP1_REG_P2_4                , RULL(0x800011410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP1_REG_P2_4                , RULL(0x800011410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP1_REG_P3_0                , RULL(0x8000014107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP1_REG_P3_0                , RULL(0x8000014108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP1_REG_P3_1                , RULL(0x8000054107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP1_REG_P3_1                , RULL(0x8000054108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP1_REG_P3_2                , RULL(0x8000094107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP1_REG_P3_2                , RULL(0x8000094108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP1_REG_P3_3                , RULL(0x80000D4107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP1_REG_P3_3                , RULL(0x80000D4108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP1_REG_P3_4                , RULL(0x8000114107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP1_REG_P3_4                , RULL(0x8000114108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_0                  , RULL(0x800002410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_0                , RULL(0x800002410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_0                , RULL(0x800002410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_1                  , RULL(0x800006410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_1                , RULL(0x800006410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_1                , RULL(0x800006410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_2                  , RULL(0x80000A410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_2                , RULL(0x80000A410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_2                , RULL(0x80000A410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_3                  , RULL(0x80000E410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_3                , RULL(0x80000E410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_3                , RULL(0x80000E410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_4                  , RULL(0x800012410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_4                , RULL(0x800012410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_4                , RULL(0x800012410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP2_REG_P1_0                , RULL(0x800002410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP2_REG_P1_0                , RULL(0x800002410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP2_REG_P1_1                , RULL(0x800006410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP2_REG_P1_1                , RULL(0x800006410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP2_REG_P1_2                , RULL(0x80000A410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP2_REG_P1_2                , RULL(0x80000A410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP2_REG_P1_3                , RULL(0x80000E410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP2_REG_P1_3                , RULL(0x80000E410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP2_REG_P1_4                , RULL(0x800012410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP2_REG_P1_4                , RULL(0x800012410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP2_REG_P2_0                , RULL(0x800002410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP2_REG_P2_0                , RULL(0x800002410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP2_REG_P2_1                , RULL(0x800006410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP2_REG_P2_1                , RULL(0x800006410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP2_REG_P2_2                , RULL(0x80000A410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP2_REG_P2_2                , RULL(0x80000A410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP2_REG_P2_3                , RULL(0x80000E410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP2_REG_P2_3                , RULL(0x80000E410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP2_REG_P2_4                , RULL(0x800012410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP2_REG_P2_4                , RULL(0x800012410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP2_REG_P3_0                , RULL(0x8000024107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP2_REG_P3_0                , RULL(0x8000024108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP2_REG_P3_1                , RULL(0x8000064107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP2_REG_P3_1                , RULL(0x8000064108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP2_REG_P3_2                , RULL(0x80000A4107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP2_REG_P3_2                , RULL(0x80000A4108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP2_REG_P3_3                , RULL(0x80000E4107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP2_REG_P3_3                , RULL(0x80000E4108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP2_REG_P3_4                , RULL(0x8000124107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP2_REG_P3_4                , RULL(0x8000124108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_0                  , RULL(0x800003410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_0                , RULL(0x800003410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_0                , RULL(0x800003410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_1                  , RULL(0x800007410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_1                , RULL(0x800007410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_1                , RULL(0x800007410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_2                  , RULL(0x80000B410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_2                , RULL(0x80000B410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_2                , RULL(0x80000B410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_3                  , RULL(0x80000F410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_3                , RULL(0x80000F410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_3                , RULL(0x80000F410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_4                  , RULL(0x800013410701103F), SH_UNT_MCA      ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_0_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_4                , RULL(0x800013410701103F), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_4                , RULL(0x800013410801103F), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP3_REG_P1_0                , RULL(0x800003410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP3_REG_P1_0                , RULL(0x800003410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP3_REG_P1_1                , RULL(0x800007410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP3_REG_P1_1                , RULL(0x800007410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP3_REG_P1_2                , RULL(0x80000B410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP3_REG_P1_2                , RULL(0x80000B410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP3_REG_P1_3                , RULL(0x80000F410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP3_REG_P1_3                , RULL(0x80000F410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_DP16_WR_DELAY_VALUE_9_RP3_REG_P1_4                , RULL(0x800013410701143F), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_DP16_WR_DELAY_VALUE_9_RP3_REG_P1_4                , RULL(0x800013410801143F), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP3_REG_P2_0                , RULL(0x800003410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP3_REG_P2_0                , RULL(0x800003410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP3_REG_P2_1                , RULL(0x800007410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP3_REG_P2_1                , RULL(0x800007410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP3_REG_P2_2                , RULL(0x80000B410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP3_REG_P2_2                , RULL(0x80000B410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP3_REG_P2_3                , RULL(0x80000F410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP3_REG_P2_3                , RULL(0x80000F410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_DP16_WR_DELAY_VALUE_9_RP3_REG_P2_4                , RULL(0x800013410701183F), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_DP16_WR_DELAY_VALUE_9_RP3_REG_P2_4                , RULL(0x800013410801183F), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP3_REG_P3_0                , RULL(0x8000034107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP3_REG_P3_0                , RULL(0x8000034108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP3_REG_P3_1                , RULL(0x8000074107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP3_REG_P3_1                , RULL(0x8000074108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP3_REG_P3_2                , RULL(0x80000B4107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP3_REG_P3_2                , RULL(0x80000B4108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP3_REG_P3_3                , RULL(0x80000F4107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP3_REG_P3_3                , RULL(0x80000F4108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_DP16_WR_DELAY_VALUE_9_RP3_REG_P3_4                , RULL(0x8000134107011C3F), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_DP16_WR_DELAY_VALUE_9_RP3_REG_P3_4                , RULL(0x8000134108011C3F), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_EICR                                                , RULL(0x07010A0D), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_EICR                                              , RULL(0x07010A0D), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_EICR                                              , RULL(0x07010A4D), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_EICR                                              , RULL(0x07010A8D), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_EICR                                              , RULL(0x07010ACD), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_EICR                                              , RULL(0x08010A0D), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_EICR                                              , RULL(0x08010A4D), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_EICR                                              , RULL(0x08010A8D), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_EICR                                              , RULL(0x08010ACD), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_ELPR                                                , RULL(0x07010A2F), SH_UNT_MCA      , SH_ACS_SCOM_RO   );
+REG64( MCA_0_ELPR                                              , RULL(0x07010A2F), SH_UNT_MCA_0    , SH_ACS_SCOM_RO   );
+REG64( MCA_1_ELPR                                              , RULL(0x07010A6F), SH_UNT_MCA_1    , SH_ACS_SCOM_RO   );
+REG64( MCA_2_ELPR                                              , RULL(0x07010AAF), SH_UNT_MCA_2    , SH_ACS_SCOM_RO   );
+REG64( MCA_3_ELPR                                              , RULL(0x07010AEF), SH_UNT_MCA_3    , SH_ACS_SCOM_RO   );
+REG64( MCA_4_ELPR                                              , RULL(0x08010A2F), SH_UNT_MCA_4    , SH_ACS_SCOM_RO   );
+REG64( MCA_5_ELPR                                              , RULL(0x08010A6F), SH_UNT_MCA_5    , SH_ACS_SCOM_RO   );
+REG64( MCA_6_ELPR                                              , RULL(0x08010AAF), SH_UNT_MCA_6    , SH_ACS_SCOM_RO   );
+REG64( MCA_7_ELPR                                              , RULL(0x08010AEF), SH_UNT_MCA_7    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_FIR                                                 , RULL(0x07010A00), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_FIR_OR                                              , RULL(0x07010A02), SH_UNT_MCA      , SH_ACS_SCOM2_OR  );
+REG64( MCA_0_FIR                                               , RULL(0x07010A00), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_0_FIR_OR                                            , RULL(0x07010A02), SH_UNT_MCA_0    , SH_ACS_SCOM2_OR  );
+REG64( MCA_0_WDF_FIR                                           , RULL(0x07010A01), SH_UNT_MCA_0_WDF, SH_ACS_SCOM1_AND );
+REG64( MCA_1_FIR                                               , RULL(0x07010A40), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_FIR_OR                                            , RULL(0x07010A42), SH_UNT_MCA_1    , SH_ACS_SCOM2_OR  );
+REG64( MCA_1_WDF_FIR                                           , RULL(0x07010A41), SH_UNT_MCA_1_WDF, SH_ACS_SCOM1_AND );
+REG64( MCA_2_FIR                                               , RULL(0x07010A80), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_FIR_OR                                            , RULL(0x07010A82), SH_UNT_MCA_2    , SH_ACS_SCOM2_OR  );
+REG64( MCA_2_WDF_FIR                                           , RULL(0x07010A81), SH_UNT_MCA_2_WDF, SH_ACS_SCOM1_AND );
+REG64( MCA_3_FIR                                               , RULL(0x07010AC0), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_FIR_OR                                            , RULL(0x07010AC2), SH_UNT_MCA_3    , SH_ACS_SCOM2_OR  );
+REG64( MCA_3_WDF_FIR                                           , RULL(0x07010AC1), SH_UNT_MCA_3_WDF, SH_ACS_SCOM1_AND );
+REG64( MCA_4_WDF_FIR                                           , RULL(0x08010A01), SH_UNT_MCA_4_WDF, SH_ACS_SCOM1_AND );
+REG64( MCA_4_FIR                                               , RULL(0x08010A00), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_FIR_OR                                            , RULL(0x08010A02), SH_UNT_MCA_4    , SH_ACS_SCOM2_OR  );
+REG64( MCA_5_FIR                                               , RULL(0x08010A40), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_FIR_OR                                            , RULL(0x08010A42), SH_UNT_MCA_5    , SH_ACS_SCOM2_OR  );
+REG64( MCA_5_WDF_FIR                                           , RULL(0x08010A41), SH_UNT_MCA_5_WDF, SH_ACS_SCOM1_AND );
+REG64( MCA_6_WDF_FIR                                           , RULL(0x08010A81), SH_UNT_MCA_6_WDF, SH_ACS_SCOM1_AND );
+REG64( MCA_6_FIR                                               , RULL(0x08010A80), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_FIR_OR                                            , RULL(0x08010A82), SH_UNT_MCA_6    , SH_ACS_SCOM2_OR  );
+REG64( MCA_7_WDF_FIR                                           , RULL(0x08010AC1), SH_UNT_MCA_7_WDF, SH_ACS_SCOM1_AND );
+REG64( MCA_7_FIR                                               , RULL(0x08010AC0), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_FIR_OR                                            , RULL(0x08010AC2), SH_UNT_MCA_7    , SH_ACS_SCOM2_OR  );
+REG64( MCA_WDF_FIR                                             , RULL(0x07010A01), SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND );
+
+REG64( MCA_FWMS0                                               , RULL(0x07010A18), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_FWMS0                                             , RULL(0x07010A18), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_FWMS0                                             , RULL(0x07010A58), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_FWMS0                                             , RULL(0x07010A98), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_FWMS0                                             , RULL(0x07010AD8), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_FWMS0                                             , RULL(0x08010A18), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_FWMS0                                             , RULL(0x08010A58), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_FWMS0                                             , RULL(0x08010A98), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_FWMS0                                             , RULL(0x08010AD8), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_0_WREITE_FWMS1                                      , RULL(0x07010A19), SH_UNT_MCA_0_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_1_WREITE_FWMS1                                      , RULL(0x07010A59), SH_UNT_MCA_1_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_2_WREITE_FWMS1                                      , RULL(0x07010A99), SH_UNT_MCA_2_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_3_WREITE_FWMS1                                      , RULL(0x07010AD9), SH_UNT_MCA_3_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_4_WREITE_FWMS1                                      , RULL(0x08010A19), SH_UNT_MCA_4_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_5_WREITE_FWMS1                                      , RULL(0x08010A59), SH_UNT_MCA_5_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_6_WREITE_FWMS1                                      , RULL(0x08010A99), SH_UNT_MCA_6_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_7_WREITE_FWMS1                                      , RULL(0x08010AD9), SH_UNT_MCA_7_WREITE,
+       SH_ACS_SCOM_RW   );
+REG64( MCA_WREITE_FWMS1                                        , RULL(0x07010A19), SH_UNT_MCA_WREITE,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCA_FWMS2                                               , RULL(0x07010A1A), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_FWMS2                                             , RULL(0x07010A1A), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_FWMS2                                             , RULL(0x07010A5A), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_FWMS2                                             , RULL(0x07010A9A), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_FWMS2                                             , RULL(0x07010ADA), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_FWMS2                                             , RULL(0x08010A1A), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_FWMS2                                             , RULL(0x08010A5A), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_FWMS2                                             , RULL(0x08010A9A), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_FWMS2                                             , RULL(0x08010ADA), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_FWMS3                                               , RULL(0x07010A1B), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_FWMS3                                             , RULL(0x07010A1B), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_FWMS3                                             , RULL(0x07010A5B), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_FWMS3                                             , RULL(0x07010A9B), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_FWMS3                                             , RULL(0x07010ADB), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_FWMS3                                             , RULL(0x08010A1B), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_FWMS3                                             , RULL(0x08010A5B), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_FWMS3                                             , RULL(0x08010A9B), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_FWMS3                                             , RULL(0x08010ADB), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_FWMS4                                               , RULL(0x07010A1C), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_FWMS4                                             , RULL(0x07010A1C), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_FWMS4                                             , RULL(0x07010A5C), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_FWMS4                                             , RULL(0x07010A9C), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_FWMS4                                             , RULL(0x07010ADC), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_FWMS4                                             , RULL(0x08010A1C), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_FWMS4                                             , RULL(0x08010A5C), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_FWMS4                                             , RULL(0x08010A9C), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_FWMS4                                             , RULL(0x08010ADC), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_FWMS5                                               , RULL(0x07010A1D), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_FWMS5                                             , RULL(0x07010A1D), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_FWMS5                                             , RULL(0x07010A5D), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_FWMS5                                             , RULL(0x07010A9D), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_FWMS5                                             , RULL(0x07010ADD), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_FWMS5                                             , RULL(0x08010A1D), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_FWMS5                                             , RULL(0x08010A5D), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_FWMS5                                             , RULL(0x08010A9D), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_FWMS5                                             , RULL(0x08010ADD), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_FWMS6                                               , RULL(0x07010A1E), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_FWMS6                                             , RULL(0x07010A1E), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_FWMS6                                             , RULL(0x07010A5E), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_FWMS6                                             , RULL(0x07010A9E), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_FWMS6                                             , RULL(0x07010ADE), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_FWMS6                                             , RULL(0x08010A1E), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_FWMS6                                             , RULL(0x08010A5E), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_FWMS6                                             , RULL(0x08010A9E), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_FWMS6                                             , RULL(0x08010ADE), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_FWMS7                                               , RULL(0x07010A1F), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_FWMS7                                             , RULL(0x07010A1F), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_FWMS7                                             , RULL(0x07010A5F), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_FWMS7                                             , RULL(0x07010A9F), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_FWMS7                                             , RULL(0x07010ADF), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_FWMS7                                             , RULL(0x08010A1F), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_FWMS7                                             , RULL(0x08010A5F), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_FWMS7                                             , RULL(0x08010A9F), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_FWMS7                                             , RULL(0x08010ADF), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_HCA_ACCUM_REG                                       , RULL(0x07010A32), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_HCA_ACCUM_REG                                     , RULL(0x07010A32), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_HCA_ACCUM_REG                                     , RULL(0x07010A72), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_HCA_ACCUM_REG                                     , RULL(0x07010AB2), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_HCA_ACCUM_REG                                     , RULL(0x07010AF2), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_HCA_ACCUM_REG                                     , RULL(0x08010A32), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_HCA_ACCUM_REG                                     , RULL(0x08010A72), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_HCA_ACCUM_REG                                     , RULL(0x08010AB2), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_HCA_ACCUM_REG                                     , RULL(0x08010AF2), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_HWMS0                                               , RULL(0x07010A10), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_HWMS0                                             , RULL(0x07010A10), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_HWMS0                                             , RULL(0x07010A50), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_HWMS0                                             , RULL(0x07010A90), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_HWMS0                                             , RULL(0x07010AD0), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_HWMS0                                             , RULL(0x08010A10), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_HWMS0                                             , RULL(0x08010A50), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_HWMS0                                             , RULL(0x08010A90), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_HWMS0                                             , RULL(0x08010AD0), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_0_WDF_HWMS1                                         , RULL(0x07010A11), SH_UNT_MCA_0_WDF, SH_ACS_SCOM_RW   );
+REG64( MCA_1_WDF_HWMS1                                         , RULL(0x07010A51), SH_UNT_MCA_1_WDF, SH_ACS_SCOM_RW   );
+REG64( MCA_2_WDF_HWMS1                                         , RULL(0x07010A91), SH_UNT_MCA_2_WDF, SH_ACS_SCOM_RW   );
+REG64( MCA_3_WDF_HWMS1                                         , RULL(0x07010AD1), SH_UNT_MCA_3_WDF, SH_ACS_SCOM_RW   );
+REG64( MCA_4_WDF_HWMS1                                         , RULL(0x08010A11), SH_UNT_MCA_4_WDF, SH_ACS_SCOM_RW   );
+REG64( MCA_5_WDF_HWMS1                                         , RULL(0x08010A51), SH_UNT_MCA_5_WDF, SH_ACS_SCOM_RW   );
+REG64( MCA_6_WDF_HWMS1                                         , RULL(0x08010A91), SH_UNT_MCA_6_WDF, SH_ACS_SCOM_RW   );
+REG64( MCA_7_WDF_HWMS1                                         , RULL(0x08010AD1), SH_UNT_MCA_7_WDF, SH_ACS_SCOM_RW   );
+REG64( MCA_WDF_HWMS1                                           , RULL(0x07010A11), SH_UNT_MCA_WDF  , SH_ACS_SCOM_RW   );
+
+REG64( MCA_HWMS2                                               , RULL(0x07010A12), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_HWMS2                                             , RULL(0x07010A12), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_HWMS2                                             , RULL(0x07010A52), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_HWMS2                                             , RULL(0x07010A92), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_HWMS2                                             , RULL(0x07010AD2), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_HWMS2                                             , RULL(0x08010A12), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_HWMS2                                             , RULL(0x08010A52), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_HWMS2                                             , RULL(0x08010A92), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_HWMS2                                             , RULL(0x08010AD2), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_HWMS3                                               , RULL(0x07010A13), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_HWMS3                                             , RULL(0x07010A13), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_HWMS3                                             , RULL(0x07010A53), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_HWMS3                                             , RULL(0x07010A93), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_HWMS3                                             , RULL(0x07010AD3), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_HWMS3                                             , RULL(0x08010A13), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_HWMS3                                             , RULL(0x08010A53), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_HWMS3                                             , RULL(0x08010A93), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_HWMS3                                             , RULL(0x08010AD3), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_HWMS4                                               , RULL(0x07010A14), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_HWMS4                                             , RULL(0x07010A14), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_HWMS4                                             , RULL(0x07010A54), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_HWMS4                                             , RULL(0x07010A94), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_HWMS4                                             , RULL(0x07010AD4), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_HWMS4                                             , RULL(0x08010A14), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_HWMS4                                             , RULL(0x08010A54), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_HWMS4                                             , RULL(0x08010A94), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_HWMS4                                             , RULL(0x08010AD4), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_HWMS5                                               , RULL(0x07010A15), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_HWMS5                                             , RULL(0x07010A15), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_HWMS5                                             , RULL(0x07010A55), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_HWMS5                                             , RULL(0x07010A95), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_HWMS5                                             , RULL(0x07010AD5), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_HWMS5                                             , RULL(0x08010A15), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_HWMS5                                             , RULL(0x08010A55), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_HWMS5                                             , RULL(0x08010A95), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_HWMS5                                             , RULL(0x08010AD5), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_HWMS6                                               , RULL(0x07010A16), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_HWMS6                                             , RULL(0x07010A16), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_HWMS6                                             , RULL(0x07010A56), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_HWMS6                                             , RULL(0x07010A96), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_HWMS6                                             , RULL(0x07010AD6), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_HWMS6                                             , RULL(0x08010A16), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_HWMS6                                             , RULL(0x08010A56), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_HWMS6                                             , RULL(0x08010A96), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_HWMS6                                             , RULL(0x08010AD6), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_HWMS7                                               , RULL(0x07010A17), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_HWMS7                                             , RULL(0x07010A17), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_HWMS7                                             , RULL(0x07010A57), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_HWMS7                                             , RULL(0x07010A97), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_HWMS7                                             , RULL(0x07010AD7), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_HWMS7                                             , RULL(0x08010A17), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_HWMS7                                             , RULL(0x08010A57), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_HWMS7                                             , RULL(0x08010A97), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_HWMS7                                             , RULL(0x08010AD7), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MASK                                                , RULL(0x07010A03), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_MASK_AND                                            , RULL(0x07010A04), SH_UNT_MCA      , SH_ACS_SCOM1_AND );
+REG64( MCA_MASK_OR                                             , RULL(0x07010A05), SH_UNT_MCA      , SH_ACS_SCOM2_OR  );
+REG64( MCA_0_MASK                                              , RULL(0x07010A03), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MASK_AND                                          , RULL(0x07010A04), SH_UNT_MCA_0    , SH_ACS_SCOM1_AND );
+REG64( MCA_0_MASK_OR                                           , RULL(0x07010A05), SH_UNT_MCA_0    , SH_ACS_SCOM2_OR  );
+REG64( MCA_1_MASK                                              , RULL(0x07010A43), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MASK_AND                                          , RULL(0x07010A44), SH_UNT_MCA_1    , SH_ACS_SCOM1_AND );
+REG64( MCA_1_MASK_OR                                           , RULL(0x07010A45), SH_UNT_MCA_1    , SH_ACS_SCOM2_OR  );
+REG64( MCA_2_MASK                                              , RULL(0x07010A83), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MASK_AND                                          , RULL(0x07010A84), SH_UNT_MCA_2    , SH_ACS_SCOM1_AND );
+REG64( MCA_2_MASK_OR                                           , RULL(0x07010A85), SH_UNT_MCA_2    , SH_ACS_SCOM2_OR  );
+REG64( MCA_3_MASK                                              , RULL(0x07010AC3), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MASK_AND                                          , RULL(0x07010AC4), SH_UNT_MCA_3    , SH_ACS_SCOM1_AND );
+REG64( MCA_3_MASK_OR                                           , RULL(0x07010AC5), SH_UNT_MCA_3    , SH_ACS_SCOM2_OR  );
+REG64( MCA_4_MASK                                              , RULL(0x08010A03), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MASK_AND                                          , RULL(0x08010A04), SH_UNT_MCA_4    , SH_ACS_SCOM1_AND );
+REG64( MCA_4_MASK_OR                                           , RULL(0x08010A05), SH_UNT_MCA_4    , SH_ACS_SCOM2_OR  );
+REG64( MCA_5_MASK                                              , RULL(0x08010A43), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MASK_AND                                          , RULL(0x08010A44), SH_UNT_MCA_5    , SH_ACS_SCOM1_AND );
+REG64( MCA_5_MASK_OR                                           , RULL(0x08010A45), SH_UNT_MCA_5    , SH_ACS_SCOM2_OR  );
+REG64( MCA_6_MASK                                              , RULL(0x08010A83), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MASK_AND                                          , RULL(0x08010A84), SH_UNT_MCA_6    , SH_ACS_SCOM1_AND );
+REG64( MCA_6_MASK_OR                                           , RULL(0x08010A85), SH_UNT_MCA_6    , SH_ACS_SCOM2_OR  );
+REG64( MCA_7_MASK                                              , RULL(0x08010AC3), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MASK_AND                                          , RULL(0x08010AC4), SH_UNT_MCA_7    , SH_ACS_SCOM1_AND );
+REG64( MCA_7_MASK_OR                                           , RULL(0x08010AC5), SH_UNT_MCA_7    , SH_ACS_SCOM2_OR  );
+
+REG64( MCA_MBACALFIRQ                                          , RULL(0x07010900), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_MBACALFIRQ_AND                                      , RULL(0x07010901), SH_UNT_MCA      , SH_ACS_SCOM1_AND );
+REG64( MCA_MBACALFIRQ_OR                                       , RULL(0x07010902), SH_UNT_MCA      , SH_ACS_SCOM2_OR  );
+REG64( MCA_0_MBACALFIRQ                                        , RULL(0x07010900), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBACALFIRQ_AND                                    , RULL(0x07010901), SH_UNT_MCA_0    , SH_ACS_SCOM1_AND );
+REG64( MCA_0_MBACALFIRQ_OR                                     , RULL(0x07010902), SH_UNT_MCA_0    , SH_ACS_SCOM2_OR  );
+REG64( MCA_1_MBACALFIRQ                                        , RULL(0x07010940), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBACALFIRQ_AND                                    , RULL(0x07010941), SH_UNT_MCA_1    , SH_ACS_SCOM1_AND );
+REG64( MCA_1_MBACALFIRQ_OR                                     , RULL(0x07010942), SH_UNT_MCA_1    , SH_ACS_SCOM2_OR  );
+REG64( MCA_2_MBACALFIRQ                                        , RULL(0x07010980), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBACALFIRQ_AND                                    , RULL(0x07010981), SH_UNT_MCA_2    , SH_ACS_SCOM1_AND );
+REG64( MCA_2_MBACALFIRQ_OR                                     , RULL(0x07010982), SH_UNT_MCA_2    , SH_ACS_SCOM2_OR  );
+REG64( MCA_3_MBACALFIRQ                                        , RULL(0x070109C0), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBACALFIRQ_AND                                    , RULL(0x070109C1), SH_UNT_MCA_3    , SH_ACS_SCOM1_AND );
+REG64( MCA_3_MBACALFIRQ_OR                                     , RULL(0x070109C2), SH_UNT_MCA_3    , SH_ACS_SCOM2_OR  );
+REG64( MCA_4_MBACALFIRQ                                        , RULL(0x08010900), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBACALFIRQ_AND                                    , RULL(0x08010901), SH_UNT_MCA_4    , SH_ACS_SCOM1_AND );
+REG64( MCA_4_MBACALFIRQ_OR                                     , RULL(0x08010902), SH_UNT_MCA_4    , SH_ACS_SCOM2_OR  );
+REG64( MCA_5_MBACALFIRQ                                        , RULL(0x08010940), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBACALFIRQ_AND                                    , RULL(0x08010941), SH_UNT_MCA_5    , SH_ACS_SCOM1_AND );
+REG64( MCA_5_MBACALFIRQ_OR                                     , RULL(0x08010942), SH_UNT_MCA_5    , SH_ACS_SCOM2_OR  );
+REG64( MCA_6_MBACALFIRQ                                        , RULL(0x08010980), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBACALFIRQ_AND                                    , RULL(0x08010981), SH_UNT_MCA_6    , SH_ACS_SCOM1_AND );
+REG64( MCA_6_MBACALFIRQ_OR                                     , RULL(0x08010982), SH_UNT_MCA_6    , SH_ACS_SCOM2_OR  );
+REG64( MCA_7_MBACALFIRQ                                        , RULL(0x080109C0), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBACALFIRQ_AND                                    , RULL(0x080109C1), SH_UNT_MCA_7    , SH_ACS_SCOM1_AND );
+REG64( MCA_7_MBACALFIRQ_OR                                     , RULL(0x080109C2), SH_UNT_MCA_7    , SH_ACS_SCOM2_OR  );
+
+REG64( MCA_MBACALFIR_ACTION0                                   , RULL(0x07010906), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBACALFIR_ACTION0                                 , RULL(0x07010906), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBACALFIR_ACTION0                                 , RULL(0x07010946), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBACALFIR_ACTION0                                 , RULL(0x07010986), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBACALFIR_ACTION0                                 , RULL(0x070109C6), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBACALFIR_ACTION0                                 , RULL(0x08010906), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBACALFIR_ACTION0                                 , RULL(0x08010946), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBACALFIR_ACTION0                                 , RULL(0x08010986), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBACALFIR_ACTION0                                 , RULL(0x080109C6), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBACALFIR_ACTION1                                   , RULL(0x07010907), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBACALFIR_ACTION1                                 , RULL(0x07010907), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBACALFIR_ACTION1                                 , RULL(0x07010947), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBACALFIR_ACTION1                                 , RULL(0x07010987), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBACALFIR_ACTION1                                 , RULL(0x070109C7), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBACALFIR_ACTION1                                 , RULL(0x08010907), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBACALFIR_ACTION1                                 , RULL(0x08010947), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBACALFIR_ACTION1                                 , RULL(0x08010987), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBACALFIR_ACTION1                                 , RULL(0x080109C7), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBACALFIR_MASK                                      , RULL(0x07010903), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_MBACALFIR_MASK_AND                                  , RULL(0x07010904), SH_UNT_MCA      , SH_ACS_SCOM1_AND );
+REG64( MCA_MBACALFIR_MASK_OR                                   , RULL(0x07010905), SH_UNT_MCA      , SH_ACS_SCOM2_OR  );
+REG64( MCA_0_MBACALFIR_MASK                                    , RULL(0x07010903), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBACALFIR_MASK_AND                                , RULL(0x07010904), SH_UNT_MCA_0    , SH_ACS_SCOM1_AND );
+REG64( MCA_0_MBACALFIR_MASK_OR                                 , RULL(0x07010905), SH_UNT_MCA_0    , SH_ACS_SCOM2_OR  );
+REG64( MCA_1_MBACALFIR_MASK                                    , RULL(0x07010943), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBACALFIR_MASK_AND                                , RULL(0x07010944), SH_UNT_MCA_1    , SH_ACS_SCOM1_AND );
+REG64( MCA_1_MBACALFIR_MASK_OR                                 , RULL(0x07010945), SH_UNT_MCA_1    , SH_ACS_SCOM2_OR  );
+REG64( MCA_2_MBACALFIR_MASK                                    , RULL(0x07010983), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBACALFIR_MASK_AND                                , RULL(0x07010984), SH_UNT_MCA_2    , SH_ACS_SCOM1_AND );
+REG64( MCA_2_MBACALFIR_MASK_OR                                 , RULL(0x07010985), SH_UNT_MCA_2    , SH_ACS_SCOM2_OR  );
+REG64( MCA_3_MBACALFIR_MASK                                    , RULL(0x070109C3), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBACALFIR_MASK_AND                                , RULL(0x070109C4), SH_UNT_MCA_3    , SH_ACS_SCOM1_AND );
+REG64( MCA_3_MBACALFIR_MASK_OR                                 , RULL(0x070109C5), SH_UNT_MCA_3    , SH_ACS_SCOM2_OR  );
+REG64( MCA_4_MBACALFIR_MASK                                    , RULL(0x08010903), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBACALFIR_MASK_AND                                , RULL(0x08010904), SH_UNT_MCA_4    , SH_ACS_SCOM1_AND );
+REG64( MCA_4_MBACALFIR_MASK_OR                                 , RULL(0x08010905), SH_UNT_MCA_4    , SH_ACS_SCOM2_OR  );
+REG64( MCA_5_MBACALFIR_MASK                                    , RULL(0x08010943), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBACALFIR_MASK_AND                                , RULL(0x08010944), SH_UNT_MCA_5    , SH_ACS_SCOM1_AND );
+REG64( MCA_5_MBACALFIR_MASK_OR                                 , RULL(0x08010945), SH_UNT_MCA_5    , SH_ACS_SCOM2_OR  );
+REG64( MCA_6_MBACALFIR_MASK                                    , RULL(0x08010983), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBACALFIR_MASK_AND                                , RULL(0x08010984), SH_UNT_MCA_6    , SH_ACS_SCOM1_AND );
+REG64( MCA_6_MBACALFIR_MASK_OR                                 , RULL(0x08010985), SH_UNT_MCA_6    , SH_ACS_SCOM2_OR  );
+REG64( MCA_7_MBACALFIR_MASK                                    , RULL(0x080109C3), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBACALFIR_MASK_AND                                , RULL(0x080109C4), SH_UNT_MCA_7    , SH_ACS_SCOM1_AND );
+REG64( MCA_7_MBACALFIR_MASK_OR                                 , RULL(0x080109C5), SH_UNT_MCA_7    , SH_ACS_SCOM2_OR  );
+
+REG64( MCA_MBAREF0Q                                            , RULL(0x07010932), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBAREF0Q                                          , RULL(0x07010932), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBAREF0Q                                          , RULL(0x07010972), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBAREF0Q                                          , RULL(0x070109B2), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBAREF0Q                                          , RULL(0x070109F2), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBAREF0Q                                          , RULL(0x08010932), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBAREF0Q                                          , RULL(0x08010972), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBAREF0Q                                          , RULL(0x080109B2), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBAREF0Q                                          , RULL(0x080109F2), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBAREFAQ                                            , RULL(0x07010936), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBAREFAQ                                          , RULL(0x07010936), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBAREFAQ                                          , RULL(0x07010976), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBAREFAQ                                          , RULL(0x070109B6), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBAREFAQ                                          , RULL(0x070109F6), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBAREFAQ                                          , RULL(0x08010936), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBAREFAQ                                          , RULL(0x08010976), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBAREFAQ                                          , RULL(0x080109B6), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBAREFAQ                                          , RULL(0x080109F6), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBARPC0Q                                            , RULL(0x07010934), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBARPC0Q                                          , RULL(0x07010934), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBARPC0Q                                          , RULL(0x07010974), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBARPC0Q                                          , RULL(0x070109B4), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBARPC0Q                                          , RULL(0x070109F4), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBARPC0Q                                          , RULL(0x08010934), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBARPC0Q                                          , RULL(0x08010974), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBARPC0Q                                          , RULL(0x080109B4), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBARPC0Q                                          , RULL(0x080109F4), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBASTR0Q                                            , RULL(0x07010935), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBASTR0Q                                          , RULL(0x07010935), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBASTR0Q                                          , RULL(0x07010975), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBASTR0Q                                          , RULL(0x070109B5), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBASTR0Q                                          , RULL(0x070109F5), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBASTR0Q                                          , RULL(0x08010935), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBASTR0Q                                          , RULL(0x08010975), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBASTR0Q                                          , RULL(0x080109B5), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBASTR0Q                                          , RULL(0x080109F5), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBAUER0Q                                         , RULL(0x0701236E), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBAUER0Q                                       , RULL(0x0701236E), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBAUER0Q                                       , RULL(0x0801236E), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBAUER1Q                                         , RULL(0x07012373), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBAUER1Q                                       , RULL(0x07012373), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBAUER1Q                                       , RULL(0x08012373), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBAUER2Q                                         , RULL(0x07012378), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBAUER2Q                                       , RULL(0x07012378), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBAUER2Q                                       , RULL(0x08012378), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBAUER3Q                                         , RULL(0x0701237D), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBAUER3Q                                       , RULL(0x0701237D), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBAUER3Q                                       , RULL(0x0801237D), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_CAL0Q                                           , RULL(0x0701090F), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_CAL0Q                                         , RULL(0x0701090F), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_CAL0Q                                         , RULL(0x0701094F), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_CAL0Q                                         , RULL(0x0701098F), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_CAL0Q                                         , RULL(0x070109CF), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_CAL0Q                                         , RULL(0x0801090F), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_CAL0Q                                         , RULL(0x0801094F), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_CAL0Q                                         , RULL(0x0801098F), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_CAL0Q                                         , RULL(0x080109CF), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_CAL1Q                                           , RULL(0x07010910), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_CAL1Q                                         , RULL(0x07010910), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_CAL1Q                                         , RULL(0x07010950), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_CAL1Q                                         , RULL(0x07010990), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_CAL1Q                                         , RULL(0x070109D0), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_CAL1Q                                         , RULL(0x08010910), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_CAL1Q                                         , RULL(0x08010950), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_CAL1Q                                         , RULL(0x08010990), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_CAL1Q                                         , RULL(0x080109D0), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_CAL2Q                                           , RULL(0x07010911), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_CAL2Q                                         , RULL(0x07010911), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_CAL2Q                                         , RULL(0x07010951), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_CAL2Q                                         , RULL(0x07010991), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_CAL2Q                                         , RULL(0x070109D1), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_CAL2Q                                         , RULL(0x08010911), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_CAL2Q                                         , RULL(0x08010951), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_CAL2Q                                         , RULL(0x08010991), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_CAL2Q                                         , RULL(0x080109D1), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_CAL3Q                                           , RULL(0x07010912), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_CAL3Q                                         , RULL(0x07010912), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_CAL3Q                                         , RULL(0x07010952), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_CAL3Q                                         , RULL(0x07010992), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_CAL3Q                                         , RULL(0x070109D2), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_CAL3Q                                         , RULL(0x08010912), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_CAL3Q                                         , RULL(0x08010952), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_CAL3Q                                         , RULL(0x08010992), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_CAL3Q                                         , RULL(0x080109D2), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_DBG0Q                                           , RULL(0x07010926), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_DBG0Q                                         , RULL(0x07010926), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_DBG0Q                                         , RULL(0x07010966), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_DBG0Q                                         , RULL(0x070109A6), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_DBG0Q                                         , RULL(0x070109E6), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_DBG0Q                                         , RULL(0x08010926), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_DBG0Q                                         , RULL(0x08010966), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_DBG0Q                                         , RULL(0x080109A6), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_DBG0Q                                         , RULL(0x080109E6), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_DBG1Q                                           , RULL(0x07010927), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_DBG1Q                                         , RULL(0x07010927), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_DBG1Q                                         , RULL(0x07010967), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_DBG1Q                                         , RULL(0x070109A7), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_DBG1Q                                         , RULL(0x070109E7), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_DBG1Q                                         , RULL(0x08010927), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_DBG1Q                                         , RULL(0x08010967), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_DBG1Q                                         , RULL(0x080109A7), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_DBG1Q                                         , RULL(0x080109E7), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_DSM0Q                                           , RULL(0x0701090A), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_DSM0Q                                         , RULL(0x0701090A), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_DSM0Q                                         , RULL(0x0701094A), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_DSM0Q                                         , RULL(0x0701098A), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_DSM0Q                                         , RULL(0x070109CA), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_DSM0Q                                         , RULL(0x0801090A), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_DSM0Q                                         , RULL(0x0801094A), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_DSM0Q                                         , RULL(0x0801098A), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_DSM0Q                                         , RULL(0x080109CA), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_ERR_REPORTQ                                     , RULL(0x0701091A), SH_UNT_MCA      , SH_ACS_SCOM_RO   );
+REG64( MCA_0_MBA_ERR_REPORTQ                                   , RULL(0x0701091A), SH_UNT_MCA_0    , SH_ACS_SCOM_RO   );
+REG64( MCA_1_MBA_ERR_REPORTQ                                   , RULL(0x0701095A), SH_UNT_MCA_1    , SH_ACS_SCOM_RO   );
+REG64( MCA_2_MBA_ERR_REPORTQ                                   , RULL(0x0701099A), SH_UNT_MCA_2    , SH_ACS_SCOM_RO   );
+REG64( MCA_3_MBA_ERR_REPORTQ                                   , RULL(0x070109DA), SH_UNT_MCA_3    , SH_ACS_SCOM_RO   );
+REG64( MCA_4_MBA_ERR_REPORTQ                                   , RULL(0x0801091A), SH_UNT_MCA_4    , SH_ACS_SCOM_RO   );
+REG64( MCA_5_MBA_ERR_REPORTQ                                   , RULL(0x0801095A), SH_UNT_MCA_5    , SH_ACS_SCOM_RO   );
+REG64( MCA_6_MBA_ERR_REPORTQ                                   , RULL(0x0801099A), SH_UNT_MCA_6    , SH_ACS_SCOM_RO   );
+REG64( MCA_7_MBA_ERR_REPORTQ                                   , RULL(0x080109DA), SH_UNT_MCA_7    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_MBA_FARB0Q                                          , RULL(0x07010913), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_FARB0Q                                        , RULL(0x07010913), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_FARB0Q                                        , RULL(0x07010953), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_FARB0Q                                        , RULL(0x07010993), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_FARB0Q                                        , RULL(0x070109D3), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_FARB0Q                                        , RULL(0x08010913), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_FARB0Q                                        , RULL(0x08010953), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_FARB0Q                                        , RULL(0x08010993), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_FARB0Q                                        , RULL(0x080109D3), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_FARB1Q                                          , RULL(0x07010914), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_FARB1Q                                        , RULL(0x07010914), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_FARB1Q                                        , RULL(0x07010954), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_FARB1Q                                        , RULL(0x07010994), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_FARB1Q                                        , RULL(0x070109D4), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_FARB1Q                                        , RULL(0x08010914), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_FARB1Q                                        , RULL(0x08010954), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_FARB1Q                                        , RULL(0x08010994), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_FARB1Q                                        , RULL(0x080109D4), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_FARB2Q                                          , RULL(0x07010915), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_FARB2Q                                        , RULL(0x07010915), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_FARB2Q                                        , RULL(0x07010955), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_FARB2Q                                        , RULL(0x07010995), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_FARB2Q                                        , RULL(0x070109D5), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_FARB2Q                                        , RULL(0x08010915), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_FARB2Q                                        , RULL(0x08010955), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_FARB2Q                                        , RULL(0x08010995), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_FARB2Q                                        , RULL(0x080109D5), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_FARB3Q                                          , RULL(0x07010916), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_FARB3Q                                        , RULL(0x07010916), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_FARB3Q                                        , RULL(0x07010956), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_FARB3Q                                        , RULL(0x07010996), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_FARB3Q                                        , RULL(0x070109D6), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_FARB3Q                                        , RULL(0x08010916), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_FARB3Q                                        , RULL(0x08010956), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_FARB3Q                                        , RULL(0x08010996), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_FARB3Q                                        , RULL(0x080109D6), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_FARB4Q                                          , RULL(0x07010917), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_FARB4Q                                        , RULL(0x07010917), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_FARB4Q                                        , RULL(0x07010957), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_FARB4Q                                        , RULL(0x07010997), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_FARB4Q                                        , RULL(0x070109D7), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_FARB4Q                                        , RULL(0x08010917), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_FARB4Q                                        , RULL(0x08010957), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_FARB4Q                                        , RULL(0x08010997), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_FARB4Q                                        , RULL(0x080109D7), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_FARB5Q                                          , RULL(0x07010918), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_FARB5Q                                        , RULL(0x07010918), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_FARB5Q                                        , RULL(0x07010958), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_FARB5Q                                        , RULL(0x07010998), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_FARB5Q                                        , RULL(0x070109D8), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_FARB5Q                                        , RULL(0x08010918), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_FARB5Q                                        , RULL(0x08010958), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_FARB5Q                                        , RULL(0x08010998), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_FARB5Q                                        , RULL(0x080109D8), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_FARB6Q                                          , RULL(0x07010919), SH_UNT_MCA      , SH_ACS_SCOM_RO   );
+REG64( MCA_0_MBA_FARB6Q                                        , RULL(0x07010919), SH_UNT_MCA_0    , SH_ACS_SCOM_RO   );
+REG64( MCA_1_MBA_FARB6Q                                        , RULL(0x07010959), SH_UNT_MCA_1    , SH_ACS_SCOM_RO   );
+REG64( MCA_2_MBA_FARB6Q                                        , RULL(0x07010999), SH_UNT_MCA_2    , SH_ACS_SCOM_RO   );
+REG64( MCA_3_MBA_FARB6Q                                        , RULL(0x070109D9), SH_UNT_MCA_3    , SH_ACS_SCOM_RO   );
+REG64( MCA_4_MBA_FARB6Q                                        , RULL(0x08010919), SH_UNT_MCA_4    , SH_ACS_SCOM_RO   );
+REG64( MCA_5_MBA_FARB6Q                                        , RULL(0x08010959), SH_UNT_MCA_5    , SH_ACS_SCOM_RO   );
+REG64( MCA_6_MBA_FARB6Q                                        , RULL(0x08010999), SH_UNT_MCA_6    , SH_ACS_SCOM_RO   );
+REG64( MCA_7_MBA_FARB6Q                                        , RULL(0x080109D9), SH_UNT_MCA_7    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_MBA_FARB7Q                                          , RULL(0x07010925), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_FARB7Q                                        , RULL(0x07010925), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_FARB7Q                                        , RULL(0x07010965), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_FARB7Q                                        , RULL(0x070109A5), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_FARB7Q                                        , RULL(0x070109E5), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_FARB7Q                                        , RULL(0x08010925), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_FARB7Q                                        , RULL(0x08010965), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_FARB7Q                                        , RULL(0x080109A5), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_FARB7Q                                        , RULL(0x080109E5), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_FARB8Q                                          , RULL(0x07010928), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_FARB8Q                                        , RULL(0x07010928), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_FARB8Q                                        , RULL(0x07010968), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_FARB8Q                                        , RULL(0x070109A8), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_FARB8Q                                        , RULL(0x070109E8), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_FARB8Q                                        , RULL(0x08010928), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_FARB8Q                                        , RULL(0x08010968), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_FARB8Q                                        , RULL(0x080109A8), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_FARB8Q                                        , RULL(0x080109E8), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBA_MCBERRPTQ                                    , RULL(0x070123E7), SH_UNT_MCBIST   , SH_ACS_SCOM_RO   );
+REG64( MCBIST_0_MBA_MCBERRPTQ                                  , RULL(0x070123E7), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RO   );
+REG64( MCBIST_1_MBA_MCBERRPTQ                                  , RULL(0x080123E7), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RO   );
+
+REG64( MCA_MBA_PMU0Q                                           , RULL(0x07010937), SH_UNT_MCA      , SH_ACS_SCOM_RO   );
+REG64( MCA_0_MBA_PMU0Q                                         , RULL(0x07010937), SH_UNT_MCA_0    , SH_ACS_SCOM_RO   );
+REG64( MCA_1_MBA_PMU0Q                                         , RULL(0x07010977), SH_UNT_MCA_1    , SH_ACS_SCOM_RO   );
+REG64( MCA_2_MBA_PMU0Q                                         , RULL(0x070109B7), SH_UNT_MCA_2    , SH_ACS_SCOM_RO   );
+REG64( MCA_3_MBA_PMU0Q                                         , RULL(0x070109F7), SH_UNT_MCA_3    , SH_ACS_SCOM_RO   );
+REG64( MCA_4_MBA_PMU0Q                                         , RULL(0x08010937), SH_UNT_MCA_4    , SH_ACS_SCOM_RO   );
+REG64( MCA_5_MBA_PMU0Q                                         , RULL(0x08010977), SH_UNT_MCA_5    , SH_ACS_SCOM_RO   );
+REG64( MCA_6_MBA_PMU0Q                                         , RULL(0x080109B7), SH_UNT_MCA_6    , SH_ACS_SCOM_RO   );
+REG64( MCA_7_MBA_PMU0Q                                         , RULL(0x080109F7), SH_UNT_MCA_7    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_MBA_PMU1Q                                           , RULL(0x07010938), SH_UNT_MCA      , SH_ACS_SCOM_RO   );
+REG64( MCA_0_MBA_PMU1Q                                         , RULL(0x07010938), SH_UNT_MCA_0    , SH_ACS_SCOM_RO   );
+REG64( MCA_1_MBA_PMU1Q                                         , RULL(0x07010978), SH_UNT_MCA_1    , SH_ACS_SCOM_RO   );
+REG64( MCA_2_MBA_PMU1Q                                         , RULL(0x070109B8), SH_UNT_MCA_2    , SH_ACS_SCOM_RO   );
+REG64( MCA_3_MBA_PMU1Q                                         , RULL(0x070109F8), SH_UNT_MCA_3    , SH_ACS_SCOM_RO   );
+REG64( MCA_4_MBA_PMU1Q                                         , RULL(0x08010938), SH_UNT_MCA_4    , SH_ACS_SCOM_RO   );
+REG64( MCA_5_MBA_PMU1Q                                         , RULL(0x08010978), SH_UNT_MCA_5    , SH_ACS_SCOM_RO   );
+REG64( MCA_6_MBA_PMU1Q                                         , RULL(0x080109B8), SH_UNT_MCA_6    , SH_ACS_SCOM_RO   );
+REG64( MCA_7_MBA_PMU1Q                                         , RULL(0x080109F8), SH_UNT_MCA_7    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_MBA_PMU2Q                                           , RULL(0x07010939), SH_UNT_MCA      , SH_ACS_SCOM_RO   );
+REG64( MCA_0_MBA_PMU2Q                                         , RULL(0x07010939), SH_UNT_MCA_0    , SH_ACS_SCOM_RO   );
+REG64( MCA_1_MBA_PMU2Q                                         , RULL(0x07010979), SH_UNT_MCA_1    , SH_ACS_SCOM_RO   );
+REG64( MCA_2_MBA_PMU2Q                                         , RULL(0x070109B9), SH_UNT_MCA_2    , SH_ACS_SCOM_RO   );
+REG64( MCA_3_MBA_PMU2Q                                         , RULL(0x070109F9), SH_UNT_MCA_3    , SH_ACS_SCOM_RO   );
+REG64( MCA_4_MBA_PMU2Q                                         , RULL(0x08010939), SH_UNT_MCA_4    , SH_ACS_SCOM_RO   );
+REG64( MCA_5_MBA_PMU2Q                                         , RULL(0x08010979), SH_UNT_MCA_5    , SH_ACS_SCOM_RO   );
+REG64( MCA_6_MBA_PMU2Q                                         , RULL(0x080109B9), SH_UNT_MCA_6    , SH_ACS_SCOM_RO   );
+REG64( MCA_7_MBA_PMU2Q                                         , RULL(0x080109F9), SH_UNT_MCA_7    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_MBA_PMU3Q                                           , RULL(0x0701093A), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_PMU3Q                                         , RULL(0x0701093A), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_PMU3Q                                         , RULL(0x0701097A), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_PMU3Q                                         , RULL(0x070109BA), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_PMU3Q                                         , RULL(0x070109FA), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_PMU3Q                                         , RULL(0x0801093A), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_PMU3Q                                         , RULL(0x0801097A), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_PMU3Q                                         , RULL(0x080109BA), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_PMU3Q                                         , RULL(0x080109FA), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_PMU4Q                                           , RULL(0x0701093B), SH_UNT_MCA      , SH_ACS_SCOM_RO   );
+REG64( MCA_0_MBA_PMU4Q                                         , RULL(0x0701093B), SH_UNT_MCA_0    , SH_ACS_SCOM_RO   );
+REG64( MCA_1_MBA_PMU4Q                                         , RULL(0x0701097B), SH_UNT_MCA_1    , SH_ACS_SCOM_RO   );
+REG64( MCA_2_MBA_PMU4Q                                         , RULL(0x070109BB), SH_UNT_MCA_2    , SH_ACS_SCOM_RO   );
+REG64( MCA_3_MBA_PMU4Q                                         , RULL(0x070109FB), SH_UNT_MCA_3    , SH_ACS_SCOM_RO   );
+REG64( MCA_4_MBA_PMU4Q                                         , RULL(0x0801093B), SH_UNT_MCA_4    , SH_ACS_SCOM_RO   );
+REG64( MCA_5_MBA_PMU4Q                                         , RULL(0x0801097B), SH_UNT_MCA_5    , SH_ACS_SCOM_RO   );
+REG64( MCA_6_MBA_PMU4Q                                         , RULL(0x080109BB), SH_UNT_MCA_6    , SH_ACS_SCOM_RO   );
+REG64( MCA_7_MBA_PMU4Q                                         , RULL(0x080109FB), SH_UNT_MCA_7    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_MBA_PMU5Q                                           , RULL(0x0701093C), SH_UNT_MCA      , SH_ACS_SCOM_RO   );
+REG64( MCA_0_MBA_PMU5Q                                         , RULL(0x0701093C), SH_UNT_MCA_0    , SH_ACS_SCOM_RO   );
+REG64( MCA_1_MBA_PMU5Q                                         , RULL(0x0701097C), SH_UNT_MCA_1    , SH_ACS_SCOM_RO   );
+REG64( MCA_2_MBA_PMU5Q                                         , RULL(0x070109BC), SH_UNT_MCA_2    , SH_ACS_SCOM_RO   );
+REG64( MCA_3_MBA_PMU5Q                                         , RULL(0x070109FC), SH_UNT_MCA_3    , SH_ACS_SCOM_RO   );
+REG64( MCA_4_MBA_PMU5Q                                         , RULL(0x0801093C), SH_UNT_MCA_4    , SH_ACS_SCOM_RO   );
+REG64( MCA_5_MBA_PMU5Q                                         , RULL(0x0801097C), SH_UNT_MCA_5    , SH_ACS_SCOM_RO   );
+REG64( MCA_6_MBA_PMU5Q                                         , RULL(0x080109BC), SH_UNT_MCA_6    , SH_ACS_SCOM_RO   );
+REG64( MCA_7_MBA_PMU5Q                                         , RULL(0x080109FC), SH_UNT_MCA_7    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_MBA_PMU6Q                                           , RULL(0x0701093D), SH_UNT_MCA      , SH_ACS_SCOM_RO   );
+REG64( MCA_0_MBA_PMU6Q                                         , RULL(0x0701093D), SH_UNT_MCA_0    , SH_ACS_SCOM_RO   );
+REG64( MCA_1_MBA_PMU6Q                                         , RULL(0x0701097D), SH_UNT_MCA_1    , SH_ACS_SCOM_RO   );
+REG64( MCA_2_MBA_PMU6Q                                         , RULL(0x070109BD), SH_UNT_MCA_2    , SH_ACS_SCOM_RO   );
+REG64( MCA_3_MBA_PMU6Q                                         , RULL(0x070109FD), SH_UNT_MCA_3    , SH_ACS_SCOM_RO   );
+REG64( MCA_4_MBA_PMU6Q                                         , RULL(0x0801093D), SH_UNT_MCA_4    , SH_ACS_SCOM_RO   );
+REG64( MCA_5_MBA_PMU6Q                                         , RULL(0x0801097D), SH_UNT_MCA_5    , SH_ACS_SCOM_RO   );
+REG64( MCA_6_MBA_PMU6Q                                         , RULL(0x080109BD), SH_UNT_MCA_6    , SH_ACS_SCOM_RO   );
+REG64( MCA_7_MBA_PMU6Q                                         , RULL(0x080109FD), SH_UNT_MCA_7    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_MBA_PMU7Q                                           , RULL(0x0701093E), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_PMU7Q                                         , RULL(0x0701093E), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_PMU7Q                                         , RULL(0x0701097E), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_PMU7Q                                         , RULL(0x070109BE), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_PMU7Q                                         , RULL(0x070109FE), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_PMU7Q                                         , RULL(0x0801093E), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_PMU7Q                                         , RULL(0x0801097E), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_PMU7Q                                         , RULL(0x080109BE), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_PMU7Q                                         , RULL(0x080109FE), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_PMU8Q                                           , RULL(0x0701093F), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_PMU8Q                                         , RULL(0x0701093F), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_PMU8Q                                         , RULL(0x0701097F), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_PMU8Q                                         , RULL(0x070109BF), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_PMU8Q                                         , RULL(0x070109FF), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_PMU8Q                                         , RULL(0x0801093F), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_PMU8Q                                         , RULL(0x0801097F), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_PMU8Q                                         , RULL(0x080109BF), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_PMU8Q                                         , RULL(0x080109FF), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_RRQ0Q                                           , RULL(0x0701090E), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_RRQ0Q                                         , RULL(0x0701090E), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_RRQ0Q                                         , RULL(0x0701094E), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_RRQ0Q                                         , RULL(0x0701098E), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_RRQ0Q                                         , RULL(0x070109CE), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_RRQ0Q                                         , RULL(0x0801090E), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_RRQ0Q                                         , RULL(0x0801094E), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_RRQ0Q                                         , RULL(0x0801098E), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_RRQ0Q                                         , RULL(0x080109CE), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_TMR0Q                                           , RULL(0x0701090B), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_TMR0Q                                         , RULL(0x0701090B), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_TMR0Q                                         , RULL(0x0701094B), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_TMR0Q                                         , RULL(0x0701098B), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_TMR0Q                                         , RULL(0x070109CB), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_TMR0Q                                         , RULL(0x0801090B), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_TMR0Q                                         , RULL(0x0801094B), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_TMR0Q                                         , RULL(0x0801098B), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_TMR0Q                                         , RULL(0x080109CB), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_TMR1Q                                           , RULL(0x0701090C), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_TMR1Q                                         , RULL(0x0701090C), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_TMR1Q                                         , RULL(0x0701094C), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_TMR1Q                                         , RULL(0x0701098C), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_TMR1Q                                         , RULL(0x070109CC), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_TMR1Q                                         , RULL(0x0801090C), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_TMR1Q                                         , RULL(0x0801094C), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_TMR1Q                                         , RULL(0x0801098C), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_TMR1Q                                         , RULL(0x080109CC), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_TMR2Q                                           , RULL(0x0701092F), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_TMR2Q                                         , RULL(0x0701092F), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_TMR2Q                                         , RULL(0x0701096F), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_TMR2Q                                         , RULL(0x070109AF), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_TMR2Q                                         , RULL(0x070109EF), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_TMR2Q                                         , RULL(0x0801092F), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_TMR2Q                                         , RULL(0x0801096F), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_TMR2Q                                         , RULL(0x080109AF), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_TMR2Q                                         , RULL(0x080109EF), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBA_WRQ0Q                                           , RULL(0x0701090D), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBA_WRQ0Q                                         , RULL(0x0701090D), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBA_WRQ0Q                                         , RULL(0x0701094D), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBA_WRQ0Q                                         , RULL(0x0701098D), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBA_WRQ0Q                                         , RULL(0x070109CD), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBA_WRQ0Q                                         , RULL(0x0801090D), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBA_WRQ0Q                                         , RULL(0x0801094D), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBA_WRQ0Q                                         , RULL(0x0801098D), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBA_WRQ0Q                                         , RULL(0x080109CD), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBECTLQ                                          , RULL(0x07012310), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBECTLQ                                        , RULL(0x07012310), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBECTLQ                                        , RULL(0x08012310), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MBMDI                                               , RULL(0x07010A2D), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MBMDI                                             , RULL(0x07010A2D), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MBMDI                                             , RULL(0x07010A6D), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MBMDI                                             , RULL(0x07010AAD), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MBMDI                                             , RULL(0x07010AED), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MBMDI                                             , RULL(0x08010A2D), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MBMDI                                             , RULL(0x08010A6D), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MBMDI                                             , RULL(0x08010AAD), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MBMDI                                             , RULL(0x08010AED), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBMPER0Q                                         , RULL(0x0701236C), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBMPER0Q                                       , RULL(0x0701236C), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBMPER0Q                                       , RULL(0x0801236C), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBMPER1Q                                         , RULL(0x07012371), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBMPER1Q                                       , RULL(0x07012371), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBMPER1Q                                       , RULL(0x08012371), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBMPER2Q                                         , RULL(0x07012376), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBMPER2Q                                       , RULL(0x07012376), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBMPER2Q                                       , RULL(0x08012376), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBMPER3Q                                         , RULL(0x0701237B), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBMPER3Q                                       , RULL(0x0701237B), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBMPER3Q                                       , RULL(0x0801237B), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBNCER0Q                                         , RULL(0x0701236A), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBNCER0Q                                       , RULL(0x0701236A), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBNCER0Q                                       , RULL(0x0801236A), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBNCER1Q                                         , RULL(0x0701236F), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBNCER1Q                                       , RULL(0x0701236F), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBNCER1Q                                       , RULL(0x0801236F), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBNCER2Q                                         , RULL(0x07012374), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBNCER2Q                                       , RULL(0x07012374), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBNCER2Q                                       , RULL(0x08012374), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBNCER3Q                                         , RULL(0x07012379), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBNCER3Q                                       , RULL(0x07012379), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBNCER3Q                                       , RULL(0x08012379), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBRCER0Q                                         , RULL(0x0701236B), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBRCER0Q                                       , RULL(0x0701236B), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBRCER0Q                                       , RULL(0x0801236B), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBRCER1Q                                         , RULL(0x07012370), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBRCER1Q                                       , RULL(0x07012370), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBRCER1Q                                       , RULL(0x08012370), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBRCER2Q                                         , RULL(0x07012375), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBRCER2Q                                       , RULL(0x07012375), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBRCER2Q                                       , RULL(0x08012375), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBRCER3Q                                         , RULL(0x0701237A), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBRCER3Q                                       , RULL(0x0701237A), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBRCER3Q                                       , RULL(0x0801237A), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSEC0Q                                          , RULL(0x07012355), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSEC0Q                                        , RULL(0x07012355), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSEC0Q                                        , RULL(0x08012355), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSEC1Q                                          , RULL(0x07012356), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSEC1Q                                        , RULL(0x07012356), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSEC1Q                                        , RULL(0x08012356), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSEVR0Q                                         , RULL(0x0701237E), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSEVR0Q                                       , RULL(0x0701237E), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSEVR0Q                                       , RULL(0x0801237E), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSEVR1Q                                         , RULL(0x0701237F), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSEVR1Q                                       , RULL(0x0701237F), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSEVR1Q                                       , RULL(0x0801237F), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSMODESQ                                        , RULL(0x07012362), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSMODESQ                                      , RULL(0x07012362), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSMODESQ                                      , RULL(0x08012362), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSMSECQ                                         , RULL(0x07012369), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSMSECQ                                       , RULL(0x07012369), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSMSECQ                                       , RULL(0x08012369), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSSYMEC0Q                                       , RULL(0x07012358), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSSYMEC0Q                                     , RULL(0x07012358), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSSYMEC0Q                                     , RULL(0x08012358), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSSYMEC1Q                                       , RULL(0x07012359), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSSYMEC1Q                                     , RULL(0x07012359), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSSYMEC1Q                                     , RULL(0x08012359), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSSYMEC2Q                                       , RULL(0x0701235A), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSSYMEC2Q                                     , RULL(0x0701235A), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSSYMEC2Q                                     , RULL(0x0801235A), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSSYMEC3Q                                       , RULL(0x0701235B), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSSYMEC3Q                                     , RULL(0x0701235B), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSSYMEC3Q                                     , RULL(0x0801235B), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSSYMEC4Q                                       , RULL(0x0701235C), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSSYMEC4Q                                     , RULL(0x0701235C), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSSYMEC4Q                                     , RULL(0x0801235C), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSSYMEC5Q                                       , RULL(0x0701235D), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSSYMEC5Q                                     , RULL(0x0701235D), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSSYMEC5Q                                     , RULL(0x0801235D), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSSYMEC6Q                                       , RULL(0x0701235E), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSSYMEC6Q                                     , RULL(0x0701235E), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSSYMEC6Q                                     , RULL(0x0801235E), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSSYMEC7Q                                       , RULL(0x0701235F), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSSYMEC7Q                                     , RULL(0x0701235F), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSSYMEC7Q                                     , RULL(0x0801235F), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSSYMEC8Q                                       , RULL(0x07012360), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSSYMEC8Q                                     , RULL(0x07012360), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSSYMEC8Q                                     , RULL(0x08012360), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBSTRQ                                           , RULL(0x07012357), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBSTRQ                                         , RULL(0x07012357), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBSTRQ                                         , RULL(0x08012357), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBUER0Q                                          , RULL(0x0701236D), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBUER0Q                                        , RULL(0x0701236D), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBUER0Q                                        , RULL(0x0801236D), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBUER1Q                                          , RULL(0x07012372), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBUER1Q                                        , RULL(0x07012372), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBUER1Q                                        , RULL(0x08012372), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBUER2Q                                          , RULL(0x07012377), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBUER2Q                                        , RULL(0x07012377), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBUER2Q                                        , RULL(0x08012377), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MBUER3Q                                          , RULL(0x0701237C), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MBUER3Q                                        , RULL(0x0701237C), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MBUER3Q                                        , RULL(0x0801237C), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCS_0_PORT02_MCAMOC                                     , RULL(0x05010825), SH_UNT_MCS_0_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_0_PORT13_MCAMOC                                     , RULL(0x05010835), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT02_MCAMOC                                     , RULL(0x050108A5), SH_UNT_MCS_1_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT13_MCAMOC                                     , RULL(0x050108B5), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT02_MCAMOC                                     , RULL(0x03010825), SH_UNT_MCS_2_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT13_MCAMOC                                     , RULL(0x03010835), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT02_MCAMOC                                     , RULL(0x030108A5), SH_UNT_MCS_3_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT13_MCAMOC                                     , RULL(0x030108B5), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT02_MCAMOC                                       , RULL(0x05010825), SH_UNT_MCS_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT13_MCAMOC                                       , RULL(0x05010835), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM3_RW  );
+
+REG64( MCBIST_MCBACQ                                           , RULL(0x070123D5), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBACQ                                         , RULL(0x070123D5), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBACQ                                         , RULL(0x080123D5), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBAGRAQ                                         , RULL(0x070123D6), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBAGRAQ                                       , RULL(0x070123D6), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBAGRAQ                                       , RULL(0x080123D6), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBAMR0A0Q                                       , RULL(0x070123C8), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBAMR0A0Q                                     , RULL(0x070123C8), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBAMR0A0Q                                     , RULL(0x080123C8), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBAMR1A0Q                                       , RULL(0x070123C9), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBAMR1A0Q                                     , RULL(0x070123C9), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBAMR1A0Q                                     , RULL(0x080123C9), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBAMR2A0Q                                       , RULL(0x070123CA), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBAMR2A0Q                                     , RULL(0x070123CA), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBAMR2A0Q                                     , RULL(0x080123CA), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBAMR3A0Q                                       , RULL(0x070123CB), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBAMR3A0Q                                     , RULL(0x070123CB), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBAMR3A0Q                                     , RULL(0x080123CB), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBCFGQ                                          , RULL(0x070123E0), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBCFGQ                                        , RULL(0x070123E0), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBCFGQ                                        , RULL(0x080123E0), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCA_MCBCM                                               , RULL(0x07010A2C), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_MCBCM                                             , RULL(0x07010A2C), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_MCBCM                                             , RULL(0x07010A6C), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_MCBCM                                             , RULL(0x07010AAC), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_MCBCM                                             , RULL(0x07010AEC), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_MCBCM                                             , RULL(0x08010A2C), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_MCBCM                                             , RULL(0x08010A6C), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_MCBCM                                             , RULL(0x08010AAC), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_MCBCM                                             , RULL(0x08010AEC), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBDRCRQ                                         , RULL(0x070123BD), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBDRCRQ                                       , RULL(0x070123BD), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBDRCRQ                                       , RULL(0x080123BD), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBDRSRQ                                         , RULL(0x070123BC), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBDRSRQ                                       , RULL(0x070123BC), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBDRSRQ                                       , RULL(0x080123BC), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBEA0Q                                          , RULL(0x070123CE), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBEA0Q                                        , RULL(0x070123CE), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBEA0Q                                        , RULL(0x080123CE), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBEA1Q                                          , RULL(0x070123CF), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBEA1Q                                        , RULL(0x070123CF), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBEA1Q                                        , RULL(0x080123CF), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBEA2Q                                          , RULL(0x070123D2), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBEA2Q                                        , RULL(0x070123D2), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBEA2Q                                        , RULL(0x080123D2), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBEA3Q                                          , RULL(0x070123D3), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBEA3Q                                        , RULL(0x070123D3), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBEA3Q                                        , RULL(0x080123D3), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBFD0Q                                          , RULL(0x070123BE), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBFD0Q                                        , RULL(0x070123BE), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBFD0Q                                        , RULL(0x080123BE), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBFD1Q                                          , RULL(0x070123BF), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBFD1Q                                        , RULL(0x070123BF), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBFD1Q                                        , RULL(0x080123BF), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBFD2Q                                          , RULL(0x070123C0), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBFD2Q                                        , RULL(0x070123C0), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBFD2Q                                        , RULL(0x080123C0), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBFD3Q                                          , RULL(0x070123C1), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBFD3Q                                        , RULL(0x070123C1), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBFD3Q                                        , RULL(0x080123C1), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBFD4Q                                          , RULL(0x070123C2), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBFD4Q                                        , RULL(0x070123C2), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBFD4Q                                        , RULL(0x080123C2), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBFD5Q                                          , RULL(0x070123C3), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBFD5Q                                        , RULL(0x070123C3), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBFD5Q                                        , RULL(0x080123C3), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBFD6Q                                          , RULL(0x070123C4), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBFD6Q                                        , RULL(0x070123C4), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBFD6Q                                        , RULL(0x080123C4), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBFD7Q                                          , RULL(0x070123C5), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBFD7Q                                        , RULL(0x070123C5), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBFD7Q                                        , RULL(0x080123C5), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBFDQ                                           , RULL(0x070123C6), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBFDQ                                         , RULL(0x070123C6), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBFDQ                                         , RULL(0x080123C6), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBISTFIRACT0                                    , RULL(0x07012306), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBISTFIRACT0                                  , RULL(0x07012306), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBISTFIRACT0                                  , RULL(0x08012306), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBISTFIRACT1                                    , RULL(0x07012307), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBISTFIRACT1                                  , RULL(0x07012307), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBISTFIRACT1                                  , RULL(0x08012307), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBISTFIRMASK                                    , RULL(0x07012303), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_MCBISTFIRMASK_AND                                , RULL(0x07012304), SH_UNT_MCBIST   , SH_ACS_SCOM1_AND );
+REG64( MCBIST_MCBISTFIRMASK_OR                                 , RULL(0x07012305), SH_UNT_MCBIST   , SH_ACS_SCOM2_OR  );
+REG64( MCBIST_0_MCBISTFIRMASK                                  , RULL(0x07012303), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBISTFIRMASK_AND                              , RULL(0x07012304), SH_UNT_MCBIST_0 , SH_ACS_SCOM1_AND );
+REG64( MCBIST_0_MCBISTFIRMASK_OR                               , RULL(0x07012305), SH_UNT_MCBIST_0 , SH_ACS_SCOM2_OR  );
+REG64( MCBIST_1_MCBISTFIRMASK                                  , RULL(0x08012303), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBISTFIRMASK_AND                              , RULL(0x08012304), SH_UNT_MCBIST_1 , SH_ACS_SCOM1_AND );
+REG64( MCBIST_1_MCBISTFIRMASK_OR                               , RULL(0x08012305), SH_UNT_MCBIST_1 , SH_ACS_SCOM2_OR  );
+
+REG64( MCBIST_MCBISTFIRQ                                       , RULL(0x07012300), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_MCBISTFIRQ_AND                                   , RULL(0x07012301), SH_UNT_MCBIST   , SH_ACS_SCOM1_AND );
+REG64( MCBIST_MCBISTFIRQ_OR                                    , RULL(0x07012302), SH_UNT_MCBIST   , SH_ACS_SCOM2_OR  );
+REG64( MCBIST_0_MCBISTFIRQ                                     , RULL(0x07012300), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBISTFIRQ_AND                                 , RULL(0x07012301), SH_UNT_MCBIST_0 , SH_ACS_SCOM1_AND );
+REG64( MCBIST_0_MCBISTFIRQ_OR                                  , RULL(0x07012302), SH_UNT_MCBIST_0 , SH_ACS_SCOM2_OR  );
+REG64( MCBIST_1_MCBISTFIRQ                                     , RULL(0x08012300), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBISTFIRQ_AND                                 , RULL(0x08012301), SH_UNT_MCBIST_1 , SH_ACS_SCOM1_AND );
+REG64( MCBIST_1_MCBISTFIRQ_OR                                  , RULL(0x08012302), SH_UNT_MCBIST_1 , SH_ACS_SCOM2_OR  );
+
+REG64( MCBIST_MCBISTFIRWOF                                     , RULL(0x07012308), SH_UNT_MCBIST   ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCBIST_0_MCBISTFIRWOF                                   , RULL(0x07012308), SH_UNT_MCBIST_0 ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCBIST_1_MCBISTFIRWOF                                   , RULL(0x08012308), SH_UNT_MCBIST_1 ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( MCBIST_MCBLFSRA0Q                                       , RULL(0x070123D4), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBLFSRA0Q                                     , RULL(0x070123D4), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBLFSRA0Q                                     , RULL(0x080123D4), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBMCATQ                                         , RULL(0x070123D7), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBMCATQ                                       , RULL(0x070123D7), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBMCATQ                                       , RULL(0x080123D7), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBMR0Q                                          , RULL(0x070123A8), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBMR0Q                                        , RULL(0x070123A8), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBMR0Q                                        , RULL(0x080123A8), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBMR1Q                                          , RULL(0x070123A9), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBMR1Q                                        , RULL(0x070123A9), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBMR1Q                                        , RULL(0x080123A9), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBMR2Q                                          , RULL(0x070123AA), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBMR2Q                                        , RULL(0x070123AA), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBMR2Q                                        , RULL(0x080123AA), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBMR3Q                                          , RULL(0x070123AB), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBMR3Q                                        , RULL(0x070123AB), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBMR3Q                                        , RULL(0x080123AB), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBMR4Q                                          , RULL(0x070123AC), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBMR4Q                                        , RULL(0x070123AC), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBMR4Q                                        , RULL(0x080123AC), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBMR5Q                                          , RULL(0x070123AD), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBMR5Q                                        , RULL(0x070123AD), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBMR5Q                                        , RULL(0x080123AD), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBMR6Q                                          , RULL(0x070123AE), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBMR6Q                                        , RULL(0x070123AE), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBMR6Q                                        , RULL(0x080123AE), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBMR7Q                                          , RULL(0x070123DF), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBMR7Q                                        , RULL(0x070123DF), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBMR7Q                                        , RULL(0x080123DF), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBPARMQ                                         , RULL(0x070123AF), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBPARMQ                                       , RULL(0x070123AF), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBPARMQ                                       , RULL(0x080123AF), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBRCRQ                                          , RULL(0x070123B1), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBRCRQ                                        , RULL(0x070123B1), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBRCRQ                                        , RULL(0x080123B1), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBRDS0Q                                         , RULL(0x070123B2), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBRDS0Q                                       , RULL(0x070123B2), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBRDS0Q                                       , RULL(0x080123B2), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBRDS1Q                                         , RULL(0x070123B3), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBRDS1Q                                       , RULL(0x070123B3), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBRDS1Q                                       , RULL(0x080123B3), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBSA0Q                                          , RULL(0x070123CC), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBSA0Q                                        , RULL(0x070123CC), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBSA0Q                                        , RULL(0x080123CC), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBSA1Q                                          , RULL(0x070123CD), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBSA1Q                                        , RULL(0x070123CD), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBSA1Q                                        , RULL(0x080123CD), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBSA2Q                                          , RULL(0x070123D0), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBSA2Q                                        , RULL(0x070123D0), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBSA2Q                                        , RULL(0x080123D0), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBSA3Q                                          , RULL(0x070123D1), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCBSA3Q                                        , RULL(0x070123D1), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCBSA3Q                                        , RULL(0x080123D1), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCBSTATQ                                         , RULL(0x07012366), SH_UNT_MCBIST   , SH_ACS_SCOM_RO   );
+REG64( MCBIST_0_MCBSTATQ                                       , RULL(0x07012366), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RO   );
+REG64( MCBIST_1_MCBSTATQ                                       , RULL(0x08012366), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RO   );
+
+REG64( MCS_0_PORT02_MCBUSYQ                                    , RULL(0x05010827), SH_UNT_MCS_0_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_0_PORT13_MCBUSYQ                                    , RULL(0x05010837), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT02_MCBUSYQ                                    , RULL(0x050108A7), SH_UNT_MCS_1_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT13_MCBUSYQ                                    , RULL(0x050108B7), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT02_MCBUSYQ                                    , RULL(0x03010827), SH_UNT_MCS_2_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT13_MCBUSYQ                                    , RULL(0x03010837), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT02_MCBUSYQ                                    , RULL(0x030108A7), SH_UNT_MCS_3_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT13_MCBUSYQ                                    , RULL(0x030108B7), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT02_MCBUSYQ                                      , RULL(0x05010827), SH_UNT_MCS_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT13_MCBUSYQ                                      , RULL(0x05010837), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM3_RW  );
+
+REG64( MCBIST_MCB_CNTLQ                                        , RULL(0x070123DB), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCB_CNTLQ                                      , RULL(0x070123DB), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCB_CNTLQ                                      , RULL(0x080123DB), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_MCB_CNTLSTATQ                                    , RULL(0x070123DC), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_MCB_CNTLSTATQ                                  , RULL(0x070123DC), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_MCB_CNTLSTATQ                                  , RULL(0x080123DC), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCS_MCDBG0                                              , RULL(0x05010816), SH_UNT_MCS      , SH_ACS_SCOM_RO   );
+REG64( MCS_0_MCDBG0                                            , RULL(0x05010816), SH_UNT_MCS_0    , SH_ACS_SCOM_RO   );
+REG64( MCS_1_MCDBG0                                            , RULL(0x05010896), SH_UNT_MCS_1    , SH_ACS_SCOM_RO   );
+REG64( MCS_2_MCDBG0                                            , RULL(0x03010816), SH_UNT_MCS_2    , SH_ACS_SCOM_RO   );
+REG64( MCS_3_MCDBG0                                            , RULL(0x03010896), SH_UNT_MCS_3    , SH_ACS_SCOM_RO   );
+
+REG64( MCS_MCDBG1                                              , RULL(0x05010817), SH_UNT_MCS      , SH_ACS_SCOM_RO   );
+REG64( MCS_0_MCDBG1                                            , RULL(0x05010817), SH_UNT_MCS_0    , SH_ACS_SCOM_RO   );
+REG64( MCS_1_MCDBG1                                            , RULL(0x05010897), SH_UNT_MCS_1    , SH_ACS_SCOM_RO   );
+REG64( MCS_2_MCDBG1                                            , RULL(0x03010817), SH_UNT_MCS_2    , SH_ACS_SCOM_RO   );
+REG64( MCS_3_MCDBG1                                            , RULL(0x03010897), SH_UNT_MCS_3    , SH_ACS_SCOM_RO   );
+
+REG64( MCS_0_PORT02_MCEBUSCL                                   , RULL(0x05010829), SH_UNT_MCS_0_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_0_PORT13_MCEBUSCL                                   , RULL(0x05010839), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT02_MCEBUSCL                                   , RULL(0x050108A9), SH_UNT_MCS_1_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT13_MCEBUSCL                                   , RULL(0x050108B9), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT02_MCEBUSCL                                   , RULL(0x03010829), SH_UNT_MCS_2_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT13_MCEBUSCL                                   , RULL(0x03010839), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT02_MCEBUSCL                                   , RULL(0x030108A9), SH_UNT_MCS_3_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT13_MCEBUSCL                                   , RULL(0x030108B9), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT02_MCEBUSCL                                     , RULL(0x05010829), SH_UNT_MCS_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT13_MCEBUSCL                                     , RULL(0x05010839), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM3_RW  );
+
+REG64( MCS_0_PORT13_MCEBUSEN0                                  , RULL(0x0501083C), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_1_PORT13_MCEBUSEN0                                  , RULL(0x050108BC), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_2_PORT13_MCEBUSEN0                                  , RULL(0x0301083C), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_3_PORT13_MCEBUSEN0                                  , RULL(0x030108BC), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_PORT13_MCEBUSEN0                                    , RULL(0x0501083C), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCS_0_PORT13_MCEBUSEN1                                  , RULL(0x0501083D), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_1_PORT13_MCEBUSEN1                                  , RULL(0x050108BD), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_2_PORT13_MCEBUSEN1                                  , RULL(0x0301083D), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_3_PORT13_MCEBUSEN1                                  , RULL(0x030108BD), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_PORT13_MCEBUSEN1                                    , RULL(0x0501083D), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCS_0_PORT13_MCEBUSEN2                                  , RULL(0x0501083E), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_1_PORT13_MCEBUSEN2                                  , RULL(0x050108BE), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_2_PORT13_MCEBUSEN2                                  , RULL(0x0301083E), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_3_PORT13_MCEBUSEN2                                  , RULL(0x030108BE), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_PORT13_MCEBUSEN2                                    , RULL(0x0501083E), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCS_0_PORT13_MCEBUSEN3                                  , RULL(0x0501083F), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_1_PORT13_MCEBUSEN3                                  , RULL(0x050108BF), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_2_PORT13_MCEBUSEN3                                  , RULL(0x0301083F), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_3_PORT13_MCEBUSEN3                                  , RULL(0x030108BF), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM_RW   );
+REG64( MCS_PORT13_MCEBUSEN3                                    , RULL(0x0501083F), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM_RW   );
+
+REG64( MCS_0_PORT02_MCEPSQ                                     , RULL(0x05010826), SH_UNT_MCS_0_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_0_PORT13_MCEPSQ                                     , RULL(0x05010836), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT02_MCEPSQ                                     , RULL(0x050108A6), SH_UNT_MCS_1_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT13_MCEPSQ                                     , RULL(0x050108B6), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT02_MCEPSQ                                     , RULL(0x03010826), SH_UNT_MCS_2_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT13_MCEPSQ                                     , RULL(0x03010836), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT02_MCEPSQ                                     , RULL(0x030108A6), SH_UNT_MCS_3_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT13_MCEPSQ                                     , RULL(0x030108B6), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT02_MCEPSQ                                       , RULL(0x05010826), SH_UNT_MCS_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT13_MCEPSQ                                       , RULL(0x05010836), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM3_RW  );
+
+REG64( MCS_MCERPT0                                             , RULL(0x0501081E), SH_UNT_MCS      , SH_ACS_SCOM_RO   );
+REG64( MCS_0_MCERPT0                                           , RULL(0x0501081E), SH_UNT_MCS_0    , SH_ACS_SCOM_RO   );
+REG64( MCS_1_MCERPT0                                           , RULL(0x0501089E), SH_UNT_MCS_1    , SH_ACS_SCOM_RO   );
+REG64( MCS_2_MCERPT0                                           , RULL(0x0301081E), SH_UNT_MCS_2    , SH_ACS_SCOM_RO   );
+REG64( MCS_3_MCERPT0                                           , RULL(0x0301089E), SH_UNT_MCS_3    , SH_ACS_SCOM_RO   );
+
+REG64( MCS_MCERPT1                                             , RULL(0x0501081F), SH_UNT_MCS      , SH_ACS_SCOM_RO   );
+REG64( MCS_0_MCERPT1                                           , RULL(0x0501081F), SH_UNT_MCS_0    , SH_ACS_SCOM_RO   );
+REG64( MCS_1_MCERPT1                                           , RULL(0x0501089F), SH_UNT_MCS_1    , SH_ACS_SCOM_RO   );
+REG64( MCS_2_MCERPT1                                           , RULL(0x0301081F), SH_UNT_MCS_2    , SH_ACS_SCOM_RO   );
+REG64( MCS_3_MCERPT1                                           , RULL(0x0301089F), SH_UNT_MCS_3    , SH_ACS_SCOM_RO   );
+
+REG64( MCS_MCERPT2                                             , RULL(0x0501081A), SH_UNT_MCS      , SH_ACS_SCOM_RO   );
+REG64( MCS_0_MCERPT2                                           , RULL(0x0501081A), SH_UNT_MCS_0    , SH_ACS_SCOM_RO   );
+REG64( MCS_1_MCERPT2                                           , RULL(0x0501089A), SH_UNT_MCS_1    , SH_ACS_SCOM_RO   );
+REG64( MCS_2_MCERPT2                                           , RULL(0x0301081A), SH_UNT_MCS_2    , SH_ACS_SCOM_RO   );
+REG64( MCS_3_MCERPT2                                           , RULL(0x0301089A), SH_UNT_MCS_3    , SH_ACS_SCOM_RO   );
+
+REG64( MCS_0_PORT02_MCERRINJ                                   , RULL(0x05010828), SH_UNT_MCS_0_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_0_PORT13_MCERRINJ                                   , RULL(0x05010838), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT02_MCERRINJ                                   , RULL(0x050108A8), SH_UNT_MCS_1_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT13_MCERRINJ                                   , RULL(0x050108B8), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT02_MCERRINJ                                   , RULL(0x03010828), SH_UNT_MCS_2_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT13_MCERRINJ                                   , RULL(0x03010838), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT02_MCERRINJ                                   , RULL(0x030108A8), SH_UNT_MCS_3_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT13_MCERRINJ                                   , RULL(0x030108B8), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT02_MCERRINJ                                     , RULL(0x05010828), SH_UNT_MCS_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT13_MCERRINJ                                     , RULL(0x05010838), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM3_RW  );
+
+REG64( MCS_MCFGP                                               , RULL(0x0501080A), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCFGP                                             , RULL(0x0501080A), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCFGP                                             , RULL(0x0501088A), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCFGP                                             , RULL(0x0301080A), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCFGP                                             , RULL(0x0301088A), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+
+REG64( MCS_MCFGPA                                              , RULL(0x0501080B), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCFGPA                                            , RULL(0x0501080B), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCFGPA                                            , RULL(0x0501088B), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCFGPA                                            , RULL(0x0301080B), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCFGPA                                            , RULL(0x0301088B), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+
+REG64( MCS_MCFGPM                                              , RULL(0x0501080C), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCFGPM                                            , RULL(0x0501080C), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCFGPM                                            , RULL(0x0501088C), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCFGPM                                            , RULL(0x0301080C), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCFGPM                                            , RULL(0x0301088C), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+
+REG64( MCS_MCFGPMA                                             , RULL(0x0501080D), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCFGPMA                                           , RULL(0x0501080D), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCFGPMA                                           , RULL(0x0501088D), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCFGPMA                                           , RULL(0x0301080D), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCFGPMA                                           , RULL(0x0301088D), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+
+REG64( MCS_MCFIR                                               , RULL(0x05010800), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_MCFIR_AND                                           , RULL(0x05010801), SH_UNT_MCS      , SH_ACS_SCOM1_AND );
+REG64( MCS_MCFIR_OR                                            , RULL(0x05010802), SH_UNT_MCS      , SH_ACS_SCOM2_OR  );
+REG64( MCS_0_MCFIR                                             , RULL(0x05010800), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCFIR_AND                                         , RULL(0x05010801), SH_UNT_MCS_0    , SH_ACS_SCOM1_AND );
+REG64( MCS_0_MCFIR_OR                                          , RULL(0x05010802), SH_UNT_MCS_0    , SH_ACS_SCOM2_OR  );
+REG64( MCS_1_MCFIR                                             , RULL(0x05010880), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCFIR_AND                                         , RULL(0x05010881), SH_UNT_MCS_1    , SH_ACS_SCOM1_AND );
+REG64( MCS_1_MCFIR_OR                                          , RULL(0x05010882), SH_UNT_MCS_1    , SH_ACS_SCOM2_OR  );
+REG64( MCS_2_MCFIR                                             , RULL(0x03010800), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCFIR_AND                                         , RULL(0x03010801), SH_UNT_MCS_2    , SH_ACS_SCOM1_AND );
+REG64( MCS_2_MCFIR_OR                                          , RULL(0x03010802), SH_UNT_MCS_2    , SH_ACS_SCOM2_OR  );
+REG64( MCS_3_MCFIR                                             , RULL(0x03010880), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCFIR_AND                                         , RULL(0x03010881), SH_UNT_MCS_3    , SH_ACS_SCOM1_AND );
+REG64( MCS_3_MCFIR_OR                                          , RULL(0x03010882), SH_UNT_MCS_3    , SH_ACS_SCOM2_OR  );
+
+REG64( MCS_MCFIRACT0                                           , RULL(0x05010806), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCFIRACT0                                         , RULL(0x05010806), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCFIRACT0                                         , RULL(0x05010886), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCFIRACT0                                         , RULL(0x03010806), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCFIRACT0                                         , RULL(0x03010886), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+
+REG64( MCS_MCFIRACT1                                           , RULL(0x05010807), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCFIRACT1                                         , RULL(0x05010807), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCFIRACT1                                         , RULL(0x05010887), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCFIRACT1                                         , RULL(0x03010807), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCFIRACT1                                         , RULL(0x03010887), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+
+REG64( MCS_MCFIRMASK                                           , RULL(0x05010803), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_MCFIRMASK_AND                                       , RULL(0x05010804), SH_UNT_MCS      , SH_ACS_SCOM1_AND );
+REG64( MCS_MCFIRMASK_OR                                        , RULL(0x05010805), SH_UNT_MCS      , SH_ACS_SCOM2_OR  );
+REG64( MCS_0_MCFIRMASK                                         , RULL(0x05010803), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCFIRMASK_AND                                     , RULL(0x05010804), SH_UNT_MCS_0    , SH_ACS_SCOM1_AND );
+REG64( MCS_0_MCFIRMASK_OR                                      , RULL(0x05010805), SH_UNT_MCS_0    , SH_ACS_SCOM2_OR  );
+REG64( MCS_1_MCFIRMASK                                         , RULL(0x05010883), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCFIRMASK_AND                                     , RULL(0x05010884), SH_UNT_MCS_1    , SH_ACS_SCOM1_AND );
+REG64( MCS_1_MCFIRMASK_OR                                      , RULL(0x05010885), SH_UNT_MCS_1    , SH_ACS_SCOM2_OR  );
+REG64( MCS_2_MCFIRMASK                                         , RULL(0x03010803), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCFIRMASK_AND                                     , RULL(0x03010804), SH_UNT_MCS_2    , SH_ACS_SCOM1_AND );
+REG64( MCS_2_MCFIRMASK_OR                                      , RULL(0x03010805), SH_UNT_MCS_2    , SH_ACS_SCOM2_OR  );
+REG64( MCS_3_MCFIRMASK                                         , RULL(0x03010883), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCFIRMASK_AND                                     , RULL(0x03010884), SH_UNT_MCS_3    , SH_ACS_SCOM1_AND );
+REG64( MCS_3_MCFIRMASK_OR                                      , RULL(0x03010885), SH_UNT_MCS_3    , SH_ACS_SCOM2_OR  );
+
+REG64( MCS_MCLFSR                                              , RULL(0x05010814), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCLFSR                                            , RULL(0x05010814), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCLFSR                                            , RULL(0x05010894), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCLFSR                                            , RULL(0x03010814), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCLFSR                                            , RULL(0x03010894), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+
+REG64( MCS_MCMODE0                                             , RULL(0x05010811), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCMODE0                                           , RULL(0x05010811), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCMODE0                                           , RULL(0x05010891), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCMODE0                                           , RULL(0x03010811), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCMODE0                                           , RULL(0x03010891), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+
+REG64( MCS_MCMODE1                                             , RULL(0x05010812), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCMODE1                                           , RULL(0x05010812), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCMODE1                                           , RULL(0x05010892), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCMODE1                                           , RULL(0x03010812), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCMODE1                                           , RULL(0x03010892), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+
+REG64( MCS_MCMODE2                                             , RULL(0x05010813), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCMODE2                                           , RULL(0x05010813), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCMODE2                                           , RULL(0x05010893), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCMODE2                                           , RULL(0x03010813), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCMODE2                                           , RULL(0x03010893), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+
+REG64( MCS_0_PORT02_MCP0XLT0                                   , RULL(0x05010820), SH_UNT_MCS_0_PORT02,
+       SH_ACS_SCOM3     );
+REG64( MCS_0_PORT13_MCP0XLT0                                   , RULL(0x05010830), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM3     );
+REG64( MCS_1_PORT02_MCP0XLT0                                   , RULL(0x050108A0), SH_UNT_MCS_1_PORT02,
+       SH_ACS_SCOM3     );
+REG64( MCS_1_PORT13_MCP0XLT0                                   , RULL(0x050108B0), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM3     );
+REG64( MCS_2_PORT02_MCP0XLT0                                   , RULL(0x03010820), SH_UNT_MCS_2_PORT02,
+       SH_ACS_SCOM3     );
+REG64( MCS_2_PORT13_MCP0XLT0                                   , RULL(0x03010830), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM3     );
+REG64( MCS_3_PORT02_MCP0XLT0                                   , RULL(0x030108A0), SH_UNT_MCS_3_PORT02,
+       SH_ACS_SCOM3     );
+REG64( MCS_3_PORT13_MCP0XLT0                                   , RULL(0x030108B0), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM3     );
+REG64( MCS_PORT02_MCP0XLT0                                     , RULL(0x05010820), SH_UNT_MCS_PORT02,
+       SH_ACS_SCOM3     );
+REG64( MCS_PORT13_MCP0XLT0                                     , RULL(0x05010830), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM3     );
+
+REG64( MCS_0_PORT02_MCP0XLT1                                   , RULL(0x05010821), SH_UNT_MCS_0_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_0_PORT13_MCP0XLT1                                   , RULL(0x05010831), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT02_MCP0XLT1                                   , RULL(0x050108A1), SH_UNT_MCS_1_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT13_MCP0XLT1                                   , RULL(0x050108B1), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT02_MCP0XLT1                                   , RULL(0x03010821), SH_UNT_MCS_2_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT13_MCP0XLT1                                   , RULL(0x03010831), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT02_MCP0XLT1                                   , RULL(0x030108A1), SH_UNT_MCS_3_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT13_MCP0XLT1                                   , RULL(0x030108B1), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT02_MCP0XLT1                                     , RULL(0x05010821), SH_UNT_MCS_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT13_MCP0XLT1                                     , RULL(0x05010831), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM3_RW  );
+
+REG64( MCS_0_PORT02_MCP0XLT2                                   , RULL(0x05010822), SH_UNT_MCS_0_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_0_PORT13_MCP0XLT2                                   , RULL(0x05010832), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT02_MCP0XLT2                                   , RULL(0x050108A2), SH_UNT_MCS_1_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT13_MCP0XLT2                                   , RULL(0x050108B2), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT02_MCP0XLT2                                   , RULL(0x03010822), SH_UNT_MCS_2_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT13_MCP0XLT2                                   , RULL(0x03010832), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT02_MCP0XLT2                                   , RULL(0x030108A2), SH_UNT_MCS_3_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT13_MCP0XLT2                                   , RULL(0x030108B2), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT02_MCP0XLT2                                     , RULL(0x05010822), SH_UNT_MCS_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT13_MCP0XLT2                                     , RULL(0x05010832), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM3_RW  );
+
+REG64( MCS_0_PORT02_MCPERF0                                    , RULL(0x05010823), SH_UNT_MCS_0_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_0_PORT13_MCPERF0                                    , RULL(0x05010833), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT02_MCPERF0                                    , RULL(0x050108A3), SH_UNT_MCS_1_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT13_MCPERF0                                    , RULL(0x050108B3), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT02_MCPERF0                                    , RULL(0x03010823), SH_UNT_MCS_2_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT13_MCPERF0                                    , RULL(0x03010833), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT02_MCPERF0                                    , RULL(0x030108A3), SH_UNT_MCS_3_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT13_MCPERF0                                    , RULL(0x030108B3), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT02_MCPERF0                                      , RULL(0x05010823), SH_UNT_MCS_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT13_MCPERF0                                      , RULL(0x05010833), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM3_RW  );
+
+REG64( MCS_MCPERF1                                             , RULL(0x05010810), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCPERF1                                           , RULL(0x05010810), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCPERF1                                           , RULL(0x05010890), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCPERF1                                           , RULL(0x03010810), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCPERF1                                           , RULL(0x03010890), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+
+REG64( MCS_0_PORT02_MCPERF2                                    , RULL(0x05010824), SH_UNT_MCS_0_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_0_PORT13_MCPERF2                                    , RULL(0x05010834), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT02_MCPERF2                                    , RULL(0x050108A4), SH_UNT_MCS_1_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT13_MCPERF2                                    , RULL(0x050108B4), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT02_MCPERF2                                    , RULL(0x03010824), SH_UNT_MCS_2_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT13_MCPERF2                                    , RULL(0x03010834), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT02_MCPERF2                                    , RULL(0x030108A4), SH_UNT_MCS_3_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT13_MCPERF2                                    , RULL(0x030108B4), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT02_MCPERF2                                      , RULL(0x05010824), SH_UNT_MCS_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT13_MCPERF2                                      , RULL(0x05010834), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM3_RW  );
+
+REG64( MCS_0_PORT02_MCPERF3                                    , RULL(0x0501082B), SH_UNT_MCS_0_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_0_PORT13_MCPERF3                                    , RULL(0x0501083B), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT02_MCPERF3                                    , RULL(0x050108AB), SH_UNT_MCS_1_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT13_MCPERF3                                    , RULL(0x050108BB), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT02_MCPERF3                                    , RULL(0x0301082B), SH_UNT_MCS_2_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT13_MCPERF3                                    , RULL(0x0301083B), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT02_MCPERF3                                    , RULL(0x030108AB), SH_UNT_MCS_3_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT13_MCPERF3                                    , RULL(0x030108BB), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT02_MCPERF3                                      , RULL(0x0501082B), SH_UNT_MCS_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT13_MCPERF3                                      , RULL(0x0501083B), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM3_RW  );
+
+REG64( MCS_MCSYNC                                              , RULL(0x05010815), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCSYNC                                            , RULL(0x05010815), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCSYNC                                            , RULL(0x05010895), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCSYNC                                            , RULL(0x03010815), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCSYNC                                            , RULL(0x03010895), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+
+REG64( MCS_MCTEST                                              , RULL(0x05010818), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCTEST                                            , RULL(0x05010818), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCTEST                                            , RULL(0x05010898), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCTEST                                            , RULL(0x03010818), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCTEST                                            , RULL(0x03010898), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+
+REG64( MCS_MCTO                                                , RULL(0x0501081B), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCTO                                              , RULL(0x0501081B), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCTO                                              , RULL(0x0501089B), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCTO                                              , RULL(0x0301081B), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCTO                                              , RULL(0x0301089B), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+
+REG64( MCS_0_PORT02_MCWAT                                      , RULL(0x0501082A), SH_UNT_MCS_0_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_0_PORT13_MCWAT                                      , RULL(0x0501083A), SH_UNT_MCS_0_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT02_MCWAT                                      , RULL(0x050108AA), SH_UNT_MCS_1_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_1_PORT13_MCWAT                                      , RULL(0x050108BA), SH_UNT_MCS_1_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT02_MCWAT                                      , RULL(0x0301082A), SH_UNT_MCS_2_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_2_PORT13_MCWAT                                      , RULL(0x0301083A), SH_UNT_MCS_2_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT02_MCWAT                                      , RULL(0x030108AA), SH_UNT_MCS_3_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_3_PORT13_MCWAT                                      , RULL(0x030108BA), SH_UNT_MCS_3_PORT13,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT02_MCWAT                                        , RULL(0x0501082A), SH_UNT_MCS_PORT02,
+       SH_ACS_SCOM3_RW  );
+REG64( MCS_PORT13_MCWAT                                        , RULL(0x0501083A), SH_UNT_MCS_PORT13,
+       SH_ACS_SCOM3_RW  );
+
+REG64( MCS_MCWATCNTL                                           , RULL(0x0501081C), SH_UNT_MCS      , SH_ACS_SCOM_RW   );
+REG64( MCS_0_MCWATCNTL                                         , RULL(0x0501081C), SH_UNT_MCS_0    , SH_ACS_SCOM_RW   );
+REG64( MCS_1_MCWATCNTL                                         , RULL(0x0501089C), SH_UNT_MCS_1    , SH_ACS_SCOM_RW   );
+REG64( MCS_2_MCWATCNTL                                         , RULL(0x0301081C), SH_UNT_MCS_2    , SH_ACS_SCOM_RW   );
+REG64( MCS_3_MCWATCNTL                                         , RULL(0x0301089C), SH_UNT_MCS_3    , SH_ACS_SCOM_RW   );
+
+REG64( MCS_MCWATDATA                                           , RULL(0x0501081D), SH_UNT_MCS      , SH_ACS_SCOM_RO   );
+REG64( MCS_0_MCWATDATA                                         , RULL(0x0501081D), SH_UNT_MCS_0    , SH_ACS_SCOM_RO   );
+REG64( MCS_1_MCWATDATA                                         , RULL(0x0501089D), SH_UNT_MCS_1    , SH_ACS_SCOM_RO   );
+REG64( MCS_2_MCWATDATA                                         , RULL(0x0301081D), SH_UNT_MCS_2    , SH_ACS_SCOM_RO   );
+REG64( MCS_3_MCWATDATA                                         , RULL(0x0301089D), SH_UNT_MCS_3    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_MSR                                                 , RULL(0x07010A0C), SH_UNT_MCA      , SH_ACS_SCOM_RO   );
+REG64( MCA_0_MSR                                               , RULL(0x07010A0C), SH_UNT_MCA_0    , SH_ACS_SCOM_RO   );
+REG64( MCA_1_MSR                                               , RULL(0x07010A4C), SH_UNT_MCA_1    , SH_ACS_SCOM_RO   );
+REG64( MCA_2_MSR                                               , RULL(0x07010A8C), SH_UNT_MCA_2    , SH_ACS_SCOM_RO   );
+REG64( MCA_3_MSR                                               , RULL(0x07010ACC), SH_UNT_MCA_3    , SH_ACS_SCOM_RO   );
+REG64( MCA_4_MSR                                               , RULL(0x08010A0C), SH_UNT_MCA_4    , SH_ACS_SCOM_RO   );
+REG64( MCA_5_MSR                                               , RULL(0x08010A4C), SH_UNT_MCA_5    , SH_ACS_SCOM_RO   );
+REG64( MCA_6_MSR                                               , RULL(0x08010A8C), SH_UNT_MCA_6    , SH_ACS_SCOM_RO   );
+REG64( MCA_7_MSR                                               , RULL(0x08010ACC), SH_UNT_MCA_7    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_PHY0_DDRPHY_FIR_ACTION0_REG                         , RULL(0x07011006), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_PHY0_DDRPHY_FIR_ACTION0_REG                       , RULL(0x07011006), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_PHY0_DDRPHY_FIR_ACTION0_REG                       , RULL(0x08011006), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_PHY0_DDRPHY_FIR_ACTION1_REG                         , RULL(0x07011007), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_PHY0_DDRPHY_FIR_ACTION1_REG                       , RULL(0x07011007), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_PHY0_DDRPHY_FIR_ACTION1_REG                       , RULL(0x08011007), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_PHY0_DDRPHY_FIR_MASK_REG                            , RULL(0x07011003), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_PHY0_DDRPHY_FIR_MASK_REG_AND                        , RULL(0x07011004), SH_UNT_MCA      , SH_ACS_SCOM1_AND );
+REG64( MCA_PHY0_DDRPHY_FIR_MASK_REG_OR                         , RULL(0x07011005), SH_UNT_MCA      , SH_ACS_SCOM2_OR  );
+REG64( MCA_0_PHY0_DDRPHY_FIR_MASK_REG                          , RULL(0x07011003), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_0_PHY0_DDRPHY_FIR_MASK_REG_AND                      , RULL(0x07011004), SH_UNT_MCA_0    , SH_ACS_SCOM1_AND );
+REG64( MCA_0_PHY0_DDRPHY_FIR_MASK_REG_OR                       , RULL(0x07011005), SH_UNT_MCA_0    , SH_ACS_SCOM2_OR  );
+REG64( MCA_4_PHY0_DDRPHY_FIR_MASK_REG                          , RULL(0x08011003), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_PHY0_DDRPHY_FIR_MASK_REG_AND                      , RULL(0x08011004), SH_UNT_MCA_4    , SH_ACS_SCOM1_AND );
+REG64( MCA_4_PHY0_DDRPHY_FIR_MASK_REG_OR                       , RULL(0x08011005), SH_UNT_MCA_4    , SH_ACS_SCOM2_OR  );
+
+REG64( MCA_PHY0_DDRPHY_FIR_REG                                 , RULL(0x07011000), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_PHY0_DDRPHY_FIR_REG_AND                             , RULL(0x07011001), SH_UNT_MCA      , SH_ACS_SCOM1_AND );
+REG64( MCA_PHY0_DDRPHY_FIR_REG_OR                              , RULL(0x07011002), SH_UNT_MCA      , SH_ACS_SCOM2_OR  );
+REG64( MCA_0_PHY0_DDRPHY_FIR_REG                               , RULL(0x07011000), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_0_PHY0_DDRPHY_FIR_REG_AND                           , RULL(0x07011001), SH_UNT_MCA_0    , SH_ACS_SCOM1_AND );
+REG64( MCA_0_PHY0_DDRPHY_FIR_REG_OR                            , RULL(0x07011002), SH_UNT_MCA_0    , SH_ACS_SCOM2_OR  );
+REG64( MCA_4_PHY0_DDRPHY_FIR_REG                               , RULL(0x08011000), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_PHY0_DDRPHY_FIR_REG_AND                           , RULL(0x08011001), SH_UNT_MCA_4    , SH_ACS_SCOM1_AND );
+REG64( MCA_4_PHY0_DDRPHY_FIR_REG_OR                            , RULL(0x08011002), SH_UNT_MCA_4    , SH_ACS_SCOM2_OR  );
+
+REG64( MCA_PHY0_DDRPHY_FIR_WOF_REG                             , RULL(0x07011008), SH_UNT_MCA      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_0_PHY0_DDRPHY_FIR_WOF_REG                           , RULL(0x07011008), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_4_PHY0_DDRPHY_FIR_WOF_REG                           , RULL(0x08011008), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( MCA_1_PHY1_DDRPHY_FIR_ACTION0_REG                       , RULL(0x07011406), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_PHY1_DDRPHY_FIR_ACTION0_REG                       , RULL(0x08011406), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_PHY1_DDRPHY_FIR_ACTION1_REG                       , RULL(0x07011407), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_PHY1_DDRPHY_FIR_ACTION1_REG                       , RULL(0x08011407), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_1_PHY1_DDRPHY_FIR_MASK_REG                          , RULL(0x07011403), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_PHY1_DDRPHY_FIR_MASK_REG_AND                      , RULL(0x07011404), SH_UNT_MCA_1    , SH_ACS_SCOM1_AND );
+REG64( MCA_1_PHY1_DDRPHY_FIR_MASK_REG_OR                       , RULL(0x07011405), SH_UNT_MCA_1    , SH_ACS_SCOM2_OR  );
+REG64( MCA_5_PHY1_DDRPHY_FIR_MASK_REG                          , RULL(0x08011403), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_PHY1_DDRPHY_FIR_MASK_REG_AND                      , RULL(0x08011404), SH_UNT_MCA_5    , SH_ACS_SCOM1_AND );
+REG64( MCA_5_PHY1_DDRPHY_FIR_MASK_REG_OR                       , RULL(0x08011405), SH_UNT_MCA_5    , SH_ACS_SCOM2_OR  );
+
+REG64( MCA_1_PHY1_DDRPHY_FIR_REG                               , RULL(0x07011400), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_PHY1_DDRPHY_FIR_REG_AND                           , RULL(0x07011401), SH_UNT_MCA_1    , SH_ACS_SCOM1_AND );
+REG64( MCA_1_PHY1_DDRPHY_FIR_REG_OR                            , RULL(0x07011402), SH_UNT_MCA_1    , SH_ACS_SCOM2_OR  );
+REG64( MCA_5_PHY1_DDRPHY_FIR_REG                               , RULL(0x08011400), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_PHY1_DDRPHY_FIR_REG_AND                           , RULL(0x08011401), SH_UNT_MCA_5    , SH_ACS_SCOM1_AND );
+REG64( MCA_5_PHY1_DDRPHY_FIR_REG_OR                            , RULL(0x08011402), SH_UNT_MCA_5    , SH_ACS_SCOM2_OR  );
+
+REG64( MCA_1_PHY1_DDRPHY_FIR_WOF_REG                           , RULL(0x07011408), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_5_PHY1_DDRPHY_FIR_WOF_REG                           , RULL(0x08011408), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( MCA_2_PHY2_DDRPHY_FIR_ACTION0_REG                       , RULL(0x07011806), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_PHY2_DDRPHY_FIR_ACTION0_REG                       , RULL(0x08011806), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_PHY2_DDRPHY_FIR_ACTION1_REG                       , RULL(0x07011807), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_PHY2_DDRPHY_FIR_ACTION1_REG                       , RULL(0x08011807), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_2_PHY2_DDRPHY_FIR_MASK_REG                          , RULL(0x07011803), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_PHY2_DDRPHY_FIR_MASK_REG_AND                      , RULL(0x07011804), SH_UNT_MCA_2    , SH_ACS_SCOM1_AND );
+REG64( MCA_2_PHY2_DDRPHY_FIR_MASK_REG_OR                       , RULL(0x07011805), SH_UNT_MCA_2    , SH_ACS_SCOM2_OR  );
+REG64( MCA_6_PHY2_DDRPHY_FIR_MASK_REG                          , RULL(0x08011803), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_PHY2_DDRPHY_FIR_MASK_REG_AND                      , RULL(0x08011804), SH_UNT_MCA_6    , SH_ACS_SCOM1_AND );
+REG64( MCA_6_PHY2_DDRPHY_FIR_MASK_REG_OR                       , RULL(0x08011805), SH_UNT_MCA_6    , SH_ACS_SCOM2_OR  );
+
+REG64( MCA_2_PHY2_DDRPHY_FIR_REG                               , RULL(0x07011800), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_PHY2_DDRPHY_FIR_REG_AND                           , RULL(0x07011801), SH_UNT_MCA_2    , SH_ACS_SCOM1_AND );
+REG64( MCA_2_PHY2_DDRPHY_FIR_REG_OR                            , RULL(0x07011802), SH_UNT_MCA_2    , SH_ACS_SCOM2_OR  );
+REG64( MCA_6_PHY2_DDRPHY_FIR_REG                               , RULL(0x08011800), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_PHY2_DDRPHY_FIR_REG_AND                           , RULL(0x08011801), SH_UNT_MCA_6    , SH_ACS_SCOM1_AND );
+REG64( MCA_6_PHY2_DDRPHY_FIR_REG_OR                            , RULL(0x08011802), SH_UNT_MCA_6    , SH_ACS_SCOM2_OR  );
+
+REG64( MCA_2_PHY2_DDRPHY_FIR_WOF_REG                           , RULL(0x07011808), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_6_PHY2_DDRPHY_FIR_WOF_REG                           , RULL(0x08011808), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( MCA_3_PHY3_DDRPHY_FIR_ACTION0_REG                       , RULL(0x07011C06), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_PHY3_DDRPHY_FIR_ACTION0_REG                       , RULL(0x08011C06), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_PHY3_DDRPHY_FIR_ACTION1_REG                       , RULL(0x07011C07), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_PHY3_DDRPHY_FIR_ACTION1_REG                       , RULL(0x08011C07), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_3_PHY3_DDRPHY_FIR_MASK_REG                          , RULL(0x07011C03), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_PHY3_DDRPHY_FIR_MASK_REG_AND                      , RULL(0x07011C04), SH_UNT_MCA_3    , SH_ACS_SCOM1_AND );
+REG64( MCA_3_PHY3_DDRPHY_FIR_MASK_REG_OR                       , RULL(0x07011C05), SH_UNT_MCA_3    , SH_ACS_SCOM2_OR  );
+REG64( MCA_7_PHY3_DDRPHY_FIR_MASK_REG                          , RULL(0x08011C03), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_PHY3_DDRPHY_FIR_MASK_REG_AND                      , RULL(0x08011C04), SH_UNT_MCA_7    , SH_ACS_SCOM1_AND );
+REG64( MCA_7_PHY3_DDRPHY_FIR_MASK_REG_OR                       , RULL(0x08011C05), SH_UNT_MCA_7    , SH_ACS_SCOM2_OR  );
+
+REG64( MCA_3_PHY3_DDRPHY_FIR_REG                               , RULL(0x07011C00), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_PHY3_DDRPHY_FIR_REG_AND                           , RULL(0x07011C01), SH_UNT_MCA_3    , SH_ACS_SCOM1_AND );
+REG64( MCA_3_PHY3_DDRPHY_FIR_REG_OR                            , RULL(0x07011C02), SH_UNT_MCA_3    , SH_ACS_SCOM2_OR  );
+REG64( MCA_7_PHY3_DDRPHY_FIR_REG                               , RULL(0x08011C00), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_PHY3_DDRPHY_FIR_REG_AND                           , RULL(0x08011C01), SH_UNT_MCA_7    , SH_ACS_SCOM1_AND );
+REG64( MCA_7_PHY3_DDRPHY_FIR_REG_OR                            , RULL(0x08011C02), SH_UNT_MCA_7    , SH_ACS_SCOM2_OR  );
+
+REG64( MCA_3_PHY3_DDRPHY_FIR_WOF_REG                           , RULL(0x07011C08), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_7_PHY3_DDRPHY_FIR_WOF_REG                           , RULL(0x08011C08), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( MCA_PSCOM_ERROR_MASK                                    , RULL(0x07010002), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_PSCOM_ERROR_MASK                                  , RULL(0x07010002), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+REG64( MCA_4_PSCOM_ERROR_MASK                                  , RULL(0x08010002), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCA_PSCOM_MODE_REG                                      , RULL(0x07010000), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_PSCOM_MODE_REG                                    , RULL(0x07010000), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+REG64( MCA_4_PSCOM_MODE_REG                                    , RULL(0x08010000), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCA_PSCOM_STATUS_ERROR_REG                              , RULL(0x07010001), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_PSCOM_STATUS_ERROR_REG                            , RULL(0x07010001), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+REG64( MCA_4_PSCOM_STATUS_ERROR_REG                            , RULL(0x08010001), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q                         , RULL(0x070123DD), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_RCD_LRDIM_CNTL_WORD0_15Q                       , RULL(0x070123DD), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_RCD_LRDIM_CNTL_WORD0_15Q                       , RULL(0x080123DD), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCA_RECR                                                , RULL(0x07010A0A), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_RECR                                              , RULL(0x07010A0A), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_RECR                                              , RULL(0x07010A4A), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_RECR                                              , RULL(0x07010A8A), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_RECR                                              , RULL(0x07010ACA), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_RECR                                              , RULL(0x08010A0A), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_RECR                                              , RULL(0x08010A4A), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_RECR                                              , RULL(0x08010A8A), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_RECR                                              , RULL(0x08010ACA), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_RING_FENCE_MASK_LATCH_REG                           , RULL(0x07010008), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_RING_FENCE_MASK_LATCH_REG                         , RULL(0x07010008), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+REG64( MCA_4_RING_FENCE_MASK_LATCH_REG                         , RULL(0x08010008), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCBIST_RUNTIMECTRQ                                      , RULL(0x070123B0), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_RUNTIMECTRQ                                    , RULL(0x070123B0), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_RUNTIMECTRQ                                    , RULL(0x080123B0), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCA_TCMC01_SLOW_TRA0_TRACE_HI_DATA_REG                  , RULL(0x07010400), SH_UNT_MCA      , SH_ACS_SCOM_RO   );
+REG64( MCA_0_TCMC01_SLOW_TRA0_TRACE_HI_DATA_REG                , RULL(0x07010400), SH_UNT_MCA_0    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG                  , RULL(0x07010401), SH_UNT_MCA      , SH_ACS_SCOM_RO   );
+REG64( MCA_0_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG                , RULL(0x07010401), SH_UNT_MCA_0    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG                , RULL(0x07010402), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG              , RULL(0x07010402), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+
+REG64( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_0              , RULL(0x07010403), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_0            , RULL(0x07010403), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+
+REG64( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_1              , RULL(0x07010404), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_1            , RULL(0x07010404), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+
+REG64( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_2              , RULL(0x07010405), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_2            , RULL(0x07010405), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+
+REG64( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_3              , RULL(0x07010406), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_3            , RULL(0x07010406), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+
+REG64( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_4              , RULL(0x07010407), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_4            , RULL(0x07010407), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+
+REG64( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_5              , RULL(0x07010408), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_5            , RULL(0x07010408), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+
+REG64( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9              , RULL(0x07010409), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9            , RULL(0x07010409), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+
+REG64( MCA_4_TCMC23_SLOW_TRA0_TRACE_HI_DATA_REG                , RULL(0x08010400), SH_UNT_MCA_4    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_4_TCMC23_SLOW_TRA0_TRACE_LO_DATA_REG                , RULL(0x08010401), SH_UNT_MCA_4    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_4_TCMC23_SLOW_TRA0_TRACE_TRCTRL_CONFIG              , RULL(0x08010402), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCA_4_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_0            , RULL(0x08010403), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCA_4_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_1            , RULL(0x08010404), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCA_4_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_2            , RULL(0x08010405), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCA_4_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_3            , RULL(0x08010406), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCA_4_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_4            , RULL(0x08010407), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCA_4_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_5            , RULL(0x08010408), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCA_4_TCMC23_SLOW_TRA0_TRACE_TRDATA_CONFIG_9            , RULL(0x08010409), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCBIST_WATCFG0AQ                                        , RULL(0x07012380), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG0AQ                                      , RULL(0x07012380), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG0AQ                                      , RULL(0x08012380), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG0BQ                                        , RULL(0x07012381), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG0BQ                                      , RULL(0x07012381), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG0BQ                                      , RULL(0x08012381), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG0CQ                                        , RULL(0x07012382), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG0CQ                                      , RULL(0x07012382), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG0CQ                                      , RULL(0x08012382), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG0DQ                                        , RULL(0x07012383), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG0DQ                                      , RULL(0x07012383), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG0DQ                                      , RULL(0x08012383), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG0EQ                                        , RULL(0x07012384), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG0EQ                                      , RULL(0x07012384), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG0EQ                                      , RULL(0x08012384), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG1AQ                                        , RULL(0x07012385), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG1AQ                                      , RULL(0x07012385), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG1AQ                                      , RULL(0x08012385), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG1BQ                                        , RULL(0x07012386), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG1BQ                                      , RULL(0x07012386), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG1BQ                                      , RULL(0x08012386), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG1CQ                                        , RULL(0x07012387), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG1CQ                                      , RULL(0x07012387), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG1CQ                                      , RULL(0x08012387), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG1DQ                                        , RULL(0x07012388), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG1DQ                                      , RULL(0x07012388), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG1DQ                                      , RULL(0x08012388), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG1EQ                                        , RULL(0x07012389), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG1EQ                                      , RULL(0x07012389), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG1EQ                                      , RULL(0x08012389), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG2AQ                                        , RULL(0x0701238A), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG2AQ                                      , RULL(0x0701238A), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG2AQ                                      , RULL(0x0801238A), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG2BQ                                        , RULL(0x0701238B), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG2BQ                                      , RULL(0x0701238B), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG2BQ                                      , RULL(0x0801238B), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG2CQ                                        , RULL(0x0701238C), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG2CQ                                      , RULL(0x0701238C), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG2CQ                                      , RULL(0x0801238C), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG2DQ                                        , RULL(0x0701238D), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG2DQ                                      , RULL(0x0701238D), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG2DQ                                      , RULL(0x0801238D), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG2EQ                                        , RULL(0x0701238E), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG2EQ                                      , RULL(0x0701238E), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG2EQ                                      , RULL(0x0801238E), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG3AQ                                        , RULL(0x0701238F), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG3AQ                                      , RULL(0x0701238F), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG3AQ                                      , RULL(0x0801238F), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG3BQ                                        , RULL(0x07012390), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG3BQ                                      , RULL(0x07012390), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG3BQ                                      , RULL(0x08012390), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG3CQ                                        , RULL(0x07012391), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG3CQ                                      , RULL(0x07012391), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG3CQ                                      , RULL(0x08012391), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG3DQ                                        , RULL(0x07012392), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG3DQ                                      , RULL(0x07012392), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG3DQ                                      , RULL(0x08012392), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCBIST_WATCFG3EQ                                        , RULL(0x07012393), SH_UNT_MCBIST   , SH_ACS_SCOM_RW   );
+REG64( MCBIST_0_WATCFG3EQ                                      , RULL(0x07012393), SH_UNT_MCBIST_0 , SH_ACS_SCOM_RW   );
+REG64( MCBIST_1_WATCFG3EQ                                      , RULL(0x08012393), SH_UNT_MCBIST_1 , SH_ACS_SCOM_RW   );
+
+REG64( MCA_WBMGR_TAG_INFO                                      , RULL(0x07010A33), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_WBMGR_TAG_INFO                                    , RULL(0x07010A33), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_WBMGR_TAG_INFO                                    , RULL(0x07010A73), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_WBMGR_TAG_INFO                                    , RULL(0x07010AB3), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_WBMGR_TAG_INFO                                    , RULL(0x07010AF3), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_WBMGR_TAG_INFO                                    , RULL(0x08010A33), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_WBMGR_TAG_INFO                                    , RULL(0x08010A73), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_WBMGR_TAG_INFO                                    , RULL(0x08010AB3), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_WBMGR_TAG_INFO                                    , RULL(0x08010AF3), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_WDFCFG                                              , RULL(0x07010A30), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_WDFCFG                                            , RULL(0x07010A30), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_WDFCFG                                            , RULL(0x07010A70), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_WDFCFG                                            , RULL(0x07010AB0), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_WDFCFG                                            , RULL(0x07010AF0), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_WDFCFG                                            , RULL(0x08010A30), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_WDFCFG                                            , RULL(0x08010A70), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_WDFCFG                                            , RULL(0x08010AB0), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_WDFCFG                                            , RULL(0x08010AF0), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_WDFDBG                                              , RULL(0x07010A34), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_WDFDBG                                            , RULL(0x07010A34), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_WDFDBG                                            , RULL(0x07010A74), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_WDFDBG                                            , RULL(0x07010AB4), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_WDFDBG                                            , RULL(0x07010AF4), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_WDFDBG                                            , RULL(0x08010A34), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_WDFDBG                                            , RULL(0x08010A74), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_WDFDBG                                            , RULL(0x08010AB4), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_WDFDBG                                            , RULL(0x08010AF4), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_WECR                                                , RULL(0x07010A28), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_WECR                                              , RULL(0x07010A28), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_WECR                                              , RULL(0x07010A68), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_WECR                                              , RULL(0x07010AA8), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_WECR                                              , RULL(0x07010AE8), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_WECR                                              , RULL(0x08010A28), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_WECR                                              , RULL(0x08010A68), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_WECR                                              , RULL(0x08010AA8), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_WECR                                              , RULL(0x08010AE8), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_WESR                                                , RULL(0x07010A2E), SH_UNT_MCA      , SH_ACS_SCOM_RO   );
+REG64( MCA_0_WESR                                              , RULL(0x07010A2E), SH_UNT_MCA_0    , SH_ACS_SCOM_RO   );
+REG64( MCA_1_WESR                                              , RULL(0x07010A6E), SH_UNT_MCA_1    , SH_ACS_SCOM_RO   );
+REG64( MCA_2_WESR                                              , RULL(0x07010AAE), SH_UNT_MCA_2    , SH_ACS_SCOM_RO   );
+REG64( MCA_3_WESR                                              , RULL(0x07010AEE), SH_UNT_MCA_3    , SH_ACS_SCOM_RO   );
+REG64( MCA_4_WESR                                              , RULL(0x08010A2E), SH_UNT_MCA_4    , SH_ACS_SCOM_RO   );
+REG64( MCA_5_WESR                                              , RULL(0x08010A6E), SH_UNT_MCA_5    , SH_ACS_SCOM_RO   );
+REG64( MCA_6_WESR                                              , RULL(0x08010AAE), SH_UNT_MCA_6    , SH_ACS_SCOM_RO   );
+REG64( MCA_7_WESR                                              , RULL(0x08010AEE), SH_UNT_MCA_7    , SH_ACS_SCOM_RO   );
+
+REG64( MCA_WOF                                                 , RULL(0x07010A08), SH_UNT_MCA      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_0_WOF                                               , RULL(0x07010A08), SH_UNT_MCA_0    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_1_WOF                                               , RULL(0x07010A48), SH_UNT_MCA_1    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_2_WOF                                               , RULL(0x07010A88), SH_UNT_MCA_2    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_3_WOF                                               , RULL(0x07010AC8), SH_UNT_MCA_3    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_4_WOF                                               , RULL(0x08010A08), SH_UNT_MCA_4    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_5_WOF                                               , RULL(0x08010A48), SH_UNT_MCA_5    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_6_WOF                                               , RULL(0x08010A88), SH_UNT_MCA_6    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( MCA_7_WOF                                               , RULL(0x08010AC8), SH_UNT_MCA_7    ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( MCA_WRITE_PROTECT_ENABLE_REG                            , RULL(0x07010005), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_WRITE_PROTECT_ENABLE_REG                          , RULL(0x07010005), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+REG64( MCA_4_WRITE_PROTECT_ENABLE_REG                          , RULL(0x08010005), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCA_WRITE_PROTECT_RINGS_REG                             , RULL(0x07010006), SH_UNT_MCA      , SH_ACS_SCOM      );
+REG64( MCA_0_WRITE_PROTECT_RINGS_REG                           , RULL(0x07010006), SH_UNT_MCA_0    , SH_ACS_SCOM      );
+REG64( MCA_4_WRITE_PROTECT_RINGS_REG                           , RULL(0x08010006), SH_UNT_MCA_4    , SH_ACS_SCOM      );
+
+REG64( MCA_WRTCFG                                              , RULL(0x07010A38), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_WRTCFG                                            , RULL(0x07010A38), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_WRTCFG                                            , RULL(0x07010A78), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_WRTCFG                                            , RULL(0x07010AB8), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_WRTCFG                                            , RULL(0x07010AF8), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_WRTCFG                                            , RULL(0x08010A38), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_WRTCFG                                            , RULL(0x08010A78), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_WRTCFG                                            , RULL(0x08010AB8), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_WRTCFG                                            , RULL(0x08010AF8), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_WRTDBGMCA                                           , RULL(0x07010A3A), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_WRTDBGMCA                                         , RULL(0x07010A3A), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_WRTDBGMCA                                         , RULL(0x07010A7A), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_WRTDBGMCA                                         , RULL(0x07010ABA), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_WRTDBGMCA                                         , RULL(0x07010AFA), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_WRTDBGMCA                                         , RULL(0x08010A3A), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_WRTDBGMCA                                         , RULL(0x08010A7A), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_WRTDBGMCA                                         , RULL(0x08010ABA), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_WRTDBGMCA                                         , RULL(0x08010AFA), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_WRTDBGNEST                                          , RULL(0x07010A3B), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_0_WRTDBGNEST                                        , RULL(0x07010A3B), SH_UNT_MCA_0    , SH_ACS_SCOM_RW   );
+REG64( MCA_1_WRTDBGNEST                                        , RULL(0x07010A7B), SH_UNT_MCA_1    , SH_ACS_SCOM_RW   );
+REG64( MCA_2_WRTDBGNEST                                        , RULL(0x07010ABB), SH_UNT_MCA_2    , SH_ACS_SCOM_RW   );
+REG64( MCA_3_WRTDBGNEST                                        , RULL(0x07010AFB), SH_UNT_MCA_3    , SH_ACS_SCOM_RW   );
+REG64( MCA_4_WRTDBGNEST                                        , RULL(0x08010A3B), SH_UNT_MCA_4    , SH_ACS_SCOM_RW   );
+REG64( MCA_5_WRTDBGNEST                                        , RULL(0x08010A7B), SH_UNT_MCA_5    , SH_ACS_SCOM_RW   );
+REG64( MCA_6_WRTDBGNEST                                        , RULL(0x08010ABB), SH_UNT_MCA_6    , SH_ACS_SCOM_RW   );
+REG64( MCA_7_WRTDBGNEST                                        , RULL(0x08010AFB), SH_UNT_MCA_7    , SH_ACS_SCOM_RW   );
+
+REG64( MCA_0_WREITE_WRT_ECC                                    , RULL(0x07010A39), SH_UNT_MCA_0_WREITE,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_0_WDF_WRT_ECC                                       , RULL(0x07010A31), SH_UNT_MCA_0_WDF,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_1_WREITE_WRT_ECC                                    , RULL(0x07010A79), SH_UNT_MCA_1_WREITE,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_1_WDF_WRT_ECC                                       , RULL(0x07010A71), SH_UNT_MCA_1_WDF,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_2_WDF_WRT_ECC                                       , RULL(0x07010AB1), SH_UNT_MCA_2_WDF,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_2_WREITE_WRT_ECC                                    , RULL(0x07010AB9), SH_UNT_MCA_2_WREITE,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_3_WREITE_WRT_ECC                                    , RULL(0x07010AF9), SH_UNT_MCA_3_WREITE,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_3_WDF_WRT_ECC                                       , RULL(0x07010AF1), SH_UNT_MCA_3_WDF,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_4_WREITE_WRT_ECC                                    , RULL(0x08010A39), SH_UNT_MCA_4_WREITE,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_4_WDF_WRT_ECC                                       , RULL(0x08010A31), SH_UNT_MCA_4_WDF,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_5_WREITE_WRT_ECC                                    , RULL(0x08010A79), SH_UNT_MCA_5_WREITE,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_5_WDF_WRT_ECC                                       , RULL(0x08010A71), SH_UNT_MCA_5_WDF,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_6_WREITE_WRT_ECC                                    , RULL(0x08010AB9), SH_UNT_MCA_6_WREITE,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_6_WDF_WRT_ECC                                       , RULL(0x08010AB1), SH_UNT_MCA_6_WDF,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_7_WDF_WRT_ECC                                       , RULL(0x08010AF1), SH_UNT_MCA_7_WDF,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_7_WREITE_WRT_ECC                                    , RULL(0x08010AF9), SH_UNT_MCA_7_WREITE,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_WDF_WRT_ECC                                         , RULL(0x07010A31), SH_UNT_MCA_WDF  ,
+       SH_ACS_SCOM_WCLRPART );
+REG64( MCA_WREITE_WRT_ECC                                      , RULL(0x07010A39), SH_UNT_MCA_WREITE,
+       SH_ACS_SCOM_WCLRPART );
+
+REG64( MCA_3_XTRA_TRACE_MODE                                   , RULL(0x070107D1), SH_UNT_MCA_3    , SH_ACS_SCOM      );
+REG64( MCA_7_XTRA_TRACE_MODE                                   , RULL(0x080107D1), SH_UNT_MCA_7    , SH_ACS_SCOM      );
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H
new file mode 100644
index 00000000..e1a0b264
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H
@@ -0,0 +1,1991 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_mc_scom_addresses_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file mc_scom_addresses_fixes.H
+/// @brief The *scom_addresses.H files are  generated form figtree, but
+///        the figree can be wrong.  This file is included at the end
+///        of scom_addresses.H and allows incorrect constants to be
+///        fixed manually.
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SAO
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __P9_MC_SCOM_ADDRESSES_FIXES_H
+#define __P9_MC_SCOM_ADDRESSES_FIXES_H
+
+// More of an addition than a fix.
+REG64( MCA_MBA_MCP0XLT0                                     , RULL(0x05010820), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_MBA_MCP0XLT1                                     , RULL(0x05010821), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+REG64( MCA_MBA_MCP0XLT2                                     , RULL(0x05010822), SH_UNT_MCA      , SH_ACS_SCOM_RW   );
+
+// FIXREG64( MCBIST_MCBIST_CCSARRERRINJQ                                    , RULL(0x07010FDE),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701219E) );
+// FIXREG64( MCBIST_MCBIST_0_CCSARRERRINJQ                                  , RULL(0x07010FDE),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701219E) );
+// FIXREG64( MCBIST_MCBIST_1_CCSARRERRINJQ                                  , RULL(0x08010FDE),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801219E) );
+// FIXREG64( MCBIST_MCBIST_CCS_CNTLQ                                        , RULL(0x07010FA5),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012165) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_CNTLQ                                      , RULL(0x07010FA5),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012165) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_CNTLQ                                      , RULL(0x08010FA5),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012165) );
+// FIXREG64( MCBIST_MCBIST_CCS_FIXED_DATA0Q                                 , RULL(0x07010FE5),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070121A5) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_FIXED_DATA0Q                               , RULL(0x07010FE5),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070121A5) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_FIXED_DATA0Q                               , RULL(0x08010FE5),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080121A5) );
+// FIXREG64( MCBIST_MCBIST_CCS_FIXED_DATA1Q                                 , RULL(0x07010FE6),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070121A6) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_FIXED_DATA1Q                               , RULL(0x07010FE6),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070121A6) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_FIXED_DATA1Q                               , RULL(0x08010FE6),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080121A6) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_00                                 , RULL(0x07010F15),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120D5) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_00                               , RULL(0x07010F15),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120D5) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_00                               , RULL(0x08010F15),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120D5) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_01                                 , RULL(0x07010F16),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120D6) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_01                               , RULL(0x07010F16),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120D6) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_01                               , RULL(0x08010F16),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120D6) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_02                                 , RULL(0x07010F17),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120D7) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_02                               , RULL(0x07010F17),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120D7) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_02                               , RULL(0x08010F17),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120D7) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_03                                 , RULL(0x07010F18),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120D8) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_03                               , RULL(0x07010F18),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120D8) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_03                               , RULL(0x08010F18),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120D8) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_04                                 , RULL(0x07010F19),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120D9) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_04                               , RULL(0x07010F19),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120D9) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_04                               , RULL(0x08010F19),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120D9) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_05                                 , RULL(0x07010F1A),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120DA) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_05                               , RULL(0x07010F1A),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120DA) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_05                               , RULL(0x08010F1A),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120DA) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_06                                 , RULL(0x07010F1B),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120DB) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_06                               , RULL(0x07010F1B),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120DB) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_06                               , RULL(0x08010F1B),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120DB) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_07                                 , RULL(0x07010F1C),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120DC) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_07                               , RULL(0x07010F1C),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120DC) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_07                               , RULL(0x08010F1C),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120DC) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_08                                 , RULL(0x07010F1D),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120DD) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_08                               , RULL(0x07010F1D),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120DD) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_08                               , RULL(0x08010F1D),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120DD) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_09                                 , RULL(0x07010F1E),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120DE) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_09                               , RULL(0x07010F1E),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120DE) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_09                               , RULL(0x08010F1E),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120DE) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_10                                 , RULL(0x07010F1F),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120DF) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_10                               , RULL(0x07010F1F),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120DF) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_10                               , RULL(0x08010F1F),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120DF) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_11                                 , RULL(0x07010F20),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E0) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_11                               , RULL(0x07010F20),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E0) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_11                               , RULL(0x08010F20),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120E0) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_12                                 , RULL(0x07010F21),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E1) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_12                               , RULL(0x07010F21),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E1) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_12                               , RULL(0x08010F21),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120E1) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_13                                 , RULL(0x07010F22),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E2) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_13                               , RULL(0x07010F22),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E2) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_13                               , RULL(0x08010F22),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120E2) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_14                                 , RULL(0x07010F23),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E3) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_14                               , RULL(0x07010F23),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E3) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_14                               , RULL(0x08010F23),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120E3) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_15                                 , RULL(0x07010F24),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E4) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_15                               , RULL(0x07010F24),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E4) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_15                               , RULL(0x08010F24),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120E4) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_16                                 , RULL(0x07010F25),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E5) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_16                               , RULL(0x07010F25),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E5) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_16                               , RULL(0x08010F25),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120E5) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_17                                 , RULL(0x07010F26),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E6) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_17                               , RULL(0x07010F26),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E6) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_17                               , RULL(0x08010F26),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120E6) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_18                                 , RULL(0x07010F27),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E7) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_18                               , RULL(0x07010F27),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E7) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_18                               , RULL(0x08010F27),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120E7) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_19                                 , RULL(0x07010F28),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E8) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_19                               , RULL(0x07010F28),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E8) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_19                               , RULL(0x08010F28),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120E8) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_20                                 , RULL(0x07010F29),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E9) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_20                               , RULL(0x07010F29),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120E9) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_20                               , RULL(0x08010F29),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120E9) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_21                                 , RULL(0x07010F2A),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120EA) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_21                               , RULL(0x07010F2A),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120EA) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_21                               , RULL(0x08010F2A),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120EA) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_22                                 , RULL(0x07010F2B),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120EB) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_22                               , RULL(0x07010F2B),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120EB) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_22                               , RULL(0x08010F2B),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120EB) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_23                                 , RULL(0x07010F2C),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120EC) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_23                               , RULL(0x07010F2C),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120EC) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_23                               , RULL(0x08010F2C),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120EC) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_24                                 , RULL(0x07010F2D),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120ED) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_24                               , RULL(0x07010F2D),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120ED) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_24                               , RULL(0x08010F2D),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120ED) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_25                                 , RULL(0x07010F2E),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120EE) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_25                               , RULL(0x07010F2E),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120EE) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_25                               , RULL(0x08010F2E),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120EE) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_26                                 , RULL(0x07010F2F),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120EF) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_26                               , RULL(0x07010F2F),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120EF) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_26                               , RULL(0x08010F2F),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120EF) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_27                                 , RULL(0x07010F30),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F0) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_27                               , RULL(0x07010F30),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F0) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_27                               , RULL(0x08010F30),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120F0) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_28                                 , RULL(0x07010F31),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F1) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_28                               , RULL(0x07010F31),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F1) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_28                               , RULL(0x08010F31),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120F1) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_29                                 , RULL(0x07010F32),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F2) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_29                               , RULL(0x07010F32),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F2) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_29                               , RULL(0x08010F32),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120F2) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_30                                 , RULL(0x07010F33),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F3) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_30                               , RULL(0x07010F33),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F3) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_30                               , RULL(0x08010F33),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120F3) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR0_31                                 , RULL(0x07010F34),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F4) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR0_31                               , RULL(0x07010F34),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F4) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR0_31                               , RULL(0x08010F34),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120F4) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_00                                 , RULL(0x07010F35),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F5) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_00                               , RULL(0x07010F35),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F5) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_00                               , RULL(0x08010F35),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120F5) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_01                                 , RULL(0x07010F36),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F6) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_01                               , RULL(0x07010F36),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F6) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_01                               , RULL(0x08010F36),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120F6) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_02                                 , RULL(0x07010F37),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F7) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_02                               , RULL(0x07010F37),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F7) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_02                               , RULL(0x08010F37),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120F7) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_03                                 , RULL(0x07010F38),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F8) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_03                               , RULL(0x07010F38),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F8) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_03                               , RULL(0x08010F38),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120F8) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_04                                 , RULL(0x07010F39),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F9) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_04                               , RULL(0x07010F39),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120F9) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_04                               , RULL(0x08010F39),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120F9) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_05                                 , RULL(0x07010F3A),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120FA) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_05                               , RULL(0x07010F3A),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120FA) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_05                               , RULL(0x08010F3A),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120FA) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_06                                 , RULL(0x07010F3B),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120FB) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_06                               , RULL(0x07010F3B),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120FB) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_06                               , RULL(0x08010F3B),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120FB) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_07                                 , RULL(0x07010F3C),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120FC) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_07                               , RULL(0x07010F3C),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120FC) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_07                               , RULL(0x08010F3C),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120FC) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_08                                 , RULL(0x07010F3D),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120FD) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_08                               , RULL(0x07010F3D),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120FD) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_08                               , RULL(0x08010F3D),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120FD) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_09                                 , RULL(0x07010F3E),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120FE) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_09                               , RULL(0x07010F3E),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120FE) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_09                               , RULL(0x08010F3E),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120FE) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_10                                 , RULL(0x07010F3F),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120FF) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_10                               , RULL(0x07010F3F),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120FF) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_10                               , RULL(0x08010F3F),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120FF) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_11                                 , RULL(0x07010F40),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012100) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_11                               , RULL(0x07010F40),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012100) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_11                               , RULL(0x08010F40),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012100) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_12                                 , RULL(0x07010F41),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012101) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_12                               , RULL(0x07010F41),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012101) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_12                               , RULL(0x08010F41),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012101) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_13                                 , RULL(0x07010F42),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012102) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_13                               , RULL(0x07010F42),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012102) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_13                               , RULL(0x08010F42),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012102) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_14                                 , RULL(0x07010F43),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012103) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_14                               , RULL(0x07010F43),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012103) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_14                               , RULL(0x08010F43),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012103) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_15                                 , RULL(0x07010F44),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012104) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_15                               , RULL(0x07010F44),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012104) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_15                               , RULL(0x08010F44),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012104) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_16                                 , RULL(0x07010F45),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012105) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_16                               , RULL(0x07010F45),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012105) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_16                               , RULL(0x08010F45),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012105) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_17                                 , RULL(0x07010F46),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012106) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_17                               , RULL(0x07010F46),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012106) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_17                               , RULL(0x08010F46),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012106) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_18                                 , RULL(0x07010F47),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012107) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_18                               , RULL(0x07010F47),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012107) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_18                               , RULL(0x08010F47),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012107) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_19                                 , RULL(0x07010F48),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012108) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_19                               , RULL(0x07010F48),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012108) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_19                               , RULL(0x08010F48),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012108) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_20                                 , RULL(0x07010F49),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012109) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_20                               , RULL(0x07010F49),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012109) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_20                               , RULL(0x08010F49),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012109) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_21                                 , RULL(0x07010F4A),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701210A) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_21                               , RULL(0x07010F4A),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701210A) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_21                               , RULL(0x08010F4A),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801210A) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_22                                 , RULL(0x07010F4B),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701210B) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_22                               , RULL(0x07010F4B),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701210B) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_22                               , RULL(0x08010F4B),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801210B) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_23                                 , RULL(0x07010F4C),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701210C) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_23                               , RULL(0x07010F4C),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701210C) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_23                               , RULL(0x08010F4C),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801210C) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_24                                 , RULL(0x07010F4D),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701210D) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_24                               , RULL(0x07010F4D),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701210D) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_24                               , RULL(0x08010F4D),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801210D) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_25                                 , RULL(0x07010F4E),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701210E) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_25                               , RULL(0x07010F4E),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701210E) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_25                               , RULL(0x08010F4E),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801210E) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_26                                 , RULL(0x07010F4F),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701210F) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_26                               , RULL(0x07010F4F),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701210F) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_26                               , RULL(0x08010F4F),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801210F) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_27                                 , RULL(0x07010F50),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012110) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_27                               , RULL(0x07010F50),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012110) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_27                               , RULL(0x08010F50),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012110) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_28                                 , RULL(0x07010F51),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012111) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_28                               , RULL(0x07010F51),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012111) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_28                               , RULL(0x08010F51),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012111) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_29                                 , RULL(0x07010F52),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012112) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_29                               , RULL(0x07010F52),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012112) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_29                               , RULL(0x08010F52),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012112) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_30                                 , RULL(0x07010F53),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012113) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_30                               , RULL(0x07010F53),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012113) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_30                               , RULL(0x08010F53),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012113) );
+// FIXREG64( MCBIST_MCBIST_CCS_INST_ARR1_31                                 , RULL(0x07010F54),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012114) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_INST_ARR1_31                               , RULL(0x07010F54),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012114) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_INST_ARR1_31                               , RULL(0x08010F54),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012114) );
+// FIXREG64( MCBIST_MCBIST_CCS_MODEQ                                        , RULL(0x07010FA7),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012167) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_MODEQ                                      , RULL(0x07010FA7),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012167) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_MODEQ                                      , RULL(0x08010FA7),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012167) );
+// FIXREG64( MCBIST_MCBIST_CCS_STATQ                                        , RULL(0x07010FA6),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012166) );
+// FIXREG64( MCBIST_MCBIST_0_CCS_STATQ                                      , RULL(0x07010FA6),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012166) );
+// FIXREG64( MCBIST_MCBIST_1_CCS_STATQ                                      , RULL(0x08010FA6),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012166) );
+// FIXREG64( MCBIST_MCBIST_MBAUER0Q                                         , RULL(0x07010F6E),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701212E) );
+// FIXREG64( MCBIST_MCBIST_0_MBAUER0Q                                       , RULL(0x07010F6E),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701212E) );
+// FIXREG64( MCBIST_MCBIST_1_MBAUER0Q                                       , RULL(0x08010F6E),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801212E) );
+// FIXREG64( MCBIST_MCBIST_MBAUER1Q                                         , RULL(0x07010F73),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012133) );
+// FIXREG64( MCBIST_MCBIST_0_MBAUER1Q                                       , RULL(0x07010F73),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012133) );
+// FIXREG64( MCBIST_MCBIST_1_MBAUER1Q                                       , RULL(0x08010F73),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012133) );
+// FIXREG64( MCBIST_MCBIST_MBAUER2Q                                         , RULL(0x07010F78),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012138) );
+// FIXREG64( MCBIST_MCBIST_0_MBAUER2Q                                       , RULL(0x07010F78),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012138) );
+// FIXREG64( MCBIST_MCBIST_1_MBAUER2Q                                       , RULL(0x08010F78),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012138) );
+// FIXREG64( MCBIST_MCBIST_MBAUER3Q                                         , RULL(0x07010F7D),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701213D) );
+// FIXREG64( MCBIST_MCBIST_0_MBAUER3Q                                       , RULL(0x07010F7D),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701213D) );
+// FIXREG64( MCBIST_MCBIST_1_MBAUER3Q                                       , RULL(0x08010F7D),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801213D) );
+// FIXREG64( MCBIST_MCBIST_MBA_MCBERRPTQ                                    , RULL(0x07010FE7),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RO   , RULL(0x070121A7) );
+// FIXREG64( MCBIST_MCBIST_0_MBA_MCBERRPTQ                                  , RULL(0x07010FE7),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RO   , RULL(0x070121A7) );
+// FIXREG64( MCBIST_MCBIST_1_MBA_MCBERRPTQ                                  , RULL(0x08010FE7),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RO   , RULL(0x080121A7) );
+// FIXREG64( MCBIST_MCBIST_MBECTLQ                                          , RULL(0x07010F10),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120D0) );
+// FIXREG64( MCBIST_MCBIST_0_MBECTLQ                                        , RULL(0x07010F10),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120D0) );
+// FIXREG64( MCBIST_MCBIST_1_MBECTLQ                                        , RULL(0x08010F10),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120D0) );
+// FIXREG64( MCBIST_MCBIST_MBMPER0Q                                         , RULL(0x07010F6C),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701212C) );
+// FIXREG64( MCBIST_MCBIST_0_MBMPER0Q                                       , RULL(0x07010F6C),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701212C) );
+// FIXREG64( MCBIST_MCBIST_1_MBMPER0Q                                       , RULL(0x08010F6C),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801212C) );
+// FIXREG64( MCBIST_MCBIST_MBMPER1Q                                         , RULL(0x07010F71),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012131) );
+// FIXREG64( MCBIST_MCBIST_0_MBMPER1Q                                       , RULL(0x07010F71),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012131) );
+// FIXREG64( MCBIST_MCBIST_1_MBMPER1Q                                       , RULL(0x08010F71),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012131) );
+// FIXREG64( MCBIST_MCBIST_MBMPER2Q                                         , RULL(0x07010F76),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012136) );
+// FIXREG64( MCBIST_MCBIST_0_MBMPER2Q                                       , RULL(0x07010F76),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012136) );
+// FIXREG64( MCBIST_MCBIST_1_MBMPER2Q                                       , RULL(0x08010F76),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012136) );
+// FIXREG64( MCBIST_MCBIST_MBMPER3Q                                         , RULL(0x07010F7B),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701213B) );
+// FIXREG64( MCBIST_MCBIST_0_MBMPER3Q                                       , RULL(0x07010F7B),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701213B) );
+// FIXREG64( MCBIST_MCBIST_1_MBMPER3Q                                       , RULL(0x08010F7B),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801213B) );
+// FIXREG64( MCBIST_MCBIST_MBNCER0Q                                         , RULL(0x07010F6A),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701212A) );
+// FIXREG64( MCBIST_MCBIST_0_MBNCER0Q                                       , RULL(0x07010F6A),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701212A) );
+// FIXREG64( MCBIST_MCBIST_1_MBNCER0Q                                       , RULL(0x08010F6A),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801212A) );
+// FIXREG64( MCBIST_MCBIST_MBNCER1Q                                         , RULL(0x07010F6F),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701212F) );
+// FIXREG64( MCBIST_MCBIST_0_MBNCER1Q                                       , RULL(0x07010F6F),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701212F) );
+// FIXREG64( MCBIST_MCBIST_1_MBNCER1Q                                       , RULL(0x08010F6F),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801212F) );
+// FIXREG64( MCBIST_MCBIST_MBNCER2Q                                         , RULL(0x07010F74),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012134) );
+// FIXREG64( MCBIST_MCBIST_0_MBNCER2Q                                       , RULL(0x07010F74),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012134) );
+// FIXREG64( MCBIST_MCBIST_1_MBNCER2Q                                       , RULL(0x08010F74),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012134) );
+// FIXREG64( MCBIST_MCBIST_MBNCER3Q                                         , RULL(0x07010F79),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012139) );
+// FIXREG64( MCBIST_MCBIST_0_MBNCER3Q                                       , RULL(0x07010F79),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012139) );
+// FIXREG64( MCBIST_MCBIST_1_MBNCER3Q                                       , RULL(0x08010F79),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012139) );
+// FIXREG64( MCBIST_MCBIST_MBRCER0Q                                         , RULL(0x07010F6B),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701212B) );
+// FIXREG64( MCBIST_MCBIST_0_MBRCER0Q                                       , RULL(0x07010F6B),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701212B) );
+// FIXREG64( MCBIST_MCBIST_1_MBRCER0Q                                       , RULL(0x08010F6B),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801212B) );
+// FIXREG64( MCBIST_MCBIST_MBRCER1Q                                         , RULL(0x07010F70),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012130) );
+// FIXREG64( MCBIST_MCBIST_0_MBRCER1Q                                       , RULL(0x07010F70),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012130) );
+// FIXREG64( MCBIST_MCBIST_1_MBRCER1Q                                       , RULL(0x08010F70),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012130) );
+// FIXREG64( MCBIST_MCBIST_MBRCER2Q                                         , RULL(0x07010F75),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012135) );
+// FIXREG64( MCBIST_MCBIST_0_MBRCER2Q                                       , RULL(0x07010F75),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012135) );
+// FIXREG64( MCBIST_MCBIST_1_MBRCER2Q                                       , RULL(0x08010F75),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012135) );
+// FIXREG64( MCBIST_MCBIST_MBRCER3Q                                         , RULL(0x07010F7A),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701213A) );
+// FIXREG64( MCBIST_MCBIST_0_MBRCER3Q                                       , RULL(0x07010F7A),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701213A) );
+// FIXREG64( MCBIST_MCBIST_1_MBRCER3Q                                       , RULL(0x08010F7A),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801213A) );
+// FIXREG64( MCBIST_MCBIST_MBSEC0Q                                          , RULL(0x07010F55),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012115) );
+// FIXREG64( MCBIST_MCBIST_0_MBSEC0Q                                        , RULL(0x07010F55),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012115) );
+// FIXREG64( MCBIST_MCBIST_1_MBSEC0Q                                        , RULL(0x08010F55),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012115) );
+// FIXREG64( MCBIST_MCBIST_MBSEC1Q                                          , RULL(0x07010F56),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012116) );
+// FIXREG64( MCBIST_MCBIST_0_MBSEC1Q                                        , RULL(0x07010F56),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012116) );
+// FIXREG64( MCBIST_MCBIST_1_MBSEC1Q                                        , RULL(0x08010F56),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012116) );
+// FIXREG64( MCBIST_MCBIST_MBSEVR0Q                                         , RULL(0x07010F7E),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701213E) );
+// FIXREG64( MCBIST_MCBIST_0_MBSEVR0Q                                       , RULL(0x07010F7E),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701213E) );
+// FIXREG64( MCBIST_MCBIST_1_MBSEVR0Q                                       , RULL(0x08010F7E),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801213E) );
+// FIXREG64( MCBIST_MCBIST_MBSEVR1Q                                         , RULL(0x07010F7F),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701213F) );
+// FIXREG64( MCBIST_MCBIST_0_MBSEVR1Q                                       , RULL(0x07010F7F),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701213F) );
+// FIXREG64( MCBIST_MCBIST_1_MBSEVR1Q                                       , RULL(0x08010F7F),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801213F) );
+// FIXREG64( MCBIST_MCBIST_MBSMODESQ                                        , RULL(0x07010F62),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012122) );
+// FIXREG64( MCBIST_MCBIST_0_MBSMODESQ                                      , RULL(0x07010F62),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012122) );
+// FIXREG64( MCBIST_MCBIST_1_MBSMODESQ                                      , RULL(0x08010F62),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012122) );
+// FIXREG64( MCBIST_MCBIST_MBSMSECQ                                         , RULL(0x07010F69),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012129) );
+// FIXREG64( MCBIST_MCBIST_0_MBSMSECQ                                       , RULL(0x07010F69),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012129) );
+// FIXREG64( MCBIST_MCBIST_1_MBSMSECQ                                       , RULL(0x08010F69),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012129) );
+// FIXREG64( MCBIST_MCBIST_MBSSYMEC0Q                                       , RULL(0x07010F58),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012118) );
+// FIXREG64( MCBIST_MCBIST_0_MBSSYMEC0Q                                     , RULL(0x07010F58),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012118) );
+// FIXREG64( MCBIST_MCBIST_1_MBSSYMEC0Q                                     , RULL(0x08010F58),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012118) );
+// FIXREG64( MCBIST_MCBIST_MBSSYMEC1Q                                       , RULL(0x07010F59),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012119) );
+// FIXREG64( MCBIST_MCBIST_0_MBSSYMEC1Q                                     , RULL(0x07010F59),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012119) );
+// FIXREG64( MCBIST_MCBIST_1_MBSSYMEC1Q                                     , RULL(0x08010F59),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012119) );
+// FIXREG64( MCBIST_MCBIST_MBSSYMEC2Q                                       , RULL(0x07010F5A),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701211A) );
+// FIXREG64( MCBIST_MCBIST_0_MBSSYMEC2Q                                     , RULL(0x07010F5A),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701211A) );
+// FIXREG64( MCBIST_MCBIST_1_MBSSYMEC2Q                                     , RULL(0x08010F5A),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801211A) );
+// FIXREG64( MCBIST_MCBIST_MBSSYMEC3Q                                       , RULL(0x07010F5B),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701211B) );
+// FIXREG64( MCBIST_MCBIST_0_MBSSYMEC3Q                                     , RULL(0x07010F5B),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701211B) );
+// FIXREG64( MCBIST_MCBIST_1_MBSSYMEC3Q                                     , RULL(0x08010F5B),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801211B) );
+// FIXREG64( MCBIST_MCBIST_MBSSYMEC4Q                                       , RULL(0x07010F5C),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701211C) );
+// FIXREG64( MCBIST_MCBIST_0_MBSSYMEC4Q                                     , RULL(0x07010F5C),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701211C) );
+// FIXREG64( MCBIST_MCBIST_1_MBSSYMEC4Q                                     , RULL(0x08010F5C),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801211C) );
+// FIXREG64( MCBIST_MCBIST_MBSSYMEC5Q                                       , RULL(0x07010F5D),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701211D) );
+// FIXREG64( MCBIST_MCBIST_0_MBSSYMEC5Q                                     , RULL(0x07010F5D),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701211D) );
+// FIXREG64( MCBIST_MCBIST_1_MBSSYMEC5Q                                     , RULL(0x08010F5D),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801211D) );
+// FIXREG64( MCBIST_MCBIST_MBSSYMEC6Q                                       , RULL(0x07010F5E),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701211E) );
+// FIXREG64( MCBIST_MCBIST_0_MBSSYMEC6Q                                     , RULL(0x07010F5E),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701211E) );
+// FIXREG64( MCBIST_MCBIST_1_MBSSYMEC6Q                                     , RULL(0x08010F5E),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801211E) );
+// FIXREG64( MCBIST_MCBIST_MBSSYMEC7Q                                       , RULL(0x07010F5F),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701211F) );
+// FIXREG64( MCBIST_MCBIST_0_MBSSYMEC7Q                                     , RULL(0x07010F5F),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701211F) );
+// FIXREG64( MCBIST_MCBIST_1_MBSSYMEC7Q                                     , RULL(0x08010F5F),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801211F) );
+// FIXREG64( MCBIST_MCBIST_MBSSYMEC8Q                                       , RULL(0x07010F60),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012120) );
+// FIXREG64( MCBIST_MCBIST_0_MBSSYMEC8Q                                     , RULL(0x07010F60),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012120) );
+// FIXREG64( MCBIST_MCBIST_1_MBSSYMEC8Q                                     , RULL(0x08010F60),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012120) );
+// FIXREG64( MCBIST_MCBIST_MBSTRQ                                           , RULL(0x07010F57),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012117) );
+// FIXREG64( MCBIST_MCBIST_0_MBSTRQ                                         , RULL(0x07010F57),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012117) );
+// FIXREG64( MCBIST_MCBIST_1_MBSTRQ                                         , RULL(0x08010F57),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012117) );
+// FIXREG64( MCBIST_MCBIST_MBUER0Q                                          , RULL(0x07010F6D),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701212D) );
+// FIXREG64( MCBIST_MCBIST_0_MBUER0Q                                        , RULL(0x07010F6D),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701212D) );
+// FIXREG64( MCBIST_MCBIST_1_MBUER0Q                                        , RULL(0x08010F6D),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801212D) );
+// FIXREG64( MCBIST_MCBIST_MBUER1Q                                          , RULL(0x07010F72),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012132) );
+// FIXREG64( MCBIST_MCBIST_0_MBUER1Q                                        , RULL(0x07010F72),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012132) );
+// FIXREG64( MCBIST_MCBIST_1_MBUER1Q                                        , RULL(0x08010F72),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012132) );
+// FIXREG64( MCBIST_MCBIST_MBUER2Q                                          , RULL(0x07010F77),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012137) );
+// FIXREG64( MCBIST_MCBIST_0_MBUER2Q                                        , RULL(0x07010F77),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012137) );
+// FIXREG64( MCBIST_MCBIST_1_MBUER2Q                                        , RULL(0x08010F77),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012137) );
+// FIXREG64( MCBIST_MCBIST_MBUER3Q                                          , RULL(0x07010F7C),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701213C) );
+// FIXREG64( MCBIST_MCBIST_0_MBUER3Q                                        , RULL(0x07010F7C),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701213C) );
+// FIXREG64( MCBIST_MCBIST_1_MBUER3Q                                        , RULL(0x08010F7C),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801213C) );
+// FIXREG64( MCBIST_MCBIST_MCBACQ                                           , RULL(0x07010FD5),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012195) );
+// FIXREG64( MCBIST_MCBIST_0_MCBACQ                                         , RULL(0x07010FD5),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012195) );
+// FIXREG64( MCBIST_MCBIST_1_MCBACQ                                         , RULL(0x08010FD5),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012195) );
+// FIXREG64( MCBIST_MCBIST_MCBAGRAQ                                         , RULL(0x07010FD6),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012196) );
+// FIXREG64( MCBIST_MCBIST_0_MCBAGRAQ                                       , RULL(0x07010FD6),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012196) );
+// FIXREG64( MCBIST_MCBIST_1_MCBAGRAQ                                       , RULL(0x08010FD6),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012196) );
+// FIXREG64( MCBIST_MCBIST_MCBAMR0A0Q                                       , RULL(0x07010FC8),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012188) );
+// FIXREG64( MCBIST_MCBIST_0_MCBAMR0A0Q                                     , RULL(0x07010FC8),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012188) );
+// FIXREG64( MCBIST_MCBIST_1_MCBAMR0A0Q                                     , RULL(0x08010FC8),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012188) );
+// FIXREG64( MCBIST_MCBIST_MCBAMR1A0Q                                       , RULL(0x07010FC9),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012189) );
+// FIXREG64( MCBIST_MCBIST_0_MCBAMR1A0Q                                     , RULL(0x07010FC9),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012189) );
+// FIXREG64( MCBIST_MCBIST_1_MCBAMR1A0Q                                     , RULL(0x08010FC9),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012189) );
+// FIXREG64( MCBIST_MCBIST_MCBAMR2A0Q                                       , RULL(0x07010FCA),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701218A) );
+// FIXREG64( MCBIST_MCBIST_0_MCBAMR2A0Q                                     , RULL(0x07010FCA),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701218A) );
+// FIXREG64( MCBIST_MCBIST_1_MCBAMR2A0Q                                     , RULL(0x08010FCA),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801218A) );
+// FIXREG64( MCBIST_MCBIST_MCBAMR3A0Q                                       , RULL(0x07010FCB),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701218B) );
+// FIXREG64( MCBIST_MCBIST_0_MCBAMR3A0Q                                     , RULL(0x07010FCB),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701218B) );
+// FIXREG64( MCBIST_MCBIST_1_MCBAMR3A0Q                                     , RULL(0x08010FCB),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801218B) );
+// FIXREG64( MCBIST_MCBIST_MCBCFGQ                                          , RULL(0x07010FE0),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070121A0) );
+// FIXREG64( MCBIST_MCBIST_0_MCBCFGQ                                        , RULL(0x07010FE0),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070121A0) );
+// FIXREG64( MCBIST_MCBIST_1_MCBCFGQ                                        , RULL(0x08010FE0),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080121A0) );
+// FIXREG64( MCBIST_MCBIST_MCBDRCRQ                                         , RULL(0x07010FBD),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701217D) );
+// FIXREG64( MCBIST_MCBIST_0_MCBDRCRQ                                       , RULL(0x07010FBD),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701217D) );
+// FIXREG64( MCBIST_MCBIST_1_MCBDRCRQ                                       , RULL(0x08010FBD),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801217D) );
+// FIXREG64( MCBIST_MCBIST_MCBDRSRQ                                         , RULL(0x07010FBC),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701217C) );
+// FIXREG64( MCBIST_MCBIST_0_MCBDRSRQ                                       , RULL(0x07010FBC),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701217C) );
+// FIXREG64( MCBIST_MCBIST_1_MCBDRSRQ                                       , RULL(0x08010FBC),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801217C) );
+// FIXREG64( MCBIST_MCBIST_MCBEA0Q                                          , RULL(0x07010FCE),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701218E) );
+// FIXREG64( MCBIST_MCBIST_0_MCBEA0Q                                        , RULL(0x07010FCE),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701218E) );
+// FIXREG64( MCBIST_MCBIST_1_MCBEA0Q                                        , RULL(0x08010FCE),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801218E) );
+// FIXREG64( MCBIST_MCBIST_MCBEA1Q                                          , RULL(0x07010FCF),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701218F) );
+// FIXREG64( MCBIST_MCBIST_0_MCBEA1Q                                        , RULL(0x07010FCF),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701218F) );
+// FIXREG64( MCBIST_MCBIST_1_MCBEA1Q                                        , RULL(0x08010FCF),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801218F) );
+// FIXREG64( MCBIST_MCBIST_MCBEA2Q                                          , RULL(0x07010FD2),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012192) );
+// FIXREG64( MCBIST_MCBIST_0_MCBEA2Q                                        , RULL(0x07010FD2),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012192) );
+// FIXREG64( MCBIST_MCBIST_1_MCBEA2Q                                        , RULL(0x08010FD2),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012192) );
+// FIXREG64( MCBIST_MCBIST_MCBEA3Q                                          , RULL(0x07010FD3),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012193) );
+// FIXREG64( MCBIST_MCBIST_0_MCBEA3Q                                        , RULL(0x07010FD3),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012193) );
+// FIXREG64( MCBIST_MCBIST_1_MCBEA3Q                                        , RULL(0x08010FD3),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012193) );
+// FIXREG64( MCBIST_MCBIST_MCBFD0Q                                          , RULL(0x07010FBE),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701217E) );
+// FIXREG64( MCBIST_MCBIST_0_MCBFD0Q                                        , RULL(0x07010FBE),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701217E) );
+// FIXREG64( MCBIST_MCBIST_1_MCBFD0Q                                        , RULL(0x08010FBE),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801217E) );
+// FIXREG64( MCBIST_MCBIST_MCBFD1Q                                          , RULL(0x07010FBF),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701217F) );
+// FIXREG64( MCBIST_MCBIST_0_MCBFD1Q                                        , RULL(0x07010FBF),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701217F) );
+// FIXREG64( MCBIST_MCBIST_1_MCBFD1Q                                        , RULL(0x08010FBF),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801217F) );
+// FIXREG64( MCBIST_MCBIST_MCBFD2Q                                          , RULL(0x07010FC0),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012180) );
+// FIXREG64( MCBIST_MCBIST_0_MCBFD2Q                                        , RULL(0x07010FC0),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012180) );
+// FIXREG64( MCBIST_MCBIST_1_MCBFD2Q                                        , RULL(0x08010FC0),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012180) );
+// FIXREG64( MCBIST_MCBIST_MCBFD3Q                                          , RULL(0x07010FC1),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012181) );
+// FIXREG64( MCBIST_MCBIST_0_MCBFD3Q                                        , RULL(0x07010FC1),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012181) );
+// FIXREG64( MCBIST_MCBIST_1_MCBFD3Q                                        , RULL(0x08010FC1),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012181) );
+// FIXREG64( MCBIST_MCBIST_MCBFD4Q                                          , RULL(0x07010FC2),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012182) );
+// FIXREG64( MCBIST_MCBIST_0_MCBFD4Q                                        , RULL(0x07010FC2),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012182) );
+// FIXREG64( MCBIST_MCBIST_1_MCBFD4Q                                        , RULL(0x08010FC2),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012182) );
+// FIXREG64( MCBIST_MCBIST_MCBFD5Q                                          , RULL(0x07010FC3),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012183) );
+// FIXREG64( MCBIST_MCBIST_0_MCBFD5Q                                        , RULL(0x07010FC3),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012183) );
+// FIXREG64( MCBIST_MCBIST_1_MCBFD5Q                                        , RULL(0x08010FC3),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012183) );
+// FIXREG64( MCBIST_MCBIST_MCBFD6Q                                          , RULL(0x07010FC4),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012184) );
+// FIXREG64( MCBIST_MCBIST_0_MCBFD6Q                                        , RULL(0x07010FC4),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012184) );
+// FIXREG64( MCBIST_MCBIST_1_MCBFD6Q                                        , RULL(0x08010FC4),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012184) );
+// FIXREG64( MCBIST_MCBIST_MCBFD7Q                                          , RULL(0x07010FC5),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012185) );
+// FIXREG64( MCBIST_MCBIST_0_MCBFD7Q                                        , RULL(0x07010FC5),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012185) );
+// FIXREG64( MCBIST_MCBIST_1_MCBFD7Q                                        , RULL(0x08010FC5),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012185) );
+// FIXREG64( MCBIST_MCBIST_MCBFDQ                                           , RULL(0x07010FC6),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012186) );
+// FIXREG64( MCBIST_MCBIST_0_MCBFDQ                                         , RULL(0x07010FC6),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012186) );
+// FIXREG64( MCBIST_MCBIST_1_MCBFDQ                                         , RULL(0x08010FC6),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012186) );
+// FIXREG64( MCBIST_MCBIST_MCBISTFIRACT0                                    , RULL(0x07010F06),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120C6) );
+// FIXREG64( MCBIST_MCBIST_0_MCBISTFIRACT0                                  , RULL(0x07010F06),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120C6) );
+// FIXREG64( MCBIST_MCBIST_1_MCBISTFIRACT0                                  , RULL(0x08010F06),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120C6) );
+// FIXREG64( MCBIST_MCBIST_MCBISTFIRACT1                                    , RULL(0x07010F07),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120C7) );
+// FIXREG64( MCBIST_MCBIST_0_MCBISTFIRACT1                                  , RULL(0x07010F07),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120C7) );
+// FIXREG64( MCBIST_MCBIST_1_MCBISTFIRACT1                                  , RULL(0x08010F07),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120C7) );
+// FIXREG64( MCBIST_MCBIST_MCBISTFIRMASK                                    , RULL(0x07010F03),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120C3) );
+// FIXREG64( MCBIST_MCBIST_MCBISTFIRMASK_AND                                , RULL(0x07010F04),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM1_AND , RULL(0x070120C4) );
+// FIXREG64( MCBIST_MCBIST_MCBISTFIRMASK_OR                                 , RULL(0x07010F05),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM2_OR  , RULL(0x070120C5) );
+// FIXREG64( MCBIST_MCBIST_0_MCBISTFIRMASK                                  , RULL(0x07010F03),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120C3) );
+// FIXREG64( MCBIST_MCBIST_0_MCBISTFIRMASK_AND                              , RULL(0x07010F04),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM1_AND , RULL(0x070120C4) );
+// FIXREG64( MCBIST_MCBIST_0_MCBISTFIRMASK_OR                               , RULL(0x07010F05),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM2_OR  , RULL(0x070120C5) );
+// FIXREG64( MCBIST_MCBIST_1_MCBISTFIRMASK                                  , RULL(0x08010F03),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120C3) );
+// FIXREG64( MCBIST_MCBIST_1_MCBISTFIRMASK_AND                              , RULL(0x08010F04),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM1_AND , RULL(0x080120C4) );
+// FIXREG64( MCBIST_MCBIST_1_MCBISTFIRMASK_OR                               , RULL(0x08010F05),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM2_OR  , RULL(0x080120C5) );
+// FIXREG64( MCBIST_MCBIST_MCBISTFIRQ                                       , RULL(0x07010F00),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120C0) );
+// FIXREG64( MCBIST_MCBIST_MCBISTFIRQ_AND                                   , RULL(0x07010F01),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM1_AND , RULL(0x070120C1) );
+// FIXREG64( MCBIST_MCBIST_MCBISTFIRQ_OR                                    , RULL(0x07010F02),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM2_OR  , RULL(0x070120C2) );
+// FIXREG64( MCBIST_MCBIST_0_MCBISTFIRQ                                     , RULL(0x07010F00),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x070120C0) );
+// FIXREG64( MCBIST_MCBIST_0_MCBISTFIRQ_AND                                 , RULL(0x07010F01),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM1_AND , RULL(0x070120C1) );
+// FIXREG64( MCBIST_MCBIST_0_MCBISTFIRQ_OR                                  , RULL(0x07010F02),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM2_OR  , RULL(0x070120C2) );
+// FIXREG64( MCBIST_MCBIST_1_MCBISTFIRQ                                     , RULL(0x08010F00),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x080120C0) );
+// FIXREG64( MCBIST_MCBIST_1_MCBISTFIRQ_AND                                 , RULL(0x08010F01),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM1_AND , RULL(0x080120C1) );
+// FIXREG64( MCBIST_MCBIST_1_MCBISTFIRQ_OR                                  , RULL(0x08010F02),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM2_OR  , RULL(0x080120C2) );
+// FIXREG64( MCBIST_MCBIST_MCBISTFIRWOF                                     , RULL(0x07010F08),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RO   , RULL(0x070120C8) );
+// FIXREG64( MCBIST_MCBIST_0_MCBISTFIRWOF                                   , RULL(0x07010F08),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RO   , RULL(0x070120C8) );
+// FIXREG64( MCBIST_MCBIST_1_MCBISTFIRWOF                                   , RULL(0x08010F08),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RO   , RULL(0x080120C8) );
+// FIXREG64( MCBIST_MCBIST_MCBLFSRA0Q                                       , RULL(0x07010FD4),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012194) );
+// FIXREG64( MCBIST_MCBIST_0_MCBLFSRA0Q                                     , RULL(0x07010FD4),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012194) );
+// FIXREG64( MCBIST_MCBIST_1_MCBLFSRA0Q                                     , RULL(0x08010FD4),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012194) );
+// FIXREG64( MCBIST_MCBIST_MCBMCATQ                                         , RULL(0x07010FD7),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012197) );
+// FIXREG64( MCBIST_MCBIST_0_MCBMCATQ                                       , RULL(0x07010FD7),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012197) );
+// FIXREG64( MCBIST_MCBIST_1_MCBMCATQ                                       , RULL(0x08010FD7),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012197) );
+// FIXREG64( MCBIST_MCBIST_MCBMR0Q                                          , RULL(0x07010FA8),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012168) );
+// FIXREG64( MCBIST_MCBIST_0_MCBMR0Q                                        , RULL(0x07010FA8),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012168) );
+// FIXREG64( MCBIST_MCBIST_1_MCBMR0Q                                        , RULL(0x08010FA8),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012168) );
+// FIXREG64( MCBIST_MCBIST_MCBMR1Q                                          , RULL(0x07010FA9),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012169) );
+// FIXREG64( MCBIST_MCBIST_0_MCBMR1Q                                        , RULL(0x07010FA9),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012169) );
+// FIXREG64( MCBIST_MCBIST_1_MCBMR1Q                                        , RULL(0x08010FA9),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012169) );
+// FIXREG64( MCBIST_MCBIST_MCBMR2Q                                          , RULL(0x07010FAA),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701216A) );
+// FIXREG64( MCBIST_MCBIST_0_MCBMR2Q                                        , RULL(0x07010FAA),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701216A) );
+// FIXREG64( MCBIST_MCBIST_1_MCBMR2Q                                        , RULL(0x08010FAA),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801216A) );
+// FIXREG64( MCBIST_MCBIST_MCBMR3Q                                          , RULL(0x07010FAB),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701216B) );
+// FIXREG64( MCBIST_MCBIST_0_MCBMR3Q                                        , RULL(0x07010FAB),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701216B) );
+// FIXREG64( MCBIST_MCBIST_1_MCBMR3Q                                        , RULL(0x08010FAB),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801216B) );
+// FIXREG64( MCBIST_MCBIST_MCBMR4Q                                          , RULL(0x07010FAC),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701216C) );
+// FIXREG64( MCBIST_MCBIST_0_MCBMR4Q                                        , RULL(0x07010FAC),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701216C) );
+// FIXREG64( MCBIST_MCBIST_1_MCBMR4Q                                        , RULL(0x08010FAC),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801216C) );
+// FIXREG64( MCBIST_MCBIST_MCBMR5Q                                          , RULL(0x07010FAD),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701216D) );
+// FIXREG64( MCBIST_MCBIST_0_MCBMR5Q                                        , RULL(0x07010FAD),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701216D) );
+// FIXREG64( MCBIST_MCBIST_1_MCBMR5Q                                        , RULL(0x08010FAD),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801216D) );
+// FIXREG64( MCBIST_MCBIST_MCBMR6Q                                          , RULL(0x07010FAE),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701216E) );
+// FIXREG64( MCBIST_MCBIST_0_MCBMR6Q                                        , RULL(0x07010FAE),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701216E) );
+// FIXREG64( MCBIST_MCBIST_1_MCBMR6Q                                        , RULL(0x08010FAE),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801216E) );
+// FIXREG64( MCBIST_MCBIST_MCBMR7Q                                          , RULL(0x07010FDF),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701219F) );
+// FIXREG64( MCBIST_MCBIST_0_MCBMR7Q                                        , RULL(0x07010FDF),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701219F) );
+// FIXREG64( MCBIST_MCBIST_1_MCBMR7Q                                        , RULL(0x08010FDF),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801219F) );
+// FIXREG64( MCBIST_MCBIST_MCBPARMQ                                         , RULL(0x07010FAF),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701216F) );
+// FIXREG64( MCBIST_MCBIST_0_MCBPARMQ                                       , RULL(0x07010FAF),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701216F) );
+// FIXREG64( MCBIST_MCBIST_1_MCBPARMQ                                       , RULL(0x08010FAF),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801216F) );
+// FIXREG64( MCBIST_MCBIST_MCBRCRQ                                          , RULL(0x07010FB1),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012171) );
+// FIXREG64( MCBIST_MCBIST_0_MCBRCRQ                                        , RULL(0x07010FB1),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012171) );
+// FIXREG64( MCBIST_MCBIST_1_MCBRCRQ                                        , RULL(0x08010FB1),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012171) );
+// FIXREG64( MCBIST_MCBIST_MCBRDS0Q                                         , RULL(0x07010FB2),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012172) );
+// FIXREG64( MCBIST_MCBIST_0_MCBRDS0Q                                       , RULL(0x07010FB2),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012172) );
+// FIXREG64( MCBIST_MCBIST_1_MCBRDS0Q                                       , RULL(0x08010FB2),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012172) );
+// FIXREG64( MCBIST_MCBIST_MCBRDS1Q                                         , RULL(0x07010FB3),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012173) );
+// FIXREG64( MCBIST_MCBIST_0_MCBRDS1Q                                       , RULL(0x07010FB3),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012173) );
+// FIXREG64( MCBIST_MCBIST_1_MCBRDS1Q                                       , RULL(0x08010FB3),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012173) );
+// FIXREG64( MCBIST_MCBIST_MCBSA0Q                                          , RULL(0x07010FCC),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701218C) );
+// FIXREG64( MCBIST_MCBIST_0_MCBSA0Q                                        , RULL(0x07010FCC),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701218C) );
+// FIXREG64( MCBIST_MCBIST_1_MCBSA0Q                                        , RULL(0x08010FCC),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801218C) );
+// FIXREG64( MCBIST_MCBIST_MCBSA1Q                                          , RULL(0x07010FCD),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701218D) );
+// FIXREG64( MCBIST_MCBIST_0_MCBSA1Q                                        , RULL(0x07010FCD),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701218D) );
+// FIXREG64( MCBIST_MCBIST_1_MCBSA1Q                                        , RULL(0x08010FCD),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801218D) );
+// FIXREG64( MCBIST_MCBIST_MCBSA2Q                                          , RULL(0x07010FD0),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012190) );
+// FIXREG64( MCBIST_MCBIST_0_MCBSA2Q                                        , RULL(0x07010FD0),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012190) );
+// FIXREG64( MCBIST_MCBIST_1_MCBSA2Q                                        , RULL(0x08010FD0),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012190) );
+// FIXREG64( MCBIST_MCBIST_MCBSA3Q                                          , RULL(0x07010FD1),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012191) );
+// FIXREG64( MCBIST_MCBIST_0_MCBSA3Q                                        , RULL(0x07010FD1),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012191) );
+// FIXREG64( MCBIST_MCBIST_1_MCBSA3Q                                        , RULL(0x08010FD1),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012191) );
+// FIXREG64( MCBIST_MCBIST_MCBSTATQ                                         , RULL(0x07010F66),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RO   , RULL(0x07012126) );
+// FIXREG64( MCBIST_MCBIST_0_MCBSTATQ                                       , RULL(0x07010F66),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RO   , RULL(0x07012126) );
+// FIXREG64( MCBIST_MCBIST_1_MCBSTATQ                                       , RULL(0x08010F66),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RO   , RULL(0x08012126) );
+// FIXREG64( MCBIST_MCBIST_MCB_CNTLQ                                        , RULL(0x07010FDB),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701219B) );
+// FIXREG64( MCBIST_MCBIST_0_MCB_CNTLQ                                      , RULL(0x07010FDB),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701219B) );
+// FIXREG64( MCBIST_MCBIST_1_MCB_CNTLQ                                      , RULL(0x08010FDB),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801219B) );
+// FIXREG64( MCBIST_MCBIST_MCB_CNTLSTATQ                                    , RULL(0x07010FDC),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701219C) );
+// FIXREG64( MCBIST_MCBIST_0_MCB_CNTLSTATQ                                  , RULL(0x07010FDC),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701219C) );
+// FIXREG64( MCBIST_MCBIST_1_MCB_CNTLSTATQ                                  , RULL(0x08010FDC),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801219C) );
+// FIXREG64( MCBIST_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q                         , RULL(0x07010FDD),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701219D) );
+// FIXREG64( MCBIST_MCBIST_0_RCD_LRDIM_CNTL_WORD0_15Q                       , RULL(0x07010FDD),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0701219D) );
+// FIXREG64( MCBIST_MCBIST_1_RCD_LRDIM_CNTL_WORD0_15Q                       , RULL(0x08010FDD),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x0801219D) );
+// FIXREG64( MCBIST_MCBIST_RUNTIMECTRQ                                      , RULL(0x07010FB0),  SH_UNT_MCBIST   ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012170) );
+// FIXREG64( MCBIST_MCBIST_0_RUNTIMECTRQ                                    , RULL(0x07010FB0),  SH_UNT_MCBIST_0 ,
+//           SH_ACS_SCOM_RW   , RULL(0x07012170) );
+// FIXREG64( MCBIST_MCBIST_1_RUNTIMECTRQ                                    , RULL(0x08010FB0),  SH_UNT_MCBIST_1 ,
+//           SH_ACS_SCOM_RW   , RULL(0x08012170) );
+//
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_19, RULL(0x070120E8), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBISTFIRACT1, RULL(0x080120C7), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBISTFIRWOF, RULL(0x070120C8), SH_UNT_MCBIST_0, SH_ACS_SCOM_RO);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSEC0Q, RULL(0x08012115), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_10, RULL(0x070120DF), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBNCER2Q, RULL(0x08012134), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBUER0Q, RULL(0x0701212D), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_CNTLQ, RULL(0x08012165), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBISTFIRQ, RULL(0x070120C0), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_18, RULL(0x07012107), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBDRCRQ, RULL(0x0701217D), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBAMR0A0Q, RULL(0x07012188), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_31, RULL(0x07012114), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBFD3Q, RULL(0x08012181), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBEA2Q, RULL(0x07012192), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_12, RULL(0x07012101), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBRCER1Q, RULL(0x08012130), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSTRQ, RULL(0x07012117), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_27, RULL(0x07012110), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_FIXED_DATA0Q, RULL(0x070121A5), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_00, RULL(0x070120D5), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCB_CNTLQ, RULL(0x0801219B), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBFD4Q, RULL(0x07012182), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBEA2Q, RULL(0x07012192), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_07, RULL(0x070120DC), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBUER3Q, RULL(0x0801213C), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_09, RULL(0x080120FE), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_17, RULL(0x08012106), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBAMR0A0Q, RULL(0x08012188), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBRDS1Q, RULL(0x07012173), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBNCER1Q, RULL(0x0801212F), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBISTFIRMASK_OR, RULL(0x080120C5), SH_UNT_MCBIST_1, SH_ACS_SCOM2_OR);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_07, RULL(0x070120DC), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_14, RULL(0x08012103), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBPARMQ, RULL(0x0701216F), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBMR4Q, RULL(0x0701216C), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_14, RULL(0x07012103), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBRCRQ, RULL(0x08012171), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_29, RULL(0x070120F2), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBUER2Q, RULL(0x08012137), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBAUER1Q, RULL(0x07012133), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_00, RULL(0x070120F5), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_01, RULL(0x070120F6), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBEA1Q, RULL(0x0701218F), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSSYMEC5Q, RULL(0x0801211D), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBFD3Q, RULL(0x07012181), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSSYMEC0Q, RULL(0x07012118), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_16, RULL(0x07012105), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_FIXED_DATA1Q, RULL(0x070121A6), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_20, RULL(0x070120E9), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBEA3Q, RULL(0x07012193), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBSA1Q, RULL(0x0801218D), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_CNTLQ, RULL(0x07012165), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSSYMEC1Q, RULL(0x07012119), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_24, RULL(0x070120ED), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBMPER1Q, RULL(0x07012131), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_26, RULL(0x080120EF), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_22, RULL(0x0801210B), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCSARRERRINJQ, RULL(0x0701219E), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBISTFIRMASK, RULL(0x070120C3), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_27, RULL(0x07012110), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBMR5Q, RULL(0x0701216D), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_20, RULL(0x07012109), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSMSECQ, RULL(0x07012129), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBMR2Q, RULL(0x0701216A), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_10, RULL(0x080120FF), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSSYMEC3Q, RULL(0x0701211B), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBMPER1Q, RULL(0x07012131), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_23, RULL(0x0701210C), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBNCER0Q, RULL(0x0801212A), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSEC1Q, RULL(0x07012116), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSEC1Q, RULL(0x07012116), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSSYMEC2Q, RULL(0x0701211A), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_24, RULL(0x0701210D), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBFDQ, RULL(0x08012186), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBISTFIRACT1, RULL(0x070120C7), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSSYMEC6Q, RULL(0x0701211E), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBISTFIRQ, RULL(0x080120C0), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_RUNTIMECTRQ, RULL(0x07012170), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSSYMEC4Q, RULL(0x0801211C), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBFD1Q, RULL(0x0701217F), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBDRCRQ, RULL(0x0701217D), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSSYMEC7Q, RULL(0x0801211F), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_21, RULL(0x070120EA), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBEA0Q, RULL(0x0801218E), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBEA1Q, RULL(0x0801218F), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBPARMQ, RULL(0x0801216F), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBSTATQ, RULL(0x07012126), SH_UNT_MCBIST_0, SH_ACS_SCOM_RO);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBAUER3Q, RULL(0x0701213D), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_05, RULL(0x070120FA), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_09, RULL(0x070120FE), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_20, RULL(0x08012109), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_09, RULL(0x080120DE), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_05, RULL(0x080120DA), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_10, RULL(0x080120DF), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBISTFIRMASK_AND, RULL(0x070120C4), SH_UNT_MCBIST, SH_ACS_SCOM1_AND);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBA_MCBERRPTQ, RULL(0x070121A7), SH_UNT_MCBIST_0, SH_ACS_SCOM_RO);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_28, RULL(0x07012111), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_02, RULL(0x070120D7), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSMODESQ, RULL(0x08012122), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_23, RULL(0x080120EC), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_06, RULL(0x070120FB), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBNCER1Q, RULL(0x0701212F), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_26, RULL(0x0801210F), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_15, RULL(0x070120E4), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBFD7Q, RULL(0x08012185), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_30, RULL(0x08012113), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_03, RULL(0x070120F8), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_14, RULL(0x080120E3), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_13, RULL(0x08012102), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBUER1Q, RULL(0x07012132), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_02, RULL(0x080120F7), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBISTFIRWOF, RULL(0x080120C8), SH_UNT_MCBIST_1, SH_ACS_SCOM_RO);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBMR5Q, RULL(0x0701216D), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBRCER3Q, RULL(0x0701213A), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_24, RULL(0x070120ED), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBAMR1A0Q, RULL(0x07012189), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBAGRAQ, RULL(0x07012196), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_FIXED_DATA1Q, RULL(0x070121A6), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBNCER3Q, RULL(0x08012139), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_28, RULL(0x070120F1), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_11, RULL(0x07012100), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_14, RULL(0x070120E3), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBRDS1Q, RULL(0x08012173), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_16, RULL(0x070120E5), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_23, RULL(0x070120EC), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBEA3Q, RULL(0x07012193), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSSYMEC4Q, RULL(0x0701211C), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBRCER2Q, RULL(0x07012135), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBUER2Q, RULL(0x07012137), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSSYMEC5Q, RULL(0x0701211D), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBRCER0Q, RULL(0x0801212B), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_25, RULL(0x080120EE), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_03, RULL(0x080120F8), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBAUER0Q, RULL(0x0701212E), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_00, RULL(0x080120F5), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSEC1Q, RULL(0x08012116), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBMR1Q, RULL(0x07012169), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_30, RULL(0x07012113), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_25, RULL(0x0801210E), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBRCER1Q, RULL(0x07012130), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_13, RULL(0x07012102), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBRCER1Q, RULL(0x07012130), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBFD0Q, RULL(0x0801217E), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBFD0Q, RULL(0x0701217E), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBFD1Q, RULL(0x0801217F), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_15, RULL(0x08012104), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBLFSRA0Q, RULL(0x07012194), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBECTLQ, RULL(0x080120D0), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSMSECQ, RULL(0x07012129), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCB_CNTLQ, RULL(0x0701219B), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_15, RULL(0x07012104), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_19, RULL(0x080120E8), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBDRSRQ, RULL(0x0801217C), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBMR0Q, RULL(0x07012168), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSEC0Q, RULL(0x07012115), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSSYMEC2Q, RULL(0x0801211A), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_17, RULL(0x070120E6), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBMR7Q, RULL(0x0801219F), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBMR4Q, RULL(0x0701216C), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSSYMEC6Q, RULL(0x0701211E), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBECTLQ, RULL(0x070120D0), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSSYMEC7Q, RULL(0x0701211F), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBAMR3A0Q, RULL(0x0701218B), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBAUER0Q, RULL(0x0801212E), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_08, RULL(0x080120FD), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_23, RULL(0x0701210C), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBRCER2Q, RULL(0x07012135), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_26, RULL(0x0701210F), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCB_CNTLSTATQ, RULL(0x0801219C), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBUER0Q, RULL(0x0701212D), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBMR6Q, RULL(0x0701216E), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSSYMEC0Q, RULL(0x07012118), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_10, RULL(0x070120DF), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_01, RULL(0x070120D6), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBMR1Q, RULL(0x07012169), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_00, RULL(0x070120F5), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBSA2Q, RULL(0x08012190), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_11, RULL(0x070120E0), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_06, RULL(0x070120DB), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_00, RULL(0x080120D5), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSSYMEC2Q, RULL(0x0701211A), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_11, RULL(0x08012100), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBDRSRQ, RULL(0x0701217C), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBAGRAQ, RULL(0x08012196), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBNCER2Q, RULL(0x07012134), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBISTFIRQ_AND, RULL(0x080120C1), SH_UNT_MCBIST_1, SH_ACS_SCOM1_AND);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBEA3Q, RULL(0x08012193), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_04, RULL(0x070120D9), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBRCER0Q, RULL(0x0701212B), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_02, RULL(0x070120F7), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_29, RULL(0x08012112), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_FIXED_DATA1Q, RULL(0x080121A6), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_27, RULL(0x070120F0), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBSA0Q, RULL(0x0801218C), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSSYMEC3Q, RULL(0x0801211B), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_19, RULL(0x07012108), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBMR7Q, RULL(0x0701219F), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBRCRQ, RULL(0x07012171), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBACQ, RULL(0x08012195), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_18, RULL(0x08012107), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_30, RULL(0x070120F3), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBISTFIRQ_AND, RULL(0x070120C1), SH_UNT_MCBIST_0, SH_ACS_SCOM1_AND);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBA_MCBERRPTQ, RULL(0x080121A7), SH_UNT_MCBIST_1, SH_ACS_SCOM_RO);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBMR3Q, RULL(0x0801216B), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_29, RULL(0x080120F2), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_16, RULL(0x070120E5), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_30, RULL(0x080120F3), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBRCER2Q, RULL(0x08012135), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_12, RULL(0x070120E1), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBMR1Q, RULL(0x08012169), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_05, RULL(0x070120FA), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_MODEQ, RULL(0x07012167), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_11, RULL(0x080120E0), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_15, RULL(0x080120E4), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBMPER2Q, RULL(0x07012136), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_11, RULL(0x070120E0), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_26, RULL(0x0701210F), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBISTFIRQ, RULL(0x070120C0), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBNCER3Q, RULL(0x07012139), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBNCER3Q, RULL(0x07012139), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_23, RULL(0x070120EC), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBFD2Q, RULL(0x07012180), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_20, RULL(0x070120E9), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBA_MCBERRPTQ, RULL(0x070121A7), SH_UNT_MCBIST, SH_ACS_SCOM_RO);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_10, RULL(0x070120FF), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_04, RULL(0x070120F9), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBRDS0Q, RULL(0x08012172), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_08, RULL(0x080120DD), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSMODESQ, RULL(0x07012122), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSMSECQ, RULL(0x08012129), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_04, RULL(0x080120D9), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_17, RULL(0x07012106), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBECTLQ, RULL(0x070120D0), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBAUER3Q, RULL(0x0801213D), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBNCER2Q, RULL(0x07012134), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_22, RULL(0x0701210B), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_08, RULL(0x070120FD), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBISTFIRMASK_OR, RULL(0x070120C5), SH_UNT_MCBIST, SH_ACS_SCOM2_OR);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBMR6Q, RULL(0x0701216E), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBSA2Q, RULL(0x07012190), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_31, RULL(0x08012114), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSSYMEC5Q, RULL(0x0701211D), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_05, RULL(0x070120DA), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBMPER1Q, RULL(0x08012131), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_22, RULL(0x080120EB), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_09, RULL(0x070120DE), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_00, RULL(0x070120D5), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_RCD_LRDIM_CNTL_WORD0_15Q, RULL(0x0801219D), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_12, RULL(0x07012101), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSEVR1Q, RULL(0x0701213F), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBFD7Q, RULL(0x07012185), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBRDS0Q, RULL(0x07012172), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCSARRERRINJQ, RULL(0x0701219E), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBRDS0Q, RULL(0x07012172), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_20, RULL(0x080120E9), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBMR4Q, RULL(0x0801216C), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_14, RULL(0x07012103), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBSTATQ, RULL(0x07012126), SH_UNT_MCBIST, SH_ACS_SCOM_RO);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSSYMEC4Q, RULL(0x0701211C), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBISTFIRACT1, RULL(0x070120C7), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBAMR2A0Q, RULL(0x0701218A), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_03, RULL(0x080120D8), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_27, RULL(0x070120F0), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_11, RULL(0x07012100), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBFD3Q, RULL(0x07012181), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_07, RULL(0x080120DC), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_24, RULL(0x080120ED), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBISTFIRQ_OR, RULL(0x080120C2), SH_UNT_MCBIST_1, SH_ACS_SCOM2_OR);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_22, RULL(0x070120EB), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBMPER0Q, RULL(0x0801212C), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_01, RULL(0x080120F6), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBAMR3A0Q, RULL(0x0701218B), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_22, RULL(0x070120EB), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSEVR1Q, RULL(0x0801213F), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSEVR0Q, RULL(0x0701213E), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBEA1Q, RULL(0x0701218F), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBRCER0Q, RULL(0x0701212B), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBMCATQ, RULL(0x07012197), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBISTFIRMASK_AND, RULL(0x070120C4), SH_UNT_MCBIST_0, SH_ACS_SCOM1_AND);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBUER0Q, RULL(0x0801212D), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSSYMEC8Q, RULL(0x08012120), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSSYMEC6Q, RULL(0x0801211E), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBMPER2Q, RULL(0x07012136), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_24, RULL(0x0801210D), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSSYMEC0Q, RULL(0x08012118), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_CNTLQ, RULL(0x07012165), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_25, RULL(0x0701210E), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBFD0Q, RULL(0x0701217E), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBMPER0Q, RULL(0x0701212C), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_RUNTIMECTRQ, RULL(0x07012170), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_STATQ, RULL(0x07012166), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBCFGQ, RULL(0x070121A0), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSSYMEC1Q, RULL(0x08012119), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_MODEQ, RULL(0x07012167), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_06, RULL(0x070120DB), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSMODESQ, RULL(0x07012122), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_09, RULL(0x070120FE), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBISTFIRMASK_AND, RULL(0x080120C4), SH_UNT_MCBIST_1, SH_ACS_SCOM1_AND);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_28, RULL(0x080120F1), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBISTFIRACT0, RULL(0x070120C6), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBMCATQ, RULL(0x08012197), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBRCER3Q, RULL(0x0801213A), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_RUNTIMECTRQ, RULL(0x08012170), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBMR5Q, RULL(0x0801216D), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBFD6Q, RULL(0x07012184), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBFD5Q, RULL(0x07012183), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBSA0Q, RULL(0x0701218C), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBAMR2A0Q, RULL(0x0701218A), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBUER2Q, RULL(0x07012137), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBAMR2A0Q, RULL(0x0801218A), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_29, RULL(0x07012112), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_22, RULL(0x0701210B), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_07, RULL(0x070120FC), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBAUER2Q, RULL(0x07012138), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_18, RULL(0x07012107), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBSA1Q, RULL(0x0701218D), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_03, RULL(0x070120F8), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBSA2Q, RULL(0x07012190), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_26, RULL(0x070120EF), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_31, RULL(0x080120F4), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_04, RULL(0x070120D9), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBFD2Q, RULL(0x08012180), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_19, RULL(0x08012108), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBMPER0Q, RULL(0x0701212C), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_17, RULL(0x070120E6), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_16, RULL(0x080120E5), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_12, RULL(0x080120E1), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBMPER3Q, RULL(0x0701213B), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_18, RULL(0x070120E7), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_03, RULL(0x070120D8), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_28, RULL(0x08012111), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_31, RULL(0x070120F4), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSSYMEC8Q, RULL(0x07012120), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBAMR1A0Q, RULL(0x08012189), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBCFGQ, RULL(0x080121A0), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSSYMEC1Q, RULL(0x07012119), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_04, RULL(0x080120F9), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_26, RULL(0x070120EF), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_01, RULL(0x070120F6), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_09, RULL(0x070120DE), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_MODEQ, RULL(0x08012167), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_13, RULL(0x07012102), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_16, RULL(0x07012105), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBISTFIRQ_OR, RULL(0x070120C2), SH_UNT_MCBIST_0, SH_ACS_SCOM2_OR);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_02, RULL(0x070120D7), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBFD6Q, RULL(0x08012184), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_21, RULL(0x0701210A), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBAGRAQ, RULL(0x07012196), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBAMR1A0Q, RULL(0x07012189), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBRCRQ, RULL(0x07012171), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBMR7Q, RULL(0x0701219F), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBMPER3Q, RULL(0x0801213B), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_25, RULL(0x0701210E), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBFDQ, RULL(0x07012186), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_04, RULL(0x070120F9), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBMR0Q, RULL(0x08012168), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_07, RULL(0x080120FC), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_31, RULL(0x070120F4), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBAUER0Q, RULL(0x0701212E), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBUER1Q, RULL(0x08012132), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSTRQ, RULL(0x07012117), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBMPER2Q, RULL(0x08012136), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCB_CNTLQ, RULL(0x0701219B), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_30, RULL(0x07012113), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_FIXED_DATA0Q, RULL(0x070121A5), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBAUER3Q, RULL(0x0701213D), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBSSYMEC8Q, RULL(0x07012120), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBISTFIRMASK_OR, RULL(0x070120C5), SH_UNT_MCBIST_0, SH_ACS_SCOM2_OR);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBAUER2Q, RULL(0x08012138), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBACQ, RULL(0x07012195), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBRCER3Q, RULL(0x0701213A), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBLFSRA0Q, RULL(0x08012194), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBAUER1Q, RULL(0x08012133), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBAMR0A0Q, RULL(0x07012188), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCB_CNTLSTATQ, RULL(0x0701219C), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBNCER0Q, RULL(0x0701212A), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_03, RULL(0x070120D8), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_19, RULL(0x070120E8), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBRDS1Q, RULL(0x07012173), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBEA0Q, RULL(0x0701218E), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBSA3Q, RULL(0x08012191), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBFD6Q, RULL(0x07012184), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBSTATQ, RULL(0x08012126), SH_UNT_MCBIST_1, SH_ACS_SCOM_RO);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_21, RULL(0x070120EA), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSTRQ, RULL(0x08012117), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBSA3Q, RULL(0x07012191), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBISTFIRWOF, RULL(0x070120C8), SH_UNT_MCBIST, SH_ACS_SCOM_RO);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_10, RULL(0x070120FF), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_28, RULL(0x07012111), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_FIXED_DATA0Q, RULL(0x080121A5), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBLFSRA0Q, RULL(0x07012194), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_08, RULL(0x070120DD), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBUER3Q, RULL(0x0701213C), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_06, RULL(0x080120FB), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSEC0Q, RULL(0x07012115), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBFD1Q, RULL(0x0701217F), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBFD7Q, RULL(0x07012185), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_12, RULL(0x070120E1), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBFD5Q, RULL(0x08012183), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBNCER1Q, RULL(0x0701212F), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_08, RULL(0x070120DD), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_13, RULL(0x070120E2), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_18, RULL(0x070120E7), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_19, RULL(0x07012108), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_02, RULL(0x080120D7), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBFD4Q, RULL(0x07012182), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_07, RULL(0x070120FC), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q, RULL(0x0701219D), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_21, RULL(0x080120EA), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_06, RULL(0x080120DB), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBMR6Q, RULL(0x0801216E), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_28, RULL(0x070120F1), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_20, RULL(0x07012109), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBUER1Q, RULL(0x07012132), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_27, RULL(0x080120F0), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBISTFIRACT0, RULL(0x070120C6), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBFD4Q, RULL(0x08012182), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_23, RULL(0x0801210C), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_25, RULL(0x070120EE), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBAUER1Q, RULL(0x07012133), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBACQ, RULL(0x07012195), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_21, RULL(0x0701210A), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_30, RULL(0x070120F3), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBPARMQ, RULL(0x0701216F), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_16, RULL(0x08012105), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBISTFIRMASK, RULL(0x070120C3), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_15, RULL(0x07012104), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_05, RULL(0x070120DA), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBMCATQ, RULL(0x07012197), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBISTFIRACT0, RULL(0x080120C6), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_RCD_LRDIM_CNTL_WORD0_15Q, RULL(0x0701219D), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSEVR1Q, RULL(0x0701213F), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_08, RULL(0x070120FD), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBDRCRQ, RULL(0x0801217D), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_17, RULL(0x07012106), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBFDQ, RULL(0x07012186), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_13, RULL(0x080120E2), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBMR2Q, RULL(0x0801216A), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCSARRERRINJQ, RULL(0x0801219E), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_13, RULL(0x070120E2), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_24, RULL(0x0701210D), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_17, RULL(0x080120E6), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBFD5Q, RULL(0x07012183), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBISTFIRQ_AND, RULL(0x070120C1), SH_UNT_MCBIST, SH_ACS_SCOM1_AND);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSSYMEC7Q, RULL(0x0701211F), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBISTFIRMASK, RULL(0x080120C3), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBFD2Q, RULL(0x07012180), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBMR3Q, RULL(0x0701216B), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBSA0Q, RULL(0x0701218C), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBAUER2Q, RULL(0x07012138), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBNCER0Q, RULL(0x0701212A), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_STATQ, RULL(0x07012166), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBEA2Q, RULL(0x08012192), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_15, RULL(0x070120E4), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBDRSRQ, RULL(0x0701217C), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MCBAMR3A0Q, RULL(0x0801218B), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_25, RULL(0x070120EE), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBMPER3Q, RULL(0x0701213B), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_01, RULL(0x080120D6), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCB_CNTLSTATQ, RULL(0x0701219C), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBSA3Q, RULL(0x07012191), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_06, RULL(0x070120FB), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_02, RULL(0x070120F7), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBMR2Q, RULL(0x0701216A), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBMR0Q, RULL(0x07012168), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSEVR0Q, RULL(0x0701213E), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_27, RULL(0x08012110), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBSA1Q, RULL(0x0701218D), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR1_31, RULL(0x07012114), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MBUER3Q, RULL(0x0701213C), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR0_18, RULL(0x080120E7), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_05, RULL(0x080120FA), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_29, RULL(0x070120F2), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBISTFIRQ_OR, RULL(0x070120C2), SH_UNT_MCBIST, SH_ACS_SCOM2_OR);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_STATQ, RULL(0x08012166), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_CCS_INST_ARR0_01, RULL(0x070120D6), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MBSSYMEC3Q, RULL(0x0701211B), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_MCBCFGQ, RULL(0x070121A0), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBMR3Q, RULL(0x0701216B), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_21, RULL(0x0801210A), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_CCS_INST_ARR1_12, RULL(0x08012101), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_MCBEA0Q, RULL(0x0701218E), SH_UNT_MCBIST, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR0_14, RULL(0x070120E3), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_0_CCS_INST_ARR1_29, RULL(0x07012112), SH_UNT_MCBIST_0, SH_ACS_SCOM_RW);
+// //WARNING: This register is not defined anymore in the figtree.
+// REG64( MCBIST_MCBIST_1_MBSEVR0Q, RULL(0x0801213E), SH_UNT_MCBIST_1, SH_ACS_SCOM_RW);
+#endif
diff --git a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H
new file mode 100644
index 00000000..23a86b17
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld.H
@@ -0,0 +1,28302 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_mc_scom_addresses_fld.H $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_mc_scom_addresses_fld.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#include <p9_const_common.H>
+
+#ifndef __P9_MC_SCOM_ADDRESSES_FLD_H
+#define __P9_MC_SCOM_ADDRESSES_FLD_H
+
+
+#include <p9_scom_template_consts.H>
+#include <p9_mc_scom_addresses_fld_fixes.H>
+
+REG64_FLD( MCS_PORT02_AACR_BUFFER                                  , 0   , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RW  ,
+           SH_FLD_BUFFER     );
+REG64_FLD( MCS_PORT02_AACR_ADDRESS                                 , 1   , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( MCS_PORT02_AACR_ADDRESS_LEN                             , 9   , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( MCS_PORT02_AACR_AUTOINC                                 , 10  , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RW  ,
+           SH_FLD_AUTOINC    );
+
+REG64_FLD( MCA_WREITE_AACR_BUFFER                                  , 0   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW  ,
+           SH_FLD_BUFFER     );
+REG64_FLD( MCA_WREITE_AACR_ADDRESS                                 , 1   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( MCA_WREITE_AACR_ADDRESS_LEN                             , 9   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( MCA_WREITE_AACR_AUTOINC                                 , 10  , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW  ,
+           SH_FLD_AUTOINC    );
+REG64_FLD( MCA_WREITE_AACR_ECCGEN                                  , 11  , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW  ,
+           SH_FLD_ECCGEN     );
+
+REG64_FLD( MCS_PORT02_AADR_DATA                                    , 0   , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( MCS_PORT02_AADR_DATA_LEN                                , 64  , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( MCA_AADR_DATA                                           , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( MCA_AADR_DATA_LEN                                       , 64  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( MCS_PORT02_AAER_TAG_ECC                                 , 0   , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RO  ,
+           SH_FLD_TAG_ECC    );
+REG64_FLD( MCS_PORT02_AAER_TAG_ECC_LEN                             , 9   , SH_UNT_MCS_PORT02, SH_ACS_SCOM_RO  ,
+           SH_FLD_TAG_ECC_LEN );
+
+REG64_FLD( MCA_AAER_TAG_ECC                                        , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TAG_ECC    );
+REG64_FLD( MCA_AAER_TAG_ECC_LEN                                    , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TAG_ECC_LEN );
+
+REG64_FLD( MCA_ACTION0_FIR                                         , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR        );
+REG64_FLD( MCA_ACTION0_FIR_LEN                                     , 64  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_LEN    );
+
+REG64_FLD( MCA_ACTION1_FIR                                         , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR        );
+REG64_FLD( MCA_ACTION1_FIR_LEN                                     , 64  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_LEN    );
+
+REG64_FLD( MCA_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( MCA_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN );
+REG64_FLD( MCA_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( MCA_ADDR_TRAP_REG_RESERVED_LAST_LT                      , 17  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LAST_LT );
+REG64_FLD( MCA_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR );
+REG64_FLD( MCA_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN );
+REG64_FLD( MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY );
+REG64_FLD( MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR );
+REG64_FLD( MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION );
+REG64_FLD( MCA_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER );
+
+REG64_FLD( MCA_ATOMIC_LOCK_MASK_LATCH_REG_MASK                     , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MASK       );
+REG64_FLD( MCA_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN                 , 16  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ_MODE          , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CCS_ARRAY_CE_ERR_INJ_MODE );
+REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ               , 1   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CCS_ARRAY_CE_ERR_INJ );
+REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ_MODE          , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CCS_ARRAY_UE_ERR_INJ_MODE );
+REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ               , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CCS_ARRAY_UE_ERR_INJ );
+REG64_FLD( MCBIST_CCSARRERRINJQ_RESERVED_4                         , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_4 );
+REG64_FLD( MCBIST_CCSARRERRINJQ_DISABLE_2N_MODE                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_2N_MODE );
+REG64_FLD( MCBIST_CCSARRERRINJQ_RESERVED_6_14                      , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_6_14 );
+REG64_FLD( MCBIST_CCSARRERRINJQ_RESERVED_6_14_LEN                  , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_6_14_LEN );
+REG64_FLD( MCBIST_CCSARRERRINJQ_READ_RESPONSE_DELAY_ENABLE         , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_RESPONSE_DELAY_ENABLE );
+REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0          , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CCS_LOOP_COUNTER_COMPARE0 );
+REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0_LEN      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CCS_LOOP_COUNTER_COMPARE0_LEN );
+REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1          , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CCS_LOOP_COUNTER_COMPARE1 );
+REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1_LEN      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CCS_LOOP_COUNTER_COMPARE1_LEN );
+REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2          , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CCS_LOOP_COUNTER_COMPARE2 );
+REG64_FLD( MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2_LEN      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CCS_LOOP_COUNTER_COMPARE2_LEN );
+
+REG64_FLD( MCBIST_CCS_CNTLQ_START                                  , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_START      );
+REG64_FLD( MCBIST_CCS_CNTLQ_STOP                                   , 1   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP       );
+
+REG64_FLD( MCBIST_CCS_FIXED_DATA0Q_DATA_0_63                       , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_0_63  );
+REG64_FLD( MCBIST_CCS_FIXED_DATA0Q_DATA_0_63_LEN                   , 64  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_0_63_LEN );
+
+REG64_FLD( MCBIST_CCS_FIXED_DATA1Q_DATA_64_79                      , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_64_79 );
+REG64_FLD( MCBIST_CCS_FIXED_DATA1Q_DATA_64_79_LEN                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_64_79_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_01_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_02_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_03_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_04_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_05_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_06_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_07_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_08_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_09_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_10_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_11_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_12_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_0                   , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_0_LEN               , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_13_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS                     , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_14_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS                     , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_15_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS                     , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_16_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS                     , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_17_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_18_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_19_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_20_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_21_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_22_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_23_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_24_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_25_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_26_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_27_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_RESERVED_31                     , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_RESERVED_31_LEN                 , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_28_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_29_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_RESERVED_28_31                  , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_RESERVED_28_31_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_30_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_0_13                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_0_13_LEN            , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_17                  , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_BANK_GROUP_1                , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_RESETN                      , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_RESETN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_BANK_0_1                    , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_BANK_0_1_LEN                , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_BANK_GROUP_0                , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ACTN                        , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ACTN   );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_16                  , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_15                  , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_14                  , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CKE                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CKE_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CKE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_RESERVED_28                     , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_RESERVED_28_LEN                 , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CSN_0_1                     , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CSN_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CID_0_1                     , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CID_0_1_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_0_1_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CSN_2_3                     , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CSN_2_3_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CSN_2_3_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CID_2                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CID_2  );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_RESERVED_39_47                  , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_RESERVED_39_47_LEN              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_47_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ODT                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT    );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_ODT_LEN                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_ODT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_RESERVED_52_55                  , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_RESERVED_52_55_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52_55_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CAL_TYPE                    , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_CAL_TYPE_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_PARITY                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_DDR_BANK_2                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_BANK_2 );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_LOOP_BREAK_MODE                 , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE );
+REG64_FLD( MCBIST_CCS_INST_ARR0_31_LOOP_BREAK_MODE_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOOP_BREAK_MODE_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_00_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_00_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_00_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_00_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_00_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_00_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_01_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_01_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_01_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_01_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_01_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_01_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_01_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_01_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_01_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_01_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_01_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_01_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_01_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_02_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_02_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_02_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_02_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_02_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_02_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_02_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_02_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_02_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_02_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_02_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_02_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_02_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_03_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_03_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_03_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_03_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_03_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_03_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_03_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_03_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_03_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_03_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_03_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_03_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_03_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_04_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_04_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_04_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_04_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_04_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_04_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_04_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_04_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_04_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_04_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_04_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_04_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_04_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_05_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_05_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_05_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_05_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_05_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_05_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_05_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_05_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_05_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_05_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_05_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_05_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_05_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_06_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_06_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_06_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_06_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_06_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_06_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_06_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_06_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_06_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_06_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_06_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_06_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_06_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_07_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_07_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_07_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_07_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_07_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_07_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_07_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_07_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_07_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_07_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_07_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_07_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_07_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_08_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_08_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_08_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_08_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_08_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_08_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_08_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_08_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_08_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_08_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_08_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_08_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_08_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_09_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_09_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_09_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_09_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_09_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_09_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_09_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_09_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_09_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_09_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_09_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_09_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_09_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_10_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_10_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_10_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_10_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_10_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_10_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_10_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_10_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_10_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_10_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_10_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_10_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_10_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_11_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_11_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_11_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_11_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_11_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_11_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_11_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_11_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_11_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_11_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_11_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_11_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_11_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_12_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_12_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_12_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_12_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_12_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_12_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_12_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_12_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_12_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_12_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_12_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_12_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_12_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_13_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_13_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_13_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_13_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_13_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_13_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_13_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_13_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_13_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_13_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_13_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_13_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_13_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_14_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_14_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_14_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_14_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_14_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_14_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_14_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_14_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_14_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_14_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_14_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_14_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_14_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_15_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_15_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_15_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_15_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_15_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_15_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_15_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_15_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_15_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_15_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_15_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_15_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_15_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_16_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_16_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_16_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_16_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_16_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_16_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_16_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_16_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_16_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_16_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_16_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_16_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_16_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_17_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_17_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_17_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_17_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_17_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_17_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_17_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_17_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_17_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_17_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_17_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_17_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_17_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_18_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_18_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_18_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_18_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_18_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_18_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_18_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_18_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_18_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_18_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_18_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_18_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_18_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_19_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_19_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_19_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_19_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_19_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_19_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_19_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_19_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_19_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_19_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_19_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_19_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_19_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_20_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_20_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_20_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_20_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_20_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_20_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_20_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_20_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_20_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_20_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_20_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_20_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_20_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_21_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_21_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_21_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_21_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_21_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_21_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_21_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_21_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_21_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_21_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_21_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_21_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_21_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_22_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_22_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_22_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_22_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_22_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_22_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_22_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_22_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_22_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_22_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_22_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_22_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_22_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_23_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_23_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_23_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_23_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_23_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_23_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_23_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_23_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_23_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_23_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_23_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_23_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_23_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_24_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_24_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_24_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_24_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_24_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_24_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_24_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_24_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_24_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_24_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_24_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_24_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_24_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_25_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_25_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_25_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_25_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_25_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_25_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_25_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_25_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_25_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_25_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_25_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_25_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_25_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_26_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_26_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_26_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_26_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_26_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_26_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_26_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_26_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_26_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_26_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_26_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_26_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_26_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_27_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_27_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_27_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_27_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_27_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_27_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_27_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_27_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_27_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_27_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_27_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_27_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_27_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_28_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_28_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_28_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_28_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_28_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_28_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_28_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_28_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_28_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_28_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_28_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_28_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_28_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_29_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_29_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_29_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_29_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_29_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_29_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_29_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_29_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_29_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_29_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_29_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_29_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_29_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_30_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_30_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_30_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_30_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_30_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_30_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_30_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_30_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_30_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_30_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_30_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_30_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_30_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_INST_ARR1_31_IDLES                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES      );
+REG64_FLD( MCBIST_CCS_INST_ARR1_31_IDLES_LEN                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLES_LEN  );
+REG64_FLD( MCBIST_CCS_INST_ARR1_31_REPEAT_CMD_CNT                  , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT );
+REG64_FLD( MCBIST_CCS_INST_ARR1_31_REPEAT_CMD_CNT_LEN              , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REPEAT_CMD_CNT_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_31_READ_OR_WRITE_DATA              , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA );
+REG64_FLD( MCBIST_CCS_INST_ARR1_31_READ_OR_WRITE_DATA_LEN          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_OR_WRITE_DATA_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_31_READ_COMPARE_REQUIRED           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_COMPARE_REQUIRED );
+REG64_FLD( MCBIST_CCS_INST_ARR1_31_DDR_CAL_RANK                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK );
+REG64_FLD( MCBIST_CCS_INST_ARR1_31_DDR_CAL_RANK_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_RANK_LEN );
+REG64_FLD( MCBIST_CCS_INST_ARR1_31_DDR_CALIBRATION_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CALIBRATION_ENABLE );
+REG64_FLD( MCBIST_CCS_INST_ARR1_31_END                             , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_END        );
+REG64_FLD( MCBIST_CCS_INST_ARR1_31_GOTO_CMD                        , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD   );
+REG64_FLD( MCBIST_CCS_INST_ARR1_31_GOTO_CMD_LEN                    , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GOTO_CMD_LEN );
+
+REG64_FLD( MCBIST_CCS_MODEQ_STOP_ON_ERR                            , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_ON_ERR );
+REG64_FLD( MCBIST_CCS_MODEQ_UE_DISABLE                             , 1   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_UE_DISABLE );
+REG64_FLD( MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_COMPARE_BURST_SEL );
+REG64_FLD( MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL_LEN             , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_COMPARE_BURST_SEL_LEN );
+REG64_FLD( MCBIST_CCS_MODEQ_RESERVED_4_7                           , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_4_7 );
+REG64_FLD( MCBIST_CCS_MODEQ_RESERVED_4_7_LEN                       , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_4_7_LEN );
+REG64_FLD( MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT                    , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TIMEOUT_CNT );
+REG64_FLD( MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_LEN                , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TIMEOUT_CNT_LEN );
+REG64_FLD( MCBIST_CCS_MODEQ_CFG_PARITY_AFTER_CMD                   , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PARITY_AFTER_CMD );
+REG64_FLD( MCBIST_CCS_MODEQ_RESERVED_25                            , 25  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_25 );
+REG64_FLD( MCBIST_CCS_MODEQ_COPY_CKE_TO_SPARE_CKE                  , 26  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_COPY_CKE_TO_SPARE_CKE );
+REG64_FLD( MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CHK                  , 27  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_ECC_ARRAY_CHK );
+REG64_FLD( MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CORRECTION           , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_ECC_ARRAY_CORRECTION );
+REG64_FLD( MCBIST_CCS_MODEQ_CFG_DGEN_FIXED_MODE                    , 29  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DGEN_FIXED_MODE );
+REG64_FLD( MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT               , 30  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT );
+REG64_FLD( MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT_LEN );
+REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13                  , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLE_PAT_ADDRESS_0_13 );
+REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13_LEN              , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLE_PAT_ADDRESS_0_13_LEN );
+REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_17                    , 46  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLE_PAT_ADDRESS_17 );
+REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_1                  , 47  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLE_PAT_BANK_GROUP_1 );
+REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1                      , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLE_PAT_BANK_0_1 );
+REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1_LEN                  , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLE_PAT_BANK_0_1_LEN );
+REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_0                  , 50  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLE_PAT_BANK_GROUP_0 );
+REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_ACTN                          , 51  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLE_PAT_ACTN );
+REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_16                    , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLE_PAT_ADDRESS_16 );
+REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_15                    , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLE_PAT_ADDRESS_15 );
+REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_14                    , 54  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLE_PAT_ADDRESS_14 );
+REG64_FLD( MCBIST_CCS_MODEQ_NTTM_MODE                              , 55  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_NTTM_MODE  );
+REG64_FLD( MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY                       , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_NTTM_RW_DATA_DLY );
+REG64_FLD( MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY_LEN                   , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_NTTM_RW_DATA_DLY_LEN );
+REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_BANK_2                        , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLE_PAT_BANK_2 );
+REG64_FLD( MCBIST_CCS_MODEQ_DDR_PARITY_ENABLE                      , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR_PARITY_ENABLE );
+REG64_FLD( MCBIST_CCS_MODEQ_IDLE_PAT_PARITY                        , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IDLE_PAT_PARITY );
+REG64_FLD( MCBIST_CCS_MODEQ_RESERVED_63                            , 63  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_63 );
+
+REG64_FLD( MCBIST_CCS_STATQ_IP                                     , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IP         );
+REG64_FLD( MCBIST_CCS_STATQ_DONE                                   , 1   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DONE       );
+REG64_FLD( MCBIST_CCS_STATQ_FAIL                                   , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FAIL       );
+REG64_FLD( MCBIST_CCS_STATQ_FAIL_TYPE                              , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FAIL_TYPE  );
+REG64_FLD( MCBIST_CCS_STATQ_FAIL_TYPE_LEN                          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FAIL_TYPE_LEN );
+REG64_FLD( MCBIST_CCS_STATQ_MCBIST_SUBTEST_IP                      , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_SUBTEST_IP );
+REG64_FLD( MCBIST_CCS_STATQ_FAIL_RCD                               , 7   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FAIL_RCD   );
+
+REG64_FLD( MCA_CERR0_RECR_PE                                       , 10  , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_RECR_PE    );
+REG64_FLD( MCA_CERR0_MSR_PE                                        , 12  , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_MSR_PE     );
+REG64_FLD( MCA_CERR0_EICR_PE                                       , 13  , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_EICR_PE    );
+REG64_FLD( MCA_CERR0_HWMSX_PE                                      , 16  , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_HWMSX_PE   );
+REG64_FLD( MCA_CERR0_HWMSX_PE_LEN                                  , 8   , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_HWMSX_PE_LEN );
+REG64_FLD( MCA_CERR0_FWMSX_PE                                      , 24  , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_FWMSX_PE   );
+REG64_FLD( MCA_CERR0_FWMSX_PE_LEN                                  , 8   , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_FWMSX_PE_LEN );
+REG64_FLD( MCA_CERR0_WECR_PE                                       , 40  , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_WECR_PE    );
+REG64_FLD( MCA_CERR0_AACR_PE                                       , 41  , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_AACR_PE    );
+REG64_FLD( MCA_CERR0_AADR_PE                                       , 42  , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_AADR_PE    );
+REG64_FLD( MCA_CERR0_AAER_PE                                       , 43  , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_AAER_PE    );
+REG64_FLD( MCA_CERR0_MCBCM_PE                                      , 44  , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_MCBCM_PE   );
+REG64_FLD( MCA_CERR0_WDFCFG_PE                                     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_WDFCFG_PE  );
+REG64_FLD( MCA_CERR0_WRTCFG_PE                                     , 56  , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_WRTCFG_PE  );
+
+REG64_FLD( MCA_CERR1_ECC_CTL_AF_PERR                               , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ECC_CTL_AF_PERR );
+REG64_FLD( MCA_CERR1_ECC_CTL_RPTR_PERR                             , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ECC_CTL_RPTR_PERR );
+REG64_FLD( MCA_CERR1_ECC_CTL_TCHN_PERR                             , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ECC_CTL_TCHN_PERR );
+REG64_FLD( MCA_CERR1_ECC_CTL_CMPMODE_ERR                           , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ECC_CTL_CMPMODE_ERR );
+REG64_FLD( MCA_CERR1_ECC_CTL_SCH_PERR                              , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ECC_CTL_SCH_PERR );
+REG64_FLD( MCA_CERR1_ECC_CTL_PCTL_PERR                             , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ECC_CTL_PCTL_PERR );
+REG64_FLD( MCA_CERR1_ECC_CTL_TGST_PERR                             , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ECC_CTL_TGST_PERR );
+REG64_FLD( MCA_CERR1_READ_ECC_DATAPATH_PARITY_ERROR                , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_READ_ECC_DATAPATH_PARITY_ERROR );
+REG64_FLD( MCA_CERR1_ECC_PIPE_PARITY_ERROR_0                       , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ECC_PIPE_PARITY_ERROR_0 );
+REG64_FLD( MCA_CERR1_ECC_PIPE_PARITY_ERROR_1                       , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ECC_PIPE_PARITY_ERROR_1 );
+REG64_FLD( MCA_CERR1_ECC_PIPE_PARITY_ERROR_2                       , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ECC_PIPE_PARITY_ERROR_2 );
+REG64_FLD( MCA_CERR1_ECC_PIPE_PARITY_ERROR_3                       , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ECC_PIPE_PARITY_ERROR_3 );
+REG64_FLD( MCA_CERR1_PHY_PARITY_HOLD_OUT                           , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PHY_PARITY_HOLD_OUT );
+REG64_FLD( MCA_CERR1_WDF_ASYNC_ERROR                               , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WDF_ASYNC_ERROR );
+REG64_FLD( MCA_CERR1_WDF_BUFFER_CE                                 , 17  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WDF_BUFFER_CE );
+REG64_FLD( MCA_CERR1_WDF_BUFFER_UE                                 , 18  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WDF_BUFFER_UE );
+REG64_FLD( MCA_CERR1_WDF_BUFFER_SUE                                , 19  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WDF_BUFFER_SUE );
+REG64_FLD( MCA_CERR1_WRT_BUFFER_CE                                 , 25  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRT_BUFFER_CE );
+REG64_FLD( MCA_CERR1_WRT_BUFFER_UE                                 , 26  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRT_BUFFER_UE );
+REG64_FLD( MCA_CERR1_WRT_BUFFER_SUE                                , 27  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRT_BUFFER_SUE );
+REG64_FLD( MCA_CERR1_READ_CONTROL_OVERFLOW_ERROR                   , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_READ_CONTROL_OVERFLOW_ERROR );
+REG64_FLD( MCA_CERR1_WRITE_ECC_DATAPATH_ERROR                      , 40  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ECC_DATAPATH_ERROR );
+
+REG64_FLD( MCBIST_CLKRATIO_RATIO                                   , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_RATIO      );
+REG64_FLD( MCBIST_CLKRATIO_RATIO_LEN                               , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_RATIO_LEN  );
+
+REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_ENABLE                          , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_ENABLE );
+REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT01               , 1   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_PICK_ASYNC_PORT01 );
+REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT01_LEN           , 11  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_PICK_ASYNC_PORT01_LEN );
+REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT23               , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_PICK_ASYNC_PORT23 );
+REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT23_LEN           , 11  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_PICK_ASYNC_PORT23_LEN );
+REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST01                   , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_PICK_MCBIST01 );
+REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST01_LEN               , 11  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_PICK_MCBIST01_LEN );
+REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST23                   , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_PICK_MCBIST23 );
+REG64_FLD( MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST23_LEN               , 11  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_PICK_MCBIST23_LEN );
+REG64_FLD( MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_TRIGGER                , 45  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SCOM_SET_WAT_EXT_TRIGGER );
+REG64_FLD( MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_RESET                  , 46  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SCOM_SET_WAT_EXT_RESET );
+REG64_FLD( MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_ARM                    , 47  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SCOM_SET_WAT_EXT_ARM );
+
+REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_ENABLE                          , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_ENABLE );
+REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_EVENT_TO_INT                , 1   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EXT_EVENT_TO_INT );
+REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_EVENT_TO_INT_LEN            , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EXT_EVENT_TO_INT_LEN );
+REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_TRIGGER_SEL                 , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EXT_TRIGGER_SEL );
+REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_TRIGGER_SEL_LEN             , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EXT_TRIGGER_SEL_LEN );
+REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_RESET_SEL                   , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EXT_RESET_SEL );
+REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_RESET_SEL_LEN               , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EXT_RESET_SEL_LEN );
+REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_ARM_SEL                     , 43  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EXT_ARM_SEL );
+REG64_FLD( MCBIST_DBGCFG1Q_CFG_WAT_EXT_ARM_SEL_LEN                 , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EXT_ARM_SEL_LEN );
+REG64_FLD( MCBIST_DBGCFG1Q_RESERVED_63                             , 63  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_63 );
+
+REG64_FLD( MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT0_SEL                  , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_LOC_EVENT0_SEL );
+REG64_FLD( MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT0_SEL_LEN              , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_LOC_EVENT0_SEL_LEN );
+REG64_FLD( MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT1_SEL                  , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_LOC_EVENT1_SEL );
+REG64_FLD( MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT1_SEL_LEN              , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_LOC_EVENT1_SEL_LEN );
+REG64_FLD( MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT2_SEL                  , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_LOC_EVENT2_SEL );
+REG64_FLD( MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT2_SEL_LEN              , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_LOC_EVENT2_SEL_LEN );
+REG64_FLD( MCBIST_DBGCFG2Q_RESERVED_60_63                          , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_60_63 );
+REG64_FLD( MCBIST_DBGCFG2Q_RESERVED_60_63_LEN                      , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_60_63_LEN );
+
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_LOC_EVENT3_SEL                  , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_LOC_EVENT3_SEL );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_LOC_EVENT3_SEL_LEN              , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_LOC_EVENT3_SEL_LEN );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT0_SEL                 , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_GLOB_EVENT0_SEL );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT0_SEL_LEN             , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_GLOB_EVENT0_SEL_LEN );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT1_SEL                 , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_GLOB_EVENT1_SEL );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT1_SEL_LEN             , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_GLOB_EVENT1_SEL_LEN );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT2_SEL                 , 26  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_GLOB_EVENT2_SEL );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT2_SEL_LEN             , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_GLOB_EVENT2_SEL_LEN );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT3_SEL                 , 29  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_GLOB_EVENT3_SEL );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT3_SEL_LEN             , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_GLOB_EVENT3_SEL_LEN );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_OUTPUT_PULSE                    , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_OUTPUT_PULSE );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_ACT_MNT_GO_IDLE_PULSE           , 33  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_ACT_MNT_GO_IDLE_PULSE );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_ACT_MNT_GO_IDLE_PULSE_LEN       , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_ACT_MNT_GO_IDLE_PULSE_LEN );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_ACT_SET_SPATTN_PULSE            , 37  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_ACT_SET_SPATTN_PULSE );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_ACT_SET_SPATTN_PULSE_LEN        , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_ACT_SET_SPATTN_PULSE_LEN );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE          , 41  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_ACT_FRC_TB_PULSE_PULSE );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE_LEN      , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_ACT_FRC_TB_PULSE_PULSE_LEN );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_CNT_VALUE                       , 45  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_CNT_VALUE );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_CNT_VALUE_LEN                   , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_CNT_VALUE_LEN );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_TMR_VALUE                       , 51  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_TMR_VALUE );
+REG64_FLD( MCBIST_DBGCFG3Q_CFG_WAT_TMR_VALUE_LEN                   , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_TMR_VALUE_LEN );
+
+REG64_FLD( MCA_DBGR_ECC_DEBUG_ENABLE                               , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_DEBUG_ENABLE );
+REG64_FLD( MCA_DBGR_ECC_DEBUG_CHUNK_SELECT                         , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_DEBUG_CHUNK_SELECT );
+REG64_FLD( MCA_DBGR_ECC_DEBUG_CHUNK_SELECT_LEN                     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_DEBUG_CHUNK_SELECT_LEN );
+REG64_FLD( MCA_DBGR_ECC_DEBUG_PRIMARY_SELECT                       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_DEBUG_PRIMARY_SELECT );
+REG64_FLD( MCA_DBGR_ECC_DEBUG_PRIMARY_SELECT_LEN                   , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_DEBUG_PRIMARY_SELECT_LEN );
+REG64_FLD( MCA_DBGR_ECC_DEBUG_SECONDARY_SELECT                     , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_DEBUG_SECONDARY_SELECT );
+REG64_FLD( MCA_DBGR_ECC_DEBUG_SECONDARY_SELECT_LEN                 , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_DEBUG_SECONDARY_SELECT_LEN );
+REG64_FLD( MCA_DBGR_ECC_WAT_ENABLE                                 , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_WAT_ENABLE );
+REG64_FLD( MCA_DBGR_ECC_WAT_ACTION_SELECT                          , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_WAT_ACTION_SELECT );
+REG64_FLD( MCA_DBGR_ECC_WAT_SOURCE                                 , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_WAT_SOURCE );
+REG64_FLD( MCA_DBGR_ECC_WAT_SOURCE_LEN                             , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_WAT_SOURCE_LEN );
+REG64_FLD( MCA_DBGR_READ_DEBUG_SELECT                              , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_DEBUG_SELECT );
+REG64_FLD( MCA_DBGR_READ_DEBUG_SELECT_LEN                          , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_DEBUG_SELECT_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_0_11               , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_0_11    );
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_0_11_LEN           , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_0_11_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_12_15              , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_12_15   );
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR0_01_12_15_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_12_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_0_11               , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_0_11    );
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_0_11_LEN           , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_0_11_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_12_15              , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_12_15   );
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR1_01_12_15_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_12_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_0_11               , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_0_11    );
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_0_11_LEN           , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_0_11_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_12_15              , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_12_15   );
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR2_23_12_15_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_12_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_0_11               , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_0_11    );
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_0_11_LEN           , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_0_11_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_12_15              , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_12_15   );
+REG64_FLD( MCA_DDRPHY_ADR_BIT_ENABLE_P0_ADR3_23_12_15_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_12_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST   , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_DLL_ADJUST );
+REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ADJUST_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_DLL_ADJUST_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_CORRECT_EN , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_DLL_CORRECT_EN );
+REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_ITER_A   , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_DLL_ITER_A );
+REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S0_ADR0_DLL_COMPARE_OUT , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_DLL_COMPARE_OUT );
+
+REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ADJUST   , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_DLL_ADJUST );
+REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ADJUST_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_DLL_ADJUST_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_CORRECT_EN , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_DLL_CORRECT_EN );
+REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_ITER_A   , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_DLL_ITER_A );
+REG64_FLD( MCA_DDRPHY_ADR_DCD_CONTROL_P0_ADR32S1_ADR1_DLL_COMPARE_OUT , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_DLL_COMPARE_OUT );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01                        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01_LEN                    , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEN     );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01_DELAY1                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY1  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR0_01_DELAY1_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01                        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01_LEN                    , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEN     );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01_DELAY1                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY1  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR1_01_DELAY1_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23                        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23_LEN                    , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEN     );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23_DELAY1                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY1  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR2_23_DELAY1_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23                        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23_LEN                    , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEN     );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23_DELAY1                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY1  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY0_P0_ADR3_23_DELAY1_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY2                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY2  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY2_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY3                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY3  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR0_01_DELAY3_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY2                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY2  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY2_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY3                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY3  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR1_01_DELAY3_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY2                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY2  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY2_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY3                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY3  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR2_23_DELAY3_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY2                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY2  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY2_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY3                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY3  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY1_P0_ADR3_23_DELAY3_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY4                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY4  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY4_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY5                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY5  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR0_01_DELAY5_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY4                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY4  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY4_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY5                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY5  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR1_01_DELAY5_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY4                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY4  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY4_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY5                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY5  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR2_23_DELAY5_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY4                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY4  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY4_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY5                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY5  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY2_P0_ADR3_23_DELAY5_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY6                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY6  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY6_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY7                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY7  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR0_01_DELAY7_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY6                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY6  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY6_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY7                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY7  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR1_01_DELAY7_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY6                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY6  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY6_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY7                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY7  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR2_23_DELAY7_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY6                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY6  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY6_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY7                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY7  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY3_P0_ADR3_23_DELAY7_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY8                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY8  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY8_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY8_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY9                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY9  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR0_01_DELAY9_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY9_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY8                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY8  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY8_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY8_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY9                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY9  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR1_01_DELAY9_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY9_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY8                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY8  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY8_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY8_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY9                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY9  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR2_23_DELAY9_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY9_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY8                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY8  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY8_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY8_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY9                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY9  );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY4_P0_ADR3_23_DELAY9_LEN             , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY9_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY10                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY10 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY10_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY10_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY11                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY11 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR0_01_DELAY11_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY11_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY10                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY10 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY10_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY10_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY11                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY11 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR1_01_DELAY11_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY11_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY10                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY10 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY10_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY10_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY11                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY11 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR2_23_DELAY11_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY11_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY10                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY10 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY10_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY10_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY11                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY11 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY5_P0_ADR3_23_DELAY11_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY11_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY12                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY12 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY12_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY12_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY13                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY13 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR0_01_DELAY13_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY13_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY12                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY12 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY12_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY12_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY13                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY13 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR1_01_DELAY13_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY13_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY12                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY12 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY12_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY12_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY13                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY13 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR2_23_DELAY13_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY13_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY12                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY12 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY12_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY12_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY13                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY13 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY6_P0_ADR3_23_DELAY13_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY13_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY14                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY14 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY14_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY14_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY15                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY15 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR0_01_DELAY15_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY14                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY14 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY14_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY14_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY15                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY15 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR1_01_DELAY15_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY14                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY14 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY14_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY14_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY15                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY15 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR2_23_DELAY15_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY14                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY14 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY14_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY14_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY15                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY15 );
+REG64_FLD( MCA_DDRPHY_ADR_DELAY7_P0_ADR3_23_DELAY15_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_LANE_PAIR_FAIL , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_01_TEST_LANE_PAIR_FAIL );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_LANE_PAIR_FAIL_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_01_TEST_LANE_PAIR_FAIL_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_DATA_EN , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_TEST_DATA_EN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_MODE , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_TEST_MODE );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_MODE_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_TEST_MODE_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_4TO1_MODE , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_TEST_4TO1_MODE );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_RESET , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_TEST_RESET );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_GEN_EN , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_TEST_GEN_EN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_CLEAR_ERROR , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_01_TEST_CLEAR_ERROR );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR0_01_TEST_CHECK_EN , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_TEST_CHECK_EN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_LANE_PAIR_FAIL , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_01_TEST_LANE_PAIR_FAIL );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_LANE_PAIR_FAIL_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_01_TEST_LANE_PAIR_FAIL_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_DATA_EN , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_TEST_DATA_EN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_MODE , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_TEST_MODE );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_MODE_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_TEST_MODE_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_4TO1_MODE , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_TEST_4TO1_MODE );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_RESET , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_TEST_RESET );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_GEN_EN , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_TEST_GEN_EN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_CLEAR_ERROR , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_01_TEST_CLEAR_ERROR );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR1_01_TEST_CHECK_EN , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_TEST_CHECK_EN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_LANE_PAIR_FAIL , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_23_TEST_LANE_PAIR_FAIL );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_LANE_PAIR_FAIL_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_23_TEST_LANE_PAIR_FAIL_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_DATA_EN , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_TEST_DATA_EN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_MODE , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_TEST_MODE );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_MODE_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_TEST_MODE_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_4TO1_MODE , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_TEST_4TO1_MODE );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_RESET , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_TEST_RESET );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_GEN_EN , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_TEST_GEN_EN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_CLEAR_ERROR , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_23_TEST_CLEAR_ERROR );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR2_23_TEST_CHECK_EN , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_TEST_CHECK_EN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_LANE_PAIR_FAIL , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_23_TEST_LANE_PAIR_FAIL );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_LANE_PAIR_FAIL_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_23_TEST_LANE_PAIR_FAIL_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_DATA_EN , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_TEST_DATA_EN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_MODE , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_TEST_MODE );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_MODE_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_TEST_MODE_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_4TO1_MODE , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_TEST_4TO1_MODE );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_RESET , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_TEST_RESET );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_GEN_EN , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_TEST_GEN_EN );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_CLEAR_ERROR , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_23_TEST_CLEAR_ERROR );
+REG64_FLD( MCA_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL_P0_ADR3_23_TEST_CHECK_EN , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_TEST_CHECK_EN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR1       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR1 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR2_ADR3  , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR2_ADR3 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR4_ADR5  , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR4_ADR5 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR6_ADR7  , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR6_ADR7 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR8_ADR9  , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR8_ADR9 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR10_ADR11 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR10_ADR11 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR12_ADR13 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR12_ADR13 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0_01_DI_ADR14_ADR15 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR14_ADR15 );
+
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR0       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR0 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR2_ADR3  , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR2_ADR3 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR4_ADR5  , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR4_ADR5 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR6_ADR7  , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR6_ADR7 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR8_ADR9  , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR8_ADR9 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR10_ADR11 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR10_ADR11 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR12_ADR13 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR12_ADR13 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR1_01_DI_ADR14_ADR15 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DI_ADR14_ADR15 );
+
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR0_ADR1  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR0_ADR1 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR3       , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR3 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR4_ADR5  , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR4_ADR5 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR6_ADR7  , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR6_ADR7 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR8_ADR9  , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR8_ADR9 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR10_ADR11 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR10_ADR11 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR12_ADR13 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR12_ADR13 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2_23_DI_ADR14_ADR15 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR14_ADR15 );
+
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR0_ADR1  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR0_ADR1 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR2       , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR2 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR4_ADR5  , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR4_ADR5 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR6_ADR7  , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR6_ADR7 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR8_ADR9  , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR8_ADR9 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR10_ADR11 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR10_ADR11 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR12_ADR13 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR12_ADR13 );
+REG64_FLD( MCA_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3_23_DI_ADR14_ADR15 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DI_ADR14_ADR15 );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_RESET , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_INIT_RXDLL_CAL_RESET );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_INIT_RXDLL_CAL_UPDATE , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_INIT_RXDLL_CAL_UPDATE );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_CAL_SKIP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FILTER_LENGTH_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FILTER_LENGTH_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_LEAD_LAG_SEPARATION_DC , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_EN_DRIVER_INVFB_DC , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_EN_DRIVER_INVFB_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_RXREG_FINECAL_2XILSB_DC , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_RXREG_FINECAL_2XILSB_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_GOOD        , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_CAL_GOOD );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_ERROR       , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_CAL_ERROR );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S0_ADR0_CAL_ERROR_FINE  , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_CAL_ERROR_FINE );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_RESET , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_INIT_RXDLL_CAL_RESET );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_INIT_RXDLL_CAL_UPDATE , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_INIT_RXDLL_CAL_UPDATE );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_CAL_SKIP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FILTER_LENGTH_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FILTER_LENGTH_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_LEAD_LAG_SEPARATION_DC , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_EN_DRIVER_INVFB_DC , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_EN_DRIVER_INVFB_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_RXREG_FINECAL_2XILSB_DC , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_RXREG_FINECAL_2XILSB_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_GOOD        , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_CAL_GOOD );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_ERROR       , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_CAL_ERROR );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_CNTL_P0_ADR32S1_ADR1_CAL_ERROR_FINE  , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_CAL_ERROR_FINE );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_REGS_RXDLL_VREG );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_REGS_RXDLL_VREG_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_REGS_RXDLL_VREG );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_LOWER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_REGS_RXDLL_VREG_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_REGS_RXDLL_VREG );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S0_ADR0_REGS_RXDLL_VREG_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_REGS_RXDLL_VREG_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_REGS_RXDLL_VREG );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_DAC_UPPER_P0_ADR32S1_ADR1_REGS_RXDLL_VREG_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_REGS_RXDLL_VREG_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S0_ADR0_SLAVE_VREG_OVERRIDE , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_SLAVE_VREG_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S0_ADR0_SLAVE_VREG_REF_SEL_DC , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_SLAVE_VREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S0_ADR0_SLAVE_VREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_SLAVE_VREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S0_ADR0_SLAVE_VREG_DAC_COARSE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_SLAVE_VREG_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S0_ADR0_SLAVE_VREG_DAC_COARSE_LEN , 7   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_SLAVE_VREG_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S1_ADR1_SLAVE_VREG_OVERRIDE , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_SLAVE_VREG_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S1_ADR1_SLAVE_VREG_REF_SEL_DC , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_SLAVE_VREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S1_ADR1_SLAVE_VREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_SLAVE_VREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S1_ADR1_SLAVE_VREG_DAC_COARSE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_SLAVE_VREG_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_EXTRA_P0_ADR32S1_ADR1_SLAVE_VREG_DAC_COARSE_LEN , 7   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_SLAVE_VREG_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0_ADR0     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0       );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S0_ADR0_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_LEN   );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S1_ADR1     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1       );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_LOWER_P0_ADR32S1_ADR1_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_LEN   );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S0_ADR0     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0       );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S0_ADR0_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_LEN   );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1_ADR1     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1       );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SLAVE_VREG_UPPER_P0_ADR32S1_ADR1_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_LEN   );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_OVERRIDE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_CAL_PD_ENABLE , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_CAL_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_MAIN_PD_ENABLE , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_MAIN_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_DETECT_REQ , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR0_DETECT_REQ );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_SLAVE_CAL_CKT_POWERDOWN , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR0_SLAVE_CAL_CKT_POWERDOWN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_VREG_RXCAL_COMP_OUT_META , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR0_VREG_RXCAL_COMP_OUT_META );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_RXCAL_DETECT_DONE_META , 57  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR0_RXCAL_DETECT_DONE_META );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_RXCAL_PD_CAL_LAG_META , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR0_RXCAL_PD_CAL_LAG_META );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_RXCAL_PD_MAIN_LEAD_META , 59  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR0_RXCAL_PD_MAIN_LEAD_META );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_RXCAL_PD_MAIN_LAG_META , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR0_RXCAL_PD_MAIN_LAG_META );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_VREG_SLAVE1_COMP_OUT , 61  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR0_VREG_SLAVE1_COMP_OUT );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S0_ADR0_VREG_SLAVE2_COMP_OUT , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR0_VREG_SLAVE2_COMP_OUT );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_OVERRIDE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_CAL_PD_ENABLE , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_CAL_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_MAIN_PD_ENABLE , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_MAIN_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_DETECT_REQ , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ADR1_DETECT_REQ );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_SLAVE_CAL_CKT_POWERDOWN , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR1_SLAVE_CAL_CKT_POWERDOWN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_VREG_RXCAL_COMP_OUT_META , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR1_VREG_RXCAL_COMP_OUT_META );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_RXCAL_DETECT_DONE_META , 57  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR1_RXCAL_DETECT_DONE_META );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_RXCAL_PD_CAL_LAG_META , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR1_RXCAL_PD_CAL_LAG_META );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_RXCAL_PD_MAIN_LEAD_META , 59  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR1_RXCAL_PD_MAIN_LEAD_META );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_RXCAL_PD_MAIN_LAG_META , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR1_RXCAL_PD_MAIN_LAG_META );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_VREG_SLAVE1_COMP_OUT , 61  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR1_VREG_SLAVE1_COMP_OUT );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_SW_CONTROL_P0_ADR32S1_ADR1_VREG_SLAVE2_COMP_OUT , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ADR1_VREG_SLAVE2_COMP_OUT );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_REGS_RXDLL_EN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_EN_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_REGS_RXDLL_EN_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_DAC , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_REGS_RXDLL_DAC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S0_ADR0_REGS_RXDLL_DAC_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_REGS_RXDLL_DAC_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_REGS_RXDLL_EN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_EN_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_REGS_RXDLL_EN_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_DAC , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_REGS_RXDLL_DAC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_COARSE_P0_ADR32S1_ADR1_REGS_RXDLL_DAC_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_REGS_RXDLL_DAC_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_HS_DLLMUX_SEL_0_3 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_HS_DLLMUX_SEL_0_3 );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_HS_DLLMUX_SEL_0_3_LEN , 4   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_HS_DLLMUX_SEL_0_3_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_ATEST_SEL_0 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_ATEST_SEL_0 );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_ATEST_SEL_0_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_ATEST_SEL_0_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_INTERP_SIG_SLEW , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_INTERP_SIG_SLEW );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_INTERP_SIG_SLEW_LEN , 4   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_INTERP_SIG_SLEW_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S0_ADR0_ANALOG_WRAPON , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_ANALOG_WRAPON );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_HS_DLLMUX_SEL_0_3 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_HS_DLLMUX_SEL_0_3 );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_HS_DLLMUX_SEL_0_3_LEN , 4   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_HS_DLLMUX_SEL_0_3_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_ATEST_SEL_0 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_ATEST_SEL_0 );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_ATEST_SEL_0_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_ATEST_SEL_0_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_INTERP_SIG_SLEW , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_INTERP_SIG_SLEW );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_INTERP_SIG_SLEW_LEN , 4   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_INTERP_SIG_SLEW_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONFIG_1_P0_ADR32S1_ADR1_ANALOG_WRAPON , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_ANALOG_WRAPON );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_COMPCON_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_RXREG_COMPCON_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_COMPCON_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_RXREG_COMPCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_CON_DC , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_RXREG_CON_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_DAC_PULLUP_DC , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_RXREG_DAC_PULLUP_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_DRVCON_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_RXREG_DRVCON_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_DRVCON_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_RXREG_DRVCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_REF_SEL_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_RXREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_RXREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_RXREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S0_ADR0_CAL_CKTS_ACTIVE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_CAL_CKTS_ACTIVE );
+
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_COMPCON_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_RXREG_COMPCON_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_COMPCON_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_RXREG_COMPCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_CON_DC , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_RXREG_CON_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_DAC_PULLUP_DC , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_RXREG_DAC_PULLUP_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_DRVCON_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_RXREG_DRVCON_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_DRVCON_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_RXREG_DRVCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_REF_SEL_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_RXREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_RXREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_RXREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_DLL_VREG_CONTROL_P0_ADR32S1_ADR1_CAL_CKTS_ACTIVE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_CAL_CKTS_ACTIVE );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL0     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL0    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL1     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL1    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL1_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL1_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL2     , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL2    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL2_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL2_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL3     , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL3    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL3_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL3_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL4     , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL4    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL4_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL4_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL5     , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL5    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL5_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL5_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL6     , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL6    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL6_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL6_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL7     , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL7    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0_01_SEL7_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL7_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL0     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL0    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL1     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL1    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL1_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL1_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL2     , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL2    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL2_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL2_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL3     , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL3    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL3_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL3_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL4     , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL4    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL4_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL4_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL5     , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL5    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL5_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL5_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL6     , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL6    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL6_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL6_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL7     , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL7    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1_01_SEL7_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL7_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL0     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL0    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL1     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL1    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL1_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL1_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL2     , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL2    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL2_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL2_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL3     , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL3    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL3_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL3_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL4     , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL4    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL4_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL4_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL5     , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL5    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL5_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL5_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL6     , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL6    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL6_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL6_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL7     , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL7    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2_23_SEL7_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL7_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL0     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL0    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL1     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL1    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL1_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL1_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL2     , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL2    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL2_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL2_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL3     , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL3    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL3_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL3_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL4     , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL4    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL4_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL4_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL5     , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL5    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL5_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL5_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL6     , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL6    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL6_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL6_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL7     , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL7    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3_23_SEL7_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL7_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL8     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL8    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL9     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL9    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL9_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL9_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL10    , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL10   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL10_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL10_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL11    , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL11   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL11_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL11_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL12    , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL12   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL12_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL12_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL13    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL13   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL13_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL13_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL14    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL14   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL14_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL14_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL15    , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL15   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0_01_SEL15_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL8     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL8    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL9     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL9    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL9_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL9_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL10    , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL10   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL10_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL10_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL11    , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL11   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL11_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL11_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL12    , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL12   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL12_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL12_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL13    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL13   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL13_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL13_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL14    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL14   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL14_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL14_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL15    , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL15   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1_01_SEL15_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL8     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL8    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL9     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL9    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL9_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL9_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL10    , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL10   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL10_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL10_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL11    , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL11   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL11_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL11_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL12    , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL12   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL12_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL12_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL13    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL13   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL13_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL13_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL14    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL14   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL14_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL14_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL15    , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL15   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2_23_SEL15_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL8     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL8    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL9     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL9    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL9_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL9_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL10    , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL10   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL10_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL10_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL11    , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL11   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL11_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL11_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL12    , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL12   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL12_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL12_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL13    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL13   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL13_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL13_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL14    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL14   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL14_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL14_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL15    , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL15   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3_23_SEL15_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL0   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL0    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL0_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL0_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL1   , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL1    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL1_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL1_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL2   , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL2    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL2_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL2_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL3   , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL3    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL3_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL3_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL4   , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL4    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL4_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL4_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL5   , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL5    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL5_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL5_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL6   , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL6    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL6_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL6_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL7   , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL7    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0_01_SEL7_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL7_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL0   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL0    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL0_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL0_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL1   , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL1    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL1_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL1_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL2   , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL2    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL2_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL2_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL3   , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL3    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL3_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL3_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL4   , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL4    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL4_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL4_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL5   , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL5    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL5_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL5_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL6   , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL6    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL6_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL6_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL7   , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL7    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1_01_SEL7_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL7_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL0   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL0    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL0_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL0_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL1   , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL1    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL1_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL1_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL2   , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL2    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL2_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL2_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL3   , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL3    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL3_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL3_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL4   , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL4    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL4_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL4_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL5   , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL5    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL5_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL5_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL6   , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL6    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL6_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL6_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL7   , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL7    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2_23_SEL7_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL7_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL0   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL0    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL0_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL0_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL1   , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL1    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL1_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL1_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL2   , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL2    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL2_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL2_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL3   , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL3    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL3_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL3_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL4   , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL4    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL4_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL4_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL5   , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL5    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL5_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL5_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL6   , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL6    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL6_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL6_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL7   , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL7    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3_23_SEL7_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL7_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL8   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL8    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL8_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL8_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL9   , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL9    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL9_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL9_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL10  , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL10   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL10_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL10_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL11  , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL11   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL11_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL11_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL12  , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL12   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL12_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL12_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL13  , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL13   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL13_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL13_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL14  , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL14   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL14_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL14_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL15  , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL15   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0_01_SEL15_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL8   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL8    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL8_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL8_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL9   , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL9    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL9_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL9_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL10  , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL10   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL10_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL10_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL11  , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL11   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL11_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL11_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL12  , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL12   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL12_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL12_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL13  , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL13   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL13_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL13_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL14  , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL14   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL14_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL14_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL15  , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL15   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1_01_SEL15_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL8   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL8    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL8_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL8_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL9   , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL9    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL9_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL9_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL10  , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL10   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL10_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL10_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL11  , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL11   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL11_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL11_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL12  , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL12   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL12_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL12_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL13  , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL13   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL13_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL13_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL14  , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL14   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL14_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL14_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL15  , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL15   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2_23_SEL15_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL8   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL8    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL8_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL8_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL9   , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL9    );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL9_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL9_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL10  , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL10   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL10_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL10_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL11  , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL11   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL11_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL11_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL12  , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL12   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL12_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL12_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL13  , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL13   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL13_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL13_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL14  , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL14   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL14_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL14_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL15  , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL15   );
+REG64_FLD( MCA_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3_23_SEL15_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL15_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0_ADR0_TSYS , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_TSYS  );
+REG64_FLD( MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0_ADR0_TSYS_LEN , 7   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_TSYS_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1_ADR1_TSYS , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_TSYS  );
+REG64_FLD( MCA_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S1_ADR1_TSYS_LEN , 7   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_TSYS_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0_ADR0_VALUE , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_VALUE );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0_ADR0_VALUE_LEN , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1_ADR1_VALUE , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_VALUE );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1_ADR1_VALUE_LEN , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0_ADR0_VALUE , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_VALUE );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S0_ADR0_VALUE_LEN , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1_ADR1_VALUE , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_VALUE );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE1_P0_ADR32S1_ADR1_VALUE_LEN , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_FLUSH , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_FLUSH );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_EN , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_EN    );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_INIT_IO , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_INIT_IO );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_A_SEL_0_3 , 51  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_HS_PROBE_A_SEL_0_3 );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_A_SEL_0_3_LEN , 4   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_HS_PROBE_A_SEL_0_3_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_B_SEL_0_3 , 55  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_HS_PROBE_B_SEL_0_3 );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_HS_PROBE_B_SEL_0_3_LEN , 4   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_HS_PROBE_B_SEL_0_3_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_ATESTSEL_0_2 , 59  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_ATESTSEL_0_2 );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0_ADR0_ATESTSEL_0_2_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR0_ATESTSEL_0_2_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_FLUSH , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_FLUSH );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_EN , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_EN    );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_INIT_IO , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_INIT_IO );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_A_SEL_0_3 , 51  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_HS_PROBE_A_SEL_0_3 );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_A_SEL_0_3_LEN , 4   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_HS_PROBE_A_SEL_0_3_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_B_SEL_0_3 , 55  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_HS_PROBE_B_SEL_0_3 );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_HS_PROBE_B_SEL_0_3_LEN , 4   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_HS_PROBE_B_SEL_0_3_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_ATESTSEL_0_2 , 59  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_ATESTSEL_0_2 );
+REG64_FLD( MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1_ADR1_ATESTSEL_0_2_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ADR1_ATESTSEL_0_2_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__0_11_PD     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LANE__0_11_PD );
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__0_11_PD_LEN , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LANE__0_11_PD_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__12_15_PD    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LANE__12_15_PD );
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR0_01_LANE__12_15_PD_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LANE__12_15_PD_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__0_11_PD     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LANE__0_11_PD );
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__0_11_PD_LEN , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LANE__0_11_PD_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__12_15_PD    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LANE__12_15_PD );
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR1_01_LANE__12_15_PD_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LANE__12_15_PD_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__0_11_PD     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LANE__0_11_PD );
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__0_11_PD_LEN , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LANE__0_11_PD_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__12_15_PD    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LANE__12_15_PD );
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR2_23_LANE__12_15_PD_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LANE__12_15_PD_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__0_11_PD     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LANE__0_11_PD );
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__0_11_PD_LEN , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LANE__0_11_PD_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__12_15_PD    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LANE__12_15_PD );
+REG64_FLD( MCA_DDRPHY_ADR_POWERDOWN_2_P0_ADR3_23_LANE__12_15_PD_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LANE__12_15_PD_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_START      , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_START );
+REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_OVERRIDE_EN , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_OVERRIDE_EN );
+REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_OVERRIDE   , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_OVERRIDE_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_OVERRIDE_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_TARGET_PR_OFFSET , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_TARGET_PR_OFFSET );
+REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_TARGET_PR_OFFSET_LEN , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_TARGET_PR_OFFSET_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_START      , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_START );
+REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_OVERRIDE_EN , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_OVERRIDE_EN );
+REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_OVERRIDE   , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_OVERRIDE_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_OVERRIDE_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_TARGET_PR_OFFSET , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_TARGET_PR_OFFSET );
+REG64_FLD( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_ADR1_TARGET_PR_OFFSET_LEN , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_TARGET_PR_OFFSET_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_ROT_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_ROT_OVERRIDE_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_ROT_OVERRIDE_EN , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_ROT_OVERRIDE_EN );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_PHASE_ALIGN_RESET , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_PHASE_ALIGN_RESET );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_PHASE_EN  , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_PHASE_EN );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_PHASE_DEFAULT_EN , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_PHASE_DEFAULT_EN );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_POS_EDGE_ALIGN , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_POS_EDGE_ALIGN );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_ADR0_CONTINUOUS_UPDATE , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR0_CONTINUOUS_UPDATE );
+
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_ROT_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_ROT_OVERRIDE_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_ROT_OVERRIDE_EN , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_ROT_OVERRIDE_EN );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_PHASE_ALIGN_RESET , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_PHASE_ALIGN_RESET );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_PHASE_EN  , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_PHASE_EN );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_PHASE_DEFAULT_EN , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_PHASE_DEFAULT_EN );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_POS_EDGE_ALIGN , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_POS_EDGE_ALIGN );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_ADR1_CONTINUOUS_UPDATE , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR1_CONTINUOUS_UPDATE );
+
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_ROT   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADR0_ROT   );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_ROT_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADR0_ROT_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_BB_LOCK , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADR0_BB_LOCK );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_SLEW_DONE_STATUS , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_ADR0_SLEW_DONE_STATUS );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_ADR0_SLEW_DONE_STATUS_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_ADR0_SLEW_DONE_STATUS_LEN );
+
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_ROT   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADR1_ROT   );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_ROT_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADR1_ROT_LEN );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_BB_LOCK , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADR1_BB_LOCK );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_SLEW_DONE_STATUS , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_ADR1_SLEW_DONE_STATUS );
+REG64_FLD( MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_ADR1_SLEW_DONE_STATUS_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_ADR1_SLEW_DONE_STATUS_LEN );
+
+REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_CNTL                    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNTL       );
+REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_CNTL_LEN                , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNTL_LEN   );
+REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR0         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_INJECT_FIR_ERR0 );
+REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR1         , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_INJECT_FIR_ERR1 );
+REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR2         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_INJECT_FIR_ERR2 );
+REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR3         , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_INJECT_FIR_ERR3 );
+REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_INJECT_FIR_ERR4         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_INJECT_FIR_ERR4 );
+REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_VPROTH_CTL              , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPROTH_CTL );
+REG64_FLD( MCA_DDRPHY_APB_ATEST_MUX_SEL_P0_VPROTH_CTL_LEN          , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPROTH_CTL_LEN );
+
+REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_DISABLE_PARITY_CHECKER        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_PARITY_CHECKER );
+REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_RESET_ERR_RPT                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESET_ERR_RPT );
+REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_FORCE_ON_CLK_GATE             , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_ON_CLK_GATE );
+REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL                 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEBUG_BUS_SEL );
+REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL_LEN             , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEBUG_BUS_SEL_LEN );
+REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_ADR_SLAVE_SEL                 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADR_SLAVE_SEL );
+REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL2                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEBUG_BUS_SEL2 );
+REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_DEBUG_BUS_SEL2_LEN            , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEBUG_BUS_SEL2_LEN );
+REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_LOW_PROBE_TRACE_GATE          , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOW_PROBE_TRACE_GATE );
+REG64_FLD( MCA_DDRPHY_APB_CONFIG0_P0_HS_PROBE_TOP_SEL              , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HS_PROBE_TOP_SEL );
+
+REG64_FLD( MCA_DDRPHY_APB_ERROR_MASK0_P0_INVALID_ADDRESS_MASK      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_INVALID_ADDRESS_MASK );
+REG64_FLD( MCA_DDRPHY_APB_ERROR_MASK0_P0_WR_PAR_ERR_MASK           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WR_PAR_ERR_MASK );
+
+REG64_FLD( MCA_DDRPHY_APB_ERROR_STATUS0_P0_INVALID_ADDRESS         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_INVALID_ADDRESS );
+REG64_FLD( MCA_DDRPHY_APB_ERROR_STATUS0_P0_WR_PAR_ERR              , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_PAR_ERR );
+
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET0                     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR_SET0   );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET1                     , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR_SET1   );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET2                     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR_SET2   );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET3                     , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR_SET3   );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET4                     , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR_SET4   );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_SET5                     , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR_SET5   );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP16                 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR_FSM_DP16 );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_ERR_FSM_DP16_LEN             , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR_FSM_DP16_LEN );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_PC_ERR_STATUS0               , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_ERR_STATUS0 );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR0_P0_PC_ERR_STATUS0_LEN           , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_ERR_STATUS0_LEN );
+
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR              , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_INIT_CAL_ERR );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_PC_INIT_CAL_ERR_LEN          , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_INIT_CAL_ERR_LEN );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_DP_DLL_CAL_ERROR             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DP_DLL_CAL_ERROR );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_DP_DLL_CAL_ERROR_FINE        , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DP_DLL_CAL_ERROR_FINE );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_ADR_DLL_CAL_ERROR            , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADR_DLL_CAL_ERROR );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR1_P0_ADR_DLL_CAL_ERROR_FINE       , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADR_DLL_CAL_ERROR_FINE );
+
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR2_P0_ERR0_REG_DP16                , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR0_REG_DP16 );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR2_P0_ERR0_REG_DP16_LEN            , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR0_REG_DP16_LEN );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR2_P0_ERR1_REG_DP16                , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR1_REG_DP16 );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR2_P0_ERR1_REG_DP16_LEN            , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR1_REG_DP16_LEN );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR2_P0_REG_DP16                     , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_REG_DP16   );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR2_P0_REG_DP16_LEN                 , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_REG_DP16_LEN );
+
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR3_P0_REG_DP16                     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_REG_DP16   );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR3_P0_REG_DP16_LEN                 , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_REG_DP16_LEN );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR3_P0_ERR4_REG_DP16                , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR4_REG_DP16 );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR3_P0_ERR4_REG_DP16_LEN            , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR4_REG_DP16_LEN );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR3_P0_ERR5_REG_DP16                , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR5_REG_DP16 );
+REG64_FLD( MCA_DDRPHY_APB_FIR_ERR3_P0_ERR5_REG_DP16_LEN            , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERR5_REG_DP16_LEN );
+
+REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_RESET_0                  , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_RESET_0    );
+REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_HOLD_0                   , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_0     );
+REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_0                        , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_0_LEN                    , 6   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_0_LEN      );
+REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_RESET_1                  , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_RESET_1    );
+REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_HOLD_1                   , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_1     );
+REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_1                        , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( MCA_DDRPHY_APB_LO_PROBE_SEL_P0_1_LEN                    , 6   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_1_LEN      );
+
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S0ACENSLICENDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICENDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S0ACENSLICENDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S0ACENSLICEPDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S0ACENSLICEPDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPTERM_DC , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S0ACENSLICEPTERM_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_0_01_S0ACENSLICEPTERM_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S0ACENSLICEPTERM_DC_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICENDRV_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S0ACENSLICENDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICENDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S0ACENSLICENDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPDRV_DC , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S0ACENSLICEPDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S0ACENSLICEPDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S0ACENSLICEPTERM_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_1_01_S0ACENSLICEPTERM_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S0ACENSLICEPTERM_DC_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICENDRV_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S0ACENSLICENDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICENDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S0ACENSLICENDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPDRV_DC , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S0ACENSLICEPDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S0ACENSLICEPDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPTERM_DC , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S0ACENSLICEPTERM_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_2_23_S0ACENSLICEPTERM_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S0ACENSLICEPTERM_DC_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICENDRV_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S0ACENSLICENDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICENDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S0ACENSLICENDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPDRV_DC , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S0ACENSLICEPDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S0ACENSLICEPDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPTERM_DC , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S0ACENSLICEPTERM_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_3_23_S0ACENSLICEPTERM_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S0ACENSLICEPTERM_DC_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICENDRV_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_S0ACENSLICENDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICENDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_S0ACENSLICENDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPDRV_DC , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_S0ACENSLICEPDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_S0ACENSLICEPDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPTERM_DC , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_S0ACENSLICEPTERM_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE0_P0_4_4_S0ACENSLICEPTERM_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_S0ACENSLICEPTERM_DC_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICENDRV_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S1ACENSLICENDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICENDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S1ACENSLICENDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPDRV_DC , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S1ACENSLICEPDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S1ACENSLICEPDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPTERM_DC , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S1ACENSLICEPTERM_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_0_01_S1ACENSLICEPTERM_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S1ACENSLICEPTERM_DC_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICENDRV_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S1ACENSLICENDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICENDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S1ACENSLICENDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPDRV_DC , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S1ACENSLICEPDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S1ACENSLICEPDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPTERM_DC , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S1ACENSLICEPTERM_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_1_01_S1ACENSLICEPTERM_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S1ACENSLICEPTERM_DC_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICENDRV_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S1ACENSLICENDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICENDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S1ACENSLICENDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPDRV_DC , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S1ACENSLICEPDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S1ACENSLICEPDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPTERM_DC , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S1ACENSLICEPTERM_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_2_23_S1ACENSLICEPTERM_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S1ACENSLICEPTERM_DC_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICENDRV_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S1ACENSLICENDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICENDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S1ACENSLICENDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPDRV_DC , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S1ACENSLICEPDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S1ACENSLICEPDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPTERM_DC , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S1ACENSLICEPTERM_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_3_23_S1ACENSLICEPTERM_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S1ACENSLICEPTERM_DC_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICENDRV_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_S1ACENSLICENDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICENDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_S1ACENSLICENDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPDRV_DC , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_S1ACENSLICEPDRV_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPDRV_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_S1ACENSLICEPDRV_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPTERM_DC , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_S1ACENSLICEPTERM_DC );
+REG64_FLD( MCA_DDRPHY_DP16_ACBOOST_CTL_BYTE1_P0_4_4_S1ACENSLICEPTERM_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_S1ACENSLICEPTERM_DC_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_2_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_2_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES  , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_2_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_2_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_2_DQSEL_RES_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_1_3_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_1_3_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_1_3_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_0_01_NIB_1_3_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_1_3_DQSEL_RES_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_CAP , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_0_2_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_0_2_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_RES , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_0_2_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_0_2_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_0_2_DQSEL_RES_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_CAP  , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_3_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_3_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_RES  , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_3_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_1_01_NIB_3_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_3_DQSEL_RES_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_CAP  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_RES  , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_0_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_DQSEL_RES_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_CAP , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_3_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_3_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_RES , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_3_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_2_23_NIB_1_3_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_3_DQSEL_RES_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_CAP , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_2_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_2_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_RES , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_2_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_0_2_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_2_DQSEL_RES_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_CAP  , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_RES  , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_3_23_NIB_1_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_DQSEL_RES_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_CAP , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_0_2_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_0_2_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_RES , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_0_2_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_0_2_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_0_2_DQSEL_RES_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_CAP , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_1_3_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_1_3_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_RES , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_1_3_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE0_P0_4_4_NIB_1_3_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_1_3_DQSEL_RES_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_CAP  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_2_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_2_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_RES  , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_2_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_2_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_2_DQSEL_RES_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_CAP , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_1_3_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_1_3_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_RES , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_1_3_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_0_01_NIB_1_3_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_1_3_DQSEL_RES_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_CAP , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_0_2_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_0_2_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_RES , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_0_2_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_0_2_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_0_2_DQSEL_RES_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_CAP  , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_3_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_3_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_RES  , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_3_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_1_01_NIB_3_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB_3_DQSEL_RES_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_CAP  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_RES  , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_0_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_DQSEL_RES_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_CAP , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_3_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_3_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_RES , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_3_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_2_23_NIB_1_3_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_3_DQSEL_RES_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_CAP , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_2_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_2_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_RES , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_2_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_0_2_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_0_2_DQSEL_RES_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_CAP  , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_RES  , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_3_23_NIB_1_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB_1_DQSEL_RES_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_CAP , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_0_2_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_0_2_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_RES , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_0_2_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_0_2_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_0_2_DQSEL_RES_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_CAP , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_1_3_DQSEL_CAP );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_CAP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_1_3_DQSEL_CAP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_RES , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_1_3_DQSEL_RES );
+REG64_FLD( MCA_DDRPHY_DP16_CTLE_CTL_BYTE1_P0_4_4_NIB_1_3_DQSEL_RES_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB_1_3_DQSEL_RES_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_0_01_DIR_15            , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DIR_15  );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_0_01_DIR_15_LEN        , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DIR_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_1_01_DIR_0_15          , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DIR_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_1_01_DIR_0_15_LEN      , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DIR_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_2_23_DIR_0_15          , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DIR_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_2_23_DIR_0_15_LEN      , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DIR_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_3_23_DIR_0_15          , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DIR_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_3_23_DIR_0_15_LEN      , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DIR_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_4_4_DIR_0_15           , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DIR_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR0_P0_4_4_DIR_0_15_LEN       , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DIR_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_FLUSH             , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_FLUSH   );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_FORCE_DQS_LANES_ON , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_FORCE_DQS_LANES_ON );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_DD2_FIX_DIS       , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DD2_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_INIT_IO           , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INIT_IO );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_ADVANCE_PING_PONG , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ADVANCE_PING_PONG );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_WL_ADVANCE_DISABLE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ADVANCE_DISABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_DISABLE_PING_PONG , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_PING_PONG );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_DELAY_PING_PONG_HALF , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY_PING_PONG_HALF );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_ATESTSEL_4        , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ATESTSEL_4 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_ATESTSEL_4_LEN    , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ATESTSEL_4_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_FLUSH             , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_FLUSH   );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_FORCE_DQS_LANES_ON , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_FORCE_DQS_LANES_ON );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_DD2_FIX_DIS       , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DD2_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_INIT_IO           , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INIT_IO );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_ADVANCE_PING_PONG , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ADVANCE_PING_PONG );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_WL_ADVANCE_DISABLE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ADVANCE_DISABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_DISABLE_PING_PONG , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_PING_PONG );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_DELAY_PING_PONG_HALF , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAY_PING_PONG_HALF );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_ATESTSEL_0_4      , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ATESTSEL_0_4 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_1_01_ATESTSEL_0_4_LEN  , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ATESTSEL_0_4_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_FLUSH             , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_FLUSH   );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_FORCE_DQS_LANES_ON , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_FORCE_DQS_LANES_ON );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_DD2_FIX_DIS       , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DD2_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_INIT_IO           , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INIT_IO );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_ADVANCE_PING_PONG , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ADVANCE_PING_PONG );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_WL_ADVANCE_DISABLE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ADVANCE_DISABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_DISABLE_PING_PONG , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_PING_PONG );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_DELAY_PING_PONG_HALF , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY_PING_PONG_HALF );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_ATESTSEL_0_4      , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ATESTSEL_0_4 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_2_23_ATESTSEL_0_4_LEN  , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ATESTSEL_0_4_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_FLUSH             , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_FLUSH   );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_FORCE_DQS_LANES_ON , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_FORCE_DQS_LANES_ON );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_DD2_FIX_DIS       , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DD2_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_INIT_IO           , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INIT_IO );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_ADVANCE_PING_PONG , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ADVANCE_PING_PONG );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_WL_ADVANCE_DISABLE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ADVANCE_DISABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_DISABLE_PING_PONG , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_PING_PONG );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_DELAY_PING_PONG_HALF , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAY_PING_PONG_HALF );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_ATESTSEL_0_4      , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ATESTSEL_0_4 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_3_23_ATESTSEL_0_4_LEN  , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ATESTSEL_0_4_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_FLUSH              , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_FLUSH    );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_FORCE_DQS_LANES_ON , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_FORCE_DQS_LANES_ON );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_DD2_FIX_DIS        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DD2_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_INIT_IO            , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_INIT_IO  );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_ADVANCE_PING_PONG  , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ADVANCE_PING_PONG );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_WL_ADVANCE_DISABLE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_WL_ADVANCE_DISABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_DISABLE_PING_PONG  , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_PING_PONG );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_DELAY_PING_PONG_HALF , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAY_PING_PONG_HALF );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_ATESTSEL_0         , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ATESTSEL_0 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_4_4_ATESTSEL_0_LEN     , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ATESTSEL_0_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_0_01_DISABLE_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_0_01_DISABLE_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_1_01_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_1_01_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_2_23_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_2_23_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_3_23_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_3_23_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_4_4_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_4_4_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_0_01_DISABLE_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_0_01_DISABLE_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_1_01_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_1_01_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_2_23_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_2_23_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_3_23_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_3_23_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_4_4_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_4_4_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_0_01_DISABLE_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_0_01_DISABLE_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_1_01_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_1_01_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_2_23_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_2_23_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_3_23_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_3_23_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_4_4_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_4_4_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_0_01_DISABLE_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_0_01_DISABLE_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_1_01_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_1_01_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_2_23_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_2_23_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_3_23_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_3_23_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_4_4_DISABLE_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_4_4_DISABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_0_01_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_0_01_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_1_01_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_1_01_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_2_23_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_2_23_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_3_23_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_3_23_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_4_4_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP0_P0_4_4_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_0_01_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_0_01_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_1_01_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_1_01_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_2_23_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_2_23_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_3_23_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_3_23_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_4_4_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP1_P0_4_4_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_0_01_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_0_01_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_1_01_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_1_01_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_2_23_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_2_23_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_3_23_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_3_23_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_4_4_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP2_P0_4_4_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_0_01_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_0_01_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_1_01_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_1_01_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_2_23_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_2_23_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_3_23_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_3_23_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_4_4_DISABLE_16_23 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_DISABLE1_RP3_P0_4_4_DISABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_0_01_ENABLE_15      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ENABLE_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_0_01_ENABLE_15_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ENABLE_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_1_01_ENABLE_0_15    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ENABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_1_01_ENABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ENABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_2_23_ENABLE_0_15    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ENABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_2_23_ENABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ENABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_3_23_ENABLE_0_15    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ENABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_3_23_ENABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ENABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_4_4_ENABLE_0_15     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ENABLE_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE0_P0_4_4_ENABLE_0_15_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ENABLE_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_ENABLE_16_23   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ENABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_ENABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ENABLE_16_23_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_DFT_FORCE_OUTPUTS , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DFT_FORCE_OUTPUTS );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_DFT_PRBS7_GEN_EN , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DFT_PRBS7_GEN_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_WRAPSEL        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WRAPSEL );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_HW_VALUE       , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HW_VALUE );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N0     , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MRS_CMD_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N1     , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MRS_CMD_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N2     , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MRS_CMD_N2 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_0_01_MRS_CMD_N3     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MRS_CMD_N3 );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_ENABLE_16_23   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ENABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_ENABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ENABLE_16_23_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_DFT_FORCE_OUTPUTS , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DFT_FORCE_OUTPUTS );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_DFT_PRBS7_GEN_EN , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DFT_PRBS7_GEN_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_WRAPSEL        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WRAPSEL );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_HW_VALUE       , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HW_VALUE );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_MRS_CMD_N0     , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MRS_CMD_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_MRS_CMD_N1     , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MRS_CMD_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_MRS_CMD_N2     , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MRS_CMD_N2 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_1_01_MRS_CMD_N3     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MRS_CMD_N3 );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_ENABLE_16_23   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ENABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_ENABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ENABLE_16_23_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_DFT_FORCE_OUTPUTS , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DFT_FORCE_OUTPUTS );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_DFT_PRBS7_GEN_EN , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DFT_PRBS7_GEN_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_WRAPSEL        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WRAPSEL );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_HW_VALUE       , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HW_VALUE );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_MRS_CMD_N0     , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MRS_CMD_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_MRS_CMD_N1     , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MRS_CMD_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_MRS_CMD_N2     , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MRS_CMD_N2 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_2_23_MRS_CMD_N3     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MRS_CMD_N3 );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_ENABLE_16_23   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ENABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_ENABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ENABLE_16_23_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_DFT_FORCE_OUTPUTS , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DFT_FORCE_OUTPUTS );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_DFT_PRBS7_GEN_EN , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DFT_PRBS7_GEN_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_WRAPSEL        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WRAPSEL );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_HW_VALUE       , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HW_VALUE );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_MRS_CMD_N0     , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MRS_CMD_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_MRS_CMD_N1     , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MRS_CMD_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_MRS_CMD_N2     , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MRS_CMD_N2 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_3_23_MRS_CMD_N3     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MRS_CMD_N3 );
+
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_ENABLE_16_23    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ENABLE_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_ENABLE_16_23_LEN , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ENABLE_16_23_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_DFT_FORCE_OUTPUTS , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DFT_FORCE_OUTPUTS );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_DFT_PRBS7_GEN_EN , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DFT_PRBS7_GEN_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_WRAPSEL         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_WRAPSEL  );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_HW_VALUE        , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_HW_VALUE );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_MRS_CMD_N0      , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MRS_CMD_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_MRS_CMD_N1      , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MRS_CMD_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_MRS_CMD_N2      , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MRS_CMD_N2 );
+REG64_FLD( MCA_DDRPHY_DP16_DATA_BIT_ENABLE1_P0_4_4_MRS_CMD_N3      , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MRS_CMD_N3 );
+
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ADJUST         , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_ADJUST );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ADJUST_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_ADJUST_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_CORRECT_EN     , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_CORRECT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_ITER_A         , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_ITER_A );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_0_01_DLL_COMPARE_OUT    , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_COMPARE_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ADJUST         , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_ADJUST );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ADJUST_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_ADJUST_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_CORRECT_EN     , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_CORRECT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_ITER_A         , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_ITER_A );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_1_01_DLL_COMPARE_OUT    , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_COMPARE_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ADJUST         , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_ADJUST );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ADJUST_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_ADJUST_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_CORRECT_EN     , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_CORRECT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_ITER_A         , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_ITER_A );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_2_23_DLL_COMPARE_OUT    , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_COMPARE_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ADJUST         , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_ADJUST );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ADJUST_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_ADJUST_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_CORRECT_EN     , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_CORRECT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_ITER_A         , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_ITER_A );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_3_23_DLL_COMPARE_OUT    , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_COMPARE_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ADJUST          , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DLL_ADJUST );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ADJUST_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DLL_ADJUST_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_CORRECT_EN      , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DLL_CORRECT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_ITER_A          , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DLL_ITER_A );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL0_P0_4_4_DLL_COMPARE_OUT     , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DLL_COMPARE_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ADJUST         , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_ADJUST );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ADJUST_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_ADJUST_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_CORRECT_EN     , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_CORRECT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_ITER_A         , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_ITER_A );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_0_01_DLL_COMPARE_OUT    , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_COMPARE_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ADJUST         , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_ADJUST );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ADJUST_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_ADJUST_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_CORRECT_EN     , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_CORRECT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_ITER_A         , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_ITER_A );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_1_01_DLL_COMPARE_OUT    , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DLL_COMPARE_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ADJUST         , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_ADJUST );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ADJUST_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_ADJUST_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_CORRECT_EN     , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_CORRECT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_ITER_A         , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_ITER_A );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_2_23_DLL_COMPARE_OUT    , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_COMPARE_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ADJUST         , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_ADJUST );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ADJUST_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_ADJUST_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_CORRECT_EN     , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_CORRECT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_ITER_A         , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_ITER_A );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_3_23_DLL_COMPARE_OUT    , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DLL_COMPARE_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ADJUST          , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DLL_ADJUST );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ADJUST_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DLL_ADJUST_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_CORRECT_EN      , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DLL_CORRECT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_ITER_A          , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DLL_ITER_A );
+REG64_FLD( MCA_DDRPHY_DP16_DCD_CONTROL1_P0_4_4_DLL_COMPARE_OUT     , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DLL_COMPARE_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_A            , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_PROBE_A );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_A_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_PROBE_A_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_B            , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_PROBE_B );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_HS_PROBE_B_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_PROBE_B_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_RD                    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_0_01_RD_LEN                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_A            , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_PROBE_A );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_A_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_PROBE_A_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_B            , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_PROBE_B );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_HS_PROBE_B_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_PROBE_B_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_RD                    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_1_01_RD_LEN                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_A            , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_PROBE_A );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_A_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_PROBE_A_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_B            , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_PROBE_B );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_HS_PROBE_B_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_PROBE_B_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_RD                    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_2_23_RD_LEN                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_A            , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_PROBE_A );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_A_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_PROBE_A_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_B            , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_PROBE_B );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_HS_PROBE_B_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_PROBE_B_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_RD                    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_3_23_RD_LEN                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_A             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_HS_PROBE_A );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_A_LEN         , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_HS_PROBE_A_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_B             , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_HS_PROBE_B );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_HS_PROBE_B_LEN         , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_HS_PROBE_B_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_RD                     , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_DEBUG_SEL_P0_4_4_RD_LEN                 , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD0        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD0_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD1        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD1_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD2        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD2_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD3        , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_0_01_QUAD3_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD0        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD0_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD1        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD1_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD2        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD2_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD3        , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_1_01_QUAD3_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD0        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD0_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD1        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD1_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD2        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD2_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD3        , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_2_23_QUAD3_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD0        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD0_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD1        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD1_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD2        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD2_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD3        , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3   );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_3_23_QUAD3_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD0         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0    );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD0_LEN     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD1         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1    );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD1_LEN     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD2         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2    );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD2_LEN     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD3         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3    );
+REG64_FLD( MCA_DDRPHY_DP16_DELAY_LINE_PWR_CTL_P0_4_4_QUAD3_LEN     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_DIGITAL_EN          , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DIGITAL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_BUMP                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BUMP    );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_TRIG_PERIOD         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_TRIG_PERIOD );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_CNTL_POL            , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CNTL_POL );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_0_01_CNTL_SRC            , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CNTL_SRC );
+
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_DIGITAL_EN          , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DIGITAL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_BUMP                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BUMP    );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_TRIG_PERIOD         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_TRIG_PERIOD );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_CNTL_POL            , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CNTL_POL );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_1_01_CNTL_SRC            , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CNTL_SRC );
+
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_DIGITAL_EN          , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DIGITAL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_BUMP                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BUMP    );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_TRIG_PERIOD         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_TRIG_PERIOD );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_CNTL_POL            , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CNTL_POL );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_2_23_CNTL_SRC            , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CNTL_SRC );
+
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_DIGITAL_EN          , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DIGITAL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_BUMP                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BUMP    );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_TRIG_PERIOD         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_TRIG_PERIOD );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_CNTL_POL            , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CNTL_POL );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_3_23_CNTL_SRC            , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CNTL_SRC );
+
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_DIGITAL_EN           , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DIGITAL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_BUMP                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_BUMP     );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_TRIG_PERIOD          , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_TRIG_PERIOD );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_CNTL_POL             , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CNTL_POL );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_DIG_EYE_P0_4_4_CNTL_SRC             , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CNTL_SRC );
+
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_CHECKER_ENABLE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CHECKER_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_CHECKER_RESET   , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CHECKER_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_SYNC            , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_SYNC    );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_SYNC_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_SYNC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_ERROR           , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_ERROR   );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_0_01_ERROR_LEN       , 6   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_ERROR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_CHECKER_ENABLE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CHECKER_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_CHECKER_RESET   , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CHECKER_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_SYNC            , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_SYNC    );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_SYNC_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_SYNC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_ERROR           , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_ERROR   );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_1_01_ERROR_LEN       , 6   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_ERROR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_CHECKER_ENABLE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CHECKER_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_CHECKER_RESET   , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CHECKER_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_SYNC            , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_SYNC    );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_SYNC_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_SYNC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_ERROR           , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_ERROR   );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_2_23_ERROR_LEN       , 6   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_ERROR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_CHECKER_ENABLE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CHECKER_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_CHECKER_RESET   , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CHECKER_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_SYNC            , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_SYNC    );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_SYNC_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_SYNC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_ERROR           , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_ERROR   );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_3_23_ERROR_LEN       , 6   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_ERROR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_CHECKER_ENABLE   , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_CHECKER_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_CHECKER_RESET    , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_CHECKER_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_SYNC             , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_SYNC     );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_SYNC_LEN         , 6   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_SYNC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_ERROR            , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_ERROR    );
+REG64_FLD( MCA_DDRPHY_DP16_DFT_WRAP_STATUS_P0_4_4_ERROR_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_ERROR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_RESET  , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_INIT_RXDLL_CAL_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_INIT_RXDLL_CAL_UPDATE , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_INIT_RXDLL_CAL_UPDATE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP   , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_REGS_RXDLL_CAL_SKIP );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_FILTER_LENGTH_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_EN_DRIVER_INVFB_DC    , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_EN_DRIVER_INVFB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_RXREG_FINECAL_2XILSB_DC , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_FINECAL_2XILSB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_GOOD              , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_GOOD );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_ERROR             , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_ERROR );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_0_01_CAL_ERROR_FINE        , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_ERROR_FINE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_RESET  , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_INIT_RXDLL_CAL_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_INIT_RXDLL_CAL_UPDATE , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_INIT_RXDLL_CAL_UPDATE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP   , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_REGS_RXDLL_CAL_SKIP );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_FILTER_LENGTH_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_EN_DRIVER_INVFB_DC    , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_EN_DRIVER_INVFB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_RXREG_FINECAL_2XILSB_DC , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_FINECAL_2XILSB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_GOOD              , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_GOOD );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_ERROR             , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_ERROR );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_1_01_CAL_ERROR_FINE        , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_ERROR_FINE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_RESET  , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_INIT_RXDLL_CAL_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_INIT_RXDLL_CAL_UPDATE , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_INIT_RXDLL_CAL_UPDATE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP   , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_REGS_RXDLL_CAL_SKIP );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_FILTER_LENGTH_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_EN_DRIVER_INVFB_DC    , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_EN_DRIVER_INVFB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_RXREG_FINECAL_2XILSB_DC , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_FINECAL_2XILSB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_GOOD              , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_GOOD );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_ERROR             , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_ERROR );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_2_23_CAL_ERROR_FINE        , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_ERROR_FINE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_RESET  , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_INIT_RXDLL_CAL_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_INIT_RXDLL_CAL_UPDATE , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_INIT_RXDLL_CAL_UPDATE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP   , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_REGS_RXDLL_CAL_SKIP );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_FILTER_LENGTH_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_EN_DRIVER_INVFB_DC    , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_EN_DRIVER_INVFB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_RXREG_FINECAL_2XILSB_DC , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_FINECAL_2XILSB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_GOOD              , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_GOOD );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_ERROR             , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_ERROR );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_3_23_CAL_ERROR_FINE        , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_ERROR_FINE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_RESET   , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_INIT_RXDLL_CAL_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_INIT_RXDLL_CAL_UPDATE  , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_INIT_RXDLL_CAL_UPDATE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP    , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_REGS_RXDLL_CAL_SKIP );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_REGS_RXDLL_CAL_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY2 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXREG_FILTER_LENGTH_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXREG_FILTER_LENGTH_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_EN_DRIVER_INVFB_DC     , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_EN_DRIVER_INVFB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_RXREG_FINECAL_2XILSB_DC , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXREG_FINECAL_2XILSB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_GOOD               , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_CAL_GOOD );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_ERROR              , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_CAL_ERROR );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL0_P0_4_4_CAL_ERROR_FINE         , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_CAL_ERROR_FINE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_RESET  , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_INIT_RXDLL_CAL_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_INIT_RXDLL_CAL_UPDATE , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_INIT_RXDLL_CAL_UPDATE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP   , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_REGS_RXDLL_CAL_SKIP );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_CAL_SKIP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_FILTER_LENGTH_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FILTER_LENGTH_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_EN_DRIVER_INVFB_DC    , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_EN_DRIVER_INVFB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_RXREG_FINECAL_2XILSB_DC , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_FINECAL_2XILSB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_GOOD              , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_GOOD );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_ERROR             , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_ERROR );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_0_01_CAL_ERROR_FINE        , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_ERROR_FINE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_RESET  , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_INIT_RXDLL_CAL_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_INIT_RXDLL_CAL_UPDATE , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_INIT_RXDLL_CAL_UPDATE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP   , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_REGS_RXDLL_CAL_SKIP );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_CAL_SKIP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_REGS_RXDLL_COARSE_ADJ_BY2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_FILTER_LENGTH_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FILTER_LENGTH_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_EN_DRIVER_INVFB_DC    , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_EN_DRIVER_INVFB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_RXREG_FINECAL_2XILSB_DC , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXREG_FINECAL_2XILSB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_GOOD              , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_GOOD );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_ERROR             , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_ERROR );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_1_01_CAL_ERROR_FINE        , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_ERROR_FINE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_RESET  , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_INIT_RXDLL_CAL_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_INIT_RXDLL_CAL_UPDATE , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_INIT_RXDLL_CAL_UPDATE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP   , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_REGS_RXDLL_CAL_SKIP );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_CAL_SKIP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_FILTER_LENGTH_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FILTER_LENGTH_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_EN_DRIVER_INVFB_DC    , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_EN_DRIVER_INVFB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_RXREG_FINECAL_2XILSB_DC , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_FINECAL_2XILSB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_GOOD              , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_GOOD );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_ERROR             , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_ERROR );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_2_23_CAL_ERROR_FINE        , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_ERROR_FINE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_RESET  , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_INIT_RXDLL_CAL_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_INIT_RXDLL_CAL_UPDATE , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_INIT_RXDLL_CAL_UPDATE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP   , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_REGS_RXDLL_CAL_SKIP );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_CAL_SKIP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_REGS_RXDLL_COARSE_ADJ_BY2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_FILTER_LENGTH_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FILTER_LENGTH_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_EN_DRIVER_INVFB_DC    , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_EN_DRIVER_INVFB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_RXREG_FINECAL_2XILSB_DC , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXREG_FINECAL_2XILSB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_GOOD              , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_GOOD );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_ERROR             , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_ERROR );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_3_23_CAL_ERROR_FINE        , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_ERROR_FINE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_RESET   , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_INIT_RXDLL_CAL_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_INIT_RXDLL_CAL_UPDATE  , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_INIT_RXDLL_CAL_UPDATE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP    , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_REGS_RXDLL_CAL_SKIP );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_CAL_SKIP_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_REGS_RXDLL_CAL_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_REGS_RXDLL_COARSE_ADJ_BY2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY2 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXREG_FILTER_LENGTH_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FILTER_LENGTH_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXREG_FILTER_LENGTH_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_EN_DRIVER_INVFB_DC     , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_EN_DRIVER_INVFB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_RXREG_FINECAL_2XILSB_DC , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXREG_FINECAL_2XILSB_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_GOOD               , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_CAL_GOOD );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_ERROR              , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_CAL_ERROR );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CNTL1_P0_4_4_CAL_ERROR_FINE         , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_CAL_ERROR_FINE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_0_3   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_DLLMUX_SEL_0_3 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_0_3_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_DLLMUX_SEL_0_3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_1_3   , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_DLLMUX_SEL_1_3 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_HS_DLLMUX_SEL_1_3_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_DLLMUX_SEL_1_3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_ATEST_SEL_1         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ATEST_SEL_1 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_ATEST_SEL_1_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ATEST_SEL_1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_S0INSDLYTAP         , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S0INSDLYTAP );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_0_01_S1INSDLYTAP         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S1INSDLYTAP );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_0_3 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_DLLMUX_SEL_0_0_3 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_0_3_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_DLLMUX_SEL_0_0_3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_3   , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_DLLMUX_SEL_0_3 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_HS_DLLMUX_SEL_0_3_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_HS_DLLMUX_SEL_0_3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_ATEST_SEL_0         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ATEST_SEL_0 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_ATEST_SEL_0_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ATEST_SEL_0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_S0INSDLYTAP         , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S0INSDLYTAP );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_1_01_S1INSDLYTAP         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_S1INSDLYTAP );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_0_0_3 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_DLLMUX_SEL_0_0_3 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_0_0_3_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_DLLMUX_SEL_0_0_3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_1_0_3 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_DLLMUX_SEL_1_0_3 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_HS_DLLMUX_SEL_1_0_3_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_DLLMUX_SEL_1_0_3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_ATEST_SEL_0_1       , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ATEST_SEL_0_1 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_ATEST_SEL_0_1_LEN   , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ATEST_SEL_0_1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_S0INSDLYTAP         , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S0INSDLYTAP );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_2_23_S1INSDLYTAP         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S1INSDLYTAP );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_0_0   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_DLLMUX_SEL_0_0 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_0_0_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_DLLMUX_SEL_0_0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_1_0   , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_DLLMUX_SEL_1_0 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_HS_DLLMUX_SEL_1_0_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_HS_DLLMUX_SEL_1_0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_ATEST_SEL_0_1       , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ATEST_SEL_0_1 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_ATEST_SEL_0_1_LEN   , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ATEST_SEL_0_1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_S0INSDLYTAP         , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S0INSDLYTAP );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_3_23_S1INSDLYTAP         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_S1INSDLYTAP );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_0_0_3  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_HS_DLLMUX_SEL_0_0_3 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_0_0_3_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_HS_DLLMUX_SEL_0_0_3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_1_0_3  , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_HS_DLLMUX_SEL_1_0_3 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_HS_DLLMUX_SEL_1_0_3_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_HS_DLLMUX_SEL_1_0_3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_ATEST_SEL_0_1        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ATEST_SEL_0_1 );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_ATEST_SEL_0_1_LEN    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ATEST_SEL_0_1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_S0INSDLYTAP          , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_S0INSDLYTAP );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_CONFIG1_P0_4_4_S1INSDLYTAP          , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_S1INSDLYTAP );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0_01_REGS_RXDLL_VREG_LOWER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_LOWER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_0_01_REGS_RXDLL_VREG_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1_01_REGS_RXDLL_VREG_LOWER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_LOWER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_1_01_REGS_RXDLL_VREG_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2_23_REGS_RXDLL_VREG_LOWER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_LOWER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_2_23_REGS_RXDLL_VREG_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3_23_REGS_RXDLL_VREG_LOWER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_LOWER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_3_23_REGS_RXDLL_VREG_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4_4_REGS_RXDLL_VREG_LOWER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_VREG_LOWER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER0_P0_4_4_REGS_RXDLL_VREG_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_VREG_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0_01_REGS_RXDLL_VREG_LOWER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_LOWER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_0_01_REGS_RXDLL_VREG_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1_01_REGS_RXDLL_VREG_LOWER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_LOWER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_1_01_REGS_RXDLL_VREG_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2_23_REGS_RXDLL_VREG_LOWER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_LOWER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_2_23_REGS_RXDLL_VREG_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3_23_REGS_RXDLL_VREG_LOWER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_LOWER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_3_23_REGS_RXDLL_VREG_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4_4_REGS_RXDLL_VREG_LOWER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_VREG_LOWER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_LOWER1_P0_4_4_REGS_RXDLL_VREG_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_VREG_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0_01_REGS_RXDLL_VREG_UPPER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_UPPER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_0_01_REGS_RXDLL_VREG_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1_01_REGS_RXDLL_VREG_UPPER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_UPPER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_1_01_REGS_RXDLL_VREG_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2_23_REGS_RXDLL_VREG_UPPER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_UPPER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_2_23_REGS_RXDLL_VREG_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3_23_REGS_RXDLL_VREG_UPPER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_UPPER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_3_23_REGS_RXDLL_VREG_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4_4_REGS_RXDLL_VREG_UPPER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_VREG_UPPER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER0_P0_4_4_REGS_RXDLL_VREG_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_VREG_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0_01_REGS_RXDLL_VREG_UPPER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_UPPER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_0_01_REGS_RXDLL_VREG_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1_01_REGS_RXDLL_VREG_UPPER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_UPPER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_1_01_REGS_RXDLL_VREG_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2_23_REGS_RXDLL_VREG_UPPER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_UPPER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_2_23_REGS_RXDLL_VREG_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3_23_REGS_RXDLL_VREG_UPPER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_UPPER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_3_23_REGS_RXDLL_VREG_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4_4_REGS_RXDLL_VREG_UPPER , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_VREG_UPPER );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_DAC_UPPER1_P0_4_4_REGS_RXDLL_VREG_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_VREG_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_OVERRIDE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_REF_SEL_DC , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_DAC_COARSE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_0_01_SLAVE_VREG_DAC_COARSE_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_OVERRIDE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_REF_SEL_DC , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_DAC_COARSE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_1_01_SLAVE_VREG_DAC_COARSE_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_OVERRIDE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_REF_SEL_DC , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_DAC_COARSE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_2_23_SLAVE_VREG_DAC_COARSE_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_OVERRIDE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_REF_SEL_DC , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_DAC_COARSE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_3_23_SLAVE_VREG_DAC_COARSE_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_OVERRIDE   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SLAVE_VREG_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_REF_SEL_DC , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SLAVE_VREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SLAVE_VREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_DAC_COARSE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SLAVE_VREG_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA0_P0_4_4_SLAVE_VREG_DAC_COARSE_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SLAVE_VREG_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_OVERRIDE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_REF_SEL_DC , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_DAC_COARSE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_0_01_SLAVE_VREG_DAC_COARSE_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_OVERRIDE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_REF_SEL_DC , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_DAC_COARSE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_1_01_SLAVE_VREG_DAC_COARSE_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SLAVE_VREG_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_OVERRIDE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_REF_SEL_DC , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_DAC_COARSE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_2_23_SLAVE_VREG_DAC_COARSE_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_OVERRIDE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_REF_SEL_DC , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_DAC_COARSE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_3_23_SLAVE_VREG_DAC_COARSE_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SLAVE_VREG_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_OVERRIDE   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SLAVE_VREG_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_REF_SEL_DC , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SLAVE_VREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SLAVE_VREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_DAC_COARSE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SLAVE_VREG_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_EXTRA1_P0_4_4_SLAVE_VREG_DAC_COARSE_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SLAVE_VREG_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0_01_LOWER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LOWER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_0_01_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1_01_LOWER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LOWER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_1_01_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2_23_LOWER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LOWER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_2_23_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3_23_LOWER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LOWER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_3_23_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4_4_LOWER      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LOWER    );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER0_P0_4_4_LOWER_LEN  , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0_01_LOWER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LOWER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_0_01_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1_01_LOWER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LOWER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_1_01_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2_23_LOWER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LOWER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_2_23_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3_23_LOWER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LOWER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_3_23_LOWER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4_4_LOWER      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LOWER    );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_LOWER1_P0_4_4_LOWER_LEN  , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LOWER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0_01_UPPER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_UPPER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_0_01_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1_01_UPPER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_UPPER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_1_01_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2_23_UPPER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_UPPER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_2_23_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3_23_UPPER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_UPPER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_3_23_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4_4_UPPER      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_UPPER    );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER0_P0_4_4_UPPER_LEN  , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0_01_UPPER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_UPPER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_0_01_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1_01_UPPER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_UPPER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_1_01_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2_23_UPPER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_UPPER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_2_23_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3_23_UPPER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_UPPER   );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_3_23_UPPER_LEN , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4_4_UPPER      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_UPPER    );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SLAVE_VREG_UPPER1_P0_4_4_UPPER_LEN  , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_UPPER_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_OVERRIDE        , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_CAL_PD_ENABLE   , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_MAIN_PD_ENABLE  , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_MAIN_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_DETECT_REQ      , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DETECT_REQ );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_SLAVE_CAL_CKT_POWERDOWN , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_SLAVE_CAL_CKT_POWERDOWN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_VREG_RXCAL_COMP_OUT_META , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_VREG_RXCAL_COMP_OUT_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_DETECT_DONE_META , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_DETECT_DONE_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_PD_CAL_LAG_META , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_PD_CAL_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_PD_MAIN_LEAD_META , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_PD_MAIN_LEAD_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_RXCAL_PD_MAIN_LAG_META , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_PD_MAIN_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_0_01_VREG_SLAVE_COMP_OUT , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_VREG_SLAVE_COMP_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_OVERRIDE        , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_CAL_PD_ENABLE   , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_MAIN_PD_ENABLE  , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_MAIN_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_DETECT_REQ      , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DETECT_REQ );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_SLAVE_CAL_CKT_POWERDOWN , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_SLAVE_CAL_CKT_POWERDOWN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_VREG_RXCAL_COMP_OUT_META , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_VREG_RXCAL_COMP_OUT_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_DETECT_DONE_META , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_DETECT_DONE_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_PD_CAL_LAG_META , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_PD_CAL_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_PD_MAIN_LEAD_META , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_PD_MAIN_LEAD_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_RXCAL_PD_MAIN_LAG_META , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_PD_MAIN_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_1_01_VREG_SLAVE_COMP_OUT , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_VREG_SLAVE_COMP_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_OVERRIDE        , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_CAL_PD_ENABLE   , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_MAIN_PD_ENABLE  , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_MAIN_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_DETECT_REQ      , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DETECT_REQ );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_SLAVE_CAL_CKT_POWERDOWN , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_SLAVE_CAL_CKT_POWERDOWN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_VREG_RXCAL_COMP_OUT_META , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_VREG_RXCAL_COMP_OUT_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_DETECT_DONE_META , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_DETECT_DONE_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_PD_CAL_LAG_META , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_PD_CAL_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_PD_MAIN_LEAD_META , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_PD_MAIN_LEAD_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_RXCAL_PD_MAIN_LAG_META , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_PD_MAIN_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_2_23_VREG_SLAVE_COMP_OUT , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_VREG_SLAVE_COMP_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_OVERRIDE        , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_CAL_PD_ENABLE   , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_MAIN_PD_ENABLE  , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_MAIN_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_DETECT_REQ      , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DETECT_REQ );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_SLAVE_CAL_CKT_POWERDOWN , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_SLAVE_CAL_CKT_POWERDOWN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_VREG_RXCAL_COMP_OUT_META , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_VREG_RXCAL_COMP_OUT_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_DETECT_DONE_META , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_DETECT_DONE_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_PD_CAL_LAG_META , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_PD_CAL_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_PD_MAIN_LEAD_META , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_PD_MAIN_LEAD_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_RXCAL_PD_MAIN_LAG_META , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_PD_MAIN_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_3_23_VREG_SLAVE_COMP_OUT , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_VREG_SLAVE_COMP_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_OVERRIDE         , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_CAL_PD_ENABLE    , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_CAL_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_MAIN_PD_ENABLE   , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_MAIN_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_DETECT_REQ       , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DETECT_REQ );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_SLAVE_CAL_CKT_POWERDOWN , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_SLAVE_CAL_CKT_POWERDOWN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_VREG_RXCAL_COMP_OUT_META , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_VREG_RXCAL_COMP_OUT_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_DETECT_DONE_META , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXCAL_DETECT_DONE_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_PD_CAL_LAG_META , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXCAL_PD_CAL_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_PD_MAIN_LEAD_META , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXCAL_PD_MAIN_LEAD_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_RXCAL_PD_MAIN_LAG_META , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXCAL_PD_MAIN_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL0_P0_4_4_VREG_SLAVE_COMP_OUT , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_VREG_SLAVE_COMP_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_OVERRIDE        , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_CAL_PD_ENABLE   , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_MAIN_PD_ENABLE  , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_MAIN_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_DETECT_REQ      , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DETECT_REQ );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_SLAVE_CAL_CKT_POWERDOWN , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_SLAVE_CAL_CKT_POWERDOWN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_VREG_RXCAL_COMP_OUT_META , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_VREG_RXCAL_COMP_OUT_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_DETECT_DONE_META , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_DETECT_DONE_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_PD_CAL_LAG_META , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_PD_CAL_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_PD_MAIN_LEAD_META , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_PD_MAIN_LEAD_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_RXCAL_PD_MAIN_LAG_META , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_PD_MAIN_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_0_01_VREG_SLAVE_COMP_OUT , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_VREG_SLAVE_COMP_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_OVERRIDE        , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_CAL_PD_ENABLE   , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CAL_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_MAIN_PD_ENABLE  , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_MAIN_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_DETECT_REQ      , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DETECT_REQ );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_SLAVE_CAL_CKT_POWERDOWN , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_SLAVE_CAL_CKT_POWERDOWN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_VREG_RXCAL_COMP_OUT_META , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_VREG_RXCAL_COMP_OUT_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_DETECT_DONE_META , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_DETECT_DONE_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_PD_CAL_LAG_META , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_PD_CAL_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_PD_MAIN_LEAD_META , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_PD_MAIN_LEAD_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_RXCAL_PD_MAIN_LAG_META , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_RXCAL_PD_MAIN_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_1_01_VREG_SLAVE_COMP_OUT , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_VREG_SLAVE_COMP_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_OVERRIDE        , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_CAL_PD_ENABLE   , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_MAIN_PD_ENABLE  , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_MAIN_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_DETECT_REQ      , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DETECT_REQ );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_SLAVE_CAL_CKT_POWERDOWN , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_SLAVE_CAL_CKT_POWERDOWN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_VREG_RXCAL_COMP_OUT_META , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_VREG_RXCAL_COMP_OUT_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_DETECT_DONE_META , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_DETECT_DONE_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_PD_CAL_LAG_META , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_PD_CAL_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_PD_MAIN_LEAD_META , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_PD_MAIN_LEAD_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_RXCAL_PD_MAIN_LAG_META , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_PD_MAIN_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_2_23_VREG_SLAVE_COMP_OUT , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_VREG_SLAVE_COMP_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_OVERRIDE        , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_CAL_PD_ENABLE   , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CAL_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_MAIN_PD_ENABLE  , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_MAIN_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_DETECT_REQ      , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DETECT_REQ );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_SLAVE_CAL_CKT_POWERDOWN , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_SLAVE_CAL_CKT_POWERDOWN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_VREG_RXCAL_COMP_OUT_META , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_VREG_RXCAL_COMP_OUT_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_DETECT_DONE_META , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_DETECT_DONE_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_PD_CAL_LAG_META , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_PD_CAL_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_PD_MAIN_LEAD_META , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_PD_MAIN_LEAD_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_RXCAL_PD_MAIN_LAG_META , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_RXCAL_PD_MAIN_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_3_23_VREG_SLAVE_COMP_OUT , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_VREG_SLAVE_COMP_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_OVERRIDE         , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_CAL_PD_ENABLE    , 49  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_CAL_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_MAIN_PD_ENABLE   , 50  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_MAIN_PD_ENABLE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_DETECT_REQ       , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DETECT_REQ );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_SLAVE_CAL_CKT_POWERDOWN , 52  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_SLAVE_CAL_CKT_POWERDOWN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_VREG_RXCAL_COMP_OUT_META , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_VREG_RXCAL_COMP_OUT_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_DETECT_DONE_META , 57  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXCAL_DETECT_DONE_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_PD_CAL_LAG_META , 58  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXCAL_PD_CAL_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_PD_MAIN_LEAD_META , 59  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXCAL_PD_MAIN_LEAD_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_RXCAL_PD_MAIN_LAG_META , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_RXCAL_PD_MAIN_LAG_META );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_SW_CONTROL1_P0_4_4_VREG_SLAVE_COMP_OUT , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_VREG_SLAVE_COMP_OUT );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_COARSE_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_COARSE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_COARSE_EN_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_COARSE_EN_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_DAC_COARSE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_0_01_REGS_RXDLL_DAC_COARSE_LEN , 7   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_REGS_RXDLL_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_COARSE_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_COARSE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_COARSE_EN_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_COARSE_EN_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_DAC_COARSE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_1_01_REGS_RXDLL_DAC_COARSE_LEN , 7   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_REGS_RXDLL_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_COARSE_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_COARSE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_COARSE_EN_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_COARSE_EN_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_DAC_COARSE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_2_23_REGS_RXDLL_DAC_COARSE_LEN , 7   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_REGS_RXDLL_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_COARSE_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_COARSE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_COARSE_EN_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_COARSE_EN_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_DAC_COARSE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_3_23_REGS_RXDLL_DAC_COARSE_LEN , 7   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_REGS_RXDLL_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_COARSE_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_COARSE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_COARSE_EN_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_COARSE_EN_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_DAC_COARSE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE0_P0_4_4_REGS_RXDLL_DAC_COARSE_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_COARSE_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_COARSE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_COARSE_EN_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_COARSE_EN_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_DAC_COARSE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_0_01_REGS_RXDLL_DAC_COARSE_LEN , 7   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_REGS_RXDLL_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_COARSE_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_COARSE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_COARSE_EN_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_COARSE_EN_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_DAC_COARSE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REGS_RXDLL_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_1_01_REGS_RXDLL_DAC_COARSE_LEN , 7   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_REGS_RXDLL_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_COARSE_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_COARSE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_COARSE_EN_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_COARSE_EN_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_DAC_COARSE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_2_23_REGS_RXDLL_DAC_COARSE_LEN , 7   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_REGS_RXDLL_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_COARSE_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_COARSE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_COARSE_EN_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_COARSE_EN_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_DAC_COARSE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REGS_RXDLL_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_3_23_REGS_RXDLL_DAC_COARSE_LEN , 7   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_REGS_RXDLL_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_COARSE_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_COARSE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_COARSE_EN_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_COARSE_EN_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_DAC_COARSE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_DAC_COARSE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_COARSE1_P0_4_4_REGS_RXDLL_DAC_COARSE_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REGS_RXDLL_DAC_COARSE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_COMPCON_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_COMPCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_COMPCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_COMPCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_CON_DC  , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_CON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_DAC_PULLUP_DC , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_DAC_PULLUP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_DRVCON_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_DRVCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_DRVCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_DRVCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_REF_SEL_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_RXREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_DRVREN_MODE   , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DRVREN_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_0_01_CAL_CKTS_ACTIVE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CAL_CKTS_ACTIVE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_COMPCON_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_COMPCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_COMPCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_COMPCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_CON_DC  , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_CON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_DAC_PULLUP_DC , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_DAC_PULLUP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_DRVCON_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_DRVCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_DRVCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_DRVCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_REF_SEL_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_RXREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_DRVREN_MODE   , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DRVREN_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_1_01_CAL_CKTS_ACTIVE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CAL_CKTS_ACTIVE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_COMPCON_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_COMPCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_COMPCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_COMPCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_CON_DC  , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_CON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_DAC_PULLUP_DC , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_DAC_PULLUP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_DRVCON_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_DRVCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_DRVCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_DRVCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_REF_SEL_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_RXREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_DRVREN_MODE   , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DRVREN_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_2_23_CAL_CKTS_ACTIVE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CAL_CKTS_ACTIVE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_COMPCON_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_COMPCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_COMPCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_COMPCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_CON_DC  , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_CON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_DAC_PULLUP_DC , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_DAC_PULLUP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_DRVCON_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_DRVCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_DRVCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_DRVCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_REF_SEL_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_RXREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_DRVREN_MODE   , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DRVREN_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_3_23_CAL_CKTS_ACTIVE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CAL_CKTS_ACTIVE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_COMPCON_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_COMPCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_COMPCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_COMPCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_CON_DC   , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_CON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_DAC_PULLUP_DC , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_DAC_PULLUP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_DRVCON_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_DRVCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_DRVCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_DRVCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_REF_SEL_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_RXREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_DRVREN_MODE    , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DRVREN_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL0_P0_4_4_CAL_CKTS_ACTIVE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CAL_CKTS_ACTIVE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_COMPCON_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_COMPCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_COMPCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_COMPCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_CON_DC  , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_CON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_DAC_PULLUP_DC , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_DAC_PULLUP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_DRVCON_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_DRVCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_DRVCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_DRVCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_REF_SEL_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_RXREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_DRVREN_MODE   , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DRVREN_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_0_01_CAL_CKTS_ACTIVE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CAL_CKTS_ACTIVE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_COMPCON_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_COMPCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_COMPCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_COMPCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_CON_DC  , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_CON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_DAC_PULLUP_DC , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_DAC_PULLUP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_DRVCON_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_DRVCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_DRVCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_DRVCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_REF_SEL_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_RXREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RXREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_DRVREN_MODE   , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DRVREN_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_1_01_CAL_CKTS_ACTIVE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CAL_CKTS_ACTIVE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_COMPCON_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_COMPCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_COMPCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_COMPCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_CON_DC  , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_CON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_DAC_PULLUP_DC , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_DAC_PULLUP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_DRVCON_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_DRVCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_DRVCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_DRVCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_REF_SEL_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_RXREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_DRVREN_MODE   , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DRVREN_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_2_23_CAL_CKTS_ACTIVE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CAL_CKTS_ACTIVE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_COMPCON_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_COMPCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_COMPCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_COMPCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_CON_DC  , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_CON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_DAC_PULLUP_DC , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_DAC_PULLUP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_DRVCON_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_DRVCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_DRVCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_DRVCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_REF_SEL_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_RXREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RXREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_DRVREN_MODE   , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DRVREN_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_3_23_CAL_CKTS_ACTIVE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CAL_CKTS_ACTIVE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_COMPCON_DC , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_COMPCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_COMPCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_COMPCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_CON_DC   , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_CON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_DAC_PULLUP_DC , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_DAC_PULLUP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_DRVCON_DC , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_DRVCON_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_DRVCON_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_DRVCON_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_REF_SEL_DC , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_REF_SEL_DC );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_RXREG_REF_SEL_DC_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RXREG_REF_SEL_DC_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_DRVREN_MODE    , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DRVREN_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_DLL_VREG_CONTROL1_P0_4_4_CAL_CKTS_ACTIVE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CAL_CKTS_ACTIVE );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_0_01_DQS               , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DQS     );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_0_01_DQS_LEN           , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DQS_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_1_01_DQS               , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DQS     );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_1_01_DQS_LEN           , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DQS_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_2_23_DQS               , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DQS     );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_2_23_DQS_LEN           , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DQS_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_3_23_DQS               , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DQS     );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_3_23_DQS_LEN           , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DQS_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_4_4_DQS                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DQS      );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_OFFSET_P0_4_4_DQS_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DQS_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_0_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_1_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_2_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_3_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR0_P0_4_4_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_0_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_1_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_2_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_3_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR1_P0_4_4_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_0_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_1_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_2_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_3_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR2_P0_4_4_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_0_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_1_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_2_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_3_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR0_RANK_PAIR3_P0_4_4_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_0_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_1_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_2_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_3_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR0_P0_4_4_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_0_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_1_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_2_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_3_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR1_P0_4_4_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_0_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_1_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_2_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_3_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR2_P0_4_4_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_0_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_1_01_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_2_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_3_23_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQSCLK_PR1_RANK_PAIR3_P0_4_4_ROT_CLK_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_CLK_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_0_01_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_1_01_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_2_23_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_3_23_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N0            , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N0_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N1            , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N1_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N2            , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N2_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N3            , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP0_P0_4_4_N3_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_0_01_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_1_01_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_2_23_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_3_23_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N0            , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N0_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N1            , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N1_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N2            , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N2_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N3            , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP1_P0_4_4_N3_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_0_01_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_1_01_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_2_23_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_3_23_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N0            , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N0_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N1            , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N1_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N2            , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N2_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N3            , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP2_P0_4_4_N3_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_0_01_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_1_01_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_2_23_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N0_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N1           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N1_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N2           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N2_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N3           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_3_23_N3_LEN       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N0            , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N0_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N1            , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N1_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N2            , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N2_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N3            , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3       );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_GATE_DELAY_RP3_P0_4_4_N3_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_01_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_23_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_23_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_4_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_01_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_01_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_23_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_23_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_4_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_01_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_01_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_23_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_23_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_4_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_01_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_01_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_23_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_23_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT0 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT0 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT0 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT0_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT1 , 52  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT1 , 54  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT1 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT1_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT1_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT2 , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT2 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT2 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT2_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT3 , 60  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_DQSCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DQSCLK_SELECT3_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT3 , 62  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT3 );
+REG64_FLD( MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_4_RDCLK_SELECT3_LEN , 2   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_RDCLK_SELECT3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_0_01_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_1_01_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_2_23_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_3_23_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N0              , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N0_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N1              , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N1_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N2              , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N2_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N3              , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP0_P0_4_4_N3_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_0_01_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_1_01_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_2_23_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_3_23_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N0              , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N0_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N1              , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N1_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N2              , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N2_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N3              , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP1_P0_4_4_N3_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_0_01_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_1_01_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_2_23_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_3_23_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N0              , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N0_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N1              , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N1_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N2              , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N2_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N3              , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP2_P0_4_4_N3_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_0_01_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_1_01_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_2_23_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N0             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N0_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N0_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N1             , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N1_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N1_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N2             , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N2_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N2_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3      );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_3_23_N3_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_N3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N0              , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N0_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N0_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N1              , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N1_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N1_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N2              , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N2_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N2_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N3              , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3       );
+REG64_FLD( MCA_DDRPHY_DP16_DQ_WR_OFFSET_RP3_P0_4_4_N3_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_N3_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MIN_RD_EYE_SIZE    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_RD_EYE_SIZE );
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MIN_RD_EYE_SIZE_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_RD_EYE_SIZE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MAX_DQS            , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MAX_DQS );
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_MAX_DQS_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MAX_DQS_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MIN_RD_EYE_SIZE    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_RD_EYE_SIZE );
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MIN_RD_EYE_SIZE_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_RD_EYE_SIZE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MAX_DQS            , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MAX_DQS );
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1_01_MAX_DQS_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MAX_DQS_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MIN_RD_EYE_SIZE    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_RD_EYE_SIZE );
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MIN_RD_EYE_SIZE_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_RD_EYE_SIZE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MAX_DQS            , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MAX_DQS );
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2_23_MAX_DQS_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MAX_DQS_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MIN_RD_EYE_SIZE    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_RD_EYE_SIZE );
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MIN_RD_EYE_SIZE_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_RD_EYE_SIZE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MAX_DQS            , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MAX_DQS );
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3_23_MAX_DQS_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MAX_DQS_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MIN_RD_EYE_SIZE     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MIN_RD_EYE_SIZE );
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MIN_RD_EYE_SIZE_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MIN_RD_EYE_SIZE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MAX_DQS             , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MAX_DQS  );
+REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4_4_MAX_DQS_LEN         , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MAX_DQS_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_0_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_1_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_2_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_3_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR0_P0_4_4_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_0_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_1_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_2_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_3_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR1_P0_4_4_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_0_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_1_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_2_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_3_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR2_P0_4_4_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_0_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_1_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_2_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_3_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN0_RANK_PAIR3_P0_4_4_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_0_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_1_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_2_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_3_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR0_P0_4_4_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_0_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_1_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_2_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_3_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR1_P0_4_4_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_0_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_1_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_2_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_3_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR2_P0_4_4_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_0_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_1_01_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_2_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1  );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_3_23_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1   );
+REG64_FLD( MCA_DDRPHY_DP16_INITIAL_DQS_ALIGN1_RANK_PAIR3_P0_4_4_ROT_N1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT_N1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0_01_INTERP_SIG_SLEW   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INTERP_SIG_SLEW );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_0_01_INTERP_SIG_SLEW_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INTERP_SIG_SLEW_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1_01_INTERP_SIG_SLEW   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INTERP_SIG_SLEW );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_1_01_INTERP_SIG_SLEW_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INTERP_SIG_SLEW_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2_23_INTERP_SIG_SLEW   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INTERP_SIG_SLEW );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_2_23_INTERP_SIG_SLEW_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INTERP_SIG_SLEW_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3_23_INTERP_SIG_SLEW   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INTERP_SIG_SLEW );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_3_23_INTERP_SIG_SLEW_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INTERP_SIG_SLEW_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4_4_INTERP_SIG_SLEW    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_INTERP_SIG_SLEW );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_CONFIG0_P0_4_4_INTERP_SIG_SLEW_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_INTERP_SIG_SLEW_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_N_WR         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EN_N_WR );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_N_WR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EN_N_WR_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_P_WR         , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EN_P_WR );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_0_01_EN_P_WR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EN_P_WR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_N_WR         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EN_N_WR );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_N_WR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EN_N_WR_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_P_WR         , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EN_P_WR );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_1_01_EN_P_WR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EN_P_WR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_N_WR         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EN_N_WR );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_N_WR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EN_N_WR_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_P_WR         , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EN_P_WR );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_2_23_EN_P_WR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EN_P_WR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_N_WR         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EN_N_WR );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_N_WR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EN_N_WR_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_P_WR         , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EN_P_WR );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_3_23_EN_P_WR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EN_P_WR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_N_WR          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_EN_N_WR  );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_N_WR_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_EN_N_WR_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_P_WR          , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_EN_P_WR  );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_FET_SLICE_P0_4_4_EN_P_WR_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_EN_P_WR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0_01_EN_P_WR         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EN_P_WR );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_0_01_EN_P_WR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EN_P_WR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1_01_EN_P_WR         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EN_P_WR );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_1_01_EN_P_WR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EN_P_WR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2_23_EN_P_WR         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EN_P_WR );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_2_23_EN_P_WR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EN_P_WR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3_23_EN_P_WR         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EN_P_WR );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_3_23_EN_P_WR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EN_P_WR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4_4_EN_P_WR          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_EN_P_WR  );
+REG64_FLD( MCA_DDRPHY_DP16_IO_TX_PFET_TERM_P0_4_4_EN_P_WR_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_EN_P_WR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_A           , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL_A   );
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_A_LEN       , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL_A_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_B           , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL_B   );
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_0_01_SEL_B_LEN       , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL_B_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_A           , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL_A   );
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_A_LEN       , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL_A_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_B           , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL_B   );
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_1_01_SEL_B_LEN       , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SEL_B_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_A           , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL_A   );
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_A_LEN       , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL_A_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_B           , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL_B   );
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_2_23_SEL_B_LEN       , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL_B_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_A           , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL_A   );
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_A_LEN       , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL_A_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_B           , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL_B   );
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_3_23_SEL_B_LEN       , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SEL_B_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_A            , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SEL_A    );
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_A_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SEL_A_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_B            , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SEL_B    );
+REG64_FLD( MCA_DDRPHY_DP16_LO_PROBE_SELECT_P0_4_4_SEL_B_LEN        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SEL_B_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD00         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD00 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD00_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD00_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD01         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD01 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD01_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD01_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD02         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD02 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD02_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD02_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD03         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD03 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD03_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD03_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD04         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD04 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD04_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD04_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD05         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD05 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD05_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD05_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD06         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD06 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD06_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD06_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD07         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD07 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_0_01_MEMINTD07_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD07_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD00         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD00 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD00_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD00_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD01         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD01 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD01_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD01_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD02         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD02 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD02_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD02_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD03         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD03 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD03_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD03_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD04         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD04 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD04_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD04_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD05         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD05 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD05_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD05_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD06         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD06 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD06_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD06_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD07         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD07 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_1_01_MEMINTD07_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD07_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD00         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD00 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD00_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD00_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD01         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD01 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD01_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD01_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD02         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD02 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD02_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD02_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD03         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD03 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD03_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD03_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD04         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD04 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD04_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD04_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD05         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD05 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD05_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD05_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD06         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD06 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD06_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD06_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD07         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD07 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_2_23_MEMINTD07_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD07_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD00         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD00 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD00_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD00_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD01         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD01 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD01_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD01_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD02         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD02 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD02_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD02_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD03         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD03 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD03_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD03_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD04         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD04 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD04_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD04_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD05         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD05 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD05_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD05_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD06         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD06 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD06_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD06_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD07         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD07 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_3_23_MEMINTD07_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD07_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD00          , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD00 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD00_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD00_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD01          , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD01 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD01_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD01_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD02          , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD02 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD02_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD02_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD03          , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD03 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD03_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD03_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD04          , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD04 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD04_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD04_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD05          , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD05 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD05_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD05_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD06          , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD06 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD06_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD06_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD07          , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD07 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_0_P0_4_4_MEMINTD07_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD07_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD08         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD08 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD08_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD08_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD09         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD09 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD09_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD09_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD10         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD10 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD10_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD10_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD11         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD11 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD11_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD11_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD12         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD12 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD12_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD12_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD13         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD13 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD13_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD13_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD14         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD14 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD14_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD14_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD15         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD15 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_0_01_MEMINTD15_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD08         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD08 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD08_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD08_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD09         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD09 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD09_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD09_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD10         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD10 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD10_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD10_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD11         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD11 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD11_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD11_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD12         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD12 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD12_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD12_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD13         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD13 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD13_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD13_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD14         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD14 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD14_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD14_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD15         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD15 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_1_01_MEMINTD15_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD08         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD08 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD08_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD08_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD09         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD09 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD09_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD09_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD10         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD10 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD10_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD10_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD11         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD11 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD11_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD11_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD12         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD12 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD12_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD12_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD13         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD13 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD13_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD13_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD14         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD14 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD14_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD14_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD15         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD15 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_2_23_MEMINTD15_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD08         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD08 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD08_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD08_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD09         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD09 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD09_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD09_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD10         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD10 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD10_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD10_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD11         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD11 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD11_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD11_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD12         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD12 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD12_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD12_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD13         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD13 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD13_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD13_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD14         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD14 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD14_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD14_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD15         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD15 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_3_23_MEMINTD15_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD08          , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD08 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD08_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD08_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD09          , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD09 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD09_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD09_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD10          , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD10 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD10_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD10_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD11          , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD11 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD11_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD11_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD12          , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD12 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD12_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD12_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD13          , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD13 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD13_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD13_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD14          , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD14 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD14_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD14_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD15          , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD15 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_1_P0_4_4_MEMINTD15_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD16         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD16 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD16_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD16_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD17         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD17 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD17_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD17_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD18         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD18 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD18_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD18_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD19         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD19 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD19_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD19_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD20         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD20 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD20_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD20_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD21         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD21 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD21_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD21_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD22         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD22 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD22_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD22_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD23         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD23 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_0_01_MEMINTD23_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD16         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD16 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD16_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD16_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD17         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD17 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD17_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD17_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD18         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD18 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD18_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD18_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD19         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD19 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD19_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD19_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD20         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD20 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD20_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD20_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD21         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD21 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD21_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD21_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD22         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD22 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD22_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD22_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD23         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD23 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_1_01_MEMINTD23_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MEMINTD23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD16         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD16 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD16_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD16_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD17         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD17 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD17_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD17_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD18         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD18 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD18_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD18_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD19         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD19 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD19_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD19_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD20         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD20 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD20_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD20_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD21         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD21 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD21_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD21_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD22         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD22 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD22_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD22_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD23         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD23 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_2_23_MEMINTD23_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD16         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD16 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD16_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD16_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD17         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD17 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD17_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD17_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD18         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD18 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD18_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD18_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD19         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD19 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD19_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD19_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD20         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD20 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD20_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD20_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD21         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD21 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD21_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD21_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD22         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD22 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD22_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD22_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD23         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD23 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_3_23_MEMINTD23_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MEMINTD23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD16          , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD16 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD16_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD16_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD17          , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD17 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD17_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD17_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD18          , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD18 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD18_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD18_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD19          , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD19 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD19_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD19_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD20          , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD20 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD20_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD20_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD21          , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD21 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD21_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD21_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD22          , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD22 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD22_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD22_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD23          , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD23 );
+REG64_FLD( MCA_DDRPHY_DP16_PATTERN_POS_2_P0_4_4_MEMINTD23_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MEMINTD23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_DQSCLK_OFFSET , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SYSCLK_DQSCLK_OFFSET );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_DQSCLK_OFFSET_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SYSCLK_DQSCLK_OFFSET_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_RDCLK_OFFSET , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SYSCLK_RDCLK_OFFSET );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_0_01_SYSCLK_RDCLK_OFFSET_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SYSCLK_RDCLK_OFFSET_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_DQSCLK_OFFSET , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SYSCLK_DQSCLK_OFFSET );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_DQSCLK_OFFSET_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SYSCLK_DQSCLK_OFFSET_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_RDCLK_OFFSET , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SYSCLK_RDCLK_OFFSET );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_1_01_SYSCLK_RDCLK_OFFSET_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_SYSCLK_RDCLK_OFFSET_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_DQSCLK_OFFSET , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SYSCLK_DQSCLK_OFFSET );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_DQSCLK_OFFSET_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SYSCLK_DQSCLK_OFFSET_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_RDCLK_OFFSET , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SYSCLK_RDCLK_OFFSET );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_2_23_SYSCLK_RDCLK_OFFSET_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SYSCLK_RDCLK_OFFSET_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_DQSCLK_OFFSET , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SYSCLK_DQSCLK_OFFSET );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_DQSCLK_OFFSET_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SYSCLK_DQSCLK_OFFSET_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_RDCLK_OFFSET , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SYSCLK_RDCLK_OFFSET );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_3_23_SYSCLK_RDCLK_OFFSET_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_SYSCLK_RDCLK_OFFSET_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_DQSCLK_OFFSET , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SYSCLK_DQSCLK_OFFSET );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_DQSCLK_OFFSET_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SYSCLK_DQSCLK_OFFSET_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_RDCLK_OFFSET , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SYSCLK_RDCLK_OFFSET );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG0_P0_4_4_SYSCLK_RDCLK_OFFSET_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_SYSCLK_RDCLK_OFFSET_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_SM     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_DQS_ALIGN_SM );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_SM_LEN , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_DQS_ALIGN_SM_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_CNTR   , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_DQS_ALIGN_CNTR );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_DQS_ALIGN_CNTR_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_DQS_ALIGN_CNTR_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_ITERATION_CNTR   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ITERATION_CNTR );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_0_01_ITERATION_CNTR_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ITERATION_CNTR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_SM     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_DQS_ALIGN_SM );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_SM_LEN , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_DQS_ALIGN_SM_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_CNTR   , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_DQS_ALIGN_CNTR );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_DQS_ALIGN_CNTR_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_DQS_ALIGN_CNTR_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_ITERATION_CNTR   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ITERATION_CNTR );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_1_01_ITERATION_CNTR_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ITERATION_CNTR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_SM     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_DQS_ALIGN_SM );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_SM_LEN , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_DQS_ALIGN_SM_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_CNTR   , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_DQS_ALIGN_CNTR );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_DQS_ALIGN_CNTR_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_DQS_ALIGN_CNTR_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_ITERATION_CNTR   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ITERATION_CNTR );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_2_23_ITERATION_CNTR_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ITERATION_CNTR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_SM     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_DQS_ALIGN_SM );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_SM_LEN , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_DQS_ALIGN_SM_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_CNTR   , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_DQS_ALIGN_CNTR );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_DQS_ALIGN_CNTR_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_DQS_ALIGN_CNTR_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_ITERATION_CNTR   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ITERATION_CNTR );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_3_23_ITERATION_CNTR_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ITERATION_CNTR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_SM      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_DQS_ALIGN_SM );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_SM_LEN  , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_DQS_ALIGN_SM_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_CNTR    , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_DQS_ALIGN_CNTR );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_DQS_ALIGN_CNTR_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_DQS_ALIGN_CNTR_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_ITERATION_CNTR    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ITERATION_CNTR );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG1_P0_4_4_ITERATION_CNTR_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ITERATION_CNTR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_CALIBRATE_BIT    , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CALIBRATE_BIT );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_CALIBRATE_BIT_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CALIBRATE_BIT_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_ALIGN_QUAD   , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DQS_ALIGN_QUAD );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_ALIGN_QUAD_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DQS_ALIGN_QUAD_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_QUAD_CONFIG  , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DQS_QUAD_CONFIG );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_QUAD_CONFIG_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DQS_QUAD_CONFIG_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_OPERATE_MODE     , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_OPERATE_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_OPERATE_MODE_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_OPERATE_MODE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_EN_DQS_OFFSET    , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_EN_DQS_OFFSET );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DQS_ALIGN_JITTER , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DQS_ALIGN_JITTER );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_DIS_CLK_GATE     , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DIS_CLK_GATE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_0_01_MAX_DQS_ITER     , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_MAX_DQS_ITER );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_CALIBRATE_BIT    , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CALIBRATE_BIT );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_CALIBRATE_BIT_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_CALIBRATE_BIT_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_ALIGN_QUAD   , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DQS_ALIGN_QUAD );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_ALIGN_QUAD_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DQS_ALIGN_QUAD_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_QUAD_CONFIG  , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DQS_QUAD_CONFIG );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_QUAD_CONFIG_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DQS_QUAD_CONFIG_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_OPERATE_MODE     , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_OPERATE_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_OPERATE_MODE_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_OPERATE_MODE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_EN_DQS_OFFSET    , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_EN_DQS_OFFSET );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DQS_ALIGN_JITTER , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DQS_ALIGN_JITTER );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_DIS_CLK_GATE     , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_DIS_CLK_GATE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_1_01_MAX_DQS_ITER     , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_01_MAX_DQS_ITER );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_CALIBRATE_BIT    , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CALIBRATE_BIT );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_CALIBRATE_BIT_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CALIBRATE_BIT_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_ALIGN_QUAD   , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DQS_ALIGN_QUAD );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_ALIGN_QUAD_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DQS_ALIGN_QUAD_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_QUAD_CONFIG  , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DQS_QUAD_CONFIG );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_QUAD_CONFIG_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DQS_QUAD_CONFIG_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_OPERATE_MODE     , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_OPERATE_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_OPERATE_MODE_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_OPERATE_MODE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_EN_DQS_OFFSET    , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_EN_DQS_OFFSET );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DQS_ALIGN_JITTER , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DQS_ALIGN_JITTER );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_DIS_CLK_GATE     , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DIS_CLK_GATE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_2_23_MAX_DQS_ITER     , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_MAX_DQS_ITER );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_CALIBRATE_BIT    , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CALIBRATE_BIT );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_CALIBRATE_BIT_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_CALIBRATE_BIT_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_ALIGN_QUAD   , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DQS_ALIGN_QUAD );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_ALIGN_QUAD_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DQS_ALIGN_QUAD_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_QUAD_CONFIG  , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DQS_QUAD_CONFIG );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_QUAD_CONFIG_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DQS_QUAD_CONFIG_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_OPERATE_MODE     , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_OPERATE_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_OPERATE_MODE_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_OPERATE_MODE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_EN_DQS_OFFSET    , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_EN_DQS_OFFSET );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DQS_ALIGN_JITTER , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DQS_ALIGN_JITTER );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_DIS_CLK_GATE     , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_DIS_CLK_GATE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_3_23_MAX_DQS_ITER     , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_23_MAX_DQS_ITER );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_CALIBRATE_BIT     , 48  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_CALIBRATE_BIT );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_CALIBRATE_BIT_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_CALIBRATE_BIT_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_ALIGN_QUAD    , 51  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DQS_ALIGN_QUAD );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_ALIGN_QUAD_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DQS_ALIGN_QUAD_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_QUAD_CONFIG   , 53  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DQS_QUAD_CONFIG );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_QUAD_CONFIG_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DQS_QUAD_CONFIG_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_OPERATE_MODE      , 56  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_OPERATE_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_OPERATE_MODE_LEN  , 4   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_OPERATE_MODE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_EN_DQS_OFFSET     , 60  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_EN_DQS_OFFSET );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DQS_ALIGN_JITTER  , 61  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DQS_ALIGN_JITTER );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_DIS_CLK_GATE      , 62  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_DIS_CLK_GATE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG2_P0_4_4_MAX_DQS_ITER      , 63  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_4_MAX_DQS_ITER );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_HIGH , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_LOW , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_0_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_HIGH , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_LOW , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_1_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_HIGH , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_LOW , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_2_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_HIGH , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_LOW , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_3_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_HIGH , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_LOW , 56  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG3_P0_4_4_DESIRED_EDGE_CNTR_TARGET_LOW_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_0_01_DQS_ALIGN_FIX_DIS , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DQS_ALIGN_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_0_01_CHICKSW_HW278227 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CHICKSW_HW278227 );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_1_01_DQS_ALIGN_FIX_DIS , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DQS_ALIGN_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_1_01_CHICKSW_HW278227 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CHICKSW_HW278227 );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_2_23_DQS_ALIGN_FIX_DIS , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DQS_ALIGN_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_2_23_CHICKSW_HW278227 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CHICKSW_HW278227 );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_3_23_DQS_ALIGN_FIX_DIS , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DQS_ALIGN_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_3_23_CHICKSW_HW278227 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CHICKSW_HW278227 );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_4_4_DQS_ALIGN_FIX_DIS , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DQS_ALIGN_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG4_P0_4_4_CHICKSW_HW278227  , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CHICKSW_HW278227 );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DYN_POWER_CNTL_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DYN_POWER_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DYN_MCTERM_CNTL_EN , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DYN_MCTERM_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DYN_RX_GATE_CNTL_EN , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DYN_RX_GATE_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_CALGATE_ON       , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CALGATE_ON );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_PER_CAL_UPDATE_DISABLE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PER_CAL_UPDATE_DISABLE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DQS_PIPE_FIX_DIS , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DQS_PIPE_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DQS_PIPE_FIX_DIS_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DQS_PIPE_FIX_DIS_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DD2_DQS_FIX_DIS  , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DD2_DQS_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DL_FORCE_ON      , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DL_FORCE_ON );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_BLFIFO_DIS       , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BLFIFO_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_WTRFL_AVE_DIS    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WTRFL_AVE_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_PERCAL_PWR_DIS   , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PERCAL_PWR_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_LOOPBACK_FIX_EN  , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LOOPBACK_FIX_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_LOOPBACK_DLY12   , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LOOPBACK_DLY12 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_DD2_WTRFL_SYNC_DIS , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DD2_WTRFL_SYNC_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_0_01_FORCE_FIFO_CAPTURE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_FORCE_FIFO_CAPTURE );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DYN_POWER_CNTL_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DYN_POWER_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DYN_MCTERM_CNTL_EN , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DYN_MCTERM_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DYN_RX_GATE_CNTL_EN , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DYN_RX_GATE_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_CALGATE_ON       , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CALGATE_ON );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_PER_CAL_UPDATE_DISABLE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PER_CAL_UPDATE_DISABLE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DQS_PIPE_FIX_DIS , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DQS_PIPE_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DQS_PIPE_FIX_DIS_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DQS_PIPE_FIX_DIS_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DD2_DQS_FIX_DIS  , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DD2_DQS_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DL_FORCE_ON      , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DL_FORCE_ON );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_BLFIFO_DIS       , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BLFIFO_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_WTRFL_AVE_DIS    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WTRFL_AVE_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_PERCAL_PWR_DIS   , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PERCAL_PWR_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_LOOPBACK_FIX_EN  , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LOOPBACK_FIX_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_LOOPBACK_DLY12   , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LOOPBACK_DLY12 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_DD2_WTRFL_SYNC_DIS , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DD2_WTRFL_SYNC_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_1_01_FORCE_FIFO_CAPTURE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_FORCE_FIFO_CAPTURE );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DYN_POWER_CNTL_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DYN_POWER_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DYN_MCTERM_CNTL_EN , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DYN_MCTERM_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DYN_RX_GATE_CNTL_EN , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DYN_RX_GATE_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_CALGATE_ON       , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CALGATE_ON );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_PER_CAL_UPDATE_DISABLE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PER_CAL_UPDATE_DISABLE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DQS_PIPE_FIX_DIS , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DQS_PIPE_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DQS_PIPE_FIX_DIS_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DQS_PIPE_FIX_DIS_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DD2_DQS_FIX_DIS  , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DD2_DQS_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DL_FORCE_ON      , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DL_FORCE_ON );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_BLFIFO_DIS       , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BLFIFO_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_WTRFL_AVE_DIS    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WTRFL_AVE_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_PERCAL_PWR_DIS   , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PERCAL_PWR_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_LOOPBACK_FIX_EN  , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LOOPBACK_FIX_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_LOOPBACK_DLY12   , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LOOPBACK_DLY12 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_DD2_WTRFL_SYNC_DIS , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DD2_WTRFL_SYNC_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_2_23_FORCE_FIFO_CAPTURE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_FORCE_FIFO_CAPTURE );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DYN_POWER_CNTL_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DYN_POWER_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DYN_MCTERM_CNTL_EN , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DYN_MCTERM_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DYN_RX_GATE_CNTL_EN , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DYN_RX_GATE_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_CALGATE_ON       , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CALGATE_ON );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_PER_CAL_UPDATE_DISABLE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PER_CAL_UPDATE_DISABLE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DQS_PIPE_FIX_DIS , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DQS_PIPE_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DQS_PIPE_FIX_DIS_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DQS_PIPE_FIX_DIS_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DD2_DQS_FIX_DIS  , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DD2_DQS_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DL_FORCE_ON      , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DL_FORCE_ON );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_BLFIFO_DIS       , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BLFIFO_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_WTRFL_AVE_DIS    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WTRFL_AVE_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_PERCAL_PWR_DIS   , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PERCAL_PWR_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_LOOPBACK_FIX_EN  , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LOOPBACK_FIX_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_LOOPBACK_DLY12   , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LOOPBACK_DLY12 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_DD2_WTRFL_SYNC_DIS , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DD2_WTRFL_SYNC_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_3_23_FORCE_FIFO_CAPTURE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_FORCE_FIFO_CAPTURE );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DYN_POWER_CNTL_EN , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DYN_POWER_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DYN_MCTERM_CNTL_EN , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DYN_MCTERM_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DYN_RX_GATE_CNTL_EN , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DYN_RX_GATE_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_CALGATE_ON        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CALGATE_ON );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_PER_CAL_UPDATE_DISABLE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_PER_CAL_UPDATE_DISABLE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DQS_PIPE_FIX_DIS  , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DQS_PIPE_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DQS_PIPE_FIX_DIS_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DQS_PIPE_FIX_DIS_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DD2_DQS_FIX_DIS   , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DD2_DQS_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DL_FORCE_ON       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DL_FORCE_ON );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_BLFIFO_DIS        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_BLFIFO_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_WTRFL_AVE_DIS     , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_WTRFL_AVE_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_PERCAL_PWR_DIS    , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_PERCAL_PWR_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_LOOPBACK_FIX_EN   , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LOOPBACK_FIX_EN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_LOOPBACK_DLY12    , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LOOPBACK_DLY12 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_DD2_WTRFL_SYNC_DIS , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DD2_WTRFL_SYNC_DIS );
+REG64_FLD( MCA_DDRPHY_DP16_RD_DIA_CONFIG5_P0_4_4_FORCE_FIFO_CAPTURE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_FORCE_FIFO_CAPTURE );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_NO_EYE_DETECTED_MASK , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_EYE_DETECTED_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_LEADING_EDGE_FOUND_MASK , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEADING_EDGE_FOUND_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_TRAILING_EDGE_FOUND_MASK , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_TRAILING_EDGE_FOUND_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N0_MASK , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N0_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N1_MASK , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N1_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N2_MASK , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N2_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_INCOMPLETE_CAL_N3_MASK , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N3_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N0_MASK , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N0_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N1_MASK , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N1_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N2_MASK , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N2_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_COARSE_PATTERN_ERR_N3_MASK , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N3_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_EYE_CLIPPING_MASK , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EYE_CLIPPING_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_NO_DQS_MASK      , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_DQS_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_NO_LOCK_MASK     , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_LOCK_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_DRIFT_MASK       , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DRIFT_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_0_01_MIN_EYE_MASK     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_EYE_MASK );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_NO_EYE_DETECTED_MASK , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_EYE_DETECTED_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_LEADING_EDGE_FOUND_MASK , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEADING_EDGE_FOUND_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_TRAILING_EDGE_FOUND_MASK , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_TRAILING_EDGE_FOUND_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N0_MASK , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N0_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N1_MASK , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N1_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N2_MASK , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N2_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_INCOMPLETE_CAL_N3_MASK , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N3_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N0_MASK , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N0_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N1_MASK , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N1_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N2_MASK , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N2_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_COARSE_PATTERN_ERR_N3_MASK , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N3_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_EYE_CLIPPING_MASK , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EYE_CLIPPING_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_NO_DQS_MASK      , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_DQS_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_NO_LOCK_MASK     , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_LOCK_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_DRIFT_MASK       , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DRIFT_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_1_01_MIN_EYE_MASK     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_EYE_MASK );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_NO_EYE_DETECTED_MASK , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_EYE_DETECTED_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_LEADING_EDGE_FOUND_MASK , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEADING_EDGE_FOUND_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_TRAILING_EDGE_FOUND_MASK , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_TRAILING_EDGE_FOUND_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N0_MASK , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N0_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N1_MASK , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N1_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N2_MASK , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N2_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_INCOMPLETE_CAL_N3_MASK , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N3_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N0_MASK , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N0_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N1_MASK , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N1_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N2_MASK , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N2_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_COARSE_PATTERN_ERR_N3_MASK , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N3_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_EYE_CLIPPING_MASK , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EYE_CLIPPING_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_NO_DQS_MASK      , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_DQS_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_NO_LOCK_MASK     , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_LOCK_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_DRIFT_MASK       , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DRIFT_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_2_23_MIN_EYE_MASK     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_EYE_MASK );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_NO_EYE_DETECTED_MASK , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_EYE_DETECTED_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_LEADING_EDGE_FOUND_MASK , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEADING_EDGE_FOUND_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_TRAILING_EDGE_FOUND_MASK , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_TRAILING_EDGE_FOUND_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N0_MASK , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N0_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N1_MASK , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N1_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N2_MASK , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N2_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_INCOMPLETE_CAL_N3_MASK , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N3_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N0_MASK , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N0_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N1_MASK , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N1_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N2_MASK , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N2_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_COARSE_PATTERN_ERR_N3_MASK , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N3_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_EYE_CLIPPING_MASK , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EYE_CLIPPING_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_NO_DQS_MASK      , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_DQS_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_NO_LOCK_MASK     , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_LOCK_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_DRIFT_MASK       , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DRIFT_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_3_23_MIN_EYE_MASK     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_EYE_MASK );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_NO_EYE_DETECTED_MASK , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NO_EYE_DETECTED_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_LEADING_EDGE_FOUND_MASK , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LEADING_EDGE_FOUND_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_TRAILING_EDGE_FOUND_MASK , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_TRAILING_EDGE_FOUND_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N0_MASK , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_INCOMPLETE_CAL_N0_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N1_MASK , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_INCOMPLETE_CAL_N1_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N2_MASK , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_INCOMPLETE_CAL_N2_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_INCOMPLETE_CAL_N3_MASK , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_INCOMPLETE_CAL_N3_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N0_MASK , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_COARSE_PATTERN_ERR_N0_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N1_MASK , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_COARSE_PATTERN_ERR_N1_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N2_MASK , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_COARSE_PATTERN_ERR_N2_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_COARSE_PATTERN_ERR_N3_MASK , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_COARSE_PATTERN_ERR_N3_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_EYE_CLIPPING_MASK , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_EYE_CLIPPING_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_NO_DQS_MASK       , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NO_DQS_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_NO_LOCK_MASK      , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NO_LOCK_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_DRIFT_MASK        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DRIFT_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_ERROR_MASK0_P0_4_4_MIN_EYE_MASK      , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MIN_EYE_MASK );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_0_01_LEADING_EDGE_NOT_FOUND_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_LEADING_EDGE_NOT_FOUND_15 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_0_01_LEADING_EDGE_NOT_FOUND_15_LEN , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_01_LEADING_EDGE_NOT_FOUND_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_1_01_LEADING_EDGE_NOT_FOUND_0_15 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_01_LEADING_EDGE_NOT_FOUND_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_1_01_LEADING_EDGE_NOT_FOUND_0_15_LEN , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_01_LEADING_EDGE_NOT_FOUND_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_2_23_LEADING_EDGE_NOT_FOUND_0_15 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_2_23_LEADING_EDGE_NOT_FOUND_0_15_LEN , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_3_23_LEADING_EDGE_NOT_FOUND_0_15 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_3_23_LEADING_EDGE_NOT_FOUND_0_15_LEN , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_4_4_LEADING_EDGE_NOT_FOUND_0_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS0_P0_4_4_LEADING_EDGE_NOT_FOUND_0_15_LEN , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_0_01_LEADING_EDGE_NOT_FOUND_16_23 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_0_01_LEADING_EDGE_NOT_FOUND_16_23_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_1_01_LEADING_EDGE_NOT_FOUND_16_23 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_1_01_LEADING_EDGE_NOT_FOUND_16_23_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_2_23_LEADING_EDGE_NOT_FOUND_16_23 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_2_23_LEADING_EDGE_NOT_FOUND_16_23_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_3_23_LEADING_EDGE_NOT_FOUND_16_23 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_3_23_LEADING_EDGE_NOT_FOUND_16_23_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_4_4_LEADING_EDGE_NOT_FOUND_16_23 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS1_P0_4_4_LEADING_EDGE_NOT_FOUND_16_23_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_0_01_TRAILING_EDGE_NOT_FOUND_15 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_0_01_TRAILING_EDGE_NOT_FOUND_15_LEN , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_1_01_TRAILING_EDGE_NOT_FOUND_0_15 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_1_01_TRAILING_EDGE_NOT_FOUND_0_15_LEN , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_2_23_TRAILING_EDGE_NOT_FOUND_0_15 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_2_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_3_23_TRAILING_EDGE_NOT_FOUND_0_15 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_3_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_4_4_TRAILING_EDGE_NOT_FOUND_0_15 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS2_P0_4_4_TRAILING_EDGE_NOT_FOUND_0_15_LEN , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_0_01_TRAILING_EDGE_NOT_FOUND_16_23 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_0_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_1_01_TRAILING_EDGE_NOT_FOUND_16_23 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_1_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_2_23_TRAILING_EDGE_NOT_FOUND_16_23 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_2_23_TRAILING_EDGE_NOT_FOUND_16_23_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_3_23_TRAILING_EDGE_NOT_FOUND_16_23 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_3_23_TRAILING_EDGE_NOT_FOUND_16_23_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_4_4_TRAILING_EDGE_NOT_FOUND_16_23 , 48  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_LVL_STATUS3_P0_4_4_TRAILING_EDGE_NOT_FOUND_16_23_LEN , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RO  , SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_NO_EYE_DETECTED      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_EYE_DETECTED );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_LEADING_EDGE_NOT_FOUND , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEADING_EDGE_NOT_FOUND );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_TRAILING_EDGE_NOT_FOUND , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_TRAILING_EDGE_NOT_FOUND );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N0    , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N1    , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N2    , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N2 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_INCOMPLETE_CAL_N3    , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N3 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N0 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N2 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N2 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_COARSE_PATTERN_ERR_N3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N3 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_EYE_CLIPPING         , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EYE_CLIPPING );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_NO_DQS               , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_DQS  );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_NO_LOCK              , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_LOCK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_DRIFT_ERROR          , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DRIFT_ERROR );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_0_01_MIN_EYE              , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_EYE );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_NO_EYE_DETECTED      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_EYE_DETECTED );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_LEADING_EDGE_NOT_FOUND , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEADING_EDGE_NOT_FOUND );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_TRAILING_EDGE_NOT_FOUND , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_TRAILING_EDGE_NOT_FOUND );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N0    , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N1    , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N2    , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N2 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_INCOMPLETE_CAL_N3    , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INCOMPLETE_CAL_N3 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N0 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N2 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N2 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_COARSE_PATTERN_ERR_N3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_COARSE_PATTERN_ERR_N3 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_EYE_CLIPPING         , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_EYE_CLIPPING );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_NO_DQS               , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_DQS  );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_NO_LOCK              , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_LOCK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_DRIFT_ERROR          , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DRIFT_ERROR );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_1_01_MIN_EYE              , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_EYE );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_NO_EYE_DETECTED      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_EYE_DETECTED );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_LEADING_EDGE_NOT_FOUND , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEADING_EDGE_NOT_FOUND );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_TRAILING_EDGE_NOT_FOUND , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_TRAILING_EDGE_NOT_FOUND );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N0    , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N1    , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N2    , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N2 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_INCOMPLETE_CAL_N3    , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N3 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N0 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N2 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N2 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_COARSE_PATTERN_ERR_N3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N3 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_EYE_CLIPPING         , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EYE_CLIPPING );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_NO_DQS               , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_DQS  );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_NO_LOCK              , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_LOCK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_DRIFT_ERROR          , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DRIFT_ERROR );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_2_23_MIN_EYE              , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_EYE );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_NO_EYE_DETECTED      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_EYE_DETECTED );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_LEADING_EDGE_NOT_FOUND , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEADING_EDGE_NOT_FOUND );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_TRAILING_EDGE_NOT_FOUND , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_TRAILING_EDGE_NOT_FOUND );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N0    , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N1    , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N2    , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N2 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_INCOMPLETE_CAL_N3    , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INCOMPLETE_CAL_N3 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N0 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N2 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N2 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_COARSE_PATTERN_ERR_N3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_COARSE_PATTERN_ERR_N3 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_EYE_CLIPPING         , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_EYE_CLIPPING );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_NO_DQS               , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_DQS  );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_NO_LOCK              , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_LOCK );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_DRIFT_ERROR          , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DRIFT_ERROR );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_3_23_MIN_EYE              , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_EYE );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_NO_EYE_DETECTED       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NO_EYE_DETECTED );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_LEADING_EDGE_NOT_FOUND , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LEADING_EDGE_NOT_FOUND );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_TRAILING_EDGE_NOT_FOUND , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_TRAILING_EDGE_NOT_FOUND );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N0     , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_INCOMPLETE_CAL_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N1     , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_INCOMPLETE_CAL_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N2     , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_INCOMPLETE_CAL_N2 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_INCOMPLETE_CAL_N3     , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_INCOMPLETE_CAL_N3 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N0 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_COARSE_PATTERN_ERR_N0 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_COARSE_PATTERN_ERR_N1 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N2 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_COARSE_PATTERN_ERR_N2 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_COARSE_PATTERN_ERR_N3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_COARSE_PATTERN_ERR_N3 );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_EYE_CLIPPING          , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_EYE_CLIPPING );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_NO_DQS                , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NO_DQS   );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_NO_LOCK               , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NO_LOCK  );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_DRIFT_ERROR           , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DRIFT_ERROR );
+REG64_FLD( MCA_DDRPHY_DP16_RD_STATUS0_P0_4_4_MIN_EYE               , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MIN_EYE  );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0_01_NIB0_EN_FORCE , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB0_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0_01_NIB0          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB0    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0_01_NIB0_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0_01_NIB1_EN_FORCE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB1_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0_01_NIB1          , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB1    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_0_01_NIB1_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1_01_NIB0_EN_FORCE , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB0_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1_01_NIB0          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB0    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1_01_NIB0_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1_01_NIB1_EN_FORCE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB1_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1_01_NIB1          , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB1    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_1_01_NIB1_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2_23_NIB0_EN_FORCE , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB0_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2_23_NIB0          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB0    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2_23_NIB0_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2_23_NIB1_EN_FORCE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB1_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2_23_NIB1          , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB1    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_2_23_NIB1_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3_23_NIB0_EN_FORCE , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB0_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3_23_NIB0          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB0    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3_23_NIB0_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3_23_NIB1_EN_FORCE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB1_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3_23_NIB1          , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB1    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_3_23_NIB1_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4_4_NIB0_EN_FORCE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB0_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4_4_NIB0           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB0     );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4_4_NIB0_LEN       , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4_4_NIB1_EN_FORCE  , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB1_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4_4_NIB1           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB1     );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE0_DAC_P0_4_4_NIB1_LEN       , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0_01_NIB2_EN_FORCE , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB2_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0_01_NIB2          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB2    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0_01_NIB2_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0_01_NIB3_EN_FORCE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB3_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0_01_NIB3          , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB3    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_0_01_NIB3_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1_01_NIB2_EN_FORCE , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB2_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1_01_NIB2          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB2    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1_01_NIB2_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1_01_NIB3_EN_FORCE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB3_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1_01_NIB3          , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB3    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_1_01_NIB3_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2_23_NIB2_EN_FORCE , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB2_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2_23_NIB2          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB2    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2_23_NIB2_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2_23_NIB3_EN_FORCE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB3_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2_23_NIB3          , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB3    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_2_23_NIB3_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3_23_NIB2_EN_FORCE , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB2_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3_23_NIB2          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB2    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3_23_NIB2_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3_23_NIB3_EN_FORCE , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB3_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3_23_NIB3          , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB3    );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_3_23_NIB3_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4_4_NIB2_EN_FORCE  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB2_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4_4_NIB2           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB2     );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4_4_NIB2_LEN       , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4_4_NIB3_EN_FORCE  , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB3_EN_FORCE );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4_4_NIB3           , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB3     );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_BYTE1_DAC_P0_4_4_NIB3_LEN       , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0_01                  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_0_01_LEN              , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1_01                  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_1_01_LEN              , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2_23                  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_2_23_LEN              , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3_23                  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_3_23_LEN              , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4_4                   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4          );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_EN_P0_4_4_LEN               , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LEN      );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0_01               , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_0_01_LEN           , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1_01               , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_1_01_LEN           , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2_23               , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_2_23_LEN           , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3_23               , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_3_23_LEN           , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4_4                , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4          );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_CAL_ERROR_P0_4_4_LEN            , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_LEN      );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_0_01            , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_0_01_LEN        , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_1_01            , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_1_01_LEN        , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_2_23            , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_2_23_LEN        , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_3_23            , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_3_23_LEN        , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_4_4             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4          );
+REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_DAC_COMP_OUT_P0_4_4_LEN         , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_LEN      );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_0_01_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_1_01_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_2_23_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_3_23_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR0_P0_4_4_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_0_01_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_1_01_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_2_23_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_3_23_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR1_P0_4_4_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_0_01_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_1_01_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_2_23_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_3_23_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR2_P0_4_4_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_0_01_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_1_01_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_2_23_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_3_23_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD0_CLK16 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD1_CLK16 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD0_CLK18 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD1_CLK18 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD2_CLK20 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD3_CLK20 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD2_CLK22 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_CLOCK_RANK_PAIR3_P0_4_4_QUAD3_CLK22 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK22 );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD_LEN    , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_0_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_1_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_2_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_3_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR0_P0_4_4_RD_LEN    , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY1_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD_LEN    , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY2_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_0_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_1_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_2_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_3_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR1_P0_4_4_RD_LEN    , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY3_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD_LEN    , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY4_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_0_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_1_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_2_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_3_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR2_P0_4_4_RD_LEN    , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY5_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_0_01_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_1_01_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_2_23_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_3_23_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD_LEN    , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD_DELAY7 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY6_RANK_PAIR3_P0_4_4_RD_DELAY7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_0_01_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_1_01_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_2_23_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_3_23_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY0 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR0_P0_4_4_RD_DELAY1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_0_01_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_1_01_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_2_23_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_3_23_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR1_P0_4_4_RD_DELAY3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_0_01_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_1_01_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_2_23_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_3_23_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY4 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY5 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR2_P0_4_4_RD_DELAY5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_0_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_1_01_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_2_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_3_23_RD_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD_DELAY6 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD_DELAY6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_DELAY6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY7_RANK_PAIR3_P0_4_4_RD_LEN    , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEN     );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_0_01_OFFSET1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEN     );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01_OFFSET1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_1_01_OFFSET1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEN     );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23_OFFSET1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_2_23_OFFSET1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEN     );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23_OFFSET1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_3_23_OFFSET1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4    , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4          );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LEN      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4_OFFSET1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET1  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR0_P0_4_4_OFFSET1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_0_01_OFFSET3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_1_01_OFFSET3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_2_23_OFFSET3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_3_23_OFFSET3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET2  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET3  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR1_P0_4_4_OFFSET3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET4 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET5 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_0_01_OFFSET5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET4 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET5 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_1_01_OFFSET5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET4 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET5 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_2_23_OFFSET5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET4 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET5 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_3_23_OFFSET5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET4 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET4  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET5 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET5  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR2_P0_4_4_OFFSET5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET6 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET7 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_0_01_OFFSET7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET6 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET7 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_1_01_OFFSET7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET6 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET7 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_2_23_OFFSET7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET6 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET7 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_3_23_OFFSET7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET6 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET6  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET7 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET7  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET0_RANK_PAIR3_P0_4_4_OFFSET7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01_OFFSET0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01_OFFSET0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_0_01_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01_OFFSET0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01_OFFSET0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_1_01_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23_OFFSET0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23_OFFSET0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_2_23_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23_OFFSET0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23_OFFSET0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_3_23_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4_OFFSET0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET0  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4_OFFSET0_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4          );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR0_P0_4_4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LEN      );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_0_01_OFFSET3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_1_01_OFFSET3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_2_23_OFFSET3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_3_23_OFFSET3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET2  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET3  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR1_P0_4_4_OFFSET3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET4 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET5 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_0_01_OFFSET5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET4 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET5 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_1_01_OFFSET5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET4 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET5 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_2_23_OFFSET5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET4 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET5 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_3_23_OFFSET5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET4 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET4  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET4_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET5 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET5  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR2_P0_4_4_OFFSET5_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET6 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET7 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_0_01_OFFSET7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET6 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET7 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_1_01_OFFSET7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET6 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET7 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_2_23_OFFSET7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET6 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET7 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_3_23_OFFSET7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET6 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET6  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET6_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET7 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET7  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DELAY_OFFSET1_RANK_PAIR3_P0_4_4_OFFSET7_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0_01       , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_0_01_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1_01       , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_1_01_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2_23       , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_2_23_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3_23       , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_3_23_LEN   , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEN     );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4_4        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4          );
+REG64_FLD( MCA_DDRPHY_DP16_READ_DQS_TIMING_REFERENCE_P0_4_4_LEN    , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LEN      );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE0_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE10_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE11_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_0_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_1_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_2_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_3_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD     , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR0_P0_4_4_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE1_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE2_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_0_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_1_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_2_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_3_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD     , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR1_P0_4_4_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE3_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE4_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_0_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_1_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_2_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_3_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD     , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR2_P0_4_4_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE5_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE6_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_0_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_1_01_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_2_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD    , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_3_23_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_LEN  );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD     , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD       );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE7_RANK_PAIR3_P0_4_4_RD_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_LEN   );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE8_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_0_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_1_01_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_2_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_3_23_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR0_P0_4_4_RD_SIZE1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_0_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_1_01_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_2_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_3_23_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR1_P0_4_4_RD_SIZE3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_0_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_1_01_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_2_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_3_23_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE4 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE4_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE4_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE5 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR2_P0_4_4_RD_SIZE5_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE5_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_0_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_1_01_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_2_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_3_23_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE6 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE6_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE6_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE7 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_EYE_SIZE9_RANK_PAIR3_P0_4_4_RD_SIZE7_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RD_SIZE7_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEN     );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01_REFERENCE1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REFERENCE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_0_01_REFERENCE1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REFERENCE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_LEN     );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01_REFERENCE1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REFERENCE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_1_01_REFERENCE1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REFERENCE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEN     );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23_REFERENCE1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REFERENCE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_2_23_REFERENCE1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REFERENCE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23         );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_LEN     );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23_REFERENCE1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REFERENCE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_3_23_REFERENCE1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REFERENCE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4          );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4_LEN       , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LEN      );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4_REFERENCE1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REFERENCE1 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE0_P0_4_4_REFERENCE1_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REFERENCE1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REFERENCE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REFERENCE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REFERENCE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_0_01_REFERENCE3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REFERENCE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REFERENCE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REFERENCE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REFERENCE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_1_01_REFERENCE3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_REFERENCE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REFERENCE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REFERENCE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REFERENCE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_2_23_REFERENCE3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REFERENCE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REFERENCE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REFERENCE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REFERENCE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_3_23_REFERENCE3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_REFERENCE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REFERENCE2 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE2_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REFERENCE2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REFERENCE3 );
+REG64_FLD( MCA_DDRPHY_DP16_READ_TIMING_REFERENCE1_P0_4_4_REFERENCE3_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_REFERENCE3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_NIB0TCFLIP_DC       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB0TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_NIB1TCFLIP_DC       , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB1TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_NIB2TCFLIP_DC       , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB2TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_NIB3TCFLIP_DC       , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB3TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_DISABLE_TERMINATION , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_TERMINATION );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_READ_CENTERING_MODE , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_READ_CENTERING_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_0_01_READ_CENTERING_MODE_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_READ_CENTERING_MODE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1_01_NIB0TCFLIP_DC       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB0TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1_01_NIB1TCFLIP_DC       , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB1TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1_01_NIB2TCFLIP_DC       , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB2TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1_01_NIB3TCFLIP_DC       , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NIB3TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1_01_DISABLE_TERMINATION , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DISABLE_TERMINATION );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1_01_READ_CENTERING_MODE , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_READ_CENTERING_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_1_01_READ_CENTERING_MODE_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_READ_CENTERING_MODE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2_23_NIB0TCFLIP_DC       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB0TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2_23_NIB1TCFLIP_DC       , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB1TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2_23_NIB2TCFLIP_DC       , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB2TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2_23_NIB3TCFLIP_DC       , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB3TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2_23_DISABLE_TERMINATION , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_TERMINATION );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2_23_READ_CENTERING_MODE , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_READ_CENTERING_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_2_23_READ_CENTERING_MODE_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_READ_CENTERING_MODE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3_23_NIB0TCFLIP_DC       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB0TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3_23_NIB1TCFLIP_DC       , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB1TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3_23_NIB2TCFLIP_DC       , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB2TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3_23_NIB3TCFLIP_DC       , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NIB3TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3_23_DISABLE_TERMINATION , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DISABLE_TERMINATION );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3_23_READ_CENTERING_MODE , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_READ_CENTERING_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_3_23_READ_CENTERING_MODE_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_READ_CENTERING_MODE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_NIB0TCFLIP_DC        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB0TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_NIB1TCFLIP_DC        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB1TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_NIB2TCFLIP_DC        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB2TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_NIB3TCFLIP_DC        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NIB3TCFLIP_DC );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_DISABLE_TERMINATION  , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DISABLE_TERMINATION );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_READ_CENTERING_MODE  , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_READ_CENTERING_MODE );
+REG64_FLD( MCA_DDRPHY_DP16_RX_PEAK_AMP_P0_4_4_READ_CENTERING_MODE_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_READ_CENTERING_MODE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ROT_OVERRIDE         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ROT_OVERRIDE_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_OVERRIDE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ROT_OVERRIDE_EN      , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_OVERRIDE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_PHASE_ALIGN_RESET    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PHASE_ALIGN_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_PHASE_CNTL_EN        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PHASE_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_PHASE_DEFAULT_EN     , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PHASE_DEFAULT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_POS_EDGE_ALIGN       , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_POS_EDGE_ALIGN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_CONTINUOUS_UPDATE    , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CONTINUOUS_UPDATE );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ROT_OVERRIDE         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ROT_OVERRIDE_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_OVERRIDE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_ROT_OVERRIDE_EN      , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_OVERRIDE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_PHASE_ALIGN_RESET    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PHASE_ALIGN_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_PHASE_CNTL_EN        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PHASE_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_PHASE_DEFAULT_EN     , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PHASE_DEFAULT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_POS_EDGE_ALIGN       , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_POS_EDGE_ALIGN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_1_01_CONTINUOUS_UPDATE    , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CONTINUOUS_UPDATE );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ROT_OVERRIDE         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ROT_OVERRIDE_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_OVERRIDE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_ROT_OVERRIDE_EN      , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_OVERRIDE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_PHASE_ALIGN_RESET    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PHASE_ALIGN_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_PHASE_CNTL_EN        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PHASE_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_PHASE_DEFAULT_EN     , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PHASE_DEFAULT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_POS_EDGE_ALIGN       , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_POS_EDGE_ALIGN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_2_23_CONTINUOUS_UPDATE    , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CONTINUOUS_UPDATE );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ROT_OVERRIDE         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ROT_OVERRIDE_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_OVERRIDE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_ROT_OVERRIDE_EN      , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_OVERRIDE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_PHASE_ALIGN_RESET    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PHASE_ALIGN_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_PHASE_CNTL_EN        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PHASE_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_PHASE_DEFAULT_EN     , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PHASE_DEFAULT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_POS_EDGE_ALIGN       , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_POS_EDGE_ALIGN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_3_23_CONTINUOUS_UPDATE    , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CONTINUOUS_UPDATE );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ROT_OVERRIDE          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ROT_OVERRIDE_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_OVERRIDE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_ROT_OVERRIDE_EN       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_OVERRIDE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_PHASE_ALIGN_RESET     , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_PHASE_ALIGN_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_PHASE_CNTL_EN         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_PHASE_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_PHASE_DEFAULT_EN      , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_PHASE_DEFAULT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_POS_EDGE_ALIGN        , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_POS_EDGE_ALIGN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_4_4_CONTINUOUS_UPDATE     , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CONTINUOUS_UPDATE );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ROT_OVERRIDE         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ROT_OVERRIDE_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_OVERRIDE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_ROT_OVERRIDE_EN      , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_OVERRIDE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_PHASE_ALIGN_RESET    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PHASE_ALIGN_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_PHASE_CNTL_EN        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PHASE_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_PHASE_DEFAULT_EN     , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PHASE_DEFAULT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_POS_EDGE_ALIGN       , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_POS_EDGE_ALIGN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_0_01_CONTINUOUS_UPDATE    , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CONTINUOUS_UPDATE );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ROT_OVERRIDE         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ROT_OVERRIDE_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_OVERRIDE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_ROT_OVERRIDE_EN      , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ROT_OVERRIDE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_PHASE_ALIGN_RESET    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PHASE_ALIGN_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_PHASE_CNTL_EN        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PHASE_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_PHASE_DEFAULT_EN     , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_PHASE_DEFAULT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_POS_EDGE_ALIGN       , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_POS_EDGE_ALIGN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_1_01_CONTINUOUS_UPDATE    , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CONTINUOUS_UPDATE );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ROT_OVERRIDE         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ROT_OVERRIDE_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_OVERRIDE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_ROT_OVERRIDE_EN      , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_OVERRIDE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_PHASE_ALIGN_RESET    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PHASE_ALIGN_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_PHASE_CNTL_EN        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PHASE_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_PHASE_DEFAULT_EN     , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PHASE_DEFAULT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_POS_EDGE_ALIGN       , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_POS_EDGE_ALIGN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_2_23_CONTINUOUS_UPDATE    , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CONTINUOUS_UPDATE );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ROT_OVERRIDE         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ROT_OVERRIDE_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_OVERRIDE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_ROT_OVERRIDE_EN      , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ROT_OVERRIDE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_PHASE_ALIGN_RESET    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PHASE_ALIGN_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_PHASE_CNTL_EN        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PHASE_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_PHASE_DEFAULT_EN     , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_PHASE_DEFAULT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_POS_EDGE_ALIGN       , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_POS_EDGE_ALIGN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_3_23_CONTINUOUS_UPDATE    , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CONTINUOUS_UPDATE );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ROT_OVERRIDE          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ROT_OVERRIDE_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_OVERRIDE_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_ROT_OVERRIDE_EN       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ROT_OVERRIDE_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_PHASE_ALIGN_RESET     , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_PHASE_ALIGN_RESET );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_PHASE_CNTL_EN         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_PHASE_CNTL_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_PHASE_DEFAULT_EN      , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_PHASE_DEFAULT_EN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_POS_EDGE_ALIGN        , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_POS_EDGE_ALIGN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR1_P0_4_4_CONTINUOUS_UPDATE     , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CONTINUOUS_UPDATE );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_BB_LOCK0        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BB_LOCK0 );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT0            , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT0    );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT0_LEN        , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_BB_LOCK1        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BB_LOCK1 );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT1            , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT1    );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_0_01_ROT1_LEN        , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_BB_LOCK0        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BB_LOCK0 );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT0            , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT0    );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT0_LEN        , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_BB_LOCK1        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BB_LOCK1 );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT1            , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT1    );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_1_01_ROT1_LEN        , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_ROT1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_BB_LOCK0        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BB_LOCK0 );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT0            , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT0    );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT0_LEN        , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_BB_LOCK1        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BB_LOCK1 );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT1            , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT1    );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_2_23_ROT1_LEN        , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_BB_LOCK0        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BB_LOCK0 );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT0            , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT0    );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT0_LEN        , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_BB_LOCK1        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BB_LOCK1 );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT1            , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT1    );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_3_23_ROT1_LEN        , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_ROT1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_BB_LOCK0         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_BB_LOCK0 );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT0             , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT0     );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT0_LEN         , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_BB_LOCK1         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_BB_LOCK1 );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT1             , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT1     );
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR_VALUE_P0_4_4_ROT1_LEN         , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_ROT1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_0_01_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_1_01_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_2_23_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_3_23_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD0_CLK16         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD1_CLK16         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD2_CLK16         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD3_CLK16         , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD0_CLK18         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD1_CLK18         , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD2_CLK20         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD3_CLK20         , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD2_CLK22         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD3_CLK22         , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_CLK16_SINGLE_ENDED  , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_CLK18_SINGLE_ENDED  , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_CLK20_SINGLE_ENDED  , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_CLK22_SINGLE_ENDED  , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD2_CLK18         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP0_P0_4_4_QUAD3_CLK18         , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_0_01_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_1_01_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_2_23_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_3_23_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD0_CLK16         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD1_CLK16         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD2_CLK16         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD3_CLK16         , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD0_CLK18         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD1_CLK18         , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD2_CLK20         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD3_CLK20         , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD2_CLK22         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD3_CLK22         , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_CLK16_SINGLE_ENDED  , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_CLK18_SINGLE_ENDED  , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_CLK20_SINGLE_ENDED  , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_CLK22_SINGLE_ENDED  , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD2_CLK18         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP1_P0_4_4_QUAD3_CLK18         , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_0_01_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_1_01_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_2_23_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_3_23_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD0_CLK16         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD1_CLK16         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD2_CLK16         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD3_CLK16         , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD0_CLK18         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD1_CLK18         , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD2_CLK20         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD3_CLK20         , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD2_CLK22         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD3_CLK22         , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_CLK16_SINGLE_ENDED  , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_CLK18_SINGLE_ENDED  , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_CLK20_SINGLE_ENDED  , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_CLK22_SINGLE_ENDED  , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD2_CLK18         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP2_P0_4_4_QUAD3_CLK18         , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_0_01_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_1_01_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_2_23_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD0_CLK16        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD1_CLK16        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK16        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK16        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD0_CLK18        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD1_CLK18        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK20        , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK20        , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK22        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK22        , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_CLK16_SINGLE_ENDED , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_CLK18_SINGLE_ENDED , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_CLK20_SINGLE_ENDED , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_CLK22_SINGLE_ENDED , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD2_CLK18        , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_3_23_QUAD3_CLK18        , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD0_CLK16         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD1_CLK16         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD2_CLK16         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD3_CLK16         , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD0_CLK18         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD0_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD1_CLK18         , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD1_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD2_CLK20         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD3_CLK20         , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD2_CLK22         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD3_CLK22         , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_CLK16_SINGLE_ENDED  , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK16_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_CLK18_SINGLE_ENDED  , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK18_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_CLK20_SINGLE_ENDED  , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK20_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_CLK22_SINGLE_ENDED  , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK22_SINGLE_ENDED );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD2_CLK18         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD2_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_EN_RP3_P0_4_4_QUAD3_CLK18         , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_QUAD3_CLK18 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS                   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_TSYS    );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS_LEN               , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_TSYS_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_1_01_TSYS                   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_TSYS    );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_1_01_TSYS_LEN               , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_TSYS_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_2_23_TSYS                   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_TSYS    );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_2_23_TSYS_LEN               , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_TSYS_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_3_23_TSYS                   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_TSYS    );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_3_23_TSYS_LEN               , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_TSYS_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_4_4_TSYS                    , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_TSYS     );
+REG64_FLD( MCA_DDRPHY_DP16_WRCLK_PR_P0_4_4_TSYS_LEN                , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_TSYS_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_BIT_CENTERED    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BIT_CENTERED );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_BIT_CENTERED_LEN , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BIT_CENTERED_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_SMALL_STEP_LEFT , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_SMALL_STEP_LEFT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_BIG_STEP_RIGHT  , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BIG_STEP_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_MATCH_STEP_RIGHT , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MATCH_STEP_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_JUMP_BACK_RIGHT , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_JUMP_BACK_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_SMALL_STEP_RIGHT , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_SMALL_STEP_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_0_01_DONE            , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_DONE    );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_BIT_CENTERED    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BIT_CENTERED );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_BIT_CENTERED_LEN , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BIT_CENTERED_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_SMALL_STEP_LEFT , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_SMALL_STEP_LEFT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_BIG_STEP_RIGHT  , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BIG_STEP_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_MATCH_STEP_RIGHT , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MATCH_STEP_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_JUMP_BACK_RIGHT , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_JUMP_BACK_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_SMALL_STEP_RIGHT , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_SMALL_STEP_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_1_01_DONE            , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_DONE    );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_BIT_CENTERED    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BIT_CENTERED );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_BIT_CENTERED_LEN , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BIT_CENTERED_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_SMALL_STEP_LEFT , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_SMALL_STEP_LEFT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_BIG_STEP_RIGHT  , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BIG_STEP_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_MATCH_STEP_RIGHT , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MATCH_STEP_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_JUMP_BACK_RIGHT , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_JUMP_BACK_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_SMALL_STEP_RIGHT , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_SMALL_STEP_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_2_23_DONE            , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_DONE    );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_BIT_CENTERED    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BIT_CENTERED );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_BIT_CENTERED_LEN , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BIT_CENTERED_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_SMALL_STEP_LEFT , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_SMALL_STEP_LEFT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_BIG_STEP_RIGHT  , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BIG_STEP_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_MATCH_STEP_RIGHT , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MATCH_STEP_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_JUMP_BACK_RIGHT , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_JUMP_BACK_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_SMALL_STEP_RIGHT , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_SMALL_STEP_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_3_23_DONE            , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_DONE    );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_BIT_CENTERED     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_BIT_CENTERED );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_BIT_CENTERED_LEN , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_BIT_CENTERED_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_SMALL_STEP_LEFT  , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_SMALL_STEP_LEFT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_BIG_STEP_RIGHT   , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_BIG_STEP_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_MATCH_STEP_RIGHT , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_MATCH_STEP_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_JUMP_BACK_RIGHT  , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_JUMP_BACK_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_SMALL_STEP_RIGHT , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_SMALL_STEP_RIGHT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS0_P0_4_4_DONE             , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_DONE     );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0_01_FW_LEFT_SIDE    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_FW_LEFT_SIDE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_0_01_FW_LEFT_SIDE_LEN , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_FW_LEFT_SIDE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1_01_FW_LEFT_SIDE    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_FW_LEFT_SIDE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_1_01_FW_LEFT_SIDE_LEN , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_FW_LEFT_SIDE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2_23_FW_LEFT_SIDE    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_FW_LEFT_SIDE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_2_23_FW_LEFT_SIDE_LEN , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_FW_LEFT_SIDE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3_23_FW_LEFT_SIDE    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_FW_LEFT_SIDE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_3_23_FW_LEFT_SIDE_LEN , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_FW_LEFT_SIDE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4_4_FW_LEFT_SIDE     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_FW_LEFT_SIDE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS1_P0_4_4_FW_LEFT_SIDE_LEN , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_FW_LEFT_SIDE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0_01_FW_RIGHT_SIDE   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_FW_RIGHT_SIDE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_0_01_FW_RIGHT_SIDE_LEN , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_FW_RIGHT_SIDE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1_01_FW_RIGHT_SIDE   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_FW_RIGHT_SIDE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_1_01_FW_RIGHT_SIDE_LEN , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_FW_RIGHT_SIDE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2_23_FW_RIGHT_SIDE   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_FW_RIGHT_SIDE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_2_23_FW_RIGHT_SIDE_LEN , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_FW_RIGHT_SIDE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3_23_FW_RIGHT_SIDE   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_FW_RIGHT_SIDE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_3_23_FW_RIGHT_SIDE_LEN , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_FW_RIGHT_SIDE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4_4_FW_RIGHT_SIDE    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_FW_RIGHT_SIDE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_CNTR_STATUS2_P0_4_4_FW_RIGHT_SIDE_LEN , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_FW_RIGHT_SIDE_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK16          , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_WL_ERR_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK18          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_WL_ERR_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK20          , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_WL_ERR_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_WL_ERR_CLK22          , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_WL_ERR_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_VALID_NS_BIG_L        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_VALID_NS_BIG_L );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_INVALID_NS_SMALL_L    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_INVALID_NS_SMALL_L );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_VALID_NS_BIG_R        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_VALID_NS_BIG_R );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_INVALID_NS_BIG_R      , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_INVALID_NS_BIG_R );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_VALID_NS_JUMP_BACK    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_VALID_NS_JUMP_BACK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_INVALID_NS_SMALL_R    , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_INVALID_NS_SMALL_R );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_0_01_OFFSET_ERR            , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_OFFSET_ERR );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK16          , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_WL_ERR_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK18          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_WL_ERR_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK20          , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_WL_ERR_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_WL_ERR_CLK22          , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_WL_ERR_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_VALID_NS_BIG_L        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_VALID_NS_BIG_L );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_INVALID_NS_SMALL_L    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_INVALID_NS_SMALL_L );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_VALID_NS_BIG_R        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_VALID_NS_BIG_R );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_INVALID_NS_BIG_R      , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_INVALID_NS_BIG_R );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_VALID_NS_JUMP_BACK    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_VALID_NS_JUMP_BACK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_INVALID_NS_SMALL_R    , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_INVALID_NS_SMALL_R );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_1_01_OFFSET_ERR            , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_01_OFFSET_ERR );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK16          , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_WL_ERR_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK18          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_WL_ERR_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK20          , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_WL_ERR_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_WL_ERR_CLK22          , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_WL_ERR_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_VALID_NS_BIG_L        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_VALID_NS_BIG_L );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_INVALID_NS_SMALL_L    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_INVALID_NS_SMALL_L );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_VALID_NS_BIG_R        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_VALID_NS_BIG_R );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_INVALID_NS_BIG_R      , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_INVALID_NS_BIG_R );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_VALID_NS_JUMP_BACK    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_VALID_NS_JUMP_BACK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_INVALID_NS_SMALL_R    , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_INVALID_NS_SMALL_R );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_2_23_OFFSET_ERR            , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_OFFSET_ERR );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK16          , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_WL_ERR_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK18          , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_WL_ERR_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK20          , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_WL_ERR_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_WL_ERR_CLK22          , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_WL_ERR_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_VALID_NS_BIG_L        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_VALID_NS_BIG_L );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_INVALID_NS_SMALL_L    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_INVALID_NS_SMALL_L );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_VALID_NS_BIG_R        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_VALID_NS_BIG_R );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_INVALID_NS_BIG_R      , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_INVALID_NS_BIG_R );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_VALID_NS_JUMP_BACK    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_VALID_NS_JUMP_BACK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_INVALID_NS_SMALL_R    , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_INVALID_NS_SMALL_R );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_3_23_OFFSET_ERR            , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_23_OFFSET_ERR );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK16           , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_4_WL_ERR_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK18           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_4_WL_ERR_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK20           , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_4_WL_ERR_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_WL_ERR_CLK22           , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_4_WL_ERR_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_VALID_NS_BIG_L         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_4_VALID_NS_BIG_L );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_INVALID_NS_SMALL_L     , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_4_INVALID_NS_SMALL_L );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_VALID_NS_BIG_R         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_4_VALID_NS_BIG_R );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_INVALID_NS_BIG_R       , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_4_INVALID_NS_BIG_R );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_VALID_NS_JUMP_BACK     , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_4_VALID_NS_JUMP_BACK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_INVALID_NS_SMALL_R     , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_4_INVALID_NS_SMALL_R );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR0_P0_4_4_OFFSET_ERR             , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RCLRPART,
+           SH_FLD_4_OFFSET_ERR );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_WL_ERR_CLK16_MASK , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ERR_CLK16_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_WL_ERR_CLK18_MASK , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ERR_CLK18_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_WL_ERR_CLK20_MASK , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ERR_CLK20_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_ERR_CLK22_MASK   , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ERR_CLK22_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_VALID_NS_BIG_L_MASK , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALID_NS_BIG_L_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_INVALID_NS_SMALL_L_MASK , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INVALID_NS_SMALL_L_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_VALID_NS_BIG_R_MASK , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALID_NS_BIG_R_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_INVALID_NS_BIG_R_MASK , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INVALID_NS_BIG_R_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_VALID_NS_JUMP_BACK_MASK , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALID_NS_JUMP_BACK_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_INVALID_NS_SMALL_R_MASK , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INVALID_NS_SMALL_R_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_OFFSET_ERR_MASK  , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET_ERR_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_0_01_ADVANCE_PR_VALUE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ADVANCE_PR_VALUE );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_WL_ERR_CLK16_MASK , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ERR_CLK16_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_WL_ERR_CLK18_MASK , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ERR_CLK18_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_WL_ERR_CLK20_MASK , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ERR_CLK20_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_ERR_CLK22_MASK   , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ERR_CLK22_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_VALID_NS_BIG_L_MASK , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALID_NS_BIG_L_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_INVALID_NS_SMALL_L_MASK , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INVALID_NS_SMALL_L_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_VALID_NS_BIG_R_MASK , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALID_NS_BIG_R_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_INVALID_NS_BIG_R_MASK , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INVALID_NS_BIG_R_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_VALID_NS_JUMP_BACK_MASK , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALID_NS_JUMP_BACK_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_INVALID_NS_SMALL_R_MASK , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_INVALID_NS_SMALL_R_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_OFFSET_ERR_MASK  , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_OFFSET_ERR_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_1_01_ADVANCE_PR_VALUE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ADVANCE_PR_VALUE );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_WL_ERR_CLK16_MASK , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ERR_CLK16_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_WL_ERR_CLK18_MASK , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ERR_CLK18_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_WL_ERR_CLK20_MASK , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ERR_CLK20_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_ERR_CLK22_MASK   , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ERR_CLK22_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_VALID_NS_BIG_L_MASK , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALID_NS_BIG_L_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_INVALID_NS_SMALL_L_MASK , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INVALID_NS_SMALL_L_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_VALID_NS_BIG_R_MASK , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALID_NS_BIG_R_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_INVALID_NS_BIG_R_MASK , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INVALID_NS_BIG_R_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_VALID_NS_JUMP_BACK_MASK , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALID_NS_JUMP_BACK_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_INVALID_NS_SMALL_R_MASK , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INVALID_NS_SMALL_R_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_OFFSET_ERR_MASK  , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET_ERR_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_2_23_ADVANCE_PR_VALUE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ADVANCE_PR_VALUE );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_WL_ERR_CLK16_MASK , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ERR_CLK16_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_WL_ERR_CLK18_MASK , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ERR_CLK18_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_WL_ERR_CLK20_MASK , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ERR_CLK20_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_ERR_CLK22_MASK   , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ERR_CLK22_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_VALID_NS_BIG_L_MASK , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALID_NS_BIG_L_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_INVALID_NS_SMALL_L_MASK , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INVALID_NS_SMALL_L_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_VALID_NS_BIG_R_MASK , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALID_NS_BIG_R_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_INVALID_NS_BIG_R_MASK , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INVALID_NS_BIG_R_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_VALID_NS_JUMP_BACK_MASK , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALID_NS_JUMP_BACK_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_INVALID_NS_SMALL_R_MASK , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_INVALID_NS_SMALL_R_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_OFFSET_ERR_MASK  , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_OFFSET_ERR_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_3_23_ADVANCE_PR_VALUE , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ADVANCE_PR_VALUE );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_WL_ERR_CLK16_MASK , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_WL_ERR_CLK16_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_WL_ERR_CLK18_MASK , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_WL_ERR_CLK18_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_WL_ERR_CLK20_MASK , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_WL_ERR_CLK20_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_ERR_CLK22_MASK    , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ERR_CLK22_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_VALID_NS_BIG_L_MASK , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALID_NS_BIG_L_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_INVALID_NS_SMALL_L_MASK , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_INVALID_NS_SMALL_L_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_VALID_NS_BIG_R_MASK , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALID_NS_BIG_R_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_INVALID_NS_BIG_R_MASK , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_INVALID_NS_BIG_R_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_VALID_NS_JUMP_BACK_MASK , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALID_NS_JUMP_BACK_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_INVALID_NS_SMALL_R_MASK , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_INVALID_NS_SMALL_R_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_OFFSET_ERR_MASK   , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_OFFSET_ERR_MASK );
+REG64_FLD( MCA_DDRPHY_DP16_WR_ERROR_MASK0_P0_4_4_ADVANCE_PR_VALUE  , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ADVANCE_PR_VALUE );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_CLK_LEVEL        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK_LEVEL );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_CLK_LEVEL_LEN    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK_LEVEL_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_FINE_STEPPING    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_FINE_STEPPING );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_DONE             , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DONE    );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK16     , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ERR_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK18     , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ERR_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK20     , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ERR_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_WL_ERR_CLK22     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ERR_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_0_01_ZERO_DETECTED    , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ZERO_DETECTED );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_CLK_LEVEL        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK_LEVEL );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_CLK_LEVEL_LEN    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CLK_LEVEL_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_FINE_STEPPING    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_FINE_STEPPING );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_DONE             , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DONE    );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK16     , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ERR_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK18     , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ERR_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK20     , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ERR_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_WL_ERR_CLK22     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_WL_ERR_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_1_01_ZERO_DETECTED    , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_ZERO_DETECTED );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_CLK_LEVEL        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK_LEVEL );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_CLK_LEVEL_LEN    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK_LEVEL_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_FINE_STEPPING    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_FINE_STEPPING );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_DONE             , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DONE    );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK16     , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ERR_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK18     , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ERR_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK20     , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ERR_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_WL_ERR_CLK22     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ERR_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_2_23_ZERO_DETECTED    , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ZERO_DETECTED );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_CLK_LEVEL        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK_LEVEL );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_CLK_LEVEL_LEN    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CLK_LEVEL_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_FINE_STEPPING    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_FINE_STEPPING );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_DONE             , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DONE    );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK16     , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ERR_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK18     , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ERR_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK20     , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ERR_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_WL_ERR_CLK22     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_WL_ERR_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_3_23_ZERO_DETECTED    , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_ZERO_DETECTED );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_CLK_LEVEL         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK_LEVEL );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_CLK_LEVEL_LEN     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CLK_LEVEL_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_FINE_STEPPING     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_FINE_STEPPING );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_DONE              , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DONE     );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK16      , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_WL_ERR_CLK16 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK18      , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_WL_ERR_CLK18 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK20      , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_WL_ERR_CLK20 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_WL_ERR_CLK22      , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_WL_ERR_CLK22 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_LVL_STATUS0_P0_4_4_ZERO_DETECTED     , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_ZERO_DETECTED );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_1D_CHICKEN_SWITCH , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_1D_CHICKEN_SWITCH );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_RUN_FULL_1D , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_RUN_FULL_1D );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_SMALL_STEP_VAL , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_2D_SMALL_STEP_VAL );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_SMALL_STEP_VAL_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_2D_SMALL_STEP_VAL_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_BIG_STEP_VAL , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_2D_BIG_STEP_VAL );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_2D_BIG_STEP_VAL_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_2D_BIG_STEP_VAL_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_BITS_TO_SKIP , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_BITS_TO_SKIP );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_BITS_TO_SKIP_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_BITS_TO_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_NO_INC_COMP , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_NO_INC_COMP );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_0_01_CTR_NUM_NO_INC_COMP_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_NO_INC_COMP_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_1D_CHICKEN_SWITCH , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_1D_CHICKEN_SWITCH );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_RUN_FULL_1D , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_RUN_FULL_1D );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_2D_SMALL_STEP_VAL , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_2D_SMALL_STEP_VAL );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_2D_SMALL_STEP_VAL_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_2D_SMALL_STEP_VAL_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_2D_BIG_STEP_VAL , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_2D_BIG_STEP_VAL );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_2D_BIG_STEP_VAL_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_2D_BIG_STEP_VAL_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_BITS_TO_SKIP , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_BITS_TO_SKIP );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_BITS_TO_SKIP_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_BITS_TO_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_NO_INC_COMP , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_NO_INC_COMP );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_1_01_CTR_NUM_NO_INC_COMP_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_NO_INC_COMP_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_1D_CHICKEN_SWITCH , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_1D_CHICKEN_SWITCH );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_RUN_FULL_1D , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_RUN_FULL_1D );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_2D_SMALL_STEP_VAL , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_2D_SMALL_STEP_VAL );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_2D_SMALL_STEP_VAL_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_2D_SMALL_STEP_VAL_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_2D_BIG_STEP_VAL , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_2D_BIG_STEP_VAL );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_2D_BIG_STEP_VAL_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_2D_BIG_STEP_VAL_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_BITS_TO_SKIP , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_BITS_TO_SKIP );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_BITS_TO_SKIP_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_BITS_TO_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_NO_INC_COMP , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_NO_INC_COMP );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_2_23_CTR_NUM_NO_INC_COMP_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_NO_INC_COMP_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_1D_CHICKEN_SWITCH , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_1D_CHICKEN_SWITCH );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_RUN_FULL_1D , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_RUN_FULL_1D );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_2D_SMALL_STEP_VAL , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_2D_SMALL_STEP_VAL );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_2D_SMALL_STEP_VAL_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_2D_SMALL_STEP_VAL_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_2D_BIG_STEP_VAL , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_2D_BIG_STEP_VAL );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_2D_BIG_STEP_VAL_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_2D_BIG_STEP_VAL_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_BITS_TO_SKIP , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_BITS_TO_SKIP );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_BITS_TO_SKIP_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_BITS_TO_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_NO_INC_COMP , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_NO_INC_COMP );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_3_23_CTR_NUM_NO_INC_COMP_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_NO_INC_COMP_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_1D_CHICKEN_SWITCH , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_1D_CHICKEN_SWITCH );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_RUN_FULL_1D  , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_RUN_FULL_1D );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_2D_SMALL_STEP_VAL , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_2D_SMALL_STEP_VAL );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_2D_SMALL_STEP_VAL_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_2D_SMALL_STEP_VAL_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_2D_BIG_STEP_VAL , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_2D_BIG_STEP_VAL );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_2D_BIG_STEP_VAL_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_2D_BIG_STEP_VAL_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_BITS_TO_SKIP , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_NUM_BITS_TO_SKIP );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_BITS_TO_SKIP_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_NUM_BITS_TO_SKIP_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_NO_INC_COMP , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_NUM_NO_INC_COMP );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG0_P0_4_4_CTR_NUM_NO_INC_COMP_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_NUM_NO_INC_COMP_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_RANGE_SELECT , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_RANGE_SELECT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_RANGE_CROSSOVER , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_RANGE_CROSSOVER );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_RANGE_CROSSOVER_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_RANGE_CROSSOVER_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_SINGLE_RANGE_MAX , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_SINGLE_RANGE_MAX );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_0_01_CTR_SINGLE_RANGE_MAX_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_SINGLE_RANGE_MAX_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_RANGE_SELECT , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_RANGE_SELECT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_RANGE_CROSSOVER , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_RANGE_CROSSOVER );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_RANGE_CROSSOVER_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_RANGE_CROSSOVER_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_SINGLE_RANGE_MAX , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_SINGLE_RANGE_MAX );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_1_01_CTR_SINGLE_RANGE_MAX_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_SINGLE_RANGE_MAX_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_RANGE_SELECT , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_RANGE_SELECT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_RANGE_CROSSOVER , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_RANGE_CROSSOVER );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_RANGE_CROSSOVER_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_RANGE_CROSSOVER_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_SINGLE_RANGE_MAX , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_SINGLE_RANGE_MAX );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_2_23_CTR_SINGLE_RANGE_MAX_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_SINGLE_RANGE_MAX_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_RANGE_SELECT , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_RANGE_SELECT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_RANGE_CROSSOVER , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_RANGE_CROSSOVER );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_RANGE_CROSSOVER_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_RANGE_CROSSOVER_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_SINGLE_RANGE_MAX , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_SINGLE_RANGE_MAX );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_3_23_CTR_SINGLE_RANGE_MAX_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_SINGLE_RANGE_MAX_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_RANGE_SELECT , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_RANGE_SELECT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_RANGE_CROSSOVER , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_RANGE_CROSSOVER );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_RANGE_CROSSOVER_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_RANGE_CROSSOVER_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_SINGLE_RANGE_MAX , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_SINGLE_RANGE_MAX );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_CONFIG1_P0_4_4_CTR_SINGLE_RANGE_MAX_LEN , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_SINGLE_RANGE_MAX_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MAX_RANGE_ERR0   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MAX_RANGE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MIN_RANGE_ERR0   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MIN_RANGE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_TWO_RANGE_BEST_CASE_ERR0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_TWO_RANGE_BEST_CASE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BIT_STEP_DELTA_ERR0 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BIT_STEP_DELTA_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_STEP_RANGE_EDGE_ERR0 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_STEP_RANGE_EDGE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_NO_INCREASE_ERR0 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_NO_INCREASE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_1D_EYE_NOISE_ERR0 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_1D_EYE_NOISE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BAD_BIT_ERR0     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BAD_BIT_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MAX_RANGE_ERR1   , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MAX_RANGE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_MIN_RANGE_ERR1   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MIN_RANGE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_TWO_RANGE_BEST_CASE_ERR1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_TWO_RANGE_BEST_CASE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BIT_STEP_DELTA_ERR1 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BIT_STEP_DELTA_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_STEP_RANGE_EDGE_ERR1 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_STEP_RANGE_EDGE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_NO_INCREASE_ERR1 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_NO_INCREASE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_1D_EYE_NOISE_ERR1 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_1D_EYE_NOISE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_0_01_BAD_BIT_ERR1     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BAD_BIT_ERR1 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MAX_RANGE_ERR0   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MAX_RANGE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MIN_RANGE_ERR0   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MIN_RANGE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_TWO_RANGE_BEST_CASE_ERR0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_TWO_RANGE_BEST_CASE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BIT_STEP_DELTA_ERR0 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BIT_STEP_DELTA_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_STEP_RANGE_EDGE_ERR0 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_STEP_RANGE_EDGE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_NO_INCREASE_ERR0 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_NO_INCREASE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_1D_EYE_NOISE_ERR0 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_1D_EYE_NOISE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BAD_BIT_ERR0     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BAD_BIT_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MAX_RANGE_ERR1   , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MAX_RANGE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_MIN_RANGE_ERR1   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MIN_RANGE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_TWO_RANGE_BEST_CASE_ERR1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_TWO_RANGE_BEST_CASE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BIT_STEP_DELTA_ERR1 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BIT_STEP_DELTA_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_STEP_RANGE_EDGE_ERR1 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_STEP_RANGE_EDGE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_NO_INCREASE_ERR1 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_NO_INCREASE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_1D_EYE_NOISE_ERR1 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_1D_EYE_NOISE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_1_01_BAD_BIT_ERR1     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BAD_BIT_ERR1 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MAX_RANGE_ERR0   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MAX_RANGE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MIN_RANGE_ERR0   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MIN_RANGE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_TWO_RANGE_BEST_CASE_ERR0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_TWO_RANGE_BEST_CASE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BIT_STEP_DELTA_ERR0 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BIT_STEP_DELTA_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_STEP_RANGE_EDGE_ERR0 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_STEP_RANGE_EDGE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_NO_INCREASE_ERR0 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_NO_INCREASE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_1D_EYE_NOISE_ERR0 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_1D_EYE_NOISE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BAD_BIT_ERR0     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BAD_BIT_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MAX_RANGE_ERR1   , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MAX_RANGE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_MIN_RANGE_ERR1   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MIN_RANGE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_TWO_RANGE_BEST_CASE_ERR1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_TWO_RANGE_BEST_CASE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BIT_STEP_DELTA_ERR1 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BIT_STEP_DELTA_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_STEP_RANGE_EDGE_ERR1 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_STEP_RANGE_EDGE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_NO_INCREASE_ERR1 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_NO_INCREASE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_1D_EYE_NOISE_ERR1 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_1D_EYE_NOISE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_2_23_BAD_BIT_ERR1     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BAD_BIT_ERR1 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MAX_RANGE_ERR0   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MAX_RANGE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MIN_RANGE_ERR0   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MIN_RANGE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_TWO_RANGE_BEST_CASE_ERR0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_TWO_RANGE_BEST_CASE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BIT_STEP_DELTA_ERR0 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BIT_STEP_DELTA_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_STEP_RANGE_EDGE_ERR0 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_STEP_RANGE_EDGE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_NO_INCREASE_ERR0 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_NO_INCREASE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_1D_EYE_NOISE_ERR0 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_1D_EYE_NOISE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BAD_BIT_ERR0     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BAD_BIT_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MAX_RANGE_ERR1   , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MAX_RANGE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_MIN_RANGE_ERR1   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MIN_RANGE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_TWO_RANGE_BEST_CASE_ERR1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_TWO_RANGE_BEST_CASE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BIT_STEP_DELTA_ERR1 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BIT_STEP_DELTA_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_STEP_RANGE_EDGE_ERR1 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_STEP_RANGE_EDGE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_NO_INCREASE_ERR1 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_NO_INCREASE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_1D_EYE_NOISE_ERR1 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_1D_EYE_NOISE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_3_23_BAD_BIT_ERR1     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BAD_BIT_ERR1 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MAX_RANGE_ERR0    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_MAX_RANGE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MIN_RANGE_ERR0    , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_MIN_RANGE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_TWO_RANGE_BEST_CASE_ERR0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_TWO_RANGE_BEST_CASE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BIT_STEP_DELTA_ERR0 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_BIT_STEP_DELTA_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_STEP_RANGE_EDGE_ERR0 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_STEP_RANGE_EDGE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_NO_INCREASE_ERR0  , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_NO_INCREASE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_1D_EYE_NOISE_ERR0 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_1D_EYE_NOISE_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BAD_BIT_ERR0      , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_BAD_BIT_ERR0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MAX_RANGE_ERR1    , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_MAX_RANGE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_MIN_RANGE_ERR1    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_MIN_RANGE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_TWO_RANGE_BEST_CASE_ERR1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_TWO_RANGE_BEST_CASE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BIT_STEP_DELTA_ERR1 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_BIT_STEP_DELTA_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_STEP_RANGE_EDGE_ERR1 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_STEP_RANGE_EDGE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_NO_INCREASE_ERR1  , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_NO_INCREASE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_1D_EYE_NOISE_ERR1 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_1D_EYE_NOISE_ERR1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR0_P0_4_4_BAD_BIT_ERR1      , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_BAD_BIT_ERR1 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MAX_RANGE_ERR2   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MAX_RANGE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MIN_RANGE_ERR2   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MIN_RANGE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_TWO_RANGE_BEST_CASE_ERR2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_TWO_RANGE_BEST_CASE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BIT_STEP_DELTA_ERR2 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BIT_STEP_DELTA_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_STEP_RANGE_EDGE_ERR2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_STEP_RANGE_EDGE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_NO_INCREASE_ERR2 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_NO_INCREASE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_1D_EYE_NOISE_ERR2 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_1D_EYE_NOISE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BAD_BIT_ERR2     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BAD_BIT_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MAX_RANGE_ERR3   , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MAX_RANGE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_MIN_RANGE_ERR3   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MIN_RANGE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_TWO_RANGE_BEST_CASE_ERR3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_TWO_RANGE_BEST_CASE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BIT_STEP_DELTA_ERR3 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BIT_STEP_DELTA_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_STEP_RANGE_EDGE_ERR3 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_STEP_RANGE_EDGE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_NO_INCREASE_ERR3 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_NO_INCREASE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_1D_EYE_NOISE_ERR3 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_1D_EYE_NOISE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_0_01_BAD_BIT_ERR3     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BAD_BIT_ERR3 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MAX_RANGE_ERR2   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MAX_RANGE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MIN_RANGE_ERR2   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MIN_RANGE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_TWO_RANGE_BEST_CASE_ERR2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_TWO_RANGE_BEST_CASE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BIT_STEP_DELTA_ERR2 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BIT_STEP_DELTA_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_STEP_RANGE_EDGE_ERR2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_STEP_RANGE_EDGE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_NO_INCREASE_ERR2 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_NO_INCREASE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_1D_EYE_NOISE_ERR2 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_1D_EYE_NOISE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BAD_BIT_ERR2     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BAD_BIT_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MAX_RANGE_ERR3   , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MAX_RANGE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_MIN_RANGE_ERR3   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_MIN_RANGE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_TWO_RANGE_BEST_CASE_ERR3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_TWO_RANGE_BEST_CASE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BIT_STEP_DELTA_ERR3 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BIT_STEP_DELTA_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_STEP_RANGE_EDGE_ERR3 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_STEP_RANGE_EDGE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_NO_INCREASE_ERR3 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_NO_INCREASE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_1D_EYE_NOISE_ERR3 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_1D_EYE_NOISE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_1_01_BAD_BIT_ERR3     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_01_BAD_BIT_ERR3 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MAX_RANGE_ERR2   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MAX_RANGE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MIN_RANGE_ERR2   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MIN_RANGE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_TWO_RANGE_BEST_CASE_ERR2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_TWO_RANGE_BEST_CASE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BIT_STEP_DELTA_ERR2 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BIT_STEP_DELTA_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_STEP_RANGE_EDGE_ERR2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_STEP_RANGE_EDGE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_NO_INCREASE_ERR2 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_NO_INCREASE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_1D_EYE_NOISE_ERR2 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_1D_EYE_NOISE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BAD_BIT_ERR2     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BAD_BIT_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MAX_RANGE_ERR3   , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MAX_RANGE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_MIN_RANGE_ERR3   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MIN_RANGE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_TWO_RANGE_BEST_CASE_ERR3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_TWO_RANGE_BEST_CASE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BIT_STEP_DELTA_ERR3 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BIT_STEP_DELTA_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_STEP_RANGE_EDGE_ERR3 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_STEP_RANGE_EDGE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_NO_INCREASE_ERR3 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_NO_INCREASE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_1D_EYE_NOISE_ERR3 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_1D_EYE_NOISE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_2_23_BAD_BIT_ERR3     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BAD_BIT_ERR3 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MAX_RANGE_ERR2   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MAX_RANGE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MIN_RANGE_ERR2   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MIN_RANGE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_TWO_RANGE_BEST_CASE_ERR2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_TWO_RANGE_BEST_CASE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BIT_STEP_DELTA_ERR2 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BIT_STEP_DELTA_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_STEP_RANGE_EDGE_ERR2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_STEP_RANGE_EDGE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_NO_INCREASE_ERR2 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_NO_INCREASE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_1D_EYE_NOISE_ERR2 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_1D_EYE_NOISE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BAD_BIT_ERR2     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BAD_BIT_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MAX_RANGE_ERR3   , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MAX_RANGE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_MIN_RANGE_ERR3   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_MIN_RANGE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_TWO_RANGE_BEST_CASE_ERR3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_TWO_RANGE_BEST_CASE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BIT_STEP_DELTA_ERR3 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BIT_STEP_DELTA_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_STEP_RANGE_EDGE_ERR3 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_STEP_RANGE_EDGE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_NO_INCREASE_ERR3 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_NO_INCREASE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_1D_EYE_NOISE_ERR3 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_1D_EYE_NOISE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_3_23_BAD_BIT_ERR3     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_23_BAD_BIT_ERR3 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MAX_RANGE_ERR2    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_MAX_RANGE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MIN_RANGE_ERR2    , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_MIN_RANGE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_TWO_RANGE_BEST_CASE_ERR2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_TWO_RANGE_BEST_CASE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BIT_STEP_DELTA_ERR2 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_BIT_STEP_DELTA_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_STEP_RANGE_EDGE_ERR2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_STEP_RANGE_EDGE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_NO_INCREASE_ERR2  , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_NO_INCREASE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_1D_EYE_NOISE_ERR2 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_1D_EYE_NOISE_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BAD_BIT_ERR2      , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_BAD_BIT_ERR2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MAX_RANGE_ERR3    , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_MAX_RANGE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_MIN_RANGE_ERR3    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_MIN_RANGE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_TWO_RANGE_BEST_CASE_ERR3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_TWO_RANGE_BEST_CASE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BIT_STEP_DELTA_ERR3 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_BIT_STEP_DELTA_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_STEP_RANGE_EDGE_ERR3 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_STEP_RANGE_EDGE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_NO_INCREASE_ERR3  , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_NO_INCREASE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_1D_EYE_NOISE_ERR3 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_1D_EYE_NOISE_ERR3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR1_P0_4_4_BAD_BIT_ERR3      , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_4_BAD_BIT_ERR3 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MAX_RANGE   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MAX_RANGE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MIN_RANGE   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_RANGE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_TWO_RANGE_BEST_CASE , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_TWO_RANGE_BEST_CASE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BIT_STEP_DELTA , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BIT_STEP_DELTA );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_STEP_RANGE_EDGE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_STEP_RANGE_EDGE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_NO_INCREASE , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_INCREASE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_1D_EYE_NOISE , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_1D_EYE_NOISE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BAD_BIT     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BAD_BIT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MAX_RANGE_MASK1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MAX_RANGE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_MIN_RANGE_MASK1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_RANGE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_TWO_RANGE_BEST_CASE_MASK1 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_TWO_RANGE_BEST_CASE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BIT_STEP_DELTA_MASK1 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BIT_STEP_DELTA_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_STEP_RANGE_EDGE_MASK1 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_STEP_RANGE_EDGE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_NO_INCREASE_MASK1 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_INCREASE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_1D_EYE_NOISE_MASK1 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_1D_EYE_NOISE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_0_01_BAD_BIT_MASK1 , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BAD_BIT_MASK1 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MAX_RANGE   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MAX_RANGE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MIN_RANGE   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_RANGE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_TWO_RANGE_BEST_CASE , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_TWO_RANGE_BEST_CASE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BIT_STEP_DELTA , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BIT_STEP_DELTA );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_STEP_RANGE_EDGE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_STEP_RANGE_EDGE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_NO_INCREASE , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_INCREASE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_1D_EYE_NOISE , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_1D_EYE_NOISE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BAD_BIT     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BAD_BIT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MAX_RANGE_MASK1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MAX_RANGE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_MIN_RANGE_MASK1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_RANGE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_TWO_RANGE_BEST_CASE_MASK1 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_TWO_RANGE_BEST_CASE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BIT_STEP_DELTA_MASK1 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BIT_STEP_DELTA_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_STEP_RANGE_EDGE_MASK1 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_STEP_RANGE_EDGE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_NO_INCREASE_MASK1 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_INCREASE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_1D_EYE_NOISE_MASK1 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_1D_EYE_NOISE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_1_01_BAD_BIT_MASK1 , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BAD_BIT_MASK1 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MAX_RANGE   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MAX_RANGE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MIN_RANGE   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_RANGE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_TWO_RANGE_BEST_CASE , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_TWO_RANGE_BEST_CASE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BIT_STEP_DELTA , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BIT_STEP_DELTA );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_STEP_RANGE_EDGE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_STEP_RANGE_EDGE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_NO_INCREASE , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_INCREASE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_1D_EYE_NOISE , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_1D_EYE_NOISE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BAD_BIT     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BAD_BIT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MAX_RANGE_MASK1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MAX_RANGE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_MIN_RANGE_MASK1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_RANGE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_TWO_RANGE_BEST_CASE_MASK1 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_TWO_RANGE_BEST_CASE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BIT_STEP_DELTA_MASK1 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BIT_STEP_DELTA_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_STEP_RANGE_EDGE_MASK1 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_STEP_RANGE_EDGE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_NO_INCREASE_MASK1 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_INCREASE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_1D_EYE_NOISE_MASK1 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_1D_EYE_NOISE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_2_23_BAD_BIT_MASK1 , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BAD_BIT_MASK1 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MAX_RANGE   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MAX_RANGE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MIN_RANGE   , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_RANGE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_TWO_RANGE_BEST_CASE , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_TWO_RANGE_BEST_CASE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BIT_STEP_DELTA , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BIT_STEP_DELTA );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_STEP_RANGE_EDGE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_STEP_RANGE_EDGE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_NO_INCREASE , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_INCREASE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_1D_EYE_NOISE , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_1D_EYE_NOISE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BAD_BIT     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BAD_BIT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MAX_RANGE_MASK1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MAX_RANGE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_MIN_RANGE_MASK1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_RANGE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_TWO_RANGE_BEST_CASE_MASK1 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_TWO_RANGE_BEST_CASE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BIT_STEP_DELTA_MASK1 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BIT_STEP_DELTA_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_STEP_RANGE_EDGE_MASK1 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_STEP_RANGE_EDGE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_NO_INCREASE_MASK1 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_INCREASE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_1D_EYE_NOISE_MASK1 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_1D_EYE_NOISE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_3_23_BAD_BIT_MASK1 , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BAD_BIT_MASK1 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MAX_RANGE    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MAX_RANGE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MIN_RANGE    , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MIN_RANGE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_TWO_RANGE_BEST_CASE , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_TWO_RANGE_BEST_CASE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BIT_STEP_DELTA , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_BIT_STEP_DELTA );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_STEP_RANGE_EDGE , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_STEP_RANGE_EDGE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_NO_INCREASE  , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NO_INCREASE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_1D_EYE_NOISE , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_1D_EYE_NOISE );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BAD_BIT      , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_BAD_BIT  );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MAX_RANGE_MASK1 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MAX_RANGE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_MIN_RANGE_MASK1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MIN_RANGE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_TWO_RANGE_BEST_CASE_MASK1 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_TWO_RANGE_BEST_CASE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BIT_STEP_DELTA_MASK1 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_BIT_STEP_DELTA_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_STEP_RANGE_EDGE_MASK1 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_STEP_RANGE_EDGE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_NO_INCREASE_MASK1 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NO_INCREASE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_1D_EYE_NOISE_MASK1 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_1D_EYE_NOISE_MASK1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK0_P0_4_4_BAD_BIT_MASK1 , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_BAD_BIT_MASK1 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MAX_RANGE_MASK2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MAX_RANGE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MIN_RANGE_MASK2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_RANGE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_TWO_RANGE_BEST_CASE_MASK2 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_TWO_RANGE_BEST_CASE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BIT_STEP_DELTA_MASK2 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BIT_STEP_DELTA_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_STEP_RANGE_EDGE_MASK2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_STEP_RANGE_EDGE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_NO_INCREASE_MASK2 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_INCREASE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_1D_EYE_NOISE_MASK2 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_1D_EYE_NOISE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BAD_BIT_MASK2 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BAD_BIT_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MAX_RANGE_MASK3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MAX_RANGE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_MIN_RANGE_MASK3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_RANGE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_TWO_RANGE_BEST_CASE_MASK3 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_TWO_RANGE_BEST_CASE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BIT_STEP_DELTA_MASK3 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BIT_STEP_DELTA_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_STEP_RANGE_EDGE_MASK3 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_STEP_RANGE_EDGE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_NO_INCREASE_MASK3 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_INCREASE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_1D_EYE_NOISE_MASK3 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_1D_EYE_NOISE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_0_01_BAD_BIT_MASK3 , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BAD_BIT_MASK3 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MAX_RANGE_MASK2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MAX_RANGE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MIN_RANGE_MASK2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_RANGE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_TWO_RANGE_BEST_CASE_MASK2 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_TWO_RANGE_BEST_CASE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BIT_STEP_DELTA_MASK2 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BIT_STEP_DELTA_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_STEP_RANGE_EDGE_MASK2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_STEP_RANGE_EDGE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_NO_INCREASE_MASK2 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_INCREASE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_1D_EYE_NOISE_MASK2 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_1D_EYE_NOISE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BAD_BIT_MASK2 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BAD_BIT_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MAX_RANGE_MASK3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MAX_RANGE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_MIN_RANGE_MASK3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_MIN_RANGE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_TWO_RANGE_BEST_CASE_MASK3 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_01_TWO_RANGE_BEST_CASE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BIT_STEP_DELTA_MASK3 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BIT_STEP_DELTA_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_STEP_RANGE_EDGE_MASK3 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_STEP_RANGE_EDGE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_NO_INCREASE_MASK3 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_NO_INCREASE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_1D_EYE_NOISE_MASK3 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_1D_EYE_NOISE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_1_01_BAD_BIT_MASK3 , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_BAD_BIT_MASK3 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MAX_RANGE_MASK2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MAX_RANGE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MIN_RANGE_MASK2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_RANGE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_TWO_RANGE_BEST_CASE_MASK2 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_TWO_RANGE_BEST_CASE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BIT_STEP_DELTA_MASK2 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BIT_STEP_DELTA_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_STEP_RANGE_EDGE_MASK2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_STEP_RANGE_EDGE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_NO_INCREASE_MASK2 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_INCREASE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_1D_EYE_NOISE_MASK2 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_1D_EYE_NOISE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BAD_BIT_MASK2 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BAD_BIT_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MAX_RANGE_MASK3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MAX_RANGE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_MIN_RANGE_MASK3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_RANGE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_TWO_RANGE_BEST_CASE_MASK3 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_TWO_RANGE_BEST_CASE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BIT_STEP_DELTA_MASK3 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BIT_STEP_DELTA_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_STEP_RANGE_EDGE_MASK3 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_STEP_RANGE_EDGE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_NO_INCREASE_MASK3 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_INCREASE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_1D_EYE_NOISE_MASK3 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_1D_EYE_NOISE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_2_23_BAD_BIT_MASK3 , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BAD_BIT_MASK3 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MAX_RANGE_MASK2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MAX_RANGE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MIN_RANGE_MASK2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_RANGE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_TWO_RANGE_BEST_CASE_MASK2 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_TWO_RANGE_BEST_CASE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BIT_STEP_DELTA_MASK2 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BIT_STEP_DELTA_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_STEP_RANGE_EDGE_MASK2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_STEP_RANGE_EDGE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_NO_INCREASE_MASK2 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_INCREASE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_1D_EYE_NOISE_MASK2 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_1D_EYE_NOISE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BAD_BIT_MASK2 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BAD_BIT_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MAX_RANGE_MASK3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MAX_RANGE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_MIN_RANGE_MASK3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_MIN_RANGE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_TWO_RANGE_BEST_CASE_MASK3 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_23_TWO_RANGE_BEST_CASE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BIT_STEP_DELTA_MASK3 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BIT_STEP_DELTA_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_STEP_RANGE_EDGE_MASK3 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_STEP_RANGE_EDGE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_NO_INCREASE_MASK3 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_NO_INCREASE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_1D_EYE_NOISE_MASK3 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_1D_EYE_NOISE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_3_23_BAD_BIT_MASK3 , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_BAD_BIT_MASK3 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MAX_RANGE_MASK2 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MAX_RANGE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MIN_RANGE_MASK2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MIN_RANGE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_TWO_RANGE_BEST_CASE_MASK2 , 50  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_TWO_RANGE_BEST_CASE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BIT_STEP_DELTA_MASK2 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_BIT_STEP_DELTA_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_STEP_RANGE_EDGE_MASK2 , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_STEP_RANGE_EDGE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_NO_INCREASE_MASK2 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NO_INCREASE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_1D_EYE_NOISE_MASK2 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_1D_EYE_NOISE_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BAD_BIT_MASK2 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_BAD_BIT_MASK2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MAX_RANGE_MASK3 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MAX_RANGE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_MIN_RANGE_MASK3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_MIN_RANGE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_TWO_RANGE_BEST_CASE_MASK3 , 58  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_4_TWO_RANGE_BEST_CASE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BIT_STEP_DELTA_MASK3 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_BIT_STEP_DELTA_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_STEP_RANGE_EDGE_MASK3 , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_STEP_RANGE_EDGE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_NO_INCREASE_MASK3 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_NO_INCREASE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_1D_EYE_NOISE_MASK3 , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_1D_EYE_NOISE_MASK3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_ERROR_MASK1_P0_4_4_BAD_BIT_MASK3 , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_BAD_BIT_MASK3 );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0_01_CTR_NUM_WRRDREQ_CNT , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_WRRDREQ_CNT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_0_01_CTR_NUM_WRRDREQ_CNT_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_WRRDREQ_CNT_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_1_01_CTR_NUM_WRRDREQ_CNT , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_WRRDREQ_CNT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_1_01_CTR_NUM_WRRDREQ_CNT_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_WRRDREQ_CNT_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_2_23_CTR_NUM_WRRDREQ_CNT , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_WRRDREQ_CNT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_2_23_CTR_NUM_WRRDREQ_CNT_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_WRRDREQ_CNT_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_3_23_CTR_NUM_WRRDREQ_CNT , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_WRRDREQ_CNT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_3_23_CTR_NUM_WRRDREQ_CNT_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_WRRDREQ_CNT_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_4_4_CTR_NUM_WRRDREQ_CNT , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_NUM_WRRDREQ_CNT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS0_P0_4_4_CTR_NUM_WRRDREQ_CNT_LEN , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_NUM_WRRDREQ_CNT_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_NUM_VREFREQ_CNT , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_VREFREQ_CNT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_NUM_VREFREQ_CNT_LEN , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_VREFREQ_CNT_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_CUR         , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_CUR );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_0_01_CTR_CUR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_CUR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_NUM_VREFREQ_CNT , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_VREFREQ_CNT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_NUM_VREFREQ_CNT_LEN , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_NUM_VREFREQ_CNT_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_CUR         , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_CUR );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_1_01_CTR_CUR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_CTR_CUR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_NUM_VREFREQ_CNT , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_VREFREQ_CNT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_NUM_VREFREQ_CNT_LEN , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_VREFREQ_CNT_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_CUR         , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_CUR );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_2_23_CTR_CUR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_CUR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_NUM_VREFREQ_CNT , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_VREFREQ_CNT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_NUM_VREFREQ_CNT_LEN , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_NUM_VREFREQ_CNT_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_CUR         , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_CUR );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_3_23_CTR_CUR_LEN     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_CTR_CUR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_NUM_VREFREQ_CNT , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_NUM_VREFREQ_CNT );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_NUM_VREFREQ_CNT_LEN , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_NUM_VREFREQ_CNT_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_CUR          , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_CUR  );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_STATUS1_P0_4_4_CTR_CUR_LEN      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_CTR_CUR_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_0_01_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_1_01_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_2_23_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_3_23_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR0_P0_4_4_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_0_01_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_1_01_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_2_23_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_3_23_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR1_P0_4_4_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_0_01_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_1_01_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_2_23_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_3_23_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR2_P0_4_4_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_0_01_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_1_01_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_2_23_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_3_23_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_RANGE_DRAM0 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM0 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM0 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM0_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM0_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_RANGE_DRAM1 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM1 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM1 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE0_RANK_PAIR3_P0_4_4_VALUE_DRAM1_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM1_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_0_01_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_1_01_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_2_23_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_3_23_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR0_P0_4_4_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_0_01_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_1_01_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_2_23_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_3_23_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR1_P0_4_4_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_0_01_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_1_01_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_2_23_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_3_23_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR2_P0_4_4_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_0_01_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_1_01_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_2_23_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_3_23_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_RANGE_DRAM2 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM2 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM2 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM2_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM2_LEN );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_RANGE_DRAM3 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_RANGE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM3 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM3 );
+REG64_FLD( MCA_DDRPHY_DP16_WR_VREF_VALUE1_RANK_PAIR3_P0_4_4_VALUE_DRAM3_LEN , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_VALUE_DRAM3_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_BASE_CNTR0_P0_PERIODIC                    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PERIODIC   );
+REG64_FLD( MCA_DDRPHY_PC_BASE_CNTR0_P0_PERIODIC_LEN                , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PERIODIC_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_BASE_CNTR1_P0_PERIODIC                    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PERIODIC   );
+REG64_FLD( MCA_DDRPHY_PC_BASE_CNTR1_P0_PERIODIC_LEN                , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PERIODIC_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_CAL_TIMER_P0_PERIODIC                     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PERIODIC   );
+REG64_FLD( MCA_DDRPHY_PC_CAL_TIMER_P0_PERIODIC_LEN                 , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PERIODIC_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0_PERIODIC        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERIODIC   );
+REG64_FLD( MCA_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0_PERIODIC_LEN    , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERIODIC_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_PROTOCOL                       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PROTOCOL   );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_PROTOCOL_LEN                   , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PROTOCOL_LEN );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_DATA_MUX4_1MODE                , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_MUX4_1MODE );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_DDR4_CMD_SIG_REDUCTION         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR4_CMD_SIG_REDUCTION );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_SYSCLK_2X_MEMINTCLKO           , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYSCLK_2X_MEMINTCLKO );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE                  , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RANK_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE_VALUE            , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RANK_OVERRIDE_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_RANK_OVERRIDE_VALUE_LEN        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RANK_OVERRIDE_VALUE_LEN );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_LOW_LATENCY                    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOW_LATENCY );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_DDR4_IPW_LOOP_DIS              , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR4_IPW_LOOP_DIS );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_DDR4_VLEVEL_BANK_GROUP         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR4_VLEVEL_BANK_GROUP );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG0_P0_VPROTH_PSEL_MODE               , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPROTH_PSEL_MODE );
+
+REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET           , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRITE_LATENCY_OFFSET );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET_LEN       , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRITE_LATENCY_OFFSET_LEN );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_READ_LATENCY_OFFSET            , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_LATENCY_OFFSET );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_READ_LATENCY_OFFSET_LEN        , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_LATENCY_OFFSET_LEN );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_MEMCTL_CIC_FAST                , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEMCTL_CIC_FAST );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_MEMCTL_CTRN_IGNORE             , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEMCTL_CTRN_IGNORE );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_DISABLE_MEMCTL_CAL             , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_MEMCTL_CAL );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE                    , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEMORY_TYPE );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_MEMORY_TYPE_LEN                , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEMORY_TYPE_LEN );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_DDR4_LATENCY_SW                , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR4_LATENCY_SW );
+REG64_FLD( MCA_DDRPHY_PC_CONFIG1_P0_RETRAIN_PERCAL_SW              , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RETRAIN_PERCAL_SW );
+
+REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS0_INIT_CAL_VALUE            , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CS0_INIT_CAL_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS1_INIT_CAL_VALUE            , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CS1_INIT_CAL_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS2_INIT_CAL_VALUE            , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CS2_INIT_CAL_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS3_INIT_CAL_VALUE            , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CS3_INIT_CAL_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS4_INIT_CAL_VALUE            , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CS4_INIT_CAL_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS5_INIT_CAL_VALUE            , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CS5_INIT_CAL_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS6_INIT_CAL_VALUE            , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CS6_INIT_CAL_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_CSID_CFG_P0_CS7_INIT_CAL_VALUE            , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CS7_INIT_CAL_VALUE );
+
+REG64_FLD( MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_DP_GOOD            , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DP_GOOD    );
+REG64_FLD( MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_DP_ERROR           , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DP_ERROR   );
+REG64_FLD( MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_DP_ERROR_FINE      , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DP_ERROR_FINE );
+REG64_FLD( MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_ADR_GOOD           , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADR_GOOD   );
+REG64_FLD( MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_ADR_ERROR          , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADR_ERROR  );
+REG64_FLD( MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_ADR_ERROR_FINE     , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADR_ERROR_FINE );
+REG64_FLD( MCA_DDRPHY_PC_DLL_ZCAL_CAL_STATUS_P0_DONE               , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DONE       );
+
+REG64_FLD( MCA_DDRPHY_PC_ERROR_MASK0_P0_RC_MASK                    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RC_MASK    );
+REG64_FLD( MCA_DDRPHY_PC_ERROR_MASK0_P0_WC_MASK                    , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WC_MASK    );
+REG64_FLD( MCA_DDRPHY_PC_ERROR_MASK0_P0_SEQ_MASK                   , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEQ_MASK   );
+REG64_FLD( MCA_DDRPHY_PC_ERROR_MASK0_P0_CC_MASK                    , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CC_MASK    );
+REG64_FLD( MCA_DDRPHY_PC_ERROR_MASK0_P0_APB_MASK                   , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_APB_MASK   );
+REG64_FLD( MCA_DDRPHY_PC_ERROR_MASK0_P0_MASK                       , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MASK       );
+
+REG64_FLD( MCA_DDRPHY_PC_ERROR_STATUS0_P0_RC                       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RC         );
+REG64_FLD( MCA_DDRPHY_PC_ERROR_STATUS0_P0_WC                       , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WC         );
+REG64_FLD( MCA_DDRPHY_PC_ERROR_STATUS0_P0_SEQ                      , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_SEQ        );
+REG64_FLD( MCA_DDRPHY_PC_ERROR_STATUS0_P0_CC                       , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CC         );
+REG64_FLD( MCA_DDRPHY_PC_ERROR_STATUS0_P0_APB                      , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_APB        );
+REG64_FLD( MCA_DDRPHY_PC_ERROR_STATUS0_P0_ERROR                    , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR      );
+
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_WR_LEVEL          , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_WR_LEVEL );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_INITIAL_PAT_WR    , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_INITIAL_PAT_WR );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_DQS_ALIGN         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_DQS_ALIGN );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RDCLK_ALIGN       , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_RDCLK_ALIGN );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_READ_CTR          , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_READ_CTR );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_WRITE_CTR         , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_WRITE_CTR );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_INITIAL_COARSE_WR , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_INITIAL_COARSE_WR );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_COARSE_RD         , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_COARSE_RD );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_CUSTOM_RD         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_CUSTOM_RD );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_CUSTOM_WR         , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_CUSTOM_WR );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ABORT_ON_ERROR        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ABORT_ON_ERROR );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_DIGITAL_EYE       , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_DIGITAL_EYE );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RANK_PAIR         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_RANK_PAIR );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0_ENA_RANK_PAIR_LEN     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_RANK_PAIR_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_COUNT         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REFRESH_COUNT );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_COUNT_LEN     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REFRESH_COUNT_LEN );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_CONTROL       , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REFRESH_CONTROL );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_CONTROL_LEN   , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REFRESH_CONTROL_LEN );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_ALL_RANKS     , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REFRESH_ALL_RANKS );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_SNOOP_DIS             , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SNOOP_DIS  );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_INTERVAL      , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REFRESH_INTERVAL );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_CONFIG1_P0_REFRESH_INTERVAL_LEN  , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REFRESH_INTERVAL_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_WR_LEVEL                , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_LEVEL   );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_INITIAL_PAT_WRITE       , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_INITIAL_PAT_WRITE );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_DQS_ALIGN               , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DQS_ALIGN  );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_RDCLK_ALIGN             , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RDCLK_ALIGN );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_READ_CTR                , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_READ_CTR   );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_WRITE_CTR               , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_CTR  );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_INITIAL_COARSE_WR       , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_INITIAL_COARSE_WR );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_COARSE_RD               , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_COARSE_RD  );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_CUSTOM_RD               , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CUSTOM_RD  );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_CUSTOM_WR               , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CUSTOM_WR  );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_DIGITAL_EYE             , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DIGITAL_EYE );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_VREF                    , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_VREF       );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_RANK_PAIR               , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RANK_PAIR  );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_ERROR_P0_RANK_PAIR_LEN           , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RANK_PAIR_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_WR_LEVEL           , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_WR_LEVEL );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_INITIAL_PAT_WRITE  , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_INITIAL_PAT_WRITE );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_DQS_ALIGN          , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_DQS_ALIGN );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_RDCLK_ALIGN        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_RDCLK_ALIGN );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_READ_CTR           , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_READ_CTR );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_WRITE_CTR          , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_WRITE_CTR );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_INITIAL_COARSE_WR  , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_INITIAL_COARSE_WR );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_COARSE_RD          , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_COARSE_RD );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_CUSTOM_RD          , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CUSTOM_RD );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_CUSTOM_WR          , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CUSTOM_WR );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_DIGITAL_EYE        , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_DIGITAL_EYE );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_MASK_P0_ERROR_VREF               , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_VREF );
+
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_COMPLETE               , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_COMPLETE   );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_COMPLETE_LEN           , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_COMPLETE_LEN );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_RESERVED_52_56         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_52_56 );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_RESERVED_52_56_LEN     , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_52_56_LEN );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_PER_ABORT              , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PER_ABORT  );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_RESERVED_58_63         , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_58_63 );
+REG64_FLD( MCA_DDRPHY_PC_INIT_CAL_STATUS_P0_RESERVED_58_63_LEN     , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_58_63_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTPB               , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PVTPB      );
+REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTPL               , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PVTPL      );
+REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTPL_LEN           , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PVTPL_LEN  );
+REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTNB               , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PVTNB      );
+REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTN                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PVTN       );
+REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_PVTN_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PVTN_LEN   );
+
+REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTPB                , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PVTPB      );
+REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTPL                , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PVTPL      );
+REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTPL_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PVTPL_LEN  );
+REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTNB                , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PVTNB      );
+REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTNL                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PVTNL      );
+REG64_FLD( MCA_DDRPHY_PC_IO_PVT_FET_STATUS_P0_PVTNL_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PVTNL_LEN  );
+
+REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP0_P0_MODE_REGISTER_0_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP0_P0_MODE_REGISTER_0_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP1_P0_MODE_REGISTER_0_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP1_P0_MODE_REGISTER_0_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP2_P0_MODE_REGISTER_0_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP2_P0_MODE_REGISTER_0_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP3_P0_MODE_REGISTER_0_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR0_PRI_RP3_P0_MODE_REGISTER_0_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP0_P0_MODE_REGISTER_0_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP0_P0_MODE_REGISTER_0_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP1_P0_MODE_REGISTER_0_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP1_P0_MODE_REGISTER_0_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP2_P0_MODE_REGISTER_0_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP2_P0_MODE_REGISTER_0_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP3_P0_MODE_REGISTER_0_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR0_SEC_RP3_P0_MODE_REGISTER_0_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_0_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP0_P0_MODE_REGISTER_1_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP0_P0_MODE_REGISTER_1_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP1_P0_MODE_REGISTER_1_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP1_P0_MODE_REGISTER_1_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP2_P0_MODE_REGISTER_1_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP2_P0_MODE_REGISTER_1_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP3_P0_MODE_REGISTER_1_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR1_PRI_RP3_P0_MODE_REGISTER_1_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP0_P0_MODE_REGISTER_1_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP0_P0_MODE_REGISTER_1_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP1_P0_MODE_REGISTER_1_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP1_P0_MODE_REGISTER_1_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP2_P0_MODE_REGISTER_1_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP2_P0_MODE_REGISTER_1_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP3_P0_MODE_REGISTER_1_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR1_SEC_RP3_P0_MODE_REGISTER_1_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_1_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP0_P0_MODE_REGISTER_2_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP0_P0_MODE_REGISTER_2_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP1_P0_MODE_REGISTER_2_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP1_P0_MODE_REGISTER_2_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP2_P0_MODE_REGISTER_2_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP2_P0_MODE_REGISTER_2_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP3_P0_MODE_REGISTER_2_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR2_PRI_RP3_P0_MODE_REGISTER_2_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP0_P0_MODE_REGISTER_2_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP0_P0_MODE_REGISTER_2_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP1_P0_MODE_REGISTER_2_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP1_P0_MODE_REGISTER_2_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP2_P0_MODE_REGISTER_2_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP2_P0_MODE_REGISTER_2_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP3_P0_MODE_REGISTER_2_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR2_SEC_RP3_P0_MODE_REGISTER_2_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_2_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP0_P0_MODE_REGISTER_3_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP0_P0_MODE_REGISTER_3_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP1_P0_MODE_REGISTER_3_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP1_P0_MODE_REGISTER_3_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP2_P0_MODE_REGISTER_3_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP2_P0_MODE_REGISTER_3_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP3_P0_MODE_REGISTER_3_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR3_PRI_RP3_P0_MODE_REGISTER_3_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP0_P0_MODE_REGISTER_3_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP0_P0_MODE_REGISTER_3_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP1_P0_MODE_REGISTER_3_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP1_P0_MODE_REGISTER_3_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP2_P0_MODE_REGISTER_3_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP2_P0_MODE_REGISTER_3_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP3_P0_MODE_REGISTER_3_VALUE      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE );
+REG64_FLD( MCA_DDRPHY_PC_MR3_SEC_RP3_P0_MODE_REGISTER_3_VALUE_LEN  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_REGISTER_3_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_RANK_PAIR           , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_RANK_PAIR );
+REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_RANK_PAIR_LEN       , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_RANK_PAIR_LEN );
+REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_ZCAL                , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_ZCAL   );
+REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_SYSCLK_ALIGN        , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_SYSCLK_ALIGN );
+REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_READ_CTR            , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_READ_CTR );
+REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_RDCLK_ALIGN         , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_RDCLK_ALIGN );
+REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ENA_DQS_ALIGN           , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_DQS_ALIGN );
+REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_NEXT_RANK_PAIR          , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_NEXT_RANK_PAIR );
+REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_NEXT_RANK_PAIR_LEN      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_NEXT_RANK_PAIR_LEN );
+REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_FAST_SIM_CNTR           , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FAST_SIM_CNTR );
+REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_START_INIT              , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_START_INIT );
+REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_START                   , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_START      );
+REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_ABORT_ON_ERR_EN         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ABORT_ON_ERR_EN );
+REG64_FLD( MCA_DDRPHY_PC_PER_CAL_CONFIG_P0_DD2_FIX_DIS             , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DD2_FIX_DIS );
+
+REG64_FLD( MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_ENA_RANK               , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_RANK   );
+REG64_FLD( MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_ENA_RANK_LEN           , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENA_RANK_LEN );
+REG64_FLD( MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_NEXT_RANK              , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_NEXT_RANK  );
+REG64_FLD( MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_NEXT_RANK_LEN          , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_NEXT_RANK_LEN );
+REG64_FLD( MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0_START                  , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_START      );
+
+REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_MASTER                     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MASTER     );
+REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DLL                        , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DLL        );
+REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DLL_CLOCK_GATE             , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DLL_CLOCK_GATE );
+REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DQS                        , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DQS        );
+REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_VPROTH                     , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPROTH     );
+REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_KPRIME                     , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_KPRIME     );
+REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_PORTPOWERDOWN              , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORTPOWERDOWN );
+REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_ANALOG_INPUT_STAB          , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ANALOG_INPUT_STAB );
+REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_ZCAL                       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ZCAL       );
+REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_DELAY_LINE_CTL_OVERRIDE    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DELAY_LINE_CTL_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_WR_FIFO_STAB               , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WR_FIFO_STAB );
+REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_RX                         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX         );
+REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_TX_TRISTATE                , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TX_TRISTATE );
+REG64_FLD( MCA_DDRPHY_PC_POWERDOWN_1_P0_VREG_S                     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VREG_S     );
+
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP0_TER     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP0_TER );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP0_QUA     , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP0_QUA );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP1_TER     , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP1_TER );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP1_QUA     , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP1_QUA );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP2_TER     , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP2_TER );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP2_QUA     , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP2_QUA );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP3_TER     , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP3_TER );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_EXT_P0_ADDR_MIRROR_RP3_QUA     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP3_QUA );
+
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP0_PRI         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP0_PRI );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP0_SEC         , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP0_SEC );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP1_PRI         , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP1_PRI );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP1_SEC         , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP1_SEC );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP2_PRI         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP2_PRI );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP2_SEC         , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP2_SEC );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP3_PRI         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP3_PRI );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_RP3_SEC         , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_RP3_SEC );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_GROUPING                    , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_GROUPING   );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_GROUPING_LEN                , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_GROUPING_LEN );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_A3_A4           , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_A3_A4 );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_A5_A6           , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_A5_A6 );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_A7_A8           , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_A7_A8 );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_A11_A13         , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_A11_A13 );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_BA0_BA1         , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_BA0_BA1 );
+REG64_FLD( MCA_DDRPHY_PC_RANK_GROUP_P0_ADDR_MIRROR_BG0_BG1         , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_MIRROR_BG0_BG1 );
+
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PRI                         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRI        );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PRI_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRI_LEN    );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PRI_V                       , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRI_V      );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_SEC                         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEC        );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_SEC_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEC_LEN    );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_SEC_V                       , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEC_V      );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI                   , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR1_PRI  );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI_LEN               , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR1_PRI_LEN );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_PRI_V                 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR1_PRI_V );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_SEC                   , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR1_SEC  );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_SEC_LEN               , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR1_SEC_LEN );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR0_P0_PAIR1_SEC_V                 , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR1_SEC_V );
+
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI                   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR2_PRI  );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI_LEN               , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR2_PRI_LEN );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_PRI_V                 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR2_PRI_V );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_SEC                   , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR2_SEC  );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_SEC_LEN               , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR2_SEC_LEN );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR2_SEC_V                 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR2_SEC_V );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI                   , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR3_PRI  );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI_LEN               , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR3_PRI_LEN );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_PRI_V                 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR3_PRI_V );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_SEC                   , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR3_SEC  );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_SEC_LEN               , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR3_SEC_LEN );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR1_P0_PAIR3_SEC_V                 , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR3_SEC_V );
+
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_TER                   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR0_TER  );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_TER_LEN               , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR0_TER_LEN );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_TER_V                 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR0_TER_V );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_QUA                   , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR0_QUA  );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_QUA_LEN               , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR0_QUA_LEN );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR0_QUA_V                 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR0_QUA_V );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_TER                   , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR1_TER  );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_TER_LEN               , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR1_TER_LEN );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_TER_V                 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR1_TER_V );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_QUA                   , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR1_QUA  );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_QUA_LEN               , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR1_QUA_LEN );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR2_P0_PAIR1_QUA_V                 , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR1_QUA_V );
+
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_TER                   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR2_TER  );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_TER_LEN               , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR2_TER_LEN );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_TER_V                 , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR2_TER_V );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_QUA                   , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR2_QUA  );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_QUA_LEN               , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR2_QUA_LEN );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_PAIR2_QUA_V                 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAIR2_QUA_V );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_TER                         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TER        );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_TER_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TER_LEN    );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_TER_V                       , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TER_V      );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_QUA                         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_QUA        );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_QUA_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_QUA_LEN    );
+REG64_FLD( MCA_DDRPHY_PC_RANK_PAIR3_P0_QUA_V                       , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_QUA_V      );
+
+REG64_FLD( MCA_DDRPHY_PC_RELOAD_VALUE0_P0_PERIODIC_CAL_REQ_EN      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERIODIC_CAL_REQ_EN );
+REG64_FLD( MCA_DDRPHY_PC_RELOAD_VALUE0_P0_PERIODIC                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERIODIC   );
+REG64_FLD( MCA_DDRPHY_PC_RELOAD_VALUE0_P0_PERIODIC_LEN             , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERIODIC_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_RESETS_P0_SYSCLK_RESET                    , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYSCLK_RESET );
+REG64_FLD( MCA_DDRPHY_PC_RESETS_P0_PVT_OVERRIDE                    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PVT_OVERRIDE );
+REG64_FLD( MCA_DDRPHY_PC_RESETS_P0_ENABLE_ZCAL                     , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_ZCAL );
+
+REG64_FLD( MCA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ0DSGN           , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VREFDQ0DSGN );
+REG64_FLD( MCA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ0D              , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VREFDQ0D   );
+REG64_FLD( MCA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ0D_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VREFDQ0D_LEN );
+REG64_FLD( MCA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ1DSGN           , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VREFDQ1DSGN );
+REG64_FLD( MCA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ1D              , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VREFDQ1D   );
+REG64_FLD( MCA_DDRPHY_PC_VREF_DRV_CONTROL_P0_VREFDQ1D_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VREFDQ1D_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_ZCAL_TIMER_P0_PERIODIC                    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PERIODIC   );
+REG64_FLD( MCA_DDRPHY_PC_ZCAL_TIMER_P0_PERIODIC_LEN                , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PERIODIC_LEN );
+
+REG64_FLD( MCA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0_PERIODIC       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERIODIC   );
+REG64_FLD( MCA_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0_PERIODIC_LEN   , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERIODIC_LEN );
+
+REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_GLOBAL_PHY_OFFSET              , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_GLOBAL_PHY_OFFSET );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_GLOBAL_PHY_OFFSET_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_GLOBAL_PHY_OFFSET_LEN );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_ADVANCE_RD_VALID               , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADVANCE_RD_VALID );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_PER_DUTY_CYCLE_SW              , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PER_DUTY_CYCLE_SW );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_PER_REPEAT_COUNT               , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PER_REPEAT_COUNT );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_PER_REPEAT_COUNT_LEN           , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PER_REPEAT_COUNT_LEN );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_SINGLE_BIT_MPR_RP0             , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SINGLE_BIT_MPR_RP0 );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_SINGLE_BIT_MPR_RP1             , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SINGLE_BIT_MPR_RP1 );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_SINGLE_BIT_MPR_RP2             , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SINGLE_BIT_MPR_RP2 );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_SINGLE_BIT_MPR_RP3             , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SINGLE_BIT_MPR_RP3 );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_ALIGN_ON_EVEN_CYCLES           , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ALIGN_ON_EVEN_CYCLES );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_PERFORM_RDCLK_ALIGN            , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFORM_RDCLK_ALIGN );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG0_P0_STAGGERED_PATTERN              , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_STAGGERED_PATTERN );
+
+REG64_FLD( MCA_DDRPHY_RC_CONFIG1_P0_OUTER_LOOP_CNT                 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_OUTER_LOOP_CNT );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG1_P0_OUTER_LOOP_CNT_LEN             , 14  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_OUTER_LOOP_CNT_LEN );
+
+REG64_FLD( MCA_DDRPHY_RC_CONFIG2_P0_CONSEQ_PASS                    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONSEQ_PASS );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG2_P0_CONSEQ_PASS_LEN                , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONSEQ_PASS_LEN );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG2_P0_BURST_WINDOW                   , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_BURST_WINDOW );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG2_P0_BURST_WINDOW_LEN               , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_BURST_WINDOW_LEN );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG2_P0_ALLOW_RD_FIFO_AUTO_RESET       , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ALLOW_RD_FIFO_AUTO_RESET );
+
+REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_FINE_CAL_STEP_SIZE             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FINE_CAL_STEP_SIZE );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_FINE_CAL_STEP_SIZE_LEN         , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FINE_CAL_STEP_SIZE_LEN );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_COARSE_CAL_STEP_SIZE           , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_COARSE_CAL_STEP_SIZE );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_COARSE_CAL_STEP_SIZE_LEN       , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_COARSE_CAL_STEP_SIZE_LEN );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_QUAD                    , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DQ_SEL_QUAD );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_QUAD_LEN                , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DQ_SEL_QUAD_LEN );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_LANE                    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DQ_SEL_LANE );
+REG64_FLD( MCA_DDRPHY_RC_CONFIG3_P0_DQ_SEL_LANE_LEN                , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DQ_SEL_LANE_LEN );
+
+REG64_FLD( MCA_DDRPHY_RC_ERROR_MASK0_P0_RD_CNTL_MASK               , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RD_CNTL_MASK );
+
+REG64_FLD( MCA_DDRPHY_RC_ERROR_STATUS0_P0_RD_CNTL                  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_CNTL    );
+
+REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG0_P0_GUESS_WAIT_TIME         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_GUESS_WAIT_TIME );
+REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG0_P0_GUESS_WAIT_TIME_LEN     , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_GUESS_WAIT_TIME_LEN );
+
+REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CMD_PRECEDE_TIME        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_PRECEDE_TIME );
+REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CMD_PRECEDE_TIME_LEN    , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_PRECEDE_TIME_LEN );
+REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_MPR_PAGE                , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MPR_PAGE   );
+REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_MPR_PAGE_LEN            , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MPR_PAGE_LEN );
+REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_CALIBRATION_ENABLE      , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CALIBRATION_ENABLE );
+REG64_FLD( MCA_DDRPHY_RC_RDVREF_CONFIG1_P0_SKIP_RDCENTERING        , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SKIP_RDCENTERING );
+
+REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_MPR_PATTERN_BIT               , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MPR_PATTERN_BIT );
+REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_TWO_CYCLE_ADDR_EN             , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TWO_CYCLE_ADDR_EN );
+REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_MR_MASK_EN                    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MR_MASK_EN );
+REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_MR_MASK_EN_LEN                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MR_MASK_EN_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_DELAYED_PAR                   , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DELAYED_PAR );
+REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_LRDIMM_CONTEXT                , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_CONTEXT );
+REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_FORCE_RESERVED                , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_RESERVED );
+REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_HALT_ROTATION                 , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HALT_ROTATION );
+REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_FORCE_MPR                     , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_MPR  );
+REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_CLONE_CS_MODE                 , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CLONE_CS_MODE );
+REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_PAR_INVERT                    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAR_INVERT );
+REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_IPW_SIDEAB_SEL                , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_IPW_SIDEAB_SEL );
+REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_PAR_17_MASK                   , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAR_17_MASK );
+REG64_FLD( MCA_DDRPHY_SEQ_CONFIG0_P0_CW_MIRROR                     , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CW_MIRROR  );
+
+REG64_FLD( MCA_DDRPHY_SEQ_ERROR_MASK0_P0_MULT_REQ_ERR_MASK         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MULT_REQ_ERR_MASK );
+REG64_FLD( MCA_DDRPHY_SEQ_ERROR_MASK0_P0_INVALID_REQTYPE_ERR_MASK  , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_INVALID_REQTYPE_ERR_MASK );
+REG64_FLD( MCA_DDRPHY_SEQ_ERROR_MASK0_P0_EARLY_REQ_ERR_MASK        , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EARLY_REQ_ERR_MASK );
+
+REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_MULTIPLE_REQ            , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_MULTIPLE_REQ );
+REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_EARLY_REQ               , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_EARLY_REQ  );
+REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_MULTIPLE_REQ_SOURCE     , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_MULTIPLE_REQ_SOURCE );
+REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_MULTIPLE_REQ_SOURCE_LEN , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_MULTIPLE_REQ_SOURCE_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQTYPE         , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_INVALID_REQTYPE );
+REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQTYPE_LEN     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_INVALID_REQTYPE_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQ_SOURCE      , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_INVALID_REQ_SOURCE );
+REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_INVALID_REQ_SOURCE_LEN  , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_INVALID_REQ_SOURCE_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_EARLY_REQ_SOURCE        , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_EARLY_REQ_SOURCE );
+REG64_FLD( MCA_DDRPHY_SEQ_ERROR_STATUS0_P0_EARLY_REQ_SOURCE_LEN    , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_EARLY_REQ_SOURCE_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_LPT_ADDR2_P0_ADDR2                       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR2      );
+REG64_FLD( MCA_DDRPHY_SEQ_LPT_ADDR2_P0_ADDR2_LEN                   , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR2_LEN  );
+
+REG64_FLD( MCA_DDRPHY_SEQ_LPT_ADDR3_P0_ADDR3                       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR3      );
+REG64_FLD( MCA_DDRPHY_SEQ_LPT_ADDR3_P0_ADDR3_LEN                   , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_SEQ_LPT_ADDR4_P0_ADDR4                       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR4      );
+REG64_FLD( MCA_DDRPHY_SEQ_LPT_ADDR4_P0_ADDR4_LEN                   , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR4_LEN  );
+
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TMOD_CYCLES         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TMOD_CYCLES );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TMOD_CYCLES_LEN     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TMOD_CYCLES_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRCD_CYCLES         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRCD_CYCLES );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRCD_CYCLES_LEN     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRCD_CYCLES_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRP_CYCLES          , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRP_CYCLES );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRP_CYCLES_LEN      , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRP_CYCLES_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRFC_CYCLES         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRFC_CYCLES );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0_TRFC_CYCLES_LEN     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRFC_CYCLES_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQINIT_CYCLES      , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TZQINIT_CYCLES );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQINIT_CYCLES_LEN  , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TZQINIT_CYCLES_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQCS_CYCLES        , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TZQCS_CYCLES );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TZQCS_CYCLES_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TZQCS_CYCLES_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWLDQSEN_CYCLES     , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TWLDQSEN_CYCLES );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWLDQSEN_CYCLES_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TWLDQSEN_CYCLES_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWRMRD_CYCLES       , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TWRMRD_CYCLES );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0_TWRMRD_CYCLES_LEN   , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TWRMRD_CYCLES_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TODTLON_OFF_CYCLES  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TODTLON_OFF_CYCLES );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TODTLON_OFF_CYCLES_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TODTLON_OFF_CYCLES_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TRC_CYCLES          , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRC_CYCLES );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TRC_CYCLES_LEN      , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRC_CYCLES_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TMRSC_CYCLES        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TMRSC_CYCLES );
+REG64_FLD( MCA_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0_TMRSC_CYCLES_LEN    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TMRSC_CYCLES_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0_DEF_VALUES         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEF_VALUES );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_DEFAULT_CONFIG_P0_DEF_VALUES_LEN     , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEF_VALUES_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES0                , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES0    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES0_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES0_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES1                , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES1    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0_VALUES1_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES1_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES2                , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES2    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES2_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES2_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES3                , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES3    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0_VALUES3_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES3_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0_VALUES4                , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES4    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0_VALUES4_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES4_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0_VALUES5                , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES5    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0_VALUES5_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES5_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0_VALUES6                , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES6    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0_VALUES6_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES6_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0_VALUES7                , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES7    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0_VALUES7_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES7_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES0                , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES0    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES0_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES0_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES1                , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES1    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0_VALUES1_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES1_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES2                , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES2    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES2_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES2_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES3                , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES3    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0_VALUES3_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES3_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0_VALUES4                , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES4    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0_VALUES4_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES4_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0_VALUES5                , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES5    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0_VALUES5_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES5_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0_VALUES6                , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES6    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0_VALUES6_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES6_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0_VALUES7                , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES7    );
+REG64_FLD( MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0_VALUES7_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUES7_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_RD_WR_DATA0_P0_DATA_REG0                 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_REG0  );
+REG64_FLD( MCA_DDRPHY_SEQ_RD_WR_DATA0_P0_DATA_REG0_LEN             , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_REG0_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_RD_WR_DATA1_P0_DATA_REG1                 , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_REG1  );
+REG64_FLD( MCA_DDRPHY_SEQ_RD_WR_DATA1_P0_DATA_REG1_LEN             , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_REG1_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR0_P0_ADDR0                  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR0      );
+REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR0_P0_ADDR0_LEN              , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR0_LEN  );
+
+REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR1_P0_ADDR1                  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR1      );
+REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR1_P0_ADDR1_LEN              , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR1_LEN  );
+
+REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR2_P0_ADDR2                  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR2      );
+REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR2_P0_ADDR2_LEN              , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR2_LEN  );
+
+REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR3_P0_ADDR3                  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR3      );
+REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR3_P0_ADDR3_LEN              , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR3_LEN  );
+
+REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR4_P0_ADDR4                  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR4      );
+REG64_FLD( MCA_DDRPHY_SEQ_RESERVED_ADDR4_P0_ADDR4_LEN              , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR4_LEN  );
+
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR0_NOM_VALUE       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR0_NOM_VALUE );
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR0_NOM_VALUE_LEN   , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR0_NOM_VALUE_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR1_NOM_VALUE       , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR1_NOM_VALUE );
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR1_NOM_VALUE_LEN   , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR1_NOM_VALUE_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR2_NOM_VALUE       , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR2_NOM_VALUE );
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR2_NOM_VALUE_LEN   , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR2_NOM_VALUE_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR3_NOM_VALUE       , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR3_NOM_VALUE );
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR3_NOM_VALUE_LEN   , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR3_NOM_VALUE_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR4_NOM_VALUE       , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR4_NOM_VALUE );
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP0_P0_RTT_WR4_NOM_VALUE_LEN   , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR4_NOM_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR5_NOM_VALUE       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR5_NOM_VALUE );
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR5_NOM_VALUE_LEN   , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR5_NOM_VALUE_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR6_NOM_VALUE       , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR6_NOM_VALUE );
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR6_NOM_VALUE_LEN   , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR6_NOM_VALUE_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR7_NOM_VALUE       , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR7_NOM_VALUE );
+REG64_FLD( MCA_DDRPHY_SEQ_WR_TERM_SWAP1_P0_RTT_WR7_NOM_VALUE_LEN   , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RTT_WR7_NOM_VALUE_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_0_2           , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_2        );
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_TYPE_0_2  , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_TYPE_0_2 );
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_0_2       , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_0_2    );
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_0_2_LEN   , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_0_2_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_1_3           , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_3        );
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_TYPE_1_3  , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_TYPE_1_3 );
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_1_3       , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_1_3    );
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG0_P0_SEL_1_3_LEN   , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_1_3_LEN );
+
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_0_2           , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_2        );
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_TYPE_0_2  , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_TYPE_0_2 );
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_0_2       , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_0_2    );
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_0_2_LEN   , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_0_2_LEN );
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_1_3           , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_3        );
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_TYPE_1_3  , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_TYPE_1_3 );
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_1_3       , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_1_3    );
+REG64_FLD( MCA_DDRPHY_SEQ_ZQCAL_ENC_RANK_CTL_REG1_P0_SEL_1_3_LEN   , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_1_3_LEN );
+
+REG64_FLD( MCA_DDRPHY_WC_CONFIG0_P0_TWLO_TWLOE                     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TWLO_TWLOE );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG0_P0_TWLO_TWLOE_LEN                 , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TWLO_TWLOE_LEN );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG0_P0_WL_ONE_DQS_PULSE               , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WL_ONE_DQS_PULSE );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG0_P0_FW_WR_RD                       , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FW_WR_RD   );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG0_P0_FW_WR_RD_LEN                   , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FW_WR_RD_LEN );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG0_P0_CUSTOM_INIT_WRITE              , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CUSTOM_INIT_WRITE );
+
+REG64_FLD( MCA_DDRPHY_WC_CONFIG1_P0_BIG_STEP                       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_BIG_STEP   );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG1_P0_BIG_STEP_LEN                   , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_BIG_STEP_LEN );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG1_P0_SMALL_STEP                     , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SMALL_STEP );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG1_P0_SMALL_STEP_LEN                 , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SMALL_STEP_LEN );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG1_P0_WR_PRE_DLY                     , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WR_PRE_DLY );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG1_P0_WR_PRE_DLY_LEN                 , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WR_PRE_DLY_LEN );
+
+REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_NUM_VALID_SAMPLES              , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_NUM_VALID_SAMPLES );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_NUM_VALID_SAMPLES_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_NUM_VALID_SAMPLES_LEN );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_FW_RD_WR                       , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FW_RD_WR   );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_FW_RD_WR_LEN                   , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FW_RD_WR_LEN );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_IPW_WR_WR                      , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_IPW_WR_WR  );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_IPW_WR_WR_LEN                  , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_IPW_WR_WR_LEN );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_EN_RESET_DD2_FIX_DIS           , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EN_RESET_DD2_FIX_DIS );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG2_P0_EN_RESET_WR_DELAY_WL           , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EN_RESET_WR_DELAY_WL );
+
+REG64_FLD( MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON                  , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MRS_CMD_DQ_ON );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON_LEN              , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MRS_CMD_DQ_ON_LEN );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_OFF                 , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MRS_CMD_DQ_OFF );
+REG64_FLD( MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_OFF_LEN             , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MRS_CMD_DQ_OFF_LEN );
+
+REG64_FLD( MCA_DDRPHY_WC_ERROR_MASK0_P0_WR_CNTL_MASK               , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WR_CNTL_MASK );
+
+REG64_FLD( MCA_DDRPHY_WC_ERROR_STATUS0_P0_WR_CNTL                  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_CNTL    );
+
+REG64_FLD( MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_WL                  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WL         );
+REG64_FLD( MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_CTR                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CTR        );
+REG64_FLD( MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_CTR_VREF_COUNTER_RESET_VAL , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CTR_VREF_COUNTER_RESET_VAL );
+REG64_FLD( MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0_CTR_VREF_COUNTER_RESET_VAL_LEN , 10  , SH_UNT_MCA      ,
+           SH_ACS_SCOM_RW  , SH_FLD_CTR_VREF_COUNTER_RESET_VAL_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP0_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP1_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP2_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_0_RP3_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP0_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP1_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP2_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_10_RP3_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP0_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP1_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP2_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_11_RP3_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP0_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP1_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP2_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_12_RP3_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP0_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP1_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP2_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_13_RP3_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP0_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP1_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP2_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_14_RP3_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP0_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP1_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP2_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_15_RP3_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP0_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP1_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP2_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_16_RP3_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP0_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP1_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP2_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_18_RP3_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP0_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP1_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP2_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_1_RP3_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP0_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP1_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP2_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_20_RP3_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP0_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP1_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP2_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_0_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_0_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_1_01_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_1_01_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_2_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_2_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_3_23_DELAYG       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_3_23_DELAYG_LEN   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_4_4_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_22_RP3_REG_P0_4_4_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP0_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP1_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP2_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_2_RP3_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP0_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP1_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP2_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_3_RP3_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_4_DELAYG           , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DELAYG     );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP0_REG_P0_4_DELAYG_LEN       , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_4_DELAYG           , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DELAYG     );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP1_REG_P0_4_DELAYG_LEN       , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_4_DELAYG           , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DELAYG     );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP2_REG_P0_4_DELAYG_LEN       , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_4_DELAYG           , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DELAYG     );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_4_RP3_REG_P0_4_DELAYG_LEN       , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP0_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP1_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP2_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_5_RP3_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP0_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP1_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP2_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_6_RP3_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP0_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP1_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP2_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_7_RP3_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP0_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP1_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP2_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_8_RP3_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP0_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP1_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP2_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_0_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_0_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_1_01_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_1_01_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_01_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_2_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_2_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_3_23_DELAYG        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG  );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_3_23_DELAYG_LEN    , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_23_DELAYG_LEN );
+
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_4_4_DELAYG         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG   );
+REG64_FLD( MCA_DP16_WR_DELAY_VALUE_9_RP3_REG_P0_4_4_DELAYG_LEN     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_DELAYG_LEN );
+
+REG64_FLD( MCA_EICR_ADDRESS                                        , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( MCA_EICR_ADDRESS_LEN                                    , 37  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( MCA_EICR_RESERVED                                       , 37  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED   );
+REG64_FLD( MCA_EICR_PERSIST                                        , 38  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERSIST    );
+REG64_FLD( MCA_EICR_PERSIST_LEN                                    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERSIST_LEN );
+REG64_FLD( MCA_EICR_REGION                                         , 40  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION     );
+REG64_FLD( MCA_EICR_REGION_LEN                                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION_LEN );
+REG64_FLD( MCA_EICR_TYPE                                           , 43  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TYPE       );
+REG64_FLD( MCA_EICR_TYPE_LEN                                       , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( MCA_EICR_MISC                                           , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MISC       );
+REG64_FLD( MCA_EICR_MISC_LEN                                       , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MISC_LEN   );
+
+REG64_FLD( MCA_ELPR_LOG_FULL                                       , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_LOG_FULL   );
+REG64_FLD( MCA_ELPR_LOG_POINTER                                    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_LOG_POINTER );
+REG64_FLD( MCA_ELPR_LOG_POINTER_LEN                                , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_LOG_POINTER_LEN );
+
+REG64_FLD( MCA_WDF_FIR_MAINLINE_MPE_RANK_0_TO_7                    , 0   , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINLINE_MPE_RANK_0_TO_7 );
+REG64_FLD( MCA_WDF_FIR_MAINLINE_MPE_RANK_0_TO_7_LEN                , 8   , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINLINE_MPE_RANK_0_TO_7_LEN );
+REG64_FLD( MCA_WDF_FIR_MAINLINE_NCE                                , 8   , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINLINE_NCE );
+REG64_FLD( MCA_WDF_FIR_MAINLINE_TCE                                , 9   , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINLINE_TCE );
+REG64_FLD( MCA_WDF_FIR_MAINLINE_SCE                                , 10  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINLINE_SCE );
+REG64_FLD( MCA_WDF_FIR_MAINLINE_MCE                                , 11  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINLINE_MCE );
+REG64_FLD( MCA_WDF_FIR_MAINLINE_SUE                                , 12  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINLINE_SUE );
+REG64_FLD( MCA_WDF_FIR_MAINLINE_AUE                                , 13  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINLINE_AUE );
+REG64_FLD( MCA_WDF_FIR_MAINLINE_UE                                 , 14  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINLINE_UE );
+REG64_FLD( MCA_WDF_FIR_MAINLINE_RCD                                , 15  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINLINE_RCD );
+REG64_FLD( MCA_WDF_FIR_MAINLINE_IAUE                               , 16  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINLINE_IAUE );
+REG64_FLD( MCA_WDF_FIR_MAINLINE_IUE                                , 17  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINLINE_IUE );
+REG64_FLD( MCA_WDF_FIR_MAINLINE_IRCD                               , 18  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINLINE_IRCD );
+REG64_FLD( MCA_WDF_FIR_MAINLINE_IMPE                               , 19  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINLINE_IMPE );
+REG64_FLD( MCA_WDF_FIR_MAINTENANCE_MPE_RANK_0_TO_7                 , 20  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7 );
+REG64_FLD( MCA_WDF_FIR_MAINTENANCE_MPE_RANK_0_TO_7_LEN             , 8   , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7_LEN );
+REG64_FLD( MCA_WDF_FIR_MAINTENANCE_NCE                             , 28  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINTENANCE_NCE );
+REG64_FLD( MCA_WDF_FIR_MAINTENANCE_TCE                             , 29  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINTENANCE_TCE );
+REG64_FLD( MCA_WDF_FIR_MAINTENANCE_SCE                             , 30  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINTENANCE_SCE );
+REG64_FLD( MCA_WDF_FIR_MAINTENANCE_MCE                             , 31  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINTENANCE_MCE );
+REG64_FLD( MCA_WDF_FIR_MAINTENANCE_SUE                             , 32  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINTENANCE_SUE );
+REG64_FLD( MCA_WDF_FIR_MAINTENANCE_AUE                             , 33  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINTENANCE_AUE );
+REG64_FLD( MCA_WDF_FIR_MAINTENANCE_UE                              , 34  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINTENANCE_UE );
+REG64_FLD( MCA_WDF_FIR_MAINTENANCE_RCD                             , 35  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINTENANCE_RCD );
+REG64_FLD( MCA_WDF_FIR_MAINTENANCE_IAUE                            , 36  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINTENANCE_IAUE );
+REG64_FLD( MCA_WDF_FIR_MAINTENANCE_IUE                             , 37  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINTENANCE_IUE );
+REG64_FLD( MCA_WDF_FIR_MAINTENANCE_IRCD                            , 38  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINTENANCE_IRCD );
+REG64_FLD( MCA_WDF_FIR_MAINTENANCE_IMPE                            , 39  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_MAINTENANCE_IMPE );
+REG64_FLD( MCA_WDF_FIR_RESERVED_40                                 , 40  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_RESERVED_40 );
+REG64_FLD( MCA_WDF_FIR_SCOM_PARITY_CLASS_STATUS                    , 41  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_SCOM_PARITY_CLASS_STATUS );
+REG64_FLD( MCA_WDF_FIR_SCOM_PARITY_CLASS_RECOVERABLE               , 42  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_SCOM_PARITY_CLASS_RECOVERABLE );
+REG64_FLD( MCA_WDF_FIR_SCOM_PARITY_CLASS_UNRECOVERABLE             , 43  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_SCOM_PARITY_CLASS_UNRECOVERABLE );
+REG64_FLD( MCA_WDF_FIR_ECC_CORRECTOR_INTERNAL_PARITY_ERROR         , 44  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_ECC_CORRECTOR_INTERNAL_PARITY_ERROR );
+REG64_FLD( MCA_WDF_FIR_WRITE_RMW_CE                                , 45  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_WRITE_RMW_CE );
+REG64_FLD( MCA_WDF_FIR_WRITE_RMW_UE                                , 46  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_WRITE_RMW_UE );
+REG64_FLD( MCA_WDF_FIR_WRITE_RMW_SUE                               , 47  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_WRITE_RMW_SUE );
+REG64_FLD( MCA_WDF_FIR_WDF_OVERRUN_ERROR_0                         , 48  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_WDF_OVERRUN_ERROR_0 );
+REG64_FLD( MCA_WDF_FIR_WDF_OVERRUN_ERROR_1                         , 49  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_WDF_OVERRUN_ERROR_1 );
+REG64_FLD( MCA_WDF_FIR_WDF_SCOM_SEQUENCE_ERROR                     , 50  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_WDF_SCOM_SEQUENCE_ERROR );
+REG64_FLD( MCA_WDF_FIR_WDF_STATE_MACHINE_ERROR                     , 51  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_WDF_STATE_MACHINE_ERROR );
+REG64_FLD( MCA_WDF_FIR_WDF_MISC_REGISTER_PARITY_ERROR              , 52  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_WDF_MISC_REGISTER_PARITY_ERROR );
+REG64_FLD( MCA_WDF_FIR_WRT_SCOM_SEQUENCE_ERROR                     , 53  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_WRT_SCOM_SEQUENCE_ERROR );
+REG64_FLD( MCA_WDF_FIR_WRT_MISC_REGISTER_PARITY_ERROR              , 54  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_WRT_MISC_REGISTER_PARITY_ERROR );
+REG64_FLD( MCA_WDF_FIR_ECC_GENERATOR_INTERNAL_PARITY_ERROR         , 55  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_ECC_GENERATOR_INTERNAL_PARITY_ERROR );
+REG64_FLD( MCA_WDF_FIR_READ_BUFFER_OVERFLOW_ERROR                  , 56  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_READ_BUFFER_OVERFLOW_ERROR );
+REG64_FLD( MCA_WDF_FIR_WDF_ASYNC_INTERFACE_ERROR                   , 57  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_WDF_ASYNC_INTERFACE_ERROR );
+REG64_FLD( MCA_WDF_FIR_READ_ASYNC_INTERFACE_PARITY_ERROR           , 58  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_READ_ASYNC_INTERFACE_PARITY_ERROR );
+REG64_FLD( MCA_WDF_FIR_READ_ASYNC_INTERFACE_SEQUENCE_ERROR         , 59  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_READ_ASYNC_INTERFACE_SEQUENCE_ERROR );
+REG64_FLD( MCA_WDF_FIR_RESERVED                                    , 60  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_RESERVED   );
+REG64_FLD( MCA_WDF_FIR_RESERVED_LEN                                , 2   , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( MCA_WDF_FIR_INTERNAL_SCOM_ERROR                         , 62  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_INTERNAL_SCOM_ERROR );
+REG64_FLD( MCA_WDF_FIR_INTERNAL_SCOM_ERROR_COPY                    , 63  , SH_UNT_MCA_WDF  , SH_ACS_SCOM1_AND,
+           SH_FLD_INTERNAL_SCOM_ERROR_COPY );
+
+REG64_FLD( MCA_FIR_MAINLINE_MPE_RANK_0_TO_7                        , 0   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINLINE_MPE_RANK_0_TO_7 );
+REG64_FLD( MCA_FIR_MAINLINE_MPE_RANK_0_TO_7_LEN                    , 8   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINLINE_MPE_RANK_0_TO_7_LEN );
+REG64_FLD( MCA_FIR_MAINLINE_NCE                                    , 8   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINLINE_NCE );
+REG64_FLD( MCA_FIR_MAINLINE_TCE                                    , 9   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINLINE_TCE );
+REG64_FLD( MCA_FIR_MAINLINE_SCE                                    , 10  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINLINE_SCE );
+REG64_FLD( MCA_FIR_MAINLINE_MCE                                    , 11  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINLINE_MCE );
+REG64_FLD( MCA_FIR_MAINLINE_SUE                                    , 12  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINLINE_SUE );
+REG64_FLD( MCA_FIR_MAINLINE_AUE                                    , 13  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINLINE_AUE );
+REG64_FLD( MCA_FIR_MAINLINE_UE                                     , 14  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINLINE_UE );
+REG64_FLD( MCA_FIR_MAINLINE_RCD                                    , 15  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINLINE_RCD );
+REG64_FLD( MCA_FIR_MAINLINE_IAUE                                   , 16  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINLINE_IAUE );
+REG64_FLD( MCA_FIR_MAINLINE_IUE                                    , 17  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINLINE_IUE );
+REG64_FLD( MCA_FIR_MAINLINE_IRCD                                   , 18  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINLINE_IRCD );
+REG64_FLD( MCA_FIR_MAINLINE_IMPE                                   , 19  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINLINE_IMPE );
+REG64_FLD( MCA_FIR_MAINTENANCE_MPE_RANK_0_TO_7                     , 20  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7 );
+REG64_FLD( MCA_FIR_MAINTENANCE_MPE_RANK_0_TO_7_LEN                 , 8   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7_LEN );
+REG64_FLD( MCA_FIR_MAINTENANCE_NCE                                 , 28  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINTENANCE_NCE );
+REG64_FLD( MCA_FIR_MAINTENANCE_TCE                                 , 29  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINTENANCE_TCE );
+REG64_FLD( MCA_FIR_MAINTENANCE_SCE                                 , 30  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINTENANCE_SCE );
+REG64_FLD( MCA_FIR_MAINTENANCE_MCE                                 , 31  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINTENANCE_MCE );
+REG64_FLD( MCA_FIR_MAINTENANCE_SUE                                 , 32  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINTENANCE_SUE );
+REG64_FLD( MCA_FIR_MAINTENANCE_AUE                                 , 33  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINTENANCE_AUE );
+REG64_FLD( MCA_FIR_MAINTENANCE_UE                                  , 34  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINTENANCE_UE );
+REG64_FLD( MCA_FIR_MAINTENANCE_RCD                                 , 35  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINTENANCE_RCD );
+REG64_FLD( MCA_FIR_MAINTENANCE_IAUE                                , 36  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINTENANCE_IAUE );
+REG64_FLD( MCA_FIR_MAINTENANCE_IUE                                 , 37  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINTENANCE_IUE );
+REG64_FLD( MCA_FIR_MAINTENANCE_IRCD                                , 38  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINTENANCE_IRCD );
+REG64_FLD( MCA_FIR_MAINTENANCE_IMPE                                , 39  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MAINTENANCE_IMPE );
+REG64_FLD( MCA_FIR_RESERVED_40                                     , 40  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_40 );
+REG64_FLD( MCA_FIR_SCOM_PARITY_CLASS_STATUS                        , 41  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PARITY_CLASS_STATUS );
+REG64_FLD( MCA_FIR_SCOM_PARITY_CLASS_RECOVERABLE                   , 42  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PARITY_CLASS_RECOVERABLE );
+REG64_FLD( MCA_FIR_SCOM_PARITY_CLASS_UNRECOVERABLE                 , 43  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PARITY_CLASS_UNRECOVERABLE );
+REG64_FLD( MCA_FIR_ECC_CORRECTOR_INTERNAL_PARITY_ERROR             , 44  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_CORRECTOR_INTERNAL_PARITY_ERROR );
+REG64_FLD( MCA_FIR_WRITE_RMW_CE                                    , 45  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_WRITE_RMW_CE );
+REG64_FLD( MCA_FIR_WRITE_RMW_UE                                    , 46  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_WRITE_RMW_UE );
+REG64_FLD( MCA_FIR_WRITE_RMW_SUE                                   , 47  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_WRITE_RMW_SUE );
+REG64_FLD( MCA_FIR_WDF_OVERRUN_ERROR_0                             , 48  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_WDF_OVERRUN_ERROR_0 );
+REG64_FLD( MCA_FIR_WDF_OVERRUN_ERROR_1                             , 49  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_WDF_OVERRUN_ERROR_1 );
+REG64_FLD( MCA_FIR_WDF_SCOM_SEQUENCE_ERROR                         , 50  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_WDF_SCOM_SEQUENCE_ERROR );
+REG64_FLD( MCA_FIR_WDF_STATE_MACHINE_ERROR                         , 51  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_WDF_STATE_MACHINE_ERROR );
+REG64_FLD( MCA_FIR_WDF_MISC_REGISTER_PARITY_ERROR                  , 52  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_WDF_MISC_REGISTER_PARITY_ERROR );
+REG64_FLD( MCA_FIR_WRT_SCOM_SEQUENCE_ERROR                         , 53  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_WRT_SCOM_SEQUENCE_ERROR );
+REG64_FLD( MCA_FIR_WRT_MISC_REGISTER_PARITY_ERROR                  , 54  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_WRT_MISC_REGISTER_PARITY_ERROR );
+REG64_FLD( MCA_FIR_ECC_GENERATOR_INTERNAL_PARITY_ERROR             , 55  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_GENERATOR_INTERNAL_PARITY_ERROR );
+REG64_FLD( MCA_FIR_READ_BUFFER_OVERFLOW_ERROR                      , 56  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_READ_BUFFER_OVERFLOW_ERROR );
+REG64_FLD( MCA_FIR_WDF_ASYNC_INTERFACE_ERROR                       , 57  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_WDF_ASYNC_INTERFACE_ERROR );
+REG64_FLD( MCA_FIR_READ_ASYNC_INTERFACE_PARITY_ERROR               , 58  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_READ_ASYNC_INTERFACE_PARITY_ERROR );
+REG64_FLD( MCA_FIR_READ_ASYNC_INTERFACE_SEQUENCE_ERROR             , 59  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_READ_ASYNC_INTERFACE_SEQUENCE_ERROR );
+REG64_FLD( MCA_FIR_RESERVED                                        , 60  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED   );
+REG64_FLD( MCA_FIR_RESERVED_LEN                                    , 2   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( MCA_FIR_INTERNAL_SCOM_ERROR                             , 62  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_SCOM_ERROR );
+REG64_FLD( MCA_FIR_INTERNAL_SCOM_ERROR_COPY                        , 63  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_SCOM_ERROR_COPY );
+
+REG64_FLD( MCA_FWMS0_MARK                                          , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK       );
+REG64_FLD( MCA_FWMS0_MARK_LEN                                      , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK_LEN   );
+REG64_FLD( MCA_FWMS0_TYPE                                          , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TYPE       );
+REG64_FLD( MCA_FWMS0_REGION                                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION     );
+REG64_FLD( MCA_FWMS0_REGION_LEN                                    , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION_LEN );
+REG64_FLD( MCA_FWMS0_ADDRESS                                       , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( MCA_FWMS0_ADDRESS_LEN                                   , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( MCA_FWMS0_EXIT_1                                        , 23  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_WREITE_FWMS1_MARK                                   , 0   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK       );
+REG64_FLD( MCA_WREITE_FWMS1_MARK_LEN                               , 8   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK_LEN   );
+REG64_FLD( MCA_WREITE_FWMS1_TYPE                                   , 8   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW  ,
+           SH_FLD_TYPE       );
+REG64_FLD( MCA_WREITE_FWMS1_REGION                                 , 9   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION     );
+REG64_FLD( MCA_WREITE_FWMS1_REGION_LEN                             , 3   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION_LEN );
+REG64_FLD( MCA_WREITE_FWMS1_ADDRESS                                , 12  , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( MCA_WREITE_FWMS1_ADDRESS_LEN                            , 11  , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( MCA_WREITE_FWMS1_EXIT_1                                 , 23  , SH_UNT_MCA_WREITE, SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_FWMS2_MARK                                          , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK       );
+REG64_FLD( MCA_FWMS2_MARK_LEN                                      , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK_LEN   );
+REG64_FLD( MCA_FWMS2_TYPE                                          , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TYPE       );
+REG64_FLD( MCA_FWMS2_REGION                                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION     );
+REG64_FLD( MCA_FWMS2_REGION_LEN                                    , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION_LEN );
+REG64_FLD( MCA_FWMS2_ADDRESS                                       , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( MCA_FWMS2_ADDRESS_LEN                                   , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( MCA_FWMS2_EXIT_1                                        , 23  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_FWMS3_MARK                                          , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK       );
+REG64_FLD( MCA_FWMS3_MARK_LEN                                      , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK_LEN   );
+REG64_FLD( MCA_FWMS3_TYPE                                          , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TYPE       );
+REG64_FLD( MCA_FWMS3_REGION                                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION     );
+REG64_FLD( MCA_FWMS3_REGION_LEN                                    , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION_LEN );
+REG64_FLD( MCA_FWMS3_ADDRESS                                       , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( MCA_FWMS3_ADDRESS_LEN                                   , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( MCA_FWMS3_EXIT_1                                        , 23  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_FWMS4_MARK                                          , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK       );
+REG64_FLD( MCA_FWMS4_MARK_LEN                                      , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK_LEN   );
+REG64_FLD( MCA_FWMS4_TYPE                                          , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TYPE       );
+REG64_FLD( MCA_FWMS4_REGION                                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION     );
+REG64_FLD( MCA_FWMS4_REGION_LEN                                    , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION_LEN );
+REG64_FLD( MCA_FWMS4_ADDRESS                                       , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( MCA_FWMS4_ADDRESS_LEN                                   , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( MCA_FWMS4_EXIT_1                                        , 23  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_FWMS5_MARK                                          , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK       );
+REG64_FLD( MCA_FWMS5_MARK_LEN                                      , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK_LEN   );
+REG64_FLD( MCA_FWMS5_TYPE                                          , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TYPE       );
+REG64_FLD( MCA_FWMS5_REGION                                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION     );
+REG64_FLD( MCA_FWMS5_REGION_LEN                                    , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION_LEN );
+REG64_FLD( MCA_FWMS5_ADDRESS                                       , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( MCA_FWMS5_ADDRESS_LEN                                   , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( MCA_FWMS5_EXIT_1                                        , 23  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_FWMS6_MARK                                          , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK       );
+REG64_FLD( MCA_FWMS6_MARK_LEN                                      , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK_LEN   );
+REG64_FLD( MCA_FWMS6_TYPE                                          , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TYPE       );
+REG64_FLD( MCA_FWMS6_REGION                                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION     );
+REG64_FLD( MCA_FWMS6_REGION_LEN                                    , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION_LEN );
+REG64_FLD( MCA_FWMS6_ADDRESS                                       , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( MCA_FWMS6_ADDRESS_LEN                                   , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( MCA_FWMS6_EXIT_1                                        , 23  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_FWMS7_MARK                                          , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK       );
+REG64_FLD( MCA_FWMS7_MARK_LEN                                      , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MARK_LEN   );
+REG64_FLD( MCA_FWMS7_TYPE                                          , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TYPE       );
+REG64_FLD( MCA_FWMS7_REGION                                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION     );
+REG64_FLD( MCA_FWMS7_REGION_LEN                                    , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGION_LEN );
+REG64_FLD( MCA_FWMS7_ADDRESS                                       , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( MCA_FWMS7_ADDRESS_LEN                                   , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( MCA_FWMS7_EXIT_1                                        , 23  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_HCA_ACCUM_REG_REG                                   , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REG        );
+REG64_FLD( MCA_HCA_ACCUM_REG_REG_LEN                               , 64  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REG_LEN    );
+
+REG64_FLD( MCA_HWMS0_CHIPMARK                                      , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK   );
+REG64_FLD( MCA_HWMS0_CHIPMARK_LEN                                  , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK_LEN );
+REG64_FLD( MCA_HWMS0_CONFIRMED                                     , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIRMED  );
+REG64_FLD( MCA_HWMS0_EXIT_1                                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_WDF_HWMS1_CHIPMARK                                  , 0   , SH_UNT_MCA_WDF  , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK   );
+REG64_FLD( MCA_WDF_HWMS1_CHIPMARK_LEN                              , 8   , SH_UNT_MCA_WDF  , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK_LEN );
+REG64_FLD( MCA_WDF_HWMS1_CONFIRMED                                 , 8   , SH_UNT_MCA_WDF  , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIRMED  );
+REG64_FLD( MCA_WDF_HWMS1_EXIT_1                                    , 9   , SH_UNT_MCA_WDF  , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_HWMS2_CHIPMARK                                      , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK   );
+REG64_FLD( MCA_HWMS2_CHIPMARK_LEN                                  , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK_LEN );
+REG64_FLD( MCA_HWMS2_CONFIRMED                                     , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIRMED  );
+REG64_FLD( MCA_HWMS2_EXIT_1                                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_HWMS3_CHIPMARK                                      , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK   );
+REG64_FLD( MCA_HWMS3_CHIPMARK_LEN                                  , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK_LEN );
+REG64_FLD( MCA_HWMS3_CONFIRMED                                     , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIRMED  );
+REG64_FLD( MCA_HWMS3_EXIT_1                                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_HWMS4_CHIPMARK                                      , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK   );
+REG64_FLD( MCA_HWMS4_CHIPMARK_LEN                                  , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK_LEN );
+REG64_FLD( MCA_HWMS4_CONFIRMED                                     , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIRMED  );
+REG64_FLD( MCA_HWMS4_EXIT_1                                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_HWMS5_CHIPMARK                                      , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK   );
+REG64_FLD( MCA_HWMS5_CHIPMARK_LEN                                  , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK_LEN );
+REG64_FLD( MCA_HWMS5_CONFIRMED                                     , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIRMED  );
+REG64_FLD( MCA_HWMS5_EXIT_1                                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_HWMS6_CHIPMARK                                      , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK   );
+REG64_FLD( MCA_HWMS6_CHIPMARK_LEN                                  , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK_LEN );
+REG64_FLD( MCA_HWMS6_CONFIRMED                                     , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIRMED  );
+REG64_FLD( MCA_HWMS6_EXIT_1                                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_HWMS7_CHIPMARK                                      , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK   );
+REG64_FLD( MCA_HWMS7_CHIPMARK_LEN                                  , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHIPMARK_LEN );
+REG64_FLD( MCA_HWMS7_CONFIRMED                                     , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIRMED  );
+REG64_FLD( MCA_HWMS7_EXIT_1                                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_1     );
+
+REG64_FLD( MCA_MASK_FIR                                            , 0   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR        );
+REG64_FLD( MCA_MASK_FIR_LEN                                        , 64  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_LEN    );
+
+REG64_FLD( MCA_MBACALFIRQ_MBA_RECOVERABLE_ERROR                    , 0   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MBA_RECOVERABLE_ERROR );
+REG64_FLD( MCA_MBACALFIRQ_MBA_NONRECOVERABLE_ERROR                 , 1   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MBA_NONRECOVERABLE_ERROR );
+REG64_FLD( MCA_MBACALFIRQ_REFRESH_OVERRUN                          , 2   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_REFRESH_OVERRUN );
+REG64_FLD( MCA_MBACALFIRQ_WAT_ERROR                                , 3   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_WAT_ERROR  );
+REG64_FLD( MCA_MBACALFIRQ_RCD_PARITY_ERROR                         , 4   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RCD_PARITY_ERROR );
+REG64_FLD( MCA_MBACALFIRQ_DDR_CAL_TIMEOUT_ERR                      , 5   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR_CAL_TIMEOUT_ERR );
+REG64_FLD( MCA_MBACALFIRQ_EMERGENCY_THROTTLE                       , 6   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_EMERGENCY_THROTTLE );
+REG64_FLD( MCA_MBACALFIRQ_DDR_CAL_RESET_TIMEOUT                    , 7   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR_CAL_RESET_TIMEOUT );
+REG64_FLD( MCA_MBACALFIRQ_DDR_MBA_EVENT_N                          , 8   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR_MBA_EVENT_N );
+REG64_FLD( MCA_MBACALFIRQ_WRQ_RRQ_HANG_ERR                         , 9   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_WRQ_RRQ_HANG_ERR );
+REG64_FLD( MCA_MBACALFIRQ_SM_1HOT_ERR                              , 10  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_SM_1HOT_ERR );
+REG64_FLD( MCA_MBACALFIRQ_ASYNC_IF_ERROR                           , 11  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ASYNC_IF_ERROR );
+REG64_FLD( MCA_MBACALFIRQ_CMD_PARITY_ERROR                         , 12  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_CMD_PARITY_ERROR );
+REG64_FLD( MCA_MBACALFIRQ_PORT_FAIL                                , 13  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_PORT_FAIL  );
+REG64_FLD( MCA_MBACALFIRQ_RCD_CAL_PARITY_ERROR                     , 14  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RCD_CAL_PARITY_ERROR );
+REG64_FLD( MCA_MBACALFIRQ_INTERNAL_SCOM_ERROR                      , 15  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_SCOM_ERROR );
+REG64_FLD( MCA_MBACALFIRQ_INTERNAL_SCOM_ERROR_COPY                 , 16  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_SCOM_ERROR_COPY );
+
+REG64_FLD( MCA_MBACALFIR_ACTION0_FIR                               , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR        );
+REG64_FLD( MCA_MBACALFIR_ACTION0_FIR_LEN                           , 17  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_LEN    );
+
+REG64_FLD( MCA_MBACALFIR_ACTION1_FIR                               , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR        );
+REG64_FLD( MCA_MBACALFIR_ACTION1_FIR_LEN                           , 17  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_LEN    );
+
+REG64_FLD( MCA_MBACALFIR_MASK_MBA_RECOVERABLE_ERROR                , 0   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MBA_RECOVERABLE_ERROR );
+REG64_FLD( MCA_MBACALFIR_MASK_MBA_NONRECOVERABLE_ERROR             , 1   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MBA_NONRECOVERABLE_ERROR );
+REG64_FLD( MCA_MBACALFIR_MASK_REFRESH_OVERRUN                      , 2   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_REFRESH_OVERRUN );
+REG64_FLD( MCA_MBACALFIR_MASK_WAT_ERROR                            , 3   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_WAT_ERROR  );
+REG64_FLD( MCA_MBACALFIR_MASK_RCD_PARITY_ERROR                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RCD_PARITY_ERROR );
+REG64_FLD( MCA_MBACALFIR_MASK_DDR_CAL_TIMEOUT_ERR                  , 5   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR_CAL_TIMEOUT_ERR );
+REG64_FLD( MCA_MBACALFIR_MASK_EMERGENCY_THROTTLE                   , 6   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_EMERGENCY_THROTTLE );
+REG64_FLD( MCA_MBACALFIR_MASK_DDR_CAL_RESET_TIMEOUT                , 7   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR_CAL_RESET_TIMEOUT );
+REG64_FLD( MCA_MBACALFIR_MASK_DDR_MBA_EVENT_N                      , 8   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR_MBA_EVENT_N );
+REG64_FLD( MCA_MBACALFIR_MASK_WRQ_RRQ_HANG_ERR                     , 9   , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_WRQ_RRQ_HANG_ERR );
+REG64_FLD( MCA_MBACALFIR_MASK_SM_1HOT_ERR                          , 10  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_SM_1HOT_ERR );
+REG64_FLD( MCA_MBACALFIR_MASK_ASYNC_IF_ERROR                       , 11  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ASYNC_IF_ERROR );
+REG64_FLD( MCA_MBACALFIR_MASK_CMD_PARITY_ERROR                     , 12  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_CMD_PARITY_ERROR );
+REG64_FLD( MCA_MBACALFIR_MASK_MBACALFIRQ_PORT_FAIL                 , 13  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MBACALFIRQ_PORT_FAIL );
+REG64_FLD( MCA_MBACALFIR_MASK_MBACALFIRQ_RCD_CAL_PARITY_ERROR      , 14  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MBACALFIRQ_RCD_CAL_PARITY_ERROR );
+REG64_FLD( MCA_MBACALFIR_MASK_INTERNAL_SCOM_ERROR                  , 15  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_SCOM_ERROR );
+REG64_FLD( MCA_MBACALFIR_MASK_INTERNAL_SCOM_ERROR_COPY             , 16  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_SCOM_ERROR_COPY );
+
+REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_ENABLE                         , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REFRESH_ENABLE );
+REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT       , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT );
+REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN   , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN );
+REG64_FLD( MCA_MBAREF0Q_CFG_PER_BANK_REFRESH                       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PER_BANK_REFRESH );
+REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_DEBUG_SELECT                   , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REFRESH_DEBUG_SELECT );
+REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD             , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD );
+REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD_LEN         , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD_LEN );
+REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_INTERVAL                       , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REFRESH_INTERVAL );
+REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_INTERVAL_LEN                   , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REFRESH_INTERVAL_LEN );
+REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL                 , 19  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REFRESH_RESET_INTERVAL );
+REG64_FLD( MCA_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL_LEN             , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REFRESH_RESET_INTERVAL_LEN );
+REG64_FLD( MCA_MBAREF0Q_CFG_TRFC                                   , 30  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TRFC   );
+REG64_FLD( MCA_MBAREF0Q_CFG_TRFC_LEN                               , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TRFC_LEN );
+REG64_FLD( MCA_MBAREF0Q_CFG_REFR_TSV_STACK                         , 40  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REFR_TSV_STACK );
+REG64_FLD( MCA_MBAREF0Q_CFG_REFR_TSV_STACK_LEN                     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REFR_TSV_STACK_LEN );
+REG64_FLD( MCA_MBAREF0Q_CFG_REFR_CHECK_INTERVAL                    , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REFR_CHECK_INTERVAL );
+REG64_FLD( MCA_MBAREF0Q_CFG_REFR_CHECK_INTERVAL_LEN                , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REFR_CHECK_INTERVAL_LEN );
+REG64_FLD( MCA_MBAREF0Q_CFG_TRFC_STACK_GATE_ALL_REF                , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TRFC_STACK_GATE_ALL_REF );
+REG64_FLD( MCA_MBAREF0Q_RESERVED_62_63                             , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_62_63 );
+REG64_FLD( MCA_MBAREF0Q_RESERVED_62_63_LEN                         , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_62_63_LEN );
+
+REG64_FLD( MCA_MBAREFAQ_CFG_STATIC_IDLE_DLY                        , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_STATIC_IDLE_DLY );
+REG64_FLD( MCA_MBAREFAQ_CFG_STATIC_IDLE_DLY_LEN                    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_STATIC_IDLE_DLY_LEN );
+REG64_FLD( MCA_MBAREFAQ_CFG_LP_SUB_CNT                             , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_LP_SUB_CNT );
+REG64_FLD( MCA_MBAREFAQ_CFG_LP_SUB_CNT_LEN                         , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_LP_SUB_CNT_LEN );
+REG64_FLD( MCA_MBAREFAQ_CFG_REFRESH_HP_RANK_BLOCK_ENABLE           , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REFRESH_HP_RANK_BLOCK_ENABLE );
+REG64_FLD( MCA_MBAREFAQ_RESERVED_7_9                               , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_7_9 );
+REG64_FLD( MCA_MBAREFAQ_RESERVED_7_9_LEN                           , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_7_9_LEN );
+REG64_FLD( MCA_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY                     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REF_BLOCK_STOP_DLY );
+REG64_FLD( MCA_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY_LEN                 , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_REF_BLOCK_STOP_DLY_LEN );
+
+REG64_FLD( MCA_MBARPC0Q_RESERVED_0_1                               , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_1 );
+REG64_FLD( MCA_MBARPC0Q_RESERVED_0_1_LEN                           , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_1_LEN );
+REG64_FLD( MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE                 , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MIN_MAX_DOMAINS_ENABLE );
+REG64_FLD( MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS                        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MIN_MAX_DOMAINS );
+REG64_FLD( MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_LEN                    , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MIN_MAX_DOMAINS_LEN );
+REG64_FLD( MCA_MBARPC0Q_CFG_PUP_AVAIL                              , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUP_AVAIL );
+REG64_FLD( MCA_MBARPC0Q_CFG_PUP_AVAIL_LEN                          , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUP_AVAIL_LEN );
+REG64_FLD( MCA_MBARPC0Q_CFG_PDN_PUP                                , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PDN_PUP );
+REG64_FLD( MCA_MBARPC0Q_CFG_PDN_PUP_LEN                            , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PDN_PUP_LEN );
+REG64_FLD( MCA_MBARPC0Q_CFG_PUP_PDN                                , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUP_PDN );
+REG64_FLD( MCA_MBARPC0Q_CFG_PUP_PDN_LEN                            , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUP_PDN_LEN );
+REG64_FLD( MCA_MBARPC0Q_RESERVED_21                                , 21  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_21 );
+REG64_FLD( MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_ENABLE            , 22  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MIN_DOMAIN_REDUCTION_ENABLE );
+REG64_FLD( MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME              , 23  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME );
+REG64_FLD( MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN          , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN );
+REG64_FLD( MCA_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE         , 33  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE );
+REG64_FLD( MCA_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME           , 34  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME );
+REG64_FLD( MCA_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN       , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN );
+REG64_FLD( MCA_MBARPC0Q_CFG_FORCE_SPARE_PUP                        , 42  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FORCE_SPARE_PUP );
+REG64_FLD( MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_CNT_REFR_INT      , 43  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MIN_DOMAIN_REDUCTION_CNT_REFR_INT );
+REG64_FLD( MCA_MBARPC0Q_CFG_EMER_MIN_MAX_DOMAIN                    , 44  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EMER_MIN_MAX_DOMAIN );
+REG64_FLD( MCA_MBARPC0Q_CFG_EMER_MIN_MAX_DOMAIN_LEN                , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EMER_MIN_MAX_DOMAIN_LEN );
+REG64_FLD( MCA_MBARPC0Q_CFG_PUP_ALL_WRITES_PENDING                 , 47  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUP_ALL_WRITES_PENDING );
+REG64_FLD( MCA_MBARPC0Q_CFG_ALWAYS_WAIT_ACT_TIME                   , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ALWAYS_WAIT_ACT_TIME );
+REG64_FLD( MCA_MBARPC0Q_RESERVED_49_63                             , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_49_63 );
+REG64_FLD( MCA_MBARPC0Q_RESERVED_49_63_LEN                         , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_49_63_LEN );
+
+REG64_FLD( MCA_MBASTR0Q_CFG_STR_ENABLE                             , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_STR_ENABLE );
+REG64_FLD( MCA_MBASTR0Q_CFG_DIS_CLK_IN_STR                         , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DIS_CLK_IN_STR );
+REG64_FLD( MCA_MBASTR0Q_CFG_ENTER_STR_TIME                         , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ENTER_STR_TIME );
+REG64_FLD( MCA_MBASTR0Q_CFG_ENTER_STR_TIME_LEN                     , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ENTER_STR_TIME_LEN );
+REG64_FLD( MCA_MBASTR0Q_CFG_TCKESR                                 , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TCKESR );
+REG64_FLD( MCA_MBASTR0Q_CFG_TCKESR_LEN                             , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TCKESR_LEN );
+REG64_FLD( MCA_MBASTR0Q_CFG_TCKSRE                                 , 17  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TCKSRE );
+REG64_FLD( MCA_MBASTR0Q_CFG_TCKSRE_LEN                             , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TCKSRE_LEN );
+REG64_FLD( MCA_MBASTR0Q_CFG_TCKSRX                                 , 22  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TCKSRX );
+REG64_FLD( MCA_MBASTR0Q_CFG_TCKSRX_LEN                             , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TCKSRX_LEN );
+REG64_FLD( MCA_MBASTR0Q_CFG_TXSDLL                                 , 27  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TXSDLL );
+REG64_FLD( MCA_MBASTR0Q_CFG_TXSDLL_LEN                             , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TXSDLL_LEN );
+REG64_FLD( MCA_MBASTR0Q_CFG_TRFC_COUNTER_DIS                       , 38  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TRFC_COUNTER_DIS );
+REG64_FLD( MCA_MBASTR0Q_CFG_TRFC_COUNTER_DIS_LEN                   , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TRFC_COUNTER_DIS_LEN );
+REG64_FLD( MCA_MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL                  , 46  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SAFE_REFRESH_INTERVAL );
+REG64_FLD( MCA_MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL_LEN              , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SAFE_REFRESH_INTERVAL_LEN );
+REG64_FLD( MCA_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL                  , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL );
+REG64_FLD( MCA_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL_LEN              , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL_LEN );
+REG64_FLD( MCA_MBASTR0Q_RESERVED_61_63                             , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_61_63 );
+REG64_FLD( MCA_MBASTR0Q_RESERVED_61_63_LEN                         , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_61_63_LEN );
+
+REG64_FLD( MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBAUER0Q_RESERVED_38_39                          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39 );
+REG64_FLD( MCBIST_MBAUER0Q_RESERVED_38_39_LEN                      , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39_LEN );
+
+REG64_FLD( MCBIST_MBAUER1Q_PORT_1_MAINLINE_AUE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBAUER1Q_PORT_1_MAINLINE_AUE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBAUER1Q_RESERVED_38_39                          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39 );
+REG64_FLD( MCBIST_MBAUER1Q_RESERVED_38_39_LEN                      , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39_LEN );
+
+REG64_FLD( MCBIST_MBAUER2Q_PORT_2_MAINLINE_AUE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBAUER2Q_PORT_2_MAINLINE_AUE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBAUER2Q_RESERVED_38_39                          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39 );
+REG64_FLD( MCBIST_MBAUER2Q_RESERVED_38_39_LEN                      , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39_LEN );
+
+REG64_FLD( MCBIST_MBAUER3Q_PORT_3_MAINLINE_AUE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBAUER3Q_PORT_3_MAINLINE_AUE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBAUER3Q_RESERVED_38_39                          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39 );
+REG64_FLD( MCBIST_MBAUER3Q_RESERVED_38_39_LEN                      , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39_LEN );
+
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_INTERVAL_TMR0_ENABLE              , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_INTERVAL_TMR0_ENABLE );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_TIME_BASE_TMR0                        , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TIME_BASE_TMR0 );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_TIME_BASE_TMR0_LEN                    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TIME_BASE_TMR0_LEN );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_INTERVAL_COUNTER_TMR0                 , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_INTERVAL_COUNTER_TMR0 );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_INTERVAL_COUNTER_TMR0_LEN             , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_INTERVAL_COUNTER_TMR0_LEN );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_ENABLE                  , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_CAL1_ENABLE );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_TYPE                    , 13  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_CAL1_TYPE );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_TYPE_LEN                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_CAL1_TYPE_LEN );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL1_DDR_DONE                , 17  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_CAL1_DDR_DONE );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_ENABLE                  , 18  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_CAL2_ENABLE );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_TYPE                    , 19  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_CAL2_TYPE );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_TYPE_LEN                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_CAL2_TYPE_LEN );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL2_DDR_DONE                , 23  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_CAL2_DDR_DONE );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_ENABLE                  , 24  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_CAL3_ENABLE );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_TYPE                    , 25  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_CAL3_TYPE );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_TYPE_LEN                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_CAL3_TYPE_LEN );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_CAL3_DDR_DONE                , 29  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_CAL3_DDR_DONE );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_Z_SYNC                       , 30  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_Z_SYNC );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_Z_SYNC_LEN                   , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_Z_SYNC_LEN );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR                , 39  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR_LEN            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_LEN );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR_TB             , 47  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_TMR_TB_LEN         , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB_LEN );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_DDR_RESET_ENABLE             , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_DDR_RESET_ENABLE );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_TMR0_SINGLE_RANK                  , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR0_SINGLE_RANK );
+REG64_FLD( MCA_MBA_CAL0Q_RESERVED_51                               , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_51 );
+REG64_FLD( MCA_MBA_CAL0Q_INJECT_1HOT_SM_ERROR                      , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_INJECT_1HOT_SM_ERROR );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_SINGLE_PORT_MODE                  , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_SINGLE_PORT_MODE );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_CAL_SINGLE_PORT_MODE_LEN              , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_SINGLE_PORT_MODE_LEN );
+REG64_FLD( MCA_MBA_CAL0Q_DBG_BUS_BIT                               , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_BUS_BIT );
+REG64_FLD( MCA_MBA_CAL0Q_RESET_RECOVER                             , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESET_RECOVER );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_RANK_SM_STALL_DISABLE                 , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK_SM_STALL_DISABLE );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_ENABLE_SPEC_ATTN                      , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ENABLE_SPEC_ATTN );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_ENABLE_HOST_ATTN                      , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ENABLE_HOST_ATTN );
+REG64_FLD( MCA_MBA_CAL0Q_CFG_DISABLE_RESET_RECOVER                 , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DISABLE_RESET_RECOVER );
+REG64_FLD( MCA_MBA_CAL0Q_RESERVED_62_63                            , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_62_63 );
+REG64_FLD( MCA_MBA_CAL0Q_RESERVED_62_63_LEN                        , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_62_63_LEN );
+
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_INTERVAL_TMR1_ENABLE              , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_INTERVAL_TMR1_ENABLE );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_TIME_BASE_TMR1                        , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TIME_BASE_TMR1 );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_TIME_BASE_TMR1_LEN                    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TIME_BASE_TMR1_LEN );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_INTERVAL_COUNTER_TMR1                 , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_INTERVAL_COUNTER_TMR1 );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_INTERVAL_COUNTER_TMR1_LEN             , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_INTERVAL_COUNTER_TMR1_LEN );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_ENABLE                  , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR1_CAL1_ENABLE );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_TYPE                    , 13  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR1_CAL1_TYPE );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_TYPE_LEN                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR1_CAL1_TYPE_LEN );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL1_DDR_DONE                , 17  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR1_CAL1_DDR_DONE );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_ENABLE                  , 18  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR1_CAL2_ENABLE );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_TYPE                    , 19  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR1_CAL2_TYPE );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_TYPE_LEN                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR1_CAL2_TYPE_LEN );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL2_DDR_DONE                , 23  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR1_CAL2_DDR_DONE );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_ENABLE                  , 24  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR1_CAL3_ENABLE );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_TYPE                    , 25  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR1_CAL3_TYPE );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_TYPE_LEN                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR1_CAL3_TYPE_LEN );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_CAL3_DDR_DONE                , 29  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR1_CAL3_DDR_DONE );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_Z_SYNC                       , 30  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR1_Z_SYNC );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_Z_SYNC_LEN                   , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR1_Z_SYNC_LEN );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_TMR1_SINGLE_RANK                  , 39  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR1_SINGLE_RANK );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_RANK_ENABLE                       , 40  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_RANK_ENABLE );
+REG64_FLD( MCA_MBA_CAL1Q_CFG_CAL_RANK_ENABLE_LEN                   , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_RANK_ENABLE_LEN );
+REG64_FLD( MCA_MBA_CAL1Q_RESERVED_48_63                            , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48_63 );
+REG64_FLD( MCA_MBA_CAL1Q_RESERVED_48_63_LEN                        , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48_63_LEN );
+
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_INTERVAL_TMR2_ENABLE              , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_INTERVAL_TMR2_ENABLE );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_TIME_BASE_TMR2                        , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TIME_BASE_TMR2 );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_TIME_BASE_TMR2_LEN                    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TIME_BASE_TMR2_LEN );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_INTERVAL_COUNTER_TMR2                 , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_INTERVAL_COUNTER_TMR2 );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_INTERVAL_COUNTER_TMR2_LEN             , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_INTERVAL_COUNTER_TMR2_LEN );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_ENABLE                  , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_CAL1_ENABLE );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_TYPE                    , 13  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_CAL1_TYPE );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_TYPE_LEN                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_CAL1_TYPE_LEN );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL1_DDR_DONE                , 17  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_CAL1_DDR_DONE );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_ENABLE                  , 18  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_CAL2_ENABLE );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_TYPE                    , 19  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_CAL2_TYPE );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_TYPE_LEN                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_CAL2_TYPE_LEN );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL2_DDR_DONE                , 23  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_CAL2_DDR_DONE );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_ENABLE                  , 24  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_CAL3_ENABLE );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_TYPE                    , 25  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_CAL3_TYPE );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_TYPE_LEN                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_CAL3_TYPE_LEN );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_CAL3_DDR_DONE                , 29  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_CAL3_DDR_DONE );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_Z_SYNC                       , 30  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_Z_SYNC );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_Z_SYNC_LEN                   , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_Z_SYNC_LEN );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_SINGLE_RANK                  , 39  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_SINGLE_RANK );
+REG64_FLD( MCA_MBA_CAL2Q_CFG_CAL_TMR2_WAT_EVENT_ENABLE             , 40  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CAL_TMR2_WAT_EVENT_ENABLE );
+REG64_FLD( MCA_MBA_CAL2Q_RESERVED_41_63                            , 41  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_41_63 );
+REG64_FLD( MCA_MBA_CAL2Q_RESERVED_41_63_LEN                        , 23  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_41_63_LEN );
+
+REG64_FLD( MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_TB                        , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_INTERNAL_ZQ_TB );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_TB_LEN                    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_INTERNAL_ZQ_TB_LEN );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_LENGTH                    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_INTERNAL_ZQ_LENGTH );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_INTERNAL_ZQ_LENGTH_LEN                , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_INTERNAL_ZQ_LENGTH_LEN );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_TB                        , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EXTERNAL_ZQ_TB );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_TB_LEN                    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EXTERNAL_ZQ_TB_LEN );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_LENGTH                    , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EXTERNAL_ZQ_LENGTH );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_EXTERNAL_ZQ_LENGTH_LEN                , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EXTERNAL_ZQ_LENGTH_LEN );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_TB                       , 20  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RDCLK_SYSCLK_TB );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_TB_LEN                   , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RDCLK_SYSCLK_TB_LEN );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_LENGTH                   , 22  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RDCLK_SYSCLK_LENGTH );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_RDCLK_SYSCLK_LENGTH_LEN               , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RDCLK_SYSCLK_LENGTH_LEN );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_TB                      , 30  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DQS_ALIGNMENT_TB );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_TB_LEN                  , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DQS_ALIGNMENT_TB_LEN );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_LENGTH                  , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DQS_ALIGNMENT_LENGTH );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_DQS_ALIGNMENT_LENGTH_LEN              , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DQS_ALIGNMENT_LENGTH_LEN );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_MPR_READEYE_TB                        , 40  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MPR_READEYE_TB );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_MPR_READEYE_TB_LEN                    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MPR_READEYE_TB_LEN );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_MPR_READEYE_LENGTH                    , 42  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MPR_READEYE_LENGTH );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_MPR_READEYE_LENGTH_LEN                , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MPR_READEYE_LENGTH_LEN );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_TB                       , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ALL_PERIODIC_TB );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_TB_LEN                   , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ALL_PERIODIC_TB_LEN );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_LENGTH                   , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ALL_PERIODIC_LENGTH );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_ALL_PERIODIC_LENGTH_LEN               , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ALL_PERIODIC_LENGTH_LEN );
+REG64_FLD( MCA_MBA_CAL3Q_CFG_FREEZE_ON_PARITY_ERROR_DIS            , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FREEZE_ON_PARITY_ERROR_DIS );
+REG64_FLD( MCA_MBA_CAL3Q_RESERVED_61_63                            , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_61_63 );
+REG64_FLD( MCA_MBA_CAL3Q_RESERVED_61_63_LEN                        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_61_63_LEN );
+
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_ENABLE                        , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_ENABLE );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL0                          , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL0 );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL0_LEN                      , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL0_LEN );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL1                          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL1 );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL1_LEN                      , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL1_LEN );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL2                          , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL2 );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL2_LEN                      , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL2_LEN );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL3                          , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL3 );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL3_LEN                      , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL3_LEN );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL4                          , 13  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL4 );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL4_LEN                      , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL4_LEN );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL5                          , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL5 );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL5_LEN                      , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL5_LEN );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL6                          , 19  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL6 );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL6_LEN                      , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL6_LEN );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL7                          , 22  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL7 );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL7_LEN                      , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL7_LEN );
+REG64_FLD( MCA_MBA_DBG0Q_RESERVED_25_33                            , 25  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_25_33 );
+REG64_FLD( MCA_MBA_DBG0Q_RESERVED_25_33_LEN                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_25_33_LEN );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL_OTHER_SRQ                 , 34  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL_OTHER_SRQ );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_DBG_SRQ_SEL_OTHER_SRQ_LEN             , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DBG_SRQ_SEL_OTHER_SRQ_LEN );
+REG64_FLD( MCA_MBA_DBG0Q_RESERVED_42_47                            , 42  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_42_47 );
+REG64_FLD( MCA_MBA_DBG0Q_RESERVED_42_47_LEN                        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_42_47_LEN );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_RRQ_GT                       , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_FARB_RRQ_GT );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_RRQ_GT_LEN                   , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_FARB_RRQ_GT_LEN );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_WRQ_GT                       , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_FARB_WRQ_GT );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_WRQ_GT_LEN                   , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_FARB_WRQ_GT_LEN );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_REF_GT                       , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_FARB_REF_GT );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_REF_GT_LEN                   , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_FARB_REF_GT_LEN );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_CAL_GT                       , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_FARB_CAL_GT );
+REG64_FLD( MCA_MBA_DBG0Q_CFG_WAT_FARB_CAL_GT_LEN                   , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_FARB_CAL_GT_LEN );
+
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_FORCE_WR_ENTRY0_HP                , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_FORCE_WR_ENTRY0_HP );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_FORCE_WR_ENTRY0_HP_LEN            , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_FORCE_WR_ENTRY0_HP_LEN );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_FORCE_RD_ENTRY0_HP                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_FORCE_RD_ENTRY0_HP );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_FORCE_RD_ENTRY0_HP_LEN            , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_FORCE_RD_ENTRY0_HP_LEN );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_FP_DIS                            , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_FP_DIS );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_FP_DIS_LEN                        , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_FP_DIS_LEN );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_DIS_RD_PG                         , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_DIS_RD_PG );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_DIS_RD_PG_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_DIS_RD_PG_LEN );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_DIS_WR_PG                         , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_DIS_WR_PG );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_DIS_WR_PG_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_DIS_WR_PG_LEN );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_PUP_ALL                           , 20  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PUP_ALL );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_PUP_ALL_LEN                       , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PUP_ALL_LEN );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_EXIT_STR                          , 24  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EXIT_STR );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_EXIT_STR_LEN                      , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EXIT_STR_LEN );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_REF_HP                            , 28  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_REF_HP );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_REF_HP_LEN                        , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_REF_HP_LEN );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_REF_SYNC                          , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_REF_SYNC );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_REF_SYNC_LEN                      , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_REF_SYNC_LEN );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_REF_SAFE                          , 36  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_REF_SAFE );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_REF_SAFE_LEN                      , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_REF_SAFE_LEN );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_CAL_SYNC                          , 40  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_CAL_SYNC );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_CAL_SYNC_LEN                      , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_CAL_SYNC_LEN );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_RRQ_MNT_GT                        , 44  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_RRQ_MNT_GT );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_RRQ_MNT_GT_LEN                    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_RRQ_MNT_GT_LEN );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_WRQ_MNT_GT                        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_WRQ_MNT_GT );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_WRQ_MNT_GT_LEN                    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_WRQ_MNT_GT_LEN );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_SET_FIR                           , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_SET_FIR );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_SET_FIR_LEN                       , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_SET_FIR_LEN );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_EMER_TH                           , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EMER_TH );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_EMER_TH_LEN                       , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EMER_TH_LEN );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_START_RECOVERY                    , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_START_RECOVERY );
+REG64_FLD( MCA_MBA_DBG1Q_CFG_WAT_START_RECOVERY_LEN                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_START_RECOVERY_LEN );
+
+REG64_FLD( MCA_MBA_DSM0Q_CFG_RODT_START_DLY                        , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RODT_START_DLY );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_RODT_START_DLY_LEN                    , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RODT_START_DLY_LEN );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_RODT_END_DLY                          , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RODT_END_DLY );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_RODT_END_DLY_LEN                      , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RODT_END_DLY_LEN );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_WODT_START_DLY                        , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WODT_START_DLY );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_WODT_START_DLY_LEN                    , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WODT_START_DLY_LEN );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_WODT_END_DLY                          , 18  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WODT_END_DLY );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_WODT_END_DLY_LEN                      , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WODT_END_DLY_LEN );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_WRDONE_DLY                            , 24  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRDONE_DLY );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_WRDONE_DLY_LEN                        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRDONE_DLY_LEN );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_WRDATA_DLY                            , 30  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRDATA_DLY );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_WRDATA_DLY_LEN                        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRDATA_DLY_LEN );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_RDTAG_DLY                             , 36  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RDTAG_DLY );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_RDTAG_DLY_LEN                         , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RDTAG_DLY_LEN );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_RDTAG_MBX_CYCLE                       , 42  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RDTAG_MBX_CYCLE );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_RODT_BC4_END_DLY                      , 43  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RODT_BC4_END_DLY );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_RODT_BC4_END_DLY_LEN                  , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RODT_BC4_END_DLY_LEN );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_WODT_BC4_END_DLY                      , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WODT_BC4_END_DLY );
+REG64_FLD( MCA_MBA_DSM0Q_CFG_WODT_BC4_END_DLY_LEN                  , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WODT_BC4_END_DLY_LEN );
+REG64_FLD( MCA_MBA_DSM0Q_RESERVED_55_63                            , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_55_63 );
+REG64_FLD( MCA_MBA_DSM0Q_RESERVED_55_63_LEN                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_55_63_LEN );
+
+REG64_FLD( MCA_MBA_ERR_REPORTQ_WRQ_HANG                            , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRQ_HANG   );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_RRQ_HANG                            , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RRQ_HANG   );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_DSM_PE                              , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DSM_PE     );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_TMR_PE                              , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_TMR_PE     );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_RRQ_PE                              , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RRQ_PE     );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_WRQ_PE                              , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRQ_PE     );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_FARB_PE                             , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_FARB_PE    );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_PC_PE                               , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_PE      );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL0_PE                             , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CAL0_PE    );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL1_PE                             , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CAL1_PE    );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL2_PE                             , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CAL2_PE    );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL3_PE                             , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CAL3_PE    );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_DDR_IF_SM_1HOT                      , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DDR_IF_SM_1HOT );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_CAL_SM_1HOT                         , 13  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CAL_SM_1HOT );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_RANK_SM_1HOT                        , 14  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RANK_SM_1HOT );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_15                         , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_15 );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_PC_CAL_PCFSM_1HOT                   , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_CAL_PCFSM_1HOT );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_FARB_CAL_RECVFSM_1HOT               , 17  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_FARB_CAL_RECVFSM_1HOT );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_18_23                      , 18  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_18_23 );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_18_23_LEN                  , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_18_23_LEN );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_RCMD_ASYNC_IF                       , 24  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RCMD_ASYNC_IF );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_PF_PROMOTE_ASYNC_IF                 , 25  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PF_PROMOTE_ASYNC_IF );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_26                         , 26  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_26 );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_FARB_CMD_PE_HOLD_OUT                , 27  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_FARB_CMD_PE_HOLD_OUT );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_DSM_CMD_PE_HOLD_OUT                 , 28  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DSM_CMD_PE_HOLD_OUT );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_29_30                      , 29  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_29_30 );
+REG64_FLD( MCA_MBA_ERR_REPORTQ_RESERVED_29_30_LEN                  , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_29_30_LEN );
+
+REG64_FLD( MCA_MBA_FARB0Q_CFG_MISR_BLOCK                           , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MISR_BLOCK );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_MISR_BLOCK_LEN                       , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MISR_BLOCK_LEN );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_MISR_FEEDBACK_ENABLE                 , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MISR_FEEDBACK_ENABLE );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_2N_ADDR                              , 17  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_2N_ADDR );
+REG64_FLD( MCA_MBA_FARB0Q_RESERVED_18_19                           , 18  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_18_19 );
+REG64_FLD( MCA_MBA_FARB0Q_RESERVED_18_19_LEN                       , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_18_19_LEN );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_ACT_SAME_RANK_HOLD_TIME              , 20  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ACT_SAME_RANK_HOLD_TIME );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_ACT_SAME_RANK_HOLD_TIME_LEN          , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ACT_SAME_RANK_HOLD_TIME_LEN );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_MAX_READS_IN_A_ROW                   , 24  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MAX_READS_IN_A_ROW );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_MAX_READS_IN_A_ROW_LEN               , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MAX_READS_IN_A_ROW_LEN );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_MAX_WRITES_IN_A_ROW                  , 31  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MAX_WRITES_IN_A_ROW );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_MAX_WRITES_IN_A_ROW_LEN              , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MAX_WRITES_IN_A_ROW_LEN );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_PARITY_AFTER_CMD                     , 38  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PARITY_AFTER_CMD );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_WEN                , 39  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_INJECT_PARITY_ERR_WEN );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_ADDR5              , 40  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_INJECT_PARITY_ERR_ADDR5 );
+REG64_FLD( MCA_MBA_FARB0Q_RESERVED_41_42                           , 41  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_41_42 );
+REG64_FLD( MCA_MBA_FARB0Q_RESERVED_41_42_LEN                       , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_41_42_LEN );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_PARITY_DETECT_TIME                   , 43  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PARITY_DETECT_TIME );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_PARITY_DETECT_TIME_LEN               , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PARITY_DETECT_TIME_LEN );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME                  , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RCD_PROTECTION_TIME );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME_LEN              , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RCD_PROTECTION_TIME_LEN );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_DISABLE_RCD_RECOVERY                 , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DISABLE_RCD_RECOVERY );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_OE_ALWAYS_ON                         , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_OE_ALWAYS_ON );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_FARB_CLOSE_ALL_PAGES                 , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FARB_CLOSE_ALL_PAGES );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_PORT_FAIL_DISABLE                    , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PORT_FAIL_DISABLE );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_OE_ALL_CKE_POWERED_DOWN              , 58  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_OE_ALL_CKE_POWERED_DOWN );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_CONSTANT           , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_INJECT_PARITY_ERR_CONSTANT );
+REG64_FLD( MCA_MBA_FARB0Q_RESERVED_60_61                           , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_60_61 );
+REG64_FLD( MCA_MBA_FARB0Q_RESERVED_60_61_LEN                       , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_60_61_LEN );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_OPT_RD_SIZE                          , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_OPT_RD_SIZE );
+REG64_FLD( MCA_MBA_FARB0Q_CFG_OPT_RD_SIZE_LEN                      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_OPT_RD_SIZE_LEN );
+
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S0_CID                         , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S0_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S0_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S0_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S1_CID                         , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S1_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S1_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S1_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S2_CID                         , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S2_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S2_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S2_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S3_CID                         , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S3_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S3_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S3_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S4_CID                         , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S4_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S4_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S4_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S5_CID                         , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S5_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S5_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S5_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S6_CID                         , 18  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S6_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S6_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S6_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S7_CID                         , 21  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S7_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT0_S7_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT0_S7_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S0_CID                         , 24  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S0_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S0_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S0_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S1_CID                         , 27  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S1_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S1_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S1_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S2_CID                         , 30  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S2_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S2_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S2_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S3_CID                         , 33  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S3_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S3_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S3_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S4_CID                         , 36  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S4_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S4_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S4_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S5_CID                         , 39  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S5_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S5_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S5_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S6_CID                         , 42  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S6_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S6_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S6_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S7_CID                         , 45  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S7_CID );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_SLOT1_S7_CID_LEN                     , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SLOT1_S7_CID_LEN );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_DIS_SMDR                             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DIS_SMDR );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_DDR4_PARITY_ON_CID_DIS               , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DDR4_PARITY_ON_CID_DIS );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_RSV0                                 , 50  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RSV0   );
+REG64_FLD( MCA_MBA_FARB1Q_CFG_RSV0_LEN                             , 14  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RSV0_LEN );
+
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK0_RD_ODT                         , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK0_RD_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK0_RD_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK0_RD_ODT_LEN );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK1_RD_ODT                         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK1_RD_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK1_RD_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK1_RD_ODT_LEN );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK2_RD_ODT                         , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK2_RD_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK2_RD_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK2_RD_ODT_LEN );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK3_RD_ODT                         , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK3_RD_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK3_RD_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK3_RD_ODT_LEN );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK4_RD_ODT                         , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK4_RD_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK4_RD_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK4_RD_ODT_LEN );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK5_RD_ODT                         , 20  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK5_RD_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK5_RD_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK5_RD_ODT_LEN );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK6_RD_ODT                         , 24  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK6_RD_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK6_RD_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK6_RD_ODT_LEN );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK7_RD_ODT                         , 28  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK7_RD_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK7_RD_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK7_RD_ODT_LEN );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK0_WR_ODT                         , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK0_WR_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK0_WR_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK0_WR_ODT_LEN );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK1_WR_ODT                         , 36  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK1_WR_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK1_WR_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK1_WR_ODT_LEN );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK2_WR_ODT                         , 40  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK2_WR_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK2_WR_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK2_WR_ODT_LEN );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK3_WR_ODT                         , 44  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK3_WR_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK3_WR_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK3_WR_ODT_LEN );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK4_WR_ODT                         , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK4_WR_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK4_WR_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK4_WR_ODT_LEN );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK5_WR_ODT                         , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK5_WR_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK5_WR_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK5_WR_ODT_LEN );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK6_WR_ODT                         , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK6_WR_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK6_WR_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK6_WR_ODT_LEN );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK7_WR_ODT                         , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK7_WR_ODT );
+REG64_FLD( MCA_MBA_FARB2Q_CFG_RANK7_WR_ODT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANK7_WR_ODT_LEN );
+
+REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_N_PER_SLOT                        , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NM_N_PER_SLOT );
+REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_N_PER_SLOT_LEN                    , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NM_N_PER_SLOT_LEN );
+REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_N_PER_PORT                        , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NM_N_PER_PORT );
+REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_N_PER_PORT_LEN                    , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NM_N_PER_PORT_LEN );
+REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_M                                 , 31  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NM_M   );
+REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_M_LEN                             , 14  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NM_M_LEN );
+REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_RAS_WEIGHT                        , 45  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NM_RAS_WEIGHT );
+REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_RAS_WEIGHT_LEN                    , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NM_RAS_WEIGHT_LEN );
+REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_CAS_WEIGHT                        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NM_CAS_WEIGHT );
+REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_CAS_WEIGHT_LEN                    , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NM_CAS_WEIGHT_LEN );
+REG64_FLD( MCA_MBA_FARB3Q_RESERVED_51                              , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_51 );
+REG64_FLD( MCA_MBA_FARB3Q_RESERVED_52                              , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52 );
+REG64_FLD( MCA_MBA_FARB3Q_CFG_NM_CHANGE_AFTER_SYNC                 , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NM_CHANGE_AFTER_SYNC );
+REG64_FLD( MCA_MBA_FARB3Q_RESERVED_54_63                           , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_54_63 );
+REG64_FLD( MCA_MBA_FARB3Q_RESERVED_54_63_LEN                       , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_54_63_LEN );
+
+REG64_FLD( MCA_MBA_FARB4Q_CFG_NOISE_WAIT_TIME                      , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NOISE_WAIT_TIME );
+REG64_FLD( MCA_MBA_FARB4Q_CFG_NOISE_WAIT_TIME_LEN                  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NOISE_WAIT_TIME_LEN );
+REG64_FLD( MCA_MBA_FARB4Q_CFG_PRECHARGE_WAIT_TIME                  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRECHARGE_WAIT_TIME );
+REG64_FLD( MCA_MBA_FARB4Q_CFG_PRECHARGE_WAIT_TIME_LEN              , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRECHARGE_WAIT_TIME_LEN );
+REG64_FLD( MCA_MBA_FARB4Q_CFG_SIM_FAST_NOISE_WINDOW                , 22  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SIM_FAST_NOISE_WINDOW );
+REG64_FLD( MCA_MBA_FARB4Q_RESERVED_23_26                           , 23  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_23_26 );
+REG64_FLD( MCA_MBA_FARB4Q_RESERVED_23_26_LEN                       , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_23_26_LEN );
+REG64_FLD( MCA_MBA_FARB4Q_EMERGENCY_N                              , 27  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EMERGENCY_N );
+REG64_FLD( MCA_MBA_FARB4Q_EMERGENCY_N_LEN                          , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EMERGENCY_N_LEN );
+REG64_FLD( MCA_MBA_FARB4Q_EMERGENCY_M                              , 42  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EMERGENCY_M );
+REG64_FLD( MCA_MBA_FARB4Q_EMERGENCY_M_LEN                          , 14  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EMERGENCY_M_LEN );
+REG64_FLD( MCA_MBA_FARB4Q_RESERVED_56_63                           , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_63 );
+REG64_FLD( MCA_MBA_FARB4Q_RESERVED_56_63_LEN                       , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_63_LEN );
+
+REG64_FLD( MCA_MBA_FARB5Q_CFG_DDR_DPHY_NCLK                        , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DDR_DPHY_NCLK );
+REG64_FLD( MCA_MBA_FARB5Q_CFG_DDR_DPHY_NCLK_LEN                    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DDR_DPHY_NCLK_LEN );
+REG64_FLD( MCA_MBA_FARB5Q_CFG_DDR_DPHY_PCLK                        , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DDR_DPHY_PCLK );
+REG64_FLD( MCA_MBA_FARB5Q_CFG_DDR_DPHY_PCLK_LEN                    , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DDR_DPHY_PCLK_LEN );
+REG64_FLD( MCA_MBA_FARB5Q_CFG_DDR_RESETN                           , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DDR_RESETN );
+REG64_FLD( MCA_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL                     , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CCS_ADDR_MUX_SEL );
+REG64_FLD( MCA_MBA_FARB5Q_CFG_CCS_INST_RESET_ENABLE                , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CCS_INST_RESET_ENABLE );
+REG64_FLD( MCA_MBA_FARB5Q_CFG_GP_BIT_3_ENABLE                      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_GP_BIT_3_ENABLE );
+REG64_FLD( MCA_MBA_FARB5Q_CFG_FORCE_MCLK_LOW_N                     , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FORCE_MCLK_LOW_N );
+REG64_FLD( MCA_MBA_FARB5Q_RESERVED_56_63                           , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_63 );
+REG64_FLD( MCA_MBA_FARB5Q_RESERVED_56_63_LEN                       , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_63_LEN );
+
+REG64_FLD( MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT                          , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CFG_BW_SNAPSHOT );
+REG64_FLD( MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT_LEN                      , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CFG_BW_SNAPSHOT_LEN );
+REG64_FLD( MCA_MBA_FARB6Q_CFG_CKE_PUP_STATE                        , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CFG_CKE_PUP_STATE );
+REG64_FLD( MCA_MBA_FARB6Q_CFG_CKE_PUP_STATE_LEN                    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CFG_CKE_PUP_STATE_LEN );
+REG64_FLD( MCA_MBA_FARB6Q_CFG_STR_STATE                            , 14  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CFG_STR_STATE );
+REG64_FLD( MCA_MBA_FARB6Q_CFG_RRQ_DEPTH                            , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CFG_RRQ_DEPTH );
+REG64_FLD( MCA_MBA_FARB6Q_CFG_RRQ_DEPTH_LEN                        , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CFG_RRQ_DEPTH_LEN );
+REG64_FLD( MCA_MBA_FARB6Q_CFG_WRQ_DEPTH                            , 20  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CFG_WRQ_DEPTH );
+REG64_FLD( MCA_MBA_FARB6Q_CFG_WRQ_DEPTH_LEN                        , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CFG_WRQ_DEPTH_LEN );
+REG64_FLD( MCA_MBA_FARB6Q_CFG_RCD_PARITY_DLY                       , 26  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CFG_RCD_PARITY_DLY );
+REG64_FLD( MCA_MBA_FARB6Q_CFG_RCD_PARITY_DLY_LEN                   , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CFG_RCD_PARITY_DLY_LEN );
+REG64_FLD( MCA_MBA_FARB6Q_RESERVED_31                              , 31  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_31 );
+
+REG64_FLD( MCA_MBA_FARB7Q_EMER_THROTTLE_IP                         , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EMER_THROTTLE_IP );
+
+REG64_FLD( MCA_MBA_FARB8Q_SAFE_REFRESH_MODE                        , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SAFE_REFRESH_MODE );
+
+REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCB_FIR_CCS_ERR_HOLD_OUT           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_MCB_FIR_CCS_ERR_HOLD_OUT );
+REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCB_FIR_MCBFSM_ERR_HOLD_OUT        , 1   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_MCB_FIR_MCBFSM_ERR_HOLD_OUT );
+REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCB_CNTLQ_PE_HOLD_OUT              , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_MCB_CNTLQ_PE_HOLD_OUT );
+REG64_FLD( MCBIST_MBA_MCBERRPTQ_CCS_CNTLQ_PE_HOLD_OUT              , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_CCS_CNTLQ_PE_HOLD_OUT );
+REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCBCNTL_PE_HOLD_OUT                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_MCBCNTL_PE_HOLD_OUT );
+REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCBAGEN_PE_HOLD_OUT                , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_MCBAGEN_PE_HOLD_OUT );
+REG64_FLD( MCBIST_MBA_MCBERRPTQ_MAINT_CCS_PE_HOLD_OUT              , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAINT_CCS_PE_HOLD_OUT );
+REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCBDGEN_PE_HOLD_OUT                , 7   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_MCBDGEN_PE_HOLD_OUT );
+REG64_FLD( MCBIST_MBA_MCBERRPTQ_MCBERR_SCOM_PE_HOLD_OUT            , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_MCBERR_SCOM_PE_HOLD_OUT );
+REG64_FLD( MCBIST_MBA_MCBERRPTQ_ECC_MCBIST_OUT_OF_SYNC_HOLD_OUT    , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ECC_MCBIST_OUT_OF_SYNC_HOLD_OUT );
+REG64_FLD( MCBIST_MBA_MCBERRPTQ_SRQ_MCBIST_OUT_OF_SYNC_HOLD_OUT    , 10  , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_SRQ_MCBIST_OUT_OF_SYNC_HOLD_OUT );
+REG64_FLD( MCBIST_MBA_MCBERRPTQ_WRD_MCBIST_OUT_OF_SYNC_HOLD_OUT    , 11  , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRD_MCBIST_OUT_OF_SYNC_HOLD_OUT );
+REG64_FLD( MCBIST_MBA_MCBERRPTQ_SRQ_CCS_UNEXPECTED_PORT_ACTIVE_HOLD_OUT , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_SRQ_CCS_UNEXPECTED_PORT_ACTIVE_HOLD_OUT );
+REG64_FLD( MCBIST_MBA_MCBERRPTQ_FATAL_CNFG_HOLD_OUT                , 13  , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_FATAL_CNFG_HOLD_OUT );
+
+REG64_FLD( MCA_MBA_PMU0Q_READ_COUNT                                , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_READ_COUNT );
+REG64_FLD( MCA_MBA_PMU0Q_READ_COUNT_LEN                            , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_READ_COUNT_LEN );
+REG64_FLD( MCA_MBA_PMU0Q_WRITE_COUNT                               , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_COUNT );
+REG64_FLD( MCA_MBA_PMU0Q_WRITE_COUNT_LEN                           , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_COUNT_LEN );
+
+REG64_FLD( MCA_MBA_PMU1Q_ACTIVATE_COUNT                            , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTIVATE_COUNT );
+REG64_FLD( MCA_MBA_PMU1Q_ACTIVATE_COUNT_LEN                        , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTIVATE_COUNT_LEN );
+REG64_FLD( MCA_MBA_PMU1Q_PU_COUNTS                                 , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PU_COUNTS  );
+REG64_FLD( MCA_MBA_PMU1Q_PU_COUNTS_LEN                             , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PU_COUNTS_LEN );
+
+REG64_FLD( MCA_MBA_PMU2Q_FRAME_COUNT                               , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_FRAME_COUNT );
+REG64_FLD( MCA_MBA_PMU2Q_FRAME_COUNT_LEN                           , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_FRAME_COUNT_LEN );
+
+REG64_FLD( MCA_MBA_PMU3Q_LOW_IDLE_THRESHOLD                        , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOW_IDLE_THRESHOLD );
+REG64_FLD( MCA_MBA_PMU3Q_LOW_IDLE_THRESHOLD_LEN                    , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOW_IDLE_THRESHOLD_LEN );
+REG64_FLD( MCA_MBA_PMU3Q_MED_IDLE_THRESHOLD                        , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MED_IDLE_THRESHOLD );
+REG64_FLD( MCA_MBA_PMU3Q_MED_IDLE_THRESHOLD_LEN                    , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MED_IDLE_THRESHOLD_LEN );
+REG64_FLD( MCA_MBA_PMU3Q_HIGH_IDLE_THRESHOLD                       , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HIGH_IDLE_THRESHOLD );
+REG64_FLD( MCA_MBA_PMU3Q_HIGH_IDLE_THRESHOLD_LEN                   , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HIGH_IDLE_THRESHOLD_LEN );
+
+REG64_FLD( MCA_MBA_PMU4Q_BASE_IDLE_COUNT                           , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_BASE_IDLE_COUNT );
+REG64_FLD( MCA_MBA_PMU4Q_BASE_IDLE_COUNT_LEN                       , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_BASE_IDLE_COUNT_LEN );
+REG64_FLD( MCA_MBA_PMU4Q_LOW_IDLE_COUNT                            , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_LOW_IDLE_COUNT );
+REG64_FLD( MCA_MBA_PMU4Q_LOW_IDLE_COUNT_LEN                        , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_LOW_IDLE_COUNT_LEN );
+
+REG64_FLD( MCA_MBA_PMU5Q_MED_IDLE_COUNT                            , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_MED_IDLE_COUNT );
+REG64_FLD( MCA_MBA_PMU5Q_MED_IDLE_COUNT_LEN                        , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_MED_IDLE_COUNT_LEN );
+REG64_FLD( MCA_MBA_PMU5Q_HIGH_IDLE_COUNT                           , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIGH_IDLE_COUNT );
+REG64_FLD( MCA_MBA_PMU5Q_HIGH_IDLE_COUNT_LEN                       , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIGH_IDLE_COUNT_LEN );
+
+REG64_FLD( MCA_MBA_PMU6Q_EVENT0_COUNTER                            , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_EVENT0_COUNTER );
+REG64_FLD( MCA_MBA_PMU6Q_EVENT0_COUNTER_LEN                        , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_EVENT0_COUNTER_LEN );
+REG64_FLD( MCA_MBA_PMU6Q_EVENT1_COUNTER                            , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_EVENT1_COUNTER );
+REG64_FLD( MCA_MBA_PMU6Q_EVENT1_COUNTER_LEN                        , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_EVENT1_COUNTER_LEN );
+REG64_FLD( MCA_MBA_PMU6Q_EVENT2_COUNTER                            , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_EVENT2_COUNTER );
+REG64_FLD( MCA_MBA_PMU6Q_EVENT2_COUNTER_LEN                        , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_EVENT2_COUNTER_LEN );
+REG64_FLD( MCA_MBA_PMU6Q_EVENT3_COUNTER                            , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_EVENT3_COUNTER );
+REG64_FLD( MCA_MBA_PMU6Q_EVENT3_COUNTER_LEN                        , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_EVENT3_COUNTER_LEN );
+
+REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT0_SELECT                         , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EVENT0_SELECT );
+REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT0_SELECT_LEN                     , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EVENT0_SELECT_LEN );
+REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT1_SELECT                         , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EVENT1_SELECT );
+REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT1_SELECT_LEN                     , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EVENT1_SELECT_LEN );
+REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT2_SELECT                         , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EVENT2_SELECT );
+REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT2_SELECT_LEN                     , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EVENT2_SELECT_LEN );
+REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT3_SELECT                         , 18  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EVENT3_SELECT );
+REG64_FLD( MCA_MBA_PMU7Q_CFG_EVENT3_SELECT_LEN                     , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EVENT3_SELECT_LEN );
+REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C0                          , 24  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRESCALER_C0 );
+REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C0_LEN                      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRESCALER_C0_LEN );
+REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C1                          , 26  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRESCALER_C1 );
+REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C1_LEN                      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRESCALER_C1_LEN );
+REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C2                          , 28  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRESCALER_C2 );
+REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C2_LEN                      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRESCALER_C2_LEN );
+REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C3                          , 30  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRESCALER_C3 );
+REG64_FLD( MCA_MBA_PMU7Q_CFG_PRESCALER_C3_LEN                      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRESCALER_C3_LEN );
+REG64_FLD( MCA_MBA_PMU7Q_CASCADE                                   , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CASCADE    );
+REG64_FLD( MCA_MBA_PMU7Q_CASCADE_LEN                               , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CASCADE_LEN );
+REG64_FLD( MCA_MBA_PMU7Q_FREEZE                                    , 35  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FREEZE     );
+
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_TYPE                             , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD0_TYPE );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_TYPE_LEN                         , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD0_TYPE_LEN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_MRANK_MATCH_EN                   , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD0_MRANK_MATCH_EN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_SRANK_MATCH_EN                   , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD0_SRANK_MATCH_EN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_BG_MATCH_EN                      , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD0_BG_MATCH_EN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_BANK_MATCH_EN                    , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD0_BANK_MATCH_EN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_MRANK                            , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD0_MRANK );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_MRANK_LEN                        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD0_MRANK_LEN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_SRANK                            , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD0_SRANK );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_SRANK_LEN                        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD0_SRANK_LEN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_BG                               , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD0_BG );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_BG_LEN                           , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD0_BG_LEN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_BANK                             , 14  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD0_BANK );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD0_BANK_LEN                         , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD0_BANK_LEN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_TYPE                             , 17  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD1_TYPE );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_TYPE_LEN                         , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD1_TYPE_LEN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_MRANK_MATCH_EN                   , 19  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD1_MRANK_MATCH_EN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_SRANK_MATCH_EN                   , 20  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD1_SRANK_MATCH_EN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_BG_MATCH_EN                      , 21  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD1_BG_MATCH_EN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_BANK_MATCH_EN                    , 22  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD1_BANK_MATCH_EN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_MRANK                            , 23  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD1_MRANK );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_MRANK_LEN                        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD1_MRANK_LEN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_SRANK                            , 26  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD1_SRANK );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_SRANK_LEN                        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD1_SRANK_LEN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_BG                               , 29  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD1_BG );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_BG_LEN                           , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD1_BG_LEN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_BANK                             , 31  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD1_BANK );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD1_BANK_LEN                         , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD1_BANK_LEN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_TYPE                             , 34  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD2_TYPE );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_TYPE_LEN                         , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD2_TYPE_LEN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_MRANK_MATCH_EN                   , 36  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD2_MRANK_MATCH_EN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_SRANK_MATCH_EN                   , 37  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD2_SRANK_MATCH_EN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_BG_MATCH_EN                      , 38  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD2_BG_MATCH_EN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_BANK_MATCH_EN                    , 39  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD2_BANK_MATCH_EN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_MRANK                            , 40  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD2_MRANK );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_MRANK_LEN                        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD2_MRANK_LEN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_SRANK                            , 43  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD2_SRANK );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_SRANK_LEN                        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD2_SRANK_LEN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_BG                               , 46  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD2_BG );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_BG_LEN                           , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD2_BG_LEN );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_BANK                             , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD2_BANK );
+REG64_FLD( MCA_MBA_PMU8Q_CFG_CMD2_BANK_LEN                         , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD2_BANK_LEN );
+REG64_FLD( MCA_MBA_PMU8Q_RESERVED_51_63                            , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_51_63 );
+REG64_FLD( MCA_MBA_PMU8Q_RESERVED_51_63_LEN                        , 13  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_51_63_LEN );
+
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_RRQ_SKIP_LIMIT                        , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RRQ_SKIP_LIMIT );
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_RRQ_SKIP_LIMIT_LEN                    , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RRQ_SKIP_LIMIT_LEN );
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_RRQ_FIFO_MODE                         , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RRQ_FIFO_MODE );
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_RRQ_SINGLE_THREAD_MODE                , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RRQ_SINGLE_THREAD_MODE );
+REG64_FLD( MCA_MBA_RRQ0Q_RESERVED_8_10                             , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_10 );
+REG64_FLD( MCA_MBA_RRQ0Q_RESERVED_8_10_LEN                         , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_10_LEN );
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_DISABLE_RD_PG_MODE                    , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DISABLE_RD_PG_MODE );
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_DISABLE_FAST_PATH                     , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DISABLE_FAST_PATH );
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_RD_IDLE_ALLOW_WR                      , 13  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RD_IDLE_ALLOW_WR );
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_RD_IDLE_ALLOW_WR_LEN                  , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RD_IDLE_ALLOW_WR_LEN );
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT                 , 24  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT );
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT_LEN             , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT_LEN );
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_RMWBUFF_CAPACITY_LIMIT                , 30  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT );
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_RMWBUFF_CAPACITY_LIMIT_LEN            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT_LEN );
+REG64_FLD( MCA_MBA_RRQ0Q_RESERVED_37_56                            , 37  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_37_56 );
+REG64_FLD( MCA_MBA_RRQ0Q_RESERVED_37_56_LEN                        , 20  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_37_56_LEN );
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_RRQ_ACT_NUM_READS_PENDING             , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING );
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_RRQ_ACT_NUM_READS_PENDING_LEN         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING_LEN );
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_INJ_CANCEL_ACK_ERR                    , 61  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_INJ_CANCEL_ACK_ERR );
+REG64_FLD( MCA_MBA_RRQ0Q_CFG_RRQ_ENTRY0_ENABLE                     , 62  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RRQ_ENTRY0_ENABLE );
+REG64_FLD( MCA_MBA_RRQ0Q_RESERVED_63                               , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_63 );
+
+REG64_FLD( MCA_MBA_TMR0Q_RRDM_DLY                                  , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RRDM_DLY   );
+REG64_FLD( MCA_MBA_TMR0Q_RRDM_DLY_LEN                              , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RRDM_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR0Q_RRSMSR_DLY                                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RRSMSR_DLY );
+REG64_FLD( MCA_MBA_TMR0Q_RRSMSR_DLY_LEN                            , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RRSMSR_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR0Q_RRSMDR_DLY                                , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RRSMDR_DLY );
+REG64_FLD( MCA_MBA_TMR0Q_RRSMDR_DLY_LEN                            , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RRSMDR_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR0Q_RROP_DLY                                  , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RROP_DLY   );
+REG64_FLD( MCA_MBA_TMR0Q_RROP_DLY_LEN                              , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RROP_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR0Q_WWDM_DLY                                  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WWDM_DLY   );
+REG64_FLD( MCA_MBA_TMR0Q_WWDM_DLY_LEN                              , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WWDM_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR0Q_WWSMSR_DLY                                , 20  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WWSMSR_DLY );
+REG64_FLD( MCA_MBA_TMR0Q_WWSMSR_DLY_LEN                            , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WWSMSR_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR0Q_WWSMDR_DLY                                , 24  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WWSMDR_DLY );
+REG64_FLD( MCA_MBA_TMR0Q_WWSMDR_DLY_LEN                            , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WWSMDR_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR0Q_WWOP_DLY                                  , 28  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WWOP_DLY   );
+REG64_FLD( MCA_MBA_TMR0Q_WWOP_DLY_LEN                              , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WWOP_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR0Q_RWDM_DLY                                  , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RWDM_DLY   );
+REG64_FLD( MCA_MBA_TMR0Q_RWDM_DLY_LEN                              , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RWDM_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR0Q_RWSMSR_DLY                                , 37  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RWSMSR_DLY );
+REG64_FLD( MCA_MBA_TMR0Q_RWSMSR_DLY_LEN                            , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RWSMSR_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR0Q_RWSMDR_DLY                                , 42  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RWSMDR_DLY );
+REG64_FLD( MCA_MBA_TMR0Q_RWSMDR_DLY_LEN                            , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RWSMDR_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR0Q_WRDM_DLY                                  , 47  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRDM_DLY   );
+REG64_FLD( MCA_MBA_TMR0Q_WRDM_DLY_LEN                              , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRDM_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR0Q_WRSMSR_DLY                                , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRSMSR_DLY );
+REG64_FLD( MCA_MBA_TMR0Q_WRSMSR_DLY_LEN                            , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRSMSR_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR0Q_WRSMDR_DLY                                , 57  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRSMDR_DLY );
+REG64_FLD( MCA_MBA_TMR0Q_WRSMDR_DLY_LEN                            , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRSMDR_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR0Q_RESERVED_63                               , 63  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_63 );
+
+REG64_FLD( MCA_MBA_TMR1Q_RRSBG_DLY                                 , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RRSBG_DLY  );
+REG64_FLD( MCA_MBA_TMR1Q_RRSBG_DLY_LEN                             , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RRSBG_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR1Q_WRSBG_DLY                                 , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRSBG_DLY  );
+REG64_FLD( MCA_MBA_TMR1Q_WRSBG_DLY_LEN                             , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRSBG_DLY_LEN );
+REG64_FLD( MCA_MBA_TMR1Q_CFG_TFAW                                  , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TFAW   );
+REG64_FLD( MCA_MBA_TMR1Q_CFG_TFAW_LEN                              , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TFAW_LEN );
+REG64_FLD( MCA_MBA_TMR1Q_CFG_TRCD                                  , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TRCD   );
+REG64_FLD( MCA_MBA_TMR1Q_CFG_TRCD_LEN                              , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TRCD_LEN );
+REG64_FLD( MCA_MBA_TMR1Q_CFG_TRP                                   , 21  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TRP    );
+REG64_FLD( MCA_MBA_TMR1Q_CFG_TRP_LEN                               , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TRP_LEN );
+REG64_FLD( MCA_MBA_TMR1Q_CFG_TRAS                                  , 26  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TRAS   );
+REG64_FLD( MCA_MBA_TMR1Q_CFG_TRAS_LEN                              , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_TRAS_LEN );
+REG64_FLD( MCA_MBA_TMR1Q_RESERVED_32_40                            , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_40 );
+REG64_FLD( MCA_MBA_TMR1Q_RESERVED_32_40_LEN                        , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_40_LEN );
+REG64_FLD( MCA_MBA_TMR1Q_CFG_WR2PRE                                , 41  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WR2PRE );
+REG64_FLD( MCA_MBA_TMR1Q_CFG_WR2PRE_LEN                            , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WR2PRE_LEN );
+REG64_FLD( MCA_MBA_TMR1Q_CFG_RD2PRE                                , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RD2PRE );
+REG64_FLD( MCA_MBA_TMR1Q_CFG_RD2PRE_LEN                            , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RD2PRE_LEN );
+REG64_FLD( MCA_MBA_TMR1Q_TRRD                                      , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRRD       );
+REG64_FLD( MCA_MBA_TMR1Q_TRRD_LEN                                  , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRRD_LEN   );
+REG64_FLD( MCA_MBA_TMR1Q_TRRD_SBG                                  , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRRD_SBG   );
+REG64_FLD( MCA_MBA_TMR1Q_TRRD_SBG_LEN                              , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRRD_SBG_LEN );
+REG64_FLD( MCA_MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY                  , 60  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY );
+REG64_FLD( MCA_MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY_LEN              , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY_LEN );
+
+REG64_FLD( MCA_MBA_TMR2Q_CFG_BANK_BUSY_FSM_DIS                     , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_BANK_BUSY_FSM_DIS );
+REG64_FLD( MCA_MBA_TMR2Q_CFG_BANK_BUSY_FSM_DIS_LEN                 , 20  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_BANK_BUSY_FSM_DIS_LEN );
+REG64_FLD( MCA_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS               , 20  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS );
+REG64_FLD( MCA_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN           , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN );
+REG64_FLD( MCA_MBA_TMR2Q_RESERVED_32_63                            , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_63 );
+REG64_FLD( MCA_MBA_TMR2Q_RESERVED_32_63_LEN                        , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_63_LEN );
+
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRITE_HW_MARK                         , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRITE_HW_MARK );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRITE_HW_MARK_LEN                     , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRITE_HW_MARK_LEN );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_FIFO_MODE                         , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRQ_FIFO_MODE );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_DISABLE_WR_PG_MODE                    , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DISABLE_WR_PG_MODE );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY                     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRQ_ENTRY0_HP_DLY );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY_LEN                 , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRQ_ENTRY0_HP_DLY_LEN );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_FLUSH_WR_RANK                     , 19  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRQ_FLUSH_WR_RANK );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_ENABLE_NON_HP_WR                  , 20  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRQ_ENABLE_NON_HP_WR );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR            , 21  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN        , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRITE_LW_MARK                         , 33  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRITE_LW_MARK );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRITE_LW_MARK_LEN                     , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRITE_LW_MARK_LEN );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_SKIP_LIMIT                        , 38  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRQ_SKIP_LIMIT );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_SKIP_LIMIT_LEN                    , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRQ_SKIP_LIMIT_LEN );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_SINGLE_THREAD_MODE                , 44  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRQ_SINGLE_THREAD_MODE );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD                     , 45  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RQ_HANG_THRESHOLD );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD_LEN                 , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RQ_HANG_THRESHOLD_LEN );
+REG64_FLD( MCA_MBA_WRQ0Q_RESERVED_53_54                            , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_53_54 );
+REG64_FLD( MCA_MBA_WRQ0Q_RESERVED_53_54_LEN                        , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_53_54_LEN );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING            , 55  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING );
+REG64_FLD( MCA_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN        , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN );
+REG64_FLD( MCA_MBA_WRQ0Q_RESERVED_59_63                            , 59  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_59_63 );
+REG64_FLD( MCA_MBA_WRQ0Q_RESERVED_59_63_LEN                        , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_59_63_LEN );
+
+REG64_FLD( MCBIST_MBECTLQ_ATOMIC_ALT_CE_INJ                        , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATOMIC_ALT_CE_INJ );
+REG64_FLD( MCBIST_MBECTLQ_ATOMIC_ALT_CHIP_KILL_INJ                 , 1   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATOMIC_ALT_CHIP_KILL_INJ );
+REG64_FLD( MCBIST_MBECTLQ_ATOMIC_ALT_UE_INJ                        , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATOMIC_ALT_UE_INJ );
+REG64_FLD( MCBIST_MBECTLQ_ATOMIC_ALT_SUE_INJ                       , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATOMIC_ALT_SUE_INJ );
+REG64_FLD( MCBIST_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL                   , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATOMIC_ALT_INJ_SYM_SEL );
+REG64_FLD( MCBIST_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL_LEN               , 7   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATOMIC_ALT_INJ_SYM_SEL_LEN );
+REG64_FLD( MCBIST_MBECTLQ_RESERVE_11                               , 11  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVE_11 );
+REG64_FLD( MCBIST_MBECTLQ_SCOM_CMD_REG_INJ_MODE                    , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SCOM_CMD_REG_INJ_MODE );
+REG64_FLD( MCBIST_MBECTLQ_SCOM_CMD_REG_INJ                         , 13  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SCOM_CMD_REG_INJ );
+REG64_FLD( MCBIST_MBECTLQ_MCBIST_FSM_INJ_MODE                      , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_FSM_INJ_MODE );
+REG64_FLD( MCBIST_MBECTLQ_MCBIST_FSM_INJ_REG                       , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_FSM_INJ_REG );
+REG64_FLD( MCBIST_MBECTLQ_CCS_FSM_INJ_MODE                         , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CCS_FSM_INJ_MODE );
+REG64_FLD( MCBIST_MBECTLQ_CCS_FSM_INJ_REG                          , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CCS_FSM_INJ_REG );
+REG64_FLD( MCBIST_MBECTLQ_RESERVED_18_31                           , 18  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_18_31 );
+REG64_FLD( MCBIST_MBECTLQ_RESERVED_18_31_LEN                       , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_18_31_LEN );
+
+REG64_FLD( MCA_MBMDI_MDI_0                                         , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MDI_0      );
+REG64_FLD( MCA_MBMDI_SUE_0                                         , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUE_0      );
+REG64_FLD( MCA_MBMDI_MDI_1                                         , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MDI_1      );
+REG64_FLD( MCA_MBMDI_SUE_1                                         , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUE_1      );
+
+REG64_FLD( MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ON_RCE              , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_MPE_ON_RCE );
+REG64_FLD( MCBIST_MBMPER0Q_RESERVED_39                             , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39 );
+
+REG64_FLD( MCBIST_MBMPER1Q_PORT_1_MAINLINE_MPE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBMPER1Q_PORT_1_MAINLINE_MPE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBMPER1Q_PORT_1_MAINLINE_MPE_ON_RCE              , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_MPE_ON_RCE );
+REG64_FLD( MCBIST_MBMPER1Q_RESERVED_39                             , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39 );
+
+REG64_FLD( MCBIST_MBMPER2Q_PORT_2_MAINLINE_MPE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBMPER2Q_PORT_2_MAINLINE_MPE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBMPER2Q_PORT_2_MAINLINE_MPE_ON_RCE              , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_MPE_ON_RCE );
+REG64_FLD( MCBIST_MBMPER2Q_RESERVED_39                             , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39 );
+
+REG64_FLD( MCBIST_MBMPER3Q_PORT_3_MAINLINE_MPE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBMPER3Q_PORT_3_MAINLINE_MPE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBMPER3Q_PORT_3_MAINLINE_MPE_ON_RCE              , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_MPE_ON_RCE );
+REG64_FLD( MCBIST_MBMPER3Q_RESERVED_39                             , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39 );
+
+REG64_FLD( MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ON_RCE              , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_NCE_ON_RCE );
+REG64_FLD( MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_IS_TCE              , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_NCE_IS_TCE );
+
+REG64_FLD( MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_ON_RCE              , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_NCE_ON_RCE );
+REG64_FLD( MCBIST_MBNCER1Q_PORT_1_MAINLINE_NCE_IS_TCE              , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_NCE_IS_TCE );
+
+REG64_FLD( MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_ON_RCE              , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_NCE_ON_RCE );
+REG64_FLD( MCBIST_MBNCER2Q_PORT_2_MAINLINE_NCE_IS_TCE              , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_NCE_IS_TCE );
+
+REG64_FLD( MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_ON_RCE              , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_NCE_ON_RCE );
+REG64_FLD( MCBIST_MBNCER3Q_PORT_3_MAINLINE_NCE_IS_TCE              , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_NCE_IS_TCE );
+
+REG64_FLD( MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBRCER0Q_RESERVED_38_39                          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39 );
+REG64_FLD( MCBIST_MBRCER0Q_RESERVED_38_39_LEN                      , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39_LEN );
+
+REG64_FLD( MCBIST_MBRCER1Q_PORT_1_MAINLINE_RCE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBRCER1Q_PORT_1_MAINLINE_RCE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBRCER1Q_RESERVED_38_39                          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39 );
+REG64_FLD( MCBIST_MBRCER1Q_RESERVED_38_39_LEN                      , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39_LEN );
+
+REG64_FLD( MCBIST_MBRCER2Q_PORT_2_MAINLINE_RCE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBRCER2Q_PORT_2_MAINLINE_RCE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBRCER2Q_RESERVED_38_39                          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39 );
+REG64_FLD( MCBIST_MBRCER2Q_RESERVED_38_39_LEN                      , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39_LEN );
+
+REG64_FLD( MCBIST_MBRCER3Q_PORT_3_MAINLINE_RCE_ADDR_TRAP           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBRCER3Q_PORT_3_MAINLINE_RCE_ADDR_TRAP_LEN       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBRCER3Q_RESERVED_38_39                          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39 );
+REG64_FLD( MCBIST_MBRCER3Q_RESERVED_38_39_LEN                      , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39_LEN );
+
+REG64_FLD( MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT                    , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_INTERMITTENT_CE_COUNT );
+REG64_FLD( MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT_LEN                , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_INTERMITTENT_CE_COUNT_LEN );
+REG64_FLD( MCBIST_MBSEC0Q_SOFT_CE_COUNT                            , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SOFT_CE_COUNT );
+REG64_FLD( MCBIST_MBSEC0Q_SOFT_CE_COUNT_LEN                        , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SOFT_CE_COUNT_LEN );
+REG64_FLD( MCBIST_MBSEC0Q_HARD_CE_COUNT                            , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_HARD_CE_COUNT );
+REG64_FLD( MCBIST_MBSEC0Q_HARD_CE_COUNT_LEN                        , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_HARD_CE_COUNT_LEN );
+REG64_FLD( MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT                   , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_INTERMITTENT_MCE_COUNT );
+REG64_FLD( MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT_LEN               , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_INTERMITTENT_MCE_COUNT_LEN );
+REG64_FLD( MCBIST_MBSEC0Q_SOFT_MCE_COUNT                           , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SOFT_MCE_COUNT );
+REG64_FLD( MCBIST_MBSEC0Q_SOFT_MCE_COUNT_LEN                       , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SOFT_MCE_COUNT_LEN );
+
+REG64_FLD( MCBIST_MBSEC1Q_HARD_MCE_COUNT                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_HARD_MCE_COUNT );
+REG64_FLD( MCBIST_MBSEC1Q_HARD_MCE_COUNT_LEN                       , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_HARD_MCE_COUNT_LEN );
+REG64_FLD( MCBIST_MBSEC1Q_ICE_COUNT                                , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ICE_COUNT  );
+REG64_FLD( MCBIST_MBSEC1Q_ICE_COUNT_LEN                            , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ICE_COUNT_LEN );
+REG64_FLD( MCBIST_MBSEC1Q_UE_COUNT                                 , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_UE_COUNT   );
+REG64_FLD( MCBIST_MBSEC1Q_UE_COUNT_LEN                             , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_UE_COUNT_LEN );
+REG64_FLD( MCBIST_MBSEC1Q_AUE                                      , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_AUE        );
+REG64_FLD( MCBIST_MBSEC1Q_AUE_LEN                                  , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_AUE_LEN    );
+REG64_FLD( MCBIST_MBSEC1Q_RCE_COUNT                                , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RCE_COUNT  );
+REG64_FLD( MCBIST_MBSEC1Q_RCE_COUNT_LEN                            , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RCE_COUNT_LEN );
+
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD        , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD );
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN    , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN );
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD     , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD );
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN );
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD        , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD );
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN    , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN );
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD     , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD );
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN );
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_GALOIS_FIELD        , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD );
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_GALOIS_FIELD_LEN    , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD_LEN );
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD     , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD );
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD_LEN , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD_LEN );
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_GALOIS_FIELD        , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD );
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_GALOIS_FIELD_LEN    , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD_LEN );
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD     , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD );
+REG64_FLD( MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD_LEN , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD_LEN );
+
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_GALOIS_FIELD        , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD );
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_GALOIS_FIELD_LEN    , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD_LEN );
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD     , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD );
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD_LEN , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD_LEN );
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_GALOIS_FIELD        , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD );
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_GALOIS_FIELD_LEN    , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD_LEN );
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD     , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD );
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD_LEN , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD_LEN );
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_GALOIS_FIELD        , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD );
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_GALOIS_FIELD_LEN    , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD_LEN );
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD     , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD );
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD_LEN , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD_LEN );
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_GALOIS_FIELD        , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD );
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_GALOIS_FIELD_LEN    , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD_LEN );
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD     , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD );
+REG64_FLD( MCBIST_MBSEVR1Q_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD_LEN , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD_LEN );
+
+REG64_FLD( MCBIST_MBSMODESQ_CFG_DDR4E_BLIND_STEER_MODE             , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DDR4E_BLIND_STEER_MODE );
+REG64_FLD( MCBIST_MBSMODESQ_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS , 1   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS );
+REG64_FLD( MCBIST_MBSMODESQ_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS_LEN , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS_LEN );
+REG64_FLD( MCBIST_MBSMODESQ_RESERVE_5_15                           , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVE_5_15 );
+REG64_FLD( MCBIST_MBSMODESQ_RESERVE_5_15_LEN                       , 11  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVE_5_15_LEN );
+
+REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT                       , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCE_SYMBOL0_COUNT );
+REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT_LEN                   , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCE_SYMBOL0_COUNT_LEN );
+REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT                       , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCE_SYMBOL1_COUNT );
+REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT_LEN                   , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCE_SYMBOL1_COUNT_LEN );
+REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT                       , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCE_SYMBOL2_COUNT );
+REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT_LEN                   , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCE_SYMBOL2_COUNT_LEN );
+REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT                       , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCE_SYMBOL3_COUNT );
+REG64_FLD( MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT_LEN                   , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCE_SYMBOL3_COUNT_LEN );
+
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00               , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_00 );
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_00_LEN );
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01               , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_01 );
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_01_LEN );
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02               , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_02 );
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_02_LEN );
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03               , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_03 );
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_03_LEN );
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04               , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_04 );
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_04_LEN );
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05               , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_05 );
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_05_LEN );
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06               , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_06 );
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_06_LEN );
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07               , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_07 );
+REG64_FLD( MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_07_LEN );
+
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_08               , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_08 );
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_08_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_08_LEN );
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_09               , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_09 );
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_09_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_09_LEN );
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_10               , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_10 );
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_10_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_10_LEN );
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_11               , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_11 );
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_11_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_11_LEN );
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_12               , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_12 );
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_12_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_12_LEN );
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_13               , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_13 );
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_13_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_13_LEN );
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_14               , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_14 );
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_14_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_14_LEN );
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_15               , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_15 );
+REG64_FLD( MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_15_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_15_LEN );
+
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_16               , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_16 );
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_16_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_16_LEN );
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_17               , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_17 );
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_17_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_17_LEN );
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_18               , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_18 );
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_18_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_18_LEN );
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_19               , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_19 );
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_19_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_19_LEN );
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_20               , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_20 );
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_20_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_20_LEN );
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_21               , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_21 );
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_21_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_21_LEN );
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_22               , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_22 );
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_22_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_22_LEN );
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_23               , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_23 );
+REG64_FLD( MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_23_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_23_LEN );
+
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_24               , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_24 );
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_24_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_24_LEN );
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_25               , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_25 );
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_25_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_25_LEN );
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_26               , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_26 );
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_26_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_26_LEN );
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_27               , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_27 );
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_27_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_27_LEN );
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_28               , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_28 );
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_28_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_28_LEN );
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_29               , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_29 );
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_29_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_29_LEN );
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_30               , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_30 );
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_30_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_30_LEN );
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_31               , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_31 );
+REG64_FLD( MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_31_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_31_LEN );
+
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_32               , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_32 );
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_32_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_32_LEN );
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_33               , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_33 );
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_33_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_33_LEN );
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_34               , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_34 );
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_34_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_34_LEN );
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_35               , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_35 );
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_35_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_35_LEN );
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_36               , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_36 );
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_36_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_36_LEN );
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_37               , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_37 );
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_37_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_37_LEN );
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_38               , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_38 );
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_38_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_38_LEN );
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_39               , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_39 );
+REG64_FLD( MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_39_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_39_LEN );
+
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_40               , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_40 );
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_40_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_40_LEN );
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_41               , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_41 );
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_41_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_41_LEN );
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_42               , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_42 );
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_42_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_42_LEN );
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_43               , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_43 );
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_43_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_43_LEN );
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_44               , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_44 );
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_44_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_44_LEN );
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_45               , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_45 );
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_45_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_45_LEN );
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_46               , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_46 );
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_46_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_46_LEN );
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_47               , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_47 );
+REG64_FLD( MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_47_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_47_LEN );
+
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_48               , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_48 );
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_48_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_48_LEN );
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_49               , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_49 );
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_49_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_49_LEN );
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_50               , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_50 );
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_50_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_50_LEN );
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_51               , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_51 );
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_51_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_51_LEN );
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_52               , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_52 );
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_52_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_52_LEN );
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_53               , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_53 );
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_53_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_53_LEN );
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_54               , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_54 );
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_54_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_54_LEN );
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_55               , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_55 );
+REG64_FLD( MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_55_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_55_LEN );
+
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_56               , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_56 );
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_56_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_56_LEN );
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_57               , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_57 );
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_57_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_57_LEN );
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_58               , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_58 );
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_58_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_58_LEN );
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_59               , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_59 );
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_59_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_59_LEN );
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_60               , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_60 );
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_60_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_60_LEN );
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_61               , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_61 );
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_61_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_61_LEN );
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_62               , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_62 );
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_62_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_62_LEN );
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_63               , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_63 );
+REG64_FLD( MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_63_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_63_LEN );
+
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_64               , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_64 );
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_64_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_64_LEN );
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_65               , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_65 );
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_65_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_65_LEN );
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_66               , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_66 );
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_66_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_66_LEN );
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_67               , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_67 );
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_67_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_67_LEN );
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_68               , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_68 );
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_68_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_68_LEN );
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_69               , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_69 );
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_69_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_69_LEN );
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_70               , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_70 );
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_70_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_70_LEN );
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_71               , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_71 );
+REG64_FLD( MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_71_LEN           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODAL_SYMBOL_COUNTER_71_LEN );
+
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT                    , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_NCE_INT );
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_NCE_INT_LEN );
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT                   , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_NCE_SOFT );
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT_LEN               , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_NCE_SOFT_LEN );
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD                   , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_NCE_HARD );
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD_LEN               , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_NCE_HARD_LEN );
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE                        , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_RCE );
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE_LEN                    , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_RCE_LEN );
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE                        , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_ICE );
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE_LEN                    , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_ICE_LEN );
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT                    , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_MCE_INT );
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT_LEN                , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_MCE_INT_LEN );
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT                   , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_MCE_SOFT );
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT_LEN               , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_MCE_SOFT_LEN );
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD                   , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_MCE_HARD );
+REG64_FLD( MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD_LEN               , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRESH_MAG_MCE_HARD_LEN );
+REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_SCE                          , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PAUSE_ON_SCE );
+REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_MCE                          , 33  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PAUSE_ON_MCE );
+REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_MPE                          , 34  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PAUSE_ON_MPE );
+REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_UE                           , 35  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PAUSE_ON_UE );
+REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_SUE                          , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PAUSE_ON_SUE );
+REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_AUE                          , 37  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PAUSE_ON_AUE );
+REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_ON_RCD                          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PAUSE_ON_RCD );
+REG64_FLD( MCBIST_MBSTRQ_RESERVE_39_52                             , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVE_39_52 );
+REG64_FLD( MCBIST_MBSTRQ_RESERVE_39_52_LEN                         , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVE_39_52_LEN );
+REG64_FLD( MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE                   , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SYMBOL_COUNTER_MODE );
+REG64_FLD( MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE_LEN               , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SYMBOL_COUNTER_MODE_LEN );
+REG64_FLD( MCBIST_MBSTRQ_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE          , 55  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE );
+REG64_FLD( MCBIST_MBSTRQ_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE         , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE );
+REG64_FLD( MCBIST_MBSTRQ_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE          , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE );
+REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_MCB_ERROR                       , 58  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PAUSE_MCB_ERROR );
+REG64_FLD( MCBIST_MBSTRQ_CFG_PAUSE_MCB_LOG_FULL                    , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PAUSE_MCB_LOG_FULL );
+REG64_FLD( MCBIST_MBSTRQ_CFG_MAINT_RCE_WITH_CE                     , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MAINT_RCE_WITH_CE );
+REG64_FLD( MCBIST_MBSTRQ_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE          , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE );
+REG64_FLD( MCBIST_MBSTRQ_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE         , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE );
+REG64_FLD( MCBIST_MBSTRQ_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE          , 63  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE );
+
+REG64_FLD( MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP             , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN         , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBUER0Q_RESERVED_38_39                           , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39 );
+REG64_FLD( MCBIST_MBUER0Q_RESERVED_38_39_LEN                       , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39_LEN );
+
+REG64_FLD( MCBIST_MBUER1Q_PORT_1_MAINLINE_UE_ADDR_TRAP             , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBUER1Q_PORT_1_MAINLINE_UE_ADDR_TRAP_LEN         , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBUER1Q_RESERVED_38_39                           , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39 );
+REG64_FLD( MCBIST_MBUER1Q_RESERVED_38_39_LEN                       , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39_LEN );
+
+REG64_FLD( MCBIST_MBUER2Q_PORT_2_MAINLINE_UE_ADDR_TRAP             , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBUER2Q_PORT_2_MAINLINE_UE_ADDR_TRAP_LEN         , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBUER2Q_RESERVED_38_39                           , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39 );
+REG64_FLD( MCBIST_MBUER2Q_RESERVED_38_39_LEN                       , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39_LEN );
+
+REG64_FLD( MCBIST_MBUER3Q_PORT_3_MAINLINE_UE_ADDR_TRAP             , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP );
+REG64_FLD( MCBIST_MBUER3Q_PORT_3_MAINLINE_UE_ADDR_TRAP_LEN         , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MBUER3Q_RESERVED_38_39                           , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39 );
+REG64_FLD( MCBIST_MBUER3Q_RESERVED_38_39_LEN                       , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_39_LEN );
+
+REG64_FLD( MCS_PORT02_MCAMOC_ENABLE_CLEAN                          , 0   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_CLEAN );
+REG64_FLD( MCS_PORT02_MCAMOC_ENABLE_READ_DATA_FROM_AMOC            , 1   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_READ_DATA_FROM_AMOC );
+REG64_FLD( MCS_PORT02_MCAMOC_ENABLE_READ_DATA_FROM_AMOC_LEN        , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_READ_DATA_FROM_AMOC_LEN );
+REG64_FLD( MCS_PORT02_MCAMOC_WRTO_AMO_COLLISION_RULES              , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_WRTO_AMO_COLLISION_RULES );
+REG64_FLD( MCS_PORT02_MCAMOC_WRTO_AMO_COLLISION_RULES_LEN          , 25  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_WRTO_AMO_COLLISION_RULES_LEN );
+REG64_FLD( MCS_PORT02_MCAMOC_AMO_DRAM_SIZE_128B                    , 29  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_AMO_DRAM_SIZE_128B );
+REG64_FLD( MCS_PORT02_MCAMOC_RESERVED1                             , 30  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( MCS_PORT02_MCAMOC_RESERVED1_LEN                         , 2   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( MCS_PORT13_MCAMOC_ENABLE_CLEAN                          , 0   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_CLEAN );
+REG64_FLD( MCS_PORT13_MCAMOC_ENABLE_READ_DATA_FROM_AMOC            , 1   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_READ_DATA_FROM_AMOC );
+REG64_FLD( MCS_PORT13_MCAMOC_ENABLE_READ_DATA_FROM_AMOC_LEN        , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_READ_DATA_FROM_AMOC_LEN );
+REG64_FLD( MCS_PORT13_MCAMOC_WRTO_AMO_COLLISION_RULES              , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_WRTO_AMO_COLLISION_RULES );
+REG64_FLD( MCS_PORT13_MCAMOC_WRTO_AMO_COLLISION_RULES_LEN          , 25  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_WRTO_AMO_COLLISION_RULES_LEN );
+REG64_FLD( MCS_PORT13_MCAMOC_AMO_DRAM_SIZE_128B                    , 29  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_AMO_DRAM_SIZE_128B );
+REG64_FLD( MCS_PORT13_MCAMOC_RESERVED1                             , 30  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( MCS_PORT13_MCAMOC_RESERVED1_LEN                         , 2   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( MCBIST_MCBACQ_CFG_ADDRESS_COUNTER                       , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ADDRESS_COUNTER );
+REG64_FLD( MCBIST_MCBACQ_CFG_ADDRESS_COUNTER_LEN                   , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ADDRESS_COUNTER_LEN );
+
+REG64_FLD( MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH                         , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_WIDTH );
+REG64_FLD( MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_WIDTH_LEN );
+REG64_FLD( MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE                   , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ADDR_COUNTER_MODE );
+REG64_FLD( MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE_LEN               , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ADDR_COUNTER_MODE_LEN );
+REG64_FLD( MCBIST_MCBAGRAQ_CFG_MAINT_ADDR_MODE_EN                  , 10  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MAINT_ADDR_MODE_EN );
+REG64_FLD( MCBIST_MCBAGRAQ_CFG_MAINT_BROADCAST_MODE_EN             , 11  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MAINT_BROADCAST_MODE_EN );
+REG64_FLD( MCBIST_MCBAGRAQ_CFG_MAINT_DETECT_SRANK_BOUNDARIES       , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MAINT_DETECT_SRANK_BOUNDARIES );
+REG64_FLD( MCBIST_MCBAGRAQ_RESERVED_13_31                          , 13  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_13_31 );
+REG64_FLD( MCBIST_MCBAGRAQ_RESERVED_13_31_LEN                      , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_13_31_LEN );
+
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT                  , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_DIMM_SELECT );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT_LEN              , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_DIMM_SELECT_LEN );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0                       , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_MRANK0 );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0_LEN                   , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_MRANK0_LEN );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1                       , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_MRANK1 );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1_LEN                   , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_MRANK1_LEN );
+REG64_FLD( MCBIST_MCBAMR0A0Q_RESERVED_18_23                        , 18  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_18_23 );
+REG64_FLD( MCBIST_MCBAMR0A0Q_RESERVED_18_23_LEN                    , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_18_23_LEN );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0                       , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_SRANK0 );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0_LEN                   , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_SRANK0_LEN );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1                       , 30  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_SRANK1 );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1_LEN                   , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_SRANK1_LEN );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2                       , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_SRANK2 );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2_LEN                   , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_SRANK2_LEN );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2                        , 42  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_BANK2 );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2_LEN                    , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_BANK2_LEN );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1                        , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_BANK1 );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1_LEN                    , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_BANK1_LEN );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0                        , 54  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_BANK0 );
+REG64_FLD( MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0_LEN                    , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_BANK0_LEN );
+REG64_FLD( MCBIST_MCBAMR0A0Q_RESERVED_60_63                        , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_60_63 );
+REG64_FLD( MCBIST_MCBAMR0A0Q_RESERVED_60_63_LEN                    , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_60_63_LEN );
+
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1                  , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_BANK_GROUP1 );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1_LEN              , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_BANK_GROUP1_LEN );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0                  , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_BANK_GROUP0 );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0_LEN              , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_BANK_GROUP0_LEN );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17                        , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW17 );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17_LEN                    , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW17_LEN );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16                        , 18  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW16 );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16_LEN                    , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW16_LEN );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15                        , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW15 );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15_LEN                    , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW15_LEN );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14                        , 30  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW14 );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14_LEN                    , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW14_LEN );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13                        , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW13 );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13_LEN                    , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW13_LEN );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12                        , 42  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW12 );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12_LEN                    , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW12_LEN );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11                        , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW11 );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11_LEN                    , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW11_LEN );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10                        , 54  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW10 );
+REG64_FLD( MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10_LEN                    , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW10_LEN );
+REG64_FLD( MCBIST_MCBAMR1A0Q_RESERVED_60_63                        , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_60_63 );
+REG64_FLD( MCBIST_MCBAMR1A0Q_RESERVED_60_63_LEN                    , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_60_63_LEN );
+
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9                         , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW9 );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW9_LEN );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8                         , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW8 );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW8_LEN );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7                         , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW7 );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW7_LEN );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6                         , 18  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW6 );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW6_LEN );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW5 );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW5_LEN );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4                         , 30  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW4 );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW4_LEN );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3                         , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW3 );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW3_LEN );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2                         , 42  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW2 );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW2_LEN );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1                         , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW1 );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW1_LEN );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0                         , 54  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW0 );
+REG64_FLD( MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_ROW0_LEN );
+REG64_FLD( MCBIST_MCBAMR2A0Q_RESERVED_60_63                        , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_60_63 );
+REG64_FLD( MCBIST_MCBAMR2A0Q_RESERVED_60_63_LEN                    , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_60_63_LEN );
+
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9                         , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL9 );
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL9_LEN );
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8                         , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL8 );
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL8_LEN );
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7                         , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL7 );
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL7_LEN );
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6                         , 18  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL6 );
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL6_LEN );
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL5 );
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL5_LEN );
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4                         , 30  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL4 );
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL4_LEN );
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3                         , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL3 );
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL3_LEN );
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2                         , 42  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL2 );
+REG64_FLD( MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2_LEN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_AMAP_COL2_LEN );
+REG64_FLD( MCBIST_MCBAMR3A0Q_RESERVED_48_63                        , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48_63 );
+REG64_FLD( MCBIST_MCBAMR3A0Q_RESERVED_48_63_LEN                    , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48_63_LEN );
+
+REG64_FLD( MCBIST_MCBCFGQ_BROADCAST_SYNC_EN                        , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_BROADCAST_SYNC_EN );
+REG64_FLD( MCBIST_MCBCFGQ_BROADCAST_SYNC_WAIT                      , 1   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_BROADCAST_SYNC_WAIT );
+REG64_FLD( MCBIST_MCBCFGQ_BROADCAST_SYNC_WAIT_LEN                  , 7   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_BROADCAST_SYNC_WAIT_LEN );
+REG64_FLD( MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE                     , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD_TIMEOUT_MODE );
+REG64_FLD( MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE_LEN                 , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CMD_TIMEOUT_MODE_LEN );
+REG64_FLD( MCBIST_MCBCFGQ_RESET_KEEPER                             , 10  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESET_KEEPER );
+REG64_FLD( MCBIST_MCBCFGQ_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS         , 11  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS );
+REG64_FLD( MCBIST_MCBCFGQ_CFG_CCS_RETRY_DIS                        , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CCS_RETRY_DIS );
+REG64_FLD( MCBIST_MCBCFGQ_RESERVED_13_34                           , 13  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_13_34 );
+REG64_FLD( MCBIST_MCBCFGQ_RESERVED_13_34_LEN                       , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_13_34_LEN );
+REG64_FLD( MCBIST_MCBCFGQ_CFG_RESET_CNTS_START_OF_RANK             , 35  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RESET_CNTS_START_OF_RANK );
+REG64_FLD( MCBIST_MCBCFGQ_CFG_LOG_COUNTS_IN_TRACE                  , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_LOG_COUNTS_IN_TRACE );
+REG64_FLD( MCBIST_MCBCFGQ_SKIP_INVALID_ADDR_DIMM_DIS               , 37  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SKIP_INVALID_ADDR_DIMM_DIS );
+REG64_FLD( MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_EN                  , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REFRESH_ONLY_SUBTEST_EN );
+REG64_FLD( MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL        , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL );
+REG64_FLD( MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN    , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN );
+REG64_FLD( MCBIST_MCBCFGQ_RAND_ADDR_ALL_ADDR_MODE_EN               , 41  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RAND_ADDR_ALL_ADDR_MODE_EN );
+REG64_FLD( MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME                 , 42  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_REF_WAIT_TIME );
+REG64_FLD( MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME_LEN             , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_REF_WAIT_TIME_LEN );
+REG64_FLD( MCBIST_MCBCFGQ_CFG_MCB_LEN64                            , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MCB_LEN64 );
+REG64_FLD( MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE                  , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PAUSE_ON_ERROR_MODE );
+REG64_FLD( MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE_LEN              , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PAUSE_ON_ERROR_MODE_LEN );
+REG64_FLD( MCBIST_MCBCFGQ_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST       , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST );
+REG64_FLD( MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR        , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR );
+REG64_FLD( MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST     , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST );
+REG64_FLD( MCBIST_MCBCFGQ_CFG_ENABLE_SPEC_ATTN                     , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ENABLE_SPEC_ATTN );
+REG64_FLD( MCBIST_MCBCFGQ_CFG_ENABLE_HOST_ATTN                     , 63  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ENABLE_HOST_ATTN );
+
+REG64_FLD( MCA_MCBCM_MCBIST_HALF_COMPARE_MASK                      , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_HALF_COMPARE_MASK );
+REG64_FLD( MCA_MCBCM_MCBIST_HALF_COMPARE_MASK_LEN                  , 40  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_HALF_COMPARE_MASK_LEN );
+REG64_FLD( MCA_MCBCM_MCBIST_MASK_COVERAGE_SELECTOR                 , 40  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_MASK_COVERAGE_SELECTOR );
+REG64_FLD( MCA_MCBCM_MCBIST_TRAP_NONSTOP                           , 41  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_TRAP_NONSTOP );
+REG64_FLD( MCA_MCBCM_MCBIST_TRAP_CE_ENABLE                         , 42  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_TRAP_CE_ENABLE );
+REG64_FLD( MCA_MCBCM_MCBIST_TRAP_MPE_ENABLE                        , 43  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_TRAP_MPE_ENABLE );
+REG64_FLD( MCA_MCBCM_MCBIST_TRAP_UE_ENABLE                         , 44  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_TRAP_UE_ENABLE );
+
+REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_ROT                            , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DATA_ROT );
+REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_ROT_LEN                        , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DATA_ROT_LEN );
+REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED                       , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DATA_ROT_SEED );
+REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED_LEN                   , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DATA_ROT_SEED_LEN );
+REG64_FLD( MCBIST_MCBDRCRQ_RESERVED_20                             , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_20 );
+REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE                      , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DATA_SEED_MODE );
+REG64_FLD( MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE_LEN                  , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DATA_SEED_MODE_LEN );
+REG64_FLD( MCBIST_MCBDRCRQ_RESERVED_23_63                          , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_23_63 );
+REG64_FLD( MCBIST_MCBDRCRQ_RESERVED_23_63_LEN                      , 41  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_23_63_LEN );
+
+REG64_FLD( MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED                       , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DATA_ROT_SEED );
+REG64_FLD( MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED_LEN                   , 64  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DATA_ROT_SEED_LEN );
+
+REG64_FLD( MCBIST_MCBEA0Q_CFG_END_ADDR_0                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_END_ADDR_0 );
+REG64_FLD( MCBIST_MCBEA0Q_CFG_END_ADDR_0_LEN                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_END_ADDR_0_LEN );
+
+REG64_FLD( MCBIST_MCBEA1Q_CFG_END_ADDR_1                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_END_ADDR_1 );
+REG64_FLD( MCBIST_MCBEA1Q_CFG_END_ADDR_1_LEN                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_END_ADDR_1_LEN );
+
+REG64_FLD( MCBIST_MCBEA2Q_CFG_END_ADDR_2                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_END_ADDR_2 );
+REG64_FLD( MCBIST_MCBEA2Q_CFG_END_ADDR_2_LEN                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_END_ADDR_2_LEN );
+
+REG64_FLD( MCBIST_MCBEA3Q_CFG_END_ADDR_3                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_END_ADDR_3 );
+REG64_FLD( MCBIST_MCBEA3Q_CFG_END_ADDR_3_LEN                       , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_END_ADDR_3_LEN );
+
+REG64_FLD( MCBIST_MCBFD0Q_CFG_FIXED_SEED                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED );
+REG64_FLD( MCBIST_MCBFD0Q_CFG_FIXED_SEED_LEN                       , 64  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED_LEN );
+
+REG64_FLD( MCBIST_MCBFD1Q_CFG_FIXED_SEED                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED );
+REG64_FLD( MCBIST_MCBFD1Q_CFG_FIXED_SEED_LEN                       , 64  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED_LEN );
+
+REG64_FLD( MCBIST_MCBFD2Q_CFG_FIXED_SEED                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED );
+REG64_FLD( MCBIST_MCBFD2Q_CFG_FIXED_SEED_LEN                       , 64  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED_LEN );
+
+REG64_FLD( MCBIST_MCBFD3Q_CFG_FIXED_SEED                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED );
+REG64_FLD( MCBIST_MCBFD3Q_CFG_FIXED_SEED_LEN                       , 64  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED_LEN );
+
+REG64_FLD( MCBIST_MCBFD4Q_CFG_FIXED_SEED                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED );
+REG64_FLD( MCBIST_MCBFD4Q_CFG_FIXED_SEED_LEN                       , 64  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED_LEN );
+
+REG64_FLD( MCBIST_MCBFD5Q_CFG_FIXED_SEED                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED );
+REG64_FLD( MCBIST_MCBFD5Q_CFG_FIXED_SEED_LEN                       , 64  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED_LEN );
+
+REG64_FLD( MCBIST_MCBFD6Q_CFG_FIXED_SEED                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED );
+REG64_FLD( MCBIST_MCBFD6Q_CFG_FIXED_SEED_LEN                       , 64  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED_LEN );
+
+REG64_FLD( MCBIST_MCBFD7Q_CFG_FIXED_SEED                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED );
+REG64_FLD( MCBIST_MCBFD7Q_CFG_FIXED_SEED_LEN                       , 64  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED_LEN );
+
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED1                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED1 );
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED1_LEN                       , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED1_LEN );
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED2                           , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED2 );
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED2_LEN                       , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED2_LEN );
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED3                           , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED3 );
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED3_LEN                       , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED3_LEN );
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED4                           , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED4 );
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED4_LEN                       , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED4_LEN );
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED5                           , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED5 );
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED5_LEN                       , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED5_LEN );
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED6                           , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED6 );
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED6_LEN                       , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED6_LEN );
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED7                           , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED7 );
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED7_LEN                       , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED7_LEN );
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED8                           , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED8 );
+REG64_FLD( MCBIST_MCBFDQ_CFG_FIXED_SEED8_LEN                       , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FIXED_SEED8_LEN );
+
+REG64_FLD( MCBIST_MCBISTFIRACT0_FIR_ACTION0                        , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION0 );
+REG64_FLD( MCBIST_MCBISTFIRACT0_FIR_ACTION0_LEN                    , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION0_LEN );
+
+REG64_FLD( MCBIST_MCBISTFIRACT1_FIR_ACTION1                        , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION1 );
+REG64_FLD( MCBIST_MCBISTFIRACT1_FIR_ACTION1_LEN                    , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION1_LEN );
+
+REG64_FLD( MCBIST_MCBISTFIRMASK_FIR_MASK                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_MASK   );
+REG64_FLD( MCBIST_MCBISTFIRMASK_FIR_MASK_LEN                       , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_MASK_LEN );
+
+REG64_FLD( MCBIST_MCBISTFIRQ_INVALID_MAINT_ADDRESS                 , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_INVALID_MAINT_ADDRESS );
+REG64_FLD( MCBIST_MCBISTFIRQ_COMMAND_ADDRESS_TIMEOUT               , 1   , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMMAND_ADDRESS_TIMEOUT );
+REG64_FLD( MCBIST_MCBISTFIRQ_INTERNAL_FSM_ERROR                    , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_FSM_ERROR );
+REG64_FLD( MCBIST_MCBISTFIRQ_MCBIST_BRODCAST_OUT_OF_SYNC           , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC );
+REG64_FLD( MCBIST_MCBISTFIRQ_MCBIST_DATA_ERROR                     , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCBIST_DATA_ERROR );
+REG64_FLD( MCBIST_MCBISTFIRQ_HARD_NCE_ETE_ATTN                     , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_HARD_NCE_ETE_ATTN );
+REG64_FLD( MCBIST_MCBISTFIRQ_SOFT_NCE_ETE_ATTN                     , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SOFT_NCE_ETE_ATTN );
+REG64_FLD( MCBIST_MCBISTFIRQ_INT_NCE_ETE_ATTN                      , 7   , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_INT_NCE_ETE_ATTN );
+REG64_FLD( MCBIST_MCBISTFIRQ_RCE_ETE_ATTN                          , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_RCE_ETE_ATTN );
+REG64_FLD( MCBIST_MCBISTFIRQ_ICE_ETE_ATTN                          , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_ICE_ETE_ATTN );
+REG64_FLD( MCBIST_MCBISTFIRQ_MCBIST_PROGRAM_COMPLETE               , 10  , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCBIST_PROGRAM_COMPLETE );
+REG64_FLD( MCBIST_MCBISTFIRQ_MCBIST_CCS_SUBTEST_DONE               , 11  , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCBIST_CCS_SUBTEST_DONE );
+REG64_FLD( MCBIST_MCBISTFIRQ_WAT_DEBUG_ATTN                        , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_WAT_DEBUG_ATTN );
+REG64_FLD( MCBIST_MCBISTFIRQ_SCOM_RECOVERABLE_REG_PE               , 13  , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_RECOVERABLE_REG_PE );
+REG64_FLD( MCBIST_MCBISTFIRQ_SCOM_FATAL_REG_PE                     , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_FATAL_REG_PE );
+REG64_FLD( MCBIST_MCBISTFIRQ_WAT_DEBUG_REG_PE                      , 15  , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_WAT_DEBUG_REG_PE );
+REG64_FLD( MCBIST_MCBISTFIRQ_RESERVED_16                           , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_16 );
+REG64_FLD( MCBIST_MCBISTFIRQ_RESERVED_17                           , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_17 );
+REG64_FLD( MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR                   , 18  , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_SCOM_ERROR );
+REG64_FLD( MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR_CLONE             , 19  , SH_UNT_MCBIST   , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_SCOM_ERROR_CLONE );
+
+REG64_FLD( MCBIST_MCBISTFIRWOF_INVALID_MAINT_ADDRESS               , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_INVALID_MAINT_ADDRESS );
+REG64_FLD( MCBIST_MCBISTFIRWOF_INVALID_MAINT_ADDRESS_LEN           , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_INVALID_MAINT_ADDRESS_LEN );
+
+REG64_FLD( MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0                      , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_LFSR_MASK_A0 );
+REG64_FLD( MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0_LEN                  , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_LFSR_MASK_A0_LEN );
+REG64_FLD( MCBIST_MCBLFSRA0Q_RESERVED_38_63                        , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_63 );
+REG64_FLD( MCBIST_MCBLFSRA0Q_RESERVED_38_63_LEN                    , 26  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_63_LEN );
+
+REG64_FLD( MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP                   , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CURRENT_ADDR_TRAP );
+REG64_FLD( MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP_LEN               , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CURRENT_ADDR_TRAP_LEN );
+REG64_FLD( MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP                   , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CURRENT_PORT_TRAP );
+REG64_FLD( MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP_LEN               , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CURRENT_PORT_TRAP_LEN );
+REG64_FLD( MCBIST_MCBMCATQ_CFG_CURRENT_DIMM_TRAP                   , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CURRENT_DIMM_TRAP );
+
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST00_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST00_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD          , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST00_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_2ND_CMD          , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST00_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_3RD_CMD          , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST00_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_REV_MODE          , 7   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST00_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_RAND_MODE         , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST00_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST00_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST00_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ECC_MODE               , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST00_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DONE                   , 13  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST00_DONE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL               , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE                , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST01_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST01_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_1ST_CMD          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST01_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_2ND_CMD          , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST01_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_3RD_CMD          , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST01_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_REV_MODE          , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST01_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_RAND_MODE         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST01_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE              , 25  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST01_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST01_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ECC_MODE               , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST01_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DONE                   , 29  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST01_DONE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL               , 30  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE                , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST02_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST02_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_1ST_CMD          , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST02_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_2ND_CMD          , 37  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST02_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_3RD_CMD          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST02_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_REV_MODE          , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST02_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_RAND_MODE         , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST02_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE              , 41  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST02_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST02_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ECC_MODE               , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST02_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DONE                   , 45  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST02_DONE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL               , 46  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE                , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST03_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST03_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_1ST_CMD          , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST03_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_2ND_CMD          , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST03_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_3RD_CMD          , 54  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST03_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_REV_MODE          , 55  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST03_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_RAND_MODE         , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST03_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE              , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST03_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST03_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ECC_MODE               , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST03_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DONE                   , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST03_DONE );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL               , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL_LEN );
+
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST04_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST04_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_1ST_CMD          , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST04_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_2ND_CMD          , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST04_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_3RD_CMD          , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST04_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_REV_MODE          , 7   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST04_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_RAND_MODE         , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST04_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST04_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST04_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ECC_MODE               , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST04_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DONE                   , 13  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST04_DONE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL               , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE                , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST05_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST05_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_1ST_CMD          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST05_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_2ND_CMD          , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST05_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_3RD_CMD          , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST05_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_REV_MODE          , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST05_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_RAND_MODE         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST05_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE              , 25  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST05_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST05_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ECC_MODE               , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST05_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DONE                   , 29  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST05_DONE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL               , 30  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE                , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST06_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST06_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_1ST_CMD          , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST06_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_2ND_CMD          , 37  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST06_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_3RD_CMD          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST06_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_REV_MODE          , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST06_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_RAND_MODE         , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST06_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE              , 41  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST06_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST06_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ECC_MODE               , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST06_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DONE                   , 45  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST06_DONE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL               , 46  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE                , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST07_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST07_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_1ST_CMD          , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST07_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_2ND_CMD          , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST07_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_3RD_CMD          , 54  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST07_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_REV_MODE          , 55  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST07_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_RAND_MODE         , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST07_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE              , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST07_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST07_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ECC_MODE               , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST07_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DONE                   , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST07_DONE );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL               , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL_LEN );
+
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST08_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST08_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_1ST_CMD          , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST08_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_2ND_CMD          , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST08_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_3RD_CMD          , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST08_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_REV_MODE          , 7   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST08_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_RAND_MODE         , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST08_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST08_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST08_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ECC_MODE               , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST08_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DONE                   , 13  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST08_DONE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL               , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE                , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST09_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST09_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_1ST_CMD          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST09_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_2ND_CMD          , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST09_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_3RD_CMD          , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST09_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_REV_MODE          , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST09_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_RAND_MODE         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST09_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE              , 25  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST09_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST09_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ECC_MODE               , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST09_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DONE                   , 29  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST09_DONE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL               , 30  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE                , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST10_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST10_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_1ST_CMD          , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST10_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_2ND_CMD          , 37  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST10_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_3RD_CMD          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST10_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_REV_MODE          , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST10_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_RAND_MODE         , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST10_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE              , 41  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST10_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST10_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ECC_MODE               , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST10_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DONE                   , 45  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST10_DONE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL               , 46  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE                , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST11_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST11_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_1ST_CMD          , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST11_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_2ND_CMD          , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST11_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_3RD_CMD          , 54  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST11_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_REV_MODE          , 55  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST11_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_RAND_MODE         , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST11_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE              , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST11_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST11_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ECC_MODE               , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST11_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DONE                   , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST11_DONE );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL               , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL_LEN );
+
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST12_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST12_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_1ST_CMD          , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST12_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_2ND_CMD          , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST12_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_3RD_CMD          , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST12_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_REV_MODE          , 7   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST12_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_RAND_MODE         , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST12_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST12_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST12_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ECC_MODE               , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST12_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DONE                   , 13  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST12_DONE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL               , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE                , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST13_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST13_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_1ST_CMD          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST13_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_2ND_CMD          , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST13_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_3RD_CMD          , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST13_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_REV_MODE          , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST13_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_RAND_MODE         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST13_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE              , 25  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST13_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST13_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ECC_MODE               , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST13_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DONE                   , 29  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST13_DONE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL               , 30  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE                , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST14_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST14_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_1ST_CMD          , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST14_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_2ND_CMD          , 37  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST14_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_3RD_CMD          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST14_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_REV_MODE          , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST14_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_RAND_MODE         , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST14_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE              , 41  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST14_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST14_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ECC_MODE               , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST14_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DONE                   , 45  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST14_DONE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL               , 46  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE                , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST15_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST15_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_1ST_CMD          , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST15_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_2ND_CMD          , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST15_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_3RD_CMD          , 54  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST15_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_REV_MODE          , 55  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST15_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_RAND_MODE         , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST15_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE              , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST15_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST15_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ECC_MODE               , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST15_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DONE                   , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST15_DONE );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL               , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL_LEN );
+
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST16_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST16_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_1ST_CMD          , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST16_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_2ND_CMD          , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST16_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_3RD_CMD          , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST16_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_REV_MODE          , 7   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST16_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_RAND_MODE         , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST16_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST16_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST16_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ECC_MODE               , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST16_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DONE                   , 13  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST16_DONE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL               , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE                , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST17_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST17_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_1ST_CMD          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST17_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_2ND_CMD          , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST17_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_3RD_CMD          , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST17_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_REV_MODE          , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST17_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_RAND_MODE         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST17_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE              , 25  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST17_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST17_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ECC_MODE               , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST17_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DONE                   , 29  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST17_DONE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL               , 30  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE                , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST18_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST18_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_1ST_CMD          , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST18_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_2ND_CMD          , 37  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST18_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_3RD_CMD          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST18_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_REV_MODE          , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST18_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_RAND_MODE         , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST18_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE              , 41  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST18_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST18_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ECC_MODE               , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST18_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DONE                   , 45  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST18_DONE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL               , 46  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE                , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST19_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST19_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_1ST_CMD          , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST19_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_2ND_CMD          , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST19_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_3RD_CMD          , 54  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST19_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_REV_MODE          , 55  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST19_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_RAND_MODE         , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST19_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE              , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST19_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST19_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ECC_MODE               , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST19_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DONE                   , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST19_DONE );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL               , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL_LEN );
+
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST20_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST20_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_1ST_CMD          , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST20_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_2ND_CMD          , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST20_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_3RD_CMD          , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST20_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_REV_MODE          , 7   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST20_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_RAND_MODE         , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST20_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST20_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST20_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ECC_MODE               , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST20_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DONE                   , 13  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST20_DONE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL               , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE                , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST21_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST21_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_1ST_CMD          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST21_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_2ND_CMD          , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST21_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_3RD_CMD          , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST21_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_REV_MODE          , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST21_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_RAND_MODE         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST21_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE              , 25  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST21_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST21_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ECC_MODE               , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST21_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DONE                   , 29  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST21_DONE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL               , 30  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE                , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST22_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST22_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_1ST_CMD          , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST22_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_2ND_CMD          , 37  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST22_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_3RD_CMD          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST22_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_REV_MODE          , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST22_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_RAND_MODE         , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST22_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE              , 41  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST22_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST22_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ECC_MODE               , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST22_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DONE                   , 45  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST22_DONE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL               , 46  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE                , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST23_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST23_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_1ST_CMD          , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST23_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_2ND_CMD          , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST23_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_3RD_CMD          , 54  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST23_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_REV_MODE          , 55  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST23_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_RAND_MODE         , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST23_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE              , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST23_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST23_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ECC_MODE               , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST23_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DONE                   , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST23_DONE );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL               , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL_LEN );
+
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST24_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST24_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_1ST_CMD          , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST24_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_2ND_CMD          , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST24_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_3RD_CMD          , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST24_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_REV_MODE          , 7   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST24_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_RAND_MODE         , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST24_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST24_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST24_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ECC_MODE               , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST24_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DONE                   , 13  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST24_DONE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL               , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE                , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST25_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST25_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_1ST_CMD          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST25_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_2ND_CMD          , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST25_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_3RD_CMD          , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST25_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_REV_MODE          , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST25_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_RAND_MODE         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST25_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE              , 25  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST25_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST25_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ECC_MODE               , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST25_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DONE                   , 29  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST25_DONE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL               , 30  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE                , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST26_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST26_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_1ST_CMD          , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST26_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_2ND_CMD          , 37  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST26_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_3RD_CMD          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST26_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_REV_MODE          , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST26_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_RAND_MODE         , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST26_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE              , 41  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST26_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST26_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ECC_MODE               , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST26_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DONE                   , 45  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST26_DONE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL               , 46  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE                , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST27_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST27_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_1ST_CMD          , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST27_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_2ND_CMD          , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST27_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_3RD_CMD          , 54  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST27_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_REV_MODE          , 55  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST27_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_RAND_MODE         , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST27_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE              , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST27_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST27_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ECC_MODE               , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST27_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DONE                   , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST27_DONE );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL               , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL_LEN );
+
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE                , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST28_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST28_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_1ST_CMD          , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST28_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_2ND_CMD          , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST28_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_3RD_CMD          , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST28_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_REV_MODE          , 7   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST28_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_RAND_MODE         , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST28_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE              , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST28_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST28_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ECC_MODE               , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST28_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DONE                   , 13  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST28_DONE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL               , 14  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE                , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST29_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST29_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_1ST_CMD          , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST29_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_2ND_CMD          , 21  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST29_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_3RD_CMD          , 22  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST29_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_REV_MODE          , 23  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST29_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_RAND_MODE         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST29_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE              , 25  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST29_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST29_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ECC_MODE               , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST29_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DONE                   , 29  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST29_DONE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL               , 30  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE                , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST30_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST30_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_1ST_CMD          , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST30_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_2ND_CMD          , 37  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST30_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_3RD_CMD          , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST30_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_REV_MODE          , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST30_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_RAND_MODE         , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST30_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE              , 41  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST30_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST30_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ECC_MODE               , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST30_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DONE                   , 45  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST30_DONE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL               , 46  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL_LEN );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE                , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST31_OP_TYPE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE_LEN            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST31_OP_TYPE_LEN );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_1ST_CMD          , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST31_COMPL_1ST_CMD );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_2ND_CMD          , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST31_COMPL_2ND_CMD );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_3RD_CMD          , 54  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST31_COMPL_3RD_CMD );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_REV_MODE          , 55  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST31_ADDR_REV_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_RAND_MODE         , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST31_ADDR_RAND_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE              , 57  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST31_DATA_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE_LEN          , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST31_DATA_MODE_LEN );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ECC_MODE               , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST31_ECC_MODE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DONE                   , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST31_DONE );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL               , 62  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL );
+REG64_FLD( MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL_LEN           , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL_LEN );
+
+REG64_FLD( MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP                         , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MIN_CMD_GAP );
+REG64_FLD( MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_LEN                     , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MIN_CMD_GAP_LEN );
+REG64_FLD( MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE                    , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MIN_GAP_TIMEBASE );
+REG64_FLD( MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER             , 13  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MIN_CMD_GAP_BLIND_STEER );
+REG64_FLD( MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER_LEN         , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MIN_CMD_GAP_BLIND_STEER_LEN );
+REG64_FLD( MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE_BLIND_STEER        , 25  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MIN_GAP_TIMEBASE_BLIND_STEER );
+REG64_FLD( MCBIST_MCBPARMQ_RESERVED_26_49                          , 26  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_26_49 );
+REG64_FLD( MCBIST_MCBPARMQ_RESERVED_26_49_LEN                      , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_26_49_LEN );
+REG64_FLD( MCBIST_MCBPARMQ_CFG_RANDCMD_WGT                         , 50  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANDCMD_WGT );
+REG64_FLD( MCBIST_MCBPARMQ_CFG_RANDCMD_WGT_LEN                     , 3   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANDCMD_WGT_LEN );
+REG64_FLD( MCBIST_MCBPARMQ_RESERVED_53_58                          , 53  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_53_58 );
+REG64_FLD( MCBIST_MCBPARMQ_RESERVED_53_58_LEN                      , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_53_58_LEN );
+REG64_FLD( MCBIST_MCBPARMQ_CFG_CLOCK_MONITOR_EN                    , 59  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CLOCK_MONITOR_EN );
+REG64_FLD( MCBIST_MCBPARMQ_CFG_EN_RANDCMD_GAP                      , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EN_RANDCMD_GAP );
+REG64_FLD( MCBIST_MCBPARMQ_CFG_RANDGAP_WGT                         , 61  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANDGAP_WGT );
+REG64_FLD( MCBIST_MCBPARMQ_CFG_RANDGAP_WGT_LEN                     , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RANDGAP_WGT_LEN );
+REG64_FLD( MCBIST_MCBPARMQ_CFG_BC4_EN                              , 63  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_BC4_EN );
+
+REG64_FLD( MCBIST_MCBRCRQ_RESERVED_0_31                            , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_31 );
+REG64_FLD( MCBIST_MCBRCRQ_RESERVED_0_31_LEN                        , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_31_LEN );
+REG64_FLD( MCBIST_MCBRCRQ_CFG_RUNTIME_MCBALL                       , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RUNTIME_MCBALL );
+REG64_FLD( MCBIST_MCBRCRQ_CFG_RUNTIME_SUBTEST                      , 33  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RUNTIME_SUBTEST );
+REG64_FLD( MCBIST_MCBRCRQ_CFG_RUNTIME_SUBTEST_LEN                  , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RUNTIME_SUBTEST_LEN );
+REG64_FLD( MCBIST_MCBRCRQ_CFG_RUNTIME_OVERHEAD                     , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RUNTIME_OVERHEAD );
+REG64_FLD( MCBIST_MCBRCRQ_RESERVED_39                              , 39  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39 );
+
+REG64_FLD( MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0                         , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DGEN_RNDD_SEED0 );
+REG64_FLD( MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0_LEN                     , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DGEN_RNDD_SEED0_LEN );
+REG64_FLD( MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1                         , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DGEN_RNDD_SEED1 );
+REG64_FLD( MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1_LEN                     , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DGEN_RNDD_SEED1_LEN );
+
+REG64_FLD( MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2                         , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DGEN_RNDD_SEED2 );
+REG64_FLD( MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2_LEN                     , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DGEN_RNDD_SEED2_LEN );
+REG64_FLD( MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING                  , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DGEN_RNDD_DATA_MAPPING );
+REG64_FLD( MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING_LEN              , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DGEN_RNDD_DATA_MAPPING_LEN );
+
+REG64_FLD( MCBIST_MCBSA0Q_CFG_START_ADDR_0                         , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_START_ADDR_0 );
+REG64_FLD( MCBIST_MCBSA0Q_CFG_START_ADDR_0_LEN                     , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_START_ADDR_0_LEN );
+
+REG64_FLD( MCBIST_MCBSA1Q_CFG_START_ADDR_1                         , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_START_ADDR_1 );
+REG64_FLD( MCBIST_MCBSA1Q_CFG_START_ADDR_1_LEN                     , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_START_ADDR_1_LEN );
+
+REG64_FLD( MCBIST_MCBSA2Q_CFG_START_ADDR_2                         , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_START_ADDR_2 );
+REG64_FLD( MCBIST_MCBSA2Q_CFG_START_ADDR_2_LEN                     , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_START_ADDR_2_LEN );
+
+REG64_FLD( MCBIST_MCBSA3Q_CFG_START_ADDR_3                         , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_START_ADDR_3 );
+REG64_FLD( MCBIST_MCBSA3Q_CFG_START_ADDR_3_LEN                     , 38  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_START_ADDR_3_LEN );
+
+REG64_FLD( MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR   , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR );
+REG64_FLD( MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR_LEN , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR_LEN );
+REG64_FLD( MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_MCBIST_SUBTEST_NUM_INDICATOR );
+REG64_FLD( MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR_LEN        , 5   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_MCBIST_SUBTEST_NUM_INDICATOR_LEN );
+REG64_FLD( MCBIST_MCBSTATQ_RESERVED_9_15                           , 9   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_9_15 );
+REG64_FLD( MCBIST_MCBSTATQ_RESERVED_9_15_LEN                       , 7   , SH_UNT_MCBIST   , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_9_15_LEN );
+
+REG64_FLD( MCS_PORT02_MCBUSYQ_ENABLE_BUSY_COUNTERS                 , 0   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_BUSY_COUNTERS );
+REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT           , 1   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_WINDOW_SELECT );
+REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_LEN       , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_WINDOW_SELECT_LEN );
+REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD0              , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_THRESHOLD0 );
+REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_LEN          , 10  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_THRESHOLD0_LEN );
+REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD1              , 14  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_THRESHOLD1 );
+REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_LEN          , 10  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_THRESHOLD1_LEN );
+REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD2              , 24  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_THRESHOLD2 );
+REG64_FLD( MCS_PORT02_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_LEN          , 10  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_THRESHOLD2_LEN );
+REG64_FLD( MCS_PORT02_MCBUSYQ_ENABLE_AGGRESSIVE_BUSY               , 34  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_AGGRESSIVE_BUSY );
+REG64_FLD( MCS_PORT02_MCBUSYQ_RSVD_35_43                           , 35  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RSVD_35_43 );
+REG64_FLD( MCS_PORT02_MCBUSYQ_RSVD_35_43_LEN                       , 9   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RSVD_35_43_LEN );
+
+REG64_FLD( MCS_PORT13_MCBUSYQ_ENABLE_BUSY_COUNTERS                 , 0   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_BUSY_COUNTERS );
+REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT           , 1   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_WINDOW_SELECT );
+REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_LEN       , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_WINDOW_SELECT_LEN );
+REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD0              , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_THRESHOLD0 );
+REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_LEN          , 10  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_THRESHOLD0_LEN );
+REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD1              , 14  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_THRESHOLD1 );
+REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_LEN          , 10  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_THRESHOLD1_LEN );
+REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD2              , 24  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_THRESHOLD2 );
+REG64_FLD( MCS_PORT13_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_LEN          , 10  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BUSY_COUNTER_THRESHOLD2_LEN );
+REG64_FLD( MCS_PORT13_MCBUSYQ_ENABLE_AGGRESSIVE_BUSY               , 34  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_AGGRESSIVE_BUSY );
+REG64_FLD( MCS_PORT13_MCBUSYQ_RSVD_35_43                           , 35  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RSVD_35_43 );
+REG64_FLD( MCS_PORT13_MCBUSYQ_RSVD_35_43_LEN                       , 9   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RSVD_35_43_LEN );
+
+REG64_FLD( MCBIST_MCB_CNTLQ_START                                  , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_START      );
+REG64_FLD( MCBIST_MCB_CNTLQ_STOP                                   , 1   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP       );
+REG64_FLD( MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL                       , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBCNTL_PORT_SEL );
+REG64_FLD( MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL_LEN                   , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCBCNTL_PORT_SEL_LEN );
+REG64_FLD( MCBIST_MCB_CNTLQ_RESET_TRAP_CNFG                        , 6   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESET_TRAP_CNFG );
+REG64_FLD( MCBIST_MCB_CNTLQ_RESET_ERROR_LOGS                       , 7   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESET_ERROR_LOGS );
+REG64_FLD( MCBIST_MCB_CNTLQ_RESUME_FROM_PAUSE                      , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESUME_FROM_PAUSE );
+
+REG64_FLD( MCBIST_MCB_CNTLSTATQ_IP                                 , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_IP         );
+REG64_FLD( MCBIST_MCB_CNTLSTATQ_DONE                               , 1   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DONE       );
+REG64_FLD( MCBIST_MCB_CNTLSTATQ_FAIL                               , 2   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FAIL       );
+
+REG64_FLD( MCS_MCDBG0_DEBUG_BUS_0_63                               , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DEBUG_BUS_0_63 );
+REG64_FLD( MCS_MCDBG0_DEBUG_BUS_0_63_LEN                           , 64  , SH_UNT_MCS      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DEBUG_BUS_0_63_LEN );
+
+REG64_FLD( MCS_MCDBG1_DEBUG_BUS_64_87                              , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DEBUG_BUS_64_87 );
+REG64_FLD( MCS_MCDBG1_DEBUG_BUS_64_87_LEN                          , 24  , SH_UNT_MCS      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DEBUG_BUS_64_87_LEN );
+REG64_FLD( MCS_MCDBG1_WRQ0_EMPTY                                   , 24  , SH_UNT_MCS      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRQ0_EMPTY );
+REG64_FLD( MCS_MCDBG1_WRQ1_EMPTY                                   , 25  , SH_UNT_MCS      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRQ1_EMPTY );
+
+REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE0_SEL                           , 0   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE0_SEL  );
+REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE0_SEL_LEN                       , 2   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE0_SEL_LEN );
+REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE1_SEL                           , 2   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE1_SEL  );
+REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE1_SEL_LEN                       , 2   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE1_SEL_LEN );
+REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE2_SEL                           , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE2_SEL  );
+REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE2_SEL_LEN                       , 2   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE2_SEL_LEN );
+REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE3_SEL                           , 6   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE3_SEL  );
+REG64_FLD( MCS_PORT02_MCEBUSCL_BYTE3_SEL_LEN                       , 2   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE3_SEL_LEN );
+REG64_FLD( MCS_PORT02_MCEBUSCL_LAT_THRESHA                         , 8   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_LAT_THRESHA );
+REG64_FLD( MCS_PORT02_MCEBUSCL_LAT_THRESHA_LEN                     , 8   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_LAT_THRESHA_LEN );
+REG64_FLD( MCS_PORT02_MCEBUSCL_LAT_THRESHB                         , 16  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_LAT_THRESHB );
+REG64_FLD( MCS_PORT02_MCEBUSCL_LAT_THRESHB_LEN                     , 8   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_LAT_THRESHB_LEN );
+REG64_FLD( MCS_PORT02_MCEBUSCL_LAT_THRESHC                         , 24  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_LAT_THRESHC );
+REG64_FLD( MCS_PORT02_MCEBUSCL_LAT_THRESHC_LEN                     , 8   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_LAT_THRESHC_LEN );
+REG64_FLD( MCS_PORT02_MCEBUSCL_SCOM20A_SEL                         , 32  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_SCOM20A_SEL );
+
+REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE0_SEL                           , 0   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE0_SEL  );
+REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE0_SEL_LEN                       , 2   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE0_SEL_LEN );
+REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE1_SEL                           , 2   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE1_SEL  );
+REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE1_SEL_LEN                       , 2   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE1_SEL_LEN );
+REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE2_SEL                           , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE2_SEL  );
+REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE2_SEL_LEN                       , 2   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE2_SEL_LEN );
+REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE3_SEL                           , 6   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE3_SEL  );
+REG64_FLD( MCS_PORT13_MCEBUSCL_BYTE3_SEL_LEN                       , 2   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BYTE3_SEL_LEN );
+REG64_FLD( MCS_PORT13_MCEBUSCL_LAT_THRESHA                         , 8   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_LAT_THRESHA );
+REG64_FLD( MCS_PORT13_MCEBUSCL_LAT_THRESHA_LEN                     , 8   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_LAT_THRESHA_LEN );
+REG64_FLD( MCS_PORT13_MCEBUSCL_LAT_THRESHB                         , 16  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_LAT_THRESHB );
+REG64_FLD( MCS_PORT13_MCEBUSCL_LAT_THRESHB_LEN                     , 8   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_LAT_THRESHB_LEN );
+REG64_FLD( MCS_PORT13_MCEBUSCL_LAT_THRESHC                         , 24  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_LAT_THRESHC );
+REG64_FLD( MCS_PORT13_MCEBUSCL_LAT_THRESHC_LEN                     , 8   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_LAT_THRESHC_LEN );
+REG64_FLD( MCS_PORT13_MCEBUSCL_SCOM20A_SEL                         , 32  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_SCOM20A_SEL );
+
+REG64_FLD( MCS_PORT13_MCEBUSEN0_EVENT_BUS_SELECTS                  , 0   , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT_BUS_SELECTS );
+REG64_FLD( MCS_PORT13_MCEBUSEN0_EVENT_BUS_SELECTS_LEN              , 64  , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT_BUS_SELECTS_LEN );
+
+REG64_FLD( MCS_PORT13_MCEBUSEN1_EVENT_BUS_SELECTS                  , 0   , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT_BUS_SELECTS );
+REG64_FLD( MCS_PORT13_MCEBUSEN1_EVENT_BUS_SELECTS_LEN              , 64  , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT_BUS_SELECTS_LEN );
+
+REG64_FLD( MCS_PORT13_MCEBUSEN2_EVENT_BUS_SELECTS                  , 0   , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT_BUS_SELECTS );
+REG64_FLD( MCS_PORT13_MCEBUSEN2_EVENT_BUS_SELECTS_LEN              , 64  , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT_BUS_SELECTS_LEN );
+
+REG64_FLD( MCS_PORT13_MCEBUSEN3_EVENT_BUS_EN                       , 0   , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT_BUS_EN );
+REG64_FLD( MCS_PORT13_MCEBUSEN3_EVENT_BUS_EN_LEN                   , 16  , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT_BUS_EN_LEN );
+REG64_FLD( MCS_PORT13_MCEBUSEN3_EVENT_BUS_ENABLE                   , 16  , SH_UNT_MCS_PORT13, SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT_BUS_ENABLE );
+
+REG64_FLD( MCS_PORT02_MCEPSQ_JITTER_EPSILON                        , 0   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_JITTER_EPSILON );
+REG64_FLD( MCS_PORT02_MCEPSQ_JITTER_EPSILON_LEN                    , 8   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_JITTER_EPSILON_LEN );
+REG64_FLD( MCS_PORT02_MCEPSQ_LOCAL_NODE_EPSILON                    , 8   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_LOCAL_NODE_EPSILON );
+REG64_FLD( MCS_PORT02_MCEPSQ_LOCAL_NODE_EPSILON_LEN                , 8   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_LOCAL_NODE_EPSILON_LEN );
+REG64_FLD( MCS_PORT02_MCEPSQ_NEAR_NODAL_EPSILON                    , 16  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NEAR_NODAL_EPSILON );
+REG64_FLD( MCS_PORT02_MCEPSQ_NEAR_NODAL_EPSILON_LEN                , 8   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NEAR_NODAL_EPSILON_LEN );
+REG64_FLD( MCS_PORT02_MCEPSQ_GROUP_EPSILON                         , 24  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_GROUP_EPSILON );
+REG64_FLD( MCS_PORT02_MCEPSQ_GROUP_EPSILON_LEN                     , 8   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_GROUP_EPSILON_LEN );
+REG64_FLD( MCS_PORT02_MCEPSQ_REMOTE_NODAL_EPSILON                  , 32  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_REMOTE_NODAL_EPSILON );
+REG64_FLD( MCS_PORT02_MCEPSQ_REMOTE_NODAL_EPSILON_LEN              , 8   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_REMOTE_NODAL_EPSILON_LEN );
+REG64_FLD( MCS_PORT02_MCEPSQ_VECTOR_GROUP_EPSILON                  , 40  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_VECTOR_GROUP_EPSILON );
+REG64_FLD( MCS_PORT02_MCEPSQ_VECTOR_GROUP_EPSILON_LEN              , 8   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_VECTOR_GROUP_EPSILON_LEN );
+
+REG64_FLD( MCS_PORT13_MCEPSQ_JITTER_EPSILON                        , 0   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_JITTER_EPSILON );
+REG64_FLD( MCS_PORT13_MCEPSQ_JITTER_EPSILON_LEN                    , 8   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_JITTER_EPSILON_LEN );
+REG64_FLD( MCS_PORT13_MCEPSQ_LOCAL_NODE_EPSILON                    , 8   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_LOCAL_NODE_EPSILON );
+REG64_FLD( MCS_PORT13_MCEPSQ_LOCAL_NODE_EPSILON_LEN                , 8   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_LOCAL_NODE_EPSILON_LEN );
+REG64_FLD( MCS_PORT13_MCEPSQ_NEAR_NODAL_EPSILON                    , 16  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NEAR_NODAL_EPSILON );
+REG64_FLD( MCS_PORT13_MCEPSQ_NEAR_NODAL_EPSILON_LEN                , 8   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NEAR_NODAL_EPSILON_LEN );
+REG64_FLD( MCS_PORT13_MCEPSQ_GROUP_EPSILON                         , 24  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_GROUP_EPSILON );
+REG64_FLD( MCS_PORT13_MCEPSQ_GROUP_EPSILON_LEN                     , 8   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_GROUP_EPSILON_LEN );
+REG64_FLD( MCS_PORT13_MCEPSQ_REMOTE_NODAL_EPSILON                  , 32  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_REMOTE_NODAL_EPSILON );
+REG64_FLD( MCS_PORT13_MCEPSQ_REMOTE_NODAL_EPSILON_LEN              , 8   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_REMOTE_NODAL_EPSILON_LEN );
+REG64_FLD( MCS_PORT13_MCEPSQ_VECTOR_GROUP_EPSILON                  , 40  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_VECTOR_GROUP_EPSILON );
+REG64_FLD( MCS_PORT13_MCEPSQ_VECTOR_GROUP_EPSILON_LEN              , 8   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_VECTOR_GROUP_EPSILON_LEN );
+
+REG64_FLD( MCS_MCERPT0_DATA                                        , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( MCS_MCERPT0_DATA_LEN                                    , 63  , SH_UNT_MCS      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( MCS_MCERPT1_DATA                                        , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( MCS_MCERPT1_DATA_LEN                                    , 63  , SH_UNT_MCS      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( MCS_MCERPT2_DATA                                        , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( MCS_MCERPT2_DATA_LEN                                    , 7   , SH_UNT_MCS      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( MCS_PORT02_MCERRINJ_WDF_ERR_INJECT0                     , 0   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_WDF_ERR_INJECT0 );
+REG64_FLD( MCS_PORT02_MCERRINJ_WDF_ERR_INJECT0_LEN                 , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_WDF_ERR_INJECT0_LEN );
+REG64_FLD( MCS_PORT02_MCERRINJ_READ_ERR_INJECT0                    , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_READ_ERR_INJECT0 );
+REG64_FLD( MCS_PORT02_MCERRINJ_READ_ERR_INJECT0_LEN                , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_READ_ERR_INJECT0_LEN );
+REG64_FLD( MCS_PORT02_MCERRINJ_WRITE_ERR_INJECT0                   , 8   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_WRITE_ERR_INJECT0 );
+REG64_FLD( MCS_PORT02_MCERRINJ_WRITE_ERR_INJECT0_LEN               , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_WRITE_ERR_INJECT0_LEN );
+REG64_FLD( MCS_PORT02_MCERRINJ_RCMD_ERR_INJ                        , 12  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RCMD_ERR_INJ );
+REG64_FLD( MCS_PORT02_MCERRINJ_PF_PROMOTE_ERR_INJ                  , 13  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_PROMOTE_ERR_INJ );
+REG64_FLD( MCS_PORT02_MCERRINJ_READ_PAR_NOT_SEQ                    , 14  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_READ_PAR_NOT_SEQ );
+REG64_FLD( MCS_PORT02_MCERRINJ_RESET_KEEPER                        , 15  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESET_KEEPER );
+
+REG64_FLD( MCS_PORT13_MCERRINJ_WDF_ERR_INJECT0                     , 0   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_WDF_ERR_INJECT0 );
+REG64_FLD( MCS_PORT13_MCERRINJ_WDF_ERR_INJECT0_LEN                 , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_WDF_ERR_INJECT0_LEN );
+REG64_FLD( MCS_PORT13_MCERRINJ_READ_ERR_INJECT0                    , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_READ_ERR_INJECT0 );
+REG64_FLD( MCS_PORT13_MCERRINJ_READ_ERR_INJECT0_LEN                , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_READ_ERR_INJECT0_LEN );
+REG64_FLD( MCS_PORT13_MCERRINJ_WRITE_ERR_INJECT0                   , 8   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_WRITE_ERR_INJECT0 );
+REG64_FLD( MCS_PORT13_MCERRINJ_WRITE_ERR_INJECT0_LEN               , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_WRITE_ERR_INJECT0_LEN );
+REG64_FLD( MCS_PORT13_MCERRINJ_RCMD_ERR_INJ                        , 12  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RCMD_ERR_INJ );
+REG64_FLD( MCS_PORT13_MCERRINJ_PF_PROMOTE_ERR_INJ                  , 13  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_PROMOTE_ERR_INJ );
+REG64_FLD( MCS_PORT13_MCERRINJ_READ_PAR_NOT_SEQ                    , 14  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_READ_PAR_NOT_SEQ );
+REG64_FLD( MCS_PORT13_MCERRINJ_RESET_KEEPER                        , 15  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESET_KEEPER );
+
+REG64_FLD( MCS_MCFGP_VALID                                         , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( MCS_MCFGP_MC_CHANNELS_PER_GROUP                         , 1   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MC_CHANNELS_PER_GROUP );
+REG64_FLD( MCS_MCFGP_MC_CHANNELS_PER_GROUP_LEN                     , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MC_CHANNELS_PER_GROUP_LEN );
+REG64_FLD( MCS_MCFGP_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION         , 5   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION );
+REG64_FLD( MCS_MCFGP_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION_LEN     , 3   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION_LEN );
+REG64_FLD( MCS_MCFGP_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION         , 8   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION );
+REG64_FLD( MCS_MCFGP_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION_LEN     , 3   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION_LEN );
+REG64_FLD( MCS_MCFGP_RESERVED_11_12                                , 11  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_11_12 );
+REG64_FLD( MCS_MCFGP_RESERVED_11_12_LEN                            , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_11_12_LEN );
+REG64_FLD( MCS_MCFGP_GROUP_SIZE                                    , 13  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_GROUP_SIZE );
+REG64_FLD( MCS_MCFGP_GROUP_SIZE_LEN                                , 11  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_GROUP_SIZE_LEN );
+REG64_FLD( MCS_MCFGP_GROUP_BASE_ADDRESS                            , 24  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_GROUP_BASE_ADDRESS );
+REG64_FLD( MCS_MCFGP_GROUP_BASE_ADDRESS_LEN                        , 24  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_GROUP_BASE_ADDRESS_LEN );
+
+REG64_FLD( MCS_MCFGPA_HOLE0_VALID                                  , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE0_VALID );
+REG64_FLD( MCS_MCFGPA_RESERVED_1                                   , 1   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1 );
+REG64_FLD( MCS_MCFGPA_HOLE0_LOWER_ADDRESS                          , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE0_LOWER_ADDRESS );
+REG64_FLD( MCS_MCFGPA_HOLE0_LOWER_ADDRESS_LEN                      , 10  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE0_LOWER_ADDRESS_LEN );
+REG64_FLD( MCS_MCFGPA_RESERVED_12_13                               , 12  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_12_13 );
+REG64_FLD( MCS_MCFGPA_RESERVED_12_13_LEN                           , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_12_13_LEN );
+REG64_FLD( MCS_MCFGPA_HOLE0_UPPER_ADDRESS                          , 14  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE0_UPPER_ADDRESS );
+REG64_FLD( MCS_MCFGPA_HOLE0_UPPER_ADDRESS_LEN                      , 10  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE0_UPPER_ADDRESS_LEN );
+REG64_FLD( MCS_MCFGPA_HOLE1_VALID                                  , 24  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE1_VALID );
+REG64_FLD( MCS_MCFGPA_RESERVED_25                                  , 25  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_25 );
+REG64_FLD( MCS_MCFGPA_HOLE1_LOWER_ADDRESS                          , 26  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE1_LOWER_ADDRESS );
+REG64_FLD( MCS_MCFGPA_HOLE1_LOWER_ADDRESS_LEN                      , 10  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE1_LOWER_ADDRESS_LEN );
+REG64_FLD( MCS_MCFGPA_RESERVED_36_37                               , 36  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_36_37 );
+REG64_FLD( MCS_MCFGPA_RESERVED_36_37_LEN                           , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_36_37_LEN );
+REG64_FLD( MCS_MCFGPA_HOLE1_UPPER_ADDRESS                          , 38  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE1_UPPER_ADDRESS );
+REG64_FLD( MCS_MCFGPA_HOLE1_UPPER_ADDRESS_LEN                      , 10  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE1_UPPER_ADDRESS_LEN );
+
+REG64_FLD( MCS_MCFGPM_VALID                                        , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( MCS_MCFGPM_RESERVED_1_12                                , 1   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_12 );
+REG64_FLD( MCS_MCFGPM_RESERVED_1_12_LEN                            , 12  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_12_LEN );
+REG64_FLD( MCS_MCFGPM_GROUP_SIZE                                   , 13  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_GROUP_SIZE );
+REG64_FLD( MCS_MCFGPM_GROUP_SIZE_LEN                               , 11  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_GROUP_SIZE_LEN );
+REG64_FLD( MCS_MCFGPM_GROUP_BASE_ADDRESS                           , 24  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_GROUP_BASE_ADDRESS );
+REG64_FLD( MCS_MCFGPM_GROUP_BASE_ADDRESS_LEN                       , 24  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_GROUP_BASE_ADDRESS_LEN );
+
+REG64_FLD( MCS_MCFGPMA_HOLE0_VALID                                 , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE0_VALID );
+REG64_FLD( MCS_MCFGPMA_RESERVED_1                                  , 1   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1 );
+REG64_FLD( MCS_MCFGPMA_HOLE0_LOWER_ADDRESS                         , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE0_LOWER_ADDRESS );
+REG64_FLD( MCS_MCFGPMA_HOLE0_LOWER_ADDRESS_LEN                     , 10  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE0_LOWER_ADDRESS_LEN );
+REG64_FLD( MCS_MCFGPMA_RESERVED_12_13                              , 12  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_12_13 );
+REG64_FLD( MCS_MCFGPMA_RESERVED_12_13_LEN                          , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_12_13_LEN );
+REG64_FLD( MCS_MCFGPMA_HOLE0_UPPER_ADDRESS                         , 14  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE0_UPPER_ADDRESS );
+REG64_FLD( MCS_MCFGPMA_HOLE0_UPPER_ADDRESS_LEN                     , 10  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE0_UPPER_ADDRESS_LEN );
+REG64_FLD( MCS_MCFGPMA_HOLE1_VALID                                 , 24  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE1_VALID );
+REG64_FLD( MCS_MCFGPMA_RESERVED_25                                 , 25  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_25 );
+REG64_FLD( MCS_MCFGPMA_HOLE1_LOWER_ADDRESS                         , 26  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE1_LOWER_ADDRESS );
+REG64_FLD( MCS_MCFGPMA_HOLE1_LOWER_ADDRESS_LEN                     , 10  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE1_LOWER_ADDRESS_LEN );
+REG64_FLD( MCS_MCFGPMA_RESERVED_36_37                              , 36  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_36_37 );
+REG64_FLD( MCS_MCFGPMA_RESERVED_36_37_LEN                          , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_36_37_LEN );
+REG64_FLD( MCS_MCFGPMA_HOLE1_UPPER_ADDRESS                         , 38  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE1_UPPER_ADDRESS );
+REG64_FLD( MCS_MCFGPMA_HOLE1_UPPER_ADDRESS_LEN                     , 10  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HOLE1_UPPER_ADDRESS_LEN );
+
+REG64_FLD( MCS_MCFIR_MC_INTERNAL_RECOVERABLE_ERROR                 , 0   , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MC_INTERNAL_RECOVERABLE_ERROR );
+REG64_FLD( MCS_MCFIR_MC_INTERNAL_NONRECOVERABLE_ERROR              , 1   , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MC_INTERNAL_NONRECOVERABLE_ERROR );
+REG64_FLD( MCS_MCFIR_POWERBUS_PROTOCOL_ERROR                       , 2   , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_POWERBUS_PROTOCOL_ERROR );
+REG64_FLD( MCS_MCFIR_INBAND_BAR_HIT_WITH_INCORRECT_TTYPE           , 3   , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_INBAND_BAR_HIT_WITH_INCORRECT_TTYPE );
+REG64_FLD( MCS_MCFIR_MULTIPLE_BAR                                  , 4   , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MULTIPLE_BAR );
+REG64_FLD( MCS_MCFIR_INVALID_ADDRESS                               , 5   , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_INVALID_ADDRESS );
+REG64_FLD( MCS_MCFIR_HA_ILLEGAL_CONSUMER_ACCESS                    , 6   , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_HA_ILLEGAL_CONSUMER_ACCESS );
+REG64_FLD( MCS_MCFIR_HA_ILLEGAL_PRODUCER_ACCESS                    , 7   , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_HA_ILLEGAL_PRODUCER_ACCESS );
+REG64_FLD( MCS_MCFIR_COMMAND_LIST_TIMEOUT                          , 8   , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMMAND_LIST_TIMEOUT );
+REG64_FLD( MCS_MCFIR_CHANNEL_0_TIMEOUT_ERROR                       , 9   , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_CHANNEL_0_TIMEOUT_ERROR );
+REG64_FLD( MCS_MCFIR_CHANNEL_1_TIMEOUT_ERROR                       , 10  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_CHANNEL_1_TIMEOUT_ERROR );
+REG64_FLD( MCS_MCFIR_MCS_WAT0                                      , 11  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCS_WAT0   );
+REG64_FLD( MCS_MCFIR_MCS_WAT1                                      , 12  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCS_WAT1   );
+REG64_FLD( MCS_MCFIR_MCS_WAT2                                      , 13  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCS_WAT2   );
+REG64_FLD( MCS_MCFIR_MCS_WAT3                                      , 14  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCS_WAT3   );
+REG64_FLD( MCS_MCFIR_MIRROR_ACTION_OCCURRED                        , 15  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MIRROR_ACTION_OCCURRED );
+REG64_FLD( MCS_MCFIR_CENTAUR_SYNC_COMMAND_DETECTED                 , 16  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_CENTAUR_SYNC_COMMAND_DETECTED );
+REG64_FLD( MCS_MCFIR_MS_WAT_DEBUG_CONFIG_REG_ERROR                 , 17  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MS_WAT_DEBUG_CONFIG_REG_ERROR );
+REG64_FLD( MCS_MCFIR_RESERVED18                                    , 18  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED18 );
+REG64_FLD( MCS_MCFIR_RESERVED19                                    , 19  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED19 );
+REG64_FLD( MCS_MCFIR_RESERVED20                                    , 20  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED20 );
+REG64_FLD( MCS_MCFIR_RESERVED21                                    , 21  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED21 );
+REG64_FLD( MCS_MCFIR_RESERVED22                                    , 22  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED22 );
+REG64_FLD( MCS_MCFIR_RESERVED23                                    , 23  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED23 );
+REG64_FLD( MCS_MCFIR_INTERNAL_SCOM_ERROR                           , 24  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_SCOM_ERROR );
+REG64_FLD( MCS_MCFIR_INTERNAL_SCOM_ERROR_CLONE                     , 25  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_SCOM_ERROR_CLONE );
+
+REG64_FLD( MCS_MCFIRACT0_ACTION_0                                  , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION_0   );
+REG64_FLD( MCS_MCFIRACT0_ACTION_0_LEN                              , 26  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION_0_LEN );
+
+REG64_FLD( MCS_MCFIRACT1_ACTION_1                                  , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION_1   );
+REG64_FLD( MCS_MCFIRACT1_ACTION_1_LEN                              , 26  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION_1_LEN );
+
+REG64_FLD( MCS_MCFIRMASK_FIR_MASK                                  , 0   , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_MASK   );
+REG64_FLD( MCS_MCFIRMASK_FIR_MASK_LEN                              , 26  , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_MASK_LEN );
+
+REG64_FLD( MCS_MCLFSR_RETRY_LPC_LFSR_SELECT                        , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RETRY_LPC_LFSR_SELECT );
+REG64_FLD( MCS_MCLFSR_RETRY_LPC_LFSR_SELECT_LEN                    , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RETRY_LPC_LFSR_SELECT_LEN );
+REG64_FLD( MCS_MCLFSR_RESERVED2_15                                 , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED2_15 );
+REG64_FLD( MCS_MCLFSR_RESERVED2_15_LEN                             , 14  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED2_15_LEN );
+
+REG64_FLD( MCS_MCMODE0_CENTAUR_MODE                                , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CENTAUR_MODE );
+REG64_FLD( MCS_MCMODE0_RESERVED1                                   , 1   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_CP_ME                       , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CENTAURP_ENABLE_CP_ME );
+REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_NEW_AMO                     , 3   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CENTAURP_ENABLE_NEW_AMO );
+REG64_FLD( MCS_MCMODE0_CENTAURP_INBAND_IS_63                       , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CENTAURP_INBAND_IS_63 );
+REG64_FLD( MCS_MCMODE0_SYNC_MODE                                   , 5   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_MODE  );
+REG64_FLD( MCS_MCMODE0_ASYNC_MODE                                  , 6   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ASYNC_MODE );
+REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_ECRESP                      , 7   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CENTAURP_ENABLE_ECRESP );
+REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_DYNAMIC_WRBUF_ALLOC         , 8   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CENTAURP_ENABLE_DYNAMIC_WRBUF_ALLOC );
+REG64_FLD( MCS_MCMODE0_ENABLE_64_128B_READ                         , 9   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_64_128B_READ );
+REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_CENTAURP_CMD                , 10  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CENTAURP_ENABLE_CENTAURP_CMD );
+REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_BYPASS_CMD                  , 11  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CENTAURP_ENABLE_BYPASS_CMD );
+REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_CR_SIDEBAND                 , 12  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CENTAURP_ENABLE_CR_SIDEBAND );
+REG64_FLD( MCS_MCMODE0_CENTAURP_ENABLE_DTAG_CR                     , 13  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CENTAURP_ENABLE_DTAG_CR );
+REG64_FLD( MCS_MCMODE0_EN_CHARB_STALL                              , 14  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_EN_CHARB_STALL );
+REG64_FLD( MCS_MCMODE0_SYNC_FENCE                                  , 15  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_FENCE );
+REG64_FLD( MCS_MCMODE0_ECRESP_HASH_MODE                            , 16  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECRESP_HASH_MODE );
+REG64_FLD( MCS_MCMODE0_FORCE_ANY_CL_ACTIVE                         , 17  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_ANY_CL_ACTIVE );
+REG64_FLD( MCS_MCMODE0_FORCE_ANY_BAR_ACTIVE                        , 18  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_ANY_BAR_ACTIVE );
+REG64_FLD( MCS_MCMODE0_MCS_RESET_KEEPER                            , 19  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCS_RESET_KEEPER );
+REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_SYNC                         , 20  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_CENTAUR_SYNC );
+REG64_FLD( MCS_MCMODE0_ENABLE_EMER_THROTTLE                        , 21  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_EMER_THROTTLE );
+REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_CHECKSTOP_COMMAND            , 22  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_CENTAUR_CHECKSTOP_COMMAND );
+REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_TRACESTOP_COMMAND            , 23  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_CENTAUR_TRACESTOP_COMMAND );
+REG64_FLD( MCS_MCMODE0_ENABLE_ENABLE_CRESP_PE                      , 24  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_ENABLE_CRESP_PE );
+REG64_FLD( MCS_MCMODE0_RESERVED25                                  , 25  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED25 );
+REG64_FLD( MCS_MCMODE0_RESERVED26                                  , 26  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED26 );
+REG64_FLD( MCS_MCMODE0_RESERVED27                                  , 27  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED27 );
+REG64_FLD( MCS_MCMODE0_RESERVED28                                  , 28  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED28 );
+REG64_FLD( MCS_MCMODE0_MCMODE0_64B_WR_IS_PWRT                      , 29  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCMODE0_64B_WR_IS_PWRT );
+REG64_FLD( MCS_MCMODE0_CL_GLOBAL_DISABLE                           , 30  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CL_GLOBAL_DISABLE );
+REG64_FLD( MCS_MCMODE0_CL_GLOBAL_DISABLE_LEN                       , 10  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CL_GLOBAL_DISABLE_LEN );
+REG64_FLD( MCS_MCMODE0_CL_FINE_DISABLE                             , 40  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CL_FINE_DISABLE );
+REG64_FLD( MCS_MCMODE0_CL_FINE_DISABLE_LEN                         , 7   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CL_FINE_DISABLE_LEN );
+REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_PERFMON_START_COMMAND        , 47  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_CENTAUR_PERFMON_START_COMMAND );
+REG64_FLD( MCS_MCMODE0_ENABLE_CENTAUR_PERFMON_STOP_COMMAND         , 48  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_CENTAUR_PERFMON_STOP_COMMAND );
+REG64_FLD( MCS_MCMODE0_SCOM_PERFMON_START_COMMAND                  , 49  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SCOM_PERFMON_START_COMMAND );
+REG64_FLD( MCS_MCMODE0_SCOM_PERFMON_STOP_COMMAND                   , 50  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SCOM_PERFMON_STOP_COMMAND );
+REG64_FLD( MCS_MCMODE0_DISABLE_PERFMON_RESET_ON_START              , 51  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_PERFMON_RESET_ON_START );
+REG64_FLD( MCS_MCMODE0_RESERVED52_55                               , 52  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED52_55 );
+REG64_FLD( MCS_MCMODE0_RESERVED52_55_LEN                           , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED52_55_LEN );
+REG64_FLD( MCS_MCMODE0_GENERATE_MPIPL_SEQUENCE                     , 56  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_GENERATE_MPIPL_SEQUENCE );
+REG64_FLD( MCS_MCMODE0_RESERVED57_63                               , 57  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED57_63 );
+REG64_FLD( MCS_MCMODE0_RESERVED57_63_LEN                           , 7   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED57_63_LEN );
+
+REG64_FLD( MCS_MCMODE1_DISABLE_HIGH_PRIORITY                       , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_HIGH_PRIORITY );
+REG64_FLD( MCS_MCMODE1_DISABLE_HIGH_PRIORITY_LEN                   , 10  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_HIGH_PRIORITY_LEN );
+REG64_FLD( MCS_MCMODE1_DISABLE_FP_M_BIT                            , 10  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_FP_M_BIT );
+REG64_FLD( MCS_MCMODE1_DISABLE_CRC_ECC_BYPASS                      , 11  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_CRC_ECC_BYPASS );
+REG64_FLD( MCS_MCMODE1_DISABLE_CRC_ECC_BYPASS_LEN                  , 6   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_CRC_ECC_BYPASS_LEN );
+REG64_FLD( MCS_MCMODE1_DISABLE_CRC_ECC_FP_BYPASS                   , 17  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_CRC_ECC_FP_BYPASS );
+REG64_FLD( MCS_MCMODE1_ENABLE_CRC_ECC_BPASS_NODAL_ONLY             , 18  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_CRC_ECC_BPASS_NODAL_ONLY );
+REG64_FLD( MCS_MCMODE1_DISABLE_SPEC_SOURCE_SCOPE                   , 19  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_SPEC_SOURCE_SCOPE );
+REG64_FLD( MCS_MCMODE1_DISABLE_SPEC_SOURCE_SCOPE_LEN               , 9   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_SPEC_SOURCE_SCOPE_LEN );
+REG64_FLD( MCS_MCMODE1_DISABLE_CENTAUR_CMD_PREFETCH                , 28  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH );
+REG64_FLD( MCS_MCMODE1_DISABLE_CENTAUR_CMD_PREFETCH_LEN            , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH_LEN );
+REG64_FLD( MCS_MCMODE1_DISABLE_ALL_SPEC_OPS                        , 32  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_ALL_SPEC_OPS );
+REG64_FLD( MCS_MCMODE1_DISABLE_SPEC_OP                             , 33  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_SPEC_OP );
+REG64_FLD( MCS_MCMODE1_DISABLE_SPEC_OP_LEN                         , 19  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_SPEC_OP_LEN );
+REG64_FLD( MCS_MCMODE1_DISABLE_CI                                  , 52  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_CI );
+REG64_FLD( MCS_MCMODE1_DISABLE_CI_LEN                              , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_CI_LEN );
+REG64_FLD( MCS_MCMODE1_DISABLE_COMMAND_BYPASS                      , 54  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_COMMAND_BYPASS );
+REG64_FLD( MCS_MCMODE1_DISABLE_COMMAND_BYPASS_LEN                  , 7   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_COMMAND_BYPASS_LEN );
+REG64_FLD( MCS_MCMODE1_DISABLE_FP_COMMAND_BYPASS                   , 61  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_FP_COMMAND_BYPASS );
+REG64_FLD( MCS_MCMODE1_DISABLE_BYPASS_IN_READ_DATAFLOW             , 62  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_BYPASS_IN_READ_DATAFLOW );
+REG64_FLD( MCS_MCMODE1_RESERVED63                                  , 63  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED63 );
+
+REG64_FLD( MCS_MCMODE2_FORCE_SFSTAT_ACTIVE                         , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_SFSTAT_ACTIVE );
+REG64_FLD( MCS_MCMODE2_DISABLE_MDI0                                , 1   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_MDI0 );
+REG64_FLD( MCS_MCMODE2_DISABLE_MDI0_LEN                            , 13  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_MDI0_LEN );
+REG64_FLD( MCS_MCMODE2_RESERVED14                                  , 14  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED14 );
+REG64_FLD( MCS_MCMODE2_RESERVED15                                  , 15  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED15 );
+REG64_FLD( MCS_MCMODE2_DISABLE_SHARD_PRESP_ABORT                   , 16  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_SHARD_PRESP_ABORT );
+REG64_FLD( MCS_MCMODE2_DISABLE_RETRY_LOST_CLAIM                    , 17  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_RETRY_LOST_CLAIM );
+REG64_FLD( MCS_MCMODE2_DOUBLE_EPSILON_LENGTH                       , 18  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DOUBLE_EPSILON_LENGTH );
+REG64_FLD( MCS_MCMODE2_RESERVED19_22                               , 19  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED19_22 );
+REG64_FLD( MCS_MCMODE2_RESERVED19_22_LEN                           , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED19_22_LEN );
+REG64_FLD( MCS_MCMODE2_ENABLE_OP_HIT_ERROR                         , 23  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_OP_HIT_ERROR );
+REG64_FLD( MCS_MCMODE2_COLLISION_MODES                             , 24  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_COLLISION_MODES );
+REG64_FLD( MCS_MCMODE2_COLLISION_MODES_LEN                         , 16  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_COLLISION_MODES_LEN );
+REG64_FLD( MCS_MCMODE2_ENABLE_FIR_SPEC_ATTN                        , 40  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_FIR_SPEC_ATTN );
+REG64_FLD( MCS_MCMODE2_ENABLE_FIR_HOST_ATTN                        , 41  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_FIR_HOST_ATTN );
+
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_VALID                         , 0   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_D_VALUE                       , 1   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_D_VALUE );
+REG64_FLD( MCS_PORT02_MCP0XLT0_12GB_ENABLE                         , 2   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_12GB_ENABLE );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_M0_VALID                      , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_M0_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_M1_VALID                      , 6   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_M1_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_S0_VALID                      , 9   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_S0_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_S1_VALID                      , 10  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_S1_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_S2_VALID                      , 11  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_S2_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_B2_VALID                      , 12  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_B2_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID                   , 13  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_ROW15_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID                   , 14  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_ROW16_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID                   , 15  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_ROW17_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_VALID                         , 16  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_D_VALUE                       , 17  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_D_VALUE );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_M0_VALID                      , 21  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_M0_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_M1_VALID                      , 22  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_M1_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_S0_VALID                      , 25  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_S0_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_S1_VALID                      , 26  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_S1_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_S2_VALID                      , 27  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_S2_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_B2_VALID                      , 28  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_B2_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_ROW15_VALID                   , 29  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_ROW15_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_ROW16_VALID                   , 30  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_ROW16_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_SLOT1_ROW17_VALID                   , 31  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_ROW17_VALID );
+REG64_FLD( MCS_PORT02_MCP0XLT0_D_BIT_MAP                           , 35  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_D_BIT_MAP  );
+REG64_FLD( MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN                       , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_D_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT0_M0_BIT_MAP                          , 41  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_M0_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT0_M0_BIT_MAP_LEN                      , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_M0_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT0_M1_BIT_MAP                          , 47  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_M1_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT0_M1_BIT_MAP_LEN                      , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_M1_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT0_R17_BIT_MAP                         , 53  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_R17_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT0_R17_BIT_MAP_LEN                     , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_R17_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT0_R16_BIT_MAP                         , 57  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_R16_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT0_R16_BIT_MAP_LEN                     , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_R16_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT0_R15_BIT_MAP                         , 61  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_R15_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT0_R15_BIT_MAP_LEN                     , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3    ,
+           SH_FLD_R15_BIT_MAP_LEN );
+
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_VALID                         , 0   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_D_VALUE                       , 1   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_D_VALUE );
+REG64_FLD( MCS_PORT13_MCP0XLT0_12GB_ENABLE                         , 2   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_12GB_ENABLE );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_M0_VALID                      , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_M0_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_M1_VALID                      , 6   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_M1_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_S0_VALID                      , 9   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_S0_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_S1_VALID                      , 10  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_S1_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_S2_VALID                      , 11  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_S2_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_B2_VALID                      , 12  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_B2_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_ROW15_VALID                   , 13  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_ROW15_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_ROW16_VALID                   , 14  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_ROW16_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT0_ROW17_VALID                   , 15  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT0_ROW17_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_VALID                         , 16  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_D_VALUE                       , 17  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_D_VALUE );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_M0_VALID                      , 21  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_M0_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_M1_VALID                      , 22  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_M1_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_S0_VALID                      , 25  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_S0_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_S1_VALID                      , 26  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_S1_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_S2_VALID                      , 27  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_S2_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_B2_VALID                      , 28  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_B2_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_ROW15_VALID                   , 29  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_ROW15_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_ROW16_VALID                   , 30  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_ROW16_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_SLOT1_ROW17_VALID                   , 31  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_SLOT1_ROW17_VALID );
+REG64_FLD( MCS_PORT13_MCP0XLT0_D_BIT_MAP                           , 35  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_D_BIT_MAP  );
+REG64_FLD( MCS_PORT13_MCP0XLT0_D_BIT_MAP_LEN                       , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_D_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT0_M0_BIT_MAP                          , 41  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_M0_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT0_M0_BIT_MAP_LEN                      , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_M0_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT0_M1_BIT_MAP                          , 47  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_M1_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT0_M1_BIT_MAP_LEN                      , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_M1_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT0_R17_BIT_MAP                         , 53  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_R17_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT0_R17_BIT_MAP_LEN                     , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_R17_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT0_R16_BIT_MAP                         , 57  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_R16_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT0_R16_BIT_MAP_LEN                     , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_R16_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT0_R15_BIT_MAP                         , 61  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_R15_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT0_R15_BIT_MAP_LEN                     , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3    ,
+           SH_FLD_R15_BIT_MAP_LEN );
+
+REG64_FLD( MCS_PORT02_MCP0XLT1_S0_BIT_MAP                          , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_S0_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT1_S0_BIT_MAP_LEN                      , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_S0_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT1_S1_BIT_MAP                          , 11  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_S1_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT1_S1_BIT_MAP_LEN                      , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_S1_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT1_S2_BIT_MAP                          , 19  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_S2_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT1_S2_BIT_MAP_LEN                      , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_S2_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT1_COL4_BIT_MAP                        , 35  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL4_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT1_COL4_BIT_MAP_LEN                    , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL4_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT1_COL5_BIT_MAP                        , 43  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL5_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT1_COL5_BIT_MAP_LEN                    , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL5_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT1_COL6_BIT_MAP                        , 51  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL6_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT1_COL6_BIT_MAP_LEN                    , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL6_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT1_COL7_BIT_MAP                        , 59  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL7_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT1_COL7_BIT_MAP_LEN                    , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL7_BIT_MAP_LEN );
+
+REG64_FLD( MCS_PORT13_MCP0XLT1_S0_BIT_MAP                          , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_S0_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT1_S0_BIT_MAP_LEN                      , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_S0_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT1_S1_BIT_MAP                          , 11  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_S1_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT1_S1_BIT_MAP_LEN                      , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_S1_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT1_S2_BIT_MAP                          , 19  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_S2_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT1_S2_BIT_MAP_LEN                      , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_S2_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT1_COL4_BIT_MAP                        , 35  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL4_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT1_COL4_BIT_MAP_LEN                    , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL4_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT1_COL5_BIT_MAP                        , 43  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL5_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT1_COL5_BIT_MAP_LEN                    , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL5_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT1_COL6_BIT_MAP                        , 51  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL6_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT1_COL6_BIT_MAP_LEN                    , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL6_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT1_COL7_BIT_MAP                        , 59  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL7_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT1_COL7_BIT_MAP_LEN                    , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL7_BIT_MAP_LEN );
+
+REG64_FLD( MCS_PORT02_MCP0XLT2_COL8_BIT_MAP                        , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL8_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT2_COL8_BIT_MAP_LEN                    , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL8_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT2_COL9_BIT_MAP                        , 11  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL9_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT2_COL9_BIT_MAP_LEN                    , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL9_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT2_BANK0_BIT_MAP                       , 19  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK0_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT2_BANK0_BIT_MAP_LEN                   , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK0_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT2_BANK1_BIT_MAP                       , 27  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK1_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT2_BANK1_BIT_MAP_LEN                   , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK1_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT2_BANK2_BIT_MAP                       , 35  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK2_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT2_BANK2_BIT_MAP_LEN                   , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK2_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT2_BANK_GROUP0_BIT_MAP                 , 43  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK_GROUP0_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT2_BANK_GROUP0_BIT_MAP_LEN             , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK_GROUP0_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT02_MCP0XLT2_BANK_GROUP1_BIT_MAP                 , 51  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK_GROUP1_BIT_MAP );
+REG64_FLD( MCS_PORT02_MCP0XLT2_BANK_GROUP1_BIT_MAP_LEN             , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK_GROUP1_BIT_MAP_LEN );
+
+REG64_FLD( MCS_PORT13_MCP0XLT2_COL8_BIT_MAP                        , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL8_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT2_COL8_BIT_MAP_LEN                    , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL8_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT2_COL9_BIT_MAP                        , 11  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL9_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT2_COL9_BIT_MAP_LEN                    , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_COL9_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT2_BANK0_BIT_MAP                       , 19  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK0_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT2_BANK0_BIT_MAP_LEN                   , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK0_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT2_BANK1_BIT_MAP                       , 27  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK1_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT2_BANK1_BIT_MAP_LEN                   , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK1_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT2_BANK2_BIT_MAP                       , 35  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK2_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT2_BANK2_BIT_MAP_LEN                   , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK2_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT2_BANK_GROUP0_BIT_MAP                 , 43  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK_GROUP0_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT2_BANK_GROUP0_BIT_MAP_LEN             , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK_GROUP0_BIT_MAP_LEN );
+REG64_FLD( MCS_PORT13_MCP0XLT2_BANK_GROUP1_BIT_MAP                 , 51  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK_GROUP1_BIT_MAP );
+REG64_FLD( MCS_PORT13_MCP0XLT2_BANK_GROUP1_BIT_MAP_LEN             , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_BANK_GROUP1_BIT_MAP_LEN );
+
+REG64_FLD( MCS_PORT02_MCPERF0_ENABLE_DYNAMIC_WR_USAGE              , 0   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_DYNAMIC_WR_USAGE );
+REG64_FLD( MCS_PORT02_MCPERF0_ENABLE_DYNAMIC_PF_USAGE              , 1   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_DYNAMIC_PF_USAGE );
+REG64_FLD( MCS_PORT02_MCPERF0_DYNAMIC_WINDOW_SELECT                , 2   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_DYNAMIC_WINDOW_SELECT );
+REG64_FLD( MCS_PORT02_MCPERF0_DYNAMIC_WINDOW_SELECT_LEN            , 2   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_DYNAMIC_WINDOW_SELECT_LEN );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD                  , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_SEC_MIRROR_RSVD );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD_LEN              , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_SEC_MIRROR_RSVD_LEN );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_HPC_RD_RSVD                      , 8   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HPC_RD_RSVD );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_HPC_RD_RSVD_LEN                  , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HPC_RD_RSVD_LEN );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_HA_RSVD                          , 12  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HA_RSVD );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_HA_RSVD_LEN                      , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HA_RSVD_LEN );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_HTM_RSVD                         , 16  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HTM_RSVD );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_HTM_RSVD_LEN                     , 6   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HTM_RSVD_LEN );
+REG64_FLD( MCS_PORT02_MCPERF0_AMO_LIMIT                            , 22  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_AMO_LIMIT  );
+REG64_FLD( MCS_PORT02_MCPERF0_AMO_LIMIT_LEN                        , 6   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_AMO_LIMIT_LEN );
+REG64_FLD( MCS_PORT02_MCPERF0_PREFETCH_LIMIT                       , 28  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PREFETCH_LIMIT );
+REG64_FLD( MCS_PORT02_MCPERF0_PREFETCH_LIMIT_LEN                   , 6   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PREFETCH_LIMIT_LEN );
+REG64_FLD( MCS_PORT02_MCPERF0_FASTPATH_LIMIT                       , 34  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_FASTPATH_LIMIT );
+REG64_FLD( MCS_PORT02_MCPERF0_FASTPATH_LIMIT_LEN                   , 6   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_FASTPATH_LIMIT_LEN );
+REG64_FLD( MCS_PORT02_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT        , 40  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT );
+REG64_FLD( MCS_PORT02_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN    , 6   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN );
+REG64_FLD( MCS_PORT02_MCPERF0_WR_RSVD_UPPER_LIMIT                  , 46  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_WR_RSVD_UPPER_LIMIT );
+REG64_FLD( MCS_PORT02_MCPERF0_WR_RSVD_UPPER_LIMIT_LEN              , 6   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_WR_RSVD_UPPER_LIMIT_LEN );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_CL_ACTIVE                        , 52  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_CL_ACTIVE );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_CL_ACTIVE_LEN                    , 6   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_CL_ACTIVE_LEN );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_HA_RSVD_SEL                      , 58  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HA_RSVD_SEL );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_HA_RSVD_SEL_LEN                  , 2   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HA_RSVD_SEL_LEN );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_HTM_RSVD_SEL                     , 60  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HTM_RSVD_SEL );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_HTM_RSVD_SEL_LEN                 , 2   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HTM_RSVD_SEL_LEN );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL              , 62  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_SEC_MIRROR_RSVD_SEL );
+REG64_FLD( MCS_PORT02_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL_LEN          , 2   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_SEC_MIRROR_RSVD_SEL_LEN );
+
+REG64_FLD( MCS_PORT13_MCPERF0_ENABLE_DYNAMIC_WR_USAGE              , 0   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_DYNAMIC_WR_USAGE );
+REG64_FLD( MCS_PORT13_MCPERF0_ENABLE_DYNAMIC_PF_USAGE              , 1   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_DYNAMIC_PF_USAGE );
+REG64_FLD( MCS_PORT13_MCPERF0_DYNAMIC_WINDOW_SELECT                , 2   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_DYNAMIC_WINDOW_SELECT );
+REG64_FLD( MCS_PORT13_MCPERF0_DYNAMIC_WINDOW_SELECT_LEN            , 2   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_DYNAMIC_WINDOW_SELECT_LEN );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD                  , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_SEC_MIRROR_RSVD );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD_LEN              , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_SEC_MIRROR_RSVD_LEN );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_HPC_RD_RSVD                      , 8   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HPC_RD_RSVD );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_HPC_RD_RSVD_LEN                  , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HPC_RD_RSVD_LEN );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_HA_RSVD                          , 12  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HA_RSVD );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_HA_RSVD_LEN                      , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HA_RSVD_LEN );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_HTM_RSVD                         , 16  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HTM_RSVD );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_HTM_RSVD_LEN                     , 6   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HTM_RSVD_LEN );
+REG64_FLD( MCS_PORT13_MCPERF0_AMO_LIMIT                            , 22  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_AMO_LIMIT  );
+REG64_FLD( MCS_PORT13_MCPERF0_AMO_LIMIT_LEN                        , 6   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_AMO_LIMIT_LEN );
+REG64_FLD( MCS_PORT13_MCPERF0_PREFETCH_LIMIT                       , 28  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PREFETCH_LIMIT );
+REG64_FLD( MCS_PORT13_MCPERF0_PREFETCH_LIMIT_LEN                   , 6   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PREFETCH_LIMIT_LEN );
+REG64_FLD( MCS_PORT13_MCPERF0_FASTPATH_LIMIT                       , 34  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_FASTPATH_LIMIT );
+REG64_FLD( MCS_PORT13_MCPERF0_FASTPATH_LIMIT_LEN                   , 6   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_FASTPATH_LIMIT_LEN );
+REG64_FLD( MCS_PORT13_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT        , 40  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT );
+REG64_FLD( MCS_PORT13_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN    , 6   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN );
+REG64_FLD( MCS_PORT13_MCPERF0_WR_RSVD_UPPER_LIMIT                  , 46  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_WR_RSVD_UPPER_LIMIT );
+REG64_FLD( MCS_PORT13_MCPERF0_WR_RSVD_UPPER_LIMIT_LEN              , 6   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_WR_RSVD_UPPER_LIMIT_LEN );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_CL_ACTIVE                        , 52  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_CL_ACTIVE );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_CL_ACTIVE_LEN                    , 6   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_CL_ACTIVE_LEN );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_HA_RSVD_SEL                      , 58  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HA_RSVD_SEL );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_HA_RSVD_SEL_LEN                  , 2   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HA_RSVD_SEL_LEN );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_HTM_RSVD_SEL                     , 60  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HTM_RSVD_SEL );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_HTM_RSVD_SEL_LEN                 , 2   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_HTM_RSVD_SEL_LEN );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL              , 62  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_SEC_MIRROR_RSVD_SEL );
+REG64_FLD( MCS_PORT13_MCPERF0_NUM_SEC_MIRROR_RSVD_SEL_LEN          , 2   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_SEC_MIRROR_RSVD_SEL_LEN );
+
+REG64_FLD( MCS_MCPERF1_DISABLE_FASTPATH                            , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_FASTPATH );
+REG64_FLD( MCS_MCPERF1_RESERVED1_2                                 , 1   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED1_2 );
+REG64_FLD( MCS_MCPERF1_RESERVED1_2_LEN                             , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED1_2_LEN );
+REG64_FLD( MCS_MCPERF1_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ , 3   , SH_UNT_MCS      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ );
+REG64_FLD( MCS_MCPERF1_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ , 4   , SH_UNT_MCS      ,
+           SH_ACS_SCOM_RW  , SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ );
+REG64_FLD( MCS_MCPERF1_MCPERF1_DISABLE_FASTPATH_QOS                , 5   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCPERF1_DISABLE_FASTPATH_QOS );
+REG64_FLD( MCS_MCPERF1_DISABLE_CHARB_BYPASS                        , 6   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_CHARB_BYPASS );
+REG64_FLD( MCS_MCPERF1_DISABLE_SPEC_DISABLE_HINT_BIT               , 7   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_SPEC_DISABLE_HINT_BIT );
+REG64_FLD( MCS_MCPERF1_DISABLE_2K_SPEC_FILTER                      , 8   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_2K_SPEC_FILTER );
+REG64_FLD( MCS_MCPERF1_DISABLE_RESET_2K_COUNT_IF_HINT_BIT_SET      , 9   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_RESET_2K_COUNT_IF_HINT_BIT_SET );
+REG64_FLD( MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT     , 10  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT );
+REG64_FLD( MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT_LEN , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT_LEN );
+REG64_FLD( MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT     , 14  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT );
+REG64_FLD( MCS_MCPERF1_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT_LEN , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT_LEN );
+REG64_FLD( MCS_MCPERF1_SPEC_READ_FILTER_NO_HASH_MODE               , 18  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPEC_READ_FILTER_NO_HASH_MODE );
+REG64_FLD( MCS_MCPERF1_RESERVED19_31                               , 19  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED19_31 );
+REG64_FLD( MCS_MCPERF1_RESERVED19_31_LEN                           , 13  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED19_31_LEN );
+REG64_FLD( MCS_MCPERF1_PF_DROP_CNT_THRESH                          , 32  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PF_DROP_CNT_THRESH );
+REG64_FLD( MCS_MCPERF1_PF_DROP_CNT_THRESH_LEN                      , 7   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PF_DROP_CNT_THRESH_LEN );
+REG64_FLD( MCS_MCPERF1_CP_RETRY_THRESH                             , 39  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CP_RETRY_THRESH );
+REG64_FLD( MCS_MCPERF1_CP_RETRY_THRESH_LEN                         , 7   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CP_RETRY_THRESH_LEN );
+REG64_FLD( MCS_MCPERF1_MERGE_CAPACITY_LIMIT                        , 46  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MERGE_CAPACITY_LIMIT );
+REG64_FLD( MCS_MCPERF1_MERGE_CAPACITY_LIMIT_LEN                    , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MERGE_CAPACITY_LIMIT_LEN );
+REG64_FLD( MCS_MCPERF1_RRQ_CAPACITY_LIMIT                          , 50  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RRQ_CAPACITY_LIMIT );
+REG64_FLD( MCS_MCPERF1_RRQ_CAPACITY_LIMIT_LEN                      , 5   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RRQ_CAPACITY_LIMIT_LEN );
+REG64_FLD( MCS_MCPERF1_WRQ_CAPACITY_LIMIT                          , 55  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRQ_CAPACITY_LIMIT );
+REG64_FLD( MCS_MCPERF1_WRQ_CAPACITY_LIMIT_LEN                      , 6   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRQ_CAPACITY_LIMIT_LEN );
+REG64_FLD( MCS_MCPERF1_ENABLE_PF_DROP_CMDLIST                      , 61  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_PF_DROP_CMDLIST );
+REG64_FLD( MCS_MCPERF1_ENABLE_PF_DROP_SRQ                          , 62  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_PF_DROP_SRQ );
+REG64_FLD( MCS_MCPERF1_ENABLE_PREFETCH_PROMOTE                     , 63  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_PREFETCH_PROMOTE );
+
+REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE0                       , 0   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE0 );
+REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE0_LEN                   , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE0_LEN );
+REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE1                       , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE1 );
+REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE1_LEN                   , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE1_LEN );
+REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE2                       , 6   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE2 );
+REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE2_LEN                   , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE2_LEN );
+REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE3                       , 9   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE3 );
+REG64_FLD( MCS_PORT02_MCPERF2_PF_DROP_VALUE3_LEN                   , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE3_LEN );
+REG64_FLD( MCS_PORT02_MCPERF2_DISABLE_DROPABLE                     , 12  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_DISABLE_DROPABLE );
+REG64_FLD( MCS_PORT02_MCPERF2_REFRESH_BLOCK_CONFIG                 , 13  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_REFRESH_BLOCK_CONFIG );
+REG64_FLD( MCS_PORT02_MCPERF2_REFRESH_BLOCK_CONFIG_LEN             , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_REFRESH_BLOCK_CONFIG_LEN );
+REG64_FLD( MCS_PORT02_MCPERF2_ENABLE_REFRESH_BLOCK_SQ              , 16  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_REFRESH_BLOCK_SQ );
+REG64_FLD( MCS_PORT02_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ             , 17  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_REFRESH_BLOCK_NSQ );
+REG64_FLD( MCS_PORT02_MCPERF2_ENABLE_REFRESH_BLOCK_DISP            , 18  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_REFRESH_BLOCK_DISP );
+REG64_FLD( MCS_PORT02_MCPERF2_PERF_THRESH                          , 19  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PERF_THRESH );
+REG64_FLD( MCS_PORT02_MCPERF2_PERF_THRESH_LEN                      , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PERF_THRESH_LEN );
+REG64_FLD( MCS_PORT02_MCPERF2_NSQ_LFSR_CNTL                        , 24  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NSQ_LFSR_CNTL );
+REG64_FLD( MCS_PORT02_MCPERF2_NSQ_LFSR_CNTL_LEN                    , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NSQ_LFSR_CNTL_LEN );
+REG64_FLD( MCS_PORT02_MCPERF2_SQ_LFSR_CNTL                         , 28  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_SQ_LFSR_CNTL );
+REG64_FLD( MCS_PORT02_MCPERF2_SQ_LFSR_CNTL_LEN                     , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_SQ_LFSR_CNTL_LEN );
+REG64_FLD( MCS_PORT02_MCPERF2_EN_CHARB_CMD_STALL                   , 32  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_CHARB_CMD_STALL );
+REG64_FLD( MCS_PORT02_MCPERF2_EN_CHARB_RRQ_STALL                   , 33  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_CHARB_RRQ_STALL );
+REG64_FLD( MCS_PORT02_MCPERF2_EN_CHARB_WRQ_STALL                   , 34  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_CHARB_WRQ_STALL );
+REG64_FLD( MCS_PORT02_MCPERF2_EN_CHARB_MERGE_STALL                 , 35  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_CHARB_MERGE_STALL );
+REG64_FLD( MCS_PORT02_MCPERF2_EN_64_128_PB_READ                    , 36  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_64_128_PB_READ );
+REG64_FLD( MCS_PORT02_MCPERF2_RCTRL_CONFIG                         , 37  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RCTRL_CONFIG );
+REG64_FLD( MCS_PORT02_MCPERF2_RCTRL_CONFIG_LEN                     , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RCTRL_CONFIG_LEN );
+REG64_FLD( MCS_PORT02_MCPERF2_ALT_M                                , 40  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_ALT_M      );
+REG64_FLD( MCS_PORT02_MCPERF2_ALT_M_LEN                            , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_ALT_M_LEN  );
+REG64_FLD( MCS_PORT02_MCPERF2_NUM_CLEAN                            , 44  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_CLEAN  );
+REG64_FLD( MCS_PORT02_MCPERF2_NUM_CLEAN_LEN                        , 6   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_CLEAN_LEN );
+REG64_FLD( MCS_PORT02_MCPERF2_NUM_RMW_BUF                          , 50  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_RMW_BUF );
+REG64_FLD( MCS_PORT02_MCPERF2_NUM_RMW_BUF_LEN                      , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_RMW_BUF_LEN );
+REG64_FLD( MCS_PORT02_MCPERF2_RMW_BUF_THRESH                       , 55  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RMW_BUF_THRESH );
+REG64_FLD( MCS_PORT02_MCPERF2_RMW_BUF_THRESH_LEN                   , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RMW_BUF_THRESH_LEN );
+REG64_FLD( MCS_PORT02_MCPERF2_EN_ALT_ECR_NO_ERR                    , 60  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_ALT_ECR_NO_ERR );
+REG64_FLD( MCS_PORT02_MCPERF2_EN_ALT_ECR_ERR                       , 61  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_ALT_ECR_ERR );
+REG64_FLD( MCS_PORT02_MCPERF2_EN_ALT_CR                            , 62  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_ALT_CR  );
+REG64_FLD( MCS_PORT02_MCPERF2_LOAD_RSVD_VALUES                     , 63  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_LOAD_RSVD_VALUES );
+
+REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE0                       , 0   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE0 );
+REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE0_LEN                   , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE0_LEN );
+REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE1                       , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE1 );
+REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE1_LEN                   , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE1_LEN );
+REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE2                       , 6   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE2 );
+REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE2_LEN                   , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE2_LEN );
+REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE3                       , 9   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE3 );
+REG64_FLD( MCS_PORT13_MCPERF2_PF_DROP_VALUE3_LEN                   , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_DROP_VALUE3_LEN );
+REG64_FLD( MCS_PORT13_MCPERF2_DISABLE_DROPABLE                     , 12  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_DISABLE_DROPABLE );
+REG64_FLD( MCS_PORT13_MCPERF2_REFRESH_BLOCK_CONFIG                 , 13  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_REFRESH_BLOCK_CONFIG );
+REG64_FLD( MCS_PORT13_MCPERF2_REFRESH_BLOCK_CONFIG_LEN             , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_REFRESH_BLOCK_CONFIG_LEN );
+REG64_FLD( MCS_PORT13_MCPERF2_ENABLE_REFRESH_BLOCK_SQ              , 16  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_REFRESH_BLOCK_SQ );
+REG64_FLD( MCS_PORT13_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ             , 17  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_REFRESH_BLOCK_NSQ );
+REG64_FLD( MCS_PORT13_MCPERF2_ENABLE_REFRESH_BLOCK_DISP            , 18  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_ENABLE_REFRESH_BLOCK_DISP );
+REG64_FLD( MCS_PORT13_MCPERF2_PERF_THRESH                          , 19  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PERF_THRESH );
+REG64_FLD( MCS_PORT13_MCPERF2_PERF_THRESH_LEN                      , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PERF_THRESH_LEN );
+REG64_FLD( MCS_PORT13_MCPERF2_NSQ_LFSR_CNTL                        , 24  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NSQ_LFSR_CNTL );
+REG64_FLD( MCS_PORT13_MCPERF2_NSQ_LFSR_CNTL_LEN                    , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NSQ_LFSR_CNTL_LEN );
+REG64_FLD( MCS_PORT13_MCPERF2_SQ_LFSR_CNTL                         , 28  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_SQ_LFSR_CNTL );
+REG64_FLD( MCS_PORT13_MCPERF2_SQ_LFSR_CNTL_LEN                     , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_SQ_LFSR_CNTL_LEN );
+REG64_FLD( MCS_PORT13_MCPERF2_EN_CHARB_CMD_STALL                   , 32  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_CHARB_CMD_STALL );
+REG64_FLD( MCS_PORT13_MCPERF2_EN_CHARB_RRQ_STALL                   , 33  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_CHARB_RRQ_STALL );
+REG64_FLD( MCS_PORT13_MCPERF2_EN_CHARB_WRQ_STALL                   , 34  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_CHARB_WRQ_STALL );
+REG64_FLD( MCS_PORT13_MCPERF2_EN_CHARB_MERGE_STALL                 , 35  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_CHARB_MERGE_STALL );
+REG64_FLD( MCS_PORT13_MCPERF2_EN_64_128_PB_READ                    , 36  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_64_128_PB_READ );
+REG64_FLD( MCS_PORT13_MCPERF2_RCTRL_CONFIG                         , 37  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RCTRL_CONFIG );
+REG64_FLD( MCS_PORT13_MCPERF2_RCTRL_CONFIG_LEN                     , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RCTRL_CONFIG_LEN );
+REG64_FLD( MCS_PORT13_MCPERF2_ALT_M                                , 40  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_ALT_M      );
+REG64_FLD( MCS_PORT13_MCPERF2_ALT_M_LEN                            , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_ALT_M_LEN  );
+REG64_FLD( MCS_PORT13_MCPERF2_NUM_CLEAN                            , 44  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_CLEAN  );
+REG64_FLD( MCS_PORT13_MCPERF2_NUM_CLEAN_LEN                        , 6   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_CLEAN_LEN );
+REG64_FLD( MCS_PORT13_MCPERF2_NUM_RMW_BUF                          , 50  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_RMW_BUF );
+REG64_FLD( MCS_PORT13_MCPERF2_NUM_RMW_BUF_LEN                      , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_NUM_RMW_BUF_LEN );
+REG64_FLD( MCS_PORT13_MCPERF2_RMW_BUF_THRESH                       , 55  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RMW_BUF_THRESH );
+REG64_FLD( MCS_PORT13_MCPERF2_RMW_BUF_THRESH_LEN                   , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RMW_BUF_THRESH_LEN );
+REG64_FLD( MCS_PORT13_MCPERF2_EN_ALT_ECR_NO_ERR                    , 60  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_ALT_ECR_NO_ERR );
+REG64_FLD( MCS_PORT13_MCPERF2_EN_ALT_ECR_ERR                       , 61  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_ALT_ECR_ERR );
+REG64_FLD( MCS_PORT13_MCPERF2_EN_ALT_CR                            , 62  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_ALT_CR  );
+REG64_FLD( MCS_PORT13_MCPERF2_LOAD_RSVD_VALUES                     , 63  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_LOAD_RSVD_VALUES );
+
+REG64_FLD( MCS_PORT02_MCPERF3_EN_DROP_PLS_F_FULL                   , 0   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_DROP_PLS_F_FULL );
+REG64_FLD( MCS_PORT02_MCPERF3_DIS_DROPABLE_HP                      , 1   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_DIS_DROPABLE_HP );
+REG64_FLD( MCS_PORT02_MCPERF3_EN_PF_CONF_RETRY                     , 2   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_PF_CONF_RETRY );
+REG64_FLD( MCS_PORT02_MCPERF3_DROP_PLS_DIV00                       , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV00 );
+REG64_FLD( MCS_PORT02_MCPERF3_DROP_PLS_DIV00_LEN                   , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV00_LEN );
+REG64_FLD( MCS_PORT02_MCPERF3_DROP_PLS_DIV01                       , 6   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV01 );
+REG64_FLD( MCS_PORT02_MCPERF3_DROP_PLS_DIV01_LEN                   , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV01_LEN );
+REG64_FLD( MCS_PORT02_MCPERF3_DROP_PLS_DIV10                       , 9   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV10 );
+REG64_FLD( MCS_PORT02_MCPERF3_DROP_PLS_DIV10_LEN                   , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV10_LEN );
+REG64_FLD( MCS_PORT02_MCPERF3_DROP_PLS_DIV11                       , 12  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV11 );
+REG64_FLD( MCS_PORT02_MCPERF3_DROP_PLS_DIV11_LEN                   , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV11_LEN );
+REG64_FLD( MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH0                , 15  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH0 );
+REG64_FLD( MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH0_LEN            , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH0_LEN );
+REG64_FLD( MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH1                , 19  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH1 );
+REG64_FLD( MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH1_LEN            , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH1_LEN );
+REG64_FLD( MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH2                , 23  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH2 );
+REG64_FLD( MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH2_LEN            , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH2_LEN );
+REG64_FLD( MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH3                , 27  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH3 );
+REG64_FLD( MCS_PORT02_MCPERF3_PF_CONF_RETRY_THRESH3_LEN            , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH3_LEN );
+REG64_FLD( MCS_PORT02_MCPERF3_RESERVED31                           , 31  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED31 );
+
+REG64_FLD( MCS_PORT13_MCPERF3_EN_DROP_PLS_F_FULL                   , 0   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_DROP_PLS_F_FULL );
+REG64_FLD( MCS_PORT13_MCPERF3_DIS_DROPABLE_HP                      , 1   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_DIS_DROPABLE_HP );
+REG64_FLD( MCS_PORT13_MCPERF3_EN_PF_CONF_RETRY                     , 2   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_EN_PF_CONF_RETRY );
+REG64_FLD( MCS_PORT13_MCPERF3_DROP_PLS_DIV00                       , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV00 );
+REG64_FLD( MCS_PORT13_MCPERF3_DROP_PLS_DIV00_LEN                   , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV00_LEN );
+REG64_FLD( MCS_PORT13_MCPERF3_DROP_PLS_DIV01                       , 6   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV01 );
+REG64_FLD( MCS_PORT13_MCPERF3_DROP_PLS_DIV01_LEN                   , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV01_LEN );
+REG64_FLD( MCS_PORT13_MCPERF3_DROP_PLS_DIV10                       , 9   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV10 );
+REG64_FLD( MCS_PORT13_MCPERF3_DROP_PLS_DIV10_LEN                   , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV10_LEN );
+REG64_FLD( MCS_PORT13_MCPERF3_DROP_PLS_DIV11                       , 12  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV11 );
+REG64_FLD( MCS_PORT13_MCPERF3_DROP_PLS_DIV11_LEN                   , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_DROP_PLS_DIV11_LEN );
+REG64_FLD( MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH0                , 15  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH0 );
+REG64_FLD( MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH0_LEN            , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH0_LEN );
+REG64_FLD( MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH1                , 19  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH1 );
+REG64_FLD( MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH1_LEN            , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH1_LEN );
+REG64_FLD( MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH2                , 23  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH2 );
+REG64_FLD( MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH2_LEN            , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH2_LEN );
+REG64_FLD( MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH3                , 27  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH3 );
+REG64_FLD( MCS_PORT13_MCPERF3_PF_CONF_RETRY_THRESH3_LEN            , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_PF_CONF_RETRY_THRESH3_LEN );
+REG64_FLD( MCS_PORT13_MCPERF3_RESERVED31                           , 31  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED31 );
+
+REG64_FLD( MCS_MCSYNC_CHANNEL_SELECT                               , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHANNEL_SELECT );
+REG64_FLD( MCS_MCSYNC_CHANNEL_SELECT_LEN                           , 8   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHANNEL_SELECT_LEN );
+REG64_FLD( MCS_MCSYNC_SYNC_TYPE                                    , 8   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_TYPE  );
+REG64_FLD( MCS_MCSYNC_SYNC_TYPE_LEN                                , 8   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_TYPE_LEN );
+REG64_FLD( MCS_MCSYNC_SYNC_GO_CH0                                  , 16  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_GO_CH0 );
+REG64_FLD( MCS_MCSYNC_SYNC_GO_CH1                                  , 17  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_GO_CH1 );
+REG64_FLD( MCS_MCSYNC_SYNC_REPLAY_COUNT                            , 18  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_REPLAY_COUNT );
+REG64_FLD( MCS_MCSYNC_SYNC_REPLAY_COUNT_LEN                        , 7   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_REPLAY_COUNT_LEN );
+REG64_FLD( MCS_MCSYNC_SYNC_RESERVED                                , 25  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_RESERVED );
+REG64_FLD( MCS_MCSYNC_SYNC_RESERVED_LEN                            , 3   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_RESERVED_LEN );
+
+REG64_FLD( MCS_MCTEST_RESERVED0_3                                  , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED0_3 );
+REG64_FLD( MCS_MCTEST_RESERVED0_3_LEN                              , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED0_3_LEN );
+REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_ALL_SPEC                      , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_ACTION_DIS_ALL_SPEC );
+REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_ALL_SPEC_LEN                  , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_ACTION_DIS_ALL_SPEC_LEN );
+REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_READ_BYP                      , 8   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_ACTION_DIS_READ_BYP );
+REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_READ_BYP_LEN                  , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_ACTION_DIS_READ_BYP_LEN );
+REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_PREFETCH                      , 12  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_ACTION_DIS_PREFETCH );
+REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_PREFETCH_LEN                  , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_ACTION_DIS_PREFETCH_LEN );
+REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_FASTPATH                      , 16  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_ACTION_DIS_FASTPATH );
+REG64_FLD( MCS_MCTEST_WAT_ACTION_DIS_FASTPATH_LEN                  , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_ACTION_DIS_FASTPATH_LEN );
+REG64_FLD( MCS_MCTEST_WAT_ACTION_FORCE_SFSTAT                      , 20  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_ACTION_FORCE_SFSTAT );
+REG64_FLD( MCS_MCTEST_WAT_ACTION_FORCE_SFSTAT_LEN                  , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_ACTION_FORCE_SFSTAT_LEN );
+REG64_FLD( MCS_MCTEST_WAT_ACTION_FORCE_MDI                         , 24  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_ACTION_FORCE_MDI );
+REG64_FLD( MCS_MCTEST_WAT_ACTION_FORCE_MDI_LEN                     , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_ACTION_FORCE_MDI_LEN );
+REG64_FLD( MCS_MCTEST_RESERVED28_31                                , 28  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED28_31 );
+REG64_FLD( MCS_MCTEST_RESERVED28_31_LEN                            , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED28_31_LEN );
+REG64_FLD( MCS_MCTEST_RCTRL_WAT_ACTION_SEL                         , 32  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RCTRL_WAT_ACTION_SEL );
+REG64_FLD( MCS_MCTEST_RCTRL_WAT_ACTION_SEL_LEN                     , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RCTRL_WAT_ACTION_SEL_LEN );
+REG64_FLD( MCS_MCTEST_RESERVED36_47                                , 36  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED36_47 );
+REG64_FLD( MCS_MCTEST_RESERVED36_47_LEN                            , 12  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED36_47_LEN );
+
+REG64_FLD( MCS_MCTO_SELECT_PB_HANG_PULSE                           , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_PB_HANG_PULSE );
+REG64_FLD( MCS_MCTO_SELECT_LOCAL_HANG_PULSE                        , 1   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_LOCAL_HANG_PULSE );
+REG64_FLD( MCS_MCTO_RPTHANG_SELECT                                 , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RPTHANG_SELECT );
+REG64_FLD( MCS_MCTO_RPTHANG_SELECT_LEN                             , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RPTHANG_SELECT_LEN );
+REG64_FLD( MCS_MCTO_RESERVED4                                      , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED4  );
+REG64_FLD( MCS_MCTO_TIMEOUT_VALUE                                  , 5   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TIMEOUT_VALUE );
+REG64_FLD( MCS_MCTO_TIMEOUT_VALUE_LEN                              , 3   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_TIMEOUT_VALUE_LEN );
+REG64_FLD( MCS_MCTO_LOCAL_HANG_COMP                                , 8   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_HANG_COMP );
+REG64_FLD( MCS_MCTO_LOCAL_HANG_COMP_LEN                            , 16  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_HANG_COMP_LEN );
+REG64_FLD( MCS_MCTO_COMP_MASK                                      , 24  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_COMP_MASK  );
+REG64_FLD( MCS_MCTO_COMP_MASK_LEN                                  , 8   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_COMP_MASK_LEN );
+REG64_FLD( MCS_MCTO_ENABLE_NONMIRROR_HANG                          , 32  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_NONMIRROR_HANG );
+REG64_FLD( MCS_MCTO_ENABLE_MIRROR_HANG                             , 33  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_MIRROR_HANG );
+REG64_FLD( MCS_MCTO_ENABLE_APO_HANG                                , 34  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_APO_HANG );
+REG64_FLD( MCS_MCTO_ENABLE_CLIB_HANG                               , 35  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_CLIB_HANG );
+
+REG64_FLD( MCS_PORT02_MCWAT_WAT_STALL_ACTION                       , 0   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_WAT_STALL_ACTION );
+REG64_FLD( MCS_PORT02_MCWAT_WAT_STALL_ACTION_LEN                   , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_WAT_STALL_ACTION_LEN );
+REG64_FLD( MCS_PORT02_MCWAT_RESERVED4                              , 4   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED4  );
+REG64_FLD( MCS_PORT02_MCWAT_CLSTATE_DEBUG_SEL                      , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_CLSTATE_DEBUG_SEL );
+REG64_FLD( MCS_PORT02_MCWAT_CLSTATE_DEBUG_SEL_LEN                  , 3   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_CLSTATE_DEBUG_SEL_LEN );
+REG64_FLD( MCS_PORT02_MCWAT_RESERVED8_9                            , 8   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED8_9 );
+REG64_FLD( MCS_PORT02_MCWAT_RESERVED8_9_LEN                        , 2   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED8_9_LEN );
+REG64_FLD( MCS_PORT02_MCWAT_DISP_DEBUG_SEL                         , 10  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_DISP_DEBUG_SEL );
+REG64_FLD( MCS_PORT02_MCWAT_DISP_DEBUG_SEL_LEN                     , 2   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_DISP_DEBUG_SEL_LEN );
+REG64_FLD( MCS_PORT02_MCWAT_CL_WRAP_DEBUG_SEL                      , 12  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_CL_WRAP_DEBUG_SEL );
+REG64_FLD( MCS_PORT02_MCWAT_CL_WRAP_DEBUG_SEL_LEN                  , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_CL_WRAP_DEBUG_SEL_LEN );
+REG64_FLD( MCS_PORT02_MCWAT_WAT_ACTION_SEL                         , 17  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_WAT_ACTION_SEL );
+REG64_FLD( MCS_PORT02_MCWAT_WAT_ACTION_SEL_LEN                     , 5   , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_WAT_ACTION_SEL_LEN );
+REG64_FLD( MCS_PORT02_MCWAT_RESERVED22_31                          , 22  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED22_31 );
+REG64_FLD( MCS_PORT02_MCWAT_RESERVED22_31_LEN                      , 10  , SH_UNT_MCS_PORT02, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED22_31_LEN );
+
+REG64_FLD( MCS_PORT13_MCWAT_WAT_STALL_ACTION                       , 0   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_WAT_STALL_ACTION );
+REG64_FLD( MCS_PORT13_MCWAT_WAT_STALL_ACTION_LEN                   , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_WAT_STALL_ACTION_LEN );
+REG64_FLD( MCS_PORT13_MCWAT_RESERVED4                              , 4   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED4  );
+REG64_FLD( MCS_PORT13_MCWAT_CLSTATE_DEBUG_SEL                      , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_CLSTATE_DEBUG_SEL );
+REG64_FLD( MCS_PORT13_MCWAT_CLSTATE_DEBUG_SEL_LEN                  , 3   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_CLSTATE_DEBUG_SEL_LEN );
+REG64_FLD( MCS_PORT13_MCWAT_RESERVED8_9                            , 8   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED8_9 );
+REG64_FLD( MCS_PORT13_MCWAT_RESERVED8_9_LEN                        , 2   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED8_9_LEN );
+REG64_FLD( MCS_PORT13_MCWAT_DISP_DEBUG_SEL                         , 10  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_DISP_DEBUG_SEL );
+REG64_FLD( MCS_PORT13_MCWAT_DISP_DEBUG_SEL_LEN                     , 2   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_DISP_DEBUG_SEL_LEN );
+REG64_FLD( MCS_PORT13_MCWAT_CL_WRAP_DEBUG_SEL                      , 12  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_CL_WRAP_DEBUG_SEL );
+REG64_FLD( MCS_PORT13_MCWAT_CL_WRAP_DEBUG_SEL_LEN                  , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_CL_WRAP_DEBUG_SEL_LEN );
+REG64_FLD( MCS_PORT13_MCWAT_WAT_ACTION_SEL                         , 17  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_WAT_ACTION_SEL );
+REG64_FLD( MCS_PORT13_MCWAT_WAT_ACTION_SEL_LEN                     , 5   , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_WAT_ACTION_SEL_LEN );
+REG64_FLD( MCS_PORT13_MCWAT_RESERVED22_31                          , 22  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED22_31 );
+REG64_FLD( MCS_PORT13_MCWAT_RESERVED22_31_LEN                      , 10  , SH_UNT_MCS_PORT13, SH_ACS_SCOM3_RW ,
+           SH_FLD_RESERVED22_31_LEN );
+
+REG64_FLD( MCS_MCWATCNTL_ENABLE_WAT                                , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_WAT );
+REG64_FLD( MCS_MCWATCNTL_SET_EXT_ARM                               , 1   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_EXT_ARM );
+REG64_FLD( MCS_MCWATCNTL_SET_EXT_RESET                             , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_EXT_RESET );
+REG64_FLD( MCS_MCWATCNTL_SET_EXT_TRIGGER                           , 3   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_EXT_TRIGGER );
+REG64_FLD( MCS_MCWATCNTL_WAT_CNTL_REG_SEL                          , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_CNTL_REG_SEL );
+REG64_FLD( MCS_MCWATCNTL_WAT_CNTL_REG_SEL_LEN                      , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_CNTL_REG_SEL_LEN );
+REG64_FLD( MCS_MCWATCNTL_WAT_EVENT_SEL                             , 8   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_EVENT_SEL );
+REG64_FLD( MCS_MCWATCNTL_WAT_EVENT_SEL_LEN                         , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_EVENT_SEL_LEN );
+REG64_FLD( MCS_MCWATCNTL_WAT_EXT_SEL                               , 10  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_EXT_SEL );
+REG64_FLD( MCS_MCWATCNTL_WAT_EXT_SEL_LEN                           , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_EXT_SEL_LEN );
+REG64_FLD( MCS_MCWATCNTL_WAT_LOCAL_EVENT_SEL                       , 12  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_LOCAL_EVENT_SEL );
+REG64_FLD( MCS_MCWATCNTL_WAT_LOCAL_EVENT_SEL_LEN                   , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_LOCAL_EVENT_SEL_LEN );
+REG64_FLD( MCS_MCWATCNTL_WAT_EXT_EVENT_TO_INT_SEL                  , 14  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_EXT_EVENT_TO_INT_SEL );
+REG64_FLD( MCS_MCWATCNTL_WAT_EXT_EVENT_TO_INT_SEL_LEN              , 2   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_EXT_EVENT_TO_INT_SEL_LEN );
+REG64_FLD( MCS_MCWATCNTL_WAT_GLOB_EVENT0_SEL                       , 16  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_GLOB_EVENT0_SEL );
+REG64_FLD( MCS_MCWATCNTL_WAT_GLOB_EVENT0_SEL_LEN                   , 3   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_GLOB_EVENT0_SEL_LEN );
+REG64_FLD( MCS_MCWATCNTL_WAT_GLOB_EVENT1_SEL                       , 19  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_GLOB_EVENT1_SEL );
+REG64_FLD( MCS_MCWATCNTL_WAT_GLOB_EVENT1_SEL_LEN                   , 3   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_GLOB_EVENT1_SEL_LEN );
+REG64_FLD( MCS_MCWATCNTL_WAT_GLOB_EVENT2_SEL                       , 22  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_GLOB_EVENT2_SEL );
+REG64_FLD( MCS_MCWATCNTL_WAT_GLOB_EVENT2_SEL_LEN                   , 3   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_GLOB_EVENT2_SEL_LEN );
+REG64_FLD( MCS_MCWATCNTL_WAT_GLOB_EVENT3_SEL                       , 25  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_GLOB_EVENT3_SEL );
+REG64_FLD( MCS_MCWATCNTL_WAT_GLOB_EVENT3_SEL_LEN                   , 3   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_GLOB_EVENT3_SEL_LEN );
+REG64_FLD( MCS_MCWATCNTL_RESERVED_28_31                            , 28  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31 );
+REG64_FLD( MCS_MCWATCNTL_RESERVED_28_31_LEN                        , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28_31_LEN );
+REG64_FLD( MCS_MCWATCNTL_PBI_DEBUG_SEL                             , 32  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBI_DEBUG_SEL );
+REG64_FLD( MCS_MCWATCNTL_PBI_DEBUG_SEL_LEN                         , 4   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBI_DEBUG_SEL_LEN );
+REG64_FLD( MCS_MCWATCNTL_RCTRL_DEBUG_SEL                           , 36  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RCTRL_DEBUG_SEL );
+REG64_FLD( MCS_MCWATCNTL_RCTRL_DEBUG_SEL_LEN                       , 3   , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RCTRL_DEBUG_SEL_LEN );
+REG64_FLD( MCS_MCWATCNTL_RESERVED_39_63                            , 39  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_63 );
+REG64_FLD( MCS_MCWATCNTL_RESERVED_39_63_LEN                        , 25  , SH_UNT_MCS      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_39_63_LEN );
+
+REG64_FLD( MCS_MCWATDATA_MCWATDATA0                                , 0   , SH_UNT_MCS      , SH_ACS_SCOM_RO  ,
+           SH_FLD_MCWATDATA0 );
+REG64_FLD( MCS_MCWATDATA_MCWATDATA0_LEN                            , 40  , SH_UNT_MCS      , SH_ACS_SCOM_RO  ,
+           SH_FLD_MCWATDATA0_LEN );
+
+REG64_FLD( MCA_MSR_CHIPMARK                                        , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CHIPMARK   );
+REG64_FLD( MCA_MSR_CHIPMARK_LEN                                    , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_CHIPMARK_LEN );
+REG64_FLD( MCA_MSR_RANK                                            , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RANK       );
+REG64_FLD( MCA_MSR_RANK_LEN                                        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RANK_LEN   );
+
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION0_REG_DDR0                    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR0       );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION0_REG_DDR0_LEN                , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR0_LEN   );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION0_REG_DDR1                    , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR1       );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION0_REG_DDR1_LEN                , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR1_LEN   );
+
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION1_REG_DDR0                    , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR0       );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION1_REG_DDR0_LEN                , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR0_LEN   );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION1_REG_DDR1                    , 56  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR1       );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_ACTION1_REG_DDR1_LEN                , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DDR1_LEN   );
+
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR0_FSM_CKSTP             , 48  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR0_FSM_CKSTP );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR0_PARITY_CKSTP          , 49  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR0_PARITY_CKSTP );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR0_CALIBRATION_ERROR     , 50  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR0_CALIBRATION_ERROR );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR0_FSM_ERR               , 51  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR0_FSM_ERR );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR0_PARITY_ERR            , 52  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR0_PARITY_ERR );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR01_PARITY_ERR           , 53  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR01_PARITY_ERR );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR1_FSM_CKSTP             , 56  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR1_FSM_CKSTP );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR1_PARITY_CKSTP          , 57  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR1_PARITY_CKSTP );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR1_CALIBRATION_ERROR     , 58  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR1_CALIBRATION_ERROR );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR1_FSM_ERR               , 59  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR1_FSM_ERR );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_MASK_REG_DDR1_PARITY_ERR            , 60  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR1_PARITY_ERR );
+
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR0_FSM_CKSTP                  , 48  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR0_FSM_CKSTP );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR0_PARITY_CKSTP               , 49  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR0_PARITY_CKSTP );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR0_CALIBRATION_ERROR          , 50  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR0_CALIBRATION_ERROR );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR0_FSM_ERR                    , 51  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR0_FSM_ERR );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR0_PARITY_ERR                 , 52  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR0_PARITY_ERR );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR01_PARITY_ERR                , 53  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR01_PARITY_ERR );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR1_FSM_CKSTP                  , 56  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR1_FSM_CKSTP );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR1_PARITY_CKSTP               , 57  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR1_PARITY_CKSTP );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR1_CALIBRATION_ERROR          , 58  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR1_CALIBRATION_ERROR );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR1_FSM_ERR                    , 59  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR1_FSM_ERR );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_REG_DDR1_PARITY_ERR                 , 60  , SH_UNT_MCA      , SH_ACS_SCOM2_OR ,
+           SH_FLD_DDR1_PARITY_ERR );
+
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_WOF_REG_DDR0                        , 48  , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_DDR0       );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_WOF_REG_DDR0_LEN                    , 6   , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_DDR0_LEN   );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_WOF_REG_DDR1                        , 56  , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_DDR1       );
+REG64_FLD( MCA_PHY0_DDRPHY_FIR_WOF_REG_DDR1_LEN                    , 5   , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_DDR1_LEN   );
+
+REG64_FLD( MCA_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                   , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PCB_WDATA_PARITY );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY                 , 1   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_PARITY );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY             , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_WDATA_PARITY );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_DL_RETURN_P0                       , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_P0 );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_UL_RDATA_PARITY                    , 4   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_UL_RDATA_PARITY );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_UL_P0                              , 5   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_UL_P0      );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE        , 6   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE              , 7   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_P2S_MACHINE );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH    , 8   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH    , 10  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD                , 11  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_WRITE_NVLD );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD                 , 12  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_READ_NVLD );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID              , 13  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_ADDR_INVALID );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY                 , 14  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PCB_COMMAND_PARITY );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                    , 15  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_GENERAL_TIMEOUT );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( MCA_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( MCA_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR       , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR );
+REG64_FLD( MCA_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR      , 1   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR );
+REG64_FLD( MCA_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR          , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR );
+REG64_FLD( MCA_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR );
+REG64_FLD( MCA_PSCOM_MODE_REG_WATCHDOG_ENABLE                      , 4   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_WATCHDOG_ENABLE );
+REG64_FLD( MCA_PSCOM_MODE_REG_SCOM_HANG_LIMIT                      , 5   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT );
+REG64_FLD( MCA_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                  , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT_LEN );
+REG64_FLD( MCA_PSCOM_MODE_REG_FORCE_ALL_RINGS                      , 7   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ALL_RINGS );
+REG64_FLD( MCA_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE );
+REG64_FLD( MCA_PSCOM_MODE_REG_RESERVED_LT                          , 9   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT );
+REG64_FLD( MCA_PSCOM_MODE_REG_RESERVED_LT_LEN                      , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT_LEN );
+
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_WDATA_PARITY );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0     , 3   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_P0 );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY  , 4   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_RDATA_PARITY );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0            , 5   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_P0 );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT  , 15  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_GENERAL_TIMEOUT );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY     , 18  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_WDATA_PARITY );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY   , 19  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_ADDRESS_PARITY );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0         , 21  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_P0 );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY      , 22  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_RDATA_PARITY );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0                , 23  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_P0 );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD  , 29  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD   , 30  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_READ_NVLD );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY   , 32  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_COMMAND_PARITY );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT      , 33  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_GENERAL_TIMEOUT );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( MCA_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM                  , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM     );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_LEN              , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_LEN );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1            , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD1 );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1_LEN        , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD1_LEN );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2            , 8   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD2 );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2_LEN        , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD2_LEN );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3            , 12  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD3 );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3_LEN        , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD3_LEN );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4            , 16  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD4 );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4_LEN        , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD4_LEN );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5            , 20  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD5 );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5_LEN        , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD5_LEN );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6            , 24  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD6 );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6_LEN        , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD6_LEN );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7            , 28  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD7 );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7_LEN        , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD7_LEN );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8            , 32  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD8 );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8_LEN        , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD8_LEN );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9            , 36  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD9 );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9_LEN        , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD9_LEN );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10           , 40  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD10 );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10_LEN       , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD10_LEN );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11           , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD11 );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11_LEN       , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD11_LEN );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12           , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD12 );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12_LEN       , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD12_LEN );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13           , 52  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD13 );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13_LEN       , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD13_LEN );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14           , 56  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD14 );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14_LEN       , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD14_LEN );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15           , 60  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD15 );
+REG64_FLD( MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15_LEN       , 4   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LRDIMM_WORD15_LEN );
+
+REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT       , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT );
+REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT             , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT );
+REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_MARK_STORE_WRITE               , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_DISABLE_MARK_STORE_WRITE );
+REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_UE_RETRY                       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_DISABLE_UE_RETRY );
+REG64_FLD( MCA_RECR_MBSECCQ_ITAG_METADATA_ENABLE                   , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_ITAG_METADATA_ENABLE );
+REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_5                             , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_RESERVED_5 );
+REG64_FLD( MCA_RECR_MBSECCQ_READ_POINTER_DELAY                     , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_READ_POINTER_DELAY );
+REG64_FLD( MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN                 , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_READ_POINTER_DELAY_LEN );
+REG64_FLD( MCA_RECR_MBSECCQ_EXIT_OVERRIDE                          , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_EXIT_OVERRIDE );
+REG64_FLD( MCA_RECR_MBSECCQ_EXIT_OVERRIDE_LEN                      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_EXIT_OVERRIDE_LEN );
+REG64_FLD( MCA_RECR_MBSECCQ_HWMARK_EXIT1                           , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_HWMARK_EXIT1 );
+REG64_FLD( MCA_RECR_MBSECCQ_DATA_GENERATOR_OVERRIDE                , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_DATA_GENERATOR_OVERRIDE );
+REG64_FLD( MCA_RECR_MBSECCQ_ECC_SCHEDULER_DELAY                    , 13  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY );
+REG64_FLD( MCA_RECR_MBSECCQ_ECC_SCHEDULER_DELAY_LEN                , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY_LEN );
+REG64_FLD( MCA_RECR_MBSECCQ_VAL_TO_DATA_DELAY                      , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY );
+REG64_FLD( MCA_RECR_MBSECCQ_VAL_TO_DATA_DELAY_LEN                  , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY_LEN );
+REG64_FLD( MCA_RECR_MBSECCQ_DELAY_VALID_1X                         , 19  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_DELAY_VALID_1X );
+REG64_FLD( MCA_RECR_MBSECCQ_NEST_VAL_TO_DATA_DELAY                 , 20  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY );
+REG64_FLD( MCA_RECR_MBSECCQ_NEST_VAL_TO_DATA_DELAY_LEN             , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY_LEN );
+REG64_FLD( MCA_RECR_MBSECCQ_DELAY_NONBYPASS                        , 22  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_DELAY_NONBYPASS );
+REG64_FLD( MCA_RECR_MBSECCQ_ENABLE_SPECIAL_ATTENTION               , 23  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_ENABLE_SPECIAL_ATTENTION );
+REG64_FLD( MCA_RECR_MBSECCQ_ENABLE_HOST_ATTENTION                  , 24  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_ENABLE_HOST_ATTENTION );
+REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_MPE_CONFIRM                    , 25  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_DISABLE_MPE_CONFIRM );
+REG64_FLD( MCA_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW                 , 26  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_ENABLE_UE_NOISE_WINDOW );
+REG64_FLD( MCA_RECR_MBSECCQ_ENABLE_TCE_CORRECTION                  , 27  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_ENABLE_TCE_CORRECTION );
+REG64_FLD( MCA_RECR_MBSECCQ_ENABLE_CHIPMARKED_SCE_NCE              , 28  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_ENABLE_CHIPMARKED_SCE_NCE );
+REG64_FLD( MCA_RECR_MBSECCQ_USE_ADDRESS_HASH                       , 29  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_USE_ADDRESS_HASH );
+REG64_FLD( MCA_RECR_MBSECCQ_DATA_INVERSION                         , 30  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_DATA_INVERSION );
+REG64_FLD( MCA_RECR_MBSECCQ_DATA_INVERSION_LEN                     , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_DATA_INVERSION_LEN );
+REG64_FLD( MCA_RECR_MBSECCQ_DISABLE_PIPE_NOERR_CLOCK_GATING        , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_DISABLE_PIPE_NOERR_CLOCK_GATING );
+REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_33_39                         , 33  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_RESERVED_33_39 );
+REG64_FLD( MCA_RECR_MBSECCQ_RESERVED_33_39_LEN                     , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBSECCQ_RESERVED_33_39_LEN );
+
+REG64_FLD( MCA_RING_FENCE_MASK_LATCH_REG_DISABLED                  , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED   );
+REG64_FLD( MCA_RING_FENCE_MASK_LATCH_REG_ENABLE                    , 1   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( MCA_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN                , 15  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR                      , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RUNTIME_CTR );
+REG64_FLD( MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR_LEN                  , 37  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_RUNTIME_CTR_LEN );
+
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_HI_DATA_REG_DATA             , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_HI_DATA_REG_DATA_LEN         , 64  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_DATA             , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_DATA_LEN         , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_ADDRESS          , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_ADDRESS_LEN      , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_LAST_BANK        , 42  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_LAST_BANK_LEN    , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_LAST_BANK_VALID  , 51  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_WRITE_ON_RUN     , 52  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_RUNNING          , 53  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS     , 54  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA     , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB     , 24  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC     , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND     , 24  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKA        , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKA_LEN    , 24  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKB        , 24  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_4_MASKB_LEN    , 24  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKC        , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKC_LEN    , 24  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKD        , 24  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_5_MASKD_LEN    , 24  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_MCA      ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( MCA_TCMC01_SLOW_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( MCBIST_WATCFG0AQ_CFG_WAT_EVENT_SEL                      , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EVENT_SEL );
+REG64_FLD( MCBIST_WATCFG0AQ_CFG_WAT_EVENT_SEL_LEN                  , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EVENT_SEL_LEN );
+
+REG64_FLD( MCBIST_WATCFG0BQ_CFG_WAT_MSKA                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKA );
+REG64_FLD( MCBIST_WATCFG0BQ_CFG_WAT_MSKA_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKA_LEN );
+REG64_FLD( MCBIST_WATCFG0BQ_CFG_WAT_CNTL                           , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_CNTL );
+REG64_FLD( MCBIST_WATCFG0BQ_CFG_WAT_CNTL_LEN                       , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_CNTL_LEN );
+
+REG64_FLD( MCBIST_WATCFG0CQ_CFG_WAT_MSKB                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKB );
+REG64_FLD( MCBIST_WATCFG0CQ_CFG_WAT_MSKB_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKB_LEN );
+
+REG64_FLD( MCBIST_WATCFG0DQ_CFG_WAT_PATA                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATA );
+REG64_FLD( MCBIST_WATCFG0DQ_CFG_WAT_PATA_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATA_LEN );
+
+REG64_FLD( MCBIST_WATCFG0EQ_CFG_WAT_PATB                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATB );
+REG64_FLD( MCBIST_WATCFG0EQ_CFG_WAT_PATB_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATB_LEN );
+
+REG64_FLD( MCBIST_WATCFG1AQ_CFG_WAT_EVENT_SEL                      , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EVENT_SEL );
+REG64_FLD( MCBIST_WATCFG1AQ_CFG_WAT_EVENT_SEL_LEN                  , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EVENT_SEL_LEN );
+
+REG64_FLD( MCBIST_WATCFG1BQ_CFG_WAT_MSKA                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKA );
+REG64_FLD( MCBIST_WATCFG1BQ_CFG_WAT_MSKA_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKA_LEN );
+REG64_FLD( MCBIST_WATCFG1BQ_CFG_WAT_CNTL                           , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_CNTL );
+REG64_FLD( MCBIST_WATCFG1BQ_CFG_WAT_CNTL_LEN                       , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_CNTL_LEN );
+
+REG64_FLD( MCBIST_WATCFG1CQ_CFG_WAT_MSKB                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKB );
+REG64_FLD( MCBIST_WATCFG1CQ_CFG_WAT_MSKB_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKB_LEN );
+
+REG64_FLD( MCBIST_WATCFG1DQ_CFG_WAT_PATA                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATA );
+REG64_FLD( MCBIST_WATCFG1DQ_CFG_WAT_PATA_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATA_LEN );
+
+REG64_FLD( MCBIST_WATCFG1EQ_CFG_WAT_PATB                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATB );
+REG64_FLD( MCBIST_WATCFG1EQ_CFG_WAT_PATB_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATB_LEN );
+
+REG64_FLD( MCBIST_WATCFG2AQ_CFG_WAT_EVENT_SEL                      , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EVENT_SEL );
+REG64_FLD( MCBIST_WATCFG2AQ_CFG_WAT_EVENT_SEL_LEN                  , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EVENT_SEL_LEN );
+
+REG64_FLD( MCBIST_WATCFG2BQ_CFG_WAT_MSKA                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKA );
+REG64_FLD( MCBIST_WATCFG2BQ_CFG_WAT_MSKA_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKA_LEN );
+REG64_FLD( MCBIST_WATCFG2BQ_CFG_WAT_CNTL                           , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_CNTL );
+REG64_FLD( MCBIST_WATCFG2BQ_CFG_WAT_CNTL_LEN                       , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_CNTL_LEN );
+
+REG64_FLD( MCBIST_WATCFG2CQ_CFG_WAT_MSKB                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKB );
+REG64_FLD( MCBIST_WATCFG2CQ_CFG_WAT_MSKB_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKB_LEN );
+
+REG64_FLD( MCBIST_WATCFG2DQ_CFG_WAT_PATA                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATA );
+REG64_FLD( MCBIST_WATCFG2DQ_CFG_WAT_PATA_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATA_LEN );
+
+REG64_FLD( MCBIST_WATCFG2EQ_CFG_WAT_PATB                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATB );
+REG64_FLD( MCBIST_WATCFG2EQ_CFG_WAT_PATB_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATB_LEN );
+
+REG64_FLD( MCBIST_WATCFG3AQ_CFG_WAT_EVENT_SEL                      , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EVENT_SEL );
+REG64_FLD( MCBIST_WATCFG3AQ_CFG_WAT_EVENT_SEL_LEN                  , 48  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_EVENT_SEL_LEN );
+
+REG64_FLD( MCBIST_WATCFG3BQ_CFG_WAT_MSKA                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKA );
+REG64_FLD( MCBIST_WATCFG3BQ_CFG_WAT_MSKA_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKA_LEN );
+REG64_FLD( MCBIST_WATCFG3BQ_CFG_WAT_CNTL                           , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_CNTL );
+REG64_FLD( MCBIST_WATCFG3BQ_CFG_WAT_CNTL_LEN                       , 17  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_CNTL_LEN );
+
+REG64_FLD( MCBIST_WATCFG3CQ_CFG_WAT_MSKB                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKB );
+REG64_FLD( MCBIST_WATCFG3CQ_CFG_WAT_MSKB_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_MSKB_LEN );
+
+REG64_FLD( MCBIST_WATCFG3DQ_CFG_WAT_PATA                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATA );
+REG64_FLD( MCBIST_WATCFG3DQ_CFG_WAT_PATA_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATA_LEN );
+
+REG64_FLD( MCBIST_WATCFG3EQ_CFG_WAT_PATB                           , 0   , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATB );
+REG64_FLD( MCBIST_WATCFG3EQ_CFG_WAT_PATB_LEN                       , 44  , SH_UNT_MCBIST   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WAT_PATB_LEN );
+
+REG64_FLD( MCA_WBMGR_TAG_INFO_BUFFER_OVERRUN                       , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_BUFFER_OVERRUN );
+REG64_FLD( MCA_WBMGR_TAG_INFO_OVERRUN                              , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_OVERRUN    );
+REG64_FLD( MCA_WBMGR_TAG_INFO_REL_ASYNC_PARITY_ERROR               , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REL_ASYNC_PARITY_ERROR );
+REG64_FLD( MCA_WBMGR_TAG_INFO_REL_ASYNC_SEQUENCE_ERROR             , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REL_ASYNC_SEQUENCE_ERROR );
+REG64_FLD( MCA_WBMGR_TAG_INFO_REL_MERGE_ASYNC_PARITY_ERROR         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REL_MERGE_ASYNC_PARITY_ERROR );
+REG64_FLD( MCA_WBMGR_TAG_INFO_REL_MERGE_ASYNC_SEQUENCE_ERROR       , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_REL_MERGE_ASYNC_SEQUENCE_ERROR );
+REG64_FLD( MCA_WBMGR_TAG_INFO_INFORMATION                          , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_INFORMATION );
+REG64_FLD( MCA_WBMGR_TAG_INFO_INFORMATION_LEN                      , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_INFORMATION_LEN );
+
+REG64_FLD( MCA_WDFCFG_CFG_WRITE_MODE_ECC_CHK_DIS                   , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRITE_MODE_ECC_CHK_DIS );
+REG64_FLD( MCA_WDFCFG_CFG_WRITE_MODE_ECC_COR_DIS                   , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRITE_MODE_ECC_COR_DIS );
+REG64_FLD( MCA_WDFCFG_CFG_WDF_SERIAL_SEQ_MODE                      , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WDF_SERIAL_SEQ_MODE );
+REG64_FLD( MCA_WDFCFG_RESET_KEEPER                                 , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESET_KEEPER );
+REG64_FLD( MCA_WDFCFG_MERGE_CAPACITY_LIMIT                         , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MERGE_CAPACITY_LIMIT );
+REG64_FLD( MCA_WDFCFG_MERGE_CAPACITY_LIMIT_LEN                     , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MERGE_CAPACITY_LIMIT_LEN );
+REG64_FLD( MCA_WDFCFG_8_11_SPARE                                   , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_8_11_SPARE );
+REG64_FLD( MCA_WDFCFG_8_11_SPARE_LEN                               , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_8_11_SPARE_LEN );
+REG64_FLD( MCA_WDFCFG_ASYNC_INJ                                    , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ASYNC_INJ  );
+REG64_FLD( MCA_WDFCFG_ASYNC_INJ_LEN                                , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ASYNC_INJ_LEN );
+REG64_FLD( MCA_WDFCFG_18_31_SPARE                                  , 18  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_18_31_SPARE );
+REG64_FLD( MCA_WDFCFG_18_31_SPARE_LEN                              , 14  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_18_31_SPARE_LEN );
+REG64_FLD( MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE_SELECT                  , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT );
+REG64_FLD( MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE_SELECT_LEN              , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT_LEN );
+REG64_FLD( MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE                         , 36  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_WDF_HCA_TIMEBASE );
+REG64_FLD( MCA_WDFCFG_ECC_WDF_HCA_TIMEBASE_LEN                     , 28  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_WDF_HCA_TIMEBASE_LEN );
+
+REG64_FLD( MCA_WDFDBG_DBG_SEL_IN                                   , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_IN );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_WDF                                  , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_WDF );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ0_DEBUG_0                       , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_PWSEQ0_DEBUG_0 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ0_DEBUG_1                       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_PWSEQ0_DEBUG_1 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ1_DEBUG_0                       , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_PWSEQ1_DEBUG_0 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ1_DEBUG_1                       , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_PWSEQ1_DEBUG_1 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ2_DEBUG_0                       , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_PWSEQ2_DEBUG_0 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ2_DEBUG_1                       , 7   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_PWSEQ2_DEBUG_1 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ3_DEBUG_0                       , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_PWSEQ3_DEBUG_0 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ3_DEBUG_1                       , 9   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_PWSEQ3_DEBUG_1 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ4_DEBUG_0                       , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_PWSEQ4_DEBUG_0 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ4_DEBUG_1                       , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_PWSEQ4_DEBUG_1 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ5_DEBUG_0                       , 12  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_PWSEQ5_DEBUG_0 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_PWSEQ5_DEBUG_1                       , 13  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_PWSEQ5_DEBUG_1 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_PWCTL_DEBUG                          , 14  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_PWCTL_DEBUG );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_WDFMGR_DEBUG                         , 15  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_WDFMGR_DEBUG );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_WDFRD_DEBUG_0                        , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_WDFRD_DEBUG_0 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_WDFRD_DEBUG_1                        , 17  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_WDFRD_DEBUG_1 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_WDFWR_DEBUG_0                        , 18  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_WDFWR_DEBUG_0 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_WDFWR_DEBUG_1                        , 19  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_WDFWR_DEBUG_1 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_SEC_WDFRD_DEBUG_0                    , 20  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_0 );
+REG64_FLD( MCA_WDFDBG_DBG_SEL_SEC_WDFRD_DEBUG_1                    , 21  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_1 );
+REG64_FLD( MCA_WDFDBG_DBG_SPARE                                    , 22  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SPARE  );
+REG64_FLD( MCA_WDFDBG_DBG_SPARE_LEN                                , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SPARE_LEN );
+REG64_FLD( MCA_WDFDBG_WAT_EVENT_ENABLE                             , 32  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_EVENT_ENABLE );
+REG64_FLD( MCA_WDFDBG_WAT_SPARE1                                   , 33  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_SPARE1 );
+REG64_FLD( MCA_WDFDBG_WAT_SPARE1_LEN                               , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_SPARE1_LEN );
+REG64_FLD( MCA_WDFDBG_WAT0_EVENT_SELECT                            , 36  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT0_EVENT_SELECT );
+REG64_FLD( MCA_WDFDBG_WAT0_EVENT_SELECT_LEN                        , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT0_EVENT_SELECT_LEN );
+REG64_FLD( MCA_WDFDBG_WAT1_EVENT_SELECT                            , 40  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT1_EVENT_SELECT );
+REG64_FLD( MCA_WDFDBG_WAT1_EVENT_SELECT_LEN                        , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT1_EVENT_SELECT_LEN );
+
+REG64_FLD( MCA_WECR_MBA_WRD_MODE_CFG_WRD_ECC_CHK_DISABLE           , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_CHK_DISABLE );
+REG64_FLD( MCA_WECR_MBA_WRD_MODE_CFG_WRD_ECC_COR_DISABLE           , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_COR_DISABLE );
+REG64_FLD( MCA_WECR_MBA_WRD_MODE_CFG_CRC_MODE_EN                   , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_EN );
+REG64_FLD( MCA_WECR_MBA_WRD_MODE_CFG_CRC_MODE_X8                   , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_X8 );
+REG64_FLD( MCA_WECR_MBA_WRD_MODE_RESERVED_4                        , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBA_WRD_MODE_RESERVED_4 );
+REG64_FLD( MCA_WECR_MBA_WRD_MODE_CFG_CAW2_CE_UE_ERR_DETECT_EN      , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MBA_WRD_MODE_CFG_CAW2_CE_UE_ERR_DETECT_EN );
+
+REG64_FLD( MCA_WESR_SYNDROME                                       , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_SYNDROME   );
+REG64_FLD( MCA_WESR_SYNDROME_LEN                                   , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_SYNDROME_LEN );
+REG64_FLD( MCA_WESR_WHICH_8BECK                                    , 8   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WHICH_8BECK );
+REG64_FLD( MCA_WESR_WHICH_8BECK_LEN                                , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WHICH_8BECK_LEN );
+REG64_FLD( MCA_WESR_PAR_ERR_ONLY                                   , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PAR_ERR_ONLY );
+
+REG64_FLD( MCA_WOF_FIR                                             , 0   , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_FIR        );
+REG64_FLD( MCA_WOF_FIR_LEN                                         , 64  , SH_UNT_MCA      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_FIR_LEN    );
+
+REG64_FLD( MCA_WRITE_PROTECT_ENABLE_REG_RING_LOCKING               , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_RING_LOCKING );
+REG64_FLD( MCA_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING      , 1   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_RING_LOCKING );
+
+REG64_FLD( MCA_WRITE_PROTECT_RINGS_REG_RINGS                       , 0   , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_RINGS      );
+REG64_FLD( MCA_WRITE_PROTECT_RINGS_REG_RINGS_LEN                   , 16  , SH_UNT_MCA      , SH_ACS_SCOM     ,
+           SH_FLD_RINGS_LEN  );
+
+REG64_FLD( MCA_WRTCFG_CFG_WRITE_MODE_ECC_CHK_DIS                   , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRITE_MODE_ECC_CHK_DIS );
+REG64_FLD( MCA_WRTCFG_CFG_WRITE_MODE_ECC_COR_DIS                   , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_WRITE_MODE_ECC_COR_DIS );
+REG64_FLD( MCA_WRTCFG_RESET_KEEPER                                 , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESET_KEEPER );
+REG64_FLD( MCA_WRTCFG_SPARE                                        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE      );
+REG64_FLD( MCA_WRTCFG_ASYNC_INJ                                    , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ASYNC_INJ  );
+REG64_FLD( MCA_WRTCFG_ASYNC_INJ_LEN                                , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_ASYNC_INJ_LEN );
+
+REG64_FLD( MCA_WRTDBGMCA_MCA_DBG_SEL_IN                            , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCA_DBG_SEL_IN );
+REG64_FLD( MCA_WRTDBGMCA_MCA_DBG_SEL_WRT                           , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_MCA_DBG_SEL_WRT );
+REG64_FLD( MCA_WRTDBGMCA_WBRD_DEBUG_0_SELECT                       , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WBRD_DEBUG_0_SELECT );
+REG64_FLD( MCA_WRTDBGMCA_WBRD_DEBUG_1_SELECT                       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WBRD_DEBUG_1_SELECT );
+REG64_FLD( MCA_WRTDBGMCA_SEC_WBRD_DEBUG_0_SELECT                   , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEC_WBRD_DEBUG_0_SELECT );
+REG64_FLD( MCA_WRTDBGMCA_SEC_WBRD_DEBUG_1_SELECT                   , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEC_WBRD_DEBUG_1_SELECT );
+REG64_FLD( MCA_WRTDBGMCA_DBG_SPARE_MCA                             , 6   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SPARE_MCA );
+REG64_FLD( MCA_WRTDBGMCA_DBG_SPARE_MCA_LEN                         , 10  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SPARE_MCA_LEN );
+REG64_FLD( MCA_WRTDBGMCA_WAT_EVENT_ENABLE_MCA                      , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_EVENT_ENABLE_MCA );
+REG64_FLD( MCA_WRTDBGMCA_WAT_SPARE1_MCA                            , 17  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_SPARE1_MCA );
+REG64_FLD( MCA_WRTDBGMCA_WAT_SPARE1_MCA_LEN                        , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_SPARE1_MCA_LEN );
+REG64_FLD( MCA_WRTDBGMCA_WAT0_EVENT_SELECT_MCA                     , 20  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT0_EVENT_SELECT_MCA );
+REG64_FLD( MCA_WRTDBGMCA_WAT0_EVENT_SELECT_MCA_LEN                 , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT0_EVENT_SELECT_MCA_LEN );
+REG64_FLD( MCA_WRTDBGMCA_WAT1_EVENT_SELECT_MCA                     , 24  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT1_EVENT_SELECT_MCA );
+REG64_FLD( MCA_WRTDBGMCA_WAT1_EVENT_SELECT_MCA_LEN                 , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT1_EVENT_SELECT_MCA_LEN );
+
+REG64_FLD( MCA_WRTDBGNEST_NEST_DBG_SEL_IN                          , 0   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_NEST_DBG_SEL_IN );
+REG64_FLD( MCA_WRTDBGNEST_NEST_DBG_SEL_WRT                         , 1   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_NEST_DBG_SEL_WRT );
+REG64_FLD( MCA_WRTDBGNEST_WBMGR_DBG_0_SELECT                       , 2   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WBMGR_DBG_0_SELECT );
+REG64_FLD( MCA_WRTDBGNEST_WBMGR_DBG_1_SELECT                       , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WBMGR_DBG_1_SELECT );
+REG64_FLD( MCA_WRTDBGNEST_WRCNTL_DBG_SELECT                        , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRCNTL_DBG_SELECT );
+REG64_FLD( MCA_WRTDBGNEST_DBG_SPARE_NEST                           , 5   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SPARE_NEST );
+REG64_FLD( MCA_WRTDBGNEST_DBG_SPARE_NEST_LEN                       , 11  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_SPARE_NEST_LEN );
+REG64_FLD( MCA_WRTDBGNEST_WAT_EVENT_ENABLE_NEST                    , 16  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_EVENT_ENABLE_NEST );
+REG64_FLD( MCA_WRTDBGNEST_WAT_SPARE1_NEST                          , 17  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_SPARE1_NEST );
+REG64_FLD( MCA_WRTDBGNEST_WAT_SPARE1_NEST_LEN                      , 3   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT_SPARE1_NEST_LEN );
+REG64_FLD( MCA_WRTDBGNEST_WAT0_EVENT_SELECT_NEST                   , 20  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT0_EVENT_SELECT_NEST );
+REG64_FLD( MCA_WRTDBGNEST_WAT0_EVENT_SELECT_NEST_LEN               , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT0_EVENT_SELECT_NEST_LEN );
+REG64_FLD( MCA_WRTDBGNEST_WAT1_EVENT_SELECT_NEST                   , 24  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT1_EVENT_SELECT_NEST );
+REG64_FLD( MCA_WRTDBGNEST_WAT1_EVENT_SELECT_NEST_LEN               , 4   , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           SH_FLD_WAT1_EVENT_SELECT_NEST_LEN );
+
+REG64_FLD( MCA_WDF_WRT_ECC_DW0_ERR_TYPE                            , 0   , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW0_ERR_TYPE );
+REG64_FLD( MCA_WDF_WRT_ECC_DW0_ERR_TYPE_LEN                        , 3   , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW0_ERR_TYPE_LEN );
+REG64_FLD( MCA_WDF_WRT_ECC_DW0_SYNDROME                            , 8   , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW0_SYNDROME );
+REG64_FLD( MCA_WDF_WRT_ECC_DW0_SYNDROME_LEN                        , 8   , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW0_SYNDROME_LEN );
+REG64_FLD( MCA_WDF_WRT_ECC_DW1_ERR_TYPE                            , 16  , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW1_ERR_TYPE );
+REG64_FLD( MCA_WDF_WRT_ECC_DW1_ERR_TYPE_LEN                        , 3   , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW1_ERR_TYPE_LEN );
+REG64_FLD( MCA_WDF_WRT_ECC_DW1_SYNDROME                            , 24  , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW1_SYNDROME );
+REG64_FLD( MCA_WDF_WRT_ECC_DW1_SYNDROME_LEN                        , 8   , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW1_SYNDROME_LEN );
+REG64_FLD( MCA_WDF_WRT_ECC_DW2_ERR_TYPE                            , 32  , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW2_ERR_TYPE );
+REG64_FLD( MCA_WDF_WRT_ECC_DW2_ERR_TYPE_LEN                        , 3   , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW2_ERR_TYPE_LEN );
+REG64_FLD( MCA_WDF_WRT_ECC_DW2_SYNDROME                            , 40  , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW2_SYNDROME );
+REG64_FLD( MCA_WDF_WRT_ECC_DW2_SYNDROME_LEN                        , 8   , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW2_SYNDROME_LEN );
+REG64_FLD( MCA_WDF_WRT_ECC_DW3_ERR_TYPE                            , 48  , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW3_ERR_TYPE );
+REG64_FLD( MCA_WDF_WRT_ECC_DW3_ERR_TYPE_LEN                        , 3   , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW3_ERR_TYPE_LEN );
+REG64_FLD( MCA_WDF_WRT_ECC_DW3_SYNDROME                            , 56  , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW3_SYNDROME );
+REG64_FLD( MCA_WDF_WRT_ECC_DW3_SYNDROME_LEN                        , 8   , SH_UNT_MCA_WDF  , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW3_SYNDROME_LEN );
+
+REG64_FLD( MCA_WREITE_WRT_ECC_DW0_ERR_TYPE                         , 0   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW0_ERR_TYPE );
+REG64_FLD( MCA_WREITE_WRT_ECC_DW0_ERR_TYPE_LEN                     , 3   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW0_ERR_TYPE_LEN );
+REG64_FLD( MCA_WREITE_WRT_ECC_DW0_SYNDROME                         , 8   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW0_SYNDROME );
+REG64_FLD( MCA_WREITE_WRT_ECC_DW0_SYNDROME_LEN                     , 8   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW0_SYNDROME_LEN );
+REG64_FLD( MCA_WREITE_WRT_ECC_DW1_ERR_TYPE                         , 16  , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW1_ERR_TYPE );
+REG64_FLD( MCA_WREITE_WRT_ECC_DW1_ERR_TYPE_LEN                     , 3   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW1_ERR_TYPE_LEN );
+REG64_FLD( MCA_WREITE_WRT_ECC_DW1_SYNDROME                         , 24  , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW1_SYNDROME );
+REG64_FLD( MCA_WREITE_WRT_ECC_DW1_SYNDROME_LEN                     , 8   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW1_SYNDROME_LEN );
+REG64_FLD( MCA_WREITE_WRT_ECC_DW2_ERR_TYPE                         , 32  , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW2_ERR_TYPE );
+REG64_FLD( MCA_WREITE_WRT_ECC_DW2_ERR_TYPE_LEN                     , 3   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW2_ERR_TYPE_LEN );
+REG64_FLD( MCA_WREITE_WRT_ECC_DW2_SYNDROME                         , 40  , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW2_SYNDROME );
+REG64_FLD( MCA_WREITE_WRT_ECC_DW2_SYNDROME_LEN                     , 8   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW2_SYNDROME_LEN );
+REG64_FLD( MCA_WREITE_WRT_ECC_DW3_ERR_TYPE                         , 48  , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW3_ERR_TYPE );
+REG64_FLD( MCA_WREITE_WRT_ECC_DW3_ERR_TYPE_LEN                     , 3   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW3_ERR_TYPE_LEN );
+REG64_FLD( MCA_WREITE_WRT_ECC_DW3_SYNDROME                         , 56  , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW3_SYNDROME );
+REG64_FLD( MCA_WREITE_WRT_ECC_DW3_SYNDROME_LEN                     , 8   , SH_UNT_MCA_WREITE, SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DW3_SYNDROME_LEN );
+
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H
new file mode 100644
index 00000000..0c27c47f
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file mc_scom_addresses_fld_fixes.H
+/// @brief The *scom_addresses_fld.H files are generated form figtree,
+///        but the figree can be wrong.  This file is included in
+///        *_scom_addresses_fld.H and allows incorrect constants to be
+///        fixed manually.
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SAO
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __P9_MC_SCOM_ADDRESSES_FLD_FIXES_H
+#define __P9_MC_SCOM_ADDRESSES_FLD_FIXES_H
+
+//Example
+//Copy the whole line from the *scom_addresses_fld.H file.  Then add FIX in front of REG
+//and add another paramter that is the new value you want.
+//
+//FIXREG64_FLD( PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE, 24, SH_UNT, SH_ACS_SCOM, SH_FLD_FBC_WITH_TM_QUIESCE,
+//              12);
+
+static const uint64_t SH_FLD_COMMAND_LIST_TIMEOUT_SPEC = 99990000;
+
+REG64_FLD( MCS_MCFIR_COMMAND_LIST_TIMEOUT_SPEC                     , 9   , SH_UNT_MCS      , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMMAND_LIST_TIMEOUT_SPEC );
+
+REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ENABLE               , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           0 );
+
+REG64_FLD( MCA_DDRPHY_WC_RTT_WL_SWAP_ENABLE_P0                     , 48  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           0 );
+REG64_FLD( MCA_DDRPHY_WC_RTT_WR_CTL_SWAP_ENABLE_P0                 , 49  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           0 );
+
+REG64_FLD( MCBIST_MCBCFGQ_CFG_MCBIST_CFG_FORCE_PAUSE_AFTER_RANK    , 34  , SH_UNT_MCA      , SH_ACS_SCOM_RW  ,
+           0 );
+
+#endif
diff --git a/src/import/chips/p9/common/include/p9_misc_scom_addresses.H b/src/import/chips/p9/common/include/p9_misc_scom_addresses.H
new file mode 100644
index 00000000..c387ea06
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_misc_scom_addresses.H
@@ -0,0 +1,10465 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_misc_scom_addresses.H $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_misc_scom_addresses.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+/*---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ *
+ *  Issues:
+ *
+ * Closed
+ *    TOD reg same address.             HW323439
+ *       - Issue was closed with the explaination "same as p8"
+ *    IO0 registers need fixed.         HW320437
+ *    PHB registers need fixed.         HW320416  ( all regs commented out now )
+ *    OSC/perv regs same address.       HW323437
+ *    MC regs with same address.        HW323435 (matteo)
+ *         Duplicate IOM registers.          HW320456 (designers)
+ *    PEC Sat_id issue                  HW329652
+ *    PB.PB_PPE registers need fixed.   HW320435
+ *    EX05 registers need fixed.        HW320427  (9020) - L2 ring id's are incorrect
+ *    IOFPPE registers need fixed.      HW320424  (9020) - Investigate NULL scope
+ *    PEC addresses are wrong.          HW322598  (9020)
+ *    MC registers need fixed.          HW320433
+ *    VA.VA_NORTH registers need fixed. HW320436
+ *
+ * Format:
+ *
+ *  <UNIT>_<SUBUNIT>_<INSTANCE>_<REGISTER>_<ACCESS/TYPE>
+ *
+ *  Notes: Subunits are only added to make names unique when
+ *  there are name collisions.
+ *  Only units with more than one instance has instance numbers.
+ *  If there is only one, the instance number is omitted.
+ *
+ *  Instance numbers are chiplet id's for the PERV unit.  The
+ *  chiplet id's are mapped to their name and used instead of
+ *  instance numbers.  See bellow.
+ *
+ *  For registers with a single access type the type and access
+ *  methods are omitted.
+ *
+ *  For access types where all bits have the same access methods, the
+ *  access method is appended to the name.  If the access methods
+ *  are different for some bits, the access type is appended to the
+ *  name _SCOM instead of _RO.  The _RW(X) access method is omitted
+ *  and assumed to be default.
+ *
+ *  Valid units / subunits
+ *    PU                    : No unit chip level
+ *        MCD0[0..1]        : mcd subunit
+ *        PIB2OPB[0..1]     : PIB2OPB subunit
+ *        OTPROM[0..1]      : otprom subunit
+ *        NPU               : common npu subunit
+ *        NPU[0..2]         : Npu stacks 0 to 2
+ *          CTL             : Npu CTL subunit
+ *          DAT             : Npu DAT subunit
+ *          SM[0..3]        : Npu SM subunits
+ *          NTL[0..1]       : Npu NTL subunit
+ *    PERV                  : Pervasive
+ *        FSI2PIB           : subunit
+ *        FSISHIFT          : subunit
+ *        FSII2C            : subunit
+ *        FSB               : subunit
+ *    EX                    : Ex unit (1/2 quad, 2 cores)
+ *        L2                : L2 subunit
+ *        L3                : L3 subunit
+ *    PEC                   : PCI Pec unit
+ *        STACK0            : subunit
+ *        STACK1            : subunit
+ *        STACK2            : subunit
+ *    C                     : core
+ *    EQ                    : quad
+ *    OBUS                  : obus
+ *    CAPP                  : capp
+ *    MCBIST                : mcbist
+ *    MCA                   : mca
+ *    NVBUS                 : (not implemented yet)
+ *    PHB                   : (not implemented yet)
+ *    MI                    : (not implemented yet)
+ *    DMI                   : (not implemented yet)
+ *    MCS                   : (not implemented yet)
+ *    OCC                   : (not implemented yet)
+ *    PPE                   : (not implemented yet)
+ *    SBE                   : (not implemented yet)
+ *    XBUS                  : (not implemented yet)
+ *
+ * Pervasive instance names follow chiplet id.
+ *
+ * Instance/  | Chiplet
+ * Chiplet    | name
+ * -----------+-----------
+ * 0x00       | PIB
+ * 0x01       | TP
+ * 0x02       | N0
+ * 0x03       | N1
+ * 0x04       | N2
+ * 0x05       | N3
+ * 0x06       | XB
+ * 0x07       | MC01
+ * 0x08       | MC23
+ * 0x09       | OB0
+ * 0x0A       | OB1
+ * 0x0B       | OB2
+ * 0x0C       | OB3
+ * 0x0D       | PCI0
+ * 0x0E       | PCI1
+ * 0x0F       | PCI2
+ * 0x10       | EP00
+ * 0x11       | EP01
+ * 0x12       | EP02
+ * 0x13       | EP03
+ * 0x14       | EP04
+ * 0x15       | EP05
+ * 0x20       | EC00
+ * 0x21       | EC01
+ * 0x22       | EC02
+ * 0x23       | EC03
+ * 0x24       | EC04
+ * 0x25       | EC05
+ * 0x26       | EC06
+ * 0x27       | EC07
+ * 0x28       | EC08
+ * 0x29       | EC09
+ * 0x2A       | EC10
+ * 0x2B       | EC11
+ * 0x2C       | EC12
+ * 0x2D       | EC13
+ * 0x2E       | EC14
+ * 0x2F       | EC15
+ * 0x30       | EC16
+ * 0x31       | EC17
+ * 0x32       | EC18
+ * 0x33       | EC19
+ * 0x34       | EC20
+ * 0x35       | EC21
+ * 0x36       | EC22
+ * 0x37       | EC23
+ *
+ *
+ *---------------------------------------------------------------
+ *
+ * NOTES:
+ *
+ * there is a SPR ring that goes around the chip with an
+ * address(0:9)/tid(0:1) (thread id)/mfspr_data(0:63) and return mfspr_data_v/mfspr_data(0:63)
+ *
+ *    Add PU_<SUBUNITS>  (only if there are conflicts on these registers)
+ *       0x0001XXXX OTPROM
+ *       0x0002XXXX FSIM0
+ *       0x0003XXXX FSIM1
+ *       0x0004XXXX TOD
+ *       0x0005XXXX FSI_MBOX
+ *       0x0006XXXX OCI_BRIDGE
+ *       0x0007XXXX SPI_ADC
+ *       0x0008XXXX PIBMEM
+ *       0x0009XXXX ADU
+ *       0x000AXXXX I2CM
+ *       0x000BXXXX SBE_FIFO
+ *       0x000DXXXX PSU
+ *       0x000EXXXX SBE
+ *
+ * 0x0000100A for FSI2PIB  => PERV_FSI2PIB
+ * 0x00000Cxx for FSISHIFT =>  PERV_FSISHIFT
+ * 0x000018xx for FSI I2C =>  PERV_FSII2C
+ * 0x000024xx for FSI SBEFIFO => PERV_FSB
+ *
+ * 0x00000400 PEEK_TABLE
+ * 0x00000800 FSI_SLAVE
+ * 0x00000C00 FSI_SHIFT
+ * 0x00001000 FSI2PIB
+ * 0x00001400 FSI_SCRATCHPAD
+ * 0x00001800 FSI_I2CM
+ * 0x00002400 FSI_SBE_FIFO
+ *
+ * address fields
+ * 0xCCRPxxxx
+ *
+ * CC=chiplet
+ * R=always 0?
+ * P=port
+ *   0=gpregs
+ *   1=normal unit scom ring (exclude)
+ *   3=clock controller
+ *   4=firs
+ *   5=cpm
+ *
+ * =============================================================================
+ * Compiling
+ *
+ * Precompile the header to save time on subsquent compiles:
+ * g++ -I. -c scom_addresses.H
+ *
+ * Use these options to help reduce the binary size
+ * g++ -I. -Os -fdata-sections -ffunction-sections <file>.C -o <output> -Wl,--gc-sections
+ *
+ *
+ *---------------------------------------------------------------
+ */
+
+#include <p9_const_common.H>
+
+
+#ifndef __P9_MISC_SCOM_ADDRESSES_H
+#define __P9_MISC_SCOM_ADDRESSES_H
+
+
+#include <p9_scom_template_consts.H>
+#include <p9_misc_scom_addresses_fixes.H>
+
+
+REG64( PHB_ACT0_REG                                            , RULL(0x0D01090E), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_0_ACT0_REG                                          , RULL(0x0D01090E), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_ACT0_REG                                          , RULL(0x0E01090E), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_ACT0_REG                                          , RULL(0x0E01094E), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_ACT0_REG                                          , RULL(0x0F01090E), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_ACT0_REG                                          , RULL(0x0F01094E), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_ACT0_REG                                          , RULL(0x0F01098E), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+
+REG64( PHB_ACTION1_REG                                         , RULL(0x0D01090F), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_0_ACTION1_REG                                       , RULL(0x0D01090F), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_ACTION1_REG                                       , RULL(0x0E01090F), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_ACTION1_REG                                       , RULL(0x0E01094F), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_ACTION1_REG                                       , RULL(0x0F01090F), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_ACTION1_REG                                       , RULL(0x0F01094F), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_ACTION1_REG                                       , RULL(0x0F01098F), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_0_HASH_FUNCTION_REG                             , RULL(0x02011141), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_10_HASH_FUNCTION_REG                            , RULL(0x0201114B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_1_HASH_FUNCTION_REG                             , RULL(0x02011142), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_2_HASH_FUNCTION_REG                             , RULL(0x02011143), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_3_HASH_FUNCTION_REG                             , RULL(0x02011144), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_4_HASH_FUNCTION_REG                             , RULL(0x02011145), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_5_HASH_FUNCTION_REG                             , RULL(0x02011146), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_6_HASH_FUNCTION_REG                             , RULL(0x02011147), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_7_HASH_FUNCTION_REG                             , RULL(0x02011148), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_8_HASH_FUNCTION_REG                             , RULL(0x02011149), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_9_HASH_FUNCTION_REG                             , RULL(0x0201114A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ADDR_TRAP_REG                                        , RULL(0x06010003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_ADDR_TRAP_REG                                       , RULL(0x0D010003), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_ADDR_TRAP_REG                                     , RULL(0x0D010003), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_ADDR_TRAP_REG                                     , RULL(0x0E010003), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_ADDR_TRAP_REG                                     , RULL(0x0F010003), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_ADDR_TRAP_REG                                     , RULL(0x02010003), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_ADDR_TRAP_REG                                     , RULL(0x03010003), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_ADDR_TRAP_REG                                     , RULL(0x04010003), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_ADDR_TRAP_REG                                     , RULL(0x05010003), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PU_ADS_XSCOM_CMD_REG                                    , RULL(0x0009001C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_ADU_HANG_DIV_REG                                     , RULL(0x00090050), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ALTD_ADDR_REG                                        , RULL(0x00090000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_ALTD_CMD_REG                                         , RULL(0x00090001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_ALTD_DATA_REG                                        , RULL(0x00090004), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_ALTD_OPTION_REG                                      , RULL(0x00090002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_ALTD_STATUS_REG                                      , RULL(0x00090003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( CAPP_APCFG                                              , RULL(0x02010819), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_APCFG                                            , RULL(0x02010819), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_APCFG                                            , RULL(0x04010819), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_APCLCO                                             , RULL(0x02010821), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_APCLCO                                           , RULL(0x02010821), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_APCLCO                                           , RULL(0x04010821), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_APCRDFSMMASK                                       , RULL(0x02010823), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_APCRDFSMMASK                                     , RULL(0x02010823), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_APCRDFSMMASK                                     , RULL(0x04010823), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_APCTL                                              , RULL(0x02010818), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_APCTL                                            , RULL(0x02010818), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_APCTL                                            , RULL(0x04010818), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_APC_ARRY_ADDR                                      , RULL(0x0201082A), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_APC_ARRY_ADDR                                    , RULL(0x0201082A), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_APC_ARRY_ADDR                                    , RULL(0x0401082A), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_APC_ARRY_RDDATA                                    , RULL(0x0201082B), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_APC_ARRY_RDDATA                                  , RULL(0x0201082B), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_APC_ARRY_RDDATA                                  , RULL(0x0401082B), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_APC_ARRY_WRDATA                                    , RULL(0x02010842), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_APC_ARRY_WRDATA                                  , RULL(0x02010842), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_APC_ARRY_WRDATA                                  , RULL(0x04010842), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_APC_ERRINJ                                         , RULL(0x02010810), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_APC_ERRINJ                                       , RULL(0x02010810), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_APC_ERRINJ                                       , RULL(0x04010810), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_APC_PMUSEL                                         , RULL(0x02010816), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_APC_PMUSEL                                       , RULL(0x02010816), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_APC_PMUSEL                                       , RULL(0x04010816), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_ASE_TUPLE0                                         , RULL(0x02010846), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_ASE_TUPLE0                                       , RULL(0x02010846), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_ASE_TUPLE0                                       , RULL(0x04010846), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_ASE_TUPLE1                                         , RULL(0x02010847), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_ASE_TUPLE1                                       , RULL(0x02010847), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_ASE_TUPLE1                                       , RULL(0x04010847), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_ASE_TUPLE2                                         , RULL(0x02010848), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_ASE_TUPLE2                                       , RULL(0x02010848), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_ASE_TUPLE2                                       , RULL(0x04010848), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_ASE_TUPLE3                                         , RULL(0x02010849), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_ASE_TUPLE3                                       , RULL(0x02010849), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_ASE_TUPLE3                                       , RULL(0x04010849), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( PEC_ASSIST_INTERRUPT_REG                                , RULL(0x0D0F0011), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_ASSIST_INTERRUPT_REG                              , RULL(0x0D0F0011), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_ASSIST_INTERRUPT_REG                              , RULL(0x0E0F0011), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_ASSIST_INTERRUPT_REG                              , RULL(0x0F0F0011), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_ATOMIC_LOCK_MASK_LATCH_REG                           , RULL(0x06010007), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_ATOMIC_LOCK_MASK_LATCH_REG                          , RULL(0x0D010007), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_ATOMIC_LOCK_MASK_LATCH_REG                        , RULL(0x0D010007), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_ATOMIC_LOCK_MASK_LATCH_REG                        , RULL(0x0E010007), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_ATOMIC_LOCK_MASK_LATCH_REG                        , RULL(0x0F010007), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_ATOMIC_LOCK_MASK_LATCH_REG                        , RULL(0x02010007), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_ATOMIC_LOCK_MASK_LATCH_REG                        , RULL(0x03010007), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_ATOMIC_LOCK_MASK_LATCH_REG                        , RULL(0x04010007), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_ATOMIC_LOCK_MASK_LATCH_REG                        , RULL(0x05010007), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PEC_ATOMIC_LOCK_REG                                     , RULL(0x0D0F03FF), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_ATOMIC_LOCK_REG                                   , RULL(0x0D0F03FF), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_ATOMIC_LOCK_REG                                   , RULL(0x0E0F03FF), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_ATOMIC_LOCK_REG                                   , RULL(0x0F0F03FF), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( NV_ATR_HA_PTR                                           , RULL(0x050110D2), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_ATR_HA_PTR                                         , RULL(0x050110D2), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_ATR_HA_PTR                                         , RULL(0x050110F2), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_ATR_HA_PTR                                         , RULL(0x050111D2), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_ATR_HA_PTR                                         , RULL(0x050111F2), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_ATR_HA_PTR                                 , RULL(0x050112D2), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_ATR_HA_PTR                                 , RULL(0x050112F2), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM0_ATS_CKSW                                     , RULL(0x05011304), SH_UNT_PU_NPU_SM0,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU_SM1_ATS_CTRL                                     , RULL(0x05011320), SH_UNT_PU_NPU_SM1,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU_SM0_ATS_HOLD                                     , RULL(0x05011305), SH_UNT_PU_NPU_SM0,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_NPU_SM0_ATS_MASK                                     , RULL(0x05011306), SH_UNT_PU_NPU_SM0,
+       SH_ACS_SCOM_RO   );
+
+REG64( PU_NPU_SM1_ATS_TCR                                      , RULL(0x05011326), SH_UNT_PU_NPU_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PEC_ATTN_INTERRUPT_REG                                  , RULL(0x0D0F001A), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_ATTN_INTERRUPT_REG                                , RULL(0x0D0F001A), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_ATTN_INTERRUPT_REG                                , RULL(0x0E0F001A), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_ATTN_INTERRUPT_REG                                , RULL(0x0F0F001A), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_BANK0_MCD_BOT                                        , RULL(0x0301140C), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_BANK0_MCD_BOT                                   , RULL(0x0301100C), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_BANK0_MCD_CHA                                        , RULL(0x0301140D), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_BANK0_MCD_CHA                                   , RULL(0x0301100D), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_BANK0_MCD_CMD                                        , RULL(0x0301140E), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_BANK0_MCD_CMD                                   , RULL(0x0301100E), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_BANK0_MCD_REC                                        , RULL(0x03011410), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_MCD1_BANK0_MCD_REC                                   , RULL(0x03011010), SH_UNT_PU_MCD1  , SH_ACS_SCOM      );
+
+REG64( PU_BANK0_MCD_RW                                         , RULL(0x0301140F), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_MCD1_BANK0_MCD_RW                                    , RULL(0x0301100F), SH_UNT_PU_MCD1  , SH_ACS_SCOM      );
+
+REG64( PU_BANK0_MCD_STR                                        , RULL(0x0301140B), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_BANK0_MCD_STR                                   , RULL(0x0301100B), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_BANK0_MCD_TOP                                        , RULL(0x0301140A), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_BANK0_MCD_TOP                                   , RULL(0x0301100A), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_BANK0_MCD_VGC                                        , RULL(0x03011411), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_BANK0_MCD_VGC                                   , RULL(0x03011011), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+
+REG64( PEC_0_STACK0_BARE_REG                                   , RULL(0x04010C54), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK1_BARE_REG                                   , RULL(0x04010C94), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK2_BARE_REG                                   , RULL(0x04010CD4), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK0_BARE_REG                                   , RULL(0x04011054), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK1_BARE_REG                                   , RULL(0x04011094), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK2_BARE_REG                                   , RULL(0x040110D4), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK0_BARE_REG                                   , RULL(0x04011454), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK1_BARE_REG                                   , RULL(0x04011494), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK2_BARE_REG                                   , RULL(0x040114D4), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK0_BARE_REG                                     , RULL(0x04010C54), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK1_BARE_REG                                     , RULL(0x04010C94), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK2_BARE_REG                                     , RULL(0x04010CD4), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PHB_BARE_REG                                            , RULL(0x04010C54), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_0_BARE_REG                                          , RULL(0x04010C54), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_BARE_REG                                          , RULL(0x04011054), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_BARE_REG                                          , RULL(0x04011094), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_BARE_REG                                          , RULL(0x04011454), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_BARE_REG                                          , RULL(0x04011494), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_BARE_REG                                          , RULL(0x040114D4), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+
+REG64( PU_BCDE_CTL_OCI                                         , RULL(0xC0040080), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCDE_CTL_PIB                                         , RULL(0x00064010), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_BCDE_OCIBAR_OCI                                      , RULL(0xC00400A0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCDE_OCIBAR_PIB                                      , RULL(0x00064014), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_BCDE_PBADR_OCI                                       , RULL(0xC0040098), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCDE_PBADR_PIB                                       , RULL(0x00064013), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_BCDE_SET_OCI                                         , RULL(0xC0040088), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCDE_SET_PIB                                         , RULL(0x00064011), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_BCDE_STAT_OCI                                        , RULL(0xC0040090), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCDE_STAT_PIB                                        , RULL(0x00064012), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_BCUE_CTL_OCI                                         , RULL(0xC00400A8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCUE_CTL_PIB                                         , RULL(0x00064015), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_BCUE_OCIBAR_OCI                                      , RULL(0xC00400C8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCUE_OCIBAR_PIB                                      , RULL(0x00064019), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_BCUE_PBADR_OCI                                       , RULL(0xC00400C0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCUE_PBADR_PIB                                       , RULL(0x00064018), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_BCUE_SET_OCI                                         , RULL(0xC00400B0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCUE_SET_PIB                                         , RULL(0x00064016), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_BCUE_STAT_OCI                                        , RULL(0xC00400B8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_BCUE_STAT_PIB                                        , RULL(0x00064017), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_NPU_BDF2PE_00_CONFIG                                 , RULL(0x050113A0), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_BDF2PE_00_CONFIG                            , RULL(0x0501108A), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_BDF2PE_00_CONFIG                            , RULL(0x0501118A), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_BDF2PE_00_CONFIG                            , RULL(0x0501128A), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_BDF2PE_01_CONFIG                                 , RULL(0x050113A1), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_BDF2PE_01_CONFIG                            , RULL(0x0501108B), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_BDF2PE_01_CONFIG                            , RULL(0x0501118B), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_BDF2PE_01_CONFIG                            , RULL(0x0501128B), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_BDF2PE_02_CONFIG                                 , RULL(0x050113A2), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_BDF2PE_02_CONFIG                            , RULL(0x0501108C), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_BDF2PE_02_CONFIG                            , RULL(0x0501118C), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_BDF2PE_02_CONFIG                            , RULL(0x0501128C), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_BDF2PE_10_CONFIG                                 , RULL(0x050113A3), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_BDF2PE_10_CONFIG                            , RULL(0x0501108D), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_BDF2PE_10_CONFIG                            , RULL(0x0501118D), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_BDF2PE_10_CONFIG                            , RULL(0x0501128D), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_BDF2PE_11_CONFIG                                 , RULL(0x050113A4), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_BDF2PE_11_CONFIG                            , RULL(0x0501108E), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_BDF2PE_11_CONFIG                            , RULL(0x0501118E), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_BDF2PE_11_CONFIG                            , RULL(0x0501128E), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_BDF2PE_12_CONFIG                                 , RULL(0x050113A5), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_BDF2PE_12_CONFIG                            , RULL(0x0501108F), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_BDF2PE_12_CONFIG                            , RULL(0x0501118F), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_BDF2PE_12_CONFIG                            , RULL(0x0501128F), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_BDF2PE_20_CONFIG                                 , RULL(0x050113A6), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+
+REG64( PU_NPU_BDF2PE_21_CONFIG                                 , RULL(0x050113A7), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+
+REG64( PU_NPU_BDF2PE_22_CONFIG                                 , RULL(0x050113A8), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+
+REG64( PU_NPU_BDF2PE_30_CONFIG                                 , RULL(0x050113A9), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+
+REG64( PU_NPU_BDF2PE_31_CONFIG                                 , RULL(0x050113AA), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+
+REG64( PU_NPU_BDF2PE_32_CONFIG                                 , RULL(0x050113AB), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+
+REG64( PU_NPU_BDF2PE_40_CONFIG                                 , RULL(0x050113AC), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+
+REG64( PU_NPU_BDF2PE_41_CONFIG                                 , RULL(0x050113AD), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+
+REG64( PU_NPU_BDF2PE_42_CONFIG                                 , RULL(0x050113AE), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+
+REG64( PU_NPU_BDF2PE_50_CONFIG                                 , RULL(0x050113AF), SH_UNT_PU_NPU   , SH_ACS_SCOM      );
+
+REG64( PU_NPU_DAT_BDF2PE_51_CONFIG                             , RULL(0x050113B0), SH_UNT_PU_NPU_DAT,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_DAT_BDF2PE_52_CONFIG                             , RULL(0x050113B1), SH_UNT_PU_NPU_DAT,
+       SH_ACS_SCOM      );
+
+REG64( PEC_BIST                                                , RULL(0x0D03000B), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_BIST                                              , RULL(0x0D03000B), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_BIST                                              , RULL(0x0E03000B), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_BIST                                              , RULL(0x0F03000B), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL                , RULL(0x0201082C), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL              , RULL(0x0201082C), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL              , RULL(0x0401082C), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CAPP_ERR_STATUS_CONTROL                            , RULL(0x0201080E), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CAPP_ERR_STATUS_CONTROL                          , RULL(0x0201080E), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CAPP_ERR_STATUS_CONTROL                          , RULL(0x0401080E), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( PEC_CC_ATOMIC_LOCK_REG                                  , RULL(0x0D0303FF), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_CC_ATOMIC_LOCK_REG                                , RULL(0x0D0303FF), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_CC_ATOMIC_LOCK_REG                                , RULL(0x0E0303FF), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_CC_ATOMIC_LOCK_REG                                , RULL(0x0F0303FF), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_CC_PROTECT_MODE_REG                                 , RULL(0x0D0303FE), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_CC_PROTECT_MODE_REG                               , RULL(0x0D0303FE), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_CC_PROTECT_MODE_REG                               , RULL(0x0E0303FE), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_CC_PROTECT_MODE_REG                               , RULL(0x0F0303FE), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CERR_ECC_FIRST                                  , RULL(0x050110A6), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CERR_ECC_FIRST                                  , RULL(0x050111A6), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_CERR_ECC_FIRST                                  , RULL(0x050112A6), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CERR_ECC_HOLD                                   , RULL(0x050110A4), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CERR_ECC_HOLD                                   , RULL(0x050111A4), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_CERR_ECC_HOLD                                   , RULL(0x050112A4), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CERR_ECC_MASK                                   , RULL(0x050110A5), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CERR_ECC_MASK                                   , RULL(0x050111A5), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_CERR_ECC_MASK                                   , RULL(0x050112A5), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_CERR_FIRST0                                 , RULL(0x0501109A), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CERR_FIRST0                                 , RULL(0x0501119A), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CERR_FIRST0                                 , RULL(0x0501129A), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CERR_FIRST0                                 , RULL(0x05011017), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CERR_FIRST0                                 , RULL(0x05011037), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CERR_FIRST0                                 , RULL(0x05011057), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CERR_FIRST0                                 , RULL(0x05011077), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CERR_FIRST0                                 , RULL(0x05011117), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CERR_FIRST0                                 , RULL(0x05011137), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CERR_FIRST0                                 , RULL(0x05011157), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CERR_FIRST0                                 , RULL(0x05011177), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CERR_FIRST0                                 , RULL(0x05011217), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CERR_FIRST0                                 , RULL(0x05011237), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CERR_FIRST0                                 , RULL(0x05011257), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CERR_FIRST0                                 , RULL(0x05011277), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( NV_CERR_FIRST1                                          , RULL(0x050110C4), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_CERR_FIRST1                                        , RULL(0x050110C4), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_CERR_FIRST1                                        , RULL(0x050110E4), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_CERR_FIRST1                                        , RULL(0x050111C4), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_CERR_FIRST1                                        , RULL(0x050111E4), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_CERR_FIRST1                                 , RULL(0x0501109B), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CERR_FIRST1                                 , RULL(0x0501119B), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CERR_FIRST1                                 , RULL(0x0501129B), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CERR_FIRST1                                 , RULL(0x05011018), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CERR_FIRST1                                 , RULL(0x05011038), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CERR_FIRST1                                 , RULL(0x05011058), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CERR_FIRST1                                 , RULL(0x05011078), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CERR_FIRST1                                 , RULL(0x05011118), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CERR_FIRST1                                 , RULL(0x05011138), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CERR_FIRST1                                 , RULL(0x05011158), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CERR_FIRST1                                 , RULL(0x05011178), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CERR_FIRST1                                , RULL(0x050112C4), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CERR_FIRST1                                , RULL(0x050112E4), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CERR_FIRST1                                 , RULL(0x05011218), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CERR_FIRST1                                 , RULL(0x05011238), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CERR_FIRST1                                 , RULL(0x05011258), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CERR_FIRST1                                 , RULL(0x05011278), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( NV_CERR_FIRST2                                          , RULL(0x050110C8), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_CERR_FIRST2                                        , RULL(0x050110C8), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_CERR_FIRST2                                        , RULL(0x050110E8), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_CERR_FIRST2                                        , RULL(0x050111C8), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_CERR_FIRST2                                        , RULL(0x050111E8), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CERR_FIRST2                                 , RULL(0x05011019), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CERR_FIRST2                                 , RULL(0x05011039), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CERR_FIRST2                                 , RULL(0x05011059), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CERR_FIRST2                                 , RULL(0x05011079), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CERR_FIRST2                                 , RULL(0x05011119), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CERR_FIRST2                                 , RULL(0x05011139), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CERR_FIRST2                                 , RULL(0x05011159), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CERR_FIRST2                                 , RULL(0x05011179), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CERR_FIRST2                                , RULL(0x050112C8), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CERR_FIRST2                                , RULL(0x050112E8), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CERR_FIRST2                                 , RULL(0x05011219), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CERR_FIRST2                                 , RULL(0x05011239), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CERR_FIRST2                                 , RULL(0x05011259), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CERR_FIRST2                                 , RULL(0x05011279), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( NV_CERR_FIRST_MASK1                                     , RULL(0x050110C5), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_CERR_FIRST_MASK1                                   , RULL(0x050110C5), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_CERR_FIRST_MASK1                                   , RULL(0x050110E5), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_CERR_FIRST_MASK1                                   , RULL(0x050111C5), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_CERR_FIRST_MASK1                                   , RULL(0x050111E5), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CERR_FIRST_MASK1                           , RULL(0x050112C5), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CERR_FIRST_MASK1                           , RULL(0x050112E5), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( NV_CERR_FIRST_MASK2                                     , RULL(0x050110C9), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_CERR_FIRST_MASK2                                   , RULL(0x050110C9), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_CERR_FIRST_MASK2                                   , RULL(0x050110E9), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_CERR_FIRST_MASK2                                   , RULL(0x050111C9), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_CERR_FIRST_MASK2                                   , RULL(0x050111E9), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CERR_FIRST_MASK2                           , RULL(0x050112C9), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CERR_FIRST_MASK2                           , RULL(0x050112E9), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_CERR_HOLD0                                  , RULL(0x0501109E), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CERR_HOLD0                                  , RULL(0x0501119E), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CERR_HOLD0                                  , RULL(0x0501129E), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CERR_HOLD0                                  , RULL(0x0501101D), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CERR_HOLD0                                  , RULL(0x0501103D), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CERR_HOLD0                                  , RULL(0x0501105D), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CERR_HOLD0                                  , RULL(0x0501107D), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CERR_HOLD0                                  , RULL(0x0501111D), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CERR_HOLD0                                  , RULL(0x0501113D), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CERR_HOLD0                                  , RULL(0x0501115D), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CERR_HOLD0                                  , RULL(0x0501117D), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CERR_HOLD0                                  , RULL(0x0501121D), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CERR_HOLD0                                  , RULL(0x0501123D), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CERR_HOLD0                                  , RULL(0x0501125D), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CERR_HOLD0                                  , RULL(0x0501127D), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( NV_CERR_HOLD1                                           , RULL(0x050110C2), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_CERR_HOLD1                                         , RULL(0x050110C2), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_CERR_HOLD1                                         , RULL(0x050110E2), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_CERR_HOLD1                                         , RULL(0x050111C2), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_CERR_HOLD1                                         , RULL(0x050111E2), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_CERR_HOLD1                                  , RULL(0x0501109F), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CERR_HOLD1                                  , RULL(0x0501119F), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CERR_HOLD1                                  , RULL(0x0501129F), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CERR_HOLD1                                  , RULL(0x0501101E), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CERR_HOLD1                                  , RULL(0x0501103E), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CERR_HOLD1                                  , RULL(0x0501105E), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CERR_HOLD1                                  , RULL(0x0501107E), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CERR_HOLD1                                  , RULL(0x0501111E), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CERR_HOLD1                                  , RULL(0x0501113E), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CERR_HOLD1                                  , RULL(0x0501115E), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CERR_HOLD1                                  , RULL(0x0501117E), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CERR_HOLD1                                 , RULL(0x050112C2), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CERR_HOLD1                                 , RULL(0x050112E2), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CERR_HOLD1                                  , RULL(0x0501121E), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CERR_HOLD1                                  , RULL(0x0501123E), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CERR_HOLD1                                  , RULL(0x0501125E), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CERR_HOLD1                                  , RULL(0x0501127E), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( NV_CERR_HOLD2                                           , RULL(0x050110C6), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_CERR_HOLD2                                         , RULL(0x050110C6), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_CERR_HOLD2                                         , RULL(0x050110E6), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_CERR_HOLD2                                         , RULL(0x050111C6), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_CERR_HOLD2                                         , RULL(0x050111E6), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CERR_HOLD2                                  , RULL(0x0501101F), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CERR_HOLD2                                  , RULL(0x0501103F), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CERR_HOLD2                                  , RULL(0x0501105F), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CERR_HOLD2                                  , RULL(0x0501107F), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CERR_HOLD2                                  , RULL(0x0501111F), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CERR_HOLD2                                  , RULL(0x0501113F), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CERR_HOLD2                                  , RULL(0x0501115F), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CERR_HOLD2                                  , RULL(0x0501117F), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CERR_HOLD2                                 , RULL(0x050112C6), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CERR_HOLD2                                 , RULL(0x050112E6), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CERR_HOLD2                                  , RULL(0x0501121F), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CERR_HOLD2                                  , RULL(0x0501123F), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CERR_HOLD2                                  , RULL(0x0501125F), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CERR_HOLD2                                  , RULL(0x0501127F), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CERR_LOG_FIRST                                  , RULL(0x050110AC), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CERR_LOG_FIRST                                  , RULL(0x050111AC), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_CERR_LOG_FIRST                                  , RULL(0x050112AC), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CERR_LOG_HOLD                                   , RULL(0x050110AA), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CERR_LOG_HOLD                                   , RULL(0x050111AA), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_CERR_LOG_HOLD                                   , RULL(0x050112AA), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CERR_LOG_MASK                                   , RULL(0x050110AB), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CERR_LOG_MASK                                   , RULL(0x050111AB), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_CERR_LOG_MASK                                   , RULL(0x050112AB), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_CERR_MASK0                                  , RULL(0x0501109C), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CERR_MASK0                                  , RULL(0x0501119C), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CERR_MASK0                                  , RULL(0x0501129C), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CERR_MASK0                                  , RULL(0x0501101A), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CERR_MASK0                                  , RULL(0x0501103A), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CERR_MASK0                                  , RULL(0x0501105A), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CERR_MASK0                                  , RULL(0x0501107A), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CERR_MASK0                                  , RULL(0x0501111A), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CERR_MASK0                                  , RULL(0x0501113A), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CERR_MASK0                                  , RULL(0x0501115A), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CERR_MASK0                                  , RULL(0x0501117A), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CERR_MASK0                                  , RULL(0x0501121A), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CERR_MASK0                                  , RULL(0x0501123A), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CERR_MASK0                                  , RULL(0x0501125A), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CERR_MASK0                                  , RULL(0x0501127A), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( NV_CERR_MASK1                                           , RULL(0x050110C3), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_CERR_MASK1                                         , RULL(0x050110C3), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_CERR_MASK1                                         , RULL(0x050110E3), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_CERR_MASK1                                         , RULL(0x050111C3), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_CERR_MASK1                                         , RULL(0x050111E3), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_CERR_MASK1                                  , RULL(0x0501109D), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CERR_MASK1                                  , RULL(0x0501119D), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CERR_MASK1                                  , RULL(0x0501129D), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CERR_MASK1                                  , RULL(0x0501101B), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CERR_MASK1                                  , RULL(0x0501103B), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CERR_MASK1                                  , RULL(0x0501105B), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CERR_MASK1                                  , RULL(0x0501107B), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CERR_MASK1                                  , RULL(0x0501111B), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CERR_MASK1                                  , RULL(0x0501113B), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CERR_MASK1                                  , RULL(0x0501115B), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CERR_MASK1                                  , RULL(0x0501117B), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CERR_MASK1                                 , RULL(0x050112C3), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CERR_MASK1                                 , RULL(0x050112E3), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CERR_MASK1                                  , RULL(0x0501121B), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CERR_MASK1                                  , RULL(0x0501123B), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CERR_MASK1                                  , RULL(0x0501125B), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CERR_MASK1                                  , RULL(0x0501127B), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( NV_CERR_MASK2                                           , RULL(0x050110C7), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_CERR_MASK2                                         , RULL(0x050110C7), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_CERR_MASK2                                         , RULL(0x050110E7), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_CERR_MASK2                                         , RULL(0x050111C7), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_CERR_MASK2                                         , RULL(0x050111E7), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CERR_MASK2                                  , RULL(0x0501101C), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CERR_MASK2                                  , RULL(0x0501103C), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CERR_MASK2                                  , RULL(0x0501105C), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CERR_MASK2                                  , RULL(0x0501107C), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CERR_MASK2                                  , RULL(0x0501111C), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CERR_MASK2                                  , RULL(0x0501113C), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CERR_MASK2                                  , RULL(0x0501115C), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CERR_MASK2                                  , RULL(0x0501117C), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CERR_MASK2                                 , RULL(0x050112C7), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CERR_MASK2                                 , RULL(0x050112E7), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CERR_MASK2                                  , RULL(0x0501121C), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CERR_MASK2                                  , RULL(0x0501123C), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CERR_MASK2                                  , RULL(0x0501125C), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CERR_MASK2                                  , RULL(0x0501127C), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_CERR_MESSAGE0                               , RULL(0x05011098), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CERR_MESSAGE0                               , RULL(0x05011198), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CERR_MESSAGE0                               , RULL(0x05011298), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CERR_MESSAGE0                               , RULL(0x05011011), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CERR_MESSAGE0                               , RULL(0x05011031), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CERR_MESSAGE0                               , RULL(0x05011051), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CERR_MESSAGE0                               , RULL(0x05011071), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CERR_MESSAGE0                               , RULL(0x05011111), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CERR_MESSAGE0                               , RULL(0x05011131), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CERR_MESSAGE0                               , RULL(0x05011151), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CERR_MESSAGE0                               , RULL(0x05011171), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CERR_MESSAGE0                               , RULL(0x05011211), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CERR_MESSAGE0                               , RULL(0x05011231), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CERR_MESSAGE0                               , RULL(0x05011251), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CERR_MESSAGE0                               , RULL(0x05011271), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_CERR_MESSAGE1                               , RULL(0x05011099), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CERR_MESSAGE1                               , RULL(0x05011199), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CERR_MESSAGE1                               , RULL(0x05011299), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CERR_MESSAGE1                               , RULL(0x05011012), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CERR_MESSAGE1                               , RULL(0x05011032), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CERR_MESSAGE1                               , RULL(0x05011052), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CERR_MESSAGE1                               , RULL(0x05011072), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CERR_MESSAGE1                               , RULL(0x05011112), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CERR_MESSAGE1                               , RULL(0x05011132), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CERR_MESSAGE1                               , RULL(0x05011152), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CERR_MESSAGE1                               , RULL(0x05011172), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CERR_MESSAGE1                               , RULL(0x05011212), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CERR_MESSAGE1                               , RULL(0x05011232), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CERR_MESSAGE1                               , RULL(0x05011252), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CERR_MESSAGE1                               , RULL(0x05011272), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_CERR_MESSAGE2                               , RULL(0x05011013), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CERR_MESSAGE2                               , RULL(0x05011033), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CERR_MESSAGE2                               , RULL(0x05011053), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CERR_MESSAGE2                               , RULL(0x05011073), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CERR_MESSAGE2                               , RULL(0x05011113), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CERR_MESSAGE2                               , RULL(0x05011133), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CERR_MESSAGE2                               , RULL(0x05011153), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CERR_MESSAGE2                               , RULL(0x05011173), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CERR_MESSAGE2                               , RULL(0x05011213), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CERR_MESSAGE2                               , RULL(0x05011233), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CERR_MESSAGE2                               , RULL(0x05011253), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CERR_MESSAGE2                               , RULL(0x05011273), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_CERR_MESSAGE3                               , RULL(0x05011014), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CERR_MESSAGE3                               , RULL(0x05011034), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CERR_MESSAGE3                               , RULL(0x05011054), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CERR_MESSAGE3                               , RULL(0x05011074), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CERR_MESSAGE3                               , RULL(0x05011114), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CERR_MESSAGE3                               , RULL(0x05011134), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CERR_MESSAGE3                               , RULL(0x05011154), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CERR_MESSAGE3                               , RULL(0x05011174), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CERR_MESSAGE3                               , RULL(0x05011214), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CERR_MESSAGE3                               , RULL(0x05011234), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CERR_MESSAGE3                               , RULL(0x05011254), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CERR_MESSAGE3                               , RULL(0x05011274), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_CERR_MESSAGE4                               , RULL(0x05011015), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CERR_MESSAGE4                               , RULL(0x05011035), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CERR_MESSAGE4                               , RULL(0x05011055), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CERR_MESSAGE4                               , RULL(0x05011075), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CERR_MESSAGE4                               , RULL(0x05011115), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CERR_MESSAGE4                               , RULL(0x05011135), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CERR_MESSAGE4                               , RULL(0x05011155), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CERR_MESSAGE4                               , RULL(0x05011175), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CERR_MESSAGE4                               , RULL(0x05011215), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CERR_MESSAGE4                               , RULL(0x05011235), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CERR_MESSAGE4                               , RULL(0x05011255), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CERR_MESSAGE4                               , RULL(0x05011275), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CERR_PTY_FIRST                                  , RULL(0x050110A9), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CERR_PTY_FIRST                                  , RULL(0x050111A9), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_CERR_PTY_FIRST                                  , RULL(0x050112A9), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CERR_PTY_HOLD                                   , RULL(0x050110A7), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CERR_PTY_HOLD                                   , RULL(0x050111A7), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_CERR_PTY_HOLD                                   , RULL(0x050112A7), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CERR_PTY_MASK                                   , RULL(0x050110A8), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CERR_PTY_MASK                                   , RULL(0x050111A8), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_CERR_PTY_MASK                                   , RULL(0x050112A8), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PEC_0_STACK0_CERR_RPT0_REG                              , RULL(0x04010C4A), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_0_STACK1_CERR_RPT0_REG                              , RULL(0x04010C8A), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_0_STACK2_CERR_RPT0_REG                              , RULL(0x04010CCA), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK0_CERR_RPT0_REG                              , RULL(0x0401104A), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK1_CERR_RPT0_REG                              , RULL(0x0401108A), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK2_CERR_RPT0_REG                              , RULL(0x040110CA), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK0_CERR_RPT0_REG                              , RULL(0x0401144A), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK1_CERR_RPT0_REG                              , RULL(0x0401148A), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK2_CERR_RPT0_REG                              , RULL(0x040114CA), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_STACK0_CERR_RPT0_REG                                , RULL(0x04010C4A), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_STACK1_CERR_RPT0_REG                                , RULL(0x04010C8A), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_STACK2_CERR_RPT0_REG                                , RULL(0x04010CCA), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM_RO   );
+REG64( PHB_CERR_RPT0_REG                                       , RULL(0x04010C4A), SH_UNT_PHB      , SH_ACS_SCOM_RO   );
+REG64( PHB_0_CERR_RPT0_REG                                     , RULL(0x04010C4A), SH_UNT_PHB_0    , SH_ACS_SCOM_RO   );
+REG64( PHB_1_CERR_RPT0_REG                                     , RULL(0x0401104A), SH_UNT_PHB_1    , SH_ACS_SCOM_RO   );
+REG64( PHB_2_CERR_RPT0_REG                                     , RULL(0x0401108A), SH_UNT_PHB_2    , SH_ACS_SCOM_RO   );
+REG64( PHB_3_CERR_RPT0_REG                                     , RULL(0x0401144A), SH_UNT_PHB_3    , SH_ACS_SCOM_RO   );
+REG64( PHB_4_CERR_RPT0_REG                                     , RULL(0x0401148A), SH_UNT_PHB_4    , SH_ACS_SCOM_RO   );
+REG64( PHB_5_CERR_RPT0_REG                                     , RULL(0x040114CA), SH_UNT_PHB_5    , SH_ACS_SCOM_RO   );
+
+REG64( PEC_0_STACK0_CERR_RPT1_REG                              , RULL(0x04010C4B), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_0_STACK1_CERR_RPT1_REG                              , RULL(0x04010C8B), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_0_STACK2_CERR_RPT1_REG                              , RULL(0x04010CCB), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK0_CERR_RPT1_REG                              , RULL(0x0401104B), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK1_CERR_RPT1_REG                              , RULL(0x0401108B), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK2_CERR_RPT1_REG                              , RULL(0x040110CB), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK0_CERR_RPT1_REG                              , RULL(0x0401144B), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK1_CERR_RPT1_REG                              , RULL(0x0401148B), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK2_CERR_RPT1_REG                              , RULL(0x040114CB), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_STACK0_CERR_RPT1_REG                                , RULL(0x04010C4B), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_STACK1_CERR_RPT1_REG                                , RULL(0x04010C8B), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_STACK2_CERR_RPT1_REG                                , RULL(0x04010CCB), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM_RO   );
+REG64( PHB_CERR_RPT1_REG                                       , RULL(0x04010C4B), SH_UNT_PHB      , SH_ACS_SCOM_RO   );
+REG64( PHB_0_CERR_RPT1_REG                                     , RULL(0x04010C4B), SH_UNT_PHB_0    , SH_ACS_SCOM_RO   );
+REG64( PHB_1_CERR_RPT1_REG                                     , RULL(0x0401104B), SH_UNT_PHB_1    , SH_ACS_SCOM_RO   );
+REG64( PHB_2_CERR_RPT1_REG                                     , RULL(0x0401108B), SH_UNT_PHB_2    , SH_ACS_SCOM_RO   );
+REG64( PHB_3_CERR_RPT1_REG                                     , RULL(0x0401144B), SH_UNT_PHB_3    , SH_ACS_SCOM_RO   );
+REG64( PHB_4_CERR_RPT1_REG                                     , RULL(0x0401148B), SH_UNT_PHB_4    , SH_ACS_SCOM_RO   );
+REG64( PHB_5_CERR_RPT1_REG                                     , RULL(0x040114CB), SH_UNT_PHB_5    , SH_ACS_SCOM_RO   );
+
+REG64( PEC_CLK_REGION                                          , RULL(0x0D030006), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_CLK_REGION                                        , RULL(0x0D030006), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_CLK_REGION                                        , RULL(0x0E030006), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_CLK_REGION                                        , RULL(0x0F030006), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_CLOCK_STAT_ARY                                      , RULL(0x0D03000A), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_CLOCK_STAT_ARY                                    , RULL(0x0D03000A), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_CLOCK_STAT_ARY                                    , RULL(0x0E03000A), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_CLOCK_STAT_ARY                                    , RULL(0x0F03000A), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_CLOCK_STAT_NSL                                      , RULL(0x0D030009), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_CLOCK_STAT_NSL                                    , RULL(0x0D030009), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_CLOCK_STAT_NSL                                    , RULL(0x0E030009), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_CLOCK_STAT_NSL                                    , RULL(0x0F030009), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_CLOCK_STAT_SL                                       , RULL(0x0D030008), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_CLOCK_STAT_SL                                     , RULL(0x0D030008), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_CLOCK_STAT_SL                                     , RULL(0x0E030008), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_CLOCK_STAT_SL                                     , RULL(0x0F030008), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_CME0_CME_LCL_DBG_PPE                                 , RULL(0x109010120), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME0_CME_LCL_DBG_PPE1                                , RULL(0x109010138), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME0_CME_LCL_DBG_PPE2                                , RULL(0x109010130), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME1_CME_LCL_DBG_PPE                                 , RULL(0x109020120), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_DBG_PPE1                                , RULL(0x109020138), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME1_CME_LCL_DBG_PPE2                                , RULL(0x109020130), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME2_CME_LCL_DBG_PPE                                 , RULL(0x10A010120), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_DBG_PPE1                                , RULL(0x10A010138), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME2_CME_LCL_DBG_PPE2                                , RULL(0x10A010130), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME3_CME_LCL_DBG_PPE                                 , RULL(0x10A020120), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_DBG_PPE1                                , RULL(0x10A020138), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME3_CME_LCL_DBG_PPE2                                , RULL(0x10A020130), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME4_CME_LCL_DBG_PPE                                 , RULL(0x10B010120), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_DBG_PPE1                                , RULL(0x10B010138), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME4_CME_LCL_DBG_PPE2                                , RULL(0x10B010130), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME5_CME_LCL_DBG_PPE                                 , RULL(0x10B020120), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_DBG_PPE1                                , RULL(0x10B020138), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME5_CME_LCL_DBG_PPE2                                , RULL(0x10B020130), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME6_CME_LCL_DBG_PPE                                 , RULL(0x10C010120), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_DBG_PPE1                                , RULL(0x10C010138), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME6_CME_LCL_DBG_PPE2                                , RULL(0x10C010130), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME7_CME_LCL_DBG_PPE                                 , RULL(0x10C020120), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_DBG_PPE1                                , RULL(0x10C020138), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME7_CME_LCL_DBG_PPE2                                , RULL(0x10C020130), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME8_CME_LCL_DBG_PPE                                 , RULL(0x10D010120), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_DBG_PPE1                                , RULL(0x10D010138), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME8_CME_LCL_DBG_PPE2                                , RULL(0x10D010130), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME9_CME_LCL_DBG_PPE                                 , RULL(0x10D020120), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_DBG_PPE1                                , RULL(0x10D020138), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME9_CME_LCL_DBG_PPE2                                , RULL(0x10D020130), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME10_CME_LCL_DBG_PPE                                , RULL(0x10E010120), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_DBG_PPE1                               , RULL(0x10E010138), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME10_CME_LCL_DBG_PPE2                               , RULL(0x10E010130), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE2      );
+REG64( PU_CME11_CME_LCL_DBG_PPE                                , RULL(0x10E020120), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_DBG_PPE1                               , RULL(0x10E020138), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME11_CME_LCL_DBG_PPE2                               , RULL(0x10E020130), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_LCL_EIMR_PPE                                , RULL(0x109010020), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME0_CME_LCL_EIMR_PPE1                               , RULL(0x109010038), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME0_CME_LCL_EIMR_PPE2                               , RULL(0x109010030), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME1_CME_LCL_EIMR_PPE                                , RULL(0x109020020), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_EIMR_PPE1                               , RULL(0x109020038), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME1_CME_LCL_EIMR_PPE2                               , RULL(0x109020030), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME2_CME_LCL_EIMR_PPE                                , RULL(0x10A010020), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_EIMR_PPE1                               , RULL(0x10A010038), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME2_CME_LCL_EIMR_PPE2                               , RULL(0x10A010030), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME3_CME_LCL_EIMR_PPE                                , RULL(0x10A020020), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_EIMR_PPE1                               , RULL(0x10A020038), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME3_CME_LCL_EIMR_PPE2                               , RULL(0x10A020030), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME4_CME_LCL_EIMR_PPE                                , RULL(0x10B010020), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_EIMR_PPE1                               , RULL(0x10B010038), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME4_CME_LCL_EIMR_PPE2                               , RULL(0x10B010030), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME5_CME_LCL_EIMR_PPE                                , RULL(0x10B020020), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_EIMR_PPE1                               , RULL(0x10B020038), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME5_CME_LCL_EIMR_PPE2                               , RULL(0x10B020030), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME6_CME_LCL_EIMR_PPE                                , RULL(0x10C010020), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_EIMR_PPE1                               , RULL(0x10C010038), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME6_CME_LCL_EIMR_PPE2                               , RULL(0x10C010030), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME7_CME_LCL_EIMR_PPE                                , RULL(0x10C020020), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_EIMR_PPE1                               , RULL(0x10C020038), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME7_CME_LCL_EIMR_PPE2                               , RULL(0x10C020030), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME8_CME_LCL_EIMR_PPE                                , RULL(0x10D010020), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_EIMR_PPE1                               , RULL(0x10D010038), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME8_CME_LCL_EIMR_PPE2                               , RULL(0x10D010030), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME9_CME_LCL_EIMR_PPE                                , RULL(0x10D020020), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_EIMR_PPE1                               , RULL(0x10D020038), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME9_CME_LCL_EIMR_PPE2                               , RULL(0x10D020030), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME10_CME_LCL_EIMR_PPE                               , RULL(0x10E010020), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_EIMR_PPE1                              , RULL(0x10E010038), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME10_CME_LCL_EIMR_PPE2                              , RULL(0x10E010030), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE2      );
+REG64( PU_CME11_CME_LCL_EIMR_PPE                               , RULL(0x10E020020), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_EIMR_PPE1                              , RULL(0x10E020038), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME11_CME_LCL_EIMR_PPE2                              , RULL(0x10E020030), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_LCL_EINR_PPE                                , RULL(0x1090100A0), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_EINR_PPE                                , RULL(0x1090200A0), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_EINR_PPE                                , RULL(0x10A0100A0), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_EINR_PPE                                , RULL(0x10A0200A0), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_EINR_PPE                                , RULL(0x10B0100A0), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_EINR_PPE                                , RULL(0x10B0200A0), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_EINR_PPE                                , RULL(0x10C0100A0), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_EINR_PPE                                , RULL(0x10C0200A0), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_EINR_PPE                                , RULL(0x10D0100A0), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_EINR_PPE                                , RULL(0x10D0200A0), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_EINR_PPE                               , RULL(0x10E0100A0), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_EINR_PPE                               , RULL(0x10E0200A0), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_EIPR_PPE                                , RULL(0x109010040), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME0_CME_LCL_EIPR_PPE1                               , RULL(0x109010058), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME0_CME_LCL_EIPR_PPE2                               , RULL(0x109010050), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME1_CME_LCL_EIPR_PPE                                , RULL(0x109020040), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_EIPR_PPE1                               , RULL(0x109020058), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME1_CME_LCL_EIPR_PPE2                               , RULL(0x109020050), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME2_CME_LCL_EIPR_PPE                                , RULL(0x10A010040), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_EIPR_PPE1                               , RULL(0x10A010058), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME2_CME_LCL_EIPR_PPE2                               , RULL(0x10A010050), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME3_CME_LCL_EIPR_PPE                                , RULL(0x10A020040), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_EIPR_PPE1                               , RULL(0x10A020058), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME3_CME_LCL_EIPR_PPE2                               , RULL(0x10A020050), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME4_CME_LCL_EIPR_PPE                                , RULL(0x10B010040), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_EIPR_PPE1                               , RULL(0x10B010058), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME4_CME_LCL_EIPR_PPE2                               , RULL(0x10B010050), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME5_CME_LCL_EIPR_PPE                                , RULL(0x10B020040), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_EIPR_PPE1                               , RULL(0x10B020058), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME5_CME_LCL_EIPR_PPE2                               , RULL(0x10B020050), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME6_CME_LCL_EIPR_PPE                                , RULL(0x10C010040), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_EIPR_PPE1                               , RULL(0x10C010058), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME6_CME_LCL_EIPR_PPE2                               , RULL(0x10C010050), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME7_CME_LCL_EIPR_PPE                                , RULL(0x10C020040), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_EIPR_PPE1                               , RULL(0x10C020058), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME7_CME_LCL_EIPR_PPE2                               , RULL(0x10C020050), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME8_CME_LCL_EIPR_PPE                                , RULL(0x10D010040), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_EIPR_PPE1                               , RULL(0x10D010058), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME8_CME_LCL_EIPR_PPE2                               , RULL(0x10D010050), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME9_CME_LCL_EIPR_PPE                                , RULL(0x10D020040), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_EIPR_PPE1                               , RULL(0x10D020058), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME9_CME_LCL_EIPR_PPE2                               , RULL(0x10D020050), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME10_CME_LCL_EIPR_PPE                               , RULL(0x10E010040), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_EIPR_PPE1                              , RULL(0x10E010058), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME10_CME_LCL_EIPR_PPE2                              , RULL(0x10E010050), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE2      );
+REG64( PU_CME11_CME_LCL_EIPR_PPE                               , RULL(0x10E020040), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_EIPR_PPE1                              , RULL(0x10E020058), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME11_CME_LCL_EIPR_PPE2                              , RULL(0x10E020050), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_LCL_EISR_PPE                                , RULL(0x109010000), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME0_CME_LCL_EISR_PPE1                               , RULL(0x109010018), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME0_CME_LCL_EISR_PPE2                               , RULL(0x109010010), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME1_CME_LCL_EISR_PPE                                , RULL(0x109020000), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_EISR_PPE1                               , RULL(0x109020018), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME1_CME_LCL_EISR_PPE2                               , RULL(0x109020010), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME2_CME_LCL_EISR_PPE                                , RULL(0x10A010000), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_EISR_PPE1                               , RULL(0x10A010018), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME2_CME_LCL_EISR_PPE2                               , RULL(0x10A010010), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME3_CME_LCL_EISR_PPE                                , RULL(0x10A020000), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_EISR_PPE1                               , RULL(0x10A020018), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME3_CME_LCL_EISR_PPE2                               , RULL(0x10A020010), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME4_CME_LCL_EISR_PPE                                , RULL(0x10B010000), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_EISR_PPE1                               , RULL(0x10B010018), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME4_CME_LCL_EISR_PPE2                               , RULL(0x10B010010), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME5_CME_LCL_EISR_PPE                                , RULL(0x10B020000), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_EISR_PPE1                               , RULL(0x10B020018), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME5_CME_LCL_EISR_PPE2                               , RULL(0x10B020010), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME6_CME_LCL_EISR_PPE                                , RULL(0x10C010000), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_EISR_PPE1                               , RULL(0x10C010018), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME6_CME_LCL_EISR_PPE2                               , RULL(0x10C010010), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME7_CME_LCL_EISR_PPE                                , RULL(0x10C020000), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_EISR_PPE1                               , RULL(0x10C020018), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME7_CME_LCL_EISR_PPE2                               , RULL(0x10C020010), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME8_CME_LCL_EISR_PPE                                , RULL(0x10D010000), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_EISR_PPE1                               , RULL(0x10D010018), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME8_CME_LCL_EISR_PPE2                               , RULL(0x10D010010), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME9_CME_LCL_EISR_PPE                                , RULL(0x10D020000), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_EISR_PPE1                               , RULL(0x10D020018), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME9_CME_LCL_EISR_PPE2                               , RULL(0x10D020010), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME10_CME_LCL_EISR_PPE                               , RULL(0x10E010000), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_EISR_PPE1                              , RULL(0x10E010018), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME10_CME_LCL_EISR_PPE2                              , RULL(0x10E010010), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE2      );
+REG64( PU_CME11_CME_LCL_EISR_PPE                               , RULL(0x10E020000), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_EISR_PPE1                              , RULL(0x10E020018), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME11_CME_LCL_EISR_PPE2                              , RULL(0x10E020010), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_LCL_EISTR_PPE                               , RULL(0x109010080), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_EISTR_PPE                               , RULL(0x109020080), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_EISTR_PPE                               , RULL(0x10A010080), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_EISTR_PPE                               , RULL(0x10A020080), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_EISTR_PPE                               , RULL(0x10B010080), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_EISTR_PPE                               , RULL(0x10B020080), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_EISTR_PPE                               , RULL(0x10C010080), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_EISTR_PPE                               , RULL(0x10C020080), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_EISTR_PPE                               , RULL(0x10D010080), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_EISTR_PPE                               , RULL(0x10D020080), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_EISTR_PPE                              , RULL(0x10E010080), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_EISTR_PPE                              , RULL(0x10E020080), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_EITR_PPE                                , RULL(0x109010060), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME0_CME_LCL_EITR_PPE1                               , RULL(0x109010078), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME0_CME_LCL_EITR_PPE2                               , RULL(0x109010070), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME1_CME_LCL_EITR_PPE                                , RULL(0x109020060), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_EITR_PPE1                               , RULL(0x109020078), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME1_CME_LCL_EITR_PPE2                               , RULL(0x109020070), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME2_CME_LCL_EITR_PPE                                , RULL(0x10A010060), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_EITR_PPE1                               , RULL(0x10A010078), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME2_CME_LCL_EITR_PPE2                               , RULL(0x10A010070), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME3_CME_LCL_EITR_PPE                                , RULL(0x10A020060), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_EITR_PPE1                               , RULL(0x10A020078), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME3_CME_LCL_EITR_PPE2                               , RULL(0x10A020070), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME4_CME_LCL_EITR_PPE                                , RULL(0x10B010060), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_EITR_PPE1                               , RULL(0x10B010078), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME4_CME_LCL_EITR_PPE2                               , RULL(0x10B010070), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME5_CME_LCL_EITR_PPE                                , RULL(0x10B020060), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_EITR_PPE1                               , RULL(0x10B020078), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME5_CME_LCL_EITR_PPE2                               , RULL(0x10B020070), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME6_CME_LCL_EITR_PPE                                , RULL(0x10C010060), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_EITR_PPE1                               , RULL(0x10C010078), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME6_CME_LCL_EITR_PPE2                               , RULL(0x10C010070), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME7_CME_LCL_EITR_PPE                                , RULL(0x10C020060), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_EITR_PPE1                               , RULL(0x10C020078), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME7_CME_LCL_EITR_PPE2                               , RULL(0x10C020070), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME8_CME_LCL_EITR_PPE                                , RULL(0x10D010060), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_EITR_PPE1                               , RULL(0x10D010078), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME8_CME_LCL_EITR_PPE2                               , RULL(0x10D010070), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME9_CME_LCL_EITR_PPE                                , RULL(0x10D020060), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_EITR_PPE1                               , RULL(0x10D020078), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME9_CME_LCL_EITR_PPE2                               , RULL(0x10D020070), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME10_CME_LCL_EITR_PPE                               , RULL(0x10E010060), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_EITR_PPE1                              , RULL(0x10E010078), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME10_CME_LCL_EITR_PPE2                              , RULL(0x10E010070), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE2      );
+REG64( PU_CME11_CME_LCL_EITR_PPE                               , RULL(0x10E020060), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_EITR_PPE1                              , RULL(0x10E020078), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME11_CME_LCL_EITR_PPE2                              , RULL(0x10E020070), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_LCL_ICCR_PPE                                , RULL(0x109010700), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME0_CME_LCL_ICCR_PPE1                               , RULL(0x109010718), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME0_CME_LCL_ICCR_PPE2                               , RULL(0x109010710), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME1_CME_LCL_ICCR_PPE                                , RULL(0x109020700), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_ICCR_PPE1                               , RULL(0x109020718), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME1_CME_LCL_ICCR_PPE2                               , RULL(0x109020710), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME2_CME_LCL_ICCR_PPE                                , RULL(0x10A010700), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_ICCR_PPE1                               , RULL(0x10A010718), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME2_CME_LCL_ICCR_PPE2                               , RULL(0x10A010710), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME3_CME_LCL_ICCR_PPE                                , RULL(0x10A020700), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_ICCR_PPE1                               , RULL(0x10A020718), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME3_CME_LCL_ICCR_PPE2                               , RULL(0x10A020710), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME4_CME_LCL_ICCR_PPE                                , RULL(0x10B010700), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_ICCR_PPE1                               , RULL(0x10B010718), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME4_CME_LCL_ICCR_PPE2                               , RULL(0x10B010710), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME5_CME_LCL_ICCR_PPE                                , RULL(0x10B020700), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_ICCR_PPE1                               , RULL(0x10B020718), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME5_CME_LCL_ICCR_PPE2                               , RULL(0x10B020710), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME6_CME_LCL_ICCR_PPE                                , RULL(0x10C010700), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_ICCR_PPE1                               , RULL(0x10C010718), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME6_CME_LCL_ICCR_PPE2                               , RULL(0x10C010710), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME7_CME_LCL_ICCR_PPE                                , RULL(0x10C020700), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_ICCR_PPE1                               , RULL(0x10C020718), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME7_CME_LCL_ICCR_PPE2                               , RULL(0x10C020710), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME8_CME_LCL_ICCR_PPE                                , RULL(0x10D010700), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_ICCR_PPE1                               , RULL(0x10D010718), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME8_CME_LCL_ICCR_PPE2                               , RULL(0x10D010710), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME9_CME_LCL_ICCR_PPE                                , RULL(0x10D020700), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_ICCR_PPE1                               , RULL(0x10D020718), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME9_CME_LCL_ICCR_PPE2                               , RULL(0x10D020710), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME10_CME_LCL_ICCR_PPE                               , RULL(0x10E010700), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_ICCR_PPE1                              , RULL(0x10E010718), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME10_CME_LCL_ICCR_PPE2                              , RULL(0x10E010710), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE2      );
+REG64( PU_CME11_CME_LCL_ICCR_PPE                               , RULL(0x10E020700), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_ICCR_PPE1                              , RULL(0x10E020718), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME11_CME_LCL_ICCR_PPE2                              , RULL(0x10E020710), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_LCL_ICRR_PPE                                , RULL(0x109010740), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_ICRR_PPE                                , RULL(0x109020740), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_ICRR_PPE                                , RULL(0x10A010740), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_ICRR_PPE                                , RULL(0x10A020740), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_ICRR_PPE                                , RULL(0x10B010740), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_ICRR_PPE                                , RULL(0x10B020740), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_ICRR_PPE                                , RULL(0x10C010740), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_ICRR_PPE                                , RULL(0x10C020740), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_ICRR_PPE                                , RULL(0x10D010740), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_ICRR_PPE                                , RULL(0x10D020740), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_ICRR_PPE                               , RULL(0x10E010740), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_ICRR_PPE                               , RULL(0x10E020740), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_ICSR_PPE                                , RULL(0x109010720), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_ICSR_PPE                                , RULL(0x109020720), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_ICSR_PPE                                , RULL(0x10A010720), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_ICSR_PPE                                , RULL(0x10A020720), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_ICSR_PPE                                , RULL(0x10B010720), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_ICSR_PPE                                , RULL(0x10B020720), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_ICSR_PPE                                , RULL(0x10C010720), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_ICSR_PPE                                , RULL(0x10C020720), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_ICSR_PPE                                , RULL(0x10D010720), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_ICSR_PPE                                , RULL(0x10D020720), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_ICSR_PPE                               , RULL(0x10E010720), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_ICSR_PPE                               , RULL(0x10E020720), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_LMCR_PPE                                , RULL(0x1090101A0), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_LMCR_PPE                                , RULL(0x1090201A0), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_LMCR_PPE                                , RULL(0x10A0101A0), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_LMCR_PPE                                , RULL(0x10A0201A0), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_LMCR_PPE                                , RULL(0x10B0101A0), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_LMCR_PPE                                , RULL(0x10B0201A0), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_LMCR_PPE                                , RULL(0x10C0101A0), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_LMCR_PPE                                , RULL(0x10C0201A0), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_LMCR_PPE                                , RULL(0x10D0101A0), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_LMCR_PPE                                , RULL(0x10D0201A0), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_LMCR_PPE                               , RULL(0x10E0101A0), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_LMCR_PPE                               , RULL(0x10E0201A0), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_PECESR0_PPE                             , RULL(0x109010280), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_PECESR0_PPE                             , RULL(0x109020280), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_PECESR0_PPE                             , RULL(0x10A010280), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_PECESR0_PPE                             , RULL(0x10A020280), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_PECESR0_PPE                             , RULL(0x10B010280), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_PECESR0_PPE                             , RULL(0x10B020280), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_PECESR0_PPE                             , RULL(0x10C010280), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_PECESR0_PPE                             , RULL(0x10C020280), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_PECESR0_PPE                             , RULL(0x10D010280), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_PECESR0_PPE                             , RULL(0x10D020280), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_PECESR0_PPE                            , RULL(0x10E010280), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_PECESR0_PPE                            , RULL(0x10E020280), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_PECESR1_PPE                             , RULL(0x1090102A0), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_PECESR1_PPE                             , RULL(0x1090202A0), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_PECESR1_PPE                             , RULL(0x10A0102A0), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_PECESR1_PPE                             , RULL(0x10A0202A0), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_PECESR1_PPE                             , RULL(0x10B0102A0), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_PECESR1_PPE                             , RULL(0x10B0202A0), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_PECESR1_PPE                             , RULL(0x10C0102A0), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_PECESR1_PPE                             , RULL(0x10C0202A0), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_PECESR1_PPE                             , RULL(0x10D0102A0), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_PECESR1_PPE                             , RULL(0x10D0202A0), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_PECESR1_PPE                            , RULL(0x10E0102A0), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_PECESR1_PPE                            , RULL(0x10E0202A0), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_SISR_PPE                                , RULL(0x109010520), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_SISR_PPE                                , RULL(0x109020520), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_SISR_PPE                                , RULL(0x10A010520), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_SISR_PPE                                , RULL(0x10A020520), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_SISR_PPE                                , RULL(0x10B010520), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_SISR_PPE                                , RULL(0x10B020520), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_SISR_PPE                                , RULL(0x10C010520), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_SISR_PPE                                , RULL(0x10C020520), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_SISR_PPE                                , RULL(0x10D010520), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_SISR_PPE                                , RULL(0x10D020520), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_SISR_PPE                               , RULL(0x10E010520), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_SISR_PPE                               , RULL(0x10E020520), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_LCL_TSEL_PPE                                , RULL(0x109010100), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_LCL_TSEL_PPE                                , RULL(0x109020100), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_LCL_TSEL_PPE                                , RULL(0x10A010100), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_LCL_TSEL_PPE                                , RULL(0x10A020100), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_LCL_TSEL_PPE                                , RULL(0x10B010100), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_LCL_TSEL_PPE                                , RULL(0x10B020100), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_LCL_TSEL_PPE                                , RULL(0x10C010100), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_LCL_TSEL_PPE                                , RULL(0x10C020100), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_LCL_TSEL_PPE                                , RULL(0x10D010100), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_LCL_TSEL_PPE                                , RULL(0x10D020100), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_LCL_TSEL_PPE                               , RULL(0x10E010100), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_LCL_TSEL_PPE                               , RULL(0x10E020100), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_AFSR_PPE                               , RULL(0x109010160), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_AFSR_PPE                               , RULL(0x109020160), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_AFSR_PPE                               , RULL(0x10A010160), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_AFSR_PPE                               , RULL(0x10A020160), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_AFSR_PPE                               , RULL(0x10B010160), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_AFSR_PPE                               , RULL(0x10B020160), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_AFSR_PPE                               , RULL(0x10C010160), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_AFSR_PPE                               , RULL(0x10C020160), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_AFSR_PPE                               , RULL(0x10D010160), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_AFSR_PPE                               , RULL(0x10D020160), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_AFSR_PPE                              , RULL(0x10E010160), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_AFSR_PPE                              , RULL(0x10E020160), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_AFTR_PPE                               , RULL(0x109010180), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_AFTR_PPE                               , RULL(0x109020180), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_AFTR_PPE                               , RULL(0x10A010180), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_AFTR_PPE                               , RULL(0x10A020180), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_AFTR_PPE                               , RULL(0x10B010180), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_AFTR_PPE                               , RULL(0x10B020180), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_AFTR_PPE                               , RULL(0x10C010180), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_AFTR_PPE                               , RULL(0x10C020180), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_AFTR_PPE                               , RULL(0x10D010180), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_AFTR_PPE                               , RULL(0x10D020180), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_AFTR_PPE                              , RULL(0x10E010180), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_AFTR_PPE                              , RULL(0x10E020180), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_BCECSR_PPE                             , RULL(0x1090101E0), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_BCECSR_PPE                             , RULL(0x1090201E0), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_BCECSR_PPE                             , RULL(0x10A0101E0), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_BCECSR_PPE                             , RULL(0x10A0201E0), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_BCECSR_PPE                             , RULL(0x10B0101E0), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_BCECSR_PPE                             , RULL(0x10B0201E0), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_BCECSR_PPE                             , RULL(0x10C0101E0), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_BCECSR_PPE                             , RULL(0x10C0201E0), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_BCECSR_PPE                             , RULL(0x10D0101E0), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_BCECSR_PPE                             , RULL(0x10D0201E0), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_BCECSR_PPE                            , RULL(0x10E0101E0), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_BCECSR_PPE                            , RULL(0x10E0201E0), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_CIDSR_PPE                              , RULL(0x1090106C0), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_CIDSR_PPE                              , RULL(0x1090206C0), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_CIDSR_PPE                              , RULL(0x10A0106C0), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_CIDSR_PPE                              , RULL(0x10A0206C0), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_CIDSR_PPE                              , RULL(0x10B0106C0), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_CIDSR_PPE                              , RULL(0x10B0206C0), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_CIDSR_PPE                              , RULL(0x10C0106C0), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_CIDSR_PPE                              , RULL(0x10C0206C0), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_CIDSR_PPE                              , RULL(0x10D0106C0), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_CIDSR_PPE                              , RULL(0x10D0206C0), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_CIDSR_PPE                             , RULL(0x10E0106C0), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_CIDSR_PPE                             , RULL(0x10E0206C0), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_FLAGS_PPE                              , RULL(0x109010400), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME0_CME_SCOM_FLAGS_PPE1                             , RULL(0x109010418), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME0_CME_SCOM_FLAGS_PPE2                             , RULL(0x109010410), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME1_CME_SCOM_FLAGS_PPE                              , RULL(0x109020400), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_FLAGS_PPE1                             , RULL(0x109020418), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME1_CME_SCOM_FLAGS_PPE2                             , RULL(0x109020410), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME2_CME_SCOM_FLAGS_PPE                              , RULL(0x10A010400), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_FLAGS_PPE1                             , RULL(0x10A010418), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME2_CME_SCOM_FLAGS_PPE2                             , RULL(0x10A010410), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME3_CME_SCOM_FLAGS_PPE                              , RULL(0x10A020400), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_FLAGS_PPE1                             , RULL(0x10A020418), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME3_CME_SCOM_FLAGS_PPE2                             , RULL(0x10A020410), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME4_CME_SCOM_FLAGS_PPE                              , RULL(0x10B010400), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_FLAGS_PPE1                             , RULL(0x10B010418), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME4_CME_SCOM_FLAGS_PPE2                             , RULL(0x10B010410), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME5_CME_SCOM_FLAGS_PPE                              , RULL(0x10B020400), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_FLAGS_PPE1                             , RULL(0x10B020418), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME5_CME_SCOM_FLAGS_PPE2                             , RULL(0x10B020410), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME6_CME_SCOM_FLAGS_PPE                              , RULL(0x10C010400), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_FLAGS_PPE1                             , RULL(0x10C010418), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME6_CME_SCOM_FLAGS_PPE2                             , RULL(0x10C010410), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME7_CME_SCOM_FLAGS_PPE                              , RULL(0x10C020400), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_FLAGS_PPE1                             , RULL(0x10C020418), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME7_CME_SCOM_FLAGS_PPE2                             , RULL(0x10C020410), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME8_CME_SCOM_FLAGS_PPE                              , RULL(0x10D010400), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_FLAGS_PPE1                             , RULL(0x10D010418), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME8_CME_SCOM_FLAGS_PPE2                             , RULL(0x10D010410), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME9_CME_SCOM_FLAGS_PPE                              , RULL(0x10D020400), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_FLAGS_PPE1                             , RULL(0x10D020418), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME9_CME_SCOM_FLAGS_PPE2                             , RULL(0x10D020410), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME10_CME_SCOM_FLAGS_PPE                             , RULL(0x10E010400), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_FLAGS_PPE1                            , RULL(0x10E010418), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME10_CME_SCOM_FLAGS_PPE2                            , RULL(0x10E010410), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE2      );
+REG64( PU_CME11_CME_SCOM_FLAGS_PPE                             , RULL(0x10E020400), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_FLAGS_PPE1                            , RULL(0x10E020418), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME11_CME_SCOM_FLAGS_PPE2                            , RULL(0x10E020410), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_SCOM_IDCR_PPE                               , RULL(0x1090106A0), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_IDCR_PPE                               , RULL(0x1090206A0), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_IDCR_PPE                               , RULL(0x10A0106A0), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_IDCR_PPE                               , RULL(0x10A0206A0), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_IDCR_PPE                               , RULL(0x10B0106A0), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_IDCR_PPE                               , RULL(0x10B0206A0), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_IDCR_PPE                               , RULL(0x10C0106A0), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_IDCR_PPE                               , RULL(0x10C0206A0), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_IDCR_PPE                               , RULL(0x10D0106A0), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_IDCR_PPE                               , RULL(0x10D0206A0), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_IDCR_PPE                              , RULL(0x10E0106A0), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_IDCR_PPE                              , RULL(0x10E0206A0), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PMCRS0_PPE                             , RULL(0x109010240), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PMCRS0_PPE                             , RULL(0x109020240), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PMCRS0_PPE                             , RULL(0x10A010240), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PMCRS0_PPE                             , RULL(0x10A020240), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PMCRS0_PPE                             , RULL(0x10B010240), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PMCRS0_PPE                             , RULL(0x10B020240), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PMCRS0_PPE                             , RULL(0x10C010240), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PMCRS0_PPE                             , RULL(0x10C020240), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PMCRS0_PPE                             , RULL(0x10D010240), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PMCRS0_PPE                             , RULL(0x10D020240), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PMCRS0_PPE                            , RULL(0x10E010240), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PMCRS0_PPE                            , RULL(0x10E020240), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PMCRS1_PPE                             , RULL(0x109010260), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PMCRS1_PPE                             , RULL(0x109020260), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PMCRS1_PPE                             , RULL(0x10A010260), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PMCRS1_PPE                             , RULL(0x10A020260), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PMCRS1_PPE                             , RULL(0x10B010260), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PMCRS1_PPE                             , RULL(0x10B020260), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PMCRS1_PPE                             , RULL(0x10C010260), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PMCRS1_PPE                             , RULL(0x10C020260), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PMCRS1_PPE                             , RULL(0x10D010260), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PMCRS1_PPE                             , RULL(0x10D020260), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PMCRS1_PPE                            , RULL(0x10E010260), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PMCRS1_PPE                            , RULL(0x10E020260), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PMSRS0_PPE                             , RULL(0x109010200), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PMSRS0_PPE                             , RULL(0x109020200), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PMSRS0_PPE                             , RULL(0x10A010200), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PMSRS0_PPE                             , RULL(0x10A020200), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PMSRS0_PPE                             , RULL(0x10B010200), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PMSRS0_PPE                             , RULL(0x10B020200), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PMSRS0_PPE                             , RULL(0x10C010200), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PMSRS0_PPE                             , RULL(0x10C020200), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PMSRS0_PPE                             , RULL(0x10D010200), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PMSRS0_PPE                             , RULL(0x10D020200), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PMSRS0_PPE                            , RULL(0x10E010200), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PMSRS0_PPE                            , RULL(0x10E020200), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PMSRS1_PPE                             , RULL(0x109010220), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PMSRS1_PPE                             , RULL(0x109020220), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PMSRS1_PPE                             , RULL(0x10A010220), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PMSRS1_PPE                             , RULL(0x10A020220), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PMSRS1_PPE                             , RULL(0x10B010220), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PMSRS1_PPE                             , RULL(0x10B020220), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PMSRS1_PPE                             , RULL(0x10C010220), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PMSRS1_PPE                             , RULL(0x10C020220), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PMSRS1_PPE                             , RULL(0x10D010220), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PMSRS1_PPE                             , RULL(0x10D020220), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PMSRS1_PPE                            , RULL(0x10E010220), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PMSRS1_PPE                            , RULL(0x10E020220), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS00_PPE                            , RULL(0x109010300), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS00_PPE                            , RULL(0x109020300), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS00_PPE                            , RULL(0x10A010300), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS00_PPE                            , RULL(0x10A020300), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS00_PPE                            , RULL(0x10B010300), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS00_PPE                            , RULL(0x10B020300), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS00_PPE                            , RULL(0x10C010300), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS00_PPE                            , RULL(0x10C020300), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS00_PPE                            , RULL(0x10D010300), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS00_PPE                            , RULL(0x10D020300), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS00_PPE                           , RULL(0x10E010300), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS00_PPE                           , RULL(0x10E020300), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS01_PPE                            , RULL(0x109010320), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS01_PPE                            , RULL(0x109020320), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS01_PPE                            , RULL(0x10A010320), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS01_PPE                            , RULL(0x10A020320), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS01_PPE                            , RULL(0x10B010320), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS01_PPE                            , RULL(0x10B020320), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS01_PPE                            , RULL(0x10C010320), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS01_PPE                            , RULL(0x10C020320), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS01_PPE                            , RULL(0x10D010320), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS01_PPE                            , RULL(0x10D020320), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS01_PPE                           , RULL(0x10E010320), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS01_PPE                           , RULL(0x10E020320), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS02_PPE                            , RULL(0x109010340), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS02_PPE                            , RULL(0x109020340), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS02_PPE                            , RULL(0x10A010340), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS02_PPE                            , RULL(0x10A020340), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS02_PPE                            , RULL(0x10B010340), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS02_PPE                            , RULL(0x10B020340), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS02_PPE                            , RULL(0x10C010340), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS02_PPE                            , RULL(0x10C020340), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS02_PPE                            , RULL(0x10D010340), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS02_PPE                            , RULL(0x10D020340), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS02_PPE                           , RULL(0x10E010340), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS02_PPE                           , RULL(0x10E020340), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS03_PPE                            , RULL(0x109010360), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS03_PPE                            , RULL(0x109020360), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS03_PPE                            , RULL(0x10A010360), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS03_PPE                            , RULL(0x10A020360), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS03_PPE                            , RULL(0x10B010360), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS03_PPE                            , RULL(0x10B020360), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS03_PPE                            , RULL(0x10C010360), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS03_PPE                            , RULL(0x10C020360), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS03_PPE                            , RULL(0x10D010360), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS03_PPE                            , RULL(0x10D020360), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS03_PPE                           , RULL(0x10E010360), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS03_PPE                           , RULL(0x10E020360), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS10_PPE                            , RULL(0x109010380), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS10_PPE                            , RULL(0x109020380), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS10_PPE                            , RULL(0x10A010380), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS10_PPE                            , RULL(0x10A020380), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS10_PPE                            , RULL(0x10B010380), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS10_PPE                            , RULL(0x10B020380), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS10_PPE                            , RULL(0x10C010380), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS10_PPE                            , RULL(0x10C020380), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS10_PPE                            , RULL(0x10D010380), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS10_PPE                            , RULL(0x10D020380), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS10_PPE                           , RULL(0x10E010380), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS10_PPE                           , RULL(0x10E020380), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS11_PPE                            , RULL(0x1090103A0), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS11_PPE                            , RULL(0x1090203A0), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS11_PPE                            , RULL(0x10A0103A0), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS11_PPE                            , RULL(0x10A0203A0), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS11_PPE                            , RULL(0x10B0103A0), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS11_PPE                            , RULL(0x10B0203A0), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS11_PPE                            , RULL(0x10C0103A0), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS11_PPE                            , RULL(0x10C0203A0), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS11_PPE                            , RULL(0x10D0103A0), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS11_PPE                            , RULL(0x10D0203A0), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS11_PPE                           , RULL(0x10E0103A0), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS11_PPE                           , RULL(0x10E0203A0), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS12_PPE                            , RULL(0x1090103C0), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS12_PPE                            , RULL(0x1090203C0), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS12_PPE                            , RULL(0x10A0103C0), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS12_PPE                            , RULL(0x10A0203C0), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS12_PPE                            , RULL(0x10B0103C0), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS12_PPE                            , RULL(0x10B0203C0), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS12_PPE                            , RULL(0x10C0103C0), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS12_PPE                            , RULL(0x10C0203C0), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS12_PPE                            , RULL(0x10D0103C0), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS12_PPE                            , RULL(0x10D0203C0), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS12_PPE                           , RULL(0x10E0103C0), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS12_PPE                           , RULL(0x10E0203C0), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_PSCRS13_PPE                            , RULL(0x1090103E0), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_PSCRS13_PPE                            , RULL(0x1090203E0), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_PSCRS13_PPE                            , RULL(0x10A0103E0), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_PSCRS13_PPE                            , RULL(0x10A0203E0), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_PSCRS13_PPE                            , RULL(0x10B0103E0), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_PSCRS13_PPE                            , RULL(0x10B0203E0), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_PSCRS13_PPE                            , RULL(0x10C0103E0), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_PSCRS13_PPE                            , RULL(0x10C0203E0), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_PSCRS13_PPE                            , RULL(0x10D0103E0), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_PSCRS13_PPE                            , RULL(0x10D0203E0), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_PSCRS13_PPE                           , RULL(0x10E0103E0), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_PSCRS13_PPE                           , RULL(0x10E0203E0), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_QFMR_PPE                               , RULL(0x109010140), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_QFMR_PPE                               , RULL(0x109020140), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_QFMR_PPE                               , RULL(0x10A010140), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_QFMR_PPE                               , RULL(0x10A020140), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_QFMR_PPE                               , RULL(0x10B010140), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_QFMR_PPE                               , RULL(0x10B020140), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_QFMR_PPE                               , RULL(0x10C010140), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_QFMR_PPE                               , RULL(0x10C020140), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_QFMR_PPE                               , RULL(0x10D010140), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_QFMR_PPE                               , RULL(0x10D020140), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_QFMR_PPE                              , RULL(0x10E010140), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_QFMR_PPE                              , RULL(0x10E020140), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_QIDSR_PPE                              , RULL(0x1090106E0), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_QIDSR_PPE                              , RULL(0x1090206E0), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_QIDSR_PPE                              , RULL(0x10A0106E0), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_QIDSR_PPE                              , RULL(0x10A0206E0), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_QIDSR_PPE                              , RULL(0x10B0106E0), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_QIDSR_PPE                              , RULL(0x10B0206E0), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_QIDSR_PPE                              , RULL(0x10C0106E0), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_QIDSR_PPE                              , RULL(0x10C0206E0), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_QIDSR_PPE                              , RULL(0x10D0106E0), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_QIDSR_PPE                              , RULL(0x10D0206E0), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_QIDSR_PPE                             , RULL(0x10E0106E0), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_QIDSR_PPE                             , RULL(0x10E0206E0), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_SICR_PPE                               , RULL(0x109010500), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME0_CME_SCOM_SICR_PPE1                              , RULL(0x109010518), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME0_CME_SCOM_SICR_PPE2                              , RULL(0x109010510), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME1_CME_SCOM_SICR_PPE                               , RULL(0x109020500), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_SICR_PPE1                              , RULL(0x109020518), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME1_CME_SCOM_SICR_PPE2                              , RULL(0x109020510), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME2_CME_SCOM_SICR_PPE                               , RULL(0x10A010500), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_SICR_PPE1                              , RULL(0x10A010518), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME2_CME_SCOM_SICR_PPE2                              , RULL(0x10A010510), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME3_CME_SCOM_SICR_PPE                               , RULL(0x10A020500), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_SICR_PPE1                              , RULL(0x10A020518), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME3_CME_SCOM_SICR_PPE2                              , RULL(0x10A020510), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME4_CME_SCOM_SICR_PPE                               , RULL(0x10B010500), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_SICR_PPE1                              , RULL(0x10B010518), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME4_CME_SCOM_SICR_PPE2                              , RULL(0x10B010510), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME5_CME_SCOM_SICR_PPE                               , RULL(0x10B020500), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_SICR_PPE1                              , RULL(0x10B020518), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME5_CME_SCOM_SICR_PPE2                              , RULL(0x10B020510), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME6_CME_SCOM_SICR_PPE                               , RULL(0x10C010500), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_SICR_PPE1                              , RULL(0x10C010518), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME6_CME_SCOM_SICR_PPE2                              , RULL(0x10C010510), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME7_CME_SCOM_SICR_PPE                               , RULL(0x10C020500), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_SICR_PPE1                              , RULL(0x10C020518), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME7_CME_SCOM_SICR_PPE2                              , RULL(0x10C020510), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME8_CME_SCOM_SICR_PPE                               , RULL(0x10D010500), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_SICR_PPE1                              , RULL(0x10D010518), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME8_CME_SCOM_SICR_PPE2                              , RULL(0x10D010510), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME9_CME_SCOM_SICR_PPE                               , RULL(0x10D020500), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_SICR_PPE1                              , RULL(0x10D020518), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE1      );
+REG64( PU_CME9_CME_SCOM_SICR_PPE2                              , RULL(0x10D020510), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE2      );
+REG64( PU_CME10_CME_SCOM_SICR_PPE                              , RULL(0x10E010500), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_SICR_PPE1                             , RULL(0x10E010518), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME10_CME_SCOM_SICR_PPE2                             , RULL(0x10E010510), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE2      );
+REG64( PU_CME11_CME_SCOM_SICR_PPE                              , RULL(0x10E020500), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_SICR_PPE1                             , RULL(0x10E020518), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE1      );
+REG64( PU_CME11_CME_SCOM_SICR_PPE2                             , RULL(0x10E020510), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE2      );
+
+REG64( PU_CME0_CME_SCOM_SRTCH0_PPE                             , RULL(0x109010420), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_SRTCH0_PPE                             , RULL(0x109020420), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_SRTCH0_PPE                             , RULL(0x10A010420), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_SRTCH0_PPE                             , RULL(0x10A020420), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_SRTCH0_PPE                             , RULL(0x10B010420), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_SRTCH0_PPE                             , RULL(0x10B020420), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_SRTCH0_PPE                             , RULL(0x10C010420), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_SRTCH0_PPE                             , RULL(0x10C020420), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_SRTCH0_PPE                             , RULL(0x10D010420), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_SRTCH0_PPE                             , RULL(0x10D020420), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_SRTCH0_PPE                            , RULL(0x10E010420), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_SRTCH0_PPE                            , RULL(0x10E020420), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_SRTCH1_PPE                             , RULL(0x109010440), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_SRTCH1_PPE                             , RULL(0x109020440), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_SRTCH1_PPE                             , RULL(0x10A010440), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_SRTCH1_PPE                             , RULL(0x10A020440), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_SRTCH1_PPE                             , RULL(0x10B010440), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_SRTCH1_PPE                             , RULL(0x10B020440), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_SRTCH1_PPE                             , RULL(0x10C010440), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_SRTCH1_PPE                             , RULL(0x10C020440), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_SRTCH1_PPE                             , RULL(0x10D010440), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_SRTCH1_PPE                             , RULL(0x10D020440), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_SRTCH1_PPE                            , RULL(0x10E010440), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_SRTCH1_PPE                            , RULL(0x10E020440), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_VCCR_PPE                               , RULL(0x109010680), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_VCCR_PPE                               , RULL(0x109020680), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_VCCR_PPE                               , RULL(0x10A010680), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_VCCR_PPE                               , RULL(0x10A020680), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_VCCR_PPE                               , RULL(0x10B010680), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_VCCR_PPE                               , RULL(0x10B020680), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_VCCR_PPE                               , RULL(0x10C010680), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_VCCR_PPE                               , RULL(0x10C020680), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_VCCR_PPE                               , RULL(0x10D010680), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_VCCR_PPE                               , RULL(0x10D020680), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_VCCR_PPE                              , RULL(0x10E010680), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_VCCR_PPE                              , RULL(0x10E020680), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_VDCR_PPE                               , RULL(0x109010600), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_VDCR_PPE                               , RULL(0x109020600), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_VDCR_PPE                               , RULL(0x10A010600), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_VDCR_PPE                               , RULL(0x10A020600), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_VDCR_PPE                               , RULL(0x10B010600), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_VDCR_PPE                               , RULL(0x10B020600), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_VDCR_PPE                               , RULL(0x10C010600), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_VDCR_PPE                               , RULL(0x10C020600), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_VDCR_PPE                               , RULL(0x10D010600), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_VDCR_PPE                               , RULL(0x10D020600), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_VDCR_PPE                              , RULL(0x10E010600), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_VDCR_PPE                              , RULL(0x10E020600), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_VDSR_PPE                               , RULL(0x109010640), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_VDSR_PPE                               , RULL(0x109020640), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_VDSR_PPE                               , RULL(0x10A010640), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_VDSR_PPE                               , RULL(0x10A020640), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_VDSR_PPE                               , RULL(0x10B010640), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_VDSR_PPE                               , RULL(0x10B020640), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_VDSR_PPE                               , RULL(0x10C010640), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_VDSR_PPE                               , RULL(0x10C020640), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_VDSR_PPE                               , RULL(0x10D010640), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_VDSR_PPE                               , RULL(0x10D020640), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_VDSR_PPE                              , RULL(0x10E010640), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_VDSR_PPE                              , RULL(0x10E020640), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_VECR_PPE                               , RULL(0x109010660), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_VECR_PPE                               , RULL(0x109020660), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_VECR_PPE                               , RULL(0x10A010660), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_VECR_PPE                               , RULL(0x10A020660), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_VECR_PPE                               , RULL(0x10B010660), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_VECR_PPE                               , RULL(0x10B020660), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_VECR_PPE                               , RULL(0x10C010660), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_VECR_PPE                               , RULL(0x10C020660), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_VECR_PPE                               , RULL(0x10D010660), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_VECR_PPE                               , RULL(0x10D020660), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_VECR_PPE                              , RULL(0x10E010660), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_VECR_PPE                              , RULL(0x10E020660), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_VNCR_PPE                               , RULL(0x109010620), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_VNCR_PPE                               , RULL(0x109020620), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_VNCR_PPE                               , RULL(0x10A010620), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_VNCR_PPE                               , RULL(0x10A020620), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_VNCR_PPE                               , RULL(0x10B010620), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_VNCR_PPE                               , RULL(0x10B020620), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_VNCR_PPE                               , RULL(0x10C010620), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_VNCR_PPE                               , RULL(0x10C020620), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_VNCR_PPE                               , RULL(0x10D010620), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_VNCR_PPE                               , RULL(0x10D020620), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_VNCR_PPE                              , RULL(0x10E010620), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_VNCR_PPE                              , RULL(0x10E020620), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_XIPCBMD0_PPE                           , RULL(0x109010580), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_XIPCBMD0_PPE                           , RULL(0x109020580), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_XIPCBMD0_PPE                           , RULL(0x10A010580), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_XIPCBMD0_PPE                           , RULL(0x10A020580), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_XIPCBMD0_PPE                           , RULL(0x10B010580), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_XIPCBMD0_PPE                           , RULL(0x10B020580), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_XIPCBMD0_PPE                           , RULL(0x10C010580), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_XIPCBMD0_PPE                           , RULL(0x10C020580), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_XIPCBMD0_PPE                           , RULL(0x10D010580), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_XIPCBMD0_PPE                           , RULL(0x10D020580), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_XIPCBMD0_PPE                          , RULL(0x10E010580), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_XIPCBMD0_PPE                          , RULL(0x10E020580), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_XIPCBMD1_PPE                           , RULL(0x1090105A0), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_XIPCBMD1_PPE                           , RULL(0x1090205A0), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_XIPCBMD1_PPE                           , RULL(0x10A0105A0), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_XIPCBMD1_PPE                           , RULL(0x10A0205A0), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_XIPCBMD1_PPE                           , RULL(0x10B0105A0), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_XIPCBMD1_PPE                           , RULL(0x10B0205A0), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_XIPCBMD1_PPE                           , RULL(0x10C0105A0), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_XIPCBMD1_PPE                           , RULL(0x10C0205A0), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_XIPCBMD1_PPE                           , RULL(0x10D0105A0), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_XIPCBMD1_PPE                           , RULL(0x10D0205A0), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_XIPCBMD1_PPE                          , RULL(0x10E0105A0), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_XIPCBMD1_PPE                          , RULL(0x10E0205A0), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_XIPCBMI0_PPE                           , RULL(0x1090105C0), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_XIPCBMI0_PPE                           , RULL(0x1090205C0), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_XIPCBMI0_PPE                           , RULL(0x10A0105C0), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_XIPCBMI0_PPE                           , RULL(0x10A0205C0), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_XIPCBMI0_PPE                           , RULL(0x10B0105C0), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_XIPCBMI0_PPE                           , RULL(0x10B0205C0), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_XIPCBMI0_PPE                           , RULL(0x10C0105C0), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_XIPCBMI0_PPE                           , RULL(0x10C0205C0), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_XIPCBMI0_PPE                           , RULL(0x10D0105C0), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_XIPCBMI0_PPE                           , RULL(0x10D0205C0), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_XIPCBMI0_PPE                          , RULL(0x10E0105C0), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_XIPCBMI0_PPE                          , RULL(0x10E0205C0), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_CME0_CME_SCOM_XIPCBMI1_PPE                           , RULL(0x1090105E0), SH_UNT_PU_CME0  ,
+       SH_ACS_PPE       );
+REG64( PU_CME1_CME_SCOM_XIPCBMI1_PPE                           , RULL(0x1090205E0), SH_UNT_PU_CME1  ,
+       SH_ACS_PPE       );
+REG64( PU_CME2_CME_SCOM_XIPCBMI1_PPE                           , RULL(0x10A0105E0), SH_UNT_PU_CME2  ,
+       SH_ACS_PPE       );
+REG64( PU_CME3_CME_SCOM_XIPCBMI1_PPE                           , RULL(0x10A0205E0), SH_UNT_PU_CME3  ,
+       SH_ACS_PPE       );
+REG64( PU_CME4_CME_SCOM_XIPCBMI1_PPE                           , RULL(0x10B0105E0), SH_UNT_PU_CME4  ,
+       SH_ACS_PPE       );
+REG64( PU_CME5_CME_SCOM_XIPCBMI1_PPE                           , RULL(0x10B0205E0), SH_UNT_PU_CME5  ,
+       SH_ACS_PPE       );
+REG64( PU_CME6_CME_SCOM_XIPCBMI1_PPE                           , RULL(0x10C0105E0), SH_UNT_PU_CME6  ,
+       SH_ACS_PPE       );
+REG64( PU_CME7_CME_SCOM_XIPCBMI1_PPE                           , RULL(0x10C0205E0), SH_UNT_PU_CME7  ,
+       SH_ACS_PPE       );
+REG64( PU_CME8_CME_SCOM_XIPCBMI1_PPE                           , RULL(0x10D0105E0), SH_UNT_PU_CME8  ,
+       SH_ACS_PPE       );
+REG64( PU_CME9_CME_SCOM_XIPCBMI1_PPE                           , RULL(0x10D0205E0), SH_UNT_PU_CME9  ,
+       SH_ACS_PPE       );
+REG64( PU_CME10_CME_SCOM_XIPCBMI1_PPE                          , RULL(0x10E0105E0), SH_UNT_PU_CME10 ,
+       SH_ACS_PPE       );
+REG64( PU_CME11_CME_SCOM_XIPCBMI1_PPE                          , RULL(0x10E0205E0), SH_UNT_PU_CME11 ,
+       SH_ACS_PPE       );
+
+REG64( PU_COMMAND_REGISTER                                     , RULL(0x00010000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_COMMAND_REGISTER_B                                   , RULL(0x000A0005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_COMMAND_REGISTER_C                                   , RULL(0x000A1005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_COMMAND_REGISTER_D                                   , RULL(0x000A2005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_COMMAND_REGISTER_E                                   , RULL(0x000A3005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_CONFIG0                                     , RULL(0x05011080), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CONFIG0                                     , RULL(0x05011180), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CONFIG0                                     , RULL(0x05011280), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CONFIG0                                     , RULL(0x05011000), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CONFIG0                                     , RULL(0x05011020), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CONFIG0                                     , RULL(0x05011040), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CONFIG0                                     , RULL(0x05011060), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CONFIG0                                     , RULL(0x05011100), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CONFIG0                                     , RULL(0x05011120), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CONFIG0                                     , RULL(0x05011140), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CONFIG0                                     , RULL(0x05011160), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CONFIG0                                     , RULL(0x05011200), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CONFIG0                                     , RULL(0x05011220), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CONFIG0                                     , RULL(0x05011240), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CONFIG0                                     , RULL(0x05011260), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( NV_CONFIG1                                              , RULL(0x050110D8), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_CONFIG1                                            , RULL(0x050110D8), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_CONFIG1                                            , RULL(0x050110F8), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_CONFIG1                                            , RULL(0x050111D8), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_CONFIG1                                            , RULL(0x050111F8), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_CONFIG1                                     , RULL(0x05011081), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_CONFIG1                                         , RULL(0x050110A1), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CONFIG1                                         , RULL(0x050111A1), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CONFIG1                                     , RULL(0x05011181), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CONFIG1                                     , RULL(0x05011281), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CONFIG1                                         , RULL(0x050112A1), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_CONFIG1                                     , RULL(0x05011001), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CONFIG1                                     , RULL(0x05011021), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CONFIG1                                     , RULL(0x05011041), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CONFIG1                                     , RULL(0x05011061), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CONFIG1                                     , RULL(0x05011101), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CONFIG1                                     , RULL(0x05011121), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CONFIG1                                     , RULL(0x05011141), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CONFIG1                                     , RULL(0x05011161), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CONFIG1                                    , RULL(0x050112D8), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CONFIG1                                    , RULL(0x050112F8), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CONFIG1                                     , RULL(0x05011201), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CONFIG1                                     , RULL(0x05011221), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CONFIG1                                     , RULL(0x05011241), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CONFIG1                                     , RULL(0x05011261), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( NV_CONFIG2                                              , RULL(0x050110C0), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_CONFIG2                                            , RULL(0x050110C0), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_CONFIG2                                            , RULL(0x050110E0), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_CONFIG2                                            , RULL(0x050111C0), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_CONFIG2                                            , RULL(0x050111E0), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_CONFIG2                                     , RULL(0x05011082), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CONFIG2                                     , RULL(0x05011182), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CONFIG2                                     , RULL(0x05011282), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CONFIG2                                    , RULL(0x050112C0), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CONFIG2                                    , RULL(0x050112E0), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( NV_CONFIG3                                              , RULL(0x050110C1), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_CONFIG3                                            , RULL(0x050110C1), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_CONFIG3                                            , RULL(0x050110E1), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_CONFIG3                                            , RULL(0x050111C1), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_CONFIG3                                            , RULL(0x050111E1), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_CONFIG3                                     , RULL(0x05011083), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CONFIG3                                     , RULL(0x05011183), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CONFIG3                                     , RULL(0x05011283), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CONFIG3                                    , RULL(0x050112C1), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CONFIG3                                    , RULL(0x050112E1), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_CONFIG_RELAXED0                             , RULL(0x0501100A), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CONFIG_RELAXED0                             , RULL(0x0501102A), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CONFIG_RELAXED0                             , RULL(0x0501104A), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CONFIG_RELAXED0                             , RULL(0x0501106A), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CONFIG_RELAXED0                             , RULL(0x0501110A), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CONFIG_RELAXED0                             , RULL(0x0501112A), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CONFIG_RELAXED0                             , RULL(0x0501114A), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CONFIG_RELAXED0                             , RULL(0x0501116A), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CONFIG_RELAXED0                             , RULL(0x0501120A), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CONFIG_RELAXED0                             , RULL(0x0501122A), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CONFIG_RELAXED0                             , RULL(0x0501124A), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CONFIG_RELAXED0                             , RULL(0x0501126A), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_CONFIG_RELAXED1                             , RULL(0x0501100B), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CONFIG_RELAXED1                             , RULL(0x0501102B), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CONFIG_RELAXED1                             , RULL(0x0501104B), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CONFIG_RELAXED1                             , RULL(0x0501106B), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CONFIG_RELAXED1                             , RULL(0x0501110B), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CONFIG_RELAXED1                             , RULL(0x0501112B), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CONFIG_RELAXED1                             , RULL(0x0501114B), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CONFIG_RELAXED1                             , RULL(0x0501116B), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CONFIG_RELAXED1                             , RULL(0x0501120B), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CONFIG_RELAXED1                             , RULL(0x0501122B), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CONFIG_RELAXED1                             , RULL(0x0501124B), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CONFIG_RELAXED1                             , RULL(0x0501126B), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_CONFIG_RELAXED2                             , RULL(0x0501100C), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_CONFIG_RELAXED2                             , RULL(0x0501102C), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_CONFIG_RELAXED2                             , RULL(0x0501104C), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_CONFIG_RELAXED2                             , RULL(0x0501106C), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_CONFIG_RELAXED2                             , RULL(0x0501110C), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_CONFIG_RELAXED2                             , RULL(0x0501112C), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_CONFIG_RELAXED2                             , RULL(0x0501114C), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_CONFIG_RELAXED2                             , RULL(0x0501116C), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_CONFIG_RELAXED2                             , RULL(0x0501120C), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_CONFIG_RELAXED2                             , RULL(0x0501122C), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_CONFIG_RELAXED2                             , RULL(0x0501124C), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_CONFIG_RELAXED2                             , RULL(0x0501126C), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PEC_CONTROL_REG                                         , RULL(0x0D050012), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_CONTROL_REG                                       , RULL(0x0D050012), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_CONTROL_REG                                       , RULL(0x0E050012), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_CONTROL_REG                                       , RULL(0x0F050012), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_CONTROL_REGISTER_B                                   , RULL(0x000A0000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_CONTROL_REGISTER_C                                   , RULL(0x000A1000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_CONTROL_REGISTER_D                                   , RULL(0x000A2000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_CONTROL_REGISTER_E                                   , RULL(0x000A3000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_CPLT_CONF0                                          , RULL(0x0D000008), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_CPLT_CONF0_OR                                       , RULL(0x0D000018), SH_UNT_PEC      , SH_ACS_SCOM1_OR  );
+REG64( PEC_CPLT_CONF0_CLEAR                                    , RULL(0x0D000028), SH_UNT_PEC      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PEC_0_CPLT_CONF0                                        , RULL(0x0D000008), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_0_CPLT_CONF0_OR                                     , RULL(0x0D000018), SH_UNT_PEC_0    , SH_ACS_SCOM1_OR  );
+REG64( PEC_0_CPLT_CONF0_CLEAR                                  , RULL(0x0D000028), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PEC_1_CPLT_CONF0                                        , RULL(0x0E000008), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_CPLT_CONF0_OR                                     , RULL(0x0E000018), SH_UNT_PEC_1    , SH_ACS_SCOM1_OR  );
+REG64( PEC_1_CPLT_CONF0_CLEAR                                  , RULL(0x0E000028), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PEC_2_CPLT_CONF0                                        , RULL(0x0F000008), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_CPLT_CONF0_OR                                     , RULL(0x0F000018), SH_UNT_PEC_2    , SH_ACS_SCOM1_OR  );
+REG64( PEC_2_CPLT_CONF0_CLEAR                                  , RULL(0x0F000028), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM2_CLEAR );
+
+REG64( PEC_CPLT_CONF1                                          , RULL(0x0D000009), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_CPLT_CONF1_OR                                       , RULL(0x0D000019), SH_UNT_PEC      , SH_ACS_SCOM1_OR  );
+REG64( PEC_CPLT_CONF1_CLEAR                                    , RULL(0x0D000029), SH_UNT_PEC      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PEC_0_CPLT_CONF1                                        , RULL(0x0D000009), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_0_CPLT_CONF1_OR                                     , RULL(0x0D000019), SH_UNT_PEC_0    , SH_ACS_SCOM1_OR  );
+REG64( PEC_0_CPLT_CONF1_CLEAR                                  , RULL(0x0D000029), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PEC_1_CPLT_CONF1                                        , RULL(0x0E000009), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_CPLT_CONF1_OR                                     , RULL(0x0E000019), SH_UNT_PEC_1    , SH_ACS_SCOM1_OR  );
+REG64( PEC_1_CPLT_CONF1_CLEAR                                  , RULL(0x0E000029), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PEC_2_CPLT_CONF1                                        , RULL(0x0F000009), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_CPLT_CONF1_OR                                     , RULL(0x0F000019), SH_UNT_PEC_2    , SH_ACS_SCOM1_OR  );
+REG64( PEC_2_CPLT_CONF1_CLEAR                                  , RULL(0x0F000029), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM2_CLEAR );
+
+REG64( PEC_CPLT_CTRL0                                          , RULL(0x0D000000), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_CPLT_CTRL0_OR                                       , RULL(0x0D000010), SH_UNT_PEC      , SH_ACS_SCOM1_OR  );
+REG64( PEC_CPLT_CTRL0_CLEAR                                    , RULL(0x0D000020), SH_UNT_PEC      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PEC_0_CPLT_CTRL0                                        , RULL(0x0D000000), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_0_CPLT_CTRL0_OR                                     , RULL(0x0D000010), SH_UNT_PEC_0    , SH_ACS_SCOM1_OR  );
+REG64( PEC_0_CPLT_CTRL0_CLEAR                                  , RULL(0x0D000020), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PEC_1_CPLT_CTRL0                                        , RULL(0x0E000000), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_CPLT_CTRL0_OR                                     , RULL(0x0E000010), SH_UNT_PEC_1    , SH_ACS_SCOM1_OR  );
+REG64( PEC_1_CPLT_CTRL0_CLEAR                                  , RULL(0x0E000020), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PEC_2_CPLT_CTRL0                                        , RULL(0x0F000000), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_CPLT_CTRL0_OR                                     , RULL(0x0F000010), SH_UNT_PEC_2    , SH_ACS_SCOM1_OR  );
+REG64( PEC_2_CPLT_CTRL0_CLEAR                                  , RULL(0x0F000020), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM2_CLEAR );
+
+REG64( PEC_CPLT_CTRL1                                          , RULL(0x0D000001), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_CPLT_CTRL1_OR                                       , RULL(0x0D000011), SH_UNT_PEC      , SH_ACS_SCOM1_OR  );
+REG64( PEC_CPLT_CTRL1_CLEAR                                    , RULL(0x0D000021), SH_UNT_PEC      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PEC_0_CPLT_CTRL1                                        , RULL(0x0D000001), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_0_CPLT_CTRL1_OR                                     , RULL(0x0D000011), SH_UNT_PEC_0    , SH_ACS_SCOM1_OR  );
+REG64( PEC_0_CPLT_CTRL1_CLEAR                                  , RULL(0x0D000021), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PEC_1_CPLT_CTRL1                                        , RULL(0x0E000001), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_CPLT_CTRL1_OR                                     , RULL(0x0E000011), SH_UNT_PEC_1    , SH_ACS_SCOM1_OR  );
+REG64( PEC_1_CPLT_CTRL1_CLEAR                                  , RULL(0x0E000021), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PEC_2_CPLT_CTRL1                                        , RULL(0x0F000001), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_CPLT_CTRL1_OR                                     , RULL(0x0F000011), SH_UNT_PEC_2    , SH_ACS_SCOM1_OR  );
+REG64( PEC_2_CPLT_CTRL1_CLEAR                                  , RULL(0x0F000021), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM2_CLEAR );
+
+REG64( PEC_CPLT_MASK0                                          , RULL(0x0D000101), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_CPLT_MASK0                                        , RULL(0x0D000101), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_CPLT_MASK0                                        , RULL(0x0E000101), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_CPLT_MASK0                                        , RULL(0x0F000101), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_CPLT_STAT0                                          , RULL(0x0D000100), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_CPLT_STAT0                                        , RULL(0x0D000100), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_CPLT_STAT0                                        , RULL(0x0E000100), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_CPLT_STAT0                                        , RULL(0x0F000100), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_0_STACK0_CQSTAT_REG                                 , RULL(0x04010C4C), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_0_STACK1_CQSTAT_REG                                 , RULL(0x04010C8C), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_0_STACK2_CQSTAT_REG                                 , RULL(0x04010CCC), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK0_CQSTAT_REG                                 , RULL(0x0401104C), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK1_CQSTAT_REG                                 , RULL(0x0401108C), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_1_STACK2_CQSTAT_REG                                 , RULL(0x040110CC), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK0_CQSTAT_REG                                 , RULL(0x0401144C), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK1_CQSTAT_REG                                 , RULL(0x0401148C), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_2_STACK2_CQSTAT_REG                                 , RULL(0x040114CC), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_STACK0_CQSTAT_REG                                   , RULL(0x04010C4C), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_STACK1_CQSTAT_REG                                   , RULL(0x04010C8C), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM_RO   );
+REG64( PEC_STACK2_CQSTAT_REG                                   , RULL(0x04010CCC), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM_RO   );
+REG64( PHB_CQSTAT_REG                                          , RULL(0x04010C4C), SH_UNT_PHB      , SH_ACS_SCOM_RO   );
+REG64( PHB_0_CQSTAT_REG                                        , RULL(0x04010C4C), SH_UNT_PHB_0    , SH_ACS_SCOM_RO   );
+REG64( PHB_1_CQSTAT_REG                                        , RULL(0x0401104C), SH_UNT_PHB_1    , SH_ACS_SCOM_RO   );
+REG64( PHB_2_CQSTAT_REG                                        , RULL(0x0401108C), SH_UNT_PHB_2    , SH_ACS_SCOM_RO   );
+REG64( PHB_3_CQSTAT_REG                                        , RULL(0x0401144C), SH_UNT_PHB_3    , SH_ACS_SCOM_RO   );
+REG64( PHB_4_CQSTAT_REG                                        , RULL(0x0401148C), SH_UNT_PHB_4    , SH_ACS_SCOM_RO   );
+REG64( PHB_5_CQSTAT_REG                                        , RULL(0x040114CC), SH_UNT_PHB_5    , SH_ACS_SCOM_RO   );
+
+REG64( NV_CREQ_DA_PTR                                          , RULL(0x050110D4), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_CREQ_DA_PTR                                        , RULL(0x050110D4), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_CREQ_DA_PTR                                        , RULL(0x050110F4), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_CREQ_DA_PTR                                        , RULL(0x050111D4), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_CREQ_DA_PTR                                        , RULL(0x050111F4), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CREQ_DA_PTR                                , RULL(0x050112D4), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CREQ_DA_PTR                                , RULL(0x050112F4), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( NV_CREQ_HA_PTR                                          , RULL(0x050110D0), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_CREQ_HA_PTR                                        , RULL(0x050110D0), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_CREQ_HA_PTR                                        , RULL(0x050110F0), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_CREQ_HA_PTR                                        , RULL(0x050111D0), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_CREQ_HA_PTR                                        , RULL(0x050111F0), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_CREQ_HA_PTR                                , RULL(0x050112D0), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_CREQ_HA_PTR                                , RULL(0x050112F0), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_CSAR                                                 , RULL(0x0501240D), SH_UNT          ,
+       SH_ACS_SCOM_RW   ); //DUPS: 09011058, 0C011058,
+
+REG64( PU_CSCR                                                 , RULL(0x0501240A), SH_UNT          ,
+       SH_ACS_SCOM_RW   ); //DUPS: 09011055, 0C011055,
+REG64( PU_CSCR_CLEAR                                           , RULL(0x0501240B), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 09011001, 0C011001,
+REG64( PU_CSCR_OR                                              , RULL(0x0501240C), SH_UNT          ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 09011002, 0C011002,
+
+REG64( PU_CSDR                                                 , RULL(0x0501240E), SH_UNT          ,
+       SH_ACS_SCOM_RW   ); //DUPS: 09011059, 0C011059,
+
+REG64( PU_NPU0_CTL_CTL_STATUS                                  , RULL(0x05011092), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_CTL_STATUS                                  , RULL(0x05011192), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_CTL_STATUS                                  , RULL(0x05011292), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PEC_CTRL_ATOMIC_LOCK_REG                                , RULL(0x0D0003FF), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_CTRL_ATOMIC_LOCK_REG                              , RULL(0x0D0003FF), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_CTRL_ATOMIC_LOCK_REG                              , RULL(0x0E0003FF), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_CTRL_ATOMIC_LOCK_REG                              , RULL(0x0F0003FF), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_CTRL_PROTECT_MODE_REG                               , RULL(0x0D0003FE), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_CTRL_PROTECT_MODE_REG                             , RULL(0x0D0003FE), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_CTRL_PROTECT_MODE_REG                             , RULL(0x0E0003FE), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_CTRL_PROTECT_MODE_REG                             , RULL(0x0F0003FE), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_SNP_ARRAY_ADDR_REG                             , RULL(0x02010828), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_SNP_ARRAY_ADDR_REG                           , RULL(0x02010828), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_SNP_ARRAY_ADDR_REG                           , RULL(0x04010828), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_SNP_ARRAY_READ_REG                             , RULL(0x02010829), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_SNP_ARRAY_READ_REG                           , RULL(0x02010829), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_SNP_ARRAY_READ_REG                           , RULL(0x04010829), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_SNP_ARRAY_WRITE_REG                            , RULL(0x02010841), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_SNP_ARRAY_WRITE_REG                          , RULL(0x02010841), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_SNP_ARRAY_WRITE_REG                          , RULL(0x04010841), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_SNP_CAN_PRESP_REG0                             , RULL(0x0201081D), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_SNP_CAN_PRESP_REG0                           , RULL(0x0201081D), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_SNP_CAN_PRESP_REG0                           , RULL(0x0401081D), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_SNP_CAN_PRESP_REG1                             , RULL(0x0201081E), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_SNP_CAN_PRESP_REG1                           , RULL(0x0201081E), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_SNP_CAN_PRESP_REG1                           , RULL(0x0401081E), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_SNP_CAN_PRESP_REG2                             , RULL(0x0201081F), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_SNP_CAN_PRESP_REG2                           , RULL(0x0201081F), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_SNP_CAN_PRESP_REG2                           , RULL(0x0401081F), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_SNP_CAPI_CFG_REG                               , RULL(0x0201081A), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_SNP_CAPI_CFG_REG                             , RULL(0x0201081A), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_SNP_CAPI_CFG_REG                             , RULL(0x0401081A), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_SNP_CNTL_REG                                   , RULL(0x0201081B), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_SNP_CNTL_REG                                 , RULL(0x0201081B), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_SNP_CNTL_REG                                 , RULL(0x0401081B), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_SNP_ERROR_REPORT_REG                           , RULL(0x0201080A), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_SNP_ERROR_REPORT_REG                         , RULL(0x0201080A), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_SNP_ERROR_REPORT_REG                         , RULL(0x0401080A), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_SNP_PHB_TTAG_FILTER_REG                        , RULL(0x02010831), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_SNP_PHB_TTAG_FILTER_REG                      , RULL(0x02010831), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_SNP_PHB_TTAG_FILTER_REG                      , RULL(0x04010831), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG                      , RULL(0x02010817), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_SNP_PMU_EVENTS_SELECT_REG                    , RULL(0x02010817), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_SNP_PMU_EVENTS_SELECT_REG                    , RULL(0x04010817), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG                   , RULL(0x02010840), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG                 , RULL(0x02010840), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG                 , RULL(0x04010840), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1                  , RULL(0x02010844), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1                , RULL(0x02010844), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1                , RULL(0x04010844), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG                   , RULL(0x0201084A), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG                 , RULL(0x0201084A), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG                 , RULL(0x0401084A), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1                  , RULL(0x0201084B), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1                , RULL(0x0201084B), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1                , RULL(0x0401084B), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_CXA_TRIGCTL                                        , RULL(0x02010812), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_CXA_TRIGCTL                                      , RULL(0x02010812), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_CXA_TRIGCTL                                      , RULL(0x04010812), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( PU_DATA0TO7_REGISTER_B                                  , RULL(0x000A0003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATA0TO7_REGISTER_C                                  , RULL(0x000A1003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATA0TO7_REGISTER_D                                  , RULL(0x000A2003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATA0TO7_REGISTER_E                                  , RULL(0x000A3003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATA8TO15_REGISTER_B                                 , RULL(0x000A0001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATA8TO15_REGISTER_C                                 , RULL(0x000A1001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATA8TO15_REGISTER_D                                 , RULL(0x000A2001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATA8TO15_REGISTER_E                                 , RULL(0x000A3001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DATATAG_0_HASH_FUNCTION_REG                          , RULL(0x0201114C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_DATATAG_1_HASH_FUNCTION_REG                          , RULL(0x0201114D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_DATATAG_2_HASH_FUNCTION_REG                          , RULL(0x0201114E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_DATATAG_3_HASH_FUNCTION_REG                          , RULL(0x0201114F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_DATATAG_4_HASH_FUNCTION_REG                          , RULL(0x02011150), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_DATATAG_5_HASH_FUNCTION_REG                          , RULL(0x02011151), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_DATA_REGISTER                                        , RULL(0x00010003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_DA_ADDR                                      , RULL(0x0501138E), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_DA_DATA                                      , RULL(0x0501138F), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM_RW   );
+
+REG64( PEC_DBG_CBS_CC                                          , RULL(0x0D030013), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_DBG_CBS_CC                                        , RULL(0x0D030013), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_DBG_CBS_CC                                        , RULL(0x0E030013), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_DBG_CBS_CC                                        , RULL(0x0F030013), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_DBG_INST1_COND_REG_1                                , RULL(0x0D0107C1), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_DBG_INST1_COND_REG_1                              , RULL(0x0D0107C1), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_DBG_INST1_COND_REG_1                              , RULL(0x0E0107C1), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_DBG_INST1_COND_REG_1                              , RULL(0x0F0107C1), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_DBG_INST1_COND_REG_1                              , RULL(0x020107C1), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_DBG_INST1_COND_REG_1                              , RULL(0x030107C1), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_DBG_INST1_COND_REG_1                              , RULL(0x040107C1), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_DBG_INST1_COND_REG_1                              , RULL(0x050107C1), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PEC_DBG_INST1_COND_REG_2                                , RULL(0x0D0107C2), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_DBG_INST1_COND_REG_2                              , RULL(0x0D0107C2), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_DBG_INST1_COND_REG_2                              , RULL(0x0E0107C2), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_DBG_INST1_COND_REG_2                              , RULL(0x0F0107C2), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_DBG_INST1_COND_REG_2                              , RULL(0x020107C2), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_DBG_INST1_COND_REG_2                              , RULL(0x030107C2), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_DBG_INST1_COND_REG_2                              , RULL(0x040107C2), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_DBG_INST1_COND_REG_2                              , RULL(0x050107C2), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PEC_DBG_INST1_COND_REG_3                                , RULL(0x0D0107C3), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_DBG_INST1_COND_REG_3                              , RULL(0x0D0107C3), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_DBG_INST1_COND_REG_3                              , RULL(0x0E0107C3), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_DBG_INST1_COND_REG_3                              , RULL(0x0F0107C3), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_DBG_INST1_COND_REG_3                              , RULL(0x020107C3), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_DBG_INST1_COND_REG_3                              , RULL(0x030107C3), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_DBG_INST1_COND_REG_3                              , RULL(0x040107C3), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_DBG_INST1_COND_REG_3                              , RULL(0x050107C3), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PEC_DBG_INST2_COND_REG_1                                , RULL(0x0D0107C4), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_DBG_INST2_COND_REG_1                              , RULL(0x0D0107C4), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_DBG_INST2_COND_REG_1                              , RULL(0x0E0107C4), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_DBG_INST2_COND_REG_1                              , RULL(0x0F0107C4), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_DBG_INST2_COND_REG_1                              , RULL(0x020107C4), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_DBG_INST2_COND_REG_1                              , RULL(0x030107C4), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_DBG_INST2_COND_REG_1                              , RULL(0x040107C4), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_DBG_INST2_COND_REG_1                              , RULL(0x050107C4), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PEC_DBG_INST2_COND_REG_2                                , RULL(0x0D0107C5), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_DBG_INST2_COND_REG_2                              , RULL(0x0D0107C5), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_DBG_INST2_COND_REG_2                              , RULL(0x0E0107C5), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_DBG_INST2_COND_REG_2                              , RULL(0x0F0107C5), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_DBG_INST2_COND_REG_2                              , RULL(0x020107C5), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_DBG_INST2_COND_REG_2                              , RULL(0x030107C5), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_DBG_INST2_COND_REG_2                              , RULL(0x040107C5), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_DBG_INST2_COND_REG_2                              , RULL(0x050107C5), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PEC_DBG_INST2_COND_REG_3                                , RULL(0x0D0107C6), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_DBG_INST2_COND_REG_3                              , RULL(0x0D0107C6), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_DBG_INST2_COND_REG_3                              , RULL(0x0E0107C6), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_DBG_INST2_COND_REG_3                              , RULL(0x0F0107C6), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_DBG_INST2_COND_REG_3                              , RULL(0x020107C6), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_DBG_INST2_COND_REG_3                              , RULL(0x030107C6), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_DBG_INST2_COND_REG_3                              , RULL(0x040107C6), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_DBG_INST2_COND_REG_3                              , RULL(0x050107C6), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PEC_DBG_MODE_REG                                        , RULL(0x0D0107C0), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_DBG_MODE_REG                                      , RULL(0x0D0107C0), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_DBG_MODE_REG                                      , RULL(0x0E0107C0), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_DBG_MODE_REG                                      , RULL(0x0F0107C0), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_DBG_MODE_REG                                      , RULL(0x020107C0), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_DBG_MODE_REG                                      , RULL(0x030107C0), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_DBG_MODE_REG                                      , RULL(0x040107C0), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_DBG_MODE_REG                                      , RULL(0x050107C0), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PEC_DBG_TRACE_MODE_REG_2                                , RULL(0x0D0107CF), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_DBG_TRACE_MODE_REG_2                              , RULL(0x0D0107CF), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_DBG_TRACE_MODE_REG_2                              , RULL(0x0E0107CF), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_DBG_TRACE_MODE_REG_2                              , RULL(0x0F0107CF), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_DBG_TRACE_MODE_REG_2                              , RULL(0x020107CF), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_DBG_TRACE_MODE_REG_2                              , RULL(0x030107CF), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_DBG_TRACE_MODE_REG_2                              , RULL(0x040107CF), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_DBG_TRACE_MODE_REG_2                              , RULL(0x050107CF), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PEC_DBG_TRACE_REG_0                                     , RULL(0x0D0107CD), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_DBG_TRACE_REG_0                                   , RULL(0x0D0107CD), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_DBG_TRACE_REG_0                                   , RULL(0x0E0107CD), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_DBG_TRACE_REG_0                                   , RULL(0x0F0107CD), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_DBG_TRACE_REG_0                                   , RULL(0x020107CD), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_DBG_TRACE_REG_0                                   , RULL(0x030107CD), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_DBG_TRACE_REG_0                                   , RULL(0x040107CD), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_DBG_TRACE_REG_0                                   , RULL(0x050107CD), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PEC_DBG_TRACE_REG_1                                     , RULL(0x0D0107CE), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_DBG_TRACE_REG_1                                   , RULL(0x0D0107CE), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_DBG_TRACE_REG_1                                   , RULL(0x0E0107CE), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_DBG_TRACE_REG_1                                   , RULL(0x0F0107CE), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_DBG_TRACE_REG_1                                   , RULL(0x020107CE), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_DBG_TRACE_REG_1                                   , RULL(0x030107CE), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_DBG_TRACE_REG_1                                   , RULL(0x040107CE), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_DBG_TRACE_REG_1                                   , RULL(0x050107CE), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( NV_DEBUG0_CONFIG                                        , RULL(0x050110CC), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_DEBUG0_CONFIG                                      , RULL(0x050110CC), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_DEBUG0_CONFIG                                      , RULL(0x050110EC), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_DEBUG0_CONFIG                                      , RULL(0x050111CC), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_DEBUG0_CONFIG                                      , RULL(0x050111EC), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_DEBUG0_CONFIG                               , RULL(0x05011088), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_DAT_DEBUG0_CONFIG                               , RULL(0x050110B0), SH_UNT_PU_NPU0_DAT,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_DEBUG0_CONFIG                               , RULL(0x05011188), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_DAT_DEBUG0_CONFIG                               , RULL(0x050111B0), SH_UNT_PU_NPU1_DAT,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_DEBUG0_CONFIG                               , RULL(0x05011288), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_DAT_DEBUG0_CONFIG                               , RULL(0x050112B0), SH_UNT_PU_NPU2_DAT,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_DEBUG0_CONFIG                              , RULL(0x050112CC), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_DEBUG0_CONFIG                              , RULL(0x050112EC), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU_SM2_DEBUG0_CONFIG                                , RULL(0x05011346), SH_UNT_PU_NPU_SM2,
+       SH_ACS_SCOM      );
+
+REG64( NV_DEBUG1_CONFIG                                        , RULL(0x050110CD), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_DEBUG1_CONFIG                                      , RULL(0x050110CD), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_DEBUG1_CONFIG                                      , RULL(0x050110ED), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_DEBUG1_CONFIG                                      , RULL(0x050111CD), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_DEBUG1_CONFIG                                      , RULL(0x050111ED), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_DEBUG1_CONFIG                               , RULL(0x05011089), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_DAT_DEBUG1_CONFIG                               , RULL(0x050110B1), SH_UNT_PU_NPU0_DAT,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_DEBUG1_CONFIG                               , RULL(0x05011189), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_DAT_DEBUG1_CONFIG                               , RULL(0x050111B1), SH_UNT_PU_NPU1_DAT,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_DEBUG1_CONFIG                               , RULL(0x05011289), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_DAT_DEBUG1_CONFIG                               , RULL(0x050112B1), SH_UNT_PU_NPU2_DAT,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_DEBUG1_CONFIG                              , RULL(0x050112CD), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_DEBUG1_CONFIG                              , RULL(0x050112ED), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU_SM2_DEBUG1_CONFIG                                , RULL(0x05011347), SH_UNT_PU_NPU_SM2,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_DEBUG_CONFIG                                 , RULL(0x05011380), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( CAPP_DEBUG_CONTROL                                      , RULL(0x02010811), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_DEBUG_CONTROL                                    , RULL(0x02010811), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_DEBUG_CONTROL                                    , RULL(0x04010811), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( PU_DEBUG_TRACE_CONTROL                                  , RULL(0x020107D0), SH_UNT          ,
+       SH_ACS_SCOM      ); //DUPS: 050107D0, 030107D0, 040107D0,
+
+REG64( PEC_DEBUG_TRACE_CONTROL                                 , RULL(0x0D0107D0), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_DEBUG_TRACE_CONTROL                               , RULL(0x0D0107D0), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_DEBUG_TRACE_CONTROL                               , RULL(0x0E0107D0), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_DEBUG_TRACE_CONTROL                               , RULL(0x0F0107D0), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( CAPP_DFSUOP1                                            , RULL(0x02010843), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_DFSUOP1                                          , RULL(0x02010843), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_DFSUOP1                                          , RULL(0x04010843), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( PU_DISABLE_FORCE_PFET_OFF                               , RULL(0x0001000D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM1_DMA_SYNC                                     , RULL(0x05011323), SH_UNT_PU_NPU_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_DMA_UP_ADDR                                          , RULL(0x05012914), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_DMA_VAS_MMIO_BAR                                     , RULL(0x0201105E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PEC_DRPPRICTL_REG                                       , RULL(0x04010C01), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_DRPPRICTL_REG                                     , RULL(0x04010C01), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_DRPPRICTL_REG                                     , RULL(0x04011001), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_DRPPRICTL_REG                                     , RULL(0x04011401), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_DTS_RESULT0                                         , RULL(0x0D050000), SH_UNT_PEC      , SH_ACS_SCOM_RO   );
+REG64( PEC_0_DTS_RESULT0                                       , RULL(0x0D050000), SH_UNT_PEC_0    , SH_ACS_SCOM_RO   );
+REG64( PEC_1_DTS_RESULT0                                       , RULL(0x0E050000), SH_UNT_PEC_1    , SH_ACS_SCOM_RO   );
+REG64( PEC_2_DTS_RESULT0                                       , RULL(0x0F050000), SH_UNT_PEC_2    , SH_ACS_SCOM_RO   );
+
+REG64( PEC_DTS_TRC_RESULT                                      , RULL(0x0D050003), SH_UNT_PEC      , SH_ACS_SCOM_RO   );
+REG64( PEC_0_DTS_TRC_RESULT                                    , RULL(0x0D050003), SH_UNT_PEC_0    , SH_ACS_SCOM_RO   );
+REG64( PEC_1_DTS_TRC_RESULT                                    , RULL(0x0E050003), SH_UNT_PEC_1    , SH_ACS_SCOM_RO   );
+REG64( PEC_2_DTS_TRC_RESULT                                    , RULL(0x0F050003), SH_UNT_PEC_2    , SH_ACS_SCOM_RO   );
+
+REG64( PU_NPU0_ECC_CONFIG                                      , RULL(0x050110A2), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_ECC_CONFIG                                      , RULL(0x050111A2), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_ECC_CONFIG                                      , RULL(0x050112A2), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART0_REGISTER                          , RULL(0x00018000), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART0_REGISTER                          , RULL(0x00018040), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART10_REGISTER                         , RULL(0x0001800A), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART10_REGISTER                         , RULL(0x0001804A), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART11_REGISTER                         , RULL(0x0001800B), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART11_REGISTER                         , RULL(0x0001804B), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART12_REGISTER                         , RULL(0x0001800C), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART12_REGISTER                         , RULL(0x0001804C), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART13_REGISTER                         , RULL(0x0001800D), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART13_REGISTER                         , RULL(0x0001804D), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART14_REGISTER                         , RULL(0x0001800E), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART14_REGISTER                         , RULL(0x0001804E), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART15_REGISTER                         , RULL(0x0001800F), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART15_REGISTER                         , RULL(0x0001804F), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART16_REGISTER                         , RULL(0x00018010), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART16_REGISTER                         , RULL(0x00018050), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART17_REGISTER                         , RULL(0x00018011), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART17_REGISTER                         , RULL(0x00018051), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART18_REGISTER                         , RULL(0x00018012), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART18_REGISTER                         , RULL(0x00018052), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART19_REGISTER                         , RULL(0x00018013), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART19_REGISTER                         , RULL(0x00018053), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART1_REGISTER                          , RULL(0x00018001), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART1_REGISTER                          , RULL(0x00018041), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART20_REGISTER                         , RULL(0x00018014), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART20_REGISTER                         , RULL(0x00018054), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART21_REGISTER                         , RULL(0x00018015), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART21_REGISTER                         , RULL(0x00018055), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART22_REGISTER                         , RULL(0x00018016), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART22_REGISTER                         , RULL(0x00018056), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART23_REGISTER                         , RULL(0x00018017), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART23_REGISTER                         , RULL(0x00018057), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART24_REGISTER                         , RULL(0x00018018), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART24_REGISTER                         , RULL(0x00018058), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART25_REGISTER                         , RULL(0x00018019), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART25_REGISTER                         , RULL(0x00018059), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART26_REGISTER                         , RULL(0x0001801A), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART26_REGISTER                         , RULL(0x0001805A), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART27_REGISTER                         , RULL(0x0001801B), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART27_REGISTER                         , RULL(0x0001805B), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART28_REGISTER                         , RULL(0x0001801C), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART28_REGISTER                         , RULL(0x0001805C), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART29_REGISTER                         , RULL(0x0001801D), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART29_REGISTER                         , RULL(0x0001805D), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART2_REGISTER                          , RULL(0x00018002), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART2_REGISTER                          , RULL(0x00018042), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART30_REGISTER                         , RULL(0x0001801E), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART30_REGISTER                         , RULL(0x0001805E), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART31_REGISTER                         , RULL(0x0001801F), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART31_REGISTER                         , RULL(0x0001805F), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART32_REGISTER                         , RULL(0x00018020), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART32_REGISTER                         , RULL(0x00018060), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART33_REGISTER                         , RULL(0x00018021), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART33_REGISTER                         , RULL(0x00018061), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART34_REGISTER                         , RULL(0x00018022), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART34_REGISTER                         , RULL(0x00018062), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART35_REGISTER                         , RULL(0x00018023), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART35_REGISTER                         , RULL(0x00018063), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART36_REGISTER                         , RULL(0x00018024), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART36_REGISTER                         , RULL(0x00018064), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART37_REGISTER                         , RULL(0x00018025), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART37_REGISTER                         , RULL(0x00018065), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART38_REGISTER                         , RULL(0x00018026), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART38_REGISTER                         , RULL(0x00018066), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART39_REGISTER                         , RULL(0x00018027), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART39_REGISTER                         , RULL(0x00018067), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART3_REGISTER                          , RULL(0x00018003), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART3_REGISTER                          , RULL(0x00018043), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART40_REGISTER                         , RULL(0x00018028), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART40_REGISTER                         , RULL(0x00018068), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART41_REGISTER                         , RULL(0x00018029), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART41_REGISTER                         , RULL(0x00018069), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART42_REGISTER                         , RULL(0x0001802A), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART42_REGISTER                         , RULL(0x0001806A), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART43_REGISTER                         , RULL(0x0001802B), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART43_REGISTER                         , RULL(0x0001806B), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART44_REGISTER                         , RULL(0x0001802C), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART44_REGISTER                         , RULL(0x0001806C), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART45_REGISTER                         , RULL(0x0001802D), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART45_REGISTER                         , RULL(0x0001806D), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART46_REGISTER                         , RULL(0x0001802E), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART46_REGISTER                         , RULL(0x0001806E), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART47_REGISTER                         , RULL(0x0001802F), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART47_REGISTER                         , RULL(0x0001806F), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART48_REGISTER                         , RULL(0x00018030), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART48_REGISTER                         , RULL(0x00018070), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART49_REGISTER                         , RULL(0x00018031), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART49_REGISTER                         , RULL(0x00018071), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART4_REGISTER                          , RULL(0x00018004), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART4_REGISTER                          , RULL(0x00018044), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART50_REGISTER                         , RULL(0x00018032), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART50_REGISTER                         , RULL(0x00018072), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART51_REGISTER                         , RULL(0x00018033), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART51_REGISTER                         , RULL(0x00018073), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART52_REGISTER                         , RULL(0x00018034), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART52_REGISTER                         , RULL(0x00018074), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART53_REGISTER                         , RULL(0x00018035), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART53_REGISTER                         , RULL(0x00018075), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART54_REGISTER                         , RULL(0x00018036), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART54_REGISTER                         , RULL(0x00018076), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART55_REGISTER                         , RULL(0x00018037), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART55_REGISTER                         , RULL(0x00018077), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART56_REGISTER                         , RULL(0x00018038), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART56_REGISTER                         , RULL(0x00018078), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART57_REGISTER                         , RULL(0x00018039), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART57_REGISTER                         , RULL(0x00018079), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART58_REGISTER                         , RULL(0x0001803A), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART58_REGISTER                         , RULL(0x0001807A), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART59_REGISTER                         , RULL(0x0001803B), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART59_REGISTER                         , RULL(0x0001807B), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART5_REGISTER                          , RULL(0x00018005), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART5_REGISTER                          , RULL(0x00018045), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART60_REGISTER                         , RULL(0x0001803C), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART60_REGISTER                         , RULL(0x0001807C), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART61_REGISTER                         , RULL(0x0001803D), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART61_REGISTER                         , RULL(0x0001807D), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART62_REGISTER                         , RULL(0x0001803E), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART62_REGISTER                         , RULL(0x0001807E), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART63_REGISTER                         , RULL(0x0001803F), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART63_REGISTER                         , RULL(0x0001807F), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART6_REGISTER                          , RULL(0x00018006), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART6_REGISTER                          , RULL(0x00018046), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART7_REGISTER                          , RULL(0x00018007), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART7_REGISTER                          , RULL(0x00018047), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART8_REGISTER                          , RULL(0x00018008), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART8_REGISTER                          , RULL(0x00018048), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_OTPROM0_ECID_PART9_REGISTER                          , RULL(0x00018009), SH_UNT_PU_OTPROM0,
+       SH_ACS_SCOM      );
+REG64( PU_OTPROM1_ECID_PART9_REGISTER                          , RULL(0x00018049), SH_UNT_PU_OTPROM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_EECNT_REG                                            , RULL(0x05012809), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EFT_HI_PRIOR_RCV_FIFO_ASB                            , RULL(0x020110C6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EFT_HI_PRIOR_RCV_FIFO_BAR                            , RULL(0x020110C0), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL                           , RULL(0x020110C3), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EFT_LO_PRIOR_RCV_FIFO_ASB                            , RULL(0x020110CF), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EFT_LO_PRIOR_RCV_FIFO_BAR                            , RULL(0x020110C9), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EFT_LO_PRIOR_RCV_FIFO_CNTL                           , RULL(0x020110CC), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EFT_MAX_BYTE_CNT                                     , RULL(0x02011059), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_EHHCA_FIR_ACTION0_REG                                , RULL(0x05012986), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_EHHCA_FIR_ACTION1_REG                                , RULL(0x05012987), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_EHHCA_FIR_MASK_REG                                   , RULL(0x05012983), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_EHHCA_FIR_MASK_REG_AND                               , RULL(0x05012984), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_EHHCA_FIR_MASK_REG_OR                                , RULL(0x05012985), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_EHHCA_FIR_REG                                        , RULL(0x05012980), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_EHHCA_FIR_REG_AND                                    , RULL(0x05012981), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_EHHCA_FIR_REG_OR                                     , RULL(0x05012982), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_NPU0_SM0_EPSILON_CONFIG                              , RULL(0x05011002), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_EPSILON_CONFIG                              , RULL(0x05011022), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_EPSILON_CONFIG                              , RULL(0x05011042), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_EPSILON_CONFIG                              , RULL(0x05011062), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_EPSILON_CONFIG                              , RULL(0x05011102), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_EPSILON_CONFIG                              , RULL(0x05011122), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_EPSILON_CONFIG                              , RULL(0x05011142), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_EPSILON_CONFIG                              , RULL(0x05011162), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_EPSILON_CONFIG                              , RULL(0x05011202), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_EPSILON_CONFIG                              , RULL(0x05011222), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_EPSILON_CONFIG                              , RULL(0x05011242), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_EPSILON_CONFIG                              , RULL(0x05011262), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_ERAT_STATUS_CONTROL                                  , RULL(0x020110D6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG                     , RULL(0x05011394), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PEC_ERROR_REG                                           , RULL(0x0D0F001F), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_ERROR_REG                                         , RULL(0x0D0F001F), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_ERROR_REG                                         , RULL(0x0E0F001F), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_ERROR_REG                                         , RULL(0x0F0F001F), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_ERROR_STATUS                                        , RULL(0x0D03000F), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_ERROR_STATUS                                      , RULL(0x0D03000F), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_ERROR_STATUS                                      , RULL(0x0E03000F), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_ERROR_STATUS                                      , RULL(0x0F03000F), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( CAPP_ERRRPT                                             , RULL(0x0201080B), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_ERRRPT                                           , RULL(0x0201080B), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_ERRRPT                                           , RULL(0x0401080B), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM2_ERR_FIRST                                    , RULL(0x05011343), SH_UNT_PU_NPU_SM2,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM2_ERR_HOLD                                     , RULL(0x05011340), SH_UNT_PU_NPU_SM2,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR                       , RULL(0x05011392), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM2_ERR_MASK                                     , RULL(0x05011342), SH_UNT_PU_NPU_SM2,
+       SH_ACS_SCOM      );
+
+REG64( CAPP_ERR_RPT_CLR                                        , RULL(0x02010813), SH_UNT_CAPP     , SH_ACS_SCOM_WO   );
+REG64( CAPP_0_ERR_RPT_CLR                                      , RULL(0x02010813), SH_UNT_CAPP_0   , SH_ACS_SCOM_WO   );
+REG64( CAPP_1_ERR_RPT_CLR                                      , RULL(0x04010813), SH_UNT_CAPP_1   , SH_ACS_SCOM_WO   );
+
+REG64( PU_NPU_CTL_ERR_SCOPE_CTL_CONFIG                         , RULL(0x05011391), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PEC_ERR_STATUS_REG                                      , RULL(0x0D050013), SH_UNT_PEC      , SH_ACS_SCOM_RO   );
+REG64( PEC_0_ERR_STATUS_REG                                    , RULL(0x0D050013), SH_UNT_PEC_0    , SH_ACS_SCOM_RO   );
+REG64( PEC_1_ERR_STATUS_REG                                    , RULL(0x0E050013), SH_UNT_PEC_1    , SH_ACS_SCOM_RO   );
+REG64( PEC_2_ERR_STATUS_REG                                    , RULL(0x0F050013), SH_UNT_PEC_2    , SH_ACS_SCOM_RO   );
+
+REG64( PU_ESB_CI_BASE                                          , RULL(0x05012916), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_ESB_NOTIFY                                           , RULL(0x05012917), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EXPORT_REGL_CTRL                                     , RULL(0x0001000E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EXTENDED_STATUS_B                                    , RULL(0x000A000C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EXTENDED_STATUS_C                                    , RULL(0x000A100C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EXTENDED_STATUS_D                                    , RULL(0x000A200C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_EXTENDED_STATUS_E                                    , RULL(0x000A300C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM1_EXTFIR_ACTION0_REG                       , RULL(0x05011C34), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_CENT_SM1_EXTFIR_ACTION1_REG                       , RULL(0x05011C35), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_CENT_SM1_EXTFIR_MASK_REG                          , RULL(0x05011C31), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PB_CENT_SM1_EXTFIR_MASK_REG_AND                      , RULL(0x05011C32), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM1_AND );
+REG64( PU_PB_CENT_SM1_EXTFIR_MASK_REG_OR                       , RULL(0x05011C33), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_CENT_SM1_EXTFIR_REG                               , RULL(0x05011C2E), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PB_CENT_SM1_EXTFIR_REG_AND                           , RULL(0x05011C2F), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM1_AND );
+REG64( PU_PB_CENT_SM1_EXTFIR_REG_OR                            , RULL(0x05011C30), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM2_OR  );
+
+REG64( PU_NPU_CTL_FENCE_0_CONFIG                               , RULL(0x0501138A), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_FENCE_1_CONFIG                               , RULL(0x0501138B), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_FENCE_STATE                                  , RULL(0x05011396), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_FI2C_CFG_PPE                                         , RULL(0xC0000800), SH_UNT          , SH_ACS_PPE       );
+REG64( PU_FI2C_CFG_PPE1                                        , RULL(0xC0000810), SH_UNT          , SH_ACS_PPE1      );
+REG64( PU_FI2C_CFG_PPE2                                        , RULL(0xC0000818), SH_UNT          , SH_ACS_PPE2      );
+
+REG64( PU_FI2C_SCFG0_PPE                                       , RULL(0xC0000860), SH_UNT          , SH_ACS_PPE       );
+REG64( PU_FI2C_SCFG0_PPE1                                      , RULL(0xC0000870), SH_UNT          , SH_ACS_PPE1      );
+REG64( PU_FI2C_SCFG0_PPE2                                      , RULL(0xC0000878), SH_UNT          , SH_ACS_PPE2      );
+
+REG64( PU_FI2C_SCFG1_PPE                                       , RULL(0xC0000880), SH_UNT          , SH_ACS_PPE       );
+REG64( PU_FI2C_SCFG1_PPE1                                      , RULL(0xC0000890), SH_UNT          , SH_ACS_PPE1      );
+REG64( PU_FI2C_SCFG1_PPE2                                      , RULL(0xC0000898), SH_UNT          , SH_ACS_PPE2      );
+
+REG64( PU_FI2C_SCFG2_PPE                                       , RULL(0xC00008A0), SH_UNT          , SH_ACS_PPE       );
+REG64( PU_FI2C_SCFG2_PPE1                                      , RULL(0xC00008B0), SH_UNT          , SH_ACS_PPE1      );
+REG64( PU_FI2C_SCFG2_PPE2                                      , RULL(0xC00008B8), SH_UNT          , SH_ACS_PPE2      );
+
+REG64( PU_FI2C_SCFG3_PPE                                       , RULL(0xC00008C0), SH_UNT          , SH_ACS_PPE       );
+REG64( PU_FI2C_SCFG3_PPE1                                      , RULL(0xC00008D0), SH_UNT          , SH_ACS_PPE1      );
+REG64( PU_FI2C_SCFG3_PPE2                                      , RULL(0xC00008D8), SH_UNT          , SH_ACS_PPE2      );
+
+REG64( PU_FI2C_STAT_PPE                                        , RULL(0xC0000820), SH_UNT          , SH_ACS_PPE       );
+
+REG64( PU_FIFO1_REGISTER_READ_B                                , RULL(0x000A0004), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIFO1_REGISTER_READ_C                                , RULL(0x000A1004), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIFO1_REGISTER_READ_D                                , RULL(0x000A2004), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIFO1_REGISTER_READ_E                                , RULL(0x000A3004), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIFO4_REGISTER_READ_B                                , RULL(0x000A0012), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIFO4_REGISTER_READ_C                                , RULL(0x000A1012), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIFO4_REGISTER_READ_D                                , RULL(0x000A2012), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIFO4_REGISTER_READ_E                                , RULL(0x000A3012), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FIR_ACTION0_REG                                      , RULL(0x04011806), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( CAPP_FIR_ACTION0_REG                                    , RULL(0x02010806), SH_UNT_CAPP     , SH_ACS_SCOM_RO   );
+REG64( CAPP_0_FIR_ACTION0_REG                                  , RULL(0x02010806), SH_UNT_CAPP_0   , SH_ACS_SCOM_RO   );
+REG64( CAPP_1_FIR_ACTION0_REG                                  , RULL(0x04010806), SH_UNT_CAPP_1   , SH_ACS_SCOM_RO   );
+
+REG64( PEC_FIR_ACTION0_REG                                     , RULL(0x0D010C06), SH_UNT_PEC      , SH_ACS_SCOM_RO   );
+REG64( PEC_0_FIR_ACTION0_REG                                   , RULL(0x0D010C06), SH_UNT_PEC_0    , SH_ACS_SCOM_RO   );
+REG64( PEC_1_FIR_ACTION0_REG                                   , RULL(0x0E010C06), SH_UNT_PEC_1    , SH_ACS_SCOM_RO   );
+REG64( PEC_2_FIR_ACTION0_REG                                   , RULL(0x0F010C06), SH_UNT_PEC_2    , SH_ACS_SCOM_RO   );
+
+REG64( PU_NPU_MSC_SM0_FIR_ACTION0_REG_0                        , RULL(0x05011406), SH_UNT_PU_NPU_MSC_SM0,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU_MSC_SM2_FIR_ACTION0_REG_1                        , RULL(0x05011446), SH_UNT_PU_NPU_MSC_SM2,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_FIR_ACTION1_REG                                      , RULL(0x04011807), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( CAPP_FIR_ACTION1_REG                                    , RULL(0x02010807), SH_UNT_CAPP     , SH_ACS_SCOM_RO   );
+REG64( CAPP_0_FIR_ACTION1_REG                                  , RULL(0x02010807), SH_UNT_CAPP_0   , SH_ACS_SCOM_RO   );
+REG64( CAPP_1_FIR_ACTION1_REG                                  , RULL(0x04010807), SH_UNT_CAPP_1   , SH_ACS_SCOM_RO   );
+
+REG64( PEC_FIR_ACTION1_REG                                     , RULL(0x0D010C07), SH_UNT_PEC      , SH_ACS_SCOM_RO   );
+REG64( PEC_0_FIR_ACTION1_REG                                   , RULL(0x0D010C07), SH_UNT_PEC_0    , SH_ACS_SCOM_RO   );
+REG64( PEC_1_FIR_ACTION1_REG                                   , RULL(0x0E010C07), SH_UNT_PEC_1    , SH_ACS_SCOM_RO   );
+REG64( PEC_2_FIR_ACTION1_REG                                   , RULL(0x0F010C07), SH_UNT_PEC_2    , SH_ACS_SCOM_RO   );
+
+REG64( PU_NPU_MSC_SM0_FIR_ACTION1_REG_0                        , RULL(0x05011407), SH_UNT_PU_NPU_MSC_SM0,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU_MSC_SM2_FIR_ACTION1_REG_1                        , RULL(0x05011447), SH_UNT_PU_NPU_MSC_SM2,
+       SH_ACS_SCOM_RW   );
+
+REG64( PEC_FIR_MASK                                            , RULL(0x0D040002), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_FIR_MASK                                          , RULL(0x0D040002), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_FIR_MASK                                          , RULL(0x0E040002), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_FIR_MASK                                          , RULL(0x0F040002), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_FIR_MASK_REG                                         , RULL(0x04011803), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_FIR_MASK_REG_AND                                     , RULL(0x04011804), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_FIR_MASK_REG_OR                                      , RULL(0x04011805), SH_UNT          , SH_ACS_SCOM2_OR  );
+REG64( CAPP_FIR_MASK_REG                                       , RULL(0x02010803), SH_UNT_CAPP     , SH_ACS_SCOM_RW   );
+REG64( CAPP_FIR_MASK_REG_AND                                   , RULL(0x02010804), SH_UNT_CAPP     , SH_ACS_SCOM1_AND );
+REG64( CAPP_FIR_MASK_REG_OR                                    , RULL(0x02010805), SH_UNT_CAPP     , SH_ACS_SCOM2_OR  );
+REG64( CAPP_0_FIR_MASK_REG                                     , RULL(0x02010803), SH_UNT_CAPP_0   , SH_ACS_SCOM_RW   );
+REG64( CAPP_0_FIR_MASK_REG_AND                                 , RULL(0x02010804), SH_UNT_CAPP_0   , SH_ACS_SCOM1_AND );
+REG64( CAPP_0_FIR_MASK_REG_OR                                  , RULL(0x02010805), SH_UNT_CAPP_0   , SH_ACS_SCOM2_OR  );
+REG64( CAPP_1_FIR_MASK_REG                                     , RULL(0x04010803), SH_UNT_CAPP_1   , SH_ACS_SCOM_RW   );
+REG64( CAPP_1_FIR_MASK_REG_AND                                 , RULL(0x04010804), SH_UNT_CAPP_1   , SH_ACS_SCOM1_AND );
+REG64( CAPP_1_FIR_MASK_REG_OR                                  , RULL(0x04010805), SH_UNT_CAPP_1   , SH_ACS_SCOM2_OR  );
+
+REG64( PEC_FIR_MASK_REG                                        , RULL(0x0D010C03), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_FIR_MASK_REG_AND                                    , RULL(0x0D010C04), SH_UNT_PEC      , SH_ACS_SCOM1_AND );
+REG64( PEC_FIR_MASK_REG_OR                                     , RULL(0x0D010C05), SH_UNT_PEC      , SH_ACS_SCOM2_OR  );
+REG64( PEC_0_FIR_MASK_REG                                      , RULL(0x0D010C03), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_0_FIR_MASK_REG_AND                                  , RULL(0x0D010C04), SH_UNT_PEC_0    , SH_ACS_SCOM1_AND );
+REG64( PEC_0_FIR_MASK_REG_OR                                   , RULL(0x0D010C05), SH_UNT_PEC_0    , SH_ACS_SCOM2_OR  );
+REG64( PEC_1_FIR_MASK_REG                                      , RULL(0x0E010C03), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_FIR_MASK_REG_AND                                  , RULL(0x0E010C04), SH_UNT_PEC_1    , SH_ACS_SCOM1_AND );
+REG64( PEC_1_FIR_MASK_REG_OR                                   , RULL(0x0E010C05), SH_UNT_PEC_1    , SH_ACS_SCOM2_OR  );
+REG64( PEC_2_FIR_MASK_REG                                      , RULL(0x0F010C03), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_FIR_MASK_REG_AND                                  , RULL(0x0F010C04), SH_UNT_PEC_2    , SH_ACS_SCOM1_AND );
+REG64( PEC_2_FIR_MASK_REG_OR                                   , RULL(0x0F010C05), SH_UNT_PEC_2    , SH_ACS_SCOM2_OR  );
+
+REG64( PU_FIR_MASK_REGISTER                                    , RULL(0x00088008), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU_MSC_SM0_FIR_MASK_REG_0                           , RULL(0x05011403), SH_UNT_PU_NPU_MSC_SM0,
+       SH_ACS_SCOM_RW   );
+REG64( PU_NPU_MSC_SM0_FIR_MASK_REG_0_AND                       , RULL(0x05011404), SH_UNT_PU_NPU_MSC_SM0,
+       SH_ACS_SCOM1_AND );
+REG64( PU_NPU_MSC_SM0_FIR_MASK_REG_0_OR                        , RULL(0x05011405), SH_UNT_PU_NPU_MSC_SM0,
+       SH_ACS_SCOM2_OR  );
+
+REG64( PU_NPU_MSC_SM2_FIR_MASK_REG_1                           , RULL(0x05011443), SH_UNT_PU_NPU_MSC_SM2,
+       SH_ACS_SCOM_RW   );
+REG64( PU_NPU_MSC_SM2_FIR_MASK_REG_1_AND                       , RULL(0x05011444), SH_UNT_PU_NPU_MSC_SM2,
+       SH_ACS_SCOM1_AND );
+REG64( PU_NPU_MSC_SM2_FIR_MASK_REG_1_OR                        , RULL(0x05011445), SH_UNT_PU_NPU_MSC_SM2,
+       SH_ACS_SCOM2_OR  );
+
+REG64( PU_FIR_REG                                              , RULL(0x04011800), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_FIR_REG_AND                                          , RULL(0x04011801), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_FIR_REG_OR                                           , RULL(0x04011802), SH_UNT          , SH_ACS_SCOM2_OR  );
+REG64( CAPP_FIR_REG                                            , RULL(0x02010800), SH_UNT_CAPP     , SH_ACS_SCOM_RW   );
+REG64( CAPP_FIR_REG_AND                                        , RULL(0x02010801), SH_UNT_CAPP     , SH_ACS_SCOM1_AND );
+REG64( CAPP_FIR_REG_OR                                         , RULL(0x02010802), SH_UNT_CAPP     , SH_ACS_SCOM2_OR  );
+REG64( CAPP_0_FIR_REG                                          , RULL(0x02010800), SH_UNT_CAPP_0   , SH_ACS_SCOM_RW   );
+REG64( CAPP_0_FIR_REG_AND                                      , RULL(0x02010801), SH_UNT_CAPP_0   , SH_ACS_SCOM1_AND );
+REG64( CAPP_0_FIR_REG_OR                                       , RULL(0x02010802), SH_UNT_CAPP_0   , SH_ACS_SCOM2_OR  );
+REG64( CAPP_1_FIR_REG                                          , RULL(0x04010800), SH_UNT_CAPP_1   , SH_ACS_SCOM_RW   );
+REG64( CAPP_1_FIR_REG_AND                                      , RULL(0x04010801), SH_UNT_CAPP_1   , SH_ACS_SCOM1_AND );
+REG64( CAPP_1_FIR_REG_OR                                       , RULL(0x04010802), SH_UNT_CAPP_1   , SH_ACS_SCOM2_OR  );
+
+REG64( PHB_FIR_REG                                             , RULL(0x0D010908), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_FIR_REG_AND                                         , RULL(0x0D010909), SH_UNT_PHB      , SH_ACS_SCOM1_AND );
+REG64( PHB_FIR_REG_OR                                          , RULL(0x0D01090A), SH_UNT_PHB      , SH_ACS_SCOM2_OR  );
+REG64( PHB_0_FIR_REG                                           , RULL(0x0D010908), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_0_FIR_REG_AND                                       , RULL(0x0D010909), SH_UNT_PHB_0    , SH_ACS_SCOM1_AND );
+REG64( PHB_0_FIR_REG_OR                                        , RULL(0x0D01090A), SH_UNT_PHB_0    , SH_ACS_SCOM2_OR  );
+REG64( PHB_1_FIR_REG                                           , RULL(0x0E010908), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_FIR_REG_AND                                       , RULL(0x0E010909), SH_UNT_PHB_1    , SH_ACS_SCOM1_AND );
+REG64( PHB_1_FIR_REG_OR                                        , RULL(0x0E01090A), SH_UNT_PHB_1    , SH_ACS_SCOM2_OR  );
+REG64( PHB_2_FIR_REG                                           , RULL(0x0E010948), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_FIR_REG_AND                                       , RULL(0x0E010949), SH_UNT_PHB_2    , SH_ACS_SCOM1_AND );
+REG64( PHB_2_FIR_REG_OR                                        , RULL(0x0E01094A), SH_UNT_PHB_2    , SH_ACS_SCOM2_OR  );
+REG64( PHB_3_FIR_REG                                           , RULL(0x0F010908), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_FIR_REG_AND                                       , RULL(0x0F010909), SH_UNT_PHB_3    , SH_ACS_SCOM1_AND );
+REG64( PHB_3_FIR_REG_OR                                        , RULL(0x0F01090A), SH_UNT_PHB_3    , SH_ACS_SCOM2_OR  );
+REG64( PHB_4_FIR_REG                                           , RULL(0x0F010948), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_FIR_REG_AND                                       , RULL(0x0F010949), SH_UNT_PHB_4    , SH_ACS_SCOM1_AND );
+REG64( PHB_4_FIR_REG_OR                                        , RULL(0x0F01094A), SH_UNT_PHB_4    , SH_ACS_SCOM2_OR  );
+REG64( PHB_5_FIR_REG                                           , RULL(0x0F010988), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_FIR_REG_AND                                       , RULL(0x0F010989), SH_UNT_PHB_5    , SH_ACS_SCOM1_AND );
+REG64( PHB_5_FIR_REG_OR                                        , RULL(0x0F01098A), SH_UNT_PHB_5    , SH_ACS_SCOM2_OR  );
+
+REG64( PU_NPU_MSC_SM0_FIR_REG_0                                , RULL(0x05011400), SH_UNT_PU_NPU_MSC_SM0,
+       SH_ACS_SCOM_RW   );
+REG64( PU_NPU_MSC_SM0_FIR_REG_0_AND                            , RULL(0x05011401), SH_UNT_PU_NPU_MSC_SM0,
+       SH_ACS_SCOM1_AND );
+REG64( PU_NPU_MSC_SM0_FIR_REG_0_OR                             , RULL(0x05011402), SH_UNT_PU_NPU_MSC_SM0,
+       SH_ACS_SCOM2_OR  );
+
+REG64( PU_NPU_MSC_SM2_FIR_REG_1                                , RULL(0x05011440), SH_UNT_PU_NPU_MSC_SM2,
+       SH_ACS_SCOM_RW   );
+REG64( PU_NPU_MSC_SM2_FIR_REG_1_AND                            , RULL(0x05011441), SH_UNT_PU_NPU_MSC_SM2,
+       SH_ACS_SCOM1_AND );
+REG64( PU_NPU_MSC_SM2_FIR_REG_1_OR                             , RULL(0x05011442), SH_UNT_PU_NPU_MSC_SM2,
+       SH_ACS_SCOM2_OR  );
+
+REG64( PEC_FIR_STATUS_REG                                      , RULL(0x0D010C00), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_FIR_STATUS_REG_AND                                  , RULL(0x0D010C01), SH_UNT_PEC      , SH_ACS_SCOM1_AND );
+REG64( PEC_FIR_STATUS_REG_OR                                   , RULL(0x0D010C02), SH_UNT_PEC      , SH_ACS_SCOM2_OR  );
+REG64( PEC_0_FIR_STATUS_REG                                    , RULL(0x0D010C00), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_0_FIR_STATUS_REG_AND                                , RULL(0x0D010C01), SH_UNT_PEC_0    , SH_ACS_SCOM1_AND );
+REG64( PEC_0_FIR_STATUS_REG_OR                                 , RULL(0x0D010C02), SH_UNT_PEC_0    , SH_ACS_SCOM2_OR  );
+REG64( PEC_1_FIR_STATUS_REG                                    , RULL(0x0E010C00), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_FIR_STATUS_REG_AND                                , RULL(0x0E010C01), SH_UNT_PEC_1    , SH_ACS_SCOM1_AND );
+REG64( PEC_1_FIR_STATUS_REG_OR                                 , RULL(0x0E010C02), SH_UNT_PEC_1    , SH_ACS_SCOM2_OR  );
+REG64( PEC_2_FIR_STATUS_REG                                    , RULL(0x0F010C00), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_FIR_STATUS_REG_AND                                , RULL(0x0F010C01), SH_UNT_PEC_2    , SH_ACS_SCOM1_AND );
+REG64( PEC_2_FIR_STATUS_REG_OR                                 , RULL(0x0F010C02), SH_UNT_PEC_2    , SH_ACS_SCOM2_OR  );
+
+REG64( PU_FIR_WOF_REG                                          , RULL(0x04011808), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PEC_FIR_WOF_REG                                         , RULL(0x0D010C08), SH_UNT_PEC      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PEC_0_FIR_WOF_REG                                       , RULL(0x0D010C08), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PEC_1_FIR_WOF_REG                                       , RULL(0x0E010C08), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PEC_2_FIR_WOF_REG                                       , RULL(0x0F010C08), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_NPU_MSC_SM0_FIR_WOF_REG_0                            , RULL(0x05011408), SH_UNT_PU_NPU_MSC_SM0,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_NPU_MSC_SM2_FIR_WOF_REG_1                            , RULL(0x05011448), SH_UNT_PU_NPU_MSC_SM2,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( CAPP_FLUSHCPIG                                          , RULL(0x02010820), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_FLUSHCPIG                                        , RULL(0x02010820), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_FLUSHCPIG                                        , RULL(0x04010820), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_FLUSHSHUE                                          , RULL(0x0201080F), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_FLUSHSHUE                                        , RULL(0x0201080F), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_FLUSHSHUE                                        , RULL(0x0401080F), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( PU_FORCE_ECC_REG                                        , RULL(0x0009000D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU_CTL_FREEZE_0_CONFIG                              , RULL(0x05011388), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_FREEZE_1_CONFIG                              , RULL(0x05011389), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_FREEZE_STATE                                 , RULL(0x05011395), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_FSB_DOWNFIFO_DATA_IN                                 , RULL(0x000B0010), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_FSB_DOWNFIFO_REQ_RESET                               , RULL(0x000B0013), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_FSB_DOWNFIFO_SIG_EOT                                 , RULL(0x000B0012), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_FSB_DOWNFIFO_STATUS                                  , RULL(0x000B0011), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_FSB_UPFIFO_ACK_EOT                                   , RULL(0x000B0005), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_FSB_UPFIFO_DATA_OUT                                  , RULL(0x000B0000), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_FSB_UPFIFO_RESET                                     , RULL(0x000B0004), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_FSB_UPFIFO_STATUS                                    , RULL(0x000B0001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_GENID_BAR                                   , RULL(0x05011007), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_GENID_BAR                                   , RULL(0x05011027), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_GENID_BAR                                   , RULL(0x05011047), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_GENID_BAR                                   , RULL(0x05011067), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_GENID_BAR                                   , RULL(0x05011107), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_GENID_BAR                                   , RULL(0x05011127), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_GENID_BAR                                   , RULL(0x05011147), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_GENID_BAR                                   , RULL(0x05011167), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_GENID_BAR                                   , RULL(0x05011207), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_GENID_BAR                                   , RULL(0x05011227), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_GENID_BAR                                   , RULL(0x05011247), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_GENID_BAR                                   , RULL(0x05011267), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_GPE0_GPEDBG_OCI                                      , RULL(0xC0000010), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEDBG_SCOM                                     , RULL(0x00060002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_GPEIVPR_OCI                                     , RULL(0xC0000008), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEIVPR_SCOM                                    , RULL(0x00060001), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_GPEMACR_OCI                                     , RULL(0xC0000020), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEMACR_SCOM                                    , RULL(0x00060004), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_GPENXIXCR_OCI                                   , RULL(0xC0000080), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE0_GPENXIXCR_SCOM                                  , RULL(0x00060010), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE0_GPESTR_OCI                                      , RULL(0xC0000018), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE0_GPESTR_SCOM                                     , RULL(0x00060003), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_GPETSEL_OCI                                     , RULL(0xC0000000), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE0_GPETSEL_SCOM                                    , RULL(0x00060000), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_GPEXIEDR_OCI                                    , RULL(0xC0000118), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEXIEDR_SCOM                                   , RULL(0x00060023), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_GPEXIIAR_OCI                                    , RULL(0xC0000128), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEXIIAR_SCOM                                   , RULL(0x00060025), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_GPEXIIR_OCI                                     , RULL(0xC0000120), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEXIIR_SCOM                                    , RULL(0x00060024), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_GPEXISPRG0_OCI                                  , RULL(0xC0000110), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEXISPRG0_SCOM                                 , RULL(0x00060022), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE0_GPEXIXCR_OCI                                    , RULL(0xC0000100), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEXIXCR_SCOM                                   , RULL(0x00060020), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE0_GPEXIXSR_OCI                                    , RULL(0xC0000108), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE0_GPEXIXSR_SCOM                                   , RULL(0x00060021), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_MIB_XIDCAC_OCI                                  , RULL(0xC00000D0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE0_MIB_XIDCAC_SCOM                                 , RULL(0x0006001A), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_MIB_XIICAC                                      , RULL(0x00060019), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_MIB_XIMEM                                       , RULL(0x00060017), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_MIB_XISGB                                       , RULL(0x00060018), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE0_PPE_XIDBGPRO                                    , RULL(0x00060015), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_PPE_XIRAMDBG                                    , RULL(0x00060013), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_PPE_XIRAMEDR                                    , RULL(0x00060014), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE0_PPE_XIRAMGA                                     , RULL(0x00060012), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE0_PPE_XIRAMRA                                     , RULL(0x00060011), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE0_PPE_XIXCR                                       , RULL(0x00060010), SH_UNT          ,
+       SH_ACS_SCOM_WO   ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_GPE1_GPEDBG_OCI                                      , RULL(0xC0010010), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEDBG_SCOM                                     , RULL(0x00062002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE1_GPEIVPR_OCI                                     , RULL(0xC0010008), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEIVPR_SCOM                                    , RULL(0x00062001), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_GPEMACR_OCI                                     , RULL(0xC0010020), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEMACR_SCOM                                    , RULL(0x00062004), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_GPENXIXCR_OCI                                   , RULL(0xC0010080), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE1_GPENXIXCR_SCOM                                  , RULL(0x00062010), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE1_GPESTR_OCI                                      , RULL(0xC0010018), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE1_GPESTR_SCOM                                     , RULL(0x00062003), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_GPETSEL_OCI                                     , RULL(0xC0010000), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE1_GPETSEL_SCOM                                    , RULL(0x00062000), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_GPEXIEDR_OCI                                    , RULL(0xC0010118), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEXIEDR_SCOM                                   , RULL(0x00062023), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_GPEXIIAR_OCI                                    , RULL(0xC0010128), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEXIIAR_SCOM                                   , RULL(0x00062025), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_GPEXIIR_OCI                                     , RULL(0xC0010120), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEXIIR_SCOM                                    , RULL(0x00062024), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_GPEXISPRG0_OCI                                  , RULL(0xC0010110), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEXISPRG0_SCOM                                 , RULL(0x00062022), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE1_GPEXIXCR_OCI                                    , RULL(0xC0010100), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEXIXCR_SCOM                                   , RULL(0x00062020), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE1_GPEXIXSR_OCI                                    , RULL(0xC0010108), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE1_GPEXIXSR_SCOM                                   , RULL(0x00062021), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_MIB_XIDCAC_OCI                                  , RULL(0xC00100D0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE1_MIB_XIDCAC_SCOM                                 , RULL(0x0006201A), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_MIB_XIICAC                                      , RULL(0x00062019), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_MIB_XIMEM                                       , RULL(0x00062017), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_MIB_XISGB                                       , RULL(0x00062018), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE1_PPE_XIDBGPRO                                    , RULL(0x00062015), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE1_PPE_XIRAMDBG                                    , RULL(0x00062013), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE1_PPE_XIRAMEDR                                    , RULL(0x00062014), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE1_PPE_XIRAMGA                                     , RULL(0x00062012), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE1_PPE_XIRAMRA                                     , RULL(0x00062011), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE1_PPE_XIXCR                                       , RULL(0x00062010), SH_UNT          ,
+       SH_ACS_SCOM_WO   ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_GPE2_GPEDBG_OCI                                      , RULL(0xC0020010), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEDBG_SCOM                                     , RULL(0x00064002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE2_GPEIVPR_OCI                                     , RULL(0xC0020008), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEIVPR_SCOM                                    , RULL(0x00064001), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE2_GPEMACR_OCI                                     , RULL(0xC0020020), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEMACR_SCOM                                    , RULL(0x00064004), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE2_GPENXIXCR_OCI                                   , RULL(0xC0020080), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE2_GPENXIXCR_SCOM                                  , RULL(0x00064010), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE2_GPESTR_OCI                                      , RULL(0xC0020018), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE2_GPESTR_SCOM                                     , RULL(0x00064003), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE2_GPETSEL_OCI                                     , RULL(0xC0020000), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE2_GPETSEL_SCOM                                    , RULL(0x00064000), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE2_GPEXIEDR_OCI                                    , RULL(0xC0020118), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEXIEDR_SCOM                                   , RULL(0x00064023), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE2_GPEXIIAR_OCI                                    , RULL(0xC0020128), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEXIIAR_SCOM                                   , RULL(0x00064025), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE2_GPEXIIR_OCI                                     , RULL(0xC0020120), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEXIIR_SCOM                                    , RULL(0x00064024), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE2_GPEXISPRG0_OCI                                  , RULL(0xC0020110), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEXISPRG0_SCOM                                 , RULL(0x00064022), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE2_GPEXIXCR_OCI                                    , RULL(0xC0020100), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEXIXCR_SCOM                                   , RULL(0x00064020), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE2_GPEXIXSR_OCI                                    , RULL(0xC0020108), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE2_GPEXIXSR_SCOM                                   , RULL(0x00064021), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE2_MIB_XIDCAC_OCI                                  , RULL(0xC00200D0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE2_MIB_XIDCAC_SCOM                                 , RULL(0x0006401A), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE2_MIB_XIICAC                                      , RULL(0x00064019), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE2_MIB_XIMEM                                       , RULL(0x00064017), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE2_MIB_XISGB                                       , RULL(0x00064018), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE2_PPE_XIDBGPRO                                    , RULL(0x00064015), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE2_PPE_XIRAMDBG                                    , RULL(0x00064013), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE2_PPE_XIRAMEDR                                    , RULL(0x00064014), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE2_PPE_XIRAMGA                                     , RULL(0x00064012), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE2_PPE_XIRAMRA                                     , RULL(0x00064011), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE2_PPE_XIXCR                                       , RULL(0x00064010), SH_UNT          ,
+       SH_ACS_SCOM_WO   ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_GPE3_GPEDBG_OCI                                      , RULL(0xC0030010), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEDBG_SCOM                                     , RULL(0x00066002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE3_GPEIVPR_OCI                                     , RULL(0xC0030008), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEIVPR_SCOM                                    , RULL(0x00066001), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE3_GPEMACR_OCI                                     , RULL(0xC0030020), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEMACR_SCOM                                    , RULL(0x00066004), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE3_GPENXIXCR_OCI                                   , RULL(0xC0030080), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE3_GPENXIXCR_SCOM                                  , RULL(0x00066010), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE3_GPESTR_OCI                                      , RULL(0xC0030018), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE3_GPESTR_SCOM                                     , RULL(0x00066003), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE3_GPETSEL_OCI                                     , RULL(0xC0030000), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE3_GPETSEL_SCOM                                    , RULL(0x00066000), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE3_GPEXIEDR_OCI                                    , RULL(0xC0030118), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEXIEDR_SCOM                                   , RULL(0x00066023), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE3_GPEXIIAR_OCI                                    , RULL(0xC0030128), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEXIIAR_SCOM                                   , RULL(0x00066025), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE3_GPEXIIR_OCI                                     , RULL(0xC0030120), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEXIIR_SCOM                                    , RULL(0x00066024), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE3_GPEXISPRG0_OCI                                  , RULL(0xC0030110), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEXISPRG0_SCOM                                 , RULL(0x00066022), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_GPE3_GPEXIXCR_OCI                                    , RULL(0xC0030100), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEXIXCR_SCOM                                   , RULL(0x00066020), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE3_GPEXIXSR_OCI                                    , RULL(0xC0030108), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE3_GPEXIXSR_SCOM                                   , RULL(0x00066021), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE3_MIB_XIDCAC_OCI                                  , RULL(0xC00300D0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_GPE3_MIB_XIDCAC_SCOM                                 , RULL(0x0006601A), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE3_MIB_XIICAC                                      , RULL(0x00066019), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE3_MIB_XIMEM                                       , RULL(0x00066017), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE3_MIB_XISGB                                       , RULL(0x00066018), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_GPE3_PPE_XIDBGPRO                                    , RULL(0x00066015), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE3_PPE_XIRAMDBG                                    , RULL(0x00066013), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE3_PPE_XIRAMEDR                                    , RULL(0x00066014), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GPE3_PPE_XIRAMGA                                     , RULL(0x00066012), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE3_PPE_XIRAMRA                                     , RULL(0x00066011), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_GPE3_PPE_XIXCR                                       , RULL(0x00066010), SH_UNT          ,
+       SH_ACS_SCOM_WO   ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_NPU0_SM0_GPU_BAR                                     , RULL(0x05011004), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_GPU_BAR                                     , RULL(0x05011024), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_GPU_BAR                                     , RULL(0x05011044), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_GPU_BAR                                     , RULL(0x05011064), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_GPU_BAR                                     , RULL(0x05011104), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_GPU_BAR                                     , RULL(0x05011124), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_GPU_BAR                                     , RULL(0x05011144), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_GPU_BAR                                     , RULL(0x05011164), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_GPU_BAR                                     , RULL(0x05011204), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_GPU_BAR                                     , RULL(0x05011224), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_GPU_BAR                                     , RULL(0x05011244), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_GPU_BAR                                     , RULL(0x05011264), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PEC_GXSTOP0_MASK_REG                                    , RULL(0x0D040014), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_GXSTOP0_MASK_REG                                  , RULL(0x0D040014), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_GXSTOP0_MASK_REG                                  , RULL(0x0E040014), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_GXSTOP0_MASK_REG                                  , RULL(0x0F040014), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_GXSTOP1_MASK_REG                                    , RULL(0x0D040015), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_GXSTOP1_MASK_REG                                  , RULL(0x0D040015), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_GXSTOP1_MASK_REG                                  , RULL(0x0E040015), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_GXSTOP1_MASK_REG                                  , RULL(0x0F040015), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_GXSTOP2_MASK_REG                                    , RULL(0x0D040016), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_GXSTOP2_MASK_REG                                  , RULL(0x0D040016), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_GXSTOP2_MASK_REG                                  , RULL(0x0E040016), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_GXSTOP2_MASK_REG                                  , RULL(0x0F040016), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_GXSTOP_TRIG_REG                                     , RULL(0x0D040013), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_GXSTOP_TRIG_REG                                   , RULL(0x0D040013), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_GXSTOP_TRIG_REG                                   , RULL(0x0E040013), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_GXSTOP_TRIG_REG                                   , RULL(0x0F040013), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_CONTROL_REG                                     , RULL(0x02011140), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_ERRRPT_HOLD_REG                                 , RULL(0x02011152), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB                           , RULL(0x020110C8), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_HI_PRIOR_RCV_FIFO_BAR                           , RULL(0x020110C2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL                          , RULL(0x020110C5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB                           , RULL(0x020110D1), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_LO_PRIOR_RCV_FIFO_BAR                           , RULL(0x020110CB), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL                          , RULL(0x020110CE), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_GZIP_MAX_BYTE_CNT                                    , RULL(0x0201105B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PEC_HANG_PULSE_0_REG                                    , RULL(0x0D0F0020), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_HANG_PULSE_0_REG                                  , RULL(0x0D0F0020), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_HANG_PULSE_0_REG                                  , RULL(0x0E0F0020), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_HANG_PULSE_0_REG                                  , RULL(0x0F0F0020), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_HANG_PULSE_1_REG                                    , RULL(0x0D0F0021), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_HANG_PULSE_1_REG                                  , RULL(0x0D0F0021), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_HANG_PULSE_1_REG                                  , RULL(0x0E0F0021), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_HANG_PULSE_1_REG                                  , RULL(0x0F0F0021), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_HANG_PULSE_2_REG                                    , RULL(0x0D0F0022), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_HANG_PULSE_2_REG                                  , RULL(0x0D0F0022), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_HANG_PULSE_2_REG                                  , RULL(0x0E0F0022), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_HANG_PULSE_2_REG                                  , RULL(0x0F0F0022), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_HANG_PULSE_3_REG                                    , RULL(0x0D0F0023), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_HANG_PULSE_3_REG                                  , RULL(0x0D0F0023), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_HANG_PULSE_3_REG                                  , RULL(0x0E0F0023), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_HANG_PULSE_3_REG                                  , RULL(0x0F0F0023), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_HANG_PULSE_4_REG                                    , RULL(0x0D0F0024), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_HANG_PULSE_4_REG                                  , RULL(0x0D0F0024), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_HANG_PULSE_4_REG                                  , RULL(0x0E0F0024), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_HANG_PULSE_4_REG                                  , RULL(0x0F0F0024), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_HANG_PULSE_5_REG                                    , RULL(0x0D0F0025), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_HANG_PULSE_5_REG                                  , RULL(0x0D0F0025), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_HANG_PULSE_5_REG                                  , RULL(0x0E0F0025), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_HANG_PULSE_5_REG                                  , RULL(0x0F0F0025), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_HANG_PULSE_6_REG                                    , RULL(0x0D0F0026), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_HANG_PULSE_6_REG                                  , RULL(0x0D0F0026), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_HANG_PULSE_6_REG                                  , RULL(0x0E0F0026), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_HANG_PULSE_6_REG                                  , RULL(0x0F0F0026), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PU_HCA_BAR                                              , RULL(0x0501298A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_HCA_COUNT_BAR                                        , RULL(0x0501298B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_HCA_DROP                                             , RULL(0x05012991), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_HCA_FLUSH                                            , RULL(0x05012990), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_HCA_MIRROR_BAR                                       , RULL(0x05012993), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_HCA_MODES                                            , RULL(0x0501298F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_HCA_REF_BAR                                          , RULL(0x0501298E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_HCA_RESET                                            , RULL(0x05012992), SH_UNT          , SH_ACS_SCOM_W    );
+
+REG64( PEC_HEARTBEAT_REG                                       , RULL(0x0D0F0018), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_HEARTBEAT_REG                                     , RULL(0x0D0F0018), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_HEARTBEAT_REG                                     , RULL(0x0E0F0018), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_HEARTBEAT_REG                                     , RULL(0x0F0F0018), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_HIGH_WATER                                  , RULL(0x05011009), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_HIGH_WATER                                  , RULL(0x05011029), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_HIGH_WATER                                  , RULL(0x05011049), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_HIGH_WATER                                  , RULL(0x05011069), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_HIGH_WATER                                  , RULL(0x05011109), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_HIGH_WATER                                  , RULL(0x05011129), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_HIGH_WATER                                  , RULL(0x05011149), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_HIGH_WATER                                  , RULL(0x05011169), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_HIGH_WATER                                  , RULL(0x05011209), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_HIGH_WATER                                  , RULL(0x05011229), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_HIGH_WATER                                  , RULL(0x05011249), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_HIGH_WATER                                  , RULL(0x05011269), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PEC_HOSTATTN                                            , RULL(0x0D040009), SH_UNT_PEC      , SH_ACS_SCOM_RO   );
+REG64( PEC_0_HOSTATTN                                          , RULL(0x0D040009), SH_UNT_PEC_0    , SH_ACS_SCOM_RO   );
+REG64( PEC_1_HOSTATTN                                          , RULL(0x0E040009), SH_UNT_PEC_1    , SH_ACS_SCOM_RO   );
+REG64( PEC_2_HOSTATTN                                          , RULL(0x0F040009), SH_UNT_PEC_2    , SH_ACS_SCOM_RO   );
+
+REG64( PEC_HOSTATTN_MASK                                       , RULL(0x0D04001A), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_HOSTATTN_MASK                                     , RULL(0x0D04001A), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_HOSTATTN_MASK                                     , RULL(0x0E04001A), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_HOSTATTN_MASK                                     , RULL(0x0F04001A), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_HTM0_HTM_CFG                                         , RULL(0x05012888), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_CFG                                         , RULL(0x050128C8), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_HTM0_HTM_CTRL                                        , RULL(0x05012885), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_CTRL                                        , RULL(0x050128C5), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_HTM0_HTM_FILT                                        , RULL(0x05012886), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_FILT                                        , RULL(0x050128C6), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_HTM0_HTM_FLEX                                        , RULL(0x05012889), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_FLEX                                        , RULL(0x050128C9), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_HTM0_HTM_LAST                                        , RULL(0x05012883), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO   );
+REG64( PU_HTM1_HTM_LAST                                        , RULL(0x050128C3), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO   );
+
+REG64( PU_HTM0_HTM_MEM                                         , RULL(0x05012881), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_MEM                                         , RULL(0x050128C1), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_HTM0_HTM_MODE                                        , RULL(0x05012880), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_MODE                                        , RULL(0x050128C0), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_HTM0_HTM_STAT                                        , RULL(0x05012882), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO   );
+REG64( PU_HTM1_HTM_STAT                                        , RULL(0x050128C2), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO   );
+
+REG64( PU_HTM0_HTM_TRIG                                        , RULL(0x05012884), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_TRIG                                        , RULL(0x050128C4), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_HTM0_HTM_TTYPEFILT                                   , RULL(0x05012887), SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW   );
+REG64( PU_HTM1_HTM_TTYPEFILT                                   , RULL(0x050128C7), SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_I2C_BUSY_REGISTER_B                                  , RULL(0x000A000E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_I2C_BUSY_REGISTER_C                                  , RULL(0x000A100E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_I2C_BUSY_REGISTER_D                                  , RULL(0x000A200E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_I2C_BUSY_REGISTER_E                                  , RULL(0x000A300E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_ERR_B                                      , RULL(0x000A000C), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_IMM_RESET_ERR_C                                      , RULL(0x000A100C), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_IMM_RESET_ERR_D                                      , RULL(0x000A200C), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_IMM_RESET_ERR_E                                      , RULL(0x000A300C), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_IMM_RESET_I2C_B                                      , RULL(0x000A000B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_I2C_C                                      , RULL(0x000A100B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_I2C_D                                      , RULL(0x000A200B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_I2C_E                                      , RULL(0x000A300B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SCL_B                                    , RULL(0x000A000F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SCL_C                                    , RULL(0x000A100F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SCL_D                                    , RULL(0x000A200F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SCL_E                                    , RULL(0x000A300F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SDA_B                                    , RULL(0x000A0011), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SDA_C                                    , RULL(0x000A1011), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SDA_D                                    , RULL(0x000A2011), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_RESET_S_SDA_E                                    , RULL(0x000A3011), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SCL_B                                      , RULL(0x000A000D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SCL_C                                      , RULL(0x000A100D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SCL_D                                      , RULL(0x000A200D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SCL_E                                      , RULL(0x000A300D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SDA_B                                      , RULL(0x000A0010), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SDA_C                                      , RULL(0x000A1010), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SDA_D                                      , RULL(0x000A2010), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_IMM_SET_S_SDA_E                                      , RULL(0x000A3010), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_INHIBIT_CONFIG                              , RULL(0x05011091), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_INHIBIT_CONFIG                              , RULL(0x05011191), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_INHIBIT_CONFIG                              , RULL(0x05011291), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_INHIBIT_CONFIG                              , RULL(0x05011010), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_INHIBIT_CONFIG                              , RULL(0x05011030), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_INHIBIT_CONFIG                              , RULL(0x05011050), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_INHIBIT_CONFIG                              , RULL(0x05011070), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_INHIBIT_CONFIG                              , RULL(0x05011110), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_INHIBIT_CONFIG                              , RULL(0x05011130), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_INHIBIT_CONFIG                              , RULL(0x05011150), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_INHIBIT_CONFIG                              , RULL(0x05011170), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_INHIBIT_CONFIG                              , RULL(0x05011210), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_INHIBIT_CONFIG                              , RULL(0x05011230), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_INHIBIT_CONFIG                              , RULL(0x05011250), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_INHIBIT_CONFIG                              , RULL(0x05011270), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU_CTL_INHIBIT_CONFIG                               , RULL(0x05011387), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PEC_INJECT_REG                                          , RULL(0x0D050011), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_INJECT_REG                                        , RULL(0x0D050011), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_INJECT_REG                                        , RULL(0x0E050011), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_INJECT_REG                                        , RULL(0x0F050011), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_0_STACK0_INTBAR_REG                                 , RULL(0x04010C53), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_0_STACK1_INTBAR_REG                                 , RULL(0x04010C93), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_0_STACK2_INTBAR_REG                                 , RULL(0x04010CD3), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK0_INTBAR_REG                                 , RULL(0x04011053), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK1_INTBAR_REG                                 , RULL(0x04011093), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK2_INTBAR_REG                                 , RULL(0x040110D3), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK0_INTBAR_REG                                 , RULL(0x04011453), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK1_INTBAR_REG                                 , RULL(0x04011493), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK2_INTBAR_REG                                 , RULL(0x040114D3), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK0_INTBAR_REG                                   , RULL(0x04010C53), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK1_INTBAR_REG                                   , RULL(0x04010C93), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK2_INTBAR_REG                                   , RULL(0x04010CD3), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM      );
+REG64( PHB_INTBAR_REG                                          , RULL(0x04010C53), SH_UNT_PHB      , SH_ACS_SCOM      );
+REG64( PHB_0_INTBAR_REG                                        , RULL(0x04010C53), SH_UNT_PHB_0    , SH_ACS_SCOM      );
+REG64( PHB_1_INTBAR_REG                                        , RULL(0x04011053), SH_UNT_PHB_1    , SH_ACS_SCOM      );
+REG64( PHB_2_INTBAR_REG                                        , RULL(0x04011093), SH_UNT_PHB_2    , SH_ACS_SCOM      );
+REG64( PHB_3_INTBAR_REG                                        , RULL(0x04011453), SH_UNT_PHB_3    , SH_ACS_SCOM      );
+REG64( PHB_4_INTBAR_REG                                        , RULL(0x04011493), SH_UNT_PHB_4    , SH_ACS_SCOM      );
+REG64( PHB_5_INTBAR_REG                                        , RULL(0x040114D3), SH_UNT_PHB_5    , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPTS_B                                         , RULL(0x000A000A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPTS_C                                         , RULL(0x000A100A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPTS_D                                         , RULL(0x000A200A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPTS_E                                         , RULL(0x000A300A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_COND_B                                     , RULL(0x000A0009), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_COND_C                                     , RULL(0x000A1009), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_COND_D                                     , RULL(0x000A2009), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_COND_E                                     , RULL(0x000A3009), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_B_WO                         , RULL(0x000A0008), SH_UNT          , SH_ACS_SCOM_WO   );
+REG64( PU_INTERRUPT_MASK_REGISTER_B_OR                         , RULL(0x000A0009), SH_UNT          , SH_ACS_SCOM1_OR  );
+REG64( PU_INTERRUPT_MASK_REGISTER_B_AND                        , RULL(0x000A000A), SH_UNT          , SH_ACS_SCOM2_AND );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_C_WO                         , RULL(0x000A1008), SH_UNT          , SH_ACS_SCOM_WO   );
+REG64( PU_INTERRUPT_MASK_REGISTER_C_OR                         , RULL(0x000A1009), SH_UNT          , SH_ACS_SCOM1_OR  );
+REG64( PU_INTERRUPT_MASK_REGISTER_C_AND                        , RULL(0x000A100A), SH_UNT          , SH_ACS_SCOM2_AND );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_D_WO                         , RULL(0x000A2008), SH_UNT          , SH_ACS_SCOM_WO   );
+REG64( PU_INTERRUPT_MASK_REGISTER_D_OR                         , RULL(0x000A2009), SH_UNT          , SH_ACS_SCOM1_OR  );
+REG64( PU_INTERRUPT_MASK_REGISTER_D_AND                        , RULL(0x000A200A), SH_UNT          , SH_ACS_SCOM2_AND );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_E_WO                         , RULL(0x000A3008), SH_UNT          , SH_ACS_SCOM_WO   );
+REG64( PU_INTERRUPT_MASK_REGISTER_E_OR                         , RULL(0x000A3009), SH_UNT          , SH_ACS_SCOM1_OR  );
+REG64( PU_INTERRUPT_MASK_REGISTER_E_AND                        , RULL(0x000A300A), SH_UNT          , SH_ACS_SCOM2_AND );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_READ_B                       , RULL(0x000A0008), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_READ_C                       , RULL(0x000A1008), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_READ_D                       , RULL(0x000A2008), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INTERRUPT_MASK_REGISTER_READ_E                       , RULL(0x000A3008), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_INT_0_CONFIG                                 , RULL(0x0501138C), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_INT_1_CONFIG                                 , RULL(0x0501138D), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_INT_BAR                                      , RULL(0x05011393), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_INT_CQ_ACTION0                                       , RULL(0x05013036), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_ACTION1                                       , RULL(0x05013037), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_AIB_CTL                                       , RULL(0x05013022), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_CQ_CFG_LDQ                                       , RULL(0x05013026), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_CFG_PB_GEN                                    , RULL(0x0501300A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_CQ_CFG_STQ1                                      , RULL(0x05013024), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_CFG_STQ2                                      , RULL(0x05013025), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_CNPM_SEL                                      , RULL(0x0501300F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_ERR_INFO0                                     , RULL(0x0501303A), SH_UNT          ,
+       SH_ACS_SCOM_WCLRPART );
+
+REG64( PU_INT_CQ_ERR_INFO1                                     , RULL(0x0501303B), SH_UNT          ,
+       SH_ACS_SCOM_WCLRPART );
+
+REG64( PU_INT_CQ_ERR_INFO2                                     , RULL(0x0501303C), SH_UNT          ,
+       SH_ACS_SCOM_WCLRPART );
+
+REG64( PU_INT_CQ_ERR_INFO3                                     , RULL(0x0501303D), SH_UNT          ,
+       SH_ACS_SCOM_WCLRPART );
+
+REG64( PU_INT_CQ_ERR_RPT_HOLD                                  , RULL(0x05013039), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_CQ_FIR                                           , RULL(0x05013030), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_FIRMASK                                       , RULL(0x05013033), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_IC_BAR                                        , RULL(0x05013010), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_MSGSND                                        , RULL(0x0501300B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_PBI_CTL                                       , RULL(0x05013020), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_CQ_PBO_CTL                                       , RULL(0x05013021), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_CQ_PC_BAR                                        , RULL(0x05013016), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_PC_BARM                                       , RULL(0x05013017), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_PMC_0                                         , RULL(0x05013028), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_CQ_PMC_1                                         , RULL(0x05013029), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_CQ_PMC_2                                         , RULL(0x0501302A), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_CQ_PMC_3                                         , RULL(0x0501302B), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_CQ_PMC_4                                         , RULL(0x0501302C), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_CQ_PMC_5                                         , RULL(0x0501302D), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_CQ_PMC_6                                         , RULL(0x0501302E), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_CQ_PMC_7                                         , RULL(0x0501302F), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_CQ_PM_CTL                                        , RULL(0x05013027), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_CQ_RST_CTL                                       , RULL(0x05013023), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_CQ_SWI_RSP                                       , RULL(0x05013009), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_CQ_TAR                                           , RULL(0x0501301E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_TM1_BAR                                       , RULL(0x05013012), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_TM2_BAR                                       , RULL(0x05013014), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_VC_BAR                                        , RULL(0x05013018), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_CQ_VC_BARM                                       , RULL(0x05013019), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE0                                 , RULL(0x050113E0), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE1                                 , RULL(0x050113E1), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE10                                , RULL(0x050113EA), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE11                                , RULL(0x050113EB), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE12                                , RULL(0x050113EC), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE13                                , RULL(0x050113ED), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE14                                , RULL(0x050113EE), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE15                                , RULL(0x050113EF), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE2                                 , RULL(0x050113E2), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE3                                 , RULL(0x050113E3), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE4                                 , RULL(0x050113E4), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE5                                 , RULL(0x050113E5), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE6                                 , RULL(0x050113E6), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE7                                 , RULL(0x050113E7), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE8                                 , RULL(0x050113E8), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL1_INT_LOG_PE9                                 , RULL(0x050113E9), SH_UNT_PU_NPU_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_INT_PC_AIB_RX_CRD_CMD                                , RULL(0x05013121), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_AIB_RX_CRD_DAT                                , RULL(0x05013122), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_AIB_RX_CRD_INIT                               , RULL(0x05013120), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_AIB_TX_CRD                                    , RULL(0x05013124), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_AIB_TX_ORDER                                  , RULL(0x05013126), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_AIB_TX_PRIO                                   , RULL(0x05013125), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_AT_KILL                                       , RULL(0x05013116), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_AT_KILL_MASK                                  , RULL(0x05013117), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_DBG_ECC                                       , RULL(0x05013131), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_DBG_PMC                                       , RULL(0x05013134), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_DBG_PMC_ATX0                                  , RULL(0x05013135), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_DBG_PMC_ATX1                                  , RULL(0x05013136), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_DBG_PMC_ATX2                                  , RULL(0x05013137), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_DBG_TMOT                                      , RULL(0x05013130), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_DBG_TRACE                                     , RULL(0x05013133), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_EQD_BLOCK_MODE                                , RULL(0x05013114), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_ERR0_CFG0                                     , RULL(0x05013140), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_ERR0_CFG1                                     , RULL(0x05013141), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_ERR0_FATAL                                    , RULL(0x05013144), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_ERR0_INFO                                     , RULL(0x05013146), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_ERR0_RECOV                                    , RULL(0x05013145), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_ERR0_WOF                                      , RULL(0x05013142), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_ERR0_WOF_DETAIL                               , RULL(0x05013143), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_PC_ERR1_CFG0                                     , RULL(0x05013148), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_ERR1_CFG1                                     , RULL(0x05013149), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_ERR1_FATAL                                    , RULL(0x0501314C), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_ERR1_INFO                                     , RULL(0x0501314E), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_ERR1_RECOV                                    , RULL(0x0501314D), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_ERR1_WOF                                      , RULL(0x0501314A), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_ERR1_WOF_DETAIL                               , RULL(0x0501314B), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_PC_GLOBAL_CFG                                    , RULL(0x05013110), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_IVE_BLOCK_MODE                                , RULL(0x05013113), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_MMIO_ARB                                      , RULL(0x0501311A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_PCMD_ARB                                      , RULL(0x05013118), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_ADDITIONAL_PERF_1                         , RULL(0x05013174), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_PC_VPC_ADDITIONAL_PERF_2                         , RULL(0x05013175), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_PC_VPC_CACHE_EN                                  , RULL(0x05013161), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA0                         , RULL(0x05013168), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA2                         , RULL(0x0501316A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA3                         , RULL(0x0501316B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA4                         , RULL(0x0501316C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA6                         , RULL(0x0501316E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA7                         , RULL(0x0501316F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_CACHE_WATCH_SPEC                          , RULL(0x05013167), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_PC_VPC_CONFIG                                    , RULL(0x05013164), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_DEBUG                                     , RULL(0x05013170), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_ERR_CFG0                                  , RULL(0x05013178), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_ERR_CFG1                                  , RULL(0x05013179), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_FATAL_ERR                                 , RULL(0x0501317C), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_VPC_INFO_ERR                                  , RULL(0x0501317E), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD                  , RULL(0x05013160), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_PERF_EVENT_SEL_1                          , RULL(0x05013171), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_PERF_EVENT_SEL_2                          , RULL(0x05013172), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_PERF_EVENT_SEL_3                          , RULL(0x05013173), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_RECOV_ERR                                 , RULL(0x0501317D), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_VPC_SCRUB_MASK                                , RULL(0x05013163), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_SCRUB_TRIG                                , RULL(0x05013162), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VPC_WOF_ERR                                   , RULL(0x0501317A), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_PC_VPC_WOF_ERR_DETAIL                            , RULL(0x0501317B), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_PC_VPD_BLOCK_MODE                                , RULL(0x05013115), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VRQ_CFG                                       , RULL(0x0501311C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VRQ_PEND_ARB                                  , RULL(0x0501311D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VRQ_VPC_ARB                                   , RULL(0x0501311F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VRQ_VPC_CRD                                   , RULL(0x0501311E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_PC_VSD_TABLE_ADDR                                , RULL(0x05013111), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU_CTL_INT_REQ                                      , RULL(0x05011397), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_INT_TCTXT_CFG                                        , RULL(0x05013100), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_TCTXT_EN0                                        , RULL(0x05013108), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_TCTXT_EN1                                        , RULL(0x0501310C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_TCTXT_INDIR0                                     , RULL(0x05013104), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_TCTXT_INDIR1                                     , RULL(0x05013105), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_TCTXT_INDIR2                                     , RULL(0x05013106), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_TCTXT_INDIR3                                     , RULL(0x05013107), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_TCTXT_TRACK                                      , RULL(0x05013101), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_AIB_TIMEOUT                                   , RULL(0x0501322B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_AIB_TX_CMD_PRIORITY                           , RULL(0x0501323D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_AIB_TX_ORDERING_TAG_1                         , RULL(0x0501322C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_AIB_TX_ORDERING_TAG_2                         , RULL(0x0501322D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ATX_INIT_CREDIT_COUNT                         , RULL(0x0501323C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ATX_PERF_EVENT_SEL_1                          , RULL(0x05013240), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ATX_PERF_EVENT_SEL_2                          , RULL(0x05013241), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ATX_PERF_EVENT_SEL_3                          , RULL(0x05013242), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_AT_MACRO_KILL                                 , RULL(0x0501323E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_AT_MACRO_KILL_MASK                            , RULL(0x0501323F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_ADDITIONAL_PERF_1                         , RULL(0x05013253), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_VC_EQC_ADDITIONAL_PERF_2                         , RULL(0x05013254), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_VC_EQC_CACHE_EN                                  , RULL(0x05013211), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_CACHE_WATCH_DATA0                         , RULL(0x05013216), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_CACHE_WATCH_DATA1                         , RULL(0x05013217), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_CACHE_WATCH_DATA2                         , RULL(0x05013218), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_CACHE_WATCH_DATA3                         , RULL(0x05013219), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_CACHE_WATCH_SPEC                          , RULL(0x05013215), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_VC_EQC_CONFIG                                    , RULL(0x05013214), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_DEBUG                                     , RULL(0x0501321A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_PERF_EVENT_SEL_1                          , RULL(0x05013250), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_PERF_EVENT_SEL_2                          , RULL(0x05013251), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_PERF_EVENT_SEL_3                          , RULL(0x05013252), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_SCRUB_MASK                                , RULL(0x05013213), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQC_SCRUB_TRIG                                , RULL(0x05013212), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_EQD_BLOCK_MODE                                , RULL(0x05013204), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ERR_CFG_G0R0                                  , RULL(0x05013270), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ERR_CFG_G0R1                                  , RULL(0x05013271), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ERR_CFG_G1R0                                  , RULL(0x05013272), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_ERR_CFG_G1R1                                  , RULL(0x05013273), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_FATAL_ERR_G0                                  , RULL(0x05013278), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_FATAL_ERR_G1                                  , RULL(0x0501327B), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_GLOBAL_CONFIG                                 , RULL(0x05013200), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_INFO_ERR_G0                                   , RULL(0x0501327A), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_INFO_ERR_G1                                   , RULL(0x0501327D), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_IRQ_CONFIG_0                                  , RULL(0x05013208), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_VC_IRQ_CONFIG_1                                  , RULL(0x05013209), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_VC_IRQ_CONFIG_2                                  , RULL(0x0501320A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_VC_IRQ_CONFIG_3                                  , RULL(0x0501320B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_VC_IRQ_CONFIG_4                                  , RULL(0x0501320C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_VC_IRQ_CONFIG_5                                  , RULL(0x0501320D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_INT_VC_IRQ_PERF_EVENT_SEL_0                          , RULL(0x05013268), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IRQ_PERF_EVENT_SEL_1                          , RULL(0x05013269), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IRQ_PERF_EVENT_SEL_2                          , RULL(0x0501326A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IRQ_PERF_EVENT_SEL_3                          , RULL(0x0501326B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IRQ_PERF_EVENT_SEL_4                          , RULL(0x0501326C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IRQ_PERF_EVENT_SEL_5                          , RULL(0x0501326D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IRQ_TO_EQC_CREDITS                            , RULL(0x0501320E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_ADDITIONAL_PERF                           , RULL(0x0501325B), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_VC_IVC_CACHE_EN                                  , RULL(0x05013221), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_CACHE_WATCH_ADDR                          , RULL(0x05013225), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_CACHE_WATCH_DATA                          , RULL(0x05013226), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_VC_IVC_DEBUG                                     , RULL(0x0501322A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_HASH_1                                    , RULL(0x05013227), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_HASH_2                                    , RULL(0x05013228), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_HASH_3                                    , RULL(0x05013229), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_PERF_EVENT_SEL_1                          , RULL(0x05013258), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_PERF_EVENT_SEL_2                          , RULL(0x05013259), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_PERF_EVENT_SEL_3                          , RULL(0x0501325A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_SCRUB_MASK                                , RULL(0x05013223), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVC_SCRUB_TRIG                                , RULL(0x05013222), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_IVE_ISB_BLOCK_MODE                            , RULL(0x05013203), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_LBS6_DEBUG                                    , RULL(0x05013206), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD                  , RULL(0x05013210), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA                       , RULL(0x0501323B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD                       , RULL(0x05013220), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD                       , RULL(0x05013230), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_RECOV_ERR_G0                                  , RULL(0x05013279), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_RECOV_ERR_G1                                  , RULL(0x0501327C), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_SBC_ADDITIONAL_PERF                           , RULL(0x05013263), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_VC_SBC_CACHE_EN                                  , RULL(0x05013231), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_CACHE_WATCH_ADDR                          , RULL(0x05013235), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_CACHE_WATCH_DATA                          , RULL(0x05013236), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_VC_SBC_CONFIG                                    , RULL(0x05013234), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_DEBUG                                     , RULL(0x0501323A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_PERF_EVENT_SEL_1                          , RULL(0x05013260), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_PERF_EVENT_SEL_2                          , RULL(0x05013261), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_PERF_EVENT_SEL_3                          , RULL(0x05013262), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_SCRUB_MASK                                , RULL(0x05013233), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_SCRUB_TRIG                                , RULL(0x05013232), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_SOFTWR_ADDR                               , RULL(0x05013237), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_SOFTWR_DATA                               , RULL(0x05013239), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_SBC_SOFTWR_MASK                               , RULL(0x05013238), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_VPS_BLOCK_MODE                                , RULL(0x05013205), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_VSD_TABLE_ADDR                                , RULL(0x05013201), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_INT_VC_WOF_ERR_G0                                    , RULL(0x05013274), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_WOF_ERR_G0_DETAIL                             , RULL(0x05013275), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_INT_VC_WOF_ERR_G1                                    , RULL(0x05013276), SH_UNT          ,
+       SH_ACS_SCOM_CLRPART );
+
+REG64( PU_INT_VC_WOF_ERR_G1_DETAIL                             , RULL(0x05013277), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_NPU_SM1_IODA_ADDR                                    , RULL(0x05011321), SH_UNT_PU_NPU_SM1,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU_SM1_IODA_DAT0                                    , RULL(0x05011322), SH_UNT_PU_NPU_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_IO_DATA_REG                                          , RULL(0x00090030), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_IVT_OFFSET                                           , RULL(0x05012918), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_JTG_PIB_OJCFG                                        , RULL(0x0006D004), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_JTG_PIB_OJCFG_AND                                    , RULL(0x0006D005), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_JTG_PIB_OJCFG_OR                                     , RULL(0x0006D006), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_JTG_PIB_OJFRST                                       , RULL(0x0006D007), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_JTG_PIB_OJIC_SCOM                                    , RULL(0x0006D008), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_JTG_PIB_OJIC_SCOM1                                   , RULL(0x0006D009), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_JTG_PIB_OJIC_SCOM2                                   , RULL(0x0006D00A), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_JTG_PIB_OJSTAT                                       , RULL(0x0006D00B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_JTG_PIB_OJTDI                                        , RULL(0x0006D00C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_JTG_PIB_OJTDO                                        , RULL(0x0006D00D), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_NPU_CTL_LCO_CONFIG                                   , RULL(0x05011382), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA0                              , RULL(0x02010850), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA0                            , RULL(0x02010850), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA0                            , RULL(0x04010850), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA1                              , RULL(0x02010851), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA1                            , RULL(0x02010851), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA1                            , RULL(0x04010851), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA10                             , RULL(0x0201085A), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA10                           , RULL(0x0201085A), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA10                           , RULL(0x0401085A), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA11                             , RULL(0x0201085B), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA11                           , RULL(0x0201085B), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA11                           , RULL(0x0401085B), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA12                             , RULL(0x0201085C), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA12                           , RULL(0x0201085C), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA12                           , RULL(0x0401085C), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA13                             , RULL(0x0201085D), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA13                           , RULL(0x0201085D), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA13                           , RULL(0x0401085D), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA14                             , RULL(0x0201085E), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA14                           , RULL(0x0201085E), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA14                           , RULL(0x0401085E), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA15                             , RULL(0x0201085F), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA15                           , RULL(0x0201085F), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA15                           , RULL(0x0401085F), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA2                              , RULL(0x02010852), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA2                            , RULL(0x02010852), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA2                            , RULL(0x04010852), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA3                              , RULL(0x02010853), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA3                            , RULL(0x02010853), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA3                            , RULL(0x04010853), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA4                              , RULL(0x02010854), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA4                            , RULL(0x02010854), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA4                            , RULL(0x04010854), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA5                              , RULL(0x02010855), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA5                            , RULL(0x02010855), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA5                            , RULL(0x04010855), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA6                              , RULL(0x02010856), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA6                            , RULL(0x02010856), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA6                            , RULL(0x04010856), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA7                              , RULL(0x02010857), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA7                            , RULL(0x02010857), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA7                            , RULL(0x04010857), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA8                              , RULL(0x02010858), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA8                            , RULL(0x02010858), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA8                            , RULL(0x04010858), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_RESP_DATA9                              , RULL(0x02010859), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_RESP_DATA9                            , RULL(0x02010859), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_RESP_DATA9                            , RULL(0x04010859), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_LINK_DELAY_TIMER                                   , RULL(0x02010845), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_LINK_DELAY_TIMER                                 , RULL(0x02010845), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_LINK_DELAY_TIMER                                 , RULL(0x04010845), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( PEC_LOCAL_FIR                                           , RULL(0x0D04000A), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_LOCAL_FIR_AND                                       , RULL(0x0D04000B), SH_UNT_PEC      , SH_ACS_SCOM1_AND );
+REG64( PEC_LOCAL_FIR_OR                                        , RULL(0x0D04000C), SH_UNT_PEC      , SH_ACS_SCOM2_OR  );
+REG64( PEC_0_LOCAL_FIR                                         , RULL(0x0D04000A), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_0_LOCAL_FIR_AND                                     , RULL(0x0D04000B), SH_UNT_PEC_0    , SH_ACS_SCOM1_AND );
+REG64( PEC_0_LOCAL_FIR_OR                                      , RULL(0x0D04000C), SH_UNT_PEC_0    , SH_ACS_SCOM2_OR  );
+REG64( PEC_1_LOCAL_FIR                                         , RULL(0x0E04000A), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_LOCAL_FIR_AND                                     , RULL(0x0E04000B), SH_UNT_PEC_1    , SH_ACS_SCOM1_AND );
+REG64( PEC_1_LOCAL_FIR_OR                                      , RULL(0x0E04000C), SH_UNT_PEC_1    , SH_ACS_SCOM2_OR  );
+REG64( PEC_2_LOCAL_FIR                                         , RULL(0x0F04000A), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_LOCAL_FIR_AND                                     , RULL(0x0F04000B), SH_UNT_PEC_2    , SH_ACS_SCOM1_AND );
+REG64( PEC_2_LOCAL_FIR_OR                                      , RULL(0x0F04000C), SH_UNT_PEC_2    , SH_ACS_SCOM2_OR  );
+
+REG64( PEC_LOCAL_FIR_ACTION0                                   , RULL(0x0D040010), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_LOCAL_FIR_ACTION0                                 , RULL(0x0D040010), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_LOCAL_FIR_ACTION0                                 , RULL(0x0E040010), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_LOCAL_FIR_ACTION0                                 , RULL(0x0F040010), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_LOCAL_FIR_ACTION1                                   , RULL(0x0D040011), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_LOCAL_FIR_ACTION1                                 , RULL(0x0D040011), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_LOCAL_FIR_ACTION1                                 , RULL(0x0E040011), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_LOCAL_FIR_ACTION1                                 , RULL(0x0F040011), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_LOCAL_FIR_MASK                                      , RULL(0x0D04000D), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_LOCAL_FIR_MASK_AND                                  , RULL(0x0D04000E), SH_UNT_PEC      , SH_ACS_SCOM1_AND );
+REG64( PEC_LOCAL_FIR_MASK_OR                                   , RULL(0x0D04000F), SH_UNT_PEC      , SH_ACS_SCOM2_OR  );
+REG64( PEC_0_LOCAL_FIR_MASK                                    , RULL(0x0D04000D), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_0_LOCAL_FIR_MASK_AND                                , RULL(0x0D04000E), SH_UNT_PEC_0    , SH_ACS_SCOM1_AND );
+REG64( PEC_0_LOCAL_FIR_MASK_OR                                 , RULL(0x0D04000F), SH_UNT_PEC_0    , SH_ACS_SCOM2_OR  );
+REG64( PEC_1_LOCAL_FIR_MASK                                    , RULL(0x0E04000D), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_LOCAL_FIR_MASK_AND                                , RULL(0x0E04000E), SH_UNT_PEC_1    , SH_ACS_SCOM1_AND );
+REG64( PEC_1_LOCAL_FIR_MASK_OR                                 , RULL(0x0E04000F), SH_UNT_PEC_1    , SH_ACS_SCOM2_OR  );
+REG64( PEC_2_LOCAL_FIR_MASK                                    , RULL(0x0F04000D), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_LOCAL_FIR_MASK_AND                                , RULL(0x0F04000E), SH_UNT_PEC_2    , SH_ACS_SCOM1_AND );
+REG64( PEC_2_LOCAL_FIR_MASK_OR                                 , RULL(0x0F04000F), SH_UNT_PEC_2    , SH_ACS_SCOM2_OR  );
+
+REG64( PEC_LOCAL_XSTOP_ERR                                     , RULL(0x0D040018), SH_UNT_PEC      , SH_ACS_SCOM_RO   );
+REG64( PEC_0_LOCAL_XSTOP_ERR                                   , RULL(0x0D040018), SH_UNT_PEC_0    , SH_ACS_SCOM_RO   );
+REG64( PEC_1_LOCAL_XSTOP_ERR                                   , RULL(0x0E040018), SH_UNT_PEC_1    , SH_ACS_SCOM_RO   );
+REG64( PEC_2_LOCAL_XSTOP_ERR                                   , RULL(0x0F040018), SH_UNT_PEC_2    , SH_ACS_SCOM_RO   );
+
+REG64( PEC_LOCAL_XSTOP_MASK                                    , RULL(0x0D040019), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_LOCAL_XSTOP_MASK                                  , RULL(0x0D040019), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_LOCAL_XSTOP_MASK                                  , RULL(0x0E040019), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_LOCAL_XSTOP_MASK                                  , RULL(0x0F040019), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( NV_LOW_PWR                                              , RULL(0x050110DC), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_LOW_PWR                                            , RULL(0x050110DC), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_LOW_PWR                                            , RULL(0x050110FC), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_LOW_PWR                                            , RULL(0x050111DC), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_LOW_PWR                                            , RULL(0x050111FC), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_LOW_PWR                                    , RULL(0x050112DC), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_LOW_PWR                                    , RULL(0x050112FC), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_LOW_WATER                                   , RULL(0x05011008), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_LOW_WATER                                   , RULL(0x05011028), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_LOW_WATER                                   , RULL(0x05011048), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_LOW_WATER                                   , RULL(0x05011068), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_LOW_WATER                                   , RULL(0x05011108), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_LOW_WATER                                   , RULL(0x05011128), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_LOW_WATER                                   , RULL(0x05011148), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_LOW_WATER                                   , RULL(0x05011168), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_LOW_WATER                                   , RULL(0x05011208), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_LOW_WATER                                   , RULL(0x05011228), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_LOW_WATER                                   , RULL(0x05011248), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_LOW_WATER                                   , RULL(0x05011268), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_LPCTH_CONFIG                                , RULL(0x05011090), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_LPCTH_CONFIG                                , RULL(0x05011190), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_LPCTH_CONFIG                                , RULL(0x05011290), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_LPC_BASE_REG                                         , RULL(0x00090040), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_LPC_CMD_REG                                          , RULL(0x00090041), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_LPC_DATA_REG                                         , RULL(0x00090042), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_LPC_STATUS_REG                                       , RULL(0x00090043), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PHB_MASK_REG                                            , RULL(0x0D01090B), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_MASK_REG_AND                                        , RULL(0x0D01090C), SH_UNT_PHB      , SH_ACS_SCOM1_AND );
+REG64( PHB_MASK_REG_OR                                         , RULL(0x0D01090D), SH_UNT_PHB      , SH_ACS_SCOM2_OR  );
+REG64( PHB_0_MASK_REG                                          , RULL(0x0D01090B), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_0_MASK_REG_AND                                      , RULL(0x0D01090C), SH_UNT_PHB_0    , SH_ACS_SCOM1_AND );
+REG64( PHB_0_MASK_REG_OR                                       , RULL(0x0D01090D), SH_UNT_PHB_0    , SH_ACS_SCOM2_OR  );
+REG64( PHB_1_MASK_REG                                          , RULL(0x0E01090B), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_MASK_REG_AND                                      , RULL(0x0E01090C), SH_UNT_PHB_1    , SH_ACS_SCOM1_AND );
+REG64( PHB_1_MASK_REG_OR                                       , RULL(0x0E01090D), SH_UNT_PHB_1    , SH_ACS_SCOM2_OR  );
+REG64( PHB_2_MASK_REG                                          , RULL(0x0E01094B), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_MASK_REG_AND                                      , RULL(0x0E01094C), SH_UNT_PHB_2    , SH_ACS_SCOM1_AND );
+REG64( PHB_2_MASK_REG_OR                                       , RULL(0x0E01094D), SH_UNT_PHB_2    , SH_ACS_SCOM2_OR  );
+REG64( PHB_3_MASK_REG                                          , RULL(0x0F01090B), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_MASK_REG_AND                                      , RULL(0x0F01090C), SH_UNT_PHB_3    , SH_ACS_SCOM1_AND );
+REG64( PHB_3_MASK_REG_OR                                       , RULL(0x0F01090D), SH_UNT_PHB_3    , SH_ACS_SCOM2_OR  );
+REG64( PHB_4_MASK_REG                                          , RULL(0x0F01094B), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_MASK_REG_AND                                      , RULL(0x0F01094C), SH_UNT_PHB_4    , SH_ACS_SCOM1_AND );
+REG64( PHB_4_MASK_REG_OR                                       , RULL(0x0F01094D), SH_UNT_PHB_4    , SH_ACS_SCOM2_OR  );
+REG64( PHB_5_MASK_REG                                          , RULL(0x0F01098B), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_MASK_REG_AND                                      , RULL(0x0F01098C), SH_UNT_PHB_5    , SH_ACS_SCOM1_AND );
+REG64( PHB_5_MASK_REG_OR                                       , RULL(0x0F01098D), SH_UNT_PHB_5    , SH_ACS_SCOM2_OR  );
+
+REG64( PU_MCC_FIR_REG                                          , RULL(0x03011400), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCC_FIR_REG_AND                                      , RULL(0x03011401), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_MCC_FIR_REG_OR                                       , RULL(0x03011402), SH_UNT          , SH_ACS_SCOM2_OR  );
+REG64( PU_MCD1_MCC_FIR_REG                                     , RULL(0x03011000), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_MCC_FIR_REG_AND                                 , RULL(0x03011001), SH_UNT_PU_MCD1  , SH_ACS_SCOM1_AND );
+REG64( PU_MCD1_MCC_FIR_REG_OR                                  , RULL(0x03011002), SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_MCD_DBG                                              , RULL(0x03011413), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_MCD1_MCD_DBG                                         , RULL(0x03011013), SH_UNT_PU_MCD1  , SH_ACS_SCOM      );
+
+REG64( PU_MCD_ECAP                                             , RULL(0x03011412), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_MCD1_MCD_ECAP                                        , RULL(0x03011012), SH_UNT_PU_MCD1  , SH_ACS_SCOM      );
+
+REG64( PU_MCD_FIR_ACTION0_REG                                  , RULL(0x03011406), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_MCD_FIR_ACTION0_REG                             , RULL(0x03011006), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_MCD_FIR_ACTION1_REG                                  , RULL(0x03011407), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_MCD_FIR_ACTION1_REG                             , RULL(0x03011007), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+
+REG64( PU_MCD_FIR_MASK_REG                                     , RULL(0x03011403), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_MCD_FIR_MASK_REG_AND                                 , RULL(0x03011404), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_MCD_FIR_MASK_REG_OR                                  , RULL(0x03011405), SH_UNT          , SH_ACS_SCOM2_OR  );
+REG64( PU_MCD1_MCD_FIR_MASK_REG                                , RULL(0x03011003), SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW   );
+REG64( PU_MCD1_MCD_FIR_MASK_REG_AND                            , RULL(0x03011004), SH_UNT_PU_MCD1  , SH_ACS_SCOM1_AND );
+REG64( PU_MCD1_MCD_FIR_MASK_REG_OR                             , RULL(0x03011005), SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_MIB_XIICAC                                           , RULL(0x000E0009), SH_UNT          ,
+       SH_ACS_SCOM_RO   ); //DUPS: 05012419, 09011053, 0C011053,
+
+REG64( PU_MIB_XIMEM                                            , RULL(0x000E0007), SH_UNT          ,
+       SH_ACS_SCOM_RO   ); //DUPS: 05012417, 09011051, 0C011051,
+
+REG64( PU_MIB_XISGB                                            , RULL(0x000E0008), SH_UNT          ,
+       SH_ACS_SCOM_RO   ); //DUPS: 05012418, 09011052, 0C011052,
+
+REG64( PU_MIB_XISIB                                            , RULL(0x000E0006), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_NPU_CTL_MISC_CONFIG                                  , RULL(0x05011386), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_MISC_HOLD                                    , RULL(0x05011384), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_MISC_MASK                                    , RULL(0x05011385), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NMMU_MMCQ_PB_MODE_REG                                , RULL(0x05012C15), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PEC_0_STACK0_MMIOBAR0_MASK_REG                          , RULL(0x04010C4F), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_0_STACK1_MMIOBAR0_MASK_REG                          , RULL(0x04010C8F), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_0_STACK2_MMIOBAR0_MASK_REG                          , RULL(0x04010CCF), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK0_MMIOBAR0_MASK_REG                          , RULL(0x0401104F), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK1_MMIOBAR0_MASK_REG                          , RULL(0x0401108F), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK2_MMIOBAR0_MASK_REG                          , RULL(0x040110CF), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK0_MMIOBAR0_MASK_REG                          , RULL(0x0401144F), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK1_MMIOBAR0_MASK_REG                          , RULL(0x0401148F), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK2_MMIOBAR0_MASK_REG                          , RULL(0x040114CF), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK0_MMIOBAR0_MASK_REG                            , RULL(0x04010C4F), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK1_MMIOBAR0_MASK_REG                            , RULL(0x04010C8F), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK2_MMIOBAR0_MASK_REG                            , RULL(0x04010CCF), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM      );
+REG64( PHB_MMIOBAR0_MASK_REG                                   , RULL(0x04010C4F), SH_UNT_PHB      , SH_ACS_SCOM      );
+REG64( PHB_0_MMIOBAR0_MASK_REG                                 , RULL(0x04010C4F), SH_UNT_PHB_0    , SH_ACS_SCOM      );
+REG64( PHB_1_MMIOBAR0_MASK_REG                                 , RULL(0x0401104F), SH_UNT_PHB_1    , SH_ACS_SCOM      );
+REG64( PHB_2_MMIOBAR0_MASK_REG                                 , RULL(0x0401108F), SH_UNT_PHB_2    , SH_ACS_SCOM      );
+REG64( PHB_3_MMIOBAR0_MASK_REG                                 , RULL(0x0401144F), SH_UNT_PHB_3    , SH_ACS_SCOM      );
+REG64( PHB_4_MMIOBAR0_MASK_REG                                 , RULL(0x0401148F), SH_UNT_PHB_4    , SH_ACS_SCOM      );
+REG64( PHB_5_MMIOBAR0_MASK_REG                                 , RULL(0x040114CF), SH_UNT_PHB_5    , SH_ACS_SCOM      );
+
+REG64( PEC_0_STACK0_MMIOBAR0_REG                               , RULL(0x04010C4E), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_0_STACK1_MMIOBAR0_REG                               , RULL(0x04010C8E), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_0_STACK2_MMIOBAR0_REG                               , RULL(0x04010CCE), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK0_MMIOBAR0_REG                               , RULL(0x0401104E), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK1_MMIOBAR0_REG                               , RULL(0x0401108E), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK2_MMIOBAR0_REG                               , RULL(0x040110CE), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK0_MMIOBAR0_REG                               , RULL(0x0401144E), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK1_MMIOBAR0_REG                               , RULL(0x0401148E), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK2_MMIOBAR0_REG                               , RULL(0x040114CE), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK0_MMIOBAR0_REG                                 , RULL(0x04010C4E), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK1_MMIOBAR0_REG                                 , RULL(0x04010C8E), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK2_MMIOBAR0_REG                                 , RULL(0x04010CCE), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM      );
+REG64( PHB_MMIOBAR0_REG                                        , RULL(0x04010C4E), SH_UNT_PHB      , SH_ACS_SCOM      );
+REG64( PHB_0_MMIOBAR0_REG                                      , RULL(0x04010C4E), SH_UNT_PHB_0    , SH_ACS_SCOM      );
+REG64( PHB_1_MMIOBAR0_REG                                      , RULL(0x0401104E), SH_UNT_PHB_1    , SH_ACS_SCOM      );
+REG64( PHB_2_MMIOBAR0_REG                                      , RULL(0x0401108E), SH_UNT_PHB_2    , SH_ACS_SCOM      );
+REG64( PHB_3_MMIOBAR0_REG                                      , RULL(0x0401144E), SH_UNT_PHB_3    , SH_ACS_SCOM      );
+REG64( PHB_4_MMIOBAR0_REG                                      , RULL(0x0401148E), SH_UNT_PHB_4    , SH_ACS_SCOM      );
+REG64( PHB_5_MMIOBAR0_REG                                      , RULL(0x040114CE), SH_UNT_PHB_5    , SH_ACS_SCOM      );
+
+REG64( PEC_0_STACK0_MMIOBAR1_MASK_REG                          , RULL(0x04010C51), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_0_STACK1_MMIOBAR1_MASK_REG                          , RULL(0x04010C91), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_0_STACK2_MMIOBAR1_MASK_REG                          , RULL(0x04010CD1), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK0_MMIOBAR1_MASK_REG                          , RULL(0x04011051), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK1_MMIOBAR1_MASK_REG                          , RULL(0x04011091), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK2_MMIOBAR1_MASK_REG                          , RULL(0x040110D1), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK0_MMIOBAR1_MASK_REG                          , RULL(0x04011451), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK1_MMIOBAR1_MASK_REG                          , RULL(0x04011491), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK2_MMIOBAR1_MASK_REG                          , RULL(0x040114D1), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK0_MMIOBAR1_MASK_REG                            , RULL(0x04010C51), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK1_MMIOBAR1_MASK_REG                            , RULL(0x04010C91), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK2_MMIOBAR1_MASK_REG                            , RULL(0x04010CD1), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM      );
+REG64( PHB_MMIOBAR1_MASK_REG                                   , RULL(0x04010C51), SH_UNT_PHB      , SH_ACS_SCOM      );
+REG64( PHB_0_MMIOBAR1_MASK_REG                                 , RULL(0x04010C51), SH_UNT_PHB_0    , SH_ACS_SCOM      );
+REG64( PHB_1_MMIOBAR1_MASK_REG                                 , RULL(0x04011051), SH_UNT_PHB_1    , SH_ACS_SCOM      );
+REG64( PHB_2_MMIOBAR1_MASK_REG                                 , RULL(0x04011091), SH_UNT_PHB_2    , SH_ACS_SCOM      );
+REG64( PHB_3_MMIOBAR1_MASK_REG                                 , RULL(0x04011451), SH_UNT_PHB_3    , SH_ACS_SCOM      );
+REG64( PHB_4_MMIOBAR1_MASK_REG                                 , RULL(0x04011491), SH_UNT_PHB_4    , SH_ACS_SCOM      );
+REG64( PHB_5_MMIOBAR1_MASK_REG                                 , RULL(0x040114D1), SH_UNT_PHB_5    , SH_ACS_SCOM      );
+
+REG64( PEC_0_STACK0_MMIOBAR1_REG                               , RULL(0x04010C50), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_0_STACK1_MMIOBAR1_REG                               , RULL(0x04010C90), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_0_STACK2_MMIOBAR1_REG                               , RULL(0x04010CD0), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK0_MMIOBAR1_REG                               , RULL(0x04011050), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK1_MMIOBAR1_REG                               , RULL(0x04011090), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK2_MMIOBAR1_REG                               , RULL(0x040110D0), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK0_MMIOBAR1_REG                               , RULL(0x04011450), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK1_MMIOBAR1_REG                               , RULL(0x04011490), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK2_MMIOBAR1_REG                               , RULL(0x040114D0), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK0_MMIOBAR1_REG                                 , RULL(0x04010C50), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK1_MMIOBAR1_REG                                 , RULL(0x04010C90), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK2_MMIOBAR1_REG                                 , RULL(0x04010CD0), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM      );
+REG64( PHB_MMIOBAR1_REG                                        , RULL(0x04010C50), SH_UNT_PHB      , SH_ACS_SCOM      );
+REG64( PHB_0_MMIOBAR1_REG                                      , RULL(0x04010C50), SH_UNT_PHB_0    , SH_ACS_SCOM      );
+REG64( PHB_1_MMIOBAR1_REG                                      , RULL(0x04011050), SH_UNT_PHB_1    , SH_ACS_SCOM      );
+REG64( PHB_2_MMIOBAR1_REG                                      , RULL(0x04011090), SH_UNT_PHB_2    , SH_ACS_SCOM      );
+REG64( PHB_3_MMIOBAR1_REG                                      , RULL(0x04011450), SH_UNT_PHB_3    , SH_ACS_SCOM      );
+REG64( PHB_4_MMIOBAR1_REG                                      , RULL(0x04011490), SH_UNT_PHB_4    , SH_ACS_SCOM      );
+REG64( PHB_5_MMIOBAR1_REG                                      , RULL(0x040114D0), SH_UNT_PHB_5    , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_MM_CFG_NMMU_CTL_MISC                            , RULL(0x05012C53), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_MM_CFG_NMMU_CTL_SLB                             , RULL(0x05012C54), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_MM_CFG_NMMU_CTL_SM                              , RULL(0x05012C52), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_MM_CFG_NMMU_CTL_TLB                             , RULL(0x05012C55), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0                       , RULL(0x05012C4A), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG1                       , RULL(0x05012C4B), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG2                       , RULL(0x05012C4C), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_MM_EPSILON_COUNTER_VALUE                        , RULL(0x05012C1D), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_MM_FIR1_ACTION0_REG                             , RULL(0x05012C46), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_NMMU_MM_FIR1_ACTION1_REG                             , RULL(0x05012C47), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_NMMU_MM_FIR1_MASK_REG                                , RULL(0x05012C43), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+REG64( PU_NMMU_MM_FIR1_MASK_REG_AND                            , RULL(0x05012C44), SH_UNT_PU_NMMU  , SH_ACS_SCOM1_AND );
+REG64( PU_NMMU_MM_FIR1_MASK_REG_OR                             , RULL(0x05012C45), SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_NMMU_MM_FIR1_REG                                     , RULL(0x05012C40), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+REG64( PU_NMMU_MM_FIR1_REG_AND                                 , RULL(0x05012C41), SH_UNT_PU_NMMU  , SH_ACS_SCOM1_AND );
+REG64( PU_NMMU_MM_FIR1_REG_OR                                  , RULL(0x05012C42), SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_NMMU_MM_FIR1_WOF_REG                                 , RULL(0x05012C48), SH_UNT_PU_NMMU  ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_NMMU_MM_NMMU_DBG_MODE                                , RULL(0x05012C59), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_MM_NMMU_ERR_INJ                                 , RULL(0x05012C58), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_MM_NMMU_ERR_LOG                                 , RULL(0x05012C57), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PEC_MODE_REG                                            , RULL(0x0D040008), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_MODE_REG                                          , RULL(0x0D040008), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_MODE_REG                                          , RULL(0x0E040008), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_MODE_REG                                          , RULL(0x0F040008), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_MODE_REGISTER                                        , RULL(0x00010008), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MODE_REGISTER_B                                      , RULL(0x000A0006), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MODE_REGISTER_C                                      , RULL(0x000A1006), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MODE_REGISTER_D                                      , RULL(0x000A2006), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_MODE_REGISTER_E                                      , RULL(0x000A3006), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_MULTICAST_GROUP_1                                   , RULL(0x0D0F0001), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_MULTICAST_GROUP_1                                 , RULL(0x0D0F0001), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_MULTICAST_GROUP_1                                 , RULL(0x0E0F0001), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_MULTICAST_GROUP_1                                 , RULL(0x0F0F0001), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_MULTICAST_GROUP_2                                   , RULL(0x0D0F0002), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_MULTICAST_GROUP_2                                 , RULL(0x0D0F0002), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_MULTICAST_GROUP_2                                 , RULL(0x0E0F0002), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_MULTICAST_GROUP_2                                 , RULL(0x0F0F0002), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_MULTICAST_GROUP_3                                   , RULL(0x0D0F0003), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_MULTICAST_GROUP_3                                 , RULL(0x0D0F0003), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_MULTICAST_GROUP_3                                 , RULL(0x0E0F0003), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_MULTICAST_GROUP_3                                 , RULL(0x0F0F0003), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_MULTICAST_GROUP_4                                   , RULL(0x0D0F0004), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_MULTICAST_GROUP_4                                 , RULL(0x0D0F0004), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_MULTICAST_GROUP_4                                 , RULL(0x0E0F0004), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_MULTICAST_GROUP_4                                 , RULL(0x0F0F0004), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_NDT0_BAR                                    , RULL(0x0501100D), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_NDT0_BAR                                    , RULL(0x0501102D), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_NDT0_BAR                                    , RULL(0x0501104D), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_NDT0_BAR                                    , RULL(0x0501106D), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_NDT0_BAR                                    , RULL(0x0501110D), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_NDT0_BAR                                    , RULL(0x0501112D), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_NDT0_BAR                                    , RULL(0x0501114D), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_NDT0_BAR                                    , RULL(0x0501116D), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_NDT0_BAR                                    , RULL(0x0501120D), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_NDT0_BAR                                    , RULL(0x0501122D), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_NDT0_BAR                                    , RULL(0x0501124D), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_NDT0_BAR                                    , RULL(0x0501126D), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_NDT1_BAR                                    , RULL(0x0501100E), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_NDT1_BAR                                    , RULL(0x0501102E), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_NDT1_BAR                                    , RULL(0x0501104E), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_NDT1_BAR                                    , RULL(0x0501106E), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_NDT1_BAR                                    , RULL(0x0501110E), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_NDT1_BAR                                    , RULL(0x0501112E), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_NDT1_BAR                                    , RULL(0x0501114E), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_NDT1_BAR                                    , RULL(0x0501116E), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_NDT1_BAR                                    , RULL(0x0501120E), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_NDT1_BAR                                    , RULL(0x0501122E), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_NDT1_BAR                                    , RULL(0x0501124E), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_NDT1_BAR                                    , RULL(0x0501126E), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PEC_NESTTRC_REG                                         , RULL(0x04010C03), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_NESTTRC_REG                                       , RULL(0x04010C03), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_NESTTRC_REG                                       , RULL(0x04011003), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_NESTTRC_REG                                       , RULL(0x04011403), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_0_STACK0_NET_CTRL0                                  , RULL(0x0D0F0040), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK0_NET_CTRL0_WAND                             , RULL(0x0D0F0041), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM1_WAND );
+REG64( PEC_0_STACK0_NET_CTRL0_WOR                              , RULL(0x0D0F0042), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM2_WOR );
+REG64( PEC_1_STACK0_NET_CTRL0                                  , RULL(0x0E0F0040), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK0_NET_CTRL0_WAND                             , RULL(0x0E0F0041), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM1_WAND );
+REG64( PEC_1_STACK0_NET_CTRL0_WOR                              , RULL(0x0E0F0042), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM2_WOR );
+REG64( PEC_2_STACK0_NET_CTRL0                                  , RULL(0x0F0F0040), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK0_NET_CTRL0_WAND                             , RULL(0x0F0F0041), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM1_WAND );
+REG64( PEC_2_STACK0_NET_CTRL0_WOR                              , RULL(0x0F0F0042), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM2_WOR );
+REG64( PEC_STACK0_NET_CTRL0                                    , RULL(0x0D0F0040), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK0_NET_CTRL0_WAND                               , RULL(0x0D0F0041), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM1_WAND );
+REG64( PEC_STACK0_NET_CTRL0_WOR                                , RULL(0x0D0F0042), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM2_WOR );
+
+REG64( PEC_0_STACK0_NET_CTRL1                                  , RULL(0x0D0F0044), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK0_NET_CTRL1_WAND                             , RULL(0x0D0F0045), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM1_WAND );
+REG64( PEC_0_STACK0_NET_CTRL1_WOR                              , RULL(0x0D0F0046), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM2_WOR );
+REG64( PEC_1_STACK0_NET_CTRL1                                  , RULL(0x0E0F0044), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK0_NET_CTRL1_WAND                             , RULL(0x0E0F0045), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM1_WAND );
+REG64( PEC_1_STACK0_NET_CTRL1_WOR                              , RULL(0x0E0F0046), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM2_WOR );
+REG64( PEC_2_STACK0_NET_CTRL1                                  , RULL(0x0F0F0044), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK0_NET_CTRL1_WAND                             , RULL(0x0F0F0045), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM1_WAND );
+REG64( PEC_2_STACK0_NET_CTRL1_WOR                              , RULL(0x0F0F0046), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM2_WOR );
+REG64( PEC_STACK0_NET_CTRL1                                    , RULL(0x0D0F0044), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK0_NET_CTRL1_WAND                               , RULL(0x0D0F0045), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM1_WAND );
+REG64( PEC_STACK0_NET_CTRL1_WOR                                , RULL(0x0D0F0046), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM2_WOR );
+
+REG64( PEC_0_STACK0_NFIRACTION0_REG                            , RULL(0x04010C46), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK1_NFIRACTION0_REG                            , RULL(0x04010C86), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK2_NFIRACTION0_REG                            , RULL(0x04010CC6), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK0_NFIRACTION0_REG                            , RULL(0x04011046), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK1_NFIRACTION0_REG                            , RULL(0x04011086), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK2_NFIRACTION0_REG                            , RULL(0x040110C6), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK0_NFIRACTION0_REG                            , RULL(0x04011446), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK1_NFIRACTION0_REG                            , RULL(0x04011486), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK2_NFIRACTION0_REG                            , RULL(0x040114C6), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK0_NFIRACTION0_REG                              , RULL(0x04010C46), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK1_NFIRACTION0_REG                              , RULL(0x04010C86), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK2_NFIRACTION0_REG                              , RULL(0x04010CC6), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PHB_NFIRACTION0_REG                                     , RULL(0x04010C46), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_0_NFIRACTION0_REG                                   , RULL(0x04010C46), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_NFIRACTION0_REG                                   , RULL(0x04011046), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_NFIRACTION0_REG                                   , RULL(0x04011086), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_NFIRACTION0_REG                                   , RULL(0x04011446), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_NFIRACTION0_REG                                   , RULL(0x04011486), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_NFIRACTION0_REG                                   , RULL(0x040114C6), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_0_STACK0_NFIRACTION1_REG                            , RULL(0x04010C47), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK1_NFIRACTION1_REG                            , RULL(0x04010C87), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK2_NFIRACTION1_REG                            , RULL(0x04010CC7), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK0_NFIRACTION1_REG                            , RULL(0x04011047), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK1_NFIRACTION1_REG                            , RULL(0x04011087), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK2_NFIRACTION1_REG                            , RULL(0x040110C7), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK0_NFIRACTION1_REG                            , RULL(0x04011447), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK1_NFIRACTION1_REG                            , RULL(0x04011487), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK2_NFIRACTION1_REG                            , RULL(0x040114C7), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK0_NFIRACTION1_REG                              , RULL(0x04010C47), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK1_NFIRACTION1_REG                              , RULL(0x04010C87), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK2_NFIRACTION1_REG                              , RULL(0x04010CC7), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PHB_NFIRACTION1_REG                                     , RULL(0x04010C47), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_0_NFIRACTION1_REG                                   , RULL(0x04010C47), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_NFIRACTION1_REG                                   , RULL(0x04011047), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_NFIRACTION1_REG                                   , RULL(0x04011087), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_NFIRACTION1_REG                                   , RULL(0x04011447), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_NFIRACTION1_REG                                   , RULL(0x04011487), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_NFIRACTION1_REG                                   , RULL(0x040114C7), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_0_STACK0_NFIRMASK_REG                               , RULL(0x04010C43), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK0_NFIRMASK_REG_AND                           , RULL(0x04010C44), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_0_STACK0_NFIRMASK_REG_OR                            , RULL(0x04010C45), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_0_STACK1_NFIRMASK_REG                               , RULL(0x04010C83), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK1_NFIRMASK_REG_AND                           , RULL(0x04010C84), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_0_STACK1_NFIRMASK_REG_OR                            , RULL(0x04010C85), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_0_STACK2_NFIRMASK_REG                               , RULL(0x04010CC3), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK2_NFIRMASK_REG_AND                           , RULL(0x04010CC4), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_0_STACK2_NFIRMASK_REG_OR                            , RULL(0x04010CC5), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_1_STACK0_NFIRMASK_REG                               , RULL(0x04011043), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK0_NFIRMASK_REG_AND                           , RULL(0x04011044), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_1_STACK0_NFIRMASK_REG_OR                            , RULL(0x04011045), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_1_STACK1_NFIRMASK_REG                               , RULL(0x04011083), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK1_NFIRMASK_REG_AND                           , RULL(0x04011084), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_1_STACK1_NFIRMASK_REG_OR                            , RULL(0x04011085), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_1_STACK2_NFIRMASK_REG                               , RULL(0x040110C3), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK2_NFIRMASK_REG_AND                           , RULL(0x040110C4), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_1_STACK2_NFIRMASK_REG_OR                            , RULL(0x040110C5), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_2_STACK0_NFIRMASK_REG                               , RULL(0x04011443), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK0_NFIRMASK_REG_AND                           , RULL(0x04011444), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_2_STACK0_NFIRMASK_REG_OR                            , RULL(0x04011445), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_2_STACK1_NFIRMASK_REG                               , RULL(0x04011483), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK1_NFIRMASK_REG_AND                           , RULL(0x04011484), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_2_STACK1_NFIRMASK_REG_OR                            , RULL(0x04011485), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_2_STACK2_NFIRMASK_REG                               , RULL(0x040114C3), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK2_NFIRMASK_REG_AND                           , RULL(0x040114C4), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_2_STACK2_NFIRMASK_REG_OR                            , RULL(0x040114C5), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_STACK0_NFIRMASK_REG                                 , RULL(0x04010C43), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK0_NFIRMASK_REG_AND                             , RULL(0x04010C44), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_STACK0_NFIRMASK_REG_OR                              , RULL(0x04010C45), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_STACK1_NFIRMASK_REG                                 , RULL(0x04010C83), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK1_NFIRMASK_REG_AND                             , RULL(0x04010C84), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_STACK1_NFIRMASK_REG_OR                              , RULL(0x04010C85), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_STACK2_NFIRMASK_REG                                 , RULL(0x04010CC3), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK2_NFIRMASK_REG_AND                             , RULL(0x04010CC4), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_STACK2_NFIRMASK_REG_OR                              , RULL(0x04010CC5), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM2_OR  );
+REG64( PHB_NFIRMASK_REG                                        , RULL(0x04010C43), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_NFIRMASK_REG_AND                                    , RULL(0x04010C44), SH_UNT_PHB      , SH_ACS_SCOM1_AND );
+REG64( PHB_NFIRMASK_REG_OR                                     , RULL(0x04010C45), SH_UNT_PHB      , SH_ACS_SCOM2_OR  );
+REG64( PHB_0_NFIRMASK_REG                                      , RULL(0x04010C43), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_0_NFIRMASK_REG_AND                                  , RULL(0x04010C44), SH_UNT_PHB_0    , SH_ACS_SCOM1_AND );
+REG64( PHB_0_NFIRMASK_REG_OR                                   , RULL(0x04010C45), SH_UNT_PHB_0    , SH_ACS_SCOM2_OR  );
+REG64( PHB_1_NFIRMASK_REG                                      , RULL(0x04011043), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_NFIRMASK_REG_AND                                  , RULL(0x04011044), SH_UNT_PHB_1    , SH_ACS_SCOM1_AND );
+REG64( PHB_1_NFIRMASK_REG_OR                                   , RULL(0x04011045), SH_UNT_PHB_1    , SH_ACS_SCOM2_OR  );
+REG64( PHB_2_NFIRMASK_REG                                      , RULL(0x04011083), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_NFIRMASK_REG_AND                                  , RULL(0x04011084), SH_UNT_PHB_2    , SH_ACS_SCOM1_AND );
+REG64( PHB_2_NFIRMASK_REG_OR                                   , RULL(0x04011085), SH_UNT_PHB_2    , SH_ACS_SCOM2_OR  );
+REG64( PHB_3_NFIRMASK_REG                                      , RULL(0x04011443), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_NFIRMASK_REG_AND                                  , RULL(0x04011444), SH_UNT_PHB_3    , SH_ACS_SCOM1_AND );
+REG64( PHB_3_NFIRMASK_REG_OR                                   , RULL(0x04011445), SH_UNT_PHB_3    , SH_ACS_SCOM2_OR  );
+REG64( PHB_4_NFIRMASK_REG                                      , RULL(0x04011483), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_NFIRMASK_REG_AND                                  , RULL(0x04011484), SH_UNT_PHB_4    , SH_ACS_SCOM1_AND );
+REG64( PHB_4_NFIRMASK_REG_OR                                   , RULL(0x04011485), SH_UNT_PHB_4    , SH_ACS_SCOM2_OR  );
+REG64( PHB_5_NFIRMASK_REG                                      , RULL(0x040114C3), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_NFIRMASK_REG_AND                                  , RULL(0x040114C4), SH_UNT_PHB_5    , SH_ACS_SCOM1_AND );
+REG64( PHB_5_NFIRMASK_REG_OR                                   , RULL(0x040114C5), SH_UNT_PHB_5    , SH_ACS_SCOM2_OR  );
+
+REG64( PEC_0_STACK0_NFIRWOF_REG                                , RULL(0x04010C48), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PEC_0_STACK1_NFIRWOF_REG                                , RULL(0x04010C88), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PEC_0_STACK2_NFIRWOF_REG                                , RULL(0x04010CC8), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PEC_1_STACK0_NFIRWOF_REG                                , RULL(0x04011048), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PEC_1_STACK1_NFIRWOF_REG                                , RULL(0x04011088), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PEC_1_STACK2_NFIRWOF_REG                                , RULL(0x040110C8), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PEC_2_STACK0_NFIRWOF_REG                                , RULL(0x04011448), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PEC_2_STACK1_NFIRWOF_REG                                , RULL(0x04011488), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PEC_2_STACK2_NFIRWOF_REG                                , RULL(0x040114C8), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PEC_STACK0_NFIRWOF_REG                                  , RULL(0x04010C48), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PEC_STACK1_NFIRWOF_REG                                  , RULL(0x04010C88), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PEC_STACK2_NFIRWOF_REG                                  , RULL(0x04010CC8), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_NFIRWOF_REG                                         , RULL(0x04010C48), SH_UNT_PHB      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_0_NFIRWOF_REG                                       , RULL(0x04010C48), SH_UNT_PHB_0    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_1_NFIRWOF_REG                                       , RULL(0x04011048), SH_UNT_PHB_1    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_2_NFIRWOF_REG                                       , RULL(0x04011088), SH_UNT_PHB_2    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_3_NFIRWOF_REG                                       , RULL(0x04011448), SH_UNT_PHB_3    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_4_NFIRWOF_REG                                       , RULL(0x04011488), SH_UNT_PHB_4    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_5_NFIRWOF_REG                                       , RULL(0x040114C8), SH_UNT_PHB_5    ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PEC_0_STACK0_NFIR_REG                                   , RULL(0x04010C40), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK0_NFIR_REG_AND                               , RULL(0x04010C41), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_0_STACK0_NFIR_REG_OR                                , RULL(0x04010C42), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_0_STACK1_NFIR_REG                                   , RULL(0x04010C80), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK1_NFIR_REG_AND                               , RULL(0x04010C81), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_0_STACK1_NFIR_REG_OR                                , RULL(0x04010C82), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_0_STACK2_NFIR_REG                                   , RULL(0x04010CC0), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK2_NFIR_REG_AND                               , RULL(0x04010CC1), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_0_STACK2_NFIR_REG_OR                                , RULL(0x04010CC2), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_1_STACK0_NFIR_REG                                   , RULL(0x04011040), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK0_NFIR_REG_AND                               , RULL(0x04011041), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_1_STACK0_NFIR_REG_OR                                , RULL(0x04011042), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_1_STACK1_NFIR_REG                                   , RULL(0x04011080), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK1_NFIR_REG_AND                               , RULL(0x04011081), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_1_STACK1_NFIR_REG_OR                                , RULL(0x04011082), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_1_STACK2_NFIR_REG                                   , RULL(0x040110C0), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK2_NFIR_REG_AND                               , RULL(0x040110C1), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_1_STACK2_NFIR_REG_OR                                , RULL(0x040110C2), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_2_STACK0_NFIR_REG                                   , RULL(0x04011440), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK0_NFIR_REG_AND                               , RULL(0x04011441), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_2_STACK0_NFIR_REG_OR                                , RULL(0x04011442), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_2_STACK1_NFIR_REG                                   , RULL(0x04011480), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK1_NFIR_REG_AND                               , RULL(0x04011481), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_2_STACK1_NFIR_REG_OR                                , RULL(0x04011482), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_2_STACK2_NFIR_REG                                   , RULL(0x040114C0), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK2_NFIR_REG_AND                               , RULL(0x040114C1), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_2_STACK2_NFIR_REG_OR                                , RULL(0x040114C2), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_STACK0_NFIR_REG                                     , RULL(0x04010C40), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK0_NFIR_REG_AND                                 , RULL(0x04010C41), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_STACK0_NFIR_REG_OR                                  , RULL(0x04010C42), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_STACK1_NFIR_REG                                     , RULL(0x04010C80), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK1_NFIR_REG_AND                                 , RULL(0x04010C81), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_STACK1_NFIR_REG_OR                                  , RULL(0x04010C82), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM2_OR  );
+REG64( PEC_STACK2_NFIR_REG                                     , RULL(0x04010CC0), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK2_NFIR_REG_AND                                 , RULL(0x04010CC1), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM1_AND );
+REG64( PEC_STACK2_NFIR_REG_OR                                  , RULL(0x04010CC2), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM2_OR  );
+REG64( PHB_NFIR_REG                                            , RULL(0x04010C40), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_NFIR_REG_AND                                        , RULL(0x04010C41), SH_UNT_PHB      , SH_ACS_SCOM1_AND );
+REG64( PHB_NFIR_REG_OR                                         , RULL(0x04010C42), SH_UNT_PHB      , SH_ACS_SCOM2_OR  );
+REG64( PHB_0_NFIR_REG                                          , RULL(0x04010C40), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_0_NFIR_REG_AND                                      , RULL(0x04010C41), SH_UNT_PHB_0    , SH_ACS_SCOM1_AND );
+REG64( PHB_0_NFIR_REG_OR                                       , RULL(0x04010C42), SH_UNT_PHB_0    , SH_ACS_SCOM2_OR  );
+REG64( PHB_1_NFIR_REG                                          , RULL(0x04011040), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_NFIR_REG_AND                                      , RULL(0x04011041), SH_UNT_PHB_1    , SH_ACS_SCOM1_AND );
+REG64( PHB_1_NFIR_REG_OR                                       , RULL(0x04011042), SH_UNT_PHB_1    , SH_ACS_SCOM2_OR  );
+REG64( PHB_2_NFIR_REG                                          , RULL(0x04011080), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_NFIR_REG_AND                                      , RULL(0x04011081), SH_UNT_PHB_2    , SH_ACS_SCOM1_AND );
+REG64( PHB_2_NFIR_REG_OR                                       , RULL(0x04011082), SH_UNT_PHB_2    , SH_ACS_SCOM2_OR  );
+REG64( PHB_3_NFIR_REG                                          , RULL(0x04011440), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_NFIR_REG_AND                                      , RULL(0x04011441), SH_UNT_PHB_3    , SH_ACS_SCOM1_AND );
+REG64( PHB_3_NFIR_REG_OR                                       , RULL(0x04011442), SH_UNT_PHB_3    , SH_ACS_SCOM2_OR  );
+REG64( PHB_4_NFIR_REG                                          , RULL(0x04011480), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_NFIR_REG_AND                                      , RULL(0x04011481), SH_UNT_PHB_4    , SH_ACS_SCOM1_AND );
+REG64( PHB_4_NFIR_REG_OR                                       , RULL(0x04011482), SH_UNT_PHB_4    , SH_ACS_SCOM2_OR  );
+REG64( PHB_5_NFIR_REG                                          , RULL(0x040114C0), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_NFIR_REG_AND                                      , RULL(0x040114C1), SH_UNT_PHB_5    , SH_ACS_SCOM1_AND );
+REG64( PHB_5_NFIR_REG_OR                                       , RULL(0x040114C2), SH_UNT_PHB_5    , SH_ACS_SCOM2_OR  );
+
+REG64( PU_NOTRUST_BAR0                                         , RULL(0x05012B40), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NOTRUST_BAR0MASK                                     , RULL(0x05012B42), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NOTRUST_BAR1                                         , RULL(0x05012B41), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NOTRUST_BAR1MASK                                     , RULL(0x05012B43), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM0_NPU_ATS_DEBUG                                , RULL(0x05011303), SH_UNT_PU_NPU_SM0,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU_SM0_NPU_AT_ECC                                   , RULL(0x05011302), SH_UNT_PU_NPU_SM0,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU_SM1_NPU_AT_ESMR                                  , RULL(0x05011328), SH_UNT_PU_NPU_SM1,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU_SM1_NPU_AT_ESR                                   , RULL(0x05011327), SH_UNT_PU_NPU_SM1,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU_SM1_NPU_AT_FESMR                                 , RULL(0x0501132A), SH_UNT_PU_NPU_SM1,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU_SM1_NPU_AT_FESR                                  , RULL(0x05011329), SH_UNT_PU_NPU_SM1,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU_SM0_NPU_AT_PMU_CNT                               , RULL(0x05011301), SH_UNT_PU_NPU_SM0,
+       SH_ACS_SCOM_RO   );
+
+REG64( PU_NPU_SM0_NPU_AT_PMU_CTRL                              , RULL(0x05011300), SH_UNT_PU_NPU_SM0,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU_SM1_NPU_Q_DMA_R                                  , RULL(0x05011325), SH_UNT_PU_NPU_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_NPU_VERSION                                  , RULL(0x05011390), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NXCQ_PB_MODE_REG                                     , RULL(0x02011095), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_CQ_FIR_ACTION0_REG                                , RULL(0x02011086), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_NMMU_NX_CQ_FIR_ACTION0_REG                           , RULL(0x05012C06), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_CQ_FIR_ACTION1_REG                                , RULL(0x02011087), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_NMMU_NX_CQ_FIR_ACTION1_REG                           , RULL(0x05012C07), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_CQ_FIR_MASK_REG                                   , RULL(0x02011083), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_NX_CQ_FIR_MASK_REG_AND                               , RULL(0x02011084), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_NX_CQ_FIR_MASK_REG_OR                                , RULL(0x02011085), SH_UNT          , SH_ACS_SCOM2_OR  );
+REG64( PU_NMMU_NX_CQ_FIR_MASK_REG                              , RULL(0x05012C03), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+REG64( PU_NMMU_NX_CQ_FIR_MASK_REG_AND                          , RULL(0x05012C04), SH_UNT_PU_NMMU  , SH_ACS_SCOM1_AND );
+REG64( PU_NMMU_NX_CQ_FIR_MASK_REG_OR                           , RULL(0x05012C05), SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_NX_CQ_FIR_REG                                        , RULL(0x02011080), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_NX_CQ_FIR_REG_AND                                    , RULL(0x02011081), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_NX_CQ_FIR_REG_OR                                     , RULL(0x02011082), SH_UNT          , SH_ACS_SCOM2_OR  );
+REG64( PU_NMMU_NX_CQ_FIR_REG                                   , RULL(0x05012C00), SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW   );
+REG64( PU_NMMU_NX_CQ_FIR_REG_AND                               , RULL(0x05012C01), SH_UNT_PU_NMMU  , SH_ACS_SCOM1_AND );
+REG64( PU_NMMU_NX_CQ_FIR_REG_OR                                , RULL(0x05012C02), SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR  );
+
+REG64( PU_NX_CQ_FIR_WOF_REG                                    , RULL(0x02011088), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PU_NMMU_NX_CQ_FIR_WOF_REG                               , RULL(0x05012C08), SH_UNT_PU_NMMU  ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_NX_DEBUGMUX_CTRL                                     , RULL(0x0201110A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_DEBUG_SNAPSHOT_0                                  , RULL(0x020110A4), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_NMMU_NX_DEBUG_SNAPSHOT_0                             , RULL(0x05012C24), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NX_DEBUG_SNAPSHOT_1                                  , RULL(0x020110A5), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_NMMU_NX_DEBUG_SNAPSHOT_1                             , RULL(0x05012C25), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NX_DMA_ENG_FIR                                       , RULL(0x02011100), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_NX_DMA_ENG_FIR_AND                                   , RULL(0x02011101), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_NX_DMA_ENG_FIR_OR                                    , RULL(0x02011102), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_NX_DMA_ENG_FIR_ACTION0                               , RULL(0x02011106), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_DMA_ENG_FIR_ACTION1                               , RULL(0x02011107), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_DMA_ENG_FIR_MASK                                  , RULL(0x02011103), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_NX_DMA_ENG_FIR_MASK_AND                              , RULL(0x02011104), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_NX_DMA_ENG_FIR_MASK_OR                               , RULL(0x02011105), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_NX_DMA_ENG_FIR_WOF                                   , RULL(0x02011108), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_NX_ERRORINJ_CTRL                                     , RULL(0x0201110C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_NX_MISC_CONTROL_REG                                  , RULL(0x020110A8), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_NMMU_NX_MISC_CONTROL_REG                             , RULL(0x05012C28), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NX_MMIO_BAR                                          , RULL(0x0201108D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_PB_DEBUG_REG                                      , RULL(0x02011090), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_NMMU_NX_PB_DEBUG_REG                                 , RULL(0x05012C10), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NX_PB_ECC_REG                                        , RULL(0x02011091), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_NMMU_NX_PB_ECC_REG                                   , RULL(0x05012C11), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NX_PB_ERR_RPT_0                                      , RULL(0x020110A2), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_NMMU_NX_PB_ERR_RPT_0                                 , RULL(0x05012C22), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NX_PB_ERR_RPT_1                                      , RULL(0x020110A1), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_PMU0_CONTROL_REG                                  , RULL(0x020110A6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_PMU0_COUNTER_REG                                  , RULL(0x020110A7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_PMU1_CONTROL_REG                                  , RULL(0x020110A9), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_PMU1_COUNTER_REG                                  , RULL(0x020110AA), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_NX_PMU_CONTROL_REG                              , RULL(0x05012C26), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NMMU_NX_PMU_COUNTER_REG                              , RULL(0x05012C27), SH_UNT_PU_NMMU  , SH_ACS_SCOM      );
+
+REG64( PU_NX_RNG_BYPASS                                        , RULL(0x020110E4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_RNG_CFG                                           , RULL(0x020110E0), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_RNG_RDELAY                                        , RULL(0x020110E5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_RNG_RESET                                         , RULL(0x020110E6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_RNG_ST0                                           , RULL(0x020110E1), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_RNG_ST1                                           , RULL(0x020110E2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_RNG_ST2                                           , RULL(0x020110E3), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_RNG_ST3                                           , RULL(0x020110E8), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_NX_TRIGGER_CTRL                                      , RULL(0x0201110B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_CCSR_OCI                                     , RULL(0xC0060480), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_CCSR_OCI1                                    , RULL(0xC0060488), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_CCSR_OCI2                                    , RULL(0xC0060490), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_CCSR_SCOM                                    , RULL(0x0006C090), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_CCSR_SCOM1                                   , RULL(0x0006C091), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_CCSR_SCOM2                                   , RULL(0x0006C092), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_G0ISR0_OCI                                   , RULL(0xC0060320), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_G0ISR0_SCOM                                  , RULL(0x0006C064), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_G0ISR1_OCI                                   , RULL(0xC00603A0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_G0ISR1_SCOM                                  , RULL(0x0006C074), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_G1ISR0_OCI                                   , RULL(0xC0060328), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_G1ISR0_SCOM                                  , RULL(0x0006C065), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_G1ISR1_OCI                                   , RULL(0xC00603A8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_G1ISR1_SCOM                                  , RULL(0x0006C075), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_G2ISR0_OCI                                   , RULL(0xC0060330), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_G2ISR0_SCOM                                  , RULL(0x0006C066), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_G2ISR1_OCI                                   , RULL(0xC00603B0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_G2ISR1_SCOM                                  , RULL(0x0006C076), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_G3ISR0_OCI                                   , RULL(0xC0060338), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_G3ISR0_SCOM                                  , RULL(0x0006C067), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_G3ISR1_OCI                                   , RULL(0xC00603B8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_G3ISR1_SCOM                                  , RULL(0x0006C077), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_O2SCMD0A_OCI                                 , RULL(0xC0063838), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCMD0A_SCOM                                , RULL(0x0006C707), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCMD0B_OCI                                 , RULL(0xC00638B8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCMD0B_SCOM                                , RULL(0x0006C717), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCMD1A_OCI                                 , RULL(0xC0063938), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCMD1A_SCOM                                , RULL(0x0006C727), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCMD1B_OCI                                 , RULL(0xC00639B8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCMD1B_SCOM                                , RULL(0x0006C737), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRL10A_OCI                               , RULL(0xC0063810), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRL10A_SCOM                              , RULL(0x0006C702), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRL10B_OCI                               , RULL(0xC0063890), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRL10B_SCOM                              , RULL(0x0006C712), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRL11A_OCI                               , RULL(0xC0063910), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRL11A_SCOM                              , RULL(0x0006C722), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRL11B_OCI                               , RULL(0xC0063990), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRL11B_SCOM                              , RULL(0x0006C732), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRL20A_OCI                               , RULL(0xC0063818), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRL20A_SCOM                              , RULL(0x0006C703), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRL20B_OCI                               , RULL(0xC0063898), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRL20B_SCOM                              , RULL(0x0006C713), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRL21A_OCI                               , RULL(0xC0063918), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRL21A_SCOM                              , RULL(0x0006C723), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRL21B_OCI                               , RULL(0xC0063998), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRL21B_SCOM                              , RULL(0x0006C733), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRLF0A_OCI                               , RULL(0xC0063800), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRLF0A_SCOM                              , RULL(0x0006C700), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRLF0B_OCI                               , RULL(0xC0063880), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRLF0B_SCOM                              , RULL(0x0006C710), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRLF1A_OCI                               , RULL(0xC0063900), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRLF1A_SCOM                              , RULL(0x0006C720), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRLF1B_OCI                               , RULL(0xC0063980), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRLF1B_SCOM                              , RULL(0x0006C730), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRLS0A_OCI                               , RULL(0xC0063808), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRLS0A_SCOM                              , RULL(0x0006C701), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRLS0B_OCI                               , RULL(0xC0063888), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRLS0B_SCOM                              , RULL(0x0006C711), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRLS1A_OCI                               , RULL(0xC0063908), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRLS1A_SCOM                              , RULL(0x0006C721), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SCTRLS1B_OCI                               , RULL(0xC0063988), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SCTRLS1B_SCOM                              , RULL(0x0006C731), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SRD0A_OCI                                  , RULL(0xC0063848), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SRD0A_SCOM                                 , RULL(0x0006C709), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_O2SRD0B_OCI                                  , RULL(0xC00638C8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SRD0B_SCOM                                 , RULL(0x0006C719), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_O2SRD1A_OCI                                  , RULL(0xC0063948), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SRD1A_SCOM                                 , RULL(0x0006C729), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_O2SRD1B_OCI                                  , RULL(0xC00639C8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SRD1B_SCOM                                 , RULL(0x0006C739), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_O2SST0A_OCI                                  , RULL(0xC0063830), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SST0A_SCOM                                 , RULL(0x0006C706), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_O2SST0B_OCI                                  , RULL(0xC00638B0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SST0B_SCOM                                 , RULL(0x0006C716), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_O2SST1A_OCI                                  , RULL(0xC0063930), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SST1A_SCOM                                 , RULL(0x0006C726), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_O2SST1B_OCI                                  , RULL(0xC00639B0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SST1B_SCOM                                 , RULL(0x0006C736), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_O2SWD0A_OCI                                  , RULL(0xC0063840), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SWD0A_SCOM                                 , RULL(0x0006C708), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SWD0B_OCI                                  , RULL(0xC00638C0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SWD0B_SCOM                                 , RULL(0x0006C718), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SWD1A_OCI                                  , RULL(0xC0063940), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SWD1A_SCOM                                 , RULL(0x0006C728), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_O2SWD1B_OCI                                  , RULL(0xC00639C0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_O2SWD1B_SCOM                                 , RULL(0x0006C738), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBLWCR0_OCI                                 , RULL(0xC0061040), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBLWCR0_SCOM                                , RULL(0x0006C208), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBLWCR1_OCI                                 , RULL(0xC00610C0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBLWCR1_SCOM                                , RULL(0x0006C218), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBLWCR2_OCI                                 , RULL(0xC0061140), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBLWCR2_SCOM                                , RULL(0x0006C228), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBLWCR3_OCI                                 , RULL(0xC00611C0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBLWCR3_SCOM                                , RULL(0x0006C238), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBLWSBR0_OCI                                , RULL(0xC0061060), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBLWSBR0_SCOM                               , RULL(0x0006C20C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBLWSBR1_OCI                                , RULL(0xC00610E0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBLWSBR1_SCOM                               , RULL(0x0006C21C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBLWSBR2_OCI                                , RULL(0xC0061160), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBLWSBR2_SCOM                               , RULL(0x0006C22C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBLWSBR3_OCI                                , RULL(0xC00611E0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBLWSBR3_SCOM                               , RULL(0x0006C23C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBLWSR0_OCI                                 , RULL(0xC0061050), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBLWSR0_SCOM                                , RULL(0x0006C20A), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_OCBLWSR1_OCI                                 , RULL(0xC00610D0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBLWSR1_SCOM                                , RULL(0x0006C21A), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_OCBLWSR2_OCI                                 , RULL(0xC0061150), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBLWSR2_SCOM                                , RULL(0x0006C22A), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_OCBLWSR3_OCI                                 , RULL(0xC00611D0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBLWSR3_SCOM                                , RULL(0x0006C23A), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_OCBSES0_OCI                                  , RULL(0xC0061030), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSES0_SCOM                                 , RULL(0x0006C206), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBSES1_OCI                                  , RULL(0xC00610B0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSES1_SCOM                                 , RULL(0x0006C216), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBSES2_OCI                                  , RULL(0xC0061130), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSES2_SCOM                                 , RULL(0x0006C226), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBSES3_OCI                                  , RULL(0xC00611B0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSES3_SCOM                                 , RULL(0x0006C236), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBSHBR0_OCI                                 , RULL(0xC0061018), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSHBR0_SCOM                                , RULL(0x0006C203), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBSHBR1_OCI                                 , RULL(0xC0061098), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSHBR1_SCOM                                , RULL(0x0006C213), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBSHBR2_OCI                                 , RULL(0xC0061118), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSHBR2_SCOM                                , RULL(0x0006C223), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBSHBR3_OCI                                 , RULL(0xC0061198), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSHBR3_SCOM                                , RULL(0x0006C233), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBSHCS0_OCI                                 , RULL(0xC0061020), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSHCS0_SCOM                                , RULL(0x0006C204), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCBSHCS1_OCI                                 , RULL(0xC00610A0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSHCS1_SCOM                                , RULL(0x0006C214), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCBSHCS2_OCI                                 , RULL(0xC0061120), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSHCS2_SCOM                                , RULL(0x0006C224), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCBSHCS3_OCI                                 , RULL(0xC00611A0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSHCS3_SCOM                                , RULL(0x0006C234), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCBSHI0_OCI                                  , RULL(0xC0061028), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSHI0_SCOM                                 , RULL(0x0006C205), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCBSHI1_OCI                                  , RULL(0xC00610A8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSHI1_SCOM                                 , RULL(0x0006C215), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCBSHI2_OCI                                  , RULL(0xC0061128), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSHI2_SCOM                                 , RULL(0x0006C225), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCBSHI3_OCI                                  , RULL(0xC00611A8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSHI3_SCOM                                 , RULL(0x0006C235), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCBSLBR0_OCI                                 , RULL(0xC0061000), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSLBR0_SCOM                                , RULL(0x0006C200), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBSLBR1_OCI                                 , RULL(0xC0061080), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSLBR1_SCOM                                , RULL(0x0006C210), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBSLBR2_OCI                                 , RULL(0xC0061100), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSLBR2_SCOM                                , RULL(0x0006C220), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBSLBR3_OCI                                 , RULL(0xC0061180), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSLBR3_SCOM                                , RULL(0x0006C230), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCBSLCS0_OCI                                 , RULL(0xC0061008), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSLCS0_SCOM                                , RULL(0x0006C201), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCBSLCS1_OCI                                 , RULL(0xC0061088), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSLCS1_SCOM                                , RULL(0x0006C211), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCBSLCS2_OCI                                 , RULL(0xC0061108), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSLCS2_SCOM                                , RULL(0x0006C221), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCBSLCS3_OCI                                 , RULL(0xC0061188), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSLCS3_SCOM                                , RULL(0x0006C231), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCBSLI0_OCI                                  , RULL(0xC0061010), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSLI0_SCOM                                 , RULL(0x0006C202), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCBSLI1_OCI                                  , RULL(0xC0061090), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSLI1_SCOM                                 , RULL(0x0006C212), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCBSLI2_OCI                                  , RULL(0xC0061110), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSLI2_SCOM                                 , RULL(0x0006C222), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCBSLI3_OCI                                  , RULL(0xC0061190), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCBSLI3_SCOM                                 , RULL(0x0006C232), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OCCFLG_OCI                                   , RULL(0xC0060450), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCCFLG_OCI1                                  , RULL(0xC0060458), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OCCFLG_OCI2                                  , RULL(0xC0060460), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OCCFLG_SCOM                                  , RULL(0x0006C08A), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_OCCFLG_SCOM1                                 , RULL(0x0006C08B), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_OCCFLG_SCOM2                                 , RULL(0x0006C08C), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_OCCHBR_OCI                                   , RULL(0xC0060478), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCCHBR_SCOM                                  , RULL(0x0006C08F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCCMISC_OCI                                  , RULL(0xC0060400), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCCMISC_OCI1                                 , RULL(0xC0060408), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OCCMISC_OCI2                                 , RULL(0xC0060410), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OCCMISC_SCOM                                 , RULL(0x0006C080), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_OCB_OCI_OCCMISC_SCOM1                                , RULL(0x0006C081), SH_UNT          , SH_ACS_SCOM1     );
+REG64( PU_OCB_OCI_OCCMISC_SCOM2                                , RULL(0x0006C082), SH_UNT          , SH_ACS_SCOM2     );
+
+REG64( PU_OCB_OCI_OCCS0_OCI                                    , RULL(0xC0060430), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCCS0_SCOM                                   , RULL(0x0006C086), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCCS1_OCI                                    , RULL(0xC0060438), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCCS1_SCOM                                   , RULL(0x0006C087), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCCS2_OCI                                    , RULL(0xC0060440), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCCS2_SCOM                                   , RULL(0x0006C088), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCICFG_OCI                                   , RULL(0xC0060428), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCICFG_SCOM                                  , RULL(0x0006C085), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OCISR0_OCI                                   , RULL(0xC0060308), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCISR0_SCOM                                  , RULL(0x0006C061), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_OCISR1_OCI                                   , RULL(0xC0060388), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OCISR1_SCOM                                  , RULL(0x0006C071), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_ODISR0_OCI                                   , RULL(0xC0060318), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_ODISR0_SCOM                                  , RULL(0x0006C063), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_ODISR1_OCI                                   , RULL(0xC0060398), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_ODISR1_SCOM                                  , RULL(0x0006C073), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_OEHDR_OCI                                    , RULL(0xC0060420), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OEHDR_SCOM                                   , RULL(0x0006C084), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_OCI_OHTMCR_OCI                                   , RULL(0xC0060418), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OHTMCR_SCOM                                  , RULL(0x0006C083), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OIEPR0_OCI                                   , RULL(0xC0060060), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OIEPR0_OCI1                                  , RULL(0xC0060068), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OIEPR0_OCI2                                  , RULL(0xC0060070), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OIEPR0_SCOM                                  , RULL(0x0006C00C), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_OIEPR0_SCOM1                                 , RULL(0x0006C00D), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_OIEPR0_SCOM2                                 , RULL(0x0006C00E), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_OIEPR1_OCI                                   , RULL(0xC0060160), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OIEPR1_OCI1                                  , RULL(0xC0060168), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OIEPR1_OCI2                                  , RULL(0xC0060170), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OIEPR1_SCOM                                  , RULL(0x0006C02C), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_OIEPR1_SCOM1                                 , RULL(0x0006C02D), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_OIEPR1_SCOM2                                 , RULL(0x0006C02E), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_OIMR0_OCI                                    , RULL(0xC0060020), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OIMR0_OCI1                                   , RULL(0xC0060028), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OIMR0_OCI2                                   , RULL(0xC0060030), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OIMR0_SCOM                                   , RULL(0x0006C004), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_OIMR0_SCOM1                                  , RULL(0x0006C005), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_OIMR0_SCOM2                                  , RULL(0x0006C006), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_OIMR1_OCI                                    , RULL(0xC0060120), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OIMR1_OCI1                                   , RULL(0xC0060128), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OIMR1_OCI2                                   , RULL(0xC0060130), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OIMR1_SCOM                                   , RULL(0x0006C024), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_OIMR1_SCOM1                                  , RULL(0x0006C025), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_OIMR1_SCOM2                                  , RULL(0x0006C026), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_OIRR0A_OCI                                   , RULL(0xC0060200), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OIRR0A_OCI1                                  , RULL(0xC0060208), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OIRR0A_OCI2                                  , RULL(0xC0060210), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OIRR0A_SCOM                                  , RULL(0x0006C040), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_OIRR0A_SCOM1                                 , RULL(0x0006C041), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_OIRR0A_SCOM2                                 , RULL(0x0006C042), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_OIRR0B_OCI                                   , RULL(0xC0060220), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OIRR0B_OCI1                                  , RULL(0xC0060228), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OIRR0B_OCI2                                  , RULL(0xC0060230), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OIRR0B_SCOM                                  , RULL(0x0006C044), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_OIRR0B_SCOM1                                 , RULL(0x0006C045), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_OIRR0B_SCOM2                                 , RULL(0x0006C046), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_OIRR0C_OCI                                   , RULL(0xC0060240), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OIRR0C_OCI1                                  , RULL(0xC0060248), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OIRR0C_OCI2                                  , RULL(0xC0060250), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OIRR0C_SCOM                                  , RULL(0x0006C048), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_OIRR0C_SCOM1                                 , RULL(0x0006C049), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_OIRR0C_SCOM2                                 , RULL(0x0006C04A), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_OIRR1A_OCI                                   , RULL(0xC0060280), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OIRR1A_OCI1                                  , RULL(0xC0060288), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OIRR1A_OCI2                                  , RULL(0xC0060290), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OIRR1A_SCOM                                  , RULL(0x0006C050), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_OIRR1A_SCOM1                                 , RULL(0x0006C051), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_OIRR1A_SCOM2                                 , RULL(0x0006C052), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_OIRR1B_OCI                                   , RULL(0xC00602A0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OIRR1B_OCI1                                  , RULL(0xC00602A8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OIRR1B_OCI2                                  , RULL(0xC00602B0), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OIRR1B_SCOM                                  , RULL(0x0006C054), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_OIRR1B_SCOM1                                 , RULL(0x0006C055), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_OIRR1B_SCOM2                                 , RULL(0x0006C056), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_OIRR1C_OCI                                   , RULL(0xC00602C0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OIRR1C_OCI1                                  , RULL(0xC00602C8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OIRR1C_OCI2                                  , RULL(0xC00602D0), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OIRR1C_SCOM                                  , RULL(0x0006C058), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_OIRR1C_SCOM1                                 , RULL(0x0006C059), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_OIRR1C_SCOM2                                 , RULL(0x0006C05A), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_OISR0_OCI                                    , RULL(0xC0060000), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OISR0_OCI1                                   , RULL(0xC0060008), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OISR0_OCI2                                   , RULL(0xC0060010), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OISR0_SCOM                                   , RULL(0x0006C000), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OISR0_SCOM1                                  , RULL(0x0006C001), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_OISR0_SCOM2                                  , RULL(0x0006C002), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_OISR1_OCI                                    , RULL(0xC0060100), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OISR1_OCI1                                   , RULL(0xC0060108), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OISR1_OCI2                                   , RULL(0xC0060110), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OISR1_SCOM                                   , RULL(0x0006C020), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OISR1_SCOM1                                  , RULL(0x0006C021), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_OISR1_SCOM2                                  , RULL(0x0006C022), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_OITR0_OCI                                    , RULL(0xC0060040), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OITR0_OCI1                                   , RULL(0xC0060048), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OITR0_OCI2                                   , RULL(0xC0060050), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OITR0_SCOM                                   , RULL(0x0006C008), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_OITR0_SCOM1                                  , RULL(0x0006C009), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_OITR0_SCOM2                                  , RULL(0x0006C00A), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_OITR1_OCI                                    , RULL(0xC0060140), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OITR1_OCI1                                   , RULL(0xC0060148), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OITR1_OCI2                                   , RULL(0xC0060150), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_OITR1_SCOM                                   , RULL(0x0006C028), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_OITR1_SCOM1                                  , RULL(0x0006C029), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_OITR1_SCOM2                                  , RULL(0x0006C02A), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_ONISR0_OCI                                   , RULL(0xC0060300), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_ONISR0_SCOM                                  , RULL(0x0006C060), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_ONISR1_OCI                                   , RULL(0xC0060380), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_ONISR1_SCOM                                  , RULL(0x0006C070), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_OPIT0C0_OCI                                  , RULL(0xC0062000), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C0_OCI1                                 , RULL(0xC0062800), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C0_SCOM                                 , RULL(0x0006C400), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C0_SCOM1                                , RULL(0x0006C500), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C1_OCI                                  , RULL(0xC0062008), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C1_OCI1                                 , RULL(0xC0062808), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C1_SCOM                                 , RULL(0x0006C401), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C1_SCOM1                                , RULL(0x0006C501), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C10_OCI                                 , RULL(0xC0062050), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C10_OCI1                                , RULL(0xC0062850), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C10_SCOM                                , RULL(0x0006C40A), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C10_SCOM1                               , RULL(0x0006C50A), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C11_OCI                                 , RULL(0xC0062058), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C11_OCI1                                , RULL(0xC0062858), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C11_SCOM                                , RULL(0x0006C40B), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C11_SCOM1                               , RULL(0x0006C50B), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C12_OCI                                 , RULL(0xC0062060), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C12_OCI1                                , RULL(0xC0062860), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C12_SCOM                                , RULL(0x0006C40C), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C12_SCOM1                               , RULL(0x0006C50C), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C13_OCI                                 , RULL(0xC0062068), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C13_OCI1                                , RULL(0xC0062868), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C13_SCOM                                , RULL(0x0006C40D), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C13_SCOM1                               , RULL(0x0006C50D), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C14_OCI                                 , RULL(0xC0062070), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C14_OCI1                                , RULL(0xC0062870), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C14_SCOM                                , RULL(0x0006C40E), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C14_SCOM1                               , RULL(0x0006C50E), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C15_OCI                                 , RULL(0xC0062078), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C15_OCI1                                , RULL(0xC0062878), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C15_SCOM                                , RULL(0x0006C40F), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C15_SCOM1                               , RULL(0x0006C50F), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C16_OCI                                 , RULL(0xC0062080), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C16_OCI1                                , RULL(0xC0062880), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C16_SCOM                                , RULL(0x0006C410), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C16_SCOM1                               , RULL(0x0006C510), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C17_OCI                                 , RULL(0xC0062088), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C17_OCI1                                , RULL(0xC0062888), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C17_SCOM                                , RULL(0x0006C411), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C17_SCOM1                               , RULL(0x0006C511), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C18_OCI                                 , RULL(0xC0062090), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C18_OCI1                                , RULL(0xC0062890), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C18_SCOM                                , RULL(0x0006C412), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C18_SCOM1                               , RULL(0x0006C512), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C19_OCI                                 , RULL(0xC0062098), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C19_OCI1                                , RULL(0xC0062898), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C19_SCOM                                , RULL(0x0006C413), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C19_SCOM1                               , RULL(0x0006C513), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C2_OCI                                  , RULL(0xC0062010), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C2_OCI1                                 , RULL(0xC0062810), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C2_SCOM                                 , RULL(0x0006C402), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C2_SCOM1                                , RULL(0x0006C502), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C20_OCI                                 , RULL(0xC00620A0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C20_OCI1                                , RULL(0xC00628A0), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C20_SCOM                                , RULL(0x0006C414), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C20_SCOM1                               , RULL(0x0006C514), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C21_OCI                                 , RULL(0xC00620A8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C21_OCI1                                , RULL(0xC00628A8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C21_SCOM                                , RULL(0x0006C415), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C21_SCOM1                               , RULL(0x0006C515), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C22_OCI                                 , RULL(0xC00620B0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C22_OCI1                                , RULL(0xC00628B0), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C22_SCOM                                , RULL(0x0006C416), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C22_SCOM1                               , RULL(0x0006C516), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C23_OCI                                 , RULL(0xC00620B8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C23_OCI1                                , RULL(0xC00628B8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C23_SCOM                                , RULL(0x0006C417), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C23_SCOM1                               , RULL(0x0006C517), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C3_OCI                                  , RULL(0xC0062018), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C3_OCI1                                 , RULL(0xC0062818), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C3_SCOM                                 , RULL(0x0006C403), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C3_SCOM1                                , RULL(0x0006C503), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C4_OCI                                  , RULL(0xC0062020), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C4_OCI1                                 , RULL(0xC0062820), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C4_SCOM                                 , RULL(0x0006C404), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C4_SCOM1                                , RULL(0x0006C504), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C5_OCI                                  , RULL(0xC0062028), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C5_OCI1                                 , RULL(0xC0062828), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C5_SCOM                                 , RULL(0x0006C405), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C5_SCOM1                                , RULL(0x0006C505), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C6_OCI                                  , RULL(0xC0062030), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C6_OCI1                                 , RULL(0xC0062830), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C6_SCOM                                 , RULL(0x0006C406), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C6_SCOM1                                , RULL(0x0006C506), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C7_OCI                                  , RULL(0xC0062038), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C7_OCI1                                 , RULL(0xC0062838), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C7_SCOM                                 , RULL(0x0006C407), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C7_SCOM1                                , RULL(0x0006C507), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C8_OCI                                  , RULL(0xC0062040), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C8_OCI1                                 , RULL(0xC0062840), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C8_SCOM                                 , RULL(0x0006C408), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C8_SCOM1                                , RULL(0x0006C508), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0C9_OCI                                  , RULL(0xC0062048), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0C9_OCI1                                 , RULL(0xC0062848), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0C9_SCOM                                 , RULL(0x0006C409), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0C9_SCOM1                                , RULL(0x0006C509), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT0PRA_OCI                                 , RULL(0xC0063000), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT0PRA_OCI1                                , RULL(0xC0063008), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT0PRA_SCOM                                , RULL(0x0006C600), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT0PRA_SCOM1                               , RULL(0x0006C601), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_OCB_OCI_OPIT1C0_OCI                                  , RULL(0xC0062100), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C0_OCI1                                 , RULL(0xC0062900), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C0_SCOM                                 , RULL(0x0006C420), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C0_SCOM1                                , RULL(0x0006C520), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C1_OCI                                  , RULL(0xC0062108), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C1_OCI1                                 , RULL(0xC0062908), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C1_SCOM                                 , RULL(0x0006C421), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C1_SCOM1                                , RULL(0x0006C521), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C10_OCI                                 , RULL(0xC0062150), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C10_OCI1                                , RULL(0xC0062950), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C10_SCOM                                , RULL(0x0006C42A), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C10_SCOM1                               , RULL(0x0006C52A), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C11_OCI                                 , RULL(0xC0062158), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C11_OCI1                                , RULL(0xC0062958), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C11_SCOM                                , RULL(0x0006C42B), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C11_SCOM1                               , RULL(0x0006C52B), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C12_OCI                                 , RULL(0xC0062160), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C12_OCI1                                , RULL(0xC0062960), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C12_SCOM                                , RULL(0x0006C42C), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C12_SCOM1                               , RULL(0x0006C52C), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C13_OCI                                 , RULL(0xC0062168), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C13_OCI1                                , RULL(0xC0062968), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C13_SCOM                                , RULL(0x0006C42D), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C13_SCOM1                               , RULL(0x0006C52D), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C14_OCI                                 , RULL(0xC0062170), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C14_OCI1                                , RULL(0xC0062970), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C14_SCOM                                , RULL(0x0006C42E), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C14_SCOM1                               , RULL(0x0006C52E), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C15_OCI                                 , RULL(0xC0062178), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C15_OCI1                                , RULL(0xC0062978), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C15_SCOM                                , RULL(0x0006C42F), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C15_SCOM1                               , RULL(0x0006C52F), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C16_OCI                                 , RULL(0xC0062180), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C16_OCI1                                , RULL(0xC0062980), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C16_SCOM                                , RULL(0x0006C430), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C16_SCOM1                               , RULL(0x0006C530), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C17_OCI                                 , RULL(0xC0062188), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C17_OCI1                                , RULL(0xC0062988), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C17_SCOM                                , RULL(0x0006C431), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C17_SCOM1                               , RULL(0x0006C531), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C18_OCI                                 , RULL(0xC0062190), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C18_OCI1                                , RULL(0xC0062990), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C18_SCOM                                , RULL(0x0006C432), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C18_SCOM1                               , RULL(0x0006C532), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C19_OCI                                 , RULL(0xC0062198), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C19_OCI1                                , RULL(0xC0062998), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C19_SCOM                                , RULL(0x0006C433), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C19_SCOM1                               , RULL(0x0006C533), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C2_OCI                                  , RULL(0xC0062110), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C2_OCI1                                 , RULL(0xC0062910), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C2_SCOM                                 , RULL(0x0006C422), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C2_SCOM1                                , RULL(0x0006C522), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C20_OCI                                 , RULL(0xC00621A0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C20_OCI1                                , RULL(0xC00629A0), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C20_SCOM                                , RULL(0x0006C434), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C20_SCOM1                               , RULL(0x0006C534), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C21_OCI                                 , RULL(0xC00621A8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C21_OCI1                                , RULL(0xC00629A8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C21_SCOM                                , RULL(0x0006C435), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C21_SCOM1                               , RULL(0x0006C535), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C22_OCI                                 , RULL(0xC00621B0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C22_OCI1                                , RULL(0xC00629B0), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C22_SCOM                                , RULL(0x0006C436), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C22_SCOM1                               , RULL(0x0006C536), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C23_OCI                                 , RULL(0xC00621B8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C23_OCI1                                , RULL(0xC00629B8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C23_SCOM                                , RULL(0x0006C437), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C23_SCOM1                               , RULL(0x0006C537), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C3_OCI                                  , RULL(0xC0062118), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C3_OCI1                                 , RULL(0xC0062918), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C3_SCOM                                 , RULL(0x0006C423), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C3_SCOM1                                , RULL(0x0006C523), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C4_OCI                                  , RULL(0xC0062120), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C4_OCI1                                 , RULL(0xC0062920), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C4_SCOM                                 , RULL(0x0006C424), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C4_SCOM1                                , RULL(0x0006C524), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C5_OCI                                  , RULL(0xC0062128), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C5_OCI1                                 , RULL(0xC0062928), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C5_SCOM                                 , RULL(0x0006C425), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C5_SCOM1                                , RULL(0x0006C525), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C6_OCI                                  , RULL(0xC0062130), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C6_OCI1                                 , RULL(0xC0062930), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C6_SCOM                                 , RULL(0x0006C426), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C6_SCOM1                                , RULL(0x0006C526), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C7_OCI                                  , RULL(0xC0062138), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C7_OCI1                                 , RULL(0xC0062938), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C7_SCOM                                 , RULL(0x0006C427), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C7_SCOM1                                , RULL(0x0006C527), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C8_OCI                                  , RULL(0xC0062140), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C8_OCI1                                 , RULL(0xC0062940), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C8_SCOM                                 , RULL(0x0006C428), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C8_SCOM1                                , RULL(0x0006C528), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1C9_OCI                                  , RULL(0xC0062148), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1C9_OCI1                                 , RULL(0xC0062948), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1C9_SCOM                                 , RULL(0x0006C429), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1C9_SCOM1                                , RULL(0x0006C529), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT1PRA_OCI                                 , RULL(0xC0063100), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT1PRA_OCI1                                , RULL(0xC0063108), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT1PRA_SCOM                                , RULL(0x0006C620), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT1PRA_SCOM1                               , RULL(0x0006C621), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_OCB_OCI_OPIT2C0_OCI                                  , RULL(0xC0062200), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C0_OCI1                                 , RULL(0xC0062A00), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C0_SCOM                                 , RULL(0x0006C440), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C0_SCOM1                                , RULL(0x0006C540), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C1_OCI                                  , RULL(0xC0062208), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C1_OCI1                                 , RULL(0xC0062A08), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C1_SCOM                                 , RULL(0x0006C441), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C1_SCOM1                                , RULL(0x0006C541), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C10_OCI                                 , RULL(0xC0062250), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C10_OCI1                                , RULL(0xC0062A50), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C10_SCOM                                , RULL(0x0006C44A), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C10_SCOM1                               , RULL(0x0006C54A), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C11_OCI                                 , RULL(0xC0062258), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C11_OCI1                                , RULL(0xC0062A58), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C11_SCOM                                , RULL(0x0006C44B), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C11_SCOM1                               , RULL(0x0006C54B), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C12_OCI                                 , RULL(0xC0062260), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C12_OCI1                                , RULL(0xC0062A60), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C12_SCOM                                , RULL(0x0006C44C), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C12_SCOM1                               , RULL(0x0006C54C), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C13_OCI                                 , RULL(0xC0062268), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C13_OCI1                                , RULL(0xC0062A68), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C13_SCOM                                , RULL(0x0006C44D), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C13_SCOM1                               , RULL(0x0006C54D), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C14_OCI                                 , RULL(0xC0062270), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C14_OCI1                                , RULL(0xC0062A70), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C14_SCOM                                , RULL(0x0006C44E), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C14_SCOM1                               , RULL(0x0006C54E), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C15_OCI                                 , RULL(0xC0062278), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C15_OCI1                                , RULL(0xC0062A78), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C15_SCOM                                , RULL(0x0006C44F), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C15_SCOM1                               , RULL(0x0006C54F), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C16_OCI                                 , RULL(0xC0062280), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C16_OCI1                                , RULL(0xC0062A80), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C16_SCOM                                , RULL(0x0006C450), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C16_SCOM1                               , RULL(0x0006C550), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C17_OCI                                 , RULL(0xC0062288), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C17_OCI1                                , RULL(0xC0062A88), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C17_SCOM                                , RULL(0x0006C451), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C17_SCOM1                               , RULL(0x0006C551), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C18_OCI                                 , RULL(0xC0062290), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C18_OCI1                                , RULL(0xC0062A90), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C18_SCOM                                , RULL(0x0006C452), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C18_SCOM1                               , RULL(0x0006C552), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C19_OCI                                 , RULL(0xC0062298), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C19_OCI1                                , RULL(0xC0062A98), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C19_SCOM                                , RULL(0x0006C453), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C19_SCOM1                               , RULL(0x0006C553), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C2_OCI                                  , RULL(0xC0062210), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C2_OCI1                                 , RULL(0xC0062A10), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C2_SCOM                                 , RULL(0x0006C442), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C2_SCOM1                                , RULL(0x0006C542), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C20_OCI                                 , RULL(0xC00622A0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C20_OCI1                                , RULL(0xC0062AA0), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C20_SCOM                                , RULL(0x0006C454), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C20_SCOM1                               , RULL(0x0006C554), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C21_OCI                                 , RULL(0xC00622A8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C21_OCI1                                , RULL(0xC0062AA8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C21_SCOM                                , RULL(0x0006C455), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C21_SCOM1                               , RULL(0x0006C555), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C22_OCI                                 , RULL(0xC00622B0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C22_OCI1                                , RULL(0xC0062AB0), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C22_SCOM                                , RULL(0x0006C456), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C22_SCOM1                               , RULL(0x0006C556), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C23_OCI                                 , RULL(0xC00622B8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C23_OCI1                                , RULL(0xC0062AB8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C23_SCOM                                , RULL(0x0006C457), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C23_SCOM1                               , RULL(0x0006C557), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C3_OCI                                  , RULL(0xC0062218), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C3_OCI1                                 , RULL(0xC0062A18), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C3_SCOM                                 , RULL(0x0006C443), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C3_SCOM1                                , RULL(0x0006C543), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C4_OCI                                  , RULL(0xC0062220), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C4_OCI1                                 , RULL(0xC0062A20), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C4_SCOM                                 , RULL(0x0006C444), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C4_SCOM1                                , RULL(0x0006C544), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C5_OCI                                  , RULL(0xC0062228), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C5_OCI1                                 , RULL(0xC0062A28), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C5_SCOM                                 , RULL(0x0006C445), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C5_SCOM1                                , RULL(0x0006C545), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C6_OCI                                  , RULL(0xC0062230), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C6_OCI1                                 , RULL(0xC0062A30), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C6_SCOM                                 , RULL(0x0006C446), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C6_SCOM1                                , RULL(0x0006C546), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C7_OCI                                  , RULL(0xC0062238), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C7_OCI1                                 , RULL(0xC0062A38), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C7_SCOM                                 , RULL(0x0006C447), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C7_SCOM1                                , RULL(0x0006C547), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C8_OCI                                  , RULL(0xC0062240), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C8_OCI1                                 , RULL(0xC0062A40), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C8_SCOM                                 , RULL(0x0006C448), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C8_SCOM1                                , RULL(0x0006C548), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2C9_OCI                                  , RULL(0xC0062248), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2C9_OCI1                                 , RULL(0xC0062A48), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2C9_SCOM                                 , RULL(0x0006C449), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2C9_SCOM1                                , RULL(0x0006C549), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT2PRA_OCI                                 , RULL(0xC0063200), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT2PRA_OCI1                                , RULL(0xC0063208), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT2PRA_SCOM                                , RULL(0x0006C640), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT2PRA_SCOM1                               , RULL(0x0006C641), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_OCB_OCI_OPIT3C0_OCI                                  , RULL(0xC0062300), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C0_OCI1                                 , RULL(0xC0062B00), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C0_SCOM                                 , RULL(0x0006C460), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C0_SCOM1                                , RULL(0x0006C560), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C1_OCI                                  , RULL(0xC0062308), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C1_OCI1                                 , RULL(0xC0062B08), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C1_SCOM                                 , RULL(0x0006C461), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C1_SCOM1                                , RULL(0x0006C561), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C10_OCI                                 , RULL(0xC0062350), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C10_OCI1                                , RULL(0xC0062B50), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C10_SCOM                                , RULL(0x0006C46A), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C10_SCOM1                               , RULL(0x0006C56A), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C11_OCI                                 , RULL(0xC0062358), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C11_OCI1                                , RULL(0xC0062B58), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C11_SCOM                                , RULL(0x0006C46B), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C11_SCOM1                               , RULL(0x0006C56B), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C12_OCI                                 , RULL(0xC0062360), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C12_OCI1                                , RULL(0xC0062B60), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C12_SCOM                                , RULL(0x0006C46C), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C12_SCOM1                               , RULL(0x0006C56C), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C13_OCI                                 , RULL(0xC0062368), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C13_OCI1                                , RULL(0xC0062B68), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C13_SCOM                                , RULL(0x0006C46D), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C13_SCOM1                               , RULL(0x0006C56D), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C14_OCI                                 , RULL(0xC0062370), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C14_OCI1                                , RULL(0xC0062B70), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C14_SCOM                                , RULL(0x0006C46E), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C14_SCOM1                               , RULL(0x0006C56E), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C15_OCI                                 , RULL(0xC0062378), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C15_OCI1                                , RULL(0xC0062B78), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C15_SCOM                                , RULL(0x0006C46F), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C15_SCOM1                               , RULL(0x0006C56F), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C16_OCI                                 , RULL(0xC0062380), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C16_OCI1                                , RULL(0xC0062B80), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C16_SCOM                                , RULL(0x0006C470), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C16_SCOM1                               , RULL(0x0006C570), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C17_OCI                                 , RULL(0xC0062388), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C17_OCI1                                , RULL(0xC0062B88), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C17_SCOM                                , RULL(0x0006C471), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C17_SCOM1                               , RULL(0x0006C571), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C18_OCI                                 , RULL(0xC0062390), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C18_OCI1                                , RULL(0xC0062B90), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C18_SCOM                                , RULL(0x0006C472), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C18_SCOM1                               , RULL(0x0006C572), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C19_OCI                                 , RULL(0xC0062398), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C19_OCI1                                , RULL(0xC0062B98), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C19_SCOM                                , RULL(0x0006C473), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C19_SCOM1                               , RULL(0x0006C573), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C2_OCI                                  , RULL(0xC0062310), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C2_OCI1                                 , RULL(0xC0062B10), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C2_SCOM                                 , RULL(0x0006C462), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C2_SCOM1                                , RULL(0x0006C562), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C20_OCI                                 , RULL(0xC00623A0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C20_OCI1                                , RULL(0xC0062BA0), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C20_SCOM                                , RULL(0x0006C474), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C20_SCOM1                               , RULL(0x0006C574), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C21_OCI                                 , RULL(0xC00623A8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C21_OCI1                                , RULL(0xC0062BA8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C21_SCOM                                , RULL(0x0006C475), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C21_SCOM1                               , RULL(0x0006C575), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C22_OCI                                 , RULL(0xC00623B0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C22_OCI1                                , RULL(0xC0062BB0), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C22_SCOM                                , RULL(0x0006C476), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C22_SCOM1                               , RULL(0x0006C576), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C23_OCI                                 , RULL(0xC00623B8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C23_OCI1                                , RULL(0xC0062BB8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C23_SCOM                                , RULL(0x0006C477), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C23_SCOM1                               , RULL(0x0006C577), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C3_OCI                                  , RULL(0xC0062318), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C3_OCI1                                 , RULL(0xC0062B18), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C3_SCOM                                 , RULL(0x0006C463), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C3_SCOM1                                , RULL(0x0006C563), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C4_OCI                                  , RULL(0xC0062320), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C4_OCI1                                 , RULL(0xC0062B20), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C4_SCOM                                 , RULL(0x0006C464), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C4_SCOM1                                , RULL(0x0006C564), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C5_OCI                                  , RULL(0xC0062328), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C5_OCI1                                 , RULL(0xC0062B28), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C5_SCOM                                 , RULL(0x0006C465), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C5_SCOM1                                , RULL(0x0006C565), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C6_OCI                                  , RULL(0xC0062330), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C6_OCI1                                 , RULL(0xC0062B30), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C6_SCOM                                 , RULL(0x0006C466), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C6_SCOM1                                , RULL(0x0006C566), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C7_OCI                                  , RULL(0xC0062338), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C7_OCI1                                 , RULL(0xC0062B38), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C7_SCOM                                 , RULL(0x0006C467), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C7_SCOM1                                , RULL(0x0006C567), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C8_OCI                                  , RULL(0xC0062340), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C8_OCI1                                 , RULL(0xC0062B40), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C8_SCOM                                 , RULL(0x0006C468), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C8_SCOM1                                , RULL(0x0006C568), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3C9_OCI                                  , RULL(0xC0062348), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3C9_OCI1                                 , RULL(0xC0062B48), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3C9_SCOM                                 , RULL(0x0006C469), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3C9_SCOM1                                , RULL(0x0006C569), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT3PRA_OCI                                 , RULL(0xC0063300), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT3PRA_OCI1                                , RULL(0xC0063308), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT3PRA_SCOM                                , RULL(0x0006C660), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT3PRA_SCOM1                               , RULL(0x0006C661), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_OCB_OCI_OPIT4C0_OCI                                  , RULL(0xC0062400), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C0_OCI1                                 , RULL(0xC0062C00), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C0_SCOM                                 , RULL(0x0006C480), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C0_SCOM1                                , RULL(0x0006C580), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C1_OCI                                  , RULL(0xC0062408), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C1_OCI1                                 , RULL(0xC0062C08), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C1_SCOM                                 , RULL(0x0006C481), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C1_SCOM1                                , RULL(0x0006C581), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C10_OCI                                 , RULL(0xC0062450), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C10_OCI1                                , RULL(0xC0062C50), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C10_SCOM                                , RULL(0x0006C48A), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C10_SCOM1                               , RULL(0x0006C58A), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C11_OCI                                 , RULL(0xC0062458), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C11_OCI1                                , RULL(0xC0062C58), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C11_SCOM                                , RULL(0x0006C48B), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C11_SCOM1                               , RULL(0x0006C58B), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C12_OCI                                 , RULL(0xC0062460), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C12_OCI1                                , RULL(0xC0062C60), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C12_SCOM                                , RULL(0x0006C48C), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C12_SCOM1                               , RULL(0x0006C58C), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C13_OCI                                 , RULL(0xC0062468), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C13_OCI1                                , RULL(0xC0062C68), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C13_SCOM                                , RULL(0x0006C48D), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C13_SCOM1                               , RULL(0x0006C58D), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C14_OCI                                 , RULL(0xC0062470), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C14_OCI1                                , RULL(0xC0062C70), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C14_SCOM                                , RULL(0x0006C48E), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C14_SCOM1                               , RULL(0x0006C58E), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C15_OCI                                 , RULL(0xC0062478), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C15_OCI1                                , RULL(0xC0062C78), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C15_SCOM                                , RULL(0x0006C48F), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C15_SCOM1                               , RULL(0x0006C58F), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C16_OCI                                 , RULL(0xC0062480), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C16_OCI1                                , RULL(0xC0062C80), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C16_SCOM                                , RULL(0x0006C490), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C16_SCOM1                               , RULL(0x0006C590), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C17_OCI                                 , RULL(0xC0062488), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C17_OCI1                                , RULL(0xC0062C88), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C17_SCOM                                , RULL(0x0006C491), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C17_SCOM1                               , RULL(0x0006C591), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C18_OCI                                 , RULL(0xC0062490), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C18_OCI1                                , RULL(0xC0062C90), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C18_SCOM                                , RULL(0x0006C492), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C18_SCOM1                               , RULL(0x0006C592), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C19_OCI                                 , RULL(0xC0062498), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C19_OCI1                                , RULL(0xC0062C98), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C19_SCOM                                , RULL(0x0006C493), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C19_SCOM1                               , RULL(0x0006C593), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C2_OCI                                  , RULL(0xC0062410), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C2_OCI1                                 , RULL(0xC0062C10), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C2_SCOM                                 , RULL(0x0006C482), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C2_SCOM1                                , RULL(0x0006C582), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C20_OCI                                 , RULL(0xC00624A0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C20_OCI1                                , RULL(0xC0062CA0), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C20_SCOM                                , RULL(0x0006C494), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C20_SCOM1                               , RULL(0x0006C594), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C21_OCI                                 , RULL(0xC00624A8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C21_OCI1                                , RULL(0xC0062CA8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C21_SCOM                                , RULL(0x0006C495), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C21_SCOM1                               , RULL(0x0006C595), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C22_OCI                                 , RULL(0xC00624B0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C22_OCI1                                , RULL(0xC0062CB0), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C22_SCOM                                , RULL(0x0006C496), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C22_SCOM1                               , RULL(0x0006C596), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C23_OCI                                 , RULL(0xC00624B8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C23_OCI1                                , RULL(0xC0062CB8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C23_SCOM                                , RULL(0x0006C497), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C23_SCOM1                               , RULL(0x0006C597), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C3_OCI                                  , RULL(0xC0062418), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C3_OCI1                                 , RULL(0xC0062C18), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C3_SCOM                                 , RULL(0x0006C483), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C3_SCOM1                                , RULL(0x0006C583), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C4_OCI                                  , RULL(0xC0062420), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C4_OCI1                                 , RULL(0xC0062C20), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C4_SCOM                                 , RULL(0x0006C484), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C4_SCOM1                                , RULL(0x0006C584), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C5_OCI                                  , RULL(0xC0062428), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C5_OCI1                                 , RULL(0xC0062C28), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C5_SCOM                                 , RULL(0x0006C485), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C5_SCOM1                                , RULL(0x0006C585), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C6_OCI                                  , RULL(0xC0062430), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C6_OCI1                                 , RULL(0xC0062C30), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C6_SCOM                                 , RULL(0x0006C486), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C6_SCOM1                                , RULL(0x0006C586), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C7_OCI                                  , RULL(0xC0062438), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C7_OCI1                                 , RULL(0xC0062C38), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C7_SCOM                                 , RULL(0x0006C487), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C7_SCOM1                                , RULL(0x0006C587), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C8_OCI                                  , RULL(0xC0062440), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C8_OCI1                                 , RULL(0xC0062C40), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C8_SCOM                                 , RULL(0x0006C488), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C8_SCOM1                                , RULL(0x0006C588), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4C9_OCI                                  , RULL(0xC0062448), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4C9_OCI1                                 , RULL(0xC0062C48), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4C9_SCOM                                 , RULL(0x0006C489), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4C9_SCOM1                                , RULL(0x0006C589), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT4PRA_OCI                                 , RULL(0xC0063400), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT4PRA_OCI1                                , RULL(0xC0063408), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT4PRA_SCOM                                , RULL(0x0006C680), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT4PRA_SCOM1                               , RULL(0x0006C681), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_OCB_OCI_OPIT5C0_OCI                                  , RULL(0xC0062500), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C0_OCI1                                 , RULL(0xC0062D00), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C0_SCOM                                 , RULL(0x0006C4A0), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C0_SCOM1                                , RULL(0x0006C5A0), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C1_OCI                                  , RULL(0xC0062508), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C1_OCI1                                 , RULL(0xC0062D08), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C1_SCOM                                 , RULL(0x0006C4A1), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C1_SCOM1                                , RULL(0x0006C5A1), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C10_OCI                                 , RULL(0xC0062550), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C10_OCI1                                , RULL(0xC0062D50), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C10_SCOM                                , RULL(0x0006C4AA), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C10_SCOM1                               , RULL(0x0006C5AA), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C11_OCI                                 , RULL(0xC0062558), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C11_OCI1                                , RULL(0xC0062D58), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C11_SCOM                                , RULL(0x0006C4AB), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C11_SCOM1                               , RULL(0x0006C5AB), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C12_OCI                                 , RULL(0xC0062560), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C12_OCI1                                , RULL(0xC0062D60), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C12_SCOM                                , RULL(0x0006C4AC), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C12_SCOM1                               , RULL(0x0006C5AC), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C13_OCI                                 , RULL(0xC0062568), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C13_OCI1                                , RULL(0xC0062D68), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C13_SCOM                                , RULL(0x0006C4AD), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C13_SCOM1                               , RULL(0x0006C5AD), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C14_OCI                                 , RULL(0xC0062570), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C14_OCI1                                , RULL(0xC0062D70), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C14_SCOM                                , RULL(0x0006C4AE), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C14_SCOM1                               , RULL(0x0006C5AE), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C15_OCI                                 , RULL(0xC0062578), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C15_OCI1                                , RULL(0xC0062D78), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C15_SCOM                                , RULL(0x0006C4AF), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C15_SCOM1                               , RULL(0x0006C5AF), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C16_OCI                                 , RULL(0xC0062580), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C16_OCI1                                , RULL(0xC0062D80), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C16_SCOM                                , RULL(0x0006C4B0), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C16_SCOM1                               , RULL(0x0006C5B0), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C17_OCI                                 , RULL(0xC0062588), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C17_OCI1                                , RULL(0xC0062D88), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C17_SCOM                                , RULL(0x0006C4B1), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C17_SCOM1                               , RULL(0x0006C5B1), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C18_OCI                                 , RULL(0xC0062590), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C18_OCI1                                , RULL(0xC0062D90), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C18_SCOM                                , RULL(0x0006C4B2), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C18_SCOM1                               , RULL(0x0006C5B2), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C19_OCI                                 , RULL(0xC0062598), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C19_OCI1                                , RULL(0xC0062D98), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C19_SCOM                                , RULL(0x0006C4B3), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C19_SCOM1                               , RULL(0x0006C5B3), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C2_OCI                                  , RULL(0xC0062510), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C2_OCI1                                 , RULL(0xC0062D10), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C2_SCOM                                 , RULL(0x0006C4A2), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C2_SCOM1                                , RULL(0x0006C5A2), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C20_OCI                                 , RULL(0xC00625A0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C20_OCI1                                , RULL(0xC0062DA0), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C20_SCOM                                , RULL(0x0006C4B4), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C20_SCOM1                               , RULL(0x0006C5B4), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C21_OCI                                 , RULL(0xC00625A8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C21_OCI1                                , RULL(0xC0062DA8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C21_SCOM                                , RULL(0x0006C4B5), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C21_SCOM1                               , RULL(0x0006C5B5), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C22_OCI                                 , RULL(0xC00625B0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C22_OCI1                                , RULL(0xC0062DB0), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C22_SCOM                                , RULL(0x0006C4B6), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C22_SCOM1                               , RULL(0x0006C5B6), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C23_OCI                                 , RULL(0xC00625B8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C23_OCI1                                , RULL(0xC0062DB8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C23_SCOM                                , RULL(0x0006C4B7), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C23_SCOM1                               , RULL(0x0006C5B7), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C3_OCI                                  , RULL(0xC0062518), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C3_OCI1                                 , RULL(0xC0062D18), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C3_SCOM                                 , RULL(0x0006C4A3), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C3_SCOM1                                , RULL(0x0006C5A3), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C4_OCI                                  , RULL(0xC0062520), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C4_OCI1                                 , RULL(0xC0062D20), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C4_SCOM                                 , RULL(0x0006C4A4), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C4_SCOM1                                , RULL(0x0006C5A4), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C5_OCI                                  , RULL(0xC0062528), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C5_OCI1                                 , RULL(0xC0062D28), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C5_SCOM                                 , RULL(0x0006C4A5), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C5_SCOM1                                , RULL(0x0006C5A5), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C6_OCI                                  , RULL(0xC0062530), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C6_OCI1                                 , RULL(0xC0062D30), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C6_SCOM                                 , RULL(0x0006C4A6), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C6_SCOM1                                , RULL(0x0006C5A6), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C7_OCI                                  , RULL(0xC0062538), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C7_OCI1                                 , RULL(0xC0062D38), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C7_SCOM                                 , RULL(0x0006C4A7), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C7_SCOM1                                , RULL(0x0006C5A7), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C8_OCI                                  , RULL(0xC0062540), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C8_OCI1                                 , RULL(0xC0062D40), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C8_SCOM                                 , RULL(0x0006C4A8), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C8_SCOM1                                , RULL(0x0006C5A8), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5C9_OCI                                  , RULL(0xC0062548), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5C9_OCI1                                 , RULL(0xC0062D48), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5C9_SCOM                                 , RULL(0x0006C4A9), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5C9_SCOM1                                , RULL(0x0006C5A9), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT5PRA_OCI                                 , RULL(0xC0063500), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT5PRA_OCI1                                , RULL(0xC0063508), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT5PRA_SCOM                                , RULL(0x0006C6A0), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT5PRA_SCOM1                               , RULL(0x0006C6A1), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_OCB_OCI_OPIT6PRB_OCI                                 , RULL(0xC0063600), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT6PRB_OCI1                                , RULL(0xC0063608), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT6PRB_SCOM                                , RULL(0x0006C6C0), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT6PRB_SCOM1                               , RULL(0x0006C6C1), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_OCB_OCI_OPIT6Q0_OCI                                  , RULL(0xC0062600), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT6Q0_OCI1                                 , RULL(0xC0062E00), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT6Q0_SCOM                                 , RULL(0x0006C4C0), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT6Q0_SCOM1                                , RULL(0x0006C5C0), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT6Q1_OCI                                  , RULL(0xC0062608), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT6Q1_OCI1                                 , RULL(0xC0062E08), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT6Q1_SCOM                                 , RULL(0x0006C4C1), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT6Q1_SCOM1                                , RULL(0x0006C5C1), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT6Q2_OCI                                  , RULL(0xC0062610), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT6Q2_OCI1                                 , RULL(0xC0062E10), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT6Q2_SCOM                                 , RULL(0x0006C4C2), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT6Q2_SCOM1                                , RULL(0x0006C5C2), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT6Q3_OCI                                  , RULL(0xC0062618), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT6Q3_OCI1                                 , RULL(0xC0062E18), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT6Q3_SCOM                                 , RULL(0x0006C4C3), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT6Q3_SCOM1                                , RULL(0x0006C5C3), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT6Q4_OCI                                  , RULL(0xC0062620), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT6Q4_OCI1                                 , RULL(0xC0062E20), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT6Q4_SCOM                                 , RULL(0x0006C4C4), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT6Q4_SCOM1                                , RULL(0x0006C5C4), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT6Q5_OCI                                  , RULL(0xC0062628), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT6Q5_OCI1                                 , RULL(0xC0062E28), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT6Q5_SCOM                                 , RULL(0x0006C4C5), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT6Q5_SCOM1                                , RULL(0x0006C5C5), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT7PRB_OCI                                 , RULL(0xC0063700), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT7PRB_OCI1                                , RULL(0xC0063708), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT7PRB_SCOM                                , RULL(0x0006C6E0), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT7PRB_SCOM1                               , RULL(0x0006C6E1), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+
+REG64( PU_OCB_OCI_OPIT7Q0_OCI                                  , RULL(0xC0062700), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT7Q0_OCI1                                 , RULL(0xC0062F00), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT7Q0_SCOM                                 , RULL(0x0006C4E0), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT7Q0_SCOM1                                , RULL(0x0006C5E0), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT7Q1_OCI                                  , RULL(0xC0062708), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT7Q1_OCI1                                 , RULL(0xC0062F08), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT7Q1_SCOM                                 , RULL(0x0006C4E1), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT7Q1_SCOM1                                , RULL(0x0006C5E1), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT7Q2_OCI                                  , RULL(0xC0062710), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT7Q2_OCI1                                 , RULL(0xC0062F10), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT7Q2_SCOM                                 , RULL(0x0006C4E2), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT7Q2_SCOM1                                , RULL(0x0006C5E2), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT7Q3_OCI                                  , RULL(0xC0062718), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT7Q3_OCI1                                 , RULL(0xC0062F18), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT7Q3_SCOM                                 , RULL(0x0006C4E3), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT7Q3_SCOM1                                , RULL(0x0006C5E3), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT7Q4_OCI                                  , RULL(0xC0062720), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT7Q4_OCI1                                 , RULL(0xC0062F20), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT7Q4_SCOM                                 , RULL(0x0006C4E4), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT7Q4_SCOM1                                , RULL(0x0006C5E4), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OPIT7Q5_OCI                                  , RULL(0xC0062728), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OPIT7Q5_OCI1                                 , RULL(0xC0062F28), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_OPIT7Q5_SCOM                                 , RULL(0x0006C4E5), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_OCI_OPIT7Q5_SCOM1                                , RULL(0x0006C5E5), SH_UNT          , SH_ACS_SCOM1_RO  );
+
+REG64( PU_OCB_OCI_OTBR_OCI                                     , RULL(0xC00604F8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OTBR_SCOM                                    , RULL(0x0006C09F), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_OTR0_OCI                                     , RULL(0xC0060800), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OTR0_SCOM                                    , RULL(0x0006C100), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OTR1_OCI                                     , RULL(0xC0060808), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OTR1_SCOM                                    , RULL(0x0006C101), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_OCI_OUISR0_OCI                                   , RULL(0xC0060310), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OUISR0_SCOM                                  , RULL(0x0006C062), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_OUISR1_OCI                                   , RULL(0xC0060390), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_OUISR1_SCOM                                  , RULL(0x0006C072), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_OCI_QCSR_OCI                                     , RULL(0xC00604A0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_QCSR_OCI1                                    , RULL(0xC00604A8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_QCSR_OCI2                                    , RULL(0xC00604B0), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_QCSR_SCOM                                    , RULL(0x0006C094), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_QCSR_SCOM1                                   , RULL(0x0006C095), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_QCSR_SCOM2                                   , RULL(0x0006C096), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_OCI_QSSR_OCI                                     , RULL(0xC00604C0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_OCB_OCI_QSSR_OCI1                                    , RULL(0xC00604C8), SH_UNT          , SH_ACS_OCI1      );
+REG64( PU_OCB_OCI_QSSR_OCI2                                    , RULL(0xC00604D0), SH_UNT          , SH_ACS_OCI2      );
+REG64( PU_OCB_OCI_QSSR_SCOM                                    , RULL(0x0006C098), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_OCB_OCI_QSSR_SCOM1                                   , RULL(0x0006C099), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_OCI_QSSR_SCOM2                                   , RULL(0x0006C09A), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_PIB_OACR                                         , RULL(0x0006D207), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_PIB_OCBAR0                                       , RULL(0x0006D010), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_PIB_OCBAR1                                       , RULL(0x0006D030), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_PIB_OCBAR2                                       , RULL(0x0006D050), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_PIB_OCBAR3                                       , RULL(0x0006D070), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_PIB_OCBCSR0_RO                                   , RULL(0x0006D011), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_PIB_OCBCSR0_CLEAR                                , RULL(0x0006D012), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_PIB_OCBCSR0_OR                                   , RULL(0x0006D013), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_PIB_OCBCSR1_RO                                   , RULL(0x0006D031), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_PIB_OCBCSR1_CLEAR                                , RULL(0x0006D032), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_PIB_OCBCSR1_OR                                   , RULL(0x0006D033), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_PIB_OCBCSR2_RO                                   , RULL(0x0006D051), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_PIB_OCBCSR2_CLEAR                                , RULL(0x0006D052), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_PIB_OCBCSR2_OR                                   , RULL(0x0006D053), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_PIB_OCBCSR3_RO                                   , RULL(0x0006D071), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_PIB_OCBCSR3_CLEAR                                , RULL(0x0006D072), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_PIB_OCBCSR3_OR                                   , RULL(0x0006D073), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_PIB_OCBDR0                                       , RULL(0x0006D015), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_PIB_OCBDR1                                       , RULL(0x0006D035), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_PIB_OCBDR2                                       , RULL(0x0006D055), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_PIB_OCBDR3                                       , RULL(0x0006D075), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_PIB_OCBEAR                                       , RULL(0x0006D210), SH_UNT          ,
+       SH_ACS_SCOM_WCLRPART );
+
+REG64( PU_OCB_PIB_OCBESR0                                      , RULL(0x0006D014), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_OCB_PIB_OCBESR1                                      , RULL(0x0006D034), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_OCB_PIB_OCBESR2                                      , RULL(0x0006D054), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_OCB_PIB_OCBESR3                                      , RULL(0x0006D074), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_OCB_PIB_OCDBG                                        , RULL(0x0006D003), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_PIB_OCR_RO                                       , RULL(0x0006D000), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_OCB_PIB_OCR_CLEAR                                    , RULL(0x0006D001), SH_UNT          ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PU_OCB_PIB_OCR_OR                                       , RULL(0x0006D002), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_OCB_PIB_OEAR                                         , RULL(0x0006D206), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_PIB_OESR                                         , RULL(0x0006D204), SH_UNT          ,
+       SH_ACS_SCOM_WCLEAR );
+
+REG64( PU_OCB_PIB_OPPCINJ                                      , RULL(0x0006D111), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_OCB_PIB_OREV                                         , RULL(0x0006D202), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_OCB_PIB_OSTOEAR                                      , RULL(0x0006D200), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_OCB_PIB_OSTOESR                                      , RULL(0x0006D201), SH_UNT          ,
+       SH_ACS_SCOM_WCLEAR );
+
+REG64( PU_OCB_PIB_OTDCR                                        , RULL(0x0006D110), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PEC_OPCG_ALIGN                                          , RULL(0x0D030001), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_OPCG_ALIGN                                        , RULL(0x0D030001), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_OPCG_ALIGN                                        , RULL(0x0E030001), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_OPCG_ALIGN                                        , RULL(0x0F030001), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_OPCG_CAPT1                                          , RULL(0x0D030010), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_OPCG_CAPT1                                        , RULL(0x0D030010), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_OPCG_CAPT1                                        , RULL(0x0E030010), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_OPCG_CAPT1                                        , RULL(0x0F030010), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_OPCG_CAPT2                                          , RULL(0x0D030011), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_OPCG_CAPT2                                        , RULL(0x0D030011), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_OPCG_CAPT2                                        , RULL(0x0E030011), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_OPCG_CAPT2                                        , RULL(0x0F030011), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_OPCG_CAPT3                                          , RULL(0x0D030012), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_OPCG_CAPT3                                        , RULL(0x0D030012), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_OPCG_CAPT3                                        , RULL(0x0E030012), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_OPCG_CAPT3                                        , RULL(0x0F030012), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_OPCG_REG0                                           , RULL(0x0D030002), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_OPCG_REG0                                         , RULL(0x0D030002), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_OPCG_REG0                                         , RULL(0x0E030002), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_OPCG_REG0                                         , RULL(0x0F030002), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_OPCG_REG1                                           , RULL(0x0D030003), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_OPCG_REG1                                         , RULL(0x0D030003), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_OPCG_REG1                                         , RULL(0x0E030003), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_OPCG_REG1                                         , RULL(0x0F030003), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_OPCG_REG2                                           , RULL(0x0D030004), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_OPCG_REG2                                         , RULL(0x0D030004), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_OPCG_REG2                                         , RULL(0x0E030004), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_OPCG_REG2                                         , RULL(0x0F030004), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_OPTICAL_IO_CONFIG                            , RULL(0x05011383), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_PBABAR0                                              , RULL(0x05012B00), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBABAR1                                              , RULL(0x05012B01), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBABAR2                                              , RULL(0x05012B02), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBABAR3                                              , RULL(0x05012B03), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBABARMSK0                                           , RULL(0x05012B04), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBABARMSK1                                           , RULL(0x05012B05), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBABARMSK2                                           , RULL(0x05012B06), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBABARMSK3                                           , RULL(0x05012B07), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBACFG                                               , RULL(0x0501284B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBAERRRPT0                                           , RULL(0x0501284C), SH_UNT          ,
+       SH_ACS_SCOM_WCLRPART );
+
+REG64( PU_PBAERRRPT1                                           , RULL(0x0501284D), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAERRRPT2                                           , RULL(0x0501284E), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAFIR                                               , RULL(0x05012840), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PBAFIR_AND                                           , RULL(0x05012841), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PBAFIR_OR                                            , RULL(0x05012842), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PBAFIRACT0                                           , RULL(0x05012846), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBAFIRACT1                                           , RULL(0x05012847), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBAFIRMASK                                           , RULL(0x05012843), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PBAFIRMASK_AND                                       , RULL(0x05012844), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PBAFIRMASK_OR                                        , RULL(0x05012845), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PEC_PBAIBHWCFG_REG                                      , RULL(0x0D010800), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_PBAIBHWCFG_REG                                    , RULL(0x0D010800), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_PBAIBHWCFG_REG                                    , RULL(0x0E010800), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_PBAIBHWCFG_REG                                    , RULL(0x0F010800), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PHB_PBAIB_CERR_RPT_REG                                  , RULL(0x0D01084B), SH_UNT_PHB      , SH_ACS_SCOM_RO   );
+REG64( PHB_0_PBAIB_CERR_RPT_REG                                , RULL(0x0D01084B), SH_UNT_PHB_0    , SH_ACS_SCOM_RO   );
+REG64( PHB_1_PBAIB_CERR_RPT_REG                                , RULL(0x0E01084B), SH_UNT_PHB_1    , SH_ACS_SCOM_RO   );
+REG64( PHB_2_PBAIB_CERR_RPT_REG                                , RULL(0x0E01088B), SH_UNT_PHB_2    , SH_ACS_SCOM_RO   );
+REG64( PHB_3_PBAIB_CERR_RPT_REG                                , RULL(0x0F01084B), SH_UNT_PHB_3    , SH_ACS_SCOM_RO   );
+REG64( PHB_4_PBAIB_CERR_RPT_REG                                , RULL(0x0F01088B), SH_UNT_PHB_4    , SH_ACS_SCOM_RO   );
+REG64( PHB_5_PBAIB_CERR_RPT_REG                                , RULL(0x0F0108CB), SH_UNT_PHB_5    , SH_ACS_SCOM_RO   );
+REG64( PU_PBAIB_STACK1_PBAIB_CERR_RPT_REG                      , RULL(0x0D01088B), SH_UNT_PU_PBAIB_STACK1,
+       SH_ACS_SCOM_RO   );
+REG64( PU_PBAIB_STACK2_PBAIB_CERR_RPT_REG                      , RULL(0x0D0108CB), SH_UNT_PU_PBAIB_STACK2,
+       SH_ACS_SCOM_RO   );
+REG64( PU_PBAIB_STACK5_PBAIB_CERR_RPT_REG                      , RULL(0x0E0108CB), SH_UNT_PU_PBAIB_STACK5,
+       SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAMODE_OCI                                          , RULL(0xC0040000), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAMODE_PIB                                          , RULL(0x00064000), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBAOCCACT                                            , RULL(0x0501284A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBAPBOCR0_OCI                                        , RULL(0xC00400D0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAPBOCR0_PIB                                        , RULL(0x0006401A), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBAPBOCR1_OCI                                        , RULL(0xC00400D8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAPBOCR1_PIB                                        , RULL(0x0006401B), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBAPBOCR2_OCI                                        , RULL(0xC00400E0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAPBOCR2_PIB                                        , RULL(0x0006401C), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBAPBOCR3_OCI                                        , RULL(0xC00400E8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAPBOCR3_PIB                                        , RULL(0x0006401D), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBAPBOCR4_OCI                                        , RULL(0xC00400F0), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAPBOCR4_PIB                                        , RULL(0x0006401E), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBAPBOCR5_OCI                                        , RULL(0xC00400F8), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAPBOCR5_PIB                                        , RULL(0x0006401F), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBARBUFVAL0                                          , RULL(0x05012850), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBARBUFVAL1                                          , RULL(0x05012851), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBARBUFVAL2                                          , RULL(0x05012852), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBARBUFVAL3                                          , RULL(0x05012853), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBARBUFVAL4                                          , RULL(0x05012854), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBARBUFVAL5                                          , RULL(0x05012855), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBASLVCTL0_OCI                                       , RULL(0xC0040020), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBASLVCTL0_PIB                                       , RULL(0x00064004), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBASLVCTL1_OCI                                       , RULL(0xC0040028), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBASLVCTL1_PIB                                       , RULL(0x00064005), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBASLVCTL2_OCI                                       , RULL(0xC0040030), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBASLVCTL2_PIB                                       , RULL(0x00064006), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBASLVCTL3_OCI                                       , RULL(0xC0040038), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBASLVCTL3_PIB                                       , RULL(0x00064007), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBASLVRST_OCI                                        , RULL(0xC0040008), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBASLVRST_PIB                                        , RULL(0x00064001), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBAWBUFVAL0                                          , RULL(0x05012858), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAWBUFVAL1                                          , RULL(0x05012859), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PBAXCFG_OCI                                          , RULL(0xC0040108), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXCFG_PIB                                          , RULL(0x00064021), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBAXRCVSTAT_OCI                                      , RULL(0xC0040120), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXRCVSTAT_PIB                                      , RULL(0x00064024), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBAXSHBR0_OCI                                        , RULL(0xC0040130), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXSHBR0_PIB                                        , RULL(0x00064026), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBAXSHBR1_OCI                                        , RULL(0xC0040150), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXSHBR1_PIB                                        , RULL(0x0006402A), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBAXSHCS0_OCI                                        , RULL(0xC0040138), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXSHCS0_PIB                                        , RULL(0x00064027), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBAXSHCS1_OCI                                        , RULL(0xC0040158), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXSHCS1_PIB                                        , RULL(0x0006402B), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBAXSNDSTAT_OCI                                      , RULL(0xC0040110), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXSNDSTAT_PIB                                      , RULL(0x00064022), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PU_PBAXSNDTX_OCI                                        , RULL(0xC0040100), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_PBAXSNDTX_PIB                                        , RULL(0x00064020), SH_UNT          , SH_ACS_PIB       );
+
+REG64( PEC_PBCQEINJ_REG                                        , RULL(0x04010C02), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_PBCQEINJ_REG                                      , RULL(0x04010C02), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_PBCQEINJ_REG                                      , RULL(0x04011002), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_PBCQEINJ_REG                                      , RULL(0x04011402), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_PBCQHWCFG_REG                                       , RULL(0x04010C00), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_PBCQHWCFG_REG                                     , RULL(0x04010C00), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_PBCQHWCFG_REG                                     , RULL(0x04011000), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_PBCQHWCFG_REG                                     , RULL(0x04011400), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_0_STACK0_PBCQMODE_REG                               , RULL(0x04010C4D), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK1_PBCQMODE_REG                               , RULL(0x04010C8D), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK2_PBCQMODE_REG                               , RULL(0x04010CCD), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK0_PBCQMODE_REG                               , RULL(0x0401104D), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK1_PBCQMODE_REG                               , RULL(0x0401108D), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK2_PBCQMODE_REG                               , RULL(0x040110CD), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK0_PBCQMODE_REG                               , RULL(0x0401144D), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK1_PBCQMODE_REG                               , RULL(0x0401148D), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK2_PBCQMODE_REG                               , RULL(0x040114CD), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK0_PBCQMODE_REG                                 , RULL(0x04010C4D), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK1_PBCQMODE_REG                                 , RULL(0x04010C8D), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK2_PBCQMODE_REG                                 , RULL(0x04010CCD), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PHB_PBCQMODE_REG                                        , RULL(0x04010C4D), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_0_PBCQMODE_REG                                      , RULL(0x04010C4D), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_PBCQMODE_REG                                      , RULL(0x0401104D), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_PBCQMODE_REG                                      , RULL(0x0401108D), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_PBCQMODE_REG                                      , RULL(0x0401144D), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_PBCQMODE_REG                                      , RULL(0x0401148D), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_PBCQMODE_REG                                      , RULL(0x040114CD), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_00_REG                                   , RULL(0x05013430), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_01_REG                                   , RULL(0x05013431), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_10_REG                                   , RULL(0x05013432), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_11_REG                                   , RULL(0x05013433), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_20_REG                                   , RULL(0x05013434), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_21_REG                                   , RULL(0x05013435), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_30_REG                                   , RULL(0x05013436), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_31_REG                                   , RULL(0x05013437), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_40_REG                                   , RULL(0x05013438), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_41_REG                                   , RULL(0x05013439), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_50_REG                                   , RULL(0x0501343A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_51_REG                                   , RULL(0x0501343B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PBE_MAILBOX_CTL_REG                                  , RULL(0x0501342E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PBE_MAILBOX_DATA_REG                                 , RULL(0x0501342F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_00_REG                               , RULL(0x05013830), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_01_REG                               , RULL(0x05013831), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_10_REG                               , RULL(0x05013832), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_11_REG                               , RULL(0x05013833), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_20_REG                               , RULL(0x05013834), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_21_REG                               , RULL(0x05013835), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_30_REG                               , RULL(0x05013836), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_31_REG                               , RULL(0x05013837), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_40_REG                               , RULL(0x05013838), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_41_REG                               , RULL(0x05013839), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_50_REG                               , RULL(0x0501383A), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_51_REG                               , RULL(0x0501383B), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_60_REG                               , RULL(0x0501383C), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_61_REG                               , RULL(0x0501383D), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_70_REG                               , RULL(0x0501383E), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_71_REG                               , RULL(0x0501383F), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PBO_MAILBOX_CTL_REG                              , RULL(0x0501382E), SH_UNT_PU_IOE   , SH_ACS_SCOM      );
+
+REG64( PU_IOE_PBO_MAILBOX_DATA_REG                             , RULL(0x0501382F), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_CNPME                            , RULL(0x05011C13), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_CNPMW                            , RULL(0x05011C14), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM1_PB_CENT_CR_ERROR                         , RULL(0x05011C2C), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA                      , RULL(0x05011C17), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB                      , RULL(0x05011C18), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX                      , RULL(0x05011C19), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL                        , RULL(0x05011C16), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM1_PB_CENT_EXTDAT_COUNTER                   , RULL(0x05011C25), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG                  , RULL(0x05011C06), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG                  , RULL(0x05011C07), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG                     , RULL(0x05011C03), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_AND                 , RULL(0x05011C04), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM1_AND );
+REG64( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_OR                  , RULL(0x05011C05), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_FIR_REG                          , RULL(0x05011C00), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PB_CENT_SM0_PB_CENT_FIR_REG_AND                      , RULL(0x05011C01), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM1_AND );
+REG64( PU_PB_CENT_SM0_PB_CENT_FIR_REG_OR                       , RULL(0x05011C02), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0                  , RULL(0x05011C26), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1                  , RULL(0x05011C27), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_CURR                    , RULL(0x05011C0E), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_HPA_MODE_NEXT                    , RULL(0x05011C0D), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR                    , RULL(0x05011C10), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT                    , RULL(0x05011C0F), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR                     , RULL(0x05011C0C), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT                     , RULL(0x05011C0B), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER                     , RULL(0x05011C23), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_MODE                             , RULL(0x05011C0A), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER                     , RULL(0x05011C22), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPME_COUNTER               , RULL(0x05011C1A), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_PMU0_CNPMW_COUNTER               , RULL(0x05011C1E), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPME_COUNTER               , RULL(0x05011C1B), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_PMU1_CNPMW_COUNTER               , RULL(0x05011C1F), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_PMU2_CNPME_COUNTER               , RULL(0x05011C1C), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM1_PB_CENT_PMU2_CNPMW_COUNTER               , RULL(0x05011C20), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_PMU3_CNPME_COUNTER               , RULL(0x05011C1D), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM1_PB_CENT_PMU3_CNPMW_COUNTER               , RULL(0x05011C21), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER                    , RULL(0x05011C15), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM1_PB_CENT_RCMD_INTDAT_COUNTER              , RULL(0x05011C24), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0                 , RULL(0x05011C28), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1                 , RULL(0x05011C29), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD                     , RULL(0x05011C11), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0                  , RULL(0x05011C2A), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1                  , RULL(0x05011C2B), SH_UNT_PU_PB_CENT_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_CENT_SM0_PB_CENT_TRACE                            , RULL(0x05011C12), SH_UNT_PU_PB_CENT_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_EAST_FIR_ACTION0_REG                              , RULL(0x05012006), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_EAST_FIR_ACTION1_REG                              , RULL(0x05012007), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_EAST_FIR_MASK_REG                                 , RULL(0x05012003), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PB_EAST_FIR_MASK_REG_AND                             , RULL(0x05012004), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PB_EAST_FIR_MASK_REG_OR                              , RULL(0x05012005), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_EAST_FIR_REG                                      , RULL(0x05012000), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PB_EAST_FIR_REG_AND                                  , RULL(0x05012001), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PB_EAST_FIR_REG_OR                                   , RULL(0x05012002), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_EAST_FW_SCRATCH0                                  , RULL(0x05012013), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PB_EAST_FW_SCRATCH0_AND                              , RULL(0x05012014), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PB_EAST_FW_SCRATCH0_OR                               , RULL(0x05012015), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_EAST_FW_SCRATCH1                                  , RULL(0x05012016), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PB_EAST_FW_SCRATCH1_AND                              , RULL(0x05012017), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PB_EAST_FW_SCRATCH1_OR                               , RULL(0x05012018), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_EAST_HPA_MODE_CURR                                , RULL(0x0501200E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PB_EAST_HPA_MODE_NEXT                                , RULL(0x0501200D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PB_EAST_HPX_MODE_CURR                                , RULL(0x05012010), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PB_EAST_HPX_MODE_NEXT                                , RULL(0x0501200F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PB_EAST_HP_MODE_CURR                                 , RULL(0x0501200C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PB_EAST_HP_MODE_NEXT                                 , RULL(0x0501200B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PB_EAST_MODE                                         , RULL(0x0501200A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PB_EAST_SCONFIG_LOAD                                 , RULL(0x05012011), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PB_EAST_SPARE                                        , RULL(0x05012012), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PB_ELINK_DATA_01_CFG_REG                             , RULL(0x05013410), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_DATA_23_CFG_REG                             , RULL(0x05013411), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_DATA_45_CFG_REG                             , RULL(0x05013412), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_DLY_0123_REG                                , RULL(0x0501340E), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_ELINK_DLY_45_REG                                  , RULL(0x0501340F), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_ELINK_PMU0                                        , RULL(0x0501341B), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_PB_ELINK_PMU1                                        , RULL(0x0501341C), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_PB_ELINK_PMU2                                        , RULL(0x0501341D), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_PB_ELINK_PMU3                                        , RULL(0x0501341E), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_PB_ELINK_PMU4                                        , RULL(0x0501341F), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_PB_ELINK_PMU5                                        , RULL(0x05013420), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_PB_ELINK_PMU6                                        , RULL(0x05013421), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_PB_ELINK_PMU7                                        , RULL(0x05013422), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_PB_ELINK_PMU_CTL_REG                                 , RULL(0x0501341A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_ELINK_RT_DELAY_CTL_REG                            , RULL(0x05013419), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PB_ELINK_SYN_01_REG                                  , RULL(0x05013414), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_ELINK_SYN_23_REG                                  , RULL(0x05013415), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_ELINK_SYN_45_REG                                  , RULL(0x05013416), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_EN_DOB_ECC_ERR_REG                                , RULL(0x05013418), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_IOE_PB_EN_DOB_ECC_ERR_REG                            , RULL(0x05013818), SH_UNT_PU_IOE   , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_FM0123_ERR                                        , RULL(0x05013425), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_IOE_PB_FM0123_ERR                                    , RULL(0x05013825), SH_UNT_PU_IOE   , SH_ACS_SCOM_RO   );
+
+REG64( PU_IOE_PB_FM4567_ERR                                    , RULL(0x05013826), SH_UNT_PU_IOE   , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_FM45_ERR                                          , RULL(0x05013426), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_FP01_CFG                                          , RULL(0x0501340A), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_IOE_PB_FP01_CFG                                      , RULL(0x0501380A), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_FP23_CFG                                          , RULL(0x0501340B), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_IOE_PB_FP23_CFG                                      , RULL(0x0501380B), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_FP45_CFG                                          , RULL(0x0501340C), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_IOE_PB_FP45_CFG                                      , RULL(0x0501380C), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PB_FP67_CFG                                      , RULL(0x0501380D), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_IOE_FIR_ACTION0_REG                               , RULL(0x05013406), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_IOE_FIR_ACTION1_REG                               , RULL(0x05013407), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_IOE_FIR_MASK_REG                                  , RULL(0x05013403), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PB_IOE_FIR_MASK_REG_AND                              , RULL(0x05013404), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PB_IOE_FIR_MASK_REG_OR                               , RULL(0x05013405), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_IOE_FIR_REG                                       , RULL(0x05013400), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PB_IOE_FIR_REG_AND                                   , RULL(0x05013401), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PB_IOE_FIR_REG_OR                                    , RULL(0x05013402), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_IOE_PB_IOO_FIR_ACTION0_REG                           , RULL(0x05013806), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PB_IOO_FIR_ACTION1_REG                           , RULL(0x05013807), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PB_IOO_FIR_MASK_REG                              , RULL(0x05013803), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+REG64( PU_IOE_PB_IOO_FIR_MASK_REG_AND                          , RULL(0x05013804), SH_UNT_PU_IOE   , SH_ACS_SCOM1_AND );
+REG64( PU_IOE_PB_IOO_FIR_MASK_REG_OR                           , RULL(0x05013805), SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR  );
+
+REG64( PU_IOE_PB_IOO_FIR_REG                                   , RULL(0x05013800), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+REG64( PU_IOE_PB_IOO_FIR_REG_AND                               , RULL(0x05013801), SH_UNT_PU_IOE   , SH_ACS_SCOM1_AND );
+REG64( PU_IOE_PB_IOO_FIR_REG_OR                                , RULL(0x05013802), SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_MISC_CFG                                          , RULL(0x05013423), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_IOE_PB_MISC_CFG                                      , RULL(0x05013823), SH_UNT_PU_IOE   , SH_ACS_SCOM      );
+
+REG64( PU_IOE_PB_OLINK_DATA_01_CFG_REG                         , RULL(0x05013810), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PB_OLINK_DATA_23_CFG_REG                         , RULL(0x05013811), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PB_OLINK_DATA_45_CFG_REG                         , RULL(0x05013812), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PB_OLINK_DATA_67_CFG_REG                         , RULL(0x05013813), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PB_OLINK_DLY_0123_REG                            , RULL(0x0501380E), SH_UNT_PU_IOE   , SH_ACS_SCOM_RO   );
+
+REG64( PU_IOE_PB_OLINK_DLY_4567_REG                            , RULL(0x0501380F), SH_UNT_PU_IOE   , SH_ACS_SCOM_RO   );
+
+REG64( PU_IOE_PB_OLINK_PMU0                                    , RULL(0x0501381B), SH_UNT_PU_IOE   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_IOE_PB_OLINK_PMU1                                    , RULL(0x0501381C), SH_UNT_PU_IOE   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_IOE_PB_OLINK_PMU2                                    , RULL(0x0501381D), SH_UNT_PU_IOE   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_IOE_PB_OLINK_PMU3                                    , RULL(0x0501381E), SH_UNT_PU_IOE   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_IOE_PB_OLINK_PMU4                                    , RULL(0x0501381F), SH_UNT_PU_IOE   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_IOE_PB_OLINK_PMU5                                    , RULL(0x05013820), SH_UNT_PU_IOE   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_IOE_PB_OLINK_PMU6                                    , RULL(0x05013821), SH_UNT_PU_IOE   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_IOE_PB_OLINK_PMU7                                    , RULL(0x05013822), SH_UNT_PU_IOE   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_IOE_PB_OLINK_PMU_CTL_REG                             , RULL(0x0501381A), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG                        , RULL(0x05013819), SH_UNT_PU_IOE   , SH_ACS_SCOM      );
+
+REG64( PU_IOE_PB_OLINK_SYN_01_REG                              , RULL(0x05013814), SH_UNT_PU_IOE   , SH_ACS_SCOM_RO   );
+
+REG64( PU_IOE_PB_OLINK_SYN_23_REG                              , RULL(0x05013815), SH_UNT_PU_IOE   , SH_ACS_SCOM_RO   );
+
+REG64( PU_IOE_PB_OLINK_SYN_45_REG                              , RULL(0x05013816), SH_UNT_PU_IOE   , SH_ACS_SCOM_RO   );
+
+REG64( PU_IOE_PB_OLINK_SYN_67_REG                              , RULL(0x05013817), SH_UNT_PU_IOE   , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_PERFTRACE_CFG_REG                                 , RULL(0x05013429), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_IOE_PB_PERFTRACE_CFG_REG                             , RULL(0x05013829), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_PPE_LFIR                                          , RULL(0x05012400), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PB_PPE_LFIR_AND                                      , RULL(0x05012401), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PB_PPE_LFIR_OR                                       , RULL(0x05012402), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_PPE_LFIRACT0                                      , RULL(0x05012406), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_PPE_LFIRACT1                                      , RULL(0x05012407), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_PPE_LFIRMASK                                      , RULL(0x05012403), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PB_PPE_LFIRMASK_AND                                  , RULL(0x05012404), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PB_PPE_LFIRMASK_OR                                   , RULL(0x05012405), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_PR0123_ERR                                        , RULL(0x05013427), SH_UNT          , SH_ACS_SCOM_RO   );
+REG64( PU_IOE_PB_PR0123_ERR                                    , RULL(0x05013827), SH_UNT_PU_IOE   , SH_ACS_SCOM_RO   );
+
+REG64( PU_IOE_PB_PR4567_ERR                                    , RULL(0x05013828), SH_UNT_PU_IOE   , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_PR45_ERR                                          , RULL(0x05013428), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_PSAVE_CFG                                         , RULL(0x0501241A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PB_PSAVE_MON_CFG                                     , RULL(0x0501241B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_PSAVE_X0EVN_HIST                                  , RULL(0x0501241C), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_PSAVE_X0ODD_HIST                                  , RULL(0x0501241D), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_PSAVE_X1EVN_HIST                                  , RULL(0x0501241E), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_PSAVE_X1ODD_HIST                                  , RULL(0x0501241F), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_PSAVE_X2EVN_HIST                                  , RULL(0x05012420), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_PSAVE_X2ODD_HIST                                  , RULL(0x05012421), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PB_TRACE_CFG                                         , RULL(0x05013424), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_IOE_PB_TRACE_CFG                                     , RULL(0x05013824), SH_UNT_PU_IOE   , SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG                  , RULL(0x05011806), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG                  , RULL(0x05011807), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG                     , RULL(0x05011803), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_AND                 , RULL(0x05011804), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM1_AND );
+REG64( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_OR                  , RULL(0x05011805), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_WEST_SM0_PB_WEST_FIR_REG                          , RULL(0x05011800), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PB_WEST_SM0_PB_WEST_FIR_REG_AND                      , RULL(0x05011801), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM1_AND );
+REG64( PU_PB_WEST_SM0_PB_WEST_FIR_REG_OR                       , RULL(0x05011802), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH0                      , RULL(0x05011813), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH0_AND                  , RULL(0x05011814), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM1_AND );
+REG64( PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH0_OR                   , RULL(0x05011815), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH1                      , RULL(0x05011816), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH1_AND                  , RULL(0x05011817), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM1_AND );
+REG64( PU_PB_WEST_SM0_PB_WEST_FW_SCRATCH1_OR                   , RULL(0x05011818), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM2_OR  );
+
+REG64( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_CURR                    , RULL(0x0501180E), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_WEST_SM0_PB_WEST_HPA_MODE_NEXT                    , RULL(0x0501180D), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR                    , RULL(0x05011810), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT                    , RULL(0x0501180F), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR                     , RULL(0x0501180C), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT                     , RULL(0x0501180B), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_WEST_SM0_PB_WEST_MODE                             , RULL(0x0501180A), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD                     , RULL(0x05011811), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PU_PB_WEST_SM0_PB_WEST_SPARE                            , RULL(0x05011812), SH_UNT_PU_PB_WEST_SM0,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_M1_CONTROL_REG                                  , RULL(0x80000C010D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_M1_CONTROL_REG                                , RULL(0x80000C010D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_M1_CONTROL_REG                                , RULL(0x80000C010E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_M1_CONTROL_REG                                , RULL(0x80000C010F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_M2_CONTROL_REG                                  , RULL(0x80000C020D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_M2_CONTROL_REG                                , RULL(0x80000C020D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_M2_CONTROL_REG                                , RULL(0x80000C020E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_M2_CONTROL_REG                                , RULL(0x80000C020F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_M3_CONTROL_REG                                  , RULL(0x80000C030D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_M3_CONTROL_REG                                , RULL(0x80000C030D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_M3_CONTROL_REG                                , RULL(0x80000C030E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_M3_CONTROL_REG                                , RULL(0x80000C030F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_M4_CONTROL_REG                                  , RULL(0x80000C040D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_M4_CONTROL_REG                                , RULL(0x80000C040D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_M4_CONTROL_REG                                , RULL(0x80000C040E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_M4_CONTROL_REG                                , RULL(0x80000C040F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_SYS_CONTROL_REG                                 , RULL(0x80000C000D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_SYS_CONTROL_REG                               , RULL(0x80000C000D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_SYS_CONTROL_REG                               , RULL(0x80000C000E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_SYS_CONTROL_REG                               , RULL(0x80000C000F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PECAPP_CNTL_REG                                     , RULL(0x04010C07), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_PECAPP_CNTL_REG                                   , RULL(0x04010C07), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_PECAPP_CNTL_REG                                   , RULL(0x04011007), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_PECAPP_CNTL_REG                                   , RULL(0x04011407), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_PECAPP_SEC_BAR                                      , RULL(0x0D010801), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_PECAPP_SEC_BAR                                    , RULL(0x0D010801), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_PECAPP_SEC_BAR                                    , RULL(0x0E010801), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_PECAPP_SEC_BAR                                    , RULL(0x0F010801), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( NV_PERF_CONFIG                                          , RULL(0x050110CE), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_PERF_CONFIG                                        , RULL(0x050110CE), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_PERF_CONFIG                                        , RULL(0x050110EE), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_PERF_CONFIG                                        , RULL(0x050111CE), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_PERF_CONFIG                                        , RULL(0x050111EE), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_PERF_CONFIG                                 , RULL(0x05011087), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_PERF_CONFIG                                 , RULL(0x05011187), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_PERF_CONFIG                                 , RULL(0x05011287), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM0_PERF_CONFIG                                 , RULL(0x0501100F), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_PERF_CONFIG                                 , RULL(0x0501102F), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_PERF_CONFIG                                 , RULL(0x0501104F), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_PERF_CONFIG                                 , RULL(0x0501106F), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_PERF_CONFIG                                 , RULL(0x0501110F), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_PERF_CONFIG                                 , RULL(0x0501112F), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_PERF_CONFIG                                 , RULL(0x0501114F), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_PERF_CONFIG                                 , RULL(0x0501116F), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_PERF_CONFIG                                , RULL(0x050112CE), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_PERF_CONFIG                                , RULL(0x050112EE), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_PERF_CONFIG                                 , RULL(0x0501120F), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_PERF_CONFIG                                 , RULL(0x0501122F), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_PERF_CONFIG                                 , RULL(0x0501124F), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_PERF_CONFIG                                 , RULL(0x0501126F), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( NV_PERF_COUNT                                           , RULL(0x050110CF), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_PERF_COUNT                                         , RULL(0x050110CF), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_PERF_COUNT                                         , RULL(0x050110EF), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_PERF_COUNT                                         , RULL(0x050111CF), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_PERF_COUNT                                         , RULL(0x050111EF), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU0_CTL_PERF_COUNT                                  , RULL(0x05011086), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_PERF_COUNT                                  , RULL(0x05011186), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_PERF_COUNT                                  , RULL(0x05011286), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_PERF_COUNT                                 , RULL(0x050112CF), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_PERF_COUNT                                 , RULL(0x050112EF), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_PERF_MASK_CONFIG                            , RULL(0x05011085), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_PERF_MASK_CONFIG                            , RULL(0x05011185), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_PERF_MASK_CONFIG                            , RULL(0x05011285), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU0_CTL_PERF_MATCH_CONFIG                           , RULL(0x05011084), SH_UNT_PU_NPU0_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_CTL_PERF_MATCH_CONFIG                           , RULL(0x05011184), SH_UNT_PU_NPU1_CTL,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_CTL_PERF_MATCH_CONFIG                           , RULL(0x05011284), SH_UNT_PU_NPU2_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE0                              , RULL(0x050113D0), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE1                              , RULL(0x050113D1), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE10                             , RULL(0x050113DA), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE11                             , RULL(0x050113DB), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE12                             , RULL(0x050113DC), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE13                             , RULL(0x050113DD), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE14                             , RULL(0x050113DE), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE15                             , RULL(0x050113DF), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE2                              , RULL(0x050113D2), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE3                              , RULL(0x050113D3), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE4                              , RULL(0x050113D4), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE5                              , RULL(0x050113D5), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE6                              , RULL(0x050113D6), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE7                              , RULL(0x050113D7), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE8                              , RULL(0x050113D8), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_ADDR_PE9                              , RULL(0x050113D9), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE0                              , RULL(0x050113C0), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE1                              , RULL(0x050113C1), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE10                             , RULL(0x050113CA), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE11                             , RULL(0x050113CB), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE12                             , RULL(0x050113CC), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE13                             , RULL(0x050113CD), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE14                             , RULL(0x050113CE), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE15                             , RULL(0x050113CF), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE2                              , RULL(0x050113C2), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE3                              , RULL(0x050113C3), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE4                              , RULL(0x050113C4), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE5                              , RULL(0x050113C5), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE6                              , RULL(0x050113C6), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE7                              , RULL(0x050113C7), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE8                              , RULL(0x050113C8), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_NTL0_PESTB_DATA_PE9                              , RULL(0x050113C9), SH_UNT_PU_NPU_NTL0,
+       SH_ACS_SCOM      );
+
+REG64( PEC_0_STACK0_PE_DFREEZE_REG                             , RULL(0x04010C55), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK1_PE_DFREEZE_REG                             , RULL(0x04010C95), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_0_STACK2_PE_DFREEZE_REG                             , RULL(0x04010CD5), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK0_PE_DFREEZE_REG                             , RULL(0x04011055), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK1_PE_DFREEZE_REG                             , RULL(0x04011095), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_1_STACK2_PE_DFREEZE_REG                             , RULL(0x040110D5), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK0_PE_DFREEZE_REG                             , RULL(0x04011455), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK1_PE_DFREEZE_REG                             , RULL(0x04011495), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_2_STACK2_PE_DFREEZE_REG                             , RULL(0x040114D5), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK0_PE_DFREEZE_REG                               , RULL(0x04010C55), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK1_PE_DFREEZE_REG                               , RULL(0x04010C95), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PEC_STACK2_PE_DFREEZE_REG                               , RULL(0x04010CD5), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PHB_PE_DFREEZE_REG                                      , RULL(0x04010C55), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_0_PE_DFREEZE_REG                                    , RULL(0x04010C55), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_PE_DFREEZE_REG                                    , RULL(0x04011055), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_PE_DFREEZE_REG                                    , RULL(0x04011095), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_PE_DFREEZE_REG                                    , RULL(0x04011455), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_PE_DFREEZE_REG                                    , RULL(0x04011495), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_PE_DFREEZE_REG                                    , RULL(0x040114D5), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+
+REG64( PHB_PFIRACTION0_REG                                     , RULL(0x0D010846), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_0_PFIRACTION0_REG                                   , RULL(0x0D010846), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_PFIRACTION0_REG                                   , RULL(0x0E010846), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_PFIRACTION0_REG                                   , RULL(0x0E010886), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_PFIRACTION0_REG                                   , RULL(0x0F010846), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_PFIRACTION0_REG                                   , RULL(0x0F010886), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_PFIRACTION0_REG                                   , RULL(0x0F0108C6), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK1_PFIRACTION0_REG                         , RULL(0x0D010886), SH_UNT_PU_PBAIB_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK2_PFIRACTION0_REG                         , RULL(0x0D0108C6), SH_UNT_PU_PBAIB_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK5_PFIRACTION0_REG                         , RULL(0x0E0108C6), SH_UNT_PU_PBAIB_STACK5,
+       SH_ACS_SCOM_RW   );
+
+REG64( PHB_PFIRACTION1_REG                                     , RULL(0x0D010847), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_0_PFIRACTION1_REG                                   , RULL(0x0D010847), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_PFIRACTION1_REG                                   , RULL(0x0E010847), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_PFIRACTION1_REG                                   , RULL(0x0E010887), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_PFIRACTION1_REG                                   , RULL(0x0F010847), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_PFIRACTION1_REG                                   , RULL(0x0F010887), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_PFIRACTION1_REG                                   , RULL(0x0F0108C7), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK1_PFIRACTION1_REG                         , RULL(0x0D010887), SH_UNT_PU_PBAIB_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK2_PFIRACTION1_REG                         , RULL(0x0D0108C7), SH_UNT_PU_PBAIB_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK5_PFIRACTION1_REG                         , RULL(0x0E0108C7), SH_UNT_PU_PBAIB_STACK5,
+       SH_ACS_SCOM_RW   );
+
+REG64( PHB_PFIRMASK_REG                                        , RULL(0x0D010843), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_PFIRMASK_REG_AND                                    , RULL(0x0D010844), SH_UNT_PHB      , SH_ACS_SCOM1_AND );
+REG64( PHB_PFIRMASK_REG_OR                                     , RULL(0x0D010845), SH_UNT_PHB      , SH_ACS_SCOM2_OR  );
+REG64( PHB_0_PFIRMASK_REG                                      , RULL(0x0D010843), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_0_PFIRMASK_REG_AND                                  , RULL(0x0D010844), SH_UNT_PHB_0    , SH_ACS_SCOM1_AND );
+REG64( PHB_0_PFIRMASK_REG_OR                                   , RULL(0x0D010845), SH_UNT_PHB_0    , SH_ACS_SCOM2_OR  );
+REG64( PHB_1_PFIRMASK_REG                                      , RULL(0x0E010843), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_PFIRMASK_REG_AND                                  , RULL(0x0E010844), SH_UNT_PHB_1    , SH_ACS_SCOM1_AND );
+REG64( PHB_1_PFIRMASK_REG_OR                                   , RULL(0x0E010845), SH_UNT_PHB_1    , SH_ACS_SCOM2_OR  );
+REG64( PHB_2_PFIRMASK_REG                                      , RULL(0x0E010883), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_PFIRMASK_REG_AND                                  , RULL(0x0E010884), SH_UNT_PHB_2    , SH_ACS_SCOM1_AND );
+REG64( PHB_2_PFIRMASK_REG_OR                                   , RULL(0x0E010885), SH_UNT_PHB_2    , SH_ACS_SCOM2_OR  );
+REG64( PHB_3_PFIRMASK_REG                                      , RULL(0x0F010843), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_PFIRMASK_REG_AND                                  , RULL(0x0F010844), SH_UNT_PHB_3    , SH_ACS_SCOM1_AND );
+REG64( PHB_3_PFIRMASK_REG_OR                                   , RULL(0x0F010845), SH_UNT_PHB_3    , SH_ACS_SCOM2_OR  );
+REG64( PHB_4_PFIRMASK_REG                                      , RULL(0x0F010883), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_PFIRMASK_REG_AND                                  , RULL(0x0F010884), SH_UNT_PHB_4    , SH_ACS_SCOM1_AND );
+REG64( PHB_4_PFIRMASK_REG_OR                                   , RULL(0x0F010885), SH_UNT_PHB_4    , SH_ACS_SCOM2_OR  );
+REG64( PHB_5_PFIRMASK_REG                                      , RULL(0x0F0108C3), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_PFIRMASK_REG_AND                                  , RULL(0x0F0108C4), SH_UNT_PHB_5    , SH_ACS_SCOM1_AND );
+REG64( PHB_5_PFIRMASK_REG_OR                                   , RULL(0x0F0108C5), SH_UNT_PHB_5    , SH_ACS_SCOM2_OR  );
+REG64( PU_PBAIB_STACK1_PFIRMASK_REG                            , RULL(0x0D010883), SH_UNT_PU_PBAIB_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK1_PFIRMASK_REG_AND                        , RULL(0x0D010884), SH_UNT_PU_PBAIB_STACK1,
+       SH_ACS_SCOM1_AND );
+REG64( PU_PBAIB_STACK1_PFIRMASK_REG_OR                         , RULL(0x0D010885), SH_UNT_PU_PBAIB_STACK1,
+       SH_ACS_SCOM2_OR  );
+REG64( PU_PBAIB_STACK2_PFIRMASK_REG                            , RULL(0x0D0108C3), SH_UNT_PU_PBAIB_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK2_PFIRMASK_REG_AND                        , RULL(0x0D0108C4), SH_UNT_PU_PBAIB_STACK2,
+       SH_ACS_SCOM1_AND );
+REG64( PU_PBAIB_STACK2_PFIRMASK_REG_OR                         , RULL(0x0D0108C5), SH_UNT_PU_PBAIB_STACK2,
+       SH_ACS_SCOM2_OR  );
+REG64( PU_PBAIB_STACK5_PFIRMASK_REG                            , RULL(0x0E0108C3), SH_UNT_PU_PBAIB_STACK5,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK5_PFIRMASK_REG_AND                        , RULL(0x0E0108C4), SH_UNT_PU_PBAIB_STACK5,
+       SH_ACS_SCOM1_AND );
+REG64( PU_PBAIB_STACK5_PFIRMASK_REG_OR                         , RULL(0x0E0108C5), SH_UNT_PU_PBAIB_STACK5,
+       SH_ACS_SCOM2_OR  );
+
+REG64( PHB_PFIRWOF_REG                                         , RULL(0x0D010848), SH_UNT_PHB      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_0_PFIRWOF_REG                                       , RULL(0x0D010848), SH_UNT_PHB_0    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_1_PFIRWOF_REG                                       , RULL(0x0E010848), SH_UNT_PHB_1    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_2_PFIRWOF_REG                                       , RULL(0x0E010888), SH_UNT_PHB_2    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_3_PFIRWOF_REG                                       , RULL(0x0F010848), SH_UNT_PHB_3    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_4_PFIRWOF_REG                                       , RULL(0x0F010888), SH_UNT_PHB_4    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_5_PFIRWOF_REG                                       , RULL(0x0F0108C8), SH_UNT_PHB_5    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PU_PBAIB_STACK1_PFIRWOF_REG                             , RULL(0x0D010888), SH_UNT_PU_PBAIB_STACK1,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PU_PBAIB_STACK2_PFIRWOF_REG                             , RULL(0x0D0108C8), SH_UNT_PU_PBAIB_STACK2,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PU_PBAIB_STACK5_PFIRWOF_REG                             , RULL(0x0E0108C8), SH_UNT_PU_PBAIB_STACK5,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PHB_PFIR_REG                                            , RULL(0x0D010840), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_PFIR_REG_AND                                        , RULL(0x0D010841), SH_UNT_PHB      , SH_ACS_SCOM1_AND );
+REG64( PHB_PFIR_REG_OR                                         , RULL(0x0D010842), SH_UNT_PHB      , SH_ACS_SCOM2_OR  );
+REG64( PHB_0_PFIR_REG                                          , RULL(0x0D010840), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_0_PFIR_REG_AND                                      , RULL(0x0D010841), SH_UNT_PHB_0    , SH_ACS_SCOM1_AND );
+REG64( PHB_0_PFIR_REG_OR                                       , RULL(0x0D010842), SH_UNT_PHB_0    , SH_ACS_SCOM2_OR  );
+REG64( PHB_1_PFIR_REG                                          , RULL(0x0E010840), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_PFIR_REG_AND                                      , RULL(0x0E010841), SH_UNT_PHB_1    , SH_ACS_SCOM1_AND );
+REG64( PHB_1_PFIR_REG_OR                                       , RULL(0x0E010842), SH_UNT_PHB_1    , SH_ACS_SCOM2_OR  );
+REG64( PHB_2_PFIR_REG                                          , RULL(0x0E010880), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_PFIR_REG_AND                                      , RULL(0x0E010881), SH_UNT_PHB_2    , SH_ACS_SCOM1_AND );
+REG64( PHB_2_PFIR_REG_OR                                       , RULL(0x0E010882), SH_UNT_PHB_2    , SH_ACS_SCOM2_OR  );
+REG64( PHB_3_PFIR_REG                                          , RULL(0x0F010840), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_PFIR_REG_AND                                      , RULL(0x0F010841), SH_UNT_PHB_3    , SH_ACS_SCOM1_AND );
+REG64( PHB_3_PFIR_REG_OR                                       , RULL(0x0F010842), SH_UNT_PHB_3    , SH_ACS_SCOM2_OR  );
+REG64( PHB_4_PFIR_REG                                          , RULL(0x0F010880), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_PFIR_REG_AND                                      , RULL(0x0F010881), SH_UNT_PHB_4    , SH_ACS_SCOM1_AND );
+REG64( PHB_4_PFIR_REG_OR                                       , RULL(0x0F010882), SH_UNT_PHB_4    , SH_ACS_SCOM2_OR  );
+REG64( PHB_5_PFIR_REG                                          , RULL(0x0F0108C0), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_PFIR_REG_AND                                      , RULL(0x0F0108C1), SH_UNT_PHB_5    , SH_ACS_SCOM1_AND );
+REG64( PHB_5_PFIR_REG_OR                                       , RULL(0x0F0108C2), SH_UNT_PHB_5    , SH_ACS_SCOM2_OR  );
+REG64( PU_PBAIB_STACK1_PFIR_REG                                , RULL(0x0D010880), SH_UNT_PU_PBAIB_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK1_PFIR_REG_AND                            , RULL(0x0D010881), SH_UNT_PU_PBAIB_STACK1,
+       SH_ACS_SCOM1_AND );
+REG64( PU_PBAIB_STACK1_PFIR_REG_OR                             , RULL(0x0D010882), SH_UNT_PU_PBAIB_STACK1,
+       SH_ACS_SCOM2_OR  );
+REG64( PU_PBAIB_STACK2_PFIR_REG                                , RULL(0x0D0108C0), SH_UNT_PU_PBAIB_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK2_PFIR_REG_AND                            , RULL(0x0D0108C1), SH_UNT_PU_PBAIB_STACK2,
+       SH_ACS_SCOM1_AND );
+REG64( PU_PBAIB_STACK2_PFIR_REG_OR                             , RULL(0x0D0108C2), SH_UNT_PU_PBAIB_STACK2,
+       SH_ACS_SCOM2_OR  );
+REG64( PU_PBAIB_STACK5_PFIR_REG                                , RULL(0x0E0108C0), SH_UNT_PU_PBAIB_STACK5,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK5_PFIR_REG_AND                            , RULL(0x0E0108C1), SH_UNT_PU_PBAIB_STACK5,
+       SH_ACS_SCOM1_AND );
+REG64( PU_PBAIB_STACK5_PFIR_REG_OR                             , RULL(0x0E0108C2), SH_UNT_PU_PBAIB_STACK5,
+       SH_ACS_SCOM2_OR  );
+
+REG64( PEC_0_STACK0_PHBBAR_REG                                 , RULL(0x04010C52), SH_UNT_PEC_0_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_0_STACK1_PHBBAR_REG                                 , RULL(0x04010C92), SH_UNT_PEC_0_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_0_STACK2_PHBBAR_REG                                 , RULL(0x04010CD2), SH_UNT_PEC_0_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK0_PHBBAR_REG                                 , RULL(0x04011052), SH_UNT_PEC_1_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK1_PHBBAR_REG                                 , RULL(0x04011092), SH_UNT_PEC_1_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_1_STACK2_PHBBAR_REG                                 , RULL(0x040110D2), SH_UNT_PEC_1_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK0_PHBBAR_REG                                 , RULL(0x04011452), SH_UNT_PEC_2_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK1_PHBBAR_REG                                 , RULL(0x04011492), SH_UNT_PEC_2_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_2_STACK2_PHBBAR_REG                                 , RULL(0x040114D2), SH_UNT_PEC_2_STACK2,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK0_PHBBAR_REG                                   , RULL(0x04010C52), SH_UNT_PEC_STACK0,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK1_PHBBAR_REG                                   , RULL(0x04010C92), SH_UNT_PEC_STACK1,
+       SH_ACS_SCOM      );
+REG64( PEC_STACK2_PHBBAR_REG                                   , RULL(0x04010CD2), SH_UNT_PEC_STACK2,
+       SH_ACS_SCOM      );
+REG64( PHB_PHBBAR_REG                                          , RULL(0x04010C52), SH_UNT_PHB      , SH_ACS_SCOM      );
+REG64( PHB_0_PHBBAR_REG                                        , RULL(0x04010C52), SH_UNT_PHB_0    , SH_ACS_SCOM      );
+REG64( PHB_1_PHBBAR_REG                                        , RULL(0x04011052), SH_UNT_PHB_1    , SH_ACS_SCOM      );
+REG64( PHB_2_PHBBAR_REG                                        , RULL(0x04011092), SH_UNT_PHB_2    , SH_ACS_SCOM      );
+REG64( PHB_3_PHBBAR_REG                                        , RULL(0x04011452), SH_UNT_PHB_3    , SH_ACS_SCOM      );
+REG64( PHB_4_PHBBAR_REG                                        , RULL(0x04011492), SH_UNT_PHB_4    , SH_ACS_SCOM      );
+REG64( PHB_5_PHBBAR_REG                                        , RULL(0x040114D2), SH_UNT_PHB_5    , SH_ACS_SCOM      );
+
+REG64( PHB_PHBRESET_REG                                        , RULL(0x0D01084A), SH_UNT_PHB      , SH_ACS_SCOM_RW   );
+REG64( PHB_0_PHBRESET_REG                                      , RULL(0x0D01084A), SH_UNT_PHB_0    , SH_ACS_SCOM_RW   );
+REG64( PHB_1_PHBRESET_REG                                      , RULL(0x0E01084A), SH_UNT_PHB_1    , SH_ACS_SCOM_RW   );
+REG64( PHB_2_PHBRESET_REG                                      , RULL(0x0E01088A), SH_UNT_PHB_2    , SH_ACS_SCOM_RW   );
+REG64( PHB_3_PHBRESET_REG                                      , RULL(0x0F01084A), SH_UNT_PHB_3    , SH_ACS_SCOM_RW   );
+REG64( PHB_4_PHBRESET_REG                                      , RULL(0x0F01088A), SH_UNT_PHB_4    , SH_ACS_SCOM_RW   );
+REG64( PHB_5_PHBRESET_REG                                      , RULL(0x0F0108CA), SH_UNT_PHB_5    , SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK1_PHBRESET_REG                            , RULL(0x0D01088A), SH_UNT_PU_PBAIB_STACK1,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK2_PHBRESET_REG                            , RULL(0x0D0108CA), SH_UNT_PU_PBAIB_STACK2,
+       SH_ACS_SCOM_RW   );
+REG64( PU_PBAIB_STACK5_PHBRESET_REG                            , RULL(0x0E0108CA), SH_UNT_PU_PBAIB_STACK5,
+       SH_ACS_SCOM_RW   );
+
+REG64( PU_NPU0_SM0_PHY_BAR                                     , RULL(0x05011006), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_PHY_BAR                                     , RULL(0x05011026), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_PHY_BAR                                     , RULL(0x05011046), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_PHY_BAR                                     , RULL(0x05011066), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_PHY_BAR                                     , RULL(0x05011106), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_PHY_BAR                                     , RULL(0x05011126), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_PHY_BAR                                     , RULL(0x05011146), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_PHY_BAR                                     , RULL(0x05011166), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_PHY_BAR                                     , RULL(0x05011206), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_PHY_BAR                                     , RULL(0x05011226), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_PHY_BAR                                     , RULL(0x05011246), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_PHY_BAR                                     , RULL(0x05011266), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_PIBI2CM_ATOMIC_LOCK_REG_B                            , RULL(0x000A03FF), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBI2CM_ATOMIC_LOCK_REG_C                            , RULL(0x000A13FF), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBI2CM_ATOMIC_LOCK_REG_D                            , RULL(0x000A23FF), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBI2CM_ATOMIC_LOCK_REG_E                            , RULL(0x000A33FF), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBI2CM_PROTECT_MODE_REG_B                           , RULL(0x000A03FE), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBI2CM_PROTECT_MODE_REG_C                           , RULL(0x000A13FE), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBI2CM_PROTECT_MODE_REG_D                           , RULL(0x000A23FE), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBI2CM_PROTECT_MODE_REG_E                           , RULL(0x000A33FE), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_ADDRESS_REGISTER                              , RULL(0x00088001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_ADDRESS_REGISTER_FA                           , RULL(0x00088007), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_CONTROL_REGISTER                              , RULL(0x00088000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_REPAIR_REGISTER_0                             , RULL(0x0008800B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_REPAIR_REGISTER_1                             , RULL(0x0008800C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_REPAIR_REGISTER_2                             , RULL(0x0008800D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_REPAIR_REGISTER_3                             , RULL(0x0008800E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_RESET_REGISTER                                , RULL(0x00088006), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIBMEM_STATUS_REG                                    , RULL(0x00088005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIB_CMD_REG                                          , RULL(0x00090031), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PIB_DATA_REG                                         , RULL(0x00090032), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PIB_RESET_REG                                        , RULL(0x00090033), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_PLL_LOCK_REG                                        , RULL(0x0D0F0019), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_PLL_LOCK_REG                                      , RULL(0x0D0F0019), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_PLL_LOCK_REG                                      , RULL(0x0E0F0019), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_PLL_LOCK_REG                                      , RULL(0x0F0F0019), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_PMONCTL_REG                                         , RULL(0x04010C04), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_PMONCTL_REG                                       , RULL(0x04010C04), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_PMONCTL_REG                                       , RULL(0x04011004), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_PMONCTL_REG                                       , RULL(0x04011404), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( CAPP_PMU_CNTRA_CFG                                      , RULL(0x02010814), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_PMU_CNTRA_CFG                                    , RULL(0x02010814), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_PMU_CNTRA_CFG                                    , RULL(0x04010814), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_PMU_CNTRA_REG                                      , RULL(0x02010815), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_PMU_CNTRA_REG                                    , RULL(0x02010815), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_PMU_CNTRA_REG                                    , RULL(0x04010815), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_PMU_CNTRB_CFG                                      , RULL(0x02010824), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_PMU_CNTRB_CFG                                    , RULL(0x02010824), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_PMU_CNTRB_CFG                                    , RULL(0x04010824), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_PMU_CNTRB_REG                                      , RULL(0x02010825), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_PMU_CNTRB_REG                                    , RULL(0x02010825), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_PMU_CNTRB_REG                                    , RULL(0x04010825), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( PU_PPE_XIDBGPRO                                         , RULL(0x000E0005), SH_UNT          ,
+       SH_ACS_SCOM      ); //DUPS: 05012415, 0901104F, 0C01104F,
+
+REG64( PU_PPE_XIRAMDBG                                         , RULL(0x000E0003), SH_UNT          ,
+       SH_ACS_SCOM      ); //DUPS: 05012413, 0901104D, 0C01104D,
+
+REG64( PU_PPE_XIRAMEDR                                         , RULL(0x000E0004), SH_UNT          ,
+       SH_ACS_SCOM      ); //DUPS: 05012414, 0901104E, 0C01104E,
+
+REG64( PU_PPE_XIRAMGA                                          , RULL(0x000E0002), SH_UNT          ,
+       SH_ACS_SCOM_WO   ); //DUPS: 05012412, 0901104C, 0C01104C,
+
+REG64( PU_PPE_XIRAMRA                                          , RULL(0x000E0001), SH_UNT          ,
+       SH_ACS_SCOM_WO   ); //DUPS: 05012411, 0901104B, 0C01104B,
+
+REG64( PU_PPE_XIXCR                                            , RULL(0x000E0000), SH_UNT          ,
+       SH_ACS_SCOM_WO   ); //DUPS: 05012410, 0901104A, 0C01104A,
+
+REG64( NV_PRB_HA_PTR                                           , RULL(0x050110D1), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_PRB_HA_PTR                                         , RULL(0x050110D1), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_PRB_HA_PTR                                         , RULL(0x050110F1), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_PRB_HA_PTR                                         , RULL(0x050111D1), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_PRB_HA_PTR                                         , RULL(0x050111F1), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_PRB_HA_PTR                                 , RULL(0x050112D1), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_PRB_HA_PTR                                 , RULL(0x050112F1), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PREDV_REG                                           , RULL(0x04010C06), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_PREDV_REG                                         , RULL(0x04010C06), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_PREDV_REG                                         , RULL(0x04011006), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_PREDV_REG                                         , RULL(0x04011406), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PEC_PRE_COUNTER_REG                                     , RULL(0x0D0F0028), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_PRE_COUNTER_REG                                   , RULL(0x0D0F0028), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_PRE_COUNTER_REG                                   , RULL(0x0E0F0028), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_PRE_COUNTER_REG                                   , RULL(0x0F0F0028), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_PRGM_REGISTER                                        , RULL(0x00010009), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_PRIMARY_ADDRESS_REG                                 , RULL(0x0D0F0000), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_PRIMARY_ADDRESS_REG                               , RULL(0x0D0F0000), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_PRIMARY_ADDRESS_REG                               , RULL(0x0E0F0000), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_PRIMARY_ADDRESS_REG                               , RULL(0x0F0F0000), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( NV_PRI_CONFIG                                           , RULL(0x050110D6), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_PRI_CONFIG                                         , RULL(0x050110D6), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_PRI_CONFIG                                         , RULL(0x050110F6), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_PRI_CONFIG                                         , RULL(0x050111D6), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_PRI_CONFIG                                         , RULL(0x050111F6), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_PRI_CONFIG                                 , RULL(0x050112D6), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_PRI_CONFIG                                 , RULL(0x050112F6), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_PROBE_PROTECT_STATUS                                 , RULL(0x0001000A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_PROTECT_MODE_REG                                    , RULL(0x0D0F03FE), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_PROTECT_MODE_REG                                  , RULL(0x0D0F03FE), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_PROTECT_MODE_REG                                  , RULL(0x0E0F03FE), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_PROTECT_MODE_REG                                  , RULL(0x0F0F03FE), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_PRV_MISC_PPE                                         , RULL(0xC0002000), SH_UNT          , SH_ACS_PPE       );
+REG64( PU_PRV_MISC_PPE1                                        , RULL(0xC0002010), SH_UNT          , SH_ACS_PPE1      );
+REG64( PU_PRV_MISC_PPE2                                        , RULL(0xC0002018), SH_UNT          , SH_ACS_PPE2      );
+
+REG64( PU_PSCOM_ERROR_MASK                                     , RULL(0x06010002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_PSCOM_ERROR_MASK                                    , RULL(0x0D010002), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_PSCOM_ERROR_MASK                                  , RULL(0x0D010002), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_PSCOM_ERROR_MASK                                  , RULL(0x0E010002), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_PSCOM_ERROR_MASK                                  , RULL(0x0F010002), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_PSCOM_ERROR_MASK                                  , RULL(0x02010002), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_PSCOM_ERROR_MASK                                  , RULL(0x03010002), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_PSCOM_ERROR_MASK                                  , RULL(0x04010002), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_PSCOM_ERROR_MASK                                  , RULL(0x05010002), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PU_PSCOM_MODE_REG                                       , RULL(0x06010000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_PSCOM_MODE_REG                                      , RULL(0x0D010000), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_PSCOM_MODE_REG                                    , RULL(0x0D010000), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_PSCOM_MODE_REG                                    , RULL(0x0E010000), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_PSCOM_MODE_REG                                    , RULL(0x0F010000), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_PSCOM_MODE_REG                                    , RULL(0x02010000), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_PSCOM_MODE_REG                                    , RULL(0x03010000), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_PSCOM_MODE_REG                                    , RULL(0x04010000), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_PSCOM_MODE_REG                                    , RULL(0x05010000), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PU_PSCOM_STATUS_ERROR_REG                               , RULL(0x06010001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_PSCOM_STATUS_ERROR_REG                              , RULL(0x0D010001), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_PSCOM_STATUS_ERROR_REG                            , RULL(0x0D010001), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_PSCOM_STATUS_ERROR_REG                            , RULL(0x0E010001), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_PSCOM_STATUS_ERROR_REG                            , RULL(0x0F010001), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_PSCOM_STATUS_ERROR_REG                            , RULL(0x02010001), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_PSCOM_STATUS_ERROR_REG                            , RULL(0x03010001), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_PSCOM_STATUS_ERROR_REG                            , RULL(0x04010001), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_PSCOM_STATUS_ERROR_REG                            , RULL(0x05010001), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PU_PSIHB_DEBUG_REG                                      , RULL(0x05012911), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSIHB_ERROR_MASK_REG                                 , RULL(0x0501290F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSIHB_FIR_ACTION0_REG                                , RULL(0x05012906), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PSIHB_FIR_ACTION1_REG                                , RULL(0x05012907), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_PSIHB_FIR_MASK_REG                                   , RULL(0x05012903), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PSIHB_FIR_MASK_REG_AND                               , RULL(0x05012904), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PSIHB_FIR_MASK_REG_OR                                , RULL(0x05012905), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PSIHB_FIR_REG                                        , RULL(0x05012900), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PSIHB_FIR_REG_AND                                    , RULL(0x05012901), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PSIHB_FIR_REG_OR                                     , RULL(0x05012902), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PSIHB_INTERRUPT_CONTROL                              , RULL(0x05012915), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSIHB_INTERRUPT_LEVEL                                , RULL(0x05012919), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSIHB_INTERRUPT_STATUS                               , RULL(0x0501291A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSIHB_STATUS_CTL_REG_SCOM                            , RULL(0x0501290E), SH_UNT          , SH_ACS_SCOM      );
+REG64( PU_PSIHB_STATUS_CTL_REG_SCOM1                           , RULL(0x05012912), SH_UNT          , SH_ACS_SCOM1     );
+REG64( PU_PSIHB_STATUS_CTL_REG_SCOM2                           , RULL(0x05012913), SH_UNT          , SH_ACS_SCOM2     );
+
+REG64( PU_PSI_BRIDGE_BAR_REG                                   , RULL(0x0501290A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSI_BRIDGE_FSP_BAR_REG                               , RULL(0x0501290B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSI_FSP_MMR_REG                                      , RULL(0x0501290C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSI_TCE_ADDR_REG                                     , RULL(0x05012B44), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( CAPP_PSLTTMAP0                                          , RULL(0x0201082D), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_PSLTTMAP0                                        , RULL(0x0201082D), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_PSLTTMAP0                                        , RULL(0x0401082D), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_PSLTTMAP1                                          , RULL(0x0201082E), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_PSLTTMAP1                                        , RULL(0x0201082E), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_PSLTTMAP1                                        , RULL(0x0401082E), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_PSLTTMAP2                                          , RULL(0x0201082F), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_PSLTTMAP2                                        , RULL(0x0201082F), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_PSLTTMAP2                                        , RULL(0x0401082F), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_PSLTTMAP3                                          , RULL(0x02010830), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_PSLTTMAP3                                        , RULL(0x02010830), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_PSLTTMAP3                                        , RULL(0x04010830), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_DOORBELL_REG                                , RULL(0x000D0063), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PSU_HOST_DOORBELL_REG_AND                            , RULL(0x000D0064), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PSU_HOST_DOORBELL_REG_OR                             , RULL(0x000D0065), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_PSU_HOST_SBE_MBOX0_REG                               , RULL(0x000D0050), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_SBE_MBOX1_REG                               , RULL(0x000D0051), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_SBE_MBOX2_REG                               , RULL(0x000D0052), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_SBE_MBOX3_REG                               , RULL(0x000D0053), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_SBE_MBOX4_REG                               , RULL(0x000D0054), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_SBE_MBOX5_REG                               , RULL(0x000D0055), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_SBE_MBOX6_REG                               , RULL(0x000D0056), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_HOST_SBE_MBOX7_REG                               , RULL(0x000D0057), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR0_ACTCYCLECNT_REG                           , RULL(0x000D0023), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR0_CYCLECNT_REG                              , RULL(0x000D0022), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR0_EVENTCNT_REG                              , RULL(0x000D0024), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR0_FILTER_REG                                , RULL(0x000D0021), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR0_MAXCYCLECNT_REG                           , RULL(0x000D0025), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR0_MINCYCLECNT_REG                           , RULL(0x000D0026), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR0_STOP_TIMER_REG                            , RULL(0x000D0020), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR1_ACTCYCLECNT_REG                           , RULL(0x000D0033), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR1_CYCLECNT_REG                              , RULL(0x000D0032), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR1_EVENTCNT_REG                              , RULL(0x000D0034), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR1_FILTER_REG                                , RULL(0x000D0031), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR1_MAXCYCLECNT_REG                           , RULL(0x000D0035), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR1_MINCYCLECNT_REG                           , RULL(0x000D0036), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR1_STOP_TIMER_REG                            , RULL(0x000D0030), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR2_ACTCYCLECNT_REG                           , RULL(0x000D0043), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR2_CYCLECNT_REG                              , RULL(0x000D0042), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR2_EVENTCNT_REG                              , RULL(0x000D0044), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR2_FILTER_REG                                , RULL(0x000D0041), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR2_MAXCYCLECNT_REG                           , RULL(0x000D0045), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR2_MINCYCLECNT_REG                           , RULL(0x000D0046), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR2_STOP_TIMER_REG                            , RULL(0x000D0040), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_INSTR_CTRL_STATUS_REG                            , RULL(0x000D0010), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG                   , RULL(0x000D0005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG                , RULL(0x000D0006), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG                , RULL(0x000D0007), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_CTRL_STATUS_REG                          , RULL(0x000D0000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_FILTER_REG                               , RULL(0x000D0001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_LAST_ADDR_TRACE_REG                      , RULL(0x000D0002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_LAST_REQDATA_TRACE_REG                   , RULL(0x000D0003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG                   , RULL(0x000D0004), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_PSU_SBE_DOORBELL_REG                                 , RULL(0x000D0060), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_PSU_SBE_DOORBELL_REG_AND                             , RULL(0x000D0061), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_PSU_SBE_DOORBELL_REG_OR                              , RULL(0x000D0062), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_RCV_ERRLOG0_REG                                      , RULL(0x00090022), SH_UNT          , SH_ACS_SCOM_WAND );
+
+REG64( PU_RCV_ERRLOG1_REG                                      , RULL(0x00090023), SH_UNT          , SH_ACS_SCOM_WAND );
+
+REG64( PEC_RECOV_INTERRUPT_REG                                 , RULL(0x0D0F001B), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_RECOV_INTERRUPT_REG                               , RULL(0x0D0F001B), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_RECOV_INTERRUPT_REG                               , RULL(0x0E0F001B), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_RECOV_INTERRUPT_REG                               , RULL(0x0F0F001B), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_REM0                                            , RULL(0x050110AD), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_REM0                                            , RULL(0x050111AD), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_REM0                                            , RULL(0x050112AD), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_REM1                                            , RULL(0x050110AE), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_REM1                                            , RULL(0x050111AE), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_REM1                                            , RULL(0x050112AE), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_RESET_REGISTER                                       , RULL(0x00010001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RESET_REGISTER_B                                     , RULL(0x000A0001), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_RESET_REGISTER_C                                     , RULL(0x000A1001), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_RESET_REGISTER_D                                     , RULL(0x000A2001), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_RESET_REGISTER_E                                     , RULL(0x000A3001), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B                 , RULL(0x000A000D), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C                 , RULL(0x000A100D), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D                 , RULL(0x000A200D), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E                 , RULL(0x000A300D), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PEC_RFIR                                                , RULL(0x0D040001), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_RFIR                                              , RULL(0x0D040001), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_RFIR                                              , RULL(0x0E040001), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_RFIR                                              , RULL(0x0F040001), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_RING_FENCE_MASK_LATCH_REG                            , RULL(0x06010008), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_RING_FENCE_MASK_LATCH_REG                           , RULL(0x0D010008), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_RING_FENCE_MASK_LATCH_REG                         , RULL(0x0D010008), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_RING_FENCE_MASK_LATCH_REG                         , RULL(0x0E010008), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_RING_FENCE_MASK_LATCH_REG                         , RULL(0x0F010008), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_RING_FENCE_MASK_LATCH_REG                         , RULL(0x02010008), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_RING_FENCE_MASK_LATCH_REG                         , RULL(0x03010008), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_RING_FENCE_MASK_LATCH_REG                         , RULL(0x04010008), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_RING_FENCE_MASK_LATCH_REG                         , RULL(0x05010008), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PU_NPU_CTL_RLX_CONFIG                                   , RULL(0x05011381), SH_UNT_PU_NPU_CTL,
+       SH_ACS_SCOM      );
+
+REG64( PU_RNG_FAILED_INT                                       , RULL(0x020110E7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( NV_RSP_DA_PTR                                           , RULL(0x050110D5), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_RSP_DA_PTR                                         , RULL(0x050110D5), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_RSP_DA_PTR                                         , RULL(0x050110F5), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_RSP_DA_PTR                                         , RULL(0x050111D5), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_RSP_DA_PTR                                         , RULL(0x050111F5), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_RSP_DA_PTR                                 , RULL(0x050112D5), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_RSP_DA_PTR                                 , RULL(0x050112F5), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( NV_RSP_HA_PTR                                           , RULL(0x050110D3), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_RSP_HA_PTR                                         , RULL(0x050110D3), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_RSP_HA_PTR                                         , RULL(0x050110F3), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_RSP_HA_PTR                                         , RULL(0x050111D3), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_RSP_HA_PTR                                         , RULL(0x050111F3), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_RSP_HA_PTR                                 , RULL(0x050112D3), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_RSP_HA_PTR                                 , RULL(0x050112F3), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_RX_CH_FSM_REG                                        , RULL(0x0501280D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_CH_INTADDR_REG                                    , RULL(0x05012818), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_CH_MISC_REG                                       , RULL(0x0501281B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_CTRL_STAT_REG                                     , RULL(0x05012808), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_DBFF_REG0                                         , RULL(0x05012819), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_DBFF_REG1                                         , RULL(0x0501281A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_DF_FSM_REG                                        , RULL(0x0501280E), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_ERROR_REG_WCLEAR                                  , RULL(0x0501280A), SH_UNT          ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PU_RX_ERROR_REG_OR                                      , RULL(0x0501280C), SH_UNT          , SH_ACS_SCOM1_OR  );
+
+REG64( PU_RX_ERR_MODE                                          , RULL(0x0501280F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_MASK_REG                                          , RULL(0x0501280B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_PSI_CNTL                                          , RULL(0x04011820), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_PSI_MODE                                          , RULL(0x04011821), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_RX_PSI_STATUS                                        , RULL(0x04011822), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_SCAN_REGION_TYPE                                    , RULL(0x0D030005), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_SCAN_REGION_TYPE                                  , RULL(0x0D030005), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_SCAN_REGION_TYPE                                  , RULL(0x0E030005), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_SCAN_REGION_TYPE                                  , RULL(0x0F030005), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_SCOM_PPE_CNTL                                        , RULL(0x09011060), SH_UNT          ,
+       SH_ACS_SCOM      ); //DUPS: 0C011060,
+
+REG64( PU_SCOM_PPE_FLAGS                                       , RULL(0x09011063), SH_UNT          ,
+       SH_ACS_SCOM_RW   ); //DUPS: 0C011063,
+REG64( PU_SCOM_PPE_FLAGS_OR                                    , RULL(0x09011064), SH_UNT          ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 0C011064,
+REG64( PU_SCOM_PPE_FLAGS_CLEAR                                 , RULL(0x09011065), SH_UNT          ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 0C011065,
+
+REG64( PU_SCOM_PPE_WORK_REG1                                   , RULL(0x09011061), SH_UNT          ,
+       SH_ACS_SCOM      ); //DUPS: 0C011061,
+
+REG64( PU_SCOM_PPE_WORK_REG2                                   , RULL(0x09011062), SH_UNT          ,
+       SH_ACS_SCOM      ); //DUPS: 0C011062,
+
+REG64( PU_SCRATCH0_PPE                                         , RULL(0xC0001000), SH_UNT          , SH_ACS_PPE       );
+REG64( PU_SCRATCH0_PPE1                                        , RULL(0xC0001010), SH_UNT          , SH_ACS_PPE1      );
+REG64( PU_SCRATCH0_PPE2                                        , RULL(0xC0001018), SH_UNT          , SH_ACS_PPE2      );
+REG64( PU_NPU0_SCRATCH0                                        , RULL(0x050110A3), SH_UNT_PU_NPU0  , SH_ACS_SCOM      );
+REG64( PU_NPU1_SCRATCH0                                        , RULL(0x050111A3), SH_UNT_PU_NPU1  , SH_ACS_SCOM      );
+REG64( PU_NPU2_SCRATCH0                                        , RULL(0x050112A3), SH_UNT_PU_NPU2  , SH_ACS_SCOM      );
+
+REG64( PU_SCRATCH1_PPE                                         , RULL(0xC0001020), SH_UNT          , SH_ACS_PPE       );
+REG64( PU_SCRATCH1_PPE1                                        , RULL(0xC0001030), SH_UNT          , SH_ACS_PPE1      );
+REG64( PU_SCRATCH1_PPE2                                        , RULL(0xC0001038), SH_UNT          , SH_ACS_PPE2      );
+REG64( NV_SCRATCH1                                             , RULL(0x050110DA), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_SCRATCH1                                           , RULL(0x050110DA), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_SCRATCH1                                           , RULL(0x050110FA), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_SCRATCH1                                           , RULL(0x050111DA), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_SCRATCH1                                           , RULL(0x050111FA), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU0_DAT_SCRATCH1                                    , RULL(0x050110BC), SH_UNT_PU_NPU0_DAT,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_DAT_SCRATCH1                                    , RULL(0x050111BC), SH_UNT_PU_NPU1_DAT,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_DAT_SCRATCH1                                    , RULL(0x050112BC), SH_UNT_PU_NPU2_DAT,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_SCRATCH1                                   , RULL(0x050112DA), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_SCRATCH1                                   , RULL(0x050112FA), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_SCRATCH2_PPE                                         , RULL(0xC0001040), SH_UNT          , SH_ACS_PPE       );
+REG64( PU_SCRATCH2_PPE1                                        , RULL(0xC0001050), SH_UNT          , SH_ACS_PPE1      );
+REG64( PU_SCRATCH2_PPE2                                        , RULL(0xC0001058), SH_UNT          , SH_ACS_PPE2      );
+REG64( NV_SCRATCH2                                             , RULL(0x050110CA), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_SCRATCH2                                           , RULL(0x050110CA), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_SCRATCH2                                           , RULL(0x050110EA), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_SCRATCH2                                           , RULL(0x050111CA), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_SCRATCH2                                           , RULL(0x050111EA), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_SCRATCH2                                   , RULL(0x050112CA), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_SCRATCH2                                   , RULL(0x050112EA), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_SCRATCH3_PPE                                         , RULL(0xC0001060), SH_UNT          , SH_ACS_PPE       );
+REG64( PU_SCRATCH3_PPE1                                        , RULL(0xC0001070), SH_UNT          , SH_ACS_PPE1      );
+REG64( PU_SCRATCH3_PPE2                                        , RULL(0xC0001078), SH_UNT          , SH_ACS_PPE2      );
+REG64( NV_SCRATCH3                                             , RULL(0x050110CB), SH_UNT_NV       , SH_ACS_SCOM      );
+REG64( NV_0_SCRATCH3                                           , RULL(0x050110CB), SH_UNT_NV_0     , SH_ACS_SCOM      );
+REG64( NV_1_SCRATCH3                                           , RULL(0x050110EB), SH_UNT_NV_1     , SH_ACS_SCOM      );
+REG64( NV_2_SCRATCH3                                           , RULL(0x050111CB), SH_UNT_NV_2     , SH_ACS_SCOM      );
+REG64( NV_3_SCRATCH3                                           , RULL(0x050111EB), SH_UNT_NV_3     , SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL0_SCRATCH3                                   , RULL(0x050112CB), SH_UNT_PU_NPU2_NTL0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_NTL1_SCRATCH3                                   , RULL(0x050112EB), SH_UNT_PU_NPU2_NTL1,
+       SH_ACS_SCOM      );
+
+REG64( PU_SECURITY_SWITCH_REGISTER_SCOM                        , RULL(0x00010005), SH_UNT          , SH_ACS_SCOM_WOR  );
+REG64( PU_SECURITY_SWITCH_REGISTER_SCOM1                       , RULL(0x00010006), SH_UNT          , SH_ACS_SCOM1     );
+
+REG64( PU_SEND_WC_BASE_ADDR                                    , RULL(0x020110D2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_SKITTER_CLKSRC_REG                                  , RULL(0x0D050016), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_SKITTER_CLKSRC_REG                                , RULL(0x0D050016), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_SKITTER_CLKSRC_REG                                , RULL(0x0E050016), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_SKITTER_CLKSRC_REG                                , RULL(0x0F050016), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_SKITTER_DATA0                                       , RULL(0x0D050019), SH_UNT_PEC      , SH_ACS_SCOM_RO   );
+REG64( PEC_0_SKITTER_DATA0                                     , RULL(0x0D050019), SH_UNT_PEC_0    , SH_ACS_SCOM_RO   );
+REG64( PEC_1_SKITTER_DATA0                                     , RULL(0x0E050019), SH_UNT_PEC_1    , SH_ACS_SCOM_RO   );
+REG64( PEC_2_SKITTER_DATA0                                     , RULL(0x0F050019), SH_UNT_PEC_2    , SH_ACS_SCOM_RO   );
+
+REG64( PEC_SKITTER_DATA1                                       , RULL(0x0D05001A), SH_UNT_PEC      , SH_ACS_SCOM_RO   );
+REG64( PEC_0_SKITTER_DATA1                                     , RULL(0x0D05001A), SH_UNT_PEC_0    , SH_ACS_SCOM_RO   );
+REG64( PEC_1_SKITTER_DATA1                                     , RULL(0x0E05001A), SH_UNT_PEC_1    , SH_ACS_SCOM_RO   );
+REG64( PEC_2_SKITTER_DATA1                                     , RULL(0x0F05001A), SH_UNT_PEC_2    , SH_ACS_SCOM_RO   );
+
+REG64( PEC_SKITTER_DATA2                                       , RULL(0x0D05001B), SH_UNT_PEC      , SH_ACS_SCOM_RO   );
+REG64( PEC_0_SKITTER_DATA2                                     , RULL(0x0D05001B), SH_UNT_PEC_0    , SH_ACS_SCOM_RO   );
+REG64( PEC_1_SKITTER_DATA2                                     , RULL(0x0E05001B), SH_UNT_PEC_1    , SH_ACS_SCOM_RO   );
+REG64( PEC_2_SKITTER_DATA2                                     , RULL(0x0F05001B), SH_UNT_PEC_2    , SH_ACS_SCOM_RO   );
+
+REG64( PEC_SKITTER_FORCE_REG                                   , RULL(0x0D050014), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_SKITTER_FORCE_REG                                 , RULL(0x0D050014), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_SKITTER_FORCE_REG                                 , RULL(0x0E050014), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_SKITTER_FORCE_REG                                 , RULL(0x0F050014), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_SKITTER_MODE_REG                                    , RULL(0x0D050010), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_SKITTER_MODE_REG                                  , RULL(0x0D050010), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_SKITTER_MODE_REG                                  , RULL(0x0E050010), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_SKITTER_MODE_REG                                  , RULL(0x0F050010), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_SLAVE_CONFIG_REG                                    , RULL(0x0D0F001E), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_SLAVE_CONFIG_REG                                  , RULL(0x0D0F001E), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_SLAVE_CONFIG_REG                                  , RULL(0x0E0F001E), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_SLAVE_CONFIG_REG                                  , RULL(0x0F0F001E), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_SM_STATUS                                   , RULL(0x05011016), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_SM_STATUS                                   , RULL(0x05011036), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_SM_STATUS                                   , RULL(0x05011056), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_SM_STATUS                                   , RULL(0x05011076), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_SM_STATUS                                   , RULL(0x05011116), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_SM_STATUS                                   , RULL(0x05011136), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_SM_STATUS                                   , RULL(0x05011156), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_SM_STATUS                                   , RULL(0x05011176), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_SM_STATUS                                   , RULL(0x05011216), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_SM_STATUS                                   , RULL(0x05011236), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_SM_STATUS                                   , RULL(0x05011256), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_SM_STATUS                                   , RULL(0x05011276), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_SND_MODE_REG                                         , RULL(0x00090021), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SND_STAT_REG                                         , RULL(0x00090020), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_SPATTN_SCOM                                         , RULL(0x0D040004), SH_UNT_PEC      , SH_ACS_SCOM_RO   );
+REG64( PEC_SPATTN_SCOM1                                        , RULL(0x0D040005), SH_UNT_PEC      , SH_ACS_SCOM1_NC  );
+REG64( PEC_SPATTN_SCOM2                                        , RULL(0x0D040006), SH_UNT_PEC      , SH_ACS_SCOM2_NC  );
+REG64( PEC_0_SPATTN_SCOM                                       , RULL(0x0D040004), SH_UNT_PEC_0    , SH_ACS_SCOM_RO   );
+REG64( PEC_0_SPATTN_SCOM1                                      , RULL(0x0D040005), SH_UNT_PEC_0    , SH_ACS_SCOM1_NC  );
+REG64( PEC_0_SPATTN_SCOM2                                      , RULL(0x0D040006), SH_UNT_PEC_0    , SH_ACS_SCOM2_NC  );
+REG64( PEC_1_SPATTN_SCOM                                       , RULL(0x0E040004), SH_UNT_PEC_1    , SH_ACS_SCOM_RO   );
+REG64( PEC_1_SPATTN_SCOM1                                      , RULL(0x0E040005), SH_UNT_PEC_1    , SH_ACS_SCOM1_NC  );
+REG64( PEC_1_SPATTN_SCOM2                                      , RULL(0x0E040006), SH_UNT_PEC_1    , SH_ACS_SCOM2_NC  );
+REG64( PEC_2_SPATTN_SCOM                                       , RULL(0x0F040004), SH_UNT_PEC_2    , SH_ACS_SCOM_RO   );
+REG64( PEC_2_SPATTN_SCOM1                                      , RULL(0x0F040005), SH_UNT_PEC_2    , SH_ACS_SCOM1_NC  );
+REG64( PEC_2_SPATTN_SCOM2                                      , RULL(0x0F040006), SH_UNT_PEC_2    , SH_ACS_SCOM2_NC  );
+
+REG64( PEC_SPA_MASK                                            , RULL(0x0D040007), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_SPA_MASK                                          , RULL(0x0D040007), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_SPA_MASK                                          , RULL(0x0E040007), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_SPA_MASK                                          , RULL(0x0F040007), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_SPIMPSS_ADC_CTRL_REG0                                , RULL(0x00070000), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_100NS_REG                                     , RULL(0x00070028), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_CMD_REG                                   , RULL(0x00070004), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_CTRL_REG1                                 , RULL(0x00070001), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_CTRL_REG2                                 , RULL(0x00070002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_RDATA_REG0                                , RULL(0x00070020), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_RDATA_REG1                                , RULL(0x00070021), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_RDATA_REG2                                , RULL(0x00070022), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_RDATA_REG3                                , RULL(0x00070023), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_RESET_REGISTER                            , RULL(0x00070005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_STATUS_REG                                , RULL(0x00070003), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_ADC_WDATA_REG                                 , RULL(0x00070010), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_COMMAND_REG                               , RULL(0x00070044), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_CTRL_REG0                                 , RULL(0x00070040), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_CTRL_REG1                                 , RULL(0x00070041), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_CTRL_REG2                                 , RULL(0x00070042), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_RDATA_REG                                 , RULL(0x00070060), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_RESET_REGISTER                            , RULL(0x00070045), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_STATUS_REG                                , RULL(0x00070043), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SPIPSS_P2S_WDATA_REG                                 , RULL(0x00070050), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SRAM_SRBV0_OCI                                       , RULL(0xC0050020), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_SRAM_SRBV0_SCOM                                      , RULL(0x0006A004), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SRAM_SRBV1_OCI                                       , RULL(0xC0050028), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_SRAM_SRBV1_SCOM                                      , RULL(0x0006A005), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SRAM_SRBV2_OCI                                       , RULL(0xC0050030), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_SRAM_SRBV2_SCOM                                      , RULL(0x0006A006), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SRAM_SRBV3_OCI                                       , RULL(0xC0050038), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_SRAM_SRBV3_SCOM                                      , RULL(0x0006A007), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SRAM_SRCHSW_OCI                                      , RULL(0xC0050040), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_SRAM_SRCHSW_SCOM                                     , RULL(0x0006A008), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SRAM_SREAR_OCI                                       , RULL(0xC0050018), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_SRAM_SREAR_SCOM                                      , RULL(0x0006A003), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SRAM_SRMAP_OCI                                       , RULL(0xC0050010), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_SRAM_SRMAP_SCOM                                      , RULL(0x0006A002), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SRAM_SRMR_OCI                                        , RULL(0xC0050008), SH_UNT          , SH_ACS_OCI       );
+REG64( PU_SRAM_SRMR_SCOM                                       , RULL(0x0006A001), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_STATUS_REGISTER                                      , RULL(0x00010002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_STATUS_REGISTER_B                                    , RULL(0x000A0002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_STATUS_REGISTER_C                                    , RULL(0x000A1002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_STATUS_REGISTER_D                                    , RULL(0x000A2002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_STATUS_REGISTER_E                                    , RULL(0x000A3002), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_STATUS_REGISTER_ENGINE_B                             , RULL(0x000A000B), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_STATUS_REGISTER_ENGINE_C                             , RULL(0x000A100B), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_STATUS_REGISTER_ENGINE_D                             , RULL(0x000A200B), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PU_STATUS_REGISTER_ENGINE_E                             , RULL(0x000A300B), SH_UNT          ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PEC_SUM_MASK_REG                                        , RULL(0x0D040017), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_SUM_MASK_REG                                      , RULL(0x0D040017), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_SUM_MASK_REG                                      , RULL(0x0E040017), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_SUM_MASK_REG                                      , RULL(0x0F040017), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_SU_CH0_ABORT_CSB                                     , RULL(0x02011043), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_CH1_ABORT_CSB                                     , RULL(0x02011045), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_CH2_ABORT_CSB                                     , RULL(0x02011047), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_CH3_ABORT_CSB                                     , RULL(0x02011049), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_CH4_ABORT_CSB                                     , RULL(0x0201104B), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_CRB_KILL_REQ                                      , RULL(0x02011053), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SU_DMA_ERROR_REPORT_0                                , RULL(0x02011057), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_DMA_ERROR_REPORT_1                                , RULL(0x02011058), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_ENGINE_ENABLE                                     , RULL(0x02011041), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SU_ERAT_ERROR_RPT                                    , RULL(0x020110D7), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_INBOUND_WRITE_CONTROL                             , RULL(0x02011042), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SU_PERFMON_CONTROL_0                                 , RULL(0x02011054), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SU_PERFMON_CONTROL_1                                 , RULL(0x02011055), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_SU_STATUS                                            , RULL(0x02011040), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SU_UMAC_ERROR_RPT                                    , RULL(0x020110D3), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SU_UMAC_ERROR_RPT1                                   , RULL(0x020110D8), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SYM_HI_PRIOR_RCV_FIFO_ASB                            , RULL(0x020110C7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SYM_HI_PRIOR_RCV_FIFO_BAR                            , RULL(0x020110C1), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL                           , RULL(0x020110C4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SYM_LO_PRIOR_RCV_FIFO_ASB                            , RULL(0x020110D0), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SYM_LO_PRIOR_RCV_FIFO_BAR                            , RULL(0x020110CA), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SYM_LO_PRIOR_RCV_FIFO_CNTL                           , RULL(0x020110CD), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_SYM_MAX_BYTE_CNT                                     , RULL(0x0201105A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PEC_SYNC_CONFIG                                         , RULL(0x0D030000), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_SYNC_CONFIG                                       , RULL(0x0D030000), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_SYNC_CONFIG                                       , RULL(0x0E030000), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_SYNC_CONFIG                                       , RULL(0x0F030000), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_SYNC_FIR_ACTION0_REG                                 , RULL(0x050129C6), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SYNC_FIR_ACTION1_REG                                 , RULL(0x050129C7), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_SYNC_FIR_MASK_REG                                    , RULL(0x050129C3), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_SYNC_FIR_MASK_REG_AND                                , RULL(0x050129C4), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_SYNC_FIR_MASK_REG_OR                                 , RULL(0x050129C5), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_SYNC_FIR_REG                                         , RULL(0x050129C0), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_SYNC_FIR_REG_AND                                     , RULL(0x050129C1), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_SYNC_FIR_REG_OR                                      , RULL(0x050129C2), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_NPU_SM1_TCE_KILL                                     , RULL(0x05011324), SH_UNT_PU_NPU_SM1,
+       SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA0_TRACE_HI_DATA_REG                   , RULL(0x07010C00), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG                   , RULL(0x07010C01), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG                 , RULL(0x07010C02), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_0               , RULL(0x07010C03), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_1               , RULL(0x07010C04), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2               , RULL(0x07010C05), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3               , RULL(0x07010C06), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4               , RULL(0x07010C07), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5               , RULL(0x07010C08), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9               , RULL(0x07010C09), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA1_TRACE_HI_DATA_REG                   , RULL(0x07010C40), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG                   , RULL(0x07010C41), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG                 , RULL(0x07010C42), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_0               , RULL(0x07010C43), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_1               , RULL(0x07010C44), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_2               , RULL(0x07010C45), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_3               , RULL(0x07010C46), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_4               , RULL(0x07010C47), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_5               , RULL(0x07010C48), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9               , RULL(0x07010C49), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA0_TRACE_HI_DATA_REG                   , RULL(0x08010C00), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG                   , RULL(0x08010C01), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG                 , RULL(0x08010C02), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_0               , RULL(0x08010C03), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_1               , RULL(0x08010C04), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_2               , RULL(0x08010C05), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_3               , RULL(0x08010C06), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_4               , RULL(0x08010C07), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_5               , RULL(0x08010C08), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9               , RULL(0x08010C09), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA1_TRACE_HI_DATA_REG                   , RULL(0x08010C40), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG                   , RULL(0x08010C41), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG                 , RULL(0x08010C42), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_0               , RULL(0x08010C43), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_1               , RULL(0x08010C44), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_2               , RULL(0x08010C45), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_3               , RULL(0x08010C46), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_4               , RULL(0x08010C47), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_5               , RULL(0x08010C48), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9               , RULL(0x08010C49), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG                      , RULL(0x02010400), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG                      , RULL(0x02010401), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x02010402), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x02010403), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x02010404), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x02010405), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x02010406), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x02010407), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x02010408), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x02010409), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_HI_DATA_REG                      , RULL(0x02010440), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG                      , RULL(0x02010441), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG                    , RULL(0x02010442), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_0                  , RULL(0x02010443), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_1                  , RULL(0x02010444), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2                  , RULL(0x02010445), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3                  , RULL(0x02010446), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4                  , RULL(0x02010447), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5                  , RULL(0x02010448), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9                  , RULL(0x02010449), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TR0_TRACE_HI_DATA_REG                      , RULL(0x02010480), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG                      , RULL(0x02010481), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x02010482), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x02010483), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x02010484), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x02010485), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x02010486), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x02010487), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x02010488), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x02010489), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_HI_DATA_REG                      , RULL(0x03010400), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG                      , RULL(0x03010401), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x03010402), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x03010403), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x03010404), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x03010405), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x03010406), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x03010407), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x03010408), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x03010409), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_HI_DATA_REG                      , RULL(0x03010440), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG                      , RULL(0x03010441), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG                    , RULL(0x03010442), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_0                  , RULL(0x03010443), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_1                  , RULL(0x03010444), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2                  , RULL(0x03010445), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3                  , RULL(0x03010446), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4                  , RULL(0x03010447), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5                  , RULL(0x03010448), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9                  , RULL(0x03010449), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_HI_DATA_REG                      , RULL(0x03010480), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG                      , RULL(0x03010481), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x03010482), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x03010483), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x03010484), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x03010485), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x03010486), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x03010487), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x03010488), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x03010489), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_HI_DATA_REG                      , RULL(0x030104C0), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG                      , RULL(0x030104C1), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG                    , RULL(0x030104C2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_0                  , RULL(0x030104C3), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_1                  , RULL(0x030104C4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2                  , RULL(0x030104C5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3                  , RULL(0x030104C6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4                  , RULL(0x030104C7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5                  , RULL(0x030104C8), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9                  , RULL(0x030104C9), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_HI_DATA_REG                      , RULL(0x03010500), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG                      , RULL(0x03010501), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x03010502), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x03010503), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x03010504), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x03010505), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x03010506), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x03010507), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x03010508), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x03010509), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_HI_DATA_REG                      , RULL(0x03010540), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG                      , RULL(0x03010541), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG                    , RULL(0x03010542), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_0                  , RULL(0x03010543), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_1                  , RULL(0x03010544), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2                  , RULL(0x03010545), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3                  , RULL(0x03010546), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4                  , RULL(0x03010547), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5                  , RULL(0x03010548), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9                  , RULL(0x03010549), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_HI_DATA_REG                      , RULL(0x03010580), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG                      , RULL(0x03010581), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x03010582), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x03010583), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x03010584), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x03010585), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x03010586), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x03010587), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x03010588), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x03010589), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_HI_DATA_REG                      , RULL(0x030105C0), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG                      , RULL(0x030105C1), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG                    , RULL(0x030105C2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_0                  , RULL(0x030105C3), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_1                  , RULL(0x030105C4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2                  , RULL(0x030105C5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3                  , RULL(0x030105C6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4                  , RULL(0x030105C7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5                  , RULL(0x030105C8), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9                  , RULL(0x030105C9), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_HI_DATA_REG                      , RULL(0x03010600), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG                      , RULL(0x03010601), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x03010602), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x03010603), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x03010604), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x03010605), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x03010606), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x03010607), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x03010608), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x03010609), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_HI_DATA_REG                      , RULL(0x03010640), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG                      , RULL(0x03010641), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG                    , RULL(0x03010642), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_0                  , RULL(0x03010643), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_1                  , RULL(0x03010644), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2                  , RULL(0x03010645), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3                  , RULL(0x03010646), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4                  , RULL(0x03010647), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5                  , RULL(0x03010648), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9                  , RULL(0x03010649), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_HI_DATA_REG                      , RULL(0x04010400), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG                      , RULL(0x04010401), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x04010402), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x04010403), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x04010404), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x04010405), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x04010406), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x04010407), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x04010408), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x04010409), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_HI_DATA_REG                      , RULL(0x04010440), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG                      , RULL(0x04010441), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG                    , RULL(0x04010442), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_0                  , RULL(0x04010443), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_1                  , RULL(0x04010444), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2                  , RULL(0x04010445), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3                  , RULL(0x04010446), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4                  , RULL(0x04010447), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5                  , RULL(0x04010448), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9                  , RULL(0x04010449), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_HI_DATA_REG                      , RULL(0x05010400), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG                      , RULL(0x05010401), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x05010402), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x05010403), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x05010404), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x05010405), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x05010406), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x05010407), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x05010408), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x05010409), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_HI_DATA_REG                      , RULL(0x05010440), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG                      , RULL(0x05010441), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG                    , RULL(0x05010442), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_0                  , RULL(0x05010443), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_1                  , RULL(0x05010444), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2                  , RULL(0x05010445), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3                  , RULL(0x05010446), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4                  , RULL(0x05010447), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5                  , RULL(0x05010448), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9                  , RULL(0x05010449), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_HI_DATA_REG                      , RULL(0x05010480), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG                      , RULL(0x05010481), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x05010482), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x05010483), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x05010484), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x05010485), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x05010486), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x05010487), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x05010488), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x05010489), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_HI_DATA_REG                      , RULL(0x050104C0), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG                      , RULL(0x050104C1), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG                    , RULL(0x050104C2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_0                  , RULL(0x050104C3), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_1                  , RULL(0x050104C4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2                  , RULL(0x050104C5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3                  , RULL(0x050104C6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4                  , RULL(0x050104C7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5                  , RULL(0x050104C8), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9                  , RULL(0x050104C9), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_HI_DATA_REG                      , RULL(0x05010500), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG                      , RULL(0x05010501), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x05010502), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x05010503), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x05010504), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x05010505), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x05010506), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x05010507), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x05010508), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x05010509), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_HI_DATA_REG                      , RULL(0x05010540), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG                      , RULL(0x05010541), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG                    , RULL(0x05010542), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_0                  , RULL(0x05010543), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_1                  , RULL(0x05010544), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2                  , RULL(0x05010545), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3                  , RULL(0x05010546), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4                  , RULL(0x05010547), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5                  , RULL(0x05010548), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9                  , RULL(0x05010549), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_HI_DATA_REG                      , RULL(0x05010580), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG                      , RULL(0x05010581), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x05010582), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x05010583), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x05010584), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x05010585), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x05010586), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x05010587), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x05010588), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x05010589), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_HI_DATA_REG                      , RULL(0x050105C0), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG                      , RULL(0x050105C1), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG                    , RULL(0x050105C2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_0                  , RULL(0x050105C3), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_1                  , RULL(0x050105C4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2                  , RULL(0x050105C5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3                  , RULL(0x050105C6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4                  , RULL(0x050105C7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5                  , RULL(0x050105C8), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9                  , RULL(0x050105C9), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TR0_TRACE_HI_DATA_REG                      , RULL(0x05010600), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG                      , RULL(0x05010601), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x05010602), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x05010603), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x05010604), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x05010605), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x05010606), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x05010607), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x05010608), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x05010609), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_HI_DATA_REG                      , RULL(0x05010680), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG                      , RULL(0x05010681), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x05010682), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x05010683), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x05010684), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x05010685), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x05010686), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x05010687), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x05010688), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x05010689), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_HI_DATA_REG                      , RULL(0x050106C0), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG                      , RULL(0x050106C1), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG                    , RULL(0x050106C2), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_0                  , RULL(0x050106C3), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_1                  , RULL(0x050106C4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2                  , RULL(0x050106C5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3                  , RULL(0x050106C6), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4                  , RULL(0x050106C7), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5                  , RULL(0x050106C8), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9                  , RULL(0x050106C9), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_TCPCI0_TRA0_TR0_TRACE_HI_DATA_REG                   , RULL(0x0D010400), SH_UNT_PEC      , SH_ACS_SCOM_RO   );
+REG64( PEC_0_TCPCI0_TRA0_TR0_TRACE_HI_DATA_REG                 , RULL(0x0D010400), SH_UNT_PEC_0    , SH_ACS_SCOM_RO   );
+
+REG64( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG                   , RULL(0x0D010401), SH_UNT_PEC      , SH_ACS_SCOM_RO   );
+REG64( PEC_0_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG                 , RULL(0x0D010401), SH_UNT_PEC_0    , SH_ACS_SCOM_RO   );
+
+REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG                 , RULL(0x0D010402), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG               , RULL(0x0D010402), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+
+REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_0               , RULL(0x0D010403), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_0             , RULL(0x0D010403), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+
+REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_1               , RULL(0x0D010404), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_1             , RULL(0x0D010404), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+
+REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_2               , RULL(0x0D010405), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_2             , RULL(0x0D010405), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+
+REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_3               , RULL(0x0D010406), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_3             , RULL(0x0D010406), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+
+REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_4               , RULL(0x0D010407), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_4             , RULL(0x0D010407), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+
+REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_5               , RULL(0x0D010408), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_5             , RULL(0x0D010408), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+
+REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9               , RULL(0x0D010409), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9             , RULL(0x0D010409), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+
+REG64( PEC_1_TCPCI1_TRA0_TR0_TRACE_HI_DATA_REG                 , RULL(0x0E010400), SH_UNT_PEC_1    , SH_ACS_SCOM_RO   );
+
+REG64( PEC_1_TCPCI1_TRA0_TR0_TRACE_LO_DATA_REG                 , RULL(0x0E010401), SH_UNT_PEC_1    , SH_ACS_SCOM_RO   );
+
+REG64( PEC_1_TCPCI1_TRA0_TR0_TRACE_TRCTRL_CONFIG               , RULL(0x0E010402), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+
+REG64( PEC_1_TCPCI1_TRA0_TR0_TRACE_TRDATA_CONFIG_0             , RULL(0x0E010403), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+
+REG64( PEC_1_TCPCI1_TRA0_TR0_TRACE_TRDATA_CONFIG_1             , RULL(0x0E010404), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+
+REG64( PEC_1_TCPCI1_TRA0_TR0_TRACE_TRDATA_CONFIG_2             , RULL(0x0E010405), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+
+REG64( PEC_1_TCPCI1_TRA0_TR0_TRACE_TRDATA_CONFIG_3             , RULL(0x0E010406), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+
+REG64( PEC_1_TCPCI1_TRA0_TR0_TRACE_TRDATA_CONFIG_4             , RULL(0x0E010407), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+
+REG64( PEC_1_TCPCI1_TRA0_TR0_TRACE_TRDATA_CONFIG_5             , RULL(0x0E010408), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+
+REG64( PEC_1_TCPCI1_TRA0_TR0_TRACE_TRDATA_CONFIG_9             , RULL(0x0E010409), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+
+REG64( PEC_2_TCPCI2_TRA0_TR0_TRACE_HI_DATA_REG                 , RULL(0x0F010400), SH_UNT_PEC_2    , SH_ACS_SCOM_RO   );
+
+REG64( PEC_2_TCPCI2_TRA0_TR0_TRACE_LO_DATA_REG                 , RULL(0x0F010401), SH_UNT_PEC_2    , SH_ACS_SCOM_RO   );
+
+REG64( PEC_2_TCPCI2_TRA0_TR0_TRACE_TRCTRL_CONFIG               , RULL(0x0F010402), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_2_TCPCI2_TRA0_TR0_TRACE_TRDATA_CONFIG_0             , RULL(0x0F010403), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_2_TCPCI2_TRA0_TR0_TRACE_TRDATA_CONFIG_1             , RULL(0x0F010404), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_2_TCPCI2_TRA0_TR0_TRACE_TRDATA_CONFIG_2             , RULL(0x0F010405), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_2_TCPCI2_TRA0_TR0_TRACE_TRDATA_CONFIG_3             , RULL(0x0F010406), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_2_TCPCI2_TRA0_TR0_TRACE_TRDATA_CONFIG_4             , RULL(0x0F010407), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_2_TCPCI2_TRA0_TR0_TRACE_TRDATA_CONFIG_5             , RULL(0x0F010408), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_2_TCPCI2_TRA0_TR0_TRACE_TRDATA_CONFIG_9             , RULL(0x0F010409), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM2_TEST_CERR                                    , RULL(0x05011341), SH_UNT_PU_NPU_SM2,
+       SH_ACS_SCOM      );
+
+REG64( CAPP_TFMR                                               , RULL(0x02010827), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_TFMR                                             , RULL(0x02010827), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_TFMR                                             , RULL(0x04010827), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( PEC_THERM_MODE_REG                                      , RULL(0x0D05000F), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_THERM_MODE_REG                                    , RULL(0x0D05000F), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_THERM_MODE_REG                                    , RULL(0x0E05000F), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_THERM_MODE_REG                                    , RULL(0x0F05000F), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_TIMEOUT_REG                                         , RULL(0x0D0F0010), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_TIMEOUT_REG                                       , RULL(0x0D0F0010), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_TIMEOUT_REG                                       , RULL(0x0E0F0010), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_TIMEOUT_REG                                       , RULL(0x0F0F0010), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_TIMESTAMP_COUNTER_READ                              , RULL(0x0D05001C), SH_UNT_PEC      , SH_ACS_SCOM_RO   );
+REG64( PEC_0_TIMESTAMP_COUNTER_READ                            , RULL(0x0D05001C), SH_UNT_PEC_0    , SH_ACS_SCOM_RO   );
+REG64( PEC_1_TIMESTAMP_COUNTER_READ                            , RULL(0x0E05001C), SH_UNT_PEC_1    , SH_ACS_SCOM_RO   );
+REG64( PEC_2_TIMESTAMP_COUNTER_READ                            , RULL(0x0F05001C), SH_UNT_PEC_2    , SH_ACS_SCOM_RO   );
+
+REG64( CAPP_TLBI_ERROR_REPORT                                  , RULL(0x0201080D), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_TLBI_ERROR_REPORT                                , RULL(0x0201080D), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_TLBI_ERROR_REPORT                                , RULL(0x0401080D), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( PU_TOD_CMD_REG                                          , RULL(0x0009002A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TOD_DATA_RCV_REG                                     , RULL(0x00090029), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_TOD_DATA_SND_REG                                     , RULL(0x00090028), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( CAPP_TOD_SYNC000                                        , RULL(0x02010826), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_TOD_SYNC000                                      , RULL(0x02010826), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_TOD_SYNC000                                      , RULL(0x04010826), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( PU_TRUST_CONTROL                                        , RULL(0x05012B45), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_TUNNEL_BAR_REG                                      , RULL(0x04010C05), SH_UNT_PEC      , SH_ACS_SCOM_RW   );
+REG64( PEC_0_TUNNEL_BAR_REG                                    , RULL(0x04010C05), SH_UNT_PEC_0    , SH_ACS_SCOM_RW   );
+REG64( PEC_1_TUNNEL_BAR_REG                                    , RULL(0x04011005), SH_UNT_PEC_1    , SH_ACS_SCOM_RW   );
+REG64( PEC_2_TUNNEL_BAR_REG                                    , RULL(0x04011405), SH_UNT_PEC_2    , SH_ACS_SCOM_RW   );
+
+REG64( PU_TX_CH_FSM_REG                                        , RULL(0x05012805), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_CH_INTADDR_REG                                    , RULL(0x05012810), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_CH_MISC_REG                                       , RULL(0x05012813), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_CTRL_STAT_REG                                     , RULL(0x05012800), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_DBFF_REG0                                         , RULL(0x05012811), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_DBFF_REG1                                         , RULL(0x05012812), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_DF_FSM_REG                                        , RULL(0x05012806), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_ERROR_REG_WCLEAR                                  , RULL(0x05012802), SH_UNT          ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PU_TX_ERROR_REG_OR                                      , RULL(0x05012804), SH_UNT          , SH_ACS_SCOM1_OR  );
+
+REG64( PU_TX_ERR_MODE                                          , RULL(0x05012807), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_MASK_REG                                          , RULL(0x05012803), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_PSI_CNTL                                          , RULL(0x04011830), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_PSI_MODE                                          , RULL(0x04011831), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_PSI_STATUS                                        , RULL(0x04011832), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_TX_TO_RT_REG                                         , RULL(0x05012801), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_UMAC_STATUS_CONTROL                                  , RULL(0x020110D5), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_BUFCTL                                           , RULL(0x0301180C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_CAMDATA0                                         , RULL(0x03011834), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_VAS_CAMDATA1                                         , RULL(0x03011835), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_VAS_CAMDISPCNTL                                      , RULL(0x03011833), SH_UNT          , SH_ACS_SCOM_WO   );
+
+REG64( PU_VAS_CQERRRPT                                         , RULL(0x03011848), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_DBGCONT                                          , RULL(0x0301182E), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_VAS_DBGNORTH                                         , RULL(0x0301182D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_DBGSOUTH                                         , RULL(0x0301184C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_DBGTRIG                                          , RULL(0x0301182F), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_VAS_EGERRRPT                                         , RULL(0x0301184A), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_ERRINJNO                                         , RULL(0x03011832), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_ERRINJSO                                         , RULL(0x0301184B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_FIR_ACTION0_REG                                  , RULL(0x03011806), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_FIR_ACTION1_REG                                  , RULL(0x03011807), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_FIR_MASK_REG                                     , RULL(0x03011803), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_VAS_FIR_MASK_REG_AND                                 , RULL(0x03011804), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_VAS_FIR_MASK_REG_OR                                  , RULL(0x03011805), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_VAS_FIR_REG                                          , RULL(0x03011800), SH_UNT          , SH_ACS_SCOM_RW   );
+REG64( PU_VAS_FIR_REG_AND                                      , RULL(0x03011801), SH_UNT          , SH_ACS_SCOM1_AND );
+REG64( PU_VAS_FIR_REG_OR                                       , RULL(0x03011802), SH_UNT          , SH_ACS_SCOM2_OR  );
+
+REG64( PU_VAS_FIR_WOF_REG                                      , RULL(0x03011808), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_VAS_INERRRPT                                         , RULL(0x0301182B), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_MISCCTL                                          , RULL(0x0301180D), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_MMIOCTL                                          , RULL(0x03011829), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_MMIODATA                                         , RULL(0x0301182A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_MMIOECC                                          , RULL(0x03011831), SH_UNT          , SH_ACS_SCOM_RO   );
+
+REG64( PU_VAS_MMIO_BASE_ADDR                                   , RULL(0x020110D4), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_PBCFG0                                           , RULL(0x0301184D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PBCFG1                                           , RULL(0x0301184E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PGMIG1                                           , RULL(0x03011841), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PGMIG2                                           , RULL(0x03011842), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PGMIG3                                           , RULL(0x03011843), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PGMIG4                                           , RULL(0x03011844), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PGMIG5                                           , RULL(0x03011845), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PGMIG6                                           , RULL(0x03011846), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PGMIG7                                           , RULL(0x03011847), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_PMCNTL                                           , RULL(0x03011830), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_RGERRRPT                                         , RULL(0x0301182C), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_RMABAR                                           , RULL(0x0301180E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_RMABARM                                          , RULL(0x0301180F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_SOUTHCTL                                         , RULL(0x0301184F), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_UWMBAR                                           , RULL(0x0301180B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WCBSBAR                                          , RULL(0x03011840), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WCERRRPT                                         , RULL(0x03011849), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_VAS_WCMBAR                                           , RULL(0x0301180A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON0BAR                                        , RULL(0x03011810), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON0CMP                                        , RULL(0x03011820), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON0WID                                        , RULL(0x03011818), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON1BAR                                        , RULL(0x03011811), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON1CMP                                        , RULL(0x03011821), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON1WID                                        , RULL(0x03011819), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON2BAR                                        , RULL(0x03011812), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON2CMP                                        , RULL(0x03011822), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON2WID                                        , RULL(0x0301181A), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON3BAR                                        , RULL(0x03011813), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON3CMP                                        , RULL(0x03011823), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON3WID                                        , RULL(0x0301181B), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON4BAR                                        , RULL(0x03011814), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON4CMP                                        , RULL(0x03011824), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON4WID                                        , RULL(0x0301181C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON5BAR                                        , RULL(0x03011815), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON5CMP                                        , RULL(0x03011825), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON5WID                                        , RULL(0x0301181D), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON6BAR                                        , RULL(0x03011816), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON6CMP                                        , RULL(0x03011826), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON6WID                                        , RULL(0x0301181E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON7BAR                                        , RULL(0x03011817), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON7CMP                                        , RULL(0x03011827), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_VAS_WRMON7WID                                        , RULL(0x0301181F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PEC_VITAL_SCAN_OUT                                      , RULL(0x0D0F0017), SH_UNT_PEC      , SH_ACS_SCOM_RO   );
+REG64( PEC_0_VITAL_SCAN_OUT                                    , RULL(0x0D0F0017), SH_UNT_PEC_0    , SH_ACS_SCOM_RO   );
+REG64( PEC_1_VITAL_SCAN_OUT                                    , RULL(0x0E0F0017), SH_UNT_PEC_1    , SH_ACS_SCOM_RO   );
+REG64( PEC_2_VITAL_SCAN_OUT                                    , RULL(0x0F0F0017), SH_UNT_PEC_2    , SH_ACS_SCOM_RO   );
+
+REG64( PU_WATCHDOG_HANG_TIMERS_CNTL                            , RULL(0x0201105C), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_WATER_MARK_REGISTER_B                                , RULL(0x000A0007), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_WATER_MARK_REGISTER_C                                , RULL(0x000A1007), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_WATER_MARK_REGISTER_D                                , RULL(0x000A2007), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_WATER_MARK_REGISTER_E                                , RULL(0x000A3007), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PHB_WOF_REG                                             , RULL(0x0D010910), SH_UNT_PHB      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_0_WOF_REG                                           , RULL(0x0D010910), SH_UNT_PHB_0    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_1_WOF_REG                                           , RULL(0x0E010910), SH_UNT_PHB_1    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_2_WOF_REG                                           , RULL(0x0E010950), SH_UNT_PHB_2    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_3_WOF_REG                                           , RULL(0x0F010910), SH_UNT_PHB_3    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_4_WOF_REG                                           , RULL(0x0F010950), SH_UNT_PHB_4    ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( PHB_5_WOF_REG                                           , RULL(0x0F010990), SH_UNT_PHB_5    ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_WRITE_PROTECT_ENABLE_REG                             , RULL(0x06010005), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_WRITE_PROTECT_ENABLE_REG                            , RULL(0x0D010005), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_WRITE_PROTECT_ENABLE_REG                          , RULL(0x0D010005), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_WRITE_PROTECT_ENABLE_REG                          , RULL(0x0E010005), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_WRITE_PROTECT_ENABLE_REG                          , RULL(0x0F010005), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_WRITE_PROTECT_ENABLE_REG                          , RULL(0x02010005), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_WRITE_PROTECT_ENABLE_REG                          , RULL(0x03010005), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_WRITE_PROTECT_ENABLE_REG                          , RULL(0x04010005), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_WRITE_PROTECT_ENABLE_REG                          , RULL(0x05010005), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PU_WRITE_PROTECT_RINGS_REG                              , RULL(0x06010006), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PEC_WRITE_PROTECT_RINGS_REG                             , RULL(0x0D010006), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_WRITE_PROTECT_RINGS_REG                           , RULL(0x0D010006), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_WRITE_PROTECT_RINGS_REG                           , RULL(0x0E010006), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_WRITE_PROTECT_RINGS_REG                           , RULL(0x0F010006), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_N0_WRITE_PROTECT_RINGS_REG                           , RULL(0x02010006), SH_UNT_PU_N0    , SH_ACS_SCOM      );
+REG64( PU_N1_WRITE_PROTECT_RINGS_REG                           , RULL(0x03010006), SH_UNT_PU_N1    , SH_ACS_SCOM      );
+REG64( PU_N2_WRITE_PROTECT_RINGS_REG                           , RULL(0x04010006), SH_UNT_PU_N2    , SH_ACS_SCOM      );
+REG64( PU_N3_WRITE_PROTECT_RINGS_REG                           , RULL(0x05010006), SH_UNT_PU_N3    , SH_ACS_SCOM      );
+
+REG64( PEC_XFIR                                                , RULL(0x0D040000), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_XFIR                                              , RULL(0x0D040000), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_XFIR                                              , RULL(0x0E040000), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_XFIR                                              , RULL(0x0F040000), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( CAPP_XPT_CONTROL                                        , RULL(0x0201081C), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_XPT_CONTROL                                      , RULL(0x0201081C), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_XPT_CONTROL                                      , RULL(0x0401081C), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_XPT_ERROR_REPORT                                   , RULL(0x0201080C), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_XPT_ERROR_REPORT                                 , RULL(0x0201080C), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_XPT_ERROR_REPORT                                 , RULL(0x0401080C), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( CAPP_XPT_PMU_EVENTS_SEL                                 , RULL(0x02010822), SH_UNT_CAPP     , SH_ACS_SCOM      );
+REG64( CAPP_0_XPT_PMU_EVENTS_SEL                               , RULL(0x02010822), SH_UNT_CAPP_0   , SH_ACS_SCOM      );
+REG64( CAPP_1_XPT_PMU_EVENTS_SEL                               , RULL(0x04010822), SH_UNT_CAPP_1   , SH_ACS_SCOM      );
+
+REG64( PU_XSCOM_BASE_REG                                       , RULL(0x00090010), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_XSCOM_DAT0_REG                                       , RULL(0x0009001E), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_XSCOM_DAT1_REG                                       , RULL(0x0009001F), SH_UNT          , SH_ACS_SCOM_RW   );
+
+REG64( PU_XSCOM_ERR_REG                                        , RULL(0x00090013), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PU_XSCOM_LOG_REG                                        , RULL(0x00090012), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_XSCOM_MODE_REG                                       , RULL(0x00090011), SH_UNT          , SH_ACS_SCOM      );
+
+REG64( PU_XSCOM_RCVED_STAT_REG                                 , RULL(0x00090018), SH_UNT          ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( PEC_XSTOP1                                              , RULL(0x0D03000C), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_XSTOP1                                            , RULL(0x0D03000C), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_XSTOP1                                            , RULL(0x0E03000C), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_XSTOP1                                            , RULL(0x0F03000C), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_XSTOP2                                              , RULL(0x0D03000D), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_XSTOP2                                            , RULL(0x0D03000D), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_XSTOP2                                            , RULL(0x0E03000D), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_XSTOP2                                            , RULL(0x0F03000D), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_XSTOP3                                              , RULL(0x0D03000E), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_XSTOP3                                            , RULL(0x0D03000E), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_XSTOP3                                            , RULL(0x0E03000E), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_XSTOP3                                            , RULL(0x0F03000E), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PEC_XSTOP_INTERRUPT_REG                                 , RULL(0x0D0F001C), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_XSTOP_INTERRUPT_REG                               , RULL(0x0D0F001C), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_XSTOP_INTERRUPT_REG                               , RULL(0x0E0F001C), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_XSTOP_INTERRUPT_REG                               , RULL(0x0F0F001C), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_NPU0_SM0_XTIMER_CONFIG                               , RULL(0x05011003), SH_UNT_PU_NPU0_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM1_XTIMER_CONFIG                               , RULL(0x05011023), SH_UNT_PU_NPU0_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM2_XTIMER_CONFIG                               , RULL(0x05011043), SH_UNT_PU_NPU0_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU0_SM3_XTIMER_CONFIG                               , RULL(0x05011063), SH_UNT_PU_NPU0_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM0_XTIMER_CONFIG                               , RULL(0x05011103), SH_UNT_PU_NPU1_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM1_XTIMER_CONFIG                               , RULL(0x05011123), SH_UNT_PU_NPU1_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM2_XTIMER_CONFIG                               , RULL(0x05011143), SH_UNT_PU_NPU1_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU1_SM3_XTIMER_CONFIG                               , RULL(0x05011163), SH_UNT_PU_NPU1_SM3,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM0_XTIMER_CONFIG                               , RULL(0x05011203), SH_UNT_PU_NPU2_SM0,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM1_XTIMER_CONFIG                               , RULL(0x05011223), SH_UNT_PU_NPU2_SM1,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM2_XTIMER_CONFIG                               , RULL(0x05011243), SH_UNT_PU_NPU2_SM2,
+       SH_ACS_SCOM      );
+REG64( PU_NPU2_SM3_XTIMER_CONFIG                               , RULL(0x05011263), SH_UNT_PU_NPU2_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_XTRA_TRACE_MODE                                      , RULL(0x020107D1), SH_UNT          ,
+       SH_ACS_SCOM      ); //DUPS: 050107D1, 030107D1, 040107D1,
+
+REG64( PEC_XTRA_TRACE_MODE                                     , RULL(0x0D0107D1), SH_UNT_PEC      , SH_ACS_SCOM      );
+REG64( PEC_0_XTRA_TRACE_MODE                                   , RULL(0x0D0107D1), SH_UNT_PEC_0    , SH_ACS_SCOM      );
+REG64( PEC_1_XTRA_TRACE_MODE                                   , RULL(0x0E0107D1), SH_UNT_PEC_1    , SH_ACS_SCOM      );
+REG64( PEC_2_XTRA_TRACE_MODE                                   , RULL(0x0F0107D1), SH_UNT_PEC_2    , SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM2_XTS_ATRMISS                                  , RULL(0x0501134A), SH_UNT_PU_NPU_SM2,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM2_XTS_ATRMISS2                                 , RULL(0x0501134C), SH_UNT_PU_NPU_SM2,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM2_XTS_ATRMISSCLR                               , RULL(0x0501134B), SH_UNT_PU_NPU_SM2,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM3_XTS_ATSD_HYP0                                , RULL(0x05011360), SH_UNT_PU_NPU_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM3_XTS_ATSD_HYP1                                , RULL(0x05011361), SH_UNT_PU_NPU_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM3_XTS_ATSD_HYP2                                , RULL(0x05011362), SH_UNT_PU_NPU_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM3_XTS_ATSD_HYP3                                , RULL(0x05011363), SH_UNT_PU_NPU_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM3_XTS_ATSD_HYP4                                , RULL(0x05011364), SH_UNT_PU_NPU_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM3_XTS_ATSD_HYP5                                , RULL(0x05011365), SH_UNT_PU_NPU_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM3_XTS_ATSD_HYP6                                , RULL(0x05011366), SH_UNT_PU_NPU_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM3_XTS_ATSD_HYP7                                , RULL(0x05011367), SH_UNT_PU_NPU_SM3,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM2_XTS_CONFIG                                   , RULL(0x05011344), SH_UNT_PU_NPU_SM2,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM2_XTS_CONFIG2                                  , RULL(0x05011345), SH_UNT_PU_NPU_SM2,
+       SH_ACS_SCOM      );
+
+REG64( PU_NPU_SM2_XTS_PMU_CNT                                  , RULL(0x05011348), SH_UNT_PU_NPU_SM2,
+       SH_ACS_SCOM      );
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9_misc_scom_addresses_fixes.H b/src/import/chips/p9/common/include/p9_misc_scom_addresses_fixes.H
new file mode 100644
index 00000000..3cf40bed
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_misc_scom_addresses_fixes.H
@@ -0,0 +1,553 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_misc_scom_addresses_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file misc_scom_addresses_fixes.H
+/// @brief The *scom_addresses.H files are  generated form figtree, but
+///        the figree can be wrong.  This file is included at the end
+///        of scom_addresses.H and allows incorrect constants to be
+///        fixed manually.
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: Infrastructure
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __P9_MISC_SCOM_ADDRESSES_FIXES_H
+#define __P9_MISC_SCOM_ADDRESSES_FIXES_H
+
+
+//Example,
+//Copy the whole line from the *scom_addresses.H file.  Then add
+//FIX in front of REG, and add another paramter that is the new
+//corrected value.
+//FIXREG64( PU_ALTD_ADDR_REG,
+//          RULL(0x05022800), SH_UNT, SH_ACS_SCOM,
+//          RULL(0x00090000)
+//        );
+
+// ADU registers
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020000) != RULL(0xC0040000)  name: PU_PBAMODE_OCI
+
+// PBA registers
+FIXREG64( PU_PBAMODE_OCI,
+          RULL(0xC0040000), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020000)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016840) != RULL(0x00014040)  name: PU_PBAMODE_SCOM
+FIXREG64( PU_PBAMODE_SCOM,
+          RULL(0x00014040), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00068000)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020008) != RULL(0xC0040008)  name: PU_PBASLVRST_OCI
+FIXREG64( PU_PBASLVRST_OCI,
+          RULL(0xC0040008), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020008)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016841) != RULL(0x00014041)  name: PU_PBASLVRST_SCOM
+FIXREG64( PU_PBASLVRST_SCOM,
+          RULL(0x00014041), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00068001)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020020) != RULL(0xC0040020)  name: PU_PBASLVCTL0_OCI
+FIXREG64( PU_PBASLVCTL0_OCI,
+          RULL(0xC0040020), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020020)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016844) != RULL(0x00014044)  name: PU_PBASLVCTL0_SCOM
+FIXREG64( PU_PBASLVCTL0_SCOM,
+          RULL(0x00014044), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068004)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020028) != RULL(0xC0040028)  name: PU_PBASLVCTL1_OCI
+FIXREG64( PU_PBASLVCTL1_OCI,
+          RULL(0xC0040028), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020028)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016845) != RULL(0x00014045)  name: PU_PBASLVCTL1_SCOM
+FIXREG64( PU_PBASLVCTL1_SCOM,
+          RULL(0x00014045), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068005)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020030) != RULL(0xC0040030)  name: PU_PBASLVCTL2_OCI
+FIXREG64( PU_PBASLVCTL2_OCI,
+          RULL(0xC0040030), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020030)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016846) != RULL(0x00014046)  name: PU_PBASLVCTL2_SCOM
+FIXREG64( PU_PBASLVCTL2_SCOM,
+          RULL(0x00014046), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068006)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020038) != RULL(0xC0040038)  name: PU_PBASLVCTL3_OCI
+FIXREG64( PU_PBASLVCTL3_OCI,
+          RULL(0xC0040038), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020038)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016847) != RULL(0x00014047)  name: PU_PBASLVCTL3_SCOM
+FIXREG64( PU_PBASLVCTL3_SCOM,
+          RULL(0x00014047), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068007)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020080) != RULL(0xC0040080)  name: PU_BCDE_CTL_OCI
+FIXREG64( PU_BCDE_CTL_OCI,
+          RULL(0xC0040080), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020080)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016850) != RULL(0x00014050)  name: PU_BCDE_CTL_SCOM
+FIXREG64( PU_BCDE_CTL_SCOM,
+          RULL(0x00014050), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00068010)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020088) != RULL(0xC0040088)  name: PU_BCDE_SET_OCI
+FIXREG64( PU_BCDE_SET_OCI,
+          RULL(0xC0040088), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020088)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016851) != RULL(0x00014051)  name: PU_BCDE_SET_SCOM
+FIXREG64( PU_BCDE_SET_SCOM,
+          RULL(0x00014051), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068011)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020090) != RULL(0xC0040090)  name: PU_BCDE_STAT_OCI
+FIXREG64( PU_BCDE_STAT_OCI,
+          RULL(0xC0040090), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020090)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016852) != RULL(0x00014052)  name: PU_BCDE_STAT_SCOM
+FIXREG64( PU_BCDE_STAT_SCOM,
+          RULL(0x00014052), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x00068012)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020098) != RULL(0xC0040098)  name: PU_BCDE_PBADR_OCI
+FIXREG64( PU_BCDE_PBADR_OCI,
+          RULL(0xC0040098), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020098)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016853) != RULL(0x00014053)  name: PU_BCDE_PBADR_SCOM
+FIXREG64( PU_BCDE_PBADR_SCOM,
+          RULL(0x00014053), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068013)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x400200A0) != RULL(0xC00400A0)  name: PU_BCDE_OCIBAR_OCI
+FIXREG64( PU_BCDE_OCIBAR_OCI,
+          RULL(0xC00400A0), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200A0)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016854) != RULL(0x00014054)  name: PU_BCDE_OCIBAR_SCOM
+FIXREG64( PU_BCDE_OCIBAR_SCOM,
+          RULL(0x00014054), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068014)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x400200A8) != RULL(0xC00400A8)  name: PU_BCUE_CTL_OCI
+FIXREG64( PU_BCUE_CTL_OCI,
+          RULL(0xC00400A8), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200A8)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016855) != RULL(0x00014055)  name: PU_BCUE_CTL_SCOM
+FIXREG64( PU_BCUE_CTL_SCOM,
+          RULL(0x00014055), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00068015)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x400200B0) != RULL(0xC00400B0)  name: PU_BCUE_SET_OCI
+FIXREG64( PU_BCUE_SET_OCI,
+          RULL(0xC00400B0), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200B0)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016856) != RULL(0x00014056)  name: PU_BCUE_SET_SCOM
+FIXREG64( PU_BCUE_SET_SCOM,
+          RULL(0x00014056), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068016)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x400200B8) != RULL(0xC00400B8)  name: PU_BCUE_STAT_OCI
+FIXREG64( PU_BCUE_STAT_OCI,
+          RULL(0xC00400B8), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200B8)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016857) != RULL(0x00014057)  name: PU_BCUE_STAT_SCOM
+FIXREG64( PU_BCUE_STAT_SCOM,
+          RULL(0x00014057), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x00068017)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x400200C0) != RULL(0xC00400C0)  name: PU_BCUE_PBADR_OCI
+FIXREG64( PU_BCUE_PBADR_OCI,
+          RULL(0xC00400C0), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200C0)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016858) != RULL(0x00014058)  name: PU_BCUE_PBADR_SCOM
+FIXREG64( PU_BCUE_PBADR_SCOM,
+          RULL(0x00014058), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068018)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x400200C8) != RULL(0xC00400C8)  name: PU_BCUE_OCIBAR_OCI
+FIXREG64( PU_BCUE_OCIBAR_OCI,
+          RULL(0xC00400C8), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200C8)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016859) != RULL(0x00014059)  name: PU_BCUE_OCIBAR_SCOM
+FIXREG64( PU_BCUE_OCIBAR_SCOM,
+          RULL(0x00014059), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068019)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x400200D0) != RULL(0xC00400D0)  name: PU_PBAPBOCR0_OCI
+FIXREG64( PU_PBAPBOCR0_OCI,
+          RULL(0xC00400D0), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200D0)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x0501685A) != RULL(0x0001405A)  name: PU_PBAPBOCR0_SCOM
+FIXREG64( PU_PBAPBOCR0_SCOM,
+          RULL(0x0001405A), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x0006801A)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x400200D8) != RULL(0xC00400D8)  name: PU_PBAPBOCR1_OCI
+FIXREG64( PU_PBAPBOCR1_OCI,
+          RULL(0xC00400D8), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200D8)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x0501685B) != RULL(0x0001405B)  name: PU_PBAPBOCR1_SCOM
+FIXREG64( PU_PBAPBOCR1_SCOM,
+          RULL(0x0001405B), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x0006801B)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x400200E0) != RULL(0xC00400E0)  name: PU_PBAPBOCR2_OCI
+FIXREG64( PU_PBAPBOCR2_OCI,
+          RULL(0xC00400E0), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200E0)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x0501685C) != RULL(0x0001405C)  name: PU_PBAPBOCR2_SCOM
+FIXREG64( PU_PBAPBOCR2_SCOM,
+          RULL(0x0001405C), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x0006801C)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x400200E8) != RULL(0xC00400E8)  name: PU_PBAPBOCR3_OCI
+FIXREG64( PU_PBAPBOCR3_OCI,
+          RULL(0xC00400E8), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200E8)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x0501685D) != RULL(0x0001405D)  name: PU_PBAPBOCR3_SCOM
+FIXREG64( PU_PBAPBOCR3_SCOM,
+          RULL(0x0001405D), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x0006801D)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x400200F0) != RULL(0xC00400F0)  name: PU_PBAPBOCR4_OCI
+FIXREG64( PU_PBAPBOCR4_OCI,
+          RULL(0xC00400F0), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200F0)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x0501685E) != RULL(0x0001405E)  name: PU_PBAPBOCR4_SCOM
+FIXREG64( PU_PBAPBOCR4_SCOM,
+          RULL(0x0001405E), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x0006801E)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x400200F8) != RULL(0xC00400F8)  name: PU_PBAPBOCR5_OCI
+FIXREG64( PU_PBAPBOCR5_OCI,
+          RULL(0xC00400F8), SH_UNT, SH_ACS_OCI,
+          RULL(0xC00200F8)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x0501685F) != RULL(0x0001405F)  name: PU_PBAPBOCR5_SCOM
+FIXREG64( PU_PBAPBOCR5_SCOM,
+          RULL(0x0001405F), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x0006801F)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020100) != RULL(0xC0040100)  name: PU_PBAXSNDTX_OCI
+FIXREG64( PU_PBAXSNDTX_OCI,
+          RULL(0xC0040100), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020100)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016860) != RULL(0x00014060)  name: PU_PBAXSNDTX_SCOM
+FIXREG64( PU_PBAXSNDTX_SCOM,
+          RULL(0x00014060), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068020)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020108) != RULL(0xC0040108)  name: PU_PBAXCFG_OCI
+FIXREG64( PU_PBAXCFG_OCI,
+          RULL(0xC0040108), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020108)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016861) != RULL(0x00014061)  name: PU_PBAXCFG_SCOM
+FIXREG64( PU_PBAXCFG_SCOM,
+          RULL(0x00014061), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00068021)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020110) != RULL(0xC0040110)  name: PU_PBAXSNDSTAT_OCI
+FIXREG64( PU_PBAXSNDSTAT_OCI,
+          RULL(0xC0040110), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020110)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016862) != RULL(0x00014062)  name: PU_PBAXSNDSTAT_SCOM
+FIXREG64( PU_PBAXSNDSTAT_SCOM,
+          RULL(0x00014062), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x00068022)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020120) != RULL(0xC0040120)  name: PU_PBAXRCVSTAT_OCI
+FIXREG64( PU_PBAXRCVSTAT_OCI,
+          RULL(0xC0040120), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020120)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016864) != RULL(0x00014064)  name: PU_PBAXRCVSTAT_SCOM
+FIXREG64( PU_PBAXRCVSTAT_SCOM,
+          RULL(0x00014064), SH_UNT, SH_ACS_SCOM_RO,
+          RULL(0x00068024)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020130) != RULL(0xC0040130)  name: PU_PBAXSHBR0_OCI
+FIXREG64( PU_PBAXSHBR0_OCI,
+          RULL(0xC0040130), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020130)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016866) != RULL(0x00014066)  name: PU_PBAXSHBR0_SCOM
+FIXREG64( PU_PBAXSHBR0_SCOM,
+          RULL(0x00014066), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x00068026)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020138) != RULL(0xC0040138)  name: PU_PBAXSHCS0_OCI
+FIXREG64( PU_PBAXSHCS0_OCI,
+          RULL(0xC0040138), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020138)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x05016867) != RULL(0x00014067)  name: PU_PBAXSHCS0_SCOM
+FIXREG64( PU_PBAXSHCS0_SCOM,
+          RULL(0x00014067), SH_UNT, SH_ACS_SCOM,
+          RULL(0x00068027)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020150) != RULL(0xC0040150)  name: PU_PBAXSHBR1_OCI
+FIXREG64( PU_PBAXSHBR1_OCI,
+          RULL(0xC0040150), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020150)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x0501686A) != RULL(0x0001406A)  name: PU_PBAXSHBR1_SCOM
+FIXREG64( PU_PBAXSHBR1_SCOM,
+          RULL(0x0001406A), SH_UNT, SH_ACS_SCOM_RW,
+          RULL(0x0006802A)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x40020158) != RULL(0xC0040158)  name: PU_PBAXSHCS1_OCI
+FIXREG64( PU_PBAXSHCS1_OCI,
+          RULL(0xC0040158), SH_UNT, SH_ACS_OCI,
+          RULL(0xC0020158)
+        );
+//WARNING AUTO CORRECT: val mismatch: RULL(0x0501686B) != RULL(0x0001406B)  name: PU_PBAXSHCS1_SCOM
+FIXREG64( PU_PBAXSHCS1_SCOM,
+          RULL(0x0001406B), SH_UNT, SH_ACS_SCOM,
+          RULL(0x0006802B)
+        );
+
+
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_BCDE_SET_SCOM, RULL(0x00068011), SH_UNT, SH_ACS_SCOM_RW);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBAPBOCR4_SCOM, RULL(0x0006801E), SH_UNT, SH_ACS_SCOM_RO);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBAPBOCR2_SCOM, RULL(0x0006801C), SH_UNT, SH_ACS_SCOM_RO);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBAXSHCS0_SCOM, RULL(0x00068027), SH_UNT, SH_ACS_SCOM);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBAPBOCR3_SCOM, RULL(0x0006801D), SH_UNT, SH_ACS_SCOM_RO);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_BCUE_STAT_SCOM, RULL(0x00068017), SH_UNT, SH_ACS_SCOM_RO);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_BCUE_OCIBAR_SCOM, RULL(0x00068019), SH_UNT, SH_ACS_SCOM_RW);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBAXSNDTX_SCOM, RULL(0x00068020), SH_UNT, SH_ACS_SCOM_RW);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_BCDE_CTL_SCOM, RULL(0x00068010), SH_UNT, SH_ACS_SCOM);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBASLVCTL0_SCOM, RULL(0x00068004), SH_UNT, SH_ACS_SCOM_RW);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBAPBOCR1_SCOM, RULL(0x0006801B), SH_UNT, SH_ACS_SCOM_RO);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBAXSHBR1_SCOM, RULL(0x0006802A), SH_UNT, SH_ACS_SCOM_RW);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBASLVCTL2_SCOM, RULL(0x00068006), SH_UNT, SH_ACS_SCOM_RW);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBASLVCTL1_SCOM, RULL(0x00068005), SH_UNT, SH_ACS_SCOM_RW);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_BCUE_SET_SCOM, RULL(0x00068016), SH_UNT, SH_ACS_SCOM_RW);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBAPBOCR0_SCOM, RULL(0x0006801A), SH_UNT, SH_ACS_SCOM_RO);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBAMODE_SCOM, RULL(0x00068000), SH_UNT, SH_ACS_SCOM);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBAXSHBR0_SCOM, RULL(0x00068026), SH_UNT, SH_ACS_SCOM_RW);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBASLVCTL3_SCOM, RULL(0x00068007), SH_UNT, SH_ACS_SCOM_RW);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_BCUE_PBADR_SCOM, RULL(0x00068018), SH_UNT, SH_ACS_SCOM_RW);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBAPBOCR5_SCOM, RULL(0x0006801F), SH_UNT, SH_ACS_SCOM_RO);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBAXSHCS1_SCOM, RULL(0x0006802B), SH_UNT, SH_ACS_SCOM);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBAXRCVSTAT_SCOM, RULL(0x00068024), SH_UNT, SH_ACS_SCOM_RO);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_BCUE_CTL_SCOM, RULL(0x00068015), SH_UNT, SH_ACS_SCOM);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBASLVRST_SCOM, RULL(0x00068001), SH_UNT, SH_ACS_SCOM);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_BCDE_PBADR_SCOM, RULL(0x00068013), SH_UNT, SH_ACS_SCOM_RW);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBAXSNDSTAT_SCOM, RULL(0x00068022), SH_UNT, SH_ACS_SCOM_RO);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_BCDE_OCIBAR_SCOM, RULL(0x00068014), SH_UNT, SH_ACS_SCOM_RW);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_BCDE_STAT_SCOM, RULL(0x00068012), SH_UNT, SH_ACS_SCOM_RO);
+//WARNING: This register is not defined anymore in the figtree.
+REG64( PU_PBAXCFG_SCOM, RULL(0x00068021), SH_UNT, SH_ACS_SCOM);
+
+REG64( PEC_PCS_RX_CONFIG_MODE_REG                              , RULL(0x800004800D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_RX_CONFIG_MODE_REG                            , RULL(0x800004800D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_RX_CONFIG_MODE_REG                            , RULL(0x800004800E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_RX_CONFIG_MODE_REG                            , RULL(0x800004800F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_RX_ROT_CNTL_REG                                 , RULL(0x800004820D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_RX_ROT_CNTL_REG                               , RULL(0x800004820D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_RX_ROT_CNTL_REG                               , RULL(0x800004820E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_RX_ROT_CNTL_REG                               , RULL(0x800004820F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_RX_CDR_GAIN_REG                                 , RULL(0x800004B30D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_RX_CDR_GAIN_REG                               , RULL(0x800004B30D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_RX_CDR_GAIN_REG                               , RULL(0x800004B30E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_RX_CDR_GAIN_REG                               , RULL(0x800004B30F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_RX_LOFF_CONTROL_REG                             , RULL(0x800004A60D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_RX_LOFF_CONTROL_REG                           , RULL(0x800004A60D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_RX_LOFF_CONTROL_REG                           , RULL(0x800004A60E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_RX_LOFF_CONTROL_REG                           , RULL(0x800004A60F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_RX_SIGDET_CONTROL_REG                           , RULL(0x800004A70D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_RX_SIGDET_CONTROL_REG                         , RULL(0x800004A70D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_RX_SIGDET_CONTROL_REG                         , RULL(0x800004A70E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_RX_SIGDET_CONTROL_REG                         , RULL(0x800004A70F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_RX_VGA_CONTROL1_REG                             , RULL(0x8000048B0D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_RX_VGA_CONTROL1_REG                           , RULL(0x8000048B0D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_RX_VGA_CONTROL1_REG                           , RULL(0x8000048B0E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_RX_VGA_CONTROL1_REG                           , RULL(0x8000048B0F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_RX_VGA_CONTROL2_REG                             , RULL(0x8000048C0D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_RX_VGA_CONTROL2_REG                           , RULL(0x8000048C0D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_RX_VGA_CONTROL2_REG                           , RULL(0x8000048C0E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_RX_VGA_CONTROL2_REG                           , RULL(0x8000048C0F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_RX_VGA_CONTROL3_REG                             , RULL(0x8000048D0D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_RX_VGA_CONTROL3_REG                           , RULL(0x8000048D0D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_RX_VGA_CONTROL3_REG                           , RULL(0x8000048D0E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_RX_VGA_CONTROL3_REG                           , RULL(0x8000048D0F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_TX_DCLCK_ROTATOR_REG                            , RULL(0x800004450D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_TX_DCLCK_ROTATOR_REG                          , RULL(0x800004450D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_TX_DCLCK_ROTATOR_REG                          , RULL(0x800004450E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_TX_DCLCK_ROTATOR_REG                          , RULL(0x800004450F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_TX_FIFO_CONFIG_OFFSET_REG                       , RULL(0x8000044F0D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_TX_FIFO_CONFIG_OFFSET_REG                     , RULL(0x8000044F0D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_TX_FIFO_CONFIG_OFFSET_REG                     , RULL(0x8000044F0E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_TX_FIFO_CONFIG_OFFSET_REG                     , RULL(0x8000044F0F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_TX_PCIE_REC_DETECT_CNTL1_REG                    , RULL(0x8000046C0D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_TX_PCIE_REC_DETECT_CNTL1_REG                  , RULL(0x8000046C0D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_TX_PCIE_REC_DETECT_CNTL1_REG                  , RULL(0x8000046C0E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_TX_PCIE_REC_DETECT_CNTL1_REG                  , RULL(0x8000046C0F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_TX_PCIE_REC_DETECT_CNTL2_REG                    , RULL(0x8000046D0D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_TX_PCIE_REC_DETECT_CNTL2_REG                  , RULL(0x8000046D0D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_TX_PCIE_REC_DETECT_CNTL2_REG                  , RULL(0x8000046D0E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_TX_PCIE_REC_DETECT_CNTL2_REG                  , RULL(0x8000046D0F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_TX_POWER_SEQ_ENABLE_REG                         , RULL(0x800004700D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_TX_POWER_SEQ_ENABLE_REG                       , RULL(0x800004700D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_TX_POWER_SEQ_ENABLE_REG                       , RULL(0x800004700E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_TX_POWER_SEQ_ENABLE_REG                       , RULL(0x800004700F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_PCLCK_CNTL_PLLA_REG                             , RULL(0x8000050F0D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_PCLCK_CNTL_PLLA_REG                           , RULL(0x8000050F0D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_PCLCK_CNTL_PLLA_REG                           , RULL(0x8000050F0E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_PCLCK_CNTL_PLLA_REG                           , RULL(0x8000050F0F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+REG64( PEC_PCS_PCLCK_CNTL_PLLB_REG                             , RULL(0x8000054F0D010C3F), SH_UNT_PEC      ,
+       SH_ACS_SCOM      );
+REG64( PEC_0_PCS_PCLCK_CNTL_PLLB_REG                           , RULL(0x8000054F0D010C3F), SH_UNT_PEC_0    ,
+       SH_ACS_SCOM      );
+REG64( PEC_1_PCS_PCLCK_CNTL_PLLB_REG                           , RULL(0x8000054F0E010C3F), SH_UNT_PEC_1    ,
+       SH_ACS_SCOM      );
+REG64( PEC_2_PCS_PCLCK_CNTL_PLLB_REG                           , RULL(0x8000054F0F010C3F), SH_UNT_PEC_2    ,
+       SH_ACS_SCOM      );
+
+
+#endif
diff --git a/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H
new file mode 100644
index 00000000..cf048f33
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H
@@ -0,0 +1,78134 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_misc_scom_addresses_fld.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_misc_scom_addresses_fld.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#include <p9_const_common.H>
+
+#ifndef __P9_MISC_SCOM_ADDRESSES_FLD_H
+#define __P9_MISC_SCOM_ADDRESSES_FLD_H
+
+
+#include <p9_scom_template_consts.H>
+#include <p9_misc_scom_addresses_fld_fixes.H>
+
+REG64_FLD( PU_ADDR_0_HASH_FUNCTION_REG_ADDRESS                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_0_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_10_HASH_FUNCTION_REG_ADDRESS                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_10_HASH_FUNCTION_REG_ADDRESS_LEN                , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_1_HASH_FUNCTION_REG_ADDRESS                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_1_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_2_HASH_FUNCTION_REG_ADDRESS                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_2_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_3_HASH_FUNCTION_REG_ADDRESS                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_3_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_4_HASH_FUNCTION_REG_ADDRESS                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_4_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_5_HASH_FUNCTION_REG_ADDRESS                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_5_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_6_HASH_FUNCTION_REG_ADDRESS                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_6_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_7_HASH_FUNCTION_REG_ADDRESS                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_7_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_8_HASH_FUNCTION_REG_ADDRESS                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_8_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_ADDR_9_HASH_FUNCTION_REG_ADDRESS                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_ADDR_9_HASH_FUNCTION_REG_ADDRESS_LEN                 , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_N3_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( PU_N3_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16  , SH_UNT_PU_N3    ,
+           SH_ACS_SCOM     , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN );
+REG64_FLD( PU_N3_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16  , SH_UNT_PU_N3    ,
+           SH_ACS_SCOM     , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( PU_N3_ADDR_TRAP_REG_RESERVED_LAST_LT                    , 17  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LAST_LT );
+REG64_FLD( PU_N3_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18  , SH_UNT_PU_N3    ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR );
+REG64_FLD( PU_N3_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13  , SH_UNT_PU_N3    ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN );
+REG64_FLD( PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY );
+REG64_FLD( PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR );
+REG64_FLD( PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION );
+REG64_FLD( PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER );
+
+REG64_FLD( PU_N1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( PU_N1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16  , SH_UNT_PU_N1    ,
+           SH_ACS_SCOM     , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN );
+REG64_FLD( PU_N1_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16  , SH_UNT_PU_N1    ,
+           SH_ACS_SCOM     , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( PU_N1_ADDR_TRAP_REG_RESERVED_LAST_LT                    , 17  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LAST_LT );
+REG64_FLD( PU_N1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18  , SH_UNT_PU_N1    ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR );
+REG64_FLD( PU_N1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13  , SH_UNT_PU_N1    ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN );
+REG64_FLD( PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY );
+REG64_FLD( PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR );
+REG64_FLD( PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION );
+REG64_FLD( PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER );
+
+REG64_FLD( PU_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( PU_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN );
+REG64_FLD( PU_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( PU_ADDR_TRAP_REG_RESERVED_LAST_LT                       , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LAST_LT );
+REG64_FLD( PU_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR );
+REG64_FLD( PU_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13  , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN );
+REG64_FLD( PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY );
+REG64_FLD( PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR );
+REG64_FLD( PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION );
+REG64_FLD( PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER );
+
+REG64_FLD( PU_N2_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( PU_N2_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16  , SH_UNT_PU_N2    ,
+           SH_ACS_SCOM     , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN );
+REG64_FLD( PU_N2_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16  , SH_UNT_PU_N2    ,
+           SH_ACS_SCOM     , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( PU_N2_ADDR_TRAP_REG_RESERVED_LAST_LT                    , 17  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LAST_LT );
+REG64_FLD( PU_N2_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18  , SH_UNT_PU_N2    ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR );
+REG64_FLD( PU_N2_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13  , SH_UNT_PU_N2    ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN );
+REG64_FLD( PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY );
+REG64_FLD( PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR );
+REG64_FLD( PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION );
+REG64_FLD( PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER );
+
+REG64_FLD( PEC_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( PEC_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN );
+REG64_FLD( PEC_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16  , SH_UNT_PEC      ,
+           SH_ACS_SCOM     , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( PEC_ADDR_TRAP_REG_RESERVED_LAST_LT                      , 17  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LAST_LT );
+REG64_FLD( PEC_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR );
+REG64_FLD( PEC_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13  , SH_UNT_PEC      ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN );
+REG64_FLD( PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY );
+REG64_FLD( PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR );
+REG64_FLD( PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION );
+REG64_FLD( PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER );
+
+REG64_FLD( PU_N0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( PU_N0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16  , SH_UNT_PU_N0    ,
+           SH_ACS_SCOM     , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN );
+REG64_FLD( PU_N0_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16  , SH_UNT_PU_N0    ,
+           SH_ACS_SCOM     , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( PU_N0_ADDR_TRAP_REG_RESERVED_LAST_LT                    , 17  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LAST_LT );
+REG64_FLD( PU_N0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18  , SH_UNT_PU_N0    ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR );
+REG64_FLD( PU_N0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13  , SH_UNT_PU_N0    ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN );
+REG64_FLD( PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY );
+REG64_FLD( PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR );
+REG64_FLD( PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION );
+REG64_FLD( PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER );
+
+REG64_FLD( PU_ADS_XSCOM_CMD_REG_RNW                                , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RNW        );
+REG64_FLD( PU_ADS_XSCOM_CMD_REG_SIZE                               , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SIZE       );
+REG64_FLD( PU_ADS_XSCOM_CMD_REG_SIZE_LEN                           , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SIZE_LEN   );
+REG64_FLD( PU_ADS_XSCOM_CMD_REG_ADR                                , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADR        );
+REG64_FLD( PU_ADS_XSCOM_CMD_REG_ADR_LEN                            , 34  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADR_LEN    );
+
+REG64_FLD( PU_ADU_HANG_DIV_REG_DATA                                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_ADU_HANG_DIV_REG_DATA_LEN                            , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_ADU_HANG_DIV_REG_OPER                                , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OPER       );
+REG64_FLD( PU_ADU_HANG_DIV_REG_OPER_LEN                            , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OPER_LEN   );
+
+REG64_FLD( PU_ALTD_ADDR_REG_FBC_ADDRESS                            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_ADDRESS );
+REG64_FLD( PU_ALTD_ADDR_REG_FBC_ADDRESS_LEN                        , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_ADDRESS_LEN );
+
+REG64_FLD( PU_ALTD_CMD_REG_FBC_START_OP                            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_START_OP );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_CLEAR_STATUS                        , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_CLEAR_STATUS );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_RESET_FSM                           , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_RESET_FSM );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_RNW                                 , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_RNW    );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_AXTYPE                              , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_AXTYPE );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_DATA_ONLY                           , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_DATA_ONLY );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCKED                              , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_LOCKED );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCK_ID                             , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_LOCK_ID );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCK_ID_LEN                         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_LOCK_ID_LEN );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_SCOPE                               , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_SCOPE  );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_SCOPE_LEN                           , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_SCOPE_LEN );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_AUTO_INC                            , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_AUTO_INC );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_DROP_PRIORITY                       , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_DROP_PRIORITY );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_DROP_PRIORITY_MAX                   , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_DROP_PRIORITY_MAX );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_OVERWRITE_PBINIT                    , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_OVERWRITE_PBINIT );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_PIB_DIRECT                          , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_PIB_DIRECT );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE                     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_WITH_TM_QUIESCE );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_TTYPE                               , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_TTYPE  );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_TTYPE_LEN                           , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_TTYPE_LEN );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_TSIZE                               , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_TSIZE  );
+REG64_FLD( PU_ALTD_CMD_REG_FBC_TSIZE_LEN                           , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_TSIZE_LEN );
+
+REG64_FLD( PU_ALTD_DATA_REG_FBC                                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FBC        );
+REG64_FLD( PU_ALTD_DATA_REG_FBC_LEN                                , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FBC_LEN    );
+
+REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PRE_QUIESCE                 , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_WITH_PRE_QUIESCE );
+REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PBINIT_LOW_WAIT             , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_WITH_PBINIT_LOW_WAIT );
+REG64_FLD( PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT         , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT );
+REG64_FLD( PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN     , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN );
+REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_POST_INIT                   , 51  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_WITH_POST_INIT );
+REG64_FLD( PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT           , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT );
+REG64_FLD( PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT_LEN       , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT_LEN );
+
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_WAIT_CMD_ARBIT                   , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_WAIT_CMD_ARBIT );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_ADDR_DONE                        , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_ADDR_DONE );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_DATA_DONE                        , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_DATA_DONE );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_WAIT_RESP                        , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_WAIT_RESP );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_OVERRUN_ERROR                    , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_OVERRUN_ERROR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_AUTOINC_ERROR                    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_AUTOINC_ERROR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_COMMAND_ERROR                    , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_COMMAND_ERROR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_ADDRESS_ERROR                    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_ADDRESS_ERROR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_OP_HANG_ERR                   , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_PB_OP_HANG_ERR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_DATA_HANG_ERR                 , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_PB_DATA_HANG_ERR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_UNEXPECT_CRESP_ERR            , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_PB_UNEXPECT_CRESP_ERR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_UNEXPECT_DATA_ERR             , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_PB_UNEXPECT_DATA_ERR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_WAIT_PIB_DIRECT                  , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_WAIT_PIB_DIRECT );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PIB_DIRECT_DONE                  , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_PIB_DIRECT_DONE );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PBINIT_MISSING                   , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_PBINIT_MISSING );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PIB_ERROR                        , 33  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_PIB_ERROR );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_PIB_ERROR_LEN                    , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_PIB_ERROR_LEN );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_ECC_CE                           , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_ECC_CE );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_ECC_UE                           , 49  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_ECC_UE );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_ECC_SUE                          , 50  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_ECC_SUE );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_CRESP_VALUE                      , 59  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_CRESP_VALUE );
+REG64_FLD( PU_ALTD_STATUS_REG_FBC_CRESP_VALUE_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_CRESP_VALUE_LEN );
+
+REG64_FLD( CAPP_APCFG_APCCTL_PHB_SEL                               , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_PHB_SEL );
+REG64_FLD( CAPP_APCFG_APCCTL_PHB_SEL_LEN                           , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_PHB_SEL_LEN );
+REG64_FLD( CAPP_APCFG_HANG_POLL_SCALE                              , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_HANG_POLL_SCALE );
+REG64_FLD( CAPP_APCFG_HANG_POLL_SCALE_LEN                          , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_HANG_POLL_SCALE_LEN );
+REG64_FLD( CAPP_APCFG_SPEC_HPC_DIR_STATE                           , 8   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SPEC_HPC_DIR_STATE );
+REG64_FLD( CAPP_APCFG_SPEC_HPC_DIR_STATE_LEN                       , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SPEC_HPC_DIR_STATE_LEN );
+REG64_FLD( CAPP_APCFG_APCCTL_P9_MODE                               , 14  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_P9_MODE );
+REG64_FLD( CAPP_APCFG_APCCTL_SYSADDR                               , 15  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_SYSADDR );
+REG64_FLD( CAPP_APCFG_APCCTL_SYSADDR_LEN                           , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_SYSADDR_LEN );
+REG64_FLD( CAPP_APCFG_APCCTL_MEM_SEL_MODE                          , 21  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_MEM_SEL_MODE );
+REG64_FLD( CAPP_APCFG_APCCTL_ENB_FRC_ADDR13                        , 22  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_ENB_FRC_ADDR13 );
+
+REG64_FLD( CAPP_APCLCO_TARGET_VALID                                , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TARGET_VALID );
+REG64_FLD( CAPP_APCLCO_TARGET_VALID_LEN                            , 12  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TARGET_VALID_LEN );
+REG64_FLD( CAPP_APCLCO_TARGET_ID0                                  , 12  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TARGET_ID0 );
+REG64_FLD( CAPP_APCLCO_TARGET_MIN                                  , 13  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TARGET_MIN );
+REG64_FLD( CAPP_APCLCO_TARGET_MIN_LEN                              , 3   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TARGET_MIN_LEN );
+
+REG64_FLD( CAPP_APCRDFSMMASK_APC_RDFSM_MASK                        , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APC_RDFSM_MASK );
+REG64_FLD( CAPP_APCRDFSMMASK_APC_RDFSM_MASK_LEN                    , 48  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APC_RDFSM_MASK_LEN );
+
+REG64_FLD( CAPP_APCTL_APCCTL_ENB_CRESP_EXAM                        , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_ENB_CRESP_EXAM );
+REG64_FLD( CAPP_APCTL_APCCTL_ADR_BAR_MODE                          , 1   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_ADR_BAR_MODE );
+REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_NN_RN                         , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_DISABLE_NN_RN );
+REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_VG_NOT_SYS                    , 3   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_DISABLE_VG_NOT_SYS );
+REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_G                             , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_DISABLE_G );
+REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_LN                            , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_DISABLE_LN );
+REG64_FLD( CAPP_APCTL_APCCTL_SKIP_G                                , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_SKIP_G );
+REG64_FLD( CAPP_APCTL_APCCTL_HANG_ARE                              , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_HANG_ARE );
+REG64_FLD( CAPP_APCTL_APCCTL_HANG_DEAD                             , 8   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_HANG_DEAD );
+REG64_FLD( CAPP_APCTL_APCCTL_CFG_BKILL_INC                         , 9   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_CFG_BKILL_INC );
+REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_PSL_CMDQUEUE                  , 12  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_DISABLE_PSL_CMDQUEUE );
+REG64_FLD( CAPP_APCTL_APCCTL_ENABLE_MASTER_RETRY_BACKOFF           , 13  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_ENABLE_MASTER_RETRY_BACKOFF );
+REG64_FLD( CAPP_APCTL_SCPTGT_LFSR_MODE                             , 14  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SCPTGT_LFSR_MODE );
+REG64_FLD( CAPP_APCTL_SCPTGT_LFSR_MODE_LEN                         , 3   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SCPTGT_LFSR_MODE_LEN );
+REG64_FLD( CAPP_APCTL_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT            , 17  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT );
+REG64_FLD( CAPP_APCTL_WR_EPSILON_VALUE                             , 39  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_WR_EPSILON_VALUE );
+REG64_FLD( CAPP_APCTL_WR_EPSILON_VALUE_LEN                         , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_WR_EPSILON_VALUE_LEN );
+REG64_FLD( CAPP_APCTL_APCCTL_MAX_RETRY                             , 56  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_MAX_RETRY );
+REG64_FLD( CAPP_APCTL_APCCTL_MAX_RETRY_LEN                         , 8   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCCTL_MAX_RETRY_LEN );
+
+REG64_FLD( CAPP_APC_ARRY_ADDR_APCARY_ADDRESS                       , 3   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCARY_ADDRESS );
+REG64_FLD( CAPP_APC_ARRY_ADDR_APCARY_ADDRESS_LEN                   , 9   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCARY_ADDRESS_LEN );
+
+REG64_FLD( CAPP_APC_ARRY_RDDATA_APCARY                             , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCARY     );
+REG64_FLD( CAPP_APC_ARRY_RDDATA_APCARY_LEN                         , 64  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCARY_LEN );
+
+REG64_FLD( CAPP_APC_ARRY_WRDATA_APCARY                             , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCARY     );
+REG64_FLD( CAPP_APC_ARRY_WRDATA_APCARY_LEN                         , 64  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APCARY_LEN );
+
+REG64_FLD( CAPP_APC_ERRINJ_ENABLE                                  , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( CAPP_APC_ERRINJ_DBLERR                                  , 1   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_DBLERR     );
+REG64_FLD( CAPP_APC_ERRINJ_CONTINUOUS                              , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CONTINUOUS );
+REG64_FLD( CAPP_APC_ERRINJ_TARGET                                  , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TARGET     );
+REG64_FLD( CAPP_APC_ERRINJ_TARGET_LEN                              , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TARGET_LEN );
+REG64_FLD( CAPP_APC_ERRINJ_SNP_ERROR_INJECT_ENABLE                 , 12  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SNP_ERROR_INJECT_ENABLE );
+REG64_FLD( CAPP_APC_ERRINJ_SNP_INJECT_DBL_ECC_ERROR                , 13  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SNP_INJECT_DBL_ECC_ERROR );
+REG64_FLD( CAPP_APC_ERRINJ_SNP_INJECT_CONTINOUS_ERROR              , 14  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SNP_INJECT_CONTINOUS_ERROR );
+REG64_FLD( CAPP_APC_ERRINJ_SNP_ERROR_INJECT_TARGET                 , 17  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SNP_ERROR_INJECT_TARGET );
+REG64_FLD( CAPP_APC_ERRINJ_SNP_ERROR_INJECT_TARGET_LEN             , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SNP_ERROR_INJECT_TARGET_LEN );
+REG64_FLD( CAPP_APC_ERRINJ_XPT_ERROR_INJECT_ENABLE                 , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_XPT_ERROR_INJECT_ENABLE );
+REG64_FLD( CAPP_APC_ERRINJ_XPT_ERROR_TYPE                          , 33  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_XPT_ERROR_TYPE );
+REG64_FLD( CAPP_APC_ERRINJ_XPT_ERROR_TYPE_LEN                      , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_XPT_ERROR_TYPE_LEN );
+REG64_FLD( CAPP_APC_ERRINJ_XPT_INJECT_CONTINUOUS_ERROR             , 35  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_XPT_INJECT_CONTINUOUS_ERROR );
+REG64_FLD( CAPP_APC_ERRINJ_XPT_ERROR_INJECT_TARGET                 , 36  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_XPT_ERROR_INJECT_TARGET );
+REG64_FLD( CAPP_APC_ERRINJ_XPT_ERROR_INJECT_TARGET_LEN             , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_XPT_ERROR_INJECT_TARGET_LEN );
+
+REG64_FLD( CAPP_APC_PMUSEL_GRPSEL                                  , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_GRPSEL     );
+REG64_FLD( CAPP_APC_PMUSEL_GRPSEL_LEN                              , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_GRPSEL_LEN );
+REG64_FLD( CAPP_APC_PMUSEL_FSMJ_EVENT_SEL                          , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_FSMJ_EVENT_SEL );
+REG64_FLD( CAPP_APC_PMUSEL_FSMJ_EVENT_SEL_LEN                      , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_FSMJ_EVENT_SEL_LEN );
+REG64_FLD( CAPP_APC_PMUSEL_FSMJ_FSM_SEL                            , 13  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_FSMJ_FSM_SEL );
+REG64_FLD( CAPP_APC_PMUSEL_FSMJ_FSM_SEL_LEN                        , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_FSMJ_FSM_SEL_LEN );
+
+REG64_FLD( CAPP_ASE_TUPLE0_LPID                                    , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_LPID       );
+REG64_FLD( CAPP_ASE_TUPLE0_LPID_LEN                                , 12  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_LPID_LEN   );
+REG64_FLD( CAPP_ASE_TUPLE0_PID                                     , 20  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PID        );
+REG64_FLD( CAPP_ASE_TUPLE0_PID_LEN                                 , 20  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PID_LEN    );
+REG64_FLD( CAPP_ASE_TUPLE0_TID                                     , 44  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TID        );
+REG64_FLD( CAPP_ASE_TUPLE0_TID_LEN                                 , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TID_LEN    );
+REG64_FLD( CAPP_ASE_TUPLE0_VALID                                   , 63  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_VALID      );
+
+REG64_FLD( CAPP_ASE_TUPLE1_LPID                                    , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_LPID       );
+REG64_FLD( CAPP_ASE_TUPLE1_LPID_LEN                                , 12  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_LPID_LEN   );
+REG64_FLD( CAPP_ASE_TUPLE1_PID                                     , 20  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PID        );
+REG64_FLD( CAPP_ASE_TUPLE1_PID_LEN                                 , 20  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PID_LEN    );
+REG64_FLD( CAPP_ASE_TUPLE1_TID                                     , 44  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TID        );
+REG64_FLD( CAPP_ASE_TUPLE1_TID_LEN                                 , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TID_LEN    );
+REG64_FLD( CAPP_ASE_TUPLE1_VALID                                   , 63  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_VALID      );
+
+REG64_FLD( CAPP_ASE_TUPLE2_LPID                                    , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_LPID       );
+REG64_FLD( CAPP_ASE_TUPLE2_LPID_LEN                                , 12  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_LPID_LEN   );
+REG64_FLD( CAPP_ASE_TUPLE2_PID                                     , 20  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PID        );
+REG64_FLD( CAPP_ASE_TUPLE2_PID_LEN                                 , 20  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PID_LEN    );
+REG64_FLD( CAPP_ASE_TUPLE2_TID                                     , 44  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TID        );
+REG64_FLD( CAPP_ASE_TUPLE2_TID_LEN                                 , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TID_LEN    );
+REG64_FLD( CAPP_ASE_TUPLE2_VALID                                   , 63  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_VALID      );
+
+REG64_FLD( CAPP_ASE_TUPLE3_LPID                                    , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_LPID       );
+REG64_FLD( CAPP_ASE_TUPLE3_LPID_LEN                                , 12  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_LPID_LEN   );
+REG64_FLD( CAPP_ASE_TUPLE3_PID                                     , 20  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PID        );
+REG64_FLD( CAPP_ASE_TUPLE3_PID_LEN                                 , 20  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PID_LEN    );
+REG64_FLD( CAPP_ASE_TUPLE3_TID                                     , 44  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TID        );
+REG64_FLD( CAPP_ASE_TUPLE3_TID_LEN                                 , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TID_LEN    );
+REG64_FLD( CAPP_ASE_TUPLE3_VALID                                   , 63  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_VALID      );
+
+REG64_FLD( PU_N3_ATOMIC_LOCK_MASK_LATCH_REG_MASK                   , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_MASK       );
+REG64_FLD( PU_N3_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN               , 16  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( PU_N1_ATOMIC_LOCK_MASK_LATCH_REG_MASK                   , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_MASK       );
+REG64_FLD( PU_N1_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN               , 16  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( PU_ATOMIC_LOCK_MASK_LATCH_REG_MASK                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASK       );
+REG64_FLD( PU_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN                  , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( PU_N2_ATOMIC_LOCK_MASK_LATCH_REG_MASK                   , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_MASK       );
+REG64_FLD( PU_N2_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN               , 16  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( PEC_ATOMIC_LOCK_MASK_LATCH_REG_MASK                     , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MASK       );
+REG64_FLD( PEC_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN                 , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( PU_N0_ATOMIC_LOCK_MASK_LATCH_REG_MASK                   , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_MASK       );
+REG64_FLD( PU_N0_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN               , 16  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( PEC_ATOMIC_LOCK_REG_ENABLE                              , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PEC_ATOMIC_LOCK_REG_ID                                  , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( PEC_ATOMIC_LOCK_REG_ID_LEN                              , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ID_LEN     );
+REG64_FLD( PEC_ATOMIC_LOCK_REG_ACTIVITY                            , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY   );
+REG64_FLD( PEC_ATOMIC_LOCK_REG_ACTIVITY_LEN                        , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_RESERVED1                       , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_RESERVED1_LEN                   , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_START                           , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_START_LEN                       , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_RESERVED2                       , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_RESERVED2_LEN                   , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_END                             , 17  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_END_LEN                         , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( NV_ATR_HA_PTR_RESERVED1                                 , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( NV_ATR_HA_PTR_RESERVED1_LEN                             , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( NV_ATR_HA_PTR_START                                     , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( NV_ATR_HA_PTR_START_LEN                                 , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( NV_ATR_HA_PTR_RESERVED2                                 , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( NV_ATR_HA_PTR_RESERVED2_LEN                             , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( NV_ATR_HA_PTR_END                                       , 17  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( NV_ATR_HA_PTR_END_LEN                                   , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_RESERVED1                       , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_RESERVED1_LEN                   , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_START                           , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_START_LEN                       , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_RESERVED2                       , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_RESERVED2_LEN                   , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_END                             , 17  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_END_LEN                         , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( PU_NPU_SM0_ATS_CKSW_SPARE                               , 0   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_NPU_SM0_ATS_CKSW_SPARE_LEN                           , 64  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_ARB_STOP                            , 0   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_ARB_STOP   );
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_ARB_STALL                           , 1   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_ARB_STALL  );
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_TCE_CACHE_DISABLE                   , 2   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_TCE_CACHE_DISABLE );
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_TCE_CACHE_1W                        , 3   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_TCE_CACHE_1W );
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_CONFIG_BRAZOS                       , 4   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIG_BRAZOS );
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_CONFIG_SYNC_WAIT                    , 5   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIG_SYNC_WAIT );
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_CONFIG_SYNC_WAIT_LEN                , 5   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIG_SYNC_WAIT_LEN );
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_SPARE                               , 10  , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_NPU_SM1_ATS_CTRL_SPARE_LEN                           , 54  , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_TVT_ENTRY_INVALID_ESR               , 0   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_TVT_ENTRY_INVALID_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_TVT_ADDR_RANGE_ERR_ESR              , 1   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_TVT_ADDR_RANGE_ERR_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_TCE_PAGE_ACCESS_ERR_ESR             , 2   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_TCE_PAGE_ACCESS_ERR_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_TCE_CACHE_MULT_HIT_ERR_ESR          , 3   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_TCE_CACHE_MULT_HIT_ERR_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_MLC_ACCESS_ERR_ESR                  , 4   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_MLC_ACCESS_ERR_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_TCE_REQ_TO_ERR_ESR                  , 5   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_TCE_REQ_TO_ERR_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_TCD_PERR_ESR                        , 6   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_TCD_PERR_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_TDR_PERR_ESR                        , 7   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_TDR_PERR_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_AT_EA_UE_ESR                        , 8   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_AT_EA_UE_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_AT_EA_CE_ESR                        , 9   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_AT_EA_CE_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_AT_TDRMEM_UE_ESR                    , 10  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_AT_TDRMEM_UE_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_AT_TDRMEM_CE_ESR                    , 11  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_AT_TDRMEM_CE_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_RSPOUT_UE_ESR                       , 12  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_RSPOUT_UE_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_RSPOUT_CE_ESR                       , 13  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_RSPOUT_CE_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_TVT_PERR_ESR                        , 14  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_TVT_PERR_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_IODA_ADDR_PERR_ESR                  , 15  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_IODA_ADDR_PERR_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_CTRLR_PERR_ESR                      , 16  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_CTRLR_PERR_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_TOR_PERR_ESR                        , 17  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_TOR_PERR_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_INVAL_IODA_TBL_SEL_ESR              , 18  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_INVAL_IODA_TBL_SEL_ESR );
+REG64_FLD( PU_NPU_SM0_ATS_HOLD_ESR_RSVD_19                         , 19  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_ESR_RSVD_19 );
+
+REG64_FLD( PU_NPU_SM0_ATS_MASK_IDIAL                               , 0   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO  ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU_SM0_ATS_MASK_IDIAL_LEN                           , 20  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO  ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU_SM1_ATS_TCR_TCE_TIMEOUT                          , 10  , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_TCE_TIMEOUT );
+REG64_FLD( PU_NPU_SM1_ATS_TCR_TCE_TIMEOUT_LEN                      , 6   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_TCE_TIMEOUT_LEN );
+
+REG64_FLD( PU_BANK0_MCD_BOT_VALID                                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_BANK0_MCD_BOT_CPG                                    , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CPG        );
+REG64_FLD( PU_BANK0_MCD_BOT_GRP_MBR_ID                             , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_BANK0_MCD_BOT_ALWAYS_RTY                             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_BANK0_MCD_BOT_GRP_SIZE                               , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_BANK0_MCD_BOT_GRP_SIZE_LEN                           , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_BANK0_MCD_BOT_GRP_BASE                               , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE   );
+REG64_FLD( PU_BANK0_MCD_BOT_GRP_BASE_LEN                           , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_VALID                             , 0   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_CPG                               , 1   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_CPG        );
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_GRP_MBR_ID                        , 2   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_ALWAYS_RTY                        , 3   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_GRP_SIZE                          , 13  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_GRP_SIZE_LEN                      , 17  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_GRP_BASE                          , 33  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_BOT_GRP_BASE_LEN                      , 31  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_BANK0_MCD_CHA_VALID                                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_BANK0_MCD_CHA_CPG                                    , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CPG        );
+REG64_FLD( PU_BANK0_MCD_CHA_GRP_MBR_ID                             , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_BANK0_MCD_CHA_ALWAYS_RTY                             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_BANK0_MCD_CHA_GRP_SIZE                               , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_BANK0_MCD_CHA_GRP_SIZE_LEN                           , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_BANK0_MCD_CHA_GRP_BASE                               , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE   );
+REG64_FLD( PU_BANK0_MCD_CHA_GRP_BASE_LEN                           , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_VALID                             , 0   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_CPG                               , 1   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_CPG        );
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_GRP_MBR_ID                        , 2   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_ALWAYS_RTY                        , 3   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_GRP_SIZE                          , 13  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_GRP_SIZE_LEN                      , 17  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_GRP_BASE                          , 33  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_CHA_GRP_BASE_LEN                      , 31  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_BANK0_MCD_CMD_CHECK_CMDS                             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHECK_CMDS );
+REG64_FLD( PU_BANK0_MCD_CMD_CHECK_CMDS_LEN                         , 19  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHECK_CMDS_LEN );
+REG64_FLD( PU_BANK0_MCD_CMD_CHECK_CMDS_EN                          , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHECK_CMDS_EN );
+REG64_FLD( PU_BANK0_MCD_CMD_SET_CMDS                               , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_CMDS   );
+REG64_FLD( PU_BANK0_MCD_CMD_SET_CMDS_LEN                           , 19  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_CMDS_LEN );
+REG64_FLD( PU_BANK0_MCD_CMD_SET_CMDS_EN                            , 63  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_CMDS_EN );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_CMD_CHECK_CMDS                        , 0   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHECK_CMDS );
+REG64_FLD( PU_MCD1_BANK0_MCD_CMD_CHECK_CMDS_LEN                    , 19  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHECK_CMDS_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_CMD_CHECK_CMDS_EN                     , 31  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHECK_CMDS_EN );
+REG64_FLD( PU_MCD1_BANK0_MCD_CMD_SET_CMDS                          , 32  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_CMDS   );
+REG64_FLD( PU_MCD1_BANK0_MCD_CMD_SET_CMDS_LEN                      , 19  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_CMDS_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_CMD_SET_CMDS_EN                       , 63  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_CMDS_EN );
+
+REG64_FLD( PU_BANK0_MCD_REC_ENABLE                                 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_BANK0_MCD_REC_DONE                                   , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DONE       );
+REG64_FLD( PU_BANK0_MCD_REC_CONTINUOUS                             , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CONTINUOUS );
+REG64_FLD( PU_BANK0_MCD_REC_STATUS                                 , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STATUS     );
+REG64_FLD( PU_BANK0_MCD_REC_PACE                                   , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PACE       );
+REG64_FLD( PU_BANK0_MCD_REC_PACE_LEN                               , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PACE_LEN   );
+REG64_FLD( PU_BANK0_MCD_REC_ADDR_ERROR                             , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_ERROR );
+REG64_FLD( PU_BANK0_MCD_REC_ADDR                                   , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR       );
+REG64_FLD( PU_BANK0_MCD_REC_ADDR_LEN                               , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_BANK0_MCD_REC_RTY_COUNT                              , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RTY_COUNT  );
+REG64_FLD( PU_BANK0_MCD_REC_RTY_COUNT_LEN                          , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RTY_COUNT_LEN );
+REG64_FLD( PU_BANK0_MCD_REC_VG_COUNT                               , 49  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_VG_COUNT   );
+REG64_FLD( PU_BANK0_MCD_REC_VG_COUNT_LEN                           , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_VG_COUNT_LEN );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_ENABLE                            , 0   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_DONE                              , 1   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_DONE       );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_CONTINUOUS                        , 2   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_CONTINUOUS );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_STATUS                            , 5   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_STATUS     );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_PACE                              , 8   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_PACE       );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_PACE_LEN                          , 12  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_PACE_LEN   );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_ADDR_ERROR                        , 20  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_ERROR );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_ADDR                              , 21  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ADDR       );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_ADDR_LEN                          , 15  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_RTY_COUNT                         , 40  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RTY_COUNT  );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_RTY_COUNT_LEN                     , 4   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RTY_COUNT_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_VG_COUNT                          , 49  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_VG_COUNT   );
+REG64_FLD( PU_MCD1_BANK0_MCD_REC_VG_COUNT_LEN                      , 15  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_VG_COUNT_LEN );
+
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_ACCESS_EN                          , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_ACCESS_EN );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_WR_ENABLE                          , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_WR_ENABLE );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_REQ_PEND                           , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_REQ_PEND );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_READ_STATUS                        , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_READ_STATUS );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_WRITE_MODE                         , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_WRITE_MODE );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_WRITE_STATUS                       , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_WRITE_STATUS );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_ADDR                               , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_ADDR  );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_ADDR_LEN                           , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_ADDR_LEN );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_RDWR_DATA                          , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_RDWR_DATA );
+REG64_FLD( PU_BANK0_MCD_RW_RDWR_RDWR_DATA_LEN                      , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_RDWR_DATA_LEN );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_ACCESS_EN                     , 0   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_ACCESS_EN );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_WR_ENABLE                     , 1   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_WR_ENABLE );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_REQ_PEND                      , 3   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_REQ_PEND );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_READ_STATUS                   , 4   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_READ_STATUS );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_WRITE_MODE                    , 5   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_WRITE_MODE );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_WRITE_STATUS                  , 6   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_WRITE_STATUS );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_ADDR                          , 17  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_ADDR  );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_ADDR_LEN                      , 15  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_ADDR_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_RDWR_DATA                     , 32  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_RDWR_DATA );
+REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_RDWR_DATA_LEN                 , 32  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_RDWR_DATA_LEN );
+
+REG64_FLD( PU_BANK0_MCD_STR_VALID                                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_BANK0_MCD_STR_CPG                                    , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CPG        );
+REG64_FLD( PU_BANK0_MCD_STR_GRP_MBR_ID                             , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_BANK0_MCD_STR_ALWAYS_RTY                             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_BANK0_MCD_STR_GRP_SIZE                               , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_BANK0_MCD_STR_GRP_SIZE_LEN                           , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_BANK0_MCD_STR_GRP_BASE                               , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE   );
+REG64_FLD( PU_BANK0_MCD_STR_GRP_BASE_LEN                           , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_VALID                             , 0   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_CPG                               , 1   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_CPG        );
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_GRP_MBR_ID                        , 2   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_ALWAYS_RTY                        , 3   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_GRP_SIZE                          , 13  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_GRP_SIZE_LEN                      , 17  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_GRP_BASE                          , 33  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_STR_GRP_BASE_LEN                      , 31  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_BANK0_MCD_TOP_VALID                                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_BANK0_MCD_TOP_CPG                                    , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CPG        );
+REG64_FLD( PU_BANK0_MCD_TOP_GRP_MBR_ID                             , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_BANK0_MCD_TOP_ALWAYS_RTY                             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_BANK0_MCD_TOP_GRP_SIZE                               , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_BANK0_MCD_TOP_GRP_SIZE_LEN                           , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_BANK0_MCD_TOP_GRP_BASE                               , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE   );
+REG64_FLD( PU_BANK0_MCD_TOP_GRP_BASE_LEN                           , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_VALID                             , 0   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_CPG                               , 1   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_CPG        );
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_GRP_MBR_ID                        , 2   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_MBR_ID );
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_ALWAYS_RTY                        , 3   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ALWAYS_RTY );
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_GRP_SIZE                          , 13  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_GRP_SIZE_LEN                      , 17  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_SIZE_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_GRP_BASE                          , 33  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_TOP_GRP_BASE_LEN                      , 31  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_GRP_BASE_LEN );
+
+REG64_FLD( PU_BANK0_MCD_VGC_AVAIL_GROUPS                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_AVAIL_GROUPS );
+REG64_FLD( PU_BANK0_MCD_VGC_AVAIL_GROUPS_LEN                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_AVAIL_GROUPS_LEN );
+REG64_FLD( PU_BANK0_MCD_VGC_4X4_MODE                               , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_4X4_MODE   );
+REG64_FLD( PU_BANK0_MCD_VGC_HANG_POLL_ENABLE                       , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HANG_POLL_ENABLE );
+REG64_FLD( PU_BANK0_MCD_VGC_RND_BACKOFF_ENABLE                     , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RND_BACKOFF_ENABLE );
+REG64_FLD( PU_BANK0_MCD_VGC_DROP_PRIORITY_MODE                     , 35  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROP_PRIORITY_MODE );
+REG64_FLD( PU_BANK0_MCD_VGC_MASK_AGV_DISABLE_MODE                  , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MASK_AGV_DISABLE_MODE );
+REG64_FLD( PU_BANK0_MCD_VGC_XLATE_TO_ADDR_ID_ENABLE                , 37  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_XLATE_TO_ADDR_ID_ENABLE );
+
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_AVAIL_GROUPS                      , 0   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_AVAIL_GROUPS );
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_AVAIL_GROUPS_LEN                  , 16  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_AVAIL_GROUPS_LEN );
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_4X4_MODE                          , 32  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_4X4_MODE   );
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_HANG_POLL_ENABLE                  , 33  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HANG_POLL_ENABLE );
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_RND_BACKOFF_ENABLE                , 34  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_RND_BACKOFF_ENABLE );
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_DROP_PRIORITY_MODE                , 35  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROP_PRIORITY_MODE );
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_MASK_AGV_DISABLE_MODE             , 36  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_MASK_AGV_DISABLE_MODE );
+REG64_FLD( PU_MCD1_BANK0_MCD_VGC_XLATE_TO_ADDR_ID_ENABLE           , 37  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_XLATE_TO_ADDR_ID_ENABLE );
+
+REG64_FLD( PEC_STACK2_BARE_REG_PE_MMIO_BAR0_EN                     , 0   , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_MMIO_BAR0_EN );
+REG64_FLD( PEC_STACK2_BARE_REG_PE_MMIO_BAR1_EN                     , 1   , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_MMIO_BAR1_EN );
+REG64_FLD( PEC_STACK2_BARE_REG_PE_PHB_BAR_EN                       , 2   , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PHB_BAR_EN );
+REG64_FLD( PEC_STACK2_BARE_REG_PE_INT_BAR_EN                       , 3   , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_INT_BAR_EN );
+
+REG64_FLD( PEC_STACK1_BARE_REG_PE_MMIO_BAR0_EN                     , 0   , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_MMIO_BAR0_EN );
+REG64_FLD( PEC_STACK1_BARE_REG_PE_MMIO_BAR1_EN                     , 1   , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_MMIO_BAR1_EN );
+REG64_FLD( PEC_STACK1_BARE_REG_PE_PHB_BAR_EN                       , 2   , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PHB_BAR_EN );
+REG64_FLD( PEC_STACK1_BARE_REG_PE_INT_BAR_EN                       , 3   , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_INT_BAR_EN );
+
+REG64_FLD( PHB_BARE_REG_PE_MMIO_BAR0_EN                            , 0   , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_MMIO_BAR0_EN );
+REG64_FLD( PHB_BARE_REG_PE_MMIO_BAR1_EN                            , 1   , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_MMIO_BAR1_EN );
+REG64_FLD( PHB_BARE_REG_PE_PHB_BAR_EN                              , 2   , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PHB_BAR_EN );
+REG64_FLD( PHB_BARE_REG_PE_INT_BAR_EN                              , 3   , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_INT_BAR_EN );
+
+REG64_FLD( PEC_STACK0_BARE_REG_PE_MMIO_BAR0_EN                     , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_MMIO_BAR0_EN );
+REG64_FLD( PEC_STACK0_BARE_REG_PE_MMIO_BAR1_EN                     , 1   , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_MMIO_BAR1_EN );
+REG64_FLD( PEC_STACK0_BARE_REG_PE_PHB_BAR_EN                       , 2   , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PHB_BAR_EN );
+REG64_FLD( PEC_STACK0_BARE_REG_PE_INT_BAR_EN                       , 3   , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_INT_BAR_EN );
+
+REG64_FLD( PU_BCDE_CTL_STOP                                        , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_STOP       );
+REG64_FLD( PU_BCDE_CTL_START                                       , 1   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_START      );
+
+REG64_FLD( PU_BCDE_OCIBAR_ADDR                                     , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ADDR       );
+REG64_FLD( PU_BCDE_OCIBAR_ADDR_LEN                                 , 25  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ADDR_LEN   );
+
+REG64_FLD( PU_BCDE_PBADR_RESERVED_0_1                              , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_0_1 );
+REG64_FLD( PU_BCDE_PBADR_RESERVED_0_1_LEN                          , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_0_1_LEN );
+REG64_FLD( PU_BCDE_PBADR_PB_OFFSET                                 , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PB_OFFSET  );
+REG64_FLD( PU_BCDE_PBADR_PB_OFFSET_LEN                             , 23  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PB_OFFSET_LEN );
+REG64_FLD( PU_BCDE_PBADR_RESERVED_25_26                            , 25  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_25_26 );
+REG64_FLD( PU_BCDE_PBADR_RESERVED_25_26_LEN                        , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_25_26_LEN );
+REG64_FLD( PU_BCDE_PBADR_EXTADDR                                   , 27  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EXTADDR    );
+REG64_FLD( PU_BCDE_PBADR_EXTADDR_LEN                               , 14  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EXTADDR_LEN );
+REG64_FLD( PU_BCDE_PBADR_RESERVED_41_42                            , 41  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_41_42 );
+REG64_FLD( PU_BCDE_PBADR_RESERVED_41_42_LEN                        , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_41_42_LEN );
+
+REG64_FLD( PU_BCDE_SET_RESERVED_0_1                                , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_0_1 );
+REG64_FLD( PU_BCDE_SET_RESERVED_0_1_LEN                            , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_0_1_LEN );
+REG64_FLD( PU_BCDE_SET_COPY_LENGTH                                 , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_COPY_LENGTH );
+REG64_FLD( PU_BCDE_SET_COPY_LENGTH_LEN                             , 6   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_COPY_LENGTH_LEN );
+
+REG64_FLD( PU_BCDE_STAT_RUNNING                                    , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_BCDE_STAT_WAITING                                    , 1   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WAITING    );
+REG64_FLD( PU_BCDE_STAT_WRCMP                                      , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRCMP      );
+REG64_FLD( PU_BCDE_STAT_WRCMP_LEN                                  , 6   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRCMP_LEN  );
+REG64_FLD( PU_BCDE_STAT_RDCMP                                      , 14  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RDCMP      );
+REG64_FLD( PU_BCDE_STAT_RDCMP_LEN                                  , 6   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RDCMP_LEN  );
+REG64_FLD( PU_BCDE_STAT_DEBUG                                      , 20  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DEBUG      );
+REG64_FLD( PU_BCDE_STAT_DEBUG_LEN                                  , 9   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DEBUG_LEN  );
+REG64_FLD( PU_BCDE_STAT_STOPPED                                    , 29  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_STOPPED    );
+REG64_FLD( PU_BCDE_STAT_ERROR                                      , 30  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_BCDE_STAT_DONE                                       , 31  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DONE       );
+
+REG64_FLD( PU_BCUE_CTL_STOP                                        , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_STOP       );
+REG64_FLD( PU_BCUE_CTL_START                                       , 1   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_START      );
+
+REG64_FLD( PU_BCUE_OCIBAR_ADDR                                     , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ADDR       );
+REG64_FLD( PU_BCUE_OCIBAR_ADDR_LEN                                 , 25  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ADDR_LEN   );
+
+REG64_FLD( PU_BCUE_PBADR_RESERVED_0_1                              , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_0_1 );
+REG64_FLD( PU_BCUE_PBADR_RESERVED_0_1_LEN                          , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_0_1_LEN );
+REG64_FLD( PU_BCUE_PBADR_PB_OFFSET                                 , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PB_OFFSET  );
+REG64_FLD( PU_BCUE_PBADR_PB_OFFSET_LEN                             , 23  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PB_OFFSET_LEN );
+REG64_FLD( PU_BCUE_PBADR_RESERVED_25_26                            , 25  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_25_26 );
+REG64_FLD( PU_BCUE_PBADR_RESERVED_25_26_LEN                        , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_25_26_LEN );
+REG64_FLD( PU_BCUE_PBADR_EXTADDR                                   , 27  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EXTADDR    );
+REG64_FLD( PU_BCUE_PBADR_EXTADDR_LEN                               , 14  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EXTADDR_LEN );
+REG64_FLD( PU_BCUE_PBADR_RESERVED_41_42                            , 41  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_41_42 );
+REG64_FLD( PU_BCUE_PBADR_RESERVED_41_42_LEN                        , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_41_42_LEN );
+
+REG64_FLD( PU_BCUE_SET_RESERVED_0_1                                , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_0_1 );
+REG64_FLD( PU_BCUE_SET_RESERVED_0_1_LEN                            , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_0_1_LEN );
+REG64_FLD( PU_BCUE_SET_COPY_LENGTH                                 , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_COPY_LENGTH );
+REG64_FLD( PU_BCUE_SET_COPY_LENGTH_LEN                             , 6   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_COPY_LENGTH_LEN );
+
+REG64_FLD( PU_BCUE_STAT_RUNNING                                    , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_BCUE_STAT_WAITING                                    , 1   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WAITING    );
+REG64_FLD( PU_BCUE_STAT_WRCMP                                      , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRCMP      );
+REG64_FLD( PU_BCUE_STAT_WRCMP_LEN                                  , 6   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRCMP_LEN  );
+REG64_FLD( PU_BCUE_STAT_RDCMP                                      , 14  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RDCMP      );
+REG64_FLD( PU_BCUE_STAT_RDCMP_LEN                                  , 6   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RDCMP_LEN  );
+REG64_FLD( PU_BCUE_STAT_DEBUG                                      , 20  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DEBUG      );
+REG64_FLD( PU_BCUE_STAT_DEBUG_LEN                                  , 9   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DEBUG_LEN  );
+REG64_FLD( PU_BCUE_STAT_STOPPED                                    , 29  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_STOPPED    );
+REG64_FLD( PU_BCUE_STAT_ERROR                                      , 30  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_BCUE_STAT_DONE                                       , 31  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DONE       );
+
+REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_WILDCARD                   , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_WILDCARD   );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_RESERVED                   , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_RESERVED_LEN               , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_PE                         , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_00_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_00_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_00_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_00_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_00_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_00_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_00_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_WILDCARD                   , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_WILDCARD   );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_RESERVED                   , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_RESERVED_LEN               , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_PE                         , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_WILDCARD                   , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_WILDCARD   );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_RESERVED                   , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_RESERVED_LEN               , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_PE                         , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_RESERVED                   , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_RESERVED_LEN               , 3   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_PE                         , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_01_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_01_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_01_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_01_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_01_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_01_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_01_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_RESERVED                   , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_RESERVED_LEN               , 3   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_PE                         , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_RESERVED                   , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_RESERVED_LEN               , 3   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_PE                         , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_RESERVED                   , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_RESERVED_LEN               , 3   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_PE                         , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_02_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_02_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_02_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_02_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_02_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_02_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_02_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_RESERVED                   , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_RESERVED_LEN               , 3   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_PE                         , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_RESERVED                   , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_RESERVED_LEN               , 3   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_PE                         , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_WILDCARD                   , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_WILDCARD   );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_RESERVED                   , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_RESERVED_LEN               , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_PE                         , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_10_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_10_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_10_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_10_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_10_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_10_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_10_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_WILDCARD                   , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_WILDCARD   );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_RESERVED                   , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_RESERVED_LEN               , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_PE                         , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_WILDCARD                   , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_WILDCARD   );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_RESERVED                   , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_RESERVED_LEN               , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_PE                         , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_RESERVED                   , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_RESERVED_LEN               , 3   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_PE                         , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_11_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_11_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_11_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_11_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_11_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_11_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_11_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_RESERVED                   , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_RESERVED_LEN               , 3   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_PE                         , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_RESERVED                   , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_RESERVED_LEN               , 3   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_PE                         , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_RESERVED                   , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_RESERVED_LEN               , 3   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_PE                         , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_12_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_12_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_12_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_12_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_12_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_12_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_12_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_RESERVED                   , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_RESERVED_LEN               , 3   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_PE                         , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_RESERVED                   , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_RESERVED_LEN               , 3   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_PE                         , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_BDF                        , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_BDF_LEN                    , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_20_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_20_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_20_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_20_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_20_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_20_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_20_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_21_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_21_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_21_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_21_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_21_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_21_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_21_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_22_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_22_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_22_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_22_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_22_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_22_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_22_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_30_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_30_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_30_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_30_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_30_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_30_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_30_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_31_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_31_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_31_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_31_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_31_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_31_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_31_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_32_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_32_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_32_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_32_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_32_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_32_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_32_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_40_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_40_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_40_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_40_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_40_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_40_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_40_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_41_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_41_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_41_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_41_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_41_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_41_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_41_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_42_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_42_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_42_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_42_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_42_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_42_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_42_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_BDF2PE_50_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_BDF2PE_50_CONFIG_RESERVED                        , 1   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_BDF2PE_50_CONFIG_RESERVED_LEN                    , 3   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_BDF2PE_50_CONFIG_PE                              , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_BDF2PE_50_CONFIG_PE_LEN                          , 4   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_BDF2PE_50_CONFIG_BDF                             , 8   , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_BDF2PE_50_CONFIG_BDF_LEN                         , 16  , SH_UNT_PU_NPU   , SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_DAT_BDF2PE_51_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_DAT_BDF2PE_51_CONFIG_RESERVED                    , 1   , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_DAT_BDF2PE_51_CONFIG_RESERVED_LEN                , 3   , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_DAT_BDF2PE_51_CONFIG_PE                          , 4   , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_DAT_BDF2PE_51_CONFIG_PE_LEN                      , 4   , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_DAT_BDF2PE_51_CONFIG_BDF                         , 8   , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_DAT_BDF2PE_51_CONFIG_BDF_LEN                     , 16  , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_RESERVED                    , 1   , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_RESERVED_LEN                , 3   , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_PE                          , 4   , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_PE_LEN                      , 4   , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_BDF                         , 8   , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     ,
+           SH_FLD_BDF        );
+REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_BDF_LEN                     , 16  , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM     ,
+           SH_FLD_BDF_LEN    );
+
+REG64_FLD( PEC_BIST_TC_START_TEST_DC                               , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TC_START_TEST_DC );
+REG64_FLD( PEC_BIST_TC_SRAM_ABIST_MODE_DC                          , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TC_SRAM_ABIST_MODE_DC );
+REG64_FLD( PEC_BIST_TC_EDRAM_ABIST_MODE_DC                         , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TC_EDRAM_ABIST_MODE_DC );
+REG64_FLD( PEC_BIST_TC_IOBIST_MODE_DC                              , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TC_IOBIST_MODE_DC );
+REG64_FLD( PEC_BIST_PERV                                           , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( PEC_BIST_UNIT1                                          , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( PEC_BIST_UNIT2                                          , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( PEC_BIST_UNIT3                                          , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( PEC_BIST_UNIT4                                          , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( PEC_BIST_UNIT5                                          , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( PEC_BIST_UNIT6                                          , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( PEC_BIST_UNIT7                                          , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( PEC_BIST_UNIT8                                          , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( PEC_BIST_UNIT9                                          , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( PEC_BIST_UNIT10                                         , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( PEC_BIST_STROBE_WINDOW_EN                               , 48  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STROBE_WINDOW_EN );
+
+REG64_FLD( CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_ENABLE   , 1   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_ENABLE );
+REG64_FLD( CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_PERIOD_MASK , 48  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_PERIOD_MASK );
+REG64_FLD( CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_PERIOD_MASK_LEN , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_PERIOD_MASK_LEN );
+
+REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_ERROR_RECOVERY_INITIATED   , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_RECOVERY_INITIATED );
+REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_ERROR_RECOVERY_COMPLETE    , 1   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_RECOVERY_COMPLETE );
+REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_TLBI_PSL_DEAD              , 3   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TLBI_PSL_DEAD );
+REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_TLBI_FENCE                 , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TLBI_FENCE );
+REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_RECOVERY_FAILED            , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_RECOVERY_FAILED );
+REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_RTAGFLUSH_FAILED           , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_RTAGFLUSH_FAILED );
+REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_PRECISE_DIR_FLUSH_FAILED   , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PRECISE_DIR_FLUSH_FAILED );
+REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_COURSE_DIR_FLUSH_FAILED    , 8   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COURSE_DIR_FLUSH_FAILED );
+REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_RECOVERY_HANG_DETECTED     , 9   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_RECOVERY_HANG_DETECTED );
+REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_EPOCH_VALUE                , 10  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_EPOCH_VALUE );
+REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_EPOCH_VALUE_LEN            , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_EPOCH_VALUE_LEN );
+REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_FORCE_QUIESCE              , 14  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_QUIESCE );
+REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_QUIESCE_DONE               , 15  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_QUIESCE_DONE );
+
+REG64_FLD( PEC_CC_ATOMIC_LOCK_REG_ENABLE                           , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PEC_CC_ATOMIC_LOCK_REG_ID                               , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( PEC_CC_ATOMIC_LOCK_REG_ID_LEN                           , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ID_LEN     );
+REG64_FLD( PEC_CC_ATOMIC_LOCK_REG_ACTIVITY                         , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY   );
+REG64_FLD( PEC_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN                     , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( PEC_CC_PROTECT_MODE_REG_READ_ENABLE                     , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_READ_ENABLE );
+REG64_FLD( PEC_CC_PROTECT_MODE_REG_WRITE_ENABLE                    , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( PU_NPU0_CERR_ECC_FIRST_BITS                             , 10  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU0_CERR_ECC_FIRST_BITS_LEN                         , 54  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU1_CERR_ECC_FIRST_BITS                             , 10  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU1_CERR_ECC_FIRST_BITS_LEN                         , 54  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU2_CERR_ECC_FIRST_BITS                             , 10  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU2_CERR_ECC_FIRST_BITS_LEN                         , 54  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_UE                       , 10  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_UE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_UE_LEN                   , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_UE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_UE                       , 14  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_UE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_UE_LEN                   , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_UE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_UE                       , 18  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_UE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_UE_LEN                   , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_UE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_UE                       , 20  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_UE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_UE_LEN                   , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_UE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_UE                       , 24  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_UE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_UE_LEN                   , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_UE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_SUE                      , 28  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_SUE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_SUE_LEN                  , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_SUE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_SUE                      , 32  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_SUE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_SUE_LEN                  , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_SUE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_SUE                      , 36  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_SUE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_SUE_LEN                  , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_SUE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_SUE                      , 38  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_SUE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_SUE_LEN                  , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_SUE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_SUE                      , 42  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_SUE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_SUE_LEN                  , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_SUE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_CE                       , 46  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_CE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_CE_LEN                   , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_CE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_CE                       , 50  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_CE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_CE_LEN                   , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_CE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_CE                       , 54  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_CE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_CE_LEN                   , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_CE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_CE                       , 56  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_CE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_CE_LEN                   , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_CE_LEN );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_CE                       , 60  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_CE );
+REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_CE_LEN                   , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_CE_LEN );
+
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_UE                       , 10  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_UE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_UE_LEN                   , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_UE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_UE                       , 14  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_UE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_UE_LEN                   , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_UE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_UE                       , 18  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_UE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_UE_LEN                   , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_UE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_UE                       , 20  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_UE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_UE_LEN                   , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_UE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_UE                       , 24  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_UE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_UE_LEN                   , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_UE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_SUE                      , 28  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_SUE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_SUE_LEN                  , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_SUE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_SUE                      , 32  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_SUE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_SUE_LEN                  , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_SUE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_SUE                      , 36  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_SUE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_SUE_LEN                  , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_SUE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_SUE                      , 38  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_SUE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_SUE_LEN                  , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_SUE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_SUE                      , 42  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_SUE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_SUE_LEN                  , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_SUE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_CE                       , 46  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_CE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_CE_LEN                   , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_CE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_CE                       , 50  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_CE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_CE_LEN                   , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_CE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_CE                       , 54  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_CE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_CE_LEN                   , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_CE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_CE                       , 56  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_CE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_CE_LEN                   , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_CE_LEN );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_CE                       , 60  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_CE );
+REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_CE_LEN                   , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_CE_LEN );
+
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_UE                       , 10  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_UE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_UE_LEN                   , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_UE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_UE                       , 14  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_UE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_UE_LEN                   , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_UE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_UE                       , 18  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_UE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_UE_LEN                   , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_UE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_UE                       , 20  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_UE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_UE_LEN                   , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_UE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_UE                       , 24  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_UE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_UE_LEN                   , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_UE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_SUE                      , 28  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_SUE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_SUE_LEN                  , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_SUE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_SUE                      , 32  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_SUE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_SUE_LEN                  , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_SUE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_SUE                      , 36  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_SUE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_SUE_LEN                  , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_SUE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_SUE                      , 38  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_SUE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_SUE_LEN                  , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_SUE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_SUE                      , 42  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_SUE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_SUE_LEN                  , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_SUE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_CE                       , 46  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_CE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_CE_LEN                   , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PT_CE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_CE                       , 50  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_CE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_CE_LEN                   , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PR_CE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_CE                       , 54  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_CE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_CE_LEN                   , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BR_CE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_CE                       , 56  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_CE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_CE_LEN                   , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IR_CE_LEN );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_CE                       , 60  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_CE );
+REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_CE_LEN                   , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OR_CE_LEN );
+
+REG64_FLD( PU_NPU0_CERR_ECC_MASK_BITS                              , 10  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU0_CERR_ECC_MASK_BITS_LEN                          , 54  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU1_CERR_ECC_MASK_BITS                              , 10  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU1_CERR_ECC_MASK_BITS_LEN                          , 54  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU2_CERR_ECC_MASK_BITS                              , 10  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU2_CERR_ECC_MASK_BITS_LEN                          , 54  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            , 5   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_8 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            , 9   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_9 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_10 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           , 11  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_11 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_12 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           , 13  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_13 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           , 14  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_14 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           , 15  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_15 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_16 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           , 17  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_17 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_18 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           , 19  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_19 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_20 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           , 21  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_21 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           , 22  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_22 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           , 23  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_23 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24           , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_24 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25           , 25  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_25 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26           , 26  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_26 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27           , 27  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_27 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28           , 28  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_28 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29           , 29  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_29 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30           , 30  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_30 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31           , 31  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_31 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            , 32  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            , 33  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            , 34  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            , 35  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            , 36  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            , 37  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            , 38  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            , 39  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           , 40  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           , 41  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           , 42  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           , 43  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            , 44  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            , 45  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            , 46  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            , 47  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            , 48  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            , 49  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            , 50  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            , 51  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            , 52  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            , 53  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            , 54  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            , 55  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_3 );
+
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            , 5   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_8 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            , 9   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_9 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_10 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           , 11  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_11 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_12 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           , 13  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_13 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           , 14  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_14 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           , 15  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_15 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_16 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           , 17  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_17 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_18 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           , 19  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_19 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_20 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           , 21  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_21 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           , 22  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_22 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           , 23  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_23 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24           , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_24 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25           , 25  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_25 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26           , 26  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_26 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27           , 27  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_27 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28           , 28  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_28 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29           , 29  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_29 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30           , 30  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_30 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31           , 31  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_31 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            , 32  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            , 33  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            , 34  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            , 35  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            , 36  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            , 37  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            , 38  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            , 39  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           , 40  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           , 41  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           , 42  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           , 43  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            , 44  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            , 45  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            , 46  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            , 47  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            , 48  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            , 49  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            , 50  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            , 51  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            , 52  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            , 53  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            , 54  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            , 55  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_3 );
+
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            , 5   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_8 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            , 9   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_9 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_10 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           , 11  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_11 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_12 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           , 13  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_13 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           , 14  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_14 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           , 15  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_15 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_16 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           , 17  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_17 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_18 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           , 19  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_19 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_20 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           , 21  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_21 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           , 22  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_22 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           , 23  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_23 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24           , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_24 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25           , 25  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_25 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26           , 26  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_26 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27           , 27  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_27 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28           , 28  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_28 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29           , 29  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_29 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30           , 30  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_30 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31           , 31  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_31 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            , 32  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            , 33  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            , 34  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            , 35  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            , 36  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            , 37  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            , 38  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            , 39  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           , 40  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           , 41  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           , 42  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           , 43  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            , 44  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            , 45  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            , 46  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            , 47  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            , 48  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            , 49  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            , 50  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            , 51  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            , 52  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            , 53  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            , 54  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            , 55  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_3 );
+
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            , 5   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_8 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            , 9   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_9 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_10 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           , 11  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_11 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_12 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           , 13  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_13 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           , 14  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_14 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           , 15  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_15 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_16 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           , 17  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_17 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_18 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           , 19  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_19 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_20 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           , 21  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_21 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           , 22  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_22 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           , 23  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_23 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24           , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_24 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25           , 25  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_25 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26           , 26  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_26 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27           , 27  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_27 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28           , 28  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_28 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29           , 29  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_29 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30           , 30  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_30 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31           , 31  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_31 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            , 32  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            , 33  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            , 34  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            , 35  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            , 36  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            , 37  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            , 38  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            , 39  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           , 40  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           , 41  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           , 42  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           , 43  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            , 44  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            , 45  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            , 46  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            , 47  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            , 48  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            , 49  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            , 50  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            , 51  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            , 52  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            , 53  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            , 54  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            , 55  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_3 );
+
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            , 5   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_8 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            , 9   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_9 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_10 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           , 11  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_11 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_12 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           , 13  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_13 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           , 14  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_14 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           , 15  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_15 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_16 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           , 17  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_17 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_18 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           , 19  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_19 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_20 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           , 21  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_21 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           , 22  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_22 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           , 23  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_23 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24           , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_24 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25           , 25  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_25 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26           , 26  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_26 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27           , 27  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_27 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28           , 28  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_28 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29           , 29  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_29 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30           , 30  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_30 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31           , 31  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_31 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            , 32  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            , 33  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            , 34  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            , 35  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            , 36  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            , 37  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            , 38  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            , 39  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           , 40  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           , 41  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           , 42  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           , 43  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            , 44  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            , 45  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            , 46  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            , 47  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            , 48  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            , 49  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            , 50  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            , 51  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            , 52  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            , 53  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            , 54  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            , 55  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_3 );
+
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            , 5   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_8 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            , 9   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_9 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_10 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           , 11  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_11 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_12 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           , 13  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_13 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           , 14  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_14 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           , 15  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_15 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_16 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           , 17  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_17 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_18 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           , 19  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_19 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_20 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           , 21  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_21 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           , 22  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_22 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           , 23  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_23 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24           , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_24 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25           , 25  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_25 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26           , 26  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_26 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27           , 27  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_27 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28           , 28  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_28 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29           , 29  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_29 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30           , 30  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_30 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31           , 31  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_31 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            , 32  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            , 33  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            , 34  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            , 35  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            , 36  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            , 37  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            , 38  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            , 39  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           , 40  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           , 41  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           , 42  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           , 43  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            , 44  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            , 45  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            , 46  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            , 47  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            , 48  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            , 49  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            , 50  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            , 51  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            , 52  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            , 53  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            , 54  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            , 55  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_3 );
+
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            , 5   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_8 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            , 9   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_9 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_10 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           , 11  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_11 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_12 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           , 13  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_13 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           , 14  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_14 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           , 15  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_15 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_16 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           , 17  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_17 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_18 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           , 19  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_19 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_20 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           , 21  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_21 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           , 22  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_22 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           , 23  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_23 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24           , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_24 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25           , 25  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_25 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26           , 26  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_26 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27           , 27  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_27 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28           , 28  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_28 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29           , 29  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_29 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30           , 30  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_30 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31           , 31  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_31 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            , 32  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            , 33  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            , 34  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            , 35  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            , 36  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            , 37  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            , 38  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            , 39  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           , 40  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           , 41  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           , 42  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           , 43  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            , 44  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            , 45  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            , 46  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            , 47  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            , 48  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            , 49  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            , 50  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            , 51  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            , 52  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            , 53  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            , 54  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            , 55  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_3 );
+
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_0           , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_1           , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_2           , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_3           , 3   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_4           , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_5           , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_6           , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_7           , 7   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_0           , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_1           , 9   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_2           , 10  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_3           , 11  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_4           , 12  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_5           , 13  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_6           , 14  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_7           , 15  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_8           , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_8 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_9           , 17  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_9 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_10          , 18  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_10 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_11          , 19  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_11 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_12          , 20  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_12 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_13          , 21  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_13 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_14          , 22  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_14 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_15          , 23  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_15 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_16          , 24  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_16 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_17          , 25  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_17 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_18          , 26  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_18 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_19          , 27  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_19 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_20          , 28  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_20 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_21          , 29  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_21 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_22          , 30  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_22 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_23          , 31  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_23 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_0          , 32  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV1_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_1          , 33  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV1_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_2          , 34  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV1_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_3          , 35  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV1_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_0          , 36  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_1          , 37  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_2          , 38  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_3          , 39  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_4          , 40  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_5          , 41  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_6          , 42  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_7          , 43  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_0           , 44  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_1           , 45  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_2           , 46  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_3           , 47  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_4           , 48  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_5           , 49  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_6           , 50  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_7           , 51  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_0           , 52  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_REG_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_1           , 53  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_REG_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_2           , 54  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_REG_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_3           , 55  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_REG_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_0           , 56  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_DUE_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_1           , 57  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_DUE_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_2           , 58  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_DUE_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_3           , 59  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_DUE_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_0           , 60  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PEF_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_1           , 61  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PEF_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_2           , 62  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PEF_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_3           , 63  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PEF_3 );
+
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            , 5   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_8 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            , 9   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_9 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_10 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           , 11  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_11 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_12 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           , 13  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_13 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           , 14  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_14 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           , 15  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_15 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_16 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           , 17  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_17 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_18 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           , 19  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_19 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_20 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           , 21  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_21 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           , 22  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_22 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           , 23  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_23 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24           , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_24 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25           , 25  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_25 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26           , 26  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_26 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27           , 27  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_27 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28           , 28  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_28 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29           , 29  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_29 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30           , 30  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_30 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31           , 31  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_31 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            , 32  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            , 33  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            , 34  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            , 35  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            , 36  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            , 37  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            , 38  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            , 39  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           , 40  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           , 41  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           , 42  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           , 43  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            , 44  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            , 45  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            , 46  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            , 47  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            , 48  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            , 49  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            , 50  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            , 51  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            , 52  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            , 53  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            , 54  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            , 55  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_3 );
+
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            , 5   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_8 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            , 9   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_9 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_10 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           , 11  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_11 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_12 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           , 13  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_13 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           , 14  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_14 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           , 15  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_15 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_16 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           , 17  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_17 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_18 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           , 19  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_19 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_20 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           , 21  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_21 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           , 22  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_22 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           , 23  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_23 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24           , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_24 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25           , 25  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_25 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26           , 26  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_26 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27           , 27  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_27 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28           , 28  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_28 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29           , 29  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_29 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30           , 30  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_30 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31           , 31  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_31 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            , 32  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            , 33  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            , 34  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            , 35  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            , 36  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            , 37  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            , 38  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            , 39  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           , 40  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           , 41  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           , 42  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           , 43  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            , 44  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            , 45  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            , 46  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            , 47  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            , 48  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            , 49  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            , 50  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            , 51  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            , 52  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            , 53  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            , 54  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            , 55  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_3 );
+
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            , 5   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_8 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            , 9   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_9 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_10 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           , 11  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_11 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_12 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           , 13  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_13 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           , 14  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_14 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           , 15  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_15 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_16 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           , 17  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_17 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_18 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           , 19  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_19 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_20 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           , 21  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_21 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           , 22  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_22 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           , 23  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_23 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24           , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_24 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25           , 25  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_25 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26           , 26  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_26 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27           , 27  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_27 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28           , 28  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_28 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29           , 29  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_29 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30           , 30  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_30 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31           , 31  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_31 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            , 32  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            , 33  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            , 34  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            , 35  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            , 36  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            , 37  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            , 38  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            , 39  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           , 40  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           , 41  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           , 42  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           , 43  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            , 44  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            , 45  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            , 46  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            , 47  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            , 48  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            , 49  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            , 50  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            , 51  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            , 52  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            , 53  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            , 54  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            , 55  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_3 );
+
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_0           , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_1           , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_2           , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_3           , 3   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_4           , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_5           , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_6           , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_7           , 7   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_0           , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_1           , 9   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_2           , 10  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_3           , 11  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_4           , 12  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_5           , 13  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_6           , 14  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_7           , 15  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_8           , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_8 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_9           , 17  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_9 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_10          , 18  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_10 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_11          , 19  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_11 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_12          , 20  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_12 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_13          , 21  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_13 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_14          , 22  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_14 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_15          , 23  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_15 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_16          , 24  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_16 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_17          , 25  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_17 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_18          , 26  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_18 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_19          , 27  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_19 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_20          , 28  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_20 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_21          , 29  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_21 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_22          , 30  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_22 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_23          , 31  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_23 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_0          , 32  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV1_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_1          , 33  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV1_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_2          , 34  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV1_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_3          , 35  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV1_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_0          , 36  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_1          , 37  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_2          , 38  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_3          , 39  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_4          , 40  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_5          , 41  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_6          , 42  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_7          , 43  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_0           , 44  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_1           , 45  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_2           , 46  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_3           , 47  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_4           , 48  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_5           , 49  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_6           , 50  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_7           , 51  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_0           , 52  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_REG_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_1           , 53  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_REG_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_2           , 54  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_REG_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_3           , 55  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_REG_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_0           , 56  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_DUE_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_1           , 57  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_DUE_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_2           , 58  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_DUE_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_3           , 59  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_DUE_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_0           , 60  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PEF_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_1           , 61  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PEF_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_2           , 62  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PEF_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_3           , 63  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PEF_3 );
+
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_0           , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_1           , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_2           , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_3           , 3   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_4           , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_5           , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_6           , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_7           , 7   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NCF_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_0           , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_1           , 9   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_2           , 10  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_3           , 11  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_4           , 12  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_5           , 13  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_6           , 14  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_7           , 15  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_8           , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_8 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_9           , 17  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_9 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_10          , 18  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_10 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_11          , 19  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_11 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_12          , 20  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_12 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_13          , 21  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_13 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_14          , 22  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_14 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_15          , 23  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_15 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_16          , 24  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_16 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_17          , 25  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_17 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_18          , 26  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_18 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_19          , 27  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_19 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_20          , 28  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_20 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_21          , 29  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_21 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_22          , 30  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_22 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_23          , 31  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NVF_23 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_0          , 32  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV1_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_1          , 33  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV1_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_2          , 34  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV1_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_3          , 35  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV1_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_0          , 36  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_1          , 37  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_2          , 38  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_3          , 39  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_4          , 40  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_5          , 41  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_6          , 42  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_7          , 43  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_ASBE_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_0           , 44  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_1           , 45  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_2           , 46  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_3           , 47  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_4           , 48  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_5           , 49  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_6           , 50  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_7           , 51  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBR_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_0           , 52  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_REG_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_1           , 53  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_REG_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_2           , 54  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_REG_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_3           , 55  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_REG_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_0           , 56  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_DUE_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_1           , 57  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_DUE_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_2           , 58  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_DUE_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_3           , 59  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_DUE_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_0           , 60  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PEF_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_1           , 61  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PEF_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_2           , 62  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PEF_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_3           , 63  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PEF_3 );
+
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            , 5   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_8 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            , 9   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_9 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_10 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           , 11  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_11 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_12 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           , 13  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_13 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           , 14  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_14 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           , 15  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_15 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_16 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           , 17  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_17 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_18 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           , 19  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_19 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_20 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           , 21  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_21 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           , 22  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_22 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           , 23  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_23 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24           , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_24 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25           , 25  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_25 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26           , 26  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_26 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27           , 27  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_27 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28           , 28  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_28 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29           , 29  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_29 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30           , 30  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_30 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31           , 31  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_31 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            , 32  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            , 33  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            , 34  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            , 35  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            , 36  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            , 37  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            , 38  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            , 39  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           , 40  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           , 41  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           , 42  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           , 43  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            , 44  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            , 45  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            , 46  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            , 47  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            , 48  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            , 49  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            , 50  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            , 51  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            , 52  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            , 53  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            , 54  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            , 55  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_3 );
+
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0            , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1            , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2            , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3            , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4            , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5            , 5   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6            , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7            , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8            , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_8 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9            , 9   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_9 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10           , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_10 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11           , 11  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_11 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12           , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_12 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13           , 13  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_13 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14           , 14  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_14 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15           , 15  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_15 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16           , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_16 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17           , 17  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_17 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18           , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_18 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19           , 19  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_19 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20           , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_20 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21           , 21  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_21 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22           , 22  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_22 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23           , 23  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_23 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24           , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_24 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25           , 25  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_25 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26           , 26  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_26 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27           , 27  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_27 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28           , 28  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_28 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29           , 29  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_29 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30           , 30  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_30 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31           , 31  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NVF_31 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0            , 32  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1            , 33  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2            , 34  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3            , 35  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4            , 36  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5            , 37  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6            , 38  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7            , 39  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NCF_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0           , 40  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1           , 41  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2           , 42  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3           , 43  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_ASBE_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0            , 44  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1            , 45  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2            , 46  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3            , 47  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4            , 48  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5            , 49  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6            , 50  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7            , 51  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBR_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0            , 52  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1            , 53  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2            , 54  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3            , 55  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_REG_3 );
+
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           , 5   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_8 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           , 9   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_9 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_10 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          , 11  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_11 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_12 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          , 13  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_13 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          , 14  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_14 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          , 15  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_15 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            , 17  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            , 19  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            , 21  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            , 22  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            , 23  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            , 25  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            , 26  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            , 27  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            , 28  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            , 29  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            , 30  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            , 31  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            , 32  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            , 33  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            , 34  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            , 35  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            , 36  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            , 37  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            , 38  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            , 39  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            , 40  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_8 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            , 41  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_9 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           , 42  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_10 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           , 43  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_11 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            , 44  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            , 45  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            , 46  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            , 47  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            , 48  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            , 49  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            , 50  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            , 51  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            , 52  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_8 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            , 53  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_9 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           , 54  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_10 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           , 55  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_11 );
+
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           , 5   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_8 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           , 9   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_9 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_10 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          , 11  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_11 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_12 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          , 13  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_13 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          , 14  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_14 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          , 15  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_15 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            , 17  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            , 19  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            , 21  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            , 22  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            , 23  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            , 25  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            , 26  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            , 27  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            , 28  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            , 29  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            , 30  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            , 31  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            , 32  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            , 33  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            , 34  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            , 35  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            , 36  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            , 37  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            , 38  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            , 39  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            , 40  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_8 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            , 41  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_9 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           , 42  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_10 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           , 43  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_11 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            , 44  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            , 45  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            , 46  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            , 47  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            , 48  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            , 49  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            , 50  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            , 51  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            , 52  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_8 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            , 53  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_9 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           , 54  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_10 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           , 55  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_11 );
+
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_0                          , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_1                          , 1   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_2                          , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_3                          , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_4                          , 4   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_5                          , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_6                          , 6   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_7                          , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_8                          , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_9                          , 9   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_10                         , 10  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_11                         , 11  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_12                         , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_13                         , 13  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_14                         , 14  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_15                         , 15  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_16                         , 16  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_17                         , 17  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_18                         , 18  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_19                         , 19  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_20                         , 20  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_21                         , 21  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_22                         , 22  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_23                         , 23  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_24                         , 24  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_25                         , 25  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_26                         , 26  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_27                         , 27  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_28                         , 28  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_29                         , 29  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_30                         , 30  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_31                         , 31  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_32                         , 32  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_33                         , 33  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_34                         , 34  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_35                         , 35  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_36                         , 36  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_37                         , 37  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_38                         , 38  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_39                         , 39  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_40                         , 40  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_41                         , 41  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_42                         , 42  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_43                         , 43  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_44                         , 44  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_45                         , 45  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_46                         , 46  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_47                         , 47  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_48                         , 48  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_49                         , 49  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_50                         , 50  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_51                         , 51  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_52                         , 52  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_53                         , 53  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_54                         , 54  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_55                         , 55  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_56                         , 56  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_57                         , 57  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_58                         , 58  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_59                         , 59  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_60                         , 60  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_61                         , 61  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_62                         , 62  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_63                         , 63  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           , 5   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_8 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           , 9   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_9 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_10 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          , 11  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_11 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_12 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          , 13  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_13 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          , 14  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_14 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          , 15  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_15 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            , 17  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            , 19  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            , 21  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            , 22  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            , 23  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            , 25  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            , 26  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            , 27  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            , 28  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            , 29  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            , 30  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            , 31  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            , 32  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            , 33  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            , 34  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            , 35  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            , 36  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            , 37  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            , 38  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            , 39  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            , 40  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_8 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            , 41  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_9 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           , 42  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_10 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           , 43  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_11 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            , 44  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            , 45  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            , 46  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            , 47  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            , 48  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            , 49  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            , 50  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            , 51  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            , 52  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_8 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            , 53  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_9 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           , 54  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_10 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           , 55  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_11 );
+
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           , 5   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_8 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           , 9   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_9 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_10 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          , 11  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_11 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_12 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          , 13  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_13 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          , 14  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_14 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          , 15  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_15 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            , 17  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            , 19  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            , 21  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            , 22  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            , 23  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            , 25  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            , 26  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            , 27  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            , 28  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            , 29  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            , 30  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            , 31  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            , 32  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            , 33  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            , 34  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            , 35  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            , 36  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            , 37  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            , 38  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            , 39  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            , 40  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_8 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            , 41  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_9 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           , 42  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_10 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           , 43  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_11 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            , 44  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            , 45  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            , 46  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            , 47  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            , 48  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            , 49  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            , 50  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            , 51  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            , 52  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_8 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            , 53  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_9 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           , 54  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_10 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           , 55  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_11 );
+
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_0           , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_1           , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_2           , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_3           , 3   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_4           , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_5           , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_6           , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_7           , 7   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_8           , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_8 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_9           , 9   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_9 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_10          , 10  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_10 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_11          , 11  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_11 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_12          , 12  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_12 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_13          , 13  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_13 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_14          , 14  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_14 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_15          , 15  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_15 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_0           , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_1           , 17  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_2           , 18  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_3           , 19  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_4           , 20  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_5           , 21  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_6           , 22  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_7           , 23  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_0           , 24  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_1           , 25  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_2           , 26  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_3           , 27  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_4           , 28  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_5           , 29  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_6           , 30  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_7           , 31  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_0           , 32  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_1           , 33  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_2           , 34  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_3           , 35  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_4           , 36  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_5           , 37  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_6           , 38  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_7           , 39  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_0           , 40  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_1           , 41  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_2           , 42  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_3           , 43  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_4           , 44  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_5           , 45  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_6           , 46  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_7           , 47  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_0           , 48  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_1           , 49  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_2           , 50  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_3           , 51  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_4           , 52  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_5           , 53  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_6           , 54  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_7           , 55  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_0          , 56  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV2_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_1          , 57  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV2_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_2          , 58  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV2_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_3          , 59  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV2_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_0          , 60  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV3_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_1          , 61  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV3_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_2          , 62  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV3_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_3          , 63  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV3_3 );
+
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           , 5   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_8 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           , 9   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_9 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_10 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          , 11  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_11 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_12 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          , 13  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_13 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          , 14  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_14 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          , 15  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_15 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            , 17  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            , 19  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            , 21  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            , 22  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            , 23  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            , 25  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            , 26  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            , 27  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            , 28  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            , 29  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            , 30  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            , 31  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            , 32  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            , 33  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            , 34  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            , 35  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            , 36  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            , 37  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            , 38  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            , 39  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            , 40  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_8 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            , 41  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_9 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           , 42  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_10 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           , 43  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_11 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            , 44  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            , 45  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            , 46  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            , 47  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            , 48  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            , 49  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            , 50  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            , 51  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            , 52  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_8 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            , 53  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_9 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           , 54  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_10 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           , 55  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_11 );
+
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           , 5   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_8 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           , 9   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_9 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_10 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          , 11  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_11 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_12 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          , 13  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_13 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          , 14  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_14 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          , 15  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_15 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            , 17  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            , 19  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            , 21  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            , 22  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            , 23  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            , 25  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            , 26  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            , 27  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            , 28  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            , 29  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            , 30  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            , 31  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            , 32  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            , 33  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            , 34  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            , 35  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            , 36  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            , 37  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            , 38  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            , 39  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            , 40  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_8 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            , 41  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_9 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           , 42  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_10 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           , 43  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_11 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            , 44  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            , 45  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            , 46  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            , 47  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            , 48  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            , 49  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            , 50  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            , 51  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            , 52  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_8 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            , 53  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_9 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           , 54  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_10 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           , 55  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_11 );
+
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_0                          , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_1                          , 1   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_2                          , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_3                          , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_4                          , 4   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_5                          , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_6                          , 6   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_7                          , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_8                          , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_9                          , 9   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_10                         , 10  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_11                         , 11  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_12                         , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_13                         , 13  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_14                         , 14  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_15                         , 15  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_16                         , 16  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_17                         , 17  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_18                         , 18  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_19                         , 19  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_20                         , 20  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_21                         , 21  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_22                         , 22  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_23                         , 23  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_24                         , 24  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_25                         , 25  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_26                         , 26  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_27                         , 27  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_28                         , 28  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_29                         , 29  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_30                         , 30  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_31                         , 31  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_32                         , 32  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_33                         , 33  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_34                         , 34  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_35                         , 35  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_36                         , 36  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_37                         , 37  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_38                         , 38  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_39                         , 39  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_40                         , 40  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_41                         , 41  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_42                         , 42  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_43                         , 43  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_44                         , 44  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_45                         , 45  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_46                         , 46  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_47                         , 47  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_48                         , 48  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_49                         , 49  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_50                         , 50  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_51                         , 51  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_52                         , 52  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_53                         , 53  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_54                         , 54  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_55                         , 55  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_56                         , 56  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_57                         , 57  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_58                         , 58  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_59                         , 59  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_60                         , 60  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_61                         , 61  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_62                         , 62  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_63                         , 63  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           , 5   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_8 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           , 9   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_9 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_10 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          , 11  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_11 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_12 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          , 13  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_13 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          , 14  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_14 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          , 15  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_15 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            , 17  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            , 19  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            , 21  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            , 22  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            , 23  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            , 25  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            , 26  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            , 27  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            , 28  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            , 29  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            , 30  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            , 31  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            , 32  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            , 33  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            , 34  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            , 35  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            , 36  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            , 37  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            , 38  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            , 39  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            , 40  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_8 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            , 41  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_9 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           , 42  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_10 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           , 43  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_11 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            , 44  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            , 45  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            , 46  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            , 47  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            , 48  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            , 49  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            , 50  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            , 51  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            , 52  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_8 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            , 53  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_9 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           , 54  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_10 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           , 55  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_11 );
+
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           , 5   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_8 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           , 9   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_9 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_10 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          , 11  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_11 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_12 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          , 13  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_13 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          , 14  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_14 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          , 15  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_15 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            , 17  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            , 19  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            , 21  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            , 22  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            , 23  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            , 25  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            , 26  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            , 27  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            , 28  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            , 29  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            , 30  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            , 31  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            , 32  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            , 33  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            , 34  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            , 35  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            , 36  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            , 37  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            , 38  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            , 39  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            , 40  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_8 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            , 41  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_9 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           , 42  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_10 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           , 43  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_11 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            , 44  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            , 45  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            , 46  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            , 47  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            , 48  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            , 49  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            , 50  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            , 51  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            , 52  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_8 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            , 53  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_9 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           , 54  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_10 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           , 55  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_11 );
+
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           , 5   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_8 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           , 9   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_9 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_10 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          , 11  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_11 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_12 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          , 13  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_13 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          , 14  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_14 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          , 15  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_15 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            , 17  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            , 19  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            , 21  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            , 22  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            , 23  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            , 25  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            , 26  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            , 27  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            , 28  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            , 29  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            , 30  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            , 31  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            , 32  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            , 33  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            , 34  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            , 35  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            , 36  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            , 37  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            , 38  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            , 39  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            , 40  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_8 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            , 41  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_9 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           , 42  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_10 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           , 43  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_11 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            , 44  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            , 45  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            , 46  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            , 47  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            , 48  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            , 49  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            , 50  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            , 51  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            , 52  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_8 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            , 53  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_9 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           , 54  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_10 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           , 55  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_11 );
+
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_0           , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_1           , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_2           , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_3           , 3   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_4           , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_5           , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_6           , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_7           , 7   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_8           , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_8 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_9           , 9   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_9 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_10          , 10  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_10 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_11          , 11  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_11 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_12          , 12  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_12 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_13          , 13  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_13 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_14          , 14  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_14 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_15          , 15  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_15 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_0           , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_1           , 17  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_2           , 18  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_3           , 19  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_4           , 20  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_5           , 21  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_6           , 22  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_7           , 23  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_0           , 24  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_1           , 25  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_2           , 26  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_3           , 27  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_4           , 28  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_5           , 29  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_6           , 30  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_7           , 31  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_0           , 32  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_1           , 33  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_2           , 34  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_3           , 35  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_4           , 36  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_5           , 37  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_6           , 38  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_7           , 39  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_0           , 40  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_1           , 41  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_2           , 42  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_3           , 43  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_4           , 44  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_5           , 45  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_6           , 46  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_7           , 47  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_0           , 48  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_1           , 49  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_2           , 50  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_3           , 51  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_4           , 52  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_5           , 53  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_6           , 54  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_7           , 55  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_0          , 56  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV2_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_1          , 57  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV2_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_2          , 58  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV2_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_3          , 59  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV2_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_0          , 60  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV3_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_1          , 61  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV3_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_2          , 62  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV3_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_3          , 63  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV3_3 );
+
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           , 5   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_8 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           , 9   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_9 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_10 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          , 11  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_11 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_12 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          , 13  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_13 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          , 14  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_14 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          , 15  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_15 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            , 17  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            , 19  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            , 21  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            , 22  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            , 23  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            , 25  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            , 26  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            , 27  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            , 28  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            , 29  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            , 30  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            , 31  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            , 32  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            , 33  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            , 34  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            , 35  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            , 36  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            , 37  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            , 38  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            , 39  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            , 40  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_8 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            , 41  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_9 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           , 42  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_10 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           , 43  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_11 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            , 44  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            , 45  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            , 46  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            , 47  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            , 48  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            , 49  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            , 50  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            , 51  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            , 52  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_8 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            , 53  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_9 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           , 54  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_10 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           , 55  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_11 );
+
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           , 5   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_8 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           , 9   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_9 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_10 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          , 11  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_11 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_12 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          , 13  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_13 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          , 14  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_14 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          , 15  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_15 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            , 17  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            , 19  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            , 21  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            , 22  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            , 23  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            , 25  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            , 26  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            , 27  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            , 28  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            , 29  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            , 30  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            , 31  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            , 32  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            , 33  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            , 34  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            , 35  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            , 36  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            , 37  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            , 38  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            , 39  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            , 40  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_8 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            , 41  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_9 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           , 42  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_10 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           , 43  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_11 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            , 44  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            , 45  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            , 46  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            , 47  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            , 48  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            , 49  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            , 50  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            , 51  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            , 52  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_8 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            , 53  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_9 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           , 54  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_10 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           , 55  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_11 );
+
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_0           , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_1           , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_2           , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_3           , 3   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_4           , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_5           , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_6           , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_7           , 7   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_8           , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_8 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_9           , 9   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_9 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_10          , 10  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_10 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_11          , 11  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_11 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_12          , 12  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_12 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_13          , 13  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_13 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_14          , 14  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_14 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_15          , 15  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_NLG_15 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_0           , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_1           , 17  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_2           , 18  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_3           , 19  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_4           , 20  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_5           , 21  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_6           , 22  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_7           , 23  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_FWD_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_0           , 24  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_1           , 25  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_2           , 26  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_3           , 27  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_4           , 28  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_5           , 29  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_6           , 30  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_7           , 31  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_AUE_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_0           , 32  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_1           , 33  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_2           , 34  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_3           , 35  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_4           , 36  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_5           , 37  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_6           , 38  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_7           , 39  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBP_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_0           , 40  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_1           , 41  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_2           , 42  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_3           , 43  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_4           , 44  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_5           , 45  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_6           , 46  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_7           , 47  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBF_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_0           , 48  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_1           , 49  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_2           , 50  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_3           , 51  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_4           , 52  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_5           , 53  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_6           , 54  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_7           , 55  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_PBC_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_0          , 56  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV2_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_1          , 57  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV2_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_2          , 58  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV2_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_3          , 59  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV2_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_0          , 60  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV3_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_1          , 61  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV3_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_2          , 62  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV3_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_3          , 63  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_FIRST_RSV3_3 );
+
+REG64_FLD( NV_CERR_FIRST1_NTL_0                                    , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( NV_CERR_FIRST1_NTL_1                                    , 1   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( NV_CERR_FIRST1_NTL_2                                    , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( NV_CERR_FIRST1_NTL_3                                    , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( NV_CERR_FIRST1_NTL_4                                    , 4   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( NV_CERR_FIRST1_NTL_5                                    , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( NV_CERR_FIRST1_NTL_6                                    , 6   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( NV_CERR_FIRST1_NTL_7                                    , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( NV_CERR_FIRST1_NTL_8                                    , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( NV_CERR_FIRST1_NTL_9                                    , 9   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( NV_CERR_FIRST1_NTL_10                                   , 10  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( NV_CERR_FIRST1_NTL_11                                   , 11  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( NV_CERR_FIRST1_NTL_12                                   , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( NV_CERR_FIRST1_NTL_13                                   , 13  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( NV_CERR_FIRST1_NTL_14                                   , 14  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( NV_CERR_FIRST1_NTL_15                                   , 15  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( NV_CERR_FIRST1_NTL_16                                   , 16  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( NV_CERR_FIRST1_NTL_17                                   , 17  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( NV_CERR_FIRST1_NTL_18                                   , 18  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( NV_CERR_FIRST1_NTL_19                                   , 19  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( NV_CERR_FIRST1_NTL_20                                   , 20  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( NV_CERR_FIRST1_NTL_21                                   , 21  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( NV_CERR_FIRST1_NTL_22                                   , 22  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( NV_CERR_FIRST1_NTL_23                                   , 23  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( NV_CERR_FIRST1_NTL_24                                   , 24  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( NV_CERR_FIRST1_NTL_25                                   , 25  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( NV_CERR_FIRST1_NTL_26                                   , 26  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( NV_CERR_FIRST1_NTL_27                                   , 27  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( NV_CERR_FIRST1_NTL_28                                   , 28  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( NV_CERR_FIRST1_NTL_29                                   , 29  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( NV_CERR_FIRST1_NTL_30                                   , 30  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( NV_CERR_FIRST1_NTL_31                                   , 31  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( NV_CERR_FIRST1_NTL_32                                   , 32  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( NV_CERR_FIRST1_NTL_33                                   , 33  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( NV_CERR_FIRST1_NTL_34                                   , 34  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( NV_CERR_FIRST1_NTL_35                                   , 35  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( NV_CERR_FIRST1_NTL_36                                   , 36  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( NV_CERR_FIRST1_NTL_37                                   , 37  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( NV_CERR_FIRST1_NTL_38                                   , 38  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( NV_CERR_FIRST1_NTL_39                                   , 39  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( NV_CERR_FIRST1_NTL_40                                   , 40  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( NV_CERR_FIRST1_NTL_41                                   , 41  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( NV_CERR_FIRST1_NTL_42                                   , 42  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( NV_CERR_FIRST1_NTL_43                                   , 43  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( NV_CERR_FIRST1_NTL_44                                   , 44  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( NV_CERR_FIRST1_NTL_45                                   , 45  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( NV_CERR_FIRST1_NTL_46                                   , 46  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( NV_CERR_FIRST1_NTL_47                                   , 47  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( NV_CERR_FIRST1_NTL_48                                   , 48  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( NV_CERR_FIRST1_NTL_49                                   , 49  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( NV_CERR_FIRST1_NTL_50                                   , 50  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( NV_CERR_FIRST1_NTL_51                                   , 51  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( NV_CERR_FIRST1_NTL_52                                   , 52  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( NV_CERR_FIRST1_NTL_53                                   , 53  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( NV_CERR_FIRST1_NTL_54                                   , 54  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( NV_CERR_FIRST1_NTL_55                                   , 55  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( NV_CERR_FIRST1_NTL_56                                   , 56  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( NV_CERR_FIRST1_NTL_57                                   , 57  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( NV_CERR_FIRST1_NTL_58                                   , 58  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( NV_CERR_FIRST1_NTL_59                                   , 59  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( NV_CERR_FIRST1_NTL_60                                   , 60  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( NV_CERR_FIRST1_NTL_61                                   , 61  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( NV_CERR_FIRST1_NTL_62                                   , 62  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( NV_CERR_FIRST1_NTL_63                                   , 63  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0           , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1           , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2           , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3           , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4           , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5           , 5   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6           , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7           , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8           , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_8 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9           , 9   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_9 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10          , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_10 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11          , 11  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_11 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12          , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_12 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13          , 13  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_13 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14          , 14  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_14 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15          , 15  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLGX_15 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0            , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1            , 17  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2            , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3            , 19  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_FWD_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0            , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1            , 21  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2            , 22  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3            , 23  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_AUE_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0            , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1            , 25  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2            , 26  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3            , 27  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4            , 28  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5            , 29  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6            , 30  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7            , 31  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBP_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0            , 32  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1            , 33  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2            , 34  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3            , 35  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4            , 36  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5            , 37  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6            , 38  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7            , 39  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8            , 40  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_8 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9            , 41  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_9 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10           , 42  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_10 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11           , 43  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBF_11 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0            , 44  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1            , 45  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2            , 46  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3            , 47  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4            , 48  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5            , 49  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6            , 50  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7            , 51  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8            , 52  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_8 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9            , 53  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_9 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10           , 54  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_10 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11           , 55  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_PBC_11 );
+
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            , 5   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_8 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            , 9   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_9 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_10 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           , 11  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_11 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_12 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           , 13  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_13 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           , 14  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_14 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           , 15  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_15 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_16 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           , 17  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_17 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_18 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           , 19  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_19 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_20 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           , 21  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_21 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           , 22  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_22 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           , 23  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_23 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_24 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           , 25  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_25 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           , 26  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_26 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           , 27  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_27 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           , 28  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_28 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           , 29  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_29 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           , 30  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_30 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           , 31  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_31 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           , 32  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_32 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           , 33  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_33 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           , 34  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_34 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           , 35  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_35 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           , 36  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_36 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           , 37  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_37 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           , 38  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_38 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           , 39  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_39 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           , 40  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_40 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           , 41  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_41 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           , 42  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_42 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           , 43  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_43 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           , 44  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_44 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           , 45  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_45 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           , 46  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_46 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           , 47  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_47 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           , 48  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_48 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           , 49  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_49 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           , 50  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_50 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           , 51  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_51 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           , 52  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_52 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           , 53  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_53 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           , 54  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_54 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           , 55  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_55 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           , 56  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_56 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           , 57  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_57 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           , 58  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_58 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           , 59  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_59 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           , 60  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_60 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           , 61  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_61 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           , 62  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_62 );
+REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           , 63  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_63 );
+
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_0                          , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_1                          , 1   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_2                          , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_3                          , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_4                          , 4   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_5                          , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_6                          , 6   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_7                          , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_8                          , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_9                          , 9   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_10                         , 10  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_11                         , 11  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_12                         , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_13                         , 13  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_14                         , 14  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_15                         , 15  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_16                         , 16  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_17                         , 17  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_18                         , 18  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_19                         , 19  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_20                         , 20  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_21                         , 21  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_22                         , 22  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_23                         , 23  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_24                         , 24  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_25                         , 25  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_26                         , 26  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_27                         , 27  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_28                         , 28  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_29                         , 29  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_30                         , 30  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_31                         , 31  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_32                         , 32  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_33                         , 33  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_34                         , 34  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_35                         , 35  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_36                         , 36  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_37                         , 37  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_38                         , 38  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_39                         , 39  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_40                         , 40  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_41                         , 41  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_42                         , 42  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_43                         , 43  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_44                         , 44  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_45                         , 45  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_46                         , 46  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_47                         , 47  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_48                         , 48  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_49                         , 49  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_50                         , 50  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_51                         , 51  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_52                         , 52  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_53                         , 53  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_54                         , 54  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_55                         , 55  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_56                         , 56  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_57                         , 57  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_58                         , 58  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_59                         , 59  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_60                         , 60  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_61                         , 61  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_62                         , 62  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_63                         , 63  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            , 5   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_8 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            , 9   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_9 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_10 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           , 11  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_11 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_12 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           , 13  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_13 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           , 14  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_14 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           , 15  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_15 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_16 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           , 17  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_17 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_18 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           , 19  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_19 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_20 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           , 21  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_21 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           , 22  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_22 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           , 23  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_23 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_24 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           , 25  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_25 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           , 26  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_26 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           , 27  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_27 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           , 28  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_28 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           , 29  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_29 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           , 30  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_30 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           , 31  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_31 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           , 32  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_32 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           , 33  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_33 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           , 34  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_34 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           , 35  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_35 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           , 36  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_36 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           , 37  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_37 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           , 38  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_38 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           , 39  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_39 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           , 40  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_40 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           , 41  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_41 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           , 42  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_42 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           , 43  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_43 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           , 44  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_44 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           , 45  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_45 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           , 46  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_46 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           , 47  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_47 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           , 48  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_48 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           , 49  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_49 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           , 50  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_50 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           , 51  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_51 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           , 52  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_52 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           , 53  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_53 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           , 54  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_54 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           , 55  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_55 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           , 56  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_56 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           , 57  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_57 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           , 58  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_58 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           , 59  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_59 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           , 60  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_60 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           , 61  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_61 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           , 62  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_62 );
+REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           , 63  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_63 );
+
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            , 5   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_8 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            , 9   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_9 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_10 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           , 11  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_11 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_12 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           , 13  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_13 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           , 14  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_14 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           , 15  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_15 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_16 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           , 17  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_17 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_18 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           , 19  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_19 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_20 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           , 21  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_21 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           , 22  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_22 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           , 23  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_23 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_24 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           , 25  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_25 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           , 26  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_26 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           , 27  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_27 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           , 28  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_28 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           , 29  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_29 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           , 30  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_30 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           , 31  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_31 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           , 32  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_32 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           , 33  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_33 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           , 34  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_34 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           , 35  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_35 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           , 36  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_36 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           , 37  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_37 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           , 38  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_38 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           , 39  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_39 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           , 40  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_40 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           , 41  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_41 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           , 42  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_42 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           , 43  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_43 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           , 44  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_44 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           , 45  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_45 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           , 46  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_46 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           , 47  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_47 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           , 48  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_48 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           , 49  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_49 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           , 50  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_50 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           , 51  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_51 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           , 52  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_52 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           , 53  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_53 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           , 54  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_54 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           , 55  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_55 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           , 56  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_56 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           , 57  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_57 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           , 58  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_58 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           , 59  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_59 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           , 60  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_60 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           , 61  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_61 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           , 62  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_62 );
+REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           , 63  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_63 );
+
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            , 5   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_8 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            , 9   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_9 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_10 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           , 11  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_11 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_12 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           , 13  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_13 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           , 14  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_14 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           , 15  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_15 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_16 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           , 17  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_17 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_18 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           , 19  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_19 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_20 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           , 21  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_21 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           , 22  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_22 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           , 23  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_23 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_24 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           , 25  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_25 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           , 26  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_26 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           , 27  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_27 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           , 28  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_28 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           , 29  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_29 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           , 30  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_30 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           , 31  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_31 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           , 32  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_32 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           , 33  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_33 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           , 34  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_34 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           , 35  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_35 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           , 36  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_36 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           , 37  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_37 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           , 38  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_38 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           , 39  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_39 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           , 40  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_40 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           , 41  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_41 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           , 42  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_42 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           , 43  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_43 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           , 44  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_44 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           , 45  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_45 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           , 46  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_46 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           , 47  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_47 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           , 48  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_48 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           , 49  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_49 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           , 50  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_50 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           , 51  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_51 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           , 52  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_52 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           , 53  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_53 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           , 54  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_54 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           , 55  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_55 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           , 56  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_56 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           , 57  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_57 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           , 58  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_58 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           , 59  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_59 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           , 60  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_60 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           , 61  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_61 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           , 62  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_62 );
+REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           , 63  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_63 );
+
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            , 5   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_8 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            , 9   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_9 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_10 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           , 11  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_11 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_12 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           , 13  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_13 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           , 14  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_14 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           , 15  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_15 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_16 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           , 17  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_17 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_18 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           , 19  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_19 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_20 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           , 21  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_21 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           , 22  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_22 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           , 23  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_23 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_24 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           , 25  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_25 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           , 26  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_26 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           , 27  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_27 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           , 28  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_28 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           , 29  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_29 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           , 30  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_30 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           , 31  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_31 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           , 32  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_32 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           , 33  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_33 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           , 34  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_34 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           , 35  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_35 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           , 36  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_36 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           , 37  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_37 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           , 38  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_38 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           , 39  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_39 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           , 40  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_40 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           , 41  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_41 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           , 42  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_42 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           , 43  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_43 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           , 44  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_44 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           , 45  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_45 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           , 46  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_46 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           , 47  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_47 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           , 48  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_48 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           , 49  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_49 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           , 50  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_50 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           , 51  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_51 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           , 52  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_52 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           , 53  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_53 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           , 54  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_54 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           , 55  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_55 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           , 56  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_56 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           , 57  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_57 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           , 58  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_58 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           , 59  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_59 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           , 60  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_60 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           , 61  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_61 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           , 62  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_62 );
+REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           , 63  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_63 );
+
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_0                          , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_1                          , 1   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_2                          , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_3                          , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_4                          , 4   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_5                          , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_6                          , 6   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_7                          , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_8                          , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_9                          , 9   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_10                         , 10  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_11                         , 11  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_12                         , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_13                         , 13  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_14                         , 14  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_15                         , 15  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_16                         , 16  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_17                         , 17  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_18                         , 18  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_19                         , 19  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_20                         , 20  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_21                         , 21  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_22                         , 22  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_23                         , 23  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_24                         , 24  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_25                         , 25  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_26                         , 26  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_27                         , 27  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_28                         , 28  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_29                         , 29  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_30                         , 30  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_31                         , 31  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_32                         , 32  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_33                         , 33  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_34                         , 34  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_35                         , 35  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_36                         , 36  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_37                         , 37  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_38                         , 38  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_39                         , 39  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_40                         , 40  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_41                         , 41  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_42                         , 42  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_43                         , 43  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_44                         , 44  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_45                         , 45  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_46                         , 46  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_47                         , 47  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_48                         , 48  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_49                         , 49  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_50                         , 50  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_51                         , 51  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_52                         , 52  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_53                         , 53  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_54                         , 54  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_55                         , 55  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_56                         , 56  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_57                         , 57  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_58                         , 58  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_59                         , 59  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_60                         , 60  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_61                         , 61  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_62                         , 62  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_63                         , 63  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            , 5   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_8 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            , 9   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_9 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_10 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           , 11  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_11 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_12 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           , 13  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_13 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           , 14  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_14 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           , 15  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_15 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_16 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           , 17  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_17 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_18 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           , 19  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_19 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_20 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           , 21  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_21 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           , 22  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_22 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           , 23  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_23 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_24 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           , 25  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_25 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           , 26  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_26 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           , 27  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_27 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           , 28  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_28 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           , 29  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_29 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           , 30  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_30 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           , 31  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_31 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           , 32  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_32 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           , 33  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_33 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           , 34  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_34 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           , 35  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_35 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           , 36  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_36 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           , 37  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_37 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           , 38  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_38 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           , 39  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_39 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           , 40  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_40 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           , 41  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_41 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           , 42  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_42 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           , 43  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_43 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           , 44  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_44 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           , 45  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_45 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           , 46  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_46 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           , 47  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_47 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           , 48  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_48 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           , 49  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_49 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           , 50  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_50 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           , 51  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_51 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           , 52  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_52 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           , 53  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_53 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           , 54  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_54 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           , 55  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_55 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           , 56  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_56 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           , 57  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_57 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           , 58  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_58 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           , 59  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_59 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           , 60  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_60 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           , 61  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_61 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           , 62  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_62 );
+REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           , 63  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_63 );
+
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            , 5   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_8 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            , 9   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_9 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_10 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           , 11  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_11 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_12 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           , 13  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_13 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           , 14  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_14 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           , 15  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_15 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_16 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           , 17  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_17 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_18 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           , 19  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_19 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_20 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           , 21  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_21 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           , 22  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_22 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           , 23  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_23 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_24 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           , 25  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_25 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           , 26  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_26 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           , 27  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_27 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           , 28  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_28 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           , 29  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_29 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           , 30  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_30 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           , 31  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_31 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           , 32  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_32 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           , 33  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_33 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           , 34  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_34 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           , 35  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_35 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           , 36  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_36 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           , 37  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_37 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           , 38  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_38 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           , 39  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_39 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           , 40  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_40 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           , 41  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_41 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           , 42  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_42 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           , 43  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_43 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           , 44  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_44 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           , 45  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_45 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           , 46  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_46 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           , 47  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_47 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           , 48  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_48 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           , 49  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_49 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           , 50  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_50 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           , 51  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_51 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           , 52  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_52 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           , 53  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_53 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           , 54  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_54 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           , 55  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_55 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           , 56  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_56 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           , 57  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_57 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           , 58  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_58 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           , 59  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_59 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           , 60  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_60 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           , 61  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_61 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           , 62  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_62 );
+REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           , 63  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_63 );
+
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            , 5   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_8 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            , 9   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_9 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_10 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           , 11  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_11 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_12 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           , 13  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_13 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           , 14  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_14 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           , 15  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_15 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_16 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           , 17  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_17 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_18 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           , 19  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_19 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_20 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           , 21  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_21 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           , 22  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_22 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           , 23  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_23 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_24 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           , 25  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_25 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           , 26  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_26 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           , 27  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_27 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           , 28  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_28 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           , 29  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_29 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           , 30  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_30 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           , 31  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_31 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           , 32  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_32 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           , 33  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_33 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           , 34  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_34 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           , 35  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_35 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           , 36  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_36 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           , 37  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_37 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           , 38  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_38 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           , 39  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_39 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           , 40  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_40 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           , 41  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_41 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           , 42  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_42 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           , 43  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_43 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           , 44  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_44 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           , 45  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_45 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           , 46  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_46 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           , 47  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_47 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           , 48  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_48 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           , 49  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_49 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           , 50  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_50 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           , 51  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_51 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           , 52  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_52 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           , 53  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_53 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           , 54  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_54 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           , 55  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_55 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           , 56  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_56 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           , 57  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_57 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           , 58  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_58 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           , 59  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_59 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           , 60  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_60 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           , 61  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_61 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           , 62  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_62 );
+REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           , 63  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_63 );
+
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            , 5   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_8 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            , 9   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_9 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_10 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           , 11  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_11 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_12 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           , 13  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_13 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           , 14  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_14 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           , 15  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_15 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_16 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           , 17  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_17 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_18 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           , 19  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_19 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_20 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           , 21  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_21 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           , 22  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_22 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           , 23  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_23 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_24 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           , 25  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_25 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           , 26  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_26 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           , 27  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_27 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           , 28  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_28 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           , 29  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_29 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           , 30  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_30 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           , 31  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_31 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           , 32  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_32 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           , 33  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_33 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           , 34  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_34 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           , 35  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_35 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           , 36  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_36 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           , 37  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_37 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           , 38  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_38 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           , 39  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_39 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           , 40  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_40 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           , 41  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_41 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           , 42  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_42 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           , 43  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_43 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           , 44  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_44 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           , 45  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_45 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           , 46  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_46 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           , 47  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_47 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           , 48  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_48 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           , 49  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_49 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           , 50  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_50 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           , 51  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_51 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           , 52  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_52 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           , 53  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_53 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           , 54  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_54 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           , 55  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_55 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           , 56  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_56 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           , 57  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_57 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           , 58  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_58 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           , 59  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_59 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           , 60  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_60 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           , 61  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_61 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           , 62  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_62 );
+REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           , 63  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_63 );
+
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            , 5   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_8 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            , 9   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_9 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_10 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           , 11  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_11 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_12 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           , 13  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_13 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           , 14  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_14 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           , 15  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_15 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_16 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           , 17  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_17 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_18 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           , 19  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_19 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_20 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           , 21  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_21 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           , 22  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_22 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           , 23  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_23 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_24 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           , 25  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_25 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           , 26  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_26 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           , 27  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_27 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           , 28  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_28 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           , 29  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_29 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           , 30  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_30 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           , 31  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_31 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           , 32  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_32 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           , 33  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_33 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           , 34  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_34 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           , 35  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_35 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           , 36  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_36 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           , 37  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_37 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           , 38  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_38 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           , 39  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_39 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           , 40  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_40 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           , 41  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_41 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           , 42  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_42 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           , 43  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_43 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           , 44  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_44 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           , 45  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_45 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           , 46  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_46 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           , 47  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_47 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           , 48  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_48 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           , 49  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_49 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           , 50  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_50 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           , 51  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_51 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           , 52  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_52 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           , 53  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_53 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           , 54  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_54 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           , 55  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_55 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           , 56  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_56 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           , 57  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_57 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           , 58  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_58 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           , 59  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_59 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           , 60  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_60 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           , 61  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_61 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           , 62  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_62 );
+REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           , 63  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_63 );
+
+REG64_FLD( NV_CERR_FIRST2_NTL_0                                    , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( NV_CERR_FIRST2_NTL_1                                    , 1   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( NV_CERR_FIRST2_NTL_2                                    , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( NV_CERR_FIRST2_NTL_3                                    , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( NV_CERR_FIRST2_NTL_4                                    , 4   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( NV_CERR_FIRST2_NTL_5                                    , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( NV_CERR_FIRST2_NTL_6                                    , 6   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( NV_CERR_FIRST2_NTL_7                                    , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( NV_CERR_FIRST2_NTL_8                                    , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( NV_CERR_FIRST2_NTL_9                                    , 9   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( NV_CERR_FIRST2_NTL_10                                   , 10  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( NV_CERR_FIRST2_NTL_11                                   , 11  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( NV_CERR_FIRST2_NTL_12                                   , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( NV_CERR_FIRST2_NTL_13                                   , 13  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( NV_CERR_FIRST2_NTL_14                                   , 14  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( NV_CERR_FIRST2_NTL_15                                   , 15  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( NV_CERR_FIRST2_NTL_16                                   , 16  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( NV_CERR_FIRST2_NTL_17                                   , 17  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( NV_CERR_FIRST2_NTL_18                                   , 18  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( NV_CERR_FIRST2_NTL_19                                   , 19  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( NV_CERR_FIRST2_NTL_20                                   , 20  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( NV_CERR_FIRST2_NTL_21                                   , 21  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( NV_CERR_FIRST2_NTL_22                                   , 22  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( NV_CERR_FIRST2_NTL_23                                   , 23  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( NV_CERR_FIRST2_NTL_24                                   , 24  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( NV_CERR_FIRST2_NTL_25                                   , 25  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( NV_CERR_FIRST2_NTL_26                                   , 26  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( NV_CERR_FIRST2_NTL_27                                   , 27  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( NV_CERR_FIRST2_NTL_28                                   , 28  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( NV_CERR_FIRST2_NTL_29                                   , 29  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( NV_CERR_FIRST2_NTL_30                                   , 30  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( NV_CERR_FIRST2_NTL_31                                   , 31  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( NV_CERR_FIRST2_NTL_32                                   , 32  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( NV_CERR_FIRST2_NTL_33                                   , 33  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( NV_CERR_FIRST2_NTL_34                                   , 34  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( NV_CERR_FIRST2_NTL_35                                   , 35  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( NV_CERR_FIRST2_NTL_36                                   , 36  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( NV_CERR_FIRST2_NTL_37                                   , 37  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( NV_CERR_FIRST2_NTL_38                                   , 38  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( NV_CERR_FIRST2_NTL_39                                   , 39  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( NV_CERR_FIRST2_NTL_40                                   , 40  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( NV_CERR_FIRST2_NTL_41                                   , 41  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( NV_CERR_FIRST2_NTL_42                                   , 42  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( NV_CERR_FIRST2_NTL_43                                   , 43  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( NV_CERR_FIRST2_NTL_44                                   , 44  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( NV_CERR_FIRST2_NTL_45                                   , 45  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( NV_CERR_FIRST2_NTL_46                                   , 46  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( NV_CERR_FIRST2_NTL_47                                   , 47  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( NV_CERR_FIRST2_NTL_48                                   , 48  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( NV_CERR_FIRST2_NTL_49                                   , 49  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( NV_CERR_FIRST2_NTL_50                                   , 50  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( NV_CERR_FIRST2_NTL_51                                   , 51  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( NV_CERR_FIRST2_NTL_52                                   , 52  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( NV_CERR_FIRST2_NTL_53                                   , 53  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( NV_CERR_FIRST2_NTL_54                                   , 54  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( NV_CERR_FIRST2_NTL_55                                   , 55  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( NV_CERR_FIRST2_NTL_56                                   , 56  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( NV_CERR_FIRST2_NTL_57                                   , 57  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( NV_CERR_FIRST2_NTL_58                                   , 58  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( NV_CERR_FIRST2_NTL_59                                   , 59  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( NV_CERR_FIRST2_NTL_60                                   , 60  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( NV_CERR_FIRST2_NTL_61                                   , 61  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( NV_CERR_FIRST2_NTL_62                                   , 62  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( NV_CERR_FIRST2_NTL_63                                   , 63  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            , 5   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_8 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            , 9   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_9 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_10 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           , 11  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_11 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_12 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           , 13  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_13 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           , 14  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_14 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           , 15  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_15 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_16 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           , 17  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_17 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_18 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           , 19  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_19 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_20 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           , 21  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_21 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           , 22  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_22 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           , 23  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_23 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_24 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           , 25  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_25 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           , 26  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_26 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           , 27  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_27 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           , 28  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_28 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           , 29  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_29 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           , 30  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_30 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           , 31  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_31 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           , 32  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_32 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           , 33  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_33 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           , 34  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_34 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           , 35  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_35 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           , 36  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_36 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           , 37  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_37 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           , 38  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_38 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           , 39  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_39 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           , 40  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_40 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           , 41  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_41 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           , 42  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_42 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           , 43  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_43 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           , 44  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_44 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           , 45  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_45 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           , 46  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_46 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           , 47  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_47 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           , 48  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_48 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           , 49  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_49 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           , 50  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_50 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           , 51  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_51 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           , 52  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_52 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           , 53  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_53 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           , 54  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_54 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           , 55  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_55 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           , 56  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_56 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           , 57  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_57 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           , 58  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_58 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           , 59  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_59 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           , 60  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_60 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           , 61  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_61 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           , 62  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_62 );
+REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           , 63  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_63 );
+
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0            , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1            , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2            , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3            , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4            , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5            , 5   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6            , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7            , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8            , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_8 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9            , 9   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_9 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10           , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_10 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11           , 11  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_11 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12           , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_12 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13           , 13  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_13 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14           , 14  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_14 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15           , 15  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_15 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16           , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_16 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17           , 17  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_17 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18           , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_18 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19           , 19  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_19 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20           , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_20 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21           , 21  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_21 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22           , 22  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_22 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23           , 23  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_23 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24           , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_24 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25           , 25  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_25 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26           , 26  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_26 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27           , 27  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_27 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28           , 28  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_28 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29           , 29  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_29 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30           , 30  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_30 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31           , 31  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_31 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32           , 32  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_32 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33           , 33  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_33 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34           , 34  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_34 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35           , 35  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_35 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36           , 36  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_36 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37           , 37  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_37 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38           , 38  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_38 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39           , 39  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_39 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40           , 40  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_40 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41           , 41  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_41 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42           , 42  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_42 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43           , 43  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_43 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44           , 44  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_44 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45           , 45  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_45 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46           , 46  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_46 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47           , 47  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_47 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48           , 48  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_48 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49           , 49  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_49 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50           , 50  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_50 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51           , 51  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_51 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52           , 52  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_52 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53           , 53  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_53 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54           , 54  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_54 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55           , 55  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_55 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56           , 56  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_56 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57           , 57  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_57 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58           , 58  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_58 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59           , 59  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_59 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60           , 60  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_60 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61           , 61  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_61 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62           , 62  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_62 );
+REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63           , 63  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_FIRST_NLG_63 );
+
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_0                     , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_1                     , 1   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_2                     , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_3                     , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_4                     , 4   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_5                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_6                     , 6   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_7                     , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_8                     , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_9                     , 9   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_10                    , 10  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_11                    , 11  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_12                    , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_13                    , 13  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_14                    , 14  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_15                    , 15  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_16                    , 16  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_17                    , 17  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_18                    , 18  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_19                    , 19  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_20                    , 20  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_21                    , 21  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_22                    , 22  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_23                    , 23  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_24                    , 24  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_25                    , 25  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_26                    , 26  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_27                    , 27  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_28                    , 28  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_29                    , 29  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_30                    , 30  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_31                    , 31  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_32                    , 32  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_33                    , 33  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_34                    , 34  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_35                    , 35  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_36                    , 36  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_37                    , 37  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_38                    , 38  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_39                    , 39  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_40                    , 40  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_41                    , 41  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_42                    , 42  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_43                    , 43  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_44                    , 44  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_45                    , 45  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_46                    , 46  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_47                    , 47  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_48                    , 48  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_49                    , 49  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_50                    , 50  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_51                    , 51  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_52                    , 52  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_53                    , 53  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_54                    , 54  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_55                    , 55  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_56                    , 56  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_57                    , 57  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_58                    , 58  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_59                    , 59  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_60                    , 60  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_61                    , 61  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_62                    , 62  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_63                    , 63  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_0                               , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_1                               , 1   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_2                               , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_3                               , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_4                               , 4   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_5                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_6                               , 6   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_7                               , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_8                               , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_9                               , 9   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_10                              , 10  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_11                              , 11  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_12                              , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_13                              , 13  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_14                              , 14  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_15                              , 15  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_16                              , 16  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_17                              , 17  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_18                              , 18  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_19                              , 19  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_20                              , 20  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_21                              , 21  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_22                              , 22  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_23                              , 23  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_24                              , 24  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_25                              , 25  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_26                              , 26  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_27                              , 27  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_28                              , 28  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_29                              , 29  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_30                              , 30  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_31                              , 31  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_32                              , 32  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_33                              , 33  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_34                              , 34  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_35                              , 35  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_36                              , 36  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_37                              , 37  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_38                              , 38  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_39                              , 39  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_40                              , 40  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_41                              , 41  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_42                              , 42  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_43                              , 43  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_44                              , 44  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_45                              , 45  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_46                              , 46  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_47                              , 47  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_48                              , 48  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_49                              , 49  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_50                              , 50  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_51                              , 51  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_52                              , 52  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_53                              , 53  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_54                              , 54  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_55                              , 55  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_56                              , 56  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_57                              , 57  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_58                              , 58  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_59                              , 59  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_60                              , 60  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_61                              , 61  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_62                              , 62  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( NV_CERR_FIRST_MASK1_NTL_63                              , 63  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_0                     , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_1                     , 1   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_2                     , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_3                     , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_4                     , 4   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_5                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_6                     , 6   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_7                     , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_8                     , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_9                     , 9   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_10                    , 10  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_11                    , 11  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_12                    , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_13                    , 13  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_14                    , 14  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_15                    , 15  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_16                    , 16  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_17                    , 17  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_18                    , 18  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_19                    , 19  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_20                    , 20  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_21                    , 21  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_22                    , 22  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_23                    , 23  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_24                    , 24  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_25                    , 25  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_26                    , 26  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_27                    , 27  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_28                    , 28  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_29                    , 29  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_30                    , 30  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_31                    , 31  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_32                    , 32  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_33                    , 33  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_34                    , 34  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_35                    , 35  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_36                    , 36  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_37                    , 37  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_38                    , 38  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_39                    , 39  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_40                    , 40  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_41                    , 41  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_42                    , 42  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_43                    , 43  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_44                    , 44  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_45                    , 45  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_46                    , 46  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_47                    , 47  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_48                    , 48  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_49                    , 49  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_50                    , 50  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_51                    , 51  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_52                    , 52  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_53                    , 53  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_54                    , 54  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_55                    , 55  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_56                    , 56  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_57                    , 57  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_58                    , 58  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_59                    , 59  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_60                    , 60  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_61                    , 61  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_62                    , 62  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_63                    , 63  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_0                     , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_1                     , 1   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_2                     , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_3                     , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_4                     , 4   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_5                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_6                     , 6   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_7                     , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_8                     , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_9                     , 9   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_10                    , 10  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_11                    , 11  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_12                    , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_13                    , 13  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_14                    , 14  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_15                    , 15  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_16                    , 16  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_17                    , 17  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_18                    , 18  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_19                    , 19  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_20                    , 20  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_21                    , 21  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_22                    , 22  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_23                    , 23  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_24                    , 24  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_25                    , 25  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_26                    , 26  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_27                    , 27  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_28                    , 28  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_29                    , 29  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_30                    , 30  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_31                    , 31  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_32                    , 32  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_33                    , 33  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_34                    , 34  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_35                    , 35  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_36                    , 36  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_37                    , 37  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_38                    , 38  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_39                    , 39  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_40                    , 40  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_41                    , 41  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_42                    , 42  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_43                    , 43  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_44                    , 44  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_45                    , 45  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_46                    , 46  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_47                    , 47  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_48                    , 48  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_49                    , 49  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_50                    , 50  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_51                    , 51  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_52                    , 52  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_53                    , 53  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_54                    , 54  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_55                    , 55  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_56                    , 56  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_57                    , 57  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_58                    , 58  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_59                    , 59  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_60                    , 60  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_61                    , 61  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_62                    , 62  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_63                    , 63  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_0                               , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_1                               , 1   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_2                               , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_3                               , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_4                               , 4   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_5                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_6                               , 6   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_7                               , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_8                               , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_9                               , 9   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_10                              , 10  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_11                              , 11  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_12                              , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_13                              , 13  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_14                              , 14  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_15                              , 15  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_16                              , 16  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_17                              , 17  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_18                              , 18  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_19                              , 19  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_20                              , 20  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_21                              , 21  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_22                              , 22  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_23                              , 23  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_24                              , 24  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_25                              , 25  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_26                              , 26  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_27                              , 27  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_28                              , 28  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_29                              , 29  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_30                              , 30  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_31                              , 31  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_32                              , 32  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_33                              , 33  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_34                              , 34  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_35                              , 35  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_36                              , 36  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_37                              , 37  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_38                              , 38  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_39                              , 39  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_40                              , 40  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_41                              , 41  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_42                              , 42  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_43                              , 43  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_44                              , 44  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_45                              , 45  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_46                              , 46  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_47                              , 47  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_48                              , 48  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_49                              , 49  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_50                              , 50  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_51                              , 51  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_52                              , 52  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_53                              , 53  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_54                              , 54  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_55                              , 55  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_56                              , 56  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_57                              , 57  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_58                              , 58  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_59                              , 59  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_60                              , 60  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_61                              , 61  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_62                              , 62  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( NV_CERR_FIRST_MASK2_NTL_63                              , 63  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_0                     , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_1                     , 1   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_2                     , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_3                     , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_4                     , 4   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_5                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_6                     , 6   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_7                     , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_8                     , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_9                     , 9   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_10                    , 10  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_11                    , 11  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_12                    , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_13                    , 13  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_14                    , 14  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_15                    , 15  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_16                    , 16  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_17                    , 17  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_18                    , 18  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_19                    , 19  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_20                    , 20  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_21                    , 21  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_22                    , 22  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_23                    , 23  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_24                    , 24  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_25                    , 25  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_26                    , 26  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_27                    , 27  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_28                    , 28  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_29                    , 29  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_30                    , 30  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_31                    , 31  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_32                    , 32  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_33                    , 33  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_34                    , 34  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_35                    , 35  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_36                    , 36  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_37                    , 37  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_38                    , 38  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_39                    , 39  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_40                    , 40  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_41                    , 41  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_42                    , 42  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_43                    , 43  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_44                    , 44  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_45                    , 45  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_46                    , 46  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_47                    , 47  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_48                    , 48  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_49                    , 49  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_50                    , 50  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_51                    , 51  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_52                    , 52  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_53                    , 53  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_54                    , 54  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_55                    , 55  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_56                    , 56  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_57                    , 57  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_58                    , 58  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_59                    , 59  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_60                    , 60  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_61                    , 61  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_62                    , 62  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_63                    , 63  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              , 5   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_8 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              , 9   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_9 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_10 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             , 11  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_11 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_12 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             , 13  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_13 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             , 14  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_14 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             , 15  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_15 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_16 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             , 17  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_17 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_18 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             , 19  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_19 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_20 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             , 21  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_21 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             , 22  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_22 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             , 23  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_23 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24             , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_24 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25             , 25  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_25 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26             , 26  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_26 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27             , 27  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_27 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28             , 28  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_28 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29             , 29  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_29 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30             , 30  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_30 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31             , 31  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_31 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              , 32  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              , 33  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              , 34  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              , 35  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              , 36  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              , 37  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              , 38  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              , 39  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             , 40  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             , 41  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             , 42  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             , 43  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              , 44  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              , 45  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              , 46  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              , 47  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              , 48  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              , 49  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              , 50  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              , 51  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              , 52  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              , 53  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              , 54  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              , 55  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_3 );
+
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              , 5   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_8 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              , 9   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_9 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_10 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             , 11  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_11 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_12 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             , 13  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_13 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             , 14  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_14 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             , 15  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_15 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_16 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             , 17  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_17 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_18 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             , 19  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_19 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_20 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             , 21  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_21 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             , 22  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_22 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             , 23  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_23 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24             , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_24 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25             , 25  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_25 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26             , 26  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_26 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27             , 27  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_27 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28             , 28  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_28 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29             , 29  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_29 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30             , 30  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_30 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31             , 31  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_31 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              , 32  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              , 33  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              , 34  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              , 35  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              , 36  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              , 37  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              , 38  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              , 39  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             , 40  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             , 41  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             , 42  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             , 43  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              , 44  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              , 45  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              , 46  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              , 47  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              , 48  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              , 49  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              , 50  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              , 51  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              , 52  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              , 53  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              , 54  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              , 55  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_3 );
+
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              , 5   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_8 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              , 9   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_9 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_10 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             , 11  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_11 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_12 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             , 13  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_13 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             , 14  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_14 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             , 15  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_15 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_16 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             , 17  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_17 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_18 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             , 19  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_19 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_20 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             , 21  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_21 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             , 22  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_22 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             , 23  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_23 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24             , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_24 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25             , 25  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_25 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26             , 26  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_26 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27             , 27  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_27 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28             , 28  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_28 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29             , 29  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_29 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30             , 30  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_30 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31             , 31  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_31 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              , 32  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              , 33  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              , 34  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              , 35  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              , 36  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              , 37  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              , 38  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              , 39  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             , 40  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             , 41  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             , 42  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             , 43  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              , 44  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              , 45  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              , 46  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              , 47  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              , 48  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              , 49  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              , 50  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              , 51  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              , 52  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              , 53  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              , 54  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              , 55  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_3 );
+
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              , 5   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_8 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              , 9   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_9 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_10 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             , 11  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_11 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_12 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             , 13  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_13 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             , 14  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_14 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             , 15  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_15 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_16 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             , 17  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_17 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_18 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             , 19  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_19 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_20 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             , 21  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_21 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             , 22  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_22 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             , 23  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_23 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24             , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_24 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25             , 25  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_25 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26             , 26  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_26 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27             , 27  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_27 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28             , 28  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_28 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29             , 29  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_29 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30             , 30  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_30 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31             , 31  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_31 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              , 32  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              , 33  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              , 34  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              , 35  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              , 36  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              , 37  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              , 38  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              , 39  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             , 40  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             , 41  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             , 42  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             , 43  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              , 44  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              , 45  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              , 46  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              , 47  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              , 48  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              , 49  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              , 50  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              , 51  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              , 52  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              , 53  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              , 54  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              , 55  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_3 );
+
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              , 5   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_8 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              , 9   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_9 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_10 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             , 11  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_11 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_12 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             , 13  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_13 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             , 14  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_14 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             , 15  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_15 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_16 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             , 17  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_17 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_18 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             , 19  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_19 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_20 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             , 21  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_21 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             , 22  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_22 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             , 23  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_23 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24             , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_24 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25             , 25  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_25 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26             , 26  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_26 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27             , 27  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_27 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28             , 28  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_28 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29             , 29  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_29 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30             , 30  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_30 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31             , 31  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_31 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              , 32  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              , 33  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              , 34  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              , 35  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              , 36  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              , 37  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              , 38  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              , 39  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             , 40  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             , 41  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             , 42  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             , 43  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              , 44  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              , 45  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              , 46  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              , 47  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              , 48  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              , 49  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              , 50  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              , 51  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              , 52  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              , 53  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              , 54  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              , 55  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_3 );
+
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              , 5   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_8 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              , 9   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_9 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_10 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             , 11  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_11 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_12 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             , 13  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_13 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             , 14  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_14 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             , 15  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_15 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_16 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             , 17  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_17 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_18 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             , 19  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_19 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_20 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             , 21  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_21 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             , 22  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_22 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             , 23  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_23 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24             , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_24 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25             , 25  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_25 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26             , 26  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_26 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27             , 27  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_27 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28             , 28  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_28 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29             , 29  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_29 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30             , 30  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_30 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31             , 31  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_31 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              , 32  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              , 33  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              , 34  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              , 35  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              , 36  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              , 37  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              , 38  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              , 39  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             , 40  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             , 41  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             , 42  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             , 43  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              , 44  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              , 45  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              , 46  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              , 47  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              , 48  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              , 49  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              , 50  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              , 51  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              , 52  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              , 53  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              , 54  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              , 55  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_3 );
+
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              , 5   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_8 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              , 9   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_9 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_10 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             , 11  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_11 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_12 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             , 13  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_13 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             , 14  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_14 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             , 15  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_15 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_16 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             , 17  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_17 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_18 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             , 19  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_19 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_20 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             , 21  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_21 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             , 22  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_22 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             , 23  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_23 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24             , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_24 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25             , 25  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_25 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26             , 26  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_26 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27             , 27  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_27 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28             , 28  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_28 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29             , 29  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_29 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30             , 30  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_30 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31             , 31  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_31 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              , 32  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              , 33  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              , 34  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              , 35  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              , 36  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              , 37  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              , 38  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              , 39  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             , 40  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             , 41  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             , 42  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             , 43  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              , 44  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              , 45  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              , 46  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              , 47  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              , 48  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              , 49  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              , 50  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              , 51  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              , 52  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              , 53  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              , 54  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              , 55  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_3 );
+
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_0             , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_1             , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_2             , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_3             , 3   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_4             , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_5             , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_6             , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_7             , 7   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_0             , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_1             , 9   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_2             , 10  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_3             , 11  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_4             , 12  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_5             , 13  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_6             , 14  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_7             , 15  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_8             , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_8 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_9             , 17  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_9 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_10            , 18  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_10 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_11            , 19  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_11 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_12            , 20  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_12 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_13            , 21  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_13 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_14            , 22  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_14 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_15            , 23  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_15 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_16            , 24  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_16 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_17            , 25  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_17 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_18            , 26  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_18 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_19            , 27  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_19 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_20            , 28  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_20 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_21            , 29  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_21 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_22            , 30  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_22 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_23            , 31  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_23 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_0            , 32  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV1_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_1            , 33  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV1_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_2            , 34  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV1_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_3            , 35  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV1_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_0            , 36  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_1            , 37  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_2            , 38  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_3            , 39  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_4            , 40  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_5            , 41  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_6            , 42  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_7            , 43  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_0             , 44  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_1             , 45  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_2             , 46  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_3             , 47  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_4             , 48  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_5             , 49  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_6             , 50  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_7             , 51  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_0             , 52  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_REG_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_1             , 53  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_REG_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_2             , 54  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_REG_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_3             , 55  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_REG_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_0             , 56  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_DUE_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_1             , 57  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_DUE_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_2             , 58  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_DUE_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_3             , 59  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_DUE_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_0             , 60  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PEF_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_1             , 61  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PEF_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_2             , 62  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PEF_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_3             , 63  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PEF_3 );
+
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              , 5   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_8 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              , 9   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_9 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_10 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             , 11  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_11 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_12 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             , 13  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_13 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             , 14  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_14 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             , 15  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_15 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_16 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             , 17  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_17 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_18 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             , 19  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_19 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_20 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             , 21  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_21 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             , 22  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_22 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             , 23  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_23 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24             , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_24 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25             , 25  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_25 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26             , 26  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_26 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27             , 27  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_27 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28             , 28  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_28 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29             , 29  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_29 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30             , 30  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_30 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31             , 31  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_31 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              , 32  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              , 33  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              , 34  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              , 35  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              , 36  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              , 37  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              , 38  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              , 39  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             , 40  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             , 41  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             , 42  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             , 43  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              , 44  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              , 45  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              , 46  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              , 47  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              , 48  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              , 49  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              , 50  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              , 51  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              , 52  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              , 53  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              , 54  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              , 55  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_3 );
+
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              , 5   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_8 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              , 9   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_9 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_10 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             , 11  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_11 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_12 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             , 13  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_13 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             , 14  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_14 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             , 15  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_15 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_16 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             , 17  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_17 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_18 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             , 19  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_19 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_20 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             , 21  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_21 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             , 22  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_22 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             , 23  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_23 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24             , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_24 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25             , 25  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_25 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26             , 26  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_26 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27             , 27  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_27 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28             , 28  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_28 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29             , 29  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_29 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30             , 30  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_30 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31             , 31  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_31 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              , 32  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              , 33  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              , 34  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              , 35  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              , 36  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              , 37  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              , 38  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              , 39  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             , 40  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             , 41  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             , 42  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             , 43  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              , 44  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              , 45  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              , 46  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              , 47  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              , 48  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              , 49  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              , 50  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              , 51  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              , 52  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              , 53  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              , 54  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              , 55  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_3 );
+
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              , 5   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_8 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              , 9   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_9 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_10 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             , 11  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_11 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_12 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             , 13  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_13 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             , 14  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_14 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             , 15  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_15 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_16 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             , 17  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_17 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_18 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             , 19  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_19 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_20 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             , 21  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_21 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             , 22  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_22 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             , 23  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_23 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24             , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_24 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25             , 25  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_25 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26             , 26  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_26 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27             , 27  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_27 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28             , 28  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_28 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29             , 29  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_29 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30             , 30  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_30 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31             , 31  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_31 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              , 32  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              , 33  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              , 34  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              , 35  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              , 36  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              , 37  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              , 38  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              , 39  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             , 40  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             , 41  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             , 42  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             , 43  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              , 44  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              , 45  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              , 46  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              , 47  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              , 48  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              , 49  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              , 50  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              , 51  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              , 52  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              , 53  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              , 54  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              , 55  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_3 );
+
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_0             , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_1             , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_2             , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_3             , 3   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_4             , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_5             , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_6             , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_7             , 7   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_0             , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_1             , 9   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_2             , 10  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_3             , 11  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_4             , 12  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_5             , 13  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_6             , 14  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_7             , 15  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_8             , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_8 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_9             , 17  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_9 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_10            , 18  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_10 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_11            , 19  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_11 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_12            , 20  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_12 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_13            , 21  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_13 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_14            , 22  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_14 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_15            , 23  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_15 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_16            , 24  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_16 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_17            , 25  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_17 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_18            , 26  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_18 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_19            , 27  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_19 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_20            , 28  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_20 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_21            , 29  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_21 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_22            , 30  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_22 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_23            , 31  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_23 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_0            , 32  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV1_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_1            , 33  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV1_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_2            , 34  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV1_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_3            , 35  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV1_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_0            , 36  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_1            , 37  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_2            , 38  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_3            , 39  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_4            , 40  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_5            , 41  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_6            , 42  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_7            , 43  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_0             , 44  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_1             , 45  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_2             , 46  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_3             , 47  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_4             , 48  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_5             , 49  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_6             , 50  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_7             , 51  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_0             , 52  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_REG_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_1             , 53  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_REG_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_2             , 54  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_REG_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_3             , 55  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_REG_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_0             , 56  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_DUE_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_1             , 57  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_DUE_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_2             , 58  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_DUE_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_3             , 59  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_DUE_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_0             , 60  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PEF_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_1             , 61  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PEF_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_2             , 62  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PEF_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_3             , 63  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PEF_3 );
+
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_0             , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_1             , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_2             , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_3             , 3   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_4             , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_5             , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_6             , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_7             , 7   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NCF_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_0             , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_1             , 9   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_2             , 10  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_3             , 11  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_4             , 12  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_5             , 13  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_6             , 14  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_7             , 15  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_8             , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_8 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_9             , 17  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_9 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_10            , 18  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_10 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_11            , 19  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_11 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_12            , 20  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_12 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_13            , 21  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_13 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_14            , 22  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_14 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_15            , 23  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_15 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_16            , 24  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_16 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_17            , 25  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_17 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_18            , 26  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_18 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_19            , 27  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_19 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_20            , 28  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_20 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_21            , 29  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_21 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_22            , 30  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_22 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_23            , 31  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NVF_23 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_0            , 32  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV1_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_1            , 33  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV1_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_2            , 34  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV1_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_3            , 35  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV1_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_0            , 36  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_1            , 37  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_2            , 38  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_3            , 39  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_4            , 40  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_5            , 41  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_6            , 42  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_7            , 43  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_ASBE_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_0             , 44  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_1             , 45  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_2             , 46  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_3             , 47  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_4             , 48  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_5             , 49  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_6             , 50  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_7             , 51  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBR_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_0             , 52  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_REG_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_1             , 53  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_REG_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_2             , 54  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_REG_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_3             , 55  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_REG_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_0             , 56  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_DUE_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_1             , 57  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_DUE_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_2             , 58  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_DUE_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_3             , 59  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_DUE_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_0             , 60  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PEF_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_1             , 61  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PEF_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_2             , 62  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PEF_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_3             , 63  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PEF_3 );
+
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              , 5   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_8 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              , 9   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_9 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_10 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             , 11  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_11 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_12 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             , 13  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_13 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             , 14  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_14 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             , 15  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_15 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_16 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             , 17  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_17 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_18 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             , 19  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_19 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_20 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             , 21  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_21 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             , 22  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_22 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             , 23  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_23 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24             , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_24 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25             , 25  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_25 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26             , 26  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_26 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27             , 27  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_27 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28             , 28  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_28 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29             , 29  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_29 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30             , 30  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_30 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31             , 31  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_31 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              , 32  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              , 33  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              , 34  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              , 35  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              , 36  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              , 37  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              , 38  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              , 39  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             , 40  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             , 41  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             , 42  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             , 43  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              , 44  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              , 45  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              , 46  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              , 47  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              , 48  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              , 49  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              , 50  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              , 51  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              , 52  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              , 53  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              , 54  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              , 55  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_3 );
+
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0              , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1              , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2              , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3              , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4              , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5              , 5   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6              , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7              , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8              , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_8 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9              , 9   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_9 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10             , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_10 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11             , 11  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_11 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12             , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_12 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13             , 13  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_13 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14             , 14  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_14 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15             , 15  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_15 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16             , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_16 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17             , 17  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_17 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18             , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_18 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19             , 19  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_19 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20             , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_20 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21             , 21  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_21 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22             , 22  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_22 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23             , 23  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_23 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24             , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_24 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25             , 25  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_25 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26             , 26  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_26 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27             , 27  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_27 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28             , 28  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_28 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29             , 29  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_29 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30             , 30  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_30 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31             , 31  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NVF_31 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0              , 32  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1              , 33  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2              , 34  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3              , 35  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4              , 36  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5              , 37  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6              , 38  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7              , 39  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NCF_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0             , 40  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1             , 41  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2             , 42  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3             , 43  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_ASBE_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0              , 44  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1              , 45  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2              , 46  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3              , 47  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4              , 48  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5              , 49  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6              , 50  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7              , 51  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBR_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0              , 52  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1              , 53  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2              , 54  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3              , 55  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_REG_3 );
+
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             , 5   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_8 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             , 9   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_9 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_10 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            , 11  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_11 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_12 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            , 13  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_13 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            , 14  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_14 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            , 15  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_15 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              , 17  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              , 19  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              , 21  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              , 22  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              , 23  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              , 25  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              , 26  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              , 27  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              , 28  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              , 29  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              , 30  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              , 31  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              , 32  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              , 33  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              , 34  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              , 35  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              , 36  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              , 37  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              , 38  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              , 39  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              , 40  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_8 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              , 41  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_9 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             , 42  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_10 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             , 43  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_11 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              , 44  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              , 45  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              , 46  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              , 47  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              , 48  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              , 49  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              , 50  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              , 51  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              , 52  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_8 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              , 53  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_9 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             , 54  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_10 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             , 55  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_11 );
+
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             , 5   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_8 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             , 9   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_9 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_10 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            , 11  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_11 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_12 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            , 13  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_13 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            , 14  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_14 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            , 15  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_15 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              , 17  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              , 19  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              , 21  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              , 22  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              , 23  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              , 25  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              , 26  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              , 27  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              , 28  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              , 29  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              , 30  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              , 31  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              , 32  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              , 33  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              , 34  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              , 35  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              , 36  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              , 37  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              , 38  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              , 39  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              , 40  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_8 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              , 41  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_9 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             , 42  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_10 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             , 43  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_11 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              , 44  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              , 45  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              , 46  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              , 47  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              , 48  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              , 49  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              , 50  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              , 51  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              , 52  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_8 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              , 53  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_9 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             , 54  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_10 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             , 55  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_11 );
+
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_0                           , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_1                           , 1   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_2                           , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_3                           , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_4                           , 4   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_5                           , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_6                           , 6   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_7                           , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_8                           , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_9                           , 9   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_10                          , 10  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_11                          , 11  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_12                          , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_13                          , 13  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_14                          , 14  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_15                          , 15  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_16                          , 16  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_17                          , 17  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_18                          , 18  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_19                          , 19  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_20                          , 20  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_21                          , 21  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_22                          , 22  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_23                          , 23  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_24                          , 24  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_25                          , 25  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_26                          , 26  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_27                          , 27  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_28                          , 28  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_29                          , 29  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_30                          , 30  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_31                          , 31  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_32                          , 32  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_33                          , 33  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_34                          , 34  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_35                          , 35  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_36                          , 36  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_37                          , 37  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_38                          , 38  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_39                          , 39  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_40                          , 40  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_41                          , 41  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_42                          , 42  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_43                          , 43  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_44                          , 44  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_45                          , 45  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_46                          , 46  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_47                          , 47  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_48                          , 48  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_49                          , 49  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_50                          , 50  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_51                          , 51  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_52                          , 52  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_53                          , 53  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_54                          , 54  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_55                          , 55  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_56                          , 56  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_57                          , 57  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_58                          , 58  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_59                          , 59  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_60                          , 60  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_61                          , 61  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_62                          , 62  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_63                          , 63  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             , 5   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_8 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             , 9   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_9 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_10 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            , 11  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_11 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_12 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            , 13  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_13 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            , 14  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_14 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            , 15  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_15 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              , 17  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              , 19  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              , 21  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              , 22  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              , 23  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              , 25  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              , 26  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              , 27  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              , 28  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              , 29  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              , 30  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              , 31  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              , 32  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              , 33  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              , 34  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              , 35  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              , 36  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              , 37  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              , 38  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              , 39  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              , 40  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_8 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              , 41  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_9 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             , 42  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_10 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             , 43  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_11 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              , 44  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              , 45  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              , 46  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              , 47  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              , 48  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              , 49  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              , 50  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              , 51  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              , 52  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_8 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              , 53  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_9 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             , 54  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_10 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             , 55  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_11 );
+
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             , 5   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_8 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             , 9   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_9 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_10 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            , 11  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_11 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_12 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            , 13  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_13 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            , 14  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_14 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            , 15  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_15 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              , 17  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              , 19  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              , 21  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              , 22  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              , 23  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              , 25  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              , 26  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              , 27  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              , 28  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              , 29  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              , 30  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              , 31  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              , 32  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              , 33  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              , 34  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              , 35  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              , 36  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              , 37  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              , 38  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              , 39  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              , 40  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_8 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              , 41  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_9 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             , 42  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_10 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             , 43  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_11 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              , 44  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              , 45  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              , 46  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              , 47  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              , 48  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              , 49  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              , 50  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              , 51  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              , 52  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_8 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              , 53  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_9 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             , 54  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_10 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             , 55  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_11 );
+
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_0             , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_1             , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_2             , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_3             , 3   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_4             , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_5             , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_6             , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_7             , 7   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_8             , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_8 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_9             , 9   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_9 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_10            , 10  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_10 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_11            , 11  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_11 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_12            , 12  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_12 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_13            , 13  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_13 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_14            , 14  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_14 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_15            , 15  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_15 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_0             , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_1             , 17  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_2             , 18  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_3             , 19  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_4             , 20  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_5             , 21  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_6             , 22  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_7             , 23  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_0             , 24  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_1             , 25  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_2             , 26  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_3             , 27  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_4             , 28  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_5             , 29  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_6             , 30  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_7             , 31  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_0             , 32  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_1             , 33  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_2             , 34  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_3             , 35  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_4             , 36  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_5             , 37  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_6             , 38  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_7             , 39  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_0             , 40  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_1             , 41  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_2             , 42  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_3             , 43  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_4             , 44  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_5             , 45  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_6             , 46  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_7             , 47  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_0             , 48  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_1             , 49  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_2             , 50  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_3             , 51  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_4             , 52  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_5             , 53  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_6             , 54  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_7             , 55  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_0            , 56  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV2_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_1            , 57  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV2_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_2            , 58  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV2_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_3            , 59  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV2_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_0            , 60  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV3_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_1            , 61  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV3_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_2            , 62  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV3_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_3            , 63  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV3_3 );
+
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             , 5   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_8 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             , 9   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_9 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_10 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            , 11  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_11 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_12 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            , 13  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_13 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            , 14  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_14 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            , 15  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_15 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              , 17  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              , 19  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              , 21  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              , 22  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              , 23  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              , 25  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              , 26  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              , 27  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              , 28  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              , 29  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              , 30  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              , 31  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              , 32  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              , 33  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              , 34  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              , 35  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              , 36  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              , 37  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              , 38  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              , 39  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              , 40  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_8 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              , 41  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_9 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             , 42  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_10 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             , 43  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_11 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              , 44  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              , 45  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              , 46  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              , 47  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              , 48  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              , 49  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              , 50  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              , 51  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              , 52  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_8 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              , 53  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_9 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             , 54  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_10 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             , 55  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_11 );
+
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             , 5   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_8 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             , 9   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_9 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_10 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            , 11  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_11 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_12 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            , 13  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_13 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            , 14  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_14 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            , 15  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_15 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              , 17  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              , 19  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              , 21  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              , 22  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              , 23  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              , 25  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              , 26  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              , 27  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              , 28  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              , 29  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              , 30  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              , 31  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              , 32  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              , 33  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              , 34  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              , 35  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              , 36  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              , 37  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              , 38  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              , 39  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              , 40  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_8 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              , 41  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_9 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             , 42  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_10 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             , 43  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_11 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              , 44  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              , 45  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              , 46  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              , 47  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              , 48  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              , 49  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              , 50  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              , 51  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              , 52  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_8 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              , 53  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_9 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             , 54  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_10 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             , 55  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_11 );
+
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_0                           , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_1                           , 1   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_2                           , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_3                           , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_4                           , 4   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_5                           , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_6                           , 6   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_7                           , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_8                           , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_9                           , 9   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_10                          , 10  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_11                          , 11  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_12                          , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_13                          , 13  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_14                          , 14  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_15                          , 15  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_16                          , 16  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_17                          , 17  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_18                          , 18  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_19                          , 19  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_20                          , 20  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_21                          , 21  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_22                          , 22  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_23                          , 23  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_24                          , 24  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_25                          , 25  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_26                          , 26  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_27                          , 27  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_28                          , 28  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_29                          , 29  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_30                          , 30  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_31                          , 31  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_32                          , 32  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_33                          , 33  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_34                          , 34  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_35                          , 35  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_36                          , 36  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_37                          , 37  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_38                          , 38  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_39                          , 39  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_40                          , 40  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_41                          , 41  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_42                          , 42  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_43                          , 43  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_44                          , 44  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_45                          , 45  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_46                          , 46  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_47                          , 47  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_48                          , 48  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_49                          , 49  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_50                          , 50  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_51                          , 51  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_52                          , 52  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_53                          , 53  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_54                          , 54  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_55                          , 55  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_56                          , 56  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_57                          , 57  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_58                          , 58  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_59                          , 59  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_60                          , 60  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_61                          , 61  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_62                          , 62  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_63                          , 63  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             , 5   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_8 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             , 9   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_9 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_10 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            , 11  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_11 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_12 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            , 13  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_13 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            , 14  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_14 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            , 15  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_15 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              , 17  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              , 19  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              , 21  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              , 22  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              , 23  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              , 25  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              , 26  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              , 27  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              , 28  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              , 29  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              , 30  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              , 31  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              , 32  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              , 33  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              , 34  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              , 35  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              , 36  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              , 37  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              , 38  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              , 39  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              , 40  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_8 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              , 41  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_9 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             , 42  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_10 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             , 43  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_11 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              , 44  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              , 45  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              , 46  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              , 47  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              , 48  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              , 49  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              , 50  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              , 51  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              , 52  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_8 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              , 53  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_9 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             , 54  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_10 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             , 55  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_11 );
+
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             , 5   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_8 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             , 9   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_9 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_10 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            , 11  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_11 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_12 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            , 13  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_13 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            , 14  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_14 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            , 15  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_15 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              , 17  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              , 19  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              , 21  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              , 22  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              , 23  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              , 25  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              , 26  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              , 27  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              , 28  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              , 29  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              , 30  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              , 31  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              , 32  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              , 33  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              , 34  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              , 35  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              , 36  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              , 37  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              , 38  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              , 39  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              , 40  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_8 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              , 41  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_9 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             , 42  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_10 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             , 43  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_11 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              , 44  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              , 45  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              , 46  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              , 47  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              , 48  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              , 49  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              , 50  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              , 51  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              , 52  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_8 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              , 53  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_9 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             , 54  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_10 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             , 55  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_11 );
+
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             , 5   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_8 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             , 9   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_9 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_10 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            , 11  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_11 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_12 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            , 13  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_13 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            , 14  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_14 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            , 15  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_15 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              , 17  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              , 19  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              , 21  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              , 22  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              , 23  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              , 25  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              , 26  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              , 27  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              , 28  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              , 29  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              , 30  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              , 31  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              , 32  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              , 33  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              , 34  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              , 35  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              , 36  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              , 37  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              , 38  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              , 39  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              , 40  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_8 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              , 41  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_9 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             , 42  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_10 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             , 43  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_11 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              , 44  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              , 45  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              , 46  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              , 47  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              , 48  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              , 49  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              , 50  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              , 51  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              , 52  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_8 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              , 53  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_9 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             , 54  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_10 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             , 55  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_11 );
+
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_0             , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_1             , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_2             , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_3             , 3   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_4             , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_5             , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_6             , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_7             , 7   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_8             , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_8 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_9             , 9   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_9 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_10            , 10  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_10 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_11            , 11  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_11 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_12            , 12  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_12 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_13            , 13  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_13 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_14            , 14  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_14 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_15            , 15  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_15 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_0             , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_1             , 17  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_2             , 18  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_3             , 19  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_4             , 20  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_5             , 21  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_6             , 22  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_7             , 23  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_0             , 24  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_1             , 25  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_2             , 26  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_3             , 27  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_4             , 28  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_5             , 29  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_6             , 30  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_7             , 31  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_0             , 32  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_1             , 33  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_2             , 34  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_3             , 35  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_4             , 36  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_5             , 37  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_6             , 38  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_7             , 39  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_0             , 40  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_1             , 41  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_2             , 42  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_3             , 43  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_4             , 44  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_5             , 45  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_6             , 46  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_7             , 47  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_0             , 48  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_1             , 49  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_2             , 50  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_3             , 51  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_4             , 52  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_5             , 53  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_6             , 54  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_7             , 55  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_0            , 56  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV2_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_1            , 57  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV2_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_2            , 58  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV2_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_3            , 59  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV2_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_0            , 60  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV3_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_1            , 61  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV3_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_2            , 62  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV3_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_3            , 63  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV3_3 );
+
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             , 5   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_8 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             , 9   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_9 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_10 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            , 11  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_11 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_12 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            , 13  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_13 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            , 14  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_14 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            , 15  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_15 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              , 17  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              , 19  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              , 21  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              , 22  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              , 23  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              , 25  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              , 26  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              , 27  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              , 28  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              , 29  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              , 30  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              , 31  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              , 32  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              , 33  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              , 34  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              , 35  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              , 36  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              , 37  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              , 38  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              , 39  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              , 40  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_8 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              , 41  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_9 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             , 42  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_10 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             , 43  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_11 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              , 44  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              , 45  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              , 46  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              , 47  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              , 48  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              , 49  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              , 50  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              , 51  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              , 52  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_8 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              , 53  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_9 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             , 54  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_10 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             , 55  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_11 );
+
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             , 5   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_8 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             , 9   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_9 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_10 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            , 11  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_11 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_12 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            , 13  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_13 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            , 14  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_14 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            , 15  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_15 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              , 17  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              , 19  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              , 21  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              , 22  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              , 23  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              , 25  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              , 26  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              , 27  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              , 28  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              , 29  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              , 30  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              , 31  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              , 32  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              , 33  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              , 34  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              , 35  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              , 36  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              , 37  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              , 38  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              , 39  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              , 40  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_8 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              , 41  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_9 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             , 42  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_10 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             , 43  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_11 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              , 44  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              , 45  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              , 46  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              , 47  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              , 48  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              , 49  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              , 50  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              , 51  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              , 52  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_8 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              , 53  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_9 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             , 54  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_10 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             , 55  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_11 );
+
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_0             , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_1             , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_2             , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_3             , 3   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_4             , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_5             , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_6             , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_7             , 7   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_8             , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_8 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_9             , 9   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_9 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_10            , 10  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_10 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_11            , 11  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_11 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_12            , 12  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_12 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_13            , 13  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_13 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_14            , 14  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_14 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_15            , 15  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_NLG_15 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_0             , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_1             , 17  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_2             , 18  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_3             , 19  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_4             , 20  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_5             , 21  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_6             , 22  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_7             , 23  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_FWD_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_0             , 24  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_1             , 25  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_2             , 26  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_3             , 27  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_4             , 28  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_5             , 29  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_6             , 30  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_7             , 31  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_AUE_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_0             , 32  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_1             , 33  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_2             , 34  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_3             , 35  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_4             , 36  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_5             , 37  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_6             , 38  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_7             , 39  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBP_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_0             , 40  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_1             , 41  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_2             , 42  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_3             , 43  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_4             , 44  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_5             , 45  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_6             , 46  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_7             , 47  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBF_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_0             , 48  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_1             , 49  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_2             , 50  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_3             , 51  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_4             , 52  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_5             , 53  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_6             , 54  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_7             , 55  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_PBC_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_0            , 56  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV2_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_1            , 57  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV2_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_2            , 58  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV2_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_3            , 59  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV2_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_0            , 60  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV3_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_1            , 61  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV3_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_2            , 62  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV3_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_3            , 63  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_HOLD_RSV3_3 );
+
+REG64_FLD( NV_CERR_HOLD1_NTL_0                                     , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( NV_CERR_HOLD1_NTL_1                                     , 1   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( NV_CERR_HOLD1_NTL_2                                     , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( NV_CERR_HOLD1_NTL_3                                     , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( NV_CERR_HOLD1_NTL_4                                     , 4   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( NV_CERR_HOLD1_NTL_5                                     , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( NV_CERR_HOLD1_NTL_6                                     , 6   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( NV_CERR_HOLD1_NTL_7                                     , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( NV_CERR_HOLD1_NTL_8                                     , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( NV_CERR_HOLD1_NTL_9                                     , 9   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( NV_CERR_HOLD1_NTL_10                                    , 10  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( NV_CERR_HOLD1_NTL_11                                    , 11  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( NV_CERR_HOLD1_NTL_12                                    , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( NV_CERR_HOLD1_NTL_13                                    , 13  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( NV_CERR_HOLD1_NTL_14                                    , 14  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( NV_CERR_HOLD1_NTL_15                                    , 15  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( NV_CERR_HOLD1_NTL_16                                    , 16  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( NV_CERR_HOLD1_NTL_17                                    , 17  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( NV_CERR_HOLD1_NTL_18                                    , 18  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( NV_CERR_HOLD1_NTL_19                                    , 19  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( NV_CERR_HOLD1_NTL_20                                    , 20  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( NV_CERR_HOLD1_NTL_21                                    , 21  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( NV_CERR_HOLD1_NTL_22                                    , 22  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( NV_CERR_HOLD1_NTL_23                                    , 23  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( NV_CERR_HOLD1_NTL_24                                    , 24  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( NV_CERR_HOLD1_NTL_25                                    , 25  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( NV_CERR_HOLD1_NTL_26                                    , 26  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( NV_CERR_HOLD1_NTL_27                                    , 27  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( NV_CERR_HOLD1_NTL_28                                    , 28  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( NV_CERR_HOLD1_NTL_29                                    , 29  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( NV_CERR_HOLD1_NTL_30                                    , 30  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( NV_CERR_HOLD1_NTL_31                                    , 31  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( NV_CERR_HOLD1_NTL_32                                    , 32  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( NV_CERR_HOLD1_NTL_33                                    , 33  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( NV_CERR_HOLD1_NTL_34                                    , 34  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( NV_CERR_HOLD1_NTL_35                                    , 35  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( NV_CERR_HOLD1_NTL_36                                    , 36  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( NV_CERR_HOLD1_NTL_37                                    , 37  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( NV_CERR_HOLD1_NTL_38                                    , 38  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( NV_CERR_HOLD1_NTL_39                                    , 39  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( NV_CERR_HOLD1_NTL_40                                    , 40  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( NV_CERR_HOLD1_NTL_41                                    , 41  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( NV_CERR_HOLD1_NTL_42                                    , 42  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( NV_CERR_HOLD1_NTL_43                                    , 43  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( NV_CERR_HOLD1_NTL_44                                    , 44  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( NV_CERR_HOLD1_NTL_45                                    , 45  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( NV_CERR_HOLD1_NTL_46                                    , 46  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( NV_CERR_HOLD1_NTL_47                                    , 47  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( NV_CERR_HOLD1_NTL_48                                    , 48  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( NV_CERR_HOLD1_NTL_49                                    , 49  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( NV_CERR_HOLD1_NTL_50                                    , 50  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( NV_CERR_HOLD1_NTL_51                                    , 51  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( NV_CERR_HOLD1_NTL_52                                    , 52  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( NV_CERR_HOLD1_NTL_53                                    , 53  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( NV_CERR_HOLD1_NTL_54                                    , 54  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( NV_CERR_HOLD1_NTL_55                                    , 55  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( NV_CERR_HOLD1_NTL_56                                    , 56  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( NV_CERR_HOLD1_NTL_57                                    , 57  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( NV_CERR_HOLD1_NTL_58                                    , 58  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( NV_CERR_HOLD1_NTL_59                                    , 59  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( NV_CERR_HOLD1_NTL_60                                    , 60  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( NV_CERR_HOLD1_NTL_61                                    , 61  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( NV_CERR_HOLD1_NTL_62                                    , 62  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( NV_CERR_HOLD1_NTL_63                                    , 63  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0             , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1             , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2             , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3             , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4             , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5             , 5   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6             , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7             , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8             , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_8 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9             , 9   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_9 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10            , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_10 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11            , 11  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_11 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12            , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_12 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13            , 13  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_13 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14            , 14  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_14 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15            , 15  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLGX_15 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0              , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1              , 17  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2              , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3              , 19  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_FWD_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0              , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1              , 21  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2              , 22  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3              , 23  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_AUE_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0              , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1              , 25  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2              , 26  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3              , 27  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4              , 28  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5              , 29  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6              , 30  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7              , 31  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBP_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0              , 32  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1              , 33  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2              , 34  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3              , 35  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4              , 36  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5              , 37  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6              , 38  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7              , 39  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8              , 40  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_8 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9              , 41  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_9 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10             , 42  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_10 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11             , 43  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBF_11 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0              , 44  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1              , 45  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2              , 46  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3              , 47  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4              , 48  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5              , 49  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6              , 50  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7              , 51  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8              , 52  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_8 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9              , 53  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_9 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10             , 54  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_10 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11             , 55  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_PBC_11 );
+
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              , 5   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_8 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              , 9   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_9 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_10 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             , 11  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_11 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_12 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             , 13  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_13 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             , 14  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_14 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             , 15  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_15 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_16 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             , 17  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_17 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_18 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             , 19  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_19 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_20 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             , 21  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_21 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             , 22  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_22 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             , 23  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_23 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_24 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             , 25  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_25 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             , 26  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_26 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             , 27  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_27 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             , 28  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_28 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             , 29  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_29 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             , 30  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_30 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             , 31  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_31 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             , 32  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_32 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             , 33  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_33 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             , 34  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_34 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             , 35  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_35 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             , 36  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_36 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             , 37  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_37 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             , 38  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_38 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             , 39  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_39 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             , 40  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_40 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             , 41  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_41 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             , 42  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_42 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             , 43  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_43 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             , 44  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_44 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             , 45  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_45 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             , 46  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_46 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             , 47  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_47 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             , 48  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_48 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             , 49  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_49 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             , 50  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_50 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             , 51  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_51 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             , 52  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_52 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             , 53  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_53 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             , 54  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_54 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             , 55  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_55 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             , 56  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_56 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             , 57  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_57 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             , 58  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_58 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             , 59  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_59 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             , 60  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_60 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             , 61  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_61 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             , 62  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_62 );
+REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             , 63  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_63 );
+
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_0                           , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_1                           , 1   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_2                           , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_3                           , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_4                           , 4   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_5                           , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_6                           , 6   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_7                           , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_8                           , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_9                           , 9   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_10                          , 10  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_11                          , 11  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_12                          , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_13                          , 13  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_14                          , 14  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_15                          , 15  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_16                          , 16  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_17                          , 17  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_18                          , 18  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_19                          , 19  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_20                          , 20  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_21                          , 21  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_22                          , 22  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_23                          , 23  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_24                          , 24  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_25                          , 25  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_26                          , 26  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_27                          , 27  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_28                          , 28  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_29                          , 29  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_30                          , 30  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_31                          , 31  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_32                          , 32  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_33                          , 33  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_34                          , 34  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_35                          , 35  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_36                          , 36  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_37                          , 37  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_38                          , 38  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_39                          , 39  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_40                          , 40  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_41                          , 41  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_42                          , 42  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_43                          , 43  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_44                          , 44  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_45                          , 45  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_46                          , 46  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_47                          , 47  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_48                          , 48  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_49                          , 49  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_50                          , 50  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_51                          , 51  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_52                          , 52  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_53                          , 53  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_54                          , 54  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_55                          , 55  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_56                          , 56  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_57                          , 57  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_58                          , 58  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_59                          , 59  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_60                          , 60  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_61                          , 61  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_62                          , 62  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_63                          , 63  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              , 5   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_8 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              , 9   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_9 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_10 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             , 11  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_11 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_12 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             , 13  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_13 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             , 14  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_14 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             , 15  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_15 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_16 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             , 17  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_17 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_18 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             , 19  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_19 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_20 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             , 21  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_21 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             , 22  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_22 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             , 23  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_23 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_24 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             , 25  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_25 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             , 26  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_26 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             , 27  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_27 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             , 28  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_28 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             , 29  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_29 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             , 30  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_30 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             , 31  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_31 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             , 32  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_32 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             , 33  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_33 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             , 34  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_34 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             , 35  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_35 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             , 36  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_36 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             , 37  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_37 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             , 38  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_38 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             , 39  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_39 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             , 40  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_40 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             , 41  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_41 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             , 42  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_42 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             , 43  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_43 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             , 44  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_44 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             , 45  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_45 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             , 46  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_46 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             , 47  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_47 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             , 48  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_48 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             , 49  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_49 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             , 50  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_50 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             , 51  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_51 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             , 52  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_52 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             , 53  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_53 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             , 54  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_54 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             , 55  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_55 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             , 56  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_56 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             , 57  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_57 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             , 58  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_58 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             , 59  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_59 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             , 60  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_60 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             , 61  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_61 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             , 62  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_62 );
+REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             , 63  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_63 );
+
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              , 5   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_8 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              , 9   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_9 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_10 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             , 11  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_11 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_12 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             , 13  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_13 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             , 14  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_14 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             , 15  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_15 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_16 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             , 17  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_17 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_18 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             , 19  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_19 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_20 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             , 21  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_21 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             , 22  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_22 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             , 23  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_23 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_24 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             , 25  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_25 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             , 26  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_26 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             , 27  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_27 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             , 28  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_28 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             , 29  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_29 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             , 30  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_30 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             , 31  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_31 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             , 32  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_32 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             , 33  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_33 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             , 34  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_34 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             , 35  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_35 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             , 36  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_36 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             , 37  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_37 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             , 38  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_38 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             , 39  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_39 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             , 40  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_40 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             , 41  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_41 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             , 42  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_42 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             , 43  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_43 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             , 44  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_44 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             , 45  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_45 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             , 46  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_46 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             , 47  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_47 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             , 48  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_48 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             , 49  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_49 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             , 50  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_50 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             , 51  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_51 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             , 52  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_52 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             , 53  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_53 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             , 54  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_54 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             , 55  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_55 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             , 56  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_56 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             , 57  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_57 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             , 58  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_58 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             , 59  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_59 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             , 60  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_60 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             , 61  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_61 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             , 62  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_62 );
+REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             , 63  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_63 );
+
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              , 5   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_8 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              , 9   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_9 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_10 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             , 11  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_11 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_12 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             , 13  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_13 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             , 14  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_14 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             , 15  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_15 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_16 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             , 17  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_17 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_18 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             , 19  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_19 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_20 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             , 21  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_21 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             , 22  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_22 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             , 23  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_23 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_24 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             , 25  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_25 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             , 26  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_26 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             , 27  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_27 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             , 28  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_28 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             , 29  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_29 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             , 30  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_30 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             , 31  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_31 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             , 32  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_32 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             , 33  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_33 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             , 34  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_34 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             , 35  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_35 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             , 36  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_36 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             , 37  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_37 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             , 38  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_38 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             , 39  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_39 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             , 40  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_40 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             , 41  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_41 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             , 42  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_42 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             , 43  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_43 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             , 44  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_44 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             , 45  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_45 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             , 46  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_46 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             , 47  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_47 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             , 48  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_48 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             , 49  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_49 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             , 50  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_50 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             , 51  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_51 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             , 52  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_52 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             , 53  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_53 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             , 54  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_54 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             , 55  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_55 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             , 56  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_56 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             , 57  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_57 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             , 58  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_58 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             , 59  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_59 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             , 60  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_60 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             , 61  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_61 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             , 62  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_62 );
+REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             , 63  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_63 );
+
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              , 5   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_8 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              , 9   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_9 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_10 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             , 11  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_11 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_12 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             , 13  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_13 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             , 14  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_14 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             , 15  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_15 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_16 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             , 17  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_17 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_18 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             , 19  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_19 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_20 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             , 21  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_21 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             , 22  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_22 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             , 23  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_23 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_24 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             , 25  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_25 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             , 26  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_26 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             , 27  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_27 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             , 28  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_28 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             , 29  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_29 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             , 30  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_30 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             , 31  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_31 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             , 32  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_32 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             , 33  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_33 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             , 34  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_34 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             , 35  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_35 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             , 36  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_36 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             , 37  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_37 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             , 38  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_38 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             , 39  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_39 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             , 40  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_40 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             , 41  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_41 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             , 42  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_42 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             , 43  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_43 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             , 44  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_44 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             , 45  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_45 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             , 46  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_46 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             , 47  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_47 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             , 48  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_48 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             , 49  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_49 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             , 50  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_50 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             , 51  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_51 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             , 52  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_52 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             , 53  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_53 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             , 54  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_54 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             , 55  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_55 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             , 56  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_56 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             , 57  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_57 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             , 58  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_58 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             , 59  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_59 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             , 60  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_60 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             , 61  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_61 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             , 62  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_62 );
+REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             , 63  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_63 );
+
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_0                           , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_1                           , 1   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_2                           , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_3                           , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_4                           , 4   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_5                           , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_6                           , 6   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_7                           , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_8                           , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_9                           , 9   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_10                          , 10  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_11                          , 11  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_12                          , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_13                          , 13  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_14                          , 14  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_15                          , 15  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_16                          , 16  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_17                          , 17  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_18                          , 18  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_19                          , 19  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_20                          , 20  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_21                          , 21  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_22                          , 22  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_23                          , 23  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_24                          , 24  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_25                          , 25  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_26                          , 26  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_27                          , 27  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_28                          , 28  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_29                          , 29  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_30                          , 30  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_31                          , 31  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_32                          , 32  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_33                          , 33  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_34                          , 34  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_35                          , 35  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_36                          , 36  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_37                          , 37  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_38                          , 38  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_39                          , 39  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_40                          , 40  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_41                          , 41  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_42                          , 42  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_43                          , 43  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_44                          , 44  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_45                          , 45  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_46                          , 46  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_47                          , 47  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_48                          , 48  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_49                          , 49  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_50                          , 50  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_51                          , 51  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_52                          , 52  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_53                          , 53  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_54                          , 54  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_55                          , 55  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_56                          , 56  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_57                          , 57  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_58                          , 58  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_59                          , 59  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_60                          , 60  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_61                          , 61  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_62                          , 62  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_63                          , 63  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              , 5   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_8 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              , 9   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_9 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_10 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             , 11  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_11 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_12 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             , 13  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_13 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             , 14  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_14 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             , 15  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_15 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_16 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             , 17  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_17 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_18 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             , 19  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_19 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_20 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             , 21  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_21 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             , 22  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_22 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             , 23  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_23 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_24 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             , 25  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_25 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             , 26  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_26 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             , 27  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_27 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             , 28  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_28 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             , 29  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_29 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             , 30  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_30 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             , 31  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_31 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             , 32  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_32 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             , 33  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_33 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             , 34  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_34 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             , 35  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_35 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             , 36  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_36 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             , 37  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_37 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             , 38  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_38 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             , 39  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_39 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             , 40  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_40 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             , 41  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_41 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             , 42  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_42 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             , 43  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_43 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             , 44  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_44 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             , 45  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_45 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             , 46  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_46 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             , 47  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_47 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             , 48  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_48 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             , 49  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_49 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             , 50  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_50 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             , 51  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_51 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             , 52  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_52 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             , 53  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_53 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             , 54  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_54 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             , 55  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_55 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             , 56  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_56 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             , 57  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_57 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             , 58  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_58 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             , 59  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_59 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             , 60  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_60 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             , 61  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_61 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             , 62  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_62 );
+REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             , 63  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_63 );
+
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              , 5   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_8 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              , 9   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_9 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_10 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             , 11  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_11 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_12 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             , 13  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_13 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             , 14  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_14 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             , 15  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_15 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_16 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             , 17  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_17 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_18 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             , 19  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_19 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_20 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             , 21  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_21 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             , 22  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_22 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             , 23  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_23 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_24 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             , 25  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_25 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             , 26  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_26 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             , 27  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_27 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             , 28  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_28 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             , 29  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_29 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             , 30  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_30 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             , 31  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_31 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             , 32  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_32 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             , 33  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_33 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             , 34  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_34 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             , 35  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_35 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             , 36  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_36 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             , 37  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_37 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             , 38  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_38 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             , 39  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_39 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             , 40  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_40 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             , 41  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_41 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             , 42  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_42 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             , 43  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_43 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             , 44  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_44 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             , 45  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_45 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             , 46  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_46 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             , 47  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_47 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             , 48  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_48 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             , 49  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_49 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             , 50  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_50 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             , 51  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_51 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             , 52  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_52 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             , 53  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_53 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             , 54  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_54 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             , 55  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_55 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             , 56  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_56 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             , 57  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_57 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             , 58  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_58 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             , 59  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_59 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             , 60  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_60 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             , 61  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_61 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             , 62  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_62 );
+REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             , 63  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_63 );
+
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              , 5   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_8 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              , 9   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_9 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_10 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             , 11  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_11 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_12 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             , 13  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_13 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             , 14  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_14 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             , 15  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_15 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_16 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             , 17  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_17 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_18 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             , 19  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_19 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_20 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             , 21  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_21 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             , 22  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_22 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             , 23  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_23 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_24 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             , 25  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_25 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             , 26  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_26 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             , 27  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_27 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             , 28  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_28 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             , 29  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_29 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             , 30  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_30 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             , 31  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_31 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             , 32  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_32 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             , 33  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_33 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             , 34  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_34 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             , 35  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_35 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             , 36  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_36 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             , 37  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_37 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             , 38  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_38 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             , 39  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_39 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             , 40  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_40 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             , 41  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_41 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             , 42  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_42 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             , 43  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_43 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             , 44  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_44 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             , 45  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_45 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             , 46  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_46 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             , 47  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_47 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             , 48  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_48 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             , 49  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_49 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             , 50  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_50 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             , 51  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_51 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             , 52  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_52 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             , 53  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_53 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             , 54  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_54 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             , 55  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_55 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             , 56  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_56 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             , 57  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_57 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             , 58  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_58 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             , 59  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_59 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             , 60  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_60 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             , 61  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_61 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             , 62  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_62 );
+REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             , 63  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_63 );
+
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              , 5   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_8 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              , 9   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_9 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_10 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             , 11  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_11 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_12 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             , 13  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_13 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             , 14  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_14 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             , 15  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_15 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_16 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             , 17  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_17 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_18 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             , 19  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_19 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_20 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             , 21  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_21 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             , 22  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_22 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             , 23  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_23 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_24 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             , 25  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_25 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             , 26  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_26 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             , 27  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_27 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             , 28  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_28 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             , 29  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_29 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             , 30  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_30 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             , 31  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_31 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             , 32  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_32 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             , 33  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_33 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             , 34  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_34 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             , 35  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_35 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             , 36  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_36 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             , 37  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_37 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             , 38  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_38 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             , 39  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_39 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             , 40  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_40 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             , 41  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_41 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             , 42  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_42 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             , 43  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_43 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             , 44  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_44 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             , 45  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_45 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             , 46  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_46 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             , 47  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_47 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             , 48  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_48 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             , 49  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_49 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             , 50  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_50 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             , 51  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_51 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             , 52  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_52 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             , 53  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_53 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             , 54  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_54 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             , 55  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_55 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             , 56  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_56 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             , 57  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_57 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             , 58  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_58 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             , 59  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_59 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             , 60  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_60 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             , 61  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_61 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             , 62  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_62 );
+REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             , 63  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_63 );
+
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              , 5   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_8 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              , 9   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_9 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_10 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             , 11  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_11 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_12 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             , 13  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_13 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             , 14  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_14 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             , 15  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_15 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_16 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             , 17  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_17 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_18 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             , 19  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_19 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_20 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             , 21  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_21 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             , 22  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_22 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             , 23  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_23 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_24 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             , 25  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_25 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             , 26  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_26 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             , 27  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_27 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             , 28  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_28 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             , 29  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_29 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             , 30  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_30 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             , 31  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_31 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             , 32  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_32 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             , 33  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_33 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             , 34  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_34 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             , 35  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_35 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             , 36  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_36 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             , 37  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_37 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             , 38  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_38 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             , 39  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_39 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             , 40  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_40 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             , 41  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_41 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             , 42  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_42 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             , 43  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_43 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             , 44  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_44 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             , 45  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_45 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             , 46  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_46 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             , 47  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_47 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             , 48  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_48 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             , 49  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_49 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             , 50  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_50 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             , 51  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_51 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             , 52  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_52 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             , 53  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_53 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             , 54  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_54 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             , 55  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_55 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             , 56  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_56 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             , 57  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_57 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             , 58  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_58 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             , 59  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_59 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             , 60  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_60 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             , 61  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_61 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             , 62  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_62 );
+REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             , 63  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_63 );
+
+REG64_FLD( NV_CERR_HOLD2_NTL_0                                     , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( NV_CERR_HOLD2_NTL_1                                     , 1   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( NV_CERR_HOLD2_NTL_2                                     , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( NV_CERR_HOLD2_NTL_3                                     , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( NV_CERR_HOLD2_NTL_4                                     , 4   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( NV_CERR_HOLD2_NTL_5                                     , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( NV_CERR_HOLD2_NTL_6                                     , 6   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( NV_CERR_HOLD2_NTL_7                                     , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( NV_CERR_HOLD2_NTL_8                                     , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( NV_CERR_HOLD2_NTL_9                                     , 9   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( NV_CERR_HOLD2_NTL_10                                    , 10  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( NV_CERR_HOLD2_NTL_11                                    , 11  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( NV_CERR_HOLD2_NTL_12                                    , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( NV_CERR_HOLD2_NTL_13                                    , 13  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( NV_CERR_HOLD2_NTL_14                                    , 14  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( NV_CERR_HOLD2_NTL_15                                    , 15  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( NV_CERR_HOLD2_NTL_16                                    , 16  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( NV_CERR_HOLD2_NTL_17                                    , 17  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( NV_CERR_HOLD2_NTL_18                                    , 18  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( NV_CERR_HOLD2_NTL_19                                    , 19  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( NV_CERR_HOLD2_NTL_20                                    , 20  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( NV_CERR_HOLD2_NTL_21                                    , 21  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( NV_CERR_HOLD2_NTL_22                                    , 22  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( NV_CERR_HOLD2_NTL_23                                    , 23  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( NV_CERR_HOLD2_NTL_24                                    , 24  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( NV_CERR_HOLD2_NTL_25                                    , 25  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( NV_CERR_HOLD2_NTL_26                                    , 26  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( NV_CERR_HOLD2_NTL_27                                    , 27  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( NV_CERR_HOLD2_NTL_28                                    , 28  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( NV_CERR_HOLD2_NTL_29                                    , 29  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( NV_CERR_HOLD2_NTL_30                                    , 30  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( NV_CERR_HOLD2_NTL_31                                    , 31  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( NV_CERR_HOLD2_NTL_32                                    , 32  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( NV_CERR_HOLD2_NTL_33                                    , 33  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( NV_CERR_HOLD2_NTL_34                                    , 34  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( NV_CERR_HOLD2_NTL_35                                    , 35  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( NV_CERR_HOLD2_NTL_36                                    , 36  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( NV_CERR_HOLD2_NTL_37                                    , 37  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( NV_CERR_HOLD2_NTL_38                                    , 38  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( NV_CERR_HOLD2_NTL_39                                    , 39  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( NV_CERR_HOLD2_NTL_40                                    , 40  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( NV_CERR_HOLD2_NTL_41                                    , 41  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( NV_CERR_HOLD2_NTL_42                                    , 42  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( NV_CERR_HOLD2_NTL_43                                    , 43  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( NV_CERR_HOLD2_NTL_44                                    , 44  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( NV_CERR_HOLD2_NTL_45                                    , 45  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( NV_CERR_HOLD2_NTL_46                                    , 46  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( NV_CERR_HOLD2_NTL_47                                    , 47  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( NV_CERR_HOLD2_NTL_48                                    , 48  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( NV_CERR_HOLD2_NTL_49                                    , 49  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( NV_CERR_HOLD2_NTL_50                                    , 50  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( NV_CERR_HOLD2_NTL_51                                    , 51  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( NV_CERR_HOLD2_NTL_52                                    , 52  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( NV_CERR_HOLD2_NTL_53                                    , 53  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( NV_CERR_HOLD2_NTL_54                                    , 54  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( NV_CERR_HOLD2_NTL_55                                    , 55  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( NV_CERR_HOLD2_NTL_56                                    , 56  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( NV_CERR_HOLD2_NTL_57                                    , 57  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( NV_CERR_HOLD2_NTL_58                                    , 58  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( NV_CERR_HOLD2_NTL_59                                    , 59  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( NV_CERR_HOLD2_NTL_60                                    , 60  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( NV_CERR_HOLD2_NTL_61                                    , 61  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( NV_CERR_HOLD2_NTL_62                                    , 62  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( NV_CERR_HOLD2_NTL_63                                    , 63  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              , 5   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_8 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              , 9   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_9 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_10 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             , 11  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_11 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_12 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             , 13  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_13 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             , 14  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_14 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             , 15  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_15 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_16 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             , 17  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_17 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_18 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             , 19  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_19 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_20 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             , 21  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_21 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             , 22  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_22 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             , 23  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_23 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_24 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             , 25  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_25 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             , 26  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_26 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             , 27  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_27 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             , 28  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_28 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             , 29  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_29 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             , 30  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_30 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             , 31  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_31 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             , 32  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_32 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             , 33  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_33 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             , 34  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_34 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             , 35  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_35 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             , 36  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_36 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             , 37  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_37 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             , 38  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_38 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             , 39  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_39 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             , 40  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_40 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             , 41  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_41 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             , 42  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_42 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             , 43  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_43 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             , 44  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_44 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             , 45  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_45 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             , 46  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_46 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             , 47  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_47 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             , 48  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_48 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             , 49  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_49 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             , 50  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_50 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             , 51  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_51 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             , 52  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_52 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             , 53  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_53 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             , 54  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_54 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             , 55  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_55 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             , 56  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_56 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             , 57  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_57 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             , 58  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_58 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             , 59  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_59 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             , 60  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_60 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             , 61  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_61 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             , 62  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_62 );
+REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             , 63  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_63 );
+
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0              , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1              , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2              , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3              , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4              , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5              , 5   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6              , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7              , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8              , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_8 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9              , 9   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_9 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10             , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_10 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11             , 11  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_11 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12             , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_12 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13             , 13  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_13 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14             , 14  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_14 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15             , 15  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_15 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16             , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_16 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17             , 17  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_17 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18             , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_18 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19             , 19  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_19 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20             , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_20 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21             , 21  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_21 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22             , 22  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_22 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23             , 23  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_23 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24             , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_24 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25             , 25  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_25 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26             , 26  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_26 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27             , 27  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_27 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28             , 28  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_28 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29             , 29  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_29 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30             , 30  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_30 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31             , 31  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_31 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32             , 32  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_32 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33             , 33  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_33 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34             , 34  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_34 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35             , 35  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_35 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36             , 36  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_36 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37             , 37  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_37 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38             , 38  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_38 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39             , 39  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_39 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40             , 40  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_40 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41             , 41  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_41 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42             , 42  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_42 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43             , 43  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_43 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44             , 44  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_44 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45             , 45  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_45 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46             , 46  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_46 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47             , 47  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_47 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48             , 48  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_48 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49             , 49  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_49 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50             , 50  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_50 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51             , 51  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_51 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52             , 52  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_52 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53             , 53  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_53 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54             , 54  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_54 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55             , 55  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_55 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56             , 56  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_56 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57             , 57  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_57 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58             , 58  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_58 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59             , 59  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_59 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60             , 60  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_60 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61             , 61  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_61 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62             , 62  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_62 );
+REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63             , 63  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_HOLD_NLG_63 );
+
+REG64_FLD( PU_NPU0_CERR_LOG_FIRST_BITS                             , 47  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU0_CERR_LOG_FIRST_BITS_LEN                         , 17  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU1_CERR_LOG_FIRST_BITS                             , 47  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU1_CERR_LOG_FIRST_BITS_LEN                         , 17  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU2_CERR_LOG_FIRST_BITS                             , 47  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU2_CERR_LOG_FIRST_BITS_LEN                         , 17  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_BBUF_RDWR                   , 47  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BBUF_RDWR );
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_IBUF_RDWR                   , 48  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBUF_RDWR );
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_OBUF_RDWR                   , 49  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OBUF_RDWR );
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_RQIN_OVF                    , 50  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_RQIN_OVF );
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_RQIN_OVF_LEN                , 6   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_RQIN_OVF_LEN );
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_IBUF_CTL_PIPE               , 56  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBUF_CTL_PIPE );
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_PBTX_PIPE                   , 57  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBTX_PIPE );
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_MRG_IR_PIPE                 , 58  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_MRG_IR_PIPE );
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_MRG_OR_PIPE                 , 59  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_MRG_OR_PIPE );
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_AMO_ADDR                    , 60  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_AMO_ADDR );
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_PBRX_RTAG                   , 61  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBRX_RTAG );
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_IBUF_WRITE                  , 62  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBUF_WRITE );
+REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_IBUF_WARB                   , 63  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBUF_WARB );
+
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_BBUF_RDWR                   , 47  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BBUF_RDWR );
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_IBUF_RDWR                   , 48  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBUF_RDWR );
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_OBUF_RDWR                   , 49  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OBUF_RDWR );
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_RQIN_OVF                    , 50  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_RQIN_OVF );
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_RQIN_OVF_LEN                , 6   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_RQIN_OVF_LEN );
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_IBUF_CTL_PIPE               , 56  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBUF_CTL_PIPE );
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_PBTX_PIPE                   , 57  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBTX_PIPE );
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_MRG_IR_PIPE                 , 58  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_MRG_IR_PIPE );
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_MRG_OR_PIPE                 , 59  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_MRG_OR_PIPE );
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_AMO_ADDR                    , 60  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_AMO_ADDR );
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_PBRX_RTAG                   , 61  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBRX_RTAG );
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_IBUF_WRITE                  , 62  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBUF_WRITE );
+REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_IBUF_WARB                   , 63  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBUF_WARB );
+
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_BBUF_RDWR                   , 47  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BBUF_RDWR );
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_IBUF_RDWR                   , 48  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBUF_RDWR );
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_OBUF_RDWR                   , 49  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OBUF_RDWR );
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_RQIN_OVF                    , 50  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_RQIN_OVF );
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_RQIN_OVF_LEN                , 6   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_RQIN_OVF_LEN );
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_IBUF_CTL_PIPE               , 56  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBUF_CTL_PIPE );
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_PBTX_PIPE                   , 57  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBTX_PIPE );
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_MRG_IR_PIPE                 , 58  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_MRG_IR_PIPE );
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_MRG_OR_PIPE                 , 59  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_MRG_OR_PIPE );
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_AMO_ADDR                    , 60  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_AMO_ADDR );
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_PBRX_RTAG                   , 61  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBRX_RTAG );
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_IBUF_WRITE                  , 62  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBUF_WRITE );
+REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_IBUF_WARB                   , 63  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBUF_WARB );
+
+REG64_FLD( PU_NPU0_CERR_LOG_MASK_BITS                              , 47  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU0_CERR_LOG_MASK_BITS_LEN                          , 17  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU1_CERR_LOG_MASK_BITS                              , 47  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU1_CERR_LOG_MASK_BITS_LEN                          , 17  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU2_CERR_LOG_MASK_BITS                              , 47  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU2_CERR_LOG_MASK_BITS_LEN                          , 17  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0              , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1              , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2              , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3              , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4              , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5              , 5   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6              , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7              , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8              , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_8 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9              , 9   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_9 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10             , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_10 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11             , 11  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_11 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12             , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_12 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13             , 13  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_13 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14             , 14  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_14 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15             , 15  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_15 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16             , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_16 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17             , 17  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_17 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18             , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_18 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19             , 19  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_19 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20             , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_20 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21             , 21  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_21 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22             , 22  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_22 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23             , 23  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_23 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_24             , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_24 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_25             , 25  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_25 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_26             , 26  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_26 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_27             , 27  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_27 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_28             , 28  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_28 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_29             , 29  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_29 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_30             , 30  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_30 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_31             , 31  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_31 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0              , 32  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1              , 33  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2              , 34  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3              , 35  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_4              , 36  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_5              , 37  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_6              , 38  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_7              , 39  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             , 40  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             , 41  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             , 42  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             , 43  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0              , 44  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1              , 45  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2              , 46  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3              , 47  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_4              , 48  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_5              , 49  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6              , 50  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7              , 51  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_0              , 52  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_1              , 53  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_2              , 54  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_3              , 55  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_3 );
+
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0              , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1              , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2              , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3              , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4              , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5              , 5   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6              , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7              , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8              , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_8 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9              , 9   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_9 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10             , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_10 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11             , 11  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_11 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12             , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_12 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13             , 13  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_13 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14             , 14  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_14 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15             , 15  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_15 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16             , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_16 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17             , 17  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_17 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18             , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_18 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19             , 19  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_19 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20             , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_20 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21             , 21  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_21 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22             , 22  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_22 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23             , 23  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_23 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_24             , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_24 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_25             , 25  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_25 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_26             , 26  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_26 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_27             , 27  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_27 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_28             , 28  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_28 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_29             , 29  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_29 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_30             , 30  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_30 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_31             , 31  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_31 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0              , 32  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1              , 33  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2              , 34  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3              , 35  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_4              , 36  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_5              , 37  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_6              , 38  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_7              , 39  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             , 40  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             , 41  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             , 42  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             , 43  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0              , 44  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1              , 45  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2              , 46  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3              , 47  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_4              , 48  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_5              , 49  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6              , 50  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7              , 51  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_0              , 52  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_1              , 53  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_2              , 54  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_3              , 55  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_3 );
+
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0              , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1              , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2              , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3              , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4              , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5              , 5   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6              , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7              , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8              , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_8 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9              , 9   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_9 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10             , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_10 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11             , 11  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_11 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12             , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_12 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13             , 13  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_13 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14             , 14  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_14 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15             , 15  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_15 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16             , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_16 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17             , 17  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_17 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18             , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_18 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19             , 19  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_19 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20             , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_20 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21             , 21  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_21 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22             , 22  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_22 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23             , 23  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_23 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_24             , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_24 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_25             , 25  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_25 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_26             , 26  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_26 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_27             , 27  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_27 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_28             , 28  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_28 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_29             , 29  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_29 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_30             , 30  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_30 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_31             , 31  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_31 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0              , 32  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1              , 33  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2              , 34  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3              , 35  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_4              , 36  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_5              , 37  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_6              , 38  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_7              , 39  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             , 40  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             , 41  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             , 42  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             , 43  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0              , 44  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1              , 45  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2              , 46  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3              , 47  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_4              , 48  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_5              , 49  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6              , 50  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7              , 51  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_0              , 52  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_1              , 53  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_2              , 54  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_3              , 55  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_3 );
+
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0              , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1              , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2              , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3              , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4              , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5              , 5   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6              , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7              , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8              , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_8 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9              , 9   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_9 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10             , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_10 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11             , 11  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_11 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12             , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_12 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13             , 13  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_13 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14             , 14  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_14 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15             , 15  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_15 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16             , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_16 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17             , 17  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_17 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18             , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_18 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19             , 19  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_19 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20             , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_20 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21             , 21  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_21 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22             , 22  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_22 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23             , 23  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_23 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_24             , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_24 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_25             , 25  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_25 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_26             , 26  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_26 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_27             , 27  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_27 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_28             , 28  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_28 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_29             , 29  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_29 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_30             , 30  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_30 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_31             , 31  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_31 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0              , 32  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1              , 33  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2              , 34  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3              , 35  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_4              , 36  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_5              , 37  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_6              , 38  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_7              , 39  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             , 40  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             , 41  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             , 42  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             , 43  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0              , 44  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1              , 45  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2              , 46  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3              , 47  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_4              , 48  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_5              , 49  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6              , 50  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7              , 51  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_0              , 52  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_1              , 53  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_2              , 54  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_3              , 55  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_3 );
+
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0              , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1              , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2              , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3              , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4              , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5              , 5   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6              , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7              , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8              , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_8 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9              , 9   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_9 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10             , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_10 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11             , 11  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_11 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12             , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_12 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13             , 13  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_13 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14             , 14  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_14 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15             , 15  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_15 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16             , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_16 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17             , 17  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_17 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18             , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_18 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19             , 19  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_19 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20             , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_20 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21             , 21  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_21 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22             , 22  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_22 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23             , 23  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_23 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_24             , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_24 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_25             , 25  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_25 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_26             , 26  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_26 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_27             , 27  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_27 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_28             , 28  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_28 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_29             , 29  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_29 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_30             , 30  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_30 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_31             , 31  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_31 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0              , 32  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1              , 33  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2              , 34  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3              , 35  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_4              , 36  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_5              , 37  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_6              , 38  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_7              , 39  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             , 40  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             , 41  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             , 42  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             , 43  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0              , 44  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1              , 45  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2              , 46  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3              , 47  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_4              , 48  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_5              , 49  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6              , 50  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7              , 51  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_0              , 52  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_1              , 53  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_2              , 54  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_3              , 55  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_3 );
+
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_0              , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_1              , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_2              , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_3              , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_4              , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_5              , 5   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_6              , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_7              , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_8              , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_8 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_9              , 9   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_9 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_10             , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_10 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_11             , 11  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_11 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_12             , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_12 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_13             , 13  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_13 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_14             , 14  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_14 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_15             , 15  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_15 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_16             , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_16 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_17             , 17  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_17 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_18             , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_18 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_19             , 19  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_19 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_20             , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_20 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_21             , 21  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_21 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_22             , 22  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_22 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_23             , 23  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_23 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_24             , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_24 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_25             , 25  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_25 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_26             , 26  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_26 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_27             , 27  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_27 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_28             , 28  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_28 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_29             , 29  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_29 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_30             , 30  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_30 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_31             , 31  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_31 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_0              , 32  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_1              , 33  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_2              , 34  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_3              , 35  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_4              , 36  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_5              , 37  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_6              , 38  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_7              , 39  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             , 40  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             , 41  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             , 42  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             , 43  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_0              , 44  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_1              , 45  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_2              , 46  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_3              , 47  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_4              , 48  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_5              , 49  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_6              , 50  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_7              , 51  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_0              , 52  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_1              , 53  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_2              , 54  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_3              , 55  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_3 );
+
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0              , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1              , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2              , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3              , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4              , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5              , 5   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6              , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7              , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8              , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_8 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9              , 9   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_9 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10             , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_10 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11             , 11  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_11 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12             , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_12 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13             , 13  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_13 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14             , 14  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_14 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15             , 15  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_15 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16             , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_16 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17             , 17  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_17 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18             , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_18 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19             , 19  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_19 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20             , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_20 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21             , 21  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_21 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22             , 22  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_22 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23             , 23  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_23 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_24             , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_24 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_25             , 25  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_25 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_26             , 26  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_26 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_27             , 27  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_27 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_28             , 28  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_28 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_29             , 29  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_29 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_30             , 30  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_30 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_31             , 31  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_31 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0              , 32  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1              , 33  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2              , 34  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3              , 35  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_4              , 36  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_5              , 37  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_6              , 38  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_7              , 39  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             , 40  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             , 41  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             , 42  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             , 43  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0              , 44  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1              , 45  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2              , 46  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3              , 47  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_4              , 48  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_5              , 49  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6              , 50  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7              , 51  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_0              , 52  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_1              , 53  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_2              , 54  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_3              , 55  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_3 );
+
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_0             , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_1             , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_2             , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_3             , 3   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_4             , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_5             , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_6             , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_7             , 7   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_0             , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_1             , 9   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_2             , 10  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_3             , 11  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_4             , 12  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_5             , 13  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_6             , 14  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_7             , 15  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_8             , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_8 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_9             , 17  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_9 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_10            , 18  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_10 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_11            , 19  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_11 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_12            , 20  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_12 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_13            , 21  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_13 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_14            , 22  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_14 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_15            , 23  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_15 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_16            , 24  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_16 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_17            , 25  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_17 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_18            , 26  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_18 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_19            , 27  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_19 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_20            , 28  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_20 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_21            , 29  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_21 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_22            , 30  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_22 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_23            , 31  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_23 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_0            , 32  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV1_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_1            , 33  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV1_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_2            , 34  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV1_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_3            , 35  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV1_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_0            , 36  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_1            , 37  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_2            , 38  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_3            , 39  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_4            , 40  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_5            , 41  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_6            , 42  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_7            , 43  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_0             , 44  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_1             , 45  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_2             , 46  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_3             , 47  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_4             , 48  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_5             , 49  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_6             , 50  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_7             , 51  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_0             , 52  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_REG_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_1             , 53  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_REG_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_2             , 54  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_REG_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_3             , 55  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_REG_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_0             , 56  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_DUE_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_1             , 57  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_DUE_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_2             , 58  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_DUE_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_3             , 59  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_DUE_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_0             , 60  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PEF_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_1             , 61  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PEF_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_2             , 62  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PEF_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_3             , 63  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PEF_3 );
+
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_0              , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_1              , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_2              , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_3              , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_4              , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_5              , 5   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_6              , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_7              , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_8              , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_8 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_9              , 9   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_9 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_10             , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_10 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_11             , 11  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_11 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_12             , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_12 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_13             , 13  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_13 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_14             , 14  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_14 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_15             , 15  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_15 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_16             , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_16 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_17             , 17  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_17 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_18             , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_18 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_19             , 19  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_19 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_20             , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_20 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_21             , 21  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_21 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_22             , 22  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_22 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_23             , 23  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_23 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_24             , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_24 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_25             , 25  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_25 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_26             , 26  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_26 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_27             , 27  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_27 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_28             , 28  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_28 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_29             , 29  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_29 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_30             , 30  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_30 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_31             , 31  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_31 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_0              , 32  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_1              , 33  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_2              , 34  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_3              , 35  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_4              , 36  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_5              , 37  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_6              , 38  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_7              , 39  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             , 40  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             , 41  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             , 42  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             , 43  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_0              , 44  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_1              , 45  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_2              , 46  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_3              , 47  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_4              , 48  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_5              , 49  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_6              , 50  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_7              , 51  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_0              , 52  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_1              , 53  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_2              , 54  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_3              , 55  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_3 );
+
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0              , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1              , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2              , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3              , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4              , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5              , 5   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6              , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7              , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8              , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_8 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9              , 9   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_9 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10             , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_10 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11             , 11  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_11 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12             , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_12 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13             , 13  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_13 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14             , 14  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_14 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15             , 15  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_15 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16             , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_16 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17             , 17  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_17 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18             , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_18 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19             , 19  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_19 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20             , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_20 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21             , 21  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_21 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22             , 22  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_22 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23             , 23  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_23 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_24             , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_24 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_25             , 25  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_25 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_26             , 26  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_26 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_27             , 27  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_27 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_28             , 28  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_28 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_29             , 29  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_29 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_30             , 30  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_30 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_31             , 31  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_31 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0              , 32  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1              , 33  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2              , 34  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3              , 35  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_4              , 36  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_5              , 37  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_6              , 38  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_7              , 39  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             , 40  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             , 41  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             , 42  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             , 43  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0              , 44  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1              , 45  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2              , 46  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3              , 47  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_4              , 48  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_5              , 49  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6              , 50  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7              , 51  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_0              , 52  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_1              , 53  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_2              , 54  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_3              , 55  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_3 );
+
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0              , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1              , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2              , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3              , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4              , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5              , 5   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6              , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7              , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8              , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_8 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9              , 9   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_9 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10             , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_10 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11             , 11  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_11 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12             , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_12 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13             , 13  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_13 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14             , 14  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_14 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15             , 15  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_15 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16             , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_16 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17             , 17  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_17 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18             , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_18 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19             , 19  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_19 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20             , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_20 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21             , 21  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_21 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22             , 22  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_22 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23             , 23  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_23 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_24             , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_24 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_25             , 25  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_25 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_26             , 26  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_26 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_27             , 27  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_27 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_28             , 28  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_28 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_29             , 29  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_29 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_30             , 30  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_30 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_31             , 31  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_31 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0              , 32  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1              , 33  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2              , 34  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3              , 35  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_4              , 36  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_5              , 37  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_6              , 38  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_7              , 39  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             , 40  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             , 41  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             , 42  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             , 43  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0              , 44  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1              , 45  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2              , 46  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3              , 47  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_4              , 48  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_5              , 49  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6              , 50  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7              , 51  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_0              , 52  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_1              , 53  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_2              , 54  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_3              , 55  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_3 );
+
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_0             , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_1             , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_2             , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_3             , 3   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_4             , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_5             , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_6             , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_7             , 7   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_0             , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_1             , 9   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_2             , 10  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_3             , 11  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_4             , 12  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_5             , 13  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_6             , 14  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_7             , 15  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_8             , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_8 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_9             , 17  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_9 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_10            , 18  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_10 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_11            , 19  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_11 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_12            , 20  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_12 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_13            , 21  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_13 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_14            , 22  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_14 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_15            , 23  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_15 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_16            , 24  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_16 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_17            , 25  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_17 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_18            , 26  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_18 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_19            , 27  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_19 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_20            , 28  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_20 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_21            , 29  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_21 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_22            , 30  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_22 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_23            , 31  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_23 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_0            , 32  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV1_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_1            , 33  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV1_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_2            , 34  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV1_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_3            , 35  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV1_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_0            , 36  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_1            , 37  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_2            , 38  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_3            , 39  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_4            , 40  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_5            , 41  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_6            , 42  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_7            , 43  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_0             , 44  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_1             , 45  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_2             , 46  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_3             , 47  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_4             , 48  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_5             , 49  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_6             , 50  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_7             , 51  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_0             , 52  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_REG_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_1             , 53  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_REG_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_2             , 54  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_REG_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_3             , 55  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_REG_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_0             , 56  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_DUE_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_1             , 57  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_DUE_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_2             , 58  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_DUE_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_3             , 59  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_DUE_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_0             , 60  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PEF_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_1             , 61  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PEF_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_2             , 62  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PEF_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_3             , 63  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PEF_3 );
+
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_0             , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_1             , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_2             , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_3             , 3   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_4             , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_5             , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_6             , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_7             , 7   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NCF_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_0             , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_1             , 9   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_2             , 10  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_3             , 11  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_4             , 12  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_5             , 13  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_6             , 14  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_7             , 15  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_8             , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_8 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_9             , 17  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_9 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_10            , 18  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_10 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_11            , 19  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_11 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_12            , 20  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_12 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_13            , 21  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_13 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_14            , 22  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_14 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_15            , 23  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_15 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_16            , 24  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_16 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_17            , 25  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_17 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_18            , 26  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_18 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_19            , 27  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_19 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_20            , 28  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_20 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_21            , 29  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_21 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_22            , 30  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_22 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_23            , 31  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NVF_23 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_0            , 32  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV1_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_1            , 33  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV1_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_2            , 34  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV1_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_3            , 35  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV1_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_0            , 36  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_1            , 37  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_2            , 38  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_3            , 39  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_4            , 40  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_5            , 41  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_6            , 42  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_7            , 43  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_ASBE_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_0             , 44  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_1             , 45  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_2             , 46  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_3             , 47  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_4             , 48  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_5             , 49  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_6             , 50  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_7             , 51  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBR_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_0             , 52  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_REG_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_1             , 53  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_REG_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_2             , 54  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_REG_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_3             , 55  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_REG_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_0             , 56  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_DUE_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_1             , 57  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_DUE_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_2             , 58  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_DUE_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_3             , 59  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_DUE_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_0             , 60  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PEF_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_1             , 61  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PEF_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_2             , 62  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PEF_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_3             , 63  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PEF_3 );
+
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_0              , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_1              , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_2              , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_3              , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_4              , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_5              , 5   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_6              , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_7              , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_8              , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_8 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_9              , 9   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_9 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_10             , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_10 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_11             , 11  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_11 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_12             , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_12 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_13             , 13  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_13 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_14             , 14  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_14 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_15             , 15  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_15 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_16             , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_16 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_17             , 17  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_17 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_18             , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_18 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_19             , 19  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_19 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_20             , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_20 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_21             , 21  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_21 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_22             , 22  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_22 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_23             , 23  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_23 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_24             , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_24 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_25             , 25  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_25 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_26             , 26  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_26 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_27             , 27  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_27 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_28             , 28  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_28 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_29             , 29  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_29 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_30             , 30  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_30 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_31             , 31  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_31 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_0              , 32  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_1              , 33  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_2              , 34  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_3              , 35  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_4              , 36  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_5              , 37  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_6              , 38  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_7              , 39  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             , 40  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             , 41  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             , 42  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             , 43  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_0              , 44  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_1              , 45  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_2              , 46  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_3              , 47  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_4              , 48  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_5              , 49  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_6              , 50  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_7              , 51  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_0              , 52  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_1              , 53  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_2              , 54  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_3              , 55  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_3 );
+
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0              , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1              , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2              , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3              , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4              , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5              , 5   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6              , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7              , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8              , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_8 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9              , 9   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_9 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10             , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_10 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11             , 11  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_11 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12             , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_12 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13             , 13  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_13 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14             , 14  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_14 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15             , 15  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_15 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16             , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_16 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17             , 17  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_17 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18             , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_18 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19             , 19  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_19 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20             , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_20 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21             , 21  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_21 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22             , 22  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_22 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23             , 23  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_23 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_24             , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_24 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_25             , 25  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_25 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_26             , 26  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_26 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_27             , 27  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_27 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_28             , 28  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_28 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_29             , 29  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_29 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_30             , 30  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_30 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_31             , 31  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NVF_31 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0              , 32  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1              , 33  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2              , 34  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3              , 35  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_4              , 36  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_5              , 37  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_6              , 38  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_7              , 39  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NCF_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0             , 40  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1             , 41  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2             , 42  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3             , 43  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_ASBE_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0              , 44  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1              , 45  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2              , 46  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3              , 47  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_4              , 48  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_5              , 49  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6              , 50  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7              , 51  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBR_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_0              , 52  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_1              , 53  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_2              , 54  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_3              , 55  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_REG_3 );
+
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             , 5   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_8 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             , 9   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_9 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_10 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            , 11  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_11 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_12 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            , 13  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_13 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            , 14  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_14 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            , 15  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_15 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0              , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1              , 17  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2              , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3              , 19  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0              , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1              , 21  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2              , 22  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3              , 23  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_0              , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_1              , 25  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_2              , 26  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_3              , 27  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_4              , 28  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_5              , 29  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_6              , 30  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_7              , 31  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_0              , 32  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_1              , 33  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_2              , 34  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_3              , 35  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_4              , 36  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_5              , 37  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_6              , 38  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_7              , 39  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_8              , 40  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_8 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_9              , 41  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_9 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_10             , 42  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_10 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_11             , 43  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_11 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_0              , 44  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_1              , 45  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_2              , 46  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_3              , 47  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_4              , 48  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_5              , 49  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_6              , 50  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_7              , 51  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_8              , 52  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_8 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_9              , 53  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_9 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_10             , 54  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_10 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_11             , 55  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_11 );
+
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             , 5   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_8 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             , 9   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_9 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_10 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            , 11  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_11 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_12 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            , 13  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_13 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            , 14  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_14 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            , 15  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_15 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0              , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1              , 17  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2              , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3              , 19  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0              , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1              , 21  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2              , 22  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3              , 23  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_0              , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_1              , 25  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_2              , 26  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_3              , 27  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_4              , 28  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_5              , 29  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_6              , 30  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_7              , 31  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_0              , 32  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_1              , 33  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_2              , 34  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_3              , 35  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_4              , 36  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_5              , 37  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_6              , 38  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_7              , 39  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_8              , 40  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_8 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_9              , 41  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_9 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_10             , 42  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_10 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_11             , 43  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_11 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_0              , 44  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_1              , 45  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_2              , 46  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_3              , 47  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_4              , 48  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_5              , 49  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_6              , 50  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_7              , 51  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_8              , 52  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_8 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_9              , 53  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_9 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_10             , 54  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_10 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_11             , 55  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_11 );
+
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_0                           , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_1                           , 1   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_2                           , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_3                           , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_4                           , 4   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_5                           , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_6                           , 6   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_7                           , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_8                           , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_9                           , 9   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_10                          , 10  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_11                          , 11  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_12                          , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_13                          , 13  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_14                          , 14  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_15                          , 15  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_16                          , 16  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_17                          , 17  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_18                          , 18  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_19                          , 19  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_20                          , 20  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_21                          , 21  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_22                          , 22  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_23                          , 23  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_24                          , 24  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_25                          , 25  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_26                          , 26  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_27                          , 27  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_28                          , 28  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_29                          , 29  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_30                          , 30  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_31                          , 31  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_32                          , 32  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_33                          , 33  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_34                          , 34  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_35                          , 35  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_36                          , 36  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_37                          , 37  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_38                          , 38  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_39                          , 39  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_40                          , 40  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_41                          , 41  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_42                          , 42  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_43                          , 43  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_44                          , 44  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_45                          , 45  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_46                          , 46  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_47                          , 47  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_48                          , 48  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_49                          , 49  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_50                          , 50  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_51                          , 51  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_52                          , 52  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_53                          , 53  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_54                          , 54  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_55                          , 55  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_56                          , 56  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_57                          , 57  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_58                          , 58  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_59                          , 59  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_60                          , 60  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_61                          , 61  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_62                          , 62  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_63                          , 63  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             , 5   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_8 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             , 9   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_9 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_10 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            , 11  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_11 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_12 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            , 13  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_13 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            , 14  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_14 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            , 15  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_15 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_0              , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_1              , 17  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_2              , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_3              , 19  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_0              , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_1              , 21  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_2              , 22  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_3              , 23  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_0              , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_1              , 25  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_2              , 26  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_3              , 27  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_4              , 28  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_5              , 29  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_6              , 30  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_7              , 31  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_0              , 32  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_1              , 33  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_2              , 34  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_3              , 35  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_4              , 36  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_5              , 37  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_6              , 38  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_7              , 39  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_8              , 40  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_8 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_9              , 41  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_9 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_10             , 42  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_10 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_11             , 43  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_11 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_0              , 44  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_1              , 45  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_2              , 46  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_3              , 47  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_4              , 48  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_5              , 49  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_6              , 50  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_7              , 51  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_8              , 52  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_8 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_9              , 53  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_9 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_10             , 54  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_10 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_11             , 55  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_11 );
+
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             , 5   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_8 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             , 9   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_9 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_10 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            , 11  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_11 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_12 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            , 13  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_13 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            , 14  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_14 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            , 15  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_15 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0              , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1              , 17  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2              , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3              , 19  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0              , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1              , 21  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2              , 22  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3              , 23  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_0              , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_1              , 25  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_2              , 26  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_3              , 27  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_4              , 28  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_5              , 29  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_6              , 30  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_7              , 31  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_0              , 32  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_1              , 33  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_2              , 34  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_3              , 35  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_4              , 36  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_5              , 37  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_6              , 38  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_7              , 39  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_8              , 40  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_8 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_9              , 41  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_9 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_10             , 42  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_10 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_11             , 43  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_11 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_0              , 44  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_1              , 45  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_2              , 46  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_3              , 47  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_4              , 48  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_5              , 49  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_6              , 50  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_7              , 51  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_8              , 52  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_8 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_9              , 53  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_9 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_10             , 54  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_10 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_11             , 55  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_11 );
+
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_0             , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_1             , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_2             , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_3             , 3   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_4             , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_5             , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_6             , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_7             , 7   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_8             , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_8 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_9             , 9   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_9 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_10            , 10  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_10 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_11            , 11  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_11 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_12            , 12  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_12 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_13            , 13  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_13 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_14            , 14  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_14 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_15            , 15  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_15 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_0             , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_1             , 17  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_2             , 18  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_3             , 19  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_4             , 20  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_5             , 21  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_6             , 22  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_7             , 23  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_0             , 24  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_1             , 25  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_2             , 26  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_3             , 27  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_4             , 28  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_5             , 29  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_6             , 30  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_7             , 31  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_0             , 32  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_1             , 33  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_2             , 34  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_3             , 35  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_4             , 36  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_5             , 37  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_6             , 38  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_7             , 39  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_0             , 40  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_1             , 41  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_2             , 42  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_3             , 43  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_4             , 44  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_5             , 45  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_6             , 46  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_7             , 47  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_0             , 48  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_1             , 49  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_2             , 50  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_3             , 51  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_4             , 52  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_4 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_5             , 53  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_5 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_6             , 54  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_6 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_7             , 55  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_7 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_0            , 56  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV2_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_1            , 57  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV2_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_2            , 58  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV2_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_3            , 59  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV2_3 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_0            , 60  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV3_0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_1            , 61  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV3_1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_2            , 62  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV3_2 );
+REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_3            , 63  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV3_3 );
+
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             , 5   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_8 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             , 9   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_9 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_10 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            , 11  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_11 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_12 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            , 13  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_13 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            , 14  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_14 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            , 15  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_15 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_0              , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_1              , 17  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_2              , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_3              , 19  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_0              , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_1              , 21  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_2              , 22  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_3              , 23  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_0              , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_1              , 25  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_2              , 26  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_3              , 27  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_4              , 28  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_5              , 29  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_6              , 30  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_7              , 31  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_0              , 32  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_1              , 33  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_2              , 34  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_3              , 35  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_4              , 36  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_5              , 37  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_6              , 38  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_7              , 39  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_8              , 40  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_8 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_9              , 41  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_9 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_10             , 42  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_10 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_11             , 43  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_11 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_0              , 44  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_1              , 45  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_2              , 46  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_3              , 47  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_4              , 48  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_5              , 49  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_6              , 50  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_7              , 51  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_8              , 52  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_8 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_9              , 53  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_9 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_10             , 54  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_10 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_11             , 55  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_11 );
+
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             , 5   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_8 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             , 9   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_9 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_10 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            , 11  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_11 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_12 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            , 13  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_13 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            , 14  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_14 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            , 15  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_15 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0              , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1              , 17  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2              , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3              , 19  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0              , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1              , 21  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2              , 22  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3              , 23  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_0              , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_1              , 25  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_2              , 26  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_3              , 27  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_4              , 28  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_5              , 29  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_6              , 30  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_7              , 31  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_0              , 32  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_1              , 33  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_2              , 34  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_3              , 35  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_4              , 36  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_5              , 37  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_6              , 38  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_7              , 39  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_8              , 40  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_8 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_9              , 41  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_9 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_10             , 42  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_10 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_11             , 43  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_11 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_0              , 44  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_1              , 45  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_2              , 46  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_3              , 47  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_4              , 48  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_5              , 49  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_6              , 50  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_7              , 51  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_8              , 52  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_8 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_9              , 53  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_9 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_10             , 54  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_10 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_11             , 55  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_11 );
+
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_0                           , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_1                           , 1   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_2                           , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_3                           , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_4                           , 4   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_5                           , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_6                           , 6   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_7                           , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_8                           , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_9                           , 9   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_10                          , 10  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_11                          , 11  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_12                          , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_13                          , 13  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_14                          , 14  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_15                          , 15  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_16                          , 16  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_17                          , 17  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_18                          , 18  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_19                          , 19  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_20                          , 20  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_21                          , 21  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_22                          , 22  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_23                          , 23  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_24                          , 24  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_25                          , 25  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_26                          , 26  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_27                          , 27  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_28                          , 28  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_29                          , 29  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_30                          , 30  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_31                          , 31  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_32                          , 32  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_33                          , 33  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_34                          , 34  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_35                          , 35  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_36                          , 36  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_37                          , 37  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_38                          , 38  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_39                          , 39  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_40                          , 40  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_41                          , 41  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_42                          , 42  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_43                          , 43  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_44                          , 44  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_45                          , 45  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_46                          , 46  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_47                          , 47  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_48                          , 48  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_49                          , 49  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_50                          , 50  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_51                          , 51  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_52                          , 52  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_53                          , 53  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_54                          , 54  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_55                          , 55  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_56                          , 56  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_57                          , 57  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_58                          , 58  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_59                          , 59  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_60                          , 60  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_61                          , 61  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_62                          , 62  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_63                          , 63  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             , 5   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_8 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             , 9   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_9 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_10 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            , 11  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_11 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_12 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            , 13  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_13 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            , 14  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_14 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            , 15  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_15 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0              , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1              , 17  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2              , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3              , 19  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0              , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1              , 21  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2              , 22  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3              , 23  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_0              , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_1              , 25  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_2              , 26  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_3              , 27  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_4              , 28  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_5              , 29  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_6              , 30  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_7              , 31  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_0              , 32  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_1              , 33  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_2              , 34  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_3              , 35  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_4              , 36  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_5              , 37  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_6              , 38  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_7              , 39  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_8              , 40  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_8 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_9              , 41  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_9 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_10             , 42  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_10 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_11             , 43  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_11 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_0              , 44  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_1              , 45  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_2              , 46  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_3              , 47  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_4              , 48  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_5              , 49  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_6              , 50  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_7              , 51  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_8              , 52  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_8 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_9              , 53  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_9 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_10             , 54  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_10 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_11             , 55  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_11 );
+
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             , 5   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_8 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             , 9   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_9 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_10 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            , 11  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_11 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_12 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            , 13  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_13 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            , 14  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_14 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            , 15  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_15 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0              , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1              , 17  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2              , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3              , 19  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0              , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1              , 21  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2              , 22  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3              , 23  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_0              , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_1              , 25  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_2              , 26  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_3              , 27  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_4              , 28  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_5              , 29  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_6              , 30  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_7              , 31  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_0              , 32  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_1              , 33  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_2              , 34  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_3              , 35  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_4              , 36  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_5              , 37  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_6              , 38  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_7              , 39  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_8              , 40  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_8 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_9              , 41  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_9 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_10             , 42  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_10 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_11             , 43  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_11 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_0              , 44  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_1              , 45  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_2              , 46  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_3              , 47  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_4              , 48  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_5              , 49  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_6              , 50  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_7              , 51  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_8              , 52  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_8 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_9              , 53  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_9 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_10             , 54  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_10 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_11             , 55  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_11 );
+
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             , 5   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_8 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             , 9   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_9 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_10 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            , 11  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_11 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_12 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            , 13  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_13 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            , 14  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_14 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            , 15  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_15 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0              , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1              , 17  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2              , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3              , 19  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0              , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1              , 21  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2              , 22  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3              , 23  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_0              , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_1              , 25  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_2              , 26  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_3              , 27  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_4              , 28  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_5              , 29  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_6              , 30  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_7              , 31  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_0              , 32  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_1              , 33  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_2              , 34  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_3              , 35  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_4              , 36  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_5              , 37  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_6              , 38  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_7              , 39  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_8              , 40  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_8 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_9              , 41  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_9 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_10             , 42  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_10 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_11             , 43  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_11 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_0              , 44  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_1              , 45  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_2              , 46  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_3              , 47  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_4              , 48  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_5              , 49  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_6              , 50  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_7              , 51  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_8              , 52  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_8 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_9              , 53  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_9 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_10             , 54  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_10 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_11             , 55  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_11 );
+
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_0             , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_1             , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_2             , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_3             , 3   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_4             , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_5             , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_6             , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_7             , 7   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_8             , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_8 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_9             , 9   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_9 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_10            , 10  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_10 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_11            , 11  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_11 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_12            , 12  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_12 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_13            , 13  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_13 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_14            , 14  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_14 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_15            , 15  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_15 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_0             , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_1             , 17  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_2             , 18  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_3             , 19  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_4             , 20  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_5             , 21  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_6             , 22  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_7             , 23  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_0             , 24  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_1             , 25  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_2             , 26  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_3             , 27  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_4             , 28  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_5             , 29  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_6             , 30  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_7             , 31  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_0             , 32  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_1             , 33  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_2             , 34  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_3             , 35  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_4             , 36  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_5             , 37  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_6             , 38  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_7             , 39  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_0             , 40  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_1             , 41  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_2             , 42  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_3             , 43  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_4             , 44  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_5             , 45  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_6             , 46  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_7             , 47  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_0             , 48  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_1             , 49  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_2             , 50  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_3             , 51  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_4             , 52  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_4 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_5             , 53  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_5 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_6             , 54  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_6 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_7             , 55  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_7 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_0            , 56  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV2_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_1            , 57  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV2_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_2            , 58  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV2_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_3            , 59  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV2_3 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_0            , 60  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV3_0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_1            , 61  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV3_1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_2            , 62  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV3_2 );
+REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_3            , 63  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV3_3 );
+
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             , 5   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_8 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             , 9   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_9 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_10 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            , 11  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_11 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_12 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            , 13  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_13 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            , 14  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_14 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            , 15  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_15 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_0              , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_1              , 17  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_2              , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_3              , 19  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_0              , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_1              , 21  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_2              , 22  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_3              , 23  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_0              , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_1              , 25  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_2              , 26  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_3              , 27  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_4              , 28  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_5              , 29  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_6              , 30  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_7              , 31  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_0              , 32  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_1              , 33  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_2              , 34  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_3              , 35  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_4              , 36  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_5              , 37  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_6              , 38  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_7              , 39  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_8              , 40  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_8 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_9              , 41  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_9 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_10             , 42  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_10 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_11             , 43  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_11 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_0              , 44  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_1              , 45  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_2              , 46  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_3              , 47  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_4              , 48  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_5              , 49  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_6              , 50  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_7              , 51  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_8              , 52  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_8 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_9              , 53  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_9 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_10             , 54  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_10 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_11             , 55  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_11 );
+
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             , 5   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_8 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             , 9   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_9 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_10 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            , 11  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_11 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_12 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            , 13  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_13 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            , 14  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_14 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            , 15  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_15 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0              , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1              , 17  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2              , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3              , 19  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0              , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1              , 21  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2              , 22  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3              , 23  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_0              , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_1              , 25  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_2              , 26  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_3              , 27  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_4              , 28  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_5              , 29  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_6              , 30  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_7              , 31  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_0              , 32  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_1              , 33  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_2              , 34  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_3              , 35  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_4              , 36  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_5              , 37  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_6              , 38  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_7              , 39  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_8              , 40  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_8 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_9              , 41  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_9 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_10             , 42  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_10 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_11             , 43  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_11 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_0              , 44  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_1              , 45  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_2              , 46  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_3              , 47  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_4              , 48  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_5              , 49  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_6              , 50  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_7              , 51  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_8              , 52  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_8 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_9              , 53  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_9 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_10             , 54  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_10 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_11             , 55  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_11 );
+
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_0             , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_1             , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_2             , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_3             , 3   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_4             , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_5             , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_6             , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_7             , 7   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_8             , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_8 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_9             , 9   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_9 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_10            , 10  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_10 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_11            , 11  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_11 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_12            , 12  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_12 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_13            , 13  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_13 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_14            , 14  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_14 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_15            , 15  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_NLG_15 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_0             , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_1             , 17  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_2             , 18  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_3             , 19  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_4             , 20  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_5             , 21  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_6             , 22  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_7             , 23  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_FWD_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_0             , 24  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_1             , 25  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_2             , 26  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_3             , 27  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_4             , 28  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_5             , 29  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_6             , 30  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_7             , 31  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_AUE_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_0             , 32  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_1             , 33  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_2             , 34  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_3             , 35  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_4             , 36  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_5             , 37  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_6             , 38  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_7             , 39  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBP_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_0             , 40  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_1             , 41  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_2             , 42  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_3             , 43  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_4             , 44  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_5             , 45  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_6             , 46  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_7             , 47  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBF_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_0             , 48  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_1             , 49  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_2             , 50  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_3             , 51  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_4             , 52  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_4 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_5             , 53  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_5 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_6             , 54  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_6 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_7             , 55  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_PBC_7 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_0            , 56  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV2_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_1            , 57  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV2_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_2            , 58  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV2_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_3            , 59  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV2_3 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_0            , 60  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV3_0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_1            , 61  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV3_1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_2            , 62  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV3_2 );
+REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_3            , 63  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CTL_MASK_RSV3_3 );
+
+REG64_FLD( NV_CERR_MASK1_NTL_0                                     , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( NV_CERR_MASK1_NTL_1                                     , 1   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( NV_CERR_MASK1_NTL_2                                     , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( NV_CERR_MASK1_NTL_3                                     , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( NV_CERR_MASK1_NTL_4                                     , 4   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( NV_CERR_MASK1_NTL_5                                     , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( NV_CERR_MASK1_NTL_6                                     , 6   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( NV_CERR_MASK1_NTL_7                                     , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( NV_CERR_MASK1_NTL_8                                     , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( NV_CERR_MASK1_NTL_9                                     , 9   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( NV_CERR_MASK1_NTL_10                                    , 10  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( NV_CERR_MASK1_NTL_11                                    , 11  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( NV_CERR_MASK1_NTL_12                                    , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( NV_CERR_MASK1_NTL_13                                    , 13  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( NV_CERR_MASK1_NTL_14                                    , 14  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( NV_CERR_MASK1_NTL_15                                    , 15  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( NV_CERR_MASK1_NTL_16                                    , 16  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( NV_CERR_MASK1_NTL_17                                    , 17  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( NV_CERR_MASK1_NTL_18                                    , 18  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( NV_CERR_MASK1_NTL_19                                    , 19  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( NV_CERR_MASK1_NTL_20                                    , 20  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( NV_CERR_MASK1_NTL_21                                    , 21  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( NV_CERR_MASK1_NTL_22                                    , 22  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( NV_CERR_MASK1_NTL_23                                    , 23  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( NV_CERR_MASK1_NTL_24                                    , 24  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( NV_CERR_MASK1_NTL_25                                    , 25  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( NV_CERR_MASK1_NTL_26                                    , 26  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( NV_CERR_MASK1_NTL_27                                    , 27  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( NV_CERR_MASK1_NTL_28                                    , 28  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( NV_CERR_MASK1_NTL_29                                    , 29  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( NV_CERR_MASK1_NTL_30                                    , 30  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( NV_CERR_MASK1_NTL_31                                    , 31  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( NV_CERR_MASK1_NTL_32                                    , 32  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( NV_CERR_MASK1_NTL_33                                    , 33  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( NV_CERR_MASK1_NTL_34                                    , 34  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( NV_CERR_MASK1_NTL_35                                    , 35  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( NV_CERR_MASK1_NTL_36                                    , 36  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( NV_CERR_MASK1_NTL_37                                    , 37  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( NV_CERR_MASK1_NTL_38                                    , 38  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( NV_CERR_MASK1_NTL_39                                    , 39  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( NV_CERR_MASK1_NTL_40                                    , 40  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( NV_CERR_MASK1_NTL_41                                    , 41  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( NV_CERR_MASK1_NTL_42                                    , 42  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( NV_CERR_MASK1_NTL_43                                    , 43  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( NV_CERR_MASK1_NTL_44                                    , 44  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( NV_CERR_MASK1_NTL_45                                    , 45  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( NV_CERR_MASK1_NTL_46                                    , 46  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( NV_CERR_MASK1_NTL_47                                    , 47  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( NV_CERR_MASK1_NTL_48                                    , 48  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( NV_CERR_MASK1_NTL_49                                    , 49  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( NV_CERR_MASK1_NTL_50                                    , 50  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( NV_CERR_MASK1_NTL_51                                    , 51  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( NV_CERR_MASK1_NTL_52                                    , 52  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( NV_CERR_MASK1_NTL_53                                    , 53  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( NV_CERR_MASK1_NTL_54                                    , 54  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( NV_CERR_MASK1_NTL_55                                    , 55  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( NV_CERR_MASK1_NTL_56                                    , 56  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( NV_CERR_MASK1_NTL_57                                    , 57  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( NV_CERR_MASK1_NTL_58                                    , 58  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( NV_CERR_MASK1_NTL_59                                    , 59  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( NV_CERR_MASK1_NTL_60                                    , 60  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( NV_CERR_MASK1_NTL_61                                    , 61  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( NV_CERR_MASK1_NTL_62                                    , 62  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( NV_CERR_MASK1_NTL_63                                    , 63  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0             , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1             , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2             , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3             , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4             , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5             , 5   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6             , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7             , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8             , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_8 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9             , 9   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_9 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10            , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_10 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11            , 11  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_11 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12            , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_12 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13            , 13  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_13 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14            , 14  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_14 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15            , 15  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLGX_15 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0              , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1              , 17  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2              , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3              , 19  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_FWD_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0              , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1              , 21  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2              , 22  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3              , 23  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_AUE_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_0              , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_1              , 25  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_2              , 26  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_3              , 27  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_4              , 28  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_5              , 29  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_6              , 30  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_7              , 31  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBP_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_0              , 32  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_1              , 33  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_2              , 34  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_3              , 35  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_4              , 36  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_5              , 37  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_6              , 38  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_7              , 39  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_8              , 40  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_8 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_9              , 41  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_9 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_10             , 42  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_10 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_11             , 43  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBF_11 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_0              , 44  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_1              , 45  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_2              , 46  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_3              , 47  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_4              , 48  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_5              , 49  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_6              , 50  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_7              , 51  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_8              , 52  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_8 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_9              , 53  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_9 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_10             , 54  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_10 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_11             , 55  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_PBC_11 );
+
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_0              , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_0 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_1              , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_1 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_2              , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_2 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_3              , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_3 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_4              , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_4 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_5              , 5   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_5 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_6              , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_6 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_7              , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_7 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_8              , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_8 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_9              , 9   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_9 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_10             , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_10 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_11             , 11  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_11 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_12             , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_12 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_13             , 13  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_13 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_14             , 14  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_14 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_15             , 15  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_15 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_16             , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_16 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_17             , 17  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_17 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_18             , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_18 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_19             , 19  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_19 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_20             , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_20 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_21             , 21  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_21 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_22             , 22  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_22 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_23             , 23  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_23 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_24             , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_24 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_25             , 25  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_25 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_26             , 26  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_26 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_27             , 27  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_27 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_28             , 28  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_28 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_29             , 29  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_29 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_30             , 30  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_30 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_31             , 31  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_31 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_32             , 32  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_32 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_33             , 33  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_33 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_34             , 34  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_34 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_35             , 35  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_35 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_36             , 36  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_36 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_37             , 37  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_37 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_38             , 38  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_38 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_39             , 39  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_39 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_40             , 40  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_40 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_41             , 41  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_41 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_42             , 42  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_42 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_43             , 43  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_43 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_44             , 44  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_44 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_45             , 45  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_45 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_46             , 46  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_46 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_47             , 47  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_47 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_48             , 48  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_48 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_49             , 49  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_49 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_50             , 50  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_50 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_51             , 51  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_51 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_52             , 52  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_52 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_53             , 53  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_53 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_54             , 54  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_54 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_55             , 55  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_55 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_56             , 56  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_56 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_57             , 57  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_57 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_58             , 58  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_58 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_59             , 59  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_59 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_60             , 60  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_60 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_61             , 61  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_61 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_62             , 62  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_62 );
+REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_63             , 63  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_63 );
+
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_0                           , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_1                           , 1   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_2                           , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_3                           , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_4                           , 4   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_5                           , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_6                           , 6   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_7                           , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_8                           , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_9                           , 9   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_10                          , 10  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_11                          , 11  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_12                          , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_13                          , 13  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_14                          , 14  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_15                          , 15  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_16                          , 16  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_17                          , 17  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_18                          , 18  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_19                          , 19  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_20                          , 20  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_21                          , 21  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_22                          , 22  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_23                          , 23  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_24                          , 24  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_25                          , 25  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_26                          , 26  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_27                          , 27  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_28                          , 28  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_29                          , 29  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_30                          , 30  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_31                          , 31  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_32                          , 32  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_33                          , 33  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_34                          , 34  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_35                          , 35  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_36                          , 36  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_37                          , 37  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_38                          , 38  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_39                          , 39  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_40                          , 40  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_41                          , 41  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_42                          , 42  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_43                          , 43  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_44                          , 44  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_45                          , 45  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_46                          , 46  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_47                          , 47  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_48                          , 48  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_49                          , 49  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_50                          , 50  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_51                          , 51  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_52                          , 52  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_53                          , 53  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_54                          , 54  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_55                          , 55  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_56                          , 56  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_57                          , 57  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_58                          , 58  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_59                          , 59  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_60                          , 60  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_61                          , 61  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_62                          , 62  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_63                          , 63  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_0              , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_0 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_1              , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_1 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_2              , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_2 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_3              , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_3 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_4              , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_4 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_5              , 5   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_5 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_6              , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_6 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_7              , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_7 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_8              , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_8 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_9              , 9   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_9 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_10             , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_10 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_11             , 11  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_11 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_12             , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_12 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_13             , 13  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_13 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_14             , 14  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_14 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_15             , 15  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_15 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_16             , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_16 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_17             , 17  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_17 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_18             , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_18 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_19             , 19  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_19 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_20             , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_20 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_21             , 21  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_21 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_22             , 22  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_22 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_23             , 23  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_23 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_24             , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_24 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_25             , 25  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_25 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_26             , 26  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_26 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_27             , 27  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_27 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_28             , 28  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_28 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_29             , 29  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_29 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_30             , 30  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_30 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_31             , 31  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_31 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_32             , 32  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_32 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_33             , 33  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_33 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_34             , 34  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_34 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_35             , 35  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_35 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_36             , 36  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_36 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_37             , 37  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_37 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_38             , 38  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_38 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_39             , 39  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_39 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_40             , 40  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_40 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_41             , 41  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_41 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_42             , 42  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_42 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_43             , 43  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_43 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_44             , 44  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_44 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_45             , 45  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_45 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_46             , 46  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_46 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_47             , 47  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_47 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_48             , 48  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_48 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_49             , 49  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_49 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_50             , 50  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_50 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_51             , 51  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_51 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_52             , 52  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_52 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_53             , 53  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_53 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_54             , 54  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_54 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_55             , 55  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_55 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_56             , 56  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_56 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_57             , 57  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_57 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_58             , 58  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_58 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_59             , 59  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_59 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_60             , 60  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_60 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_61             , 61  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_61 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_62             , 62  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_62 );
+REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_63             , 63  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_63 );
+
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_0              , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_0 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_1              , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_1 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_2              , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_2 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_3              , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_3 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_4              , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_4 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_5              , 5   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_5 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_6              , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_6 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_7              , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_7 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_8              , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_8 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_9              , 9   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_9 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_10             , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_10 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_11             , 11  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_11 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_12             , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_12 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_13             , 13  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_13 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_14             , 14  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_14 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_15             , 15  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_15 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_16             , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_16 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_17             , 17  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_17 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_18             , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_18 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_19             , 19  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_19 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_20             , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_20 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_21             , 21  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_21 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_22             , 22  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_22 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_23             , 23  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_23 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_24             , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_24 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_25             , 25  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_25 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_26             , 26  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_26 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_27             , 27  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_27 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_28             , 28  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_28 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_29             , 29  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_29 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_30             , 30  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_30 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_31             , 31  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_31 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_32             , 32  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_32 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_33             , 33  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_33 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_34             , 34  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_34 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_35             , 35  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_35 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_36             , 36  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_36 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_37             , 37  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_37 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_38             , 38  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_38 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_39             , 39  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_39 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_40             , 40  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_40 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_41             , 41  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_41 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_42             , 42  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_42 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_43             , 43  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_43 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_44             , 44  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_44 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_45             , 45  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_45 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_46             , 46  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_46 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_47             , 47  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_47 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_48             , 48  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_48 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_49             , 49  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_49 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_50             , 50  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_50 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_51             , 51  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_51 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_52             , 52  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_52 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_53             , 53  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_53 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_54             , 54  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_54 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_55             , 55  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_55 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_56             , 56  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_56 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_57             , 57  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_57 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_58             , 58  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_58 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_59             , 59  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_59 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_60             , 60  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_60 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_61             , 61  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_61 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_62             , 62  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_62 );
+REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_63             , 63  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_63 );
+
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_0              , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_0 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_1              , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_1 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_2              , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_2 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_3              , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_3 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_4              , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_4 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_5              , 5   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_5 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_6              , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_6 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_7              , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_7 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_8              , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_8 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_9              , 9   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_9 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_10             , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_10 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_11             , 11  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_11 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_12             , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_12 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_13             , 13  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_13 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_14             , 14  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_14 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_15             , 15  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_15 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_16             , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_16 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_17             , 17  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_17 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_18             , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_18 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_19             , 19  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_19 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_20             , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_20 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_21             , 21  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_21 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_22             , 22  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_22 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_23             , 23  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_23 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_24             , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_24 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_25             , 25  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_25 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_26             , 26  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_26 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_27             , 27  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_27 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_28             , 28  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_28 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_29             , 29  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_29 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_30             , 30  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_30 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_31             , 31  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_31 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_32             , 32  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_32 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_33             , 33  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_33 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_34             , 34  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_34 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_35             , 35  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_35 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_36             , 36  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_36 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_37             , 37  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_37 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_38             , 38  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_38 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_39             , 39  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_39 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_40             , 40  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_40 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_41             , 41  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_41 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_42             , 42  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_42 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_43             , 43  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_43 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_44             , 44  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_44 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_45             , 45  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_45 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_46             , 46  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_46 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_47             , 47  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_47 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_48             , 48  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_48 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_49             , 49  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_49 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_50             , 50  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_50 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_51             , 51  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_51 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_52             , 52  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_52 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_53             , 53  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_53 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_54             , 54  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_54 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_55             , 55  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_55 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_56             , 56  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_56 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_57             , 57  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_57 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_58             , 58  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_58 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_59             , 59  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_59 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_60             , 60  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_60 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_61             , 61  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_61 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_62             , 62  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_62 );
+REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_63             , 63  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_63 );
+
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_0              , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_0 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_1              , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_1 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_2              , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_2 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_3              , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_3 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_4              , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_4 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_5              , 5   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_5 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_6              , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_6 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_7              , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_7 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_8              , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_8 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_9              , 9   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_9 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_10             , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_10 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_11             , 11  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_11 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_12             , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_12 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_13             , 13  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_13 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_14             , 14  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_14 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_15             , 15  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_15 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_16             , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_16 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_17             , 17  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_17 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_18             , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_18 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_19             , 19  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_19 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_20             , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_20 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_21             , 21  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_21 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_22             , 22  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_22 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_23             , 23  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_23 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_24             , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_24 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_25             , 25  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_25 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_26             , 26  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_26 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_27             , 27  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_27 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_28             , 28  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_28 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_29             , 29  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_29 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_30             , 30  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_30 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_31             , 31  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_31 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_32             , 32  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_32 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_33             , 33  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_33 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_34             , 34  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_34 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_35             , 35  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_35 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_36             , 36  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_36 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_37             , 37  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_37 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_38             , 38  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_38 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_39             , 39  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_39 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_40             , 40  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_40 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_41             , 41  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_41 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_42             , 42  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_42 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_43             , 43  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_43 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_44             , 44  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_44 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_45             , 45  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_45 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_46             , 46  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_46 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_47             , 47  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_47 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_48             , 48  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_48 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_49             , 49  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_49 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_50             , 50  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_50 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_51             , 51  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_51 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_52             , 52  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_52 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_53             , 53  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_53 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_54             , 54  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_54 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_55             , 55  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_55 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_56             , 56  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_56 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_57             , 57  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_57 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_58             , 58  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_58 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_59             , 59  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_59 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_60             , 60  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_60 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_61             , 61  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_61 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_62             , 62  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_62 );
+REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_63             , 63  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_63 );
+
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_0                           , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_1                           , 1   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_2                           , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_3                           , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_4                           , 4   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_5                           , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_6                           , 6   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_7                           , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_8                           , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_9                           , 9   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_10                          , 10  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_11                          , 11  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_12                          , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_13                          , 13  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_14                          , 14  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_15                          , 15  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_16                          , 16  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_17                          , 17  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_18                          , 18  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_19                          , 19  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_20                          , 20  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_21                          , 21  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_22                          , 22  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_23                          , 23  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_24                          , 24  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_25                          , 25  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_26                          , 26  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_27                          , 27  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_28                          , 28  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_29                          , 29  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_30                          , 30  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_31                          , 31  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_32                          , 32  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_33                          , 33  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_34                          , 34  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_35                          , 35  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_36                          , 36  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_37                          , 37  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_38                          , 38  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_39                          , 39  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_40                          , 40  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_41                          , 41  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_42                          , 42  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_43                          , 43  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_44                          , 44  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_45                          , 45  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_46                          , 46  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_47                          , 47  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_48                          , 48  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_49                          , 49  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_50                          , 50  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_51                          , 51  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_52                          , 52  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_53                          , 53  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_54                          , 54  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_55                          , 55  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_56                          , 56  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_57                          , 57  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_58                          , 58  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_59                          , 59  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_60                          , 60  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_61                          , 61  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_62                          , 62  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_63                          , 63  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_0              , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_0 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_1              , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_1 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_2              , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_2 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_3              , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_3 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_4              , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_4 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_5              , 5   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_5 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_6              , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_6 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_7              , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_7 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_8              , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_8 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_9              , 9   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_9 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_10             , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_10 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_11             , 11  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_11 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_12             , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_12 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_13             , 13  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_13 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_14             , 14  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_14 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_15             , 15  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_15 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_16             , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_16 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_17             , 17  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_17 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_18             , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_18 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_19             , 19  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_19 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_20             , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_20 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_21             , 21  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_21 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_22             , 22  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_22 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_23             , 23  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_23 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_24             , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_24 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_25             , 25  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_25 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_26             , 26  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_26 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_27             , 27  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_27 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_28             , 28  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_28 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_29             , 29  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_29 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_30             , 30  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_30 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_31             , 31  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_31 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_32             , 32  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_32 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_33             , 33  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_33 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_34             , 34  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_34 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_35             , 35  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_35 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_36             , 36  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_36 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_37             , 37  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_37 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_38             , 38  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_38 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_39             , 39  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_39 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_40             , 40  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_40 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_41             , 41  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_41 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_42             , 42  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_42 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_43             , 43  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_43 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_44             , 44  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_44 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_45             , 45  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_45 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_46             , 46  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_46 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_47             , 47  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_47 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_48             , 48  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_48 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_49             , 49  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_49 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_50             , 50  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_50 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_51             , 51  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_51 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_52             , 52  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_52 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_53             , 53  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_53 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_54             , 54  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_54 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_55             , 55  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_55 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_56             , 56  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_56 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_57             , 57  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_57 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_58             , 58  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_58 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_59             , 59  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_59 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_60             , 60  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_60 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_61             , 61  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_61 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_62             , 62  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_62 );
+REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_63             , 63  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_63 );
+
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_0              , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_0 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_1              , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_1 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_2              , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_2 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_3              , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_3 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_4              , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_4 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_5              , 5   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_5 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_6              , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_6 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_7              , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_7 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_8              , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_8 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_9              , 9   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_9 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_10             , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_10 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_11             , 11  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_11 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_12             , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_12 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_13             , 13  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_13 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_14             , 14  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_14 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_15             , 15  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_15 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_16             , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_16 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_17             , 17  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_17 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_18             , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_18 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_19             , 19  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_19 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_20             , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_20 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_21             , 21  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_21 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_22             , 22  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_22 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_23             , 23  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_23 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_24             , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_24 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_25             , 25  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_25 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_26             , 26  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_26 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_27             , 27  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_27 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_28             , 28  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_28 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_29             , 29  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_29 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_30             , 30  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_30 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_31             , 31  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_31 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_32             , 32  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_32 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_33             , 33  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_33 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_34             , 34  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_34 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_35             , 35  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_35 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_36             , 36  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_36 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_37             , 37  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_37 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_38             , 38  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_38 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_39             , 39  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_39 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_40             , 40  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_40 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_41             , 41  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_41 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_42             , 42  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_42 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_43             , 43  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_43 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_44             , 44  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_44 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_45             , 45  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_45 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_46             , 46  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_46 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_47             , 47  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_47 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_48             , 48  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_48 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_49             , 49  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_49 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_50             , 50  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_50 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_51             , 51  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_51 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_52             , 52  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_52 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_53             , 53  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_53 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_54             , 54  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_54 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_55             , 55  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_55 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_56             , 56  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_56 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_57             , 57  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_57 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_58             , 58  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_58 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_59             , 59  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_59 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_60             , 60  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_60 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_61             , 61  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_61 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_62             , 62  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_62 );
+REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_63             , 63  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_63 );
+
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_0              , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_0 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_1              , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_1 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_2              , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_2 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_3              , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_3 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_4              , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_4 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_5              , 5   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_5 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_6              , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_6 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_7              , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_7 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_8              , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_8 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_9              , 9   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_9 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_10             , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_10 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_11             , 11  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_11 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_12             , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_12 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_13             , 13  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_13 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_14             , 14  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_14 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_15             , 15  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_15 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_16             , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_16 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_17             , 17  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_17 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_18             , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_18 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_19             , 19  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_19 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_20             , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_20 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_21             , 21  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_21 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_22             , 22  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_22 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_23             , 23  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_23 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_24             , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_24 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_25             , 25  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_25 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_26             , 26  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_26 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_27             , 27  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_27 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_28             , 28  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_28 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_29             , 29  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_29 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_30             , 30  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_30 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_31             , 31  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_31 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_32             , 32  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_32 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_33             , 33  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_33 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_34             , 34  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_34 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_35             , 35  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_35 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_36             , 36  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_36 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_37             , 37  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_37 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_38             , 38  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_38 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_39             , 39  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_39 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_40             , 40  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_40 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_41             , 41  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_41 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_42             , 42  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_42 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_43             , 43  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_43 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_44             , 44  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_44 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_45             , 45  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_45 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_46             , 46  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_46 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_47             , 47  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_47 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_48             , 48  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_48 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_49             , 49  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_49 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_50             , 50  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_50 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_51             , 51  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_51 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_52             , 52  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_52 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_53             , 53  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_53 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_54             , 54  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_54 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_55             , 55  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_55 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_56             , 56  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_56 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_57             , 57  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_57 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_58             , 58  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_58 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_59             , 59  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_59 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_60             , 60  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_60 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_61             , 61  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_61 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_62             , 62  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_62 );
+REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_63             , 63  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_63 );
+
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_0              , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_0 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_1              , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_1 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_2              , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_2 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_3              , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_3 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_4              , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_4 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_5              , 5   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_5 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_6              , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_6 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_7              , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_7 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_8              , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_8 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_9              , 9   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_9 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_10             , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_10 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_11             , 11  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_11 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_12             , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_12 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_13             , 13  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_13 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_14             , 14  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_14 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_15             , 15  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_15 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_16             , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_16 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_17             , 17  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_17 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_18             , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_18 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_19             , 19  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_19 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_20             , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_20 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_21             , 21  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_21 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_22             , 22  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_22 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_23             , 23  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_23 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_24             , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_24 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_25             , 25  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_25 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_26             , 26  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_26 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_27             , 27  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_27 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_28             , 28  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_28 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_29             , 29  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_29 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_30             , 30  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_30 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_31             , 31  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_31 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_32             , 32  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_32 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_33             , 33  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_33 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_34             , 34  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_34 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_35             , 35  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_35 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_36             , 36  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_36 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_37             , 37  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_37 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_38             , 38  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_38 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_39             , 39  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_39 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_40             , 40  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_40 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_41             , 41  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_41 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_42             , 42  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_42 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_43             , 43  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_43 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_44             , 44  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_44 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_45             , 45  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_45 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_46             , 46  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_46 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_47             , 47  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_47 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_48             , 48  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_48 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_49             , 49  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_49 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_50             , 50  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_50 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_51             , 51  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_51 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_52             , 52  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_52 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_53             , 53  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_53 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_54             , 54  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_54 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_55             , 55  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_55 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_56             , 56  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_56 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_57             , 57  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_57 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_58             , 58  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_58 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_59             , 59  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_59 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_60             , 60  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_60 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_61             , 61  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_61 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_62             , 62  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_62 );
+REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_63             , 63  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_63 );
+
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_0              , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_0 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_1              , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_1 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_2              , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_2 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_3              , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_3 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_4              , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_4 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_5              , 5   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_5 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_6              , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_6 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_7              , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_7 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_8              , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_8 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_9              , 9   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_9 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_10             , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_10 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_11             , 11  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_11 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_12             , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_12 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_13             , 13  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_13 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_14             , 14  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_14 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_15             , 15  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_15 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_16             , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_16 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_17             , 17  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_17 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_18             , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_18 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_19             , 19  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_19 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_20             , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_20 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_21             , 21  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_21 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_22             , 22  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_22 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_23             , 23  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_23 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_24             , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_24 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_25             , 25  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_25 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_26             , 26  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_26 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_27             , 27  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_27 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_28             , 28  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_28 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_29             , 29  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_29 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_30             , 30  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_30 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_31             , 31  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_31 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_32             , 32  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_32 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_33             , 33  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_33 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_34             , 34  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_34 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_35             , 35  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_35 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_36             , 36  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_36 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_37             , 37  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_37 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_38             , 38  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_38 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_39             , 39  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_39 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_40             , 40  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_40 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_41             , 41  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_41 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_42             , 42  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_42 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_43             , 43  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_43 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_44             , 44  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_44 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_45             , 45  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_45 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_46             , 46  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_46 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_47             , 47  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_47 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_48             , 48  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_48 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_49             , 49  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_49 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_50             , 50  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_50 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_51             , 51  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_51 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_52             , 52  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_52 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_53             , 53  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_53 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_54             , 54  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_54 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_55             , 55  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_55 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_56             , 56  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_56 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_57             , 57  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_57 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_58             , 58  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_58 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_59             , 59  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_59 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_60             , 60  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_60 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_61             , 61  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_61 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_62             , 62  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_62 );
+REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_63             , 63  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_63 );
+
+REG64_FLD( NV_CERR_MASK2_NTL_0                                     , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_0      );
+REG64_FLD( NV_CERR_MASK2_NTL_1                                     , 1   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_1      );
+REG64_FLD( NV_CERR_MASK2_NTL_2                                     , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_2      );
+REG64_FLD( NV_CERR_MASK2_NTL_3                                     , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_3      );
+REG64_FLD( NV_CERR_MASK2_NTL_4                                     , 4   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_4      );
+REG64_FLD( NV_CERR_MASK2_NTL_5                                     , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_5      );
+REG64_FLD( NV_CERR_MASK2_NTL_6                                     , 6   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_6      );
+REG64_FLD( NV_CERR_MASK2_NTL_7                                     , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_7      );
+REG64_FLD( NV_CERR_MASK2_NTL_8                                     , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_8      );
+REG64_FLD( NV_CERR_MASK2_NTL_9                                     , 9   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_9      );
+REG64_FLD( NV_CERR_MASK2_NTL_10                                    , 10  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_10     );
+REG64_FLD( NV_CERR_MASK2_NTL_11                                    , 11  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_11     );
+REG64_FLD( NV_CERR_MASK2_NTL_12                                    , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_12     );
+REG64_FLD( NV_CERR_MASK2_NTL_13                                    , 13  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_13     );
+REG64_FLD( NV_CERR_MASK2_NTL_14                                    , 14  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_14     );
+REG64_FLD( NV_CERR_MASK2_NTL_15                                    , 15  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_15     );
+REG64_FLD( NV_CERR_MASK2_NTL_16                                    , 16  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_16     );
+REG64_FLD( NV_CERR_MASK2_NTL_17                                    , 17  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_17     );
+REG64_FLD( NV_CERR_MASK2_NTL_18                                    , 18  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_18     );
+REG64_FLD( NV_CERR_MASK2_NTL_19                                    , 19  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_19     );
+REG64_FLD( NV_CERR_MASK2_NTL_20                                    , 20  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_20     );
+REG64_FLD( NV_CERR_MASK2_NTL_21                                    , 21  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_21     );
+REG64_FLD( NV_CERR_MASK2_NTL_22                                    , 22  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_22     );
+REG64_FLD( NV_CERR_MASK2_NTL_23                                    , 23  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_23     );
+REG64_FLD( NV_CERR_MASK2_NTL_24                                    , 24  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_24     );
+REG64_FLD( NV_CERR_MASK2_NTL_25                                    , 25  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_25     );
+REG64_FLD( NV_CERR_MASK2_NTL_26                                    , 26  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_26     );
+REG64_FLD( NV_CERR_MASK2_NTL_27                                    , 27  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_27     );
+REG64_FLD( NV_CERR_MASK2_NTL_28                                    , 28  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_28     );
+REG64_FLD( NV_CERR_MASK2_NTL_29                                    , 29  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_29     );
+REG64_FLD( NV_CERR_MASK2_NTL_30                                    , 30  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_30     );
+REG64_FLD( NV_CERR_MASK2_NTL_31                                    , 31  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_31     );
+REG64_FLD( NV_CERR_MASK2_NTL_32                                    , 32  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_32     );
+REG64_FLD( NV_CERR_MASK2_NTL_33                                    , 33  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_33     );
+REG64_FLD( NV_CERR_MASK2_NTL_34                                    , 34  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_34     );
+REG64_FLD( NV_CERR_MASK2_NTL_35                                    , 35  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_35     );
+REG64_FLD( NV_CERR_MASK2_NTL_36                                    , 36  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_36     );
+REG64_FLD( NV_CERR_MASK2_NTL_37                                    , 37  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_37     );
+REG64_FLD( NV_CERR_MASK2_NTL_38                                    , 38  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_38     );
+REG64_FLD( NV_CERR_MASK2_NTL_39                                    , 39  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_39     );
+REG64_FLD( NV_CERR_MASK2_NTL_40                                    , 40  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_40     );
+REG64_FLD( NV_CERR_MASK2_NTL_41                                    , 41  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_41     );
+REG64_FLD( NV_CERR_MASK2_NTL_42                                    , 42  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_42     );
+REG64_FLD( NV_CERR_MASK2_NTL_43                                    , 43  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_43     );
+REG64_FLD( NV_CERR_MASK2_NTL_44                                    , 44  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_44     );
+REG64_FLD( NV_CERR_MASK2_NTL_45                                    , 45  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_45     );
+REG64_FLD( NV_CERR_MASK2_NTL_46                                    , 46  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_46     );
+REG64_FLD( NV_CERR_MASK2_NTL_47                                    , 47  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_47     );
+REG64_FLD( NV_CERR_MASK2_NTL_48                                    , 48  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_48     );
+REG64_FLD( NV_CERR_MASK2_NTL_49                                    , 49  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_49     );
+REG64_FLD( NV_CERR_MASK2_NTL_50                                    , 50  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_50     );
+REG64_FLD( NV_CERR_MASK2_NTL_51                                    , 51  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_51     );
+REG64_FLD( NV_CERR_MASK2_NTL_52                                    , 52  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_52     );
+REG64_FLD( NV_CERR_MASK2_NTL_53                                    , 53  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_53     );
+REG64_FLD( NV_CERR_MASK2_NTL_54                                    , 54  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_54     );
+REG64_FLD( NV_CERR_MASK2_NTL_55                                    , 55  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_55     );
+REG64_FLD( NV_CERR_MASK2_NTL_56                                    , 56  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_56     );
+REG64_FLD( NV_CERR_MASK2_NTL_57                                    , 57  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_57     );
+REG64_FLD( NV_CERR_MASK2_NTL_58                                    , 58  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_58     );
+REG64_FLD( NV_CERR_MASK2_NTL_59                                    , 59  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_59     );
+REG64_FLD( NV_CERR_MASK2_NTL_60                                    , 60  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_60     );
+REG64_FLD( NV_CERR_MASK2_NTL_61                                    , 61  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_61     );
+REG64_FLD( NV_CERR_MASK2_NTL_62                                    , 62  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_62     );
+REG64_FLD( NV_CERR_MASK2_NTL_63                                    , 63  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_63     );
+
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_0              , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_0 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_1              , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_1 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_2              , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_2 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_3              , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_3 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_4              , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_4 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_5              , 5   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_5 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_6              , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_6 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_7              , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_7 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_8              , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_8 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_9              , 9   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_9 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_10             , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_10 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_11             , 11  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_11 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_12             , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_12 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_13             , 13  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_13 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_14             , 14  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_14 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_15             , 15  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_15 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_16             , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_16 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_17             , 17  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_17 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_18             , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_18 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_19             , 19  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_19 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_20             , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_20 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_21             , 21  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_21 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_22             , 22  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_22 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_23             , 23  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_23 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_24             , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_24 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_25             , 25  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_25 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_26             , 26  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_26 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_27             , 27  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_27 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_28             , 28  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_28 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_29             , 29  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_29 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_30             , 30  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_30 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_31             , 31  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_31 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_32             , 32  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_32 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_33             , 33  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_33 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_34             , 34  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_34 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_35             , 35  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_35 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_36             , 36  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_36 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_37             , 37  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_37 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_38             , 38  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_38 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_39             , 39  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_39 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_40             , 40  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_40 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_41             , 41  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_41 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_42             , 42  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_42 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_43             , 43  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_43 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_44             , 44  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_44 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_45             , 45  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_45 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_46             , 46  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_46 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_47             , 47  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_47 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_48             , 48  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_48 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_49             , 49  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_49 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_50             , 50  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_50 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_51             , 51  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_51 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_52             , 52  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_52 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_53             , 53  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_53 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_54             , 54  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_54 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_55             , 55  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_55 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_56             , 56  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_56 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_57             , 57  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_57 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_58             , 58  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_58 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_59             , 59  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_59 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_60             , 60  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_60 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_61             , 61  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_61 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_62             , 62  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_62 );
+REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_63             , 63  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_63 );
+
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_0              , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_0 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_1              , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_1 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_2              , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_2 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_3              , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_3 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_4              , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_4 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_5              , 5   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_5 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_6              , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_6 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_7              , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_7 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_8              , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_8 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_9              , 9   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_9 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_10             , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_10 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_11             , 11  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_11 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_12             , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_12 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_13             , 13  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_13 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_14             , 14  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_14 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_15             , 15  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_15 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_16             , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_16 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_17             , 17  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_17 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_18             , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_18 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_19             , 19  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_19 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_20             , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_20 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_21             , 21  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_21 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_22             , 22  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_22 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_23             , 23  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_23 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_24             , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_24 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_25             , 25  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_25 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_26             , 26  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_26 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_27             , 27  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_27 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_28             , 28  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_28 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_29             , 29  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_29 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_30             , 30  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_30 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_31             , 31  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_31 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_32             , 32  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_32 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_33             , 33  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_33 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_34             , 34  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_34 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_35             , 35  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_35 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_36             , 36  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_36 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_37             , 37  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_37 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_38             , 38  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_38 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_39             , 39  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_39 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_40             , 40  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_40 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_41             , 41  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_41 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_42             , 42  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_42 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_43             , 43  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_43 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_44             , 44  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_44 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_45             , 45  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_45 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_46             , 46  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_46 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_47             , 47  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_47 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_48             , 48  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_48 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_49             , 49  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_49 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_50             , 50  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_50 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_51             , 51  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_51 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_52             , 52  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_52 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_53             , 53  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_53 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_54             , 54  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_54 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_55             , 55  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_55 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_56             , 56  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_56 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_57             , 57  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_57 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_58             , 58  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_58 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_59             , 59  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_59 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_60             , 60  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_60 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_61             , 61  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_61 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_62             , 62  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_62 );
+REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_63             , 63  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SM_MASK_NLG_63 );
+
+REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE0_MESSAGE_BITS0                 , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0 );
+REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE0_MESSAGE_BITS0_LEN             , 64  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0_LEN );
+
+REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE0_MESSAGE_BITS0                 , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0 );
+REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE0_MESSAGE_BITS0_LEN             , 64  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0_LEN );
+
+REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE0_MESSAGE_BITS0                 , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0 );
+REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE0_MESSAGE_BITS0_LEN             , 64  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0_LEN );
+
+REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE0_MESSAGE_BITS0                 , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0 );
+REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE0_MESSAGE_BITS0_LEN             , 64  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0_LEN );
+
+REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE0_MESSAGE_BITS0                 , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0 );
+REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE0_MESSAGE_BITS0_LEN             , 64  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0_LEN );
+
+REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE0_MESSAGE_BITS0                 , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0 );
+REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE0_MESSAGE_BITS0_LEN             , 64  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0_LEN );
+
+REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE0_MESSAGE_BITS0                 , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0 );
+REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE0_MESSAGE_BITS0_LEN             , 64  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0_LEN );
+
+REG64_FLD( PU_NPU1_CTL_CERR_MESSAGE0_MESSAGE_BITS0                 , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0 );
+REG64_FLD( PU_NPU1_CTL_CERR_MESSAGE0_MESSAGE_BITS0_LEN             , 64  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0_LEN );
+
+REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE0_MESSAGE_BITS0                 , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0 );
+REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE0_MESSAGE_BITS0_LEN             , 64  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0_LEN );
+
+REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE0_MESSAGE_BITS0                 , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0 );
+REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE0_MESSAGE_BITS0_LEN             , 64  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0_LEN );
+
+REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE0_MESSAGE_BITS0                 , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0 );
+REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE0_MESSAGE_BITS0_LEN             , 64  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0_LEN );
+
+REG64_FLD( PU_NPU0_CTL_CERR_MESSAGE0_MESSAGE_BITS0                 , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0 );
+REG64_FLD( PU_NPU0_CTL_CERR_MESSAGE0_MESSAGE_BITS0_LEN             , 64  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0_LEN );
+
+REG64_FLD( PU_NPU2_CTL_CERR_MESSAGE0_MESSAGE_BITS0                 , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0 );
+REG64_FLD( PU_NPU2_CTL_CERR_MESSAGE0_MESSAGE_BITS0_LEN             , 64  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0_LEN );
+
+REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE0_MESSAGE_BITS0                 , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0 );
+REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE0_MESSAGE_BITS0_LEN             , 64  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0_LEN );
+
+REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE0_MESSAGE_BITS0                 , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0 );
+REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE0_MESSAGE_BITS0_LEN             , 64  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS0_LEN );
+
+REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE1_MESSAGE_BITS1                 , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1 );
+REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE1_MESSAGE_BITS1_LEN             , 64  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1_LEN );
+
+REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE1_MESSAGE_BITS1                 , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1 );
+REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE1_MESSAGE_BITS1_LEN             , 64  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1_LEN );
+
+REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE1_MESSAGE_BITS1                 , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1 );
+REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE1_MESSAGE_BITS1_LEN             , 64  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1_LEN );
+
+REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE1_MESSAGE_BITS1                 , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1 );
+REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE1_MESSAGE_BITS1_LEN             , 64  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1_LEN );
+
+REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE1_MESSAGE_BITS1                 , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1 );
+REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE1_MESSAGE_BITS1_LEN             , 64  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1_LEN );
+
+REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE1_MESSAGE_BITS1                 , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1 );
+REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE1_MESSAGE_BITS1_LEN             , 64  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1_LEN );
+
+REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE1_MESSAGE_BITS1                 , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1 );
+REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE1_MESSAGE_BITS1_LEN             , 64  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1_LEN );
+
+REG64_FLD( PU_NPU1_CTL_CERR_MESSAGE1_MESSAGE_BITS1                 , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1 );
+REG64_FLD( PU_NPU1_CTL_CERR_MESSAGE1_MESSAGE_BITS1_LEN             , 64  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1_LEN );
+
+REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE1_MESSAGE_BITS1                 , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1 );
+REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE1_MESSAGE_BITS1_LEN             , 64  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1_LEN );
+
+REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE1_MESSAGE_BITS1                 , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1 );
+REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE1_MESSAGE_BITS1_LEN             , 64  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1_LEN );
+
+REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE1_MESSAGE_BITS1                 , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1 );
+REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE1_MESSAGE_BITS1_LEN             , 64  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1_LEN );
+
+REG64_FLD( PU_NPU0_CTL_CERR_MESSAGE1_MESSAGE_BITS1                 , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1 );
+REG64_FLD( PU_NPU0_CTL_CERR_MESSAGE1_MESSAGE_BITS1_LEN             , 64  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1_LEN );
+
+REG64_FLD( PU_NPU2_CTL_CERR_MESSAGE1_MESSAGE_BITS1                 , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1 );
+REG64_FLD( PU_NPU2_CTL_CERR_MESSAGE1_MESSAGE_BITS1_LEN             , 64  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1_LEN );
+
+REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE1_MESSAGE_BITS1                 , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1 );
+REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE1_MESSAGE_BITS1_LEN             , 64  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1_LEN );
+
+REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE1_MESSAGE_BITS1                 , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1 );
+REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE1_MESSAGE_BITS1_LEN             , 64  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS1_LEN );
+
+REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE2_MESSAGE_BITS2                 , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2 );
+REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE2_MESSAGE_BITS2_LEN             , 64  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2_LEN );
+
+REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE2_MESSAGE_BITS2                 , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2 );
+REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE2_MESSAGE_BITS2_LEN             , 64  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2_LEN );
+
+REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE2_MESSAGE_BITS2                 , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2 );
+REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE2_MESSAGE_BITS2_LEN             , 64  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2_LEN );
+
+REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE2_MESSAGE_BITS2                 , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2 );
+REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE2_MESSAGE_BITS2_LEN             , 64  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2_LEN );
+
+REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE2_MESSAGE_BITS2                 , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2 );
+REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE2_MESSAGE_BITS2_LEN             , 64  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2_LEN );
+
+REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE2_MESSAGE_BITS2                 , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2 );
+REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE2_MESSAGE_BITS2_LEN             , 64  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2_LEN );
+
+REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE2_MESSAGE_BITS2                 , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2 );
+REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE2_MESSAGE_BITS2_LEN             , 64  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2_LEN );
+
+REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE2_MESSAGE_BITS2                 , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2 );
+REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE2_MESSAGE_BITS2_LEN             , 64  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2_LEN );
+
+REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE2_MESSAGE_BITS2                 , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2 );
+REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE2_MESSAGE_BITS2_LEN             , 64  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2_LEN );
+
+REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE2_MESSAGE_BITS2                 , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2 );
+REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE2_MESSAGE_BITS2_LEN             , 64  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2_LEN );
+
+REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE2_MESSAGE_BITS2                 , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2 );
+REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE2_MESSAGE_BITS2_LEN             , 64  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2_LEN );
+
+REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE2_MESSAGE_BITS2                 , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2 );
+REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE2_MESSAGE_BITS2_LEN             , 64  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS2_LEN );
+
+REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE3_MESSAGE_BITS3                 , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3 );
+REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE3_MESSAGE_BITS3_LEN             , 64  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3_LEN );
+
+REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE3_MESSAGE_BITS3                 , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3 );
+REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE3_MESSAGE_BITS3_LEN             , 64  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3_LEN );
+
+REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE3_MESSAGE_BITS3                 , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3 );
+REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE3_MESSAGE_BITS3_LEN             , 64  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3_LEN );
+
+REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE3_MESSAGE_BITS3                 , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3 );
+REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE3_MESSAGE_BITS3_LEN             , 64  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3_LEN );
+
+REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE3_MESSAGE_BITS3                 , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3 );
+REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE3_MESSAGE_BITS3_LEN             , 64  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3_LEN );
+
+REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE3_MESSAGE_BITS3                 , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3 );
+REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE3_MESSAGE_BITS3_LEN             , 64  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3_LEN );
+
+REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE3_MESSAGE_BITS3                 , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3 );
+REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE3_MESSAGE_BITS3_LEN             , 64  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3_LEN );
+
+REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE3_MESSAGE_BITS3                 , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3 );
+REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE3_MESSAGE_BITS3_LEN             , 64  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3_LEN );
+
+REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE3_MESSAGE_BITS3                 , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3 );
+REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE3_MESSAGE_BITS3_LEN             , 64  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3_LEN );
+
+REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE3_MESSAGE_BITS3                 , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3 );
+REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE3_MESSAGE_BITS3_LEN             , 64  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3_LEN );
+
+REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE3_MESSAGE_BITS3                 , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3 );
+REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE3_MESSAGE_BITS3_LEN             , 64  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3_LEN );
+
+REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE3_MESSAGE_BITS3                 , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3 );
+REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE3_MESSAGE_BITS3_LEN             , 64  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS3_LEN );
+
+REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE4_MESSAGE_BITS4                 , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4 );
+REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE4_MESSAGE_BITS4_LEN             , 64  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4_LEN );
+
+REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE4_MESSAGE_BITS4                 , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4 );
+REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE4_MESSAGE_BITS4_LEN             , 64  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4_LEN );
+
+REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE4_MESSAGE_BITS4                 , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4 );
+REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE4_MESSAGE_BITS4_LEN             , 64  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4_LEN );
+
+REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE4_MESSAGE_BITS4                 , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4 );
+REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE4_MESSAGE_BITS4_LEN             , 64  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4_LEN );
+
+REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE4_MESSAGE_BITS4                 , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4 );
+REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE4_MESSAGE_BITS4_LEN             , 64  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4_LEN );
+
+REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE4_MESSAGE_BITS4                 , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4 );
+REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE4_MESSAGE_BITS4_LEN             , 64  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4_LEN );
+
+REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE4_MESSAGE_BITS4                 , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4 );
+REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE4_MESSAGE_BITS4_LEN             , 64  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4_LEN );
+
+REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE4_MESSAGE_BITS4                 , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4 );
+REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE4_MESSAGE_BITS4_LEN             , 64  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4_LEN );
+
+REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE4_MESSAGE_BITS4                 , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4 );
+REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE4_MESSAGE_BITS4_LEN             , 64  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4_LEN );
+
+REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE4_MESSAGE_BITS4                 , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4 );
+REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE4_MESSAGE_BITS4_LEN             , 64  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4_LEN );
+
+REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE4_MESSAGE_BITS4                 , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4 );
+REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE4_MESSAGE_BITS4_LEN             , 64  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4_LEN );
+
+REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE4_MESSAGE_BITS4                 , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4 );
+REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE4_MESSAGE_BITS4_LEN             , 64  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MESSAGE_BITS4_LEN );
+
+REG64_FLD( PU_NPU0_CERR_PTY_FIRST_BITS                             , 37  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU0_CERR_PTY_FIRST_BITS_LEN                         , 27  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU1_CERR_PTY_FIRST_BITS                             , 37  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU1_CERR_PTY_FIRST_BITS_LEN                         , 27  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU2_CERR_PTY_FIRST_BITS                             , 37  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU2_CERR_PTY_FIRST_BITS_LEN                         , 27  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_INHIBIT_CONFIG              , 37  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_INHIBIT_CONFIG );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_MISC_STATE                  , 38  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_MISC_STATE );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_MRG_STATE                   , 39  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_MRG_STATE );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_OBUF_STATE                  , 40  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OBUF_STATE );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_PBTX_STATE                  , 41  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBTX_STATE );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_RQIN_STATE                  , 42  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_RQIN_STATE );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_IBUF_STATE                  , 43  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBUF_STATE );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_ERRINJ                      , 44  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_ERRINJ );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_PBTX_AMO                    , 45  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBTX_AMO );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_PBTX_AMO_LEN                , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBTX_AMO_LEN );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_IBRD                        , 49  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBRD );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_IBRD_LEN                    , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBRD_LEN );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_OBRD                        , 53  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OBRD );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_OBRD_LEN                    , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OBRD_LEN );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_BBRD                        , 57  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BBRD );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_BBRD_LEN                    , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BBRD_LEN );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_PBRX_RTAG                   , 59  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBRX_RTAG );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_ECC_CONFIG                  , 60  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_ECC_CONFIG );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_CONFIG1                     , 61  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CONFIG1 );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_DEBUG0_CONFIG               , 62  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_DEBUG0_CONFIG );
+REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_DEBUG1_CONFIG               , 63  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_DEBUG1_CONFIG );
+
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_INHIBIT_CONFIG              , 37  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_INHIBIT_CONFIG );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_MISC_STATE                  , 38  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_MISC_STATE );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_MRG_STATE                   , 39  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_MRG_STATE );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_OBUF_STATE                  , 40  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OBUF_STATE );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_PBTX_STATE                  , 41  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBTX_STATE );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_RQIN_STATE                  , 42  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_RQIN_STATE );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_IBUF_STATE                  , 43  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBUF_STATE );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_ERRINJ                      , 44  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_ERRINJ );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_PBTX_AMO                    , 45  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBTX_AMO );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_PBTX_AMO_LEN                , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBTX_AMO_LEN );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_IBRD                        , 49  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBRD );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_IBRD_LEN                    , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBRD_LEN );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_OBRD                        , 53  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OBRD );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_OBRD_LEN                    , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OBRD_LEN );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_BBRD                        , 57  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BBRD );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_BBRD_LEN                    , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BBRD_LEN );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_PBRX_RTAG                   , 59  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBRX_RTAG );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_ECC_CONFIG                  , 60  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_ECC_CONFIG );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_CONFIG1                     , 61  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CONFIG1 );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_DEBUG0_CONFIG               , 62  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_DEBUG0_CONFIG );
+REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_DEBUG1_CONFIG               , 63  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_DEBUG1_CONFIG );
+
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_INHIBIT_CONFIG              , 37  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_INHIBIT_CONFIG );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_MISC_STATE                  , 38  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_MISC_STATE );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_MRG_STATE                   , 39  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_MRG_STATE );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_OBUF_STATE                  , 40  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OBUF_STATE );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_PBTX_STATE                  , 41  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBTX_STATE );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_RQIN_STATE                  , 42  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_RQIN_STATE );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_IBUF_STATE                  , 43  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBUF_STATE );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_ERRINJ                      , 44  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_ERRINJ );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_PBTX_AMO                    , 45  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBTX_AMO );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_PBTX_AMO_LEN                , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBTX_AMO_LEN );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_IBRD                        , 49  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBRD );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_IBRD_LEN                    , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBRD_LEN );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_OBRD                        , 53  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OBRD );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_OBRD_LEN                    , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_OBRD_LEN );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_BBRD                        , 57  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BBRD );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_BBRD_LEN                    , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_BBRD_LEN );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_PBRX_RTAG                   , 59  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_PBRX_RTAG );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_ECC_CONFIG                  , 60  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_ECC_CONFIG );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_CONFIG1                     , 61  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CONFIG1 );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_DEBUG0_CONFIG               , 62  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_DEBUG0_CONFIG );
+REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_DEBUG1_CONFIG               , 63  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_DEBUG1_CONFIG );
+
+REG64_FLD( PU_NPU0_CERR_PTY_MASK_BITS                              , 37  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU0_CERR_PTY_MASK_BITS_LEN                          , 27  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU1_CERR_PTY_MASK_BITS                              , 37  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU1_CERR_PTY_MASK_BITS_LEN                          , 27  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU2_CERR_PTY_MASK_BITS                              , 37  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU2_CERR_PTY_MASK_BITS_LEN                          , 27  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PEC_CLK_REGION_CLOCK_CMD                                , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_CMD  );
+REG64_FLD( PEC_CLK_REGION_CLOCK_CMD_LEN                            , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_CMD_LEN );
+REG64_FLD( PEC_CLK_REGION_SLAVE_MODE                               , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE_MODE );
+REG64_FLD( PEC_CLK_REGION_MASTER_MODE                              , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_MODE );
+REG64_FLD( PEC_CLK_REGION_CLOCK_PERV                               , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_PERV );
+REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT1                              , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT1 );
+REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT2                              , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT2 );
+REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT3                              , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT3 );
+REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT4                              , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT4 );
+REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT5                              , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT5 );
+REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT6                              , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT6 );
+REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT7                              , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT7 );
+REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT8                              , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT8 );
+REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT9                              , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT9 );
+REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT10                             , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT10 );
+REG64_FLD( PEC_CLK_REGION_SEL_THOLD_SL                             , 48  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_SL );
+REG64_FLD( PEC_CLK_REGION_SEL_THOLD_NSL                            , 49  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_NSL );
+REG64_FLD( PEC_CLK_REGION_SEL_THOLD_ARY                            , 50  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_ARY );
+REG64_FLD( PEC_CLK_REGION_CLOCK_PULSE_USE_EVEN                     , 52  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_PULSE_USE_EVEN );
+
+REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_PERV                          , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_PERV );
+REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT1                         , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT1 );
+REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT2                         , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT2 );
+REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT3                         , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT3 );
+REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT4                         , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT4 );
+REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT5                         , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT5 );
+REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT6                         , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT6 );
+REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT7                         , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT7 );
+REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT8                         , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT8 );
+REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT9                         , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT9 );
+REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT10                        , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_PERV                          , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_PERV );
+REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT1                         , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT1 );
+REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT2                         , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT2 );
+REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT3                         , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT3 );
+REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT4                         , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT4 );
+REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT5                         , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT5 );
+REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT6                         , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT6 );
+REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT7                         , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT7 );
+REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT8                         , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT8 );
+REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT9                         , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT9 );
+REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT10                        , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_PERV                           , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_PERV );
+REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT1                          , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT1 );
+REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT2                          , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT2 );
+REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT3                          , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT3 );
+REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT4                          , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT4 );
+REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT5                          , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT5 );
+REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT6                          , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT6 );
+REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT7                          , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT7 );
+REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT8                          , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT8 );
+REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT9                          , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT9 );
+REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT10                         , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( PU_CME4_CME_LCL_DBG_EN                                  , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_EN         );
+REG64_FLD( PU_CME4_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME4_CME_LCL_DBG_HALT_ON_TRIG                        , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME4_CME_LCL_DBG_RESERVED3                           , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_CME4_CME_LCL_DBG_EN_INTR_ADDR                        , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_CME4_CME_LCL_DBG_EN_TRACE_EXTRA                      , 5   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_CME4_CME_LCL_DBG_EN_TRACE_STALL                      , 6   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_CME4_CME_LCL_DBG_EN_WAIT_CYCLES                      , 7   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_CME4_CME_LCL_DBG_EN_FULL_SPEED                       , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_CME4_CME_LCL_DBG_RESERVED9                           , 9   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_MODE_SEL                      , 10  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_CME4_CME_LCL_DBG_FIR_TRIGGER                         , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME4_CME_LCL_DBG_MIB_GPIO                            , 17  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME4_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_DATA_SEL                      , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_DBG_EN                                  , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_EN         );
+REG64_FLD( PU_CME3_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME3_CME_LCL_DBG_HALT_ON_TRIG                        , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME3_CME_LCL_DBG_RESERVED3                           , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_CME3_CME_LCL_DBG_EN_INTR_ADDR                        , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_CME3_CME_LCL_DBG_EN_TRACE_EXTRA                      , 5   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_CME3_CME_LCL_DBG_EN_TRACE_STALL                      , 6   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_CME3_CME_LCL_DBG_EN_WAIT_CYCLES                      , 7   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_CME3_CME_LCL_DBG_EN_FULL_SPEED                       , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_CME3_CME_LCL_DBG_RESERVED9                           , 9   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_MODE_SEL                      , 10  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_CME3_CME_LCL_DBG_FIR_TRIGGER                         , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME3_CME_LCL_DBG_MIB_GPIO                            , 17  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME3_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_DATA_SEL                      , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_DBG_EN                                 , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_EN         );
+REG64_FLD( PU_CME11_CME_LCL_DBG_HALT_ON_XSTOP                      , 1   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME11_CME_LCL_DBG_HALT_ON_TRIG                       , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME11_CME_LCL_DBG_RESERVED3                          , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_CME11_CME_LCL_DBG_EN_INTR_ADDR                       , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_CME11_CME_LCL_DBG_EN_TRACE_EXTRA                     , 5   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_CME11_CME_LCL_DBG_EN_TRACE_STALL                     , 6   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_CME11_CME_LCL_DBG_EN_WAIT_CYCLES                     , 7   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_CME11_CME_LCL_DBG_EN_FULL_SPEED                      , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_CME11_CME_LCL_DBG_RESERVED9                          , 9   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_MODE_SEL                     , 10  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_MODE_SEL_LEN                 , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_CME11_CME_LCL_DBG_FIR_TRIGGER                        , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME11_CME_LCL_DBG_MIB_GPIO                           , 17  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME11_CME_LCL_DBG_MIB_GPIO_LEN                       , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_DATA_SEL                     , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_DATA_SEL_LEN                 , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_DBG_EN                                  , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_EN         );
+REG64_FLD( PU_CME2_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME2_CME_LCL_DBG_HALT_ON_TRIG                        , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME2_CME_LCL_DBG_RESERVED3                           , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_CME2_CME_LCL_DBG_EN_INTR_ADDR                        , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_CME2_CME_LCL_DBG_EN_TRACE_EXTRA                      , 5   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_CME2_CME_LCL_DBG_EN_TRACE_STALL                      , 6   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_CME2_CME_LCL_DBG_EN_WAIT_CYCLES                      , 7   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_CME2_CME_LCL_DBG_EN_FULL_SPEED                       , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_CME2_CME_LCL_DBG_RESERVED9                           , 9   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_MODE_SEL                      , 10  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_CME2_CME_LCL_DBG_FIR_TRIGGER                         , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME2_CME_LCL_DBG_MIB_GPIO                            , 17  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME2_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_DATA_SEL                      , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_DBG_EN                                  , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_EN         );
+REG64_FLD( PU_CME5_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME5_CME_LCL_DBG_HALT_ON_TRIG                        , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME5_CME_LCL_DBG_RESERVED3                           , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_CME5_CME_LCL_DBG_EN_INTR_ADDR                        , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_CME5_CME_LCL_DBG_EN_TRACE_EXTRA                      , 5   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_CME5_CME_LCL_DBG_EN_TRACE_STALL                      , 6   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_CME5_CME_LCL_DBG_EN_WAIT_CYCLES                      , 7   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_CME5_CME_LCL_DBG_EN_FULL_SPEED                       , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_CME5_CME_LCL_DBG_RESERVED9                           , 9   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_MODE_SEL                      , 10  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_CME5_CME_LCL_DBG_FIR_TRIGGER                         , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME5_CME_LCL_DBG_MIB_GPIO                            , 17  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME5_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_DATA_SEL                      , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_DBG_EN                                  , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_EN         );
+REG64_FLD( PU_CME9_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME9_CME_LCL_DBG_HALT_ON_TRIG                        , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME9_CME_LCL_DBG_RESERVED3                           , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_CME9_CME_LCL_DBG_EN_INTR_ADDR                        , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_CME9_CME_LCL_DBG_EN_TRACE_EXTRA                      , 5   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_CME9_CME_LCL_DBG_EN_TRACE_STALL                      , 6   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_CME9_CME_LCL_DBG_EN_WAIT_CYCLES                      , 7   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_CME9_CME_LCL_DBG_EN_FULL_SPEED                       , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_CME9_CME_LCL_DBG_RESERVED9                           , 9   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_MODE_SEL                      , 10  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_CME9_CME_LCL_DBG_FIR_TRIGGER                         , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME9_CME_LCL_DBG_MIB_GPIO                            , 17  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME9_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_DATA_SEL                      , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_DBG_EN                                  , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_EN         );
+REG64_FLD( PU_CME6_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME6_CME_LCL_DBG_HALT_ON_TRIG                        , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME6_CME_LCL_DBG_RESERVED3                           , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_CME6_CME_LCL_DBG_EN_INTR_ADDR                        , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_CME6_CME_LCL_DBG_EN_TRACE_EXTRA                      , 5   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_CME6_CME_LCL_DBG_EN_TRACE_STALL                      , 6   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_CME6_CME_LCL_DBG_EN_WAIT_CYCLES                      , 7   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_CME6_CME_LCL_DBG_EN_FULL_SPEED                       , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_CME6_CME_LCL_DBG_RESERVED9                           , 9   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_MODE_SEL                      , 10  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_CME6_CME_LCL_DBG_FIR_TRIGGER                         , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME6_CME_LCL_DBG_MIB_GPIO                            , 17  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME6_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_DATA_SEL                      , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_DBG_EN                                 , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_EN         );
+REG64_FLD( PU_CME10_CME_LCL_DBG_HALT_ON_XSTOP                      , 1   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME10_CME_LCL_DBG_HALT_ON_TRIG                       , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME10_CME_LCL_DBG_RESERVED3                          , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_CME10_CME_LCL_DBG_EN_INTR_ADDR                       , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_CME10_CME_LCL_DBG_EN_TRACE_EXTRA                     , 5   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_CME10_CME_LCL_DBG_EN_TRACE_STALL                     , 6   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_CME10_CME_LCL_DBG_EN_WAIT_CYCLES                     , 7   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_CME10_CME_LCL_DBG_EN_FULL_SPEED                      , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_CME10_CME_LCL_DBG_RESERVED9                          , 9   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_MODE_SEL                     , 10  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_MODE_SEL_LEN                 , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_CME10_CME_LCL_DBG_FIR_TRIGGER                        , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME10_CME_LCL_DBG_MIB_GPIO                           , 17  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME10_CME_LCL_DBG_MIB_GPIO_LEN                       , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_DATA_SEL                     , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_DATA_SEL_LEN                 , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_DBG_EN                                  , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_EN         );
+REG64_FLD( PU_CME8_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME8_CME_LCL_DBG_HALT_ON_TRIG                        , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME8_CME_LCL_DBG_RESERVED3                           , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_CME8_CME_LCL_DBG_EN_INTR_ADDR                        , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_CME8_CME_LCL_DBG_EN_TRACE_EXTRA                      , 5   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_CME8_CME_LCL_DBG_EN_TRACE_STALL                      , 6   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_CME8_CME_LCL_DBG_EN_WAIT_CYCLES                      , 7   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_CME8_CME_LCL_DBG_EN_FULL_SPEED                       , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_CME8_CME_LCL_DBG_RESERVED9                           , 9   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_MODE_SEL                      , 10  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_CME8_CME_LCL_DBG_FIR_TRIGGER                         , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME8_CME_LCL_DBG_MIB_GPIO                            , 17  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME8_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_DATA_SEL                      , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_DBG_EN                                  , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_EN         );
+REG64_FLD( PU_CME1_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME1_CME_LCL_DBG_HALT_ON_TRIG                        , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME1_CME_LCL_DBG_RESERVED3                           , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_CME1_CME_LCL_DBG_EN_INTR_ADDR                        , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_CME1_CME_LCL_DBG_EN_TRACE_EXTRA                      , 5   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_CME1_CME_LCL_DBG_EN_TRACE_STALL                      , 6   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_CME1_CME_LCL_DBG_EN_WAIT_CYCLES                      , 7   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_CME1_CME_LCL_DBG_EN_FULL_SPEED                       , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_CME1_CME_LCL_DBG_RESERVED9                           , 9   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_MODE_SEL                      , 10  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_CME1_CME_LCL_DBG_FIR_TRIGGER                         , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME1_CME_LCL_DBG_MIB_GPIO                            , 17  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME1_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_DATA_SEL                      , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_DBG_EN                                  , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_EN         );
+REG64_FLD( PU_CME0_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME0_CME_LCL_DBG_HALT_ON_TRIG                        , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME0_CME_LCL_DBG_RESERVED3                           , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_CME0_CME_LCL_DBG_EN_INTR_ADDR                        , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_CME0_CME_LCL_DBG_EN_TRACE_EXTRA                      , 5   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_CME0_CME_LCL_DBG_EN_TRACE_STALL                      , 6   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_CME0_CME_LCL_DBG_EN_WAIT_CYCLES                      , 7   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_CME0_CME_LCL_DBG_EN_FULL_SPEED                       , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_CME0_CME_LCL_DBG_RESERVED9                           , 9   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_MODE_SEL                      , 10  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_CME0_CME_LCL_DBG_FIR_TRIGGER                         , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME0_CME_LCL_DBG_MIB_GPIO                            , 17  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME0_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_DATA_SEL                      , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_DBG_EN                                  , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_EN         );
+REG64_FLD( PU_CME7_CME_LCL_DBG_HALT_ON_XSTOP                       , 1   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_CME7_CME_LCL_DBG_HALT_ON_TRIG                        , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_CME7_CME_LCL_DBG_RESERVED3                           , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_CME7_CME_LCL_DBG_EN_INTR_ADDR                        , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_CME7_CME_LCL_DBG_EN_TRACE_EXTRA                      , 5   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_CME7_CME_LCL_DBG_EN_TRACE_STALL                      , 6   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_CME7_CME_LCL_DBG_EN_WAIT_CYCLES                      , 7   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_CME7_CME_LCL_DBG_EN_FULL_SPEED                       , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_CME7_CME_LCL_DBG_RESERVED9                           , 9   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_MODE_SEL                      , 10  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_MODE_SEL_LEN                  , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_CME7_CME_LCL_DBG_FIR_TRIGGER                         , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_CME7_CME_LCL_DBG_MIB_GPIO                            , 17  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO   );
+REG64_FLD( PU_CME7_CME_LCL_DBG_MIB_GPIO_LEN                        , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_DATA_SEL                      , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_DATA_SEL_LEN                  , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME4_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME3_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_EIMR_INTERRUPT_MASK                    , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME11_CME_LCL_EIMR_INTERRUPT_MASK_LEN                , 44  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME2_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME5_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME9_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME6_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_EIMR_INTERRUPT_MASK                    , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME10_CME_LCL_EIMR_INTERRUPT_MASK_LEN                , 44  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME8_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME1_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME0_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_EIMR_INTERRUPT_MASK                     , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK );
+REG64_FLD( PU_CME7_CME_LCL_EIMR_INTERRUPT_MASK_LEN                 , 44  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME4_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME3_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_EINR_INTERRUPT_INPUT                   , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME11_CME_LCL_EINR_INTERRUPT_INPUT_LEN               , 44  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME2_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME5_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME9_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME6_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_EINR_INTERRUPT_INPUT                   , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME10_CME_LCL_EINR_INTERRUPT_INPUT_LEN               , 44  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME8_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME1_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME0_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_EINR_INTERRUPT_INPUT                    , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( PU_CME7_CME_LCL_EINR_INTERRUPT_INPUT_LEN                , 44  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME4_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME3_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_EIPR_INTERRUPT_POLARITY                , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME11_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN            , 44  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME2_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME5_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME9_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME6_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_EIPR_INTERRUPT_POLARITY                , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME10_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN            , 44  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME8_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME1_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME0_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_EIPR_INTERRUPT_POLARITY                 , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( PU_CME7_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN             , 44  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_EISR_DEBUGGER                           , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME4_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME4_CME_LCL_EISR_PVREF_FAIL                         , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME4_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME4_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DROPOUT_DETECT                     , 6   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_DROPOUT_DETECT );
+REG64_FLD( PU_CME4_CME_LCL_EISR_INTERCME_DIRECT_IN_0               , 7   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME4_CME_LCL_EISR_BCE_TIMEOUT                        , 9   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL3_C0                       , 10  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL3_C1                       , 11  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL2_C0                       , 18  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL2_C1                       , 19  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_L2_PURGE_DONE                      , 22  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME4_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME4_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME4_CME_LCL_EISR_FINAL_VDM_DATA01                   , 27  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01_LEN );
+REG64_FLD( PU_CME4_CME_LCL_EISR_COMM_RECVD                         , 29  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME4_CME_LCL_EISR_COMM_SEND_ACK                      , 30  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME4_CME_LCL_EISR_COMM_SEND_NACK                     , 31  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_32_33                        , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME4_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL0_C0                       , 36  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL0_C1                       , 37  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             , 38  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2_LEN );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL1_C0                       , 40  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL1_C1                       , 41  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_RESERVED_42_43                     , 42  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME4_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_EISR_DEBUGGER                           , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME3_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME3_CME_LCL_EISR_PVREF_FAIL                         , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME3_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME3_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DROPOUT_DETECT                     , 6   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_DROPOUT_DETECT );
+REG64_FLD( PU_CME3_CME_LCL_EISR_INTERCME_DIRECT_IN_0               , 7   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME3_CME_LCL_EISR_BCE_TIMEOUT                        , 9   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL3_C0                       , 10  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL3_C1                       , 11  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL2_C0                       , 18  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL2_C1                       , 19  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_L2_PURGE_DONE                      , 22  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME3_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME3_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME3_CME_LCL_EISR_FINAL_VDM_DATA01                   , 27  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01_LEN );
+REG64_FLD( PU_CME3_CME_LCL_EISR_COMM_RECVD                         , 29  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME3_CME_LCL_EISR_COMM_SEND_ACK                      , 30  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME3_CME_LCL_EISR_COMM_SEND_NACK                     , 31  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_32_33                        , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME3_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL0_C0                       , 36  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL0_C1                       , 37  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             , 38  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2_LEN );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL1_C0                       , 40  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL1_C1                       , 41  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_RESERVED_42_43                     , 42  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME3_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_EISR_DEBUGGER                          , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DEBUG_TRIGGER                     , 1   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME11_CME_LCL_EISR_QUAD_CHECKSTOP                    , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME11_CME_LCL_EISR_PVREF_FAIL                        , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME11_CME_LCL_EISR_OCC_HEARTBEAT_LOST                , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME11_CME_LCL_EISR_CORE_CHECKSTOP                    , 5   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DROPOUT_DETECT                    , 6   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_DROPOUT_DETECT );
+REG64_FLD( PU_CME11_CME_LCL_EISR_INTERCME_DIRECT_IN_0              , 7   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_BCE_BUSY_HIGH                     , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME11_CME_LCL_EISR_BCE_TIMEOUT                       , 9   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL3_C0                      , 10  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL3_C1                      , 11  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_PC_INTR_PENDING_C0                , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_PC_INTR_PENDING_C1                , 13  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_SPECIAL_WAKEUP_C0                 , 14  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_SPECIAL_WAKEUP_C1                 , 15  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_REG_WAKEUP_C0                     , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_REG_WAKEUP_C1                     , 17  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL2_C0                      , 18  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL2_C1                      , 19  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0             , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1             , 21  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_L2_PURGE_DONE                     , 22  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME11_CME_LCL_EISR_NCU_PURGE_DONE                    , 23  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME11_CME_LCL_EISR_CHTM_PURGE_DONE_C0                , 24  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_CHTM_PURGE_DONE_C1                , 25  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_BCE_BUSY_LOW                      , 26  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME11_CME_LCL_EISR_FINAL_VDM_DATA01                  , 27  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_FINAL_VDM_DATA01_LEN              , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01_LEN );
+REG64_FLD( PU_CME11_CME_LCL_EISR_COMM_RECVD                        , 29  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME11_CME_LCL_EISR_COMM_SEND_ACK                     , 30  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME11_CME_LCL_EISR_COMM_SEND_NACK                    , 31  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_32_33                       , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_32_33_LEN                   , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME11_CME_LCL_EISR_PMCR_UPDATE_C0                    , 34  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_PMCR_UPDATE_C1                    , 35  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL0_C0                      , 36  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL0_C1                      , 37  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2            , 38  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN        , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2_LEN );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL1_C0                      , 40  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL1_C1                      , 41  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_RESERVED_42_43                    , 42  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME11_CME_LCL_EISR_RESERVED_42_43_LEN                , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_EISR_DEBUGGER                           , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME2_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME2_CME_LCL_EISR_PVREF_FAIL                         , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME2_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME2_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DROPOUT_DETECT                     , 6   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_DROPOUT_DETECT );
+REG64_FLD( PU_CME2_CME_LCL_EISR_INTERCME_DIRECT_IN_0               , 7   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME2_CME_LCL_EISR_BCE_TIMEOUT                        , 9   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL3_C0                       , 10  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL3_C1                       , 11  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL2_C0                       , 18  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL2_C1                       , 19  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_L2_PURGE_DONE                      , 22  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME2_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME2_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME2_CME_LCL_EISR_FINAL_VDM_DATA01                   , 27  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01_LEN );
+REG64_FLD( PU_CME2_CME_LCL_EISR_COMM_RECVD                         , 29  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME2_CME_LCL_EISR_COMM_SEND_ACK                      , 30  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME2_CME_LCL_EISR_COMM_SEND_NACK                     , 31  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_32_33                        , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME2_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL0_C0                       , 36  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL0_C1                       , 37  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             , 38  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2_LEN );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL1_C0                       , 40  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL1_C1                       , 41  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_RESERVED_42_43                     , 42  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME2_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_EISR_DEBUGGER                           , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME5_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME5_CME_LCL_EISR_PVREF_FAIL                         , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME5_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME5_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DROPOUT_DETECT                     , 6   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_DROPOUT_DETECT );
+REG64_FLD( PU_CME5_CME_LCL_EISR_INTERCME_DIRECT_IN_0               , 7   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME5_CME_LCL_EISR_BCE_TIMEOUT                        , 9   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL3_C0                       , 10  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL3_C1                       , 11  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL2_C0                       , 18  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL2_C1                       , 19  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_L2_PURGE_DONE                      , 22  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME5_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME5_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME5_CME_LCL_EISR_FINAL_VDM_DATA01                   , 27  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01_LEN );
+REG64_FLD( PU_CME5_CME_LCL_EISR_COMM_RECVD                         , 29  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME5_CME_LCL_EISR_COMM_SEND_ACK                      , 30  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME5_CME_LCL_EISR_COMM_SEND_NACK                     , 31  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_32_33                        , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME5_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL0_C0                       , 36  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL0_C1                       , 37  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             , 38  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2_LEN );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL1_C0                       , 40  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL1_C1                       , 41  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_RESERVED_42_43                     , 42  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME5_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_EISR_DEBUGGER                           , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME9_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME9_CME_LCL_EISR_PVREF_FAIL                         , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME9_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME9_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DROPOUT_DETECT                     , 6   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_DROPOUT_DETECT );
+REG64_FLD( PU_CME9_CME_LCL_EISR_INTERCME_DIRECT_IN_0               , 7   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME9_CME_LCL_EISR_BCE_TIMEOUT                        , 9   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL3_C0                       , 10  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL3_C1                       , 11  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL2_C0                       , 18  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL2_C1                       , 19  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_L2_PURGE_DONE                      , 22  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME9_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME9_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME9_CME_LCL_EISR_FINAL_VDM_DATA01                   , 27  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01_LEN );
+REG64_FLD( PU_CME9_CME_LCL_EISR_COMM_RECVD                         , 29  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME9_CME_LCL_EISR_COMM_SEND_ACK                      , 30  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME9_CME_LCL_EISR_COMM_SEND_NACK                     , 31  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_32_33                        , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME9_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL0_C0                       , 36  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL0_C1                       , 37  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             , 38  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2_LEN );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL1_C0                       , 40  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL1_C1                       , 41  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_RESERVED_42_43                     , 42  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME9_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_EISR_DEBUGGER                           , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME6_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME6_CME_LCL_EISR_PVREF_FAIL                         , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME6_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME6_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DROPOUT_DETECT                     , 6   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_DROPOUT_DETECT );
+REG64_FLD( PU_CME6_CME_LCL_EISR_INTERCME_DIRECT_IN_0               , 7   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME6_CME_LCL_EISR_BCE_TIMEOUT                        , 9   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL3_C0                       , 10  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL3_C1                       , 11  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL2_C0                       , 18  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL2_C1                       , 19  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_L2_PURGE_DONE                      , 22  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME6_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME6_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME6_CME_LCL_EISR_FINAL_VDM_DATA01                   , 27  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01_LEN );
+REG64_FLD( PU_CME6_CME_LCL_EISR_COMM_RECVD                         , 29  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME6_CME_LCL_EISR_COMM_SEND_ACK                      , 30  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME6_CME_LCL_EISR_COMM_SEND_NACK                     , 31  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_32_33                        , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME6_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL0_C0                       , 36  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL0_C1                       , 37  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             , 38  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2_LEN );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL1_C0                       , 40  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL1_C1                       , 41  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_RESERVED_42_43                     , 42  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME6_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_EISR_DEBUGGER                          , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DEBUG_TRIGGER                     , 1   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME10_CME_LCL_EISR_QUAD_CHECKSTOP                    , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME10_CME_LCL_EISR_PVREF_FAIL                        , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME10_CME_LCL_EISR_OCC_HEARTBEAT_LOST                , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME10_CME_LCL_EISR_CORE_CHECKSTOP                    , 5   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DROPOUT_DETECT                    , 6   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_DROPOUT_DETECT );
+REG64_FLD( PU_CME10_CME_LCL_EISR_INTERCME_DIRECT_IN_0              , 7   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_BCE_BUSY_HIGH                     , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME10_CME_LCL_EISR_BCE_TIMEOUT                       , 9   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL3_C0                      , 10  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL3_C1                      , 11  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_PC_INTR_PENDING_C0                , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_PC_INTR_PENDING_C1                , 13  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_SPECIAL_WAKEUP_C0                 , 14  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_SPECIAL_WAKEUP_C1                 , 15  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_REG_WAKEUP_C0                     , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_REG_WAKEUP_C1                     , 17  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL2_C0                      , 18  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL2_C1                      , 19  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0             , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1             , 21  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_L2_PURGE_DONE                     , 22  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME10_CME_LCL_EISR_NCU_PURGE_DONE                    , 23  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME10_CME_LCL_EISR_CHTM_PURGE_DONE_C0                , 24  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_CHTM_PURGE_DONE_C1                , 25  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_BCE_BUSY_LOW                      , 26  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME10_CME_LCL_EISR_FINAL_VDM_DATA01                  , 27  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_FINAL_VDM_DATA01_LEN              , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01_LEN );
+REG64_FLD( PU_CME10_CME_LCL_EISR_COMM_RECVD                        , 29  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME10_CME_LCL_EISR_COMM_SEND_ACK                     , 30  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME10_CME_LCL_EISR_COMM_SEND_NACK                    , 31  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_32_33                       , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_32_33_LEN                   , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME10_CME_LCL_EISR_PMCR_UPDATE_C0                    , 34  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_PMCR_UPDATE_C1                    , 35  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL0_C0                      , 36  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL0_C1                      , 37  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2            , 38  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN        , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2_LEN );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL1_C0                      , 40  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL1_C1                      , 41  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_RESERVED_42_43                    , 42  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME10_CME_LCL_EISR_RESERVED_42_43_LEN                , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_EISR_DEBUGGER                           , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME8_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME8_CME_LCL_EISR_PVREF_FAIL                         , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME8_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME8_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DROPOUT_DETECT                     , 6   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_DROPOUT_DETECT );
+REG64_FLD( PU_CME8_CME_LCL_EISR_INTERCME_DIRECT_IN_0               , 7   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME8_CME_LCL_EISR_BCE_TIMEOUT                        , 9   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL3_C0                       , 10  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL3_C1                       , 11  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL2_C0                       , 18  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL2_C1                       , 19  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_L2_PURGE_DONE                      , 22  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME8_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME8_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME8_CME_LCL_EISR_FINAL_VDM_DATA01                   , 27  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01_LEN );
+REG64_FLD( PU_CME8_CME_LCL_EISR_COMM_RECVD                         , 29  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME8_CME_LCL_EISR_COMM_SEND_ACK                      , 30  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME8_CME_LCL_EISR_COMM_SEND_NACK                     , 31  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_32_33                        , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME8_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL0_C0                       , 36  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL0_C1                       , 37  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             , 38  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2_LEN );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL1_C0                       , 40  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL1_C1                       , 41  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_RESERVED_42_43                     , 42  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME8_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_EISR_DEBUGGER                           , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME1_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME1_CME_LCL_EISR_PVREF_FAIL                         , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME1_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME1_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DROPOUT_DETECT                     , 6   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_DROPOUT_DETECT );
+REG64_FLD( PU_CME1_CME_LCL_EISR_INTERCME_DIRECT_IN_0               , 7   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME1_CME_LCL_EISR_BCE_TIMEOUT                        , 9   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL3_C0                       , 10  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL3_C1                       , 11  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL2_C0                       , 18  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL2_C1                       , 19  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_L2_PURGE_DONE                      , 22  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME1_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME1_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME1_CME_LCL_EISR_FINAL_VDM_DATA01                   , 27  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01_LEN );
+REG64_FLD( PU_CME1_CME_LCL_EISR_COMM_RECVD                         , 29  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME1_CME_LCL_EISR_COMM_SEND_ACK                      , 30  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME1_CME_LCL_EISR_COMM_SEND_NACK                     , 31  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_32_33                        , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME1_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL0_C0                       , 36  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL0_C1                       , 37  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             , 38  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2_LEN );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL1_C0                       , 40  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL1_C1                       , 41  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_RESERVED_42_43                     , 42  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME1_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_EISR_DEBUGGER                           , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME0_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME0_CME_LCL_EISR_PVREF_FAIL                         , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME0_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME0_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DROPOUT_DETECT                     , 6   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_DROPOUT_DETECT );
+REG64_FLD( PU_CME0_CME_LCL_EISR_INTERCME_DIRECT_IN_0               , 7   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME0_CME_LCL_EISR_BCE_TIMEOUT                        , 9   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL3_C0                       , 10  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL3_C1                       , 11  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL2_C0                       , 18  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL2_C1                       , 19  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_L2_PURGE_DONE                      , 22  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME0_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME0_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME0_CME_LCL_EISR_FINAL_VDM_DATA01                   , 27  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01_LEN );
+REG64_FLD( PU_CME0_CME_LCL_EISR_COMM_RECVD                         , 29  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME0_CME_LCL_EISR_COMM_SEND_ACK                      , 30  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME0_CME_LCL_EISR_COMM_SEND_NACK                     , 31  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_32_33                        , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME0_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL0_C0                       , 36  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL0_C1                       , 37  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             , 38  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2_LEN );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL1_C0                       , 40  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL1_C1                       , 41  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_RESERVED_42_43                     , 42  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME0_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_EISR_DEBUGGER                           , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DEBUG_TRIGGER                      , 1   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_CME7_CME_LCL_EISR_QUAD_CHECKSTOP                     , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( PU_CME7_CME_LCL_EISR_PVREF_FAIL                         , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PVREF_FAIL );
+REG64_FLD( PU_CME7_CME_LCL_EISR_OCC_HEARTBEAT_LOST                 , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( PU_CME7_CME_LCL_EISR_CORE_CHECKSTOP                     , 5   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DROPOUT_DETECT                     , 6   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_DROPOUT_DETECT );
+REG64_FLD( PU_CME7_CME_LCL_EISR_INTERCME_DIRECT_IN_0               , 7   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_BCE_BUSY_HIGH                      , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( PU_CME7_CME_LCL_EISR_BCE_TIMEOUT                        , 9   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL3_C0                       , 10  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL3_C1                       , 11  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL3_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_PC_INTR_PENDING_C0                 , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_PC_INTR_PENDING_C1                 , 13  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_SPECIAL_WAKEUP_C0                  , 14  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_SPECIAL_WAKEUP_C1                  , 15  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_REG_WAKEUP_C0                      , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_REG_WAKEUP_C1                      , 17  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL2_C0                       , 18  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL2_C1                       , 19  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL2_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0              , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1              , 21  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_L2_PURGE_DONE                      , 22  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( PU_CME7_CME_LCL_EISR_NCU_PURGE_DONE                     , 23  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( PU_CME7_CME_LCL_EISR_CHTM_PURGE_DONE_C0                 , 24  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_CHTM_PURGE_DONE_C1                 , 25  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_BCE_BUSY_LOW                       , 26  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( PU_CME7_CME_LCL_EISR_FINAL_VDM_DATA01                   , 27  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_FINAL_VDM_DATA01_LEN               , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_FINAL_VDM_DATA01_LEN );
+REG64_FLD( PU_CME7_CME_LCL_EISR_COMM_RECVD                         , 29  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_RECVD );
+REG64_FLD( PU_CME7_CME_LCL_EISR_COMM_SEND_ACK                      , 30  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_ACK );
+REG64_FLD( PU_CME7_CME_LCL_EISR_COMM_SEND_NACK                     , 31  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_SEND_NACK );
+REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_32_33                        , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_32_33_LEN                    , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( PU_CME7_CME_LCL_EISR_PMCR_UPDATE_C0                     , 34  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_PMCR_UPDATE_C1                     , 35  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL0_C0                       , 36  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL0_C1                       , 37  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL0_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2             , 38  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN         , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2_LEN );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL1_C0                       , 40  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C0 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL1_C1                       , 41  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_DOORBELL1_C1 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_RESERVED_42_43                     , 42  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43 );
+REG64_FLD( PU_CME7_CME_LCL_EISR_RESERVED_42_43_LEN                 , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME4_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME3_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_EITR_INTERRUPT_TYPE                    , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME11_CME_LCL_EITR_INTERRUPT_TYPE_LEN                , 44  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME2_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME5_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME9_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME6_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_EITR_INTERRUPT_TYPE                    , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME10_CME_LCL_EITR_INTERRUPT_TYPE_LEN                , 44  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME8_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME1_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME0_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_EITR_INTERRUPT_TYPE                     , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( PU_CME7_CME_LCL_EITR_INTERRUPT_TYPE_LEN                 , 44  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_ICCR_COMM_ACK                           , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME4_CME_LCL_ICCR_COMM_NACK                          , 1   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_NACK  );
+REG64_FLD( PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           , 5   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT );
+REG64_FLD( PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN );
+REG64_FLD( PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            , 9   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN );
+REG64_FLD( PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_ICCR_COMM_ACK                           , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME3_CME_LCL_ICCR_COMM_NACK                          , 1   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_NACK  );
+REG64_FLD( PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           , 5   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT );
+REG64_FLD( PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN );
+REG64_FLD( PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            , 9   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN );
+REG64_FLD( PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_ICCR_COMM_ACK                          , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME11_CME_LCL_ICCR_COMM_NACK                         , 1   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_COMM_NACK  );
+REG64_FLD( PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT          , 5   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT );
+REG64_FLD( PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN      , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN );
+REG64_FLD( PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN           , 9   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN );
+REG64_FLD( PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN       , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_ICCR_COMM_ACK                           , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME2_CME_LCL_ICCR_COMM_NACK                          , 1   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_NACK  );
+REG64_FLD( PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           , 5   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT );
+REG64_FLD( PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN );
+REG64_FLD( PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            , 9   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN );
+REG64_FLD( PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_ICCR_COMM_ACK                           , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME5_CME_LCL_ICCR_COMM_NACK                          , 1   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_NACK  );
+REG64_FLD( PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           , 5   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT );
+REG64_FLD( PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN );
+REG64_FLD( PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            , 9   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN );
+REG64_FLD( PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_ICCR_COMM_ACK                           , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME9_CME_LCL_ICCR_COMM_NACK                          , 1   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_NACK  );
+REG64_FLD( PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           , 5   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT );
+REG64_FLD( PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN );
+REG64_FLD( PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            , 9   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN );
+REG64_FLD( PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_ICCR_COMM_ACK                           , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME6_CME_LCL_ICCR_COMM_NACK                          , 1   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_NACK  );
+REG64_FLD( PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           , 5   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT );
+REG64_FLD( PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN );
+REG64_FLD( PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            , 9   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN );
+REG64_FLD( PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_ICCR_COMM_ACK                          , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME10_CME_LCL_ICCR_COMM_NACK                         , 1   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_COMM_NACK  );
+REG64_FLD( PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT          , 5   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT );
+REG64_FLD( PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN      , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN );
+REG64_FLD( PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN           , 9   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN );
+REG64_FLD( PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN       , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_ICCR_COMM_ACK                           , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME8_CME_LCL_ICCR_COMM_NACK                          , 1   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_NACK  );
+REG64_FLD( PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           , 5   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT );
+REG64_FLD( PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN );
+REG64_FLD( PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            , 9   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN );
+REG64_FLD( PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_ICCR_COMM_ACK                           , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME1_CME_LCL_ICCR_COMM_NACK                          , 1   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_NACK  );
+REG64_FLD( PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           , 5   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT );
+REG64_FLD( PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN );
+REG64_FLD( PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            , 9   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN );
+REG64_FLD( PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_ICCR_COMM_ACK                           , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME0_CME_LCL_ICCR_COMM_NACK                          , 1   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_NACK  );
+REG64_FLD( PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           , 5   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT );
+REG64_FLD( PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN );
+REG64_FLD( PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            , 9   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN );
+REG64_FLD( PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_ICCR_COMM_ACK                           , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_ACK   );
+REG64_FLD( PU_CME7_CME_LCL_ICCR_COMM_NACK                          , 1   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_COMM_NACK  );
+REG64_FLD( PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT           , 5   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT );
+REG64_FLD( PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN       , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN );
+REG64_FLD( PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN            , 9   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN );
+REG64_FLD( PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN        , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_ICRR_COMM_RECV                          , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME4_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_ICRR_COMM_RECV                          , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME3_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_ICRR_COMM_RECV                         , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME11_CME_LCL_ICRR_COMM_RECV_LEN                     , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_ICRR_COMM_RECV                          , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME2_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_ICRR_COMM_RECV                          , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME5_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_ICRR_COMM_RECV                          , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME9_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_ICRR_COMM_RECV                          , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME6_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_ICRR_COMM_RECV                         , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME10_CME_LCL_ICRR_COMM_RECV_LEN                     , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_ICRR_COMM_RECV                          , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME8_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_ICRR_COMM_RECV                          , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME1_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_ICRR_COMM_RECV                          , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME0_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_ICRR_COMM_RECV                          , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV  );
+REG64_FLD( PU_CME7_CME_LCL_ICRR_COMM_RECV_LEN                      , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_ICSR_COMM_SEND                          , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME4_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_ICSR_COMM_SEND                          , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME3_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_ICSR_COMM_SEND                         , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME11_CME_LCL_ICSR_COMM_SEND_LEN                     , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_ICSR_COMM_SEND                          , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME2_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_ICSR_COMM_SEND                          , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME5_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_ICSR_COMM_SEND                          , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME9_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_ICSR_COMM_SEND                          , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME6_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_ICSR_COMM_SEND                         , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME10_CME_LCL_ICSR_COMM_SEND_LEN                     , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_ICSR_COMM_SEND                          , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME8_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_ICSR_COMM_SEND                          , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME1_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_ICSR_COMM_SEND                          , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME0_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_ICSR_COMM_SEND                          , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND  );
+REG64_FLD( PU_CME7_CME_LCL_ICSR_COMM_SEND_LEN                      , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME4_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME4_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME4_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME4_CME_LCL_LMCR_FENCE_EISR                         , 36  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_FENCE_EISR );
+REG64_FLD( PU_CME4_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE       , 37  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE );
+REG64_FLD( PU_CME4_CME_LCL_LMCR_PC_DISABLE_DROOP                   , 38  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PC_DISABLE_DROOP );
+
+REG64_FLD( PU_CME3_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME3_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME3_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME3_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME3_CME_LCL_LMCR_FENCE_EISR                         , 36  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_FENCE_EISR );
+REG64_FLD( PU_CME3_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE       , 37  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE );
+REG64_FLD( PU_CME3_CME_LCL_LMCR_PC_DISABLE_DROOP                   , 38  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PC_DISABLE_DROOP );
+
+REG64_FLD( PU_CME11_CME_LCL_LMCR_RESET_IMPRECISE_QERR              , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME11_CME_LCL_LMCR_SET_ECC_INJECT_ERR                , 33  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME11_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE   , 34  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME11_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE   , 35  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME11_CME_LCL_LMCR_FENCE_EISR                        , 36  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_FENCE_EISR );
+REG64_FLD( PU_CME11_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE      , 37  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE );
+REG64_FLD( PU_CME11_CME_LCL_LMCR_PC_DISABLE_DROOP                  , 38  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PC_DISABLE_DROOP );
+
+REG64_FLD( PU_CME2_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME2_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME2_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME2_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME2_CME_LCL_LMCR_FENCE_EISR                         , 36  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_FENCE_EISR );
+REG64_FLD( PU_CME2_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE       , 37  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE );
+REG64_FLD( PU_CME2_CME_LCL_LMCR_PC_DISABLE_DROOP                   , 38  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PC_DISABLE_DROOP );
+
+REG64_FLD( PU_CME5_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME5_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME5_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME5_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME5_CME_LCL_LMCR_FENCE_EISR                         , 36  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_FENCE_EISR );
+REG64_FLD( PU_CME5_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE       , 37  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE );
+REG64_FLD( PU_CME5_CME_LCL_LMCR_PC_DISABLE_DROOP                   , 38  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PC_DISABLE_DROOP );
+
+REG64_FLD( PU_CME9_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME9_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME9_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME9_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME9_CME_LCL_LMCR_FENCE_EISR                         , 36  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_FENCE_EISR );
+REG64_FLD( PU_CME9_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE       , 37  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE );
+REG64_FLD( PU_CME9_CME_LCL_LMCR_PC_DISABLE_DROOP                   , 38  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PC_DISABLE_DROOP );
+
+REG64_FLD( PU_CME6_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME6_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME6_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME6_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME6_CME_LCL_LMCR_FENCE_EISR                         , 36  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_FENCE_EISR );
+REG64_FLD( PU_CME6_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE       , 37  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE );
+REG64_FLD( PU_CME6_CME_LCL_LMCR_PC_DISABLE_DROOP                   , 38  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PC_DISABLE_DROOP );
+
+REG64_FLD( PU_CME10_CME_LCL_LMCR_RESET_IMPRECISE_QERR              , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME10_CME_LCL_LMCR_SET_ECC_INJECT_ERR                , 33  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME10_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE   , 34  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME10_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE   , 35  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME10_CME_LCL_LMCR_FENCE_EISR                        , 36  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_FENCE_EISR );
+REG64_FLD( PU_CME10_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE      , 37  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE );
+REG64_FLD( PU_CME10_CME_LCL_LMCR_PC_DISABLE_DROOP                  , 38  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PC_DISABLE_DROOP );
+
+REG64_FLD( PU_CME8_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME8_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME8_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME8_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME8_CME_LCL_LMCR_FENCE_EISR                         , 36  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_FENCE_EISR );
+REG64_FLD( PU_CME8_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE       , 37  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE );
+REG64_FLD( PU_CME8_CME_LCL_LMCR_PC_DISABLE_DROOP                   , 38  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PC_DISABLE_DROOP );
+
+REG64_FLD( PU_CME1_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME1_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME1_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME1_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME1_CME_LCL_LMCR_FENCE_EISR                         , 36  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_FENCE_EISR );
+REG64_FLD( PU_CME1_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE       , 37  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE );
+REG64_FLD( PU_CME1_CME_LCL_LMCR_PC_DISABLE_DROOP                   , 38  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PC_DISABLE_DROOP );
+
+REG64_FLD( PU_CME0_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME0_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME0_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME0_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME0_CME_LCL_LMCR_FENCE_EISR                         , 36  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_FENCE_EISR );
+REG64_FLD( PU_CME0_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE       , 37  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE );
+REG64_FLD( PU_CME0_CME_LCL_LMCR_PC_DISABLE_DROOP                   , 38  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PC_DISABLE_DROOP );
+
+REG64_FLD( PU_CME7_CME_LCL_LMCR_RESET_IMPRECISE_QERR               , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( PU_CME7_CME_LCL_LMCR_SET_ECC_INJECT_ERR                 , 33  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( PU_CME7_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE    , 34  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME7_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE    , 35  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( PU_CME7_CME_LCL_LMCR_FENCE_EISR                         , 36  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_FENCE_EISR );
+REG64_FLD( PU_CME7_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE       , 37  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE );
+REG64_FLD( PU_CME7_CME_LCL_LMCR_PC_DISABLE_DROOP                   , 38  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PC_DISABLE_DROOP );
+
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_USE_PECE                        , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME4_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_USE_PECE                        , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME3_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T0                    , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T0_LEN                , 6   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T1                    , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T1_LEN                , 6   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T2                    , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T2_LEN                , 6   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T3                    , 24  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T3_LEN                , 6   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_USE_PECE                       , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME11_CME_LCL_PECESR0_USE_PECE_LEN                   , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_USE_PECE                        , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME2_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_USE_PECE                        , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME5_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_USE_PECE                        , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME9_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_USE_PECE                        , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME6_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T0                    , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T0_LEN                , 6   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T1                    , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T1_LEN                , 6   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T2                    , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T2_LEN                , 6   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T3                    , 24  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T3_LEN                , 6   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_USE_PECE                       , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME10_CME_LCL_PECESR0_USE_PECE_LEN                   , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_USE_PECE                        , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME8_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_USE_PECE                        , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME1_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_USE_PECE                        , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME0_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_USE_PECE                        , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME7_CME_LCL_PECESR0_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_USE_PECE                        , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME4_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_USE_PECE                        , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME3_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T0                    , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T0_LEN                , 6   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T1                    , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T1_LEN                , 6   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T2                    , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T2_LEN                , 6   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T3                    , 24  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T3_LEN                , 6   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_USE_PECE                       , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME11_CME_LCL_PECESR1_USE_PECE_LEN                   , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_USE_PECE                        , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME2_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_USE_PECE                        , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME5_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_USE_PECE                        , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME9_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_USE_PECE                        , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME6_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T0                    , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T0_LEN                , 6   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T1                    , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T1_LEN                , 6   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T2                    , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T2_LEN                , 6   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T3                    , 24  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T3_LEN                , 6   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_USE_PECE                       , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME10_CME_LCL_PECESR1_USE_PECE_LEN                   , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_USE_PECE                        , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME8_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_USE_PECE                        , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME1_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_USE_PECE                        , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME0_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T0                     , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T0_LEN                 , 6   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T1                     , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T1_LEN                 , 6   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T2                     , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T2_LEN                 , 6   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T3                     , 24  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T3_LEN                 , 6   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_USE_PECE                        , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( PU_CME7_CME_LCL_PECESR1_USE_PECE_LEN                    , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C0_ACTUAL );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             , 1   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C1_ACTUAL );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C0_ACTUAL );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  , 5   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C1_ACTUAL );
+REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_6_8                       , 6   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_6_8_LEN                   , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8_LEN );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_FUSED_CORE_MODE                 , 9   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PC_FUSED_CORE_MODE );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_12_15                     , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_12_15_LEN                 , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME4_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL );
+REG64_FLD( PU_CME4_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      , 17  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL );
+REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_18_29                     , 18  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_18_29_LEN                 , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29_LEN );
+REG64_FLD( PU_CME4_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       , 30  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 33  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 34  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 35  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C0                        , 36  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C1                        , 40  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 44  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 45  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 46  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 47  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 48  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 52  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+REG64_FLD( PU_CME4_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 56  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME4_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 57  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C1 );
+
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C0_ACTUAL );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             , 1   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C1_ACTUAL );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C0_ACTUAL );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  , 5   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C1_ACTUAL );
+REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_6_8                       , 6   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_6_8_LEN                   , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8_LEN );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_FUSED_CORE_MODE                 , 9   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PC_FUSED_CORE_MODE );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_12_15                     , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_12_15_LEN                 , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME3_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL );
+REG64_FLD( PU_CME3_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      , 17  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL );
+REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_18_29                     , 18  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_18_29_LEN                 , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29_LEN );
+REG64_FLD( PU_CME3_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       , 30  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 33  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 34  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 35  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C0                        , 36  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C1                        , 40  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 44  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 45  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 46  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 47  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 48  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 52  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+REG64_FLD( PU_CME3_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 56  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME3_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 57  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C1 );
+
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL            , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C0_ACTUAL );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL            , 1   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C1_ACTUAL );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL     , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL     , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                 , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C0_ACTUAL );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                 , 5   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C1_ACTUAL );
+REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_6_8                      , 6   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_6_8_LEN                  , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8_LEN );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_FUSED_CORE_MODE                , 9   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PC_FUSED_CORE_MODE );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PCBMUX_GRANT_C0                   , 10  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PCBMUX_GRANT_C1                   , 11  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_12_15                    , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_12_15_LEN                , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME11_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL     , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL );
+REG64_FLD( PU_CME11_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL     , 17  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL );
+REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_18_29                    , 18  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_18_29_LEN                , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29_LEN );
+REG64_FLD( PU_CME11_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1      , 30  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN  , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C0               , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C1               , 33  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ACTIVE_C0                , 34  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ACTIVE_C1                , 35  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C0                       , 36  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C0_LEN                   , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C1                       , 40  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C1_LEN                   , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ALL_HV_C0                , 44  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ALL_HV_C1                , 45  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_INSTR_RUNNING_C0               , 46  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_INSTR_RUNNING_C1               , 47  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C0              , 48  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN          , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C1              , 52  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN          , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+REG64_FLD( PU_CME11_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0               , 56  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME11_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1               , 57  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C1 );
+
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C0_ACTUAL );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             , 1   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C1_ACTUAL );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C0_ACTUAL );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  , 5   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C1_ACTUAL );
+REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_6_8                       , 6   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_6_8_LEN                   , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8_LEN );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_FUSED_CORE_MODE                 , 9   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PC_FUSED_CORE_MODE );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_12_15                     , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_12_15_LEN                 , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME2_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL );
+REG64_FLD( PU_CME2_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      , 17  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL );
+REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_18_29                     , 18  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_18_29_LEN                 , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29_LEN );
+REG64_FLD( PU_CME2_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       , 30  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 33  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 34  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 35  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C0                        , 36  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C1                        , 40  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 44  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 45  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 46  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 47  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 48  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 52  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+REG64_FLD( PU_CME2_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 56  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME2_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 57  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C1 );
+
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C0_ACTUAL );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             , 1   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C1_ACTUAL );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C0_ACTUAL );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  , 5   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C1_ACTUAL );
+REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_6_8                       , 6   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_6_8_LEN                   , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8_LEN );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_FUSED_CORE_MODE                 , 9   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PC_FUSED_CORE_MODE );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_12_15                     , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_12_15_LEN                 , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME5_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL );
+REG64_FLD( PU_CME5_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      , 17  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL );
+REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_18_29                     , 18  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_18_29_LEN                 , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29_LEN );
+REG64_FLD( PU_CME5_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       , 30  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 33  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 34  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 35  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C0                        , 36  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C1                        , 40  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 44  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 45  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 46  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 47  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 48  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 52  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+REG64_FLD( PU_CME5_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 56  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME5_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 57  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C1 );
+
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C0_ACTUAL );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             , 1   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C1_ACTUAL );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C0_ACTUAL );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  , 5   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C1_ACTUAL );
+REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_6_8                       , 6   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_6_8_LEN                   , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8_LEN );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_FUSED_CORE_MODE                 , 9   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PC_FUSED_CORE_MODE );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_12_15                     , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_12_15_LEN                 , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME9_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL );
+REG64_FLD( PU_CME9_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      , 17  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL );
+REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_18_29                     , 18  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_18_29_LEN                 , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29_LEN );
+REG64_FLD( PU_CME9_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       , 30  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 33  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 34  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 35  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C0                        , 36  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C1                        , 40  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 44  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 45  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 46  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 47  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 48  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 52  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+REG64_FLD( PU_CME9_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 56  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME9_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 57  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C1 );
+
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C0_ACTUAL );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             , 1   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C1_ACTUAL );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C0_ACTUAL );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  , 5   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C1_ACTUAL );
+REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_6_8                       , 6   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_6_8_LEN                   , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8_LEN );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_FUSED_CORE_MODE                 , 9   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PC_FUSED_CORE_MODE );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_12_15                     , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_12_15_LEN                 , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME6_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL );
+REG64_FLD( PU_CME6_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      , 17  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL );
+REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_18_29                     , 18  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_18_29_LEN                 , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29_LEN );
+REG64_FLD( PU_CME6_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       , 30  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 33  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 34  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 35  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C0                        , 36  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C1                        , 40  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 44  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 45  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 46  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 47  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 48  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 52  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+REG64_FLD( PU_CME6_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 56  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME6_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 57  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C1 );
+
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL            , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C0_ACTUAL );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL            , 1   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C1_ACTUAL );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL     , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL     , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                 , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C0_ACTUAL );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                 , 5   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C1_ACTUAL );
+REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_6_8                      , 6   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_6_8_LEN                  , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8_LEN );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_FUSED_CORE_MODE                , 9   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PC_FUSED_CORE_MODE );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PCBMUX_GRANT_C0                   , 10  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PCBMUX_GRANT_C1                   , 11  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_12_15                    , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_12_15_LEN                , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME10_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL     , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL );
+REG64_FLD( PU_CME10_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL     , 17  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL );
+REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_18_29                    , 18  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_18_29_LEN                , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29_LEN );
+REG64_FLD( PU_CME10_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1      , 30  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN  , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C0               , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C1               , 33  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ACTIVE_C0                , 34  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ACTIVE_C1                , 35  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C0                       , 36  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C0_LEN                   , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C1                       , 40  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C1_LEN                   , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ALL_HV_C0                , 44  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ALL_HV_C1                , 45  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_INSTR_RUNNING_C0               , 46  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_INSTR_RUNNING_C1               , 47  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C0              , 48  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN          , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C1              , 52  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN          , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+REG64_FLD( PU_CME10_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0               , 56  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME10_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1               , 57  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C1 );
+
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C0_ACTUAL );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             , 1   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C1_ACTUAL );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C0_ACTUAL );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  , 5   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C1_ACTUAL );
+REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_6_8                       , 6   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_6_8_LEN                   , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8_LEN );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_FUSED_CORE_MODE                 , 9   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PC_FUSED_CORE_MODE );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_12_15                     , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_12_15_LEN                 , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME8_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL );
+REG64_FLD( PU_CME8_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      , 17  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL );
+REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_18_29                     , 18  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_18_29_LEN                 , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29_LEN );
+REG64_FLD( PU_CME8_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       , 30  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 33  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 34  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 35  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C0                        , 36  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C1                        , 40  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 44  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 45  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 46  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 47  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 48  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 52  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+REG64_FLD( PU_CME8_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 56  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME8_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 57  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C1 );
+
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C0_ACTUAL );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             , 1   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C1_ACTUAL );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C0_ACTUAL );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  , 5   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C1_ACTUAL );
+REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_6_8                       , 6   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_6_8_LEN                   , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8_LEN );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_FUSED_CORE_MODE                 , 9   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PC_FUSED_CORE_MODE );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_12_15                     , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_12_15_LEN                 , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME1_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL );
+REG64_FLD( PU_CME1_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      , 17  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL );
+REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_18_29                     , 18  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_18_29_LEN                 , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29_LEN );
+REG64_FLD( PU_CME1_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       , 30  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 33  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 34  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 35  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C0                        , 36  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C1                        , 40  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 44  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 45  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 46  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 47  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 48  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 52  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+REG64_FLD( PU_CME1_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 56  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME1_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 57  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C1 );
+
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C0_ACTUAL );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             , 1   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C1_ACTUAL );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C0_ACTUAL );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  , 5   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C1_ACTUAL );
+REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_6_8                       , 6   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_6_8_LEN                   , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8_LEN );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_FUSED_CORE_MODE                 , 9   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PC_FUSED_CORE_MODE );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_12_15                     , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_12_15_LEN                 , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME0_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL );
+REG64_FLD( PU_CME0_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      , 17  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL );
+REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_18_29                     , 18  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_18_29_LEN                 , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29_LEN );
+REG64_FLD( PU_CME0_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       , 30  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 33  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 34  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 35  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C0                        , 36  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C1                        , 40  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 44  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 45  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 46  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 47  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 48  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 52  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+REG64_FLD( PU_CME0_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 56  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME0_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 57  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C1 );
+
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL             , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C0_ACTUAL );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL             , 1   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PM_ENTRY_ACK_C1_ACTUAL );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL      , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL      , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                  , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C0_ACTUAL );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                  , 5   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PM_EXIT_C1_ACTUAL );
+REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_6_8                       , 6   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_6_8_LEN                   , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_6_8_LEN );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_FUSED_CORE_MODE                 , 9   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PC_FUSED_CORE_MODE );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PCBMUX_GRANT_C0                    , 10  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PCBMUX_GRANT_C1                    , 11  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_12_15                     , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_12_15_LEN                 , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME7_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL      , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL );
+REG64_FLD( PU_CME7_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL      , 17  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL );
+REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_18_29                     , 18  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_18_29_LEN                 , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_18_29_LEN );
+REG64_FLD( PU_CME7_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1       , 30  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN   , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                , 33  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ACTIVE_C0                 , 34  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ACTIVE_C1                 , 35  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C0                        , 36  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C0_LEN                    , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C1                        , 40  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C1_LEN                    , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ALL_HV_C0                 , 44  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ALL_HV_C1                 , 45  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_INSTR_RUNNING_C0                , 46  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_INSTR_RUNNING_C1                , 47  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C0               , 48  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN           , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C1               , 52  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN           , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+REG64_FLD( PU_CME7_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                , 56  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( PU_CME7_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                , 57  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_ALLOW_REG_WAKEUP_C1 );
+
+REG64_FLD( PU_CME4_CME_LCL_TSEL_FIT_SEL                            , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME4_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME4_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME4_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME3_CME_LCL_TSEL_FIT_SEL                            , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME3_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME3_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME3_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME11_CME_LCL_TSEL_FIT_SEL                           , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME11_CME_LCL_TSEL_FIT_SEL_LEN                       , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME11_CME_LCL_TSEL_WATCHDOG_SEL                      , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME11_CME_LCL_TSEL_WATCHDOG_SEL_LEN                  , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME2_CME_LCL_TSEL_FIT_SEL                            , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME2_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME2_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME2_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME5_CME_LCL_TSEL_FIT_SEL                            , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME5_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME5_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME5_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME9_CME_LCL_TSEL_FIT_SEL                            , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME9_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME9_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME9_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME6_CME_LCL_TSEL_FIT_SEL                            , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME6_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME6_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME6_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME10_CME_LCL_TSEL_FIT_SEL                           , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME10_CME_LCL_TSEL_FIT_SEL_LEN                       , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME10_CME_LCL_TSEL_WATCHDOG_SEL                      , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME10_CME_LCL_TSEL_WATCHDOG_SEL_LEN                  , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME8_CME_LCL_TSEL_FIT_SEL                            , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME8_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME8_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME8_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME1_CME_LCL_TSEL_FIT_SEL                            , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME1_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME1_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME1_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME0_CME_LCL_TSEL_FIT_SEL                            , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME0_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME0_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME0_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME7_CME_LCL_TSEL_FIT_SEL                            , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_CME7_CME_LCL_TSEL_FIT_SEL_LEN                        , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_CME7_CME_LCL_TSEL_WATCHDOG_SEL                       , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_CME7_CME_LCL_TSEL_WATCHDOG_SEL_LEN                   , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME4_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME4_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME3_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME3_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME3_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME11_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME11_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN            , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                 , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME11_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_AFSR_SAMPLE_VALID                     , 63  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME2_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME2_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME2_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME5_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME5_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME5_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME9_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME9_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME9_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME6_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME6_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME6_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME10_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME10_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN            , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                 , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME10_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_AFSR_SAMPLE_VALID                     , 63  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME8_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME8_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME8_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME1_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME1_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME1_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME0_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME0_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME0_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME7_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                 , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( PU_CME7_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( PU_CME7_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_AFSR_SAMPLE_VALID                      , 63  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( PU_CME4_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME4_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME4_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME3_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME3_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                 , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME11_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                 , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME11_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME2_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME2_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME5_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME5_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME9_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME9_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME6_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME6_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                 , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME10_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                 , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME10_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN             , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME8_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME8_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME1_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME1_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME0_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME0_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                  , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( PU_CME7_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                  , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( PU_CME7_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN              , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_BUSY                            , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_ERROR                           , 1   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_RNW                             , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_RNW        );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_BARSEL                          , 5   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_BARSEL     );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_PRIORITY                        , 6   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_INJECT_ERR                      , 7   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_TYPE                            , 13  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_TYPE       );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_TYPE_LEN                        , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_SBASE                           , 28  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SBASE      );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_SBASE_LEN                       , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_MBASE                           , 42  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MBASE      );
+REG64_FLD( PU_CME4_CME_SCOM_BCECSR_MBASE_LEN                       , 22  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_BUSY                            , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_ERROR                           , 1   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_RNW                             , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_RNW        );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_BARSEL                          , 5   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_BARSEL     );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_PRIORITY                        , 6   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_INJECT_ERR                      , 7   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_TYPE                            , 13  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_TYPE       );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_TYPE_LEN                        , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_SBASE                           , 28  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SBASE      );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_SBASE_LEN                       , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_MBASE                           , 42  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MBASE      );
+REG64_FLD( PU_CME3_CME_SCOM_BCECSR_MBASE_LEN                       , 22  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_BUSY                           , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_ERROR                          , 1   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_RNW                            , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_RNW        );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_BARSEL                         , 5   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_BARSEL     );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_PRIORITY                       , 6   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_INJECT_ERR                     , 7   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_TYPE                           , 13  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_TYPE       );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_TYPE_LEN                       , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_NUM_BLOCKS                     , 17  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                 , 11  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_SBASE                          , 28  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SBASE      );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_SBASE_LEN                      , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_MBASE                          , 42  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MBASE      );
+REG64_FLD( PU_CME11_CME_SCOM_BCECSR_MBASE_LEN                      , 22  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_BUSY                            , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_ERROR                           , 1   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_RNW                             , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_RNW        );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_BARSEL                          , 5   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_BARSEL     );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_PRIORITY                        , 6   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_INJECT_ERR                      , 7   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_TYPE                            , 13  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_TYPE       );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_TYPE_LEN                        , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_SBASE                           , 28  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SBASE      );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_SBASE_LEN                       , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_MBASE                           , 42  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MBASE      );
+REG64_FLD( PU_CME2_CME_SCOM_BCECSR_MBASE_LEN                       , 22  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_BUSY                            , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_ERROR                           , 1   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_RNW                             , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_RNW        );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_BARSEL                          , 5   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_BARSEL     );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_PRIORITY                        , 6   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_INJECT_ERR                      , 7   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_TYPE                            , 13  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_TYPE       );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_TYPE_LEN                        , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_SBASE                           , 28  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SBASE      );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_SBASE_LEN                       , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_MBASE                           , 42  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MBASE      );
+REG64_FLD( PU_CME5_CME_SCOM_BCECSR_MBASE_LEN                       , 22  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_BUSY                            , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_ERROR                           , 1   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_RNW                             , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_RNW        );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_BARSEL                          , 5   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_BARSEL     );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_PRIORITY                        , 6   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_INJECT_ERR                      , 7   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_TYPE                            , 13  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_TYPE       );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_TYPE_LEN                        , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_SBASE                           , 28  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SBASE      );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_SBASE_LEN                       , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_MBASE                           , 42  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MBASE      );
+REG64_FLD( PU_CME9_CME_SCOM_BCECSR_MBASE_LEN                       , 22  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_BUSY                            , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_ERROR                           , 1   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_RNW                             , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_RNW        );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_BARSEL                          , 5   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_BARSEL     );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_PRIORITY                        , 6   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_INJECT_ERR                      , 7   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_TYPE                            , 13  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_TYPE       );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_TYPE_LEN                        , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_SBASE                           , 28  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SBASE      );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_SBASE_LEN                       , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_MBASE                           , 42  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MBASE      );
+REG64_FLD( PU_CME6_CME_SCOM_BCECSR_MBASE_LEN                       , 22  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_BUSY                           , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_ERROR                          , 1   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_RNW                            , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_RNW        );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_BARSEL                         , 5   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_BARSEL     );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_PRIORITY                       , 6   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_INJECT_ERR                     , 7   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_TYPE                           , 13  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_TYPE       );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_TYPE_LEN                       , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_NUM_BLOCKS                     , 17  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                 , 11  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_SBASE                          , 28  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SBASE      );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_SBASE_LEN                      , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_MBASE                          , 42  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MBASE      );
+REG64_FLD( PU_CME10_CME_SCOM_BCECSR_MBASE_LEN                      , 22  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_BUSY                            , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_ERROR                           , 1   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_RNW                             , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_RNW        );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_BARSEL                          , 5   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_BARSEL     );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_PRIORITY                        , 6   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_INJECT_ERR                      , 7   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_TYPE                            , 13  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_TYPE       );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_TYPE_LEN                        , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_SBASE                           , 28  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SBASE      );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_SBASE_LEN                       , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_MBASE                           , 42  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MBASE      );
+REG64_FLD( PU_CME8_CME_SCOM_BCECSR_MBASE_LEN                       , 22  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_BUSY                            , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_ERROR                           , 1   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_RNW                             , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_RNW        );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_BARSEL                          , 5   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_BARSEL     );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_PRIORITY                        , 6   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_INJECT_ERR                      , 7   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_TYPE                            , 13  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_TYPE       );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_TYPE_LEN                        , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_SBASE                           , 28  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SBASE      );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_SBASE_LEN                       , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_MBASE                           , 42  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MBASE      );
+REG64_FLD( PU_CME1_CME_SCOM_BCECSR_MBASE_LEN                       , 22  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_BUSY                            , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_ERROR                           , 1   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_RNW                             , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_RNW        );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_BARSEL                          , 5   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_BARSEL     );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_PRIORITY                        , 6   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_INJECT_ERR                      , 7   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_TYPE                            , 13  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_TYPE       );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_TYPE_LEN                        , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_SBASE                           , 28  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SBASE      );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_SBASE_LEN                       , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_MBASE                           , 42  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MBASE      );
+REG64_FLD( PU_CME0_CME_SCOM_BCECSR_MBASE_LEN                       , 22  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_BUSY                            , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_ERROR                           , 1   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_RNW                             , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_RNW        );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_BARSEL                          , 5   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_BARSEL     );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_PRIORITY                        , 6   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_INJECT_ERR                      , 7   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INJECT_ERR );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_TYPE                            , 13  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_TYPE       );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_TYPE_LEN                        , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_NUM_BLOCKS                      , 17  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                  , 11  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_SBASE                           , 28  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SBASE      );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_SBASE_LEN                       , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SBASE_LEN  );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_MBASE                           , 42  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MBASE      );
+REG64_FLD( PU_CME7_CME_SCOM_BCECSR_MBASE_LEN                       , 22  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MBASE_LEN  );
+
+REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          , 24  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          , 56  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          , 24  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          , 56  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT          , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN      , 24  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT         , 24  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN     , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT          , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN      , 24  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT         , 56  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN     , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          , 24  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          , 56  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          , 24  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          , 56  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          , 24  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          , 56  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          , 24  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          , 56  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT          , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN      , 24  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT         , 24  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN     , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT          , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN      , 24  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT         , 56  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN     , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          , 24  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          , 56  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          , 24  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          , 56  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          , 24  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          , 56  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT           , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT          , 24  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT           , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN       , 24  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT          , 56  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN      , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_FLAGS_DATA                             , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME4_CME_SCOM_FLAGS_DATA_LEN                         , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME3_CME_SCOM_FLAGS_DATA                             , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME3_CME_SCOM_FLAGS_DATA_LEN                         , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME11_CME_SCOM_FLAGS_DATA                            , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME11_CME_SCOM_FLAGS_DATA_LEN                        , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME2_CME_SCOM_FLAGS_DATA                             , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME2_CME_SCOM_FLAGS_DATA_LEN                         , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME5_CME_SCOM_FLAGS_DATA                             , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME5_CME_SCOM_FLAGS_DATA_LEN                         , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME9_CME_SCOM_FLAGS_DATA                             , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME9_CME_SCOM_FLAGS_DATA_LEN                         , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME6_CME_SCOM_FLAGS_DATA                             , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME6_CME_SCOM_FLAGS_DATA_LEN                         , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME10_CME_SCOM_FLAGS_DATA                            , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME10_CME_SCOM_FLAGS_DATA_LEN                        , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME8_CME_SCOM_FLAGS_DATA                             , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME8_CME_SCOM_FLAGS_DATA_LEN                         , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME1_CME_SCOM_FLAGS_DATA                             , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME1_CME_SCOM_FLAGS_DATA_LEN                         , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME0_CME_SCOM_FLAGS_DATA                             , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME0_CME_SCOM_FLAGS_DATA_LEN                         , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME7_CME_SCOM_FLAGS_DATA                             , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME7_CME_SCOM_FLAGS_DATA_LEN                         , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       , 24  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          , 24  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_TIMER_MODE );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 , 33  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_CHAR_MODE );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       , 34  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               , 36  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              , 38  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_SPARE                             , 39  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             , 40  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_NOTIFY_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_SPARE41_43                        , 41  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               , 59  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE );
+REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           , 5   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       , 24  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          , 24  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_TIMER_MODE );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 , 33  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_CHAR_MODE );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       , 34  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               , 36  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              , 38  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_SPARE                             , 39  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             , 40  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_NOTIFY_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_SPARE41_43                        , 41  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               , 59  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE );
+REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           , 5   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD          , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN      , 24  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD         , 24  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN     , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_TIMER_MODE               , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_TIMER_MODE );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                , 33  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_CHAR_MODE );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE      , 34  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN  , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE              , 36  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN          , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE             , 38  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_SPARE                            , 39  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE            , 40  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_NOTIFY_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_SPARE41_43                       , 41  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_SPARE41_43_LEN                   , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE              , 59  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE );
+REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN          , 5   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       , 24  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          , 24  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_TIMER_MODE );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 , 33  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_CHAR_MODE );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       , 34  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               , 36  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              , 38  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_SPARE                             , 39  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             , 40  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_NOTIFY_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_SPARE41_43                        , 41  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               , 59  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE );
+REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           , 5   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       , 24  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          , 24  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_TIMER_MODE );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 , 33  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_CHAR_MODE );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       , 34  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               , 36  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              , 38  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_SPARE                             , 39  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             , 40  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_NOTIFY_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_SPARE41_43                        , 41  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               , 59  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE );
+REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           , 5   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       , 24  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          , 24  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_TIMER_MODE );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 , 33  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_CHAR_MODE );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       , 34  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               , 36  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              , 38  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_SPARE                             , 39  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             , 40  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_NOTIFY_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_SPARE41_43                        , 41  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               , 59  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE );
+REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           , 5   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       , 24  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          , 24  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_TIMER_MODE );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 , 33  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_CHAR_MODE );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       , 34  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               , 36  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              , 38  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_SPARE                             , 39  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             , 40  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_NOTIFY_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_SPARE41_43                        , 41  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               , 59  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE );
+REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           , 5   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD          , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN      , 24  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD         , 24  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN     , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_TIMER_MODE               , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_TIMER_MODE );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                , 33  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_CHAR_MODE );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE      , 34  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN  , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE              , 36  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN          , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE             , 38  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_SPARE                            , 39  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE            , 40  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_NOTIFY_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_SPARE41_43                       , 41  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_SPARE41_43_LEN                   , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE              , 59  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE );
+REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN          , 5   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       , 24  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          , 24  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_TIMER_MODE );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 , 33  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_CHAR_MODE );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       , 34  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               , 36  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              , 38  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_SPARE                             , 39  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             , 40  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_NOTIFY_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_SPARE41_43                        , 41  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               , 59  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE );
+REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           , 5   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       , 24  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          , 24  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_TIMER_MODE );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 , 33  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_CHAR_MODE );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       , 34  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               , 36  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              , 38  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_SPARE                             , 39  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             , 40  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_NOTIFY_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_SPARE41_43                        , 41  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               , 59  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE );
+REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           , 5   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       , 24  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          , 24  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_TIMER_MODE );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 , 33  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_CHAR_MODE );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       , 34  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               , 36  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              , 38  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_SPARE                             , 39  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             , 40  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_NOTIFY_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_SPARE41_43                        , 41  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               , 59  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE );
+REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           , 5   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD           , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN       , 24  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD          , 24  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN      , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_TIMER_MODE );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                 , 33  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_CHAR_MODE );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE       , 34  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN   , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE               , 36  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN           , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE              , 38  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_SPARE                             , 39  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE             , 40  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_NOTIFY_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_SPARE41_43                        , 41  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE               , 59  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE );
+REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN           , 5   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_PMCRS0_DATA                            , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME4_CME_SCOM_PMCRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME3_CME_SCOM_PMCRS0_DATA                            , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME3_CME_SCOM_PMCRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME11_CME_SCOM_PMCRS0_DATA                           , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME11_CME_SCOM_PMCRS0_DATA_LEN                       , 64  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME2_CME_SCOM_PMCRS0_DATA                            , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME2_CME_SCOM_PMCRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME5_CME_SCOM_PMCRS0_DATA                            , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME5_CME_SCOM_PMCRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME9_CME_SCOM_PMCRS0_DATA                            , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME9_CME_SCOM_PMCRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME6_CME_SCOM_PMCRS0_DATA                            , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME6_CME_SCOM_PMCRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME10_CME_SCOM_PMCRS0_DATA                           , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME10_CME_SCOM_PMCRS0_DATA_LEN                       , 64  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME8_CME_SCOM_PMCRS0_DATA                            , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME8_CME_SCOM_PMCRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME1_CME_SCOM_PMCRS0_DATA                            , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME1_CME_SCOM_PMCRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME0_CME_SCOM_PMCRS0_DATA                            , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME0_CME_SCOM_PMCRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME7_CME_SCOM_PMCRS0_DATA                            , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME7_CME_SCOM_PMCRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME4_CME_SCOM_PMCRS1_DATA                            , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME4_CME_SCOM_PMCRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME3_CME_SCOM_PMCRS1_DATA                            , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME3_CME_SCOM_PMCRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME11_CME_SCOM_PMCRS1_DATA                           , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME11_CME_SCOM_PMCRS1_DATA_LEN                       , 64  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME2_CME_SCOM_PMCRS1_DATA                            , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME2_CME_SCOM_PMCRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME5_CME_SCOM_PMCRS1_DATA                            , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME5_CME_SCOM_PMCRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME9_CME_SCOM_PMCRS1_DATA                            , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME9_CME_SCOM_PMCRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME6_CME_SCOM_PMCRS1_DATA                            , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME6_CME_SCOM_PMCRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME10_CME_SCOM_PMCRS1_DATA                           , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME10_CME_SCOM_PMCRS1_DATA_LEN                       , 64  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME8_CME_SCOM_PMCRS1_DATA                            , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME8_CME_SCOM_PMCRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME1_CME_SCOM_PMCRS1_DATA                            , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME1_CME_SCOM_PMCRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME0_CME_SCOM_PMCRS1_DATA                            , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME0_CME_SCOM_PMCRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME7_CME_SCOM_PMCRS1_DATA                            , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME7_CME_SCOM_PMCRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME4_CME_SCOM_PMSRS0_DATA                            , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME4_CME_SCOM_PMSRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME3_CME_SCOM_PMSRS0_DATA                            , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME3_CME_SCOM_PMSRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME11_CME_SCOM_PMSRS0_DATA                           , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME11_CME_SCOM_PMSRS0_DATA_LEN                       , 64  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME2_CME_SCOM_PMSRS0_DATA                            , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME2_CME_SCOM_PMSRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME5_CME_SCOM_PMSRS0_DATA                            , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME5_CME_SCOM_PMSRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME9_CME_SCOM_PMSRS0_DATA                            , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME9_CME_SCOM_PMSRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME6_CME_SCOM_PMSRS0_DATA                            , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME6_CME_SCOM_PMSRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME10_CME_SCOM_PMSRS0_DATA                           , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME10_CME_SCOM_PMSRS0_DATA_LEN                       , 64  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME8_CME_SCOM_PMSRS0_DATA                            , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME8_CME_SCOM_PMSRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME1_CME_SCOM_PMSRS0_DATA                            , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME1_CME_SCOM_PMSRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME0_CME_SCOM_PMSRS0_DATA                            , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME0_CME_SCOM_PMSRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME7_CME_SCOM_PMSRS0_DATA                            , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME7_CME_SCOM_PMSRS0_DATA_LEN                        , 64  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME4_CME_SCOM_PMSRS1_DATA                            , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME4_CME_SCOM_PMSRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME3_CME_SCOM_PMSRS1_DATA                            , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME3_CME_SCOM_PMSRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME11_CME_SCOM_PMSRS1_DATA                           , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME11_CME_SCOM_PMSRS1_DATA_LEN                       , 64  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME2_CME_SCOM_PMSRS1_DATA                            , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME2_CME_SCOM_PMSRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME5_CME_SCOM_PMSRS1_DATA                            , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME5_CME_SCOM_PMSRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME9_CME_SCOM_PMSRS1_DATA                            , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME9_CME_SCOM_PMSRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME6_CME_SCOM_PMSRS1_DATA                            , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME6_CME_SCOM_PMSRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME10_CME_SCOM_PMSRS1_DATA                           , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME10_CME_SCOM_PMSRS1_DATA_LEN                       , 64  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME8_CME_SCOM_PMSRS1_DATA                            , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME8_CME_SCOM_PMSRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME1_CME_SCOM_PMSRS1_DATA                            , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME1_CME_SCOM_PMSRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME0_CME_SCOM_PMSRS1_DATA                            , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME0_CME_SCOM_PMSRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME7_CME_SCOM_PMSRS1_DATA                            , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME7_CME_SCOM_PMSRS1_DATA_LEN                        , 64  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_SPARE0                         , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_SPARE0                         , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_SPARE0                        , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_SPARE0                         , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_SPARE0                         , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_SPARE0                         , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_SPARE0                         , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_SPARE0                        , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_SPARE0                         , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_SPARE0                         , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_SPARE0                         , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_SPARE0                         , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_SPARE0                         , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_SPARE0                         , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_SPARE0                        , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_SPARE0                         , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_SPARE0                         , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_SPARE0                         , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_SPARE0                         , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_SPARE0                        , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_SPARE0                         , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_SPARE0                         , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_SPARE0                         , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_SPARE0                         , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_SPARE0                         , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_SPARE0                         , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_SPARE0                        , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_SPARE0                         , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_SPARE0                         , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_SPARE0                         , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_SPARE0                         , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_SPARE0                        , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_SPARE0                         , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_SPARE0                         , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_SPARE0                         , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_SPARE0                         , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_SPARE0                         , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_SPARE0                         , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_SPARE0                        , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_SPARE0                         , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_SPARE0                         , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_SPARE0                         , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_SPARE0                         , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_SPARE0                        , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_SPARE0                         , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_SPARE0                         , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_SPARE0                         , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_SPARE0                         , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_SPARE0                         , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_SPARE0                         , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_SPARE0                        , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_SPARE0                         , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_SPARE0                         , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_SPARE0                         , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_SPARE0                         , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_SPARE0                        , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_SPARE0                         , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_SPARE0                         , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_SPARE0                         , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_SPARE0                         , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_SPARE0                         , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_SPARE0                         , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_SPARE0                        , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_SPARE0                         , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_SPARE0                         , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_SPARE0                         , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_SPARE0                         , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_SPARE0                        , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_SPARE0                         , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_SPARE0                         , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_SPARE0                         , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_SPARE0                         , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_SPARE0                         , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_SPARE0                         , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_SPARE0                        , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_SPARE0                         , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_SPARE0                         , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_SPARE0                         , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_SPARE0                         , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_SPARE0                        , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_SPARE0                         , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_SPARE0                         , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_SPARE0                         , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_SPARE0                         , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_SPARE0                         , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_SPARE0                         , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_SPARE0                        , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_SPARE0                         , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_SPARE0                         , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_SPARE0                         , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_SPARE0                         , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_SPARE0                        , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N         , 1   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N         , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N            , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N        , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE          , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE           , 9   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE        , 10  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE               , 11  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE               , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE               , 13  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N     , 14  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N         , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N        , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN    , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_SPARE0                         , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_SPARE0                         , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_SPARE0                         , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_SPARE0                         , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N          , 1   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N          , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N             , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N         , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE           , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE            , 9   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE         , 10  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                , 11  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                , 13  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N      , 14  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN  , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N          , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN      , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N         , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN     , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_QFMR_TIMEBASE                          , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME4_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_QFMR_CYCLES                            , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES     );
+REG64_FLD( PU_CME4_CME_SCOM_QFMR_CYCLES_LEN                        , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_QFMR_TIMEBASE                          , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME3_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_QFMR_CYCLES                            , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES     );
+REG64_FLD( PU_CME3_CME_SCOM_QFMR_CYCLES_LEN                        , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_QFMR_TIMEBASE                         , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME11_CME_SCOM_QFMR_TIMEBASE_LEN                     , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_QFMR_CYCLES                           , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_CYCLES     );
+REG64_FLD( PU_CME11_CME_SCOM_QFMR_CYCLES_LEN                       , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_QFMR_TIMEBASE                          , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME2_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_QFMR_CYCLES                            , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES     );
+REG64_FLD( PU_CME2_CME_SCOM_QFMR_CYCLES_LEN                        , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_QFMR_TIMEBASE                          , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME5_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_QFMR_CYCLES                            , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES     );
+REG64_FLD( PU_CME5_CME_SCOM_QFMR_CYCLES_LEN                        , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_QFMR_TIMEBASE                          , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME9_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_QFMR_CYCLES                            , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES     );
+REG64_FLD( PU_CME9_CME_SCOM_QFMR_CYCLES_LEN                        , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_QFMR_TIMEBASE                          , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME6_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_QFMR_CYCLES                            , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES     );
+REG64_FLD( PU_CME6_CME_SCOM_QFMR_CYCLES_LEN                        , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_QFMR_TIMEBASE                         , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME10_CME_SCOM_QFMR_TIMEBASE_LEN                     , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_QFMR_CYCLES                           , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_CYCLES     );
+REG64_FLD( PU_CME10_CME_SCOM_QFMR_CYCLES_LEN                       , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_QFMR_TIMEBASE                          , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME8_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_QFMR_CYCLES                            , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES     );
+REG64_FLD( PU_CME8_CME_SCOM_QFMR_CYCLES_LEN                        , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_QFMR_TIMEBASE                          , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME1_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_QFMR_CYCLES                            , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES     );
+REG64_FLD( PU_CME1_CME_SCOM_QFMR_CYCLES_LEN                        , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_QFMR_TIMEBASE                          , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME0_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_QFMR_CYCLES                            , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES     );
+REG64_FLD( PU_CME0_CME_SCOM_QFMR_CYCLES_LEN                        , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_QFMR_TIMEBASE                          , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( PU_CME7_CME_SCOM_QFMR_TIMEBASE_LEN                      , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_QFMR_CYCLES                            , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES     );
+REG64_FLD( PU_CME7_CME_SCOM_QFMR_CYCLES_LEN                        , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_CYCLES_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    , 24  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       , 24  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE );
+REG64_FLD( PU_CME4_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    , 24  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       , 24  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE );
+REG64_FLD( PU_CME3_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT       , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN   , 24  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT      , 24  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN  , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_QIDSR_DROPOUT_SAMPLE                  , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE );
+REG64_FLD( PU_CME11_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN              , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    , 24  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       , 24  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE );
+REG64_FLD( PU_CME2_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    , 24  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       , 24  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE );
+REG64_FLD( PU_CME5_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    , 24  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       , 24  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE );
+REG64_FLD( PU_CME9_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    , 24  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       , 24  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE );
+REG64_FLD( PU_CME6_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT       , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN   , 24  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT      , 24  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN  , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_QIDSR_DROPOUT_SAMPLE                  , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE );
+REG64_FLD( PU_CME10_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN              , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    , 24  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       , 24  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE );
+REG64_FLD( PU_CME8_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    , 24  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       , 24  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE );
+REG64_FLD( PU_CME1_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    , 24  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       , 24  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE );
+REG64_FLD( PU_CME0_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT        , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT );
+REG64_FLD( PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN    , 24  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT       , 24  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT );
+REG64_FLD( PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN   , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_QIDSR_DROPOUT_SAMPLE                   , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE );
+REG64_FLD( PU_CME7_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN               , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROPOUT_SAMPLE_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   , 1   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_EXIT_C0                        , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_EXIT_C1                        , 5   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 7   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 9   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 10  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 11  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_12_15                    , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_12_15_LEN                , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              , 17  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_PURGE                          , 18  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_PURGE_ABORT                    , 19  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED20                        , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED20 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 21  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_PURGE                         , 22  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 23  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_CHTM_PURGE_C0                     , 24  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_CHTM_PURGE_C1                     , 25  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_HMI_REQUEST_C0                    , 26  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_HMI_REQUEST_C1                    , 27  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 28  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 29  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_30_31                    , 30  , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31 );
+REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_30_31_LEN                , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   , 1   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_EXIT_C0                        , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_EXIT_C1                        , 5   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 7   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 9   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 10  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 11  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_12_15                    , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_12_15_LEN                , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              , 17  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_PURGE                          , 18  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_PURGE_ABORT                    , 19  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED20                        , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED20 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 21  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_PURGE                         , 22  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 23  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_CHTM_PURGE_C0                     , 24  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_CHTM_PURGE_C1                     , 25  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_HMI_REQUEST_C0                    , 26  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_HMI_REQUEST_C1                    , 27  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 28  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 29  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_30_31                    , 30  , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31 );
+REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_30_31_LEN                , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_ENTRY_ACK_C0                  , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_ENTRY_ACK_C1                  , 1   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0           , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1           , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_EXIT_C0                       , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_EXIT_C1                       , 5   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0         , 6   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1         , 7   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0          , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1          , 9   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PCBMUX_REQ_C0                    , 10  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PCBMUX_REQ_C1                    , 11  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_12_15                   , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_12_15_LEN               , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0             , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1             , 17  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_PURGE                         , 18  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_PURGE_ABORT                   , 19  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED20                       , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED20 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                , 21  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_PURGE                        , 22  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_PURGE_ABORT                  , 23  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_CHTM_PURGE_C0                    , 24  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_CHTM_PURGE_C1                    , 25  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_HMI_REQUEST_C0                   , 26  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_HMI_REQUEST_C1                   , 27  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PPM_SPARE_OUT_C0                 , 28  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_PPM_SPARE_OUT_C1                 , 29  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_30_31                   , 30  , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31 );
+REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_30_31_LEN               , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   , 1   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_EXIT_C0                        , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_EXIT_C1                        , 5   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 7   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 9   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 10  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 11  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_12_15                    , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_12_15_LEN                , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              , 17  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_PURGE                          , 18  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_PURGE_ABORT                    , 19  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED20                        , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED20 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 21  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_PURGE                         , 22  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 23  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_CHTM_PURGE_C0                     , 24  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_CHTM_PURGE_C1                     , 25  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_HMI_REQUEST_C0                    , 26  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_HMI_REQUEST_C1                    , 27  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 28  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 29  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_30_31                    , 30  , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31 );
+REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_30_31_LEN                , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   , 1   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_EXIT_C0                        , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_EXIT_C1                        , 5   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 7   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 9   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 10  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 11  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_12_15                    , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_12_15_LEN                , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              , 17  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_PURGE                          , 18  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_PURGE_ABORT                    , 19  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED20                        , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED20 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 21  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_PURGE                         , 22  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 23  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_CHTM_PURGE_C0                     , 24  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_CHTM_PURGE_C1                     , 25  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_HMI_REQUEST_C0                    , 26  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_HMI_REQUEST_C1                    , 27  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 28  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 29  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_30_31                    , 30  , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31 );
+REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_30_31_LEN                , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   , 1   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_EXIT_C0                        , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_EXIT_C1                        , 5   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 7   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 9   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 10  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 11  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_12_15                    , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_12_15_LEN                , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              , 17  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_PURGE                          , 18  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_PURGE_ABORT                    , 19  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED20                        , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED20 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 21  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_PURGE                         , 22  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 23  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_CHTM_PURGE_C0                     , 24  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_CHTM_PURGE_C1                     , 25  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_HMI_REQUEST_C0                    , 26  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_HMI_REQUEST_C1                    , 27  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 28  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 29  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_30_31                    , 30  , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31 );
+REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_30_31_LEN                , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   , 1   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_EXIT_C0                        , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_EXIT_C1                        , 5   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 7   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 9   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 10  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 11  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_12_15                    , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_12_15_LEN                , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              , 17  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_PURGE                          , 18  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_PURGE_ABORT                    , 19  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED20                        , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED20 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 21  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_PURGE                         , 22  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 23  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_CHTM_PURGE_C0                     , 24  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_CHTM_PURGE_C1                     , 25  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_HMI_REQUEST_C0                    , 26  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_HMI_REQUEST_C1                    , 27  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 28  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 29  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_30_31                    , 30  , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31 );
+REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_30_31_LEN                , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_ENTRY_ACK_C0                  , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_ENTRY_ACK_C1                  , 1   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0           , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1           , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_EXIT_C0                       , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_EXIT_C1                       , 5   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0         , 6   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1         , 7   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0          , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1          , 9   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PCBMUX_REQ_C0                    , 10  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PCBMUX_REQ_C1                    , 11  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_12_15                   , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_12_15_LEN               , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0             , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1             , 17  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_PURGE                         , 18  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_PURGE_ABORT                   , 19  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED20                       , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED20 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                , 21  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_PURGE                        , 22  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_PURGE_ABORT                  , 23  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_CHTM_PURGE_C0                    , 24  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_CHTM_PURGE_C1                    , 25  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_HMI_REQUEST_C0                   , 26  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_HMI_REQUEST_C1                   , 27  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PPM_SPARE_OUT_C0                 , 28  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_PPM_SPARE_OUT_C1                 , 29  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_30_31                   , 30  , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31 );
+REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_30_31_LEN               , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   , 1   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_EXIT_C0                        , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_EXIT_C1                        , 5   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 7   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 9   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 10  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 11  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_12_15                    , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_12_15_LEN                , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              , 17  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_PURGE                          , 18  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_PURGE_ABORT                    , 19  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED20                        , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED20 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 21  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_PURGE                         , 22  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 23  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_CHTM_PURGE_C0                     , 24  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_CHTM_PURGE_C1                     , 25  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_HMI_REQUEST_C0                    , 26  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_HMI_REQUEST_C1                    , 27  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 28  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 29  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_30_31                    , 30  , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31 );
+REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_30_31_LEN                , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   , 1   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_EXIT_C0                        , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_EXIT_C1                        , 5   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 7   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 9   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 10  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 11  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_12_15                    , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_12_15_LEN                , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              , 17  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_PURGE                          , 18  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_PURGE_ABORT                    , 19  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED20                        , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED20 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 21  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_PURGE                         , 22  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 23  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_CHTM_PURGE_C0                     , 24  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_CHTM_PURGE_C1                     , 25  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_HMI_REQUEST_C0                    , 26  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_HMI_REQUEST_C1                    , 27  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 28  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 29  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_30_31                    , 30  , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31 );
+REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_30_31_LEN                , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   , 1   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_EXIT_C0                        , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_EXIT_C1                        , 5   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 7   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 9   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 10  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 11  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_12_15                    , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_12_15_LEN                , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              , 17  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_PURGE                          , 18  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_PURGE_ABORT                    , 19  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED20                        , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED20 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 21  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_PURGE                         , 22  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 23  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_CHTM_PURGE_C0                     , 24  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_CHTM_PURGE_C1                     , 25  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_HMI_REQUEST_C0                    , 26  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_HMI_REQUEST_C1                    , 27  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 28  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 29  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_30_31                    , 30  , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31 );
+REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_30_31_LEN                , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_ENTRY_ACK_C0                   , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_ENTRY_ACK_C1                   , 1   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PM_ENTRY_ACK_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0            , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1            , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_EXIT_C0                        , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_EXIT_C1                        , 5   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PM_EXIT_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0          , 6   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1          , 7   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0           , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1           , 9   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PCBMUX_REQ_C0                     , 10  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PCBMUX_REQ_C1                     , 11  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_12_15                    , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_12_15_LEN                , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0              , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1              , 17  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_SPECIAL_WKUP_DONE_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_PURGE                          , 18  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE   );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_PURGE_ABORT                    , 19  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED20                        , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED20 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                 , 21  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_PURGE                         , 22  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE  );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_PURGE_ABORT                   , 23  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_CHTM_PURGE_C0                     , 24  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_CHTM_PURGE_C1                     , 25  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_HMI_REQUEST_C0                    , 26  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_HMI_REQUEST_C1                    , 27  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PPM_SPARE_OUT_C0                  , 28  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_PPM_SPARE_OUT_C1                  , 29  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_30_31                    , 30  , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31 );
+REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_30_31_LEN                , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_30_31_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_SRTCH0_DATA                            , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME4_CME_SCOM_SRTCH0_DATA_LEN                        , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME3_CME_SCOM_SRTCH0_DATA                            , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME3_CME_SCOM_SRTCH0_DATA_LEN                        , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME11_CME_SCOM_SRTCH0_DATA                           , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME11_CME_SCOM_SRTCH0_DATA_LEN                       , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME2_CME_SCOM_SRTCH0_DATA                            , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME2_CME_SCOM_SRTCH0_DATA_LEN                        , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME5_CME_SCOM_SRTCH0_DATA                            , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME5_CME_SCOM_SRTCH0_DATA_LEN                        , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME9_CME_SCOM_SRTCH0_DATA                            , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME9_CME_SCOM_SRTCH0_DATA_LEN                        , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME6_CME_SCOM_SRTCH0_DATA                            , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME6_CME_SCOM_SRTCH0_DATA_LEN                        , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME10_CME_SCOM_SRTCH0_DATA                           , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME10_CME_SCOM_SRTCH0_DATA_LEN                       , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME8_CME_SCOM_SRTCH0_DATA                            , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME8_CME_SCOM_SRTCH0_DATA_LEN                        , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME1_CME_SCOM_SRTCH0_DATA                            , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME1_CME_SCOM_SRTCH0_DATA_LEN                        , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME0_CME_SCOM_SRTCH0_DATA                            , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME0_CME_SCOM_SRTCH0_DATA_LEN                        , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME7_CME_SCOM_SRTCH0_DATA                            , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME7_CME_SCOM_SRTCH0_DATA_LEN                        , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME4_CME_SCOM_SRTCH1_DATA                            , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME4_CME_SCOM_SRTCH1_DATA_LEN                        , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME3_CME_SCOM_SRTCH1_DATA                            , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME3_CME_SCOM_SRTCH1_DATA_LEN                        , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME11_CME_SCOM_SRTCH1_DATA                           , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME11_CME_SCOM_SRTCH1_DATA_LEN                       , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME2_CME_SCOM_SRTCH1_DATA                            , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME2_CME_SCOM_SRTCH1_DATA_LEN                        , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME5_CME_SCOM_SRTCH1_DATA                            , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME5_CME_SCOM_SRTCH1_DATA_LEN                        , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME9_CME_SCOM_SRTCH1_DATA                            , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME9_CME_SCOM_SRTCH1_DATA_LEN                        , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME6_CME_SCOM_SRTCH1_DATA                            , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME6_CME_SCOM_SRTCH1_DATA_LEN                        , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME10_CME_SCOM_SRTCH1_DATA                           , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME10_CME_SCOM_SRTCH1_DATA_LEN                       , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME8_CME_SCOM_SRTCH1_DATA                            , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME8_CME_SCOM_SRTCH1_DATA_LEN                        , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME1_CME_SCOM_SRTCH1_DATA                            , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME1_CME_SCOM_SRTCH1_DATA_LEN                        , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME0_CME_SCOM_SRTCH1_DATA                            , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME0_CME_SCOM_SRTCH1_DATA_LEN                        , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME7_CME_SCOM_SRTCH1_DATA                            , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_CME7_CME_SCOM_SRTCH1_DATA_LEN                        , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_CME4_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD );
+REG64_FLD( PU_CME4_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD );
+REG64_FLD( PU_CME4_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           , 28  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD );
+REG64_FLD( PU_CME4_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                , 36  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE );
+REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            , 2   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_TIMER_MODE                  , 38  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_TIMER_MODE );
+REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_CHAR_MODE                   , 39  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_CHAR_MODE );
+REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               , 40  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_NOTIFY_ENABLE );
+REG64_FLD( PU_CME4_CME_SCOM_VCCR_SPARE41_43                        , 41  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME4_CME_SCOM_VCCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 , 59  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE );
+REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             , 5   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD );
+REG64_FLD( PU_CME3_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD );
+REG64_FLD( PU_CME3_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           , 28  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD );
+REG64_FLD( PU_CME3_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                , 36  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE );
+REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            , 2   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_TIMER_MODE                  , 38  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_TIMER_MODE );
+REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_CHAR_MODE                   , 39  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_CHAR_MODE );
+REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               , 40  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_NOTIFY_ENABLE );
+REG64_FLD( PU_CME3_CME_SCOM_VCCR_SPARE41_43                        , 41  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME3_CME_SCOM_VCCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 , 59  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE );
+REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             , 5   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD            , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD );
+REG64_FLD( PU_CME11_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN        , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD            , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD );
+REG64_FLD( PU_CME11_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN        , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD          , 28  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD );
+REG64_FLD( PU_CME11_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN      , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_PROFILE_TYPE               , 36  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE );
+REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN           , 2   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_TIMER_MODE                 , 38  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROOP_TIMER_MODE );
+REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_CHAR_MODE                  , 39  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROOP_CHAR_MODE );
+REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE              , 40  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROOP_NOTIFY_ENABLE );
+REG64_FLD( PU_CME11_CME_SCOM_VCCR_SPARE41_43                       , 41  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME11_CME_SCOM_VCCR_SPARE41_43_LEN                   , 3   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                , 59  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE );
+REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN            , 5   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD );
+REG64_FLD( PU_CME2_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD );
+REG64_FLD( PU_CME2_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           , 28  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD );
+REG64_FLD( PU_CME2_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                , 36  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE );
+REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            , 2   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_TIMER_MODE                  , 38  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_TIMER_MODE );
+REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_CHAR_MODE                   , 39  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_CHAR_MODE );
+REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               , 40  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_NOTIFY_ENABLE );
+REG64_FLD( PU_CME2_CME_SCOM_VCCR_SPARE41_43                        , 41  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME2_CME_SCOM_VCCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 , 59  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE );
+REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             , 5   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD );
+REG64_FLD( PU_CME5_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD );
+REG64_FLD( PU_CME5_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           , 28  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD );
+REG64_FLD( PU_CME5_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                , 36  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE );
+REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            , 2   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_TIMER_MODE                  , 38  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_TIMER_MODE );
+REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_CHAR_MODE                   , 39  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_CHAR_MODE );
+REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               , 40  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_NOTIFY_ENABLE );
+REG64_FLD( PU_CME5_CME_SCOM_VCCR_SPARE41_43                        , 41  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME5_CME_SCOM_VCCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 , 59  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE );
+REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             , 5   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD );
+REG64_FLD( PU_CME9_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD );
+REG64_FLD( PU_CME9_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           , 28  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD );
+REG64_FLD( PU_CME9_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                , 36  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE );
+REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            , 2   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_TIMER_MODE                  , 38  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_TIMER_MODE );
+REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_CHAR_MODE                   , 39  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_CHAR_MODE );
+REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               , 40  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_NOTIFY_ENABLE );
+REG64_FLD( PU_CME9_CME_SCOM_VCCR_SPARE41_43                        , 41  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME9_CME_SCOM_VCCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 , 59  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE );
+REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             , 5   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD );
+REG64_FLD( PU_CME6_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD );
+REG64_FLD( PU_CME6_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           , 28  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD );
+REG64_FLD( PU_CME6_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                , 36  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE );
+REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            , 2   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_TIMER_MODE                  , 38  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_TIMER_MODE );
+REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_CHAR_MODE                   , 39  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_CHAR_MODE );
+REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               , 40  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_NOTIFY_ENABLE );
+REG64_FLD( PU_CME6_CME_SCOM_VCCR_SPARE41_43                        , 41  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME6_CME_SCOM_VCCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 , 59  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE );
+REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             , 5   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD            , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD );
+REG64_FLD( PU_CME10_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN        , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD            , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD );
+REG64_FLD( PU_CME10_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN        , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD          , 28  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD );
+REG64_FLD( PU_CME10_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN      , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_PROFILE_TYPE               , 36  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE );
+REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN           , 2   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_TIMER_MODE                 , 38  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROOP_TIMER_MODE );
+REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_CHAR_MODE                  , 39  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROOP_CHAR_MODE );
+REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE              , 40  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROOP_NOTIFY_ENABLE );
+REG64_FLD( PU_CME10_CME_SCOM_VCCR_SPARE41_43                       , 41  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME10_CME_SCOM_VCCR_SPARE41_43_LEN                   , 3   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                , 59  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE );
+REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN            , 5   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD );
+REG64_FLD( PU_CME8_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD );
+REG64_FLD( PU_CME8_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           , 28  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD );
+REG64_FLD( PU_CME8_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                , 36  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE );
+REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            , 2   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_TIMER_MODE                  , 38  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_TIMER_MODE );
+REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_CHAR_MODE                   , 39  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_CHAR_MODE );
+REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               , 40  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_NOTIFY_ENABLE );
+REG64_FLD( PU_CME8_CME_SCOM_VCCR_SPARE41_43                        , 41  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME8_CME_SCOM_VCCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 , 59  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE );
+REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             , 5   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD );
+REG64_FLD( PU_CME1_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD );
+REG64_FLD( PU_CME1_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           , 28  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD );
+REG64_FLD( PU_CME1_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                , 36  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE );
+REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            , 2   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_TIMER_MODE                  , 38  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_TIMER_MODE );
+REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_CHAR_MODE                   , 39  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_CHAR_MODE );
+REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               , 40  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_NOTIFY_ENABLE );
+REG64_FLD( PU_CME1_CME_SCOM_VCCR_SPARE41_43                        , 41  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME1_CME_SCOM_VCCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 , 59  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE );
+REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             , 5   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD );
+REG64_FLD( PU_CME0_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD );
+REG64_FLD( PU_CME0_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           , 28  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD );
+REG64_FLD( PU_CME0_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                , 36  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE );
+REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            , 2   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_TIMER_MODE                  , 38  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_TIMER_MODE );
+REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_CHAR_MODE                   , 39  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_CHAR_MODE );
+REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               , 40  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_NOTIFY_ENABLE );
+REG64_FLD( PU_CME0_CME_SCOM_VCCR_SPARE41_43                        , 41  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME0_CME_SCOM_VCCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 , 59  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE );
+REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             , 5   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD             , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD );
+REG64_FLD( PU_CME7_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN         , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD             , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD );
+REG64_FLD( PU_CME7_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN         , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD           , 28  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD );
+REG64_FLD( PU_CME7_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN       , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                , 36  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE );
+REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN            , 2   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_PROFILE_TYPE_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_TIMER_MODE                  , 38  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_TIMER_MODE );
+REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_CHAR_MODE                   , 39  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_CHAR_MODE );
+REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE               , 40  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_NOTIFY_ENABLE );
+REG64_FLD( PU_CME7_CME_SCOM_VCCR_SPARE41_43                        , 41  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( PU_CME7_CME_SCOM_VCCR_SPARE41_43_LEN                    , 3   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                 , 59  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE );
+REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN             , 5   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_DROOP_SAMPLE_RATE_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR );
+REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               , 40  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR );
+REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               , 40  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR            , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR );
+REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN        , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR              , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN          , 24  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR              , 40  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN          , 24  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR );
+REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               , 40  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR );
+REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               , 40  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR );
+REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               , 40  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR );
+REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               , 40  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR            , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR );
+REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN        , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR              , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN          , 24  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR              , 40  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN          , 24  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR );
+REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               , 40  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR );
+REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               , 40  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR );
+REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               , 40  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR             , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR );
+REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN         , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR               , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR               , 40  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN           , 24  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 20  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 36  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 40  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 44  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 48  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 52  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 20  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 36  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 40  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 44  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 48  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 52  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY      , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN  , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA           , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN       , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA           , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN       , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA           , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN       , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA           , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN       , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA           , 20  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN       , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY       , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN   , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA            , 36  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA            , 40  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA            , 44  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA            , 48  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA            , 52  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 20  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 36  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 40  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 44  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 48  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 52  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 20  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 36  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 40  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 44  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 48  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 52  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 20  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 36  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 40  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 44  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 48  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 52  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 20  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 36  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 40  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 44  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 48  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 52  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY      , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN  , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA           , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN       , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA           , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN       , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA           , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN       , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA           , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN       , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA           , 20  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN       , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY       , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN   , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA            , 36  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA            , 40  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA            , 44  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA            , 48  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA            , 52  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 20  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 36  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 40  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 44  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 48  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 52  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 20  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 36  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 40  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 44  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 48  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 52  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 20  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 36  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 40  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 44  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 48  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 52  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY       , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN   , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA            , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA            , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA            , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA            , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA            , 20  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN        , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY        , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN    , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA             , 36  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA             , 40  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA             , 44  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA             , 48  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA             , 52  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN         , 4   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             , 0   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME4_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME4_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            , 32  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME4_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           , 44  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME4_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       , 12  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           , 56  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME4_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       , 8   , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             , 0   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME3_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME3_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            , 32  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME3_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           , 44  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME3_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       , 12  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           , 56  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME3_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       , 8   , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR            , 0   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME11_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN        , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR          , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME11_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN      , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR           , 32  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME11_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN       , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR          , 44  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME11_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN      , 12  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR          , 56  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME11_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN      , 8   , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             , 0   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME2_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME2_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            , 32  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME2_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           , 44  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME2_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       , 12  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           , 56  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME2_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       , 8   , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             , 0   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME5_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME5_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            , 32  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME5_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           , 44  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME5_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       , 12  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           , 56  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME5_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       , 8   , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             , 0   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME9_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME9_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            , 32  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME9_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           , 44  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME9_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       , 12  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           , 56  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME9_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       , 8   , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             , 0   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME6_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME6_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            , 32  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME6_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           , 44  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME6_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       , 12  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           , 56  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME6_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       , 8   , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR            , 0   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME10_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN        , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR          , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME10_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN      , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR           , 32  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME10_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN       , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR          , 44  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME10_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN      , 12  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR          , 56  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME10_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN      , 8   , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             , 0   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME8_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME8_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            , 32  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME8_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           , 44  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME8_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       , 12  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           , 56  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME8_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       , 8   , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             , 0   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME1_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME1_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            , 32  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME1_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           , 44  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME1_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       , 12  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           , 56  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME1_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       , 8   , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             , 0   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME0_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME0_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            , 32  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME0_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           , 44  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME0_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       , 12  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           , 56  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME0_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       , 8   , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR             , 0   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME7_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN         , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR           , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME7_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN       , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR            , 32  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME7_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN        , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR           , 44  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR );
+REG64_FLD( PU_CME7_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN       , 12  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR           , 56  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR );
+REG64_FLD( PU_CME7_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN       , 8   , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN );
+
+REG64_FLD( PU_CME4_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  , 16  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME4_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              , 24  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME4_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  , 40  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME4_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              , 24  , SH_UNT_PU_CME4  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME3_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  , 16  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME3_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              , 24  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME3_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  , 40  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME3_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              , 24  , SH_UNT_PU_CME3  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME11_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                 , 16  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME11_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN             , 24  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME11_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                 , 40  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME11_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN             , 24  , SH_UNT_PU_CME11 , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME2_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  , 16  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME2_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              , 24  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME2_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  , 40  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME2_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              , 24  , SH_UNT_PU_CME2  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME5_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  , 16  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME5_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              , 24  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME5_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  , 40  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME5_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              , 24  , SH_UNT_PU_CME5  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME9_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  , 16  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME9_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              , 24  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME9_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  , 40  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME9_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              , 24  , SH_UNT_PU_CME9  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME6_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  , 16  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME6_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              , 24  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME6_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  , 40  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME6_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              , 24  , SH_UNT_PU_CME6  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME10_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                 , 16  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME10_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN             , 24  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME10_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                 , 40  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME10_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN             , 24  , SH_UNT_PU_CME10 , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME8_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  , 16  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME8_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              , 24  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME8_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  , 40  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME8_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              , 24  , SH_UNT_PU_CME8  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME1_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  , 16  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME1_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              , 24  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME1_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  , 40  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME1_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              , 24  , SH_UNT_PU_CME1  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME0_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  , 16  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME0_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              , 24  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME0_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  , 40  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME0_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              , 24  , SH_UNT_PU_CME0  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                  , 16  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN              , 24  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                  , 40  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN              , 24  , SH_UNT_PU_CME7  , SH_ACS_PPE      ,
+           SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_WITHSTART               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_REG_BIT_WITHSTART );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_WITHADDR                , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_REG_BIT_WITHADDR );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_READCONT                , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_REG_BIT_READCONT );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_WITHSTOP                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_REG_BIT_WITHSTOP );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_LENGTH                      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_REG_LENGTH );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_LENGTH_LEN                  , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_REG_LENGTH_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_UNUSED_8_14                         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_8_14 );
+REG32_FLD( PU_COMMAND_REGISTER_UNUSED_8_14_LEN                     , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_8_14_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_RNW                     , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_REG_BIT_RNW );
+REG32_FLD( PU_COMMAND_REGISTER_UNUSED_16_22                        , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_16_22 );
+REG32_FLD( PU_COMMAND_REGISTER_UNUSED_16_22_LEN                    , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_16_22_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_REG_ADDR_LENGTH                     , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REG_ADDR_LENGTH );
+REG32_FLD( PU_COMMAND_REGISTER_REG_ADDR_LENGTH_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REG_ADDR_LENGTH_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_UNUSED_26_31                        , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_26_31 );
+REG32_FLD( PU_COMMAND_REGISTER_UNUSED_26_31_LEN                    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_26_31_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_1                      , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_REG_ADDR_1 );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_1_LEN                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_REG_ADDR_1_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_2                      , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_REG_ADDR_2 );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_2_LEN                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_REG_ADDR_2_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_3                      , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_REG_ADDR_3 );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_3_LEN                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_REG_ADDR_3_LEN );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_4                      , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_REG_ADDR_4 );
+REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_4_LEN                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_REG_ADDR_4_LEN );
+
+REG64_FLD( PU_COMMAND_REGISTER_B_WITH_START_0                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WITH_START_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_WITH_ADDRESS_0                    , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WITH_ADDRESS_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_READ_CONTINUE_0                   , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_READ_CONTINUE_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_WITH_STOP_0                       , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WITH_STOP_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_NOT_USED_0                        , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NOT_USED_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_NOT_USED_0_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NOT_USED_0_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_B_DEVICE_ADDRESS_0                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DEVICE_ADDRESS_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_DEVICE_ADDRESS_0_LEN              , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DEVICE_ADDRESS_0_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_B_READ_NOT_WRITE_0                  , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_READ_NOT_WRITE_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_LENGTH_IN_BYTES_0                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LENGTH_IN_BYTES_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_LENGTH_IN_BYTES_0_LEN             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LENGTH_IN_BYTES_0_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_B_PEEK_DATA1_0                      , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_COMMAND_REGISTER_B_PEEK_DATA1_0_LEN                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_B_LBUS_PARITY_ERR1_0                , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_COMMAND_REGISTER_C_WITH_START_1                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WITH_START_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_WITH_ADDRESS_1                    , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WITH_ADDRESS_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_READ_CONTINUE_1                   , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_READ_CONTINUE_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_WITH_STOP_1                       , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WITH_STOP_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_NOT_USED_1                        , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NOT_USED_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_NOT_USED_1_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NOT_USED_1_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_C_DEVICE_ADDRESS_1                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DEVICE_ADDRESS_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_DEVICE_ADDRESS_1_LEN              , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DEVICE_ADDRESS_1_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_C_READ_NOT_WRITE_1                  , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_READ_NOT_WRITE_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_LENGTH_IN_BYTES_1                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LENGTH_IN_BYTES_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_LENGTH_IN_BYTES_1_LEN             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LENGTH_IN_BYTES_1_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_C_PEEK_DATA1_1                      , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_COMMAND_REGISTER_C_PEEK_DATA1_1_LEN                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_C_LBUS_PARITY_ERR1_1                , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_COMMAND_REGISTER_D_WITH_START_2                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WITH_START_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_WITH_ADDRESS_2                    , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WITH_ADDRESS_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_READ_CONTINUE_2                   , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_READ_CONTINUE_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_WITH_STOP_2                       , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WITH_STOP_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_NOT_USED_2                        , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NOT_USED_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_NOT_USED_2_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NOT_USED_2_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_D_DEVICE_ADDRESS_2                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DEVICE_ADDRESS_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_DEVICE_ADDRESS_2_LEN              , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DEVICE_ADDRESS_2_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_D_READ_NOT_WRITE_2                  , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_READ_NOT_WRITE_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_LENGTH_IN_BYTES_2                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LENGTH_IN_BYTES_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_LENGTH_IN_BYTES_2_LEN             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LENGTH_IN_BYTES_2_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_D_PEEK_DATA1_2                      , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_COMMAND_REGISTER_D_PEEK_DATA1_2_LEN                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_D_LBUS_PARITY_ERR1_2                , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_COMMAND_REGISTER_E_WITH_START_3                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WITH_START_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_WITH_ADDRESS_3                    , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WITH_ADDRESS_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_READ_CONTINUE_3                   , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_READ_CONTINUE_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_WITH_STOP_3                       , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WITH_STOP_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_NOT_USED_3                        , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NOT_USED_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_NOT_USED_3_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NOT_USED_3_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_E_DEVICE_ADDRESS_3                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DEVICE_ADDRESS_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_DEVICE_ADDRESS_3_LEN              , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DEVICE_ADDRESS_3_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_E_READ_NOT_WRITE_3                  , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_READ_NOT_WRITE_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_LENGTH_IN_BYTES_3                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LENGTH_IN_BYTES_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_LENGTH_IN_BYTES_3_LEN             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LENGTH_IN_BYTES_3_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_E_PEEK_DATA1_3                      , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_COMMAND_REGISTER_E_PEEK_DATA1_3_LEN                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_COMMAND_REGISTER_E_LBUS_PARITY_ERR1_3                , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG1_RESERVED1                   , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_G                    , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_LN                   , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_SKIP_G                       , 9   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG1_RESERVED2                   , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RESERVED4                    , 22  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MACH_CORRENAB                , 23  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_REQ0               , 41  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ0 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_PRB0               , 42  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB0 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_REQ1               , 43  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ1 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_PRB1               , 44  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB1 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_XATS               , 45  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_XATS );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_INJECT               , 46  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_INJECT );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DCACHE_MODE                  , 47  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_MODE );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      , 48  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   , 49  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB                 , 50  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PCKT_BLK_PRB );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_P9P9_MODE                    , 51  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_P9P9_MODE );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       , 52  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           , 53  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_ATOMIC );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_OPT_SNOOP_CP                 , 54  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_OPT_SNOOP_CP );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3                           , 55  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3_LEN                       , 9   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG1_RESERVED1                   , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DISABLE_G                    , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DISABLE_LN                   , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_SKIP_G                       , 9   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG1_RESERVED2                   , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RESERVED4                    , 22  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MACH_CORRENAB                , 23  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_PREALLOC2_REQ0               , 41  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ0 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_PREALLOC2_PRB0               , 42  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB0 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_PREALLOC2_REQ1               , 43  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ1 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_PREALLOC2_PRB1               , 44  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB1 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_PREALLOC2_XATS               , 45  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_XATS );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DISABLE_INJECT               , 46  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_INJECT );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DCACHE_MODE                  , 47  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_MODE );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      , 48  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   , 49  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_PCKT_BLK_PRB                 , 50  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PCKT_BLK_PRB );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_P9P9_MODE                    , 51  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_P9P9_MODE );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       , 52  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           , 53  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_ATOMIC );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_OPT_SNOOP_CP                 , 54  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_OPT_SNOOP_CP );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3                           , 55  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3_LEN                       , 9   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG1_RESERVED1                   , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_G                    , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_LN                   , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_SKIP_G                       , 9   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG1_RESERVED2                   , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RESERVED4                    , 22  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MACH_CORRENAB                , 23  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_REQ0               , 41  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ0 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_PRB0               , 42  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB0 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_REQ1               , 43  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ1 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_PRB1               , 44  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB1 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_XATS               , 45  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_XATS );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_INJECT               , 46  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_INJECT );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DCACHE_MODE                  , 47  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_MODE );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      , 48  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   , 49  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB                 , 50  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PCKT_BLK_PRB );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_P9P9_MODE                    , 51  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_P9P9_MODE );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       , 52  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           , 53  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_ATOMIC );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_OPT_SNOOP_CP                 , 54  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_OPT_SNOOP_CP );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3                           , 55  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3_LEN                       , 9   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG1_RESERVED1                   , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DISABLE_G                    , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DISABLE_LN                   , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_SKIP_G                       , 9   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG1_RESERVED2                   , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RESERVED4                    , 22  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MACH_CORRENAB                , 23  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_PREALLOC2_REQ0               , 41  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ0 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_PREALLOC2_PRB0               , 42  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB0 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_PREALLOC2_REQ1               , 43  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ1 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_PREALLOC2_PRB1               , 44  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB1 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_PREALLOC2_XATS               , 45  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_XATS );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DISABLE_INJECT               , 46  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_INJECT );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DCACHE_MODE                  , 47  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_MODE );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      , 48  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   , 49  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB                 , 50  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PCKT_BLK_PRB );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_P9P9_MODE                    , 51  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_P9P9_MODE );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       , 52  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           , 53  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_ATOMIC );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_OPT_SNOOP_CP                 , 54  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_OPT_SNOOP_CP );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3                           , 55  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3_LEN                       , 9   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG1_RESERVED1                   , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_G                    , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_LN                   , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_SKIP_G                       , 9   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG1_RESERVED2                   , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RESERVED4                    , 22  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MACH_CORRENAB                , 23  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_REQ0               , 41  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ0 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_PRB0               , 42  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB0 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_REQ1               , 43  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ1 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_PRB1               , 44  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB1 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_XATS               , 45  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_XATS );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_INJECT               , 46  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_INJECT );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DCACHE_MODE                  , 47  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_MODE );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      , 48  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   , 49  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB                 , 50  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PCKT_BLK_PRB );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_P9P9_MODE                    , 51  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_P9P9_MODE );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       , 52  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           , 53  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_ATOMIC );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_OPT_SNOOP_CP                 , 54  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_OPT_SNOOP_CP );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3                           , 55  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3_LEN                       , 9   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG1_RESERVED1                   , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DISABLE_G                    , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DISABLE_LN                   , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_SKIP_G                       , 9   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG1_RESERVED2                   , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RESERVED4                    , 22  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MACH_CORRENAB                , 23  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_PREALLOC2_REQ0               , 41  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ0 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_PREALLOC2_PRB0               , 42  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB0 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_PREALLOC2_REQ1               , 43  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ1 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_PREALLOC2_PRB1               , 44  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB1 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_PREALLOC2_XATS               , 45  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_XATS );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DISABLE_INJECT               , 46  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_INJECT );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DCACHE_MODE                  , 47  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_MODE );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      , 48  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   , 49  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB                 , 50  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PCKT_BLK_PRB );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_P9P9_MODE                    , 51  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_P9P9_MODE );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       , 52  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           , 53  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_ATOMIC );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_OPT_SNOOP_CP                 , 54  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_OPT_SNOOP_CP );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3                           , 55  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3_LEN                       , 9   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG1_RESERVED1                   , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DISABLE_G                    , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DISABLE_LN                   , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_SKIP_G                       , 9   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG1_RESERVED2                   , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RESERVED4                    , 22  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MACH_CORRENAB                , 23  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_PREALLOC2_REQ0               , 41  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ0 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_PREALLOC2_PRB0               , 42  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB0 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_PREALLOC2_REQ1               , 43  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ1 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_PREALLOC2_PRB1               , 44  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB1 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_PREALLOC2_XATS               , 45  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_XATS );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DISABLE_INJECT               , 46  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_INJECT );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DCACHE_MODE                  , 47  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_MODE );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      , 48  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   , 49  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_PCKT_BLK_PRB                 , 50  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PCKT_BLK_PRB );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_P9P9_MODE                    , 51  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_P9P9_MODE );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       , 52  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           , 53  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_ATOMIC );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_OPT_SNOOP_CP                 , 54  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_OPT_SNOOP_CP );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3                           , 55  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3_LEN                       , 9   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED0                   , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED0 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED1                   , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED1_LEN               , 3   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY               , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GEN_HEAD_DELAY );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY_LEN           , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GEN_HEAD_DELAY_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_DIV2_COUNT_AT_EXP      , 10  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_DIV2_COUNT_AT_EXP );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_DIV2_COUNT_AT_EXP      , 11  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_DIV2_COUNT_AT_EXP );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_ADJ            , 12  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_DIS_DYN_ADJ );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_ADJ            , 13  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_DIS_DYN_ADJ );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_LVL_ADJ        , 14  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_DIS_DYN_LVL_ADJ );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_LVL_ADJ        , 15  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_DIS_DYN_LVL_ADJ );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_THRESH1                , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_THRESH1 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_THRESH1_LEN            , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_THRESH1_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_THRESH2                , 22  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_THRESH2 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_THRESH2_LEN            , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_THRESH2_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_THRESH1                , 28  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_THRESH1 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_THRESH1_LEN            , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_THRESH1_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_THRESH2                , 34  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_THRESH2 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_THRESH2_LEN            , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_THRESH2_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL              , 40  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_MAX_LEVEL );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL_LEN          , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_MAX_LEVEL_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL              , 44  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_MAX_LEVEL );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN          , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_BRAZOS_MODE                  , 48  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR          , 49  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_PBM_ECC_COR );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_01          , 50  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_LAB_RANDOMIZE_PE_01 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_23          , 51  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_LAB_RANDOMIZE_PE_23 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED2                   , 52  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED2_LEN               , 12  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG1_RESERVED1                   , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_G                    , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_LN                   , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_SKIP_G                       , 9   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG1_RESERVED2                   , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RESERVED4                    , 22  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MACH_CORRENAB                , 23  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_REQ0               , 41  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ0 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_PRB0               , 42  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB0 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_REQ1               , 43  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ1 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_PRB1               , 44  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB1 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_XATS               , 45  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_XATS );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_INJECT               , 46  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_INJECT );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DCACHE_MODE                  , 47  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_MODE );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      , 48  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   , 49  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB                 , 50  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PCKT_BLK_PRB );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_P9P9_MODE                    , 51  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_P9P9_MODE );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       , 52  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           , 53  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_ATOMIC );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_OPT_SNOOP_CP                 , 54  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_OPT_SNOOP_CP );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3                           , 55  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3_LEN                       , 9   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG1_RESERVED1                   , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DISABLE_G                    , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DISABLE_LN                   , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_SKIP_G                       , 9   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG1_RESERVED2                   , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RESERVED4                    , 22  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MACH_CORRENAB                , 23  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_PREALLOC2_REQ0               , 41  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ0 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_PREALLOC2_PRB0               , 42  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB0 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_PREALLOC2_REQ1               , 43  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ1 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_PREALLOC2_PRB1               , 44  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB1 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_PREALLOC2_XATS               , 45  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_XATS );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DISABLE_INJECT               , 46  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_INJECT );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DCACHE_MODE                  , 47  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_MODE );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      , 48  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   , 49  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_PCKT_BLK_PRB                 , 50  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PCKT_BLK_PRB );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_P9P9_MODE                    , 51  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_P9P9_MODE );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       , 52  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           , 53  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_ATOMIC );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_OPT_SNOOP_CP                 , 54  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_OPT_SNOOP_CP );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3                           , 55  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3_LEN                       , 9   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG1_RESERVED1                   , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_G                    , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_LN                   , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_SKIP_G                       , 9   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG1_RESERVED2                   , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RESERVED4                    , 22  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MACH_CORRENAB                , 23  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_REQ0               , 41  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ0 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_PRB0               , 42  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB0 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_REQ1               , 43  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ1 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_PRB1               , 44  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB1 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_XATS               , 45  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_XATS );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_INJECT               , 46  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_INJECT );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DCACHE_MODE                  , 47  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_MODE );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      , 48  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   , 49  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB                 , 50  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PCKT_BLK_PRB );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_P9P9_MODE                    , 51  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_P9P9_MODE );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       , 52  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           , 53  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_ATOMIC );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_OPT_SNOOP_CP                 , 54  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_OPT_SNOOP_CP );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3                           , 55  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3_LEN                       , 9   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED0                   , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED0 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED1                   , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED1_LEN               , 3   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY               , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GEN_HEAD_DELAY );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY_LEN           , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GEN_HEAD_DELAY_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_DIV2_COUNT_AT_EXP      , 10  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_DIV2_COUNT_AT_EXP );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_DIV2_COUNT_AT_EXP      , 11  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_DIV2_COUNT_AT_EXP );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_ADJ            , 12  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_DIS_DYN_ADJ );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_ADJ            , 13  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_DIS_DYN_ADJ );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_LVL_ADJ        , 14  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_DIS_DYN_LVL_ADJ );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_LVL_ADJ        , 15  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_DIS_DYN_LVL_ADJ );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_THRESH1                , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_THRESH1 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_THRESH1_LEN            , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_THRESH1_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_THRESH2                , 22  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_THRESH2 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_THRESH2_LEN            , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_THRESH2_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_THRESH1                , 28  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_THRESH1 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_THRESH1_LEN            , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_THRESH1_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_THRESH2                , 34  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_THRESH2 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_THRESH2_LEN            , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_THRESH2_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL              , 40  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_MAX_LEVEL );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL_LEN          , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_MAX_LEVEL_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL              , 44  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_MAX_LEVEL );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN          , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_BRAZOS_MODE                  , 48  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR          , 49  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_PBM_ECC_COR );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_01          , 50  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_LAB_RANDOMIZE_PE_01 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_23          , 51  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_LAB_RANDOMIZE_PE_23 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED2                   , 52  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED2_LEN               , 12  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED0                   , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED0 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED1                   , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED1_LEN               , 3   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY               , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GEN_HEAD_DELAY );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY_LEN           , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GEN_HEAD_DELAY_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_DIV2_COUNT_AT_EXP      , 10  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_DIV2_COUNT_AT_EXP );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_DIV2_COUNT_AT_EXP      , 11  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_DIV2_COUNT_AT_EXP );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_ADJ            , 12  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_DIS_DYN_ADJ );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_ADJ            , 13  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_DIS_DYN_ADJ );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_LVL_ADJ        , 14  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_DIS_DYN_LVL_ADJ );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_LVL_ADJ        , 15  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_DIS_DYN_LVL_ADJ );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_THRESH1                , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_THRESH1 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_THRESH1_LEN            , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_THRESH1_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_THRESH2                , 22  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_THRESH2 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_THRESH2_LEN            , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_THRESH2_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_THRESH1                , 28  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_THRESH1 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_THRESH1_LEN            , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_THRESH1_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_THRESH2                , 34  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_THRESH2 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_THRESH2_LEN            , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_THRESH2_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL              , 40  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_MAX_LEVEL );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL_LEN          , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_MAX_LEVEL_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL              , 44  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_MAX_LEVEL );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN          , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_BRAZOS_MODE                  , 48  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR          , 49  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_PBM_ECC_COR );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_01          , 50  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_LAB_RANDOMIZE_PE_01 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_23          , 51  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_LAB_RANDOMIZE_PE_23 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED2                   , 52  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED2_LEN               , 12  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG1_RESERVED1                   , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_G                    , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_LN                   , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_SKIP_G                       , 9   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG1_RESERVED2                   , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RESERVED4                    , 22  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MACH_CORRENAB                , 23  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_REQ0               , 41  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ0 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_PRB0               , 42  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB0 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_REQ1               , 43  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ1 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_PRB1               , 44  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB1 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_XATS               , 45  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_XATS );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_INJECT               , 46  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_INJECT );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DCACHE_MODE                  , 47  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_MODE );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      , 48  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   , 49  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB                 , 50  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PCKT_BLK_PRB );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_P9P9_MODE                    , 51  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_P9P9_MODE );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       , 52  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           , 53  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_ATOMIC );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_OPT_SNOOP_CP                 , 54  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_OPT_SNOOP_CP );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3                           , 55  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3_LEN                       , 9   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG1_RESERVED1                   , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED1 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR          , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR          , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE           , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_ADR_BAR_MODE                 , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADR_BAR_MODE );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DISABLE_NN_RN                , 5   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_NN_RN );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS           , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DISABLE_G                    , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_G );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DISABLE_LN                   , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_LN );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_SKIP_G                       , 9   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SKIP_G );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP            , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_WRP );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ        , 11  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA        , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_INC_PRI_MASK                 , 13  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_INC_PRI_MASK_LEN             , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_INC_PRI_MASK_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG1_RESERVED2                   , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG1_RESERVED2 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_B              , 17  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_B );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_C              , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_C );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_A              , 19  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_A );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_B              , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_B );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_C              , 21  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_SCRESP_OPT_C );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RESERVED4                    , 22  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RESERVED4 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MACH_CORRENAB                , 23  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_CORRENAB );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE1          , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE2          , 25  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MACH_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RXO_CORRENAB                 , 26  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_CORRENAB );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE1           , 27  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE2           , 28  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RXO_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RSI_CORRENAB                 , 29  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_CORRENAB );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE1           , 30  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE1 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE2           , 31  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_INJECT_ENABLE2 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM         , 32  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN     , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG           , 34  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_EVAPORATE_BY_LCO             , 35  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EVAPORATE_BY_LCO );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MRBGP_TRACK_ALL              , 36  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBGP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MRBSP_TRACK_ALL              , 37  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MRBSP_TRACK_ALL );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_ENABLE_PBUS                  , 38  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_PBUS );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_BRAZOS_MODE                  , 39  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_BRAZOS_MODE );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_ENABLE_SNARF_CPM             , 40  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_SNARF_CPM );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_PREALLOC2_REQ0               , 41  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ0 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_PREALLOC2_PRB0               , 42  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB0 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_PREALLOC2_REQ1               , 43  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_REQ1 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_PREALLOC2_PRB1               , 44  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_PRB1 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_PREALLOC2_XATS               , 45  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PREALLOC2_XATS );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DISABLE_INJECT               , 46  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DISABLE_INJECT );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DCACHE_MODE                  , 47  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_MODE );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL      , 48  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH   , 49  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB                 , 50  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PCKT_BLK_PRB );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_P9P9_MODE                    , 51  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_P9P9_MODE );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32       , 52  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC           , 53  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_FORBID_MMIO_ATOMIC );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_OPT_SNOOP_CP                 , 54  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_OPT_SNOOP_CP );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3                           , 55  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3_LEN                       , 9   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT            , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          , 28  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          , 32  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_RESERVED                            , 36  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_SM2_CONFIG1_RESERVED_LEN                        , 28  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT            , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          , 28  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          , 32  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_RESERVED                            , 36  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_SM3_CONFIG1_RESERVED_LEN                        , 28  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_COMPRESSED_RSP_ENA                 , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_COMPRESSED_RSP_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED1                          , 1   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED1_LEN                      , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_CREQ_AE_ALWAYS                     , 4   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_CREQ_AE_ALWAYS );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_DGD_AE_ALWAYS                      , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_DGD_AE_ALWAYS );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_RSP_AE_ALWAYS                      , 6   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RSP_AE_ALWAYS );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED2                          , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_NTL_RESET                          , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_RESET  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_NTL_RESET_LEN                      , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NTL_RESET_LEN );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED3                          , 10  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED3_LEN                      , 54  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT            , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          , 28  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          , 32  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_RESERVED                            , 36  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_SM1_CONFIG1_RESERVED_LEN                        , 28  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT            , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          , 28  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          , 32  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_RESERVED                            , 36  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_SM2_CONFIG1_RESERVED_LEN                        , 28  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU0_CTL_CONFIG1_IDIAL                               , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_CTL_CONFIG1_IDIAL_LEN                           , 64  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_CONFIG1_MGR_CREDIT                              , 0   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MGR_CREDIT );
+REG64_FLD( PU_NPU1_CONFIG1_MGR_CREDIT_LEN                          , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MGR_CREDIT_LEN );
+REG64_FLD( PU_NPU1_CONFIG1_MRG_PBTX_NBUF                           , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_PBTX_NBUF );
+REG64_FLD( PU_NPU1_CONFIG1_MRG_PBTX_NBUF_LEN                       , 3   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_PBTX_NBUF_LEN );
+REG64_FLD( PU_NPU1_CONFIG1_MRG_RDBF_NBUF                           , 5   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_RDBF_NBUF );
+REG64_FLD( PU_NPU1_CONFIG1_MRG_RDBF_NBUF_LEN                       , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_RDBF_NBUF_LEN );
+REG64_FLD( PU_NPU1_CONFIG1_MRG_IBWR_NBUF                           , 9   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_IBWR_NBUF );
+REG64_FLD( PU_NPU1_CONFIG1_MRG_IBWR_NBUF_LEN                       , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_IBWR_NBUF_LEN );
+REG64_FLD( PU_NPU1_CONFIG1_MRG_IBRD_NBUF                           , 13  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_IBRD_NBUF );
+REG64_FLD( PU_NPU1_CONFIG1_MRG_IBRD_NBUF_LEN                       , 3   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_IBRD_NBUF_LEN );
+REG64_FLD( PU_NPU1_CONFIG1_MRG_BBRD_NBUF                           , 16  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_BBRD_NBUF );
+REG64_FLD( PU_NPU1_CONFIG1_MRG_BBRD_NBUF_LEN                       , 3   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_BBRD_NBUF_LEN );
+REG64_FLD( PU_NPU1_CONFIG1_MRG_OBRD_NBUF                           , 19  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_OBRD_NBUF );
+REG64_FLD( PU_NPU1_CONFIG1_MRG_OBRD_NBUF_LEN                       , 3   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_OBRD_NBUF_LEN );
+REG64_FLD( PU_NPU1_CONFIG1_MRG_CR_DIS                              , 22  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_CR_DIS );
+REG64_FLD( PU_NPU1_CONFIG1_MRG_CTLW_CR_DIS                         , 23  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_CTLW_CR_DIS );
+REG64_FLD( PU_NPU1_CONFIG1_NTLR_PAUSE_THRESH                       , 24  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_NTLR_PAUSE_THRESH );
+REG64_FLD( PU_NPU1_CONFIG1_NTLR_PAUSE_THRESH_LEN                   , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_NTLR_PAUSE_THRESH_LEN );
+REG64_FLD( PU_NPU1_CONFIG1_CTLR_HP_THRESH                          , 26  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_CTLR_HP_THRESH );
+REG64_FLD( PU_NPU1_CONFIG1_CTLR_HP_THRESH_LEN                      , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_CTLR_HP_THRESH_LEN );
+REG64_FLD( PU_NPU1_CONFIG1_NTLW_PAUSE_THRESH                       , 28  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_NTLW_PAUSE_THRESH );
+REG64_FLD( PU_NPU1_CONFIG1_NTLW_PAUSE_THRESH_LEN                   , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_NTLW_PAUSE_THRESH_LEN );
+REG64_FLD( PU_NPU1_CONFIG1_CTLW_HP_THRESH                          , 30  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_CTLW_HP_THRESH );
+REG64_FLD( PU_NPU1_CONFIG1_CTLW_HP_THRESH_LEN                      , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_CTLW_HP_THRESH_LEN );
+REG64_FLD( PU_NPU1_CONFIG1_PBTX_REDUCE_RTAG                        , 32  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_REDUCE_RTAG );
+REG64_FLD( PU_NPU1_CONFIG1_PBTX_DELAY_BDONE                        , 33  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_DELAY_BDONE );
+REG64_FLD( PU_NPU1_CONFIG1_PBTX_FLIP_IMIN_BIG                      , 34  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_FLIP_IMIN_BIG );
+REG64_FLD( PU_NPU1_CONFIG1_PBTX_FLIP_IMIN_LITTLE                   , 35  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_FLIP_IMIN_LITTLE );
+REG64_FLD( PU_NPU1_CONFIG1_ALU_SAFE_LATENCY                        , 36  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_SAFE_LATENCY );
+REG64_FLD( PU_NPU1_CONFIG1_ALU_FLIP_ENDIAN_BIG                     , 37  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_FLIP_ENDIAN_BIG );
+REG64_FLD( PU_NPU1_CONFIG1_ALU_FLIP_ENDIAN_LITTLE                  , 38  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_FLIP_ENDIAN_LITTLE );
+REG64_FLD( PU_NPU1_CONFIG1_PBTX_EARLY_AFTAG                        , 39  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_EARLY_AFTAG );
+REG64_FLD( PU_NPU1_CONFIG1_RESERVED1                               , 40  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_CONFIG1_RESERVED1_LEN                           , 24  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT            , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          , 28  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          , 32  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_RESERVED                            , 36  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_SM1_CONFIG1_RESERVED_LEN                        , 28  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT            , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          , 28  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          , 32  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_RESERVED                            , 36  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_SM0_CONFIG1_RESERVED_LEN                        , 28  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_COMPRESSED_RSP_ENA                 , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_COMPRESSED_RSP_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED1                          , 1   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED1_LEN                      , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_CREQ_AE_ALWAYS                     , 4   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_CREQ_AE_ALWAYS );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_DGD_AE_ALWAYS                      , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DGD_AE_ALWAYS );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_RSP_AE_ALWAYS                      , 6   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RSP_AE_ALWAYS );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED2                          , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_NTL_RESET                          , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_RESET  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_NTL_RESET_LEN                      , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NTL_RESET_LEN );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED3                          , 10  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED3_LEN                      , 54  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT            , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          , 28  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          , 32  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_RESERVED                            , 36  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_SM3_CONFIG1_RESERVED_LEN                        , 28  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT            , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          , 28  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          , 32  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_RESERVED                            , 36  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_SM3_CONFIG1_RESERVED_LEN                        , 28  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT            , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          , 28  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          , 32  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_RESERVED                            , 36  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_SM2_CONFIG1_RESERVED_LEN                        , 28  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU0_CONFIG1_MGR_CREDIT                              , 0   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MGR_CREDIT );
+REG64_FLD( PU_NPU0_CONFIG1_MGR_CREDIT_LEN                          , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MGR_CREDIT_LEN );
+REG64_FLD( PU_NPU0_CONFIG1_MRG_PBTX_NBUF                           , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_PBTX_NBUF );
+REG64_FLD( PU_NPU0_CONFIG1_MRG_PBTX_NBUF_LEN                       , 3   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_PBTX_NBUF_LEN );
+REG64_FLD( PU_NPU0_CONFIG1_MRG_RDBF_NBUF                           , 5   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_RDBF_NBUF );
+REG64_FLD( PU_NPU0_CONFIG1_MRG_RDBF_NBUF_LEN                       , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_RDBF_NBUF_LEN );
+REG64_FLD( PU_NPU0_CONFIG1_MRG_IBWR_NBUF                           , 9   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_IBWR_NBUF );
+REG64_FLD( PU_NPU0_CONFIG1_MRG_IBWR_NBUF_LEN                       , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_IBWR_NBUF_LEN );
+REG64_FLD( PU_NPU0_CONFIG1_MRG_IBRD_NBUF                           , 13  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_IBRD_NBUF );
+REG64_FLD( PU_NPU0_CONFIG1_MRG_IBRD_NBUF_LEN                       , 3   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_IBRD_NBUF_LEN );
+REG64_FLD( PU_NPU0_CONFIG1_MRG_BBRD_NBUF                           , 16  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_BBRD_NBUF );
+REG64_FLD( PU_NPU0_CONFIG1_MRG_BBRD_NBUF_LEN                       , 3   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_BBRD_NBUF_LEN );
+REG64_FLD( PU_NPU0_CONFIG1_MRG_OBRD_NBUF                           , 19  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_OBRD_NBUF );
+REG64_FLD( PU_NPU0_CONFIG1_MRG_OBRD_NBUF_LEN                       , 3   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_OBRD_NBUF_LEN );
+REG64_FLD( PU_NPU0_CONFIG1_MRG_CR_DIS                              , 22  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_CR_DIS );
+REG64_FLD( PU_NPU0_CONFIG1_MRG_CTLW_CR_DIS                         , 23  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_CTLW_CR_DIS );
+REG64_FLD( PU_NPU0_CONFIG1_NTLR_PAUSE_THRESH                       , 24  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_NTLR_PAUSE_THRESH );
+REG64_FLD( PU_NPU0_CONFIG1_NTLR_PAUSE_THRESH_LEN                   , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_NTLR_PAUSE_THRESH_LEN );
+REG64_FLD( PU_NPU0_CONFIG1_CTLR_HP_THRESH                          , 26  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_CTLR_HP_THRESH );
+REG64_FLD( PU_NPU0_CONFIG1_CTLR_HP_THRESH_LEN                      , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_CTLR_HP_THRESH_LEN );
+REG64_FLD( PU_NPU0_CONFIG1_NTLW_PAUSE_THRESH                       , 28  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_NTLW_PAUSE_THRESH );
+REG64_FLD( PU_NPU0_CONFIG1_NTLW_PAUSE_THRESH_LEN                   , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_NTLW_PAUSE_THRESH_LEN );
+REG64_FLD( PU_NPU0_CONFIG1_CTLW_HP_THRESH                          , 30  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_CTLW_HP_THRESH );
+REG64_FLD( PU_NPU0_CONFIG1_CTLW_HP_THRESH_LEN                      , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_CTLW_HP_THRESH_LEN );
+REG64_FLD( PU_NPU0_CONFIG1_PBTX_REDUCE_RTAG                        , 32  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_REDUCE_RTAG );
+REG64_FLD( PU_NPU0_CONFIG1_PBTX_DELAY_BDONE                        , 33  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_DELAY_BDONE );
+REG64_FLD( PU_NPU0_CONFIG1_PBTX_FLIP_IMIN_BIG                      , 34  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_FLIP_IMIN_BIG );
+REG64_FLD( PU_NPU0_CONFIG1_PBTX_FLIP_IMIN_LITTLE                   , 35  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_FLIP_IMIN_LITTLE );
+REG64_FLD( PU_NPU0_CONFIG1_ALU_SAFE_LATENCY                        , 36  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_SAFE_LATENCY );
+REG64_FLD( PU_NPU0_CONFIG1_ALU_FLIP_ENDIAN_BIG                     , 37  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_FLIP_ENDIAN_BIG );
+REG64_FLD( PU_NPU0_CONFIG1_ALU_FLIP_ENDIAN_LITTLE                  , 38  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_FLIP_ENDIAN_LITTLE );
+REG64_FLD( PU_NPU0_CONFIG1_PBTX_EARLY_AFTAG                        , 39  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_EARLY_AFTAG );
+REG64_FLD( PU_NPU0_CONFIG1_RESERVED1                               , 40  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_CONFIG1_RESERVED1_LEN                           , 24  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_CTL_CONFIG1_IDIAL                               , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_CTL_CONFIG1_IDIAL_LEN                           , 64  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT            , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          , 28  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          , 32  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_RESERVED                            , 36  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_SM1_CONFIG1_RESERVED_LEN                        , 28  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT            , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          , 28  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          , 32  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_RESERVED                            , 36  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_SM0_CONFIG1_RESERVED_LEN                        , 28  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU2_CTL_CONFIG1_IDIAL                               , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_CTL_CONFIG1_IDIAL_LEN                           , 64  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( NV_CONFIG1_COMPRESSED_RSP_ENA                           , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_COMPRESSED_RSP_ENA );
+REG64_FLD( NV_CONFIG1_RESERVED1                                    , 1   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( NV_CONFIG1_RESERVED1_LEN                                , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( NV_CONFIG1_CREQ_AE_ALWAYS                               , 4   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_CREQ_AE_ALWAYS );
+REG64_FLD( NV_CONFIG1_DGD_AE_ALWAYS                                , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_DGD_AE_ALWAYS );
+REG64_FLD( NV_CONFIG1_RSP_AE_ALWAYS                                , 6   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RSP_AE_ALWAYS );
+REG64_FLD( NV_CONFIG1_RESERVED2                                    , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( NV_CONFIG1_NTL_RESET                                    , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_RESET  );
+REG64_FLD( NV_CONFIG1_NTL_RESET_LEN                                , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NTL_RESET_LEN );
+REG64_FLD( NV_CONFIG1_RESERVED3                                    , 10  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( NV_CONFIG1_RESERVED3_LEN                                , 54  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU2_CONFIG1_MGR_CREDIT                              , 0   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MGR_CREDIT );
+REG64_FLD( PU_NPU2_CONFIG1_MGR_CREDIT_LEN                          , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MGR_CREDIT_LEN );
+REG64_FLD( PU_NPU2_CONFIG1_MRG_PBTX_NBUF                           , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_PBTX_NBUF );
+REG64_FLD( PU_NPU2_CONFIG1_MRG_PBTX_NBUF_LEN                       , 3   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_PBTX_NBUF_LEN );
+REG64_FLD( PU_NPU2_CONFIG1_MRG_RDBF_NBUF                           , 5   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_RDBF_NBUF );
+REG64_FLD( PU_NPU2_CONFIG1_MRG_RDBF_NBUF_LEN                       , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_RDBF_NBUF_LEN );
+REG64_FLD( PU_NPU2_CONFIG1_MRG_IBWR_NBUF                           , 9   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_IBWR_NBUF );
+REG64_FLD( PU_NPU2_CONFIG1_MRG_IBWR_NBUF_LEN                       , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_IBWR_NBUF_LEN );
+REG64_FLD( PU_NPU2_CONFIG1_MRG_IBRD_NBUF                           , 13  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_IBRD_NBUF );
+REG64_FLD( PU_NPU2_CONFIG1_MRG_IBRD_NBUF_LEN                       , 3   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_IBRD_NBUF_LEN );
+REG64_FLD( PU_NPU2_CONFIG1_MRG_BBRD_NBUF                           , 16  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_BBRD_NBUF );
+REG64_FLD( PU_NPU2_CONFIG1_MRG_BBRD_NBUF_LEN                       , 3   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_BBRD_NBUF_LEN );
+REG64_FLD( PU_NPU2_CONFIG1_MRG_OBRD_NBUF                           , 19  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_OBRD_NBUF );
+REG64_FLD( PU_NPU2_CONFIG1_MRG_OBRD_NBUF_LEN                       , 3   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_OBRD_NBUF_LEN );
+REG64_FLD( PU_NPU2_CONFIG1_MRG_CR_DIS                              , 22  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_CR_DIS );
+REG64_FLD( PU_NPU2_CONFIG1_MRG_CTLW_CR_DIS                         , 23  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_MRG_CTLW_CR_DIS );
+REG64_FLD( PU_NPU2_CONFIG1_NTLR_PAUSE_THRESH                       , 24  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_NTLR_PAUSE_THRESH );
+REG64_FLD( PU_NPU2_CONFIG1_NTLR_PAUSE_THRESH_LEN                   , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_NTLR_PAUSE_THRESH_LEN );
+REG64_FLD( PU_NPU2_CONFIG1_CTLR_HP_THRESH                          , 26  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_CTLR_HP_THRESH );
+REG64_FLD( PU_NPU2_CONFIG1_CTLR_HP_THRESH_LEN                      , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_CTLR_HP_THRESH_LEN );
+REG64_FLD( PU_NPU2_CONFIG1_NTLW_PAUSE_THRESH                       , 28  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_NTLW_PAUSE_THRESH );
+REG64_FLD( PU_NPU2_CONFIG1_NTLW_PAUSE_THRESH_LEN                   , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_NTLW_PAUSE_THRESH_LEN );
+REG64_FLD( PU_NPU2_CONFIG1_CTLW_HP_THRESH                          , 30  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_CTLW_HP_THRESH );
+REG64_FLD( PU_NPU2_CONFIG1_CTLW_HP_THRESH_LEN                      , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_CTLW_HP_THRESH_LEN );
+REG64_FLD( PU_NPU2_CONFIG1_PBTX_REDUCE_RTAG                        , 32  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_REDUCE_RTAG );
+REG64_FLD( PU_NPU2_CONFIG1_PBTX_DELAY_BDONE                        , 33  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_DELAY_BDONE );
+REG64_FLD( PU_NPU2_CONFIG1_PBTX_FLIP_IMIN_BIG                      , 34  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_FLIP_IMIN_BIG );
+REG64_FLD( PU_NPU2_CONFIG1_PBTX_FLIP_IMIN_LITTLE                   , 35  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_FLIP_IMIN_LITTLE );
+REG64_FLD( PU_NPU2_CONFIG1_ALU_SAFE_LATENCY                        , 36  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_SAFE_LATENCY );
+REG64_FLD( PU_NPU2_CONFIG1_ALU_FLIP_ENDIAN_BIG                     , 37  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_FLIP_ENDIAN_BIG );
+REG64_FLD( PU_NPU2_CONFIG1_ALU_FLIP_ENDIAN_LITTLE                  , 38  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_FLIP_ENDIAN_LITTLE );
+REG64_FLD( PU_NPU2_CONFIG1_PBTX_EARLY_AFTAG                        , 39  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_EARLY_AFTAG );
+REG64_FLD( PU_NPU2_CONFIG1_RESERVED1                               , 40  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_CONFIG1_RESERVED1_LEN                           , 24  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK      , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN  , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ    , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB    , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY            , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN        , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT            , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN        , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL          , 28  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN      , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA          , 32  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN      , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_RESERVED                            , 36  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_SM0_CONFIG1_RESERVED_LEN                        , 28  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_BRICK_ENABLE                       , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_BRICK_ENABLE );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RSP_CTL_CRED_SINGLE_ENA            , 1   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RSP_CTL_CRED_SINGLE_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_CREQ_BE_128                        , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_CREQ_BE_128 );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_DGD_BE_128                         , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DGD_BE_128 );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_WR_SPLIT_UT0_ENA                   , 4   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_WR_SPLIT_UT0_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_WR_SPLIT_UT1_ENA                   , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_WR_SPLIT_UT1_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_BRICK_DEBUG_MODE                   , 6   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_BRICK_DEBUG_MODE );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_P9_TO_P9_MODE                      , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_P9_TO_P9_MODE );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED1                          , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_CAM256_MAX_CNT                     , 10  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_CAM256_MAX_CNT );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_CAM256_MAX_CNT_LEN                 , 6   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_CAM256_MAX_CNT_LEN );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_NDL_RX_PARITY_ENA                  , 16  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NDL_RX_PARITY_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_NDL_TX_PARITY_ENA                  , 17  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NDL_TX_PARITY_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_NDL_PRI_PARITY_ENA                 , 18  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NDL_PRI_PARITY_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RCV_CREDIT_OVERFLOW_ENA            , 19  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RCV_CREDIT_OVERFLOW_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_HDR_ARR_ECC_CORR_ENA               , 20  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_HDR_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_DAT_ARR_ECC_CORR_ENA               , 21  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DAT_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_TX_DATA_ECC_CORR_ENA               , 22  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_TX_DATA_ECC_CORR_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED2                          , 23  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_PARITY_ERROR_SUE_ENA               , 24  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ERROR_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_DATA_POISON_SUE_ENA                , 25  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DATA_POISON_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_HDR_ARR_ECC_SUE_ENA                , 26  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_HDR_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_DAT_ARR_ECC_SUE_ENA                , 27  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DAT_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_TX_ECC_DATA_POISON_ENA             , 28  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_TX_ECC_DATA_POISON_ENA );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED3                          , 29  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED3_LEN                      , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_PRI_STATE_MACHINE_RESET            , 32  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_PRI_STATE_MACHINE_RESET );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED4                          , 33  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED4  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED4_LEN                      , 31  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED4_LEN );
+
+REG64_FLD( PU_NPU1_CTL_CONFIG2_IDIAL                               , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_CTL_CONFIG2_IDIAL_LEN                           , 64  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_CTL_CONFIG2_IDIAL                               , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_CTL_CONFIG2_IDIAL_LEN                           , 64  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_CTL_CONFIG2_IDIAL                               , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_CTL_CONFIG2_IDIAL_LEN                           , 64  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( NV_CONFIG2_BRICK_ENABLE                                 , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_BRICK_ENABLE );
+REG64_FLD( NV_CONFIG2_RSP_CTL_CRED_SINGLE_ENA                      , 1   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RSP_CTL_CRED_SINGLE_ENA );
+REG64_FLD( NV_CONFIG2_CREQ_BE_128                                  , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_CREQ_BE_128 );
+REG64_FLD( NV_CONFIG2_DGD_BE_128                                   , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_DGD_BE_128 );
+REG64_FLD( NV_CONFIG2_WR_SPLIT_UT0_ENA                             , 4   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_WR_SPLIT_UT0_ENA );
+REG64_FLD( NV_CONFIG2_WR_SPLIT_UT1_ENA                             , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_WR_SPLIT_UT1_ENA );
+REG64_FLD( NV_CONFIG2_BRICK_DEBUG_MODE                             , 6   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_BRICK_DEBUG_MODE );
+REG64_FLD( NV_CONFIG2_P9_TO_P9_MODE                                , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_P9_TO_P9_MODE );
+REG64_FLD( NV_CONFIG2_RESERVED1                                    , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( NV_CONFIG2_RESERVED1_LEN                                , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( NV_CONFIG2_CAM256_MAX_CNT                               , 10  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_CAM256_MAX_CNT );
+REG64_FLD( NV_CONFIG2_CAM256_MAX_CNT_LEN                           , 6   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_CAM256_MAX_CNT_LEN );
+REG64_FLD( NV_CONFIG2_NDL_RX_PARITY_ENA                            , 16  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NDL_RX_PARITY_ENA );
+REG64_FLD( NV_CONFIG2_NDL_TX_PARITY_ENA                            , 17  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NDL_TX_PARITY_ENA );
+REG64_FLD( NV_CONFIG2_NDL_PRI_PARITY_ENA                           , 18  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NDL_PRI_PARITY_ENA );
+REG64_FLD( NV_CONFIG2_RCV_CREDIT_OVERFLOW_ENA                      , 19  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RCV_CREDIT_OVERFLOW_ENA );
+REG64_FLD( NV_CONFIG2_HDR_ARR_ECC_CORR_ENA                         , 20  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_HDR_ARR_ECC_CORR_ENA );
+REG64_FLD( NV_CONFIG2_DAT_ARR_ECC_CORR_ENA                         , 21  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_DAT_ARR_ECC_CORR_ENA );
+REG64_FLD( NV_CONFIG2_TX_DATA_ECC_CORR_ENA                         , 22  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_TX_DATA_ECC_CORR_ENA );
+REG64_FLD( NV_CONFIG2_RESERVED2                                    , 23  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( NV_CONFIG2_PARITY_ERROR_SUE_ENA                         , 24  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ERROR_SUE_ENA );
+REG64_FLD( NV_CONFIG2_DATA_POISON_SUE_ENA                          , 25  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_DATA_POISON_SUE_ENA );
+REG64_FLD( NV_CONFIG2_HDR_ARR_ECC_SUE_ENA                          , 26  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_HDR_ARR_ECC_SUE_ENA );
+REG64_FLD( NV_CONFIG2_DAT_ARR_ECC_SUE_ENA                          , 27  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_DAT_ARR_ECC_SUE_ENA );
+REG64_FLD( NV_CONFIG2_TX_ECC_DATA_POISON_ENA                       , 28  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_TX_ECC_DATA_POISON_ENA );
+REG64_FLD( NV_CONFIG2_RESERVED3                                    , 29  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( NV_CONFIG2_RESERVED3_LEN                                , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+REG64_FLD( NV_CONFIG2_PRI_STATE_MACHINE_RESET                      , 32  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_PRI_STATE_MACHINE_RESET );
+REG64_FLD( NV_CONFIG2_RESERVED4                                    , 33  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED4  );
+REG64_FLD( NV_CONFIG2_RESERVED4_LEN                                , 31  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED4_LEN );
+
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_BRICK_ENABLE                       , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_BRICK_ENABLE );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RSP_CTL_CRED_SINGLE_ENA            , 1   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RSP_CTL_CRED_SINGLE_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_CREQ_BE_128                        , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_CREQ_BE_128 );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_DGD_BE_128                         , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_DGD_BE_128 );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_WR_SPLIT_UT0_ENA                   , 4   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_WR_SPLIT_UT0_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_WR_SPLIT_UT1_ENA                   , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_WR_SPLIT_UT1_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_BRICK_DEBUG_MODE                   , 6   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_BRICK_DEBUG_MODE );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_P9_TO_P9_MODE                      , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_P9_TO_P9_MODE );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED1                          , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_CAM256_MAX_CNT                     , 10  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_CAM256_MAX_CNT );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_CAM256_MAX_CNT_LEN                 , 6   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_CAM256_MAX_CNT_LEN );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_NDL_RX_PARITY_ENA                  , 16  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NDL_RX_PARITY_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_NDL_TX_PARITY_ENA                  , 17  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NDL_TX_PARITY_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_NDL_PRI_PARITY_ENA                 , 18  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NDL_PRI_PARITY_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RCV_CREDIT_OVERFLOW_ENA            , 19  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RCV_CREDIT_OVERFLOW_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_HDR_ARR_ECC_CORR_ENA               , 20  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_HDR_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_DAT_ARR_ECC_CORR_ENA               , 21  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_DAT_ARR_ECC_CORR_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_TX_DATA_ECC_CORR_ENA               , 22  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_TX_DATA_ECC_CORR_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED2                          , 23  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_PARITY_ERROR_SUE_ENA               , 24  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ERROR_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_DATA_POISON_SUE_ENA                , 25  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_DATA_POISON_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_HDR_ARR_ECC_SUE_ENA                , 26  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_HDR_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_DAT_ARR_ECC_SUE_ENA                , 27  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_DAT_ARR_ECC_SUE_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_TX_ECC_DATA_POISON_ENA             , 28  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_TX_ECC_DATA_POISON_ENA );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED3                          , 29  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED3_LEN                      , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3_LEN );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_PRI_STATE_MACHINE_RESET            , 32  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_PRI_STATE_MACHINE_RESET );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED4                          , 33  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED4  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED4_LEN                      , 31  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED4_LEN );
+
+REG64_FLD( PU_NPU2_NTL0_CONFIG3_RESERVED1                          , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL0_CONFIG3_RESERVED1_LEN                      , 64  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_CTL_CONFIG3_IDIAL                               , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_CTL_CONFIG3_IDIAL_LEN                           , 64  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_CTL_CONFIG3_IDIAL                               , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_CTL_CONFIG3_IDIAL_LEN                           , 64  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_CTL_CONFIG3_IDIAL                               , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_CTL_CONFIG3_IDIAL_LEN                           , 64  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( NV_CONFIG3_RESERVED1                                    , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( NV_CONFIG3_RESERVED1_LEN                                , 64  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_NTL1_CONFIG3_RESERVED1                          , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL1_CONFIG3_RESERVED1_LEN                      , 64  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_WRENA );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_RDENA );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH       , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK        , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0           , 38  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0 );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN       , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       , 40  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_WRENA );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       , 41  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_RDENA );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH       , 42  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH_LEN );
+
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_WRENA );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_RDENA );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH       , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK        , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0           , 38  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0 );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN       , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       , 40  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_WRENA );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       , 41  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_RDENA );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH       , 42  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH_LEN );
+
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_WRENA );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_RDENA );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH       , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK        , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0           , 38  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0 );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN       , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       , 40  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_WRENA );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       , 41  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_RDENA );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH       , 42  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH_LEN );
+
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_WRENA );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_RDENA );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH       , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK        , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0           , 38  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0 );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN       , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       , 40  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_WRENA );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       , 41  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_RDENA );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH       , 42  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH_LEN );
+
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_WRENA );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_RDENA );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH       , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK        , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0           , 38  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0 );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN       , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       , 40  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_WRENA );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       , 41  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_RDENA );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH       , 42  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH_LEN );
+
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_WRENA );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_RDENA );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH       , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK        , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0           , 38  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0 );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN       , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       , 40  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_WRENA );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       , 41  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_RDENA );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH       , 42  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH_LEN );
+
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_WRENA );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_RDENA );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH       , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK        , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0           , 38  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0 );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN       , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       , 40  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_WRENA );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       , 41  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_RDENA );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH       , 42  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH_LEN );
+
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_WRENA );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_RDENA );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH       , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK        , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0           , 38  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0 );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN       , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       , 40  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_WRENA );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       , 41  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_RDENA );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH       , 42  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH_LEN );
+
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_WRENA );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_RDENA );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH       , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK        , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0           , 38  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0 );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN       , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       , 40  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_WRENA );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       , 41  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_RDENA );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH       , 42  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH_LEN );
+
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_WRENA );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_RDENA );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH       , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK        , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0           , 38  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0 );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN       , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       , 40  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_WRENA );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       , 41  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_RDENA );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH       , 42  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH_LEN );
+
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_WRENA );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_RDENA );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH       , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK        , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0           , 38  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0 );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN       , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       , 40  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_WRENA );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       , 41  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_RDENA );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH       , 42  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH_LEN );
+
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA       , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_WRENA );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA       , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_RDENA );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH       , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MATCH_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK        , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE0_MASK_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0           , 38  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0 );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN       , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED0_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA       , 40  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_WRENA );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA       , 41  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_RDENA );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH       , 42  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MATCH_LEN );
+
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK        , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1           , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1 );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN       , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_WRENA );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       , 21  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_RDENA );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH       , 22  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK        , 40  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2           , 58  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2 );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN       , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK        , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1           , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1 );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN       , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_WRENA );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       , 21  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_RDENA );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH       , 22  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK        , 40  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2           , 58  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2 );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN       , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK        , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1           , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1 );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN       , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_WRENA );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       , 21  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_RDENA );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH       , 22  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK        , 40  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2           , 58  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2 );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN       , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK        , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1           , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1 );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN       , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_WRENA );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       , 21  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_RDENA );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH       , 22  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK        , 40  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2           , 58  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2 );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN       , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK        , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1           , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1 );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN       , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_WRENA );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       , 21  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_RDENA );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH       , 22  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK        , 40  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2           , 58  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2 );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN       , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK        , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1           , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1 );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN       , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_WRENA );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       , 21  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_RDENA );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH       , 22  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK        , 40  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2           , 58  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2 );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN       , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK        , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1           , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1 );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN       , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_WRENA );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       , 21  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_RDENA );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH       , 22  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK        , 40  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2           , 58  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2 );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN       , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK        , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1           , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1 );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN       , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_WRENA );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       , 21  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_RDENA );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH       , 22  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK        , 40  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2           , 58  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2 );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN       , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK        , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1           , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1 );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN       , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_WRENA );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       , 21  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_RDENA );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH       , 22  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK        , 40  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2           , 58  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2 );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN       , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK        , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1           , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1 );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN       , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_WRENA );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       , 21  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_RDENA );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH       , 22  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK        , 40  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2           , 58  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2 );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN       , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK        , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1           , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1 );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN       , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_WRENA );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       , 21  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_RDENA );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH       , 22  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK        , 40  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2           , 58  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2 );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN       , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK        , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE1_MASK_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1           , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1 );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN       , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA       , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_WRENA );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA       , 21  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_RDENA );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH       , 22  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MATCH_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK        , 40  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE2_MASK_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2           , 58  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2 );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN       , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED2_LEN );
+
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W_HP );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_INJ );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      , 11  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_PR_DMA_INJ );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_DMA_PR_W );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        , 13  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_ADD );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        , 14  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_AND );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         , 15  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_OR );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_XOR );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       , 17  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_ADD );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_AND );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        , 19  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_OR );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_XOR );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     , 21  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_E );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     , 22  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_U );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     , 23  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_RD_NC_F0 );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA       , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_WRENA );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA       , 25  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_RDENA );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH       , 26  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK        , 44  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK_LEN );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3           , 62  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3 );
+REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN       , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W_HP );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_INJ );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      , 11  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_PR_DMA_INJ );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_DMA_PR_W );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        , 13  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_ADD );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        , 14  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_AND );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         , 15  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_OR );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_XOR );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       , 17  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_ADD );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_AND );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        , 19  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_OR );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_XOR );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     , 21  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_E );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     , 22  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_U );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     , 23  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_RD_NC_F0 );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA       , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_WRENA );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA       , 25  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_RDENA );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH       , 26  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK        , 44  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK_LEN );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3           , 62  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3 );
+REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN       , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W_HP );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_INJ );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      , 11  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_PR_DMA_INJ );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_DMA_PR_W );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        , 13  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_ADD );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        , 14  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_AND );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         , 15  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_OR );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_XOR );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       , 17  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_ADD );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_AND );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        , 19  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_OR );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_XOR );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     , 21  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_E );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     , 22  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_U );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     , 23  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_RD_NC_F0 );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA       , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_WRENA );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA       , 25  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_RDENA );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH       , 26  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK        , 44  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK_LEN );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3           , 62  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3 );
+REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN       , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W_HP );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_INJ );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      , 11  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_PR_DMA_INJ );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_DMA_PR_W );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        , 13  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_ADD );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        , 14  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_AND );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         , 15  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_OR );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_XOR );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       , 17  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_ADD );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_AND );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        , 19  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_OR );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_XOR );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     , 21  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_E );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     , 22  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_U );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     , 23  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_RD_NC_F0 );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA       , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_WRENA );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA       , 25  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_RDENA );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH       , 26  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK        , 44  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK_LEN );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3           , 62  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3 );
+REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN       , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W_HP );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_INJ );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      , 11  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_PR_DMA_INJ );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_DMA_PR_W );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        , 13  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_ADD );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        , 14  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_AND );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         , 15  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_OR );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_XOR );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       , 17  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_ADD );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_AND );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        , 19  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_OR );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_XOR );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     , 21  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_E );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     , 22  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_U );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     , 23  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_RD_NC_F0 );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA       , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_WRENA );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA       , 25  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_RDENA );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH       , 26  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK        , 44  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK_LEN );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3           , 62  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3 );
+REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN       , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W_HP );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_INJ );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      , 11  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_PR_DMA_INJ );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_DMA_PR_W );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        , 13  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_ADD );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        , 14  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_AND );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         , 15  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_OR );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_XOR );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       , 17  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_ADD );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_AND );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        , 19  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_OR );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_XOR );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     , 21  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_E );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     , 22  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_U );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     , 23  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_RD_NC_F0 );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA       , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_WRENA );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA       , 25  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_RDENA );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH       , 26  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK        , 44  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK_LEN );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3           , 62  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3 );
+REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN       , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W_HP );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_INJ );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      , 11  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_PR_DMA_INJ );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_DMA_PR_W );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        , 13  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_ADD );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        , 14  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_AND );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         , 15  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_OR );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_XOR );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       , 17  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_ADD );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_AND );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        , 19  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_OR );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_XOR );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     , 21  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_E );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     , 22  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_U );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     , 23  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_RD_NC_F0 );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA       , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_WRENA );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA       , 25  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_RDENA );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH       , 26  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK        , 44  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK_LEN );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3           , 62  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3 );
+REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN       , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W_HP );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_INJ );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      , 11  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_PR_DMA_INJ );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_DMA_PR_W );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        , 13  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_ADD );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        , 14  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_AND );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         , 15  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_OR );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_XOR );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       , 17  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_ADD );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_AND );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        , 19  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_OR );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_XOR );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     , 21  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_E );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     , 22  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_U );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     , 23  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_RD_NC_F0 );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA       , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_WRENA );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA       , 25  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_RDENA );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH       , 26  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK        , 44  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK_LEN );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3           , 62  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3 );
+REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN       , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W_HP );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_INJ );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      , 11  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_PR_DMA_INJ );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_DMA_PR_W );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        , 13  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_ADD );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        , 14  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_AND );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         , 15  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_OR );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_XOR );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       , 17  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_ADD );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_AND );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        , 19  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_OR );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_XOR );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     , 21  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_E );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     , 22  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_U );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     , 23  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_RD_NC_F0 );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA       , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_WRENA );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA       , 25  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_RDENA );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH       , 26  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK        , 44  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK_LEN );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3           , 62  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3 );
+REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN       , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W_HP );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_INJ );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      , 11  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_PR_DMA_INJ );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_DMA_PR_W );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        , 13  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_ADD );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        , 14  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_AND );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         , 15  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_OR );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_XOR );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       , 17  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_ADD );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_AND );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        , 19  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_OR );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_XOR );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     , 21  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_E );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     , 22  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_U );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     , 23  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_RD_NC_F0 );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA       , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_WRENA );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA       , 25  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_RDENA );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH       , 26  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN   , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK        , 44  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN    , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK_LEN );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3           , 62  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3 );
+REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN       , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W_HP );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_INJ );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      , 11  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_PR_DMA_INJ );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_DMA_PR_W );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        , 13  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_ADD );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        , 14  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_AND );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         , 15  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_OR );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_XOR );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       , 17  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_ADD );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_AND );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        , 19  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_OR );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_XOR );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     , 21  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_E );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     , 22  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_U );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     , 23  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_RD_NC_F0 );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA       , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_WRENA );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA       , 25  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_RDENA );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH       , 26  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN   , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK        , 44  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN    , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK_LEN );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3           , 62  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3 );
+REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN       , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3_LEN );
+
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W        , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP     , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_W_HP );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ      , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_DMA_INJ );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ      , 11  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_PR_DMA_INJ );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W        , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_DMA_PR_W );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD        , 13  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_ADD );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND        , 14  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_AND );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR         , 15  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_OR );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR        , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMW_XOR );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD       , 17  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_ADD );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND       , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_AND );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR        , 19  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_OR );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR       , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_XOR );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E     , 21  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_E );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U     , 22  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_ARMWF_CAS_U );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0     , 23  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_CMD_CL_RD_NC_F0 );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA       , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_WRENA );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA       , 25  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_RDENA );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH       , 26  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN   , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MATCH_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK        , 44  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN    , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_SOURCE3_MASK_LEN );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3           , 62  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3 );
+REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN       , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RELAXED_RESERVED3_LEN );
+
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHSTART_0      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHADDR_0       , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_READCONT_0       , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_READCONT_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHSTOP_0       , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_LENGTH_0             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_LENGTH_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_LENGTH_0_LEN         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_LENGTH_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_ADDR_0               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_ADDR_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_ADDR_0_LEN           , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_ADDR_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_RNW_0            , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_RNW_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_SPEED_0              , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_SPEED_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_SPEED_0_LEN          , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_SPEED_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_PORT_NUMBER_0        , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_PORT_NUMBER_0_LEN    , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_REG_ADDR_LEN_0                    , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REG_ADDR_LEN_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_REG_ADDR_LEN_0_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REG_ADDR_LEN_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_ENH_MODE_0                        , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENH_MODE_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_ECC_ENABLE_0                      , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_ENABLE_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_ECCCHK_DISABLE_0                  , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECCCHK_DISABLE_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_UNUSED_0                          , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_0   );
+REG64_FLD( PU_CONTROL_REGISTER_B_FAST_MODE_INTERRUPT_STERRING_BITS_0 , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_FAST_MODE_INTERRUPT_STERRING_BITS_0_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_1_0             , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_1_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_1_0_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_1_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_2_0             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_2_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_2_0_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_2_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_3_0             , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_3_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_3_0_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_3_0_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_4_0             , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_4_0 );
+REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_4_0_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_4_0_LEN );
+
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_WITHSTART_1      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_WITHADDR_1       , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_READCONT_1       , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_READCONT_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_WITHSTOP_1       , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_LENGTH_1             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_LENGTH_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_LENGTH_1_LEN         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_LENGTH_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_ADDR_1               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_ADDR_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_ADDR_1_LEN           , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_ADDR_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_RNW_1            , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_RNW_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_SPEED_1              , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_SPEED_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_SPEED_1_LEN          , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_SPEED_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_PORT_NUMBER_1        , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_PORT_NUMBER_1_LEN    , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_REG_ADDR_LEN_1                    , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REG_ADDR_LEN_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_REG_ADDR_LEN_1_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REG_ADDR_LEN_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_ENH_MODE_1                        , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENH_MODE_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_ECC_ENABLE_1                      , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_ENABLE_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_ECCCHK_DISABLE_1                  , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECCCHK_DISABLE_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_UNUSED_1                          , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_1   );
+REG64_FLD( PU_CONTROL_REGISTER_C_FAST_MODE_INTERRUPT_STERRING_BITS_1 , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_FAST_MODE_INTERRUPT_STERRING_BITS_1_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_1_1             , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_1_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_1_1_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_1_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_2_1             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_2_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_2_1_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_2_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_3_1             , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_3_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_3_1_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_3_1_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_4_1             , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_4_1 );
+REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_4_1_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_4_1_LEN );
+
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_WITHSTART_2      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_WITHADDR_2       , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_READCONT_2       , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_READCONT_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_WITHSTOP_2       , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_LENGTH_2             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_LENGTH_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_LENGTH_2_LEN         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_LENGTH_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_ADDR_2               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_ADDR_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_ADDR_2_LEN           , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_ADDR_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_RNW_2            , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_RNW_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_SPEED_2              , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_SPEED_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_SPEED_2_LEN          , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_SPEED_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_PORT_NUMBER_2        , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_PORT_NUMBER_2_LEN    , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_REG_ADDR_LEN_2                    , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REG_ADDR_LEN_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_REG_ADDR_LEN_2_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REG_ADDR_LEN_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_ENH_MODE_2                        , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENH_MODE_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_ECC_ENABLE_2                      , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_ENABLE_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_ECCCHK_DISABLE_2                  , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECCCHK_DISABLE_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_UNUSED_2                          , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( PU_CONTROL_REGISTER_D_FAST_MODE_INTERRUPT_STERRING_BITS_2 , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_FAST_MODE_INTERRUPT_STERRING_BITS_2_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_1_2             , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_1_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_1_2_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_1_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_2_2             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_2_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_2_2_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_2_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_3_2             , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_3_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_3_2_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_3_2_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_4_2             , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_4_2 );
+REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_4_2_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_4_2_LEN );
+
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_WITHSTART_3      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_WITHADDR_3       , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_READCONT_3       , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_READCONT_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_WITHSTOP_3       , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_LENGTH_3             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_LENGTH_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_LENGTH_3_LEN         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_LENGTH_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_ADDR_3               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_ADDR_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_ADDR_3_LEN           , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_ADDR_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_RNW_3            , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_BIT_RNW_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_SPEED_3              , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_SPEED_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_SPEED_3_LEN          , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_SPEED_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_PORT_NUMBER_3        , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_PORT_NUMBER_3_LEN    , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_REG_ADDR_LEN_3                    , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REG_ADDR_LEN_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_REG_ADDR_LEN_3_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REG_ADDR_LEN_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_ENH_MODE_3                        , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENH_MODE_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_ECC_ENABLE_3                      , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_ENABLE_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_ECCCHK_DISABLE_3                  , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECCCHK_DISABLE_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_UNUSED_3                          , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_3   );
+REG64_FLD( PU_CONTROL_REGISTER_E_FAST_MODE_INTERRUPT_STERRING_BITS_3 , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_FAST_MODE_INTERRUPT_STERRING_BITS_3_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_1_3             , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_1_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_1_3_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_1_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_2_3             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_2_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_2_3_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_2_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_3_3             , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_3_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_3_3_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_3_3_LEN );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_4_3             , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_4_3 );
+REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_4_3_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_CNTR_REG_DATA_4_3_LEN );
+
+REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC                  , 0   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE0_SEL_DC );
+REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN              , 6   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_6C                              , 6   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_6C );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_7C                              , 7   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_7C );
+REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC                  , 8   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE1_SEL_DC );
+REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN              , 6   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_14C                             , 14  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_14C );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_15C                             , 15  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_15C );
+REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC                  , 16  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE2_SEL_DC );
+REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN              , 6   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_22C                             , 22  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_22C );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_23C                             , 23  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_23C );
+REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC                  , 24  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE3_SEL_DC );
+REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN              , 6   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_30C                             , 30  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_30C );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_31C                             , 31  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_31C );
+REG64_FLD( PEC_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC                 , 32  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC );
+REG64_FLD( PEC_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC                  , 33  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_SCAN_PROTECT_DC );
+REG64_FLD( PEC_CPLT_CONF0_CTRL_CC_SDIS_DC_N                        , 34  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_SDIS_DC_N );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_35C                , 35  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_35C );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_36C                , 36  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_36C );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_37C                , 37  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_37C );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_38C                , 38  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_38C );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_39C                , 39  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_39C );
+REG64_FLD( PEC_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC            , 40  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC );
+REG64_FLD( PEC_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC       , 41  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_42C                             , 42  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_42C );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_43C                             , 43  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_43C );
+REG64_FLD( PEC_CPLT_CONF0_FREE_USAGE_44C                           , 44  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_44C );
+REG64_FLD( PEC_CPLT_CONF0_FREE_USAGE_45C                           , 45  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_45C );
+REG64_FLD( PEC_CPLT_CONF0_FREE_USAGE_46C                           , 46  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_46C );
+REG64_FLD( PEC_CPLT_CONF0_FREE_USAGE_47C                           , 47  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_47C );
+REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_GROUP_ID_DC                      , 48  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_GROUP_ID_DC );
+REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN                  , 4   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_GROUP_ID_DC_LEN );
+REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_CHIP_ID_DC                       , 52  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_CHIP_ID_DC );
+REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN                   , 3   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_CHIP_ID_DC_LEN );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_55C                          , 55  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_55C );
+REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_SYS_ID_DC                        , 56  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_SYS_ID_DC );
+REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN                    , 5   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_SYS_ID_DC_LEN );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_61C                          , 61  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_61C );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_62C                          , 62  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_62C );
+REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_63C                          , 63  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_63C );
+
+REG64_FLD( PEC_CPLT_CONF1_TC_IOX_MUX_VSEL                          , 0   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_IOX_MUX_VSEL );
+REG64_FLD( PEC_CPLT_CONF1_TC_IOX_MUX_VSEL_LEN                      , 3   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_IOX_MUX_VSEL_LEN );
+REG64_FLD( PEC_CPLT_CONF1_UNUSED                                   , 3   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED     );
+REG64_FLD( PEC_CPLT_CONF1_TC_PBE0_IOVALID_DC                       , 4   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PBE0_IOVALID_DC );
+REG64_FLD( PEC_CPLT_CONF1_TC_PBE1_IOVALID_DC                       , 5   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PBE1_IOVALID_DC );
+REG64_FLD( PEC_CPLT_CONF1_TC_PBE2_IOVALID_DC                       , 6   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PBE2_IOVALID_DC );
+REG64_FLD( PEC_CPLT_CONF1_TC_PBE3_IOVALID_DC                       , 7   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PBE3_IOVALID_DC );
+REG64_FLD( PEC_CPLT_CONF1_TC_PBE4_IOVALID_DC                       , 8   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PBE4_IOVALID_DC );
+REG64_FLD( PEC_CPLT_CONF1_TC_PBE5_IOVALID_DC                       , 9   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PBE5_IOVALID_DC );
+REG64_FLD( PEC_CPLT_CONF1_TC_PSI_IOVALID_DC                        , 10  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PSI_IOVALID_DC );
+REG64_FLD( PEC_CPLT_CONF1_IOVALID                                  , 11  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_IOVALID    );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_12D                           , 12  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_12D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_13D                           , 13  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_13D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_14D                           , 14  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_14D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_15D                           , 15  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_15D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_16D                           , 16  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_16D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_17D                           , 17  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_17D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_18D                           , 18  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_18D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_19D                           , 19  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_19D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_20D                           , 20  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_20D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_21D                           , 21  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_21D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_22D                           , 22  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_22D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_23D                           , 23  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_23D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_24D                           , 24  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_24D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_25D                           , 25  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_25D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_26D                           , 26  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_26D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_27D                           , 27  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_27D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_28D                           , 28  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_28D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_29D                           , 29  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_29D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_30D                           , 30  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_30D );
+REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_31D                           , 31  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_31D );
+
+REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC                , 0   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC );
+REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC                , 1   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC );
+REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC                 , 2   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_FLUSHMODE_INH_DC );
+REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC                   , 3   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_FORCE_ALIGN_DC );
+REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC                  , 4   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_ARY_WRT_THRU_DC );
+REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_AVP_MODE                         , 5   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_AVP_MODE );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_6A                            , 6   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_6A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_7A                            , 7   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_7A );
+REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC           , 8   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_9A                            , 9   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_9A );
+REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC         , 10  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC );
+REG64_FLD( PEC_CPLT_CTRL0_RESERVED_11A                             , 11  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_11A );
+REG64_FLD( PEC_CPLT_CTRL0_TC_SKIT_MODE_BIST_DC                     , 12  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_SKIT_MODE_BIST_DC );
+REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC     , 13  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC );
+REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC            , 14  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC );
+REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC              , 15  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC );
+REG64_FLD( PEC_CPLT_CTRL0_TC_NBTI_HDR_ENABLE_OVR_DC                , 16  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC );
+REG64_FLD( PEC_CPLT_CTRL0_TC_NBTI_PROBE_GATE_DC                    , 17  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_NBTI_PROBE_GATE_DC );
+REG64_FLD( PEC_CPLT_CTRL0_RESERVED_18A                             , 18  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_18A );
+REG64_FLD( PEC_CPLT_CTRL0_RESERVED_19A                             , 19  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_19A );
+REG64_FLD( PEC_CPLT_CTRL0_TC_PSRO_SEL_DC                           , 20  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PSRO_SEL_DC );
+REG64_FLD( PEC_CPLT_CTRL0_TC_PSRO_SEL_DC_LEN                       , 8   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PSRO_SEL_DC_LEN );
+REG64_FLD( PEC_CPLT_CTRL0_TC_BSC_WRAPSEL_DC                        , 28  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_WRAPSEL_DC );
+REG64_FLD( PEC_CPLT_CTRL0_TC_BSC_INTMODE_DC                        , 29  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_INTMODE_DC );
+REG64_FLD( PEC_CPLT_CTRL0_TC_BSC_INV_DC                            , 30  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_INV_DC );
+REG64_FLD( PEC_CPLT_CTRL0_TC_BSC_EXTMODE_DC                        , 31  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_EXTMODE_DC );
+REG64_FLD( PEC_CPLT_CTRL0_TC_REFCLK_DRVR_EN_DC                     , 32  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REFCLK_DRVR_EN_DC );
+REG64_FLD( PEC_CPLT_CTRL0_RESERVED_33A                             , 33  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_33A );
+REG64_FLD( PEC_CPLT_CTRL0_RESERVED_34A                             , 34  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_34A );
+REG64_FLD( PEC_CPLT_CTRL0_RESERVED_35A                             , 35  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_35A );
+REG64_FLD( PEC_CPLT_CTRL0_TC_OELCC_EDGE_DELAYED_DC                 , 36  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_OELCC_EDGE_DELAYED_DC );
+REG64_FLD( PEC_CPLT_CTRL0_TC_OELCC_ALIGN_FLUSH_DC                  , 37  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_OELCC_ALIGN_FLUSH_DC );
+REG64_FLD( PEC_CPLT_CTRL0_RESERVED_38A                             , 38  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_38A );
+REG64_FLD( PEC_CPLT_CTRL0_RESERVED_39A                             , 39  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_39A );
+REG64_FLD( PEC_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC                  , 40  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_CLKDIV_SEL_DC );
+REG64_FLD( PEC_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN              , 2   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN );
+REG64_FLD( PEC_CPLT_CTRL0_RESERVED_42A                             , 42  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_42A );
+REG64_FLD( PEC_CPLT_CTRL0_RESERVED_43A                             , 43  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_43A );
+REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_DCTEST_DC                        , 44  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_DCTEST_DC );
+REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_OTP_PRGMODE_DC                   , 45  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_OTP_PRGMODE_DC );
+REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_SSS_CALIBRATE_DC                 , 46  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_SSS_CALIBRATE_DC );
+REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC                     , 47  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_PIN_LBIST_DC );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_48A                           , 48  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_48A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_49A                           , 49  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_49A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_50A                           , 50  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_50A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_51A                           , 51  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_51A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_52A                           , 52  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_52A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_53A                           , 53  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_53A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_54A                           , 54  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_54A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_55A                           , 55  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_55A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_56A                           , 56  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_56A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_57A                           , 57  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_57A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_58A                           , 58  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_58A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_59A                           , 59  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_59A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_60A                           , 60  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_60A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_61A                           , 61  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_61A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_62A                           , 62  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_62A );
+REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_63A                           , 63  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_63A );
+
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_0B                                , 0   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_0B  );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_1B                                , 1   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_1B  );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_2B                                , 2   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_2B  );
+REG64_FLD( PEC_CPLT_CTRL1_TC_VITL_REGION_FENCE                     , 3   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_VITL_REGION_FENCE );
+REG64_FLD( PEC_CPLT_CTRL1_TC_PERV_REGION_FENCE                     , 4   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PERV_REGION_FENCE );
+REG64_FLD( PEC_CPLT_CTRL1_TC_REGION1_FENCE                         , 5   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION1_FENCE );
+REG64_FLD( PEC_CPLT_CTRL1_TC_REGION2_FENCE                         , 6   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION2_FENCE );
+REG64_FLD( PEC_CPLT_CTRL1_TC_REGION3_FENCE                         , 7   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION3_FENCE );
+REG64_FLD( PEC_CPLT_CTRL1_TC_REGION4_FENCE                         , 8   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION4_FENCE );
+REG64_FLD( PEC_CPLT_CTRL1_TC_REGION5_FENCE                         , 9   , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION5_FENCE );
+REG64_FLD( PEC_CPLT_CTRL1_TC_REGION6_FENCE                         , 10  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION6_FENCE );
+REG64_FLD( PEC_CPLT_CTRL1_TC_REGION7_FENCE                         , 11  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION7_FENCE );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_12B                               , 12  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_12B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_13B                               , 13  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_13B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_14B                               , 14  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_14B );
+REG64_FLD( PEC_CPLT_CTRL1_RESERVED                                 , 15  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED   );
+REG64_FLD( PEC_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE            , 16  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_17B                               , 17  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_17B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_18B                               , 18  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_18B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_19B                               , 19  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_19B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_20B                               , 20  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_20B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_21B                               , 21  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_21B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_22B                               , 22  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_22B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_23B                               , 23  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_23B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_24B                               , 24  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_24B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_25B                               , 25  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_25B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_26B                               , 26  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_26B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_27B                               , 27  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_27B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_28B                               , 28  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_28B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_29B                               , 29  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_29B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_30B                               , 30  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_30B );
+REG64_FLD( PEC_CPLT_CTRL1_UNUSED_31B                               , 31  , SH_UNT_PEC      , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_31B );
+
+REG64_FLD( PEC_CPLT_MASK0_CPLTMASK0                                , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CPLTMASK0  );
+REG64_FLD( PEC_CPLT_MASK0_CPLTMASK0_LEN                            , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CPLTMASK0_LEN );
+
+REG64_FLD( PEC_CPLT_STAT0_SRAM_ABIST_DONE_DC                       , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SRAM_ABIST_DONE_DC );
+REG64_FLD( PEC_CPLT_STAT0_DRAM_ABIST_DONE_DC                       , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DRAM_ABIST_DONE_DC );
+REG64_FLD( PEC_CPLT_STAT0_RESERVED_2E                              , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_2E );
+REG64_FLD( PEC_CPLT_STAT0_RESERVED_3E                              , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_3E );
+REG64_FLD( PEC_CPLT_STAT0_TC_DIAG_PORT0_OUT                        , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TC_DIAG_PORT0_OUT );
+REG64_FLD( PEC_CPLT_STAT0_TC_DIAG_PORT1_OUT                        , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TC_DIAG_PORT1_OUT );
+REG64_FLD( PEC_CPLT_STAT0_RESERVED_6E                              , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_6E );
+REG64_FLD( PEC_CPLT_STAT0_PLL_DESTOUT                              , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PLL_DESTOUT );
+REG64_FLD( PEC_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC                     , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CC_CTRL_OPCG_DONE_DC );
+REG64_FLD( PEC_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC            , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC );
+REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_10E                           , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_10E );
+REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_11E                           , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_11E );
+REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_12E                           , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_12E );
+REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_13E                           , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_13E );
+REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_14E                           , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_14E );
+REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_15E                           , 15  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_15E );
+REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_16E                           , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_16E );
+REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_17E                           , 17  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_17E );
+REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_18E                           , 18  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_18E );
+REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_19E                           , 19  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_19E );
+REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_20E                           , 20  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_20E );
+REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_21E                           , 21  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_21E );
+REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_22E                           , 22  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_22E );
+REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_23E                           , 23  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_23E );
+
+REG64_FLD( PEC_STACK2_CQSTAT_REG_PE_INBOUND_ACTIVE                 , 0   , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RO  ,
+           SH_FLD_PE_INBOUND_ACTIVE );
+REG64_FLD( PEC_STACK2_CQSTAT_REG_PE_OUTBOUND_ACTIVE                , 1   , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RO  ,
+           SH_FLD_PE_OUTBOUND_ACTIVE );
+
+REG64_FLD( PEC_STACK1_CQSTAT_REG_PE_INBOUND_ACTIVE                 , 0   , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RO  ,
+           SH_FLD_PE_INBOUND_ACTIVE );
+REG64_FLD( PEC_STACK1_CQSTAT_REG_PE_OUTBOUND_ACTIVE                , 1   , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RO  ,
+           SH_FLD_PE_OUTBOUND_ACTIVE );
+
+REG64_FLD( PHB_CQSTAT_REG_PE_INBOUND_ACTIVE                        , 0   , SH_UNT_PHB      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PE_INBOUND_ACTIVE );
+REG64_FLD( PHB_CQSTAT_REG_PE_OUTBOUND_ACTIVE                       , 1   , SH_UNT_PHB      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PE_OUTBOUND_ACTIVE );
+
+REG64_FLD( PEC_STACK0_CQSTAT_REG_PE_INBOUND_ACTIVE                 , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RO  ,
+           SH_FLD_PE_INBOUND_ACTIVE );
+REG64_FLD( PEC_STACK0_CQSTAT_REG_PE_OUTBOUND_ACTIVE                , 1   , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RO  ,
+           SH_FLD_PE_OUTBOUND_ACTIVE );
+
+REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_RESERVED1                      , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_RESERVED1_LEN                  , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_START                          , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_START_LEN                      , 9   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_RESERVED2                      , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_RESERVED2_LEN                  , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_END                            , 15  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_END_LEN                        , 9   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( NV_CREQ_DA_PTR_RESERVED1                                , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( NV_CREQ_DA_PTR_RESERVED1_LEN                            , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( NV_CREQ_DA_PTR_START                                    , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( NV_CREQ_DA_PTR_START_LEN                                , 9   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( NV_CREQ_DA_PTR_RESERVED2                                , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( NV_CREQ_DA_PTR_RESERVED2_LEN                            , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( NV_CREQ_DA_PTR_END                                      , 15  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( NV_CREQ_DA_PTR_END_LEN                                  , 9   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_RESERVED1                      , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_RESERVED1_LEN                  , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_START                          , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_START_LEN                      , 9   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_RESERVED2                      , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_RESERVED2_LEN                  , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_END                            , 15  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_END_LEN                        , 9   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_RESERVED1                      , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_RESERVED1_LEN                  , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_START                          , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_START_LEN                      , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_RESERVED2                      , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_RESERVED2_LEN                  , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_END                            , 17  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_END_LEN                        , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( NV_CREQ_HA_PTR_RESERVED1                                , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( NV_CREQ_HA_PTR_RESERVED1_LEN                            , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( NV_CREQ_HA_PTR_START                                    , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( NV_CREQ_HA_PTR_START_LEN                                , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( NV_CREQ_HA_PTR_RESERVED2                                , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( NV_CREQ_HA_PTR_RESERVED2_LEN                            , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( NV_CREQ_HA_PTR_END                                      , 17  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( NV_CREQ_HA_PTR_END_LEN                                  , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_RESERVED1                      , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_RESERVED1_LEN                  , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_START                          , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_START_LEN                      , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_RESERVED2                      , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_RESERVED2_LEN                  , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_END                            , 17  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_END_LEN                        , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( PU_CSAR_SRAM_ADDRESS                                    , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_ADDRESS );
+REG64_FLD( PU_CSAR_SRAM_ADDRESS_LEN                                , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_ADDRESS_LEN );
+
+REG64_FLD( PU_CSCR_SRAM_ACCESS_MODE                                , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_ACCESS_MODE );
+REG64_FLD( PU_CSCR_SRAM_SCRUB_ENABLE                               , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SCRUB_ENABLE );
+REG64_FLD( PU_CSCR_ECC_CORRECT_DIS                                 , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_CORRECT_DIS );
+REG64_FLD( PU_CSCR_ECC_DETECT_DIS                                  , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_DETECT_DIS );
+REG64_FLD( PU_CSCR_ECC_INJECT_TYPE                                 , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_INJECT_TYPE );
+REG64_FLD( PU_CSCR_ECC_INJECT_ERR                                  , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_INJECT_ERR );
+REG64_FLD( PU_CSCR_SPARE_6_7                                       , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_6_7  );
+REG64_FLD( PU_CSCR_SPARE_6_7_LEN                                   , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( PU_CSCR_SRAM_SCRUB_INDEX                                , 47  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SCRUB_INDEX );
+REG64_FLD( PU_CSCR_SRAM_SCRUB_INDEX_LEN                            , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SCRUB_INDEX_LEN );
+
+REG64_FLD( PU_CSDR_SRAM_DATA                                       , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_DATA  );
+REG64_FLD( PU_CSDR_SRAM_DATA_LEN                                   , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_DATA_LEN );
+
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_SM_MMIO0                         , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SM_MMIO0   );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_SM_MMIO1                         , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SM_MMIO1   );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_SM_MMIO2                         , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SM_MMIO2   );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_SM_MMIO3                         , 3   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SM_MMIO3   );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_MRBGP                            , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP      );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_MRBGP_LEN                        , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP_LEN  );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_MRBSP                            , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP      );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_MRBSP_LEN                        , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP_LEN  );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_FENCE0                           , 12  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0     );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_FENCE0_LEN                       , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_LEN );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_FENCE1                           , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1     );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_FENCE1_LEN                       , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_LEN );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_LPCTH                            , 20  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LPCTH      );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_LPCTH_LEN                        , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LPCTH_LEN  );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBM_STATE                        , 22  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBM_STATE  );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBM_STATE_LEN                    , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBM_STATE_LEN );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_BRK0_RLX                         , 27  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK0_RLX   );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_BRK1_RLX                         , 28  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK1_RLX   );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_BRK0_NVL                         , 29  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK0_NVL   );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_BRK1_NVL                         , 30  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK1_NVL   );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_ATS_SYNC                         , 31  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ATS_SYNC   );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NMMU                             , 32  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMMU       );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBLN                             , 33  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBLN       );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBNNG                            , 34  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBNNG      );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBRNVG                           , 35  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBRNVG     );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVREQ0                           , 36  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVREQ0     );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVDGD0                           , 37  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVDGD0     );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVREQ1                           , 38  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVREQ1     );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVDGD1                           , 39  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVDGD1     );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_ATSREQ                           , 40  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ATSREQ     );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_MMIO                             , 41  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MMIO       );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBRS                             , 42  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBRS       );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVRS0                            , 43  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVRS0      );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVRS1                            , 44  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVRS1      );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_XARS                             , 45  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_XARS       );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_ATRR                             , 46  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ATRR       );
+REG64_FLD( PU_NPU1_CTL_CTL_STATUS_RESERVED1                        , 47  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_SM_MMIO0                         , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SM_MMIO0   );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_SM_MMIO1                         , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SM_MMIO1   );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_SM_MMIO2                         , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SM_MMIO2   );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_SM_MMIO3                         , 3   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SM_MMIO3   );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_MRBGP                            , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP      );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_MRBGP_LEN                        , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP_LEN  );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_MRBSP                            , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP      );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_MRBSP_LEN                        , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP_LEN  );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_FENCE0                           , 12  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0     );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_FENCE0_LEN                       , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_LEN );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_FENCE1                           , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1     );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_FENCE1_LEN                       , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_LEN );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_LPCTH                            , 20  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LPCTH      );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_LPCTH_LEN                        , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LPCTH_LEN  );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBM_STATE                        , 22  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBM_STATE  );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBM_STATE_LEN                    , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBM_STATE_LEN );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_BRK0_RLX                         , 27  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK0_RLX   );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_BRK1_RLX                         , 28  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK1_RLX   );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_BRK0_NVL                         , 29  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK0_NVL   );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_BRK1_NVL                         , 30  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK1_NVL   );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_ATS_SYNC                         , 31  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ATS_SYNC   );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NMMU                             , 32  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMMU       );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBLN                             , 33  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBLN       );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBNNG                            , 34  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBNNG      );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBRNVG                           , 35  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBRNVG     );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVREQ0                           , 36  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVREQ0     );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVDGD0                           , 37  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVDGD0     );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVREQ1                           , 38  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVREQ1     );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVDGD1                           , 39  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVDGD1     );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_ATSREQ                           , 40  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ATSREQ     );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_MMIO                             , 41  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MMIO       );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBRS                             , 42  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBRS       );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVRS0                            , 43  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVRS0      );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVRS1                            , 44  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVRS1      );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_XARS                             , 45  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_XARS       );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_ATRR                             , 46  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ATRR       );
+REG64_FLD( PU_NPU0_CTL_CTL_STATUS_RESERVED1                        , 47  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_SM_MMIO0                         , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SM_MMIO0   );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_SM_MMIO1                         , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SM_MMIO1   );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_SM_MMIO2                         , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SM_MMIO2   );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_SM_MMIO3                         , 3   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SM_MMIO3   );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_MRBGP                            , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP      );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_MRBGP_LEN                        , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP_LEN  );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_MRBSP                            , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP      );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_MRBSP_LEN                        , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP_LEN  );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_FENCE0                           , 12  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0     );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_FENCE0_LEN                       , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_LEN );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_FENCE1                           , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1     );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_FENCE1_LEN                       , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_LEN );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_LPCTH                            , 20  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LPCTH      );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_LPCTH_LEN                        , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LPCTH_LEN  );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBM_STATE                        , 22  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBM_STATE  );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBM_STATE_LEN                    , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBM_STATE_LEN );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_BRK0_RLX                         , 27  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK0_RLX   );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_BRK1_RLX                         , 28  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK1_RLX   );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_BRK0_NVL                         , 29  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK0_NVL   );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_BRK1_NVL                         , 30  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK1_NVL   );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_ATS_SYNC                         , 31  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ATS_SYNC   );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NMMU                             , 32  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMMU       );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBLN                             , 33  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBLN       );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBNNG                            , 34  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBNNG      );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBRNVG                           , 35  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBRNVG     );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVREQ0                           , 36  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVREQ0     );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVDGD0                           , 37  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVDGD0     );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVREQ1                           , 38  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVREQ1     );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVDGD1                           , 39  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVDGD1     );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_ATSREQ                           , 40  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ATSREQ     );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_MMIO                             , 41  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MMIO       );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBRS                             , 42  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PBRS       );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVRS0                            , 43  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVRS0      );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVRS1                            , 44  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NVRS1      );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_XARS                             , 45  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_XARS       );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_ATRR                             , 46  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ATRR       );
+REG64_FLD( PU_NPU2_CTL_CTL_STATUS_RESERVED1                        , 47  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+
+REG64_FLD( PEC_CTRL_ATOMIC_LOCK_REG_ENABLE                         , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PEC_CTRL_ATOMIC_LOCK_REG_ID                             , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( PEC_CTRL_ATOMIC_LOCK_REG_ID_LEN                         , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ID_LEN     );
+REG64_FLD( PEC_CTRL_ATOMIC_LOCK_REG_ACTIVITY                       , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY   );
+REG64_FLD( PEC_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN                   , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( PEC_CTRL_PROTECT_MODE_REG_READ_ENABLE                   , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_READ_ENABLE );
+REG64_FLD( PEC_CTRL_PROTECT_MODE_REG_WRITE_ENABLE                  , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( CAPP_CXA_SNP_ARRAY_ADDR_REG_ADDRESS                     , 1   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( CAPP_CXA_SNP_ARRAY_ADDR_REG_ADDRESS_LEN                 , 15  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( CAPP_CXA_SNP_ARRAY_READ_REG_DATA                        , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_DATA       );
+REG64_FLD( CAPP_CXA_SNP_ARRAY_READ_REG_DATA_LEN                    , 64  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( CAPP_CXA_SNP_ARRAY_WRITE_REG_DATA                       , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_DATA       );
+REG64_FLD( CAPP_CXA_SNP_ARRAY_WRITE_REG_DATA_LEN                   , 64  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG0_0_CANNED_0                  , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_0_CANNED_0 );
+REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG0_0_CANNED_0_LEN              , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_0_CANNED_0_LEN );
+REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG0_0_CANNED_1                  , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_0_CANNED_1 );
+REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG0_0_CANNED_1_LEN              , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_0_CANNED_1_LEN );
+
+REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG1_1_CANNED_0                  , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_1_CANNED_0 );
+REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG1_1_CANNED_0_LEN              , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_1_CANNED_0_LEN );
+REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG1_1_CANNED_1                  , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_1_CANNED_1 );
+REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG1_1_CANNED_1_LEN              , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_1_CANNED_1_LEN );
+
+REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG2_2_CANNED_0                  , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_2_CANNED_0 );
+REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG2_2_CANNED_0_LEN              , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_2_CANNED_0_LEN );
+REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG2_2_CANNED_1                  , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_2_CANNED_1 );
+REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG2_2_CANNED_1_LEN              , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_2_CANNED_1_LEN );
+
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_ENABLE_TTYPE_DECODE           , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_TTYPE_DECODE );
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_PRECISE_DIR_SIZE              , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PRECISE_DIR_SIZE );
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_PRECISE_DIR_SIZE_LEN          , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PRECISE_DIR_SIZE_LEN );
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_COARSE_DIR_ENABLE             , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COARSE_DIR_ENABLE );
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_COARSE_DIR_SECTORS            , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COARSE_DIR_SECTORS );
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_MCD_CHICKEN_SWITCH            , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_MCD_CHICKEN_SWITCH );
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_BHR_DIR_STATE                 , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BHR_DIR_STATE );
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_BHR_DIR_STATE_LEN             , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BHR_DIR_STATE_LEN );
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_LPC_MODE                      , 12  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_LPC_MODE   );
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_LPC_MODE_LEN                  , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_LPC_MODE_LEN );
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_CT_COMPARE_VECTOR             , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CT_COMPARE_VECTOR );
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_CT_COMPARE_VECTOR_LEN         , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CT_COMPARE_VECTOR_LEN );
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_PHB_FILTER_CNTL               , 38  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PHB_FILTER_CNTL );
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_PHB_FILTER_CNTL_LEN           , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PHB_FILTER_CNTL_LEN );
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_EPOCH_TEST_VECTOR             , 40  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_EPOCH_TEST_VECTOR );
+REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_EPOCH_TEST_VECTOR_LEN         , 24  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_EPOCH_TEST_VECTOR_LEN );
+
+REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_MODE                 , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_READ_EPSILON_MODE );
+REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER0                , 3   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_READ_EPSILON_TIER0 );
+REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER0_LEN            , 9   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_READ_EPSILON_TIER0_LEN );
+REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER1                , 15  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_READ_EPSILON_TIER1 );
+REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER1_LEN            , 9   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_READ_EPSILON_TIER1_LEN );
+REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER2                , 25  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_READ_EPSILON_TIER2 );
+REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER2_LEN            , 11  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_READ_EPSILON_TIER2_LEN );
+REG64_FLD( CAPP_CXA_SNP_CNTL_REG_ADDRESS_PIPELINE_MASTERWAIT_COUNT , 45  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT );
+REG64_FLD( CAPP_CXA_SNP_CNTL_REG_ADDRESS_PIPELINE_MASTERWAIT_COUNT_LEN , 3   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT_LEN );
+REG64_FLD( CAPP_CXA_SNP_CNTL_REG_DATA_HANG_POLL_SCALE              , 48  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_DATA_HANG_POLL_SCALE );
+REG64_FLD( CAPP_CXA_SNP_CNTL_REG_DATA_HANG_POLL_SCALE_LEN          , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_DATA_HANG_POLL_SCALE_LEN );
+
+REG64_FLD( CAPP_CXA_SNP_ERROR_REPORT_REG_C_ERR_RPT_HOLD_DATA       , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_C_ERR_RPT_HOLD_DATA );
+REG64_FLD( CAPP_CXA_SNP_ERROR_REPORT_REG_C_ERR_RPT_HOLD_DATA_LEN   , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_C_ERR_RPT_HOLD_DATA_LEN );
+
+REG64_FLD( CAPP_CXA_SNP_PHB_TTAG_FILTER_REG_FILTER                 , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_FILTER     );
+REG64_FLD( CAPP_CXA_SNP_PHB_TTAG_FILTER_REG_FILTER_LEN             , 48  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_FILTER_LEN );
+
+REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_GROUP                , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP      );
+REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_GROUP_LEN            , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP_LEN  );
+REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_EVENT           , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_FSMJ_EVENT );
+REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_EVENT_LEN       , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_FSMJ_EVENT_LEN );
+REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_FSM             , 14  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_FSMJ_FSM   );
+REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_FSM_LEN         , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_FSMJ_FSM_LEN );
+
+REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_EN                , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_EN         );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_SIZE              , 1   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SIZE       );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_SIZE_LEN          , 18  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SIZE_LEN   );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_STARTING_ADDRESS  , 19  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_STARTING_ADDRESS );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_STARTING_ADDRESS_LEN , 27  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_STARTING_ADDRESS_LEN );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_SYSTEM            , 50  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SYSTEM     );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_SYSTEM_LEN        , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SYSTEM_LEN );
+
+REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_EN          , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BAR1_EN    );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_SIZE        , 1   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BAR1_SIZE  );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_SIZE_LEN    , 18  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BAR1_SIZE_LEN );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_STARTING_ADDRESS , 19  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BAR1_STARTING_ADDRESS );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_STARTING_ADDRESS_LEN , 27  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BAR1_STARTING_ADDRESS_LEN );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_SYSTEM      , 50  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BAR1_SYSTEM );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_SYSTEM_LEN  , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BAR1_SYSTEM_LEN );
+
+REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG_EN                , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_EN         );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG_MS_GROUP_CHIP     , 13  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_MS_GROUP_CHIP );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG_MS_GROUP_CHIP_LEN , 9   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_MS_GROUP_CHIP_LEN );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG_STARTING_ADDRESS  , 22  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_STARTING_ADDRESS );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG_STARTING_ADDRESS_LEN , 31  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_STARTING_ADDRESS_LEN );
+
+REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_EN          , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BAR1_EN    );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_MS_GROUP_CHIP , 13  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BAR1_MS_GROUP_CHIP );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_MS_GROUP_CHIP_LEN , 9   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BAR1_MS_GROUP_CHIP_LEN );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_STARTING_ADDRESS , 22  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BAR1_STARTING_ADDRESS );
+REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_STARTING_ADDRESS_LEN , 31  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BAR1_STARTING_ADDRESS_LEN );
+
+REG64_FLD( CAPP_CXA_TRIGCTL_PORTSEL                                , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PORTSEL    );
+REG64_FLD( CAPP_CXA_TRIGCTL_PORTSEL_LEN                            , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PORTSEL_LEN );
+REG64_FLD( CAPP_CXA_TRIGCTL_APC0_ENABLE                            , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APC0_ENABLE );
+REG64_FLD( CAPP_CXA_TRIGCTL_APC1_ENABLE                            , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APC1_ENABLE );
+REG64_FLD( CAPP_CXA_TRIGCTL_SNPFE_TRIGGER_ENABLE                   , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SNPFE_TRIGGER_ENABLE );
+REG64_FLD( CAPP_CXA_TRIGCTL_SNPFE_DIR_TRIGGER_ENABLE               , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SNPFE_DIR_TRIGGER_ENABLE );
+REG64_FLD( CAPP_CXA_TRIGCTL_SNPBE_TRIGGER_ENABLE                   , 8   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SNPBE_TRIGGER_ENABLE );
+REG64_FLD( CAPP_CXA_TRIGCTL_SNPBE_UOP_TRIGGER_ENABLE               , 9   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SNPBE_UOP_TRIGGER_ENABLE );
+REG64_FLD( CAPP_CXA_TRIGCTL_SNP_MUX_PORT_SEL                       , 12  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SNP_MUX_PORT_SEL );
+REG64_FLD( CAPP_CXA_TRIGCTL_SNP_MUX_PORT_SEL_LEN                   , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SNP_MUX_PORT_SEL_LEN );
+
+REG64_FLD( PU_DATA0TO7_REGISTER_B_PIB_0                            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_0      );
+REG64_FLD( PU_DATA0TO7_REGISTER_B_PIB_0_LEN                        , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_0_LEN  );
+
+REG64_FLD( PU_DATA0TO7_REGISTER_C_PIB_1                            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_1      );
+REG64_FLD( PU_DATA0TO7_REGISTER_C_PIB_1_LEN                        , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_1_LEN  );
+
+REG64_FLD( PU_DATA0TO7_REGISTER_D_PIB_2                            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_2      );
+REG64_FLD( PU_DATA0TO7_REGISTER_D_PIB_2_LEN                        , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_2_LEN  );
+
+REG64_FLD( PU_DATA0TO7_REGISTER_E_PIB_3                            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_3      );
+REG64_FLD( PU_DATA0TO7_REGISTER_E_PIB_3_LEN                        , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_3_LEN  );
+
+REG64_FLD( PU_DATA8TO15_REGISTER_B_PIB_0                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_0      );
+REG64_FLD( PU_DATA8TO15_REGISTER_B_PIB_0_LEN                       , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_0_LEN  );
+
+REG64_FLD( PU_DATA8TO15_REGISTER_C_PIB_1                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_1      );
+REG64_FLD( PU_DATA8TO15_REGISTER_C_PIB_1_LEN                       , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_1_LEN  );
+
+REG64_FLD( PU_DATA8TO15_REGISTER_D_PIB_2                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_2      );
+REG64_FLD( PU_DATA8TO15_REGISTER_D_PIB_2_LEN                       , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_2_LEN  );
+
+REG64_FLD( PU_DATA8TO15_REGISTER_E_PIB_3                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_3      );
+REG64_FLD( PU_DATA8TO15_REGISTER_E_PIB_3_LEN                       , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_3_LEN  );
+
+REG64_FLD( PU_DATATAG_0_HASH_FUNCTION_REG_FUNCTION                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FUNCTION   );
+REG64_FLD( PU_DATATAG_0_HASH_FUNCTION_REG_FUNCTION_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FUNCTION_LEN );
+
+REG64_FLD( PU_DATATAG_1_HASH_FUNCTION_REG_FUNCTION                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FUNCTION   );
+REG64_FLD( PU_DATATAG_1_HASH_FUNCTION_REG_FUNCTION_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FUNCTION_LEN );
+
+REG64_FLD( PU_DATATAG_2_HASH_FUNCTION_REG_FUNCTION                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FUNCTION   );
+REG64_FLD( PU_DATATAG_2_HASH_FUNCTION_REG_FUNCTION_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FUNCTION_LEN );
+
+REG64_FLD( PU_DATATAG_3_HASH_FUNCTION_REG_FUNCTION                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FUNCTION   );
+REG64_FLD( PU_DATATAG_3_HASH_FUNCTION_REG_FUNCTION_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FUNCTION_LEN );
+
+REG64_FLD( PU_DATATAG_4_HASH_FUNCTION_REG_FUNCTION                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FUNCTION   );
+REG64_FLD( PU_DATATAG_4_HASH_FUNCTION_REG_FUNCTION_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FUNCTION_LEN );
+
+REG64_FLD( PU_DATATAG_5_HASH_FUNCTION_REG_FUNCTION                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FUNCTION   );
+REG64_FLD( PU_DATATAG_5_HASH_FUNCTION_REG_FUNCTION_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FUNCTION_LEN );
+
+REG64_FLD( PU_DATA_REGISTER_OTP                                    , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OTP        );
+REG64_FLD( PU_DATA_REGISTER_OTP_LEN                                , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OTP_LEN    );
+
+REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC                                 , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC       );
+REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_LEN                             , 24  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_LEN   );
+REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_LENGTH                          , 24  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_LENGTH );
+REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_LENGTH_LEN                      , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_LENGTH_LEN );
+REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_RSVD                            , 26  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_RSVD  );
+REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_RSVD_LEN                        , 38  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_RSVD_LEN );
+
+REG64_FLD( PEC_DBG_CBS_CC_RESET_EP                                 , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESET_EP   );
+REG64_FLD( PEC_DBG_CBS_CC_OPCG_IP                                  , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_OPCG_IP    );
+REG64_FLD( PEC_DBG_CBS_CC_VITL_CLKOFF                              , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_VITL_CLKOFF );
+REG64_FLD( PEC_DBG_CBS_CC_TEST_ENABLE                              , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TEST_ENABLE );
+REG64_FLD( PEC_DBG_CBS_CC_REQ                                      , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_REQ        );
+REG64_FLD( PEC_DBG_CBS_CC_CMD                                      , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CMD        );
+REG64_FLD( PEC_DBG_CBS_CC_CMD_LEN                                  , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CMD_LEN    );
+REG64_FLD( PEC_DBG_CBS_CC_STATE                                    , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATE      );
+REG64_FLD( PEC_DBG_CBS_CC_STATE_LEN                                , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STATE_LEN  );
+REG64_FLD( PEC_DBG_CBS_CC_SECURITY_DEBUG_MODE                      , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SECURITY_DEBUG_MODE );
+REG64_FLD( PEC_DBG_CBS_CC_PROTOCOL_ERROR                           , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PROTOCOL_ERROR );
+REG64_FLD( PEC_DBG_CBS_CC_PCB_IDLE                                 , 15  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PCB_IDLE   );
+REG64_FLD( PEC_DBG_CBS_CC_CURRENT_OPCG_MODE                        , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CURRENT_OPCG_MODE );
+REG64_FLD( PEC_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN                    , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CURRENT_OPCG_MODE_LEN );
+REG64_FLD( PEC_DBG_CBS_CC_LAST_OPCG_MODE                           , 20  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_LAST_OPCG_MODE );
+REG64_FLD( PEC_DBG_CBS_CC_LAST_OPCG_MODE_LEN                       , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_LAST_OPCG_MODE_LEN );
+REG64_FLD( PEC_DBG_CBS_CC_PCB_ERROR                                , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ERROR  );
+REG64_FLD( PEC_DBG_CBS_CC_PARITY_ERROR                             , 25  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ERROR );
+REG64_FLD( PEC_DBG_CBS_CC_ERROR                                    , 26  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ERROR      );
+REG64_FLD( PEC_DBG_CBS_CC_CHIPLET_IS_ALIGNED                       , 27  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_IS_ALIGNED );
+REG64_FLD( PEC_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET                  , 28  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PCB_REQUEST_SINCE_RESET );
+REG64_FLD( PEC_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE              , 29  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PARANOIA_TEST_ENABLE_CHANGE );
+REG64_FLD( PEC_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE              , 30  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE );
+REG64_FLD( PEC_DBG_CBS_CC_TP_TPFSI_ACK                             , 31  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TP_TPFSI_ACK );
+
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_A                  , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN              , 8   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_B                  , 8   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN              , 8   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_A                  , 16  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN              , 8   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_B                  , 24  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN              , 8   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C1_INAROW_MODE               , 32  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1            , 33  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1            , 34  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1           , 35  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_UNUSED                       , 36  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_UNUSED_LEN                   , 3   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C2_INAROW_MODE               , 39  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2            , 40  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2            , 41  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2           , 42  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_UNUSED_2                     , 43  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_UNUSED_2_LEN                 , 3   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET           , 46  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EXACT_TO_MODE                , 47  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1          , 48  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C3_ON_C0               , 49  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_SLOW_TO_MODE                 , 50  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO         , 51  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C1_COUNT_LT                  , 52  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN              , 4   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C2_COUNT_LT                  , 56  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN              , 4   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C3_SELECT              , 60  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN          , 3   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_A                  , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN              , 8   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_B                  , 8   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN              , 8   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_A                  , 16  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN              , 8   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_B                  , 24  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN              , 8   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C1_INAROW_MODE               , 32  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1            , 33  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1            , 34  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1           , 35  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_UNUSED                       , 36  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_UNUSED_LEN                   , 3   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C2_INAROW_MODE               , 39  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2            , 40  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2            , 41  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2           , 42  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_UNUSED_2                     , 43  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_UNUSED_2_LEN                 , 3   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET           , 46  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EXACT_TO_MODE                , 47  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1          , 48  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C3_ON_C0               , 49  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_SLOW_TO_MODE                 , 50  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO         , 51  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C1_COUNT_LT                  , 52  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN              , 4   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C2_COUNT_LT                  , 56  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN              , 4   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C3_SELECT              , 60  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN          , 3   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_A                  , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN              , 8   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_B                  , 8   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN              , 8   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_A                  , 16  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN              , 8   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_B                  , 24  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN              , 8   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C1_INAROW_MODE               , 32  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1            , 33  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1            , 34  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1           , 35  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_UNUSED                       , 36  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_UNUSED_LEN                   , 3   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C2_INAROW_MODE               , 39  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2            , 40  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2            , 41  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2           , 42  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_UNUSED_2                     , 43  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_UNUSED_2_LEN                 , 3   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET           , 46  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EXACT_TO_MODE                , 47  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1          , 48  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C3_ON_C0               , 49  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_SLOW_TO_MODE                 , 50  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO         , 51  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C1_COUNT_LT                  , 52  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN              , 4   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C2_COUNT_LT                  , 56  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN              , 4   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C3_SELECT              , 60  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN          , 3   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_A                    , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN                , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_B                    , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN                , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_A                    , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN                , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_B                    , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN                , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_C1_INAROW_MODE                 , 32  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1              , 33  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1              , 34  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1             , 35  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_UNUSED                         , 36  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_UNUSED_LEN                     , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_C2_INAROW_MODE                 , 39  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2              , 40  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2              , 41  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2             , 42  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_UNUSED_2                       , 43  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_UNUSED_2_LEN                   , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET             , 46  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_EXACT_TO_MODE                  , 47  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1            , 48  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C3_ON_C0                 , 49  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_SLOW_TO_MODE                   , 50  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO           , 51  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_C1_COUNT_LT                    , 52  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN                , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_C2_COUNT_LT                    , 56  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN                , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C3_SELECT                , 60  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN            , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_A                  , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN              , 8   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_B                  , 8   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN              , 8   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_A                  , 16  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN              , 8   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_B                  , 24  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN              , 8   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C1_INAROW_MODE               , 32  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1            , 33  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1            , 34  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1           , 35  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_UNUSED                       , 36  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_UNUSED_LEN                   , 3   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C2_INAROW_MODE               , 39  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2            , 40  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2            , 41  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2           , 42  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_UNUSED_2                     , 43  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_UNUSED_2_LEN                 , 3   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET           , 46  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EXACT_TO_MODE                , 47  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1          , 48  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C3_ON_C0               , 49  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_SLOW_TO_MODE                 , 50  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO         , 51  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C1_COUNT_LT                  , 52  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN              , 4   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C2_COUNT_LT                  , 56  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN              , 4   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C3_SELECT              , 60  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN          , 3   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A      , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B      , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A        , 10  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B        , 15  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_TO_CMP_LT                    , 20  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN                , 24  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_FORCE_TEST_MODE              , 44  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A      , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B      , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A        , 10  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B        , 15  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_TO_CMP_LT                    , 20  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN                , 24  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_FORCE_TEST_MODE              , 44  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A      , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B      , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A        , 10  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B        , 15  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_TO_CMP_LT                    , 20  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN                , 24  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_FORCE_TEST_MODE              , 44  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A        , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN    , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B        , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN    , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A          , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN      , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B          , 15  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN      , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( PEC_DBG_INST1_COND_REG_2_TO_CMP_LT                      , 20  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( PEC_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN                  , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( PEC_DBG_INST1_COND_REG_2_FORCE_TEST_MODE                , 44  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A      , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B      , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A        , 10  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B        , 15  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_TO_CMP_LT                    , 20  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN                , 24  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_FORCE_TEST_MODE              , 44  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_3_SP_COUNT_LT                  , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( PU_N3_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN              , 24  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_3_SP_COUNT_LT                  , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( PU_N1_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN              , 24  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_3_SP_COUNT_LT                  , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( PU_N2_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN              , 24  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( PEC_DBG_INST1_COND_REG_3_SP_COUNT_LT                    , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( PEC_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN                , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_3_SP_COUNT_LT                  , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( PU_N0_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN              , 24  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_A                  , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN              , 8   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_B                  , 8   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN              , 8   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_A                  , 16  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN              , 8   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_B                  , 24  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN              , 8   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C1_INAROW_MODE               , 32  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1            , 33  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1            , 34  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1           , 35  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_UNUSED                       , 36  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_UNUSED_LEN                   , 3   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C2_INAROW_MODE               , 39  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2            , 40  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2            , 41  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2           , 42  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_UNUSED_2                     , 43  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_UNUSED_2_LEN                 , 3   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET           , 46  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EXACT_TO_MODE                , 47  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1          , 48  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C3_ON_C0               , 49  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_SLOW_TO_MODE                 , 50  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO         , 51  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C1_COUNT_LT                  , 52  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN              , 4   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C2_COUNT_LT                  , 56  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN              , 4   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C3_SELECT              , 60  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN          , 3   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_A                  , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN              , 8   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_B                  , 8   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN              , 8   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_A                  , 16  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN              , 8   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_B                  , 24  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN              , 8   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C1_INAROW_MODE               , 32  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1            , 33  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1            , 34  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1           , 35  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_UNUSED                       , 36  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_UNUSED_LEN                   , 3   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C2_INAROW_MODE               , 39  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2            , 40  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2            , 41  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2           , 42  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_UNUSED_2                     , 43  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_UNUSED_2_LEN                 , 3   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET           , 46  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EXACT_TO_MODE                , 47  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1          , 48  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C3_ON_C0               , 49  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_SLOW_TO_MODE                 , 50  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO         , 51  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C1_COUNT_LT                  , 52  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN              , 4   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C2_COUNT_LT                  , 56  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN              , 4   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C3_SELECT              , 60  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN          , 3   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_A                  , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN              , 8   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_B                  , 8   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN              , 8   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_A                  , 16  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN              , 8   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_B                  , 24  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN              , 8   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C1_INAROW_MODE               , 32  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1            , 33  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1            , 34  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1           , 35  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_UNUSED                       , 36  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_UNUSED_LEN                   , 3   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C2_INAROW_MODE               , 39  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2            , 40  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2            , 41  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2           , 42  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_UNUSED_2                     , 43  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_UNUSED_2_LEN                 , 3   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET           , 46  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EXACT_TO_MODE                , 47  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1          , 48  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C3_ON_C0               , 49  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_SLOW_TO_MODE                 , 50  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO         , 51  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C1_COUNT_LT                  , 52  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN              , 4   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C2_COUNT_LT                  , 56  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN              , 4   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C3_SELECT              , 60  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN          , 3   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_A                    , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN                , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_B                    , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN                , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_A                    , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN                , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_B                    , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN                , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_C1_INAROW_MODE                 , 32  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1              , 33  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1              , 34  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1             , 35  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_UNUSED                         , 36  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_UNUSED_LEN                     , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_C2_INAROW_MODE                 , 39  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2              , 40  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2              , 41  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2             , 42  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_UNUSED_2                       , 43  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_UNUSED_2_LEN                   , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET             , 46  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_EXACT_TO_MODE                  , 47  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1            , 48  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C3_ON_C0                 , 49  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_SLOW_TO_MODE                   , 50  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO           , 51  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_C1_COUNT_LT                    , 52  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN                , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_C2_COUNT_LT                    , 56  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN                , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C3_SELECT                , 60  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN            , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_A                  , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN              , 8   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_B                  , 8   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN              , 8   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_A                  , 16  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN              , 8   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_B                  , 24  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN              , 8   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C1_INAROW_MODE               , 32  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1            , 33  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1            , 34  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1           , 35  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_UNUSED                       , 36  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_UNUSED_LEN                   , 3   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C2_INAROW_MODE               , 39  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2            , 40  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2            , 41  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2           , 42  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_UNUSED_2                     , 43  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_UNUSED_2_LEN                 , 3   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET           , 46  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EXACT_TO_MODE                , 47  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1          , 48  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C3_ON_C0               , 49  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_SLOW_TO_MODE                 , 50  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO         , 51  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C1_COUNT_LT                  , 52  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN              , 4   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C2_COUNT_LT                  , 56  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN              , 4   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C3_SELECT              , 60  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN          , 3   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A      , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B      , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A        , 10  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B        , 15  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_TO_CMP_LT                    , 20  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN                , 24  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_FORCE_TEST_MODE              , 44  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A      , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B      , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A        , 10  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B        , 15  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_TO_CMP_LT                    , 20  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN                , 24  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_FORCE_TEST_MODE              , 44  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A      , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B      , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A        , 10  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B        , 15  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_TO_CMP_LT                    , 20  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN                , 24  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_FORCE_TEST_MODE              , 44  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A        , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN    , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B        , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN    , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A          , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN      , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B          , 15  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN      , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( PEC_DBG_INST2_COND_REG_2_TO_CMP_LT                      , 20  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( PEC_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN                  , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( PEC_DBG_INST2_COND_REG_2_FORCE_TEST_MODE                , 44  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A      , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN  , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B      , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN  , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A        , 10  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN    , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B        , 15  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN    , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_TO_CMP_LT                    , 20  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN                , 24  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_FORCE_TEST_MODE              , 44  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_3_SP_COUNT_LT                  , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( PU_N3_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN              , 24  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_3_SP_COUNT_LT                  , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( PU_N1_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN              , 24  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_3_SP_COUNT_LT                  , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( PU_N2_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN              , 24  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( PEC_DBG_INST2_COND_REG_3_SP_COUNT_LT                    , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( PEC_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN                , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_3_SP_COUNT_LT                  , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( PU_N0_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN              , 24  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( PU_N3_DBG_MODE_REG_GLB_BRCST                            , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST  );
+REG64_FLD( PU_N3_DBG_MODE_REG_GLB_BRCST_LEN                        , 3   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST_LEN );
+REG64_FLD( PU_N3_DBG_MODE_REG_TRACE_SEL                            , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SEL  );
+REG64_FLD( PU_N3_DBG_MODE_REG_TRIG_SEL                             , 7   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG_SEL   );
+REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION              , 8   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_XSTOP_SELECTION );
+REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION          , 9   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_RECOV_ERR_SELECTION );
+REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION             , 10  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_SPATTN_SELECTION );
+REG64_FLD( PU_N3_DBG_MODE_REG_FREEZE_SEL                           , 11  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_SEL );
+
+REG64_FLD( PU_N1_DBG_MODE_REG_GLB_BRCST                            , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST  );
+REG64_FLD( PU_N1_DBG_MODE_REG_GLB_BRCST_LEN                        , 3   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST_LEN );
+REG64_FLD( PU_N1_DBG_MODE_REG_TRACE_SEL                            , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SEL  );
+REG64_FLD( PU_N1_DBG_MODE_REG_TRIG_SEL                             , 7   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG_SEL   );
+REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION              , 8   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_XSTOP_SELECTION );
+REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION          , 9   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_RECOV_ERR_SELECTION );
+REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION             , 10  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_SPATTN_SELECTION );
+REG64_FLD( PU_N1_DBG_MODE_REG_FREEZE_SEL                           , 11  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_SEL );
+
+REG64_FLD( PU_N2_DBG_MODE_REG_GLB_BRCST                            , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST  );
+REG64_FLD( PU_N2_DBG_MODE_REG_GLB_BRCST_LEN                        , 3   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST_LEN );
+REG64_FLD( PU_N2_DBG_MODE_REG_TRACE_SEL                            , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SEL  );
+REG64_FLD( PU_N2_DBG_MODE_REG_TRIG_SEL                             , 7   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG_SEL   );
+REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION              , 8   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_XSTOP_SELECTION );
+REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION          , 9   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_RECOV_ERR_SELECTION );
+REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION             , 10  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_SPATTN_SELECTION );
+REG64_FLD( PU_N2_DBG_MODE_REG_FREEZE_SEL                           , 11  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_SEL );
+
+REG64_FLD( PEC_DBG_MODE_REG_GLB_BRCST                              , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST  );
+REG64_FLD( PEC_DBG_MODE_REG_GLB_BRCST_LEN                          , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST_LEN );
+REG64_FLD( PEC_DBG_MODE_REG_TRACE_SEL                              , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SEL  );
+REG64_FLD( PEC_DBG_MODE_REG_TRIG_SEL                               , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG_SEL   );
+REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION                , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_XSTOP_SELECTION );
+REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION            , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_RECOV_ERR_SELECTION );
+REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION               , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_SPATTN_SELECTION );
+REG64_FLD( PEC_DBG_MODE_REG_FREEZE_SEL                             , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_SEL );
+
+REG64_FLD( PU_N0_DBG_MODE_REG_GLB_BRCST                            , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST  );
+REG64_FLD( PU_N0_DBG_MODE_REG_GLB_BRCST_LEN                        , 3   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST_LEN );
+REG64_FLD( PU_N0_DBG_MODE_REG_TRACE_SEL                            , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SEL  );
+REG64_FLD( PU_N0_DBG_MODE_REG_TRIG_SEL                             , 7   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG_SEL   );
+REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION              , 8   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_XSTOP_SELECTION );
+REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION          , 9   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_RECOV_ERR_SELECTION );
+REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION             , 10  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_SPATTN_SELECTION );
+REG64_FLD( PU_N0_DBG_MODE_REG_FREEZE_SEL                           , 11  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_SEL );
+
+REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE     , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE );
+REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_IMM_FREEZE                   , 16  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_IMM_FREEZE );
+REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_STOP_ON_ERR                  , 17  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_ERR );
+REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH           , 18  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_BANK_ON_RUNN_MATCH );
+REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_FORCE_TEST                   , 19  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST );
+REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_ACCUM_HIST                   , 20  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUM_HIST );
+REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ             , 21  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_FRZ_COUNT_ON_FRZ );
+
+REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE     , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE );
+REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_IMM_FREEZE                   , 16  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_IMM_FREEZE );
+REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_STOP_ON_ERR                  , 17  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_ERR );
+REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH           , 18  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_BANK_ON_RUNN_MATCH );
+REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_FORCE_TEST                   , 19  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST );
+REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_ACCUM_HIST                   , 20  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUM_HIST );
+REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ             , 21  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_FRZ_COUNT_ON_FRZ );
+
+REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE     , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE );
+REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_IMM_FREEZE                   , 16  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_IMM_FREEZE );
+REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_STOP_ON_ERR                  , 17  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_ERR );
+REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH           , 18  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_BANK_ON_RUNN_MATCH );
+REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_FORCE_TEST                   , 19  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST );
+REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_ACCUM_HIST                   , 20  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUM_HIST );
+REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ             , 21  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_FRZ_COUNT_ON_FRZ );
+
+REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE       , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE );
+REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN   , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN );
+REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_IMM_FREEZE                     , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IMM_FREEZE );
+REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_STOP_ON_ERR                    , 17  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_ERR );
+REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH             , 18  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_BANK_ON_RUNN_MATCH );
+REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_FORCE_TEST                     , 19  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST );
+REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_ACCUM_HIST                     , 20  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUM_HIST );
+REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ               , 21  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FRZ_COUNT_ON_FRZ );
+
+REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE     , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE );
+REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_IMM_FREEZE                   , 16  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_IMM_FREEZE );
+REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_STOP_ON_ERR                  , 17  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_ERR );
+REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH           , 18  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_BANK_ON_RUNN_MATCH );
+REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_FORCE_TEST                   , 19  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST );
+REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_ACCUM_HIST                   , 20  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUM_HIST );
+REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ             , 21  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_FRZ_COUNT_ON_FRZ );
+
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_COND3_ENABLE                , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_COND3_ENABLE );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_COND3_ENABLE                , 1   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_COND3_ENABLE );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST3_COND3_ENABLE                , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST3_COND3_ENABLE );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST4_COND3_ENABLE                , 3   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST4_COND3_ENABLE );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE              , 4   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_SLOW_LFSR_MODE );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE              , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_SLOW_LFSR_MODE );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE              , 6   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST3_SLOW_LFSR_MODE );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE              , 7   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST4_SLOW_LFSR_MODE );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL         , 8   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL         , 10  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL         , 12  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL         , 14  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL         , 16  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL         , 18  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP                  , 32  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_STOP );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE                , 33  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_FREEZE );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL                , 34  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN            , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL                , 39  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN            , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_PC_TP_TRIG_SEL                    , 44  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN                , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_ARM_SEL                           , 46  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL    );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_ARM_SEL_LEN                       , 4   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL                   , 50  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN               , 4   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL                   , 54  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL );
+REG64_FLD( PU_N3_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN               , 4   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL_LEN );
+
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_COND3_ENABLE                , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_COND3_ENABLE );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_COND3_ENABLE                , 1   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_COND3_ENABLE );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST3_COND3_ENABLE                , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST3_COND3_ENABLE );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST4_COND3_ENABLE                , 3   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST4_COND3_ENABLE );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE              , 4   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_SLOW_LFSR_MODE );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE              , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_SLOW_LFSR_MODE );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE              , 6   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST3_SLOW_LFSR_MODE );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE              , 7   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST4_SLOW_LFSR_MODE );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL         , 8   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL         , 10  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL         , 12  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL         , 14  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL         , 16  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL         , 18  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP                  , 32  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_STOP );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE                , 33  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_FREEZE );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL                , 34  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN            , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL                , 39  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN            , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL                    , 44  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN                , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_ARM_SEL                           , 46  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL    );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_ARM_SEL_LEN                       , 4   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL                   , 50  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN               , 4   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL                   , 54  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL );
+REG64_FLD( PU_N1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN               , 4   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL_LEN );
+
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_COND3_ENABLE                , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_COND3_ENABLE );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_COND3_ENABLE                , 1   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_COND3_ENABLE );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST3_COND3_ENABLE                , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST3_COND3_ENABLE );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST4_COND3_ENABLE                , 3   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST4_COND3_ENABLE );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE              , 4   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_SLOW_LFSR_MODE );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE              , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_SLOW_LFSR_MODE );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE              , 6   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST3_SLOW_LFSR_MODE );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE              , 7   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST4_SLOW_LFSR_MODE );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL         , 8   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL         , 10  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL         , 12  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL         , 14  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL         , 16  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL         , 18  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP                  , 32  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_STOP );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE                , 33  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_FREEZE );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL                , 34  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN            , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL                , 39  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN            , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_PC_TP_TRIG_SEL                    , 44  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN                , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_ARM_SEL                           , 46  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL    );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_ARM_SEL_LEN                       , 4   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL                   , 50  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN               , 4   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL                   , 54  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL );
+REG64_FLD( PU_N2_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN               , 4   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL_LEN );
+
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_COND3_ENABLE                  , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_COND3_ENABLE );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_COND3_ENABLE                  , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_COND3_ENABLE );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST3_COND3_ENABLE                  , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST3_COND3_ENABLE );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST4_COND3_ENABLE                  , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST4_COND3_ENABLE );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE                , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_SLOW_LFSR_MODE );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE                , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_SLOW_LFSR_MODE );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE                , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST3_SLOW_LFSR_MODE );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE                , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST4_SLOW_LFSR_MODE );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL           , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN       , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL           , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN       , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL           , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN       , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL           , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN       , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL           , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN       , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL           , 18  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN       , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP                    , 32  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_STOP );
+REG64_FLD( PEC_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE                  , 33  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_FREEZE );
+REG64_FLD( PEC_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL                  , 34  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL );
+REG64_FLD( PEC_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN              , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL                  , 39  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL );
+REG64_FLD( PEC_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN              , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_0_PC_TP_TRIG_SEL                      , 44  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL );
+REG64_FLD( PEC_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN                  , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_0_ARM_SEL                             , 46  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL    );
+REG64_FLD( PEC_DBG_TRACE_REG_0_ARM_SEL_LEN                         , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL                     , 50  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL );
+REG64_FLD( PEC_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN                 , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL                     , 54  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL );
+REG64_FLD( PEC_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN                 , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL_LEN );
+
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_COND3_ENABLE                , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_COND3_ENABLE );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_COND3_ENABLE                , 1   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_COND3_ENABLE );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST3_COND3_ENABLE                , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST3_COND3_ENABLE );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST4_COND3_ENABLE                , 3   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST4_COND3_ENABLE );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE              , 4   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_SLOW_LFSR_MODE );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE              , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_SLOW_LFSR_MODE );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE              , 6   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST3_SLOW_LFSR_MODE );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE              , 7   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST4_SLOW_LFSR_MODE );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL         , 8   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL         , 10  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL         , 12  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL         , 14  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL         , 16  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL         , 18  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN     , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP                  , 32  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_STOP );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE                , 33  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_FREEZE );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL                , 34  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN            , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL                , 39  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN            , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL                    , 44  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN                , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_ARM_SEL                           , 46  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL    );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_ARM_SEL_LEN                       , 4   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL                   , 50  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN               , 4   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL                   , 54  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL );
+REG64_FLD( PU_N0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN               , 4   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL_LEN );
+
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO        , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN    , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO        , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN    , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO        , 4   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN    , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO        , 6   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN    , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO        , 8   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN    , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO        , 10  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN    , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN     , 24  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_WAITN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN     , 25  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_WAITN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN     , 26  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN     , 27  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_WAITN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN     , 28  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_WAITN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN     , 29  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK      , 36  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_BANK );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK      , 37  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_BANK );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK      , 38  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK      , 39  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_BANK );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK      , 40  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_BANK );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK      , 41  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT           , 48  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN       , 3   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR     , 51  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT           , 52  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN       , 3   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR     , 55  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR );
+
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO        , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN    , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO        , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN    , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO        , 4   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN    , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO        , 6   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN    , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO        , 8   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN    , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO        , 10  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN    , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN     , 24  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_WAITN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN     , 25  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_WAITN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN     , 26  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN     , 27  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_WAITN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN     , 28  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_WAITN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN     , 29  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK      , 36  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_BANK );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK      , 37  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_BANK );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK      , 38  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK      , 39  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_BANK );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK      , 40  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_BANK );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK      , 41  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT           , 48  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN       , 3   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR     , 51  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT           , 52  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN       , 3   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR     , 55  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR );
+
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO        , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN    , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO        , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN    , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO        , 4   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN    , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO        , 6   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN    , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO        , 8   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN    , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO        , 10  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN    , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN     , 24  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_WAITN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN     , 25  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_WAITN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN     , 26  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN     , 27  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_WAITN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN     , 28  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_WAITN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN     , 29  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK      , 36  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_BANK );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK      , 37  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_BANK );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK      , 38  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK      , 39  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_BANK );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK      , 40  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_BANK );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK      , 41  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT           , 48  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN       , 3   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR     , 51  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT           , 52  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN       , 3   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR     , 55  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR );
+
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO          , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN      , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO          , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN      , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO          , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN      , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO          , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN      , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO          , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN      , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO          , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN      , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN       , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_WAITN );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN       , 25  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_WAITN );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN       , 26  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN       , 27  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_WAITN );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN       , 28  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_WAITN );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN       , 29  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK        , 36  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_BANK );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK        , 37  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_BANK );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK        , 38  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK        , 39  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_BANK );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK        , 40  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_BANK );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK        , 41  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT             , 48  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN         , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR       , 51  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT             , 52  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN         , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR       , 55  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR );
+
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO        , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN    , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO        , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN    , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO        , 4   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN    , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO        , 6   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN    , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO        , 8   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN    , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO        , 10  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN    , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN     , 24  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_WAITN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN     , 25  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_WAITN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN     , 26  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN     , 27  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_WAITN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN     , 28  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_WAITN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN     , 29  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK      , 36  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_BANK );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK      , 37  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_BANK );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK      , 38  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK      , 39  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_BANK );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK      , 40  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_BANK );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK      , 41  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT           , 48  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN       , 3   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR     , 51  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT           , 52  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN       , 3   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR     , 55  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR );
+
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD0                         , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD0_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD1                         , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD1_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD2                         , 10  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD2_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD3                         , 15  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD3_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD4                         , 20  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD4_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD5                         , 25  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD5_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD6                         , 30  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD6_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD7                         , 35  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD7_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD8                         , 40  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD8_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD9                         , 45  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD9_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD10                        , 50  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD10_LEN                    , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_RESERVED1                    , 55  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_RESERVED1_LEN                , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_ACT                          , 63  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD0                         , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD0_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD1                         , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD1_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD2                         , 10  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD2_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD3                         , 15  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD3_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD4                         , 20  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD4_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD5                         , 25  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD5_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD6                         , 30  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD6_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD7                         , 35  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD7_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD8                         , 40  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD8_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD9                         , 45  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD9_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD10                        , 50  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD10_LEN                    , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_RESERVED1                    , 55  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_RESERVED1_LEN                , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_ACT                          , 63  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD0                           , 0   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD0_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD1                           , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD1_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD2                           , 10  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD2_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD3                           , 15  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD3_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD4                           , 20  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD4_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD5                           , 25  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD5_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD6                           , 30  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD6_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD7                           , 35  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD7_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD8                           , 40  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD8_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD9                           , 45  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD9_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD10                          , 50  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD10_LEN                      , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_RESERVED1                      , 55  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_RESERVED1_LEN                  , 8   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_ACT                            , 63  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD0                          , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD0_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD1                          , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD1_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD2                          , 10  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD2_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD3                          , 15  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD3_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD4                          , 20  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD4_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD5                          , 25  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD5_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD6                          , 30  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD6_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD7                          , 35  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD7_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD8                          , 40  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD8_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD9                          , 45  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD9_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD10                         , 50  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD10_LEN                     , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_RESERVED1                     , 55  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_ACT                           , 63  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD0                          , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD0_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD1                          , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD1_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD2                          , 10  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD2_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD3                          , 15  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD3_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD4                          , 20  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD4_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD5                          , 25  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD5_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD6                          , 30  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD6_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD7                          , 35  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD7_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD8                          , 40  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD8_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD9                          , 45  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD9_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD10                         , 50  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD10_LEN                     , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_RESERVED1                     , 55  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_ACT                           , 63  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( NV_DEBUG0_CONFIG_POD0                                   , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( NV_DEBUG0_CONFIG_POD0_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( NV_DEBUG0_CONFIG_POD1                                   , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( NV_DEBUG0_CONFIG_POD1_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( NV_DEBUG0_CONFIG_POD2                                   , 10  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( NV_DEBUG0_CONFIG_POD2_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( NV_DEBUG0_CONFIG_POD3                                   , 15  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( NV_DEBUG0_CONFIG_POD3_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( NV_DEBUG0_CONFIG_POD4                                   , 20  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( NV_DEBUG0_CONFIG_POD4_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( NV_DEBUG0_CONFIG_POD5                                   , 25  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( NV_DEBUG0_CONFIG_POD5_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( NV_DEBUG0_CONFIG_POD6                                   , 30  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( NV_DEBUG0_CONFIG_POD6_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( NV_DEBUG0_CONFIG_POD7                                   , 35  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( NV_DEBUG0_CONFIG_POD7_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( NV_DEBUG0_CONFIG_POD8                                   , 40  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( NV_DEBUG0_CONFIG_POD8_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( NV_DEBUG0_CONFIG_POD9                                   , 45  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( NV_DEBUG0_CONFIG_POD9_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( NV_DEBUG0_CONFIG_POD10                                  , 50  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( NV_DEBUG0_CONFIG_POD10_LEN                              , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( NV_DEBUG0_CONFIG_RESERVED1                              , 55  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( NV_DEBUG0_CONFIG_RESERVED1_LEN                          , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( NV_DEBUG0_CONFIG_ACT                                    , 63  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD0                          , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD0_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD1                          , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD1_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD2                          , 10  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD2_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD3                          , 15  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD3_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD4                          , 20  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD4_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD5                          , 25  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD5_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD6                          , 30  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD6_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD7                          , 35  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD7_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD8                          , 40  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD8_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD9                          , 45  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD9_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD10                         , 50  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD10_LEN                     , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_RESERVED1                     , 55  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_ACT                           , 63  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD0                          , 0   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD0_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD1                          , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD1_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD2                          , 10  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD2_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD3                          , 15  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD3_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD4                          , 20  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD4_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD5                          , 25  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD5_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD6                          , 30  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD6_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD7                          , 35  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD7_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD8                          , 40  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD8_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD9                          , 45  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD9_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD10                         , 50  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD10_LEN                     , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1                     , 55  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_ACT                           , 63  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD0                          , 0   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD0_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD1                          , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD1_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD2                          , 10  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD2_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD3                          , 15  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD3_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD4                          , 20  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD4_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD5                          , 25  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD5_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD6                          , 30  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD6_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD7                          , 35  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD7_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD8                          , 40  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD8_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD9                          , 45  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD9_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD10                         , 50  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD10_LEN                     , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1                     , 55  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_ACT                           , 63  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD0                          , 0   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD0_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD1                          , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD1_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD2                          , 10  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD2_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD3                          , 15  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD3_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD4                          , 20  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD4_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD5                          , 25  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD5_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD6                          , 30  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD6_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD7                          , 35  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD7_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD8                          , 40  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD8_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD9                          , 45  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD9_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD10                         , 50  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD10_LEN                     , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_RESERVED1                     , 55  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_RESERVED1_LEN                 , 8   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_ACT                           , 63  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD0                         , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD0_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD1                         , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD1_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD2                         , 10  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD2_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD3                         , 15  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD3_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD4                         , 20  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD4_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD5                         , 25  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD5_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD6                         , 30  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD6_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD7                         , 35  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD7_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD8                         , 40  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD8_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD9                         , 45  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD9_LEN                     , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD10                        , 50  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD10_LEN                    , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_RESERVED1                    , 55  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_RESERVED1_LEN                , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_ACT                          , 63  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD0                         , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD0_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD1                         , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD1_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD2                         , 10  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD2_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD3                         , 15  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD3_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD4                         , 20  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD4_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD5                         , 25  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD5_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD6                         , 30  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD6_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD7                         , 35  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD7_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD8                         , 40  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD8_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD9                         , 45  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD9_LEN                     , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD10                        , 50  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD10_LEN                    , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_RESERVED1                    , 55  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_RESERVED1_LEN                , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_ACT                          , 63  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD0                           , 0   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD0_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD1                           , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD1_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD2                           , 10  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD2_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD3                           , 15  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD3_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD4                           , 20  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD4_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD5                           , 25  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD5_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD6                           , 30  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD6_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD7                           , 35  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD7_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD8                           , 40  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD8_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD9                           , 45  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD9_LEN                       , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD10                          , 50  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD10_LEN                      , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_RESERVED1                      , 55  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_RESERVED1_LEN                  , 8   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_ACT                            , 63  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD0                          , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD0_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD1                          , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD1_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD2                          , 10  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD2_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD3                          , 15  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD3_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD4                          , 20  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD4_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD5                          , 25  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD5_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD6                          , 30  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD6_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD7                          , 35  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD7_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD8                          , 40  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD8_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD9                          , 45  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD9_LEN                      , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD10                         , 50  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD10_LEN                     , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_RESERVED1                     , 55  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_ACT                           , 63  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD0                          , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD0_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD1                          , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD1_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD2                          , 10  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD2_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD3                          , 15  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD3_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD4                          , 20  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD4_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD5                          , 25  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD5_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD6                          , 30  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD6_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD7                          , 35  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD7_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD8                          , 40  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD8_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD9                          , 45  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD9_LEN                      , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD10                         , 50  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD10_LEN                     , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_RESERVED1                     , 55  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_ACT                           , 63  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( NV_DEBUG1_CONFIG_POD0                                   , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( NV_DEBUG1_CONFIG_POD0_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( NV_DEBUG1_CONFIG_POD1                                   , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( NV_DEBUG1_CONFIG_POD1_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( NV_DEBUG1_CONFIG_POD2                                   , 10  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( NV_DEBUG1_CONFIG_POD2_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( NV_DEBUG1_CONFIG_POD3                                   , 15  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( NV_DEBUG1_CONFIG_POD3_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( NV_DEBUG1_CONFIG_POD4                                   , 20  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( NV_DEBUG1_CONFIG_POD4_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( NV_DEBUG1_CONFIG_POD5                                   , 25  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( NV_DEBUG1_CONFIG_POD5_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( NV_DEBUG1_CONFIG_POD6                                   , 30  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( NV_DEBUG1_CONFIG_POD6_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( NV_DEBUG1_CONFIG_POD7                                   , 35  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( NV_DEBUG1_CONFIG_POD7_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( NV_DEBUG1_CONFIG_POD8                                   , 40  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( NV_DEBUG1_CONFIG_POD8_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( NV_DEBUG1_CONFIG_POD9                                   , 45  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( NV_DEBUG1_CONFIG_POD9_LEN                               , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( NV_DEBUG1_CONFIG_POD10                                  , 50  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( NV_DEBUG1_CONFIG_POD10_LEN                              , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( NV_DEBUG1_CONFIG_RESERVED1                              , 55  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( NV_DEBUG1_CONFIG_RESERVED1_LEN                          , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( NV_DEBUG1_CONFIG_ACT                                    , 63  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD0                          , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD0_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD1                          , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD1_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD2                          , 10  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD2_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD3                          , 15  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD3_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD4                          , 20  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD4_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD5                          , 25  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD5_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD6                          , 30  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD6_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD7                          , 35  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD7_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD8                          , 40  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD8_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD9                          , 45  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD9_LEN                      , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD10                         , 50  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD10_LEN                     , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_RESERVED1                     , 55  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_ACT                           , 63  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD0                          , 0   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD0_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD1                          , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD1_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD2                          , 10  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD2_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD3                          , 15  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD3_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD4                          , 20  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD4_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD5                          , 25  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD5_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD6                          , 30  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD6_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD7                          , 35  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD7_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD8                          , 40  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD8_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD9                          , 45  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD9_LEN                      , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD10                         , 50  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD10_LEN                     , 5   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1                     , 55  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_ACT                           , 63  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD0                          , 0   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD0_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD1                          , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD1_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD2                          , 10  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD2_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD3                          , 15  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD3_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD4                          , 20  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD4_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD5                          , 25  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD5_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD6                          , 30  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD6_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD7                          , 35  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD7_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD8                          , 40  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD8_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD9                          , 45  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD9_LEN                      , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD10                         , 50  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD10_LEN                     , 5   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1                     , 55  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_ACT                           , 63  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD0                          , 0   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD0       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD0_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD0_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD1                          , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD1       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD1_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD1_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD2                          , 10  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD2       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD2_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD2_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD3                          , 15  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD3       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD3_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD3_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD4                          , 20  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD4       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD4_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD4_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD5                          , 25  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD5       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD5_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD5_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD6                          , 30  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD6       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD6_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD6_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD7                          , 35  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD7       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD7_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD7_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD8                          , 40  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD8       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD8_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD8_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD9                          , 45  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD9       );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD9_LEN                      , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD9_LEN   );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD10                         , 50  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD10      );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD10_LEN                     , 5   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_POD10_LEN  );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_RESERVED1                     , 55  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_RESERVED1_LEN                 , 8   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_ACT                           , 63  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE0                  , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE0 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE0_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE0_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE1                  , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE1 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE1_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE1_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE2                  , 4   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE2 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE2_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE2_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE3                  , 6   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE3 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE3_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE3_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE4                  , 8   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE4 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE4_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE4_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE5                  , 10  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE5 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE5_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE5_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE6                  , 12  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE6 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE6_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE6_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE7                  , 14  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE7 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE7_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE7_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE8                  , 16  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE8 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE8_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE8_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE9                  , 18  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE9 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE9_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE9_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE10                 , 20  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE10 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE10_LEN             , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS0BYTE10_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE0                  , 22  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE0 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE0_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE0_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE1                  , 24  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE1 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE1_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE1_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE2                  , 26  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE2 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE2_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE2_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE3                  , 28  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE3 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE3_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE3_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE4                  , 30  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE4 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE4_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE4_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE5                  , 32  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE5 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE5_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE5_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE6                  , 34  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE6 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE6_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE6_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE7                  , 36  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE7 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE7_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE7_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE8                  , 38  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE8 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE8_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE8_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE9                  , 40  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE9 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE9_LEN              , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE9_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE10                 , 42  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE10 );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE10_LEN             , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_BUS1BYTE10_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_RESERVED                        , 44  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_RESERVED_LEN                    , 19  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_ACT                             , 63  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_MUX_PORT_SEL                   , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BLOCK_MUX_PORT_SEL );
+REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_MUX_PORT_SEL_LEN               , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BLOCK_MUX_PORT_SEL_LEN );
+REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_SEL                            , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BLOCK_SEL  );
+REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_SEL_LEN                        , 8   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BLOCK_SEL_LEN );
+
+REG64_FLD( CAPP_DFSUOP1_WORD                                       , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_WORD       );
+REG64_FLD( CAPP_DFSUOP1_WORD_LEN                                   , 56  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_WORD_LEN   );
+
+REG64_FLD( PU_DISABLE_FORCE_PFET_OFF_REG                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REG        );
+REG64_FLD( PU_DISABLE_FORCE_PFET_OFF_REG_LEN                       , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REG_LEN    );
+REG64_FLD( PU_DISABLE_FORCE_PFET_OFF_RESERVED                      , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_DISABLE_FORCE_PFET_OFF_RESERVED_LEN                  , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU_SM1_DMA_SYNC_START_READ                          , 0   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_START_READ );
+REG64_FLD( PU_NPU_SM1_DMA_SYNC_READ_COMPLETE                       , 1   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_READ_COMPLETE );
+REG64_FLD( PU_NPU_SM1_DMA_SYNC_START_WRITE                         , 2   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_START_WRITE );
+REG64_FLD( PU_NPU_SM1_DMA_SYNC_WRITE_COMPLETE                      , 3   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_WRITE_COMPLETE );
+
+REG64_FLD( PU_DMA_UP_ADDR_BASE_UPPER_BITS                          , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BASE_UPPER_BITS );
+REG64_FLD( PU_DMA_UP_ADDR_BASE_UPPER_BITS_LEN                      , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BASE_UPPER_BITS_LEN );
+REG64_FLD( PU_DMA_UP_ADDR_ESCAPE_ADDRESS                           , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ESCAPE_ADDRESS );
+REG64_FLD( PU_DMA_UP_ADDR_ESCAPE_ADDRESS_LEN                       , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ESCAPE_ADDRESS_LEN );
+
+REG64_FLD( PU_DMA_VAS_MMIO_BAR_BAR                                 , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BAR        );
+REG64_FLD( PU_DMA_VAS_MMIO_BAR_BAR_LEN                             , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BAR_LEN    );
+
+REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPRIORITYMASK                   , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DROPPRIORITYMASK );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPRIORITYMASK_LEN               , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DROPPRIORITYMASK_LEN );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_ENABLE_CTAG_DROP_PRIORITY          , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ENABLE_CTAG_DROP_PRIORITY );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_ENABLE_IO_CMD_PACING               , 7   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ENABLE_IO_CMD_PACING );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPACECOUNT                      , 8   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DROPPACECOUNT );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPACECOUNT_LEN                  , 9   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DROPPACECOUNT_LEN );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPACEINC                        , 17  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DROPPACEINC );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPACEINC_LEN                    , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DROPPACEINC_LEN );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_RTYDROPDIVIDER                     , 23  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_RTYDROPDIVIDER );
+REG64_FLD( PEC_DRPPRICTL_REG_PE_RTYDROPDIVIDER_LEN                 , 3   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_RTYDROPDIVIDER_LEN );
+
+REG64_FLD( PEC_DTS_RESULT0_0_RESULT                                , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_0_RESULT   );
+REG64_FLD( PEC_DTS_RESULT0_0_RESULT_LEN                            , 16  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_0_RESULT_LEN );
+REG64_FLD( PEC_DTS_RESULT0_1_RESULT                                , 16  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_RESULT   );
+REG64_FLD( PEC_DTS_RESULT0_1_RESULT_LEN                            , 16  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_RESULT_LEN );
+
+REG64_FLD( PEC_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE              , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMESTAMP_COUNTER_VALUE );
+REG64_FLD( PEC_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN          , 44  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN );
+REG64_FLD( PEC_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR       , 44  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR );
+REG64_FLD( PEC_DTS_TRC_RESULT_1                                    , 48  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_1          );
+REG64_FLD( PEC_DTS_TRC_RESULT_1_LEN                                , 16  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_LEN      );
+
+REG64_FLD( PU_NPU0_ECC_CONFIG_PBTX_AMO_IGNORE_XUE                  , 0   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_AMO_IGNORE_XUE );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_BR_PERR                      , 1   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_BR_PERR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_IR_PERR                      , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_IR_PERR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_OR_PERR                      , 3   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_OR_PERR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_PT                          , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_CORR_DIS_PT );
+REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_PR                          , 5   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_CORR_DIS_PR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_BR                          , 6   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_CORR_DIS_BR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_IR                          , 7   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_CORR_DIS_IR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_OR                          , 8   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_CORR_DIS_OR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_PT                           , 9   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_PT );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_PR                           , 10  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_PR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_BR                           , 11  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_BR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_IR                           , 12  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_IR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_OR                           , 13  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_OR );
+REG64_FLD( PU_NPU0_ECC_CONFIG_RESERVED                             , 14  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU0_ECC_CONFIG_RESERVED_LEN                         , 18  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU1_ECC_CONFIG_PBTX_AMO_IGNORE_XUE                  , 0   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_AMO_IGNORE_XUE );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_BR_PERR                      , 1   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_BR_PERR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_IR_PERR                      , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_IR_PERR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_OR_PERR                      , 3   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_OR_PERR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_PT                          , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_CORR_DIS_PT );
+REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_PR                          , 5   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_CORR_DIS_PR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_BR                          , 6   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_CORR_DIS_BR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_IR                          , 7   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_CORR_DIS_IR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_OR                          , 8   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_CORR_DIS_OR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_PT                           , 9   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_PT );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_PR                           , 10  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_PR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_BR                           , 11  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_BR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_IR                           , 12  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_IR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_OR                           , 13  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_OR );
+REG64_FLD( PU_NPU1_ECC_CONFIG_RESERVED                             , 14  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU1_ECC_CONFIG_RESERVED_LEN                         , 18  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU2_ECC_CONFIG_PBTX_AMO_IGNORE_XUE                  , 0   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_PBTX_AMO_IGNORE_XUE );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_BR_PERR                      , 1   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_BR_PERR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_IR_PERR                      , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_IR_PERR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_OR_PERR                      , 3   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_OR_PERR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_PT                          , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_CORR_DIS_PT );
+REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_PR                          , 5   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_CORR_DIS_PR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_BR                          , 6   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_CORR_DIS_BR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_IR                          , 7   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_CORR_DIS_IR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_OR                          , 8   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_CORR_DIS_OR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_PT                           , 9   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_PT );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_PR                           , 10  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_PR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_BR                           , 11  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_BR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_IR                           , 12  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_IR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_OR                           , 13  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_SUE_DIS_OR );
+REG64_FLD( PU_NPU2_ECC_CONFIG_RESERVED                             , 14  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_ECC_CONFIG_RESERVED_LEN                         , 18  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART0_REGISTER_PART_0                   , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_0     );
+REG64_FLD( PU_OTPROM0_ECID_PART0_REGISTER_PART_0_LEN               , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_0_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART0_REGISTER_PART_0                   , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_0     );
+REG64_FLD( PU_OTPROM1_ECID_PART0_REGISTER_PART_0_LEN               , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_0_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART10_REGISTER_PART_10                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_10    );
+REG64_FLD( PU_OTPROM0_ECID_PART10_REGISTER_PART_10_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_10_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART10_REGISTER_PART_10                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_10    );
+REG64_FLD( PU_OTPROM1_ECID_PART10_REGISTER_PART_10_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_10_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART11_REGISTER_PART_11                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_11    );
+REG64_FLD( PU_OTPROM0_ECID_PART11_REGISTER_PART_11_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_11_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART11_REGISTER_PART_11                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_11    );
+REG64_FLD( PU_OTPROM1_ECID_PART11_REGISTER_PART_11_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_11_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART12_REGISTER_PART_12                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_12    );
+REG64_FLD( PU_OTPROM0_ECID_PART12_REGISTER_PART_12_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_12_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART12_REGISTER_PART_12                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_12    );
+REG64_FLD( PU_OTPROM1_ECID_PART12_REGISTER_PART_12_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_12_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART13_REGISTER_PART_13                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_13    );
+REG64_FLD( PU_OTPROM0_ECID_PART13_REGISTER_PART_13_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_13_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART13_REGISTER_PART_13                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_13    );
+REG64_FLD( PU_OTPROM1_ECID_PART13_REGISTER_PART_13_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_13_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART14_REGISTER_PART_14                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_14    );
+REG64_FLD( PU_OTPROM0_ECID_PART14_REGISTER_PART_14_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_14_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART14_REGISTER_PART_14                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_14    );
+REG64_FLD( PU_OTPROM1_ECID_PART14_REGISTER_PART_14_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_14_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART15_REGISTER_PART_15                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_15    );
+REG64_FLD( PU_OTPROM0_ECID_PART15_REGISTER_PART_15_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_15_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART15_REGISTER_PART_15                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_15    );
+REG64_FLD( PU_OTPROM1_ECID_PART15_REGISTER_PART_15_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_15_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART16_REGISTER_PART_16                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_16    );
+REG64_FLD( PU_OTPROM0_ECID_PART16_REGISTER_PART_16_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_16_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART16_REGISTER_PART_16                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_16    );
+REG64_FLD( PU_OTPROM1_ECID_PART16_REGISTER_PART_16_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_16_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART17_REGISTER_PART_17                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_17    );
+REG64_FLD( PU_OTPROM0_ECID_PART17_REGISTER_PART_17_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_17_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART17_REGISTER_PART_17                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_17    );
+REG64_FLD( PU_OTPROM1_ECID_PART17_REGISTER_PART_17_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_17_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART18_REGISTER_PART_18                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_18    );
+REG64_FLD( PU_OTPROM0_ECID_PART18_REGISTER_PART_18_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_18_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART18_REGISTER_PART_18                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_18    );
+REG64_FLD( PU_OTPROM1_ECID_PART18_REGISTER_PART_18_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_18_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART19_REGISTER_PART_19                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_19    );
+REG64_FLD( PU_OTPROM0_ECID_PART19_REGISTER_PART_19_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_19_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART19_REGISTER_PART_19                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_19    );
+REG64_FLD( PU_OTPROM1_ECID_PART19_REGISTER_PART_19_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_19_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART1_REGISTER_PART_1                   , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_1     );
+REG64_FLD( PU_OTPROM0_ECID_PART1_REGISTER_PART_1_LEN               , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_1_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART1_REGISTER_PART_1                   , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_1     );
+REG64_FLD( PU_OTPROM1_ECID_PART1_REGISTER_PART_1_LEN               , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_1_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART20_REGISTER_PART_20                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_20    );
+REG64_FLD( PU_OTPROM0_ECID_PART20_REGISTER_PART_20_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_20_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART20_REGISTER_PART_20                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_20    );
+REG64_FLD( PU_OTPROM1_ECID_PART20_REGISTER_PART_20_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_20_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART21_REGISTER_PART_21                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_21    );
+REG64_FLD( PU_OTPROM0_ECID_PART21_REGISTER_PART_21_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_21_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART21_REGISTER_PART_21                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_21    );
+REG64_FLD( PU_OTPROM1_ECID_PART21_REGISTER_PART_21_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_21_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART22_REGISTER_PART_22                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_22    );
+REG64_FLD( PU_OTPROM0_ECID_PART22_REGISTER_PART_22_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_22_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART22_REGISTER_PART_22                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_22    );
+REG64_FLD( PU_OTPROM1_ECID_PART22_REGISTER_PART_22_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_22_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART23_REGISTER_PART_23                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_23    );
+REG64_FLD( PU_OTPROM0_ECID_PART23_REGISTER_PART_23_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_23_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART23_REGISTER_PART_23                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_23    );
+REG64_FLD( PU_OTPROM1_ECID_PART23_REGISTER_PART_23_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_23_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART24_REGISTER_PART_24                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_24    );
+REG64_FLD( PU_OTPROM0_ECID_PART24_REGISTER_PART_24_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_24_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART24_REGISTER_PART_24                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_24    );
+REG64_FLD( PU_OTPROM1_ECID_PART24_REGISTER_PART_24_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_24_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART25_REGISTER_PART_25                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_25    );
+REG64_FLD( PU_OTPROM0_ECID_PART25_REGISTER_PART_25_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_25_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART25_REGISTER_PART_25                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_25    );
+REG64_FLD( PU_OTPROM1_ECID_PART25_REGISTER_PART_25_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_25_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART26_REGISTER_PART_26                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_26    );
+REG64_FLD( PU_OTPROM0_ECID_PART26_REGISTER_PART_26_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_26_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART26_REGISTER_PART_26                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_26    );
+REG64_FLD( PU_OTPROM1_ECID_PART26_REGISTER_PART_26_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_26_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART27_REGISTER_PART_27                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_27    );
+REG64_FLD( PU_OTPROM0_ECID_PART27_REGISTER_PART_27_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_27_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART27_REGISTER_PART_27                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_27    );
+REG64_FLD( PU_OTPROM1_ECID_PART27_REGISTER_PART_27_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_27_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART28_REGISTER_PART_28                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_28    );
+REG64_FLD( PU_OTPROM0_ECID_PART28_REGISTER_PART_28_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_28_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART28_REGISTER_PART_28                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_28    );
+REG64_FLD( PU_OTPROM1_ECID_PART28_REGISTER_PART_28_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_28_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART29_REGISTER_PART_29                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_29    );
+REG64_FLD( PU_OTPROM0_ECID_PART29_REGISTER_PART_29_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_29_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART29_REGISTER_PART_29                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_29    );
+REG64_FLD( PU_OTPROM1_ECID_PART29_REGISTER_PART_29_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_29_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART2_REGISTER_PART_2                   , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_2     );
+REG64_FLD( PU_OTPROM0_ECID_PART2_REGISTER_PART_2_LEN               , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_2_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART2_REGISTER_PART_2                   , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_2     );
+REG64_FLD( PU_OTPROM1_ECID_PART2_REGISTER_PART_2_LEN               , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_2_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART30_REGISTER_PART_30                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_30    );
+REG64_FLD( PU_OTPROM0_ECID_PART30_REGISTER_PART_30_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_30_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART30_REGISTER_PART_30                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_30    );
+REG64_FLD( PU_OTPROM1_ECID_PART30_REGISTER_PART_30_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_30_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART31_REGISTER_PART_31                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_31    );
+REG64_FLD( PU_OTPROM0_ECID_PART31_REGISTER_PART_31_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_31_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART31_REGISTER_PART_31                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_31    );
+REG64_FLD( PU_OTPROM1_ECID_PART31_REGISTER_PART_31_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_31_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART32_REGISTER_PART_32                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_32    );
+REG64_FLD( PU_OTPROM0_ECID_PART32_REGISTER_PART_32_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_32_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART32_REGISTER_PART_32                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_32    );
+REG64_FLD( PU_OTPROM1_ECID_PART32_REGISTER_PART_32_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_32_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART33_REGISTER_PART_33                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_33    );
+REG64_FLD( PU_OTPROM0_ECID_PART33_REGISTER_PART_33_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_33_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART33_REGISTER_PART_33                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_33    );
+REG64_FLD( PU_OTPROM1_ECID_PART33_REGISTER_PART_33_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_33_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART34_REGISTER_PART_34                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_34    );
+REG64_FLD( PU_OTPROM0_ECID_PART34_REGISTER_PART_34_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_34_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART34_REGISTER_PART_34                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_34    );
+REG64_FLD( PU_OTPROM1_ECID_PART34_REGISTER_PART_34_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_34_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART35_REGISTER_PART_35                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_35    );
+REG64_FLD( PU_OTPROM0_ECID_PART35_REGISTER_PART_35_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_35_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART35_REGISTER_PART_35                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_35    );
+REG64_FLD( PU_OTPROM1_ECID_PART35_REGISTER_PART_35_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_35_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART36_REGISTER_PART_36                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_36    );
+REG64_FLD( PU_OTPROM0_ECID_PART36_REGISTER_PART_36_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_36_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART36_REGISTER_PART_36                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_36    );
+REG64_FLD( PU_OTPROM1_ECID_PART36_REGISTER_PART_36_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_36_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART37_REGISTER_PART_37                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_37    );
+REG64_FLD( PU_OTPROM0_ECID_PART37_REGISTER_PART_37_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_37_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART37_REGISTER_PART_37                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_37    );
+REG64_FLD( PU_OTPROM1_ECID_PART37_REGISTER_PART_37_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_37_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART38_REGISTER_PART_38                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_38    );
+REG64_FLD( PU_OTPROM0_ECID_PART38_REGISTER_PART_38_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_38_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART38_REGISTER_PART_38                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_38    );
+REG64_FLD( PU_OTPROM1_ECID_PART38_REGISTER_PART_38_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_38_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART39_REGISTER_PART_39                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_39    );
+REG64_FLD( PU_OTPROM0_ECID_PART39_REGISTER_PART_39_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_39_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART39_REGISTER_PART_39                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_39    );
+REG64_FLD( PU_OTPROM1_ECID_PART39_REGISTER_PART_39_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_39_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART3_REGISTER_PART_3                   , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_3     );
+REG64_FLD( PU_OTPROM0_ECID_PART3_REGISTER_PART_3_LEN               , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_3_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART3_REGISTER_PART_3                   , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_3     );
+REG64_FLD( PU_OTPROM1_ECID_PART3_REGISTER_PART_3_LEN               , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_3_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART40_REGISTER_PART_40                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_40    );
+REG64_FLD( PU_OTPROM0_ECID_PART40_REGISTER_PART_40_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_40_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART40_REGISTER_PART_40                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_40    );
+REG64_FLD( PU_OTPROM1_ECID_PART40_REGISTER_PART_40_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_40_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART41_REGISTER_PART_41                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_41    );
+REG64_FLD( PU_OTPROM0_ECID_PART41_REGISTER_PART_41_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_41_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART41_REGISTER_PART_41                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_41    );
+REG64_FLD( PU_OTPROM1_ECID_PART41_REGISTER_PART_41_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_41_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART42_REGISTER_PART_42                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_42    );
+REG64_FLD( PU_OTPROM0_ECID_PART42_REGISTER_PART_42_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_42_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART42_REGISTER_PART_42                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_42    );
+REG64_FLD( PU_OTPROM1_ECID_PART42_REGISTER_PART_42_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_42_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART43_REGISTER_PART_43                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_43    );
+REG64_FLD( PU_OTPROM0_ECID_PART43_REGISTER_PART_43_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_43_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART43_REGISTER_PART_43                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_43    );
+REG64_FLD( PU_OTPROM1_ECID_PART43_REGISTER_PART_43_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_43_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART44_REGISTER_PART_44                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_44    );
+REG64_FLD( PU_OTPROM0_ECID_PART44_REGISTER_PART_44_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_44_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART44_REGISTER_PART_44                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_44    );
+REG64_FLD( PU_OTPROM1_ECID_PART44_REGISTER_PART_44_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_44_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART45_REGISTER_PART_45                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_45    );
+REG64_FLD( PU_OTPROM0_ECID_PART45_REGISTER_PART_45_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_45_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART45_REGISTER_PART_45                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_45    );
+REG64_FLD( PU_OTPROM1_ECID_PART45_REGISTER_PART_45_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_45_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART46_REGISTER_PART_46                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_46    );
+REG64_FLD( PU_OTPROM0_ECID_PART46_REGISTER_PART_46_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_46_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART46_REGISTER_PART_46                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_46    );
+REG64_FLD( PU_OTPROM1_ECID_PART46_REGISTER_PART_46_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_46_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART47_REGISTER_PART_47                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_47    );
+REG64_FLD( PU_OTPROM0_ECID_PART47_REGISTER_PART_47_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_47_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART47_REGISTER_PART_47                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_47    );
+REG64_FLD( PU_OTPROM1_ECID_PART47_REGISTER_PART_47_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_47_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART48_REGISTER_PART_48                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_48    );
+REG64_FLD( PU_OTPROM0_ECID_PART48_REGISTER_PART_48_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_48_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART48_REGISTER_PART_48                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_48    );
+REG64_FLD( PU_OTPROM1_ECID_PART48_REGISTER_PART_48_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_48_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART49_REGISTER_PART_49                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_49    );
+REG64_FLD( PU_OTPROM0_ECID_PART49_REGISTER_PART_49_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_49_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART49_REGISTER_PART_49                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_49    );
+REG64_FLD( PU_OTPROM1_ECID_PART49_REGISTER_PART_49_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_49_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART4_REGISTER_PART_4                   , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_4     );
+REG64_FLD( PU_OTPROM0_ECID_PART4_REGISTER_PART_4_LEN               , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_4_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART4_REGISTER_PART_4                   , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_4     );
+REG64_FLD( PU_OTPROM1_ECID_PART4_REGISTER_PART_4_LEN               , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_4_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART50_REGISTER_PART_50                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_50    );
+REG64_FLD( PU_OTPROM0_ECID_PART50_REGISTER_PART_50_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_50_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART50_REGISTER_PART_50                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_50    );
+REG64_FLD( PU_OTPROM1_ECID_PART50_REGISTER_PART_50_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_50_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART51_REGISTER_PART_51                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_51    );
+REG64_FLD( PU_OTPROM0_ECID_PART51_REGISTER_PART_51_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_51_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART51_REGISTER_PART_51                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_51    );
+REG64_FLD( PU_OTPROM1_ECID_PART51_REGISTER_PART_51_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_51_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART52_REGISTER_PART_52                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_52    );
+REG64_FLD( PU_OTPROM0_ECID_PART52_REGISTER_PART_52_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_52_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART52_REGISTER_PART_52                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_52    );
+REG64_FLD( PU_OTPROM1_ECID_PART52_REGISTER_PART_52_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_52_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART53_REGISTER_PART_53                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_53    );
+REG64_FLD( PU_OTPROM0_ECID_PART53_REGISTER_PART_53_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_53_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART53_REGISTER_PART_53                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_53    );
+REG64_FLD( PU_OTPROM1_ECID_PART53_REGISTER_PART_53_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_53_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART54_REGISTER_PART_54                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_54    );
+REG64_FLD( PU_OTPROM0_ECID_PART54_REGISTER_PART_54_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_54_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART54_REGISTER_PART_54                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_54    );
+REG64_FLD( PU_OTPROM1_ECID_PART54_REGISTER_PART_54_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_54_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART55_REGISTER_PART_55                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_55    );
+REG64_FLD( PU_OTPROM0_ECID_PART55_REGISTER_PART_55_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_55_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART55_REGISTER_PART_55                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_55    );
+REG64_FLD( PU_OTPROM1_ECID_PART55_REGISTER_PART_55_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_55_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART56_REGISTER_PART_56                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_56    );
+REG64_FLD( PU_OTPROM0_ECID_PART56_REGISTER_PART_56_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_56_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART56_REGISTER_PART_56                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_56    );
+REG64_FLD( PU_OTPROM1_ECID_PART56_REGISTER_PART_56_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_56_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART57_REGISTER_PART_57                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_57    );
+REG64_FLD( PU_OTPROM0_ECID_PART57_REGISTER_PART_57_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_57_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART57_REGISTER_PART_57                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_57    );
+REG64_FLD( PU_OTPROM1_ECID_PART57_REGISTER_PART_57_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_57_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART58_REGISTER_PART_58                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_58    );
+REG64_FLD( PU_OTPROM0_ECID_PART58_REGISTER_PART_58_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_58_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART58_REGISTER_PART_58                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_58    );
+REG64_FLD( PU_OTPROM1_ECID_PART58_REGISTER_PART_58_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_58_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART59_REGISTER_PART_59                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_59    );
+REG64_FLD( PU_OTPROM0_ECID_PART59_REGISTER_PART_59_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_59_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART59_REGISTER_PART_59                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_59    );
+REG64_FLD( PU_OTPROM1_ECID_PART59_REGISTER_PART_59_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_59_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART5_REGISTER_PART_5                   , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_5     );
+REG64_FLD( PU_OTPROM0_ECID_PART5_REGISTER_PART_5_LEN               , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_5_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART5_REGISTER_PART_5                   , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_5     );
+REG64_FLD( PU_OTPROM1_ECID_PART5_REGISTER_PART_5_LEN               , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_5_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART60_REGISTER_PART_60                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_60    );
+REG64_FLD( PU_OTPROM0_ECID_PART60_REGISTER_PART_60_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_60_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART60_REGISTER_PART_60                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_60    );
+REG64_FLD( PU_OTPROM1_ECID_PART60_REGISTER_PART_60_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_60_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART61_REGISTER_PART_61                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_61    );
+REG64_FLD( PU_OTPROM0_ECID_PART61_REGISTER_PART_61_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_61_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART61_REGISTER_PART_61                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_61    );
+REG64_FLD( PU_OTPROM1_ECID_PART61_REGISTER_PART_61_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_61_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART62_REGISTER_PART_62                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_62    );
+REG64_FLD( PU_OTPROM0_ECID_PART62_REGISTER_PART_62_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_62_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART62_REGISTER_PART_62                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_62    );
+REG64_FLD( PU_OTPROM1_ECID_PART62_REGISTER_PART_62_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_62_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART63_REGISTER_PART_63                 , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_63    );
+REG64_FLD( PU_OTPROM0_ECID_PART63_REGISTER_PART_63_LEN             , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_63_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART63_REGISTER_PART_63                 , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_63    );
+REG64_FLD( PU_OTPROM1_ECID_PART63_REGISTER_PART_63_LEN             , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_63_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART6_REGISTER_PART_6                   , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_6     );
+REG64_FLD( PU_OTPROM0_ECID_PART6_REGISTER_PART_6_LEN               , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_6_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART6_REGISTER_PART_6                   , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_6     );
+REG64_FLD( PU_OTPROM1_ECID_PART6_REGISTER_PART_6_LEN               , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_6_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART7_REGISTER_PART_7                   , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_7     );
+REG64_FLD( PU_OTPROM0_ECID_PART7_REGISTER_PART_7_LEN               , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_7_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART7_REGISTER_PART_7                   , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_7     );
+REG64_FLD( PU_OTPROM1_ECID_PART7_REGISTER_PART_7_LEN               , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_7_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART8_REGISTER_PART_8                   , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_8     );
+REG64_FLD( PU_OTPROM0_ECID_PART8_REGISTER_PART_8_LEN               , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_8_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART8_REGISTER_PART_8                   , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_8     );
+REG64_FLD( PU_OTPROM1_ECID_PART8_REGISTER_PART_8_LEN               , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_8_LEN );
+
+REG64_FLD( PU_OTPROM0_ECID_PART9_REGISTER_PART_9                   , 0   , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_9     );
+REG64_FLD( PU_OTPROM0_ECID_PART9_REGISTER_PART_9_LEN               , 64  , SH_UNT_PU_OTPROM0, SH_ACS_SCOM     ,
+           SH_FLD_PART_9_LEN );
+
+REG64_FLD( PU_OTPROM1_ECID_PART9_REGISTER_PART_9                   , 0   , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_9     );
+REG64_FLD( PU_OTPROM1_ECID_PART9_REGISTER_PART_9_LEN               , 64  , SH_UNT_PU_OTPROM1, SH_ACS_SCOM     ,
+           SH_FLD_PART_9_LEN );
+
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID              , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LPID );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN          , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LPID_LEN );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID               , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PID );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN           , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PID_LEN );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID               , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_TID );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN           , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_TID_LEN );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE            , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_ENABLE );
+
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY                   , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN               , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LEN );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE              , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_SIZE );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN          , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_SIZE_LEN );
+
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_READ_OFFSET );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_READ_OFFSET_LEN );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED           , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_QUEUED );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN       , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_QUEUED_LEN );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX           , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PRIMAX );
+REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX_LEN       , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PRIMAX_LEN );
+
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID              , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LPID );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN          , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LPID_LEN );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID               , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PID );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN           , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PID_LEN );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID               , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_TID );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN           , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_TID_LEN );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE            , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_ENABLE );
+
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY                   , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN               , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LEN );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE              , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_SIZE );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN          , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_SIZE_LEN );
+
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_READ_OFFSET );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_READ_OFFSET_LEN );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED           , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_QUEUED );
+REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN       , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_QUEUED_LEN );
+
+REG64_FLD( PU_EFT_MAX_BYTE_CNT_LIMIT                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LIMIT      );
+REG64_FLD( PU_EFT_MAX_BYTE_CNT_LIMIT_LEN                           , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LIMIT_LEN  );
+REG64_FLD( PU_EFT_MAX_BYTE_CNT_SRC_DDE                             , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRC_DDE    );
+REG64_FLD( PU_EFT_MAX_BYTE_CNT_SRC_DDE_LEN                         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRC_DDE_LEN );
+REG64_FLD( PU_EFT_MAX_BYTE_CNT_TARGET_DDE                          , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_TARGET_DDE );
+REG64_FLD( PU_EFT_MAX_BYTE_CNT_TARGET_DDE_LEN                      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_TARGET_DDE_LEN );
+
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_0_OUT                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_0_OUT                      , 1   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_0_OUT                      , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_0_OUT                      , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_1_OUT                      , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_1_OUT                      , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_1_OUT                      , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_1_OUT                      , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_2_OUT                      , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_2_OUT                      , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_2_OUT                      , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_2_OUT                      , 11  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_3_OUT                      , 12  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_3_OUT                      , 13  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_3_OUT                      , 14  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_3_OUT                      , 15  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_4_OUT                      , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_4_OUT                      , 17  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_4_OUT                      , 18  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_4_OUT                      , 19  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_5_OUT                      , 20  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_5_OUT                      , 21  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_5_OUT                      , 22  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_5_OUT                      , 23  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_6_OUT                      , 24  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_6_OUT                      , 25  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_6_OUT                      , 26  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_6_OUT                      , 27  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_7_OUT                      , 28  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_7_OUT                      , 29  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_7_OUT                      , 30  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_7_OUT                      , 31  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_DROP_COUNTER_FULL              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DROP_COUNTER_FULL );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_INTERNAL_ERROR                 , 33  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERNAL_ERROR );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_SCOM_ERROR                     , 34  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_PARITY_ERROR                   , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_0_OUT                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_0_OUT                      , 1   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_0_OUT                      , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_0_OUT                      , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_1_OUT                      , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_1_OUT                      , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_1_OUT                      , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_1_OUT                      , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_2_OUT                      , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_2_OUT                      , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_2_OUT                      , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_2_OUT                      , 11  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_3_OUT                      , 12  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_3_OUT                      , 13  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_3_OUT                      , 14  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_3_OUT                      , 15  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_4_OUT                      , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_4_OUT                      , 17  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_4_OUT                      , 18  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_4_OUT                      , 19  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_5_OUT                      , 20  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_5_OUT                      , 21  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_5_OUT                      , 22  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_5_OUT                      , 23  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_6_OUT                      , 24  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_6_OUT                      , 25  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_6_OUT                      , 26  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_6_OUT                      , 27  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_7_OUT                      , 28  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_7_OUT                      , 29  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_7_OUT                      , 30  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_7_OUT                      , 31  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_DROP_COUNTER_FULL              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DROP_COUNTER_FULL );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_INTERNAL_ERROR                 , 33  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERNAL_ERROR );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_SCOM_ERROR                     , 34  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_PARITY_ERROR                   , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_0_OUT                         , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_0_OUT                         , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_0_OUT                         , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_0_OUT                         , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_1_OUT                         , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_1_OUT                         , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_1_OUT                         , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_1_OUT                         , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_2_OUT                         , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_2_OUT                         , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_2_OUT                         , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_2_OUT                         , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_3_OUT                         , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_3_OUT                         , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_3_OUT                         , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_3_OUT                         , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_4_OUT                         , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_4_OUT                         , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_4_OUT                         , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_4_OUT                         , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_5_OUT                         , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_5_OUT                         , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_5_OUT                         , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_5_OUT                         , 23  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_6_OUT                         , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_6_OUT                         , 25  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_6_OUT                         , 26  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_6_OUT                         , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_7_OUT                         , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_7_OUT                         , 29  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_7_OUT                         , 30  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_7_OUT                         , 31  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_DROP_COUNTER_FULL                 , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DROP_COUNTER_FULL );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_INTERNAL_ERROR                    , 33  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_ERROR );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_SCOM_ERROR                        , 34  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_EHHCA_FIR_MASK_REG_PARITY_ERROR                      , 35  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_0_OUT                              , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_0_OUT                              , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_0_OUT                              , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_0_OUT                              , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_0_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_1_OUT                              , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_1_OUT                              , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_1_OUT                              , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_1_OUT                              , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_1_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_2_OUT                              , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_2_OUT                              , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_2_OUT                              , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_2_OUT                              , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_2_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_3_OUT                              , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_3_OUT                              , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_3_OUT                              , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_3_OUT                              , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_3_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_4_OUT                              , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_4_OUT                              , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_4_OUT                              , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_4_OUT                              , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_4_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_5_OUT                              , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_5_OUT                              , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_5_OUT                              , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_5_OUT                              , 23  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_5_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_6_OUT                              , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_6_OUT                              , 25  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_6_OUT                              , 26  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_6_OUT                              , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_6_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE1_7_OUT                              , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_CE2_7_OUT                              , 29  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE1_7_OUT                              , 30  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE1_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_UE2_7_OUT                              , 31  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UE2_7_OUT  );
+REG64_FLD( PU_EHHCA_FIR_REG_DROP_COUNTER_FULL                      , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DROP_COUNTER_FULL );
+REG64_FLD( PU_EHHCA_FIR_REG_INTERNAL_ERROR                         , 33  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_ERROR );
+REG64_FLD( PU_EHHCA_FIR_REG_SCOM_ERROR                             , 34  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_EHHCA_FIR_REG_PARITY_ERROR                           , 35  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_RATE                         , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RATE       );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_RATE_LEN                     , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_W0_COUNT                     , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_W1_COUNT                     , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R0_COUNT                     , 28  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R1_COUNT                     , 40  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R2_COUNT                     , 52  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_RATE                         , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RATE       );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_RATE_LEN                     , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_W0_COUNT                     , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_W1_COUNT                     , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R0_COUNT                     , 28  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R1_COUNT                     , 40  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R2_COUNT                     , 52  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_RATE                         , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RATE       );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_RATE_LEN                     , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_W0_COUNT                     , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_W1_COUNT                     , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R0_COUNT                     , 28  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R1_COUNT                     , 40  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R2_COUNT                     , 52  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_RATE                         , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RATE       );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_RATE_LEN                     , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_W0_COUNT                     , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_W1_COUNT                     , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R0_COUNT                     , 28  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R1_COUNT                     , 40  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R2_COUNT                     , 52  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_RATE                         , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RATE       );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_RATE_LEN                     , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_W0_COUNT                     , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_W1_COUNT                     , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R0_COUNT                     , 28  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R1_COUNT                     , 40  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R2_COUNT                     , 52  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_RATE                         , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RATE       );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_RATE_LEN                     , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_W0_COUNT                     , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_W1_COUNT                     , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R0_COUNT                     , 28  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R1_COUNT                     , 40  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R2_COUNT                     , 52  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_RATE                         , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RATE       );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_RATE_LEN                     , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_W0_COUNT                     , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_W1_COUNT                     , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R0_COUNT                     , 28  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R1_COUNT                     , 40  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R2_COUNT                     , 52  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_RATE                         , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RATE       );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_RATE_LEN                     , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_W0_COUNT                     , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_W1_COUNT                     , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R0_COUNT                     , 28  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R1_COUNT                     , 40  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R2_COUNT                     , 52  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_RATE                         , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RATE       );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_RATE_LEN                     , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_W0_COUNT                     , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_W1_COUNT                     , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R0_COUNT                     , 28  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R1_COUNT                     , 40  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R2_COUNT                     , 52  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_RATE                         , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RATE       );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_RATE_LEN                     , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_W0_COUNT                     , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_W1_COUNT                     , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R0_COUNT                     , 28  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R1_COUNT                     , 40  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R2_COUNT                     , 52  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_RATE                         , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RATE       );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_RATE_LEN                     , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_W0_COUNT                     , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_W1_COUNT                     , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R0_COUNT                     , 28  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R1_COUNT                     , 40  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R2_COUNT                     , 52  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_RATE                         , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RATE       );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_RATE_LEN                     , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RATE_LEN   );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_W0_COUNT                     , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT   );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_W0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_W0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_W1_COUNT                     , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT   );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_W1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_W1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R0_COUNT                     , 28  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT   );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R0_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R0_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R1_COUNT                     , 40  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT   );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R1_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R1_COUNT_LEN );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R2_COUNT                     , 52  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT   );
+REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R2_COUNT_LEN                 , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_R2_COUNT_LEN );
+
+REG64_FLD( PU_ERAT_STATUS_CONTROL_FORCE_BYPASS                     , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_BYPASS );
+REG64_FLD( PU_ERAT_STATUS_CONTROL_IDLE                             , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IDLE       );
+REG64_FLD( PU_ERAT_STATUS_CONTROL_VALID_ENTRY                      , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_VALID_ENTRY );
+REG64_FLD( PU_ERAT_STATUS_CONTROL_DISABLE_HIT_UNDER_BARRIER        , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_HIT_UNDER_BARRIER );
+REG64_FLD( PU_ERAT_STATUS_CONTROL_DISABLE_PROMOTE                  , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_PROMOTE );
+REG64_FLD( PU_ERAT_STATUS_CONTROL_DISABLE_CHECKIN_HANG_TIMER       , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_CHECKIN_HANG_TIMER );
+REG64_FLD( PU_ERAT_STATUS_CONTROL_DISABLE_CHECKOUT_HANG_TIMER      , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_CHECKOUT_HANG_TIMER );
+REG64_FLD( PU_ERAT_STATUS_CONTROL_SPECULATIVE_CHECKIN_COUNT        , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPECULATIVE_CHECKIN_COUNT );
+REG64_FLD( PU_ERAT_STATUS_CONTROL_SPECULATIVE_CHECKIN_COUNT_LEN    , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPECULATIVE_CHECKIN_COUNT_LEN );
+
+REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK0            , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ERR_BRK0   );
+REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK0_LEN        , 6   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ERR_BRK0_LEN );
+REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK1            , 6   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ERR_BRK1   );
+REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK1_LEN        , 6   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ERR_BRK1_LEN );
+REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK2            , 12  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ERR_BRK2   );
+REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK2_LEN        , 6   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ERR_BRK2_LEN );
+REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK3            , 18  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ERR_BRK3   );
+REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK3_LEN        , 6   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ERR_BRK3_LEN );
+REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK4            , 24  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ERR_BRK4   );
+REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK4_LEN        , 6   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ERR_BRK4_LEN );
+REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK5            , 30  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ERR_BRK5   );
+REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK5_LEN        , 6   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ERR_BRK5_LEN );
+
+REG64_FLD( PEC_ERROR_REG_CE                                        , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CE         );
+REG64_FLD( PEC_ERROR_REG_CHIPLET_ERRORS                            , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_ERRORS );
+REG64_FLD( PEC_ERROR_REG_CHIPLET_ERRORS_LEN                        , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_ERRORS_LEN );
+REG64_FLD( PEC_ERROR_REG_PARITY                                    , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PARITY     );
+REG64_FLD( PEC_ERROR_REG_DATA_BUFFER                               , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DATA_BUFFER );
+REG64_FLD( PEC_ERROR_REG_ADDR_BUFFER                               , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_BUFFER );
+REG64_FLD( PEC_ERROR_REG_PCB_FSM                                   , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PCB_FSM    );
+REG64_FLD( PEC_ERROR_REG_CL_FSM                                    , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CL_FSM     );
+REG64_FLD( PEC_ERROR_REG_INT_RX_FSM                                , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INT_RX_FSM );
+REG64_FLD( PEC_ERROR_REG_INT_TX_FSM                                , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INT_TX_FSM );
+REG64_FLD( PEC_ERROR_REG_INT_TYPE                                  , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INT_TYPE   );
+REG64_FLD( PEC_ERROR_REG_CL_DATA                                   , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CL_DATA    );
+REG64_FLD( PEC_ERROR_REG_INFO                                      , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INFO       );
+REG64_FLD( PEC_ERROR_REG_UNUSED_0                                  , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_0   );
+REG64_FLD( PEC_ERROR_REG_CHIPLET_ATOMIC_LOCK                       , 15  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_ATOMIC_LOCK );
+REG64_FLD( PEC_ERROR_REG_PCB_INTERFACE                             , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PCB_INTERFACE );
+REG64_FLD( PEC_ERROR_REG_CHIPLET_OFFLINE                           , 17  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_OFFLINE );
+REG64_FLD( PEC_ERROR_REG_CHIPLET_GRID_SKITTER                      , 18  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_GRID_SKITTER );
+REG64_FLD( PEC_ERROR_REG_CTRL_PARITY                               , 19  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CTRL_PARITY );
+REG64_FLD( PEC_ERROR_REG_ADDRESS_PARITY                            , 20  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ADDRESS_PARITY );
+REG64_FLD( PEC_ERROR_REG_TIMEOUT_PARITY                            , 21  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_PARITY );
+REG64_FLD( PEC_ERROR_REG_CONFIG_PARITY                             , 22  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PARITY );
+REG64_FLD( PEC_ERROR_REG_UNUSED_1                                  , 23  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_1   );
+REG64_FLD( PEC_ERROR_REG_DIV_PARITY                                , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DIV_PARITY );
+REG64_FLD( PEC_ERROR_REG_PLL_UNLOCK                                , 25  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PLL_UNLOCK );
+REG64_FLD( PEC_ERROR_REG_PLL_UNLOCK_LEN                            , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PLL_UNLOCK_LEN );
+
+REG64_FLD( PEC_ERROR_STATUS_ERRORS                                 , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ERRORS     );
+REG64_FLD( PEC_ERROR_STATUS_ERRORS_LEN                             , 32  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ERRORS_LEN );
+
+REG64_FLD( PU_NPU_SM2_ERR_FIRST_BITS                               , 0   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU_SM2_ERR_FIRST_BITS_LEN                           , 64  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_DEBUG0_CONFIG_P                     , 0   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_DEBUG0_CONFIG_P );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_DEBUG1_CONFIG_P                     , 1   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_DEBUG1_CONFIG_P );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_XTS_CONFIG_P                        , 2   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_XTS_CONFIG_P );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED1                             , 3   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1    );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED1_LEN                         , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1_LEN );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR0                        , 8   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_SNP_REG_ERR0 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR1                        , 9   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_SNP_REG_ERR1 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR2                        , 10  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_SNP_REG_ERR2 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR3                        , 11  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_SNP_REG_ERR3 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR4                        , 12  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_SNP_REG_ERR4 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR5                        , 13  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_SNP_REG_ERR5 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR6                        , 14  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_SNP_REG_ERR6 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATR_SM_STATE                        , 15  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATR_SM_STATE );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATSD_SM_STATE                       , 16  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATSD_SM_STATE );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATR_TIMEOUT                         , 17  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATR_TIMEOUT );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATSD_TIMEOUT                        , 18  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATSD_TIMEOUT );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATSD_BAD_TAG                        , 19  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATSD_BAD_TAG );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_ERR2                        , 20  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MAP_REG_ERR2 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_ERR3                        , 21  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MAP_REG_ERR3 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_ERR4                        , 22  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MAP_REG_ERR4 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATR_ARBSTATE                        , 23  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATR_ARBSTATE );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED2                             , 24  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2    );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED2_LEN                         , 8   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2_LEN );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_CERR0                       , 32  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IFC_REG_CERR0 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_CERR1                       , 33  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IFC_REG_CERR1 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_CERR2                       , 34  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IFC_REG_CERR2 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_CERR0                       , 35  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MAP_REG_CERR0 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_CERR1                       , 36  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MAP_REG_CERR1 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED3                             , 37  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED3    );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED3_LEN                         , 11  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED3_LEN );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR0                        , 48  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IFC_REG_ERR0 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR1                        , 49  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IFC_REG_ERR1 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR2                        , 50  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IFC_REG_ERR2 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR3                        , 51  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IFC_REG_ERR3 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR4                        , 52  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IFC_REG_ERR4 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR5                        , 53  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IFC_REG_ERR5 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR6                        , 54  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IFC_REG_ERR6 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR7                        , 55  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IFC_REG_ERR7 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR8                        , 56  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IFC_REG_ERR8 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_ERR0                        , 57  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MAP_REG_ERR0 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_ERR1                        , 58  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MAP_REG_ERR1 );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED4                             , 59  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED4    );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED4_LEN                         , 4   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED4_LEN );
+REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATR_MISS_IRQ                        , 63  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATR_MISS_IRQ );
+
+REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC                  , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC       );
+REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC_LEN              , 24  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_LEN   );
+REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC_LENR             , 24  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_LENR  );
+REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC_LENR_LEN         , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_LENR_LEN );
+REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC_RNW              , 26  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_RNW   );
+REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC_DA_OP            , 27  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MISC_DA_OP );
+
+REG64_FLD( PU_NPU_SM2_ERR_MASK_BITS                                , 0   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NPU_SM2_ERR_MASK_BITS_LEN                            , 64  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NPU_CTL_ERR_SCOPE_CTL_CONFIG_CTL                     , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CTL        );
+REG64_FLD( PU_NPU_CTL_ERR_SCOPE_CTL_CONFIG_CTL_LEN                 , 16  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CTL_LEN    );
+
+REG64_FLD( PEC_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK  , 16  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK );
+REG64_FLD( PEC_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK            , 17  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_THERM_MODEREG_PARITY_MASK );
+REG64_FLD( PEC_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK          , 18  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_SKITTER_MODEREG_PARITY_MASK );
+REG64_FLD( PEC_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK         , 19  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_SKITTER_FORCEREG_PARITY_MASK );
+REG64_FLD( PEC_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK        , 20  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_SCAN_INIT_VERSION_PARITY_MASK );
+REG64_FLD( PEC_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK             , 21  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_VOLT_MODEREG_PARITY_MASK );
+REG64_FLD( PEC_ERR_STATUS_REG_COUNT_STATE_MASK                     , 23  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_STATE_MASK );
+REG64_FLD( PEC_ERR_STATUS_REG_RUN_STATE_MASK                       , 24  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUN_STATE_MASK );
+REG64_FLD( PEC_ERR_STATUS_REG_THRES_STATE_MASK                     , 25  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_THRES_STATE_MASK );
+REG64_FLD( PEC_ERR_STATUS_REG_OVERFLOW_MASK                        , 26  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_OVERFLOW_MASK );
+REG64_FLD( PEC_ERR_STATUS_REG_SHIFTER_PARITY_MASK                  , 27  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_SHIFTER_PARITY_MASK );
+REG64_FLD( PEC_ERR_STATUS_REG_SHIFTER_VALID_MASK                   , 28  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_SHIFTER_VALID_MASK );
+REG64_FLD( PEC_ERR_STATUS_REG_TIMEOUT_MASK                         , 29  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMEOUT_MASK );
+REG64_FLD( PEC_ERR_STATUS_REG_F_SKITTER_READ_MASK                  , 30  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_F_SKITTER_READ_MASK );
+REG64_FLD( PEC_ERR_STATUS_REG_PCB_MASK                             , 31  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCB_MASK   );
+
+REG64_FLD( PU_ESB_CI_BASE_BASE                                     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BASE       );
+REG64_FLD( PU_ESB_CI_BASE_BASE_LEN                                 , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BASE_LEN   );
+REG64_FLD( PU_ESB_CI_BASE_VALID                                    , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_VALID      );
+
+REG64_FLD( PU_ESB_NOTIFY_ADDR                                      , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR       );
+REG64_FLD( PU_ESB_NOTIFY_ADDR_LEN                                  , 53  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_ESB_NOTIFY_VALID                                     , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_VALID      );
+
+REG64_FLD( PU_EXPORT_REGL_CTRL_TP_NX_ALLOW_CRYPTO_DC               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TP_NX_ALLOW_CRYPTO_DC );
+REG64_FLD( PU_EXPORT_REGL_CTRL_TP_EX_FUSE_VMX_CRYPTO_DIS_DC        , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TP_EX_FUSE_VMX_CRYPTO_DIS_DC );
+REG64_FLD( PU_EXPORT_REGL_CTRL_TP_EX_FUSE_FP_THROTTLE_EN_DC        , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TP_EX_FUSE_FP_THROTTLE_EN_DC );
+REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_2CHIP           , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TP_PB_FUSE_TOPOLOGY_2CHIP );
+REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_GROUP           , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP );
+REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_GROUP_LEN       , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP_LEN );
+REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_SPARE                    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TP_PB_FUSE_SPARE );
+
+REG64_FLD( PU_EXTENDED_STATUS_B_MSM_CURR_STATE_0                   , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MSM_CURR_STATE_0 );
+REG64_FLD( PU_EXTENDED_STATUS_B_MSM_CURR_STATE_0_LEN               , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MSM_CURR_STATE_0_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_B_SELF_BUSY_0                        , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SELF_BUSY_0 );
+REG64_FLD( PU_EXTENDED_STATUS_B_PEEK_DATA1_0                       , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_EXTENDED_STATUS_B_PEEK_DATA1_0_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_B_LBUS_PARITY_ERR1_0                 , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_EXTENDED_STATUS_C_MSM_CURR_STATE_1                   , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MSM_CURR_STATE_1 );
+REG64_FLD( PU_EXTENDED_STATUS_C_MSM_CURR_STATE_1_LEN               , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MSM_CURR_STATE_1_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_C_SELF_BUSY_1                        , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SELF_BUSY_1 );
+REG64_FLD( PU_EXTENDED_STATUS_C_PEEK_DATA1_1                       , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_EXTENDED_STATUS_C_PEEK_DATA1_1_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_C_LBUS_PARITY_ERR1_1                 , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_EXTENDED_STATUS_D_MSM_CURR_STATE_2                   , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MSM_CURR_STATE_2 );
+REG64_FLD( PU_EXTENDED_STATUS_D_MSM_CURR_STATE_2_LEN               , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MSM_CURR_STATE_2_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_D_SELF_BUSY_2                        , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SELF_BUSY_2 );
+REG64_FLD( PU_EXTENDED_STATUS_D_PEEK_DATA1_2                       , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_EXTENDED_STATUS_D_PEEK_DATA1_2_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_D_LBUS_PARITY_ERR1_2                 , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_EXTENDED_STATUS_E_MSM_CURR_STATE_3                   , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MSM_CURR_STATE_3 );
+REG64_FLD( PU_EXTENDED_STATUS_E_MSM_CURR_STATE_3_LEN               , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MSM_CURR_STATE_3_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_E_SELF_BUSY_3                        , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SELF_BUSY_3 );
+REG64_FLD( PU_EXTENDED_STATUS_E_PEEK_DATA1_3                       , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_EXTENDED_STATUS_E_PEEK_DATA1_3_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_EXTENDED_STATUS_E_LBUS_PARITY_ERR1_3                 , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_ACTION0_REG_ACTION0               , 0   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_ACTION0_REG_ACTION0_LEN           , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_ACTION1_REG_ACTION1               , 0   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_ACTION1_REG_ACTION1_LEN           , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X0_FIR_ERR            , 0   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_X0_FIR_ERR );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X1_FIR_ERR            , 1   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_X1_FIR_ERR );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X2_FIR_ERR            , 2   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_X2_FIR_ERR );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X3_FIR_ERR            , 3   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_X3_FIR_ERR );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X4_FIR_ERR            , 4   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_X4_FIR_ERR );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X5_FIR_ERR            , 5   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_X5_FIR_ERR );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X6_FIR_ERR            , 6   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_X6_FIR_ERR );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_SCOM_ERROR               , 7   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERROR );
+
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X0_FIR_ERR                 , 0   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_X0_FIR_ERR );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X1_FIR_ERR                 , 1   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_X1_FIR_ERR );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X2_FIR_ERR                 , 2   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_X2_FIR_ERR );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X3_FIR_ERR                 , 3   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_X3_FIR_ERR );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X4_FIR_ERR                 , 4   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_X4_FIR_ERR );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X5_FIR_ERR                 , 5   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_X5_FIR_ERR );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X6_FIR_ERR                 , 6   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_X6_FIR_ERR );
+REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_SCOM_ERROR                    , 7   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERROR );
+
+REG64_FLD( PU_NPU_CTL_FENCE_0_CONFIG_0                             , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( PU_NPU_CTL_FENCE_0_CONFIG_0_LEN                         , 64  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_0_LEN      );
+
+REG64_FLD( PU_NPU_CTL_FENCE_1_CONFIG_1                             , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( PU_NPU_CTL_FENCE_1_CONFIG_1_LEN                         , 64  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_1_LEN      );
+
+REG64_FLD( PU_NPU_CTL_FENCE_STATE_BRK0                             , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK0       );
+REG64_FLD( PU_NPU_CTL_FENCE_STATE_BRK1                             , 1   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK1       );
+REG64_FLD( PU_NPU_CTL_FENCE_STATE_BRK2                             , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK2       );
+REG64_FLD( PU_NPU_CTL_FENCE_STATE_BRK3                             , 3   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK3       );
+REG64_FLD( PU_NPU_CTL_FENCE_STATE_BRK4                             , 4   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK4       );
+REG64_FLD( PU_NPU_CTL_FENCE_STATE_BRK5                             , 5   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK5       );
+
+REG64_FLD( PU_FI2C_CFG_PIBI2CM_PIB_SLAVE_ID                        , 0   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_PIBI2CM_PIB_SLAVE_ID );
+REG64_FLD( PU_FI2C_CFG_PIBI2CM_PIB_SLAVE_ID_LEN                    , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_PIBI2CM_PIB_SLAVE_ID_LEN );
+REG64_FLD( PU_FI2C_CFG_ECC_ENABLE                                  , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_ECC_ENABLE );
+REG64_FLD( PU_FI2C_CFG_DISABLE_ECC_CHK                             , 17  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_DISABLE_ECC_CHK );
+REG64_FLD( PU_FI2C_CFG_I2C_SPEED_MUX                               , 18  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_I2C_SPEED_MUX );
+REG64_FLD( PU_FI2C_CFG_I2C_SPEED_MUX_LEN                           , 2   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_I2C_SPEED_MUX_LEN );
+REG64_FLD( PU_FI2C_CFG_BIT_RATE_DIVISOR_VALUE                      , 20  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_BIT_RATE_DIVISOR_VALUE );
+REG64_FLD( PU_FI2C_CFG_BIT_RATE_DIVISOR_VALUE_LEN                  , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_BIT_RATE_DIVISOR_VALUE_LEN );
+REG64_FLD( PU_FI2C_CFG_I2C_BUS_HELD_MODE_ENABLE                    , 36  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_I2C_BUS_HELD_MODE_ENABLE );
+REG64_FLD( PU_FI2C_CFG_PIPELINE_ENABLE                             , 37  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_PIPELINE_ENABLE );
+REG64_FLD( PU_FI2C_CFG_BACKUP_SEEPROM_SELECT                       , 38  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_BACKUP_SEEPROM_SELECT );
+REG64_FLD( PU_FI2C_CFG_FORCE_RESET                                 , 39  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_FORCE_RESET );
+REG64_FLD( PU_FI2C_CFG_RESET_PIB                                   , 40  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESET_PIB  );
+REG64_FLD( PU_FI2C_CFG_DISABLE_TIMEOUT                             , 41  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_DISABLE_TIMEOUT );
+REG64_FLD( PU_FI2C_CFG_RESERVED_FOR_CONFIGS                        , 42  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_FOR_CONFIGS );
+REG64_FLD( PU_FI2C_CFG_RESERVED_FOR_CONFIGS_LEN                    , 18  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_FOR_CONFIGS_LEN );
+
+REG64_FLD( PU_FI2C_SCFG0_REGISTER_VALID                            , 0   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_REGISTER_VALID );
+REG64_FLD( PU_FI2C_SCFG0_RESERVED_3                                , 1   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_3 );
+REG64_FLD( PU_FI2C_SCFG0_RESERVED_4                                , 2   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_4 );
+REG64_FLD( PU_FI2C_SCFG0_RESERVED_4_LEN                            , 2   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_4_LEN );
+REG64_FLD( PU_FI2C_SCFG0_RESERVED_5                                , 4   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_5 );
+REG64_FLD( PU_FI2C_SCFG0_RESERVED_5_LEN                            , 4   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_5_LEN );
+REG64_FLD( PU_FI2C_SCFG0_DEVICE_ID                                 , 8   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_DEVICE_ID  );
+REG64_FLD( PU_FI2C_SCFG0_DEVICE_ID_LEN                             , 7   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_DEVICE_ID_LEN );
+REG64_FLD( PU_FI2C_SCFG0_ECC_ENABLE                                , 15  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_ECC_ENABLE );
+REG64_FLD( PU_FI2C_SCFG0_MEMORY_SIZE_IN_PPE_ADDR_MAP               , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP );
+REG64_FLD( PU_FI2C_SCFG0_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN           , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN );
+REG64_FLD( PU_FI2C_SCFG0_START_SEEPROM_ADDRESS                     , 32  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_SEEPROM_ADDRESS );
+REG64_FLD( PU_FI2C_SCFG0_START_SEEPROM_ADDRESS_LEN                 , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_SEEPROM_ADDRESS_LEN );
+REG64_FLD( PU_FI2C_SCFG0_START_PPE_ADDR                            , 48  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_PPE_ADDR );
+REG64_FLD( PU_FI2C_SCFG0_START_PPE_ADDR_LEN                        , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_PPE_ADDR_LEN );
+
+REG64_FLD( PU_FI2C_SCFG1_REGISTER_VALID                            , 0   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_REGISTER_VALID );
+REG64_FLD( PU_FI2C_SCFG1_RESERVED_6                                , 1   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_6 );
+REG64_FLD( PU_FI2C_SCFG1_RESERVED_7                                , 2   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_7 );
+REG64_FLD( PU_FI2C_SCFG1_RESERVED_7_LEN                            , 2   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_7_LEN );
+REG64_FLD( PU_FI2C_SCFG1_RESERVED_8                                , 4   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_8 );
+REG64_FLD( PU_FI2C_SCFG1_RESERVED_8_LEN                            , 4   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_8_LEN );
+REG64_FLD( PU_FI2C_SCFG1_DEVICE_ID                                 , 8   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_DEVICE_ID  );
+REG64_FLD( PU_FI2C_SCFG1_DEVICE_ID_LEN                             , 7   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_DEVICE_ID_LEN );
+REG64_FLD( PU_FI2C_SCFG1_ECC_ENABLE                                , 15  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_ECC_ENABLE );
+REG64_FLD( PU_FI2C_SCFG1_MEMORY_SIZE_IN_PPE_ADDR_MAP               , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP );
+REG64_FLD( PU_FI2C_SCFG1_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN           , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN );
+REG64_FLD( PU_FI2C_SCFG1_START_SEEPROM_ADDRESS                     , 32  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_SEEPROM_ADDRESS );
+REG64_FLD( PU_FI2C_SCFG1_START_SEEPROM_ADDRESS_LEN                 , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_SEEPROM_ADDRESS_LEN );
+REG64_FLD( PU_FI2C_SCFG1_START_PPE_ADDR                            , 48  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_PPE_ADDR );
+REG64_FLD( PU_FI2C_SCFG1_START_PPE_ADDR_LEN                        , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_PPE_ADDR_LEN );
+
+REG64_FLD( PU_FI2C_SCFG2_REGISTER_VALID                            , 0   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_REGISTER_VALID );
+REG64_FLD( PU_FI2C_SCFG2_RESERVED_9                                , 1   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_9 );
+REG64_FLD( PU_FI2C_SCFG2_RESERVED_10                               , 2   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_10 );
+REG64_FLD( PU_FI2C_SCFG2_RESERVED_10_LEN                           , 2   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_10_LEN );
+REG64_FLD( PU_FI2C_SCFG2_RESERVED_11                               , 4   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_11 );
+REG64_FLD( PU_FI2C_SCFG2_RESERVED_11_LEN                           , 4   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_11_LEN );
+REG64_FLD( PU_FI2C_SCFG2_DEVICE_ID                                 , 8   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_DEVICE_ID  );
+REG64_FLD( PU_FI2C_SCFG2_DEVICE_ID_LEN                             , 7   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_DEVICE_ID_LEN );
+REG64_FLD( PU_FI2C_SCFG2_ECC_ENABLE                                , 15  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_ECC_ENABLE );
+REG64_FLD( PU_FI2C_SCFG2_MEMORY_SIZE_IN_PPE_ADDR_MAP               , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP );
+REG64_FLD( PU_FI2C_SCFG2_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN           , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN );
+REG64_FLD( PU_FI2C_SCFG2_START_SEEPROM_ADDRESS                     , 32  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_SEEPROM_ADDRESS );
+REG64_FLD( PU_FI2C_SCFG2_START_SEEPROM_ADDRESS_LEN                 , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_SEEPROM_ADDRESS_LEN );
+REG64_FLD( PU_FI2C_SCFG2_START_PPE_ADDR                            , 48  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_PPE_ADDR );
+REG64_FLD( PU_FI2C_SCFG2_START_PPE_ADDR_LEN                        , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_PPE_ADDR_LEN );
+
+REG64_FLD( PU_FI2C_SCFG3_REGISTER_VALID                            , 0   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_REGISTER_VALID );
+REG64_FLD( PU_FI2C_SCFG3_RESERVED_12                               , 1   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_12 );
+REG64_FLD( PU_FI2C_SCFG3_RESERVED_13                               , 2   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_13 );
+REG64_FLD( PU_FI2C_SCFG3_RESERVED_13_LEN                           , 2   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_13_LEN );
+REG64_FLD( PU_FI2C_SCFG3_RESERVED_14                               , 4   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_14 );
+REG64_FLD( PU_FI2C_SCFG3_RESERVED_14_LEN                           , 4   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_14_LEN );
+REG64_FLD( PU_FI2C_SCFG3_DEVICE_ID                                 , 8   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_DEVICE_ID  );
+REG64_FLD( PU_FI2C_SCFG3_DEVICE_ID_LEN                             , 7   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_DEVICE_ID_LEN );
+REG64_FLD( PU_FI2C_SCFG3_ECC_ENABLE                                , 15  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_ECC_ENABLE );
+REG64_FLD( PU_FI2C_SCFG3_MEMORY_SIZE_IN_PPE_ADDR_MAP               , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP );
+REG64_FLD( PU_FI2C_SCFG3_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN           , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN );
+REG64_FLD( PU_FI2C_SCFG3_START_SEEPROM_ADDRESS                     , 32  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_SEEPROM_ADDRESS );
+REG64_FLD( PU_FI2C_SCFG3_START_SEEPROM_ADDRESS_LEN                 , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_SEEPROM_ADDRESS_LEN );
+REG64_FLD( PU_FI2C_SCFG3_START_PPE_ADDR                            , 48  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_PPE_ADDR );
+REG64_FLD( PU_FI2C_SCFG3_START_PPE_ADDR_LEN                        , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_START_PPE_ADDR_LEN );
+
+REG64_FLD( PU_FI2C_STAT_PIB_RESPONSE_INFO                          , 0   , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_PIB_RESPONSE_INFO );
+REG64_FLD( PU_FI2C_STAT_PIB_RESPONSE_INFO_LEN                      , 3   , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_PIB_RESPONSE_INFO_LEN );
+REG64_FLD( PU_FI2C_STAT_I2CM_PIB_ERRORS                            , 3   , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_I2CM_PIB_ERRORS );
+REG64_FLD( PU_FI2C_STAT_I2CM_PIB_ERRORS_LEN                        , 6   , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_I2CM_PIB_ERRORS_LEN );
+REG64_FLD( PU_FI2C_STAT_I2CM_ECC_ERRORS                            , 9   , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_I2CM_ECC_ERRORS );
+REG64_FLD( PU_FI2C_STAT_I2CM_ECC_ERRORS_LEN                        , 3   , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_I2CM_ECC_ERRORS_LEN );
+REG64_FLD( PU_FI2C_STAT_I2CM_I2C_ERRORS                            , 12  , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_I2CM_I2C_ERRORS );
+REG64_FLD( PU_FI2C_STAT_I2CM_I2C_ERRORS_LEN                        , 7   , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_I2CM_I2C_ERRORS_LEN );
+REG64_FLD( PU_FI2C_STAT_ERR_ADDR_BEYOND_RANGE                      , 19  , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_ERR_ADDR_BEYOND_RANGE );
+REG64_FLD( PU_FI2C_STAT_ERR_ADDR_OVERLAP                           , 20  , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_ERR_ADDR_OVERLAP );
+REG64_FLD( PU_FI2C_STAT_PIB_ABORT                                  , 21  , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_PIB_ABORT  );
+REG64_FLD( PU_FI2C_STAT_TIMEOUT_ON_I2C_STATUS_RD                   , 22  , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_TIMEOUT_ON_I2C_STATUS_RD );
+REG64_FLD( PU_FI2C_STAT_RESERVED_FOR_ERRS                          , 23  , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_FOR_ERRS );
+REG64_FLD( PU_FI2C_STAT_RESERVED_FOR_ERRS_LEN                      , 9   , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_FOR_ERRS_LEN );
+REG64_FLD( PU_FI2C_STAT_LOCKED_PIBM_ADDR                           , 32  , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_LOCKED_PIBM_ADDR );
+REG64_FLD( PU_FI2C_STAT_LOCKED_PIBM_ADDR_LEN                       , 8   , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_LOCKED_PIBM_ADDR_LEN );
+REG64_FLD( PU_FI2C_STAT_LOCKED_FSM_RESET_ONGOING                   , 40  , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_LOCKED_FSM_RESET_ONGOING );
+REG64_FLD( PU_FI2C_STAT_RESERVED_FOR_ADDRESS                       , 41  , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_FOR_ADDRESS );
+REG64_FLD( PU_FI2C_STAT_RESERVED_FOR_ADDRESS_LEN                   , 2   , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_RESERVED_FOR_ADDRESS_LEN );
+REG64_FLD( PU_FI2C_STAT_LOCKED_FSM_STATE                           , 43  , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_LOCKED_FSM_STATE );
+REG64_FLD( PU_FI2C_STAT_LOCKED_FSM_STATE_LEN                       , 5   , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_LOCKED_FSM_STATE_LEN );
+REG64_FLD( PU_FI2C_STAT_LOCKED_SEEPROM_ADDRESS                     , 48  , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_LOCKED_SEEPROM_ADDRESS );
+REG64_FLD( PU_FI2C_STAT_LOCKED_SEEPROM_ADDRESS_LEN                 , 16  , SH_UNT          , SH_ACS_PPE      ,
+           SH_FLD_LOCKED_SEEPROM_ADDRESS_LEN );
+
+REG64_FLD( PU_FIFO1_REGISTER_READ_B_FIFO_BITS_READ0_0              , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_0 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_B_FIFO_BITS_READ0_0_LEN          , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_0_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_B_PEEK_DATA1_0                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_B_PEEK_DATA1_0_LEN               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_B_LBUS_PARITY_ERR1_0             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_FIFO1_REGISTER_READ_C_FIFO_BITS_READ0_1              , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_1 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_C_FIFO_BITS_READ0_1_LEN          , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_1_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_C_PEEK_DATA1_1                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_C_PEEK_DATA1_1_LEN               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_C_LBUS_PARITY_ERR1_1             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_FIFO1_REGISTER_READ_D_FIFO_BITS_READ0_2              , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_2 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_D_FIFO_BITS_READ0_2_LEN          , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_2_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_D_PEEK_DATA1_2                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_D_PEEK_DATA1_2_LEN               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_D_LBUS_PARITY_ERR1_2             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_FIFO1_REGISTER_READ_E_FIFO_BITS_READ0_3              , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_3 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_E_FIFO_BITS_READ0_3_LEN          , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_3_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_E_PEEK_DATA1_3                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_FIFO1_REGISTER_READ_E_PEEK_DATA1_3_LEN               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_FIFO1_REGISTER_READ_E_LBUS_PARITY_ERR1_3             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ0_0              , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_0 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ0_0_LEN          , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_0_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_B_PEEK_DATA1_0                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_B_PEEK_DATA1_0_LEN               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_B_LBUS_PARITY_ERR1_0             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ0_1              , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_1 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ0_1_LEN          , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_1_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_C_PEEK_DATA1_1                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_C_PEEK_DATA1_1_LEN               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_C_LBUS_PARITY_ERR1_1             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ0_2              , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_2 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ0_2_LEN          , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_2_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_D_PEEK_DATA1_2                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_D_PEEK_DATA1_2_LEN               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_D_LBUS_PARITY_ERR1_2             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ0_3              , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_3 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ0_3_LEN          , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_3_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3_LEN               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_FIFO4_REGISTER_READ_E_LBUS_PARITY_ERR1_3             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( CAPP_FIR_ACTION0_REG_ACTION0                            , 0   , SH_UNT_CAPP     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( CAPP_FIR_ACTION0_REG_ACTION0_LEN                        , 52  , SH_UNT_CAPP     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PEC_FIR_ACTION0_REG_ACTION0                             , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( PEC_FIR_ACTION0_REG_ACTION0_LEN                         , 37  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_FIR_ACTION0_REG_ACTION0                              , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( PU_FIR_ACTION0_REG_ACTION0_LEN                          , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION0_REG_0_0                      , 0   , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_0          );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION0_REG_0_0_LEN                  , 64  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_0_LEN      );
+
+REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION0_REG_1_1                      , 0   , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_RW  ,
+           SH_FLD_1          );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION0_REG_1_1_LEN                  , 64  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_RW  ,
+           SH_FLD_1_LEN      );
+
+REG64_FLD( CAPP_FIR_ACTION1_REG_ACTION1                            , 0   , SH_UNT_CAPP     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( CAPP_FIR_ACTION1_REG_ACTION1_LEN                        , 52  , SH_UNT_CAPP     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PEC_FIR_ACTION1_REG_ACTION1                             , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( PEC_FIR_ACTION1_REG_ACTION1_LEN                         , 37  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_FIR_ACTION1_REG_ACTION1                              , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( PU_FIR_ACTION1_REG_ACTION1_LEN                          , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION1_REG_0_0                      , 0   , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_0          );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION1_REG_0_0_LEN                  , 64  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_0_LEN      );
+
+REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION1_REG_1_1                      , 0   , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_RW  ,
+           SH_FLD_1          );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION1_REG_1_1_LEN                  , 64  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_RW  ,
+           SH_FLD_1_LEN      );
+
+REG64_FLD( PEC_FIR_MASK_IN0                                        , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( PEC_FIR_MASK_IN1                                        , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN1        );
+REG64_FLD( PEC_FIR_MASK_IN2                                        , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN2        );
+REG64_FLD( PEC_FIR_MASK_IN3                                        , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN3        );
+REG64_FLD( PEC_FIR_MASK_IN4                                        , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( PEC_FIR_MASK_IN5                                        , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( PEC_FIR_MASK_IN6                                        , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN6        );
+REG64_FLD( PEC_FIR_MASK_IN6_LEN                                    , 20  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN6_LEN    );
+REG64_FLD( PEC_FIR_MASK_IN26                                       , 26  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN26       );
+
+REG64_FLD( CAPP_FIR_MASK_REG_BAR_PE                                , 0   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_BAR_PE     );
+REG64_FLD( CAPP_FIR_MASK_REG_REGISTER_PE                           , 1   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_REGISTER_PE );
+REG64_FLD( CAPP_FIR_MASK_REG_MASTER_ARRAY_CE                       , 2   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASTER_ARRAY_CE );
+REG64_FLD( CAPP_FIR_MASK_REG_MASTER_ARRAY_UE                       , 3   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASTER_ARRAY_UE );
+REG64_FLD( CAPP_FIR_MASK_REG_TIMER_EXPIRED_RECOV_ERROR             , 4   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TIMER_EXPIRED_RECOV_ERROR );
+REG64_FLD( CAPP_FIR_MASK_REG_TIMER_EXPIRED_XSTOP_ERROR             , 5   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TIMER_EXPIRED_XSTOP_ERROR );
+REG64_FLD( CAPP_FIR_MASK_REG_PSL_CMD_UE                            , 6   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSL_CMD_UE );
+REG64_FLD( CAPP_FIR_MASK_REG_PSL_CMD_SUE                           , 7   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSL_CMD_SUE );
+REG64_FLD( CAPP_FIR_MASK_REG_SNOOP_ARRAY_CE                        , 8   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SNOOP_ARRAY_CE );
+REG64_FLD( CAPP_FIR_MASK_REG_SNOOP_ARRAY_UE                        , 9   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SNOOP_ARRAY_UE );
+REG64_FLD( CAPP_FIR_MASK_REG_RECOVERY_FAILED                       , 10  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_RECOVERY_FAILED );
+REG64_FLD( CAPP_FIR_MASK_REG_ILLEGAL_LPC_BAR_ACCESS                , 11  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_ILLEGAL_LPC_BAR_ACCESS );
+REG64_FLD( CAPP_FIR_MASK_REG_XPT_RECOVERABLE_ERROR                 , 12  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_XPT_RECOVERABLE_ERROR );
+REG64_FLD( CAPP_FIR_MASK_REG_MASTER_RECOVERABLE_ERROR              , 13  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASTER_RECOVERABLE_ERROR );
+REG64_FLD( CAPP_FIR_MASK_REG_SNOOPER_RECOVERABLE_ERROR             , 14  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SNOOPER_RECOVERABLE_ERROR );
+REG64_FLD( CAPP_FIR_MASK_REG_SECURE_SCOM_ERROR                     , 15  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SECURE_SCOM_ERROR );
+REG64_FLD( CAPP_FIR_MASK_REG_MASTER_SYS_XSTOP_ERROR                , 16  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASTER_SYS_XSTOP_ERROR );
+REG64_FLD( CAPP_FIR_MASK_REG_SNOOPER_SYS_XSTOP_ERROR               , 17  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SNOOPER_SYS_XSTOP_ERROR );
+REG64_FLD( CAPP_FIR_MASK_REG_XPT_SYS_XSTOP_ERROR                   , 18  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_XPT_SYS_XSTOP_ERROR );
+REG64_FLD( CAPP_FIR_MASK_REG_MUOP_ERROR_1                          , 19  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_MUOP_ERROR_1 );
+REG64_FLD( CAPP_FIR_MASK_REG_MUOP_ERROR_2                          , 20  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_MUOP_ERROR_2 );
+REG64_FLD( CAPP_FIR_MASK_REG_MUOP_ERROR_3                          , 21  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_MUOP_ERROR_3 );
+REG64_FLD( CAPP_FIR_MASK_REG_SUOP_ERROR_1                          , 22  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SUOP_ERROR_1 );
+REG64_FLD( CAPP_FIR_MASK_REG_SUOP_ERROR_2                          , 23  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SUOP_ERROR_2 );
+REG64_FLD( CAPP_FIR_MASK_REG_SUOP_ERROR_3                          , 24  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SUOP_ERROR_3 );
+REG64_FLD( CAPP_FIR_MASK_REG_POWERBUS_MISC_ERROR                   , 25  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_POWERBUS_MISC_ERROR );
+REG64_FLD( CAPP_FIR_MASK_REG_POWERBUS_INTERFACE_PE                 , 26  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_POWERBUS_INTERFACE_PE );
+REG64_FLD( CAPP_FIR_MASK_REG_POWERBUS_DATA_HANG_ERROR              , 27  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_POWERBUS_DATA_HANG_ERROR );
+REG64_FLD( CAPP_FIR_MASK_REG_POWERBUS_HANG_ERROR                   , 28  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_POWERBUS_HANG_ERROR );
+REG64_FLD( CAPP_FIR_MASK_REG_LD_CLASS_CMD_ADDR_ERR                 , 29  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LD_CLASS_CMD_ADDR_ERR );
+REG64_FLD( CAPP_FIR_MASK_REG_ST_CLASS_CMD_ADDR_ERR                 , 30  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_ST_CLASS_CMD_ADDR_ERR );
+REG64_FLD( CAPP_FIR_MASK_REG_PHB_LINK_DOWN                         , 31  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_PHB_LINK_DOWN );
+REG64_FLD( CAPP_FIR_MASK_REG_LD_CLASS_CMD_FOREIGN_LINK_FAIL        , 32  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LD_CLASS_CMD_FOREIGN_LINK_FAIL );
+REG64_FLD( CAPP_FIR_MASK_REG_FOREIGN_LINK_HANG_ERROR               , 33  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_FOREIGN_LINK_HANG_ERROR );
+REG64_FLD( CAPP_FIR_MASK_REG_XPT_POWERBUS_CE                       , 34  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_XPT_POWERBUS_CE );
+REG64_FLD( CAPP_FIR_MASK_REG_XPT_POWERBUS_UE                       , 35  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_XPT_POWERBUS_UE );
+REG64_FLD( CAPP_FIR_MASK_REG_XPT_POWERBUS_SUE                      , 36  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_XPT_POWERBUS_SUE );
+REG64_FLD( CAPP_FIR_MASK_REG_TLBI_TIMEOUT                          , 37  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBI_TIMEOUT );
+REG64_FLD( CAPP_FIR_MASK_REG_TLBI_SOT_ERR                          , 38  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBI_SOT_ERR );
+REG64_FLD( CAPP_FIR_MASK_REG_TLBI_BAD_OP_ERR                       , 39  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBI_BAD_OP_ERR );
+REG64_FLD( CAPP_FIR_MASK_REG_TLBI_SEQ_NUM_PARITY_ERR               , 40  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBI_SEQ_NUM_PARITY_ERR );
+REG64_FLD( CAPP_FIR_MASK_REG_ST_CLASS_CMD_FOREIGN_LINK_FAIL        , 41  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_ST_CLASS_CMD_FOREIGN_LINK_FAIL );
+REG64_FLD( CAPP_FIR_MASK_REG_TIME_BASE_ERR                         , 42  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TIME_BASE_ERR );
+REG64_FLD( CAPP_FIR_MASK_REG_TRANSPORT_INFORMATIONAL_ERR           , 43  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TRANSPORT_INFORMATIONAL_ERR );
+REG64_FLD( CAPP_FIR_MASK_REG_APC_ARRAY_CMD_CE_ERPT                 , 44  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_APC_ARRAY_CMD_CE_ERPT );
+REG64_FLD( CAPP_FIR_MASK_REG_APC_ARRAY_CMD_UE_ERPT                 , 45  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_APC_ARRAY_CMD_UE_ERPT );
+REG64_FLD( CAPP_FIR_MASK_REG_PSL_CREDIT_TIMEOUT_ERR                , 46  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSL_CREDIT_TIMEOUT_ERR );
+REG64_FLD( CAPP_FIR_MASK_REG_SPARE_2                               , 47  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_2    );
+REG64_FLD( CAPP_FIR_MASK_REG_SPARE_3                               , 48  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_3    );
+REG64_FLD( CAPP_FIR_MASK_REG_HYPERVISOR                            , 49  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_HYPERVISOR );
+REG64_FLD( CAPP_FIR_MASK_REG_SCOM_ERR2                             , 50  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR2  );
+REG64_FLD( CAPP_FIR_MASK_REG_SCOM_ERR                              , 51  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+
+REG64_FLD( PEC_FIR_MASK_REG_HSSCALERR                              , 0   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_HSSCALERR  );
+REG64_FLD( PEC_FIR_MASK_REG_HSSPLLAERR                             , 1   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_HSSPLLAERR );
+REG64_FLD( PEC_FIR_MASK_REG_HSSPLLBERR                             , 2   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_HSSPLLBERR );
+REG64_FLD( PEC_FIR_MASK_REG_TXAERR                                 , 3   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXAERR     );
+REG64_FLD( PEC_FIR_MASK_REG_TXBERR                                 , 4   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXBERR     );
+REG64_FLD( PEC_FIR_MASK_REG_TXCERR                                 , 5   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXCERR     );
+REG64_FLD( PEC_FIR_MASK_REG_TXDERR                                 , 6   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXDERR     );
+REG64_FLD( PEC_FIR_MASK_REG_TXEERR                                 , 7   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXEERR     );
+REG64_FLD( PEC_FIR_MASK_REG_TXFERR                                 , 8   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXFERR     );
+REG64_FLD( PEC_FIR_MASK_REG_TXGERR                                 , 9   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXGERR     );
+REG64_FLD( PEC_FIR_MASK_REG_TXHERR                                 , 10  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXHERR     );
+REG64_FLD( PEC_FIR_MASK_REG_TXIERR                                 , 11  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXIERR     );
+REG64_FLD( PEC_FIR_MASK_REG_TXJERR                                 , 12  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXJERR     );
+REG64_FLD( PEC_FIR_MASK_REG_TXKERR                                 , 13  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXKERR     );
+REG64_FLD( PEC_FIR_MASK_REG_TXLERR                                 , 14  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXLERR     );
+REG64_FLD( PEC_FIR_MASK_REG_TXMERR                                 , 15  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXMERR     );
+REG64_FLD( PEC_FIR_MASK_REG_TXNERR                                 , 16  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXNERR     );
+REG64_FLD( PEC_FIR_MASK_REG_TXOERR                                 , 17  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXOERR     );
+REG64_FLD( PEC_FIR_MASK_REG_TXPERR                                 , 18  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXPERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXAERR                                 , 19  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXAERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXBERR                                 , 20  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXBERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXCERR                                 , 21  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXCERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXDERR                                 , 22  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXDERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXEERR                                 , 23  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXEERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXFERR                                 , 24  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXFERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXGERR                                 , 25  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXGERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXHERR                                 , 26  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXHERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXIERR                                 , 27  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXIERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXJERR                                 , 28  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXJERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXKERR                                 , 29  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXKERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXLERR                                 , 30  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXLERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXMERR                                 , 31  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXMERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXNERR                                 , 32  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXNERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXOERR                                 , 33  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXOERR     );
+REG64_FLD( PEC_FIR_MASK_REG_RXPERR                                 , 34  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXPERR     );
+REG64_FLD( PEC_FIR_MASK_REG_SCOM_PERR0                             , 35  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PERR0 );
+REG64_FLD( PEC_FIR_MASK_REG_SCOM_PERR1                             , 36  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PERR1 );
+
+REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED0                           , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSI_RESERVED0 );
+REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED1                           , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSI_RESERVED1 );
+REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED2                           , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSI_RESERVED2 );
+REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED3                           , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSI_RESERVED3 );
+REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED4                           , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSI_RESERVED4 );
+REG64_FLD( PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR                     , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_SCOM_ERROR );
+REG64_FLD( PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE               , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_SCOM_ERROR_CLONE );
+
+REG64_FLD( PU_FIR_MASK_REGISTER_ECC_UNCORRECTED_ERR_PIB            , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_UNCORRECTED_ERR_PIB );
+REG64_FLD( PU_FIR_MASK_REGISTER_BAD_ARRAY_ADDR_PIB                 , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAD_ARRAY_ADDR_PIB );
+REG64_FLD( PU_FIR_MASK_REGISTER_WRT_RST_INTRPT_PIB                 , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WRT_RST_INTRPT_PIB );
+REG64_FLD( PU_FIR_MASK_REGISTER_RD_RST_INTRPT_PIB                  , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RD_RST_INTRPT_PIB );
+REG64_FLD( PU_FIR_MASK_REGISTER_ECC_UNCORRECTED_ERR_FACES          , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_UNCORRECTED_ERR_FACES );
+REG64_FLD( PU_FIR_MASK_REGISTER_BAD_ARRAY_ADDR_FACES               , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAD_ARRAY_ADDR_FACES );
+REG64_FLD( PU_FIR_MASK_REGISTER_WRT_RST_INTRPT_FACES               , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WRT_RST_INTRPT_FACES );
+REG64_FLD( PU_FIR_MASK_REGISTER_RD_RST_INTRPT_FACES                , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RD_RST_INTRPT_FACES );
+
+REG64_FLD( PU_NPU_MSC_SM0_FIR_MASK_REG_0_0                         , 0   , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_0          );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_MASK_REG_0_0_LEN                     , 64  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_0_LEN      );
+
+REG64_FLD( PU_NPU_MSC_SM2_FIR_MASK_REG_1_1                         , 0   , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_1          );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_MASK_REG_1_1_LEN                     , 64  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_1_LEN      );
+
+REG64_FLD( CAPP_FIR_REG_BAR_PE                                     , 0   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_BAR_PE     );
+REG64_FLD( CAPP_FIR_REG_REGISTER_PE                                , 1   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_REGISTER_PE );
+REG64_FLD( CAPP_FIR_REG_MASTER_ARRAY_CE                            , 2   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASTER_ARRAY_CE );
+REG64_FLD( CAPP_FIR_REG_MASTER_ARRAY_UE                            , 3   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASTER_ARRAY_UE );
+REG64_FLD( CAPP_FIR_REG_TIMER_EXPIRED_RECOV_ERROR                  , 4   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TIMER_EXPIRED_RECOV_ERROR );
+REG64_FLD( CAPP_FIR_REG_TIMER_EXPIRED_XSTOP_ERROR                  , 5   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TIMER_EXPIRED_XSTOP_ERROR );
+REG64_FLD( CAPP_FIR_REG_PSL_CMD_UE                                 , 6   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSL_CMD_UE );
+REG64_FLD( CAPP_FIR_REG_PSL_CMD_SUE                                , 7   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSL_CMD_SUE );
+REG64_FLD( CAPP_FIR_REG_SNOOP_ARRAY_CE                             , 8   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SNOOP_ARRAY_CE );
+REG64_FLD( CAPP_FIR_REG_SNOOP_ARRAY_UE                             , 9   , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SNOOP_ARRAY_UE );
+REG64_FLD( CAPP_FIR_REG_RECOVERY_FAILED                            , 10  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_RECOVERY_FAILED );
+REG64_FLD( CAPP_FIR_REG_ILLEGAL_LPC_BAR_ACCESS                     , 11  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_ILLEGAL_LPC_BAR_ACCESS );
+REG64_FLD( CAPP_FIR_REG_XPT_RECOVERABLE_ERROR                      , 12  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_XPT_RECOVERABLE_ERROR );
+REG64_FLD( CAPP_FIR_REG_MASTER_RECOVERABLE_ERROR                   , 13  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASTER_RECOVERABLE_ERROR );
+REG64_FLD( CAPP_FIR_REG_SNOOPER_RECOVERABLE_ERROR                  , 14  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SNOOPER_RECOVERABLE_ERROR );
+REG64_FLD( CAPP_FIR_REG_SECURE_SCOM_ERROR                          , 15  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SECURE_SCOM_ERROR );
+REG64_FLD( CAPP_FIR_REG_MASTER_SYS_XSTOP_ERROR                     , 16  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASTER_SYS_XSTOP_ERROR );
+REG64_FLD( CAPP_FIR_REG_SNOOPER_SYS_XSTOP_ERROR                    , 17  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SNOOPER_SYS_XSTOP_ERROR );
+REG64_FLD( CAPP_FIR_REG_XPT_SYS_XSTOP_ERROR                        , 18  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_XPT_SYS_XSTOP_ERROR );
+REG64_FLD( CAPP_FIR_REG_MUOP_ERROR_1                               , 19  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_MUOP_ERROR_1 );
+REG64_FLD( CAPP_FIR_REG_MUOP_ERROR_2                               , 20  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_MUOP_ERROR_2 );
+REG64_FLD( CAPP_FIR_REG_MUOP_ERROR_3                               , 21  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_MUOP_ERROR_3 );
+REG64_FLD( CAPP_FIR_REG_SUOP_ERROR_1                               , 22  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SUOP_ERROR_1 );
+REG64_FLD( CAPP_FIR_REG_SUOP_ERROR_2                               , 23  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SUOP_ERROR_2 );
+REG64_FLD( CAPP_FIR_REG_SUOP_ERROR_3                               , 24  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SUOP_ERROR_3 );
+REG64_FLD( CAPP_FIR_REG_POWERBUS_MISC_ERROR                        , 25  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_POWERBUS_MISC_ERROR );
+REG64_FLD( CAPP_FIR_REG_POWERBUS_INTERFACE_PE                      , 26  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_POWERBUS_INTERFACE_PE );
+REG64_FLD( CAPP_FIR_REG_POWERBUS_DATA_HANG_ERROR                   , 27  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_POWERBUS_DATA_HANG_ERROR );
+REG64_FLD( CAPP_FIR_REG_POWERBUS_HANG_ERROR                        , 28  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_POWERBUS_HANG_ERROR );
+REG64_FLD( CAPP_FIR_REG_LD_CLASS_CMD_ADDR_ERR                      , 29  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LD_CLASS_CMD_ADDR_ERR );
+REG64_FLD( CAPP_FIR_REG_ST_CLASS_CMD_ADDR_ERR                      , 30  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_ST_CLASS_CMD_ADDR_ERR );
+REG64_FLD( CAPP_FIR_REG_PHB_LINK_DOWN                              , 31  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_PHB_LINK_DOWN );
+REG64_FLD( CAPP_FIR_REG_LD_CLASS_CMD_FOREIGN_LINK_FAIL             , 32  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LD_CLASS_CMD_FOREIGN_LINK_FAIL );
+REG64_FLD( CAPP_FIR_REG_FOREIGN_LINK_HANG_ERROR                    , 33  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_FOREIGN_LINK_HANG_ERROR );
+REG64_FLD( CAPP_FIR_REG_XPT_POWERBUS_CE                            , 34  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_XPT_POWERBUS_CE );
+REG64_FLD( CAPP_FIR_REG_XPT_POWERBUS_UE                            , 35  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_XPT_POWERBUS_UE );
+REG64_FLD( CAPP_FIR_REG_XPT_POWERBUS_SUE                           , 36  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_XPT_POWERBUS_SUE );
+REG64_FLD( CAPP_FIR_REG_TLBI_TIMEOUT                               , 37  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBI_TIMEOUT );
+REG64_FLD( CAPP_FIR_REG_TLBI_SOT_ERR                               , 38  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBI_SOT_ERR );
+REG64_FLD( CAPP_FIR_REG_TLBI_BAD_OP_ERR                            , 39  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBI_BAD_OP_ERR );
+REG64_FLD( CAPP_FIR_REG_TLBI_SEQ_NUM_PARITY_ERR                    , 40  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBI_SEQ_NUM_PARITY_ERR );
+REG64_FLD( CAPP_FIR_REG_ST_CLASS_CMD_FOREIGN_LINK_FAIL             , 41  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_ST_CLASS_CMD_FOREIGN_LINK_FAIL );
+REG64_FLD( CAPP_FIR_REG_TIME_BASE_ERR                              , 42  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TIME_BASE_ERR );
+REG64_FLD( CAPP_FIR_REG_TRANSPORT_INFORMATIONAL_ERR                , 43  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_TRANSPORT_INFORMATIONAL_ERR );
+REG64_FLD( CAPP_FIR_REG_APC_ARRAY_CMD_CE_ERPT                      , 44  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_APC_ARRAY_CMD_CE_ERPT );
+REG64_FLD( CAPP_FIR_REG_APC_ARRAY_CMD_UE_ERPT                      , 45  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_APC_ARRAY_CMD_UE_ERPT );
+REG64_FLD( CAPP_FIR_REG_PSL_CREDIT_TIMEOUT_ERR                     , 46  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSL_CREDIT_TIMEOUT_ERR );
+REG64_FLD( CAPP_FIR_REG_SPARE_2                                    , 47  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_2    );
+REG64_FLD( CAPP_FIR_REG_HYPERVISOR                                 , 48  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_HYPERVISOR );
+REG64_FLD( CAPP_FIR_REG_SPARE_3                                    , 49  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_3    );
+REG64_FLD( CAPP_FIR_REG_SCOM_ERR2                                  , 50  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR2  );
+REG64_FLD( CAPP_FIR_REG_SCOM_ERR                                   , 51  , SH_UNT_CAPP     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+
+REG64_FLD( PU_FIR_REG_PSI_RESERVED0                                , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSI_RESERVED0 );
+REG64_FLD( PU_FIR_REG_PSI_RESERVED1                                , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSI_RESERVED1 );
+REG64_FLD( PU_FIR_REG_PSI_RESERVED2                                , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSI_RESERVED2 );
+REG64_FLD( PU_FIR_REG_PSI_RESERVED3                                , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSI_RESERVED3 );
+REG64_FLD( PU_FIR_REG_PSI_RESERVED4                                , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSI_RESERVED4 );
+REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR                          , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_SCOM_ERROR );
+REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR_CLONE                    , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_SCOM_ERROR_CLONE );
+
+REG64_FLD( PHB_FIR_REG_AIB_COMMAND_INVALID                         , 0   , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_AIB_COMMAND_INVALID );
+REG64_FLD( PHB_FIR_REG_AIB_ADDRESS_INVALID                         , 1   , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_AIB_ADDRESS_INVALID );
+REG64_FLD( PHB_FIR_REG_AIB_ACCESS_ERROR                            , 2   , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_AIB_ACCESS_ERROR );
+REG64_FLD( PHB_FIR_REG_PAPR_OUTBOUND_INJECT_ERROR                  , 3   , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_PAPR_OUTBOUND_INJECT_ERROR );
+REG64_FLD( PHB_FIR_REG_AIB_FATAL_CLASS_ERROR                       , 4   , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_AIB_FATAL_CLASS_ERROR );
+REG64_FLD( PHB_FIR_REG_AIB_INF_CLASS_ERROR                         , 6   , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_AIB_INF_CLASS_ERROR );
+REG64_FLD( PHB_FIR_REG_PE_STOP_STATE_SIGNALED                      , 7   , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_PE_STOP_STATE_SIGNALED );
+REG64_FLD( PHB_FIR_REG_OUT_COMMON_ARRAY_FATAL_ERROR                , 8   , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR );
+REG64_FLD( PHB_FIR_REG_OUT_COMMON_LATCH_FATAL_ERROR                , 9   , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR );
+REG64_FLD( PHB_FIR_REG_OUT_COMMON_LOGIC_FATAL_ERROR                , 10  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR );
+REG64_FLD( PHB_FIR_REG_BLIF_OUT_INTERFACE_PARITY_ERROR             , 11  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR );
+REG64_FLD( PHB_FIR_REG_CFG_WRITE_CA_OR_UR_RESPONSE                 , 12  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_CFG_WRITE_CA_OR_UR_RESPONSE );
+REG64_FLD( PHB_FIR_REG_MMIO_REQUEST_TIMEOUT                        , 13  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MMIO_REQUEST_TIMEOUT );
+REG64_FLD( PHB_FIR_REG_OUT_RRB_SOURCED_ERROR                       , 14  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_OUT_RRB_SOURCED_ERROR );
+REG64_FLD( PHB_FIR_REG_CFG_LOGIC_SIGNALED_ERROR                    , 15  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_CFG_LOGIC_SIGNALED_ERROR );
+REG64_FLD( PHB_FIR_REG_RSB_REQUEST_ADDRESS_ERROR                   , 16  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSB_REQUEST_ADDRESS_ERROR );
+REG64_FLD( PHB_FIR_REG_RSB_FDA_FATAL_ERROR                         , 17  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSB_FDA_FATAL_ERROR );
+REG64_FLD( PHB_FIR_REG_RSB_FDA_INF_ERROR                           , 18  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSB_FDA_INF_ERROR );
+REG64_FLD( PHB_FIR_REG_RSB_FDB_FATAL_ERROR                         , 19  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSB_FDB_FATAL_ERROR );
+REG64_FLD( PHB_FIR_REG_RSB_FDB_INF_ERROR                           , 20  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSB_FDB_INF_ERROR );
+REG64_FLD( PHB_FIR_REG_RSB_ERR_FATAL_ERROR                         , 21  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSB_ERR_FATAL_ERROR );
+REG64_FLD( PHB_FIR_REG_RSB_ERR_INF_ERROR                           , 22  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSB_ERR_INF_ERROR );
+REG64_FLD( PHB_FIR_REG_RSB_DBG_FATAL_ERROR                         , 23  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSB_DBG_FATAL_ERROR );
+REG64_FLD( PHB_FIR_REG_RSB_DBG_INF_ERROR                           , 24  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSB_DBG_INF_ERROR );
+REG64_FLD( PHB_FIR_REG_PCIE_REQUEST_ACCESS_ERROR                   , 25  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_PCIE_REQUEST_ACCESS_ERROR );
+REG64_FLD( PHB_FIR_REG_RSB_BUS_LOGIC_ERROR                         , 26  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSB_BUS_LOGIC_ERROR );
+REG64_FLD( PHB_FIR_REG_RSB_UVI_FATAL_ERROR                         , 27  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSB_UVI_FATAL_ERROR );
+REG64_FLD( PHB_FIR_REG_RSB_UVI_INF_ERROR                           , 28  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSB_UVI_INF_ERROR );
+REG64_FLD( PHB_FIR_REG_SCOM_FATAL_ERROR                            , 29  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_FATAL_ERROR );
+REG64_FLD( PHB_FIR_REG_SCOM_INF_ERROR                              , 30  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_INF_ERROR );
+REG64_FLD( PHB_FIR_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS              , 31  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS );
+REG64_FLD( PHB_FIR_REG_ARB_IODA_FATAL_ERROR                        , 32  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARB_IODA_FATAL_ERROR );
+REG64_FLD( PHB_FIR_REG_ARB_MSI_PE_MATCH_ERROR                      , 33  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARB_MSI_PE_MATCH_ERROR );
+REG64_FLD( PHB_FIR_REG_ARB_MSI_ADDRESS_ERROR                       , 34  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARB_MSI_ADDRESS_ERROR );
+REG64_FLD( PHB_FIR_REG_ARB_TVT_ERROR                               , 35  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARB_TVT_ERROR );
+REG64_FLD( PHB_FIR_REG_ARB_RCVD_FATAL_ERROR_MSG                    , 36  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARB_RCVD_FATAL_ERROR_MSG );
+REG64_FLD( PHB_FIR_REG_ARB_RCVD_NONFATAL_ERROR_MSG                 , 37  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG );
+REG64_FLD( PHB_FIR_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG              , 38  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG );
+REG64_FLD( PHB_FIR_REG_PAPR_INBOUND_INJECT_ERROR                   , 39  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_PAPR_INBOUND_INJECT_ERROR );
+REG64_FLD( PHB_FIR_REG_ARB_COMMON_FATAL_ERROR                      , 40  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARB_COMMON_FATAL_ERROR );
+REG64_FLD( PHB_FIR_REG_ARB_TABLE_BAR_DISABLED_ERROR                , 41  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR );
+REG64_FLD( PHB_FIR_REG_ARB_BLIF_COMPLETION_ERROR                   , 42  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARB_BLIF_COMPLETION_ERROR );
+REG64_FLD( PHB_FIR_REG_ARB_PCT_TIMEOUT_ERROR                       , 43  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARB_PCT_TIMEOUT_ERROR );
+REG64_FLD( PHB_FIR_REG_ARB_ECC_CORRECTABLE_ERROR                   , 44  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARB_ECC_CORRECTABLE_ERROR );
+REG64_FLD( PHB_FIR_REG_ARB_ECC_UNCORRECTABLE_ERROR                 , 45  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR );
+REG64_FLD( PHB_FIR_REG_ARB_TLP_POISON_SIGNALED                     , 46  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARB_TLP_POISON_SIGNALED );
+REG64_FLD( PHB_FIR_REG_ARB_RTT_PENUM_INVALID_ERROR                 , 47  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARB_RTT_PENUM_INVALID_ERROR );
+REG64_FLD( PHB_FIR_REG_MRG_COMMON_FATAL_ERROR                      , 48  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MRG_COMMON_FATAL_ERROR );
+REG64_FLD( PHB_FIR_REG_MRG_TABLE_BAR_DISABLED_ERROR                , 49  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR );
+REG64_FLD( PHB_FIR_REG_MRG_ECC_CORRECTABLE_ERROR                   , 50  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MRG_ECC_CORRECTABLE_ERROR );
+REG64_FLD( PHB_FIR_REG_MRG_ECC_UNCORRECTABLE_ERROR                 , 51  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR );
+REG64_FLD( PHB_FIR_REG_MRG_AIB2_TX_TIMEOUT_ERROR                   , 52  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR );
+REG64_FLD( PHB_FIR_REG_MRG_MRT_ERROR                               , 53  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_MRG_MRT_ERROR );
+REG64_FLD( PHB_FIR_REG_TCE_IODA_PAGE_ACCESS_ERROR                  , 56  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR );
+REG64_FLD( PHB_FIR_REG_TCE_REQUEST_TIMEOUT_ERROR                   , 57  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TCE_REQUEST_TIMEOUT_ERROR );
+REG64_FLD( PHB_FIR_REG_TCE_UNEXPECTED_RESPONSE_ERROR               , 58  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR );
+REG64_FLD( PHB_FIR_REG_TCE_COMMON_FATAL_ERROR                      , 59  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TCE_COMMON_FATAL_ERROR );
+REG64_FLD( PHB_FIR_REG_TCE_ECC_CORRECTABLE_ERROR                   , 60  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TCE_ECC_CORRECTABLE_ERROR );
+REG64_FLD( PHB_FIR_REG_TCE_ECC_UNCORRECTABLE_ERROR                 , 61  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR );
+REG64_FLD( PHB_FIR_REG_INTERNAL_PARITY_ERROR                       , 63  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_PARITY_ERROR );
+
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_ARRAY_CE                   , 0   , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NTL_ARRAY_CE );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_ARRAY_HDR_UE               , 1   , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NTL_ARRAY_HDR_UE );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_ARRAY_DATA_UE              , 2   , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NTL_ARRAY_DATA_UE );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_FLIT_PERR              , 3   , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NTL_NVL_FLIT_PERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_DATA_PERR              , 4   , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NTL_NVL_DATA_PERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_PKT_MALFOR             , 5   , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NTL_NVL_PKT_MALFOR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_PKT_UNSUPPORTED        , 6   , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NTL_NVL_PKT_UNSUPPORTED );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_CONFIG_ERR             , 7   , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NTL_NVL_CONFIG_ERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_CRC_ERR                , 8   , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NTL_NVL_CRC_ERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_PRI_ERR                    , 9   , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NTL_PRI_ERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_LOGIC_ERR                  , 10  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NTL_LOGIC_ERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_LMD_POISON                 , 11  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NTL_LMD_POISON );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_ARRAY_DATA_SUE             , 12  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NTL_ARRAY_DATA_SUE );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_ARRAY_CE                   , 13  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CTL_ARRAY_CE );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PBUS_RECOV_ERR             , 14  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CTL_PBUS_RECOV_ERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_RING_ERR                   , 15  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CTL_RING_ERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_MMIO_ST_DATA_UE            , 16  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CTL_MMIO_ST_DATA_UE );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PEF                        , 17  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CTL_PEF    );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_NVL_CFG_ERR                , 18  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CTL_NVL_CFG_ERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_NVL_FATAL_ERR              , 19  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CTL_NVL_FATAL_ERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_RESERVED_1                     , 20  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_1 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_ARRAY_UE                   , 21  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CTL_ARRAY_UE );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PBUS_PERR                  , 22  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CTL_PBUS_PERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PBUS_FATAL_ERR             , 23  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CTL_PBUS_FATAL_ERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PBUS_CONFIG_ERR            , 24  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CTL_PBUS_CONFIG_ERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_FWD_PROGRESS_ERR           , 25  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CTL_FWD_PROGRESS_ERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_LOGIC_ERR                  , 26  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CTL_LOGIC_ERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PEST_DIS                   , 27  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CTL_PEST_DIS );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_RSVD_15                    , 28  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CTL_RSVD_15 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_DATA_BE_UE                 , 29  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_DAT_DATA_BE_UE );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_DATA_BE_CE                 , 30  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_DAT_DATA_BE_CE );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_DATA_BE_PERR               , 31  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_DAT_DATA_BE_PERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_CREG_PERR                  , 32  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_DAT_CREG_PERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_RTAG_PERR                  , 33  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_DAT_RTAG_PERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_STATE_PERR                 , 34  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_DAT_STATE_PERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_LOGIC_ERR                  , 35  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_DAT_LOGIC_ERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_DATA_BE_SUE                , 36  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_DAT_DATA_BE_SUE );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_PBRX_SUE                   , 37  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_DAT_PBRX_SUE );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_RSVD_9                     , 38  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_DAT_RSVD_9 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_RSVD_10                    , 39  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_DAT_RSVD_10 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_INT                        , 40  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_INT    );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_SRAM_CE                    , 41  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_SRAM_CE );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_SRAM_UE                    , 42  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_SRAM_UE );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_PROTOCOL_CE                , 43  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_PROTOCOL_CE );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_PROTOCOL_UE                , 44  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_PROTOCOL_UE );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_PBUS_PROTOCOL              , 45  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_PBUS_PROTOCOL );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_6                     , 46  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_RSVD_6 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_7                     , 47  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_RSVD_7 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_8                     , 48  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_RSVD_8 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_9                     , 49  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_RSVD_9 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_10                    , 50  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_RSVD_10 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_11                    , 51  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_RSVD_11 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_12                    , 52  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_RSVD_12 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_13                    , 53  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_RSVD_13 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_14                    , 54  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_RSVD_14 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_15                    , 55  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_RSVD_15 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_16                    , 56  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_RSVD_16 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_17                    , 57  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_RSVD_17 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_18                    , 58  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_RSVD_18 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_19                    , 59  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_XTS_RSVD_19 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_SCOMSAT00_ERR                  , 60  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOMSAT00_ERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_SCOMSAT01_ERR                  , 61  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOMSAT01_ERR );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_PARITY_ERR2                    , 62  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PARITY_ERR2 );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_PARITY_ERR                     , 63  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PARITY_ERR );
+
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK0_STALL                 , 0   , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NDL_BRK0_STALL );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK0_NOSTALL               , 1   , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NDL_BRK0_NOSTALL );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK1_STALL                 , 2   , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NDL_BRK1_STALL );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK1_NOSTALL               , 3   , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NDL_BRK1_NOSTALL );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK2_STALL                 , 4   , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NDL_BRK2_STALL );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK2_NOSTALL               , 5   , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NDL_BRK2_NOSTALL );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK3_STALL                 , 6   , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NDL_BRK3_STALL );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK3_NOSTALL               , 7   , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NDL_BRK3_NOSTALL );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK4_STALL                 , 8   , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NDL_BRK4_STALL );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK4_NOSTALL               , 9   , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NDL_BRK4_NOSTALL );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK5_STALL                 , 10  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NDL_BRK5_STALL );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK5_NOSTALL               , 11  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NDL_BRK5_NOSTALL );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_MISC_RING_ERR                  , 12  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_MISC_RING_ERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_MISC_INT_RA_PERR               , 13  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_MISC_INT_RA_PERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_MISC_DA_ADDR_PERR              , 14  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_MISC_DA_ADDR_PERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_MISC_CTRL_PERR                 , 15  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_MISC_CTRL_PERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_MISC_NMMU_ERR                  , 16  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_MISC_NMMU_ERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TVT_ENTRY_INVALID          , 17  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_TVT_ENTRY_INVALID );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TVT_ADDR_RANGE_ERR         , 18  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_TVT_ADDR_RANGE_ERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TCE_PAGE_ACCESS_CA_ERR     , 19  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_TCE_PAGE_ACCESS_CA_ERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TCE_CACHE_MULT_HIT_ERR     , 20  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_TCE_CACHE_MULT_HIT_ERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TCE_PAGE_ACCESS_TW_ERR     , 21  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_TCE_PAGE_ACCESS_TW_ERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TCE_REQ_TO_ERR             , 22  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_TCE_REQ_TO_ERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TCD_PERR                   , 23  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_TCD_PERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TDR_PERR                   , 24  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_TDR_PERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_EA_UE                   , 25  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_AT_EA_UE );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_EA_CE                   , 26  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_AT_EA_CE );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_TDRMEM_UE               , 27  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_AT_TDRMEM_UE );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_TDRMEM_CE               , 28  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_AT_TDRMEM_CE );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_RSPOUT_UE               , 29  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_AT_RSPOUT_UE );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_RSPOUT_CE               , 30  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_AT_RSPOUT_CE );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TVT_PERR                   , 31  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_TVT_PERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_IODA_ADDR_PERR             , 32  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_IODA_ADDR_PERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_NPU_CTRL_PERR              , 33  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_NPU_CTRL_PERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_NPU_TOR_PERR               , 34  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_NPU_TOR_PERR );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_INVAL_IODA_TBL_SEL         , 35  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_INVAL_IODA_TBL_SEL );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_RSVD_19                    , 36  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_ATS_RSVD_19 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_37                   , 37  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_37 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_38                   , 38  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_38 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_39                   , 39  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_39 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_40                   , 40  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_40 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_41                   , 41  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_41 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_42                   , 42  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_42 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_43                   , 43  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_43 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_44                   , 44  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_44 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_45                   , 45  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_45 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_46                   , 46  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_46 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_47                   , 47  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_47 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_48                   , 48  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_48 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_49                   , 49  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_49 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_50                   , 50  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_50 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_51                   , 51  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_51 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_52                   , 52  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_52 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_53                   , 53  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_53 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_54                   , 54  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_54 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_55                   , 55  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_55 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_56                   , 56  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_56 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_57                   , 57  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_57 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_58                   , 58  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_58 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_59                   , 59  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_59 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_60                   , 60  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_60 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_61                   , 61  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR1_RSVD_61 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_PARITY_ERR2                    , 62  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_PARITY_ERR2 );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_PARITY_ERR                     , 63  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR ,
+           SH_FLD_PARITY_ERR );
+
+REG64_FLD( PEC_FIR_STATUS_REG_HSSCALERR                            , 0   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_HSSCALERR  );
+REG64_FLD( PEC_FIR_STATUS_REG_HSSPLLAERR                           , 1   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_HSSPLLAERR );
+REG64_FLD( PEC_FIR_STATUS_REG_HSSPLLBERR                           , 2   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_HSSPLLBERR );
+REG64_FLD( PEC_FIR_STATUS_REG_TXAERR                               , 3   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXAERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_TXBERR                               , 4   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXBERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_TXCERR                               , 5   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXCERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_TXDERR                               , 6   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXDERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_TXEERR                               , 7   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXEERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_TXFERR                               , 8   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXFERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_TXGERR                               , 9   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXGERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_TXHERR                               , 10  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXHERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_TXIERR                               , 11  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXIERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_TXJERR                               , 12  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXJERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_TXKERR                               , 13  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXKERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_TXLERR                               , 14  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXLERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_TXMERR                               , 15  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXMERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_TXNERR                               , 16  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXNERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_TXOERR                               , 17  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXOERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_TXPERR                               , 18  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_TXPERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXAERR                               , 19  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXAERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXBERR                               , 20  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXBERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXCERR                               , 21  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXCERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXDERR                               , 22  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXDERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXEERR                               , 23  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXEERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXFERR                               , 24  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXFERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXGERR                               , 25  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXGERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXHERR                               , 26  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXHERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXIERR                               , 27  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXIERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXJERR                               , 28  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXJERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXKERR                               , 29  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXKERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXLERR                               , 30  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXLERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXMERR                               , 31  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXMERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXNERR                               , 32  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXNERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXOERR                               , 33  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXOERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_RXPERR                               , 34  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_RXPERR     );
+REG64_FLD( PEC_FIR_STATUS_REG_SCOM_PERR0                           , 35  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PERR0 );
+REG64_FLD( PEC_FIR_STATUS_REG_SCOM_PERR1                           , 36  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PERR1 );
+
+REG64_FLD( PEC_FIR_WOF_REG_WOF                                     , 0   , SH_UNT_PEC      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_WOF        );
+REG64_FLD( PEC_FIR_WOF_REG_WOF_LEN                                 , 37  , SH_UNT_PEC      , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_WOF_LEN    );
+
+REG64_FLD( PU_NPU_MSC_SM0_FIR_WOF_REG_0_0                          , 0   , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_0          );
+REG64_FLD( PU_NPU_MSC_SM0_FIR_WOF_REG_0_0_LEN                      , 64  , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_0_LEN      );
+
+REG64_FLD( PU_NPU_MSC_SM2_FIR_WOF_REG_1_1                          , 0   , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_1          );
+REG64_FLD( PU_NPU_MSC_SM2_FIR_WOF_REG_1_1_LEN                      , 64  , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_WCLRREG,
+           SH_FLD_1_LEN      );
+
+REG64_FLD( CAPP_FLUSHCPIG_FLUSH_CP_IG_STATE_MAP                    , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_FLUSH_CP_IG_STATE_MAP );
+REG64_FLD( CAPP_FLUSHCPIG_FLUSH_CP_IG_STATE_MAP_LEN                , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_FLUSH_CP_IG_STATE_MAP_LEN );
+
+REG64_FLD( CAPP_FLUSHSHUE_FLUSH_SUE_STATE_MAP                      , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_FLUSH_SUE_STATE_MAP );
+REG64_FLD( CAPP_FLUSHSHUE_FLUSH_SUE_STATE_MAP_LEN                  , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_FLUSH_SUE_STATE_MAP_LEN );
+
+REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_ITAG                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ALTD_DATA_ITAG );
+REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_TX                           , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ALTD_DATA_TX );
+REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_TX_LEN                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ALTD_DATA_TX_LEN );
+REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_TX_OVERWRITE                 , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ALTD_DATA_TX_OVERWRITE );
+
+REG64_FLD( PU_NPU_CTL_FREEZE_0_CONFIG_0                            , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( PU_NPU_CTL_FREEZE_0_CONFIG_0_LEN                        , 64  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_0_LEN      );
+
+REG64_FLD( PU_NPU_CTL_FREEZE_1_CONFIG_1                            , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( PU_NPU_CTL_FREEZE_1_CONFIG_1_LEN                        , 64  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_1_LEN      );
+
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_00                       , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_00  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_01                       , 1   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_01  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_02                       , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_02  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_10                       , 3   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_10  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_11                       , 4   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_11  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_12                       , 5   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_12  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_20                       , 6   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_20  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_21                       , 7   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_21  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_22                       , 8   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_22  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_30                       , 9   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_30  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_31                       , 10  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_31  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_32                       , 11  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_32  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_40                       , 12  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_40  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_41                       , 13  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_41  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_42                       , 14  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_42  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_50                       , 15  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_50  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_51                       , 16  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_51  );
+REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_52                       , 17  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BDF2PE_52  );
+
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SBE          , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DNFIFO_REQ_RESET_FR_SBE );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SP           , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DNFIFO_REQ_RESET_FR_SP );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_DEQUEUED_EOT_FLAG         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DNFIFO_DEQUEUED_EOT_FLAG );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_FULL                 , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DNFIFO_FIFO_FULL );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EMPTY                , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DNFIFO_FIFO_EMPTY );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT          , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DNFIFO_FIFO_ENTRY_COUNT );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT_LEN      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DNFIFO_FIFO_ENTRY_COUNT_LEN );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS          , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DNFIFO_FIFO_VALID_FLAGS );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS_LEN      , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DNFIFO_FIFO_VALID_FLAGS_LEN );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DNFIFO_FIFO_EOT_FLAGS );
+REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS_LEN        , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DNFIFO_FIFO_EOT_FLAGS_LEN );
+
+REG64_FLD( PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SP                    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REQ_RESET_FR_SP );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SBE                   , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REQ_RESET_FR_SBE );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_DEQUEUED_EOT_FLAG                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DEQUEUED_EOT_FLAG );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_FULL                          , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_FULL  );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EMPTY                         , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_EMPTY );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT                   , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_ENTRY_COUNT );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT_LEN               , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_ENTRY_COUNT_LEN );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS                   , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_VALID_FLAGS );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS_LEN               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_VALID_FLAGS_LEN );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS                     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_EOT_FLAGS );
+REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS_LEN                 , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_EOT_FLAGS_LEN );
+
+REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM0_GENID_BAR_RESERVED1                         , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_GENID_BAR_RESERVED1_LEN                     , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_GROUP                      , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_GROUP_LEN                  , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_CHIP                       , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_CHIP_LEN                   , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_ADDR                       , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_ADDR_LEN                   , 25  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM0_GENID_BAR_RESERVED2                         , 35  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM2_GENID_BAR_RESERVED1                         , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_GENID_BAR_RESERVED1_LEN                     , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_GROUP                      , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_GROUP_LEN                  , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_CHIP                       , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_CHIP_LEN                   , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_ADDR                       , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_ADDR_LEN                   , 25  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM2_GENID_BAR_RESERVED2                         , 35  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM3_GENID_BAR_RESERVED1                         , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_GENID_BAR_RESERVED1_LEN                     , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_GROUP                      , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_GROUP_LEN                  , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_CHIP                       , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_CHIP_LEN                   , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_ADDR                       , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_ADDR_LEN                   , 25  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM3_GENID_BAR_RESERVED2                         , 35  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM3_GENID_BAR_RESERVED1                         , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_GENID_BAR_RESERVED1_LEN                     , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_GROUP                      , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_GROUP_LEN                  , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_CHIP                       , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_CHIP_LEN                   , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_ADDR                       , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_ADDR_LEN                   , 25  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM3_GENID_BAR_RESERVED2                         , 35  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM3_GENID_BAR_RESERVED1                         , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_GENID_BAR_RESERVED1_LEN                     , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_GROUP                      , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_GROUP_LEN                  , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_CHIP                       , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_CHIP_LEN                   , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_ADDR                       , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_ADDR_LEN                   , 25  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM3_GENID_BAR_RESERVED2                         , 35  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM1_GENID_BAR_RESERVED1                         , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_GENID_BAR_RESERVED1_LEN                     , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_GROUP                      , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_GROUP_LEN                  , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_CHIP                       , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_CHIP_LEN                   , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_ADDR                       , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_ADDR_LEN                   , 25  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM1_GENID_BAR_RESERVED2                         , 35  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM2_GENID_BAR_RESERVED1                         , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_GENID_BAR_RESERVED1_LEN                     , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_GROUP                      , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_GROUP_LEN                  , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_CHIP                       , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_CHIP_LEN                   , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_ADDR                       , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_ADDR_LEN                   , 25  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM2_GENID_BAR_RESERVED2                         , 35  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM1_GENID_BAR_RESERVED1                         , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_GENID_BAR_RESERVED1_LEN                     , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_GROUP                      , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_GROUP_LEN                  , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_CHIP                       , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_CHIP_LEN                   , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_ADDR                       , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_ADDR_LEN                   , 25  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM1_GENID_BAR_RESERVED2                         , 35  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM2_GENID_BAR_RESERVED1                         , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_GENID_BAR_RESERVED1_LEN                     , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_GROUP                      , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_GROUP_LEN                  , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_CHIP                       , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_CHIP_LEN                   , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_ADDR                       , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_ADDR_LEN                   , 25  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM2_GENID_BAR_RESERVED2                         , 35  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM0_GENID_BAR_RESERVED1                         , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_GENID_BAR_RESERVED1_LEN                     , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_GROUP                      , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_GROUP_LEN                  , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_CHIP                       , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_CHIP_LEN                   , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_ADDR                       , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_ADDR_LEN                   , 25  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM0_GENID_BAR_RESERVED2                         , 35  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM1_GENID_BAR_RESERVED1                         , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_GENID_BAR_RESERVED1_LEN                     , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_GROUP                      , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_GROUP_LEN                  , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_CHIP                       , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_CHIP_LEN                   , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_ADDR                       , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_ADDR_LEN                   , 25  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM1_GENID_BAR_RESERVED2                         , 35  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_ENABLE                     , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM0_GENID_BAR_RESERVED1                         , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_GENID_BAR_RESERVED1_LEN                     , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_GROUP                      , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_GROUP_LEN                  , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_CHIP                       , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_CHIP_LEN                   , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_ADDR                       , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_ADDR_LEN                   , 25  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM0_GENID_BAR_RESERVED2                         , 35  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_GPE0_GPEDBG_EN_DBG                                   , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_DBG     );
+REG64_FLD( PU_GPE0_GPEDBG_HALT_ON_XSTOP                            , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_GPE0_GPEDBG_HALT_ON_TRIG                             , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_GPE0_GPEDBG_RESERVED3                                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_GPE0_GPEDBG_EN_INTR_ADDR                             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_GPE0_GPEDBG_EN_TRACE_EXTRA                           , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_GPE0_GPEDBG_EN_TRACE_STALL                           , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_GPE0_GPEDBG_EN_WAIT_CYCLES                           , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_GPE0_GPEDBG_EN_FULL_SPEED                            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_GPE0_GPEDBG_RESERVED9                                , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_GPE0_GPEDBG_TRACE_MODE_SEL                           , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_GPE0_GPEDBG_TRACE_MODE_SEL_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_GPE0_GPEDBG_RESERVED12_15                            , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED12_15 );
+REG64_FLD( PU_GPE0_GPEDBG_RESERVED12_15_LEN                        , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED12_15_LEN );
+REG64_FLD( PU_GPE0_GPEDBG_FIR_TRIGGER                              , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_GPE0_GPEDBG_SPARE                                    , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_GPE0_GPEDBG_SPARE_LEN                                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE0_GPEDBG_TRACE_DATA_SEL                           , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_GPE0_GPEDBG_TRACE_DATA_SEL_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_GPE0_GPEIVPR_IVPR                                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVPR       );
+REG64_FLD( PU_GPE0_GPEIVPR_IVPR_LEN                                , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVPR_LEN   );
+
+REG64_FLD( PU_GPE0_GPEMACR_MEM_LOW_PRIORITY                        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_LOW_PRIORITY );
+REG64_FLD( PU_GPE0_GPEMACR_MEM_LOW_PRIORITY_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_GPEMACR_MEM_HIGH_PRIORITY                       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE0_GPEMACR_MEM_HIGH_PRIORITY_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_GPEMACR_LOCAL_LOW_PRIORITY                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_LOW_PRIORITY );
+REG64_FLD( PU_GPE0_GPEMACR_LOCAL_LOW_PRIORITY_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_GPEMACR_LOCAL_HIGH_PRIORITY                     , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_HIGH_PRIORITY );
+REG64_FLD( PU_GPE0_GPEMACR_LOCAL_HIGH_PRIORITY_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_GPEMACR_SRAM_LOW_PRIORITY                       , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_LOW_PRIORITY );
+REG64_FLD( PU_GPE0_GPEMACR_SRAM_LOW_PRIORITY_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE0_GPEMACR_SRAM_HIGH_PRIORITY                      , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE0_GPEMACR_SRAM_HIGH_PRIORITY_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_HIGH_PRIORITY_LEN );
+
+REG64_FLD( PU_GPE0_GPENXIXCR_PPE_XIXCR_XCR                         , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR );
+REG64_FLD( PU_GPE0_GPENXIXCR_PPE_XIXCR_XCR_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR_LEN );
+
+REG64_FLD( PU_GPE0_GPESTR_PBASE                                    , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBASE      );
+REG64_FLD( PU_GPE0_GPESTR_PBASE_LEN                                , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBASE_LEN  );
+REG64_FLD( PU_GPE0_GPESTR_SIZE                                     , 29  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE       );
+REG64_FLD( PU_GPE0_GPESTR_SIZE_LEN                                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_LEN   );
+
+REG64_FLD( PU_GPE0_GPETSEL_FIT_SEL                                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_GPE0_GPETSEL_FIT_SEL_LEN                             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_GPE0_GPETSEL_WATCHDOG_SEL                            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_GPE0_GPETSEL_WATCHDOG_SEL_LEN                        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_GPE0_GPEXIEDR_PPE_XIRAMEDR_EDR                       , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PPE_XIRAMEDR_EDR );
+REG64_FLD( PU_GPE0_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN                   , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PPE_XIRAMEDR_EDR_LEN );
+
+REG64_FLD( PU_GPE0_GPEXIIR_PPE_XIRAMGA_IR                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMGA_IR );
+REG64_FLD( PU_GPE0_GPEXIIR_PPE_XIRAMGA_IR_LEN                      , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMGA_IR_LEN );
+
+REG64_FLD( PU_GPE0_GPEXISPRG0_PPE_XIRAMRA_SPRG0                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE0_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN                , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE0_GPEXIXCR_PPE_XIXCR_XCR                          , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR );
+REG64_FLD( PU_GPE0_GPEXIXCR_PPE_XIXCR_XCR_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR_LEN );
+
+REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_SIBRC                         , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_SIBRC_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_WE                            , 14  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_LP                            , 20  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DCACHE_TAG_ADDR );
+REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN                  , 27  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DCACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_ERR                           , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DCACHE_ERR );
+
+REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR );
+REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                  , 27  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_ERR                           , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_ERR );
+REG64_FLD( PU_GPE0_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING             , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_VALID                         , 36  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID );
+REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_VALID_LEN                     , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID_LEN );
+
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ADDR                              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR   );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ADDR_LEN                          , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR_LEN );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_R_NW                              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_R_NW   );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_BUSY                              , 33  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BUSY   );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING           , 34  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_BYTE_ENABLE                       , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE_LEN );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_LINE_MODE                         , 43  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_LINE_MODE );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ERROR                             , 49  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR  );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ERROR_LEN                         , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR_LEN );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_IFETCH_PENDING                    , 62  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_DATAOP_PENDING                    , 63  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_DATAOP_PENDING );
+
+REG64_FLD( PU_GPE0_MIB_XISGB_STORE_ADDRESS                         , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS );
+REG64_FLD( PU_GPE0_MIB_XISGB_STORE_ADDRESS_LEN                     , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS_LEN );
+REG64_FLD( PU_GPE0_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING     , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE0_MIB_XISGB_SGB_BYTE_VALID                        , 36  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID );
+REG64_FLD( PU_GPE0_MIB_XISGB_SGB_BYTE_VALID_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID_LEN );
+REG64_FLD( PU_GPE0_MIB_XISGB_SGB_FLUSH_PENDING                     , 63  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_FLUSH_PENDING );
+
+REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC                     , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_WE                        , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_LP                        , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_SIBRC                     , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_WE                        , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_LP                        , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XIRAMRA_SPRG0                      , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                  , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE0_PPE_XIRAMEDR_XIRAMGA_IR                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR );
+REG64_FLD( PU_GPE0_PPE_XIRAMEDR_XIRAMGA_IR_LEN                     , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR_LEN );
+REG64_FLD( PU_GPE0_PPE_XIRAMEDR_EDR                                , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EDR        );
+REG64_FLD( PU_GPE0_PPE_XIRAMEDR_EDR_LEN                            , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EDR_LEN    );
+
+REG64_FLD( PU_GPE0_PPE_XIRAMGA_IR                                  , 0   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_IR         );
+REG64_FLD( PU_GPE0_PPE_XIRAMGA_IR_LEN                              , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_IR_LEN     );
+REG64_FLD( PU_GPE0_PPE_XIRAMGA_XIRAMRA_SPRG0                       , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE0_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                   , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE0_PPE_XIRAMRA_XIXCR_XCR                           , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR  );
+REG64_FLD( PU_GPE0_PPE_XIRAMRA_XIXCR_XCR_LEN                       , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR_LEN );
+REG64_FLD( PU_GPE0_PPE_XIRAMRA_SPRG0                               , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0      );
+REG64_FLD( PU_GPE0_PPE_XIRAMRA_SPRG0_LEN                           , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0_LEN  );
+
+REG64_FLD( PU_GPE0_PPE_XIXCR_XCR                                   , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR        );
+REG64_FLD( PU_GPE0_PPE_XIXCR_XCR_LEN                               , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR_LEN    );
+
+REG64_FLD( PU_GPE1_GPEDBG_EN_DBG                                   , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_DBG     );
+REG64_FLD( PU_GPE1_GPEDBG_HALT_ON_XSTOP                            , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_GPE1_GPEDBG_HALT_ON_TRIG                             , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_GPE1_GPEDBG_RESERVED3                                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_GPE1_GPEDBG_EN_INTR_ADDR                             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_GPE1_GPEDBG_EN_TRACE_EXTRA                           , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_GPE1_GPEDBG_EN_TRACE_STALL                           , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_GPE1_GPEDBG_EN_WAIT_CYCLES                           , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_GPE1_GPEDBG_EN_FULL_SPEED                            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_GPE1_GPEDBG_RESERVED9                                , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_GPE1_GPEDBG_TRACE_MODE_SEL                           , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_GPE1_GPEDBG_TRACE_MODE_SEL_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_GPE1_GPEDBG_RESERVED12_15                            , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED12_15 );
+REG64_FLD( PU_GPE1_GPEDBG_RESERVED12_15_LEN                        , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED12_15_LEN );
+REG64_FLD( PU_GPE1_GPEDBG_FIR_TRIGGER                              , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_GPE1_GPEDBG_SPARE                                    , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_GPE1_GPEDBG_SPARE_LEN                                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE1_GPEDBG_TRACE_DATA_SEL                           , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_GPE1_GPEDBG_TRACE_DATA_SEL_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_GPE1_GPEIVPR_IVPR                                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVPR       );
+REG64_FLD( PU_GPE1_GPEIVPR_IVPR_LEN                                , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVPR_LEN   );
+
+REG64_FLD( PU_GPE1_GPEMACR_MEM_LOW_PRIORITY                        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_LOW_PRIORITY );
+REG64_FLD( PU_GPE1_GPEMACR_MEM_LOW_PRIORITY_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE1_GPEMACR_MEM_HIGH_PRIORITY                       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE1_GPEMACR_MEM_HIGH_PRIORITY_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE1_GPEMACR_LOCAL_LOW_PRIORITY                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_LOW_PRIORITY );
+REG64_FLD( PU_GPE1_GPEMACR_LOCAL_LOW_PRIORITY_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE1_GPEMACR_LOCAL_HIGH_PRIORITY                     , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_HIGH_PRIORITY );
+REG64_FLD( PU_GPE1_GPEMACR_LOCAL_HIGH_PRIORITY_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE1_GPEMACR_SRAM_LOW_PRIORITY                       , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_LOW_PRIORITY );
+REG64_FLD( PU_GPE1_GPEMACR_SRAM_LOW_PRIORITY_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE1_GPEMACR_SRAM_HIGH_PRIORITY                      , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE1_GPEMACR_SRAM_HIGH_PRIORITY_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_HIGH_PRIORITY_LEN );
+
+REG64_FLD( PU_GPE1_GPENXIXCR_PPE_XIXCR_XCR                         , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR );
+REG64_FLD( PU_GPE1_GPENXIXCR_PPE_XIXCR_XCR_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR_LEN );
+
+REG64_FLD( PU_GPE1_GPESTR_PBASE                                    , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBASE      );
+REG64_FLD( PU_GPE1_GPESTR_PBASE_LEN                                , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBASE_LEN  );
+REG64_FLD( PU_GPE1_GPESTR_SIZE                                     , 29  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE       );
+REG64_FLD( PU_GPE1_GPESTR_SIZE_LEN                                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_LEN   );
+
+REG64_FLD( PU_GPE1_GPETSEL_FIT_SEL                                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_GPE1_GPETSEL_FIT_SEL_LEN                             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_GPE1_GPETSEL_WATCHDOG_SEL                            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_GPE1_GPETSEL_WATCHDOG_SEL_LEN                        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_GPE1_GPEXIEDR_PPE_XIRAMEDR_EDR                       , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PPE_XIRAMEDR_EDR );
+REG64_FLD( PU_GPE1_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN                   , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PPE_XIRAMEDR_EDR_LEN );
+
+REG64_FLD( PU_GPE1_GPEXIIR_PPE_XIRAMGA_IR                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMGA_IR );
+REG64_FLD( PU_GPE1_GPEXIIR_PPE_XIRAMGA_IR_LEN                      , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMGA_IR_LEN );
+
+REG64_FLD( PU_GPE1_GPEXISPRG0_PPE_XIRAMRA_SPRG0                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE1_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN                , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE1_GPEXIXCR_PPE_XIXCR_XCR                          , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR );
+REG64_FLD( PU_GPE1_GPEXIXCR_PPE_XIXCR_XCR_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR_LEN );
+
+REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_SIBRC                         , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_SIBRC_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_WE                            , 14  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_LP                            , 20  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DCACHE_TAG_ADDR );
+REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN                  , 27  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DCACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_ERR                           , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DCACHE_ERR );
+
+REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR );
+REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                  , 27  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_ERR                           , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_ERR );
+REG64_FLD( PU_GPE1_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING             , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_VALID                         , 36  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID );
+REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_VALID_LEN                     , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID_LEN );
+
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ADDR                              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR   );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ADDR_LEN                          , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR_LEN );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_R_NW                              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_R_NW   );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_BUSY                              , 33  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BUSY   );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING           , 34  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_BYTE_ENABLE                       , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE_LEN );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_LINE_MODE                         , 43  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_LINE_MODE );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ERROR                             , 49  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR  );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ERROR_LEN                         , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR_LEN );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_IFETCH_PENDING                    , 62  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_DATAOP_PENDING                    , 63  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_DATAOP_PENDING );
+
+REG64_FLD( PU_GPE1_MIB_XISGB_STORE_ADDRESS                         , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS );
+REG64_FLD( PU_GPE1_MIB_XISGB_STORE_ADDRESS_LEN                     , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS_LEN );
+REG64_FLD( PU_GPE1_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING     , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE1_MIB_XISGB_SGB_BYTE_VALID                        , 36  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID );
+REG64_FLD( PU_GPE1_MIB_XISGB_SGB_BYTE_VALID_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID_LEN );
+REG64_FLD( PU_GPE1_MIB_XISGB_SGB_FLUSH_PENDING                     , 63  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_FLUSH_PENDING );
+
+REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC                     , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_WE                        , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_LP                        , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_SIBRC                     , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_WE                        , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_LP                        , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XIRAMRA_SPRG0                      , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                  , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE1_PPE_XIRAMEDR_XIRAMGA_IR                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR );
+REG64_FLD( PU_GPE1_PPE_XIRAMEDR_XIRAMGA_IR_LEN                     , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR_LEN );
+REG64_FLD( PU_GPE1_PPE_XIRAMEDR_EDR                                , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EDR        );
+REG64_FLD( PU_GPE1_PPE_XIRAMEDR_EDR_LEN                            , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EDR_LEN    );
+
+REG64_FLD( PU_GPE1_PPE_XIRAMGA_IR                                  , 0   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_IR         );
+REG64_FLD( PU_GPE1_PPE_XIRAMGA_IR_LEN                              , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_IR_LEN     );
+REG64_FLD( PU_GPE1_PPE_XIRAMGA_XIRAMRA_SPRG0                       , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE1_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                   , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE1_PPE_XIRAMRA_XIXCR_XCR                           , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR  );
+REG64_FLD( PU_GPE1_PPE_XIRAMRA_XIXCR_XCR_LEN                       , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR_LEN );
+REG64_FLD( PU_GPE1_PPE_XIRAMRA_SPRG0                               , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0      );
+REG64_FLD( PU_GPE1_PPE_XIRAMRA_SPRG0_LEN                           , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0_LEN  );
+
+REG64_FLD( PU_GPE1_PPE_XIXCR_XCR                                   , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR        );
+REG64_FLD( PU_GPE1_PPE_XIXCR_XCR_LEN                               , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR_LEN    );
+
+REG64_FLD( PU_GPE2_GPEDBG_EN_DBG                                   , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_DBG     );
+REG64_FLD( PU_GPE2_GPEDBG_HALT_ON_XSTOP                            , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_GPE2_GPEDBG_HALT_ON_TRIG                             , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_GPE2_GPEDBG_RESERVED3                                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_GPE2_GPEDBG_EN_INTR_ADDR                             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_GPE2_GPEDBG_EN_TRACE_EXTRA                           , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_GPE2_GPEDBG_EN_TRACE_STALL                           , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_GPE2_GPEDBG_EN_WAIT_CYCLES                           , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_GPE2_GPEDBG_EN_FULL_SPEED                            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_GPE2_GPEDBG_RESERVED9                                , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_GPE2_GPEDBG_TRACE_MODE_SEL                           , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_GPE2_GPEDBG_TRACE_MODE_SEL_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_GPE2_GPEDBG_RESERVED12_15                            , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED12_15 );
+REG64_FLD( PU_GPE2_GPEDBG_RESERVED12_15_LEN                        , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED12_15_LEN );
+REG64_FLD( PU_GPE2_GPEDBG_FIR_TRIGGER                              , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_GPE2_GPEDBG_SPARE                                    , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_GPE2_GPEDBG_SPARE_LEN                                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE2_GPEDBG_TRACE_DATA_SEL                           , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_GPE2_GPEDBG_TRACE_DATA_SEL_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_GPE2_GPEIVPR_IVPR                                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVPR       );
+REG64_FLD( PU_GPE2_GPEIVPR_IVPR_LEN                                , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVPR_LEN   );
+
+REG64_FLD( PU_GPE2_GPEMACR_MEM_LOW_PRIORITY                        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_LOW_PRIORITY );
+REG64_FLD( PU_GPE2_GPEMACR_MEM_LOW_PRIORITY_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE2_GPEMACR_MEM_HIGH_PRIORITY                       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE2_GPEMACR_MEM_HIGH_PRIORITY_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE2_GPEMACR_LOCAL_LOW_PRIORITY                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_LOW_PRIORITY );
+REG64_FLD( PU_GPE2_GPEMACR_LOCAL_LOW_PRIORITY_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE2_GPEMACR_LOCAL_HIGH_PRIORITY                     , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_HIGH_PRIORITY );
+REG64_FLD( PU_GPE2_GPEMACR_LOCAL_HIGH_PRIORITY_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE2_GPEMACR_SRAM_LOW_PRIORITY                       , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_LOW_PRIORITY );
+REG64_FLD( PU_GPE2_GPEMACR_SRAM_LOW_PRIORITY_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE2_GPEMACR_SRAM_HIGH_PRIORITY                      , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE2_GPEMACR_SRAM_HIGH_PRIORITY_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_HIGH_PRIORITY_LEN );
+
+REG64_FLD( PU_GPE2_GPENXIXCR_PPE_XIXCR_XCR                         , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR );
+REG64_FLD( PU_GPE2_GPENXIXCR_PPE_XIXCR_XCR_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR_LEN );
+
+REG64_FLD( PU_GPE2_GPESTR_PBASE                                    , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBASE      );
+REG64_FLD( PU_GPE2_GPESTR_PBASE_LEN                                , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBASE_LEN  );
+REG64_FLD( PU_GPE2_GPESTR_SIZE                                     , 29  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE       );
+REG64_FLD( PU_GPE2_GPESTR_SIZE_LEN                                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_LEN   );
+
+REG64_FLD( PU_GPE2_GPETSEL_FIT_SEL                                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_GPE2_GPETSEL_FIT_SEL_LEN                             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_GPE2_GPETSEL_WATCHDOG_SEL                            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_GPE2_GPETSEL_WATCHDOG_SEL_LEN                        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_GPE2_GPEXIEDR_PPE_XIRAMEDR_EDR                       , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PPE_XIRAMEDR_EDR );
+REG64_FLD( PU_GPE2_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN                   , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PPE_XIRAMEDR_EDR_LEN );
+
+REG64_FLD( PU_GPE2_GPEXIIR_PPE_XIRAMGA_IR                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMGA_IR );
+REG64_FLD( PU_GPE2_GPEXIIR_PPE_XIRAMGA_IR_LEN                      , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMGA_IR_LEN );
+
+REG64_FLD( PU_GPE2_GPEXISPRG0_PPE_XIRAMRA_SPRG0                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE2_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN                , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE2_GPEXIXCR_PPE_XIXCR_XCR                          , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR );
+REG64_FLD( PU_GPE2_GPEXIXCR_PPE_XIXCR_XCR_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR_LEN );
+
+REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_SIBRC                         , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_SIBRC_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_WE                            , 14  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_LP                            , 20  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DCACHE_TAG_ADDR );
+REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN                  , 27  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DCACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_ERR                           , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DCACHE_ERR );
+
+REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR );
+REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                  , 27  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_ERR                           , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_ERR );
+REG64_FLD( PU_GPE2_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING             , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_VALID                         , 36  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID );
+REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_VALID_LEN                     , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID_LEN );
+
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ADDR                              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR   );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ADDR_LEN                          , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR_LEN );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_R_NW                              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_R_NW   );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_BUSY                              , 33  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BUSY   );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING           , 34  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_BYTE_ENABLE                       , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE_LEN );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_LINE_MODE                         , 43  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_LINE_MODE );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ERROR                             , 49  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR  );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ERROR_LEN                         , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR_LEN );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_IFETCH_PENDING                    , 62  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_DATAOP_PENDING                    , 63  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_DATAOP_PENDING );
+
+REG64_FLD( PU_GPE2_MIB_XISGB_STORE_ADDRESS                         , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS );
+REG64_FLD( PU_GPE2_MIB_XISGB_STORE_ADDRESS_LEN                     , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS_LEN );
+REG64_FLD( PU_GPE2_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING     , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE2_MIB_XISGB_SGB_BYTE_VALID                        , 36  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID );
+REG64_FLD( PU_GPE2_MIB_XISGB_SGB_BYTE_VALID_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID_LEN );
+REG64_FLD( PU_GPE2_MIB_XISGB_SGB_FLUSH_PENDING                     , 63  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_FLUSH_PENDING );
+
+REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC                     , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_WE                        , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_LP                        , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_SIBRC                     , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_WE                        , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_LP                        , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XIRAMRA_SPRG0                      , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                  , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE2_PPE_XIRAMEDR_XIRAMGA_IR                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR );
+REG64_FLD( PU_GPE2_PPE_XIRAMEDR_XIRAMGA_IR_LEN                     , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR_LEN );
+REG64_FLD( PU_GPE2_PPE_XIRAMEDR_EDR                                , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EDR        );
+REG64_FLD( PU_GPE2_PPE_XIRAMEDR_EDR_LEN                            , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EDR_LEN    );
+
+REG64_FLD( PU_GPE2_PPE_XIRAMGA_IR                                  , 0   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_IR         );
+REG64_FLD( PU_GPE2_PPE_XIRAMGA_IR_LEN                              , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_IR_LEN     );
+REG64_FLD( PU_GPE2_PPE_XIRAMGA_XIRAMRA_SPRG0                       , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE2_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                   , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE2_PPE_XIRAMRA_XIXCR_XCR                           , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR  );
+REG64_FLD( PU_GPE2_PPE_XIRAMRA_XIXCR_XCR_LEN                       , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR_LEN );
+REG64_FLD( PU_GPE2_PPE_XIRAMRA_SPRG0                               , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0      );
+REG64_FLD( PU_GPE2_PPE_XIRAMRA_SPRG0_LEN                           , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0_LEN  );
+
+REG64_FLD( PU_GPE2_PPE_XIXCR_XCR                                   , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR        );
+REG64_FLD( PU_GPE2_PPE_XIXCR_XCR_LEN                               , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR_LEN    );
+
+REG64_FLD( PU_GPE3_GPEDBG_EN_DBG                                   , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_DBG     );
+REG64_FLD( PU_GPE3_GPEDBG_HALT_ON_XSTOP                            , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PU_GPE3_GPEDBG_HALT_ON_TRIG                             , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PU_GPE3_GPEDBG_RESERVED3                                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( PU_GPE3_GPEDBG_EN_INTR_ADDR                             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( PU_GPE3_GPEDBG_EN_TRACE_EXTRA                           , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( PU_GPE3_GPEDBG_EN_TRACE_STALL                           , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( PU_GPE3_GPEDBG_EN_WAIT_CYCLES                           , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( PU_GPE3_GPEDBG_EN_FULL_SPEED                            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( PU_GPE3_GPEDBG_RESERVED9                                , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( PU_GPE3_GPEDBG_TRACE_MODE_SEL                           , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( PU_GPE3_GPEDBG_TRACE_MODE_SEL_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( PU_GPE3_GPEDBG_RESERVED12_15                            , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED12_15 );
+REG64_FLD( PU_GPE3_GPEDBG_RESERVED12_15_LEN                        , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED12_15_LEN );
+REG64_FLD( PU_GPE3_GPEDBG_FIR_TRIGGER                              , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PU_GPE3_GPEDBG_SPARE                                    , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_GPE3_GPEDBG_SPARE_LEN                                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_GPE3_GPEDBG_TRACE_DATA_SEL                           , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( PU_GPE3_GPEDBG_TRACE_DATA_SEL_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( PU_GPE3_GPEIVPR_IVPR                                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVPR       );
+REG64_FLD( PU_GPE3_GPEIVPR_IVPR_LEN                                , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVPR_LEN   );
+
+REG64_FLD( PU_GPE3_GPEMACR_MEM_LOW_PRIORITY                        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_LOW_PRIORITY );
+REG64_FLD( PU_GPE3_GPEMACR_MEM_LOW_PRIORITY_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE3_GPEMACR_MEM_HIGH_PRIORITY                       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE3_GPEMACR_MEM_HIGH_PRIORITY_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MEM_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE3_GPEMACR_LOCAL_LOW_PRIORITY                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_LOW_PRIORITY );
+REG64_FLD( PU_GPE3_GPEMACR_LOCAL_LOW_PRIORITY_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE3_GPEMACR_LOCAL_HIGH_PRIORITY                     , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_HIGH_PRIORITY );
+REG64_FLD( PU_GPE3_GPEMACR_LOCAL_HIGH_PRIORITY_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOCAL_HIGH_PRIORITY_LEN );
+REG64_FLD( PU_GPE3_GPEMACR_SRAM_LOW_PRIORITY                       , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_LOW_PRIORITY );
+REG64_FLD( PU_GPE3_GPEMACR_SRAM_LOW_PRIORITY_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_LOW_PRIORITY_LEN );
+REG64_FLD( PU_GPE3_GPEMACR_SRAM_HIGH_PRIORITY                      , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_HIGH_PRIORITY );
+REG64_FLD( PU_GPE3_GPEMACR_SRAM_HIGH_PRIORITY_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_HIGH_PRIORITY_LEN );
+
+REG64_FLD( PU_GPE3_GPENXIXCR_PPE_XIXCR_XCR                         , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR );
+REG64_FLD( PU_GPE3_GPENXIXCR_PPE_XIXCR_XCR_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR_LEN );
+
+REG64_FLD( PU_GPE3_GPESTR_PBASE                                    , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBASE      );
+REG64_FLD( PU_GPE3_GPESTR_PBASE_LEN                                , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBASE_LEN  );
+REG64_FLD( PU_GPE3_GPESTR_SIZE                                     , 29  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE       );
+REG64_FLD( PU_GPE3_GPESTR_SIZE_LEN                                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_LEN   );
+
+REG64_FLD( PU_GPE3_GPETSEL_FIT_SEL                                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PU_GPE3_GPETSEL_FIT_SEL_LEN                             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PU_GPE3_GPETSEL_WATCHDOG_SEL                            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PU_GPE3_GPETSEL_WATCHDOG_SEL_LEN                        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PU_GPE3_GPEXIEDR_PPE_XIRAMEDR_EDR                       , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PPE_XIRAMEDR_EDR );
+REG64_FLD( PU_GPE3_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN                   , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PPE_XIRAMEDR_EDR_LEN );
+
+REG64_FLD( PU_GPE3_GPEXIIR_PPE_XIRAMGA_IR                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMGA_IR );
+REG64_FLD( PU_GPE3_GPEXIIR_PPE_XIRAMGA_IR_LEN                      , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMGA_IR_LEN );
+
+REG64_FLD( PU_GPE3_GPEXISPRG0_PPE_XIRAMRA_SPRG0                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE3_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN                , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PPE_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE3_GPEXIXCR_PPE_XIXCR_XCR                          , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR );
+REG64_FLD( PU_GPE3_GPEXIXCR_PPE_XIXCR_XCR_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_PPE_XIXCR_XCR_LEN );
+
+REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_SIBRC                         , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_SIBRC_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_WE                            , 14  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_LP                            , 20  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DCACHE_TAG_ADDR );
+REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN                  , 27  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DCACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_ERR                           , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DCACHE_ERR );
+
+REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR );
+REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                  , 27  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_ERR                           , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_ERR );
+REG64_FLD( PU_GPE3_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING             , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_VALID                         , 36  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID );
+REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_VALID_LEN                     , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID_LEN );
+
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ADDR                              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR   );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ADDR_LEN                          , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR_LEN );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_R_NW                              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_R_NW   );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_BUSY                              , 33  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BUSY   );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING           , 34  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_BYTE_ENABLE                       , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE_LEN );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_LINE_MODE                         , 43  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_LINE_MODE );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ERROR                             , 49  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR  );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ERROR_LEN                         , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR_LEN );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_IFETCH_PENDING                    , 62  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IFETCH_PENDING );
+REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_DATAOP_PENDING                    , 63  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_DATAOP_PENDING );
+
+REG64_FLD( PU_GPE3_MIB_XISGB_STORE_ADDRESS                         , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS );
+REG64_FLD( PU_GPE3_MIB_XISGB_STORE_ADDRESS_LEN                     , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS_LEN );
+REG64_FLD( PU_GPE3_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING     , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_GPE3_MIB_XISGB_SGB_BYTE_VALID                        , 36  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID );
+REG64_FLD( PU_GPE3_MIB_XISGB_SGB_BYTE_VALID_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID_LEN );
+REG64_FLD( PU_GPE3_MIB_XISGB_SGB_FLUSH_PENDING                     , 63  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_FLUSH_PENDING );
+
+REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC                     , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_WE                        , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_LP                        , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_SIBRC                     , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_WE                        , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_LP                        , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XIRAMRA_SPRG0                      , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                  , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE3_PPE_XIRAMEDR_XIRAMGA_IR                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR );
+REG64_FLD( PU_GPE3_PPE_XIRAMEDR_XIRAMGA_IR_LEN                     , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR_LEN );
+REG64_FLD( PU_GPE3_PPE_XIRAMEDR_EDR                                , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EDR        );
+REG64_FLD( PU_GPE3_PPE_XIRAMEDR_EDR_LEN                            , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EDR_LEN    );
+
+REG64_FLD( PU_GPE3_PPE_XIRAMGA_IR                                  , 0   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_IR         );
+REG64_FLD( PU_GPE3_PPE_XIRAMGA_IR_LEN                              , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_IR_LEN     );
+REG64_FLD( PU_GPE3_PPE_XIRAMGA_XIRAMRA_SPRG0                       , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_GPE3_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                   , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_GPE3_PPE_XIRAMRA_XIXCR_XCR                           , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR  );
+REG64_FLD( PU_GPE3_PPE_XIRAMRA_XIXCR_XCR_LEN                       , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR_LEN );
+REG64_FLD( PU_GPE3_PPE_XIRAMRA_SPRG0                               , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0      );
+REG64_FLD( PU_GPE3_PPE_XIRAMRA_SPRG0_LEN                           , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0_LEN  );
+
+REG64_FLD( PU_GPE3_PPE_XIXCR_XCR                                   , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR        );
+REG64_FLD( PU_GPE3_PPE_XIXCR_XCR_LEN                               , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR_LEN    );
+
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_ENABLE                  , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ENABLE );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE                 , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_GROUP                   , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_GROUP_LEN               , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_CHIP                    , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_CHIP_LEN                , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_ADDR                    , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_ADDR_LEN                , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_RESERVED                , 22  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_RESERVED );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_GRANULE                 , 23  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GRANULE );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_SIZE                    , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_SIZE_LEN                , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MODE                    , 28  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MODE_LEN                , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_ENABLE                  , 32  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ENABLE );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE                 , 33  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_GROUP                   , 35  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_GROUP_LEN               , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_CHIP                    , 39  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_CHIP_LEN                , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_ADDR                    , 42  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_ADDR_LEN                , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_RESERVED                , 54  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_RESERVED );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_GRANULE                 , 55  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GRANULE );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_SIZE                    , 56  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_SIZE_LEN                , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MODE                    , 60  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE );
+REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MODE_LEN                , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE_LEN );
+
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_ENABLE                  , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ENABLE );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE                 , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_GROUP                   , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_GROUP_LEN               , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_CHIP                    , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_CHIP_LEN                , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_ADDR                    , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_ADDR_LEN                , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_RESERVED                , 22  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_RESERVED );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_GRANULE                 , 23  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GRANULE );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_SIZE                    , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_SIZE_LEN                , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MODE                    , 28  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MODE_LEN                , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_ENABLE                  , 32  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ENABLE );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE                 , 33  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_GROUP                   , 35  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_GROUP_LEN               , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_CHIP                    , 39  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_CHIP_LEN                , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_ADDR                    , 42  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_ADDR_LEN                , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_RESERVED                , 54  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_RESERVED );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_GRANULE                 , 55  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GRANULE );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_SIZE                    , 56  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_SIZE_LEN                , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MODE                    , 60  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE );
+REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MODE_LEN                , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE_LEN );
+
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_ENABLE                  , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ENABLE );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE                 , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_GROUP                   , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_GROUP_LEN               , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_CHIP                    , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_CHIP_LEN                , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_ADDR                    , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_ADDR_LEN                , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_RESERVED                , 22  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_RESERVED );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_GRANULE                 , 23  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GRANULE );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_SIZE                    , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_SIZE_LEN                , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MODE                    , 28  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MODE_LEN                , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_ENABLE                  , 32  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ENABLE );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE                 , 33  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_GROUP                   , 35  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_GROUP_LEN               , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_CHIP                    , 39  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_CHIP_LEN                , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_ADDR                    , 42  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_ADDR_LEN                , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_RESERVED                , 54  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_RESERVED );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_GRANULE                 , 55  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GRANULE );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_SIZE                    , 56  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_SIZE_LEN                , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MODE                    , 60  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE );
+REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MODE_LEN                , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE_LEN );
+
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_ENABLE                  , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ENABLE );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE                 , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_GROUP                   , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_GROUP_LEN               , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_CHIP                    , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_CHIP_LEN                , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_ADDR                    , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_ADDR_LEN                , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_RESERVED                , 22  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_RESERVED );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_GRANULE                 , 23  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GRANULE );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_SIZE                    , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_SIZE_LEN                , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MODE                    , 28  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MODE_LEN                , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_ENABLE                  , 32  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ENABLE );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE                 , 33  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_GROUP                   , 35  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_GROUP_LEN               , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_CHIP                    , 39  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_CHIP_LEN                , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_ADDR                    , 42  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_ADDR_LEN                , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_RESERVED                , 54  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_RESERVED );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_GRANULE                 , 55  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GRANULE );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_SIZE                    , 56  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_SIZE_LEN                , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MODE                    , 60  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE );
+REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MODE_LEN                , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE_LEN );
+
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_ENABLE                  , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ENABLE );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE                 , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_GROUP                   , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_GROUP_LEN               , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_CHIP                    , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_CHIP_LEN                , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_ADDR                    , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_ADDR_LEN                , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_RESERVED                , 22  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_RESERVED );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_GRANULE                 , 23  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GRANULE );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_SIZE                    , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_SIZE_LEN                , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MODE                    , 28  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MODE_LEN                , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_ENABLE                  , 32  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ENABLE );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE                 , 33  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_GROUP                   , 35  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_GROUP_LEN               , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_CHIP                    , 39  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_CHIP_LEN                , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_ADDR                    , 42  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_ADDR_LEN                , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_RESERVED                , 54  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_RESERVED );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_GRANULE                 , 55  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GRANULE );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_SIZE                    , 56  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_SIZE_LEN                , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MODE                    , 60  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE );
+REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MODE_LEN                , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE_LEN );
+
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_ENABLE                  , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ENABLE );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE                 , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_GROUP                   , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_GROUP_LEN               , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_CHIP                    , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_CHIP_LEN                , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_ADDR                    , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_ADDR_LEN                , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_RESERVED                , 22  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_RESERVED );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_GRANULE                 , 23  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GRANULE );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_SIZE                    , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_SIZE_LEN                , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MODE                    , 28  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MODE_LEN                , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_ENABLE                  , 32  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ENABLE );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE                 , 33  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_GROUP                   , 35  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_GROUP_LEN               , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_CHIP                    , 39  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_CHIP_LEN                , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_ADDR                    , 42  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_ADDR_LEN                , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_RESERVED                , 54  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_RESERVED );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_GRANULE                 , 55  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GRANULE );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_SIZE                    , 56  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_SIZE_LEN                , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MODE                    , 60  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE );
+REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MODE_LEN                , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE_LEN );
+
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_ENABLE                  , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ENABLE );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE                 , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_GROUP                   , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_GROUP_LEN               , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_CHIP                    , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_CHIP_LEN                , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_ADDR                    , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_ADDR_LEN                , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_RESERVED                , 22  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_RESERVED );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_GRANULE                 , 23  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GRANULE );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_SIZE                    , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_SIZE_LEN                , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MODE                    , 28  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MODE_LEN                , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_ENABLE                  , 32  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ENABLE );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE                 , 33  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_GROUP                   , 35  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_GROUP_LEN               , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_CHIP                    , 39  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_CHIP_LEN                , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_ADDR                    , 42  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_ADDR_LEN                , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_RESERVED                , 54  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_RESERVED );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_GRANULE                 , 55  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GRANULE );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_SIZE                    , 56  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_SIZE_LEN                , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MODE                    , 60  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE );
+REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MODE_LEN                , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE_LEN );
+
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_ENABLE                  , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ENABLE );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE                 , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_GROUP                   , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_GROUP_LEN               , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_CHIP                    , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_CHIP_LEN                , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_ADDR                    , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_ADDR_LEN                , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_RESERVED                , 22  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_RESERVED );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_GRANULE                 , 23  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GRANULE );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_SIZE                    , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_SIZE_LEN                , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MODE                    , 28  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MODE_LEN                , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_ENABLE                  , 32  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ENABLE );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE                 , 33  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_GROUP                   , 35  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_GROUP_LEN               , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_CHIP                    , 39  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_CHIP_LEN                , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_ADDR                    , 42  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_ADDR_LEN                , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_RESERVED                , 54  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_RESERVED );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_GRANULE                 , 55  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GRANULE );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_SIZE                    , 56  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_SIZE_LEN                , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MODE                    , 60  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE );
+REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MODE_LEN                , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE_LEN );
+
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_ENABLE                  , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ENABLE );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE                 , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_GROUP                   , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_GROUP_LEN               , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_CHIP                    , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_CHIP_LEN                , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_ADDR                    , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_ADDR_LEN                , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_RESERVED                , 22  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_RESERVED );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_GRANULE                 , 23  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GRANULE );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_SIZE                    , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_SIZE_LEN                , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MODE                    , 28  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MODE_LEN                , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_ENABLE                  , 32  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ENABLE );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE                 , 33  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_GROUP                   , 35  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_GROUP_LEN               , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_CHIP                    , 39  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_CHIP_LEN                , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_ADDR                    , 42  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_ADDR_LEN                , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_RESERVED                , 54  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_RESERVED );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_GRANULE                 , 55  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GRANULE );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_SIZE                    , 56  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_SIZE_LEN                , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MODE                    , 60  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE );
+REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MODE_LEN                , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE_LEN );
+
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_ENABLE                  , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ENABLE );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE                 , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_GROUP                   , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_GROUP_LEN               , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_CHIP                    , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_CHIP_LEN                , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_ADDR                    , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_ADDR_LEN                , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_RESERVED                , 22  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_RESERVED );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_GRANULE                 , 23  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GRANULE );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_SIZE                    , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_SIZE_LEN                , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MODE                    , 28  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MODE_LEN                , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_ENABLE                  , 32  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ENABLE );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE                 , 33  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_GROUP                   , 35  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_GROUP_LEN               , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_CHIP                    , 39  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_CHIP_LEN                , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_ADDR                    , 42  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_ADDR_LEN                , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_RESERVED                , 54  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_RESERVED );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_GRANULE                 , 55  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GRANULE );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_SIZE                    , 56  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_SIZE_LEN                , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE_LEN );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MODE                    , 60  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE );
+REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MODE_LEN                , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE_LEN );
+
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_ENABLE                  , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ENABLE );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE                 , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_GROUP                   , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_GROUP_LEN               , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_CHIP                    , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_CHIP_LEN                , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_ADDR                    , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_ADDR_LEN                , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_RESERVED                , 22  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_RESERVED );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_GRANULE                 , 23  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GRANULE );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_SIZE                    , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_SIZE_LEN                , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MODE                    , 28  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MODE_LEN                , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_ENABLE                  , 32  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ENABLE );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE                 , 33  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_GROUP                   , 35  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_GROUP_LEN               , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_CHIP                    , 39  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_CHIP_LEN                , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_ADDR                    , 42  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_ADDR_LEN                , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_RESERVED                , 54  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_RESERVED );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_GRANULE                 , 55  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GRANULE );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_SIZE                    , 56  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_SIZE_LEN                , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE_LEN );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MODE                    , 60  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE );
+REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MODE_LEN                , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE_LEN );
+
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_ENABLE                  , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ENABLE );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE                 , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_GROUP                   , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_GROUP_LEN               , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_CHIP                    , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_CHIP_LEN                , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_ADDR                    , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_ADDR_LEN                , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_RESERVED                , 22  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_RESERVED );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_GRANULE                 , 23  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_GRANULE );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_SIZE                    , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_SIZE_LEN                , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MODE                    , 28  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MODE_LEN                , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU0_MODE_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_ENABLE                  , 32  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ENABLE );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE                 , 33  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN             , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MEMTYPE_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_GROUP                   , 35  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_GROUP_LEN               , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_CHIP                    , 39  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_CHIP_LEN                , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_ADDR                    , 42  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_ADDR_LEN                , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_RESERVED                , 54  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_RESERVED );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_GRANULE                 , 55  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_GRANULE );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_SIZE                    , 56  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_SIZE_LEN                , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_SIZE_LEN );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MODE                    , 60  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE );
+REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MODE_LEN                , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GPU1_MODE_LEN );
+
+REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0                    , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN0 );
+REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1                    , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN1 );
+REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2                    , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN2 );
+REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3                    , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN3 );
+REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4                    , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN4 );
+REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5                    , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN5 );
+REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6                    , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN6 );
+REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7                    , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN7 );
+REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8                    , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN8 );
+REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9                    , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN9 );
+REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10                   , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN10 );
+REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11                   , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN11 );
+
+REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0                    , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN0 );
+REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1                    , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN1 );
+REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2                    , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN2 );
+REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3                    , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN3 );
+REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4                    , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN4 );
+REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5                    , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN5 );
+REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6                    , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN6 );
+REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7                    , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN7 );
+REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8                    , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN8 );
+REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9                    , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN9 );
+REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10                   , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN10 );
+REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11                   , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN11 );
+
+REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0                    , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN0 );
+REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1                    , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN1 );
+REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2                    , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN2 );
+REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3                    , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN3 );
+REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4                    , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN4 );
+REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5                    , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN5 );
+REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6                    , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN6 );
+REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7                    , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN7 );
+REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8                    , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN8 );
+REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9                    , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN9 );
+REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10                   , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN10 );
+REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11                   , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN11 );
+
+REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN0                           , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN0  );
+REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN1                           , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN1  );
+REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN2                           , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN2  );
+REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN3                           , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN3  );
+REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN4                           , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN4  );
+REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN5                           , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN5  );
+REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN6                           , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN6  );
+REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN7                           , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN7  );
+REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN8                           , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN8  );
+REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN9                           , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN9  );
+REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN10                          , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN10 );
+REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN11                          , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN11 );
+
+REG64_FLD( PU_GZIP_CONTROL_REG_DISABLE_NEAR_HISTORY                , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_NEAR_HISTORY );
+REG64_FLD( PU_GZIP_CONTROL_REG_DISABLE_FAR_HISTORY                 , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_FAR_HISTORY );
+REG64_FLD( PU_GZIP_CONTROL_REG_DISABLE_EXTRA_HASH_ACCESSES         , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_EXTRA_HASH_ACCESSES );
+REG64_FLD( PU_GZIP_CONTROL_REG_DISABLE_EXTRA_FIFO_ACCESSES         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_EXTRA_FIFO_ACCESSES );
+REG64_FLD( PU_GZIP_CONTROL_REG_HASH_SIZE_MASK                      , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HASH_SIZE_MASK );
+REG64_FLD( PU_GZIP_CONTROL_REG_HASH_SIZE_MASK_LEN                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HASH_SIZE_MASK_LEN );
+
+REG64_FLD( PU_GZIP_ERRRPT_HOLD_REG_HOLD                            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HOLD       );
+REG64_FLD( PU_GZIP_ERRRPT_HOLD_REG_HOLD_LEN                        , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_LEN   );
+
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LPID );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN         , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LPID_LEN );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID              , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PID );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN          , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PID_LEN );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID              , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_TID );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN          , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_TID_LEN );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE           , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_ENABLE );
+
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN              , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LEN );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE             , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_SIZE );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_SIZE_LEN );
+
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET     , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_READ_OFFSET );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_READ_OFFSET_LEN );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED          , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_QUEUED );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN      , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_QUEUED_LEN );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX          , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PRIMAX );
+REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX_LEN      , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PRIMAX_LEN );
+
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LPID );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN         , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LPID_LEN );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID              , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PID );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN          , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PID_LEN );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID              , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_TID );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN          , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_TID_LEN );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE           , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_ENABLE );
+
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN              , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LEN );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE             , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_SIZE );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_SIZE_LEN );
+
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET     , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_READ_OFFSET );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_READ_OFFSET_LEN );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED          , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_QUEUED );
+REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN      , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_QUEUED_LEN );
+
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_LOW                                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOW        );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_LOW_LEN                            , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LOW_LEN    );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_HIGH                               , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HIGH       );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_HIGH_LEN                           , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HIGH_LEN   );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_THRESHOLD                          , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_THRESHOLD  );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_SRC_DDE                            , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRC_DDE    );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_SRC_DDE_LEN                        , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRC_DDE_LEN );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_TARGET_DDE                         , 19  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_TARGET_DDE );
+REG64_FLD( PU_GZIP_MAX_BYTE_CNT_TARGET_DDE_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_TARGET_DDE_LEN );
+
+REG64_FLD( PEC_HANG_PULSE_0_REG_0                                  , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_0          );
+REG64_FLD( PEC_HANG_PULSE_0_REG_0_LEN                              , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_LEN      );
+REG64_FLD( PEC_HANG_PULSE_0_REG_SUPPRESS                           , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( PEC_HANG_PULSE_1_REG_1                                  , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_1          );
+REG64_FLD( PEC_HANG_PULSE_1_REG_1_LEN                              , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_LEN      );
+REG64_FLD( PEC_HANG_PULSE_1_REG_SUPPRESS                           , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( PEC_HANG_PULSE_2_REG_2                                  , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_2          );
+REG64_FLD( PEC_HANG_PULSE_2_REG_2_LEN                              , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_2_LEN      );
+REG64_FLD( PEC_HANG_PULSE_2_REG_SUPPRESS                           , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( PEC_HANG_PULSE_3_REG_3                                  , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_3          );
+REG64_FLD( PEC_HANG_PULSE_3_REG_3_LEN                              , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_3_LEN      );
+REG64_FLD( PEC_HANG_PULSE_3_REG_SUPPRESS                           , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( PEC_HANG_PULSE_4_REG_4                                  , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4          );
+REG64_FLD( PEC_HANG_PULSE_4_REG_4_LEN                              , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LEN      );
+REG64_FLD( PEC_HANG_PULSE_4_REG_SUPPRESS                           , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( PEC_HANG_PULSE_5_REG_5                                  , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_5          );
+REG64_FLD( PEC_HANG_PULSE_5_REG_5_LEN                              , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_5_LEN      );
+REG64_FLD( PEC_HANG_PULSE_5_REG_SUPPRESS                           , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( PEC_HANG_PULSE_6_REG_6                                  , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_6          );
+REG64_FLD( PEC_HANG_PULSE_6_REG_6_LEN                              , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_6_LEN      );
+REG64_FLD( PEC_HANG_PULSE_6_REG_SUPPRESS                           , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( PU_HCA_BAR_ADDR                                         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR       );
+REG64_FLD( PU_HCA_BAR_ADDR_LEN                                     , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_HCA_BAR_RANGE                                        , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RANGE      );
+REG64_FLD( PU_HCA_BAR_RANGE_LEN                                    , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RANGE_LEN  );
+REG64_FLD( PU_HCA_BAR_PAGE_SIZE_64K                                , 62  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAGE_SIZE_64K );
+REG64_FLD( PU_HCA_BAR_VALID                                        , 63  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+
+REG64_FLD( PU_HCA_COUNT_BAR_ADDR                                   , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR       );
+REG64_FLD( PU_HCA_COUNT_BAR_ADDR_LEN                               , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_HCA_COUNT_BAR_VALID                                  , 63  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+
+REG64_FLD( PU_HCA_DROP_PIPE_COUNTER                                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PIPE_COUNTER );
+REG64_FLD( PU_HCA_DROP_PIPE_COUNTER_LEN                            , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PIPE_COUNTER_LEN );
+REG64_FLD( PU_HCA_DROP_WRITE_COUNTER                               , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_COUNTER );
+REG64_FLD( PU_HCA_DROP_WRITE_COUNTER_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_COUNTER_LEN );
+
+REG64_FLD( PU_HCA_FLUSH_INDEX                                      , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDEX      );
+REG64_FLD( PU_HCA_FLUSH_INDEX_LEN                                  , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDEX_LEN  );
+REG64_FLD( PU_HCA_FLUSH_CONG                                       , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONG       );
+REG64_FLD( PU_HCA_FLUSH_CONG_LEN                                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONG_LEN   );
+REG64_FLD( PU_HCA_FLUSH_COUNT                                      , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_COUNT      );
+REG64_FLD( PU_HCA_FLUSH_COUNT_LEN                                  , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_COUNT_LEN  );
+
+REG64_FLD( PU_HCA_MIRROR_BAR_ADDR                                  , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR       );
+REG64_FLD( PU_HCA_MIRROR_BAR_ADDR_LEN                              , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_HCA_MIRROR_BAR_VALID                                 , 63  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+
+REG64_FLD( PU_HCA_MODES_FULLMASK                                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FULLMASK   );
+REG64_FLD( PU_HCA_MODES_FULLMASK_LEN                               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FULLMASK_LEN );
+REG64_FLD( PU_HCA_MODES_ERROR_INJECT                               , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_INJECT );
+REG64_FLD( PU_HCA_MODES_ERROR_INJECT_LEN                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_INJECT_LEN );
+
+REG64_FLD( PU_HCA_REF_BAR_ADDR                                     , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR       );
+REG64_FLD( PU_HCA_REF_BAR_ADDR_LEN                                 , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_HCA_REF_BAR_VALID                                    , 63  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+
+REG64_FLD( PEC_HEARTBEAT_REG_DEAD                                  , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DEAD       );
+
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_XATS                      , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_XATS_LEN                  , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR0                      , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR1                      , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ0                      , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB0                      , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ1                      , 30  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB1                      , 36  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_RESERVED1                        , 42  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_HIGH_WATER_RESERVED1_LEN                    , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_XATS                      , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_XATS_LEN                  , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PWR0                      , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PWR1                      , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_REQ0                      , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PRB0                      , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_REQ1                      , 30  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PRB1                      , 36  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_RESERVED1                        , 42  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_HIGH_WATER_RESERVED1_LEN                    , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_XATS                      , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_XATS_LEN                  , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR0                      , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR1                      , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ0                      , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB0                      , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ1                      , 30  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB1                      , 36  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_RESERVED1                        , 42  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_HIGH_WATER_RESERVED1_LEN                    , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_XATS                      , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_XATS_LEN                  , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PWR0                      , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PWR1                      , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_REQ0                      , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PRB0                      , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_REQ1                      , 30  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PRB1                      , 36  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_RESERVED1                        , 42  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_HIGH_WATER_RESERVED1_LEN                    , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_XATS                      , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_XATS_LEN                  , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR0                      , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR1                      , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ0                      , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB0                      , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ1                      , 30  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB1                      , 36  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_RESERVED1                        , 42  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_HIGH_WATER_RESERVED1_LEN                    , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_XATS                      , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_XATS_LEN                  , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PWR0                      , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PWR1                      , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_REQ0                      , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PRB0                      , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_REQ1                      , 30  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PRB1                      , 36  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_RESERVED1                        , 42  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_HIGH_WATER_RESERVED1_LEN                    , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_XATS                      , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_XATS_LEN                  , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PWR0                      , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PWR1                      , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_REQ0                      , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PRB0                      , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_REQ1                      , 30  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PRB1                      , 36  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_RESERVED1                        , 42  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_HIGH_WATER_RESERVED1_LEN                    , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_XATS                      , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_XATS_LEN                  , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR0                      , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR1                      , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ0                      , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB0                      , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ1                      , 30  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB1                      , 36  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_RESERVED1                        , 42  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_HIGH_WATER_RESERVED1_LEN                    , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_XATS                      , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_XATS_LEN                  , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PWR0                      , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PWR1                      , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_REQ0                      , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PRB0                      , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_REQ1                      , 30  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PRB1                      , 36  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_RESERVED1                        , 42  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_HIGH_WATER_RESERVED1_LEN                    , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_XATS                      , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_XATS_LEN                  , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR0                      , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR1                      , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ0                      , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB0                      , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ1                      , 30  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB1                      , 36  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_RESERVED1                        , 42  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_HIGH_WATER_RESERVED1_LEN                    , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_XATS                      , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_XATS_LEN                  , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR0                      , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR1                      , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ0                      , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB0                      , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ1                      , 30  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB1                      , 36  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_RESERVED1                        , 42  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_HIGH_WATER_RESERVED1_LEN                    , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_XATS                      , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_XATS_LEN                  , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PWR0                      , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PWR0_LEN                  , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PWR1                      , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PWR1_LEN                  , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_REQ0                      , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_REQ0_LEN                  , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PRB0                      , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PRB0_LEN                  , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_REQ1                      , 30  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_REQ1_LEN                  , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PRB1                      , 36  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PRB1_LEN                  , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_RESERVED1                        , 42  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_HIGH_WATER_RESERVED1_LEN                    , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PEC_HOSTATTN_IN0                                        , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN0        );
+REG64_FLD( PEC_HOSTATTN_IN1                                        , 1   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN1        );
+REG64_FLD( PEC_HOSTATTN_IN2                                        , 2   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN2        );
+REG64_FLD( PEC_HOSTATTN_IN3                                        , 3   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN3        );
+REG64_FLD( PEC_HOSTATTN_IN4                                        , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN4        );
+REG64_FLD( PEC_HOSTATTN_IN5                                        , 5   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN5        );
+REG64_FLD( PEC_HOSTATTN_IN6                                        , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN6        );
+REG64_FLD( PEC_HOSTATTN_IN7                                        , 7   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN7        );
+REG64_FLD( PEC_HOSTATTN_IN8                                        , 8   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN8        );
+REG64_FLD( PEC_HOSTATTN_IN9                                        , 9   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN9        );
+REG64_FLD( PEC_HOSTATTN_IN10                                       , 10  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN10       );
+REG64_FLD( PEC_HOSTATTN_IN11                                       , 11  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN11       );
+REG64_FLD( PEC_HOSTATTN_IN12                                       , 12  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN12       );
+REG64_FLD( PEC_HOSTATTN_IN13                                       , 13  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN13       );
+REG64_FLD( PEC_HOSTATTN_IN14                                       , 14  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN14       );
+REG64_FLD( PEC_HOSTATTN_IN15                                       , 15  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN15       );
+REG64_FLD( PEC_HOSTATTN_IN16                                       , 16  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN16       );
+REG64_FLD( PEC_HOSTATTN_IN17                                       , 17  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN17       );
+REG64_FLD( PEC_HOSTATTN_IN18                                       , 18  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN18       );
+REG64_FLD( PEC_HOSTATTN_IN19                                       , 19  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN19       );
+REG64_FLD( PEC_HOSTATTN_IN20                                       , 20  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN20       );
+REG64_FLD( PEC_HOSTATTN_IN21                                       , 21  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN21       );
+REG64_FLD( PEC_HOSTATTN_IN22                                       , 22  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN22       );
+
+REG64_FLD( PEC_HOSTATTN_MASK_IN                                    , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( PEC_HOSTATTN_MASK_IN_LEN                                , 22  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO               , 0   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_OPER_HANG_DIV_RATIO );
+REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO_LEN           , 5   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_OPER_HANG_DIV_RATIO_LEN );
+REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_RTY_DRP_COUNT                     , 5   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_RTY_DRP_COUNT );
+REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_RTY_DRP_COUNT_LEN                 , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_RTY_DRP_COUNT_LEN );
+REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_DIS_DRP_PRIORITY_INCR             , 9   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_DRP_PRIORITY_INCR );
+REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_DIS_RETRY_BACKOFF                 , 10  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_RETRY_BACKOFF );
+REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_DIS_OPER_HANG                     , 11  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_OPER_HANG );
+
+REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO               , 0   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_OPER_HANG_DIV_RATIO );
+REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO_LEN           , 5   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_OPER_HANG_DIV_RATIO_LEN );
+REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_RTY_DRP_COUNT                     , 5   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_RTY_DRP_COUNT );
+REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_RTY_DRP_COUNT_LEN                 , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_RTY_DRP_COUNT_LEN );
+REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_DIS_DRP_PRIORITY_INCR             , 9   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_DRP_PRIORITY_INCR );
+REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_DIS_RETRY_BACKOFF                 , 10  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_RETRY_BACKOFF );
+REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_DIS_OPER_HANG                     , 11  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_OPER_HANG );
+
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_TRIG                             , 0   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TRIG );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_TRIG_LEN                         , 2   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TRIG_LEN );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_MARK                             , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_MARK_LEN                         , 2   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_LEN );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_DBG0_STOP                        , 6   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DBG0_STOP );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_DBG1_STOP                        , 7   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DBG1_STOP );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_RUN_STOP                         , 8   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_RUN_STOP );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_OTHER_DBG0_STOP                  , 9   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_OTHER_DBG0_STOP );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_SPARE1012                        , 10  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1012 );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_SPARE1012_LEN                    , 3   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1012_LEN );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_XSTOP_STOP                       , 13  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_XSTOP_STOP );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_SPARE1415                        , 14  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1415 );
+REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_SPARE1415_LEN                    , 2   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1415_LEN );
+
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_TRIG                             , 0   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TRIG );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_TRIG_LEN                         , 2   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TRIG_LEN );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_MARK                             , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_MARK_LEN                         , 2   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_LEN );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_DBG0_STOP                        , 6   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DBG0_STOP );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_DBG1_STOP                        , 7   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DBG1_STOP );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_RUN_STOP                         , 8   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_RUN_STOP );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_OTHER_DBG0_STOP                  , 9   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_OTHER_DBG0_STOP );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_SPARE1012                        , 10  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1012 );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_SPARE1012_LEN                    , 3   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1012_LEN );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_XSTOP_STOP                       , 13  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_XSTOP_STOP );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_SPARE1415                        , 14  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1415 );
+REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_SPARE1415_LEN                    , 2   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1415_LEN );
+
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_PAT                              , 0   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PAT  );
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_PAT_LEN                          , 23  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PAT_LEN );
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_CRESP_PAT                        , 27  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CRESP_PAT );
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_CRESP_PAT_LEN                    , 5   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CRESP_PAT_LEN );
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_MASK                             , 32  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MASK );
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_MASK_LEN                         , 23  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MASK_LEN );
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_CRESP_MASK                       , 59  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CRESP_MASK );
+REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_CRESP_MASK_LEN                   , 5   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CRESP_MASK_LEN );
+
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_PAT                              , 0   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PAT  );
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_PAT_LEN                          , 23  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PAT_LEN );
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_CRESP_PAT                        , 27  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CRESP_PAT );
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_CRESP_PAT_LEN                    , 5   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CRESP_PAT_LEN );
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_MASK                             , 32  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MASK );
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_MASK_LEN                         , 23  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MASK_LEN );
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_CRESP_MASK                       , 59  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CRESP_MASK );
+REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_CRESP_MASK_LEN                   , 5   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CRESP_MASK_LEN );
+
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL0                    , 0   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL0 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL0_LEN                , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL0_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL1                    , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL1 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL1_LEN                , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL1_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL2                    , 8   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL2 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL2_LEN                , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL2_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL3                    , 12  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL3 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL3_LEN                , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL3_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL4                    , 16  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL4 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL4_LEN                , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL4_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL5                    , 20  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL5 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL5_LEN                , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL5_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL0                    , 24  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_CGRPSEL0 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL0_LEN                , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_CGRPSEL0_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL1                    , 28  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_CGRPSEL1 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL1_LEN                , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_CGRPSEL1_LEN );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL2                    , 32  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_CGRPSEL2 );
+REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL2_LEN                , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_CGRPSEL2_LEN );
+
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL0                    , 0   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL0 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL0_LEN                , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL0_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL1                    , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL1 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL1_LEN                , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL1_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL2                    , 8   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL2 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL2_LEN                , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL2_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL3                    , 12  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL3 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL3_LEN                , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL3_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL4                    , 16  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL4 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL4_LEN                , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL4_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL5                    , 20  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL5 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL5_LEN                , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_RGRPSEL5_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL0                    , 24  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_CGRPSEL0 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL0_LEN                , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_CGRPSEL0_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL1                    , 28  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_CGRPSEL1 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL1_LEN                , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_CGRPSEL1_LEN );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL2                    , 32  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_CGRPSEL2 );
+REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL2_LEN                , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_FMUX_CGRPSEL2_LEN );
+
+REG64_FLD( PU_HTM0_HTM_LAST_ADDRESS                                , 8   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_HTM0_HTM_LAST_ADDRESS_LEN                            , 49  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_HTM1_HTM_LAST_ADDRESS                                , 8   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_HTM1_HTM_LAST_ADDRESS_LEN                            , 49  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_ALLOC                             , 0   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_ALLOC );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SCOPE                             , 1   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SCOPE );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SCOPE_LEN                         , 3   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SCOPE_LEN );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_PRIORITY                          , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PRIORITY );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SIZE_SMALL                        , 5   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SIZE_SMALL );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SPARE67                           , 6   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE67 );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SPARE67_LEN                       , 2   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE67_LEN );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_BASE                              , 8   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_BASE );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_BASE_LEN                          , 32  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_BASE_LEN );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SIZE                              , 40  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SIZE );
+REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SIZE_LEN                          , 9   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SIZE_LEN );
+
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_ALLOC                             , 0   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_ALLOC );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SCOPE                             , 1   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SCOPE );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SCOPE_LEN                         , 3   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SCOPE_LEN );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_PRIORITY                          , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PRIORITY );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SIZE_SMALL                        , 5   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SIZE_SMALL );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SPARE67                           , 6   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE67 );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SPARE67_LEN                       , 2   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE67_LEN );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_BASE                              , 8   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_BASE );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_BASE_LEN                          , 32  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_BASE_LEN );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SIZE                              , 40  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SIZE );
+REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SIZE_LEN                          , 9   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SIZE_LEN );
+
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_ENABLE                           , 0   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_ENABLE );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_CONTENT_SEL                      , 1   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CONTENT_SEL );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_CONTENT_SEL_LEN                  , 2   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CONTENT_SEL_LEN );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SPARE3                           , 3   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE3 );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_CAPTURE                          , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CAPTURE );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_CAPTURE_LEN                      , 9   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CAPTURE_LEN );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_WRAP                             , 13  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_WRAP );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_DIS_TSTAMP                       , 14  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_TSTAMP );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SINGLE_TSTAMP                    , 15  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SINGLE_TSTAMP );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SPARE16                          , 16  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE16 );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_MARKERS_ONLY                     , 17  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARKERS_ONLY );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_DIS_FORCE_GROUP_SCOPE            , 18  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_FORCE_GROUP_SCOPE );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SYNC_STAMP_FORCE                 , 19  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SYNC_STAMP_FORCE );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SYNC_STAMP_FORCE_LEN             , 3   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SYNC_STAMP_FORCE_LEN );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_WRITETOIO                        , 22  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_WRITETOIO );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SPARE23                          , 23  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE23 );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_VGTARGET                         , 24  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_VGTARGET );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_VGTARGET_LEN                     , 16  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_VGTARGET_LEN );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SPARE4043                        , 40  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE4043 );
+REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SPARE4043_LEN                    , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE4043_LEN );
+
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_ENABLE                           , 0   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_ENABLE );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_CONTENT_SEL                      , 1   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CONTENT_SEL );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_CONTENT_SEL_LEN                  , 2   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CONTENT_SEL_LEN );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SPARE3                           , 3   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE3 );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_CAPTURE                          , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CAPTURE );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_CAPTURE_LEN                      , 9   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CAPTURE_LEN );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_WRAP                             , 13  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_WRAP );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_DIS_TSTAMP                       , 14  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_TSTAMP );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SINGLE_TSTAMP                    , 15  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SINGLE_TSTAMP );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SPARE16                          , 16  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE16 );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_MARKERS_ONLY                     , 17  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARKERS_ONLY );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_DIS_FORCE_GROUP_SCOPE            , 18  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_FORCE_GROUP_SCOPE );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SYNC_STAMP_FORCE                 , 19  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SYNC_STAMP_FORCE );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SYNC_STAMP_FORCE_LEN             , 3   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SYNC_STAMP_FORCE_LEN );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_WRITETOIO                        , 22  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_WRITETOIO );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SPARE23                          , 23  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE23 );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_VGTARGET                         , 24  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_VGTARGET );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_VGTARGET_LEN                     , 16  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_VGTARGET_LEN );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SPARE4043                        , 40  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE4043 );
+REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SPARE4043_LEN                    , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE4043_LEN );
+
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_SPARE                     , 0   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_SPARE );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_SPARE_LEN                 , 2   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_SPARE_LEN );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_CRESP_OV                  , 2   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_CRESP_OV );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_REPAIR                    , 3   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_REPAIR );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_BUF_WAIT                  , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_BUF_WAIT );
+REG64_FLD( PU_HTM0_HTM_STAT_STATUS_TRIG_DROPPED_Q                  , 5   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_TRIG_DROPPED_Q );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_ADDR_ERROR                , 6   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_ADDR_ERROR );
+REG64_FLD( PU_HTM0_HTM_STAT_STATUS_REC_DROPPED_Q                   , 7   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_REC_DROPPED_Q );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_INIT                      , 8   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_INIT );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_PREREQ                    , 9   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_PREREQ );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_READY                     , 10  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_READY );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_TRACING                   , 11  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_TRACING );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_PAUSED                    , 12  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_PAUSED );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_FLUSH                     , 13  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_FLUSH );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_COMPLETE                  , 14  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_COMPLETE );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_ENABLE                    , 15  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_ENABLE );
+REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_STAMP                     , 16  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_STAMP );
+REG64_FLD( PU_HTM0_HTM_STAT_STATUS_SCOM_ERROR                      , 17  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_SCOM_ERROR );
+REG64_FLD( PU_HTM0_HTM_STAT_STATUS_PARITY_ERROR                    , 18  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_PARITY_ERROR );
+REG64_FLD( PU_HTM0_HTM_STAT_STATUS_INVALID_CRESP                   , 19  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_INVALID_CRESP );
+
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_SPARE                     , 0   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_SPARE );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_SPARE_LEN                 , 2   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_SPARE_LEN );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_CRESP_OV                  , 2   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_CRESP_OV );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_REPAIR                    , 3   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_REPAIR );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_BUF_WAIT                  , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_BUF_WAIT );
+REG64_FLD( PU_HTM1_HTM_STAT_STATUS_TRIG_DROPPED_Q                  , 5   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_TRIG_DROPPED_Q );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_ADDR_ERROR                , 6   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_ADDR_ERROR );
+REG64_FLD( PU_HTM1_HTM_STAT_STATUS_REC_DROPPED_Q                   , 7   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_REC_DROPPED_Q );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_INIT                      , 8   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_INIT );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_PREREQ                    , 9   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_PREREQ );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_READY                     , 10  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_READY );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_TRACING                   , 11  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_TRACING );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_PAUSED                    , 12  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_PAUSED );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_FLUSH                     , 13  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_FLUSH );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_COMPLETE                  , 14  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_COMPLETE );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_ENABLE                    , 15  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_ENABLE );
+REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_STAMP                     , 16  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_STAMP );
+REG64_FLD( PU_HTM1_HTM_STAT_STATUS_SCOM_ERROR                      , 17  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_SCOM_ERROR );
+REG64_FLD( PU_HTM1_HTM_STAT_STATUS_PARITY_ERROR                    , 18  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_PARITY_ERROR );
+REG64_FLD( PU_HTM1_HTM_STAT_STATUS_INVALID_CRESP                   , 19  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_INVALID_CRESP );
+
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_START                            , 0   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_START );
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_STOP                             , 1   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_STOP );
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_PAUSE                            , 2   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PAUSE );
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_STOP_ALT                         , 3   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_STOP_ALT );
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_RESET                            , 4   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_RESET );
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_MARK_VALID                       , 5   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_VALID );
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_MARK_TYPE                        , 6   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_TYPE );
+REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_MARK_TYPE_LEN                    , 10  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_TYPE_LEN );
+
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_START                            , 0   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_START );
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_STOP                             , 1   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_STOP );
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_PAUSE                            , 2   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PAUSE );
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_STOP_ALT                         , 3   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_STOP_ALT );
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_RESET                            , 4   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_RESET );
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_MARK_VALID                       , 5   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_VALID );
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_MARK_TYPE                        , 6   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_TYPE );
+REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_MARK_TYPE_LEN                    , 10  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_TYPE_LEN );
+
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_PAT                         , 1   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PAT  );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_PAT_LEN                     , 7   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PAT_LEN );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT               , 8   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TSIZEFILT_PAT );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT_LEN           , 8   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TSIZEFILT_PAT_LEN );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_MASK                        , 17  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MASK );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_MASK_LEN                    , 7   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MASK_LEN );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK              , 24  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TSIZEFILT_MASK );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK_LEN          , 8   , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TSIZEFILT_MASK_LEN );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_INVERT                      , 32  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_INVERT );
+REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_CRESPFILT_INVERT            , 33  , SH_UNT_PU_HTM0  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CRESPFILT_INVERT );
+
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_PAT                         , 1   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PAT  );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_PAT_LEN                     , 7   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PAT_LEN );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT               , 8   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TSIZEFILT_PAT );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT_LEN           , 8   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TSIZEFILT_PAT_LEN );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_MASK                        , 17  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MASK );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_MASK_LEN                    , 7   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MASK_LEN );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK              , 24  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TSIZEFILT_MASK );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK_LEN          , 8   , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TSIZEFILT_MASK_LEN );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_INVERT                      , 32  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_INVERT );
+REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_CRESPFILT_INVERT            , 33  , SH_UNT_PU_HTM1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CRESPFILT_INVERT );
+
+REG64_FLD( PU_I2C_BUSY_REGISTER_B_PEEK_DATA1_0                     , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_I2C_BUSY_REGISTER_B_PEEK_DATA1_0_LEN                 , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_I2C_BUSY_REGISTER_B_LBUS_PARITY_ERR1_0               , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_I2C_BUSY_REGISTER_C_PEEK_DATA1_1                     , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_I2C_BUSY_REGISTER_C_PEEK_DATA1_1_LEN                 , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_I2C_BUSY_REGISTER_C_LBUS_PARITY_ERR1_1               , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_I2C_BUSY_REGISTER_D_PEEK_DATA1_2                     , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_I2C_BUSY_REGISTER_D_PEEK_DATA1_2_LEN                 , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_I2C_BUSY_REGISTER_D_LBUS_PARITY_ERR1_2               , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_I2C_BUSY_REGISTER_E_PEEK_DATA1_3                     , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_I2C_BUSY_REGISTER_E_PEEK_DATA1_3_LEN                 , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_I2C_BUSY_REGISTER_E_LBUS_PARITY_ERR1_3               , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_NPU_CTL_INHIBIT_CONFIG_LFREQ                         , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ      );
+REG64_FLD( PU_NPU_CTL_INHIBIT_CONFIG_LFREQ_LEN                     , 4   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ_LEN  );
+REG64_FLD( PU_NPU_CTL_INHIBIT_CONFIG_IFREQ                         , 4   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IFREQ      );
+REG64_FLD( PU_NPU_CTL_INHIBIT_CONFIG_DEST                          , 5   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DEST       );
+REG64_FLD( PU_NPU_CTL_INHIBIT_CONFIG_DEST_LEN                      , 3   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DEST_LEN   );
+
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_LFREQ0                       , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0     );
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_LFREQ0_LEN                   , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0_LEN );
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_PFREQ0                       , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0     );
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_PFREQ0_LEN                   , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0_LEN );
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_BLOCKY0                      , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY0    );
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_ONESHOT0                     , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT0   );
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_DEST0                        , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_DEST0      );
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_DEST0_LEN                    , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_DEST0_LEN  );
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_LFREQ1                       , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1     );
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_LFREQ1_LEN                   , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1_LEN );
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_PFREQ1                       , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1     );
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_PFREQ1_LEN                   , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1_LEN );
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_BLOCKY1                      , 22  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY1    );
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_ONESHOT1                     , 23  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT1   );
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_DEST1                        , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_DEST1      );
+REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_DEST1_LEN                    , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_DEST1_LEN  );
+
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_LFREQ0                       , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0     );
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_LFREQ0_LEN                   , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0_LEN );
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_PFREQ0                       , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0     );
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_PFREQ0_LEN                   , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0_LEN );
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_BLOCKY0                      , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY0    );
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_ONESHOT0                     , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT0   );
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_DEST0                        , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_DEST0      );
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_DEST0_LEN                    , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_DEST0_LEN  );
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_LFREQ1                       , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1     );
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_LFREQ1_LEN                   , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1_LEN );
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_PFREQ1                       , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1     );
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_PFREQ1_LEN                   , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1_LEN );
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_BLOCKY1                      , 22  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY1    );
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_ONESHOT1                     , 23  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT1   );
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_DEST1                        , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_DEST1      );
+REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_DEST1_LEN                    , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_DEST1_LEN  );
+
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_LFREQ0                       , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0     );
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_LFREQ0_LEN                   , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0_LEN );
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_PFREQ0                       , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0     );
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_PFREQ0_LEN                   , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0_LEN );
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_BLOCKY0                      , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY0    );
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_ONESHOT0                     , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT0   );
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_DEST0                        , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_DEST0      );
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_DEST0_LEN                    , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_DEST0_LEN  );
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_LFREQ1                       , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1     );
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_LFREQ1_LEN                   , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1_LEN );
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_PFREQ1                       , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1     );
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_PFREQ1_LEN                   , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1_LEN );
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_BLOCKY1                      , 22  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY1    );
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_ONESHOT1                     , 23  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT1   );
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_DEST1                        , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_DEST1      );
+REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_DEST1_LEN                    , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_DEST1_LEN  );
+
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ0                       , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0     );
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ0_LEN                   , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0_LEN );
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ0                       , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0     );
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ0_LEN                   , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0_LEN );
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_BLOCKY0                      , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY0    );
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_ONESHOT0                     , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT0   );
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_DEST0                        , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_DEST0      );
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_DEST0_LEN                    , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_DEST0_LEN  );
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ1                       , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1     );
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ1_LEN                   , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1_LEN );
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ1                       , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1     );
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ1_LEN                   , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1_LEN );
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_BLOCKY1                      , 22  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY1    );
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_ONESHOT1                     , 23  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT1   );
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_DEST1                        , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_DEST1      );
+REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_DEST1_LEN                    , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_DEST1_LEN  );
+
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_LFREQ0                       , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0     );
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_LFREQ0_LEN                   , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0_LEN );
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_PFREQ0                       , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0     );
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_PFREQ0_LEN                   , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0_LEN );
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_BLOCKY0                      , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY0    );
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_ONESHOT0                     , 7   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT0   );
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_DEST0                        , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DEST0      );
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_DEST0_LEN                    , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DEST0_LEN  );
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_LFREQ1                       , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1     );
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_LFREQ1_LEN                   , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1_LEN );
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_PFREQ1                       , 20  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1     );
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_PFREQ1_LEN                   , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1_LEN );
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_BLOCKY1                      , 22  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY1    );
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_ONESHOT1                     , 23  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT1   );
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_DEST1                        , 24  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DEST1      );
+REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_DEST1_LEN                    , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DEST1_LEN  );
+
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_LFREQ0                       , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0     );
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_LFREQ0_LEN                   , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0_LEN );
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_PFREQ0                       , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0     );
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_PFREQ0_LEN                   , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0_LEN );
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_BLOCKY0                      , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY0    );
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_ONESHOT0                     , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT0   );
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_DEST0                        , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_DEST0      );
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_DEST0_LEN                    , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_DEST0_LEN  );
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_LFREQ1                       , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1     );
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_LFREQ1_LEN                   , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1_LEN );
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_PFREQ1                       , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1     );
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_PFREQ1_LEN                   , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1_LEN );
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_BLOCKY1                      , 22  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY1    );
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_ONESHOT1                     , 23  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT1   );
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_DEST1                        , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_DEST1      );
+REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_DEST1_LEN                    , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_DEST1_LEN  );
+
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ0                       , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0     );
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ0_LEN                   , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0_LEN );
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ0                       , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0     );
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ0_LEN                   , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0_LEN );
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_BLOCKY0                      , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY0    );
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_ONESHOT0                     , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT0   );
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_DEST0                        , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_DEST0      );
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_DEST0_LEN                    , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_DEST0_LEN  );
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ1                       , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1     );
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ1_LEN                   , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1_LEN );
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ1                       , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1     );
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ1_LEN                   , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1_LEN );
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_BLOCKY1                      , 22  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY1    );
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_ONESHOT1                     , 23  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT1   );
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_DEST1                        , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_DEST1      );
+REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_DEST1_LEN                    , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_DEST1_LEN  );
+
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ0                       , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0     );
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ0_LEN                   , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0_LEN );
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ0                       , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0     );
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ0_LEN                   , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0_LEN );
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_BLOCKY0                      , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY0    );
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_ONESHOT0                     , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT0   );
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_DEST0                        , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_DEST0      );
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_DEST0_LEN                    , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_DEST0_LEN  );
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ1                       , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1     );
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ1_LEN                   , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1_LEN );
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ1                       , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1     );
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ1_LEN                   , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1_LEN );
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_BLOCKY1                      , 22  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY1    );
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_ONESHOT1                     , 23  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT1   );
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_DEST1                        , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_DEST1      );
+REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_DEST1_LEN                    , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_DEST1_LEN  );
+
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ0                       , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0     );
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ0_LEN                   , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0_LEN );
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ0                       , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0     );
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ0_LEN                   , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0_LEN );
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_BLOCKY0                      , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY0    );
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_ONESHOT0                     , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT0   );
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_DEST0                        , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_DEST0      );
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_DEST0_LEN                    , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_DEST0_LEN  );
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ1                       , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1     );
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ1_LEN                   , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1_LEN );
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ1                       , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1     );
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ1_LEN                   , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1_LEN );
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_BLOCKY1                      , 22  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY1    );
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_ONESHOT1                     , 23  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT1   );
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_DEST1                        , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_DEST1      );
+REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_DEST1_LEN                    , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_DEST1_LEN  );
+
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ0                       , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0     );
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ0_LEN                   , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0_LEN );
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ0                       , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0     );
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ0_LEN                   , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0_LEN );
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_BLOCKY0                      , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY0    );
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_ONESHOT0                     , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT0   );
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_DEST0                        , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_DEST0      );
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_DEST0_LEN                    , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_DEST0_LEN  );
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ1                       , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1     );
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ1_LEN                   , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1_LEN );
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ1                       , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1     );
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ1_LEN                   , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1_LEN );
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_BLOCKY1                      , 22  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY1    );
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_ONESHOT1                     , 23  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT1   );
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_DEST1                        , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_DEST1      );
+REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_DEST1_LEN                    , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_DEST1_LEN  );
+
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_LFREQ0                       , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0     );
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_LFREQ0_LEN                   , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0_LEN );
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_PFREQ0                       , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0     );
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_PFREQ0_LEN                   , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0_LEN );
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_BLOCKY0                      , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY0    );
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_ONESHOT0                     , 7   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT0   );
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_DEST0                        , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DEST0      );
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_DEST0_LEN                    , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DEST0_LEN  );
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_LFREQ1                       , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1     );
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_LFREQ1_LEN                   , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1_LEN );
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_PFREQ1                       , 20  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1     );
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_PFREQ1_LEN                   , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1_LEN );
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_BLOCKY1                      , 22  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY1    );
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_ONESHOT1                     , 23  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT1   );
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_DEST1                        , 24  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DEST1      );
+REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_DEST1_LEN                    , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DEST1_LEN  );
+
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_LFREQ0                       , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0     );
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_LFREQ0_LEN                   , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0_LEN );
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_PFREQ0                       , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0     );
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_PFREQ0_LEN                   , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0_LEN );
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_BLOCKY0                      , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY0    );
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_ONESHOT0                     , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT0   );
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_DEST0                        , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_DEST0      );
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_DEST0_LEN                    , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_DEST0_LEN  );
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_LFREQ1                       , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1     );
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_LFREQ1_LEN                   , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1_LEN );
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_PFREQ1                       , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1     );
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_PFREQ1_LEN                   , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1_LEN );
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_BLOCKY1                      , 22  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY1    );
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_ONESHOT1                     , 23  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT1   );
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_DEST1                        , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_DEST1      );
+REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_DEST1_LEN                    , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_DEST1_LEN  );
+
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ0                       , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0     );
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ0_LEN                   , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0_LEN );
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ0                       , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0     );
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ0_LEN                   , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0_LEN );
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_BLOCKY0                      , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY0    );
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_ONESHOT0                     , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT0   );
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_DEST0                        , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_DEST0      );
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_DEST0_LEN                    , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_DEST0_LEN  );
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ1                       , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1     );
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ1_LEN                   , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1_LEN );
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ1                       , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1     );
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ1_LEN                   , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1_LEN );
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_BLOCKY1                      , 22  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY1    );
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_ONESHOT1                     , 23  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT1   );
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_DEST1                        , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_DEST1      );
+REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_DEST1_LEN                    , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_DEST1_LEN  );
+
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_LFREQ0                       , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0     );
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_LFREQ0_LEN                   , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0_LEN );
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_PFREQ0                       , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0     );
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_PFREQ0_LEN                   , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0_LEN );
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_BLOCKY0                      , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY0    );
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_ONESHOT0                     , 7   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT0   );
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_DEST0                        , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DEST0      );
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_DEST0_LEN                    , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DEST0_LEN  );
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_LFREQ1                       , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1     );
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_LFREQ1_LEN                   , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1_LEN );
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_PFREQ1                       , 20  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1     );
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_PFREQ1_LEN                   , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1_LEN );
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_BLOCKY1                      , 22  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY1    );
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_ONESHOT1                     , 23  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT1   );
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_DEST1                        , 24  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DEST1      );
+REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_DEST1_LEN                    , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DEST1_LEN  );
+
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_LFREQ0                       , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0     );
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_LFREQ0_LEN                   , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ0_LEN );
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_PFREQ0                       , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0     );
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_PFREQ0_LEN                   , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ0_LEN );
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_BLOCKY0                      , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY0    );
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_ONESHOT0                     , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT0   );
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_DEST0                        , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_DEST0      );
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_DEST0_LEN                    , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_DEST0_LEN  );
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_LFREQ1                       , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1     );
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_LFREQ1_LEN                   , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LFREQ1_LEN );
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_PFREQ1                       , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1     );
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_PFREQ1_LEN                   , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PFREQ1_LEN );
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_BLOCKY1                      , 22  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_BLOCKY1    );
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_ONESHOT1                     , 23  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_ONESHOT1   );
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_DEST1                        , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_DEST1      );
+REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_DEST1_LEN                    , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_DEST1_LEN  );
+
+REG64_FLD( PEC_INJECT_REG_THERM_TRIP                               , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_THERM_TRIP );
+REG64_FLD( PEC_INJECT_REG_THERM_TRIP_LEN                           , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_THERM_TRIP_LEN );
+REG64_FLD( PEC_INJECT_REG_THERM_MODE                               , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_THERM_MODE );
+REG64_FLD( PEC_INJECT_REG_THERM_MODE_LEN                           , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_THERM_MODE_LEN );
+
+REG64_FLD( PEC_STACK2_INTBAR_REG_PE_INT_BAR                        , 0   , SH_UNT_PEC_STACK2, SH_ACS_SCOM     ,
+           SH_FLD_PE_INT_BAR );
+REG64_FLD( PEC_STACK2_INTBAR_REG_PE_INT_BAR_LEN                    , 28  , SH_UNT_PEC_STACK2, SH_ACS_SCOM     ,
+           SH_FLD_PE_INT_BAR_LEN );
+
+REG64_FLD( PEC_STACK1_INTBAR_REG_PE_INT_BAR                        , 0   , SH_UNT_PEC_STACK1, SH_ACS_SCOM     ,
+           SH_FLD_PE_INT_BAR );
+REG64_FLD( PEC_STACK1_INTBAR_REG_PE_INT_BAR_LEN                    , 28  , SH_UNT_PEC_STACK1, SH_ACS_SCOM     ,
+           SH_FLD_PE_INT_BAR_LEN );
+
+REG64_FLD( PHB_INTBAR_REG_PE_INT_BAR                               , 0   , SH_UNT_PHB      , SH_ACS_SCOM     ,
+           SH_FLD_PE_INT_BAR );
+REG64_FLD( PHB_INTBAR_REG_PE_INT_BAR_LEN                           , 28  , SH_UNT_PHB      , SH_ACS_SCOM     ,
+           SH_FLD_PE_INT_BAR_LEN );
+
+REG64_FLD( PEC_STACK0_INTBAR_REG_PE_INT_BAR                        , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM     ,
+           SH_FLD_PE_INT_BAR );
+REG64_FLD( PEC_STACK0_INTBAR_REG_PE_INT_BAR_LEN                    , 28  , SH_UNT_PEC_STACK0, SH_ACS_SCOM     ,
+           SH_FLD_PE_INT_BAR_LEN );
+
+REG64_FLD( PU_INTERRUPTS_B_PEEK_DATA1_0                            , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_INTERRUPTS_B_PEEK_DATA1_0_LEN                        , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_INTERRUPTS_B_LBUS_PARITY_ERR1_0                      , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_INTERRUPTS_C_PEEK_DATA1_1                            , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_INTERRUPTS_C_PEEK_DATA1_1_LEN                        , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_INTERRUPTS_C_LBUS_PARITY_ERR1_1                      , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_INTERRUPTS_D_PEEK_DATA1_2                            , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_INTERRUPTS_D_PEEK_DATA1_2_LEN                        , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_INTERRUPTS_D_LBUS_PARITY_ERR1_2                      , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_INTERRUPTS_E_PEEK_DATA1_3                            , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_INTERRUPTS_E_PEEK_DATA1_3_LEN                        , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_INTERRUPTS_E_LBUS_PARITY_ERR1_3                      , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_INTERRUPT_COND_B_INVALID_CMD_0                       , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INVALID_CMD_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_LBUS_PARITY_ERROR_0                 , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERROR_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_BE_OV_ERROR_0                       , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_OV_ERROR_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_BE_ACC_ERROR_0                      , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_ACC_ERROR_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_ARBITRATION_LOST_ERROR_0            , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ARBITRATION_LOST_ERROR_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_NACK_RECEIVED_ERROR_0               , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NACK_RECEIVED_ERROR_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_DATA_REQUEST_0                      , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_REQUEST_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_STOP_ERROR_0                        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ERROR_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_PEEK_DATA1_0                        , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_INTERRUPT_COND_B_PEEK_DATA1_0_LEN                    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_INTERRUPT_COND_B_LBUS_PARITY_ERR1_0                  , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_INTERRUPT_COND_C_INVALID_CMD_1                       , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INVALID_CMD_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_LBUS_PARITY_ERROR_1                 , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERROR_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_BE_OV_ERROR_1                       , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_OV_ERROR_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_BE_ACC_ERROR_1                      , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_ACC_ERROR_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_ARBITRATION_LOST_ERROR_1            , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ARBITRATION_LOST_ERROR_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_NACK_RECEIVED_ERROR_1               , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NACK_RECEIVED_ERROR_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_DATA_REQUEST_1                      , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_REQUEST_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_STOP_ERROR_1                        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ERROR_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_PEEK_DATA1_1                        , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_INTERRUPT_COND_C_PEEK_DATA1_1_LEN                    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_INTERRUPT_COND_C_LBUS_PARITY_ERR1_1                  , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_INTERRUPT_COND_D_INVALID_CMD_2                       , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INVALID_CMD_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_LBUS_PARITY_ERROR_2                 , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERROR_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_BE_OV_ERROR_2                       , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_OV_ERROR_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_BE_ACC_ERROR_2                      , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_ACC_ERROR_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_ARBITRATION_LOST_ERROR_2            , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ARBITRATION_LOST_ERROR_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_NACK_RECEIVED_ERROR_2               , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NACK_RECEIVED_ERROR_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_DATA_REQUEST_2                      , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_REQUEST_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_STOP_ERROR_2                        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ERROR_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_PEEK_DATA1_2                        , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_INTERRUPT_COND_D_PEEK_DATA1_2_LEN                    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_INTERRUPT_COND_D_LBUS_PARITY_ERR1_2                  , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_INTERRUPT_COND_E_INVALID_CMD_3                       , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INVALID_CMD_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_LBUS_PARITY_ERROR_3                 , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERROR_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_BE_OV_ERROR_3                       , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_OV_ERROR_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_BE_ACC_ERROR_3                      , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_ACC_ERROR_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_ARBITRATION_LOST_ERROR_3            , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ARBITRATION_LOST_ERROR_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_NACK_RECEIVED_ERROR_3               , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NACK_RECEIVED_ERROR_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_DATA_REQUEST_3                      , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_REQUEST_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_STOP_ERROR_3                        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ERROR_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_PEEK_DATA1_3                        , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_INTERRUPT_COND_E_PEEK_DATA1_3_LEN                    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_INTERRUPT_COND_E_LBUS_PARITY_ERR1_3                  , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_B_INT_0                      , 16  , SH_UNT          , SH_ACS_SCOM2_AND,
+           SH_FLD_INT_0      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_B_INT_0_LEN                  , 16  , SH_UNT          , SH_ACS_SCOM2_AND,
+           SH_FLD_INT_0_LEN  );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_C_INT_1                      , 16  , SH_UNT          , SH_ACS_SCOM2_AND,
+           SH_FLD_INT_1      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_C_INT_1_LEN                  , 16  , SH_UNT          , SH_ACS_SCOM2_AND,
+           SH_FLD_INT_1_LEN  );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_D_INT_2                      , 16  , SH_UNT          , SH_ACS_SCOM2_AND,
+           SH_FLD_INT_2      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_D_INT_2_LEN                  , 16  , SH_UNT          , SH_ACS_SCOM2_AND,
+           SH_FLD_INT_2_LEN  );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_E_INT_3                      , 16  , SH_UNT          , SH_ACS_SCOM2_AND,
+           SH_FLD_INT_3      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_E_INT_3_LEN                  , 16  , SH_UNT          , SH_ACS_SCOM2_AND,
+           SH_FLD_INT_3_LEN  );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_B_INT_0                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INT_0      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_B_INT_0_LEN             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INT_0_LEN  );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_B_PEEK_DATA1_0          , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_B_PEEK_DATA1_0_LEN      , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_B_LBUS_PARITY_ERR1_0    , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_C_INT_1                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INT_1      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_C_INT_1_LEN             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INT_1_LEN  );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_C_PEEK_DATA1_1          , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_C_PEEK_DATA1_1_LEN      , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_C_LBUS_PARITY_ERR1_1    , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_D_INT_2                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INT_2      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_D_INT_2_LEN             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INT_2_LEN  );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_D_PEEK_DATA1_2          , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_D_PEEK_DATA1_2_LEN      , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_D_LBUS_PARITY_ERR1_2    , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_E_INT_3                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INT_3      );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_E_INT_3_LEN             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INT_3_LEN  );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_E_PEEK_DATA1_3          , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_E_PEEK_DATA1_3_LEN      , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_E_LBUS_PARITY_ERR1_3    , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_NPU_CTL_INT_0_CONFIG_0                               , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( PU_NPU_CTL_INT_0_CONFIG_0_LEN                           , 64  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_0_LEN      );
+
+REG64_FLD( PU_NPU_CTL_INT_1_CONFIG_1                               , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( PU_NPU_CTL_INT_1_CONFIG_1_LEN                           , 64  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_1_LEN      );
+
+REG64_FLD( PU_NPU_CTL_INT_BAR_CONFIG                               , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG     );
+REG64_FLD( PU_NPU_CTL_INT_BAR_CONFIG_LEN                           , 39  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_LEN );
+
+REG64_FLD( PU_INT_CQ_ACTION0_ACTION0                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( PU_INT_CQ_ACTION0_ACTION0_LEN                           , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_INT_CQ_ACTION1_ACTION1                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( PU_INT_CQ_ACTION1_ACTION1_LEN                           , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_INT_CQ_AIB_CTL_DIS_ECCCHK_IN                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DIS_ECCCHK_IN );
+REG64_FLD( PU_INT_CQ_AIB_CTL_EXTRA_CMD_SPACING_0_2                 , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EXTRA_CMD_SPACING_0_2 );
+REG64_FLD( PU_INT_CQ_AIB_CTL_EXTRA_CMD_SPACING_0_2_LEN             , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EXTRA_CMD_SPACING_0_2_LEN );
+REG64_FLD( PU_INT_CQ_AIB_CTL_EXTRA_DAT_SPACING_0_3                 , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EXTRA_DAT_SPACING_0_3 );
+REG64_FLD( PU_INT_CQ_AIB_CTL_EXTRA_DAT_SPACING_0_3_LEN             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EXTRA_DAT_SPACING_0_3_LEN );
+REG64_FLD( PU_INT_CQ_AIB_CTL_PC_PRIORITY_LIMIT_0_3                 , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PC_PRIORITY_LIMIT_0_3 );
+REG64_FLD( PU_INT_CQ_AIB_CTL_PC_PRIORITY_LIMIT_0_3_LEN             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PC_PRIORITY_LIMIT_0_3_LEN );
+REG64_FLD( PU_INT_CQ_AIB_CTL_VC_PRIORITY_LIMIT_0_3                 , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_VC_PRIORITY_LIMIT_0_3 );
+REG64_FLD( PU_INT_CQ_AIB_CTL_VC_PRIORITY_LIMIT_0_3_LEN             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_VC_PRIORITY_LIMIT_0_3_LEN );
+REG64_FLD( PU_INT_CQ_AIB_CTL_PRIORITY_LIMIT_0_3                    , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LIMIT_0_3 );
+REG64_FLD( PU_INT_CQ_AIB_CTL_PRIORITY_LIMIT_0_3_LEN                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LIMIT_0_3_LEN );
+REG64_FLD( PU_INT_CQ_AIB_CTL_BLOCK_CMD_OVERLAP                     , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BLOCK_CMD_OVERLAP );
+REG64_FLD( PU_INT_CQ_AIB_CTL_RESERVED_21_31                        , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_21_31 );
+REG64_FLD( PU_INT_CQ_AIB_CTL_RESERVED_21_31_LEN                    , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_21_31_LEN );
+REG64_FLD( PU_INT_CQ_AIB_CTL_CH0_CMD_CREDITS_0_5                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CH0_CMD_CREDITS_0_5 );
+REG64_FLD( PU_INT_CQ_AIB_CTL_CH0_CMD_CREDITS_0_5_LEN               , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CH0_CMD_CREDITS_0_5_LEN );
+REG64_FLD( PU_INT_CQ_AIB_CTL_CH1_CMD_CREDITS_0_5                   , 38  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CH1_CMD_CREDITS_0_5 );
+REG64_FLD( PU_INT_CQ_AIB_CTL_CH1_CMD_CREDITS_0_5_LEN               , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CH1_CMD_CREDITS_0_5_LEN );
+REG64_FLD( PU_INT_CQ_AIB_CTL_CH1_DAT_CREDITS_0_5                   , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CH1_DAT_CREDITS_0_5 );
+REG64_FLD( PU_INT_CQ_AIB_CTL_CH1_DAT_CREDITS_0_5_LEN               , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CH1_DAT_CREDITS_0_5_LEN );
+REG64_FLD( PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_PC_0_5                , 50  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CH2_CMD_CREDITS_PC_0_5 );
+REG64_FLD( PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_PC_0_5_LEN            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CH2_CMD_CREDITS_PC_0_5_LEN );
+REG64_FLD( PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_VC_0_5                , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CH2_CMD_CREDITS_VC_0_5 );
+REG64_FLD( PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_VC_0_5_LEN            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CH2_CMD_CREDITS_VC_0_5_LEN );
+REG64_FLD( PU_INT_CQ_AIB_CTL_RESERVED_62                           , 62  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_62 );
+REG64_FLD( PU_INT_CQ_AIB_CTL_REINIT_CREDITS                        , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REINIT_CREDITS );
+
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_IVE_MIN_0_4                       , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_IVE_MIN_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_IVE_MIN_0_4_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_IVE_MIN_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_IVE_MAX_0_4                       , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_IVE_MAX_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_IVE_MAX_0_4_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_IVE_MAX_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_EQD_MIN_0_4                       , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_EQD_MIN_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_EQD_MIN_0_4_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_EQD_MIN_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_EQD_MAX_0_4                       , 15  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_EQD_MAX_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_EQD_MAX_0_4_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_EQD_MAX_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_THR_MIN_0_4                       , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_THR_MIN_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_THR_MIN_0_4_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_THR_MIN_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_THR_MAX_0_4                       , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_THR_MAX_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_THR_MAX_0_4_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_THR_MAX_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_VPC_MIN_0_4                       , 30  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_VPC_MIN_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_VPC_MIN_0_4_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_VPC_MIN_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_VPC_MAX_0_4                       , 35  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_VPC_MAX_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_VPC_MAX_0_4_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_VPC_MAX_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_REG_MIN_0_4                       , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_REG_MIN_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_REG_MIN_0_4_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_REG_MIN_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_REG_MAX_0_4                       , 45  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_REG_MAX_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_REG_MAX_0_4_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_REG_MAX_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_REG_ORDER_ALL                     , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_REG_ORDER_ALL );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_RESERVED_51_63                        , 51  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_51_63 );
+REG64_FLD( PU_INT_CQ_CFG_LDQ_RESERVED_51_63_LEN                    , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_51_63_LEN );
+
+REG64_FLD( PU_INT_CQ_CFG_PB_GEN_ADDR_BAR_MODE                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_BAR_MODE );
+REG64_FLD( PU_INT_CQ_CFG_PB_GEN_PUMP_MODE                          , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUMP_MODE  );
+REG64_FLD( PU_INT_CQ_CFG_PB_GEN_PHYP_SCOPE                         , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PHYP_SCOPE );
+REG64_FLD( PU_INT_CQ_CFG_PB_GEN_INIT                               , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INIT       );
+REG64_FLD( PU_INT_CQ_CFG_PB_GEN_MODE_128K_VP                       , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MODE_128K_VP );
+REG64_FLD( PU_INT_CQ_CFG_PB_GEN_RESERVED_5_15                      , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_5_15 );
+REG64_FLD( PU_INT_CQ_CFG_PB_GEN_RESERVED_5_15_LEN                  , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_5_15_LEN );
+
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_IPI_MIN_0_4                      , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_IPI_MIN_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_IPI_MIN_0_4_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_IPI_MIN_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_IPI_MAX_0_4                      , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_IPI_MAX_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_IPI_MAX_0_4_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_IPI_MAX_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HW_MIN_0_4                       , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_HW_MIN_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HW_MIN_0_4_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_HW_MIN_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HW_MAX_0_4                       , 15  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_HW_MAX_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HW_MAX_0_4_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_HW_MAX_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_OS_MIN_0_4                       , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_OS_MIN_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_OS_MIN_0_4_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_OS_MIN_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_OS_MAX_0_4                       , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_OS_MAX_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_OS_MAX_0_4_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_OS_MAX_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HYP_MIN_0_4                      , 30  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_HYP_MIN_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HYP_MIN_0_4_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_HYP_MIN_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HYP_MAX_0_4                      , 35  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_HYP_MAX_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HYP_MAX_0_4_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_HYP_MAX_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_RDI_MIN_0_4                      , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_RDI_MIN_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_RDI_MIN_0_4_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_RDI_MIN_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_RDI_MAX_0_4                      , 45  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_RDI_MAX_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_RDI_MAX_0_4_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_RDI_MAX_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_THR_MIN_0_4                      , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_THR_MIN_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_THR_MIN_0_4_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_THR_MIN_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_THR_MAX_0_4                      , 55  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_THR_MAX_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_THR_MAX_0_4_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_THR_MAX_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_RESERVED_60_63                       , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_60_63 );
+REG64_FLD( PU_INT_CQ_CFG_STQ1_RESERVED_60_63_LEN                   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_60_63_LEN );
+
+REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_VPC_MIN_0_4                      , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_VPC_MIN_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_VPC_MIN_0_4_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_VPC_MIN_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_VPC_MAX_0_4                      , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_VPC_MAX_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_VPC_MAX_0_4_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_VPC_MAX_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_REG_MIN_0_4                      , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_REG_MIN_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_REG_MIN_0_4_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_REG_MIN_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_REG_MAX_0_4                      , 15  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_REG_MAX_0_4 );
+REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_REG_MAX_0_4_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_REG_MAX_0_4_LEN );
+REG64_FLD( PU_INT_CQ_CFG_STQ2_RESERVED_20_31                       , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_20_31 );
+REG64_FLD( PU_INT_CQ_CFG_STQ2_RESERVED_20_31_LEN                   , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_20_31_LEN );
+
+REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE0_0_2                   , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMON_MUX_BYTE0_0_2 );
+REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE0_0_2_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMON_MUX_BYTE0_0_2_LEN );
+REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE1_0_2                   , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMON_MUX_BYTE1_0_2 );
+REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE1_0_2_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMON_MUX_BYTE1_0_2_LEN );
+REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE2_0_2                   , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMON_MUX_BYTE2_0_2 );
+REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE2_0_2_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMON_MUX_BYTE2_0_2_LEN );
+REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE3_0_2                   , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMON_MUX_BYTE3_0_2 );
+REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE3_0_2_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMON_MUX_BYTE3_0_2_LEN );
+REG64_FLD( PU_INT_CQ_CNPM_SEL_RESERVED_12_23                       , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_12_23 );
+REG64_FLD( PU_INT_CQ_CNPM_SEL_RESERVED_12_23_LEN                   , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_12_23_LEN );
+REG64_FLD( PU_INT_CQ_CNPM_SEL_EBUS_ENABLE_0_15                     , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EBUS_ENABLE_0_15 );
+REG64_FLD( PU_INT_CQ_CNPM_SEL_EBUS_ENABLE_0_15_LEN                 , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EBUS_ENABLE_0_15_LEN );
+
+REG64_FLD( PU_INT_CQ_ERR_INFO0_INFO_CAPTURED                       , 0   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_INFO_CAPTURED );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD0_ADDR_PERR                     , 1   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RCMD0_ADDR_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD1_ADDR_PERR                     , 2   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RCMD1_ADDR_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD2_ADDR_PERR                     , 3   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RCMD2_ADDR_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD3_ADDR_PERR                     , 4   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RCMD3_ADDR_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD0_TTAG_PERR                     , 5   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RCMD0_TTAG_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD1_TTAG_PERR                     , 6   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RCMD1_TTAG_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD2_TTAG_PERR                     , 7   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RCMD2_TTAG_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD3_TTAG_PERR                     , 8   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RCMD3_TTAG_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_CR0_TTAG_PERR                       , 9   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CR0_TTAG_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_CR1_TTAG_PERR                       , 10  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CR1_TTAG_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_CR2_TTAG_PERR                       , 11  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CR2_TTAG_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_CR3_TTAG_PERR                       , 12  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CR3_TTAG_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_CR0_ATAG_PERR                       , 13  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CR0_ATAG_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_CR1_ATAG_PERR                       , 14  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CR1_ATAG_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_CR2_ATAG_PERR                       , 15  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CR2_ATAG_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_CR3_ATAG_PERR                       , 16  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CR3_ATAG_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO0_RTAG_PERR                           , 17  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RTAG_PERR  );
+
+REG64_FLD( PU_INT_CQ_ERR_INFO1_INFO_CAPTURED                       , 0   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_INFO_CAPTURED );
+REG64_FLD( PU_INT_CQ_ERR_INFO1_CI_WRITE                            , 1   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CI_WRITE   );
+REG64_FLD( PU_INT_CQ_ERR_INFO1_CI_READ                             , 2   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CI_READ    );
+REG64_FLD( PU_INT_CQ_ERR_INFO1_DMA_WRITE                           , 3   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DMA_WRITE  );
+REG64_FLD( PU_INT_CQ_ERR_INFO1_TSIZE_4_6                           , 4   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_TSIZE_4_6  );
+REG64_FLD( PU_INT_CQ_ERR_INFO1_TSIZE_4_6_LEN                       , 3   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_TSIZE_4_6_LEN );
+REG64_FLD( PU_INT_CQ_ERR_INFO1_RESERVED_7                          , 7   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RESERVED_7 );
+REG64_FLD( PU_INT_CQ_ERR_INFO1_ADDRESS_8_63                        , 8   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_ADDRESS_8_63 );
+REG64_FLD( PU_INT_CQ_ERR_INFO1_ADDRESS_8_63_LEN                    , 56  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_ADDRESS_8_63_LEN );
+
+REG64_FLD( PU_INT_CQ_ERR_INFO2_INFO_CAPTURED                       , 0   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_INFO_CAPTURED );
+REG64_FLD( PU_INT_CQ_ERR_INFO2_RESERVED_1_5                        , 1   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RESERVED_1_5 );
+REG64_FLD( PU_INT_CQ_ERR_INFO2_RESERVED_1_5_LEN                    , 5   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RESERVED_1_5_LEN );
+REG64_FLD( PU_INT_CQ_ERR_INFO2_HI                                  , 6   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_HI         );
+REG64_FLD( PU_INT_CQ_ERR_INFO2_LO                                  , 7   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_LO         );
+REG64_FLD( PU_INT_CQ_ERR_INFO2_RD_ADDR_0_7                         , 8   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RD_ADDR_0_7 );
+REG64_FLD( PU_INT_CQ_ERR_INFO2_RD_ADDR_0_7_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RD_ADDR_0_7_LEN );
+REG64_FLD( PU_INT_CQ_ERR_INFO2_SYN_HI_0_7                          , 16  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_SYN_HI_0_7 );
+REG64_FLD( PU_INT_CQ_ERR_INFO2_SYN_HI_0_7_LEN                      , 8   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_SYN_HI_0_7_LEN );
+REG64_FLD( PU_INT_CQ_ERR_INFO2_SYN_LO_0_7                          , 24  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_SYN_LO_0_7 );
+REG64_FLD( PU_INT_CQ_ERR_INFO2_SYN_LO_0_7_LEN                      , 8   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_SYN_LO_0_7_LEN );
+
+REG64_FLD( PU_INT_CQ_ERR_INFO3_INFO_CAPTURED                       , 0   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_INFO_CAPTURED );
+REG64_FLD( PU_INT_CQ_ERR_INFO3_STQ_FSM_PERR                        , 1   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_STQ_FSM_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO3_LDQ_FSM_PERR                        , 2   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_LDQ_FSM_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO3_WRQ_FSM_PERR                        , 3   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_WRQ_FSM_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO3_RDQ_FSM_PERR                        , 4   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RDQ_FSM_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO3_INTQ_FSM_PERR                       , 5   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_INTQ_FSM_PERR );
+REG64_FLD( PU_INT_CQ_ERR_INFO3_WRQ_OVERFLOW                        , 6   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_WRQ_OVERFLOW );
+REG64_FLD( PU_INT_CQ_ERR_INFO3_RDQ_OVERFLOW                        , 7   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RDQ_OVERFLOW );
+REG64_FLD( PU_INT_CQ_ERR_INFO3_INTQ_OVERFLOW                       , 8   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_INTQ_OVERFLOW );
+
+REG64_FLD( PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_48                        , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_0_48  );
+REG64_FLD( PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_48_LEN                    , 49  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_0_48_LEN );
+
+REG64_FLD( PU_INT_CQ_FIR_PI_ECC_CE                                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PI_ECC_CE  );
+REG64_FLD( PU_INT_CQ_FIR_PI_ECC_UE                                 , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PI_ECC_UE  );
+REG64_FLD( PU_INT_CQ_FIR_PI_ECC_SUE                                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PI_ECC_SUE );
+REG64_FLD( PU_INT_CQ_FIR_ST_ECC_CE                                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ST_ECC_CE  );
+REG64_FLD( PU_INT_CQ_FIR_ST_ECC_UE                                 , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ST_ECC_UE  );
+REG64_FLD( PU_INT_CQ_FIR_LD_ECC_CE                                 , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LD_ECC_CE  );
+REG64_FLD( PU_INT_CQ_FIR_LD_ECC_UE                                 , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LD_ECC_UE  );
+REG64_FLD( PU_INT_CQ_FIR_CL_ECC_CE                                 , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CL_ECC_CE  );
+REG64_FLD( PU_INT_CQ_FIR_CL_ECC_UE                                 , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CL_ECC_UE  );
+REG64_FLD( PU_INT_CQ_FIR_WR_ECC_CE                                 , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WR_ECC_CE  );
+REG64_FLD( PU_INT_CQ_FIR_WR_ECC_UE                                 , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WR_ECC_UE  );
+REG64_FLD( PU_INT_CQ_FIR_RD_ECC_CE                                 , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RD_ECC_CE  );
+REG64_FLD( PU_INT_CQ_FIR_RD_ECC_UE                                 , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RD_ECC_UE  );
+REG64_FLD( PU_INT_CQ_FIR_AI_ECC_CE                                 , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_AI_ECC_CE  );
+REG64_FLD( PU_INT_CQ_FIR_AI_ECC_UE                                 , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_AI_ECC_UE  );
+REG64_FLD( PU_INT_CQ_FIR_AIB_IN_CMD_CTL_PERR                       , 15  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_AIB_IN_CMD_CTL_PERR );
+REG64_FLD( PU_INT_CQ_FIR_AIB_IN_CMD_PERR                           , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_AIB_IN_CMD_PERR );
+REG64_FLD( PU_INT_CQ_FIR_AIB_IN_DAT_CTL_PERR                       , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_AIB_IN_DAT_CTL_PERR );
+REG64_FLD( PU_INT_CQ_FIR_PB_PARITY_ERROR                           , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PB_PARITY_ERROR );
+REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR1                          , 19  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PB_RCMDX_CI_ERR1 );
+REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR2                          , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PB_RCMDX_CI_ERR2 );
+REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR3                          , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PB_RCMDX_CI_ERR3 );
+REG64_FLD( PU_INT_CQ_FIR_RCVD_POISONED_CIST_DATA                   , 22  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RCVD_POISONED_CIST_DATA );
+REG64_FLD( PU_INT_CQ_FIR_MRT_ERR_NOT_VALID                         , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MRT_ERR_NOT_VALID );
+REG64_FLD( PU_INT_CQ_FIR_MRT_ERR_PSIZE                             , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MRT_ERR_PSIZE );
+REG64_FLD( PU_INT_CQ_FIR_SCOM_S_ERR                                , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SCOM_S_ERR );
+REG64_FLD( PU_INT_CQ_FIR_TCTXT_PRESP_ERROR                         , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_TCTXT_PRESP_ERROR );
+REG64_FLD( PU_INT_CQ_FIR_WRQ_OP_HANG                               , 27  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRQ_OP_HANG );
+REG64_FLD( PU_INT_CQ_FIR_RDQ_OP_HANG                               , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RDQ_OP_HANG );
+REG64_FLD( PU_INT_CQ_FIR_INTQ_OP_HANG                              , 29  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INTQ_OP_HANG );
+REG64_FLD( PU_INT_CQ_FIR_RDQ_DATA_HANG                             , 30  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RDQ_DATA_HANG );
+REG64_FLD( PU_INT_CQ_FIR_STQ_DATA_HANG                             , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_DATA_HANG );
+REG64_FLD( PU_INT_CQ_FIR_LDQ_DATA_HANG                             , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LDQ_DATA_HANG );
+REG64_FLD( PU_INT_CQ_FIR_WRQ_BAD_CRESP                             , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRQ_BAD_CRESP );
+REG64_FLD( PU_INT_CQ_FIR_RDQ_BAD_CRESP                             , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RDQ_BAD_CRESP );
+REG64_FLD( PU_INT_CQ_FIR_INTQ_BAD_CRESP                            , 35  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INTQ_BAD_CRESP );
+REG64_FLD( PU_INT_CQ_FIR_BAD_128K_VP_OP                            , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BAD_128K_VP_OP );
+REG64_FLD( PU_INT_CQ_FIR_RDQ_ABORT_OP                              , 37  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RDQ_ABORT_OP );
+REG64_FLD( PU_INT_CQ_FIR_PC_CRD_PERR                               , 38  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PC_CRD_PERR );
+REG64_FLD( PU_INT_CQ_FIR_PC_CRD_AVAIL_PERR                         , 39  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PC_CRD_AVAIL_PERR );
+REG64_FLD( PU_INT_CQ_FIR_VC_CRD_PERR                               , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VC_CRD_PERR );
+REG64_FLD( PU_INT_CQ_FIR_VC_CRD_AVAIL_PERR                         , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VC_CRD_AVAIL_PERR );
+REG64_FLD( PU_INT_CQ_FIR_CMD_QX_SEVERE_ERR                         , 42  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_QX_SEVERE_ERR );
+REG64_FLD( PU_INT_CQ_FIR_RDQ_ABORT_TRM                             , 43  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RDQ_ABORT_TRM );
+REG64_FLD( PU_INT_CQ_FIR_UNSOLICITED_CRESP                         , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNSOLICITED_CRESP );
+REG64_FLD( PU_INT_CQ_FIR_UNSOLICITED_PBDATA                        , 45  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNSOLICITED_PBDATA );
+REG64_FLD( PU_INT_CQ_FIR_FIR_PARITY_ERR                            , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_PARITY_ERR );
+REG64_FLD( PU_INT_CQ_FIR_RESERVED_47                               , 47  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_47 );
+REG64_FLD( PU_INT_CQ_FIR_RESERVED_48                               , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48 );
+REG64_FLD( PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2                        , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PC_FATAL_ERROR_0_2 );
+REG64_FLD( PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2_LEN                    , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PC_FATAL_ERROR_0_2_LEN );
+REG64_FLD( PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2                        , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PC_RECOV_ERROR_0_2 );
+REG64_FLD( PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2_LEN                    , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PC_RECOV_ERROR_0_2_LEN );
+REG64_FLD( PU_INT_CQ_FIR_PC_INFO_ERROR_0_2                         , 55  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PC_INFO_ERROR_0_2 );
+REG64_FLD( PU_INT_CQ_FIR_PC_INFO_ERROR_0_2_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PC_INFO_ERROR_0_2_LEN );
+REG64_FLD( PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1                        , 58  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VC_FATAL_ERROR_0_1 );
+REG64_FLD( PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VC_FATAL_ERROR_0_1_LEN );
+REG64_FLD( PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1                        , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VC_RECOV_ERROR_0_1 );
+REG64_FLD( PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VC_RECOV_ERROR_0_1_LEN );
+REG64_FLD( PU_INT_CQ_FIR_VC_INFO_ERROR_0_1                         , 62  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VC_INFO_ERROR_0_1 );
+REG64_FLD( PU_INT_CQ_FIR_VC_INFO_ERROR_0_1_LEN                     , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VC_INFO_ERROR_0_1_LEN );
+
+REG64_FLD( PU_INT_CQ_FIRMASK_FIR_MASK                              , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_MASK   );
+REG64_FLD( PU_INT_CQ_FIRMASK_FIR_MASK_LEN                          , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_MASK_LEN );
+
+REG64_FLD( PU_INT_CQ_IC_BAR_VALID                                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_INT_CQ_IC_BAR_PAGE_SIZE_64K                          , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAGE_SIZE_64K );
+REG64_FLD( PU_INT_CQ_IC_BAR_ADDR_8_48                              , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_8_48  );
+REG64_FLD( PU_INT_CQ_IC_BAR_ADDR_8_48_LEN                          , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_8_48_LEN );
+
+REG64_FLD( PU_INT_CQ_MSGSND_CORES_ENABLED_0_23                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CORES_ENABLED_0_23 );
+REG64_FLD( PU_INT_CQ_MSGSND_CORES_ENABLED_0_23_LEN                 , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CORES_ENABLED_0_23_LEN );
+
+REG64_FLD( PU_INT_CQ_PBI_CTL_DIS_ECCCHK                            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DIS_ECCCHK );
+REG64_FLD( PU_INT_CQ_PBI_CTL_DIS_ECCCHK_STO                        , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DIS_ECCCHK_STO );
+REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_2                            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_2 );
+REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_3                            , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_3 );
+REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_4                            , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_4 );
+REG64_FLD( PU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_PC                      , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PAGE_SIZE_64K_PC );
+REG64_FLD( PU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_VC                      , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PAGE_SIZE_64K_VC );
+REG64_FLD( PU_INT_CQ_PBI_CTL_LINUX_TRIG_MODE                       , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LINUX_TRIG_MODE );
+REG64_FLD( PU_INT_CQ_PBI_CTL_TRACE_BUS_SEL_0_1                     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_BUS_SEL_0_1 );
+REG64_FLD( PU_INT_CQ_PBI_CTL_TRACE_BUS_SEL_0_1_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_BUS_SEL_0_1_LEN );
+REG64_FLD( PU_INT_CQ_PBI_CTL_TRACE_SEL_0_1                         , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SEL_0_1 );
+REG64_FLD( PU_INT_CQ_PBI_CTL_TRACE_SEL_0_1_LEN                     , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SEL_0_1_LEN );
+REG64_FLD( PU_INT_CQ_PBI_CTL_DIS_DMA_W                             , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DIS_DMA_W  );
+REG64_FLD( PU_INT_CQ_PBI_CTL_STRICT_IPI_RULES                      , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STRICT_IPI_RULES );
+REG64_FLD( PU_INT_CQ_PBI_CTL_FORCE_ECC_CE                          , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ECC_CE );
+REG64_FLD( PU_INT_CQ_PBI_CTL_FORCE_ECC_UE                          , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ECC_UE );
+REG64_FLD( PU_INT_CQ_PBI_CTL_FORCE_ECC_SEL                         , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ECC_SEL );
+REG64_FLD( PU_INT_CQ_PBI_CTL_SPEC_CILD_G                           , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPEC_CILD_G );
+REG64_FLD( PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_IVE                      , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_SPEC_CILD_IVE );
+REG64_FLD( PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_EQD                      , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_SPEC_CILD_EQD );
+REG64_FLD( PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_VPC_HW                   , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_SPEC_CILD_VPC_HW );
+REG64_FLD( PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_VPC_SW                   , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_SPEC_CILD_VPC_SW );
+REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_22_31                        , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_22_31 );
+REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_22_31_LEN                    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_22_31_LEN );
+
+REG64_FLD( PU_INT_CQ_PBO_CTL_DIS_ECCCHK_LDO                        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DIS_ECCCHK_LDO );
+REG64_FLD( PU_INT_CQ_PBO_CTL_DIS_ECCCHK_WRO                        , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DIS_ECCCHK_WRO );
+REG64_FLD( PU_INT_CQ_PBO_CTL_DIS_ECCCHK_CLO                        , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DIS_ECCCHK_CLO );
+REG64_FLD( PU_INT_CQ_PBO_CTL_RESERVED_3                            , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_3 );
+REG64_FLD( PU_INT_CQ_PBO_CTL_STRICT_ORDER                          , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STRICT_ORDER );
+REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_MAX_SCOPE_INTRP                 , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_MAX_SCOPE_INTRP );
+REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_VG_SYS_INTRP                    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_VG_SYS_INTRP );
+REG64_FLD( PU_INT_CQ_PBO_CTL_DROP_PRI_INTRP                        , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DROP_PRI_INTRP );
+REG64_FLD( PU_INT_CQ_PBO_CTL_DROP_PRI_HPC_READ                     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DROP_PRI_HPC_READ );
+REG64_FLD( PU_INT_CQ_PBO_CTL_DROP_PRI_DMA                          , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DROP_PRI_DMA );
+REG64_FLD( PU_INT_CQ_PBO_CTL_DROP_MASK_0_5                         , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DROP_MASK_0_5 );
+REG64_FLD( PU_INT_CQ_PBO_CTL_DROP_MASK_0_5_LEN                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DROP_MASK_0_5_LEN );
+REG64_FLD( PU_INT_CQ_PBO_CTL_SLOW_CMD_RATE                         , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_CMD_RATE );
+REG64_FLD( PU_INT_CQ_PBO_CTL_EN_RANDOM_BACKOFF                     , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_RANDOM_BACKOFF );
+REG64_FLD( PU_INT_CQ_PBO_CTL_EN_POLL_BACKOFF                       , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN_POLL_BACKOFF );
+REG64_FLD( PU_INT_CQ_PBO_CTL_RESERVED_19                           , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_19 );
+REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_ECC_CE                          , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ECC_CE );
+REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_ECC_UE                          , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ECC_UE );
+REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_ECC_SEL_0_1                     , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ECC_SEL_0_1 );
+REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_ECC_SEL_0_1_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ECC_SEL_0_1_LEN );
+REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_INJECT                        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_INJECT );
+REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_CL_INJECT                       , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_CL_INJECT );
+REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_PR_INJECT                       , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_PR_INJECT );
+REG64_FLD( PU_INT_CQ_PBO_CTL_HANG_ON_ADDR_ERROR                    , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HANG_ON_ADDR_ERROR );
+REG64_FLD( PU_INT_CQ_PBO_CTL_HANG_ON_ACK_DEAD                      , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HANG_ON_ACK_DEAD );
+REG64_FLD( PU_INT_CQ_PBO_CTL_POLL_BCST_RTY_MON                     , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_POLL_BCST_RTY_MON );
+REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_1_0_4                  , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_POLL_BCAST_1_0_4 );
+REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_1_0_4_LEN              , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_POLL_BCAST_1_0_4_LEN );
+REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_2_0_4                  , 35  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_POLL_BCAST_2_0_4 );
+REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_2_0_4_LEN              , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_POLL_BCAST_2_0_4_LEN );
+REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_3_0_4                  , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_POLL_BCAST_3_0_4 );
+REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_3_0_4_LEN              , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_POLL_BCAST_3_0_4_LEN );
+REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_NN_RN                         , 45  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_NN_RN );
+REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_VG_NOT_SYS                    , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_G                             , 47  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_G  );
+REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_LN                            , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_LN );
+REG64_FLD( PU_INT_CQ_PBO_CTL_SKIP_G                                , 49  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SKIP_G     );
+REG64_FLD( PU_INT_CQ_PBO_CTL_RESERVED_50_63                        , 50  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_50_63 );
+REG64_FLD( PU_INT_CQ_PBO_CTL_RESERVED_50_63_LEN                    , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_50_63_LEN );
+
+REG64_FLD( PU_INT_CQ_PC_BAR_VALID                                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_INT_CQ_PC_BAR_ADDR_8_38                              , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_8_38  );
+REG64_FLD( PU_INT_CQ_PC_BAR_ADDR_8_38_LEN                          , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_8_38_LEN );
+
+REG64_FLD( PU_INT_CQ_PC_BARM_ADDR_26_38                            , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_26_38 );
+REG64_FLD( PU_INT_CQ_PC_BARM_ADDR_26_38_LEN                        , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_26_38_LEN );
+
+REG64_FLD( PU_INT_CQ_PMC_0_COUNT_47                                , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_47   );
+REG64_FLD( PU_INT_CQ_PMC_0_COUNT_47_LEN                            , 48  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_47_LEN );
+
+REG64_FLD( PU_INT_CQ_PMC_1_COUNT_0_47                              , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_0_47 );
+REG64_FLD( PU_INT_CQ_PMC_1_COUNT_0_47_LEN                          , 48  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_0_47_LEN );
+
+REG64_FLD( PU_INT_CQ_PMC_2_COUNT_0_47                              , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_0_47 );
+REG64_FLD( PU_INT_CQ_PMC_2_COUNT_0_47_LEN                          , 48  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_0_47_LEN );
+
+REG64_FLD( PU_INT_CQ_PMC_3_COUNT_0_47                              , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_0_47 );
+REG64_FLD( PU_INT_CQ_PMC_3_COUNT_0_47_LEN                          , 48  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_0_47_LEN );
+
+REG64_FLD( PU_INT_CQ_PMC_4_COUNT_0_47                              , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_0_47 );
+REG64_FLD( PU_INT_CQ_PMC_4_COUNT_0_47_LEN                          , 48  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_0_47_LEN );
+
+REG64_FLD( PU_INT_CQ_PMC_5_COUNT_0_47                              , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_0_47 );
+REG64_FLD( PU_INT_CQ_PMC_5_COUNT_0_47_LEN                          , 48  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_0_47_LEN );
+
+REG64_FLD( PU_INT_CQ_PMC_6_COUNT_0_47                              , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_0_47 );
+REG64_FLD( PU_INT_CQ_PMC_6_COUNT_0_47_LEN                          , 48  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_0_47_LEN );
+
+REG64_FLD( PU_INT_CQ_PMC_7_COUNT_0_47                              , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_0_47 );
+REG64_FLD( PU_INT_CQ_PMC_7_COUNT_0_47_LEN                          , 48  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_0_47_LEN );
+
+REG64_FLD( PU_INT_CQ_PM_CTL_ENABLE_0_7                             , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_0_7 );
+REG64_FLD( PU_INT_CQ_PM_CTL_ENABLE_0_7_LEN                         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_0_7_LEN );
+REG64_FLD( PU_INT_CQ_PM_CTL_RESET_0_7                              , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESET_0_7  );
+REG64_FLD( PU_INT_CQ_PM_CTL_RESET_0_7_LEN                          , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESET_0_7_LEN );
+REG64_FLD( PU_INT_CQ_PM_CTL_SOURCE_SUBUNIT_0_1                     , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SOURCE_SUBUNIT_0_1 );
+REG64_FLD( PU_INT_CQ_PM_CTL_SOURCE_SUBUNIT_0_1_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SOURCE_SUBUNIT_0_1_LEN );
+REG64_FLD( PU_INT_CQ_PM_CTL_GROUP_SEL_0_4                          , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_GROUP_SEL_0_4 );
+REG64_FLD( PU_INT_CQ_PM_CTL_GROUP_SEL_0_4_LEN                      , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_GROUP_SEL_0_4_LEN );
+
+REG64_FLD( PU_INT_CQ_RST_CTL_SYNC_RESET                            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SYNC_RESET );
+REG64_FLD( PU_INT_CQ_RST_CTL_QUIESCE_PB                            , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUIESCE_PB );
+REG64_FLD( PU_INT_CQ_RST_CTL_MASTER_IDLE                           , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_IDLE );
+REG64_FLD( PU_INT_CQ_RST_CTL_SLAVE_IDLE                            , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE_IDLE );
+REG64_FLD( PU_INT_CQ_RST_CTL_PB_BAR_RESET                          , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PB_BAR_RESET );
+REG64_FLD( PU_INT_CQ_RST_CTL_RESERVED_5_7                          , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_5_7 );
+REG64_FLD( PU_INT_CQ_RST_CTL_RESERVED_5_7_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_5_7_LEN );
+
+REG64_FLD( PU_INT_CQ_SWI_RSP_HIST_DONE                             , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIST_DONE  );
+REG64_FLD( PU_INT_CQ_SWI_RSP_POLL_DONE                             , 1   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_POLL_DONE  );
+REG64_FLD( PU_INT_CQ_SWI_RSP_BCAST_DONE                            , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_BCAST_DONE );
+REG64_FLD( PU_INT_CQ_SWI_RSP_ASSIGN_DONE                           , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ASSIGN_DONE );
+REG64_FLD( PU_INT_CQ_SWI_RSP_BLK_UPDT_DONE                         , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_BLK_UPDT_DONE );
+REG64_FLD( PU_INT_CQ_SWI_RSP_Z                                     , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_Z          );
+REG64_FLD( PU_INT_CQ_SWI_RSP_O                                     , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O          );
+REG64_FLD( PU_INT_CQ_SWI_RSP_M                                     , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_M          );
+REG64_FLD( PU_INT_CQ_SWI_RSP_CRESP_0_4                             , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CRESP_0_4  );
+REG64_FLD( PU_INT_CQ_SWI_RSP_CRESP_0_4_LEN                         , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CRESP_0_4_LEN );
+REG64_FLD( PU_INT_CQ_SWI_RSP_RESERVED_13                           , 13  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_13 );
+REG64_FLD( PU_INT_CQ_SWI_RSP_COLLISON                              , 14  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_COLLISON   );
+REG64_FLD( PU_INT_CQ_SWI_RSP_PRECLUDE                              , 15  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PRECLUDE   );
+REG64_FLD( PU_INT_CQ_SWI_RSP_ATAG_0_15                             , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ATAG_0_15  );
+REG64_FLD( PU_INT_CQ_SWI_RSP_ATAG_0_15_LEN                         , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ATAG_0_15_LEN );
+
+REG64_FLD( PU_INT_CQ_TAR_AUTO_INC                                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_AUTO_INC   );
+REG64_FLD( PU_INT_CQ_TAR_TABLE_SEL_0_3                             , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_TABLE_SEL_0_3 );
+REG64_FLD( PU_INT_CQ_TAR_TABLE_SEL_0_3_LEN                         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_TABLE_SEL_0_3_LEN );
+REG64_FLD( PU_INT_CQ_TAR_ENTRY_SEL_0_5                             , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENTRY_SEL_0_5 );
+REG64_FLD( PU_INT_CQ_TAR_ENTRY_SEL_0_5_LEN                         , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENTRY_SEL_0_5_LEN );
+
+REG64_FLD( PU_INT_CQ_TM1_BAR_VALID                                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_INT_CQ_TM1_BAR_PAGE_SIZE_64K                         , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAGE_SIZE_64K );
+REG64_FLD( PU_INT_CQ_TM1_BAR_ADDR_8_49                             , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_8_49  );
+REG64_FLD( PU_INT_CQ_TM1_BAR_ADDR_8_49_LEN                         , 42  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_8_49_LEN );
+
+REG64_FLD( PU_INT_CQ_TM2_BAR_VALID                                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_INT_CQ_TM2_BAR_PAGE_SIZE_64K                         , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAGE_SIZE_64K );
+REG64_FLD( PU_INT_CQ_TM2_BAR_ADDR_8_49                             , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_8_49  );
+REG64_FLD( PU_INT_CQ_TM2_BAR_ADDR_8_49_LEN                         , 42  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_8_49_LEN );
+
+REG64_FLD( PU_INT_CQ_VC_BAR_VALID                                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_INT_CQ_VC_BAR_ADDR_8_37                              , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_8_37  );
+REG64_FLD( PU_INT_CQ_VC_BAR_ADDR_8_37_LEN                          , 30  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_8_37_LEN );
+
+REG64_FLD( PU_INT_CQ_VC_BARM_ADDR_21_37                            , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_21_37 );
+REG64_FLD( PU_INT_CQ_VC_BARM_ADDR_21_37_LEN                        , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_21_37_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_VLD                         , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_LVL                         , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_LVL_LEN                     , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_CQ                          , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_CQ_LEN                      , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_DETAIL                      , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_DETAIL_LEN                  , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_RSVD0                       , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_RSVD0_LEN                   , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_VLD                         , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_LVL                         , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_LVL_LEN                     , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_CQ                          , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_CQ_LEN                      , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_DETAIL                      , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_DETAIL_LEN                  , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_RSVD0                       , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_RSVD0_LEN                   , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_VLD                        , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_LVL                        , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_LVL_LEN                    , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_CQ                         , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_CQ_LEN                     , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_DETAIL                     , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_DETAIL_LEN                 , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_RSVD0                      , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_RSVD0_LEN                  , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_VLD                        , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_LVL                        , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_LVL_LEN                    , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_CQ                         , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_CQ_LEN                     , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_DETAIL                     , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_DETAIL_LEN                 , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_RSVD0                      , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_RSVD0_LEN                  , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_VLD                        , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_LVL                        , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_LVL_LEN                    , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_CQ                         , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_CQ_LEN                     , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_DETAIL                     , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_DETAIL_LEN                 , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_RSVD0                      , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_RSVD0_LEN                  , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_VLD                        , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_LVL                        , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_LVL_LEN                    , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_CQ                         , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_CQ_LEN                     , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_DETAIL                     , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_DETAIL_LEN                 , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_RSVD0                      , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_RSVD0_LEN                  , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_VLD                        , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_LVL                        , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_LVL_LEN                    , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_CQ                         , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_CQ_LEN                     , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_DETAIL                     , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_DETAIL_LEN                 , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_RSVD0                      , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_RSVD0_LEN                  , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_VLD                        , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_LVL                        , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_LVL_LEN                    , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_CQ                         , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_CQ_LEN                     , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_DETAIL                     , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_DETAIL_LEN                 , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_RSVD0                      , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_RSVD0_LEN                  , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_VLD                         , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_LVL                         , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_LVL_LEN                     , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_CQ                          , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_CQ_LEN                      , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_DETAIL                      , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_DETAIL_LEN                  , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_RSVD0                       , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_RSVD0_LEN                   , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_VLD                         , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_LVL                         , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_LVL_LEN                     , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_CQ                          , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_CQ_LEN                      , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_DETAIL                      , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_DETAIL_LEN                  , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_RSVD0                       , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_RSVD0_LEN                   , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_VLD                         , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_LVL                         , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_LVL_LEN                     , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_CQ                          , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_CQ_LEN                      , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_DETAIL                      , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_DETAIL_LEN                  , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_RSVD0                       , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_RSVD0_LEN                   , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_VLD                         , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_LVL                         , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_LVL_LEN                     , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_CQ                          , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_CQ_LEN                      , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_DETAIL                      , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_DETAIL_LEN                  , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_RSVD0                       , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_RSVD0_LEN                   , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_VLD                         , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_LVL                         , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_LVL_LEN                     , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_CQ                          , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_CQ_LEN                      , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_DETAIL                      , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_DETAIL_LEN                  , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_RSVD0                       , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_RSVD0_LEN                   , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_VLD                         , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_LVL                         , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_LVL_LEN                     , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_CQ                          , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_CQ_LEN                      , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_DETAIL                      , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_DETAIL_LEN                  , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_RSVD0                       , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_RSVD0_LEN                   , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_VLD                         , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_LVL                         , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_LVL_LEN                     , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_CQ                          , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_CQ_LEN                      , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_DETAIL                      , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_DETAIL_LEN                  , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_RSVD0                       , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_RSVD0_LEN                   , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_VLD                         , 0   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_VLD    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_LVL                         , 1   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL    );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_LVL_LEN                     , 23  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_LVL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_CQ                          , 24  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ     );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_CQ_LEN                      , 12  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_CQ_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_DETAIL                      , 36  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_DETAIL_LEN                  , 20  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_DETAIL_LEN );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_RSVD0                       , 56  , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0  );
+REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_RSVD0_LEN                   , 8   , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ERR_RSVD0_LEN );
+
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_0_1                   , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_1 );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_0_1_LEN               , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_1_LEN );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH0_MAX                        , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH0_MAX    );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH0_MAX_LEN                    , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH0_MAX_LEN );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_8_9                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_9 );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_8_9_LEN               , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_9_LEN );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH1_MAX                        , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH1_MAX    );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH1_MAX_LEN                    , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH1_MAX_LEN );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_16_17                 , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_16_17_LEN             , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH2_MAX                        , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH2_MAX    );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH2_MAX_LEN                    , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH2_MAX_LEN );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_24_25                 , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_25 );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_24_25_LEN             , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_25_LEN );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH3_MAX                        , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH3_MAX    );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH3_MAX_LEN                    , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH3_MAX_LEN );
+
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_0_1                   , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_1 );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_0_1_LEN               , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_1_LEN );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH0_MAX                        , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH0_MAX    );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH0_MAX_LEN                    , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH0_MAX_LEN );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_8_9                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_9 );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_8_9_LEN               , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_9_LEN );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH1_MAX                        , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH1_MAX    );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH1_MAX_LEN                    , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH1_MAX_LEN );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_16_17                 , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_16_17_LEN             , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH2_MAX                        , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH2_MAX    );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH2_MAX_LEN                    , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH2_MAX_LEN );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_24_25                 , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_25 );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_24_25_LEN             , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_25_LEN );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH3_MAX                        , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH3_MAX    );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH3_MAX_LEN                    , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH3_MAX_LEN );
+
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_INIT_INIT_REQUEST                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INIT_REQUEST );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_INIT_RESERVED_1_7                  , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_7 );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_INIT_RESERVED_1_7_LEN              , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_7_LEN );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_INIT_INIT_TIMER                    , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INIT_TIMER );
+REG64_FLD( PU_INT_PC_AIB_RX_CRD_INIT_INIT_TIMER_LEN                , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INIT_TIMER_LEN );
+
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_CRD_INIT_REQUEST                   , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CRD_INIT_REQUEST );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_25                        , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_25 );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_DMA_READ                       , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_DMA_READ );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_DMA_READ_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_DMA_READ_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_LD_RMT                     , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_VPC_LD_RMT );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_LD_RMT_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_VPC_LD_RMT_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_AT_MACRO                       , 30  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_AT_MACRO );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_AT_MACRO_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_AT_MACRO_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_32_34                     , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_34 );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_32_34_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_34_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_READ_POOL                          , 35  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_POOL  );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_READ_POOL_LEN                      , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_POOL_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_40_47                     , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40_47 );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_40_47_LEN                 , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40_47_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_TCTXT_WRITE                    , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_TCTXT_WRITE );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_TCTXT_WRITE_LEN                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_TCTXT_WRITE_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_50_51                     , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_50_51 );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_50_51_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_50_51_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_DMA_WRITE                      , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_DMA_WRITE );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_DMA_WRITE_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_DMA_WRITE_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT                     , 54  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_VPC_ST_RMT );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_VPC_ST_RMT_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT_VC                  , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_VPC_ST_RMT_VC );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT_VC_LEN              , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_VPC_ST_RMT_VC_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_58                        , 58  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_58 );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_WRITE_POOL                         , 59  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRITE_POOL );
+REG64_FLD( PU_INT_PC_AIB_TX_CRD_WRITE_POOL_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRITE_POOL_LEN );
+
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_RESERVED_12_13                   , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_12_13 );
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_RESERVED_12_13_LEN               , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_12_13_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_RELAXED_WR_ORDERING              , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RELAXED_WR_ORDERING );
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_RESERVED_15                      , 15  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_15 );
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_REGS_ORDERING_TAG                , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGS_ORDERING_TAG );
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_REGS_ORDERING_TAG_LEN            , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGS_ORDERING_TAG_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_DMA_ORDERING_TAG             , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPC_DMA_ORDERING_TAG );
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_DMA_ORDERING_TAG_LEN         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPC_DMA_ORDERING_TAG_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_LD_RSP_ORDERING_TAG          , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPC_LD_RSP_ORDERING_TAG );
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_LD_RSP_ORDERING_TAG_LEN      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPC_LD_RSP_ORDERING_TAG_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_LD_RMT_ORDERING_TAG          , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPC_LD_RMT_ORDERING_TAG );
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_LD_RMT_ORDERING_TAG_LEN      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPC_LD_RMT_ORDERING_TAG_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_ORDERING_TAG          , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPC_ST_RMT_ORDERING_TAG );
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_ORDERING_TAG_LEN      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPC_ST_RMT_ORDERING_TAG_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_VC_ORDERING_TAG       , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPC_ST_RMT_VC_ORDERING_TAG );
+REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_VC_ORDERING_TAG_LEN   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPC_ST_RMT_VC_ORDERING_TAG_LEN );
+
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_LIMIT_AT_DEM_IN_PIPE          , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_LIMIT_AT_DEM_IN_PIPE );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_41_43                    , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_41_43 );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_41_43_LEN                , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_41_43_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_REGS                      , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_REGS );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_REGS_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_REGS_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_TCTXT_RSP_WR              , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_TCTXT_RSP_WR );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_TCTXT_RSP_WR_LEN          , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_TCTXT_RSP_WR_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_BLCK_UPD                  , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_BLCK_UPD );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_BLCK_UPD_LEN              , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_BLCK_UPD_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_50_51                    , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_50_51 );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_50_51_LEN                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_50_51_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_DMA                   , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_VPC_DMA );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_DMA_LEN               , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_VPC_DMA_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_CI_LD                 , 54  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_VPC_CI_LD );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_CI_LD_LEN             , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_VPC_CI_LD_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_LD_RMT                , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_VPC_LD_RMT );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_LD_RMT_LEN            , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_VPC_LD_RMT_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_LCL_VC             , 58  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_VPC_ST_LCL_VC );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_LCL_VC_LEN         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_VPC_ST_LCL_VC_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT                , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_VPC_ST_RMT );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT_LEN            , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_VPC_ST_RMT_LEN );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT_VC             , 62  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_VPC_ST_RMT_VC );
+REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT_VC_LEN         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_FOR_VPC_ST_RMT_VC_LEN );
+
+REG64_FLD( PU_INT_PC_AT_KILL_VALID                                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_INT_PC_AT_KILL_RESERVED_24_26                        , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_26 );
+REG64_FLD( PU_INT_PC_AT_KILL_RESERVED_24_26_LEN                    , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_26_LEN );
+REG64_FLD( PU_INT_PC_AT_KILL_BLOCKID                               , 27  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_PC_AT_KILL_BLOCKID_LEN                           , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_PC_AT_KILL_OFFSET                                , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_PC_AT_KILL_OFFSET_LEN                            , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET_LEN );
+REG64_FLD( PU_INT_PC_AT_KILL_RESERVED_61_63                        , 61  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_61_63 );
+REG64_FLD( PU_INT_PC_AT_KILL_RESERVED_61_63_LEN                    , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_61_63_LEN );
+
+REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_24_26                   , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_26 );
+REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_24_26_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_26_LEN );
+REG64_FLD( PU_INT_PC_AT_KILL_MASK_BLOCKID                          , 27  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_PC_AT_KILL_MASK_BLOCKID_LEN                      , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_PC_AT_KILL_MASK_OFFSET                           , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_PC_AT_KILL_MASK_OFFSET_LEN                       , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET_LEN );
+REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_61_63                   , 61  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_61_63 );
+REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_61_63_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_61_63_LEN );
+
+REG64_FLD( PU_INT_PC_DBG_ECC_DIS_CRESP_CORR                        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_CRESP_CORR );
+REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ARX_DAT_CORR                      , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_ARX_DAT_CORR );
+REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ARX_DAT_CORR_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_ARX_DAT_CORR_LEN );
+REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ARX_TAG_CORR                      , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_ARX_TAG_CORR );
+REG64_FLD( PU_INT_PC_DBG_ECC_DIS_MMIO_LDST_CORR                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_MMIO_LDST_CORR );
+REG64_FLD( PU_INT_PC_DBG_ECC_DIS_MMIO_RSP_CORR                     , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_MMIO_RSP_CORR );
+REG64_FLD( PU_INT_PC_DBG_ECC_DIS_VRQ_QUEUE_CORR                    , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_VRQ_QUEUE_CORR );
+REG64_FLD( PU_INT_PC_DBG_ECC_DIS_AVX_CORR                          , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_AVX_CORR );
+REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ATX_CMD_CORR                      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_ATX_CMD_CORR );
+REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ATX_BAR_CORR                      , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_ATX_BAR_CORR );
+REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ATX_AT_CORR                       , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_ATX_AT_CORR );
+REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_11_15                        , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_11_15 );
+REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_11_15_LEN                    , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_11_15_LEN );
+REG64_FLD( PU_INT_PC_DBG_ECC_FORCE_SINGLE_BIT_ERR                  , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_SINGLE_BIT_ERR );
+REG64_FLD( PU_INT_PC_DBG_ECC_FORCE_DOUBLE_BIT_ERR                  , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_DOUBLE_BIT_ERR );
+REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_CRESP_SRAM                 , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ARY_SELECT_CRESP_SRAM );
+REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_19                           , 19  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_19 );
+REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_CMD_RSP_SRAM               , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ARY_SELECT_CMD_RSP_SRAM );
+REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_CMD_VRQ_SRAM               , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ARY_SELECT_CMD_VRQ_SRAM );
+REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_CMD_SSA                , 22  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ARY_SELECT_ATX_CMD_SSA );
+REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_CMD_SSA_LEN            , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ARY_SELECT_ATX_CMD_SSA_LEN );
+REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_VPC_SSA                , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ARY_SELECT_ATX_VPC_SSA );
+REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_VPC_SSA_LEN            , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ARY_SELECT_ATX_VPC_SSA_LEN );
+REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_BAR_SRAM               , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ARY_SELECT_ATX_BAR_SRAM );
+REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_AT_SSA                 , 27  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ARY_SELECT_ATX_AT_SSA );
+REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_AIB                    , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ARY_SELECT_ATX_AIB );
+REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_AIB_LEN                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ARY_SELECT_ATX_AIB_LEN );
+REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_30_31                        , 30  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_30_31 );
+REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_30_31_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_30_31_LEN );
+
+REG64_FLD( PU_INT_PC_DBG_PMC_RESERVED_0_15                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_15 );
+REG64_FLD( PU_INT_PC_DBG_PMC_RESERVED_0_15_LEN                     , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_15_LEN );
+
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R0                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R0     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R0_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R0_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R1R                          , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1R    );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R1R_LEN                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1R_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R1W                          , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1W    );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R1W_LEN                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1W_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R2                           , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R2     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R2_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R2_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R3                           , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R3     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R3_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R3_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R4R                          , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4R    );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R4R_LEN                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4R_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R4W                          , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4W    );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R4W_LEN                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4W_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R5                           , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R5_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R6                           , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R6     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R6_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R6_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R7                           , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R7_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R8                           , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R8     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R8_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R8_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R9                           , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R9     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R9_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R9_LEN );
+
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R0                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R0     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R0_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R0_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R1R                          , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1R    );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R1R_LEN                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1R_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R1W                          , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1W    );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R1W_LEN                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1W_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R2                           , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R2     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R2_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R2_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R3                           , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R3     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R3_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R3_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R4R                          , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4R    );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R4R_LEN                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4R_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R4W                          , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4W    );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R4W_LEN                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4W_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R5                           , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R5_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R6                           , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R6     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R6_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R6_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R7                           , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R7_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R8                           , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R8     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R8_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R8_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R9                           , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R9     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R9_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R9_LEN );
+
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R0                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R0     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R0_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R0_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R1R                          , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1R    );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R1R_LEN                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1R_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R1W                          , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1W    );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R1W_LEN                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1W_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R2                           , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R2     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R2_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R2_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R3                           , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R3     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R3_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R3_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R4R                          , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4R    );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R4R_LEN                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4R_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R4W                          , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4W    );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R4W_LEN                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4W_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R5                           , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R5_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R6                           , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R6     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R6_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R6_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R7                           , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R7_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R8                           , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R8     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R8_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R8_LEN );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R9                           , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R9     );
+REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R9_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R9_LEN );
+
+REG64_FLD( PU_INT_PC_DBG_TMOT_RESERVED_0_1                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_1 );
+REG64_FLD( PU_INT_PC_DBG_TMOT_RESERVED_0_1_LEN                     , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_1_LEN );
+REG64_FLD( PU_INT_PC_DBG_TMOT_ARX_TIMEOUT                          , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ARX_TIMEOUT );
+REG64_FLD( PU_INT_PC_DBG_TMOT_ARX_TIMEOUT_LEN                      , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ARX_TIMEOUT_LEN );
+REG64_FLD( PU_INT_PC_DBG_TMOT_RESERVED_8_9                         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_9 );
+REG64_FLD( PU_INT_PC_DBG_TMOT_RESERVED_8_9_LEN                     , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_9_LEN );
+REG64_FLD( PU_INT_PC_DBG_TMOT_MMIO_LDST_TIMEOUT                    , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MMIO_LDST_TIMEOUT );
+REG64_FLD( PU_INT_PC_DBG_TMOT_MMIO_LDST_TIMEOUT_LEN                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MMIO_LDST_TIMEOUT_LEN );
+
+REG64_FLD( PU_INT_PC_DBG_TRACE_RESERVED_0                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0 );
+REG64_FLD( PU_INT_PC_DBG_TRACE_RESERVED_1                          , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1 );
+
+REG64_FLD( PU_INT_PC_EQD_BLOCK_MODE_MODE                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE       );
+REG64_FLD( PU_INT_PC_EQD_BLOCK_MODE_MODE_LEN                       , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_LEN   );
+
+REG64_FLD( PU_INT_PC_ERR0_CFG0_ERROR_CONFIG0                       , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG0 );
+REG64_FLD( PU_INT_PC_ERR0_CFG0_ERROR_CONFIG0_LEN                   , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG0_LEN );
+
+REG64_FLD( PU_INT_PC_ERR0_CFG1_ERROR_CONFIG0                       , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG0 );
+REG64_FLD( PU_INT_PC_ERR0_CFG1_ERROR_CONFIG0_LEN                   , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG0_LEN );
+
+REG64_FLD( PU_INT_PC_ERR0_FATAL_ERROR                              , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_ERR0_FATAL_ERROR_LEN                          , 64  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_ERR0_INFO_ERROR                               , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_ERR0_INFO_ERROR_LEN                           , 64  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_ERR0_RECOV_ERROR                              , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_ERR0_RECOV_ERROR_LEN                          , 64  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_ERR0_WOF_ERROR                                , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_ERR0_WOF_ERROR_LEN                            , 64  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_ERR0_WOF_DETAIL_DETAIL                        , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DETAIL     );
+REG64_FLD( PU_INT_PC_ERR0_WOF_DETAIL_DETAIL_LEN                    , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DETAIL_LEN );
+
+REG64_FLD( PU_INT_PC_ERR1_CFG0_ERROR_CONFIG0                       , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG0 );
+REG64_FLD( PU_INT_PC_ERR1_CFG0_ERROR_CONFIG0_LEN                   , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG0_LEN );
+
+REG64_FLD( PU_INT_PC_ERR1_CFG1_ERROR_CONFIG0                       , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG0 );
+REG64_FLD( PU_INT_PC_ERR1_CFG1_ERROR_CONFIG0_LEN                   , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG0_LEN );
+
+REG64_FLD( PU_INT_PC_ERR1_FATAL_ERROR                              , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_ERR1_FATAL_ERROR_LEN                          , 64  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_ERR1_INFO_ERROR                               , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_ERR1_INFO_ERROR_LEN                           , 64  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_ERR1_RECOV_ERROR                              , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_ERR1_RECOV_ERROR_LEN                          , 64  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_ERR1_WOF_ERROR                                , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_ERR1_WOF_ERROR_LEN                            , 64  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_ERR1_WOF_DETAIL_DETAIL                        , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DETAIL     );
+REG64_FLD( PU_INT_PC_ERR1_WOF_DETAIL_DETAIL_LEN                    , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DETAIL_LEN );
+
+REG64_FLD( PU_INT_PC_GLOBAL_CFG_INDIRECT_MODE                      , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDIRECT_MODE );
+REG64_FLD( PU_INT_PC_GLOBAL_CFG_RESERVED_33_39                     , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_33_39 );
+REG64_FLD( PU_INT_PC_GLOBAL_CFG_RESERVED_33_39_LEN                 , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_33_39_LEN );
+
+REG64_FLD( PU_INT_PC_IVE_BLOCK_MODE_MODE                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE       );
+REG64_FLD( PU_INT_PC_IVE_BLOCK_MODE_MODE_LEN                       , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_LEN   );
+
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_SET_LD                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_LDST_PRIO_SET_LD );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_SET_LD_LEN             , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_LDST_PRIO_SET_LD_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_RSP_LD                 , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_LDST_PRIO_RSP_LD );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_RSP_LD_LEN             , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_LDST_PRIO_RSP_LD_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_4_5                         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_4_5 );
+REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_4_5_LEN                     , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_4_5_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_PULL_RR_SEL           , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_PULL_RR_SEL_LEN       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_IACK_RR_SEL           , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_IACK_RR_SEL_LEN       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PULL_PRIO_HYP               , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DONE_PULL_PRIO_HYP );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PULL_PRIO_HYP_LEN           , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DONE_PULL_PRIO_HYP_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_IACK_PRIO_HYP               , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DONE_IACK_PRIO_HYP );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_IACK_PRIO_HYP_LEN           , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DONE_IACK_PRIO_HYP_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PRIO_IACK                   , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DONE_PRIO_IACK );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PRIO_IACK_LEN               , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_DONE_PRIO_IACK_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_16                          , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16 );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_SET               , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PCMD_PRIO_LDST_SET );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_SET_LEN           , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PCMD_PRIO_LDST_SET_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_20                          , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_20 );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_RSP               , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PCMD_PRIO_LDST_RSP );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_RSP_LEN           , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PCMD_PRIO_LDST_RSP_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_24                          , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24 );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_DONE                   , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PCMD_PRIO_DONE );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_DONE_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PCMD_PRIO_DONE_LEN );
+REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_28                          , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28 );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_RR                     , 29  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PCMD_PRIO_RR );
+REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_RR_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PCMD_PRIO_RR_LEN );
+
+REG64_FLD( PU_INT_PC_PCMD_ARB_RESERVED_0                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0 );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_LSI                         , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_LSI );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_LSI_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_LSI_LEN );
+REG64_FLD( PU_INT_PC_PCMD_ARB_RESERVED_4                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_4 );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_MMIO                        , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_MMIO );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_MMIO_LEN                    , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_MMIO_LEN );
+REG64_FLD( PU_INT_PC_PCMD_ARB_RESERVED_8                           , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8 );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_REQ                     , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_VRQ_REQ );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_REQ_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_VRQ_REQ_LEN );
+REG64_FLD( PU_INT_PC_PCMD_ARB_RESERVED_12                          , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_12 );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_RSP                     , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_VRQ_RSP );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_RSP_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_VRQ_RSP_LEN );
+REG64_FLD( PU_INT_PC_PCMD_ARB_RESERVED_16                          , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16 );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_RR                          , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_RR );
+REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_RR_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_RR_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_P0_IS_IDLE              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_P0_IS_IDLE );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_P1_IS_IDLE              , 1   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_P1_IS_IDLE );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_2_9            , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_2_9 );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_2_9_LEN        , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_2_9_LEN );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE         , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_PTAG_IN_USE );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE_LEN     , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_PTAG_IN_USE_LEN );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_16_27          , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_16_27 );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_16_27_LEN      , 12  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_16_27_LEN );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO      , 28  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_UNLOCK_IN_FIFO );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_UNLOCK_IN_FIFO_LEN );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_32_33          , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_32_33 );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_32_33_LEN      , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_32_33_LEN );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_WB      , 34  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_WB );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_WB_LEN  , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_WB_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_0_1            , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_0_1 );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_0_1_LEN        , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_0_1_LEN );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_VPD_FETCH , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_VPD_FETCH );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_VPD_FETCH_LEN , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_VPD_FETCH_LEN );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_8_9            , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_8_9 );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_8_9_LEN        , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_8_9_LEN );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_CI_LOAD );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD_LEN , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_CI_LOAD_LEN );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_16_17          , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_16_17_LEN      , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT  , 18  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_ST_RMT );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT_LEN , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_ST_RMT_LEN );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_24_25          , 24  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_24_25 );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_24_25_LEN      , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_24_25_LEN );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT_VC , 26  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_ST_RMT_VC );
+REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT_VC_LEN , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_ST_RMT_VC_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_CACHE_EN_ENABLE                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_INT_PC_VPC_CACHE_EN_ENABLE_LEN                       , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_VP                      , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VP         );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_SECURE                  , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SECURE     );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_PGOFFIRSTLS             , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGOFFIRSTLS );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_PGOFFIRSTLS_LEN         , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGOFFIRSTLS_LEN );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_BLOCK               , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVE_BLOCK  );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_BLOCK_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVE_BLOCK_LEN );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_INDEX               , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVE_INDEX  );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_INDEX_LEN           , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVE_INDEX_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA2_IPB                     , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IPB        );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA2_IPB_LEN                 , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IPB_LEN    );
+
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA3_MIG_REG                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MIG_REG    );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA3_MIG_REG_LEN             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MIG_REG_LEN );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA3_CL                      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CL         );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA3_CL_LEN                  , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CL_LEN     );
+
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_VG                      , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VG         );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_PGOFNEXTLS              , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGOFNEXTLS );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_PGOFNEXTLS_LEN          , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGOFNEXTLS_LEN );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_BLOCK               , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQD_BLOCK  );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_BLOCK_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQD_BLOCK_LEN );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_INDEX               , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQD_INDEX  );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_INDEX_LEN           , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQD_INDEX_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG0                   , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG0      );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG0_LEN               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG0_LEN  );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG1                   , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG1      );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG1_LEN               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG1_LEN  );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG2                   , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG2      );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG2_LEN               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG2_LEN  );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG3                   , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG3      );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG3_LEN               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG3_LEN  );
+
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG4                   , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG4      );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG4_LEN               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG4_LEN  );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG5                   , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG5      );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG5_LEN               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG5_LEN  );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG6                   , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG6      );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG6_LEN               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG6_LEN  );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG7                   , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG7      );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG7_LEN               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BKLG7_LEN  );
+
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_CONFLICT                 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CONFLICT   );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_1_7             , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_1_7 );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_1_7_LEN         , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_1_7_LEN );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_FULL                     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FULL       );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_9_26            , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_9_26 );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_9_26_LEN        , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_9_26_LEN );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_BLOCKID                  , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_BLOCKID_LEN              , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_32_44           , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_44 );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_32_44_LEN       , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_44_LEN );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_OFFSET                   , 45  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_OFFSET_LEN               , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_24_25                     , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_25 );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_24_25_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_25_LEN );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_PTAG_MAX_IN_USE                    , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PTAG_MAX_IN_USE );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_PTAG_MAX_IN_USE_LEN                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PTAG_MAX_IN_USE_LEN );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_32                        , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32 );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_SYNC_DONE                          , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_DONE  );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_SYNC_DONE_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_DONE_LEN );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_36_39                     , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_36_39 );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_36_39_LEN                 , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_36_39_LEN );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_LCL_FIRST_GRPSCAN_ENA              , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LCL_FIRST_GRPSCAN_ENA );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_LCL_FIRST_GRPSCAN_RMT_ENA          , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LCL_FIRST_GRPSCAN_RMT_ENA );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_RMT_FIRST_GRPSCAN_ENA              , 42  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RMT_FIRST_GRPSCAN_ENA );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_LSMFB_SCAN_ALL_PRIO_ENA            , 43  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LSMFB_SCAN_ALL_PRIO_ENA );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_P0_BACK2BACK_MODE_ENA              , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_P0_BACK2BACK_MODE_ENA );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_P0_BACK2BACK_MODE_ENA_LEN          , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_P0_BACK2BACK_MODE_ENA_LEN );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_47_51                     , 47  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_47_51 );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_47_51_LEN                 , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_47_51_LEN );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_BG_SCAN_RATE                       , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BG_SCAN_RATE );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_BG_SCAN_RATE_LEN                   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BG_SCAN_RATE_LEN );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_56_58                     , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_58 );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_56_58_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_58_LEN );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_MAX_ENTRIES_IN_MODIFIED            , 59  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_ENTRIES_IN_MODIFIED );
+REG64_FLD( PU_INT_PC_VPC_CONFIG_MAX_ENTRIES_IN_MODIFIED_LEN        , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_ENTRIES_IN_MODIFIED_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_DEBUG_RESERVED_0_29                       , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_29 );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_RESERVED_0_29_LEN                   , 30  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_29_LEN );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_LD_ECC_CORRECTION               , 30  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_LD_ECC_CORRECTION );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_TAG_ECC_CORRECTION              , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_TAG_ECC_CORRECTION );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN          , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_TAG_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_STATE_ECC_CORRECTION            , 39  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_STATE_ECC_CORRECTION );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_STATE_ECC_CORRECTION_LEN        , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_STATE_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_PTAG_ECC_CORRECTION             , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_PTAG_ECC_CORRECTION );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_PTAG_ECC_CORRECTION_LEN         , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_PTAG_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_DATA_ECC_CORRECTION             , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_DATA_ECC_CORRECTION );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_DATA_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR            , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_SINGLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR            , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_PARTITION_SEL           , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_PARTITION_SEL );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_PARTITION_SEL_LEN       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_PARTITION_SEL_LEN );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_ARRAY_SEL               , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_ARRAY_SEL );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_TRACE_ENABLE                        , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRACE_ENABLE );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_PMC_ENABLE                          , 57  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMC_ENABLE );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_RESERVED_58_59                      , 58  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_58_59 );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_RESERVED_58_59_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_58_59_LEN );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_USE_WATCH_TO_READ_CTRL_ARY          , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_USE_WATCH_TO_READ_CTRL_ARY );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_CACHE_CTRL_ARY_SELECT               , 61  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CACHE_CTRL_ARY_SELECT );
+REG64_FLD( PU_INT_PC_VPC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN           , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CACHE_CTRL_ARY_SELECT_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_ERR_CFG0_ERROR_CONFIG                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG );
+REG64_FLD( PU_INT_PC_VPC_ERR_CFG0_ERROR_CONFIG_LEN                 , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_ERR_CFG1_ERROR_CONFIG                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG );
+REG64_FLD( PU_INT_PC_VPC_ERR_CFG1_ERROR_CONFIG_LEN                 , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_FATAL_ERR_ERROR                           , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_VPC_FATAL_ERR_ERROR_LEN                       , 64  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_VPC_INFO_ERR_ERROR                            , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_VPC_INFO_ERR_ERROR_LEN                        , 64  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_0_25    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_25 );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_0_25_LEN , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_25_LEN );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT     , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CI_STORE_RMT );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT_LEN , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CI_STORE_RMT_LEN );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_32_33   , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_33 );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_32_33_LEN , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_33_LEN );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT_VC  , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CI_STORE_RMT_VC );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT_VC_LEN , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CI_STORE_RMT_VC_LEN );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_40_41   , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_40_41_LEN , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_LOAD          , 42  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CI_LOAD    );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_LOAD_LEN      , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CI_LOAD_LEN );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_48_49   , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48_49 );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_48_49_LEN , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48_49_LEN );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_READ     , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPD_DMA_READ );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_READ_LEN , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPD_DMA_READ_LEN );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_56_57   , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_57 );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_56_57_LEN , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_57_LEN );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_WRITE    , 58  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPD_DMA_WRITE );
+REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_WRITE_LEN , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VPD_DMA_WRITE_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PULL             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VRQ_PULL );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PULL_LEN         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VRQ_PULL_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_LOCAL       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VRQ_PUSH_LOCAL );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_LOCAL_LEN   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VRQ_PUSH_LOCAL_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_REMOTE      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VRQ_PUSH_REMOTE );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_REMOTE_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VRQ_PUSH_REMOTE_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_VC_LOAD     , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_NON_SPEC_VC_LOAD );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_VC_LOAD_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_NON_SPEC_VC_LOAD_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_SW_LOAD     , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_NON_SPEC_SW_LOAD );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_SW_LOAD_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_NON_SPEC_SW_LOAD_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_LOAD        , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_NON_SPEC_LOAD );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_LOAD_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_NON_SPEC_LOAD_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LOCAL_GROUP_SCAN     , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_GROUP_SCAN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LOCAL_GROUP_SCAN_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_GROUP_SCAN_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_CACHE_HIT        , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VRQ_CACHE_HIT );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_CACHE_HIT_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VRQ_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LD_CACHE_HIT         , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LD_CACHE_HIT );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LD_CACHE_HIT_LEN     , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LD_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_GROUP_SCAN_CACHE_HIT , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_GROUP_SCAN_CACHE_HIT );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_GROUP_SCAN_CACHE_HIT_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_GROUP_SCAN_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU        , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_LRU );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_LRU_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_FIRST_USABLE );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_FIRST_USABLE_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_RETRY                , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RETRY  );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_RETRY_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RETRY_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES     , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TOO_MANY_ENTRIES );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TOO_MANY_ENTRIES_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_RESERVED_56_63           , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_63 );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_RESERVED_56_63_LEN       , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_63_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_WB               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VPD_WB );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_WB_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VPD_WB_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_FETCH            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VPD_FETCH );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_FETCH_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VPD_FETCH_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_TCTXT        , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RSP_LCL_TCTXT );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_TCTXT_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RSP_LCL_TCTXT_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_VC           , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RSP_LCL_VC );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_VC_LEN       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RSP_LCL_VC_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT              , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RSP_RMT );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT_LEN          , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RSP_RMT_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT_VC           , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RSP_RMT_VC );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT_VC_LEN       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RSP_RMT_VC_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_SW_LD            , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RSP_SW_LD );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_SW_LD_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RSP_SW_LD_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STVP       , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RMT_PULL_1STVP );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STVP_LEN   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RMT_PULL_1STVP_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STGRP      , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RMT_PULL_1STGRP );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STGRP_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RMT_PULL_1STGRP_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_VP          , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RMT_PULL_VP );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_VP_LEN      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RMT_PULL_VP_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_GRP         , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RMT_PULL_GRP );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_GRP_LEN     , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RMT_PULL_GRP_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_PRESS_RELIEF     , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LCL_PRESS_RELIEF );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_PRESS_RELIEF_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LCL_PRESS_RELIEF_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_REDIST           , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LCL_REDIST );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_REDIST_LEN       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LCL_REDIST_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH             , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RMT_PUSH );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH_LEN         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RMT_PUSH_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH_VC          , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RMT_PUSH_VC );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH_VC_LEN      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RMT_PUSH_VC_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LCL_GRPSCAN_REPLAY   , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LCL_GRPSCAN_REPLAY );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LCL_GRPSCAN_REPLAY_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LCL_GRPSCAN_REPLAY_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_VPD_FETCH_REPLAY     , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VPD_FETCH_REPLAY );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_VPD_FETCH_REPLAY_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VPD_FETCH_REPLAY_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_TCTXT_REPLAY     , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RSP_TCTXT_REPLAY );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_TCTXT_REPLAY_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RSP_TCTXT_REPLAY_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_ATX_REPLAY       , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RSP_ATX_REPLAY );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_ATX_REPLAY_LEN   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RSP_ATX_REPLAY_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LD_REQ_REPLAY        , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LD_REQ_REPLAY );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LD_REQ_REPLAY_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LD_REQ_REPLAY_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_LCL_REPLAY        , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_ST_LCL_REPLAY );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_LCL_REPLAY_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_ST_LCL_REPLAY_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_REPLAY        , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_ST_RMT_REPLAY );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_REPLAY_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_ST_RMT_REPLAY_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_VC_REPLAY     , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_ST_RMT_VC_REPLAY );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_VC_REPLAY_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_ST_RMT_VC_REPLAY_LEN );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_SAME_VPD_REPLAY      , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_SAME_VPD_REPLAY );
+REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_SAME_VPD_REPLAY_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_SAME_VPD_REPLAY_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_RECOV_ERR_ERROR                           , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_VPC_RECOV_ERR_ERROR_LEN                       , 64  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_BLOCKID                        , 27  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_BLOCKID_LEN                    , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_RESERVED_32_44                 , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_44 );
+REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_RESERVED_32_44_LEN             , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_44_LEN );
+REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_OFFSET                         , 45  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_OFFSET_LEN                     , 19  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_VALID                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_WANT_CACHE_DISABLE             , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WANT_CACHE_DISABLE );
+REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_WANT_INVALIDATE                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WANT_INVALIDATE );
+REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_BLOCKID                        , 27  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_BLOCKID_LEN                    , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_RESERVED_32_44                 , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_44 );
+REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_RESERVED_32_44_LEN             , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_44_LEN );
+REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_OFFSET                         , 45  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_OFFSET_LEN                     , 19  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_PC_VPC_WOF_ERR_ERROR                             , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_VPC_WOF_ERR_ERROR_LEN                         , 64  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_VPC_WOF_ERR_DETAIL_ERROR                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_PC_VPC_WOF_ERR_DETAIL_ERROR_LEN                  , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_PC_VPD_BLOCK_MODE_MODE                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE       );
+REG64_FLD( PU_INT_PC_VPD_BLOCK_MODE_MODE_LEN                       , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_LEN   );
+
+REG64_FLD( PU_INT_PC_VRQ_CFG_CFG_CORE_PUSH_EN                      , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CORE_PUSH_EN );
+REG64_FLD( PU_INT_PC_VRQ_CFG_RESERVED_1_2                          , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_2 );
+REG64_FLD( PU_INT_PC_VRQ_CFG_RESERVED_1_2_LEN                      , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_2_LEN );
+REG64_FLD( PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PULL                   , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_QUEUE_SIZE_PULL );
+REG64_FLD( PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PULL_LEN               , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_QUEUE_SIZE_PULL_LEN );
+REG64_FLD( PU_INT_PC_VRQ_CFG_RESERVED_8_10                         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_10 );
+REG64_FLD( PU_INT_PC_VRQ_CFG_RESERVED_8_10_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_10_LEN );
+REG64_FLD( PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PUSH_LCL               , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL );
+REG64_FLD( PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PUSH_LCL_LEN           , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL_LEN );
+
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_QUERY_RR_SEL           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PARSE_QUERY_RR_SEL );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_1                       , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1 );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PULL_RR_SEL            , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PARSE_PULL_RR_SEL );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PULL_RR_SEL_LEN        , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PARSE_PULL_RR_SEL_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PUSH_RR_SEL            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PARSE_PUSH_RR_SEL );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PUSH_RR_SEL_LEN        , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PARSE_PUSH_RR_SEL_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_6_7                     , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_6_7 );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_6_7_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_6_7_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PULL_PRIO_HYP                , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PULL_PRIO_HYP );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PULL_PRIO_HYP_LEN            , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PULL_PRIO_HYP_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PUSH_PRIO_HYP                , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUSH_PRIO_HYP );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PUSH_PRIO_HYP_LEN            , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUSH_PRIO_HYP_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_12_16                   , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_12_16 );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_12_16_LEN               , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_12_16_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_QUERY                   , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_QUERY );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_QUERY_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_QUERY_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_20                      , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_20 );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PUSH                    , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_PUSH );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PUSH_LEN                , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_PUSH_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_24                      , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24 );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PULL                    , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_PULL );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PULL_LEN                , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_PULL_LEN );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_28                      , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28 );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_RR                      , 29  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_RR );
+REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_RR_LEN                  , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_RR_LEN );
+
+REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_RESERVED_0                        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0 );
+REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RSVD                     , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_RSVD );
+REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RSVD_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_RSVD_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_STALL_PULL                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_STALL_PULL );
+REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PULL                     , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_PULL );
+REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PULL_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_PULL_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_STALL_PUSH_LCL                , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_STALL_PUSH_LCL );
+REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_LCL                 , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_PUSH_LCL );
+REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_LCL_LEN             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_PUSH_LCL_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_STALL_PUSH_ARX                , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_STALL_PUSH_ARX );
+REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_ARX                 , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_PUSH_ARX );
+REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_ARX_LEN             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_PUSH_ARX_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_RESERVED_16                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16 );
+REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RR                       , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_RR );
+REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RR_LEN                   , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PRIO_RR_LEN );
+
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_0_1                      , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_1 );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_0_1_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_1_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_RSVD                     , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PULL_RSVD );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_RSVD_LEN                 , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PULL_RSVD_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_8_9                      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_9 );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_8_9_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_9_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_LMIT                     , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PULL_LMIT );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_LMIT_LEN                 , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PULL_LMIT_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_16_17                    , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16_17 );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_16_17_LEN                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16_17_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_RSVD                 , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUSH_LCL_RSVD );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_RSVD_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUSH_LCL_RSVD_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_24_25                    , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_25 );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_24_25_LEN                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_25_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_LMIT                 , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUSH_LCL_LMIT );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_LMIT_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUSH_LCL_LMIT_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_32_33                    , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_33 );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_32_33_LEN                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_33_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_RSVD                 , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUSH_ARX_RSVD );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_RSVD_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUSH_ARX_RSVD_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_40_41                    , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_40_41_LEN                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_LMIT                 , 42  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUSH_ARX_LMIT );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_LMIT_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUSH_ARX_LMIT_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_48_49                    , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48_49 );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_48_49_LEN                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48_49_LEN );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_MAX                           , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MAX    );
+REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_MAX_LEN                       , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MAX_LEN );
+
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_AUTO_INCREMENT                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_AUTO_INCREMENT );
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_1_3                   , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_3 );
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_1_3_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_3_LEN );
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_12                    , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_12 );
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_SELECT                         , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT     );
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_SELECT_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_LEN );
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_24_26                 , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_26 );
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_24_26_LEN             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_26_LEN );
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_ADDRESS                        , 27  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_ADDRESS_LEN                    , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_00                         , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_00 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_01                         , 1   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_01 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_02                         , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_02 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_03                         , 3   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_03 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_04                         , 4   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_04 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_05                         , 5   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_05 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_06                         , 6   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_06 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_07                         , 7   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_07 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_08                         , 8   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_08 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_09                         , 9   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_09 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_10                         , 10  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_10 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_11                         , 11  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_11 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_12                         , 12  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_12 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_13                         , 13  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_13 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_14                         , 14  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_14 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_15                         , 15  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_15 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_16                         , 16  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_16 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_17                         , 17  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_17 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_18                         , 18  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_18 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_19                         , 19  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_19 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_20                         , 20  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_20 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_21                         , 21  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_21 );
+REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_22                         , 22  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_22 );
+
+REG64_FLD( PU_INT_TCTXT_CFG_CFG_BLOCK_GROUP_EN                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_BLOCK_GROUP_EN );
+REG64_FLD( PU_INT_TCTXT_CFG_CFG_ACM_EN                             , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_ACM_EN );
+REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_2_3                           , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_2_3 );
+REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_2_3_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_2_3_LEN );
+REG64_FLD( PU_INT_TCTXT_CFG_CFG_FUSE_CORE_EN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_FUSE_CORE_EN );
+REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_5                             , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_5 );
+REG64_FLD( PU_INT_TCTXT_CFG_CFG_SMT_MODE                           , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SMT_MODE );
+REG64_FLD( PU_INT_TCTXT_CFG_CFG_SMT_MODE_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_SMT_MODE_LEN );
+REG64_FLD( PU_INT_TCTXT_CFG_CFG_HARD_CHIPID_IN_BLOCK_EN            , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_HARD_CHIPID_IN_BLOCK_EN );
+REG64_FLD( PU_INT_TCTXT_CFG_CFG_CHIPID_OVERRIDE                    , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CHIPID_OVERRIDE );
+REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_10_11                         , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_10_11 );
+REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_10_11_LEN                     , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_10_11_LEN );
+REG64_FLD( PU_INT_TCTXT_CFG_CFG_CHIPID                             , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CHIPID );
+REG64_FLD( PU_INT_TCTXT_CFG_CFG_CHIPID_LEN                         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_CHIPID_LEN );
+REG64_FLD( PU_INT_TCTXT_CFG_CFG_EN                                 , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_EN     );
+REG64_FLD( PU_INT_TCTXT_CFG_CFG_MSGSND                             , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_MSGSND );
+REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_18_19                         , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_18_19 );
+REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_18_19_LEN                     , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_18_19_LEN );
+REG64_FLD( PU_INT_TCTXT_CFG_CFG_PULSE_WIDTH                        , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PULSE_WIDTH );
+REG64_FLD( PU_INT_TCTXT_CFG_CFG_PULSE_WIDTH_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PULSE_WIDTH_LEN );
+
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C0_EN                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C0_EN );
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C0_EN_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C0_EN_LEN );
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C1_EN                         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C1_EN );
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C1_EN_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C1_EN_LEN );
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C2_EN                         , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C2_EN );
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C2_EN_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C2_EN_LEN );
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C3_EN                         , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C3_EN );
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C3_EN_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C3_EN_LEN );
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C4_EN                         , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C4_EN );
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C4_EN_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C4_EN_LEN );
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C5_EN                         , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C5_EN );
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C5_EN_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C5_EN_LEN );
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C6_EN                         , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C6_EN );
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C6_EN_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C6_EN_LEN );
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C7_EN                         , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C7_EN );
+REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C7_EN_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C7_EN_LEN );
+
+REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C8_EN                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C8_EN );
+REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C8_EN_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C8_EN_LEN );
+REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C9_EN                         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C9_EN );
+REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C9_EN_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C9_EN_LEN );
+REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C10_EN                        , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C10_EN );
+REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C10_EN_LEN                    , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C10_EN_LEN );
+REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C11_EN                        , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C11_EN );
+REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C11_EN_LEN                    , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_THRD_C11_EN_LEN );
+
+REG64_FLD( PU_INT_TCTXT_INDIR0_INDIR_VLD                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDIR_VLD  );
+REG64_FLD( PU_INT_TCTXT_INDIR0_INDIR_THRDID                        , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDIR_THRDID );
+REG64_FLD( PU_INT_TCTXT_INDIR0_INDIR_THRDID_LEN                    , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDIR_THRDID_LEN );
+
+REG64_FLD( PU_INT_TCTXT_INDIR1_INDIR_VLD                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDIR_VLD  );
+REG64_FLD( PU_INT_TCTXT_INDIR1_INDIR_THRDID                        , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDIR_THRDID );
+REG64_FLD( PU_INT_TCTXT_INDIR1_INDIR_THRDID_LEN                    , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDIR_THRDID_LEN );
+
+REG64_FLD( PU_INT_TCTXT_INDIR2_INDIR_VLD                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDIR_VLD  );
+REG64_FLD( PU_INT_TCTXT_INDIR2_INDIR_THRDID                        , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDIR_THRDID );
+REG64_FLD( PU_INT_TCTXT_INDIR2_INDIR_THRDID_LEN                    , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDIR_THRDID_LEN );
+
+REG64_FLD( PU_INT_TCTXT_INDIR3_INDIR_VLD                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDIR_VLD  );
+REG64_FLD( PU_INT_TCTXT_INDIR3_INDIR_THRDID                        , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDIR_THRDID );
+REG64_FLD( PU_INT_TCTXT_INDIR3_INDIR_THRDID_LEN                    , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDIR_THRDID_LEN );
+
+REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_EN                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_BLOCK_EN );
+REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_VPD_EN                     , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_BLOCK_VPD_EN );
+REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_RCMD_FILTER_EN             , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_BLOCK_RCMD_FILTER_EN );
+REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_3_9                         , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_3_9 );
+REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_3_9_LEN                     , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_3_9_LEN );
+REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET_DELAY                , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_BLOCK_RESET_DELAY );
+REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET_DELAY_LEN            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_BLOCK_RESET_DELAY_LEN );
+
+REG64_FLD( PU_INT_VC_AIB_TIMEOUT_DELAY                             , 58  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DELAY      );
+REG64_FLD( PU_INT_VC_AIB_TIMEOUT_DELAY_LEN                         , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DELAY_LEN  );
+
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_PREVENT_MTP_AT_DEM_IN_PIPE , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PREVENT_MTP_AT_DEM_IN_PIPE );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_33_43            , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_33_43 );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_33_43_LEN        , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_33_43_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_REGS         , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_REGS );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_REGS_LEN     , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_REGS_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IRQ          , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_IRQ );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IRQ_LEN      , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_IRQ_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IVC          , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_IVC );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IVC_LEN      , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_IVC_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_50_51            , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_50_51 );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_50_51_LEN        , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_50_51_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_EOI_RESP , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_EOI_RESP_LEN , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_DMA      , 54  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_SBC_DMA );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_DMA_LEN  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_SBC_DMA_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_TRIG_FWD     , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_TRIG_FWD );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_TRIG_FWD_LEN , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_TRIG_FWD_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQC_EOI_EQP  , 58  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQC_EOI_EQP_LEN , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_LSS_CI_LOAD  , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_LSS_CI_LOAD_LEN , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQD_DMA      , 62  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_EQD_DMA );
+REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQD_DMA_LEN  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ATX_PRIO_FOR_EQD_DMA_LEN );
+
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_REGS                    , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGS       );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_REGS_LEN                , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_REGS_LEN   );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_IRQ                     , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IRQ        );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_IRQ_LEN                 , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IRQ_LEN    );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_IVC                     , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVC        );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_IVC_LEN                 , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVC_LEN    );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_DMA                 , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SBC_DMA    );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_DMA_LEN             , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SBC_DMA_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI                 , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SBC_EOI    );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI_LEN             , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SBC_EOI_LEN );
+
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20_21          , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_20_21 );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20_21_LEN      , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_20_21_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_WR              , 22  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RELAXED_WR );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_DISABLE_PTAG_IN_AIBTAG  , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_PTAG_IN_AIBTAG );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_ESBE            , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQC_EOI_ESBE );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_ESBE_LEN        , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQC_EOI_ESBE_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CISTORE             , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQC_CISTORE );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CISTORE_LEN         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQC_CISTORE_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_EQP             , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQC_EOI_EQP );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_EQP_LEN         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQC_EOI_EQP_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CILOAD              , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQC_CILOAD );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CILOAD_LEN          , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQC_CILOAD_LEN );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_DMA                 , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQC_DMA    );
+REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_DMA_LEN             , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQC_DMA_LEN );
+
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_CRD_REQUEST             , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CRD_REQUEST );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_25             , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_25 );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_READ        , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_CRD_DMA_READ );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_READ_LEN    , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_CRD_DMA_READ_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_AT_MACRO        , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_CRD_AT_MACRO );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_AT_MACRO_LEN    , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_CRD_AT_MACRO_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQC_DOING_CI_LOAD , 30  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQC_DOING_CI_LOAD_LEN , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_32_33          , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_33 );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_32_33_LEN      , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_33_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_READ_CRD_POOL           , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_CRD_POOL );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_READ_CRD_POOL_LEN       , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_READ_CRD_POOL_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_40_47          , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40_47 );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_40_47_LEN      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40_47_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_WRITE       , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_CRD_DMA_WRITE );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_WRITE_LEN   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_CRD_DMA_WRITE_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQ_POST         , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_CRD_EQ_POST );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQ_POST_LEN     , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_CRD_EQ_POST_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_1      , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_CRD_TRIG_FWD_1 );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_1_LEN  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_CRD_TRIG_FWD_1_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_2      , 54  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_CRD_TRIG_FWD_2 );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_2_LEN  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RSD_CRD_TRIG_FWD_2_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_56_58          , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_58 );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_56_58_LEN      , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_58_LEN );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_WRITE_CRD_POOL          , 59  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRITE_CRD_POOL );
+REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_WRITE_CRD_POOL_LEN      , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRITE_CRD_POOL_LEN );
+
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R0                   , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R0     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R0_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R0_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1R                  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1R    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1R_LEN              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1W                  , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1W    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1W_LEN              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1W_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R2                   , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R2     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R2_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R2_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R3                   , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R3     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R3_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R3_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R4                   , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R4_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5R                  , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5R    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5R_LEN              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5W                  , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5W    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5W_LEN              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5W_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R6                   , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R6     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R6_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R6_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7RSP                , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7RSP  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7RSP_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7RSP_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7INT                , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7INT  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7INT_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7INT_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7EQP                , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7EQP  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7EQP_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7EQP_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R8                   , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R8     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R8_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R8_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R9                   , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R9     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R9_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R9_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10R                 , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R10R   );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10R_LEN             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R10R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10W                 , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R10W   );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10W_LEN             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R10W_LEN );
+
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R0                   , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R0     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R0_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R0_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1R                  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1R    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1R_LEN              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1W                  , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1W    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1W_LEN              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1W_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R2                   , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R2     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R2_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R2_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R3                   , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R3     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R3_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R3_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R4                   , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R4_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5R                  , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5R    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5R_LEN              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5W                  , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5W    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5W_LEN              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5W_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R6                   , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R6     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R6_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R6_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7RSP                , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7RSP  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7RSP_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7RSP_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7INT                , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7INT  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7INT_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7INT_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7EQP                , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7EQP  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7EQP_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7EQP_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R8                   , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R8     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R8_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R8_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R9                   , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R9     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R9_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R9_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10R                 , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R10R   );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10R_LEN             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R10R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10W                 , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R10W   );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10W_LEN             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R10W_LEN );
+
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R0                   , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R0     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R0_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R0_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1R                  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1R    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1R_LEN              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1W                  , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1W    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1W_LEN              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R1W_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R2                   , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R2     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R2_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R2_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R3                   , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R3     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R3_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R3_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R4                   , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R4_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R4_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5R                  , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5R    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5R_LEN              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5W                  , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5W    );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5W_LEN              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R5W_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R6                   , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R6     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R6_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R6_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7RSP                , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7RSP  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7RSP_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7RSP_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7INT                , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7INT  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7INT_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7INT_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7EQP                , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7EQP  );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7EQP_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R7EQP_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R8                   , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R8     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R8_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R8_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R9                   , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R9     );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R9_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R9_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10R                 , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R10R   );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10R_LEN             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R10R_LEN );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10W                 , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R10W   );
+REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10W_LEN             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_R10W_LEN );
+
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_VALID                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_VST_TYPE                        , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VST_TYPE   );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_VST_TYPE_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VST_TYPE_LEN );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_BLOCKID                         , 27  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_BLOCKID_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_OFFSET                          , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_OFFSET_LEN                      , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_MASK_BLOCKID                    , 27  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_MASK_BLOCKID_LEN                , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_MASK_OFFSET                     , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_AT_MACRO_KILL_MASK_OFFSET_LEN                 , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_P0_IS_IDLE              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_P0_IS_IDLE );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_P1_IS_IDLE              , 1   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_P1_IS_IDLE );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE         , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_PTAG_IN_USE );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE_LEN     , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_PTAG_IN_USE_LEN );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_EOI     , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_EOI );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_EOI_LEN , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_EOI_LEN );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO      , 24  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_UNLOCK_IN_FIFO );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO_LEN  , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_UNLOCK_IN_FIFO_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_FETCH , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_EQD_FETCH );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_FETCH_LEN , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_EQD_FETCH_LEN );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQP     , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_EQP );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQP_LEN , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_EQP_LEN );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING         , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_LEN     , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_LEN );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD , 24  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_CI_LOAD );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD_LEN , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_CI_LOAD_LEN );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_STORE , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_CI_STORE );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_STORE_LEN , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_CI_STORE_LEN );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_WRITE , 40  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_EQD_WRITE );
+REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_WRITE_LEN , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_EQD_WRITE_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_CACHE_EN_ENABLE                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_INT_VC_EQC_CACHE_EN_ENABLE_LEN                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA0_DATA                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA0_DATA_LEN                , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA1_DATA                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA1_DATA_LEN                , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA2_DATA                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA2_DATA_LEN                , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA3_DATA                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA3_DATA_LEN                , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_CONFLICT                 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CONFLICT   );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_1_7             , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_1_7 );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_1_7_LEN         , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_1_7_LEN );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_FULL                     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FULL       );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_9_27            , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_9_27 );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_9_27_LEN        , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_9_27_LEN );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_BLOCKID                  , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_BLOCKID_LEN              , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_32_39           , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_39 );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_32_39_LEN       , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_39_LEN );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_OFFSET                   , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_OFFSET_LEN               , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_CONFIG_PAGE_OFFSET_CFG                    , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAGE_OFFSET_CFG );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_PAGE_OFFSET_CFG_LEN                , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PAGE_OFFSET_CFG_LEN );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_SYNC_DONE                          , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_DONE  );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_SYNC_DONE_LEN                      , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_DONE_LEN );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_37_45                     , 37  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_37_45 );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_37_45_LEN                 , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_37_45_LEN );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_MAX_PTAG_IN_USE                    , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PTAG_IN_USE );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_MAX_PTAG_IN_USE_LEN                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PTAG_IN_USE_LEN );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_BG_SCAN_RATE                       , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BG_SCAN_RATE );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_BG_SCAN_RATE_LEN                   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BG_SCAN_RATE_LEN );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_56_58                     , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_58 );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_56_58_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_58_LEN );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_MAX_ENTRIES_IN_MODIFIED            , 59  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_ENTRIES_IN_MODIFIED );
+REG64_FLD( PU_INT_VC_EQC_CONFIG_MAX_ENTRIES_IN_MODIFIED_LEN        , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_ENTRIES_IN_MODIFIED_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_DEBUG_RESERVED_0_32                       , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_32 );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_RESERVED_0_32_LEN                   , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_32_LEN );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_ARX_ECC_CORRECTION              , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_ARX_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_TAG_ECC_CORRECTION              , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_TAG_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN          , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_TAG_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_STATE_ECC_CORRECTION            , 42  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_STATE_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_STATE_ECC_CORRECTION_LEN        , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_STATE_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_CTRLBUF_ECC_CORRECTION          , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_CTRLBUF_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_DATA_ECC_CORRECTION             , 45  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_DATA_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_DATA_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR            , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_SINGLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR            , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_ECC_ERR_INJ_ARRAY_SEL               , 51  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_ARRAY_SEL );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN           , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_TRACE_ENABLE                        , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRACE_ENABLE );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_RESERVED_57_58                      , 57  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_57_58 );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_RESERVED_57_58_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_57_58_LEN );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_RESERVED_59                         , 59  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_59 );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_USE_WATCH_TO_READ_CTRL_ARY          , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_USE_WATCH_TO_READ_CTRL_ARY );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_CACHE_CTRL_ARY_SELECT               , 61  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CACHE_CTRL_ARY_SELECT );
+REG64_FLD( PU_INT_VC_EQC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN           , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CACHE_CTRL_ARY_SELECT_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_IPI  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQ_TRIGGER_FROM_IPI );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_IPI_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQ_TRIGGER_FROM_IPI_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_HWD  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQ_TRIGGER_FROM_HWD );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_HWD_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQ_TRIGGER_FROM_HWD_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_1ESC , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_1ESC_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_2ESC , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_2ESC_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_REDIS , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_REDIS_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI         , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_NON_SPEC_EOI );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_LEN     , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_NON_SPEC_EOI_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESCALATE       , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_ESCALATE );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESCALATE_LEN   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_ESCALATE_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIG_CACHE_HIT    , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQ_TRIG_CACHE_HIT );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIG_CACHE_HIT_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQ_TRIG_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EOI_CACHE_HIT        , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EOI_CACHE_HIT );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EOI_CACHE_HIT_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EOI_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESC_CACHE_HIT  , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_ESC_CACHE_HIT );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESC_CACHE_HIT_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_ESC_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU        , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_LRU );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_LRU_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_FIRST_USABLE );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_FIRST_USABLE_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_RETRY                , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RETRY  );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_RETRY_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RETRY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES     , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TOO_MANY_ENTRIES );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TOO_MANY_ENTRIES_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_RESERVED_56_63           , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_63 );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_RESERVED_56_63_LEN       , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_63_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQD_FETCH            , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQD_FETCH );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQD_FETCH_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQD_FETCH_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQP                  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQP    );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQP_LEN              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQP_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_WAKEUP               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_WAKEUP );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_WAKEUP_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_WAKEUP_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS                   , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LS     );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LS_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_VP                   , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VP     );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_VP_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VP_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_GROUP                , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_GROUP  );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_GROUP_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_GROUP_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST            , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_BROADCAST );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_BROADCAST_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQ_FWD               , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQ_FWD );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQ_FWD_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQ_FWD_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_ESCALATE             , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_ESCALATE );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_ESCALATE_LEN         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_ESCALATE_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_VPC_UPD        , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_VPC_UPD );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_VPC_UPD_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_VPC_UPD_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_VPC_UPD       , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_REMOTE_VPC_UPD );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_VPC_UPD_LEN   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_REMOTE_VPC_UPD_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_SBC_UPD        , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_SBC_UPD );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_SBC_UPD_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_SBC_UPD_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_SBC_UPD       , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_REMOTE_SBC_UPD );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_SBC_UPD_LEN   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_REMOTE_SBC_UPD_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQD_FETCH_REPLAY     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQD_FETCH_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQD_FETCH_REPLAY_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQD_FETCH_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQP_REPLAY           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQP_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQP_REPLAY_LEN       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQP_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REPLAY               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REPLAY_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_CI_STORE_REPLAY      , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_CI_STORE_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_CI_STORE_REPLAY_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_CI_STORE_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_ESC_REPLAY     , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_ESC_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_ESC_REPLAY_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_ESC_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REMOTE_CI_LOAD_REPLAY , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REMOTE_CI_LOAD_REPLAY_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_VPC_REPLAY     , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_VPC_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_VPC_REPLAY_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_VPC_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_SBC_REPLAY     , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_SBC_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_SBC_REPLAY_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_LOCAL_SBC_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY      , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EOI_RESP_REPLAY );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EOI_RESP_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_NEW_CMD_STALLED      , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_NEW_CMD_STALLED );
+REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_NEW_CMD_STALLED_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_NEW_CMD_STALLED_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_BLOCKID                        , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_BLOCKID_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_RESERVED_32_39                 , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_39 );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_RESERVED_32_39_LEN             , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_39_LEN );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_OFFSET                         , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_OFFSET_LEN                     , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_VALID                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_WANT_CACHE_DISABLE             , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WANT_CACHE_DISABLE );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_WANT_INVALIDATE                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WANT_INVALIDATE );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_BLOCKID                        , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_BLOCKID_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_RESERVED_32_39                 , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_39 );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_RESERVED_32_39_LEN             , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_39_LEN );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_OFFSET                         , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_OFFSET_LEN                     , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_EQD_BLOCK_MODE_MODE                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE       );
+REG64_FLD( PU_INT_VC_EQD_BLOCK_MODE_MODE_LEN                       , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_LEN   );
+
+REG64_FLD( PU_INT_VC_ERR_CFG_G0R0_ERROR_CONFIG                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG );
+REG64_FLD( PU_INT_VC_ERR_CFG_G0R0_ERROR_CONFIG_LEN                 , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG_LEN );
+
+REG64_FLD( PU_INT_VC_ERR_CFG_G0R1_ERROR_CONFIG                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG );
+REG64_FLD( PU_INT_VC_ERR_CFG_G0R1_ERROR_CONFIG_LEN                 , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG_LEN );
+
+REG64_FLD( PU_INT_VC_ERR_CFG_G1R0_ERROR_CONFIG                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG );
+REG64_FLD( PU_INT_VC_ERR_CFG_G1R0_ERROR_CONFIG_LEN                 , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG_LEN );
+
+REG64_FLD( PU_INT_VC_ERR_CFG_G1R1_ERROR_CONFIG                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG );
+REG64_FLD( PU_INT_VC_ERR_CFG_G1R1_ERROR_CONFIG_LEN                 , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_CONFIG_LEN );
+
+REG64_FLD( PU_INT_VC_FATAL_ERR_G0_ERROR                            , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_FATAL_ERR_G0_ERROR_LEN                        , 55  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_FATAL_ERR_G1_ERROR                            , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_FATAL_ERR_G1_ERROR_LEN                        , 43  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_GLOBAL_CONFIG_INDIRECT_MODE                   , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_INDIRECT_MODE );
+REG64_FLD( PU_INT_VC_GLOBAL_CONFIG_RESERVED_33_63                  , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_33_63 );
+REG64_FLD( PU_INT_VC_GLOBAL_CONFIG_RESERVED_33_63_LEN              , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_33_63_LEN );
+
+REG64_FLD( PU_INT_VC_INFO_ERR_G0_ERROR                             , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_INFO_ERR_G0_ERROR_LEN                         , 55  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_INFO_ERR_G1_ERROR                             , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_INFO_ERR_G1_ERROR_LEN                         , 43  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_20                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_20 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_20_LEN                  , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_20_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_PREFETCH_DISTANCE                , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISTANCE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_PREFETCH_DISTANCE_LEN            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISTANCE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_CQ                    , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_CQ );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_CQ_LEN                , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_CQ_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_32_34                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_34 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_32_34_LEN               , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_34_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_PC                    , 35  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_PC );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_PC_LEN                , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_PC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_40_41                   , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_40_41_LEN               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_PREFETCH_DISABLE                 , 42  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_QUEUE_DISABLE                    , 43  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUEUE_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_IVC_INTF_DISABLE                 , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IVC_INTF_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_ENABLE_MEMORY_BACKING            , 45  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_MEMORY_BACKING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MEM_SIZE                         , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MEM_SIZE   );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MEM_SIZE_LEN                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MEM_SIZE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_52                      , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_52 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_NB_WRITE_SLOT                    , 53  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_WRITE_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_NB_WRITE_SLOT_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_WRITE_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_56                      , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_NB_CLEAN_SLOT                    , 57  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_CLEAN_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_NB_CLEAN_SLOT_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_CLEAN_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_FULL_WRITEBACK_ENABLE            , 60  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FULL_WRITEBACK_ENABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_QUEUE_NOT_EMPTY                  , 61  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUEUE_NOT_EMPTY );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_CREDIT_UPDATE_PENDING            , 62  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CREDIT_UPDATE_PENDING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_FIFO_FULL                        , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_FULL  );
+
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_0_20                    , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_0_20 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_0_20_LEN                , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_0_20_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_PREFETCH_DISTANCE                , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISTANCE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_PREFETCH_DISTANCE_LEN            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISTANCE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_CQ                    , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_CQ );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_CQ_LEN                , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_CQ_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_32_34                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_34 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_32_34_LEN               , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_34_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_PC                    , 35  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_PC );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_PC_LEN                , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_PC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_40_41                   , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_40_41_LEN               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_PREFETCH_DISABLE                 , 42  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_QUEUE_DISABLE                    , 43  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUEUE_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_IVC_INTF_DISABLE                 , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IVC_INTF_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_ENABLE_MEMORY_BACKING            , 45  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_MEMORY_BACKING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MEM_SIZE                         , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MEM_SIZE   );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MEM_SIZE_LEN                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MEM_SIZE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_52                      , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_52 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_NB_WRITE_SLOT                    , 53  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_WRITE_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_NB_WRITE_SLOT_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_WRITE_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_56                      , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_NB_CLEAN_SLOT                    , 57  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_CLEAN_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_NB_CLEAN_SLOT_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_CLEAN_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_FULL_WRITEBACK_ENABLE            , 60  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FULL_WRITEBACK_ENABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_QUEUE_NOT_EMPTY                  , 61  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUEUE_NOT_EMPTY );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_CREDIT_UPDATE_PENDING            , 62  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CREDIT_UPDATE_PENDING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_FIFO_FULL                        , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_FULL  );
+
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_0_20                    , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_0_20 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_0_20_LEN                , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_0_20_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_PREFETCH_DISTANCE                , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISTANCE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_PREFETCH_DISTANCE_LEN            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISTANCE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_CQ                    , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_CQ );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_CQ_LEN                , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_CQ_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_32_34                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_34 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_32_34_LEN               , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_34_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_PC                    , 35  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_PC );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_PC_LEN                , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_PC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_40_41                   , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_40_41_LEN               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_PREFETCH_DISABLE                 , 42  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_QUEUE_DISABLE                    , 43  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUEUE_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_IVC_INTF_DISABLE                 , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IVC_INTF_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_ENABLE_MEMORY_BACKING            , 45  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_MEMORY_BACKING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MEM_SIZE                         , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MEM_SIZE   );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MEM_SIZE_LEN                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MEM_SIZE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_52                      , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_52 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_NB_WRITE_SLOT                    , 53  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_WRITE_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_NB_WRITE_SLOT_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_WRITE_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_56                      , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_NB_CLEAN_SLOT                    , 57  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_CLEAN_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_NB_CLEAN_SLOT_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_CLEAN_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_FULL_WRITEBACK_ENABLE            , 60  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FULL_WRITEBACK_ENABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_QUEUE_NOT_EMPTY                  , 61  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUEUE_NOT_EMPTY );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_CREDIT_UPDATE_PENDING            , 62  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CREDIT_UPDATE_PENDING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_FIFO_FULL                        , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_FULL  );
+
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_0_20                    , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_0_20 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_0_20_LEN                , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_0_20_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_PREFETCH_DISTANCE                , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISTANCE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_PREFETCH_DISTANCE_LEN            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISTANCE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_CQ                    , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_CQ );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_CQ_LEN                , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_CQ_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_32_34                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_34 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_32_34_LEN               , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_34_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_PC                    , 35  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_PC );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_PC_LEN                , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_PC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_40_41                   , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_40_41_LEN               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_PREFETCH_DISABLE                 , 42  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_QUEUE_DISABLE                    , 43  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUEUE_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_IVC_INTF_DISABLE                 , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IVC_INTF_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_ENABLE_MEMORY_BACKING            , 45  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_MEMORY_BACKING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MEM_SIZE                         , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MEM_SIZE   );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MEM_SIZE_LEN                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MEM_SIZE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_52                      , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_52 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_NB_WRITE_SLOT                    , 53  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_WRITE_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_NB_WRITE_SLOT_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_WRITE_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_56                      , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_NB_CLEAN_SLOT                    , 57  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_CLEAN_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_NB_CLEAN_SLOT_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_CLEAN_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_FULL_WRITEBACK_ENABLE            , 60  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FULL_WRITEBACK_ENABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_QUEUE_NOT_EMPTY                  , 61  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUEUE_NOT_EMPTY );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_CREDIT_UPDATE_PENDING            , 62  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CREDIT_UPDATE_PENDING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_FIFO_FULL                        , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_FULL  );
+
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_0_20                    , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_0_20 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_0_20_LEN                , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_0_20_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_PREFETCH_DISTANCE                , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISTANCE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_PREFETCH_DISTANCE_LEN            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISTANCE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_CQ                    , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_CQ );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_CQ_LEN                , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_CQ_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_32_34                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_34 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_32_34_LEN               , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_34_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_PC                    , 35  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_PC );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_PC_LEN                , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_PC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_40_41                   , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_40_41_LEN               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_PREFETCH_DISABLE                 , 42  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_QUEUE_DISABLE                    , 43  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUEUE_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_IVC_INTF_DISABLE                 , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IVC_INTF_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_ENABLE_MEMORY_BACKING            , 45  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_MEMORY_BACKING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MEM_SIZE                         , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MEM_SIZE   );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MEM_SIZE_LEN                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MEM_SIZE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_52                      , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_52 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_NB_WRITE_SLOT                    , 53  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_WRITE_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_NB_WRITE_SLOT_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_WRITE_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_56                      , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_NB_CLEAN_SLOT                    , 57  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_CLEAN_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_NB_CLEAN_SLOT_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_CLEAN_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_FULL_WRITEBACK_ENABLE            , 60  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FULL_WRITEBACK_ENABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_QUEUE_NOT_EMPTY                  , 61  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUEUE_NOT_EMPTY );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_CREDIT_UPDATE_PENDING            , 62  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CREDIT_UPDATE_PENDING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_FIFO_FULL                        , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_FULL  );
+
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_0_20                    , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_0_20 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_0_20_LEN                , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_0_20_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_PREFETCH_DISTANCE                , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISTANCE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_PREFETCH_DISTANCE_LEN            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISTANCE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_CQ                    , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_CQ );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_CQ_LEN                , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_CQ_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_32_34                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_34 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_32_34_LEN               , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_32_34_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_PC                    , 35  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_PC );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_PC_LEN                , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAX_CRD_TO_PC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_40_41                   , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_40_41_LEN               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_PREFETCH_DISABLE                 , 42  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PREFETCH_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_QUEUE_DISABLE                    , 43  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUEUE_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_IVC_INTF_DISABLE                 , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IVC_INTF_DISABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_ENABLE_MEMORY_BACKING            , 45  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_MEMORY_BACKING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MEM_SIZE                         , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MEM_SIZE   );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MEM_SIZE_LEN                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MEM_SIZE_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_52                      , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_52 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_NB_WRITE_SLOT                    , 53  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_WRITE_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_NB_WRITE_SLOT_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_WRITE_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_56                      , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_NB_CLEAN_SLOT                    , 57  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_CLEAN_SLOT );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_NB_CLEAN_SLOT_LEN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NB_CLEAN_SLOT_LEN );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_FULL_WRITEBACK_ENABLE            , 60  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FULL_WRITEBACK_ENABLE );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_QUEUE_NOT_EMPTY                  , 61  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUEUE_NOT_EMPTY );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_CREDIT_UPDATE_PENDING            , 62  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CREDIT_UPDATE_PENDING );
+REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_FIFO_FULL                        , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_FULL  );
+
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FROM_AIB        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FROM_AIB );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FROM_AIB_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FROM_AIB_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_DROPPED         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_DROPPED );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_DROPPED_LEN     , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_DROPPED_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FWD_TO_EQC      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FWD_TO_EQC );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FWD_TO_EQC_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_WR               , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_WR );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_WR_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_WR_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_RD               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_RD );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_RD_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_RD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_FIFO_FULL            , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_FIFO_FULL );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_FIFO_FULL_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_FIFO_FULL_LEN );
+
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FROM_AIB        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FROM_AIB );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FROM_AIB_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FROM_AIB_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_DROPPED         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_DROPPED );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_DROPPED_LEN     , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_DROPPED_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FWD_TO_EQC      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FWD_TO_EQC );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FWD_TO_EQC_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_WR               , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_WR );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_WR_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_WR_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_RD               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_RD );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_RD_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_RD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_FIFO_FULL            , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_FIFO_FULL );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_FIFO_FULL_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_FIFO_FULL_LEN );
+
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FROM_AIB        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FROM_AIB );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FROM_AIB_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FROM_AIB_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_DROPPED         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_DROPPED );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_DROPPED_LEN     , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_DROPPED_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FWD_TO_EQC      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FWD_TO_EQC );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FWD_TO_EQC_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_WR               , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_WR );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_WR_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_WR_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_RD               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_RD );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_RD_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_RD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_FIFO_FULL            , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_FIFO_FULL );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_FIFO_FULL_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_FIFO_FULL_LEN );
+
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FROM_AIB        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FROM_AIB );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FROM_AIB_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FROM_AIB_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_DROPPED         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_DROPPED );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_DROPPED_LEN     , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_DROPPED_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FWD_TO_EQC      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FWD_TO_EQC );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FWD_TO_EQC_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_WR               , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_WR );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_WR_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_WR_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_RD               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_RD );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_RD_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_RD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_FIFO_FULL            , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_FIFO_FULL );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_FIFO_FULL_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_FIFO_FULL_LEN );
+
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FROM_AIB        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FROM_AIB );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FROM_AIB_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FROM_AIB_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_DROPPED         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_DROPPED );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_DROPPED_LEN     , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_DROPPED_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FWD_TO_EQC      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FWD_TO_EQC );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FWD_TO_EQC_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_WR               , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_WR );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_WR_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_WR_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_RD               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_RD );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_RD_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_RD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_FIFO_FULL            , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_FIFO_FULL );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_FIFO_FULL_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_FIFO_FULL_LEN );
+
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FROM_AIB        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FROM_AIB );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FROM_AIB_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FROM_AIB_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_DROPPED         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_DROPPED );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_DROPPED_LEN     , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_DROPPED_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FWD_TO_EQC      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FWD_TO_EQC );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FWD_TO_EQC_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_WR               , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_WR );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_WR_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_WR_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_RD               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_RD );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_RD_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DMA_RD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_FIFO_FULL            , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_FIFO_FULL );
+REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_FIFO_FULL_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_FIFO_FULL_LEN );
+
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_PRIORITY               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IPI_PRIORITY );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_PRIORITY_LEN           , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IPI_PRIORITY_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_RSD                    , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IPI_RSD    );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_RSD_LEN                , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IPI_RSD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_PRIORITY               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_PRIORITY );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_PRIORITY_LEN           , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_PRIORITY_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_RSD                    , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_RSD    );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_RSD_LEN                , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_RSD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_PRIORITY              , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ESC1_PRIORITY );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_PRIORITY_LEN          , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ESC1_PRIORITY_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_RSD                   , 19  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ESC1_RSD   );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_RSD_LEN               , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ESC1_RSD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_PRIORITY              , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ESC2_PRIORITY );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_PRIORITY_LEN          , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ESC2_PRIORITY_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_RSD                   , 27  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ESC2_RSD   );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_RSD_LEN               , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ESC2_RSD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_PRIORITY             , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_REDIS_PRIORITY );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_PRIORITY_LEN         , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_REDIS_PRIORITY_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_RSD                  , 35  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_REDIS_RSD  );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_RSD_LEN              , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_REDIS_RSD_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_RESERVED_40_42             , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40_42 );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_RESERVED_40_42_LEN         , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40_42_LEN );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_POOL                       , 43  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_POOL       );
+REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_POOL_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_POOL_LEN   );
+
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_P0_IS_IDLE                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_P0_IS_IDLE );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_P1_IS_IDLE                , 1   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_P1_IS_IDLE );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_PTAG_IN_USE           , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_PTAG_IN_USE );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_PTAG_IN_USE_LEN       , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_PTAG_IN_USE_LEN );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO        , 24  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_UNLOCK_IN_FIFO );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO_LEN    , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_UNLOCK_IN_FIFO_LEN );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_IVE_FETCH , 48  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_IVE_FETCH );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_IVE_FETCH_LEN , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_IVE_FETCH_LEN );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_SBC_LOOKUP , 56  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP );
+REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_SBC_LOOKUP_LEN , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_CACHE_EN_ENABLE                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_INT_VC_IVC_CACHE_EN_ENABLE_LEN                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_CACHE_WATCH_ADDR_SET_INDEX                , 54  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_INDEX  );
+REG64_FLD( PU_INT_VC_IVC_CACHE_WATCH_ADDR_SET_INDEX_LEN            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_INDEX_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_CACHE_WATCH_DATA_DATA                     , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_INT_VC_IVC_CACHE_WATCH_DATA_DATA_LEN                 , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_32                         , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32 );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_MAX_PTAG_IN_USE                     , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PTAG_IN_USE );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_MAX_PTAG_IN_USE_LEN                 , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PTAG_IN_USE_LEN );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_TAG_ECC_CORRECTION              , 38  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_TAG_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN          , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_TAG_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_STATE_ECC_CORRECTION            , 42  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_STATE_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_43_44                      , 43  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_43_44 );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_43_44_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_43_44_LEN );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_DATA_ECC_CORRECTION             , 45  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_DATA_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_DATA_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_47_48                      , 47  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_47_48 );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_47_48_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_47_48_LEN );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR            , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_SINGLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR            , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_ECC_ERR_INJ_ARRAY_SEL               , 51  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_ARRAY_SEL );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN           , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_TRACE_ENABLE                        , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRACE_ENABLE );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_57_58                      , 57  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_57_58 );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_57_58_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_57_58_LEN );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_FAST_SB_LOOKUP_DISABLE              , 59  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FAST_SB_LOOKUP_DISABLE );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_CACHE_CTRL_ARY_SELECT               , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CACHE_CTRL_ARY_SELECT );
+REG64_FLD( PU_INT_VC_IVC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CACHE_CTRL_ARY_SELECT_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_0                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_0                              , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_0      );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_0_LEN                          , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_0_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_8                         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD                                , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD        );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_LEN                            , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_LEN    );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_16                        , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_2                              , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_2      );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_2_LEN                          , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_2_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_24                        , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_3                              , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_3      );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_3_LEN                          , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_3_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_32                        , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_4                              , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_4      );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_4_LEN                          , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_4_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_40                        , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_5                              , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_5      );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_5_LEN                          , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_5_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_48                        , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_6                              , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_6      );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_6_LEN                          , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_6_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_56                        , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_7                              , 57  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_7      );
+REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_7_LEN                          , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_7_LEN  );
+
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_0                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_8                              , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_8      );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_8_LEN                          , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_8_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_8                         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_9                              , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_9      );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_9_LEN                          , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_9_LEN  );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_16                        , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_10                             , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_10     );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_10_LEN                         , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_10_LEN );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_24                        , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_11                             , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_11     );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_11_LEN                         , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_11_LEN );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_32                        , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_12                             , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_12     );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_12_LEN                         , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_12_LEN );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_40                        , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_13                             , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_13     );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_13_LEN                         , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_13_LEN );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_48                        , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_14                             , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_14     );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_14_LEN                         , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_14_LEN );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_56                        , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56 );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_15                             , 57  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_15     );
+REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_15_LEN                         , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HWD_15_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_HASH_3_RESERVED_0                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0 );
+REG64_FLD( PU_INT_VC_IVC_HASH_3_IPI                                , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IPI        );
+REG64_FLD( PU_INT_VC_IVC_HASH_3_IPI_LEN                            , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IPI_LEN    );
+
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IPI_DOES_PRF_IVE );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IPI_DOES_PRF_IVE_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE_SBC , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE_SBC_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_HWD_DOES_PRF_IVE     , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_HWD_DOES_PRF_IVE );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_HWD_DOES_PRF_IVE_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_HWD_DOES_PRF_IVE_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE     , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IPI_DOES_DEM_IVE );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IPI_DOES_DEM_IVE_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE_SBC , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE_SBC_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CND_HWD_DOES_DEM_IVE     , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CND_HWD_DOES_DEM_IVE );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CND_HWD_DOES_DEM_IVE_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CND_HWD_DOES_DEM_IVE_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT        , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_PRF_CACHE_HIT );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_PRF_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_DEM_CACHE_HIT        , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DEM_CACHE_HIT );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_DEM_CACHE_HIT_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_DEM_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU        , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_LRU );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_LRU_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_1ST_USABLE );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_1ST_USABLE_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_IVE_FETCH            , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IVE_FETCH );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_IVE_FETCH_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IVE_FETCH_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_SBC_LOOKUP           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_SBC_LOOKUP );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_SBC_LOOKUP_LEN       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_SBC_LOOKUP_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_IVE_FETCH_REPLAY     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IVE_FETCH_REPLAY );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_IVE_FETCH_REPLAY_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IVE_FETCH_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_SBC_LOOKUP_REPLAY    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_SBC_LOOKUP_REPLAY );
+REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_SBC_LOOKUP_REPLAY_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_SBC_LOOKUP_REPLAY_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_BLOCKID                        , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_BLOCKID_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_RESERVED_32_35                 , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_35 );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_RESERVED_32_35_LEN             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_35_LEN );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_OFFSET                         , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_OFFSET_LEN                     , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_VALID                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_WANT_CACHE_DISABLE             , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WANT_CACHE_DISABLE );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_BLOCKID                        , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_BLOCKID_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_RESERVED_32_35                 , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_35 );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_RESERVED_32_35_LEN             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_35_LEN );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_OFFSET                         , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_OFFSET_LEN                     , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_IVE_ISB_BLOCK_MODE_MODE                       , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE       );
+REG64_FLD( PU_INT_VC_IVE_ISB_BLOCK_MODE_MODE_LEN                   , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_LEN   );
+
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_DIS_AIB_IN_ECC_CORRECTION          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_AIB_IN_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_DIS_IRQ_ECC_CORRECTION             , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_IRQ_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_DIS_AT_SRAM_ECC_CORRECTION         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_AT_SRAM_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_DIS_BAR_SRAM_ECC_CORRECTION        , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_BAR_SRAM_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_DIS_TAG_SRAM_ECC_CORRECTION        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_TAG_SRAM_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_IRQ_TRACE_ENABLE                   , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IRQ_TRACE_ENABLE );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_FORCE_SINGLE_BIT_ECC_ERR           , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_SINGLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR           , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_RESERVED_8_9                       , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_9 );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_RESERVED_8_9_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_9_LEN );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_ECC_ERR_INJ_SELECTION              , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_SELECTION );
+REG64_FLD( PU_INT_VC_LBS6_DEBUG_ECC_ERR_INJ_SELECTION_LEN          , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_SELECTION_LEN );
+
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_0_17    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_17 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_0_17_LEN , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_17_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_STORE         , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CI_STORE   );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_STORE_LEN     , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CI_STORE_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_24_25   , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_25 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_24_25_LEN , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_25_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_REQUEST          , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_REQUEST    );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_REQUEST_LEN      , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_REQUEST_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_32_33   , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_33 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_32_33_LEN , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_33_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQ_POST          , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQ_POST    );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQ_POST_LEN      , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQ_POST_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_40_41   , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40_41 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_40_41_LEN , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40_41_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_LOAD          , 42  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CI_LOAD    );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_LOAD_LEN      , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CI_LOAD_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_48_49   , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48_49 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_48_49_LEN , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48_49_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_READ     , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQD_DMA_READ );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_READ_LEN , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQD_DMA_READ_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_56_57   , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_57 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_56_57_LEN , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_57_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_WRITE    , 58  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQD_DMA_WRITE );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_WRITE_LEN , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EQD_DMA_WRITE_LEN );
+
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_0_17         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_17 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_0_17_LEN     , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_17_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_READ              , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_READ   );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_READ_LEN          , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_READ_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_24_25        , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_25 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_24_25_LEN    , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_24_25_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_WRITE             , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_WRITE  );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_WRITE_LEN         , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_WRITE_LEN );
+
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_48_50        , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48_50 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_48_50_LEN    , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48_50_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_SBC_LOOKUP            , 51  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SBC_LOOKUP );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_SBC_LOOKUP_LEN        , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SBC_LOOKUP_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_56_58        , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_58 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_56_58_LEN    , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_58_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_DMA_READ              , 59  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_READ   );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_DMA_READ_LEN          , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_READ_LEN );
+
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_48_50        , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48_50 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_48_50_LEN    , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48_50_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_READ              , 51  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_READ   );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_READ_LEN          , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_READ_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_56_58        , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_58 );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_56_58_LEN    , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_58_LEN );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_WRITE             , 59  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_WRITE  );
+REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_WRITE_LEN         , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_WRITE_LEN );
+
+REG64_FLD( PU_INT_VC_RECOV_ERR_G0_ERROR                            , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_RECOV_ERR_G0_ERROR_LEN                        , 55  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_RECOV_ERR_G1_ERROR                            , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_RECOV_ERR_G1_ERROR_LEN                        , 43  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_P0_IS_IDLE                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_P0_IS_IDLE );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_P1_IS_IDLE                , 1   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_P1_IS_IDLE );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_PTAG_IN_USE           , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_PTAG_IN_USE );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_PTAG_IN_USE_LEN       , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_PTAG_IN_USE_LEN );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_SOFT_EOI  , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_SOFT_EOI );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_SOFT_EOI_LEN , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_SOFT_EOI_LEN );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO        , 24  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_UNLOCK_IN_FIFO );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO_LEN    , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_UNLOCK_IN_FIFO_LEN );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_FETCH , 48  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_ISB_FETCH );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_FETCH_LEN , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_ISB_FETCH_LEN );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_WRITE , 56  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_ISB_WRITE );
+REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_WRITE_LEN , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_OUTSTANDING_ISB_WRITE_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_CACHE_EN_ENABLE                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_INT_VC_SBC_CACHE_EN_ENABLE_LEN                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_CACHE_WATCH_ADDR_SET_INDEX                , 54  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_INDEX  );
+REG64_FLD( PU_INT_VC_SBC_CACHE_WATCH_ADDR_SET_INDEX_LEN            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_INDEX_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_CACHE_WATCH_DATA_DATA                     , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_INT_VC_SBC_CACHE_WATCH_DATA_DATA_LEN                 , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_INT_VC_SBC_CONFIG_RESERVED_44_46                     , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_44_46 );
+REG64_FLD( PU_INT_VC_SBC_CONFIG_RESERVED_44_46_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_44_46_LEN );
+REG64_FLD( PU_INT_VC_SBC_CONFIG_MAX_PTAG_IN_USE                    , 47  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PTAG_IN_USE );
+REG64_FLD( PU_INT_VC_SBC_CONFIG_MAX_PTAG_IN_USE_LEN                , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PTAG_IN_USE_LEN );
+REG64_FLD( PU_INT_VC_SBC_CONFIG_BG_SCAN_RATE                       , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BG_SCAN_RATE );
+REG64_FLD( PU_INT_VC_SBC_CONFIG_BG_SCAN_RATE_LEN                   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BG_SCAN_RATE_LEN );
+REG64_FLD( PU_INT_VC_SBC_CONFIG_RESERVED_56_59                     , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_59 );
+REG64_FLD( PU_INT_VC_SBC_CONFIG_RESERVED_56_59_LEN                 , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56_59_LEN );
+REG64_FLD( PU_INT_VC_SBC_CONFIG_MAX_ENTRIES_IN_MODIFIED            , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_ENTRIES_IN_MODIFIED );
+REG64_FLD( PU_INT_VC_SBC_CONFIG_MAX_ENTRIES_IN_MODIFIED_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_ENTRIES_IN_MODIFIED_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_32_33                      , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_33 );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_32_33_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_33_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_DIS_TAG_ECC_CORRECTION              , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_TAG_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN          , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_TAG_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_38_41                      , 38  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_41 );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_38_41_LEN                  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_38_41_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_DIS_STATE_ECC_CORRECTION            , 42  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_STATE_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_43_44                      , 43  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_43_44 );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_43_44_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_43_44_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_DIS_DATA_ECC_CORRECTION             , 45  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_DATA_ECC_CORRECTION );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIS_DATA_ECC_CORRECTION_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_47_48                      , 47  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_47_48 );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_47_48_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_47_48_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR            , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_SINGLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR            , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_ECC_ERR_INJ_ARRAY_SEL               , 51  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_ARRAY_SEL );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN           , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_TRACE_ENABLE                        , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRACE_ENABLE );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_57_59                      , 57  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_57_59 );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_57_59_LEN                  , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_57_59_LEN );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_CACHE_CTRL_ARY_SELECT               , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CACHE_CTRL_ARY_SELECT );
+REG64_FLD( PU_INT_VC_SBC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CACHE_CTRL_ARY_SELECT_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_PRF              , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IVC_PRF );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_PRF_LEN          , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IVC_PRF_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_DEMAND           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IVC_DEMAND );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_DEMAND_LEN       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IVC_DEMAND_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_EQC_COMMAND          , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQC_COMMAND );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_EQC_COMMAND_LEN      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EQC_COMMAND_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_OWNED   , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_NON_SPEC_EOI_OWNED );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_OWNED_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_NON_SPEC_EOI_OWNED_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_NOTOWNED , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_NOTOWNED_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI             , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_SPEC_EOI );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI_LEN         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_SPEC_EOI_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI_CACHE_HIT   , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_SPEC_EOI_CACHE_HIT );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI_CACHE_HIT_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_SPEC_EOI_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT        , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_PRF_CACHE_HIT );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_PRF_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_OTHER_CACHE_HIT      , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_OTHER_CACHE_HIT );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_OTHER_CACHE_HIT_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_OTHER_CACHE_HIT_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU        , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_LRU );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_LRU_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_1ST_USABLE );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_VICTIM_IS_1ST_USABLE_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_RETRY                , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RETRY  );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_RETRY_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_RETRY_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES     , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TOO_MANY_ENTRIES );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_TOO_MANY_ENTRIES_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_FETCH            , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_ISB_FETCH );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_FETCH_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_ISB_FETCH_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_IVVC_RESP            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IVVC_RESP );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_IVVC_RESP_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IVVC_RESP_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE            , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_ISB_WRITE );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_ISB_WRITE_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_12_15           , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_12_15_LEN       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_12_15_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_ISB_FETCH_REPLAY     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_ISB_FETCH_REPLAY );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_ISB_FETCH_REPLAY_LEN , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_ISB_FETCH_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_IVC_RESP_REPLAY      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IVC_RESP_REPLAY );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_IVC_RESP_REPLAY_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_IVC_RESP_REPLAY_LEN );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EOI_RESP_REPLAY );
+REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY_LEN  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CNT_EOI_RESP_REPLAY_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_BLOCKID                        , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_BLOCKID_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_RESERVED_32_40                 , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_40 );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_RESERVED_32_40_LEN             , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_40_LEN );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_OFFSET                         , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_OFFSET_LEN                     , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_VALID                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_WANT_CACHE_DISABLE             , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WANT_CACHE_DISABLE );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_WANT_INVALIDATE                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WANT_INVALIDATE );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_BLOCKID                        , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_BLOCKID_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_RESERVED_32_40                 , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_40 );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_RESERVED_32_40_LEN             , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_40_LEN );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_OFFSET                         , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_OFFSET_LEN                     , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_SOFTWR_ADDR_BLOCKID                       , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID    );
+REG64_FLD( PU_INT_VC_SBC_SOFTWR_ADDR_BLOCKID_LEN                   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCKID_LEN );
+REG64_FLD( PU_INT_VC_SBC_SOFTWR_ADDR_RESERVED_32_35                , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_35 );
+REG64_FLD( PU_INT_VC_SBC_SOFTWR_ADDR_RESERVED_32_35_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32_35_LEN );
+REG64_FLD( PU_INT_VC_SBC_SOFTWR_ADDR_OFFSET                        , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET     );
+REG64_FLD( PU_INT_VC_SBC_SOFTWR_ADDR_OFFSET_LEN                    , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OFFSET_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_SOFTWR_DATA_PQ_STATE                      , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PQ_STATE   );
+REG64_FLD( PU_INT_VC_SBC_SOFTWR_DATA_PQ_STATE_LEN                  , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PQ_STATE_LEN );
+
+REG64_FLD( PU_INT_VC_SBC_SOFTWR_MASK_MSK                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MSK        );
+REG64_FLD( PU_INT_VC_SBC_SOFTWR_MASK_MSK_LEN                       , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MSK_LEN    );
+
+REG64_FLD( PU_INT_VC_VPS_BLOCK_MODE_MODE                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE       );
+REG64_FLD( PU_INT_VC_VPS_BLOCK_MODE_MODE_LEN                       , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_LEN   );
+
+REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_AUTO_INCREMENT                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_AUTO_INCREMENT );
+REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_SELECT                         , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT     );
+REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_SELECT_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_LEN );
+REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_RESERVED_16_26                 , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16_26 );
+REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_RESERVED_16_26_LEN             , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16_26_LEN );
+REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_ADDRESS                        , 27  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_ADDRESS_LEN                    , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_INT_VC_WOF_ERR_G0_ERROR                              , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_WOF_ERR_G0_ERROR_LEN                          , 55  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_WOF_ERR_G0_DETAIL_ERROR                       , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_WOF_ERR_G0_DETAIL_ERROR_LEN                   , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_WOF_ERR_G1_ERROR                              , 0   , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_WOF_ERR_G1_ERROR_LEN                          , 43  , SH_UNT          , SH_ACS_SCOM_CLRPART,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_INT_VC_WOF_ERR_G1_DETAIL_ERROR                       , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_INT_VC_WOF_ERR_G1_DETAIL_ERROR_LEN                   , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_LEN  );
+
+REG64_FLD( PU_NPU_SM1_IODA_ADDR_AUTO_INCREMENT                     , 0   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_AUTO_INCREMENT );
+REG64_FLD( PU_NPU_SM1_IODA_ADDR_TABLE_SELECT                       , 11  , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_TABLE_SELECT );
+REG64_FLD( PU_NPU_SM1_IODA_ADDR_TABLE_SELECT_LEN                   , 5   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_TABLE_SELECT_LEN );
+REG64_FLD( PU_NPU_SM1_IODA_ADDR_TABLE_ADDRESS                      , 54  , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_TABLE_ADDRESS );
+REG64_FLD( PU_NPU_SM1_IODA_ADDR_TABLE_ADDRESS_LEN                  , 10  , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_TABLE_ADDRESS_LEN );
+
+REG64_FLD( PU_NPU_SM1_IODA_DAT0_TABLE_DATA                         , 0   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_TABLE_DATA );
+REG64_FLD( PU_NPU_SM1_IODA_DAT0_TABLE_DATA_LEN                     , 64  , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_TABLE_DATA_LEN );
+
+REG64_FLD( PU_IO_DATA_REG_PCB_TMP                                  , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCB_TMP    );
+REG64_FLD( PU_IO_DATA_REG_PCB_TMP_LEN                              , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCB_TMP_LEN );
+
+REG64_FLD( PU_IVT_OFFSET_PAYLOAD                                   , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PAYLOAD    );
+REG64_FLD( PU_IVT_OFFSET_PAYLOAD_LEN                               , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PAYLOAD_LEN );
+
+REG64_FLD( PU_JTG_PIB_OJCFG_JTAG_SRC_SEL                           , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_JTAG_SRC_SEL );
+REG64_FLD( PU_JTG_PIB_OJCFG_RUN_TCK                                , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RUN_TCK    );
+REG64_FLD( PU_JTG_PIB_OJCFG_TCK_WIDTH                              , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_TCK_WIDTH  );
+REG64_FLD( PU_JTG_PIB_OJCFG_TCK_WIDTH_LEN                          , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_TCK_WIDTH_LEN );
+REG64_FLD( PU_JTG_PIB_OJCFG_JTAG_TRST_B                            , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_JTAG_TRST_B );
+REG64_FLD( PU_JTG_PIB_OJCFG_DBG_HALT                               , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DBG_HALT   );
+
+REG64_FLD( PU_JTG_PIB_OJIC_START_JTAG_CMD                          , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_START_JTAG_CMD );
+REG64_FLD( PU_JTG_PIB_OJIC_DO_IR                                   , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DO_IR      );
+REG64_FLD( PU_JTG_PIB_OJIC_DO_DR                                   , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DO_DR      );
+REG64_FLD( PU_JTG_PIB_OJIC_DO_TAP_RESET                            , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DO_TAP_RESET );
+REG64_FLD( PU_JTG_PIB_OJIC_WR_VALID                                , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WR_VALID   );
+REG64_FLD( PU_JTG_PIB_OJIC_JTAG_INSTR                              , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_JTAG_INSTR );
+REG64_FLD( PU_JTG_PIB_OJIC_JTAG_INSTR_LEN                          , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_JTAG_INSTR_LEN );
+
+REG64_FLD( PU_JTG_PIB_OJSTAT_JTAG_INPROG                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_JTAG_INPROG );
+REG64_FLD( PU_JTG_PIB_OJSTAT_SRC_SEL_EQ1_ERR                       , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SRC_SEL_EQ1_ERR );
+REG64_FLD( PU_JTG_PIB_OJSTAT_RUN_TCK_EQ0_ERR                       , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RUN_TCK_EQ0_ERR );
+REG64_FLD( PU_JTG_PIB_OJSTAT_TRST_B_EQ0_ERR                        , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRST_B_EQ0_ERR );
+REG64_FLD( PU_JTG_PIB_OJSTAT_IR_DR_EQ0_ERR                         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IR_DR_EQ0_ERR );
+REG64_FLD( PU_JTG_PIB_OJSTAT_INPROG_WR_ERR                         , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INPROG_WR_ERR );
+REG64_FLD( PU_JTG_PIB_OJSTAT_FSM_ERROR                             , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FSM_ERROR  );
+
+REG64_FLD( PU_JTG_PIB_OJTDI_JTAG_TDI                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_JTAG_TDI   );
+REG64_FLD( PU_JTG_PIB_OJTDI_JTAG_TDI_LEN                           , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_JTAG_TDI_LEN );
+
+REG64_FLD( PU_JTG_PIB_OJTDO_JTAG_TDO                               , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_JTAG_TDO   );
+REG64_FLD( PU_JTG_PIB_OJTDO_JTAG_TDO_LEN                           , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_JTAG_TDO_LEN );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJCFG_JTAG_SRC_SEL                     , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJCFG_JTAG_SRC_SEL );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJCFG_RUN_TCK                          , 33  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJCFG_RUN_TCK );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJCFG_TCK_WIDTH                        , 34  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJCFG_TCK_WIDTH );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJCFG_TCK_WIDTH_LEN                    , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJCFG_TCK_WIDTH_LEN );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJCFG_JTAG_TRST_B                      , 37  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJCFG_JTAG_TRST_B );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJCFG_DBG_HALT                         , 38  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJCFG_DBG_HALT );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJSTAT_JTAG_INPROG                     , 40  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJSTAT_JTAG_INPROG );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJSTAT_SRC_SEL_EQ1_ERR                 , 41  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJSTAT_SRC_SEL_EQ1_ERR );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJSTAT_RUN_TCK_EQ0_ERR                 , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJSTAT_RUN_TCK_EQ0_ERR );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJSTAT_TRST_B_EQ0_ERR                  , 43  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJSTAT_TRST_B_EQ0_ERR );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJSTAT_IR_DR_EQ0_ERR                   , 44  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJSTAT_IR_DR_EQ0_ERR );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJSTAT_INPROG_WR_ERR                   , 45  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJSTAT_INPROG_WR_ERR );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJSTAT_FSM_ERROR                       , 46  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJSTAT_FSM_ERROR );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJIC_DO_IR                             , 49  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJIC_DO_IR );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJIC_DO_DR                             , 50  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJIC_DO_DR );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJIC_DO_TAP_RESET                      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJIC_DO_TAP_RESET );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJIC_WR_VALID                          , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJIC_WR_VALID );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJIC_JTAG_INSTR                        , 60  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJIC_JTAG_INSTR );
+REG64_FLD( PU_JTG_PIB_OJTDO_OJIC_JTAG_INSTR_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OJIC_JTAG_INSTR_LEN );
+
+REG64_FLD( PU_NPU_CTL_LCO_CONFIG_V_TARG                            , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_V_TARG     );
+REG64_FLD( PU_NPU_CTL_LCO_CONFIG_V_TARG_LEN                        , 12  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_V_TARG_LEN );
+REG64_FLD( PU_NPU_CTL_LCO_CONFIG_E_TARG_MIN                        , 12  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_E_TARG_MIN );
+REG64_FLD( PU_NPU_CTL_LCO_CONFIG_E_TARG_MIN_LEN                    , 4   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_E_TARG_MIN_LEN );
+REG64_FLD( PU_NPU_CTL_LCO_CONFIG_RAND_EVENT                        , 16  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RAND_EVENT );
+REG64_FLD( PU_NPU_CTL_LCO_CONFIG_RAND_EVENT_LEN                    , 4   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RAND_EVENT_LEN );
+
+REG64_FLD( CAPP_LINK_DELAY_TIMER_VALUE                             , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_VALUE      );
+REG64_FLD( CAPP_LINK_DELAY_TIMER_VALUE_LEN                         , 29  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_VALUE_LEN  );
+REG64_FLD( CAPP_LINK_DELAY_TIMER_VALID                             , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_VALID      );
+REG64_FLD( CAPP_LINK_DELAY_TIMER_RESP_PKT_RCV                      , 33  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_RESP_PKT_RCV );
+REG64_FLD( CAPP_LINK_DELAY_TIMER_SECURE_ERR                        , 34  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SECURE_ERR );
+
+REG64_FLD( PEC_LOCAL_FIR_IN0                                       , 0   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN0        );
+REG64_FLD( PEC_LOCAL_FIR_IN1                                       , 1   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN1        );
+REG64_FLD( PEC_LOCAL_FIR_IN2                                       , 2   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN2        );
+REG64_FLD( PEC_LOCAL_FIR_IN3                                       , 3   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN3        );
+REG64_FLD( PEC_LOCAL_FIR_IN4                                       , 4   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN4        );
+REG64_FLD( PEC_LOCAL_FIR_IN5                                       , 5   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN5        );
+REG64_FLD( PEC_LOCAL_FIR_IN6                                       , 6   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN6        );
+REG64_FLD( PEC_LOCAL_FIR_IN7                                       , 7   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN7        );
+REG64_FLD( PEC_LOCAL_FIR_IN8                                       , 8   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN8        );
+REG64_FLD( PEC_LOCAL_FIR_IN9                                       , 9   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN9        );
+REG64_FLD( PEC_LOCAL_FIR_IN10                                      , 10  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN10       );
+REG64_FLD( PEC_LOCAL_FIR_IN11                                      , 11  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN11       );
+REG64_FLD( PEC_LOCAL_FIR_IN12                                      , 12  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN12       );
+REG64_FLD( PEC_LOCAL_FIR_IN13                                      , 13  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN13       );
+REG64_FLD( PEC_LOCAL_FIR_IN14                                      , 14  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN14       );
+REG64_FLD( PEC_LOCAL_FIR_IN15                                      , 15  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN15       );
+REG64_FLD( PEC_LOCAL_FIR_IN16                                      , 16  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN16       );
+REG64_FLD( PEC_LOCAL_FIR_IN17                                      , 17  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN17       );
+REG64_FLD( PEC_LOCAL_FIR_IN18                                      , 18  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN18       );
+REG64_FLD( PEC_LOCAL_FIR_IN19                                      , 19  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN19       );
+REG64_FLD( PEC_LOCAL_FIR_IN20                                      , 20  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN20       );
+REG64_FLD( PEC_LOCAL_FIR_IN21                                      , 21  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN21       );
+REG64_FLD( PEC_LOCAL_FIR_IN22                                      , 22  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN22       );
+REG64_FLD( PEC_LOCAL_FIR_IN23                                      , 23  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN23       );
+REG64_FLD( PEC_LOCAL_FIR_IN24                                      , 24  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN24       );
+REG64_FLD( PEC_LOCAL_FIR_IN25                                      , 25  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN25       );
+REG64_FLD( PEC_LOCAL_FIR_IN26                                      , 26  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN26       );
+REG64_FLD( PEC_LOCAL_FIR_IN27                                      , 27  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN27       );
+REG64_FLD( PEC_LOCAL_FIR_IN28                                      , 28  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN28       );
+REG64_FLD( PEC_LOCAL_FIR_IN29                                      , 29  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN29       );
+REG64_FLD( PEC_LOCAL_FIR_IN30                                      , 30  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN30       );
+REG64_FLD( PEC_LOCAL_FIR_IN31                                      , 31  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN31       );
+REG64_FLD( PEC_LOCAL_FIR_IN32                                      , 32  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN32       );
+REG64_FLD( PEC_LOCAL_FIR_IN33                                      , 33  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN33       );
+REG64_FLD( PEC_LOCAL_FIR_IN34                                      , 34  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN34       );
+REG64_FLD( PEC_LOCAL_FIR_IN35                                      , 35  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN35       );
+REG64_FLD( PEC_LOCAL_FIR_IN36                                      , 36  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN36       );
+REG64_FLD( PEC_LOCAL_FIR_IN37                                      , 37  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN37       );
+REG64_FLD( PEC_LOCAL_FIR_IN38                                      , 38  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN38       );
+REG64_FLD( PEC_LOCAL_FIR_IN39                                      , 39  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN39       );
+REG64_FLD( PEC_LOCAL_FIR_IN40                                      , 40  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN40       );
+REG64_FLD( PEC_LOCAL_FIR_IN41                                      , 41  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN41       );
+
+REG64_FLD( PEC_LOCAL_FIR_ACTION0_IN                                , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( PEC_LOCAL_FIR_ACTION0_IN_LEN                            , 42  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( PEC_LOCAL_FIR_ACTION1_IN                                , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( PEC_LOCAL_FIR_ACTION1_IN_LEN                            , 42  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( PEC_LOCAL_FIR_MASK_LFIR_IN                              , 0   , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_LFIR_IN    );
+REG64_FLD( PEC_LOCAL_FIR_MASK_LFIR_IN_LEN                          , 42  , SH_UNT_PEC      , SH_ACS_SCOM2_OR ,
+           SH_FLD_LFIR_IN_LEN );
+
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN0                                 , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN0        );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN1                                 , 1   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN1        );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN2                                 , 2   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN2        );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN3                                 , 3   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN3        );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN4                                 , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN4        );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN5                                 , 5   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN5        );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN6                                 , 6   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN6        );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN7                                 , 7   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN7        );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN8                                 , 8   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN8        );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN9                                 , 9   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN9        );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN10                                , 10  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN10       );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN11                                , 11  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN11       );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN12                                , 12  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN12       );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN13                                , 13  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN13       );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN14                                , 14  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN14       );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN15                                , 15  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN15       );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN16                                , 16  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN16       );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN17                                , 17  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN17       );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN18                                , 18  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN18       );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN19                                , 19  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN19       );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN20                                , 20  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN20       );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN21                                , 21  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN21       );
+REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN22                                , 22  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN22       );
+
+REG64_FLD( PEC_LOCAL_XSTOP_MASK_IN                                 , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( PEC_LOCAL_XSTOP_MASK_IN_LEN                             , 22  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MODE_ENABLE                     , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_LP_MODE_ENABLE );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_ONLY_MODE                       , 1   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_LP_ONLY_MODE );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_TIMER_TICK_CONFIG               , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_LP_TIMER_TICK_CONFIG );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN           , 6   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_LP_TIMER_TICK_CONFIG_LEN );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MIN_CRED_THRESH                 , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_LP_MIN_CRED_THRESH );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MIN_CRED_THRESH_LEN             , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_LP_MIN_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MAX_CRED_THRESH                 , 20  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_LP_MAX_CRED_THRESH );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MAX_CRED_THRESH_LEN             , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_LP_MAX_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_CNT_THRESH                      , 32  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_LP_CNT_THRESH );
+REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_CNT_THRESH_LEN                  , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_LP_CNT_THRESH_LEN );
+
+REG64_FLD( NV_LOW_PWR_LP_MODE_ENABLE                               , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_LP_MODE_ENABLE );
+REG64_FLD( NV_LOW_PWR_LP_ONLY_MODE                                 , 1   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_LP_ONLY_MODE );
+REG64_FLD( NV_LOW_PWR_LP_TIMER_TICK_CONFIG                         , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_LP_TIMER_TICK_CONFIG );
+REG64_FLD( NV_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN                     , 6   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_LP_TIMER_TICK_CONFIG_LEN );
+REG64_FLD( NV_LOW_PWR_LP_MIN_CRED_THRESH                           , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_LP_MIN_CRED_THRESH );
+REG64_FLD( NV_LOW_PWR_LP_MIN_CRED_THRESH_LEN                       , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_LP_MIN_CRED_THRESH_LEN );
+REG64_FLD( NV_LOW_PWR_LP_MAX_CRED_THRESH                           , 20  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_LP_MAX_CRED_THRESH );
+REG64_FLD( NV_LOW_PWR_LP_MAX_CRED_THRESH_LEN                       , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_LP_MAX_CRED_THRESH_LEN );
+REG64_FLD( NV_LOW_PWR_LP_CNT_THRESH                                , 32  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_LP_CNT_THRESH );
+REG64_FLD( NV_LOW_PWR_LP_CNT_THRESH_LEN                            , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_LP_CNT_THRESH_LEN );
+
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_MODE_ENABLE                     , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_LP_MODE_ENABLE );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_ONLY_MODE                       , 1   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_LP_ONLY_MODE );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_TIMER_TICK_CONFIG               , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_LP_TIMER_TICK_CONFIG );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN           , 6   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_LP_TIMER_TICK_CONFIG_LEN );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_MIN_CRED_THRESH                 , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_LP_MIN_CRED_THRESH );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_MIN_CRED_THRESH_LEN             , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_LP_MIN_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_MAX_CRED_THRESH                 , 20  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_LP_MAX_CRED_THRESH );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_MAX_CRED_THRESH_LEN             , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_LP_MAX_CRED_THRESH_LEN );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_CNT_THRESH                      , 32  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_LP_CNT_THRESH );
+REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_CNT_THRESH_LEN                  , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_LP_CNT_THRESH_LEN );
+
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_XATS                       , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_XATS_LEN                   , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PWR0                       , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PWR0_LEN                   , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PWR1                       , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PWR1_LEN                   , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_REQ0                       , 18  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_REQ0_LEN                   , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PRB0                       , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PRB0_LEN                   , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_REQ1                       , 30  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_REQ1_LEN                   , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PRB1                       , 36  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PRB1_LEN                   , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_MAX_MACHINES               , 42  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_MAX_MACHINES_LEN           , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_RESERVED1                         , 48  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_RESERVED1_LEN                     , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 51  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_XATS                       , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_XATS_LEN                   , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PWR0                       , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PWR0_LEN                   , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PWR1                       , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PWR1_LEN                   , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_REQ0                       , 18  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_REQ0_LEN                   , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PRB0                       , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PRB0_LEN                   , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_REQ1                       , 30  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_REQ1_LEN                   , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PRB1                       , 36  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PRB1_LEN                   , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_MAX_MACHINES               , 42  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_MAX_MACHINES_LEN           , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_RESERVED1                         , 48  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_RESERVED1_LEN                     , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 51  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_XATS                       , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_XATS_LEN                   , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PWR0                       , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PWR0_LEN                   , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PWR1                       , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PWR1_LEN                   , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_REQ0                       , 18  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_REQ0_LEN                   , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PRB0                       , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PRB0_LEN                   , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_REQ1                       , 30  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_REQ1_LEN                   , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PRB1                       , 36  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PRB1_LEN                   , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_MAX_MACHINES               , 42  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_MAX_MACHINES_LEN           , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_RESERVED1                         , 48  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_RESERVED1_LEN                     , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 51  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_XATS                       , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_XATS_LEN                   , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PWR0                       , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PWR0_LEN                   , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PWR1                       , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PWR1_LEN                   , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_REQ0                       , 18  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_REQ0_LEN                   , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PRB0                       , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PRB0_LEN                   , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_REQ1                       , 30  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_REQ1_LEN                   , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PRB1                       , 36  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PRB1_LEN                   , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_MAX_MACHINES               , 42  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_MAX_MACHINES_LEN           , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_RESERVED1                         , 48  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_RESERVED1_LEN                     , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 51  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_XATS                       , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_XATS_LEN                   , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PWR0                       , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PWR0_LEN                   , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PWR1                       , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PWR1_LEN                   , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_REQ0                       , 18  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_REQ0_LEN                   , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PRB0                       , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PRB0_LEN                   , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_REQ1                       , 30  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_REQ1_LEN                   , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PRB1                       , 36  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PRB1_LEN                   , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_MAX_MACHINES               , 42  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_MAX_MACHINES_LEN           , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_RESERVED1                         , 48  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_RESERVED1_LEN                     , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 51  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_XATS                       , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_XATS_LEN                   , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PWR0                       , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PWR0_LEN                   , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PWR1                       , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PWR1_LEN                   , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_REQ0                       , 18  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_REQ0_LEN                   , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PRB0                       , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PRB0_LEN                   , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_REQ1                       , 30  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_REQ1_LEN                   , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PRB1                       , 36  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PRB1_LEN                   , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_MAX_MACHINES               , 42  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_MAX_MACHINES_LEN           , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_RESERVED1                         , 48  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_RESERVED1_LEN                     , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 51  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_XATS                       , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_XATS_LEN                   , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PWR0                       , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PWR0_LEN                   , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PWR1                       , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PWR1_LEN                   , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_REQ0                       , 18  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_REQ0_LEN                   , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PRB0                       , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PRB0_LEN                   , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_REQ1                       , 30  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_REQ1_LEN                   , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PRB1                       , 36  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PRB1_LEN                   , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_MAX_MACHINES               , 42  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_MAX_MACHINES_LEN           , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_RESERVED1                         , 48  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_RESERVED1_LEN                     , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 51  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_XATS                       , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_XATS_LEN                   , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PWR0                       , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PWR0_LEN                   , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PWR1                       , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PWR1_LEN                   , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_REQ0                       , 18  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_REQ0_LEN                   , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PRB0                       , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PRB0_LEN                   , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_REQ1                       , 30  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_REQ1_LEN                   , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PRB1                       , 36  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PRB1_LEN                   , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_MAX_MACHINES               , 42  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_MAX_MACHINES_LEN           , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_RESERVED1                         , 48  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_RESERVED1_LEN                     , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 51  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_XATS                       , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_XATS_LEN                   , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PWR0                       , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PWR0_LEN                   , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PWR1                       , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PWR1_LEN                   , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_REQ0                       , 18  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_REQ0_LEN                   , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PRB0                       , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PRB0_LEN                   , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_REQ1                       , 30  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_REQ1_LEN                   , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PRB1                       , 36  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PRB1_LEN                   , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_MAX_MACHINES               , 42  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_MAX_MACHINES_LEN           , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_RESERVED1                         , 48  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_RESERVED1_LEN                     , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 51  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_XATS                       , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_XATS_LEN                   , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PWR0                       , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PWR0_LEN                   , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PWR1                       , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PWR1_LEN                   , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_REQ0                       , 18  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_REQ0_LEN                   , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PRB0                       , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PRB0_LEN                   , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_REQ1                       , 30  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_REQ1_LEN                   , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PRB1                       , 36  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PRB1_LEN                   , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_MAX_MACHINES               , 42  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_MAX_MACHINES_LEN           , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_RESERVED1                         , 48  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_RESERVED1_LEN                     , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 51  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_XATS                       , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_XATS_LEN                   , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PWR0                       , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PWR0_LEN                   , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PWR1                       , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PWR1_LEN                   , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_REQ0                       , 18  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_REQ0_LEN                   , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PRB0                       , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PRB0_LEN                   , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_REQ1                       , 30  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_REQ1_LEN                   , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PRB1                       , 36  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PRB1_LEN                   , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_MAX_MACHINES               , 42  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_MAX_MACHINES_LEN           , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_RESERVED1                         , 48  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_RESERVED1_LEN                     , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 51  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_XATS                       , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_XATS_LEN                   , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_XATS_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PWR0                       , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0 );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PWR0_LEN                   , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR0_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PWR1                       , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1 );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PWR1_LEN                   , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PWR1_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_REQ0                       , 18  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0 );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_REQ0_LEN                   , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ0_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PRB0                       , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0 );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PRB0_LEN                   , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB0_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_REQ1                       , 30  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1 );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_REQ1_LEN                   , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_REQ1_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PRB1                       , 36  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1 );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PRB1_LEN                   , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PRB1_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_MAX_MACHINES               , 42  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_MAX_MACHINES_LEN           , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_MAX_MACHINES_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_RESERVED1                         , 48  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_RESERVED1_LEN                     , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC       , 51  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC );
+
+REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_BUSY_ENABLE                    , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BUSY_ENABLE );
+REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_WINDOW_SELECT                  , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_WINDOW_SELECT );
+REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_WINDOW_SELECT_LEN              , 3   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_WINDOW_SELECT_LEN );
+REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_THRESH_0                       , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_0   );
+REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_THRESH_0_LEN                   , 10  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_0_LEN );
+REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_THRESH_1                       , 14  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_1   );
+REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_THRESH_1_LEN                   , 10  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_1_LEN );
+REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_THRESH_2                       , 24  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_2   );
+REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_THRESH_2_LEN                   , 10  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_2_LEN );
+REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_RESERVED1                      , 34  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_RESERVED1_LEN                  , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_BUSY_ENABLE                    , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BUSY_ENABLE );
+REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_WINDOW_SELECT                  , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_WINDOW_SELECT );
+REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_WINDOW_SELECT_LEN              , 3   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_WINDOW_SELECT_LEN );
+REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_THRESH_0                       , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_0   );
+REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_THRESH_0_LEN                   , 10  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_0_LEN );
+REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_THRESH_1                       , 14  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_1   );
+REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_THRESH_1_LEN                   , 10  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_1_LEN );
+REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_THRESH_2                       , 24  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_2   );
+REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_THRESH_2_LEN                   , 10  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_2_LEN );
+REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_RESERVED1                      , 34  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_RESERVED1_LEN                  , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_BUSY_ENABLE                    , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BUSY_ENABLE );
+REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_WINDOW_SELECT                  , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_WINDOW_SELECT );
+REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_WINDOW_SELECT_LEN              , 3   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_WINDOW_SELECT_LEN );
+REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_THRESH_0                       , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_0   );
+REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_THRESH_0_LEN                   , 10  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_0_LEN );
+REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_THRESH_1                       , 14  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_1   );
+REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_THRESH_1_LEN                   , 10  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_1_LEN );
+REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_THRESH_2                       , 24  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_2   );
+REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_THRESH_2_LEN                   , 10  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_THRESH_2_LEN );
+REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_RESERVED1                      , 34  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_RESERVED1_LEN                  , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_LPC_BASE_REG_BASE                                    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BASE       );
+REG64_FLD( PU_LPC_BASE_REG_BASE_LEN                                , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BASE_LEN   );
+REG64_FLD( PU_LPC_BASE_REG_DISABLE                                 , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE    );
+
+REG64_FLD( PU_LPC_CMD_REG_RNW                                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RNW        );
+REG64_FLD( PU_LPC_CMD_REG_SIZE                                     , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SIZE       );
+REG64_FLD( PU_LPC_CMD_REG_SIZE_LEN                                 , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SIZE_LEN   );
+REG64_FLD( PU_LPC_CMD_REG_ADR                                      , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADR        );
+REG64_FLD( PU_LPC_CMD_REG_ADR_LEN                                  , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADR_LEN    );
+
+REG64_FLD( PU_LPC_DATA_REG_DATA                                    , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_LPC_DATA_REG_DATA_LEN                                , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_LPC_STATUS_REG_DONE                                  , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DONE       );
+REG64_FLD( PU_LPC_STATUS_REG_VALID                                 , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_VALID      );
+REG64_FLD( PU_LPC_STATUS_REG_ACK                                   , 11  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACK        );
+
+REG64_FLD( PU_MCC_FIR_REG_MCD_ARRAY_ECC_UE_ERR                     , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_ARRAY_ECC_UE_ERR );
+REG64_FLD( PU_MCC_FIR_REG_MCD_ARRAY_ECC_CE_ERR                     , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_ARRAY_ECC_CE_ERR );
+REG64_FLD( PU_MCC_FIR_REG_MCD_PB_ADDR_PARITY_ERR                   , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_PB_ADDR_PARITY_ERR );
+REG64_FLD( PU_MCC_FIR_REG_MCD_SM_OR_CASE_ERR                       , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_SM_OR_CASE_ERR );
+REG64_FLD( PU_MCC_FIR_REG_MCD_CL_PROBE_PB_HANG_ERR                 , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_CL_PROBE_PB_HANG_ERR );
+REG64_FLD( PU_MCC_FIR_REG_MCD_CRESP_ADDR_ERR                       , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_CRESP_ADDR_ERR );
+REG64_FLD( PU_MCC_FIR_REG_MCD_UNSOLICITED_CRESP_ERR                , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_UNSOLICITED_CRESP_ERR );
+REG64_FLD( PU_MCC_FIR_REG_MCD_TTAG_PARITY_ERR                      , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_TTAG_PARITY_ERR );
+REG64_FLD( PU_MCC_FIR_REG_MCD_UPDATE_ERR                           , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_UPDATE_ERR );
+REG64_FLD( PU_MCC_FIR_REG_MCD_ACK_DEAD_CRESP_ERR                   , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_ACK_DEAD_CRESP_ERR );
+REG64_FLD( PU_MCC_FIR_REG_MCD_SCOM_ERR                             , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_SCOM_ERR );
+REG64_FLD( PU_MCC_FIR_REG_MCD_SCOM_ERR_DUP                         , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_SCOM_ERR_DUP );
+
+REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_ARRAY_ECC_UE_ERR                , 0   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_ARRAY_ECC_UE_ERR );
+REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_ARRAY_ECC_CE_ERR                , 1   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_ARRAY_ECC_CE_ERR );
+REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_PB_ADDR_PARITY_ERR              , 2   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_PB_ADDR_PARITY_ERR );
+REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_SM_OR_CASE_ERR                  , 3   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_SM_OR_CASE_ERR );
+REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_CL_PROBE_PB_HANG_ERR            , 4   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_CL_PROBE_PB_HANG_ERR );
+REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_CRESP_ADDR_ERR                  , 5   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_CRESP_ADDR_ERR );
+REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_UNSOLICITED_CRESP_ERR           , 6   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_UNSOLICITED_CRESP_ERR );
+REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_TTAG_PARITY_ERR                 , 7   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_TTAG_PARITY_ERR );
+REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_UPDATE_ERR                      , 8   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_UPDATE_ERR );
+REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_ACK_DEAD_CRESP_ERR              , 9   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_ACK_DEAD_CRESP_ERR );
+REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_SCOM_ERR                        , 10  , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_SCOM_ERR );
+REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_SCOM_ERR_DUP                    , 11  , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MCD_SCOM_ERR_DUP );
+
+REG64_FLD( PU_MCD_DBG_TRACE_ENABLE                                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_ENABLE );
+REG64_FLD( PU_MCD_DBG_TRACE_SELECT                                 , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SELECT );
+REG64_FLD( PU_MCD_DBG_TRACE_SELECT_LEN                             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SELECT_LEN );
+REG64_FLD( PU_MCD_DBG_ERR_INJ_ENABLE                               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_ENABLE );
+REG64_FLD( PU_MCD_DBG_ERR_INJ_TYPE                                 , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_TYPE );
+REG64_FLD( PU_MCD_DBG_ERR_INJ_ACTION                               , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_ACTION );
+REG64_FLD( PU_MCD_DBG_ERR_INJ_ARRAY_SEL                            , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_ARRAY_SEL );
+REG64_FLD( PU_MCD_DBG_ERR_INJ_ARRAY_SEL_LEN                        , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_ARRAY_SEL_LEN );
+REG64_FLD( PU_MCD_DBG_ERR_INJ_STATUS                               , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_STATUS );
+REG64_FLD( PU_MCD_DBG_PMU_ENABLE                                   , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PMU_ENABLE );
+REG64_FLD( PU_MCD_DBG_PMU_SELECT_LOW                               , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PMU_SELECT_LOW );
+REG64_FLD( PU_MCD_DBG_PMU_SELECT_LOW_LEN                           , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PMU_SELECT_LOW_LEN );
+REG64_FLD( PU_MCD_DBG_PMU_SELECT_HIGH                              , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PMU_SELECT_HIGH );
+REG64_FLD( PU_MCD_DBG_PMU_SELECT_HIGH_LEN                          , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PMU_SELECT_HIGH_LEN );
+REG64_FLD( PU_MCD_DBG_PMU_BUS_ENABLE                               , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PMU_BUS_ENABLE );
+REG64_FLD( PU_MCD_DBG_PMU_BUS_ENABLE_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PMU_BUS_ENABLE_LEN );
+
+REG64_FLD( PU_MCD1_MCD_DBG_TRACE_ENABLE                            , 3   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_ENABLE );
+REG64_FLD( PU_MCD1_MCD_DBG_TRACE_SELECT                            , 4   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SELECT );
+REG64_FLD( PU_MCD1_MCD_DBG_TRACE_SELECT_LEN                        , 4   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SELECT_LEN );
+REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_ENABLE                          , 8   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_ENABLE );
+REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_TYPE                            , 9   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_TYPE );
+REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_ACTION                          , 10  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_ACTION );
+REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_ARRAY_SEL                       , 11  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_ARRAY_SEL );
+REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_ARRAY_SEL_LEN                   , 4   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_ARRAY_SEL_LEN );
+REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_STATUS                          , 15  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_STATUS );
+REG64_FLD( PU_MCD1_MCD_DBG_PMU_ENABLE                              , 19  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_PMU_ENABLE );
+REG64_FLD( PU_MCD1_MCD_DBG_PMU_SELECT_LOW                          , 20  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_PMU_SELECT_LOW );
+REG64_FLD( PU_MCD1_MCD_DBG_PMU_SELECT_LOW_LEN                      , 3   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_PMU_SELECT_LOW_LEN );
+REG64_FLD( PU_MCD1_MCD_DBG_PMU_SELECT_HIGH                         , 23  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_PMU_SELECT_HIGH );
+REG64_FLD( PU_MCD1_MCD_DBG_PMU_SELECT_HIGH_LEN                     , 3   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_PMU_SELECT_HIGH_LEN );
+REG64_FLD( PU_MCD1_MCD_DBG_PMU_BUS_ENABLE                          , 32  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_PMU_BUS_ENABLE );
+REG64_FLD( PU_MCD1_MCD_DBG_PMU_BUS_ENABLE_LEN                      , 16  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_PMU_BUS_ENABLE_LEN );
+
+REG64_FLD( PU_MCD_ECAP_ECC_CLEAR                                   , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_CLEAR  );
+REG64_FLD( PU_MCD_ECAP_ECC_UE                                      , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_UE     );
+REG64_FLD( PU_MCD_ECAP_ECC_CE                                      , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_CE     );
+REG64_FLD( PU_MCD_ECAP_ECC_ERROR_COUNT                             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_ERROR_COUNT );
+REG64_FLD( PU_MCD_ECAP_ECC_ERROR_COUNT_LEN                         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_ERROR_COUNT_LEN );
+REG64_FLD( PU_MCD_ECAP_ECC_ERROR_ADDR                              , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_ERROR_ADDR );
+REG64_FLD( PU_MCD_ECAP_ECC_ERROR_ADDR_LEN                          , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_ERROR_ADDR_LEN );
+REG64_FLD( PU_MCD_ECAP_ECC_SYNDROME                                , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_SYNDROME );
+REG64_FLD( PU_MCD_ECAP_ECC_SYNDROME_LEN                            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_SYNDROME_LEN );
+REG64_FLD( PU_MCD_ECAP_SLICE0_CFG_ECC_UE_ERR                       , 33  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SLICE0_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD_ECAP_SLICE0_CFG_ECC_CE_ERR                       , 34  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SLICE0_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD_ECAP_SLICE1_CFG_ECC_UE_ERR                       , 35  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SLICE1_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD_ECAP_SLICE1_CFG_ECC_CE_ERR                       , 36  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SLICE1_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD_ECAP_SLICE2_CFG_ECC_UE_ERR                       , 37  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SLICE2_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD_ECAP_SLICE2_CFG_ECC_CE_ERR                       , 38  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SLICE2_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD_ECAP_SLICE3_CFG_ECC_UE_ERR                       , 39  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SLICE3_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD_ECAP_SLICE3_CFG_ECC_CE_ERR                       , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SLICE3_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD_ECAP_PRESP_RTY_OTHER                             , 41  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESP_RTY_OTHER );
+REG64_FLD( PU_MCD_ECAP_REC_SM_ERROR_ERR                            , 42  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REC_SM_ERROR_ERR );
+REG64_FLD( PU_MCD_ECAP_REC_PB_SM_ERROR_ERR                         , 43  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REC_PB_SM_ERROR_ERR );
+REG64_FLD( PU_MCD_ECAP_ADDR_ERROR_PULSE                            , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_ERROR_PULSE );
+REG64_FLD( PU_MCD_ECAP_RCMD0_ADDR_PARITY_ERROR                     , 45  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RCMD0_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD_ECAP_RCMD1_ADDR_PARITY_ERROR                     , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RCMD1_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD_ECAP_RCMD2_ADDR_PARITY_ERROR                     , 47  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RCMD2_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD_ECAP_RCMD3_ADDR_PARITY_ERROR                     , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RCMD3_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD_ECAP_WARB_INVALID_CASE_ERROR                     , 49  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WARB_INVALID_CASE_ERROR );
+REG64_FLD( PU_MCD_ECAP_INVALID_CRESP_ERROR                         , 50  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INVALID_CRESP_ERROR );
+REG64_FLD( PU_MCD_ECAP_TTAG_PARITY_ERROR                           , 51  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TTAG_PARITY_ERROR );
+REG64_FLD( PU_MCD_ECAP_RDADDR_ARB_BAD_HAND                         , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RDADDR_ARB_BAD_HAND );
+REG64_FLD( PU_MCD_ECAP_RDWR_UPDATE_ERROR                           , 53  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_UPDATE_ERROR );
+REG64_FLD( PU_MCD_ECAP_REC_UPDATE_ERROR                            , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REC_UPDATE_ERROR );
+REG64_FLD( PU_MCD_ECAP_REC_ACK_DEAD_ERROR                          , 55  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REC_ACK_DEAD_ERROR );
+
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_CLEAR                              , 0   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ECC_CLEAR  );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_UE                                 , 2   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ECC_UE     );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_CE                                 , 3   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ECC_CE     );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_ERROR_COUNT                        , 4   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ECC_ERROR_COUNT );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_ERROR_COUNT_LEN                    , 4   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ECC_ERROR_COUNT_LEN );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_ERROR_ADDR                         , 10  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ECC_ERROR_ADDR );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_ERROR_ADDR_LEN                     , 14  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ECC_ERROR_ADDR_LEN );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_SYNDROME                           , 24  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ECC_SYNDROME );
+REG64_FLD( PU_MCD1_MCD_ECAP_ECC_SYNDROME_LEN                       , 8   , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ECC_SYNDROME_LEN );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE0_CFG_ECC_UE_ERR                  , 33  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_SLICE0_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE0_CFG_ECC_CE_ERR                  , 34  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_SLICE0_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE1_CFG_ECC_UE_ERR                  , 35  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_SLICE1_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE1_CFG_ECC_CE_ERR                  , 36  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_SLICE1_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE2_CFG_ECC_UE_ERR                  , 37  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_SLICE2_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE2_CFG_ECC_CE_ERR                  , 38  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_SLICE2_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE3_CFG_ECC_UE_ERR                  , 39  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_SLICE3_CFG_ECC_UE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_SLICE3_CFG_ECC_CE_ERR                  , 40  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_SLICE3_CFG_ECC_CE_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_PRESP_RTY_OTHER                        , 41  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_PRESP_RTY_OTHER );
+REG64_FLD( PU_MCD1_MCD_ECAP_REC_SM_ERROR_ERR                       , 42  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_REC_SM_ERROR_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_REC_PB_SM_ERROR_ERR                    , 43  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_REC_PB_SM_ERROR_ERR );
+REG64_FLD( PU_MCD1_MCD_ECAP_ADDR_ERROR_PULSE                       , 44  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_ERROR_PULSE );
+REG64_FLD( PU_MCD1_MCD_ECAP_RCMD0_ADDR_PARITY_ERROR                , 45  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RCMD0_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_RCMD1_ADDR_PARITY_ERROR                , 46  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RCMD1_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_RCMD2_ADDR_PARITY_ERROR                , 47  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RCMD2_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_RCMD3_ADDR_PARITY_ERROR                , 48  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RCMD3_ADDR_PARITY_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_WARB_INVALID_CASE_ERROR                , 49  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_WARB_INVALID_CASE_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_INVALID_CRESP_ERROR                    , 50  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_INVALID_CRESP_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_TTAG_PARITY_ERROR                      , 51  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_TTAG_PARITY_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_RDADDR_ARB_BAD_HAND                    , 52  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RDADDR_ARB_BAD_HAND );
+REG64_FLD( PU_MCD1_MCD_ECAP_RDWR_UPDATE_ERROR                      , 53  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_UPDATE_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_REC_UPDATE_ERROR                       , 54  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_REC_UPDATE_ERROR );
+REG64_FLD( PU_MCD1_MCD_ECAP_REC_ACK_DEAD_ERROR                     , 55  , SH_UNT_PU_MCD1  , SH_ACS_SCOM     ,
+           SH_FLD_REC_ACK_DEAD_ERROR );
+
+REG64_FLD( PU_MCD_FIR_ACTION0_REG_ACTION0                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( PU_MCD_FIR_ACTION0_REG_ACTION0_LEN                      , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_MCD1_MCD_FIR_ACTION0_REG_ACTION0                     , 0   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( PU_MCD1_MCD_FIR_ACTION0_REG_ACTION0_LEN                 , 12  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_MCD_FIR_ACTION1_REG_ACTION1                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( PU_MCD_FIR_ACTION1_REG_ACTION1_LEN                      , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_MCD1_MCD_FIR_ACTION1_REG_ACTION1                     , 0   , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( PU_MCD1_MCD_FIR_ACTION1_REG_ACTION1_LEN                 , 12  , SH_UNT_PU_MCD1  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_MCD_FIR_MASK_REG_ARRAY_ECC_UE                        , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARRAY_ECC_UE );
+REG64_FLD( PU_MCD_FIR_MASK_REG_ARRAY_ECC_CE                        , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARRAY_ECC_CE );
+REG64_FLD( PU_MCD_FIR_MASK_REG_PB_ADDR_PARITY                      , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_ADDR_PARITY );
+REG64_FLD( PU_MCD_FIR_MASK_REG_SM_OR_CASE                          , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SM_OR_CASE );
+REG64_FLD( PU_MCD_FIR_MASK_REG_CL_PROBE_PB_HANG                    , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CL_PROBE_PB_HANG );
+REG64_FLD( PU_MCD_FIR_MASK_REG_CRESP_ADDR                          , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CRESP_ADDR );
+REG64_FLD( PU_MCD_FIR_MASK_REG_UNSOLICITED_CRESP                   , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UNSOLICITED_CRESP );
+REG64_FLD( PU_MCD_FIR_MASK_REG_TTAG_PARITY                         , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_TTAG_PARITY );
+REG64_FLD( PU_MCD_FIR_MASK_REG_UPDATE_ERR                          , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UPDATE_ERR );
+REG64_FLD( PU_MCD_FIR_MASK_REG_ACK_DEAD_CRESP                      , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ACK_DEAD_CRESP );
+REG64_FLD( PU_MCD_FIR_MASK_REG_SCOM_ERR                            , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+REG64_FLD( PU_MCD_FIR_MASK_REG_SCOM_ERR_DUP                        , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+
+REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_ARRAY_ECC_UE                   , 0   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARRAY_ECC_UE );
+REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_ARRAY_ECC_CE                   , 1   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_ARRAY_ECC_CE );
+REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_PB_ADDR_PARITY                 , 2   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_ADDR_PARITY );
+REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_SM_OR_CASE                     , 3   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_SM_OR_CASE );
+REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_CL_PROBE_PB_HANG               , 4   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_CL_PROBE_PB_HANG );
+REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_CRESP_ADDR                     , 5   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_CRESP_ADDR );
+REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_UNSOLICITED_CRESP              , 6   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_UNSOLICITED_CRESP );
+REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_TTAG_PARITY                    , 7   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TTAG_PARITY );
+REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_UPDATE_ERR                     , 8   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_UPDATE_ERR );
+REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_ACK_DEAD_CRESP                 , 9   , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_ACK_DEAD_CRESP );
+REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR                       , 10  , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR_DUP                   , 11  , SH_UNT_PU_MCD1  , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+
+REG64_FLD( PU_MIB_XIICAC_ICACHE_TAG_ADDR                           , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR );
+REG64_FLD( PU_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                       , 27  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR_LEN );
+REG64_FLD( PU_MIB_XIICAC_ICACHE_ERR                                , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_ERR );
+REG64_FLD( PU_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING                  , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IFETCH_PENDING );
+REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID                              , 36  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID );
+REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID_LEN                          , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID_LEN );
+
+REG64_FLD( PU_MIB_XIMEM_MEM_ADDR                                   , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR   );
+REG64_FLD( PU_MIB_XIMEM_MEM_ADDR_LEN                               , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR_LEN );
+REG64_FLD( PU_MIB_XIMEM_MEM_R_NW                                   , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_R_NW   );
+REG64_FLD( PU_MIB_XIMEM_MEM_BUSY                                   , 33  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BUSY   );
+REG64_FLD( PU_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING                , 34  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_MIB_XIMEM_MEM_BYTE_ENABLE                            , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE );
+REG64_FLD( PU_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                        , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE_LEN );
+REG64_FLD( PU_MIB_XIMEM_MEM_LINE_MODE                              , 43  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_LINE_MODE );
+REG64_FLD( PU_MIB_XIMEM_MEM_ERROR                                  , 49  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR  );
+REG64_FLD( PU_MIB_XIMEM_MEM_ERROR_LEN                              , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR_LEN );
+REG64_FLD( PU_MIB_XIMEM_MEM_IFETCH_PENDING                         , 62  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IFETCH_PENDING );
+REG64_FLD( PU_MIB_XIMEM_MEM_DATAOP_PENDING                         , 63  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_DATAOP_PENDING );
+
+REG64_FLD( PU_MIB_XISGB_STORE_ADDRESS                              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS );
+REG64_FLD( PU_MIB_XISGB_STORE_ADDRESS_LEN                          , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS_LEN );
+REG64_FLD( PU_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING          , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_MIB_XISGB_SGB_BYTE_VALID                             , 36  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID );
+REG64_FLD( PU_MIB_XISGB_SGB_BYTE_VALID_LEN                         , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID_LEN );
+REG64_FLD( PU_MIB_XISGB_SGB_FLUSH_PENDING                          , 63  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_FLUSH_PENDING );
+
+REG64_FLD( PU_MIB_XISIB_PIB_ADDR                                   , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PIB_ADDR   );
+REG64_FLD( PU_MIB_XISIB_PIB_ADDR_LEN                               , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PIB_ADDR_LEN );
+REG64_FLD( PU_MIB_XISIB_PIB_R_NW                                   , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PIB_R_NW   );
+REG64_FLD( PU_MIB_XISIB_PIB_BUSY                                   , 33  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PIB_BUSY   );
+REG64_FLD( PU_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING                , 34  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PIB_IMPRECISE_ERROR_PENDING );
+REG64_FLD( PU_MIB_XISIB_PIB_RSP_INFO                               , 49  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PIB_RSP_INFO );
+REG64_FLD( PU_MIB_XISIB_PIB_RSP_INFO_LEN                           , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PIB_RSP_INFO_LEN );
+REG64_FLD( PU_MIB_XISIB_PIB_IFETCH_PENDING                         , 62  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PIB_IFETCH_PENDING );
+REG64_FLD( PU_MIB_XISIB_PIB_DATAOP_PENDING                         , 63  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PIB_DATAOP_PENDING );
+
+REG64_FLD( PU_NPU_CTL_MISC_CONFIG_SYNC_WAIT                        , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SYNC_WAIT  );
+REG64_FLD( PU_NPU_CTL_MISC_CONFIG_SYNC_WAIT_LEN                    , 5   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SYNC_WAIT_LEN );
+REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_ENABLE                      , 5   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PERF_ENABLE );
+REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_PE_MASK                     , 6   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PERF_PE_MASK );
+REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_PE_MATCH                    , 7   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PERF_PE_MATCH );
+REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_PE_MATCH_LEN                , 4   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PERF_PE_MATCH_LEN );
+REG64_FLD( PU_NPU_CTL_MISC_CONFIG_RSVD                             , 11  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RSVD       );
+REG64_FLD( PU_NPU_CTL_MISC_CONFIG_RSVD_LEN                         , 53  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RSVD_LEN   );
+
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL0_STALL                   , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_NDL0_STALL );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL0_NOSTALL                 , 1   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_NDL0_NOSTALL );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL1_STALL                   , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_NDL1_STALL );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL1_NOSTALL                 , 3   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_NDL1_NOSTALL );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL2_STALL                   , 4   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_NDL2_STALL );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL2_NOSTALL                 , 5   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_NDL2_NOSTALL );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL3_STALL                   , 6   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_NDL3_STALL );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL3_NOSTALL                 , 7   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_NDL3_NOSTALL );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL4_STALL                   , 8   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_NDL4_STALL );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL4_NOSTALL                 , 9   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_NDL4_NOSTALL );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL5_STALL                   , 10  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_NDL5_STALL );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL5_NOSTALL                 , 11  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_NDL5_NOSTALL );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_RING_ERRP                    , 12  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_RING_ERRP );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_IBAR_ERRP                    , 13  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_IBAR_ERRP );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_SCOMDAA_ERRP                 , 14  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_SCOMDAA_ERRP );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_CNTL_ERRP                    , 15  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_CNTL_ERRP );
+REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_MM_LOCAL_XSTOP               , 16  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_MM_LOCAL_XSTOP );
+
+REG64_FLD( PU_NPU_CTL_MISC_MASK_IDIAL                              , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU_CTL_MISC_MASK_IDIAL_LEN                          , 17  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_LN              , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DMA_WR_DISABLE_LN );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_GROUP           , 1   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DMA_WR_DISABLE_GROUP );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_VG_NOT_SYS      , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DMA_WR_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_NN_RN           , 3   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DMA_WR_DISABLE_NN_RN );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_LN              , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DMA_RD_DISABLE_LN );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_GROUP           , 5   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DMA_RD_DISABLE_GROUP );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_VG_NOT_SYS      , 6   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DMA_RD_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_NN_RN           , 7   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DMA_RD_DISABLE_NN_RN );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_CRED_MASK                  , 8   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_LCO_CRED_MASK );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_CRED_MASK_LEN              , 3   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_LCO_CRED_MASK_LEN );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_MIN                   , 11  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_LCO_TARG_MIN );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_MIN_LEN               , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_LCO_TARG_MIN_LEN );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_CONFIG                , 15  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_LCO_TARG_CONFIG );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_CONFIG_LEN            , 12  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_LCO_TARG_CONFIG_LEN );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_UNUSED                         , 27  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_UNUSED_LEN                     , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_NX_FREEZE_MODES                , 31  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NX_FREEZE_MODES );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_NX_FREEZE_MODES_LEN            , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NX_FREEZE_MODES_LEN );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_ADDR_BAR                       , 33  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_BAR   );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_SKIP_G                         , 34  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_SKIP_G     );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_RESERVED                       , 35  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_RESERVED_LEN                   , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_NXCQ_HANG_SM_ON_ARE            , 37  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_HANG_SM_ON_ARE );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_NXCQ_HANG_SM_ON_LINK_FAIL      , 38  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_HANG_SM_ON_LINK_FAIL );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_CFG_PUMP                       , 39  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PUMP   );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK     , 40  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DMA_RD_VG_RESET_TIMER_MASK );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK_LEN , 8   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DMA_RD_VG_RESET_TIMER_MASK_LEN );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK     , 48  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DMA_WR_VG_RESET_TIMER_MASK );
+REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK_LEN , 8   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DMA_WR_VG_RESET_TIMER_MASK_LEN );
+
+REG64_FLD( PEC_STACK2_MMIOBAR0_MASK_REG_PE_MMIO_MASK0              , 0   , SH_UNT_PEC_STACK2, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK0 );
+REG64_FLD( PEC_STACK2_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN          , 40  , SH_UNT_PEC_STACK2, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK0_LEN );
+
+REG64_FLD( PEC_STACK1_MMIOBAR0_MASK_REG_PE_MMIO_MASK0              , 0   , SH_UNT_PEC_STACK1, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK0 );
+REG64_FLD( PEC_STACK1_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN          , 40  , SH_UNT_PEC_STACK1, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK0_LEN );
+
+REG64_FLD( PHB_MMIOBAR0_MASK_REG_PE_MMIO_MASK0                     , 0   , SH_UNT_PHB      , SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK0 );
+REG64_FLD( PHB_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN                 , 40  , SH_UNT_PHB      , SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK0_LEN );
+
+REG64_FLD( PEC_STACK0_MMIOBAR0_MASK_REG_PE_MMIO_MASK0              , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK0 );
+REG64_FLD( PEC_STACK0_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN          , 40  , SH_UNT_PEC_STACK0, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK0_LEN );
+
+REG64_FLD( PEC_STACK2_MMIOBAR0_REG_PE_MMIO_BAR0                    , 0   , SH_UNT_PEC_STACK2, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR0 );
+REG64_FLD( PEC_STACK2_MMIOBAR0_REG_PE_MMIO_BAR0_LEN                , 40  , SH_UNT_PEC_STACK2, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR0_LEN );
+
+REG64_FLD( PEC_STACK1_MMIOBAR0_REG_PE_MMIO_BAR0                    , 0   , SH_UNT_PEC_STACK1, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR0 );
+REG64_FLD( PEC_STACK1_MMIOBAR0_REG_PE_MMIO_BAR0_LEN                , 40  , SH_UNT_PEC_STACK1, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR0_LEN );
+
+REG64_FLD( PHB_MMIOBAR0_REG_PE_MMIO_BAR0                           , 0   , SH_UNT_PHB      , SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR0 );
+REG64_FLD( PHB_MMIOBAR0_REG_PE_MMIO_BAR0_LEN                       , 40  , SH_UNT_PHB      , SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR0_LEN );
+
+REG64_FLD( PEC_STACK0_MMIOBAR0_REG_PE_MMIO_BAR0                    , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR0 );
+REG64_FLD( PEC_STACK0_MMIOBAR0_REG_PE_MMIO_BAR0_LEN                , 40  , SH_UNT_PEC_STACK0, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR0_LEN );
+
+REG64_FLD( PEC_STACK2_MMIOBAR1_MASK_REG_PE_MMIO_MASK1              , 0   , SH_UNT_PEC_STACK2, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK1 );
+REG64_FLD( PEC_STACK2_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN          , 40  , SH_UNT_PEC_STACK2, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK1_LEN );
+
+REG64_FLD( PEC_STACK1_MMIOBAR1_MASK_REG_PE_MMIO_MASK1              , 0   , SH_UNT_PEC_STACK1, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK1 );
+REG64_FLD( PEC_STACK1_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN          , 40  , SH_UNT_PEC_STACK1, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK1_LEN );
+
+REG64_FLD( PHB_MMIOBAR1_MASK_REG_PE_MMIO_MASK1                     , 0   , SH_UNT_PHB      , SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK1 );
+REG64_FLD( PHB_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN                 , 40  , SH_UNT_PHB      , SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK1_LEN );
+
+REG64_FLD( PEC_STACK0_MMIOBAR1_MASK_REG_PE_MMIO_MASK1              , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK1 );
+REG64_FLD( PEC_STACK0_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN          , 40  , SH_UNT_PEC_STACK0, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_MASK1_LEN );
+
+REG64_FLD( PEC_STACK2_MMIOBAR1_REG_PE_MMIO_BAR1                    , 0   , SH_UNT_PEC_STACK2, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR1 );
+REG64_FLD( PEC_STACK2_MMIOBAR1_REG_PE_MMIO_BAR1_LEN                , 40  , SH_UNT_PEC_STACK2, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR1_LEN );
+
+REG64_FLD( PEC_STACK1_MMIOBAR1_REG_PE_MMIO_BAR1                    , 0   , SH_UNT_PEC_STACK1, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR1 );
+REG64_FLD( PEC_STACK1_MMIOBAR1_REG_PE_MMIO_BAR1_LEN                , 40  , SH_UNT_PEC_STACK1, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR1_LEN );
+
+REG64_FLD( PHB_MMIOBAR1_REG_PE_MMIO_BAR1                           , 0   , SH_UNT_PHB      , SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR1 );
+REG64_FLD( PHB_MMIOBAR1_REG_PE_MMIO_BAR1_LEN                       , 40  , SH_UNT_PHB      , SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR1_LEN );
+
+REG64_FLD( PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1                    , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR1 );
+REG64_FLD( PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1_LEN                , 40  , SH_UNT_PEC_STACK0, SH_ACS_SCOM     ,
+           SH_FLD_PE_MMIO_BAR1_LEN );
+
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_BKINV_INTERLOCK_DIS        , 1   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_BKINV_INTERLOCK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_EN             , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DYN_ST_MODE_EN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_HANGP_EN       , 3   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DYN_ST_MODE_HANGP_EN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_LFSR_DIS                   , 8   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_LFSR_DIS   );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_LFSR_DIS               , 9   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_LFSR_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_INV_AMORT_DIS          , 10  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_INV_AMORT_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_DIN_ECC_CHK_DIS        , 12  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_DIN_ECC_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_XLAT_ECC_CHK_DIS       , 13  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_XLAT_ECC_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_XLAT_PROT_ERR_CHK_DIS  , 14  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_XLAT_PROT_ERR_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_XLAT_TIMEOUT_CHK_DIS   , 15  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_XLAT_TIMEOUT_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_CO_PROT_ERR_CHK_DIS        , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CO_PROT_ERR_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_CO_TIMEOUT_CHK_DIS         , 17  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CO_TIMEOUT_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_CKIN_PROT_ERR_CHK_DIS      , 18  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CKIN_PROT_ERR_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_CKIN_TIMEOUT_CHK_DIS       , 19  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CKIN_TIMEOUT_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_INV_PROT_ERR_CHK_DIS       , 20  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_INV_PROT_ERR_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_INV_TIMEOUT_CHK_DIS        , 21  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_INV_TIMEOUT_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_TW_PROT_ERR_CHK_DIS        , 22  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_PROT_ERR_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_TW_TIMEOUT_CHK_DIS         , 23  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_TIMEOUT_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_SNP_PROT_ERR_CHK_DIS   , 24  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_SNP_PROT_ERR_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_SNP_TIMEOUT_CHK_DIS    , 25  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_SNP_TIMEOUT_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_CMD_PROT_ERR_CHK_DIS   , 26  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_CMD_PROT_ERR_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_THRESHOLD      , 28  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DYN_ST_MODE_THRESHOLD );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_THRESHOLD_LEN  , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DYN_ST_MODE_THRESHOLD_LEN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_HANG_PLS_MULT              , 32  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_HANG_PLS_MULT );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_HANG_PLS_MULT_LEN          , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_HANG_PLS_MULT_LEN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_INC_RATE     , 48  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NCU_SNP_TLBIE_INC_RATE );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_INC_RATE_LEN , 8   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NCU_SNP_TLBIE_INC_RATE_LEN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_DEC_RATE     , 56  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NCU_SNP_TLBIE_DEC_RATE );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_DEC_RATE_LEN , 8   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NCU_SNP_TLBIE_DEC_RATE_LEN );
+
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_MBR_DIS                     , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_MBR_DIS    );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_MBR_DIS_LEN                 , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_MBR_DIS_LEN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_SNGL_THD_EN                 , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_SNGL_THD_EN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_CAC_ALLOC_DIS               , 17  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CAC_ALLOC_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DMAP_MODE_EN                , 18  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DMAP_MODE_EN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_ALT_SEGSZ_DIS               , 19  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_ALT_SEGSZ_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DIR_PERR_CHK_DIS            , 20  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DIR_PERR_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_CAC_PERR_CHK_DIS            , 21  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CAC_PERR_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_LRU_PERR_CHK_DIS            , 22  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_LRU_PERR_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS0_STG0_SEL           , 32  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DBG_BUS0_STG0_SEL );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS0_STG0_SEL_LEN       , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DBG_BUS0_STG0_SEL_LEN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS1_STG0_SEL           , 36  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DBG_BUS1_STG0_SEL );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS1_STG0_SEL_LEN       , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DBG_BUS1_STG0_SEL_LEN );
+
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TWSM_DIS                     , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TWSM_DIS   );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TWSM_DIS_LEN                 , 12  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TWSM_DIS_LEN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_CKINSM_DIS                   , 12  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CKINSM_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_CKINSM_DIS_LEN               , 8   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CKINSM_DIS_LEN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_INV_SINGLE_THREAD_EN         , 20  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_INV_SINGLE_THREAD_EN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_CXT_CAC_DIS               , 21  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_CXT_CAC_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_MPSS_DIS                  , 31  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_MPSS_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_CNT_THRESH     , 32  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NCU_SNP_TLBIE_CNT_THRESH );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_CNT_THRESH_LEN , 8   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NCU_SNP_TLBIE_CNT_THRESH_LEN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_HPT_SAO_FOLD_DIS      , 40  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_ATT_HPT_SAO_FOLD_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_RDX_SAO_FOLD_DIS      , 41  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_ATT_RDX_SAO_FOLD_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_RDX_NIO_FOLD_DIS      , 42  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_ATT_RDX_NIO_FOLD_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_RDX_TIO_FOLD_DIS      , 43  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_ATT_RDX_TIO_FOLD_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_EN                , 44  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_LCO_RDX_EN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_P_DIS             , 45  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_LCO_RDX_P_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_C_DIS             , 46  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_LCO_RDX_C_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PWC_L2_DIS        , 47  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_LCO_RDX_PWC_L2_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PWC_L3_DIS        , 48  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_LCO_RDX_PWC_L3_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PWC_L4_DIS        , 49  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_LCO_RDX_PWC_L4_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PDE_EN            , 50  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_LCO_RDX_PDE_EN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_DIS               , 52  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_RDX_PWC_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_INT_PWC_DIS           , 53  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_RDX_INT_PWC_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_INT_TLB_DIS           , 54  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_RDX_INT_TLB_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_SPLIT_EN          , 55  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_RDX_PWC_SPLIT_EN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_VA_HASH           , 56  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_RDX_PWC_VA_HASH );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_PTE_UPD_INTR_EN           , 58  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_PTE_UPD_INTR_EN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_PACING_CNT_EN  , 59  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NCU_SNP_TLBIE_PACING_CNT_EN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_DYN_ST_FREQ_MULT             , 60  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DYN_ST_FREQ_MULT );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_DYN_ST_FREQ_MULT_LEN         , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DYN_ST_FREQ_MULT_LEN );
+
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_MBR_DIS                     , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_MBR_DIS    );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_MBR_DIS_LEN                 , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_MBR_DIS_LEN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_SNGL_THD_EN                 , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_SNGL_THD_EN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_CAC_ALLOC_DIS               , 17  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CAC_ALLOC_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DMAP_MODE_EN                , 18  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DMAP_MODE_EN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_MPSS_DIS                    , 19  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_MPSS_DIS   );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_LPID_DIS               , 20  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_HASH_LPID_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS                , 21  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_HASH_PID_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DIR_PERR_CHK_DIS            , 22  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DIR_PERR_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_CAC_PERR_CHK_DIS            , 23  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CAC_PERR_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_LRU_PERR_CHK_DIS            , 24  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_LRU_PERR_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_MULTIHIT_CHK_DIS            , 25  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_MULTIHIT_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_EA_RANGE_CHK_DIS            , 26  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_EA_RANGE_CHK_DIS );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL           , 32  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DBG_BUS0_STG0_SEL );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL_LEN       , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DBG_BUS0_STG0_SEL_LEN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL           , 36  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DBG_BUS1_STG0_SEL );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL_LEN       , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DBG_BUS1_STG0_SEL_LEN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ             , 40  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_GUEST_PREF_PGSZ );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ_LEN         , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_GUEST_PREF_PGSZ_LEN );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ              , 44  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_HOST_PREF_PGSZ );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ_LEN          , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_HOST_PREF_PGSZ_LEN );
+
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0_HRMOR                 , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_HRMOR      );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0_HRMOR_LEN             , 64  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_HRMOR_LEN  );
+
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG1_PTCR                  , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_PTCR       );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG1_PTCR_LEN              , 64  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_PTCR_LEN   );
+
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG2_SEIDBAR               , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_SEIDBAR    );
+REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG2_SEIDBAR_LEN           , 64  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_SEIDBAR_LEN );
+
+REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_CNT_VAL      , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_WR_TIER_1_CNT_VAL );
+REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_CNT_VAL_LEN  , 12  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_WR_TIER_1_CNT_VAL_LEN );
+REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_DIV_VAL      , 12  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_WR_TIER_1_DIV_VAL );
+REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_DIV_VAL_LEN  , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_WR_TIER_1_DIV_VAL_LEN );
+REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_CNT_VAL      , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_WR_TIER_2_CNT_VAL );
+REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_CNT_VAL_LEN  , 12  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_WR_TIER_2_CNT_VAL_LEN );
+REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_DIV_VAL      , 28  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_WR_TIER_2_DIV_VAL );
+REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_DIV_VAL_LEN  , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_WR_TIER_2_DIV_VAL_LEN );
+REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_DISABLE                , 32  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE    );
+
+REG64_FLD( PU_NMMU_MM_FIR1_ACTION0_REG_ACTION0                     , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( PU_NMMU_MM_FIR1_ACTION0_REG_ACTION0_LEN                 , 48  , SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_NMMU_MM_FIR1_ACTION1_REG_ACTION1                     , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( PU_NMMU_MM_FIR1_ACTION1_REG_ACTION1_LEN                 , 48  , SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_NMMU_MM_FIR1_MASK_REG_MASK                           , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASK       );
+REG64_FLD( PU_NMMU_MM_FIR1_MASK_REG_MASK_LEN                       , 48  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_XLAT_ARY_ECC_CE_DET             , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_FBC_XLAT_ARY_ECC_CE_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_XLAT_ARY_ECC_UE_DET             , 1   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_FBC_XLAT_ARY_ECC_UE_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_XLAT_ARY_ECC_SUE_DET            , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_FBC_XLAT_ARY_ECC_SUE_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_CQRD_ARY_ECC_CE_DET             , 3   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_FBC_CQRD_ARY_ECC_CE_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_CQRD_ARY_ECC_UE_DET             , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_FBC_CQRD_ARY_ECC_UE_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_CQRD_ARY_ECC_SUE_DET            , 5   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_FBC_CQRD_ARY_ECC_SUE_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_XLAT_PROT_ERR_DET               , 6   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_FBC_XLAT_PROT_ERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_XLAT_TIMEOUT_DET                , 7   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_FBC_XLAT_TIMEOUT_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_SLB_DIR_PERR_DET                    , 8   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_SLB_DIR_PERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_SLB_CAC_PERR_DET                    , 9   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_SLB_CAC_PERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_SLB_LRU_PERR_DET                    , 10  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_SLB_LRU_PERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_SLB_MULTIHIT_DET                    , 11  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_SLB_MULTIHIT_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TLB_DIR_PERR_DET                    , 12  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLB_DIR_PERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TLB_CAC_PERR_DET                    , 13  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLB_CAC_PERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TLB_LRU_PERR_DET                    , 14  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLB_LRU_PERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TLB_MULTIHIT_DET                    , 15  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLB_MULTIHIT_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_SEG_FAULT_DET                    , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_SEG_FAULT_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_NOPTE_DET               , 17  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_PG_FAULT_NOPTE_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_BPCHK_DET               , 18  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_PG_FAULT_BPCHK_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_VPCHK_DET               , 19  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_PG_FAULT_VPCHK_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_SEID_DET                , 20  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_PG_FAULT_SEID_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_ADD_ERR_CR_RD_DET                , 21  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_ADD_ERR_CR_RD_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PTE_UPD_FAIL_DET                 , 22  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_PTE_UPD_FAIL_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_ADD_ERR_CR_WR_DET                , 23  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_ADD_ERR_CR_WR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_RDX_CFG_GUEST_DET                , 24  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_RDX_CFG_GUEST_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_RDX_CFG_HOST_DET                 , 25  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_RDX_CFG_HOST_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_INVALID_WIMG_DET                 , 26  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_INVALID_WIMG_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_INV_RDX_QUAD_DET                 , 27  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_INV_RDX_QUAD_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_FOREIGN_ADDR_DET                 , 28  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_FOREIGN_ADDR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PREFETCH_ABT_DET                 , 29  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_PREFETCH_ABT_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_CXT_CAC_PERR_DET                 , 30  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_CXT_CAC_PERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_RDX_PWC_PERR_DET                 , 31  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_RDX_PWC_PERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_SM_CTL_ERR_DET                   , 32  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_SM_CTL_ERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_CO_SM_CTL_ERR_DET                   , 33  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_CO_SM_CTL_ERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_CI_SM_CTL_ERR_DET                   , 34  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_CI_SM_CTL_ERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_INV_SM_CTL_ERR_DET                  , 35  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_INV_SM_CTL_ERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_TIMEOUT_ERR_DET                  , 36  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_TW_TIMEOUT_ERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_CO_TIMEOUT_ERR_DET                  , 37  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_CO_TIMEOUT_ERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_CI_TIMEOUT_ERR_DET                  , 38  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_CI_TIMEOUT_ERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_INV_TIMEOUT_ERR_DET                 , 39  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_INV_TIMEOUT_ERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_NX0_LXSTOP_ERR_DET                  , 40  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_NX0_LXSTOP_ERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_CP0_LXSTOP_ERR_DET                  , 41  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_CP0_LXSTOP_ERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_CP1_LXSTOP_ERR_DET                  , 42  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_CP1_LXSTOP_ERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_NPU_LXSTOP_ERR_DET                  , 43  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_NPU_LXSTOP_ERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_LXSTOP_ERR_DET                  , 44  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_FBC_LXSTOP_ERR_DET );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_SPARE                               , 45  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_SCOM_PE_FIR                         , 46  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PE_FIR );
+REG64_FLD( PU_NMMU_MM_FIR1_REG_SCOM_PE_DUP_FIR                     , 47  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PE_DUP_FIR );
+
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_EN                             , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_EN         );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_PRV_BUS0_STG2_SEL              , 1   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_PRV_BUS0_STG2_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_PRV_BUS1_STG2_SEL              , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_PRV_BUS1_STG2_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG2_SEL              , 3   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_BUS0_STG2_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG2_SEL              , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_BUS1_STG2_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG2_SEL              , 5   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_MSC_BUS0_STG2_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG2_SEL              , 6   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_MSC_BUS1_STG2_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS0_STG2_SEL              , 7   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_SLB_BUS0_STG2_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS1_STG2_SEL              , 8   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_SLB_BUS1_STG2_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG2_SEL               , 9   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_BUS0_STG2_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG2_SEL               , 10  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_BUS1_STG2_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG2_SEL              , 11  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_RDX_BUS0_STG2_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG2_SEL              , 12  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_RDX_BUS1_STG2_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS0_STG2_SEL              , 13  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TLB_BUS0_STG2_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS1_STG2_SEL              , 14  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TLB_BUS1_STG2_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG1_SEL              , 15  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_BUS0_STG1_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG1_SEL              , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_BUS1_STG1_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG1_SEL              , 17  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_MSC_BUS0_STG1_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG1_SEL              , 18  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_MSC_BUS1_STG1_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS0_STG1_SEL              , 19  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_SLB_BUS0_STG1_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS1_STG1_SEL              , 20  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_SLB_BUS1_STG1_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG1_SEL               , 21  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_BUS0_STG1_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG1_SEL               , 22  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_BUS1_STG1_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG1_SEL              , 23  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_RDX_BUS0_STG1_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG1_SEL              , 24  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_RDX_BUS1_STG1_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS0_STG1_SEL              , 25  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TLB_BUS0_STG1_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS1_STG1_SEL              , 26  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TLB_BUS1_STG1_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG0_SEL              , 32  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_BUS0_STG0_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG0_SEL_LEN          , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_BUS0_STG0_SEL_LEN );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG0_SEL              , 36  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_BUS1_STG0_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG0_SEL_LEN          , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_FBC_BUS1_STG0_SEL_LEN );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG0_SEL              , 40  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_MSC_BUS0_STG0_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG0_SEL_LEN          , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_MSC_BUS0_STG0_SEL_LEN );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG0_SEL              , 44  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_MSC_BUS1_STG0_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG0_SEL_LEN          , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_MSC_BUS1_STG0_SEL_LEN );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG0_SEL               , 48  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_BUS0_STG0_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG0_SEL_LEN           , 6   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_BUS0_STG0_SEL_LEN );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG0_SEL               , 54  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_BUS1_STG0_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG0_SEL_LEN           , 6   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_TW_BUS1_STG0_SEL_LEN );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG0_SEL              , 60  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_RDX_BUS0_STG0_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG0_SEL_LEN          , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_RDX_BUS0_STG0_SEL_LEN );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG0_SEL              , 62  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_RDX_BUS1_STG0_SEL );
+REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG0_SEL_LEN          , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_RDX_BUS1_STG0_SEL_LEN );
+
+REG64_FLD( PU_NMMU_MM_NMMU_ERR_INJ_INJ                             , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_INJ        );
+REG64_FLD( PU_NMMU_MM_NMMU_ERR_INJ_INJ_LEN                         , 64  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_INJ_LEN    );
+
+REG64_FLD( PU_NMMU_MM_NMMU_ERR_LOG_LOG                             , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_LOG        );
+REG64_FLD( PU_NMMU_MM_NMMU_ERR_LOG_LOG_LEN                         , 64  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_LOG_LEN    );
+
+REG64_FLD( PEC_MODE_REG_IN0                                        , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( PEC_MODE_REG_IN1                                        , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN1        );
+REG64_FLD( PEC_MODE_REG_IN2                                        , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN2        );
+REG64_FLD( PEC_MODE_REG_IN3                                        , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN3        );
+REG64_FLD( PEC_MODE_REG_IN4                                        , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( PEC_MODE_REG_IN5                                        , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( PEC_MODE_REG_IN6                                        , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN6        );
+REG64_FLD( PEC_MODE_REG_IN7                                        , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN7        );
+REG64_FLD( PEC_MODE_REG_IN8                                        , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN8        );
+REG64_FLD( PEC_MODE_REG_IN9                                        , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN9        );
+REG64_FLD( PEC_MODE_REG_IN10                                       , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN10       );
+REG64_FLD( PEC_MODE_REG_IN11                                       , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN11       );
+REG64_FLD( PEC_MODE_REG_IN                                         , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( PEC_MODE_REG_IN_LEN                                     , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( PU_MODE_REGISTER_DCOMP_ENABLE                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DCOMP_ENABLE );
+REG64_FLD( PU_MODE_REGISTER_ECC_ENABLE                             , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_ENABLE );
+REG64_FLD( PU_MODE_REGISTER_PROGRAM_ENABLE                         , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PROGRAM_ENABLE );
+REG64_FLD( PU_MODE_REGISTER_ECC_CHK_DISABLE                        , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_CHK_DISABLE );
+REG64_FLD( PU_MODE_REGISTER_UNUSED_4_15                            , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_4_15 );
+REG64_FLD( PU_MODE_REGISTER_UNUSED_4_15_LEN                        , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_4_15_LEN );
+REG64_FLD( PU_MODE_REGISTER_CLK_RATE_SEL                           , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CLK_RATE_SEL );
+REG64_FLD( PU_MODE_REGISTER_CLK_RATE_SEL_LEN                       , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CLK_RATE_SEL_LEN );
+
+REG64_FLD( PU_MODE_REGISTER_B_BIT_RATE_DIVISOR_0                   , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BIT_RATE_DIVISOR_0 );
+REG64_FLD( PU_MODE_REGISTER_B_BIT_RATE_DIVISOR_0_LEN               , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BIT_RATE_DIVISOR_0_LEN );
+REG64_FLD( PU_MODE_REGISTER_B_PORT_NUMBER_0                        , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PORT_NUMBER_0 );
+REG64_FLD( PU_MODE_REGISTER_B_PORT_NUMBER_0_LEN                    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PORT_NUMBER_0_LEN );
+REG64_FLD( PU_MODE_REGISTER_B_CHKSW_CMDQUEUEING_0                  , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHKSW_CMDQUEUEING_0 );
+REG64_FLD( PU_MODE_REGISTER_B_CHKSW_I2C_BUSY_0                     , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHKSW_I2C_BUSY_0 );
+REG64_FLD( PU_MODE_REGISTER_B_FGAT_0                               , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FGAT_0     );
+REG64_FLD( PU_MODE_REGISTER_B_DIAG_0                               , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DIAG_0     );
+REG64_FLD( PU_MODE_REGISTER_B_PACING_ALLOW_0                       , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PACING_ALLOW_0 );
+REG64_FLD( PU_MODE_REGISTER_B_WRAP_0                               , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WRAP_0     );
+REG64_FLD( PU_MODE_REGISTER_B_PEEK_DATA1_0                         , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_MODE_REGISTER_B_PEEK_DATA1_0_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_MODE_REGISTER_B_LBUS_PARITY_ERR1_0                   , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_MODE_REGISTER_C_BIT_RATE_DIVISOR_1                   , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BIT_RATE_DIVISOR_1 );
+REG64_FLD( PU_MODE_REGISTER_C_BIT_RATE_DIVISOR_1_LEN               , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BIT_RATE_DIVISOR_1_LEN );
+REG64_FLD( PU_MODE_REGISTER_C_PORT_NUMBER_1                        , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PORT_NUMBER_1 );
+REG64_FLD( PU_MODE_REGISTER_C_PORT_NUMBER_1_LEN                    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PORT_NUMBER_1_LEN );
+REG64_FLD( PU_MODE_REGISTER_C_CHKSW_CMDQUEUEING_1                  , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHKSW_CMDQUEUEING_1 );
+REG64_FLD( PU_MODE_REGISTER_C_CHKSW_I2C_BUSY_1                     , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHKSW_I2C_BUSY_1 );
+REG64_FLD( PU_MODE_REGISTER_C_FGAT_1                               , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FGAT_1     );
+REG64_FLD( PU_MODE_REGISTER_C_DIAG_1                               , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DIAG_1     );
+REG64_FLD( PU_MODE_REGISTER_C_PACING_ALLOW_1                       , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PACING_ALLOW_1 );
+REG64_FLD( PU_MODE_REGISTER_C_WRAP_1                               , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WRAP_1     );
+REG64_FLD( PU_MODE_REGISTER_C_PEEK_DATA1_1                         , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_MODE_REGISTER_C_PEEK_DATA1_1_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_MODE_REGISTER_C_LBUS_PARITY_ERR1_1                   , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_MODE_REGISTER_D_BIT_RATE_DIVISOR_2                   , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BIT_RATE_DIVISOR_2 );
+REG64_FLD( PU_MODE_REGISTER_D_BIT_RATE_DIVISOR_2_LEN               , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BIT_RATE_DIVISOR_2_LEN );
+REG64_FLD( PU_MODE_REGISTER_D_PORT_NUMBER_2                        , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PORT_NUMBER_2 );
+REG64_FLD( PU_MODE_REGISTER_D_PORT_NUMBER_2_LEN                    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PORT_NUMBER_2_LEN );
+REG64_FLD( PU_MODE_REGISTER_D_CHKSW_CMDQUEUEING_2                  , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHKSW_CMDQUEUEING_2 );
+REG64_FLD( PU_MODE_REGISTER_D_CHKSW_I2C_BUSY_2                     , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHKSW_I2C_BUSY_2 );
+REG64_FLD( PU_MODE_REGISTER_D_FGAT_2                               , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FGAT_2     );
+REG64_FLD( PU_MODE_REGISTER_D_DIAG_2                               , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DIAG_2     );
+REG64_FLD( PU_MODE_REGISTER_D_PACING_ALLOW_2                       , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PACING_ALLOW_2 );
+REG64_FLD( PU_MODE_REGISTER_D_WRAP_2                               , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WRAP_2     );
+REG64_FLD( PU_MODE_REGISTER_D_PEEK_DATA1_2                         , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_MODE_REGISTER_D_PEEK_DATA1_2_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_MODE_REGISTER_D_LBUS_PARITY_ERR1_2                   , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_MODE_REGISTER_E_BIT_RATE_DIVISOR_3                   , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BIT_RATE_DIVISOR_3 );
+REG64_FLD( PU_MODE_REGISTER_E_BIT_RATE_DIVISOR_3_LEN               , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BIT_RATE_DIVISOR_3_LEN );
+REG64_FLD( PU_MODE_REGISTER_E_PORT_NUMBER_3                        , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PORT_NUMBER_3 );
+REG64_FLD( PU_MODE_REGISTER_E_PORT_NUMBER_3_LEN                    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PORT_NUMBER_3_LEN );
+REG64_FLD( PU_MODE_REGISTER_E_CHKSW_CMDQUEUEING_3                  , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHKSW_CMDQUEUEING_3 );
+REG64_FLD( PU_MODE_REGISTER_E_CHKSW_I2C_BUSY_3                     , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHKSW_I2C_BUSY_3 );
+REG64_FLD( PU_MODE_REGISTER_E_FGAT_3                               , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FGAT_3     );
+REG64_FLD( PU_MODE_REGISTER_E_DIAG_3                               , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DIAG_3     );
+REG64_FLD( PU_MODE_REGISTER_E_PACING_ALLOW_3                       , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PACING_ALLOW_3 );
+REG64_FLD( PU_MODE_REGISTER_E_WRAP_3                               , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WRAP_3     );
+REG64_FLD( PU_MODE_REGISTER_E_PEEK_DATA1_3                         , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_MODE_REGISTER_E_PEEK_DATA1_3_LEN                     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_MODE_REGISTER_E_LBUS_PARITY_ERR1_3                   , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PEC_MULTICAST_GROUP_1_MULTICAST1                        , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST1 );
+REG64_FLD( PEC_MULTICAST_GROUP_1_MULTICAST1_LEN                    , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST1_LEN );
+
+REG64_FLD( PEC_MULTICAST_GROUP_2_MULTICAST2                        , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST2 );
+REG64_FLD( PEC_MULTICAST_GROUP_2_MULTICAST2_LEN                    , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST2_LEN );
+
+REG64_FLD( PEC_MULTICAST_GROUP_3_MULTICAST3                        , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST3 );
+REG64_FLD( PEC_MULTICAST_GROUP_3_MULTICAST3_LEN                    , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST3_LEN );
+
+REG64_FLD( PEC_MULTICAST_GROUP_4_MULTICAST4                        , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST4 );
+REG64_FLD( PEC_MULTICAST_GROUP_4_MULTICAST4_LEN                    , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST4_LEN );
+
+REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM0_NDT0_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_NDT0_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM0_NDT0_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM2_NDT0_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_NDT0_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM2_NDT0_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM3_NDT0_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_NDT0_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM3_NDT0_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM3_NDT0_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_NDT0_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM3_NDT0_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM3_NDT0_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_NDT0_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM3_NDT0_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM1_NDT0_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_NDT0_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM1_NDT0_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM2_NDT0_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_NDT0_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM2_NDT0_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM1_NDT0_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_NDT0_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM1_NDT0_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM2_NDT0_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_NDT0_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM2_NDT0_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM0_NDT0_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_NDT0_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM0_NDT0_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM1_NDT0_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_NDT0_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM1_NDT0_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM0_NDT0_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_NDT0_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM0_NDT0_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM0_NDT1_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_NDT1_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM0_NDT1_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM2_NDT1_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_NDT1_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM2_NDT1_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM3_NDT1_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_NDT1_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM3_NDT1_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM3_NDT1_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_NDT1_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM3_NDT1_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM3_NDT1_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_NDT1_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM3_NDT1_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM1_NDT1_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_NDT1_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM1_NDT1_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM2_NDT1_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_NDT1_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM2_NDT1_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM1_NDT1_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_NDT1_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM1_NDT1_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM2_NDT1_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_NDT1_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM2_NDT1_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM0_NDT1_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_NDT1_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM0_NDT1_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM1_NDT1_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_NDT1_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM1_NDT1_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ENABLE                      , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM0_NDT1_BAR_RESERVED1                          , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_NDT1_BAR_RESERVED1_LEN                      , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_GROUP                       , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_GROUP_LEN                   , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_CHIP                        , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_CHIP_LEN                    , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ADDR                        , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ADDR_LEN                    , 25  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM0_NDT1_BAR_RESERVED2                          , 35  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PEC_STACK0_NET_CTRL0_CHIPLET_ENABLE                     , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_CHIPLET_ENABLE );
+REG64_FLD( PEC_STACK0_NET_CTRL0_PCB_EP_RESET                       , 1   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_PCB_EP_RESET );
+REG64_FLD( PEC_STACK0_NET_CTRL0_CLK_ASYNC_RESET                    , 2   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_ASYNC_RESET );
+REG64_FLD( PEC_STACK0_NET_CTRL0_PLL_TEST_EN                        , 3   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_TEST_EN );
+REG64_FLD( PEC_STACK0_NET_CTRL0_PLL_RESET                          , 4   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_RESET  );
+REG64_FLD( PEC_STACK0_NET_CTRL0_PLL_BYPASS                         , 5   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_BYPASS );
+REG64_FLD( PEC_STACK0_NET_CTRL0_VITAL_SCAN                         , 6   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_SCAN );
+REG64_FLD( PEC_STACK0_NET_CTRL0_VITAL_SCAN_IN                      , 7   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_SCAN_IN );
+REG64_FLD( PEC_STACK0_NET_CTRL0_VITAL_PHASE                        , 8   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_PHASE );
+REG64_FLD( PEC_STACK0_NET_CTRL0_FLUSH_ALIGN_OVR                    , 9   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_FLUSH_ALIGN_OVR );
+REG64_FLD( PEC_STACK0_NET_CTRL0_VITAL_AL                           , 10  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_AL   );
+REG64_FLD( PEC_STACK0_NET_CTRL0_ACT_DIS                            , 11  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_ACT_DIS    );
+REG64_FLD( PEC_STACK0_NET_CTRL0_MPW1                               , 12  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_MPW1       );
+REG64_FLD( PEC_STACK0_NET_CTRL0_MPW2                               , 13  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_MPW2       );
+REG64_FLD( PEC_STACK0_NET_CTRL0_MPW3                               , 14  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_MPW3       );
+REG64_FLD( PEC_STACK0_NET_CTRL0_DELAY_LCLKR                        , 15  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_DELAY_LCLKR );
+REG64_FLD( PEC_STACK0_NET_CTRL0_VITAL_THOLD                        , 16  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_THOLD );
+REG64_FLD( PEC_STACK0_NET_CTRL0_FLUSH_SCAN_N                       , 17  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_FLUSH_SCAN_N );
+REG64_FLD( PEC_STACK0_NET_CTRL0_FENCE_EN                           , 18  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_FENCE_EN   );
+REG64_FLD( PEC_STACK0_NET_CTRL0_CPLT_RCTRL                         , 19  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_CPLT_RCTRL );
+REG64_FLD( PEC_STACK0_NET_CTRL0_CPLT_DCTRL                         , 20  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_CPLT_DCTRL );
+REG64_FLD( PEC_STACK0_NET_CTRL0_L3_EDRAM_ENABLE0                   , 23  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_L3_EDRAM_ENABLE0 );
+REG64_FLD( PEC_STACK0_NET_CTRL0_L3_EDRAM_ENABLE1                   , 24  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_L3_EDRAM_ENABLE1 );
+REG64_FLD( PEC_STACK0_NET_CTRL0_TP_FENCE_PCB                       , 25  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_TP_FENCE_PCB );
+REG64_FLD( PEC_STACK0_NET_CTRL0_LVLTRANS_FENCE                     , 26  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_LVLTRANS_FENCE );
+REG64_FLD( PEC_STACK0_NET_CTRL0_ARRAY_WRITE_ASSIST_EN              , 27  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_ARRAY_WRITE_ASSIST_EN );
+REG64_FLD( PEC_STACK0_NET_CTRL0_HTB_INTEST                         , 28  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_HTB_INTEST );
+REG64_FLD( PEC_STACK0_NET_CTRL0_HTB_EXTEST                         , 29  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_HTB_EXTEST );
+REG64_FLD( PEC_STACK0_NET_CTRL0_PLLFORCE_OUT_EN                    , 31  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_PLLFORCE_OUT_EN );
+
+REG64_FLD( PEC_STACK0_NET_CTRL1_PLL_CLKIN_SEL                      , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_CLKIN_SEL );
+REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_DCC_BYPASS_EN                  , 1   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_DCC_BYPASS_EN );
+REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PDLY_BYPASS_EN                 , 2   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PDLY_BYPASS_EN );
+REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_DIV_BYPASS_EN                  , 3   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_DIV_BYPASS_EN );
+REG64_FLD( PEC_STACK0_NET_CTRL1_REFCLK_CLKMUX0_SEL                 , 4   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_REFCLK_CLKMUX0_SEL );
+REG64_FLD( PEC_STACK0_NET_CTRL1_REFCLK_CLKMUX1_SEL                 , 5   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_REFCLK_CLKMUX1_SEL );
+REG64_FLD( PEC_STACK0_NET_CTRL1_PLL_BNDY_BYPASS_EN                 , 6   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_BNDY_BYPASS_EN );
+REG64_FLD( PEC_STACK0_NET_CTRL1_DPLL_TEST_SEL                      , 8   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_DPLL_TEST_SEL );
+REG64_FLD( PEC_STACK0_NET_CTRL1_DPLL_TEST_SEL_LEN                  , 8   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_DPLL_TEST_SEL_LEN );
+REG64_FLD( PEC_STACK0_NET_CTRL1_SB_STRENGTH                        , 16  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_SB_STRENGTH );
+REG64_FLD( PEC_STACK0_NET_CTRL1_SB_STRENGTH_LEN                    , 4   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_SB_STRENGTH_LEN );
+REG64_FLD( PEC_STACK0_NET_CTRL1_ASYNC_TYPE                         , 20  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_ASYNC_TYPE );
+REG64_FLD( PEC_STACK0_NET_CTRL1_ASYNC_OBS                          , 21  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_ASYNC_OBS  );
+REG64_FLD( PEC_STACK0_NET_CTRL1_CPM_CAL_SET                        , 22  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_CPM_CAL_SET );
+REG64_FLD( PEC_STACK0_NET_CTRL1_SENSEADJ_RESET0                    , 23  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_SENSEADJ_RESET0 );
+REG64_FLD( PEC_STACK0_NET_CTRL1_SENSEADJ_RESET1                    , 24  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_SENSEADJ_RESET1 );
+REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PULSE_EN                       , 25  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PULSE_EN );
+REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PULSE_MODE                     , 26  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PULSE_MODE );
+REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PULSE_MODE_LEN                 , 2   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PULSE_MODE_LEN );
+
+REG64_FLD( PEC_STACK2_NFIRACTION0_REG_NFIRACTION0                  , 0   , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION0 );
+REG64_FLD( PEC_STACK2_NFIRACTION0_REG_NFIRACTION0_LEN              , 30  , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION0_LEN );
+
+REG64_FLD( PEC_STACK1_NFIRACTION0_REG_NFIRACTION0                  , 0   , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION0 );
+REG64_FLD( PEC_STACK1_NFIRACTION0_REG_NFIRACTION0_LEN              , 30  , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION0_LEN );
+
+REG64_FLD( PHB_NFIRACTION0_REG_NFIRACTION0                         , 0   , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION0 );
+REG64_FLD( PHB_NFIRACTION0_REG_NFIRACTION0_LEN                     , 30  , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION0_LEN );
+
+REG64_FLD( PEC_STACK0_NFIRACTION0_REG_NFIRACTION0                  , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION0 );
+REG64_FLD( PEC_STACK0_NFIRACTION0_REG_NFIRACTION0_LEN              , 30  , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION0_LEN );
+
+REG64_FLD( PEC_STACK2_NFIRACTION1_REG_NFIRACTION1                  , 0   , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION1 );
+REG64_FLD( PEC_STACK2_NFIRACTION1_REG_NFIRACTION1_LEN              , 30  , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION1_LEN );
+
+REG64_FLD( PEC_STACK1_NFIRACTION1_REG_NFIRACTION1                  , 0   , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION1 );
+REG64_FLD( PEC_STACK1_NFIRACTION1_REG_NFIRACTION1_LEN              , 30  , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION1_LEN );
+
+REG64_FLD( PHB_NFIRACTION1_REG_NFIRACTION1                         , 0   , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION1 );
+REG64_FLD( PHB_NFIRACTION1_REG_NFIRACTION1_LEN                     , 30  , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION1_LEN );
+
+REG64_FLD( PEC_STACK0_NFIRACTION1_REG_NFIRACTION1                  , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION1 );
+REG64_FLD( PEC_STACK0_NFIRACTION1_REG_NFIRACTION1_LEN              , 30  , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  ,
+           SH_FLD_NFIRACTION1_LEN );
+
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_NFIRMASK                        , 0   , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRMASK   );
+REG64_FLD( PEC_STACK2_NFIRMASK_REG_NFIRMASK_LEN                    , 30  , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRMASK_LEN );
+
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_NFIRMASK                        , 0   , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRMASK   );
+REG64_FLD( PEC_STACK1_NFIRMASK_REG_NFIRMASK_LEN                    , 30  , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRMASK_LEN );
+
+REG64_FLD( PHB_NFIRMASK_REG_NFIRMASK                               , 0   , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRMASK   );
+REG64_FLD( PHB_NFIRMASK_REG_NFIRMASK_LEN                           , 30  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRMASK_LEN );
+
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_NFIRMASK                        , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRMASK   );
+REG64_FLD( PEC_STACK0_NFIRMASK_REG_NFIRMASK_LEN                    , 30  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRMASK_LEN );
+
+REG64_FLD( PEC_STACK2_NFIR_REG_NFIRNFIR                            , 0   , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRNFIR   );
+REG64_FLD( PEC_STACK2_NFIR_REG_NFIRNFIR_LEN                        , 30  , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRNFIR_LEN );
+
+REG64_FLD( PEC_STACK1_NFIR_REG_NFIRNFIR                            , 0   , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRNFIR   );
+REG64_FLD( PEC_STACK1_NFIR_REG_NFIRNFIR_LEN                        , 30  , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRNFIR_LEN );
+
+REG64_FLD( PHB_NFIR_REG_NFIRNFIR                                   , 0   , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRNFIR   );
+REG64_FLD( PHB_NFIR_REG_NFIRNFIR_LEN                               , 30  , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRNFIR_LEN );
+
+REG64_FLD( PEC_STACK0_NFIR_REG_NFIRNFIR                            , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRNFIR   );
+REG64_FLD( PEC_STACK0_NFIR_REG_NFIRNFIR_LEN                        , 30  , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR ,
+           SH_FLD_NFIRNFIR_LEN );
+
+REG64_FLD( PU_NOTRUST_BAR0_UNTRUSTED                               , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNTRUSTED  );
+REG64_FLD( PU_NOTRUST_BAR0_UNTRUSTED_LEN                           , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNTRUSTED_LEN );
+
+REG64_FLD( PU_NOTRUST_BAR0MASK_UNTRUSTED                           , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNTRUSTED  );
+REG64_FLD( PU_NOTRUST_BAR0MASK_UNTRUSTED_LEN                       , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNTRUSTED_LEN );
+
+REG64_FLD( PU_NOTRUST_BAR1_UNTRUSTED                               , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNTRUSTED  );
+REG64_FLD( PU_NOTRUST_BAR1_UNTRUSTED_LEN                           , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNTRUSTED_LEN );
+
+REG64_FLD( PU_NOTRUST_BAR1MASK_UNTRUSTED                           , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNTRUSTED  );
+REG64_FLD( PU_NOTRUST_BAR1MASK_UNTRUSTED_LEN                       , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNTRUSTED_LEN );
+
+REG64_FLD( PU_NPU_SM0_NPU_ATS_DEBUG_ENABLE                         , 0   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU_SM0_NPU_ATS_DEBUG_0_SELECT                       , 1   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_0_SELECT   );
+REG64_FLD( PU_NPU_SM0_NPU_ATS_DEBUG_0_SELECT_LEN                   , 3   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_0_SELECT_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_ATS_DEBUG_1_SELECT                       , 4   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_1_SELECT   );
+REG64_FLD( PU_NPU_SM0_NPU_ATS_DEBUG_1_SELECT_LEN                   , 3   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_1_SELECT_LEN );
+
+REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_INJECT_MODE                       , 0   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_INJECT_MODE );
+REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_INJECT_MODE_LEN                   , 2   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_INJECT_MODE_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_INJECT_TYPE                       , 2   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_INJECT_TYPE );
+REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_INJECT_TYPE_LEN                   , 2   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_INJECT_TYPE_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_INJECT_ENABLE                     , 4   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_INJECT_ENABLE );
+REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_ARRAY_SELECT                      , 5   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_ARRAY_SELECT );
+REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_ARRAY_SELECT_LEN                  , 4   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_ARRAY_SELECT_LEN );
+
+REG64_FLD( PU_NPU_SM1_NPU_AT_ESMR_IDIAL_ATS_ESR_MSK                , 0   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_IDIAL_ATS_ESR_MSK );
+REG64_FLD( PU_NPU_SM1_NPU_AT_ESMR_IDIAL_ATS_ESR_MSK_LEN            , 20  , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_IDIAL_ATS_ESR_MSK_LEN );
+
+REG64_FLD( PU_NPU_SM1_NPU_AT_ESR_IDIAL_ATS                         , 0   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_IDIAL_ATS  );
+REG64_FLD( PU_NPU_SM1_NPU_AT_ESR_IDIAL_ATS_LEN                     , 20  , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_IDIAL_ATS_LEN );
+
+REG64_FLD( PU_NPU_SM1_NPU_AT_FESMR_IDIAL_ATS_FER_MSK               , 0   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_IDIAL_ATS_FER_MSK );
+REG64_FLD( PU_NPU_SM1_NPU_AT_FESMR_IDIAL_ATS_FER_MSK_LEN           , 20  , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_IDIAL_ATS_FER_MSK_LEN );
+
+REG64_FLD( PU_NPU_SM1_NPU_AT_FESR_FIRST_ERROR_CAPTURED             , 0   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_FIRST_ERROR_CAPTURED );
+REG64_FLD( PU_NPU_SM1_NPU_AT_FESR_FIRST_ERROR_SPARE                , 1   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_FIRST_ERROR_SPARE );
+REG64_FLD( PU_NPU_SM1_NPU_AT_FESR_FIRST_ERROR_SPARE_LEN            , 2   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_FIRST_ERROR_SPARE_LEN );
+REG64_FLD( PU_NPU_SM1_NPU_AT_FESR_FIRST_ERROR_DECODE               , 3   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_FIRST_ERROR_DECODE );
+REG64_FLD( PU_NPU_SM1_NPU_AT_FESR_FIRST_ERROR_DECODE_LEN           , 5   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_FIRST_ERROR_DECODE_LEN );
+REG64_FLD( PU_NPU_SM1_NPU_AT_FESR_FIRST_ERROR_INFO                 , 8   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_FIRST_ERROR_INFO );
+REG64_FLD( PU_NPU_SM1_NPU_AT_FESR_FIRST_ERROR_INFO_LEN             , 56  , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW  ,
+           SH_FLD_FIRST_ERROR_INFO_LEN );
+
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT0                          , 0   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO  ,
+           SH_FLD_CNT0       );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT0_LEN                      , 16  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO  ,
+           SH_FLD_CNT0_LEN   );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT1                          , 16  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO  ,
+           SH_FLD_CNT1       );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT1_LEN                      , 16  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO  ,
+           SH_FLD_CNT1_LEN   );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT2                          , 32  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO  ,
+           SH_FLD_CNT2       );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT2_LEN                      , 16  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO  ,
+           SH_FLD_CNT2_LEN   );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT3                          , 48  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO  ,
+           SH_FLD_CNT3       );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT3_LEN                      , 16  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO  ,
+           SH_FLD_CNT3_LEN   );
+
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_ENABLE           , 0   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_ENABLE );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_RESETMODE        , 1   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_RESETMODE );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_FREEZEMODE       , 2   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_FREEZEMODE );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_DISABLE_PMISC    , 3   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_DISABLE_PMISC );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PMISC_MODE       , 4   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_PMISC_MODE );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_CASCADE          , 5   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_CASCADE );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_CASCADE_LEN      , 3   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_CASCADE_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C0      , 8   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_PRESCALE_C0 );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C0_LEN  , 2   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_PRESCALE_C0_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C1      , 10  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_PRESCALE_C1 );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C1_LEN  , 2   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_PRESCALE_C1_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C2      , 12  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_PRESCALE_C2 );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C2_LEN  , 2   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_PRESCALE_C2_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C3      , 14  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_PRESCALE_C3 );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C3_LEN  , 2   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_PRESCALE_C3_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C0     , 16  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_OPERATION_C0 );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C0_LEN , 2   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_OPERATION_C0_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C1     , 18  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_OPERATION_C1 );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C1_LEN , 2   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_OPERATION_C1_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C2     , 20  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_OPERATION_C2 );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C2_LEN , 2   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_OPERATION_C2_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C3     , 22  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_OPERATION_C3 );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C3_LEN , 2   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_OPERATION_C3_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_EVENTS           , 24  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_EVENTS );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_EVENTS_LEN       , 3   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_EVENTS_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH0                , 27  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PE_MATCH0 );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH0_LEN            , 5   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PE_MATCH0_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH1                , 32  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PE_MATCH1 );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH1_LEN            , 5   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PE_MATCH1_LEN );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_SPARE            , 37  , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_SPARE );
+REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_SPARE_LEN        , 5   , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PERF_CONFIG_SPARE_LEN );
+
+REG64_FLD( PU_NPU_SM1_NPU_Q_DMA_R_QUIESCE                          , 0   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_QUIESCE    );
+REG64_FLD( PU_NPU_SM1_NPU_Q_DMA_R_QUIESCE_AUTO_RESET               , 1   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_QUIESCE_AUTO_RESET );
+REG64_FLD( PU_NPU_SM1_NPU_Q_DMA_R_RESPONSE                         , 4   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESPONSE   );
+REG64_FLD( PU_NPU_SM1_NPU_Q_DMA_R_TCE_RESPONSE                     , 6   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_TCE_RESPONSE );
+
+REG64_FLD( PU_NPU_CTL_NPU_VERSION_RSVD0                            , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RSVD0      );
+REG64_FLD( PU_NPU_CTL_NPU_VERSION_RSVD0_LEN                        , 24  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RSVD0_LEN  );
+REG64_FLD( PU_NPU_CTL_NPU_VERSION_MAJOR                            , 24  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MAJOR      );
+REG64_FLD( PU_NPU_CTL_NPU_VERSION_MAJOR_LEN                        , 8   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MAJOR_LEN  );
+REG64_FLD( PU_NPU_CTL_NPU_VERSION_RSVD1                            , 32  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RSVD1      );
+REG64_FLD( PU_NPU_CTL_NPU_VERSION_RSVD1_LEN                        , 16  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RSVD1_LEN  );
+REG64_FLD( PU_NPU_CTL_NPU_VERSION_MINOR                            , 48  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MINOR      );
+REG64_FLD( PU_NPU_CTL_NPU_VERSION_MINOR_LEN                        , 16  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_MINOR_LEN  );
+
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_LN                   , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_WR_DISABLE_LN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_GROUP                , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_WR_DISABLE_GROUP );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_VG_NOT_SYS           , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_WR_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_NN_RN                , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_WR_DISABLE_NN_RN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_LN                   , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_RD_DISABLE_LN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_GROUP                , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_RD_DISABLE_GROUP );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_VG_NOT_SYS           , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_RD_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_NN_RN                , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_RD_DISABLE_NN_RN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_LN                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UMAC_WR_DISABLE_LN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_GROUP               , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UMAC_WR_DISABLE_GROUP );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_VG_NOT_SYS          , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UMAC_WR_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_NN_RN               , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UMAC_WR_DISABLE_NN_RN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_LN                  , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UMAC_RD_DISABLE_LN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_GROUP               , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UMAC_RD_DISABLE_GROUP );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_VG_NOT_SYS          , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UMAC_RD_DISABLE_VG_NOT_SYS );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_NN_RN               , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UMAC_RD_DISABLE_NN_RN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_NX_FREEZE_MODES                     , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NX_FREEZE_MODES );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_NX_FREEZE_MODES_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NX_FREEZE_MODES_LEN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_RESERVED                            , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_RESERVED_LEN                        , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_NOT_INJECT                   , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_WR_NOT_INJECT );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_PARTIAL_WRT_NOT_INJECT          , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_PARTIAL_WRT_NOT_INJECT );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_RD_GO_M_QOS                         , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RD_GO_M_QOS );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_ADDR_BAR                            , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_BAR   );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_SKIP_G                              , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SKIP_G     );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DATA_ARB_LFSR_CONFIG                , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_ARB_LFSR_CONFIG );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DATA_ARB_LFSR_CONFIG_LEN            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_ARB_LFSR_CONFIG_LEN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_HANG_SM_ON_ARE                      , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HANG_SM_ON_ARE );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_HANG_SM_ON_LINK_FAIL                , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HANG_SM_ON_LINK_FAIL );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_CFG_PUMP                            , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PUMP   );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DISABLE_FLOW_SCOPE                  , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_FLOW_SCOPE );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DISABLE_PMU_SNOOPING                , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_PMU_SNOOPING );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_ENDABLE_PMU_CNT_RESET               , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENDABLE_PMU_CNT_RESET );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DISABLE_WRP                         , 33  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_WRP );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UNUSED                              , 34  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_UNUSED_LEN                          , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK          , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_RD_VG_RESET_TIMER_MASK );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK_LEN      , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_RD_VG_RESET_TIMER_MASK_LEN );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK          , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_WR_VG_RESET_TIMER_MASK );
+REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK_LEN      , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_WR_VG_RESET_TIMER_MASK_LEN );
+
+REG64_FLD( PU_NMMU_NX_CQ_FIR_ACTION0_REG_ACTION0                   , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_ACTION0_REG_ACTION0_LEN               , 22  , SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_NX_CQ_FIR_ACTION0_REG_ACTION0                        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( PU_NX_CQ_FIR_ACTION0_REG_ACTION0_LEN                    , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_NMMU_NX_CQ_FIR_ACTION1_REG_ACTION1                   , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_ACTION1_REG_ACTION1_LEN               , 21  , SH_UNT_PU_NMMU  , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_NX_CQ_FIR_ACTION1_REG_ACTION1                        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( PU_NX_CQ_FIR_ACTION1_REG_ACTION1_LEN                    , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_NMMU_NX_CQ_FIR_MASK_REG_MASK                         , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASK       );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_MASK_REG_MASK_LEN                     , 22  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( PU_NX_CQ_FIR_MASK_REG_MASK                              , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASK       );
+REG64_FLD( PU_NX_CQ_FIR_MASK_REG_MASK_LEN                          , 44  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBI_PE                            , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBI_PE     );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_CMD_HANG                     , 1   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_CMD_HANG );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_READ_ARE                     , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_READ_ARE );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_WRITE_ARE                    , 3   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_WRITE_ARE );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_MISC_HW                      , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_MISC_HW );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_RSVD                              , 5   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSVD       );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_XLAT_ECC_UE                  , 6   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_XLAT_ECC_UE );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_XLAT_ECC_SUE                 , 7   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_XLAT_ECC_SUE );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_ECC_CE                       , 8   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_ECC_CE );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_ECC_UE                       , 9   , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_ECC_UE );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_ECC_SUE                      , 10  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_ECC_SUE );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_INBD_LCO_ARRAY_ECC_CE             , 11  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_INBD_LCO_ARRAY_ECC_CE );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_INBD_LCO_ARRAY_ECC_UE             , 12  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_INBD_LCO_ARRAY_ECC_UE );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_INBD_LCO_ARRAY_ECC_SUE            , 13  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_INBD_LCO_ARRAY_ECC_SUE );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_CE                 , 14  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_INBD_ARRAY_ECC_CE );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_UE                 , 15  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_INBD_ARRAY_ECC_UE );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_INT_STATE_ERR                     , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_INT_STATE_ERR );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_LOAD_LINK_ERR                , 17  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_LOAD_LINK_ERR );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_STORE_LINK_ERR               , 18  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_STORE_LINK_ERR );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_LINK_ABORT                   , 19  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_LINK_ABORT );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_SCOM_PE                           , 20  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PE    );
+REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_SCOM_PE_DUP                       , 21  , SH_UNT_PU_NMMU  , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PE_DUP );
+
+REG64_FLD( PU_NX_CQ_FIR_REG_PBI_PE                                 , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBI_PE     );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_ECC_CE                            , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_ECC_CE );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_ECC_UE                            , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_ECC_UE );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_ECC_SUE                           , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_ECC_SUE );
+REG64_FLD( PU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_CE                      , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INBD_ARRAY_ECC_CE );
+REG64_FLD( PU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_UE                      , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INBD_ARRAY_ECC_UE );
+REG64_FLD( PU_NX_CQ_FIR_REG_PASTE_REJECT                           , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PASTE_REJECT );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_CMD_HANG                          , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_CMD_HANG );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_READ_ARE                          , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_READ_ARE );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_WRITE_ARE                         , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_WRITE_ARE );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_MISC_HW                           , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_MISC_HW );
+REG64_FLD( PU_NX_CQ_FIR_REG_MMIO_BAR_PE                            , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MMIO_BAR_PE );
+REG64_FLD( PU_NX_CQ_FIR_REG_UMAC_WC_INT_ADDR_UE                    , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UMAC_WC_INT_ADDR_UE );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_LOAD_LINK_ERR                     , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_LOAD_LINK_ERR );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_STORE_LINK_ERR                    , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_STORE_LINK_ERR );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_LINK_ABORT                        , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBUS_LINK_ABORT );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBI_INTERNAL_HANG                      , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBI_INTERNAL_HANG );
+REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_ARRAY_PE                          , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ERAT_ARRAY_PE );
+REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_ARRAY_CE                          , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ERAT_ARRAY_CE );
+REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_ARRAY_UE                          , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ERAT_ARRAY_UE );
+REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_ARRAY_SUE                         , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ERAT_ARRAY_SUE );
+REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_CICO_HANG                         , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ERAT_CICO_HANG );
+REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_CNTRL_ERR                         , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ERAT_CNTRL_ERR );
+REG64_FLD( PU_NX_CQ_FIR_REG_PB_XLAT_DATA_UE                        , 23  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_XLAT_DATA_UE );
+REG64_FLD( PU_NX_CQ_FIR_REG_PB_XLAT_DATA_SUE                       , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_XLAT_DATA_SUE );
+REG64_FLD( PU_NX_CQ_FIR_REG_UMAC_LD_LINK_ERR                       , 25  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UMAC_LD_LINK_ERR );
+REG64_FLD( PU_NX_CQ_FIR_REG_UMAC_LINK_ABORT                        , 26  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UMAC_LINK_ABORT );
+REG64_FLD( PU_NX_CQ_FIR_REG_UMAC_CRB_UE                            , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UMAC_CRB_UE );
+REG64_FLD( PU_NX_CQ_FIR_REG_UMAC_CRB_SUE                           , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UMAC_CRB_SUE );
+REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_LOCAL_CSTOP                       , 29  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ERAT_LOCAL_CSTOP );
+REG64_FLD( PU_NX_CQ_FIR_REG_RNG_FIRST_FAIL                         , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RNG_FIRST_FAIL );
+REG64_FLD( PU_NX_CQ_FIR_REG_RNG_SECOND_FAIL                        , 33  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RNG_SECOND_FAIL );
+REG64_FLD( PU_NX_CQ_FIR_REG_RNG_CNTRL_LOGIC_ERR                    , 34  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RNG_CNTRL_LOGIC_ERR );
+REG64_FLD( PU_NX_CQ_FIR_REG_NMMU_LOCAL_XSTOP                       , 35  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_NMMU_LOCAL_XSTOP );
+REG64_FLD( PU_NX_CQ_FIR_REG_VAS_LOCAL_XSTOP                        , 36  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_VAS_LOCAL_XSTOP );
+REG64_FLD( PU_NX_CQ_FIR_REG_PBCQ_CNTRL_LOGIC_ERR                   , 37  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBCQ_CNTRL_LOGIC_ERR );
+REG64_FLD( PU_NX_CQ_FIR_REG_FAILED_LINK_ON_INTERRUPT               , 38  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FAILED_LINK_ON_INTERRUPT );
+REG64_FLD( PU_NX_CQ_FIR_REG_SCOM_PE                                , 42  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PE    );
+REG64_FLD( PU_NX_CQ_FIR_REG_SCOM_PE_DUP                            , 43  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PE_DUP );
+
+REG64_FLD( PU_NX_DEBUGMUX_CTRL_BITS                                , 47  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NX_DEBUGMUX_CTRL_BITS_LEN                            , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NMMU_NX_DEBUG_SNAPSHOT_0_B0_63                       , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_B0_63      );
+REG64_FLD( PU_NMMU_NX_DEBUG_SNAPSHOT_0_B0_63_LEN                   , 64  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_B0_63_LEN  );
+
+REG64_FLD( PU_NX_DEBUG_SNAPSHOT_0_B0_63                            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_B0_63      );
+REG64_FLD( PU_NX_DEBUG_SNAPSHOT_0_B0_63_LEN                        , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_B0_63_LEN  );
+
+REG64_FLD( PU_NMMU_NX_DEBUG_SNAPSHOT_1_B64_87                      , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_B64_87     );
+REG64_FLD( PU_NMMU_NX_DEBUG_SNAPSHOT_1_B64_87_LEN                  , 24  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_B64_87_LEN );
+
+REG64_FLD( PU_NX_DEBUG_SNAPSHOT_1_B64_87                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_B64_87     );
+REG64_FLD( PU_NX_DEBUG_SNAPSHOT_1_B64_87_LEN                       , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_B64_87_LEN );
+
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_00                           , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_00 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_ICS_INVALID_STATE                     , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ICS_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_02                           , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_02 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_03                           , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_03 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH0_842_ECC_CE                        , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH0_842_ECC_CE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH0_842_ECC_UE                        , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH0_842_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH1_842_ECC_CE                        , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH1_842_ECC_CE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH1_842_ECC_UE                        , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH1_842_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_NONZERO_CSB_CC                        , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_NONZERO_CSB_CC );
+REG64_FLD( PU_NX_DMA_ENG_FIR_ECC_CE                                , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_CE     );
+REG64_FLD( PU_NX_DMA_ENG_FIR_OUTWR_INRD_ECC_CE                     , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OUTWR_INRD_ECC_CE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH5_AMF_ECC_CE                        , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH5_AMF_ECC_CE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH6_AMF_ECC_CE                        , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH6_AMF_ECC_CE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH7_AMF_ECC_CE                        , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH7_AMF_ECC_CE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_OTHER_SCOM_SAT                        , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OTHER_SCOM_SAT );
+REG64_FLD( PU_NX_DMA_ENG_FIR_INVALID_STATE_RECOV                   , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INVALID_STATE_RECOV );
+REG64_FLD( PU_NX_DMA_ENG_FIR_INVALID_STATE_UNRECOV                 , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INVALID_STATE_UNRECOV );
+REG64_FLD( PU_NX_DMA_ENG_FIR_ECC_UE                                , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_UE     );
+REG64_FLD( PU_NX_DMA_ENG_FIR_OUTWR_INRD_ECC_UE                     , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OUTWR_INRD_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_INRD_DONE_ERR                         , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INRD_DONE_ERR );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH0_INVALID_STATE                     , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH0_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH1_INVALID_STATE                     , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH1_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH2_INVALID_STATE                     , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH2_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH3_INVALID_STATE                     , 23  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH3_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH4_INVALID_STATE                     , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH4_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH5_INVALID_STATE                     , 25  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH5_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH6_INVALID_STATE                     , 26  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH6_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH7_INVALID_STATE                     , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH7_INVALID_STATE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH5_AMF_ECC_UE                        , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH5_AMF_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH6_AMF_ECC_UE                        , 29  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH6_AMF_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH7_AMF_ECC_UE                        , 30  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH7_AMF_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CRB_ECC_UE                            , 31  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CRB_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CRB_ECC_SUE                           , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CRB_ECC_SUE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_OUTWR_INRD_ECC_SUE                    , 33  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OUTWR_INRD_ECC_SUE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_34                           , 34  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_34 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_35                           , 35  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_35 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH4_AMF_ECC_CE                        , 36  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH4_AMF_ECC_CE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_CH4_AMF_ECC_UE                        , 37  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CH4_AMF_ECC_UE );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_38                           , 38  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_38 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_39                           , 39  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_39 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_40                           , 40  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_40 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_41                           , 41  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_41 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_42                           , 42  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_42 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_43                           , 43  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_43 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_44                           , 44  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_44 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_45                           , 45  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_45 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_46                           , 46  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_46 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_47                           , 47  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_47 );
+REG64_FLD( PU_NX_DMA_ENG_FIR_SCOM_PE                               , 48  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PE    );
+REG64_FLD( PU_NX_DMA_ENG_FIR_SCOM_PE_DUP                           , 49  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PE_DUP );
+
+REG64_FLD( PU_NX_DMA_ENG_FIR_ACTION0_BITS                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NX_DMA_ENG_FIR_ACTION0_BITS_LEN                      , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NX_DMA_ENG_FIR_ACTION1_BITS                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NX_DMA_ENG_FIR_ACTION1_BITS_LEN                      , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NX_DMA_ENG_FIR_MASK_BITS                             , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NX_DMA_ENG_FIR_MASK_BITS_LEN                         , 50  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NX_DMA_ENG_FIR_WOF_BITS                              , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NX_DMA_ENG_FIR_WOF_BITS_LEN                          , 50  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_ENA                          , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH0EFT_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_TYPE                         , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH0EFT_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_ACTION                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH0EFT_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_SELECT                       , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH0EFT_SELECT );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_SELECT_LEN                   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH0EFT_SELECT_LEN );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH1EFT_ENA                          , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH1EFT_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH1EFT_TYPE                         , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH1EFT_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH1EFT_ACTION                       , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH1EFT_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH1EFT_SELECT                       , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH1EFT_SELECT );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH1EFT_SELECT_LEN                   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH1EFT_SELECT_LEN );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INWR_ENA                        , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_INWR_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INWR_TYPE                       , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_INWR_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INWR_ACTION                     , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_INWR_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_OUTWR_ENA                       , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_OUTWR_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_OUTWR_TYPE                      , 27  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_OUTWR_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_OUTWR_ACTION                    , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_OUTWR_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_ENA                    , 29  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_INGARRAY_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_TYPE                   , 30  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_INGARRAY_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_ACTION                 , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_INGARRAY_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_SELECT                 , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_INGARRAY_SELECT );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_SELECT_LEN             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_INGARRAY_SELECT_LEN );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_ENA                    , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_EGRARRAY_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_TYPE                   , 37  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_EGRARRAY_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_ACTION                 , 38  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_EGRARRAY_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_SELECT                 , 39  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_EGRARRAY_SELECT );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_SELECT_LEN             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_EGRARRAY_SELECT_LEN );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_ENA                    , 43  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_CRBARRAY_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_TYPE                   , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_CRBARRAY_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_ACTION                 , 45  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_CRBARRAY_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_SELECT                 , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_CRBARRAY_SELECT );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_ENA                         , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH4GZIP_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_TYPE                        , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH4GZIP_TYPE );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_ACTION                      , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH4GZIP_ACTION );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_SELECT                      , 51  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH4GZIP_SELECT );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_SELECT_LEN                  , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH4GZIP_SELECT_LEN );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_OUTWR_QW0_UEINJ_ENA             , 59  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_OUTWR_QW0_UEINJ_ENA );
+REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_OUTWR_QW4_UEINJ_ENA             , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_OUTWR_QW4_UEINJ_ENA );
+
+REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE             , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_HANG_POLL_SCALE );
+REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE_LEN         , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_HANG_POLL_SCALE_LEN );
+REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE             , 8   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_HANG_DATA_SCALE );
+REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE_LEN         , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_HANG_DATA_SCALE_LEN );
+REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE              , 12  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_HANG_SHM_SCALE );
+REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE_LEN          , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_HANG_SHM_SCALE_LEN );
+
+REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE                  , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HANG_POLL_SCALE );
+REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE_LEN              , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HANG_POLL_SCALE_LEN );
+REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HANG_DATA_SCALE );
+REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE_LEN              , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HANG_DATA_SCALE_LEN );
+REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE                   , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HANG_SHM_SCALE );
+REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE_LEN               , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HANG_SHM_SCALE_LEN );
+REG64_FLD( PU_NX_MISC_CONTROL_REG_ERAT_DATA_POLL_SCALE             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ERAT_DATA_POLL_SCALE );
+REG64_FLD( PU_NX_MISC_CONTROL_REG_ERAT_DATA_POLL_SCALE_LEN         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ERAT_DATA_POLL_SCALE_LEN );
+
+REG64_FLD( PU_NX_MMIO_BAR_BAR                                      , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR        );
+REG64_FLD( PU_NX_MMIO_BAR_BAR_LEN                                  , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR_LEN    );
+REG64_FLD( PU_NX_MMIO_BAR_ENABLE                                   , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+
+REG64_FLD( PU_NMMU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL                 , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_TRACE_CNTL );
+REG64_FLD( PU_NMMU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL_LEN             , 8   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_TRACE_CNTL_LEN );
+
+REG64_FLD( PU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_TRACE_CNTL );
+REG64_FLD( PU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL_LEN                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_TRACE_CNTL_LEN );
+
+REG64_FLD( PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_MODE                  , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_INJECT_MODE );
+REG64_FLD( PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_MODE_LEN              , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_INJECT_MODE_LEN );
+REG64_FLD( PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE                  , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_INJECT_TYPE );
+REG64_FLD( PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE_LEN              , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_INJECT_TYPE_LEN );
+REG64_FLD( PU_NMMU_NX_PB_ECC_REG_NXCQ_PBCQ_INJECT_ENABLE           , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_PBCQ_INJECT_ENABLE );
+REG64_FLD( PU_NMMU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY                   , 5   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_PBCQ_ARRAY );
+REG64_FLD( PU_NMMU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY_LEN               , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_PBCQ_ARRAY_LEN );
+
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_INJECT_MODE                       , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_INJECT_MODE );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_INJECT_MODE_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_INJECT_MODE_LEN );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE                       , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_INJECT_TYPE );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_INJECT_TYPE_LEN );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_PBCQ_INJECT_ENABLE                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_PBCQ_INJECT_ENABLE );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY                        , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_PBCQ_ARRAY );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_PBCQ_ARRAY_LEN );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_RNG_INJECT_ENABLE                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_RNG_INJECT_ENABLE );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_RNG_INJECT_ACTION                 , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_RNG_INJECT_ACTION );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_ENABLE                 , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_ERAT_ARRAY_ENABLE );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_TYPE                   , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_ERAT_ARRAY_TYPE );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_ACTION                 , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_ERAT_ARRAY_ACTION );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_SELECT                 , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_ERAT_ARRAY_SELECT );
+REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_SELECT_LEN             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NXCQ_ERAT_ARRAY_SELECT_LEN );
+
+REG64_FLD( PU_NMMU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE                  , 52  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_PBI_WRITE_IDLE );
+
+REG64_FLD( PU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE                       , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PBI_WRITE_IDLE );
+
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_ENABLE                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_FREEZE                           , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE     );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_RESET                            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESET      );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_DIS_GLOB_SCOM                    , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DIS_GLOB_SCOM );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL0                   , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL0 );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL0_LEN               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL0_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL1                   , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL1 );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL1_LEN               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL1_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL2                   , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL2 );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL2_LEN               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL2_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL3                   , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL3 );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL3_LEN               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL3_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT0_PAIR_OP                     , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT0_PAIR_OP );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT0_PAIR_OP_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT0_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT1_PAIR_OP                     , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT1_PAIR_OP );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT1_PAIR_OP_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT1_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT2_PAIR_OP                     , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT2_PAIR_OP );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT2_PAIR_OP_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT2_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT3_PAIR_OP                     , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT3_PAIR_OP );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT3_PAIR_OP_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT3_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT0_MUX_SEL                     , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT0_MUX_SEL );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT0_MUX_SEL_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT0_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT1_MUX_SEL                     , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT1_MUX_SEL );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT1_MUX_SEL_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT1_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT2_MUX_SEL                     , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT2_MUX_SEL );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT2_MUX_SEL_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT2_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT3_MUX_SEL                     , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT3_MUX_SEL );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT3_MUX_SEL_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT3_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_FREEZE_ON_OVERFLOW               , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_ON_OVERFLOW );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CASCADE                          , 33  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CASCADE    );
+REG64_FLD( PU_NX_PMU0_CONTROL_REG_CASCADE_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CASCADE_LEN );
+
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_0                                , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_0_LEN                            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_0_LEN      );
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_1                                , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_1_LEN                            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_1_LEN      );
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_2                                , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_2_LEN                            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_2_LEN      );
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_3                                , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( PU_NX_PMU0_COUNTER_REG_3_LEN                            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_3_LEN      );
+
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_ENABLE                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_FREEZE                           , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE     );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_RESET                            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESET      );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_DIS_GLOB_SCOM                    , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DIS_GLOB_SCOM );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL0                   , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL0 );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL0_LEN               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL0_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL1                   , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL1 );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL1_LEN               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL1_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL2                   , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL2 );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL2_LEN               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL2_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL3                   , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL3 );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL3_LEN               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALAR_SEL3_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT0_PAIR_OP                     , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT0_PAIR_OP );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT0_PAIR_OP_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT0_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT1_PAIR_OP                     , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT1_PAIR_OP );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT1_PAIR_OP_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT1_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT2_PAIR_OP                     , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT2_PAIR_OP );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT2_PAIR_OP_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT2_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT3_PAIR_OP                     , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT3_PAIR_OP );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT3_PAIR_OP_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT3_PAIR_OP_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT0_MUX_SEL                     , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT0_MUX_SEL );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT0_MUX_SEL_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT0_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT1_MUX_SEL                     , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT1_MUX_SEL );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT1_MUX_SEL_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT1_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT2_MUX_SEL                     , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT2_MUX_SEL );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT2_MUX_SEL_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT2_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT3_MUX_SEL                     , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT3_MUX_SEL );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT3_MUX_SEL_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CNT3_MUX_SEL_LEN );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_FREEZE_ON_OVERFLOW               , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_ON_OVERFLOW );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CASCADE                          , 33  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CASCADE    );
+REG64_FLD( PU_NX_PMU1_CONTROL_REG_CASCADE_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CASCADE_LEN );
+
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_0                                , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_0_LEN                            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_0_LEN      );
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_1                                , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_1_LEN                            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_1_LEN      );
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_2                                , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_2_LEN                            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_2_LEN      );
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_3                                , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( PU_NX_PMU1_COUNTER_REG_3_LEN                            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_3_LEN      );
+
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT0_ENABLE                  , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT0_ENABLE );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT1_ENABLE                  , 1   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT1_ENABLE );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT2_ENABLE                  , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT2_ENABLE );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT3_ENABLE                  , 3   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT3_ENABLE );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_PRESCALER_SEL                , 4   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALER_SEL );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_PRESCALER_SEL_LEN            , 3   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALER_SEL_LEN );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT0_POSEDGE_SEL             , 7   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT0_POSEDGE_SEL );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT1_POSEDGE_SEL             , 8   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT1_POSEDGE_SEL );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT2_POSEDGE_SEL             , 9   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT2_POSEDGE_SEL );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT3_POSEDGE_SEL             , 10  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT3_POSEDGE_SEL );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_RESET                        , 11  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_RESET      );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT0_EVENT_SEL               , 12  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT0_EVENT_SEL );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT0_EVENT_SEL_LEN           , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT0_EVENT_SEL_LEN );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT0_BIT_PAIR_SEL            , 14  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT0_BIT_PAIR_SEL );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT0_BIT_PAIR_SEL_LEN        , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT0_BIT_PAIR_SEL_LEN );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT1_EVENT_SEL               , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT1_EVENT_SEL );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT1_EVENT_SEL_LEN           , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT1_EVENT_SEL_LEN );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT1_BIT_PAIR_SEL            , 18  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT1_BIT_PAIR_SEL );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT1_BIT_PAIR_SEL_LEN        , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT1_BIT_PAIR_SEL_LEN );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT2_EVENT_SEL               , 20  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT2_EVENT_SEL );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT2_EVENT_SEL_LEN           , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT2_EVENT_SEL_LEN );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT2_BIT_PAIR_SEL            , 22  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT2_BIT_PAIR_SEL );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT2_BIT_PAIR_SEL_LEN        , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT2_BIT_PAIR_SEL_LEN );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT3_EVENT_SEL               , 24  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT3_EVENT_SEL );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT3_EVENT_SEL_LEN           , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT3_EVENT_SEL_LEN );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT3_BIT_PAIR_SEL            , 26  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT3_BIT_PAIR_SEL );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT3_BIT_PAIR_SEL_LEN        , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_CNT3_BIT_PAIR_SEL_LEN );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_PORT_SEL                     , 28  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_PORT_SEL   );
+REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_PORT_SEL_LEN                 , 2   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_PORT_SEL_LEN );
+
+REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_0                            , 0   , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_0_LEN                        , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_0_LEN      );
+REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_1                            , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_1_LEN                        , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_1_LEN      );
+REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_2                            , 32  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_2_LEN                        , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_2_LEN      );
+REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_3                            , 48  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_3_LEN                        , 16  , SH_UNT_PU_NMMU  , SH_ACS_SCOM     ,
+           SH_FLD_3_LEN      );
+
+REG64_FLD( PU_NX_RNG_BYPASS_RRN_DATA                               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RRN_DATA   );
+REG64_FLD( PU_NX_RNG_BYPASS_RRN_DATA_LEN                           , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RRN_DATA_LEN );
+
+REG64_FLD( PU_NX_RNG_CFG_FAIL_REG                                  , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FAIL_REG   );
+REG64_FLD( PU_NX_RNG_CFG_FAIL_REG_LEN                              , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FAIL_REG_LEN );
+REG64_FLD( PU_NX_RNG_CFG_RNG0_FAIL                                 , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RNG0_FAIL  );
+REG64_FLD( PU_NX_RNG_CFG_RNG1_FAIL                                 , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RNG1_FAIL  );
+REG64_FLD( PU_NX_RNG_CFG_INTERRUPT_SENT                            , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_SENT );
+REG64_FLD( PU_NX_RNG_CFG_BIST_ENABLE                               , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ENABLE );
+REG64_FLD( PU_NX_RNG_CFG_BIST_COMPLETE                             , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BIST_COMPLETE );
+REG64_FLD( PU_NX_RNG_CFG_RNG0_BIST_FAIL                            , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RNG0_BIST_FAIL );
+REG64_FLD( PU_NX_RNG_CFG_RNG1_BIST_FAIL                            , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RNG1_BIST_FAIL );
+REG64_FLD( PU_NX_RNG_CFG_BIST_BIT_FAIL_TH                          , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BIST_BIT_FAIL_TH );
+REG64_FLD( PU_NX_RNG_CFG_BIST_BIT_FAIL_TH_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BIST_BIT_FAIL_TH_LEN );
+REG64_FLD( PU_NX_RNG_CFG_RNG0_INJ_CONTINOUS_ERROR                  , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RNG0_INJ_CONTINOUS_ERROR );
+REG64_FLD( PU_NX_RNG_CFG_RNG1_INJ_CONTINOUS_ERROR                  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RNG1_INJ_CONTINOUS_ERROR );
+REG64_FLD( PU_NX_RNG_CFG_ST2_RESET_PERIOD                          , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ST2_RESET_PERIOD );
+REG64_FLD( PU_NX_RNG_CFG_ST2_RESET_PERIOD_LEN                      , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ST2_RESET_PERIOD_LEN );
+REG64_FLD( PU_NX_RNG_CFG_RRN_BYPASS_ENABLE                         , 38  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RRN_BYPASS_ENABLE );
+REG64_FLD( PU_NX_RNG_CFG_MASK_TOGGLE_ENABLE                        , 39  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASK_TOGGLE_ENABLE );
+REG64_FLD( PU_NX_RNG_CFG_SAMPTEST_ENABLE                           , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SAMPTEST_ENABLE );
+REG64_FLD( PU_NX_RNG_CFG_REPTEST_ENABLE                            , 41  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REPTEST_ENABLE );
+REG64_FLD( PU_NX_RNG_CFG_ADAPTEST_1BIT_ENABLE                      , 42  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_1BIT_ENABLE );
+REG64_FLD( PU_NX_RNG_CFG_ADAPTEST_ENABLE                           , 43  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_ENABLE );
+REG64_FLD( PU_NX_RNG_CFG_COND_STARTUP_TEST_FAIL                    , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_COND_STARTUP_TEST_FAIL );
+REG64_FLD( PU_NX_RNG_CFG_PACE_RATE                                 , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PACE_RATE  );
+REG64_FLD( PU_NX_RNG_CFG_PACE_RATE_LEN                             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PACE_RATE_LEN );
+REG64_FLD( PU_NX_RNG_CFG_ENABLE                                    , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+
+REG64_FLD( PU_NX_RNG_RDELAY_CQ_FILL_THRESHOLD                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_FILL_THRESHOLD );
+REG64_FLD( PU_NX_RNG_RDELAY_CQ_FILL_THRESHOLD_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_FILL_THRESHOLD_LEN );
+REG64_FLD( PU_NX_RNG_RDELAY_CQ_DRAIN_THRESHOLD                     , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_DRAIN_THRESHOLD );
+REG64_FLD( PU_NX_RNG_RDELAY_CQ_DRAIN_THRESHOLD_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_DRAIN_THRESHOLD_LEN );
+REG64_FLD( PU_NX_RNG_RDELAY_CQ_LFSR_RESEED_EN                      , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_LFSR_RESEED_EN );
+REG64_FLD( PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO                      , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_READ_RTY_RATIO );
+REG64_FLD( PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_READ_RTY_RATIO_LEN );
+
+REG64_FLD( PU_NX_RNG_RESET_RESET                                   , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESET      );
+
+REG64_FLD( PU_NX_RNG_ST0_REPTEST_MATCH_TH                          , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REPTEST_MATCH_TH );
+REG64_FLD( PU_NX_RNG_ST0_REPTEST_MATCH_TH_LEN                      , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REPTEST_MATCH_TH_LEN );
+REG64_FLD( PU_NX_RNG_ST0_REPTEST_SOFT_FAIL_TH                      , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REPTEST_SOFT_FAIL_TH );
+REG64_FLD( PU_NX_RNG_ST0_REPTEST_SOFT_FAIL_TH_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REPTEST_SOFT_FAIL_TH_LEN );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE                      , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SAMPLE_SIZE );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SAMPLE_SIZE_LEN );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE                      , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_WINDOW_SIZE );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_LEN                  , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_WINDOW_SIZE_LEN );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH                , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_LEN            , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH_LEN );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH                , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_LEN            , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH_LEN );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH                , 36  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_LEN            , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH_LEN );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH                , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH );
+REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_LEN            , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH_LEN );
+
+REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH                     , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SOFT_FAIL_TH );
+REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH_LEN                 , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SOFT_FAIL_TH_LEN );
+REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN                , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN );
+REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN_LEN            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN_LEN );
+REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX                , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX );
+REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX_LEN            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX_LEN );
+
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0 );
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0_LEN     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0_LEN );
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1 );
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1_LEN     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1_LEN );
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0         , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0 );
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0_LEN     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0_LEN );
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1 );
+REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1_LEN     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1_LEN );
+REG64_FLD( PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG0              , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0 );
+REG64_FLD( PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG0_LEN          , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0_LEN );
+REG64_FLD( PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG1              , 38  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1 );
+REG64_FLD( PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN          , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN );
+
+REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_RRN_ENABLE                       , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SAMPTEST_RRN_ENABLE );
+REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE                      , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SAMPTEST_WINDOW_SIZE );
+REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE_LEN                  , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SAMPTEST_WINDOW_SIZE_LEN );
+REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN                     , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SAMPTEST_MATCH_TH_MIN );
+REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_LEN                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SAMPTEST_MATCH_TH_MIN_LEN );
+REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX                     , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SAMPTEST_MATCH_TH_MAX );
+REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_LEN                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SAMPTEST_MATCH_TH_MAX_LEN );
+
+REG64_FLD( PU_NX_TRIGGER_CTRL_BITS                                 , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_NX_TRIGGER_CTRL_BITS_LEN                             , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PU_OCB_OCI_CCSR_CORE_CONFIG                             , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CORE_CONFIG );
+REG64_FLD( PU_OCB_OCI_CCSR_CORE_CONFIG_LEN                         , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CORE_CONFIG_LEN );
+REG64_FLD( PU_OCB_OCI_CCSR_RESERVED_24                             , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_24 );
+REG64_FLD( PU_OCB_OCI_CCSR_RESERVED_24_LEN                         , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_24_LEN );
+REG64_FLD( PU_OCB_OCI_CCSR_CHANGE_IN_PROGRESS                      , 31  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CHANGE_IN_PROGRESS );
+
+REG64_FLD( PU_OCB_OCI_O2SCMD0A_O2SCMD_A_N_RESERVED_0               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCMD_A_N_RESERVED_0 );
+REG64_FLD( PU_OCB_OCI_O2SCMD0A_O2S_CLEAR_STICKY_BITS_A_N           , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CLEAR_STICKY_BITS_A_N );
+
+REG64_FLD( PU_OCB_OCI_O2SCMD0B_O2SCMD_A_N_RESERVED_0               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCMD_A_N_RESERVED_0 );
+REG64_FLD( PU_OCB_OCI_O2SCMD0B_O2S_CLEAR_STICKY_BITS_A_N           , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CLEAR_STICKY_BITS_A_N );
+
+REG64_FLD( PU_OCB_OCI_O2SCMD1A_O2SCMD_A_N_RESERVED_0               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCMD_A_N_RESERVED_0 );
+REG64_FLD( PU_OCB_OCI_O2SCMD1A_O2S_CLEAR_STICKY_BITS_A_N           , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CLEAR_STICKY_BITS_A_N );
+
+REG64_FLD( PU_OCB_OCI_O2SCMD1B_O2SCMD_A_N_RESERVED_0               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCMD_A_N_RESERVED_0 );
+REG64_FLD( PU_OCB_OCI_O2SCMD1B_O2S_CLEAR_STICKY_BITS_A_N           , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CLEAR_STICKY_BITS_A_N );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2S_BRIDGE_ENABLE_A_N             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_BRIDGE_ENABLE_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_1           , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCTRL1_A_N_RESERVED_1 );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2S_CPOL_A_N                      , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CPOL_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2S_CPHA_A_N                      , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CPHA_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2S_CLOCK_DIVIDER_A_N             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CLOCK_DIVIDER_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2S_CLOCK_DIVIDER_A_N_LEN         , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_14_16       , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_14_16_LEN   , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2S_NR_OF_FRAMES_A_N              , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_NR_OF_FRAMES_A_N );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2S_BRIDGE_ENABLE_A_N             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_BRIDGE_ENABLE_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_1           , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCTRL1_A_N_RESERVED_1 );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2S_CPOL_A_N                      , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CPOL_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2S_CPHA_A_N                      , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CPHA_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2S_CLOCK_DIVIDER_A_N             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CLOCK_DIVIDER_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2S_CLOCK_DIVIDER_A_N_LEN         , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_14_16       , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_14_16_LEN   , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2S_NR_OF_FRAMES_A_N              , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_NR_OF_FRAMES_A_N );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2S_BRIDGE_ENABLE_A_N             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_BRIDGE_ENABLE_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_1           , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCTRL1_A_N_RESERVED_1 );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2S_CPOL_A_N                      , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CPOL_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2S_CPHA_A_N                      , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CPHA_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2S_CLOCK_DIVIDER_A_N             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CLOCK_DIVIDER_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2S_CLOCK_DIVIDER_A_N_LEN         , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_14_16       , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_14_16_LEN   , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2S_NR_OF_FRAMES_A_N              , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_NR_OF_FRAMES_A_N );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2S_BRIDGE_ENABLE_A_N             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_BRIDGE_ENABLE_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_1           , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCTRL1_A_N_RESERVED_1 );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2S_CPOL_A_N                      , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CPOL_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2S_CPHA_A_N                      , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CPHA_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2S_CLOCK_DIVIDER_A_N             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CLOCK_DIVIDER_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2S_CLOCK_DIVIDER_A_N_LEN         , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_14_16       , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_14_16_LEN   , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2S_NR_OF_FRAMES_A_N              , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_NR_OF_FRAMES_A_N );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRL20A_O2S_INTER_FRAME_DELAY_A_N         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_INTER_FRAME_DELAY_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL20A_O2S_INTER_FRAME_DELAY_A_N_LEN     , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRL20B_O2S_INTER_FRAME_DELAY_A_N         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_INTER_FRAME_DELAY_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL20B_O2S_INTER_FRAME_DELAY_A_N_LEN     , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRL21A_O2S_INTER_FRAME_DELAY_A_N         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_INTER_FRAME_DELAY_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL21A_O2S_INTER_FRAME_DELAY_A_N_LEN     , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRL21B_O2S_INTER_FRAME_DELAY_A_N         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_INTER_FRAME_DELAY_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRL21B_O2S_INTER_FRAME_DELAY_A_N_LEN     , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_FRAME_SIZE_A_N                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_FRAME_SIZE_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_FRAME_SIZE_A_N_LEN            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_FRAME_SIZE_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_OUT_COUNT1_A_N                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT1_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_OUT_COUNT1_A_N_LEN            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT1_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_IN_DELAY1_A_N                 , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY1_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_IN_DELAY1_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY1_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_IN_COUNT1_A_N                 , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT1_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_IN_COUNT1_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT1_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_FRAME_SIZE_A_N                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_FRAME_SIZE_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_FRAME_SIZE_A_N_LEN            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_FRAME_SIZE_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_OUT_COUNT1_A_N                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT1_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_OUT_COUNT1_A_N_LEN            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT1_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_IN_DELAY1_A_N                 , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY1_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_IN_DELAY1_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY1_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_IN_COUNT1_A_N                 , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT1_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_IN_COUNT1_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT1_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_FRAME_SIZE_A_N                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_FRAME_SIZE_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_FRAME_SIZE_A_N_LEN            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_FRAME_SIZE_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_OUT_COUNT1_A_N                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT1_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_OUT_COUNT1_A_N_LEN            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT1_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_IN_DELAY1_A_N                 , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY1_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_IN_DELAY1_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY1_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_IN_COUNT1_A_N                 , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT1_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_IN_COUNT1_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT1_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_FRAME_SIZE_A_N                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_FRAME_SIZE_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_FRAME_SIZE_A_N_LEN            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_FRAME_SIZE_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_OUT_COUNT1_A_N                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT1_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_OUT_COUNT1_A_N_LEN            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT1_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_IN_DELAY1_A_N                 , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY1_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_IN_DELAY1_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY1_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_IN_COUNT1_A_N                 , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT1_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_IN_COUNT1_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT1_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRLS0A_O2S_OUT_COUNT2_A_N                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT2_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS0A_O2S_OUT_COUNT2_A_N_LEN            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT2_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS0A_O2S_IN_DELAY2_A_N                 , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY2_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS0A_O2S_IN_DELAY2_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY2_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS0A_O2S_IN_COUNT2_A_N                 , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT2_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS0A_O2S_IN_COUNT2_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT2_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRLS0B_O2S_OUT_COUNT2_A_N                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT2_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS0B_O2S_OUT_COUNT2_A_N_LEN            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT2_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS0B_O2S_IN_DELAY2_A_N                 , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY2_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS0B_O2S_IN_DELAY2_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY2_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS0B_O2S_IN_COUNT2_A_N                 , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT2_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS0B_O2S_IN_COUNT2_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT2_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRLS1A_O2S_OUT_COUNT2_A_N                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT2_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS1A_O2S_OUT_COUNT2_A_N_LEN            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT2_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS1A_O2S_IN_DELAY2_A_N                 , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY2_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS1A_O2S_IN_DELAY2_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY2_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS1A_O2S_IN_COUNT2_A_N                 , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT2_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS1A_O2S_IN_COUNT2_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT2_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SCTRLS1B_O2S_OUT_COUNT2_A_N                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT2_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS1B_O2S_OUT_COUNT2_A_N_LEN            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_OUT_COUNT2_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS1B_O2S_IN_DELAY2_A_N                 , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY2_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS1B_O2S_IN_DELAY2_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_DELAY2_A_N_LEN );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS1B_O2S_IN_COUNT2_A_N                 , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT2_A_N );
+REG64_FLD( PU_OCB_OCI_O2SCTRLS1B_O2S_IN_COUNT2_A_N_LEN             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_IN_COUNT2_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SRD0A_O2S_RDATA_A_N                        , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_RDATA_A_N );
+REG64_FLD( PU_OCB_OCI_O2SRD0A_O2S_RDATA_A_N_LEN                    , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_RDATA_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SRD0B_O2S_RDATA_A_N                        , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_RDATA_A_N );
+REG64_FLD( PU_OCB_OCI_O2SRD0B_O2S_RDATA_A_N_LEN                    , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_RDATA_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SRD1A_O2S_RDATA_A_N                        , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_RDATA_A_N );
+REG64_FLD( PU_OCB_OCI_O2SRD1A_O2S_RDATA_A_N_LEN                    , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_RDATA_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SRD1B_O2S_RDATA_A_N                        , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_RDATA_A_N );
+REG64_FLD( PU_OCB_OCI_O2SRD1B_O2S_RDATA_A_N_LEN                    , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_RDATA_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SST0A_O2S_ONGOING_A_N                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_ONGOING_A_N );
+REG64_FLD( PU_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_1_4               , 1   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2SST_A_N_RESERVED_1_4 );
+REG64_FLD( PU_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_1_4_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2SST_A_N_RESERVED_1_4_LEN );
+REG64_FLD( PU_OCB_OCI_O2SST0A_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N  , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N );
+REG64_FLD( PU_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_6                 , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2SST_A_N_RESERVED_6 );
+REG64_FLD( PU_OCB_OCI_O2SST0A_O2S_FSM_ERR_A_N                      , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_FSM_ERR_A_N );
+
+REG64_FLD( PU_OCB_OCI_O2SST0B_O2S_ONGOING_A_N                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_ONGOING_A_N );
+REG64_FLD( PU_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_1_4               , 1   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2SST_A_N_RESERVED_1_4 );
+REG64_FLD( PU_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_1_4_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2SST_A_N_RESERVED_1_4_LEN );
+REG64_FLD( PU_OCB_OCI_O2SST0B_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N  , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N );
+REG64_FLD( PU_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_6                 , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2SST_A_N_RESERVED_6 );
+REG64_FLD( PU_OCB_OCI_O2SST0B_O2S_FSM_ERR_A_N                      , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_FSM_ERR_A_N );
+
+REG64_FLD( PU_OCB_OCI_O2SST1A_O2S_ONGOING_A_N                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_ONGOING_A_N );
+REG64_FLD( PU_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_1_4               , 1   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2SST_A_N_RESERVED_1_4 );
+REG64_FLD( PU_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_1_4_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2SST_A_N_RESERVED_1_4_LEN );
+REG64_FLD( PU_OCB_OCI_O2SST1A_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N  , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N );
+REG64_FLD( PU_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_6                 , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2SST_A_N_RESERVED_6 );
+REG64_FLD( PU_OCB_OCI_O2SST1A_O2S_FSM_ERR_A_N                      , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_FSM_ERR_A_N );
+
+REG64_FLD( PU_OCB_OCI_O2SST1B_O2S_ONGOING_A_N                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_ONGOING_A_N );
+REG64_FLD( PU_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_1_4               , 1   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2SST_A_N_RESERVED_1_4 );
+REG64_FLD( PU_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_1_4_LEN           , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2SST_A_N_RESERVED_1_4_LEN );
+REG64_FLD( PU_OCB_OCI_O2SST1B_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N  , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N );
+REG64_FLD( PU_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_6                 , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2SST_A_N_RESERVED_6 );
+REG64_FLD( PU_OCB_OCI_O2SST1B_O2S_FSM_ERR_A_N                      , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_O2S_FSM_ERR_A_N );
+
+REG64_FLD( PU_OCB_OCI_O2SWD0A_O2S_WDATA_A_N                        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_WDATA_A_N );
+REG64_FLD( PU_OCB_OCI_O2SWD0A_O2S_WDATA_A_N_LEN                    , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_WDATA_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SWD0B_O2S_WDATA_A_N                        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_WDATA_A_N );
+REG64_FLD( PU_OCB_OCI_O2SWD0B_O2S_WDATA_A_N_LEN                    , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_WDATA_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SWD1A_O2S_WDATA_A_N                        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_WDATA_A_N );
+REG64_FLD( PU_OCB_OCI_O2SWD1A_O2S_WDATA_A_N_LEN                    , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_WDATA_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_O2SWD1B_O2S_WDATA_A_N                        , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_WDATA_A_N );
+REG64_FLD( PU_OCB_OCI_O2SWD1B_O2S_WDATA_A_N_LEN                    , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_O2S_WDATA_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_ENABLE                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_ENABLE );
+REG64_FLD( PU_OCB_OCI_OCBLWCR0_SPARE_0                             , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_0    );
+REG64_FLD( PU_OCB_OCI_OCBLWCR0_SPARE_0_LEN                         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_0_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_BAR                   , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BAR );
+REG64_FLD( PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_BAR_LEN               , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BAR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_MASK                  , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_MASK );
+REG64_FLD( PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_MASK_LEN              , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_MASK_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_ENABLE                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_ENABLE );
+REG64_FLD( PU_OCB_OCI_OCBLWCR1_SPARE_0                             , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_0    );
+REG64_FLD( PU_OCB_OCI_OCBLWCR1_SPARE_0_LEN                         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_0_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_BAR                   , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BAR );
+REG64_FLD( PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_BAR_LEN               , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BAR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_MASK                  , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_MASK );
+REG64_FLD( PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_MASK_LEN              , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_MASK_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_ENABLE                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_ENABLE );
+REG64_FLD( PU_OCB_OCI_OCBLWCR2_SPARE_0                             , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_0    );
+REG64_FLD( PU_OCB_OCI_OCBLWCR2_SPARE_0_LEN                         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_0_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_BAR                   , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BAR );
+REG64_FLD( PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_BAR_LEN               , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BAR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_MASK                  , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_MASK );
+REG64_FLD( PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_MASK_LEN              , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_MASK_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_ENABLE                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_ENABLE );
+REG64_FLD( PU_OCB_OCI_OCBLWCR3_SPARE_0                             , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_0    );
+REG64_FLD( PU_OCB_OCI_OCBLWCR3_SPARE_0_LEN                         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_0_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_BAR                   , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BAR );
+REG64_FLD( PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_BAR_LEN               , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BAR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_MASK                  , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_MASK );
+REG64_FLD( PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_MASK_LEN              , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_MASK_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_REGION               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_REGION );
+REG64_FLD( PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_REGION_LEN           , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_REGION_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_BASE                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BASE );
+REG64_FLD( PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_BASE_LEN             , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BASE_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_REGION               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_REGION );
+REG64_FLD( PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_REGION_LEN           , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_REGION_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_BASE                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BASE );
+REG64_FLD( PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_BASE_LEN             , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BASE_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_REGION               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_REGION );
+REG64_FLD( PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_REGION_LEN           , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_REGION_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_BASE                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BASE );
+REG64_FLD( PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_BASE_LEN             , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BASE_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_REGION               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_REGION );
+REG64_FLD( PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_REGION_LEN           , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_REGION_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_BASE                 , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BASE );
+REG64_FLD( PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_BASE_LEN             , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINEAR_WINDOW_BASE_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBLWSR0_LINEAR_WINDOW_SCRESP                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINEAR_WINDOW_SCRESP );
+REG64_FLD( PU_OCB_OCI_OCBLWSR0_LINEAR_WINDOW_SCRESP_LEN            , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINEAR_WINDOW_SCRESP_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWSR0_SPARE0                              , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_OCB_OCI_OCBLWSR0_SPARE0_LEN                          , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE0_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBLWSR1_LINEAR_WINDOW_SCRESP                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINEAR_WINDOW_SCRESP );
+REG64_FLD( PU_OCB_OCI_OCBLWSR1_LINEAR_WINDOW_SCRESP_LEN            , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINEAR_WINDOW_SCRESP_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWSR1_SPARE0                              , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_OCB_OCI_OCBLWSR1_SPARE0_LEN                          , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE0_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBLWSR2_LINEAR_WINDOW_SCRESP                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINEAR_WINDOW_SCRESP );
+REG64_FLD( PU_OCB_OCI_OCBLWSR2_LINEAR_WINDOW_SCRESP_LEN            , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINEAR_WINDOW_SCRESP_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWSR2_SPARE0                              , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_OCB_OCI_OCBLWSR2_SPARE0_LEN                          , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE0_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBLWSR3_LINEAR_WINDOW_SCRESP                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINEAR_WINDOW_SCRESP );
+REG64_FLD( PU_OCB_OCI_OCBLWSR3_LINEAR_WINDOW_SCRESP_LEN            , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINEAR_WINDOW_SCRESP_LEN );
+REG64_FLD( PU_OCB_OCI_OCBLWSR3_SPARE0                              , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_OCB_OCI_OCBLWSR3_SPARE0_LEN                          , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE0_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBSES0_PUSH_READ_UNDERFLOW                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_READ_UNDERFLOW );
+REG64_FLD( PU_OCB_OCI_OCBSES0_PULL_WRITE_OVERFLOW                  , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_WRITE_OVERFLOW );
+
+REG64_FLD( PU_OCB_OCI_OCBSES1_PUSH_READ_UNDERFLOW                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_READ_UNDERFLOW );
+REG64_FLD( PU_OCB_OCI_OCBSES1_PULL_WRITE_OVERFLOW                  , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_WRITE_OVERFLOW );
+
+REG64_FLD( PU_OCB_OCI_OCBSES2_PUSH_READ_UNDERFLOW                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_READ_UNDERFLOW );
+REG64_FLD( PU_OCB_OCI_OCBSES2_PULL_WRITE_OVERFLOW                  , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_WRITE_OVERFLOW );
+
+REG64_FLD( PU_OCB_OCI_OCBSES3_PUSH_READ_UNDERFLOW                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_READ_UNDERFLOW );
+REG64_FLD( PU_OCB_OCI_OCBSES3_PULL_WRITE_OVERFLOW                  , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_WRITE_OVERFLOW );
+
+REG64_FLD( PU_OCB_OCI_OCBSHBR0_PUSH_REGION                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_REGION );
+REG64_FLD( PU_OCB_OCI_OCBSHBR0_PUSH_REGION_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_REGION_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHBR0_PUSH_START                          , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_START );
+REG64_FLD( PU_OCB_OCI_OCBSHBR0_PUSH_START_LEN                      , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBSHBR1_PUSH_REGION                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_REGION );
+REG64_FLD( PU_OCB_OCI_OCBSHBR1_PUSH_REGION_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_REGION_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHBR1_PUSH_START                          , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_START );
+REG64_FLD( PU_OCB_OCI_OCBSHBR1_PUSH_START_LEN                      , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBSHBR2_PUSH_REGION                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_REGION );
+REG64_FLD( PU_OCB_OCI_OCBSHBR2_PUSH_REGION_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_REGION_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHBR2_PUSH_START                          , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_START );
+REG64_FLD( PU_OCB_OCI_OCBSHBR2_PUSH_START_LEN                      , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBSHBR3_PUSH_REGION                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_REGION );
+REG64_FLD( PU_OCB_OCI_OCBSHBR3_PUSH_REGION_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_REGION_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHBR3_PUSH_START                          , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_START );
+REG64_FLD( PU_OCB_OCI_OCBSHBR3_PUSH_START_LEN                      , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_FULL                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_EMPTY                          , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_OCB_OCI_OCBSHCS0_SPARE                               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_OCB_OCI_OCBSHCS0_SPARE_LEN                           , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_INTR_ACTION_0_1                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_INTR_ACTION_0_1_LEN            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_LENGTH                         , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_LENGTH_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_WRITE_PTR                      , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_WRITE_PTR_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_READ_PTR                       , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_READ_PTR_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_ENABLE                         , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_FULL                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_EMPTY                          , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_OCB_OCI_OCBSHCS1_SPARE                               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_OCB_OCI_OCBSHCS1_SPARE_LEN                           , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_INTR_ACTION_0_1                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_INTR_ACTION_0_1_LEN            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_LENGTH                         , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_LENGTH_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_WRITE_PTR                      , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_WRITE_PTR_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_READ_PTR                       , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_READ_PTR_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_ENABLE                         , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_FULL                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_EMPTY                          , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_OCB_OCI_OCBSHCS2_SPARE                               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_OCB_OCI_OCBSHCS2_SPARE_LEN                           , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_INTR_ACTION_0_1                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_INTR_ACTION_0_1_LEN            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_LENGTH                         , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_LENGTH_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_WRITE_PTR                      , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_WRITE_PTR_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_READ_PTR                       , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_READ_PTR_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_ENABLE                         , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_FULL                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_EMPTY                          , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_OCB_OCI_OCBSHCS3_SPARE                               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_OCB_OCI_OCBSHCS3_SPARE_LEN                           , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_INTR_ACTION_0_1                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_INTR_ACTION_0_1_LEN            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_LENGTH                         , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_LENGTH_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_WRITE_PTR                      , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_WRITE_PTR_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_READ_PTR                       , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_READ_PTR_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_ENABLE                         , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_OCB_OCI_OCBSLBR0_PULL_REGION                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_REGION );
+REG64_FLD( PU_OCB_OCI_OCBSLBR0_PULL_REGION_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_REGION_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLBR0_PULL_START                          , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_START );
+REG64_FLD( PU_OCB_OCI_OCBSLBR0_PULL_START_LEN                      , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_START_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBSLBR1_PULL_REGION                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_REGION );
+REG64_FLD( PU_OCB_OCI_OCBSLBR1_PULL_REGION_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_REGION_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLBR1_PULL_START                          , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_START );
+REG64_FLD( PU_OCB_OCI_OCBSLBR1_PULL_START_LEN                      , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_START_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBSLBR2_PULL_REGION                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_REGION );
+REG64_FLD( PU_OCB_OCI_OCBSLBR2_PULL_REGION_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_REGION_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLBR2_PULL_START                          , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_START );
+REG64_FLD( PU_OCB_OCI_OCBSLBR2_PULL_START_LEN                      , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_START_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBSLBR3_PULL_REGION                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_REGION );
+REG64_FLD( PU_OCB_OCI_OCBSLBR3_PULL_REGION_LEN                     , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_REGION_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLBR3_PULL_START                          , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_START );
+REG64_FLD( PU_OCB_OCI_OCBSLBR3_PULL_START_LEN                      , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PULL_START_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_FULL                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_FULL  );
+REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_EMPTY                          , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_EMPTY );
+REG64_FLD( PU_OCB_OCI_OCBSLCS0_SPARE                               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_OCB_OCI_OCBSLCS0_SPARE_LEN                           , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_INTR_ACTION_0_1                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_INTR_ACTION_0_1 );
+REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_INTR_ACTION_0_1_LEN            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_LENGTH                         , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_LENGTH );
+REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_LENGTH_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_LENGTH_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_WRITE_PTR                      , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_WRITE_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_WRITE_PTR_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_WRITE_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_READ_PTR                       , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_READ_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_READ_PTR_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_READ_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_ENABLE                         , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_ENABLE );
+
+REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_FULL                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_FULL  );
+REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_EMPTY                          , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_EMPTY );
+REG64_FLD( PU_OCB_OCI_OCBSLCS1_SPARE                               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_OCB_OCI_OCBSLCS1_SPARE_LEN                           , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_INTR_ACTION_0_1                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_INTR_ACTION_0_1 );
+REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_INTR_ACTION_0_1_LEN            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_LENGTH                         , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_LENGTH );
+REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_LENGTH_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_LENGTH_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_WRITE_PTR                      , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_WRITE_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_WRITE_PTR_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_WRITE_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_READ_PTR                       , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_READ_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_READ_PTR_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_READ_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_ENABLE                         , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_ENABLE );
+
+REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_FULL                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_FULL  );
+REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_EMPTY                          , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_EMPTY );
+REG64_FLD( PU_OCB_OCI_OCBSLCS2_SPARE                               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_OCB_OCI_OCBSLCS2_SPARE_LEN                           , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_INTR_ACTION_0_1                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_INTR_ACTION_0_1 );
+REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_INTR_ACTION_0_1_LEN            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_LENGTH                         , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_LENGTH );
+REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_LENGTH_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_LENGTH_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_WRITE_PTR                      , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_WRITE_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_WRITE_PTR_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_WRITE_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_READ_PTR                       , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_READ_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_READ_PTR_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_READ_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_ENABLE                         , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_ENABLE );
+
+REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_FULL                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_FULL  );
+REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_EMPTY                          , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_EMPTY );
+REG64_FLD( PU_OCB_OCI_OCBSLCS3_SPARE                               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_OCB_OCI_OCBSLCS3_SPARE_LEN                           , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_INTR_ACTION_0_1                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_INTR_ACTION_0_1 );
+REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_INTR_ACTION_0_1_LEN            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_LENGTH                         , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_LENGTH );
+REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_LENGTH_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_LENGTH_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_WRITE_PTR                      , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_WRITE_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_WRITE_PTR_LEN                  , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_WRITE_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_READ_PTR                       , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_READ_PTR );
+REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_READ_PTR_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_READ_PTR_LEN );
+REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_ENABLE                         , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PULL_ENABLE );
+
+REG64_FLD( PU_OCB_OCI_OCCFLG_OCC_FLAGS                             , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCC_FLAGS  );
+REG64_FLD( PU_OCB_OCI_OCCFLG_OCC_FLAGS_LEN                         , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCC_FLAGS_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCCHBR_OCC_HEARTBEAT_COUNT                   , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_HEARTBEAT_COUNT );
+REG64_FLD( PU_OCB_OCI_OCCHBR_OCC_HEARTBEAT_COUNT_LEN               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_HEARTBEAT_COUNT_LEN );
+REG64_FLD( PU_OCB_OCI_OCCHBR_OCC_HEARTBEAT_EN                      , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_HEARTBEAT_EN );
+
+REG64_FLD( PU_OCB_OCI_OCCMISC_CORE_EXT_INTR                        , 0   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_CORE_EXT_INTR );
+REG64_FLD( PU_OCB_OCI_OCCMISC_SPARE_1_3                            , 1   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_SPARE_1_3  );
+REG64_FLD( PU_OCB_OCI_OCCMISC_SPARE_1_3_LEN                        , 3   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_SPARE_1_3_LEN );
+REG64_FLD( PU_OCB_OCI_OCCMISC_PVREF_ERROR_EN                       , 4   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PVREF_ERROR_EN );
+REG64_FLD( PU_OCB_OCI_OCCMISC_PVREF_ERROR_EN_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PVREF_ERROR_EN_LEN );
+REG64_FLD( PU_OCB_OCI_OCCMISC_PVREF_ERROR_GROSS                    , 6   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PVREF_ERROR_GROSS );
+REG64_FLD( PU_OCB_OCI_OCCMISC_PVREF_ERROR_FINE                     , 7   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PVREF_ERROR_FINE );
+REG64_FLD( PU_OCB_OCI_OCCMISC_FIRMWARE_FAULT                       , 8   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_FIRMWARE_FAULT );
+REG64_FLD( PU_OCB_OCI_OCCMISC_FIRMWARE_NOTIFY                      , 9   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_FIRMWARE_NOTIFY );
+REG64_FLD( PU_OCB_OCI_OCCMISC_SPARE                                , 10  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_OCB_OCI_OCCMISC_SPARE_LEN                            , 6   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_OCB_OCI_OCCMISC_I2CM_INTR_STATUS                     , 16  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_I2CM_INTR_STATUS );
+REG64_FLD( PU_OCB_OCI_OCCMISC_I2CM_INTR_STATUS_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_I2CM_INTR_STATUS_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCCS0_OCC_SCRATCH_N                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_SCRATCH_N );
+REG64_FLD( PU_OCB_OCI_OCCS0_OCC_SCRATCH_N_LEN                      , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_SCRATCH_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCCS1_OCC_SCRATCH_N                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_SCRATCH_N );
+REG64_FLD( PU_OCB_OCI_OCCS1_OCC_SCRATCH_N_LEN                      , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_SCRATCH_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCCS2_OCC_SCRATCH_N                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_SCRATCH_N );
+REG64_FLD( PU_OCB_OCI_OCCS2_OCC_SCRATCH_N_LEN                      , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_SCRATCH_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OCICFG_M0_PRIORITY                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M0_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OCICFG_M0_PRIORITY_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M0_PRIORITY_LEN );
+REG64_FLD( PU_OCB_OCI_OCICFG_M1_PRIORITY                           , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M1_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OCICFG_M1_PRIORITY_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M1_PRIORITY_LEN );
+REG64_FLD( PU_OCB_OCI_OCICFG_M2_PRIORITY                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M2_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OCICFG_M2_PRIORITY_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M2_PRIORITY_LEN );
+REG64_FLD( PU_OCB_OCI_OCICFG_M3_PRIORITY                           , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M3_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OCICFG_M3_PRIORITY_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M3_PRIORITY_LEN );
+REG64_FLD( PU_OCB_OCI_OCICFG_M4_PRIORITY                           , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M4_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OCICFG_M4_PRIORITY_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M4_PRIORITY_LEN );
+REG64_FLD( PU_OCB_OCI_OCICFG_M5_PRIORITY                           , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M5_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OCICFG_M5_PRIORITY_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M5_PRIORITY_LEN );
+REG64_FLD( PU_OCB_OCI_OCICFG_M6_PRIORITY                           , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M6_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OCICFG_M6_PRIORITY_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M6_PRIORITY_LEN );
+REG64_FLD( PU_OCB_OCI_OCICFG_M7_PRIORITY                           , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M7_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OCICFG_M7_PRIORITY_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M7_PRIORITY_LEN );
+REG64_FLD( PU_OCB_OCI_OCICFG_M0_PRIORITY_SEL                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M0_PRIORITY_SEL );
+REG64_FLD( PU_OCB_OCI_OCICFG_M1_PRIORITY_SEL                       , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M1_PRIORITY_SEL );
+REG64_FLD( PU_OCB_OCI_OCICFG_M2_PRIORITY_SEL                       , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M2_PRIORITY_SEL );
+REG64_FLD( PU_OCB_OCI_OCICFG_M3_PRIORITY_SEL                       , 19  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M3_PRIORITY_SEL );
+REG64_FLD( PU_OCB_OCI_OCICFG_OCICFG_RESERVED_20                    , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCICFG_RESERVED_20 );
+REG64_FLD( PU_OCB_OCI_OCICFG_M5_PRIORITY_SEL                       , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M5_PRIORITY_SEL );
+REG64_FLD( PU_OCB_OCI_OCICFG_OCICFG_RESERVED_23                    , 22  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCICFG_RESERVED_23 );
+REG64_FLD( PU_OCB_OCI_OCICFG_M7_PRIORITY_SEL                       , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_M7_PRIORITY_SEL );
+REG64_FLD( PU_OCB_OCI_OCICFG_PLBARB_LOCKERR                        , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PLBARB_LOCKERR );
+REG64_FLD( PU_OCB_OCI_OCICFG_SPARE_24_31                           , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_24_31 );
+REG64_FLD( PU_OCB_OCI_OCICFG_SPARE_24_31_LEN                       , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_24_31_LEN );
+
+REG64_FLD( PU_OCB_OCI_OEHDR_EVENT2HALT_DELAY                       , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT2HALT_DELAY );
+REG64_FLD( PU_OCB_OCI_OEHDR_EVENT2HALT_DELAY_LEN                   , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT2HALT_DELAY_LEN );
+
+REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_SRC_SEL                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HTM_SRC_SEL );
+REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_SRC_SEL_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HTM_SRC_SEL_LEN );
+REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_STOP                              , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HTM_STOP   );
+REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_MARKER_SLAVE_ADRS                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HTM_MARKER_SLAVE_ADRS );
+REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_MARKER_SLAVE_ADRS_LEN             , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HTM_MARKER_SLAVE_ADRS_LEN );
+REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_MODE                       , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENT2HALT_MODE );
+REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_MODE_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENT2HALT_MODE_LEN );
+REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_EN                         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENT2HALT_EN );
+REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_EN_LEN                     , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENT2HALT_EN_LEN );
+REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_GPE_SRC_SEL                       , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HTM_GPE_SRC_SEL );
+REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_GPE_SRC_SEL_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HTM_GPE_SRC_SEL_LEN );
+REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_OCC                        , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENT2HALT_OCC );
+REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE0                       , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENT2HALT_GPE0 );
+REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE1                       , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENT2HALT_GPE1 );
+REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE2                       , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENT2HALT_GPE2 );
+REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE3                       , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENT2HALT_GPE3 );
+REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_HALT_STATE                 , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENT2HALT_HALT_STATE );
+
+REG64_FLD( PU_OCB_OCI_OIEPR0_INTERRUPT_EDGE_POL_N                  , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_EDGE_POL_N );
+REG64_FLD( PU_OCB_OCI_OIEPR0_INTERRUPT_EDGE_POL_N_LEN              , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_EDGE_POL_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OIEPR1_INTERRUPT_EDGE_POL_N                  , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_EDGE_POL_N );
+REG64_FLD( PU_OCB_OCI_OIEPR1_INTERRUPT_EDGE_POL_N_LEN              , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_EDGE_POL_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OIMR0_INTERRUPT_MASK_N                       , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_MASK_N );
+REG64_FLD( PU_OCB_OCI_OIMR0_INTERRUPT_MASK_N_LEN                   , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_MASK_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OIMR1_INTERRUPT_MASK_N                       , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_MASK_N );
+REG64_FLD( PU_OCB_OCI_OIMR1_INTERRUPT_MASK_N_LEN                   , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_MASK_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OIRR0A_INTERRUPT_ROUTE_A_N                   , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_OCB_OCI_OIRR0A_INTERRUPT_ROUTE_A_N_LEN               , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OIRR0B_INTERRUPT_ROUTE_A_N                   , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_OCB_OCI_OIRR0B_INTERRUPT_ROUTE_A_N_LEN               , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OIRR0C_INTERRUPT_ROUTE_A_N                   , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_OCB_OCI_OIRR0C_INTERRUPT_ROUTE_A_N_LEN               , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OIRR1A_INTERRUPT_ROUTE_A_N                   , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_OCB_OCI_OIRR1A_INTERRUPT_ROUTE_A_N_LEN               , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OIRR1B_INTERRUPT_ROUTE_A_N                   , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_OCB_OCI_OIRR1B_INTERRUPT_ROUTE_A_N_LEN               , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OIRR1C_INTERRUPT_ROUTE_A_N                   , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_ROUTE_A_N );
+REG64_FLD( PU_OCB_OCI_OIRR1C_INTERRUPT_ROUTE_A_N_LEN               , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_ROUTE_A_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OISR0_DEBUGGER                               , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( PU_OCB_OCI_OISR0_TRACE_TRIGGER                          , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_TRACE_TRIGGER );
+REG64_FLD( PU_OCB_OCI_OISR0_OCC_ERROR                              , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCC_ERROR  );
+REG64_FLD( PU_OCB_OCI_OISR0_PBA_ERROR                              , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBA_ERROR  );
+REG64_FLD( PU_OCB_OCI_OISR0_SRT_ERROR                              , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_ERROR  );
+REG64_FLD( PU_OCB_OCI_OISR0_GPE0_ERROR                             , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE0_ERROR );
+REG64_FLD( PU_OCB_OCI_OISR0_GPE1_ERROR                             , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE1_ERROR );
+REG64_FLD( PU_OCB_OCI_OISR0_GPE2_ERROR                             , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE2_ERROR );
+REG64_FLD( PU_OCB_OCI_OISR0_GPE3_ERROR                             , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE3_ERROR );
+REG64_FLD( PU_OCB_OCI_OISR0_PPC405_HALT                            , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPC405_HALT );
+REG64_FLD( PU_OCB_OCI_OISR0_ERROR                                  , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ERROR      );
+REG64_FLD( PU_OCB_OCI_OISR0_SPARE_11                               , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_11   );
+REG64_FLD( PU_OCB_OCI_OISR0_CHECK_STOP_PPC405                      , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CHECK_STOP_PPC405 );
+REG64_FLD( PU_OCB_OCI_OISR0_CHECK_STOP_GPE0                        , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CHECK_STOP_GPE0 );
+REG64_FLD( PU_OCB_OCI_OISR0_CHECK_STOP_GPE1                        , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CHECK_STOP_GPE1 );
+REG64_FLD( PU_OCB_OCI_OISR0_CHECK_STOP_GPE2                        , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CHECK_STOP_GPE2 );
+REG64_FLD( PU_OCB_OCI_OISR0_CHECK_STOP_GPE3                        , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CHECK_STOP_GPE3 );
+REG64_FLD( PU_OCB_OCI_OISR0_OCC_MALF_ALERT                         , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCC_MALF_ALERT );
+REG64_FLD( PU_OCB_OCI_OISR0_ADU_MALF_ALERT                         , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ADU_MALF_ALERT );
+REG64_FLD( PU_OCB_OCI_OISR0_EXTERNAL_TRAP                          , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_EXTERNAL_TRAP );
+REG64_FLD( PU_OCB_OCI_OISR0_IVRM_PVREF_ERROR                       , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IVRM_PVREF_ERROR );
+REG64_FLD( PU_OCB_OCI_OISR0_OCC_TIMER0                             , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCC_TIMER0 );
+REG64_FLD( PU_OCB_OCI_OISR0_OCC_TIMER1                             , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCC_TIMER1 );
+REG64_FLD( PU_OCB_OCI_OISR0_AVS_SLAVE0                             , 23  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AVS_SLAVE0 );
+REG64_FLD( PU_OCB_OCI_OISR0_AVS_SLAVE1                             , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AVS_SLAVE1 );
+REG64_FLD( PU_OCB_OCI_OISR0_IPI0_HI_PRIORITY                       , 25  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IPI0_HI_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OISR0_IPI1_HI_PRIORITY                       , 26  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IPI1_HI_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OISR0_IPI2_HI_PRIORITY                       , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IPI2_HI_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OISR0_IPI3_HI_PRIORITY                       , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IPI3_HI_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OISR0_IPI4_HI_PRIORITY                       , 29  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IPI4_HI_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OISR0_ADCFSM_ONGOING                         , 30  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ADCFSM_ONGOING );
+REG64_FLD( PU_OCB_OCI_OISR0_I2CM_INTER                             , 31  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_I2CM_INTER );
+
+REG64_FLD( PU_OCB_OCI_OISR1_PBAX_OCC_SEND_ATTN                     , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBAX_OCC_SEND_ATTN );
+REG64_FLD( PU_OCB_OCI_OISR1_PBAX_OCC_PUSH0                         , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBAX_OCC_PUSH0 );
+REG64_FLD( PU_OCB_OCI_OISR1_PBAX_OCC_PUSH1                         , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBAX_OCC_PUSH1 );
+REG64_FLD( PU_OCB_OCI_OISR1_PBA_BCDE_ATTN                          , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBA_BCDE_ATTN );
+REG64_FLD( PU_OCB_OCI_OISR1_PBA_BCUE_ATTN                          , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBA_BCUE_ATTN );
+REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM0_PULL                         , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCC_STRM0_PULL );
+REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM0_PUSH                         , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCC_STRM0_PUSH );
+REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM1_PULL                         , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCC_STRM1_PULL );
+REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM1_PUSH                         , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCC_STRM1_PUSH );
+REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM2_PULL                         , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCC_STRM2_PULL );
+REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM2_PUSH                         , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCC_STRM2_PUSH );
+REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM3_PULL                         , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCC_STRM3_PULL );
+REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM3_PUSH                         , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCC_STRM3_PUSH );
+REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE0_PENDING             , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMC_PCB_INTR_TYPE0_PENDING );
+REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE1_PENDING             , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMC_PCB_INTR_TYPE1_PENDING );
+REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE2_PENDING             , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMC_PCB_INTR_TYPE2_PENDING );
+REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE3_PENDING             , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMC_PCB_INTR_TYPE3_PENDING );
+REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE4_PENDING             , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMC_PCB_INTR_TYPE4_PENDING );
+REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE5_PENDING             , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMC_PCB_INTR_TYPE5_PENDING );
+REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE6_PENDING             , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMC_PCB_INTR_TYPE6_PENDING );
+REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE7_PENDING             , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMC_PCB_INTR_TYPE7_PENDING );
+REG64_FLD( PU_OCB_OCI_OISR1_PMC_O2S_0A_ONGOING                     , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMC_O2S_0A_ONGOING );
+REG64_FLD( PU_OCB_OCI_OISR1_PMC_O2S_0B_ONGOING                     , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMC_O2S_0B_ONGOING );
+REG64_FLD( PU_OCB_OCI_OISR1_PMC_O2S_1A_ONGOING                     , 23  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMC_O2S_1A_ONGOING );
+REG64_FLD( PU_OCB_OCI_OISR1_PMC_O2S_1B_ONGOING                     , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMC_O2S_1B_ONGOING );
+REG64_FLD( PU_OCB_OCI_OISR1_PSSBRIDGE_ONGOING                      , 25  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSSBRIDGE_ONGOING );
+REG64_FLD( PU_OCB_OCI_OISR1_IPI0_LO_PRIORITY                       , 26  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IPI0_LO_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OISR1_IPI1_LO_PRIORITY                       , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IPI1_LO_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OISR1_IPI2_LO_PRIORITY                       , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IPI2_LO_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OISR1_IPI3_LO_PRIORITY                       , 29  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IPI3_LO_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OISR1_IPI4_LO_PRIORITY                       , 30  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IPI4_LO_PRIORITY );
+REG64_FLD( PU_OCB_OCI_OISR1_SPARE_31                               , 31  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_31   );
+
+REG64_FLD( PU_OCB_OCI_OITR0_INTERRUPT_TYPE_N                       , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_TYPE_N );
+REG64_FLD( PU_OCB_OCI_OITR0_INTERRUPT_TYPE_N_LEN                   , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_TYPE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OITR1_INTERRUPT_TYPE_N                       , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_TYPE_N );
+REG64_FLD( PU_OCB_OCI_OITR1_INTERRUPT_TYPE_N_LEN                   , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_TYPE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C1_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C1_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C10_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C10_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C11_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C11_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C12_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C12_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C13_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C13_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C14_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C14_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C15_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C15_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C16_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C16_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C17_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C17_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C18_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C18_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C19_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C19_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C2_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C2_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C20_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C20_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C21_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C21_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C22_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C22_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C23_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C23_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C3_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C3_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C4_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C4_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C5_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C5_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C6_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C6_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C7_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C7_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C8_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C8_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0C9_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT0C9_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_0           , 0   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_1           , 1   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_2           , 2   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_3           , 3   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_4           , 4   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_5           , 5   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_6           , 6   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_7           , 7   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_8           , 8   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_9           , 9   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_10          , 10  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_11          , 11  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_12          , 12  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_13          , 13  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_14          , 14  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_15          , 15  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_16          , 16  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_17          , 17  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_18          , 18  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_19          , 19  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_20          , 20  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_21          , 21  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_22          , 22  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_23          , 23  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C0_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C0_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C1_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C1_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C10_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C10_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C11_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C11_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C12_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C12_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C13_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C13_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C14_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C14_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C15_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C15_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C16_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C16_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C17_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C17_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C18_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C18_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C19_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C19_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C2_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C2_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C20_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C20_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C21_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C21_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C22_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C22_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C23_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C23_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C3_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C3_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C4_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C4_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C5_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C5_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C6_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C6_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C7_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C7_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C8_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C8_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1C9_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT1C9_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_0           , 0   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_1           , 1   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_2           , 2   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_3           , 3   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_4           , 4   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_5           , 5   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_6           , 6   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_7           , 7   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_8           , 8   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_9           , 9   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_10          , 10  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_11          , 11  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_12          , 12  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_13          , 13  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_14          , 14  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_15          , 15  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_16          , 16  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_17          , 17  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_18          , 18  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_19          , 19  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_20          , 20  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_21          , 21  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_22          , 22  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_23          , 23  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C0_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C0_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C1_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C1_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C10_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C10_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C11_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C11_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C12_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C12_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C13_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C13_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C14_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C14_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C15_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C15_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C16_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C16_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C17_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C17_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C18_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C18_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C19_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C19_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C2_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C2_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C20_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C20_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C21_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C21_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C22_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C22_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C23_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C23_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C3_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C3_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C4_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C4_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C5_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C5_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C6_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C6_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C7_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C7_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C8_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C8_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2C9_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT2C9_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_0           , 0   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_1           , 1   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_2           , 2   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_3           , 3   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_4           , 4   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_5           , 5   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_6           , 6   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_7           , 7   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_8           , 8   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_9           , 9   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_10          , 10  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_11          , 11  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_12          , 12  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_13          , 13  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_14          , 14  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_15          , 15  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_16          , 16  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_17          , 17  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_18          , 18  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_19          , 19  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_20          , 20  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_21          , 21  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_22          , 22  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_23          , 23  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C0_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C0_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C1_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C1_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C10_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C10_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C11_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C11_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C12_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C12_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C13_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C13_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C14_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C14_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C15_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C15_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C16_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C16_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C17_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C17_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C18_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C18_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C19_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C19_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C2_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C2_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C20_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C20_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C21_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C21_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C22_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C22_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C23_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C23_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C3_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C3_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C4_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C4_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C5_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C5_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C6_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C6_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C7_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C7_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C8_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C8_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3C9_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT3C9_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_0           , 0   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_1           , 1   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_2           , 2   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_3           , 3   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_4           , 4   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_5           , 5   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_6           , 6   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_7           , 7   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_8           , 8   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_9           , 9   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_10          , 10  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_11          , 11  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_12          , 12  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_13          , 13  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_14          , 14  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_15          , 15  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_16          , 16  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_17          , 17  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_18          , 18  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_19          , 19  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_20          , 20  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_21          , 21  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_22          , 22  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_23          , 23  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C0_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C0_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C1_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C1_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C10_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C10_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C11_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C11_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C12_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C12_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C13_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C13_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C14_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C14_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C15_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C15_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C16_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C16_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C17_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C17_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C18_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C18_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C19_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C19_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C2_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C2_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C20_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C20_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C21_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C21_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C22_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C22_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C23_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C23_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C3_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C3_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C4_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C4_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C5_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C5_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C6_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C6_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C7_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C7_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C8_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C8_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4C9_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT4C9_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_0           , 0   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_1           , 1   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_2           , 2   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_3           , 3   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_4           , 4   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_5           , 5   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_6           , 6   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_7           , 7   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_8           , 8   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_9           , 9   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_10          , 10  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_11          , 11  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_12          , 12  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_13          , 13  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_14          , 14  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_15          , 15  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_16          , 16  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_17          , 17  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_18          , 18  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_19          , 19  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_20          , 20  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_21          , 21  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_22          , 22  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_23          , 23  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C0_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C0_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C1_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C1_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C10_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C10_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C11_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C11_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C12_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C12_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C13_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C13_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C14_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C14_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C15_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C15_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C16_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C16_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C17_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C17_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C18_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C18_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C19_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C19_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C2_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C2_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C20_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C20_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C21_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C21_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C22_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C22_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C23_PCB_INTR_TYPE_A_CORE_N              , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C23_PCB_INTR_TYPE_A_CORE_N_LEN          , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C3_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C3_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C4_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C4_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C5_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C5_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C6_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C6_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C7_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C7_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C8_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C8_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5C9_PCB_INTR_TYPE_A_CORE_N               , 20  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N );
+REG64_FLD( PU_OCB_OCI_OPIT5C9_PCB_INTR_TYPE_A_CORE_N_LEN           , 12  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_0           , 0   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_1           , 1   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_2           , 2   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_3           , 3   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_4           , 4   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_5           , 5   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_6           , 6   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_6 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_7           , 7   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_7 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_8           , 8   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_8 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_9           , 9   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_9 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_10          , 10  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_10 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_11          , 11  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_11 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_12          , 12  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_12 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_13          , 13  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_13 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_14          , 14  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_14 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_15          , 15  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_15 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_16          , 16  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_16 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_17          , 17  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_17 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_18          , 18  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_18 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_19          , 19  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_19 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_20          , 20  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_20 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_21          , 21  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_21 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_22          , 22  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_22 );
+REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_23          , 23  , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_23 );
+
+REG64_FLD( PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_0           , 0   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_1           , 1   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_2           , 2   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_3           , 3   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_4           , 4   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_5           , 5   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+
+REG64_FLD( PU_OCB_OCI_OPIT6Q0_PCB_INTR_TYPE_A_QUAD_N               , 28  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_OCB_OCI_OPIT6Q0_PCB_INTR_TYPE_A_QUAD_N_LEN           , 4   , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT6Q1_PCB_INTR_TYPE_A_QUAD_N               , 28  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_OCB_OCI_OPIT6Q1_PCB_INTR_TYPE_A_QUAD_N_LEN           , 4   , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT6Q2_PCB_INTR_TYPE_A_QUAD_N               , 28  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_OCB_OCI_OPIT6Q2_PCB_INTR_TYPE_A_QUAD_N_LEN           , 4   , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT6Q3_PCB_INTR_TYPE_A_QUAD_N               , 28  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_OCB_OCI_OPIT6Q3_PCB_INTR_TYPE_A_QUAD_N_LEN           , 4   , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT6Q4_PCB_INTR_TYPE_A_QUAD_N               , 28  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_OCB_OCI_OPIT6Q4_PCB_INTR_TYPE_A_QUAD_N_LEN           , 4   , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT6Q5_PCB_INTR_TYPE_A_QUAD_N               , 28  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_OCB_OCI_OPIT6Q5_PCB_INTR_TYPE_A_QUAD_N_LEN           , 4   , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_0           , 0   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_0 );
+REG64_FLD( PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_1           , 1   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_1 );
+REG64_FLD( PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_2           , 2   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_2 );
+REG64_FLD( PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_3           , 3   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_3 );
+REG64_FLD( PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_4           , 4   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_4 );
+REG64_FLD( PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_5           , 5   , SH_UNT          , SH_ACS_SCOM1_CLEAR,
+           SH_FLD_PCB_INTR_TYPE_N_PENDING_5 );
+
+REG64_FLD( PU_OCB_OCI_OPIT7Q0_PCB_INTR_TYPE_A_QUAD_N               , 28  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_OCB_OCI_OPIT7Q0_PCB_INTR_TYPE_A_QUAD_N_LEN           , 4   , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT7Q1_PCB_INTR_TYPE_A_QUAD_N               , 28  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_OCB_OCI_OPIT7Q1_PCB_INTR_TYPE_A_QUAD_N_LEN           , 4   , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT7Q2_PCB_INTR_TYPE_A_QUAD_N               , 28  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_OCB_OCI_OPIT7Q2_PCB_INTR_TYPE_A_QUAD_N_LEN           , 4   , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT7Q3_PCB_INTR_TYPE_A_QUAD_N               , 28  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_OCB_OCI_OPIT7Q3_PCB_INTR_TYPE_A_QUAD_N_LEN           , 4   , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT7Q4_PCB_INTR_TYPE_A_QUAD_N               , 28  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_OCB_OCI_OPIT7Q4_PCB_INTR_TYPE_A_QUAD_N_LEN           , 4   , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OPIT7Q5_PCB_INTR_TYPE_A_QUAD_N               , 28  , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N );
+REG64_FLD( PU_OCB_OCI_OPIT7Q5_PCB_INTR_TYPE_A_QUAD_N_LEN           , 4   , SH_UNT          , SH_ACS_SCOM1_RO ,
+           SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OTBR_TIMEBASE                                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( PU_OCB_OCI_OTBR_TIMEBASE_LEN                            , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMEBASE_LEN );
+
+REG64_FLD( PU_OCB_OCI_OTR0_TIMEOUT_N                               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_N  );
+REG64_FLD( PU_OCB_OCI_OTR0_CONTROL_N                               , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CONTROL_N  );
+REG64_FLD( PU_OCB_OCI_OTR0_AUTO_RELOAD_N                           , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_RELOAD_N );
+REG64_FLD( PU_OCB_OCI_OTR0_SPARE_N                                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_N    );
+REG64_FLD( PU_OCB_OCI_OTR0_SPARE_N_LEN                             , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_N_LEN );
+REG64_FLD( PU_OCB_OCI_OTR0_TIMER_N                                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_N    );
+REG64_FLD( PU_OCB_OCI_OTR0_TIMER_N_LEN                             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_OTR1_TIMEOUT_N                               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_N  );
+REG64_FLD( PU_OCB_OCI_OTR1_CONTROL_N                               , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CONTROL_N  );
+REG64_FLD( PU_OCB_OCI_OTR1_AUTO_RELOAD_N                           , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_RELOAD_N );
+REG64_FLD( PU_OCB_OCI_OTR1_SPARE_N                                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_N    );
+REG64_FLD( PU_OCB_OCI_OTR1_SPARE_N_LEN                             , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_N_LEN );
+REG64_FLD( PU_OCB_OCI_OTR1_TIMER_N                                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_N    );
+REG64_FLD( PU_OCB_OCI_OTR1_TIMER_N_LEN                             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_N_LEN );
+
+REG64_FLD( PU_OCB_OCI_QCSR_CORE_CONFIG                             , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CORE_CONFIG );
+REG64_FLD( PU_OCB_OCI_QCSR_CORE_CONFIG_LEN                         , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CORE_CONFIG_LEN );
+REG64_FLD( PU_OCB_OCI_QCSR_RESERVED_24_31                          , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_24_31 );
+REG64_FLD( PU_OCB_OCI_QCSR_RESERVED_24_31_LEN                      , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_24_31_LEN );
+
+REG64_FLD( PU_OCB_OCI_QSSR_L2_STOPPED                              , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_STOPPED );
+REG64_FLD( PU_OCB_OCI_QSSR_L2_STOPPED_LEN                          , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_STOPPED_LEN );
+REG64_FLD( PU_OCB_OCI_QSSR_L3_STOPPED                              , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_STOPPED );
+REG64_FLD( PU_OCB_OCI_QSSR_L3_STOPPED_LEN                          , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_STOPPED_LEN );
+REG64_FLD( PU_OCB_OCI_QSSR_QUAD_STOPPED                            , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_QUAD_STOPPED );
+REG64_FLD( PU_OCB_OCI_QSSR_QUAD_STOPPED_LEN                        , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_QUAD_STOPPED_LEN );
+REG64_FLD( PU_OCB_OCI_QSSR_RESERVED_30                             , 30  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_30 );
+REG64_FLD( PU_OCB_OCI_QSSR_CHANGE_IN_PROGRESS                      , 31  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CHANGE_IN_PROGRESS );
+
+REG64_FLD( PU_OCB_PIB_OACR_OCI_PRIORITY_MODE                       , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_PRIORITY_MODE );
+REG64_FLD( PU_OCB_PIB_OACR_OCI_PRIORITY_ORDER                      , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_PRIORITY_ORDER );
+REG64_FLD( PU_OCB_PIB_OACR_OCI_PRIORITY_ORDER_LEN                  , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_PRIORITY_ORDER_LEN );
+REG64_FLD( PU_OCB_PIB_OACR_OCI_HI_BUS_MODE                         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_HI_BUS_MODE );
+REG64_FLD( PU_OCB_PIB_OACR_OCI_READ_PIPELINE_CONTROL               , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_READ_PIPELINE_CONTROL );
+REG64_FLD( PU_OCB_PIB_OACR_OCI_READ_PIPELINE_CONTROL_LEN           , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_READ_PIPELINE_CONTROL_LEN );
+REG64_FLD( PU_OCB_PIB_OACR_OCI_WRITE_PIPELINE_CONTROL              , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_WRITE_PIPELINE_CONTROL );
+
+REG64_FLD( PU_OCB_PIB_OCBAR0_OCI_REGION                            , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_REGION );
+REG64_FLD( PU_OCB_PIB_OCBAR0_OCI_REGION_LEN                        , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_REGION_LEN );
+REG64_FLD( PU_OCB_PIB_OCBAR0_ADDRESS                               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_OCB_PIB_OCBAR0_ADDRESS_LEN                           , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_OCB_PIB_OCBAR1_OCI_REGION                            , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_REGION );
+REG64_FLD( PU_OCB_PIB_OCBAR1_OCI_REGION_LEN                        , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_REGION_LEN );
+REG64_FLD( PU_OCB_PIB_OCBAR1_ADDRESS                               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_OCB_PIB_OCBAR1_ADDRESS_LEN                           , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_OCB_PIB_OCBAR2_OCI_REGION                            , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_REGION );
+REG64_FLD( PU_OCB_PIB_OCBAR2_OCI_REGION_LEN                        , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_REGION_LEN );
+REG64_FLD( PU_OCB_PIB_OCBAR2_ADDRESS                               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_OCB_PIB_OCBAR2_ADDRESS_LEN                           , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_OCB_PIB_OCBAR3_OCI_REGION                            , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_REGION );
+REG64_FLD( PU_OCB_PIB_OCBAR3_OCI_REGION_LEN                        , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_REGION_LEN );
+REG64_FLD( PU_OCB_PIB_OCBAR3_ADDRESS                               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_OCB_PIB_OCBAR3_ADDRESS_LEN                           , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_OCB_PIB_OCBCSR0_PULL_READ_UNDERFLOW                  , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PULL_READ_UNDERFLOW );
+REG64_FLD( PU_OCB_PIB_OCBCSR0_PUSH_WRITE_OVERFLOW                  , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PUSH_WRITE_OVERFLOW );
+REG64_FLD( PU_OCB_PIB_OCBCSR0_PULL_READ_UNDERFLOW_EN               , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PULL_READ_UNDERFLOW_EN );
+REG64_FLD( PU_OCB_PIB_OCBCSR0_PUSH_WRITE_OVERFLOW_EN               , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PUSH_WRITE_OVERFLOW_EN );
+REG64_FLD( PU_OCB_PIB_OCBCSR0_STREAM_MODE                          , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_STREAM_MODE );
+REG64_FLD( PU_OCB_PIB_OCBCSR0_STREAM_TYPE                          , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_STREAM_TYPE );
+REG64_FLD( PU_OCB_PIB_OCBCSR0_SPARE0                               , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_OCB_PIB_OCBCSR0_SPARE0_LEN                           , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE0_LEN );
+REG64_FLD( PU_OCB_PIB_OCBCSR0_OCI_TIMEOUT                          , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_TIMEOUT );
+REG64_FLD( PU_OCB_PIB_OCBCSR0_OCI_READ_DATA_PARITY                 , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_READ_DATA_PARITY );
+REG64_FLD( PU_OCB_PIB_OCBCSR0_OCI_SLAVE_ERROR                      , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_SLAVE_ERROR );
+REG64_FLD( PU_OCB_PIB_OCBCSR0_ADDR_PARITY_ERR                      , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ADDR_PARITY_ERR );
+REG64_FLD( PU_OCB_PIB_OCBCSR0_DATA_PARITY_ERR                      , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA_PARITY_ERR );
+REG64_FLD( PU_OCB_PIB_OCBCSR0_SPARE1                               , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE1     );
+REG64_FLD( PU_OCB_PIB_OCBCSR0_FSM_ERR                              , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FSM_ERR    );
+REG64_FLD( PU_OCB_PIB_OCBCSR0_SPARE2                               , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE2     );
+
+REG64_FLD( PU_OCB_PIB_OCBCSR1_PULL_READ_UNDERFLOW                  , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PULL_READ_UNDERFLOW );
+REG64_FLD( PU_OCB_PIB_OCBCSR1_PUSH_WRITE_OVERFLOW                  , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PUSH_WRITE_OVERFLOW );
+REG64_FLD( PU_OCB_PIB_OCBCSR1_PULL_READ_UNDERFLOW_EN               , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PULL_READ_UNDERFLOW_EN );
+REG64_FLD( PU_OCB_PIB_OCBCSR1_PUSH_WRITE_OVERFLOW_EN               , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PUSH_WRITE_OVERFLOW_EN );
+REG64_FLD( PU_OCB_PIB_OCBCSR1_STREAM_MODE                          , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_STREAM_MODE );
+REG64_FLD( PU_OCB_PIB_OCBCSR1_STREAM_TYPE                          , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_STREAM_TYPE );
+REG64_FLD( PU_OCB_PIB_OCBCSR1_SPARE0                               , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_OCB_PIB_OCBCSR1_SPARE0_LEN                           , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE0_LEN );
+REG64_FLD( PU_OCB_PIB_OCBCSR1_OCI_TIMEOUT                          , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_TIMEOUT );
+REG64_FLD( PU_OCB_PIB_OCBCSR1_OCI_READ_DATA_PARITY                 , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_READ_DATA_PARITY );
+REG64_FLD( PU_OCB_PIB_OCBCSR1_OCI_SLAVE_ERROR                      , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_SLAVE_ERROR );
+REG64_FLD( PU_OCB_PIB_OCBCSR1_ADDR_PARITY_ERR                      , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ADDR_PARITY_ERR );
+REG64_FLD( PU_OCB_PIB_OCBCSR1_DATA_PARITY_ERR                      , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA_PARITY_ERR );
+REG64_FLD( PU_OCB_PIB_OCBCSR1_SPARE1                               , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE1     );
+REG64_FLD( PU_OCB_PIB_OCBCSR1_FSM_ERR                              , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FSM_ERR    );
+REG64_FLD( PU_OCB_PIB_OCBCSR1_SPARE2                               , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE2     );
+
+REG64_FLD( PU_OCB_PIB_OCBCSR2_PULL_READ_UNDERFLOW                  , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PULL_READ_UNDERFLOW );
+REG64_FLD( PU_OCB_PIB_OCBCSR2_PUSH_WRITE_OVERFLOW                  , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PUSH_WRITE_OVERFLOW );
+REG64_FLD( PU_OCB_PIB_OCBCSR2_PULL_READ_UNDERFLOW_EN               , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PULL_READ_UNDERFLOW_EN );
+REG64_FLD( PU_OCB_PIB_OCBCSR2_PUSH_WRITE_OVERFLOW_EN               , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PUSH_WRITE_OVERFLOW_EN );
+REG64_FLD( PU_OCB_PIB_OCBCSR2_STREAM_MODE                          , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_STREAM_MODE );
+REG64_FLD( PU_OCB_PIB_OCBCSR2_STREAM_TYPE                          , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_STREAM_TYPE );
+REG64_FLD( PU_OCB_PIB_OCBCSR2_SPARE0                               , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_OCB_PIB_OCBCSR2_SPARE0_LEN                           , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE0_LEN );
+REG64_FLD( PU_OCB_PIB_OCBCSR2_OCI_TIMEOUT                          , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_TIMEOUT );
+REG64_FLD( PU_OCB_PIB_OCBCSR2_OCI_READ_DATA_PARITY                 , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_READ_DATA_PARITY );
+REG64_FLD( PU_OCB_PIB_OCBCSR2_OCI_SLAVE_ERROR                      , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_SLAVE_ERROR );
+REG64_FLD( PU_OCB_PIB_OCBCSR2_ADDR_PARITY_ERR                      , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ADDR_PARITY_ERR );
+REG64_FLD( PU_OCB_PIB_OCBCSR2_DATA_PARITY_ERR                      , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA_PARITY_ERR );
+REG64_FLD( PU_OCB_PIB_OCBCSR2_SPARE1                               , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE1     );
+REG64_FLD( PU_OCB_PIB_OCBCSR2_FSM_ERR                              , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FSM_ERR    );
+REG64_FLD( PU_OCB_PIB_OCBCSR2_SPARE2                               , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE2     );
+
+REG64_FLD( PU_OCB_PIB_OCBCSR3_PULL_READ_UNDERFLOW                  , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PULL_READ_UNDERFLOW );
+REG64_FLD( PU_OCB_PIB_OCBCSR3_PUSH_WRITE_OVERFLOW                  , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PUSH_WRITE_OVERFLOW );
+REG64_FLD( PU_OCB_PIB_OCBCSR3_PULL_READ_UNDERFLOW_EN               , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PULL_READ_UNDERFLOW_EN );
+REG64_FLD( PU_OCB_PIB_OCBCSR3_PUSH_WRITE_OVERFLOW_EN               , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PUSH_WRITE_OVERFLOW_EN );
+REG64_FLD( PU_OCB_PIB_OCBCSR3_STREAM_MODE                          , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_STREAM_MODE );
+REG64_FLD( PU_OCB_PIB_OCBCSR3_STREAM_TYPE                          , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_STREAM_TYPE );
+REG64_FLD( PU_OCB_PIB_OCBCSR3_SPARE0                               , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_OCB_PIB_OCBCSR3_SPARE0_LEN                           , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE0_LEN );
+REG64_FLD( PU_OCB_PIB_OCBCSR3_OCI_TIMEOUT                          , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_TIMEOUT );
+REG64_FLD( PU_OCB_PIB_OCBCSR3_OCI_READ_DATA_PARITY                 , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_READ_DATA_PARITY );
+REG64_FLD( PU_OCB_PIB_OCBCSR3_OCI_SLAVE_ERROR                      , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_SLAVE_ERROR );
+REG64_FLD( PU_OCB_PIB_OCBCSR3_ADDR_PARITY_ERR                      , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ADDR_PARITY_ERR );
+REG64_FLD( PU_OCB_PIB_OCBCSR3_DATA_PARITY_ERR                      , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA_PARITY_ERR );
+REG64_FLD( PU_OCB_PIB_OCBCSR3_SPARE1                               , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE1     );
+REG64_FLD( PU_OCB_PIB_OCBCSR3_FSM_ERR                              , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FSM_ERR    );
+REG64_FLD( PU_OCB_PIB_OCBCSR3_SPARE2                               , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE2     );
+
+REG64_FLD( PU_OCB_PIB_OCBDR0_DATA                                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_OCB_PIB_OCBDR0_DATA_LEN                              , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_OCB_PIB_OCBDR1_DATA                                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_OCB_PIB_OCBDR1_DATA_LEN                              , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_OCB_PIB_OCBDR2_DATA                                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_OCB_PIB_OCBDR2_DATA_LEN                              , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_OCB_PIB_OCBDR3_DATA                                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_OCB_PIB_OCBDR3_DATA_LEN                              , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_OCB_PIB_OCBEAR_ERROR_ADDRESS                         , 0   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_ERROR_ADDRESS );
+REG64_FLD( PU_OCB_PIB_OCBEAR_ERROR_ADDRESS_LEN                     , 32  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_ERROR_ADDRESS_LEN );
+REG64_FLD( PU_OCB_PIB_OCBEAR_RESERVED_32_34                        , 32  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RESERVED_32_34 );
+REG64_FLD( PU_OCB_PIB_OCBEAR_RESERVED_32_34_LEN                    , 3   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_RESERVED_32_34_LEN );
+REG64_FLD( PU_OCB_PIB_OCBEAR_DIRECT_BRIDGE_SOURCE                  , 35  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_DIRECT_BRIDGE_SOURCE );
+REG64_FLD( PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_0_SOURCE              , 36  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_INDIRECT_BRIDGE_0_SOURCE );
+REG64_FLD( PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_1_SOURCE              , 37  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_INDIRECT_BRIDGE_1_SOURCE );
+REG64_FLD( PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_2_SOURCE              , 38  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_INDIRECT_BRIDGE_2_SOURCE );
+REG64_FLD( PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_3_SOURCE              , 39  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_INDIRECT_BRIDGE_3_SOURCE );
+
+REG64_FLD( PU_OCB_PIB_OCBESR0_ERROR_ADDR                           , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_ERROR_ADDR );
+REG64_FLD( PU_OCB_PIB_OCBESR0_ERROR_ADDR_LEN                       , 32  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_ERROR_ADDR_LEN );
+
+REG64_FLD( PU_OCB_PIB_OCBESR1_ERROR_ADDR                           , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_ERROR_ADDR );
+REG64_FLD( PU_OCB_PIB_OCBESR1_ERROR_ADDR_LEN                       , 32  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_ERROR_ADDR_LEN );
+
+REG64_FLD( PU_OCB_PIB_OCBESR2_ERROR_ADDR                           , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_ERROR_ADDR );
+REG64_FLD( PU_OCB_PIB_OCBESR2_ERROR_ADDR_LEN                       , 32  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_ERROR_ADDR_LEN );
+
+REG64_FLD( PU_OCB_PIB_OCBESR3_ERROR_ADDR                           , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_ERROR_ADDR );
+REG64_FLD( PU_OCB_PIB_OCBESR3_ERROR_ADDR_LEN                       , 32  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_ERROR_ADDR_LEN );
+
+REG64_FLD( PU_OCB_PIB_OCDBG_MST_DIS_ABUSPAREN                      , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MST_DIS_ABUSPAREN );
+REG64_FLD( PU_OCB_PIB_OCDBG_MST_DIS_BEPAREN                        , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MST_DIS_BEPAREN );
+REG64_FLD( PU_OCB_PIB_OCDBG_MST_DIS_WRDBUSPAREN                    , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MST_DIS_WRDBUSPAREN );
+REG64_FLD( PU_OCB_PIB_OCDBG_MST_DIS_RDDBUSPAR                      , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MST_DIS_RDDBUSPAR );
+REG64_FLD( PU_OCB_PIB_OCDBG_MST_SPARE                              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MST_SPARE  );
+REG64_FLD( PU_OCB_PIB_OCDBG_SLV_DIS_SACK                           , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SLV_DIS_SACK );
+REG64_FLD( PU_OCB_PIB_OCDBG_SLV_DIS_ABUSPAR                        , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SLV_DIS_ABUSPAR );
+REG64_FLD( PU_OCB_PIB_OCDBG_SLV_DIS_BEPAR                          , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SLV_DIS_BEPAR );
+REG64_FLD( PU_OCB_PIB_OCDBG_SLV_DIS_BE                             , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SLV_DIS_BE );
+REG64_FLD( PU_OCB_PIB_OCDBG_SLV_DIS_WRDBUSPAR                      , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SLV_DIS_WRDBUSPAR );
+REG64_FLD( PU_OCB_PIB_OCDBG_SLV_DIS_RDDBUSPAREN                    , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SLV_DIS_RDDBUSPAREN );
+REG64_FLD( PU_OCB_PIB_OCDBG_SLV_SPARE                              , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SLV_SPARE  );
+REG64_FLD( PU_OCB_PIB_OCDBG_SPARE                                  , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_OCB_PIB_OCDBG_SPARE_LEN                              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_OCB_PIB_OCR_CORE_RESET                               , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CORE_RESET );
+REG64_FLD( PU_OCB_PIB_OCR_CHIP_RESET                               , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CHIP_RESET );
+REG64_FLD( PU_OCB_PIB_OCR_SYSTEM_RESET                             , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SYSTEM_RESET );
+REG64_FLD( PU_OCB_PIB_OCR_OCI_ARB_RESET                            , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_ARB_RESET );
+REG64_FLD( PU_OCB_PIB_OCR_TRACE_DISABLE                            , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_TRACE_DISABLE );
+REG64_FLD( PU_OCB_PIB_OCR_TRACE_EVENT                              , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_TRACE_EVENT );
+REG64_FLD( PU_OCB_PIB_OCR_DBG_UNCONDITIONAL_EVENT                  , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DBG_UNCONDITIONAL_EVENT );
+REG64_FLD( PU_OCB_PIB_OCR_EXT_INTERRUPT                            , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_EXT_INTERRUPT );
+REG64_FLD( PU_OCB_PIB_OCR_CRITICAL_INTERRUPT                       , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CRITICAL_INTERRUPT );
+REG64_FLD( PU_OCB_PIB_OCR_SLAVE_RESET_TO_405_ENABLE                , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SLAVE_RESET_TO_405_ENABLE );
+REG64_FLD( PU_OCB_PIB_OCR_OCR_DBG_HALT                             , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCR_DBG_HALT );
+REG64_FLD( PU_OCB_PIB_OCR_SPARE                                    , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_OCB_PIB_OCR_SPARE_LEN                                , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_OCB_PIB_OEAR_OCI_TIMEOUT_ADDR                        , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OCI_TIMEOUT_ADDR );
+REG64_FLD( PU_OCB_PIB_OEAR_OCI_TIMEOUT_ADDR_LEN                    , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OCI_TIMEOUT_ADDR_LEN );
+
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M0_TIMEOUT_ERROR                    , 0   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M0_TIMEOUT_ERROR );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M0_RW_STATUS                        , 1   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M0_RW_STATUS );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M0_FLCK                             , 2   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M0_FLCK );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M0_OEAR_LOCK                        , 3   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M0_OEAR_LOCK );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M1_TIMEOUT_ERROR                    , 4   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M1_TIMEOUT_ERROR );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M1_RW_STATUS                        , 5   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M1_RW_STATUS );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M1_FLCK                             , 6   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M1_FLCK );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M1_OEAR_LOCK                        , 7   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M1_OEAR_LOCK );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M2_TIMEOUT_ERROR                    , 8   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M2_TIMEOUT_ERROR );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M2_RW_STATUS                        , 9   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M2_RW_STATUS );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M2_FLCK                             , 10  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M2_FLCK );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M2_OEAR_LOCK                        , 11  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M2_OEAR_LOCK );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M3_TIMEOUT_ERROR                    , 12  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M3_TIMEOUT_ERROR );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M3_RW_STATUS                        , 13  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M3_RW_STATUS );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M3_FLCK                             , 14  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M3_FLCK );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M3_OEAR_LOCK                        , 15  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M3_OEAR_LOCK );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M4_TIMEOUT_ERROR                    , 16  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M4_TIMEOUT_ERROR );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M4_RW_STATUS                        , 17  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M4_RW_STATUS );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M4_FLCK                             , 18  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M4_FLCK );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M4_OEAR_LOCK                        , 19  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M4_OEAR_LOCK );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M5_TIMEOUT_ERROR                    , 20  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M5_TIMEOUT_ERROR );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M5_RW_STATUS                        , 21  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M5_RW_STATUS );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M5_FLCK                             , 22  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M5_FLCK );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M5_OEAR_LOCK                        , 23  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M5_OEAR_LOCK );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M6_TIMEOUT_ERROR                    , 24  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M6_TIMEOUT_ERROR );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M6_RW_STATUS                        , 25  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M6_RW_STATUS );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M6_FLCK                             , 26  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M6_FLCK );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M6_OEAR_LOCK                        , 27  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M6_OEAR_LOCK );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M7_TIMEOUT_ERROR                    , 28  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M7_TIMEOUT_ERROR );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M7_RW_STATUS                        , 29  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M7_RW_STATUS );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M7_FLCK                             , 30  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M7_FLCK );
+REG64_FLD( PU_OCB_PIB_OESR_OCI_M7_OEAR_LOCK                        , 31  , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCI_M7_OEAR_LOCK );
+
+REG64_FLD( PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_DCU                      , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_ERR_INJ_DCU );
+REG64_FLD( PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_ICU                      , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_ERR_INJ_ICU );
+REG64_FLD( PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_CE_UE                    , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_ERR_INJ_CE_UE );
+REG64_FLD( PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_SINGL_CONT               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_ERR_INJ_SINGL_CONT );
+
+REG64_FLD( PU_OCB_PIB_OSTOEAR_OCC_SPCL_TIMEOUT_ADDR                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OCC_SPCL_TIMEOUT_ADDR );
+REG64_FLD( PU_OCB_PIB_OSTOEAR_OCC_SPCL_TIMEOUT_ADDR_LEN            , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OCC_SPCL_TIMEOUT_ADDR_LEN );
+
+REG64_FLD( PU_OCB_PIB_OSTOESR_ICU_TIMEOUT_ERROR                    , 0   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_ICU_TIMEOUT_ERROR );
+REG64_FLD( PU_OCB_PIB_OSTOESR_ICU_RNW                              , 1   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_ICU_RNW    );
+REG64_FLD( PU_OCB_PIB_OSTOESR_RESERVED_2_3                         , 2   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_RESERVED_2_3 );
+REG64_FLD( PU_OCB_PIB_OSTOESR_RESERVED_2_3_LEN                     , 2   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_RESERVED_2_3_LEN );
+REG64_FLD( PU_OCB_PIB_OSTOESR_DCU_TIMEOUT_ERROR                    , 4   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_DCU_TIMEOUT_ERROR );
+REG64_FLD( PU_OCB_PIB_OSTOESR_DCU_RNW                              , 5   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_DCU_RNW    );
+REG64_FLD( PU_OCB_PIB_OSTOESR_RESERVED_6_7                         , 6   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_RESERVED_6_7 );
+REG64_FLD( PU_OCB_PIB_OSTOESR_RESERVED_6_7_LEN                     , 2   , SH_UNT          , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_RESERVED_6_7_LEN );
+
+REG64_FLD( PU_OCB_PIB_OTDCR_TRACE_BUS_EN                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRACE_BUS_EN );
+REG64_FLD( PU_OCB_PIB_OTDCR_TRACE_MUX_SEL                          , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRACE_MUX_SEL );
+REG64_FLD( PU_OCB_PIB_OTDCR_OCC_TRACE_MUX_SEL                      , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_TRACE_MUX_SEL );
+REG64_FLD( PU_OCB_PIB_OTDCR_OCC_TRACE_MUX_SEL_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_TRACE_MUX_SEL_LEN );
+REG64_FLD( PU_OCB_PIB_OTDCR_OCI_TRACE_MUX_SEL                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_TRACE_MUX_SEL );
+REG64_FLD( PU_OCB_PIB_OTDCR_OCI_TRACE_MUX_SEL_LEN                  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCI_TRACE_MUX_SEL_LEN );
+
+REG64_FLD( PEC_OPCG_ALIGN_INOP                                     , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INOP       );
+REG64_FLD( PEC_OPCG_ALIGN_INOP_LEN                                 , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INOP_LEN   );
+REG64_FLD( PEC_OPCG_ALIGN_SNOP                                     , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SNOP       );
+REG64_FLD( PEC_OPCG_ALIGN_SNOP_LEN                                 , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_LEN   );
+REG64_FLD( PEC_OPCG_ALIGN_ENOP                                     , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ENOP       );
+REG64_FLD( PEC_OPCG_ALIGN_ENOP_LEN                                 , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_LEN   );
+REG64_FLD( PEC_OPCG_ALIGN_INOP_WAIT                                , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INOP_WAIT  );
+REG64_FLD( PEC_OPCG_ALIGN_INOP_WAIT_LEN                            , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INOP_WAIT_LEN );
+REG64_FLD( PEC_OPCG_ALIGN_SNOP_WAIT                                , 20  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_WAIT  );
+REG64_FLD( PEC_OPCG_ALIGN_SNOP_WAIT_LEN                            , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_WAIT_LEN );
+REG64_FLD( PEC_OPCG_ALIGN_ENOP_WAIT                                , 32  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_WAIT  );
+REG64_FLD( PEC_OPCG_ALIGN_ENOP_WAIT_LEN                            , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_WAIT_LEN );
+REG64_FLD( PEC_OPCG_ALIGN_INOP_FORCE_SG                            , 40  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INOP_FORCE_SG );
+REG64_FLD( PEC_OPCG_ALIGN_SNOP_FORCE_SG                            , 41  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_FORCE_SG );
+REG64_FLD( PEC_OPCG_ALIGN_ENOP_FORCE_SG                            , 42  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_FORCE_SG );
+REG64_FLD( PEC_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD                       , 43  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_NO_WAIT_ON_CLK_CMD );
+REG64_FLD( PEC_OPCG_ALIGN_SOURCE_SELECT                            , 44  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SOURCE_SELECT );
+REG64_FLD( PEC_OPCG_ALIGN_SOURCE_SELECT_LEN                        , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SOURCE_SELECT_LEN );
+REG64_FLD( PEC_OPCG_ALIGN_UNUSED46                                 , 46  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED46   );
+REG64_FLD( PEC_OPCG_ALIGN_SCAN_RATIO                               , 47  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_RATIO );
+REG64_FLD( PEC_OPCG_ALIGN_SCAN_RATIO_LEN                           , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_RATIO_LEN );
+REG64_FLD( PEC_OPCG_ALIGN_WAIT_CYCLES                              , 52  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( PEC_OPCG_ALIGN_WAIT_CYCLES_LEN                          , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( PEC_OPCG_CAPT1_COUNT                                    , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COUNT      );
+REG64_FLD( PEC_OPCG_CAPT1_COUNT_LEN                                , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COUNT_LEN  );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_01                                   , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_01     );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_01_LEN                               , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_01_LEN );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_02                                   , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_02     );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_02_LEN                               , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_02_LEN );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_03                                   , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_03     );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_03_LEN                               , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_03_LEN );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_04                                   , 19  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_04     );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_04_LEN                               , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_04_LEN );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_05                                   , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_05     );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_05_LEN                               , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_05_LEN );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_06                                   , 29  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_06     );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_06_LEN                               , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_06_LEN );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_07                                   , 34  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07     );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_07_LEN                               , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07_LEN );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_08                                   , 39  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08     );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_08_LEN                               , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08_LEN );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_09                                   , 44  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09     );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_09_LEN                               , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09_LEN );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_10                                   , 49  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10     );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_10_LEN                               , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10_LEN );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_11                                   , 54  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11     );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_11_LEN                               , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11_LEN );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_12                                   , 59  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12     );
+REG64_FLD( PEC_OPCG_CAPT1_SEQ_12_LEN                               , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12_LEN );
+
+REG64_FLD( PEC_OPCG_CAPT2_UNUSED                                   , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PEC_OPCG_CAPT2_UNUSED_LEN                               , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_13_01EVEN                            , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_13_01EVEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_13_01EVEN_LEN                        , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_13_01EVEN_LEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_14_01ODD                             , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_14_01ODD );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_14_01ODD_LEN                         , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_14_01ODD_LEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_15_02EVEN                            , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_15_02EVEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_15_02EVEN_LEN                        , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_15_02EVEN_LEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_16_02ODD                             , 19  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_16_02ODD );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_16_02ODD_LEN                         , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_16_02ODD_LEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_17_03EVEN                            , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_17_03EVEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_17_03EVEN_LEN                        , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_17_03EVEN_LEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_18_03ODD                             , 29  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_18_03ODD );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_18_03ODD_LEN                         , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_18_03ODD_LEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_19_04EVEN                            , 34  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_19_04EVEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_19_04EVEN_LEN                        , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_19_04EVEN_LEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_20_04ODD                             , 39  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_20_04ODD );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_20_04ODD_LEN                         , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_20_04ODD_LEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_21_05EVEN                            , 44  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_21_05EVEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_21_05EVEN_LEN                        , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_21_05EVEN_LEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_22_05ODD                             , 49  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_22_05ODD );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_22_05ODD_LEN                         , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_22_05ODD_LEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_23_06EVEN                            , 54  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_23_06EVEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_23_06EVEN_LEN                        , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_23_06EVEN_LEN );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_24_06ODD                             , 59  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_24_06ODD );
+REG64_FLD( PEC_OPCG_CAPT2_SEQ_24_06ODD_LEN                         , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_24_06ODD_LEN );
+
+REG64_FLD( PEC_OPCG_CAPT3_UNUSED                                   , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PEC_OPCG_CAPT3_UNUSED_LEN                               , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_07EVEN                               , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07EVEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_07EVEN_LEN                           , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07EVEN_LEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_07ODD                                , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07ODD  );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_07ODD_LEN                            , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07ODD_LEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_08EVEN                               , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08EVEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_08EVEN_LEN                           , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08EVEN_LEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_08ODD                                , 19  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08ODD  );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_08ODD_LEN                            , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08ODD_LEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_09EVEN                               , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09EVEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_09EVEN_LEN                           , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09EVEN_LEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_09ODD                                , 29  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09ODD  );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_09ODD_LEN                            , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09ODD_LEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_10EVEN                               , 34  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10EVEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_10EVEN_LEN                           , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10EVEN_LEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_10ODD                                , 39  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10ODD  );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_10ODD_LEN                            , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10ODD_LEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_11EVEN                               , 44  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11EVEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_11EVEN_LEN                           , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11EVEN_LEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_11ODD                                , 49  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11ODD  );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_11ODD_LEN                            , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11ODD_LEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_12EVEN                               , 54  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12EVEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_12EVEN_LEN                           , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12EVEN_LEN );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_12ODD                                , 59  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12ODD  );
+REG64_FLD( PEC_OPCG_CAPT3_SEQ_12ODD_LEN                            , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12ODD_LEN );
+
+REG64_FLD( PEC_OPCG_REG0_RUNN_MODE                                 , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_MODE  );
+REG64_FLD( PEC_OPCG_REG0_GO                                        , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GO         );
+REG64_FLD( PEC_OPCG_REG0_RUN_SCAN0                                 , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RUN_SCAN0  );
+REG64_FLD( PEC_OPCG_REG0_SCAN0_MODE                                , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SCAN0_MODE );
+REG64_FLD( PEC_OPCG_REG0_IN_SLAVE_MODE                             , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN_SLAVE_MODE );
+REG64_FLD( PEC_OPCG_REG0_IN_MASTER_MODE                            , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN_MASTER_MODE );
+REG64_FLD( PEC_OPCG_REG0_KEEP_MS_MODE                              , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_KEEP_MS_MODE );
+REG64_FLD( PEC_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL                 , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_ON_UNIT0_SYNC_LVL );
+REG64_FLD( PEC_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL                 , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_ON_UNIT1_SYNC_LVL );
+REG64_FLD( PEC_OPCG_REG0_RUN_CHIPLET_SCAN0                         , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RUN_CHIPLET_SCAN0 );
+REG64_FLD( PEC_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL                  , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL );
+REG64_FLD( PEC_OPCG_REG0_RUN_ON_UPDATE_DR                          , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RUN_ON_UPDATE_DR );
+REG64_FLD( PEC_OPCG_REG0_RUN_ON_CAPTURE_DR                         , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RUN_ON_CAPTURE_DR );
+REG64_FLD( PEC_OPCG_REG0_STOP_RUNN_ON_XSTOP                        , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STOP_RUNN_ON_XSTOP );
+REG64_FLD( PEC_OPCG_REG0_STARTS_BIST                               , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STARTS_BIST );
+REG64_FLD( PEC_OPCG_REG0_UNUSED1520                                , 15  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1520 );
+REG64_FLD( PEC_OPCG_REG0_UNUSED1520_LEN                            , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1520_LEN );
+REG64_FLD( PEC_OPCG_REG0_LOOP_COUNT                                , 21  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_LOOP_COUNT );
+REG64_FLD( PEC_OPCG_REG0_LOOP_COUNT_LEN                            , 43  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_LOOP_COUNT_LEN );
+
+REG64_FLD( PEC_OPCG_REG1_SCAN_COUNT                                , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_COUNT );
+REG64_FLD( PEC_OPCG_REG1_SCAN_COUNT_LEN                            , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_COUNT_LEN );
+REG64_FLD( PEC_OPCG_REG1_MISR_A_VAL                                , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MISR_A_VAL );
+REG64_FLD( PEC_OPCG_REG1_MISR_A_VAL_LEN                            , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MISR_A_VAL_LEN );
+REG64_FLD( PEC_OPCG_REG1_MISR_B_VAL                                , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MISR_B_VAL );
+REG64_FLD( PEC_OPCG_REG1_MISR_B_VAL_LEN                            , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MISR_B_VAL_LEN );
+REG64_FLD( PEC_OPCG_REG1_MISR_INIT_WAIT                            , 36  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MISR_INIT_WAIT );
+REG64_FLD( PEC_OPCG_REG1_MISR_INIT_WAIT_LEN                        , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MISR_INIT_WAIT_LEN );
+REG64_FLD( PEC_OPCG_REG1_SUPPRESS_EVEN_CLK                         , 48  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SUPPRESS_EVEN_CLK );
+REG64_FLD( PEC_OPCG_REG1_SCAN_CLK_USE_EVEN                         , 49  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_CLK_USE_EVEN );
+REG64_FLD( PEC_OPCG_REG1_UNUSED2                                   , 50  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2    );
+REG64_FLD( PEC_OPCG_REG1_UNUSED2_LEN                               , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2_LEN );
+REG64_FLD( PEC_OPCG_REG1_RTIM_THOLD_FORCE                          , 52  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RTIM_THOLD_FORCE );
+REG64_FLD( PEC_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL               , 53  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_ARY_CLK_DURING_FILL );
+REG64_FLD( PEC_OPCG_REG1_SG_HIGH_DURING_FILL                       , 54  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SG_HIGH_DURING_FILL );
+REG64_FLD( PEC_OPCG_REG1_LBIST_SKITTER_CTL                         , 55  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_LBIST_SKITTER_CTL );
+REG64_FLD( PEC_OPCG_REG1_LBIST_SKITTER_CTL_LEN                     , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_LBIST_SKITTER_CTL_LEN );
+REG64_FLD( PEC_OPCG_REG1_MISR_MODE                                 , 57  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MISR_MODE  );
+REG64_FLD( PEC_OPCG_REG1_INFINITE_MODE                             , 58  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INFINITE_MODE );
+REG64_FLD( PEC_OPCG_REG1_NSL_FILL_COUNT                            , 59  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_NSL_FILL_COUNT );
+REG64_FLD( PEC_OPCG_REG1_NSL_FILL_COUNT_LEN                        , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_NSL_FILL_COUNT_LEN );
+
+REG64_FLD( PEC_OPCG_REG2_GO2                                       , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GO2        );
+REG64_FLD( PEC_OPCG_REG2_PRPG_WEIGHTING                            , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_WEIGHTING );
+REG64_FLD( PEC_OPCG_REG2_PRPG_WEIGHTING_LEN                        , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_WEIGHTING_LEN );
+REG64_FLD( PEC_OPCG_REG2_PRPG_VALUE                                , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_VALUE );
+REG64_FLD( PEC_OPCG_REG2_PRPG_VALUE_LEN                            , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_VALUE_LEN );
+REG64_FLD( PEC_OPCG_REG2_PRPG_A_VAL                                , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_A_VAL );
+REG64_FLD( PEC_OPCG_REG2_PRPG_A_VAL_LEN                            , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_A_VAL_LEN );
+REG64_FLD( PEC_OPCG_REG2_PRPG_B_VAL                                , 28  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_B_VAL );
+REG64_FLD( PEC_OPCG_REG2_PRPG_B_VAL_LEN                            , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_B_VAL_LEN );
+REG64_FLD( PEC_OPCG_REG2_PRPG_MODE                                 , 40  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_MODE  );
+REG64_FLD( PEC_OPCG_REG2_UNUSED41_63                               , 41  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED41_63 );
+REG64_FLD( PEC_OPCG_REG2_UNUSED41_63_LEN                           , 23  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED41_63_LEN );
+
+REG64_FLD( PU_NPU_CTL_OPTICAL_IO_CONFIG_NDLMUX_BRK0TO2             , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NDLMUX_BRK0TO2 );
+REG64_FLD( PU_NPU_CTL_OPTICAL_IO_CONFIG_NDLMUX_BRK0TO2_LEN         , 3   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NDLMUX_BRK0TO2_LEN );
+
+REG64_FLD( PU_PBABAR0_CMD_SCOPE                                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_SCOPE  );
+REG64_FLD( PU_PBABAR0_CMD_SCOPE_LEN                                , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_SCOPE_LEN );
+REG64_FLD( PU_PBABAR0_RESERVED_3                                   , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_3 );
+REG64_FLD( PU_PBABAR0_ADDR                                         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR       );
+REG64_FLD( PU_PBABAR0_ADDR_LEN                                     , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_PBABAR0_VTARGET                                      , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VTARGET    );
+REG64_FLD( PU_PBABAR0_VTARGET_LEN                                  , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VTARGET_LEN );
+
+REG64_FLD( PU_PBABAR1_CMD_SCOPE                                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_SCOPE  );
+REG64_FLD( PU_PBABAR1_CMD_SCOPE_LEN                                , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_SCOPE_LEN );
+REG64_FLD( PU_PBABAR1_RESERVED_3                                   , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_3 );
+REG64_FLD( PU_PBABAR1_ADDR                                         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR       );
+REG64_FLD( PU_PBABAR1_ADDR_LEN                                     , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_PBABAR1_VTARGET                                      , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VTARGET    );
+REG64_FLD( PU_PBABAR1_VTARGET_LEN                                  , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VTARGET_LEN );
+
+REG64_FLD( PU_PBABAR2_CMD_SCOPE                                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_SCOPE  );
+REG64_FLD( PU_PBABAR2_CMD_SCOPE_LEN                                , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_SCOPE_LEN );
+REG64_FLD( PU_PBABAR2_RESERVED_3                                   , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_3 );
+REG64_FLD( PU_PBABAR2_ADDR                                         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR       );
+REG64_FLD( PU_PBABAR2_ADDR_LEN                                     , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_PBABAR2_VTARGET                                      , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VTARGET    );
+REG64_FLD( PU_PBABAR2_VTARGET_LEN                                  , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VTARGET_LEN );
+
+REG64_FLD( PU_PBABAR3_CMD_SCOPE                                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_SCOPE  );
+REG64_FLD( PU_PBABAR3_CMD_SCOPE_LEN                                , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_SCOPE_LEN );
+REG64_FLD( PU_PBABAR3_RESERVED_3                                   , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_3 );
+REG64_FLD( PU_PBABAR3_ADDR                                         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR       );
+REG64_FLD( PU_PBABAR3_ADDR_LEN                                     , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_PBABAR3_VTARGET                                      , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VTARGET    );
+REG64_FLD( PU_PBABAR3_VTARGET_LEN                                  , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_VTARGET_LEN );
+
+REG64_FLD( PU_PBABARMSK0_MSK                                       , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MSK        );
+REG64_FLD( PU_PBABARMSK0_MSK_LEN                                   , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MSK_LEN    );
+
+REG64_FLD( PU_PBABARMSK1_MSK                                       , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MSK        );
+REG64_FLD( PU_PBABARMSK1_MSK_LEN                                   , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MSK_LEN    );
+
+REG64_FLD( PU_PBABARMSK2_MSK                                       , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MSK        );
+REG64_FLD( PU_PBABARMSK2_MSK_LEN                                   , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MSK_LEN    );
+
+REG64_FLD( PU_PBABARMSK3_MSK                                       , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MSK        );
+REG64_FLD( PU_PBABARMSK3_MSK_LEN                                   , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MSK_LEN    );
+
+REG64_FLD( PU_PBACFG_PBREQ_SLVFW_MAX_PRIORITY                      , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBREQ_SLVFW_MAX_PRIORITY );
+REG64_FLD( PU_PBACFG_PBREQ_EXIT_ON_HANG                            , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBREQ_EXIT_ON_HANG );
+REG64_FLD( PU_PBACFG_PBREQ_BCE_MAX_PRIORITY                        , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBREQ_BCE_MAX_PRIORITY );
+REG64_FLD( PU_PBACFG_PBREQ_EXIT_ON_HANG_PBAX                       , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBREQ_EXIT_ON_HANG_PBAX );
+REG64_FLD( PU_PBACFG_PBREQ_DATA_HANG_DIV                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBREQ_DATA_HANG_DIV );
+REG64_FLD( PU_PBACFG_PBREQ_DATA_HANG_DIV_LEN                       , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBREQ_DATA_HANG_DIV_LEN );
+REG64_FLD( PU_PBACFG_PBREQ_OPER_HANG_DIV                           , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBREQ_OPER_HANG_DIV );
+REG64_FLD( PU_PBACFG_PBREQ_OPER_HANG_DIV_LEN                       , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBREQ_OPER_HANG_DIV_LEN );
+REG64_FLD( PU_PBACFG_PBREQ_DROP_PRIORITY_MASK                      , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBREQ_DROP_PRIORITY_MASK );
+REG64_FLD( PU_PBACFG_PBREQ_DROP_PRIORITY_MASK_LEN                  , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBREQ_DROP_PRIORITY_MASK_LEN );
+REG64_FLD( PU_PBACFG_PBREQ_EXIT_HANG_DIV                           , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBREQ_EXIT_HANG_DIV );
+REG64_FLD( PU_PBACFG_PBREQ_EXIT_HANG_DIV_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBREQ_EXIT_HANG_DIV_LEN );
+REG64_FLD( PU_PBACFG_CHSW_HANG_ON_ADRERROR                         , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_HANG_ON_ADRERROR );
+REG64_FLD( PU_PBACFG_CHSW_DIS_OCIABUSPAR_CHECK                     , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_DIS_OCIABUSPAR_CHECK );
+REG64_FLD( PU_PBACFG_CHSW_DIS_OCIBEPAR_CHECK                       , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_DIS_OCIBEPAR_CHECK );
+REG64_FLD( PU_PBACFG_CHSW_HANG_ON_DERROR                           , 27  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_HANG_ON_DERROR );
+REG64_FLD( PU_PBACFG_RESERVED_28                                   , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_28 );
+REG64_FLD( PU_PBACFG_CHSW_DIS_WRITE_MATCH_REARB                    , 29  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_DIS_WRITE_MATCH_REARB );
+REG64_FLD( PU_PBACFG_CHSW_DIS_OCIDATAPAR_GEN                       , 30  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_DIS_OCIDATAPAR_GEN );
+REG64_FLD( PU_PBACFG_CHSW_DIS_OCIDATAPAR_CHECK                     , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_DIS_OCIDATAPAR_CHECK );
+REG64_FLD( PU_PBACFG_CHSW_DIS_OPER_HANG                            , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_DIS_OPER_HANG );
+REG64_FLD( PU_PBACFG_CHSW_DIS_DATA_HANG                            , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_DIS_DATA_HANG );
+REG64_FLD( PU_PBACFG_CHSW_DIS_ECC_CHECK                            , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_DIS_ECC_CHECK );
+REG64_FLD( PU_PBACFG_CHSW_DIS_RETRY_BACKOFF                        , 35  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_DIS_RETRY_BACKOFF );
+REG64_FLD( PU_PBACFG_CHSW_EXIT_ON_INVALID_CRESP                    , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_EXIT_ON_INVALID_CRESP );
+REG64_FLD( PU_PBACFG_RESERVED_37                                   , 37  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_37 );
+REG64_FLD( PU_PBACFG_CHSW_DIS_GROUP_SCOPE                          , 38  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_DIS_GROUP_SCOPE );
+REG64_FLD( PU_PBACFG_CHSW_DIS_RTAG_PARITY_CHK                      , 39  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_DIS_RTAG_PARITY_CHK );
+REG64_FLD( PU_PBACFG_CHSW_DIS_PB_PARITY_CHK                        , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_DIS_PB_PARITY_CHK );
+REG64_FLD( PU_PBACFG_CHSW_SKIP_GROUP_SCOPE                         , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_SKIP_GROUP_SCOPE );
+REG64_FLD( PU_PBACFG_CHSW_USE_PR_DMA_INJ                           , 42  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_USE_PR_DMA_INJ );
+REG64_FLD( PU_PBACFG_CHSW_USE_CL_DMA_INJ                           , 43  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHSW_USE_CL_DMA_INJ );
+REG64_FLD( PU_PBACFG_RESERVED_44_47                                , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_44_47 );
+REG64_FLD( PU_PBACFG_RESERVED_44_47_LEN                            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_44_47_LEN );
+
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_RDDATATO_FW                       , 0   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CERR_PB_RDDATATO_FW );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_RDDATATO_FW_LEN                   , 6   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CERR_PB_RDDATATO_FW_LEN );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_RDADRERR_FW                       , 6   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CERR_PB_RDADRERR_FW );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_RDADRERR_FW_LEN                   , 6   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CERR_PB_RDADRERR_FW_LEN );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_WRADRERR_FW                       , 12  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CERR_PB_WRADRERR_FW );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_WRADRERR_FW_LEN                   , 4   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CERR_PB_WRADRERR_FW_LEN );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_RD                     , 16  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CERR_PB_ACKDEAD_FW_RD );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_RD_LEN                 , 6   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CERR_PB_ACKDEAD_FW_RD_LEN );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_WR                     , 22  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CERR_PB_ACKDEAD_FW_WR );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_WR_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CERR_PB_ACKDEAD_FW_WR_LEN );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_UNEXPCRESP                        , 24  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CERR_PB_UNEXPCRESP );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_UNEXPCRESP_LEN                    , 11  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CERR_PB_UNEXPCRESP_LEN );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_UNEXPDATA                         , 35  , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CERR_PB_UNEXPDATA );
+REG64_FLD( PU_PBAERRRPT0_CERR_PB_UNEXPDATA_LEN                     , 6   , SH_UNT          , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_CERR_PB_UNEXPDATA_LEN );
+
+REG64_FLD( PU_PBAERRRPT1_CERR_PB_BADCRESP                          , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_PB_BADCRESP );
+REG64_FLD( PU_PBAERRRPT1_CERR_PB_BADCRESP_LEN                      , 12  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_PB_BADCRESP_LEN );
+REG64_FLD( PU_PBAERRRPT1_CERR_PB_OPERTO                            , 12  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_PB_OPERTO );
+REG64_FLD( PU_PBAERRRPT1_CERR_PB_OPERTO_LEN                        , 12  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_PB_OPERTO_LEN );
+REG64_FLD( PU_PBAERRRPT1_RESERVED_24_29                            , 24  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_24_29 );
+REG64_FLD( PU_PBAERRRPT1_RESERVED_24_29_LEN                        , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_24_29_LEN );
+REG64_FLD( PU_PBAERRRPT1_CERR_BCDE_SETUP_ERR                       , 30  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_BCDE_SETUP_ERR );
+REG64_FLD( PU_PBAERRRPT1_CERR_BCDE_SETUP_ERR_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_BCDE_SETUP_ERR_LEN );
+REG64_FLD( PU_PBAERRRPT1_CERR_BCUE_SETUP_ERR                       , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_BCUE_SETUP_ERR );
+REG64_FLD( PU_PBAERRRPT1_CERR_BCUE_SETUP_ERR_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_BCUE_SETUP_ERR_LEN );
+REG64_FLD( PU_PBAERRRPT1_CERR_BCUE_OCI_DATAERR                     , 34  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_BCUE_OCI_DATAERR );
+REG64_FLD( PU_PBAERRRPT1_CERR_BCUE_OCI_DATAERR_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_BCUE_OCI_DATAERR_LEN );
+
+REG64_FLD( PU_PBAERRRPT2_CERR_SLV_INTERNAL_ERR                     , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_SLV_INTERNAL_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_SLV_INTERNAL_ERR_LEN                 , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_SLV_INTERNAL_ERR_LEN );
+REG64_FLD( PU_PBAERRRPT2_CERR_BCDE_INTERNAL_ERR                    , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_BCDE_INTERNAL_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_BCDE_INTERNAL_ERR_LEN                , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_BCDE_INTERNAL_ERR_LEN );
+REG64_FLD( PU_PBAERRRPT2_CERR_BCUE_INTERNAL_ERR                    , 12  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_BCUE_INTERNAL_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_BCUE_INTERNAL_ERR_LEN                , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_BCUE_INTERNAL_ERR_LEN );
+REG64_FLD( PU_PBAERRRPT2_CERR_BAR_PARITY_ERR                       , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_BAR_PARITY_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_SCOMTB_ERR                           , 17  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_SCOMTB_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_SPARE                                , 18  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_SPARE );
+REG64_FLD( PU_PBAERRRPT2_CERR_SPARE_LEN                            , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_SPARE_LEN );
+REG64_FLD( PU_PBAERRRPT2_CERR_PBDOUT_PARITY_ERR                    , 20  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_PBDOUT_PARITY_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_PB_PARITY_ERR                        , 21  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_PB_PARITY_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_PB_PARITY_ERR_LEN                    , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_PB_PARITY_ERR_LEN );
+REG64_FLD( PU_PBAERRRPT2_CERR_AXFLOW_ERR                           , 24  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_AXFLOW_ERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_AXFLOW_ERR_LEN                       , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_AXFLOW_ERR_LEN );
+REG64_FLD( PU_PBAERRRPT2_CERR_AXPUSH_WRERR                         , 29  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_AXPUSH_WRERR );
+REG64_FLD( PU_PBAERRRPT2_CERR_AXPUSH_WRERR_LEN                     , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CERR_AXPUSH_WRERR_LEN );
+
+REG64_FLD( PU_PBAFIR_OCI_APAR_ERR                                  , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_APAR_ERR );
+REG64_FLD( PU_PBAFIR_PB_RDADRERR_FW                                , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_RDADRERR_FW );
+REG64_FLD( PU_PBAFIR_PB_RDDATATO_FW                                , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_RDDATATO_FW );
+REG64_FLD( PU_PBAFIR_PB_SUE_FW                                     , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_SUE_FW  );
+REG64_FLD( PU_PBAFIR_PB_UE_FW                                      , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_UE_FW   );
+REG64_FLD( PU_PBAFIR_PB_CE_FW                                      , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_CE_FW   );
+REG64_FLD( PU_PBAFIR_OCI_SLAVE_INIT                                , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_SLAVE_INIT );
+REG64_FLD( PU_PBAFIR_OCI_WRPAR_ERR                                 , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_WRPAR_ERR );
+REG64_FLD( PU_PBAFIR_RESERVED_8                                    , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_8 );
+REG64_FLD( PU_PBAFIR_PB_UNEXPCRESP                                 , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_UNEXPCRESP );
+REG64_FLD( PU_PBAFIR_PB_UNEXPDATA                                  , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_UNEXPDATA );
+REG64_FLD( PU_PBAFIR_PB_PARITY_ERR                                 , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_PARITY_ERR );
+REG64_FLD( PU_PBAFIR_PB_WRADRERR_FW                                , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_WRADRERR_FW );
+REG64_FLD( PU_PBAFIR_PB_BADCRESP                                   , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_BADCRESP );
+REG64_FLD( PU_PBAFIR_PB_ACKDEAD_FW_RD                              , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_ACKDEAD_FW_RD );
+REG64_FLD( PU_PBAFIR_PB_OPERTO                                     , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_OPERTO  );
+REG64_FLD( PU_PBAFIR_BCUE_SETUP_ERR                                , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCUE_SETUP_ERR );
+REG64_FLD( PU_PBAFIR_BCUE_PB_ACK_DEAD                              , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCUE_PB_ACK_DEAD );
+REG64_FLD( PU_PBAFIR_BCUE_PB_ADRERR                                , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCUE_PB_ADRERR );
+REG64_FLD( PU_PBAFIR_BCUE_OCI_DATERR                               , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCUE_OCI_DATERR );
+REG64_FLD( PU_PBAFIR_BCDE_SETUP_ERR                                , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_SETUP_ERR );
+REG64_FLD( PU_PBAFIR_BCDE_PB_ACK_DEAD                              , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_PB_ACK_DEAD );
+REG64_FLD( PU_PBAFIR_BCDE_PB_ADRERR                                , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_PB_ADRERR );
+REG64_FLD( PU_PBAFIR_BCDE_RDDATATO_ERR                             , 23  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_RDDATATO_ERR );
+REG64_FLD( PU_PBAFIR_BCDE_SUE_ERR                                  , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_SUE_ERR );
+REG64_FLD( PU_PBAFIR_BCDE_UE_ERR                                   , 25  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_UE_ERR );
+REG64_FLD( PU_PBAFIR_BCDE_CE                                       , 26  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_CE    );
+REG64_FLD( PU_PBAFIR_BCDE_OCI_DATERR                               , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_OCI_DATERR );
+REG64_FLD( PU_PBAFIR_INTERNAL_ERR                                  , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_ERR );
+REG64_FLD( PU_PBAFIR_ILLEGAL_CACHE_OP                              , 29  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ILLEGAL_CACHE_OP );
+REG64_FLD( PU_PBAFIR_OCI_BAD_REG_ADDR                              , 30  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_BAD_REG_ADDR );
+REG64_FLD( PU_PBAFIR_AXPUSH_WRERR                                  , 31  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXPUSH_WRERR );
+REG64_FLD( PU_PBAFIR_AXRCV_DLO_ERR                                 , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXRCV_DLO_ERR );
+REG64_FLD( PU_PBAFIR_AXRCV_DLO_TO                                  , 33  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXRCV_DLO_TO );
+REG64_FLD( PU_PBAFIR_AXRCV_RSVDATA_TO                              , 34  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXRCV_RSVDATA_TO );
+REG64_FLD( PU_PBAFIR_AXFLOW_ERR                                    , 35  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXFLOW_ERR );
+REG64_FLD( PU_PBAFIR_AXSND_DHI_RTYTO                               , 36  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXSND_DHI_RTYTO );
+REG64_FLD( PU_PBAFIR_AXSND_DLO_RTYTO                               , 37  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXSND_DLO_RTYTO );
+REG64_FLD( PU_PBAFIR_AXSND_RSVTO                                   , 38  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXSND_RSVTO );
+REG64_FLD( PU_PBAFIR_AXSND_RSVERR                                  , 39  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXSND_RSVERR );
+REG64_FLD( PU_PBAFIR_PB_ACKDEAD_FW_WR                              , 40  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_ACKDEAD_FW_WR );
+REG64_FLD( PU_PBAFIR_RESERVED_41                                   , 41  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_41 );
+REG64_FLD( PU_PBAFIR_RESERVED_42                                   , 42  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_42 );
+REG64_FLD( PU_PBAFIR_RESERVED_43                                   , 43  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_43 );
+REG64_FLD( PU_PBAFIR_FIR_PARITY_ERR2                               , 44  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_PARITY_ERR2 );
+REG64_FLD( PU_PBAFIR_FIR_PARITY_ERR                                , 45  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_PARITY_ERR );
+
+REG64_FLD( PU_PBAFIRACT0_FIR_ACTION0                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION0 );
+REG64_FLD( PU_PBAFIRACT0_FIR_ACTION0_LEN                           , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION0_LEN );
+
+REG64_FLD( PU_PBAFIRACT1_FIR_ACTION1                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION1 );
+REG64_FLD( PU_PBAFIRACT1_FIR_ACTION1_LEN                           , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION1_LEN );
+
+REG64_FLD( PU_PBAFIRMASK_OCI_APAR_ERR_MASK                         , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_APAR_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_RDADRERR_FW_MASK                       , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_RDADRERR_FW_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_RDDATATO_FW_MASK                       , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_RDDATATO_FW_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_SUE_FW_MASK                            , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_SUE_FW_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_UE_FW_MASK                             , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_UE_FW_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_CE_FW_MASK                             , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_CE_FW_MASK );
+REG64_FLD( PU_PBAFIRMASK_OCI_SLAVE_INIT_MASK                       , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_SLAVE_INIT_MASK );
+REG64_FLD( PU_PBAFIRMASK_OCI_WRPAR_ERR_MASK                        , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_WRPAR_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_RESERVED_8                                , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_8 );
+REG64_FLD( PU_PBAFIRMASK_PB_UNEXPCRESP_MASK                        , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_UNEXPCRESP_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_UNEXPDATA_MASK                         , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_UNEXPDATA_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_PARITY_ERR_MASK                        , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_PARITY_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_WRADRERR_FW_MASK                       , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_WRADRERR_FW_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_BADCRESP_MASK                          , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_BADCRESP_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_ACKDEAD_FW_RD_MASK                     , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_ACKDEAD_FW_RD_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_OPERTO_MASK                            , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_OPERTO_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCUE_SETUP_ERR_MASK                       , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCUE_SETUP_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCUE_PB_ACK_DEAD_MASK                     , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCUE_PB_ACK_DEAD_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCUE_PB_ADRERR_MASK                       , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCUE_PB_ADRERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCUE_OCI_DATERR_MASK                      , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCUE_OCI_DATERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_SETUP_ERR_MASK                       , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_SETUP_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_PB_ACK_DEAD_MASK                     , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_PB_ACK_DEAD_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_PB_ADRERR_MASK                       , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_PB_ADRERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_RDDATATO_ERR_MASK                    , 23  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_RDDATATO_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_SUE_ERR_MASK                         , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_SUE_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_UE_ERR_MASK                          , 25  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_UE_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_CE_MASK                              , 26  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_CE_MASK );
+REG64_FLD( PU_PBAFIRMASK_BCDE_OCI_DATERR_MASK                      , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCDE_OCI_DATERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_INTERNAL_ERR_MASK                         , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_ILLEGAL_CACHE_OP_MASK                     , 29  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ILLEGAL_CACHE_OP_MASK );
+REG64_FLD( PU_PBAFIRMASK_OCI_BAD_REG_ADDR_MASK                     , 30  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCI_BAD_REG_ADDR_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXPUSH_WRERR_MASK                         , 31  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXPUSH_WRERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXRCV_DLO_ERR_MASK                        , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXRCV_DLO_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXRCV_DLO_TO_MASK                         , 33  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXRCV_DLO_TO_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXRCV_RSVDATA_TO_MASK                     , 34  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXRCV_RSVDATA_TO_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXFLOW_ERR_MASK                           , 35  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXFLOW_ERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXSND_DHI_RTYTO_MASK                      , 36  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXSND_DHI_RTYTO_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXSND_DLO_RTYTO_MASK                      , 37  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXSND_DLO_RTYTO_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXSND_RSVTO_MASK                          , 38  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXSND_RSVTO_MASK );
+REG64_FLD( PU_PBAFIRMASK_AXSND_RSVERR_MASK                         , 39  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_AXSND_RSVERR_MASK );
+REG64_FLD( PU_PBAFIRMASK_PB_ACKDEAD_FW_WR_MASK                     , 40  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_ACKDEAD_FW_WR_MASK );
+REG64_FLD( PU_PBAFIRMASK_RESERVED_41_43                            , 41  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_41_43 );
+REG64_FLD( PU_PBAFIRMASK_RESERVED_41_43_LEN                        , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_41_43_LEN );
+REG64_FLD( PU_PBAFIRMASK_FIR_PARITY_ERR2_MASK                      , 44  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_PARITY_ERR2_MASK );
+REG64_FLD( PU_PBAFIRMASK_FIR_PARITY_ERR_MASK                       , 45  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_PARITY_ERR_MASK );
+
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE               , 16  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_OSMB_DATASTART_MODE );
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE_LEN           , 3   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_OSMB_DATASTART_MODE_LEN );
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_TX_RESP_HWM                       , 20  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_TX_RESP_HWM );
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_TX_RESP_HWM_LEN                   , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_TX_RESP_HWM_LEN );
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_TX_RESP_LWM                       , 24  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_TX_RESP_LWM );
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_TX_RESP_LWM_LEN                   , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_TX_RESP_LWM_LEN );
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_EARLYEMPTY_MODE              , 28  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_OSMB_EARLYEMPTY_MODE );
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_EARLYEMPTY_MODE_LEN          , 2   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_OSMB_EARLYEMPTY_MODE_LEN );
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_PCIE_CLK_TRACE_EN                 , 30  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PCIE_CLK_TRACE_EN );
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_SELECT_ETU_TRACE                  , 31  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_SELECT_ETU_TRACE );
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_PCI_CLK_TRACE_SEL                 , 32  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PCI_CLK_TRACE_SEL );
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_PCI_CLK_TRACE_SEL_LEN             , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PCI_CLK_TRACE_SEL_LEN );
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT                 , 36  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ISMB_ERROR_INJECT );
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT_LEN             , 3   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ISMB_ERROR_INJECT_LEN );
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT                  , 40  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_OSMB_HOL_BLK_CNT );
+REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT_LEN              , 3   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_OSMB_HOL_BLK_CNT_LEN );
+
+REG64_FLD( PU_PBAMODE_RESERVED_0_3                                 , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_0_3 );
+REG64_FLD( PU_PBAMODE_RESERVED_0_3_LEN                             , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_0_3_LEN );
+REG64_FLD( PU_PBAMODE_DIS_REARB                                    , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DIS_REARB  );
+REG64_FLD( PU_PBAMODE_DIS_MSTID_MATCH_PREF_INV                     , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DIS_MSTID_MATCH_PREF_INV );
+REG64_FLD( PU_PBAMODE_DIS_SLAVE_RDPIPE                             , 6   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DIS_SLAVE_RDPIPE );
+REG64_FLD( PU_PBAMODE_DIS_SLAVE_WRPIPE                             , 7   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DIS_SLAVE_WRPIPE );
+REG64_FLD( PU_PBAMODE_EN_MARKER_ACK                                , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EN_MARKER_ACK );
+REG64_FLD( PU_PBAMODE_RESERVED_9                                   , 9   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_9 );
+REG64_FLD( PU_PBAMODE_EN_SECOND_WRBUF                              , 10  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EN_SECOND_WRBUF );
+REG64_FLD( PU_PBAMODE_DIS_REREQUEST_TO                             , 11  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DIS_REREQUEST_TO );
+REG64_FLD( PU_PBAMODE_INJECT_TYPE                                  , 12  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_INJECT_TYPE );
+REG64_FLD( PU_PBAMODE_INJECT_TYPE_LEN                              , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_INJECT_TYPE_LEN );
+REG64_FLD( PU_PBAMODE_INJECT_MODE                                  , 14  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_INJECT_MODE );
+REG64_FLD( PU_PBAMODE_INJECT_MODE_LEN                              , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_INJECT_MODE_LEN );
+REG64_FLD( PU_PBAMODE_PBA_REGION                                   , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PBA_REGION );
+REG64_FLD( PU_PBAMODE_PBA_REGION_LEN                               , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PBA_REGION_LEN );
+REG64_FLD( PU_PBAMODE_OCI_MARKER_SPACE                             , 18  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_OCI_MARKER_SPACE );
+REG64_FLD( PU_PBAMODE_OCI_MARKER_SPACE_LEN                         , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_OCI_MARKER_SPACE_LEN );
+REG64_FLD( PU_PBAMODE_BCDE_OCITRANS                                , 21  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BCDE_OCITRANS );
+REG64_FLD( PU_PBAMODE_BCDE_OCITRANS_LEN                            , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BCDE_OCITRANS_LEN );
+REG64_FLD( PU_PBAMODE_BCUE_OCITRANS                                , 23  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BCUE_OCITRANS );
+REG64_FLD( PU_PBAMODE_BCUE_OCITRANS_LEN                            , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BCUE_OCITRANS_LEN );
+REG64_FLD( PU_PBAMODE_DIS_MASTER_RD_PIPE                           , 25  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DIS_MASTER_RD_PIPE );
+REG64_FLD( PU_PBAMODE_DIS_MASTER_WR_PIPE                           , 26  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DIS_MASTER_WR_PIPE );
+REG64_FLD( PU_PBAMODE_EN_SLV_FAIRNESS                              , 27  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EN_SLV_FAIRNESS );
+REG64_FLD( PU_PBAMODE_EN_EVENT_COUNT                               , 28  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EN_EVENT_COUNT );
+REG64_FLD( PU_PBAMODE_PB_NOCI_EVENT_SEL                            , 29  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PB_NOCI_EVENT_SEL );
+REG64_FLD( PU_PBAMODE_SLV_EVENT_MUX                                , 30  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SLV_EVENT_MUX );
+REG64_FLD( PU_PBAMODE_SLV_EVENT_MUX_LEN                            , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SLV_EVENT_MUX_LEN );
+REG64_FLD( PU_PBAMODE_ENABLE_DEBUG_BUS                             , 32  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ENABLE_DEBUG_BUS );
+REG64_FLD( PU_PBAMODE_DEBUG_PB_NOT_OCI                             , 33  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DEBUG_PB_NOT_OCI );
+REG64_FLD( PU_PBAMODE_DEBUG_OCI_MODE                               , 34  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DEBUG_OCI_MODE );
+REG64_FLD( PU_PBAMODE_DEBUG_OCI_MODE_LEN                           , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DEBUG_OCI_MODE_LEN );
+REG64_FLD( PU_PBAMODE_RESERVED_39                                  , 39  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_39 );
+REG64_FLD( PU_PBAMODE_OCISLV_FAIRNESS_MASK                         , 40  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_OCISLV_FAIRNESS_MASK );
+REG64_FLD( PU_PBAMODE_OCISLV_FAIRNESS_MASK_LEN                     , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_OCISLV_FAIRNESS_MASK_LEN );
+REG64_FLD( PU_PBAMODE_OCISLV_REREQ_HANG_DIV                        , 45  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_OCISLV_REREQ_HANG_DIV );
+REG64_FLD( PU_PBAMODE_OCISLV_REREQ_HANG_DIV_LEN                    , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_OCISLV_REREQ_HANG_DIV_LEN );
+REG64_FLD( PU_PBAMODE_DIS_CHGRATE_COUNT                            , 50  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DIS_CHGRATE_COUNT );
+REG64_FLD( PU_PBAMODE_PBREQ_EVENT_MUX                              , 51  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PBREQ_EVENT_MUX );
+REG64_FLD( PU_PBAMODE_PBREQ_EVENT_MUX_LEN                          , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PBREQ_EVENT_MUX_LEN );
+REG64_FLD( PU_PBAMODE_RESERVED_53_63                               , 53  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_53_63 );
+REG64_FLD( PU_PBAMODE_RESERVED_53_63_LEN                           , 11  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_53_63_LEN );
+
+REG64_FLD( PU_PBAOCCACT_OCC_ACTION_SET                             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_ACTION_SET );
+REG64_FLD( PU_PBAOCCACT_OCC_ACTION_SET_LEN                         , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_ACTION_SET_LEN );
+
+REG64_FLD( PU_PBAPBOCR0_EVENT                                      , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EVENT      );
+REG64_FLD( PU_PBAPBOCR0_EVENT_LEN                                  , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EVENT_LEN  );
+REG64_FLD( PU_PBAPBOCR0_ACCUM                                      , 44  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ACCUM      );
+REG64_FLD( PU_PBAPBOCR0_ACCUM_LEN                                  , 20  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ACCUM_LEN  );
+
+REG64_FLD( PU_PBAPBOCR1_EVENT                                      , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EVENT      );
+REG64_FLD( PU_PBAPBOCR1_EVENT_LEN                                  , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EVENT_LEN  );
+REG64_FLD( PU_PBAPBOCR1_ACCUM                                      , 44  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ACCUM      );
+REG64_FLD( PU_PBAPBOCR1_ACCUM_LEN                                  , 20  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ACCUM_LEN  );
+
+REG64_FLD( PU_PBAPBOCR2_EVENT                                      , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EVENT      );
+REG64_FLD( PU_PBAPBOCR2_EVENT_LEN                                  , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EVENT_LEN  );
+REG64_FLD( PU_PBAPBOCR2_ACCUM                                      , 44  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ACCUM      );
+REG64_FLD( PU_PBAPBOCR2_ACCUM_LEN                                  , 20  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ACCUM_LEN  );
+
+REG64_FLD( PU_PBAPBOCR3_EVENT                                      , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EVENT      );
+REG64_FLD( PU_PBAPBOCR3_EVENT_LEN                                  , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EVENT_LEN  );
+REG64_FLD( PU_PBAPBOCR3_ACCUM                                      , 44  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ACCUM      );
+REG64_FLD( PU_PBAPBOCR3_ACCUM_LEN                                  , 20  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ACCUM_LEN  );
+
+REG64_FLD( PU_PBAPBOCR4_EVENT                                      , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EVENT      );
+REG64_FLD( PU_PBAPBOCR4_EVENT_LEN                                  , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EVENT_LEN  );
+REG64_FLD( PU_PBAPBOCR4_ACCUM                                      , 44  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ACCUM      );
+REG64_FLD( PU_PBAPBOCR4_ACCUM_LEN                                  , 20  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ACCUM_LEN  );
+
+REG64_FLD( PU_PBAPBOCR5_EVENT                                      , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EVENT      );
+REG64_FLD( PU_PBAPBOCR5_EVENT_LEN                                  , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EVENT_LEN  );
+REG64_FLD( PU_PBAPBOCR5_ACCUM                                      , 44  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ACCUM      );
+REG64_FLD( PU_PBAPBOCR5_ACCUM_LEN                                  , 20  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ACCUM_LEN  );
+
+REG64_FLD( PU_PBARBUFVAL0_RD_SLVNUM                                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_SLVNUM  );
+REG64_FLD( PU_PBARBUFVAL0_RD_SLVNUM_LEN                            , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_SLVNUM_LEN );
+REG64_FLD( PU_PBARBUFVAL0_CUR_RD_ADDR                              , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CUR_RD_ADDR );
+REG64_FLD( PU_PBARBUFVAL0_CUR_RD_ADDR_LEN                          , 23  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CUR_RD_ADDR_LEN );
+REG64_FLD( PU_PBARBUFVAL0_PREFETCH                                 , 28  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PREFETCH   );
+REG64_FLD( PU_PBARBUFVAL0_ABORT                                    , 31  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ABORT      );
+REG64_FLD( PU_PBARBUFVAL0_BUFFER_STATUS                            , 33  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_BUFFER_STATUS );
+REG64_FLD( PU_PBARBUFVAL0_BUFFER_STATUS_LEN                        , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBARBUFVAL0_MASTERID                                 , 41  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MASTERID   );
+REG64_FLD( PU_PBARBUFVAL0_MASTERID_LEN                             , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MASTERID_LEN );
+
+REG64_FLD( PU_PBARBUFVAL1_RD_SLVNUM                                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_SLVNUM  );
+REG64_FLD( PU_PBARBUFVAL1_RD_SLVNUM_LEN                            , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_SLVNUM_LEN );
+REG64_FLD( PU_PBARBUFVAL1_CUR_RD_ADDR                              , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CUR_RD_ADDR );
+REG64_FLD( PU_PBARBUFVAL1_CUR_RD_ADDR_LEN                          , 23  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CUR_RD_ADDR_LEN );
+REG64_FLD( PU_PBARBUFVAL1_PREFETCH                                 , 28  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PREFETCH   );
+REG64_FLD( PU_PBARBUFVAL1_ABORT                                    , 31  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ABORT      );
+REG64_FLD( PU_PBARBUFVAL1_BUFFER_STATUS                            , 33  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_BUFFER_STATUS );
+REG64_FLD( PU_PBARBUFVAL1_BUFFER_STATUS_LEN                        , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBARBUFVAL1_MASTERID                                 , 41  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MASTERID   );
+REG64_FLD( PU_PBARBUFVAL1_MASTERID_LEN                             , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MASTERID_LEN );
+
+REG64_FLD( PU_PBARBUFVAL2_RD_SLVNUM                                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_SLVNUM  );
+REG64_FLD( PU_PBARBUFVAL2_RD_SLVNUM_LEN                            , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_SLVNUM_LEN );
+REG64_FLD( PU_PBARBUFVAL2_CUR_RD_ADDR                              , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CUR_RD_ADDR );
+REG64_FLD( PU_PBARBUFVAL2_CUR_RD_ADDR_LEN                          , 23  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CUR_RD_ADDR_LEN );
+REG64_FLD( PU_PBARBUFVAL2_PREFETCH                                 , 28  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PREFETCH   );
+REG64_FLD( PU_PBARBUFVAL2_ABORT                                    , 31  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ABORT      );
+REG64_FLD( PU_PBARBUFVAL2_BUFFER_STATUS                            , 33  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_BUFFER_STATUS );
+REG64_FLD( PU_PBARBUFVAL2_BUFFER_STATUS_LEN                        , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBARBUFVAL2_MASTERID                                 , 41  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MASTERID   );
+REG64_FLD( PU_PBARBUFVAL2_MASTERID_LEN                             , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MASTERID_LEN );
+
+REG64_FLD( PU_PBARBUFVAL3_RD_SLVNUM                                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_SLVNUM  );
+REG64_FLD( PU_PBARBUFVAL3_RD_SLVNUM_LEN                            , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_SLVNUM_LEN );
+REG64_FLD( PU_PBARBUFVAL3_CUR_RD_ADDR                              , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CUR_RD_ADDR );
+REG64_FLD( PU_PBARBUFVAL3_CUR_RD_ADDR_LEN                          , 23  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CUR_RD_ADDR_LEN );
+REG64_FLD( PU_PBARBUFVAL3_PREFETCH                                 , 28  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PREFETCH   );
+REG64_FLD( PU_PBARBUFVAL3_ABORT                                    , 31  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ABORT      );
+REG64_FLD( PU_PBARBUFVAL3_BUFFER_STATUS                            , 33  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_BUFFER_STATUS );
+REG64_FLD( PU_PBARBUFVAL3_BUFFER_STATUS_LEN                        , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBARBUFVAL3_MASTERID                                 , 41  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MASTERID   );
+REG64_FLD( PU_PBARBUFVAL3_MASTERID_LEN                             , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MASTERID_LEN );
+
+REG64_FLD( PU_PBARBUFVAL4_RD_SLVNUM                                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_SLVNUM  );
+REG64_FLD( PU_PBARBUFVAL4_RD_SLVNUM_LEN                            , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_SLVNUM_LEN );
+REG64_FLD( PU_PBARBUFVAL4_CUR_RD_ADDR                              , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CUR_RD_ADDR );
+REG64_FLD( PU_PBARBUFVAL4_CUR_RD_ADDR_LEN                          , 23  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CUR_RD_ADDR_LEN );
+REG64_FLD( PU_PBARBUFVAL4_PREFETCH                                 , 28  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PREFETCH   );
+REG64_FLD( PU_PBARBUFVAL4_ABORT                                    , 31  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ABORT      );
+REG64_FLD( PU_PBARBUFVAL4_BUFFER_STATUS                            , 33  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_BUFFER_STATUS );
+REG64_FLD( PU_PBARBUFVAL4_BUFFER_STATUS_LEN                        , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBARBUFVAL4_MASTERID                                 , 41  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MASTERID   );
+REG64_FLD( PU_PBARBUFVAL4_MASTERID_LEN                             , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MASTERID_LEN );
+
+REG64_FLD( PU_PBARBUFVAL5_RD_SLVNUM                                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_SLVNUM  );
+REG64_FLD( PU_PBARBUFVAL5_RD_SLVNUM_LEN                            , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_SLVNUM_LEN );
+REG64_FLD( PU_PBARBUFVAL5_CUR_RD_ADDR                              , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CUR_RD_ADDR );
+REG64_FLD( PU_PBARBUFVAL5_CUR_RD_ADDR_LEN                          , 23  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CUR_RD_ADDR_LEN );
+REG64_FLD( PU_PBARBUFVAL5_PREFETCH                                 , 28  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PREFETCH   );
+REG64_FLD( PU_PBARBUFVAL5_ABORT                                    , 31  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ABORT      );
+REG64_FLD( PU_PBARBUFVAL5_BUFFER_STATUS                            , 33  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_BUFFER_STATUS );
+REG64_FLD( PU_PBARBUFVAL5_BUFFER_STATUS_LEN                        , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBARBUFVAL5_MASTERID                                 , 41  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MASTERID   );
+REG64_FLD( PU_PBARBUFVAL5_MASTERID_LEN                             , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MASTERID_LEN );
+
+REG64_FLD( PU_PBASLVCTL0_ENABLE                                    , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_PBASLVCTL0_MID_MATCH_VALUE                           , 1   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_MATCH_VALUE );
+REG64_FLD( PU_PBASLVCTL0_MID_MATCH_VALUE_LEN                       , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_MATCH_VALUE_LEN );
+REG64_FLD( PU_PBASLVCTL0_RESERVED_4                                , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_4 );
+REG64_FLD( PU_PBASLVCTL0_MID_CARE_MASK                             , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_CARE_MASK );
+REG64_FLD( PU_PBASLVCTL0_MID_CARE_MASK_LEN                         , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_CARE_MASK_LEN );
+REG64_FLD( PU_PBASLVCTL0_WRITE_TTYPE                               , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TTYPE );
+REG64_FLD( PU_PBASLVCTL0_WRITE_TTYPE_LEN                           , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TTYPE_LEN );
+REG64_FLD( PU_PBASLVCTL0_RESERVED_11_14                            , 11  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_11_14 );
+REG64_FLD( PU_PBASLVCTL0_RESERVED_11_14_LEN                        , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_11_14_LEN );
+REG64_FLD( PU_PBASLVCTL0_READ_TTYPE                                , 15  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_READ_TTYPE );
+REG64_FLD( PU_PBASLVCTL0_READ_PREFETCH_CTL                         , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_READ_PREFETCH_CTL );
+REG64_FLD( PU_PBASLVCTL0_READ_PREFETCH_CTL_LEN                     , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_READ_PREFETCH_CTL_LEN );
+REG64_FLD( PU_PBASLVCTL0_BUF_INVALIDATE_CTL                        , 18  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_INVALIDATE_CTL );
+REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_W                               , 19  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_W );
+REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_A                               , 20  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_A );
+REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_B                               , 21  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_B );
+REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_C                               , 22  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_C );
+REG64_FLD( PU_PBASLVCTL0_RESERVED_23                               , 23  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_23 );
+REG64_FLD( PU_PBASLVCTL0_DIS_WRITE_GATHER                          , 24  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DIS_WRITE_GATHER );
+REG64_FLD( PU_PBASLVCTL0_WR_GATHER_TIMEOUT                         , 25  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WR_GATHER_TIMEOUT );
+REG64_FLD( PU_PBASLVCTL0_WR_GATHER_TIMEOUT_LEN                     , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WR_GATHER_TIMEOUT_LEN );
+REG64_FLD( PU_PBASLVCTL0_WRITE_TSIZE                               , 28  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TSIZE );
+REG64_FLD( PU_PBASLVCTL0_WRITE_TSIZE_LEN                           , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TSIZE_LEN );
+REG64_FLD( PU_PBASLVCTL0_EXTADDR                                   , 36  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EXTADDR    );
+REG64_FLD( PU_PBASLVCTL0_EXTADDR_LEN                               , 14  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EXTADDR_LEN );
+REG64_FLD( PU_PBASLVCTL0_RESERVED_50                               , 50  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_50 );
+
+REG64_FLD( PU_PBASLVCTL1_ENABLE                                    , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_PBASLVCTL1_MID_MATCH_VALUE                           , 1   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_MATCH_VALUE );
+REG64_FLD( PU_PBASLVCTL1_MID_MATCH_VALUE_LEN                       , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_MATCH_VALUE_LEN );
+REG64_FLD( PU_PBASLVCTL1_RESERVED_4                                , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_4 );
+REG64_FLD( PU_PBASLVCTL1_MID_CARE_MASK                             , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_CARE_MASK );
+REG64_FLD( PU_PBASLVCTL1_MID_CARE_MASK_LEN                         , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_CARE_MASK_LEN );
+REG64_FLD( PU_PBASLVCTL1_WRITE_TTYPE                               , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TTYPE );
+REG64_FLD( PU_PBASLVCTL1_WRITE_TTYPE_LEN                           , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TTYPE_LEN );
+REG64_FLD( PU_PBASLVCTL1_RESERVED_11_14                            , 11  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_11_14 );
+REG64_FLD( PU_PBASLVCTL1_RESERVED_11_14_LEN                        , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_11_14_LEN );
+REG64_FLD( PU_PBASLVCTL1_READ_TTYPE                                , 15  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_READ_TTYPE );
+REG64_FLD( PU_PBASLVCTL1_READ_PREFETCH_CTL                         , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_READ_PREFETCH_CTL );
+REG64_FLD( PU_PBASLVCTL1_READ_PREFETCH_CTL_LEN                     , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_READ_PREFETCH_CTL_LEN );
+REG64_FLD( PU_PBASLVCTL1_BUF_INVALIDATE_CTL                        , 18  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_INVALIDATE_CTL );
+REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_W                               , 19  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_W );
+REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_A                               , 20  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_A );
+REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_B                               , 21  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_B );
+REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_C                               , 22  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_C );
+REG64_FLD( PU_PBASLVCTL1_RESERVED_23                               , 23  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_23 );
+REG64_FLD( PU_PBASLVCTL1_DIS_WRITE_GATHER                          , 24  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DIS_WRITE_GATHER );
+REG64_FLD( PU_PBASLVCTL1_WR_GATHER_TIMEOUT                         , 25  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WR_GATHER_TIMEOUT );
+REG64_FLD( PU_PBASLVCTL1_WR_GATHER_TIMEOUT_LEN                     , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WR_GATHER_TIMEOUT_LEN );
+REG64_FLD( PU_PBASLVCTL1_WRITE_TSIZE                               , 28  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TSIZE );
+REG64_FLD( PU_PBASLVCTL1_WRITE_TSIZE_LEN                           , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TSIZE_LEN );
+REG64_FLD( PU_PBASLVCTL1_EXTADDR                                   , 36  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EXTADDR    );
+REG64_FLD( PU_PBASLVCTL1_EXTADDR_LEN                               , 14  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EXTADDR_LEN );
+REG64_FLD( PU_PBASLVCTL1_RESERVED_50                               , 50  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_50 );
+
+REG64_FLD( PU_PBASLVCTL2_ENABLE                                    , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_PBASLVCTL2_MID_MATCH_VALUE                           , 1   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_MATCH_VALUE );
+REG64_FLD( PU_PBASLVCTL2_MID_MATCH_VALUE_LEN                       , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_MATCH_VALUE_LEN );
+REG64_FLD( PU_PBASLVCTL2_RESERVED_4                                , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_4 );
+REG64_FLD( PU_PBASLVCTL2_MID_CARE_MASK                             , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_CARE_MASK );
+REG64_FLD( PU_PBASLVCTL2_MID_CARE_MASK_LEN                         , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_CARE_MASK_LEN );
+REG64_FLD( PU_PBASLVCTL2_WRITE_TTYPE                               , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TTYPE );
+REG64_FLD( PU_PBASLVCTL2_WRITE_TTYPE_LEN                           , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TTYPE_LEN );
+REG64_FLD( PU_PBASLVCTL2_RESERVED_11_14                            , 11  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_11_14 );
+REG64_FLD( PU_PBASLVCTL2_RESERVED_11_14_LEN                        , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_11_14_LEN );
+REG64_FLD( PU_PBASLVCTL2_READ_TTYPE                                , 15  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_READ_TTYPE );
+REG64_FLD( PU_PBASLVCTL2_READ_PREFETCH_CTL                         , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_READ_PREFETCH_CTL );
+REG64_FLD( PU_PBASLVCTL2_READ_PREFETCH_CTL_LEN                     , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_READ_PREFETCH_CTL_LEN );
+REG64_FLD( PU_PBASLVCTL2_BUF_INVALIDATE_CTL                        , 18  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_INVALIDATE_CTL );
+REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_W                               , 19  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_W );
+REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_A                               , 20  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_A );
+REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_B                               , 21  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_B );
+REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_C                               , 22  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_C );
+REG64_FLD( PU_PBASLVCTL2_RESERVED_23                               , 23  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_23 );
+REG64_FLD( PU_PBASLVCTL2_DIS_WRITE_GATHER                          , 24  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DIS_WRITE_GATHER );
+REG64_FLD( PU_PBASLVCTL2_WR_GATHER_TIMEOUT                         , 25  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WR_GATHER_TIMEOUT );
+REG64_FLD( PU_PBASLVCTL2_WR_GATHER_TIMEOUT_LEN                     , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WR_GATHER_TIMEOUT_LEN );
+REG64_FLD( PU_PBASLVCTL2_WRITE_TSIZE                               , 28  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TSIZE );
+REG64_FLD( PU_PBASLVCTL2_WRITE_TSIZE_LEN                           , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TSIZE_LEN );
+REG64_FLD( PU_PBASLVCTL2_EXTADDR                                   , 36  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EXTADDR    );
+REG64_FLD( PU_PBASLVCTL2_EXTADDR_LEN                               , 14  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EXTADDR_LEN );
+REG64_FLD( PU_PBASLVCTL2_RESERVED_50                               , 50  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_50 );
+
+REG64_FLD( PU_PBASLVCTL3_ENABLE                                    , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_PBASLVCTL3_MID_MATCH_VALUE                           , 1   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_MATCH_VALUE );
+REG64_FLD( PU_PBASLVCTL3_MID_MATCH_VALUE_LEN                       , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_MATCH_VALUE_LEN );
+REG64_FLD( PU_PBASLVCTL3_RESERVED_4                                , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_4 );
+REG64_FLD( PU_PBASLVCTL3_MID_CARE_MASK                             , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_CARE_MASK );
+REG64_FLD( PU_PBASLVCTL3_MID_CARE_MASK_LEN                         , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_MID_CARE_MASK_LEN );
+REG64_FLD( PU_PBASLVCTL3_WRITE_TTYPE                               , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TTYPE );
+REG64_FLD( PU_PBASLVCTL3_WRITE_TTYPE_LEN                           , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TTYPE_LEN );
+REG64_FLD( PU_PBASLVCTL3_RESERVED_11_14                            , 11  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_11_14 );
+REG64_FLD( PU_PBASLVCTL3_RESERVED_11_14_LEN                        , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_11_14_LEN );
+REG64_FLD( PU_PBASLVCTL3_READ_TTYPE                                , 15  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_READ_TTYPE );
+REG64_FLD( PU_PBASLVCTL3_READ_PREFETCH_CTL                         , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_READ_PREFETCH_CTL );
+REG64_FLD( PU_PBASLVCTL3_READ_PREFETCH_CTL_LEN                     , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_READ_PREFETCH_CTL_LEN );
+REG64_FLD( PU_PBASLVCTL3_BUF_INVALIDATE_CTL                        , 18  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_INVALIDATE_CTL );
+REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_W                               , 19  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_W );
+REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_A                               , 20  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_A );
+REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_B                               , 21  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_B );
+REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_C                               , 22  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUF_ALLOC_C );
+REG64_FLD( PU_PBASLVCTL3_RESERVED_23                               , 23  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_23 );
+REG64_FLD( PU_PBASLVCTL3_DIS_WRITE_GATHER                          , 24  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_DIS_WRITE_GATHER );
+REG64_FLD( PU_PBASLVCTL3_WR_GATHER_TIMEOUT                         , 25  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WR_GATHER_TIMEOUT );
+REG64_FLD( PU_PBASLVCTL3_WR_GATHER_TIMEOUT_LEN                     , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WR_GATHER_TIMEOUT_LEN );
+REG64_FLD( PU_PBASLVCTL3_WRITE_TSIZE                               , 28  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TSIZE );
+REG64_FLD( PU_PBASLVCTL3_WRITE_TSIZE_LEN                           , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_WRITE_TSIZE_LEN );
+REG64_FLD( PU_PBASLVCTL3_EXTADDR                                   , 36  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EXTADDR    );
+REG64_FLD( PU_PBASLVCTL3_EXTADDR_LEN                               , 14  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_EXTADDR_LEN );
+REG64_FLD( PU_PBASLVCTL3_RESERVED_50                               , 50  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_50 );
+
+REG64_FLD( PU_PBASLVRST_SET                                        , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SET        );
+REG64_FLD( PU_PBASLVRST_SET_LEN                                    , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SET_LEN    );
+REG64_FLD( PU_PBASLVRST_IN_PROG                                    , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_IN_PROG    );
+REG64_FLD( PU_PBASLVRST_IN_PROG_LEN                                , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_IN_PROG_LEN );
+REG64_FLD( PU_PBASLVRST_BUSY_STATUS                                , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUSY_STATUS );
+REG64_FLD( PU_PBASLVRST_BUSY_STATUS_LEN                            , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_BUSY_STATUS_LEN );
+REG64_FLD( PU_PBASLVRST_SCOPE_ATTN_BAR                             , 12  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SCOPE_ATTN_BAR );
+REG64_FLD( PU_PBASLVRST_SCOPE_ATTN_BAR_LEN                         , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SCOPE_ATTN_BAR_LEN );
+
+REG64_FLD( PU_PBAWBUFVAL0_WR_SLVNUM                                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_SLVNUM  );
+REG64_FLD( PU_PBAWBUFVAL0_WR_SLVNUM_LEN                            , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_SLVNUM_LEN );
+REG64_FLD( PU_PBAWBUFVAL0_START_WR_ADDR                            , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_START_WR_ADDR );
+REG64_FLD( PU_PBAWBUFVAL0_START_WR_ADDR_LEN                        , 30  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_START_WR_ADDR_LEN );
+REG64_FLD( PU_PBAWBUFVAL0_WR_BUFFER_STATUS                         , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_BUFFER_STATUS );
+REG64_FLD( PU_PBAWBUFVAL0_WR_BUFFER_STATUS_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBAWBUFVAL0_WR_BYTE_COUNT                            , 41  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_BYTE_COUNT );
+REG64_FLD( PU_PBAWBUFVAL0_WR_BYTE_COUNT_LEN                        , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_BYTE_COUNT_LEN );
+
+REG64_FLD( PU_PBAWBUFVAL1_WR_SLVNUM                                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_SLVNUM  );
+REG64_FLD( PU_PBAWBUFVAL1_WR_SLVNUM_LEN                            , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_SLVNUM_LEN );
+REG64_FLD( PU_PBAWBUFVAL1_START_WR_ADDR                            , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_START_WR_ADDR );
+REG64_FLD( PU_PBAWBUFVAL1_START_WR_ADDR_LEN                        , 30  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_START_WR_ADDR_LEN );
+REG64_FLD( PU_PBAWBUFVAL1_WR_BUFFER_STATUS                         , 35  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_BUFFER_STATUS );
+REG64_FLD( PU_PBAWBUFVAL1_WR_BUFFER_STATUS_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_BUFFER_STATUS_LEN );
+REG64_FLD( PU_PBAWBUFVAL1_WR_BYTE_COUNT                            , 41  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_BYTE_COUNT );
+REG64_FLD( PU_PBAWBUFVAL1_WR_BYTE_COUNT_LEN                        , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_BYTE_COUNT_LEN );
+
+REG64_FLD( PU_PBAXCFG_PBAX_EN                                      , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PBAX_EN    );
+REG64_FLD( PU_PBAXCFG_RESERVATION_EN                               , 1   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVATION_EN );
+REG64_FLD( PU_PBAXCFG_SND_RESET                                    , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_RESET  );
+REG64_FLD( PU_PBAXCFG_RCV_RESET                                    , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RCV_RESET  );
+REG64_FLD( PU_PBAXCFG_RCV_GROUPID                                  , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RCV_GROUPID );
+REG64_FLD( PU_PBAXCFG_RCV_GROUPID_LEN                              , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RCV_GROUPID_LEN );
+REG64_FLD( PU_PBAXCFG_RCV_CHIPID                                   , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RCV_CHIPID );
+REG64_FLD( PU_PBAXCFG_RCV_CHIPID_LEN                               , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RCV_CHIPID_LEN );
+REG64_FLD( PU_PBAXCFG_RESERVED_11                                  , 11  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_11 );
+REG64_FLD( PU_PBAXCFG_RCV_BRDCST_GROUP                             , 12  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RCV_BRDCST_GROUP );
+REG64_FLD( PU_PBAXCFG_RCV_BRDCST_GROUP_LEN                         , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RCV_BRDCST_GROUP_LEN );
+REG64_FLD( PU_PBAXCFG_RCV_DATATO_DIV                               , 20  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RCV_DATATO_DIV );
+REG64_FLD( PU_PBAXCFG_RCV_DATATO_DIV_LEN                           , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RCV_DATATO_DIV_LEN );
+REG64_FLD( PU_PBAXCFG_RESERVED_25_26                               , 25  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_25_26 );
+REG64_FLD( PU_PBAXCFG_RESERVED_25_26_LEN                           , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_25_26_LEN );
+REG64_FLD( PU_PBAXCFG_SND_RETRY_COUNT_OVERCOM                      , 27  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_RETRY_COUNT_OVERCOM );
+REG64_FLD( PU_PBAXCFG_SND_RETRY_THRESH                             , 28  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_RETRY_THRESH );
+REG64_FLD( PU_PBAXCFG_SND_RETRY_THRESH_LEN                         , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_RETRY_THRESH_LEN );
+REG64_FLD( PU_PBAXCFG_SND_RSVTO_DIV                                , 36  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_RSVTO_DIV );
+REG64_FLD( PU_PBAXCFG_SND_RSVTO_DIV_LEN                            , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_RSVTO_DIV_LEN );
+
+REG64_FLD( PU_PBAXRCVSTAT_RCV_IN_PROGRESS                          , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RCV_IN_PROGRESS );
+REG64_FLD( PU_PBAXRCVSTAT_RCV_ERROR                                , 1   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RCV_ERROR  );
+REG64_FLD( PU_PBAXRCVSTAT_RCV_WRITE_IN_PROGRESS                    , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RCV_WRITE_IN_PROGRESS );
+REG64_FLD( PU_PBAXRCVSTAT_RCV_RESERVATION_SET                      , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RCV_RESERVATION_SET );
+REG64_FLD( PU_PBAXRCVSTAT_RCV_CAPTURE                              , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RCV_CAPTURE );
+REG64_FLD( PU_PBAXRCVSTAT_RCV_CAPTURE_LEN                          , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RCV_CAPTURE_LEN );
+
+REG64_FLD( PU_PBAXSHBR0_PUSH_START                                 , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_START );
+REG64_FLD( PU_PBAXSHBR0_PUSH_START_LEN                             , 29  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_PBAXSHBR1_PUSH_START                                 , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_START );
+REG64_FLD( PU_PBAXSHBR1_PUSH_START_LEN                             , 29  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_START_LEN );
+
+REG64_FLD( PU_PBAXSHCS0_PUSH_FULL                                  , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_PBAXSHCS0_PUSH_EMPTY                                 , 1   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_PBAXSHCS0_RESERVED_2_3                               , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_2_3 );
+REG64_FLD( PU_PBAXSHCS0_RESERVED_2_3_LEN                           , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_2_3_LEN );
+REG64_FLD( PU_PBAXSHCS0_PUSH_INTR_ACTION_0_1                       , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_PBAXSHCS0_PUSH_INTR_ACTION_0_1_LEN                   , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_PBAXSHCS0_PUSH_LENGTH                                , 6   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_PBAXSHCS0_PUSH_LENGTH_LEN                            , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_PBAXSHCS0_PUSH_WRITE_PTR                             , 13  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_PBAXSHCS0_PUSH_WRITE_PTR_LEN                         , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_PBAXSHCS0_PUSH_READ_PTR                              , 21  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_PBAXSHCS0_PUSH_READ_PTR_LEN                          , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_PBAXSHCS0_PUSH_ENABLE                                , 31  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_PBAXSHCS1_PUSH_FULL                                  , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_FULL  );
+REG64_FLD( PU_PBAXSHCS1_PUSH_EMPTY                                 , 1   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_EMPTY );
+REG64_FLD( PU_PBAXSHCS1_RESERVED_2_3                               , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_2_3 );
+REG64_FLD( PU_PBAXSHCS1_RESERVED_2_3_LEN                           , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_2_3_LEN );
+REG64_FLD( PU_PBAXSHCS1_PUSH_INTR_ACTION_0_1                       , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_INTR_ACTION_0_1 );
+REG64_FLD( PU_PBAXSHCS1_PUSH_INTR_ACTION_0_1_LEN                   , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_INTR_ACTION_0_1_LEN );
+REG64_FLD( PU_PBAXSHCS1_PUSH_LENGTH                                , 6   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_LENGTH );
+REG64_FLD( PU_PBAXSHCS1_PUSH_LENGTH_LEN                            , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_LENGTH_LEN );
+REG64_FLD( PU_PBAXSHCS1_PUSH_WRITE_PTR                             , 13  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_WRITE_PTR );
+REG64_FLD( PU_PBAXSHCS1_PUSH_WRITE_PTR_LEN                         , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_WRITE_PTR_LEN );
+REG64_FLD( PU_PBAXSHCS1_PUSH_READ_PTR                              , 21  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_READ_PTR );
+REG64_FLD( PU_PBAXSHCS1_PUSH_READ_PTR_LEN                          , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_READ_PTR_LEN );
+REG64_FLD( PU_PBAXSHCS1_PUSH_ENABLE                                , 31  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_PUSH_ENABLE );
+
+REG64_FLD( PU_PBAXSNDSTAT_SND_IN_PROGRESS                          , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_IN_PROGRESS );
+REG64_FLD( PU_PBAXSNDSTAT_SND_ERROR                                , 1   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_ERROR  );
+REG64_FLD( PU_PBAXSNDSTAT_SND_PHASE_STATUS                         , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_PHASE_STATUS );
+REG64_FLD( PU_PBAXSNDSTAT_SND_PHASE_STATUS_LEN                     , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_PHASE_STATUS_LEN );
+REG64_FLD( PU_PBAXSNDSTAT_SND_CNT_STATUS                           , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_CNT_STATUS );
+REG64_FLD( PU_PBAXSNDSTAT_SND_CNT_STATUS_LEN                       , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_CNT_STATUS_LEN );
+REG64_FLD( PU_PBAXSNDSTAT_SND_RETRY_COUNT                          , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_RETRY_COUNT );
+REG64_FLD( PU_PBAXSNDSTAT_SND_RETRY_COUNT_LEN                      , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_RETRY_COUNT_LEN );
+
+REG64_FLD( PU_PBAXSNDTX_SND_SCOPE                                  , 0   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_SCOPE  );
+REG64_FLD( PU_PBAXSNDTX_SND_SCOPE_LEN                              , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_SCOPE_LEN );
+REG64_FLD( PU_PBAXSNDTX_SND_QID                                    , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_QID    );
+REG64_FLD( PU_PBAXSNDTX_SND_TYPE                                   , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_TYPE   );
+REG64_FLD( PU_PBAXSNDTX_SND_RESERVATION                            , 5   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_RESERVATION );
+REG64_FLD( PU_PBAXSNDTX_RESERVED_6_7                               , 6   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_6_7 );
+REG64_FLD( PU_PBAXSNDTX_RESERVED_6_7_LEN                           , 2   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_6_7_LEN );
+REG64_FLD( PU_PBAXSNDTX_SND_GROUPID                                , 8   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_GROUPID );
+REG64_FLD( PU_PBAXSNDTX_SND_GROUPID_LEN                            , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_GROUPID_LEN );
+REG64_FLD( PU_PBAXSNDTX_SND_CHIPID                                 , 12  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_CHIPID );
+REG64_FLD( PU_PBAXSNDTX_SND_CHIPID_LEN                             , 3   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_CHIPID_LEN );
+REG64_FLD( PU_PBAXSNDTX_RESERVED_15                                , 15  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_RESERVED_15 );
+REG64_FLD( PU_PBAXSNDTX_VG_TARGE                                   , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_VG_TARGE   );
+REG64_FLD( PU_PBAXSNDTX_VG_TARGE_LEN                               , 16  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_VG_TARGE_LEN );
+REG64_FLD( PU_PBAXSNDTX_SND_STOP                                   , 59  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_STOP   );
+REG64_FLD( PU_PBAXSNDTX_SND_CNT                                    , 60  , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_CNT    );
+REG64_FLD( PU_PBAXSNDTX_SND_CNT_LEN                                , 4   , SH_UNT          , SH_ACS_PIB      ,
+           SH_FLD_SND_CNT_LEN );
+
+REG64_FLD( PEC_PBCQEINJ_REG_PE_ECC_INJECT_TYPE                     , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ECC_INJECT_TYPE );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_ECC_INJECT_TYPE_LEN                 , 2   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ECC_INJECT_TYPE_LEN );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_ECC_INJECT_ENABLE                , 2   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_CQ_ECC_INJECT_ENABLE );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_SRAM_ARRAY                       , 3   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_CQ_SRAM_ARRAY );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_SRAM_ARRAY_LEN                   , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_CQ_SRAM_ARRAY_LEN );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_PAR_INJECT_ENABLE                , 7   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_CQ_PAR_INJECT_ENABLE );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_REGISTER_ARRAY                   , 8   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_CQ_REGISTER_ARRAY );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_REGISTER_ARRAY_LEN               , 3   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_CQ_REGISTER_ARRAY_LEN );
+REG64_FLD( PEC_PBCQEINJ_REG_PE_CONSTANT_EINJ                       , 11  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_CONSTANT_EINJ );
+
+REG64_FLD( PEC_PBCQHWCFG_REG_HANG_POLL_SCALE                       , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HANG_POLL_SCALE );
+REG64_FLD( PEC_PBCQHWCFG_REG_HANG_POLL_SCALE_LEN                   , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HANG_POLL_SCALE_LEN );
+REG64_FLD( PEC_PBCQHWCFG_REG_HANG_DATA_SCALE                       , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HANG_DATA_SCALE );
+REG64_FLD( PEC_PBCQHWCFG_REG_HANG_DATA_SCALE_LEN                   , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HANG_DATA_SCALE_LEN );
+REG64_FLD( PEC_PBCQHWCFG_REG_HANG_PE_SCALE                         , 8   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HANG_PE_SCALE );
+REG64_FLD( PEC_PBCQHWCFG_REG_HANG_PE_SCALE_LEN                     , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_HANG_PE_SCALE_LEN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_BLOCK_CQPB_PB_INIT                 , 12  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_BLOCK_CQPB_PB_INIT );
+REG64_FLD( PEC_PBCQHWCFG_REG_DISABLE_RCMD_CLKGATE                  , 13  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_RCMD_CLKGATE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_HANG_SM_ON_ARE                     , 14  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_HANG_SM_ON_ARE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_PCI_CLK_CHECK              , 15  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_PCI_CLK_CHECK );
+REG64_FLD( PEC_PBCQHWCFG_REG_LFSR_ARB_MODE                         , 16  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_LFSR_ARB_MODE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_DMAR_IOPACING               , 17  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ENABLE_DMAR_IOPACING );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_DMAW_IOPACING               , 18  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ENABLE_DMAW_IOPACING );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_ADR_BAR_MODE                       , 19  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ADR_BAR_MODE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_STQ_ALLOCATION                     , 20  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_STQ_ALLOCATION );
+REG64_FLD( PEC_PBCQHWCFG_REG_DISABLE_LPC_CMDS                      , 21  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_LPC_CMDS );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_OOO_MODE                   , 22  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_OOO_MODE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_OSMB_EARLY_START                   , 23  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_OSMB_EARLY_START );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_OSMB_EARLY_START_LEN               , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_OSMB_EARLY_START_LEN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_QFIFO_HOLD_MODE                    , 27  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_QFIFO_HOLD_MODE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_QFIFO_HOLD_MODE_LEN                , 2   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_QFIFO_HOLD_MODE_LEN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_WR_STRICT_ORDER_MODE               , 32  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_WR_STRICT_ORDER_MODE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_CHANNEL_STREAMING_EN               , 33  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_CHANNEL_STREAMING_EN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_WR_CACHE_INJECT_MODE               , 34  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_WR_CACHE_INJECT_MODE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_WR_CACHE_INJECT_MODE_LEN           , 2   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_WR_CACHE_INJECT_MODE_LEN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_NEW_FLOW_CACHE_INJECT       , 36  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ENABLE_NEW_FLOW_CACHE_INJECT );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INJ_ON_RESEND              , 37  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_INJ_ON_RESEND );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW , 38  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_ENH_FLOW                    , 39  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ENABLE_ENH_FLOW );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_WR_VG                      , 41  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_WR_VG );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_WR_SCOPE_GROUP             , 42  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_WR_SCOPE_GROUP );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_VG                   , 43  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_INTWR_VG );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_SCOPE_GROUP          , 44  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_INTWR_SCOPE_GROUP );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_SCOPE_NODE           , 45  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_INTWR_SCOPE_NODE );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_RD_WRITE_ORDERING                  , 48  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_RD_WRITE_ORDERING );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_RD_WRITE_ORDERING_LEN              , 2   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_RD_WRITE_ORDERING_LEN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_NODAL             , 50  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_RD_SCOPE_NODAL );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_GROUP             , 51  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_RD_SCOPE_GROUP );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_RNNN              , 52  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_RD_SCOPE_RNNN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_RD_SKIP_GROUP               , 53  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ENABLE_RD_SKIP_GROUP );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_RD_VG                      , 54  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_RD_VG );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_SCOPE_NODAL            , 55  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_TCE_SCOPE_NODAL );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_SCOPE_GROUP            , 56  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_TCE_SCOPE_GROUP );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_SCOPE_RNNN             , 57  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_TCE_SCOPE_RNNN );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_TCE_SKIP_GROUP              , 58  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ENABLE_TCE_SKIP_GROUP );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_VG                     , 59  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_TCE_VG );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_ARBITRATION            , 60  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_TCE_ARBITRATION );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_CQ_TCE_ARBITRATION         , 61  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_CQ_TCE_ARBITRATION );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_MC_PREFETCH                , 62  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_DISABLE_MC_PREFETCH );
+REG64_FLD( PEC_PBCQHWCFG_REG_PE_IGNORE_SFSTAT                      , 63  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_IGNORE_SFSTAT );
+
+REG64_FLD( PEC_STACK2_PBCQMODE_REG_PE_PEER2PEER_MODDE              , 0   , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PEER2PEER_MODDE );
+REG64_FLD( PEC_STACK2_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE     , 1   , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ENHANCED_PEER2PEER_MODDE );
+
+REG64_FLD( PEC_STACK1_PBCQMODE_REG_PE_PEER2PEER_MODDE              , 0   , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PEER2PEER_MODDE );
+REG64_FLD( PEC_STACK1_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE     , 1   , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ENHANCED_PEER2PEER_MODDE );
+
+REG64_FLD( PHB_PBCQMODE_REG_PE_PEER2PEER_MODDE                     , 0   , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PEER2PEER_MODDE );
+REG64_FLD( PHB_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE            , 1   , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ENHANCED_PEER2PEER_MODDE );
+
+REG64_FLD( PEC_STACK0_PBCQMODE_REG_PE_PEER2PEER_MODDE              , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PEER2PEER_MODDE );
+REG64_FLD( PEC_STACK0_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE     , 1   , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ENHANCED_PEER2PEER_MODDE );
+
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_VALID                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MB_VALID   );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_WR_NOT_RD                     , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MB_WR_NOT_RD );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_BAD_ADDR                      , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MB_BAD_ADDR );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_LINK_DOWN                     , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MB_LINK_DOWN );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_CORRUPT                       , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MB_CORRUPT );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_SENT                          , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MB_SENT    );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_BAD_WRITE                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MB_BAD_WRITE );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_RESET                         , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MB_RESET   );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_ID                               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_LINK_ID                       , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MB_LINK_ID );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_LINK_ID_LEN                   , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MB_LINK_ID_LEN );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_SPARE                         , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MB_SPARE   );
+REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_SPARE_LEN                     , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MB_SPARE_LEN );
+
+REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_VALID                     , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_MB_VALID   );
+REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_WR_NOT_RD                 , 1   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_MB_WR_NOT_RD );
+REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_BAD_ADDR                  , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_MB_BAD_ADDR );
+REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_LINK_DOWN                 , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_MB_LINK_DOWN );
+REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_CORRUPT                   , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_MB_CORRUPT );
+REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_SENT                      , 5   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_MB_SENT    );
+REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_BAD_WRITE                 , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_MB_BAD_WRITE );
+REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_RESET                     , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_MB_RESET   );
+REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_ID                           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_LINK_ID                   , 9   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_MB_LINK_ID );
+REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_LINK_ID_LEN               , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_MB_LINK_ID_LEN );
+REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_SPARE                     , 12  , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_MB_SPARE   );
+REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_SPARE_LEN                 , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_MB_SPARE_LEN );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_EN                     , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_EN     );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_RESET_MODE             , 1   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RESET_MODE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_COUNTER_MODE           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_COUNTER_MODE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_GLOBAL_PMISC_DIS       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_GLOBAL_PMISC_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_GLOBAL_PMISC_MODE      , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_GLOBAL_PMISC_MODE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_EXTERNAL_FREEZE        , 5   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_EXTERNAL_FREEZE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_0_1_OP                 , 6   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_0_1_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_0_1_OP_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_0_1_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_2_3_OP                 , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_2_3_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_2_3_OP_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_2_3_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_4_5_OP                 , 10  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_4_5_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_4_5_OP_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_4_5_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_6_7_OP                 , 12  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_6_7_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_6_7_OP_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_6_7_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_8_9_OP                 , 14  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_8_9_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_8_9_OP_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_8_9_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_10_11_OP               , 16  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_10_11_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_10_11_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_10_11_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_12_13_OP               , 18  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_12_13_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_12_13_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_12_13_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_14_15_OP               , 20  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_14_15_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_14_15_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_14_15_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_16_17_OP               , 22  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_16_17_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_16_17_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_16_17_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_18_19_OP               , 24  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_18_19_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_18_19_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_18_19_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_20_21_OP               , 26  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_20_21_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_20_21_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_20_21_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_22_23_OP               , 28  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_22_23_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_22_23_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_22_23_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_24_25_OP               , 30  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_24_25_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_24_25_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_24_25_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_26_27_OP               , 32  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_26_27_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_26_27_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_26_27_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_28_29_OP               , 34  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_28_29_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_28_29_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_28_29_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_30_31_OP               , 36  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_30_31_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_30_31_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_30_31_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU0           , 38  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU0 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU0_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU0_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU1           , 41  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU1 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU1_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU1_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU2           , 44  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU2 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU2_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU2_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU3           , 47  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU3 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU3_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU3_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MASK                   , 50  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_MASK   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC2_MCS0_MASK          , 51  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_MC2_MCS0_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC2_MCS1_MASK          , 52  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_MC2_MCS1_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC3_MCS0_MASK          , 53  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_MC3_MCS0_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC3_MCS1_MASK          , 54  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_MC3_MCS1_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MCD_MASK               , 56  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_MCD_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE0_MASK               , 57  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PE0_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE1_MASK               , 58  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PE1_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE2_MASK               , 59  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PE2_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_VAS_MASK               , 60  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VAS_MASK );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_EN                     , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_EN     );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_RESET_MODE             , 1   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RESET_MODE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_COUNTER_MODE           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_COUNTER_MODE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_GLOBAL_PMISC_DIS       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_GLOBAL_PMISC_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_GLOBAL_PMISC_MODE      , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_GLOBAL_PMISC_MODE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_EXTERNAL_FREEZE        , 5   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_EXTERNAL_FREEZE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_0_1_OP                 , 6   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_0_1_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_0_1_OP_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_0_1_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_2_3_OP                 , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_2_3_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_2_3_OP_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_2_3_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_4_5_OP                 , 10  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_4_5_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_4_5_OP_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_4_5_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_6_7_OP                 , 12  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_6_7_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_6_7_OP_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_6_7_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_8_9_OP                 , 14  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_8_9_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_8_9_OP_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_8_9_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_10_11_OP               , 16  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_10_11_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_10_11_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_10_11_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_12_13_OP               , 18  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_12_13_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_12_13_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_12_13_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_14_15_OP               , 20  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_14_15_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_14_15_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_14_15_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_16_17_OP               , 22  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_16_17_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_16_17_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_16_17_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_18_19_OP               , 24  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_18_19_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_18_19_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_18_19_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_20_21_OP               , 26  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_20_21_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_20_21_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_20_21_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_22_23_OP               , 28  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_22_23_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_22_23_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_22_23_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_24_25_OP               , 30  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_24_25_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_24_25_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_24_25_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_26_27_OP               , 32  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_26_27_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_26_27_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_26_27_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_28_29_OP               , 34  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_28_29_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_28_29_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_28_29_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_30_31_OP               , 36  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_30_31_OP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_30_31_OP_LEN           , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_30_31_OP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU0           , 38  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU0 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU0_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU0_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU1           , 41  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU1 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU1_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU1_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU2           , 44  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU2 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU2_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU2_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU3           , 47  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU3 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU3_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CASCADE_PMU3_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MASK                   , 50  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_MASK   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC0_MCS0_MASK          , 51  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_MC0_MCS0_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC0_MCS1_MASK          , 52  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_MC0_MCS1_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC1_MCS0_MASK          , 53  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_MC1_MCS0_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC1_MCS1_MASK          , 54  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_MC1_MCS1_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_INT_MASK               , 56  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_INT_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE0_MASK               , 57  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PE0_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE1_MASK               , 58  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PE1_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE2_MASK               , 59  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PE2_MASK );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE            , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTYPE  );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE_LEN        , 7   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTYPE_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE_MASK       , 7   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTYPE_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE_MASK_LEN   , 7   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTYPE_MASK_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE            , 14  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TSIZE  );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE_LEN        , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TSIZE_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE_MASK       , 22  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TSIZE_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE_MASK_LEN   , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TSIZE_MASK_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG             , 30  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTAG   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG_LEN         , 10  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTAG_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG_MASK        , 40  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTAG_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG_MASK_LEN    , 10  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTAG_MASK_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP            , 50  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CRESP  );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_LEN        , 5   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CRESP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_MASK       , 55  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CRESP_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_MASK_LEN   , 5   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CRESP_MASK_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_POLARITY   , 60  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CRESP_POLARITY );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_SCOPE            , 61  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SCOPE  );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_SCOPE_LEN        , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SCOPE_LEN );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE            , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTYPE  );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE_LEN        , 7   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTYPE_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE_MASK       , 7   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTYPE_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE_MASK_LEN   , 7   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTYPE_MASK_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE            , 14  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TSIZE  );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE_LEN        , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TSIZE_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE_MASK       , 22  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TSIZE_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE_MASK_LEN   , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TSIZE_MASK_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG             , 30  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTAG   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG_LEN         , 10  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTAG_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG_MASK        , 40  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTAG_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG_MASK_LEN    , 10  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TTAG_MASK_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP            , 50  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CRESP  );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_LEN        , 5   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CRESP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_MASK       , 55  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CRESP_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_MASK_LEN   , 5   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CRESP_MASK_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_POLARITY   , 60  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CRESP_POLARITY );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_SCOPE            , 61  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SCOPE  );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_SCOPE_LEN        , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SCOPE_LEN );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_SCOPE_MASK , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_COMPA_SCOPE_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_SCOPE_MASK_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_COMPA_SCOPE_MASK_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP      , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_COMPA_PRESP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP_LEN  , 14  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_COMPA_PRESP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP_MASK , 17  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_COMPA_PRESP_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP_MASK_LEN , 14  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_COMPA_PRESP_MASK_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_SCOPE_MASK , 32  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_COMPB_SCOPE_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_SCOPE_MASK_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_COMPB_SCOPE_MASK_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP      , 35  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_COMPB_PRESP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP_LEN  , 14  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_COMPB_PRESP_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP_MASK , 49  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_COMPB_PRESP_MASK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP_MASK_LEN , 14  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_COMPB_PRESP_MASK_LEN );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL0           , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL0 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL0_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL0_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL1           , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL1 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL1_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL1_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL2           , 6   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL2 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL2_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL2_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL3           , 9   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL3 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL3_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL3_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL4           , 12  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL4 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL4_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL4_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL5           , 15  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL5 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL5_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL5_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL6           , 18  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL6 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL6_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL6_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL7           , 21  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL7 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL7_LEN       , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_SEL7_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPME_BITWISE_ENABLE , 24  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_BITWISE_ENABLE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPME_BITWISE_ENABLE_LEN , 16  , SH_UNT_PU_PB_CENT_SM0,
+           SH_ACS_SCOM     , SH_FLD_CFG_CNPME_BITWISE_ENABLE_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPMW_BITWISE_ENABLE , 40  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_BITWISE_ENABLE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPMW_BITWISE_ENABLE_LEN , 16  , SH_UNT_PU_PB_CENT_SM0,
+           SH_ACS_SCOM     , SH_FLD_CFG_CNPMW_BITWISE_ENABLE_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_PORT           , 56  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_PORT );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0          , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0_LEN      , 18  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG_ACTION1          , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG_ACTION1_LEN      , 18  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_PROTOCOL_ERROR      , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PROTOCOL_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_OVERFLOW_ERROR      , 1   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_OVERFLOW_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_HW_PARITY_ERROR     , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_HW_PARITY_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_3             , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_3    );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_COHERENCY_ERROR     , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_COHERENCY_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_CRESP_ADDR_ERROR    , 5   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CRESP_ADDR_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_CRESP_ERROR         , 6   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CRESP_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_HANG_RECOVERY_LIMIT_ERROR , 7   , SH_UNT_PU_PB_CENT_SM0,
+           SH_ACS_SCOM2_OR , SH_FLD_HANG_RECOVERY_LIMIT_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_DATA_ROUTE_ERROR    , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA_ROUTE_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_HANG_RECOVERY_GTE_LEVEL1 , 9   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_HANG_RECOVERY_GTE_LEVEL1 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_FORCE_MP_IPL        , 10  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_FORCE_MP_IPL );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_11            , 11  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_11   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_12            , 12  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_12   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_13            , 13  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_13   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_14            , 14  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_14   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_15            , 15  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_15   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SCOM_ERR            , 16  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SCOM_ERR_DUP        , 17  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_PROTOCOL_ERROR           , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PROTOCOL_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_OVERFLOW_ERROR           , 1   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_OVERFLOW_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_HW_PARITY_ERROR          , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_HW_PARITY_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_3                  , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_3    );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_COHERENCY_ERROR          , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_COHERENCY_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_CRESP_ADDR_ERROR         , 5   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CRESP_ADDR_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_CRESP_ERROR              , 6   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_CRESP_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_HANG_RECOVERY_LIMIT_ERROR , 7   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_HANG_RECOVERY_LIMIT_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_DATA_ROUTE_ERROR         , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA_ROUTE_ERROR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_HANG_RECOVERY_GTE_LEVEL1 , 9   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_HANG_RECOVERY_GTE_LEVEL1 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_FORCE_MP_IPL             , 10  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_FORCE_MP_IPL );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_11                 , 11  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_11   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_12                 , 12  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_12   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_13                 , 13  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_13   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_14                 , 14  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_14   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_15                 , 15  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_15   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SCOM_ERR                 , 16  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SCOM_ERR_DUP             , 17  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL0         , 0   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL0   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL0_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL0_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL1         , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL1   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL1_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL1_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL2         , 16  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL2   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL2_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL2_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL3         , 24  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL3   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL3_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL3_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL4         , 32  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL4   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL4_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL4_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL5         , 40  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL5   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL5_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL5_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL6         , 48  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL6   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL6_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL6_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL7         , 56  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL7   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL7_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL7_LEN );
+
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL0         , 0   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL0   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL0_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL0_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL1         , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL1   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL1_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL1_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL2         , 16  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL2   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL2_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL2_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL3         , 24  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL3   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL3_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL3_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL4         , 32  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL4   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL4_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL4_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL5         , 40  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL5   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL5_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL5_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL6         , 48  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL6   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL6_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL6_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL7         , 56  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL7   );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL7_LEN     , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LVL7_LEN );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_EN     , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_EN     , 1   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X2_EN     , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X3_EN     , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X4_EN     , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X5_EN     , 5   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X6_EN     , 6   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX0_ADDR_DIS , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX0_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX1_ADDR_DIS , 9   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX1_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX2_ADDR_DIS , 10  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX2_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX3_ADDR_DIS , 11  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX3_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX4_ADDR_DIS , 12  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX4_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX5_ADDR_DIS , 13  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX5_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX6_ADDR_DIS , 14  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX6_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_CHIPID , 16  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_CHIPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_CHIPID_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_CHIPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_CHIPID , 19  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_CHIPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_CHIPID_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_CHIPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X2_CHIPID , 22  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_CHIPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X2_CHIPID_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_CHIPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X3_CHIPID , 25  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_CHIPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X3_CHIPID_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_CHIPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X4_CHIPID , 28  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_CHIPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X4_CHIPID_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_CHIPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X5_CHIPID , 31  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_CHIPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X5_CHIPID_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_CHIPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X6_CHIPID , 34  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_CHIPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X6_CHIPID_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_CHIPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_AGGREGATE    , 37  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_AGGREGATE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_FP_DISABLED  , 48  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_FP_DISABLED );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_INDIRECT_EN  , 49  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_INDIRECT_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_GATHER_ENABLE , 50  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_GATHER_ENABLE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_CMD_RATE     , 56  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_CMD_RATE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_CMD_RATE_LEN , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_CMD_RATE_LEN );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X0_EN     , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X1_EN     , 1   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X2_EN     , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X3_EN     , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X4_EN     , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X5_EN     , 5   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X6_EN     , 6   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX0_ADDR_DIS , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX0_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX1_ADDR_DIS , 9   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX1_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX2_ADDR_DIS , 10  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX2_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX3_ADDR_DIS , 11  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX3_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX4_ADDR_DIS , 12  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX4_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX5_ADDR_DIS , 13  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX5_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX6_ADDR_DIS , 14  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX6_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID , 16  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_CHIPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_CHIPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID , 19  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_CHIPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_CHIPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID , 22  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_CHIPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_CHIPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID , 25  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_CHIPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_CHIPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID , 28  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_CHIPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_CHIPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID , 31  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_CHIPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_CHIPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID , 34  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_CHIPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID_LEN , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_CHIPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_AGGREGATE    , 37  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_AGGREGATE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_FP_DISABLED  , 48  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_FP_DISABLED );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_INDIRECT_EN  , 49  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_INDIRECT_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_GATHER_ENABLE , 50  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_GATHER_ENABLE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_CMD_RATE     , 56  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_CMD_RATE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_CMD_RATE_LEN , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_CMD_RATE_LEN );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_MASTER_CHIP     , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_MASTER_CHIP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_TM_MASTER       , 1   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TM_MASTER );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_CHG_RATE_GP_MASTER , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CHG_RATE_GP_MASTER );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_CHG_RATE_SP_MASTER , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CHG_RATE_SP_MASTER );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A0_EN      , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A1_EN      , 5   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A2_EN      , 6   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A3_EN      , 7   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA0_ADDR_DIS , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA0_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA1_ADDR_DIS , 9   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA1_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA2_ADDR_DIS , 10  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA2_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA3_ADDR_DIS , 11  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA3_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A0_GROUPID , 12  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_GROUPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A0_GROUPID_LEN , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_GROUPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A1_GROUPID , 16  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_GROUPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A1_GROUPID_LEN , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_GROUPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A2_GROUPID , 20  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_GROUPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A2_GROUPID_LEN , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_GROUPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A3_GROUPID , 24  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_GROUPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A3_GROUPID_LEN , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_GROUPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_AGGREGATE     , 28  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_AGGREGATE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_HOP             , 29  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_HOP    );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_SMP_OPTICS      , 30  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SMP_OPTICS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_CAPI            , 31  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CAPI   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT0            , 32  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT0   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT0_LEN        , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT0_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT1            , 34  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT1   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT1_LEN        , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT1_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT2            , 36  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT2   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT2_LEN        , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT2_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT3            , 38  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT3   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT3_LEN        , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT3_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID , 40  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_XLATE_ADDR_TO_ID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN , 7   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_GATHER_ENABLE , 50  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_GATHER_ENABLE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PHYP_IS_GROUP   , 52  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PHYP_IS_GROUP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_ADDR_BAR        , 53  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_ADDR_BAR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PUMP            , 54  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PUMP   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_DCACHE_CAPP     , 55  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_DCACHE_CAPP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_CMD_RATE      , 56  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_CMD_RATE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_CMD_RATE_LEN  , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_CMD_RATE_LEN );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_MASTER_CHIP     , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_MASTER_CHIP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_TM_MASTER       , 1   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TM_MASTER );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_CHG_RATE_GP_MASTER , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CHG_RATE_GP_MASTER );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_CHG_RATE_SP_MASTER , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CHG_RATE_SP_MASTER );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A0_EN      , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A1_EN      , 5   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A2_EN      , 6   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A3_EN      , 7   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA0_ADDR_DIS , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA0_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA1_ADDR_DIS , 9   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA1_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA2_ADDR_DIS , 10  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA2_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA3_ADDR_DIS , 11  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA3_ADDR_DIS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A0_GROUPID , 12  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_GROUPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A0_GROUPID_LEN , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_GROUPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A1_GROUPID , 16  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_GROUPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A1_GROUPID_LEN , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_GROUPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A2_GROUPID , 20  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_GROUPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A2_GROUPID_LEN , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_GROUPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A3_GROUPID , 24  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_GROUPID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A3_GROUPID_LEN , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_GROUPID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_AGGREGATE     , 28  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_AGGREGATE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_HOP             , 29  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_HOP    );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_SMP_OPTICS      , 30  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SMP_OPTICS );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_CAPI            , 31  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CAPI   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT0            , 32  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT0   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT0_LEN        , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT0_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT1            , 34  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT1   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT1_LEN        , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT1_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT2            , 36  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT2   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT2_LEN        , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT2_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT3            , 38  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT3   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT3_LEN        , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT3_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID , 40  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_XLATE_ADDR_TO_ID );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN , 7   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_GATHER_ENABLE , 50  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_GATHER_ENABLE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_PHYP_IS_GROUP   , 52  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PHYP_IS_GROUP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_ADDR_BAR        , 53  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_ADDR_BAR );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_PUMP            , 54  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PUMP   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_DCACHE_CAPP     , 55  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_DCACHE_CAPP );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_CMD_RATE      , 56  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_CMD_RATE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN  , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_CMD_RATE_LEN );
+
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_DD1_MODE    , 0   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_APM_DD1_MODE );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_SEL         , 1   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_APM_SEL );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_SEL_LEN     , 2   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_APM_SEL_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_PMU_FREEZE_MODE , 4   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMU_FREEZE_MODE );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_HI_COMP  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_APM_LM_HI_COMP );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_HI_COMP_LEN , 4   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_APM_LM_HI_COMP_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_LO_COMP  , 12  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_APM_LM_LO_COMP );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_LO_COMP_LEN , 4   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_APM_LM_LO_COMP_LEN );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CHIP_IS_SYSTEM          , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CHIP_IS_SYSTEM );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_HNG_CHK_DISABLE         , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_HNG_CHK_DISABLE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_DBG_CLR_MAX_HANG_STAGE      , 9   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_DBG_CLR_MAX_HANG_STAGE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SW_AB_WAIT              , 12  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SW_AB_WAIT );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SW_AB_WAIT_LEN          , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SW_AB_WAIT_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SP_HW_MARK              , 16  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SP_HW_MARK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SP_HW_MARK_LEN          , 7   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SP_HW_MARK_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_GP_HW_MARK              , 23  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_GP_HW_MARK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_GP_HW_MARK_LEN          , 7   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_GP_HW_MARK_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_LCL_HW_MARK             , 30  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LCL_HW_MARK );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_LCL_HW_MARK_LEN         , 6   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LCL_HW_MARK_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_REQ_GATHER_ENABLE       , 57  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_REQ_GATHER_ENABLE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SWITCH_CD_PULSE         , 58  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SWITCH_CD_PULSE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SWITCH_OPTION_AB        , 59  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SWITCH_OPTION_AB );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_RESET_ERROR_CAPTURE     , 63  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RESET_ERROR_CAPTURE );
+
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_ENABLE      , 0   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_APM_ENABLE );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_SAMPLE_SEL  , 1   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_APM_SAMPLE_SEL );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_SAMPLE_SEL_LEN , 2   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_APM_SAMPLE_SEL_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_PMUCNT_EN       , 3   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMUCNT_EN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_PMUCNT_SEL      , 4   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMUCNT_SEL );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_PMUCNT_SEL_LEN  , 2   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PMUCNT_SEL_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_HI_COMP  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_APM_NM_HI_COMP );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_HI_COMP_LEN , 4   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_APM_NM_HI_COMP_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_LO_COMP  , 12  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_APM_NM_LO_COMP );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_LO_COMP_LEN , 4   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_APM_NM_LO_COMP_LEN );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C0  , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP0_C0 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C0_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP0_C0_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C1  , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP0_C1 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C1_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP0_C1_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C2  , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP0_C2 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C2_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP0_C2_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C3  , 6   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP0_C3 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C3_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP0_C3_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C0  , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP1_C0 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C0_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP1_C0_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C1  , 10  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP1_C1 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C1_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP1_C1_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C2  , 12  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP1_C2 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C2_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP1_C2_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C3  , 14  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP1_C3 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C3_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP1_C3_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C0  , 16  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP2_C0 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C0_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP2_C0_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C1  , 18  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP2_C1 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C1_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP2_C1_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C2  , 20  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP2_C2 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C2_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP2_C2_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C3  , 22  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP2_C3 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C3_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP2_C3_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C0  , 24  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP3_C0 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C0_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP3_C0_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C1  , 26  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP3_C1 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C1_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP3_C1_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C2  , 28  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP3_C2 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C2_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP3_C2_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C3  , 30  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP3_C3 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C3_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPME_GRP3_C3_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C0  , 33  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP0_C0 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C1  , 34  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP0_C1 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C1_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP0_C1_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C2  , 36  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP0_C2 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C2_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP0_C2_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C3  , 38  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP0_C3 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C3_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP0_C3_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C0  , 40  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP1_C0 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C0_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP1_C0_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C1  , 42  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP1_C1 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C1_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP1_C1_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C2  , 44  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP1_C2 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C2_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP1_C2_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C3  , 46  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP1_C3 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C3_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP1_C3_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C0  , 48  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP2_C0 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C0_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP2_C0_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C1  , 50  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP2_C1 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C1_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP2_C1_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C2  , 52  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP2_C2 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C2_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP2_C2_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C3  , 54  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP2_C3 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C3_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP2_C3_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C0  , 56  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP3_C0 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C0_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP3_C0_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C1  , 58  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP3_C1 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C1_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP3_C1_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C2  , 60  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP3_C2 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C2_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP3_C2_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C3  , 62  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP3_C3 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C3_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CNPMW_GRP3_C3_LEN );
+
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL0    , 0   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL0 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL0_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL0_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL1    , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL1 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL1_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL1_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL2    , 16  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL2 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL2_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL2_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL3    , 24  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL3 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL3_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL3_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL4    , 32  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL4 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL4_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL4_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL5    , 40  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL5 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL5_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL5_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL6    , 48  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL6 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL6_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL6_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL7    , 56  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL7 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL7_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL7_LEN );
+
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL0    , 0   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL0 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL0_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL0_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL1    , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL1 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL1_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL1_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL2    , 16  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL2 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL2_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL2_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL3    , 24  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL3 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL3_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL3_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL4    , 32  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL4 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL4_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL4_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL5    , 40  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL5 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL5_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL5_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL6    , 48  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL6 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL6_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL6_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL7    , 56  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL7 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL7_LEN , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_RNS_LVL7_LEN );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG                 , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG        );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SLOW            , 1   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SLOW   );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_COUNT     , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SHIFT_COUNT );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_COUNT_LEN , 6   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SHIFT_COUNT_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SELECT          , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELECT );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SELECT_LEN      , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELECT_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_DATA      , 12  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SHIFT_DATA );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN  , 52  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SHIFT_DATA_LEN );
+
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL0      , 0   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL0 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL0_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL0_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL1      , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL1 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL1_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL1_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL2      , 16  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL2 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL2_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL2_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL3      , 24  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL3 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL3_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL3_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL4      , 32  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL4 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL4_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL4_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL5      , 40  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL5 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL5_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL5_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL6      , 48  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL6 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL6_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL6_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL7      , 56  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL7 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL7_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL7_LEN );
+
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL0      , 0   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL0 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL0_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL0_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL1      , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL1 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL1_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL1_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL2      , 16  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL2 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL2_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL2_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL3      , 24  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL3 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL3_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL3_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL4      , 32  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL4 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL4_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL4_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL5      , 40  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL5 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL5_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL5_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL6      , 48  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL6 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL6_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL6_LEN );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL7      , 56  , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL7 );
+REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL7_LEN  , 8   , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CFG_VG_LVL7_LEN );
+
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN0                 , 0   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELSN0 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN0_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELSN0_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN1                 , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELSN1 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN1_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELSN1_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN2                 , 4   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELSN2 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN2_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELSN2_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN3                 , 6   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELSN3 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN3_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELSN3_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR0                 , 8   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELCR0 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR0_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELCR0_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR1                 , 10  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELCR1 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR1_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELCR1_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR2                 , 12  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELCR2 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR2_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELCR2_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR3                 , 14  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELCR3 );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR3_LEN             , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELCR3_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_0_SEL        , 16  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PBIEN_DBG_0_SEL );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_0_SEL_LEN    , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PBIEN_DBG_0_SEL_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_1_SEL        , 18  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PBIEN_DBG_1_SEL );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_1_SEL_LEN    , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PBIEN_DBG_1_SEL_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_0_SEL        , 20  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PBIES_DBG_0_SEL );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_0_SEL_LEN    , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PBIES_DBG_0_SEL_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_1_SEL        , 22  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PBIES_DBG_1_SEL );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_1_SEL_LEN    , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PBIES_DBG_1_SEL_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_0_SEL        , 24  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PBIOT_DBG_0_SEL );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_0_SEL_LEN    , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PBIOT_DBG_0_SEL_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_1_SEL        , 26  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PBIOT_DBG_1_SEL );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_1_SEL_LEN    , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PBIOT_DBG_1_SEL_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_SEL              , 28  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PBIOT_SEL );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELRT                  , 29  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELRT  );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELRT_LEN              , 3   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELRT_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_EN           , 32  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PERFTRACE_EN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_TRIG         , 33  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PERFTRACE_TRIG );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_SEL  , 34  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PERFTRACE_COUNTER_SEL );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_SEL_LEN , 2   , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PERFTRACE_COUNTER_SEL_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_MATCH , 36  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PERFTRACE_COUNTER_MATCH );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_MATCH_LEN , 16  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PERFTRACE_COUNTER_MATCH_LEN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_ENABLE_PERFTRACE_PRESCALE , 52  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_ENABLE_PERFTRACE_PRESCALE );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_ENABLE_PERFTRACE_FIXED_WIN , 53  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_ENABLE_PERFTRACE_FIXED_WIN );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_GRP1_SEL     , 54  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PERFTRACE_GRP1_SEL );
+REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_GRP2_SEL     , 55  , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PERFTRACE_GRP2_SEL );
+
+REG64_FLD( PU_PB_EAST_FIR_ACTION0_REG_ACTION0                      , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( PU_PB_EAST_FIR_ACTION0_REG_ACTION0_LEN                  , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_PB_EAST_FIR_ACTION1_REG_ACTION1                      , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( PU_PB_EAST_FIR_ACTION1_REG_ACTION1_LEN                  , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_HW1_ERROR           , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ04_PBH_HW1_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_HW2_ERROR           , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ04_PBH_HW2_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_PROTOCOL_ERROR      , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ04_PBH_PROTOCOL_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_OVERFLOW_ERROR      , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ04_PBH_OVERFLOW_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_HW1_ERROR           , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ05_PBH_HW1_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_HW2_ERROR           , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ05_PBH_HW2_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_PROTOCOL_ERROR      , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ05_PBH_PROTOCOL_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_OVERFLOW_ERROR      , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ05_PBH_OVERFLOW_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_8                         , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_8    );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_9                         , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_9    );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_10                        , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_10   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_11                        , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_11   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_12                        , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_12   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_13                        , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_13   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_14                        , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_14   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_15                        , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_15   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_OVERFLOW_CHECKSTOP              , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OVERFLOW_CHECKSTOP );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PROTOCOL_CHECKSTOP              , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROTOCOL_CHECKSTOP );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_ROUTE_CHECKSTOP                 , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ROUTE_CHECKSTOP );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_19                        , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_19   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_20                        , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_20   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_21                        , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_21   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_22                        , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_22   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_23                        , 23  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_23   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_24                        , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_24   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_25                        , 25  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_25   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_26                        , 26  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_26   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_27                        , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_27   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_28                        , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_28   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_29                        , 29  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_29   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_30                        , 30  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_30   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_31                        , 31  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_31   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SCOM_ERR                        , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SCOM_ERR_DUP                    , 33  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+
+REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ04_PBH_HW1_ERROR                , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ04_PBH_HW1_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ04_PBH_HW2_ERROR                , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ04_PBH_HW2_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ04_PBH_PROTOCOL_ERROR           , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ04_PBH_PROTOCOL_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ04_PBH_OVERFLOW_ERROR           , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ04_PBH_OVERFLOW_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ05_PBH_HW1_ERROR                , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ05_PBH_HW1_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ05_PBH_HW2_ERROR                , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ05_PBH_HW2_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ05_PBH_PROTOCOL_ERROR           , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ05_PBH_PROTOCOL_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ05_PBH_OVERFLOW_ERROR           , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ05_PBH_OVERFLOW_ERROR );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_8                              , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_8    );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_9                              , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_9    );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_10                             , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_10   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_11                             , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_11   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_12                             , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_12   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_13                             , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_13   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_14                             , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_14   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_15                             , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_15   );
+REG64_FLD( PU_PB_EAST_FIR_REG_OVERFLOW_CHECKSTOP                   , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OVERFLOW_CHECKSTOP );
+REG64_FLD( PU_PB_EAST_FIR_REG_PROTOCOL_CHECKSTOP                   , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROTOCOL_CHECKSTOP );
+REG64_FLD( PU_PB_EAST_FIR_REG_ROUTE_CHECKSTOP                      , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ROUTE_CHECKSTOP );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_19                             , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_19   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_20                             , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_20   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_21                             , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_21   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_22                             , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_22   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_23                             , 23  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_23   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_24                             , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_24   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_25                             , 25  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_25   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_26                             , 26  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_26   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_27                             , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_27   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_28                             , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_28   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_29                             , 29  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_29   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_30                             , 30  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_30   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_31                             , 31  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_31   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SCOM_ERR                             , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+REG64_FLD( PU_PB_EAST_FIR_REG_SCOM_ERR_DUP                         , 33  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_EN                 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_EN                 , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X2_EN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X3_EN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X4_EN                 , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X5_EN                 , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X6_EN                 , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX0_ADDR_DIS          , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX0_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX1_ADDR_DIS          , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX1_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX2_ADDR_DIS          , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX2_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX3_ADDR_DIS          , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX3_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX4_ADDR_DIS          , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX4_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX5_ADDR_DIS          , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX5_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX6_ADDR_DIS          , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX6_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_CHIPID );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_CHIPID_LEN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID             , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_CHIPID );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_CHIPID_LEN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID             , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_CHIPID );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_CHIPID_LEN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID             , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_CHIPID );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_CHIPID_LEN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID             , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_CHIPID );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_CHIPID_LEN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID             , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_CHIPID );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_CHIPID_LEN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID             , 34  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_CHIPID );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_CHIPID_LEN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_AGGREGATE                , 37  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_AGGREGATE );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_FP_DISABLED              , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_FP_DISABLED );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_INDIRECT_EN              , 49  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_INDIRECT_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_GATHER_ENABLE            , 50  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_GATHER_ENABLE );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_CMD_RATE                 , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_CMD_RATE );
+REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_CMD_RATE_LEN             , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_CMD_RATE_LEN );
+
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X0_EN                 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X1_EN                 , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X2_EN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X3_EN                 , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X4_EN                 , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X5_EN                 , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X6_EN                 , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX0_ADDR_DIS          , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX0_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX1_ADDR_DIS          , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX1_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX2_ADDR_DIS          , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX2_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX3_ADDR_DIS          , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX3_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX4_ADDR_DIS          , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX4_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX5_ADDR_DIS          , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX5_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX6_ADDR_DIS          , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX6_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_CHIPID );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_CHIPID_LEN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID             , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_CHIPID );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_CHIPID_LEN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID             , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_CHIPID );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_CHIPID_LEN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID             , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_CHIPID );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_CHIPID_LEN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID             , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_CHIPID );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_CHIPID_LEN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID             , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_CHIPID );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_CHIPID_LEN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID             , 34  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_CHIPID );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID_LEN         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_CHIPID_LEN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_AGGREGATE                , 37  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_AGGREGATE );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_FP_DISABLED              , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_FP_DISABLED );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_INDIRECT_EN              , 49  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_INDIRECT_EN );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_GATHER_ENABLE            , 50  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_GATHER_ENABLE );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_CMD_RATE                 , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_CMD_RATE );
+REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_CMD_RATE_LEN             , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_CMD_RATE_LEN );
+
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_MASTER_CHIP                 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_MASTER_CHIP );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_TM_MASTER                   , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_TM_MASTER );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_CHG_RATE_GP_MASTER          , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_CHG_RATE_GP_MASTER );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_CHG_RATE_SP_MASTER          , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_CHG_RATE_SP_MASTER );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A0_EN                  , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_EN );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A1_EN                  , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_EN );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A2_EN                  , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_EN );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A3_EN                  , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_EN );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA0_ADDR_DIS           , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA0_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA1_ADDR_DIS           , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA1_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA2_ADDR_DIS           , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA2_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA3_ADDR_DIS           , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA3_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A0_GROUPID             , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_GROUPID );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A0_GROUPID_LEN         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_GROUPID_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A1_GROUPID             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_GROUPID );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A1_GROUPID_LEN         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_GROUPID_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A2_GROUPID             , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_GROUPID );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A2_GROUPID_LEN         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_GROUPID_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A3_GROUPID             , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_GROUPID );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A3_GROUPID_LEN         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_GROUPID_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_A_AGGREGATE                 , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_AGGREGATE );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_HOP                         , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_HOP    );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_SMP_OPTICS                  , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SMP_OPTICS );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_CAPI                        , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_CAPI   );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT0                        , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT0   );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT0_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT0_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT1                        , 34  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT1   );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT1_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT1_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT2                        , 36  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT2   );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT2_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT2_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT3                        , 38  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT3   );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT3_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT3_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID            , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_XLATE_ADDR_TO_ID );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN        , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_A_GATHER_ENABLE             , 50  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_GATHER_ENABLE );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_PHYP_IS_GROUP               , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PHYP_IS_GROUP );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_ADDR_BAR                    , 53  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_ADDR_BAR );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_PUMP                        , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PUMP   );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_DCACHE_CAPP                 , 55  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DCACHE_CAPP );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_A_CMD_RATE                  , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_CMD_RATE );
+REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_A_CMD_RATE_LEN              , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_CMD_RATE_LEN );
+
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_MASTER_CHIP                 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_MASTER_CHIP );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_TM_MASTER                   , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_TM_MASTER );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_CHG_RATE_GP_MASTER          , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_CHG_RATE_GP_MASTER );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_CHG_RATE_SP_MASTER          , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_CHG_RATE_SP_MASTER );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A0_EN                  , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_EN );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A1_EN                  , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_EN );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A2_EN                  , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_EN );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A3_EN                  , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_EN );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA0_ADDR_DIS           , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA0_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA1_ADDR_DIS           , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA1_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA2_ADDR_DIS           , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA2_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA3_ADDR_DIS           , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA3_ADDR_DIS );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID             , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_GROUPID );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID_LEN         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_GROUPID_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID             , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_GROUPID );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID_LEN         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_GROUPID_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID             , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_GROUPID );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID_LEN         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_GROUPID_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID             , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_GROUPID );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID_LEN         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_GROUPID_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_AGGREGATE                 , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_AGGREGATE );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_HOP                         , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_HOP    );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_SMP_OPTICS                  , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SMP_OPTICS );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_CAPI                        , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_CAPI   );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT0                        , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT0   );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT0_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT0_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT1                        , 34  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT1   );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT1_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT1_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT2                        , 36  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT2   );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT2_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT2_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT3                        , 38  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT3   );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT3_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT3_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID            , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_XLATE_ADDR_TO_ID );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN        , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_GATHER_ENABLE             , 50  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_GATHER_ENABLE );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_PHYP_IS_GROUP               , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PHYP_IS_GROUP );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_ADDR_BAR                    , 53  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_ADDR_BAR );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_PUMP                        , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PUMP   );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_DCACHE_CAPP                 , 55  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DCACHE_CAPP );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_CMD_RATE                  , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_CMD_RATE );
+REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN              , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_CMD_RATE_LEN );
+
+REG64_FLD( PU_PB_EAST_MODE_CFG_CHIP_IS_SYSTEM                      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_CHIP_IS_SYSTEM );
+REG64_FLD( PU_PB_EAST_MODE_CFG_HNG_CHK_DISABLE                     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_HNG_CHK_DISABLE );
+REG64_FLD( PU_PB_EAST_MODE_DBG_CLR_MAX_HANG_STAGE                  , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DBG_CLR_MAX_HANG_STAGE );
+REG64_FLD( PU_PB_EAST_MODE_CFG_SW_AB_WAIT                          , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SW_AB_WAIT );
+REG64_FLD( PU_PB_EAST_MODE_CFG_SW_AB_WAIT_LEN                      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SW_AB_WAIT_LEN );
+REG64_FLD( PU_PB_EAST_MODE_CFG_SP_HW_MARK                          , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SP_HW_MARK );
+REG64_FLD( PU_PB_EAST_MODE_CFG_SP_HW_MARK_LEN                      , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SP_HW_MARK_LEN );
+REG64_FLD( PU_PB_EAST_MODE_CFG_GP_HW_MARK                          , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_GP_HW_MARK );
+REG64_FLD( PU_PB_EAST_MODE_CFG_GP_HW_MARK_LEN                      , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_GP_HW_MARK_LEN );
+REG64_FLD( PU_PB_EAST_MODE_CFG_LCL_HW_MARK                         , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LCL_HW_MARK );
+REG64_FLD( PU_PB_EAST_MODE_CFG_LCL_HW_MARK_LEN                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LCL_HW_MARK_LEN );
+REG64_FLD( PU_PB_EAST_MODE_CFG_REQ_GATHER_ENABLE                   , 57  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_REQ_GATHER_ENABLE );
+REG64_FLD( PU_PB_EAST_MODE_CFG_SWITCH_CD_PULSE                     , 58  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SWITCH_CD_PULSE );
+REG64_FLD( PU_PB_EAST_MODE_CFG_SWITCH_OPTION_AB                    , 59  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SWITCH_OPTION_AB );
+
+REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG                             , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG        );
+REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SLOW                        , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SLOW   );
+REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_COUNT                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SHIFT_COUNT );
+REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_COUNT_LEN             , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SHIFT_COUNT_LEN );
+REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SELECT                      , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELECT );
+REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SELECT_LEN                  , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELECT_LEN );
+REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_DATA                  , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SHIFT_DATA );
+REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN              , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SHIFT_DATA_LEN );
+
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT             , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK0_DOB_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT_LEN         , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK0_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT         , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK0_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT_LEN     , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK0_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT         , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK0_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT_LEN     , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK0_DOB_VC1_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT         , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK01_DIB_VC_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT_LEN     , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK01_DIB_VC_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_LIMIT             , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK1_DOB_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_LIMIT_LEN         , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK1_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT         , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK1_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT_LEN     , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK1_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT         , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK1_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT_LEN     , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK1_DOB_VC1_LIMIT_LEN );
+
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT             , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK2_DOB_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT_LEN         , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK2_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT         , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK2_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT_LEN     , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK2_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT         , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK2_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT_LEN     , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK2_DOB_VC1_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT         , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK23_DIB_VC_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT_LEN     , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK23_DIB_VC_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT             , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK3_DOB_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT_LEN         , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK3_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT         , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK3_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT_LEN     , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK3_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT         , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK3_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT_LEN     , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK3_DOB_VC1_LIMIT_LEN );
+
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT             , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK4_DOB_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT_LEN         , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK4_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT         , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK4_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT_LEN     , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK4_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT         , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK4_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT_LEN     , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK4_DOB_VC1_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT         , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK45_DIB_VC_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT_LEN     , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK45_DIB_VC_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT             , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK5_DOB_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT_LEN         , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK5_DOB_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT         , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK5_DOB_VC0_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT_LEN     , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK5_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT         , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK5_DOB_VC1_LIMIT );
+REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT_LEN     , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK5_DOB_VC1_LIMIT_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER0                               , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER0_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER1                               , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER1_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER2                               , 32  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER2_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER3                               , 48  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU0_COUNTER3_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER0                               , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER0_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER1                               , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER1_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER2                               , 32  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER2_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER3                               , 48  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU1_COUNTER3_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER0                               , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER0_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER1                               , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER1_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER2                               , 32  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER2_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER3                               , 48  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU2_COUNTER3_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER0                               , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER0_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER1                               , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER1_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER2                               , 32  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER2_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER3                               , 48  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU3_COUNTER3_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER0                               , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER0_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER1                               , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER1_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER2                               , 32  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER2_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER3                               , 48  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU4_COUNTER3_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER0                               , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER0_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER1                               , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER1_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER2                               , 32  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER2_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER3                               , 48  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU5_COUNTER3_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER0                               , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER0_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER1                               , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER1_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER2                               , 32  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER2_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER3                               , 48  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU6_COUNTER3_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER0                               , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER0_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER1                               , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER1_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER2                               , 32  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER2_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER3                               , 48  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_PB_ELINK_PMU7_COUNTER3_LEN                           , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0_ENABLE                     , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU1_ENABLE                     , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU1_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2_ENABLE                     , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU3_ENABLE                     , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU3_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU4_ENABLE                     , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU4_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU5_ENABLE                     , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU5_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU6_ENABLE                     , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU6_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU7_ENABLE                     , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU7_ENABLE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMULET_FREEZE_MODE              , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMULET_FREEZE_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_COMMON_FREEZE_MODE              , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_COMMON_FREEZE_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMULET_RESET_MODE               , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMULET_RESET_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT0_SEL                      , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT0_SEL );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT1_SEL                      , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT1_SEL );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT1_SEL_LEN                  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT1_SEL_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT2_SEL                      , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT2_SEL );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT2_SEL_LEN                  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT2_SEL_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT3_SEL                      , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT3_SEL );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT3_SEL_LEN                  , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT3_SEL_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0_SIZE                       , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0_SIZE  );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0_SIZE_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0_SIZE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU1_SIZE                       , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU1_SIZE  );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU1_SIZE_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU1_SIZE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2_SIZE                       , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2_SIZE  );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2_SIZE_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2_SIZE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU3_SIZE                       , 30  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU3_SIZE  );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU3_SIZE_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU3_SIZE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU01_LINK_SELECT               , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU01_LINK_SELECT );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU23_LINK_SELECT               , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU23_LINK_SELECT );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU45_LINK_SELECT               , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU45_LINK_SELECT );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU67_LINK_SELECT               , 35  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU67_LINK_SELECT );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT0_MODE             , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT0_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT0_MODE_LEN         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT0_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT1_MODE             , 38  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT1_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT1_MODE_LEN         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT1_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT2_MODE             , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT2_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT2_MODE_LEN         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT2_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT3_MODE             , 42  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT3_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT3_MODE_LEN         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT3_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT0_MODE             , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT0_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT0_MODE_LEN         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT0_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT1_MODE             , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT1_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT1_MODE_LEN         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT1_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT2_MODE             , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT2_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT2_MODE_LEN         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT2_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT3_MODE             , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT3_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT3_MODE_LEN         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT3_MODE_LEN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_ENABLE_GLOBAL_RUN               , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_GLOBAL_RUN );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_GLOBAL_RUN_MODE                 , 53  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GLOBAL_RUN_MODE );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_SPARE                           , 54  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_SPARE_LEN                       , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_SET                        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SET        );
+REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_SET_LEN                    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SET_LEN    );
+REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_STAT                       , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STAT       );
+REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_STAT_LEN                   , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STAT_LEN   );
+
+REG64_FLD( PU_PB_FP01_CFG_FP0_CREDIT_PRIORITY_4_NOT_8              , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_PB_FP01_CFG_FP0_DISABLE_GATHERING                    , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_DISABLE_GATHERING );
+REG64_FLD( PU_PB_FP01_CFG_FP0_DISABLE_CMD_COMPRESSION              , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_PB_FP01_CFG_FP0_DISABLE_PRSP_COMPRESSION             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT                   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT_LEN               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT                   , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT_LEN               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_PB_FP01_CFG_FP0_FMR_DISABLE                          , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_FMR_DISABLE );
+REG64_FLD( PU_PB_FP01_CFG_FP0_FMR_SPARE                            , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_FMR_SPARE );
+REG64_FLD( PU_PB_FP01_CFG_CMD_EXP_TIME                             , 22  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_EXP_TIME );
+REG64_FLD( PU_PB_FP01_CFG_CMD_EXP_TIME_LEN                         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_EXP_TIME_LEN );
+REG64_FLD( PU_PB_FP01_CFG_FP0_RUN_AFTER_FRAME_ERROR                , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_PB_FP01_CFG_FP0_PRS_DISABLE                          , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_PRS_DISABLE );
+REG64_FLD( PU_PB_FP01_CFG_FP0_PRS_SPARE                            , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_PRS_SPARE );
+REG64_FLD( PU_PB_FP01_CFG_FP0_PRS_SPARE_LEN                        , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_PRS_SPARE_LEN );
+REG64_FLD( PU_PB_FP01_CFG_FP1_CREDIT_PRIORITY_4_NOT_8              , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_PB_FP01_CFG_FP1_DISABLE_GATHERING                    , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_DISABLE_GATHERING );
+REG64_FLD( PU_PB_FP01_CFG_FP1_DISABLE_CMD_COMPRESSION              , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_PB_FP01_CFG_FP1_DISABLE_PRSP_COMPRESSION             , 35  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT                   , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT_LEN               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT                   , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT_LEN               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_PB_FP01_CFG_FP1_FMR_DISABLE                          , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_FMR_DISABLE );
+REG64_FLD( PU_PB_FP01_CFG_FP1_FMR_SPARE                            , 53  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_FMR_SPARE );
+REG64_FLD( PU_PB_FP01_CFG_FP1_FMR_SPARE_LEN                        , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_FMR_SPARE_LEN );
+REG64_FLD( PU_PB_FP01_CFG_FP1_RUN_AFTER_FRAME_ERROR                , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_PB_FP01_CFG_FP1_PRS_DISABLE                          , 57  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_PRS_DISABLE );
+REG64_FLD( PU_PB_FP01_CFG_FP1_PRS_SPARE                            , 58  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_PRS_SPARE );
+REG64_FLD( PU_PB_FP01_CFG_FP1_PRS_SPARE_LEN                        , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_PRS_SPARE_LEN );
+
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_CREDIT_PRIORITY_4_NOT_8          , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_DISABLE_GATHERING                , 1   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_DISABLE_GATHERING );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_DISABLE_CMD_COMPRESSION          , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_DISABLE_PRSP_COMPRESSION         , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT               , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT               , 12  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_FMR_DISABLE                      , 20  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_FMR_DISABLE );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_FMR_SPARE                        , 21  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_FMR_SPARE );
+REG64_FLD( PU_IOE_PB_FP01_CFG_CMD_EXP_TIME                         , 22  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_EXP_TIME );
+REG64_FLD( PU_IOE_PB_FP01_CFG_CMD_EXP_TIME_LEN                     , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_EXP_TIME_LEN );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_RUN_AFTER_FRAME_ERROR            , 24  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_PRS_DISABLE                      , 25  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_PRS_DISABLE );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_PRS_SPARE                        , 26  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_PRS_SPARE );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_PRS_SPARE_LEN                    , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP0_PRS_SPARE_LEN );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_CREDIT_PRIORITY_4_NOT_8          , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_DISABLE_GATHERING                , 33  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_DISABLE_GATHERING );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_DISABLE_CMD_COMPRESSION          , 34  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_DISABLE_PRSP_COMPRESSION         , 35  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT               , 36  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT               , 44  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_FMR_DISABLE                      , 52  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_FMR_DISABLE );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_FMR_SPARE                        , 53  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_FMR_SPARE );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_FMR_SPARE_LEN                    , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_FMR_SPARE_LEN );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_RUN_AFTER_FRAME_ERROR            , 56  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_PRS_DISABLE                      , 57  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_PRS_DISABLE );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_PRS_SPARE                        , 58  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_PRS_SPARE );
+REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_PRS_SPARE_LEN                    , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP1_PRS_SPARE_LEN );
+
+REG64_FLD( PU_PB_FP23_CFG_FP2_CREDIT_PRIORITY_4_NOT_8              , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_PB_FP23_CFG_FP2_DISABLE_GATHERING                    , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_DISABLE_GATHERING );
+REG64_FLD( PU_PB_FP23_CFG_FP2_DISABLE_CMD_COMPRESSION              , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_PB_FP23_CFG_FP2_DISABLE_PRSP_COMPRESSION             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT                   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT_LEN               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT                   , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT_LEN               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_PB_FP23_CFG_FP2_FMR_DISABLE                          , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_FMR_DISABLE );
+REG64_FLD( PU_PB_FP23_CFG_FP2_FMR_SPARE                            , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_FMR_SPARE );
+REG64_FLD( PU_PB_FP23_CFG_CMD_EXP_TIME                             , 22  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_EXP_TIME );
+REG64_FLD( PU_PB_FP23_CFG_CMD_EXP_TIME_LEN                         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_EXP_TIME_LEN );
+REG64_FLD( PU_PB_FP23_CFG_FP2_RUN_AFTER_FRAME_ERROR                , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_PB_FP23_CFG_FP2_PRS_DISABLE                          , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_PRS_DISABLE );
+REG64_FLD( PU_PB_FP23_CFG_FP2_PRS_SPARE                            , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_PRS_SPARE );
+REG64_FLD( PU_PB_FP23_CFG_FP2_PRS_SPARE_LEN                        , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_PRS_SPARE_LEN );
+REG64_FLD( PU_PB_FP23_CFG_FP3_CREDIT_PRIORITY_4_NOT_8              , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_PB_FP23_CFG_FP3_DISABLE_GATHERING                    , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_DISABLE_GATHERING );
+REG64_FLD( PU_PB_FP23_CFG_FP3_DISABLE_CMD_COMPRESSION              , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_PB_FP23_CFG_FP3_DISABLE_PRSP_COMPRESSION             , 35  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT                   , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT_LEN               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT                   , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT_LEN               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_PB_FP23_CFG_FP3_FMR_DISABLE                          , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_FMR_DISABLE );
+REG64_FLD( PU_PB_FP23_CFG_FP3_FMR_SPARE                            , 53  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_FMR_SPARE );
+REG64_FLD( PU_PB_FP23_CFG_FP3_FMR_SPARE_LEN                        , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_FMR_SPARE_LEN );
+REG64_FLD( PU_PB_FP23_CFG_FP3_RUN_AFTER_FRAME_ERROR                , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_PB_FP23_CFG_FP3_PRS_DISABLE                          , 57  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_PRS_DISABLE );
+REG64_FLD( PU_PB_FP23_CFG_FP3_PRS_SPARE                            , 58  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_PRS_SPARE );
+REG64_FLD( PU_PB_FP23_CFG_FP3_PRS_SPARE_LEN                        , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_PRS_SPARE_LEN );
+
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_CREDIT_PRIORITY_4_NOT_8          , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_DISABLE_GATHERING                , 1   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_DISABLE_GATHERING );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_DISABLE_CMD_COMPRESSION          , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_DISABLE_PRSP_COMPRESSION         , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT               , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT               , 12  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_FMR_DISABLE                      , 20  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_FMR_DISABLE );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_FMR_SPARE                        , 21  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_FMR_SPARE );
+REG64_FLD( PU_IOE_PB_FP23_CFG_CMD_EXP_TIME                         , 22  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_EXP_TIME );
+REG64_FLD( PU_IOE_PB_FP23_CFG_CMD_EXP_TIME_LEN                     , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_EXP_TIME_LEN );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_RUN_AFTER_FRAME_ERROR            , 24  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_PRS_DISABLE                      , 25  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_PRS_DISABLE );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_PRS_SPARE                        , 26  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_PRS_SPARE );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_PRS_SPARE_LEN                    , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP2_PRS_SPARE_LEN );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_CREDIT_PRIORITY_4_NOT_8          , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_DISABLE_GATHERING                , 33  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_DISABLE_GATHERING );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_DISABLE_CMD_COMPRESSION          , 34  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_DISABLE_PRSP_COMPRESSION         , 35  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT               , 36  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT               , 44  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_FMR_DISABLE                      , 52  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_FMR_DISABLE );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_FMR_SPARE                        , 53  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_FMR_SPARE );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_FMR_SPARE_LEN                    , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_FMR_SPARE_LEN );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_RUN_AFTER_FRAME_ERROR            , 56  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_PRS_DISABLE                      , 57  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_PRS_DISABLE );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_PRS_SPARE                        , 58  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_PRS_SPARE );
+REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_PRS_SPARE_LEN                    , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP3_PRS_SPARE_LEN );
+
+REG64_FLD( PU_PB_FP45_CFG_FP4_CREDIT_PRIORITY_4_NOT_8              , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_PB_FP45_CFG_FP4_DISABLE_GATHERING                    , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_DISABLE_GATHERING );
+REG64_FLD( PU_PB_FP45_CFG_FP4_DISABLE_CMD_COMPRESSION              , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_PB_FP45_CFG_FP4_DISABLE_PRSP_COMPRESSION             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT                   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT_LEN               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT                   , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT_LEN               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_PB_FP45_CFG_FP4_FMR_DISABLE                          , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_FMR_DISABLE );
+REG64_FLD( PU_PB_FP45_CFG_FP4_FMR_SPARE                            , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_FMR_SPARE );
+REG64_FLD( PU_PB_FP45_CFG_CMD_EXP_TIME                             , 22  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_EXP_TIME );
+REG64_FLD( PU_PB_FP45_CFG_CMD_EXP_TIME_LEN                         , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_EXP_TIME_LEN );
+REG64_FLD( PU_PB_FP45_CFG_FP4_RUN_AFTER_FRAME_ERROR                , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_PB_FP45_CFG_FP4_PRS_DISABLE                          , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_PRS_DISABLE );
+REG64_FLD( PU_PB_FP45_CFG_FP4_PRS_SPARE                            , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_PRS_SPARE );
+REG64_FLD( PU_PB_FP45_CFG_FP4_PRS_SPARE_LEN                        , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_PRS_SPARE_LEN );
+REG64_FLD( PU_PB_FP45_CFG_FP5_CREDIT_PRIORITY_4_NOT_8              , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_PB_FP45_CFG_FP5_DISABLE_GATHERING                    , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_DISABLE_GATHERING );
+REG64_FLD( PU_PB_FP45_CFG_FP5_DISABLE_CMD_COMPRESSION              , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_PB_FP45_CFG_FP5_DISABLE_PRSP_COMPRESSION             , 35  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT                   , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT_LEN               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT                   , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT_LEN               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_PB_FP45_CFG_FP5_FMR_DISABLE                          , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_FMR_DISABLE );
+REG64_FLD( PU_PB_FP45_CFG_FP5_FMR_SPARE                            , 53  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_FMR_SPARE );
+REG64_FLD( PU_PB_FP45_CFG_FP5_FMR_SPARE_LEN                        , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_FMR_SPARE_LEN );
+REG64_FLD( PU_PB_FP45_CFG_FP5_RUN_AFTER_FRAME_ERROR                , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_PB_FP45_CFG_FP5_PRS_DISABLE                          , 57  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_PRS_DISABLE );
+REG64_FLD( PU_PB_FP45_CFG_FP5_PRS_SPARE                            , 58  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_PRS_SPARE );
+REG64_FLD( PU_PB_FP45_CFG_FP5_PRS_SPARE_LEN                        , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_PRS_SPARE_LEN );
+
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_CREDIT_PRIORITY_4_NOT_8          , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_DISABLE_GATHERING                , 1   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_DISABLE_GATHERING );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_DISABLE_CMD_COMPRESSION          , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_DISABLE_PRSP_COMPRESSION         , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT               , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT               , 12  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_FMR_DISABLE                      , 20  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_FMR_DISABLE );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_FMR_SPARE                        , 21  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_FMR_SPARE );
+REG64_FLD( PU_IOE_PB_FP45_CFG_CMD_EXP_TIME                         , 22  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_EXP_TIME );
+REG64_FLD( PU_IOE_PB_FP45_CFG_CMD_EXP_TIME_LEN                     , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_EXP_TIME_LEN );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_RUN_AFTER_FRAME_ERROR            , 24  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_PRS_DISABLE                      , 25  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_PRS_DISABLE );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_PRS_SPARE                        , 26  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_PRS_SPARE );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_PRS_SPARE_LEN                    , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP4_PRS_SPARE_LEN );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_CREDIT_PRIORITY_4_NOT_8          , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_DISABLE_GATHERING                , 33  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_DISABLE_GATHERING );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_DISABLE_CMD_COMPRESSION          , 34  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_DISABLE_PRSP_COMPRESSION         , 35  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT               , 36  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT               , 44  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_FMR_DISABLE                      , 52  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_FMR_DISABLE );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_FMR_SPARE                        , 53  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_FMR_SPARE );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_FMR_SPARE_LEN                    , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_FMR_SPARE_LEN );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_RUN_AFTER_FRAME_ERROR            , 56  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_PRS_DISABLE                      , 57  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_PRS_DISABLE );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_PRS_SPARE                        , 58  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_PRS_SPARE );
+REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_PRS_SPARE_LEN                    , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP5_PRS_SPARE_LEN );
+
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_CREDIT_PRIORITY_4_NOT_8          , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP6_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_DISABLE_GATHERING                , 1   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP6_DISABLE_GATHERING );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_DISABLE_CMD_COMPRESSION          , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP6_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_DISABLE_PRSP_COMPRESSION         , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP6_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_LO_LIMIT               , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP6_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_LO_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP6_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_HI_LIMIT               , 12  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP6_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_HI_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP6_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_FMR_DISABLE                      , 20  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP6_FMR_DISABLE );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_FMR_SPARE                        , 21  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP6_FMR_SPARE );
+REG64_FLD( PU_IOE_PB_FP67_CFG_CMD_EXP_TIME                         , 22  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_EXP_TIME );
+REG64_FLD( PU_IOE_PB_FP67_CFG_CMD_EXP_TIME_LEN                     , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CMD_EXP_TIME_LEN );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_RUN_AFTER_FRAME_ERROR            , 24  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP6_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_PRS_DISABLE                      , 25  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP6_PRS_DISABLE );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_PRS_SPARE                        , 26  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP6_PRS_SPARE );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_PRS_SPARE_LEN                    , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP6_PRS_SPARE_LEN );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_CREDIT_PRIORITY_4_NOT_8          , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP7_CREDIT_PRIORITY_4_NOT_8 );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_DISABLE_GATHERING                , 33  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP7_DISABLE_GATHERING );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_DISABLE_CMD_COMPRESSION          , 34  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP7_DISABLE_CMD_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_DISABLE_PRSP_COMPRESSION         , 35  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP7_DISABLE_PRSP_COMPRESSION );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_LO_LIMIT               , 36  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP7_LL_CREDIT_LO_LIMIT );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_LO_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP7_LL_CREDIT_LO_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_HI_LIMIT               , 44  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP7_LL_CREDIT_HI_LIMIT );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_HI_LIMIT_LEN           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP7_LL_CREDIT_HI_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_FMR_DISABLE                      , 52  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP7_FMR_DISABLE );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_FMR_SPARE                        , 53  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP7_FMR_SPARE );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_FMR_SPARE_LEN                    , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP7_FMR_SPARE_LEN );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_RUN_AFTER_FRAME_ERROR            , 56  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP7_RUN_AFTER_FRAME_ERROR );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_PRS_DISABLE                      , 57  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP7_PRS_DISABLE );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_PRS_SPARE                        , 58  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP7_PRS_SPARE );
+REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_PRS_SPARE_LEN                    , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FP7_PRS_SPARE_LEN );
+
+REG64_FLD( PU_PB_IOE_FIR_ACTION0_REG_ACTION0                       , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( PU_PB_IOE_FIR_ACTION0_REG_ACTION0_LEN                   , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_PB_IOE_FIR_ACTION1_REG_ACTION1                       , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( PU_PB_IOE_FIR_ACTION1_REG_ACTION1_LEN                   , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR00_TRAINED                    , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR00_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR01_TRAINED                    , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR01_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR02_TRAINED                    , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR02_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR03_TRAINED                    , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR03_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR04_TRAINED                    , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR04_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR05_TRAINED                    , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR05_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV6                             , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV6       );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV7                             , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV7       );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB01_UE                         , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_UE   );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB01_CE                         , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_CE   );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB01_SUE                        , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_SUE  );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB23_UE                         , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_UE   );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB23_CE                         , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_CE   );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB23_SUE                        , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_SUE  );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB45_UE                         , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_UE   );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB45_CE                         , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_CE   );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB45_SUE                        , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_SUE  );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV17                            , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV17      );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV18                            , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV18      );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV19                            , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV19      );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER00_ATTN                    , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER00_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER01_ATTN                    , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER01_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER02_ATTN                    , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER02_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER03_ATTN                    , 23  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER03_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER04_ATTN                    , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER04_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER05_ATTN                    , 25  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER05_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV26                            , 26  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV26      );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV27                            , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV27      );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER00_ATTN                    , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER00_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER01_ATTN                    , 29  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER01_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER02_ATTN                    , 30  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER02_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER03_ATTN                    , 31  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER03_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER04_ATTN                    , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER04_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER05_ATTN                    , 33  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER05_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV34                            , 34  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV34      );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV35                            , 35  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV35      );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB00_SPATTN                      , 36  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB00_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB01_SPATTN                      , 37  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB01_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB10_SPATTN                      , 38  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB10_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB11_SPATTN                      , 39  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB11_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB20_SPATTN                      , 40  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB20_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB21_SPATTN                      , 41  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB21_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB30_SPATTN                      , 42  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB30_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB31_SPATTN                      , 43  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB31_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB40_SPATTN                      , 44  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB40_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB41_SPATTN                      , 45  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB41_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB50_SPATTN                      , 46  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB50_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB51_SPATTN                      , 47  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB51_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB01_ERR                        , 52  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB23_ERR                        , 53  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB45_ERR                        , 54  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DIB01_ERR                        , 56  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIB01_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DIB23_ERR                        , 57  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIB23_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DIB45_ERR                        , 58  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIB45_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_SCOM_ERR_DUP                     , 62  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+REG64_FLD( PU_PB_IOE_FIR_MASK_REG_SCOM_ERR                         , 63  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+
+REG64_FLD( PU_PB_IOE_FIR_REG_FMR00_TRAINED                         , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR00_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_REG_FMR01_TRAINED                         , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR01_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_REG_FMR02_TRAINED                         , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR02_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_REG_FMR03_TRAINED                         , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR03_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_REG_FMR04_TRAINED                         , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR04_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_REG_FMR05_TRAINED                         , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR05_TRAINED );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV6                                  , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV6       );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV7                                  , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV7       );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB01_UE                              , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_UE   );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB01_CE                              , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_CE   );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB01_SUE                             , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_SUE  );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB23_UE                              , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_UE   );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB23_CE                              , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_CE   );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB23_SUE                             , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_SUE  );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB45_UE                              , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_UE   );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB45_CE                              , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_CE   );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB45_SUE                             , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_SUE  );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV17                                 , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV17      );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV18                                 , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV18      );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV19                                 , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV19      );
+REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER00_ATTN                         , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER00_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER01_ATTN                         , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER01_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER02_ATTN                         , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER02_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER03_ATTN                         , 23  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER03_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER04_ATTN                         , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER04_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER05_ATTN                         , 25  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER05_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV26                                 , 26  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV26      );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV27                                 , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV27      );
+REG64_FLD( PU_PB_IOE_FIR_REG_PARSER00_ATTN                         , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER00_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_PARSER01_ATTN                         , 29  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER01_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_PARSER02_ATTN                         , 30  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER02_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_PARSER03_ATTN                         , 31  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER03_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_PARSER04_ATTN                         , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER04_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_PARSER05_ATTN                         , 33  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER05_ATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV34                                 , 34  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV34      );
+REG64_FLD( PU_PB_IOE_FIR_REG_RSV35                                 , 35  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RSV35      );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB00_SPATTN                           , 36  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB00_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB01_SPATTN                           , 37  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB01_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB10_SPATTN                           , 38  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB10_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB11_SPATTN                           , 39  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB11_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB20_SPATTN                           , 40  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB20_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB21_SPATTN                           , 41  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB21_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB30_SPATTN                           , 42  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB30_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB31_SPATTN                           , 43  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB31_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB40_SPATTN                           , 44  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB40_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB41_SPATTN                           , 45  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB41_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB50_SPATTN                           , 46  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB50_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_MB51_SPATTN                           , 47  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB51_SPATTN );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB01_ERR                             , 52  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB23_ERR                             , 53  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_REG_DOB45_ERR                             , 54  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_REG_DIB01_ERR                             , 56  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIB01_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_REG_DIB23_ERR                             , 57  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIB23_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_REG_DIB45_ERR                             , 58  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIB45_ERR  );
+REG64_FLD( PU_PB_IOE_FIR_REG_SCOM_ERR_DUP                          , 62  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+REG64_FLD( PU_PB_IOE_FIR_REG_SCOM_ERR                              , 63  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+
+REG64_FLD( PU_IOE_PB_IOO_FIR_ACTION0_REG_ACTION0                   , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( PU_IOE_PB_IOO_FIR_ACTION0_REG_ACTION0_LEN               , 64  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_IOE_PB_IOO_FIR_ACTION1_REG_ACTION1                   , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( PU_IOE_PB_IOO_FIR_ACTION1_REG_ACTION1_LEN               , 64  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR00_TRAINED                , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR00_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR01_TRAINED                , 1   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR01_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR02_TRAINED                , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR02_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR03_TRAINED                , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR03_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR04_TRAINED                , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR04_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR05_TRAINED                , 5   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR05_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR06_TRAINED                , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR06_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR07_TRAINED                , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR07_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_UE                     , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_UE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_CE                     , 9   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_CE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_SUE                    , 10  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_SUE  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_UE                     , 11  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_UE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_CE                     , 12  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_CE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_SUE                    , 13  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_SUE  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_UE                     , 14  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_UE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_CE                     , 15  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_CE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_SUE                    , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_SUE  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_UE                     , 17  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB67_UE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_CE                     , 18  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB67_CE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_SUE                    , 19  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB67_SUE  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER00_ATTN                , 20  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER00_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER01_ATTN                , 21  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER01_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER02_ATTN                , 22  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER02_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER03_ATTN                , 23  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER03_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER04_ATTN                , 24  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER04_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER05_ATTN                , 25  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER05_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER06_ATTN                , 26  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER06_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER07_ATTN                , 27  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER07_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER00_ATTN                , 28  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER00_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER01_ATTN                , 29  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER01_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER02_ATTN                , 30  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER02_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER03_ATTN                , 31  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER03_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER04_ATTN                , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER04_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER05_ATTN                , 33  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER05_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER06_ATTN                , 34  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER06_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER07_ATTN                , 35  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER07_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB00_SPATTN                  , 36  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB00_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB01_SPATTN                  , 37  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB01_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB10_SPATTN                  , 38  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB10_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB11_SPATTN                  , 39  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB11_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB20_SPATTN                  , 40  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB20_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB21_SPATTN                  , 41  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB21_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB30_SPATTN                  , 42  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB30_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB31_SPATTN                  , 43  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB31_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB40_SPATTN                  , 44  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB40_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB41_SPATTN                  , 45  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB41_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB50_SPATTN                  , 46  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB50_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB51_SPATTN                  , 47  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB51_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB60_SPATTN                  , 48  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB60_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB61_SPATTN                  , 49  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB61_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB70_SPATTN                  , 50  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB70_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB71_SPATTN                  , 51  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB71_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_ERR                    , 52  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_ERR                    , 53  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_ERR                    , 54  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_ERR                    , 55  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB67_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DIB01_ERR                    , 56  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIB01_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DIB23_ERR                    , 57  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIB23_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DIB45_ERR                    , 58  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIB45_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DIB67_ERR                    , 59  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIB67_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_SCOM_ERR_DUP                 , 62  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_SCOM_ERR                     , 63  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR00_TRAINED                     , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR00_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR01_TRAINED                     , 1   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR01_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR02_TRAINED                     , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR02_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR03_TRAINED                     , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR03_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR04_TRAINED                     , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR04_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR05_TRAINED                     , 5   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR05_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR06_TRAINED                     , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR06_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR07_TRAINED                     , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FMR07_TRAINED );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB01_UE                          , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_UE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB01_CE                          , 9   , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_CE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB01_SUE                         , 10  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_SUE  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB23_UE                          , 11  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_UE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB23_CE                          , 12  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_CE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB23_SUE                         , 13  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_SUE  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB45_UE                          , 14  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_UE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB45_CE                          , 15  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_CE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB45_SUE                         , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_SUE  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB67_UE                          , 17  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB67_UE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB67_CE                          , 18  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB67_CE   );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB67_SUE                         , 19  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB67_SUE  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER00_ATTN                     , 20  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER00_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER01_ATTN                     , 21  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER01_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER02_ATTN                     , 22  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER02_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER03_ATTN                     , 23  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER03_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER04_ATTN                     , 24  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER04_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER05_ATTN                     , 25  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER05_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER06_ATTN                     , 26  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER06_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER07_ATTN                     , 27  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FRAMER07_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER00_ATTN                     , 28  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER00_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER01_ATTN                     , 29  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER01_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER02_ATTN                     , 30  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER02_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER03_ATTN                     , 31  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER03_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER04_ATTN                     , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER04_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER05_ATTN                     , 33  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER05_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER06_ATTN                     , 34  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER06_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER07_ATTN                     , 35  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARSER07_ATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB00_SPATTN                       , 36  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB00_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB01_SPATTN                       , 37  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB01_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB10_SPATTN                       , 38  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB10_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB11_SPATTN                       , 39  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB11_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB20_SPATTN                       , 40  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB20_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB21_SPATTN                       , 41  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB21_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB30_SPATTN                       , 42  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB30_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB31_SPATTN                       , 43  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB31_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB40_SPATTN                       , 44  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB40_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB41_SPATTN                       , 45  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB41_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB50_SPATTN                       , 46  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB50_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB51_SPATTN                       , 47  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB51_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB60_SPATTN                       , 48  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB60_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB61_SPATTN                       , 49  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB61_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB70_SPATTN                       , 50  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB70_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB71_SPATTN                       , 51  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_MB71_SPATTN );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB01_ERR                         , 52  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB01_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB23_ERR                         , 53  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB23_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB45_ERR                         , 54  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB45_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB67_ERR                         , 55  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DOB67_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DIB01_ERR                         , 56  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIB01_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DIB23_ERR                         , 57  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIB23_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DIB45_ERR                         , 58  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIB45_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DIB67_ERR                         , 59  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIB67_ERR  );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_SCOM_ERR_DUP                      , 62  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+REG64_FLD( PU_IOE_PB_IOO_FIR_REG_SCOM_ERR                          , 63  , SH_UNT_PU_IOE   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+
+REG64_FLD( PU_PB_MISC_CFG_IOE01_IS_LOGICAL_PAIR                    , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IOE01_IS_LOGICAL_PAIR );
+REG64_FLD( PU_PB_MISC_CFG_IOE23_IS_LOGICAL_PAIR                    , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IOE23_IS_LOGICAL_PAIR );
+REG64_FLD( PU_PB_MISC_CFG_IOE45_IS_LOGICAL_PAIR                    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IOE45_IS_LOGICAL_PAIR );
+REG64_FLD( PU_PB_MISC_CFG_SPARE3                                   , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE3     );
+REG64_FLD( PU_PB_MISC_CFG_SCOM_LINK01_RESET_KEEPER                 , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_LINK01_RESET_KEEPER );
+REG64_FLD( PU_PB_MISC_CFG_SCOM_LINK23_RESET_KEEPER                 , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_LINK23_RESET_KEEPER );
+REG64_FLD( PU_PB_MISC_CFG_SCOM_LINK45_RESET_KEEPER                 , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_LINK45_RESET_KEEPER );
+REG64_FLD( PU_PB_MISC_CFG_SPARE7                                   , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE7     );
+REG64_FLD( PU_PB_MISC_CFG_SPARE8                                   , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE8     );
+REG64_FLD( PU_PB_MISC_CFG_SPARE9                                   , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE9     );
+REG64_FLD( PU_PB_MISC_CFG_SPARE10                                  , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE10    );
+REG64_FLD( PU_PB_MISC_CFG_SPARE11                                  , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE11    );
+REG64_FLD( PU_PB_MISC_CFG_LINK_AVP_MODE                            , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LINK_AVP_MODE );
+REG64_FLD( PU_PB_MISC_CFG_SPARE13                                  , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE13    );
+REG64_FLD( PU_PB_MISC_CFG_SPARE14                                  , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE14    );
+REG64_FLD( PU_PB_MISC_CFG_SPARE15                                  , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE15    );
+
+REG64_FLD( PU_IOE_PB_MISC_CFG_IOO01_IS_LOGICAL_PAIR                , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_IOO01_IS_LOGICAL_PAIR );
+REG64_FLD( PU_IOE_PB_MISC_CFG_IOO23_IS_LOGICAL_PAIR                , 1   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_IOO23_IS_LOGICAL_PAIR );
+REG64_FLD( PU_IOE_PB_MISC_CFG_IOO45_IS_LOGICAL_PAIR                , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_IOO45_IS_LOGICAL_PAIR );
+REG64_FLD( PU_IOE_PB_MISC_CFG_IOO67_IS_LOGICAL_PAIR                , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_IOO67_IS_LOGICAL_PAIR );
+REG64_FLD( PU_IOE_PB_MISC_CFG_SCOM_LINK01_RESET_KEEPER             , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_LINK01_RESET_KEEPER );
+REG64_FLD( PU_IOE_PB_MISC_CFG_SCOM_LINK23_RESET_KEEPER             , 5   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_LINK23_RESET_KEEPER );
+REG64_FLD( PU_IOE_PB_MISC_CFG_SCOM_LINK45_RESET_KEEPER             , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_LINK45_RESET_KEEPER );
+REG64_FLD( PU_IOE_PB_MISC_CFG_SCOM_LINK67_RESET_KEEPER             , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_LINK67_RESET_KEEPER );
+REG64_FLD( PU_IOE_PB_MISC_CFG_LINKS01_TOD_ENABLE                   , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_LINKS01_TOD_ENABLE );
+REG64_FLD( PU_IOE_PB_MISC_CFG_LINKS23_TOD_ENABLE                   , 9   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_LINKS23_TOD_ENABLE );
+REG64_FLD( PU_IOE_PB_MISC_CFG_LINKS45_TOD_ENABLE                   , 10  , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_LINKS45_TOD_ENABLE );
+REG64_FLD( PU_IOE_PB_MISC_CFG_LINKS67_TOD_ENABLE                   , 11  , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_LINKS67_TOD_ENABLE );
+REG64_FLD( PU_IOE_PB_MISC_CFG_LINK_AVP_MODE                        , 12  , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_LINK_AVP_MODE );
+REG64_FLD( PU_IOE_PB_MISC_CFG_SEL_03_NPU_NOT                       , 13  , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_SEL_03_NPU_NOT );
+REG64_FLD( PU_IOE_PB_MISC_CFG_SEL_04_NPU_NOT                       , 14  , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_SEL_04_NPU_NOT );
+REG64_FLD( PU_IOE_PB_MISC_CFG_SEL_05_NPU_NOT                       , 15  , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_SEL_05_NPU_NOT );
+REG64_FLD( PU_IOE_PB_MISC_CFG_SPARE                                , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_IOE_PB_MISC_CFG_SPARE_LEN                            , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK01_CAPP_MODE        , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK01_CAPP_MODE );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK01_HRB_INIT_STATE   , 1   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK01_HRB_INIT_STATE );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_SPARE             , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK0_SPARE );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_SPARE_LEN         , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK0_SPARE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT     , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK0_DOB_VC0_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT_LEN , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK0_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT     , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK0_DOB_VC1_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT_LEN , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK0_DOB_VC1_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT     , 24  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK01_DIB_VC_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT_LEN , 5   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK01_DIB_VC_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_DIB01_SPARE             , 29  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIB01_SPARE );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_DIB01_SPARE_LEN         , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIB01_SPARE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_SPARE             , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK1_SPARE );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_SPARE_LEN         , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK1_SPARE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT     , 40  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK1_DOB_VC0_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT_LEN , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK1_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT     , 48  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK1_DOB_VC1_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT_LEN , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK1_DOB_VC1_LIMIT_LEN );
+
+REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT         , 1   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK2_DOB_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT_LEN     , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK2_DOB_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT     , 9   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK2_DOB_VC0_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT_LEN , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK2_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT     , 17  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK2_DOB_VC1_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT_LEN , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK2_DOB_VC1_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT     , 24  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK23_DIB_VC_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT_LEN , 5   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK23_DIB_VC_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT         , 33  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK3_DOB_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT_LEN     , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK3_DOB_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT     , 41  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK3_DOB_VC0_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT_LEN , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK3_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT     , 49  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK3_DOB_VC1_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT_LEN , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK3_DOB_VC1_LIMIT_LEN );
+
+REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT         , 1   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK4_DOB_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT_LEN     , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK4_DOB_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT     , 9   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK4_DOB_VC0_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT_LEN , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK4_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT     , 17  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK4_DOB_VC1_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT_LEN , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK4_DOB_VC1_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT     , 24  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK45_DIB_VC_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT_LEN , 5   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK45_DIB_VC_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT         , 33  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK5_DOB_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT_LEN     , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK5_DOB_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT     , 41  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK5_DOB_VC0_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT_LEN , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK5_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT     , 49  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK5_DOB_VC1_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT_LEN , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK5_DOB_VC1_LIMIT_LEN );
+
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK67_CAPP_MODE        , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK67_CAPP_MODE );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK67_HRB_INIT_STATE   , 1   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK67_HRB_INIT_STATE );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_SPARE             , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK6_SPARE );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_SPARE_LEN         , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK6_SPARE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC0_LIMIT     , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK6_DOB_VC0_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC0_LIMIT_LEN , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK6_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC1_LIMIT     , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK6_DOB_VC1_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC1_LIMIT_LEN , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK6_DOB_VC1_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK67_DIB_VC_LIMIT     , 24  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK67_DIB_VC_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK67_DIB_VC_LIMIT_LEN , 5   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK67_DIB_VC_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_DIB67_SPARE             , 29  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIB67_SPARE );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_DIB67_SPARE_LEN         , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_DIB67_SPARE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_SPARE             , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK7_SPARE );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_SPARE_LEN         , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK7_SPARE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC0_LIMIT     , 40  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK7_DOB_VC0_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC0_LIMIT_LEN , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK7_DOB_VC0_LIMIT_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT     , 48  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK7_DOB_VC1_LIMIT );
+REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT_LEN , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK7_DOB_VC1_LIMIT_LEN );
+
+REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER0                           , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER0_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER1                           , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER1_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER2                           , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER2_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER3                           , 48  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER3_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER0                           , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER0_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER1                           , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER1_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER2                           , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER2_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER3                           , 48  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER3_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER0                           , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER0_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER1                           , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER1_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER2                           , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER2_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER3                           , 48  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER3_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER0                           , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER0_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER1                           , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER1_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER2                           , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER2_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER3                           , 48  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER3_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER0                           , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER0_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER1                           , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER1_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER2                           , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER2_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER3                           , 48  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER3_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER0                           , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER0_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER1                           , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER1_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER2                           , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER2_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER3                           , 48  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER3_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER0                           , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER0_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER1                           , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER1_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER2                           , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER2_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER3                           , 48  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER3_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER0                           , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER0_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER0_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER1                           , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER1_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER1_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER2                           , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER2_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER2_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER3                           , 48  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3   );
+REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER3_LEN                       , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COUNTER3_LEN );
+
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0_ENABLE                 , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0_ENABLE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU1_ENABLE                 , 1   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU1_ENABLE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2_ENABLE                 , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2_ENABLE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU3_ENABLE                 , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU3_ENABLE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU4_ENABLE                 , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU4_ENABLE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU5_ENABLE                 , 5   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU5_ENABLE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU6_ENABLE                 , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU6_ENABLE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU7_ENABLE                 , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU7_ENABLE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMULET_FREEZE_MODE          , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMULET_FREEZE_MODE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_COMMON_FREEZE_MODE          , 9   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_COMMON_FREEZE_MODE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMULET_RESET_MODE           , 10  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMULET_RESET_MODE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT0_SEL                  , 11  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT0_SEL );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT1_SEL                  , 12  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT1_SEL );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT1_SEL_LEN              , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT1_SEL_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT2_SEL                  , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT2_SEL );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT2_SEL_LEN              , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT2_SEL_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT3_SEL                  , 20  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT3_SEL );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT3_SEL_LEN              , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT3_SEL_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0_SIZE                   , 24  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0_SIZE  );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0_SIZE_LEN               , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0_SIZE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU1_SIZE                   , 26  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU1_SIZE  );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU1_SIZE_LEN               , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU1_SIZE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2_SIZE                   , 28  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2_SIZE  );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2_SIZE_LEN               , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2_SIZE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU3_SIZE                   , 30  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU3_SIZE  );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU3_SIZE_LEN               , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU3_SIZE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU01_LINK_SELECT           , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU01_LINK_SELECT );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU23_LINK_SELECT           , 33  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU23_LINK_SELECT );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU45_LINK_SELECT           , 34  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU45_LINK_SELECT );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU67_LINK_SELECT           , 35  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU67_LINK_SELECT );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT0_MODE         , 36  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT0_MODE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT0_MODE_LEN     , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT0_MODE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT1_MODE         , 38  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT1_MODE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT1_MODE_LEN     , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT1_MODE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT2_MODE         , 40  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT2_MODE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT2_MODE_LEN     , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT2_MODE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT3_MODE         , 42  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT3_MODE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT3_MODE_LEN     , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU0145_EVENT3_MODE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT0_MODE         , 44  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT0_MODE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT0_MODE_LEN     , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT0_MODE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT1_MODE         , 46  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT1_MODE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT1_MODE_LEN     , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT1_MODE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT2_MODE         , 48  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT2_MODE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT2_MODE_LEN     , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT2_MODE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT3_MODE         , 50  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT3_MODE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT3_MODE_LEN     , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMU2367_EVENT3_MODE_LEN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_ENABLE_GLOBAL_RUN           , 52  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_GLOBAL_RUN );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_GLOBAL_RUN_MODE             , 53  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_GLOBAL_RUN_MODE );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_SPARE                       , 54  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_SPARE_LEN                   , 10  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_SET                    , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_SET        );
+REG64_FLD( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_SET_LEN                , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_SET_LEN    );
+REG64_FLD( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_STAT                   , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_STAT       );
+REG64_FLD( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_STAT_LEN               , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM     ,
+           SH_FLD_STAT_LEN   );
+
+REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_ENABLE                       , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HI_ENABLE  );
+REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_FIXED_WINDOW_MODE            , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HI_FIXED_WINDOW_MODE );
+REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_PRESCALE_MODE                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HI_PRESCALE_MODE );
+REG64_FLD( PU_PB_PERFTRACE_CFG_REG_PTSPARE6                        , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PTSPARE6   );
+REG64_FLD( PU_PB_PERFTRACE_CFG_REG_LO_ENABLE                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LO_ENABLE  );
+REG64_FLD( PU_PB_PERFTRACE_CFG_REG_LO_FIXED_WINDOW_MODE            , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LO_FIXED_WINDOW_MODE );
+REG64_FLD( PU_PB_PERFTRACE_CFG_REG_LO_PRESCALE_MODE                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LO_PRESCALE_MODE );
+REG64_FLD( PU_PB_PERFTRACE_CFG_REG_PTSPARE7                        , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PTSPARE7   );
+REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_SELECT                       , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HI_SELECT  );
+REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_SELECT_LEN                   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HI_SELECT_LEN );
+REG64_FLD( PU_PB_PERFTRACE_CFG_REG_LO_SELECT                       , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LO_SELECT  );
+REG64_FLD( PU_PB_PERFTRACE_CFG_REG_LO_SELECT_LEN                   , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LO_SELECT_LEN );
+
+REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_HI_ENABLE                   , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_HI_ENABLE  );
+REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_HI_FIXED_WINDOW_MODE        , 1   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_HI_FIXED_WINDOW_MODE );
+REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_HI_PRESCALE_MODE            , 2   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_HI_PRESCALE_MODE );
+REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_PTSPARE6                    , 3   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PTSPARE6   );
+REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_ENABLE                   , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LO_ENABLE  );
+REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_FIXED_WINDOW_MODE        , 5   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LO_FIXED_WINDOW_MODE );
+REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_PRESCALE_MODE            , 6   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LO_PRESCALE_MODE );
+REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_PTSPARE7                    , 7   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PTSPARE7   );
+REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_HI_SELECT                   , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_HI_SELECT  );
+REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_HI_SELECT_LEN               , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_HI_SELECT_LEN );
+REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_SELECT                   , 12  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LO_SELECT  );
+REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_SELECT_LEN               , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LO_SELECT_LEN );
+
+REG64_FLD( PU_PB_PPE_LFIR_INTERNAL_ERROR                           , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERNAL_ERROR );
+REG64_FLD( PU_PB_PPE_LFIR_EXTERNAL_ERROR                           , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_EXTERNAL_ERROR );
+REG64_FLD( PU_PB_PPE_LFIR_PROGRESS_ERROR                           , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROGRESS_ERROR );
+REG64_FLD( PU_PB_PPE_LFIR_BREAKPOINT_ERROR                         , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BREAKPOINT_ERROR );
+REG64_FLD( PU_PB_PPE_LFIR_WATCHDOG                                 , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WATCHDOG   );
+REG64_FLD( PU_PB_PPE_LFIR_HALTED                                   , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_HALTED     );
+REG64_FLD( PU_PB_PPE_LFIR_DEBUG_TRIGGER                            , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( PU_PB_PPE_LFIR_SRAM_UE                                  , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_UE    );
+REG64_FLD( PU_PB_PPE_LFIR_SRAM_CE                                  , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_CE    );
+REG64_FLD( PU_PB_PPE_LFIR_SRAM_SCRUB_ERR                           , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SCRUB_ERR );
+REG64_FLD( PU_PB_PPE_LFIR_BCE_ERROR                                , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCE_ERROR  );
+REG64_FLD( PU_PB_PPE_LFIR_SPARE11                                  , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE11    );
+REG64_FLD( PU_PB_PPE_LFIR_FIR_PARITY_ERR_DUP                       , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_PARITY_ERR_DUP );
+REG64_FLD( PU_PB_PPE_LFIR_FIR_PARITY_ERR                           , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_PARITY_ERR );
+
+REG64_FLD( PU_PB_PPE_LFIRACT0_FIR_ACTION0                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION0 );
+REG64_FLD( PU_PB_PPE_LFIRACT0_FIR_ACTION0_LEN                      , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION0_LEN );
+
+REG64_FLD( PU_PB_PPE_LFIRACT1_FIR_ACTION1                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION1 );
+REG64_FLD( PU_PB_PPE_LFIRACT1_FIR_ACTION1_LEN                      , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION1_LEN );
+
+REG64_FLD( PU_PB_PPE_LFIRMASK_FIR_MASK                             , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_MASK   );
+REG64_FLD( PU_PB_PPE_LFIRMASK_FIR_MASK_LEN                         , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_MASK_LEN );
+
+REG64_FLD( PU_PB_PSAVE_CFG_ENABLE                                  , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_PB_PSAVE_CFG_X0_ACT                                  , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_X0_ACT     );
+REG64_FLD( PU_PB_PSAVE_CFG_X1_ACT                                  , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_X1_ACT     );
+REG64_FLD( PU_PB_PSAVE_CFG_X2_ACT                                  , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_X2_ACT     );
+REG64_FLD( PU_PB_PSAVE_CFG_PS_SPARE1                               , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PS_SPARE1  );
+REG64_FLD( PU_PB_PSAVE_CFG_WSIZE                                   , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WSIZE      );
+REG64_FLD( PU_PB_PSAVE_CFG_WSIZE_LEN                               , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WSIZE_LEN  );
+REG64_FLD( PU_PB_PSAVE_CFG_LUC                                     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LUC        );
+REG64_FLD( PU_PB_PSAVE_CFG_LUC_LEN                                 , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LUC_LEN    );
+REG64_FLD( PU_PB_PSAVE_CFG_HUC                                     , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HUC        );
+REG64_FLD( PU_PB_PSAVE_CFG_HUC_LEN                                 , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HUC_LEN    );
+REG64_FLD( PU_PB_PSAVE_CFG_LUT                                     , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LUT        );
+REG64_FLD( PU_PB_PSAVE_CFG_LUT_LEN                                 , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LUT_LEN    );
+REG64_FLD( PU_PB_PSAVE_CFG_HUT                                     , 35  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HUT        );
+REG64_FLD( PU_PB_PSAVE_CFG_HUT_LEN                                 , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HUT_LEN    );
+
+REG64_FLD( PU_PB_PSAVE_MON_CFG_X0_LO                               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_LO      );
+REG64_FLD( PU_PB_PSAVE_MON_CFG_X0_LO_LEN                           , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_LO_LEN  );
+REG64_FLD( PU_PB_PSAVE_MON_CFG_X0_HI                               , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_HI      );
+REG64_FLD( PU_PB_PSAVE_MON_CFG_X0_HI_LEN                           , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_HI_LEN  );
+REG64_FLD( PU_PB_PSAVE_MON_CFG_X1_LO                               , 19  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_LO      );
+REG64_FLD( PU_PB_PSAVE_MON_CFG_X1_LO_LEN                           , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_LO_LEN  );
+REG64_FLD( PU_PB_PSAVE_MON_CFG_X1_HI                               , 27  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_HI      );
+REG64_FLD( PU_PB_PSAVE_MON_CFG_X1_HI_LEN                           , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_HI_LEN  );
+REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_LO                               , 35  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_LO      );
+REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_LO_LEN                           , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_LO_LEN  );
+REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_HI                               , 43  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_HI      );
+REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_HI_LEN                           , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_HI_LEN  );
+
+REG64_FLD( PU_PB_TRACE_CFG_LINK00_HI                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK00_HI  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK00_HI_LEN                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK00_HI_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK00_LO                               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK00_LO  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK00_LO_LEN                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK00_LO_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK01_HI                               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK01_HI  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK01_HI_LEN                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK01_HI_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK01_LO                               , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK01_LO  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK01_LO_LEN                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK01_LO_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK02_HI                               , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK02_HI  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK02_HI_LEN                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK02_HI_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK02_LO                               , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK02_LO  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK02_LO_LEN                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK02_LO_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK03_HI                               , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK03_HI  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK03_HI_LEN                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK03_HI_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK03_LO                               , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK03_LO  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK03_LO_LEN                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK03_LO_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK04_HI                               , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK04_HI  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK04_HI_LEN                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK04_HI_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK04_LO                               , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK04_LO  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK04_LO_LEN                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK04_LO_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK05_HI                               , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK05_HI  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK05_HI_LEN                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK05_HI_LEN );
+REG64_FLD( PU_PB_TRACE_CFG_LINK05_LO                               , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK05_LO  );
+REG64_FLD( PU_PB_TRACE_CFG_LINK05_LO_LEN                           , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK05_LO_LEN );
+
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK00_HI                           , 0   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK00_HI  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK00_HI_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK00_HI_LEN );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK00_LO                           , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK00_LO  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK00_LO_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK00_LO_LEN );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK01_HI                           , 8   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK01_HI  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK01_HI_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK01_HI_LEN );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK01_LO                           , 12  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK01_LO  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK01_LO_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK01_LO_LEN );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK02_HI                           , 16  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK02_HI  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK02_HI_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK02_HI_LEN );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK02_LO                           , 20  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK02_LO  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK02_LO_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK02_LO_LEN );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK03_HI                           , 24  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK03_HI  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK03_HI_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK03_HI_LEN );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK03_LO                           , 28  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK03_LO  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK03_LO_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK03_LO_LEN );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK04_HI                           , 32  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK04_HI  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK04_HI_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK04_HI_LEN );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK04_LO                           , 36  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK04_LO  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK04_LO_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK04_LO_LEN );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK05_HI                           , 40  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK05_HI  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK05_HI_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK05_HI_LEN );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK05_LO                           , 44  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK05_LO  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK05_LO_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK05_LO_LEN );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK06_HI                           , 48  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK06_HI  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK06_HI_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK06_HI_LEN );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK06_LO                           , 52  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK06_LO  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK06_LO_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK06_LO_LEN );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK07_HI                           , 56  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK07_HI  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK07_HI_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK07_HI_LEN );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK07_LO                           , 60  , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK07_LO  );
+REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK07_LO_LEN                       , 4   , SH_UNT_PU_IOE   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK07_LO_LEN );
+
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG_ACTION0          , 0   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG_ACTION0_LEN      , 34  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG_ACTION1          , 0   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG_ACTION1_LEN      , 34  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_HW1_ERROR , 0   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ00_PBH_HW1_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_HW2_ERROR , 1   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ00_PBH_HW2_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_PROTOCOL_ERROR , 2   , SH_UNT_PU_PB_WEST_SM0,
+           SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_PROTOCOL_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_OVERFLOW_ERROR , 3   , SH_UNT_PU_PB_WEST_SM0,
+           SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_OVERFLOW_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_HW1_ERROR , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ01_PBH_HW1_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_HW2_ERROR , 5   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ01_PBH_HW2_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_PROTOCOL_ERROR , 6   , SH_UNT_PU_PB_WEST_SM0,
+           SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_PROTOCOL_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_OVERFLOW_ERROR , 7   , SH_UNT_PU_PB_WEST_SM0,
+           SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_OVERFLOW_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_HW1_ERROR , 8   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ02_PBH_HW1_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_HW2_ERROR , 9   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ02_PBH_HW2_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_PROTOCOL_ERROR , 10  , SH_UNT_PU_PB_WEST_SM0,
+           SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_PROTOCOL_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_OVERFLOW_ERROR , 11  , SH_UNT_PU_PB_WEST_SM0,
+           SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_OVERFLOW_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_HW1_ERROR , 12  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ03_PBH_HW1_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_HW2_ERROR , 13  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ03_PBH_HW2_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_PROTOCOL_ERROR , 14  , SH_UNT_PU_PB_WEST_SM0,
+           SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_PROTOCOL_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_OVERFLOW_ERROR , 15  , SH_UNT_PU_PB_WEST_SM0,
+           SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_OVERFLOW_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_16            , 16  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_16   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_17            , 17  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_17   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_18            , 18  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_18   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_19            , 19  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_19   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_20            , 20  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_20   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_21            , 21  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_21   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_22            , 22  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_22   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_23            , 23  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_23   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_24            , 24  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_24   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_25            , 25  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_25   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_26            , 26  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_26   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_27            , 27  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_27   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_28            , 28  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_28   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_29            , 29  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_29   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_30            , 30  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_30   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_31            , 31  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_31   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SCOM_ERR            , 32  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SCOM_ERR_DUP        , 33  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_HW1_ERROR    , 0   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ00_PBH_HW1_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_HW2_ERROR    , 1   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ00_PBH_HW2_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_PROTOCOL_ERROR , 2   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ00_PBH_PROTOCOL_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_OVERFLOW_ERROR , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ00_PBH_OVERFLOW_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_HW1_ERROR    , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ01_PBH_HW1_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_HW2_ERROR    , 5   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ01_PBH_HW2_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_PROTOCOL_ERROR , 6   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ01_PBH_PROTOCOL_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_OVERFLOW_ERROR , 7   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ01_PBH_OVERFLOW_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_HW1_ERROR    , 8   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ02_PBH_HW1_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_HW2_ERROR    , 9   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ02_PBH_HW2_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_PROTOCOL_ERROR , 10  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ02_PBH_PROTOCOL_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_OVERFLOW_ERROR , 11  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ02_PBH_OVERFLOW_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_HW1_ERROR    , 12  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ03_PBH_HW1_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_HW2_ERROR    , 13  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ03_PBH_HW2_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_PROTOCOL_ERROR , 14  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ03_PBH_PROTOCOL_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_OVERFLOW_ERROR , 15  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_PBIEQ03_PBH_OVERFLOW_ERROR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_16                 , 16  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_16   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_17                 , 17  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_17   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_18                 , 18  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_18   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_19                 , 19  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_19   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_20                 , 20  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_20   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_21                 , 21  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_21   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_22                 , 22  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_22   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_23                 , 23  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_23   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_24                 , 24  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_24   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_25                 , 25  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_25   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_26                 , 26  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_26   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_27                 , 27  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_27   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_28                 , 28  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_28   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_29                 , 29  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_29   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_30                 , 30  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_30   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_31                 , 31  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_31   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR                 , 32  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR_DUP             , 33  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_EN     , 0   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_EN     , 1   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X2_EN     , 2   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X3_EN     , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X4_EN     , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X5_EN     , 5   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X6_EN     , 6   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX0_ADDR_DIS , 8   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX0_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX1_ADDR_DIS , 9   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX1_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX2_ADDR_DIS , 10  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX2_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX3_ADDR_DIS , 11  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX3_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX4_ADDR_DIS , 12  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX4_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX5_ADDR_DIS , 13  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX5_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX6_ADDR_DIS , 14  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX6_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID , 16  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_CHIPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID_LEN , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_CHIPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID , 19  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_CHIPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID_LEN , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_CHIPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID , 22  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_CHIPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID_LEN , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_CHIPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID , 25  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_CHIPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID_LEN , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_CHIPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID , 28  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_CHIPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID_LEN , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_CHIPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID , 31  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_CHIPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID_LEN , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_CHIPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID , 34  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_CHIPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID_LEN , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_CHIPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_AGGREGATE    , 37  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_AGGREGATE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_FP_DISABLED  , 48  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_FP_DISABLED );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_INDIRECT_EN  , 49  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_INDIRECT_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_GATHER_ENABLE , 50  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_GATHER_ENABLE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_CMD_RATE     , 56  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_CMD_RATE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_CMD_RATE_LEN , 8   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_CMD_RATE_LEN );
+
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X0_EN     , 0   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X1_EN     , 1   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X2_EN     , 2   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X3_EN     , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X4_EN     , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X5_EN     , 5   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X6_EN     , 6   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX0_ADDR_DIS , 8   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX0_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX1_ADDR_DIS , 9   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX1_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX2_ADDR_DIS , 10  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX2_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX3_ADDR_DIS , 11  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX3_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX4_ADDR_DIS , 12  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX4_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX5_ADDR_DIS , 13  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX5_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX6_ADDR_DIS , 14  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NX6_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID , 16  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_CHIPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID_LEN , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X0_CHIPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID , 19  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_CHIPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID_LEN , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X1_CHIPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID , 22  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_CHIPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID_LEN , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X2_CHIPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID , 25  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_CHIPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID_LEN , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X3_CHIPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID , 28  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_CHIPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID_LEN , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X4_CHIPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID , 31  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_CHIPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID_LEN , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X5_CHIPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID , 34  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_CHIPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID_LEN , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_X6_CHIPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_AGGREGATE    , 37  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_AGGREGATE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_FP_DISABLED  , 48  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_FP_DISABLED );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_INDIRECT_EN  , 49  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_INDIRECT_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_GATHER_ENABLE , 50  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_GATHER_ENABLE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_CMD_RATE     , 56  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_CMD_RATE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_CMD_RATE_LEN , 8   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_X_CMD_RATE_LEN );
+
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_MASTER_CHIP     , 0   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_MASTER_CHIP );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_TM_MASTER       , 1   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TM_MASTER );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_CHG_RATE_GP_MASTER , 2   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CHG_RATE_GP_MASTER );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_CHG_RATE_SP_MASTER , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CHG_RATE_SP_MASTER );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A0_EN      , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A1_EN      , 5   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A2_EN      , 6   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A3_EN      , 7   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA0_ADDR_DIS , 8   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA0_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA1_ADDR_DIS , 9   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA1_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA2_ADDR_DIS , 10  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA2_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA3_ADDR_DIS , 11  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA3_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A0_GROUPID , 12  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_GROUPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A0_GROUPID_LEN , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_GROUPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A1_GROUPID , 16  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_GROUPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A1_GROUPID_LEN , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_GROUPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A2_GROUPID , 20  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_GROUPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A2_GROUPID_LEN , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_GROUPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A3_GROUPID , 24  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_GROUPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A3_GROUPID_LEN , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_GROUPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_AGGREGATE     , 28  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_AGGREGATE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_HOP             , 29  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_HOP    );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_SMP_OPTICS      , 30  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SMP_OPTICS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_CAPI            , 31  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CAPI   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT0            , 32  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT0   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT0_LEN        , 2   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT0_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT1            , 34  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT1   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT1_LEN        , 2   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT1_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT2            , 36  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT2   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT2_LEN        , 2   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT2_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT3            , 38  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT3   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT3_LEN        , 2   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT3_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID , 40  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_XLATE_ADDR_TO_ID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN , 7   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_GATHER_ENABLE , 50  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_GATHER_ENABLE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_PHYP_IS_GROUP   , 52  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PHYP_IS_GROUP );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_ADDR_BAR        , 53  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_ADDR_BAR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_PUMP            , 54  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PUMP   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_DCACHE_CAPP     , 55  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_DCACHE_CAPP );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_CMD_RATE      , 56  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_CMD_RATE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_CMD_RATE_LEN  , 8   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_CMD_RATE_LEN );
+
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_MASTER_CHIP     , 0   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_MASTER_CHIP );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_TM_MASTER       , 1   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_TM_MASTER );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_CHG_RATE_GP_MASTER , 2   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CHG_RATE_GP_MASTER );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_CHG_RATE_SP_MASTER , 3   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CHG_RATE_SP_MASTER );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A0_EN      , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A1_EN      , 5   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A2_EN      , 6   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A3_EN      , 7   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_EN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA0_ADDR_DIS , 8   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA0_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA1_ADDR_DIS , 9   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA1_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA2_ADDR_DIS , 10  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA2_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA3_ADDR_DIS , 11  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_NA3_ADDR_DIS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID , 12  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_GROUPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID_LEN , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A0_GROUPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID , 16  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_GROUPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID_LEN , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A1_GROUPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID , 20  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_GROUPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID_LEN , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A2_GROUPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID , 24  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_GROUPID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID_LEN , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINK_A3_GROUPID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_AGGREGATE     , 28  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_AGGREGATE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_HOP             , 29  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_HOP    );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_SMP_OPTICS      , 30  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SMP_OPTICS );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_CAPI            , 31  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CAPI   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT0            , 32  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT0   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT0_LEN        , 2   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT0_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT1            , 34  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT1   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT1_LEN        , 2   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT1_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT2            , 36  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT2   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT2_LEN        , 2   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT2_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT3            , 38  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT3   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT3_LEN        , 2   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_OPT3_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID , 40  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_XLATE_ADDR_TO_ID );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN , 7   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_GATHER_ENABLE , 50  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_GATHER_ENABLE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_PHYP_IS_GROUP   , 52  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PHYP_IS_GROUP );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_ADDR_BAR        , 53  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_ADDR_BAR );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_PUMP            , 54  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_PUMP   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_DCACHE_CAPP     , 55  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_DCACHE_CAPP );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_CMD_RATE      , 56  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_CMD_RATE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN  , 8   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_A_CMD_RATE_LEN );
+
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CHIP_IS_SYSTEM          , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CHIP_IS_SYSTEM );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_HNG_CHK_DISABLE         , 8   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_HNG_CHK_DISABLE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_DBG_CLR_MAX_HANG_STAGE      , 9   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_DBG_CLR_MAX_HANG_STAGE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SW_AB_WAIT              , 12  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SW_AB_WAIT );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SW_AB_WAIT_LEN          , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SW_AB_WAIT_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SP_HW_MARK              , 16  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SP_HW_MARK );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SP_HW_MARK_LEN          , 7   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SP_HW_MARK_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_GP_HW_MARK              , 23  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_GP_HW_MARK );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_GP_HW_MARK_LEN          , 7   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_GP_HW_MARK_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_LCL_HW_MARK             , 30  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LCL_HW_MARK );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_LCL_HW_MARK_LEN         , 6   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_LCL_HW_MARK_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CPU_RATIO_OVERRIDE      , 36  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CPU_RATIO_OVERRIDE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CPU_RATIO_OVERRIDE_LEN  , 6   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_CPU_RATIO_OVERRIDE_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_REQ_GATHER_ENABLE       , 57  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_REQ_GATHER_ENABLE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SWITCH_CD_PULSE         , 58  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SWITCH_CD_PULSE );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SWITCH_OPTION_AB        , 59  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SWITCH_OPTION_AB );
+
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG                 , 0   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG        );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SLOW            , 1   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SLOW   );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_COUNT     , 2   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SHIFT_COUNT );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_COUNT_LEN , 6   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SHIFT_COUNT_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SELECT          , 8   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELECT );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SELECT_LEN      , 4   , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SELECT_LEN );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_DATA      , 12  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SHIFT_DATA );
+REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN  , 52  , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CFG_SHIFT_DATA_LEN );
+
+REG64_FLD( PEC_PCS_M1_CONTROL_REG_CONTROL                          , 48  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CONTROL    );
+REG64_FLD( PEC_PCS_M1_CONTROL_REG_CONTROL_LEN                      , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PEC_PCS_M2_CONTROL_REG_CONTROL                          , 48  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CONTROL    );
+REG64_FLD( PEC_PCS_M2_CONTROL_REG_CONTROL_LEN                      , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PEC_PCS_M3_CONTROL_REG_CONTROL                          , 48  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CONTROL    );
+REG64_FLD( PEC_PCS_M3_CONTROL_REG_CONTROL_LEN                      , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PEC_PCS_M4_CONTROL_REG_CONTROL                          , 48  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CONTROL    );
+REG64_FLD( PEC_PCS_M4_CONTROL_REG_CONTROL_LEN                      , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PEC_PCS_SYS_CONTROL_REG_CONTROL                         , 48  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CONTROL    );
+REG64_FLD( PEC_PCS_SYS_CONTROL_REG_CONTROL_LEN                     , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CONTROL_LEN );
+
+REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_EN                          , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_CAPP_EN );
+REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_P8_MODE                     , 1   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_CAPP_P8_MODE );
+REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_NUM_MSG_ENG                 , 12  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_CAPP_NUM_MSG_ENG );
+REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_NUM_MSG_ENG_LEN             , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_CAPP_NUM_MSG_ENG_LEN );
+REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_APC_ENG                     , 16  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_CAPP_APC_ENG );
+REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_APC_ENG_LEN                 , 48  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_CAPP_APC_ENG_LEN );
+
+REG64_FLD( PEC_PECAPP_SEC_BAR_PE_CAPP                              , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PE_CAPP    );
+REG64_FLD( PEC_PECAPP_SEC_BAR_PE_CAPP_LEN                          , 26  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PE_CAPP_LEN );
+
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATSTART                        , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART   );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATSTART_LEN                    , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART_LEN );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATCANCEL                       , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL  );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATCANCEL_LEN                   , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL_LEN );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT0                          , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT0_LEN                      , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT1                          , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT1_LEN                      , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT2                          , 32  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT2_LEN                      , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT3                          , 40  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT3_LEN                      , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATFINISH                       , 48  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH  );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATFINISH_LEN                   , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH_LEN );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_RESERVED2                       , 56  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_RESERVED2_LEN                   , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_ACT                             , 63  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATSTART                        , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART   );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATSTART_LEN                    , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART_LEN );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATCANCEL                       , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL  );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATCANCEL_LEN                   , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL_LEN );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT0                          , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT0_LEN                      , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT1                          , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT1_LEN                      , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT2                          , 32  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT2_LEN                      , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT3                          , 40  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT3_LEN                      , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATFINISH                       , 48  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH  );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATFINISH_LEN                   , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH_LEN );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_RESERVED2                       , 56  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_RESERVED2_LEN                   , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_ACT                             , 63  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_ENABLE                         , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_RESETMODE                      , 1   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESETMODE  );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_FREEZEMODE                     , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_FREEZEMODE );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_DISABLE_PMISC                  , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_PMISC );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PMISC_MODE                     , 4   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_PMISC_MODE );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_CASCADE                        , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_CASCADE    );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_CASCADE_LEN                    , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_CASCADE_LEN );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C0                    , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C0 );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C0_LEN                , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C0_LEN );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C1                    , 10  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C1 );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C1_LEN                , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C1_LEN );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C2                    , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C2 );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C2_LEN                , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C2_LEN );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C3                    , 14  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C3 );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C3_LEN                , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C3_LEN );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT0                         , 16  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT0_LEN                     , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT1                         , 24  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT1_LEN                     , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT2                         , 32  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT2_LEN                     , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT3                         , 40  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT3_LEN                     , 8   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_LATENCY                        , 48  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_LATENCY    );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_LATENCY_LEN                    , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_LATENCY_LEN );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_RESERVED                       , 51  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_RESERVED_LEN                   , 13  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATSTART                        , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART   );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATSTART_LEN                    , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART_LEN );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATCANCEL                       , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL  );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATCANCEL_LEN                   , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL_LEN );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT0                          , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT0_LEN                      , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT1                          , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT1_LEN                      , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT2                          , 32  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT2_LEN                      , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT3                          , 40  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT3_LEN                      , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATFINISH                       , 48  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH  );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATFINISH_LEN                   , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH_LEN );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_RESERVED2                       , 56  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_RESERVED2_LEN                   , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_ACT                             , 63  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATSTART                        , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART   );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATSTART_LEN                    , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART_LEN );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATCANCEL                       , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL  );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATCANCEL_LEN                   , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL_LEN );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT0                          , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT0_LEN                      , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT1                          , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT1_LEN                      , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT2                          , 32  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT2_LEN                      , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT3                          , 40  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT3_LEN                      , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATFINISH                       , 48  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH  );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATFINISH_LEN                   , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH_LEN );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_RESERVED2                       , 56  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_RESERVED2_LEN                   , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_ACT                             , 63  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_RESETMODE                       , 1   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESETMODE  );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_FREEZEMODE                      , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_FREEZEMODE );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_DISABLE_PMISC                   , 3   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_PMISC );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PMISC_MODE                      , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PMISC_MODE );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_CASCADE                         , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CASCADE    );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_CASCADE_LEN                     , 3   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CASCADE_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C0                     , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C0 );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C0_LEN                 , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C0_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C1                     , 10  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C1 );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C1_LEN                 , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C1_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C2                     , 12  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C2 );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C2_LEN                 , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C2_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C3                     , 14  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C3 );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C3_LEN                 , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C3_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT0                          , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT0_LEN                      , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT1                          , 24  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT1_LEN                      , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT2                          , 32  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT2_LEN                      , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT3                          , 40  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT3_LEN                      , 8   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATSTART                        , 48  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART   );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATSTART_LEN                    , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATCANCEL                       , 53  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL  );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATCANCEL_LEN                   , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATFINISH                       , 58  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH  );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATFINISH_LEN                   , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_RESERVED                        , 63  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATSTART                        , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART   );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATSTART_LEN                    , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART_LEN );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATCANCEL                       , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL  );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATCANCEL_LEN                   , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL_LEN );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT0                          , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT0_LEN                      , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT1                          , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT1_LEN                      , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT2                          , 32  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT2_LEN                      , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT3                          , 40  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT3_LEN                      , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATFINISH                       , 48  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH  );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATFINISH_LEN                   , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH_LEN );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_RESERVED2                       , 56  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_RESERVED2_LEN                   , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_ACT                             , 63  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATSTART                        , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART   );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATSTART_LEN                    , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART_LEN );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATCANCEL                       , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL  );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATCANCEL_LEN                   , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL_LEN );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT0                          , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT0_LEN                      , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT1                          , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT1_LEN                      , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT2                          , 32  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT2_LEN                      , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT3                          , 40  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT3_LEN                      , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATFINISH                       , 48  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH  );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATFINISH_LEN                   , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH_LEN );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_RESERVED2                       , 56  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_RESERVED2_LEN                   , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_ACT                             , 63  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_ENABLE                         , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_RESETMODE                      , 1   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESETMODE  );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_FREEZEMODE                     , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_FREEZEMODE );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_DISABLE_PMISC                  , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_PMISC );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PMISC_MODE                     , 4   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_PMISC_MODE );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_CASCADE                        , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_CASCADE    );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_CASCADE_LEN                    , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_CASCADE_LEN );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C0                    , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C0 );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C0_LEN                , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C0_LEN );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C1                    , 10  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C1 );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C1_LEN                , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C1_LEN );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C2                    , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C2 );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C2_LEN                , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C2_LEN );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C3                    , 14  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C3 );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C3_LEN                , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C3_LEN );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT0                         , 16  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT0_LEN                     , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT1                         , 24  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT1_LEN                     , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT2                         , 32  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT2_LEN                     , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT3                         , 40  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT3_LEN                     , 8   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_LATENCY                        , 48  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_LATENCY    );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_LATENCY_LEN                    , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_LATENCY_LEN );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_RESERVED                       , 51  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_RESERVED_LEN                   , 13  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATSTART                        , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART   );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATSTART_LEN                    , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART_LEN );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATCANCEL                       , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL  );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATCANCEL_LEN                   , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL_LEN );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT0                          , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT0_LEN                      , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT1                          , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT1_LEN                      , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT2                          , 32  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT2_LEN                      , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT3                          , 40  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT3_LEN                      , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATFINISH                       , 48  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH  );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATFINISH_LEN                   , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH_LEN );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_RESERVED2                       , 56  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_RESERVED2_LEN                   , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_ACT                             , 63  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATSTART                        , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART   );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATSTART_LEN                    , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART_LEN );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATCANCEL                       , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL  );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATCANCEL_LEN                   , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL_LEN );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT0                          , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT0_LEN                      , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT1                          , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT1_LEN                      , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT2                          , 32  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT2_LEN                      , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT3                          , 40  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT3_LEN                      , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATFINISH                       , 48  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH  );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATFINISH_LEN                   , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH_LEN );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_RESERVED2                       , 56  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_RESERVED2_LEN                   , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_ACT                             , 63  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATSTART                        , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART   );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATSTART_LEN                    , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART_LEN );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATCANCEL                       , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL  );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATCANCEL_LEN                   , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL_LEN );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT0                          , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT0_LEN                      , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT1                          , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT1_LEN                      , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT2                          , 32  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT2_LEN                      , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT3                          , 40  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT3_LEN                      , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATFINISH                       , 48  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH  );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATFINISH_LEN                   , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH_LEN );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_RESERVED2                       , 56  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_RESERVED2_LEN                   , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_ACT                             , 63  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_RESETMODE                       , 1   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESETMODE  );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_FREEZEMODE                      , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_FREEZEMODE );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_DISABLE_PMISC                   , 3   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_PMISC );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PMISC_MODE                      , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PMISC_MODE );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_CASCADE                         , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CASCADE    );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_CASCADE_LEN                     , 3   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CASCADE_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C0                     , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C0 );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C0_LEN                 , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C0_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C1                     , 10  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C1 );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C1_LEN                 , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C1_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C2                     , 12  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C2 );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C2_LEN                 , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C2_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C3                     , 14  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C3 );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C3_LEN                 , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C3_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT0                          , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT0_LEN                      , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT1                          , 24  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT1_LEN                      , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT2                          , 32  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT2_LEN                      , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT3                          , 40  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT3_LEN                      , 8   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATSTART                        , 48  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART   );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATSTART_LEN                    , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATCANCEL                       , 53  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL  );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATCANCEL_LEN                   , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATFINISH                       , 58  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH  );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATFINISH_LEN                   , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_RESERVED                        , 63  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATSTART                        , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART   );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATSTART_LEN                    , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART_LEN );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATCANCEL                       , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL  );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATCANCEL_LEN                   , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL_LEN );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT0                          , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT0_LEN                      , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT1                          , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT1_LEN                      , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT2                          , 32  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT2_LEN                      , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT3                          , 40  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT3_LEN                      , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATFINISH                       , 48  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH  );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATFINISH_LEN                   , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH_LEN );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_RESERVED2                       , 56  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_RESERVED2_LEN                   , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_ACT                             , 63  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATSTART                        , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART   );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATSTART_LEN                    , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART_LEN );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATCANCEL                       , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL  );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATCANCEL_LEN                   , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL_LEN );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT0                          , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT0_LEN                      , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT1                          , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT1_LEN                      , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT2                          , 32  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT2_LEN                      , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT3                          , 40  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT3_LEN                      , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATFINISH                       , 48  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH  );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATFINISH_LEN                   , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH_LEN );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_RESERVED2                       , 56  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_RESERVED2_LEN                   , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_ACT                             , 63  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_ENABLE                          , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_RESETMODE                       , 1   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESETMODE  );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_FREEZEMODE                      , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_FREEZEMODE );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_DISABLE_PMISC                   , 3   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_PMISC );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PMISC_MODE                      , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PMISC_MODE );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_CASCADE                         , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CASCADE    );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_CASCADE_LEN                     , 3   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CASCADE_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C0                     , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C0 );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C0_LEN                 , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C0_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C1                     , 10  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C1 );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C1_LEN                 , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C1_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C2                     , 12  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C2 );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C2_LEN                 , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C2_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C3                     , 14  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C3 );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C3_LEN                 , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C3_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT0                          , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT0_LEN                      , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT1                          , 24  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT1_LEN                      , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT2                          , 32  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT2_LEN                      , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT3                          , 40  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT3_LEN                      , 8   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATSTART                        , 48  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART   );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATSTART_LEN                    , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATCANCEL                       , 53  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL  );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATCANCEL_LEN                   , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATFINISH                       , 58  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH  );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATFINISH_LEN                   , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_RESERVED                        , 63  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+
+REG64_FLD( NV_PERF_CONFIG_ENABLE                                   , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( NV_PERF_CONFIG_RESETMODE                                , 1   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESETMODE  );
+REG64_FLD( NV_PERF_CONFIG_FREEZEMODE                               , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_FREEZEMODE );
+REG64_FLD( NV_PERF_CONFIG_DISABLE_PMISC                            , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_PMISC );
+REG64_FLD( NV_PERF_CONFIG_PMISC_MODE                               , 4   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_PMISC_MODE );
+REG64_FLD( NV_PERF_CONFIG_CASCADE                                  , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_CASCADE    );
+REG64_FLD( NV_PERF_CONFIG_CASCADE_LEN                              , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_CASCADE_LEN );
+REG64_FLD( NV_PERF_CONFIG_PRESCALE_C0                              , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C0 );
+REG64_FLD( NV_PERF_CONFIG_PRESCALE_C0_LEN                          , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C0_LEN );
+REG64_FLD( NV_PERF_CONFIG_PRESCALE_C1                              , 10  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C1 );
+REG64_FLD( NV_PERF_CONFIG_PRESCALE_C1_LEN                          , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C1_LEN );
+REG64_FLD( NV_PERF_CONFIG_PRESCALE_C2                              , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C2 );
+REG64_FLD( NV_PERF_CONFIG_PRESCALE_C2_LEN                          , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C2_LEN );
+REG64_FLD( NV_PERF_CONFIG_PRESCALE_C3                              , 14  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C3 );
+REG64_FLD( NV_PERF_CONFIG_PRESCALE_C3_LEN                          , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_PRESCALE_C3_LEN );
+REG64_FLD( NV_PERF_CONFIG_EVENT0                                   , 16  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( NV_PERF_CONFIG_EVENT0_LEN                               , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( NV_PERF_CONFIG_EVENT1                                   , 24  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( NV_PERF_CONFIG_EVENT1_LEN                               , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( NV_PERF_CONFIG_EVENT2                                   , 32  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( NV_PERF_CONFIG_EVENT2_LEN                               , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( NV_PERF_CONFIG_EVENT3                                   , 40  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( NV_PERF_CONFIG_EVENT3_LEN                               , 8   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( NV_PERF_CONFIG_LATENCY                                  , 48  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_LATENCY    );
+REG64_FLD( NV_PERF_CONFIG_LATENCY_LEN                              , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_LATENCY_LEN );
+REG64_FLD( NV_PERF_CONFIG_RESERVED                                 , 51  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( NV_PERF_CONFIG_RESERVED_LEN                             , 13  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATSTART                        , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART   );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATSTART_LEN                    , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATSTART_LEN );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATCANCEL                       , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL  );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATCANCEL_LEN                   , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATCANCEL_LEN );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT0                          , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0     );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT0_LEN                      , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT0_LEN );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT1                          , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1     );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT1_LEN                      , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT1_LEN );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT2                          , 32  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2     );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT2_LEN                      , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT2_LEN );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT3                          , 40  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3     );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT3_LEN                      , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_EVENT3_LEN );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATFINISH                       , 48  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH  );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATFINISH_LEN                   , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_LATFINISH_LEN );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_RESERVED2                       , 56  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_RESERVED2_LEN                   , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_ACT                             , 63  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_ACT        );
+
+REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT0                    , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT0 );
+REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT0_LEN                , 16  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT0_LEN );
+REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT1                    , 16  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT1 );
+REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT1_LEN                , 16  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT1_LEN );
+REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT2                    , 32  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT2 );
+REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT2_LEN                , 16  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT2_LEN );
+REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT3                    , 48  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT3 );
+REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT3_LEN                , 16  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT3_LEN );
+
+REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT0                     , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT0 );
+REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT0_LEN                 , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT0_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT1                     , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT1 );
+REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT1_LEN                 , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT1_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT2                     , 32  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT2 );
+REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT2_LEN                 , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT2_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT3                     , 48  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT3 );
+REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT3_LEN                 , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT3_LEN );
+
+REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT0                     , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT0 );
+REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT0_LEN                 , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT0_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT1                     , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT1 );
+REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT1_LEN                 , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT1_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT2                     , 32  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT2 );
+REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT2_LEN                 , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT2_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT3                     , 48  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT3 );
+REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT3_LEN                 , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT3_LEN );
+
+REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT0                     , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT0 );
+REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT0_LEN                 , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT0_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT1                     , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT1 );
+REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT1_LEN                 , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT1_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT2                     , 32  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT2 );
+REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT2_LEN                 , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT2_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT3                     , 48  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT3 );
+REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT3_LEN                 , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT3_LEN );
+
+REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT0                              , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT0 );
+REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT0_LEN                          , 16  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT0_LEN );
+REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT1                              , 16  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT1 );
+REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT1_LEN                          , 16  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT1_LEN );
+REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT2                              , 32  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT2 );
+REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT2_LEN                          , 16  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT2_LEN );
+REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT3                              , 48  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT3 );
+REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT3_LEN                          , 16  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT3_LEN );
+
+REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT0                    , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT0 );
+REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT0_LEN                , 16  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT0_LEN );
+REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT1                    , 16  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT1 );
+REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT1_LEN                , 16  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT1_LEN );
+REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT2                    , 32  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT2 );
+REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT2_LEN                , 16  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT2_LEN );
+REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT3                    , 48  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT3 );
+REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT3_LEN                , 16  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_COUNT3_LEN );
+
+REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_NMCMD                      , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMCMD      );
+REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_NMCMD_LEN                  , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMCMD_LEN  );
+REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_NMEXCMD                    , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMEXCMD    );
+REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_NMEXCMD_LEN                , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMEXCMD_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_BE                         , 11  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BE         );
+REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_CS                         , 12  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CS         );
+REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_CS_LEN                     , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CS_LEN     );
+REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_AECS                       , 18  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_AECS       );
+REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_AECS_LEN                   , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_AECS_LEN   );
+REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_PE                         , 34  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_RESERVED1                  , 38  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_RESERVED1_LEN              , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_NMCMD                      , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMCMD      );
+REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_NMCMD_LEN                  , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMCMD_LEN  );
+REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_NMEXCMD                    , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMEXCMD    );
+REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_NMEXCMD_LEN                , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMEXCMD_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_BE                         , 11  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BE         );
+REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_CS                         , 12  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CS         );
+REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_CS_LEN                     , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CS_LEN     );
+REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_AECS                       , 18  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_AECS       );
+REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_AECS_LEN                   , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_AECS_LEN   );
+REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_PE                         , 34  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_RESERVED1                  , 38  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_RESERVED1_LEN              , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_NMCMD                      , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMCMD      );
+REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_NMCMD_LEN                  , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMCMD_LEN  );
+REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_NMEXCMD                    , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMEXCMD    );
+REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_NMEXCMD_LEN                , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMEXCMD_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_BE                         , 11  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BE         );
+REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_CS                         , 12  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CS         );
+REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_CS_LEN                     , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CS_LEN     );
+REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_AECS                       , 18  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_AECS       );
+REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_AECS_LEN                   , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_AECS_LEN   );
+REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_PE                         , 34  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_PE_LEN                     , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_RESERVED1                  , 38  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_RESERVED1_LEN              , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_NMCMD                     , 0   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMCMD      );
+REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_NMCMD_LEN                 , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMCMD_LEN  );
+REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_NMEXCMD                   , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMEXCMD    );
+REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_NMEXCMD_LEN               , 5   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMEXCMD_LEN );
+REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_BE                        , 11  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BE         );
+REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_CS                        , 12  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CS         );
+REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_CS_LEN                    , 6   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CS_LEN     );
+REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_AECS                      , 18  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_AECS       );
+REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_AECS_LEN                  , 16  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_AECS_LEN   );
+REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_PE                        , 34  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_PE_LEN                    , 4   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_RESERVED1                 , 38  , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_RESERVED1_LEN             , 2   , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_NMCMD                     , 0   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMCMD      );
+REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_NMCMD_LEN                 , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMCMD_LEN  );
+REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_NMEXCMD                   , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMEXCMD    );
+REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_NMEXCMD_LEN               , 5   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMEXCMD_LEN );
+REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_BE                        , 11  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BE         );
+REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_CS                        , 12  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CS         );
+REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_CS_LEN                    , 6   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CS_LEN     );
+REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_AECS                      , 18  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_AECS       );
+REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_AECS_LEN                  , 16  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_AECS_LEN   );
+REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_PE                        , 34  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_PE_LEN                    , 4   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_RESERVED1                 , 38  , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_RESERVED1_LEN             , 2   , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_NMCMD                     , 0   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMCMD      );
+REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_NMCMD_LEN                 , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMCMD_LEN  );
+REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_NMEXCMD                   , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMEXCMD    );
+REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_NMEXCMD_LEN               , 5   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_NMEXCMD_LEN );
+REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_BE                        , 11  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BE         );
+REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_CS                        , 12  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CS         );
+REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_CS_LEN                    , 6   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_CS_LEN     );
+REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_AECS                      , 18  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_AECS       );
+REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_AECS_LEN                  , 16  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_AECS_LEN   );
+REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_PE                        , 34  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE         );
+REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_PE_LEN                    , 4   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_PE_LEN     );
+REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_RESERVED1                 , 38  , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_RESERVED1_LEN             , 2   , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE0_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE0_DMA_STOPPED_STATE_LEN        , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE1_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE1_DMA_STOPPED_STATE_LEN        , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE10_DMA_STOPPED_STATE           , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE10_DMA_STOPPED_STATE_LEN       , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE11_DMA_STOPPED_STATE           , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE11_DMA_STOPPED_STATE_LEN       , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE12_DMA_STOPPED_STATE           , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE12_DMA_STOPPED_STATE_LEN       , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE13_DMA_STOPPED_STATE           , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE13_DMA_STOPPED_STATE_LEN       , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE14_DMA_STOPPED_STATE           , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE14_DMA_STOPPED_STATE_LEN       , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE15_DMA_STOPPED_STATE           , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE15_DMA_STOPPED_STATE_LEN       , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE2_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE2_DMA_STOPPED_STATE_LEN        , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE3_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE3_DMA_STOPPED_STATE_LEN        , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE4_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE4_DMA_STOPPED_STATE_LEN        , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE5_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE5_DMA_STOPPED_STATE_LEN        , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE6_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE6_DMA_STOPPED_STATE_LEN        , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE7_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE7_DMA_STOPPED_STATE_LEN        , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE8_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE8_DMA_STOPPED_STATE_LEN        , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE9_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE9_DMA_STOPPED_STATE_LEN        , 37  , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE_LEN );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE0_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE1_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE10_DMA_STOPPED_STATE           , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE11_DMA_STOPPED_STATE           , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE12_DMA_STOPPED_STATE           , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE13_DMA_STOPPED_STATE           , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE14_DMA_STOPPED_STATE           , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE15_DMA_STOPPED_STATE           , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE2_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE3_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE4_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE5_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE6_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE7_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE8_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE9_DMA_STOPPED_STATE            , 0   , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_DMA_STOPPED_STATE );
+
+REG64_FLD( PEC_STACK2_PE_DFREEZE_REG_DFREEZE                       , 0   , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_DFREEZE    );
+REG64_FLD( PEC_STACK2_PE_DFREEZE_REG_DFREEZE_LEN                   , 28  , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_DFREEZE_LEN );
+
+REG64_FLD( PEC_STACK1_PE_DFREEZE_REG_DFREEZE                       , 0   , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_DFREEZE    );
+REG64_FLD( PEC_STACK1_PE_DFREEZE_REG_DFREEZE_LEN                   , 28  , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_DFREEZE_LEN );
+
+REG64_FLD( PHB_PE_DFREEZE_REG_DFREEZE                              , 0   , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DFREEZE    );
+REG64_FLD( PHB_PE_DFREEZE_REG_DFREEZE_LEN                          , 28  , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_DFREEZE_LEN );
+
+REG64_FLD( PEC_STACK0_PE_DFREEZE_REG_DFREEZE                       , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  ,
+           SH_FLD_DFREEZE    );
+REG64_FLD( PEC_STACK0_PE_DFREEZE_REG_DFREEZE_LEN                   , 28  , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW  ,
+           SH_FLD_DFREEZE_LEN );
+
+REG64_FLD( PU_PBAIB_STACK5_PFIRACTION0_REG_PFIRACTION0             , 0   , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION0 );
+REG64_FLD( PU_PBAIB_STACK5_PFIRACTION0_REG_PFIRACTION0_LEN         , 7   , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION0_LEN );
+
+REG64_FLD( PHB_PFIRACTION0_REG_PFIRACTION0                         , 0   , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION0 );
+REG64_FLD( PHB_PFIRACTION0_REG_PFIRACTION0_LEN                     , 7   , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION0_LEN );
+
+REG64_FLD( PU_PBAIB_STACK2_PFIRACTION0_REG_PFIRACTION0             , 0   , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION0 );
+REG64_FLD( PU_PBAIB_STACK2_PFIRACTION0_REG_PFIRACTION0_LEN         , 7   , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION0_LEN );
+
+REG64_FLD( PU_PBAIB_STACK1_PFIRACTION0_REG_PFIRACTION0             , 0   , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION0 );
+REG64_FLD( PU_PBAIB_STACK1_PFIRACTION0_REG_PFIRACTION0_LEN         , 7   , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION0_LEN );
+
+REG64_FLD( PU_PBAIB_STACK5_PFIRACTION1_REG_PFIRACTION1             , 0   , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION1 );
+REG64_FLD( PU_PBAIB_STACK5_PFIRACTION1_REG_PFIRACTION1_LEN         , 7   , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION1_LEN );
+
+REG64_FLD( PHB_PFIRACTION1_REG_PFIRACTION1                         , 0   , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION1 );
+REG64_FLD( PHB_PFIRACTION1_REG_PFIRACTION1_LEN                     , 7   , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION1_LEN );
+
+REG64_FLD( PU_PBAIB_STACK2_PFIRACTION1_REG_PFIRACTION1             , 0   , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION1 );
+REG64_FLD( PU_PBAIB_STACK2_PFIRACTION1_REG_PFIRACTION1_LEN         , 7   , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION1_LEN );
+
+REG64_FLD( PU_PBAIB_STACK1_PFIRACTION1_REG_PFIRACTION1             , 0   , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION1 );
+REG64_FLD( PU_PBAIB_STACK1_PFIRACTION1_REG_PFIRACTION1_LEN         , 7   , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_PFIRACTION1_LEN );
+
+REG64_FLD( PU_PBAIB_STACK5_PFIRMASK_REG_PFIRMASK                   , 0   , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRMASK   );
+REG64_FLD( PU_PBAIB_STACK5_PFIRMASK_REG_PFIRMASK_LEN               , 7   , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRMASK_LEN );
+
+REG64_FLD( PHB_PFIRMASK_REG_PFIRMASK                               , 0   , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRMASK   );
+REG64_FLD( PHB_PFIRMASK_REG_PFIRMASK_LEN                           , 7   , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRMASK_LEN );
+
+REG64_FLD( PU_PBAIB_STACK2_PFIRMASK_REG_PFIRMASK                   , 0   , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRMASK   );
+REG64_FLD( PU_PBAIB_STACK2_PFIRMASK_REG_PFIRMASK_LEN               , 7   , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRMASK_LEN );
+
+REG64_FLD( PU_PBAIB_STACK1_PFIRMASK_REG_PFIRMASK                   , 0   , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRMASK   );
+REG64_FLD( PU_PBAIB_STACK1_PFIRMASK_REG_PFIRMASK_LEN               , 7   , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRMASK_LEN );
+
+REG64_FLD( PU_PBAIB_STACK5_PFIR_REG_PFIRPFIR                       , 0   , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRPFIR   );
+REG64_FLD( PU_PBAIB_STACK5_PFIR_REG_PFIRPFIR_LEN                   , 7   , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRPFIR_LEN );
+
+REG64_FLD( PHB_PFIR_REG_PFIRPFIR                                   , 0   , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRPFIR   );
+REG64_FLD( PHB_PFIR_REG_PFIRPFIR_LEN                               , 7   , SH_UNT_PHB      , SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRPFIR_LEN );
+
+REG64_FLD( PU_PBAIB_STACK2_PFIR_REG_PFIRPFIR                       , 0   , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRPFIR   );
+REG64_FLD( PU_PBAIB_STACK2_PFIR_REG_PFIRPFIR_LEN                   , 7   , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRPFIR_LEN );
+
+REG64_FLD( PU_PBAIB_STACK1_PFIR_REG_PFIRPFIR                       , 0   , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRPFIR   );
+REG64_FLD( PU_PBAIB_STACK1_PFIR_REG_PFIRPFIR_LEN                   , 7   , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM2_OR ,
+           SH_FLD_PFIRPFIR_LEN );
+
+REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR                        , 0   , SH_UNT_PEC_STACK2, SH_ACS_SCOM     ,
+           SH_FLD_PE_PHB_BAR );
+REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR_LEN                    , 42  , SH_UNT_PEC_STACK2, SH_ACS_SCOM     ,
+           SH_FLD_PE_PHB_BAR_LEN );
+
+REG64_FLD( PEC_STACK1_PHBBAR_REG_PE_PHB_BAR                        , 0   , SH_UNT_PEC_STACK1, SH_ACS_SCOM     ,
+           SH_FLD_PE_PHB_BAR );
+REG64_FLD( PEC_STACK1_PHBBAR_REG_PE_PHB_BAR_LEN                    , 42  , SH_UNT_PEC_STACK1, SH_ACS_SCOM     ,
+           SH_FLD_PE_PHB_BAR_LEN );
+
+REG64_FLD( PHB_PHBBAR_REG_PE_PHB_BAR                               , 0   , SH_UNT_PHB      , SH_ACS_SCOM     ,
+           SH_FLD_PE_PHB_BAR );
+REG64_FLD( PHB_PHBBAR_REG_PE_PHB_BAR_LEN                           , 42  , SH_UNT_PHB      , SH_ACS_SCOM     ,
+           SH_FLD_PE_PHB_BAR_LEN );
+
+REG64_FLD( PEC_STACK0_PHBBAR_REG_PE_PHB_BAR                        , 0   , SH_UNT_PEC_STACK0, SH_ACS_SCOM     ,
+           SH_FLD_PE_PHB_BAR );
+REG64_FLD( PEC_STACK0_PHBBAR_REG_PE_PHB_BAR_LEN                    , 42  , SH_UNT_PEC_STACK0, SH_ACS_SCOM     ,
+           SH_FLD_PE_PHB_BAR_LEN );
+
+REG64_FLD( PU_PBAIB_STACK5_PHBRESET_REG_PE_ETU_RESET               , 0   , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ETU_RESET );
+
+REG64_FLD( PHB_PHBRESET_REG_PE_ETU_RESET                           , 0   , SH_UNT_PHB      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ETU_RESET );
+
+REG64_FLD( PU_PBAIB_STACK2_PHBRESET_REG_PE_ETU_RESET               , 0   , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ETU_RESET );
+
+REG64_FLD( PU_PBAIB_STACK1_PHBRESET_REG_PE_ETU_RESET               , 0   , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_ETU_RESET );
+
+REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_ENABLE                       , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM0_PHY_BAR_RESERVED1                           , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM0_PHY_BAR_RESERVED1_LEN                       , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_GROUP                        , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_GROUP_LEN                    , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_CHIP                         , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_CHIP_LEN                     , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_ADDR                         , 10  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_ADDR_LEN                     , 21  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM0_PHY_BAR_RESERVED2                           , 31  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_ENABLE                       , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM2_PHY_BAR_RESERVED1                           , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM2_PHY_BAR_RESERVED1_LEN                       , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_GROUP                        , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_GROUP_LEN                    , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_CHIP                         , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_CHIP_LEN                     , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_ADDR                         , 10  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_ADDR_LEN                     , 21  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM2_PHY_BAR_RESERVED2                           , 31  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_ENABLE                       , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM3_PHY_BAR_RESERVED1                           , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM3_PHY_BAR_RESERVED1_LEN                       , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_GROUP                        , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_GROUP_LEN                    , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_CHIP                         , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_CHIP_LEN                     , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_ADDR                         , 10  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_ADDR_LEN                     , 21  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM3_PHY_BAR_RESERVED2                           , 31  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_ENABLE                       , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM3_PHY_BAR_RESERVED1                           , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM3_PHY_BAR_RESERVED1_LEN                       , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_GROUP                        , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_GROUP_LEN                    , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_CHIP                         , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_CHIP_LEN                     , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_ADDR                         , 10  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_ADDR_LEN                     , 21  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM3_PHY_BAR_RESERVED2                           , 31  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_ENABLE                       , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM3_PHY_BAR_RESERVED1                           , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM3_PHY_BAR_RESERVED1_LEN                       , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_GROUP                        , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_GROUP_LEN                    , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_CHIP                         , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_CHIP_LEN                     , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_ADDR                         , 10  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_ADDR_LEN                     , 21  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM3_PHY_BAR_RESERVED2                           , 31  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_ENABLE                       , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM1_PHY_BAR_RESERVED1                           , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM1_PHY_BAR_RESERVED1_LEN                       , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_GROUP                        , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_GROUP_LEN                    , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_CHIP                         , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_CHIP_LEN                     , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_ADDR                         , 10  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_ADDR_LEN                     , 21  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM1_PHY_BAR_RESERVED2                           , 31  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_ENABLE                       , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM2_PHY_BAR_RESERVED1                           , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM2_PHY_BAR_RESERVED1_LEN                       , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_GROUP                        , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_GROUP_LEN                    , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_CHIP                         , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_CHIP_LEN                     , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_ADDR                         , 10  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_ADDR_LEN                     , 21  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM2_PHY_BAR_RESERVED2                           , 31  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_ENABLE                       , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM1_PHY_BAR_RESERVED1                           , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM1_PHY_BAR_RESERVED1_LEN                       , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_GROUP                        , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_GROUP_LEN                    , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_CHIP                         , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_CHIP_LEN                     , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_ADDR                         , 10  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_ADDR_LEN                     , 21  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM1_PHY_BAR_RESERVED2                           , 31  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_ENABLE                       , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM2_PHY_BAR_RESERVED1                           , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM2_PHY_BAR_RESERVED1_LEN                       , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_GROUP                        , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_GROUP_LEN                    , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_CHIP                         , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_CHIP_LEN                     , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_ADDR                         , 10  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_ADDR_LEN                     , 21  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM2_PHY_BAR_RESERVED2                           , 31  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_ENABLE                       , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU2_SM0_PHY_BAR_RESERVED1                           , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_SM0_PHY_BAR_RESERVED1_LEN                       , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_GROUP                        , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_GROUP_LEN                    , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_CHIP                         , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_CHIP_LEN                     , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_ADDR                         , 10  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_ADDR_LEN                     , 21  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU2_SM0_PHY_BAR_RESERVED2                           , 31  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_ENABLE                       , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU0_SM1_PHY_BAR_RESERVED1                           , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU0_SM1_PHY_BAR_RESERVED1_LEN                       , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_GROUP                        , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_GROUP_LEN                    , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_CHIP                         , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_CHIP_LEN                     , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_ADDR                         , 10  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_ADDR_LEN                     , 21  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU0_SM1_PHY_BAR_RESERVED2                           , 31  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_ENABLE                       , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ENABLE );
+REG64_FLD( PU_NPU1_SM0_PHY_BAR_RESERVED1                           , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU1_SM0_PHY_BAR_RESERVED1_LEN                       , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_GROUP                        , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP );
+REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_GROUP_LEN                    , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_GROUP_LEN );
+REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_CHIP                         , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP );
+REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_CHIP_LEN                     , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_CHIP_LEN );
+REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_ADDR                         , 10  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR );
+REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_ADDR_LEN                     , 21  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_ADDR_LEN );
+REG64_FLD( PU_NPU1_SM0_PHY_BAR_RESERVED2                           , 31  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ENABLE_0                , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ENABLE_0 );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ID_0                    , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ID_0    );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ID_0_LEN                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ID_0_LEN );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ACTIVITY_0              , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ACTIVITY_0 );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ACTIVITY_0_LEN          , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ACTIVITY_0_LEN );
+
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ENABLE_1                , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ENABLE_1 );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ID_1                    , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ID_1    );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ID_1_LEN                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ID_1_LEN );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ACTIVITY_1              , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ACTIVITY_1 );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ACTIVITY_1_LEN          , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ACTIVITY_1_LEN );
+
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ENABLE_2                , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ENABLE_2 );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ID_2                    , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ID_2    );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ID_2_LEN                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ID_2_LEN );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ACTIVITY_2              , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ACTIVITY_2 );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ACTIVITY_2_LEN          , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ACTIVITY_2_LEN );
+
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ENABLE_3                , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ENABLE_3 );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ID_3                    , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ID_3    );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ID_3_LEN                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ID_3_LEN );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ACTIVITY_3              , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ACTIVITY_3 );
+REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ACTIVITY_3_LEN          , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_ACTIVITY_3_LEN );
+
+REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_B_CC_READ_ENABLE_0          , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_READ_ENABLE_0 );
+REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_B_CC_WRITE_ENABLE_0         , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_WRITE_ENABLE_0 );
+
+REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_C_CC_READ_ENABLE_1          , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_READ_ENABLE_1 );
+REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_C_CC_WRITE_ENABLE_1         , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_WRITE_ENABLE_1 );
+
+REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_D_CC_READ_ENABLE_2          , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_READ_ENABLE_2 );
+REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_D_CC_WRITE_ENABLE_2         , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_WRITE_ENABLE_2 );
+
+REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_E_CC_READ_ENABLE_3          , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_READ_ENABLE_3 );
+REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_E_CC_WRITE_ENABLE_3         , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CC_WRITE_ENABLE_3 );
+
+REG64_FLD( PU_PIBMEM_ADDRESS_REGISTER_POINTER                      , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_POINTER    );
+REG64_FLD( PU_PIBMEM_ADDRESS_REGISTER_POINTER_LEN                  , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_POINTER_LEN );
+
+REG64_FLD( PU_PIBMEM_ADDRESS_REGISTER_FA_POINTER                   , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_POINTER    );
+REG64_FLD( PU_PIBMEM_ADDRESS_REGISTER_FA_POINTER_LEN               , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_POINTER_LEN );
+
+REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_AUTO_PRE_INCREMENT_PIB       , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_PRE_INCREMENT_PIB );
+REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_AUTO_POST_DECREMENT_PIB      , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_POST_DECREMENT_PIB );
+REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_DISABLE_ECC                  , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_ECC );
+REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_AUTO_PRE_INCREMENT_FACES     , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_PRE_INCREMENT_FACES );
+REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_AUTO_POST_DECREMENT_FACES    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_POST_DECREMENT_FACES );
+REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_CHKSW_AR012                  , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHKSW_AR012 );
+
+REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_0_DATA                        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_0_DATA_LEN                    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_1_DATA                        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_1_DATA_LEN                    , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_2_DATA                        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_2_DATA_LEN                    , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_3_DATA                        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_3_DATA_LEN                    , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_PIBMEM_RESET_REGISTER_RESET                          , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESET      );
+REG64_FLD( PU_PIBMEM_RESET_REGISTER_RESET_LEN                      , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESET_LEN  );
+
+REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_INVALID_PIB                   , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_INVALID_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_WRITE_INVALID_PIB                  , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_INVALID_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_READ_INVALID_PIB                   , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_READ_INVALID_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_UNCORRECTED_ERROR_PIB          , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_UNCORRECTED_ERROR_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_CORRECTED_ERROR_PIB            , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_CORRECTED_ERROR_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_WRITE_RST_INTERRUPT_PIB            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_RST_INTERRUPT_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_READ_RST_INTERRUPT_PIB             , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_READ_RST_INTERRUPT_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_FSM_PRESENT_STATE                  , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FSM_PRESENT_STATE );
+REG64_FLD( PU_PIBMEM_STATUS_REG_FSM_PRESENT_STATE_LEN              , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FSM_PRESENT_STATE_LEN );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_INVALID_FACES                 , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_INVALID_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_WRITE_INVALID_FACES                , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_INVALID_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_READ_INVALID_FACES                 , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_READ_INVALID_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_UNCORRECTED_ERROR_FACES        , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_UNCORRECTED_ERROR_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_CORRECTED_ERROR_FACES          , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_CORRECTED_ERROR_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_BAD_ARRAY_ADDRESS_FACES            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAD_ARRAY_ADDRESS_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_WRITE_RST_INTERRUPT_FACES          , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_RST_INTERRUPT_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_READ_RST_INTERRUPT_FACES           , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_READ_RST_INTERRUPT_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_PIB                , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_RESET_INTR_PIB );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_PIB_LEN            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_RESET_INTR_PIB_LEN );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_FACES              , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_RESET_INTR_FACES );
+REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_FACES_LEN          , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_RESET_INTR_FACES_LEN );
+
+REG64_FLD( PU_PIB_CMD_REG_RNW                                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RNW        );
+REG64_FLD( PU_PIB_CMD_REG_ADR                                      , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADR        );
+REG64_FLD( PU_PIB_CMD_REG_ADR_LEN                                  , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADR_LEN    );
+
+REG64_FLD( PU_PIB_DATA_REG_DATA                                    , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_PIB_DATA_REG_DATA_LEN                                , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_PIB_RESET_REG_RESET                                  , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESET      );
+REG64_FLD( PU_PIB_RESET_REG_STATE                                  , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STATE      );
+REG64_FLD( PU_PIB_RESET_REG_ABORTED_CMD                            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ABORTED_CMD );
+
+REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_EN                           , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PERFMON_EN );
+REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_EN_LEN                       , 32  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PERFMON_EN_LEN );
+REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_READ_TYPE                    , 32  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PERFMON_READ_TYPE );
+REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_READ_TYPE_LEN                , 2   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PERFMON_READ_TYPE_LEN );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE0                       , 36  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PMON_MUX_BYTE0 );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE0_LEN                   , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PMON_MUX_BYTE0_LEN );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE1                       , 40  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PMON_MUX_BYTE1 );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE1_LEN                   , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PMON_MUX_BYTE1_LEN );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE2                       , 44  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PMON_MUX_BYTE2 );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE2_LEN                   , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PMON_MUX_BYTE2_LEN );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE3                       , 48  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PMON_MUX_BYTE3 );
+REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE3_LEN                   , 4   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_PMON_MUX_BYTE3_LEN );
+
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_ENABLE                 , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER0_ENABLE );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_ENABLE                 , 1   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER1_ENABLE );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_ENABLE                 , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER2_ENABLE );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_ENABLE                 , 3   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER3_ENABLE );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_PRESCALER_SELECT                , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_PRESCALER_SELECT );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_PRESCALER_SELECT_LEN            , 3   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_PRESCALER_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER_FREEZE_MODE             , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER_FREEZE_MODE );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER_RESET_MODE              , 8   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER_RESET_MODE );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_EVENT_SELECT           , 9   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER0_EVENT_SELECT );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_EVENT_SELECT_LEN       , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER0_EVENT_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_POSEDGE_SELECT         , 13  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER0_POSEDGE_SELECT );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_BIT_PAIR_SELECT        , 14  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_BIT_PAIR_SELECT_LEN    , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_EVENT_SELECT           , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER1_EVENT_SELECT );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_EVENT_SELECT_LEN       , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER1_EVENT_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_POSEDGE_SELECT         , 20  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER1_POSEDGE_SELECT );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_BIT_PAIR_SELECT        , 21  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_BIT_PAIR_SELECT_LEN    , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_EVENT_SELECT           , 23  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER2_EVENT_SELECT );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_EVENT_SELECT_LEN       , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER2_EVENT_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_POSEDGE_SELECT         , 27  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER2_POSEDGE_SELECT );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_BIT_PAIR_SELECT        , 28  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_BIT_PAIR_SELECT_LEN    , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_EVENT_SELECT           , 30  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER3_EVENT_SELECT );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_EVENT_SELECT_LEN       , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER3_EVENT_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_POSEDGE_SELECT         , 34  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER3_POSEDGE_SELECT );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_BIT_PAIR_SELECT        , 35  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_BIT_PAIR_SELECT_LEN    , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_PORT_SELECT                     , 37  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_PORT_SELECT );
+REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_PORT_SELECT_LEN                 , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUA_PORT_SELECT_LEN );
+
+REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_0                           , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERA_0 );
+REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_0_LEN                       , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERA_0_LEN );
+REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_1                           , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERA_1 );
+REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_1_LEN                       , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERA_1_LEN );
+REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_2                           , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERA_2 );
+REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_2_LEN                       , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERA_2_LEN );
+REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_3                           , 48  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERA_3 );
+REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_3_LEN                       , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERA_3_LEN );
+
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_ENABLE                 , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER0_ENABLE );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_ENABLE                 , 1   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER1_ENABLE );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_ENABLE                 , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER2_ENABLE );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_ENABLE                 , 3   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER3_ENABLE );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_PRESCALER_SELECT                , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_PRESCALER_SELECT );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_PRESCALER_SELECT_LEN            , 3   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_PRESCALER_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER_FREEZE_MODE             , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER_FREEZE_MODE );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER_RESET_MODE              , 8   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER_RESET_MODE );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_EVENT_SELECT           , 9   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER0_EVENT_SELECT );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_EVENT_SELECT_LEN       , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER0_EVENT_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_POSEDGE_SELECT         , 13  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER0_POSEDGE_SELECT );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_BIT_PAIR_SELECT        , 14  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_BIT_PAIR_SELECT_LEN    , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_EVENT_SELECT           , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER1_EVENT_SELECT );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_EVENT_SELECT_LEN       , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER1_EVENT_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_POSEDGE_SELECT         , 20  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER1_POSEDGE_SELECT );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_BIT_PAIR_SELECT        , 21  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_BIT_PAIR_SELECT_LEN    , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_EVENT_SELECT           , 23  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER2_EVENT_SELECT );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_EVENT_SELECT_LEN       , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER2_EVENT_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_POSEDGE_SELECT         , 27  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER2_POSEDGE_SELECT );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_BIT_PAIR_SELECT        , 28  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_BIT_PAIR_SELECT_LEN    , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_EVENT_SELECT           , 30  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER3_EVENT_SELECT );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_EVENT_SELECT_LEN       , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER3_EVENT_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_POSEDGE_SELECT         , 34  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER3_POSEDGE_SELECT );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_BIT_PAIR_SELECT        , 35  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_BIT_PAIR_SELECT_LEN    , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT_LEN );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_PORT_SELECT                     , 37  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_PORT_SELECT );
+REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_PORT_SELECT_LEN                 , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMUB_PORT_SELECT_LEN );
+
+REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_0                           , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERB_0 );
+REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_0_LEN                       , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERB_0_LEN );
+REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_1                           , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERB_1 );
+REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_1_LEN                       , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERB_1_LEN );
+REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_2                           , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERB_2 );
+REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_2_LEN                       , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERB_2_LEN );
+REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_3                           , 48  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERB_3 );
+REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_3_LEN                       , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_COUNTERB_3_LEN );
+
+REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_SIBRC                          , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_WE                             , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_LP                             , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_SIBRC                          , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_WE                             , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_LP                             , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+REG64_FLD( PU_PPE_XIRAMDBG_XIRAMRA_SPRG0                           , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                       , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_PPE_XIRAMEDR_XIRAMGA_IR                              , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR );
+REG64_FLD( PU_PPE_XIRAMEDR_XIRAMGA_IR_LEN                          , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR_LEN );
+REG64_FLD( PU_PPE_XIRAMEDR_EDR                                     , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EDR        );
+REG64_FLD( PU_PPE_XIRAMEDR_EDR_LEN                                 , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EDR_LEN    );
+
+REG64_FLD( PU_PPE_XIRAMGA_IR                                       , 0   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_IR         );
+REG64_FLD( PU_PPE_XIRAMGA_IR_LEN                                   , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_IR_LEN     );
+REG64_FLD( PU_PPE_XIRAMGA_XIRAMRA_SPRG0                            , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( PU_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                        , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( PU_PPE_XIRAMRA_XIXCR_XCR                                , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR  );
+REG64_FLD( PU_PPE_XIRAMRA_XIXCR_XCR_LEN                            , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR_LEN );
+REG64_FLD( PU_PPE_XIRAMRA_SPRG0                                    , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0      );
+REG64_FLD( PU_PPE_XIRAMRA_SPRG0_LEN                                , 32  , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0_LEN  );
+
+REG64_FLD( PU_PPE_XIXCR_XCR                                        , 1   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR        );
+REG64_FLD( PU_PPE_XIXCR_XCR_LEN                                    , 3   , SH_UNT          , SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR_LEN    );
+
+REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_RESERVED1                       , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_RESERVED1_LEN                   , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_START                           , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_START_LEN                       , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_RESERVED2                       , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_RESERVED2_LEN                   , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_END                             , 17  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_END_LEN                         , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( NV_PRB_HA_PTR_RESERVED1                                 , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( NV_PRB_HA_PTR_RESERVED1_LEN                             , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( NV_PRB_HA_PTR_START                                     , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( NV_PRB_HA_PTR_START_LEN                                 , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( NV_PRB_HA_PTR_RESERVED2                                 , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( NV_PRB_HA_PTR_RESERVED2_LEN                             , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( NV_PRB_HA_PTR_END                                       , 17  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( NV_PRB_HA_PTR_END_LEN                                   , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_RESERVED1                       , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_RESERVED1_LEN                   , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_START                           , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_START_LEN                       , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_RESERVED2                       , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_RESERVED2_LEN                   , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_END                             , 17  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_END_LEN                         , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( PEC_PREDV_REG_PE_RD_TIMEOUT_MASK                        , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_RD_TIMEOUT_MASK );
+REG64_FLD( PEC_PREDV_REG_PE_RD_TIMEOUT_MASK_LEN                    , 8   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_RD_TIMEOUT_MASK_LEN );
+REG64_FLD( PEC_PREDV_REG_PE_WR_TIMEOUT_MASK                        , 8   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_WR_TIMEOUT_MASK );
+REG64_FLD( PEC_PREDV_REG_PE_WR_TIMEOUT_MASK_LEN                    , 8   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_WR_TIMEOUT_MASK_LEN );
+
+REG64_FLD( PEC_PRE_COUNTER_REG_COUNTER                             , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COUNTER    );
+REG64_FLD( PEC_PRE_COUNTER_REG_COUNTER_LEN                         , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_COUNTER_LEN );
+
+REG64_FLD( PU_PRGM_REGISTER_PRGM_ADDR                              , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRGM_ADDR  );
+REG64_FLD( PU_PRGM_REGISTER_PRGM_ADDR_LEN                          , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRGM_ADDR_LEN );
+REG64_FLD( PU_PRGM_REGISTER_PRG_BIT_LOCATION                       , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRG_BIT_LOCATION );
+REG64_FLD( PU_PRGM_REGISTER_PRG_BIT_LOCATION_LEN                   , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRG_BIT_LOCATION_LEN );
+
+REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_NDL                             , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NDL        );
+REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_NDL_LEN                         , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_NDL_LEN    );
+REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_PHY                             , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_PHY        );
+REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_PHY_LEN                         , 2   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_PHY_LEN    );
+
+REG64_FLD( NV_PRI_CONFIG_NDL                                       , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NDL        );
+REG64_FLD( NV_PRI_CONFIG_NDL_LEN                                   , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_NDL_LEN    );
+REG64_FLD( NV_PRI_CONFIG_PHY                                       , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_PHY        );
+REG64_FLD( NV_PRI_CONFIG_PHY_LEN                                   , 2   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_PHY_LEN    );
+
+REG64_FLD( PU_NPU2_NTL1_PRI_CONFIG_NDL                             , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NDL        );
+REG64_FLD( PU_NPU2_NTL1_PRI_CONFIG_NDL_LEN                         , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_NDL_LEN    );
+REG64_FLD( PU_NPU2_NTL1_PRI_CONFIG_PHY                             , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_PHY        );
+REG64_FLD( PU_NPU2_NTL1_PRI_CONFIG_PHY_LEN                         , 2   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_PHY_LEN    );
+
+REG64_FLD( PU_PROBE_PROTECT_STATUS_BITS                            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BITS       );
+REG64_FLD( PU_PROBE_PROTECT_STATUS_BITS_LEN                        , 42  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BITS_LEN   );
+
+REG64_FLD( PEC_PROTECT_MODE_REG_READ_ENABLE                        , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_READ_ENABLE );
+REG64_FLD( PEC_PROTECT_MODE_REG_WRITE_ENABLE                       , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( PU_PRV_MISC_TPSBE_TPBR_SBE_INTR                         , 0   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_TPSBE_TPBR_SBE_INTR );
+REG64_FLD( PU_PRV_MISC_CHKSW_AR012                                 , 1   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_CHKSW_AR012 );
+REG64_FLD( PU_PRV_MISC_RESERVED_18                                 , 2   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_18 );
+REG64_FLD( PU_PRV_MISC_RESERVED_18_LEN                             , 2   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_18_LEN );
+REG64_FLD( PU_PRV_MISC_SBE_EXTERNAL_FIRS                           , 4   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_SBE_EXTERNAL_FIRS );
+REG64_FLD( PU_PRV_MISC_SBE_EXTERNAL_FIRS_LEN                       , 4   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_SBE_EXTERNAL_FIRS_LEN );
+REG64_FLD( PU_PRV_MISC_RESERVED_17                                 , 8   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_17 );
+REG64_FLD( PU_PRV_MISC_RESERVED_17_LEN                             , 4   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_17_LEN );
+REG64_FLD( PU_PRV_MISC_TPSBE_TPIO_TPM_RESET                        , 12  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_TPSBE_TPIO_TPM_RESET );
+REG64_FLD( PU_PRV_MISC_TPSBE_TPOCC_HALT_COMPLEX                    , 13  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_TPSBE_TPOCC_HALT_COMPLEX );
+REG64_FLD( PU_PRV_MISC_RESERVED_16                                 , 14  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_16 );
+REG64_FLD( PU_PRV_MISC_RESERVED_16_LEN                             , 2   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED_16_LEN );
+REG64_FLD( PU_PRV_MISC_I2C_TIMEOUT_VALUE                           , 16  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_I2C_TIMEOUT_VALUE );
+REG64_FLD( PU_PRV_MISC_I2C_TIMEOUT_VALUE_LEN                       , 32  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_I2C_TIMEOUT_VALUE_LEN );
+
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                 , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_WDATA_PARITY );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY               , 1   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_PARITY );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY           , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_DL_RETURN_P0                     , 3   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_P0 );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_UL_RDATA_PARITY                  , 4   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_UL_RDATA_PARITY );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_UL_P0                            , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_UL_P0      );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE      , 6   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE            , 7   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH  , 8   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH  , 10  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD              , 11  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_WRITE_NVLD );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD               , 12  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_READ_NVLD );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID            , 13  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_ADDR_INVALID );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY               , 14  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_COMMAND_PARITY );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                  , 15  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_GENERAL_TIMEOUT );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PU_N3_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                 , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_WDATA_PARITY );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY               , 1   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_PARITY );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY           , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_DL_RETURN_P0                     , 3   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_P0 );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_UL_RDATA_PARITY                  , 4   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_UL_RDATA_PARITY );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_UL_P0                            , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_UL_P0      );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE      , 6   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE            , 7   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH  , 8   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH  , 10  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD              , 11  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_WRITE_NVLD );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD               , 12  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_READ_NVLD );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID            , 13  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_ADDR_INVALID );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY               , 14  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_COMMAND_PARITY );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                  , 15  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_GENERAL_TIMEOUT );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PU_N1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( PU_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                    , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PCB_WDATA_PARITY );
+REG64_FLD( PU_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY                  , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_PARITY );
+REG64_FLD( PU_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY              , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PU_PSCOM_ERROR_MASK_DL_RETURN_P0                        , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_P0 );
+REG64_FLD( PU_PSCOM_ERROR_MASK_UL_RDATA_PARITY                     , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UL_RDATA_PARITY );
+REG64_FLD( PU_PSCOM_ERROR_MASK_UL_P0                               , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UL_P0      );
+REG64_FLD( PU_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE         , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PU_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE               , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PU_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PU_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PU_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH     , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PU_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD                 , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_WRITE_NVLD );
+REG64_FLD( PU_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD                  , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_READ_NVLD );
+REG64_FLD( PU_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID               , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_ADDR_INVALID );
+REG64_FLD( PU_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY                  , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PCB_COMMAND_PARITY );
+REG64_FLD( PU_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                     , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_GENERAL_TIMEOUT );
+REG64_FLD( PU_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PU_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                 , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_WDATA_PARITY );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY               , 1   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_PARITY );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY           , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_DL_RETURN_P0                     , 3   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_P0 );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_UL_RDATA_PARITY                  , 4   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_UL_RDATA_PARITY );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_UL_P0                            , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_UL_P0      );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE      , 6   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE            , 7   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH  , 8   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH  , 10  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD              , 11  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_WRITE_NVLD );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD               , 12  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_READ_NVLD );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID            , 13  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_ADDR_INVALID );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY               , 14  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_COMMAND_PARITY );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                  , 15  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_GENERAL_TIMEOUT );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PU_N2_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( PEC_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                   , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PCB_WDATA_PARITY );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY                 , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_PARITY );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY             , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_DL_RETURN_P0                       , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_P0 );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_UL_RDATA_PARITY                    , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UL_RDATA_PARITY );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_UL_P0                              , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UL_P0      );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE        , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE              , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH    , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH    , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD                , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_WRITE_NVLD );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD                 , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_READ_NVLD );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID              , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_ADDR_INVALID );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY                 , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PCB_COMMAND_PARITY );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                    , 15  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_GENERAL_TIMEOUT );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PEC_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                 , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_WDATA_PARITY );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY               , 1   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_PARITY );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY           , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_DL_RETURN_P0                     , 3   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_P0 );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_UL_RDATA_PARITY                  , 4   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_UL_RDATA_PARITY );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_UL_P0                            , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_UL_P0      );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE      , 6   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE            , 7   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH  , 8   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH  , 10  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD              , 11  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_WRITE_NVLD );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD               , 12  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_READ_NVLD );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID            , 13  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_ADDR_INVALID );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY               , 14  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_PCB_COMMAND_PARITY );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                  , 15  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_GENERAL_TIMEOUT );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PU_N0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( PU_N3_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR     , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR );
+REG64_FLD( PU_N3_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR    , 1   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR );
+REG64_FLD( PU_N3_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR        , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR );
+REG64_FLD( PU_N3_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR );
+REG64_FLD( PU_N3_PSCOM_MODE_REG_WATCHDOG_ENABLE                    , 4   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_WATCHDOG_ENABLE );
+REG64_FLD( PU_N3_PSCOM_MODE_REG_SCOM_HANG_LIMIT                    , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT );
+REG64_FLD( PU_N3_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT_LEN );
+REG64_FLD( PU_N3_PSCOM_MODE_REG_FORCE_ALL_RINGS                    , 7   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ALL_RINGS );
+REG64_FLD( PU_N3_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE );
+REG64_FLD( PU_N3_PSCOM_MODE_REG_RESERVED_LT                        , 9   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT );
+REG64_FLD( PU_N3_PSCOM_MODE_REG_RESERVED_LT_LEN                    , 3   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT_LEN );
+
+REG64_FLD( PU_N1_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR     , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR );
+REG64_FLD( PU_N1_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR    , 1   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR );
+REG64_FLD( PU_N1_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR        , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR );
+REG64_FLD( PU_N1_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR );
+REG64_FLD( PU_N1_PSCOM_MODE_REG_WATCHDOG_ENABLE                    , 4   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_WATCHDOG_ENABLE );
+REG64_FLD( PU_N1_PSCOM_MODE_REG_SCOM_HANG_LIMIT                    , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT );
+REG64_FLD( PU_N1_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT_LEN );
+REG64_FLD( PU_N1_PSCOM_MODE_REG_FORCE_ALL_RINGS                    , 7   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ALL_RINGS );
+REG64_FLD( PU_N1_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE );
+REG64_FLD( PU_N1_PSCOM_MODE_REG_RESERVED_LT                        , 9   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT );
+REG64_FLD( PU_N1_PSCOM_MODE_REG_RESERVED_LT_LEN                    , 3   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT_LEN );
+
+REG64_FLD( PU_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR );
+REG64_FLD( PU_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR       , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR );
+REG64_FLD( PU_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR           , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR );
+REG64_FLD( PU_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR );
+REG64_FLD( PU_PSCOM_MODE_REG_WATCHDOG_ENABLE                       , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WATCHDOG_ENABLE );
+REG64_FLD( PU_PSCOM_MODE_REG_SCOM_HANG_LIMIT                       , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT );
+REG64_FLD( PU_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                   , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT_LEN );
+REG64_FLD( PU_PSCOM_MODE_REG_FORCE_ALL_RINGS                       , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ALL_RINGS );
+REG64_FLD( PU_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE );
+REG64_FLD( PU_PSCOM_MODE_REG_RESERVED_LT                           , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT );
+REG64_FLD( PU_PSCOM_MODE_REG_RESERVED_LT_LEN                       , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT_LEN );
+
+REG64_FLD( PU_N2_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR     , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR );
+REG64_FLD( PU_N2_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR    , 1   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR );
+REG64_FLD( PU_N2_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR        , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR );
+REG64_FLD( PU_N2_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR );
+REG64_FLD( PU_N2_PSCOM_MODE_REG_WATCHDOG_ENABLE                    , 4   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_WATCHDOG_ENABLE );
+REG64_FLD( PU_N2_PSCOM_MODE_REG_SCOM_HANG_LIMIT                    , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT );
+REG64_FLD( PU_N2_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT_LEN );
+REG64_FLD( PU_N2_PSCOM_MODE_REG_FORCE_ALL_RINGS                    , 7   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ALL_RINGS );
+REG64_FLD( PU_N2_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE );
+REG64_FLD( PU_N2_PSCOM_MODE_REG_RESERVED_LT                        , 9   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT );
+REG64_FLD( PU_N2_PSCOM_MODE_REG_RESERVED_LT_LEN                    , 3   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT_LEN );
+
+REG64_FLD( PEC_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR       , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR );
+REG64_FLD( PEC_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR      , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR );
+REG64_FLD( PEC_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR          , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR );
+REG64_FLD( PEC_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR );
+REG64_FLD( PEC_PSCOM_MODE_REG_WATCHDOG_ENABLE                      , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_WATCHDOG_ENABLE );
+REG64_FLD( PEC_PSCOM_MODE_REG_SCOM_HANG_LIMIT                      , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT );
+REG64_FLD( PEC_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                  , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT_LEN );
+REG64_FLD( PEC_PSCOM_MODE_REG_FORCE_ALL_RINGS                      , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ALL_RINGS );
+REG64_FLD( PEC_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE );
+REG64_FLD( PEC_PSCOM_MODE_REG_RESERVED_LT                          , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT );
+REG64_FLD( PEC_PSCOM_MODE_REG_RESERVED_LT_LEN                      , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT_LEN );
+
+REG64_FLD( PU_N0_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR     , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR );
+REG64_FLD( PU_N0_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR    , 1   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR );
+REG64_FLD( PU_N0_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR        , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR );
+REG64_FLD( PU_N0_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR );
+REG64_FLD( PU_N0_PSCOM_MODE_REG_WATCHDOG_ENABLE                    , 4   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_WATCHDOG_ENABLE );
+REG64_FLD( PU_N0_PSCOM_MODE_REG_SCOM_HANG_LIMIT                    , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT );
+REG64_FLD( PU_N0_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT_LEN );
+REG64_FLD( PU_N0_PSCOM_MODE_REG_FORCE_ALL_RINGS                    , 7   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ALL_RINGS );
+REG64_FLD( PU_N0_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE );
+REG64_FLD( PU_N0_PSCOM_MODE_REG_RESERVED_LT                        , 9   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT );
+REG64_FLD( PU_N0_PSCOM_MODE_REG_RESERVED_LT_LEN                    , 3   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT_LEN );
+
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_WDATA_PARITY );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0   , 3   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_P0 );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_RDATA_PARITY );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0          , 5   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_P0 );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6   , SH_UNT_PU_N3    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT_PU_N3    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_PU_N3    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT_PU_N3    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_GENERAL_TIMEOUT );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_PU_N3    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_PU_N3    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY   , 18  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_WDATA_PARITY );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_ADDRESS_PARITY );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0       , 21  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_P0 );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY    , 22  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_RDATA_PARITY );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0              , 23  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_P0 );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26  , SH_UNT_PU_N3    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27  , SH_UNT_PU_N3    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28  , SH_UNT_PU_N3    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_READ_NVLD );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_COMMAND_PARITY );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT    , 33  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_GENERAL_TIMEOUT );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34  , SH_UNT_PU_N3    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35  , SH_UNT_PU_N3    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_WDATA_PARITY );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0   , 3   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_P0 );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_RDATA_PARITY );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0          , 5   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_P0 );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6   , SH_UNT_PU_N1    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT_PU_N1    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_PU_N1    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT_PU_N1    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_GENERAL_TIMEOUT );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_PU_N1    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_PU_N1    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY   , 18  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_WDATA_PARITY );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_ADDRESS_PARITY );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0       , 21  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_P0 );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY    , 22  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_RDATA_PARITY );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0              , 23  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_P0 );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26  , SH_UNT_PU_N1    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27  , SH_UNT_PU_N1    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28  , SH_UNT_PU_N1    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_READ_NVLD );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_COMMAND_PARITY );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT    , 33  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_GENERAL_TIMEOUT );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34  , SH_UNT_PU_N1    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35  , SH_UNT_PU_N1    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY  , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_WDATA_PARITY );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0      , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_P0 );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY   , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_RDATA_PARITY );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0             , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_P0 );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT   , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_GENERAL_TIMEOUT );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY      , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_WDATA_PARITY );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY    , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_ADDRESS_PARITY );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0          , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_P0 );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY       , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_RDATA_PARITY );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0                 , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_P0 );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27  , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD   , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD    , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_READ_NVLD );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY    , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_COMMAND_PARITY );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT       , 33  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_GENERAL_TIMEOUT );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34  , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35  , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_WDATA_PARITY );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0   , 3   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_P0 );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_RDATA_PARITY );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0          , 5   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_P0 );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6   , SH_UNT_PU_N2    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT_PU_N2    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_PU_N2    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT_PU_N2    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_GENERAL_TIMEOUT );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_PU_N2    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_PU_N2    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY   , 18  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_WDATA_PARITY );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_ADDRESS_PARITY );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0       , 21  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_P0 );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY    , 22  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_RDATA_PARITY );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0              , 23  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_P0 );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26  , SH_UNT_PU_N2    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27  , SH_UNT_PU_N2    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28  , SH_UNT_PU_N2    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_READ_NVLD );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_COMMAND_PARITY );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT    , 33  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_GENERAL_TIMEOUT );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34  , SH_UNT_PU_N2    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35  , SH_UNT_PU_N2    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_WDATA_PARITY );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0     , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_P0 );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY  , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_RDATA_PARITY );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0            , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_P0 );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6   , SH_UNT_PEC      ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT_PEC      ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_PEC      ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT_PEC      ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT  , 15  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_GENERAL_TIMEOUT );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_PEC      ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_PEC      ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY     , 18  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_WDATA_PARITY );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY   , 19  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_ADDRESS_PARITY );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0         , 21  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_P0 );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY      , 22  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_RDATA_PARITY );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0                , 23  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_P0 );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26  , SH_UNT_PEC      ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27  , SH_UNT_PEC      ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28  , SH_UNT_PEC      ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD  , 29  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD   , 30  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_READ_NVLD );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY   , 32  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_COMMAND_PARITY );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT      , 33  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_GENERAL_TIMEOUT );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34  , SH_UNT_PEC      ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35  , SH_UNT_PEC      ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_WDATA_PARITY );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0   , 3   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_P0 );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_RDATA_PARITY );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0          , 5   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_P0 );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6   , SH_UNT_PU_N0    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT_PU_N0    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_PU_N0    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT_PU_N0    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_GENERAL_TIMEOUT );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_PU_N0    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_PU_N0    ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY   , 18  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_WDATA_PARITY );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_ADDRESS_PARITY );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0       , 21  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_P0 );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY    , 22  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_RDATA_PARITY );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0              , 23  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_P0 );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26  , SH_UNT_PU_N0    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27  , SH_UNT_PU_N0    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28  , SH_UNT_PU_N0    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_READ_NVLD );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_COMMAND_PARITY );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT    , 33  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_GENERAL_TIMEOUT );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34  , SH_UNT_PU_N0    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35  , SH_UNT_PU_N0    ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ERR_BITS               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIHB2FSP_INJ_ERR_BITS );
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ERR_BITS_LEN           , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIHB2FSP_INJ_ERR_BITS_LEN );
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ONCE                   , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIHB2FSP_INJ_ONCE );
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_CONST                  , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIHB2FSP_INJ_CONST );
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_ERR_BITS                , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIHB2PB_INJ_ERR_BITS );
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_ERR_BITS_LEN            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIHB2PB_INJ_ERR_BITS_LEN );
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_ONCE                    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIHB2PB_INJ_ONCE );
+REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_CONST                   , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIHB2PB_INJ_CONST );
+REG64_FLD( PU_PSIHB_DEBUG_REG_TRACE_SEL                            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SEL  );
+REG64_FLD( PU_PSIHB_DEBUG_REG_TRACE_SEL_LEN                        , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SEL_LEN );
+
+REG64_FLD( PU_PSIHB_ERROR_MASK_REG_DISABLE_1                       , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_1  );
+REG64_FLD( PU_PSIHB_ERROR_MASK_REG_DISABLE_1_LEN                   , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_1_LEN );
+REG64_FLD( PU_PSIHB_ERROR_MASK_REG_INTERRUPT_DISABLE               , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_DISABLE );
+REG64_FLD( PU_PSIHB_ERROR_MASK_REG_INTERRUPT_DISABLE_LEN           , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_DISABLE_LEN );
+REG64_FLD( PU_PSIHB_ERROR_MASK_REG_DISABLE_2                       , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_2  );
+REG64_FLD( PU_PSIHB_ERROR_MASK_REG_DISABLE_2_LEN                   , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_2_LEN );
+
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PB_ECC_ERR_CE                  , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PB_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PB_ECC_ERR_UE                  , 1   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PB_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PB_ECC_ERR_SUE                 , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PB_ECC_ERR_SUE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT_FROM_ERROR           , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_FROM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT_FROM_FSP             , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_FROM_FSP );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_FSP_ECC_ERR_CE                 , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_FSP_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_FSP_ECC_ERR_UE                 , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_FSP_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_ERROR_STATE                    , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_STATE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INVALID_TTYPE                  , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INVALID_TTYPE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INVALID_CRESP                  , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INVALID_CRESP );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PB_DATA_TIME_OUT               , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PB_DATA_TIME_OUT );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PB_PARITY_ERROR                , 11  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PB_PARITY_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_FSP_ACCESS_TRUSTED_SPACE       , 12  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_FSP_ACCESS_TRUSTED_SPACE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_UNEXPECTED_PB                  , 13  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UNEXPECTED_PB );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT_CHANGE_WHILE_ACTIVE  , 14  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT0_ADDRESS_ERROR       , 15  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT0_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT1_ADDRESS_ERROR       , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT1_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT2_ADDRESS_ERROR       , 17  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT2_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT3_ADDRESS_ERROR       , 18  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT3_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT4_ADDRESS_ERROR       , 19  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT4_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT5_ADDRESS_ERROR       , 20  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT5_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_TCBR_TP_PSI_GLB_ERR_0          , 21  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_TCBR_TP_PSI_GLB_ERR_0 );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_TCBR_TP_PSI_GLB_ERR_1          , 22  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_TCBR_TP_PSI_GLB_ERR_1 );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_UPSTREAM                       , 23  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UPSTREAM   );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_SPARE                          , 24  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_SPARE_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_SCOM_ERROR                     , 27  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PARITY_ERROR                   , 28  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PB_ECC_ERR_CE                  , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PB_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PB_ECC_ERR_UE                  , 1   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PB_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PB_ECC_ERR_SUE                 , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PB_ECC_ERR_SUE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT_FROM_ERROR           , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_FROM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT_FROM_FSP             , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_FROM_FSP );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_FSP_ECC_ERR_CE                 , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_FSP_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_FSP_ECC_ERR_UE                 , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_FSP_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_ERROR_STATE                    , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_STATE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INVALID_TTYPE                  , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INVALID_TTYPE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INVALID_CRESP                  , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INVALID_CRESP );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PB_DATA_TIME_OUT               , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PB_DATA_TIME_OUT );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PB_PARITY_ERROR                , 11  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PB_PARITY_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_FSP_ACCESS_TRUSTED_SPACE       , 12  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_FSP_ACCESS_TRUSTED_SPACE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_UNEXPECTED_PB                  , 13  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UNEXPECTED_PB );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT_CHANGE_WHILE_ACTIVE  , 14  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT0_ADDRESS_ERROR       , 15  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT0_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT1_ADDRESS_ERROR       , 16  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT1_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT2_ADDRESS_ERROR       , 17  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT2_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT3_ADDRESS_ERROR       , 18  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT3_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT4_ADDRESS_ERROR       , 19  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT4_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT5_ADDRESS_ERROR       , 20  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT5_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_TCBR_TP_PSI_GLB_ERR_0          , 21  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_TCBR_TP_PSI_GLB_ERR_0 );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_TCBR_TP_PSI_GLB_ERR_1          , 22  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_TCBR_TP_PSI_GLB_ERR_1 );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_UPSTREAM                       , 23  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_UPSTREAM   );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_SPARE                          , 24  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_SPARE_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_SCOM_ERROR                     , 27  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PARITY_ERROR                   , 28  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_PB_ECC_ERR_CE                     , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_PB_ECC_ERR_UE                     , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_PB_ECC_ERR_SUE                    , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_ECC_ERR_SUE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT_FROM_ERROR              , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_FROM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT_FROM_FSP                , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_FROM_FSP );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_FSP_ECC_ERR_CE                    , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FSP_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_FSP_ECC_ERR_UE                    , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FSP_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_ERROR_STATE                       , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ERROR_STATE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INVALID_TTYPE                     , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INVALID_TTYPE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INVALID_CRESP                     , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INVALID_CRESP );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_PB_DATA_TIME_OUT                  , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_DATA_TIME_OUT );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_PB_PARITY_ERROR                   , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_PARITY_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_FSP_ACCESS_TRUSTED_SPACE          , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FSP_ACCESS_TRUSTED_SPACE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_UNEXPECTED_PB                     , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UNEXPECTED_PB );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT_CHANGE_WHILE_ACTIVE     , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT0_ADDRESS_ERROR          , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT0_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT1_ADDRESS_ERROR          , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT1_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT2_ADDRESS_ERROR          , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT2_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT3_ADDRESS_ERROR          , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT3_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT4_ADDRESS_ERROR          , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT4_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT5_ADDRESS_ERROR          , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT5_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_TCBR_TP_PSI_GLB_ERR_0             , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_TCBR_TP_PSI_GLB_ERR_0 );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_TCBR_TP_PSI_GLB_ERR_1             , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_TCBR_TP_PSI_GLB_ERR_1 );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_UPSTREAM                          , 23  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UPSTREAM   );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_SPARE                             , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_SPARE_LEN                         , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_SCOM_ERROR                        , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_MASK_REG_PARITY_ERROR                      , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_PSIHB_FIR_REG_PB_ECC_ERR_CE                          , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_REG_PB_ECC_ERR_UE                          , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_REG_PB_ECC_ERR_SUE                         , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_ECC_ERR_SUE );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT_FROM_ERROR                   , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_FROM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT_FROM_FSP                     , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_FROM_FSP );
+REG64_FLD( PU_PSIHB_FIR_REG_FSP_ECC_ERR_CE                         , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FSP_ECC_ERR_CE );
+REG64_FLD( PU_PSIHB_FIR_REG_FSP_ECC_ERR_UE                         , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FSP_ECC_ERR_UE );
+REG64_FLD( PU_PSIHB_FIR_REG_ERROR_STATE                            , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_ERROR_STATE );
+REG64_FLD( PU_PSIHB_FIR_REG_INVALID_TTYPE                          , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INVALID_TTYPE );
+REG64_FLD( PU_PSIHB_FIR_REG_INVALID_CRESP                          , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INVALID_CRESP );
+REG64_FLD( PU_PSIHB_FIR_REG_PB_DATA_TIME_OUT                       , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_DATA_TIME_OUT );
+REG64_FLD( PU_PSIHB_FIR_REG_PB_PARITY_ERROR                        , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PB_PARITY_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_FSP_ACCESS_TRUSTED_SPACE               , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_FSP_ACCESS_TRUSTED_SPACE );
+REG64_FLD( PU_PSIHB_FIR_REG_UNEXPECTED_PB                          , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UNEXPECTED_PB );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT_CHANGE_WHILE_ACTIVE          , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT0_ADDRESS_ERROR               , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT0_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT1_ADDRESS_ERROR               , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT1_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT2_ADDRESS_ERROR               , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT2_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT3_ADDRESS_ERROR               , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT3_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT4_ADDRESS_ERROR               , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT4_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT5_ADDRESS_ERROR               , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INTERRUPT5_ADDRESS_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_TCBR_TP_PSI_GLB_ERR_0                  , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_TCBR_TP_PSI_GLB_ERR_0 );
+REG64_FLD( PU_PSIHB_FIR_REG_TCBR_TP_PSI_GLB_ERR_1                  , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_TCBR_TP_PSI_GLB_ERR_1 );
+REG64_FLD( PU_PSIHB_FIR_REG_UPSTREAM                               , 23  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UPSTREAM   );
+REG64_FLD( PU_PSIHB_FIR_REG_SPARE                                  , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_PSIHB_FIR_REG_SPARE_LEN                              , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_PSIHB_FIR_REG_SCOM_ERROR                             , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERROR );
+REG64_FLD( PU_PSIHB_FIR_REG_PARITY_ERROR                           , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARITY_ERROR );
+
+REG64_FLD( PU_PSIHB_INTERRUPT_CONTROL_ESB_OR_LSI_INTERRUPTS        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ESB_OR_LSI_INTERRUPTS );
+REG64_FLD( PU_PSIHB_INTERRUPT_CONTROL_SM_RESET                     , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SM_RESET   );
+
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_CMD_ENABLE                  , 0   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_FSP_CMD_ENABLE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_ENABLE                 , 1   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_FSP_MMIO_ENABLE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PHBCSR_SPARE                    , 2   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PHBCSR_SPARE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_INT_ENABLE                  , 3   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_FSP_INT_ENABLE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_ERR_RSP_ENABLE              , 4   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_FSP_ERR_RSP_ENABLE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_LINK_ENABLE                 , 5   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSI_LINK_ENABLE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_RESET                       , 6   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_FSP_RESET  );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIHBC_RESET                    , 7   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSIHBC_RESET );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_MASK                   , 8   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_FSP_MMIO_MASK );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_MASK_LEN               , 4   , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_FSP_MMIO_MASK_LEN );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_CEC_PSI_INTERRUPT               , 16  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_CEC_PSI_INTERRUPT );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_INTERRUPT                   , 17  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_FSP_INTERRUPT );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_LINK_ACTIVE                 , 18  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_FSP_LINK_ACTIVE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_OUTBOUND_ACTIVE             , 19  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_FSP_OUTBOUND_ACTIVE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_INBOUND_ACTIVE              , 20  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_FSP_INBOUND_ACTIVE );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_LOAD_OUTSTANDING         , 21  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSIFSP_LOAD_OUTSTANDING );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_DMAR_OUTSTANDING         , 22  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSIFSP_DMAR_OUTSTANDING );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_INT_BUSY                 , 23  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSIFSP_INT_BUSY );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_XMIT_ERROR                  , 32  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSI_XMIT_ERROR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_LINK_INACTIVE_TRANS         , 33  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSI_LINK_INACTIVE_TRANS );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_ACK_TIMEOUT              , 34  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSIFSP_ACK_TIMEOUT );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_LOAD_TIMEOUT        , 35  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSIFSP_MMIO_LOAD_TIMEOUT );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_LENGTH_ERR          , 36  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSIFSP_MMIO_LENGTH_ERR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_ADDR_ERR            , 37  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSIFSP_MMIO_ADDR_ERR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_TYPE_ERR            , 38  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSIFSP_MMIO_TYPE_ERR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_UE                          , 39  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSI_UE     );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_PERR                     , 40  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSIFSP_PERR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_ALERT1                      , 41  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSI_ALERT1 );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_ALERT2                      , 42  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSI_ALERT2 );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_DMA_ERR                  , 43  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSIFSP_DMA_ERR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_DMA_ADDR_ERR             , 48  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSIFSP_DMA_ADDR_ERR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_TCE_EXTENT_ERR           , 49  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSIFSP_TCE_EXTENT_ERR );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_PAGE_FAULT               , 50  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSIFSP_PAGE_FAULT );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_INV_OP                   , 51  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_PSIFSP_INV_OP );
+REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_INV_READ                    , 52  , SH_UNT          , SH_ACS_SCOM2    ,
+           SH_FLD_FSP_INV_READ );
+
+REG64_FLD( PU_PSI_BRIDGE_BAR_REG_BAR                               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR        );
+REG64_FLD( PU_PSI_BRIDGE_BAR_REG_BAR_LEN                           , 36  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR_LEN    );
+REG64_FLD( PU_PSI_BRIDGE_BAR_REG_EN                                , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EN         );
+
+REG64_FLD( PU_PSI_BRIDGE_FSP_BAR_REG_BAR                           , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR        );
+REG64_FLD( PU_PSI_BRIDGE_FSP_BAR_REG_BAR_LEN                       , 36  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR_LEN    );
+
+REG64_FLD( PU_PSI_FSP_MMR_REG_MMR                                  , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MMR        );
+REG64_FLD( PU_PSI_FSP_MMR_REG_MMR_LEN                              , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MMR_LEN    );
+
+REG64_FLD( PU_PSI_TCE_ADDR_REG_ADDR                                , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR       );
+REG64_FLD( PU_PSI_TCE_ADDR_REG_ADDR_LEN                            , 34  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_PSI_TCE_ADDR_REG_ENTRIES                             , 61  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENTRIES    );
+REG64_FLD( PU_PSI_TCE_ADDR_REG_ENTRIES_LEN                         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENTRIES_LEN );
+
+REG64_FLD( CAPP_PSLTTMAP0_VALID                                    , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_VALID      );
+REG64_FLD( CAPP_PSLTTMAP0_TTYPE_MATCH                              , 1   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_MATCH );
+REG64_FLD( CAPP_PSLTTMAP0_TTYPE_MATCH_LEN                          , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_MATCH_LEN );
+REG64_FLD( CAPP_PSLTTMAP0_TSIZE_MATCH                              , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MATCH );
+REG64_FLD( CAPP_PSLTTMAP0_TSIZE_MATCH_LEN                          , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MATCH_LEN );
+REG64_FLD( CAPP_PSLTTMAP0_TSIZE_MASK                               , 13  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MASK );
+REG64_FLD( CAPP_PSLTTMAP0_TSIZE_MASK_LEN                           , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MASK_LEN );
+REG64_FLD( CAPP_PSLTTMAP0_TTYPE_REPLACE                            , 20  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_REPLACE );
+REG64_FLD( CAPP_PSLTTMAP0_TTYPE_REPLACE_LEN                        , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_REPLACE_LEN );
+
+REG64_FLD( CAPP_PSLTTMAP1_VALID                                    , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_VALID      );
+REG64_FLD( CAPP_PSLTTMAP1_TTYPE_MATCH                              , 1   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_MATCH );
+REG64_FLD( CAPP_PSLTTMAP1_TTYPE_MATCH_LEN                          , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_MATCH_LEN );
+REG64_FLD( CAPP_PSLTTMAP1_TSIZE_MATCH                              , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MATCH );
+REG64_FLD( CAPP_PSLTTMAP1_TSIZE_MATCH_LEN                          , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MATCH_LEN );
+REG64_FLD( CAPP_PSLTTMAP1_TSIZE_MASK                               , 13  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MASK );
+REG64_FLD( CAPP_PSLTTMAP1_TSIZE_MASK_LEN                           , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MASK_LEN );
+REG64_FLD( CAPP_PSLTTMAP1_TTYPE_REPLACE                            , 20  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_REPLACE );
+REG64_FLD( CAPP_PSLTTMAP1_TTYPE_REPLACE_LEN                        , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_REPLACE_LEN );
+
+REG64_FLD( CAPP_PSLTTMAP2_VALID                                    , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_VALID      );
+REG64_FLD( CAPP_PSLTTMAP2_TTYPE_MATCH                              , 1   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_MATCH );
+REG64_FLD( CAPP_PSLTTMAP2_TTYPE_MATCH_LEN                          , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_MATCH_LEN );
+REG64_FLD( CAPP_PSLTTMAP2_TSIZE_MATCH                              , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MATCH );
+REG64_FLD( CAPP_PSLTTMAP2_TSIZE_MATCH_LEN                          , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MATCH_LEN );
+REG64_FLD( CAPP_PSLTTMAP2_TSIZE_MASK                               , 13  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MASK );
+REG64_FLD( CAPP_PSLTTMAP2_TSIZE_MASK_LEN                           , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MASK_LEN );
+REG64_FLD( CAPP_PSLTTMAP2_TTYPE_REPLACE                            , 20  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_REPLACE );
+REG64_FLD( CAPP_PSLTTMAP2_TTYPE_REPLACE_LEN                        , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_REPLACE_LEN );
+
+REG64_FLD( CAPP_PSLTTMAP3_VALID                                    , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_VALID      );
+REG64_FLD( CAPP_PSLTTMAP3_TTYPE_MATCH                              , 1   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_MATCH );
+REG64_FLD( CAPP_PSLTTMAP3_TTYPE_MATCH_LEN                          , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_MATCH_LEN );
+REG64_FLD( CAPP_PSLTTMAP3_TSIZE_MATCH                              , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MATCH );
+REG64_FLD( CAPP_PSLTTMAP3_TSIZE_MATCH_LEN                          , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MATCH_LEN );
+REG64_FLD( CAPP_PSLTTMAP3_TSIZE_MASK                               , 13  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MASK );
+REG64_FLD( CAPP_PSLTTMAP3_TSIZE_MASK_LEN                           , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TSIZE_MASK_LEN );
+REG64_FLD( CAPP_PSLTTMAP3_TTYPE_REPLACE                            , 20  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_REPLACE );
+REG64_FLD( CAPP_PSLTTMAP3_TTYPE_REPLACE_LEN                        , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TTYPE_REPLACE_LEN );
+
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_0                              , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_0          );
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_1                              , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_1          );
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_2                              , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_2          );
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_3                              , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_3          );
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_4                              , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_4          );
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_5                              , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_5          );
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_6                              , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_6          );
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_7                              , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_7          );
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_8                              , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_8          );
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_9                              , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_9          );
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_10                             , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_10         );
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_11                             , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_11         );
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_12                             , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_12         );
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_13                             , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_13         );
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_14                             , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_14         );
+REG64_FLD( PU_PSU_HOST_DOORBELL_REG_15                             , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_15         );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX0_REG_MBOX0                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX0      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX0_REG_MBOX0_LEN                     , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX0_LEN  );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX1_REG_MBOX1                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX1      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX1_REG_MBOX1_LEN                     , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX1_LEN  );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX2_REG_MBOX2                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX2      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX2_REG_MBOX2_LEN                     , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX2_LEN  );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX3_REG_MBOX3                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX3      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX3_REG_MBOX3_LEN                     , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX3_LEN  );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX4_REG_MBOX4                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX4      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX4_REG_MBOX4_LEN                     , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX4_LEN  );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX5_REG_MBOX5                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX5      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX5_REG_MBOX5_LEN                     , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX5_LEN  );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX6_REG_MBOX6                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX6      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX6_REG_MBOX6_LEN                     , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX6_LEN  );
+
+REG64_FLD( PU_PSU_HOST_SBE_MBOX7_REG_MBOX7                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX7      );
+REG64_FLD( PU_PSU_HOST_SBE_MBOX7_REG_MBOX7_LEN                     , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MBOX7_LEN  );
+
+REG64_FLD( PU_PSU_INSTR0_ACTCYCLECNT_REG_ACTCYCLECNT               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACTCYCLECNT );
+REG64_FLD( PU_PSU_INSTR0_ACTCYCLECNT_REG_ACTCYCLECNT_LEN           , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACTCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR0_CYCLECNT_REG_CYCLECNT                     , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CYCLECNT   );
+REG64_FLD( PU_PSU_INSTR0_CYCLECNT_REG_CYCLECNT_LEN                 , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR0_EVENTCNT_REG_EVENTCNT                     , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENTCNT   );
+REG64_FLD( PU_PSU_INSTR0_EVENTCNT_REG_EVENTCNT_LEN                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENTCNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR0_FILTER_REG_CONTENT                        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CONTENT    );
+REG64_FLD( PU_PSU_INSTR0_FILTER_REG_CONTENT_LEN                    , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CONTENT_LEN );
+REG64_FLD( PU_PSU_INSTR0_FILTER_REG_MASK                           , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASK       );
+REG64_FLD( PU_PSU_INSTR0_FILTER_REG_MASK_LEN                       , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( PU_PSU_INSTR0_MAXCYCLECNT_REG_MAXCYCLECNT               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAXCYCLECNT );
+REG64_FLD( PU_PSU_INSTR0_MAXCYCLECNT_REG_MAXCYCLECNT_LEN           , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAXCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR0_MINCYCLECNT_REG_MINCYCLECNT               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MINCYCLECNT );
+REG64_FLD( PU_PSU_INSTR0_MINCYCLECNT_REG_MINCYCLECNT_LEN           , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MINCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR0_STOP_TIMER_REG_TIMER                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMER      );
+REG64_FLD( PU_PSU_INSTR0_STOP_TIMER_REG_TIMER_LEN                  , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_LEN  );
+
+REG64_FLD( PU_PSU_INSTR1_ACTCYCLECNT_REG_ACTCYCLECNT               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACTCYCLECNT );
+REG64_FLD( PU_PSU_INSTR1_ACTCYCLECNT_REG_ACTCYCLECNT_LEN           , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACTCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR1_CYCLECNT_REG_CYCLECNT                     , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CYCLECNT   );
+REG64_FLD( PU_PSU_INSTR1_CYCLECNT_REG_CYCLECNT_LEN                 , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR1_EVENTCNT_REG_EVENTCNT                     , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENTCNT   );
+REG64_FLD( PU_PSU_INSTR1_EVENTCNT_REG_EVENTCNT_LEN                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENTCNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR1_FILTER_REG_CONTENT                        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CONTENT    );
+REG64_FLD( PU_PSU_INSTR1_FILTER_REG_CONTENT_LEN                    , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CONTENT_LEN );
+REG64_FLD( PU_PSU_INSTR1_FILTER_REG_MASK                           , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASK       );
+REG64_FLD( PU_PSU_INSTR1_FILTER_REG_MASK_LEN                       , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( PU_PSU_INSTR1_MAXCYCLECNT_REG_MAXCYCLECNT               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAXCYCLECNT );
+REG64_FLD( PU_PSU_INSTR1_MAXCYCLECNT_REG_MAXCYCLECNT_LEN           , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAXCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR1_MINCYCLECNT_REG_MINCYCLECNT               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MINCYCLECNT );
+REG64_FLD( PU_PSU_INSTR1_MINCYCLECNT_REG_MINCYCLECNT_LEN           , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MINCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR1_STOP_TIMER_REG_TIMER                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMER      );
+REG64_FLD( PU_PSU_INSTR1_STOP_TIMER_REG_TIMER_LEN                  , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_LEN  );
+
+REG64_FLD( PU_PSU_INSTR2_ACTCYCLECNT_REG_ACTCYCLECNT               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACTCYCLECNT );
+REG64_FLD( PU_PSU_INSTR2_ACTCYCLECNT_REG_ACTCYCLECNT_LEN           , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ACTCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR2_CYCLECNT_REG_CYCLECNT                     , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CYCLECNT   );
+REG64_FLD( PU_PSU_INSTR2_CYCLECNT_REG_CYCLECNT_LEN                 , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR2_EVENTCNT_REG_EVENTCNT                     , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENTCNT   );
+REG64_FLD( PU_PSU_INSTR2_EVENTCNT_REG_EVENTCNT_LEN                 , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EVENTCNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR2_FILTER_REG_CONTENT                        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CONTENT    );
+REG64_FLD( PU_PSU_INSTR2_FILTER_REG_CONTENT_LEN                    , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CONTENT_LEN );
+REG64_FLD( PU_PSU_INSTR2_FILTER_REG_MASK                           , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASK       );
+REG64_FLD( PU_PSU_INSTR2_FILTER_REG_MASK_LEN                       , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( PU_PSU_INSTR2_MAXCYCLECNT_REG_MAXCYCLECNT               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAXCYCLECNT );
+REG64_FLD( PU_PSU_INSTR2_MAXCYCLECNT_REG_MAXCYCLECNT_LEN           , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAXCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR2_MINCYCLECNT_REG_MINCYCLECNT               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MINCYCLECNT );
+REG64_FLD( PU_PSU_INSTR2_MINCYCLECNT_REG_MINCYCLECNT_LEN           , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MINCYCLECNT_LEN );
+
+REG64_FLD( PU_PSU_INSTR2_STOP_TIMER_REG_TIMER                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMER      );
+REG64_FLD( PU_PSU_INSTR2_STOP_TIMER_REG_TIMER_LEN                  , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_LEN  );
+
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_MODE                , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR0_MODE );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_MODE_LEN            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR0_MODE_LEN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP_TIMER_EN       , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR0_STOP_TIMER_EN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP_ON_ERROR_GT    , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR0_STOP_ON_ERROR_GT );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP_ON_ERROR_GT_LEN , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR0_STOP_ON_ERROR_GT_LEN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_START               , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR0_START );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP                , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR0_STOP );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_MODE                , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR1_MODE );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_MODE_LEN            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR1_MODE_LEN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP_TIMER_EN       , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR1_STOP_TIMER_EN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP_ON_ERROR_GT    , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR1_STOP_ON_ERROR_GT );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP_ON_ERROR_GT_LEN , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR1_STOP_ON_ERROR_GT_LEN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_START               , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR1_START );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP                , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR1_STOP );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_MODE                , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR2_MODE );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_MODE_LEN            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR2_MODE_LEN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP_TIMER_EN       , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR2_STOP_TIMER_EN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP_ON_ERROR_GT    , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR2_STOP_ON_ERROR_GT );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP_ON_ERROR_GT_LEN , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR2_STOP_ON_ERROR_GT_LEN );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_START               , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR2_START );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP                , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR2_STOP );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_CYCLECNT_RUNNING    , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR0_CYCLECNT_RUNNING );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_BUSYCNT_RUNNING     , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR0_BUSYCNT_RUNNING );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_CYCLECNT_RUNNING    , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR1_CYCLECNT_RUNNING );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_BUSYCNT_RUNNING     , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR1_BUSYCNT_RUNNING );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_CYCLECNT_RUNNING    , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR2_CYCLECNT_RUNNING );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_BUSYCNT_RUNNING     , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR2_BUSYCNT_RUNNING );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOPPED_ON_ERROR    , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR0_STOPPED_ON_ERROR );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOPPED_ON_ERROR    , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR1_STOPPED_ON_ERROR );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOPPED_ON_ERROR    , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR2_STOPPED_ON_ERROR );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_RESET               , 33  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR0_RESET );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_RESET               , 34  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR1_RESET );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_RESET               , 35  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INSTR2_RESET );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INCLUDE_TRAFFIC            , 36  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INCLUDE_TRAFFIC );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_RESERVED                   , 37  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_RESERVED_LEN               , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+
+REG64_FLD( PU_PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG_HIST              , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST       );
+REG64_FLD( PU_PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG_HIST_LEN          , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_LEN   );
+
+REG64_FLD( PU_PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG_HIST           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST       );
+REG64_FLD( PU_PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG_HIST_LEN       , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_LEN   );
+
+REG64_FLD( PU_PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG_HIST           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST       );
+REG64_FLD( PU_PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG_HIST_LEN       , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_LEN   );
+
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_MANUAL_MODE_EN      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MANUAL_MODE_EN );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_START_NOT_STOP      , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_START_NOT_STOP );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_FREEZE_HISTORY      , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_FREEZE_HISTORY );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_RESET_HISTORY       , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_RESET_HISTORY );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_TRACE_TRAFFIC       , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_TRACE_TRAFFIC );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_STOP_ON_ERROR_GT    , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_STOP_ON_ERROR_GT );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_STOP_ON_ERROR_GT_LEN , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_STOP_ON_ERROR_GT_LEN );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_RESERVED            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_RESERVED );
+REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_RESERVED_LEN        , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_RESERVED_LEN );
+
+REG64_FLD( PU_PSU_PIBHIST_FILTER_REG_HIST_ADDRESS                  , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_ADDRESS );
+REG64_FLD( PU_PSU_PIBHIST_FILTER_REG_HIST_ADDRESS_LEN              , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_ADDRESS_LEN );
+REG64_FLD( PU_PSU_PIBHIST_FILTER_REG_HIST_MASK                     , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MASK  );
+REG64_FLD( PU_PSU_PIBHIST_FILTER_REG_HIST_MASK_LEN                 , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MASK_LEN );
+
+REG64_FLD( PU_PSU_PIBHIST_LAST_ADDR_TRACE_REG_HIST                 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST       );
+REG64_FLD( PU_PSU_PIBHIST_LAST_ADDR_TRACE_REG_HIST_LEN             , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_LEN   );
+
+REG64_FLD( PU_PSU_PIBHIST_LAST_REQDATA_TRACE_REG_HIST              , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST       );
+REG64_FLD( PU_PSU_PIBHIST_LAST_REQDATA_TRACE_REG_HIST_LEN          , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_LEN   );
+
+REG64_FLD( PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG_HIST              , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST       );
+REG64_FLD( PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG_HIST_LEN          , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HIST_LEN   );
+
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_0                               , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_0          );
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_1                               , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_1          );
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_2                               , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_2          );
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_3                               , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_3          );
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_4                               , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_4          );
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_5                               , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_5          );
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_6                               , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_6          );
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_7                               , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_7          );
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_8                               , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_8          );
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_9                               , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_9          );
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_10                              , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_10         );
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_11                              , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_11         );
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_12                              , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_12         );
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_13                              , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_13         );
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_14                              , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_14         );
+REG64_FLD( PU_PSU_SBE_DOORBELL_REG_15                              , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_15         );
+
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP0                 , 0   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP0 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP0_LEN             , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP0_LEN );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP1                 , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP1 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP1_LEN             , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP1_LEN );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP2                 , 16  , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP2 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP2_LEN             , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP2_LEN );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP3                 , 24  , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP3 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP3_LEN             , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP3_LEN );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP4                 , 32  , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP4 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP4_LEN             , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP4_LEN );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP5                 , 40  , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP5 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP5_LEN             , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP5_LEN );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP6                 , 48  , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP6 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP6_LEN             , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP6_LEN );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP7                 , 56  , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP7 );
+REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP7_LEN             , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP7_LEN );
+
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP8                 , 0   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP8 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP8_LEN             , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP8_LEN );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP9                 , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP9 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP9_LEN             , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP9_LEN );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP10                , 16  , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP10 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP10_LEN            , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP10_LEN );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP11                , 24  , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP11 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP11_LEN            , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP11_LEN );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP12                , 32  , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP12 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP12_LEN            , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP12_LEN );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP13                , 40  , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP13 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP13_LEN            , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP13_LEN );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP14                , 48  , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP14 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP14_LEN            , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP14_LEN );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15                , 56  , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP15 );
+REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15_LEN            , 8   , SH_UNT          , SH_ACS_SCOM_WAND,
+           SH_FLD_MALF_ERR_FROM_GROUP15_LEN );
+
+REG64_FLD( PU_NPU0_REM0_IBUF_WSRC                                  , 17  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_WSRC  );
+REG64_FLD( PU_NPU0_REM0_IBUF_WSRC_LEN                              , 5   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_WSRC_LEN );
+REG64_FLD( PU_NPU0_REM0_IBUF_RSRC                                  , 22  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_RSRC  );
+REG64_FLD( PU_NPU0_REM0_IBUF_RSRC_LEN                              , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_RSRC_LEN );
+REG64_FLD( PU_NPU0_REM0_IBUF_AIDX                                  , 24  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_AIDX  );
+REG64_FLD( PU_NPU0_REM0_IBUF_AIDX_LEN                              , 8   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_AIDX_LEN );
+REG64_FLD( PU_NPU0_REM0_IBUF_ABANK                                 , 32  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_ABANK );
+REG64_FLD( PU_NPU0_REM0_IBUF_ABANK_LEN                             , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_ABANK_LEN );
+REG64_FLD( PU_NPU0_REM0_OBUF_WSRC                                  , 34  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_WSRC  );
+REG64_FLD( PU_NPU0_REM0_OBUF_WSRC_LEN                              , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_WSRC_LEN );
+REG64_FLD( PU_NPU0_REM0_OBUF_RSRC                                  , 36  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_RSRC  );
+REG64_FLD( PU_NPU0_REM0_OBUF_RSRC_LEN                              , 6   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_RSRC_LEN );
+REG64_FLD( PU_NPU0_REM0_OBUF_AIDX                                  , 42  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_AIDX  );
+REG64_FLD( PU_NPU0_REM0_OBUF_AIDX_LEN                              , 8   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_AIDX_LEN );
+REG64_FLD( PU_NPU0_REM0_OBUF_ABANK                                 , 50  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_ABANK );
+REG64_FLD( PU_NPU0_REM0_OBUF_ABANK_LEN                             , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_ABANK_LEN );
+REG64_FLD( PU_NPU0_REM0_BBUF_WSRC                                  , 52  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_WSRC  );
+REG64_FLD( PU_NPU0_REM0_BBUF_WSRC_LEN                              , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_WSRC_LEN );
+REG64_FLD( PU_NPU0_REM0_BBUF_RSRC                                  , 54  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_RSRC  );
+REG64_FLD( PU_NPU0_REM0_BBUF_RSRC_LEN                              , 2   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_RSRC_LEN );
+REG64_FLD( PU_NPU0_REM0_BBUF_AIDX                                  , 56  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_AIDX  );
+REG64_FLD( PU_NPU0_REM0_BBUF_AIDX_LEN                              , 8   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_AIDX_LEN );
+
+REG64_FLD( PU_NPU1_REM0_IBUF_WSRC                                  , 17  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_WSRC  );
+REG64_FLD( PU_NPU1_REM0_IBUF_WSRC_LEN                              , 5   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_WSRC_LEN );
+REG64_FLD( PU_NPU1_REM0_IBUF_RSRC                                  , 22  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_RSRC  );
+REG64_FLD( PU_NPU1_REM0_IBUF_RSRC_LEN                              , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_RSRC_LEN );
+REG64_FLD( PU_NPU1_REM0_IBUF_AIDX                                  , 24  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_AIDX  );
+REG64_FLD( PU_NPU1_REM0_IBUF_AIDX_LEN                              , 8   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_AIDX_LEN );
+REG64_FLD( PU_NPU1_REM0_IBUF_ABANK                                 , 32  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_ABANK );
+REG64_FLD( PU_NPU1_REM0_IBUF_ABANK_LEN                             , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_ABANK_LEN );
+REG64_FLD( PU_NPU1_REM0_OBUF_WSRC                                  , 34  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_WSRC  );
+REG64_FLD( PU_NPU1_REM0_OBUF_WSRC_LEN                              , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_WSRC_LEN );
+REG64_FLD( PU_NPU1_REM0_OBUF_RSRC                                  , 36  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_RSRC  );
+REG64_FLD( PU_NPU1_REM0_OBUF_RSRC_LEN                              , 6   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_RSRC_LEN );
+REG64_FLD( PU_NPU1_REM0_OBUF_AIDX                                  , 42  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_AIDX  );
+REG64_FLD( PU_NPU1_REM0_OBUF_AIDX_LEN                              , 8   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_AIDX_LEN );
+REG64_FLD( PU_NPU1_REM0_OBUF_ABANK                                 , 50  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_ABANK );
+REG64_FLD( PU_NPU1_REM0_OBUF_ABANK_LEN                             , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_ABANK_LEN );
+REG64_FLD( PU_NPU1_REM0_BBUF_WSRC                                  , 52  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_WSRC  );
+REG64_FLD( PU_NPU1_REM0_BBUF_WSRC_LEN                              , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_WSRC_LEN );
+REG64_FLD( PU_NPU1_REM0_BBUF_RSRC                                  , 54  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_RSRC  );
+REG64_FLD( PU_NPU1_REM0_BBUF_RSRC_LEN                              , 2   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_RSRC_LEN );
+REG64_FLD( PU_NPU1_REM0_BBUF_AIDX                                  , 56  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_AIDX  );
+REG64_FLD( PU_NPU1_REM0_BBUF_AIDX_LEN                              , 8   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_AIDX_LEN );
+
+REG64_FLD( PU_NPU2_REM0_IBUF_WSRC                                  , 17  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_WSRC  );
+REG64_FLD( PU_NPU2_REM0_IBUF_WSRC_LEN                              , 5   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_WSRC_LEN );
+REG64_FLD( PU_NPU2_REM0_IBUF_RSRC                                  , 22  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_RSRC  );
+REG64_FLD( PU_NPU2_REM0_IBUF_RSRC_LEN                              , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_RSRC_LEN );
+REG64_FLD( PU_NPU2_REM0_IBUF_AIDX                                  , 24  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_AIDX  );
+REG64_FLD( PU_NPU2_REM0_IBUF_AIDX_LEN                              , 8   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_AIDX_LEN );
+REG64_FLD( PU_NPU2_REM0_IBUF_ABANK                                 , 32  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_ABANK );
+REG64_FLD( PU_NPU2_REM0_IBUF_ABANK_LEN                             , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IBUF_ABANK_LEN );
+REG64_FLD( PU_NPU2_REM0_OBUF_WSRC                                  , 34  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_WSRC  );
+REG64_FLD( PU_NPU2_REM0_OBUF_WSRC_LEN                              , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_WSRC_LEN );
+REG64_FLD( PU_NPU2_REM0_OBUF_RSRC                                  , 36  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_RSRC  );
+REG64_FLD( PU_NPU2_REM0_OBUF_RSRC_LEN                              , 6   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_RSRC_LEN );
+REG64_FLD( PU_NPU2_REM0_OBUF_AIDX                                  , 42  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_AIDX  );
+REG64_FLD( PU_NPU2_REM0_OBUF_AIDX_LEN                              , 8   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_AIDX_LEN );
+REG64_FLD( PU_NPU2_REM0_OBUF_ABANK                                 , 50  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_ABANK );
+REG64_FLD( PU_NPU2_REM0_OBUF_ABANK_LEN                             , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_OBUF_ABANK_LEN );
+REG64_FLD( PU_NPU2_REM0_BBUF_WSRC                                  , 52  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_WSRC  );
+REG64_FLD( PU_NPU2_REM0_BBUF_WSRC_LEN                              , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_WSRC_LEN );
+REG64_FLD( PU_NPU2_REM0_BBUF_RSRC                                  , 54  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_RSRC  );
+REG64_FLD( PU_NPU2_REM0_BBUF_RSRC_LEN                              , 2   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_RSRC_LEN );
+REG64_FLD( PU_NPU2_REM0_BBUF_AIDX                                  , 56  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_AIDX  );
+REG64_FLD( PU_NPU2_REM0_BBUF_AIDX_LEN                              , 8   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_BBUF_AIDX_LEN );
+
+REG64_FLD( PU_NPU0_REM1_PBRX_RTAG                                  , 34  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_PBRX_RTAG  );
+REG64_FLD( PU_NPU0_REM1_PBRX_RTAG_LEN                              , 22  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_PBRX_RTAG_LEN );
+REG64_FLD( PU_NPU0_REM1_ALU_ADR                                    , 56  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_ADR    );
+REG64_FLD( PU_NPU0_REM1_ALU_ADR_LEN                                , 3   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_ADR_LEN );
+REG64_FLD( PU_NPU0_REM1_ALU_TYPE                                   , 59  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_TYPE   );
+REG64_FLD( PU_NPU0_REM1_ALU_TYPE_LEN                               , 4   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_TYPE_LEN );
+REG64_FLD( PU_NPU0_REM1_ALU_SZ                                     , 63  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_SZ     );
+
+REG64_FLD( PU_NPU1_REM1_PBRX_RTAG                                  , 34  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_PBRX_RTAG  );
+REG64_FLD( PU_NPU1_REM1_PBRX_RTAG_LEN                              , 22  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_PBRX_RTAG_LEN );
+REG64_FLD( PU_NPU1_REM1_ALU_ADR                                    , 56  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_ADR    );
+REG64_FLD( PU_NPU1_REM1_ALU_ADR_LEN                                , 3   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_ADR_LEN );
+REG64_FLD( PU_NPU1_REM1_ALU_TYPE                                   , 59  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_TYPE   );
+REG64_FLD( PU_NPU1_REM1_ALU_TYPE_LEN                               , 4   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_TYPE_LEN );
+REG64_FLD( PU_NPU1_REM1_ALU_SZ                                     , 63  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_SZ     );
+
+REG64_FLD( PU_NPU2_REM1_PBRX_RTAG                                  , 34  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_PBRX_RTAG  );
+REG64_FLD( PU_NPU2_REM1_PBRX_RTAG_LEN                              , 22  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_PBRX_RTAG_LEN );
+REG64_FLD( PU_NPU2_REM1_ALU_ADR                                    , 56  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_ADR    );
+REG64_FLD( PU_NPU2_REM1_ALU_ADR_LEN                                , 3   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_ADR_LEN );
+REG64_FLD( PU_NPU2_REM1_ALU_TYPE                                   , 59  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_TYPE   );
+REG64_FLD( PU_NPU2_REM1_ALU_TYPE_LEN                               , 4   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_TYPE_LEN );
+REG64_FLD( PU_NPU2_REM1_ALU_SZ                                     , 63  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_ALU_SZ     );
+
+REG64_FLD( PU_RESET_REGISTER_CHICKEN_SWITCH                        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHICKEN_SWITCH );
+
+REG64_FLD( PU_RESET_REGISTER_B_CHKSW_AR012_0                       , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHKSW_AR012_0 );
+
+REG64_FLD( PU_RESET_REGISTER_C_CHKSW_AR012_1                       , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHKSW_AR012_1 );
+
+REG64_FLD( PU_RESET_REGISTER_D_CHKSW_AR012_2                       , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHKSW_AR012_2 );
+
+REG64_FLD( PU_RESET_REGISTER_E_CHKSW_AR012_3                       , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHKSW_AR012_3 );
+
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_RESID_FE_LEN_0  , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESID_FE_LEN_0 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_RESID_FE_LEN_0_LEN , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESID_FE_LEN_0_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_PEEK_DATA1_0    , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_PEEK_DATA1_0_LEN , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_LBUS_PARITY_ERR1_0 , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_RESID_FE_LEN_1  , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESID_FE_LEN_1 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_RESID_FE_LEN_1_LEN , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESID_FE_LEN_1_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_PEEK_DATA1_1    , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_PEEK_DATA1_1_LEN , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_LBUS_PARITY_ERR1_1 , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_RESID_FE_LEN_2  , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESID_FE_LEN_2 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_RESID_FE_LEN_2_LEN , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESID_FE_LEN_2_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_PEEK_DATA1_2    , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_PEEK_DATA1_2_LEN , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_LBUS_PARITY_ERR1_2 , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_RESID_FE_LEN_3  , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESID_FE_LEN_3 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_RESID_FE_LEN_3_LEN , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESID_FE_LEN_3_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_PEEK_DATA1_3    , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_PEEK_DATA1_3_LEN , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_LBUS_PARITY_ERR1_3 , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PEC_RFIR_IN0                                            , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( PEC_RFIR_LFIR_RECOV_ERR                                 , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_LFIR_RECOV_ERR );
+REG64_FLD( PEC_RFIR_IN4                                            , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( PEC_RFIR_IN5                                            , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( PEC_RFIR_IN6                                            , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN6        );
+REG64_FLD( PEC_RFIR_IN6_LEN                                        , 20  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN6_LEN    );
+
+REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_DISABLED                , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED   );
+REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE                  , 1   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN              , 15  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_DISABLED                , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED   );
+REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE                  , 1   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN              , 15  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( PU_RING_FENCE_MASK_LATCH_REG_DISABLED                   , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED   );
+REG64_FLD( PU_RING_FENCE_MASK_LATCH_REG_ENABLE                     , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN                 , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_DISABLED                , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED   );
+REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE                  , 1   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN              , 15  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_DISABLED                  , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED   );
+REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_ENABLE                    , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN                , 15  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_DISABLED                , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED   );
+REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE                  , 1   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN              , 15  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK0_CLUSTER                      , 0   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK0_CLUSTER );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK0_CLUSTER_LEN                  , 3   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK0_CLUSTER_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK1_CLUSTER                      , 3   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK1_CLUSTER );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK1_CLUSTER_LEN                  , 3   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK1_CLUSTER_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK2_CLUSTER                      , 6   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK2_CLUSTER );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK2_CLUSTER_LEN                  , 3   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK2_CLUSTER_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK3_CLUSTER                      , 9   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK3_CLUSTER );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK3_CLUSTER_LEN                  , 3   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK3_CLUSTER_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK4_CLUSTER                      , 12  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK4_CLUSTER );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK4_CLUSTER_LEN                  , 3   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK4_CLUSTER_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK5_CLUSTER                      , 15  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK5_CLUSTER );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK5_CLUSTER_LEN                  , 3   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_BRK5_CLUSTER_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_RESERVED1                         , 18  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_RESERVED1_LEN                     , 2   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_SYNC_BRK                          , 20  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SYNC_BRK   );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_SYNC_BRK_LEN                      , 6   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_SYNC_BRK_LEN );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_IDIAL_ISSYNC                      , 26  , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_ISSYNC );
+REG64_FLD( PU_NPU_CTL_RLX_CONFIG_IDIAL_ISSYNC_LEN                  , 6   , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_ISSYNC_LEN );
+
+REG64_FLD( PU_RNG_FAILED_INT_ENABLE                                , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_RNG_FAILED_INT_ADDRESS                               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_RNG_FAILED_INT_ADDRESS_LEN                           , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_RESERVED1                       , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_RESERVED1_LEN                   , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_START                           , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_START_LEN                       , 9   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_RESERVED2                       , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_RESERVED2_LEN                   , 3   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_END                             , 15  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_END_LEN                         , 9   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( NV_RSP_DA_PTR_RESERVED1                                 , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( NV_RSP_DA_PTR_RESERVED1_LEN                             , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( NV_RSP_DA_PTR_START                                     , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( NV_RSP_DA_PTR_START_LEN                                 , 9   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( NV_RSP_DA_PTR_RESERVED2                                 , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( NV_RSP_DA_PTR_RESERVED2_LEN                             , 3   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( NV_RSP_DA_PTR_END                                       , 15  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( NV_RSP_DA_PTR_END_LEN                                   , 9   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_RESERVED1                       , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_RESERVED1_LEN                   , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_START                           , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_START_LEN                       , 9   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_RESERVED2                       , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_RESERVED2_LEN                   , 3   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_END                             , 15  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_END_LEN                         , 9   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_RESERVED1                       , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_RESERVED1_LEN                   , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_START                           , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_START_LEN                       , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_RESERVED2                       , 12  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_RESERVED2_LEN                   , 5   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_END                             , 17  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_END_LEN                         , 7   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( NV_RSP_HA_PTR_RESERVED1                                 , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( NV_RSP_HA_PTR_RESERVED1_LEN                             , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( NV_RSP_HA_PTR_START                                     , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( NV_RSP_HA_PTR_START_LEN                                 , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( NV_RSP_HA_PTR_RESERVED2                                 , 12  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( NV_RSP_HA_PTR_RESERVED2_LEN                             , 5   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( NV_RSP_HA_PTR_END                                       , 17  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( NV_RSP_HA_PTR_END_LEN                                   , 7   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_RESERVED1                       , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_RESERVED1_LEN                   , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1_LEN );
+REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_START                           , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_START      );
+REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_START_LEN                       , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_START_LEN  );
+REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_RESERVED2                       , 12  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2  );
+REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_RESERVED2_LEN                   , 5   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED2_LEN );
+REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_END                             , 17  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_END        );
+REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_END_LEN                         , 7   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_END_LEN    );
+
+REG64_FLD( PU_RX_CTRL_STAT_REG_ENABLE_SCWR_TO_RXRF                 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_SCWR_TO_RXRF );
+REG64_FLD( PU_RX_CTRL_STAT_REG_DISABLE_ECC_COR_RXRF_PSI            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_ECC_COR_RXRF_PSI );
+REG64_FLD( PU_RX_CTRL_STAT_REG_CRC_MODE                            , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CRC_MODE   );
+REG64_FLD( PU_RX_CTRL_STAT_REG_ENABLE_SCRD_FR_RXRF                 , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_SCRD_FR_RXRF );
+REG64_FLD( PU_RX_CTRL_STAT_REG_ENABLE_STREAMING_MODE               , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_STREAMING_MODE );
+REG64_FLD( PU_RX_CTRL_STAT_REG_CHIP_INTERFACEMODE                  , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHIP_INTERFACEMODE );
+REG64_FLD( PU_RX_CTRL_STAT_REG_CHIP_PERSONALISATION                , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHIP_PERSONALISATION );
+
+REG64_FLD( PU_RX_MASK_REG_PSIRXINS_RFGSHIFT_PCK                    , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXINS_RFGSHIFT_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXINS_RZRTMP_PCK                      , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXINS_RZRTMP_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXINS_DATA_PCK                        , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXINS_DATA_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXEI_SHIFT_PCK                        , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXEI_SHIFT_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXEI_TRANSMIT_PCK                     , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXEI_TRANSMIT_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXINS_OVERRUN                         , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXINS_OVERRUN );
+REG64_FLD( PU_RX_MASK_REG_PSIRXBFF_DATA_PCK                        , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXBFF_DATA_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXBFF_DATAO_PCK                       , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXBFF_DATAO_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXBFF_RFC_PCK                         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXBFF_RFC_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_FSM_PCK                          , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXLC_FSM_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_DATA_BUFF_PCK                    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXLC_DATA_BUFF_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_DATA_PCK                         , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXLC_DATA_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_RADDR_PCK                        , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXLC_RADDR_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_RCTRL_PCK                        , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXLC_RCTRL_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_UE_RF                            , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXLC_UE_RF );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_CE_RF                            , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXLC_CE_RF );
+REG64_FLD( PU_RX_MASK_REG_PSIRXLC_DATA_GXST1_PCK_2N                , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRXLC_DATA_GXST1_PCK_2N );
+REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RADDR_PCK                       , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRFACC_RADDR_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RCTRL_PCK                       , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRFACC_RCTRL_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RFSM_PCK                        , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRFACC_RFSM_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RDL_FSM_PCK                     , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRFACC_RDL_FSM_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RXSC_PCK                        , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRFACC_RXSC_PCK );
+REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RLINK_STATE_LT_02               , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRFACC_RLINK_STATE_LT_02 );
+REG64_FLD( PU_RX_MASK_REG_PSIRFACC_C_RXDATA_RDY_ERR                , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRFACC_C_RXDATA_RDY_ERR );
+
+REG64_FLD( PU_RX_PSI_CNTL_PATTERN_CHECK_EN                         , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERN_CHECK_EN );
+REG64_FLD( PU_RX_PSI_CNTL_PATTERN_SEL                              , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERN_SEL );
+REG64_FLD( PU_RX_PSI_CNTL_PATTERN_SEL_LEN                          , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERN_SEL_LEN );
+REG64_FLD( PU_RX_PSI_CNTL_CLK_INVERT                               , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CLK_INVERT );
+REG64_FLD( PU_RX_PSI_CNTL_LANE_INVERT                              , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( PU_RX_PSI_CNTL_PDWN                                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PDWN       );
+REG64_FLD( PU_RX_PSI_CNTL_CLK_DLY                                  , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CLK_DLY    );
+REG64_FLD( PU_RX_PSI_CNTL_CLK_DLY_LEN                              , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CLK_DLY_LEN );
+REG64_FLD( PU_RX_PSI_CNTL_DATA_DLY                                 , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_DLY   );
+REG64_FLD( PU_RX_PSI_CNTL_DATA_DLY_LEN                             , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_DLY_LEN );
+REG64_FLD( PU_RX_PSI_CNTL_DEGLITCH_CLK_DLY                         , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DEGLITCH_CLK_DLY );
+REG64_FLD( PU_RX_PSI_CNTL_DEGLITCH_CLK_DLY_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DEGLITCH_CLK_DLY_LEN );
+REG64_FLD( PU_RX_PSI_CNTL_DEGLITCH_DATA_DLY                        , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DEGLITCH_DATA_DLY );
+REG64_FLD( PU_RX_PSI_CNTL_DEGLITCH_DATA_DLY_LEN                    , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DEGLITCH_DATA_DLY_LEN );
+
+REG64_FLD( PU_RX_PSI_MODE_VREF                                     , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_VREF       );
+REG64_FLD( PU_RX_PSI_MODE_VREF_LEN                                 , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_VREF_LEN   );
+REG64_FLD( PU_RX_PSI_MODE_TERM_TEST                                , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TERM_TEST  );
+REG64_FLD( PU_RX_PSI_MODE_TERM_ENC                                 , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TERM_ENC   );
+REG64_FLD( PU_RX_PSI_MODE_TERM_ENC_LEN                             , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TERM_ENC_LEN );
+REG64_FLD( PU_RX_PSI_MODE_SPARE                                    , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_RX_PSI_MODE_SPARE_LEN                                , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_RX_PSI_STATUS_LD_UNLD_DLY                            , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LD_UNLD_DLY );
+REG64_FLD( PU_RX_PSI_STATUS_LD_UNLD_DLY_LEN                        , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LD_UNLD_DLY_LEN );
+REG64_FLD( PU_RX_PSI_STATUS_OVER_OR_UNDERRUN_ERR                   , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OVER_OR_UNDERRUN_ERR );
+REG64_FLD( PU_RX_PSI_STATUS_CLEAR                                  , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CLEAR      );
+REG64_FLD( PU_RX_PSI_STATUS_SPARE                                  , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_RX_PSI_STATUS_SPARE_LEN                              , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PEC_SCAN_REGION_TYPE_SYSTEM_FAST_INIT                   , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SYSTEM_FAST_INIT );
+REG64_FLD( PEC_SCAN_REGION_TYPE_VITL                               , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_VITL       );
+REG64_FLD( PEC_SCAN_REGION_TYPE_PERV                               , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT1                              , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT2                              , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT3                              , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT4                              , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT5                              , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT6                              , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT7                              , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT8                              , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT9                              , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT10                             , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( PEC_SCAN_REGION_TYPE_FUNC                               , 48  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FUNC       );
+REG64_FLD( PEC_SCAN_REGION_TYPE_CFG                                , 49  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CFG        );
+REG64_FLD( PEC_SCAN_REGION_TYPE_CCFG_GPTR                          , 50  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CCFG_GPTR  );
+REG64_FLD( PEC_SCAN_REGION_TYPE_REGF                               , 51  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_REGF       );
+REG64_FLD( PEC_SCAN_REGION_TYPE_LBIST                              , 52  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_LBIST      );
+REG64_FLD( PEC_SCAN_REGION_TYPE_ABIST                              , 53  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ABIST      );
+REG64_FLD( PEC_SCAN_REGION_TYPE_REPR                               , 54  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_REPR       );
+REG64_FLD( PEC_SCAN_REGION_TYPE_TIME                               , 55  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TIME       );
+REG64_FLD( PEC_SCAN_REGION_TYPE_BNDY                               , 56  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_BNDY       );
+REG64_FLD( PEC_SCAN_REGION_TYPE_FARR                               , 57  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FARR       );
+REG64_FLD( PEC_SCAN_REGION_TYPE_CMSK                               , 58  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CMSK       );
+REG64_FLD( PEC_SCAN_REGION_TYPE_INEX                               , 59  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_INEX       );
+
+REG64_FLD( PU_SCOM_PPE_CNTL_IORESET                                , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+REG64_FLD( PU_SCOM_PPE_CNTL_PDWN                                   , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PDWN       );
+REG64_FLD( PU_SCOM_PPE_CNTL_INTERRUPT                              , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT  );
+REG64_FLD( PU_SCOM_PPE_CNTL_ARB_ECC_INJECT_ERR                     , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ARB_ECC_INJECT_ERR );
+REG64_FLD( PU_SCOM_PPE_CNTL_SPARES                                 , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARES     );
+REG64_FLD( PU_SCOM_PPE_CNTL_SPARES_LEN                             , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARES_LEN );
+
+REG64_FLD( PU_SCOM_PPE_FLAGS_FIELD                                 , 0   , SH_UNT          , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FIELD      );
+REG64_FLD( PU_SCOM_PPE_FLAGS_FIELD_LEN                             , 16  , SH_UNT          , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FIELD_LEN  );
+
+REG64_FLD( PU_SCOM_PPE_WORK_REG1_WORK1                             , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WORK1      );
+REG64_FLD( PU_SCOM_PPE_WORK_REG1_WORK1_LEN                         , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WORK1_LEN  );
+
+REG64_FLD( PU_SCOM_PPE_WORK_REG2_WORK2                             , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WORK2      );
+REG64_FLD( PU_SCOM_PPE_WORK_REG2_WORK2_LEN                         , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WORK2_LEN  );
+
+REG64_FLD( PU_NPU0_SCRATCH0_IDIAL                                  , 0   , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_SCRATCH0_IDIAL_LEN                              , 64  , SH_UNT_PU_NPU0  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_SCRATCH0_SCRATCH_N                                   , 0   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_SCRATCH_N  );
+REG64_FLD( PU_SCRATCH0_SCRATCH_N_LEN                               , 64  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_SCRATCH_N_LEN );
+
+REG64_FLD( PU_NPU1_SCRATCH0_IDIAL                                  , 0   , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_SCRATCH0_IDIAL_LEN                              , 64  , SH_UNT_PU_NPU1  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_SCRATCH0_IDIAL                                  , 0   , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_SCRATCH0_IDIAL_LEN                              , 64  , SH_UNT_PU_NPU2  , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL0_SCRATCH1_IDIAL                             , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL0_SCRATCH1_IDIAL_LEN                         , 64  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_SCRATCH1_SCRATCH_N                                   , 0   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_SCRATCH_N  );
+REG64_FLD( PU_SCRATCH1_SCRATCH_N_LEN                               , 64  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_SCRATCH_N_LEN );
+
+REG64_FLD( NV_SCRATCH1_IDIAL                                       , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( NV_SCRATCH1_IDIAL_LEN                                   , 64  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_DAT_SCRATCH1_IDIAL                              , 0   , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_DAT_SCRATCH1_IDIAL_LEN                          , 64  , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL1_SCRATCH1_IDIAL                             , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL1_SCRATCH1_IDIAL_LEN                         , 64  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU1_DAT_SCRATCH1_IDIAL                              , 0   , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU1_DAT_SCRATCH1_IDIAL_LEN                          , 64  , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU0_DAT_SCRATCH1_IDIAL                              , 0   , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU0_DAT_SCRATCH1_IDIAL_LEN                          , 64  , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL0_SCRATCH2_IDIAL                             , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL0_SCRATCH2_IDIAL_LEN                         , 64  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_SCRATCH2_SCRATCH_N                                   , 0   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_SCRATCH_N  );
+REG64_FLD( PU_SCRATCH2_SCRATCH_N_LEN                               , 64  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_SCRATCH_N_LEN );
+
+REG64_FLD( NV_SCRATCH2_IDIAL                                       , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( NV_SCRATCH2_IDIAL_LEN                                   , 64  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL1_SCRATCH2_IDIAL                             , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL1_SCRATCH2_IDIAL_LEN                         , 64  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL0_SCRATCH3_IDIAL                             , 0   , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL0_SCRATCH3_IDIAL_LEN                         , 64  , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_SCRATCH3_SCRATCH_N                                   , 0   , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_SCRATCH_N  );
+REG64_FLD( PU_SCRATCH3_SCRATCH_N_LEN                               , 64  , SH_UNT          , SH_ACS_PPE2     ,
+           SH_FLD_SCRATCH_N_LEN );
+
+REG64_FLD( NV_SCRATCH3_IDIAL                                       , 0   , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( NV_SCRATCH3_IDIAL_LEN                                   , 64  , SH_UNT_NV       , SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_NPU2_NTL1_SCRATCH3_IDIAL                             , 0   , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL      );
+REG64_FLD( PU_NPU2_NTL1_SCRATCH3_IDIAL_LEN                         , 64  , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM     ,
+           SH_FLD_IDIAL_LEN  );
+
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SECURE_ACCESS               , 0   , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_SECURE_ACCESS );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LATE_LAUNCH_PRIMARY         , 1   , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_LATE_LAUNCH_PRIMARY );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LATE_LAUNCH_SECONDARY       , 2   , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_LATE_LAUNCH_SECONDARY );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LOCAL_QUIESCE_ACHIEVED      , 3   , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_LOCAL_QUIESCE_ACHIEVED );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SEEPROM_UPDATE_LOCK         , 4   , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_SEEPROM_UPDATE_LOCK );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LOCALITY_4_ACCESS           , 5   , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_LOCALITY_4_ACCESS );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SECURE_DEBUG                , 6   , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_SECURE_DEBUG );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_CMFSI_ACCESS_PROTCT         , 7   , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_CMFSI_ACCESS_PROTCT );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_ABUS_LOCK                   , 8   , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_ABUS_LOCK  );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_NX_RAND_NUM_GEN_LOCK        , 9   , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_NX_RAND_NUM_GEN_LOCK );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_EX_SPARE0              , 10  , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_PROT_EX_SPARE0 );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_EX_SPARE1              , 11  , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_PROT_EX_SPARE1 );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_I2CM_TPM_DECONFIG_PROTECT   , 12  , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_I2CM_TPM_DECONFIG_PROTECT );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE0              , 13  , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_PROT_TP_SPARE0 );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE1              , 14  , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_PROT_TP_SPARE1 );
+REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE2              , 15  , SH_UNT          , SH_ACS_SCOM1    ,
+           SH_FLD_PROT_TP_SPARE2 );
+
+REG64_FLD( PU_SEND_WC_BASE_ADDR_BAR                                , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR        );
+REG64_FLD( PU_SEND_WC_BASE_ADDR_BAR_LEN                            , 33  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR_LEN    );
+
+REG64_FLD( PEC_SKITTER_CLKSRC_REG_SKITTER0                         , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0   );
+REG64_FLD( PEC_SKITTER_CLKSRC_REG_SKITTER0_LEN                     , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0_LEN );
+REG64_FLD( PEC_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT            , 36  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0_DELAY_SELECT );
+REG64_FLD( PEC_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN        , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0_DELAY_SELECT_LEN );
+
+REG64_FLD( PEC_SKITTER_FORCE_REG_F_READ                            , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_F_READ     );
+
+REG64_FLD( PEC_SKITTER_MODE_REG_HOLD_SAMPLE                        , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_SAMPLE );
+REG64_FLD( PEC_SKITTER_MODE_REG_DISABLE_STICKINESS                 , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_STICKINESS );
+REG64_FLD( PEC_SKITTER_MODE_REG_UNUSED1                            , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1    );
+REG64_FLD( PEC_SKITTER_MODE_REG_UNUSED1_LEN                        , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1_LEN );
+REG64_FLD( PEC_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL                   , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_DBGTRIG_SEL );
+REG64_FLD( PEC_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN               , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_DBGTRIG_SEL_LEN );
+REG64_FLD( PEC_SKITTER_MODE_REG_RESET_TRIG_SEL                     , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESET_TRIG_SEL );
+REG64_FLD( PEC_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN                 , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESET_TRIG_SEL_LEN );
+REG64_FLD( PEC_SKITTER_MODE_REG_SAMPLE_GUTS                        , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_GUTS );
+REG64_FLD( PEC_SKITTER_MODE_REG_SAMPLE_GUTS_LEN                    , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_GUTS_LEN );
+REG64_FLD( PEC_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER           , 44  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_SAMPLE_WITH_TRIGGER );
+REG64_FLD( PEC_SKITTER_MODE_REG_DATA_V_LT                          , 45  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DATA_V_LT  );
+
+REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK       , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK );
+REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN         , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_MALF_PULSE_GEN );
+REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP         , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP );
+REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK         , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK );
+REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT              , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_HEARTBEAT );
+REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO          , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_FORCE_TO_ZERO );
+REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_PM_DISABLE                     , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PM_DISABLE );
+REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE                 , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PM_MUX_DISABLE );
+REG64_FLD( PEC_SLAVE_CONFIG_REG_ERROR_MASK                         , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_MASK );
+REG64_FLD( PEC_SLAVE_CONFIG_REG_ERROR_MASK_LEN                     , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_MASK_LEN );
+
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_CREQ0                             , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CREQ0      );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_PRB0                              , 1   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PRB0       );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_CREQ1                             , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CREQ1      );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_PRB1                              , 3   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PRB1       );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_XATS                              , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_XATS       );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_PWR0                              , 5   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PWR0       );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_PWR1                              , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PWR1       );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_CHGRATE                           , 7   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CHGRATE    );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_MRBGP                             , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP      );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_MRBGP_LEN                         , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP_LEN  );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_MRBSP                             , 12  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP      );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_MRBSP_LEN                         , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP_LEN  );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE0                            , 16  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0     );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE0_LEN                        , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_LEN );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE1                            , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1     );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE1_LEN                        , 4   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_LEN );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBLN                              , 24  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PBLN       );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBNNG                             , 25  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PBNNG      );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBRNVG                            , 26  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PBRNVG     );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_N0REQ                             , 27  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N0REQ      );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_N0DGD                             , 28  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N0DGD      );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_N1REQ                             , 29  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N1REQ      );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_N1DGD                             , 30  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N1DGD      );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_MMIO                              , 31  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MMIO       );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_ATSXLATE                          , 32  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_ATSXLATE   );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBRSP                             , 33  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PBRSP      );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_N0RSP                             , 34  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N0RSP      );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_N1RSP                             , 35  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N1RSP      );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_XARSP                             , 36  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_XARSP      );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_SACOLL                            , 37  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_SACOLL     );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_FREE                              , 38  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FREE       );
+REG64_FLD( PU_NPU0_SM0_SM_STATUS_RESERVED1                         , 39  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_CREQ0                             , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CREQ0      );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_PRB0                              , 1   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PRB0       );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_CREQ1                             , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CREQ1      );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_PRB1                              , 3   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PRB1       );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_XATS                              , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_XATS       );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_PWR0                              , 5   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PWR0       );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_PWR1                              , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PWR1       );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_CHGRATE                           , 7   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CHGRATE    );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_MRBGP                             , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP      );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_MRBGP_LEN                         , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP_LEN  );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_MRBSP                             , 12  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP      );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_MRBSP_LEN                         , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP_LEN  );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE0                            , 16  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0     );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE0_LEN                        , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_LEN );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE1                            , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1     );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE1_LEN                        , 4   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_LEN );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBLN                              , 24  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PBLN       );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBNNG                             , 25  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PBNNG      );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBRNVG                            , 26  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PBRNVG     );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_N0REQ                             , 27  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N0REQ      );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_N0DGD                             , 28  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N0DGD      );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_N1REQ                             , 29  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N1REQ      );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_N1DGD                             , 30  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N1DGD      );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_MMIO                              , 31  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MMIO       );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_ATSXLATE                          , 32  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATSXLATE   );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBRSP                             , 33  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PBRSP      );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_N0RSP                             , 34  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N0RSP      );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_N1RSP                             , 35  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N1RSP      );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_XARSP                             , 36  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_XARSP      );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_SACOLL                            , 37  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_SACOLL     );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_FREE                              , 38  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FREE       );
+REG64_FLD( PU_NPU1_SM2_SM_STATUS_RESERVED1                         , 39  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_CREQ0                             , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CREQ0      );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_PRB0                              , 1   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PRB0       );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_CREQ1                             , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CREQ1      );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_PRB1                              , 3   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PRB1       );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_XATS                              , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_XATS       );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_PWR0                              , 5   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PWR0       );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_PWR1                              , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PWR1       );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_CHGRATE                           , 7   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CHGRATE    );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_MRBGP                             , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP      );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_MRBGP_LEN                         , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP_LEN  );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_MRBSP                             , 12  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP      );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_MRBSP_LEN                         , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP_LEN  );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE0                            , 16  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0     );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE0_LEN                        , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_LEN );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE1                            , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1     );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE1_LEN                        , 4   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_LEN );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBLN                              , 24  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PBLN       );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBNNG                             , 25  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PBNNG      );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBRNVG                            , 26  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PBRNVG     );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_N0REQ                             , 27  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N0REQ      );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_N0DGD                             , 28  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N0DGD      );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_N1REQ                             , 29  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N1REQ      );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_N1DGD                             , 30  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N1DGD      );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_MMIO                              , 31  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MMIO       );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_ATSXLATE                          , 32  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_ATSXLATE   );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBRSP                             , 33  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PBRSP      );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_N0RSP                             , 34  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N0RSP      );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_N1RSP                             , 35  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N1RSP      );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_XARSP                             , 36  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_XARSP      );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_SACOLL                            , 37  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_SACOLL     );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_FREE                              , 38  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FREE       );
+REG64_FLD( PU_NPU2_SM3_SM_STATUS_RESERVED1                         , 39  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_CREQ0                             , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CREQ0      );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_PRB0                              , 1   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PRB0       );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_CREQ1                             , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CREQ1      );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_PRB1                              , 3   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PRB1       );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_XATS                              , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_XATS       );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_PWR0                              , 5   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PWR0       );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_PWR1                              , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PWR1       );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_CHGRATE                           , 7   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CHGRATE    );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_MRBGP                             , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP      );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_MRBGP_LEN                         , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP_LEN  );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_MRBSP                             , 12  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP      );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_MRBSP_LEN                         , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP_LEN  );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE0                            , 16  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0     );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE0_LEN                        , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_LEN );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE1                            , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1     );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE1_LEN                        , 4   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_LEN );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBLN                              , 24  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PBLN       );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBNNG                             , 25  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PBNNG      );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBRNVG                            , 26  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PBRNVG     );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_N0REQ                             , 27  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N0REQ      );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_N0DGD                             , 28  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N0DGD      );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_N1REQ                             , 29  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N1REQ      );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_N1DGD                             , 30  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N1DGD      );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_MMIO                              , 31  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MMIO       );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_ATSXLATE                          , 32  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_ATSXLATE   );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBRSP                             , 33  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PBRSP      );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_N0RSP                             , 34  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N0RSP      );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_N1RSP                             , 35  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N1RSP      );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_XARSP                             , 36  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_XARSP      );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_SACOLL                            , 37  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_SACOLL     );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_FREE                              , 38  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FREE       );
+REG64_FLD( PU_NPU1_SM3_SM_STATUS_RESERVED1                         , 39  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_CREQ0                             , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CREQ0      );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_PRB0                              , 1   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PRB0       );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_CREQ1                             , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CREQ1      );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_PRB1                              , 3   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PRB1       );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_XATS                              , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_XATS       );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_PWR0                              , 5   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PWR0       );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_PWR1                              , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PWR1       );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_CHGRATE                           , 7   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CHGRATE    );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_MRBGP                             , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP      );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_MRBGP_LEN                         , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP_LEN  );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_MRBSP                             , 12  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP      );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_MRBSP_LEN                         , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP_LEN  );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE0                            , 16  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0     );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE0_LEN                        , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_LEN );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE1                            , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1     );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE1_LEN                        , 4   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_LEN );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBLN                              , 24  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PBLN       );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBNNG                             , 25  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PBNNG      );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBRNVG                            , 26  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PBRNVG     );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_N0REQ                             , 27  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N0REQ      );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_N0DGD                             , 28  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N0DGD      );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_N1REQ                             , 29  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N1REQ      );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_N1DGD                             , 30  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N1DGD      );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_MMIO                              , 31  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_MMIO       );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_ATSXLATE                          , 32  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_ATSXLATE   );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBRSP                             , 33  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_PBRSP      );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_N0RSP                             , 34  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N0RSP      );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_N1RSP                             , 35  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_N1RSP      );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_XARSP                             , 36  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_XARSP      );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_SACOLL                            , 37  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_SACOLL     );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_FREE                              , 38  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FREE       );
+REG64_FLD( PU_NPU0_SM3_SM_STATUS_RESERVED1                         , 39  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_CREQ0                             , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CREQ0      );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_PRB0                              , 1   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PRB0       );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_CREQ1                             , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CREQ1      );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_PRB1                              , 3   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PRB1       );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_XATS                              , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_XATS       );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_PWR0                              , 5   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PWR0       );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_PWR1                              , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PWR1       );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_CHGRATE                           , 7   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CHGRATE    );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_MRBGP                             , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP      );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_MRBGP_LEN                         , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP_LEN  );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_MRBSP                             , 12  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP      );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_MRBSP_LEN                         , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP_LEN  );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE0                            , 16  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0     );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE0_LEN                        , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_LEN );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE1                            , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1     );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE1_LEN                        , 4   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_LEN );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBLN                              , 24  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PBLN       );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBNNG                             , 25  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PBNNG      );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBRNVG                            , 26  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PBRNVG     );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_N0REQ                             , 27  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N0REQ      );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_N0DGD                             , 28  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N0DGD      );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_N1REQ                             , 29  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N1REQ      );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_N1DGD                             , 30  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N1DGD      );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_MMIO                              , 31  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MMIO       );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_ATSXLATE                          , 32  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_ATSXLATE   );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBRSP                             , 33  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PBRSP      );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_N0RSP                             , 34  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N0RSP      );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_N1RSP                             , 35  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N1RSP      );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_XARSP                             , 36  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_XARSP      );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_SACOLL                            , 37  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_SACOLL     );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_FREE                              , 38  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FREE       );
+REG64_FLD( PU_NPU1_SM1_SM_STATUS_RESERVED1                         , 39  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_CREQ0                             , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CREQ0      );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_PRB0                              , 1   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PRB0       );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_CREQ1                             , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CREQ1      );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_PRB1                              , 3   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PRB1       );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_XATS                              , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_XATS       );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_PWR0                              , 5   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PWR0       );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_PWR1                              , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PWR1       );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_CHGRATE                           , 7   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CHGRATE    );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_MRBGP                             , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP      );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_MRBGP_LEN                         , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP_LEN  );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_MRBSP                             , 12  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP      );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_MRBSP_LEN                         , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP_LEN  );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE0                            , 16  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0     );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE0_LEN                        , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_LEN );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE1                            , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1     );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE1_LEN                        , 4   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_LEN );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBLN                              , 24  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PBLN       );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBNNG                             , 25  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PBNNG      );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBRNVG                            , 26  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PBRNVG     );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_N0REQ                             , 27  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N0REQ      );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_N0DGD                             , 28  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N0DGD      );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_N1REQ                             , 29  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N1REQ      );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_N1DGD                             , 30  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N1DGD      );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_MMIO                              , 31  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MMIO       );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_ATSXLATE                          , 32  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATSXLATE   );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBRSP                             , 33  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PBRSP      );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_N0RSP                             , 34  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N0RSP      );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_N1RSP                             , 35  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N1RSP      );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_XARSP                             , 36  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_XARSP      );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_SACOLL                            , 37  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_SACOLL     );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_FREE                              , 38  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FREE       );
+REG64_FLD( PU_NPU2_SM2_SM_STATUS_RESERVED1                         , 39  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_CREQ0                             , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CREQ0      );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_PRB0                              , 1   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PRB0       );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_CREQ1                             , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CREQ1      );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_PRB1                              , 3   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PRB1       );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_XATS                              , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_XATS       );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_PWR0                              , 5   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PWR0       );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_PWR1                              , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PWR1       );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_CHGRATE                           , 7   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CHGRATE    );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_MRBGP                             , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP      );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_MRBGP_LEN                         , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP_LEN  );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_MRBSP                             , 12  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP      );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_MRBSP_LEN                         , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP_LEN  );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE0                            , 16  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0     );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE0_LEN                        , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_LEN );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE1                            , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1     );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE1_LEN                        , 4   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_LEN );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBLN                              , 24  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PBLN       );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBNNG                             , 25  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PBNNG      );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBRNVG                            , 26  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PBRNVG     );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_N0REQ                             , 27  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N0REQ      );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_N0DGD                             , 28  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N0DGD      );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_N1REQ                             , 29  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N1REQ      );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_N1DGD                             , 30  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N1DGD      );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_MMIO                              , 31  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MMIO       );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_ATSXLATE                          , 32  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_ATSXLATE   );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBRSP                             , 33  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PBRSP      );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_N0RSP                             , 34  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N0RSP      );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_N1RSP                             , 35  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N1RSP      );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_XARSP                             , 36  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_XARSP      );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_SACOLL                            , 37  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_SACOLL     );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_FREE                              , 38  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FREE       );
+REG64_FLD( PU_NPU2_SM1_SM_STATUS_RESERVED1                         , 39  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_CREQ0                             , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CREQ0      );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_PRB0                              , 1   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PRB0       );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_CREQ1                             , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CREQ1      );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_PRB1                              , 3   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PRB1       );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_XATS                              , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_XATS       );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_PWR0                              , 5   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PWR0       );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_PWR1                              , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PWR1       );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_CHGRATE                           , 7   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CHGRATE    );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_MRBGP                             , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP      );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_MRBGP_LEN                         , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP_LEN  );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_MRBSP                             , 12  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP      );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_MRBSP_LEN                         , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP_LEN  );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE0                            , 16  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0     );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE0_LEN                        , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_LEN );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE1                            , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1     );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE1_LEN                        , 4   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_LEN );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBLN                              , 24  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PBLN       );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBNNG                             , 25  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PBNNG      );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBRNVG                            , 26  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PBRNVG     );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_N0REQ                             , 27  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N0REQ      );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_N0DGD                             , 28  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N0DGD      );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_N1REQ                             , 29  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N1REQ      );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_N1DGD                             , 30  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N1DGD      );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_MMIO                              , 31  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MMIO       );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_ATSXLATE                          , 32  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATSXLATE   );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBRSP                             , 33  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PBRSP      );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_N0RSP                             , 34  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N0RSP      );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_N1RSP                             , 35  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_N1RSP      );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_XARSP                             , 36  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_XARSP      );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_SACOLL                            , 37  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_SACOLL     );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_FREE                              , 38  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FREE       );
+REG64_FLD( PU_NPU0_SM2_SM_STATUS_RESERVED1                         , 39  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_CREQ0                             , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CREQ0      );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_PRB0                              , 1   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PRB0       );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_CREQ1                             , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CREQ1      );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_PRB1                              , 3   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PRB1       );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_XATS                              , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_XATS       );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_PWR0                              , 5   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PWR0       );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_PWR1                              , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PWR1       );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_CHGRATE                           , 7   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CHGRATE    );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_MRBGP                             , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP      );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_MRBGP_LEN                         , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP_LEN  );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_MRBSP                             , 12  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP      );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_MRBSP_LEN                         , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP_LEN  );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE0                            , 16  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0     );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE0_LEN                        , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_LEN );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE1                            , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1     );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE1_LEN                        , 4   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_LEN );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBLN                              , 24  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PBLN       );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBNNG                             , 25  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PBNNG      );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBRNVG                            , 26  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PBRNVG     );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_N0REQ                             , 27  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N0REQ      );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_N0DGD                             , 28  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N0DGD      );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_N1REQ                             , 29  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N1REQ      );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_N1DGD                             , 30  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N1DGD      );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_MMIO                              , 31  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MMIO       );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_ATSXLATE                          , 32  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_ATSXLATE   );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBRSP                             , 33  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PBRSP      );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_N0RSP                             , 34  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N0RSP      );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_N1RSP                             , 35  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N1RSP      );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_XARSP                             , 36  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_XARSP      );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_SACOLL                            , 37  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_SACOLL     );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_FREE                              , 38  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FREE       );
+REG64_FLD( PU_NPU2_SM0_SM_STATUS_RESERVED1                         , 39  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_CREQ0                             , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CREQ0      );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_PRB0                              , 1   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PRB0       );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_CREQ1                             , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CREQ1      );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_PRB1                              , 3   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PRB1       );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_XATS                              , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_XATS       );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_PWR0                              , 5   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PWR0       );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_PWR1                              , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PWR1       );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_CHGRATE                           , 7   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CHGRATE    );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_MRBGP                             , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP      );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_MRBGP_LEN                         , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP_LEN  );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_MRBSP                             , 12  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP      );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_MRBSP_LEN                         , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP_LEN  );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE0                            , 16  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0     );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE0_LEN                        , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_LEN );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE1                            , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1     );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE1_LEN                        , 4   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_LEN );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBLN                              , 24  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PBLN       );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBNNG                             , 25  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PBNNG      );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBRNVG                            , 26  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PBRNVG     );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_N0REQ                             , 27  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N0REQ      );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_N0DGD                             , 28  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N0DGD      );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_N1REQ                             , 29  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N1REQ      );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_N1DGD                             , 30  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N1DGD      );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_MMIO                              , 31  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_MMIO       );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_ATSXLATE                          , 32  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_ATSXLATE   );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBRSP                             , 33  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_PBRSP      );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_N0RSP                             , 34  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N0RSP      );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_N1RSP                             , 35  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_N1RSP      );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_XARSP                             , 36  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_XARSP      );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_SACOLL                            , 37  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_SACOLL     );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_FREE                              , 38  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FREE       );
+REG64_FLD( PU_NPU0_SM1_SM_STATUS_RESERVED1                         , 39  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_CREQ0                             , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CREQ0      );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_PRB0                              , 1   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PRB0       );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_CREQ1                             , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CREQ1      );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_PRB1                              , 3   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PRB1       );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_XATS                              , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_XATS       );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_PWR0                              , 5   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PWR0       );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_PWR1                              , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PWR1       );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_CHGRATE                           , 7   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CHGRATE    );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_MRBGP                             , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP      );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_MRBGP_LEN                         , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MRBGP_LEN  );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_MRBSP                             , 12  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP      );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_MRBSP_LEN                         , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MRBSP_LEN  );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE0                            , 16  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0     );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE0_LEN                        , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_LEN );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE1                            , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1     );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE1_LEN                        , 4   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_LEN );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBLN                              , 24  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PBLN       );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBNNG                             , 25  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PBNNG      );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBRNVG                            , 26  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PBRNVG     );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_N0REQ                             , 27  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N0REQ      );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_N0DGD                             , 28  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N0DGD      );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_N1REQ                             , 29  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N1REQ      );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_N1DGD                             , 30  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N1DGD      );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_MMIO                              , 31  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_MMIO       );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_ATSXLATE                          , 32  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_ATSXLATE   );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBRSP                             , 33  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_PBRSP      );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_N0RSP                             , 34  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N0RSP      );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_N1RSP                             , 35  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_N1RSP      );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_XARSP                             , 36  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_XARSP      );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_SACOLL                            , 37  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_SACOLL     );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_FREE                              , 38  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FREE       );
+REG64_FLD( PU_NPU1_SM0_SM_STATUS_RESERVED1                         , 39  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_RESERVED1  );
+
+REG64_FLD( PU_SND_MODE_REG_ENABLE_TRC_GLB_TRIG0                    , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_TRC_GLB_TRIG0 );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_TRC_GLB_TRIG1                    , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_TRC_GLB_TRIG1 );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_GLB_PULSE                        , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_GLB_PULSE );
+REG64_FLD( PU_SND_MODE_REG_SINGLE_OUTSTANDING_CMD                  , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SINGLE_OUTSTANDING_CMD );
+REG64_FLD( PU_SND_MODE_REG_PROG_REQ_DELAY                          , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PROG_REQ_DELAY );
+REG64_FLD( PU_SND_MODE_REG_PROG_REQ_DELAY_LEN                      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PROG_REQ_DELAY_LEN );
+REG64_FLD( PU_SND_MODE_REG_DISABLE_ERR_CMD                         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_ERR_CMD );
+REG64_FLD( PU_SND_MODE_REG_DISABLE_HTM_CMD                         , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_HTM_CMD );
+REG64_FLD( PU_SND_MODE_REG_DISABLE_TRACE_CMD                       , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_TRACE_CMD );
+REG64_FLD( PU_SND_MODE_REG_DISABLE_TOD_CMD                         , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_TOD_CMD );
+REG64_FLD( PU_SND_MODE_REG_DISABLE_XSCOM_CMD                       , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_XSCOM_CMD );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_CLR_ERR_CMD                      , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CLR_ERR_CMD );
+REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_ERR_CMD                 , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OVERRIDE_PBINIT_ERR_CMD );
+REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_HTM_CMD                 , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OVERRIDE_PBINIT_HTM_CMD );
+REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_TRACE_CMD               , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OVERRIDE_PBINIT_TRACE_CMD );
+REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_TOD_CMD                 , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OVERRIDE_PBINIT_TOD_CMD );
+REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_XSCOM_CMD               , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OVERRIDE_PBINIT_XSCOM_CMD );
+REG64_FLD( PU_SND_MODE_REG_DISABLE_CHECKSTOP                       , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_CHECKSTOP );
+REG64_FLD( PU_SND_MODE_REG_MANUAL_SET_PB_STOP                      , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MANUAL_SET_PB_STOP );
+REG64_FLD( PU_SND_MODE_REG_MANUAL_CLR_PB_STOP                      , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MANUAL_CLR_PB_STOP );
+REG64_FLD( PU_SND_MODE_REG_PB_STOP                                 , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PB_STOP    );
+REG64_FLD( PU_SND_MODE_REG_MANUAL_PB_SWITCH_ABCD                   , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MANUAL_PB_SWITCH_ABCD );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TRIGGER              , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TRIGGER_LEN          , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER_LEN );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TOD                  , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_RECEIVE_OWN_TOD );
+REG64_FLD( PU_SND_MODE_REG_RESET_TOD_STATE                         , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESET_TOD_STATE );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_PB_SWITCH_AB                     , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_PB_SWITCH_AB );
+REG64_FLD( PU_SND_MODE_REG_ENABLE_PB_SWITCH_CD                     , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_PB_SWITCH_CD );
+
+REG64_FLD( PU_SND_STAT_REG_ERR_CMD_OVERRUN                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ERR_CMD_OVERRUN );
+REG64_FLD( PU_SND_STAT_REG_TRC_CMD_OVERRUN                         , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRC_CMD_OVERRUN );
+REG64_FLD( PU_SND_STAT_REG_XSC_CMD_OVERRUN                         , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_XSC_CMD_OVERRUN );
+REG64_FLD( PU_SND_STAT_REG_HTM_CMD_OVERRUN                         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HTM_CMD_OVERRUN );
+REG64_FLD( PU_SND_STAT_REG_TOD_CMD_OVERRUN                         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TOD_CMD_OVERRUN );
+REG64_FLD( PU_SND_STAT_REG_CMD_COUNT_ERR                           , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_COUNT_ERR );
+REG64_FLD( PU_SND_STAT_REG_PB_OP_HANG_ERR                          , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PB_OP_HANG_ERR );
+REG64_FLD( PU_SND_STAT_REG_INVALID_CRESP_ERR                       , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INVALID_CRESP_ERR );
+REG64_FLD( PU_SND_STAT_REG_RCV_TTAG_PARITY_ERR                     , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RCV_TTAG_PARITY_ERR );
+REG64_FLD( PU_SND_STAT_REG_RCV_PB_OP_HANG_ERR                      , 33  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RCV_PB_OP_HANG_ERR );
+REG64_FLD( PU_SND_STAT_REG_TOD_HANG_ERR                            , 34  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TOD_HANG_ERR );
+REG64_FLD( PU_SND_STAT_REG_RCV_TOD_STATE                           , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RCV_TOD_STATE );
+REG64_FLD( PU_SND_STAT_REG_RCV_TOD_STATE_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RCV_TOD_STATE_LEN );
+
+REG64_FLD( PEC_SPATTN_IN                                           , 0   , SH_UNT_PEC      , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN         );
+REG64_FLD( PEC_SPATTN_IN_LEN                                       , 10  , SH_UNT_PEC      , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( PEC_SPA_MASK_IN                                         , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( PEC_SPA_MASK_IN_LEN                                     , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_FRAME_SIZE              , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_FRAME_SIZE );
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_FRAME_SIZE_LEN          , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_FRAME_SIZE_LEN );
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_OUT_COUNT               , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_OUT_COUNT );
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_OUT_COUNT_LEN           , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_OUT_COUNT_LEN );
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_DELAY                , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_IN_DELAY );
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_DELAY_LEN            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_IN_DELAY_LEN );
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_COUNT                , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_IN_COUNT );
+REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_COUNT_LEN            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_IN_COUNT_LEN );
+
+REG64_FLD( PU_SPIPSS_100NS_REG_OUT                                 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OUT        );
+REG64_FLD( PU_SPIPSS_100NS_REG_OUT_LEN                             , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OUT_LEN    );
+
+REG64_FLD( PU_SPIPSS_ADC_CMD_REG_HWCTRL_START_SAMPLING             , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_START_SAMPLING );
+
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_FSM_ENABLE               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_FSM_ENABLE );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_DEVICE                   , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_DEVICE );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CPOL                     , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_CPOL );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CPHA                     , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_CPHA );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CLOCK_DIVIDER            , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_CLOCK_DIVIDER );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CLOCK_DIVIDER_LEN        , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_CLOCK_DIVIDER_LEN );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_NR_OF_FRAMES             , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_NR_OF_FRAMES );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_NR_OF_FRAMES_LEN         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_NR_OF_FRAMES_LEN );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_BUSY_RESPONSE_CODE              , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUSY_RESPONSE_CODE );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_BUSY_RESPONSE_CODE_LEN          , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUSY_RESPONSE_CODE_LEN );
+
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG2_HWCTRL_INTER_FRAME_DELAY        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_INTER_FRAME_DELAY );
+REG64_FLD( PU_SPIPSS_ADC_CTRL_REG2_HWCTRL_INTER_FRAME_DELAY_LEN    , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_INTER_FRAME_DELAY_LEN );
+
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG0_HWCTRL_RDATA0                  , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_RDATA0 );
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG0_HWCTRL_RDATA0_LEN              , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_RDATA0_LEN );
+
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG1_HWCTRL_RDATA1                  , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_RDATA1 );
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG1_HWCTRL_RDATA1_LEN              , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_RDATA1_LEN );
+
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG2_HWCTRL_RDATA2                  , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_RDATA2 );
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG2_HWCTRL_RDATA2_LEN              , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_RDATA2_LEN );
+
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG3_HWCTRL_RDATA3                  , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_RDATA3 );
+REG64_FLD( PU_SPIPSS_ADC_RDATA_REG3_HWCTRL_RDATA3_LEN              , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_RDATA3_LEN );
+
+REG64_FLD( PU_SPIPSS_ADC_RESET_REGISTER_HWCTRL                     , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL     );
+REG64_FLD( PU_SPIPSS_ADC_RESET_REGISTER_HWCTRL_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_LEN );
+
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_HWCTRL_ONGOING                 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_ONGOING );
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_RESERVED_1                     , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_1 );
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_RESERVED_2                     , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_2 );
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_RESERVED_3                     , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_3 );
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_HWCTRL_INVALID_NUMBER_OF_FRAMES , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_INVALID_NUMBER_OF_FRAMES );
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_HWCTRL_WRITE_WHILE_FSM_BUSY_ERR , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_WRITE_WHILE_FSM_BUSY_ERR );
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_RESERVED_6                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_6 );
+REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_HWCTRL_FSM_ERR                 , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_FSM_ERR );
+
+REG64_FLD( PU_SPIPSS_ADC_WDATA_REG_HWCTRL                          , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL     );
+REG64_FLD( PU_SPIPSS_ADC_WDATA_REG_HWCTRL_LEN                      , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HWCTRL_LEN );
+
+REG64_FLD( PU_SPIPSS_P2S_COMMAND_REG_START                         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_START      );
+
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_FRAME_SIZE                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_SIZE );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_FRAME_SIZE_LEN                  , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_SIZE_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT1                      , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OUT_COUNT1 );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT1_LEN                  , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OUT_COUNT1_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY1                       , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_DELAY1  );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY1_LEN                   , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_DELAY1_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT1                       , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_COUNT1  );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT1_LEN                   , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_COUNT1_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT2                      , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OUT_COUNT2 );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT2_LEN                  , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_OUT_COUNT2_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY2                       , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_DELAY2  );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY2_LEN                   , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_DELAY2_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT2                       , 36  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_COUNT2  );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT2_LEN                   , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_COUNT2_LEN );
+
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_BRIDGE_ENABLE                   , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BRIDGE_ENABLE );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_DEVICE                          , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DEVICE     );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_CPOL                            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CPOL       );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_CPHA                            , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CPHA       );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_CLOCK_DIVIDER                   , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_DIVIDER );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_CLOCK_DIVIDER_LEN               , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_DIVIDER_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_RESERVED                        , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_RESERVED_LEN                    , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_NR_OF_FRAMES                    , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NR_OF_FRAMES );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_BUSY_RESPONSE_CODE_NO_1         , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUSY_RESPONSE_CODE_NO_1 );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_BUSY_RESPONSE_CODE_NO_1_LEN     , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUSY_RESPONSE_CODE_NO_1_LEN );
+
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG2_INTER_FRAME_DELAY               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INTER_FRAME_DELAY );
+REG64_FLD( PU_SPIPSS_P2S_CTRL_REG2_INTER_FRAME_DELAY_LEN           , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INTER_FRAME_DELAY_LEN );
+
+REG64_FLD( PU_SPIPSS_P2S_RDATA_REG_RDATA                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RDATA      );
+REG64_FLD( PU_SPIPSS_P2S_RDATA_REG_RDATA_LEN                       , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RDATA_LEN  );
+
+REG64_FLD( PU_SPIPSS_P2S_RESET_REGISTER_RESET                      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESET      );
+REG64_FLD( PU_SPIPSS_P2S_RESET_REGISTER_RESET_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESET_LEN  );
+
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_ONGOING                        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ONGOING    );
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_RESERVED_1                     , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_1 );
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_RESERVED_2                     , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_2 );
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_RESERVED_3                     , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_3 );
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_RESERVED_4                     , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_4 );
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_WRITE_WHILE_BRIDGE_BUSY_ERR    , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_WHILE_BRIDGE_BUSY_ERR );
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_RESERVED6                      , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED6  );
+REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_FSM_ERR                        , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FSM_ERR    );
+
+REG64_FLD( PU_SPIPSS_P2S_WDATA_REG_WDATA                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WDATA      );
+REG64_FLD( PU_SPIPSS_P2S_WDATA_REG_WDATA_LEN                       , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WDATA_LEN  );
+
+REG64_FLD( PU_SRAM_SRBV0_BOOT_VECTOR_WORD0                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BOOT_VECTOR_WORD0 );
+REG64_FLD( PU_SRAM_SRBV0_BOOT_VECTOR_WORD0_LEN                     , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BOOT_VECTOR_WORD0_LEN );
+
+REG64_FLD( PU_SRAM_SRBV1_BOOT_VECTOR_WORD1                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BOOT_VECTOR_WORD1 );
+REG64_FLD( PU_SRAM_SRBV1_BOOT_VECTOR_WORD1_LEN                     , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BOOT_VECTOR_WORD1_LEN );
+
+REG64_FLD( PU_SRAM_SRBV2_BOOT_VECTOR_WORD2                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BOOT_VECTOR_WORD2 );
+REG64_FLD( PU_SRAM_SRBV2_BOOT_VECTOR_WORD2_LEN                     , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BOOT_VECTOR_WORD2_LEN );
+
+REG64_FLD( PU_SRAM_SRBV3_BOOT_VECTOR_WORD3                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BOOT_VECTOR_WORD3 );
+REG64_FLD( PU_SRAM_SRBV3_BOOT_VECTOR_WORD3_LEN                     , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BOOT_VECTOR_WORD3_LEN );
+
+REG64_FLD( PU_SRAM_SRCHSW_CHKSW_WRFSM_DLY_DIS                      , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHKSW_WRFSM_DLY_DIS );
+REG64_FLD( PU_SRAM_SRCHSW_CHKSW_ALLOW1_RD                          , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHKSW_ALLOW1_RD );
+REG64_FLD( PU_SRAM_SRCHSW_CHKSW_ALLOW1_WR                          , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHKSW_ALLOW1_WR );
+REG64_FLD( PU_SRAM_SRCHSW_CHKSW_ALLOW1_RDWR                        , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHKSW_ALLOW1_RDWR );
+REG64_FLD( PU_SRAM_SRCHSW_CHKSW_OCI_PARCHK_DIS                     , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHKSW_OCI_PARCHK_DIS );
+REG64_FLD( PU_SRAM_SRCHSW_CHKSW_TANK_RDDATA_PARCHK_DIS             , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHKSW_TANK_RDDATA_PARCHK_DIS );
+REG64_FLD( PU_SRAM_SRCHSW_CHKSW_SPARE_6                            , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHKSW_SPARE_6 );
+REG64_FLD( PU_SRAM_SRCHSW_CHKSW_VAL_BE_ADDR_CHK_DIS                , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHKSW_VAL_BE_ADDR_CHK_DIS );
+REG64_FLD( PU_SRAM_SRCHSW_CHKSW_SO_SPARE                           , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHKSW_SO_SPARE );
+REG64_FLD( PU_SRAM_SRCHSW_CHKSW_SO_SPARE_LEN                       , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CHKSW_SO_SPARE_LEN );
+
+REG64_FLD( PU_SRAM_SREAR_ERROR_ADDRESS                             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_ADDRESS );
+REG64_FLD( PU_SRAM_SREAR_ERROR_ADDRESS_LEN                         , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_ADDRESS_LEN );
+
+REG64_FLD( PU_SRAM_SRMAP_REMAP_SOURCE                              , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_REMAP_SOURCE );
+REG64_FLD( PU_SRAM_SRMAP_REMAP_SOURCE_LEN                          , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_REMAP_SOURCE_LEN );
+REG64_FLD( PU_SRAM_SRMAP_REMAP_DEST                                , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_REMAP_DEST );
+REG64_FLD( PU_SRAM_SRMAP_REMAP_DEST_LEN                            , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_REMAP_DEST_LEN );
+
+REG64_FLD( PU_SRAM_SRMR_ENABLE_REMAP                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_REMAP );
+REG64_FLD( PU_SRAM_SRMR_ARB_EN_SEND_ALL_WRITES                     , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ARB_EN_SEND_ALL_WRITES );
+REG64_FLD( PU_SRAM_SRMR_DISABLE_LFSR                               , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_LFSR );
+REG64_FLD( PU_SRAM_SRMR_LFSR_FAIRNESS_MASK                         , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LFSR_FAIRNESS_MASK );
+REG64_FLD( PU_SRAM_SRMR_LFSR_FAIRNESS_MASK_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LFSR_FAIRNESS_MASK_LEN );
+REG64_FLD( PU_SRAM_SRMR_ERROR_INJECT_ENABLE                        , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_INJECT_ENABLE );
+REG64_FLD( PU_SRAM_SRMR_CTL_TRACE_EN                               , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CTL_TRACE_EN );
+REG64_FLD( PU_SRAM_SRMR_CTL_TRACE_SEL                              , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CTL_TRACE_SEL );
+REG64_FLD( PU_SRAM_SRMR_SPARE                                      , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_SRAM_SRMR_SPARE_LEN                                  , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_STATUS_REGISTER_ADDR_NVLD                            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_NVLD  );
+REG64_FLD( PU_STATUS_REGISTER_WRITE_NVLD                           , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_NVLD );
+REG64_FLD( PU_STATUS_REGISTER_READ_NVLD                            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_READ_NVLD  );
+REG64_FLD( PU_STATUS_REGISTER_INVLD_CMD_ERR                        , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INVLD_CMD_ERR );
+REG64_FLD( PU_STATUS_REGISTER_CORR_ERR                             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CORR_ERR   );
+REG64_FLD( PU_STATUS_REGISTER_UNCORR_ERROR                         , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNCORR_ERROR );
+REG64_FLD( PU_STATUS_REGISTER_DATA_REG_0_31                        , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_REG_0_31 );
+REG64_FLD( PU_STATUS_REGISTER_DATA_REG_0_31_LEN                    , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_REG_0_31_LEN );
+REG64_FLD( PU_STATUS_REGISTER_UNUSED_39_43                         , 39  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_39_43 );
+REG64_FLD( PU_STATUS_REGISTER_UNUSED_39_43_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_39_43_LEN );
+REG64_FLD( PU_STATUS_REGISTER_CTRL_BUSY                            , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CTRL_BUSY  );
+REG64_FLD( PU_STATUS_REGISTER_DCOMP_ERR                            , 45  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DCOMP_ERR  );
+REG64_FLD( PU_STATUS_REGISTER_INVLD_PRGM_ERR                       , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INVLD_PRGM_ERR );
+REG64_FLD( PU_STATUS_REGISTER_UNUSED_47_51                         , 47  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_47_51 );
+REG64_FLD( PU_STATUS_REGISTER_UNUSED_47_51_LEN                     , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_47_51_LEN );
+REG64_FLD( PU_STATUS_REGISTER_COMMAND_COMPLETE                     , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_COMMAND_COMPLETE );
+REG64_FLD( PU_STATUS_REGISTER_UNUSED_53                            , 53  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_53  );
+REG64_FLD( PU_STATUS_REGISTER_RDWR_OP_BUSY                         , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RDWR_OP_BUSY );
+REG64_FLD( PU_STATUS_REGISTER_DCOMP_ENGINE_BUSY                    , 55  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DCOMP_ENGINE_BUSY );
+REG64_FLD( PU_STATUS_REGISTER_RD_DATA_COUNT                        , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RD_DATA_COUNT );
+REG64_FLD( PU_STATUS_REGISTER_RD_DATA_COUNT_LEN                    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RD_DATA_COUNT_LEN );
+
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_ADDR_NVLD_0                    , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ADDR_NVLD_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_WRITE_NVLD_0                   , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_WRITE_NVLD_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_READ_NVLD_0                    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_READ_NVLD_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_ADDR_P_ERR_0                   , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ADDR_P_ERR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_PAR_ERR_0                      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_PAR_ERR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_LB_PARITY_ERROR_0              , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_LB_PARITY_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_PIB_DATA0TO7_0                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_DATA0TO7_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_PIB_DATA0TO7_0_LEN                 , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_DATA0TO7_0_LEN );
+REG64_FLD( PU_STATUS_REGISTER_B_ECC_CORRECTED_ERROR_0              , 41  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_CORRECTED_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_ECC_UNCORRECTED_ERROR_0            , 42  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_UNCORRECTED_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_ECC_CONFIG_ERROR_0                 , 43  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_CONFIG_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_BUSY_0                         , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_BUSY_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_INVALID_COMMAND_0              , 45  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_INVALID_COMMAND_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_PARITY_ERROR_0                 , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_PARITY_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_BACK_END_OVERRUN_ERROR_0       , 47  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_BACK_END_OVERRUN_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_BACK_END_ACCESS_ERROR_0        , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_BACK_END_ACCESS_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_ARBITRATION_LOST_ERROR_0       , 49  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ARBITRATION_LOST_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_NACK_RECEIVED_ERROR_0          , 50  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_NACK_RECEIVED_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_DATA_REQUEST_0                 , 51  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_DATA_REQUEST_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_COMMAND_COMPLETE_0             , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_COMMAND_COMPLETE_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_STOP_ERROR_0                   , 53  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_STOP_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_I2C_PORT_BUSY_0                , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_I2C_PORT_BUSY_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_I2C_INTERFACE_BUSY_0           , 55  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_I2C_INTERFACE_BUSY_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_FIFO_ENTRY_COUNT_0             , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_FIFO_ENTRY_COUNT_0 );
+REG64_FLD( PU_STATUS_REGISTER_B_BUS_FIFO_ENTRY_COUNT_0_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_FIFO_ENTRY_COUNT_0_LEN );
+
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_ADDR_NVLD_1                    , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ADDR_NVLD_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_WRITE_NVLD_1                   , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_WRITE_NVLD_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_READ_NVLD_1                    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_READ_NVLD_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_ADDR_P_ERR_1                   , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ADDR_P_ERR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_PAR_ERR_1                      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_PAR_ERR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_LB_PARITY_ERROR_1              , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_LB_PARITY_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_PIB_DATA0TO7_1                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_DATA0TO7_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_PIB_DATA0TO7_1_LEN                 , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_DATA0TO7_1_LEN );
+REG64_FLD( PU_STATUS_REGISTER_C_ECC_CORRECTED_ERROR_1              , 41  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_CORRECTED_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_ECC_UNCORRECTED_ERROR_1            , 42  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_UNCORRECTED_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_ECC_CONFIG_ERROR_1                 , 43  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_CONFIG_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_BUSY_1                         , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_BUSY_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_INVALID_COMMAND_1              , 45  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_INVALID_COMMAND_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_PARITY_ERROR_1                 , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_PARITY_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_BACK_END_OVERRUN_ERROR_1       , 47  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_BACK_END_OVERRUN_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_BACK_END_ACCESS_ERROR_1        , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_BACK_END_ACCESS_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_ARBITRATION_LOST_ERROR_1       , 49  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ARBITRATION_LOST_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_NACK_RECEIVED_ERROR_1          , 50  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_NACK_RECEIVED_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_DATA_REQUEST_1                 , 51  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_DATA_REQUEST_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_COMMAND_COMPLETE_1             , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_COMMAND_COMPLETE_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_STOP_ERROR_1                   , 53  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_STOP_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_I2C_PORT_BUSY_1                , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_I2C_PORT_BUSY_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_I2C_INTERFACE_BUSY_1           , 55  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_I2C_INTERFACE_BUSY_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_FIFO_ENTRY_COUNT_1             , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_FIFO_ENTRY_COUNT_1 );
+REG64_FLD( PU_STATUS_REGISTER_C_BUS_FIFO_ENTRY_COUNT_1_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_FIFO_ENTRY_COUNT_1_LEN );
+
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_ADDR_NVLD_2                    , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ADDR_NVLD_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_WRITE_NVLD_2                   , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_WRITE_NVLD_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_READ_NVLD_2                    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_READ_NVLD_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_ADDR_P_ERR_2                   , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ADDR_P_ERR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_PAR_ERR_2                      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_PAR_ERR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_LB_PARITY_ERROR_2              , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_LB_PARITY_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_PIB_DATA0TO7_2                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_DATA0TO7_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_PIB_DATA0TO7_2_LEN                 , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_DATA0TO7_2_LEN );
+REG64_FLD( PU_STATUS_REGISTER_D_ECC_CORRECTED_ERROR_2              , 41  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_CORRECTED_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_ECC_UNCORRECTED_ERROR_2            , 42  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_UNCORRECTED_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_ECC_CONFIG_ERROR_2                 , 43  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_CONFIG_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_BUSY_2                         , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_BUSY_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_INVALID_COMMAND_2              , 45  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_INVALID_COMMAND_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_PARITY_ERROR_2                 , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_PARITY_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_BACK_END_OVERRUN_ERROR_2       , 47  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_BACK_END_OVERRUN_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_BACK_END_ACCESS_ERROR_2        , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_BACK_END_ACCESS_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_ARBITRATION_LOST_ERROR_2       , 49  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ARBITRATION_LOST_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_NACK_RECEIVED_ERROR_2          , 50  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_NACK_RECEIVED_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_DATA_REQUEST_2                 , 51  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_DATA_REQUEST_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_COMMAND_COMPLETE_2             , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_COMMAND_COMPLETE_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_STOP_ERROR_2                   , 53  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_STOP_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_I2C_PORT_BUSY_2                , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_I2C_PORT_BUSY_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_I2C_INTERFACE_BUSY_2           , 55  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_I2C_INTERFACE_BUSY_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_FIFO_ENTRY_COUNT_2             , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_FIFO_ENTRY_COUNT_2 );
+REG64_FLD( PU_STATUS_REGISTER_D_BUS_FIFO_ENTRY_COUNT_2_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_FIFO_ENTRY_COUNT_2_LEN );
+
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_ADDR_NVLD_3                    , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ADDR_NVLD_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_WRITE_NVLD_3                   , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_WRITE_NVLD_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_READ_NVLD_3                    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_READ_NVLD_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_ADDR_P_ERR_3                   , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ADDR_P_ERR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_PAR_ERR_3                      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_PAR_ERR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_LB_PARITY_ERROR_3              , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_LB_PARITY_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_PIB_DATA0TO7_3                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_DATA0TO7_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_PIB_DATA0TO7_3_LEN                 , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_DATA0TO7_3_LEN );
+REG64_FLD( PU_STATUS_REGISTER_E_ECC_CORRECTED_ERROR_3              , 41  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_CORRECTED_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_ECC_UNCORRECTED_ERROR_3            , 42  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_UNCORRECTED_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_ECC_CONFIG_ERROR_3                 , 43  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ECC_CONFIG_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_BUSY_3                         , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_BUSY_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_INVALID_COMMAND_3              , 45  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_INVALID_COMMAND_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_PARITY_ERROR_3                 , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_PARITY_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_BACK_END_OVERRUN_ERROR_3       , 47  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_BACK_END_OVERRUN_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_BACK_END_ACCESS_ERROR_3        , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_BACK_END_ACCESS_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_ARBITRATION_LOST_ERROR_3       , 49  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ARBITRATION_LOST_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_NACK_RECEIVED_ERROR_3          , 50  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_NACK_RECEIVED_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_DATA_REQUEST_3                 , 51  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_DATA_REQUEST_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_COMMAND_COMPLETE_3             , 52  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_COMMAND_COMPLETE_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_STOP_ERROR_3                   , 53  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_STOP_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_I2C_PORT_BUSY_3                , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_I2C_PORT_BUSY_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_I2C_INTERFACE_BUSY_3           , 55  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_I2C_INTERFACE_BUSY_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_FIFO_ENTRY_COUNT_3             , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_FIFO_ENTRY_COUNT_3 );
+REG64_FLD( PU_STATUS_REGISTER_E_BUS_FIFO_ENTRY_COUNT_3_LEN         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUS_FIFO_ENTRY_COUNT_3_LEN );
+
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_INVALID_CMD_0               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INVALID_CMD_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_LBUS_PARITY_ERROR_0         , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_BE_OV_ERROR_0               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_OV_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_BE_ACC_ERROR_0              , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_ACC_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_ARBITRATION_LOST_ERROR_0    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ARBITRATION_LOST_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_NACK_RECEIVED_ERROR_0       , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NACK_RECEIVED_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_DATA_REQUEST_0              , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_REQUEST_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_STOP_ERROR_0                , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ERROR_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_BUSY                        , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_SELF_BUSY_0                 , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SELF_BUSY_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_FIFO_ENTRY_COUNT_0          , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_ENTRY_COUNT_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_FIFO_ENTRY_COUNT_0_LEN      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_ENTRY_COUNT_0_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_PEEK_DATA1_0                , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_PEEK_DATA1_0_LEN            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_LBUS_PARITY_ERR1_0          , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_I2CM_STEERED_INTERRUPTS_0   , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_I2CM_STEERED_INTERRUPTS_0 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_I2CM_STEERED_INTERRUPTS_0_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_I2CM_STEERED_INTERRUPTS_0_LEN );
+
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_INVALID_CMD_1               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INVALID_CMD_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_LBUS_PARITY_ERROR_1         , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_BE_OV_ERROR_1               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_OV_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_BE_ACC_ERROR_1              , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_ACC_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_ARBITRATION_LOST_ERROR_1    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ARBITRATION_LOST_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_NACK_RECEIVED_ERROR_1       , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NACK_RECEIVED_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_DATA_REQUEST_1              , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_REQUEST_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_STOP_ERROR_1                , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ERROR_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_BUSY                        , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_SELF_BUSY_1                 , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SELF_BUSY_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_FIFO_ENTRY_COUNT_1          , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_ENTRY_COUNT_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_FIFO_ENTRY_COUNT_1_LEN      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_ENTRY_COUNT_1_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_PEEK_DATA1_1                , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_PEEK_DATA1_1_LEN            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_LBUS_PARITY_ERR1_1          , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_I2CM_STEERED_INTERRUPTS_1   , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_I2CM_STEERED_INTERRUPTS_1 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_I2CM_STEERED_INTERRUPTS_1_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_I2CM_STEERED_INTERRUPTS_1_LEN );
+
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_INVALID_CMD_2               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INVALID_CMD_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_LBUS_PARITY_ERROR_2         , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_BE_OV_ERROR_2               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_OV_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_BE_ACC_ERROR_2              , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_ACC_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_ARBITRATION_LOST_ERROR_2    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ARBITRATION_LOST_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_NACK_RECEIVED_ERROR_2       , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NACK_RECEIVED_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_DATA_REQUEST_2              , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_REQUEST_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_STOP_ERROR_2                , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ERROR_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_BUSY                        , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_SELF_BUSY_2                 , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SELF_BUSY_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_FIFO_ENTRY_COUNT_2          , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_ENTRY_COUNT_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_FIFO_ENTRY_COUNT_2_LEN      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_ENTRY_COUNT_2_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_PEEK_DATA1_2                , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_PEEK_DATA1_2_LEN            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_LBUS_PARITY_ERR1_2          , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_I2CM_STEERED_INTERRUPTS_2   , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_I2CM_STEERED_INTERRUPTS_2 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_I2CM_STEERED_INTERRUPTS_2_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_I2CM_STEERED_INTERRUPTS_2_LEN );
+
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_INVALID_CMD_3               , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_INVALID_CMD_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_LBUS_PARITY_ERROR_3         , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_BE_OV_ERROR_3               , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_OV_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_BE_ACC_ERROR_3              , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BE_ACC_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_ARBITRATION_LOST_ERROR_3    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ARBITRATION_LOST_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_NACK_RECEIVED_ERROR_3       , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_NACK_RECEIVED_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_DATA_REQUEST_3              , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_REQUEST_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_STOP_ERROR_3                , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ERROR_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_BUSY                        , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BUSY       );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_SELF_BUSY_3                 , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SELF_BUSY_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_FIFO_ENTRY_COUNT_3          , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_ENTRY_COUNT_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_FIFO_ENTRY_COUNT_3_LEN      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_ENTRY_COUNT_3_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_PEEK_DATA1_3                , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_PEEK_DATA1_3_LEN            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_LBUS_PARITY_ERR1_3          , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_I2CM_STEERED_INTERRUPTS_3   , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_I2CM_STEERED_INTERRUPTS_3 );
+REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_I2CM_STEERED_INTERRUPTS_3_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_I2CM_STEERED_INTERRUPTS_3_LEN );
+
+REG64_FLD( PEC_SUM_MASK_REG_SMASK_IN0                              , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN0  );
+REG64_FLD( PEC_SUM_MASK_REG_SMASK_IN1                              , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN1  );
+REG64_FLD( PEC_SUM_MASK_REG_SMASK_IN2                              , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN2  );
+REG64_FLD( PEC_SUM_MASK_REG_SMASK_IN3                              , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN3  );
+REG64_FLD( PEC_SUM_MASK_REG_SMASK_IN4                              , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN4  );
+
+REG64_FLD( PU_SU_CRB_KILL_REQ_ENABLE                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PU_SU_CRB_KILL_REQ_DONE                                 , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DONE       );
+REG64_FLD( PU_SU_CRB_KILL_REQ_SUMMARY                              , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUMMARY    );
+REG64_FLD( PU_SU_CRB_KILL_REQ_DISPATCH_SLOT_KILLED_CNT             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISPATCH_SLOT_KILLED_CNT );
+REG64_FLD( PU_SU_CRB_KILL_REQ_DISPATCH_SLOT_KILLED_CNT_LEN         , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISPATCH_SLOT_KILLED_CNT_LEN );
+REG64_FLD( PU_SU_CRB_KILL_REQ_PREFETCH_CHANNEL_CNT                 , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PREFETCH_CHANNEL_CNT );
+REG64_FLD( PU_SU_CRB_KILL_REQ_PREFETCH_CHANNEL_CNT_LEN             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PREFETCH_CHANNEL_CNT_LEN );
+REG64_FLD( PU_SU_CRB_KILL_REQ_ACTIVE_CHANNEL_CNT                   , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTIVE_CHANNEL_CNT );
+REG64_FLD( PU_SU_CRB_KILL_REQ_ACTIVE_CHANNEL_CNT_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTIVE_CHANNEL_CNT_LEN );
+REG64_FLD( PU_SU_CRB_KILL_REQ_SWC_VALUE                            , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SWC_VALUE  );
+REG64_FLD( PU_SU_CRB_KILL_REQ_SWC_VALUE_LEN                        , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SWC_VALUE_LEN );
+
+REG64_FLD( PU_SU_DMA_ERROR_REPORT_0_0                              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_0          );
+REG64_FLD( PU_SU_DMA_ERROR_REPORT_0_0_LEN                          , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_0_LEN      );
+
+REG64_FLD( PU_SU_DMA_ERROR_REPORT_1_1                              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_1          );
+REG64_FLD( PU_SU_DMA_ERROR_REPORT_1_1_LEN                          , 17  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_LEN      );
+
+REG64_FLD( PU_SU_ENGINE_ENABLE_ALLOW_CRYPTO                        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ALLOW_CRYPTO );
+REG64_FLD( PU_SU_ENGINE_ENABLE_CH3_SYM                             , 57  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CH3_SYM    );
+REG64_FLD( PU_SU_ENGINE_ENABLE_CH2_SYM                             , 58  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CH2_SYM    );
+REG64_FLD( PU_SU_ENGINE_ENABLE_CH4_GZIP                            , 61  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CH4_GZIP   );
+REG64_FLD( PU_SU_ENGINE_ENABLE_CH1_EFT                             , 62  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CH1_EFT    );
+REG64_FLD( PU_SU_ENGINE_ENABLE_CH0_EFT                             , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CH0_EFT    );
+
+REG64_FLD( PU_SU_ERAT_ERROR_RPT_RPT                                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RPT        );
+REG64_FLD( PU_SU_ERAT_ERROR_RPT_RPT_LEN                            , 48  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RPT_LEN    );
+
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIPCOMP_MAX_INRD           , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GZIPCOMP_MAX_INRD );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIPCOMP_MAX_INRD_LEN       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GZIPCOMP_MAX_INRD_LEN );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIPDECOMP_MAX_INRD         , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GZIPDECOMP_MAX_INRD );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIPDECOMP_MAX_INRD_LEN     , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GZIPDECOMP_MAX_INRD_LEN );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIP_COMP_PREFETCH_ENABLE   , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GZIP_COMP_PREFETCH_ENABLE );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIP_DECOMP_PREFETCH_ENABLE , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GZIP_DECOMP_PREFETCH_ENABLE );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFT_COMP_PREFETCH_ENABLE    , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EFT_COMP_PREFETCH_ENABLE );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFT_DECOMP_PREFETCH_ENABLE  , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EFT_DECOMP_PREFETCH_ENABLE );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_SYM_MAX_INRD                , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYM_MAX_INRD );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_SYM_MAX_INRD_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYM_MAX_INRD_LEN );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFTCOMP_MAX_INRD            , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EFTCOMP_MAX_INRD );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFTCOMP_MAX_INRD_LEN        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EFTCOMP_MAX_INRD_LEN );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFTDECOMP_MAX_INRD          , 37  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EFTDECOMP_MAX_INRD );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFTDECOMP_MAX_INRD_LEN      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EFTDECOMP_MAX_INRD_LEN );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_SYM_CPB_CHECK_DISABLE       , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYM_CPB_CHECK_DISABLE );
+REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFT_SPBC_ENABLE             , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EFT_SPBC_ENABLE );
+
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_LPID                            , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LPID       );
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_LPID_LEN                        , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LPID_LEN   );
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_LPID_MASK                       , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LPID_MASK  );
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_LPID_MASK_LEN                   , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LPID_MASK_LEN );
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_PID                             , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PID        );
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_PID_LEN                         , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PID_LEN    );
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_PID_MASK                        , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PID_MASK   );
+REG64_FLD( PU_SU_PERFMON_CONTROL_0_PID_MASK_LEN                    , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PID_MASK_LEN );
+
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_GZIP_FC_SELECT                  , 27  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GZIP_FC_SELECT );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_GZIP_FC_SELECT_LEN              , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GZIP_FC_SELECT_LEN );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_842_FC_SELECT                   , 29  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_842_FC_SELECT );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_842_FC_SELECT_LEN               , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_842_FC_SELECT_LEN );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_DMA_MUX_SELECT                  , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_MUX_SELECT );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_DMA_MUX_SELECT_LEN              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_MUX_SELECT_LEN );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_EFT_MUX_SELECT                  , 35  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EFT_MUX_SELECT );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_EFT_MUX_SELECT_LEN              , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EFT_MUX_SELECT_LEN );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_GZIP_MUX_SELECT                 , 38  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GZIP_MUX_SELECT );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_GZIP_MUX_SELECT_LEN             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GZIP_MUX_SELECT_LEN );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_ERAT_MUX_SELECT                 , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERAT_MUX_SELECT );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_ERAT_MUX_SELECT_LEN             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERAT_MUX_SELECT_LEN );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_UMAC_MUX_SELECT                 , 45  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_UMAC_MUX_SELECT );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_UMAC_MUX_SELECT_LEN             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_UMAC_MUX_SELECT_LEN );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_PBI_MUX_SELECT                  , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBI_MUX_SELECT );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_PBI_MUX_SELECT_LEN              , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBI_MUX_SELECT_LEN );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_SHA_LATENCY_CFG                 , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SHA_LATENCY_CFG );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_MD5_LATENCY_CFG                 , 54  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MD5_LATENCY_CFG );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_AES_LATENCY_CFG                 , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_AES_LATENCY_CFG );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_AESSHA_LATENCY_CFG              , 58  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_AESSHA_LATENCY_CFG );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_GZIP_LATENCY_CFG                , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_GZIP_LATENCY_CFG );
+REG64_FLD( PU_SU_PERFMON_CONTROL_1_842_LATENCY_CFG                 , 62  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_842_LATENCY_CFG );
+
+REG64_FLD( PU_SU_STATUS_HMI_ACTIVE                                 , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HMI_ACTIVE );
+REG64_FLD( PU_SU_STATUS_PBI_IDLE                                   , 55  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PBI_IDLE   );
+REG64_FLD( PU_SU_STATUS_DMA_CH0_IDLE                               , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_CH0_IDLE );
+REG64_FLD( PU_SU_STATUS_DMA_CH1_IDLE                               , 57  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_CH1_IDLE );
+REG64_FLD( PU_SU_STATUS_DMA_CH2_IDLE                               , 58  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_CH2_IDLE );
+REG64_FLD( PU_SU_STATUS_DMA_CH3_IDLE                               , 59  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_CH3_IDLE );
+REG64_FLD( PU_SU_STATUS_DMA_CH4_IDLE                               , 60  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DMA_CH4_IDLE );
+
+REG64_FLD( PU_SU_UMAC_ERROR_RPT_RPT                                , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RPT        );
+REG64_FLD( PU_SU_UMAC_ERROR_RPT_RPT_LEN                            , 56  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RPT_LEN    );
+
+REG64_FLD( PU_SU_UMAC_ERROR_RPT1_RPT1                              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RPT1       );
+REG64_FLD( PU_SU_UMAC_ERROR_RPT1_RPT1_LEN                          , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RPT1_LEN   );
+
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID              , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LPID );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN          , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LPID_LEN );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID               , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PID );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN           , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PID_LEN );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID               , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_TID );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN           , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_TID_LEN );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE            , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_ENABLE );
+
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY                   , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN               , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LEN );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE              , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_SIZE );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN          , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_SIZE_LEN );
+
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_READ_OFFSET );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_READ_OFFSET_LEN );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED           , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_QUEUED );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN       , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_QUEUED_LEN );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX           , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PRIMAX );
+REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX_LEN       , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PRIMAX_LEN );
+
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID              , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LPID );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN          , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LPID_LEN );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID               , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PID );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN           , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_PID_LEN );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID               , 44  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_TID );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN           , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_TID_LEN );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE            , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_ENABLE );
+
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY                   , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN               , 46  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_LEN );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE              , 54  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_SIZE );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN          , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_SIZE_LEN );
+
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_READ_OFFSET );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_READ_OFFSET_LEN );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED           , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_QUEUED );
+REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN       , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY_QUEUED_LEN );
+
+REG64_FLD( PU_SYM_MAX_BYTE_CNT_LIMIT                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LIMIT      );
+REG64_FLD( PU_SYM_MAX_BYTE_CNT_LIMIT_LEN                           , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_LIMIT_LEN  );
+REG64_FLD( PU_SYM_MAX_BYTE_CNT_SRC_DDE                             , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRC_DDE    );
+REG64_FLD( PU_SYM_MAX_BYTE_CNT_SRC_DDE_LEN                         , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRC_DDE_LEN );
+REG64_FLD( PU_SYM_MAX_BYTE_CNT_TARGET_DDE                          , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_TARGET_DDE );
+REG64_FLD( PU_SYM_MAX_BYTE_CNT_TARGET_DDE_LEN                      , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_TARGET_DDE_LEN );
+
+REG64_FLD( PEC_SYNC_CONFIG_PULSE_DELAY                             , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PULSE_DELAY );
+REG64_FLD( PEC_SYNC_CONFIG_PULSE_DELAY_LEN                         , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PULSE_DELAY_LEN );
+REG64_FLD( PEC_SYNC_CONFIG_LISTEN_TO_PULSE_DIS                     , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_LISTEN_TO_PULSE_DIS );
+REG64_FLD( PEC_SYNC_CONFIG_PULSE_INPUT_SEL                         , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PULSE_INPUT_SEL );
+REG64_FLD( PEC_SYNC_CONFIG_USE_FOR_SCAN                            , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_USE_FOR_SCAN );
+REG64_FLD( PEC_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED                , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CLEAR_CHIPLET_IS_ALIGNED );
+REG64_FLD( PEC_SYNC_CONFIG_UNIT_REGION_CLKCMD_DISABLE              , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT_REGION_CLKCMD_DISABLE );
+REG64_FLD( PEC_SYNC_CONFIG_DISABLE_PCB_ITR                         , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_PCB_ITR );
+REG64_FLD( PEC_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK                 , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_VITL_ALIGN_CHECK );
+REG64_FLD( PEC_SYNC_CONFIG_UNUSED1119                              , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1119 );
+REG64_FLD( PEC_SYNC_CONFIG_UNUSED1119_LEN                          , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1119_LEN );
+
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_INVALID_TRANSFER_SIZE           , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INVALID_TRANSFER_SIZE );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_INVALID_COMMAND                 , 1   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INVALID_COMMAND );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_INVALID_ADDRESS_ALIGNMENT       , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INVALID_ADDRESS_ALIGNMENT );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_OPB_ERROR                       , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OPB_ERROR  );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_OPB_TIMEOUT                     , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OPB_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_OPB_MASTER_HANG_TIMEOUT         , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OPB_MASTER_HANG_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_CMD_BUFFER_PAR_ERR              , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CMD_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_DAT_BUFFER_PAR_ERR              , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DAT_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_RETURNQ_ERR                     , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RETURNQ_ERR );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_RESERVED                        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_SCOM_PARITY_ERR2                , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SCOM_PARITY_ERR2 );
+REG64_FLD( PU_SYNC_FIR_ACTION0_REG_SCOM_PARITY_ERR                 , 11  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SCOM_PARITY_ERR );
+
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_INVALID_TRANSFER_SIZE           , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INVALID_TRANSFER_SIZE );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_INVALID_COMMAND                 , 1   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INVALID_COMMAND );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_INVALID_ADDRESS_ALIGNMENT       , 2   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_INVALID_ADDRESS_ALIGNMENT );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_OPB_ERROR                       , 3   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OPB_ERROR  );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_OPB_TIMEOUT                     , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OPB_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_OPB_MASTER_HANG_TIMEOUT         , 5   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_OPB_MASTER_HANG_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_CMD_BUFFER_PAR_ERR              , 6   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CMD_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_DAT_BUFFER_PAR_ERR              , 7   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DAT_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_RETURNQ_ERR                     , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RETURNQ_ERR );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_RESERVED                        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_SCOM_PARITY_ERR2                , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SCOM_PARITY_ERR2 );
+REG64_FLD( PU_SYNC_FIR_ACTION1_REG_SCOM_PARITY_ERR                 , 11  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_SCOM_PARITY_ERR );
+
+REG64_FLD( PU_SYNC_FIR_MASK_REG_INVALID_TRANSFER_SIZE              , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INVALID_TRANSFER_SIZE );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_INVALID_COMMAND                    , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INVALID_COMMAND );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_INVALID_ADDRESS_ALIGNMENT          , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INVALID_ADDRESS_ALIGNMENT );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_OPB_ERROR                          , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OPB_ERROR  );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_OPB_TIMEOUT                        , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OPB_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_OPB_MASTER_HANG_TIMEOUT            , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OPB_MASTER_HANG_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_CMD_BUFFER_PAR_ERR                 , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CMD_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_DAT_BUFFER_PAR_ERR                 , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DAT_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_RETURNQ_ERR                        , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RETURNQ_ERR );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_RESERVED                           , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_SCOM_PARITY_ERR2                   , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PARITY_ERR2 );
+REG64_FLD( PU_SYNC_FIR_MASK_REG_SCOM_PARITY_ERR                    , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_PARITY_ERR );
+
+REG64_FLD( PU_SYNC_FIR_REG_INVALID_TRANSFER_SIZE                   , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INVALID_TRANSFER_SIZE );
+REG64_FLD( PU_SYNC_FIR_REG_INVALID_COMMAND                         , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INVALID_COMMAND );
+REG64_FLD( PU_SYNC_FIR_REG_INVALID_ADDRESS_ALIGNMENT               , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INVALID_ADDRESS_ALIGNMENT );
+REG64_FLD( PU_SYNC_FIR_REG_OPB_ERROR                               , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OPB_ERROR  );
+REG64_FLD( PU_SYNC_FIR_REG_OPB_TIMEOUT                             , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OPB_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_REG_OPB_MASTER_HANG_TIMEOUT                 , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_OPB_MASTER_HANG_TIMEOUT );
+REG64_FLD( PU_SYNC_FIR_REG_CMD_BUFFER_PAR_ERR                      , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CMD_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_REG_DAT_BUFFER_PAR_ERR                      , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DAT_BUFFER_PAR_ERR );
+REG64_FLD( PU_SYNC_FIR_REG_RETURNQ_ERR                             , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RETURNQ_ERR );
+REG64_FLD( PU_SYNC_FIR_REG_RESERVED                                , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED   );
+REG64_FLD( PU_SYNC_FIR_REG_PARITY_ERR2                             , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARITY_ERR2 );
+REG64_FLD( PU_SYNC_FIR_REG_PARITY_ERR                              , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PARITY_ERR );
+
+REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ALL                      , 0   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INVALIDATE_ALL );
+REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ONE                      , 2   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INVALIDATE_ONE );
+REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_PE_NUMBER                , 4   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INVALIDATE_PE_NUMBER );
+REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_PE_NUMBER_LEN            , 4   , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INVALIDATE_PE_NUMBER_LEN );
+REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ADDRESS                  , 15  , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INVALIDATE_ADDRESS );
+REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ADDRESS_LEN              , 37  , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INVALIDATE_ADDRESS_LEN );
+
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_HI_DATA_REG_DATA              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_HI_DATA_REG_DATA_LEN          , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_DATA              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_DATA_LEN          , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_ADDRESS           , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_ADDRESS_LEN       , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK         , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK_LEN     , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK_VALID   , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_WRITE_ON_RUN      , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_RUNNING           , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS      , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN  , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB      , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND      , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKD         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKD_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_HI_DATA_REG_DATA              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_HI_DATA_REG_DATA_LEN          , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_DATA              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_DATA_LEN          , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_ADDRESS           , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_ADDRESS_LEN       , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK         , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK_LEN     , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK_VALID   , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_WRITE_ON_RUN      , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_RUNNING           , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS      , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN  , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB      , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND      , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKD         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKD_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_HI_DATA_REG_DATA              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_HI_DATA_REG_DATA_LEN          , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_DATA              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_DATA_LEN          , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_ADDRESS           , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_ADDRESS_LEN       , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK         , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK_LEN     , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK_VALID   , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_WRITE_ON_RUN      , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_RUNNING           , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS      , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN  , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB      , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND      , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKD         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKD_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_HI_DATA_REG_DATA              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_HI_DATA_REG_DATA_LEN          , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_DATA              , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_DATA_LEN          , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_ADDRESS           , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_ADDRESS_LEN       , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK         , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK_LEN     , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK_VALID   , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_WRITE_ON_RUN      , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_RUNNING           , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS      , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN  , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB      , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC      , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND      , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN  , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKD         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKD_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_HI_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_HI_DATA_REG_DATA_LEN             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_DATA                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_DATA_LEN             , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_ADDRESS              , 32  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN          , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_LAST_BANK            , 42  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN        , 9   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID      , 51  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN         , 52  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_RUNNING              , 53  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS         , 54  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN     , 10  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC         , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERND         , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN     , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKA            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKB            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKC            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKD            , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT          ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL    , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL    , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK   , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK    , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK   , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE   , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE   , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_HI_DATA_REG_DATA              , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN          , 64  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_DATA              , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN          , 32  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS           , 32  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN       , 10  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK         , 42  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN     , 9   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID   , 51  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN      , 52  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING           , 53  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS      , 54  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN  , 10  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_PEC      ,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA      , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN  , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB      , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN  , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC      , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN  , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND      , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN  , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA         , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN     , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB         , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN     , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC         , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN     , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD         , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN     , 24  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_PEC      ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PU_NPU_SM2_TEST_CERR_ATR_ERR_INJ_PEND                   , 0   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATR_ERR_INJ_PEND );
+REG64_FLD( PU_NPU_SM2_TEST_CERR_MAP_ERR_INJ_PEND                   , 1   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MAP_ERR_INJ_PEND );
+REG64_FLD( PU_NPU_SM2_TEST_CERR_REGSEL                             , 56  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_REGSEL     );
+REG64_FLD( PU_NPU_SM2_TEST_CERR_REGSEL_LEN                         , 2   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_REGSEL_LEN );
+REG64_FLD( PU_NPU_SM2_TEST_CERR_BITSEL                             , 58  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_BITSEL     );
+REG64_FLD( PU_NPU_SM2_TEST_CERR_BITSEL_LEN                         , 6   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_BITSEL_LEN );
+
+REG64_FLD( CAPP_TFMR_CHIP_TOD_STATUS                               , 47  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CHIP_TOD_STATUS );
+REG64_FLD( CAPP_TFMR_CHIP_TOD_STATUS_LEN                           , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CHIP_TOD_STATUS_LEN );
+
+REG64_FLD( PEC_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR                  , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DIS_CPM_BUBBLE_CORR );
+REG64_FLD( PEC_THERM_MODE_REG_FORCE_THRES_ACT                      , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_THRES_ACT );
+REG64_FLD( PEC_THERM_MODE_REG_THRES_TRIP_ENA                       , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_THRES_TRIP_ENA );
+REG64_FLD( PEC_THERM_MODE_REG_THRES_TRIP_ENA_LEN                   , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_THRES_TRIP_ENA_LEN );
+REG64_FLD( PEC_THERM_MODE_REG_DTS_SAMPLE_ENA                       , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DTS_SAMPLE_ENA );
+REG64_FLD( PEC_THERM_MODE_REG_SAMPLE_PULSE_CNT                     , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_PULSE_CNT );
+REG64_FLD( PEC_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN                 , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_PULSE_CNT_LEN );
+REG64_FLD( PEC_THERM_MODE_REG_THRES_ENA                            , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_THRES_ENA  );
+REG64_FLD( PEC_THERM_MODE_REG_THRES_ENA_LEN                        , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_THRES_ENA_LEN );
+REG64_FLD( PEC_THERM_MODE_REG_DTS_TRIGGER                          , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DTS_TRIGGER );
+REG64_FLD( PEC_THERM_MODE_REG_DTS_TRIGGER_SEL                      , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DTS_TRIGGER_SEL );
+REG64_FLD( PEC_THERM_MODE_REG_THRES_OVERFLOW_MASK                  , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_THRES_OVERFLOW_MASK );
+REG64_FLD( PEC_THERM_MODE_REG_UNUSED                               , 15  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PEC_THERM_MODE_REG_DTS_READ_SEL                         , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DTS_READ_SEL );
+REG64_FLD( PEC_THERM_MODE_REG_DTS_READ_SEL_LEN                     , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DTS_READ_SEL_LEN );
+REG64_FLD( PEC_THERM_MODE_REG_DTS_ENABLE_L1                        , 20  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DTS_ENABLE_L1 );
+REG64_FLD( PEC_THERM_MODE_REG_DTS_ENABLE_L1_LEN                    , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DTS_ENABLE_L1_LEN );
+
+REG64_FLD( PEC_TIMESTAMP_COUNTER_READ_VALUE                        , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_VALUE      );
+REG64_FLD( PEC_TIMESTAMP_COUNTER_READ_VALUE_LEN                    , 44  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_VALUE_LEN  );
+REG64_FLD( PEC_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR                 , 44  , SH_UNT_PEC      , SH_ACS_SCOM_RO  ,
+           SH_FLD_OVERFLOW_ERR );
+
+REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_TIMEOUT                       , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_IN_TIMEOUT );
+REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SEQ_ERR                       , 1   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_IN_SEQ_ERR );
+REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SEQ_PERR                      , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_IN_SEQ_PERR );
+REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_BAD_OP_ERR                    , 3   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_IN_BAD_OP_ERR );
+REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SNP_ADDR_PERR                 , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_IN_SNP_ADDR_PERR );
+REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SNP_TTAG_PERR                 , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_IN_SNP_TTAG_PERR );
+
+REG64_FLD( PU_TOD_CMD_REG_ADR                                      , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADR        );
+REG64_FLD( PU_TOD_CMD_REG_ADR_LEN                                  , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADR_LEN    );
+
+REG64_FLD( PU_TOD_DATA_RCV_REG_PCB                                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCB        );
+REG64_FLD( PU_TOD_DATA_RCV_REG_PCB_LEN                             , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCB_LEN    );
+
+REG64_FLD( PU_TOD_DATA_SND_REG_PCB                                 , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PCB        );
+REG64_FLD( PU_TOD_DATA_SND_REG_PCB_LEN                             , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PCB_LEN    );
+
+REG64_FLD( CAPP_TOD_SYNC000_TIMEBASE                               , 55  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( CAPP_TOD_SYNC000_TIMEBASE_LEN                           , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( CAPP_TOD_SYNC000_CHIP_STATUS                            , 60  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( CAPP_TOD_SYNC000_CHIP_STATUS_LEN                        , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( PU_TRUST_CONTROL_FSP_TCE_ENABLE                         , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FSP_TCE_ENABLE );
+
+REG64_FLD( PEC_TUNNEL_BAR_REG_PE                                   , 0   , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE         );
+REG64_FLD( PEC_TUNNEL_BAR_REG_PE_LEN                               , 43  , SH_UNT_PEC      , SH_ACS_SCOM_RW  ,
+           SH_FLD_PE_LEN     );
+
+REG64_FLD( PU_TX_CTRL_STAT_REG_ENABLE_SCWR_TO_TXRF                 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_SCWR_TO_TXRF );
+REG64_FLD( PU_TX_CTRL_STAT_REG_DISABLE_ECC_COR_GXC_PSI             , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_ECC_COR_GXC_PSI );
+REG64_FLD( PU_TX_CTRL_STAT_REG_DISABLE_ECC_COR_TXRF_PSI            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_ECC_COR_TXRF_PSI );
+REG64_FLD( PU_TX_CTRL_STAT_REG_CRC_MODE                            , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CRC_MODE   );
+REG64_FLD( PU_TX_CTRL_STAT_REG_CHIP_PERSONALISATION                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHIP_PERSONALISATION );
+REG64_FLD( PU_TX_CTRL_STAT_REG_ENABLE_STREAMING_MODE               , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_STREAMING_MODE );
+REG64_FLD( PU_TX_CTRL_STAT_REG_CHIP_INTERFACEMODE                  , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CHIP_INTERFACEMODE );
+REG64_FLD( PU_TX_CTRL_STAT_REG_DISABLE_TIMEOUT_AND_RETRY           , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_TIMEOUT_AND_RETRY );
+REG64_FLD( PU_TX_CTRL_STAT_REG_FENCE_IO_INTERFACE                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FENCE_IO_INTERFACE );
+REG64_FLD( PU_TX_CTRL_STAT_REG_FENCE_GX_INTERFACE                  , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FENCE_GX_INTERFACE );
+REG64_FLD( PU_TX_CTRL_STAT_REG_GX_ENABLE_OVERWRITE                 , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_GX_ENABLE_OVERWRITE );
+
+REG64_FLD( PU_TX_MASK_REG_PSITXINS_DATA_PCK                        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXINS_DATA_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXINS_TZRTMP_PCK                      , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXINS_TZRTMP_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXEI_SHIFT_PCK                        , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXEI_SHIFT_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXEI_TRANSMIT_PCK                     , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXEI_TRANSMIT_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXINS_PARITY                          , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXINS_PARITY );
+REG64_FLD( PU_TX_MASK_REG_PSITXINS_UNDERRUN                        , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXINS_UNDERRUN );
+REG64_FLD( PU_TX_MASK_REG_PSITXBFF_DATA_PCK                        , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXBFF_DATA_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXBFF_TDO_PCK                         , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXBFF_TDO_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXBFF_TFC_PCK                         , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXBFF_TFC_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_FSM_PCK                          , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXLC_FSM_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_DATA_BUFF_PCK                    , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXLC_DATA_BUFF_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_TDO_PCK                          , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXLC_TDO_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_TADDR_PCK                        , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXLC_TADDR_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_TCTRL_PCK                        , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXLC_TCTRL_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_UE_RF                            , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXLC_UE_RF );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_CE_RF                            , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXLC_CE_RF );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_UE_GX_2N                         , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXLC_UE_GX_2N );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_CE_GX_2N                         , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXLC_CE_GX_2N );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_DATA_GXST2_PCK_2N                , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXLC_DATA_GXST2_PCK_2N );
+REG64_FLD( PU_TX_MASK_REG_PSITXLC_DATA_GXST3_PCK_2N                , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSITXLC_DATA_GXST3_PCK_2N );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TADDR_PCK                       , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRFACC_TADDR_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TCTRL_PCK                       , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRFACC_TCTRL_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TDL_CMD_CTRL_PCK                , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRFACC_TDL_CMD_CTRL_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TDL_RSP_CTRL_PCK                , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRFACC_TDL_RSP_CTRL_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TFSM_PCK                        , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRFACC_TFSM_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TDL_FSM_PCK                     , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRFACC_TDL_FSM_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TXSC_PCK                        , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRFACC_TXSC_PCK );
+REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TDL_RETRY_ERR                   , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PSIRFACC_TDL_RETRY_ERR );
+
+REG64_FLD( PU_TX_PSI_CNTL_DRV_PATTERN_EN                           , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DRV_PATTERN_EN );
+REG64_FLD( PU_TX_PSI_CNTL_PATTERN_SEL                              , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERN_SEL );
+REG64_FLD( PU_TX_PSI_CNTL_PATTERN_SEL_LEN                          , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PATTERN_SEL_LEN );
+REG64_FLD( PU_TX_PSI_CNTL_CLK_QUIESCE_P                            , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CLK_QUIESCE_P );
+REG64_FLD( PU_TX_PSI_CNTL_CLK_QUIESCE_P_LEN                        , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CLK_QUIESCE_P_LEN );
+REG64_FLD( PU_TX_PSI_CNTL_CLK_QUIESCE_N                            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CLK_QUIESCE_N );
+REG64_FLD( PU_TX_PSI_CNTL_CLK_QUIESCE_N_LEN                        , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CLK_QUIESCE_N_LEN );
+REG64_FLD( PU_TX_PSI_CNTL_LANE_QUIESCE                             , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( PU_TX_PSI_CNTL_LANE_QUIESCE_LEN                         , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( PU_TX_PSI_CNTL_CLK_INVERT                               , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CLK_INVERT );
+REG64_FLD( PU_TX_PSI_CNTL_LANE_INVERT                              , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( PU_TX_PSI_CNTL_PDWN                                     , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PDWN       );
+REG64_FLD( PU_TX_PSI_CNTL_BIST_EN                                  , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EN    );
+REG64_FLD( PU_TX_PSI_CNTL_SPARE                                    , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_TX_PSI_CNTL_SPARE_LEN                                , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+
+REG64_FLD( PU_TX_PSI_MODE_PC_TEST                                  , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PC_TEST    );
+REG64_FLD( PU_TX_PSI_MODE_MAIN_SLICE_EN_ENC                        , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAIN_SLICE_EN_ENC );
+REG64_FLD( PU_TX_PSI_MODE_MAIN_SLICE_EN_ENC_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MAIN_SLICE_EN_ENC_LEN );
+REG64_FLD( PU_TX_PSI_MODE_PC_SLICE_EN_ENC                          , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PC_SLICE_EN_ENC );
+REG64_FLD( PU_TX_PSI_MODE_PC_SLICE_EN_ENC_LEN                      , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PC_SLICE_EN_ENC_LEN );
+REG64_FLD( PU_TX_PSI_MODE_SLEWCTL                                  , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SLEWCTL    );
+REG64_FLD( PU_TX_PSI_MODE_SLEWCTL_LEN                              , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SLEWCTL_LEN );
+REG64_FLD( PU_TX_PSI_MODE_PVTNL_ENC                                , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PVTNL_ENC  );
+REG64_FLD( PU_TX_PSI_MODE_PVTNL_ENC_LEN                            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PVTNL_ENC_LEN );
+REG64_FLD( PU_TX_PSI_MODE_PVTPL_ENC                                , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PVTPL_ENC  );
+REG64_FLD( PU_TX_PSI_MODE_PVTPL_ENC_LEN                            , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PVTPL_ENC_LEN );
+
+REG64_FLD( PU_TX_PSI_STATUS_SPARE                                  , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_TX_PSI_STATUS_SPARE_LEN                              , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_TX_PSI_STATUS_BIST_ERROR                             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERROR );
+REG64_FLD( PU_TX_PSI_STATUS_BIST_ERROR_LEN                         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERROR_LEN );
+
+REG64_FLD( PU_TX_TO_RT_REG_TIMEOUT_VALUE                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_VALUE );
+REG64_FLD( PU_TX_TO_RT_REG_TIMEOUT_VALUE_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_VALUE_LEN );
+REG64_FLD( PU_TX_TO_RT_REG_RETRY_VALUE                             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RETRY_VALUE );
+REG64_FLD( PU_TX_TO_RT_REG_RETRY_VALUE_LEN                         , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RETRY_VALUE_LEN );
+
+REG64_FLD( PU_UMAC_STATUS_CONTROL_CRB_READS_ENBL                   , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CRB_READS_ENBL );
+REG64_FLD( PU_UMAC_STATUS_CONTROL_CRB_READS_HALTED                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CRB_READS_HALTED );
+REG64_FLD( PU_UMAC_STATUS_CONTROL_IDLE                             , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IDLE       );
+REG64_FLD( PU_UMAC_STATUS_CONTROL_QUIESCE_REQUEST                  , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUIESCE_REQUEST );
+REG64_FLD( PU_UMAC_STATUS_CONTROL_QUIESCE_ACHEIVED                 , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUIESCE_ACHEIVED );
+REG64_FLD( PU_UMAC_STATUS_CONTROL_QUIESCE_FAILED                   , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUIESCE_FAILED );
+REG64_FLD( PU_UMAC_STATUS_CONTROL_QUIESCED                         , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_QUIESCED   );
+REG64_FLD( PU_UMAC_STATUS_CONTROL_PASTE_ADDR_ALIGN                 , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PASTE_ADDR_ALIGN );
+
+REG64_FLD( PU_VAS_BUFCTL_TOTAL_FREE_BUF_COUNT                      , 49  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TOTAL_FREE_BUF_COUNT );
+REG64_FLD( PU_VAS_BUFCTL_TOTAL_FREE_BUF_COUNT_LEN                  , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_TOTAL_FREE_BUF_COUNT_LEN );
+REG64_FLD( PU_VAS_BUFCTL_CONSUMED_BUF_COUNT                        , 57  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CONSUMED_BUF_COUNT );
+REG64_FLD( PU_VAS_BUFCTL_CONSUMED_BUF_COUNT_LEN                    , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CONSUMED_BUF_COUNT_LEN );
+
+REG64_FLD( PU_VAS_CAMDATA0_CAM_DISPLAY_REG_0                       , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CAM_DISPLAY_REG_0 );
+REG64_FLD( PU_VAS_CAMDATA0_CAM_DISPLAY_REG_0_LEN                   , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CAM_DISPLAY_REG_0_LEN );
+
+REG64_FLD( PU_VAS_CAMDATA1_CAM_DISPLAY_REG_1                       , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CAM_DISPLAY_REG_1 );
+REG64_FLD( PU_VAS_CAMDATA1_CAM_DISPLAY_REG_1_LEN                   , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_CAM_DISPLAY_REG_1_LEN );
+
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_RESET                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_RESET );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT4                            , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT4 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT5                            , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT5 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT6                            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT6 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT7                            , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT7 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT8                            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT8 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT9                            , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT9 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT10                           , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT10 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT11                           , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT11 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT12                           , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT12 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT13                           , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT13 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT14                           , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT14 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT15                           , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT15 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT16                           , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT16 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT17                           , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT17 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT18                           , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT18 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT19                           , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT19 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT20                           , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT20 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT21                           , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT21 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT22                           , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT22 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT23                           , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT23 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT24                           , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT24 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT25                           , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT25 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT26                           , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT26 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT27                           , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT27 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT28                           , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT28 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT29                           , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT29 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT30                           , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT30 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT31                           , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT31 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT32                           , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT32 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT33                           , 33  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT33 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT34                           , 34  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT34 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT35                           , 35  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT35 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT36                           , 36  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT36 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT37                           , 37  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT37 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT38                           , 38  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT38 );
+REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT39                           , 39  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CQ_CERR_BIT39 );
+
+REG64_FLD( PU_VAS_DBGCONT_TRACE_BUS_BITS_0_63                      , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_TRACE_BUS_BITS_0_63 );
+REG64_FLD( PU_VAS_DBGCONT_TRACE_BUS_BITS_0_63_LEN                  , 64  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_TRACE_BUS_BITS_0_63_LEN );
+
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_LO                    , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_RG_TRACE_DATA_LO );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_LO_LEN                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_RG_TRACE_DATA_LO_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_HI                    , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_RG_TRACE_DATA_HI );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_HI_LEN                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_RG_TRACE_DATA_HI_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_01                      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_RG_TRIGGERS_01 );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_01_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_RG_TRIGGERS_01_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_23                      , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_RG_TRIGGERS_23 );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_23_LEN                  , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_RG_TRIGGERS_23_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_LO                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IN_TRACE_GROUP_SEL_LO );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_LO_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IN_TRACE_GROUP_SEL_LO_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_HI                   , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IN_TRACE_GROUP_SEL_HI );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_HI_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IN_TRACE_GROUP_SEL_HI_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_01                 , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IN_TRACE_TRIGGER_SEL_01 );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_01_LEN             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IN_TRACE_TRIGGER_SEL_01_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_23                 , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IN_TRACE_TRIGGER_SEL_23 );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_23_LEN             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IN_TRACE_TRIGGER_SEL_23_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_LO                   , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RG_TRACE_GROUP_SEL_LO );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_LO_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RG_TRACE_GROUP_SEL_LO_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_HI                   , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RG_TRACE_GROUP_SEL_HI );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_HI_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RG_TRACE_GROUP_SEL_HI_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_01                 , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RG_TRACE_TRIGGER_SEL_01 );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_01_LEN             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RG_TRACE_TRIGGER_SEL_01_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_23                 , 29  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RG_TRACE_TRIGGER_SEL_23 );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_23_LEN             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RG_TRACE_TRIGGER_SEL_23_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_ENABLE_IN_TRACE                         , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_IN_TRACE );
+REG64_FLD( PU_VAS_DBGNORTH_ENABLE_RG_TRACE                         , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_RG_TRACE );
+REG64_FLD( PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS0                  , 34  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_NORTH_UNUSED_BITS0 );
+REG64_FLD( PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS0_LEN              , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_NORTH_UNUSED_BITS0_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_PMU_DATA                         , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEL_RG_PMU_DATA );
+REG64_FLD( PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS1                  , 37  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_NORTH_UNUSED_BITS1 );
+REG64_FLD( PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS1_LEN              , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DBG_NORTH_UNUSED_BITS1_LEN );
+REG64_FLD( PU_VAS_DBGNORTH_ENABLE_IN_PMU_COUNTING                  , 40  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_IN_PMU_COUNTING );
+REG64_FLD( PU_VAS_DBGNORTH_ENABLE_RG_PMU_COUNTING                  , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_RG_PMU_COUNTING );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_INT_DATA_LO                    , 42  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IN_TRACE_INT_DATA_LO );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_INT_DATA_HI                    , 43  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IN_TRACE_INT_DATA_HI );
+REG64_FLD( PU_VAS_DBGNORTH_EG_TRACE_INT_DATA_LO                    , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_INT_DATA_LO );
+REG64_FLD( PU_VAS_DBGNORTH_EG_TRACE_INT_DATA_HI                    , 45  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_INT_DATA_HI );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_INT_DATA_LO                    , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RG_TRACE_INT_DATA_LO );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_INT_DATA_HI                    , 47  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RG_TRACE_INT_DATA_HI );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_INT_TRIG_01                    , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IN_TRACE_INT_TRIG_01 );
+REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_INT_TRIG_23                    , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_IN_TRACE_INT_TRIG_23 );
+REG64_FLD( PU_VAS_DBGNORTH_EG_TRACE_INT_TRIG_01                    , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_INT_TRIG_01 );
+REG64_FLD( PU_VAS_DBGNORTH_EG_TRACE_INT_TRIG_23                    , 51  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_INT_TRIG_23 );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_INT_TRIG_01                    , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RG_TRACE_INT_TRIG_01 );
+REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_INT_TRIG_23                    , 53  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RG_TRACE_INT_TRIG_23 );
+
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_DATA_LO               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PASS_WC_INT_TRACE_DATA_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_DATA_HI               , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PASS_WC_INT_TRACE_DATA_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_DATA_LO               , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PASS_CQ_INT_TRACE_DATA_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_DATA_HI               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PASS_CQ_INT_TRACE_DATA_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_TRIG_01               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PASS_WC_INT_TRACE_TRIG_01 );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_TRIG_23               , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PASS_WC_INT_TRACE_TRIG_23 );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_TRIG_01               , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PASS_CQ_INT_TRACE_TRIG_01 );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_TRIG_23               , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PASS_CQ_INT_TRACE_TRIG_23 );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_LO                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_GROUP_SEL_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_LO_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_GROUP_SEL_LO_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_HI                   , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_GROUP_SEL_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_HI_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_GROUP_SEL_HI_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_01                 , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_TRIGGER_SEL_01 );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_01_LEN             , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_TRIGGER_SEL_01_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_23                 , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_TRIGGER_SEL_23 );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_23_LEN             , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_TRIGGER_SEL_23_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_LO                   , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WC_TRACE_GROUP_SEL_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_LO_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WC_TRACE_GROUP_SEL_LO_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_HI                   , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WC_TRACE_GROUP_SEL_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_HI_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WC_TRACE_GROUP_SEL_HI_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_01                 , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WC_TRACE_TRIGGER_SEL_01 );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_01_LEN             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WC_TRACE_TRIGGER_SEL_01_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_23                 , 29  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WC_TRACE_TRIGGER_SEL_23 );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_23_LEN             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WC_TRACE_TRIGGER_SEL_23_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_LO                   , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CQ_TRACE_GROUP_SEL_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_LO_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CQ_TRACE_GROUP_SEL_LO_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_HI                   , 35  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CQ_TRACE_GROUP_SEL_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_HI_LEN               , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CQ_TRACE_GROUP_SEL_HI_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_01                 , 38  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CQ_TRACE_TRIGGER_SEL_01 );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_01_LEN             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CQ_TRACE_TRIGGER_SEL_01_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_23                 , 41  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CQ_TRACE_TRIGGER_SEL_23 );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_23_LEN             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CQ_TRACE_TRIGGER_SEL_23_LEN );
+REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_EG_TRACE                         , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_EG_TRACE );
+REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_WC_TRACE                         , 45  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_WC_TRACE );
+REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_CQ_TRACE                         , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_CQ_TRACE );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_INT_DATA_LO                    , 47  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WC_TRACE_INT_DATA_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_INT_DATA_HI                    , 48  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WC_TRACE_INT_DATA_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_INT_DATA_LO                    , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_INT_DATA_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_PMU_DATA_LO                 , 50  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PASS_CQ_INT_PMU_DATA_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_PMU_DATA_HI                 , 51  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PASS_CQ_INT_PMU_DATA_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_EG_PMU_COUNTING                  , 52  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_EG_PMU_COUNTING );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_INT_DATA_HI                    , 53  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_INT_DATA_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_CQ_PMU_COUNTING                  , 54  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_CQ_PMU_COUNTING );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_INT_DATA_LO                    , 55  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CQ_TRACE_INT_DATA_LO );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_INT_DATA_HI                    , 56  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CQ_TRACE_INT_DATA_HI );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_INT_TRIG_01                    , 57  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WC_TRACE_INT_TRIG_01 );
+REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_INT_TRIG_23                    , 58  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WC_TRACE_INT_TRIG_23 );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_INT_TRIG_01                    , 59  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_INT_TRIG_01 );
+REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_INT_TRIG_23                    , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_EG_TRACE_INT_TRIG_23 );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_INT_TRIG_01                    , 61  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CQ_TRACE_INT_TRIG_01 );
+REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_INT_TRIG_23                    , 62  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CQ_TRACE_INT_TRIG_23 );
+
+REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_BITS_64_87                     , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_TRACE_BUS_BITS_64_87 );
+REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_BITS_64_87_LEN                 , 24  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_TRACE_BUS_BITS_64_87_LEN );
+REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_TRIGGER_BITS                   , 24  , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_TRACE_BUS_TRIGGER_BITS );
+REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_TRIGGER_BITS_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_TRACE_BUS_TRIGGER_BITS_LEN );
+
+REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_RESET                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EG_CERR_RESET );
+REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT4                            , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EG_CERR_BIT4 );
+REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT5                            , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EG_CERR_BIT5 );
+REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT6                            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EG_CERR_BIT6 );
+REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT7                            , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EG_CERR_BIT7 );
+REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT8                            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EG_CERR_BIT8 );
+REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT9                            , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EG_CERR_BIT9 );
+REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT10                           , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EG_CERR_BIT10 );
+REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT11                           , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EG_CERR_BIT11 );
+REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_UNUSEDBITS                      , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EG_CERR_UNUSEDBITS );
+REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_UNUSEDBITS_LEN                  , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_EG_CERR_UNUSEDBITS_LEN );
+
+REG64_FLD( PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_ENA                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_NORTH_WC_ENA );
+REG64_FLD( PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_TYP                , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_NORTH_WC_TYP );
+REG64_FLD( PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_FRQ                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_NORTH_WC_FRQ );
+REG64_FLD( PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_UNUSED             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_NORTH_WC_UNUSED );
+REG64_FLD( PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_UNUSED_LEN         , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_NORTH_WC_UNUSED_LEN );
+
+REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_ENA                , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_SOUTH_WC_ENA );
+REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_TYP                , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_SOUTH_WC_TYP );
+REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_FRQ                , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_SOUTH_WC_FRQ );
+REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_SEL                , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_SOUTH_WC_SEL );
+REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_SEL_LEN            , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_SOUTH_WC_SEL_LEN );
+REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_ENA                , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_SOUTH_EG_ENA );
+REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_TYP                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_SOUTH_EG_TYP );
+REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_FRQ                , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_SOUTH_EG_FRQ );
+REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_SEL                , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_SOUTH_EG_SEL );
+REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_UNUSED                , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_SOUTH_UNUSED );
+REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_UNUSED_LEN            , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ECC_ERR_INJ_SOUTH_UNUSED_LEN );
+
+REG64_FLD( PU_VAS_FIR_ACTION0_REG_ACTION0                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( PU_VAS_FIR_ACTION0_REG_ACTION0_LEN                      , 54  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( PU_VAS_FIR_ACTION1_REG_ACTION1                          , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( PU_VAS_FIR_ACTION1_REG_ACTION1_LEN                      , 54  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( PU_VAS_FIR_MASK_REG_EG_LOGIC_HW_ERROR                   , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_EG_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_IN_LOGIC_HW_ERROR                   , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_LOGIC_HW_ERROR                   , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_WC_LOGIC_HW_ERROR                   , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WC_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_RG_LOGIC_HW_ERROR                   , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RG_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_PARITY_ERROR                  , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_PARITY_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_RD_ADDR_ERROR                 , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_RD_ADDR_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_WR_ADDR_ERROR                 , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_WR_ADDR_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_EG_ECC_CE_ERROR                     , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_EG_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_IN_ECC_CE_ERROR                     , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_ECC_CE_ERROR                     , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_WC_ECC_CE_ERROR                     , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WC_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_RG_ECC_CE_ERROR                     , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RG_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_OB_CE_ERROR                   , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_OB_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_OB_UE_ERROR                   , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_OB_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_MASTER_FSM_HANG               , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_MASTER_FSM_HANG );
+REG64_FLD( PU_VAS_FIR_MASK_REG_EG_ECC_UE_ERROR                     , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_EG_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_IN_ECC_UE_ERROR                     , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_ECC_UE_ERROR                     , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_WC_ECC_UE_ERROR                     , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WC_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_RG_ECC_UE_ERROR                     , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RG_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_IN_PARITY_ERROR                     , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN_PARITY_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_IN_SW_CAST_ERROR                    , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN_SW_CAST_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_EG_ECC_SUE_ERROR                    , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_EG_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_IN_ECC_SUE_ERROR                    , 25  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_ECC_SUE_ERROR                    , 26  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_WC_ECC_SUE_ERROR                    , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WC_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_RG_ECC_SUE_ERROR                    , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RG_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_RD_LINK_ERROR                 , 29  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_RD_LINK_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_WR_LINK_ERROR                 , 30  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_WR_LINK_ERROR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_LINK_ABORT                    , 31  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_LINK_ABORT );
+REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_HYP_RD_ADDR_ERR                , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MMIO_HYP_RD_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_OS_RD_ADDR_ERR                 , 33  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MMIO_OS_RD_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_HYP_WR_ADDR_ERR                , 34  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MMIO_HYP_WR_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_OS_WR_ADDR_ERR                 , 35  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MMIO_OS_WR_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_NON8B_HYP_ERR                  , 36  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MMIO_NON8B_HYP_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_NON8B_OS_ERR                   , 37  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MMIO_NON8B_OS_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_WM_WIN_NOT_OPEN_ERR                 , 38  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WM_WIN_NOT_OPEN_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_WM_MULTIHIT_ERR                     , 39  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WM_MULTIHIT_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_PG_MIG_DISABLED_ERR                 , 40  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PG_MIG_DISABLED_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_PG_MIG_SIZE_MISMATCH_ERR            , 41  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PG_MIG_SIZE_MISMATCH_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_NOTIFY_FAILED_ERR                   , 42  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_NOTIFY_FAILED_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_WR_MON_NOT_DISABLED_ERR             , 43  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WR_MON_NOT_DISABLED_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_REJECTED_PASTE_CMD                  , 44  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_REJECTED_PASTE_CMD );
+REG64_FLD( PU_VAS_FIR_MASK_REG_DATA_HANG_DETECTED                  , 45  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA_HANG_DETECTED );
+REG64_FLD( PU_VAS_FIR_MASK_REG_INCOMING_PB_PARITY_ERR              , 46  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INCOMING_PB_PARITY_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_SCOM1_SAT_ERR                       , 47  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM1_SAT_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_NX_LOCAL_XSTOP                      , 48  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_NX_LOCAL_XSTOP );
+REG64_FLD( PU_VAS_FIR_MASK_REG_SCOM_MMIO_ADDR_ERR                  , 49  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_MMIO_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_MASK_REG_UNUSED50                            , 50  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UNUSED50   );
+REG64_FLD( PU_VAS_FIR_MASK_REG_UNUSED51                            , 51  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UNUSED51   );
+REG64_FLD( PU_VAS_FIR_MASK_REG_SCOMFIR_INT_ERR_0                   , 52  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOMFIR_INT_ERR_0 );
+REG64_FLD( PU_VAS_FIR_MASK_REG_SCOMFIR_INT_ERR_1                   , 53  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOMFIR_INT_ERR_1 );
+
+REG64_FLD( PU_VAS_FIR_REG_EG_LOGIC_HW_ERROR                        , 0   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_EG_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_IN_LOGIC_HW_ERROR                        , 1   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_LOGIC_HW_ERROR                        , 2   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_WC_LOGIC_HW_ERROR                        , 3   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WC_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_RG_LOGIC_HW_ERROR                        , 4   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RG_LOGIC_HW_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_PARITY_ERROR                       , 5   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_PARITY_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_RD_ADDR_ERROR                      , 6   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_RD_ADDR_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_WR_ADDR_ERROR                      , 7   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_WR_ADDR_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_EG_ECC_CE_ERROR                          , 8   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_EG_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_IN_ECC_CE_ERROR                          , 9   , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_ECC_CE_ERROR                          , 10  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_WC_ECC_CE_ERROR                          , 11  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WC_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_RG_ECC_CE_ERROR                          , 12  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RG_ECC_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_OB_CE_ERROR                        , 13  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_OB_CE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_OB_UE_ERROR                        , 14  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_OB_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_MASTER_FSM_HANG                    , 15  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_MASTER_FSM_HANG );
+REG64_FLD( PU_VAS_FIR_REG_EG_ECC_UE_ERROR                          , 16  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_EG_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_IN_ECC_UE_ERROR                          , 17  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_ECC_UE_ERROR                          , 18  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_WC_ECC_UE_ERROR                          , 19  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WC_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_RG_ECC_UE_ERROR                          , 20  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RG_ECC_UE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_IN_PARITY_ERROR                          , 21  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN_PARITY_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_IN_SW_CAST_ERROR                         , 22  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN_SW_CAST_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_EG_ECC_SUE_ERROR                         , 24  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_EG_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_IN_ECC_SUE_ERROR                         , 25  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_ECC_SUE_ERROR                         , 26  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_WC_ECC_SUE_ERROR                         , 27  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WC_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_RG_ECC_SUE_ERROR                         , 28  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_RG_ECC_SUE_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_RD_LINK_ERROR                      , 29  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_RD_LINK_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_WR_LINK_ERROR                      , 30  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_WR_LINK_ERROR );
+REG64_FLD( PU_VAS_FIR_REG_CQ_PB_LINK_ABORT                         , 31  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_CQ_PB_LINK_ABORT );
+REG64_FLD( PU_VAS_FIR_REG_MMIO_HYP_RD_ADDR_ERR                     , 32  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MMIO_HYP_RD_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_REG_MMIO_OS_RD_ADDR_ERR                      , 33  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MMIO_OS_RD_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_REG_MMIO_HYP_WR_ADDR_ERR                     , 34  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MMIO_HYP_WR_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_REG_MMIO_OS_WR_ADDR_ERR                      , 35  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MMIO_OS_WR_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_REG_MMIO_NON8B_HYP_ERR                       , 36  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MMIO_NON8B_HYP_ERR );
+REG64_FLD( PU_VAS_FIR_REG_MMIO_NON8B_OS_ERR                        , 37  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_MMIO_NON8B_OS_ERR );
+REG64_FLD( PU_VAS_FIR_REG_WM_WIN_NOT_OPEN_ERR                      , 38  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WM_WIN_NOT_OPEN_ERR );
+REG64_FLD( PU_VAS_FIR_REG_WM_MULTIHIT_ERR                          , 39  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WM_MULTIHIT_ERR );
+REG64_FLD( PU_VAS_FIR_REG_PG_MIG_DISABLED_ERR                      , 40  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PG_MIG_DISABLED_ERR );
+REG64_FLD( PU_VAS_FIR_REG_PG_MIG_SIZE_MISMATCH_ERR                 , 41  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_PG_MIG_SIZE_MISMATCH_ERR );
+REG64_FLD( PU_VAS_FIR_REG_NOTIFY_FAILED_ERR                        , 42  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_NOTIFY_FAILED_ERR );
+REG64_FLD( PU_VAS_FIR_REG_WR_MON_NOT_DISABLED_ERR                  , 43  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_WR_MON_NOT_DISABLED_ERR );
+REG64_FLD( PU_VAS_FIR_REG_REJECTED_PASTE_CMD                       , 44  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_REJECTED_PASTE_CMD );
+REG64_FLD( PU_VAS_FIR_REG_DATA_HANG_DETECTED                       , 45  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA_HANG_DETECTED );
+REG64_FLD( PU_VAS_FIR_REG_INCOMING_PB_PARITY_ERR                   , 46  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_INCOMING_PB_PARITY_ERR );
+REG64_FLD( PU_VAS_FIR_REG_SCOM1_SAT_ERR                            , 47  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM1_SAT_ERR );
+REG64_FLD( PU_VAS_FIR_REG_NX_LOCAL_XSTOP                           , 48  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_NX_LOCAL_XSTOP );
+REG64_FLD( PU_VAS_FIR_REG_SCOM_MMIO_ADDR_ERR                       , 49  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_MMIO_ADDR_ERR );
+REG64_FLD( PU_VAS_FIR_REG_UNUSED50                                 , 50  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UNUSED50   );
+REG64_FLD( PU_VAS_FIR_REG_UNUSED51                                 , 51  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_UNUSED51   );
+REG64_FLD( PU_VAS_FIR_REG_SCOMFIR_INT_ERR_0                        , 52  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOMFIR_INT_ERR_0 );
+REG64_FLD( PU_VAS_FIR_REG_SCOMFIR_INT_ERR_1                        , 53  , SH_UNT          , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOMFIR_INT_ERR_1 );
+
+REG64_FLD( PU_VAS_FIR_WOF_REG_WOF                                  , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_WOF        );
+REG64_FLD( PU_VAS_FIR_WOF_REG_WOF_LEN                              , 54  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_WOF_LEN    );
+
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_RESET                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_RESET );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT4                            , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT4 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT5                            , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT5 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT6                            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT6 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT7                            , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT7 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT8                            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT8 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT9                            , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT9 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT10                           , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT10 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT11                           , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT11 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT12                           , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT12 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT13                           , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT13 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT14                           , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT14 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT15                           , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT15 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT16                           , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT16 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT17                           , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT17 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT18                           , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT18 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT19                           , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT19 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT20                           , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT20 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT21                           , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT21 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT22                           , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT22 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT23                           , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT23 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT24                           , 24  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT24 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT25                           , 25  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT25 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT26                           , 26  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT26 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT27                           , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT27 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT28                           , 28  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT28 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT29                           , 29  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT29 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT30                           , 30  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT30 );
+REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT31                           , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_IN_CERR_BIT31 );
+
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_4VS64                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_4VS64 );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_ACCEPT_PASTE                    , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_ACCEPT_PASTE );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_ENABLE_WRMON                    , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_ENABLE_WRMON );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_DISABLE_PUSH2MEM_LIMIT          , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_DISABLE_PUSH2MEM_LIMIT );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_QUIESCE_REQUEST                 , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_QUIESCE_REQUEST );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_PREFETCH_DISABLE                , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_PREFETCH_DISABLE );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_UNUSED_BITS );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS_LEN                 , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_UNUSED_BITS_LEN );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_INVALIDATE_CAM_LOC              , 47  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_INVALIDATE_CAM_LOC );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_INVALIDATE_CAM_ALL              , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_INVALIDATE_CAM_ALL );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_CAM_LOCATION                    , 49  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_CAM_LOCATION );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_CAM_LOCATION_LEN                , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_CAM_LOCATION_LEN );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_CAM_INVAL_DONE                  , 56  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_CAM_INVAL_DONE );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS2                    , 57  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_UNUSED_BITS2 );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_HMI_ACTIVE                      , 58  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_HMI_ACTIVE );
+REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_RG_IS_IDLE                      , 59  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CTL_RG_IS_IDLE );
+
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_INIT                            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MMIO_CTL_INIT );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_COMP                            , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MMIO_CTL_COMP );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_OPTYPE                          , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MMIO_CTL_OPTYPE );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_ACTYPE                          , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MMIO_CTL_ACTYPE );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_OP_ERR                          , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MMIO_CTL_OP_ERR );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_UNUSED                          , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MMIO_CTL_UNUSED );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_UNUSED_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MMIO_CTL_UNUSED_LEN );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_OFFSET                          , 36  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MMIO_CTL_OFFSET );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_OFFSET_LEN                      , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MMIO_CTL_OFFSET_LEN );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_WINID                           , 48  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MMIO_CTL_WINID );
+REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_WINID_LEN                       , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_MMIO_CTL_WINID_LEN );
+
+REG64_FLD( PU_VAS_MMIODATA_MMIO_DATA                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MMIO_DATA  );
+REG64_FLD( PU_VAS_MMIODATA_MMIO_DATA_LEN                           , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_MMIO_DATA_LEN );
+
+REG64_FLD( PU_VAS_MMIOECC_MMIO_ECC                                 , 0   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MMIO_ECC   );
+REG64_FLD( PU_VAS_MMIOECC_MMIO_ECC_LEN                             , 8   , SH_UNT          , SH_ACS_SCOM_RO  ,
+           SH_FLD_MMIO_ECC_LEN );
+
+REG64_FLD( PU_VAS_MMIO_BASE_ADDR_BAR                               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR        );
+REG64_FLD( PU_VAS_MMIO_BASE_ADDR_BAR_LEN                           , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR_LEN    );
+
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_EPSILON                           , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_EPSILON );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_EPSILON_LEN                       , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_EPSILON_LEN );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_HANG_POLL_MAX_CNT                 , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_HANG_POLL_MAX_CNT_LEN             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT_LEN );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED1                           , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_UNUSED1 );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED1_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_UNUSED1_LEN );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_HANG_NX_MAX_CNT                   , 15  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_HANG_NX_MAX_CNT );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_HANG_NX_MAX_CNT_LEN               , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_HANG_NX_MAX_CNT_LEN );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_DISABLE_WR_RD_PUSH                , 19  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_DISABLE_WR_RD_PUSH );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_INJ_CE                            , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_INJ_CE );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_INJ_UE                            , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_INJ_UE );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_INJ_SUE                           , 22  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_INJ_SUE );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_INJ_ARRAY_SEL                     , 23  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_INJ_ARRAY_SEL );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_INJ_FREQ                          , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_INJ_FREQ );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED2                           , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_UNUSED2 );
+REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED2_LEN                       , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_0_UNUSED2_LEN );
+
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_LN_WR                             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_LN_WR );
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_G_WR                              , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_G_WR );
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_VG_WR                             , 2   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_VG_WR );
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_NN_WR                             , 3   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_NN_WR );
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_LN_RD                             , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_LN_RD );
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_G_RD                              , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_G_RD );
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_VG_RD                             , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_VG_RD );
+REG64_FLD( PU_VAS_PBCFG1_DISABLE_NN_RD                             , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISABLE_NN_RD );
+REG64_FLD( PU_VAS_PBCFG1_PBCFG_1_UNUSED1                           , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_1_UNUSED1 );
+REG64_FLD( PU_VAS_PBCFG1_PBCFG_1_UNUSED1_LEN                       , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_1_UNUSED1_LEN );
+REG64_FLD( PU_VAS_PBCFG1_RD_GO_M_QOS                               , 12  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RD_GO_M_QOS );
+REG64_FLD( PU_VAS_PBCFG1_ADDR_BAR_MODE                             , 13  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_ADDR_BAR_MODE );
+REG64_FLD( PU_VAS_PBCFG1_SKIP_G                                    , 14  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_SKIP_G     );
+REG64_FLD( PU_VAS_PBCFG1_HANG_SM_ON_ARE                            , 15  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HANG_SM_ON_ARE );
+REG64_FLD( PU_VAS_PBCFG1_HANG_SM_ON_LINK_FAIL                      , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_HANG_SM_ON_LINK_FAIL );
+REG64_FLD( PU_VAS_PBCFG1_CFG_PUMP_MODE                             , 17  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CFG_PUMP_MODE );
+REG64_FLD( PU_VAS_PBCFG1_DMA_WR_NOT_INJ                            , 18  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_WR_NOT_INJ );
+REG64_FLD( PU_VAS_PBCFG1_DMA_PART_WR_NOT_INJ                       , 19  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_PART_WR_NOT_INJ );
+REG64_FLD( PU_VAS_PBCFG1_DMA_RD_VG_RST_TMASK                       , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_RD_VG_RST_TMASK );
+REG64_FLD( PU_VAS_PBCFG1_DMA_RD_VG_RST_TMASK_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_RD_VG_RST_TMASK_LEN );
+REG64_FLD( PU_VAS_PBCFG1_DMA_WR_VG_RST_TMASK                       , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_WR_VG_RST_TMASK );
+REG64_FLD( PU_VAS_PBCFG1_DMA_WR_VG_RST_TMASK_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_WR_VG_RST_TMASK_LEN );
+REG64_FLD( PU_VAS_PBCFG1_PBCFG_1_UNUSED2                           , 36  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_1_UNUSED2 );
+REG64_FLD( PU_VAS_PBCFG1_PBCFG_1_UNUSED2_LEN                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PBCFG_1_UNUSED2_LEN );
+
+REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_VAL                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR1_VAL );
+REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_BAR                               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR1_BAR );
+REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_BAR_LEN                           , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR1_BAR_LEN );
+REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_PGSZ                              , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR1_PGSZ );
+REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_PGSZ_LEN                          , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR1_PGSZ_LEN );
+
+REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_VAL                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR2_VAL );
+REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_BAR                               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR2_BAR );
+REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_BAR_LEN                           , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR2_BAR_LEN );
+REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_PGSZ                              , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR2_PGSZ );
+REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_PGSZ_LEN                          , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR2_PGSZ_LEN );
+
+REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_VAL                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR3_VAL );
+REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_BAR                               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR3_BAR );
+REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_BAR_LEN                           , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR3_BAR_LEN );
+REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_PGSZ                              , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR3_PGSZ );
+REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_PGSZ_LEN                          , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR3_PGSZ_LEN );
+
+REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_VAL                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR4_VAL );
+REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_BAR                               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR4_BAR );
+REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_BAR_LEN                           , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR4_BAR_LEN );
+REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_PGSZ                              , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR4_PGSZ );
+REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_PGSZ_LEN                          , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR4_PGSZ_LEN );
+
+REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_VAL                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR5_VAL );
+REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_BAR                               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR5_BAR );
+REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_BAR_LEN                           , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR5_BAR_LEN );
+REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_PGSZ                              , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR5_PGSZ );
+REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_PGSZ_LEN                          , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR5_PGSZ_LEN );
+
+REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_VAL                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR6_VAL );
+REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_BAR                               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR6_BAR );
+REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_BAR_LEN                           , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR6_BAR_LEN );
+REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_PGSZ                              , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR6_PGSZ );
+REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_PGSZ_LEN                          , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR6_PGSZ_LEN );
+
+REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_VAL                               , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR7_VAL );
+REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_BAR                               , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR7_BAR );
+REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_BAR_LEN                           , 46  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR7_BAR_LEN );
+REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_PGSZ                              , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR7_PGSZ );
+REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_PGSZ_LEN                          , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PGMIGR7_PGSZ_LEN );
+
+REG64_FLD( PU_VAS_PMCNTL_PU_BIT_ENABLES                            , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PU_BIT_ENABLES );
+REG64_FLD( PU_VAS_PMCNTL_PU_BIT_ENABLES_LEN                        , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PU_BIT_ENABLES_LEN );
+REG64_FLD( PU_VAS_PMCNTL_PU_CNTL_UNUSED                            , 32  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PU_CNTL_UNUSED );
+REG64_FLD( PU_VAS_PMCNTL_PU_CNTL_UNUSED_LEN                        , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_PU_CNTL_UNUSED_LEN );
+
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_RESET                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RG_CERR_RESET );
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT4                            , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RG_CERR_BIT4 );
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT5                            , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RG_CERR_BIT5 );
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT6                            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RG_CERR_BIT6 );
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT7                            , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RG_CERR_BIT7 );
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT8                            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RG_CERR_BIT8 );
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT9                            , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RG_CERR_BIT9 );
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT10                           , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RG_CERR_BIT10 );
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT11                           , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RG_CERR_BIT11 );
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT12                           , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RG_CERR_BIT12 );
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT13                           , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RG_CERR_BIT13 );
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_UNUSED_BITS                     , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RG_CERR_UNUSED_BITS );
+REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_UNUSED_BITS_LEN                 , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RG_CERR_UNUSED_BITS_LEN );
+
+REG64_FLD( PU_VAS_RMABAR_RMA_BAR                                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RMA_BAR    );
+REG64_FLD( PU_VAS_RMABAR_RMA_BAR_LEN                               , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RMA_BAR_LEN );
+
+REG64_FLD( PU_VAS_RMABARM_RMA_BAR_MASK                             , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RMA_BAR_MASK );
+REG64_FLD( PU_VAS_RMABARM_RMA_BAR_MASK_LEN                         , 44  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_RMA_BAR_MASK_LEN );
+
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_DISABLE_WC_SCRUB              , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SOUTH_CTL_DISABLE_WC_SCRUB );
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_DISABLE_WC_ECC                , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SOUTH_CTL_DISABLE_WC_ECC );
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EG_SINGLE_THREAD              , 2   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SOUTH_CTL_EG_SINGLE_THREAD );
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE );
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EG_STAMP_DEBUG                , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SOUTH_CTL_EG_STAMP_DEBUG );
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EN_FAST_SCRUB                 , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SOUTH_CTL_EN_FAST_SCRUB );
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_DIS_SIMULT_RD_WR              , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SOUTH_CTL_DIS_SIMULT_RD_WR );
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_ENA_NOTIFY_ORDER              , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SOUTH_CTL_ENA_NOTIFY_ORDER );
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_WC_IDLE_BIT                   , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SOUTH_CTL_WC_IDLE_BIT );
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_CQ_IDLE_BIT                   , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SOUTH_CTL_CQ_IDLE_BIT );
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EG_IDLE_BIT                   , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SOUTH_CTL_EG_IDLE_BIT );
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_UNUSED                        , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SOUTH_CTL_UNUSED );
+REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_UNUSED_LEN                    , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SOUTH_CTL_UNUSED_LEN );
+
+REG64_FLD( PU_VAS_UWMBAR_BASE_ADDR                                 , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BASE_ADDR  );
+REG64_FLD( PU_VAS_UWMBAR_BASE_ADDR_LEN                             , 28  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BASE_ADDR_LEN );
+
+REG64_FLD( PU_VAS_WCBSBAR_WC_BS_BAR                                , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WC_BS_BAR  );
+REG64_FLD( PU_VAS_WCBSBAR_WC_BS_BAR_LEN                            , 33  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WC_BS_BAR_LEN );
+
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_RESET                           , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_RESET );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT4                            , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT4 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT5                            , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT5 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT6                            , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT6 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT7                            , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT7 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT8                            , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT8 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT9                            , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT9 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT10                           , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT10 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT11                           , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT11 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT12                           , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT12 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT13                           , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT13 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT14                           , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT14 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT15                           , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT15 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT16                           , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT16 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT17                           , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT17 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT18                           , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT18 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT19                           , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT19 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT20                           , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT20 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT21                           , 21  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT21 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT22                           , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT22 );
+REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT23                           , 23  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WC_CERR_BIT23 );
+
+REG64_FLD( PU_VAS_WCMBAR_BASE_ADDR                                 , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BASE_ADDR  );
+REG64_FLD( PU_VAS_WCMBAR_BASE_ADDR_LEN                             , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_BASE_ADDR_LEN );
+
+REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_BA                          , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR0_BA );
+REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_BA_LEN                      , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR0_BA_LEN );
+REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_SIZE                        , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR0_SIZE );
+REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_SIZE_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR0_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_VAL                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP0_VAL );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPEDIS                    , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP0_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPEDIS_LEN                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP0_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_UNUSED                      , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP0_UNUSED );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_ENADTTYPE                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP0_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPE                       , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP0_TTYPE );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPE_LEN                   , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP0_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TSIZE                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP0_TSIZE );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TSIZE_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP0_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPEMSK                    , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP0_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPEMSK_LEN                , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP0_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TSIZEMSK                    , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP0_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TSIZEMSK_LEN                , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP0_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON0WID_WRMON_WID0                             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID0 );
+REG64_FLD( PU_VAS_WRMON0WID_WRMON_WID0_LEN                         , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID0_LEN );
+
+REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_BA                          , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR1_BA );
+REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_BA_LEN                      , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR1_BA_LEN );
+REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_SIZE                        , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR1_SIZE );
+REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_SIZE_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR1_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_VAL                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP1_VAL );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPEDIS                    , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP1_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPEDIS_LEN                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP1_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_UNUSED                      , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP1_UNUSED );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_ENADTTYPE                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP1_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPE                       , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP1_TTYPE );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPE_LEN                   , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP1_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TSIZE                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP1_TSIZE );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TSIZE_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP1_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPEMSK                    , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP1_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPEMSK_LEN                , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP1_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TSIZEMSK                    , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP1_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TSIZEMSK_LEN                , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP1_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON1WID_WRMON_WID1                             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID1 );
+REG64_FLD( PU_VAS_WRMON1WID_WRMON_WID1_LEN                         , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID1_LEN );
+
+REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_BA                          , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR2_BA );
+REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_BA_LEN                      , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR2_BA_LEN );
+REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_SIZE                        , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR2_SIZE );
+REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_SIZE_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR2_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_VAL                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP2_VAL );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPEDIS                    , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP2_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPEDIS_LEN                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP2_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_UNUSED                      , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP2_UNUSED );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_ENADTTYPE                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP2_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPE                       , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP2_TTYPE );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPE_LEN                   , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP2_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TSIZE                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP2_TSIZE );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TSIZE_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP2_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPEMSK                    , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP2_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPEMSK_LEN                , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP2_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TSIZEMSK                    , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP2_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TSIZEMSK_LEN                , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP2_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON2WID_WRMON_WID2                             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID2 );
+REG64_FLD( PU_VAS_WRMON2WID_WRMON_WID2_LEN                         , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID2_LEN );
+
+REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_BA                          , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR3_BA );
+REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_BA_LEN                      , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR3_BA_LEN );
+REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_SIZE                        , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR3_SIZE );
+REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_SIZE_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR3_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_VAL                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP3_VAL );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPEDIS                    , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP3_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPEDIS_LEN                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP3_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_UNUSED                      , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP3_UNUSED );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_ENADTTYPE                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP3_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPE                       , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP3_TTYPE );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPE_LEN                   , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP3_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TSIZE                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP3_TSIZE );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TSIZE_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP3_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPEMSK                    , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP3_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPEMSK_LEN                , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP3_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TSIZEMSK                    , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP3_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TSIZEMSK_LEN                , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP3_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON3WID_WRMON_WID3                             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID3 );
+REG64_FLD( PU_VAS_WRMON3WID_WRMON_WID3_LEN                         , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID3_LEN );
+
+REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_BA                          , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR4_BA );
+REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_BA_LEN                      , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR4_BA_LEN );
+REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_SIZE                        , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR4_SIZE );
+REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_SIZE_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR4_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_VAL                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP4_VAL );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPEDIS                    , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP4_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPEDIS_LEN                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP4_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_UNUSED                      , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP4_UNUSED );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_ENADTTYPE                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP4_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPE                       , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP4_TTYPE );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPE_LEN                   , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP4_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TSIZE                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP4_TSIZE );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TSIZE_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP4_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPEMSK                    , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP4_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPEMSK_LEN                , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP4_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TSIZEMSK                    , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP4_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TSIZEMSK_LEN                , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP4_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON4WID_WRMON_WID4                             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID4 );
+REG64_FLD( PU_VAS_WRMON4WID_WRMON_WID4_LEN                         , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID4_LEN );
+
+REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_BA                          , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR5_BA );
+REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_BA_LEN                      , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR5_BA_LEN );
+REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_SIZE                        , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR5_SIZE );
+REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_SIZE_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR5_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_VAL                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP5_VAL );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPEDIS                    , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP5_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPEDIS_LEN                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP5_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_UNUSED                      , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP5_UNUSED );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_ENADTTYPE                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP5_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPE                       , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP5_TTYPE );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPE_LEN                   , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP5_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TSIZE                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP5_TSIZE );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TSIZE_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP5_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPEMSK                    , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP5_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPEMSK_LEN                , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP5_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TSIZEMSK                    , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP5_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TSIZEMSK_LEN                , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP5_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON5WID_WRMON_WID5                             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID5 );
+REG64_FLD( PU_VAS_WRMON5WID_WRMON_WID5_LEN                         , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID5_LEN );
+
+REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_BA                          , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR6_BA );
+REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_BA_LEN                      , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR6_BA_LEN );
+REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_SIZE                        , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR6_SIZE );
+REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_SIZE_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR6_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_VAL                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP6_VAL );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPEDIS                    , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP6_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPEDIS_LEN                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP6_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_UNUSED                      , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP6_UNUSED );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_ENADTTYPE                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP6_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPE                       , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP6_TTYPE );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPE_LEN                   , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP6_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TSIZE                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP6_TSIZE );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TSIZE_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP6_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPEMSK                    , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP6_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPEMSK_LEN                , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP6_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TSIZEMSK                    , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP6_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TSIZEMSK_LEN                , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP6_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON6WID_WRMON_WID6                             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID6 );
+REG64_FLD( PU_VAS_WRMON6WID_WRMON_WID6_LEN                         , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID6_LEN );
+
+REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_BA                          , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR7_BA );
+REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_BA_LEN                      , 49  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR7_BA_LEN );
+REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_SIZE                        , 60  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR7_SIZE );
+REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_SIZE_LEN                    , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_BAR7_SIZE_LEN );
+
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_VAL                         , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP7_VAL );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPEDIS                    , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP7_TTYPEDIS );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPEDIS_LEN                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP7_TTYPEDIS_LEN );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_UNUSED                      , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP7_UNUSED );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_ENADTTYPE                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP7_ENADTTYPE );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPE                       , 9   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP7_TTYPE );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPE_LEN                   , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP7_TTYPE_LEN );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TSIZE                       , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP7_TSIZE );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TSIZE_LEN                   , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP7_TSIZE_LEN );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPEMSK                    , 24  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP7_TTYPEMSK );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPEMSK_LEN                , 7   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP7_TTYPEMSK_LEN );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TSIZEMSK                    , 31  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP7_TSIZEMSK );
+REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TSIZEMSK_LEN                , 8   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_CMP7_TSIZEMSK_LEN );
+
+REG64_FLD( PU_VAS_WRMON7WID_WRMON_WID7                             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID7 );
+REG64_FLD( PU_VAS_WRMON7WID_WRMON_WID7_LEN                         , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_WRMON_WID7_LEN );
+
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH0_TIMER_ENBL             , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH0_TIMER_ENBL );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH0_REF_DIV                , 1   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH0_REF_DIV );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH0_REF_DIV_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH0_REF_DIV_LEN );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH1_TIMER_ENBL             , 5   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH1_TIMER_ENBL );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH1_REF_DIV                , 6   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH1_REF_DIV );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH1_REF_DIV_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH1_REF_DIV_LEN );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH2_TIMER_ENBL             , 10  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH2_TIMER_ENBL );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH2_REF_DIV                , 11  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH2_REF_DIV );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH2_REF_DIV_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH2_REF_DIV_LEN );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH3_TIMER_ENBL             , 15  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH3_TIMER_ENBL );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH3_REF_DIV                , 16  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH3_REF_DIV );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH3_REF_DIV_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH3_REF_DIV_LEN );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH4_TIMER_ENBL             , 20  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH4_TIMER_ENBL );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH4_REF_DIV                , 21  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH4_REF_DIV );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH4_REF_DIV_LEN            , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_CH4_REF_DIV_LEN );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_DMA_TIMER_ENBL             , 25  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_TIMER_ENBL );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_DMA_TIMER_REF_DIV          , 26  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_TIMER_REF_DIV );
+REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_DMA_TIMER_REF_DIV_LEN      , 4   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DMA_TIMER_REF_DIV_LEN );
+
+REG64_FLD( PU_WATER_MARK_REGISTER_B_WATERMARK_REG_0                , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WATERMARK_REG_0 );
+REG64_FLD( PU_WATER_MARK_REGISTER_B_WATERMARK_REG_0_LEN            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WATERMARK_REG_0_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_B_PEEK_DATA1_0                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0 );
+REG64_FLD( PU_WATER_MARK_REGISTER_B_PEEK_DATA1_0_LEN               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_0_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_B_LBUS_PARITY_ERR1_0             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_0 );
+
+REG64_FLD( PU_WATER_MARK_REGISTER_C_WATERMARK_REG_1                , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WATERMARK_REG_1 );
+REG64_FLD( PU_WATER_MARK_REGISTER_C_WATERMARK_REG_1_LEN            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WATERMARK_REG_1_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_C_PEEK_DATA1_1                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1 );
+REG64_FLD( PU_WATER_MARK_REGISTER_C_PEEK_DATA1_1_LEN               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_1_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_C_LBUS_PARITY_ERR1_1             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_1 );
+
+REG64_FLD( PU_WATER_MARK_REGISTER_D_WATERMARK_REG_2                , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WATERMARK_REG_2 );
+REG64_FLD( PU_WATER_MARK_REGISTER_D_WATERMARK_REG_2_LEN            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WATERMARK_REG_2_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_D_PEEK_DATA1_2                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2 );
+REG64_FLD( PU_WATER_MARK_REGISTER_D_PEEK_DATA1_2_LEN               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_2_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_D_LBUS_PARITY_ERR1_2             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_2 );
+
+REG64_FLD( PU_WATER_MARK_REGISTER_E_WATERMARK_REG_3                , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WATERMARK_REG_3 );
+REG64_FLD( PU_WATER_MARK_REGISTER_E_WATERMARK_REG_3_LEN            , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WATERMARK_REG_3_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_E_PEEK_DATA1_3                   , 32  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3 );
+REG64_FLD( PU_WATER_MARK_REGISTER_E_PEEK_DATA1_3_LEN               , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PEEK_DATA1_3_LEN );
+REG64_FLD( PU_WATER_MARK_REGISTER_E_LBUS_PARITY_ERR1_3             , 40  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERR1_3 );
+
+REG64_FLD( PU_N3_WRITE_PROTECT_ENABLE_REG_RING_LOCKING             , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RING_LOCKING );
+REG64_FLD( PU_N3_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING    , 1   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_RING_LOCKING );
+
+REG64_FLD( PU_N1_WRITE_PROTECT_ENABLE_REG_RING_LOCKING             , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RING_LOCKING );
+REG64_FLD( PU_N1_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING    , 1   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_RING_LOCKING );
+
+REG64_FLD( PU_WRITE_PROTECT_ENABLE_REG_RING_LOCKING                , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RING_LOCKING );
+REG64_FLD( PU_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING       , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_RING_LOCKING );
+
+REG64_FLD( PU_N2_WRITE_PROTECT_ENABLE_REG_RING_LOCKING             , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RING_LOCKING );
+REG64_FLD( PU_N2_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING    , 1   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_RING_LOCKING );
+
+REG64_FLD( PEC_WRITE_PROTECT_ENABLE_REG_RING_LOCKING               , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RING_LOCKING );
+REG64_FLD( PEC_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING      , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_RING_LOCKING );
+
+REG64_FLD( PU_N0_WRITE_PROTECT_ENABLE_REG_RING_LOCKING             , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RING_LOCKING );
+REG64_FLD( PU_N0_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING    , 1   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_RING_LOCKING );
+
+REG64_FLD( PU_N3_WRITE_PROTECT_RINGS_REG_RINGS                     , 0   , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RINGS      );
+REG64_FLD( PU_N3_WRITE_PROTECT_RINGS_REG_RINGS_LEN                 , 16  , SH_UNT_PU_N3    , SH_ACS_SCOM     ,
+           SH_FLD_RINGS_LEN  );
+
+REG64_FLD( PU_N1_WRITE_PROTECT_RINGS_REG_RINGS                     , 0   , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RINGS      );
+REG64_FLD( PU_N1_WRITE_PROTECT_RINGS_REG_RINGS_LEN                 , 16  , SH_UNT_PU_N1    , SH_ACS_SCOM     ,
+           SH_FLD_RINGS_LEN  );
+
+REG64_FLD( PU_WRITE_PROTECT_RINGS_REG_RINGS                        , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RINGS      );
+REG64_FLD( PU_WRITE_PROTECT_RINGS_REG_RINGS_LEN                    , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RINGS_LEN  );
+
+REG64_FLD( PU_N2_WRITE_PROTECT_RINGS_REG_RINGS                     , 0   , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RINGS      );
+REG64_FLD( PU_N2_WRITE_PROTECT_RINGS_REG_RINGS_LEN                 , 16  , SH_UNT_PU_N2    , SH_ACS_SCOM     ,
+           SH_FLD_RINGS_LEN  );
+
+REG64_FLD( PEC_WRITE_PROTECT_RINGS_REG_RINGS                       , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RINGS      );
+REG64_FLD( PEC_WRITE_PROTECT_RINGS_REG_RINGS_LEN                   , 16  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_RINGS_LEN  );
+
+REG64_FLD( PU_N0_WRITE_PROTECT_RINGS_REG_RINGS                     , 0   , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RINGS      );
+REG64_FLD( PU_N0_WRITE_PROTECT_RINGS_REG_RINGS_LEN                 , 16  , SH_UNT_PU_N0    , SH_ACS_SCOM     ,
+           SH_FLD_RINGS_LEN  );
+
+REG64_FLD( PEC_XFIR_IN0                                            , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( PEC_XFIR_IN1                                            , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN1        );
+REG64_FLD( PEC_XFIR_IN2                                            , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN2        );
+REG64_FLD( PEC_XFIR_IN3                                            , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN3        );
+REG64_FLD( PEC_XFIR_IN4                                            , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( PEC_XFIR_IN5                                            , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( PEC_XFIR_IN6                                            , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN6        );
+REG64_FLD( PEC_XFIR_IN6_LEN                                        , 20  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN6_LEN    );
+REG64_FLD( PEC_XFIR_IN26                                           , 26  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_IN26       );
+
+REG64_FLD( CAPP_XPT_CONTROL_SEND_PACKET_TIMER_VALUE                , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SEND_PACKET_TIMER_VALUE );
+REG64_FLD( CAPP_XPT_CONTROL_SEND_PACKET_TIMER_VALUE_LEN            , 10  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SEND_PACKET_TIMER_VALUE_LEN );
+REG64_FLD( CAPP_XPT_CONTROL_CI_STORE_BUFFER_THRESHOLD              , 10  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CI_STORE_BUFFER_THRESHOLD );
+REG64_FLD( CAPP_XPT_CONTROL_CI_STORE_BUFFER_THRESHOLD_LEN          , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CI_STORE_BUFFER_THRESHOLD_LEN );
+REG64_FLD( CAPP_XPT_CONTROL_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS     , 14  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS );
+REG64_FLD( CAPP_XPT_CONTROL_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS_LEN , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS_LEN );
+REG64_FLD( CAPP_XPT_CONTROL_TLBI_DATA_POLL_PULSE_DIV               , 18  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TLBI_DATA_POLL_PULSE_DIV );
+REG64_FLD( CAPP_XPT_CONTROL_TLBI_DATA_POLL_PULSE_DIV_LEN           , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TLBI_DATA_POLL_PULSE_DIV_LEN );
+REG64_FLD( CAPP_XPT_CONTROL_SN_WRT_DBUF_MAX_CREDIT                 , 22  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SN_WRT_DBUF_MAX_CREDIT );
+REG64_FLD( CAPP_XPT_CONTROL_SN_WRT_DBUF_MAX_CREDIT_LEN             , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SN_WRT_DBUF_MAX_CREDIT_LEN );
+REG64_FLD( CAPP_XPT_CONTROL_RESERVED                               , 26  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED   );
+REG64_FLD( CAPP_XPT_CONTROL_RESERVED_LEN                           , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LEN );
+REG64_FLD( CAPP_XPT_CONTROL_SN_MSG_MAX_CREDIT                      , 28  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SN_MSG_MAX_CREDIT );
+REG64_FLD( CAPP_XPT_CONTROL_SN_MSG_MAX_CREDIT_LEN                  , 9   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SN_MSG_MAX_CREDIT_LEN );
+REG64_FLD( CAPP_XPT_CONTROL_BENIGN_PTR_DATA                        , 37  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_BENIGN_PTR_DATA );
+REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_EN                         , 38  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_EN );
+REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_THRESHOLD                  , 39  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_THRESHOLD );
+REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_THRESHOLD_LEN              , 3   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_THRESHOLD_LEN );
+REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_CMPLT_CNT                  , 42  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_CMPLT_CNT );
+REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_CMPLT_CNT_LEN              , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_CMPLT_CNT_LEN );
+REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_DELAY_CNT                  , 46  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_DELAY_CNT );
+REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_DELAY_CNT_LEN              , 8   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_DELAY_CNT_LEN );
+REG64_FLD( CAPP_XPT_CONTROL_CI_BUFF_MIN                            , 58  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CI_BUFF_MIN );
+REG64_FLD( CAPP_XPT_CONTROL_CI_BUFF_MIN_LEN                        , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CI_BUFF_MIN_LEN );
+REG64_FLD( CAPP_XPT_CONTROL_CI_BUFF_AVAIL                          , 62  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CI_BUFF_AVAIL );
+REG64_FLD( CAPP_XPT_CONTROL_LOAD_CI_BUFF                           , 63  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_LOAD_CI_BUFF );
+
+REG64_FLD( CAPP_XPT_ERROR_REPORT_PSL_CMD_UE_ERRHOLD                , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PSL_CMD_UE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_PSL_CMD_SUE_ERRHOLD               , 1   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PSL_CMD_SUE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_SC_RDATA_PARITY_ERRHOLD           , 2   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SC_RDATA_PARITY_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_APC_SC_RDATA_PARITY_ERRHOLD       , 3   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APC_SC_RDATA_PARITY_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_SN_SC_RDATA_PARITY_ERRHOLD        , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SN_SC_RDATA_PARITY_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_NX_DATA_RTAG_PARITY_ERRHOLD       , 5   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_NX_DATA_RTAG_PARITY_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_ECC_CE_ERRHOLD      , 6   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_NXPBXPT_PBRCV_ECC_CE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_ECC_UE_ERRHOLD      , 7   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_NXPBXPT_PBRCV_ECC_UE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_ECC_SUE_ERRHOLD     , 8   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_NXPBXPT_PBRCV_ECC_SUE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_DBG_CTL_REG_PARITY_ERRHOLD        , 9   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_CTL_REG_PARITY_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_CFG_REG_PARITY_ERRHOLD            , 10  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CFG_REG_PARITY_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_CAPP_ERR_STAT_CTL_REG_PARITY_ERRHOLD , 11  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CAPP_ERR_STAT_CTL_REG_PARITY_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_PMU_CNTRA_CFG_REG_PARITY_ERRHOLD  , 12  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMU_CNTRA_CFG_REG_PARITY_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_PMU_CNTRB_CFG_REG_PARITY_ERRHOLD  , 13  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMU_CNTRB_CFG_REG_PARITY_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_PMU_EVENT_SEL_REG_PARITY_ERRHOLD  , 14  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMU_EVENT_SEL_REG_PARITY_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_PE0_CXA_LINKDOWN_ERRHOLD          , 15  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PE0_CXA_LINKDOWN_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_PE1_CXA_LINKDOWN_ERRHOLD          , 16  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PE1_CXA_LINKDOWN_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_SB_SCOM_ERRHOLD                   , 17  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SB_SCOM_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_PBXMIT_MSGQ_SEQ_ERRHOLD           , 18  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PBXMIT_MSGQ_SEQ_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_PBXMIT_DXMIT_SEQ_ERRHOLD          , 19  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PBXMIT_DXMIT_SEQ_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_EPH_REC_TMR_CNTL_REG_PARITY_ERRHOLD , 20  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_EPH_REC_TMR_CNTL_REG_PARITY_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_RCS_RECOVERY_FAILED_ERRHOLD       , 21  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_RCS_RECOVERY_FAILED_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_RCS_STATE_MACHINE_ERRHOLD         , 22  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_RCS_STATE_MACHINE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_LNK_RSP_ECC_UE_ERRHOLD , 23  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_NXPBXPT_PBRCV_LNK_RSP_ECC_UE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_LNK_RSP_ECC_SUE_ERRHOLD , 24  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_NXPBXPT_PBRCV_LNK_RSP_ECC_SUE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_LNK_RSP_PKT_DISCARDED_ERRHOLD     , 25  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_LNK_RSP_PKT_DISCARDED_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_SECURE_LNK_RSP_PKT_NOT_VALID_ERRHOLD , 26  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SECURE_LNK_RSP_PKT_NOT_VALID_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_SECURE_LNK_SCOM_CONFLICT_ERRHOLD  , 27  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SECURE_LNK_SCOM_CONFLICT_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_UNSOLICITED_DATA_RCV_ERRHOLD      , 28  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_UNSOLICITED_DATA_RCV_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_AS_RCMD0_PARITY_ERR_ERRHOLD       , 29  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_AS_RCMD0_PARITY_ERR_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_AS_REGS_PARITY_ERR_ERRHOLD        , 30  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_AS_REGS_PARITY_ERR_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_AS_SM_ERRHOLD                     , 31  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_AS_SM_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_AS_REG_RDATA_PERR_ERRHOLD         , 32  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_AS_REG_RDATA_PERR_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_DFS_SM_ERRHOLD                    , 33  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_DFS_SM_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_FIR_ERR_ERRHOLD                , 34  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TB_FIR_ERR_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_CMD_DISCARDED_ERRHOLD          , 35  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TB_CMD_DISCARDED_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_REG_RDATA_PERR_ERRHOLD         , 36  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TB_REG_RDATA_PERR_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_RNG_WR_ENBL_REG_PERR_ERRHOLD      , 37  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_RNG_WR_ENBL_REG_PERR_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_HI_UE_ERRHOLD             , 38  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SSA_ECC_HI_UE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_HI_CE_ERRHOLD             , 39  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SSA_ECC_HI_CE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_HI_SUE_ERRHOLD            , 40  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SSA_ECC_HI_SUE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_LO_SUE_ERRHOLD            , 41  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SSA_ECC_LO_SUE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_LO_CE_ERRHOLD             , 42  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SSA_ECC_LO_CE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_LO_UE_ERRHOLD             , 43  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_SSA_ECC_LO_UE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_CXACQPB_MUX_ECC_CE_ERRHOLD        , 44  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CXACQPB_MUX_ECC_CE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_CXACQPB_MUX_ECC_UE_ERRHOLD        , 45  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CXACQPB_MUX_ECC_UE_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_APC0_SC_RDATA_PARITY_ERRHOLD      , 46  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_APC0_SC_RDATA_PARITY_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_CREDIT_TIMEOUT_ERRHOLD            , 47  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_CREDIT_TIMEOUT_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_TLBI_SC_RDATA_PARITY_ERRHOLD      , 48  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TLBI_SC_RDATA_PARITY_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_TLBI_REGS_PARITY_ERRHOLD          , 49  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TLBI_REGS_PARITY_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_RCS_RECOVERY_TIMEOUT_ERRHOLD      , 50  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_RCS_RECOVERY_TIMEOUT_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST0_BADIN_ERRHOLD               , 51  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TBST0_BADIN_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST6_BADIN_ERRHOLD               , 52  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TBST6_BADIN_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST7_BADIN_ERRHOLD               , 53  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TBST7_BADIN_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_TWO_TFMRCMDS_ERR_ERRHOLD          , 54  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TWO_TFMRCMDS_ERR_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_MISSING_SYNC_ERRHOLD           , 55  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TB_MISSING_SYNC_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_MISSING_STEP_ERRHOLD           , 56  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TB_MISSING_STEP_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_RESIDUE_ERR_ERRHOLD            , 57  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TB_RESIDUE_ERR_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_TX_TFMR_CORRUPT_ERRHOLD           , 58  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TX_TFMR_CORRUPT_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST_CORRUPT_ERRHOLD              , 59  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TBST_CORRUPT_ERRHOLD );
+REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST9_BADIN_ERRHOLD               , 60  , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_TBST9_BADIN_ERRHOLD );
+
+REG64_FLD( CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT               , 0   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMON_GROUP_SELECT );
+REG64_FLD( CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT_LEN           , 4   , SH_UNT_CAPP     , SH_ACS_SCOM     ,
+           SH_FLD_PMON_GROUP_SELECT_LEN );
+
+REG64_FLD( PU_XSCOM_BASE_REG_FBC                                   , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC        );
+REG64_FLD( PU_XSCOM_BASE_REG_FBC_LEN                               , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_LEN    );
+REG64_FLD( PU_XSCOM_BASE_REG_FBC_RESET                             , 61  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_RESET  );
+REG64_FLD( PU_XSCOM_BASE_REG_FBC_DISABLE                           , 62  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_DISABLE );
+REG64_FLD( PU_XSCOM_BASE_REG_FBC_DISABLE_LOCAL_SHORTCUT            , 63  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FBC_DISABLE_LOCAL_SHORTCUT );
+
+REG64_FLD( PU_XSCOM_DAT0_REG_DAT0                                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DAT0       );
+REG64_FLD( PU_XSCOM_DAT0_REG_DAT0_LEN                              , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DAT0_LEN   );
+
+REG64_FLD( PU_XSCOM_DAT1_REG_DAT1                                  , 0   , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DAT1       );
+REG64_FLD( PU_XSCOM_DAT1_REG_DAT1_LEN                              , 64  , SH_UNT          , SH_ACS_SCOM_RW  ,
+           SH_FLD_DAT1_LEN   );
+
+REG64_FLD( PU_XSCOM_ERR_REG_ADDRESS                                , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PU_XSCOM_ERR_REG_TSIZE                                  , 1   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_TSIZE      );
+REG64_FLD( PU_XSCOM_ERR_REG_RC_TTAG_PAR                            , 2   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_RC_TTAG_PAR );
+REG64_FLD( PU_XSCOM_ERR_REG_CR_TTAG_PAR                            , 3   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_CR_TTAG_PAR );
+REG64_FLD( PU_XSCOM_ERR_REG_CR_ATAG_PAR                            , 4   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_CR_ATAG_PAR );
+REG64_FLD( PU_XSCOM_ERR_REG_RC_ADDR_PAR                            , 5   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_RC_ADDR_PAR );
+REG64_FLD( PU_XSCOM_ERR_REG_PB_ECC_CE                              , 8   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PB_ECC_CE  );
+REG64_FLD( PU_XSCOM_ERR_REG_PB_ECC_UE                              , 9   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PB_ECC_UE  );
+REG64_FLD( PU_XSCOM_ERR_REG_PB_ECC_SUE                             , 10  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PB_ECC_SUE );
+REG64_FLD( PU_XSCOM_ERR_REG_RTAG_PARITY                            , 11  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_RTAG_PARITY );
+REG64_FLD( PU_XSCOM_ERR_REG_CRESP_HANG                             , 12  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_CRESP_HANG );
+REG64_FLD( PU_XSCOM_ERR_REG_PIB_HANG                               , 13  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PIB_HANG   );
+REG64_FLD( PU_XSCOM_ERR_REG_PBDATA_HANG                            , 14  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PBDATA_HANG );
+REG64_FLD( PU_XSCOM_ERR_REG_ADS_HANG                               , 15  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_ADS_HANG   );
+REG64_FLD( PU_XSCOM_ERR_REG_FSM_PERR                               , 16  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_FSM_PERR   );
+REG64_FLD( PU_XSCOM_ERR_REG_SPARE0                                 , 17  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_SPARE0     );
+REG64_FLD( PU_XSCOM_ERR_REG_SPARE1                                 , 18  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_SPARE1     );
+REG64_FLD( PU_XSCOM_ERR_REG_UNEXPECT_DATA                          , 19  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_UNEXPECT_DATA );
+REG64_FLD( PU_XSCOM_ERR_REG_ILL_CRESP                              , 20  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_ILL_CRESP  );
+
+REG64_FLD( PU_XSCOM_LOG_REG_CMD_IN_PROG                            , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_IN_PROG );
+REG64_FLD( PU_XSCOM_LOG_REG_CMD_STATUS                             , 1   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_STATUS );
+REG64_FLD( PU_XSCOM_LOG_REG_CMD_STATUS_LEN                         , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_CMD_STATUS_LEN );
+REG64_FLD( PU_XSCOM_LOG_REG_WRITE_CMD                              , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_CMD  );
+REG64_FLD( PU_XSCOM_LOG_REG_ADDR_TAG                               , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_TAG   );
+REG64_FLD( PU_XSCOM_LOG_REG_ADDR_TAG_LEN                           , 22  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_TAG_LEN );
+REG64_FLD( PU_XSCOM_LOG_REG_THR_ID                                 , 27  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_THR_ID     );
+REG64_FLD( PU_XSCOM_LOG_REG_THR_ID_LEN                             , 3   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_THR_ID_LEN );
+REG64_FLD( PU_XSCOM_LOG_REG_PIB_COMPONENT_BUSY                     , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_COMPONENT_BUSY );
+REG64_FLD( PU_XSCOM_LOG_REG_PIB_ADDR                               , 33  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_ADDR   );
+REG64_FLD( PU_XSCOM_LOG_REG_PIB_ADDR_LEN                           , 31  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_PIB_ADDR_LEN );
+
+REG64_FLD( PU_XSCOM_MODE_REG_SPARE                                 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PU_XSCOM_MODE_REG_SPARE_LEN                             , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR1                     , 4   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR_PIB_ON_ERROR1 );
+REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR2                     , 5   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR_PIB_ON_ERROR2 );
+REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR3                     , 6   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR_PIB_ON_ERROR3 );
+REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR4                     , 7   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR_PIB_ON_ERROR4 );
+REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR5                     , 8   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR_PIB_ON_ERROR5 );
+REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR6                     , 9   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR_PIB_ON_ERROR6 );
+REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR7                     , 10  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_BAR_PIB_ON_ERROR7 );
+REG64_FLD( PU_XSCOM_MODE_REG_HANG_PIB_RESET                        , 11  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HANG_PIB_RESET );
+REG64_FLD( PU_XSCOM_MODE_REG_HANG_RESET                            , 12  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_HANG_RESET );
+REG64_FLD( PU_XSCOM_MODE_REG_RESET_ON_PARITY                       , 13  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_RESET_ON_PARITY );
+REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR1                  , 14  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_LOG_ON_ERROR1 );
+REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR2                  , 15  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_LOG_ON_ERROR2 );
+REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR3                  , 16  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_LOG_ON_ERROR3 );
+REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR4                  , 17  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_LOG_ON_ERROR4 );
+REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR5                  , 18  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_LOG_ON_ERROR5 );
+REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR6                  , 19  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_LOG_ON_ERROR6 );
+REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR7                  , 20  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_LOG_ON_ERROR7 );
+
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DONE                            , 0   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_DONE       );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_RESULT                          , 1   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_RESULT     );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_RESULT_LEN                      , 3   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_RESULT_LEN );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_COREID                          , 4   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COREID     );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_COREID_LEN                      , 6   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_COREID_LEN );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_THRID                           , 10  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_THRID      );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_THRID_LEN                       , 3   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_THRID_LEN  );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_GROUPID                    , 13  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_DEST_GROUPID );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_GROUPID_LEN                , 4   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_DEST_GROUPID_LEN );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_CHIPID                     , 17  , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_DEST_CHIPID );
+REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_CHIPID_LEN                 , 3   , SH_UNT          , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_DEST_CHIPID_LEN );
+
+REG64_FLD( PEC_XSTOP1_MASK_B                                       , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MASK_B     );
+REG64_FLD( PEC_XSTOP1_UNUSED                                       , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PEC_XSTOP1_TRIGGER_OPCG_ON                              , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( PEC_XSTOP1_WAIT_ALLWAYS                                 , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( PEC_XSTOP1_PERV                                         , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( PEC_XSTOP1_UNIT1                                        , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( PEC_XSTOP1_UNIT2                                        , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( PEC_XSTOP1_UNIT3                                        , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( PEC_XSTOP1_UNIT4                                        , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( PEC_XSTOP1_UNIT5                                        , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( PEC_XSTOP1_UNIT6                                        , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( PEC_XSTOP1_UNIT7                                        , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( PEC_XSTOP1_UNIT8                                        , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( PEC_XSTOP1_UNIT9                                        , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( PEC_XSTOP1_UNIT10                                       , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( PEC_XSTOP1_WAIT_CYCLES                                  , 48  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( PEC_XSTOP1_WAIT_CYCLES_LEN                              , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( PEC_XSTOP2_MASK_B                                       , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MASK_B     );
+REG64_FLD( PEC_XSTOP2_UNUSED                                       , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PEC_XSTOP2_TRIGGER_OPCG_ON                              , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( PEC_XSTOP2_WAIT_ALLWAYS                                 , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( PEC_XSTOP2_PERV                                         , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( PEC_XSTOP2_UNIT1                                        , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( PEC_XSTOP2_UNIT2                                        , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( PEC_XSTOP2_UNIT3                                        , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( PEC_XSTOP2_UNIT4                                        , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( PEC_XSTOP2_UNIT5                                        , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( PEC_XSTOP2_UNIT6                                        , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( PEC_XSTOP2_UNIT7                                        , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( PEC_XSTOP2_UNIT8                                        , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( PEC_XSTOP2_UNIT9                                        , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( PEC_XSTOP2_UNIT10                                       , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( PEC_XSTOP2_WAIT_CYCLES                                  , 48  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( PEC_XSTOP2_WAIT_CYCLES_LEN                              , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( PEC_XSTOP3_MASK_B                                       , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_MASK_B     );
+REG64_FLD( PEC_XSTOP3_UNUSED                                       , 1   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PEC_XSTOP3_TRIGGER_OPCG_ON                              , 2   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( PEC_XSTOP3_WAIT_ALLWAYS                                 , 3   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( PEC_XSTOP3_PERV                                         , 4   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( PEC_XSTOP3_UNIT1                                        , 5   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( PEC_XSTOP3_UNIT2                                        , 6   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( PEC_XSTOP3_UNIT3                                        , 7   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( PEC_XSTOP3_UNIT4                                        , 8   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( PEC_XSTOP3_UNIT5                                        , 9   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( PEC_XSTOP3_UNIT6                                        , 10  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( PEC_XSTOP3_UNIT7                                        , 11  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( PEC_XSTOP3_UNIT8                                        , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( PEC_XSTOP3_UNIT9                                        , 13  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( PEC_XSTOP3_UNIT10                                       , 14  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( PEC_XSTOP3_WAIT_CYCLES                                  , 48  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( PEC_XSTOP3_WAIT_CYCLES_LEN                              , 12  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE1                  , 0   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE2                  , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE3                  , 8   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_CTL_TICK                      , 20  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK   );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_CTL_TICK_LEN                  , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK_LEN );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_INH0_TICK                     , 26  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK  );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_INH0_TICK_LEN                 , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK_LEN );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_INH1_TICK                     , 32  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK  );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_INH1_TICK_LEN                 , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK_LEN );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE1                 , 38  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1 );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE1_LEN             , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1_LEN );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE2                 , 40  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2 );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE2_LEN             , 6   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_ND_RATE1               , 46  , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1 );
+REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_ND_RATE1_LEN           , 2   , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1_LEN );
+
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE1                  , 0   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE2                  , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE3                  , 8   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_CTL_TICK                      , 20  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK   );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_CTL_TICK_LEN                  , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK_LEN );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_INH0_TICK                     , 26  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK  );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_INH0_TICK_LEN                 , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK_LEN );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_INH1_TICK                     , 32  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK  );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_INH1_TICK_LEN                 , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK_LEN );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_NV_RESP_RATE1                 , 38  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1 );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_NV_RESP_RATE1_LEN             , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1_LEN );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_NV_RESP_RATE2                 , 40  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2 );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_NV_RESP_RATE2_LEN             , 6   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_ND_RATE1               , 46  , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1 );
+REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_ND_RATE1_LEN           , 2   , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1_LEN );
+
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE1                  , 0   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE2                  , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE3                  , 8   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_CTL_TICK                      , 20  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK   );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_CTL_TICK_LEN                  , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK_LEN );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_INH0_TICK                     , 26  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK  );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_INH0_TICK_LEN                 , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK_LEN );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_INH1_TICK                     , 32  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK  );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_INH1_TICK_LEN                 , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK_LEN );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE1                 , 38  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1 );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE1_LEN             , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1_LEN );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE2                 , 40  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2 );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE2_LEN             , 6   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_ND_RATE1               , 46  , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1 );
+REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_ND_RATE1_LEN           , 2   , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1_LEN );
+
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE1                  , 0   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE2                  , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE3                  , 8   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_CTL_TICK                      , 20  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK   );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_CTL_TICK_LEN                  , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK_LEN );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_INH0_TICK                     , 26  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK  );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_INH0_TICK_LEN                 , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK_LEN );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_INH1_TICK                     , 32  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK  );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_INH1_TICK_LEN                 , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK_LEN );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_NV_RESP_RATE1                 , 38  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1 );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_NV_RESP_RATE1_LEN             , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1_LEN );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_NV_RESP_RATE2                 , 40  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2 );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_NV_RESP_RATE2_LEN             , 6   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_ND_RATE1               , 46  , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1 );
+REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_ND_RATE1_LEN           , 2   , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1_LEN );
+
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE1                  , 0   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE2                  , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE3                  , 8   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_CTL_TICK                      , 20  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK   );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_CTL_TICK_LEN                  , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK_LEN );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_INH0_TICK                     , 26  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK  );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_INH0_TICK_LEN                 , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK_LEN );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_INH1_TICK                     , 32  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK  );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_INH1_TICK_LEN                 , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK_LEN );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE1                 , 38  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1 );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE1_LEN             , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1_LEN );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE2                 , 40  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2 );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE2_LEN             , 6   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_ND_RATE1               , 46  , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1 );
+REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_ND_RATE1_LEN           , 2   , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1_LEN );
+
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE1                  , 0   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE2                  , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE3                  , 8   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_CTL_TICK                      , 20  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK   );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_CTL_TICK_LEN                  , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK_LEN );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_INH0_TICK                     , 26  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK  );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_INH0_TICK_LEN                 , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK_LEN );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_INH1_TICK                     , 32  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK  );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_INH1_TICK_LEN                 , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK_LEN );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_NV_RESP_RATE1                 , 38  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1 );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_NV_RESP_RATE1_LEN             , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1_LEN );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_NV_RESP_RATE2                 , 40  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2 );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_NV_RESP_RATE2_LEN             , 6   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_ND_RATE1               , 46  , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1 );
+REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_ND_RATE1_LEN           , 2   , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1_LEN );
+
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE1                  , 0   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE2                  , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE3                  , 8   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_CTL_TICK                      , 20  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK   );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_CTL_TICK_LEN                  , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK_LEN );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_INH0_TICK                     , 26  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK  );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_INH0_TICK_LEN                 , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK_LEN );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_INH1_TICK                     , 32  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK  );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_INH1_TICK_LEN                 , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK_LEN );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_NV_RESP_RATE1                 , 38  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1 );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_NV_RESP_RATE1_LEN             , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1_LEN );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_NV_RESP_RATE2                 , 40  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2 );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_NV_RESP_RATE2_LEN             , 6   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_ND_RATE1               , 46  , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1 );
+REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_ND_RATE1_LEN           , 2   , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1_LEN );
+
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE1                  , 0   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE2                  , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE3                  , 8   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_CTL_TICK                      , 20  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK   );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_CTL_TICK_LEN                  , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK_LEN );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_INH0_TICK                     , 26  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK  );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_INH0_TICK_LEN                 , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK_LEN );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_INH1_TICK                     , 32  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK  );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_INH1_TICK_LEN                 , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK_LEN );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE1                 , 38  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1 );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE1_LEN             , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1_LEN );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE2                 , 40  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2 );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE2_LEN             , 6   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_ND_RATE1               , 46  , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1 );
+REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_ND_RATE1_LEN           , 2   , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1_LEN );
+
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE1                  , 0   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE2                  , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE3                  , 8   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_CTL_TICK                      , 20  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK   );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_CTL_TICK_LEN                  , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK_LEN );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_INH0_TICK                     , 26  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK  );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_INH0_TICK_LEN                 , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK_LEN );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_INH1_TICK                     , 32  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK  );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_INH1_TICK_LEN                 , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK_LEN );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_NV_RESP_RATE1                 , 38  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1 );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_NV_RESP_RATE1_LEN             , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1_LEN );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_NV_RESP_RATE2                 , 40  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2 );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_NV_RESP_RATE2_LEN             , 6   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_ND_RATE1               , 46  , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1 );
+REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_ND_RATE1_LEN           , 2   , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1_LEN );
+
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE1                  , 0   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE2                  , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE3                  , 8   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_CTL_TICK                      , 20  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK   );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_CTL_TICK_LEN                  , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK_LEN );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_INH0_TICK                     , 26  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK  );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_INH0_TICK_LEN                 , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK_LEN );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_INH1_TICK                     , 32  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK  );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_INH1_TICK_LEN                 , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK_LEN );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE1                 , 38  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1 );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE1_LEN             , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1_LEN );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE2                 , 40  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2 );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE2_LEN             , 6   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2_LEN );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_ND_RATE1               , 46  , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1 );
+REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_ND_RATE1_LEN           , 2   , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1_LEN );
+
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE1                  , 0   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE2                  , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE3                  , 8   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_CTL_TICK                      , 20  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK   );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_CTL_TICK_LEN                  , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK_LEN );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_INH0_TICK                     , 26  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK  );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_INH0_TICK_LEN                 , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK_LEN );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_INH1_TICK                     , 32  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK  );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_INH1_TICK_LEN                 , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK_LEN );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE1                 , 38  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1 );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE1_LEN             , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1_LEN );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE2                 , 40  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2 );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE2_LEN             , 6   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2_LEN );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_ND_RATE1               , 46  , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1 );
+REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_ND_RATE1_LEN           , 2   , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1_LEN );
+
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE1                  , 0   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1 );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE1_LEN              , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE1_LEN );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE2                  , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2 );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE2_LEN              , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE3                  , 8   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3 );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE3_LEN              , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_RATE3_LEN );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_FWD_PROG_RATE2                , 14  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2 );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_FWD_PROG_RATE2_LEN            , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_FWD_PROG_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_CTL_TICK                      , 20  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK   );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_CTL_TICK_LEN                  , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_CTL_TICK_LEN );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_INH0_TICK                     , 26  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK  );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_INH0_TICK_LEN                 , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_INH0_TICK_LEN );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_INH1_TICK                     , 32  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK  );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_INH1_TICK_LEN                 , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_INH1_TICK_LEN );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_NV_RESP_RATE1                 , 38  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1 );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_NV_RESP_RATE1_LEN             , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE1_LEN );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_NV_RESP_RATE2                 , 40  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2 );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_NV_RESP_RATE2_LEN             , 6   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_NV_RESP_RATE2_LEN );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_ND_RATE1               , 46  , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1 );
+REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_ND_RATE1_LEN           , 2   , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM     ,
+           SH_FLD_POCKET_ND_RATE1_LEN );
+
+REG64_FLD( PEC_XTRA_TRACE_MODE_DATA                                , 0   , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DATA       );
+REG64_FLD( PEC_XTRA_TRACE_MODE_DATA_LEN                            , 38  , SH_UNT_PEC      , SH_ACS_SCOM     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_XTRA_TRACE_MODE_DATA                                 , 0   , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA       );
+REG64_FLD( PU_XTRA_TRACE_MODE_DATA_LEN                             , 38  , SH_UNT          , SH_ACS_SCOM     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_ADDR                             , 15  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ADDR       );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_ADDR_LEN                         , 37  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ADDR_LEN   );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_FLAG_OTHER                       , 54  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FLAG_OTHER );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_FLAG_PREF                        , 55  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FLAG_PREF  );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_FLAG_DMD                         , 56  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FLAG_DMD   );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_FLAG_MAP                         , 57  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FLAG_MAP   );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_FLAG_FENCE                       , 58  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_FLAG_FENCE );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_RETIRE                           , 59  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_RETIRE     );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_IRQENA                           , 60  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_IRQENA     );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_SECOND                           , 61  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_SECOND     );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_TRIGGERED                        , 62  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_TRIGGERED  );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_ENA                              , 63  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ENA        );
+
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS2_ATRMISS_GPA                     , 27  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_GPA );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS2_ATRMISS_BDF                     , 28  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_BDF );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS2_ATRMISS_BDF_LEN                 , 16  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_BDF_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS2_ATRMISS_PASID                   , 44  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_PASID );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISS2_ATRMISS_PASID_LEN               , 20  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_PASID_LEN );
+
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_ADDR                  , 15  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_ADDR );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_ADDR_LEN              , 37  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_ADDR_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_OTHER            , 54  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_FLAG_OTHER );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_PREF             , 55  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_FLAG_PREF );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_DMD              , 56  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_FLAG_DMD );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_MAP              , 57  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_FLAG_MAP );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_FENCE            , 58  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_FLAG_FENCE );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_RETIRE                , 59  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_RETIRE );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_IRQENA                , 60  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_IRQENA );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_SECOND                , 61  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_SECOND );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_TRIGGERED             , 62  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_TRIGGERED );
+REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_ENA                   , 63  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATRMISS_ENA );
+
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP0_LPARID                         , 52  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID     );
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP0_LPARID_LEN                     , 12  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID_LEN );
+
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP1_LPARID                         , 52  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID     );
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP1_LPARID_LEN                     , 12  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID_LEN );
+
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP2_LPARID                         , 52  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID     );
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP2_LPARID_LEN                     , 12  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID_LEN );
+
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP3_LPARID                         , 52  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID     );
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP3_LPARID_LEN                     , 12  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID_LEN );
+
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP4_LPARID                         , 52  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID     );
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP4_LPARID_LEN                     , 12  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID_LEN );
+
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP5_LPARID                         , 52  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID     );
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP5_LPARID_LEN                     , 12  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID_LEN );
+
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP6_LPARID                         , 52  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID     );
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP6_LPARID_LEN                     , 12  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID_LEN );
+
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP7_LPARID                         , 52  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID     );
+REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP7_LPARID_LEN                     , 12  , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM     ,
+           SH_FLD_LPARID_LEN );
+
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_BRAZOS                            , 0   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_BRAZOS     );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_MMIOSD                            , 1   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_MMIOSD     );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_BIG_RSP                           , 2   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_BIG_RSP    );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_CHOP1G                            , 3   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CHOP1G     );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_DIS_NCNP                          , 4   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_DIS_NCNP   );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_OVR_PM                            , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_OVR_PM     );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TRY_ATR_RO                        , 6   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_TRY_ATR_RO );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_SPLURGE                           , 7   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_SPLURGE    );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_LIM_PS                            , 8   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_LIM_PS     );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF2DMD                          , 9   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PREF2DMD   );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREFEVOD                          , 10  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PREFEVOD   );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_EAINJ                             , 11  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_EAINJ      );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1                           , 12  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1    );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1_LEN                       , 4   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_DEC_RATE                    , 16  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_DEC_RATE );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_DEC_RATE_LEN                , 8   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_DEC_RATE_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_INC_RATE                    , 24  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_INC_RATE );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_INC_RATE_LEN                , 8   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_INC_RATE_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_CNT_THRESH                  , 32  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_CNT_THRESH );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_CNT_THRESH_LEN              , 8   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_CNT_THRESH_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED2                           , 40  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2    );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_TIMEOUT                      , 41  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PREF_TIMEOUT );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_TIMEOUT_LEN                  , 3   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PREF_TIMEOUT_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_DEPTH                        , 44  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PREF_DEPTH );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_DEPTH_LEN                    , 4   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PREF_DEPTH_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH0                       , 48  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PREF_THRSH0 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH0_LEN                   , 4   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PREF_THRSH0_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH1                       , 52  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PREF_THRSH1 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH1_LEN                   , 4   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PREF_THRSH1_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH2                       , 56  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PREF_THRSH2 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH2_LEN                   , 4   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PREF_THRSH2_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH3                       , 60  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PREF_THRSH3 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH3_LEN                   , 4   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PREF_THRSH3_LEN );
+
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_ENABLE                      , 0   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_ENABLE );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_RESETMODE                   , 1   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_RESETMODE );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_FREEZEMODE                  , 2   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_FREEZEMODE );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_DISABLE_PMISC               , 3   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_DISABLE_PMISC );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PMISC_MODE                  , 4   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_PMISC_MODE );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_CASCADE                     , 5   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_CASCADE );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_CASCADE_LEN                 , 3   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_CASCADE_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C0                 , 8   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_PRESCALE_C0 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C0_LEN             , 2   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_PRESCALE_C0_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C1                 , 10  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_PRESCALE_C1 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C1_LEN             , 2   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_PRESCALE_C1_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C2                 , 12  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_PRESCALE_C2 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C2_LEN             , 2   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_PRESCALE_C2_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C3                 , 14  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_PRESCALE_C3 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C3_LEN             , 2   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_PRESCALE_C3_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT0                      , 16  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_EVENT0 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT0_LEN                  , 8   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_EVENT0_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT1                      , 24  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_EVENT1 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT1_LEN                  , 8   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_EVENT1_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT2                      , 32  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_EVENT2 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT2_LEN                  , 8   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_EVENT2_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT3                      , 40  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_EVENT3 );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT3_LEN                  , 8   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_PERF_EVENT3_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_UNUSED                           , 48  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_UNUSED_LEN                       , 8   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_ATSD_TIMEOUT                     , 56  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATSD_TIMEOUT );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_ATSD_TIMEOUT_LEN                 , 4   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATSD_TIMEOUT_LEN );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_ATR_TIMEOUT                      , 60  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATR_TIMEOUT );
+REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_ATR_TIMEOUT_LEN                  , 4   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_ATR_TIMEOUT_LEN );
+
+REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT0                             , 0   , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CNT0       );
+REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT0_LEN                         , 16  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CNT0_LEN   );
+REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT1                             , 16  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CNT1       );
+REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT1_LEN                         , 16  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CNT1_LEN   );
+REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT2                             , 32  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CNT2       );
+REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT2_LEN                         , 16  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CNT2_LEN   );
+REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT3                             , 48  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CNT3       );
+REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT3_LEN                         , 16  , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM     ,
+           SH_FLD_CNT3_LEN   );
+
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld_fixes.H b/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld_fixes.H
new file mode 100644
index 00000000..b62d9d92
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_misc_scom_addresses_fld_fixes.H
@@ -0,0 +1,71 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_misc_scom_addresses_fld_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file misc_scom_addresses_fld_fixes.H
+/// @brief The *scom_addresses_fld.H files are generated form figtree,
+///        but the figree can be wrong.  This file is included in
+///        *_scom_addresses_fld.H and allows incorrect constants to be
+///        fixed manually.
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SAO
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __P9_MISC_SCOM_ADDRESSES_FLD_FIXES_H
+#define __P9_MISC_SCOM_ADDRESSES_FLD_FIXES_H
+
+// N2 Chiplet Config Register1
+REG64_FLD(PERV_N2_CPLT_CONF1_TC_PSI_IOVALID_DC,  10, SH_UNT, SH_ACS_SCOM, SH_FLD_UNUSED);
+
+// PSI Receive Status Register
+REG64_FLD(PU_RX_PSI_STATUS_CHECK_PASS,            0, SH_UNT, SH_ACS_SCOM, SH_FLD_UNUSED);
+REG64_FLD(PU_RX_PSI_STATUS_CHECK_FAIL,            1, SH_UNT, SH_ACS_SCOM, SH_FLD_UNUSED);
+
+// PSI Transmit Control Register
+REG64_FLD(PU_TX_PSI_CNTL_IORESET,                 0, SH_UNT, SH_ACS_SCOM, SH_FLD_UNUSED);
+
+// PSI Receive Control Register
+REG64_FLD(PU_RX_PSI_CNTL_IORESET,                 0, SH_UNT, SH_ACS_SCOM, SH_FLD_UNUSED);
+
+// PSI Transmit Channel Internal Address Register
+REG64_FLD(PU_TX_CH_INTADDR_IAR_ADDR,              0, SH_UNT, SH_ACS_SCOM, SH_FLD_UNUSED);
+REG64_FLD(PU_TX_CH_INTADDR_IAR_ADDR_LEN,          8, SH_UNT, SH_ACS_SCOM, SH_FLD_UNUSED);
+
+// PSI Transmit Channel Misc Register
+REG64_FLD(PU_TX_CH_MISC_WEN0,                    12, SH_UNT, SH_ACS_SCOM, SH_FLD_UNUSED);
+REG64_FLD(PU_TX_CH_MISC_WEN1,                    13, SH_UNT, SH_ACS_SCOM, SH_FLD_UNUSED);
+REG64_FLD(PU_TX_CH_MISC_WEN2,                    14, SH_UNT, SH_ACS_SCOM, SH_FLD_UNUSED);
+
+//Example
+//Copy the whole line from the *scom_addresses_fld.H file.  Then add FIX in front of REG
+//and add another paramter that is the new value you want.
+//
+//FIXREG64_FLD( PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE, 24, SH_UNT, SH_ACS_SCOM, SH_FLD_FBC_WITH_TM_QUIESCE,
+//              12);
+
+
+#endif
diff --git a/src/import/chips/p9/common/include/p9_obus_scom_addresses.H b/src/import/chips/p9/common/include/p9_obus_scom_addresses.H
new file mode 100644
index 00000000..48ac3c2c
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_obus_scom_addresses.H
@@ -0,0 +1,10583 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_obus_scom_addresses.H $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_obus_scom_addresses.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+/*---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ *
+ *  Issues:
+ *
+ * Closed
+ *    TOD reg same address.             HW323439
+ *       - Issue was closed with the explaination "same as p8"
+ *    IO0 registers need fixed.         HW320437
+ *    PHB registers need fixed.         HW320416  ( all regs commented out now )
+ *    OSC/perv regs same address.       HW323437
+ *    MC regs with same address.        HW323435 (matteo)
+ *         Duplicate IOM registers.          HW320456 (designers)
+ *    PEC Sat_id issue                  HW329652
+ *    PB.PB_PPE registers need fixed.   HW320435
+ *    EX05 registers need fixed.        HW320427  (9020) - L2 ring id's are incorrect
+ *    IOFPPE registers need fixed.      HW320424  (9020) - Investigate NULL scope
+ *    PEC addresses are wrong.          HW322598  (9020)
+ *    MC registers need fixed.          HW320433
+ *    VA.VA_NORTH registers need fixed. HW320436
+ *
+ * Format:
+ *
+ *  <UNIT>_<SUBUNIT>_<INSTANCE>_<REGISTER>_<ACCESS/TYPE>
+ *
+ *  Notes: Subunits are only added to make names unique when
+ *  there are name collisions.
+ *  Only units with more than one instance has instance numbers.
+ *  If there is only one, the instance number is omitted.
+ *
+ *  Instance numbers are chiplet id's for the PERV unit.  The
+ *  chiplet id's are mapped to their name and used instead of
+ *  instance numbers.  See bellow.
+ *
+ *  For registers with a single access type the type and access
+ *  methods are omitted.
+ *
+ *  For access types where all bits have the same access methods, the
+ *  access method is appended to the name.  If the access methods
+ *  are different for some bits, the access type is appended to the
+ *  name _SCOM instead of _RO.  The _RW(X) access method is omitted
+ *  and assumed to be default.
+ *
+ *  Valid units / subunits
+ *    PU                    : No unit chip level
+ *        MCD0[0..1]        : mcd subunit
+ *        PIB2OPB[0..1]     : PIB2OPB subunit
+ *        OTPROM[0..1]      : otprom subunit
+ *        NPU               : common npu subunit
+ *        NPU[0..2]         : Npu stacks 0 to 2
+ *          CTL             : Npu CTL subunit
+ *          DAT             : Npu DAT subunit
+ *          SM[0..3]        : Npu SM subunits
+ *          NTL[0..1]       : Npu NTL subunit
+ *    PERV                  : Pervasive
+ *        FSI2PIB           : subunit
+ *        FSISHIFT          : subunit
+ *        FSII2C            : subunit
+ *        FSB               : subunit
+ *    EX                    : Ex unit (1/2 quad, 2 cores)
+ *        L2                : L2 subunit
+ *        L3                : L3 subunit
+ *    PEC                   : PCI Pec unit
+ *        STACK0            : subunit
+ *        STACK1            : subunit
+ *        STACK2            : subunit
+ *    C                     : core
+ *    EQ                    : quad
+ *    OBUS                  : obus
+ *    CAPP                  : capp
+ *    MCBIST                : mcbist
+ *    MCA                   : mca
+ *    NVBUS                 : (not implemented yet)
+ *    PHB                   : (not implemented yet)
+ *    MI                    : (not implemented yet)
+ *    DMI                   : (not implemented yet)
+ *    MCS                   : (not implemented yet)
+ *    OCC                   : (not implemented yet)
+ *    PPE                   : (not implemented yet)
+ *    SBE                   : (not implemented yet)
+ *    XBUS                  : (not implemented yet)
+ *
+ * Pervasive instance names follow chiplet id.
+ *
+ * Instance/  | Chiplet
+ * Chiplet    | name
+ * -----------+-----------
+ * 0x00       | PIB
+ * 0x01       | TP
+ * 0x02       | N0
+ * 0x03       | N1
+ * 0x04       | N2
+ * 0x05       | N3
+ * 0x06       | XB
+ * 0x07       | MC01
+ * 0x08       | MC23
+ * 0x09       | OB0
+ * 0x0A       | OB1
+ * 0x0B       | OB2
+ * 0x0C       | OB3
+ * 0x0D       | PCI0
+ * 0x0E       | PCI1
+ * 0x0F       | PCI2
+ * 0x10       | EP00
+ * 0x11       | EP01
+ * 0x12       | EP02
+ * 0x13       | EP03
+ * 0x14       | EP04
+ * 0x15       | EP05
+ * 0x20       | EC00
+ * 0x21       | EC01
+ * 0x22       | EC02
+ * 0x23       | EC03
+ * 0x24       | EC04
+ * 0x25       | EC05
+ * 0x26       | EC06
+ * 0x27       | EC07
+ * 0x28       | EC08
+ * 0x29       | EC09
+ * 0x2A       | EC10
+ * 0x2B       | EC11
+ * 0x2C       | EC12
+ * 0x2D       | EC13
+ * 0x2E       | EC14
+ * 0x2F       | EC15
+ * 0x30       | EC16
+ * 0x31       | EC17
+ * 0x32       | EC18
+ * 0x33       | EC19
+ * 0x34       | EC20
+ * 0x35       | EC21
+ * 0x36       | EC22
+ * 0x37       | EC23
+ *
+ *
+ *---------------------------------------------------------------
+ *
+ * NOTES:
+ *
+ * there is a SPR ring that goes around the chip with an
+ * address(0:9)/tid(0:1) (thread id)/mfspr_data(0:63) and return mfspr_data_v/mfspr_data(0:63)
+ *
+ *    Add PU_<SUBUNITS>  (only if there are conflicts on these registers)
+ *       0x0001XXXX OTPROM
+ *       0x0002XXXX FSIM0
+ *       0x0003XXXX FSIM1
+ *       0x0004XXXX TOD
+ *       0x0005XXXX FSI_MBOX
+ *       0x0006XXXX OCI_BRIDGE
+ *       0x0007XXXX SPI_ADC
+ *       0x0008XXXX PIBMEM
+ *       0x0009XXXX ADU
+ *       0x000AXXXX I2CM
+ *       0x000BXXXX SBE_FIFO
+ *       0x000DXXXX PSU
+ *       0x000EXXXX SBE
+ *
+ * 0x0000100A for FSI2PIB  => PERV_FSI2PIB
+ * 0x00000Cxx for FSISHIFT =>  PERV_FSISHIFT
+ * 0x000018xx for FSI I2C =>  PERV_FSII2C
+ * 0x000024xx for FSI SBEFIFO => PERV_FSB
+ *
+ * 0x00000400 PEEK_TABLE
+ * 0x00000800 FSI_SLAVE
+ * 0x00000C00 FSI_SHIFT
+ * 0x00001000 FSI2PIB
+ * 0x00001400 FSI_SCRATCHPAD
+ * 0x00001800 FSI_I2CM
+ * 0x00002400 FSI_SBE_FIFO
+ *
+ * address fields
+ * 0xCCRPxxxx
+ *
+ * CC=chiplet
+ * R=always 0?
+ * P=port
+ *   0=gpregs
+ *   1=normal unit scom ring (exclude)
+ *   3=clock controller
+ *   4=firs
+ *   5=cpm
+ *
+ * =============================================================================
+ * Compiling
+ *
+ * Precompile the header to save time on subsquent compiles:
+ * g++ -I. -c scom_addresses.H
+ *
+ * Use these options to help reduce the binary size
+ * g++ -I. -Os -fdata-sections -ffunction-sections <file>.C -o <output> -Wl,--gc-sections
+ *
+ *
+ *---------------------------------------------------------------
+ */
+
+#include <p9_const_common.H>
+
+
+#ifndef __P9_OBUS_SCOM_ADDRESSES_H
+#define __P9_OBUS_SCOM_ADDRESSES_H
+
+
+#include <p9_scom_template_consts.H>
+#include <p9_obus_scom_addresses_fixes.H>
+
+
+REG64( OBUS_LL0_IOOL_CONFIG                                    , RULL(0x0901080A), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_CONFIG                                  , RULL(0x0901080A), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_CONTROL                                   , RULL(0x0901080B), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_CONTROL                                 , RULL(0x0901080B), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_DLL_STATUS                                , RULL(0x09010828), SH_UNT_OBUS     , SH_ACS_SCOM_RO   );
+REG64( OBUS_0_LL0_IOOL_DLL_STATUS                              , RULL(0x09010828), SH_UNT_OBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_LL0_IOOL_ERR_INJ_LFSR                              , RULL(0x0901081B), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_ERR_INJ_LFSR                            , RULL(0x0901081B), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_LAT_MEASURE                               , RULL(0x0901080E), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_LAT_MEASURE                             , RULL(0x0901080E), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_LINK0_EDPL_STATUS                         , RULL(0x09010824), SH_UNT_OBUS     , SH_ACS_SCOM_RO   );
+REG64( OBUS_0_LL0_IOOL_LINK0_EDPL_STATUS                       , RULL(0x09010824), SH_UNT_OBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_LL0_IOOL_LINK0_ERROR_STATUS                        , RULL(0x09010816), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_LINK0_ERROR_STATUS                      , RULL(0x09010816), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_LINK0_INFO                                , RULL(0x09010814), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_LINK0_INFO                              , RULL(0x09010814), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_LINK0_QUALITY                             , RULL(0x09010826), SH_UNT_OBUS     , SH_ACS_SCOM_RO   );
+REG64( OBUS_0_LL0_IOOL_LINK0_QUALITY                           , RULL(0x09010826), SH_UNT_OBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL                     , RULL(0x09010812), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_LINK0_RX_LANE_CONTROL                   , RULL(0x09010812), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE                         , RULL(0x09010822), SH_UNT_OBUS     , SH_ACS_SCOM_RW   );
+REG64( OBUS_0_LL0_IOOL_LINK0_SYN_CAPTURE                       , RULL(0x09010822), SH_UNT_OBUS_0   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL                     , RULL(0x09010810), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_LINK0_TX_LANE_CONTROL                   , RULL(0x09010810), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_LINK1_EDPL_STATUS                         , RULL(0x09010825), SH_UNT_OBUS     , SH_ACS_SCOM_RO   );
+REG64( OBUS_0_LL0_IOOL_LINK1_EDPL_STATUS                       , RULL(0x09010825), SH_UNT_OBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_LL0_IOOL_LINK1_ERROR_STATUS                        , RULL(0x09010817), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_LINK1_ERROR_STATUS                      , RULL(0x09010817), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_LINK1_INFO                                , RULL(0x09010815), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_LINK1_INFO                              , RULL(0x09010815), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_LINK1_QUALITY                             , RULL(0x09010827), SH_UNT_OBUS     , SH_ACS_SCOM_RO   );
+REG64( OBUS_0_LL0_IOOL_LINK1_QUALITY                           , RULL(0x09010827), SH_UNT_OBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL                     , RULL(0x09010813), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_LINK1_RX_LANE_CONTROL                   , RULL(0x09010813), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE                         , RULL(0x09010823), SH_UNT_OBUS     , SH_ACS_SCOM_RW   );
+REG64( OBUS_0_LL0_IOOL_LINK1_SYN_CAPTURE                       , RULL(0x09010823), SH_UNT_OBUS_0   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL                     , RULL(0x09010811), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_LINK1_TX_LANE_CONTROL                   , RULL(0x09010811), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_LINKX_ERROR_STATUS                        , RULL(0x09010829), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_LINKX_ERROR_STATUS                      , RULL(0x09010829), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_OPTICAL_CONFIG                            , RULL(0x0901080F), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_OPTICAL_CONFIG                          , RULL(0x0901080F), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_PERF_COUNTERS_0                           , RULL(0x0901081E), SH_UNT_OBUS     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( OBUS_0_LL0_IOOL_PERF_COUNTERS_0                         , RULL(0x0901081E), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( OBUS_LL0_IOOL_PERF_COUNTERS_1                           , RULL(0x0901081F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( OBUS_0_LL0_IOOL_PERF_COUNTERS_1                         , RULL(0x0901081F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( OBUS_LL0_IOOL_PERF_COUNT_LSB_0                          , RULL(0x09010820), SH_UNT_OBUS     , SH_ACS_SCOM_RO   );
+REG64( OBUS_0_LL0_IOOL_PERF_COUNT_LSB_0                        , RULL(0x09010820), SH_UNT_OBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_LL0_IOOL_PERF_COUNT_LSB_1                          , RULL(0x09010821), SH_UNT_OBUS     , SH_ACS_SCOM_RO   );
+REG64( OBUS_0_LL0_IOOL_PERF_COUNT_LSB_1                        , RULL(0x09010821), SH_UNT_OBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_LL0_IOOL_PERF_SEL_CONFIG                           , RULL(0x0901081D), SH_UNT_OBUS     , SH_ACS_SCOM_RW   );
+REG64( OBUS_0_LL0_IOOL_PERF_SEL_CONFIG                         , RULL(0x0901081D), SH_UNT_OBUS_0   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_LL0_IOOL_PERF_TRACE_CONFIG                         , RULL(0x0901081C), SH_UNT_OBUS     , SH_ACS_SCOM_RW   );
+REG64( OBUS_0_LL0_IOOL_PERF_TRACE_CONFIG                       , RULL(0x0901081C), SH_UNT_OBUS_0   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_LL0_IOOL_PHY_CONFIG                                , RULL(0x0901080C), SH_UNT_OBUS     , SH_ACS_SCOM_RW   );
+REG64( OBUS_0_LL0_IOOL_PHY_CONFIG                              , RULL(0x0901080C), SH_UNT_OBUS_0   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_LL0_IOOL_REPLAY_THRESHOLD                          , RULL(0x09010818), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_REPLAY_THRESHOLD                        , RULL(0x09010818), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_RETRAIN_THRESHOLD                         , RULL(0x0901081A), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_RETRAIN_THRESHOLD                       , RULL(0x0901081A), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_IOOL_SEC_CONFIG                                , RULL(0x0901080D), SH_UNT_OBUS     , SH_ACS_SCOM_RW   );
+REG64( OBUS_0_LL0_IOOL_SEC_CONFIG                              , RULL(0x0901080D), SH_UNT_OBUS_0   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_LL0_IOOL_SL_ECC_THRESHOLD                          , RULL(0x09010819), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_LL0_IOOL_SL_ECC_THRESHOLD                        , RULL(0x09010819), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG                   , RULL(0x09010803), SH_UNT_OBUS     , SH_ACS_SCOM_RW   );
+REG64( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_AND               , RULL(0x09010804), SH_UNT_OBUS     , SH_ACS_SCOM1_AND );
+REG64( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_OR                , RULL(0x09010805), SH_UNT_OBUS     , SH_ACS_SCOM2_OR  );
+REG64( OBUS_0_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG                 , RULL(0x09010803), SH_UNT_OBUS_0   , SH_ACS_SCOM_RW   );
+REG64( OBUS_0_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_AND             , RULL(0x09010804), SH_UNT_OBUS_0   , SH_ACS_SCOM1_AND );
+REG64( OBUS_0_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_OR              , RULL(0x09010805), SH_UNT_OBUS_0   , SH_ACS_SCOM2_OR  );
+
+REG64( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG                        , RULL(0x09010800), SH_UNT_OBUS     , SH_ACS_SCOM_RW   );
+REG64( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_AND                    , RULL(0x09010801), SH_UNT_OBUS     , SH_ACS_SCOM1_AND );
+REG64( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_OR                     , RULL(0x09010802), SH_UNT_OBUS     , SH_ACS_SCOM2_OR  );
+REG64( OBUS_0_LL0_LL0_LL0_PB_IOOL_FIR_REG                      , RULL(0x09010800), SH_UNT_OBUS_0   , SH_ACS_SCOM_RW   );
+REG64( OBUS_0_LL0_LL0_LL0_PB_IOOL_FIR_REG_AND                  , RULL(0x09010801), SH_UNT_OBUS_0   , SH_ACS_SCOM1_AND );
+REG64( OBUS_0_LL0_LL0_LL0_PB_IOOL_FIR_REG_OR                   , RULL(0x09010802), SH_UNT_OBUS_0   , SH_ACS_SCOM2_OR  );
+
+REG64( OBUS_LL0_PB_IOOL_FIR_ACTION0_REG                        , RULL(0x09010806), SH_UNT_OBUS     , SH_ACS_SCOM_RW   );
+REG64( OBUS_0_LL0_PB_IOOL_FIR_ACTION0_REG                      , RULL(0x09010806), SH_UNT_OBUS_0   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_LL0_PB_IOOL_FIR_ACTION1_REG                        , RULL(0x09010807), SH_UNT_OBUS     , SH_ACS_SCOM_RW   );
+REG64( OBUS_0_LL0_PB_IOOL_FIR_ACTION1_REG                      , RULL(0x09010807), SH_UNT_OBUS_0   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_3_LL3_IOOL_CONFIG                                  , RULL(0x0C01080A), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_CONTROL                                 , RULL(0x0C01080B), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_DLL_STATUS                              , RULL(0x0C010828), SH_UNT_OBUS_3   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_3_LL3_IOOL_ERR_INJ_LFSR                            , RULL(0x0C01081B), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_LAT_MEASURE                             , RULL(0x0C01080E), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_LINK0_EDPL_STATUS                       , RULL(0x0C010824), SH_UNT_OBUS_3   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_3_LL3_IOOL_LINK0_ERROR_STATUS                      , RULL(0x0C010816), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_LINK0_INFO                              , RULL(0x0C010814), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_LINK0_QUALITY                           , RULL(0x0C010826), SH_UNT_OBUS_3   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_3_LL3_IOOL_LINK0_RX_LANE_CONTROL                   , RULL(0x0C010812), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_LINK0_SYN_CAPTURE                       , RULL(0x0C010822), SH_UNT_OBUS_3   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_3_LL3_IOOL_LINK0_TX_LANE_CONTROL                   , RULL(0x0C010810), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_LINK1_EDPL_STATUS                       , RULL(0x0C010825), SH_UNT_OBUS_3   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_3_LL3_IOOL_LINK1_ERROR_STATUS                      , RULL(0x0C010817), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_LINK1_INFO                              , RULL(0x0C010815), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_LINK1_QUALITY                           , RULL(0x0C010827), SH_UNT_OBUS_3   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_3_LL3_IOOL_LINK1_RX_LANE_CONTROL                   , RULL(0x0C010813), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_LINK1_SYN_CAPTURE                       , RULL(0x0C010823), SH_UNT_OBUS_3   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_3_LL3_IOOL_LINK1_TX_LANE_CONTROL                   , RULL(0x0C010811), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_LINKX_ERROR_STATUS                      , RULL(0x0C010829), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_OPTICAL_CONFIG                          , RULL(0x0C01080F), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_PERF_COUNTERS_0                         , RULL(0x0C01081E), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( OBUS_3_LL3_IOOL_PERF_COUNTERS_1                         , RULL(0x0C01081F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( OBUS_3_LL3_IOOL_PERF_COUNT_LSB_0                        , RULL(0x0C010820), SH_UNT_OBUS_3   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_3_LL3_IOOL_PERF_COUNT_LSB_1                        , RULL(0x0C010821), SH_UNT_OBUS_3   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_3_LL3_IOOL_PERF_SEL_CONFIG                         , RULL(0x0C01081D), SH_UNT_OBUS_3   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_3_LL3_IOOL_PERF_TRACE_CONFIG                       , RULL(0x0C01081C), SH_UNT_OBUS_3   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_3_LL3_IOOL_PHY_CONFIG                              , RULL(0x0C01080C), SH_UNT_OBUS_3   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_3_LL3_IOOL_REPLAY_THRESHOLD                        , RULL(0x0C010818), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_RETRAIN_THRESHOLD                       , RULL(0x0C01081A), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_IOOL_SEC_CONFIG                              , RULL(0x0C01080D), SH_UNT_OBUS_3   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_3_LL3_IOOL_SL_ECC_THRESHOLD                        , RULL(0x0C010819), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_LL3_LL3_LL3_PB_IOOL_FIR_MASK_REG                 , RULL(0x0C010803), SH_UNT_OBUS_3   , SH_ACS_SCOM_RW   );
+REG64( OBUS_3_LL3_LL3_LL3_PB_IOOL_FIR_MASK_REG_AND             , RULL(0x0C010804), SH_UNT_OBUS_3   , SH_ACS_SCOM1_AND );
+REG64( OBUS_3_LL3_LL3_LL3_PB_IOOL_FIR_MASK_REG_OR              , RULL(0x0C010805), SH_UNT_OBUS_3   , SH_ACS_SCOM2_OR  );
+
+REG64( OBUS_3_LL3_LL3_LL3_PB_IOOL_FIR_REG                      , RULL(0x0C010800), SH_UNT_OBUS_3   , SH_ACS_SCOM_RW   );
+REG64( OBUS_3_LL3_LL3_LL3_PB_IOOL_FIR_REG_AND                  , RULL(0x0C010801), SH_UNT_OBUS_3   , SH_ACS_SCOM1_AND );
+REG64( OBUS_3_LL3_LL3_LL3_PB_IOOL_FIR_REG_OR                   , RULL(0x0C010802), SH_UNT_OBUS_3   , SH_ACS_SCOM2_OR  );
+
+REG64( OBUS_3_LL3_PB_IOOL_FIR_ACTION0_REG                      , RULL(0x0C010806), SH_UNT_OBUS_3   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_3_LL3_PB_IOOL_FIR_ACTION1_REG                      , RULL(0x0C010807), SH_UNT_OBUS_3   , SH_ACS_SCOM_RW   );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x800248000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x800250000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x800258000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x800260000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL             , RULL(0x8002200009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x8002200009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x800220000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL             , RULL(0x8002280009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x8002280009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x800228000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL             , RULL(0x8002300009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x8002300009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x800230000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL             , RULL(0x8002380009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL           , RULL(0x8002380009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL           , RULL(0x800238000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL             , RULL(0x8002680009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x8002680009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x800268000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL              , RULL(0x8003180009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL            , RULL(0x8003180009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL            , RULL(0x800318000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL             , RULL(0x8002700009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x8002700009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x800270000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL             , RULL(0x8002780009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x8002780009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x800278000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL             , RULL(0x8002800009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL           , RULL(0x8002800009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_BIT_STAT4_EO_PL           , RULL(0x800280000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x800008000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_O_PL              , RULL(0x8000800009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_O_PL            , RULL(0x8000800009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_O_PL            , RULL(0x800080000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x800010000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL              , RULL(0x8000880009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL            , RULL(0x8000880009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL            , RULL(0x800088000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x800018000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL              , RULL(0x8000900009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL            , RULL(0x8000900009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL            , RULL(0x800090000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x800020000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL              , RULL(0x8000980009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL            , RULL(0x8000980009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL            , RULL(0x800098000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x800028000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x800030000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x800038000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x800040000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL                 , RULL(0x8002100009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL               , RULL(0x8002100009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL               , RULL(0x800210000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_PL                      , RULL(0x8002080009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_FIR_PL                    , RULL(0x8002080009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_FIR_PL                    , RULL(0x800208000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL               , RULL(0x8002000009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL             , RULL(0x8002000009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL             , RULL(0x800200000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x800248010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x800250010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x800258010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x800260010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL             , RULL(0x8002200109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x8002200109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x800220010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL             , RULL(0x8002280109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x8002280109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x800228010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL             , RULL(0x8002300109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x8002300109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x800230010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL             , RULL(0x8002380109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL           , RULL(0x8002380109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL           , RULL(0x800238010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL             , RULL(0x8002680109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x8002680109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x800268010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL              , RULL(0x8003180109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL            , RULL(0x8003180109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL            , RULL(0x800318010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL             , RULL(0x8002700109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x8002700109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x800270010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL             , RULL(0x8002780109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x8002780109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x800278010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL             , RULL(0x8002800109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL           , RULL(0x8002800109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_BIT_STAT4_EO_PL           , RULL(0x800280010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x800008010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_O_PL              , RULL(0x8000800109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_O_PL            , RULL(0x8000800109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_O_PL            , RULL(0x800080010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x800010010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL              , RULL(0x8000880109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL            , RULL(0x8000880109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL            , RULL(0x800088010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x800018010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL              , RULL(0x8000900109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL            , RULL(0x8000900109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL            , RULL(0x800090010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x800020010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL              , RULL(0x8000980109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL            , RULL(0x8000980109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL            , RULL(0x800098010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x800028010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x800030010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x800038010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x800040010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL                 , RULL(0x8002100109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL               , RULL(0x8002100109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL               , RULL(0x800210010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_PL                      , RULL(0x8002080109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_FIR_PL                    , RULL(0x8002080109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_FIR_PL                    , RULL(0x800208010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL               , RULL(0x8002000109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL             , RULL(0x8002000109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL             , RULL(0x800200010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x800248020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x800250020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x800258020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x800260020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL             , RULL(0x8002200209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x8002200209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x800220020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL             , RULL(0x8002280209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x8002280209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x800228020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL             , RULL(0x8002300209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x8002300209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x800230020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL             , RULL(0x8002380209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL           , RULL(0x8002380209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL           , RULL(0x800238020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL             , RULL(0x8002680209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x8002680209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x800268020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL              , RULL(0x8003180209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL            , RULL(0x8003180209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL            , RULL(0x800318020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL             , RULL(0x8002700209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x8002700209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x800270020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL             , RULL(0x8002780209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x8002780209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x800278020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL             , RULL(0x8002800209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL           , RULL(0x8002800209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_BIT_STAT4_EO_PL           , RULL(0x800280020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x800008020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_O_PL              , RULL(0x8000800209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_O_PL            , RULL(0x8000800209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_O_PL            , RULL(0x800080020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x800010020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL              , RULL(0x8000880209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL            , RULL(0x8000880209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL            , RULL(0x800088020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x800018020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL              , RULL(0x8000900209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL            , RULL(0x8000900209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL            , RULL(0x800090020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x800020020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL              , RULL(0x8000980209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL            , RULL(0x8000980209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL            , RULL(0x800098020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x800028020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x800030020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x800038020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x800040020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL                 , RULL(0x8002100209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL               , RULL(0x8002100209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL               , RULL(0x800210020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_PL                      , RULL(0x8002080209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_FIR_PL                    , RULL(0x8002080209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_FIR_PL                    , RULL(0x800208020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL               , RULL(0x8002000209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL             , RULL(0x8002000209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL             , RULL(0x800200020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL             , RULL(0x8002200309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x8002200309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL             , RULL(0x8002280309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x8002280309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL             , RULL(0x8002300309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x8002300309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL             , RULL(0x8002380309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL           , RULL(0x8002380309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL           , RULL(0x800238030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL             , RULL(0x8002680309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x8002680309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL              , RULL(0x8003180309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL            , RULL(0x8003180309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL            , RULL(0x800318030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL             , RULL(0x8002700309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x8002700309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL             , RULL(0x8002780309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x8002780309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL             , RULL(0x8002800309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL           , RULL(0x8002800309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_BIT_STAT4_EO_PL           , RULL(0x800280030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_O_PL              , RULL(0x8000800309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_O_PL            , RULL(0x8000800309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_O_PL            , RULL(0x800080030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL              , RULL(0x8000880309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL            , RULL(0x8000880309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL            , RULL(0x800088030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL              , RULL(0x8000900309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL            , RULL(0x8000900309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL            , RULL(0x800090030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL              , RULL(0x8000980309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL            , RULL(0x8000980309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL            , RULL(0x800098030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL                 , RULL(0x8002100309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL               , RULL(0x8002100309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_PL                      , RULL(0x8002080309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_FIR_PL                    , RULL(0x8002080309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_FIR_PL                    , RULL(0x800208030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL               , RULL(0x8002000309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL             , RULL(0x8002000309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x800248040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x800250040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x800258040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x800260040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL             , RULL(0x8002200409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x8002200409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x800220040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL             , RULL(0x8002280409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x8002280409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x800228040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL             , RULL(0x8002300409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x8002300409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x800230040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL             , RULL(0x8002380409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL           , RULL(0x8002380409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL           , RULL(0x800238040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL             , RULL(0x8002680409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x8002680409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x800268040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL              , RULL(0x8003180409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL            , RULL(0x8003180409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL            , RULL(0x800318040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL             , RULL(0x8002700409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x8002700409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x800270040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL             , RULL(0x8002780409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x8002780409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x800278040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL             , RULL(0x8002800409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL           , RULL(0x8002800409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_BIT_STAT4_EO_PL           , RULL(0x800280040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x800008040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_O_PL              , RULL(0x8000800409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_O_PL            , RULL(0x8000800409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_O_PL            , RULL(0x800080040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x800010040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL              , RULL(0x8000880409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL            , RULL(0x8000880409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL            , RULL(0x800088040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x800018040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL              , RULL(0x8000900409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL            , RULL(0x8000900409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL            , RULL(0x800090040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x800020040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL              , RULL(0x8000980409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL            , RULL(0x8000980409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL            , RULL(0x800098040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x800028040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x800030040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x800038040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x800040040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL                 , RULL(0x8002100409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL               , RULL(0x8002100409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL               , RULL(0x800210040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_PL                      , RULL(0x8002080409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_FIR_PL                    , RULL(0x8002080409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_FIR_PL                    , RULL(0x800208040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL               , RULL(0x8002000409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL             , RULL(0x8002000409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL             , RULL(0x800200040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x800248050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x800250050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x800258050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x800260050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL             , RULL(0x8002200509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x8002200509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x800220050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL             , RULL(0x8002280509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x8002280509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x800228050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL             , RULL(0x8002300509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x8002300509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x800230050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL             , RULL(0x8002380509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL           , RULL(0x8002380509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL           , RULL(0x800238050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL             , RULL(0x8002680509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x8002680509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x800268050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL              , RULL(0x8003180509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL            , RULL(0x8003180509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL            , RULL(0x800318050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL             , RULL(0x8002700509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x8002700509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x800270050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL             , RULL(0x8002780509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x8002780509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x800278050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL             , RULL(0x8002800509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL           , RULL(0x8002800509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_BIT_STAT4_EO_PL           , RULL(0x800280050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x800008050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_O_PL              , RULL(0x8000800509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_O_PL            , RULL(0x8000800509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_O_PL            , RULL(0x800080050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x800010050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL              , RULL(0x8000880509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL            , RULL(0x8000880509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL            , RULL(0x800088050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x800018050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL              , RULL(0x8000900509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL            , RULL(0x8000900509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL            , RULL(0x800090050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x800020050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL              , RULL(0x8000980509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL            , RULL(0x8000980509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL            , RULL(0x800098050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x800028050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x800030050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x800038050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x800040050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL                 , RULL(0x8002100509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL               , RULL(0x8002100509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL               , RULL(0x800210050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_PL                      , RULL(0x8002080509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_FIR_PL                    , RULL(0x8002080509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_FIR_PL                    , RULL(0x800208050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL               , RULL(0x8002000509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL             , RULL(0x8002000509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL             , RULL(0x800200050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x800248060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x800250060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x800258060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x800260060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL             , RULL(0x8002200609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x8002200609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x800220060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL             , RULL(0x8002280609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x8002280609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x800228060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL             , RULL(0x8002300609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x8002300609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x800230060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL             , RULL(0x8002380609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL           , RULL(0x8002380609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL           , RULL(0x800238060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL             , RULL(0x8002680609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x8002680609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x800268060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL              , RULL(0x8003180609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL            , RULL(0x8003180609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL            , RULL(0x800318060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL             , RULL(0x8002700609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x8002700609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x800270060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL             , RULL(0x8002780609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x8002780609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x800278060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL             , RULL(0x8002800609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL           , RULL(0x8002800609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_BIT_STAT4_EO_PL           , RULL(0x800280060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x800008060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_O_PL              , RULL(0x8000800609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_O_PL            , RULL(0x8000800609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_O_PL            , RULL(0x800080060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x800010060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL              , RULL(0x8000880609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL            , RULL(0x8000880609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL            , RULL(0x800088060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x800018060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL              , RULL(0x8000900609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL            , RULL(0x8000900609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL            , RULL(0x800090060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x800020060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL              , RULL(0x8000980609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL            , RULL(0x8000980609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL            , RULL(0x800098060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x800028060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x800030060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x800038060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x800040060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL                 , RULL(0x8002100609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL               , RULL(0x8002100609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL               , RULL(0x800210060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_PL                      , RULL(0x8002080609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_FIR_PL                    , RULL(0x8002080609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_FIR_PL                    , RULL(0x800208060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL               , RULL(0x8002000609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL             , RULL(0x8002000609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL             , RULL(0x800200060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL             , RULL(0x8002200709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x8002200709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL             , RULL(0x8002280709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x8002280709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL             , RULL(0x8002300709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x8002300709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL             , RULL(0x8002380709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL           , RULL(0x8002380709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL           , RULL(0x800238070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL             , RULL(0x8002680709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x8002680709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL              , RULL(0x8003180709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL            , RULL(0x8003180709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL            , RULL(0x800318070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL             , RULL(0x8002700709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x8002700709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL             , RULL(0x8002780709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x8002780709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL             , RULL(0x8002800709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL           , RULL(0x8002800709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_BIT_STAT4_EO_PL           , RULL(0x800280070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_O_PL              , RULL(0x8000800709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_O_PL            , RULL(0x8000800709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_O_PL            , RULL(0x800080070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL              , RULL(0x8000880709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL            , RULL(0x8000880709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL            , RULL(0x800088070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL              , RULL(0x8000900709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL            , RULL(0x8000900709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL            , RULL(0x800090070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL              , RULL(0x8000980709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL            , RULL(0x8000980709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL            , RULL(0x800098070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL                 , RULL(0x8002100709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL               , RULL(0x8002100709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_PL                      , RULL(0x8002080709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_FIR_PL                    , RULL(0x8002080709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_FIR_PL                    , RULL(0x800208070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL               , RULL(0x8002000709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL             , RULL(0x8002000709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x800248080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x800250080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x800258080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x800260080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL             , RULL(0x8002200809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x8002200809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x800220080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL             , RULL(0x8002280809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x8002280809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x800228080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL             , RULL(0x8002300809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x8002300809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x800230080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL             , RULL(0x8002380809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL           , RULL(0x8002380809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL           , RULL(0x800238080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL             , RULL(0x8002680809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x8002680809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x800268080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL              , RULL(0x8003180809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL            , RULL(0x8003180809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL            , RULL(0x800318080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL             , RULL(0x8002700809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x8002700809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x800270080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL             , RULL(0x8002780809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x8002780809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x800278080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL             , RULL(0x8002800809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL           , RULL(0x8002800809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_BIT_STAT4_EO_PL           , RULL(0x800280080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x800008080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_O_PL              , RULL(0x8000800809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_O_PL            , RULL(0x8000800809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_O_PL            , RULL(0x800080080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x800010080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL              , RULL(0x8000880809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL            , RULL(0x8000880809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL            , RULL(0x800088080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x800018080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL              , RULL(0x8000900809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL            , RULL(0x8000900809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL            , RULL(0x800090080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x800020080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL              , RULL(0x8000980809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL            , RULL(0x8000980809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL            , RULL(0x800098080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x800028080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x800030080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x800038080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x800040080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL                 , RULL(0x8002100809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL               , RULL(0x8002100809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL               , RULL(0x800210080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_PL                      , RULL(0x8002080809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_FIR_PL                    , RULL(0x8002080809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_FIR_PL                    , RULL(0x800208080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL               , RULL(0x8002000809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL             , RULL(0x8002000809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL             , RULL(0x800200080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x800248090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x800250090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x800258090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x800260090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL             , RULL(0x8002200909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x8002200909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x800220090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL             , RULL(0x8002280909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x8002280909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x800228090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL             , RULL(0x8002300909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x8002300909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x800230090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL             , RULL(0x8002380909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL           , RULL(0x8002380909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL           , RULL(0x800238090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL             , RULL(0x8002680909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x8002680909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x800268090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL              , RULL(0x8003180909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL            , RULL(0x8003180909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL            , RULL(0x800318090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL             , RULL(0x8002700909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x8002700909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x800270090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL             , RULL(0x8002780909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x8002780909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x800278090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL             , RULL(0x8002800909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL           , RULL(0x8002800909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_BIT_STAT4_EO_PL           , RULL(0x800280090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x800008090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_O_PL              , RULL(0x8000800909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_O_PL            , RULL(0x8000800909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_O_PL            , RULL(0x800080090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x800010090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL              , RULL(0x8000880909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL            , RULL(0x8000880909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL            , RULL(0x800088090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x800018090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL              , RULL(0x8000900909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL            , RULL(0x8000900909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL            , RULL(0x800090090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x800020090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL              , RULL(0x8000980909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL            , RULL(0x8000980909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL            , RULL(0x800098090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x800028090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x800030090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x800038090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x800040090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL                 , RULL(0x8002100909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL               , RULL(0x8002100909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL               , RULL(0x800210090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_PL                      , RULL(0x8002080909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_FIR_PL                    , RULL(0x8002080909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_FIR_PL                    , RULL(0x800208090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL               , RULL(0x8002000909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL             , RULL(0x8002000909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL             , RULL(0x800200090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL             , RULL(0x8002200A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x8002200A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x8002200A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL             , RULL(0x8002280A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x8002280A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x8002280A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL             , RULL(0x8002300A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x8002300A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x8002300A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL             , RULL(0x8002380A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL           , RULL(0x8002380A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL           , RULL(0x8002380A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL             , RULL(0x8002680A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x8002680A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x8002680A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL              , RULL(0x8003180A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL            , RULL(0x8003180A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL            , RULL(0x8003180A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL             , RULL(0x8002700A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x8002700A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x8002700A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL             , RULL(0x8002780A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x8002780A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x8002780A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL             , RULL(0x8002800A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL           , RULL(0x8002800A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_BIT_STAT4_EO_PL           , RULL(0x8002800A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_O_PL              , RULL(0x8000800A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_O_PL            , RULL(0x8000800A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_O_PL            , RULL(0x8000800A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL              , RULL(0x8000880A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL            , RULL(0x8000880A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL            , RULL(0x8000880A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL              , RULL(0x8000900A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL            , RULL(0x8000900A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL            , RULL(0x8000900A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL              , RULL(0x8000980A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL            , RULL(0x8000980A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL            , RULL(0x8000980A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL                 , RULL(0x8002100A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL               , RULL(0x8002100A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL               , RULL(0x8002100A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_PL                      , RULL(0x8002080A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_FIR_PL                    , RULL(0x8002080A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_FIR_PL                    , RULL(0x8002080A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL               , RULL(0x8002000A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL             , RULL(0x8002000A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL             , RULL(0x8002000A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL             , RULL(0x8002200B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x8002200B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x8002200B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL             , RULL(0x8002280B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x8002280B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x8002280B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL             , RULL(0x8002300B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x8002300B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x8002300B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL             , RULL(0x8002380B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL           , RULL(0x8002380B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL           , RULL(0x8002380B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL             , RULL(0x8002680B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x8002680B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x8002680B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL              , RULL(0x8003180B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL            , RULL(0x8003180B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL            , RULL(0x8003180B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL             , RULL(0x8002700B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x8002700B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x8002700B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL             , RULL(0x8002780B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x8002780B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x8002780B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL             , RULL(0x8002800B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL           , RULL(0x8002800B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_BIT_STAT4_EO_PL           , RULL(0x8002800B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_O_PL              , RULL(0x8000800B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_O_PL            , RULL(0x8000800B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_O_PL            , RULL(0x8000800B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL              , RULL(0x8000880B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL            , RULL(0x8000880B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL            , RULL(0x8000880B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL              , RULL(0x8000900B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL            , RULL(0x8000900B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL            , RULL(0x8000900B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL              , RULL(0x8000980B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL            , RULL(0x8000980B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL            , RULL(0x8000980B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL                 , RULL(0x8002100B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL               , RULL(0x8002100B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL               , RULL(0x8002100B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_PL                      , RULL(0x8002080B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_FIR_PL                    , RULL(0x8002080B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_FIR_PL                    , RULL(0x8002080B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL               , RULL(0x8002000B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL             , RULL(0x8002000B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL             , RULL(0x8002000B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL             , RULL(0x8002200C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x8002200C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x8002200C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL             , RULL(0x8002280C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x8002280C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x8002280C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL             , RULL(0x8002300C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x8002300C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x8002300C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL             , RULL(0x8002380C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL           , RULL(0x8002380C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL           , RULL(0x8002380C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL             , RULL(0x8002680C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x8002680C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x8002680C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL              , RULL(0x8003180C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL            , RULL(0x8003180C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL            , RULL(0x8003180C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL             , RULL(0x8002700C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x8002700C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x8002700C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL             , RULL(0x8002780C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x8002780C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x8002780C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL             , RULL(0x8002800C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL           , RULL(0x8002800C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_BIT_STAT4_EO_PL           , RULL(0x8002800C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_O_PL              , RULL(0x8000800C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_O_PL            , RULL(0x8000800C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_O_PL            , RULL(0x8000800C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL              , RULL(0x8000880C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL            , RULL(0x8000880C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL            , RULL(0x8000880C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL              , RULL(0x8000900C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL            , RULL(0x8000900C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL            , RULL(0x8000900C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL              , RULL(0x8000980C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL            , RULL(0x8000980C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL            , RULL(0x8000980C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL                 , RULL(0x8002100C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL               , RULL(0x8002100C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL               , RULL(0x8002100C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_PL                      , RULL(0x8002080C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_FIR_PL                    , RULL(0x8002080C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_FIR_PL                    , RULL(0x8002080C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL               , RULL(0x8002000C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL             , RULL(0x8002000C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL             , RULL(0x8002000C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL             , RULL(0x8002200D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x8002200D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x8002200D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL             , RULL(0x8002280D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x8002280D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x8002280D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL             , RULL(0x8002300D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x8002300D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x8002300D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL             , RULL(0x8002380D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL           , RULL(0x8002380D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL           , RULL(0x8002380D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL             , RULL(0x8002680D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x8002680D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x8002680D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL              , RULL(0x8003180D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL            , RULL(0x8003180D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL            , RULL(0x8003180D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL             , RULL(0x8002700D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x8002700D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x8002700D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL             , RULL(0x8002780D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x8002780D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x8002780D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL             , RULL(0x8002800D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL           , RULL(0x8002800D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_BIT_STAT4_EO_PL           , RULL(0x8002800D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_O_PL              , RULL(0x8000800D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_O_PL            , RULL(0x8000800D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_O_PL            , RULL(0x8000800D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL              , RULL(0x8000880D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL            , RULL(0x8000880D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL            , RULL(0x8000880D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL              , RULL(0x8000900D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL            , RULL(0x8000900D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL            , RULL(0x8000900D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL              , RULL(0x8000980D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL            , RULL(0x8000980D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL            , RULL(0x8000980D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL                 , RULL(0x8002100D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL               , RULL(0x8002100D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL               , RULL(0x8002100D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_PL                      , RULL(0x8002080D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_FIR_PL                    , RULL(0x8002080D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_FIR_PL                    , RULL(0x8002080D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL               , RULL(0x8002000D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL             , RULL(0x8002000D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL             , RULL(0x8002000D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL             , RULL(0x8002200E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x8002200E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x8002200E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL             , RULL(0x8002280E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x8002280E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x8002280E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL             , RULL(0x8002300E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x8002300E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x8002300E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL             , RULL(0x8002380E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL           , RULL(0x8002380E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL           , RULL(0x8002380E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL             , RULL(0x8002680E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x8002680E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x8002680E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL              , RULL(0x8003180E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL            , RULL(0x8003180E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL            , RULL(0x8003180E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL             , RULL(0x8002700E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x8002700E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x8002700E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL             , RULL(0x8002780E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x8002780E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x8002780E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL             , RULL(0x8002800E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL           , RULL(0x8002800E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_BIT_STAT4_EO_PL           , RULL(0x8002800E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_O_PL              , RULL(0x8000800E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_O_PL            , RULL(0x8000800E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_O_PL            , RULL(0x8000800E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL              , RULL(0x8000880E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL            , RULL(0x8000880E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL            , RULL(0x8000880E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL              , RULL(0x8000900E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL            , RULL(0x8000900E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL            , RULL(0x8000900E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL              , RULL(0x8000980E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL            , RULL(0x8000980E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL            , RULL(0x8000980E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL                 , RULL(0x8002100E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL               , RULL(0x8002100E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL               , RULL(0x8002100E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_PL                      , RULL(0x8002080E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_FIR_PL                    , RULL(0x8002080E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_FIR_PL                    , RULL(0x8002080E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL               , RULL(0x8002000E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL             , RULL(0x8002000E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL             , RULL(0x8002000E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL             , RULL(0x8002200F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x8002200F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x8002200F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL             , RULL(0x8002280F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x8002280F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x8002280F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL             , RULL(0x8002300F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x8002300F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x8002300F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL             , RULL(0x8002380F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL           , RULL(0x8002380F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL           , RULL(0x8002380F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL             , RULL(0x8002680F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x8002680F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x8002680F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL              , RULL(0x8003180F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL            , RULL(0x8003180F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL            , RULL(0x8003180F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL             , RULL(0x8002700F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x8002700F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x8002700F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL             , RULL(0x8002780F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x8002780F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x8002780F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL             , RULL(0x8002800F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL           , RULL(0x8002800F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_BIT_STAT4_EO_PL           , RULL(0x8002800F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL             , RULL(0x8000C80F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL           , RULL(0x8000C80F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_O_PL              , RULL(0x8000800F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_O_PL            , RULL(0x8000800F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_O_PL            , RULL(0x8000800F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL              , RULL(0x8000880F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL            , RULL(0x8000880F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL            , RULL(0x8000880F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL              , RULL(0x8000900F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL            , RULL(0x8000900F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL            , RULL(0x8000900F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL              , RULL(0x8000980F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL            , RULL(0x8000980F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL            , RULL(0x8000980F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL              , RULL(0x8000A00F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL            , RULL(0x8000A00F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL              , RULL(0x8000A80F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL            , RULL(0x8000A80F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_O_PL              , RULL(0x8000B00F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_O_PL            , RULL(0x8000B00F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL              , RULL(0x8000B80F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL            , RULL(0x8000B80F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL              , RULL(0x8000C00F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL            , RULL(0x8000C00F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL                 , RULL(0x8002100F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL               , RULL(0x8002100F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL               , RULL(0x8002100F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_PL                      , RULL(0x8002080F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_FIR_PL                    , RULL(0x8002080F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_FIR_PL                    , RULL(0x8002080F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL               , RULL(0x8002000F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL             , RULL(0x8002000F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL             , RULL(0x8002000F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL             , RULL(0x8002481009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x8002481009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x800248100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL             , RULL(0x8002501009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x8002501009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x800250100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL             , RULL(0x8002581009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x8002581009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x800258100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL5_EO_PL             , RULL(0x8002601009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x8002601009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x800260100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002401009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002401009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL             , RULL(0x8002201009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x8002201009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x800220100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL             , RULL(0x8002281009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x8002281009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x800228100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL             , RULL(0x8002301009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x8002301009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x800230100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL             , RULL(0x8002381009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL           , RULL(0x8002381009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL           , RULL(0x800238100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_EO_PL             , RULL(0x8002681009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x8002681009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x800268100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL              , RULL(0x8003181009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL            , RULL(0x8003181009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL            , RULL(0x800318100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL             , RULL(0x8002701009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x8002701009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x800270100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL             , RULL(0x8002781009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x8002781009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x800278100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL             , RULL(0x8002801009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL           , RULL(0x8002801009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_BIT_STAT4_EO_PL           , RULL(0x800280100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL             , RULL(0x8000C81009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL           , RULL(0x8000C81009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL             , RULL(0x8000081009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x8000081009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x800008100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_O_PL              , RULL(0x8000801009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_O_PL            , RULL(0x8000801009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_O_PL            , RULL(0x800080100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL             , RULL(0x8000101009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x8000101009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x800010100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL              , RULL(0x8000881009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL            , RULL(0x8000881009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL            , RULL(0x800088100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL             , RULL(0x8000181009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x8000181009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x800018100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL              , RULL(0x8000901009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL            , RULL(0x8000901009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL            , RULL(0x800090100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL             , RULL(0x8000201009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x8000201009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x800020100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL              , RULL(0x8000981009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL            , RULL(0x8000981009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL            , RULL(0x800098100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL             , RULL(0x8000281009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x8000281009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x800028100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL              , RULL(0x8000A01009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL            , RULL(0x8000A01009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL             , RULL(0x8000301009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x8000301009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x800030100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL              , RULL(0x8000A81009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL            , RULL(0x8000A81009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL             , RULL(0x8000381009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x8000381009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x800038100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_O_PL              , RULL(0x8000B01009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_O_PL            , RULL(0x8000B01009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_EO_PL             , RULL(0x8000401009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x8000401009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x800040100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL              , RULL(0x8000B81009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL            , RULL(0x8000B81009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL              , RULL(0x8000C01009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL            , RULL(0x8000C01009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000001009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000001009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002181009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002181009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_MASK_PL                 , RULL(0x8002101009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_FIR_MASK_PL               , RULL(0x8002101009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_FIR_MASK_PL               , RULL(0x800210100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_PL                      , RULL(0x8002081009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_FIR_PL                    , RULL(0x8002081009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_FIR_PL                    , RULL(0x800208100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL               , RULL(0x8002001009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL             , RULL(0x8002001009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL             , RULL(0x800200100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL             , RULL(0x8002481109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x8002481109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x800248110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL             , RULL(0x8002501109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x8002501109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x800250110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL             , RULL(0x8002581109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x8002581109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x800258110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL5_EO_PL             , RULL(0x8002601109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x8002601109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x800260110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002401109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002401109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL             , RULL(0x8002201109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x8002201109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x800220110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL             , RULL(0x8002281109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x8002281109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x800228110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL             , RULL(0x8002301109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x8002301109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x800230110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL             , RULL(0x8002381109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL           , RULL(0x8002381109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL           , RULL(0x800238110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_EO_PL             , RULL(0x8002681109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x8002681109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x800268110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL              , RULL(0x8003181109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL            , RULL(0x8003181109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL            , RULL(0x800318110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL             , RULL(0x8002701109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x8002701109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x800270110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL             , RULL(0x8002781109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x8002781109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x800278110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL             , RULL(0x8002801109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL           , RULL(0x8002801109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_BIT_STAT4_EO_PL           , RULL(0x800280110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL             , RULL(0x8000C81109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL           , RULL(0x8000C81109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL             , RULL(0x8000081109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x8000081109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x800008110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_O_PL              , RULL(0x8000801109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_O_PL            , RULL(0x8000801109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_O_PL            , RULL(0x800080110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL             , RULL(0x8000101109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x8000101109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x800010110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL              , RULL(0x8000881109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL            , RULL(0x8000881109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL            , RULL(0x800088110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL             , RULL(0x8000181109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x8000181109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x800018110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL              , RULL(0x8000901109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL            , RULL(0x8000901109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL            , RULL(0x800090110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL             , RULL(0x8000201109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x8000201109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x800020110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL              , RULL(0x8000981109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL            , RULL(0x8000981109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL            , RULL(0x800098110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL             , RULL(0x8000281109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x8000281109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x800028110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL              , RULL(0x8000A01109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL            , RULL(0x8000A01109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL             , RULL(0x8000301109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x8000301109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x800030110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL              , RULL(0x8000A81109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL            , RULL(0x8000A81109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL             , RULL(0x8000381109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x8000381109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x800038110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_O_PL              , RULL(0x8000B01109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_O_PL            , RULL(0x8000B01109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_EO_PL             , RULL(0x8000401109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x8000401109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x800040110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL              , RULL(0x8000B81109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL            , RULL(0x8000B81109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL              , RULL(0x8000C01109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL            , RULL(0x8000C01109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000001109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000001109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002181109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002181109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_MASK_PL                 , RULL(0x8002101109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_FIR_MASK_PL               , RULL(0x8002101109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_FIR_MASK_PL               , RULL(0x800210110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_PL                      , RULL(0x8002081109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_FIR_PL                    , RULL(0x8002081109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_FIR_PL                    , RULL(0x800208110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL               , RULL(0x8002001109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL             , RULL(0x8002001109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL             , RULL(0x800200110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL             , RULL(0x8002481209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x8002481209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x800248120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL             , RULL(0x8002501209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x8002501209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x800250120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL             , RULL(0x8002581209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x8002581209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x800258120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL5_EO_PL             , RULL(0x8002601209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x8002601209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x800260120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002401209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002401209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL             , RULL(0x8002201209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x8002201209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x800220120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL             , RULL(0x8002281209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x8002281209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x800228120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL             , RULL(0x8002301209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x8002301209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x800230120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL             , RULL(0x8002381209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL           , RULL(0x8002381209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL           , RULL(0x800238120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_EO_PL             , RULL(0x8002681209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x8002681209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x800268120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL              , RULL(0x8003181209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL            , RULL(0x8003181209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL            , RULL(0x800318120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL             , RULL(0x8002701209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x8002701209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x800270120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL             , RULL(0x8002781209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x8002781209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x800278120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL             , RULL(0x8002801209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL           , RULL(0x8002801209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_BIT_STAT4_EO_PL           , RULL(0x800280120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL             , RULL(0x8000C81209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL           , RULL(0x8000C81209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL             , RULL(0x8000081209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x8000081209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x800008120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_O_PL              , RULL(0x8000801209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_O_PL            , RULL(0x8000801209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_O_PL            , RULL(0x800080120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL             , RULL(0x8000101209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x8000101209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x800010120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL              , RULL(0x8000881209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL            , RULL(0x8000881209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL            , RULL(0x800088120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL             , RULL(0x8000181209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x8000181209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x800018120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL              , RULL(0x8000901209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL            , RULL(0x8000901209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL            , RULL(0x800090120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL             , RULL(0x8000201209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x8000201209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x800020120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL              , RULL(0x8000981209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL            , RULL(0x8000981209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL            , RULL(0x800098120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL             , RULL(0x8000281209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x8000281209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x800028120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL              , RULL(0x8000A01209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL            , RULL(0x8000A01209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL             , RULL(0x8000301209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x8000301209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x800030120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL              , RULL(0x8000A81209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL            , RULL(0x8000A81209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL             , RULL(0x8000381209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x8000381209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x800038120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_O_PL              , RULL(0x8000B01209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_O_PL            , RULL(0x8000B01209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_EO_PL             , RULL(0x8000401209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x8000401209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x800040120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL              , RULL(0x8000B81209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL            , RULL(0x8000B81209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL              , RULL(0x8000C01209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL            , RULL(0x8000C01209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000001209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000001209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002181209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002181209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_MASK_PL                 , RULL(0x8002101209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_FIR_MASK_PL               , RULL(0x8002101209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_FIR_MASK_PL               , RULL(0x800210120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_PL                      , RULL(0x8002081209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_FIR_PL                    , RULL(0x8002081209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_FIR_PL                    , RULL(0x800208120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL               , RULL(0x8002001209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL             , RULL(0x8002001209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL             , RULL(0x800200120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL             , RULL(0x8002481309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x8002481309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL             , RULL(0x8002501309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x8002501309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL             , RULL(0x8002581309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x8002581309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL5_EO_PL             , RULL(0x8002601309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x8002601309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002401309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002401309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL             , RULL(0x8002201309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x8002201309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL             , RULL(0x8002281309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x8002281309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL             , RULL(0x8002301309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x8002301309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL             , RULL(0x8002381309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL           , RULL(0x8002381309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL           , RULL(0x800238130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_EO_PL             , RULL(0x8002681309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x8002681309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL              , RULL(0x8003181309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL            , RULL(0x8003181309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL            , RULL(0x800318130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL             , RULL(0x8002701309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x8002701309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL             , RULL(0x8002781309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x8002781309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL             , RULL(0x8002801309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL           , RULL(0x8002801309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_BIT_STAT4_EO_PL           , RULL(0x800280130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL             , RULL(0x8000C81309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL           , RULL(0x8000C81309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL             , RULL(0x8000081309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x8000081309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_O_PL              , RULL(0x8000801309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_O_PL            , RULL(0x8000801309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_O_PL            , RULL(0x800080130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL             , RULL(0x8000101309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x8000101309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL              , RULL(0x8000881309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL            , RULL(0x8000881309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL            , RULL(0x800088130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL             , RULL(0x8000181309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x8000181309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL              , RULL(0x8000901309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL            , RULL(0x8000901309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL            , RULL(0x800090130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL             , RULL(0x8000201309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x8000201309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL              , RULL(0x8000981309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL            , RULL(0x8000981309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL            , RULL(0x800098130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL             , RULL(0x8000281309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x8000281309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL              , RULL(0x8000A01309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL            , RULL(0x8000A01309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL             , RULL(0x8000301309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x8000301309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL              , RULL(0x8000A81309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL            , RULL(0x8000A81309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL             , RULL(0x8000381309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x8000381309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_O_PL              , RULL(0x8000B01309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_O_PL            , RULL(0x8000B01309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_EO_PL             , RULL(0x8000401309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x8000401309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL              , RULL(0x8000B81309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL            , RULL(0x8000B81309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL              , RULL(0x8000C01309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL            , RULL(0x8000C01309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000001309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000001309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002181309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002181309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_MASK_PL                 , RULL(0x8002101309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_FIR_MASK_PL               , RULL(0x8002101309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_PL                      , RULL(0x8002081309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_FIR_PL                    , RULL(0x8002081309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_FIR_PL                    , RULL(0x800208130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL               , RULL(0x8002001309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL             , RULL(0x8002001309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL             , RULL(0x8002481409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x8002481409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x800248140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL             , RULL(0x8002501409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x8002501409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x800250140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL             , RULL(0x8002581409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x8002581409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x800258140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL5_EO_PL             , RULL(0x8002601409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x8002601409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x800260140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002401409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002401409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL             , RULL(0x8002201409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x8002201409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x800220140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL             , RULL(0x8002281409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x8002281409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x800228140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL             , RULL(0x8002301409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x8002301409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x800230140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL             , RULL(0x8002381409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL           , RULL(0x8002381409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL           , RULL(0x800238140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_EO_PL             , RULL(0x8002681409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x8002681409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x800268140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL              , RULL(0x8003181409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL            , RULL(0x8003181409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL            , RULL(0x800318140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL             , RULL(0x8002701409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x8002701409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x800270140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL             , RULL(0x8002781409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x8002781409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x800278140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL             , RULL(0x8002801409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL           , RULL(0x8002801409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_BIT_STAT4_EO_PL           , RULL(0x800280140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL             , RULL(0x8000C81409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL           , RULL(0x8000C81409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL             , RULL(0x8000081409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x8000081409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x800008140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_O_PL              , RULL(0x8000801409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_O_PL            , RULL(0x8000801409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_O_PL            , RULL(0x800080140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL             , RULL(0x8000101409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x8000101409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x800010140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL              , RULL(0x8000881409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL            , RULL(0x8000881409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL            , RULL(0x800088140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL             , RULL(0x8000181409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x8000181409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x800018140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL              , RULL(0x8000901409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL            , RULL(0x8000901409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL            , RULL(0x800090140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL             , RULL(0x8000201409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x8000201409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x800020140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL              , RULL(0x8000981409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL            , RULL(0x8000981409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL            , RULL(0x800098140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL             , RULL(0x8000281409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x8000281409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x800028140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL              , RULL(0x8000A01409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL            , RULL(0x8000A01409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL             , RULL(0x8000301409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x8000301409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x800030140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL              , RULL(0x8000A81409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL            , RULL(0x8000A81409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL             , RULL(0x8000381409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x8000381409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x800038140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_O_PL              , RULL(0x8000B01409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_O_PL            , RULL(0x8000B01409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_EO_PL             , RULL(0x8000401409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x8000401409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x800040140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL              , RULL(0x8000B81409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL            , RULL(0x8000B81409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL              , RULL(0x8000C01409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL            , RULL(0x8000C01409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000001409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000001409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002181409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002181409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_MASK_PL                 , RULL(0x8002101409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_FIR_MASK_PL               , RULL(0x8002101409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_FIR_MASK_PL               , RULL(0x800210140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_PL                      , RULL(0x8002081409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_FIR_PL                    , RULL(0x8002081409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_FIR_PL                    , RULL(0x800208140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL               , RULL(0x8002001409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL             , RULL(0x8002001409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL             , RULL(0x800200140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL             , RULL(0x8002481509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x8002481509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x800248150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL             , RULL(0x8002501509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x8002501509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x800250150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL             , RULL(0x8002581509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x8002581509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x800258150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL5_EO_PL             , RULL(0x8002601509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x8002601509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x800260150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002401509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002401509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL             , RULL(0x8002201509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x8002201509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x800220150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL             , RULL(0x8002281509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x8002281509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x800228150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL             , RULL(0x8002301509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x8002301509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x800230150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL             , RULL(0x8002381509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL           , RULL(0x8002381509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL           , RULL(0x800238150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_EO_PL             , RULL(0x8002681509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x8002681509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x800268150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL              , RULL(0x8003181509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL            , RULL(0x8003181509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL            , RULL(0x800318150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL             , RULL(0x8002701509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x8002701509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x800270150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL             , RULL(0x8002781509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x8002781509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x800278150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL             , RULL(0x8002801509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL           , RULL(0x8002801509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_BIT_STAT4_EO_PL           , RULL(0x800280150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL             , RULL(0x8000C81509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL           , RULL(0x8000C81509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL             , RULL(0x8000081509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x8000081509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x800008150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_O_PL              , RULL(0x8000801509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_O_PL            , RULL(0x8000801509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_O_PL            , RULL(0x800080150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL             , RULL(0x8000101509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x8000101509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x800010150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL              , RULL(0x8000881509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL            , RULL(0x8000881509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL            , RULL(0x800088150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL             , RULL(0x8000181509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x8000181509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x800018150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL              , RULL(0x8000901509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL            , RULL(0x8000901509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL            , RULL(0x800090150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL             , RULL(0x8000201509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x8000201509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x800020150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL              , RULL(0x8000981509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL            , RULL(0x8000981509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL            , RULL(0x800098150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL             , RULL(0x8000281509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x8000281509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x800028150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL              , RULL(0x8000A01509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL            , RULL(0x8000A01509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL             , RULL(0x8000301509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x8000301509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x800030150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL              , RULL(0x8000A81509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL            , RULL(0x8000A81509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL             , RULL(0x8000381509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x8000381509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x800038150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_O_PL              , RULL(0x8000B01509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_O_PL            , RULL(0x8000B01509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_EO_PL             , RULL(0x8000401509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x8000401509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x800040150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL              , RULL(0x8000B81509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL            , RULL(0x8000B81509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL              , RULL(0x8000C01509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL            , RULL(0x8000C01509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000001509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000001509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002181509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002181509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_MASK_PL                 , RULL(0x8002101509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_FIR_MASK_PL               , RULL(0x8002101509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_FIR_MASK_PL               , RULL(0x800210150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_PL                      , RULL(0x8002081509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_FIR_PL                    , RULL(0x8002081509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_FIR_PL                    , RULL(0x800208150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL               , RULL(0x8002001509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL             , RULL(0x8002001509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL             , RULL(0x800200150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL             , RULL(0x8002481609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x8002481609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x800248160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL             , RULL(0x8002501609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x8002501609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x800250160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL             , RULL(0x8002581609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x8002581609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x800258160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL5_EO_PL             , RULL(0x8002601609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x8002601609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x800260160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002401609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002401609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL             , RULL(0x8002201609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x8002201609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x800220160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL             , RULL(0x8002281609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x8002281609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x800228160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL             , RULL(0x8002301609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x8002301609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x800230160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL             , RULL(0x8002381609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL           , RULL(0x8002381609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL           , RULL(0x800238160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_EO_PL             , RULL(0x8002681609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x8002681609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x800268160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL              , RULL(0x8003181609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL            , RULL(0x8003181609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL            , RULL(0x800318160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL             , RULL(0x8002701609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x8002701609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x800270160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL             , RULL(0x8002781609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x8002781609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x800278160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL             , RULL(0x8002801609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL           , RULL(0x8002801609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_BIT_STAT4_EO_PL           , RULL(0x800280160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL             , RULL(0x8000C81609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL           , RULL(0x8000C81609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL             , RULL(0x8000081609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x8000081609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x800008160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_O_PL              , RULL(0x8000801609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_O_PL            , RULL(0x8000801609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_O_PL            , RULL(0x800080160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL             , RULL(0x8000101609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x8000101609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x800010160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL              , RULL(0x8000881609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL            , RULL(0x8000881609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL            , RULL(0x800088160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL             , RULL(0x8000181609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x8000181609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x800018160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL              , RULL(0x8000901609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL            , RULL(0x8000901609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL            , RULL(0x800090160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL             , RULL(0x8000201609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x8000201609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x800020160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL              , RULL(0x8000981609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL            , RULL(0x8000981609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL            , RULL(0x800098160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL             , RULL(0x8000281609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x8000281609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x800028160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL              , RULL(0x8000A01609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL            , RULL(0x8000A01609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL             , RULL(0x8000301609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x8000301609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x800030160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL              , RULL(0x8000A81609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL            , RULL(0x8000A81609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL             , RULL(0x8000381609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x8000381609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x800038160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_O_PL              , RULL(0x8000B01609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_O_PL            , RULL(0x8000B01609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_EO_PL             , RULL(0x8000401609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x8000401609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x800040160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL              , RULL(0x8000B81609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL            , RULL(0x8000B81609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL              , RULL(0x8000C01609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL            , RULL(0x8000C01609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000001609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000001609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002181609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002181609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_MASK_PL                 , RULL(0x8002101609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_FIR_MASK_PL               , RULL(0x8002101609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_FIR_MASK_PL               , RULL(0x800210160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_PL                      , RULL(0x8002081609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_FIR_PL                    , RULL(0x8002081609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_FIR_PL                    , RULL(0x800208160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL               , RULL(0x8002001609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL             , RULL(0x8002001609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL             , RULL(0x800200160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL             , RULL(0x8002481709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x8002481709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL             , RULL(0x8002501709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x8002501709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL             , RULL(0x8002581709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x8002581709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL5_EO_PL             , RULL(0x8002601709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x8002601709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002401709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002401709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL             , RULL(0x8002201709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x8002201709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL             , RULL(0x8002281709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x8002281709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL             , RULL(0x8002301709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x8002301709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL             , RULL(0x8002381709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL           , RULL(0x8002381709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL           , RULL(0x800238170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_EO_PL             , RULL(0x8002681709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x8002681709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL              , RULL(0x8003181709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL            , RULL(0x8003181709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL            , RULL(0x800318170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL             , RULL(0x8002701709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x8002701709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL             , RULL(0x8002781709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x8002781709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL             , RULL(0x8002801709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL           , RULL(0x8002801709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_BIT_STAT4_EO_PL           , RULL(0x800280170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL             , RULL(0x8000C81709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL           , RULL(0x8000C81709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL           , RULL(0x8000C8170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL             , RULL(0x8000081709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x8000081709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_O_PL              , RULL(0x8000801709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_O_PL            , RULL(0x8000801709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_O_PL            , RULL(0x800080170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL             , RULL(0x8000101709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x8000101709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL              , RULL(0x8000881709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL            , RULL(0x8000881709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL            , RULL(0x800088170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL             , RULL(0x8000181709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x8000181709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL              , RULL(0x8000901709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL            , RULL(0x8000901709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL            , RULL(0x800090170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL             , RULL(0x8000201709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x8000201709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL              , RULL(0x8000981709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL            , RULL(0x8000981709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL            , RULL(0x800098170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL             , RULL(0x8000281709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x8000281709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL              , RULL(0x8000A01709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL            , RULL(0x8000A01709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL            , RULL(0x8000A0170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL             , RULL(0x8000301709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x8000301709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL              , RULL(0x8000A81709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL            , RULL(0x8000A81709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL            , RULL(0x8000A8170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL             , RULL(0x8000381709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x8000381709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_O_PL              , RULL(0x8000B01709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_O_PL            , RULL(0x8000B01709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_O_PL            , RULL(0x8000B0170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_EO_PL             , RULL(0x8000401709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x8000401709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL              , RULL(0x8000B81709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL            , RULL(0x8000B81709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL            , RULL(0x8000B8170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL              , RULL(0x8000C01709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL            , RULL(0x8000C01709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL            , RULL(0x8000C0170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000001709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000001709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002181709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002181709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_MASK_PL                 , RULL(0x8002101709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_FIR_MASK_PL               , RULL(0x8002101709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_PL                      , RULL(0x8002081709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_FIR_PL                    , RULL(0x8002081709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_FIR_PL                    , RULL(0x800208170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL               , RULL(0x8002001709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL             , RULL(0x8002001709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_CNTL10_EO_PG                            , RULL(0x8009200009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_CNTL10_EO_PG                          , RULL(0x8009200009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_CNTL10_EO_PG                          , RULL(0x800920000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_CNTL11_EO_PG                            , RULL(0x8009280009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_CNTL11_EO_PG                          , RULL(0x8009280009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_CNTL11_EO_PG                          , RULL(0x800928000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_CNTL12_EO_PG                            , RULL(0x8009300009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_CNTL12_EO_PG                          , RULL(0x8009300009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_CNTL12_EO_PG                          , RULL(0x800930000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_CNTL13_EO_PG                            , RULL(0x8009380009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_CNTL13_EO_PG                          , RULL(0x8009380009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_CNTL13_EO_PG                          , RULL(0x800938000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_CNTL14_EO_PG                            , RULL(0x8009400009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_CNTL14_EO_PG                          , RULL(0x8009400009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_CNTL14_EO_PG                          , RULL(0x800940000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_CNTL1_EO_PG                             , RULL(0x8008D80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_CNTL1_EO_PG                           , RULL(0x8008D80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_CNTL1_EO_PG                           , RULL(0x8008D8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_CNTL2_EO_PG                             , RULL(0x8008E00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_CNTL2_EO_PG                           , RULL(0x8008E00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_CNTL2_EO_PG                           , RULL(0x8008E0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_CNTL3_EO_PG                             , RULL(0x8008E80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_CNTL3_EO_PG                           , RULL(0x8008E80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_CNTL3_EO_PG                           , RULL(0x8008E8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_CNTL4_EO_PG                             , RULL(0x8008F00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_CNTL4_EO_PG                           , RULL(0x8008F00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_CNTL4_EO_PG                           , RULL(0x8008F0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_CNTL5_EO_PG                             , RULL(0x8008F80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_CNTL5_EO_PG                           , RULL(0x8008F80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_CNTL5_EO_PG                           , RULL(0x8008F8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_CNTL6_EO_PG                             , RULL(0x8009000009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_CNTL6_EO_PG                           , RULL(0x8009000009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_CNTL6_EO_PG                           , RULL(0x800900000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_CNTL8_EO_PG                             , RULL(0x8009100009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_CNTL8_EO_PG                           , RULL(0x8009100009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_CNTL8_EO_PG                           , RULL(0x800910000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_CNTL9_EO_PG                             , RULL(0x8009180009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_CNTL9_EO_PG                           , RULL(0x8009180009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_CNTL9_EO_PG                           , RULL(0x800918000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_CNTLX7_EO_PG                            , RULL(0x8009080009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_CNTLX7_EO_PG                          , RULL(0x8009080009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_CNTLX7_EO_PG                          , RULL(0x800908000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE10_EO_PG                            , RULL(0x8008580009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE10_EO_PG                          , RULL(0x8008580009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE10_EO_PG                          , RULL(0x800858000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE11_EO_PG                            , RULL(0x8008600009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE11_EO_PG                          , RULL(0x8008600009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE11_EO_PG                          , RULL(0x800860000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE12_EO_PG                            , RULL(0x8008680009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE12_EO_PG                          , RULL(0x8008680009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE12_EO_PG                          , RULL(0x800868000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE13_EO_PG                            , RULL(0x8008700009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE13_EO_PG                          , RULL(0x8008700009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE13_EO_PG                          , RULL(0x800870000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE14_EO_PG                            , RULL(0x8008780009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE14_EO_PG                          , RULL(0x8008780009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE14_EO_PG                          , RULL(0x800878000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE15_EO_PG                            , RULL(0x8008800009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE15_EO_PG                          , RULL(0x8008800009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE15_EO_PG                          , RULL(0x800880000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE16_EO_PG                            , RULL(0x8008880009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE16_EO_PG                          , RULL(0x8008880009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE16_EO_PG                          , RULL(0x800888000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE17_EO_PG                            , RULL(0x8008900009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE17_EO_PG                          , RULL(0x8008900009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE17_EO_PG                          , RULL(0x800890000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE18_EO_PG                            , RULL(0x8008980009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE18_EO_PG                          , RULL(0x8008980009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE18_EO_PG                          , RULL(0x800898000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE19_EO_PG                            , RULL(0x8008A00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE19_EO_PG                          , RULL(0x8008A00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE19_EO_PG                          , RULL(0x8008A0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE1_EO_PG                             , RULL(0x8008100009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE1_EO_PG                           , RULL(0x8008100009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE1_EO_PG                           , RULL(0x800810000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE1_O_PG                              , RULL(0x8009B00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE1_O_PG                            , RULL(0x8009B00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE1_O_PG                            , RULL(0x8009B0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE20_EO_PG                            , RULL(0x8008A80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE20_EO_PG                          , RULL(0x8008A80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE20_EO_PG                          , RULL(0x8008A8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE21_EO_PG                            , RULL(0x8008B00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE21_EO_PG                          , RULL(0x8008B00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE21_EO_PG                          , RULL(0x8008B0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE22_EO_PG                            , RULL(0x8008B80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE22_EO_PG                          , RULL(0x8008B80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE22_EO_PG                          , RULL(0x8008B8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE23_EO_PG                            , RULL(0x8008C00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE23_EO_PG                          , RULL(0x8008C00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE23_EO_PG                          , RULL(0x8008C0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE24_EO_PG                            , RULL(0x8008C80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE24_EO_PG                          , RULL(0x8008C80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE24_EO_PG                          , RULL(0x8008C8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE26_EO_PG                            , RULL(0x8009680009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE26_EO_PG                          , RULL(0x8009680009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE26_EO_PG                          , RULL(0x800968000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE27_EO_PG                            , RULL(0x8009700009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE27_EO_PG                          , RULL(0x8009700009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE27_EO_PG                          , RULL(0x800970000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE28_EO_PG                            , RULL(0x8009780009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE28_EO_PG                          , RULL(0x8009780009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE28_EO_PG                          , RULL(0x800978000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE29_EO_PG                            , RULL(0x8008D00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE29_EO_PG                          , RULL(0x8008D00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE29_EO_PG                          , RULL(0x8008D0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE2_EO_PG                             , RULL(0x8008180009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE2_EO_PG                           , RULL(0x8008180009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE2_EO_PG                           , RULL(0x800818000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE2_O_PG                              , RULL(0x8009880009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE2_O_PG                            , RULL(0x8009880009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE2_O_PG                            , RULL(0x800988000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE5_EO_PG                             , RULL(0x8008300009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE5_EO_PG                           , RULL(0x8008300009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE5_EO_PG                           , RULL(0x800830000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE6_EO_PG                             , RULL(0x8008380009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE6_EO_PG                           , RULL(0x8008380009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE6_EO_PG                           , RULL(0x800838000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE7_EO_PG                             , RULL(0x8008400009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE7_EO_PG                           , RULL(0x8008400009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE7_EO_PG                           , RULL(0x800840000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_MODE9_EO_PG                             , RULL(0x8008500009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_MODE9_EO_PG                           , RULL(0x8008500009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_MODE9_EO_PG                           , RULL(0x800850000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_STAT1_EO_PG                             , RULL(0x8009500009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_STAT1_EO_PG                           , RULL(0x8009500009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_STAT1_EO_PG                           , RULL(0x800950000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_CTL_STAT2_EO_PG                             , RULL(0x8009580009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_CTL_STAT2_EO_PG                           , RULL(0x8009580009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_CTL_STAT2_EO_PG                           , RULL(0x800958000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_DATASM_CNTLX1_EO_PG                         , RULL(0x800B880009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_DATASM_CNTLX1_EO_PG                       , RULL(0x800B880009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_DATASM_CNTLX1_EO_PG                       , RULL(0x800B88000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_DATASM_SPARE_MODE_PG                        , RULL(0x800B800009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_DATASM_SPARE_MODE_PG                      , RULL(0x800B800009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_DATASM_SPARE_MODE_PG                      , RULL(0x800B80000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_DATASM_STAT10_EO_PG                         , RULL(0x800BD80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_DATASM_STAT10_EO_PG                       , RULL(0x800BD80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_DATASM_STAT10_EO_PG                       , RULL(0x800BD8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_DATASM_STAT11_EO_PG                         , RULL(0x800BE00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_DATASM_STAT11_EO_PG                       , RULL(0x800BE00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_DATASM_STAT11_EO_PG                       , RULL(0x800BE0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_DATASM_STAT1_EO_PG                          , RULL(0x800B900009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_DATASM_STAT1_EO_PG                        , RULL(0x800B900009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_DATASM_STAT1_EO_PG                        , RULL(0x800B90000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_DATASM_STAT2_EO_PG                          , RULL(0x800B980009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_DATASM_STAT2_EO_PG                        , RULL(0x800B980009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_DATASM_STAT2_EO_PG                        , RULL(0x800B98000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_DATASM_STAT3_EO_PG                          , RULL(0x800BA00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_DATASM_STAT3_EO_PG                        , RULL(0x800BA00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_DATASM_STAT3_EO_PG                        , RULL(0x800BA0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_DATASM_STAT4_EO_PG                          , RULL(0x800BA80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_DATASM_STAT4_EO_PG                        , RULL(0x800BA80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_DATASM_STAT4_EO_PG                        , RULL(0x800BA8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_DATASM_STAT5_EO_PG                          , RULL(0x800BB00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_DATASM_STAT5_EO_PG                        , RULL(0x800BB00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_DATASM_STAT5_EO_PG                        , RULL(0x800BB0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_DATASM_STAT6_EO_PG                          , RULL(0x800BB80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_DATASM_STAT6_EO_PG                        , RULL(0x800BB80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_DATASM_STAT6_EO_PG                        , RULL(0x800BB8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_DATASM_STAT7_EO_PG                          , RULL(0x800BC00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_DATASM_STAT7_EO_PG                        , RULL(0x800BC00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_DATASM_STAT7_EO_PG                        , RULL(0x800BC0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_DATASM_STAT8_EO_PG                          , RULL(0x800BC80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_DATASM_STAT8_EO_PG                        , RULL(0x800BC80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_DATASM_STAT8_EO_PG                        , RULL(0x800BC8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_DATASM_STAT9_EO_PG                          , RULL(0x800BD00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_DATASM_STAT9_EO_PG                        , RULL(0x800BD00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_DATASM_STAT9_EO_PG                        , RULL(0x800BD0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_FIR1_ERROR_INJECT_PG                        , RULL(0x800A980009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_FIR1_ERROR_INJECT_PG                      , RULL(0x800A980009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_FIR1_ERROR_INJECT_PG                      , RULL(0x800A98000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_FIR1_MASK_PG                                , RULL(0x800A900009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_FIR1_MASK_PG                              , RULL(0x800A900009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_FIR1_MASK_PG                              , RULL(0x800A90000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_FIR1_PG                                     , RULL(0x800A880009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_FIR1_PG                                   , RULL(0x800A880009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_FIR1_PG                                   , RULL(0x800A88000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_GLBSM_CNTL2_EO_PG                           , RULL(0x800AE00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_GLBSM_CNTL2_EO_PG                         , RULL(0x800AE00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_GLBSM_CNTL2_EO_PG                         , RULL(0x800AE0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_GLBSM_CNTL3_EO_PG                           , RULL(0x800AE80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_GLBSM_CNTL3_EO_PG                         , RULL(0x800AE80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_GLBSM_CNTL3_EO_PG                         , RULL(0x800AE8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_GLBSM_CNTLX1_EO_PG                          , RULL(0x800AB00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_GLBSM_CNTLX1_EO_PG                        , RULL(0x800AB00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_GLBSM_CNTLX1_EO_PG                        , RULL(0x800AB0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG                         , RULL(0x800A800009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_GLBSM_SPARE_MODE_PG                       , RULL(0x800A800009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_GLBSM_SPARE_MODE_PG                       , RULL(0x800A80000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_GLBSM_STAT1_EO_PG                           , RULL(0x800AB80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_GLBSM_STAT1_EO_PG                         , RULL(0x800AB80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_GLBSM_STAT1_EO_PG                         , RULL(0x800AB8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_GLBSM_STAT2_EO_PG                           , RULL(0x800AC00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_GLBSM_STAT2_EO_PG                         , RULL(0x800AC00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_GLBSM_STAT2_EO_PG                         , RULL(0x800AC0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_GLBSM_STAT3_EO_PG                           , RULL(0x800AC80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_GLBSM_STAT3_EO_PG                         , RULL(0x800AC80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_GLBSM_STAT3_EO_PG                         , RULL(0x800AC8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_GLBSM_STAT4_EO_PG                           , RULL(0x800AD00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_GLBSM_STAT4_EO_PG                         , RULL(0x800AD00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_GLBSM_STAT4_EO_PG                         , RULL(0x800AD0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_GLBSM_STAT5_EO_PG                           , RULL(0x800AD80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_GLBSM_STAT5_EO_PG                         , RULL(0x800AD80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_GLBSM_STAT5_EO_PG                         , RULL(0x800AD8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_ID1_PG                                      , RULL(0x8008080009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_ID1_PG                                    , RULL(0x8008080009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_ID1_PG                                    , RULL(0x800808000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_RX_SPARE_MODE_PG                               , RULL(0x8008000009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_RX_SPARE_MODE_PG                             , RULL(0x8008000009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_RX_SPARE_MODE_PG                             , RULL(0x800800000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL                 , RULL(0x8003300009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x8003300009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE0_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x800330000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL                  , RULL(0x8003200009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x8003200009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x800320000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL                  , RULL(0x8003280009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x8003280009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE0_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x800328000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE0_RX_WORK_CNTL1_O_PL                      , RULL(0x8003A80009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE0_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A80009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE0_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A8000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE0_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE0_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE0_RX_WORK_STAT1_EO_PL                   , RULL(0x800388000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE0_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE0_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE0_RX_WORK_STAT2_EO_PL                   , RULL(0x800390000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE0_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE0_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE0_RX_WORK_STAT3_EO_PL                   , RULL(0x800398000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE0_RX_WORK_STAT4_O_PL                      , RULL(0x8003A00009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE0_RX_WORK_STAT4_O_PL                    , RULL(0x8003A00009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE0_RX_WORK_STAT4_O_PL                    , RULL(0x8003A0000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003800A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003800A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003800A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL                , RULL(0x8003300A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003300A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE10_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003300A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL                 , RULL(0x8003200A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003200A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003200A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL                 , RULL(0x8003280A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003280A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE10_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003280A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE10_RX_WORK_CNTL1_O_PL                     , RULL(0x8003A80A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE10_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A80A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE10_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A80A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE10_RX_WORK_STAT1_EO_PL                    , RULL(0x8003880A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE10_RX_WORK_STAT1_EO_PL                  , RULL(0x8003880A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE10_RX_WORK_STAT1_EO_PL                  , RULL(0x8003880A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE10_RX_WORK_STAT2_EO_PL                    , RULL(0x8003900A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE10_RX_WORK_STAT2_EO_PL                  , RULL(0x8003900A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE10_RX_WORK_STAT2_EO_PL                  , RULL(0x8003900A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE10_RX_WORK_STAT3_EO_PL                    , RULL(0x8003980A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE10_RX_WORK_STAT3_EO_PL                  , RULL(0x8003980A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE10_RX_WORK_STAT3_EO_PL                  , RULL(0x8003980A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE10_RX_WORK_STAT4_O_PL                     , RULL(0x8003A00A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE10_RX_WORK_STAT4_O_PL                   , RULL(0x8003A00A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE10_RX_WORK_STAT4_O_PL                   , RULL(0x8003A00A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003800B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003800B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003800B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL                , RULL(0x8003300B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003300B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE11_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003300B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL                 , RULL(0x8003200B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003200B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003200B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL                 , RULL(0x8003280B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003280B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE11_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003280B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE11_RX_WORK_CNTL1_O_PL                     , RULL(0x8003A80B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE11_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A80B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE11_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A80B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE11_RX_WORK_STAT1_EO_PL                    , RULL(0x8003880B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE11_RX_WORK_STAT1_EO_PL                  , RULL(0x8003880B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE11_RX_WORK_STAT1_EO_PL                  , RULL(0x8003880B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE11_RX_WORK_STAT2_EO_PL                    , RULL(0x8003900B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE11_RX_WORK_STAT2_EO_PL                  , RULL(0x8003900B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE11_RX_WORK_STAT2_EO_PL                  , RULL(0x8003900B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE11_RX_WORK_STAT3_EO_PL                    , RULL(0x8003980B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE11_RX_WORK_STAT3_EO_PL                  , RULL(0x8003980B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE11_RX_WORK_STAT3_EO_PL                  , RULL(0x8003980B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE11_RX_WORK_STAT4_O_PL                     , RULL(0x8003A00B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE11_RX_WORK_STAT4_O_PL                   , RULL(0x8003A00B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE11_RX_WORK_STAT4_O_PL                   , RULL(0x8003A00B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003800C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003800C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003800C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL                , RULL(0x8003300C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003300C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE12_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003300C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL                 , RULL(0x8003200C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003200C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003200C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL                 , RULL(0x8003280C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003280C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE12_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003280C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE12_RX_WORK_CNTL1_O_PL                     , RULL(0x8003A80C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE12_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A80C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE12_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A80C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE12_RX_WORK_STAT1_EO_PL                    , RULL(0x8003880C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE12_RX_WORK_STAT1_EO_PL                  , RULL(0x8003880C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE12_RX_WORK_STAT1_EO_PL                  , RULL(0x8003880C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE12_RX_WORK_STAT2_EO_PL                    , RULL(0x8003900C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE12_RX_WORK_STAT2_EO_PL                  , RULL(0x8003900C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE12_RX_WORK_STAT2_EO_PL                  , RULL(0x8003900C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE12_RX_WORK_STAT3_EO_PL                    , RULL(0x8003980C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE12_RX_WORK_STAT3_EO_PL                  , RULL(0x8003980C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE12_RX_WORK_STAT3_EO_PL                  , RULL(0x8003980C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE12_RX_WORK_STAT4_O_PL                     , RULL(0x8003A00C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE12_RX_WORK_STAT4_O_PL                   , RULL(0x8003A00C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE12_RX_WORK_STAT4_O_PL                   , RULL(0x8003A00C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003800D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003800D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003800D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL                , RULL(0x8003300D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003300D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE13_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003300D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL                 , RULL(0x8003200D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003200D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003200D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL                 , RULL(0x8003280D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003280D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE13_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003280D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE13_RX_WORK_CNTL1_O_PL                     , RULL(0x8003A80D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE13_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A80D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE13_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A80D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE13_RX_WORK_STAT1_EO_PL                    , RULL(0x8003880D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE13_RX_WORK_STAT1_EO_PL                  , RULL(0x8003880D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE13_RX_WORK_STAT1_EO_PL                  , RULL(0x8003880D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE13_RX_WORK_STAT2_EO_PL                    , RULL(0x8003900D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE13_RX_WORK_STAT2_EO_PL                  , RULL(0x8003900D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE13_RX_WORK_STAT2_EO_PL                  , RULL(0x8003900D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE13_RX_WORK_STAT3_EO_PL                    , RULL(0x8003980D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE13_RX_WORK_STAT3_EO_PL                  , RULL(0x8003980D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE13_RX_WORK_STAT3_EO_PL                  , RULL(0x8003980D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE13_RX_WORK_STAT4_O_PL                     , RULL(0x8003A00D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE13_RX_WORK_STAT4_O_PL                   , RULL(0x8003A00D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE13_RX_WORK_STAT4_O_PL                   , RULL(0x8003A00D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003800E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003800E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003800E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL                , RULL(0x8003300E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003300E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE14_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003300E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL                 , RULL(0x8003200E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003200E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003200E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL                 , RULL(0x8003280E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003280E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE14_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003280E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE14_RX_WORK_CNTL1_O_PL                     , RULL(0x8003A80E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE14_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A80E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE14_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A80E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE14_RX_WORK_STAT1_EO_PL                    , RULL(0x8003880E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE14_RX_WORK_STAT1_EO_PL                  , RULL(0x8003880E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE14_RX_WORK_STAT1_EO_PL                  , RULL(0x8003880E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE14_RX_WORK_STAT2_EO_PL                    , RULL(0x8003900E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE14_RX_WORK_STAT2_EO_PL                  , RULL(0x8003900E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE14_RX_WORK_STAT2_EO_PL                  , RULL(0x8003900E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE14_RX_WORK_STAT3_EO_PL                    , RULL(0x8003980E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE14_RX_WORK_STAT3_EO_PL                  , RULL(0x8003980E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE14_RX_WORK_STAT3_EO_PL                  , RULL(0x8003980E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE14_RX_WORK_STAT4_O_PL                     , RULL(0x8003A00E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE14_RX_WORK_STAT4_O_PL                   , RULL(0x8003A00E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE14_RX_WORK_STAT4_O_PL                   , RULL(0x8003A00E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003800F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003800F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003800F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL                , RULL(0x8003300F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003300F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE15_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003300F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL                 , RULL(0x8003200F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003200F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003200F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL                 , RULL(0x8003280F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003280F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE15_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003280F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE15_RX_WORK_CNTL1_O_PL                     , RULL(0x8003A80F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE15_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A80F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE15_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A80F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE15_RX_WORK_STAT1_EO_PL                    , RULL(0x8003880F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE15_RX_WORK_STAT1_EO_PL                  , RULL(0x8003880F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE15_RX_WORK_STAT1_EO_PL                  , RULL(0x8003880F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE15_RX_WORK_STAT2_EO_PL                    , RULL(0x8003900F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE15_RX_WORK_STAT2_EO_PL                  , RULL(0x8003900F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE15_RX_WORK_STAT2_EO_PL                  , RULL(0x8003900F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE15_RX_WORK_STAT3_EO_PL                    , RULL(0x8003980F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE15_RX_WORK_STAT3_EO_PL                  , RULL(0x8003980F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE15_RX_WORK_STAT3_EO_PL                  , RULL(0x8003980F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE15_RX_WORK_STAT4_O_PL                     , RULL(0x8003A00F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE15_RX_WORK_STAT4_O_PL                   , RULL(0x8003A00F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE15_RX_WORK_STAT4_O_PL                   , RULL(0x8003A00F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003801009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003801009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL                , RULL(0x8003301009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003301009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE16_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x800330100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL                 , RULL(0x8003201009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003201009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x800320100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL                 , RULL(0x8003281009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003281009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE16_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x800328100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE16_RX_WORK_CNTL1_O_PL                     , RULL(0x8003A81009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE16_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A81009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE16_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A8100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE16_RX_WORK_STAT1_EO_PL                    , RULL(0x8003881009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE16_RX_WORK_STAT1_EO_PL                  , RULL(0x8003881009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE16_RX_WORK_STAT1_EO_PL                  , RULL(0x800388100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE16_RX_WORK_STAT2_EO_PL                    , RULL(0x8003901009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE16_RX_WORK_STAT2_EO_PL                  , RULL(0x8003901009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE16_RX_WORK_STAT2_EO_PL                  , RULL(0x800390100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE16_RX_WORK_STAT3_EO_PL                    , RULL(0x8003981009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE16_RX_WORK_STAT3_EO_PL                  , RULL(0x8003981009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE16_RX_WORK_STAT3_EO_PL                  , RULL(0x800398100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE16_RX_WORK_STAT4_O_PL                     , RULL(0x8003A01009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE16_RX_WORK_STAT4_O_PL                   , RULL(0x8003A01009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE16_RX_WORK_STAT4_O_PL                   , RULL(0x8003A0100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003801109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003801109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL                , RULL(0x8003301109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003301109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE17_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x800330110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL                 , RULL(0x8003201109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003201109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x800320110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL                 , RULL(0x8003281109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003281109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE17_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x800328110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE17_RX_WORK_CNTL1_O_PL                     , RULL(0x8003A81109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE17_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A81109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE17_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A8110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE17_RX_WORK_STAT1_EO_PL                    , RULL(0x8003881109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE17_RX_WORK_STAT1_EO_PL                  , RULL(0x8003881109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE17_RX_WORK_STAT1_EO_PL                  , RULL(0x800388110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE17_RX_WORK_STAT2_EO_PL                    , RULL(0x8003901109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE17_RX_WORK_STAT2_EO_PL                  , RULL(0x8003901109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE17_RX_WORK_STAT2_EO_PL                  , RULL(0x800390110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE17_RX_WORK_STAT3_EO_PL                    , RULL(0x8003981109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE17_RX_WORK_STAT3_EO_PL                  , RULL(0x8003981109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE17_RX_WORK_STAT3_EO_PL                  , RULL(0x800398110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE17_RX_WORK_STAT4_O_PL                     , RULL(0x8003A01109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE17_RX_WORK_STAT4_O_PL                   , RULL(0x8003A01109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE17_RX_WORK_STAT4_O_PL                   , RULL(0x8003A0110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003801209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003801209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL                , RULL(0x8003301209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003301209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE18_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x800330120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL                 , RULL(0x8003201209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003201209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x800320120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL                 , RULL(0x8003281209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003281209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE18_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x800328120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE18_RX_WORK_CNTL1_O_PL                     , RULL(0x8003A81209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE18_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A81209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE18_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A8120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE18_RX_WORK_STAT1_EO_PL                    , RULL(0x8003881209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE18_RX_WORK_STAT1_EO_PL                  , RULL(0x8003881209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE18_RX_WORK_STAT1_EO_PL                  , RULL(0x800388120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE18_RX_WORK_STAT2_EO_PL                    , RULL(0x8003901209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE18_RX_WORK_STAT2_EO_PL                  , RULL(0x8003901209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE18_RX_WORK_STAT2_EO_PL                  , RULL(0x800390120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE18_RX_WORK_STAT3_EO_PL                    , RULL(0x8003981209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE18_RX_WORK_STAT3_EO_PL                  , RULL(0x8003981209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE18_RX_WORK_STAT3_EO_PL                  , RULL(0x800398120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE18_RX_WORK_STAT4_O_PL                     , RULL(0x8003A01209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE18_RX_WORK_STAT4_O_PL                   , RULL(0x8003A01209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE18_RX_WORK_STAT4_O_PL                   , RULL(0x8003A0120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003801309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003801309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL                , RULL(0x8003301309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003301309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE19_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x800330130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL                 , RULL(0x8003201309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003201309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x800320130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL                 , RULL(0x8003281309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003281309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE19_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x800328130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE19_RX_WORK_CNTL1_O_PL                     , RULL(0x8003A81309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE19_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A81309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE19_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A8130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE19_RX_WORK_STAT1_EO_PL                    , RULL(0x8003881309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE19_RX_WORK_STAT1_EO_PL                  , RULL(0x8003881309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE19_RX_WORK_STAT1_EO_PL                  , RULL(0x800388130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE19_RX_WORK_STAT2_EO_PL                    , RULL(0x8003901309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE19_RX_WORK_STAT2_EO_PL                  , RULL(0x8003901309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE19_RX_WORK_STAT2_EO_PL                  , RULL(0x800390130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE19_RX_WORK_STAT3_EO_PL                    , RULL(0x8003981309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE19_RX_WORK_STAT3_EO_PL                  , RULL(0x8003981309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE19_RX_WORK_STAT3_EO_PL                  , RULL(0x800398130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE19_RX_WORK_STAT4_O_PL                     , RULL(0x8003A01309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE19_RX_WORK_STAT4_O_PL                   , RULL(0x8003A01309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE19_RX_WORK_STAT4_O_PL                   , RULL(0x8003A0130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL                 , RULL(0x8003300109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x8003300109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE1_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x800330010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL                  , RULL(0x8003200109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x8003200109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x800320010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL                  , RULL(0x8003280109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x8003280109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE1_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x800328010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE1_RX_WORK_CNTL1_O_PL                      , RULL(0x8003A80109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE1_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A80109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE1_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A8010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE1_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE1_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE1_RX_WORK_STAT1_EO_PL                   , RULL(0x800388010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE1_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE1_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE1_RX_WORK_STAT2_EO_PL                   , RULL(0x800390010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE1_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE1_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE1_RX_WORK_STAT3_EO_PL                   , RULL(0x800398010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE1_RX_WORK_STAT4_O_PL                      , RULL(0x8003A00109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE1_RX_WORK_STAT4_O_PL                    , RULL(0x8003A00109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE1_RX_WORK_STAT4_O_PL                    , RULL(0x8003A0010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003801409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003801409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL                , RULL(0x8003301409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003301409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE20_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x800330140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL                 , RULL(0x8003201409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003201409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x800320140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL                 , RULL(0x8003281409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003281409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE20_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x800328140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE20_RX_WORK_CNTL1_O_PL                     , RULL(0x8003A81409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE20_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A81409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE20_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A8140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE20_RX_WORK_STAT1_EO_PL                    , RULL(0x8003881409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE20_RX_WORK_STAT1_EO_PL                  , RULL(0x8003881409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE20_RX_WORK_STAT1_EO_PL                  , RULL(0x800388140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE20_RX_WORK_STAT2_EO_PL                    , RULL(0x8003901409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE20_RX_WORK_STAT2_EO_PL                  , RULL(0x8003901409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE20_RX_WORK_STAT2_EO_PL                  , RULL(0x800390140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE20_RX_WORK_STAT3_EO_PL                    , RULL(0x8003981409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE20_RX_WORK_STAT3_EO_PL                  , RULL(0x8003981409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE20_RX_WORK_STAT3_EO_PL                  , RULL(0x800398140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE20_RX_WORK_STAT4_O_PL                     , RULL(0x8003A01409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE20_RX_WORK_STAT4_O_PL                   , RULL(0x8003A01409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE20_RX_WORK_STAT4_O_PL                   , RULL(0x8003A0140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003801509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003801509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL                , RULL(0x8003301509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003301509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE21_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x800330150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL                 , RULL(0x8003201509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003201509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x800320150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL                 , RULL(0x8003281509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003281509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE21_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x800328150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE21_RX_WORK_CNTL1_O_PL                     , RULL(0x8003A81509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE21_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A81509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE21_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A8150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE21_RX_WORK_STAT1_EO_PL                    , RULL(0x8003881509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE21_RX_WORK_STAT1_EO_PL                  , RULL(0x8003881509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE21_RX_WORK_STAT1_EO_PL                  , RULL(0x800388150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE21_RX_WORK_STAT2_EO_PL                    , RULL(0x8003901509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE21_RX_WORK_STAT2_EO_PL                  , RULL(0x8003901509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE21_RX_WORK_STAT2_EO_PL                  , RULL(0x800390150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE21_RX_WORK_STAT3_EO_PL                    , RULL(0x8003981509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE21_RX_WORK_STAT3_EO_PL                  , RULL(0x8003981509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE21_RX_WORK_STAT3_EO_PL                  , RULL(0x800398150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE21_RX_WORK_STAT4_O_PL                     , RULL(0x8003A01509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE21_RX_WORK_STAT4_O_PL                   , RULL(0x8003A01509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE21_RX_WORK_STAT4_O_PL                   , RULL(0x8003A0150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003801609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003801609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL                , RULL(0x8003301609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003301609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE22_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x800330160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL                 , RULL(0x8003201609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003201609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x800320160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL                 , RULL(0x8003281609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003281609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE22_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x800328160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE22_RX_WORK_CNTL1_O_PL                     , RULL(0x8003A81609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE22_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A81609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE22_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A8160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE22_RX_WORK_STAT1_EO_PL                    , RULL(0x8003881609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE22_RX_WORK_STAT1_EO_PL                  , RULL(0x8003881609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE22_RX_WORK_STAT1_EO_PL                  , RULL(0x800388160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE22_RX_WORK_STAT2_EO_PL                    , RULL(0x8003901609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE22_RX_WORK_STAT2_EO_PL                  , RULL(0x8003901609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE22_RX_WORK_STAT2_EO_PL                  , RULL(0x800390160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE22_RX_WORK_STAT3_EO_PL                    , RULL(0x8003981609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE22_RX_WORK_STAT3_EO_PL                  , RULL(0x8003981609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE22_RX_WORK_STAT3_EO_PL                  , RULL(0x800398160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE22_RX_WORK_STAT4_O_PL                     , RULL(0x8003A01609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE22_RX_WORK_STAT4_O_PL                   , RULL(0x8003A01609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE22_RX_WORK_STAT4_O_PL                   , RULL(0x8003A0160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003801709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003801709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL                , RULL(0x8003301709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x8003301709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE23_RX_GLBSM_PL_CNTL1X_O_PL              , RULL(0x800330170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL                 , RULL(0x8003201709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x8003201709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL               , RULL(0x800320170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL                 , RULL(0x8003281709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x8003281709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE23_RX_GLBSM_PL_STAT1_O_PL               , RULL(0x800328170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE23_RX_WORK_CNTL1_O_PL                     , RULL(0x8003A81709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE23_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A81709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE23_RX_WORK_CNTL1_O_PL                   , RULL(0x8003A8170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE23_RX_WORK_STAT1_EO_PL                    , RULL(0x8003881709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE23_RX_WORK_STAT1_EO_PL                  , RULL(0x8003881709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE23_RX_WORK_STAT1_EO_PL                  , RULL(0x800388170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE23_RX_WORK_STAT2_EO_PL                    , RULL(0x8003901709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE23_RX_WORK_STAT2_EO_PL                  , RULL(0x8003901709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE23_RX_WORK_STAT2_EO_PL                  , RULL(0x800390170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE23_RX_WORK_STAT3_EO_PL                    , RULL(0x8003981709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE23_RX_WORK_STAT3_EO_PL                  , RULL(0x8003981709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE23_RX_WORK_STAT3_EO_PL                  , RULL(0x800398170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE23_RX_WORK_STAT4_O_PL                     , RULL(0x8003A01709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE23_RX_WORK_STAT4_O_PL                   , RULL(0x8003A01709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE23_RX_WORK_STAT4_O_PL                   , RULL(0x8003A0170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL                 , RULL(0x8003300209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x8003300209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE2_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x800330020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL                  , RULL(0x8003200209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x8003200209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x800320020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL                  , RULL(0x8003280209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x8003280209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE2_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x800328020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE2_RX_WORK_CNTL1_O_PL                      , RULL(0x8003A80209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE2_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A80209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE2_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A8020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE2_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE2_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE2_RX_WORK_STAT1_EO_PL                   , RULL(0x800388020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE2_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE2_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE2_RX_WORK_STAT2_EO_PL                   , RULL(0x800390020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE2_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE2_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE2_RX_WORK_STAT3_EO_PL                   , RULL(0x800398020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE2_RX_WORK_STAT4_O_PL                      , RULL(0x8003A00209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE2_RX_WORK_STAT4_O_PL                    , RULL(0x8003A00209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE2_RX_WORK_STAT4_O_PL                    , RULL(0x8003A0020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL                 , RULL(0x8003300309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x8003300309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE3_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x800330030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL                  , RULL(0x8003200309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x8003200309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x800320030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL                  , RULL(0x8003280309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x8003280309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE3_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x800328030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE3_RX_WORK_CNTL1_O_PL                      , RULL(0x8003A80309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE3_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A80309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE3_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A8030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE3_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE3_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE3_RX_WORK_STAT1_EO_PL                   , RULL(0x800388030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE3_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE3_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE3_RX_WORK_STAT2_EO_PL                   , RULL(0x800390030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE3_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE3_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE3_RX_WORK_STAT3_EO_PL                   , RULL(0x800398030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE3_RX_WORK_STAT4_O_PL                      , RULL(0x8003A00309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE3_RX_WORK_STAT4_O_PL                    , RULL(0x8003A00309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE3_RX_WORK_STAT4_O_PL                    , RULL(0x8003A0030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL                 , RULL(0x8003300409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x8003300409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE4_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x800330040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL                  , RULL(0x8003200409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x8003200409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x800320040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL                  , RULL(0x8003280409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x8003280409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE4_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x800328040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE4_RX_WORK_CNTL1_O_PL                      , RULL(0x8003A80409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE4_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A80409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE4_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A8040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE4_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE4_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE4_RX_WORK_STAT1_EO_PL                   , RULL(0x800388040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE4_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE4_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE4_RX_WORK_STAT2_EO_PL                   , RULL(0x800390040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE4_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE4_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE4_RX_WORK_STAT3_EO_PL                   , RULL(0x800398040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE4_RX_WORK_STAT4_O_PL                      , RULL(0x8003A00409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE4_RX_WORK_STAT4_O_PL                    , RULL(0x8003A00409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE4_RX_WORK_STAT4_O_PL                    , RULL(0x8003A0040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL                 , RULL(0x8003300509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x8003300509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE5_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x800330050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL                  , RULL(0x8003200509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x8003200509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x800320050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL                  , RULL(0x8003280509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x8003280509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE5_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x800328050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE5_RX_WORK_CNTL1_O_PL                      , RULL(0x8003A80509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE5_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A80509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE5_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A8050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE5_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE5_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE5_RX_WORK_STAT1_EO_PL                   , RULL(0x800388050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE5_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE5_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE5_RX_WORK_STAT2_EO_PL                   , RULL(0x800390050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE5_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE5_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE5_RX_WORK_STAT3_EO_PL                   , RULL(0x800398050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE5_RX_WORK_STAT4_O_PL                      , RULL(0x8003A00509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE5_RX_WORK_STAT4_O_PL                    , RULL(0x8003A00509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE5_RX_WORK_STAT4_O_PL                    , RULL(0x8003A0050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL                 , RULL(0x8003300609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x8003300609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE6_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x800330060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL                  , RULL(0x8003200609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x8003200609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x800320060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL                  , RULL(0x8003280609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x8003280609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE6_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x800328060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE6_RX_WORK_CNTL1_O_PL                      , RULL(0x8003A80609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE6_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A80609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE6_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A8060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE6_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE6_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE6_RX_WORK_STAT1_EO_PL                   , RULL(0x800388060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE6_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE6_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE6_RX_WORK_STAT2_EO_PL                   , RULL(0x800390060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE6_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE6_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE6_RX_WORK_STAT3_EO_PL                   , RULL(0x800398060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE6_RX_WORK_STAT4_O_PL                      , RULL(0x8003A00609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE6_RX_WORK_STAT4_O_PL                    , RULL(0x8003A00609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE6_RX_WORK_STAT4_O_PL                    , RULL(0x8003A0060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL                 , RULL(0x8003300709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x8003300709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE7_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x800330070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL                  , RULL(0x8003200709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x8003200709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x800320070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL                  , RULL(0x8003280709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x8003280709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE7_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x800328070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE7_RX_WORK_CNTL1_O_PL                      , RULL(0x8003A80709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE7_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A80709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE7_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A8070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE7_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE7_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE7_RX_WORK_STAT1_EO_PL                   , RULL(0x800388070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE7_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE7_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE7_RX_WORK_STAT2_EO_PL                   , RULL(0x800390070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE7_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE7_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE7_RX_WORK_STAT3_EO_PL                   , RULL(0x800398070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE7_RX_WORK_STAT4_O_PL                      , RULL(0x8003A00709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE7_RX_WORK_STAT4_O_PL                    , RULL(0x8003A00709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE7_RX_WORK_STAT4_O_PL                    , RULL(0x8003A0070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL                 , RULL(0x8003300809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x8003300809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE8_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x800330080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL                  , RULL(0x8003200809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x8003200809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x800320080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL                  , RULL(0x8003280809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x8003280809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE8_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x800328080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE8_RX_WORK_CNTL1_O_PL                      , RULL(0x8003A80809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE8_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A80809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE8_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A8080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE8_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE8_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE8_RX_WORK_STAT1_EO_PL                   , RULL(0x800388080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE8_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE8_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE8_RX_WORK_STAT2_EO_PL                   , RULL(0x800390080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE8_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE8_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE8_RX_WORK_STAT3_EO_PL                   , RULL(0x800398080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE8_RX_WORK_STAT4_O_PL                      , RULL(0x8003A00809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE8_RX_WORK_STAT4_O_PL                    , RULL(0x8003A00809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE8_RX_WORK_STAT4_O_PL                    , RULL(0x8003A0080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL                 , RULL(0x8003300909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x8003300909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE9_RX_GLBSM_PL_CNTL1X_O_PL               , RULL(0x800330090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL                  , RULL(0x8003200909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x8003200909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL                , RULL(0x800320090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL                  , RULL(0x8003280909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x8003280909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE9_RX_GLBSM_PL_STAT1_O_PL                , RULL(0x800328090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE9_RX_WORK_CNTL1_O_PL                      , RULL(0x8003A80909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE9_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A80909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE9_RX_WORK_CNTL1_O_PL                    , RULL(0x8003A8090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE9_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE9_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE9_RX_WORK_STAT1_EO_PL                   , RULL(0x800388090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE9_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE9_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE9_RX_WORK_STAT2_EO_PL                   , RULL(0x800390090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE9_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE9_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE9_RX_WORK_STAT3_EO_PL                   , RULL(0x800398090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX0_SLICE9_RX_WORK_STAT4_O_PL                      , RULL(0x8003A00909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX0_SLICE9_RX_WORK_STAT4_O_PL                    , RULL(0x8003A00909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX0_SLICE9_RX_WORK_STAT4_O_PL                    , RULL(0x8003A0090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX_FIR_ERROR_INJECT_PB                             , RULL(0x800F980009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX_FIR_ERROR_INJECT_PB                           , RULL(0x800F980009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX_FIR_ERROR_INJECT_PB                           , RULL(0x800F98000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX_FIR_MASK_PB                                     , RULL(0x800F900009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX_FIR_MASK_PB                                   , RULL(0x800F900009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX_FIR_MASK_PB                                   , RULL(0x800F90000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX_FIR_PB                                          , RULL(0x800F880009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX_FIR_PB                                        , RULL(0x800F880009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX_FIR_PB                                        , RULL(0x800F88000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_RX_FIR_RESET_PB                                    , RULL(0x800F800009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_RX_FIR_RESET_PB                                  , RULL(0x800F800009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_RX_FIR_RESET_PB                                  , RULL(0x800F80000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_SCOM_MODE_PB                                       , RULL(0x09010C20), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_SCOM_MODE_PB                                     , RULL(0x09010C20), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+REG64( OBUS_3_SCOM_MODE_PB                                     , RULL(0x0C010C20), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_SPARE_MODE_PB                                      , RULL(0x800F340009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_SPARE_MODE_PB                                    , RULL(0x800F340009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_SPARE_MODE_PB                                    , RULL(0x800F34000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_ADDR_TRAP_REG                                , RULL(0x09010003), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_ADDR_TRAP_REG                              , RULL(0x09010003), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_ATOMIC_LOCK_MASK_LATCH_REG                   , RULL(0x09010007), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_ATOMIC_LOCK_MASK_LATCH_REG                 , RULL(0x09010007), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_DBG_INST1_COND_REG_1                         , RULL(0x090107C1), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_DBG_INST1_COND_REG_1                       , RULL(0x090107C1), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_DBG_INST1_COND_REG_2                         , RULL(0x090107C2), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_DBG_INST1_COND_REG_2                       , RULL(0x090107C2), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_DBG_INST1_COND_REG_3                         , RULL(0x090107C3), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_DBG_INST1_COND_REG_3                       , RULL(0x090107C3), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_DBG_INST2_COND_REG_1                         , RULL(0x090107C4), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_DBG_INST2_COND_REG_1                       , RULL(0x090107C4), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_DBG_INST2_COND_REG_2                         , RULL(0x090107C5), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_DBG_INST2_COND_REG_2                       , RULL(0x090107C5), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_DBG_INST2_COND_REG_3                         , RULL(0x090107C6), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_DBG_INST2_COND_REG_3                       , RULL(0x090107C6), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_DBG_MODE_REG                                 , RULL(0x090107C0), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_DBG_MODE_REG                               , RULL(0x090107C0), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_DBG_TRACE_MODE_REG_2                         , RULL(0x090107CF), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_DBG_TRACE_MODE_REG_2                       , RULL(0x090107CF), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_DBG_TRACE_REG_0                              , RULL(0x090107CD), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_DBG_TRACE_REG_0                            , RULL(0x090107CD), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_DBG_TRACE_REG_1                              , RULL(0x090107CE), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_DBG_TRACE_REG_1                            , RULL(0x090107CE), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_DEBUG_TRACE_CONTROL                          , RULL(0x090107D0), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_DEBUG_TRACE_CONTROL                        , RULL(0x090107D0), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_PSCOM_ERROR_MASK                             , RULL(0x09010002), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_PSCOM_ERROR_MASK                           , RULL(0x09010002), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_PSCOM_MODE_REG                               , RULL(0x09010000), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_PSCOM_MODE_REG                             , RULL(0x09010000), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG                       , RULL(0x09010001), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_PSCOM_STATUS_ERROR_REG                     , RULL(0x09010001), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_RING_FENCE_MASK_LATCH_REG                    , RULL(0x09010008), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_RING_FENCE_MASK_LATCH_REG                  , RULL(0x09010008), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_TRA0_TR0_TRACE_HI_DATA_REG                   , RULL(0x09010400), SH_UNT_OBUS     , SH_ACS_SCOM_RO   );
+REG64( OBUS_0_TCOB0_TRA0_TR0_TRACE_HI_DATA_REG                 , RULL(0x09010400), SH_UNT_OBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG                   , RULL(0x09010401), SH_UNT_OBUS     , SH_ACS_SCOM_RO   );
+REG64( OBUS_0_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG                 , RULL(0x09010401), SH_UNT_OBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG                 , RULL(0x09010402), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG               , RULL(0x09010402), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_0               , RULL(0x09010403), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_0             , RULL(0x09010403), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_1               , RULL(0x09010404), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_1             , RULL(0x09010404), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2               , RULL(0x09010405), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2             , RULL(0x09010405), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3               , RULL(0x09010406), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3             , RULL(0x09010406), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4               , RULL(0x09010407), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4             , RULL(0x09010407), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5               , RULL(0x09010408), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5             , RULL(0x09010408), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9               , RULL(0x09010409), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9             , RULL(0x09010409), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_WRITE_PROTECT_ENABLE_REG                     , RULL(0x09010005), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_WRITE_PROTECT_ENABLE_REG                   , RULL(0x09010005), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_WRITE_PROTECT_RINGS_REG                      , RULL(0x09010006), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_WRITE_PROTECT_RINGS_REG                    , RULL(0x09010006), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_TCOB0_XTRA_TRACE_MODE                              , RULL(0x090107D1), SH_UNT_OBUS     , SH_ACS_SCOM      );
+REG64( OBUS_0_TCOB0_XTRA_TRACE_MODE                            , RULL(0x090107D1), SH_UNT_OBUS_0   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_ADDR_TRAP_REG                              , RULL(0x0C010003), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_ATOMIC_LOCK_MASK_LATCH_REG                 , RULL(0x0C010007), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_DBG_INST1_COND_REG_1                       , RULL(0x0C0107C1), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_DBG_INST1_COND_REG_2                       , RULL(0x0C0107C2), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_DBG_INST1_COND_REG_3                       , RULL(0x0C0107C3), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_DBG_INST2_COND_REG_1                       , RULL(0x0C0107C4), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_DBG_INST2_COND_REG_2                       , RULL(0x0C0107C5), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_DBG_INST2_COND_REG_3                       , RULL(0x0C0107C6), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_DBG_MODE_REG                               , RULL(0x0C0107C0), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_DBG_TRACE_MODE_REG_2                       , RULL(0x0C0107CF), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_DBG_TRACE_REG_0                            , RULL(0x0C0107CD), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_DBG_TRACE_REG_1                            , RULL(0x0C0107CE), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_DEBUG_TRACE_CONTROL                        , RULL(0x0C0107D0), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_PSCOM_ERROR_MASK                           , RULL(0x0C010002), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_PSCOM_MODE_REG                             , RULL(0x0C010000), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_PSCOM_STATUS_ERROR_REG                     , RULL(0x0C010001), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_RING_FENCE_MASK_LATCH_REG                  , RULL(0x0C010008), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_TRA0_TR0_TRACE_HI_DATA_REG                 , RULL(0x0C010400), SH_UNT_OBUS_3   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_3_TCOB3_TRA0_TR0_TRACE_LO_DATA_REG                 , RULL(0x0C010401), SH_UNT_OBUS_3   , SH_ACS_SCOM_RO   );
+
+REG64( OBUS_3_TCOB3_TRA0_TR0_TRACE_TRCTRL_CONFIG               , RULL(0x0C010402), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_TRA0_TR0_TRACE_TRDATA_CONFIG_0             , RULL(0x0C010403), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_TRA0_TR0_TRACE_TRDATA_CONFIG_1             , RULL(0x0C010404), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_TRA0_TR0_TRACE_TRDATA_CONFIG_2             , RULL(0x0C010405), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_TRA0_TR0_TRACE_TRDATA_CONFIG_3             , RULL(0x0C010406), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_TRA0_TR0_TRACE_TRDATA_CONFIG_4             , RULL(0x0C010407), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_TRA0_TR0_TRACE_TRDATA_CONFIG_5             , RULL(0x0C010408), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_TRA0_TR0_TRACE_TRDATA_CONFIG_9             , RULL(0x0C010409), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_WRITE_PROTECT_ENABLE_REG                   , RULL(0x0C010005), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_WRITE_PROTECT_RINGS_REG                    , RULL(0x0C010006), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_3_TCOB3_XTRA_TRACE_MODE                            , RULL(0x0C0107D1), SH_UNT_OBUS_3   , SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL                   , RULL(0x8004140009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL                 , RULL(0x8004140009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE0_TX_CNTL2_O_PL                  , RULL(0x80044C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE0_TX_CNTL2_O_PL                , RULL(0x80044C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE0_TX_CNTL2_O_PL                , RULL(0x80044C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL                 , RULL(0x8004540009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL               , RULL(0x8004540009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL                 , RULL(0x80042C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE0_TX_FIR_PL                      , RULL(0x8004240009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE0_TX_FIR_PL                    , RULL(0x8004240009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE0_TX_FIR_PL                    , RULL(0x800424000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL                    , RULL(0x8004040009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE0_TX_MODE1_PL                  , RULL(0x8004040009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE0_TX_MODE1_PL                  , RULL(0x800404000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE2_PL                    , RULL(0x80040C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE0_TX_MODE2_PL                  , RULL(0x80040C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE0_TX_MODE2_PL                  , RULL(0x80040C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE0_TX_STAT1_PL                    , RULL(0x80041C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE0_TX_STAT1_PL                  , RULL(0x80041C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE0_TX_STAT1_PL                  , RULL(0x80041C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL                   , RULL(0x8004140109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL                 , RULL(0x8004140109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE1_TX_CNTL2_O_PL                  , RULL(0x80044C0109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE1_TX_CNTL2_O_PL                , RULL(0x80044C0109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE1_TX_CNTL2_O_PL                , RULL(0x80044C010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL                 , RULL(0x8004540109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL               , RULL(0x8004540109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL                 , RULL(0x80042C0109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C0109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE1_TX_FIR_PL                      , RULL(0x8004240109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE1_TX_FIR_PL                    , RULL(0x8004240109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE1_TX_FIR_PL                    , RULL(0x800424010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL                    , RULL(0x8004040109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE1_TX_MODE1_PL                  , RULL(0x8004040109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE1_TX_MODE1_PL                  , RULL(0x800404010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE2_PL                    , RULL(0x80040C0109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE1_TX_MODE2_PL                  , RULL(0x80040C0109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE1_TX_MODE2_PL                  , RULL(0x80040C010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE1_TX_STAT1_PL                    , RULL(0x80041C0109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE1_TX_STAT1_PL                  , RULL(0x80041C0109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE1_TX_STAT1_PL                  , RULL(0x80041C010C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL                   , RULL(0x8004140209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004140209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL                 , RULL(0x800414020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE2_TX_CNTL2_O_PL                  , RULL(0x80044C0209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE2_TX_CNTL2_O_PL                , RULL(0x80044C0209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE2_TX_CNTL2_O_PL                , RULL(0x80044C020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL                 , RULL(0x8004540209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004540209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL               , RULL(0x800454020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL                 , RULL(0x80042C0209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C0209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE2_TX_FIR_PL                      , RULL(0x8004240209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE2_TX_FIR_PL                    , RULL(0x8004240209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE2_TX_FIR_PL                    , RULL(0x800424020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL                    , RULL(0x8004040209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE2_TX_MODE1_PL                  , RULL(0x8004040209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE2_TX_MODE1_PL                  , RULL(0x800404020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE2_PL                    , RULL(0x80040C0209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE2_TX_MODE2_PL                  , RULL(0x80040C0209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE2_TX_MODE2_PL                  , RULL(0x80040C020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE2_TX_STAT1_PL                    , RULL(0x80041C0209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE2_TX_STAT1_PL                  , RULL(0x80041C0209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE2_TX_STAT1_PL                  , RULL(0x80041C020C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL                   , RULL(0x8004140309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004140309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL                 , RULL(0x800414030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE3_TX_CNTL2_O_PL                  , RULL(0x80044C0309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE3_TX_CNTL2_O_PL                , RULL(0x80044C0309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE3_TX_CNTL2_O_PL                , RULL(0x80044C030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL                 , RULL(0x8004540309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004540309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL               , RULL(0x800454030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL                 , RULL(0x80042C0309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C0309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE3_TX_FIR_PL                      , RULL(0x8004240309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE3_TX_FIR_PL                    , RULL(0x8004240309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE3_TX_FIR_PL                    , RULL(0x800424030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL                    , RULL(0x8004040309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE3_TX_MODE1_PL                  , RULL(0x8004040309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE3_TX_MODE1_PL                  , RULL(0x800404030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE2_PL                    , RULL(0x80040C0309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE3_TX_MODE2_PL                  , RULL(0x80040C0309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE3_TX_MODE2_PL                  , RULL(0x80040C030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS0_SLICE3_TX_STAT1_PL                    , RULL(0x80041C0309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS0_SLICE3_TX_STAT1_PL                  , RULL(0x80041C0309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS0_SLICE3_TX_STAT1_PL                  , RULL(0x80041C030C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL                   , RULL(0x8004140409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL                 , RULL(0x8004140409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE0_TX_CNTL2_O_PL                  , RULL(0x80044C0409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE0_TX_CNTL2_O_PL                , RULL(0x80044C0409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE0_TX_CNTL2_O_PL                , RULL(0x80044C040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL                 , RULL(0x8004540409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL               , RULL(0x8004540409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL                 , RULL(0x80042C0409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C0409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE0_TX_FIR_PL                      , RULL(0x8004240409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE0_TX_FIR_PL                    , RULL(0x8004240409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE0_TX_FIR_PL                    , RULL(0x800424040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL                    , RULL(0x8004040409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE0_TX_MODE1_PL                  , RULL(0x8004040409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE0_TX_MODE1_PL                  , RULL(0x800404040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE2_PL                    , RULL(0x80040C0409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE0_TX_MODE2_PL                  , RULL(0x80040C0409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE0_TX_MODE2_PL                  , RULL(0x80040C040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE0_TX_STAT1_PL                    , RULL(0x80041C0409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE0_TX_STAT1_PL                  , RULL(0x80041C0409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE0_TX_STAT1_PL                  , RULL(0x80041C040C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL                   , RULL(0x8004140509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL                 , RULL(0x8004140509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE1_TX_CNTL2_O_PL                  , RULL(0x80044C0509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE1_TX_CNTL2_O_PL                , RULL(0x80044C0509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE1_TX_CNTL2_O_PL                , RULL(0x80044C050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL                 , RULL(0x8004540509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL               , RULL(0x8004540509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL                 , RULL(0x80042C0509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C0509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE1_TX_FIR_PL                      , RULL(0x8004240509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE1_TX_FIR_PL                    , RULL(0x8004240509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE1_TX_FIR_PL                    , RULL(0x800424050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL                    , RULL(0x8004040509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE1_TX_MODE1_PL                  , RULL(0x8004040509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE1_TX_MODE1_PL                  , RULL(0x800404050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE2_PL                    , RULL(0x80040C0509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE1_TX_MODE2_PL                  , RULL(0x80040C0509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE1_TX_MODE2_PL                  , RULL(0x80040C050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE1_TX_STAT1_PL                    , RULL(0x80041C0509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE1_TX_STAT1_PL                  , RULL(0x80041C0509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE1_TX_STAT1_PL                  , RULL(0x80041C050C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL                   , RULL(0x8004140609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004140609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL                 , RULL(0x800414060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE2_TX_CNTL2_O_PL                  , RULL(0x80044C0609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE2_TX_CNTL2_O_PL                , RULL(0x80044C0609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE2_TX_CNTL2_O_PL                , RULL(0x80044C060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL                 , RULL(0x8004540609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004540609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL               , RULL(0x800454060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL                 , RULL(0x80042C0609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C0609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE2_TX_FIR_PL                      , RULL(0x8004240609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE2_TX_FIR_PL                    , RULL(0x8004240609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE2_TX_FIR_PL                    , RULL(0x800424060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL                    , RULL(0x8004040609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE2_TX_MODE1_PL                  , RULL(0x8004040609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE2_TX_MODE1_PL                  , RULL(0x800404060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE2_PL                    , RULL(0x80040C0609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE2_TX_MODE2_PL                  , RULL(0x80040C0609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE2_TX_MODE2_PL                  , RULL(0x80040C060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE2_TX_STAT1_PL                    , RULL(0x80041C0609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE2_TX_STAT1_PL                  , RULL(0x80041C0609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE2_TX_STAT1_PL                  , RULL(0x80041C060C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL                   , RULL(0x8004140709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004140709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL                 , RULL(0x800414070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE3_TX_CNTL2_O_PL                  , RULL(0x80044C0709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE3_TX_CNTL2_O_PL                , RULL(0x80044C0709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE3_TX_CNTL2_O_PL                , RULL(0x80044C070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL                 , RULL(0x8004540709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004540709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL               , RULL(0x800454070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL                 , RULL(0x80042C0709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C0709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE3_TX_FIR_PL                      , RULL(0x8004240709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE3_TX_FIR_PL                    , RULL(0x8004240709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE3_TX_FIR_PL                    , RULL(0x800424070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL                    , RULL(0x8004040709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE3_TX_MODE1_PL                  , RULL(0x8004040709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE3_TX_MODE1_PL                  , RULL(0x800404070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE2_PL                    , RULL(0x80040C0709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE3_TX_MODE2_PL                  , RULL(0x80040C0709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE3_TX_MODE2_PL                  , RULL(0x80040C070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS1_SLICE3_TX_STAT1_PL                    , RULL(0x80041C0709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS1_SLICE3_TX_STAT1_PL                  , RULL(0x80041C0709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS1_SLICE3_TX_STAT1_PL                  , RULL(0x80041C070C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL                   , RULL(0x8004140809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL                 , RULL(0x8004140809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE0_TX_CNTL2_O_PL                  , RULL(0x80044C0809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE0_TX_CNTL2_O_PL                , RULL(0x80044C0809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE0_TX_CNTL2_O_PL                , RULL(0x80044C080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL                 , RULL(0x8004540809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL               , RULL(0x8004540809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL                 , RULL(0x80042C0809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C0809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE0_TX_FIR_PL                      , RULL(0x8004240809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE0_TX_FIR_PL                    , RULL(0x8004240809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE0_TX_FIR_PL                    , RULL(0x800424080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL                    , RULL(0x8004040809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE0_TX_MODE1_PL                  , RULL(0x8004040809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE0_TX_MODE1_PL                  , RULL(0x800404080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE2_PL                    , RULL(0x80040C0809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE0_TX_MODE2_PL                  , RULL(0x80040C0809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE0_TX_MODE2_PL                  , RULL(0x80040C080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE0_TX_STAT1_PL                    , RULL(0x80041C0809010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE0_TX_STAT1_PL                  , RULL(0x80041C0809010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE0_TX_STAT1_PL                  , RULL(0x80041C080C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL                   , RULL(0x8004140909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL                 , RULL(0x8004140909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE1_TX_CNTL2_O_PL                  , RULL(0x80044C0909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE1_TX_CNTL2_O_PL                , RULL(0x80044C0909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE1_TX_CNTL2_O_PL                , RULL(0x80044C090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL                 , RULL(0x8004540909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL               , RULL(0x8004540909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL                 , RULL(0x80042C0909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C0909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE1_TX_FIR_PL                      , RULL(0x8004240909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE1_TX_FIR_PL                    , RULL(0x8004240909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE1_TX_FIR_PL                    , RULL(0x800424090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL                    , RULL(0x8004040909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE1_TX_MODE1_PL                  , RULL(0x8004040909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE1_TX_MODE1_PL                  , RULL(0x800404090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE2_PL                    , RULL(0x80040C0909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE1_TX_MODE2_PL                  , RULL(0x80040C0909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE1_TX_MODE2_PL                  , RULL(0x80040C090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE1_TX_STAT1_PL                    , RULL(0x80041C0909010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE1_TX_STAT1_PL                  , RULL(0x80041C0909010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE1_TX_STAT1_PL                  , RULL(0x80041C090C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL                   , RULL(0x8004140A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004140A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004140A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE2_TX_CNTL2_O_PL                  , RULL(0x80044C0A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE2_TX_CNTL2_O_PL                , RULL(0x80044C0A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE2_TX_CNTL2_O_PL                , RULL(0x80044C0A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL                 , RULL(0x8004540A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004540A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004540A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL                 , RULL(0x80042C0A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C0A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C0A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE2_TX_FIR_PL                      , RULL(0x8004240A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE2_TX_FIR_PL                    , RULL(0x8004240A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE2_TX_FIR_PL                    , RULL(0x8004240A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL                    , RULL(0x8004040A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE2_TX_MODE1_PL                  , RULL(0x8004040A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE2_TX_MODE1_PL                  , RULL(0x8004040A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE2_PL                    , RULL(0x80040C0A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE2_TX_MODE2_PL                  , RULL(0x80040C0A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE2_TX_MODE2_PL                  , RULL(0x80040C0A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE2_TX_STAT1_PL                    , RULL(0x80041C0A09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE2_TX_STAT1_PL                  , RULL(0x80041C0A09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE2_TX_STAT1_PL                  , RULL(0x80041C0A0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL                   , RULL(0x8004140B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004140B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004140B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE3_TX_CNTL2_O_PL                  , RULL(0x80044C0B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE3_TX_CNTL2_O_PL                , RULL(0x80044C0B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE3_TX_CNTL2_O_PL                , RULL(0x80044C0B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL                 , RULL(0x8004540B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004540B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004540B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL                 , RULL(0x80042C0B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C0B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C0B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE3_TX_FIR_PL                      , RULL(0x8004240B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE3_TX_FIR_PL                    , RULL(0x8004240B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE3_TX_FIR_PL                    , RULL(0x8004240B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL                    , RULL(0x8004040B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE3_TX_MODE1_PL                  , RULL(0x8004040B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE3_TX_MODE1_PL                  , RULL(0x8004040B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE2_PL                    , RULL(0x80040C0B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE3_TX_MODE2_PL                  , RULL(0x80040C0B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE3_TX_MODE2_PL                  , RULL(0x80040C0B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS2_SLICE3_TX_STAT1_PL                    , RULL(0x80041C0B09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS2_SLICE3_TX_STAT1_PL                  , RULL(0x80041C0B09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS2_SLICE3_TX_STAT1_PL                  , RULL(0x80041C0B0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL                   , RULL(0x8004140C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL                 , RULL(0x8004140C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL                 , RULL(0x8004140C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE0_TX_CNTL2_O_PL                  , RULL(0x80044C0C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE0_TX_CNTL2_O_PL                , RULL(0x80044C0C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE0_TX_CNTL2_O_PL                , RULL(0x80044C0C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL                 , RULL(0x8004540C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL               , RULL(0x8004540C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL               , RULL(0x8004540C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL                 , RULL(0x80042C0C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C0C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C0C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE0_TX_FIR_PL                      , RULL(0x8004240C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE0_TX_FIR_PL                    , RULL(0x8004240C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE0_TX_FIR_PL                    , RULL(0x8004240C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL                    , RULL(0x8004040C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE0_TX_MODE1_PL                  , RULL(0x8004040C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE0_TX_MODE1_PL                  , RULL(0x8004040C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE2_PL                    , RULL(0x80040C0C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE0_TX_MODE2_PL                  , RULL(0x80040C0C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE0_TX_MODE2_PL                  , RULL(0x80040C0C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE0_TX_STAT1_PL                    , RULL(0x80041C0C09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE0_TX_STAT1_PL                  , RULL(0x80041C0C09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE0_TX_STAT1_PL                  , RULL(0x80041C0C0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL                   , RULL(0x8004140D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL                 , RULL(0x8004140D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL                 , RULL(0x8004140D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE1_TX_CNTL2_O_PL                  , RULL(0x80044C0D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE1_TX_CNTL2_O_PL                , RULL(0x80044C0D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE1_TX_CNTL2_O_PL                , RULL(0x80044C0D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL                 , RULL(0x8004540D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL               , RULL(0x8004540D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL               , RULL(0x8004540D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL                 , RULL(0x80042C0D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C0D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C0D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE1_TX_FIR_PL                      , RULL(0x8004240D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE1_TX_FIR_PL                    , RULL(0x8004240D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE1_TX_FIR_PL                    , RULL(0x8004240D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL                    , RULL(0x8004040D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE1_TX_MODE1_PL                  , RULL(0x8004040D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE1_TX_MODE1_PL                  , RULL(0x8004040D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE2_PL                    , RULL(0x80040C0D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE1_TX_MODE2_PL                  , RULL(0x80040C0D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE1_TX_MODE2_PL                  , RULL(0x80040C0D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE1_TX_STAT1_PL                    , RULL(0x80041C0D09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE1_TX_STAT1_PL                  , RULL(0x80041C0D09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE1_TX_STAT1_PL                  , RULL(0x80041C0D0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL                   , RULL(0x8004140E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004140E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004140E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE2_TX_CNTL2_O_PL                  , RULL(0x80044C0E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE2_TX_CNTL2_O_PL                , RULL(0x80044C0E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE2_TX_CNTL2_O_PL                , RULL(0x80044C0E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL                 , RULL(0x8004540E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004540E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004540E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL                 , RULL(0x80042C0E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C0E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C0E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE2_TX_FIR_PL                      , RULL(0x8004240E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE2_TX_FIR_PL                    , RULL(0x8004240E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE2_TX_FIR_PL                    , RULL(0x8004240E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL                    , RULL(0x8004040E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE2_TX_MODE1_PL                  , RULL(0x8004040E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE2_TX_MODE1_PL                  , RULL(0x8004040E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE2_PL                    , RULL(0x80040C0E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE2_TX_MODE2_PL                  , RULL(0x80040C0E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE2_TX_MODE2_PL                  , RULL(0x80040C0E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE2_TX_STAT1_PL                    , RULL(0x80041C0E09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE2_TX_STAT1_PL                  , RULL(0x80041C0E09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE2_TX_STAT1_PL                  , RULL(0x80041C0E0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL                   , RULL(0x8004140F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004140F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004140F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE3_TX_CNTL2_O_PL                  , RULL(0x80044C0F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE3_TX_CNTL2_O_PL                , RULL(0x80044C0F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE3_TX_CNTL2_O_PL                , RULL(0x80044C0F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL                 , RULL(0x8004540F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004540F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004540F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL                 , RULL(0x80042C0F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C0F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C0F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE3_TX_FIR_PL                      , RULL(0x8004240F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE3_TX_FIR_PL                    , RULL(0x8004240F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE3_TX_FIR_PL                    , RULL(0x8004240F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL                    , RULL(0x8004040F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE3_TX_MODE1_PL                  , RULL(0x8004040F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE3_TX_MODE1_PL                  , RULL(0x8004040F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE2_PL                    , RULL(0x80040C0F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE3_TX_MODE2_PL                  , RULL(0x80040C0F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE3_TX_MODE2_PL                  , RULL(0x80040C0F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS3_SLICE3_TX_STAT1_PL                    , RULL(0x80041C0F09010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS3_SLICE3_TX_STAT1_PL                  , RULL(0x80041C0F09010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS3_SLICE3_TX_STAT1_PL                  , RULL(0x80041C0F0C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL                   , RULL(0x8004141009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL                 , RULL(0x8004141009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE0_TX_CNTL2_O_PL                  , RULL(0x80044C1009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE0_TX_CNTL2_O_PL                , RULL(0x80044C1009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE0_TX_CNTL2_O_PL                , RULL(0x80044C100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE0_TX_CNTL3_EO_PL                 , RULL(0x8004541009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE0_TX_CNTL3_EO_PL               , RULL(0x8004541009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE0_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004341009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004341009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE0_TX_FIR_MASK_PL                 , RULL(0x80042C1009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C1009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE0_TX_FIR_PL                      , RULL(0x8004241009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE0_TX_FIR_PL                    , RULL(0x8004241009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE0_TX_FIR_PL                    , RULL(0x800424100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL                    , RULL(0x8004041009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE0_TX_MODE1_PL                  , RULL(0x8004041009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE0_TX_MODE1_PL                  , RULL(0x800404100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE2_PL                    , RULL(0x80040C1009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE0_TX_MODE2_PL                  , RULL(0x80040C1009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE0_TX_MODE2_PL                  , RULL(0x80040C100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE0_TX_STAT1_PL                    , RULL(0x80041C1009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE0_TX_STAT1_PL                  , RULL(0x80041C1009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE0_TX_STAT1_PL                  , RULL(0x80041C100C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL                   , RULL(0x8004141109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL                 , RULL(0x8004141109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE1_TX_CNTL2_O_PL                  , RULL(0x80044C1109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE1_TX_CNTL2_O_PL                , RULL(0x80044C1109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE1_TX_CNTL2_O_PL                , RULL(0x80044C110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE1_TX_CNTL3_EO_PL                 , RULL(0x8004541109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE1_TX_CNTL3_EO_PL               , RULL(0x8004541109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE1_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004341109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004341109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE1_TX_FIR_MASK_PL                 , RULL(0x80042C1109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C1109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE1_TX_FIR_PL                      , RULL(0x8004241109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE1_TX_FIR_PL                    , RULL(0x8004241109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE1_TX_FIR_PL                    , RULL(0x800424110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL                    , RULL(0x8004041109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE1_TX_MODE1_PL                  , RULL(0x8004041109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE1_TX_MODE1_PL                  , RULL(0x800404110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE2_PL                    , RULL(0x80040C1109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE1_TX_MODE2_PL                  , RULL(0x80040C1109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE1_TX_MODE2_PL                  , RULL(0x80040C110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE1_TX_STAT1_PL                    , RULL(0x80041C1109010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE1_TX_STAT1_PL                  , RULL(0x80041C1109010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE1_TX_STAT1_PL                  , RULL(0x80041C110C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL                   , RULL(0x8004141209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004141209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE2_TX_CNTL1G_PL                 , RULL(0x800414120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE2_TX_CNTL2_O_PL                  , RULL(0x80044C1209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE2_TX_CNTL2_O_PL                , RULL(0x80044C1209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE2_TX_CNTL2_O_PL                , RULL(0x80044C120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE2_TX_CNTL3_EO_PL                 , RULL(0x8004541209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004541209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE2_TX_CNTL3_EO_PL               , RULL(0x800454120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE2_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004341209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004341209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE2_TX_FIR_MASK_PL                 , RULL(0x80042C1209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C1209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE2_TX_FIR_PL                      , RULL(0x8004241209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE2_TX_FIR_PL                    , RULL(0x8004241209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE2_TX_FIR_PL                    , RULL(0x800424120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL                    , RULL(0x8004041209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE2_TX_MODE1_PL                  , RULL(0x8004041209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE2_TX_MODE1_PL                  , RULL(0x800404120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE2_PL                    , RULL(0x80040C1209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE2_TX_MODE2_PL                  , RULL(0x80040C1209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE2_TX_MODE2_PL                  , RULL(0x80040C120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE2_TX_STAT1_PL                    , RULL(0x80041C1209010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE2_TX_STAT1_PL                  , RULL(0x80041C1209010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE2_TX_STAT1_PL                  , RULL(0x80041C120C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL                   , RULL(0x8004141309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004141309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE3_TX_CNTL1G_PL                 , RULL(0x800414130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE3_TX_CNTL2_O_PL                  , RULL(0x80044C1309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE3_TX_CNTL2_O_PL                , RULL(0x80044C1309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE3_TX_CNTL2_O_PL                , RULL(0x80044C130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE3_TX_CNTL3_EO_PL                 , RULL(0x8004541309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004541309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE3_TX_CNTL3_EO_PL               , RULL(0x800454130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE3_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004341309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004341309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE3_TX_FIR_MASK_PL                 , RULL(0x80042C1309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C1309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE3_TX_FIR_PL                      , RULL(0x8004241309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE3_TX_FIR_PL                    , RULL(0x8004241309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE3_TX_FIR_PL                    , RULL(0x800424130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL                    , RULL(0x8004041309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE3_TX_MODE1_PL                  , RULL(0x8004041309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE3_TX_MODE1_PL                  , RULL(0x800404130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE2_PL                    , RULL(0x80040C1309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE3_TX_MODE2_PL                  , RULL(0x80040C1309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE3_TX_MODE2_PL                  , RULL(0x80040C130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS4_SLICE3_TX_STAT1_PL                    , RULL(0x80041C1309010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS4_SLICE3_TX_STAT1_PL                  , RULL(0x80041C1309010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS4_SLICE3_TX_STAT1_PL                  , RULL(0x80041C130C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL                   , RULL(0x8004141409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL                 , RULL(0x8004141409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE0_TX_CNTL2_O_PL                  , RULL(0x80044C1409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE0_TX_CNTL2_O_PL                , RULL(0x80044C1409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE0_TX_CNTL2_O_PL                , RULL(0x80044C140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE0_TX_CNTL3_EO_PL                 , RULL(0x8004541409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE0_TX_CNTL3_EO_PL               , RULL(0x8004541409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE0_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004341409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004341409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE0_TX_FIR_MASK_PL                 , RULL(0x80042C1409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C1409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE0_TX_FIR_PL                      , RULL(0x8004241409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE0_TX_FIR_PL                    , RULL(0x8004241409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE0_TX_FIR_PL                    , RULL(0x800424140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL                    , RULL(0x8004041409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE0_TX_MODE1_PL                  , RULL(0x8004041409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE0_TX_MODE1_PL                  , RULL(0x800404140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE2_PL                    , RULL(0x80040C1409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE0_TX_MODE2_PL                  , RULL(0x80040C1409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE0_TX_MODE2_PL                  , RULL(0x80040C140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE0_TX_STAT1_PL                    , RULL(0x80041C1409010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE0_TX_STAT1_PL                  , RULL(0x80041C1409010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE0_TX_STAT1_PL                  , RULL(0x80041C140C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL                   , RULL(0x8004141509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL                 , RULL(0x8004141509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE1_TX_CNTL2_O_PL                  , RULL(0x80044C1509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE1_TX_CNTL2_O_PL                , RULL(0x80044C1509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE1_TX_CNTL2_O_PL                , RULL(0x80044C150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE1_TX_CNTL3_EO_PL                 , RULL(0x8004541509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE1_TX_CNTL3_EO_PL               , RULL(0x8004541509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE1_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004341509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004341509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE1_TX_FIR_MASK_PL                 , RULL(0x80042C1509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C1509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE1_TX_FIR_PL                      , RULL(0x8004241509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE1_TX_FIR_PL                    , RULL(0x8004241509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE1_TX_FIR_PL                    , RULL(0x800424150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL                    , RULL(0x8004041509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE1_TX_MODE1_PL                  , RULL(0x8004041509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE1_TX_MODE1_PL                  , RULL(0x800404150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE2_PL                    , RULL(0x80040C1509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE1_TX_MODE2_PL                  , RULL(0x80040C1509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE1_TX_MODE2_PL                  , RULL(0x80040C150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE1_TX_STAT1_PL                    , RULL(0x80041C1509010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE1_TX_STAT1_PL                  , RULL(0x80041C1509010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE1_TX_STAT1_PL                  , RULL(0x80041C150C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL                   , RULL(0x8004141609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004141609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE2_TX_CNTL1G_PL                 , RULL(0x800414160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE2_TX_CNTL2_O_PL                  , RULL(0x80044C1609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE2_TX_CNTL2_O_PL                , RULL(0x80044C1609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE2_TX_CNTL2_O_PL                , RULL(0x80044C160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE2_TX_CNTL3_EO_PL                 , RULL(0x8004541609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004541609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE2_TX_CNTL3_EO_PL               , RULL(0x800454160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE2_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004341609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004341609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE2_TX_FIR_MASK_PL                 , RULL(0x80042C1609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C1609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE2_TX_FIR_PL                      , RULL(0x8004241609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE2_TX_FIR_PL                    , RULL(0x8004241609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE2_TX_FIR_PL                    , RULL(0x800424160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL                    , RULL(0x8004041609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE2_TX_MODE1_PL                  , RULL(0x8004041609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE2_TX_MODE1_PL                  , RULL(0x800404160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE2_PL                    , RULL(0x80040C1609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE2_TX_MODE2_PL                  , RULL(0x80040C1609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE2_TX_MODE2_PL                  , RULL(0x80040C160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE2_TX_STAT1_PL                    , RULL(0x80041C1609010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE2_TX_STAT1_PL                  , RULL(0x80041C1609010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE2_TX_STAT1_PL                  , RULL(0x80041C160C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL                   , RULL(0x8004141709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004141709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE3_TX_CNTL1G_PL                 , RULL(0x800414170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE3_TX_CNTL2_O_PL                  , RULL(0x80044C1709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE3_TX_CNTL2_O_PL                , RULL(0x80044C1709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE3_TX_CNTL2_O_PL                , RULL(0x80044C170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE3_TX_CNTL3_EO_PL                 , RULL(0x8004541709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004541709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE3_TX_CNTL3_EO_PL               , RULL(0x800454170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE3_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004341709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004341709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE3_TX_FIR_MASK_PL                 , RULL(0x80042C1709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C1709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE3_TX_FIR_PL                      , RULL(0x8004241709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE3_TX_FIR_PL                    , RULL(0x8004241709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE3_TX_FIR_PL                    , RULL(0x800424170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL                    , RULL(0x8004041709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE3_TX_MODE1_PL                  , RULL(0x8004041709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE3_TX_MODE1_PL                  , RULL(0x800404170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE2_PL                    , RULL(0x80040C1709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE3_TX_MODE2_PL                  , RULL(0x80040C1709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE3_TX_MODE2_PL                  , RULL(0x80040C170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TXPACKS5_SLICE3_TX_STAT1_PL                    , RULL(0x80041C1709010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TXPACKS5_SLICE3_TX_STAT1_PL                  , RULL(0x80041C1709010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TXPACKS5_SLICE3_TX_STAT1_PL                  , RULL(0x80041C170C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTLSM_CNTL1_EO_PG                           , RULL(0x800D340009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTLSM_CNTL1_EO_PG                         , RULL(0x800D340009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTLSM_CNTL1_EO_PG                         , RULL(0x800D34000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTLSM_CNTL1_O_PG                            , RULL(0x800D840009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTLSM_CNTL1_O_PG                          , RULL(0x800D840009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTLSM_CNTL1_O_PG                          , RULL(0x800D84000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTLSM_CNTL2_EO_PG                           , RULL(0x800D3C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTLSM_CNTL2_EO_PG                         , RULL(0x800D3C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTLSM_CNTL2_EO_PG                         , RULL(0x800D3C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTLSM_CNTL2_O_PG                            , RULL(0x800D8C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTLSM_CNTL2_O_PG                          , RULL(0x800D8C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTLSM_CNTL2_O_PG                          , RULL(0x800D8C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTLSM_CNTL3_EO_PG                           , RULL(0x800D440009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTLSM_CNTL3_EO_PG                         , RULL(0x800D440009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTLSM_CNTL3_EO_PG                         , RULL(0x800D44000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTLSM_CNTL4_EO_PG                           , RULL(0x800D4C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTLSM_CNTL4_EO_PG                         , RULL(0x800D4C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTLSM_CNTL4_EO_PG                         , RULL(0x800D4C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTLSM_CNTL5_EO_PG                           , RULL(0x800D540009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTLSM_CNTL5_EO_PG                         , RULL(0x800D540009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTLSM_CNTL5_EO_PG                         , RULL(0x800D54000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTLSM_CNTL6_EO_PG                           , RULL(0x800D5C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTLSM_CNTL6_EO_PG                         , RULL(0x800D5C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTLSM_CNTL6_EO_PG                         , RULL(0x800D5C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTLSM_CNTL7_EO_PG                           , RULL(0x800D640009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTLSM_CNTL7_EO_PG                         , RULL(0x800D640009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTLSM_CNTL7_EO_PG                         , RULL(0x800D64000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTLSM_MODE1_EO_PG                           , RULL(0x800D2C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTLSM_MODE1_EO_PG                         , RULL(0x800D2C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTLSM_MODE1_EO_PG                         , RULL(0x800D2C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG                         , RULL(0x800D240009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTLSM_SPARE_MODE_PG                       , RULL(0x800D240009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTLSM_SPARE_MODE_PG                       , RULL(0x800D24000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTLSM_STAT1_EO_PG                           , RULL(0x800D6C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTLSM_STAT1_EO_PG                         , RULL(0x800D6C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTLSM_STAT1_EO_PG                         , RULL(0x800D6C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTL_CNTL10_EO_PG                            , RULL(0x800CDC0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTL_CNTL10_EO_PG                          , RULL(0x800CDC0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTL_CNTL10_EO_PG                          , RULL(0x800CDC000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTL_CNTL2_EO_PG                             , RULL(0x800C2C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTL_CNTL2_EO_PG                           , RULL(0x800C2C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTL_CNTL2_EO_PG                           , RULL(0x800C2C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTL_CNTL3_EO_PG                             , RULL(0x800C340009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTL_CNTL3_EO_PG                           , RULL(0x800C340009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTL_CNTL3_EO_PG                           , RULL(0x800C34000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTL_CNTL8_EO_PG                             , RULL(0x800CCC0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTL_CNTL8_EO_PG                           , RULL(0x800CCC0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTL_CNTL8_EO_PG                           , RULL(0x800CCC000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTL_CNTL9_EO_PG                             , RULL(0x800CD40009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTL_CNTL9_EO_PG                           , RULL(0x800CD40009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTL_CNTL9_EO_PG                           , RULL(0x800CD4000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTL_CNTLG1_EO_PG                            , RULL(0x800C240009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTL_CNTLG1_EO_PG                          , RULL(0x800C240009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTL_CNTLG1_EO_PG                          , RULL(0x800C24000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_CTL_MODE1_EO_PG                             , RULL(0x800C140009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_CTL_MODE1_EO_PG                           , RULL(0x800C140009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_CTL_MODE1_EO_PG                           , RULL(0x800C14000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_FIR_ERROR_INJECT_PG                         , RULL(0x800D1C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_FIR_ERROR_INJECT_PG                       , RULL(0x800D1C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_FIR_ERROR_INJECT_PG                       , RULL(0x800D1C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_FIR_MASK_PG                                 , RULL(0x800D0C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_FIR_MASK_PG                               , RULL(0x800D0C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_FIR_MASK_PG                               , RULL(0x800D0C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_FIR_PG                                      , RULL(0x800D040009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_FIR_PG                                    , RULL(0x800D040009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_FIR_PG                                    , RULL(0x800D04000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_FIR_RESET_PG                                , RULL(0x800D140009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_FIR_RESET_PG                              , RULL(0x800D140009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_FIR_RESET_PG                              , RULL(0x800D14000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_ID1_PG                                      , RULL(0x800C0C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_ID1_PG                                    , RULL(0x800C0C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_ID1_PG                                    , RULL(0x800C0C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX0_TX_SPARE_MODE_PG                               , RULL(0x800C040009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX0_TX_SPARE_MODE_PG                             , RULL(0x800C040009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX0_TX_SPARE_MODE_PG                             , RULL(0x800C04000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX_IMPCAL2_PB                                      , RULL(0x800F3C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX_IMPCAL2_PB                                    , RULL(0x800F3C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX_IMPCAL2_PB                                    , RULL(0x800F3C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX_IMPCAL_NVAL_PB                                  , RULL(0x800F0C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX_IMPCAL_NVAL_PB                                , RULL(0x800F0C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX_IMPCAL_NVAL_PB                                , RULL(0x800F0C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX_IMPCAL_PB                                       , RULL(0x800F040009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX_IMPCAL_PB                                     , RULL(0x800F040009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX_IMPCAL_PB                                     , RULL(0x800F04000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX_IMPCAL_PVAL_PB                                  , RULL(0x800F140009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX_IMPCAL_PVAL_PB                                , RULL(0x800F140009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX_IMPCAL_PVAL_PB                                , RULL(0x800F14000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX_IMPCAL_P_4X_PB                                  , RULL(0x800F1C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX_IMPCAL_P_4X_PB                                , RULL(0x800F1C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX_IMPCAL_P_4X_PB                                , RULL(0x800F1C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX_IMPCAL_SWO1_PB                                  , RULL(0x800F240009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX_IMPCAL_SWO1_PB                                , RULL(0x800F240009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX_IMPCAL_SWO1_PB                                , RULL(0x800F24000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+
+REG64( OBUS_TX_IMPCAL_SWO2_PB                                  , RULL(0x800F2C0009010C3F), SH_UNT_OBUS     ,
+       SH_ACS_SCOM      );
+REG64( OBUS_0_TX_IMPCAL_SWO2_PB                                , RULL(0x800F2C0009010C3F), SH_UNT_OBUS_0   ,
+       SH_ACS_SCOM      );
+REG64( OBUS_3_TX_IMPCAL_SWO2_PB                                , RULL(0x800F2C000C010C3F), SH_UNT_OBUS_3   ,
+       SH_ACS_SCOM      );
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H b/src/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H
new file mode 100644
index 00000000..dd9766f0
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file obus_scom_addresses_fixes.H
+/// @brief The *scom_addresses.H files are  generated form figtree, but
+///        the figree can be wrong.  This file is included at the end
+///        of scom_addresses.H and allows incorrect constants to be
+///        fixed manually.
+///
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SAO
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __P9_OBUS_SCOM_ADDRESSES_FIXES_H
+#define __P9_OBUS_SCOM_ADDRESSES_FIXES_H
+
+//Example,
+//Copy the whole line from the *scom_addresses.H file.  Then add
+//FIX in front of REG, and add another paramter that is the new
+//corrected value.
+//FIXREG64( PU_ALTD_ADDR_REG,
+//          RULL(0x05022800), SH_UNT, SH_ACS_SCOM,
+//          RULL(0x00090000)
+//        );
+
+static const uint64_t SH_UNT_OBUS_1 = 514;
+static const uint64_t SH_UNT_OBUS_2 = 515;
+
+REG64( OBUS_1_LL1_IOOL_CONTROL,
+       RULL(0x0A01080B), SH_UNT_OBUS_1, SH_ACS_SCOM );
+REG64( OBUS_1_LL1_LL1_LL1_PB_IOOL_FIR_REG,
+       RULL(0x0A010800), SH_UNT_OBUS_2, SH_ACS_SCOM );
+
+REG64( OBUS_2_LL2_IOOL_CONTROL,
+       RULL(0x0B01080B), SH_UNT_OBUS_2, SH_ACS_SCOM );
+REG64( OBUS_2_LL2_LL2_LL2_PB_IOOL_FIR_REG,
+       RULL(0x0B010800), SH_UNT_OBUS_2, SH_ACS_SCOM );
+
+#endif
diff --git a/src/import/chips/p9/common/include/p9_obus_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_obus_scom_addresses_fld.H
new file mode 100644
index 00000000..722b1970
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_obus_scom_addresses_fld.H
@@ -0,0 +1,14675 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_obus_scom_addresses_fld.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_obus_scom_addresses_fld.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#include <p9_const_common.H>
+
+#ifndef __P9_OBUS_SCOM_ADDRESSES_FLD_H
+#define __P9_OBUS_SCOM_ADDRESSES_FLD_H
+
+
+#include <p9_scom_template_consts.H>
+#include <p9_obus_scom_addresses_fld_fixes.H>
+
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_LINK_PAIR                          , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK_PAIR  );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_DISABLE_SL_ECC                     , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_SL_ECC );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_CRC_LANE_ID                        , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CRC_LANE_ID );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_EDPL_LANE_ID                       , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_EDPL_LANE_ID );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_SL_UE_CRC_ERR                      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SL_UE_CRC_ERR );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_REPORT_SL_CHKBIT_ERR               , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPORT_SL_CHKBIT_ERR );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_BW_SAMPLE_SIZE                     , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BW_SAMPLE_SIZE );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_BW_WINDOW_SIZE                     , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BW_WINDOW_SIZE );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_UNUSED1                            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1    );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_UNUSED1_LEN                        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1_LEN );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_PACKET_DELAY_LIMIT                 , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PACKET_DELAY_LIMIT );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_PACKET_DELAY_LIMIT_LEN             , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PACKET_DELAY_LIMIT_LEN );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_TDM_DELAY                          , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDM_DELAY  );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_TDM_DELAY_LEN                      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDM_DELAY_LEN );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_AUTO_TDM_TX                        , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_TX );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_AUTO_TDM_RX                        , 21  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_RX );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_AUTO_TDM_AND_NOT_OR                , 22  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_AND_NOT_OR );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_UNUSED2                            , 23  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2    );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_AUTO_TDM_BW_DIFF                   , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_BW_DIFF );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_AUTO_TDM_BW_DIFF_LEN               , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_BW_DIFF_LEN );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_AUTO_TDM_ERROR_RATE                , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_ERROR_RATE );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_AUTO_TDM_ERROR_RATE_LEN            , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_ERROR_RATE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_UNUSED3                            , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED3    );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_UNUSED3_LEN                        , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED3_LEN );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_TIMEOUT                            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT    );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_TIMEOUT_LEN                        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_LEN );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_TIMER_1US                          , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_1US  );
+REG64_FLD( OBUS_LL0_IOOL_CONFIG_TIMER_1US_LEN                      , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_1US_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_PHY_TRAINING                , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_PHY_TRAINING );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_STARTUP                     , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_STARTUP );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_HOLD_PATT_A                 , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_HOLD_PATT_A );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_HOLD_PATT_B                 , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_HOLD_PATT_B );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_RUN_LANE_DISABLE            , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_RUN_LANE_DISABLE );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_RUN_LANE_OVERRIDE           , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_RUN_LANE_OVERRIDE );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_IGNORE_PHY                  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_IGNORE_PHY );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_IGNORE_FENCE                , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_IGNORE_FENCE );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_ERR_INJ_COMMAND             , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ERR_INJ_COMMAND );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_ERR_INJ_COMMAND_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ERR_INJ_COMMAND_LEN );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES       , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ERR_INJ_COMMAND_LANES );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES_LEN   , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ERR_INJ_COMMAND_LANES_LEN );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_UNUSED0                           , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED0    );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_UNUSED0_LEN                       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED0_LEN );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_COMMAND                     , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_COMMAND );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK0_COMMAND_LEN                 , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_COMMAND_LEN );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_PHY_TRAINING                , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_PHY_TRAINING );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_STARTUP                     , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_STARTUP );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_HOLD_PATT_A                 , 34  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_HOLD_PATT_A );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_HOLD_PATT_B                 , 35  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_HOLD_PATT_B );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_RUN_LANE_DISABLE            , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_RUN_LANE_DISABLE );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_RUN_LANE_OVERRIDE           , 37  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_RUN_LANE_OVERRIDE );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_IGNORE_PHY                  , 38  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_IGNORE_PHY );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_IGNORE_FENCE                , 39  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_IGNORE_FENCE );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_ERR_INJ_COMMAND             , 40  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ERR_INJ_COMMAND );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_ERR_INJ_COMMAND_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ERR_INJ_COMMAND_LEN );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES       , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ERR_INJ_COMMAND_LANES );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES_LEN   , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ERR_INJ_COMMAND_LANES_LEN );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_UNUSED1                           , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1    );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_UNUSED1_LEN                       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1_LEN );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_COMMAND                     , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_COMMAND );
+REG64_FLD( OBUS_LL0_IOOL_CONTROL_LINK1_COMMAND_LEN                 , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_COMMAND_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_CURRENT_STATE            , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_CURRENT_STATE );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_CURRENT_STATE_LEN        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_CURRENT_STATE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_PRIOR_STATE              , 12  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_PRIOR_STATE );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_PRIOR_STATE_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_PRIOR_STATE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_OPTICS_RST_B             , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_OPTICS_RST_B );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_OPTICS_IRQ               , 17  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_OPTICS_IRQ );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_TRAINING                 , 18  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_TRAINING );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_MAX_PKT_TIMER            , 19  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_MAX_PKT_TIMER );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK0_MAX_PKT_TIMER_LEN        , 5   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_MAX_PKT_TIMER_LEN );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_CURRENT_STATE            , 28  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_CURRENT_STATE );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_CURRENT_STATE_LEN        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_CURRENT_STATE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_PRIOR_STATE              , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_PRIOR_STATE );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_PRIOR_STATE_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_PRIOR_STATE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_OPTICS_RST_B             , 40  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_OPTICS_RST_B );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_OPTICS_IRQ               , 41  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_OPTICS_IRQ );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_TRAINING                 , 42  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_TRAINING );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_MAX_PKT_TIMER            , 43  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_MAX_PKT_TIMER );
+REG64_FLD( OBUS_LL0_IOOL_DLL_STATUS_LINK1_MAX_PKT_TIMER_LEN        , 5   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_MAX_PKT_TIMER_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_ERR_INJ_LFSR_LFSR                         , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LFSR       );
+REG64_FLD( OBUS_LL0_IOOL_ERR_INJ_LFSR_LFSR_LEN                     , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LFSR_LEN   );
+
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK0_ROUND_TRIP_VALID        , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ROUND_TRIP_VALID );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK0_ROUND_TRIP              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ROUND_TRIP );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK0_ROUND_TRIP_LEN          , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ROUND_TRIP_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK1_ROUND_TRIP_VALID        , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ROUND_TRIP_VALID );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK1_ROUND_TRIP              , 14  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ROUND_TRIP );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK1_ROUND_TRIP_LEN          , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ROUND_TRIP_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_VALID , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LOCAL_LATENCY_DIFFERENCE_VALID );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LOCAL_LATENCY_LONGER_LINK     , 25  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LOCAL_LATENCY_LONGER_LINK );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE      , 29  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LOCAL_LATENCY_DIFFERENCE );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_LEN  , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LOCAL_LATENCY_DIFFERENCE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_VALID , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REMOTE_LATENCY_DIFFERENCE_VALID );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_REMOTE_LATENCY_LONGER_LINK    , 37  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REMOTE_LATENCY_LONGER_LINK );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE     , 41  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REMOTE_LATENCY_DIFFERENCE );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REMOTE_LATENCY_DIFFERENCE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK0_TOD_LATENCY             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_TOD_LATENCY );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK0_TOD_LATENCY_LEN         , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_TOD_LATENCY_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK1_TOD_LATENCY             , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_TOD_LATENCY );
+REG64_FLD( OBUS_LL0_IOOL_LAT_MEASURE_LINK1_TOD_LATENCY_LEN         , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_TOD_LATENCY_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_0           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_0 );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_0_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_0_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_1           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_1 );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_1_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_1_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_2           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_2 );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_2_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_2_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_3           , 12  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_3 );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_3_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_3_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_4           , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_4 );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_4_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_4_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_5           , 20  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_5 );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_5_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_5_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_6           , 24  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_6 );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_6_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_6_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_7           , 28  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_7 );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_7_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_7_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_8           , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_8 );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_8_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_8_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_9           , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_9 );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_9_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_9_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_10          , 40  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_10 );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_10_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_10_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_11          , 44  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_11 );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_EDPL_STATUS_ERROR_COUNT_11_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_11_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_RESET_KEEPER           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESET_KEEPER );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_CE                     , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CE         );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_CE_LEN                 , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CE_LEN     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_UE                     , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UE         );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_UE_LEN                 , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UE_LEN     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_OSC                    , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OSC        );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_OSC_LEN                , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OSC_LEN    );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_TRAIN                  , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAIN      );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_TRAIN_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAIN_LEN  );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_UNRECOV                , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNRECOV    );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_UNRECOV_LEN            , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNRECOV_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_INTERNAL               , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INTERNAL   );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_ERROR_STATUS_INTERNAL_LEN           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INTERNAL_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_MAX_TIMEOUT                    , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MAX_TIMEOUT );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_MAX_TIMEOUT_LEN                , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MAX_TIMEOUT_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_FRAME_CAP_VALID                , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_VALID );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_FRAME_CAP_INST                 , 17  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_INST );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_FRAME_CAP_ADDR                 , 18  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_ADDR );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_FRAME_CAP_ADDR_LEN             , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_ADDR_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_FRAME_CAP_SYN                  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_SYN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_FRAME_CAP_SYN_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_SYN_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_REPLAY_CAP_VALID               , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_VALID );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_REPLAY_CAP_INST                , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_INST );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_REPLAY_CAP_INST_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_INST_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_REPLAY_CAP_ADDR                , 35  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_ADDR );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_REPLAY_CAP_ADDR_LEN            , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_ADDR_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_REPLAY_CAP_SYN                 , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_SYN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_REPLAY_CAP_SYN_LEN             , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_SYN_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_ACK_FIFO_CAP_VALID             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_VALID );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_ACK_FIFO_CAP_ADDR              , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_ADDR );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_INFO_ACK_FIFO_CAP_ADDR_LEN          , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_ADDR_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_LINK0_QUALITY_TX_BW                       , 1   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_TX_BW      );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_QUALITY_TX_BW_LEN                   , 11  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_TX_BW_LEN  );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_QUALITY_RX_BW                       , 13  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_RX_BW      );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_QUALITY_RX_BW_LEN                   , 11  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_RX_BW_LEN  );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_QUALITY_ERROR_RATE                  , 25  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_RATE );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_QUALITY_ERROR_RATE_LEN              , 23  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_RATE_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_DISABLED            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED   );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_DISABLED_LEN        , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_BRINGUP             , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BRINGUP    );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_BRINGUP_LEN         , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BRINGUP_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_SPARED              , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARED     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_SPARED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARED_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_LOCKED              , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LOCKED     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_LOCKED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LOCKED_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_FAILED              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FAILED     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_RX_LANE_CONTROL_FAILED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FAILED_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_CRC            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LEN        , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0     , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN0 );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN0_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1     , 44  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN1 );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN1_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN2     , 52  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN2 );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN2_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN2_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LANE );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN   , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LANE_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE00              , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE00     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE00_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE00_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE01              , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE01     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE01_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE01_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE02              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE02     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE02_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE02_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE03              , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE03     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE03_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE03_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE04              , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE04     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE04_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE04_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE05              , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE05     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE05_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE05_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE06              , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE06     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE06_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE06_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE07              , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE07     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE07_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE07_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE08              , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE08     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE08_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE08_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE09              , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE09     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE09_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE09_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE10              , 40  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE10     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE10_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE10_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE11              , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE11     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_LANE11_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE11_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_FAILED              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FAILED     );
+REG64_FLD( OBUS_LL0_IOOL_LINK0_TX_LANE_CONTROL_FAILED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FAILED_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_0           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_0 );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_0_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_0_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_1           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_1 );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_1_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_1_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_2           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_2 );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_2_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_2_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_3           , 12  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_3 );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_3_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_3_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_4           , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_4 );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_4_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_4_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_5           , 20  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_5 );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_5_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_5_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_6           , 24  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_6 );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_6_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_6_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_7           , 28  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_7 );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_7_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_7_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_8           , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_8 );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_8_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_8_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_9           , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_9 );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_9_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_9_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_10          , 40  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_10 );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_10_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_10_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_11          , 44  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_11 );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_EDPL_STATUS_ERROR_COUNT_11_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_11_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_RESET_KEEPER           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESET_KEEPER );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_CE                     , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CE         );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_CE_LEN                 , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CE_LEN     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_UE                     , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UE         );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_UE_LEN                 , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UE_LEN     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_OSC                    , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OSC        );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_OSC_LEN                , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OSC_LEN    );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_TRAIN                  , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAIN      );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_TRAIN_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAIN_LEN  );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_UNRECOV                , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNRECOV    );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_UNRECOV_LEN            , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNRECOV_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_INTERNAL               , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INTERNAL   );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_ERROR_STATUS_INTERNAL_LEN           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INTERNAL_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_MAX_TIMEOUT                    , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MAX_TIMEOUT );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_MAX_TIMEOUT_LEN                , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MAX_TIMEOUT_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_FRAME_CAP_VALID                , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_VALID );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_FRAME_CAP_INST                 , 17  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_INST );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_FRAME_CAP_ADDR                 , 18  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_ADDR );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_FRAME_CAP_ADDR_LEN             , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_ADDR_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_FRAME_CAP_SYN                  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_SYN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_FRAME_CAP_SYN_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_SYN_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_REPLAY_CAP_VALID               , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_VALID );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_REPLAY_CAP_INST                , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_INST );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_REPLAY_CAP_INST_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_INST_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_REPLAY_CAP_ADDR                , 35  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_ADDR );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_REPLAY_CAP_ADDR_LEN            , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_ADDR_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_REPLAY_CAP_SYN                 , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_SYN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_REPLAY_CAP_SYN_LEN             , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_SYN_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_ACK_FIFO_CAP_VALID             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_VALID );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_ACK_FIFO_CAP_ADDR              , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_ADDR );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_INFO_ACK_FIFO_CAP_ADDR_LEN          , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_ADDR_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_LINK1_QUALITY_TX_BW                       , 1   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_TX_BW      );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_QUALITY_TX_BW_LEN                   , 11  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_TX_BW_LEN  );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_QUALITY_RX_BW                       , 13  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_RX_BW      );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_QUALITY_RX_BW_LEN                   , 11  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_RX_BW_LEN  );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_QUALITY_ERROR_RATE                  , 25  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_RATE );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_QUALITY_ERROR_RATE_LEN              , 23  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_RATE_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_DISABLED            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED   );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_DISABLED_LEN        , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_BRINGUP             , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BRINGUP    );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_BRINGUP_LEN         , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BRINGUP_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_SPARED              , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARED     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_SPARED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARED_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_LOCKED              , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LOCKED     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_LOCKED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LOCKED_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_FAILED              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FAILED     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_RX_LANE_CONTROL_FAILED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FAILED_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_CRC            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LEN        , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0     , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN0 );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN0_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1     , 44  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN1 );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN1_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN2     , 52  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN2 );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN2_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN2_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LANE );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN   , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LANE_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE00              , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE00     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE00_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE00_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE01              , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE01     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE01_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE01_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE02              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE02     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE02_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE02_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE03              , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE03     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE03_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE03_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE04              , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE04     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE04_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE04_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE05              , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE05     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE05_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE05_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE06              , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE06     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE06_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE06_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE07              , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE07     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE07_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE07_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE08              , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE08     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE08_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE08_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE09              , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE09     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE09_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE09_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE10              , 40  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE10     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE10_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE10_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE11              , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE11     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_LANE11_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE11_LEN );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_FAILED              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FAILED     );
+REG64_FLD( OBUS_LL0_IOOL_LINK1_TX_LANE_CONTROL_FAILED_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FAILED_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_LINKX_ERROR_STATUS_RESET_KEEPER           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESET_KEEPER );
+REG64_FLD( OBUS_LL0_IOOL_LINKX_ERROR_STATUS_STATUS                 , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_STATUS     );
+REG64_FLD( OBUS_LL0_IOOL_LINKX_ERROR_STATUS_STATUS_LEN             , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_DISABLE_BAD_LANE_COUNT     , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_BAD_LANE_COUNT );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_DISABLE_CLEAR_BAD_LANE_COUNT , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_CLEAR_BAD_LANE_COUNT );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED1                , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OPT_UNUSED1 );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED1_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OPT_UNUSED1_LEN );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_DURATION          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE_DURATION );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_DURATION_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE_DURATION_LEN );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED2                , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OPT_UNUSED2 );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_MAX               , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE_MAX );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_BAD_LANE_MAX_LEN           , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE_MAX_LEN );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_DISABLE_LINK_FAIL_COUNT    , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_LINK_FAIL_COUNT );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED3                , 17  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OPT_UNUSED3 );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED3_LEN            , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OPT_UNUSED3_LEN );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_DURATION         , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK_FAIL_DURATION );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_DURATION_LEN     , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK_FAIL_DURATION_LEN );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED4                , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OPT_UNUSED4 );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_MAX              , 25  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK_FAIL_MAX );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK_FAIL_MAX_LEN          , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK_FAIL_MAX_LEN );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_CLEAR_LINK_FAIL_COUNTER    , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CLEAR_LINK_FAIL_COUNTER );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_CLEAR_BAD_LANE_COUNTER     , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CLEAR_BAD_LANE_COUNTER );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED5                , 34  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OPT_UNUSED5 );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_OPT_UNUSED5_LEN            , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OPT_UNUSED5_LEN );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_ELEVEN_LANE_MODE           , 37  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ELEVEN_LANE_MODE );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK0_ELEVEN_LANE_SHIFT    , 38  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ELEVEN_LANE_SHIFT );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK1_ELEVEN_LANE_SHIFT    , 39  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ELEVEN_LANE_SHIFT );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK0_RX_LANE_SWAP         , 40  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_RX_LANE_SWAP );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK0_TX_LANE_SWAP         , 41  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_TX_LANE_SWAP );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK1_RX_LANE_SWAP         , 42  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_RX_LANE_SWAP );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK1_TX_LANE_SWAP         , 43  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_TX_LANE_SWAP );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_LOW              , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_QUEUE_LOW );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_LOW_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_QUEUE_LOW_LEN );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_START            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_QUEUE_START );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_START_LEN        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_QUEUE_START_LEN );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_HIGH             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_QUEUE_HIGH );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_ACK_QUEUE_HIGH_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_QUEUE_HIGH_LEN );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_REPLAY_BUFFER_SIZE         , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_BUFFER_SIZE );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_REPLAY_BUFFER_SIZE_LEN     , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_BUFFER_SIZE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK0_OLL_ENABLED          , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_OLL_ENABLED );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_LINK1_OLL_ENABLED          , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_OLL_ENABLED );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_NPU_TRANSPORT_SWAP         , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NPU_TRANSPORT_SWAP );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_NV0_NPU_ENABLED            , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NV0_NPU_ENABLED );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_NV1_NPU_ENABLED            , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NV1_NPU_ENABLED );
+REG64_FLD( OBUS_LL0_IOOL_OPTICAL_CONFIG_NV2_NPU_ENABLED            , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NV2_NPU_ENABLED );
+
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER );
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_LEN       , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_1         , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_1 );
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_1_LEN     , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_1_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_2         , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_2 );
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_2_LEN     , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_2_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_3         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_3 );
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_0_PERFMON_COUNTER_3_LEN     , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_3_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_4         , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_4 );
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_4_LEN     , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_4_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_5         , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_5 );
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_5_LEN     , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_5_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_6         , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_6 );
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_6_LEN     , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_6_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_7         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_7 );
+REG64_FLD( OBUS_LL0_IOOL_PERF_COUNTERS_1_PERFMON_COUNTER_7_LEN     , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_7_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_0                  , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_0   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_0_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_0_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_1                  , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_1   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_1_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_1_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_2                  , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_2   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_2_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_2_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_3                  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_3   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_3_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_3_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_4                  , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_4   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_4_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_4_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_5                  , 40  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_5   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_5_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_5_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_6                  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_6   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_6_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_6_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_7                  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_7   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_SEL_CONFIG_SELECT_7_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_7_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_0                , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_0   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_0_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_0_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_1                , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_1   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_1_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_1_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_2                , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_2   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_2_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_2_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_3                , 6   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_3   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_3_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_3_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_4                , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_4   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_4_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_4_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_5                , 10  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_5   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_5_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_5_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_6                , 12  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_6   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_6_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_6_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_7                , 14  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_7   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_ENABLE_7_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_7_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_0                  , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_0     );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_0_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_0_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_1                  , 18  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_1     );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_1_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_1_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_2                  , 20  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_2     );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_2_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_2_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_3                  , 22  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_3     );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_3_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_3_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_4                  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_4     );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_4_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_4_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_5                  , 26  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_5     );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_5_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_5_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_6                  , 28  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_6     );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_6_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_6_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_7                  , 30  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_7     );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_SIZE_7_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_7_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_PMULET_FREEZE_MODE      , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMULET_FREEZE_MODE );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_COMMON_FREEZE_MODE      , 33  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_COMMON_FREEZE_MODE );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_RESET_MODE              , 34  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESET_MODE );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_PERFTRACE_ENABLE        , 35  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFTRACE_ENABLE );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_PERFTRACE_FIXED_WINDOW  , 36  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFTRACE_FIXED_WINDOW );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_PERFTRACE_PRESCALE      , 37  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFTRACE_PRESCALE );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_PERFTRACE_MODE          , 38  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFTRACE_MODE );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_PERFTRACE_MODE_LEN      , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFTRACE_MODE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_CONFIG_0                , 40  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIG_0   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_CONFIG_0_LEN            , 12  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIG_0_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_CONFIG_1                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIG_1   );
+REG64_FLD( OBUS_LL0_IOOL_PERF_TRACE_CONFIG_CONFIG_1_LEN            , 12  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIG_1_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_A_ADJ                    , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRAIN_A_ADJ );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_A_ADJ_LEN                , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRAIN_A_ADJ_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_B_ADJ                    , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRAIN_B_ADJ );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_B_ADJ_LEN                , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRAIN_B_ADJ_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_TIME                     , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRAIN_TIME );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_TIME_LEN                 , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRAIN_TIME_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_A_HYST                   , 8   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRAIN_A_HYST );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_A_HYST_LEN               , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRAIN_A_HYST_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_B_HYST                   , 12  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRAIN_B_HYST );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_TRAIN_B_HYST_LEN               , 4   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRAIN_B_HYST_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_PRBS_PHASE_SELECT              , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRBS_PHASE_SELECT );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_PRBS_PHASE_SELECT_LEN          , 24  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRBS_PHASE_SELECT_LEN );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_PRBS                           , 40  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRBS       );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_PRBS_LEN                       , 10  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRBS_LEN   );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_PRBS_INVERT                    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRBS_INVERT );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_UNUSED                         , 51  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNUSED     );
+REG64_FLD( OBUS_LL0_IOOL_PHY_CONFIG_UNUSED_LEN                     , 13  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNUSED_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_TB_SEL            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TB_SEL );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_TB_SEL_LEN        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TB_SEL_LEN );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_TAP_SEL           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TAP_SEL );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_TAP_SEL_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TAP_SEL_LEN );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_ENABLE            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_ENABLE );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_ENABLE_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_ENABLE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_UNUSED1           , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED1 );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_UNUSED1_LEN       , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED1_LEN );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK0_CLEAR       , 26  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_CLEAR );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK1_CLEAR       , 27  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_CLEAR );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_DIS_TB_CLEAR      , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TB_CLEAR );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_DIS_TAP_CLEAR     , 29  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TAP_CLEAR );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_DIS_TAP_STOP      , 30  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TAP_STOP );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_UNUSED2           , 31  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED2 );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT       , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_COUNT );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT_LEN   , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_COUNT_LEN );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_COUNT );
+REG64_FLD( OBUS_LL0_IOOL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT_LEN   , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_COUNT_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_TB_SEL           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TB_SEL );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_TB_SEL_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TB_SEL_LEN );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_TAP_SEL          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TAP_SEL );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_TAP_SEL_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TAP_SEL_LEN );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_ENABLE           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_ENABLE );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_ENABLE_LEN       , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_ENABLE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_UNUSED1          , 17  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED1 );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_UNUSED1_LEN      , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED1_LEN );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK0_CLEAR      , 26  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_CLEAR );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK1_CLEAR      , 27  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_CLEAR );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_DIS_TB_CLEAR     , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TB_CLEAR );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_DIS_TAP_CLEAR    , 29  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TAP_CLEAR );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_DIS_TAP_STOP     , 30  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TAP_STOP );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_UNUSED2          , 31  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED2 );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK0_COUNT      , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_COUNT );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK0_COUNT_LEN  , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_COUNT_LEN );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK1_COUNT      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_COUNT );
+REG64_FLD( OBUS_LL0_IOOL_RETRAIN_THRESHOLD_THRESH_LINK1_COUNT_LEN  , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_COUNT_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_ENABLE_ERR_INJ                 , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_ERR_INJ );
+REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_UNUSED4                        , 1   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNUSED4    );
+REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_UNUSED4_LEN                    , 15  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNUSED4_LEN );
+REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_SBE_ERROR_RATE                 , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SBE_ERROR_RATE );
+REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_SBE_ERROR_RATE_LEN             , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SBE_ERROR_RATE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_RAND_ERROR_RATE                , 18  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RAND_ERROR_RATE );
+REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_RAND_ERROR_RATE_LEN            , 6   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RAND_ERROR_RATE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_INV_SH_ERROR_RATE              , 24  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_INV_SH_ERROR_RATE );
+REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_INV_SH_ERROR_RATE_LEN          , 2   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_INV_SH_ERROR_RATE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_SYNC_HEADER_ERROR_RATE         , 26  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_HEADER_ERROR_RATE );
+REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_SYNC_HEADER_ERROR_RATE_LEN     , 6   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_HEADER_ERROR_RATE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_UNUSED5                        , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNUSED5    );
+REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_UNUSED5_LEN                    , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNUSED5_LEN );
+REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_EDPL_RATE                      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_EDPL_RATE  );
+REG64_FLD( OBUS_LL0_IOOL_SEC_CONFIG_EDPL_RATE_LEN                  , 16  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_EDPL_RATE_LEN );
+
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_TB_SEL            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TB_SEL );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_TB_SEL_LEN        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TB_SEL_LEN );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_TAP_SEL           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TAP_SEL );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_TAP_SEL_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TAP_SEL_LEN );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_ENABLE            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_ENABLE );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_ENABLE_LEN        , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_ENABLE_LEN );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_UNUSED1           , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED1 );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_UNUSED1_LEN       , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED1_LEN );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK0_CLEAR       , 26  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_CLEAR );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK1_CLEAR       , 27  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_CLEAR );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_DIS_TB_CLEAR      , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TB_CLEAR );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_CLEAR     , 29  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TAP_CLEAR );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_STOP      , 30  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TAP_STOP );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_UNUSED2           , 31  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED2 );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT       , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_COUNT );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT_LEN   , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_COUNT_LEN );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_COUNT );
+REG64_FLD( OBUS_LL0_IOOL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT_LEN   , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_COUNT_LEN );
+
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TRAINED     , 0   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TRAINED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TRAINED     , 1   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TRAINED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_OP_IRQ      , 2   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_OP_IRQ );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_OP_IRQ      , 3   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_OP_IRQ );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_REPLAY_THRESHOLD , 4   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_REPLAY_THRESHOLD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_REPLAY_THRESHOLD , 5   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_REPLAY_THRESHOLD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_CRC_ERROR   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_CRC_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_CRC_ERROR   , 7   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_CRC_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_NAK_RECEIVED , 8   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_NAK_RECEIVED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_NAK_RECEIVED , 9   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_NAK_RECEIVED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_REPLAY_BUFFER_FULL , 10  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_REPLAY_BUFFER_FULL );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_REPLAY_BUFFER_FULL , 11  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_REPLAY_BUFFER_FULL );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SL_ECC_THRESHOLD , 12  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_THRESHOLD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SL_ECC_THRESHOLD , 13  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_THRESHOLD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SL_ECC_CORRECTABLE , 14  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_CORRECTABLE );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SL_ECC_CORRECTABLE , 15  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_CORRECTABLE );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SL_ECC_UE   , 16  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_UE );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SL_ECC_UE   , 17  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_UE );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_RETRAIN_THRESHOLD , 18  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_RETRAIN_THRESHOLD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_RETRAIN_THRESHOLD , 19  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_RETRAIN_THRESHOLD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_LOSS_BLOCK_ALIGN , 20  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_LOSS_BLOCK_ALIGN );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_LOSS_BLOCK_ALIGN , 21  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_LOSS_BLOCK_ALIGN );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_INVALID_BLOCK , 22  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_INVALID_BLOCK );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_INVALID_BLOCK , 23  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_INVALID_BLOCK );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_DESKEW_ERROR , 24  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_DESKEW_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_DESKEW_ERROR , 25  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_DESKEW_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_DESKEW_OVERFLOW , 26  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_DESKEW_OVERFLOW );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_DESKEW_OVERFLOW , 27  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_DESKEW_OVERFLOW );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SW_RETRAIN  , 28  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SW_RETRAIN );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SW_RETRAIN  , 29  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SW_RETRAIN );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_ACK_QUEUE_OVERFLOW , 30  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_ACK_QUEUE_OVERFLOW );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_ACK_QUEUE_OVERFLOW , 31  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_ACK_QUEUE_OVERFLOW );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_ACK_QUEUE_UNDERFLOW , 32  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_ACK_QUEUE_UNDERFLOW );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_ACK_QUEUE_UNDERFLOW , 33  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_ACK_QUEUE_UNDERFLOW );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_NUM_REPLAY  , 34  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_NUM_REPLAY );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_NUM_REPLAY  , 35  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_NUM_REPLAY );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TRAINING_SET_RECEIVED , 36  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TRAINING_SET_RECEIVED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TRAINING_SET_RECEIVED , 37  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TRAINING_SET_RECEIVED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_PRBS_SELECT_ERROR , 38  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_PRBS_SELECT_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_PRBS_SELECT_ERROR , 39  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_PRBS_SELECT_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TCOMPLETE_BAD , 40  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TCOMPLETE_BAD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TCOMPLETE_BAD , 41  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TCOMPLETE_BAD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SPARE_DONE  , 44  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SPARE_DONE );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SPARE_DONE  , 45  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SPARE_DONE );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TOO_MANY_CRC_ERRORS , 46  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TOO_MANY_CRC_ERRORS );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TOO_MANY_CRC_ERRORS , 47  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TOO_MANY_CRC_ERRORS );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_NPU_ERROR   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_NPU_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_NPU_ERROR   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_NPU_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINKX_NPU_ERROR   , 50  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINKX_NPU_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_OSC_SWITCH        , 51  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_OSC_SWITCH );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_CORRECTABLE_ARRAY_ERROR , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM2_OR , SH_FLD_LINK0_CORRECTABLE_ARRAY_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_CORRECTABLE_ARRAY_ERROR , 53  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM2_OR , SH_FLD_LINK1_CORRECTABLE_ARRAY_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR , 54  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM2_OR , SH_FLD_LINK0_UNCORRECTABLE_ARRAY_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR , 55  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM2_OR , SH_FLD_LINK1_UNCORRECTABLE_ARRAY_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TRAINING_FAILED , 56  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TRAINING_FAILED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TRAINING_FAILED , 57  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TRAINING_FAILED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_UNRECOVERABLE_ERROR , 58  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_UNRECOVERABLE_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_UNRECOVERABLE_ERROR , 59  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_UNRECOVERABLE_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_INTERNAL_ERROR , 60  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_INTERNAL_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_INTERNAL_ERROR , 61  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_INTERNAL_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_SCOM_ERR_DUP      , 62  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_SCOM_ERR          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_TRAINED          , 0   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TRAINED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_TRAINED          , 1   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TRAINED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_OP_IRQ           , 2   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_OP_IRQ );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_OP_IRQ           , 3   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_OP_IRQ );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_REPLAY_THRESHOLD , 4   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_REPLAY_THRESHOLD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_REPLAY_THRESHOLD , 5   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_REPLAY_THRESHOLD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_CRC_ERROR        , 6   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_CRC_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_CRC_ERROR        , 7   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_CRC_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_NAK_RECEIVED     , 8   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_NAK_RECEIVED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_NAK_RECEIVED     , 9   , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_NAK_RECEIVED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_REPLAY_BUFFER_FULL , 10  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_REPLAY_BUFFER_FULL );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_REPLAY_BUFFER_FULL , 11  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_REPLAY_BUFFER_FULL );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_SL_ECC_THRESHOLD , 12  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_THRESHOLD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_SL_ECC_THRESHOLD , 13  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_THRESHOLD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_SL_ECC_CORRECTABLE , 14  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_CORRECTABLE );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_SL_ECC_CORRECTABLE , 15  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_CORRECTABLE );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_SL_ECC_UE        , 16  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_UE );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_SL_ECC_UE        , 17  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_UE );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_RETRAIN_THRESHOLD , 18  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_RETRAIN_THRESHOLD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_RETRAIN_THRESHOLD , 19  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_RETRAIN_THRESHOLD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_LOSS_BLOCK_ALIGN , 20  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_LOSS_BLOCK_ALIGN );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_LOSS_BLOCK_ALIGN , 21  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_LOSS_BLOCK_ALIGN );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_INVALID_BLOCK    , 22  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_INVALID_BLOCK );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_INVALID_BLOCK    , 23  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_INVALID_BLOCK );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_DESKEW_ERROR     , 24  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_DESKEW_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_DESKEW_ERROR     , 25  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_DESKEW_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_DESKEW_OVERFLOW  , 26  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_DESKEW_OVERFLOW );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_DESKEW_OVERFLOW  , 27  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_DESKEW_OVERFLOW );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_SW_RETRAIN       , 28  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SW_RETRAIN );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_SW_RETRAIN       , 29  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SW_RETRAIN );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_ACK_QUEUE_OVERFLOW , 30  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_ACK_QUEUE_OVERFLOW );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_ACK_QUEUE_OVERFLOW , 31  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_ACK_QUEUE_OVERFLOW );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_ACK_QUEUE_UNDERFLOW , 32  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_ACK_QUEUE_UNDERFLOW );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_ACK_QUEUE_UNDERFLOW , 33  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_ACK_QUEUE_UNDERFLOW );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_NUM_REPLAY       , 34  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_NUM_REPLAY );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_NUM_REPLAY       , 35  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_NUM_REPLAY );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_TRAINING_SET_RECEIVED , 36  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TRAINING_SET_RECEIVED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_TRAINING_SET_RECEIVED , 37  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TRAINING_SET_RECEIVED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_PRBS_SELECT_ERROR , 38  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_PRBS_SELECT_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_PRBS_SELECT_ERROR , 39  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_PRBS_SELECT_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_TCOMPLETE_BAD    , 40  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TCOMPLETE_BAD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_TCOMPLETE_BAD    , 41  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TCOMPLETE_BAD );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_SPARE_DONE       , 44  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SPARE_DONE );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_SPARE_DONE       , 45  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SPARE_DONE );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_TOO_MANY_CRC_ERRORS , 46  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TOO_MANY_CRC_ERRORS );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_TOO_MANY_CRC_ERRORS , 47  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TOO_MANY_CRC_ERRORS );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_NPU_ERROR        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_NPU_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_NPU_ERROR        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_NPU_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINKX_NPU_ERROR        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINKX_NPU_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_OSC_SWITCH             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_OSC_SWITCH );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_CORRECTABLE_ARRAY_ERROR , 52  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_CORRECTABLE_ARRAY_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_CORRECTABLE_ARRAY_ERROR , 53  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_CORRECTABLE_ARRAY_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR , 54  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_UNCORRECTABLE_ARRAY_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR , 55  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_UNCORRECTABLE_ARRAY_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_TRAINING_FAILED  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TRAINING_FAILED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_TRAINING_FAILED  , 57  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TRAINING_FAILED );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_UNRECOVERABLE_ERROR , 58  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_UNRECOVERABLE_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_UNRECOVERABLE_ERROR , 59  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_UNRECOVERABLE_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK0_INTERNAL_ERROR   , 60  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_INTERNAL_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_LINK1_INTERNAL_ERROR   , 61  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_INTERNAL_ERROR );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_SCOM_ERR_DUP           , 62  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+REG64_FLD( OBUS_LL0_LL0_LL0_PB_IOOL_FIR_REG_SCOM_ERR               , 63  , SH_UNT_OBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+
+REG64_FLD( OBUS_LL0_PB_IOOL_FIR_ACTION0_REG_ACTION0                , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( OBUS_LL0_PB_IOOL_FIR_ACTION0_REG_ACTION0_LEN            , 64  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( OBUS_LL0_PB_IOOL_FIR_ACTION1_REG_ACTION1                , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( OBUS_LL0_PB_IOOL_FIR_ACTION1_REG_ACTION1_LEN            , 64  , SH_UNT_OBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE0_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE1_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE2_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS4_SLICE3_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE0_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE1_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE2_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_B );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_EDGE , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_EDGE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_B    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_B   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_B , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_B , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_B );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_B_OFFSET_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_B_OFFSET_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_PR_RESET    , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_RESET   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTL4_EO_PL_IORESET     , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_SEL_A , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_SEL_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_MARGIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_MARGIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_SCOPE_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_MODE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_CNTLX1_EO_PL_BANK_PDWN_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_PDWN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_A , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_A );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_DECOUPLE_EDGE_B , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DECOUPLE_EDGE_B );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_DIG_REQ_DIS , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_DIG_REQ_DIS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE1_EO_PL_PSAVE_ANA_REQ_DIS , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_ANA_REQ_DIS );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_OFF   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_OFF  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL_PR_FW_INERTIA_AMT_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_FW_INERTIA_AMT_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG     , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_EN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_COARSE_MODE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_INVALID_LOCK_COARSE_EN , 49  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_COARSE_EN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE , 50  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_FW_INERTIA_AMT_COARSE_LEN , 3   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_PHASE_STEP_COARSE_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_PHASE_STEP_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL , 57  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_MODE4_EO_PL_PR_COARSE_MODE_TIMER_SEL_LEN , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT1_O_PL_B_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL10_O_PL_E_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_A_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BANK_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_EO_PL_B_BANK_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BANK_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL1_O_PL_B_CONTROLS_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_PR_HALFRATE_MODE , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_HALFRATE_MODE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL2_O_PL_B_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1  , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL3_O_PL_B_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL4_O_PL_B_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN  , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL5_O_PL_B_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_COARSE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_COARSE_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL_B_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL    , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL6_O_PL_B_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL7_O_PL_E_CONTROLS_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_CONTROLS_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_E_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_E_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET     , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET   );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL8_O_PL_E_OFFSET_LEN , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_OFFSET_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_INTEG_COARSE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_ODD_INTEG_FINE_GAIN );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DAC_CNTL9_O_PL_E_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_FIR_MASK_PL_ERRS_LEN        , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_0             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_1             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_2             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_3             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_4             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_5             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_6             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RXPACKS5_SLICE3_RX_SPARE_MODE_PL_7             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PRBS_TEST_TIME );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME_LEN    , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PRBS_TEST_TIME_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL10_EO_PG_BIST_BUS_DATA_MODE         , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_BUS_DATA_MODE );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME        , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PRBS_PROP_TIME );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME_LEN    , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PRBS_PROP_TIME_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT               , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_LLMT );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT_LEN           , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_LLMT_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_RESET              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_RESET );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_START              , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_START );
+
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT               , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_HLMT );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT_LEN           , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_HLMT_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_VALID   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_VALID );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_LANE );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_LANE_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH         , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LEN     , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_VALID  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_VALID );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_LANE );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_LANE_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT        , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LEN    , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_EN                      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_EN     );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_FREEZE_EN         , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_TIMER_FREEZE_EN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_FREEZE_EN         , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_COUNT_FREEZE_EN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL               , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_COUNT_SEL );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL_LEN           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_COUNT_SEL_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL               , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_TIMER_SEL );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL_LEN           , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_TIMER_SEL_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_CLR_COUNT_ON_READ_EN    , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CLR_COUNT_ON_READ_EN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL1_EO_PG_BER_CLR_TIMER_ON_READ_EN    , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_CLR_TIMER_ON_READ_EN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL2_EO_PG_TRC_MODE                    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRC_MODE   );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL2_EO_PG_TRC_MODE_LEN                , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRC_MODE_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL3_EO_PG_INT_MODE                    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INT_MODE   );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL3_EO_PG_INT_MODE_LEN                , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INT_MODE_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INT_CURRENT_STATE );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE_LEN       , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INT_CURRENT_STATE_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INT_ENABLE_ENC );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INT_ENABLE_ENC_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE              , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INT_NEXT_STATE );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INT_NEXT_STATE_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE              , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INT_GOTO_STATE );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE_LEN          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INT_GOTO_STATE_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INT_RETURN_STATE );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE_LEN        , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INT_RETURN_STATE_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL8_EO_PG_SERVO_OP                    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_OP   );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL8_EO_PG_SERVO_OP_LEN                , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_OP_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL8_EO_PG_SERVO_DONE                  , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_DONE );
+
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_EN                     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EN    );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_EXT_START_MODE         , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EXT_START_MODE );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_INIT_DISABLE );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE_LEN       , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_INIT_DISABLE_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_CUPLL_LOCK_CHECK_EN    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_CUPLL_LOCK_CHECK_EN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_STORE_EYES_LANE_SEL );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_STORE_EYES_LANE_SEL_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL    , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_STORE_EYES_BANK_SEL );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_STORE_EYES_BANK_SEL_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_PERVASIVE_CAPT              , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PERVASIVE_CAPT );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTL9_EO_PG_BIST_LL_TEST_EN             , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_LL_TEST_EN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG        , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_PHY_GCRMSG );
+REG64_FLD( OBUS_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG_LEN    , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_PHY_GCRMSG_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG               , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_INIT_CFG );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG_LEN           , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_INIT_CFG_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG              , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_RECAL_CFG );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG_LEN          , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_RECAL_CFG_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG              , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_INIT_CFG );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG_LEN          , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_INIT_CFG_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG             , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_RECAL_CFG );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG_LEN         , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_RECAL_CFG_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_AMP_CFG                    , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_CFG    );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE10_EO_PG_AMP_CFG_LEN                , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG               , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OFF_INIT_CFG );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG_LEN           , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OFF_INIT_CFG_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG              , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OFF_RECAL_CFG );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG_LEN          , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OFF_RECAL_CFG_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_CM_CFG                     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CFG     );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_CM_CFG_LEN                 , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_CFG_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_AMIN_CFG                   , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMIN_CFG   );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_AMIN_CFG_LEN               , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMIN_CFG_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_USERDEF_CFG                , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_USERDEF_CFG );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE11_EO_PG_USERDEF_CFG_LEN            , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_USERDEF_CFG_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_CHG_CFG );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_CHG_CFG_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_DAC_BO_CFG                 , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DAC_BO_CFG );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_DAC_BO_CFG_LEN             , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DAC_BO_CFG_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_FILTER_MODE                , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FILTER_MODE );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_FILTER_MODE_LEN            , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FILTER_MODE_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_MISC_CFG                   , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CFG   );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_MISC_CFG_LEN               , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CFG_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_DISABLE_H1_CLEAR           , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_H1_CLEAR );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_VOFF_CFG                   , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_VOFF_CFG   );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_VOFF_CFG_LEN               , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_VOFF_CFG_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE12_EO_PG_LOFF_AMP_EN                , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LOFF_AMP_EN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL              , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_OFFSET_VAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL_LEN          , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_OFFSET_VAL_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH1              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH1 );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH1_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH1_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH2              , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH2 );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH2_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH2_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_INIT_TIMEOUT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_INIT_TIMEOUT_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT          , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_RECAL_TIMEOUT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_RECAL_TIMEOUT_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT          , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_INIT_TIMEOUT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_INIT_TIMEOUT_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT         , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_RECAL_TIMEOUT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT_LEN     , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_RECAL_TIMEOUT_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OFF_INIT_TIMEOUT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OFF_INIT_TIMEOUT_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT          , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OFF_RECAL_TIMEOUT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT_LEN      , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OFF_RECAL_TIMEOUT_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_CM_TIMEOUT                 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_TIMEOUT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_CM_TIMEOUT_LEN             , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CM_TIMEOUT_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT               , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMIN_TIMEOUT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT_LEN           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMIN_TIMEOUT_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_TIMEOUT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT_LEN            , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_TIMEOUT_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_USERDEF_TIMEOUT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT_LEN        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_USERDEF_TIMEOUT_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_BER_TIMEOUT                , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_TIMEOUT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_BER_TIMEOUT_LEN            , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BER_TIMEOUT_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT             , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE4_TIMEOUT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE4_TIMEOUT_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE17_EO_PG_AMAX_HIGH                  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMAX_HIGH  );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE17_EO_PG_AMAX_HIGH_LEN              , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMAX_HIGH_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE17_EO_PG_AMAX_LOW                   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMAX_LOW   );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE17_EO_PG_AMAX_LOW_LEN               , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMAX_LOW_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP0_FILTER_MASK );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK_LEN       , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP0_FILTER_MASK_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK           , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP1_FILTER_MASK );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK_LEN       , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP1_FILTER_MASK_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CTLE_GAIN_MAX );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CTLE_GAIN_MAX_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE19_EO_PG_AMP_START_VAL              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_START_VAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE19_EO_PG_AMP_START_VAL_LEN          , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_START_VAL_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_CLKDIST_PDWN                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CLKDIST_PDWN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_CLKDIST_PDWN_LEN            , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CLKDIST_PDWN_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH          , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_MIN_EYE_WIDTH );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH_LEN      , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_MIN_EYE_WIDTH_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_A_BIST_EN                   , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BIST_EN  );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_B_BIST_EN                   , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BIST_EN  );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_E_BIST_EN                   , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_E_BIST_EN  );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_BISTCLK_EN                  , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BISTCLK_EN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_BISTCLK_EN_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BISTCLK_EN_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE1_EO_PG_DISABLE_BANK_PDWN           , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_BANK_PDWN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE1_O_PG_MINIKERF                     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MINIKERF   );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE1_O_PG_MINIKERF_LEN                 , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MINIKERF_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DFE_CONVERGED_CNT_MAX );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX_LEN  , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DFE_CONVERGED_CNT_MAX_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX      , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AP110_AP010_DELTA_MAX );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX_LEN  , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AP110_AP010_DELTA_MAX_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_INTEG_LATCH_OFFSET_CAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_INTEG_LATCH_OFFSET_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_COARSE_CAL     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CTLE_COARSE_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DAC_H1_CAL          , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DAC_H1_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_VGA_CAL             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_VGA_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DFE_H1_CAL          , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DFE_H1_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_H1AP_TWEAK          , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_H1AP_TWEAK );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DDC                 , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DDC );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CM_COARSE_CAL       , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CM_COARSE_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CM_FINE_CAL         , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CM_FINE_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_VGA_EDGE_OFFSET_CAL , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_VGA_EDGE_OFFSET_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_EDGE_OFFSET_CAL , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CTLE_EDGE_OFFSET_CAL );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_INTEG_LATCH_OFFSET_CAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_INTEG_LATCH_OFFSET_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_COARSE_CAL  , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_CTLE_COARSE_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DAC_H1_CAL       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DAC_H1_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_VGA_CAL          , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_VGA_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DFE_H1_CAL       , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DFE_H1_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_H1AP_TWEAK       , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_H1AP_TWEAK );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DDC              , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DDC );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_COARSE_CAL    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_CM_COARSE_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_FINE_CAL      , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_CM_FINE_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_VGA_EDGE_OFFSET_CAL , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_VGA_EDGE_OFFSET_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_EDGE_OFFSET_CAL , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_CTLE_EDGE_OFFSET_CAL );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE23_EO_PG_QUAD_SEL                   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_QUAD_SEL   );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE23_EO_PG_QUAD_SEL_LEN               , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_QUAD_SEL_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE23_EO_PG_IREF_RES_DAC               , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IREF_RES_DAC );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE23_EO_PG_IREF_RES_DAC_LEN           , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IREF_RES_DAC_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE23_EO_PG_IREF_BYPASS                , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IREF_BYPASS );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE23_EO_PG_IREF_PDWN_B                , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IREF_PDWN_B );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE24_EO_PG_H1AP_CFG                   , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_H1AP_CFG   );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE24_EO_PG_H1AP_CFG_LEN               , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_H1AP_CFG_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE24_EO_PG_CTLE_UPDATE_MODE           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CTLE_UPDATE_MODE );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK           , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_USER_FILTER_MASK );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK_LEN       , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_USER_FILTER_MASK_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE26_EO_PG_ENABLE_VGA_AMAX_MODE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_VGA_AMAX_MODE );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_VGA_AMAX_MODE    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_VGA_AMAX_MODE );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_AUTO_RECAL       , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_AUTO_RECAL );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_COARSE_CAL    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DC_ENABLE_CM_COARSE_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_FINE_CAL      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DC_ENABLE_CM_FINE_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_INTEG_LATCH_OFFSET_CAL , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DC_ENABLE_INTEG_LATCH_OFFSET_CAL );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE29_EO_PG_APX111_HIGH                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_APX111_HIGH );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE29_EO_PG_APX111_HIGH_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_APX111_HIGH_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE29_EO_PG_APX111_LOW                 , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_APX111_LOW );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE29_EO_PG_APX111_LOW_LEN             , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_APX111_LOW_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_DFE_CA_CFG                  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DFE_CA_CFG );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_DFE_CA_CFG_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DFE_CA_CFG_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL               , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_CONTROL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL_LEN           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_CONTROL_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_RECAL_REQ_DL_MASK           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ_DL_MASK );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_RECAL_DONE_DL_MASK          , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_DONE_DL_MASK );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_RUN_LANE_DL_MASK            , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE_DL_MASK );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_RECAL_ABORT_DL_MASK         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT_DL_MASK );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_INIT_DONE_DL_MASK           , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INIT_DONE_DL_MASK );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_DATA_PIPE_CLR_ON_READ_MODE  , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DATA_PIPE_CLR_ON_READ_MODE );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_CFG_LTE_MC                  , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LTE_MC );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_EO_PG_CFG_LTE_MC_LEN              , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LTE_MC_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_O_PG_OCTANT_SELECT                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OCTANT_SELECT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_O_PG_OCTANT_SELECT_LEN            , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_OCTANT_SELECT_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_O_PG_SPEED_SELECT                 , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPEED_SELECT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_O_PG_SPEED_SELECT_LEN             , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPEED_SELECT_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE2_O_PG_AC_COUPLED                   , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AC_COUPLED );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL        , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRACKING_TIMEOUT_SEL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL_LEN    , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRACKING_TIMEOUT_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CONVERGED_END_COUNT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT_LEN     , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CONVERGED_END_COUNT_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE     , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_MODE );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_MODE_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_MODE );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_MODE_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX            , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_GAIN_CNT_MAX );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX_LEN        , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AMP_GAIN_CNT_MAX_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_CHECK_TIMEOUT_SEL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_CHECK_TIMEOUT_SEL_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL         , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_POLLING_TIMEOUT_SEL );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL_LEN     , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_POLLING_TIMEOUT_SEL_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH               , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MIN_EYE_WIDTH );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH_LEN           , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MIN_EYE_WIDTH_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MIN_EYE_HEIGHT );
+REG64_FLD( OBUS_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT_LEN          , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MIN_EYE_HEIGHT_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_STAT1_EO_PG_SERVO_RESULT                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_RESULT );
+REG64_FLD( OBUS_RX0_RX_CTL_STAT1_EO_PG_SERVO_RESULT_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_RESULT_LEN );
+
+REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_INIT_DONE              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_INIT_DONE );
+REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_DONE                   , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_DONE  );
+REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_LL_ERR                 , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_LL_ERR );
+REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_NO_EDGE_DET            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_NO_EDGE_DET );
+REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EYE_A_WIDTH );
+REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH_LEN        , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EYE_A_WIDTH_LEN );
+REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH            , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EYE_B_WIDTH );
+REG64_FLD( OBUS_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH_LEN        , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EYE_B_WIDTH_LEN );
+
+REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_0                      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_1                      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_2                      , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_3                      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_4                      , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_5                      , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_6                      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_7                      , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG           , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_CONFIG );
+REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG_LEN       , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_CONFIG_LEN );
+REG64_FLD( OBUS_RX0_RX_DATASM_SPARE_MODE_PG_CTL_CLKDIST_PDWN       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CTL_CLKDIST_PDWN );
+
+REG64_FLD( OBUS_RX0_RX_FIR1_ERROR_INJECT_PG_ERR_INJ                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_RX0_RX_FIR1_ERROR_INJECT_PG_ERR_INJ_LEN            , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_RX0_RX_FIR1_MASK_PG_ERRS                           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX0_RX_FIR1_MASK_PG_ERRS_LEN                       , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL2_EO_PG_CNT_SINGLE_LANE_RECAL     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CNT_SINGLE_LANE_RECAL );
+REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_LANE_TO_MONITOR );
+REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_LANE_TO_MONITOR_LEN );
+
+REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_REQUEST      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MANUAL_RECAL_REQUEST );
+REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE         , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MANUAL_RECAL_LANE );
+REG64_FLD( OBUS_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE_LEN     , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MANUAL_RECAL_LANE_LEN );
+
+REG64_FLD( OBUS_RX0_RX_GLBSM_CNTLX1_EO_PG_CLR_PAR_ERRS             , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CLR_PAR_ERRS );
+REG64_FLD( OBUS_RX0_RX_GLBSM_CNTLX1_EO_PG_FIR_RESET                , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIR_RESET  );
+
+REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_0                       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_1                       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_2                       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_3                       , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_4                       , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_5                       , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_6                       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_RX_GLBSM_SPARE_MODE_PG_7                       , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_RX_ID1_PG_BUS_ID                               , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ID     );
+REG64_FLD( OBUS_RX0_RX_ID1_PG_BUS_ID_LEN                           , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ID_LEN );
+
+REG64_FLD( OBUS_RX0_RX_SPARE_MODE_PG_0                             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_RX_SPARE_MODE_PG_1                             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_RX_SPARE_MODE_PG_2                             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_RX_SPARE_MODE_PG_3                             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_RX_SPARE_MODE_PG_4                             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+
+REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE0_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE0_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE10_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE10_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE11_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE11_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE12_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE12_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE13_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE13_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE14_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE14_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE15_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE15_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE16_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE16_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE17_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE17_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE18_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE18_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE19_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE19_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE1_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE1_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE20_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE20_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE21_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE21_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE22_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE22_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_0           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_1           , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_2           , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_3           , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_4           , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_5           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_6           , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_7           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL       , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE23_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED   , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_CNTL1_O_PL_REGS_IORESET        , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BIST_ERR_A         , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BIST_ERR_B         , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BIST_ERR_E         , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV     , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_AP               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_AP_LEN           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD     , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE23_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE2_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE2_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE3_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE3_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE4_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE4_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE5_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE5_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE6_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE6_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE7_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE7_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE8_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE8_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_0            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_1            , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_2            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_3            , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_4            , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_5            , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_6            , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_7            , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_RUN_LANE         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_LANE   );
+REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_RUN_DCCAL        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DCCAL  );
+REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_RECAL_REQ        , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_REQ  );
+REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_RECAL_ABORT      , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ABORT );
+REG64_FLD( OBUS_RX0_SLICE9_RX_GLBSM_PL_CNTL1_O_PL_LANE_DISABLED    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED );
+
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_CNTL1_O_PL_REGS_IORESET         , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REGS_IORESET );
+
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BIST_ERR_A          , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_A );
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BIST_ERR_B          , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_B );
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BIST_ERR_E          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR_E );
+
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT2_EO_PL_B_BAD_DFE_CONV      , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_BAD_DFE_CONV );
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT     , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT2_EO_PL_B_H1AP_AT_LIMIT     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_H1AP_AT_LIMIT );
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_AP                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_AP_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN );
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT4_O_PL_B_PATH_OFF_EVEN_LEN  , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_EVEN_LEN );
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD       , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD );
+REG64_FLD( OBUS_RX0_SLICE9_RX_WORK_STAT4_O_PL_B_PATH_OFF_ODD_LEN   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_B_PATH_OFF_ODD_LEN );
+
+REG64_FLD( OBUS_RX_FIR_ERROR_INJECT_PB_ERRS_INJ                    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_INJ   );
+REG64_FLD( OBUS_RX_FIR_ERROR_INJECT_PB_ERRS_INJ_LEN                , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_INJ_LEN );
+
+REG64_FLD( OBUS_RX_FIR_MASK_PB_ERRS                                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_RX_FIR_MASK_PB_ERRS_LEN                            , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( OBUS_RX_FIR_RESET_PB_CLR_PAR_ERRS                       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CLR_PAR_ERRS );
+REG64_FLD( OBUS_RX_FIR_RESET_PB_RESET                              , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESET      );
+
+REG64_FLD( OBUS_SCOM_MODE_PB_GCR_TEST                              , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_GCR_TEST   );
+REG64_FLD( OBUS_SCOM_MODE_PB_ENABLE_GCR_OFL_BUFF                   , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_GCR_OFL_BUFF );
+REG64_FLD( OBUS_SCOM_MODE_PB_IORESET_HARD_BUS0                     , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET_HARD_BUS0 );
+REG64_FLD( OBUS_SCOM_MODE_PB_MMIO_PG_REG_ACCESS                    , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MMIO_PG_REG_ACCESS );
+REG64_FLD( OBUS_SCOM_MODE_PB_SPARES1                               , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARES1    );
+REG64_FLD( OBUS_SCOM_MODE_PB_SPARES1_LEN                           , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARES1_LEN );
+REG64_FLD( OBUS_SCOM_MODE_PB_GCR_HANG_DET_SEL                      , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_GCR_HANG_DET_SEL );
+REG64_FLD( OBUS_SCOM_MODE_PB_GCR_HANG_DET_SEL_LEN                  , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_GCR_HANG_DET_SEL_LEN );
+REG64_FLD( OBUS_SCOM_MODE_PB_GCR_BUFFER_ENABLED_RO_SIGNAL          , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_GCR_BUFFER_ENABLED_RO_SIGNAL );
+REG64_FLD( OBUS_SCOM_MODE_PB_GCR_HANG_ERROR_MASK                   , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_GCR_HANG_ERROR_MASK );
+REG64_FLD( OBUS_SCOM_MODE_PB_GCR_HANG_ERROR_INJ                    , 13  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_GCR_HANG_ERROR_INJ );
+REG64_FLD( OBUS_SCOM_MODE_PB_PPE_GCR                               , 14  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PPE_GCR    );
+REG64_FLD( OBUS_SCOM_MODE_PB_CHAN_FAIL_MASK                        , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CHAN_FAIL_MASK );
+REG64_FLD( OBUS_SCOM_MODE_PB_CHAN_FAIL_MASK_LEN                    , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CHAN_FAIL_MASK_LEN );
+REG64_FLD( OBUS_SCOM_MODE_PB_SPARES2                               , 23  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARES2    );
+REG64_FLD( OBUS_SCOM_MODE_PB_SPARES2_LEN                           , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARES2_LEN );
+
+REG64_FLD( OBUS_SPARE_MODE_PB_0                                    , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_SPARE_MODE_PB_1                                    , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_SPARE_MODE_PB_2                                    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_SPARE_MODE_PB_3                                    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_SPARE_MODE_PB_4                                    , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_SPARE_MODE_PB_5                                    , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_SPARE_MODE_PB_6                                    , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_SPARE_MODE_PB_7                                    , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN );
+REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_RESERVED_LAST_LT               , 17  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LAST_LT );
+REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR );
+REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN );
+REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY );
+REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR );
+REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION );
+REG64_FLD( OBUS_TCOB0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER );
+
+REG64_FLD( OBUS_TCOB0_ATOMIC_LOCK_MASK_LATCH_REG_MASK              , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MASK       );
+REG64_FLD( OBUS_TCOB0_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN          , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND1_SEL_A             , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND1_SEL_B             , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND2_SEL_A             , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND2_SEL_B             , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_C1_INAROW_MODE          , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1       , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1       , 34  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1      , 35  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_UNUSED                  , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_UNUSED_LEN              , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_C2_INAROW_MODE          , 39  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2       , 40  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2       , 41  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2      , 42  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_UNUSED_2                , 43  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_UNUSED_2_LEN            , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET      , 46  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_EXACT_TO_MODE           , 47  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_RESET_C3_ON_C0          , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_SLOW_TO_MODE            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_C1_COUNT_LT             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_C2_COUNT_LT             , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_RESET_C3_SELECT         , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A   , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B   , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_TO_CMP_LT               , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN           , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_2_FORCE_TEST_MODE         , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_3_SP_COUNT_LT             , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( OBUS_TCOB0_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN         , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND1_SEL_A             , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND1_SEL_B             , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND2_SEL_A             , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND2_SEL_B             , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_C1_INAROW_MODE          , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1       , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1       , 34  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1      , 35  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_UNUSED                  , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_UNUSED_LEN              , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_C2_INAROW_MODE          , 39  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2       , 40  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2       , 41  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2      , 42  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_UNUSED_2                , 43  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_UNUSED_2_LEN            , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET      , 46  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_EXACT_TO_MODE           , 47  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1     , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_RESET_C3_ON_C0          , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_SLOW_TO_MODE            , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO    , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_C1_COUNT_LT             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_C2_COUNT_LT             , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_RESET_C3_SELECT         , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A   , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B   , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_TO_CMP_LT               , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN           , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_2_FORCE_TEST_MODE         , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_3_SP_COUNT_LT             , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( OBUS_TCOB0_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN         , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_GLB_BRCST                       , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST  );
+REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_GLB_BRCST_LEN                   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_TRACE_SEL                       , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SEL  );
+REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_TRIG_SEL                        , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRIG_SEL   );
+REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_XSTOP_SELECTION );
+REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION     , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_RECOV_ERR_SELECTION );
+REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION        , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_SPATTN_SELECTION );
+REG64_FLD( OBUS_TCOB0_DBG_MODE_REG_FREEZE_SEL                      , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_SEL );
+
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_IMM_FREEZE              , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IMM_FREEZE );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_STOP_ON_ERR             , 17  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_ERR );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH      , 18  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BANK_ON_RUNN_MATCH );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_FORCE_TEST              , 19  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_ACCUM_HIST              , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACCUM_HIST );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ        , 21  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRZ_COUNT_ON_FRZ );
+
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_COND3_ENABLE           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_COND3_ENABLE );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_COND3_ENABLE           , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_COND3_ENABLE );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST3_COND3_ENABLE           , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST3_COND3_ENABLE );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST4_COND3_ENABLE           , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST4_COND3_ENABLE );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE         , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_SLOW_LFSR_MODE );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE         , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_SLOW_LFSR_MODE );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE         , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST3_SLOW_LFSR_MODE );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE         , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST4_SLOW_LFSR_MODE );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL    , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL    , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL    , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL    , 14  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL    , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL    , 18  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP             , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_STOP );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE           , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_FREEZE );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL           , 34  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN       , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL           , 39  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN       , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL               , 44  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN           , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_ARM_SEL                      , 46  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL    );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_ARM_SEL_LEN                  , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL              , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL              , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN          , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL_LEN );
+
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO   , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO   , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO   , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO   , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO   , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_WAITN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_WAITN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_WAITN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_WAITN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_BANK );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_BANK );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_BANK );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_BANK );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN  , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT      , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN  , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( OBUS_TCOB0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR );
+
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PCB_WDATA_PARITY            , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PCB_WDATA_PARITY );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY          , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_PARITY );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY      , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_WDATA_PARITY );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_DL_RETURN_P0                , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_P0 );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_UL_RDATA_PARITY             , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UL_RDATA_PARITY );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_UL_P0                       , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UL_P0      );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE       , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_P2S_MACHINE );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD         , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_WRITE_NVLD );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD          , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_READ_NVLD );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID       , 13  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_ADDR_INVALID );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY          , 14  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PCB_COMMAND_PARITY );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_GENERAL_TIMEOUT             , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_GENERAL_TIMEOUT );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( OBUS_TCOB0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR );
+REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR );
+REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR );
+REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR );
+REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_WATCHDOG_ENABLE               , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_WATCHDOG_ENABLE );
+REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_SCOM_HANG_LIMIT               , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT );
+REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN           , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT_LEN );
+REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_FORCE_ALL_RINGS               , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ALL_RINGS );
+REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE );
+REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_RESERVED_LT                   , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT );
+REG64_FLD( OBUS_TCOB0_PSCOM_MODE_REG_RESERVED_LT_LEN               , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT_LEN );
+
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_WDATA_PARITY );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_P0 );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_RDATA_PARITY );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0     , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_P0 );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   ,
+           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_GENERAL_TIMEOUT );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  ,
+           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  ,
+           SH_UNT_OBUS     , SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_WDATA_PARITY );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_ADDRESS_PARITY );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0  , 21  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_P0 );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_RDATA_PARITY );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0         , 23  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_P0 );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_READ_NVLD );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_COMMAND_PARITY );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_GENERAL_TIMEOUT );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( OBUS_TCOB0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( OBUS_TCOB0_RING_FENCE_MASK_LATCH_REG_DISABLED           , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED   );
+REG64_FLD( OBUS_TCOB0_RING_FENCE_MASK_LATCH_REG_ENABLE             , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( OBUS_TCOB0_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN         , 15  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_HI_DATA_REG_DATA              , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN          , 64  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_DATA              , 0   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN          , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS           , 32  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN       , 10  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK         , 42  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN     , 9   , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID   , 51  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN      , 52  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING           , 53  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN  , 10  , SH_UNT_OBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA      , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB      , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC      , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND      , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN  , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA         , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN     , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB         , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN     , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC         , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN     , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD         , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN     , 24  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_OBUS     ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( OBUS_TCOB0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( OBUS_TCOB0_WRITE_PROTECT_ENABLE_REG_RING_LOCKING        , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RING_LOCKING );
+REG64_FLD( OBUS_TCOB0_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_RING_LOCKING );
+
+REG64_FLD( OBUS_TCOB0_WRITE_PROTECT_RINGS_REG_RINGS                , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RINGS      );
+REG64_FLD( OBUS_TCOB0_WRITE_PROTECT_RINGS_REG_RINGS_LEN            , 16  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RINGS_LEN  );
+
+REG64_FLD( OBUS_TCOB0_XTRA_TRACE_MODE_DATA                         , 0   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DATA       );
+REG64_FLD( OBUS_TCOB0_XTRA_TRACE_MODE_DATA_LEN                     , 38  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS4_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_CNTL2_O_PL_IORESET          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_FIR_MASK_PL_ERRS            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_LANE_PDWN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_LANE_INVERT        , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_LANE_QUIESCE       , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN   , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_PSAVE_REQ_DIS      , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_REQ_DIS );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE   , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE   , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_SPARE_MODE_0       , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_SPARE_MODE_1       , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_SPARE_MODE_2       , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE1_PL_SPARE_MODE_3       , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY       , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN   , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_RXCAL              , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_UNLOAD_SEL         , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN     , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_LANE_BIST_ERR      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( OBUS_TX0_TXPACKS5_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN               , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_PRE_EN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN_LEN           , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_PRE_EN_LEN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_PRE_SEL );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL_LEN          , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_PRE_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_O_PG_PSEG_POST_EN               , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_POST_EN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_O_PG_PSEG_POST_EN_LEN           , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_POST_EN_LEN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_O_PG_PSEG_POST_SEL              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_POST_SEL );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL1_O_PG_PSEG_POST_SEL_LEN          , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_POST_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN               , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_PRE_EN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN_LEN           , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_PRE_EN_LEN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_PRE_SEL );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL_LEN          , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_PRE_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_O_PG_NSEG_POST_EN               , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_POST_EN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_O_PG_NSEG_POST_EN_LEN           , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_POST_EN_LEN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_O_PG_NSEG_POST_SEL              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_POST_SEL );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL2_O_PG_NSEG_POST_SEL_LEN          , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_POST_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MARGINPU_EN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN_LEN      , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MARGINPU_EN_LEN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN          , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MARGINPD_EN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN_LEN      , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MARGINPD_EN_LEN );
+
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MARGINPU_EN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN_LEN      , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MARGINPU_EN_LEN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN          , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MARGINPD_EN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN_LEN      , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MARGINPD_EN_LEN );
+
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL              , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MARGINPU_SEL );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL_LEN          , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MARGINPU_SEL_LEN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL              , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MARGINPD_SEL );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL_LEN          , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MARGINPD_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN              , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MAIN_EN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN_LEN          , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MAIN_EN_LEN );
+
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN              , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MAIN_EN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN_LEN          , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MAIN_EN_LEN );
+
+REG64_FLD( OBUS_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_MODE );
+REG64_FLD( OBUS_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE_LEN         , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_MODE_LEN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_MODE1_EO_PG_FFE_BOOST_EN              , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FFE_BOOST_EN );
+REG64_FLD( OBUS_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_LEAKAGE_CTRL     , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_LEAKAGE_CTRL );
+
+REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_0                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_0   );
+REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_1                , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_1   );
+REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_2                , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_2   );
+REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_3                , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_3   );
+REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_4                , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_4   );
+REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_5                , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_5   );
+REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_6                , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_6   );
+REG64_FLD( OBUS_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_7                , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_7   );
+
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_PULSE_WIDTH );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH_LEN        , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_PULSE_WIDTH_LEN );
+
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_FINE_SEL );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL_LEN      , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_FINE_SEL_LEN );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL        , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_COARSE_SEL );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL_LEN    , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_COARSE_SEL_LEN );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_BER_SEL );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL_LEN       , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_BER_SEL_LEN );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_ENABLE              , 61  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_ENABLE );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_CLOCK_ENABLE        , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_CLOCK_ENABLE );
+
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL          , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_FINE_SEL );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL_LEN      , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_FINE_SEL_LEN );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL        , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_COARSE_SEL );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL_LEN    , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_COARSE_SEL_LEN );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL           , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_BER_SEL );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL_LEN       , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_BER_SEL_LEN );
+
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_DAC_CNTL );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL_LEN            , 8   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_DAC_CNTL_LEN );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL8_EO_PG_TDR_PHASE_SEL               , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_PHASE_SEL );
+
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_PULSE_OFFSET );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET_LEN        , 14  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDR_PULSE_OFFSET_LEN );
+
+REG64_FLD( OBUS_TX0_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG    , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DRV_DATA_PATTERN_GCRMSG );
+REG64_FLD( OBUS_TX0_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG_LEN , 4   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DRV_DATA_PATTERN_GCRMSG_LEN );
+
+REG64_FLD( OBUS_TX0_TX_CTL_MODE1_EO_PG_CLKDIST_PDWN                , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CLKDIST_PDWN );
+REG64_FLD( OBUS_TX0_TX_CTL_MODE1_EO_PG_CLKDIST_PDWN_LEN            , 3   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CLKDIST_PDWN_LEN );
+REG64_FLD( OBUS_TX0_TX_CTL_MODE1_EO_PG_BIST_EN                     , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EN    );
+REG64_FLD( OBUS_TX0_TX_CTL_MODE1_EO_PG_EXBIST_MODE                 , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_EXBIST_MODE );
+
+REG64_FLD( OBUS_TX0_TX_FIR_ERROR_INJECT_PG_ERR_INJ                 , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( OBUS_TX0_TX_FIR_ERROR_INJECT_PG_ERR_INJ_LEN             , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( OBUS_TX0_TX_FIR_MASK_PG_ERRS                            , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( OBUS_TX0_TX_FIR_MASK_PG_ERRS_LEN                        , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+REG64_FLD( OBUS_TX0_TX_FIR_MASK_PG_PL_ERR                          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PL_ERR     );
+
+REG64_FLD( OBUS_TX0_TX_FIR_RESET_PG_CLR_PAR_ERRS                   , 62  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CLR_PAR_ERRS );
+REG64_FLD( OBUS_TX0_TX_FIR_RESET_PG_RESET                          , 63  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESET      );
+
+REG64_FLD( OBUS_TX0_TX_ID1_PG_BUS_ID                               , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ID     );
+REG64_FLD( OBUS_TX0_TX_ID1_PG_BUS_ID_LEN                           , 6   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ID_LEN );
+
+REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_0                             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_1                             , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_2                             , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_3                             , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_4                             , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_5                             , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_6                             , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_7                             , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_8_9                           , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_8_9        );
+REG64_FLD( OBUS_TX0_TX_SPARE_MODE_PG_8_9_LEN                       , 2   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_8_9_LEN    );
+
+REG64_FLD( OBUS_TX_IMPCAL_NVAL_PB_ZCAL_N                           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_N     );
+REG64_FLD( OBUS_TX_IMPCAL_NVAL_PB_ZCAL_N_LEN                       , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_N_LEN );
+
+REG64_FLD( OBUS_TX_IMPCAL_PVAL_PB_ZCAL_P                           , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_P     );
+REG64_FLD( OBUS_TX_IMPCAL_PVAL_PB_ZCAL_P_LEN                       , 9   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_P_LEN );
+
+REG64_FLD( OBUS_TX_IMPCAL_P_4X_PB_ZCAL                             , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL       );
+REG64_FLD( OBUS_TX_IMPCAL_P_4X_PB_ZCAL_LEN                         , 5   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_LEN   );
+
+REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_SWO_EN                      , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SWO_EN );
+REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CAL_SEGS                , 49  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SWO_CAL_SEGS );
+REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_INV                 , 50  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SWO_CMP_INV );
+REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_OFFSET              , 51  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SWO_CMP_OFFSET );
+REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_RESET               , 52  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SWO_CMP_RESET );
+REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_SWO_POWERDOWN               , 53  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SWO_POWERDOWN );
+REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_SWO_TCOIL                   , 54  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SWO_TCOIL );
+REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_RANGE_CHECK                 , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_RANGE_CHECK );
+REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_CYA_DATA_INV                , 56  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_CYA_DATA_INV );
+REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_2R                 , 57  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_TEST_OVR_2R );
+REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_1R                 , 58  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_TEST_OVR_1R );
+REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_4X_SEG             , 59  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_TEST_OVR_4X_SEG );
+REG64_FLD( OBUS_TX_IMPCAL_SWO1_PB_ZCAL_TEST_CLK_DIV                , 60  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_TEST_CLK_DIV );
+
+REG64_FLD( OBUS_TX_IMPCAL_SWO2_PB_ZCAL_SM_MIN_VAL                  , 48  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SM_MIN_VAL );
+REG64_FLD( OBUS_TX_IMPCAL_SWO2_PB_ZCAL_SM_MIN_VAL_LEN              , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SM_MIN_VAL_LEN );
+REG64_FLD( OBUS_TX_IMPCAL_SWO2_PB_ZCAL_SM_MAX_VAL                  , 55  , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SM_MAX_VAL );
+REG64_FLD( OBUS_TX_IMPCAL_SWO2_PB_ZCAL_SM_MAX_VAL_LEN              , 7   , SH_UNT_OBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SM_MAX_VAL_LEN );
+
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9_obus_scom_addresses_fld_fixes.H b/src/import/chips/p9/common/include/p9_obus_scom_addresses_fld_fixes.H
new file mode 100644
index 00000000..41b4ad89
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_obus_scom_addresses_fld_fixes.H
@@ -0,0 +1,48 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_obus_scom_addresses_fld_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file obus_scom_addresses_fld_fixes.H
+/// @brief The *scom_addresses_fld.H files are generated form figtree,
+///        but the figree can be wrong.  This file is included in
+///        *_scom_addresses_fld.H and allows incorrect constants to be
+///        fixed manually.
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SAO
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __P9_OBUS_SCOM_ADDRESSES_FLD_FIXES_H
+#define __P9_OBUS_SCOM_ADDRESSES_FLD_FIXES_H
+
+//Example
+//Copy the whole line from the *scom_addresses_fld.H file.  Then add FIX in front of REG
+//and add another paramter that is the new value you want.
+//
+//FIXREG64_FLD( PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE, 24, SH_UNT, SH_ACS_SCOM, SH_FLD_FBC_WITH_TM_QUIESCE,
+//              12);
+
+#endif
diff --git a/src/import/chips/p9/common/include/p9_perv_scom_addresses.H b/src/import/chips/p9/common/include/p9_perv_scom_addresses.H
new file mode 100644
index 00000000..d418ad7c
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_perv_scom_addresses.H
@@ -0,0 +1,10253 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_perv_scom_addresses.H $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_perv_scom_addresses.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+/*---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ *
+ *  Issues:
+ *
+ * Closed
+ *    TOD reg same address.             HW323439
+ *       - Issue was closed with the explaination "same as p8"
+ *    IO0 registers need fixed.         HW320437
+ *    PHB registers need fixed.         HW320416  ( all regs commented out now )
+ *    OSC/perv regs same address.       HW323437
+ *    MC regs with same address.        HW323435 (matteo)
+ *         Duplicate IOM registers.          HW320456 (designers)
+ *    PEC Sat_id issue                  HW329652
+ *    PB.PB_PPE registers need fixed.   HW320435
+ *    EX05 registers need fixed.        HW320427  (9020) - L2 ring id's are incorrect
+ *    IOFPPE registers need fixed.      HW320424  (9020) - Investigate NULL scope
+ *    PEC addresses are wrong.          HW322598  (9020)
+ *    MC registers need fixed.          HW320433
+ *    VA.VA_NORTH registers need fixed. HW320436
+ *
+ * Format:
+ *
+ *  <UNIT>_<SUBUNIT>_<INSTANCE>_<REGISTER>_<ACCESS/TYPE>
+ *
+ *  Notes: Subunits are only added to make names unique when
+ *  there are name collisions.
+ *  Only units with more than one instance has instance numbers.
+ *  If there is only one, the instance number is omitted.
+ *
+ *  Instance numbers are chiplet id's for the PERV unit.  The
+ *  chiplet id's are mapped to their name and used instead of
+ *  instance numbers.  See bellow.
+ *
+ *  For registers with a single access type the type and access
+ *  methods are omitted.
+ *
+ *  For access types where all bits have the same access methods, the
+ *  access method is appended to the name.  If the access methods
+ *  are different for some bits, the access type is appended to the
+ *  name _SCOM instead of _RO.  The _RW(X) access method is omitted
+ *  and assumed to be default.
+ *
+ *  Valid units / subunits
+ *    PU                    : No unit chip level
+ *        MCD0[0..1]        : mcd subunit
+ *        PIB2OPB[0..1]     : PIB2OPB subunit
+ *        OTPROM[0..1]      : otprom subunit
+ *        NPU               : common npu subunit
+ *        NPU[0..2]         : Npu stacks 0 to 2
+ *          CTL             : Npu CTL subunit
+ *          DAT             : Npu DAT subunit
+ *          SM[0..3]        : Npu SM subunits
+ *          NTL[0..1]       : Npu NTL subunit
+ *    PERV                  : Pervasive
+ *        FSI2PIB           : subunit
+ *        FSISHIFT          : subunit
+ *        FSII2C            : subunit
+ *        FSB               : subunit
+ *    EX                    : Ex unit (1/2 quad, 2 cores)
+ *        L2                : L2 subunit
+ *        L3                : L3 subunit
+ *    PEC                   : PCI Pec unit
+ *        STACK0            : subunit
+ *        STACK1            : subunit
+ *        STACK2            : subunit
+ *    C                     : core
+ *    EQ                    : quad
+ *    OBUS                  : obus
+ *    CAPP                  : capp
+ *    MCBIST                : mcbist
+ *    MCA                   : mca
+ *    NVBUS                 : (not implemented yet)
+ *    PHB                   : (not implemented yet)
+ *    MI                    : (not implemented yet)
+ *    DMI                   : (not implemented yet)
+ *    MCS                   : (not implemented yet)
+ *    OCC                   : (not implemented yet)
+ *    PPE                   : (not implemented yet)
+ *    SBE                   : (not implemented yet)
+ *    XBUS                  : (not implemented yet)
+ *
+ * Pervasive instance names follow chiplet id.
+ *
+ * Instance/  | Chiplet
+ * Chiplet    | name
+ * -----------+-----------
+ * 0x00       | PIB
+ * 0x01       | TP
+ * 0x02       | N0
+ * 0x03       | N1
+ * 0x04       | N2
+ * 0x05       | N3
+ * 0x06       | XB
+ * 0x07       | MC01
+ * 0x08       | MC23
+ * 0x09       | OB0
+ * 0x0A       | OB1
+ * 0x0B       | OB2
+ * 0x0C       | OB3
+ * 0x0D       | PCI0
+ * 0x0E       | PCI1
+ * 0x0F       | PCI2
+ * 0x10       | EP00
+ * 0x11       | EP01
+ * 0x12       | EP02
+ * 0x13       | EP03
+ * 0x14       | EP04
+ * 0x15       | EP05
+ * 0x20       | EC00
+ * 0x21       | EC01
+ * 0x22       | EC02
+ * 0x23       | EC03
+ * 0x24       | EC04
+ * 0x25       | EC05
+ * 0x26       | EC06
+ * 0x27       | EC07
+ * 0x28       | EC08
+ * 0x29       | EC09
+ * 0x2A       | EC10
+ * 0x2B       | EC11
+ * 0x2C       | EC12
+ * 0x2D       | EC13
+ * 0x2E       | EC14
+ * 0x2F       | EC15
+ * 0x30       | EC16
+ * 0x31       | EC17
+ * 0x32       | EC18
+ * 0x33       | EC19
+ * 0x34       | EC20
+ * 0x35       | EC21
+ * 0x36       | EC22
+ * 0x37       | EC23
+ *
+ *
+ *---------------------------------------------------------------
+ *
+ * NOTES:
+ *
+ * there is a SPR ring that goes around the chip with an
+ * address(0:9)/tid(0:1) (thread id)/mfspr_data(0:63) and return mfspr_data_v/mfspr_data(0:63)
+ *
+ *    Add PU_<SUBUNITS>  (only if there are conflicts on these registers)
+ *       0x0001XXXX OTPROM
+ *       0x0002XXXX FSIM0
+ *       0x0003XXXX FSIM1
+ *       0x0004XXXX TOD
+ *       0x0005XXXX FSI_MBOX
+ *       0x0006XXXX OCI_BRIDGE
+ *       0x0007XXXX SPI_ADC
+ *       0x0008XXXX PIBMEM
+ *       0x0009XXXX ADU
+ *       0x000AXXXX I2CM
+ *       0x000BXXXX SBE_FIFO
+ *       0x000DXXXX PSU
+ *       0x000EXXXX SBE
+ *
+ * 0x0000100A for FSI2PIB  => PERV_FSI2PIB
+ * 0x00000Cxx for FSISHIFT =>  PERV_FSISHIFT
+ * 0x000018xx for FSI I2C =>  PERV_FSII2C
+ * 0x000024xx for FSI SBEFIFO => PERV_FSB
+ *
+ * 0x00000400 PEEK_TABLE
+ * 0x00000800 FSI_SLAVE
+ * 0x00000C00 FSI_SHIFT
+ * 0x00001000 FSI2PIB
+ * 0x00001400 FSI_SCRATCHPAD
+ * 0x00001800 FSI_I2CM
+ * 0x00002400 FSI_SBE_FIFO
+ *
+ * address fields
+ * 0xCCRPxxxx
+ *
+ * CC=chiplet
+ * R=always 0?
+ * P=port
+ *   0=gpregs
+ *   1=normal unit scom ring (exclude)
+ *   3=clock controller
+ *   4=firs
+ *   5=cpm
+ *
+ * =============================================================================
+ * Compiling
+ *
+ * Precompile the header to save time on subsquent compiles:
+ * g++ -I. -c scom_addresses.H
+ *
+ * Use these options to help reduce the binary size
+ * g++ -I. -Os -fdata-sections -ffunction-sections <file>.C -o <output> -Wl,--gc-sections
+ *
+ *
+ *---------------------------------------------------------------
+ */
+
+#include <p9_const_common.H>
+
+
+#ifndef __P9_PERV_SCOM_ADDRESSES_H
+#define __P9_PERV_SCOM_ADDRESSES_H
+
+
+#include <p9_scom_template_consts.H>
+#include <p9_perv_scom_addresses_fixes.H>
+
+
+REG64( PERV_ADDR_TRAP_REG                                      , RULL(0x00010003), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_ADDR_TRAP_REG                                   , RULL(0x01010003), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_ASSIST_INTERRUPT_REG                               , RULL(0x000F0011), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_ASSIST_INTERRUPT_REG                            , RULL(0x010F0011), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_ASSIST_INTERRUPT_REG                            , RULL(0x020F0011), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_ASSIST_INTERRUPT_REG                            , RULL(0x030F0011), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_ASSIST_INTERRUPT_REG                            , RULL(0x040F0011), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_ASSIST_INTERRUPT_REG                            , RULL(0x050F0011), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_ASSIST_INTERRUPT_REG                            , RULL(0x060F0011), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_ASSIST_INTERRUPT_REG                          , RULL(0x070F0011), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_ASSIST_INTERRUPT_REG                          , RULL(0x080F0011), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_ASSIST_INTERRUPT_REG                           , RULL(0x090F0011), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_ASSIST_INTERRUPT_REG                           , RULL(0x0C0F0011), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_ASSIST_INTERRUPT_REG                          , RULL(0x0D0F0011), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_ASSIST_INTERRUPT_REG                          , RULL(0x0E0F0011), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_ASSIST_INTERRUPT_REG                          , RULL(0x0F0F0011), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_ASSIST_INTERRUPT_REG                          , RULL(0x100F0011), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_ASSIST_INTERRUPT_REG                          , RULL(0x110F0011), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_ASSIST_INTERRUPT_REG                          , RULL(0x120F0011), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_ASSIST_INTERRUPT_REG                          , RULL(0x130F0011), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_ASSIST_INTERRUPT_REG                          , RULL(0x140F0011), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_ASSIST_INTERRUPT_REG                          , RULL(0x150F0011), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_ASSIST_INTERRUPT_REG                          , RULL(0x200F0011), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_ASSIST_INTERRUPT_REG                          , RULL(0x210F0011), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_ASSIST_INTERRUPT_REG                          , RULL(0x220F0011), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_ASSIST_INTERRUPT_REG                          , RULL(0x230F0011), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_ASSIST_INTERRUPT_REG                          , RULL(0x240F0011), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_ASSIST_INTERRUPT_REG                          , RULL(0x250F0011), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_ASSIST_INTERRUPT_REG                          , RULL(0x260F0011), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_ASSIST_INTERRUPT_REG                          , RULL(0x270F0011), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_ASSIST_INTERRUPT_REG                          , RULL(0x280F0011), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_ASSIST_INTERRUPT_REG                          , RULL(0x290F0011), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_ASSIST_INTERRUPT_REG                          , RULL(0x2A0F0011), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_ASSIST_INTERRUPT_REG                          , RULL(0x2B0F0011), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_ASSIST_INTERRUPT_REG                          , RULL(0x2C0F0011), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_ASSIST_INTERRUPT_REG                          , RULL(0x2D0F0011), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_ASSIST_INTERRUPT_REG                          , RULL(0x2E0F0011), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_ASSIST_INTERRUPT_REG                          , RULL(0x2F0F0011), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_ASSIST_INTERRUPT_REG                          , RULL(0x300F0011), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_ASSIST_INTERRUPT_REG                          , RULL(0x310F0011), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_ASSIST_INTERRUPT_REG                          , RULL(0x320F0011), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_ASSIST_INTERRUPT_REG                          , RULL(0x330F0011), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_ASSIST_INTERRUPT_REG                          , RULL(0x340F0011), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_ASSIST_INTERRUPT_REG                          , RULL(0x350F0011), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_ASSIST_INTERRUPT_REG                          , RULL(0x360F0011), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_ASSIST_INTERRUPT_REG                          , RULL(0x370F0011), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x00010007), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_ATOMIC_LOCK_MASK_LATCH_REG                      , RULL(0x01010007), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_ATOMIC_LOCK_REG                                    , RULL(0x000F03FF), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_ATOMIC_LOCK_REG                                 , RULL(0x010F03FF), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_ATOMIC_LOCK_REG                                 , RULL(0x020F03FF), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_ATOMIC_LOCK_REG                                 , RULL(0x030F03FF), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_ATOMIC_LOCK_REG                                 , RULL(0x040F03FF), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_ATOMIC_LOCK_REG                                 , RULL(0x050F03FF), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_ATOMIC_LOCK_REG                                 , RULL(0x060F03FF), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_ATOMIC_LOCK_REG                               , RULL(0x070F03FF), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_ATOMIC_LOCK_REG                               , RULL(0x080F03FF), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_ATOMIC_LOCK_REG                                , RULL(0x090F03FF), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_ATOMIC_LOCK_REG                                , RULL(0x0C0F03FF), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_ATOMIC_LOCK_REG                               , RULL(0x0D0F03FF), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_ATOMIC_LOCK_REG                               , RULL(0x0E0F03FF), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_ATOMIC_LOCK_REG                               , RULL(0x0F0F03FF), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_ATOMIC_LOCK_REG                               , RULL(0x100F03FF), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_ATOMIC_LOCK_REG                               , RULL(0x110F03FF), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_ATOMIC_LOCK_REG                               , RULL(0x120F03FF), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_ATOMIC_LOCK_REG                               , RULL(0x130F03FF), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_ATOMIC_LOCK_REG                               , RULL(0x140F03FF), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_ATOMIC_LOCK_REG                               , RULL(0x150F03FF), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_ATOMIC_LOCK_REG                               , RULL(0x200F03FF), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_ATOMIC_LOCK_REG                               , RULL(0x210F03FF), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_ATOMIC_LOCK_REG                               , RULL(0x220F03FF), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_ATOMIC_LOCK_REG                               , RULL(0x230F03FF), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_ATOMIC_LOCK_REG                               , RULL(0x240F03FF), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_ATOMIC_LOCK_REG                               , RULL(0x250F03FF), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_ATOMIC_LOCK_REG                               , RULL(0x260F03FF), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_ATOMIC_LOCK_REG                               , RULL(0x270F03FF), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_ATOMIC_LOCK_REG                               , RULL(0x280F03FF), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_ATOMIC_LOCK_REG                               , RULL(0x290F03FF), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_ATOMIC_LOCK_REG                               , RULL(0x2A0F03FF), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_ATOMIC_LOCK_REG                               , RULL(0x2B0F03FF), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_ATOMIC_LOCK_REG                               , RULL(0x2C0F03FF), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_ATOMIC_LOCK_REG                               , RULL(0x2D0F03FF), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_ATOMIC_LOCK_REG                               , RULL(0x2E0F03FF), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_ATOMIC_LOCK_REG                               , RULL(0x2F0F03FF), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_ATOMIC_LOCK_REG                               , RULL(0x300F03FF), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_ATOMIC_LOCK_REG                               , RULL(0x310F03FF), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_ATOMIC_LOCK_REG                               , RULL(0x320F03FF), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_ATOMIC_LOCK_REG                               , RULL(0x330F03FF), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_ATOMIC_LOCK_REG                               , RULL(0x340F03FF), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_ATOMIC_LOCK_REG                               , RULL(0x350F03FF), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_ATOMIC_LOCK_REG                               , RULL(0x360F03FF), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_ATOMIC_LOCK_REG                               , RULL(0x370F03FF), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_ATTN_INTERRUPT_REG                                 , RULL(0x000F001A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_ATTN_INTERRUPT_REG                              , RULL(0x010F001A), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_ATTN_INTERRUPT_REG                              , RULL(0x020F001A), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_ATTN_INTERRUPT_REG                              , RULL(0x030F001A), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_ATTN_INTERRUPT_REG                              , RULL(0x040F001A), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_ATTN_INTERRUPT_REG                              , RULL(0x050F001A), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_ATTN_INTERRUPT_REG                              , RULL(0x060F001A), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_ATTN_INTERRUPT_REG                            , RULL(0x070F001A), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_ATTN_INTERRUPT_REG                            , RULL(0x080F001A), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_ATTN_INTERRUPT_REG                             , RULL(0x090F001A), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_ATTN_INTERRUPT_REG                             , RULL(0x0C0F001A), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_ATTN_INTERRUPT_REG                            , RULL(0x0D0F001A), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_ATTN_INTERRUPT_REG                            , RULL(0x0E0F001A), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_ATTN_INTERRUPT_REG                            , RULL(0x0F0F001A), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_ATTN_INTERRUPT_REG                            , RULL(0x100F001A), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_ATTN_INTERRUPT_REG                            , RULL(0x110F001A), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_ATTN_INTERRUPT_REG                            , RULL(0x120F001A), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_ATTN_INTERRUPT_REG                            , RULL(0x130F001A), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_ATTN_INTERRUPT_REG                            , RULL(0x140F001A), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_ATTN_INTERRUPT_REG                            , RULL(0x150F001A), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_ATTN_INTERRUPT_REG                            , RULL(0x200F001A), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_ATTN_INTERRUPT_REG                            , RULL(0x210F001A), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_ATTN_INTERRUPT_REG                            , RULL(0x220F001A), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_ATTN_INTERRUPT_REG                            , RULL(0x230F001A), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_ATTN_INTERRUPT_REG                            , RULL(0x240F001A), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_ATTN_INTERRUPT_REG                            , RULL(0x250F001A), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_ATTN_INTERRUPT_REG                            , RULL(0x260F001A), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_ATTN_INTERRUPT_REG                            , RULL(0x270F001A), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_ATTN_INTERRUPT_REG                            , RULL(0x280F001A), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_ATTN_INTERRUPT_REG                            , RULL(0x290F001A), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_ATTN_INTERRUPT_REG                            , RULL(0x2A0F001A), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_ATTN_INTERRUPT_REG                            , RULL(0x2B0F001A), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_ATTN_INTERRUPT_REG                            , RULL(0x2C0F001A), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_ATTN_INTERRUPT_REG                            , RULL(0x2D0F001A), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_ATTN_INTERRUPT_REG                            , RULL(0x2E0F001A), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_ATTN_INTERRUPT_REG                            , RULL(0x2F0F001A), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_ATTN_INTERRUPT_REG                            , RULL(0x300F001A), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_ATTN_INTERRUPT_REG                            , RULL(0x310F001A), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_ATTN_INTERRUPT_REG                            , RULL(0x320F001A), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_ATTN_INTERRUPT_REG                            , RULL(0x330F001A), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_ATTN_INTERRUPT_REG                            , RULL(0x340F001A), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_ATTN_INTERRUPT_REG                            , RULL(0x350F001A), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_ATTN_INTERRUPT_REG                            , RULL(0x360F001A), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_ATTN_INTERRUPT_REG                            , RULL(0x370F001A), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_BIST                                               , RULL(0x0003000B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_BIST                                            , RULL(0x0103000B), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_BIST                                            , RULL(0x0203000B), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_BIST                                            , RULL(0x0303000B), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_BIST                                            , RULL(0x0403000B), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_BIST                                            , RULL(0x0503000B), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_BIST                                            , RULL(0x0603000B), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_BIST                                          , RULL(0x0703000B), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_BIST                                          , RULL(0x0803000B), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_BIST                                           , RULL(0x0903000B), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_BIST                                           , RULL(0x0C03000B), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_BIST                                          , RULL(0x0D03000B), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_BIST                                          , RULL(0x0E03000B), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_BIST                                          , RULL(0x0F03000B), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_BIST                                          , RULL(0x1003000B), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_BIST                                          , RULL(0x1103000B), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_BIST                                          , RULL(0x1203000B), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_BIST                                          , RULL(0x1303000B), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_BIST                                          , RULL(0x1403000B), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_BIST                                          , RULL(0x1503000B), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_BIST                                          , RULL(0x2003000B), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_BIST                                          , RULL(0x2103000B), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_BIST                                          , RULL(0x2203000B), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_BIST                                          , RULL(0x2303000B), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_BIST                                          , RULL(0x2403000B), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_BIST                                          , RULL(0x2503000B), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_BIST                                          , RULL(0x2603000B), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_BIST                                          , RULL(0x2703000B), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_BIST                                          , RULL(0x2803000B), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_BIST                                          , RULL(0x2903000B), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_BIST                                          , RULL(0x2A03000B), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_BIST                                          , RULL(0x2B03000B), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_BIST                                          , RULL(0x2C03000B), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_BIST                                          , RULL(0x2D03000B), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_BIST                                          , RULL(0x2E03000B), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_BIST                                          , RULL(0x2F03000B), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_BIST                                          , RULL(0x3003000B), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_BIST                                          , RULL(0x3103000B), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_BIST                                          , RULL(0x3203000B), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_BIST                                          , RULL(0x3303000B), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_BIST                                          , RULL(0x3403000B), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_BIST                                          , RULL(0x3503000B), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_BIST                                          , RULL(0x3603000B), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_BIST                                          , RULL(0x3703000B), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_BIT_SEL_REG_2                                      , RULL(0x000F0008), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_BIT_SEL_REG_2                                  , RULL(0x000F0008), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_CBS_CS_FSI                                         , RULL(0x00002801), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_CBS_CS_FSI_BYTE                                    , RULL(0x00002804), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_CBS_CS_SCOM                                        , RULL(0x00050001), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_CBS_CS                                         , RULL(0x00050001), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_CBS_EL_FSI                                         , RULL(0x00002803), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_CBS_EL_FSI_BYTE                                    , RULL(0x0000280C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_CBS_EL_SCOM                                        , RULL(0x00050003), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_CBS_EL                                         , RULL(0x00050003), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_CBS_EL_HIST_FSI                                    , RULL(0x00002806), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_CBS_EL_HIST_FSI_BYTE                               , RULL(0x00002818), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_CBS_EL_HIST_SCOM                                   , RULL(0x00050006), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_CBS_EL_HIST                                    , RULL(0x00050006), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_CBS_STAT_FSI                                       , RULL(0x0000280B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_CBS_STAT_FSI_BYTE                                  , RULL(0x0000282C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_CBS_STAT_SCOM                                      , RULL(0x0005000B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_CBS_STAT                                       , RULL(0x0005000B), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_CBS_TR_FSI                                         , RULL(0x00002802), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_CBS_TR_FSI_BYTE                                    , RULL(0x00002808), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_CBS_TR_SCOM                                        , RULL(0x00050002), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_CBS_TR                                         , RULL(0x00050002), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_CBS_TR_HIST_FSI                                    , RULL(0x00002805), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_CBS_TR_HIST_FSI_BYTE                               , RULL(0x00002814), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_CBS_TR_HIST_SCOM                                   , RULL(0x00050005), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_CBS_TR_HIST                                    , RULL(0x00050005), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_CC_ATOMIC_LOCK_REG                                 , RULL(0x000303FF), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_CC_ATOMIC_LOCK_REG                              , RULL(0x010303FF), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CC_ATOMIC_LOCK_REG                              , RULL(0x020303FF), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CC_ATOMIC_LOCK_REG                              , RULL(0x030303FF), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CC_ATOMIC_LOCK_REG                              , RULL(0x040303FF), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CC_ATOMIC_LOCK_REG                              , RULL(0x050303FF), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CC_ATOMIC_LOCK_REG                              , RULL(0x060303FF), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CC_ATOMIC_LOCK_REG                            , RULL(0x070303FF), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CC_ATOMIC_LOCK_REG                            , RULL(0x080303FF), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CC_ATOMIC_LOCK_REG                             , RULL(0x090303FF), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CC_ATOMIC_LOCK_REG                             , RULL(0x0C0303FF), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CC_ATOMIC_LOCK_REG                            , RULL(0x0D0303FF), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CC_ATOMIC_LOCK_REG                            , RULL(0x0E0303FF), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CC_ATOMIC_LOCK_REG                            , RULL(0x0F0303FF), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CC_ATOMIC_LOCK_REG                            , RULL(0x100303FF), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CC_ATOMIC_LOCK_REG                            , RULL(0x110303FF), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CC_ATOMIC_LOCK_REG                            , RULL(0x120303FF), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CC_ATOMIC_LOCK_REG                            , RULL(0x130303FF), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CC_ATOMIC_LOCK_REG                            , RULL(0x140303FF), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CC_ATOMIC_LOCK_REG                            , RULL(0x150303FF), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CC_ATOMIC_LOCK_REG                            , RULL(0x200303FF), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CC_ATOMIC_LOCK_REG                            , RULL(0x210303FF), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CC_ATOMIC_LOCK_REG                            , RULL(0x220303FF), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CC_ATOMIC_LOCK_REG                            , RULL(0x230303FF), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CC_ATOMIC_LOCK_REG                            , RULL(0x240303FF), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CC_ATOMIC_LOCK_REG                            , RULL(0x250303FF), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CC_ATOMIC_LOCK_REG                            , RULL(0x260303FF), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CC_ATOMIC_LOCK_REG                            , RULL(0x270303FF), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CC_ATOMIC_LOCK_REG                            , RULL(0x280303FF), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CC_ATOMIC_LOCK_REG                            , RULL(0x290303FF), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CC_ATOMIC_LOCK_REG                            , RULL(0x2A0303FF), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CC_ATOMIC_LOCK_REG                            , RULL(0x2B0303FF), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CC_ATOMIC_LOCK_REG                            , RULL(0x2C0303FF), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CC_ATOMIC_LOCK_REG                            , RULL(0x2D0303FF), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CC_ATOMIC_LOCK_REG                            , RULL(0x2E0303FF), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CC_ATOMIC_LOCK_REG                            , RULL(0x2F0303FF), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CC_ATOMIC_LOCK_REG                            , RULL(0x300303FF), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CC_ATOMIC_LOCK_REG                            , RULL(0x310303FF), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CC_ATOMIC_LOCK_REG                            , RULL(0x320303FF), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CC_ATOMIC_LOCK_REG                            , RULL(0x330303FF), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CC_ATOMIC_LOCK_REG                            , RULL(0x340303FF), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CC_ATOMIC_LOCK_REG                            , RULL(0x350303FF), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CC_ATOMIC_LOCK_REG                            , RULL(0x360303FF), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CC_ATOMIC_LOCK_REG                            , RULL(0x370303FF), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CC_PROTECT_MODE_REG                                , RULL(0x000303FE), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_CC_PROTECT_MODE_REG                             , RULL(0x010303FE), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CC_PROTECT_MODE_REG                             , RULL(0x020303FE), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CC_PROTECT_MODE_REG                             , RULL(0x030303FE), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CC_PROTECT_MODE_REG                             , RULL(0x040303FE), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CC_PROTECT_MODE_REG                             , RULL(0x050303FE), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CC_PROTECT_MODE_REG                             , RULL(0x060303FE), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CC_PROTECT_MODE_REG                           , RULL(0x070303FE), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CC_PROTECT_MODE_REG                           , RULL(0x080303FE), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CC_PROTECT_MODE_REG                            , RULL(0x090303FE), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CC_PROTECT_MODE_REG                            , RULL(0x0C0303FE), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CC_PROTECT_MODE_REG                           , RULL(0x0D0303FE), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CC_PROTECT_MODE_REG                           , RULL(0x0E0303FE), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CC_PROTECT_MODE_REG                           , RULL(0x0F0303FE), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CC_PROTECT_MODE_REG                           , RULL(0x100303FE), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CC_PROTECT_MODE_REG                           , RULL(0x110303FE), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CC_PROTECT_MODE_REG                           , RULL(0x120303FE), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CC_PROTECT_MODE_REG                           , RULL(0x130303FE), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CC_PROTECT_MODE_REG                           , RULL(0x140303FE), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CC_PROTECT_MODE_REG                           , RULL(0x150303FE), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CC_PROTECT_MODE_REG                           , RULL(0x200303FE), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CC_PROTECT_MODE_REG                           , RULL(0x210303FE), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CC_PROTECT_MODE_REG                           , RULL(0x220303FE), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CC_PROTECT_MODE_REG                           , RULL(0x230303FE), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CC_PROTECT_MODE_REG                           , RULL(0x240303FE), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CC_PROTECT_MODE_REG                           , RULL(0x250303FE), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CC_PROTECT_MODE_REG                           , RULL(0x260303FE), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CC_PROTECT_MODE_REG                           , RULL(0x270303FE), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CC_PROTECT_MODE_REG                           , RULL(0x280303FE), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CC_PROTECT_MODE_REG                           , RULL(0x290303FE), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CC_PROTECT_MODE_REG                           , RULL(0x2A0303FE), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CC_PROTECT_MODE_REG                           , RULL(0x2B0303FE), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CC_PROTECT_MODE_REG                           , RULL(0x2C0303FE), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CC_PROTECT_MODE_REG                           , RULL(0x2D0303FE), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CC_PROTECT_MODE_REG                           , RULL(0x2E0303FE), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CC_PROTECT_MODE_REG                           , RULL(0x2F0303FE), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CC_PROTECT_MODE_REG                           , RULL(0x300303FE), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CC_PROTECT_MODE_REG                           , RULL(0x310303FE), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CC_PROTECT_MODE_REG                           , RULL(0x320303FE), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CC_PROTECT_MODE_REG                           , RULL(0x330303FE), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CC_PROTECT_MODE_REG                           , RULL(0x340303FE), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CC_PROTECT_MODE_REG                           , RULL(0x350303FE), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CC_PROTECT_MODE_REG                           , RULL(0x360303FE), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CC_PROTECT_MODE_REG                           , RULL(0x370303FE), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG32( PERV_FSI2PIB_CHIPID_FSI                                 , RULL(0x0000100A), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_CHIPID_FSI_BYTE                            , RULL(0x00001028), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_CHIP_ID_FSI                               , RULL(0x00000C09), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_CHIP_ID_FSI_BYTE                          , RULL(0x00000C24), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG64( PERV_CLK_REGION                                         , RULL(0x00030006), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_CLK_REGION                                      , RULL(0x01030006), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CLK_REGION                                      , RULL(0x02030006), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CLK_REGION                                      , RULL(0x03030006), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CLK_REGION                                      , RULL(0x04030006), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CLK_REGION                                      , RULL(0x05030006), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CLK_REGION                                      , RULL(0x06030006), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CLK_REGION                                    , RULL(0x07030006), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CLK_REGION                                    , RULL(0x08030006), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CLK_REGION                                     , RULL(0x09030006), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CLK_REGION                                     , RULL(0x0C030006), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CLK_REGION                                    , RULL(0x0D030006), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CLK_REGION                                    , RULL(0x0E030006), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CLK_REGION                                    , RULL(0x0F030006), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CLK_REGION                                    , RULL(0x10030006), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CLK_REGION                                    , RULL(0x11030006), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CLK_REGION                                    , RULL(0x12030006), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CLK_REGION                                    , RULL(0x13030006), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CLK_REGION                                    , RULL(0x14030006), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CLK_REGION                                    , RULL(0x15030006), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CLK_REGION                                    , RULL(0x20030006), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CLK_REGION                                    , RULL(0x21030006), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CLK_REGION                                    , RULL(0x22030006), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CLK_REGION                                    , RULL(0x23030006), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CLK_REGION                                    , RULL(0x24030006), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CLK_REGION                                    , RULL(0x25030006), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CLK_REGION                                    , RULL(0x26030006), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CLK_REGION                                    , RULL(0x27030006), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CLK_REGION                                    , RULL(0x28030006), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CLK_REGION                                    , RULL(0x29030006), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CLK_REGION                                    , RULL(0x2A030006), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CLK_REGION                                    , RULL(0x2B030006), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CLK_REGION                                    , RULL(0x2C030006), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CLK_REGION                                    , RULL(0x2D030006), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CLK_REGION                                    , RULL(0x2E030006), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CLK_REGION                                    , RULL(0x2F030006), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CLK_REGION                                    , RULL(0x30030006), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CLK_REGION                                    , RULL(0x31030006), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CLK_REGION                                    , RULL(0x32030006), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CLK_REGION                                    , RULL(0x33030006), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CLK_REGION                                    , RULL(0x34030006), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CLK_REGION                                    , RULL(0x35030006), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CLK_REGION                                    , RULL(0x36030006), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CLK_REGION                                    , RULL(0x37030006), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CLOCK_STAT_ARY                                     , RULL(0x0003000A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_CLOCK_STAT_ARY                                  , RULL(0x0103000A), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CLOCK_STAT_ARY                                  , RULL(0x0203000A), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CLOCK_STAT_ARY                                  , RULL(0x0303000A), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CLOCK_STAT_ARY                                  , RULL(0x0403000A), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CLOCK_STAT_ARY                                  , RULL(0x0503000A), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CLOCK_STAT_ARY                                  , RULL(0x0603000A), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CLOCK_STAT_ARY                                , RULL(0x0703000A), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CLOCK_STAT_ARY                                , RULL(0x0803000A), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CLOCK_STAT_ARY                                 , RULL(0x0903000A), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CLOCK_STAT_ARY                                 , RULL(0x0C03000A), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CLOCK_STAT_ARY                                , RULL(0x0D03000A), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CLOCK_STAT_ARY                                , RULL(0x0E03000A), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CLOCK_STAT_ARY                                , RULL(0x0F03000A), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CLOCK_STAT_ARY                                , RULL(0x1003000A), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CLOCK_STAT_ARY                                , RULL(0x1103000A), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CLOCK_STAT_ARY                                , RULL(0x1203000A), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CLOCK_STAT_ARY                                , RULL(0x1303000A), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CLOCK_STAT_ARY                                , RULL(0x1403000A), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CLOCK_STAT_ARY                                , RULL(0x1503000A), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CLOCK_STAT_ARY                                , RULL(0x2003000A), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CLOCK_STAT_ARY                                , RULL(0x2103000A), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CLOCK_STAT_ARY                                , RULL(0x2203000A), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CLOCK_STAT_ARY                                , RULL(0x2303000A), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CLOCK_STAT_ARY                                , RULL(0x2403000A), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CLOCK_STAT_ARY                                , RULL(0x2503000A), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CLOCK_STAT_ARY                                , RULL(0x2603000A), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CLOCK_STAT_ARY                                , RULL(0x2703000A), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CLOCK_STAT_ARY                                , RULL(0x2803000A), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CLOCK_STAT_ARY                                , RULL(0x2903000A), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CLOCK_STAT_ARY                                , RULL(0x2A03000A), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CLOCK_STAT_ARY                                , RULL(0x2B03000A), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CLOCK_STAT_ARY                                , RULL(0x2C03000A), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CLOCK_STAT_ARY                                , RULL(0x2D03000A), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CLOCK_STAT_ARY                                , RULL(0x2E03000A), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CLOCK_STAT_ARY                                , RULL(0x2F03000A), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CLOCK_STAT_ARY                                , RULL(0x3003000A), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CLOCK_STAT_ARY                                , RULL(0x3103000A), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CLOCK_STAT_ARY                                , RULL(0x3203000A), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CLOCK_STAT_ARY                                , RULL(0x3303000A), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CLOCK_STAT_ARY                                , RULL(0x3403000A), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CLOCK_STAT_ARY                                , RULL(0x3503000A), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CLOCK_STAT_ARY                                , RULL(0x3603000A), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CLOCK_STAT_ARY                                , RULL(0x3703000A), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CLOCK_STAT_NSL                                     , RULL(0x00030009), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_CLOCK_STAT_NSL                                  , RULL(0x01030009), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CLOCK_STAT_NSL                                  , RULL(0x02030009), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CLOCK_STAT_NSL                                  , RULL(0x03030009), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CLOCK_STAT_NSL                                  , RULL(0x04030009), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CLOCK_STAT_NSL                                  , RULL(0x05030009), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CLOCK_STAT_NSL                                  , RULL(0x06030009), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CLOCK_STAT_NSL                                , RULL(0x07030009), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CLOCK_STAT_NSL                                , RULL(0x08030009), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CLOCK_STAT_NSL                                 , RULL(0x09030009), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CLOCK_STAT_NSL                                 , RULL(0x0C030009), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CLOCK_STAT_NSL                                , RULL(0x0D030009), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CLOCK_STAT_NSL                                , RULL(0x0E030009), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CLOCK_STAT_NSL                                , RULL(0x0F030009), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CLOCK_STAT_NSL                                , RULL(0x10030009), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CLOCK_STAT_NSL                                , RULL(0x11030009), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CLOCK_STAT_NSL                                , RULL(0x12030009), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CLOCK_STAT_NSL                                , RULL(0x13030009), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CLOCK_STAT_NSL                                , RULL(0x14030009), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CLOCK_STAT_NSL                                , RULL(0x15030009), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CLOCK_STAT_NSL                                , RULL(0x20030009), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CLOCK_STAT_NSL                                , RULL(0x21030009), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CLOCK_STAT_NSL                                , RULL(0x22030009), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CLOCK_STAT_NSL                                , RULL(0x23030009), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CLOCK_STAT_NSL                                , RULL(0x24030009), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CLOCK_STAT_NSL                                , RULL(0x25030009), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CLOCK_STAT_NSL                                , RULL(0x26030009), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CLOCK_STAT_NSL                                , RULL(0x27030009), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CLOCK_STAT_NSL                                , RULL(0x28030009), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CLOCK_STAT_NSL                                , RULL(0x29030009), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CLOCK_STAT_NSL                                , RULL(0x2A030009), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CLOCK_STAT_NSL                                , RULL(0x2B030009), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CLOCK_STAT_NSL                                , RULL(0x2C030009), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CLOCK_STAT_NSL                                , RULL(0x2D030009), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CLOCK_STAT_NSL                                , RULL(0x2E030009), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CLOCK_STAT_NSL                                , RULL(0x2F030009), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CLOCK_STAT_NSL                                , RULL(0x30030009), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CLOCK_STAT_NSL                                , RULL(0x31030009), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CLOCK_STAT_NSL                                , RULL(0x32030009), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CLOCK_STAT_NSL                                , RULL(0x33030009), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CLOCK_STAT_NSL                                , RULL(0x34030009), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CLOCK_STAT_NSL                                , RULL(0x35030009), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CLOCK_STAT_NSL                                , RULL(0x36030009), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CLOCK_STAT_NSL                                , RULL(0x37030009), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CLOCK_STAT_SL                                      , RULL(0x00030008), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_CLOCK_STAT_SL                                   , RULL(0x01030008), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CLOCK_STAT_SL                                   , RULL(0x02030008), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CLOCK_STAT_SL                                   , RULL(0x03030008), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CLOCK_STAT_SL                                   , RULL(0x04030008), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CLOCK_STAT_SL                                   , RULL(0x05030008), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CLOCK_STAT_SL                                   , RULL(0x06030008), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CLOCK_STAT_SL                                 , RULL(0x07030008), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CLOCK_STAT_SL                                 , RULL(0x08030008), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CLOCK_STAT_SL                                  , RULL(0x09030008), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CLOCK_STAT_SL                                  , RULL(0x0C030008), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CLOCK_STAT_SL                                 , RULL(0x0D030008), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CLOCK_STAT_SL                                 , RULL(0x0E030008), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CLOCK_STAT_SL                                 , RULL(0x0F030008), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CLOCK_STAT_SL                                 , RULL(0x10030008), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CLOCK_STAT_SL                                 , RULL(0x11030008), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CLOCK_STAT_SL                                 , RULL(0x12030008), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CLOCK_STAT_SL                                 , RULL(0x13030008), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CLOCK_STAT_SL                                 , RULL(0x14030008), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CLOCK_STAT_SL                                 , RULL(0x15030008), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CLOCK_STAT_SL                                 , RULL(0x20030008), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CLOCK_STAT_SL                                 , RULL(0x21030008), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CLOCK_STAT_SL                                 , RULL(0x22030008), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CLOCK_STAT_SL                                 , RULL(0x23030008), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CLOCK_STAT_SL                                 , RULL(0x24030008), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CLOCK_STAT_SL                                 , RULL(0x25030008), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CLOCK_STAT_SL                                 , RULL(0x26030008), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CLOCK_STAT_SL                                 , RULL(0x27030008), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CLOCK_STAT_SL                                 , RULL(0x28030008), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CLOCK_STAT_SL                                 , RULL(0x29030008), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CLOCK_STAT_SL                                 , RULL(0x2A030008), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CLOCK_STAT_SL                                 , RULL(0x2B030008), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CLOCK_STAT_SL                                 , RULL(0x2C030008), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CLOCK_STAT_SL                                 , RULL(0x2D030008), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CLOCK_STAT_SL                                 , RULL(0x2E030008), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CLOCK_STAT_SL                                 , RULL(0x2F030008), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CLOCK_STAT_SL                                 , RULL(0x30030008), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CLOCK_STAT_SL                                 , RULL(0x31030008), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CLOCK_STAT_SL                                 , RULL(0x32030008), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CLOCK_STAT_SL                                 , RULL(0x33030008), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CLOCK_STAT_SL                                 , RULL(0x34030008), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CLOCK_STAT_SL                                 , RULL(0x35030008), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CLOCK_STAT_SL                                 , RULL(0x36030008), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CLOCK_STAT_SL                                 , RULL(0x37030008), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CMD_WRDAT                                          , RULL(0x00030000), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_CMD_WRDAT                                      , RULL(0x00030000), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+REG64( PERV_0_PIB2OPB0_CMD_WRDAT                               , RULL(0x00020000), SH_UNT_PERV_0_PIB2OPB0,
+       SH_ACS_SCOM      );
+REG64( PERV_0_PIB2OPB1_CMD_WRDAT                               , RULL(0x00020010), SH_UNT_PERV_0_PIB2OPB1,
+       SH_ACS_SCOM      );
+REG64( PERV_PIB2OPB0_CMD_WRDAT                                 , RULL(0x00020000), SH_UNT_PERV_PIB2OPB0,
+       SH_ACS_SCOM      );
+REG64( PERV_PIB2OPB1_CMD_WRDAT                                 , RULL(0x00020010), SH_UNT_PERV_PIB2OPB1,
+       SH_ACS_SCOM      );
+
+REG32( PERV_FSI2PIB_COMMAND_REGISTER_FSI                       , RULL(0x00001002), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_COMMAND_REGISTER_FSI_BYTE                  , RULL(0x00001008), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI_BYTE  );
+REG32( PERV_FSISHIFT_COMMAND_REGISTER_FSI                      , RULL(0x00000C01), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_COMMAND_REGISTER_FSI_BYTE                 , RULL(0x00000C04), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG64( PERV_0_FSII2C_COMMAND_REGISTER_A                        , RULL(0x00001801), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      );
+REG32( PERV_FSII2C_COMMAND_REGISTER_A                          , RULL(0x00001801), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      );
+
+REG32( PERV_FSI2PIB_COMPLEMENT_MASK_FSI                        , RULL(0x0000100C), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_COMPLEMENT_MASK_FSI_BYTE                   , RULL(0x00001030), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI_BYTE  );
+REG32( PERV_FSISHIFT_COMPLEMENT_MASK_FSI                       , RULL(0x00000C0C), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_COMPLEMENT_MASK_FSI_BYTE                  , RULL(0x00000C30), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG64( PERV_CONTROL_REG                                        , RULL(0x00050012), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_CONTROL_REG                                     , RULL(0x01050012), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CONTROL_REG                                     , RULL(0x02050012), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CONTROL_REG                                     , RULL(0x03050012), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CONTROL_REG                                     , RULL(0x04050012), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CONTROL_REG                                     , RULL(0x05050012), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CONTROL_REG                                     , RULL(0x06050012), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CONTROL_REG                                   , RULL(0x07050012), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CONTROL_REG                                   , RULL(0x08050012), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CONTROL_REG                                    , RULL(0x09050012), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CONTROL_REG                                    , RULL(0x0C050012), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CONTROL_REG                                   , RULL(0x0D050012), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CONTROL_REG                                   , RULL(0x0E050012), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CONTROL_REG                                   , RULL(0x0F050012), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CONTROL_REG                                   , RULL(0x10050012), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CONTROL_REG                                   , RULL(0x11050012), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CONTROL_REG                                   , RULL(0x12050012), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CONTROL_REG                                   , RULL(0x13050012), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CONTROL_REG                                   , RULL(0x14050012), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CONTROL_REG                                   , RULL(0x15050012), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CONTROL_REG                                   , RULL(0x20050012), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CONTROL_REG                                   , RULL(0x21050012), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CONTROL_REG                                   , RULL(0x22050012), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CONTROL_REG                                   , RULL(0x23050012), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CONTROL_REG                                   , RULL(0x24050012), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CONTROL_REG                                   , RULL(0x25050012), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CONTROL_REG                                   , RULL(0x26050012), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CONTROL_REG                                   , RULL(0x27050012), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CONTROL_REG                                   , RULL(0x28050012), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CONTROL_REG                                   , RULL(0x29050012), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CONTROL_REG                                   , RULL(0x2A050012), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CONTROL_REG                                   , RULL(0x2B050012), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CONTROL_REG                                   , RULL(0x2C050012), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CONTROL_REG                                   , RULL(0x2D050012), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CONTROL_REG                                   , RULL(0x2E050012), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CONTROL_REG                                   , RULL(0x2F050012), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CONTROL_REG                                   , RULL(0x30050012), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CONTROL_REG                                   , RULL(0x31050012), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CONTROL_REG                                   , RULL(0x32050012), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CONTROL_REG                                   , RULL(0x33050012), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CONTROL_REG                                   , RULL(0x34050012), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CONTROL_REG                                   , RULL(0x35050012), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CONTROL_REG                                   , RULL(0x36050012), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CONTROL_REG                                   , RULL(0x37050012), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CPLT_CONF0                                         , RULL(0x00000008), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_CPLT_CONF0                                      , RULL(0x01000008), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_CPLT_CONF0_OR                                      , RULL(0x00000018), SH_UNT_PERV     , SH_ACS_SCOM1_OR  );
+REG64( PERV_TP_CPLT_CONF0_OR                                   , RULL(0x01000018), SH_UNT_PERV_1   , SH_ACS_SCOM1_OR  );
+REG64( PERV_CPLT_CONF0_CLEAR                                   , RULL(0x00000028), SH_UNT_PERV     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_TP_CPLT_CONF0_CLEAR                                , RULL(0x01000028), SH_UNT_PERV_1   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N0_CPLT_CONF0                                      , RULL(0x02000008), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_CPLT_CONF0_OR                                   , RULL(0x02000018), SH_UNT_PERV_2   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N0_CPLT_CONF0_CLEAR                                , RULL(0x02000028), SH_UNT_PERV_2   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N1_CPLT_CONF0                                      , RULL(0x03000008), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_CPLT_CONF0_OR                                   , RULL(0x03000018), SH_UNT_PERV_3   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N1_CPLT_CONF0_CLEAR                                , RULL(0x03000028), SH_UNT_PERV_3   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N2_CPLT_CONF0                                      , RULL(0x04000008), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_CPLT_CONF0_OR                                   , RULL(0x04000018), SH_UNT_PERV_4   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N2_CPLT_CONF0_CLEAR                                , RULL(0x04000028), SH_UNT_PERV_4   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N3_CPLT_CONF0                                      , RULL(0x05000008), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_CPLT_CONF0_OR                                   , RULL(0x05000018), SH_UNT_PERV_5   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N3_CPLT_CONF0_CLEAR                                , RULL(0x05000028), SH_UNT_PERV_5   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_XB_CPLT_CONF0                                      , RULL(0x06000008), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_CPLT_CONF0_OR                                   , RULL(0x06000018), SH_UNT_PERV_6   , SH_ACS_SCOM1_OR  );
+REG64( PERV_XB_CPLT_CONF0_CLEAR                                , RULL(0x06000028), SH_UNT_PERV_6   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC01_CPLT_CONF0                                    , RULL(0x07000008), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_CPLT_CONF0_OR                                 , RULL(0x07000018), SH_UNT_PERV_7   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC01_CPLT_CONF0_CLEAR                              , RULL(0x07000028), SH_UNT_PERV_7   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC23_CPLT_CONF0                                    , RULL(0x08000008), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_CPLT_CONF0_OR                                 , RULL(0x08000018), SH_UNT_PERV_8   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC23_CPLT_CONF0_CLEAR                              , RULL(0x08000028), SH_UNT_PERV_8   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB0_CPLT_CONF0                                     , RULL(0x09000008), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_CPLT_CONF0_OR                                  , RULL(0x09000018), SH_UNT_PERV_9   , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB0_CPLT_CONF0_CLEAR                               , RULL(0x09000028), SH_UNT_PERV_9   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB3_CPLT_CONF0                                     , RULL(0x0C000008), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_CPLT_CONF0_OR                                  , RULL(0x0C000018), SH_UNT_PERV_12  , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB3_CPLT_CONF0_CLEAR                               , RULL(0x0C000028), SH_UNT_PERV_12  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI0_CPLT_CONF0                                    , RULL(0x0D000008), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_CPLT_CONF0_OR                                 , RULL(0x0D000018), SH_UNT_PERV_13  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI0_CPLT_CONF0_CLEAR                              , RULL(0x0D000028), SH_UNT_PERV_13  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI1_CPLT_CONF0                                    , RULL(0x0E000008), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_CPLT_CONF0_OR                                 , RULL(0x0E000018), SH_UNT_PERV_14  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI1_CPLT_CONF0_CLEAR                              , RULL(0x0E000028), SH_UNT_PERV_14  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI2_CPLT_CONF0                                    , RULL(0x0F000008), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_CPLT_CONF0_OR                                 , RULL(0x0F000018), SH_UNT_PERV_15  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI2_CPLT_CONF0_CLEAR                              , RULL(0x0F000028), SH_UNT_PERV_15  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP00_CPLT_CONF0                                    , RULL(0x10000008), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_CPLT_CONF0_OR                                 , RULL(0x10000018), SH_UNT_PERV_16  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP00_CPLT_CONF0_CLEAR                              , RULL(0x10000028), SH_UNT_PERV_16  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP01_CPLT_CONF0                                    , RULL(0x11000008), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_CPLT_CONF0_OR                                 , RULL(0x11000018), SH_UNT_PERV_17  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP01_CPLT_CONF0_CLEAR                              , RULL(0x11000028), SH_UNT_PERV_17  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP02_CPLT_CONF0                                    , RULL(0x12000008), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_CPLT_CONF0_OR                                 , RULL(0x12000018), SH_UNT_PERV_18  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP02_CPLT_CONF0_CLEAR                              , RULL(0x12000028), SH_UNT_PERV_18  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP03_CPLT_CONF0                                    , RULL(0x13000008), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_CPLT_CONF0_OR                                 , RULL(0x13000018), SH_UNT_PERV_19  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP03_CPLT_CONF0_CLEAR                              , RULL(0x13000028), SH_UNT_PERV_19  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP04_CPLT_CONF0                                    , RULL(0x14000008), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_CPLT_CONF0_OR                                 , RULL(0x14000018), SH_UNT_PERV_20  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP04_CPLT_CONF0_CLEAR                              , RULL(0x14000028), SH_UNT_PERV_20  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP05_CPLT_CONF0                                    , RULL(0x15000008), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_CPLT_CONF0_OR                                 , RULL(0x15000018), SH_UNT_PERV_21  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP05_CPLT_CONF0_CLEAR                              , RULL(0x15000028), SH_UNT_PERV_21  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC00_CPLT_CONF0                                    , RULL(0x20000008), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPLT_CONF0_OR                                 , RULL(0x20000018), SH_UNT_PERV_32  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC00_CPLT_CONF0_CLEAR                              , RULL(0x20000028), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC01_CPLT_CONF0                                    , RULL(0x21000008), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPLT_CONF0_OR                                 , RULL(0x21000018), SH_UNT_PERV_33  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC01_CPLT_CONF0_CLEAR                              , RULL(0x21000028), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC02_CPLT_CONF0                                    , RULL(0x22000008), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPLT_CONF0_OR                                 , RULL(0x22000018), SH_UNT_PERV_34  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC02_CPLT_CONF0_CLEAR                              , RULL(0x22000028), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC03_CPLT_CONF0                                    , RULL(0x23000008), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPLT_CONF0_OR                                 , RULL(0x23000018), SH_UNT_PERV_35  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC03_CPLT_CONF0_CLEAR                              , RULL(0x23000028), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC04_CPLT_CONF0                                    , RULL(0x24000008), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPLT_CONF0_OR                                 , RULL(0x24000018), SH_UNT_PERV_36  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC04_CPLT_CONF0_CLEAR                              , RULL(0x24000028), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC05_CPLT_CONF0                                    , RULL(0x25000008), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPLT_CONF0_OR                                 , RULL(0x25000018), SH_UNT_PERV_37  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC05_CPLT_CONF0_CLEAR                              , RULL(0x25000028), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC06_CPLT_CONF0                                    , RULL(0x26000008), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPLT_CONF0_OR                                 , RULL(0x26000018), SH_UNT_PERV_38  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC06_CPLT_CONF0_CLEAR                              , RULL(0x26000028), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC07_CPLT_CONF0                                    , RULL(0x27000008), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPLT_CONF0_OR                                 , RULL(0x27000018), SH_UNT_PERV_39  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC07_CPLT_CONF0_CLEAR                              , RULL(0x27000028), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC08_CPLT_CONF0                                    , RULL(0x28000008), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPLT_CONF0_OR                                 , RULL(0x28000018), SH_UNT_PERV_40  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC08_CPLT_CONF0_CLEAR                              , RULL(0x28000028), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC09_CPLT_CONF0                                    , RULL(0x29000008), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPLT_CONF0_OR                                 , RULL(0x29000018), SH_UNT_PERV_41  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC09_CPLT_CONF0_CLEAR                              , RULL(0x29000028), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC10_CPLT_CONF0                                    , RULL(0x2A000008), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPLT_CONF0_OR                                 , RULL(0x2A000018), SH_UNT_PERV_42  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC10_CPLT_CONF0_CLEAR                              , RULL(0x2A000028), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC11_CPLT_CONF0                                    , RULL(0x2B000008), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPLT_CONF0_OR                                 , RULL(0x2B000018), SH_UNT_PERV_43  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC11_CPLT_CONF0_CLEAR                              , RULL(0x2B000028), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC12_CPLT_CONF0                                    , RULL(0x2C000008), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPLT_CONF0_OR                                 , RULL(0x2C000018), SH_UNT_PERV_44  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC12_CPLT_CONF0_CLEAR                              , RULL(0x2C000028), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC13_CPLT_CONF0                                    , RULL(0x2D000008), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPLT_CONF0_OR                                 , RULL(0x2D000018), SH_UNT_PERV_45  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC13_CPLT_CONF0_CLEAR                              , RULL(0x2D000028), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC14_CPLT_CONF0                                    , RULL(0x2E000008), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPLT_CONF0_OR                                 , RULL(0x2E000018), SH_UNT_PERV_46  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC14_CPLT_CONF0_CLEAR                              , RULL(0x2E000028), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC15_CPLT_CONF0                                    , RULL(0x2F000008), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPLT_CONF0_OR                                 , RULL(0x2F000018), SH_UNT_PERV_47  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC15_CPLT_CONF0_CLEAR                              , RULL(0x2F000028), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC16_CPLT_CONF0                                    , RULL(0x30000008), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPLT_CONF0_OR                                 , RULL(0x30000018), SH_UNT_PERV_48  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC16_CPLT_CONF0_CLEAR                              , RULL(0x30000028), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC17_CPLT_CONF0                                    , RULL(0x31000008), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPLT_CONF0_OR                                 , RULL(0x31000018), SH_UNT_PERV_49  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC17_CPLT_CONF0_CLEAR                              , RULL(0x31000028), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC18_CPLT_CONF0                                    , RULL(0x32000008), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPLT_CONF0_OR                                 , RULL(0x32000018), SH_UNT_PERV_50  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC18_CPLT_CONF0_CLEAR                              , RULL(0x32000028), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC19_CPLT_CONF0                                    , RULL(0x33000008), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPLT_CONF0_OR                                 , RULL(0x33000018), SH_UNT_PERV_51  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC19_CPLT_CONF0_CLEAR                              , RULL(0x33000028), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC20_CPLT_CONF0                                    , RULL(0x34000008), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPLT_CONF0_OR                                 , RULL(0x34000018), SH_UNT_PERV_52  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC20_CPLT_CONF0_CLEAR                              , RULL(0x34000028), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC21_CPLT_CONF0                                    , RULL(0x35000008), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPLT_CONF0_OR                                 , RULL(0x35000018), SH_UNT_PERV_53  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC21_CPLT_CONF0_CLEAR                              , RULL(0x35000028), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC22_CPLT_CONF0                                    , RULL(0x36000008), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPLT_CONF0_OR                                 , RULL(0x36000018), SH_UNT_PERV_54  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC22_CPLT_CONF0_CLEAR                              , RULL(0x36000028), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC23_CPLT_CONF0                                    , RULL(0x37000008), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPLT_CONF0_OR                                 , RULL(0x37000018), SH_UNT_PERV_55  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC23_CPLT_CONF0_CLEAR                              , RULL(0x37000028), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM2_CLEAR );
+
+REG64( PERV_CPLT_CONF1                                         , RULL(0x00000009), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_CPLT_CONF1                                      , RULL(0x01000009), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_CPLT_CONF1_OR                                      , RULL(0x00000019), SH_UNT_PERV     , SH_ACS_SCOM1_OR  );
+REG64( PERV_TP_CPLT_CONF1_OR                                   , RULL(0x01000019), SH_UNT_PERV_1   , SH_ACS_SCOM1_OR  );
+REG64( PERV_CPLT_CONF1_CLEAR                                   , RULL(0x00000029), SH_UNT_PERV     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_TP_CPLT_CONF1_CLEAR                                , RULL(0x01000029), SH_UNT_PERV_1   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N0_CPLT_CONF1                                      , RULL(0x02000009), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_CPLT_CONF1_OR                                   , RULL(0x02000019), SH_UNT_PERV_2   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N0_CPLT_CONF1_CLEAR                                , RULL(0x02000029), SH_UNT_PERV_2   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N1_CPLT_CONF1                                      , RULL(0x03000009), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_CPLT_CONF1_OR                                   , RULL(0x03000019), SH_UNT_PERV_3   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N1_CPLT_CONF1_CLEAR                                , RULL(0x03000029), SH_UNT_PERV_3   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N2_CPLT_CONF1                                      , RULL(0x04000009), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_CPLT_CONF1_OR                                   , RULL(0x04000019), SH_UNT_PERV_4   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N2_CPLT_CONF1_CLEAR                                , RULL(0x04000029), SH_UNT_PERV_4   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N3_CPLT_CONF1                                      , RULL(0x05000009), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_CPLT_CONF1_OR                                   , RULL(0x05000019), SH_UNT_PERV_5   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N3_CPLT_CONF1_CLEAR                                , RULL(0x05000029), SH_UNT_PERV_5   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_XB_CPLT_CONF1                                      , RULL(0x06000009), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_CPLT_CONF1_OR                                   , RULL(0x06000019), SH_UNT_PERV_6   , SH_ACS_SCOM1_OR  );
+REG64( PERV_XB_CPLT_CONF1_CLEAR                                , RULL(0x06000029), SH_UNT_PERV_6   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC01_CPLT_CONF1                                    , RULL(0x07000009), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_CPLT_CONF1_OR                                 , RULL(0x07000019), SH_UNT_PERV_7   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC01_CPLT_CONF1_CLEAR                              , RULL(0x07000029), SH_UNT_PERV_7   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC23_CPLT_CONF1                                    , RULL(0x08000009), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_CPLT_CONF1_OR                                 , RULL(0x08000019), SH_UNT_PERV_8   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC23_CPLT_CONF1_CLEAR                              , RULL(0x08000029), SH_UNT_PERV_8   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB0_CPLT_CONF1                                     , RULL(0x09000009), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_CPLT_CONF1_OR                                  , RULL(0x09000019), SH_UNT_PERV_9   , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB0_CPLT_CONF1_CLEAR                               , RULL(0x09000029), SH_UNT_PERV_9   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB3_CPLT_CONF1                                     , RULL(0x0C000009), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_CPLT_CONF1_OR                                  , RULL(0x0C000019), SH_UNT_PERV_12  , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB3_CPLT_CONF1_CLEAR                               , RULL(0x0C000029), SH_UNT_PERV_12  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI0_CPLT_CONF1                                    , RULL(0x0D000009), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_CPLT_CONF1_OR                                 , RULL(0x0D000019), SH_UNT_PERV_13  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI0_CPLT_CONF1_CLEAR                              , RULL(0x0D000029), SH_UNT_PERV_13  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI1_CPLT_CONF1                                    , RULL(0x0E000009), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_CPLT_CONF1_OR                                 , RULL(0x0E000019), SH_UNT_PERV_14  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI1_CPLT_CONF1_CLEAR                              , RULL(0x0E000029), SH_UNT_PERV_14  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI2_CPLT_CONF1                                    , RULL(0x0F000009), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_CPLT_CONF1_OR                                 , RULL(0x0F000019), SH_UNT_PERV_15  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI2_CPLT_CONF1_CLEAR                              , RULL(0x0F000029), SH_UNT_PERV_15  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP00_CPLT_CONF1                                    , RULL(0x10000009), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_CPLT_CONF1_OR                                 , RULL(0x10000019), SH_UNT_PERV_16  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP00_CPLT_CONF1_CLEAR                              , RULL(0x10000029), SH_UNT_PERV_16  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP01_CPLT_CONF1                                    , RULL(0x11000009), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_CPLT_CONF1_OR                                 , RULL(0x11000019), SH_UNT_PERV_17  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP01_CPLT_CONF1_CLEAR                              , RULL(0x11000029), SH_UNT_PERV_17  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP02_CPLT_CONF1                                    , RULL(0x12000009), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_CPLT_CONF1_OR                                 , RULL(0x12000019), SH_UNT_PERV_18  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP02_CPLT_CONF1_CLEAR                              , RULL(0x12000029), SH_UNT_PERV_18  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP03_CPLT_CONF1                                    , RULL(0x13000009), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_CPLT_CONF1_OR                                 , RULL(0x13000019), SH_UNT_PERV_19  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP03_CPLT_CONF1_CLEAR                              , RULL(0x13000029), SH_UNT_PERV_19  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP04_CPLT_CONF1                                    , RULL(0x14000009), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_CPLT_CONF1_OR                                 , RULL(0x14000019), SH_UNT_PERV_20  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP04_CPLT_CONF1_CLEAR                              , RULL(0x14000029), SH_UNT_PERV_20  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP05_CPLT_CONF1                                    , RULL(0x15000009), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_CPLT_CONF1_OR                                 , RULL(0x15000019), SH_UNT_PERV_21  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP05_CPLT_CONF1_CLEAR                              , RULL(0x15000029), SH_UNT_PERV_21  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC00_CPLT_CONF1                                    , RULL(0x20000009), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPLT_CONF1_OR                                 , RULL(0x20000019), SH_UNT_PERV_32  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC00_CPLT_CONF1_CLEAR                              , RULL(0x20000029), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC01_CPLT_CONF1                                    , RULL(0x21000009), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPLT_CONF1_OR                                 , RULL(0x21000019), SH_UNT_PERV_33  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC01_CPLT_CONF1_CLEAR                              , RULL(0x21000029), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC02_CPLT_CONF1                                    , RULL(0x22000009), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPLT_CONF1_OR                                 , RULL(0x22000019), SH_UNT_PERV_34  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC02_CPLT_CONF1_CLEAR                              , RULL(0x22000029), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC03_CPLT_CONF1                                    , RULL(0x23000009), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPLT_CONF1_OR                                 , RULL(0x23000019), SH_UNT_PERV_35  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC03_CPLT_CONF1_CLEAR                              , RULL(0x23000029), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC04_CPLT_CONF1                                    , RULL(0x24000009), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPLT_CONF1_OR                                 , RULL(0x24000019), SH_UNT_PERV_36  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC04_CPLT_CONF1_CLEAR                              , RULL(0x24000029), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC05_CPLT_CONF1                                    , RULL(0x25000009), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPLT_CONF1_OR                                 , RULL(0x25000019), SH_UNT_PERV_37  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC05_CPLT_CONF1_CLEAR                              , RULL(0x25000029), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC06_CPLT_CONF1                                    , RULL(0x26000009), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPLT_CONF1_OR                                 , RULL(0x26000019), SH_UNT_PERV_38  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC06_CPLT_CONF1_CLEAR                              , RULL(0x26000029), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC07_CPLT_CONF1                                    , RULL(0x27000009), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPLT_CONF1_OR                                 , RULL(0x27000019), SH_UNT_PERV_39  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC07_CPLT_CONF1_CLEAR                              , RULL(0x27000029), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC08_CPLT_CONF1                                    , RULL(0x28000009), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPLT_CONF1_OR                                 , RULL(0x28000019), SH_UNT_PERV_40  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC08_CPLT_CONF1_CLEAR                              , RULL(0x28000029), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC09_CPLT_CONF1                                    , RULL(0x29000009), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPLT_CONF1_OR                                 , RULL(0x29000019), SH_UNT_PERV_41  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC09_CPLT_CONF1_CLEAR                              , RULL(0x29000029), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC10_CPLT_CONF1                                    , RULL(0x2A000009), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPLT_CONF1_OR                                 , RULL(0x2A000019), SH_UNT_PERV_42  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC10_CPLT_CONF1_CLEAR                              , RULL(0x2A000029), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC11_CPLT_CONF1                                    , RULL(0x2B000009), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPLT_CONF1_OR                                 , RULL(0x2B000019), SH_UNT_PERV_43  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC11_CPLT_CONF1_CLEAR                              , RULL(0x2B000029), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC12_CPLT_CONF1                                    , RULL(0x2C000009), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPLT_CONF1_OR                                 , RULL(0x2C000019), SH_UNT_PERV_44  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC12_CPLT_CONF1_CLEAR                              , RULL(0x2C000029), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC13_CPLT_CONF1                                    , RULL(0x2D000009), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPLT_CONF1_OR                                 , RULL(0x2D000019), SH_UNT_PERV_45  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC13_CPLT_CONF1_CLEAR                              , RULL(0x2D000029), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC14_CPLT_CONF1                                    , RULL(0x2E000009), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPLT_CONF1_OR                                 , RULL(0x2E000019), SH_UNT_PERV_46  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC14_CPLT_CONF1_CLEAR                              , RULL(0x2E000029), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC15_CPLT_CONF1                                    , RULL(0x2F000009), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPLT_CONF1_OR                                 , RULL(0x2F000019), SH_UNT_PERV_47  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC15_CPLT_CONF1_CLEAR                              , RULL(0x2F000029), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC16_CPLT_CONF1                                    , RULL(0x30000009), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPLT_CONF1_OR                                 , RULL(0x30000019), SH_UNT_PERV_48  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC16_CPLT_CONF1_CLEAR                              , RULL(0x30000029), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC17_CPLT_CONF1                                    , RULL(0x31000009), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPLT_CONF1_OR                                 , RULL(0x31000019), SH_UNT_PERV_49  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC17_CPLT_CONF1_CLEAR                              , RULL(0x31000029), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC18_CPLT_CONF1                                    , RULL(0x32000009), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPLT_CONF1_OR                                 , RULL(0x32000019), SH_UNT_PERV_50  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC18_CPLT_CONF1_CLEAR                              , RULL(0x32000029), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC19_CPLT_CONF1                                    , RULL(0x33000009), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPLT_CONF1_OR                                 , RULL(0x33000019), SH_UNT_PERV_51  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC19_CPLT_CONF1_CLEAR                              , RULL(0x33000029), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC20_CPLT_CONF1                                    , RULL(0x34000009), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPLT_CONF1_OR                                 , RULL(0x34000019), SH_UNT_PERV_52  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC20_CPLT_CONF1_CLEAR                              , RULL(0x34000029), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC21_CPLT_CONF1                                    , RULL(0x35000009), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPLT_CONF1_OR                                 , RULL(0x35000019), SH_UNT_PERV_53  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC21_CPLT_CONF1_CLEAR                              , RULL(0x35000029), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC22_CPLT_CONF1                                    , RULL(0x36000009), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPLT_CONF1_OR                                 , RULL(0x36000019), SH_UNT_PERV_54  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC22_CPLT_CONF1_CLEAR                              , RULL(0x36000029), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC23_CPLT_CONF1                                    , RULL(0x37000009), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPLT_CONF1_OR                                 , RULL(0x37000019), SH_UNT_PERV_55  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC23_CPLT_CONF1_CLEAR                              , RULL(0x37000029), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM2_CLEAR );
+
+REG64( PERV_CPLT_CTRL0                                         , RULL(0x00000000), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_CPLT_CTRL0                                      , RULL(0x01000000), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_CPLT_CTRL0_OR                                      , RULL(0x00000010), SH_UNT_PERV     , SH_ACS_SCOM1_OR  );
+REG64( PERV_TP_CPLT_CTRL0_OR                                   , RULL(0x01000010), SH_UNT_PERV_1   , SH_ACS_SCOM1_OR  );
+REG64( PERV_CPLT_CTRL0_CLEAR                                   , RULL(0x00000020), SH_UNT_PERV     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_TP_CPLT_CTRL0_CLEAR                                , RULL(0x01000020), SH_UNT_PERV_1   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N0_CPLT_CTRL0                                      , RULL(0x02000000), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_CPLT_CTRL0_OR                                   , RULL(0x02000010), SH_UNT_PERV_2   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N0_CPLT_CTRL0_CLEAR                                , RULL(0x02000020), SH_UNT_PERV_2   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N1_CPLT_CTRL0                                      , RULL(0x03000000), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_CPLT_CTRL0_OR                                   , RULL(0x03000010), SH_UNT_PERV_3   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N1_CPLT_CTRL0_CLEAR                                , RULL(0x03000020), SH_UNT_PERV_3   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N2_CPLT_CTRL0                                      , RULL(0x04000000), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_CPLT_CTRL0_OR                                   , RULL(0x04000010), SH_UNT_PERV_4   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N2_CPLT_CTRL0_CLEAR                                , RULL(0x04000020), SH_UNT_PERV_4   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N3_CPLT_CTRL0                                      , RULL(0x05000000), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_CPLT_CTRL0_OR                                   , RULL(0x05000010), SH_UNT_PERV_5   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N3_CPLT_CTRL0_CLEAR                                , RULL(0x05000020), SH_UNT_PERV_5   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_XB_CPLT_CTRL0                                      , RULL(0x06000000), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_CPLT_CTRL0_OR                                   , RULL(0x06000010), SH_UNT_PERV_6   , SH_ACS_SCOM1_OR  );
+REG64( PERV_XB_CPLT_CTRL0_CLEAR                                , RULL(0x06000020), SH_UNT_PERV_6   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC01_CPLT_CTRL0                                    , RULL(0x07000000), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_CPLT_CTRL0_OR                                 , RULL(0x07000010), SH_UNT_PERV_7   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC01_CPLT_CTRL0_CLEAR                              , RULL(0x07000020), SH_UNT_PERV_7   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC23_CPLT_CTRL0                                    , RULL(0x08000000), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_CPLT_CTRL0_OR                                 , RULL(0x08000010), SH_UNT_PERV_8   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC23_CPLT_CTRL0_CLEAR                              , RULL(0x08000020), SH_UNT_PERV_8   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB0_CPLT_CTRL0                                     , RULL(0x09000000), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_CPLT_CTRL0_OR                                  , RULL(0x09000010), SH_UNT_PERV_9   , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB0_CPLT_CTRL0_CLEAR                               , RULL(0x09000020), SH_UNT_PERV_9   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB3_CPLT_CTRL0                                     , RULL(0x0C000000), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_CPLT_CTRL0_OR                                  , RULL(0x0C000010), SH_UNT_PERV_12  , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB3_CPLT_CTRL0_CLEAR                               , RULL(0x0C000020), SH_UNT_PERV_12  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI0_CPLT_CTRL0                                    , RULL(0x0D000000), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_CPLT_CTRL0_OR                                 , RULL(0x0D000010), SH_UNT_PERV_13  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI0_CPLT_CTRL0_CLEAR                              , RULL(0x0D000020), SH_UNT_PERV_13  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI1_CPLT_CTRL0                                    , RULL(0x0E000000), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_CPLT_CTRL0_OR                                 , RULL(0x0E000010), SH_UNT_PERV_14  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI1_CPLT_CTRL0_CLEAR                              , RULL(0x0E000020), SH_UNT_PERV_14  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI2_CPLT_CTRL0                                    , RULL(0x0F000000), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_CPLT_CTRL0_OR                                 , RULL(0x0F000010), SH_UNT_PERV_15  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI2_CPLT_CTRL0_CLEAR                              , RULL(0x0F000020), SH_UNT_PERV_15  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP00_CPLT_CTRL0                                    , RULL(0x10000000), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_CPLT_CTRL0_OR                                 , RULL(0x10000010), SH_UNT_PERV_16  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP00_CPLT_CTRL0_CLEAR                              , RULL(0x10000020), SH_UNT_PERV_16  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP01_CPLT_CTRL0                                    , RULL(0x11000000), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_CPLT_CTRL0_OR                                 , RULL(0x11000010), SH_UNT_PERV_17  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP01_CPLT_CTRL0_CLEAR                              , RULL(0x11000020), SH_UNT_PERV_17  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP02_CPLT_CTRL0                                    , RULL(0x12000000), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_CPLT_CTRL0_OR                                 , RULL(0x12000010), SH_UNT_PERV_18  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP02_CPLT_CTRL0_CLEAR                              , RULL(0x12000020), SH_UNT_PERV_18  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP03_CPLT_CTRL0                                    , RULL(0x13000000), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_CPLT_CTRL0_OR                                 , RULL(0x13000010), SH_UNT_PERV_19  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP03_CPLT_CTRL0_CLEAR                              , RULL(0x13000020), SH_UNT_PERV_19  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP04_CPLT_CTRL0                                    , RULL(0x14000000), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_CPLT_CTRL0_OR                                 , RULL(0x14000010), SH_UNT_PERV_20  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP04_CPLT_CTRL0_CLEAR                              , RULL(0x14000020), SH_UNT_PERV_20  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP05_CPLT_CTRL0                                    , RULL(0x15000000), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_CPLT_CTRL0_OR                                 , RULL(0x15000010), SH_UNT_PERV_21  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP05_CPLT_CTRL0_CLEAR                              , RULL(0x15000020), SH_UNT_PERV_21  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC00_CPLT_CTRL0                                    , RULL(0x20000000), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPLT_CTRL0_OR                                 , RULL(0x20000010), SH_UNT_PERV_32  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC00_CPLT_CTRL0_CLEAR                              , RULL(0x20000020), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC01_CPLT_CTRL0                                    , RULL(0x21000000), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPLT_CTRL0_OR                                 , RULL(0x21000010), SH_UNT_PERV_33  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC01_CPLT_CTRL0_CLEAR                              , RULL(0x21000020), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC02_CPLT_CTRL0                                    , RULL(0x22000000), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPLT_CTRL0_OR                                 , RULL(0x22000010), SH_UNT_PERV_34  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC02_CPLT_CTRL0_CLEAR                              , RULL(0x22000020), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC03_CPLT_CTRL0                                    , RULL(0x23000000), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPLT_CTRL0_OR                                 , RULL(0x23000010), SH_UNT_PERV_35  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC03_CPLT_CTRL0_CLEAR                              , RULL(0x23000020), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC04_CPLT_CTRL0                                    , RULL(0x24000000), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPLT_CTRL0_OR                                 , RULL(0x24000010), SH_UNT_PERV_36  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC04_CPLT_CTRL0_CLEAR                              , RULL(0x24000020), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC05_CPLT_CTRL0                                    , RULL(0x25000000), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPLT_CTRL0_OR                                 , RULL(0x25000010), SH_UNT_PERV_37  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC05_CPLT_CTRL0_CLEAR                              , RULL(0x25000020), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC06_CPLT_CTRL0                                    , RULL(0x26000000), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPLT_CTRL0_OR                                 , RULL(0x26000010), SH_UNT_PERV_38  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC06_CPLT_CTRL0_CLEAR                              , RULL(0x26000020), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC07_CPLT_CTRL0                                    , RULL(0x27000000), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPLT_CTRL0_OR                                 , RULL(0x27000010), SH_UNT_PERV_39  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC07_CPLT_CTRL0_CLEAR                              , RULL(0x27000020), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC08_CPLT_CTRL0                                    , RULL(0x28000000), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPLT_CTRL0_OR                                 , RULL(0x28000010), SH_UNT_PERV_40  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC08_CPLT_CTRL0_CLEAR                              , RULL(0x28000020), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC09_CPLT_CTRL0                                    , RULL(0x29000000), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPLT_CTRL0_OR                                 , RULL(0x29000010), SH_UNT_PERV_41  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC09_CPLT_CTRL0_CLEAR                              , RULL(0x29000020), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC10_CPLT_CTRL0                                    , RULL(0x2A000000), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPLT_CTRL0_OR                                 , RULL(0x2A000010), SH_UNT_PERV_42  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC10_CPLT_CTRL0_CLEAR                              , RULL(0x2A000020), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC11_CPLT_CTRL0                                    , RULL(0x2B000000), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPLT_CTRL0_OR                                 , RULL(0x2B000010), SH_UNT_PERV_43  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC11_CPLT_CTRL0_CLEAR                              , RULL(0x2B000020), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC12_CPLT_CTRL0                                    , RULL(0x2C000000), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPLT_CTRL0_OR                                 , RULL(0x2C000010), SH_UNT_PERV_44  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC12_CPLT_CTRL0_CLEAR                              , RULL(0x2C000020), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC13_CPLT_CTRL0                                    , RULL(0x2D000000), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPLT_CTRL0_OR                                 , RULL(0x2D000010), SH_UNT_PERV_45  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC13_CPLT_CTRL0_CLEAR                              , RULL(0x2D000020), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC14_CPLT_CTRL0                                    , RULL(0x2E000000), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPLT_CTRL0_OR                                 , RULL(0x2E000010), SH_UNT_PERV_46  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC14_CPLT_CTRL0_CLEAR                              , RULL(0x2E000020), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC15_CPLT_CTRL0                                    , RULL(0x2F000000), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPLT_CTRL0_OR                                 , RULL(0x2F000010), SH_UNT_PERV_47  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC15_CPLT_CTRL0_CLEAR                              , RULL(0x2F000020), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC16_CPLT_CTRL0                                    , RULL(0x30000000), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPLT_CTRL0_OR                                 , RULL(0x30000010), SH_UNT_PERV_48  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC16_CPLT_CTRL0_CLEAR                              , RULL(0x30000020), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC17_CPLT_CTRL0                                    , RULL(0x31000000), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPLT_CTRL0_OR                                 , RULL(0x31000010), SH_UNT_PERV_49  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC17_CPLT_CTRL0_CLEAR                              , RULL(0x31000020), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC18_CPLT_CTRL0                                    , RULL(0x32000000), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPLT_CTRL0_OR                                 , RULL(0x32000010), SH_UNT_PERV_50  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC18_CPLT_CTRL0_CLEAR                              , RULL(0x32000020), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC19_CPLT_CTRL0                                    , RULL(0x33000000), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPLT_CTRL0_OR                                 , RULL(0x33000010), SH_UNT_PERV_51  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC19_CPLT_CTRL0_CLEAR                              , RULL(0x33000020), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC20_CPLT_CTRL0                                    , RULL(0x34000000), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPLT_CTRL0_OR                                 , RULL(0x34000010), SH_UNT_PERV_52  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC20_CPLT_CTRL0_CLEAR                              , RULL(0x34000020), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC21_CPLT_CTRL0                                    , RULL(0x35000000), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPLT_CTRL0_OR                                 , RULL(0x35000010), SH_UNT_PERV_53  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC21_CPLT_CTRL0_CLEAR                              , RULL(0x35000020), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC22_CPLT_CTRL0                                    , RULL(0x36000000), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPLT_CTRL0_OR                                 , RULL(0x36000010), SH_UNT_PERV_54  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC22_CPLT_CTRL0_CLEAR                              , RULL(0x36000020), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC23_CPLT_CTRL0                                    , RULL(0x37000000), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPLT_CTRL0_OR                                 , RULL(0x37000010), SH_UNT_PERV_55  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC23_CPLT_CTRL0_CLEAR                              , RULL(0x37000020), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM2_CLEAR );
+
+REG64( PERV_CPLT_CTRL1                                         , RULL(0x00000001), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_CPLT_CTRL1                                      , RULL(0x01000001), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_CPLT_CTRL1_OR                                      , RULL(0x00000011), SH_UNT_PERV     , SH_ACS_SCOM1_OR  );
+REG64( PERV_TP_CPLT_CTRL1_OR                                   , RULL(0x01000011), SH_UNT_PERV_1   , SH_ACS_SCOM1_OR  );
+REG64( PERV_CPLT_CTRL1_CLEAR                                   , RULL(0x00000021), SH_UNT_PERV     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_TP_CPLT_CTRL1_CLEAR                                , RULL(0x01000021), SH_UNT_PERV_1   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N0_CPLT_CTRL1                                      , RULL(0x02000001), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_CPLT_CTRL1_OR                                   , RULL(0x02000011), SH_UNT_PERV_2   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N0_CPLT_CTRL1_CLEAR                                , RULL(0x02000021), SH_UNT_PERV_2   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N1_CPLT_CTRL1                                      , RULL(0x03000001), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_CPLT_CTRL1_OR                                   , RULL(0x03000011), SH_UNT_PERV_3   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N1_CPLT_CTRL1_CLEAR                                , RULL(0x03000021), SH_UNT_PERV_3   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N2_CPLT_CTRL1                                      , RULL(0x04000001), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_CPLT_CTRL1_OR                                   , RULL(0x04000011), SH_UNT_PERV_4   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N2_CPLT_CTRL1_CLEAR                                , RULL(0x04000021), SH_UNT_PERV_4   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_N3_CPLT_CTRL1                                      , RULL(0x05000001), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_CPLT_CTRL1_OR                                   , RULL(0x05000011), SH_UNT_PERV_5   , SH_ACS_SCOM1_OR  );
+REG64( PERV_N3_CPLT_CTRL1_CLEAR                                , RULL(0x05000021), SH_UNT_PERV_5   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_XB_CPLT_CTRL1                                      , RULL(0x06000001), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_CPLT_CTRL1_OR                                   , RULL(0x06000011), SH_UNT_PERV_6   , SH_ACS_SCOM1_OR  );
+REG64( PERV_XB_CPLT_CTRL1_CLEAR                                , RULL(0x06000021), SH_UNT_PERV_6   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC01_CPLT_CTRL1                                    , RULL(0x07000001), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_CPLT_CTRL1_OR                                 , RULL(0x07000011), SH_UNT_PERV_7   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC01_CPLT_CTRL1_CLEAR                              , RULL(0x07000021), SH_UNT_PERV_7   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_MC23_CPLT_CTRL1                                    , RULL(0x08000001), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_CPLT_CTRL1_OR                                 , RULL(0x08000011), SH_UNT_PERV_8   , SH_ACS_SCOM1_OR  );
+REG64( PERV_MC23_CPLT_CTRL1_CLEAR                              , RULL(0x08000021), SH_UNT_PERV_8   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB0_CPLT_CTRL1                                     , RULL(0x09000001), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_CPLT_CTRL1_OR                                  , RULL(0x09000011), SH_UNT_PERV_9   , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB0_CPLT_CTRL1_CLEAR                               , RULL(0x09000021), SH_UNT_PERV_9   ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_OB3_CPLT_CTRL1                                     , RULL(0x0C000001), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_CPLT_CTRL1_OR                                  , RULL(0x0C000011), SH_UNT_PERV_12  , SH_ACS_SCOM1_OR  );
+REG64( PERV_OB3_CPLT_CTRL1_CLEAR                               , RULL(0x0C000021), SH_UNT_PERV_12  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI0_CPLT_CTRL1                                    , RULL(0x0D000001), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_CPLT_CTRL1_OR                                 , RULL(0x0D000011), SH_UNT_PERV_13  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI0_CPLT_CTRL1_CLEAR                              , RULL(0x0D000021), SH_UNT_PERV_13  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI1_CPLT_CTRL1                                    , RULL(0x0E000001), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_CPLT_CTRL1_OR                                 , RULL(0x0E000011), SH_UNT_PERV_14  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI1_CPLT_CTRL1_CLEAR                              , RULL(0x0E000021), SH_UNT_PERV_14  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_PCI2_CPLT_CTRL1                                    , RULL(0x0F000001), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_CPLT_CTRL1_OR                                 , RULL(0x0F000011), SH_UNT_PERV_15  , SH_ACS_SCOM1_OR  );
+REG64( PERV_PCI2_CPLT_CTRL1_CLEAR                              , RULL(0x0F000021), SH_UNT_PERV_15  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP00_CPLT_CTRL1                                    , RULL(0x10000001), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_CPLT_CTRL1_OR                                 , RULL(0x10000011), SH_UNT_PERV_16  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP00_CPLT_CTRL1_CLEAR                              , RULL(0x10000021), SH_UNT_PERV_16  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP01_CPLT_CTRL1                                    , RULL(0x11000001), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_CPLT_CTRL1_OR                                 , RULL(0x11000011), SH_UNT_PERV_17  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP01_CPLT_CTRL1_CLEAR                              , RULL(0x11000021), SH_UNT_PERV_17  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP02_CPLT_CTRL1                                    , RULL(0x12000001), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_CPLT_CTRL1_OR                                 , RULL(0x12000011), SH_UNT_PERV_18  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP02_CPLT_CTRL1_CLEAR                              , RULL(0x12000021), SH_UNT_PERV_18  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP03_CPLT_CTRL1                                    , RULL(0x13000001), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_CPLT_CTRL1_OR                                 , RULL(0x13000011), SH_UNT_PERV_19  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP03_CPLT_CTRL1_CLEAR                              , RULL(0x13000021), SH_UNT_PERV_19  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP04_CPLT_CTRL1                                    , RULL(0x14000001), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_CPLT_CTRL1_OR                                 , RULL(0x14000011), SH_UNT_PERV_20  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP04_CPLT_CTRL1_CLEAR                              , RULL(0x14000021), SH_UNT_PERV_20  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EP05_CPLT_CTRL1                                    , RULL(0x15000001), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_CPLT_CTRL1_OR                                 , RULL(0x15000011), SH_UNT_PERV_21  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EP05_CPLT_CTRL1_CLEAR                              , RULL(0x15000021), SH_UNT_PERV_21  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC00_CPLT_CTRL1                                    , RULL(0x20000001), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPLT_CTRL1_OR                                 , RULL(0x20000011), SH_UNT_PERV_32  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC00_CPLT_CTRL1_CLEAR                              , RULL(0x20000021), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC01_CPLT_CTRL1                                    , RULL(0x21000001), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPLT_CTRL1_OR                                 , RULL(0x21000011), SH_UNT_PERV_33  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC01_CPLT_CTRL1_CLEAR                              , RULL(0x21000021), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC02_CPLT_CTRL1                                    , RULL(0x22000001), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPLT_CTRL1_OR                                 , RULL(0x22000011), SH_UNT_PERV_34  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC02_CPLT_CTRL1_CLEAR                              , RULL(0x22000021), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC03_CPLT_CTRL1                                    , RULL(0x23000001), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPLT_CTRL1_OR                                 , RULL(0x23000011), SH_UNT_PERV_35  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC03_CPLT_CTRL1_CLEAR                              , RULL(0x23000021), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC04_CPLT_CTRL1                                    , RULL(0x24000001), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPLT_CTRL1_OR                                 , RULL(0x24000011), SH_UNT_PERV_36  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC04_CPLT_CTRL1_CLEAR                              , RULL(0x24000021), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC05_CPLT_CTRL1                                    , RULL(0x25000001), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPLT_CTRL1_OR                                 , RULL(0x25000011), SH_UNT_PERV_37  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC05_CPLT_CTRL1_CLEAR                              , RULL(0x25000021), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC06_CPLT_CTRL1                                    , RULL(0x26000001), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPLT_CTRL1_OR                                 , RULL(0x26000011), SH_UNT_PERV_38  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC06_CPLT_CTRL1_CLEAR                              , RULL(0x26000021), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC07_CPLT_CTRL1                                    , RULL(0x27000001), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPLT_CTRL1_OR                                 , RULL(0x27000011), SH_UNT_PERV_39  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC07_CPLT_CTRL1_CLEAR                              , RULL(0x27000021), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC08_CPLT_CTRL1                                    , RULL(0x28000001), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPLT_CTRL1_OR                                 , RULL(0x28000011), SH_UNT_PERV_40  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC08_CPLT_CTRL1_CLEAR                              , RULL(0x28000021), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC09_CPLT_CTRL1                                    , RULL(0x29000001), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPLT_CTRL1_OR                                 , RULL(0x29000011), SH_UNT_PERV_41  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC09_CPLT_CTRL1_CLEAR                              , RULL(0x29000021), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC10_CPLT_CTRL1                                    , RULL(0x2A000001), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPLT_CTRL1_OR                                 , RULL(0x2A000011), SH_UNT_PERV_42  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC10_CPLT_CTRL1_CLEAR                              , RULL(0x2A000021), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC11_CPLT_CTRL1                                    , RULL(0x2B000001), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPLT_CTRL1_OR                                 , RULL(0x2B000011), SH_UNT_PERV_43  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC11_CPLT_CTRL1_CLEAR                              , RULL(0x2B000021), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC12_CPLT_CTRL1                                    , RULL(0x2C000001), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPLT_CTRL1_OR                                 , RULL(0x2C000011), SH_UNT_PERV_44  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC12_CPLT_CTRL1_CLEAR                              , RULL(0x2C000021), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC13_CPLT_CTRL1                                    , RULL(0x2D000001), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPLT_CTRL1_OR                                 , RULL(0x2D000011), SH_UNT_PERV_45  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC13_CPLT_CTRL1_CLEAR                              , RULL(0x2D000021), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC14_CPLT_CTRL1                                    , RULL(0x2E000001), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPLT_CTRL1_OR                                 , RULL(0x2E000011), SH_UNT_PERV_46  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC14_CPLT_CTRL1_CLEAR                              , RULL(0x2E000021), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC15_CPLT_CTRL1                                    , RULL(0x2F000001), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPLT_CTRL1_OR                                 , RULL(0x2F000011), SH_UNT_PERV_47  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC15_CPLT_CTRL1_CLEAR                              , RULL(0x2F000021), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC16_CPLT_CTRL1                                    , RULL(0x30000001), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPLT_CTRL1_OR                                 , RULL(0x30000011), SH_UNT_PERV_48  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC16_CPLT_CTRL1_CLEAR                              , RULL(0x30000021), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC17_CPLT_CTRL1                                    , RULL(0x31000001), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPLT_CTRL1_OR                                 , RULL(0x31000011), SH_UNT_PERV_49  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC17_CPLT_CTRL1_CLEAR                              , RULL(0x31000021), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC18_CPLT_CTRL1                                    , RULL(0x32000001), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPLT_CTRL1_OR                                 , RULL(0x32000011), SH_UNT_PERV_50  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC18_CPLT_CTRL1_CLEAR                              , RULL(0x32000021), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC19_CPLT_CTRL1                                    , RULL(0x33000001), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPLT_CTRL1_OR                                 , RULL(0x33000011), SH_UNT_PERV_51  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC19_CPLT_CTRL1_CLEAR                              , RULL(0x33000021), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC20_CPLT_CTRL1                                    , RULL(0x34000001), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPLT_CTRL1_OR                                 , RULL(0x34000011), SH_UNT_PERV_52  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC20_CPLT_CTRL1_CLEAR                              , RULL(0x34000021), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC21_CPLT_CTRL1                                    , RULL(0x35000001), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPLT_CTRL1_OR                                 , RULL(0x35000011), SH_UNT_PERV_53  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC21_CPLT_CTRL1_CLEAR                              , RULL(0x35000021), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC22_CPLT_CTRL1                                    , RULL(0x36000001), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPLT_CTRL1_OR                                 , RULL(0x36000011), SH_UNT_PERV_54  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC22_CPLT_CTRL1_CLEAR                              , RULL(0x36000021), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( PERV_EC23_CPLT_CTRL1                                    , RULL(0x37000001), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPLT_CTRL1_OR                                 , RULL(0x37000011), SH_UNT_PERV_55  , SH_ACS_SCOM1_OR  );
+REG64( PERV_EC23_CPLT_CTRL1_CLEAR                              , RULL(0x37000021), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM2_CLEAR );
+
+REG64( PERV_CPLT_MASK0                                         , RULL(0x00000101), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_CPLT_MASK0                                      , RULL(0x01000101), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CPLT_MASK0                                      , RULL(0x02000101), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CPLT_MASK0                                      , RULL(0x03000101), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CPLT_MASK0                                      , RULL(0x04000101), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CPLT_MASK0                                      , RULL(0x05000101), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CPLT_MASK0                                      , RULL(0x06000101), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CPLT_MASK0                                    , RULL(0x07000101), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CPLT_MASK0                                    , RULL(0x08000101), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CPLT_MASK0                                     , RULL(0x09000101), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CPLT_MASK0                                     , RULL(0x0C000101), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CPLT_MASK0                                    , RULL(0x0D000101), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CPLT_MASK0                                    , RULL(0x0E000101), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CPLT_MASK0                                    , RULL(0x0F000101), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CPLT_MASK0                                    , RULL(0x10000101), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CPLT_MASK0                                    , RULL(0x11000101), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CPLT_MASK0                                    , RULL(0x12000101), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CPLT_MASK0                                    , RULL(0x13000101), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CPLT_MASK0                                    , RULL(0x14000101), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CPLT_MASK0                                    , RULL(0x15000101), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CPLT_MASK0                                    , RULL(0x20000101), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CPLT_MASK0                                    , RULL(0x21000101), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CPLT_MASK0                                    , RULL(0x22000101), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CPLT_MASK0                                    , RULL(0x23000101), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CPLT_MASK0                                    , RULL(0x24000101), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CPLT_MASK0                                    , RULL(0x25000101), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CPLT_MASK0                                    , RULL(0x26000101), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CPLT_MASK0                                    , RULL(0x27000101), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CPLT_MASK0                                    , RULL(0x28000101), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CPLT_MASK0                                    , RULL(0x29000101), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CPLT_MASK0                                    , RULL(0x2A000101), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CPLT_MASK0                                    , RULL(0x2B000101), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CPLT_MASK0                                    , RULL(0x2C000101), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CPLT_MASK0                                    , RULL(0x2D000101), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CPLT_MASK0                                    , RULL(0x2E000101), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CPLT_MASK0                                    , RULL(0x2F000101), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CPLT_MASK0                                    , RULL(0x30000101), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CPLT_MASK0                                    , RULL(0x31000101), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CPLT_MASK0                                    , RULL(0x32000101), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CPLT_MASK0                                    , RULL(0x33000101), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CPLT_MASK0                                    , RULL(0x34000101), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CPLT_MASK0                                    , RULL(0x35000101), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CPLT_MASK0                                    , RULL(0x36000101), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CPLT_MASK0                                    , RULL(0x37000101), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CPLT_STAT0                                         , RULL(0x00000100), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_CPLT_STAT0                                      , RULL(0x01000100), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CPLT_STAT0                                      , RULL(0x02000100), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CPLT_STAT0                                      , RULL(0x03000100), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CPLT_STAT0                                      , RULL(0x04000100), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CPLT_STAT0                                      , RULL(0x05000100), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CPLT_STAT0                                      , RULL(0x06000100), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CPLT_STAT0                                    , RULL(0x07000100), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CPLT_STAT0                                    , RULL(0x08000100), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CPLT_STAT0                                     , RULL(0x09000100), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CPLT_STAT0                                     , RULL(0x0C000100), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CPLT_STAT0                                    , RULL(0x0D000100), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CPLT_STAT0                                    , RULL(0x0E000100), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CPLT_STAT0                                    , RULL(0x0F000100), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CPLT_STAT0                                    , RULL(0x10000100), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CPLT_STAT0                                    , RULL(0x11000100), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CPLT_STAT0                                    , RULL(0x12000100), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CPLT_STAT0                                    , RULL(0x13000100), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CPLT_STAT0                                    , RULL(0x14000100), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CPLT_STAT0                                    , RULL(0x15000100), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CPLT_STAT0                                    , RULL(0x20000100), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CPLT_STAT0                                    , RULL(0x21000100), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CPLT_STAT0                                    , RULL(0x22000100), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CPLT_STAT0                                    , RULL(0x23000100), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CPLT_STAT0                                    , RULL(0x24000100), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CPLT_STAT0                                    , RULL(0x25000100), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CPLT_STAT0                                    , RULL(0x26000100), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CPLT_STAT0                                    , RULL(0x27000100), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CPLT_STAT0                                    , RULL(0x28000100), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CPLT_STAT0                                    , RULL(0x29000100), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CPLT_STAT0                                    , RULL(0x2A000100), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CPLT_STAT0                                    , RULL(0x2B000100), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CPLT_STAT0                                    , RULL(0x2C000100), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CPLT_STAT0                                    , RULL(0x2D000100), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CPLT_STAT0                                    , RULL(0x2E000100), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CPLT_STAT0                                    , RULL(0x2F000100), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CPLT_STAT0                                    , RULL(0x30000100), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CPLT_STAT0                                    , RULL(0x31000100), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CPLT_STAT0                                    , RULL(0x32000100), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CPLT_STAT0                                    , RULL(0x33000100), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CPLT_STAT0                                    , RULL(0x34000100), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CPLT_STAT0                                    , RULL(0x35000100), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CPLT_STAT0                                    , RULL(0x36000100), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CPLT_STAT0                                    , RULL(0x37000100), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EC00_CPPM_CACCR                                    , RULL(0x200F0168), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CACCR_CLEAR                              , RULL(0x200F0169), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CACCR_OR                                 , RULL(0x200F016A), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CACCR                                    , RULL(0x210F0168), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CACCR_CLEAR                              , RULL(0x210F0169), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CACCR_OR                                 , RULL(0x210F016A), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CACCR                                    , RULL(0x220F0168), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CACCR_CLEAR                              , RULL(0x220F0169), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CACCR_OR                                 , RULL(0x220F016A), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CACCR                                    , RULL(0x230F0168), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CACCR_CLEAR                              , RULL(0x230F0169), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CACCR_OR                                 , RULL(0x230F016A), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CACCR                                    , RULL(0x240F0168), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CACCR_CLEAR                              , RULL(0x240F0169), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CACCR_OR                                 , RULL(0x240F016A), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CACCR                                    , RULL(0x250F0168), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CACCR_CLEAR                              , RULL(0x250F0169), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CACCR_OR                                 , RULL(0x250F016A), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CACCR                                    , RULL(0x260F0168), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CACCR_CLEAR                              , RULL(0x260F0169), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CACCR_OR                                 , RULL(0x260F016A), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CACCR                                    , RULL(0x270F0168), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CACCR_CLEAR                              , RULL(0x270F0169), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CACCR_OR                                 , RULL(0x270F016A), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CACCR                                    , RULL(0x280F0168), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CACCR_CLEAR                              , RULL(0x280F0169), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CACCR_OR                                 , RULL(0x280F016A), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CACCR                                    , RULL(0x290F0168), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CACCR_CLEAR                              , RULL(0x290F0169), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CACCR_OR                                 , RULL(0x290F016A), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CACCR                                    , RULL(0x2A0F0168), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CACCR_CLEAR                              , RULL(0x2A0F0169), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CACCR_OR                                 , RULL(0x2A0F016A), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CACCR                                    , RULL(0x2B0F0168), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CACCR_CLEAR                              , RULL(0x2B0F0169), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CACCR_OR                                 , RULL(0x2B0F016A), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CACCR                                    , RULL(0x2C0F0168), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CACCR_CLEAR                              , RULL(0x2C0F0169), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CACCR_OR                                 , RULL(0x2C0F016A), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CACCR                                    , RULL(0x2D0F0168), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CACCR_CLEAR                              , RULL(0x2D0F0169), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CACCR_OR                                 , RULL(0x2D0F016A), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CACCR                                    , RULL(0x2E0F0168), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CACCR_CLEAR                              , RULL(0x2E0F0169), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CACCR_OR                                 , RULL(0x2E0F016A), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CACCR                                    , RULL(0x2F0F0168), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CACCR_CLEAR                              , RULL(0x2F0F0169), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CACCR_OR                                 , RULL(0x2F0F016A), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CACCR                                    , RULL(0x300F0168), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CACCR_CLEAR                              , RULL(0x300F0169), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CACCR_OR                                 , RULL(0x300F016A), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CACCR                                    , RULL(0x310F0168), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CACCR_CLEAR                              , RULL(0x310F0169), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CACCR_OR                                 , RULL(0x310F016A), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CACCR                                    , RULL(0x320F0168), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CACCR_CLEAR                              , RULL(0x320F0169), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CACCR_OR                                 , RULL(0x320F016A), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CACCR                                    , RULL(0x330F0168), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CACCR_CLEAR                              , RULL(0x330F0169), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CACCR_OR                                 , RULL(0x330F016A), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CACCR                                    , RULL(0x340F0168), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CACCR_CLEAR                              , RULL(0x340F0169), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CACCR_OR                                 , RULL(0x340F016A), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CACCR                                    , RULL(0x350F0168), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CACCR_CLEAR                              , RULL(0x350F0169), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CACCR_OR                                 , RULL(0x350F016A), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CACCR                                    , RULL(0x360F0168), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CACCR_CLEAR                              , RULL(0x360F0169), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CACCR_OR                                 , RULL(0x360F016A), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CACCR                                    , RULL(0x370F0168), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CACCR_CLEAR                              , RULL(0x370F0169), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CACCR_OR                                 , RULL(0x370F016A), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_CACSR                                    , RULL(0x200F016B), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_CPPM_CACSR                                    , RULL(0x210F016B), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_CPPM_CACSR                                    , RULL(0x220F016B), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_CPPM_CACSR                                    , RULL(0x230F016B), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_CPPM_CACSR                                    , RULL(0x240F016B), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_CPPM_CACSR                                    , RULL(0x250F016B), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_CPPM_CACSR                                    , RULL(0x260F016B), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_CPPM_CACSR                                    , RULL(0x270F016B), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_CPPM_CACSR                                    , RULL(0x280F016B), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_CPPM_CACSR                                    , RULL(0x290F016B), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_CPPM_CACSR                                    , RULL(0x2A0F016B), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_CPPM_CACSR                                    , RULL(0x2B0F016B), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_CPPM_CACSR                                    , RULL(0x2C0F016B), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_CPPM_CACSR                                    , RULL(0x2D0F016B), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_CPPM_CACSR                                    , RULL(0x2E0F016B), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_CPPM_CACSR                                    , RULL(0x2F0F016B), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_CPPM_CACSR                                    , RULL(0x300F016B), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_CPPM_CACSR                                    , RULL(0x310F016B), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_CPPM_CACSR                                    , RULL(0x320F016B), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_CPPM_CACSR                                    , RULL(0x330F016B), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_CPPM_CACSR                                    , RULL(0x340F016B), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_CPPM_CACSR                                    , RULL(0x350F016B), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_CPPM_CACSR                                    , RULL(0x360F016B), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_CPPM_CACSR                                    , RULL(0x370F016B), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EC00_CPPM_CIIR                                     , RULL(0x200F01AD), SH_UNT_PERV_32  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC01_CPPM_CIIR                                     , RULL(0x210F01AD), SH_UNT_PERV_33  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC02_CPPM_CIIR                                     , RULL(0x220F01AD), SH_UNT_PERV_34  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC03_CPPM_CIIR                                     , RULL(0x230F01AD), SH_UNT_PERV_35  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC04_CPPM_CIIR                                     , RULL(0x240F01AD), SH_UNT_PERV_36  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC05_CPPM_CIIR                                     , RULL(0x250F01AD), SH_UNT_PERV_37  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC06_CPPM_CIIR                                     , RULL(0x260F01AD), SH_UNT_PERV_38  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC07_CPPM_CIIR                                     , RULL(0x270F01AD), SH_UNT_PERV_39  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC08_CPPM_CIIR                                     , RULL(0x280F01AD), SH_UNT_PERV_40  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC09_CPPM_CIIR                                     , RULL(0x290F01AD), SH_UNT_PERV_41  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC10_CPPM_CIIR                                     , RULL(0x2A0F01AD), SH_UNT_PERV_42  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC11_CPPM_CIIR                                     , RULL(0x2B0F01AD), SH_UNT_PERV_43  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC12_CPPM_CIIR                                     , RULL(0x2C0F01AD), SH_UNT_PERV_44  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC13_CPPM_CIIR                                     , RULL(0x2D0F01AD), SH_UNT_PERV_45  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC14_CPPM_CIIR                                     , RULL(0x2E0F01AD), SH_UNT_PERV_46  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC15_CPPM_CIIR                                     , RULL(0x2F0F01AD), SH_UNT_PERV_47  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC16_CPPM_CIIR                                     , RULL(0x300F01AD), SH_UNT_PERV_48  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC17_CPPM_CIIR                                     , RULL(0x310F01AD), SH_UNT_PERV_49  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC18_CPPM_CIIR                                     , RULL(0x320F01AD), SH_UNT_PERV_50  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC19_CPPM_CIIR                                     , RULL(0x330F01AD), SH_UNT_PERV_51  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC20_CPPM_CIIR                                     , RULL(0x340F01AD), SH_UNT_PERV_52  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC21_CPPM_CIIR                                     , RULL(0x350F01AD), SH_UNT_PERV_53  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC22_CPPM_CIIR                                     , RULL(0x360F01AD), SH_UNT_PERV_54  , SH_ACS_SCOM_4P   );
+REG64( PERV_EC23_CPPM_CIIR                                     , RULL(0x370F01AD), SH_UNT_PERV_55  , SH_ACS_SCOM_4P   );
+
+REG64( PERV_EC00_CPPM_CISR                                     , RULL(0x200F01AE), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_CPPM_CISR                                     , RULL(0x210F01AE), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_CPPM_CISR                                     , RULL(0x220F01AE), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_CPPM_CISR                                     , RULL(0x230F01AE), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_CPPM_CISR                                     , RULL(0x240F01AE), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_CPPM_CISR                                     , RULL(0x250F01AE), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_CPPM_CISR                                     , RULL(0x260F01AE), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_CPPM_CISR                                     , RULL(0x270F01AE), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_CPPM_CISR                                     , RULL(0x280F01AE), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_CPPM_CISR                                     , RULL(0x290F01AE), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_CPPM_CISR                                     , RULL(0x2A0F01AE), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_CPPM_CISR                                     , RULL(0x2B0F01AE), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_CPPM_CISR                                     , RULL(0x2C0F01AE), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_CPPM_CISR                                     , RULL(0x2D0F01AE), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_CPPM_CISR                                     , RULL(0x2E0F01AE), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_CPPM_CISR                                     , RULL(0x2F0F01AE), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_CPPM_CISR                                     , RULL(0x300F01AE), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_CPPM_CISR                                     , RULL(0x310F01AE), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_CPPM_CISR                                     , RULL(0x320F01AE), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_CPPM_CISR                                     , RULL(0x330F01AE), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_CPPM_CISR                                     , RULL(0x340F01AE), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_CPPM_CISR                                     , RULL(0x350F01AE), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_CPPM_CISR                                     , RULL(0x360F01AE), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_CPPM_CISR                                     , RULL(0x370F01AE), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EC00_CPPM_CIVRMLCR                                 , RULL(0x200F01B7), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CIVRMLCR                                 , RULL(0x210F01B7), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CIVRMLCR                                 , RULL(0x220F01B7), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CIVRMLCR                                 , RULL(0x230F01B7), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CIVRMLCR                                 , RULL(0x240F01B7), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CIVRMLCR                                 , RULL(0x250F01B7), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CIVRMLCR                                 , RULL(0x260F01B7), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CIVRMLCR                                 , RULL(0x270F01B7), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CIVRMLCR                                 , RULL(0x280F01B7), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CIVRMLCR                                 , RULL(0x290F01B7), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CIVRMLCR                                 , RULL(0x2A0F01B7), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CIVRMLCR                                 , RULL(0x2B0F01B7), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CIVRMLCR                                 , RULL(0x2C0F01B7), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CIVRMLCR                                 , RULL(0x2D0F01B7), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CIVRMLCR                                 , RULL(0x2E0F01B7), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CIVRMLCR                                 , RULL(0x2F0F01B7), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CIVRMLCR                                 , RULL(0x300F01B7), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CIVRMLCR                                 , RULL(0x310F01B7), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CIVRMLCR                                 , RULL(0x320F01B7), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CIVRMLCR                                 , RULL(0x330F01B7), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CIVRMLCR                                 , RULL(0x340F01B7), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CIVRMLCR                                 , RULL(0x350F01B7), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CIVRMLCR                                 , RULL(0x360F01B7), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CIVRMLCR                                 , RULL(0x370F01B7), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EC00_CPPM_CMEDATA                                  , RULL(0x200F01A8), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CMEDATA_CLEAR                            , RULL(0x200F01A9), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CMEDATA_OR                               , RULL(0x200F01AA), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CMEDATA                                  , RULL(0x210F01A8), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CMEDATA_CLEAR                            , RULL(0x210F01A9), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CMEDATA_OR                               , RULL(0x210F01AA), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CMEDATA                                  , RULL(0x220F01A8), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CMEDATA_CLEAR                            , RULL(0x220F01A9), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CMEDATA_OR                               , RULL(0x220F01AA), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CMEDATA                                  , RULL(0x230F01A8), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CMEDATA_CLEAR                            , RULL(0x230F01A9), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CMEDATA_OR                               , RULL(0x230F01AA), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CMEDATA                                  , RULL(0x240F01A8), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CMEDATA_CLEAR                            , RULL(0x240F01A9), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CMEDATA_OR                               , RULL(0x240F01AA), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CMEDATA                                  , RULL(0x250F01A8), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CMEDATA_CLEAR                            , RULL(0x250F01A9), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CMEDATA_OR                               , RULL(0x250F01AA), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CMEDATA                                  , RULL(0x260F01A8), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CMEDATA_CLEAR                            , RULL(0x260F01A9), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CMEDATA_OR                               , RULL(0x260F01AA), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CMEDATA                                  , RULL(0x270F01A8), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CMEDATA_CLEAR                            , RULL(0x270F01A9), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CMEDATA_OR                               , RULL(0x270F01AA), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CMEDATA                                  , RULL(0x280F01A8), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CMEDATA_CLEAR                            , RULL(0x280F01A9), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CMEDATA_OR                               , RULL(0x280F01AA), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CMEDATA                                  , RULL(0x290F01A8), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CMEDATA_CLEAR                            , RULL(0x290F01A9), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CMEDATA_OR                               , RULL(0x290F01AA), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CMEDATA                                  , RULL(0x2A0F01A8), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CMEDATA_CLEAR                            , RULL(0x2A0F01A9), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CMEDATA_OR                               , RULL(0x2A0F01AA), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CMEDATA                                  , RULL(0x2B0F01A8), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CMEDATA_CLEAR                            , RULL(0x2B0F01A9), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CMEDATA_OR                               , RULL(0x2B0F01AA), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CMEDATA                                  , RULL(0x2C0F01A8), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CMEDATA_CLEAR                            , RULL(0x2C0F01A9), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CMEDATA_OR                               , RULL(0x2C0F01AA), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CMEDATA                                  , RULL(0x2D0F01A8), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CMEDATA_CLEAR                            , RULL(0x2D0F01A9), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CMEDATA_OR                               , RULL(0x2D0F01AA), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CMEDATA                                  , RULL(0x2E0F01A8), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CMEDATA_CLEAR                            , RULL(0x2E0F01A9), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CMEDATA_OR                               , RULL(0x2E0F01AA), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CMEDATA                                  , RULL(0x2F0F01A8), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CMEDATA_CLEAR                            , RULL(0x2F0F01A9), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CMEDATA_OR                               , RULL(0x2F0F01AA), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CMEDATA                                  , RULL(0x300F01A8), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CMEDATA_CLEAR                            , RULL(0x300F01A9), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CMEDATA_OR                               , RULL(0x300F01AA), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CMEDATA                                  , RULL(0x310F01A8), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CMEDATA_CLEAR                            , RULL(0x310F01A9), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CMEDATA_OR                               , RULL(0x310F01AA), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CMEDATA                                  , RULL(0x320F01A8), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CMEDATA_CLEAR                            , RULL(0x320F01A9), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CMEDATA_OR                               , RULL(0x320F01AA), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CMEDATA                                  , RULL(0x330F01A8), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CMEDATA_CLEAR                            , RULL(0x330F01A9), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CMEDATA_OR                               , RULL(0x330F01AA), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CMEDATA                                  , RULL(0x340F01A8), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CMEDATA_CLEAR                            , RULL(0x340F01A9), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CMEDATA_OR                               , RULL(0x340F01AA), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CMEDATA                                  , RULL(0x350F01A8), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CMEDATA_CLEAR                            , RULL(0x350F01A9), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CMEDATA_OR                               , RULL(0x350F01AA), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CMEDATA                                  , RULL(0x360F01A8), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CMEDATA_CLEAR                            , RULL(0x360F01A9), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CMEDATA_OR                               , RULL(0x360F01AA), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CMEDATA                                  , RULL(0x370F01A8), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CMEDATA_CLEAR                            , RULL(0x370F01A9), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CMEDATA_OR                               , RULL(0x370F01AA), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_CMEDB0                                   , RULL(0x200F0190), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CMEDB0_CLEAR                             , RULL(0x200F0191), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CMEDB0_OR                                , RULL(0x200F0192), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CMEDB0                                   , RULL(0x210F0190), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CMEDB0_CLEAR                             , RULL(0x210F0191), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CMEDB0_OR                                , RULL(0x210F0192), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CMEDB0                                   , RULL(0x220F0190), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CMEDB0_CLEAR                             , RULL(0x220F0191), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CMEDB0_OR                                , RULL(0x220F0192), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CMEDB0                                   , RULL(0x230F0190), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CMEDB0_CLEAR                             , RULL(0x230F0191), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CMEDB0_OR                                , RULL(0x230F0192), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CMEDB0                                   , RULL(0x240F0190), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CMEDB0_CLEAR                             , RULL(0x240F0191), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CMEDB0_OR                                , RULL(0x240F0192), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CMEDB0                                   , RULL(0x250F0190), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CMEDB0_CLEAR                             , RULL(0x250F0191), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CMEDB0_OR                                , RULL(0x250F0192), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CMEDB0                                   , RULL(0x260F0190), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CMEDB0_CLEAR                             , RULL(0x260F0191), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CMEDB0_OR                                , RULL(0x260F0192), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CMEDB0                                   , RULL(0x270F0190), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CMEDB0_CLEAR                             , RULL(0x270F0191), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CMEDB0_OR                                , RULL(0x270F0192), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CMEDB0                                   , RULL(0x280F0190), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CMEDB0_CLEAR                             , RULL(0x280F0191), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CMEDB0_OR                                , RULL(0x280F0192), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CMEDB0                                   , RULL(0x290F0190), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CMEDB0_CLEAR                             , RULL(0x290F0191), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CMEDB0_OR                                , RULL(0x290F0192), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CMEDB0                                   , RULL(0x2A0F0190), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CMEDB0_CLEAR                             , RULL(0x2A0F0191), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CMEDB0_OR                                , RULL(0x2A0F0192), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CMEDB0                                   , RULL(0x2B0F0190), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CMEDB0_CLEAR                             , RULL(0x2B0F0191), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CMEDB0_OR                                , RULL(0x2B0F0192), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CMEDB0                                   , RULL(0x2C0F0190), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CMEDB0_CLEAR                             , RULL(0x2C0F0191), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CMEDB0_OR                                , RULL(0x2C0F0192), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CMEDB0                                   , RULL(0x2D0F0190), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CMEDB0_CLEAR                             , RULL(0x2D0F0191), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CMEDB0_OR                                , RULL(0x2D0F0192), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CMEDB0                                   , RULL(0x2E0F0190), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CMEDB0_CLEAR                             , RULL(0x2E0F0191), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CMEDB0_OR                                , RULL(0x2E0F0192), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CMEDB0                                   , RULL(0x2F0F0190), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CMEDB0_CLEAR                             , RULL(0x2F0F0191), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CMEDB0_OR                                , RULL(0x2F0F0192), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CMEDB0                                   , RULL(0x300F0190), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CMEDB0_CLEAR                             , RULL(0x300F0191), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CMEDB0_OR                                , RULL(0x300F0192), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CMEDB0                                   , RULL(0x310F0190), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CMEDB0_CLEAR                             , RULL(0x310F0191), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CMEDB0_OR                                , RULL(0x310F0192), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CMEDB0                                   , RULL(0x320F0190), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CMEDB0_CLEAR                             , RULL(0x320F0191), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CMEDB0_OR                                , RULL(0x320F0192), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CMEDB0                                   , RULL(0x330F0190), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CMEDB0_CLEAR                             , RULL(0x330F0191), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CMEDB0_OR                                , RULL(0x330F0192), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CMEDB0                                   , RULL(0x340F0190), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CMEDB0_CLEAR                             , RULL(0x340F0191), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CMEDB0_OR                                , RULL(0x340F0192), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CMEDB0                                   , RULL(0x350F0190), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CMEDB0_CLEAR                             , RULL(0x350F0191), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CMEDB0_OR                                , RULL(0x350F0192), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CMEDB0                                   , RULL(0x360F0190), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CMEDB0_CLEAR                             , RULL(0x360F0191), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CMEDB0_OR                                , RULL(0x360F0192), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CMEDB0                                   , RULL(0x370F0190), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CMEDB0_CLEAR                             , RULL(0x370F0191), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CMEDB0_OR                                , RULL(0x370F0192), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_CMEDB1                                   , RULL(0x200F0194), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CMEDB1_CLEAR                             , RULL(0x200F0195), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CMEDB1_OR                                , RULL(0x200F0196), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CMEDB1                                   , RULL(0x210F0194), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CMEDB1_CLEAR                             , RULL(0x210F0195), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CMEDB1_OR                                , RULL(0x210F0196), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CMEDB1                                   , RULL(0x220F0194), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CMEDB1_CLEAR                             , RULL(0x220F0195), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CMEDB1_OR                                , RULL(0x220F0196), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CMEDB1                                   , RULL(0x230F0194), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CMEDB1_CLEAR                             , RULL(0x230F0195), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CMEDB1_OR                                , RULL(0x230F0196), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CMEDB1                                   , RULL(0x240F0194), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CMEDB1_CLEAR                             , RULL(0x240F0195), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CMEDB1_OR                                , RULL(0x240F0196), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CMEDB1                                   , RULL(0x250F0194), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CMEDB1_CLEAR                             , RULL(0x250F0195), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CMEDB1_OR                                , RULL(0x250F0196), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CMEDB1                                   , RULL(0x260F0194), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CMEDB1_CLEAR                             , RULL(0x260F0195), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CMEDB1_OR                                , RULL(0x260F0196), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CMEDB1                                   , RULL(0x270F0194), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CMEDB1_CLEAR                             , RULL(0x270F0195), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CMEDB1_OR                                , RULL(0x270F0196), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CMEDB1                                   , RULL(0x280F0194), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CMEDB1_CLEAR                             , RULL(0x280F0195), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CMEDB1_OR                                , RULL(0x280F0196), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CMEDB1                                   , RULL(0x290F0194), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CMEDB1_CLEAR                             , RULL(0x290F0195), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CMEDB1_OR                                , RULL(0x290F0196), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CMEDB1                                   , RULL(0x2A0F0194), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CMEDB1_CLEAR                             , RULL(0x2A0F0195), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CMEDB1_OR                                , RULL(0x2A0F0196), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CMEDB1                                   , RULL(0x2B0F0194), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CMEDB1_CLEAR                             , RULL(0x2B0F0195), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CMEDB1_OR                                , RULL(0x2B0F0196), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CMEDB1                                   , RULL(0x2C0F0194), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CMEDB1_CLEAR                             , RULL(0x2C0F0195), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CMEDB1_OR                                , RULL(0x2C0F0196), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CMEDB1                                   , RULL(0x2D0F0194), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CMEDB1_CLEAR                             , RULL(0x2D0F0195), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CMEDB1_OR                                , RULL(0x2D0F0196), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CMEDB1                                   , RULL(0x2E0F0194), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CMEDB1_CLEAR                             , RULL(0x2E0F0195), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CMEDB1_OR                                , RULL(0x2E0F0196), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CMEDB1                                   , RULL(0x2F0F0194), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CMEDB1_CLEAR                             , RULL(0x2F0F0195), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CMEDB1_OR                                , RULL(0x2F0F0196), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CMEDB1                                   , RULL(0x300F0194), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CMEDB1_CLEAR                             , RULL(0x300F0195), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CMEDB1_OR                                , RULL(0x300F0196), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CMEDB1                                   , RULL(0x310F0194), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CMEDB1_CLEAR                             , RULL(0x310F0195), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CMEDB1_OR                                , RULL(0x310F0196), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CMEDB1                                   , RULL(0x320F0194), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CMEDB1_CLEAR                             , RULL(0x320F0195), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CMEDB1_OR                                , RULL(0x320F0196), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CMEDB1                                   , RULL(0x330F0194), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CMEDB1_CLEAR                             , RULL(0x330F0195), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CMEDB1_OR                                , RULL(0x330F0196), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CMEDB1                                   , RULL(0x340F0194), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CMEDB1_CLEAR                             , RULL(0x340F0195), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CMEDB1_OR                                , RULL(0x340F0196), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CMEDB1                                   , RULL(0x350F0194), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CMEDB1_CLEAR                             , RULL(0x350F0195), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CMEDB1_OR                                , RULL(0x350F0196), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CMEDB1                                   , RULL(0x360F0194), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CMEDB1_CLEAR                             , RULL(0x360F0195), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CMEDB1_OR                                , RULL(0x360F0196), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CMEDB1                                   , RULL(0x370F0194), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CMEDB1_CLEAR                             , RULL(0x370F0195), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CMEDB1_OR                                , RULL(0x370F0196), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_CMEDB2                                   , RULL(0x200F0198), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CMEDB2_CLEAR                             , RULL(0x200F0199), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CMEDB2_OR                                , RULL(0x200F019A), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CMEDB2                                   , RULL(0x210F0198), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CMEDB2_CLEAR                             , RULL(0x210F0199), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CMEDB2_OR                                , RULL(0x210F019A), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CMEDB2                                   , RULL(0x220F0198), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CMEDB2_CLEAR                             , RULL(0x220F0199), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CMEDB2_OR                                , RULL(0x220F019A), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CMEDB2                                   , RULL(0x230F0198), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CMEDB2_CLEAR                             , RULL(0x230F0199), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CMEDB2_OR                                , RULL(0x230F019A), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CMEDB2                                   , RULL(0x240F0198), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CMEDB2_CLEAR                             , RULL(0x240F0199), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CMEDB2_OR                                , RULL(0x240F019A), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CMEDB2                                   , RULL(0x250F0198), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CMEDB2_CLEAR                             , RULL(0x250F0199), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CMEDB2_OR                                , RULL(0x250F019A), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CMEDB2                                   , RULL(0x260F0198), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CMEDB2_CLEAR                             , RULL(0x260F0199), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CMEDB2_OR                                , RULL(0x260F019A), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CMEDB2                                   , RULL(0x270F0198), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CMEDB2_CLEAR                             , RULL(0x270F0199), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CMEDB2_OR                                , RULL(0x270F019A), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CMEDB2                                   , RULL(0x280F0198), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CMEDB2_CLEAR                             , RULL(0x280F0199), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CMEDB2_OR                                , RULL(0x280F019A), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CMEDB2                                   , RULL(0x290F0198), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CMEDB2_CLEAR                             , RULL(0x290F0199), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CMEDB2_OR                                , RULL(0x290F019A), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CMEDB2                                   , RULL(0x2A0F0198), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CMEDB2_CLEAR                             , RULL(0x2A0F0199), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CMEDB2_OR                                , RULL(0x2A0F019A), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CMEDB2                                   , RULL(0x2B0F0198), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CMEDB2_CLEAR                             , RULL(0x2B0F0199), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CMEDB2_OR                                , RULL(0x2B0F019A), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CMEDB2                                   , RULL(0x2C0F0198), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CMEDB2_CLEAR                             , RULL(0x2C0F0199), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CMEDB2_OR                                , RULL(0x2C0F019A), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CMEDB2                                   , RULL(0x2D0F0198), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CMEDB2_CLEAR                             , RULL(0x2D0F0199), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CMEDB2_OR                                , RULL(0x2D0F019A), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CMEDB2                                   , RULL(0x2E0F0198), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CMEDB2_CLEAR                             , RULL(0x2E0F0199), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CMEDB2_OR                                , RULL(0x2E0F019A), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CMEDB2                                   , RULL(0x2F0F0198), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CMEDB2_CLEAR                             , RULL(0x2F0F0199), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CMEDB2_OR                                , RULL(0x2F0F019A), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CMEDB2                                   , RULL(0x300F0198), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CMEDB2_CLEAR                             , RULL(0x300F0199), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CMEDB2_OR                                , RULL(0x300F019A), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CMEDB2                                   , RULL(0x310F0198), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CMEDB2_CLEAR                             , RULL(0x310F0199), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CMEDB2_OR                                , RULL(0x310F019A), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CMEDB2                                   , RULL(0x320F0198), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CMEDB2_CLEAR                             , RULL(0x320F0199), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CMEDB2_OR                                , RULL(0x320F019A), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CMEDB2                                   , RULL(0x330F0198), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CMEDB2_CLEAR                             , RULL(0x330F0199), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CMEDB2_OR                                , RULL(0x330F019A), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CMEDB2                                   , RULL(0x340F0198), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CMEDB2_CLEAR                             , RULL(0x340F0199), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CMEDB2_OR                                , RULL(0x340F019A), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CMEDB2                                   , RULL(0x350F0198), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CMEDB2_CLEAR                             , RULL(0x350F0199), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CMEDB2_OR                                , RULL(0x350F019A), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CMEDB2                                   , RULL(0x360F0198), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CMEDB2_CLEAR                             , RULL(0x360F0199), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CMEDB2_OR                                , RULL(0x360F019A), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CMEDB2                                   , RULL(0x370F0198), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CMEDB2_CLEAR                             , RULL(0x370F0199), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CMEDB2_OR                                , RULL(0x370F019A), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_CMEDB3                                   , RULL(0x200F019C), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CMEDB3_CLEAR                             , RULL(0x200F019D), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CMEDB3_OR                                , RULL(0x200F019E), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CMEDB3                                   , RULL(0x210F019C), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CMEDB3_CLEAR                             , RULL(0x210F019D), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CMEDB3_OR                                , RULL(0x210F019E), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CMEDB3                                   , RULL(0x220F019C), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CMEDB3_CLEAR                             , RULL(0x220F019D), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CMEDB3_OR                                , RULL(0x220F019E), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CMEDB3                                   , RULL(0x230F019C), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CMEDB3_CLEAR                             , RULL(0x230F019D), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CMEDB3_OR                                , RULL(0x230F019E), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CMEDB3                                   , RULL(0x240F019C), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CMEDB3_CLEAR                             , RULL(0x240F019D), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CMEDB3_OR                                , RULL(0x240F019E), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CMEDB3                                   , RULL(0x250F019C), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CMEDB3_CLEAR                             , RULL(0x250F019D), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CMEDB3_OR                                , RULL(0x250F019E), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CMEDB3                                   , RULL(0x260F019C), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CMEDB3_CLEAR                             , RULL(0x260F019D), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CMEDB3_OR                                , RULL(0x260F019E), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CMEDB3                                   , RULL(0x270F019C), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CMEDB3_CLEAR                             , RULL(0x270F019D), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CMEDB3_OR                                , RULL(0x270F019E), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CMEDB3                                   , RULL(0x280F019C), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CMEDB3_CLEAR                             , RULL(0x280F019D), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CMEDB3_OR                                , RULL(0x280F019E), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CMEDB3                                   , RULL(0x290F019C), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CMEDB3_CLEAR                             , RULL(0x290F019D), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CMEDB3_OR                                , RULL(0x290F019E), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CMEDB3                                   , RULL(0x2A0F019C), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CMEDB3_CLEAR                             , RULL(0x2A0F019D), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CMEDB3_OR                                , RULL(0x2A0F019E), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CMEDB3                                   , RULL(0x2B0F019C), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CMEDB3_CLEAR                             , RULL(0x2B0F019D), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CMEDB3_OR                                , RULL(0x2B0F019E), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CMEDB3                                   , RULL(0x2C0F019C), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CMEDB3_CLEAR                             , RULL(0x2C0F019D), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CMEDB3_OR                                , RULL(0x2C0F019E), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CMEDB3                                   , RULL(0x2D0F019C), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CMEDB3_CLEAR                             , RULL(0x2D0F019D), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CMEDB3_OR                                , RULL(0x2D0F019E), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CMEDB3                                   , RULL(0x2E0F019C), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CMEDB3_CLEAR                             , RULL(0x2E0F019D), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CMEDB3_OR                                , RULL(0x2E0F019E), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CMEDB3                                   , RULL(0x2F0F019C), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CMEDB3_CLEAR                             , RULL(0x2F0F019D), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CMEDB3_OR                                , RULL(0x2F0F019E), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CMEDB3                                   , RULL(0x300F019C), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CMEDB3_CLEAR                             , RULL(0x300F019D), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CMEDB3_OR                                , RULL(0x300F019E), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CMEDB3                                   , RULL(0x310F019C), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CMEDB3_CLEAR                             , RULL(0x310F019D), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CMEDB3_OR                                , RULL(0x310F019E), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CMEDB3                                   , RULL(0x320F019C), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CMEDB3_CLEAR                             , RULL(0x320F019D), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CMEDB3_OR                                , RULL(0x320F019E), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CMEDB3                                   , RULL(0x330F019C), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CMEDB3_CLEAR                             , RULL(0x330F019D), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CMEDB3_OR                                , RULL(0x330F019E), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CMEDB3                                   , RULL(0x340F019C), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CMEDB3_CLEAR                             , RULL(0x340F019D), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CMEDB3_OR                                , RULL(0x340F019E), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CMEDB3                                   , RULL(0x350F019C), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CMEDB3_CLEAR                             , RULL(0x350F019D), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CMEDB3_OR                                , RULL(0x350F019E), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CMEDB3                                   , RULL(0x360F019C), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CMEDB3_CLEAR                             , RULL(0x360F019D), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CMEDB3_OR                                , RULL(0x360F019E), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CMEDB3                                   , RULL(0x370F019C), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CMEDB3_CLEAR                             , RULL(0x370F019D), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CMEDB3_OR                                , RULL(0x370F019E), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_CMEMSG                                   , RULL(0x200F01AB), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CMEMSG                                   , RULL(0x210F01AB), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CMEMSG                                   , RULL(0x220F01AB), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CMEMSG                                   , RULL(0x230F01AB), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CMEMSG                                   , RULL(0x240F01AB), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CMEMSG                                   , RULL(0x250F01AB), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CMEMSG                                   , RULL(0x260F01AB), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CMEMSG                                   , RULL(0x270F01AB), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CMEMSG                                   , RULL(0x280F01AB), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CMEMSG                                   , RULL(0x290F01AB), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CMEMSG                                   , RULL(0x2A0F01AB), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CMEMSG                                   , RULL(0x2B0F01AB), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CMEMSG                                   , RULL(0x2C0F01AB), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CMEMSG                                   , RULL(0x2D0F01AB), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CMEMSG                                   , RULL(0x2E0F01AB), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CMEMSG                                   , RULL(0x2F0F01AB), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CMEMSG                                   , RULL(0x300F01AB), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CMEMSG                                   , RULL(0x310F01AB), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CMEMSG                                   , RULL(0x320F01AB), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CMEMSG                                   , RULL(0x330F01AB), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CMEMSG                                   , RULL(0x340F01AB), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CMEMSG                                   , RULL(0x350F01AB), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CMEMSG                                   , RULL(0x360F01AB), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CMEMSG                                   , RULL(0x370F01AB), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EC00_CPPM_CPMMR                                    , RULL(0x200F0106), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CPMMR_CLEAR                              , RULL(0x200F0107), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CPMMR_OR                                 , RULL(0x200F0108), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CPMMR                                    , RULL(0x210F0106), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CPMMR_CLEAR                              , RULL(0x210F0107), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CPMMR_OR                                 , RULL(0x210F0108), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CPMMR                                    , RULL(0x220F0106), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CPMMR_CLEAR                              , RULL(0x220F0107), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CPMMR_OR                                 , RULL(0x220F0108), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CPMMR                                    , RULL(0x230F0106), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CPMMR_CLEAR                              , RULL(0x230F0107), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CPMMR_OR                                 , RULL(0x230F0108), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CPMMR                                    , RULL(0x240F0106), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CPMMR_CLEAR                              , RULL(0x240F0107), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CPMMR_OR                                 , RULL(0x240F0108), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CPMMR                                    , RULL(0x250F0106), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CPMMR_CLEAR                              , RULL(0x250F0107), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CPMMR_OR                                 , RULL(0x250F0108), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CPMMR                                    , RULL(0x260F0106), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CPMMR_CLEAR                              , RULL(0x260F0107), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CPMMR_OR                                 , RULL(0x260F0108), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CPMMR                                    , RULL(0x270F0106), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CPMMR_CLEAR                              , RULL(0x270F0107), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CPMMR_OR                                 , RULL(0x270F0108), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CPMMR                                    , RULL(0x280F0106), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CPMMR_CLEAR                              , RULL(0x280F0107), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CPMMR_OR                                 , RULL(0x280F0108), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CPMMR                                    , RULL(0x290F0106), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CPMMR_CLEAR                              , RULL(0x290F0107), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CPMMR_OR                                 , RULL(0x290F0108), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CPMMR                                    , RULL(0x2A0F0106), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CPMMR_CLEAR                              , RULL(0x2A0F0107), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CPMMR_OR                                 , RULL(0x2A0F0108), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CPMMR                                    , RULL(0x2B0F0106), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CPMMR_CLEAR                              , RULL(0x2B0F0107), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CPMMR_OR                                 , RULL(0x2B0F0108), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CPMMR                                    , RULL(0x2C0F0106), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CPMMR_CLEAR                              , RULL(0x2C0F0107), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CPMMR_OR                                 , RULL(0x2C0F0108), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CPMMR                                    , RULL(0x2D0F0106), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CPMMR_CLEAR                              , RULL(0x2D0F0107), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CPMMR_OR                                 , RULL(0x2D0F0108), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CPMMR                                    , RULL(0x2E0F0106), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CPMMR_CLEAR                              , RULL(0x2E0F0107), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CPMMR_OR                                 , RULL(0x2E0F0108), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CPMMR                                    , RULL(0x2F0F0106), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CPMMR_CLEAR                              , RULL(0x2F0F0107), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CPMMR_OR                                 , RULL(0x2F0F0108), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CPMMR                                    , RULL(0x300F0106), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CPMMR_CLEAR                              , RULL(0x300F0107), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CPMMR_OR                                 , RULL(0x300F0108), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CPMMR                                    , RULL(0x310F0106), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CPMMR_CLEAR                              , RULL(0x310F0107), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CPMMR_OR                                 , RULL(0x310F0108), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CPMMR                                    , RULL(0x320F0106), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CPMMR_CLEAR                              , RULL(0x320F0107), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CPMMR_OR                                 , RULL(0x320F0108), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CPMMR                                    , RULL(0x330F0106), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CPMMR_CLEAR                              , RULL(0x330F0107), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CPMMR_OR                                 , RULL(0x330F0108), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CPMMR                                    , RULL(0x340F0106), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CPMMR_CLEAR                              , RULL(0x340F0107), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CPMMR_OR                                 , RULL(0x340F0108), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CPMMR                                    , RULL(0x350F0106), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CPMMR_CLEAR                              , RULL(0x350F0107), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CPMMR_OR                                 , RULL(0x350F0108), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CPMMR                                    , RULL(0x360F0106), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CPMMR_CLEAR                              , RULL(0x360F0107), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CPMMR_OR                                 , RULL(0x360F0108), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CPMMR                                    , RULL(0x370F0106), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CPMMR_CLEAR                              , RULL(0x370F0107), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CPMMR_OR                                 , RULL(0x370F0108), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_CSAR                                     , RULL(0x200F0138), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_CPPM_CSAR_CLEAR                               , RULL(0x200F0139), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_CPPM_CSAR_OR                                  , RULL(0x200F013A), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_CPPM_CSAR                                     , RULL(0x210F0138), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_CSAR_CLEAR                               , RULL(0x210F0139), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_CPPM_CSAR_OR                                  , RULL(0x210F013A), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_CPPM_CSAR                                     , RULL(0x220F0138), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_CSAR_CLEAR                               , RULL(0x220F0139), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_CPPM_CSAR_OR                                  , RULL(0x220F013A), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_CPPM_CSAR                                     , RULL(0x230F0138), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_CSAR_CLEAR                               , RULL(0x230F0139), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_CPPM_CSAR_OR                                  , RULL(0x230F013A), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_CPPM_CSAR                                     , RULL(0x240F0138), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_CSAR_CLEAR                               , RULL(0x240F0139), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_CPPM_CSAR_OR                                  , RULL(0x240F013A), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_CPPM_CSAR                                     , RULL(0x250F0138), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_CSAR_CLEAR                               , RULL(0x250F0139), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_CPPM_CSAR_OR                                  , RULL(0x250F013A), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_CPPM_CSAR                                     , RULL(0x260F0138), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_CSAR_CLEAR                               , RULL(0x260F0139), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_CPPM_CSAR_OR                                  , RULL(0x260F013A), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_CPPM_CSAR                                     , RULL(0x270F0138), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_CSAR_CLEAR                               , RULL(0x270F0139), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_CPPM_CSAR_OR                                  , RULL(0x270F013A), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_CPPM_CSAR                                     , RULL(0x280F0138), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_CSAR_CLEAR                               , RULL(0x280F0139), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_CPPM_CSAR_OR                                  , RULL(0x280F013A), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_CPPM_CSAR                                     , RULL(0x290F0138), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_CSAR_CLEAR                               , RULL(0x290F0139), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_CPPM_CSAR_OR                                  , RULL(0x290F013A), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_CPPM_CSAR                                     , RULL(0x2A0F0138), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_CSAR_CLEAR                               , RULL(0x2A0F0139), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_CPPM_CSAR_OR                                  , RULL(0x2A0F013A), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_CPPM_CSAR                                     , RULL(0x2B0F0138), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_CSAR_CLEAR                               , RULL(0x2B0F0139), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_CPPM_CSAR_OR                                  , RULL(0x2B0F013A), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_CPPM_CSAR                                     , RULL(0x2C0F0138), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_CSAR_CLEAR                               , RULL(0x2C0F0139), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_CPPM_CSAR_OR                                  , RULL(0x2C0F013A), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_CPPM_CSAR                                     , RULL(0x2D0F0138), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_CSAR_CLEAR                               , RULL(0x2D0F0139), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_CPPM_CSAR_OR                                  , RULL(0x2D0F013A), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_CPPM_CSAR                                     , RULL(0x2E0F0138), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_CSAR_CLEAR                               , RULL(0x2E0F0139), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_CPPM_CSAR_OR                                  , RULL(0x2E0F013A), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_CPPM_CSAR                                     , RULL(0x2F0F0138), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_CSAR_CLEAR                               , RULL(0x2F0F0139), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_CPPM_CSAR_OR                                  , RULL(0x2F0F013A), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_CPPM_CSAR                                     , RULL(0x300F0138), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_CSAR_CLEAR                               , RULL(0x300F0139), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_CPPM_CSAR_OR                                  , RULL(0x300F013A), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_CPPM_CSAR                                     , RULL(0x310F0138), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_CSAR_CLEAR                               , RULL(0x310F0139), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_CPPM_CSAR_OR                                  , RULL(0x310F013A), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_CPPM_CSAR                                     , RULL(0x320F0138), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_CSAR_CLEAR                               , RULL(0x320F0139), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_CPPM_CSAR_OR                                  , RULL(0x320F013A), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_CPPM_CSAR                                     , RULL(0x330F0138), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_CSAR_CLEAR                               , RULL(0x330F0139), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_CPPM_CSAR_OR                                  , RULL(0x330F013A), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_CPPM_CSAR                                     , RULL(0x340F0138), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_CSAR_CLEAR                               , RULL(0x340F0139), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_CPPM_CSAR_OR                                  , RULL(0x340F013A), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_CPPM_CSAR                                     , RULL(0x350F0138), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_CSAR_CLEAR                               , RULL(0x350F0139), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_CPPM_CSAR_OR                                  , RULL(0x350F013A), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_CPPM_CSAR                                     , RULL(0x360F0138), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_CSAR_CLEAR                               , RULL(0x360F0139), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_CPPM_CSAR_OR                                  , RULL(0x360F013A), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_CPPM_CSAR                                     , RULL(0x370F0138), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_CSAR_CLEAR                               , RULL(0x370F0139), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_CPPM_CSAR_OR                                  , RULL(0x370F013A), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EC00_CPPM_ERR                                      , RULL(0x200F0121), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CPPM_ERR                                      , RULL(0x210F0121), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CPPM_ERR                                      , RULL(0x220F0121), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CPPM_ERR                                      , RULL(0x230F0121), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CPPM_ERR                                      , RULL(0x240F0121), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CPPM_ERR                                      , RULL(0x250F0121), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CPPM_ERR                                      , RULL(0x260F0121), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CPPM_ERR                                      , RULL(0x270F0121), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CPPM_ERR                                      , RULL(0x280F0121), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CPPM_ERR                                      , RULL(0x290F0121), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CPPM_ERR                                      , RULL(0x2A0F0121), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CPPM_ERR                                      , RULL(0x2B0F0121), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CPPM_ERR                                      , RULL(0x2C0F0121), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CPPM_ERR                                      , RULL(0x2D0F0121), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CPPM_ERR                                      , RULL(0x2E0F0121), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CPPM_ERR                                      , RULL(0x2F0F0121), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CPPM_ERR                                      , RULL(0x300F0121), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CPPM_ERR                                      , RULL(0x310F0121), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CPPM_ERR                                      , RULL(0x320F0121), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CPPM_ERR                                      , RULL(0x330F0121), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CPPM_ERR                                      , RULL(0x340F0121), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CPPM_ERR                                      , RULL(0x350F0121), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CPPM_ERR                                      , RULL(0x360F0121), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CPPM_ERR                                      , RULL(0x370F0121), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EC00_CPPM_ERRMSK                                   , RULL(0x200F0122), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_ERRMSK                                   , RULL(0x210F0122), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_ERRMSK                                   , RULL(0x220F0122), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_ERRMSK                                   , RULL(0x230F0122), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_ERRMSK                                   , RULL(0x240F0122), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_ERRMSK                                   , RULL(0x250F0122), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_ERRMSK                                   , RULL(0x260F0122), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_ERRMSK                                   , RULL(0x270F0122), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_ERRMSK                                   , RULL(0x280F0122), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_ERRMSK                                   , RULL(0x290F0122), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_ERRMSK                                   , RULL(0x2A0F0122), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_ERRMSK                                   , RULL(0x2B0F0122), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_ERRMSK                                   , RULL(0x2C0F0122), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_ERRMSK                                   , RULL(0x2D0F0122), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_ERRMSK                                   , RULL(0x2E0F0122), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_ERRMSK                                   , RULL(0x2F0F0122), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_ERRMSK                                   , RULL(0x300F0122), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_ERRMSK                                   , RULL(0x310F0122), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_ERRMSK                                   , RULL(0x320F0122), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_ERRMSK                                   , RULL(0x330F0122), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_ERRMSK                                   , RULL(0x340F0122), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_ERRMSK                                   , RULL(0x350F0122), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_ERRMSK                                   , RULL(0x360F0122), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_ERRMSK                                   , RULL(0x370F0122), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EC00_CPPM_IPPMCMD                                  , RULL(0x200F01C0), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_IPPMCMD                                  , RULL(0x210F01C0), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_IPPMCMD                                  , RULL(0x220F01C0), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_IPPMCMD                                  , RULL(0x230F01C0), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_IPPMCMD                                  , RULL(0x240F01C0), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_IPPMCMD                                  , RULL(0x250F01C0), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_IPPMCMD                                  , RULL(0x260F01C0), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_IPPMCMD                                  , RULL(0x270F01C0), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_IPPMCMD                                  , RULL(0x280F01C0), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_IPPMCMD                                  , RULL(0x290F01C0), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_IPPMCMD                                  , RULL(0x2A0F01C0), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_IPPMCMD                                  , RULL(0x2B0F01C0), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_IPPMCMD                                  , RULL(0x2C0F01C0), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_IPPMCMD                                  , RULL(0x2D0F01C0), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_IPPMCMD                                  , RULL(0x2E0F01C0), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_IPPMCMD                                  , RULL(0x2F0F01C0), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_IPPMCMD                                  , RULL(0x300F01C0), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_IPPMCMD                                  , RULL(0x310F01C0), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_IPPMCMD                                  , RULL(0x320F01C0), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_IPPMCMD                                  , RULL(0x330F01C0), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_IPPMCMD                                  , RULL(0x340F01C0), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_IPPMCMD                                  , RULL(0x350F01C0), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_IPPMCMD                                  , RULL(0x360F01C0), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_IPPMCMD                                  , RULL(0x370F01C0), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EC00_CPPM_IPPMRDATA                                , RULL(0x200F01C3), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_IPPMRDATA                                , RULL(0x210F01C3), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_IPPMRDATA                                , RULL(0x220F01C3), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_IPPMRDATA                                , RULL(0x230F01C3), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_IPPMRDATA                                , RULL(0x240F01C3), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_IPPMRDATA                                , RULL(0x250F01C3), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_IPPMRDATA                                , RULL(0x260F01C3), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_IPPMRDATA                                , RULL(0x270F01C3), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_IPPMRDATA                                , RULL(0x280F01C3), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_IPPMRDATA                                , RULL(0x290F01C3), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_IPPMRDATA                                , RULL(0x2A0F01C3), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_IPPMRDATA                                , RULL(0x2B0F01C3), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_IPPMRDATA                                , RULL(0x2C0F01C3), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_IPPMRDATA                                , RULL(0x2D0F01C3), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_IPPMRDATA                                , RULL(0x2E0F01C3), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_IPPMRDATA                                , RULL(0x2F0F01C3), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_IPPMRDATA                                , RULL(0x300F01C3), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_IPPMRDATA                                , RULL(0x310F01C3), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_IPPMRDATA                                , RULL(0x320F01C3), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_IPPMRDATA                                , RULL(0x330F01C3), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_IPPMRDATA                                , RULL(0x340F01C3), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_IPPMRDATA                                , RULL(0x350F01C3), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_IPPMRDATA                                , RULL(0x360F01C3), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_IPPMRDATA                                , RULL(0x370F01C3), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EC00_CPPM_IPPMSTAT                                 , RULL(0x200F01C1), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_CPPM_IPPMSTAT                                 , RULL(0x210F01C1), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_CPPM_IPPMSTAT                                 , RULL(0x220F01C1), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_CPPM_IPPMSTAT                                 , RULL(0x230F01C1), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_CPPM_IPPMSTAT                                 , RULL(0x240F01C1), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_CPPM_IPPMSTAT                                 , RULL(0x250F01C1), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_CPPM_IPPMSTAT                                 , RULL(0x260F01C1), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_CPPM_IPPMSTAT                                 , RULL(0x270F01C1), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_CPPM_IPPMSTAT                                 , RULL(0x280F01C1), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_CPPM_IPPMSTAT                                 , RULL(0x290F01C1), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_CPPM_IPPMSTAT                                 , RULL(0x2A0F01C1), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_CPPM_IPPMSTAT                                 , RULL(0x2B0F01C1), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_CPPM_IPPMSTAT                                 , RULL(0x2C0F01C1), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_CPPM_IPPMSTAT                                 , RULL(0x2D0F01C1), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_CPPM_IPPMSTAT                                 , RULL(0x2E0F01C1), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_CPPM_IPPMSTAT                                 , RULL(0x2F0F01C1), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_CPPM_IPPMSTAT                                 , RULL(0x300F01C1), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_CPPM_IPPMSTAT                                 , RULL(0x310F01C1), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_CPPM_IPPMSTAT                                 , RULL(0x320F01C1), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_CPPM_IPPMSTAT                                 , RULL(0x330F01C1), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_CPPM_IPPMSTAT                                 , RULL(0x340F01C1), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_CPPM_IPPMSTAT                                 , RULL(0x350F01C1), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_CPPM_IPPMSTAT                                 , RULL(0x360F01C1), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_CPPM_IPPMSTAT                                 , RULL(0x370F01C1), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EC00_CPPM_IPPMWDATA                                , RULL(0x200F01C2), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_IPPMWDATA                                , RULL(0x210F01C2), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_IPPMWDATA                                , RULL(0x220F01C2), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_IPPMWDATA                                , RULL(0x230F01C2), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_IPPMWDATA                                , RULL(0x240F01C2), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_IPPMWDATA                                , RULL(0x250F01C2), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_IPPMWDATA                                , RULL(0x260F01C2), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_IPPMWDATA                                , RULL(0x270F01C2), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_IPPMWDATA                                , RULL(0x280F01C2), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_IPPMWDATA                                , RULL(0x290F01C2), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_IPPMWDATA                                , RULL(0x2A0F01C2), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_IPPMWDATA                                , RULL(0x2B0F01C2), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_IPPMWDATA                                , RULL(0x2C0F01C2), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_IPPMWDATA                                , RULL(0x2D0F01C2), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_IPPMWDATA                                , RULL(0x2E0F01C2), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_IPPMWDATA                                , RULL(0x2F0F01C2), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_IPPMWDATA                                , RULL(0x300F01C2), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_IPPMWDATA                                , RULL(0x310F01C2), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_IPPMWDATA                                , RULL(0x320F01C2), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_IPPMWDATA                                , RULL(0x330F01C2), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_IPPMWDATA                                , RULL(0x340F01C2), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_IPPMWDATA                                , RULL(0x350F01C2), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_IPPMWDATA                                , RULL(0x360F01C2), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_IPPMWDATA                                , RULL(0x370F01C2), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EC00_CPPM_NC0INDIR_SCOM                            , RULL(0x200F0130), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_CPPM_NC0INDIR_SCOM1                           , RULL(0x200F0131), SH_UNT_PERV_32  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC00_CPPM_NC0INDIR_SCOM2                           , RULL(0x200F0132), SH_UNT_PERV_32  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC01_CPPM_NC0INDIR_SCOM                            , RULL(0x210F0130), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_CPPM_NC0INDIR_SCOM1                           , RULL(0x210F0131), SH_UNT_PERV_33  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC01_CPPM_NC0INDIR_SCOM2                           , RULL(0x210F0132), SH_UNT_PERV_33  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC02_CPPM_NC0INDIR_SCOM                            , RULL(0x220F0130), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_CPPM_NC0INDIR_SCOM1                           , RULL(0x220F0131), SH_UNT_PERV_34  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC02_CPPM_NC0INDIR_SCOM2                           , RULL(0x220F0132), SH_UNT_PERV_34  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC03_CPPM_NC0INDIR_SCOM                            , RULL(0x230F0130), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_CPPM_NC0INDIR_SCOM1                           , RULL(0x230F0131), SH_UNT_PERV_35  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC03_CPPM_NC0INDIR_SCOM2                           , RULL(0x230F0132), SH_UNT_PERV_35  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC04_CPPM_NC0INDIR_SCOM                            , RULL(0x240F0130), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_CPPM_NC0INDIR_SCOM1                           , RULL(0x240F0131), SH_UNT_PERV_36  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC04_CPPM_NC0INDIR_SCOM2                           , RULL(0x240F0132), SH_UNT_PERV_36  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC05_CPPM_NC0INDIR_SCOM                            , RULL(0x250F0130), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_CPPM_NC0INDIR_SCOM1                           , RULL(0x250F0131), SH_UNT_PERV_37  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC05_CPPM_NC0INDIR_SCOM2                           , RULL(0x250F0132), SH_UNT_PERV_37  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC06_CPPM_NC0INDIR_SCOM                            , RULL(0x260F0130), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_CPPM_NC0INDIR_SCOM1                           , RULL(0x260F0131), SH_UNT_PERV_38  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC06_CPPM_NC0INDIR_SCOM2                           , RULL(0x260F0132), SH_UNT_PERV_38  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC07_CPPM_NC0INDIR_SCOM                            , RULL(0x270F0130), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_CPPM_NC0INDIR_SCOM1                           , RULL(0x270F0131), SH_UNT_PERV_39  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC07_CPPM_NC0INDIR_SCOM2                           , RULL(0x270F0132), SH_UNT_PERV_39  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC08_CPPM_NC0INDIR_SCOM                            , RULL(0x280F0130), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_CPPM_NC0INDIR_SCOM1                           , RULL(0x280F0131), SH_UNT_PERV_40  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC08_CPPM_NC0INDIR_SCOM2                           , RULL(0x280F0132), SH_UNT_PERV_40  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC09_CPPM_NC0INDIR_SCOM                            , RULL(0x290F0130), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_CPPM_NC0INDIR_SCOM1                           , RULL(0x290F0131), SH_UNT_PERV_41  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC09_CPPM_NC0INDIR_SCOM2                           , RULL(0x290F0132), SH_UNT_PERV_41  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC10_CPPM_NC0INDIR_SCOM                            , RULL(0x2A0F0130), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_CPPM_NC0INDIR_SCOM1                           , RULL(0x2A0F0131), SH_UNT_PERV_42  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC10_CPPM_NC0INDIR_SCOM2                           , RULL(0x2A0F0132), SH_UNT_PERV_42  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC11_CPPM_NC0INDIR_SCOM                            , RULL(0x2B0F0130), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_CPPM_NC0INDIR_SCOM1                           , RULL(0x2B0F0131), SH_UNT_PERV_43  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC11_CPPM_NC0INDIR_SCOM2                           , RULL(0x2B0F0132), SH_UNT_PERV_43  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC12_CPPM_NC0INDIR_SCOM                            , RULL(0x2C0F0130), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_CPPM_NC0INDIR_SCOM1                           , RULL(0x2C0F0131), SH_UNT_PERV_44  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC12_CPPM_NC0INDIR_SCOM2                           , RULL(0x2C0F0132), SH_UNT_PERV_44  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC13_CPPM_NC0INDIR_SCOM                            , RULL(0x2D0F0130), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_CPPM_NC0INDIR_SCOM1                           , RULL(0x2D0F0131), SH_UNT_PERV_45  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC13_CPPM_NC0INDIR_SCOM2                           , RULL(0x2D0F0132), SH_UNT_PERV_45  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC14_CPPM_NC0INDIR_SCOM                            , RULL(0x2E0F0130), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_CPPM_NC0INDIR_SCOM1                           , RULL(0x2E0F0131), SH_UNT_PERV_46  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC14_CPPM_NC0INDIR_SCOM2                           , RULL(0x2E0F0132), SH_UNT_PERV_46  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC15_CPPM_NC0INDIR_SCOM                            , RULL(0x2F0F0130), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_CPPM_NC0INDIR_SCOM1                           , RULL(0x2F0F0131), SH_UNT_PERV_47  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC15_CPPM_NC0INDIR_SCOM2                           , RULL(0x2F0F0132), SH_UNT_PERV_47  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC16_CPPM_NC0INDIR_SCOM                            , RULL(0x300F0130), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_CPPM_NC0INDIR_SCOM1                           , RULL(0x300F0131), SH_UNT_PERV_48  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC16_CPPM_NC0INDIR_SCOM2                           , RULL(0x300F0132), SH_UNT_PERV_48  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC17_CPPM_NC0INDIR_SCOM                            , RULL(0x310F0130), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_CPPM_NC0INDIR_SCOM1                           , RULL(0x310F0131), SH_UNT_PERV_49  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC17_CPPM_NC0INDIR_SCOM2                           , RULL(0x310F0132), SH_UNT_PERV_49  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC18_CPPM_NC0INDIR_SCOM                            , RULL(0x320F0130), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_CPPM_NC0INDIR_SCOM1                           , RULL(0x320F0131), SH_UNT_PERV_50  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC18_CPPM_NC0INDIR_SCOM2                           , RULL(0x320F0132), SH_UNT_PERV_50  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC19_CPPM_NC0INDIR_SCOM                            , RULL(0x330F0130), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_CPPM_NC0INDIR_SCOM1                           , RULL(0x330F0131), SH_UNT_PERV_51  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC19_CPPM_NC0INDIR_SCOM2                           , RULL(0x330F0132), SH_UNT_PERV_51  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC20_CPPM_NC0INDIR_SCOM                            , RULL(0x340F0130), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_CPPM_NC0INDIR_SCOM1                           , RULL(0x340F0131), SH_UNT_PERV_52  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC20_CPPM_NC0INDIR_SCOM2                           , RULL(0x340F0132), SH_UNT_PERV_52  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC21_CPPM_NC0INDIR_SCOM                            , RULL(0x350F0130), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_CPPM_NC0INDIR_SCOM1                           , RULL(0x350F0131), SH_UNT_PERV_53  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC21_CPPM_NC0INDIR_SCOM2                           , RULL(0x350F0132), SH_UNT_PERV_53  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC22_CPPM_NC0INDIR_SCOM                            , RULL(0x360F0130), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_CPPM_NC0INDIR_SCOM1                           , RULL(0x360F0131), SH_UNT_PERV_54  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC22_CPPM_NC0INDIR_SCOM2                           , RULL(0x360F0132), SH_UNT_PERV_54  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC23_CPPM_NC0INDIR_SCOM                            , RULL(0x370F0130), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_CPPM_NC0INDIR_SCOM1                           , RULL(0x370F0131), SH_UNT_PERV_55  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC23_CPPM_NC0INDIR_SCOM2                           , RULL(0x370F0132), SH_UNT_PERV_55  , SH_ACS_SCOM2_NC  );
+
+REG64( PERV_EC00_CPPM_NC1INDIR_SCOM                            , RULL(0x200F0133), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_CPPM_NC1INDIR_SCOM1                           , RULL(0x200F0134), SH_UNT_PERV_32  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC00_CPPM_NC1INDIR_SCOM2                           , RULL(0x200F0135), SH_UNT_PERV_32  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC01_CPPM_NC1INDIR_SCOM                            , RULL(0x210F0133), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_CPPM_NC1INDIR_SCOM1                           , RULL(0x210F0134), SH_UNT_PERV_33  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC01_CPPM_NC1INDIR_SCOM2                           , RULL(0x210F0135), SH_UNT_PERV_33  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC02_CPPM_NC1INDIR_SCOM                            , RULL(0x220F0133), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_CPPM_NC1INDIR_SCOM1                           , RULL(0x220F0134), SH_UNT_PERV_34  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC02_CPPM_NC1INDIR_SCOM2                           , RULL(0x220F0135), SH_UNT_PERV_34  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC03_CPPM_NC1INDIR_SCOM                            , RULL(0x230F0133), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_CPPM_NC1INDIR_SCOM1                           , RULL(0x230F0134), SH_UNT_PERV_35  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC03_CPPM_NC1INDIR_SCOM2                           , RULL(0x230F0135), SH_UNT_PERV_35  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC04_CPPM_NC1INDIR_SCOM                            , RULL(0x240F0133), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_CPPM_NC1INDIR_SCOM1                           , RULL(0x240F0134), SH_UNT_PERV_36  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC04_CPPM_NC1INDIR_SCOM2                           , RULL(0x240F0135), SH_UNT_PERV_36  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC05_CPPM_NC1INDIR_SCOM                            , RULL(0x250F0133), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_CPPM_NC1INDIR_SCOM1                           , RULL(0x250F0134), SH_UNT_PERV_37  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC05_CPPM_NC1INDIR_SCOM2                           , RULL(0x250F0135), SH_UNT_PERV_37  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC06_CPPM_NC1INDIR_SCOM                            , RULL(0x260F0133), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_CPPM_NC1INDIR_SCOM1                           , RULL(0x260F0134), SH_UNT_PERV_38  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC06_CPPM_NC1INDIR_SCOM2                           , RULL(0x260F0135), SH_UNT_PERV_38  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC07_CPPM_NC1INDIR_SCOM                            , RULL(0x270F0133), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_CPPM_NC1INDIR_SCOM1                           , RULL(0x270F0134), SH_UNT_PERV_39  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC07_CPPM_NC1INDIR_SCOM2                           , RULL(0x270F0135), SH_UNT_PERV_39  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC08_CPPM_NC1INDIR_SCOM                            , RULL(0x280F0133), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_CPPM_NC1INDIR_SCOM1                           , RULL(0x280F0134), SH_UNT_PERV_40  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC08_CPPM_NC1INDIR_SCOM2                           , RULL(0x280F0135), SH_UNT_PERV_40  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC09_CPPM_NC1INDIR_SCOM                            , RULL(0x290F0133), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_CPPM_NC1INDIR_SCOM1                           , RULL(0x290F0134), SH_UNT_PERV_41  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC09_CPPM_NC1INDIR_SCOM2                           , RULL(0x290F0135), SH_UNT_PERV_41  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC10_CPPM_NC1INDIR_SCOM                            , RULL(0x2A0F0133), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_CPPM_NC1INDIR_SCOM1                           , RULL(0x2A0F0134), SH_UNT_PERV_42  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC10_CPPM_NC1INDIR_SCOM2                           , RULL(0x2A0F0135), SH_UNT_PERV_42  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC11_CPPM_NC1INDIR_SCOM                            , RULL(0x2B0F0133), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_CPPM_NC1INDIR_SCOM1                           , RULL(0x2B0F0134), SH_UNT_PERV_43  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC11_CPPM_NC1INDIR_SCOM2                           , RULL(0x2B0F0135), SH_UNT_PERV_43  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC12_CPPM_NC1INDIR_SCOM                            , RULL(0x2C0F0133), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_CPPM_NC1INDIR_SCOM1                           , RULL(0x2C0F0134), SH_UNT_PERV_44  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC12_CPPM_NC1INDIR_SCOM2                           , RULL(0x2C0F0135), SH_UNT_PERV_44  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC13_CPPM_NC1INDIR_SCOM                            , RULL(0x2D0F0133), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_CPPM_NC1INDIR_SCOM1                           , RULL(0x2D0F0134), SH_UNT_PERV_45  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC13_CPPM_NC1INDIR_SCOM2                           , RULL(0x2D0F0135), SH_UNT_PERV_45  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC14_CPPM_NC1INDIR_SCOM                            , RULL(0x2E0F0133), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_CPPM_NC1INDIR_SCOM1                           , RULL(0x2E0F0134), SH_UNT_PERV_46  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC14_CPPM_NC1INDIR_SCOM2                           , RULL(0x2E0F0135), SH_UNT_PERV_46  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC15_CPPM_NC1INDIR_SCOM                            , RULL(0x2F0F0133), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_CPPM_NC1INDIR_SCOM1                           , RULL(0x2F0F0134), SH_UNT_PERV_47  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC15_CPPM_NC1INDIR_SCOM2                           , RULL(0x2F0F0135), SH_UNT_PERV_47  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC16_CPPM_NC1INDIR_SCOM                            , RULL(0x300F0133), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_CPPM_NC1INDIR_SCOM1                           , RULL(0x300F0134), SH_UNT_PERV_48  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC16_CPPM_NC1INDIR_SCOM2                           , RULL(0x300F0135), SH_UNT_PERV_48  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC17_CPPM_NC1INDIR_SCOM                            , RULL(0x310F0133), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_CPPM_NC1INDIR_SCOM1                           , RULL(0x310F0134), SH_UNT_PERV_49  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC17_CPPM_NC1INDIR_SCOM2                           , RULL(0x310F0135), SH_UNT_PERV_49  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC18_CPPM_NC1INDIR_SCOM                            , RULL(0x320F0133), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_CPPM_NC1INDIR_SCOM1                           , RULL(0x320F0134), SH_UNT_PERV_50  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC18_CPPM_NC1INDIR_SCOM2                           , RULL(0x320F0135), SH_UNT_PERV_50  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC19_CPPM_NC1INDIR_SCOM                            , RULL(0x330F0133), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_CPPM_NC1INDIR_SCOM1                           , RULL(0x330F0134), SH_UNT_PERV_51  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC19_CPPM_NC1INDIR_SCOM2                           , RULL(0x330F0135), SH_UNT_PERV_51  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC20_CPPM_NC1INDIR_SCOM                            , RULL(0x340F0133), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_CPPM_NC1INDIR_SCOM1                           , RULL(0x340F0134), SH_UNT_PERV_52  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC20_CPPM_NC1INDIR_SCOM2                           , RULL(0x340F0135), SH_UNT_PERV_52  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC21_CPPM_NC1INDIR_SCOM                            , RULL(0x350F0133), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_CPPM_NC1INDIR_SCOM1                           , RULL(0x350F0134), SH_UNT_PERV_53  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC21_CPPM_NC1INDIR_SCOM2                           , RULL(0x350F0135), SH_UNT_PERV_53  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC22_CPPM_NC1INDIR_SCOM                            , RULL(0x360F0133), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_CPPM_NC1INDIR_SCOM1                           , RULL(0x360F0134), SH_UNT_PERV_54  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC22_CPPM_NC1INDIR_SCOM2                           , RULL(0x360F0135), SH_UNT_PERV_54  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC23_CPPM_NC1INDIR_SCOM                            , RULL(0x370F0133), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_CPPM_NC1INDIR_SCOM1                           , RULL(0x370F0134), SH_UNT_PERV_55  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC23_CPPM_NC1INDIR_SCOM2                           , RULL(0x370F0135), SH_UNT_PERV_55  , SH_ACS_SCOM2_NC  );
+
+REG64( PERV_EC00_CPPM_PECES                                    , RULL(0x200F01AF), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_CPPM_PECES                                    , RULL(0x210F01AF), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_CPPM_PECES                                    , RULL(0x220F01AF), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_CPPM_PECES                                    , RULL(0x230F01AF), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_CPPM_PECES                                    , RULL(0x240F01AF), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_CPPM_PECES                                    , RULL(0x250F01AF), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_CPPM_PECES                                    , RULL(0x260F01AF), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_CPPM_PECES                                    , RULL(0x270F01AF), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_CPPM_PECES                                    , RULL(0x280F01AF), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_CPPM_PECES                                    , RULL(0x290F01AF), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_CPPM_PECES                                    , RULL(0x2A0F01AF), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_CPPM_PECES                                    , RULL(0x2B0F01AF), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_CPPM_PECES                                    , RULL(0x2C0F01AF), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_CPPM_PECES                                    , RULL(0x2D0F01AF), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_CPPM_PECES                                    , RULL(0x2E0F01AF), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_CPPM_PECES                                    , RULL(0x2F0F01AF), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_CPPM_PECES                                    , RULL(0x300F01AF), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_CPPM_PECES                                    , RULL(0x310F01AF), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_CPPM_PECES                                    , RULL(0x320F01AF), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_CPPM_PECES                                    , RULL(0x330F01AF), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_CPPM_PECES                                    , RULL(0x340F01AF), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_CPPM_PECES                                    , RULL(0x350F01AF), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_CPPM_PECES                                    , RULL(0x360F01AF), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_CPPM_PECES                                    , RULL(0x370F01AF), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EC00_CPPM_PERRSUM                                  , RULL(0x200F0120), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC01_CPPM_PERRSUM                                  , RULL(0x210F0120), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC02_CPPM_PERRSUM                                  , RULL(0x220F0120), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC03_CPPM_PERRSUM                                  , RULL(0x230F0120), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC04_CPPM_PERRSUM                                  , RULL(0x240F0120), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC05_CPPM_PERRSUM                                  , RULL(0x250F0120), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC06_CPPM_PERRSUM                                  , RULL(0x260F0120), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC07_CPPM_PERRSUM                                  , RULL(0x270F0120), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC08_CPPM_PERRSUM                                  , RULL(0x280F0120), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC09_CPPM_PERRSUM                                  , RULL(0x290F0120), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC10_CPPM_PERRSUM                                  , RULL(0x2A0F0120), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC11_CPPM_PERRSUM                                  , RULL(0x2B0F0120), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC12_CPPM_PERRSUM                                  , RULL(0x2C0F0120), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC13_CPPM_PERRSUM                                  , RULL(0x2D0F0120), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC14_CPPM_PERRSUM                                  , RULL(0x2E0F0120), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC15_CPPM_PERRSUM                                  , RULL(0x2F0F0120), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC16_CPPM_PERRSUM                                  , RULL(0x300F0120), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC17_CPPM_PERRSUM                                  , RULL(0x310F0120), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC18_CPPM_PERRSUM                                  , RULL(0x320F0120), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC19_CPPM_PERRSUM                                  , RULL(0x330F0120), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC20_CPPM_PERRSUM                                  , RULL(0x340F0120), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC21_CPPM_PERRSUM                                  , RULL(0x350F0120), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC22_CPPM_PERRSUM                                  , RULL(0x360F0120), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EC23_CPPM_PERRSUM                                  , RULL(0x370F0120), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM_WCLEAR );
+
+REG64( PERV_CRSIC                                              , RULL(0x00030005), SH_UNT_PERV     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_PIB_CRSIC                                          , RULL(0x00030005), SH_UNT_PERV_0   ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_0_PIB2OPB0_CRSIC                                   , RULL(0x00020005), SH_UNT_PERV_0_PIB2OPB0,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_0_PIB2OPB1_CRSIC                                   , RULL(0x00020015), SH_UNT_PERV_0_PIB2OPB1,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_PIB2OPB0_CRSIC                                     , RULL(0x00020005), SH_UNT_PERV_PIB2OPB0,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_PIB2OPB1_CRSIC                                     , RULL(0x00020015), SH_UNT_PERV_PIB2OPB1,
+       SH_ACS_SCOM_WCLEAR );
+
+REG64( PERV_CRSIM                                              , RULL(0x00030006), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_CRSIM                                          , RULL(0x00030006), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+REG64( PERV_0_PIB2OPB0_CRSIM                                   , RULL(0x00020006), SH_UNT_PERV_0_PIB2OPB0,
+       SH_ACS_SCOM_RW   );
+REG64( PERV_0_PIB2OPB1_CRSIM                                   , RULL(0x00020016), SH_UNT_PERV_0_PIB2OPB1,
+       SH_ACS_SCOM_RW   );
+REG64( PERV_PIB2OPB0_CRSIM                                     , RULL(0x00020006), SH_UNT_PERV_PIB2OPB0,
+       SH_ACS_SCOM_RW   );
+REG64( PERV_PIB2OPB1_CRSIM                                     , RULL(0x00020016), SH_UNT_PERV_PIB2OPB1,
+       SH_ACS_SCOM_RW   );
+
+REG64( PERV_CRSIS                                              , RULL(0x00030007), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_CRSIS                                          , RULL(0x00030007), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+REG64( PERV_0_PIB2OPB0_CRSIS                                   , RULL(0x00020007), SH_UNT_PERV_0_PIB2OPB0,
+       SH_ACS_SCOM_RO   );
+REG64( PERV_0_PIB2OPB1_CRSIS                                   , RULL(0x00020017), SH_UNT_PERV_0_PIB2OPB1,
+       SH_ACS_SCOM_RO   );
+REG64( PERV_PIB2OPB0_CRSIS                                     , RULL(0x00020007), SH_UNT_PERV_PIB2OPB0,
+       SH_ACS_SCOM_RO   );
+REG64( PERV_PIB2OPB1_CRSIS                                     , RULL(0x00020017), SH_UNT_PERV_PIB2OPB1,
+       SH_ACS_SCOM_RO   );
+
+REG64( PERV_CTRL_ATOMIC_LOCK_REG                               , RULL(0x000003FF), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_CTRL_ATOMIC_LOCK_REG                            , RULL(0x010003FF), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CTRL_ATOMIC_LOCK_REG                            , RULL(0x020003FF), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CTRL_ATOMIC_LOCK_REG                            , RULL(0x030003FF), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CTRL_ATOMIC_LOCK_REG                            , RULL(0x040003FF), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CTRL_ATOMIC_LOCK_REG                            , RULL(0x050003FF), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CTRL_ATOMIC_LOCK_REG                            , RULL(0x060003FF), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CTRL_ATOMIC_LOCK_REG                          , RULL(0x070003FF), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CTRL_ATOMIC_LOCK_REG                          , RULL(0x080003FF), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CTRL_ATOMIC_LOCK_REG                           , RULL(0x090003FF), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CTRL_ATOMIC_LOCK_REG                           , RULL(0x0C0003FF), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CTRL_ATOMIC_LOCK_REG                          , RULL(0x0D0003FF), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CTRL_ATOMIC_LOCK_REG                          , RULL(0x0E0003FF), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CTRL_ATOMIC_LOCK_REG                          , RULL(0x0F0003FF), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CTRL_ATOMIC_LOCK_REG                          , RULL(0x100003FF), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CTRL_ATOMIC_LOCK_REG                          , RULL(0x110003FF), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CTRL_ATOMIC_LOCK_REG                          , RULL(0x120003FF), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CTRL_ATOMIC_LOCK_REG                          , RULL(0x130003FF), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CTRL_ATOMIC_LOCK_REG                          , RULL(0x140003FF), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CTRL_ATOMIC_LOCK_REG                          , RULL(0x150003FF), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CTRL_ATOMIC_LOCK_REG                          , RULL(0x200003FF), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CTRL_ATOMIC_LOCK_REG                          , RULL(0x210003FF), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CTRL_ATOMIC_LOCK_REG                          , RULL(0x220003FF), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CTRL_ATOMIC_LOCK_REG                          , RULL(0x230003FF), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CTRL_ATOMIC_LOCK_REG                          , RULL(0x240003FF), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CTRL_ATOMIC_LOCK_REG                          , RULL(0x250003FF), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CTRL_ATOMIC_LOCK_REG                          , RULL(0x260003FF), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CTRL_ATOMIC_LOCK_REG                          , RULL(0x270003FF), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CTRL_ATOMIC_LOCK_REG                          , RULL(0x280003FF), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CTRL_ATOMIC_LOCK_REG                          , RULL(0x290003FF), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CTRL_ATOMIC_LOCK_REG                          , RULL(0x2A0003FF), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CTRL_ATOMIC_LOCK_REG                          , RULL(0x2B0003FF), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CTRL_ATOMIC_LOCK_REG                          , RULL(0x2C0003FF), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CTRL_ATOMIC_LOCK_REG                          , RULL(0x2D0003FF), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CTRL_ATOMIC_LOCK_REG                          , RULL(0x2E0003FF), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CTRL_ATOMIC_LOCK_REG                          , RULL(0x2F0003FF), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CTRL_ATOMIC_LOCK_REG                          , RULL(0x300003FF), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CTRL_ATOMIC_LOCK_REG                          , RULL(0x310003FF), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CTRL_ATOMIC_LOCK_REG                          , RULL(0x320003FF), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CTRL_ATOMIC_LOCK_REG                          , RULL(0x330003FF), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CTRL_ATOMIC_LOCK_REG                          , RULL(0x340003FF), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CTRL_ATOMIC_LOCK_REG                          , RULL(0x350003FF), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CTRL_ATOMIC_LOCK_REG                          , RULL(0x360003FF), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CTRL_ATOMIC_LOCK_REG                          , RULL(0x370003FF), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_CTRL_PROTECT_MODE_REG                              , RULL(0x000003FE), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_CTRL_PROTECT_MODE_REG                           , RULL(0x010003FE), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_CTRL_PROTECT_MODE_REG                           , RULL(0x020003FE), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_CTRL_PROTECT_MODE_REG                           , RULL(0x030003FE), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_CTRL_PROTECT_MODE_REG                           , RULL(0x040003FE), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_CTRL_PROTECT_MODE_REG                           , RULL(0x050003FE), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_CTRL_PROTECT_MODE_REG                           , RULL(0x060003FE), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_CTRL_PROTECT_MODE_REG                         , RULL(0x070003FE), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_CTRL_PROTECT_MODE_REG                         , RULL(0x080003FE), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_CTRL_PROTECT_MODE_REG                          , RULL(0x090003FE), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_CTRL_PROTECT_MODE_REG                          , RULL(0x0C0003FE), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_CTRL_PROTECT_MODE_REG                         , RULL(0x0D0003FE), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_CTRL_PROTECT_MODE_REG                         , RULL(0x0E0003FE), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_CTRL_PROTECT_MODE_REG                         , RULL(0x0F0003FE), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_CTRL_PROTECT_MODE_REG                         , RULL(0x100003FE), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_CTRL_PROTECT_MODE_REG                         , RULL(0x110003FE), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_CTRL_PROTECT_MODE_REG                         , RULL(0x120003FE), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_CTRL_PROTECT_MODE_REG                         , RULL(0x130003FE), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_CTRL_PROTECT_MODE_REG                         , RULL(0x140003FE), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_CTRL_PROTECT_MODE_REG                         , RULL(0x150003FE), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_CTRL_PROTECT_MODE_REG                         , RULL(0x200003FE), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_CTRL_PROTECT_MODE_REG                         , RULL(0x210003FE), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_CTRL_PROTECT_MODE_REG                         , RULL(0x220003FE), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_CTRL_PROTECT_MODE_REG                         , RULL(0x230003FE), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_CTRL_PROTECT_MODE_REG                         , RULL(0x240003FE), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_CTRL_PROTECT_MODE_REG                         , RULL(0x250003FE), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_CTRL_PROTECT_MODE_REG                         , RULL(0x260003FE), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_CTRL_PROTECT_MODE_REG                         , RULL(0x270003FE), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_CTRL_PROTECT_MODE_REG                         , RULL(0x280003FE), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_CTRL_PROTECT_MODE_REG                         , RULL(0x290003FE), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_CTRL_PROTECT_MODE_REG                         , RULL(0x2A0003FE), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_CTRL_PROTECT_MODE_REG                         , RULL(0x2B0003FE), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_CTRL_PROTECT_MODE_REG                         , RULL(0x2C0003FE), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_CTRL_PROTECT_MODE_REG                         , RULL(0x2D0003FE), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_CTRL_PROTECT_MODE_REG                         , RULL(0x2E0003FE), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_CTRL_PROTECT_MODE_REG                         , RULL(0x2F0003FE), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_CTRL_PROTECT_MODE_REG                         , RULL(0x300003FE), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_CTRL_PROTECT_MODE_REG                         , RULL(0x310003FE), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_CTRL_PROTECT_MODE_REG                         , RULL(0x320003FE), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_CTRL_PROTECT_MODE_REG                         , RULL(0x330003FE), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_CTRL_PROTECT_MODE_REG                         , RULL(0x340003FE), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_CTRL_PROTECT_MODE_REG                         , RULL(0x350003FE), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_CTRL_PROTECT_MODE_REG                         , RULL(0x360003FE), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_CTRL_PROTECT_MODE_REG                         , RULL(0x370003FE), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG32( PERV_FSI2PIB_DATA_REGISTER_0_FSI                        , RULL(0x00001000), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI       );
+
+REG32( PERV_FSI2PIB_DATA_REGISTER_1_FSI                        , RULL(0x00001001), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_DATA_REGISTER_1_FSI_BYTE                   , RULL(0x00001004), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI_BYTE  );
+
+REG64( PERV_DBG_CBS_CC                                         , RULL(0x00030013), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_DBG_CBS_CC                                      , RULL(0x01030013), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_DBG_CBS_CC                                      , RULL(0x02030013), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_DBG_CBS_CC                                      , RULL(0x03030013), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_DBG_CBS_CC                                      , RULL(0x04030013), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_DBG_CBS_CC                                      , RULL(0x05030013), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_DBG_CBS_CC                                      , RULL(0x06030013), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_DBG_CBS_CC                                    , RULL(0x07030013), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_DBG_CBS_CC                                    , RULL(0x08030013), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_DBG_CBS_CC                                     , RULL(0x09030013), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_DBG_CBS_CC                                     , RULL(0x0C030013), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_DBG_CBS_CC                                    , RULL(0x0D030013), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_DBG_CBS_CC                                    , RULL(0x0E030013), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_DBG_CBS_CC                                    , RULL(0x0F030013), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_DBG_CBS_CC                                    , RULL(0x10030013), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_DBG_CBS_CC                                    , RULL(0x11030013), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_DBG_CBS_CC                                    , RULL(0x12030013), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_DBG_CBS_CC                                    , RULL(0x13030013), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_DBG_CBS_CC                                    , RULL(0x14030013), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_DBG_CBS_CC                                    , RULL(0x15030013), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_DBG_CBS_CC                                    , RULL(0x20030013), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_DBG_CBS_CC                                    , RULL(0x21030013), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_DBG_CBS_CC                                    , RULL(0x22030013), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_DBG_CBS_CC                                    , RULL(0x23030013), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_DBG_CBS_CC                                    , RULL(0x24030013), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_DBG_CBS_CC                                    , RULL(0x25030013), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_DBG_CBS_CC                                    , RULL(0x26030013), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_DBG_CBS_CC                                    , RULL(0x27030013), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_DBG_CBS_CC                                    , RULL(0x28030013), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_DBG_CBS_CC                                    , RULL(0x29030013), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_DBG_CBS_CC                                    , RULL(0x2A030013), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_DBG_CBS_CC                                    , RULL(0x2B030013), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_DBG_CBS_CC                                    , RULL(0x2C030013), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_DBG_CBS_CC                                    , RULL(0x2D030013), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_DBG_CBS_CC                                    , RULL(0x2E030013), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_DBG_CBS_CC                                    , RULL(0x2F030013), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_DBG_CBS_CC                                    , RULL(0x30030013), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_DBG_CBS_CC                                    , RULL(0x31030013), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_DBG_CBS_CC                                    , RULL(0x32030013), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_DBG_CBS_CC                                    , RULL(0x33030013), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_DBG_CBS_CC                                    , RULL(0x34030013), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_DBG_CBS_CC                                    , RULL(0x35030013), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_DBG_CBS_CC                                    , RULL(0x36030013), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_DBG_CBS_CC                                    , RULL(0x37030013), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_DBG_INST1_COND_REG_1                               , RULL(0x000107C1), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_DBG_INST1_COND_REG_1                            , RULL(0x010107C1), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_DBG_INST1_COND_REG_2                               , RULL(0x000107C2), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_DBG_INST1_COND_REG_2                            , RULL(0x010107C2), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_DBG_INST1_COND_REG_3                               , RULL(0x000107C3), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_DBG_INST1_COND_REG_3                            , RULL(0x010107C3), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_DBG_INST2_COND_REG_1                               , RULL(0x000107C4), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_DBG_INST2_COND_REG_1                            , RULL(0x010107C4), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_DBG_INST2_COND_REG_2                               , RULL(0x000107C5), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_DBG_INST2_COND_REG_2                            , RULL(0x010107C5), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_DBG_INST2_COND_REG_3                               , RULL(0x000107C6), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_DBG_INST2_COND_REG_3                            , RULL(0x010107C6), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_DBG_MODE_REG                                       , RULL(0x000107C0), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_DBG_MODE_REG                                    , RULL(0x010107C0), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_DBG_TRACE_MODE_REG_2                               , RULL(0x000107CF), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_DBG_TRACE_MODE_REG_2                            , RULL(0x010107CF), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_DBG_TRACE_REG_0                                    , RULL(0x000107CD), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_DBG_TRACE_REG_0                                 , RULL(0x010107CD), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_DBG_TRACE_REG_1                                    , RULL(0x000107CE), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_DBG_TRACE_REG_1                                 , RULL(0x010107CE), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_DEBUG_TRACE_CONTROL                                , RULL(0x000107D0), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_DEBUG_TRACE_CONTROL                             , RULL(0x010107D0), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_DEVICE_ID_REG                                      , RULL(0x000F000F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_DEVICE_ID_REG                                  , RULL(0x000F000F), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_FSISHIFT_DMA_ERROR_PTR_REGISTER_FSI                , RULL(0x00000C21), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_ERROR_PTR_REGISTER_FSI_BYTE           , RULL(0x00000C84), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_MODE_REGISTER_FSI                     , RULL(0x00000C19), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_MODE_REGISTER_FSI_BYTE                , RULL(0x00000C64), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_FSI             , RULL(0x00000C1B), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_FSI_BYTE        , RULL(0x00000C6C), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER0_REGISTER_FSI          , RULL(0x00000C1F), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER0_REGISTER_FSI_BYTE     , RULL(0x00000C7C), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER1_REGISTER_FSI          , RULL(0x00000C20), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER1_REGISTER_FSI_BYTE     , RULL(0x00000C80), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_PIB_SND_BUFFER0_REGISTER_FSI          , RULL(0x00000C1D), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_PIB_SND_BUFFER0_REGISTER_FSI_BYTE     , RULL(0x00000C74), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_PIB_SND_BUFFER1_REGISTER_FSI          , RULL(0x00000C1E), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_PIB_SND_BUFFER1_REGISTER_FSI_BYTE     , RULL(0x00000C78), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_REM_SIZE_REGISTER_FSI                 , RULL(0x00000C1C), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_REM_SIZE_REGISTER_FSI_BYTE            , RULL(0x00000C70), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_SCOM_CMD_REGISTER_FSI                 , RULL(0x00000C22), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_SCOM_CMD_REGISTER_FSI_BYTE            , RULL(0x00000C88), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_DMA_STAT_COMP_MASK_REGISTER_FSI           , RULL(0x00000C1A), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_DMA_STAT_COMP_MASK_REGISTER_FSI_BYTE      , RULL(0x00000C68), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG32( PERV_DOORBELL_STATUS_CONTROL_1A_FSI                     , RULL(0x00002824), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_DOORBELL_STATUS_CONTROL_1A_FSI_BYTE                , RULL(0x00002890), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_DOORBELL_STATUS_CONTROL_1A_SCOM                    , RULL(0x00050020), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_DOORBELL_STATUS_CONTROL_1A                     , RULL(0x00050020), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_DOORBELL_STATUS_CONTROL_2A_FSI                     , RULL(0x0000282C), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_DOORBELL_STATUS_CONTROL_2A_FSI_BYTE                , RULL(0x000028B0), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_DOORBELL_STATUS_CONTROL_2A_SCOM                    , RULL(0x00050028), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_DOORBELL_STATUS_CONTROL_2A                     , RULL(0x00050028), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_DTS_RESULT0                                        , RULL(0x00050000), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_DTS_RESULT0                                     , RULL(0x01050000), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_DTS_RESULT0                                     , RULL(0x02050000), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_DTS_RESULT0                                     , RULL(0x03050000), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_DTS_RESULT0                                     , RULL(0x04050000), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_DTS_RESULT0                                     , RULL(0x05050000), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_DTS_RESULT0                                     , RULL(0x06050000), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_DTS_RESULT0                                   , RULL(0x07050000), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_DTS_RESULT0                                   , RULL(0x08050000), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_DTS_RESULT0                                    , RULL(0x09050000), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_DTS_RESULT0                                    , RULL(0x0C050000), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_DTS_RESULT0                                   , RULL(0x0D050000), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_DTS_RESULT0                                   , RULL(0x0E050000), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_DTS_RESULT0                                   , RULL(0x0F050000), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_DTS_RESULT0                                   , RULL(0x10050000), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_DTS_RESULT0                                   , RULL(0x11050000), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_DTS_RESULT0                                   , RULL(0x12050000), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_DTS_RESULT0                                   , RULL(0x13050000), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_DTS_RESULT0                                   , RULL(0x14050000), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_DTS_RESULT0                                   , RULL(0x15050000), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_DTS_RESULT0                                   , RULL(0x20050000), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_DTS_RESULT0                                   , RULL(0x21050000), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_DTS_RESULT0                                   , RULL(0x22050000), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_DTS_RESULT0                                   , RULL(0x23050000), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_DTS_RESULT0                                   , RULL(0x24050000), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_DTS_RESULT0                                   , RULL(0x25050000), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_DTS_RESULT0                                   , RULL(0x26050000), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_DTS_RESULT0                                   , RULL(0x27050000), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_DTS_RESULT0                                   , RULL(0x28050000), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_DTS_RESULT0                                   , RULL(0x29050000), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_DTS_RESULT0                                   , RULL(0x2A050000), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_DTS_RESULT0                                   , RULL(0x2B050000), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_DTS_RESULT0                                   , RULL(0x2C050000), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_DTS_RESULT0                                   , RULL(0x2D050000), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_DTS_RESULT0                                   , RULL(0x2E050000), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_DTS_RESULT0                                   , RULL(0x2F050000), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_DTS_RESULT0                                   , RULL(0x30050000), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_DTS_RESULT0                                   , RULL(0x31050000), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_DTS_RESULT0                                   , RULL(0x32050000), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_DTS_RESULT0                                   , RULL(0x33050000), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_DTS_RESULT0                                   , RULL(0x34050000), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_DTS_RESULT0                                   , RULL(0x35050000), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_DTS_RESULT0                                   , RULL(0x36050000), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_DTS_RESULT0                                   , RULL(0x37050000), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_DTS_TRC_RESULT                                     , RULL(0x00050003), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_DTS_TRC_RESULT                                  , RULL(0x01050003), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_DTS_TRC_RESULT                                  , RULL(0x02050003), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_DTS_TRC_RESULT                                  , RULL(0x03050003), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_DTS_TRC_RESULT                                  , RULL(0x04050003), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_DTS_TRC_RESULT                                  , RULL(0x05050003), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_DTS_TRC_RESULT                                  , RULL(0x06050003), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_DTS_TRC_RESULT                                , RULL(0x07050003), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_DTS_TRC_RESULT                                , RULL(0x08050003), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_DTS_TRC_RESULT                                 , RULL(0x09050003), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_DTS_TRC_RESULT                                 , RULL(0x0C050003), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_DTS_TRC_RESULT                                , RULL(0x0D050003), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_DTS_TRC_RESULT                                , RULL(0x0E050003), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_DTS_TRC_RESULT                                , RULL(0x0F050003), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_DTS_TRC_RESULT                                , RULL(0x10050003), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_DTS_TRC_RESULT                                , RULL(0x11050003), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_DTS_TRC_RESULT                                , RULL(0x12050003), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_DTS_TRC_RESULT                                , RULL(0x13050003), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_DTS_TRC_RESULT                                , RULL(0x14050003), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_DTS_TRC_RESULT                                , RULL(0x15050003), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_DTS_TRC_RESULT                                , RULL(0x20050003), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_DTS_TRC_RESULT                                , RULL(0x21050003), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_DTS_TRC_RESULT                                , RULL(0x22050003), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_DTS_TRC_RESULT                                , RULL(0x23050003), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_DTS_TRC_RESULT                                , RULL(0x24050003), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_DTS_TRC_RESULT                                , RULL(0x25050003), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_DTS_TRC_RESULT                                , RULL(0x26050003), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_DTS_TRC_RESULT                                , RULL(0x27050003), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_DTS_TRC_RESULT                                , RULL(0x28050003), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_DTS_TRC_RESULT                                , RULL(0x29050003), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_DTS_TRC_RESULT                                , RULL(0x2A050003), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_DTS_TRC_RESULT                                , RULL(0x2B050003), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_DTS_TRC_RESULT                                , RULL(0x2C050003), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_DTS_TRC_RESULT                                , RULL(0x2D050003), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_DTS_TRC_RESULT                                , RULL(0x2E050003), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_DTS_TRC_RESULT                                , RULL(0x2F050003), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_DTS_TRC_RESULT                                , RULL(0x30050003), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_DTS_TRC_RESULT                                , RULL(0x31050003), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_DTS_TRC_RESULT                                , RULL(0x32050003), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_DTS_TRC_RESULT                                , RULL(0x33050003), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_DTS_TRC_RESULT                                , RULL(0x34050003), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_DTS_TRC_RESULT                                , RULL(0x35050003), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_DTS_TRC_RESULT                                , RULL(0x36050003), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_DTS_TRC_RESULT                                , RULL(0x37050003), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_ERROR_REG                                          , RULL(0x000F001F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ERROR_REG                                      , RULL(0x000F001F), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+REG64( PERV_TP_ERROR_REG                                       , RULL(0x010F001F), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_ERROR_REG                                       , RULL(0x020F001F), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_ERROR_REG                                       , RULL(0x030F001F), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_ERROR_REG                                       , RULL(0x040F001F), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_ERROR_REG                                       , RULL(0x050F001F), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_ERROR_REG                                       , RULL(0x060F001F), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_ERROR_REG                                     , RULL(0x070F001F), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_ERROR_REG                                     , RULL(0x080F001F), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_ERROR_REG                                      , RULL(0x090F001F), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_ERROR_REG                                      , RULL(0x0C0F001F), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_ERROR_REG                                     , RULL(0x0D0F001F), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_ERROR_REG                                     , RULL(0x0E0F001F), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_ERROR_REG                                     , RULL(0x0F0F001F), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_ERROR_REG                                     , RULL(0x100F001F), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_ERROR_REG                                     , RULL(0x110F001F), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_ERROR_REG                                     , RULL(0x120F001F), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_ERROR_REG                                     , RULL(0x130F001F), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_ERROR_REG                                     , RULL(0x140F001F), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_ERROR_REG                                     , RULL(0x150F001F), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_ERROR_REG                                     , RULL(0x200F001F), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_ERROR_REG                                     , RULL(0x210F001F), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_ERROR_REG                                     , RULL(0x220F001F), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_ERROR_REG                                     , RULL(0x230F001F), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_ERROR_REG                                     , RULL(0x240F001F), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_ERROR_REG                                     , RULL(0x250F001F), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_ERROR_REG                                     , RULL(0x260F001F), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_ERROR_REG                                     , RULL(0x270F001F), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_ERROR_REG                                     , RULL(0x280F001F), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_ERROR_REG                                     , RULL(0x290F001F), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_ERROR_REG                                     , RULL(0x2A0F001F), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_ERROR_REG                                     , RULL(0x2B0F001F), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_ERROR_REG                                     , RULL(0x2C0F001F), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_ERROR_REG                                     , RULL(0x2D0F001F), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_ERROR_REG                                     , RULL(0x2E0F001F), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_ERROR_REG                                     , RULL(0x2F0F001F), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_ERROR_REG                                     , RULL(0x300F001F), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_ERROR_REG                                     , RULL(0x310F001F), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_ERROR_REG                                     , RULL(0x320F001F), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_ERROR_REG                                     , RULL(0x330F001F), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_ERROR_REG                                     , RULL(0x340F001F), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_ERROR_REG                                     , RULL(0x350F001F), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_ERROR_REG                                     , RULL(0x360F001F), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_ERROR_REG                                     , RULL(0x370F001F), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_ERROR_STATUS                                       , RULL(0x0003000F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_ERROR_STATUS                                    , RULL(0x0103000F), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_ERROR_STATUS                                    , RULL(0x0203000F), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_ERROR_STATUS                                    , RULL(0x0303000F), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_ERROR_STATUS                                    , RULL(0x0403000F), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_ERROR_STATUS                                    , RULL(0x0503000F), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_ERROR_STATUS                                    , RULL(0x0603000F), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_ERROR_STATUS                                  , RULL(0x0703000F), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_ERROR_STATUS                                  , RULL(0x0803000F), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_ERROR_STATUS                                   , RULL(0x0903000F), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_ERROR_STATUS                                   , RULL(0x0C03000F), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_ERROR_STATUS                                  , RULL(0x0D03000F), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_ERROR_STATUS                                  , RULL(0x0E03000F), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_ERROR_STATUS                                  , RULL(0x0F03000F), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_ERROR_STATUS                                  , RULL(0x1003000F), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_ERROR_STATUS                                  , RULL(0x1103000F), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_ERROR_STATUS                                  , RULL(0x1203000F), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_ERROR_STATUS                                  , RULL(0x1303000F), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_ERROR_STATUS                                  , RULL(0x1403000F), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_ERROR_STATUS                                  , RULL(0x1503000F), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_ERROR_STATUS                                  , RULL(0x2003000F), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_ERROR_STATUS                                  , RULL(0x2103000F), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_ERROR_STATUS                                  , RULL(0x2203000F), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_ERROR_STATUS                                  , RULL(0x2303000F), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_ERROR_STATUS                                  , RULL(0x2403000F), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_ERROR_STATUS                                  , RULL(0x2503000F), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_ERROR_STATUS                                  , RULL(0x2603000F), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_ERROR_STATUS                                  , RULL(0x2703000F), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_ERROR_STATUS                                  , RULL(0x2803000F), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_ERROR_STATUS                                  , RULL(0x2903000F), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_ERROR_STATUS                                  , RULL(0x2A03000F), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_ERROR_STATUS                                  , RULL(0x2B03000F), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_ERROR_STATUS                                  , RULL(0x2C03000F), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_ERROR_STATUS                                  , RULL(0x2D03000F), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_ERROR_STATUS                                  , RULL(0x2E03000F), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_ERROR_STATUS                                  , RULL(0x2F03000F), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_ERROR_STATUS                                  , RULL(0x3003000F), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_ERROR_STATUS                                  , RULL(0x3103000F), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_ERROR_STATUS                                  , RULL(0x3203000F), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_ERROR_STATUS                                  , RULL(0x3303000F), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_ERROR_STATUS                                  , RULL(0x3403000F), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_ERROR_STATUS                                  , RULL(0x3503000F), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_ERROR_STATUS                                  , RULL(0x3603000F), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_ERROR_STATUS                                  , RULL(0x3703000F), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_ERROR_STATUS_REG                                   , RULL(0x000F0034), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ERROR_STATUS_REG                               , RULL(0x000F0034), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_ERR_STATUS_REG                                     , RULL(0x00050013), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_ERR_STATUS_REG                                  , RULL(0x01050013), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_ERR_STATUS_REG                                  , RULL(0x02050013), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_ERR_STATUS_REG                                  , RULL(0x03050013), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_ERR_STATUS_REG                                  , RULL(0x04050013), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_ERR_STATUS_REG                                  , RULL(0x05050013), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_ERR_STATUS_REG                                  , RULL(0x06050013), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_ERR_STATUS_REG                                , RULL(0x07050013), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_ERR_STATUS_REG                                , RULL(0x08050013), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_ERR_STATUS_REG                                 , RULL(0x09050013), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_ERR_STATUS_REG                                 , RULL(0x0C050013), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_ERR_STATUS_REG                                , RULL(0x0D050013), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_ERR_STATUS_REG                                , RULL(0x0E050013), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_ERR_STATUS_REG                                , RULL(0x0F050013), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_ERR_STATUS_REG                                , RULL(0x10050013), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_ERR_STATUS_REG                                , RULL(0x11050013), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_ERR_STATUS_REG                                , RULL(0x12050013), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_ERR_STATUS_REG                                , RULL(0x13050013), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_ERR_STATUS_REG                                , RULL(0x14050013), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_ERR_STATUS_REG                                , RULL(0x15050013), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_ERR_STATUS_REG                                , RULL(0x20050013), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_ERR_STATUS_REG                                , RULL(0x21050013), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_ERR_STATUS_REG                                , RULL(0x22050013), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_ERR_STATUS_REG                                , RULL(0x23050013), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_ERR_STATUS_REG                                , RULL(0x24050013), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_ERR_STATUS_REG                                , RULL(0x25050013), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_ERR_STATUS_REG                                , RULL(0x26050013), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_ERR_STATUS_REG                                , RULL(0x27050013), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_ERR_STATUS_REG                                , RULL(0x28050013), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_ERR_STATUS_REG                                , RULL(0x29050013), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_ERR_STATUS_REG                                , RULL(0x2A050013), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_ERR_STATUS_REG                                , RULL(0x2B050013), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_ERR_STATUS_REG                                , RULL(0x2C050013), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_ERR_STATUS_REG                                , RULL(0x2D050013), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_ERR_STATUS_REG                                , RULL(0x2E050013), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_ERR_STATUS_REG                                , RULL(0x2F050013), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_ERR_STATUS_REG                                , RULL(0x30050013), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_ERR_STATUS_REG                                , RULL(0x31050013), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_ERR_STATUS_REG                                , RULL(0x32050013), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_ERR_STATUS_REG                                , RULL(0x33050013), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_ERR_STATUS_REG                                , RULL(0x34050013), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_ERR_STATUS_REG                                , RULL(0x35050013), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_ERR_STATUS_REG                                , RULL(0x36050013), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_ERR_STATUS_REG                                , RULL(0x37050013), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG32( PERV_FSISHIFT_EXTENDED_STATUS_FSI                       , RULL(0x00000C08), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_EXTENDED_STATUS_FSI_BYTE                  , RULL(0x00000C20), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG64( PERV_0_FSII2C_EXTENDED_STATUS_A                         , RULL(0x00001808), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      );
+REG32( PERV_FSII2C_EXTENDED_STATUS_A                           , RULL(0x00001808), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_FIFO1_REGISTER_READ_A                     , RULL(0x00001800), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      );
+REG32( PERV_FSII2C_FIFO1_REGISTER_READ_A                       , RULL(0x00001800), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      );
+
+REG64( PERV_FIRST_ERR_REG                                      , RULL(0x000F001E), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_FIRST_ERR_REG                                  , RULL(0x000F001E), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_FIRST_REPLY_REG                                    , RULL(0x000F0018), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_FIRST_REPLY_REG                                , RULL(0x000F0018), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_FIR_MASK                                           , RULL(0x00040002), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_FIR_MASK                                        , RULL(0x01040002), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_FIR_MASK                                        , RULL(0x02040002), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_FIR_MASK                                        , RULL(0x03040002), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_FIR_MASK                                        , RULL(0x04040002), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_FIR_MASK                                        , RULL(0x05040002), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_FIR_MASK                                        , RULL(0x06040002), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_FIR_MASK                                      , RULL(0x07040002), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_FIR_MASK                                      , RULL(0x08040002), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_FIR_MASK                                       , RULL(0x09040002), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_FIR_MASK                                       , RULL(0x0C040002), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_FIR_MASK                                      , RULL(0x0D040002), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_FIR_MASK                                      , RULL(0x0E040002), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_FIR_MASK                                      , RULL(0x0F040002), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_FIR_MASK                                      , RULL(0x10040002), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_FIR_MASK                                      , RULL(0x11040002), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_FIR_MASK                                      , RULL(0x12040002), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_FIR_MASK                                      , RULL(0x13040002), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_FIR_MASK                                      , RULL(0x14040002), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_FIR_MASK                                      , RULL(0x15040002), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_FIR_MASK                                      , RULL(0x20040002), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_FIR_MASK                                      , RULL(0x21040002), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_FIR_MASK                                      , RULL(0x22040002), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_FIR_MASK                                      , RULL(0x23040002), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_FIR_MASK                                      , RULL(0x24040002), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_FIR_MASK                                      , RULL(0x25040002), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_FIR_MASK                                      , RULL(0x26040002), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_FIR_MASK                                      , RULL(0x27040002), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_FIR_MASK                                      , RULL(0x28040002), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_FIR_MASK                                      , RULL(0x29040002), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_FIR_MASK                                      , RULL(0x2A040002), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_FIR_MASK                                      , RULL(0x2B040002), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_FIR_MASK                                      , RULL(0x2C040002), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_FIR_MASK                                      , RULL(0x2D040002), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_FIR_MASK                                      , RULL(0x2E040002), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_FIR_MASK                                      , RULL(0x2F040002), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_FIR_MASK                                      , RULL(0x30040002), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_FIR_MASK                                      , RULL(0x31040002), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_FIR_MASK                                      , RULL(0x32040002), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_FIR_MASK                                      , RULL(0x33040002), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_FIR_MASK                                      , RULL(0x34040002), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_FIR_MASK                                      , RULL(0x35040002), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_FIR_MASK                                      , RULL(0x36040002), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_FIR_MASK                                      , RULL(0x37040002), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_FMU_FORCE_OP_REG                                   , RULL(0x00020003), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_FMU_FORCE_OP_REG                                , RULL(0x01020003), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_FMU_KVREF_DATAREG                                  , RULL(0x00020004), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_FMU_KVREF_DATAREG                               , RULL(0x01020004), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_FMU_MODE_REG                                       , RULL(0x00020000), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_FMU_MODE_REG                                    , RULL(0x01020000), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_FMU_OSC_CNTR1_REG                                  , RULL(0x00020001), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_FMU_OSC_CNTR1_REG                               , RULL(0x01020001), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_FMU_OSC_CNTR2_REG                                  , RULL(0x00020002), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_FMU_OSC_CNTR2_REG                               , RULL(0x01020002), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_FMU_PULSE_GEN_REG                                  , RULL(0x00020001), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_TP_FMU_PULSE_GEN_REG                               , RULL(0x01020001), SH_UNT_PERV_1   ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PERV_FMU_VMEAS_MAX_RESULT                               , RULL(0x00020008), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_FMU_VMEAS_MAX_RESULT                            , RULL(0x01020008), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_FMU_VMEAS_MIN_RESULT                               , RULL(0x00020009), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_FMU_VMEAS_MIN_RESULT                            , RULL(0x01020009), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+
+REG32( PERV_FSISHIFT_FRONT_END_LENGTH_REGISTER_FSI             , RULL(0x00000C02), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_FRONT_END_LENGTH_REGISTER_FSI_BYTE        , RULL(0x00000C08), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSB_FSB_DNFIFO_DATA_OUT_FSI                        , RULL(0x00002410), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+REG64( PERV_FSB_FSB_DNFIFO_DATA_OUT_FSI_BYTE                   , RULL(0x00002440), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSB_FSB_DOWNFIFO_ACK_EOT_FSI                       , RULL(0x00002415), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+REG64( PERV_FSB_FSB_DOWNFIFO_ACK_EOT_FSI_BYTE                  , RULL(0x00002454), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSB_FSB_DOWNFIFO_RESET_FSI                         , RULL(0x00002414), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+REG64( PERV_FSB_FSB_DOWNFIFO_RESET_FSI_BYTE                    , RULL(0x00002450), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSB_FSB_DOWNFIFO_STATUS_FSI                        , RULL(0x00002411), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+REG64( PERV_FSB_FSB_DOWNFIFO_STATUS_FSI_BYTE                   , RULL(0x00002444), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSB_FSB_UPFIFO_DATA_IN_FSI                         , RULL(0x00002400), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+
+REG32( PERV_FSB_FSB_UPFIFO_REQ_RESET_FSI                       , RULL(0x00002403), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+REG64( PERV_FSB_FSB_UPFIFO_REQ_RESET_FSI_BYTE                  , RULL(0x0000240C), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSB_FSB_UPFIFO_SIG_EOT_FSI                         , RULL(0x00002402), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+REG64( PERV_FSB_FSB_UPFIFO_SIG_EOT_FSI_BYTE                    , RULL(0x00002408), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSB_FSB_UPFIFO_STATUS_FSI                          , RULL(0x00002401), SH_UNT_PERV_FSB , SH_ACS_FSI       );
+REG64( PERV_FSB_FSB_UPFIFO_STATUS_FSI_BYTE                     , RULL(0x00002404), SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISCRPD1_FSI                                      , RULL(0x00001401), SH_UNT_PERV     , SH_ACS_FSI       );
+REG32( PERV_FSISCRPD1_FSI_BYTE                                 , RULL(0x00001404), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISCRPD2_FSI                                      , RULL(0x00001402), SH_UNT_PERV     , SH_ACS_FSI       );
+REG32( PERV_FSISCRPD2_FSI_BYTE                                 , RULL(0x00001408), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISCRPD3_FSI                                      , RULL(0x00001403), SH_UNT_PERV     , SH_ACS_FSI       );
+REG32( PERV_FSISCRPD3_FSI_BYTE                                 , RULL(0x0000140C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSI_A_LLMOD_FSI0                                   , RULL(0x00000900), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_LLSTAT_FSI0                                  , RULL(0x00000904), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_MST_0_MAEB_FSI0                              , RULL(0x00003070), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAEB                          , RULL(0x00000C1C), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MAESP0_FSI0                            , RULL(0x00003050), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP0                        , RULL(0x00000C14), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MAESP1_FSI0                            , RULL(0x00003054), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP1                        , RULL(0x00000C15), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MAESP2_FSI0                            , RULL(0x00003058), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP2                        , RULL(0x00000C16), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MAESP3_FSI0                            , RULL(0x0000305C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP3                        , RULL(0x00000C17), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MAESP4_FSI0                            , RULL(0x00003060), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP4                        , RULL(0x00000C18), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MAESP5_FSI0                            , RULL(0x00003064), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP5                        , RULL(0x00000C19), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MAESP6_FSI0                            , RULL(0x00003068), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP6                        , RULL(0x00000C1A), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MAESP7_FSI0                            , RULL(0x0000306C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MAESP7                        , RULL(0x00000C1B), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MATRB0_FSI0                            , RULL(0x000031D8), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MATRB0                        , RULL(0x00000C76), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MCENP0_FSI0                            , RULL(0x00003020), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MCENP0                        , RULL(0x00000C08), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MCRSP0_FSI0                            , RULL(0x00003008), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MCRSP0                        , RULL(0x00000C02), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MCRSP1_FSI0                            , RULL(0x0000300C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MCRSP1                        , RULL(0x00000C03), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MCSIEP0_FSI0                           , RULL(0x00003070), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MCSIEP0                       , RULL(0x00000C1C), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0_CLEAR );
+
+REG32( PERV_FSI_A_MST_0_MDLYR_FSI0                             , RULL(0x00003004), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MDLYR                         , RULL(0x00000C01), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MDTRB0_FSI0                            , RULL(0x000031DC), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MDTRB0                        , RULL(0x00000C77), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MECTRL_FSI0                            , RULL(0x000032E0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MECTRL                        , RULL(0x00000CB8), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MENP0_FSI0                             , RULL(0x00003010), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MENP0                         , RULL(0x00000C04), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MENP1_FSI0                             , RULL(0x00003014), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MENP1                         , RULL(0x00000C05), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MESRB0_FSI0                            , RULL(0x000031D0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MESRB0                        , RULL(0x00000C74), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MLEVP0_FSI0                            , RULL(0x00003018), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MLEVP0                        , RULL(0x00000C06), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MLEVP1_FSI0                            , RULL(0x0000301C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MLEVP1                        , RULL(0x00000C07), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MMODE_FSI0                             , RULL(0x00003000), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MMODE                         , RULL(0x00000C00), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MREFP0_FSI0                            , RULL(0x00003020), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MREFP0                        , RULL(0x00000C08), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MREFP1_FSI0                            , RULL(0x00003024), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MREFP1                        , RULL(0x00000C09), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MRESB0_FSI0                            , RULL(0x000031D0), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESB0                        , RULL(0x00000C74), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MRESP0_FSI0                            , RULL(0x000030D0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP0                        , RULL(0x00000C34), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MRESP1_FSI0                            , RULL(0x000030D4), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP1                        , RULL(0x00000C35), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MRESP2_FSI0                            , RULL(0x000030D8), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP2                        , RULL(0x00000C36), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MRESP3_FSI0                            , RULL(0x000030DC), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP3                        , RULL(0x00000C37), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MRESP4_FSI0                            , RULL(0x000030E0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP4                        , RULL(0x00000C38), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MRESP5_FSI0                            , RULL(0x000030E4), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP5                        , RULL(0x00000C39), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MRESP6_FSI0                            , RULL(0x000030E8), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP6                        , RULL(0x00000C3A), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MRESP7_FSI0                            , RULL(0x000030EC), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MRESP7                        , RULL(0x00000C3B), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSCSB0_FSI0                            , RULL(0x000031D4), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSCSB0                        , RULL(0x00000C75), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_0_MSENP0_FSI0                            , RULL(0x00003018), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSENP0                        , RULL(0x00000C06), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSIEP0_FSI0                            , RULL(0x00003030), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP0                        , RULL(0x00000C0C), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0_RW );
+
+REG32( PERV_FSI_A_MST_0_MSIEP1_FSI0                            , RULL(0x00003034), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP1                        , RULL(0x00000C0D), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSIEP2_FSI0                            , RULL(0x00003038), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP2                        , RULL(0x00000C0E), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSIEP3_FSI0                            , RULL(0x0000303C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP3                        , RULL(0x00000C0F), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSIEP4_FSI0                            , RULL(0x00003040), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP4                        , RULL(0x00000C10), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSIEP5_FSI0                            , RULL(0x00003044), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP5                        , RULL(0x00000C11), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSIEP6_FSI0                            , RULL(0x00003048), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP6                        , RULL(0x00000C12), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSIEP7_FSI0                            , RULL(0x0000304C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSIEP7                        , RULL(0x00000C13), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_0_MSSIEP0_FSI0                           , RULL(0x00003050), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSSIEP0                       , RULL(0x00000C14), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0_OR );
+
+REG32( PERV_FSI_A_MST_0_MSTAP0_FSI0                            , RULL(0x000030D0), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0                        , RULL(0x00000C34), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MSTAP1_FSI0                            , RULL(0x000030D4), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1                        , RULL(0x00000C35), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MSTAP2_FSI0                            , RULL(0x000030D8), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2                        , RULL(0x00000C36), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MSTAP3_FSI0                            , RULL(0x000030DC), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3                        , RULL(0x00000C37), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MSTAP4_FSI0                            , RULL(0x000030E0), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4                        , RULL(0x00000C38), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MSTAP5_FSI0                            , RULL(0x000030E4), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5                        , RULL(0x00000C39), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MSTAP6_FSI0                            , RULL(0x000030E8), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6                        , RULL(0x00000C3A), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MSTAP7_FSI0                            , RULL(0x000030EC), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7                        , RULL(0x00000C3B), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_0_MVER_FSI0                              , RULL(0x00003074), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSISHIFT_FSI_A_MST_0_MVER                          , RULL(0x00000C1D), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAEB_FSI0                              , RULL(0x00003470), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAEB_SCOMFSI0                          , RULL(0x00000D1C), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAESP0_FSI0                            , RULL(0x00003450), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP0_SCOMFSI0                        , RULL(0x00000D14), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MAESP1_FSI0                            , RULL(0x00003454), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP1_SCOMFSI0                        , RULL(0x00000D15), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAESP2_FSI0                            , RULL(0x00003458), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP2_SCOMFSI0                        , RULL(0x00000D16), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAESP3_FSI0                            , RULL(0x0000345C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP3_SCOMFSI0                        , RULL(0x00000D17), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAESP4_FSI0                            , RULL(0x00003460), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP4_SCOMFSI0                        , RULL(0x00000D18), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAESP5_FSI0                            , RULL(0x00003464), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP5_SCOMFSI0                        , RULL(0x00000D19), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAESP6_FSI0                            , RULL(0x00003468), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP6_SCOMFSI0                        , RULL(0x00000D1A), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MAESP7_FSI0                            , RULL(0x0000346C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MAESP7_SCOMFSI0                        , RULL(0x00000D1B), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MATRB0_FSI0                            , RULL(0x000035D8), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MATRB0_SCOMFSI0                        , RULL(0x00000D76), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MCENP0_FSI0                            , RULL(0x00003420), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MCENP0_SCOMFSI0                        , RULL(0x00000D08), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MCRSP0_FSI0                            , RULL(0x00003408), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MCRSP0_SCOMFSI0                        , RULL(0x00000D02), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MCRSP1_FSI0                            , RULL(0x0000340C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MCRSP1_SCOMFSI0                        , RULL(0x00000D03), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MCSIEP0_FSI0                           , RULL(0x00003470), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MCSIEP0_SCOMFSI0                       , RULL(0x00000D1C), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0_CLEAR );
+
+REG32( PERV_FSI_A_MST_1_MDLYR_FSI0                             , RULL(0x00003404), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MDLYR_SCOMFSI0                         , RULL(0x00000D01), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MDTRB0_FSI0                            , RULL(0x000035DC), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MDTRB0_SCOMFSI0                        , RULL(0x00000D77), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MECTRL_FSI0                            , RULL(0x000036E0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MECTRL_SCOMFSI0                        , RULL(0x00000DB8), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MENP0_FSI0                             , RULL(0x00003410), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MENP0_SCOMFSI0                         , RULL(0x00000D04), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MENP1_FSI0                             , RULL(0x00003414), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MENP1_SCOMFSI0                         , RULL(0x00000D05), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MESRB0_FSI0                            , RULL(0x000035D0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MESRB0_SCOMFSI0                        , RULL(0x00000D74), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MLEVP0_FSI0                            , RULL(0x00003418), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MLEVP0_SCOMFSI0                        , RULL(0x00000D06), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MLEVP1_FSI0                            , RULL(0x0000341C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MLEVP1_SCOMFSI0                        , RULL(0x00000D07), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MMODE_FSI0                             , RULL(0x00003400), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MMODE_SCOMFSI0                         , RULL(0x00000D00), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MREFP0_FSI0                            , RULL(0x00003420), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MREFP0_SCOMFSI0                        , RULL(0x00000D08), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MREFP1_FSI0                            , RULL(0x00003424), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MREFP1_SCOMFSI0                        , RULL(0x00000D09), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MRESB0_FSI0                            , RULL(0x000035D0), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MRESB0_SCOMFSI0                        , RULL(0x00000D74), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MRESP0_FSI0                            , RULL(0x000034D0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP0_SCOMFSI0                        , RULL(0x00000D34), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MRESP1_FSI0                            , RULL(0x000034D4), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP1_SCOMFSI0                        , RULL(0x00000D35), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MRESP2_FSI0                            , RULL(0x000034D8), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP2_SCOMFSI0                        , RULL(0x00000D36), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MRESP3_FSI0                            , RULL(0x000034DC), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP3_SCOMFSI0                        , RULL(0x00000D37), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MRESP4_FSI0                            , RULL(0x000034E0), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP4_SCOMFSI0                        , RULL(0x00000D38), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MRESP5_FSI0                            , RULL(0x000034E4), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP5_SCOMFSI0                        , RULL(0x00000D39), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MRESP6_FSI0                            , RULL(0x000034E8), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP6_SCOMFSI0                        , RULL(0x00000D3A), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MRESP7_FSI0                            , RULL(0x000034EC), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MRESP7_SCOMFSI0                        , RULL(0x00000D3B), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSCSB0_FSI0                            , RULL(0x000035D4), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSCSB0_SCOMFSI0                        , RULL(0x00000D75), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0_RO );
+
+REG32( PERV_FSI_A_MST_1_MSENP0_FSI0                            , RULL(0x00003418), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSENP0_SCOMFSI0                        , RULL(0x00000D06), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSIEP0_FSI0                            , RULL(0x00003430), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP0_SCOMFSI0                        , RULL(0x00000D0C), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0_RW );
+
+REG32( PERV_FSI_A_MST_1_MSIEP1_FSI0                            , RULL(0x00003434), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP1_SCOMFSI0                        , RULL(0x00000D0D), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSIEP2_FSI0                            , RULL(0x00003438), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP2_SCOMFSI0                        , RULL(0x00000D0E), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSIEP3_FSI0                            , RULL(0x0000343C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP3_SCOMFSI0                        , RULL(0x00000D0F), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSIEP4_FSI0                            , RULL(0x00003440), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP4_SCOMFSI0                        , RULL(0x00000D10), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSIEP5_FSI0                            , RULL(0x00003444), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP5_SCOMFSI0                        , RULL(0x00000D11), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSIEP6_FSI0                            , RULL(0x00003448), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP6_SCOMFSI0                        , RULL(0x00000D12), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSIEP7_FSI0                            , RULL(0x0000344C), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MSIEP7_SCOMFSI0                        , RULL(0x00000D13), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_MST_1_MSSIEP0_FSI0                           , RULL(0x00003450), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSSIEP0_SCOMFSI0                       , RULL(0x00000D14), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0_OR );
+
+REG32( PERV_FSI_A_MST_1_MSTAP0_FSI0                            , RULL(0x000034D0), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP0_SCOMFSI0                        , RULL(0x00000D34), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MSTAP1_FSI0                            , RULL(0x000034D4), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP1_SCOMFSI0                        , RULL(0x00000D35), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MSTAP2_FSI0                            , RULL(0x000034D8), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP2_SCOMFSI0                        , RULL(0x00000D36), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MSTAP3_FSI0                            , RULL(0x000034DC), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP3_SCOMFSI0                        , RULL(0x00000D37), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MSTAP4_FSI0                            , RULL(0x000034E0), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP4_SCOMFSI0                        , RULL(0x00000D38), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MSTAP5_FSI0                            , RULL(0x000034E4), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP5_SCOMFSI0                        , RULL(0x00000D39), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MSTAP6_FSI0                            , RULL(0x000034E8), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP6_SCOMFSI0                        , RULL(0x00000D3A), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MSTAP7_FSI0                            , RULL(0x000034EC), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI_A_MST_1_MSTAP7_SCOMFSI0                        , RULL(0x00000D3B), SH_UNT_PERV     ,
+       SH_ACS_SCOMFSI0  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_MST_1_MVER_FSI0                              , RULL(0x00003474), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG32( PERV_FSI_A_MST_1_MVER_SCOMFSI0                          , RULL(0x00000D1D), SH_UNT_PERV     , SH_ACS_SCOMFSI0  );
+
+REG32( PERV_FSI_A_SCI1M_FSI0                                   , RULL(0x00000820), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCI2CM_FSI0                                  , RULL(0x0000082C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCISC_FSI0                                   , RULL(0x00000808), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCISM_FSI0                                   , RULL(0x00000814), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCMBL_FSI0                                   , RULL(0x00000840), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCMBR_FSI0                                   , RULL(0x0000084C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCMDT_FSI0                                   , RULL(0x0000082C), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SCRSIC0_FSI0                                 , RULL(0x00000850), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCRSIC4_FSI0                                 , RULL(0x00000854), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCRSIM0_FSI0                                 , RULL(0x00000858), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCRSIM4_FSI0                                 , RULL(0x0000085C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCRSIS0_FSI0                                 , RULL(0x00000860), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SCRSIS4_FSI0                                 , RULL(0x00000864), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SDATA_FSI0                                   , RULL(0x00000830), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SDMA_FSI0                                    , RULL(0x00000804), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SI1M_FSI0                                    , RULL(0x00000818), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SI1S_FSI0                                    , RULL(0x0000081C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SI2M_FSI0                                    , RULL(0x00000824), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SI2S_FSI0                                    , RULL(0x00000828), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SIC_FSI0                                     , RULL(0x00000820), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SISC_FSI0                                    , RULL(0x00000808), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SISM_FSI0                                    , RULL(0x0000080C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SISS_FSI0                                    , RULL(0x00000810), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SLASTD_SRES_FSI0                             , RULL(0x00000834), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SLBUS_FSI0                                   , RULL(0x00000830), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SMBL_FSI0                                    , RULL(0x00000838), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SMBR_FSI0                                    , RULL(0x00000844), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SMODE_FSI0                                   , RULL(0x00000800), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SNML_FSI0                                    , RULL(0x00000840), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SNMR_FSI0                                    , RULL(0x0000084C), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SOML_FSI0                                    , RULL(0x0000083C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SOMR_FSI0                                    , RULL(0x00000848), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SRSIC0_FSI0                                  , RULL(0x00000868), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SRSIC4_FSI0                                  , RULL(0x0000086C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SRSIM0_FSI0                                  , RULL(0x00000870), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SRSIM4_FSI0                                  , RULL(0x00000874), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SRSIS0_FSI0                                  , RULL(0x00000878), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SRSIS4_FSI0                                  , RULL(0x0000087C), SH_UNT_PERV     , SH_ACS_FSI0      );
+
+REG32( PERV_FSI_A_SSI1M_FSI0                                   , RULL(0x0000081C), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SSI2M_FSI0                                   , RULL(0x00000828), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SSISM_FSI0                                   , RULL(0x00000810), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SSMBL_FSI0                                   , RULL(0x0000083C), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SSMBR_FSI0                                   , RULL(0x00000848), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_A_SSTAT_FSI0                                   , RULL(0x00000814), SH_UNT_PERV     ,
+       SH_ACS_FSI0      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_LLMOD_FSI1                                   , RULL(0x00000900), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_LLSTAT_FSI1                                  , RULL(0x00000904), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_MST_0_MAEB_FSI1                              , RULL(0x00003070), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAEB                          , RULL(0x00000C1C), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MAESP0_FSI1                            , RULL(0x00003050), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP0                        , RULL(0x00000C14), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MAESP1_FSI1                            , RULL(0x00003054), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP1                        , RULL(0x00000C15), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MAESP2_FSI1                            , RULL(0x00003058), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP2                        , RULL(0x00000C16), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MAESP3_FSI1                            , RULL(0x0000305C), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP3                        , RULL(0x00000C17), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MAESP4_FSI1                            , RULL(0x00003060), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP4                        , RULL(0x00000C18), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MAESP5_FSI1                            , RULL(0x00003064), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP5                        , RULL(0x00000C19), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MAESP6_FSI1                            , RULL(0x00003068), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP6                        , RULL(0x00000C1A), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MAESP7_FSI1                            , RULL(0x0000306C), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MAESP7                        , RULL(0x00000C1B), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MATRB0_FSI1                            , RULL(0x000031D8), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MATRB0                        , RULL(0x00000C76), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MCENP0_FSI1                            , RULL(0x00003020), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MCENP0                        , RULL(0x00000C08), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MCRSP0_FSI1                            , RULL(0x00003008), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MCRSP0                        , RULL(0x00000C02), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MCRSP1_FSI1                            , RULL(0x0000300C), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MCRSP1                        , RULL(0x00000C03), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MCSIEP0_FSI1                           , RULL(0x00003070), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MCSIEP0                       , RULL(0x00000C1C), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1_CLEAR );
+
+REG32( PERV_FSI_B_MST_0_MDLYR_FSI1                             , RULL(0x00003004), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MDLYR                         , RULL(0x00000C01), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MDTRB0_FSI1                            , RULL(0x000031DC), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MDTRB0                        , RULL(0x00000C77), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MECTRL_FSI1                            , RULL(0x000032E0), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MECTRL                        , RULL(0x00000CB8), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MENP0_FSI1                             , RULL(0x00003010), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MENP0                         , RULL(0x00000C04), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MENP1_FSI1                             , RULL(0x00003014), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MENP1                         , RULL(0x00000C05), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MESRB0_FSI1                            , RULL(0x000031D0), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MESRB0                        , RULL(0x00000C74), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MLEVP0_FSI1                            , RULL(0x00003018), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MLEVP0                        , RULL(0x00000C06), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MLEVP1_FSI1                            , RULL(0x0000301C), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MLEVP1                        , RULL(0x00000C07), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MMODE_FSI1                             , RULL(0x00003000), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MMODE                         , RULL(0x00000C00), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MREFP0_FSI1                            , RULL(0x00003020), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MREFP0                        , RULL(0x00000C08), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MREFP1_FSI1                            , RULL(0x00003024), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MREFP1                        , RULL(0x00000C09), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MRESB0_FSI1                            , RULL(0x000031D0), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESB0                        , RULL(0x00000C74), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MRESP0_FSI1                            , RULL(0x000030D0), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP0                        , RULL(0x00000C34), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MRESP1_FSI1                            , RULL(0x000030D4), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP1                        , RULL(0x00000C35), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MRESP2_FSI1                            , RULL(0x000030D8), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP2                        , RULL(0x00000C36), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MRESP3_FSI1                            , RULL(0x000030DC), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP3                        , RULL(0x00000C37), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MRESP4_FSI1                            , RULL(0x000030E0), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP4                        , RULL(0x00000C38), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MRESP5_FSI1                            , RULL(0x000030E4), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP5                        , RULL(0x00000C39), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MRESP6_FSI1                            , RULL(0x000030E8), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP6                        , RULL(0x00000C3A), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MRESP7_FSI1                            , RULL(0x000030EC), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MRESP7                        , RULL(0x00000C3B), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSCSB0_FSI1                            , RULL(0x000031D4), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSCSB0                        , RULL(0x00000C75), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1_RO );
+
+REG32( PERV_FSI_B_MST_0_MSENP0_FSI1                            , RULL(0x00003018), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSENP0                        , RULL(0x00000C06), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSIEP0_FSI1                            , RULL(0x00003030), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP0                        , RULL(0x00000C0C), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1_RW );
+
+REG32( PERV_FSI_B_MST_0_MSIEP1_FSI1                            , RULL(0x00003034), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP1                        , RULL(0x00000C0D), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSIEP2_FSI1                            , RULL(0x00003038), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP2                        , RULL(0x00000C0E), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSIEP3_FSI1                            , RULL(0x0000303C), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP3                        , RULL(0x00000C0F), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSIEP4_FSI1                            , RULL(0x00003040), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP4                        , RULL(0x00000C10), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSIEP5_FSI1                            , RULL(0x00003044), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP5                        , RULL(0x00000C11), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSIEP6_FSI1                            , RULL(0x00003048), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP6                        , RULL(0x00000C12), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSIEP7_FSI1                            , RULL(0x0000304C), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSIEP7                        , RULL(0x00000C13), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_MST_0_MSSIEP0_FSI1                           , RULL(0x00003050), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSSIEP0                       , RULL(0x00000C14), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1_OR );
+
+REG32( PERV_FSI_B_MST_0_MSTAP0_FSI1                            , RULL(0x000030D0), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0                        , RULL(0x00000C34), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MSTAP1_FSI1                            , RULL(0x000030D4), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1                        , RULL(0x00000C35), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MSTAP2_FSI1                            , RULL(0x000030D8), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2                        , RULL(0x00000C36), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MSTAP3_FSI1                            , RULL(0x000030DC), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3                        , RULL(0x00000C37), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MSTAP4_FSI1                            , RULL(0x000030E0), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4                        , RULL(0x00000C38), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MSTAP5_FSI1                            , RULL(0x000030E4), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5                        , RULL(0x00000C39), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MSTAP6_FSI1                            , RULL(0x000030E8), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6                        , RULL(0x00000C3A), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MSTAP7_FSI1                            , RULL(0x000030EC), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7                        , RULL(0x00000C3B), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_MST_0_MVER_FSI1                              , RULL(0x00003074), SH_UNT_PERV     , SH_ACS_FSI1      );
+REG32( PERV_FSISHIFT_FSI_B_MST_0_MVER                          , RULL(0x00000C1D), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_SCOMFSI1  );
+
+REG32( PERV_FSI_B_SCI1M_FSI1                                   , RULL(0x00000820), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCI2CM_FSI1                                  , RULL(0x0000082C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCISC_FSI1                                   , RULL(0x00000808), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCISM_FSI1                                   , RULL(0x00000814), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCMBL_FSI1                                   , RULL(0x00000840), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCMBR_FSI1                                   , RULL(0x0000084C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCMDT_FSI1                                   , RULL(0x0000082C), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SCRSIC0_FSI1                                 , RULL(0x00000850), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCRSIC4_FSI1                                 , RULL(0x00000854), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCRSIM0_FSI1                                 , RULL(0x00000858), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCRSIM4_FSI1                                 , RULL(0x0000085C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCRSIS0_FSI1                                 , RULL(0x00000860), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SCRSIS4_FSI1                                 , RULL(0x00000864), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SDATA_FSI1                                   , RULL(0x00000830), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SDMA_FSI1                                    , RULL(0x00000804), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SI1M_FSI1                                    , RULL(0x00000818), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SI1S_FSI1                                    , RULL(0x0000081C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SI2M_FSI1                                    , RULL(0x00000824), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SI2S_FSI1                                    , RULL(0x00000828), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SIC_FSI1                                     , RULL(0x00000820), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SISC_FSI1                                    , RULL(0x00000808), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SISM_FSI1                                    , RULL(0x0000080C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SISS_FSI1                                    , RULL(0x00000810), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SLASTD_SRES_FSI1                             , RULL(0x00000834), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SLBUS_FSI1                                   , RULL(0x00000830), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SMBL_FSI1                                    , RULL(0x00000838), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SMBR_FSI1                                    , RULL(0x00000844), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SMODE_FSI1                                   , RULL(0x00000800), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SNML_FSI1                                    , RULL(0x00000840), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SNMR_FSI1                                    , RULL(0x0000084C), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SOML_FSI1                                    , RULL(0x0000083C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SOMR_FSI1                                    , RULL(0x00000848), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SRSIC0_FSI1                                  , RULL(0x00000868), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SRSIC4_FSI1                                  , RULL(0x0000086C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SRSIM0_FSI1                                  , RULL(0x00000870), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SRSIM4_FSI1                                  , RULL(0x00000874), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SRSIS0_FSI1                                  , RULL(0x00000878), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SRSIS4_FSI1                                  , RULL(0x0000087C), SH_UNT_PERV     , SH_ACS_FSI1      );
+
+REG32( PERV_FSI_B_SSI1M_FSI1                                   , RULL(0x0000081C), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SSI2M_FSI1                                   , RULL(0x00000828), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SSISM_FSI1                                   , RULL(0x00000810), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SSMBL_FSI1                                   , RULL(0x0000083C), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SSMBR_FSI1                                   , RULL(0x00000848), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_FSI_B_SSTAT_FSI1                                   , RULL(0x00000814), SH_UNT_PERV     ,
+       SH_ACS_FSI1      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG32( PERV_GPWRP_FSI                                          , RULL(0x0000281F), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_GPWRP_FSI_BYTE                                     , RULL(0x0000287C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_GPWRP_SCOM                                         , RULL(0x0005001F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_GPWRP                                          , RULL(0x0005001F), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_GXSTOP0_MASK_REG                                   , RULL(0x00040014), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_GXSTOP0_MASK_REG                                , RULL(0x01040014), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_GXSTOP0_MASK_REG                                , RULL(0x02040014), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_GXSTOP0_MASK_REG                                , RULL(0x03040014), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_GXSTOP0_MASK_REG                                , RULL(0x04040014), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_GXSTOP0_MASK_REG                                , RULL(0x05040014), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_GXSTOP0_MASK_REG                                , RULL(0x06040014), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_GXSTOP0_MASK_REG                              , RULL(0x07040014), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_GXSTOP0_MASK_REG                              , RULL(0x08040014), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_GXSTOP0_MASK_REG                               , RULL(0x09040014), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_GXSTOP0_MASK_REG                               , RULL(0x0C040014), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_GXSTOP0_MASK_REG                              , RULL(0x0D040014), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_GXSTOP0_MASK_REG                              , RULL(0x0E040014), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_GXSTOP0_MASK_REG                              , RULL(0x0F040014), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_GXSTOP0_MASK_REG                              , RULL(0x10040014), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_GXSTOP0_MASK_REG                              , RULL(0x11040014), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_GXSTOP0_MASK_REG                              , RULL(0x12040014), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_GXSTOP0_MASK_REG                              , RULL(0x13040014), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_GXSTOP0_MASK_REG                              , RULL(0x14040014), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_GXSTOP0_MASK_REG                              , RULL(0x15040014), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_GXSTOP0_MASK_REG                              , RULL(0x20040014), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_GXSTOP0_MASK_REG                              , RULL(0x21040014), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_GXSTOP0_MASK_REG                              , RULL(0x22040014), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_GXSTOP0_MASK_REG                              , RULL(0x23040014), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_GXSTOP0_MASK_REG                              , RULL(0x24040014), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_GXSTOP0_MASK_REG                              , RULL(0x25040014), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_GXSTOP0_MASK_REG                              , RULL(0x26040014), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_GXSTOP0_MASK_REG                              , RULL(0x27040014), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_GXSTOP0_MASK_REG                              , RULL(0x28040014), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_GXSTOP0_MASK_REG                              , RULL(0x29040014), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_GXSTOP0_MASK_REG                              , RULL(0x2A040014), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_GXSTOP0_MASK_REG                              , RULL(0x2B040014), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_GXSTOP0_MASK_REG                              , RULL(0x2C040014), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_GXSTOP0_MASK_REG                              , RULL(0x2D040014), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_GXSTOP0_MASK_REG                              , RULL(0x2E040014), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_GXSTOP0_MASK_REG                              , RULL(0x2F040014), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_GXSTOP0_MASK_REG                              , RULL(0x30040014), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_GXSTOP0_MASK_REG                              , RULL(0x31040014), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_GXSTOP0_MASK_REG                              , RULL(0x32040014), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_GXSTOP0_MASK_REG                              , RULL(0x33040014), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_GXSTOP0_MASK_REG                              , RULL(0x34040014), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_GXSTOP0_MASK_REG                              , RULL(0x35040014), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_GXSTOP0_MASK_REG                              , RULL(0x36040014), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_GXSTOP0_MASK_REG                              , RULL(0x37040014), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_GXSTOP1_MASK_REG                                   , RULL(0x00040015), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_GXSTOP1_MASK_REG                                , RULL(0x01040015), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_GXSTOP1_MASK_REG                                , RULL(0x02040015), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_GXSTOP1_MASK_REG                                , RULL(0x03040015), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_GXSTOP1_MASK_REG                                , RULL(0x04040015), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_GXSTOP1_MASK_REG                                , RULL(0x05040015), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_GXSTOP1_MASK_REG                                , RULL(0x06040015), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_GXSTOP1_MASK_REG                              , RULL(0x07040015), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_GXSTOP1_MASK_REG                              , RULL(0x08040015), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_GXSTOP1_MASK_REG                               , RULL(0x09040015), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_GXSTOP1_MASK_REG                               , RULL(0x0C040015), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_GXSTOP1_MASK_REG                              , RULL(0x0D040015), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_GXSTOP1_MASK_REG                              , RULL(0x0E040015), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_GXSTOP1_MASK_REG                              , RULL(0x0F040015), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_GXSTOP1_MASK_REG                              , RULL(0x10040015), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_GXSTOP1_MASK_REG                              , RULL(0x11040015), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_GXSTOP1_MASK_REG                              , RULL(0x12040015), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_GXSTOP1_MASK_REG                              , RULL(0x13040015), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_GXSTOP1_MASK_REG                              , RULL(0x14040015), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_GXSTOP1_MASK_REG                              , RULL(0x15040015), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_GXSTOP1_MASK_REG                              , RULL(0x20040015), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_GXSTOP1_MASK_REG                              , RULL(0x21040015), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_GXSTOP1_MASK_REG                              , RULL(0x22040015), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_GXSTOP1_MASK_REG                              , RULL(0x23040015), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_GXSTOP1_MASK_REG                              , RULL(0x24040015), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_GXSTOP1_MASK_REG                              , RULL(0x25040015), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_GXSTOP1_MASK_REG                              , RULL(0x26040015), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_GXSTOP1_MASK_REG                              , RULL(0x27040015), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_GXSTOP1_MASK_REG                              , RULL(0x28040015), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_GXSTOP1_MASK_REG                              , RULL(0x29040015), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_GXSTOP1_MASK_REG                              , RULL(0x2A040015), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_GXSTOP1_MASK_REG                              , RULL(0x2B040015), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_GXSTOP1_MASK_REG                              , RULL(0x2C040015), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_GXSTOP1_MASK_REG                              , RULL(0x2D040015), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_GXSTOP1_MASK_REG                              , RULL(0x2E040015), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_GXSTOP1_MASK_REG                              , RULL(0x2F040015), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_GXSTOP1_MASK_REG                              , RULL(0x30040015), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_GXSTOP1_MASK_REG                              , RULL(0x31040015), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_GXSTOP1_MASK_REG                              , RULL(0x32040015), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_GXSTOP1_MASK_REG                              , RULL(0x33040015), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_GXSTOP1_MASK_REG                              , RULL(0x34040015), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_GXSTOP1_MASK_REG                              , RULL(0x35040015), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_GXSTOP1_MASK_REG                              , RULL(0x36040015), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_GXSTOP1_MASK_REG                              , RULL(0x37040015), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_GXSTOP2_MASK_REG                                   , RULL(0x00040016), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_GXSTOP2_MASK_REG                                , RULL(0x01040016), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_GXSTOP2_MASK_REG                                , RULL(0x02040016), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_GXSTOP2_MASK_REG                                , RULL(0x03040016), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_GXSTOP2_MASK_REG                                , RULL(0x04040016), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_GXSTOP2_MASK_REG                                , RULL(0x05040016), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_GXSTOP2_MASK_REG                                , RULL(0x06040016), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_GXSTOP2_MASK_REG                              , RULL(0x07040016), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_GXSTOP2_MASK_REG                              , RULL(0x08040016), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_GXSTOP2_MASK_REG                               , RULL(0x09040016), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_GXSTOP2_MASK_REG                               , RULL(0x0C040016), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_GXSTOP2_MASK_REG                              , RULL(0x0D040016), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_GXSTOP2_MASK_REG                              , RULL(0x0E040016), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_GXSTOP2_MASK_REG                              , RULL(0x0F040016), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_GXSTOP2_MASK_REG                              , RULL(0x10040016), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_GXSTOP2_MASK_REG                              , RULL(0x11040016), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_GXSTOP2_MASK_REG                              , RULL(0x12040016), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_GXSTOP2_MASK_REG                              , RULL(0x13040016), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_GXSTOP2_MASK_REG                              , RULL(0x14040016), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_GXSTOP2_MASK_REG                              , RULL(0x15040016), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_GXSTOP2_MASK_REG                              , RULL(0x20040016), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_GXSTOP2_MASK_REG                              , RULL(0x21040016), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_GXSTOP2_MASK_REG                              , RULL(0x22040016), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_GXSTOP2_MASK_REG                              , RULL(0x23040016), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_GXSTOP2_MASK_REG                              , RULL(0x24040016), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_GXSTOP2_MASK_REG                              , RULL(0x25040016), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_GXSTOP2_MASK_REG                              , RULL(0x26040016), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_GXSTOP2_MASK_REG                              , RULL(0x27040016), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_GXSTOP2_MASK_REG                              , RULL(0x28040016), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_GXSTOP2_MASK_REG                              , RULL(0x29040016), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_GXSTOP2_MASK_REG                              , RULL(0x2A040016), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_GXSTOP2_MASK_REG                              , RULL(0x2B040016), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_GXSTOP2_MASK_REG                              , RULL(0x2C040016), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_GXSTOP2_MASK_REG                              , RULL(0x2D040016), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_GXSTOP2_MASK_REG                              , RULL(0x2E040016), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_GXSTOP2_MASK_REG                              , RULL(0x2F040016), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_GXSTOP2_MASK_REG                              , RULL(0x30040016), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_GXSTOP2_MASK_REG                              , RULL(0x31040016), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_GXSTOP2_MASK_REG                              , RULL(0x32040016), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_GXSTOP2_MASK_REG                              , RULL(0x33040016), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_GXSTOP2_MASK_REG                              , RULL(0x34040016), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_GXSTOP2_MASK_REG                              , RULL(0x35040016), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_GXSTOP2_MASK_REG                              , RULL(0x36040016), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_GXSTOP2_MASK_REG                              , RULL(0x37040016), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_GXSTOP_TRIG_REG                                    , RULL(0x00040013), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_GXSTOP_TRIG_REG                                 , RULL(0x01040013), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_GXSTOP_TRIG_REG                                 , RULL(0x02040013), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_GXSTOP_TRIG_REG                                 , RULL(0x03040013), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_GXSTOP_TRIG_REG                                 , RULL(0x04040013), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_GXSTOP_TRIG_REG                                 , RULL(0x05040013), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_GXSTOP_TRIG_REG                                 , RULL(0x06040013), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_GXSTOP_TRIG_REG                               , RULL(0x07040013), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_GXSTOP_TRIG_REG                               , RULL(0x08040013), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_GXSTOP_TRIG_REG                                , RULL(0x09040013), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_GXSTOP_TRIG_REG                                , RULL(0x0C040013), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_GXSTOP_TRIG_REG                               , RULL(0x0D040013), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_GXSTOP_TRIG_REG                               , RULL(0x0E040013), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_GXSTOP_TRIG_REG                               , RULL(0x0F040013), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_GXSTOP_TRIG_REG                               , RULL(0x10040013), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_GXSTOP_TRIG_REG                               , RULL(0x11040013), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_GXSTOP_TRIG_REG                               , RULL(0x12040013), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_GXSTOP_TRIG_REG                               , RULL(0x13040013), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_GXSTOP_TRIG_REG                               , RULL(0x14040013), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_GXSTOP_TRIG_REG                               , RULL(0x15040013), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_GXSTOP_TRIG_REG                               , RULL(0x20040013), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_GXSTOP_TRIG_REG                               , RULL(0x21040013), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_GXSTOP_TRIG_REG                               , RULL(0x22040013), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_GXSTOP_TRIG_REG                               , RULL(0x23040013), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_GXSTOP_TRIG_REG                               , RULL(0x24040013), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_GXSTOP_TRIG_REG                               , RULL(0x25040013), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_GXSTOP_TRIG_REG                               , RULL(0x26040013), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_GXSTOP_TRIG_REG                               , RULL(0x27040013), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_GXSTOP_TRIG_REG                               , RULL(0x28040013), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_GXSTOP_TRIG_REG                               , RULL(0x29040013), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_GXSTOP_TRIG_REG                               , RULL(0x2A040013), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_GXSTOP_TRIG_REG                               , RULL(0x2B040013), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_GXSTOP_TRIG_REG                               , RULL(0x2C040013), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_GXSTOP_TRIG_REG                               , RULL(0x2D040013), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_GXSTOP_TRIG_REG                               , RULL(0x2E040013), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_GXSTOP_TRIG_REG                               , RULL(0x2F040013), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_GXSTOP_TRIG_REG                               , RULL(0x30040013), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_GXSTOP_TRIG_REG                               , RULL(0x31040013), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_GXSTOP_TRIG_REG                               , RULL(0x32040013), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_GXSTOP_TRIG_REG                               , RULL(0x33040013), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_GXSTOP_TRIG_REG                               , RULL(0x34040013), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_GXSTOP_TRIG_REG                               , RULL(0x35040013), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_GXSTOP_TRIG_REG                               , RULL(0x36040013), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_GXSTOP_TRIG_REG                               , RULL(0x37040013), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_HANG_PULSE_0_REG                                   , RULL(0x000F0020), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_HANG_PULSE_0_REG                                , RULL(0x010F0020), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_HANG_PULSE_0_REG                                , RULL(0x020F0020), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_HANG_PULSE_0_REG                                , RULL(0x030F0020), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_HANG_PULSE_0_REG                                , RULL(0x040F0020), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_HANG_PULSE_0_REG                                , RULL(0x050F0020), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_HANG_PULSE_0_REG                                , RULL(0x060F0020), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_HANG_PULSE_0_REG                              , RULL(0x070F0020), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_HANG_PULSE_0_REG                              , RULL(0x080F0020), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_HANG_PULSE_0_REG                               , RULL(0x090F0020), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_HANG_PULSE_0_REG                               , RULL(0x0C0F0020), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_HANG_PULSE_0_REG                              , RULL(0x0D0F0020), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_HANG_PULSE_0_REG                              , RULL(0x0E0F0020), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_HANG_PULSE_0_REG                              , RULL(0x0F0F0020), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_HANG_PULSE_0_REG                              , RULL(0x100F0020), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_HANG_PULSE_0_REG                              , RULL(0x110F0020), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_HANG_PULSE_0_REG                              , RULL(0x120F0020), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_HANG_PULSE_0_REG                              , RULL(0x130F0020), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_HANG_PULSE_0_REG                              , RULL(0x140F0020), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_HANG_PULSE_0_REG                              , RULL(0x150F0020), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_HANG_PULSE_0_REG                              , RULL(0x200F0020), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_HANG_PULSE_0_REG                              , RULL(0x210F0020), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_HANG_PULSE_0_REG                              , RULL(0x220F0020), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_HANG_PULSE_0_REG                              , RULL(0x230F0020), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_HANG_PULSE_0_REG                              , RULL(0x240F0020), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_HANG_PULSE_0_REG                              , RULL(0x250F0020), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_HANG_PULSE_0_REG                              , RULL(0x260F0020), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_HANG_PULSE_0_REG                              , RULL(0x270F0020), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_HANG_PULSE_0_REG                              , RULL(0x280F0020), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_HANG_PULSE_0_REG                              , RULL(0x290F0020), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_HANG_PULSE_0_REG                              , RULL(0x2A0F0020), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_HANG_PULSE_0_REG                              , RULL(0x2B0F0020), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_HANG_PULSE_0_REG                              , RULL(0x2C0F0020), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_HANG_PULSE_0_REG                              , RULL(0x2D0F0020), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_HANG_PULSE_0_REG                              , RULL(0x2E0F0020), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_HANG_PULSE_0_REG                              , RULL(0x2F0F0020), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_HANG_PULSE_0_REG                              , RULL(0x300F0020), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_HANG_PULSE_0_REG                              , RULL(0x310F0020), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_HANG_PULSE_0_REG                              , RULL(0x320F0020), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_HANG_PULSE_0_REG                              , RULL(0x330F0020), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_HANG_PULSE_0_REG                              , RULL(0x340F0020), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_HANG_PULSE_0_REG                              , RULL(0x350F0020), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_HANG_PULSE_0_REG                              , RULL(0x360F0020), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_HANG_PULSE_0_REG                              , RULL(0x370F0020), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_HANG_PULSE_1_REG                                   , RULL(0x000F0021), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_HANG_PULSE_1_REG                                , RULL(0x010F0021), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_HANG_PULSE_1_REG                                , RULL(0x020F0021), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_HANG_PULSE_1_REG                                , RULL(0x030F0021), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_HANG_PULSE_1_REG                                , RULL(0x040F0021), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_HANG_PULSE_1_REG                                , RULL(0x050F0021), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_HANG_PULSE_1_REG                                , RULL(0x060F0021), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_HANG_PULSE_1_REG                              , RULL(0x070F0021), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_HANG_PULSE_1_REG                              , RULL(0x080F0021), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_HANG_PULSE_1_REG                               , RULL(0x090F0021), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_HANG_PULSE_1_REG                               , RULL(0x0C0F0021), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_HANG_PULSE_1_REG                              , RULL(0x0D0F0021), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_HANG_PULSE_1_REG                              , RULL(0x0E0F0021), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_HANG_PULSE_1_REG                              , RULL(0x0F0F0021), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_HANG_PULSE_1_REG                              , RULL(0x100F0021), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_HANG_PULSE_1_REG                              , RULL(0x110F0021), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_HANG_PULSE_1_REG                              , RULL(0x120F0021), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_HANG_PULSE_1_REG                              , RULL(0x130F0021), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_HANG_PULSE_1_REG                              , RULL(0x140F0021), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_HANG_PULSE_1_REG                              , RULL(0x150F0021), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_HANG_PULSE_1_REG                              , RULL(0x200F0021), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_HANG_PULSE_1_REG                              , RULL(0x210F0021), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_HANG_PULSE_1_REG                              , RULL(0x220F0021), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_HANG_PULSE_1_REG                              , RULL(0x230F0021), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_HANG_PULSE_1_REG                              , RULL(0x240F0021), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_HANG_PULSE_1_REG                              , RULL(0x250F0021), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_HANG_PULSE_1_REG                              , RULL(0x260F0021), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_HANG_PULSE_1_REG                              , RULL(0x270F0021), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_HANG_PULSE_1_REG                              , RULL(0x280F0021), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_HANG_PULSE_1_REG                              , RULL(0x290F0021), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_HANG_PULSE_1_REG                              , RULL(0x2A0F0021), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_HANG_PULSE_1_REG                              , RULL(0x2B0F0021), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_HANG_PULSE_1_REG                              , RULL(0x2C0F0021), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_HANG_PULSE_1_REG                              , RULL(0x2D0F0021), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_HANG_PULSE_1_REG                              , RULL(0x2E0F0021), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_HANG_PULSE_1_REG                              , RULL(0x2F0F0021), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_HANG_PULSE_1_REG                              , RULL(0x300F0021), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_HANG_PULSE_1_REG                              , RULL(0x310F0021), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_HANG_PULSE_1_REG                              , RULL(0x320F0021), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_HANG_PULSE_1_REG                              , RULL(0x330F0021), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_HANG_PULSE_1_REG                              , RULL(0x340F0021), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_HANG_PULSE_1_REG                              , RULL(0x350F0021), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_HANG_PULSE_1_REG                              , RULL(0x360F0021), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_HANG_PULSE_1_REG                              , RULL(0x370F0021), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_HANG_PULSE_2_REG                                   , RULL(0x000F0022), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_HANG_PULSE_2_REG                                , RULL(0x010F0022), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_HANG_PULSE_2_REG                                , RULL(0x020F0022), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_HANG_PULSE_2_REG                                , RULL(0x030F0022), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_HANG_PULSE_2_REG                                , RULL(0x040F0022), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_HANG_PULSE_2_REG                                , RULL(0x050F0022), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_HANG_PULSE_2_REG                                , RULL(0x060F0022), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_HANG_PULSE_2_REG                              , RULL(0x070F0022), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_HANG_PULSE_2_REG                              , RULL(0x080F0022), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_HANG_PULSE_2_REG                               , RULL(0x090F0022), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_HANG_PULSE_2_REG                               , RULL(0x0C0F0022), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_HANG_PULSE_2_REG                              , RULL(0x0D0F0022), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_HANG_PULSE_2_REG                              , RULL(0x0E0F0022), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_HANG_PULSE_2_REG                              , RULL(0x0F0F0022), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_HANG_PULSE_2_REG                              , RULL(0x100F0022), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_HANG_PULSE_2_REG                              , RULL(0x110F0022), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_HANG_PULSE_2_REG                              , RULL(0x120F0022), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_HANG_PULSE_2_REG                              , RULL(0x130F0022), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_HANG_PULSE_2_REG                              , RULL(0x140F0022), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_HANG_PULSE_2_REG                              , RULL(0x150F0022), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_HANG_PULSE_2_REG                              , RULL(0x200F0022), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_HANG_PULSE_2_REG                              , RULL(0x210F0022), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_HANG_PULSE_2_REG                              , RULL(0x220F0022), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_HANG_PULSE_2_REG                              , RULL(0x230F0022), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_HANG_PULSE_2_REG                              , RULL(0x240F0022), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_HANG_PULSE_2_REG                              , RULL(0x250F0022), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_HANG_PULSE_2_REG                              , RULL(0x260F0022), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_HANG_PULSE_2_REG                              , RULL(0x270F0022), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_HANG_PULSE_2_REG                              , RULL(0x280F0022), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_HANG_PULSE_2_REG                              , RULL(0x290F0022), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_HANG_PULSE_2_REG                              , RULL(0x2A0F0022), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_HANG_PULSE_2_REG                              , RULL(0x2B0F0022), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_HANG_PULSE_2_REG                              , RULL(0x2C0F0022), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_HANG_PULSE_2_REG                              , RULL(0x2D0F0022), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_HANG_PULSE_2_REG                              , RULL(0x2E0F0022), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_HANG_PULSE_2_REG                              , RULL(0x2F0F0022), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_HANG_PULSE_2_REG                              , RULL(0x300F0022), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_HANG_PULSE_2_REG                              , RULL(0x310F0022), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_HANG_PULSE_2_REG                              , RULL(0x320F0022), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_HANG_PULSE_2_REG                              , RULL(0x330F0022), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_HANG_PULSE_2_REG                              , RULL(0x340F0022), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_HANG_PULSE_2_REG                              , RULL(0x350F0022), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_HANG_PULSE_2_REG                              , RULL(0x360F0022), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_HANG_PULSE_2_REG                              , RULL(0x370F0022), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_HANG_PULSE_3_REG                                   , RULL(0x000F0023), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_HANG_PULSE_3_REG                                , RULL(0x010F0023), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_HANG_PULSE_3_REG                                , RULL(0x020F0023), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_HANG_PULSE_3_REG                                , RULL(0x030F0023), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_HANG_PULSE_3_REG                                , RULL(0x040F0023), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_HANG_PULSE_3_REG                                , RULL(0x050F0023), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_HANG_PULSE_3_REG                                , RULL(0x060F0023), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_HANG_PULSE_3_REG                              , RULL(0x070F0023), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_HANG_PULSE_3_REG                              , RULL(0x080F0023), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_HANG_PULSE_3_REG                               , RULL(0x090F0023), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_HANG_PULSE_3_REG                               , RULL(0x0C0F0023), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_HANG_PULSE_3_REG                              , RULL(0x0D0F0023), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_HANG_PULSE_3_REG                              , RULL(0x0E0F0023), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_HANG_PULSE_3_REG                              , RULL(0x0F0F0023), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_HANG_PULSE_3_REG                              , RULL(0x100F0023), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_HANG_PULSE_3_REG                              , RULL(0x110F0023), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_HANG_PULSE_3_REG                              , RULL(0x120F0023), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_HANG_PULSE_3_REG                              , RULL(0x130F0023), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_HANG_PULSE_3_REG                              , RULL(0x140F0023), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_HANG_PULSE_3_REG                              , RULL(0x150F0023), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_HANG_PULSE_3_REG                              , RULL(0x200F0023), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_HANG_PULSE_3_REG                              , RULL(0x210F0023), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_HANG_PULSE_3_REG                              , RULL(0x220F0023), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_HANG_PULSE_3_REG                              , RULL(0x230F0023), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_HANG_PULSE_3_REG                              , RULL(0x240F0023), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_HANG_PULSE_3_REG                              , RULL(0x250F0023), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_HANG_PULSE_3_REG                              , RULL(0x260F0023), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_HANG_PULSE_3_REG                              , RULL(0x270F0023), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_HANG_PULSE_3_REG                              , RULL(0x280F0023), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_HANG_PULSE_3_REG                              , RULL(0x290F0023), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_HANG_PULSE_3_REG                              , RULL(0x2A0F0023), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_HANG_PULSE_3_REG                              , RULL(0x2B0F0023), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_HANG_PULSE_3_REG                              , RULL(0x2C0F0023), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_HANG_PULSE_3_REG                              , RULL(0x2D0F0023), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_HANG_PULSE_3_REG                              , RULL(0x2E0F0023), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_HANG_PULSE_3_REG                              , RULL(0x2F0F0023), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_HANG_PULSE_3_REG                              , RULL(0x300F0023), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_HANG_PULSE_3_REG                              , RULL(0x310F0023), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_HANG_PULSE_3_REG                              , RULL(0x320F0023), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_HANG_PULSE_3_REG                              , RULL(0x330F0023), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_HANG_PULSE_3_REG                              , RULL(0x340F0023), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_HANG_PULSE_3_REG                              , RULL(0x350F0023), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_HANG_PULSE_3_REG                              , RULL(0x360F0023), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_HANG_PULSE_3_REG                              , RULL(0x370F0023), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_HANG_PULSE_4_REG                                   , RULL(0x000F0024), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_HANG_PULSE_4_REG                                , RULL(0x010F0024), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_HANG_PULSE_4_REG                                , RULL(0x020F0024), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_HANG_PULSE_4_REG                                , RULL(0x030F0024), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_HANG_PULSE_4_REG                                , RULL(0x040F0024), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_HANG_PULSE_4_REG                                , RULL(0x050F0024), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_HANG_PULSE_4_REG                                , RULL(0x060F0024), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_HANG_PULSE_4_REG                              , RULL(0x070F0024), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_HANG_PULSE_4_REG                              , RULL(0x080F0024), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_HANG_PULSE_4_REG                               , RULL(0x090F0024), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_HANG_PULSE_4_REG                               , RULL(0x0C0F0024), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_HANG_PULSE_4_REG                              , RULL(0x0D0F0024), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_HANG_PULSE_4_REG                              , RULL(0x0E0F0024), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_HANG_PULSE_4_REG                              , RULL(0x0F0F0024), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_HANG_PULSE_4_REG                              , RULL(0x100F0024), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_HANG_PULSE_4_REG                              , RULL(0x110F0024), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_HANG_PULSE_4_REG                              , RULL(0x120F0024), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_HANG_PULSE_4_REG                              , RULL(0x130F0024), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_HANG_PULSE_4_REG                              , RULL(0x140F0024), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_HANG_PULSE_4_REG                              , RULL(0x150F0024), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_HANG_PULSE_4_REG                              , RULL(0x200F0024), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_HANG_PULSE_4_REG                              , RULL(0x210F0024), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_HANG_PULSE_4_REG                              , RULL(0x220F0024), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_HANG_PULSE_4_REG                              , RULL(0x230F0024), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_HANG_PULSE_4_REG                              , RULL(0x240F0024), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_HANG_PULSE_4_REG                              , RULL(0x250F0024), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_HANG_PULSE_4_REG                              , RULL(0x260F0024), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_HANG_PULSE_4_REG                              , RULL(0x270F0024), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_HANG_PULSE_4_REG                              , RULL(0x280F0024), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_HANG_PULSE_4_REG                              , RULL(0x290F0024), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_HANG_PULSE_4_REG                              , RULL(0x2A0F0024), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_HANG_PULSE_4_REG                              , RULL(0x2B0F0024), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_HANG_PULSE_4_REG                              , RULL(0x2C0F0024), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_HANG_PULSE_4_REG                              , RULL(0x2D0F0024), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_HANG_PULSE_4_REG                              , RULL(0x2E0F0024), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_HANG_PULSE_4_REG                              , RULL(0x2F0F0024), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_HANG_PULSE_4_REG                              , RULL(0x300F0024), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_HANG_PULSE_4_REG                              , RULL(0x310F0024), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_HANG_PULSE_4_REG                              , RULL(0x320F0024), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_HANG_PULSE_4_REG                              , RULL(0x330F0024), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_HANG_PULSE_4_REG                              , RULL(0x340F0024), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_HANG_PULSE_4_REG                              , RULL(0x350F0024), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_HANG_PULSE_4_REG                              , RULL(0x360F0024), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_HANG_PULSE_4_REG                              , RULL(0x370F0024), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_HANG_PULSE_5_REG                                   , RULL(0x000F0025), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_HANG_PULSE_5_REG                                , RULL(0x010F0025), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_HANG_PULSE_5_REG                                , RULL(0x020F0025), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_HANG_PULSE_5_REG                                , RULL(0x030F0025), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_HANG_PULSE_5_REG                                , RULL(0x040F0025), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_HANG_PULSE_5_REG                                , RULL(0x050F0025), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_HANG_PULSE_5_REG                                , RULL(0x060F0025), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_HANG_PULSE_5_REG                              , RULL(0x070F0025), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_HANG_PULSE_5_REG                              , RULL(0x080F0025), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_HANG_PULSE_5_REG                               , RULL(0x090F0025), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_HANG_PULSE_5_REG                               , RULL(0x0C0F0025), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_HANG_PULSE_5_REG                              , RULL(0x0D0F0025), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_HANG_PULSE_5_REG                              , RULL(0x0E0F0025), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_HANG_PULSE_5_REG                              , RULL(0x0F0F0025), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_HANG_PULSE_5_REG                              , RULL(0x100F0025), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_HANG_PULSE_5_REG                              , RULL(0x110F0025), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_HANG_PULSE_5_REG                              , RULL(0x120F0025), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_HANG_PULSE_5_REG                              , RULL(0x130F0025), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_HANG_PULSE_5_REG                              , RULL(0x140F0025), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_HANG_PULSE_5_REG                              , RULL(0x150F0025), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_HANG_PULSE_5_REG                              , RULL(0x200F0025), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_HANG_PULSE_5_REG                              , RULL(0x210F0025), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_HANG_PULSE_5_REG                              , RULL(0x220F0025), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_HANG_PULSE_5_REG                              , RULL(0x230F0025), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_HANG_PULSE_5_REG                              , RULL(0x240F0025), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_HANG_PULSE_5_REG                              , RULL(0x250F0025), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_HANG_PULSE_5_REG                              , RULL(0x260F0025), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_HANG_PULSE_5_REG                              , RULL(0x270F0025), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_HANG_PULSE_5_REG                              , RULL(0x280F0025), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_HANG_PULSE_5_REG                              , RULL(0x290F0025), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_HANG_PULSE_5_REG                              , RULL(0x2A0F0025), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_HANG_PULSE_5_REG                              , RULL(0x2B0F0025), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_HANG_PULSE_5_REG                              , RULL(0x2C0F0025), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_HANG_PULSE_5_REG                              , RULL(0x2D0F0025), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_HANG_PULSE_5_REG                              , RULL(0x2E0F0025), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_HANG_PULSE_5_REG                              , RULL(0x2F0F0025), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_HANG_PULSE_5_REG                              , RULL(0x300F0025), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_HANG_PULSE_5_REG                              , RULL(0x310F0025), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_HANG_PULSE_5_REG                              , RULL(0x320F0025), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_HANG_PULSE_5_REG                              , RULL(0x330F0025), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_HANG_PULSE_5_REG                              , RULL(0x340F0025), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_HANG_PULSE_5_REG                              , RULL(0x350F0025), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_HANG_PULSE_5_REG                              , RULL(0x360F0025), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_HANG_PULSE_5_REG                              , RULL(0x370F0025), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_HANG_PULSE_6_REG                                   , RULL(0x000F0026), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_HANG_PULSE_6_REG                                , RULL(0x010F0026), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_HANG_PULSE_6_REG                                , RULL(0x020F0026), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_HANG_PULSE_6_REG                                , RULL(0x030F0026), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_HANG_PULSE_6_REG                                , RULL(0x040F0026), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_HANG_PULSE_6_REG                                , RULL(0x050F0026), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_HANG_PULSE_6_REG                                , RULL(0x060F0026), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_HANG_PULSE_6_REG                              , RULL(0x070F0026), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_HANG_PULSE_6_REG                              , RULL(0x080F0026), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_HANG_PULSE_6_REG                               , RULL(0x090F0026), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_HANG_PULSE_6_REG                               , RULL(0x0C0F0026), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_HANG_PULSE_6_REG                              , RULL(0x0D0F0026), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_HANG_PULSE_6_REG                              , RULL(0x0E0F0026), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_HANG_PULSE_6_REG                              , RULL(0x0F0F0026), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_HANG_PULSE_6_REG                              , RULL(0x100F0026), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_HANG_PULSE_6_REG                              , RULL(0x110F0026), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_HANG_PULSE_6_REG                              , RULL(0x120F0026), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_HANG_PULSE_6_REG                              , RULL(0x130F0026), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_HANG_PULSE_6_REG                              , RULL(0x140F0026), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_HANG_PULSE_6_REG                              , RULL(0x150F0026), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_HANG_PULSE_6_REG                              , RULL(0x200F0026), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_HANG_PULSE_6_REG                              , RULL(0x210F0026), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_HANG_PULSE_6_REG                              , RULL(0x220F0026), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_HANG_PULSE_6_REG                              , RULL(0x230F0026), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_HANG_PULSE_6_REG                              , RULL(0x240F0026), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_HANG_PULSE_6_REG                              , RULL(0x250F0026), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_HANG_PULSE_6_REG                              , RULL(0x260F0026), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_HANG_PULSE_6_REG                              , RULL(0x270F0026), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_HANG_PULSE_6_REG                              , RULL(0x280F0026), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_HANG_PULSE_6_REG                              , RULL(0x290F0026), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_HANG_PULSE_6_REG                              , RULL(0x2A0F0026), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_HANG_PULSE_6_REG                              , RULL(0x2B0F0026), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_HANG_PULSE_6_REG                              , RULL(0x2C0F0026), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_HANG_PULSE_6_REG                              , RULL(0x2D0F0026), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_HANG_PULSE_6_REG                              , RULL(0x2E0F0026), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_HANG_PULSE_6_REG                              , RULL(0x2F0F0026), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_HANG_PULSE_6_REG                              , RULL(0x300F0026), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_HANG_PULSE_6_REG                              , RULL(0x310F0026), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_HANG_PULSE_6_REG                              , RULL(0x320F0026), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_HANG_PULSE_6_REG                              , RULL(0x330F0026), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_HANG_PULSE_6_REG                              , RULL(0x340F0026), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_HANG_PULSE_6_REG                              , RULL(0x350F0026), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_HANG_PULSE_6_REG                              , RULL(0x360F0026), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_HANG_PULSE_6_REG                              , RULL(0x370F0026), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_HEARTBEAT_REG                                      , RULL(0x000F0018), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_TP_HEARTBEAT_REG                                   , RULL(0x010F0018), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_HEARTBEAT_REG                                   , RULL(0x020F0018), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_HEARTBEAT_REG                                   , RULL(0x030F0018), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_HEARTBEAT_REG                                   , RULL(0x040F0018), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_HEARTBEAT_REG                                   , RULL(0x050F0018), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_HEARTBEAT_REG                                   , RULL(0x060F0018), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_HEARTBEAT_REG                                 , RULL(0x070F0018), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_HEARTBEAT_REG                                 , RULL(0x080F0018), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_HEARTBEAT_REG                                  , RULL(0x090F0018), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_HEARTBEAT_REG                                  , RULL(0x0C0F0018), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_HEARTBEAT_REG                                 , RULL(0x0D0F0018), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_HEARTBEAT_REG                                 , RULL(0x0E0F0018), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_HEARTBEAT_REG                                 , RULL(0x0F0F0018), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_HEARTBEAT_REG                                 , RULL(0x100F0018), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_HEARTBEAT_REG                                 , RULL(0x110F0018), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_HEARTBEAT_REG                                 , RULL(0x120F0018), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_HEARTBEAT_REG                                 , RULL(0x130F0018), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_HEARTBEAT_REG                                 , RULL(0x140F0018), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_HEARTBEAT_REG                                 , RULL(0x150F0018), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_HEARTBEAT_REG                                 , RULL(0x200F0018), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_HEARTBEAT_REG                                 , RULL(0x210F0018), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_HEARTBEAT_REG                                 , RULL(0x220F0018), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_HEARTBEAT_REG                                 , RULL(0x230F0018), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_HEARTBEAT_REG                                 , RULL(0x240F0018), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_HEARTBEAT_REG                                 , RULL(0x250F0018), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_HEARTBEAT_REG                                 , RULL(0x260F0018), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_HEARTBEAT_REG                                 , RULL(0x270F0018), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_HEARTBEAT_REG                                 , RULL(0x280F0018), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_HEARTBEAT_REG                                 , RULL(0x290F0018), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_HEARTBEAT_REG                                 , RULL(0x2A0F0018), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_HEARTBEAT_REG                                 , RULL(0x2B0F0018), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_HEARTBEAT_REG                                 , RULL(0x2C0F0018), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_HEARTBEAT_REG                                 , RULL(0x2D0F0018), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_HEARTBEAT_REG                                 , RULL(0x2E0F0018), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_HEARTBEAT_REG                                 , RULL(0x2F0F0018), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_HEARTBEAT_REG                                 , RULL(0x300F0018), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_HEARTBEAT_REG                                 , RULL(0x310F0018), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_HEARTBEAT_REG                                 , RULL(0x320F0018), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_HEARTBEAT_REG                                 , RULL(0x330F0018), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_HEARTBEAT_REG                                 , RULL(0x340F0018), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_HEARTBEAT_REG                                 , RULL(0x350F0018), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_HEARTBEAT_REG                                 , RULL(0x360F0018), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_HEARTBEAT_REG                                 , RULL(0x370F0018), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_HOSTATTN                                           , RULL(0x00040009), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_HOSTATTN                                        , RULL(0x01040009), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_HOSTATTN                                        , RULL(0x02040009), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_HOSTATTN                                        , RULL(0x03040009), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_HOSTATTN                                        , RULL(0x04040009), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_HOSTATTN                                        , RULL(0x05040009), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_HOSTATTN                                        , RULL(0x06040009), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_HOSTATTN                                      , RULL(0x07040009), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_HOSTATTN                                      , RULL(0x08040009), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_HOSTATTN                                       , RULL(0x09040009), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_HOSTATTN                                       , RULL(0x0C040009), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_HOSTATTN                                      , RULL(0x0D040009), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_HOSTATTN                                      , RULL(0x0E040009), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_HOSTATTN                                      , RULL(0x0F040009), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_HOSTATTN                                      , RULL(0x10040009), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_HOSTATTN                                      , RULL(0x11040009), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_HOSTATTN                                      , RULL(0x12040009), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_HOSTATTN                                      , RULL(0x13040009), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_HOSTATTN                                      , RULL(0x14040009), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_HOSTATTN                                      , RULL(0x15040009), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_HOSTATTN                                      , RULL(0x20040009), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_HOSTATTN                                      , RULL(0x21040009), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_HOSTATTN                                      , RULL(0x22040009), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_HOSTATTN                                      , RULL(0x23040009), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_HOSTATTN                                      , RULL(0x24040009), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_HOSTATTN                                      , RULL(0x25040009), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_HOSTATTN                                      , RULL(0x26040009), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_HOSTATTN                                      , RULL(0x27040009), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_HOSTATTN                                      , RULL(0x28040009), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_HOSTATTN                                      , RULL(0x29040009), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_HOSTATTN                                      , RULL(0x2A040009), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_HOSTATTN                                      , RULL(0x2B040009), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_HOSTATTN                                      , RULL(0x2C040009), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_HOSTATTN                                      , RULL(0x2D040009), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_HOSTATTN                                      , RULL(0x2E040009), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_HOSTATTN                                      , RULL(0x2F040009), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_HOSTATTN                                      , RULL(0x30040009), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_HOSTATTN                                      , RULL(0x31040009), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_HOSTATTN                                      , RULL(0x32040009), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_HOSTATTN                                      , RULL(0x33040009), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_HOSTATTN                                      , RULL(0x34040009), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_HOSTATTN                                      , RULL(0x35040009), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_HOSTATTN                                      , RULL(0x36040009), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_HOSTATTN                                      , RULL(0x37040009), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_HOSTATTN_MASK                                      , RULL(0x0004001A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_HOSTATTN_MASK                                   , RULL(0x0104001A), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_HOSTATTN_MASK                                   , RULL(0x0204001A), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_HOSTATTN_MASK                                   , RULL(0x0304001A), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_HOSTATTN_MASK                                   , RULL(0x0404001A), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_HOSTATTN_MASK                                   , RULL(0x0504001A), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_HOSTATTN_MASK                                   , RULL(0x0604001A), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_HOSTATTN_MASK                                 , RULL(0x0704001A), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_HOSTATTN_MASK                                 , RULL(0x0804001A), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_HOSTATTN_MASK                                  , RULL(0x0904001A), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_HOSTATTN_MASK                                  , RULL(0x0C04001A), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_HOSTATTN_MASK                                 , RULL(0x0D04001A), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_HOSTATTN_MASK                                 , RULL(0x0E04001A), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_HOSTATTN_MASK                                 , RULL(0x0F04001A), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_HOSTATTN_MASK                                 , RULL(0x1004001A), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_HOSTATTN_MASK                                 , RULL(0x1104001A), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_HOSTATTN_MASK                                 , RULL(0x1204001A), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_HOSTATTN_MASK                                 , RULL(0x1304001A), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_HOSTATTN_MASK                                 , RULL(0x1404001A), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_HOSTATTN_MASK                                 , RULL(0x1504001A), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_HOSTATTN_MASK                                 , RULL(0x2004001A), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_HOSTATTN_MASK                                 , RULL(0x2104001A), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_HOSTATTN_MASK                                 , RULL(0x2204001A), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_HOSTATTN_MASK                                 , RULL(0x2304001A), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_HOSTATTN_MASK                                 , RULL(0x2404001A), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_HOSTATTN_MASK                                 , RULL(0x2504001A), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_HOSTATTN_MASK                                 , RULL(0x2604001A), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_HOSTATTN_MASK                                 , RULL(0x2704001A), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_HOSTATTN_MASK                                 , RULL(0x2804001A), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_HOSTATTN_MASK                                 , RULL(0x2904001A), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_HOSTATTN_MASK                                 , RULL(0x2A04001A), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_HOSTATTN_MASK                                 , RULL(0x2B04001A), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_HOSTATTN_MASK                                 , RULL(0x2C04001A), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_HOSTATTN_MASK                                 , RULL(0x2D04001A), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_HOSTATTN_MASK                                 , RULL(0x2E04001A), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_HOSTATTN_MASK                                 , RULL(0x2F04001A), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_HOSTATTN_MASK                                 , RULL(0x3004001A), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_HOSTATTN_MASK                                 , RULL(0x3104001A), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_HOSTATTN_MASK                                 , RULL(0x3204001A), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_HOSTATTN_MASK                                 , RULL(0x3304001A), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_HOSTATTN_MASK                                 , RULL(0x3404001A), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_HOSTATTN_MASK                                 , RULL(0x3504001A), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_HOSTATTN_MASK                                 , RULL(0x3604001A), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_HOSTATTN_MASK                                 , RULL(0x3704001A), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_HOST_MASK_REG                                      , RULL(0x000F0033), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_HOST_MASK_REG                                  , RULL(0x000F0033), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_I2C_BUSY_REGISTER_A                       , RULL(0x0000180A), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      );
+REG32( PERV_FSII2C_I2C_BUSY_REGISTER_A                         , RULL(0x0000180A), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      );
+
+REG64( PERV_IGNORE_PAR_REG                                     , RULL(0x000F001C), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_IGNORE_PAR_REG                                 , RULL(0x000F001C), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_IMM_RESET_ERR_A                           , RULL(0x00001808), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSII2C_IMM_RESET_ERR_A                             , RULL(0x00001808), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PERV_0_FSII2C_IMM_RESET_I2C_A                           , RULL(0x00001807), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      );
+REG32( PERV_FSII2C_IMM_RESET_I2C_A                             , RULL(0x00001807), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_IMM_RESET_S_SCL_A                         , RULL(0x0000180B), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      );
+REG32( PERV_FSII2C_IMM_RESET_S_SCL_A                           , RULL(0x0000180B), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_IMM_RESET_S_SDA_A                         , RULL(0x0000180D), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      );
+REG32( PERV_FSII2C_IMM_RESET_S_SDA_A                           , RULL(0x0000180D), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_IMM_SET_S_SCL_A                           , RULL(0x00001809), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      );
+REG32( PERV_FSII2C_IMM_SET_S_SCL_A                             , RULL(0x00001809), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_IMM_SET_S_SDA_A                           , RULL(0x0000180C), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      );
+REG32( PERV_FSII2C_IMM_SET_S_SDA_A                             , RULL(0x0000180C), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      );
+
+REG64( PERV_INJECT_REG                                         , RULL(0x00050011), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_INJECT_REG                                      , RULL(0x01050011), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_INJECT_REG                                      , RULL(0x02050011), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_INJECT_REG                                      , RULL(0x03050011), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_INJECT_REG                                      , RULL(0x04050011), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_INJECT_REG                                      , RULL(0x05050011), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_INJECT_REG                                      , RULL(0x06050011), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_INJECT_REG                                    , RULL(0x07050011), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_INJECT_REG                                    , RULL(0x08050011), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_INJECT_REG                                     , RULL(0x09050011), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_INJECT_REG                                     , RULL(0x0C050011), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_INJECT_REG                                    , RULL(0x0D050011), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_INJECT_REG                                    , RULL(0x0E050011), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_INJECT_REG                                    , RULL(0x0F050011), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_INJECT_REG                                    , RULL(0x10050011), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_INJECT_REG                                    , RULL(0x11050011), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_INJECT_REG                                    , RULL(0x12050011), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_INJECT_REG                                    , RULL(0x13050011), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_INJECT_REG                                    , RULL(0x14050011), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_INJECT_REG                                    , RULL(0x15050011), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_INJECT_REG                                    , RULL(0x20050011), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_INJECT_REG                                    , RULL(0x21050011), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_INJECT_REG                                    , RULL(0x22050011), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_INJECT_REG                                    , RULL(0x23050011), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_INJECT_REG                                    , RULL(0x24050011), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_INJECT_REG                                    , RULL(0x25050011), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_INJECT_REG                                    , RULL(0x26050011), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_INJECT_REG                                    , RULL(0x27050011), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_INJECT_REG                                    , RULL(0x28050011), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_INJECT_REG                                    , RULL(0x29050011), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_INJECT_REG                                    , RULL(0x2A050011), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_INJECT_REG                                    , RULL(0x2B050011), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_INJECT_REG                                    , RULL(0x2C050011), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_INJECT_REG                                    , RULL(0x2D050011), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_INJECT_REG                                    , RULL(0x2E050011), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_INJECT_REG                                    , RULL(0x2F050011), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_INJECT_REG                                    , RULL(0x30050011), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_INJECT_REG                                    , RULL(0x31050011), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_INJECT_REG                                    , RULL(0x32050011), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_INJECT_REG                                    , RULL(0x33050011), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_INJECT_REG                                    , RULL(0x34050011), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_INJECT_REG                                    , RULL(0x35050011), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_INJECT_REG                                    , RULL(0x36050011), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_INJECT_REG                                    , RULL(0x37050011), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG32( PERV_FSI2PIB_INTERRUPT_FSI                              , RULL(0x0000100B), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_INTERRUPT_FSI_BYTE                         , RULL(0x0000102C), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI_BYTE  );
+
+REG64( PERV_INTERRUPT1_REG                                     , RULL(0x000F0020), SH_UNT_PERV     ,
+       SH_ACS_SCOM_RW   ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_INTERRUPT1_REG_OR                                  , RULL(0x000F0021), SH_UNT_PERV     , SH_ACS_SCOM1_OR  );
+REG64( PERV_INTERRUPT1_REG_AND                                 , RULL(0x000F0022), SH_UNT_PERV     , SH_ACS_SCOM2_AND );
+REG64( PERV_PIB_INTERRUPT1_REG                                 , RULL(0x000F0020), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_INTERRUPT1_REG_OR                              , RULL(0x000F0021), SH_UNT_PERV_0   , SH_ACS_SCOM1_OR  );
+REG64( PERV_PIB_INTERRUPT1_REG_AND                             , RULL(0x000F0022), SH_UNT_PERV_0   , SH_ACS_SCOM2_AND );
+
+REG64( PERV_INTERRUPT2_REG                                     , RULL(0x000F0023), SH_UNT_PERV     ,
+       SH_ACS_SCOM_RW   ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_INTERRUPT2_REG_OR                                  , RULL(0x000F0024), SH_UNT_PERV     , SH_ACS_SCOM1_OR  );
+REG64( PERV_INTERRUPT2_REG_AND                                 , RULL(0x000F0025), SH_UNT_PERV     , SH_ACS_SCOM2_AND );
+REG64( PERV_PIB_INTERRUPT2_REG                                 , RULL(0x000F0023), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_INTERRUPT2_REG_OR                              , RULL(0x000F0024), SH_UNT_PERV_0   , SH_ACS_SCOM1_OR  );
+REG64( PERV_PIB_INTERRUPT2_REG_AND                             , RULL(0x000F0025), SH_UNT_PERV_0   , SH_ACS_SCOM2_AND );
+
+REG64( PERV_INTERRUPT3_REG                                     , RULL(0x000F0026), SH_UNT_PERV     ,
+       SH_ACS_SCOM_RW   ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_INTERRUPT3_REG_OR                                  , RULL(0x000F0027), SH_UNT_PERV     , SH_ACS_SCOM1_OR  );
+REG64( PERV_INTERRUPT3_REG_AND                                 , RULL(0x000F0028), SH_UNT_PERV     , SH_ACS_SCOM2_AND );
+REG64( PERV_PIB_INTERRUPT3_REG                                 , RULL(0x000F0026), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_INTERRUPT3_REG_OR                              , RULL(0x000F0027), SH_UNT_PERV_0   , SH_ACS_SCOM1_OR  );
+REG64( PERV_PIB_INTERRUPT3_REG_AND                             , RULL(0x000F0028), SH_UNT_PERV_0   , SH_ACS_SCOM2_AND );
+
+REG64( PERV_INTERRUPT4_REG                                     , RULL(0x000F0029), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_INTERRUPT4_REG_OR                                  , RULL(0x000F002A), SH_UNT_PERV     , SH_ACS_SCOM1_OR  );
+REG64( PERV_INTERRUPT4_REG_AND                                 , RULL(0x000F002B), SH_UNT_PERV     , SH_ACS_SCOM2_AND );
+REG64( PERV_PIB_INTERRUPT4_REG                                 , RULL(0x000F0029), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_INTERRUPT4_REG_OR                              , RULL(0x000F002A), SH_UNT_PERV_0   , SH_ACS_SCOM1_OR  );
+REG64( PERV_PIB_INTERRUPT4_REG_AND                             , RULL(0x000F002B), SH_UNT_PERV_0   , SH_ACS_SCOM2_AND );
+
+REG64( PERV_0_FSII2C_INTERRUPTS_A                              , RULL(0x00001806), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      );
+REG32( PERV_FSII2C_INTERRUPTS_A                                , RULL(0x00001806), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_INTERRUPT_COND_A                          , RULL(0x00001805), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      );
+REG32( PERV_FSII2C_INTERRUPT_COND_A                            , RULL(0x00001805), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      );
+
+REG64( PERV_INTERRUPT_CONF_REG                                 , RULL(0x000F002F), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_INTERRUPT_CONF_REG_WOR                             , RULL(0x000F0030), SH_UNT_PERV     , SH_ACS_SCOM1_WOR );
+REG64( PERV_INTERRUPT_CONF_REG_WAND                            , RULL(0x000F0031), SH_UNT_PERV     ,
+       SH_ACS_SCOM2_WAND );
+REG64( PERV_PIB_INTERRUPT_CONF_REG                             , RULL(0x000F002F), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_INTERRUPT_CONF_REG_WOR                         , RULL(0x000F0030), SH_UNT_PERV_0   , SH_ACS_SCOM1_WOR );
+REG64( PERV_PIB_INTERRUPT_CONF_REG_WAND                        , RULL(0x000F0031), SH_UNT_PERV_0   ,
+       SH_ACS_SCOM2_WAND );
+
+REG64( PERV_INTERRUPT_HOLD_REG                                 , RULL(0x000F0032), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_INTERRUPT_HOLD_REG                             , RULL(0x000F0032), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_A_WO              , RULL(0x00001804), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM_WO   );
+REG64( PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_A_OR              , RULL(0x00001805), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM1_OR  );
+REG64( PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_A_AND             , RULL(0x00001806), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM2_AND );
+REG32( PERV_FSII2C_INTERRUPT_MASK_REGISTER_A_WO                , RULL(0x00001804), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM_WO   );
+REG32( PERV_FSII2C_INTERRUPT_MASK_REGISTER_A_OR                , RULL(0x00001805), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM1_OR  );
+REG32( PERV_FSII2C_INTERRUPT_MASK_REGISTER_A_AND               , RULL(0x00001806), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM2_AND );
+
+REG64( PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_READ_A            , RULL(0x00001804), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      );
+REG32( PERV_FSII2C_INTERRUPT_MASK_REGISTER_READ_A              , RULL(0x00001804), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      );
+
+REG64( PERV_INTERRUPT_TYPE_MASK_REG                            , RULL(0x000F002C), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_INTERRUPT_TYPE_MASK_REG_WOR                        , RULL(0x000F002D), SH_UNT_PERV     , SH_ACS_SCOM1_WOR );
+REG64( PERV_INTERRUPT_TYPE_MASK_REG_WAND                       , RULL(0x000F002E), SH_UNT_PERV     ,
+       SH_ACS_SCOM2_WAND );
+REG64( PERV_PIB_INTERRUPT_TYPE_MASK_REG                        , RULL(0x000F002C), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_INTERRUPT_TYPE_MASK_REG_WOR                    , RULL(0x000F002D), SH_UNT_PERV_0   , SH_ACS_SCOM1_WOR );
+REG64( PERV_PIB_INTERRUPT_TYPE_MASK_REG_WAND                   , RULL(0x000F002E), SH_UNT_PERV_0   ,
+       SH_ACS_SCOM2_WAND );
+
+REG64( PERV_INTERRUPT_TYPE_REG                                 , RULL(0x000F001A), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_PIB_INTERRUPT_TYPE_REG                             , RULL(0x000F001A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_IODA_TCD_IODA                                      , RULL(0x00002800), SH_UNT_PERV     , SH_ACS_IODA      );
+
+REG64( PERV_IODA_TDR_IODA                                      , RULL(0x00002C00), SH_UNT_PERV     , SH_ACS_IODA      );
+
+REG64( PERV_IODA_TDR_MEM_IODA                                  , RULL(0x00003000), SH_UNT_PERV     , SH_ACS_IODA      );
+
+REG64( PERV_FSB_IODA_TVT_IODA                                  , RULL(0x00002400), SH_UNT_PERV_FSB , SH_ACS_IODA      );
+
+REG64( PERV_IODA_XLT_EA_IODA                                   , RULL(0x00004000), SH_UNT_PERV     , SH_ACS_IODA      );
+
+REG64( PERV_KVREF_AND_VMEAS_MODE_STATUS_REG                    , RULL(0x00020007), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_KVREF_AND_VMEAS_MODE_STATUS_REG                 , RULL(0x01020007), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_KVREF_TUNE_DATA                                    , RULL(0x00020005), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_KVREF_TUNE_DATA                                 , RULL(0x01020005), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_LOCAL_FIR                                          , RULL(0x0004000A), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_LOCAL_FIR                                       , RULL(0x0104000A), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_LOCAL_FIR_AND                                      , RULL(0x0004000B), SH_UNT_PERV     , SH_ACS_SCOM1_AND );
+REG64( PERV_TP_LOCAL_FIR_AND                                   , RULL(0x0104000B), SH_UNT_PERV_1   , SH_ACS_SCOM1_AND );
+REG64( PERV_LOCAL_FIR_OR                                       , RULL(0x0004000C), SH_UNT_PERV     , SH_ACS_SCOM2_OR  );
+REG64( PERV_TP_LOCAL_FIR_OR                                    , RULL(0x0104000C), SH_UNT_PERV_1   , SH_ACS_SCOM2_OR  );
+REG64( PERV_N0_LOCAL_FIR                                       , RULL(0x0204000A), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_LOCAL_FIR_AND                                   , RULL(0x0204000B), SH_UNT_PERV_2   , SH_ACS_SCOM1_AND );
+REG64( PERV_N0_LOCAL_FIR_OR                                    , RULL(0x0204000C), SH_UNT_PERV_2   , SH_ACS_SCOM2_OR  );
+REG64( PERV_N1_LOCAL_FIR                                       , RULL(0x0304000A), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_LOCAL_FIR_AND                                   , RULL(0x0304000B), SH_UNT_PERV_3   , SH_ACS_SCOM1_AND );
+REG64( PERV_N1_LOCAL_FIR_OR                                    , RULL(0x0304000C), SH_UNT_PERV_3   , SH_ACS_SCOM2_OR  );
+REG64( PERV_N2_LOCAL_FIR                                       , RULL(0x0404000A), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_LOCAL_FIR_AND                                   , RULL(0x0404000B), SH_UNT_PERV_4   , SH_ACS_SCOM1_AND );
+REG64( PERV_N2_LOCAL_FIR_OR                                    , RULL(0x0404000C), SH_UNT_PERV_4   , SH_ACS_SCOM2_OR  );
+REG64( PERV_N3_LOCAL_FIR                                       , RULL(0x0504000A), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_LOCAL_FIR_AND                                   , RULL(0x0504000B), SH_UNT_PERV_5   , SH_ACS_SCOM1_AND );
+REG64( PERV_N3_LOCAL_FIR_OR                                    , RULL(0x0504000C), SH_UNT_PERV_5   , SH_ACS_SCOM2_OR  );
+REG64( PERV_XB_LOCAL_FIR                                       , RULL(0x0604000A), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_LOCAL_FIR_AND                                   , RULL(0x0604000B), SH_UNT_PERV_6   , SH_ACS_SCOM1_AND );
+REG64( PERV_XB_LOCAL_FIR_OR                                    , RULL(0x0604000C), SH_UNT_PERV_6   , SH_ACS_SCOM2_OR  );
+REG64( PERV_MC01_LOCAL_FIR                                     , RULL(0x0704000A), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_LOCAL_FIR_AND                                 , RULL(0x0704000B), SH_UNT_PERV_7   , SH_ACS_SCOM1_AND );
+REG64( PERV_MC01_LOCAL_FIR_OR                                  , RULL(0x0704000C), SH_UNT_PERV_7   , SH_ACS_SCOM2_OR  );
+REG64( PERV_MC23_LOCAL_FIR                                     , RULL(0x0804000A), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_LOCAL_FIR_AND                                 , RULL(0x0804000B), SH_UNT_PERV_8   , SH_ACS_SCOM1_AND );
+REG64( PERV_MC23_LOCAL_FIR_OR                                  , RULL(0x0804000C), SH_UNT_PERV_8   , SH_ACS_SCOM2_OR  );
+REG64( PERV_OB0_LOCAL_FIR                                      , RULL(0x0904000A), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_LOCAL_FIR_AND                                  , RULL(0x0904000B), SH_UNT_PERV_9   , SH_ACS_SCOM1_AND );
+REG64( PERV_OB0_LOCAL_FIR_OR                                   , RULL(0x0904000C), SH_UNT_PERV_9   , SH_ACS_SCOM2_OR  );
+REG64( PERV_OB3_LOCAL_FIR                                      , RULL(0x0C04000A), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_LOCAL_FIR_AND                                  , RULL(0x0C04000B), SH_UNT_PERV_12  , SH_ACS_SCOM1_AND );
+REG64( PERV_OB3_LOCAL_FIR_OR                                   , RULL(0x0C04000C), SH_UNT_PERV_12  , SH_ACS_SCOM2_OR  );
+REG64( PERV_PCI0_LOCAL_FIR                                     , RULL(0x0D04000A), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_LOCAL_FIR_AND                                 , RULL(0x0D04000B), SH_UNT_PERV_13  , SH_ACS_SCOM1_AND );
+REG64( PERV_PCI0_LOCAL_FIR_OR                                  , RULL(0x0D04000C), SH_UNT_PERV_13  , SH_ACS_SCOM2_OR  );
+REG64( PERV_PCI1_LOCAL_FIR                                     , RULL(0x0E04000A), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_LOCAL_FIR_AND                                 , RULL(0x0E04000B), SH_UNT_PERV_14  , SH_ACS_SCOM1_AND );
+REG64( PERV_PCI1_LOCAL_FIR_OR                                  , RULL(0x0E04000C), SH_UNT_PERV_14  , SH_ACS_SCOM2_OR  );
+REG64( PERV_PCI2_LOCAL_FIR                                     , RULL(0x0F04000A), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_LOCAL_FIR_AND                                 , RULL(0x0F04000B), SH_UNT_PERV_15  , SH_ACS_SCOM1_AND );
+REG64( PERV_PCI2_LOCAL_FIR_OR                                  , RULL(0x0F04000C), SH_UNT_PERV_15  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP00_LOCAL_FIR                                     , RULL(0x1004000A), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_LOCAL_FIR_AND                                 , RULL(0x1004000B), SH_UNT_PERV_16  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP00_LOCAL_FIR_OR                                  , RULL(0x1004000C), SH_UNT_PERV_16  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP01_LOCAL_FIR                                     , RULL(0x1104000A), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_LOCAL_FIR_AND                                 , RULL(0x1104000B), SH_UNT_PERV_17  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP01_LOCAL_FIR_OR                                  , RULL(0x1104000C), SH_UNT_PERV_17  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP02_LOCAL_FIR                                     , RULL(0x1204000A), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_LOCAL_FIR_AND                                 , RULL(0x1204000B), SH_UNT_PERV_18  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP02_LOCAL_FIR_OR                                  , RULL(0x1204000C), SH_UNT_PERV_18  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP03_LOCAL_FIR                                     , RULL(0x1304000A), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_LOCAL_FIR_AND                                 , RULL(0x1304000B), SH_UNT_PERV_19  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP03_LOCAL_FIR_OR                                  , RULL(0x1304000C), SH_UNT_PERV_19  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP04_LOCAL_FIR                                     , RULL(0x1404000A), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_LOCAL_FIR_AND                                 , RULL(0x1404000B), SH_UNT_PERV_20  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP04_LOCAL_FIR_OR                                  , RULL(0x1404000C), SH_UNT_PERV_20  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP05_LOCAL_FIR                                     , RULL(0x1504000A), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_LOCAL_FIR_AND                                 , RULL(0x1504000B), SH_UNT_PERV_21  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP05_LOCAL_FIR_OR                                  , RULL(0x1504000C), SH_UNT_PERV_21  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC00_LOCAL_FIR                                     , RULL(0x2004000A), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_LOCAL_FIR_AND                                 , RULL(0x2004000B), SH_UNT_PERV_32  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC00_LOCAL_FIR_OR                                  , RULL(0x2004000C), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_LOCAL_FIR                                     , RULL(0x2104000A), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_LOCAL_FIR_AND                                 , RULL(0x2104000B), SH_UNT_PERV_33  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC01_LOCAL_FIR_OR                                  , RULL(0x2104000C), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_LOCAL_FIR                                     , RULL(0x2204000A), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_LOCAL_FIR_AND                                 , RULL(0x2204000B), SH_UNT_PERV_34  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC02_LOCAL_FIR_OR                                  , RULL(0x2204000C), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_LOCAL_FIR                                     , RULL(0x2304000A), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_LOCAL_FIR_AND                                 , RULL(0x2304000B), SH_UNT_PERV_35  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC03_LOCAL_FIR_OR                                  , RULL(0x2304000C), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_LOCAL_FIR                                     , RULL(0x2404000A), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_LOCAL_FIR_AND                                 , RULL(0x2404000B), SH_UNT_PERV_36  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC04_LOCAL_FIR_OR                                  , RULL(0x2404000C), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_LOCAL_FIR                                     , RULL(0x2504000A), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_LOCAL_FIR_AND                                 , RULL(0x2504000B), SH_UNT_PERV_37  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC05_LOCAL_FIR_OR                                  , RULL(0x2504000C), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_LOCAL_FIR                                     , RULL(0x2604000A), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_LOCAL_FIR_AND                                 , RULL(0x2604000B), SH_UNT_PERV_38  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC06_LOCAL_FIR_OR                                  , RULL(0x2604000C), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_LOCAL_FIR                                     , RULL(0x2704000A), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_LOCAL_FIR_AND                                 , RULL(0x2704000B), SH_UNT_PERV_39  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC07_LOCAL_FIR_OR                                  , RULL(0x2704000C), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_LOCAL_FIR                                     , RULL(0x2804000A), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_LOCAL_FIR_AND                                 , RULL(0x2804000B), SH_UNT_PERV_40  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC08_LOCAL_FIR_OR                                  , RULL(0x2804000C), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_LOCAL_FIR                                     , RULL(0x2904000A), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_LOCAL_FIR_AND                                 , RULL(0x2904000B), SH_UNT_PERV_41  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC09_LOCAL_FIR_OR                                  , RULL(0x2904000C), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_LOCAL_FIR                                     , RULL(0x2A04000A), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_LOCAL_FIR_AND                                 , RULL(0x2A04000B), SH_UNT_PERV_42  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC10_LOCAL_FIR_OR                                  , RULL(0x2A04000C), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_LOCAL_FIR                                     , RULL(0x2B04000A), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_LOCAL_FIR_AND                                 , RULL(0x2B04000B), SH_UNT_PERV_43  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC11_LOCAL_FIR_OR                                  , RULL(0x2B04000C), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_LOCAL_FIR                                     , RULL(0x2C04000A), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_LOCAL_FIR_AND                                 , RULL(0x2C04000B), SH_UNT_PERV_44  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC12_LOCAL_FIR_OR                                  , RULL(0x2C04000C), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_LOCAL_FIR                                     , RULL(0x2D04000A), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_LOCAL_FIR_AND                                 , RULL(0x2D04000B), SH_UNT_PERV_45  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC13_LOCAL_FIR_OR                                  , RULL(0x2D04000C), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_LOCAL_FIR                                     , RULL(0x2E04000A), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_LOCAL_FIR_AND                                 , RULL(0x2E04000B), SH_UNT_PERV_46  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC14_LOCAL_FIR_OR                                  , RULL(0x2E04000C), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_LOCAL_FIR                                     , RULL(0x2F04000A), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_LOCAL_FIR_AND                                 , RULL(0x2F04000B), SH_UNT_PERV_47  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC15_LOCAL_FIR_OR                                  , RULL(0x2F04000C), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_LOCAL_FIR                                     , RULL(0x3004000A), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_LOCAL_FIR_AND                                 , RULL(0x3004000B), SH_UNT_PERV_48  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC16_LOCAL_FIR_OR                                  , RULL(0x3004000C), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_LOCAL_FIR                                     , RULL(0x3104000A), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_LOCAL_FIR_AND                                 , RULL(0x3104000B), SH_UNT_PERV_49  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC17_LOCAL_FIR_OR                                  , RULL(0x3104000C), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_LOCAL_FIR                                     , RULL(0x3204000A), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_LOCAL_FIR_AND                                 , RULL(0x3204000B), SH_UNT_PERV_50  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC18_LOCAL_FIR_OR                                  , RULL(0x3204000C), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_LOCAL_FIR                                     , RULL(0x3304000A), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_LOCAL_FIR_AND                                 , RULL(0x3304000B), SH_UNT_PERV_51  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC19_LOCAL_FIR_OR                                  , RULL(0x3304000C), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_LOCAL_FIR                                     , RULL(0x3404000A), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_LOCAL_FIR_AND                                 , RULL(0x3404000B), SH_UNT_PERV_52  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC20_LOCAL_FIR_OR                                  , RULL(0x3404000C), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_LOCAL_FIR                                     , RULL(0x3504000A), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_LOCAL_FIR_AND                                 , RULL(0x3504000B), SH_UNT_PERV_53  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC21_LOCAL_FIR_OR                                  , RULL(0x3504000C), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_LOCAL_FIR                                     , RULL(0x3604000A), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_LOCAL_FIR_AND                                 , RULL(0x3604000B), SH_UNT_PERV_54  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC22_LOCAL_FIR_OR                                  , RULL(0x3604000C), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_LOCAL_FIR                                     , RULL(0x3704000A), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_LOCAL_FIR_AND                                 , RULL(0x3704000B), SH_UNT_PERV_55  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC23_LOCAL_FIR_OR                                  , RULL(0x3704000C), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_LOCAL_FIR_ACTION0                                  , RULL(0x00040010), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_LOCAL_FIR_ACTION0                               , RULL(0x01040010), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_LOCAL_FIR_ACTION0                               , RULL(0x02040010), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_LOCAL_FIR_ACTION0                               , RULL(0x03040010), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_LOCAL_FIR_ACTION0                               , RULL(0x04040010), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_LOCAL_FIR_ACTION0                               , RULL(0x05040010), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_LOCAL_FIR_ACTION0                               , RULL(0x06040010), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_LOCAL_FIR_ACTION0                             , RULL(0x07040010), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_LOCAL_FIR_ACTION0                             , RULL(0x08040010), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_LOCAL_FIR_ACTION0                              , RULL(0x09040010), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_LOCAL_FIR_ACTION0                              , RULL(0x0C040010), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_LOCAL_FIR_ACTION0                             , RULL(0x0D040010), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_LOCAL_FIR_ACTION0                             , RULL(0x0E040010), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_LOCAL_FIR_ACTION0                             , RULL(0x0F040010), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_LOCAL_FIR_ACTION0                             , RULL(0x10040010), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_LOCAL_FIR_ACTION0                             , RULL(0x11040010), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_LOCAL_FIR_ACTION0                             , RULL(0x12040010), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_LOCAL_FIR_ACTION0                             , RULL(0x13040010), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_LOCAL_FIR_ACTION0                             , RULL(0x14040010), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_LOCAL_FIR_ACTION0                             , RULL(0x15040010), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_LOCAL_FIR_ACTION0                             , RULL(0x20040010), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_LOCAL_FIR_ACTION0                             , RULL(0x21040010), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_LOCAL_FIR_ACTION0                             , RULL(0x22040010), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_LOCAL_FIR_ACTION0                             , RULL(0x23040010), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_LOCAL_FIR_ACTION0                             , RULL(0x24040010), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_LOCAL_FIR_ACTION0                             , RULL(0x25040010), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_LOCAL_FIR_ACTION0                             , RULL(0x26040010), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_LOCAL_FIR_ACTION0                             , RULL(0x27040010), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_LOCAL_FIR_ACTION0                             , RULL(0x28040010), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_LOCAL_FIR_ACTION0                             , RULL(0x29040010), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_LOCAL_FIR_ACTION0                             , RULL(0x2A040010), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_LOCAL_FIR_ACTION0                             , RULL(0x2B040010), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_LOCAL_FIR_ACTION0                             , RULL(0x2C040010), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_LOCAL_FIR_ACTION0                             , RULL(0x2D040010), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_LOCAL_FIR_ACTION0                             , RULL(0x2E040010), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_LOCAL_FIR_ACTION0                             , RULL(0x2F040010), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_LOCAL_FIR_ACTION0                             , RULL(0x30040010), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_LOCAL_FIR_ACTION0                             , RULL(0x31040010), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_LOCAL_FIR_ACTION0                             , RULL(0x32040010), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_LOCAL_FIR_ACTION0                             , RULL(0x33040010), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_LOCAL_FIR_ACTION0                             , RULL(0x34040010), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_LOCAL_FIR_ACTION0                             , RULL(0x35040010), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_LOCAL_FIR_ACTION0                             , RULL(0x36040010), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_LOCAL_FIR_ACTION0                             , RULL(0x37040010), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_LOCAL_FIR_ACTION1                                  , RULL(0x00040011), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_LOCAL_FIR_ACTION1                               , RULL(0x01040011), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_LOCAL_FIR_ACTION1                               , RULL(0x02040011), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_LOCAL_FIR_ACTION1                               , RULL(0x03040011), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_LOCAL_FIR_ACTION1                               , RULL(0x04040011), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_LOCAL_FIR_ACTION1                               , RULL(0x05040011), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_LOCAL_FIR_ACTION1                               , RULL(0x06040011), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_LOCAL_FIR_ACTION1                             , RULL(0x07040011), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_LOCAL_FIR_ACTION1                             , RULL(0x08040011), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_LOCAL_FIR_ACTION1                              , RULL(0x09040011), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_LOCAL_FIR_ACTION1                              , RULL(0x0C040011), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_LOCAL_FIR_ACTION1                             , RULL(0x0D040011), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_LOCAL_FIR_ACTION1                             , RULL(0x0E040011), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_LOCAL_FIR_ACTION1                             , RULL(0x0F040011), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_LOCAL_FIR_ACTION1                             , RULL(0x10040011), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_LOCAL_FIR_ACTION1                             , RULL(0x11040011), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_LOCAL_FIR_ACTION1                             , RULL(0x12040011), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_LOCAL_FIR_ACTION1                             , RULL(0x13040011), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_LOCAL_FIR_ACTION1                             , RULL(0x14040011), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_LOCAL_FIR_ACTION1                             , RULL(0x15040011), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_LOCAL_FIR_ACTION1                             , RULL(0x20040011), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_LOCAL_FIR_ACTION1                             , RULL(0x21040011), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_LOCAL_FIR_ACTION1                             , RULL(0x22040011), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_LOCAL_FIR_ACTION1                             , RULL(0x23040011), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_LOCAL_FIR_ACTION1                             , RULL(0x24040011), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_LOCAL_FIR_ACTION1                             , RULL(0x25040011), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_LOCAL_FIR_ACTION1                             , RULL(0x26040011), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_LOCAL_FIR_ACTION1                             , RULL(0x27040011), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_LOCAL_FIR_ACTION1                             , RULL(0x28040011), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_LOCAL_FIR_ACTION1                             , RULL(0x29040011), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_LOCAL_FIR_ACTION1                             , RULL(0x2A040011), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_LOCAL_FIR_ACTION1                             , RULL(0x2B040011), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_LOCAL_FIR_ACTION1                             , RULL(0x2C040011), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_LOCAL_FIR_ACTION1                             , RULL(0x2D040011), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_LOCAL_FIR_ACTION1                             , RULL(0x2E040011), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_LOCAL_FIR_ACTION1                             , RULL(0x2F040011), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_LOCAL_FIR_ACTION1                             , RULL(0x30040011), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_LOCAL_FIR_ACTION1                             , RULL(0x31040011), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_LOCAL_FIR_ACTION1                             , RULL(0x32040011), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_LOCAL_FIR_ACTION1                             , RULL(0x33040011), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_LOCAL_FIR_ACTION1                             , RULL(0x34040011), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_LOCAL_FIR_ACTION1                             , RULL(0x35040011), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_LOCAL_FIR_ACTION1                             , RULL(0x36040011), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_LOCAL_FIR_ACTION1                             , RULL(0x37040011), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_LOCAL_FIR_MASK                                     , RULL(0x0004000D), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_LOCAL_FIR_MASK                                  , RULL(0x0104000D), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_LOCAL_FIR_MASK_AND                                 , RULL(0x0004000E), SH_UNT_PERV     , SH_ACS_SCOM1_AND );
+REG64( PERV_TP_LOCAL_FIR_MASK_AND                              , RULL(0x0104000E), SH_UNT_PERV_1   , SH_ACS_SCOM1_AND );
+REG64( PERV_LOCAL_FIR_MASK_OR                                  , RULL(0x0004000F), SH_UNT_PERV     , SH_ACS_SCOM2_OR  );
+REG64( PERV_TP_LOCAL_FIR_MASK_OR                               , RULL(0x0104000F), SH_UNT_PERV_1   , SH_ACS_SCOM2_OR  );
+REG64( PERV_N0_LOCAL_FIR_MASK                                  , RULL(0x0204000D), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_LOCAL_FIR_MASK_AND                              , RULL(0x0204000E), SH_UNT_PERV_2   , SH_ACS_SCOM1_AND );
+REG64( PERV_N0_LOCAL_FIR_MASK_OR                               , RULL(0x0204000F), SH_UNT_PERV_2   , SH_ACS_SCOM2_OR  );
+REG64( PERV_N1_LOCAL_FIR_MASK                                  , RULL(0x0304000D), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_LOCAL_FIR_MASK_AND                              , RULL(0x0304000E), SH_UNT_PERV_3   , SH_ACS_SCOM1_AND );
+REG64( PERV_N1_LOCAL_FIR_MASK_OR                               , RULL(0x0304000F), SH_UNT_PERV_3   , SH_ACS_SCOM2_OR  );
+REG64( PERV_N2_LOCAL_FIR_MASK                                  , RULL(0x0404000D), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_LOCAL_FIR_MASK_AND                              , RULL(0x0404000E), SH_UNT_PERV_4   , SH_ACS_SCOM1_AND );
+REG64( PERV_N2_LOCAL_FIR_MASK_OR                               , RULL(0x0404000F), SH_UNT_PERV_4   , SH_ACS_SCOM2_OR  );
+REG64( PERV_N3_LOCAL_FIR_MASK                                  , RULL(0x0504000D), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_LOCAL_FIR_MASK_AND                              , RULL(0x0504000E), SH_UNT_PERV_5   , SH_ACS_SCOM1_AND );
+REG64( PERV_N3_LOCAL_FIR_MASK_OR                               , RULL(0x0504000F), SH_UNT_PERV_5   , SH_ACS_SCOM2_OR  );
+REG64( PERV_XB_LOCAL_FIR_MASK                                  , RULL(0x0604000D), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_LOCAL_FIR_MASK_AND                              , RULL(0x0604000E), SH_UNT_PERV_6   , SH_ACS_SCOM1_AND );
+REG64( PERV_XB_LOCAL_FIR_MASK_OR                               , RULL(0x0604000F), SH_UNT_PERV_6   , SH_ACS_SCOM2_OR  );
+REG64( PERV_MC01_LOCAL_FIR_MASK                                , RULL(0x0704000D), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_LOCAL_FIR_MASK_AND                            , RULL(0x0704000E), SH_UNT_PERV_7   , SH_ACS_SCOM1_AND );
+REG64( PERV_MC01_LOCAL_FIR_MASK_OR                             , RULL(0x0704000F), SH_UNT_PERV_7   , SH_ACS_SCOM2_OR  );
+REG64( PERV_MC23_LOCAL_FIR_MASK                                , RULL(0x0804000D), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_LOCAL_FIR_MASK_AND                            , RULL(0x0804000E), SH_UNT_PERV_8   , SH_ACS_SCOM1_AND );
+REG64( PERV_MC23_LOCAL_FIR_MASK_OR                             , RULL(0x0804000F), SH_UNT_PERV_8   , SH_ACS_SCOM2_OR  );
+REG64( PERV_OB0_LOCAL_FIR_MASK                                 , RULL(0x0904000D), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_LOCAL_FIR_MASK_AND                             , RULL(0x0904000E), SH_UNT_PERV_9   , SH_ACS_SCOM1_AND );
+REG64( PERV_OB0_LOCAL_FIR_MASK_OR                              , RULL(0x0904000F), SH_UNT_PERV_9   , SH_ACS_SCOM2_OR  );
+REG64( PERV_OB3_LOCAL_FIR_MASK                                 , RULL(0x0C04000D), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_LOCAL_FIR_MASK_AND                             , RULL(0x0C04000E), SH_UNT_PERV_12  , SH_ACS_SCOM1_AND );
+REG64( PERV_OB3_LOCAL_FIR_MASK_OR                              , RULL(0x0C04000F), SH_UNT_PERV_12  , SH_ACS_SCOM2_OR  );
+REG64( PERV_PCI0_LOCAL_FIR_MASK                                , RULL(0x0D04000D), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_LOCAL_FIR_MASK_AND                            , RULL(0x0D04000E), SH_UNT_PERV_13  , SH_ACS_SCOM1_AND );
+REG64( PERV_PCI0_LOCAL_FIR_MASK_OR                             , RULL(0x0D04000F), SH_UNT_PERV_13  , SH_ACS_SCOM2_OR  );
+REG64( PERV_PCI1_LOCAL_FIR_MASK                                , RULL(0x0E04000D), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_LOCAL_FIR_MASK_AND                            , RULL(0x0E04000E), SH_UNT_PERV_14  , SH_ACS_SCOM1_AND );
+REG64( PERV_PCI1_LOCAL_FIR_MASK_OR                             , RULL(0x0E04000F), SH_UNT_PERV_14  , SH_ACS_SCOM2_OR  );
+REG64( PERV_PCI2_LOCAL_FIR_MASK                                , RULL(0x0F04000D), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_LOCAL_FIR_MASK_AND                            , RULL(0x0F04000E), SH_UNT_PERV_15  , SH_ACS_SCOM1_AND );
+REG64( PERV_PCI2_LOCAL_FIR_MASK_OR                             , RULL(0x0F04000F), SH_UNT_PERV_15  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP00_LOCAL_FIR_MASK                                , RULL(0x1004000D), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_LOCAL_FIR_MASK_AND                            , RULL(0x1004000E), SH_UNT_PERV_16  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP00_LOCAL_FIR_MASK_OR                             , RULL(0x1004000F), SH_UNT_PERV_16  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP01_LOCAL_FIR_MASK                                , RULL(0x1104000D), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_LOCAL_FIR_MASK_AND                            , RULL(0x1104000E), SH_UNT_PERV_17  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP01_LOCAL_FIR_MASK_OR                             , RULL(0x1104000F), SH_UNT_PERV_17  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP02_LOCAL_FIR_MASK                                , RULL(0x1204000D), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_LOCAL_FIR_MASK_AND                            , RULL(0x1204000E), SH_UNT_PERV_18  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP02_LOCAL_FIR_MASK_OR                             , RULL(0x1204000F), SH_UNT_PERV_18  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP03_LOCAL_FIR_MASK                                , RULL(0x1304000D), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_LOCAL_FIR_MASK_AND                            , RULL(0x1304000E), SH_UNT_PERV_19  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP03_LOCAL_FIR_MASK_OR                             , RULL(0x1304000F), SH_UNT_PERV_19  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP04_LOCAL_FIR_MASK                                , RULL(0x1404000D), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_LOCAL_FIR_MASK_AND                            , RULL(0x1404000E), SH_UNT_PERV_20  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP04_LOCAL_FIR_MASK_OR                             , RULL(0x1404000F), SH_UNT_PERV_20  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP05_LOCAL_FIR_MASK                                , RULL(0x1504000D), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_LOCAL_FIR_MASK_AND                            , RULL(0x1504000E), SH_UNT_PERV_21  , SH_ACS_SCOM1_AND );
+REG64( PERV_EP05_LOCAL_FIR_MASK_OR                             , RULL(0x1504000F), SH_UNT_PERV_21  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC00_LOCAL_FIR_MASK                                , RULL(0x2004000D), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_LOCAL_FIR_MASK_AND                            , RULL(0x2004000E), SH_UNT_PERV_32  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC00_LOCAL_FIR_MASK_OR                             , RULL(0x2004000F), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_LOCAL_FIR_MASK                                , RULL(0x2104000D), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_LOCAL_FIR_MASK_AND                            , RULL(0x2104000E), SH_UNT_PERV_33  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC01_LOCAL_FIR_MASK_OR                             , RULL(0x2104000F), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_LOCAL_FIR_MASK                                , RULL(0x2204000D), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_LOCAL_FIR_MASK_AND                            , RULL(0x2204000E), SH_UNT_PERV_34  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC02_LOCAL_FIR_MASK_OR                             , RULL(0x2204000F), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_LOCAL_FIR_MASK                                , RULL(0x2304000D), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_LOCAL_FIR_MASK_AND                            , RULL(0x2304000E), SH_UNT_PERV_35  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC03_LOCAL_FIR_MASK_OR                             , RULL(0x2304000F), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_LOCAL_FIR_MASK                                , RULL(0x2404000D), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_LOCAL_FIR_MASK_AND                            , RULL(0x2404000E), SH_UNT_PERV_36  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC04_LOCAL_FIR_MASK_OR                             , RULL(0x2404000F), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_LOCAL_FIR_MASK                                , RULL(0x2504000D), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_LOCAL_FIR_MASK_AND                            , RULL(0x2504000E), SH_UNT_PERV_37  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC05_LOCAL_FIR_MASK_OR                             , RULL(0x2504000F), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_LOCAL_FIR_MASK                                , RULL(0x2604000D), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_LOCAL_FIR_MASK_AND                            , RULL(0x2604000E), SH_UNT_PERV_38  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC06_LOCAL_FIR_MASK_OR                             , RULL(0x2604000F), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_LOCAL_FIR_MASK                                , RULL(0x2704000D), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_LOCAL_FIR_MASK_AND                            , RULL(0x2704000E), SH_UNT_PERV_39  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC07_LOCAL_FIR_MASK_OR                             , RULL(0x2704000F), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_LOCAL_FIR_MASK                                , RULL(0x2804000D), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_LOCAL_FIR_MASK_AND                            , RULL(0x2804000E), SH_UNT_PERV_40  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC08_LOCAL_FIR_MASK_OR                             , RULL(0x2804000F), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_LOCAL_FIR_MASK                                , RULL(0x2904000D), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_LOCAL_FIR_MASK_AND                            , RULL(0x2904000E), SH_UNT_PERV_41  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC09_LOCAL_FIR_MASK_OR                             , RULL(0x2904000F), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_LOCAL_FIR_MASK                                , RULL(0x2A04000D), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_LOCAL_FIR_MASK_AND                            , RULL(0x2A04000E), SH_UNT_PERV_42  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC10_LOCAL_FIR_MASK_OR                             , RULL(0x2A04000F), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_LOCAL_FIR_MASK                                , RULL(0x2B04000D), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_LOCAL_FIR_MASK_AND                            , RULL(0x2B04000E), SH_UNT_PERV_43  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC11_LOCAL_FIR_MASK_OR                             , RULL(0x2B04000F), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_LOCAL_FIR_MASK                                , RULL(0x2C04000D), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_LOCAL_FIR_MASK_AND                            , RULL(0x2C04000E), SH_UNT_PERV_44  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC12_LOCAL_FIR_MASK_OR                             , RULL(0x2C04000F), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_LOCAL_FIR_MASK                                , RULL(0x2D04000D), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_LOCAL_FIR_MASK_AND                            , RULL(0x2D04000E), SH_UNT_PERV_45  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC13_LOCAL_FIR_MASK_OR                             , RULL(0x2D04000F), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_LOCAL_FIR_MASK                                , RULL(0x2E04000D), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_LOCAL_FIR_MASK_AND                            , RULL(0x2E04000E), SH_UNT_PERV_46  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC14_LOCAL_FIR_MASK_OR                             , RULL(0x2E04000F), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_LOCAL_FIR_MASK                                , RULL(0x2F04000D), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_LOCAL_FIR_MASK_AND                            , RULL(0x2F04000E), SH_UNT_PERV_47  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC15_LOCAL_FIR_MASK_OR                             , RULL(0x2F04000F), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_LOCAL_FIR_MASK                                , RULL(0x3004000D), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_LOCAL_FIR_MASK_AND                            , RULL(0x3004000E), SH_UNT_PERV_48  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC16_LOCAL_FIR_MASK_OR                             , RULL(0x3004000F), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_LOCAL_FIR_MASK                                , RULL(0x3104000D), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_LOCAL_FIR_MASK_AND                            , RULL(0x3104000E), SH_UNT_PERV_49  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC17_LOCAL_FIR_MASK_OR                             , RULL(0x3104000F), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_LOCAL_FIR_MASK                                , RULL(0x3204000D), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_LOCAL_FIR_MASK_AND                            , RULL(0x3204000E), SH_UNT_PERV_50  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC18_LOCAL_FIR_MASK_OR                             , RULL(0x3204000F), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_LOCAL_FIR_MASK                                , RULL(0x3304000D), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_LOCAL_FIR_MASK_AND                            , RULL(0x3304000E), SH_UNT_PERV_51  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC19_LOCAL_FIR_MASK_OR                             , RULL(0x3304000F), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_LOCAL_FIR_MASK                                , RULL(0x3404000D), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_LOCAL_FIR_MASK_AND                            , RULL(0x3404000E), SH_UNT_PERV_52  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC20_LOCAL_FIR_MASK_OR                             , RULL(0x3404000F), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_LOCAL_FIR_MASK                                , RULL(0x3504000D), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_LOCAL_FIR_MASK_AND                            , RULL(0x3504000E), SH_UNT_PERV_53  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC21_LOCAL_FIR_MASK_OR                             , RULL(0x3504000F), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_LOCAL_FIR_MASK                                , RULL(0x3604000D), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_LOCAL_FIR_MASK_AND                            , RULL(0x3604000E), SH_UNT_PERV_54  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC22_LOCAL_FIR_MASK_OR                             , RULL(0x3604000F), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_LOCAL_FIR_MASK                                , RULL(0x3704000D), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_LOCAL_FIR_MASK_AND                            , RULL(0x3704000E), SH_UNT_PERV_55  , SH_ACS_SCOM1_AND );
+REG64( PERV_EC23_LOCAL_FIR_MASK_OR                             , RULL(0x3704000F), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_LOCAL_XSTOP_ERR                                    , RULL(0x00040018), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_LOCAL_XSTOP_ERR                                 , RULL(0x01040018), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_LOCAL_XSTOP_ERR                                 , RULL(0x02040018), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_LOCAL_XSTOP_ERR                                 , RULL(0x03040018), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_LOCAL_XSTOP_ERR                                 , RULL(0x04040018), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_LOCAL_XSTOP_ERR                                 , RULL(0x05040018), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_LOCAL_XSTOP_ERR                                 , RULL(0x06040018), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_LOCAL_XSTOP_ERR                               , RULL(0x07040018), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_LOCAL_XSTOP_ERR                               , RULL(0x08040018), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_LOCAL_XSTOP_ERR                                , RULL(0x09040018), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_LOCAL_XSTOP_ERR                                , RULL(0x0C040018), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_LOCAL_XSTOP_ERR                               , RULL(0x0D040018), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_LOCAL_XSTOP_ERR                               , RULL(0x0E040018), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_LOCAL_XSTOP_ERR                               , RULL(0x0F040018), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_LOCAL_XSTOP_ERR                               , RULL(0x10040018), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_LOCAL_XSTOP_ERR                               , RULL(0x11040018), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_LOCAL_XSTOP_ERR                               , RULL(0x12040018), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_LOCAL_XSTOP_ERR                               , RULL(0x13040018), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_LOCAL_XSTOP_ERR                               , RULL(0x14040018), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_LOCAL_XSTOP_ERR                               , RULL(0x15040018), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_LOCAL_XSTOP_ERR                               , RULL(0x20040018), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_LOCAL_XSTOP_ERR                               , RULL(0x21040018), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_LOCAL_XSTOP_ERR                               , RULL(0x22040018), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_LOCAL_XSTOP_ERR                               , RULL(0x23040018), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_LOCAL_XSTOP_ERR                               , RULL(0x24040018), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_LOCAL_XSTOP_ERR                               , RULL(0x25040018), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_LOCAL_XSTOP_ERR                               , RULL(0x26040018), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_LOCAL_XSTOP_ERR                               , RULL(0x27040018), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_LOCAL_XSTOP_ERR                               , RULL(0x28040018), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_LOCAL_XSTOP_ERR                               , RULL(0x29040018), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_LOCAL_XSTOP_ERR                               , RULL(0x2A040018), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_LOCAL_XSTOP_ERR                               , RULL(0x2B040018), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_LOCAL_XSTOP_ERR                               , RULL(0x2C040018), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_LOCAL_XSTOP_ERR                               , RULL(0x2D040018), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_LOCAL_XSTOP_ERR                               , RULL(0x2E040018), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_LOCAL_XSTOP_ERR                               , RULL(0x2F040018), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_LOCAL_XSTOP_ERR                               , RULL(0x30040018), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_LOCAL_XSTOP_ERR                               , RULL(0x31040018), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_LOCAL_XSTOP_ERR                               , RULL(0x32040018), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_LOCAL_XSTOP_ERR                               , RULL(0x33040018), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_LOCAL_XSTOP_ERR                               , RULL(0x34040018), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_LOCAL_XSTOP_ERR                               , RULL(0x35040018), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_LOCAL_XSTOP_ERR                               , RULL(0x36040018), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_LOCAL_XSTOP_ERR                               , RULL(0x37040018), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_LOCAL_XSTOP_MASK                                   , RULL(0x00040019), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_LOCAL_XSTOP_MASK                                , RULL(0x01040019), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_LOCAL_XSTOP_MASK                                , RULL(0x02040019), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_LOCAL_XSTOP_MASK                                , RULL(0x03040019), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_LOCAL_XSTOP_MASK                                , RULL(0x04040019), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_LOCAL_XSTOP_MASK                                , RULL(0x05040019), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_LOCAL_XSTOP_MASK                                , RULL(0x06040019), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_LOCAL_XSTOP_MASK                              , RULL(0x07040019), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_LOCAL_XSTOP_MASK                              , RULL(0x08040019), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_LOCAL_XSTOP_MASK                               , RULL(0x09040019), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_LOCAL_XSTOP_MASK                               , RULL(0x0C040019), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_LOCAL_XSTOP_MASK                              , RULL(0x0D040019), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_LOCAL_XSTOP_MASK                              , RULL(0x0E040019), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_LOCAL_XSTOP_MASK                              , RULL(0x0F040019), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_LOCAL_XSTOP_MASK                              , RULL(0x10040019), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_LOCAL_XSTOP_MASK                              , RULL(0x11040019), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_LOCAL_XSTOP_MASK                              , RULL(0x12040019), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_LOCAL_XSTOP_MASK                              , RULL(0x13040019), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_LOCAL_XSTOP_MASK                              , RULL(0x14040019), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_LOCAL_XSTOP_MASK                              , RULL(0x15040019), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_LOCAL_XSTOP_MASK                              , RULL(0x20040019), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_LOCAL_XSTOP_MASK                              , RULL(0x21040019), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_LOCAL_XSTOP_MASK                              , RULL(0x22040019), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_LOCAL_XSTOP_MASK                              , RULL(0x23040019), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_LOCAL_XSTOP_MASK                              , RULL(0x24040019), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_LOCAL_XSTOP_MASK                              , RULL(0x25040019), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_LOCAL_XSTOP_MASK                              , RULL(0x26040019), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_LOCAL_XSTOP_MASK                              , RULL(0x27040019), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_LOCAL_XSTOP_MASK                              , RULL(0x28040019), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_LOCAL_XSTOP_MASK                              , RULL(0x29040019), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_LOCAL_XSTOP_MASK                              , RULL(0x2A040019), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_LOCAL_XSTOP_MASK                              , RULL(0x2B040019), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_LOCAL_XSTOP_MASK                              , RULL(0x2C040019), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_LOCAL_XSTOP_MASK                              , RULL(0x2D040019), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_LOCAL_XSTOP_MASK                              , RULL(0x2E040019), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_LOCAL_XSTOP_MASK                              , RULL(0x2F040019), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_LOCAL_XSTOP_MASK                              , RULL(0x30040019), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_LOCAL_XSTOP_MASK                              , RULL(0x31040019), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_LOCAL_XSTOP_MASK                              , RULL(0x32040019), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_LOCAL_XSTOP_MASK                              , RULL(0x33040019), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_LOCAL_XSTOP_MASK                              , RULL(0x34040019), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_LOCAL_XSTOP_MASK                              , RULL(0x35040019), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_LOCAL_XSTOP_MASK                              , RULL(0x36040019), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_LOCAL_XSTOP_MASK                              , RULL(0x37040019), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_LSTAT                                              , RULL(0x00030002), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_LSTAT                                          , RULL(0x00030002), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+REG64( PERV_0_PIB2OPB0_LSTAT                                   , RULL(0x00020002), SH_UNT_PERV_0_PIB2OPB0,
+       SH_ACS_SCOM_RO   );
+REG64( PERV_0_PIB2OPB1_LSTAT                                   , RULL(0x00020012), SH_UNT_PERV_0_PIB2OPB1,
+       SH_ACS_SCOM_RO   );
+REG64( PERV_PIB2OPB0_LSTAT                                     , RULL(0x00020002), SH_UNT_PERV_PIB2OPB0,
+       SH_ACS_SCOM_RO   );
+REG64( PERV_PIB2OPB1_LSTAT                                     , RULL(0x00020012), SH_UNT_PERV_PIB2OPB1,
+       SH_ACS_SCOM_RO   );
+
+REG32( PERV_M1A_DATA_AREA_0_FSI                                , RULL(0x00002840), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_0_FSI_BYTE                           , RULL(0x00002900), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_0_SCOM                               , RULL(0x00050040), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_0                                , RULL(0x00050040), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_1_FSI                                , RULL(0x00002841), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_1_FSI_BYTE                           , RULL(0x00002904), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_1_SCOM                               , RULL(0x00050041), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_1                                , RULL(0x00050041), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_10_FSI                               , RULL(0x0000284A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_10_FSI_BYTE                          , RULL(0x00002928), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_10_SCOM                              , RULL(0x0005004A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_10                               , RULL(0x0005004A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_11_FSI                               , RULL(0x0000284B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_11_FSI_BYTE                          , RULL(0x0000292C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_11_SCOM                              , RULL(0x0005004B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_11                               , RULL(0x0005004B), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_12_FSI                               , RULL(0x0000284C), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_12_FSI_BYTE                          , RULL(0x00002930), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_12_SCOM                              , RULL(0x0005004C), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_12                               , RULL(0x0005004C), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_13_FSI                               , RULL(0x0000284D), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_13_FSI_BYTE                          , RULL(0x00002934), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_13_SCOM                              , RULL(0x0005004D), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_13                               , RULL(0x0005004D), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_14_FSI                               , RULL(0x0000284E), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_14_FSI_BYTE                          , RULL(0x00002938), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_14_SCOM                              , RULL(0x0005004E), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_14                               , RULL(0x0005004E), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_15_FSI                               , RULL(0x0000284F), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_15_FSI_BYTE                          , RULL(0x0000293C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_15_SCOM                              , RULL(0x0005004F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_15                               , RULL(0x0005004F), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_2_FSI                                , RULL(0x00002842), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_2_FSI_BYTE                           , RULL(0x00002908), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_2_SCOM                               , RULL(0x00050042), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_2                                , RULL(0x00050042), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_3_FSI                                , RULL(0x00002843), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_3_FSI_BYTE                           , RULL(0x0000290C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_3_SCOM                               , RULL(0x00050043), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_3                                , RULL(0x00050043), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_4_FSI                                , RULL(0x00002844), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_4_FSI_BYTE                           , RULL(0x00002910), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_4_SCOM                               , RULL(0x00050044), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_4                                , RULL(0x00050044), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_5_FSI                                , RULL(0x00002845), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_5_FSI_BYTE                           , RULL(0x00002914), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_5_SCOM                               , RULL(0x00050045), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_5                                , RULL(0x00050045), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_6_FSI                                , RULL(0x00002846), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_6_FSI_BYTE                           , RULL(0x00002918), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_6_SCOM                               , RULL(0x00050046), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_6                                , RULL(0x00050046), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_7_FSI                                , RULL(0x00002847), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_7_FSI_BYTE                           , RULL(0x0000291C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_7_SCOM                               , RULL(0x00050047), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_7                                , RULL(0x00050047), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_8_FSI                                , RULL(0x00002848), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_8_FSI_BYTE                           , RULL(0x00002920), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_8_SCOM                               , RULL(0x00050048), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_8                                , RULL(0x00050048), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1A_DATA_AREA_9_FSI                                , RULL(0x00002849), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1A_DATA_AREA_9_FSI_BYTE                           , RULL(0x00002924), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1A_DATA_AREA_9_SCOM                               , RULL(0x00050049), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1A_DATA_AREA_9                                , RULL(0x00050049), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_0_FSI                                , RULL(0x00002880), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_0_FSI_BYTE                           , RULL(0x00002A00), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_0_SCOM                               , RULL(0x00050080), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_0                                , RULL(0x00050080), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_1_FSI                                , RULL(0x00002881), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_1_FSI_BYTE                           , RULL(0x00002A04), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_1_SCOM                               , RULL(0x00050081), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_1                                , RULL(0x00050081), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_10_FSI                               , RULL(0x0000288A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_10_FSI_BYTE                          , RULL(0x00002A28), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_10_SCOM                              , RULL(0x0005008A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_10                               , RULL(0x0005008A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_11_FSI                               , RULL(0x0000288B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_11_FSI_BYTE                          , RULL(0x00002A2C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_11_SCOM                              , RULL(0x0005008B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_11                               , RULL(0x0005008B), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_12_FSI                               , RULL(0x0000288C), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_12_FSI_BYTE                          , RULL(0x00002A30), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_12_SCOM                              , RULL(0x0005008C), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_12                               , RULL(0x0005008C), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_13_FSI                               , RULL(0x0000288D), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_13_FSI_BYTE                          , RULL(0x00002A34), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_13_SCOM                              , RULL(0x0005008D), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_13                               , RULL(0x0005008D), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_14_FSI                               , RULL(0x0000288E), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_14_FSI_BYTE                          , RULL(0x00002A38), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_14_SCOM                              , RULL(0x0005008E), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_14                               , RULL(0x0005008E), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_15_FSI                               , RULL(0x0000288F), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_15_FSI_BYTE                          , RULL(0x00002A3C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_15_SCOM                              , RULL(0x0005008F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_15                               , RULL(0x0005008F), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_2_FSI                                , RULL(0x00002882), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_2_FSI_BYTE                           , RULL(0x00002A08), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_2_SCOM                               , RULL(0x00050082), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_2                                , RULL(0x00050082), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_3_FSI                                , RULL(0x00002883), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_3_FSI_BYTE                           , RULL(0x00002A0C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_3_SCOM                               , RULL(0x00050083), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_3                                , RULL(0x00050083), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_4_FSI                                , RULL(0x00002884), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_4_FSI_BYTE                           , RULL(0x00002A10), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_4_SCOM                               , RULL(0x00050084), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_4                                , RULL(0x00050084), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_5_FSI                                , RULL(0x00002885), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_5_FSI_BYTE                           , RULL(0x00002A14), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_5_SCOM                               , RULL(0x00050085), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_5                                , RULL(0x00050085), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_6_FSI                                , RULL(0x00002886), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_6_FSI_BYTE                           , RULL(0x00002A18), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_6_SCOM                               , RULL(0x00050086), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_6                                , RULL(0x00050086), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_7_FSI                                , RULL(0x00002887), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_7_FSI_BYTE                           , RULL(0x00002A1C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_7_SCOM                               , RULL(0x00050087), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_7                                , RULL(0x00050087), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_8_FSI                                , RULL(0x00002888), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_8_FSI_BYTE                           , RULL(0x00002A20), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_8_SCOM                               , RULL(0x00050088), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_8                                , RULL(0x00050088), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M1B_DATA_AREA_9_FSI                                , RULL(0x00002889), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M1B_DATA_AREA_9_FSI_BYTE                           , RULL(0x00002A24), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M1B_DATA_AREA_9_SCOM                               , RULL(0x00050089), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M1B_DATA_AREA_9                                , RULL(0x00050089), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_0_FSI                                , RULL(0x000028C0), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_0_FSI_BYTE                           , RULL(0x00002B00), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_0_SCOM                               , RULL(0x000500C0), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_0                                , RULL(0x000500C0), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_1_FSI                                , RULL(0x000028C1), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_1_FSI_BYTE                           , RULL(0x00002B04), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_1_SCOM                               , RULL(0x000500C1), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_1                                , RULL(0x000500C1), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_10_FSI                               , RULL(0x000028CA), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_10_FSI_BYTE                          , RULL(0x00002B28), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_10_SCOM                              , RULL(0x000500CA), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_10                               , RULL(0x000500CA), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_11_FSI                               , RULL(0x000028CB), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_11_FSI_BYTE                          , RULL(0x00002B2C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_11_SCOM                              , RULL(0x000500CB), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_11                               , RULL(0x000500CB), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_12_FSI                               , RULL(0x000028CC), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_12_FSI_BYTE                          , RULL(0x00002B30), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_12_SCOM                              , RULL(0x000500CC), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_12                               , RULL(0x000500CC), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_13_FSI                               , RULL(0x000028CD), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_13_FSI_BYTE                          , RULL(0x00002B34), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_13_SCOM                              , RULL(0x000500CD), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_13                               , RULL(0x000500CD), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_14_FSI                               , RULL(0x000028CE), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_14_FSI_BYTE                          , RULL(0x00002B38), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_14_SCOM                              , RULL(0x000500CE), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_14                               , RULL(0x000500CE), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_15_FSI                               , RULL(0x000028CF), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_15_FSI_BYTE                          , RULL(0x00002B3C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_15_SCOM                              , RULL(0x000500CF), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_15                               , RULL(0x000500CF), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_2_FSI                                , RULL(0x000028C2), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_2_FSI_BYTE                           , RULL(0x00002B08), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_2_SCOM                               , RULL(0x000500C2), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_2                                , RULL(0x000500C2), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_3_FSI                                , RULL(0x000028C3), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_3_FSI_BYTE                           , RULL(0x00002B0C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_3_SCOM                               , RULL(0x000500C3), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_3                                , RULL(0x000500C3), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_4_FSI                                , RULL(0x000028C4), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_4_FSI_BYTE                           , RULL(0x00002B10), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_4_SCOM                               , RULL(0x000500C4), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_4                                , RULL(0x000500C4), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_5_FSI                                , RULL(0x000028C5), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_5_FSI_BYTE                           , RULL(0x00002B14), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_5_SCOM                               , RULL(0x000500C5), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_5                                , RULL(0x000500C5), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_6_FSI                                , RULL(0x000028C6), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_6_FSI_BYTE                           , RULL(0x00002B18), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_6_SCOM                               , RULL(0x000500C6), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_6                                , RULL(0x000500C6), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_7_FSI                                , RULL(0x000028C7), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_7_FSI_BYTE                           , RULL(0x00002B1C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_7_SCOM                               , RULL(0x000500C7), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_7                                , RULL(0x000500C7), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_8_FSI                                , RULL(0x000028C8), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_8_FSI_BYTE                           , RULL(0x00002B20), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_8_SCOM                               , RULL(0x000500C8), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_8                                , RULL(0x000500C8), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2A_DATA_AREA_9_FSI                                , RULL(0x000028C9), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2A_DATA_AREA_9_FSI_BYTE                           , RULL(0x00002B24), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2A_DATA_AREA_9_SCOM                               , RULL(0x000500C9), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2A_DATA_AREA_9                                , RULL(0x000500C9), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_0_FSI                                , RULL(0x00002900), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_0_FSI_BYTE                           , RULL(0x00002C00), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_0_SCOM                               , RULL(0x00050100), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_0                                , RULL(0x00050100), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_1_FSI                                , RULL(0x00002901), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_1_FSI_BYTE                           , RULL(0x00002C04), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_1_SCOM                               , RULL(0x00050101), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_1                                , RULL(0x00050101), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_10_FSI                               , RULL(0x0000290A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_10_FSI_BYTE                          , RULL(0x00002C28), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_10_SCOM                              , RULL(0x0005010A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_10                               , RULL(0x0005010A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_11_FSI                               , RULL(0x0000290B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_11_FSI_BYTE                          , RULL(0x00002C2C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_11_SCOM                              , RULL(0x0005010B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_11                               , RULL(0x0005010B), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_12_FSI                               , RULL(0x0000290C), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_12_FSI_BYTE                          , RULL(0x00002C30), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_12_SCOM                              , RULL(0x0005010C), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_12                               , RULL(0x0005010C), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_13_FSI                               , RULL(0x0000290D), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_13_FSI_BYTE                          , RULL(0x00002C34), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_13_SCOM                              , RULL(0x0005010D), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_13                               , RULL(0x0005010D), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_14_FSI                               , RULL(0x0000290E), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_14_FSI_BYTE                          , RULL(0x00002C38), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_14_SCOM                              , RULL(0x0005010E), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_14                               , RULL(0x0005010E), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_15_FSI                               , RULL(0x0000290F), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_15_FSI_BYTE                          , RULL(0x00002C3C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_15_SCOM                              , RULL(0x0005010F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_15                               , RULL(0x0005010F), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_2_FSI                                , RULL(0x00002902), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_2_FSI_BYTE                           , RULL(0x00002C08), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_2_SCOM                               , RULL(0x00050102), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_2                                , RULL(0x00050102), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_3_FSI                                , RULL(0x00002903), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_3_FSI_BYTE                           , RULL(0x00002C0C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_3_SCOM                               , RULL(0x00050103), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_3                                , RULL(0x00050103), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_4_FSI                                , RULL(0x00002904), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_4_FSI_BYTE                           , RULL(0x00002C10), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_4_SCOM                               , RULL(0x00050104), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_4                                , RULL(0x00050104), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_5_FSI                                , RULL(0x00002905), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_5_FSI_BYTE                           , RULL(0x00002C14), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_5_SCOM                               , RULL(0x00050105), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_5                                , RULL(0x00050105), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_6_FSI                                , RULL(0x00002906), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_6_FSI_BYTE                           , RULL(0x00002C18), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_6_SCOM                               , RULL(0x00050106), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_6                                , RULL(0x00050106), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_7_FSI                                , RULL(0x00002907), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_7_FSI_BYTE                           , RULL(0x00002C1C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_7_SCOM                               , RULL(0x00050107), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_7                                , RULL(0x00050107), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_8_FSI                                , RULL(0x00002908), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_8_FSI_BYTE                           , RULL(0x00002C20), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_8_SCOM                               , RULL(0x00050108), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_8                                , RULL(0x00050108), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_M2B_DATA_AREA_9_FSI                                , RULL(0x00002909), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_M2B_DATA_AREA_9_FSI_BYTE                           , RULL(0x00002C24), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_M2B_DATA_AREA_9_SCOM                               , RULL(0x00050109), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_M2B_DATA_AREA_9                                , RULL(0x00050109), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_MAILBOX_1_HEADER_COMMAND_0_A_FSI                   , RULL(0x00002821), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_0_A_FSI_BYTE              , RULL(0x00002884), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_0_A_SCOM                  , RULL(0x00050021), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_0_A                   , RULL(0x00050021), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG32( PERV_MAILBOX_1_HEADER_COMMAND_0_B_FSI                   , RULL(0x00002825), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_0_B_FSI_BYTE              , RULL(0x00002894), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_0_B_SCOM                  , RULL(0x00050025), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_0_B                   , RULL(0x00050025), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG32( PERV_MAILBOX_1_HEADER_COMMAND_1_A_FSI                   , RULL(0x00002822), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_1_A_FSI_BYTE              , RULL(0x00002888), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_1_A_SCOM                  , RULL(0x00050022), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_1_A                   , RULL(0x00050022), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG32( PERV_MAILBOX_1_HEADER_COMMAND_1_B_FSI                   , RULL(0x00002826), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_1_B_FSI_BYTE              , RULL(0x00002898), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_1_B_SCOM                  , RULL(0x00050026), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_1_B                   , RULL(0x00050026), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG32( PERV_MAILBOX_1_HEADER_COMMAND_2_A_FSI                   , RULL(0x00002823), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_2_A_FSI_BYTE              , RULL(0x0000288C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_2_A_SCOM                  , RULL(0x00050023), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_2_A                   , RULL(0x00050023), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG32( PERV_MAILBOX_1_HEADER_COMMAND_2_B_FSI                   , RULL(0x00002827), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_2_B_FSI_BYTE              , RULL(0x0000289C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_1_HEADER_COMMAND_2_B_SCOM                  , RULL(0x00050027), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MAILBOX_1_HEADER_COMMAND_2_B                   , RULL(0x00050027), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG32( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_FSI    , RULL(0x00002833), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_FSI_BYTE , RULL(0x000028CC), SH_UNT_PERV     ,
+       SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_SCOM   , RULL(0x00050033), SH_UNT_PERV     , SH_ACS_SCOM_WOR  );
+REG64( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_SCOM1  , RULL(0x00050034), SH_UNT_PERV     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_PIB_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_WOR , RULL(0x00050033), SH_UNT_PERV_0   ,
+       SH_ACS_SCOM_WOR  );
+REG64( PERV_PIB_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_CLEAR , RULL(0x00050034), SH_UNT_PERV_0   ,
+       SH_ACS_SCOM1_CLEAR );
+
+REG32( PERV_MAILBOX_2_HEADER_COMMAND_0_A_FSI                   , RULL(0x00002829), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_0_A_FSI_BYTE              , RULL(0x000028A4), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_0_A_SCOM                  , RULL(0x00050029), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_0_A                   , RULL(0x00050029), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG32( PERV_MAILBOX_2_HEADER_COMMAND_0_B_FSI                   , RULL(0x0000282D), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_0_B_FSI_BYTE              , RULL(0x000028B4), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_0_B_SCOM                  , RULL(0x0005002D), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_0_B                   , RULL(0x0005002D), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG32( PERV_MAILBOX_2_HEADER_COMMAND_1_A_FSI                   , RULL(0x0000282A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_1_A_FSI_BYTE              , RULL(0x000028A8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_1_A_SCOM                  , RULL(0x0005002A), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_1_A                   , RULL(0x0005002A), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG32( PERV_MAILBOX_2_HEADER_COMMAND_1_B_FSI                   , RULL(0x0000282E), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_1_B_FSI_BYTE              , RULL(0x000028B8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_1_B_SCOM                  , RULL(0x0005002E), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_1_B                   , RULL(0x0005002E), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG32( PERV_MAILBOX_2_HEADER_COMMAND_2_A_FSI                   , RULL(0x0000282B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_2_A_FSI_BYTE              , RULL(0x000028AC), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_2_A_SCOM                  , RULL(0x0005002B), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_2_A                   , RULL(0x0005002B), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG32( PERV_MAILBOX_2_HEADER_COMMAND_2_B_FSI                   , RULL(0x0000282F), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_2_B_FSI_BYTE              , RULL(0x000028BC), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_2_HEADER_COMMAND_2_B_SCOM                  , RULL(0x0005002F), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MAILBOX_2_HEADER_COMMAND_2_B                   , RULL(0x0005002F), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG32( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_FSI          , RULL(0x00002831), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_FSI_BYTE     , RULL(0x000028C4), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_SCOM         , RULL(0x00050031), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS          , RULL(0x00050031), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_FSI             , RULL(0x00002832), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_FSI_BYTE        , RULL(0x000028C8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_SCOM            , RULL(0x00050032), SH_UNT_PERV     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_PIB_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT             , RULL(0x00050032), SH_UNT_PERV_0   ,
+       SH_ACS_SCOM_WCLEAR );
+
+REG32( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_FSI          , RULL(0x00002830), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_FSI_BYTE     , RULL(0x000028C0), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_SCOM         , RULL(0x00050030), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS          , RULL(0x00050030), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_FSI             , RULL(0x00002835), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_FSI_BYTE        , RULL(0x000028D4), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_SCOM            , RULL(0x00050035), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT             , RULL(0x00050035), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_FSI      , RULL(0x00002836), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_FSI0     , RULL(0x00002837), SH_UNT_PERV     , SH_ACS_FSI0      );
+REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_FSI_BYTE , RULL(0x000028D8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_SCOM     , RULL(0x00050036), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1      , RULL(0x00050036), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_MCAST_COMP_MASK_REG                                , RULL(0x000F0017), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_COMP_MASK_REG                            , RULL(0x000F0017), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_COMP_REG                                     , RULL(0x000F0015), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_COMP_REG                                 , RULL(0x000F0015), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_COMP_VAL_REG                                 , RULL(0x000F0016), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_COMP_VAL_REG                             , RULL(0x000F0016), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_GRP_0_SLAVES_REG                             , RULL(0x000F0000), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_GRP_0_SLAVES_REG                         , RULL(0x000F0000), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_GRP_1_SLAVES_REG                             , RULL(0x000F0001), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_GRP_1_SLAVES_REG                         , RULL(0x000F0001), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_GRP_2_SLAVES_REG                             , RULL(0x000F0002), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_GRP_2_SLAVES_REG                         , RULL(0x000F0002), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_GRP_3_SLAVES_REG                             , RULL(0x000F0003), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_GRP_3_SLAVES_REG                         , RULL(0x000F0003), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_GRP_4_SLAVES_REG                             , RULL(0x000F0004), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_GRP_4_SLAVES_REG                         , RULL(0x000F0004), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_GRP_5_SLAVES_REG                             , RULL(0x000F0005), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_GRP_5_SLAVES_REG                         , RULL(0x000F0005), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MCAST_GRP_6_SLAVES_REG                             , RULL(0x000F0006), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_MCAST_GRP_6_SLAVES_REG                         , RULL(0x000F0006), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_MODE_REG                                           , RULL(0x00040008), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_MODE_REG                                        , RULL(0x01040008), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_MODE_REG                                        , RULL(0x02040008), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_MODE_REG                                        , RULL(0x03040008), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_MODE_REG                                        , RULL(0x04040008), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_MODE_REG                                        , RULL(0x05040008), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_MODE_REG                                        , RULL(0x06040008), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_MODE_REG                                      , RULL(0x07040008), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_MODE_REG                                      , RULL(0x08040008), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_MODE_REG                                       , RULL(0x09040008), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_MODE_REG                                       , RULL(0x0C040008), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_MODE_REG                                      , RULL(0x0D040008), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_MODE_REG                                      , RULL(0x0E040008), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_MODE_REG                                      , RULL(0x0F040008), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_MODE_REG                                      , RULL(0x10040008), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_MODE_REG                                      , RULL(0x11040008), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_MODE_REG                                      , RULL(0x12040008), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_MODE_REG                                      , RULL(0x13040008), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_MODE_REG                                      , RULL(0x14040008), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_MODE_REG                                      , RULL(0x15040008), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_MODE_REG                                      , RULL(0x20040008), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_MODE_REG                                      , RULL(0x21040008), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_MODE_REG                                      , RULL(0x22040008), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_MODE_REG                                      , RULL(0x23040008), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_MODE_REG                                      , RULL(0x24040008), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_MODE_REG                                      , RULL(0x25040008), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_MODE_REG                                      , RULL(0x26040008), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_MODE_REG                                      , RULL(0x27040008), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_MODE_REG                                      , RULL(0x28040008), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_MODE_REG                                      , RULL(0x29040008), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_MODE_REG                                      , RULL(0x2A040008), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_MODE_REG                                      , RULL(0x2B040008), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_MODE_REG                                      , RULL(0x2C040008), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_MODE_REG                                      , RULL(0x2D040008), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_MODE_REG                                      , RULL(0x2E040008), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_MODE_REG                                      , RULL(0x2F040008), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_MODE_REG                                      , RULL(0x30040008), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_MODE_REG                                      , RULL(0x31040008), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_MODE_REG                                      , RULL(0x32040008), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_MODE_REG                                      , RULL(0x33040008), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_MODE_REG                                      , RULL(0x34040008), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_MODE_REG                                      , RULL(0x35040008), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_MODE_REG                                      , RULL(0x36040008), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_MODE_REG                                      , RULL(0x37040008), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_MODE_REGISTER_A                           , RULL(0x00001802), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      );
+REG32( PERV_FSII2C_MODE_REGISTER_A                             , RULL(0x00001802), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      );
+
+REG64( PERV_MULTICAST_GROUP_1                                  , RULL(0x000F0001), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_TP_MULTICAST_GROUP_1                               , RULL(0x010F0001), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_MULTICAST_GROUP_1                               , RULL(0x020F0001), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_MULTICAST_GROUP_1                               , RULL(0x030F0001), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_MULTICAST_GROUP_1                               , RULL(0x040F0001), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_MULTICAST_GROUP_1                               , RULL(0x050F0001), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_MULTICAST_GROUP_1                               , RULL(0x060F0001), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_MULTICAST_GROUP_1                             , RULL(0x070F0001), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_MULTICAST_GROUP_1                             , RULL(0x080F0001), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_MULTICAST_GROUP_1                              , RULL(0x090F0001), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_MULTICAST_GROUP_1                              , RULL(0x0C0F0001), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_MULTICAST_GROUP_1                             , RULL(0x0D0F0001), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_MULTICAST_GROUP_1                             , RULL(0x0E0F0001), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_MULTICAST_GROUP_1                             , RULL(0x0F0F0001), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_MULTICAST_GROUP_1                             , RULL(0x100F0001), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_MULTICAST_GROUP_1                             , RULL(0x110F0001), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_MULTICAST_GROUP_1                             , RULL(0x120F0001), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_MULTICAST_GROUP_1                             , RULL(0x130F0001), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_MULTICAST_GROUP_1                             , RULL(0x140F0001), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_MULTICAST_GROUP_1                             , RULL(0x150F0001), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_MULTICAST_GROUP_1                             , RULL(0x200F0001), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_MULTICAST_GROUP_1                             , RULL(0x210F0001), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_MULTICAST_GROUP_1                             , RULL(0x220F0001), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_MULTICAST_GROUP_1                             , RULL(0x230F0001), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_MULTICAST_GROUP_1                             , RULL(0x240F0001), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_MULTICAST_GROUP_1                             , RULL(0x250F0001), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_MULTICAST_GROUP_1                             , RULL(0x260F0001), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_MULTICAST_GROUP_1                             , RULL(0x270F0001), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_MULTICAST_GROUP_1                             , RULL(0x280F0001), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_MULTICAST_GROUP_1                             , RULL(0x290F0001), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_MULTICAST_GROUP_1                             , RULL(0x2A0F0001), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_MULTICAST_GROUP_1                             , RULL(0x2B0F0001), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_MULTICAST_GROUP_1                             , RULL(0x2C0F0001), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_MULTICAST_GROUP_1                             , RULL(0x2D0F0001), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_MULTICAST_GROUP_1                             , RULL(0x2E0F0001), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_MULTICAST_GROUP_1                             , RULL(0x2F0F0001), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_MULTICAST_GROUP_1                             , RULL(0x300F0001), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_MULTICAST_GROUP_1                             , RULL(0x310F0001), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_MULTICAST_GROUP_1                             , RULL(0x320F0001), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_MULTICAST_GROUP_1                             , RULL(0x330F0001), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_MULTICAST_GROUP_1                             , RULL(0x340F0001), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_MULTICAST_GROUP_1                             , RULL(0x350F0001), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_MULTICAST_GROUP_1                             , RULL(0x360F0001), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_MULTICAST_GROUP_1                             , RULL(0x370F0001), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_MULTICAST_GROUP_2                                  , RULL(0x000F0002), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_TP_MULTICAST_GROUP_2                               , RULL(0x010F0002), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_MULTICAST_GROUP_2                               , RULL(0x020F0002), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_MULTICAST_GROUP_2                               , RULL(0x030F0002), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_MULTICAST_GROUP_2                               , RULL(0x040F0002), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_MULTICAST_GROUP_2                               , RULL(0x050F0002), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_MULTICAST_GROUP_2                               , RULL(0x060F0002), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_MULTICAST_GROUP_2                             , RULL(0x070F0002), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_MULTICAST_GROUP_2                             , RULL(0x080F0002), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_MULTICAST_GROUP_2                              , RULL(0x090F0002), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_MULTICAST_GROUP_2                              , RULL(0x0C0F0002), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_MULTICAST_GROUP_2                             , RULL(0x0D0F0002), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_MULTICAST_GROUP_2                             , RULL(0x0E0F0002), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_MULTICAST_GROUP_2                             , RULL(0x0F0F0002), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_MULTICAST_GROUP_2                             , RULL(0x100F0002), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_MULTICAST_GROUP_2                             , RULL(0x110F0002), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_MULTICAST_GROUP_2                             , RULL(0x120F0002), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_MULTICAST_GROUP_2                             , RULL(0x130F0002), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_MULTICAST_GROUP_2                             , RULL(0x140F0002), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_MULTICAST_GROUP_2                             , RULL(0x150F0002), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_MULTICAST_GROUP_2                             , RULL(0x200F0002), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_MULTICAST_GROUP_2                             , RULL(0x210F0002), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_MULTICAST_GROUP_2                             , RULL(0x220F0002), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_MULTICAST_GROUP_2                             , RULL(0x230F0002), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_MULTICAST_GROUP_2                             , RULL(0x240F0002), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_MULTICAST_GROUP_2                             , RULL(0x250F0002), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_MULTICAST_GROUP_2                             , RULL(0x260F0002), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_MULTICAST_GROUP_2                             , RULL(0x270F0002), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_MULTICAST_GROUP_2                             , RULL(0x280F0002), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_MULTICAST_GROUP_2                             , RULL(0x290F0002), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_MULTICAST_GROUP_2                             , RULL(0x2A0F0002), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_MULTICAST_GROUP_2                             , RULL(0x2B0F0002), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_MULTICAST_GROUP_2                             , RULL(0x2C0F0002), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_MULTICAST_GROUP_2                             , RULL(0x2D0F0002), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_MULTICAST_GROUP_2                             , RULL(0x2E0F0002), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_MULTICAST_GROUP_2                             , RULL(0x2F0F0002), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_MULTICAST_GROUP_2                             , RULL(0x300F0002), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_MULTICAST_GROUP_2                             , RULL(0x310F0002), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_MULTICAST_GROUP_2                             , RULL(0x320F0002), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_MULTICAST_GROUP_2                             , RULL(0x330F0002), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_MULTICAST_GROUP_2                             , RULL(0x340F0002), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_MULTICAST_GROUP_2                             , RULL(0x350F0002), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_MULTICAST_GROUP_2                             , RULL(0x360F0002), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_MULTICAST_GROUP_2                             , RULL(0x370F0002), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_MULTICAST_GROUP_3                                  , RULL(0x000F0003), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_TP_MULTICAST_GROUP_3                               , RULL(0x010F0003), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_MULTICAST_GROUP_3                               , RULL(0x020F0003), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_MULTICAST_GROUP_3                               , RULL(0x030F0003), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_MULTICAST_GROUP_3                               , RULL(0x040F0003), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_MULTICAST_GROUP_3                               , RULL(0x050F0003), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_MULTICAST_GROUP_3                               , RULL(0x060F0003), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_MULTICAST_GROUP_3                             , RULL(0x070F0003), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_MULTICAST_GROUP_3                             , RULL(0x080F0003), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_MULTICAST_GROUP_3                              , RULL(0x090F0003), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_MULTICAST_GROUP_3                              , RULL(0x0C0F0003), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_MULTICAST_GROUP_3                             , RULL(0x0D0F0003), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_MULTICAST_GROUP_3                             , RULL(0x0E0F0003), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_MULTICAST_GROUP_3                             , RULL(0x0F0F0003), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_MULTICAST_GROUP_3                             , RULL(0x100F0003), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_MULTICAST_GROUP_3                             , RULL(0x110F0003), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_MULTICAST_GROUP_3                             , RULL(0x120F0003), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_MULTICAST_GROUP_3                             , RULL(0x130F0003), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_MULTICAST_GROUP_3                             , RULL(0x140F0003), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_MULTICAST_GROUP_3                             , RULL(0x150F0003), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_MULTICAST_GROUP_3                             , RULL(0x200F0003), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_MULTICAST_GROUP_3                             , RULL(0x210F0003), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_MULTICAST_GROUP_3                             , RULL(0x220F0003), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_MULTICAST_GROUP_3                             , RULL(0x230F0003), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_MULTICAST_GROUP_3                             , RULL(0x240F0003), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_MULTICAST_GROUP_3                             , RULL(0x250F0003), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_MULTICAST_GROUP_3                             , RULL(0x260F0003), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_MULTICAST_GROUP_3                             , RULL(0x270F0003), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_MULTICAST_GROUP_3                             , RULL(0x280F0003), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_MULTICAST_GROUP_3                             , RULL(0x290F0003), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_MULTICAST_GROUP_3                             , RULL(0x2A0F0003), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_MULTICAST_GROUP_3                             , RULL(0x2B0F0003), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_MULTICAST_GROUP_3                             , RULL(0x2C0F0003), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_MULTICAST_GROUP_3                             , RULL(0x2D0F0003), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_MULTICAST_GROUP_3                             , RULL(0x2E0F0003), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_MULTICAST_GROUP_3                             , RULL(0x2F0F0003), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_MULTICAST_GROUP_3                             , RULL(0x300F0003), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_MULTICAST_GROUP_3                             , RULL(0x310F0003), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_MULTICAST_GROUP_3                             , RULL(0x320F0003), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_MULTICAST_GROUP_3                             , RULL(0x330F0003), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_MULTICAST_GROUP_3                             , RULL(0x340F0003), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_MULTICAST_GROUP_3                             , RULL(0x350F0003), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_MULTICAST_GROUP_3                             , RULL(0x360F0003), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_MULTICAST_GROUP_3                             , RULL(0x370F0003), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_MULTICAST_GROUP_4                                  , RULL(0x000F0004), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_TP_MULTICAST_GROUP_4                               , RULL(0x010F0004), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_MULTICAST_GROUP_4                               , RULL(0x020F0004), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_MULTICAST_GROUP_4                               , RULL(0x030F0004), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_MULTICAST_GROUP_4                               , RULL(0x040F0004), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_MULTICAST_GROUP_4                               , RULL(0x050F0004), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_MULTICAST_GROUP_4                               , RULL(0x060F0004), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_MULTICAST_GROUP_4                             , RULL(0x070F0004), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_MULTICAST_GROUP_4                             , RULL(0x080F0004), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_MULTICAST_GROUP_4                              , RULL(0x090F0004), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_MULTICAST_GROUP_4                              , RULL(0x0C0F0004), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_MULTICAST_GROUP_4                             , RULL(0x0D0F0004), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_MULTICAST_GROUP_4                             , RULL(0x0E0F0004), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_MULTICAST_GROUP_4                             , RULL(0x0F0F0004), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_MULTICAST_GROUP_4                             , RULL(0x100F0004), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_MULTICAST_GROUP_4                             , RULL(0x110F0004), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_MULTICAST_GROUP_4                             , RULL(0x120F0004), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_MULTICAST_GROUP_4                             , RULL(0x130F0004), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_MULTICAST_GROUP_4                             , RULL(0x140F0004), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_MULTICAST_GROUP_4                             , RULL(0x150F0004), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_MULTICAST_GROUP_4                             , RULL(0x200F0004), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_MULTICAST_GROUP_4                             , RULL(0x210F0004), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_MULTICAST_GROUP_4                             , RULL(0x220F0004), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_MULTICAST_GROUP_4                             , RULL(0x230F0004), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_MULTICAST_GROUP_4                             , RULL(0x240F0004), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_MULTICAST_GROUP_4                             , RULL(0x250F0004), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_MULTICAST_GROUP_4                             , RULL(0x260F0004), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_MULTICAST_GROUP_4                             , RULL(0x270F0004), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_MULTICAST_GROUP_4                             , RULL(0x280F0004), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_MULTICAST_GROUP_4                             , RULL(0x290F0004), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_MULTICAST_GROUP_4                             , RULL(0x2A0F0004), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_MULTICAST_GROUP_4                             , RULL(0x2B0F0004), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_MULTICAST_GROUP_4                             , RULL(0x2C0F0004), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_MULTICAST_GROUP_4                             , RULL(0x2D0F0004), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_MULTICAST_GROUP_4                             , RULL(0x2E0F0004), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_MULTICAST_GROUP_4                             , RULL(0x2F0F0004), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_MULTICAST_GROUP_4                             , RULL(0x300F0004), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_MULTICAST_GROUP_4                             , RULL(0x310F0004), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_MULTICAST_GROUP_4                             , RULL(0x320F0004), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_MULTICAST_GROUP_4                             , RULL(0x330F0004), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_MULTICAST_GROUP_4                             , RULL(0x340F0004), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_MULTICAST_GROUP_4                             , RULL(0x350F0004), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_MULTICAST_GROUP_4                             , RULL(0x360F0004), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_MULTICAST_GROUP_4                             , RULL(0x370F0004), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_NET_CTRL0                                          , RULL(0x000F0040), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_NET_CTRL0                                       , RULL(0x010F0040), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_NET_CTRL0_WAND                                     , RULL(0x000F0041), SH_UNT_PERV     ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_TP_NET_CTRL0_WAND                                  , RULL(0x010F0041), SH_UNT_PERV_1   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_NET_CTRL0_WOR                                      , RULL(0x000F0042), SH_UNT_PERV     , SH_ACS_SCOM2_WOR );
+REG64( PERV_TP_NET_CTRL0_WOR                                   , RULL(0x010F0042), SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N0_NET_CTRL0                                       , RULL(0x020F0040), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_NET_CTRL0_WAND                                  , RULL(0x020F0041), SH_UNT_PERV_2   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_N0_NET_CTRL0_WOR                                   , RULL(0x020F0042), SH_UNT_PERV_2   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N1_NET_CTRL0                                       , RULL(0x030F0040), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_NET_CTRL0_WAND                                  , RULL(0x030F0041), SH_UNT_PERV_3   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_N1_NET_CTRL0_WOR                                   , RULL(0x030F0042), SH_UNT_PERV_3   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N2_NET_CTRL0                                       , RULL(0x040F0040), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_NET_CTRL0_WAND                                  , RULL(0x040F0041), SH_UNT_PERV_4   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_N2_NET_CTRL0_WOR                                   , RULL(0x040F0042), SH_UNT_PERV_4   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N3_NET_CTRL0                                       , RULL(0x050F0040), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_NET_CTRL0_WAND                                  , RULL(0x050F0041), SH_UNT_PERV_5   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_N3_NET_CTRL0_WOR                                   , RULL(0x050F0042), SH_UNT_PERV_5   , SH_ACS_SCOM2_WOR );
+REG64( PERV_XB_NET_CTRL0                                       , RULL(0x060F0040), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_NET_CTRL0_WAND                                  , RULL(0x060F0041), SH_UNT_PERV_6   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_XB_NET_CTRL0_WOR                                   , RULL(0x060F0042), SH_UNT_PERV_6   , SH_ACS_SCOM2_WOR );
+REG64( PERV_MC01_NET_CTRL0                                     , RULL(0x070F0040), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_NET_CTRL0_WAND                                , RULL(0x070F0041), SH_UNT_PERV_7   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_MC01_NET_CTRL0_WOR                                 , RULL(0x070F0042), SH_UNT_PERV_7   , SH_ACS_SCOM2_WOR );
+REG64( PERV_MC23_NET_CTRL0                                     , RULL(0x080F0040), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_NET_CTRL0_WAND                                , RULL(0x080F0041), SH_UNT_PERV_8   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_MC23_NET_CTRL0_WOR                                 , RULL(0x080F0042), SH_UNT_PERV_8   , SH_ACS_SCOM2_WOR );
+REG64( PERV_OB0_NET_CTRL0                                      , RULL(0x090F0040), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_NET_CTRL0_WAND                                 , RULL(0x090F0041), SH_UNT_PERV_9   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_OB0_NET_CTRL0_WOR                                  , RULL(0x090F0042), SH_UNT_PERV_9   , SH_ACS_SCOM2_WOR );
+REG64( PERV_OB3_NET_CTRL0                                      , RULL(0x0C0F0040), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_NET_CTRL0_WAND                                 , RULL(0x0C0F0041), SH_UNT_PERV_12  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_OB3_NET_CTRL0_WOR                                  , RULL(0x0C0F0042), SH_UNT_PERV_12  , SH_ACS_SCOM2_WOR );
+REG64( PERV_PCI0_NET_CTRL0                                     , RULL(0x0D0F0040), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_NET_CTRL0_WAND                                , RULL(0x0D0F0041), SH_UNT_PERV_13  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_PCI0_NET_CTRL0_WOR                                 , RULL(0x0D0F0042), SH_UNT_PERV_13  , SH_ACS_SCOM2_WOR );
+REG64( PERV_PCI1_NET_CTRL0                                     , RULL(0x0E0F0040), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_NET_CTRL0_WAND                                , RULL(0x0E0F0041), SH_UNT_PERV_14  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_PCI1_NET_CTRL0_WOR                                 , RULL(0x0E0F0042), SH_UNT_PERV_14  , SH_ACS_SCOM2_WOR );
+REG64( PERV_PCI2_NET_CTRL0                                     , RULL(0x0F0F0040), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_NET_CTRL0_WAND                                , RULL(0x0F0F0041), SH_UNT_PERV_15  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_PCI2_NET_CTRL0_WOR                                 , RULL(0x0F0F0042), SH_UNT_PERV_15  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP00_NET_CTRL0                                     , RULL(0x100F0040), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_NET_CTRL0_WAND                                , RULL(0x100F0041), SH_UNT_PERV_16  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EP00_NET_CTRL0_WOR                                 , RULL(0x100F0042), SH_UNT_PERV_16  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP01_NET_CTRL0                                     , RULL(0x110F0040), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_NET_CTRL0_WAND                                , RULL(0x110F0041), SH_UNT_PERV_17  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EP01_NET_CTRL0_WOR                                 , RULL(0x110F0042), SH_UNT_PERV_17  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP02_NET_CTRL0                                     , RULL(0x120F0040), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_NET_CTRL0_WAND                                , RULL(0x120F0041), SH_UNT_PERV_18  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EP02_NET_CTRL0_WOR                                 , RULL(0x120F0042), SH_UNT_PERV_18  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP03_NET_CTRL0                                     , RULL(0x130F0040), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_NET_CTRL0_WAND                                , RULL(0x130F0041), SH_UNT_PERV_19  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EP03_NET_CTRL0_WOR                                 , RULL(0x130F0042), SH_UNT_PERV_19  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP04_NET_CTRL0                                     , RULL(0x140F0040), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_NET_CTRL0_WAND                                , RULL(0x140F0041), SH_UNT_PERV_20  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EP04_NET_CTRL0_WOR                                 , RULL(0x140F0042), SH_UNT_PERV_20  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP05_NET_CTRL0                                     , RULL(0x150F0040), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_NET_CTRL0_WAND                                , RULL(0x150F0041), SH_UNT_PERV_21  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EP05_NET_CTRL0_WOR                                 , RULL(0x150F0042), SH_UNT_PERV_21  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC00_NET_CTRL0                                     , RULL(0x200F0040), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_NET_CTRL0_WAND                                , RULL(0x200F0041), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC00_NET_CTRL0_WOR                                 , RULL(0x200F0042), SH_UNT_PERV_32  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC01_NET_CTRL0                                     , RULL(0x210F0040), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_NET_CTRL0_WAND                                , RULL(0x210F0041), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC01_NET_CTRL0_WOR                                 , RULL(0x210F0042), SH_UNT_PERV_33  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC02_NET_CTRL0                                     , RULL(0x220F0040), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_NET_CTRL0_WAND                                , RULL(0x220F0041), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC02_NET_CTRL0_WOR                                 , RULL(0x220F0042), SH_UNT_PERV_34  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC03_NET_CTRL0                                     , RULL(0x230F0040), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_NET_CTRL0_WAND                                , RULL(0x230F0041), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC03_NET_CTRL0_WOR                                 , RULL(0x230F0042), SH_UNT_PERV_35  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC04_NET_CTRL0                                     , RULL(0x240F0040), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_NET_CTRL0_WAND                                , RULL(0x240F0041), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC04_NET_CTRL0_WOR                                 , RULL(0x240F0042), SH_UNT_PERV_36  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC05_NET_CTRL0                                     , RULL(0x250F0040), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_NET_CTRL0_WAND                                , RULL(0x250F0041), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC05_NET_CTRL0_WOR                                 , RULL(0x250F0042), SH_UNT_PERV_37  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC06_NET_CTRL0                                     , RULL(0x260F0040), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_NET_CTRL0_WAND                                , RULL(0x260F0041), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC06_NET_CTRL0_WOR                                 , RULL(0x260F0042), SH_UNT_PERV_38  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC07_NET_CTRL0                                     , RULL(0x270F0040), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_NET_CTRL0_WAND                                , RULL(0x270F0041), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC07_NET_CTRL0_WOR                                 , RULL(0x270F0042), SH_UNT_PERV_39  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC08_NET_CTRL0                                     , RULL(0x280F0040), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_NET_CTRL0_WAND                                , RULL(0x280F0041), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC08_NET_CTRL0_WOR                                 , RULL(0x280F0042), SH_UNT_PERV_40  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC09_NET_CTRL0                                     , RULL(0x290F0040), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_NET_CTRL0_WAND                                , RULL(0x290F0041), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC09_NET_CTRL0_WOR                                 , RULL(0x290F0042), SH_UNT_PERV_41  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC10_NET_CTRL0                                     , RULL(0x2A0F0040), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_NET_CTRL0_WAND                                , RULL(0x2A0F0041), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC10_NET_CTRL0_WOR                                 , RULL(0x2A0F0042), SH_UNT_PERV_42  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC11_NET_CTRL0                                     , RULL(0x2B0F0040), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_NET_CTRL0_WAND                                , RULL(0x2B0F0041), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC11_NET_CTRL0_WOR                                 , RULL(0x2B0F0042), SH_UNT_PERV_43  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC12_NET_CTRL0                                     , RULL(0x2C0F0040), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_NET_CTRL0_WAND                                , RULL(0x2C0F0041), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC12_NET_CTRL0_WOR                                 , RULL(0x2C0F0042), SH_UNT_PERV_44  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC13_NET_CTRL0                                     , RULL(0x2D0F0040), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_NET_CTRL0_WAND                                , RULL(0x2D0F0041), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC13_NET_CTRL0_WOR                                 , RULL(0x2D0F0042), SH_UNT_PERV_45  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC14_NET_CTRL0                                     , RULL(0x2E0F0040), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_NET_CTRL0_WAND                                , RULL(0x2E0F0041), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC14_NET_CTRL0_WOR                                 , RULL(0x2E0F0042), SH_UNT_PERV_46  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC15_NET_CTRL0                                     , RULL(0x2F0F0040), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_NET_CTRL0_WAND                                , RULL(0x2F0F0041), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC15_NET_CTRL0_WOR                                 , RULL(0x2F0F0042), SH_UNT_PERV_47  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC16_NET_CTRL0                                     , RULL(0x300F0040), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_NET_CTRL0_WAND                                , RULL(0x300F0041), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC16_NET_CTRL0_WOR                                 , RULL(0x300F0042), SH_UNT_PERV_48  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC17_NET_CTRL0                                     , RULL(0x310F0040), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_NET_CTRL0_WAND                                , RULL(0x310F0041), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC17_NET_CTRL0_WOR                                 , RULL(0x310F0042), SH_UNT_PERV_49  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC18_NET_CTRL0                                     , RULL(0x320F0040), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_NET_CTRL0_WAND                                , RULL(0x320F0041), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC18_NET_CTRL0_WOR                                 , RULL(0x320F0042), SH_UNT_PERV_50  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC19_NET_CTRL0                                     , RULL(0x330F0040), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_NET_CTRL0_WAND                                , RULL(0x330F0041), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC19_NET_CTRL0_WOR                                 , RULL(0x330F0042), SH_UNT_PERV_51  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC20_NET_CTRL0                                     , RULL(0x340F0040), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_NET_CTRL0_WAND                                , RULL(0x340F0041), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC20_NET_CTRL0_WOR                                 , RULL(0x340F0042), SH_UNT_PERV_52  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC21_NET_CTRL0                                     , RULL(0x350F0040), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_NET_CTRL0_WAND                                , RULL(0x350F0041), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC21_NET_CTRL0_WOR                                 , RULL(0x350F0042), SH_UNT_PERV_53  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC22_NET_CTRL0                                     , RULL(0x360F0040), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_NET_CTRL0_WAND                                , RULL(0x360F0041), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC22_NET_CTRL0_WOR                                 , RULL(0x360F0042), SH_UNT_PERV_54  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC23_NET_CTRL0                                     , RULL(0x370F0040), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_NET_CTRL0_WAND                                , RULL(0x370F0041), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC23_NET_CTRL0_WOR                                 , RULL(0x370F0042), SH_UNT_PERV_55  , SH_ACS_SCOM2_WOR );
+
+REG64( PERV_NET_CTRL1                                          , RULL(0x000F0044), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_NET_CTRL1                                       , RULL(0x010F0044), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_NET_CTRL1_WAND                                     , RULL(0x000F0045), SH_UNT_PERV     ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_TP_NET_CTRL1_WAND                                  , RULL(0x010F0045), SH_UNT_PERV_1   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_NET_CTRL1_WOR                                      , RULL(0x000F0046), SH_UNT_PERV     , SH_ACS_SCOM2_WOR );
+REG64( PERV_TP_NET_CTRL1_WOR                                   , RULL(0x010F0046), SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N0_NET_CTRL1                                       , RULL(0x020F0044), SH_UNT_PERV_2   , SH_ACS_SCOM_RW   );
+REG64( PERV_N0_NET_CTRL1_WAND                                  , RULL(0x020F0045), SH_UNT_PERV_2   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_N0_NET_CTRL1_WOR                                   , RULL(0x020F0046), SH_UNT_PERV_2   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N1_NET_CTRL1                                       , RULL(0x030F0044), SH_UNT_PERV_3   , SH_ACS_SCOM_RW   );
+REG64( PERV_N1_NET_CTRL1_WAND                                  , RULL(0x030F0045), SH_UNT_PERV_3   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_N1_NET_CTRL1_WOR                                   , RULL(0x030F0046), SH_UNT_PERV_3   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N2_NET_CTRL1                                       , RULL(0x040F0044), SH_UNT_PERV_4   , SH_ACS_SCOM_RW   );
+REG64( PERV_N2_NET_CTRL1_WAND                                  , RULL(0x040F0045), SH_UNT_PERV_4   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_N2_NET_CTRL1_WOR                                   , RULL(0x040F0046), SH_UNT_PERV_4   , SH_ACS_SCOM2_WOR );
+REG64( PERV_N3_NET_CTRL1                                       , RULL(0x050F0044), SH_UNT_PERV_5   , SH_ACS_SCOM_RW   );
+REG64( PERV_N3_NET_CTRL1_WAND                                  , RULL(0x050F0045), SH_UNT_PERV_5   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_N3_NET_CTRL1_WOR                                   , RULL(0x050F0046), SH_UNT_PERV_5   , SH_ACS_SCOM2_WOR );
+REG64( PERV_XB_NET_CTRL1                                       , RULL(0x060F0044), SH_UNT_PERV_6   , SH_ACS_SCOM_RW   );
+REG64( PERV_XB_NET_CTRL1_WAND                                  , RULL(0x060F0045), SH_UNT_PERV_6   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_XB_NET_CTRL1_WOR                                   , RULL(0x060F0046), SH_UNT_PERV_6   , SH_ACS_SCOM2_WOR );
+REG64( PERV_MC01_NET_CTRL1                                     , RULL(0x070F0044), SH_UNT_PERV_7   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC01_NET_CTRL1_WAND                                , RULL(0x070F0045), SH_UNT_PERV_7   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_MC01_NET_CTRL1_WOR                                 , RULL(0x070F0046), SH_UNT_PERV_7   , SH_ACS_SCOM2_WOR );
+REG64( PERV_MC23_NET_CTRL1                                     , RULL(0x080F0044), SH_UNT_PERV_8   , SH_ACS_SCOM_RW   );
+REG64( PERV_MC23_NET_CTRL1_WAND                                , RULL(0x080F0045), SH_UNT_PERV_8   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_MC23_NET_CTRL1_WOR                                 , RULL(0x080F0046), SH_UNT_PERV_8   , SH_ACS_SCOM2_WOR );
+REG64( PERV_OB0_NET_CTRL1                                      , RULL(0x090F0044), SH_UNT_PERV_9   , SH_ACS_SCOM_RW   );
+REG64( PERV_OB0_NET_CTRL1_WAND                                 , RULL(0x090F0045), SH_UNT_PERV_9   ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_OB0_NET_CTRL1_WOR                                  , RULL(0x090F0046), SH_UNT_PERV_9   , SH_ACS_SCOM2_WOR );
+REG64( PERV_OB3_NET_CTRL1                                      , RULL(0x0C0F0044), SH_UNT_PERV_12  , SH_ACS_SCOM_RW   );
+REG64( PERV_OB3_NET_CTRL1_WAND                                 , RULL(0x0C0F0045), SH_UNT_PERV_12  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_OB3_NET_CTRL1_WOR                                  , RULL(0x0C0F0046), SH_UNT_PERV_12  , SH_ACS_SCOM2_WOR );
+REG64( PERV_PCI0_NET_CTRL1                                     , RULL(0x0D0F0044), SH_UNT_PERV_13  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI0_NET_CTRL1_WAND                                , RULL(0x0D0F0045), SH_UNT_PERV_13  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_PCI0_NET_CTRL1_WOR                                 , RULL(0x0D0F0046), SH_UNT_PERV_13  , SH_ACS_SCOM2_WOR );
+REG64( PERV_PCI1_NET_CTRL1                                     , RULL(0x0E0F0044), SH_UNT_PERV_14  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI1_NET_CTRL1_WAND                                , RULL(0x0E0F0045), SH_UNT_PERV_14  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_PCI1_NET_CTRL1_WOR                                 , RULL(0x0E0F0046), SH_UNT_PERV_14  , SH_ACS_SCOM2_WOR );
+REG64( PERV_PCI2_NET_CTRL1                                     , RULL(0x0F0F0044), SH_UNT_PERV_15  , SH_ACS_SCOM_RW   );
+REG64( PERV_PCI2_NET_CTRL1_WAND                                , RULL(0x0F0F0045), SH_UNT_PERV_15  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_PCI2_NET_CTRL1_WOR                                 , RULL(0x0F0F0046), SH_UNT_PERV_15  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP00_NET_CTRL1                                     , RULL(0x100F0044), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_NET_CTRL1_WAND                                , RULL(0x100F0045), SH_UNT_PERV_16  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EP00_NET_CTRL1_WOR                                 , RULL(0x100F0046), SH_UNT_PERV_16  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP01_NET_CTRL1                                     , RULL(0x110F0044), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_NET_CTRL1_WAND                                , RULL(0x110F0045), SH_UNT_PERV_17  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EP01_NET_CTRL1_WOR                                 , RULL(0x110F0046), SH_UNT_PERV_17  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP02_NET_CTRL1                                     , RULL(0x120F0044), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_NET_CTRL1_WAND                                , RULL(0x120F0045), SH_UNT_PERV_18  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EP02_NET_CTRL1_WOR                                 , RULL(0x120F0046), SH_UNT_PERV_18  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP03_NET_CTRL1                                     , RULL(0x130F0044), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_NET_CTRL1_WAND                                , RULL(0x130F0045), SH_UNT_PERV_19  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EP03_NET_CTRL1_WOR                                 , RULL(0x130F0046), SH_UNT_PERV_19  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP04_NET_CTRL1                                     , RULL(0x140F0044), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_NET_CTRL1_WAND                                , RULL(0x140F0045), SH_UNT_PERV_20  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EP04_NET_CTRL1_WOR                                 , RULL(0x140F0046), SH_UNT_PERV_20  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EP05_NET_CTRL1                                     , RULL(0x150F0044), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_NET_CTRL1_WAND                                , RULL(0x150F0045), SH_UNT_PERV_21  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EP05_NET_CTRL1_WOR                                 , RULL(0x150F0046), SH_UNT_PERV_21  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC00_NET_CTRL1                                     , RULL(0x200F0044), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_NET_CTRL1_WAND                                , RULL(0x200F0045), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC00_NET_CTRL1_WOR                                 , RULL(0x200F0046), SH_UNT_PERV_32  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC01_NET_CTRL1                                     , RULL(0x210F0044), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_NET_CTRL1_WAND                                , RULL(0x210F0045), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC01_NET_CTRL1_WOR                                 , RULL(0x210F0046), SH_UNT_PERV_33  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC02_NET_CTRL1                                     , RULL(0x220F0044), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_NET_CTRL1_WAND                                , RULL(0x220F0045), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC02_NET_CTRL1_WOR                                 , RULL(0x220F0046), SH_UNT_PERV_34  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC03_NET_CTRL1                                     , RULL(0x230F0044), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_NET_CTRL1_WAND                                , RULL(0x230F0045), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC03_NET_CTRL1_WOR                                 , RULL(0x230F0046), SH_UNT_PERV_35  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC04_NET_CTRL1                                     , RULL(0x240F0044), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_NET_CTRL1_WAND                                , RULL(0x240F0045), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC04_NET_CTRL1_WOR                                 , RULL(0x240F0046), SH_UNT_PERV_36  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC05_NET_CTRL1                                     , RULL(0x250F0044), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_NET_CTRL1_WAND                                , RULL(0x250F0045), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC05_NET_CTRL1_WOR                                 , RULL(0x250F0046), SH_UNT_PERV_37  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC06_NET_CTRL1                                     , RULL(0x260F0044), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_NET_CTRL1_WAND                                , RULL(0x260F0045), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC06_NET_CTRL1_WOR                                 , RULL(0x260F0046), SH_UNT_PERV_38  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC07_NET_CTRL1                                     , RULL(0x270F0044), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_NET_CTRL1_WAND                                , RULL(0x270F0045), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC07_NET_CTRL1_WOR                                 , RULL(0x270F0046), SH_UNT_PERV_39  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC08_NET_CTRL1                                     , RULL(0x280F0044), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_NET_CTRL1_WAND                                , RULL(0x280F0045), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC08_NET_CTRL1_WOR                                 , RULL(0x280F0046), SH_UNT_PERV_40  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC09_NET_CTRL1                                     , RULL(0x290F0044), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_NET_CTRL1_WAND                                , RULL(0x290F0045), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC09_NET_CTRL1_WOR                                 , RULL(0x290F0046), SH_UNT_PERV_41  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC10_NET_CTRL1                                     , RULL(0x2A0F0044), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_NET_CTRL1_WAND                                , RULL(0x2A0F0045), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC10_NET_CTRL1_WOR                                 , RULL(0x2A0F0046), SH_UNT_PERV_42  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC11_NET_CTRL1                                     , RULL(0x2B0F0044), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_NET_CTRL1_WAND                                , RULL(0x2B0F0045), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC11_NET_CTRL1_WOR                                 , RULL(0x2B0F0046), SH_UNT_PERV_43  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC12_NET_CTRL1                                     , RULL(0x2C0F0044), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_NET_CTRL1_WAND                                , RULL(0x2C0F0045), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC12_NET_CTRL1_WOR                                 , RULL(0x2C0F0046), SH_UNT_PERV_44  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC13_NET_CTRL1                                     , RULL(0x2D0F0044), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_NET_CTRL1_WAND                                , RULL(0x2D0F0045), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC13_NET_CTRL1_WOR                                 , RULL(0x2D0F0046), SH_UNT_PERV_45  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC14_NET_CTRL1                                     , RULL(0x2E0F0044), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_NET_CTRL1_WAND                                , RULL(0x2E0F0045), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC14_NET_CTRL1_WOR                                 , RULL(0x2E0F0046), SH_UNT_PERV_46  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC15_NET_CTRL1                                     , RULL(0x2F0F0044), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_NET_CTRL1_WAND                                , RULL(0x2F0F0045), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC15_NET_CTRL1_WOR                                 , RULL(0x2F0F0046), SH_UNT_PERV_47  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC16_NET_CTRL1                                     , RULL(0x300F0044), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_NET_CTRL1_WAND                                , RULL(0x300F0045), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC16_NET_CTRL1_WOR                                 , RULL(0x300F0046), SH_UNT_PERV_48  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC17_NET_CTRL1                                     , RULL(0x310F0044), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_NET_CTRL1_WAND                                , RULL(0x310F0045), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC17_NET_CTRL1_WOR                                 , RULL(0x310F0046), SH_UNT_PERV_49  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC18_NET_CTRL1                                     , RULL(0x320F0044), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_NET_CTRL1_WAND                                , RULL(0x320F0045), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC18_NET_CTRL1_WOR                                 , RULL(0x320F0046), SH_UNT_PERV_50  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC19_NET_CTRL1                                     , RULL(0x330F0044), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_NET_CTRL1_WAND                                , RULL(0x330F0045), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC19_NET_CTRL1_WOR                                 , RULL(0x330F0046), SH_UNT_PERV_51  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC20_NET_CTRL1                                     , RULL(0x340F0044), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_NET_CTRL1_WAND                                , RULL(0x340F0045), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC20_NET_CTRL1_WOR                                 , RULL(0x340F0046), SH_UNT_PERV_52  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC21_NET_CTRL1                                     , RULL(0x350F0044), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_NET_CTRL1_WAND                                , RULL(0x350F0045), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC21_NET_CTRL1_WOR                                 , RULL(0x350F0046), SH_UNT_PERV_53  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC22_NET_CTRL1                                     , RULL(0x360F0044), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_NET_CTRL1_WAND                                , RULL(0x360F0045), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC22_NET_CTRL1_WOR                                 , RULL(0x360F0046), SH_UNT_PERV_54  , SH_ACS_SCOM2_WOR );
+REG64( PERV_EC23_NET_CTRL1                                     , RULL(0x370F0044), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_NET_CTRL1_WAND                                , RULL(0x370F0045), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM1_WAND );
+REG64( PERV_EC23_NET_CTRL1_WOR                                 , RULL(0x370F0046), SH_UNT_PERV_55  , SH_ACS_SCOM2_WOR );
+
+REG64( PERV_OCC_SCOM_OCCERRRPT                                 , RULL(0x0001080A), SH_UNT_PERV     ,
+       SH_ACS_SCOM_WCLRPART );
+REG64( PERV_TP_OCC_SCOM_OCCERRRPT                              , RULL(0x0101080A), SH_UNT_PERV_1   ,
+       SH_ACS_SCOM_WCLRPART );
+
+REG64( PERV_OCC_SCOM_OCCLFIR                                   , RULL(0x00010800), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_OCC_SCOM_OCCLFIR                                , RULL(0x01010800), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_OCC_SCOM_OCCLFIR_AND                               , RULL(0x00010801), SH_UNT_PERV     , SH_ACS_SCOM1_AND );
+REG64( PERV_TP_OCC_SCOM_OCCLFIR_AND                            , RULL(0x01010801), SH_UNT_PERV_1   , SH_ACS_SCOM1_AND );
+REG64( PERV_OCC_SCOM_OCCLFIR_OR                                , RULL(0x00010802), SH_UNT_PERV     , SH_ACS_SCOM2_OR  );
+REG64( PERV_TP_OCC_SCOM_OCCLFIR_OR                             , RULL(0x01010802), SH_UNT_PERV_1   , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_OCC_SCOM_OCCLFIRACT0                               , RULL(0x00010806), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_OCC_SCOM_OCCLFIRACT0                            , RULL(0x01010806), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_OCC_SCOM_OCCLFIRACT1                               , RULL(0x00010807), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_OCC_SCOM_OCCLFIRACT1                            , RULL(0x01010807), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_OCC_SCOM_OCCLFIRMASK                               , RULL(0x00010803), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_TP_OCC_SCOM_OCCLFIRMASK                            , RULL(0x01010803), SH_UNT_PERV_1   , SH_ACS_SCOM_RW   );
+REG64( PERV_OCC_SCOM_OCCLFIRMASK_AND                           , RULL(0x00010804), SH_UNT_PERV     , SH_ACS_SCOM1_AND );
+REG64( PERV_TP_OCC_SCOM_OCCLFIRMASK_AND                        , RULL(0x01010804), SH_UNT_PERV_1   , SH_ACS_SCOM1_AND );
+REG64( PERV_OCC_SCOM_OCCLFIRMASK_OR                            , RULL(0x00010805), SH_UNT_PERV     , SH_ACS_SCOM2_OR  );
+REG64( PERV_TP_OCC_SCOM_OCCLFIRMASK_OR                         , RULL(0x01010805), SH_UNT_PERV_1   , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_OPCG_ALIGN                                         , RULL(0x00030001), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_OPCG_ALIGN                                      , RULL(0x01030001), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_OPCG_ALIGN                                      , RULL(0x02030001), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_OPCG_ALIGN                                      , RULL(0x03030001), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_OPCG_ALIGN                                      , RULL(0x04030001), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_OPCG_ALIGN                                      , RULL(0x05030001), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_OPCG_ALIGN                                      , RULL(0x06030001), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_OPCG_ALIGN                                    , RULL(0x07030001), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_OPCG_ALIGN                                    , RULL(0x08030001), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_OPCG_ALIGN                                     , RULL(0x09030001), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_OPCG_ALIGN                                     , RULL(0x0C030001), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_OPCG_ALIGN                                    , RULL(0x0D030001), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_OPCG_ALIGN                                    , RULL(0x0E030001), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_OPCG_ALIGN                                    , RULL(0x0F030001), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_OPCG_ALIGN                                    , RULL(0x10030001), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_OPCG_ALIGN                                    , RULL(0x11030001), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_OPCG_ALIGN                                    , RULL(0x12030001), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_OPCG_ALIGN                                    , RULL(0x13030001), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_OPCG_ALIGN                                    , RULL(0x14030001), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_OPCG_ALIGN                                    , RULL(0x15030001), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_OPCG_ALIGN                                    , RULL(0x20030001), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_OPCG_ALIGN                                    , RULL(0x21030001), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_OPCG_ALIGN                                    , RULL(0x22030001), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_OPCG_ALIGN                                    , RULL(0x23030001), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_OPCG_ALIGN                                    , RULL(0x24030001), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_OPCG_ALIGN                                    , RULL(0x25030001), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_OPCG_ALIGN                                    , RULL(0x26030001), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_OPCG_ALIGN                                    , RULL(0x27030001), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_OPCG_ALIGN                                    , RULL(0x28030001), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_OPCG_ALIGN                                    , RULL(0x29030001), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_OPCG_ALIGN                                    , RULL(0x2A030001), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_OPCG_ALIGN                                    , RULL(0x2B030001), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_OPCG_ALIGN                                    , RULL(0x2C030001), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_OPCG_ALIGN                                    , RULL(0x2D030001), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_OPCG_ALIGN                                    , RULL(0x2E030001), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_OPCG_ALIGN                                    , RULL(0x2F030001), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_OPCG_ALIGN                                    , RULL(0x30030001), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_OPCG_ALIGN                                    , RULL(0x31030001), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_OPCG_ALIGN                                    , RULL(0x32030001), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_OPCG_ALIGN                                    , RULL(0x33030001), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_OPCG_ALIGN                                    , RULL(0x34030001), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_OPCG_ALIGN                                    , RULL(0x35030001), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_OPCG_ALIGN                                    , RULL(0x36030001), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_OPCG_ALIGN                                    , RULL(0x37030001), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_OPCG_CAPT1                                         , RULL(0x00030010), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_OPCG_CAPT1                                      , RULL(0x01030010), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_OPCG_CAPT1                                      , RULL(0x02030010), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_OPCG_CAPT1                                      , RULL(0x03030010), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_OPCG_CAPT1                                      , RULL(0x04030010), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_OPCG_CAPT1                                      , RULL(0x05030010), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_OPCG_CAPT1                                      , RULL(0x06030010), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_OPCG_CAPT1                                    , RULL(0x07030010), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_OPCG_CAPT1                                    , RULL(0x08030010), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_OPCG_CAPT1                                     , RULL(0x09030010), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_OPCG_CAPT1                                     , RULL(0x0C030010), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_OPCG_CAPT1                                    , RULL(0x0D030010), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_OPCG_CAPT1                                    , RULL(0x0E030010), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_OPCG_CAPT1                                    , RULL(0x0F030010), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_OPCG_CAPT1                                    , RULL(0x10030010), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_OPCG_CAPT1                                    , RULL(0x11030010), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_OPCG_CAPT1                                    , RULL(0x12030010), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_OPCG_CAPT1                                    , RULL(0x13030010), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_OPCG_CAPT1                                    , RULL(0x14030010), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_OPCG_CAPT1                                    , RULL(0x15030010), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_OPCG_CAPT1                                    , RULL(0x20030010), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_OPCG_CAPT1                                    , RULL(0x21030010), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_OPCG_CAPT1                                    , RULL(0x22030010), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_OPCG_CAPT1                                    , RULL(0x23030010), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_OPCG_CAPT1                                    , RULL(0x24030010), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_OPCG_CAPT1                                    , RULL(0x25030010), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_OPCG_CAPT1                                    , RULL(0x26030010), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_OPCG_CAPT1                                    , RULL(0x27030010), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_OPCG_CAPT1                                    , RULL(0x28030010), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_OPCG_CAPT1                                    , RULL(0x29030010), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_OPCG_CAPT1                                    , RULL(0x2A030010), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_OPCG_CAPT1                                    , RULL(0x2B030010), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_OPCG_CAPT1                                    , RULL(0x2C030010), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_OPCG_CAPT1                                    , RULL(0x2D030010), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_OPCG_CAPT1                                    , RULL(0x2E030010), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_OPCG_CAPT1                                    , RULL(0x2F030010), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_OPCG_CAPT1                                    , RULL(0x30030010), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_OPCG_CAPT1                                    , RULL(0x31030010), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_OPCG_CAPT1                                    , RULL(0x32030010), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_OPCG_CAPT1                                    , RULL(0x33030010), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_OPCG_CAPT1                                    , RULL(0x34030010), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_OPCG_CAPT1                                    , RULL(0x35030010), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_OPCG_CAPT1                                    , RULL(0x36030010), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_OPCG_CAPT1                                    , RULL(0x37030010), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_OPCG_CAPT2                                         , RULL(0x00030011), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_OPCG_CAPT2                                      , RULL(0x01030011), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_OPCG_CAPT2                                      , RULL(0x02030011), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_OPCG_CAPT2                                      , RULL(0x03030011), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_OPCG_CAPT2                                      , RULL(0x04030011), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_OPCG_CAPT2                                      , RULL(0x05030011), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_OPCG_CAPT2                                      , RULL(0x06030011), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_OPCG_CAPT2                                    , RULL(0x07030011), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_OPCG_CAPT2                                    , RULL(0x08030011), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_OPCG_CAPT2                                     , RULL(0x09030011), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_OPCG_CAPT2                                     , RULL(0x0C030011), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_OPCG_CAPT2                                    , RULL(0x0D030011), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_OPCG_CAPT2                                    , RULL(0x0E030011), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_OPCG_CAPT2                                    , RULL(0x0F030011), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_OPCG_CAPT2                                    , RULL(0x10030011), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_OPCG_CAPT2                                    , RULL(0x11030011), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_OPCG_CAPT2                                    , RULL(0x12030011), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_OPCG_CAPT2                                    , RULL(0x13030011), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_OPCG_CAPT2                                    , RULL(0x14030011), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_OPCG_CAPT2                                    , RULL(0x15030011), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_OPCG_CAPT2                                    , RULL(0x20030011), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_OPCG_CAPT2                                    , RULL(0x21030011), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_OPCG_CAPT2                                    , RULL(0x22030011), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_OPCG_CAPT2                                    , RULL(0x23030011), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_OPCG_CAPT2                                    , RULL(0x24030011), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_OPCG_CAPT2                                    , RULL(0x25030011), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_OPCG_CAPT2                                    , RULL(0x26030011), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_OPCG_CAPT2                                    , RULL(0x27030011), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_OPCG_CAPT2                                    , RULL(0x28030011), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_OPCG_CAPT2                                    , RULL(0x29030011), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_OPCG_CAPT2                                    , RULL(0x2A030011), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_OPCG_CAPT2                                    , RULL(0x2B030011), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_OPCG_CAPT2                                    , RULL(0x2C030011), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_OPCG_CAPT2                                    , RULL(0x2D030011), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_OPCG_CAPT2                                    , RULL(0x2E030011), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_OPCG_CAPT2                                    , RULL(0x2F030011), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_OPCG_CAPT2                                    , RULL(0x30030011), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_OPCG_CAPT2                                    , RULL(0x31030011), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_OPCG_CAPT2                                    , RULL(0x32030011), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_OPCG_CAPT2                                    , RULL(0x33030011), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_OPCG_CAPT2                                    , RULL(0x34030011), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_OPCG_CAPT2                                    , RULL(0x35030011), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_OPCG_CAPT2                                    , RULL(0x36030011), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_OPCG_CAPT2                                    , RULL(0x37030011), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_OPCG_CAPT3                                         , RULL(0x00030012), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_OPCG_CAPT3                                      , RULL(0x01030012), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_OPCG_CAPT3                                      , RULL(0x02030012), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_OPCG_CAPT3                                      , RULL(0x03030012), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_OPCG_CAPT3                                      , RULL(0x04030012), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_OPCG_CAPT3                                      , RULL(0x05030012), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_OPCG_CAPT3                                      , RULL(0x06030012), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_OPCG_CAPT3                                    , RULL(0x07030012), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_OPCG_CAPT3                                    , RULL(0x08030012), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_OPCG_CAPT3                                     , RULL(0x09030012), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_OPCG_CAPT3                                     , RULL(0x0C030012), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_OPCG_CAPT3                                    , RULL(0x0D030012), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_OPCG_CAPT3                                    , RULL(0x0E030012), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_OPCG_CAPT3                                    , RULL(0x0F030012), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_OPCG_CAPT3                                    , RULL(0x10030012), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_OPCG_CAPT3                                    , RULL(0x11030012), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_OPCG_CAPT3                                    , RULL(0x12030012), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_OPCG_CAPT3                                    , RULL(0x13030012), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_OPCG_CAPT3                                    , RULL(0x14030012), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_OPCG_CAPT3                                    , RULL(0x15030012), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_OPCG_CAPT3                                    , RULL(0x20030012), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_OPCG_CAPT3                                    , RULL(0x21030012), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_OPCG_CAPT3                                    , RULL(0x22030012), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_OPCG_CAPT3                                    , RULL(0x23030012), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_OPCG_CAPT3                                    , RULL(0x24030012), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_OPCG_CAPT3                                    , RULL(0x25030012), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_OPCG_CAPT3                                    , RULL(0x26030012), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_OPCG_CAPT3                                    , RULL(0x27030012), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_OPCG_CAPT3                                    , RULL(0x28030012), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_OPCG_CAPT3                                    , RULL(0x29030012), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_OPCG_CAPT3                                    , RULL(0x2A030012), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_OPCG_CAPT3                                    , RULL(0x2B030012), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_OPCG_CAPT3                                    , RULL(0x2C030012), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_OPCG_CAPT3                                    , RULL(0x2D030012), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_OPCG_CAPT3                                    , RULL(0x2E030012), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_OPCG_CAPT3                                    , RULL(0x2F030012), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_OPCG_CAPT3                                    , RULL(0x30030012), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_OPCG_CAPT3                                    , RULL(0x31030012), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_OPCG_CAPT3                                    , RULL(0x32030012), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_OPCG_CAPT3                                    , RULL(0x33030012), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_OPCG_CAPT3                                    , RULL(0x34030012), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_OPCG_CAPT3                                    , RULL(0x35030012), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_OPCG_CAPT3                                    , RULL(0x36030012), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_OPCG_CAPT3                                    , RULL(0x37030012), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_OPCG_REG0                                          , RULL(0x00030002), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_OPCG_REG0                                       , RULL(0x01030002), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_OPCG_REG0                                       , RULL(0x02030002), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_OPCG_REG0                                       , RULL(0x03030002), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_OPCG_REG0                                       , RULL(0x04030002), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_OPCG_REG0                                       , RULL(0x05030002), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_OPCG_REG0                                       , RULL(0x06030002), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_OPCG_REG0                                     , RULL(0x07030002), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_OPCG_REG0                                     , RULL(0x08030002), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_OPCG_REG0                                      , RULL(0x09030002), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_OPCG_REG0                                      , RULL(0x0C030002), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_OPCG_REG0                                     , RULL(0x0D030002), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_OPCG_REG0                                     , RULL(0x0E030002), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_OPCG_REG0                                     , RULL(0x0F030002), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_OPCG_REG0                                     , RULL(0x10030002), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_OPCG_REG0                                     , RULL(0x11030002), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_OPCG_REG0                                     , RULL(0x12030002), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_OPCG_REG0                                     , RULL(0x13030002), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_OPCG_REG0                                     , RULL(0x14030002), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_OPCG_REG0                                     , RULL(0x15030002), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_OPCG_REG0                                     , RULL(0x20030002), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_OPCG_REG0                                     , RULL(0x21030002), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_OPCG_REG0                                     , RULL(0x22030002), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_OPCG_REG0                                     , RULL(0x23030002), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_OPCG_REG0                                     , RULL(0x24030002), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_OPCG_REG0                                     , RULL(0x25030002), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_OPCG_REG0                                     , RULL(0x26030002), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_OPCG_REG0                                     , RULL(0x27030002), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_OPCG_REG0                                     , RULL(0x28030002), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_OPCG_REG0                                     , RULL(0x29030002), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_OPCG_REG0                                     , RULL(0x2A030002), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_OPCG_REG0                                     , RULL(0x2B030002), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_OPCG_REG0                                     , RULL(0x2C030002), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_OPCG_REG0                                     , RULL(0x2D030002), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_OPCG_REG0                                     , RULL(0x2E030002), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_OPCG_REG0                                     , RULL(0x2F030002), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_OPCG_REG0                                     , RULL(0x30030002), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_OPCG_REG0                                     , RULL(0x31030002), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_OPCG_REG0                                     , RULL(0x32030002), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_OPCG_REG0                                     , RULL(0x33030002), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_OPCG_REG0                                     , RULL(0x34030002), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_OPCG_REG0                                     , RULL(0x35030002), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_OPCG_REG0                                     , RULL(0x36030002), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_OPCG_REG0                                     , RULL(0x37030002), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_OPCG_REG1                                          , RULL(0x00030003), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_OPCG_REG1                                       , RULL(0x01030003), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_OPCG_REG1                                       , RULL(0x02030003), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_OPCG_REG1                                       , RULL(0x03030003), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_OPCG_REG1                                       , RULL(0x04030003), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_OPCG_REG1                                       , RULL(0x05030003), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_OPCG_REG1                                       , RULL(0x06030003), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_OPCG_REG1                                     , RULL(0x07030003), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_OPCG_REG1                                     , RULL(0x08030003), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_OPCG_REG1                                      , RULL(0x09030003), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_OPCG_REG1                                      , RULL(0x0C030003), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_OPCG_REG1                                     , RULL(0x0D030003), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_OPCG_REG1                                     , RULL(0x0E030003), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_OPCG_REG1                                     , RULL(0x0F030003), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_OPCG_REG1                                     , RULL(0x10030003), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_OPCG_REG1                                     , RULL(0x11030003), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_OPCG_REG1                                     , RULL(0x12030003), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_OPCG_REG1                                     , RULL(0x13030003), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_OPCG_REG1                                     , RULL(0x14030003), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_OPCG_REG1                                     , RULL(0x15030003), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_OPCG_REG1                                     , RULL(0x20030003), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_OPCG_REG1                                     , RULL(0x21030003), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_OPCG_REG1                                     , RULL(0x22030003), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_OPCG_REG1                                     , RULL(0x23030003), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_OPCG_REG1                                     , RULL(0x24030003), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_OPCG_REG1                                     , RULL(0x25030003), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_OPCG_REG1                                     , RULL(0x26030003), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_OPCG_REG1                                     , RULL(0x27030003), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_OPCG_REG1                                     , RULL(0x28030003), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_OPCG_REG1                                     , RULL(0x29030003), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_OPCG_REG1                                     , RULL(0x2A030003), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_OPCG_REG1                                     , RULL(0x2B030003), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_OPCG_REG1                                     , RULL(0x2C030003), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_OPCG_REG1                                     , RULL(0x2D030003), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_OPCG_REG1                                     , RULL(0x2E030003), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_OPCG_REG1                                     , RULL(0x2F030003), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_OPCG_REG1                                     , RULL(0x30030003), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_OPCG_REG1                                     , RULL(0x31030003), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_OPCG_REG1                                     , RULL(0x32030003), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_OPCG_REG1                                     , RULL(0x33030003), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_OPCG_REG1                                     , RULL(0x34030003), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_OPCG_REG1                                     , RULL(0x35030003), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_OPCG_REG1                                     , RULL(0x36030003), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_OPCG_REG1                                     , RULL(0x37030003), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_OPCG_REG2                                          , RULL(0x00030004), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_OPCG_REG2                                       , RULL(0x01030004), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_OPCG_REG2                                       , RULL(0x02030004), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_OPCG_REG2                                       , RULL(0x03030004), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_OPCG_REG2                                       , RULL(0x04030004), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_OPCG_REG2                                       , RULL(0x05030004), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_OPCG_REG2                                       , RULL(0x06030004), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_OPCG_REG2                                     , RULL(0x07030004), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_OPCG_REG2                                     , RULL(0x08030004), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_OPCG_REG2                                      , RULL(0x09030004), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_OPCG_REG2                                      , RULL(0x0C030004), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_OPCG_REG2                                     , RULL(0x0D030004), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_OPCG_REG2                                     , RULL(0x0E030004), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_OPCG_REG2                                     , RULL(0x0F030004), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_OPCG_REG2                                     , RULL(0x10030004), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_OPCG_REG2                                     , RULL(0x11030004), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_OPCG_REG2                                     , RULL(0x12030004), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_OPCG_REG2                                     , RULL(0x13030004), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_OPCG_REG2                                     , RULL(0x14030004), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_OPCG_REG2                                     , RULL(0x15030004), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_OPCG_REG2                                     , RULL(0x20030004), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_OPCG_REG2                                     , RULL(0x21030004), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_OPCG_REG2                                     , RULL(0x22030004), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_OPCG_REG2                                     , RULL(0x23030004), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_OPCG_REG2                                     , RULL(0x24030004), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_OPCG_REG2                                     , RULL(0x25030004), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_OPCG_REG2                                     , RULL(0x26030004), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_OPCG_REG2                                     , RULL(0x27030004), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_OPCG_REG2                                     , RULL(0x28030004), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_OPCG_REG2                                     , RULL(0x29030004), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_OPCG_REG2                                     , RULL(0x2A030004), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_OPCG_REG2                                     , RULL(0x2B030004), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_OPCG_REG2                                     , RULL(0x2C030004), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_OPCG_REG2                                     , RULL(0x2D030004), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_OPCG_REG2                                     , RULL(0x2E030004), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_OPCG_REG2                                     , RULL(0x2F030004), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_OPCG_REG2                                     , RULL(0x30030004), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_OPCG_REG2                                     , RULL(0x31030004), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_OPCG_REG2                                     , RULL(0x32030004), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_OPCG_REG2                                     , RULL(0x33030004), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_OPCG_REG2                                     , RULL(0x34030004), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_OPCG_REG2                                     , RULL(0x35030004), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_OPCG_REG2                                     , RULL(0x36030004), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_OPCG_REG2                                     , RULL(0x37030004), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_OSCERR_HOLD                                        , RULL(0x00020019), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_OSCERR_HOLD                                     , RULL(0x01020019), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_OSCERR_MASK                                        , RULL(0x0002001A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_OSCERR_MASK                                     , RULL(0x0102001A), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_OSCERR_MCODE                                       , RULL(0x0002001B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_OSCERR_MCODE                                    , RULL(0x0102001B), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG32( PERV_PEEK4A0_FSI                                        , RULL(0x000004A0), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_PEEK4A4_FSI                                        , RULL(0x000004A4), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_PEEK4A8_FSI                                        , RULL(0x000004A8), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_PEEK4AC_FSI                                        , RULL(0x000004AC), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_PEEK4B0_FSI                                        , RULL(0x000004B0), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_PEEK4B4_FSI                                        , RULL(0x000004B4), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_PEEK4B8_FSI                                        , RULL(0x000004B8), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_PERV_CTRL0_FSI                                     , RULL(0x0000281A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_PERV_CTRL0_FSI_BYTE                                , RULL(0x00002868), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_PERV_CTRL0_SCOM                                    , RULL(0x0005001A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_PERV_CTRL0                                     , RULL(0x0005001A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_PERV_CTRL0_CLEAR_FSI                               , RULL(0x0000293A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_PERV_CTRL0_CLEAR_FSI_BYTE                          , RULL(0x00002CE8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_PERV_CTRL0_CLEAR_SCOM                              , RULL(0x0005013A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_PERV_CTRL0_CLEAR                               , RULL(0x0005013A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_PERV_CTRL0_COPY_FSI                                , RULL(0x0000291A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_PERV_CTRL0_COPY_FSI_BYTE                           , RULL(0x00002C68), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_PERV_CTRL0_COPY_SCOM                               , RULL(0x0005011A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_PERV_CTRL0_COPY                                , RULL(0x0005011A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_PERV_CTRL0_SET_FSI                                 , RULL(0x0000292A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_PERV_CTRL0_SET_FSI_BYTE                            , RULL(0x00002CA8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_PERV_CTRL0_SET_SCOM                                , RULL(0x0005012A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_PERV_CTRL0_SET                                 , RULL(0x0005012A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_PERV_CTRL1_FSI                                     , RULL(0x0000281B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_PERV_CTRL1_FSI_BYTE                                , RULL(0x0000286C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_PERV_CTRL1_SCOM                                    , RULL(0x0005001B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_PERV_CTRL1                                     , RULL(0x0005001B), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_PERV_CTRL1_CLEAR_FSI                               , RULL(0x0000293B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_PERV_CTRL1_CLEAR_FSI_BYTE                          , RULL(0x00002CEC), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_PERV_CTRL1_CLEAR_SCOM                              , RULL(0x0005013B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_PERV_CTRL1_CLEAR                               , RULL(0x0005013B), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_PERV_CTRL1_COPY_FSI                                , RULL(0x0000291B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_PERV_CTRL1_COPY_FSI_BYTE                           , RULL(0x00002C6C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_PERV_CTRL1_COPY_SCOM                               , RULL(0x0005011B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_PERV_CTRL1_COPY                                , RULL(0x0005011B), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_PERV_CTRL1_SET_FSI                                 , RULL(0x0000292B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_PERV_CTRL1_SET_FSI_BYTE                            , RULL(0x00002CAC), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_PERV_CTRL1_SET_SCOM                                , RULL(0x0005012B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_PERV_CTRL1_SET                                 , RULL(0x0005012B), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_PLL_LOCK_REG                                       , RULL(0x000F0019), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_PLL_LOCK_REG                                    , RULL(0x010F0019), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_PLL_LOCK_REG                                    , RULL(0x020F0019), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_PLL_LOCK_REG                                    , RULL(0x030F0019), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_PLL_LOCK_REG                                    , RULL(0x040F0019), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_PLL_LOCK_REG                                    , RULL(0x050F0019), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_PLL_LOCK_REG                                    , RULL(0x060F0019), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_PLL_LOCK_REG                                  , RULL(0x070F0019), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_PLL_LOCK_REG                                  , RULL(0x080F0019), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_PLL_LOCK_REG                                   , RULL(0x090F0019), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_PLL_LOCK_REG                                   , RULL(0x0C0F0019), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_PLL_LOCK_REG                                  , RULL(0x0D0F0019), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_PLL_LOCK_REG                                  , RULL(0x0E0F0019), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_PLL_LOCK_REG                                  , RULL(0x0F0F0019), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_PLL_LOCK_REG                                  , RULL(0x100F0019), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PLL_LOCK_REG                                  , RULL(0x110F0019), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PLL_LOCK_REG                                  , RULL(0x120F0019), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PLL_LOCK_REG                                  , RULL(0x130F0019), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PLL_LOCK_REG                                  , RULL(0x140F0019), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PLL_LOCK_REG                                  , RULL(0x150F0019), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PLL_LOCK_REG                                  , RULL(0x200F0019), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PLL_LOCK_REG                                  , RULL(0x210F0019), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PLL_LOCK_REG                                  , RULL(0x220F0019), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PLL_LOCK_REG                                  , RULL(0x230F0019), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PLL_LOCK_REG                                  , RULL(0x240F0019), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PLL_LOCK_REG                                  , RULL(0x250F0019), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PLL_LOCK_REG                                  , RULL(0x260F0019), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PLL_LOCK_REG                                  , RULL(0x270F0019), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PLL_LOCK_REG                                  , RULL(0x280F0019), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PLL_LOCK_REG                                  , RULL(0x290F0019), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PLL_LOCK_REG                                  , RULL(0x2A0F0019), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PLL_LOCK_REG                                  , RULL(0x2B0F0019), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PLL_LOCK_REG                                  , RULL(0x2C0F0019), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PLL_LOCK_REG                                  , RULL(0x2D0F0019), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PLL_LOCK_REG                                  , RULL(0x2E0F0019), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PLL_LOCK_REG                                  , RULL(0x2F0F0019), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PLL_LOCK_REG                                  , RULL(0x300F0019), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PLL_LOCK_REG                                  , RULL(0x310F0019), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PLL_LOCK_REG                                  , RULL(0x320F0019), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PLL_LOCK_REG                                  , RULL(0x330F0019), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PLL_LOCK_REG                                  , RULL(0x340F0019), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PLL_LOCK_REG                                  , RULL(0x350F0019), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PLL_LOCK_REG                                  , RULL(0x360F0019), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PLL_LOCK_REG                                  , RULL(0x370F0019), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EP00_PPM_CGCR                                      , RULL(0x100F0164), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_CGCR                                      , RULL(0x110F0164), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_CGCR                                      , RULL(0x120F0164), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_CGCR                                      , RULL(0x130F0164), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_CGCR                                      , RULL(0x140F0164), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_CGCR                                      , RULL(0x150F0164), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_CGCR                                      , RULL(0x200F0164), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_CGCR                                      , RULL(0x210F0164), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_CGCR                                      , RULL(0x220F0164), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_CGCR                                      , RULL(0x230F0164), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_CGCR                                      , RULL(0x240F0164), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_CGCR                                      , RULL(0x250F0164), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_CGCR                                      , RULL(0x260F0164), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_CGCR                                      , RULL(0x270F0164), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_CGCR                                      , RULL(0x280F0164), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_CGCR                                      , RULL(0x290F0164), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_CGCR                                      , RULL(0x2A0F0164), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_CGCR                                      , RULL(0x2B0F0164), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_CGCR                                      , RULL(0x2C0F0164), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_CGCR                                      , RULL(0x2D0F0164), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_CGCR                                      , RULL(0x2E0F0164), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_CGCR                                      , RULL(0x2F0F0164), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_CGCR                                      , RULL(0x300F0164), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_CGCR                                      , RULL(0x310F0164), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_CGCR                                      , RULL(0x320F0164), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_CGCR                                      , RULL(0x330F0164), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_CGCR                                      , RULL(0x340F0164), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_CGCR                                      , RULL(0x350F0164), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_CGCR                                      , RULL(0x360F0164), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_CGCR                                      , RULL(0x370F0164), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_GPMMR_SCOM                                , RULL(0x100F0100), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP00_PPM_GPMMR_SCOM1                               , RULL(0x100F0101), SH_UNT_PERV_16  , SH_ACS_SCOM1     );
+REG64( PERV_EP00_PPM_GPMMR_SCOM2                               , RULL(0x100F0102), SH_UNT_PERV_16  , SH_ACS_SCOM2     );
+REG64( PERV_EP01_PPM_GPMMR_SCOM                                , RULL(0x110F0100), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_GPMMR_SCOM1                               , RULL(0x110F0101), SH_UNT_PERV_17  , SH_ACS_SCOM1     );
+REG64( PERV_EP01_PPM_GPMMR_SCOM2                               , RULL(0x110F0102), SH_UNT_PERV_17  , SH_ACS_SCOM2     );
+REG64( PERV_EP02_PPM_GPMMR_SCOM                                , RULL(0x120F0100), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_GPMMR_SCOM1                               , RULL(0x120F0101), SH_UNT_PERV_18  , SH_ACS_SCOM1     );
+REG64( PERV_EP02_PPM_GPMMR_SCOM2                               , RULL(0x120F0102), SH_UNT_PERV_18  , SH_ACS_SCOM2     );
+REG64( PERV_EP03_PPM_GPMMR_SCOM                                , RULL(0x130F0100), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_GPMMR_SCOM1                               , RULL(0x130F0101), SH_UNT_PERV_19  , SH_ACS_SCOM1     );
+REG64( PERV_EP03_PPM_GPMMR_SCOM2                               , RULL(0x130F0102), SH_UNT_PERV_19  , SH_ACS_SCOM2     );
+REG64( PERV_EP04_PPM_GPMMR_SCOM                                , RULL(0x140F0100), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_GPMMR_SCOM1                               , RULL(0x140F0101), SH_UNT_PERV_20  , SH_ACS_SCOM1     );
+REG64( PERV_EP04_PPM_GPMMR_SCOM2                               , RULL(0x140F0102), SH_UNT_PERV_20  , SH_ACS_SCOM2     );
+REG64( PERV_EP05_PPM_GPMMR_SCOM                                , RULL(0x150F0100), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_GPMMR_SCOM1                               , RULL(0x150F0101), SH_UNT_PERV_21  , SH_ACS_SCOM1     );
+REG64( PERV_EP05_PPM_GPMMR_SCOM2                               , RULL(0x150F0102), SH_UNT_PERV_21  , SH_ACS_SCOM2     );
+REG64( PERV_EC00_PPM_GPMMR_SCOM                                , RULL(0x200F0100), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_GPMMR_SCOM1                               , RULL(0x200F0101), SH_UNT_PERV_32  , SH_ACS_SCOM1     );
+REG64( PERV_EC00_PPM_GPMMR_SCOM2                               , RULL(0x200F0102), SH_UNT_PERV_32  , SH_ACS_SCOM2     );
+REG64( PERV_EC01_PPM_GPMMR_SCOM                                , RULL(0x210F0100), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_GPMMR_SCOM1                               , RULL(0x210F0101), SH_UNT_PERV_33  , SH_ACS_SCOM1     );
+REG64( PERV_EC01_PPM_GPMMR_SCOM2                               , RULL(0x210F0102), SH_UNT_PERV_33  , SH_ACS_SCOM2     );
+REG64( PERV_EC02_PPM_GPMMR_SCOM                                , RULL(0x220F0100), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_GPMMR_SCOM1                               , RULL(0x220F0101), SH_UNT_PERV_34  , SH_ACS_SCOM1     );
+REG64( PERV_EC02_PPM_GPMMR_SCOM2                               , RULL(0x220F0102), SH_UNT_PERV_34  , SH_ACS_SCOM2     );
+REG64( PERV_EC03_PPM_GPMMR_SCOM                                , RULL(0x230F0100), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_GPMMR_SCOM1                               , RULL(0x230F0101), SH_UNT_PERV_35  , SH_ACS_SCOM1     );
+REG64( PERV_EC03_PPM_GPMMR_SCOM2                               , RULL(0x230F0102), SH_UNT_PERV_35  , SH_ACS_SCOM2     );
+REG64( PERV_EC04_PPM_GPMMR_SCOM                                , RULL(0x240F0100), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_GPMMR_SCOM1                               , RULL(0x240F0101), SH_UNT_PERV_36  , SH_ACS_SCOM1     );
+REG64( PERV_EC04_PPM_GPMMR_SCOM2                               , RULL(0x240F0102), SH_UNT_PERV_36  , SH_ACS_SCOM2     );
+REG64( PERV_EC05_PPM_GPMMR_SCOM                                , RULL(0x250F0100), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_GPMMR_SCOM1                               , RULL(0x250F0101), SH_UNT_PERV_37  , SH_ACS_SCOM1     );
+REG64( PERV_EC05_PPM_GPMMR_SCOM2                               , RULL(0x250F0102), SH_UNT_PERV_37  , SH_ACS_SCOM2     );
+REG64( PERV_EC06_PPM_GPMMR_SCOM                                , RULL(0x260F0100), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_GPMMR_SCOM1                               , RULL(0x260F0101), SH_UNT_PERV_38  , SH_ACS_SCOM1     );
+REG64( PERV_EC06_PPM_GPMMR_SCOM2                               , RULL(0x260F0102), SH_UNT_PERV_38  , SH_ACS_SCOM2     );
+REG64( PERV_EC07_PPM_GPMMR_SCOM                                , RULL(0x270F0100), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_GPMMR_SCOM1                               , RULL(0x270F0101), SH_UNT_PERV_39  , SH_ACS_SCOM1     );
+REG64( PERV_EC07_PPM_GPMMR_SCOM2                               , RULL(0x270F0102), SH_UNT_PERV_39  , SH_ACS_SCOM2     );
+REG64( PERV_EC08_PPM_GPMMR_SCOM                                , RULL(0x280F0100), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_GPMMR_SCOM1                               , RULL(0x280F0101), SH_UNT_PERV_40  , SH_ACS_SCOM1     );
+REG64( PERV_EC08_PPM_GPMMR_SCOM2                               , RULL(0x280F0102), SH_UNT_PERV_40  , SH_ACS_SCOM2     );
+REG64( PERV_EC09_PPM_GPMMR_SCOM                                , RULL(0x290F0100), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_GPMMR_SCOM1                               , RULL(0x290F0101), SH_UNT_PERV_41  , SH_ACS_SCOM1     );
+REG64( PERV_EC09_PPM_GPMMR_SCOM2                               , RULL(0x290F0102), SH_UNT_PERV_41  , SH_ACS_SCOM2     );
+REG64( PERV_EC10_PPM_GPMMR_SCOM                                , RULL(0x2A0F0100), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_GPMMR_SCOM1                               , RULL(0x2A0F0101), SH_UNT_PERV_42  , SH_ACS_SCOM1     );
+REG64( PERV_EC10_PPM_GPMMR_SCOM2                               , RULL(0x2A0F0102), SH_UNT_PERV_42  , SH_ACS_SCOM2     );
+REG64( PERV_EC11_PPM_GPMMR_SCOM                                , RULL(0x2B0F0100), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_GPMMR_SCOM1                               , RULL(0x2B0F0101), SH_UNT_PERV_43  , SH_ACS_SCOM1     );
+REG64( PERV_EC11_PPM_GPMMR_SCOM2                               , RULL(0x2B0F0102), SH_UNT_PERV_43  , SH_ACS_SCOM2     );
+REG64( PERV_EC12_PPM_GPMMR_SCOM                                , RULL(0x2C0F0100), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_GPMMR_SCOM1                               , RULL(0x2C0F0101), SH_UNT_PERV_44  , SH_ACS_SCOM1     );
+REG64( PERV_EC12_PPM_GPMMR_SCOM2                               , RULL(0x2C0F0102), SH_UNT_PERV_44  , SH_ACS_SCOM2     );
+REG64( PERV_EC13_PPM_GPMMR_SCOM                                , RULL(0x2D0F0100), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_GPMMR_SCOM1                               , RULL(0x2D0F0101), SH_UNT_PERV_45  , SH_ACS_SCOM1     );
+REG64( PERV_EC13_PPM_GPMMR_SCOM2                               , RULL(0x2D0F0102), SH_UNT_PERV_45  , SH_ACS_SCOM2     );
+REG64( PERV_EC14_PPM_GPMMR_SCOM                                , RULL(0x2E0F0100), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_GPMMR_SCOM1                               , RULL(0x2E0F0101), SH_UNT_PERV_46  , SH_ACS_SCOM1     );
+REG64( PERV_EC14_PPM_GPMMR_SCOM2                               , RULL(0x2E0F0102), SH_UNT_PERV_46  , SH_ACS_SCOM2     );
+REG64( PERV_EC15_PPM_GPMMR_SCOM                                , RULL(0x2F0F0100), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_GPMMR_SCOM1                               , RULL(0x2F0F0101), SH_UNT_PERV_47  , SH_ACS_SCOM1     );
+REG64( PERV_EC15_PPM_GPMMR_SCOM2                               , RULL(0x2F0F0102), SH_UNT_PERV_47  , SH_ACS_SCOM2     );
+REG64( PERV_EC16_PPM_GPMMR_SCOM                                , RULL(0x300F0100), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_GPMMR_SCOM1                               , RULL(0x300F0101), SH_UNT_PERV_48  , SH_ACS_SCOM1     );
+REG64( PERV_EC16_PPM_GPMMR_SCOM2                               , RULL(0x300F0102), SH_UNT_PERV_48  , SH_ACS_SCOM2     );
+REG64( PERV_EC17_PPM_GPMMR_SCOM                                , RULL(0x310F0100), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_GPMMR_SCOM1                               , RULL(0x310F0101), SH_UNT_PERV_49  , SH_ACS_SCOM1     );
+REG64( PERV_EC17_PPM_GPMMR_SCOM2                               , RULL(0x310F0102), SH_UNT_PERV_49  , SH_ACS_SCOM2     );
+REG64( PERV_EC18_PPM_GPMMR_SCOM                                , RULL(0x320F0100), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_GPMMR_SCOM1                               , RULL(0x320F0101), SH_UNT_PERV_50  , SH_ACS_SCOM1     );
+REG64( PERV_EC18_PPM_GPMMR_SCOM2                               , RULL(0x320F0102), SH_UNT_PERV_50  , SH_ACS_SCOM2     );
+REG64( PERV_EC19_PPM_GPMMR_SCOM                                , RULL(0x330F0100), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_GPMMR_SCOM1                               , RULL(0x330F0101), SH_UNT_PERV_51  , SH_ACS_SCOM1     );
+REG64( PERV_EC19_PPM_GPMMR_SCOM2                               , RULL(0x330F0102), SH_UNT_PERV_51  , SH_ACS_SCOM2     );
+REG64( PERV_EC20_PPM_GPMMR_SCOM                                , RULL(0x340F0100), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_GPMMR_SCOM1                               , RULL(0x340F0101), SH_UNT_PERV_52  , SH_ACS_SCOM1     );
+REG64( PERV_EC20_PPM_GPMMR_SCOM2                               , RULL(0x340F0102), SH_UNT_PERV_52  , SH_ACS_SCOM2     );
+REG64( PERV_EC21_PPM_GPMMR_SCOM                                , RULL(0x350F0100), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_GPMMR_SCOM1                               , RULL(0x350F0101), SH_UNT_PERV_53  , SH_ACS_SCOM1     );
+REG64( PERV_EC21_PPM_GPMMR_SCOM2                               , RULL(0x350F0102), SH_UNT_PERV_53  , SH_ACS_SCOM2     );
+REG64( PERV_EC22_PPM_GPMMR_SCOM                                , RULL(0x360F0100), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_GPMMR_SCOM1                               , RULL(0x360F0101), SH_UNT_PERV_54  , SH_ACS_SCOM1     );
+REG64( PERV_EC22_PPM_GPMMR_SCOM2                               , RULL(0x360F0102), SH_UNT_PERV_54  , SH_ACS_SCOM2     );
+REG64( PERV_EC23_PPM_GPMMR_SCOM                                , RULL(0x370F0100), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_GPMMR_SCOM1                               , RULL(0x370F0101), SH_UNT_PERV_55  , SH_ACS_SCOM1     );
+REG64( PERV_EC23_PPM_GPMMR_SCOM2                               , RULL(0x370F0102), SH_UNT_PERV_55  , SH_ACS_SCOM2     );
+
+REG64( PERV_EP00_PPM_IVRMAVR                                   , RULL(0x100F01B5), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_PPM_IVRMAVR                                   , RULL(0x110F01B5), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_PPM_IVRMAVR                                   , RULL(0x120F01B5), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_PPM_IVRMAVR                                   , RULL(0x130F01B5), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_PPM_IVRMAVR                                   , RULL(0x140F01B5), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_PPM_IVRMAVR                                   , RULL(0x150F01B5), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_PPM_IVRMAVR                                   , RULL(0x200F01B5), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_PPM_IVRMAVR                                   , RULL(0x210F01B5), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_PPM_IVRMAVR                                   , RULL(0x220F01B5), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_PPM_IVRMAVR                                   , RULL(0x230F01B5), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_PPM_IVRMAVR                                   , RULL(0x240F01B5), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_PPM_IVRMAVR                                   , RULL(0x250F01B5), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_PPM_IVRMAVR                                   , RULL(0x260F01B5), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_PPM_IVRMAVR                                   , RULL(0x270F01B5), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_PPM_IVRMAVR                                   , RULL(0x280F01B5), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_PPM_IVRMAVR                                   , RULL(0x290F01B5), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_PPM_IVRMAVR                                   , RULL(0x2A0F01B5), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_PPM_IVRMAVR                                   , RULL(0x2B0F01B5), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_PPM_IVRMAVR                                   , RULL(0x2C0F01B5), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_PPM_IVRMAVR                                   , RULL(0x2D0F01B5), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_PPM_IVRMAVR                                   , RULL(0x2E0F01B5), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_PPM_IVRMAVR                                   , RULL(0x2F0F01B5), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_PPM_IVRMAVR                                   , RULL(0x300F01B5), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_PPM_IVRMAVR                                   , RULL(0x310F01B5), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_PPM_IVRMAVR                                   , RULL(0x320F01B5), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_PPM_IVRMAVR                                   , RULL(0x330F01B5), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_PPM_IVRMAVR                                   , RULL(0x340F01B5), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_PPM_IVRMAVR                                   , RULL(0x350F01B5), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_PPM_IVRMAVR                                   , RULL(0x360F01B5), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_PPM_IVRMAVR                                   , RULL(0x370F01B5), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EP00_PPM_IVRMCR                                    , RULL(0x100F01B0), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_PPM_IVRMCR_CLEAR                              , RULL(0x100F01B1), SH_UNT_PERV_16  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP00_PPM_IVRMCR_OR                                 , RULL(0x100F01B2), SH_UNT_PERV_16  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP01_PPM_IVRMCR                                    , RULL(0x110F01B0), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_IVRMCR_CLEAR                              , RULL(0x110F01B1), SH_UNT_PERV_17  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP01_PPM_IVRMCR_OR                                 , RULL(0x110F01B2), SH_UNT_PERV_17  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP02_PPM_IVRMCR                                    , RULL(0x120F01B0), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_IVRMCR_CLEAR                              , RULL(0x120F01B1), SH_UNT_PERV_18  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP02_PPM_IVRMCR_OR                                 , RULL(0x120F01B2), SH_UNT_PERV_18  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP03_PPM_IVRMCR                                    , RULL(0x130F01B0), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_IVRMCR_CLEAR                              , RULL(0x130F01B1), SH_UNT_PERV_19  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP03_PPM_IVRMCR_OR                                 , RULL(0x130F01B2), SH_UNT_PERV_19  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP04_PPM_IVRMCR                                    , RULL(0x140F01B0), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_IVRMCR_CLEAR                              , RULL(0x140F01B1), SH_UNT_PERV_20  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP04_PPM_IVRMCR_OR                                 , RULL(0x140F01B2), SH_UNT_PERV_20  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP05_PPM_IVRMCR                                    , RULL(0x150F01B0), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_IVRMCR_CLEAR                              , RULL(0x150F01B1), SH_UNT_PERV_21  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP05_PPM_IVRMCR_OR                                 , RULL(0x150F01B2), SH_UNT_PERV_21  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC00_PPM_IVRMCR                                    , RULL(0x200F01B0), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_IVRMCR_CLEAR                              , RULL(0x200F01B1), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_PPM_IVRMCR_OR                                 , RULL(0x200F01B2), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_PPM_IVRMCR                                    , RULL(0x210F01B0), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_IVRMCR_CLEAR                              , RULL(0x210F01B1), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_PPM_IVRMCR_OR                                 , RULL(0x210F01B2), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_PPM_IVRMCR                                    , RULL(0x220F01B0), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_IVRMCR_CLEAR                              , RULL(0x220F01B1), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_PPM_IVRMCR_OR                                 , RULL(0x220F01B2), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_PPM_IVRMCR                                    , RULL(0x230F01B0), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_IVRMCR_CLEAR                              , RULL(0x230F01B1), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_PPM_IVRMCR_OR                                 , RULL(0x230F01B2), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_PPM_IVRMCR                                    , RULL(0x240F01B0), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_IVRMCR_CLEAR                              , RULL(0x240F01B1), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_PPM_IVRMCR_OR                                 , RULL(0x240F01B2), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_PPM_IVRMCR                                    , RULL(0x250F01B0), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_IVRMCR_CLEAR                              , RULL(0x250F01B1), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_PPM_IVRMCR_OR                                 , RULL(0x250F01B2), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_PPM_IVRMCR                                    , RULL(0x260F01B0), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_IVRMCR_CLEAR                              , RULL(0x260F01B1), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_PPM_IVRMCR_OR                                 , RULL(0x260F01B2), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_PPM_IVRMCR                                    , RULL(0x270F01B0), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_IVRMCR_CLEAR                              , RULL(0x270F01B1), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_PPM_IVRMCR_OR                                 , RULL(0x270F01B2), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_PPM_IVRMCR                                    , RULL(0x280F01B0), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_IVRMCR_CLEAR                              , RULL(0x280F01B1), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_PPM_IVRMCR_OR                                 , RULL(0x280F01B2), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_PPM_IVRMCR                                    , RULL(0x290F01B0), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_IVRMCR_CLEAR                              , RULL(0x290F01B1), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_PPM_IVRMCR_OR                                 , RULL(0x290F01B2), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_PPM_IVRMCR                                    , RULL(0x2A0F01B0), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_IVRMCR_CLEAR                              , RULL(0x2A0F01B1), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_PPM_IVRMCR_OR                                 , RULL(0x2A0F01B2), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_PPM_IVRMCR                                    , RULL(0x2B0F01B0), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_IVRMCR_CLEAR                              , RULL(0x2B0F01B1), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_PPM_IVRMCR_OR                                 , RULL(0x2B0F01B2), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_PPM_IVRMCR                                    , RULL(0x2C0F01B0), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_IVRMCR_CLEAR                              , RULL(0x2C0F01B1), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_PPM_IVRMCR_OR                                 , RULL(0x2C0F01B2), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_PPM_IVRMCR                                    , RULL(0x2D0F01B0), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_IVRMCR_CLEAR                              , RULL(0x2D0F01B1), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_PPM_IVRMCR_OR                                 , RULL(0x2D0F01B2), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_PPM_IVRMCR                                    , RULL(0x2E0F01B0), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_IVRMCR_CLEAR                              , RULL(0x2E0F01B1), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_PPM_IVRMCR_OR                                 , RULL(0x2E0F01B2), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_PPM_IVRMCR                                    , RULL(0x2F0F01B0), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_IVRMCR_CLEAR                              , RULL(0x2F0F01B1), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_PPM_IVRMCR_OR                                 , RULL(0x2F0F01B2), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_PPM_IVRMCR                                    , RULL(0x300F01B0), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_IVRMCR_CLEAR                              , RULL(0x300F01B1), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_PPM_IVRMCR_OR                                 , RULL(0x300F01B2), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_PPM_IVRMCR                                    , RULL(0x310F01B0), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_IVRMCR_CLEAR                              , RULL(0x310F01B1), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_PPM_IVRMCR_OR                                 , RULL(0x310F01B2), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_PPM_IVRMCR                                    , RULL(0x320F01B0), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_IVRMCR_CLEAR                              , RULL(0x320F01B1), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_PPM_IVRMCR_OR                                 , RULL(0x320F01B2), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_PPM_IVRMCR                                    , RULL(0x330F01B0), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_IVRMCR_CLEAR                              , RULL(0x330F01B1), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_PPM_IVRMCR_OR                                 , RULL(0x330F01B2), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_PPM_IVRMCR                                    , RULL(0x340F01B0), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_IVRMCR_CLEAR                              , RULL(0x340F01B1), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_PPM_IVRMCR_OR                                 , RULL(0x340F01B2), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_PPM_IVRMCR                                    , RULL(0x350F01B0), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_IVRMCR_CLEAR                              , RULL(0x350F01B1), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_PPM_IVRMCR_OR                                 , RULL(0x350F01B2), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_PPM_IVRMCR                                    , RULL(0x360F01B0), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_IVRMCR_CLEAR                              , RULL(0x360F01B1), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_PPM_IVRMCR_OR                                 , RULL(0x360F01B2), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_PPM_IVRMCR                                    , RULL(0x370F01B0), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_IVRMCR_CLEAR                              , RULL(0x370F01B1), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_PPM_IVRMCR_OR                                 , RULL(0x370F01B2), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EP00_PPM_IVRMDVR                                   , RULL(0x100F01B4), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_IVRMDVR                                   , RULL(0x110F01B4), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_IVRMDVR                                   , RULL(0x120F01B4), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_IVRMDVR                                   , RULL(0x130F01B4), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_IVRMDVR                                   , RULL(0x140F01B4), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_IVRMDVR                                   , RULL(0x150F01B4), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_IVRMDVR                                   , RULL(0x200F01B4), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_IVRMDVR                                   , RULL(0x210F01B4), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_IVRMDVR                                   , RULL(0x220F01B4), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_IVRMDVR                                   , RULL(0x230F01B4), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_IVRMDVR                                   , RULL(0x240F01B4), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_IVRMDVR                                   , RULL(0x250F01B4), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_IVRMDVR                                   , RULL(0x260F01B4), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_IVRMDVR                                   , RULL(0x270F01B4), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_IVRMDVR                                   , RULL(0x280F01B4), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_IVRMDVR                                   , RULL(0x290F01B4), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_IVRMDVR                                   , RULL(0x2A0F01B4), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_IVRMDVR                                   , RULL(0x2B0F01B4), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_IVRMDVR                                   , RULL(0x2C0F01B4), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_IVRMDVR                                   , RULL(0x2D0F01B4), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_IVRMDVR                                   , RULL(0x2E0F01B4), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_IVRMDVR                                   , RULL(0x2F0F01B4), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_IVRMDVR                                   , RULL(0x300F01B4), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_IVRMDVR                                   , RULL(0x310F01B4), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_IVRMDVR                                   , RULL(0x320F01B4), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_IVRMDVR                                   , RULL(0x330F01B4), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_IVRMDVR                                   , RULL(0x340F01B4), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_IVRMDVR                                   , RULL(0x350F01B4), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_IVRMDVR                                   , RULL(0x360F01B4), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_IVRMDVR                                   , RULL(0x370F01B4), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_IVRMST                                    , RULL(0x100F01B3), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_PPM_IVRMST                                    , RULL(0x110F01B3), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_PPM_IVRMST                                    , RULL(0x120F01B3), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_PPM_IVRMST                                    , RULL(0x130F01B3), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_PPM_IVRMST                                    , RULL(0x140F01B3), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_PPM_IVRMST                                    , RULL(0x150F01B3), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_PPM_IVRMST                                    , RULL(0x200F01B3), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_PPM_IVRMST                                    , RULL(0x210F01B3), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_PPM_IVRMST                                    , RULL(0x220F01B3), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_PPM_IVRMST                                    , RULL(0x230F01B3), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_PPM_IVRMST                                    , RULL(0x240F01B3), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_PPM_IVRMST                                    , RULL(0x250F01B3), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_PPM_IVRMST                                    , RULL(0x260F01B3), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_PPM_IVRMST                                    , RULL(0x270F01B3), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_PPM_IVRMST                                    , RULL(0x280F01B3), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_PPM_IVRMST                                    , RULL(0x290F01B3), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_PPM_IVRMST                                    , RULL(0x2A0F01B3), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_PPM_IVRMST                                    , RULL(0x2B0F01B3), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_PPM_IVRMST                                    , RULL(0x2C0F01B3), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_PPM_IVRMST                                    , RULL(0x2D0F01B3), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_PPM_IVRMST                                    , RULL(0x2E0F01B3), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_PPM_IVRMST                                    , RULL(0x2F0F01B3), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_PPM_IVRMST                                    , RULL(0x300F01B3), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_PPM_IVRMST                                    , RULL(0x310F01B3), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_PPM_IVRMST                                    , RULL(0x320F01B3), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_PPM_IVRMST                                    , RULL(0x330F01B3), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_PPM_IVRMST                                    , RULL(0x340F01B3), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_PPM_IVRMST                                    , RULL(0x350F01B3), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_PPM_IVRMST                                    , RULL(0x360F01B3), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_PPM_IVRMST                                    , RULL(0x370F01B3), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EP00_PPM_PFCS_SCOM                                 , RULL(0x100F0118), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP00_PPM_PFCS_SCOM1                                , RULL(0x100F0119), SH_UNT_PERV_16  , SH_ACS_SCOM1     );
+REG64( PERV_EP00_PPM_PFCS_SCOM2                                , RULL(0x100F011A), SH_UNT_PERV_16  , SH_ACS_SCOM2     );
+REG64( PERV_EP01_PPM_PFCS_SCOM                                 , RULL(0x110F0118), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_PFCS_SCOM1                                , RULL(0x110F0119), SH_UNT_PERV_17  , SH_ACS_SCOM1     );
+REG64( PERV_EP01_PPM_PFCS_SCOM2                                , RULL(0x110F011A), SH_UNT_PERV_17  , SH_ACS_SCOM2     );
+REG64( PERV_EP02_PPM_PFCS_SCOM                                 , RULL(0x120F0118), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_PFCS_SCOM1                                , RULL(0x120F0119), SH_UNT_PERV_18  , SH_ACS_SCOM1     );
+REG64( PERV_EP02_PPM_PFCS_SCOM2                                , RULL(0x120F011A), SH_UNT_PERV_18  , SH_ACS_SCOM2     );
+REG64( PERV_EP03_PPM_PFCS_SCOM                                 , RULL(0x130F0118), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_PFCS_SCOM1                                , RULL(0x130F0119), SH_UNT_PERV_19  , SH_ACS_SCOM1     );
+REG64( PERV_EP03_PPM_PFCS_SCOM2                                , RULL(0x130F011A), SH_UNT_PERV_19  , SH_ACS_SCOM2     );
+REG64( PERV_EP04_PPM_PFCS_SCOM                                 , RULL(0x140F0118), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_PFCS_SCOM1                                , RULL(0x140F0119), SH_UNT_PERV_20  , SH_ACS_SCOM1     );
+REG64( PERV_EP04_PPM_PFCS_SCOM2                                , RULL(0x140F011A), SH_UNT_PERV_20  , SH_ACS_SCOM2     );
+REG64( PERV_EP05_PPM_PFCS_SCOM                                 , RULL(0x150F0118), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_PFCS_SCOM1                                , RULL(0x150F0119), SH_UNT_PERV_21  , SH_ACS_SCOM1     );
+REG64( PERV_EP05_PPM_PFCS_SCOM2                                , RULL(0x150F011A), SH_UNT_PERV_21  , SH_ACS_SCOM2     );
+REG64( PERV_EC00_PPM_PFCS_SCOM                                 , RULL(0x200F0118), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_PFCS_SCOM1                                , RULL(0x200F0119), SH_UNT_PERV_32  , SH_ACS_SCOM1     );
+REG64( PERV_EC00_PPM_PFCS_SCOM2                                , RULL(0x200F011A), SH_UNT_PERV_32  , SH_ACS_SCOM2     );
+REG64( PERV_EC01_PPM_PFCS_SCOM                                 , RULL(0x210F0118), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_PFCS_SCOM1                                , RULL(0x210F0119), SH_UNT_PERV_33  , SH_ACS_SCOM1     );
+REG64( PERV_EC01_PPM_PFCS_SCOM2                                , RULL(0x210F011A), SH_UNT_PERV_33  , SH_ACS_SCOM2     );
+REG64( PERV_EC02_PPM_PFCS_SCOM                                 , RULL(0x220F0118), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_PFCS_SCOM1                                , RULL(0x220F0119), SH_UNT_PERV_34  , SH_ACS_SCOM1     );
+REG64( PERV_EC02_PPM_PFCS_SCOM2                                , RULL(0x220F011A), SH_UNT_PERV_34  , SH_ACS_SCOM2     );
+REG64( PERV_EC03_PPM_PFCS_SCOM                                 , RULL(0x230F0118), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_PFCS_SCOM1                                , RULL(0x230F0119), SH_UNT_PERV_35  , SH_ACS_SCOM1     );
+REG64( PERV_EC03_PPM_PFCS_SCOM2                                , RULL(0x230F011A), SH_UNT_PERV_35  , SH_ACS_SCOM2     );
+REG64( PERV_EC04_PPM_PFCS_SCOM                                 , RULL(0x240F0118), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_PFCS_SCOM1                                , RULL(0x240F0119), SH_UNT_PERV_36  , SH_ACS_SCOM1     );
+REG64( PERV_EC04_PPM_PFCS_SCOM2                                , RULL(0x240F011A), SH_UNT_PERV_36  , SH_ACS_SCOM2     );
+REG64( PERV_EC05_PPM_PFCS_SCOM                                 , RULL(0x250F0118), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_PFCS_SCOM1                                , RULL(0x250F0119), SH_UNT_PERV_37  , SH_ACS_SCOM1     );
+REG64( PERV_EC05_PPM_PFCS_SCOM2                                , RULL(0x250F011A), SH_UNT_PERV_37  , SH_ACS_SCOM2     );
+REG64( PERV_EC06_PPM_PFCS_SCOM                                 , RULL(0x260F0118), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_PFCS_SCOM1                                , RULL(0x260F0119), SH_UNT_PERV_38  , SH_ACS_SCOM1     );
+REG64( PERV_EC06_PPM_PFCS_SCOM2                                , RULL(0x260F011A), SH_UNT_PERV_38  , SH_ACS_SCOM2     );
+REG64( PERV_EC07_PPM_PFCS_SCOM                                 , RULL(0x270F0118), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_PFCS_SCOM1                                , RULL(0x270F0119), SH_UNT_PERV_39  , SH_ACS_SCOM1     );
+REG64( PERV_EC07_PPM_PFCS_SCOM2                                , RULL(0x270F011A), SH_UNT_PERV_39  , SH_ACS_SCOM2     );
+REG64( PERV_EC08_PPM_PFCS_SCOM                                 , RULL(0x280F0118), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_PFCS_SCOM1                                , RULL(0x280F0119), SH_UNT_PERV_40  , SH_ACS_SCOM1     );
+REG64( PERV_EC08_PPM_PFCS_SCOM2                                , RULL(0x280F011A), SH_UNT_PERV_40  , SH_ACS_SCOM2     );
+REG64( PERV_EC09_PPM_PFCS_SCOM                                 , RULL(0x290F0118), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_PFCS_SCOM1                                , RULL(0x290F0119), SH_UNT_PERV_41  , SH_ACS_SCOM1     );
+REG64( PERV_EC09_PPM_PFCS_SCOM2                                , RULL(0x290F011A), SH_UNT_PERV_41  , SH_ACS_SCOM2     );
+REG64( PERV_EC10_PPM_PFCS_SCOM                                 , RULL(0x2A0F0118), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_PFCS_SCOM1                                , RULL(0x2A0F0119), SH_UNT_PERV_42  , SH_ACS_SCOM1     );
+REG64( PERV_EC10_PPM_PFCS_SCOM2                                , RULL(0x2A0F011A), SH_UNT_PERV_42  , SH_ACS_SCOM2     );
+REG64( PERV_EC11_PPM_PFCS_SCOM                                 , RULL(0x2B0F0118), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_PFCS_SCOM1                                , RULL(0x2B0F0119), SH_UNT_PERV_43  , SH_ACS_SCOM1     );
+REG64( PERV_EC11_PPM_PFCS_SCOM2                                , RULL(0x2B0F011A), SH_UNT_PERV_43  , SH_ACS_SCOM2     );
+REG64( PERV_EC12_PPM_PFCS_SCOM                                 , RULL(0x2C0F0118), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_PFCS_SCOM1                                , RULL(0x2C0F0119), SH_UNT_PERV_44  , SH_ACS_SCOM1     );
+REG64( PERV_EC12_PPM_PFCS_SCOM2                                , RULL(0x2C0F011A), SH_UNT_PERV_44  , SH_ACS_SCOM2     );
+REG64( PERV_EC13_PPM_PFCS_SCOM                                 , RULL(0x2D0F0118), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_PFCS_SCOM1                                , RULL(0x2D0F0119), SH_UNT_PERV_45  , SH_ACS_SCOM1     );
+REG64( PERV_EC13_PPM_PFCS_SCOM2                                , RULL(0x2D0F011A), SH_UNT_PERV_45  , SH_ACS_SCOM2     );
+REG64( PERV_EC14_PPM_PFCS_SCOM                                 , RULL(0x2E0F0118), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_PFCS_SCOM1                                , RULL(0x2E0F0119), SH_UNT_PERV_46  , SH_ACS_SCOM1     );
+REG64( PERV_EC14_PPM_PFCS_SCOM2                                , RULL(0x2E0F011A), SH_UNT_PERV_46  , SH_ACS_SCOM2     );
+REG64( PERV_EC15_PPM_PFCS_SCOM                                 , RULL(0x2F0F0118), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_PFCS_SCOM1                                , RULL(0x2F0F0119), SH_UNT_PERV_47  , SH_ACS_SCOM1     );
+REG64( PERV_EC15_PPM_PFCS_SCOM2                                , RULL(0x2F0F011A), SH_UNT_PERV_47  , SH_ACS_SCOM2     );
+REG64( PERV_EC16_PPM_PFCS_SCOM                                 , RULL(0x300F0118), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_PFCS_SCOM1                                , RULL(0x300F0119), SH_UNT_PERV_48  , SH_ACS_SCOM1     );
+REG64( PERV_EC16_PPM_PFCS_SCOM2                                , RULL(0x300F011A), SH_UNT_PERV_48  , SH_ACS_SCOM2     );
+REG64( PERV_EC17_PPM_PFCS_SCOM                                 , RULL(0x310F0118), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_PFCS_SCOM1                                , RULL(0x310F0119), SH_UNT_PERV_49  , SH_ACS_SCOM1     );
+REG64( PERV_EC17_PPM_PFCS_SCOM2                                , RULL(0x310F011A), SH_UNT_PERV_49  , SH_ACS_SCOM2     );
+REG64( PERV_EC18_PPM_PFCS_SCOM                                 , RULL(0x320F0118), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_PFCS_SCOM1                                , RULL(0x320F0119), SH_UNT_PERV_50  , SH_ACS_SCOM1     );
+REG64( PERV_EC18_PPM_PFCS_SCOM2                                , RULL(0x320F011A), SH_UNT_PERV_50  , SH_ACS_SCOM2     );
+REG64( PERV_EC19_PPM_PFCS_SCOM                                 , RULL(0x330F0118), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_PFCS_SCOM1                                , RULL(0x330F0119), SH_UNT_PERV_51  , SH_ACS_SCOM1     );
+REG64( PERV_EC19_PPM_PFCS_SCOM2                                , RULL(0x330F011A), SH_UNT_PERV_51  , SH_ACS_SCOM2     );
+REG64( PERV_EC20_PPM_PFCS_SCOM                                 , RULL(0x340F0118), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_PFCS_SCOM1                                , RULL(0x340F0119), SH_UNT_PERV_52  , SH_ACS_SCOM1     );
+REG64( PERV_EC20_PPM_PFCS_SCOM2                                , RULL(0x340F011A), SH_UNT_PERV_52  , SH_ACS_SCOM2     );
+REG64( PERV_EC21_PPM_PFCS_SCOM                                 , RULL(0x350F0118), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_PFCS_SCOM1                                , RULL(0x350F0119), SH_UNT_PERV_53  , SH_ACS_SCOM1     );
+REG64( PERV_EC21_PPM_PFCS_SCOM2                                , RULL(0x350F011A), SH_UNT_PERV_53  , SH_ACS_SCOM2     );
+REG64( PERV_EC22_PPM_PFCS_SCOM                                 , RULL(0x360F0118), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_PFCS_SCOM1                                , RULL(0x360F0119), SH_UNT_PERV_54  , SH_ACS_SCOM1     );
+REG64( PERV_EC22_PPM_PFCS_SCOM2                                , RULL(0x360F011A), SH_UNT_PERV_54  , SH_ACS_SCOM2     );
+REG64( PERV_EC23_PPM_PFCS_SCOM                                 , RULL(0x370F0118), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_PFCS_SCOM1                                , RULL(0x370F0119), SH_UNT_PERV_55  , SH_ACS_SCOM1     );
+REG64( PERV_EC23_PPM_PFCS_SCOM2                                , RULL(0x370F011A), SH_UNT_PERV_55  , SH_ACS_SCOM2     );
+
+REG64( PERV_EP00_PPM_PFDLY                                     , RULL(0x100F011B), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_PFDLY                                     , RULL(0x110F011B), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_PFDLY                                     , RULL(0x120F011B), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_PFDLY                                     , RULL(0x130F011B), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_PFDLY                                     , RULL(0x140F011B), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_PFDLY                                     , RULL(0x150F011B), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_PFDLY                                     , RULL(0x200F011B), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_PFDLY                                     , RULL(0x210F011B), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_PFDLY                                     , RULL(0x220F011B), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_PFDLY                                     , RULL(0x230F011B), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_PFDLY                                     , RULL(0x240F011B), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_PFDLY                                     , RULL(0x250F011B), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_PFDLY                                     , RULL(0x260F011B), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_PFDLY                                     , RULL(0x270F011B), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_PFDLY                                     , RULL(0x280F011B), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_PFDLY                                     , RULL(0x290F011B), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_PFDLY                                     , RULL(0x2A0F011B), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_PFDLY                                     , RULL(0x2B0F011B), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_PFDLY                                     , RULL(0x2C0F011B), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_PFDLY                                     , RULL(0x2D0F011B), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_PFDLY                                     , RULL(0x2E0F011B), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_PFDLY                                     , RULL(0x2F0F011B), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_PFDLY                                     , RULL(0x300F011B), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_PFDLY                                     , RULL(0x310F011B), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_PFDLY                                     , RULL(0x320F011B), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_PFDLY                                     , RULL(0x330F011B), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_PFDLY                                     , RULL(0x340F011B), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_PFDLY                                     , RULL(0x350F011B), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_PFDLY                                     , RULL(0x360F011B), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_PFDLY                                     , RULL(0x370F011B), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_PFOFF                                     , RULL(0x100F011D), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_PFOFF                                     , RULL(0x110F011D), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_PFOFF                                     , RULL(0x120F011D), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_PFOFF                                     , RULL(0x130F011D), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_PFOFF                                     , RULL(0x140F011D), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_PFOFF                                     , RULL(0x150F011D), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_PFOFF                                     , RULL(0x200F011D), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_PFOFF                                     , RULL(0x210F011D), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_PFOFF                                     , RULL(0x220F011D), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_PFOFF                                     , RULL(0x230F011D), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_PFOFF                                     , RULL(0x240F011D), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_PFOFF                                     , RULL(0x250F011D), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_PFOFF                                     , RULL(0x260F011D), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_PFOFF                                     , RULL(0x270F011D), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_PFOFF                                     , RULL(0x280F011D), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_PFOFF                                     , RULL(0x290F011D), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_PFOFF                                     , RULL(0x2A0F011D), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_PFOFF                                     , RULL(0x2B0F011D), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_PFOFF                                     , RULL(0x2C0F011D), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_PFOFF                                     , RULL(0x2D0F011D), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_PFOFF                                     , RULL(0x2E0F011D), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_PFOFF                                     , RULL(0x2F0F011D), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_PFOFF                                     , RULL(0x300F011D), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_PFOFF                                     , RULL(0x310F011D), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_PFOFF                                     , RULL(0x320F011D), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_PFOFF                                     , RULL(0x330F011D), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_PFOFF                                     , RULL(0x340F011D), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_PFOFF                                     , RULL(0x350F011D), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_PFOFF                                     , RULL(0x360F011D), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_PFOFF                                     , RULL(0x370F011D), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_PFSNS                                     , RULL(0x100F011C), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_PPM_PFSNS                                     , RULL(0x110F011C), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_PPM_PFSNS                                     , RULL(0x120F011C), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_PPM_PFSNS                                     , RULL(0x130F011C), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_PPM_PFSNS                                     , RULL(0x140F011C), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_PPM_PFSNS                                     , RULL(0x150F011C), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_PPM_PFSNS                                     , RULL(0x200F011C), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_PPM_PFSNS                                     , RULL(0x210F011C), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_PPM_PFSNS                                     , RULL(0x220F011C), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_PPM_PFSNS                                     , RULL(0x230F011C), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_PPM_PFSNS                                     , RULL(0x240F011C), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_PPM_PFSNS                                     , RULL(0x250F011C), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_PPM_PFSNS                                     , RULL(0x260F011C), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_PPM_PFSNS                                     , RULL(0x270F011C), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_PPM_PFSNS                                     , RULL(0x280F011C), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_PPM_PFSNS                                     , RULL(0x290F011C), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_PPM_PFSNS                                     , RULL(0x2A0F011C), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_PPM_PFSNS                                     , RULL(0x2B0F011C), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_PPM_PFSNS                                     , RULL(0x2C0F011C), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_PPM_PFSNS                                     , RULL(0x2D0F011C), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_PPM_PFSNS                                     , RULL(0x2E0F011C), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_PPM_PFSNS                                     , RULL(0x2F0F011C), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_PPM_PFSNS                                     , RULL(0x300F011C), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_PPM_PFSNS                                     , RULL(0x310F011C), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_PPM_PFSNS                                     , RULL(0x320F011C), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_PPM_PFSNS                                     , RULL(0x330F011C), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_PPM_PFSNS                                     , RULL(0x340F011C), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_PPM_PFSNS                                     , RULL(0x350F011C), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_PPM_PFSNS                                     , RULL(0x360F011C), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_PPM_PFSNS                                     , RULL(0x370F011C), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EP00_PPM_PIG                                       , RULL(0x100F0180), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_PIG                                       , RULL(0x110F0180), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_PIG                                       , RULL(0x120F0180), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_PIG                                       , RULL(0x130F0180), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_PIG                                       , RULL(0x140F0180), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_PIG                                       , RULL(0x150F0180), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_PIG                                       , RULL(0x200F0180), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_PIG                                       , RULL(0x210F0180), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_PIG                                       , RULL(0x220F0180), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_PIG                                       , RULL(0x230F0180), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_PIG                                       , RULL(0x240F0180), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_PIG                                       , RULL(0x250F0180), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_PIG                                       , RULL(0x260F0180), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_PIG                                       , RULL(0x270F0180), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_PIG                                       , RULL(0x280F0180), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_PIG                                       , RULL(0x290F0180), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_PIG                                       , RULL(0x2A0F0180), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_PIG                                       , RULL(0x2B0F0180), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_PIG                                       , RULL(0x2C0F0180), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_PIG                                       , RULL(0x2D0F0180), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_PIG                                       , RULL(0x2E0F0180), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_PIG                                       , RULL(0x2F0F0180), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_PIG                                       , RULL(0x300F0180), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_PIG                                       , RULL(0x310F0180), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_PIG                                       , RULL(0x320F0180), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_PIG                                       , RULL(0x330F0180), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_PIG                                       , RULL(0x340F0180), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_PIG                                       , RULL(0x350F0180), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_PIG                                       , RULL(0x360F0180), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_PIG                                       , RULL(0x370F0180), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EP00_PPM_SCRATCH0                                  , RULL(0x100F011E), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_SCRATCH0                                  , RULL(0x110F011E), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_SCRATCH0                                  , RULL(0x120F011E), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_SCRATCH0                                  , RULL(0x130F011E), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_SCRATCH0                                  , RULL(0x140F011E), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_SCRATCH0                                  , RULL(0x150F011E), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_SCRATCH0                                  , RULL(0x200F011E), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_SCRATCH0                                  , RULL(0x210F011E), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_SCRATCH0                                  , RULL(0x220F011E), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_SCRATCH0                                  , RULL(0x230F011E), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_SCRATCH0                                  , RULL(0x240F011E), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_SCRATCH0                                  , RULL(0x250F011E), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_SCRATCH0                                  , RULL(0x260F011E), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_SCRATCH0                                  , RULL(0x270F011E), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_SCRATCH0                                  , RULL(0x280F011E), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_SCRATCH0                                  , RULL(0x290F011E), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_SCRATCH0                                  , RULL(0x2A0F011E), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_SCRATCH0                                  , RULL(0x2B0F011E), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_SCRATCH0                                  , RULL(0x2C0F011E), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_SCRATCH0                                  , RULL(0x2D0F011E), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_SCRATCH0                                  , RULL(0x2E0F011E), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_SCRATCH0                                  , RULL(0x2F0F011E), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_SCRATCH0                                  , RULL(0x300F011E), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_SCRATCH0                                  , RULL(0x310F011E), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_SCRATCH0                                  , RULL(0x320F011E), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_SCRATCH0                                  , RULL(0x330F011E), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_SCRATCH0                                  , RULL(0x340F011E), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_SCRATCH0                                  , RULL(0x350F011E), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_SCRATCH0                                  , RULL(0x360F011E), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_SCRATCH0                                  , RULL(0x370F011E), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_SCRATCH1                                  , RULL(0x100F011F), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_SCRATCH1                                  , RULL(0x110F011F), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_SCRATCH1                                  , RULL(0x120F011F), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_SCRATCH1                                  , RULL(0x130F011F), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_SCRATCH1                                  , RULL(0x140F011F), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_SCRATCH1                                  , RULL(0x150F011F), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_SCRATCH1                                  , RULL(0x200F011F), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_SCRATCH1                                  , RULL(0x210F011F), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_SCRATCH1                                  , RULL(0x220F011F), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_SCRATCH1                                  , RULL(0x230F011F), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_SCRATCH1                                  , RULL(0x240F011F), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_SCRATCH1                                  , RULL(0x250F011F), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_SCRATCH1                                  , RULL(0x260F011F), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_SCRATCH1                                  , RULL(0x270F011F), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_SCRATCH1                                  , RULL(0x280F011F), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_SCRATCH1                                  , RULL(0x290F011F), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_SCRATCH1                                  , RULL(0x2A0F011F), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_SCRATCH1                                  , RULL(0x2B0F011F), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_SCRATCH1                                  , RULL(0x2C0F011F), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_SCRATCH1                                  , RULL(0x2D0F011F), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_SCRATCH1                                  , RULL(0x2E0F011F), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_SCRATCH1                                  , RULL(0x2F0F011F), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_SCRATCH1                                  , RULL(0x300F011F), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_SCRATCH1                                  , RULL(0x310F011F), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_SCRATCH1                                  , RULL(0x320F011F), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_SCRATCH1                                  , RULL(0x330F011F), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_SCRATCH1                                  , RULL(0x340F011F), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_SCRATCH1                                  , RULL(0x350F011F), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_SCRATCH1                                  , RULL(0x360F011F), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_SCRATCH1                                  , RULL(0x370F011F), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_SPWKUP_FSP                                , RULL(0x100F010B), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_SPWKUP_FSP                                , RULL(0x110F010B), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_SPWKUP_FSP                                , RULL(0x120F010B), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_SPWKUP_FSP                                , RULL(0x130F010B), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_SPWKUP_FSP                                , RULL(0x140F010B), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_SPWKUP_FSP                                , RULL(0x150F010B), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_SPWKUP_FSP                                , RULL(0x200F010B), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_SPWKUP_FSP                                , RULL(0x210F010B), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_SPWKUP_FSP                                , RULL(0x220F010B), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_SPWKUP_FSP                                , RULL(0x230F010B), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_SPWKUP_FSP                                , RULL(0x240F010B), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_SPWKUP_FSP                                , RULL(0x250F010B), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_SPWKUP_FSP                                , RULL(0x260F010B), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_SPWKUP_FSP                                , RULL(0x270F010B), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_SPWKUP_FSP                                , RULL(0x280F010B), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_SPWKUP_FSP                                , RULL(0x290F010B), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_SPWKUP_FSP                                , RULL(0x2A0F010B), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_SPWKUP_FSP                                , RULL(0x2B0F010B), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_SPWKUP_FSP                                , RULL(0x2C0F010B), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_SPWKUP_FSP                                , RULL(0x2D0F010B), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_SPWKUP_FSP                                , RULL(0x2E0F010B), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_SPWKUP_FSP                                , RULL(0x2F0F010B), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_SPWKUP_FSP                                , RULL(0x300F010B), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_SPWKUP_FSP                                , RULL(0x310F010B), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_SPWKUP_FSP                                , RULL(0x320F010B), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_SPWKUP_FSP                                , RULL(0x330F010B), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_SPWKUP_FSP                                , RULL(0x340F010B), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_SPWKUP_FSP                                , RULL(0x350F010B), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_SPWKUP_FSP                                , RULL(0x360F010B), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_SPWKUP_FSP                                , RULL(0x370F010B), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_SPWKUP_HYP                                , RULL(0x100F010D), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_SPWKUP_HYP                                , RULL(0x110F010D), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_SPWKUP_HYP                                , RULL(0x120F010D), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_SPWKUP_HYP                                , RULL(0x130F010D), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_SPWKUP_HYP                                , RULL(0x140F010D), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_SPWKUP_HYP                                , RULL(0x150F010D), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_SPWKUP_HYP                                , RULL(0x200F010D), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_SPWKUP_HYP                                , RULL(0x210F010D), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_SPWKUP_HYP                                , RULL(0x220F010D), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_SPWKUP_HYP                                , RULL(0x230F010D), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_SPWKUP_HYP                                , RULL(0x240F010D), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_SPWKUP_HYP                                , RULL(0x250F010D), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_SPWKUP_HYP                                , RULL(0x260F010D), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_SPWKUP_HYP                                , RULL(0x270F010D), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_SPWKUP_HYP                                , RULL(0x280F010D), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_SPWKUP_HYP                                , RULL(0x290F010D), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_SPWKUP_HYP                                , RULL(0x2A0F010D), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_SPWKUP_HYP                                , RULL(0x2B0F010D), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_SPWKUP_HYP                                , RULL(0x2C0F010D), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_SPWKUP_HYP                                , RULL(0x2D0F010D), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_SPWKUP_HYP                                , RULL(0x2E0F010D), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_SPWKUP_HYP                                , RULL(0x2F0F010D), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_SPWKUP_HYP                                , RULL(0x300F010D), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_SPWKUP_HYP                                , RULL(0x310F010D), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_SPWKUP_HYP                                , RULL(0x320F010D), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_SPWKUP_HYP                                , RULL(0x330F010D), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_SPWKUP_HYP                                , RULL(0x340F010D), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_SPWKUP_HYP                                , RULL(0x350F010D), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_SPWKUP_HYP                                , RULL(0x360F010D), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_SPWKUP_HYP                                , RULL(0x370F010D), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_SPWKUP_OCC                                , RULL(0x100F010C), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_SPWKUP_OCC                                , RULL(0x110F010C), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_SPWKUP_OCC                                , RULL(0x120F010C), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_SPWKUP_OCC                                , RULL(0x130F010C), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_SPWKUP_OCC                                , RULL(0x140F010C), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_SPWKUP_OCC                                , RULL(0x150F010C), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_SPWKUP_OCC                                , RULL(0x200F010C), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_SPWKUP_OCC                                , RULL(0x210F010C), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_SPWKUP_OCC                                , RULL(0x220F010C), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_SPWKUP_OCC                                , RULL(0x230F010C), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_SPWKUP_OCC                                , RULL(0x240F010C), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_SPWKUP_OCC                                , RULL(0x250F010C), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_SPWKUP_OCC                                , RULL(0x260F010C), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_SPWKUP_OCC                                , RULL(0x270F010C), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_SPWKUP_OCC                                , RULL(0x280F010C), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_SPWKUP_OCC                                , RULL(0x290F010C), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_SPWKUP_OCC                                , RULL(0x2A0F010C), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_SPWKUP_OCC                                , RULL(0x2B0F010C), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_SPWKUP_OCC                                , RULL(0x2C0F010C), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_SPWKUP_OCC                                , RULL(0x2D0F010C), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_SPWKUP_OCC                                , RULL(0x2E0F010C), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_SPWKUP_OCC                                , RULL(0x2F0F010C), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_SPWKUP_OCC                                , RULL(0x300F010C), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_SPWKUP_OCC                                , RULL(0x310F010C), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_SPWKUP_OCC                                , RULL(0x320F010C), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_SPWKUP_OCC                                , RULL(0x330F010C), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_SPWKUP_OCC                                , RULL(0x340F010C), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_SPWKUP_OCC                                , RULL(0x350F010C), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_SPWKUP_OCC                                , RULL(0x360F010C), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_SPWKUP_OCC                                , RULL(0x370F010C), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_SPWKUP_OTR                                , RULL(0x100F010A), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_SPWKUP_OTR                                , RULL(0x110F010A), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_SPWKUP_OTR                                , RULL(0x120F010A), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_SPWKUP_OTR                                , RULL(0x130F010A), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_SPWKUP_OTR                                , RULL(0x140F010A), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_SPWKUP_OTR                                , RULL(0x150F010A), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_SPWKUP_OTR                                , RULL(0x200F010A), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_SPWKUP_OTR                                , RULL(0x210F010A), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_SPWKUP_OTR                                , RULL(0x220F010A), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_SPWKUP_OTR                                , RULL(0x230F010A), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_SPWKUP_OTR                                , RULL(0x240F010A), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_SPWKUP_OTR                                , RULL(0x250F010A), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_SPWKUP_OTR                                , RULL(0x260F010A), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_SPWKUP_OTR                                , RULL(0x270F010A), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_SPWKUP_OTR                                , RULL(0x280F010A), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_SPWKUP_OTR                                , RULL(0x290F010A), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_SPWKUP_OTR                                , RULL(0x2A0F010A), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_SPWKUP_OTR                                , RULL(0x2B0F010A), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_SPWKUP_OTR                                , RULL(0x2C0F010A), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_SPWKUP_OTR                                , RULL(0x2D0F010A), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_SPWKUP_OTR                                , RULL(0x2E0F010A), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_SPWKUP_OTR                                , RULL(0x2F0F010A), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_SPWKUP_OTR                                , RULL(0x300F010A), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_SPWKUP_OTR                                , RULL(0x310F010A), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_SPWKUP_OTR                                , RULL(0x320F010A), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_SPWKUP_OTR                                , RULL(0x330F010A), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_SPWKUP_OTR                                , RULL(0x340F010A), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_SPWKUP_OTR                                , RULL(0x350F010A), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_SPWKUP_OTR                                , RULL(0x360F010A), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_SPWKUP_OTR                                , RULL(0x370F010A), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_PPM_SSHFSP                                    , RULL(0x100F0111), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_SSHFSP                                    , RULL(0x110F0111), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_SSHFSP                                    , RULL(0x120F0111), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_SSHFSP                                    , RULL(0x130F0111), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_SSHFSP                                    , RULL(0x140F0111), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_SSHFSP                                    , RULL(0x150F0111), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_SSHFSP                                    , RULL(0x200F0111), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_SSHFSP                                    , RULL(0x210F0111), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_SSHFSP                                    , RULL(0x220F0111), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_SSHFSP                                    , RULL(0x230F0111), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_SSHFSP                                    , RULL(0x240F0111), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_SSHFSP                                    , RULL(0x250F0111), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_SSHFSP                                    , RULL(0x260F0111), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_SSHFSP                                    , RULL(0x270F0111), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_SSHFSP                                    , RULL(0x280F0111), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_SSHFSP                                    , RULL(0x290F0111), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_SSHFSP                                    , RULL(0x2A0F0111), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_SSHFSP                                    , RULL(0x2B0F0111), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_SSHFSP                                    , RULL(0x2C0F0111), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_SSHFSP                                    , RULL(0x2D0F0111), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_SSHFSP                                    , RULL(0x2E0F0111), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_SSHFSP                                    , RULL(0x2F0F0111), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_SSHFSP                                    , RULL(0x300F0111), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_SSHFSP                                    , RULL(0x310F0111), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_SSHFSP                                    , RULL(0x320F0111), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_SSHFSP                                    , RULL(0x330F0111), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_SSHFSP                                    , RULL(0x340F0111), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_SSHFSP                                    , RULL(0x350F0111), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_SSHFSP                                    , RULL(0x360F0111), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_SSHFSP                                    , RULL(0x370F0111), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EP00_PPM_SSHHYP                                    , RULL(0x100F0114), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_SSHHYP                                    , RULL(0x110F0114), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_SSHHYP                                    , RULL(0x120F0114), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_SSHHYP                                    , RULL(0x130F0114), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_SSHHYP                                    , RULL(0x140F0114), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_SSHHYP                                    , RULL(0x150F0114), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_SSHHYP                                    , RULL(0x200F0114), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_SSHHYP                                    , RULL(0x210F0114), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_SSHHYP                                    , RULL(0x220F0114), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_SSHHYP                                    , RULL(0x230F0114), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_SSHHYP                                    , RULL(0x240F0114), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_SSHHYP                                    , RULL(0x250F0114), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_SSHHYP                                    , RULL(0x260F0114), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_SSHHYP                                    , RULL(0x270F0114), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_SSHHYP                                    , RULL(0x280F0114), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_SSHHYP                                    , RULL(0x290F0114), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_SSHHYP                                    , RULL(0x2A0F0114), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_SSHHYP                                    , RULL(0x2B0F0114), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_SSHHYP                                    , RULL(0x2C0F0114), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_SSHHYP                                    , RULL(0x2D0F0114), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_SSHHYP                                    , RULL(0x2E0F0114), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_SSHHYP                                    , RULL(0x2F0F0114), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_SSHHYP                                    , RULL(0x300F0114), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_SSHHYP                                    , RULL(0x310F0114), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_SSHHYP                                    , RULL(0x320F0114), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_SSHHYP                                    , RULL(0x330F0114), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_SSHHYP                                    , RULL(0x340F0114), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_SSHHYP                                    , RULL(0x350F0114), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_SSHHYP                                    , RULL(0x360F0114), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_SSHHYP                                    , RULL(0x370F0114), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EP00_PPM_SSHOCC                                    , RULL(0x100F0112), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_SSHOCC                                    , RULL(0x110F0112), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_SSHOCC                                    , RULL(0x120F0112), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_SSHOCC                                    , RULL(0x130F0112), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_SSHOCC                                    , RULL(0x140F0112), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_SSHOCC                                    , RULL(0x150F0112), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_SSHOCC                                    , RULL(0x200F0112), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_SSHOCC                                    , RULL(0x210F0112), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_SSHOCC                                    , RULL(0x220F0112), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_SSHOCC                                    , RULL(0x230F0112), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_SSHOCC                                    , RULL(0x240F0112), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_SSHOCC                                    , RULL(0x250F0112), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_SSHOCC                                    , RULL(0x260F0112), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_SSHOCC                                    , RULL(0x270F0112), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_SSHOCC                                    , RULL(0x280F0112), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_SSHOCC                                    , RULL(0x290F0112), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_SSHOCC                                    , RULL(0x2A0F0112), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_SSHOCC                                    , RULL(0x2B0F0112), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_SSHOCC                                    , RULL(0x2C0F0112), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_SSHOCC                                    , RULL(0x2D0F0112), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_SSHOCC                                    , RULL(0x2E0F0112), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_SSHOCC                                    , RULL(0x2F0F0112), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_SSHOCC                                    , RULL(0x300F0112), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_SSHOCC                                    , RULL(0x310F0112), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_SSHOCC                                    , RULL(0x320F0112), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_SSHOCC                                    , RULL(0x330F0112), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_SSHOCC                                    , RULL(0x340F0112), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_SSHOCC                                    , RULL(0x350F0112), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_SSHOCC                                    , RULL(0x360F0112), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_SSHOCC                                    , RULL(0x370F0112), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EP00_PPM_SSHOTR                                    , RULL(0x100F0113), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_SSHOTR                                    , RULL(0x110F0113), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_SSHOTR                                    , RULL(0x120F0113), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_SSHOTR                                    , RULL(0x130F0113), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_SSHOTR                                    , RULL(0x140F0113), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_SSHOTR                                    , RULL(0x150F0113), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_SSHOTR                                    , RULL(0x200F0113), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_SSHOTR                                    , RULL(0x210F0113), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_SSHOTR                                    , RULL(0x220F0113), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_SSHOTR                                    , RULL(0x230F0113), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_SSHOTR                                    , RULL(0x240F0113), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_SSHOTR                                    , RULL(0x250F0113), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_SSHOTR                                    , RULL(0x260F0113), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_SSHOTR                                    , RULL(0x270F0113), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_SSHOTR                                    , RULL(0x280F0113), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_SSHOTR                                    , RULL(0x290F0113), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_SSHOTR                                    , RULL(0x2A0F0113), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_SSHOTR                                    , RULL(0x2B0F0113), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_SSHOTR                                    , RULL(0x2C0F0113), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_SSHOTR                                    , RULL(0x2D0F0113), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_SSHOTR                                    , RULL(0x2E0F0113), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_SSHOTR                                    , RULL(0x2F0F0113), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_SSHOTR                                    , RULL(0x300F0113), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_SSHOTR                                    , RULL(0x310F0113), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_SSHOTR                                    , RULL(0x320F0113), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_SSHOTR                                    , RULL(0x330F0113), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_SSHOTR                                    , RULL(0x340F0113), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_SSHOTR                                    , RULL(0x350F0113), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_SSHOTR                                    , RULL(0x360F0113), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_SSHOTR                                    , RULL(0x370F0113), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EP00_PPM_SSHSRC                                    , RULL(0x100F0110), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PPM_SSHSRC                                    , RULL(0x110F0110), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PPM_SSHSRC                                    , RULL(0x120F0110), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PPM_SSHSRC                                    , RULL(0x130F0110), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PPM_SSHSRC                                    , RULL(0x140F0110), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PPM_SSHSRC                                    , RULL(0x150F0110), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PPM_SSHSRC                                    , RULL(0x200F0110), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PPM_SSHSRC                                    , RULL(0x210F0110), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PPM_SSHSRC                                    , RULL(0x220F0110), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PPM_SSHSRC                                    , RULL(0x230F0110), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PPM_SSHSRC                                    , RULL(0x240F0110), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PPM_SSHSRC                                    , RULL(0x250F0110), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PPM_SSHSRC                                    , RULL(0x260F0110), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PPM_SSHSRC                                    , RULL(0x270F0110), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PPM_SSHSRC                                    , RULL(0x280F0110), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PPM_SSHSRC                                    , RULL(0x290F0110), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PPM_SSHSRC                                    , RULL(0x2A0F0110), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PPM_SSHSRC                                    , RULL(0x2B0F0110), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PPM_SSHSRC                                    , RULL(0x2C0F0110), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PPM_SSHSRC                                    , RULL(0x2D0F0110), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PPM_SSHSRC                                    , RULL(0x2E0F0110), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PPM_SSHSRC                                    , RULL(0x2F0F0110), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PPM_SSHSRC                                    , RULL(0x300F0110), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PPM_SSHSRC                                    , RULL(0x310F0110), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PPM_SSHSRC                                    , RULL(0x320F0110), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PPM_SSHSRC                                    , RULL(0x330F0110), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PPM_SSHSRC                                    , RULL(0x340F0110), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PPM_SSHSRC                                    , RULL(0x350F0110), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PPM_SSHSRC                                    , RULL(0x360F0110), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PPM_SSHSRC                                    , RULL(0x370F0110), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_EP00_PPM_VDMCR                                     , RULL(0x100F01B8), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_PPM_VDMCR_CLEAR                               , RULL(0x100F01B9), SH_UNT_PERV_16  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP00_PPM_VDMCR_OR                                  , RULL(0x100F01BA), SH_UNT_PERV_16  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP01_PPM_VDMCR                                     , RULL(0x110F01B8), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_PPM_VDMCR_CLEAR                               , RULL(0x110F01B9), SH_UNT_PERV_17  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP01_PPM_VDMCR_OR                                  , RULL(0x110F01BA), SH_UNT_PERV_17  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP02_PPM_VDMCR                                     , RULL(0x120F01B8), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_PPM_VDMCR_CLEAR                               , RULL(0x120F01B9), SH_UNT_PERV_18  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP02_PPM_VDMCR_OR                                  , RULL(0x120F01BA), SH_UNT_PERV_18  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP03_PPM_VDMCR                                     , RULL(0x130F01B8), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_PPM_VDMCR_CLEAR                               , RULL(0x130F01B9), SH_UNT_PERV_19  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP03_PPM_VDMCR_OR                                  , RULL(0x130F01BA), SH_UNT_PERV_19  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP04_PPM_VDMCR                                     , RULL(0x140F01B8), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_PPM_VDMCR_CLEAR                               , RULL(0x140F01B9), SH_UNT_PERV_20  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP04_PPM_VDMCR_OR                                  , RULL(0x140F01BA), SH_UNT_PERV_20  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP05_PPM_VDMCR                                     , RULL(0x150F01B8), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_PPM_VDMCR_CLEAR                               , RULL(0x150F01B9), SH_UNT_PERV_21  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP05_PPM_VDMCR_OR                                  , RULL(0x150F01BA), SH_UNT_PERV_21  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC00_PPM_VDMCR                                     , RULL(0x200F01B8), SH_UNT_PERV_32  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC00_PPM_VDMCR_CLEAR                               , RULL(0x200F01B9), SH_UNT_PERV_32  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC00_PPM_VDMCR_OR                                  , RULL(0x200F01BA), SH_UNT_PERV_32  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC01_PPM_VDMCR                                     , RULL(0x210F01B8), SH_UNT_PERV_33  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC01_PPM_VDMCR_CLEAR                               , RULL(0x210F01B9), SH_UNT_PERV_33  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC01_PPM_VDMCR_OR                                  , RULL(0x210F01BA), SH_UNT_PERV_33  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC02_PPM_VDMCR                                     , RULL(0x220F01B8), SH_UNT_PERV_34  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC02_PPM_VDMCR_CLEAR                               , RULL(0x220F01B9), SH_UNT_PERV_34  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC02_PPM_VDMCR_OR                                  , RULL(0x220F01BA), SH_UNT_PERV_34  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC03_PPM_VDMCR                                     , RULL(0x230F01B8), SH_UNT_PERV_35  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC03_PPM_VDMCR_CLEAR                               , RULL(0x230F01B9), SH_UNT_PERV_35  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC03_PPM_VDMCR_OR                                  , RULL(0x230F01BA), SH_UNT_PERV_35  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC04_PPM_VDMCR                                     , RULL(0x240F01B8), SH_UNT_PERV_36  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC04_PPM_VDMCR_CLEAR                               , RULL(0x240F01B9), SH_UNT_PERV_36  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC04_PPM_VDMCR_OR                                  , RULL(0x240F01BA), SH_UNT_PERV_36  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC05_PPM_VDMCR                                     , RULL(0x250F01B8), SH_UNT_PERV_37  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC05_PPM_VDMCR_CLEAR                               , RULL(0x250F01B9), SH_UNT_PERV_37  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC05_PPM_VDMCR_OR                                  , RULL(0x250F01BA), SH_UNT_PERV_37  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC06_PPM_VDMCR                                     , RULL(0x260F01B8), SH_UNT_PERV_38  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC06_PPM_VDMCR_CLEAR                               , RULL(0x260F01B9), SH_UNT_PERV_38  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC06_PPM_VDMCR_OR                                  , RULL(0x260F01BA), SH_UNT_PERV_38  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC07_PPM_VDMCR                                     , RULL(0x270F01B8), SH_UNT_PERV_39  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC07_PPM_VDMCR_CLEAR                               , RULL(0x270F01B9), SH_UNT_PERV_39  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC07_PPM_VDMCR_OR                                  , RULL(0x270F01BA), SH_UNT_PERV_39  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC08_PPM_VDMCR                                     , RULL(0x280F01B8), SH_UNT_PERV_40  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC08_PPM_VDMCR_CLEAR                               , RULL(0x280F01B9), SH_UNT_PERV_40  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC08_PPM_VDMCR_OR                                  , RULL(0x280F01BA), SH_UNT_PERV_40  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC09_PPM_VDMCR                                     , RULL(0x290F01B8), SH_UNT_PERV_41  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC09_PPM_VDMCR_CLEAR                               , RULL(0x290F01B9), SH_UNT_PERV_41  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC09_PPM_VDMCR_OR                                  , RULL(0x290F01BA), SH_UNT_PERV_41  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC10_PPM_VDMCR                                     , RULL(0x2A0F01B8), SH_UNT_PERV_42  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC10_PPM_VDMCR_CLEAR                               , RULL(0x2A0F01B9), SH_UNT_PERV_42  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC10_PPM_VDMCR_OR                                  , RULL(0x2A0F01BA), SH_UNT_PERV_42  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC11_PPM_VDMCR                                     , RULL(0x2B0F01B8), SH_UNT_PERV_43  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC11_PPM_VDMCR_CLEAR                               , RULL(0x2B0F01B9), SH_UNT_PERV_43  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC11_PPM_VDMCR_OR                                  , RULL(0x2B0F01BA), SH_UNT_PERV_43  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC12_PPM_VDMCR                                     , RULL(0x2C0F01B8), SH_UNT_PERV_44  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC12_PPM_VDMCR_CLEAR                               , RULL(0x2C0F01B9), SH_UNT_PERV_44  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC12_PPM_VDMCR_OR                                  , RULL(0x2C0F01BA), SH_UNT_PERV_44  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC13_PPM_VDMCR                                     , RULL(0x2D0F01B8), SH_UNT_PERV_45  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC13_PPM_VDMCR_CLEAR                               , RULL(0x2D0F01B9), SH_UNT_PERV_45  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC13_PPM_VDMCR_OR                                  , RULL(0x2D0F01BA), SH_UNT_PERV_45  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC14_PPM_VDMCR                                     , RULL(0x2E0F01B8), SH_UNT_PERV_46  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC14_PPM_VDMCR_CLEAR                               , RULL(0x2E0F01B9), SH_UNT_PERV_46  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC14_PPM_VDMCR_OR                                  , RULL(0x2E0F01BA), SH_UNT_PERV_46  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC15_PPM_VDMCR                                     , RULL(0x2F0F01B8), SH_UNT_PERV_47  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC15_PPM_VDMCR_CLEAR                               , RULL(0x2F0F01B9), SH_UNT_PERV_47  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC15_PPM_VDMCR_OR                                  , RULL(0x2F0F01BA), SH_UNT_PERV_47  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC16_PPM_VDMCR                                     , RULL(0x300F01B8), SH_UNT_PERV_48  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC16_PPM_VDMCR_CLEAR                               , RULL(0x300F01B9), SH_UNT_PERV_48  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC16_PPM_VDMCR_OR                                  , RULL(0x300F01BA), SH_UNT_PERV_48  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC17_PPM_VDMCR                                     , RULL(0x310F01B8), SH_UNT_PERV_49  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC17_PPM_VDMCR_CLEAR                               , RULL(0x310F01B9), SH_UNT_PERV_49  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC17_PPM_VDMCR_OR                                  , RULL(0x310F01BA), SH_UNT_PERV_49  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC18_PPM_VDMCR                                     , RULL(0x320F01B8), SH_UNT_PERV_50  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC18_PPM_VDMCR_CLEAR                               , RULL(0x320F01B9), SH_UNT_PERV_50  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC18_PPM_VDMCR_OR                                  , RULL(0x320F01BA), SH_UNT_PERV_50  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC19_PPM_VDMCR                                     , RULL(0x330F01B8), SH_UNT_PERV_51  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC19_PPM_VDMCR_CLEAR                               , RULL(0x330F01B9), SH_UNT_PERV_51  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC19_PPM_VDMCR_OR                                  , RULL(0x330F01BA), SH_UNT_PERV_51  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC20_PPM_VDMCR                                     , RULL(0x340F01B8), SH_UNT_PERV_52  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC20_PPM_VDMCR_CLEAR                               , RULL(0x340F01B9), SH_UNT_PERV_52  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC20_PPM_VDMCR_OR                                  , RULL(0x340F01BA), SH_UNT_PERV_52  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC21_PPM_VDMCR                                     , RULL(0x350F01B8), SH_UNT_PERV_53  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC21_PPM_VDMCR_CLEAR                               , RULL(0x350F01B9), SH_UNT_PERV_53  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC21_PPM_VDMCR_OR                                  , RULL(0x350F01BA), SH_UNT_PERV_53  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC22_PPM_VDMCR                                     , RULL(0x360F01B8), SH_UNT_PERV_54  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC22_PPM_VDMCR_CLEAR                               , RULL(0x360F01B9), SH_UNT_PERV_54  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC22_PPM_VDMCR_OR                                  , RULL(0x360F01BA), SH_UNT_PERV_54  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EC23_PPM_VDMCR                                     , RULL(0x370F01B8), SH_UNT_PERV_55  , SH_ACS_SCOM_RW   );
+REG64( PERV_EC23_PPM_VDMCR_CLEAR                               , RULL(0x370F01B9), SH_UNT_PERV_55  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EC23_PPM_VDMCR_OR                                  , RULL(0x370F01BA), SH_UNT_PERV_55  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_PRE_COUNTER_REG                                    , RULL(0x000F0028), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_PRE_COUNTER_REG                                 , RULL(0x010F0028), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_PRE_COUNTER_REG                                 , RULL(0x020F0028), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_PRE_COUNTER_REG                                 , RULL(0x030F0028), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_PRE_COUNTER_REG                                 , RULL(0x040F0028), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_PRE_COUNTER_REG                                 , RULL(0x050F0028), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_PRE_COUNTER_REG                                 , RULL(0x060F0028), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_PRE_COUNTER_REG                               , RULL(0x070F0028), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_PRE_COUNTER_REG                               , RULL(0x080F0028), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_PRE_COUNTER_REG                                , RULL(0x090F0028), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_PRE_COUNTER_REG                                , RULL(0x0C0F0028), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_PRE_COUNTER_REG                               , RULL(0x0D0F0028), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_PRE_COUNTER_REG                               , RULL(0x0E0F0028), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_PRE_COUNTER_REG                               , RULL(0x0F0F0028), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_PRE_COUNTER_REG                               , RULL(0x100F0028), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PRE_COUNTER_REG                               , RULL(0x110F0028), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PRE_COUNTER_REG                               , RULL(0x120F0028), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PRE_COUNTER_REG                               , RULL(0x130F0028), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PRE_COUNTER_REG                               , RULL(0x140F0028), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PRE_COUNTER_REG                               , RULL(0x150F0028), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PRE_COUNTER_REG                               , RULL(0x200F0028), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PRE_COUNTER_REG                               , RULL(0x210F0028), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PRE_COUNTER_REG                               , RULL(0x220F0028), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PRE_COUNTER_REG                               , RULL(0x230F0028), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PRE_COUNTER_REG                               , RULL(0x240F0028), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PRE_COUNTER_REG                               , RULL(0x250F0028), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PRE_COUNTER_REG                               , RULL(0x260F0028), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PRE_COUNTER_REG                               , RULL(0x270F0028), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PRE_COUNTER_REG                               , RULL(0x280F0028), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PRE_COUNTER_REG                               , RULL(0x290F0028), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PRE_COUNTER_REG                               , RULL(0x2A0F0028), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PRE_COUNTER_REG                               , RULL(0x2B0F0028), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PRE_COUNTER_REG                               , RULL(0x2C0F0028), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PRE_COUNTER_REG                               , RULL(0x2D0F0028), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PRE_COUNTER_REG                               , RULL(0x2E0F0028), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PRE_COUNTER_REG                               , RULL(0x2F0F0028), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PRE_COUNTER_REG                               , RULL(0x300F0028), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PRE_COUNTER_REG                               , RULL(0x310F0028), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PRE_COUNTER_REG                               , RULL(0x320F0028), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PRE_COUNTER_REG                               , RULL(0x330F0028), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PRE_COUNTER_REG                               , RULL(0x340F0028), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PRE_COUNTER_REG                               , RULL(0x350F0028), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PRE_COUNTER_REG                               , RULL(0x360F0028), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PRE_COUNTER_REG                               , RULL(0x370F0028), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_PRIMARY_ADDRESS_REG                                , RULL(0x000F0000), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_TP_PRIMARY_ADDRESS_REG                             , RULL(0x010F0000), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_PRIMARY_ADDRESS_REG                             , RULL(0x020F0000), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_PRIMARY_ADDRESS_REG                             , RULL(0x030F0000), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_PRIMARY_ADDRESS_REG                             , RULL(0x040F0000), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_PRIMARY_ADDRESS_REG                             , RULL(0x050F0000), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_PRIMARY_ADDRESS_REG                             , RULL(0x060F0000), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_PRIMARY_ADDRESS_REG                           , RULL(0x070F0000), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_PRIMARY_ADDRESS_REG                           , RULL(0x080F0000), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_PRIMARY_ADDRESS_REG                            , RULL(0x090F0000), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_PRIMARY_ADDRESS_REG                            , RULL(0x0C0F0000), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_PRIMARY_ADDRESS_REG                           , RULL(0x0D0F0000), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_PRIMARY_ADDRESS_REG                           , RULL(0x0E0F0000), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_PRIMARY_ADDRESS_REG                           , RULL(0x0F0F0000), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_PRIMARY_ADDRESS_REG                           , RULL(0x100F0000), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PRIMARY_ADDRESS_REG                           , RULL(0x110F0000), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PRIMARY_ADDRESS_REG                           , RULL(0x120F0000), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PRIMARY_ADDRESS_REG                           , RULL(0x130F0000), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PRIMARY_ADDRESS_REG                           , RULL(0x140F0000), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PRIMARY_ADDRESS_REG                           , RULL(0x150F0000), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PRIMARY_ADDRESS_REG                           , RULL(0x200F0000), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PRIMARY_ADDRESS_REG                           , RULL(0x210F0000), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PRIMARY_ADDRESS_REG                           , RULL(0x220F0000), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PRIMARY_ADDRESS_REG                           , RULL(0x230F0000), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PRIMARY_ADDRESS_REG                           , RULL(0x240F0000), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PRIMARY_ADDRESS_REG                           , RULL(0x250F0000), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PRIMARY_ADDRESS_REG                           , RULL(0x260F0000), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PRIMARY_ADDRESS_REG                           , RULL(0x270F0000), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PRIMARY_ADDRESS_REG                           , RULL(0x280F0000), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PRIMARY_ADDRESS_REG                           , RULL(0x290F0000), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PRIMARY_ADDRESS_REG                           , RULL(0x2A0F0000), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PRIMARY_ADDRESS_REG                           , RULL(0x2B0F0000), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PRIMARY_ADDRESS_REG                           , RULL(0x2C0F0000), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PRIMARY_ADDRESS_REG                           , RULL(0x2D0F0000), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PRIMARY_ADDRESS_REG                           , RULL(0x2E0F0000), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PRIMARY_ADDRESS_REG                           , RULL(0x2F0F0000), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PRIMARY_ADDRESS_REG                           , RULL(0x300F0000), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PRIMARY_ADDRESS_REG                           , RULL(0x310F0000), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PRIMARY_ADDRESS_REG                           , RULL(0x320F0000), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PRIMARY_ADDRESS_REG                           , RULL(0x330F0000), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PRIMARY_ADDRESS_REG                           , RULL(0x340F0000), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PRIMARY_ADDRESS_REG                           , RULL(0x350F0000), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PRIMARY_ADDRESS_REG                           , RULL(0x360F0000), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PRIMARY_ADDRESS_REG                           , RULL(0x370F0000), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_PROTECT_MODE_REG                                   , RULL(0x000F03FE), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_PROTECT_MODE_REG                                , RULL(0x010F03FE), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_PROTECT_MODE_REG                                , RULL(0x020F03FE), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_PROTECT_MODE_REG                                , RULL(0x030F03FE), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_PROTECT_MODE_REG                                , RULL(0x040F03FE), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_PROTECT_MODE_REG                                , RULL(0x050F03FE), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_PROTECT_MODE_REG                                , RULL(0x060F03FE), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_PROTECT_MODE_REG                              , RULL(0x070F03FE), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_PROTECT_MODE_REG                              , RULL(0x080F03FE), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_PROTECT_MODE_REG                               , RULL(0x090F03FE), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_PROTECT_MODE_REG                               , RULL(0x0C0F03FE), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_PROTECT_MODE_REG                              , RULL(0x0D0F03FE), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_PROTECT_MODE_REG                              , RULL(0x0E0F03FE), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_PROTECT_MODE_REG                              , RULL(0x0F0F03FE), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_PROTECT_MODE_REG                              , RULL(0x100F03FE), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_PROTECT_MODE_REG                              , RULL(0x110F03FE), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_PROTECT_MODE_REG                              , RULL(0x120F03FE), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_PROTECT_MODE_REG                              , RULL(0x130F03FE), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_PROTECT_MODE_REG                              , RULL(0x140F03FE), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_PROTECT_MODE_REG                              , RULL(0x150F03FE), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_PROTECT_MODE_REG                              , RULL(0x200F03FE), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_PROTECT_MODE_REG                              , RULL(0x210F03FE), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_PROTECT_MODE_REG                              , RULL(0x220F03FE), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_PROTECT_MODE_REG                              , RULL(0x230F03FE), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_PROTECT_MODE_REG                              , RULL(0x240F03FE), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_PROTECT_MODE_REG                              , RULL(0x250F03FE), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_PROTECT_MODE_REG                              , RULL(0x260F03FE), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_PROTECT_MODE_REG                              , RULL(0x270F03FE), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_PROTECT_MODE_REG                              , RULL(0x280F03FE), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_PROTECT_MODE_REG                              , RULL(0x290F03FE), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_PROTECT_MODE_REG                              , RULL(0x2A0F03FE), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_PROTECT_MODE_REG                              , RULL(0x2B0F03FE), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_PROTECT_MODE_REG                              , RULL(0x2C0F03FE), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_PROTECT_MODE_REG                              , RULL(0x2D0F03FE), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_PROTECT_MODE_REG                              , RULL(0x2E0F03FE), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_PROTECT_MODE_REG                              , RULL(0x2F0F03FE), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_PROTECT_MODE_REG                              , RULL(0x300F03FE), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_PROTECT_MODE_REG                              , RULL(0x310F03FE), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_PROTECT_MODE_REG                              , RULL(0x320F03FE), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_PROTECT_MODE_REG                              , RULL(0x330F03FE), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_PROTECT_MODE_REG                              , RULL(0x340F03FE), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_PROTECT_MODE_REG                              , RULL(0x350F03FE), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_PROTECT_MODE_REG                              , RULL(0x360F03FE), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_PROTECT_MODE_REG                              , RULL(0x370F03FE), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_PSCOM_ERROR_MASK                                   , RULL(0x00010002), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_PSCOM_ERROR_MASK                                , RULL(0x01010002), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_PSCOM_MODE_REG                                     , RULL(0x00010000), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_PSCOM_MODE_REG                                  , RULL(0x01010000), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_PSCOM_STATUS_ERROR_REG                             , RULL(0x00010001), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_PSCOM_STATUS_ERROR_REG                          , RULL(0x01010001), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_EP00_QPPM_DPLL_CTRL                                , RULL(0x100F0152), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_QPPM_DPLL_CTRL_CLEAR                          , RULL(0x100F0153), SH_UNT_PERV_16  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP00_QPPM_DPLL_CTRL_OR                             , RULL(0x100F0154), SH_UNT_PERV_16  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP01_QPPM_DPLL_CTRL                                , RULL(0x110F0152), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_QPPM_DPLL_CTRL_CLEAR                          , RULL(0x110F0153), SH_UNT_PERV_17  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP01_QPPM_DPLL_CTRL_OR                             , RULL(0x110F0154), SH_UNT_PERV_17  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP02_QPPM_DPLL_CTRL                                , RULL(0x120F0152), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_QPPM_DPLL_CTRL_CLEAR                          , RULL(0x120F0153), SH_UNT_PERV_18  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP02_QPPM_DPLL_CTRL_OR                             , RULL(0x120F0154), SH_UNT_PERV_18  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP03_QPPM_DPLL_CTRL                                , RULL(0x130F0152), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_QPPM_DPLL_CTRL_CLEAR                          , RULL(0x130F0153), SH_UNT_PERV_19  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP03_QPPM_DPLL_CTRL_OR                             , RULL(0x130F0154), SH_UNT_PERV_19  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP04_QPPM_DPLL_CTRL                                , RULL(0x140F0152), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_QPPM_DPLL_CTRL_CLEAR                          , RULL(0x140F0153), SH_UNT_PERV_20  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP04_QPPM_DPLL_CTRL_OR                             , RULL(0x140F0154), SH_UNT_PERV_20  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP05_QPPM_DPLL_CTRL                                , RULL(0x150F0152), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_QPPM_DPLL_CTRL_CLEAR                          , RULL(0x150F0153), SH_UNT_PERV_21  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP05_QPPM_DPLL_CTRL_OR                             , RULL(0x150F0154), SH_UNT_PERV_21  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EP00_QPPM_DPLL_FREQ                                , RULL(0x100F0151), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_QPPM_DPLL_FREQ                                , RULL(0x110F0151), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_QPPM_DPLL_FREQ                                , RULL(0x120F0151), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_QPPM_DPLL_FREQ                                , RULL(0x130F0151), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_QPPM_DPLL_FREQ                                , RULL(0x140F0151), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_QPPM_DPLL_FREQ                                , RULL(0x150F0151), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_QPPM_DPLL_ICHAR                               , RULL(0x100F0157), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_QPPM_DPLL_ICHAR                               , RULL(0x110F0157), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_QPPM_DPLL_ICHAR                               , RULL(0x120F0157), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_QPPM_DPLL_ICHAR                               , RULL(0x130F0157), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_QPPM_DPLL_ICHAR                               , RULL(0x140F0157), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_QPPM_DPLL_ICHAR                               , RULL(0x150F0157), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EP00_QPPM_DPLL_OCHAR                               , RULL(0x100F0156), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_QPPM_DPLL_OCHAR                               , RULL(0x110F0156), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_QPPM_DPLL_OCHAR                               , RULL(0x120F0156), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_QPPM_DPLL_OCHAR                               , RULL(0x130F0156), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_QPPM_DPLL_OCHAR                               , RULL(0x140F0156), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_QPPM_DPLL_OCHAR                               , RULL(0x150F0156), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EP00_QPPM_DPLL_STAT                                , RULL(0x100F0155), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_QPPM_DPLL_STAT                                , RULL(0x110F0155), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_QPPM_DPLL_STAT                                , RULL(0x120F0155), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_QPPM_DPLL_STAT                                , RULL(0x130F0155), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_QPPM_DPLL_STAT                                , RULL(0x140F0155), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_QPPM_DPLL_STAT                                , RULL(0x150F0155), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EP00_QPPM_ERR                                      , RULL(0x100F0121), SH_UNT_PERV_16  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EP01_QPPM_ERR                                      , RULL(0x110F0121), SH_UNT_PERV_17  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EP02_QPPM_ERR                                      , RULL(0x120F0121), SH_UNT_PERV_18  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EP03_QPPM_ERR                                      , RULL(0x130F0121), SH_UNT_PERV_19  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EP04_QPPM_ERR                                      , RULL(0x140F0121), SH_UNT_PERV_20  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EP05_QPPM_ERR                                      , RULL(0x150F0121), SH_UNT_PERV_21  ,
+       SH_ACS_SCOM_WCLEAR );
+
+REG64( PERV_EP00_QPPM_ERRMSK                                   , RULL(0x100F0122), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_QPPM_ERRMSK                                   , RULL(0x110F0122), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_QPPM_ERRMSK                                   , RULL(0x120F0122), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_QPPM_ERRMSK                                   , RULL(0x130F0122), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_QPPM_ERRMSK                                   , RULL(0x140F0122), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_QPPM_ERRMSK                                   , RULL(0x150F0122), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_QPPM_ERRSUM                                   , RULL(0x100F0120), SH_UNT_PERV_16  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EP01_QPPM_ERRSUM                                   , RULL(0x110F0120), SH_UNT_PERV_17  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EP02_QPPM_ERRSUM                                   , RULL(0x120F0120), SH_UNT_PERV_18  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EP03_QPPM_ERRSUM                                   , RULL(0x130F0120), SH_UNT_PERV_19  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EP04_QPPM_ERRSUM                                   , RULL(0x140F0120), SH_UNT_PERV_20  ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_EP05_QPPM_ERRSUM                                   , RULL(0x150F0120), SH_UNT_PERV_21  ,
+       SH_ACS_SCOM_WCLEAR );
+
+REG64( PERV_EP00_QPPM_EXCGCR                                   , RULL(0x100F0165), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_QPPM_EXCGCR_CLEAR                             , RULL(0x100F0166), SH_UNT_PERV_16  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP00_QPPM_EXCGCR_OR                                , RULL(0x100F0167), SH_UNT_PERV_16  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP01_QPPM_EXCGCR                                   , RULL(0x110F0165), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_QPPM_EXCGCR_CLEAR                             , RULL(0x110F0166), SH_UNT_PERV_17  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP01_QPPM_EXCGCR_OR                                , RULL(0x110F0167), SH_UNT_PERV_17  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP02_QPPM_EXCGCR                                   , RULL(0x120F0165), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_QPPM_EXCGCR_CLEAR                             , RULL(0x120F0166), SH_UNT_PERV_18  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP02_QPPM_EXCGCR_OR                                , RULL(0x120F0167), SH_UNT_PERV_18  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP03_QPPM_EXCGCR                                   , RULL(0x130F0165), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_QPPM_EXCGCR_CLEAR                             , RULL(0x130F0166), SH_UNT_PERV_19  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP03_QPPM_EXCGCR_OR                                , RULL(0x130F0167), SH_UNT_PERV_19  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP04_QPPM_EXCGCR                                   , RULL(0x140F0165), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_QPPM_EXCGCR_CLEAR                             , RULL(0x140F0166), SH_UNT_PERV_20  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP04_QPPM_EXCGCR_OR                                , RULL(0x140F0167), SH_UNT_PERV_20  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP05_QPPM_EXCGCR                                   , RULL(0x150F0165), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_QPPM_EXCGCR_CLEAR                             , RULL(0x150F0166), SH_UNT_PERV_21  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP05_QPPM_EXCGCR_OR                                , RULL(0x150F0167), SH_UNT_PERV_21  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EP00_QPPM_OCCHB                                    , RULL(0x100F015F), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_QPPM_OCCHB                                    , RULL(0x110F015F), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_QPPM_OCCHB                                    , RULL(0x120F015F), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_QPPM_OCCHB                                    , RULL(0x130F015F), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_QPPM_OCCHB                                    , RULL(0x140F015F), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_QPPM_OCCHB                                    , RULL(0x150F015F), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_QPPM_QACCR                                    , RULL(0x100F0160), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_QPPM_QACCR_CLEAR                              , RULL(0x100F0161), SH_UNT_PERV_16  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP00_QPPM_QACCR_OR                                 , RULL(0x100F0162), SH_UNT_PERV_16  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP01_QPPM_QACCR                                    , RULL(0x110F0160), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_QPPM_QACCR_CLEAR                              , RULL(0x110F0161), SH_UNT_PERV_17  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP01_QPPM_QACCR_OR                                 , RULL(0x110F0162), SH_UNT_PERV_17  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP02_QPPM_QACCR                                    , RULL(0x120F0160), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_QPPM_QACCR_CLEAR                              , RULL(0x120F0161), SH_UNT_PERV_18  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP02_QPPM_QACCR_OR                                 , RULL(0x120F0162), SH_UNT_PERV_18  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP03_QPPM_QACCR                                    , RULL(0x130F0160), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_QPPM_QACCR_CLEAR                              , RULL(0x130F0161), SH_UNT_PERV_19  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP03_QPPM_QACCR_OR                                 , RULL(0x130F0162), SH_UNT_PERV_19  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP04_QPPM_QACCR                                    , RULL(0x140F0160), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_QPPM_QACCR_CLEAR                              , RULL(0x140F0161), SH_UNT_PERV_20  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP04_QPPM_QACCR_OR                                 , RULL(0x140F0162), SH_UNT_PERV_20  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP05_QPPM_QACCR                                    , RULL(0x150F0160), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_QPPM_QACCR_CLEAR                              , RULL(0x150F0161), SH_UNT_PERV_21  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP05_QPPM_QACCR_OR                                 , RULL(0x150F0162), SH_UNT_PERV_21  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EP00_QPPM_QACSR                                    , RULL(0x100F0163), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_QPPM_QACSR                                    , RULL(0x110F0163), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_QPPM_QACSR                                    , RULL(0x120F0163), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_QPPM_QACSR                                    , RULL(0x130F0163), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_QPPM_QACSR                                    , RULL(0x140F0163), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_QPPM_QACSR                                    , RULL(0x150F0163), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_EP00_QPPM_QCCR_SCOM                                , RULL(0x100F01BD), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP00_QPPM_QCCR_SCOM1                               , RULL(0x100F01BE), SH_UNT_PERV_16  , SH_ACS_SCOM1     );
+REG64( PERV_EP00_QPPM_QCCR_SCOM2                               , RULL(0x100F01BF), SH_UNT_PERV_16  , SH_ACS_SCOM2     );
+REG64( PERV_EP01_QPPM_QCCR_SCOM                                , RULL(0x110F01BD), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP01_QPPM_QCCR_SCOM1                               , RULL(0x110F01BE), SH_UNT_PERV_17  , SH_ACS_SCOM1     );
+REG64( PERV_EP01_QPPM_QCCR_SCOM2                               , RULL(0x110F01BF), SH_UNT_PERV_17  , SH_ACS_SCOM2     );
+REG64( PERV_EP02_QPPM_QCCR_SCOM                                , RULL(0x120F01BD), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP02_QPPM_QCCR_SCOM1                               , RULL(0x120F01BE), SH_UNT_PERV_18  , SH_ACS_SCOM1     );
+REG64( PERV_EP02_QPPM_QCCR_SCOM2                               , RULL(0x120F01BF), SH_UNT_PERV_18  , SH_ACS_SCOM2     );
+REG64( PERV_EP03_QPPM_QCCR_SCOM                                , RULL(0x130F01BD), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP03_QPPM_QCCR_SCOM1                               , RULL(0x130F01BE), SH_UNT_PERV_19  , SH_ACS_SCOM1     );
+REG64( PERV_EP03_QPPM_QCCR_SCOM2                               , RULL(0x130F01BF), SH_UNT_PERV_19  , SH_ACS_SCOM2     );
+REG64( PERV_EP04_QPPM_QCCR_SCOM                                , RULL(0x140F01BD), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP04_QPPM_QCCR_SCOM1                               , RULL(0x140F01BE), SH_UNT_PERV_20  , SH_ACS_SCOM1     );
+REG64( PERV_EP04_QPPM_QCCR_SCOM2                               , RULL(0x140F01BF), SH_UNT_PERV_20  , SH_ACS_SCOM2     );
+REG64( PERV_EP05_QPPM_QCCR_SCOM                                , RULL(0x150F01BD), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EP05_QPPM_QCCR_SCOM1                               , RULL(0x150F01BE), SH_UNT_PERV_21  , SH_ACS_SCOM1     );
+REG64( PERV_EP05_QPPM_QCCR_SCOM2                               , RULL(0x150F01BF), SH_UNT_PERV_21  , SH_ACS_SCOM2     );
+
+REG64( PERV_EP00_QPPM_QPMMR                                    , RULL(0x100F0103), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP00_QPPM_QPMMR_CLEAR                              , RULL(0x100F0104), SH_UNT_PERV_16  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP00_QPPM_QPMMR_OR                                 , RULL(0x100F0105), SH_UNT_PERV_16  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP01_QPPM_QPMMR                                    , RULL(0x110F0103), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_QPPM_QPMMR_CLEAR                              , RULL(0x110F0104), SH_UNT_PERV_17  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP01_QPPM_QPMMR_OR                                 , RULL(0x110F0105), SH_UNT_PERV_17  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP02_QPPM_QPMMR                                    , RULL(0x120F0103), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_QPPM_QPMMR_CLEAR                              , RULL(0x120F0104), SH_UNT_PERV_18  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP02_QPPM_QPMMR_OR                                 , RULL(0x120F0105), SH_UNT_PERV_18  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP03_QPPM_QPMMR                                    , RULL(0x130F0103), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_QPPM_QPMMR_CLEAR                              , RULL(0x130F0104), SH_UNT_PERV_19  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP03_QPPM_QPMMR_OR                                 , RULL(0x130F0105), SH_UNT_PERV_19  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP04_QPPM_QPMMR                                    , RULL(0x140F0103), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_QPPM_QPMMR_CLEAR                              , RULL(0x140F0104), SH_UNT_PERV_20  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP04_QPPM_QPMMR_OR                                 , RULL(0x140F0105), SH_UNT_PERV_20  , SH_ACS_SCOM2_OR  );
+REG64( PERV_EP05_QPPM_QPMMR                                    , RULL(0x150F0103), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_QPPM_QPMMR_CLEAR                              , RULL(0x150F0104), SH_UNT_PERV_21  ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( PERV_EP05_QPPM_QPMMR_OR                                 , RULL(0x150F0105), SH_UNT_PERV_21  , SH_ACS_SCOM2_OR  );
+
+REG64( PERV_EP00_QPPM_VDMCFGR                                  , RULL(0x100F01B6), SH_UNT_PERV_16  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP01_QPPM_VDMCFGR                                  , RULL(0x110F01B6), SH_UNT_PERV_17  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP02_QPPM_VDMCFGR                                  , RULL(0x120F01B6), SH_UNT_PERV_18  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP03_QPPM_VDMCFGR                                  , RULL(0x130F01B6), SH_UNT_PERV_19  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP04_QPPM_VDMCFGR                                  , RULL(0x140F01B6), SH_UNT_PERV_20  , SH_ACS_SCOM_RW   );
+REG64( PERV_EP05_QPPM_VDMCFGR                                  , RULL(0x150F01B6), SH_UNT_PERV_21  , SH_ACS_SCOM_RW   );
+
+REG64( PERV_EP00_QPPM_VOLT_CHAR                                , RULL(0x100F01BB), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_QPPM_VOLT_CHAR                                , RULL(0x110F01BB), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_QPPM_VOLT_CHAR                                , RULL(0x120F01BB), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_QPPM_VOLT_CHAR                                , RULL(0x130F01BB), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_QPPM_VOLT_CHAR                                , RULL(0x140F01BB), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_QPPM_VOLT_CHAR                                , RULL(0x150F01BB), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+
+REG32( PERV_FSISHIFT_READ_BUFFER_FSI                           , RULL(0x00000C03), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_READ_BUFFER_FSI_BYTE                      , RULL(0x00000C0C), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG64( PERV_RECOV_INTERRUPT_REG                                , RULL(0x000F001B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_RECOV_INTERRUPT_REG                             , RULL(0x010F001B), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_RECOV_INTERRUPT_REG                             , RULL(0x020F001B), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_RECOV_INTERRUPT_REG                             , RULL(0x030F001B), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_RECOV_INTERRUPT_REG                             , RULL(0x040F001B), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_RECOV_INTERRUPT_REG                             , RULL(0x050F001B), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_RECOV_INTERRUPT_REG                             , RULL(0x060F001B), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_RECOV_INTERRUPT_REG                           , RULL(0x070F001B), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_RECOV_INTERRUPT_REG                           , RULL(0x080F001B), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_RECOV_INTERRUPT_REG                            , RULL(0x090F001B), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_RECOV_INTERRUPT_REG                            , RULL(0x0C0F001B), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_RECOV_INTERRUPT_REG                           , RULL(0x0D0F001B), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_RECOV_INTERRUPT_REG                           , RULL(0x0E0F001B), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_RECOV_INTERRUPT_REG                           , RULL(0x0F0F001B), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_RECOV_INTERRUPT_REG                           , RULL(0x100F001B), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_RECOV_INTERRUPT_REG                           , RULL(0x110F001B), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_RECOV_INTERRUPT_REG                           , RULL(0x120F001B), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_RECOV_INTERRUPT_REG                           , RULL(0x130F001B), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_RECOV_INTERRUPT_REG                           , RULL(0x140F001B), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_RECOV_INTERRUPT_REG                           , RULL(0x150F001B), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_RECOV_INTERRUPT_REG                           , RULL(0x200F001B), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_RECOV_INTERRUPT_REG                           , RULL(0x210F001B), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_RECOV_INTERRUPT_REG                           , RULL(0x220F001B), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_RECOV_INTERRUPT_REG                           , RULL(0x230F001B), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_RECOV_INTERRUPT_REG                           , RULL(0x240F001B), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_RECOV_INTERRUPT_REG                           , RULL(0x250F001B), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_RECOV_INTERRUPT_REG                           , RULL(0x260F001B), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_RECOV_INTERRUPT_REG                           , RULL(0x270F001B), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_RECOV_INTERRUPT_REG                           , RULL(0x280F001B), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_RECOV_INTERRUPT_REG                           , RULL(0x290F001B), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_RECOV_INTERRUPT_REG                           , RULL(0x2A0F001B), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_RECOV_INTERRUPT_REG                           , RULL(0x2B0F001B), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_RECOV_INTERRUPT_REG                           , RULL(0x2C0F001B), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_RECOV_INTERRUPT_REG                           , RULL(0x2D0F001B), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_RECOV_INTERRUPT_REG                           , RULL(0x2E0F001B), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_RECOV_INTERRUPT_REG                           , RULL(0x2F0F001B), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_RECOV_INTERRUPT_REG                           , RULL(0x300F001B), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_RECOV_INTERRUPT_REG                           , RULL(0x310F001B), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_RECOV_INTERRUPT_REG                           , RULL(0x320F001B), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_RECOV_INTERRUPT_REG                           , RULL(0x330F001B), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_RECOV_INTERRUPT_REG                           , RULL(0x340F001B), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_RECOV_INTERRUPT_REG                           , RULL(0x350F001B), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_RECOV_INTERRUPT_REG                           , RULL(0x360F001B), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_RECOV_INTERRUPT_REG                           , RULL(0x370F001B), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_REC_ACK_REG                                        , RULL(0x000F0010), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_REC_ACK_REG                                    , RULL(0x000F0010), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_REC_ERR_REG0                                       , RULL(0x000F0011), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_PIB_REC_ERR_REG0                                   , RULL(0x000F0011), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_REC_ERR_REG1                                       , RULL(0x000F0012), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_REC_ERR_REG1                                   , RULL(0x000F0012), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_REC_ERR_REG2                                       , RULL(0x000F0013), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_REC_ERR_REG2                                   , RULL(0x000F0013), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_REC_ERR_REG3                                       , RULL(0x000F0014), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_REC_ERR_REG3                                   , RULL(0x000F0014), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_RESET                                              , RULL(0x00030004), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_PIB_RESET                                          , RULL(0x00030004), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+REG64( PERV_0_PIB2OPB0_RESET                                   , RULL(0x00020004), SH_UNT_PERV_0_PIB2OPB0,
+       SH_ACS_SCOM      );
+REG64( PERV_0_PIB2OPB1_RESET                                   , RULL(0x00020014), SH_UNT_PERV_0_PIB2OPB1,
+       SH_ACS_SCOM      );
+REG32( PERV_FSI2PIB_RESET_FSI                                  , RULL(0x00001006), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_RESET_FSI_BYTE                             , RULL(0x00001018), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI_BYTE  );
+REG32( PERV_FSISHIFT_RESET_FSI                                 , RULL(0x00000C06), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_RESET_FSI_BYTE                            , RULL(0x00000C18), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+REG64( PERV_PIB2OPB0_RESET                                     , RULL(0x00020004), SH_UNT_PERV_PIB2OPB0,
+       SH_ACS_SCOM      );
+REG64( PERV_PIB2OPB1_RESET                                     , RULL(0x00020014), SH_UNT_PERV_PIB2OPB1,
+       SH_ACS_SCOM      );
+
+REG32( PERV_FSISHIFT_RESET_ERRORS_FSI                          , RULL(0x00000C07), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_RESET_ERRORS_FSI_BYTE                     , RULL(0x00000C1C), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG64( PERV_RESET_REG                                          , RULL(0x000F001D), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_RESET_REG                                      , RULL(0x000F001D), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_0_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH_A      , RULL(0x00001809), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH_A        , RULL(0x00001809), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PERV_RFIR                                               , RULL(0x00040001), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_RFIR                                            , RULL(0x01040001), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_RFIR                                            , RULL(0x02040001), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_RFIR                                            , RULL(0x03040001), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_RFIR                                            , RULL(0x04040001), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_RFIR                                            , RULL(0x05040001), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_RFIR                                            , RULL(0x06040001), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_RFIR                                          , RULL(0x07040001), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_RFIR                                          , RULL(0x08040001), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_RFIR                                           , RULL(0x09040001), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_RFIR                                           , RULL(0x0C040001), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_RFIR                                          , RULL(0x0D040001), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_RFIR                                          , RULL(0x0E040001), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_RFIR                                          , RULL(0x0F040001), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_RFIR                                          , RULL(0x10040001), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_RFIR                                          , RULL(0x11040001), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_RFIR                                          , RULL(0x12040001), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_RFIR                                          , RULL(0x13040001), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_RFIR                                          , RULL(0x14040001), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_RFIR                                          , RULL(0x15040001), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_RFIR                                          , RULL(0x20040001), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_RFIR                                          , RULL(0x21040001), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_RFIR                                          , RULL(0x22040001), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_RFIR                                          , RULL(0x23040001), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_RFIR                                          , RULL(0x24040001), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_RFIR                                          , RULL(0x25040001), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_RFIR                                          , RULL(0x26040001), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_RFIR                                          , RULL(0x27040001), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_RFIR                                          , RULL(0x28040001), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_RFIR                                          , RULL(0x29040001), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_RFIR                                          , RULL(0x2A040001), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_RFIR                                          , RULL(0x2B040001), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_RFIR                                          , RULL(0x2C040001), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_RFIR                                          , RULL(0x2D040001), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_RFIR                                          , RULL(0x2E040001), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_RFIR                                          , RULL(0x2F040001), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_RFIR                                          , RULL(0x30040001), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_RFIR                                          , RULL(0x31040001), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_RFIR                                          , RULL(0x32040001), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_RFIR                                          , RULL(0x33040001), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_RFIR                                          , RULL(0x34040001), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_RFIR                                          , RULL(0x35040001), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_RFIR                                          , RULL(0x36040001), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_RFIR                                          , RULL(0x37040001), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_RING_FENCE_MASK_LATCH_REG                          , RULL(0x00010008), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_RING_FENCE_MASK_LATCH_REG                       , RULL(0x01010008), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL0_FSI                                     , RULL(0x00002810), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL0_FSI_BYTE                                , RULL(0x00002840), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL0_SCOM                                    , RULL(0x00050010), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL0                                     , RULL(0x00050010), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL0_CLEAR_FSI                               , RULL(0x00002930), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL0_CLEAR_FSI_BYTE                          , RULL(0x00002CC0), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL0_CLEAR_SCOM                              , RULL(0x00050130), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL0_CLEAR                               , RULL(0x00050130), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL0_COPY_FSI                                , RULL(0x00002910), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL0_COPY_FSI_BYTE                           , RULL(0x00002C40), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL0_COPY_SCOM                               , RULL(0x00050110), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL0_COPY                                , RULL(0x00050110), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL0_SET_FSI                                 , RULL(0x00002920), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL0_SET_FSI_BYTE                            , RULL(0x00002C80), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL0_SET_SCOM                                , RULL(0x00050120), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL0_SET                                 , RULL(0x00050120), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL1_FSI                                     , RULL(0x00002811), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL1_FSI_BYTE                                , RULL(0x00002844), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL1_SCOM                                    , RULL(0x00050011), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_PIB_ROOT_CTRL1                                     , RULL(0x00050011), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL1_CLEAR_FSI                               , RULL(0x00002931), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL1_CLEAR_FSI_BYTE                          , RULL(0x00002CC4), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL1_CLEAR_SCOM                              , RULL(0x00050131), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL1_CLEAR                               , RULL(0x00050131), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL1_COPY_FSI                                , RULL(0x00002911), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL1_COPY_FSI_BYTE                           , RULL(0x00002C44), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL1_COPY_SCOM                               , RULL(0x00050111), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL1_COPY                                , RULL(0x00050111), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL1_SET_FSI                                 , RULL(0x00002921), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL1_SET_FSI_BYTE                            , RULL(0x00002C84), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL1_SET_SCOM                                , RULL(0x00050121), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL1_SET                                 , RULL(0x00050121), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL2_FSI                                     , RULL(0x00002812), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL2_FSI_BYTE                                , RULL(0x00002848), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL2_SCOM                                    , RULL(0x00050012), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_PIB_ROOT_CTRL2                                     , RULL(0x00050012), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL2_CLEAR_FSI                               , RULL(0x00002932), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL2_CLEAR_FSI_BYTE                          , RULL(0x00002CC8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL2_CLEAR_SCOM                              , RULL(0x00050132), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL2_CLEAR                               , RULL(0x00050132), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL2_COPY_FSI                                , RULL(0x00002912), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL2_COPY_FSI_BYTE                           , RULL(0x00002C48), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL2_COPY_SCOM                               , RULL(0x00050112), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL2_COPY                                , RULL(0x00050112), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL2_SET_FSI                                 , RULL(0x00002922), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL2_SET_FSI_BYTE                            , RULL(0x00002C88), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL2_SET_SCOM                                , RULL(0x00050122), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL2_SET                                 , RULL(0x00050122), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL3_FSI                                     , RULL(0x00002813), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL3_FSI_BYTE                                , RULL(0x0000284C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL3_SCOM                                    , RULL(0x00050013), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL3                                     , RULL(0x00050013), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL3_CLEAR_FSI                               , RULL(0x00002933), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL3_CLEAR_FSI_BYTE                          , RULL(0x00002CCC), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL3_CLEAR_SCOM                              , RULL(0x00050133), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL3_CLEAR                               , RULL(0x00050133), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL3_COPY_FSI                                , RULL(0x00002913), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL3_COPY_FSI_BYTE                           , RULL(0x00002C4C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL3_COPY_SCOM                               , RULL(0x00050113), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL3_COPY                                , RULL(0x00050113), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL3_SET_FSI                                 , RULL(0x00002923), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL3_SET_FSI_BYTE                            , RULL(0x00002C8C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL3_SET_SCOM                                , RULL(0x00050123), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL3_SET                                 , RULL(0x00050123), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL4_FSI                                     , RULL(0x00002814), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL4_FSI_BYTE                                , RULL(0x00002850), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL4_SCOM                                    , RULL(0x00050014), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL4                                     , RULL(0x00050014), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL4_CLEAR_FSI                               , RULL(0x00002934), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL4_CLEAR_FSI_BYTE                          , RULL(0x00002CD0), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL4_CLEAR_SCOM                              , RULL(0x00050134), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL4_CLEAR                               , RULL(0x00050134), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL4_COPY_FSI                                , RULL(0x00002914), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL4_COPY_FSI_BYTE                           , RULL(0x00002C50), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL4_COPY_SCOM                               , RULL(0x00050114), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL4_COPY                                , RULL(0x00050114), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL4_SET_FSI                                 , RULL(0x00002924), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL4_SET_FSI_BYTE                            , RULL(0x00002C90), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL4_SET_SCOM                                , RULL(0x00050124), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL4_SET                                 , RULL(0x00050124), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL5_FSI                                     , RULL(0x00002815), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL5_FSI_BYTE                                , RULL(0x00002854), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL5_SCOM                                    , RULL(0x00050015), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL5                                     , RULL(0x00050015), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL5_CLEAR_FSI                               , RULL(0x00002935), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL5_CLEAR_FSI_BYTE                          , RULL(0x00002CD4), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL5_CLEAR_SCOM                              , RULL(0x00050135), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL5_CLEAR                               , RULL(0x00050135), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL5_COPY_FSI                                , RULL(0x00002915), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL5_COPY_FSI_BYTE                           , RULL(0x00002C54), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL5_COPY_SCOM                               , RULL(0x00050115), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL5_COPY                                , RULL(0x00050115), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL5_SET_FSI                                 , RULL(0x00002925), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL5_SET_FSI_BYTE                            , RULL(0x00002C94), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL5_SET_SCOM                                , RULL(0x00050125), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL5_SET                                 , RULL(0x00050125), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL6_FSI                                     , RULL(0x00002816), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL6_FSI_BYTE                                , RULL(0x00002858), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL6_SCOM                                    , RULL(0x00050016), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL6                                     , RULL(0x00050016), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL6_CLEAR_FSI                               , RULL(0x00002936), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL6_CLEAR_FSI_BYTE                          , RULL(0x00002CD8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL6_CLEAR_SCOM                              , RULL(0x00050136), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL6_CLEAR                               , RULL(0x00050136), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL6_COPY_FSI                                , RULL(0x00002916), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL6_COPY_FSI_BYTE                           , RULL(0x00002C58), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL6_COPY_SCOM                               , RULL(0x00050116), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL6_COPY                                , RULL(0x00050116), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL6_SET_FSI                                 , RULL(0x00002926), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL6_SET_FSI_BYTE                            , RULL(0x00002C98), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL6_SET_SCOM                                , RULL(0x00050126), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL6_SET                                 , RULL(0x00050126), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL7_FSI                                     , RULL(0x00002817), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL7_FSI_BYTE                                , RULL(0x0000285C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL7_SCOM                                    , RULL(0x00050017), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL7                                     , RULL(0x00050017), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL7_CLEAR_FSI                               , RULL(0x00002937), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL7_CLEAR_FSI_BYTE                          , RULL(0x00002CDC), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL7_CLEAR_SCOM                              , RULL(0x00050137), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL7_CLEAR                               , RULL(0x00050137), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL7_COPY_FSI                                , RULL(0x00002917), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL7_COPY_FSI_BYTE                           , RULL(0x00002C5C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL7_COPY_SCOM                               , RULL(0x00050117), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL7_COPY                                , RULL(0x00050117), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL7_SET_FSI                                 , RULL(0x00002927), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL7_SET_FSI_BYTE                            , RULL(0x00002C9C), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL7_SET_SCOM                                , RULL(0x00050127), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL7_SET                                 , RULL(0x00050127), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL8_FSI                                     , RULL(0x00002818), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL8_FSI_BYTE                                , RULL(0x00002860), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL8_SCOM                                    , RULL(0x00050018), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL8                                     , RULL(0x00050018), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL8_CLEAR_FSI                               , RULL(0x00002938), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL8_CLEAR_FSI_BYTE                          , RULL(0x00002CE0), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL8_CLEAR_SCOM                              , RULL(0x00050138), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL8_CLEAR                               , RULL(0x00050138), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL8_COPY_FSI                                , RULL(0x00002918), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL8_COPY_FSI_BYTE                           , RULL(0x00002C60), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL8_COPY_SCOM                               , RULL(0x00050118), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL8_COPY                                , RULL(0x00050118), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_ROOT_CTRL8_SET_FSI                                 , RULL(0x00002928), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_ROOT_CTRL8_SET_FSI_BYTE                            , RULL(0x00002CA0), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_ROOT_CTRL8_SET_SCOM                                , RULL(0x00050128), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_ROOT_CTRL8_SET                                 , RULL(0x00050128), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_RSIC                                               , RULL(0x00030008), SH_UNT_PERV     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_PIB_RSIC                                           , RULL(0x00030008), SH_UNT_PERV_0   ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_0_PIB2OPB0_RSIC                                    , RULL(0x00020008), SH_UNT_PERV_0_PIB2OPB0,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_0_PIB2OPB1_RSIC                                    , RULL(0x00020018), SH_UNT_PERV_0_PIB2OPB1,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_PIB2OPB0_RSIC                                      , RULL(0x00020008), SH_UNT_PERV_PIB2OPB0,
+       SH_ACS_SCOM_WCLEAR );
+REG64( PERV_PIB2OPB1_RSIC                                      , RULL(0x00020018), SH_UNT_PERV_PIB2OPB1,
+       SH_ACS_SCOM_WCLEAR );
+
+REG64( PERV_RSIM                                               , RULL(0x00030009), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_RSIM                                           , RULL(0x00030009), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+REG64( PERV_0_PIB2OPB0_RSIM                                    , RULL(0x00020009), SH_UNT_PERV_0_PIB2OPB0,
+       SH_ACS_SCOM_RW   );
+REG64( PERV_0_PIB2OPB1_RSIM                                    , RULL(0x00020019), SH_UNT_PERV_0_PIB2OPB1,
+       SH_ACS_SCOM_RW   );
+REG64( PERV_PIB2OPB0_RSIM                                      , RULL(0x00020009), SH_UNT_PERV_PIB2OPB0,
+       SH_ACS_SCOM_RW   );
+REG64( PERV_PIB2OPB1_RSIM                                      , RULL(0x00020019), SH_UNT_PERV_PIB2OPB1,
+       SH_ACS_SCOM_RW   );
+
+REG64( PERV_RSIS                                               , RULL(0x0003000A), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_RSIS                                           , RULL(0x0003000A), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+REG64( PERV_0_PIB2OPB0_RSIS                                    , RULL(0x0002000A), SH_UNT_PERV_0_PIB2OPB0,
+       SH_ACS_SCOM_RO   );
+REG64( PERV_0_PIB2OPB1_RSIS                                    , RULL(0x0002001A), SH_UNT_PERV_0_PIB2OPB1,
+       SH_ACS_SCOM_RO   );
+REG64( PERV_PIB2OPB0_RSIS                                      , RULL(0x0002000A), SH_UNT_PERV_PIB2OPB0,
+       SH_ACS_SCOM_RO   );
+REG64( PERV_PIB2OPB1_RSIS                                      , RULL(0x0002001A), SH_UNT_PERV_PIB2OPB1,
+       SH_ACS_SCOM_RO   );
+
+REG64( PERV_SBE_LCL_DBG_PPE                                    , RULL(0x00000120), SH_UNT_PERV     , SH_ACS_PPE       );
+
+REG64( PERV_SBE_LCL_EIMR_PPE                                   , RULL(0x00000020), SH_UNT_PERV     , SH_ACS_PPE       );
+REG64( PERV_SBE_LCL_EIMR_PPE1                                  , RULL(0x00000030), SH_UNT_PERV     , SH_ACS_PPE1      );
+REG64( PERV_SBE_LCL_EIMR_PPE2                                  , RULL(0x00000038), SH_UNT_PERV     , SH_ACS_PPE2      );
+
+REG64( PERV_SBE_LCL_EINR_PPE                                   , RULL(0x000000A0), SH_UNT_PERV     , SH_ACS_PPE       );
+
+REG64( PERV_SBE_LCL_EIPR_PPE                                   , RULL(0x00000040), SH_UNT_PERV     , SH_ACS_PPE       );
+REG64( PERV_SBE_LCL_EIPR_PPE1                                  , RULL(0x00000050), SH_UNT_PERV     , SH_ACS_PPE1      );
+REG64( PERV_SBE_LCL_EIPR_PPE2                                  , RULL(0x00000058), SH_UNT_PERV     , SH_ACS_PPE2      );
+
+REG64( PERV_SBE_LCL_EISR_PPE                                   , RULL(0x00000000), SH_UNT_PERV     , SH_ACS_PPE       );
+REG64( PERV_SBE_LCL_EISR_PPE1                                  , RULL(0x00000010), SH_UNT_PERV     , SH_ACS_PPE1      );
+REG64( PERV_SBE_LCL_EISR_PPE2                                  , RULL(0x00000018), SH_UNT_PERV     , SH_ACS_PPE2      );
+
+REG64( PERV_SBE_LCL_EISTR_PPE                                  , RULL(0x00000080), SH_UNT_PERV     , SH_ACS_PPE       );
+
+REG64( PERV_SBE_LCL_EITR_PPE                                   , RULL(0x00000060), SH_UNT_PERV     , SH_ACS_PPE       );
+REG64( PERV_SBE_LCL_EITR_PPE1                                  , RULL(0x00000070), SH_UNT_PERV     , SH_ACS_PPE1      );
+REG64( PERV_SBE_LCL_EITR_PPE2                                  , RULL(0x00000078), SH_UNT_PERV     , SH_ACS_PPE2      );
+
+REG64( PERV_SBE_LCL_IVPR_PPE                                   , RULL(0x00000160), SH_UNT_PERV     , SH_ACS_PPE       );
+
+REG64( PERV_SBE_LCL_TBR_PPE                                    , RULL(0x00000140), SH_UNT_PERV     , SH_ACS_PPE       );
+
+REG64( PERV_SBE_LCL_TSEL_PPE                                   , RULL(0x00000100), SH_UNT_PERV     , SH_ACS_PPE       );
+
+REG32( PERV_SB_CS_FSI                                          , RULL(0x00002808), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SB_CS_FSI_BYTE                                     , RULL(0x00002820), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SB_CS_SCOM                                         , RULL(0x00050008), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SB_CS                                          , RULL(0x00050008), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SB_MSG_FSI                                         , RULL(0x00002809), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SB_MSG_FSI_BYTE                                    , RULL(0x00002824), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SB_MSG_SCOM                                        , RULL(0x00050009), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SB_MSG                                         , RULL(0x00050009), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_SCAN_REGION_TYPE                                   , RULL(0x00030005), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_SCAN_REGION_TYPE                                , RULL(0x01030005), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_SCAN_REGION_TYPE                                , RULL(0x02030005), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_SCAN_REGION_TYPE                                , RULL(0x03030005), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_SCAN_REGION_TYPE                                , RULL(0x04030005), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_SCAN_REGION_TYPE                                , RULL(0x05030005), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_SCAN_REGION_TYPE                                , RULL(0x06030005), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_SCAN_REGION_TYPE                              , RULL(0x07030005), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_SCAN_REGION_TYPE                              , RULL(0x08030005), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_SCAN_REGION_TYPE                               , RULL(0x09030005), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_SCAN_REGION_TYPE                               , RULL(0x0C030005), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_SCAN_REGION_TYPE                              , RULL(0x0D030005), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_SCAN_REGION_TYPE                              , RULL(0x0E030005), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_SCAN_REGION_TYPE                              , RULL(0x0F030005), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_SCAN_REGION_TYPE                              , RULL(0x10030005), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_SCAN_REGION_TYPE                              , RULL(0x11030005), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_SCAN_REGION_TYPE                              , RULL(0x12030005), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_SCAN_REGION_TYPE                              , RULL(0x13030005), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_SCAN_REGION_TYPE                              , RULL(0x14030005), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_SCAN_REGION_TYPE                              , RULL(0x15030005), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_SCAN_REGION_TYPE                              , RULL(0x20030005), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_SCAN_REGION_TYPE                              , RULL(0x21030005), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_SCAN_REGION_TYPE                              , RULL(0x22030005), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_SCAN_REGION_TYPE                              , RULL(0x23030005), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_SCAN_REGION_TYPE                              , RULL(0x24030005), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_SCAN_REGION_TYPE                              , RULL(0x25030005), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_SCAN_REGION_TYPE                              , RULL(0x26030005), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_SCAN_REGION_TYPE                              , RULL(0x27030005), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_SCAN_REGION_TYPE                              , RULL(0x28030005), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_SCAN_REGION_TYPE                              , RULL(0x29030005), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_SCAN_REGION_TYPE                              , RULL(0x2A030005), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_SCAN_REGION_TYPE                              , RULL(0x2B030005), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_SCAN_REGION_TYPE                              , RULL(0x2C030005), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_SCAN_REGION_TYPE                              , RULL(0x2D030005), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_SCAN_REGION_TYPE                              , RULL(0x2E030005), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_SCAN_REGION_TYPE                              , RULL(0x2F030005), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_SCAN_REGION_TYPE                              , RULL(0x30030005), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_SCAN_REGION_TYPE                              , RULL(0x31030005), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_SCAN_REGION_TYPE                              , RULL(0x32030005), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_SCAN_REGION_TYPE                              , RULL(0x33030005), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_SCAN_REGION_TYPE                              , RULL(0x34030005), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_SCAN_REGION_TYPE                              , RULL(0x35030005), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_SCAN_REGION_TYPE                              , RULL(0x36030005), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_SCAN_REGION_TYPE                              , RULL(0x37030005), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG32( PERV_SCPSIZE_FSI                                        , RULL(0x00001400), SH_UNT_PERV     , SH_ACS_FSI       );
+
+REG32( PERV_SCRATCH_REGISTER_1_FSI                             , RULL(0x00002838), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_1_FSI_BYTE                        , RULL(0x000028E0), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_1_SCOM                            , RULL(0x00050038), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_1                             , RULL(0x00050038), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SCRATCH_REGISTER_2_FSI                             , RULL(0x00002839), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_2_FSI_BYTE                        , RULL(0x000028E4), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_2_SCOM                            , RULL(0x00050039), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_2                             , RULL(0x00050039), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SCRATCH_REGISTER_3_FSI                             , RULL(0x0000283A), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_3_FSI_BYTE                        , RULL(0x000028E8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_3_SCOM                            , RULL(0x0005003A), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_3                             , RULL(0x0005003A), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SCRATCH_REGISTER_4_FSI                             , RULL(0x0000283B), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_4_FSI_BYTE                        , RULL(0x000028EC), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_4_SCOM                            , RULL(0x0005003B), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_4                             , RULL(0x0005003B), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SCRATCH_REGISTER_5_FSI                             , RULL(0x0000283C), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_5_FSI_BYTE                        , RULL(0x000028F0), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_5_SCOM                            , RULL(0x0005003C), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_5                             , RULL(0x0005003C), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SCRATCH_REGISTER_6_FSI                             , RULL(0x0000283D), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_6_FSI_BYTE                        , RULL(0x000028F4), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_6_SCOM                            , RULL(0x0005003D), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_6                             , RULL(0x0005003D), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SCRATCH_REGISTER_7_FSI                             , RULL(0x0000283E), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_7_FSI_BYTE                        , RULL(0x000028F8), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_7_SCOM                            , RULL(0x0005003E), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_7                             , RULL(0x0005003E), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SCRATCH_REGISTER_8_FSI                             , RULL(0x0000283F), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SCRATCH_REGISTER_8_FSI_BYTE                        , RULL(0x000028FC), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SCRATCH_REGISTER_8_SCOM                            , RULL(0x0005003F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SCRATCH_REGISTER_8                             , RULL(0x0005003F), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_FSI2PIB_SET_PIB_RESET_FSI                          , RULL(0x00001007), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_SET_PIB_RESET_FSI_BYTE                     , RULL(0x0000101C), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI_BYTE  );
+
+REG32( PERV_FSISHIFT_SHIFT_CONTROL_REGISTER_2_FSI              , RULL(0x00000C10), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_SHIFT_CONTROL_REGISTER_2_FSI_BYTE         , RULL(0x00000C40), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG64( PERV_SKITTER_CLKSRC_REG                                 , RULL(0x00050016), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_TP_SKITTER_CLKSRC_REG                              , RULL(0x01050016), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_SKITTER_CLKSRC_REG                              , RULL(0x02050016), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_SKITTER_CLKSRC_REG                              , RULL(0x03050016), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_SKITTER_CLKSRC_REG                              , RULL(0x04050016), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_SKITTER_CLKSRC_REG                              , RULL(0x05050016), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_SKITTER_CLKSRC_REG                              , RULL(0x06050016), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_SKITTER_CLKSRC_REG                            , RULL(0x07050016), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_SKITTER_CLKSRC_REG                            , RULL(0x08050016), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_SKITTER_CLKSRC_REG                             , RULL(0x09050016), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_SKITTER_CLKSRC_REG                             , RULL(0x0C050016), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_SKITTER_CLKSRC_REG                            , RULL(0x0D050016), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_SKITTER_CLKSRC_REG                            , RULL(0x0E050016), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_SKITTER_CLKSRC_REG                            , RULL(0x0F050016), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_SKITTER_CLKSRC_REG                            , RULL(0x10050016), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_SKITTER_CLKSRC_REG                            , RULL(0x11050016), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_SKITTER_CLKSRC_REG                            , RULL(0x12050016), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_SKITTER_CLKSRC_REG                            , RULL(0x13050016), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_SKITTER_CLKSRC_REG                            , RULL(0x14050016), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_SKITTER_CLKSRC_REG                            , RULL(0x15050016), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_SKITTER_CLKSRC_REG                            , RULL(0x20050016), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_SKITTER_CLKSRC_REG                            , RULL(0x21050016), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_SKITTER_CLKSRC_REG                            , RULL(0x22050016), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_SKITTER_CLKSRC_REG                            , RULL(0x23050016), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_SKITTER_CLKSRC_REG                            , RULL(0x24050016), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_SKITTER_CLKSRC_REG                            , RULL(0x25050016), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_SKITTER_CLKSRC_REG                            , RULL(0x26050016), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_SKITTER_CLKSRC_REG                            , RULL(0x27050016), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_SKITTER_CLKSRC_REG                            , RULL(0x28050016), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_SKITTER_CLKSRC_REG                            , RULL(0x29050016), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_SKITTER_CLKSRC_REG                            , RULL(0x2A050016), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_SKITTER_CLKSRC_REG                            , RULL(0x2B050016), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_SKITTER_CLKSRC_REG                            , RULL(0x2C050016), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_SKITTER_CLKSRC_REG                            , RULL(0x2D050016), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_SKITTER_CLKSRC_REG                            , RULL(0x2E050016), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_SKITTER_CLKSRC_REG                            , RULL(0x2F050016), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_SKITTER_CLKSRC_REG                            , RULL(0x30050016), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_SKITTER_CLKSRC_REG                            , RULL(0x31050016), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_SKITTER_CLKSRC_REG                            , RULL(0x32050016), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_SKITTER_CLKSRC_REG                            , RULL(0x33050016), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_SKITTER_CLKSRC_REG                            , RULL(0x34050016), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_SKITTER_CLKSRC_REG                            , RULL(0x35050016), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_SKITTER_CLKSRC_REG                            , RULL(0x36050016), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_SKITTER_CLKSRC_REG                            , RULL(0x37050016), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_SKITTER_DATA0                                      , RULL(0x00050019), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_SKITTER_DATA0                                   , RULL(0x01050019), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_SKITTER_DATA0                                   , RULL(0x02050019), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_SKITTER_DATA0                                   , RULL(0x03050019), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_SKITTER_DATA0                                   , RULL(0x04050019), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_SKITTER_DATA0                                   , RULL(0x05050019), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_SKITTER_DATA0                                   , RULL(0x06050019), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_SKITTER_DATA0                                 , RULL(0x07050019), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_SKITTER_DATA0                                 , RULL(0x08050019), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_SKITTER_DATA0                                  , RULL(0x09050019), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_SKITTER_DATA0                                  , RULL(0x0C050019), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_SKITTER_DATA0                                 , RULL(0x0D050019), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_SKITTER_DATA0                                 , RULL(0x0E050019), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_SKITTER_DATA0                                 , RULL(0x0F050019), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_SKITTER_DATA0                                 , RULL(0x10050019), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_SKITTER_DATA0                                 , RULL(0x11050019), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_SKITTER_DATA0                                 , RULL(0x12050019), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_SKITTER_DATA0                                 , RULL(0x13050019), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_SKITTER_DATA0                                 , RULL(0x14050019), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_SKITTER_DATA0                                 , RULL(0x15050019), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_SKITTER_DATA0                                 , RULL(0x20050019), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_SKITTER_DATA0                                 , RULL(0x21050019), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_SKITTER_DATA0                                 , RULL(0x22050019), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_SKITTER_DATA0                                 , RULL(0x23050019), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_SKITTER_DATA0                                 , RULL(0x24050019), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_SKITTER_DATA0                                 , RULL(0x25050019), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_SKITTER_DATA0                                 , RULL(0x26050019), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_SKITTER_DATA0                                 , RULL(0x27050019), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_SKITTER_DATA0                                 , RULL(0x28050019), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_SKITTER_DATA0                                 , RULL(0x29050019), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_SKITTER_DATA0                                 , RULL(0x2A050019), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_SKITTER_DATA0                                 , RULL(0x2B050019), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_SKITTER_DATA0                                 , RULL(0x2C050019), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_SKITTER_DATA0                                 , RULL(0x2D050019), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_SKITTER_DATA0                                 , RULL(0x2E050019), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_SKITTER_DATA0                                 , RULL(0x2F050019), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_SKITTER_DATA0                                 , RULL(0x30050019), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_SKITTER_DATA0                                 , RULL(0x31050019), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_SKITTER_DATA0                                 , RULL(0x32050019), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_SKITTER_DATA0                                 , RULL(0x33050019), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_SKITTER_DATA0                                 , RULL(0x34050019), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_SKITTER_DATA0                                 , RULL(0x35050019), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_SKITTER_DATA0                                 , RULL(0x36050019), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_SKITTER_DATA0                                 , RULL(0x37050019), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_SKITTER_DATA1                                      , RULL(0x0005001A), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_SKITTER_DATA1                                   , RULL(0x0105001A), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_SKITTER_DATA1                                   , RULL(0x0205001A), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_SKITTER_DATA1                                   , RULL(0x0305001A), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_SKITTER_DATA1                                   , RULL(0x0405001A), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_SKITTER_DATA1                                   , RULL(0x0505001A), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_SKITTER_DATA1                                   , RULL(0x0605001A), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_SKITTER_DATA1                                 , RULL(0x0705001A), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_SKITTER_DATA1                                 , RULL(0x0805001A), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_SKITTER_DATA1                                  , RULL(0x0905001A), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_SKITTER_DATA1                                  , RULL(0x0C05001A), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_SKITTER_DATA1                                 , RULL(0x0D05001A), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_SKITTER_DATA1                                 , RULL(0x0E05001A), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_SKITTER_DATA1                                 , RULL(0x0F05001A), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_SKITTER_DATA1                                 , RULL(0x1005001A), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_SKITTER_DATA1                                 , RULL(0x1105001A), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_SKITTER_DATA1                                 , RULL(0x1205001A), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_SKITTER_DATA1                                 , RULL(0x1305001A), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_SKITTER_DATA1                                 , RULL(0x1405001A), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_SKITTER_DATA1                                 , RULL(0x1505001A), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_SKITTER_DATA1                                 , RULL(0x2005001A), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_SKITTER_DATA1                                 , RULL(0x2105001A), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_SKITTER_DATA1                                 , RULL(0x2205001A), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_SKITTER_DATA1                                 , RULL(0x2305001A), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_SKITTER_DATA1                                 , RULL(0x2405001A), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_SKITTER_DATA1                                 , RULL(0x2505001A), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_SKITTER_DATA1                                 , RULL(0x2605001A), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_SKITTER_DATA1                                 , RULL(0x2705001A), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_SKITTER_DATA1                                 , RULL(0x2805001A), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_SKITTER_DATA1                                 , RULL(0x2905001A), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_SKITTER_DATA1                                 , RULL(0x2A05001A), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_SKITTER_DATA1                                 , RULL(0x2B05001A), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_SKITTER_DATA1                                 , RULL(0x2C05001A), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_SKITTER_DATA1                                 , RULL(0x2D05001A), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_SKITTER_DATA1                                 , RULL(0x2E05001A), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_SKITTER_DATA1                                 , RULL(0x2F05001A), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_SKITTER_DATA1                                 , RULL(0x3005001A), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_SKITTER_DATA1                                 , RULL(0x3105001A), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_SKITTER_DATA1                                 , RULL(0x3205001A), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_SKITTER_DATA1                                 , RULL(0x3305001A), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_SKITTER_DATA1                                 , RULL(0x3405001A), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_SKITTER_DATA1                                 , RULL(0x3505001A), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_SKITTER_DATA1                                 , RULL(0x3605001A), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_SKITTER_DATA1                                 , RULL(0x3705001A), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_SKITTER_DATA2                                      , RULL(0x0005001B), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_SKITTER_DATA2                                   , RULL(0x0105001B), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_SKITTER_DATA2                                   , RULL(0x0205001B), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_SKITTER_DATA2                                   , RULL(0x0305001B), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_SKITTER_DATA2                                   , RULL(0x0405001B), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_SKITTER_DATA2                                   , RULL(0x0505001B), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_SKITTER_DATA2                                   , RULL(0x0605001B), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_SKITTER_DATA2                                 , RULL(0x0705001B), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_SKITTER_DATA2                                 , RULL(0x0805001B), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_SKITTER_DATA2                                  , RULL(0x0905001B), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_SKITTER_DATA2                                  , RULL(0x0C05001B), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_SKITTER_DATA2                                 , RULL(0x0D05001B), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_SKITTER_DATA2                                 , RULL(0x0E05001B), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_SKITTER_DATA2                                 , RULL(0x0F05001B), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_SKITTER_DATA2                                 , RULL(0x1005001B), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_SKITTER_DATA2                                 , RULL(0x1105001B), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_SKITTER_DATA2                                 , RULL(0x1205001B), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_SKITTER_DATA2                                 , RULL(0x1305001B), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_SKITTER_DATA2                                 , RULL(0x1405001B), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_SKITTER_DATA2                                 , RULL(0x1505001B), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_SKITTER_DATA2                                 , RULL(0x2005001B), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_SKITTER_DATA2                                 , RULL(0x2105001B), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_SKITTER_DATA2                                 , RULL(0x2205001B), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_SKITTER_DATA2                                 , RULL(0x2305001B), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_SKITTER_DATA2                                 , RULL(0x2405001B), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_SKITTER_DATA2                                 , RULL(0x2505001B), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_SKITTER_DATA2                                 , RULL(0x2605001B), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_SKITTER_DATA2                                 , RULL(0x2705001B), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_SKITTER_DATA2                                 , RULL(0x2805001B), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_SKITTER_DATA2                                 , RULL(0x2905001B), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_SKITTER_DATA2                                 , RULL(0x2A05001B), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_SKITTER_DATA2                                 , RULL(0x2B05001B), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_SKITTER_DATA2                                 , RULL(0x2C05001B), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_SKITTER_DATA2                                 , RULL(0x2D05001B), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_SKITTER_DATA2                                 , RULL(0x2E05001B), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_SKITTER_DATA2                                 , RULL(0x2F05001B), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_SKITTER_DATA2                                 , RULL(0x3005001B), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_SKITTER_DATA2                                 , RULL(0x3105001B), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_SKITTER_DATA2                                 , RULL(0x3205001B), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_SKITTER_DATA2                                 , RULL(0x3305001B), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_SKITTER_DATA2                                 , RULL(0x3405001B), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_SKITTER_DATA2                                 , RULL(0x3505001B), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_SKITTER_DATA2                                 , RULL(0x3605001B), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_SKITTER_DATA2                                 , RULL(0x3705001B), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_SKITTER_FORCE_REG                                  , RULL(0x00050014), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_TP_SKITTER_FORCE_REG                               , RULL(0x01050014), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_SKITTER_FORCE_REG                               , RULL(0x02050014), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_SKITTER_FORCE_REG                               , RULL(0x03050014), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_SKITTER_FORCE_REG                               , RULL(0x04050014), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_SKITTER_FORCE_REG                               , RULL(0x05050014), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_SKITTER_FORCE_REG                               , RULL(0x06050014), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_SKITTER_FORCE_REG                             , RULL(0x07050014), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_SKITTER_FORCE_REG                             , RULL(0x08050014), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_SKITTER_FORCE_REG                              , RULL(0x09050014), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_SKITTER_FORCE_REG                              , RULL(0x0C050014), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_SKITTER_FORCE_REG                             , RULL(0x0D050014), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_SKITTER_FORCE_REG                             , RULL(0x0E050014), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_SKITTER_FORCE_REG                             , RULL(0x0F050014), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_SKITTER_FORCE_REG                             , RULL(0x10050014), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_SKITTER_FORCE_REG                             , RULL(0x11050014), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_SKITTER_FORCE_REG                             , RULL(0x12050014), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_SKITTER_FORCE_REG                             , RULL(0x13050014), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_SKITTER_FORCE_REG                             , RULL(0x14050014), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_SKITTER_FORCE_REG                             , RULL(0x15050014), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_SKITTER_FORCE_REG                             , RULL(0x20050014), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_SKITTER_FORCE_REG                             , RULL(0x21050014), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_SKITTER_FORCE_REG                             , RULL(0x22050014), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_SKITTER_FORCE_REG                             , RULL(0x23050014), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_SKITTER_FORCE_REG                             , RULL(0x24050014), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_SKITTER_FORCE_REG                             , RULL(0x25050014), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_SKITTER_FORCE_REG                             , RULL(0x26050014), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_SKITTER_FORCE_REG                             , RULL(0x27050014), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_SKITTER_FORCE_REG                             , RULL(0x28050014), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_SKITTER_FORCE_REG                             , RULL(0x29050014), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_SKITTER_FORCE_REG                             , RULL(0x2A050014), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_SKITTER_FORCE_REG                             , RULL(0x2B050014), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_SKITTER_FORCE_REG                             , RULL(0x2C050014), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_SKITTER_FORCE_REG                             , RULL(0x2D050014), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_SKITTER_FORCE_REG                             , RULL(0x2E050014), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_SKITTER_FORCE_REG                             , RULL(0x2F050014), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_SKITTER_FORCE_REG                             , RULL(0x30050014), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_SKITTER_FORCE_REG                             , RULL(0x31050014), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_SKITTER_FORCE_REG                             , RULL(0x32050014), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_SKITTER_FORCE_REG                             , RULL(0x33050014), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_SKITTER_FORCE_REG                             , RULL(0x34050014), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_SKITTER_FORCE_REG                             , RULL(0x35050014), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_SKITTER_FORCE_REG                             , RULL(0x36050014), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_SKITTER_FORCE_REG                             , RULL(0x37050014), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_SKITTER_MODE_REG                                   , RULL(0x00050010), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_TP_SKITTER_MODE_REG                                , RULL(0x01050010), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_SKITTER_MODE_REG                                , RULL(0x02050010), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_SKITTER_MODE_REG                                , RULL(0x03050010), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_SKITTER_MODE_REG                                , RULL(0x04050010), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_SKITTER_MODE_REG                                , RULL(0x05050010), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_SKITTER_MODE_REG                                , RULL(0x06050010), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_SKITTER_MODE_REG                              , RULL(0x07050010), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_SKITTER_MODE_REG                              , RULL(0x08050010), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_SKITTER_MODE_REG                               , RULL(0x09050010), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_SKITTER_MODE_REG                               , RULL(0x0C050010), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_SKITTER_MODE_REG                              , RULL(0x0D050010), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_SKITTER_MODE_REG                              , RULL(0x0E050010), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_SKITTER_MODE_REG                              , RULL(0x0F050010), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_SKITTER_MODE_REG                              , RULL(0x10050010), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_SKITTER_MODE_REG                              , RULL(0x11050010), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_SKITTER_MODE_REG                              , RULL(0x12050010), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_SKITTER_MODE_REG                              , RULL(0x13050010), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_SKITTER_MODE_REG                              , RULL(0x14050010), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_SKITTER_MODE_REG                              , RULL(0x15050010), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_SKITTER_MODE_REG                              , RULL(0x20050010), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_SKITTER_MODE_REG                              , RULL(0x21050010), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_SKITTER_MODE_REG                              , RULL(0x22050010), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_SKITTER_MODE_REG                              , RULL(0x23050010), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_SKITTER_MODE_REG                              , RULL(0x24050010), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_SKITTER_MODE_REG                              , RULL(0x25050010), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_SKITTER_MODE_REG                              , RULL(0x26050010), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_SKITTER_MODE_REG                              , RULL(0x27050010), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_SKITTER_MODE_REG                              , RULL(0x28050010), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_SKITTER_MODE_REG                              , RULL(0x29050010), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_SKITTER_MODE_REG                              , RULL(0x2A050010), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_SKITTER_MODE_REG                              , RULL(0x2B050010), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_SKITTER_MODE_REG                              , RULL(0x2C050010), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_SKITTER_MODE_REG                              , RULL(0x2D050010), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_SKITTER_MODE_REG                              , RULL(0x2E050010), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_SKITTER_MODE_REG                              , RULL(0x2F050010), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_SKITTER_MODE_REG                              , RULL(0x30050010), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_SKITTER_MODE_REG                              , RULL(0x31050010), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_SKITTER_MODE_REG                              , RULL(0x32050010), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_SKITTER_MODE_REG                              , RULL(0x33050010), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_SKITTER_MODE_REG                              , RULL(0x34050010), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_SKITTER_MODE_REG                              , RULL(0x35050010), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_SKITTER_MODE_REG                              , RULL(0x36050010), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_SKITTER_MODE_REG                              , RULL(0x37050010), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_SLAVE_CONFIG_REG                                   , RULL(0x000F001E), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_TP_SLAVE_CONFIG_REG                                , RULL(0x010F001E), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_SLAVE_CONFIG_REG                                , RULL(0x020F001E), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_SLAVE_CONFIG_REG                                , RULL(0x030F001E), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_SLAVE_CONFIG_REG                                , RULL(0x040F001E), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_SLAVE_CONFIG_REG                                , RULL(0x050F001E), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_SLAVE_CONFIG_REG                                , RULL(0x060F001E), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_SLAVE_CONFIG_REG                              , RULL(0x070F001E), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_SLAVE_CONFIG_REG                              , RULL(0x080F001E), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_SLAVE_CONFIG_REG                               , RULL(0x090F001E), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_SLAVE_CONFIG_REG                               , RULL(0x0C0F001E), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_SLAVE_CONFIG_REG                              , RULL(0x0D0F001E), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_SLAVE_CONFIG_REG                              , RULL(0x0E0F001E), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_SLAVE_CONFIG_REG                              , RULL(0x0F0F001E), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_SLAVE_CONFIG_REG                              , RULL(0x100F001E), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_SLAVE_CONFIG_REG                              , RULL(0x110F001E), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_SLAVE_CONFIG_REG                              , RULL(0x120F001E), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_SLAVE_CONFIG_REG                              , RULL(0x130F001E), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_SLAVE_CONFIG_REG                              , RULL(0x140F001E), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_SLAVE_CONFIG_REG                              , RULL(0x150F001E), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_SLAVE_CONFIG_REG                              , RULL(0x200F001E), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_SLAVE_CONFIG_REG                              , RULL(0x210F001E), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_SLAVE_CONFIG_REG                              , RULL(0x220F001E), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_SLAVE_CONFIG_REG                              , RULL(0x230F001E), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_SLAVE_CONFIG_REG                              , RULL(0x240F001E), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_SLAVE_CONFIG_REG                              , RULL(0x250F001E), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_SLAVE_CONFIG_REG                              , RULL(0x260F001E), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_SLAVE_CONFIG_REG                              , RULL(0x270F001E), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_SLAVE_CONFIG_REG                              , RULL(0x280F001E), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_SLAVE_CONFIG_REG                              , RULL(0x290F001E), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_SLAVE_CONFIG_REG                              , RULL(0x2A0F001E), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_SLAVE_CONFIG_REG                              , RULL(0x2B0F001E), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_SLAVE_CONFIG_REG                              , RULL(0x2C0F001E), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_SLAVE_CONFIG_REG                              , RULL(0x2D0F001E), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_SLAVE_CONFIG_REG                              , RULL(0x2E0F001E), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_SLAVE_CONFIG_REG                              , RULL(0x2F0F001E), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_SLAVE_CONFIG_REG                              , RULL(0x300F001E), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_SLAVE_CONFIG_REG                              , RULL(0x310F001E), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_SLAVE_CONFIG_REG                              , RULL(0x320F001E), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_SLAVE_CONFIG_REG                              , RULL(0x330F001E), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_SLAVE_CONFIG_REG                              , RULL(0x340F001E), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_SLAVE_CONFIG_REG                              , RULL(0x350F001E), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_SLAVE_CONFIG_REG                              , RULL(0x360F001E), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_SLAVE_CONFIG_REG                              , RULL(0x370F001E), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG32( PERV_SNS1LTH_FSI                                        , RULL(0x0000281D), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SNS1LTH_FSI_BYTE                                   , RULL(0x00002874), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SNS1LTH_SCOM                                       , RULL(0x0005001D), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SNS1LTH                                        , RULL(0x0005001D), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG32( PERV_SNS2LTH_FSI                                        , RULL(0x0000281E), SH_UNT_PERV     , SH_ACS_FSI       );
+REG64( PERV_SNS2LTH_FSI_BYTE                                   , RULL(0x00002878), SH_UNT_PERV     , SH_ACS_FSI_BYTE  );
+REG64( PERV_SNS2LTH_SCOM                                       , RULL(0x0005001E), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_SNS2LTH                                        , RULL(0x0005001E), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_SPATTN_SCOM                                        , RULL(0x00040004), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_SPATTN_SCOM                                     , RULL(0x01040004), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_SPATTN_SCOM1                                       , RULL(0x00040005), SH_UNT_PERV     , SH_ACS_SCOM1_NC  );
+REG64( PERV_TP_SPATTN_SCOM1                                    , RULL(0x01040005), SH_UNT_PERV_1   , SH_ACS_SCOM1_NC  );
+REG64( PERV_SPATTN_SCOM2                                       , RULL(0x00040006), SH_UNT_PERV     , SH_ACS_SCOM2_NC  );
+REG64( PERV_TP_SPATTN_SCOM2                                    , RULL(0x01040006), SH_UNT_PERV_1   , SH_ACS_SCOM2_NC  );
+REG64( PERV_N0_SPATTN_SCOM                                     , RULL(0x02040004), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_SPATTN_SCOM1                                    , RULL(0x02040005), SH_UNT_PERV_2   , SH_ACS_SCOM1_NC  );
+REG64( PERV_N0_SPATTN_SCOM2                                    , RULL(0x02040006), SH_UNT_PERV_2   , SH_ACS_SCOM2_NC  );
+REG64( PERV_N1_SPATTN_SCOM                                     , RULL(0x03040004), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_SPATTN_SCOM1                                    , RULL(0x03040005), SH_UNT_PERV_3   , SH_ACS_SCOM1_NC  );
+REG64( PERV_N1_SPATTN_SCOM2                                    , RULL(0x03040006), SH_UNT_PERV_3   , SH_ACS_SCOM2_NC  );
+REG64( PERV_N2_SPATTN_SCOM                                     , RULL(0x04040004), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_SPATTN_SCOM1                                    , RULL(0x04040005), SH_UNT_PERV_4   , SH_ACS_SCOM1_NC  );
+REG64( PERV_N2_SPATTN_SCOM2                                    , RULL(0x04040006), SH_UNT_PERV_4   , SH_ACS_SCOM2_NC  );
+REG64( PERV_N3_SPATTN_SCOM                                     , RULL(0x05040004), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_SPATTN_SCOM1                                    , RULL(0x05040005), SH_UNT_PERV_5   , SH_ACS_SCOM1_NC  );
+REG64( PERV_N3_SPATTN_SCOM2                                    , RULL(0x05040006), SH_UNT_PERV_5   , SH_ACS_SCOM2_NC  );
+REG64( PERV_XB_SPATTN_SCOM                                     , RULL(0x06040004), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_SPATTN_SCOM1                                    , RULL(0x06040005), SH_UNT_PERV_6   , SH_ACS_SCOM1_NC  );
+REG64( PERV_XB_SPATTN_SCOM2                                    , RULL(0x06040006), SH_UNT_PERV_6   , SH_ACS_SCOM2_NC  );
+REG64( PERV_MC01_SPATTN_SCOM                                   , RULL(0x07040004), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_SPATTN_SCOM1                                  , RULL(0x07040005), SH_UNT_PERV_7   , SH_ACS_SCOM1_NC  );
+REG64( PERV_MC01_SPATTN_SCOM2                                  , RULL(0x07040006), SH_UNT_PERV_7   , SH_ACS_SCOM2_NC  );
+REG64( PERV_MC23_SPATTN_SCOM                                   , RULL(0x08040004), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_SPATTN_SCOM1                                  , RULL(0x08040005), SH_UNT_PERV_8   , SH_ACS_SCOM1_NC  );
+REG64( PERV_MC23_SPATTN_SCOM2                                  , RULL(0x08040006), SH_UNT_PERV_8   , SH_ACS_SCOM2_NC  );
+REG64( PERV_OB0_SPATTN_SCOM                                    , RULL(0x09040004), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_SPATTN_SCOM1                                   , RULL(0x09040005), SH_UNT_PERV_9   , SH_ACS_SCOM1_NC  );
+REG64( PERV_OB0_SPATTN_SCOM2                                   , RULL(0x09040006), SH_UNT_PERV_9   , SH_ACS_SCOM2_NC  );
+REG64( PERV_OB3_SPATTN_SCOM                                    , RULL(0x0C040004), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_SPATTN_SCOM1                                   , RULL(0x0C040005), SH_UNT_PERV_12  , SH_ACS_SCOM1_NC  );
+REG64( PERV_OB3_SPATTN_SCOM2                                   , RULL(0x0C040006), SH_UNT_PERV_12  , SH_ACS_SCOM2_NC  );
+REG64( PERV_PCI0_SPATTN_SCOM                                   , RULL(0x0D040004), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_SPATTN_SCOM1                                  , RULL(0x0D040005), SH_UNT_PERV_13  , SH_ACS_SCOM1_NC  );
+REG64( PERV_PCI0_SPATTN_SCOM2                                  , RULL(0x0D040006), SH_UNT_PERV_13  , SH_ACS_SCOM2_NC  );
+REG64( PERV_PCI1_SPATTN_SCOM                                   , RULL(0x0E040004), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_SPATTN_SCOM1                                  , RULL(0x0E040005), SH_UNT_PERV_14  , SH_ACS_SCOM1_NC  );
+REG64( PERV_PCI1_SPATTN_SCOM2                                  , RULL(0x0E040006), SH_UNT_PERV_14  , SH_ACS_SCOM2_NC  );
+REG64( PERV_PCI2_SPATTN_SCOM                                   , RULL(0x0F040004), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_SPATTN_SCOM1                                  , RULL(0x0F040005), SH_UNT_PERV_15  , SH_ACS_SCOM1_NC  );
+REG64( PERV_PCI2_SPATTN_SCOM2                                  , RULL(0x0F040006), SH_UNT_PERV_15  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EP00_SPATTN_SCOM                                   , RULL(0x10040004), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_SPATTN_SCOM1                                  , RULL(0x10040005), SH_UNT_PERV_16  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EP00_SPATTN_SCOM2                                  , RULL(0x10040006), SH_UNT_PERV_16  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EP01_SPATTN_SCOM                                   , RULL(0x11040004), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_SPATTN_SCOM1                                  , RULL(0x11040005), SH_UNT_PERV_17  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EP01_SPATTN_SCOM2                                  , RULL(0x11040006), SH_UNT_PERV_17  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EP02_SPATTN_SCOM                                   , RULL(0x12040004), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_SPATTN_SCOM1                                  , RULL(0x12040005), SH_UNT_PERV_18  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EP02_SPATTN_SCOM2                                  , RULL(0x12040006), SH_UNT_PERV_18  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EP03_SPATTN_SCOM                                   , RULL(0x13040004), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_SPATTN_SCOM1                                  , RULL(0x13040005), SH_UNT_PERV_19  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EP03_SPATTN_SCOM2                                  , RULL(0x13040006), SH_UNT_PERV_19  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EP04_SPATTN_SCOM                                   , RULL(0x14040004), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_SPATTN_SCOM1                                  , RULL(0x14040005), SH_UNT_PERV_20  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EP04_SPATTN_SCOM2                                  , RULL(0x14040006), SH_UNT_PERV_20  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EP05_SPATTN_SCOM                                   , RULL(0x15040004), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_SPATTN_SCOM1                                  , RULL(0x15040005), SH_UNT_PERV_21  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EP05_SPATTN_SCOM2                                  , RULL(0x15040006), SH_UNT_PERV_21  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC00_SPATTN_SCOM                                   , RULL(0x20040004), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_SPATTN_SCOM1                                  , RULL(0x20040005), SH_UNT_PERV_32  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC00_SPATTN_SCOM2                                  , RULL(0x20040006), SH_UNT_PERV_32  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC01_SPATTN_SCOM                                   , RULL(0x21040004), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_SPATTN_SCOM1                                  , RULL(0x21040005), SH_UNT_PERV_33  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC01_SPATTN_SCOM2                                  , RULL(0x21040006), SH_UNT_PERV_33  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC02_SPATTN_SCOM                                   , RULL(0x22040004), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_SPATTN_SCOM1                                  , RULL(0x22040005), SH_UNT_PERV_34  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC02_SPATTN_SCOM2                                  , RULL(0x22040006), SH_UNT_PERV_34  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC03_SPATTN_SCOM                                   , RULL(0x23040004), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_SPATTN_SCOM1                                  , RULL(0x23040005), SH_UNT_PERV_35  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC03_SPATTN_SCOM2                                  , RULL(0x23040006), SH_UNT_PERV_35  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC04_SPATTN_SCOM                                   , RULL(0x24040004), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_SPATTN_SCOM1                                  , RULL(0x24040005), SH_UNT_PERV_36  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC04_SPATTN_SCOM2                                  , RULL(0x24040006), SH_UNT_PERV_36  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC05_SPATTN_SCOM                                   , RULL(0x25040004), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_SPATTN_SCOM1                                  , RULL(0x25040005), SH_UNT_PERV_37  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC05_SPATTN_SCOM2                                  , RULL(0x25040006), SH_UNT_PERV_37  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC06_SPATTN_SCOM                                   , RULL(0x26040004), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_SPATTN_SCOM1                                  , RULL(0x26040005), SH_UNT_PERV_38  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC06_SPATTN_SCOM2                                  , RULL(0x26040006), SH_UNT_PERV_38  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC07_SPATTN_SCOM                                   , RULL(0x27040004), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_SPATTN_SCOM1                                  , RULL(0x27040005), SH_UNT_PERV_39  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC07_SPATTN_SCOM2                                  , RULL(0x27040006), SH_UNT_PERV_39  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC08_SPATTN_SCOM                                   , RULL(0x28040004), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_SPATTN_SCOM1                                  , RULL(0x28040005), SH_UNT_PERV_40  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC08_SPATTN_SCOM2                                  , RULL(0x28040006), SH_UNT_PERV_40  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC09_SPATTN_SCOM                                   , RULL(0x29040004), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_SPATTN_SCOM1                                  , RULL(0x29040005), SH_UNT_PERV_41  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC09_SPATTN_SCOM2                                  , RULL(0x29040006), SH_UNT_PERV_41  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC10_SPATTN_SCOM                                   , RULL(0x2A040004), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_SPATTN_SCOM1                                  , RULL(0x2A040005), SH_UNT_PERV_42  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC10_SPATTN_SCOM2                                  , RULL(0x2A040006), SH_UNT_PERV_42  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC11_SPATTN_SCOM                                   , RULL(0x2B040004), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_SPATTN_SCOM1                                  , RULL(0x2B040005), SH_UNT_PERV_43  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC11_SPATTN_SCOM2                                  , RULL(0x2B040006), SH_UNT_PERV_43  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC12_SPATTN_SCOM                                   , RULL(0x2C040004), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_SPATTN_SCOM1                                  , RULL(0x2C040005), SH_UNT_PERV_44  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC12_SPATTN_SCOM2                                  , RULL(0x2C040006), SH_UNT_PERV_44  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC13_SPATTN_SCOM                                   , RULL(0x2D040004), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_SPATTN_SCOM1                                  , RULL(0x2D040005), SH_UNT_PERV_45  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC13_SPATTN_SCOM2                                  , RULL(0x2D040006), SH_UNT_PERV_45  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC14_SPATTN_SCOM                                   , RULL(0x2E040004), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_SPATTN_SCOM1                                  , RULL(0x2E040005), SH_UNT_PERV_46  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC14_SPATTN_SCOM2                                  , RULL(0x2E040006), SH_UNT_PERV_46  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC15_SPATTN_SCOM                                   , RULL(0x2F040004), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_SPATTN_SCOM1                                  , RULL(0x2F040005), SH_UNT_PERV_47  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC15_SPATTN_SCOM2                                  , RULL(0x2F040006), SH_UNT_PERV_47  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC16_SPATTN_SCOM                                   , RULL(0x30040004), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_SPATTN_SCOM1                                  , RULL(0x30040005), SH_UNT_PERV_48  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC16_SPATTN_SCOM2                                  , RULL(0x30040006), SH_UNT_PERV_48  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC17_SPATTN_SCOM                                   , RULL(0x31040004), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_SPATTN_SCOM1                                  , RULL(0x31040005), SH_UNT_PERV_49  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC17_SPATTN_SCOM2                                  , RULL(0x31040006), SH_UNT_PERV_49  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC18_SPATTN_SCOM                                   , RULL(0x32040004), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_SPATTN_SCOM1                                  , RULL(0x32040005), SH_UNT_PERV_50  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC18_SPATTN_SCOM2                                  , RULL(0x32040006), SH_UNT_PERV_50  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC19_SPATTN_SCOM                                   , RULL(0x33040004), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_SPATTN_SCOM1                                  , RULL(0x33040005), SH_UNT_PERV_51  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC19_SPATTN_SCOM2                                  , RULL(0x33040006), SH_UNT_PERV_51  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC20_SPATTN_SCOM                                   , RULL(0x34040004), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_SPATTN_SCOM1                                  , RULL(0x34040005), SH_UNT_PERV_52  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC20_SPATTN_SCOM2                                  , RULL(0x34040006), SH_UNT_PERV_52  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC21_SPATTN_SCOM                                   , RULL(0x35040004), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_SPATTN_SCOM1                                  , RULL(0x35040005), SH_UNT_PERV_53  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC21_SPATTN_SCOM2                                  , RULL(0x35040006), SH_UNT_PERV_53  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC22_SPATTN_SCOM                                   , RULL(0x36040004), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_SPATTN_SCOM1                                  , RULL(0x36040005), SH_UNT_PERV_54  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC22_SPATTN_SCOM2                                  , RULL(0x36040006), SH_UNT_PERV_54  , SH_ACS_SCOM2_NC  );
+REG64( PERV_EC23_SPATTN_SCOM                                   , RULL(0x37040004), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_SPATTN_SCOM1                                  , RULL(0x37040005), SH_UNT_PERV_55  , SH_ACS_SCOM1_NC  );
+REG64( PERV_EC23_SPATTN_SCOM2                                  , RULL(0x37040006), SH_UNT_PERV_55  , SH_ACS_SCOM2_NC  );
+
+REG64( PERV_SPA_MASK                                           , RULL(0x00040007), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_SPA_MASK                                        , RULL(0x01040007), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_SPA_MASK                                        , RULL(0x02040007), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_SPA_MASK                                        , RULL(0x03040007), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_SPA_MASK                                        , RULL(0x04040007), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_SPA_MASK                                        , RULL(0x05040007), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_SPA_MASK                                        , RULL(0x06040007), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_SPA_MASK                                      , RULL(0x07040007), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_SPA_MASK                                      , RULL(0x08040007), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_SPA_MASK                                       , RULL(0x09040007), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_SPA_MASK                                       , RULL(0x0C040007), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_SPA_MASK                                      , RULL(0x0D040007), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_SPA_MASK                                      , RULL(0x0E040007), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_SPA_MASK                                      , RULL(0x0F040007), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_SPA_MASK                                      , RULL(0x10040007), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_SPA_MASK                                      , RULL(0x11040007), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_SPA_MASK                                      , RULL(0x12040007), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_SPA_MASK                                      , RULL(0x13040007), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_SPA_MASK                                      , RULL(0x14040007), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_SPA_MASK                                      , RULL(0x15040007), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_SPA_MASK                                      , RULL(0x20040007), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_SPA_MASK                                      , RULL(0x21040007), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_SPA_MASK                                      , RULL(0x22040007), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_SPA_MASK                                      , RULL(0x23040007), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_SPA_MASK                                      , RULL(0x24040007), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_SPA_MASK                                      , RULL(0x25040007), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_SPA_MASK                                      , RULL(0x26040007), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_SPA_MASK                                      , RULL(0x27040007), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_SPA_MASK                                      , RULL(0x28040007), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_SPA_MASK                                      , RULL(0x29040007), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_SPA_MASK                                      , RULL(0x2A040007), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_SPA_MASK                                      , RULL(0x2B040007), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_SPA_MASK                                      , RULL(0x2C040007), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_SPA_MASK                                      , RULL(0x2D040007), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_SPA_MASK                                      , RULL(0x2E040007), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_SPA_MASK                                      , RULL(0x2F040007), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_SPA_MASK                                      , RULL(0x30040007), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_SPA_MASK                                      , RULL(0x31040007), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_SPA_MASK                                      , RULL(0x32040007), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_SPA_MASK                                      , RULL(0x33040007), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_SPA_MASK                                      , RULL(0x34040007), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_SPA_MASK                                      , RULL(0x35040007), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_SPA_MASK                                      , RULL(0x36040007), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_SPA_MASK                                      , RULL(0x37040007), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG32( PERV_FSI2PIB_STATUS_FSI                                 , RULL(0x00001007), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI       ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSI2PIB_STATUS_FSI_BYTE                            , RULL(0x0000101C), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI_BYTE  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_STATUS_FSI                                , RULL(0x00000C07), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSISHIFT_STATUS_FSI_BYTE                           , RULL(0x00000C1C), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PERV_0_FSII2C_STATUS_REGISTER_ENGINE_A                  , RULL(0x00001807), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG32( PERV_FSII2C_STATUS_REGISTER_ENGINE_A                    , RULL(0x00001807), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+
+REG64( PERV_STAT_RDDAT_ERRES                                   , RULL(0x00030001), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_PIB_STAT_RDDAT_ERRES                               , RULL(0x00030001), SH_UNT_PERV_0   , SH_ACS_SCOM_RO   );
+REG64( PERV_0_PIB2OPB0_STAT_RDDAT_ERRES                        , RULL(0x00020001), SH_UNT_PERV_0_PIB2OPB0,
+       SH_ACS_SCOM_RO   );
+REG64( PERV_0_PIB2OPB1_STAT_RDDAT_ERRES                        , RULL(0x00020011), SH_UNT_PERV_0_PIB2OPB1,
+       SH_ACS_SCOM_RO   );
+REG64( PERV_PIB2OPB0_STAT_RDDAT_ERRES                          , RULL(0x00020001), SH_UNT_PERV_PIB2OPB0,
+       SH_ACS_SCOM_RO   );
+REG64( PERV_PIB2OPB1_STAT_RDDAT_ERRES                          , RULL(0x00020011), SH_UNT_PERV_PIB2OPB1,
+       SH_ACS_SCOM_RO   );
+
+REG64( PERV_SUM_MASK_REG                                       , RULL(0x00040017), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_SUM_MASK_REG                                    , RULL(0x01040017), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_SUM_MASK_REG                                    , RULL(0x02040017), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_SUM_MASK_REG                                    , RULL(0x03040017), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_SUM_MASK_REG                                    , RULL(0x04040017), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_SUM_MASK_REG                                    , RULL(0x05040017), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_SUM_MASK_REG                                    , RULL(0x06040017), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_SUM_MASK_REG                                  , RULL(0x07040017), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_SUM_MASK_REG                                  , RULL(0x08040017), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_SUM_MASK_REG                                   , RULL(0x09040017), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_SUM_MASK_REG                                   , RULL(0x0C040017), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_SUM_MASK_REG                                  , RULL(0x0D040017), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_SUM_MASK_REG                                  , RULL(0x0E040017), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_SUM_MASK_REG                                  , RULL(0x0F040017), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_SUM_MASK_REG                                  , RULL(0x10040017), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_SUM_MASK_REG                                  , RULL(0x11040017), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_SUM_MASK_REG                                  , RULL(0x12040017), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_SUM_MASK_REG                                  , RULL(0x13040017), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_SUM_MASK_REG                                  , RULL(0x14040017), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_SUM_MASK_REG                                  , RULL(0x15040017), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_SUM_MASK_REG                                  , RULL(0x20040017), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_SUM_MASK_REG                                  , RULL(0x21040017), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_SUM_MASK_REG                                  , RULL(0x22040017), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_SUM_MASK_REG                                  , RULL(0x23040017), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_SUM_MASK_REG                                  , RULL(0x24040017), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_SUM_MASK_REG                                  , RULL(0x25040017), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_SUM_MASK_REG                                  , RULL(0x26040017), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_SUM_MASK_REG                                  , RULL(0x27040017), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_SUM_MASK_REG                                  , RULL(0x28040017), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_SUM_MASK_REG                                  , RULL(0x29040017), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_SUM_MASK_REG                                  , RULL(0x2A040017), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_SUM_MASK_REG                                  , RULL(0x2B040017), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_SUM_MASK_REG                                  , RULL(0x2C040017), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_SUM_MASK_REG                                  , RULL(0x2D040017), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_SUM_MASK_REG                                  , RULL(0x2E040017), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_SUM_MASK_REG                                  , RULL(0x2F040017), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_SUM_MASK_REG                                  , RULL(0x30040017), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_SUM_MASK_REG                                  , RULL(0x31040017), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_SUM_MASK_REG                                  , RULL(0x32040017), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_SUM_MASK_REG                                  , RULL(0x33040017), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_SUM_MASK_REG                                  , RULL(0x34040017), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_SUM_MASK_REG                                  , RULL(0x35040017), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_SUM_MASK_REG                                  , RULL(0x36040017), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_SUM_MASK_REG                                  , RULL(0x37040017), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_SYNC_CONFIG                                        , RULL(0x00030000), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_TP_SYNC_CONFIG                                     , RULL(0x01030000), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_SYNC_CONFIG                                     , RULL(0x02030000), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_SYNC_CONFIG                                     , RULL(0x03030000), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_SYNC_CONFIG                                     , RULL(0x04030000), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_SYNC_CONFIG                                     , RULL(0x05030000), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_SYNC_CONFIG                                     , RULL(0x06030000), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_SYNC_CONFIG                                   , RULL(0x07030000), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_SYNC_CONFIG                                   , RULL(0x08030000), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_SYNC_CONFIG                                    , RULL(0x09030000), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_SYNC_CONFIG                                    , RULL(0x0C030000), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_SYNC_CONFIG                                   , RULL(0x0D030000), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_SYNC_CONFIG                                   , RULL(0x0E030000), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_SYNC_CONFIG                                   , RULL(0x0F030000), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_SYNC_CONFIG                                   , RULL(0x10030000), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_SYNC_CONFIG                                   , RULL(0x11030000), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_SYNC_CONFIG                                   , RULL(0x12030000), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_SYNC_CONFIG                                   , RULL(0x13030000), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_SYNC_CONFIG                                   , RULL(0x14030000), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_SYNC_CONFIG                                   , RULL(0x15030000), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_SYNC_CONFIG                                   , RULL(0x20030000), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_SYNC_CONFIG                                   , RULL(0x21030000), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_SYNC_CONFIG                                   , RULL(0x22030000), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_SYNC_CONFIG                                   , RULL(0x23030000), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_SYNC_CONFIG                                   , RULL(0x24030000), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_SYNC_CONFIG                                   , RULL(0x25030000), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_SYNC_CONFIG                                   , RULL(0x26030000), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_SYNC_CONFIG                                   , RULL(0x27030000), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_SYNC_CONFIG                                   , RULL(0x28030000), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_SYNC_CONFIG                                   , RULL(0x29030000), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_SYNC_CONFIG                                   , RULL(0x2A030000), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_SYNC_CONFIG                                   , RULL(0x2B030000), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_SYNC_CONFIG                                   , RULL(0x2C030000), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_SYNC_CONFIG                                   , RULL(0x2D030000), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_SYNC_CONFIG                                   , RULL(0x2E030000), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_SYNC_CONFIG                                   , RULL(0x2F030000), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_SYNC_CONFIG                                   , RULL(0x30030000), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_SYNC_CONFIG                                   , RULL(0x31030000), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_SYNC_CONFIG                                   , RULL(0x32030000), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_SYNC_CONFIG                                   , RULL(0x33030000), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_SYNC_CONFIG                                   , RULL(0x34030000), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_SYNC_CONFIG                                   , RULL(0x35030000), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_SYNC_CONFIG                                   , RULL(0x36030000), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_SYNC_CONFIG                                   , RULL(0x37030000), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_THERM_MODE_REG                                     , RULL(0x0005000F), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_THERM_MODE_REG                                  , RULL(0x0105000F), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_THERM_MODE_REG                                  , RULL(0x0205000F), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_THERM_MODE_REG                                  , RULL(0x0305000F), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_THERM_MODE_REG                                  , RULL(0x0405000F), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_THERM_MODE_REG                                  , RULL(0x0505000F), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_THERM_MODE_REG                                  , RULL(0x0605000F), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_THERM_MODE_REG                                , RULL(0x0705000F), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_THERM_MODE_REG                                , RULL(0x0805000F), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_THERM_MODE_REG                                 , RULL(0x0905000F), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_THERM_MODE_REG                                 , RULL(0x0C05000F), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_THERM_MODE_REG                                , RULL(0x0D05000F), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_THERM_MODE_REG                                , RULL(0x0E05000F), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_THERM_MODE_REG                                , RULL(0x0F05000F), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_THERM_MODE_REG                                , RULL(0x1005000F), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_THERM_MODE_REG                                , RULL(0x1105000F), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_THERM_MODE_REG                                , RULL(0x1205000F), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_THERM_MODE_REG                                , RULL(0x1305000F), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_THERM_MODE_REG                                , RULL(0x1405000F), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_THERM_MODE_REG                                , RULL(0x1505000F), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_THERM_MODE_REG                                , RULL(0x2005000F), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_THERM_MODE_REG                                , RULL(0x2105000F), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_THERM_MODE_REG                                , RULL(0x2205000F), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_THERM_MODE_REG                                , RULL(0x2305000F), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_THERM_MODE_REG                                , RULL(0x2405000F), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_THERM_MODE_REG                                , RULL(0x2505000F), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_THERM_MODE_REG                                , RULL(0x2605000F), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_THERM_MODE_REG                                , RULL(0x2705000F), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_THERM_MODE_REG                                , RULL(0x2805000F), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_THERM_MODE_REG                                , RULL(0x2905000F), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_THERM_MODE_REG                                , RULL(0x2A05000F), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_THERM_MODE_REG                                , RULL(0x2B05000F), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_THERM_MODE_REG                                , RULL(0x2C05000F), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_THERM_MODE_REG                                , RULL(0x2D05000F), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_THERM_MODE_REG                                , RULL(0x2E05000F), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_THERM_MODE_REG                                , RULL(0x2F05000F), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_THERM_MODE_REG                                , RULL(0x3005000F), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_THERM_MODE_REG                                , RULL(0x3105000F), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_THERM_MODE_REG                                , RULL(0x3205000F), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_THERM_MODE_REG                                , RULL(0x3305000F), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_THERM_MODE_REG                                , RULL(0x3405000F), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_THERM_MODE_REG                                , RULL(0x3505000F), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_THERM_MODE_REG                                , RULL(0x3605000F), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_THERM_MODE_REG                                , RULL(0x3705000F), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_TIMEOUT_REG                                        , RULL(0x000F0019), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_PIB_TIMEOUT_REG                                    , RULL(0x000F0019), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+REG64( PERV_TP_TIMEOUT_REG                                     , RULL(0x010F0010), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_TIMEOUT_REG                                     , RULL(0x020F0010), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_TIMEOUT_REG                                     , RULL(0x030F0010), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_TIMEOUT_REG                                     , RULL(0x040F0010), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_TIMEOUT_REG                                     , RULL(0x050F0010), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_TIMEOUT_REG                                     , RULL(0x060F0010), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_TIMEOUT_REG                                   , RULL(0x070F0010), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_TIMEOUT_REG                                   , RULL(0x080F0010), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_TIMEOUT_REG                                    , RULL(0x090F0010), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_TIMEOUT_REG                                    , RULL(0x0C0F0010), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_TIMEOUT_REG                                   , RULL(0x0D0F0010), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_TIMEOUT_REG                                   , RULL(0x0E0F0010), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_TIMEOUT_REG                                   , RULL(0x0F0F0010), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_TIMEOUT_REG                                   , RULL(0x100F0010), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_TIMEOUT_REG                                   , RULL(0x110F0010), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_TIMEOUT_REG                                   , RULL(0x120F0010), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_TIMEOUT_REG                                   , RULL(0x130F0010), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_TIMEOUT_REG                                   , RULL(0x140F0010), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_TIMEOUT_REG                                   , RULL(0x150F0010), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_TIMEOUT_REG                                   , RULL(0x200F0010), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_TIMEOUT_REG                                   , RULL(0x210F0010), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_TIMEOUT_REG                                   , RULL(0x220F0010), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_TIMEOUT_REG                                   , RULL(0x230F0010), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_TIMEOUT_REG                                   , RULL(0x240F0010), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_TIMEOUT_REG                                   , RULL(0x250F0010), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_TIMEOUT_REG                                   , RULL(0x260F0010), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_TIMEOUT_REG                                   , RULL(0x270F0010), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_TIMEOUT_REG                                   , RULL(0x280F0010), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_TIMEOUT_REG                                   , RULL(0x290F0010), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_TIMEOUT_REG                                   , RULL(0x2A0F0010), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_TIMEOUT_REG                                   , RULL(0x2B0F0010), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_TIMEOUT_REG                                   , RULL(0x2C0F0010), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_TIMEOUT_REG                                   , RULL(0x2D0F0010), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_TIMEOUT_REG                                   , RULL(0x2E0F0010), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_TIMEOUT_REG                                   , RULL(0x2F0F0010), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_TIMEOUT_REG                                   , RULL(0x300F0010), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_TIMEOUT_REG                                   , RULL(0x310F0010), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_TIMEOUT_REG                                   , RULL(0x320F0010), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_TIMEOUT_REG                                   , RULL(0x330F0010), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_TIMEOUT_REG                                   , RULL(0x340F0010), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_TIMEOUT_REG                                   , RULL(0x350F0010), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_TIMEOUT_REG                                   , RULL(0x360F0010), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_TIMEOUT_REG                                   , RULL(0x370F0010), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_TIMESTAMP_COUNTER_READ                             , RULL(0x0005001C), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_TIMESTAMP_COUNTER_READ                          , RULL(0x0105001C), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_TIMESTAMP_COUNTER_READ                          , RULL(0x0205001C), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_TIMESTAMP_COUNTER_READ                          , RULL(0x0305001C), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_TIMESTAMP_COUNTER_READ                          , RULL(0x0405001C), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_TIMESTAMP_COUNTER_READ                          , RULL(0x0505001C), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_TIMESTAMP_COUNTER_READ                          , RULL(0x0605001C), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_TIMESTAMP_COUNTER_READ                        , RULL(0x0705001C), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_TIMESTAMP_COUNTER_READ                        , RULL(0x0805001C), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_TIMESTAMP_COUNTER_READ                         , RULL(0x0905001C), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_TIMESTAMP_COUNTER_READ                         , RULL(0x0C05001C), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_TIMESTAMP_COUNTER_READ                        , RULL(0x0D05001C), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_TIMESTAMP_COUNTER_READ                        , RULL(0x0E05001C), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_TIMESTAMP_COUNTER_READ                        , RULL(0x0F05001C), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_TIMESTAMP_COUNTER_READ                        , RULL(0x1005001C), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_TIMESTAMP_COUNTER_READ                        , RULL(0x1105001C), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_TIMESTAMP_COUNTER_READ                        , RULL(0x1205001C), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_TIMESTAMP_COUNTER_READ                        , RULL(0x1305001C), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_TIMESTAMP_COUNTER_READ                        , RULL(0x1405001C), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_TIMESTAMP_COUNTER_READ                        , RULL(0x1505001C), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_TIMESTAMP_COUNTER_READ                        , RULL(0x2005001C), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_TIMESTAMP_COUNTER_READ                        , RULL(0x2105001C), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_TIMESTAMP_COUNTER_READ                        , RULL(0x2205001C), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_TIMESTAMP_COUNTER_READ                        , RULL(0x2305001C), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_TIMESTAMP_COUNTER_READ                        , RULL(0x2405001C), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_TIMESTAMP_COUNTER_READ                        , RULL(0x2505001C), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_TIMESTAMP_COUNTER_READ                        , RULL(0x2605001C), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_TIMESTAMP_COUNTER_READ                        , RULL(0x2705001C), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_TIMESTAMP_COUNTER_READ                        , RULL(0x2805001C), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_TIMESTAMP_COUNTER_READ                        , RULL(0x2905001C), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_TIMESTAMP_COUNTER_READ                        , RULL(0x2A05001C), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_TIMESTAMP_COUNTER_READ                        , RULL(0x2B05001C), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_TIMESTAMP_COUNTER_READ                        , RULL(0x2C05001C), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_TIMESTAMP_COUNTER_READ                        , RULL(0x2D05001C), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_TIMESTAMP_COUNTER_READ                        , RULL(0x2E05001C), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_TIMESTAMP_COUNTER_READ                        , RULL(0x2F05001C), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_TIMESTAMP_COUNTER_READ                        , RULL(0x3005001C), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_TIMESTAMP_COUNTER_READ                        , RULL(0x3105001C), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_TIMESTAMP_COUNTER_READ                        , RULL(0x3205001C), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_TIMESTAMP_COUNTER_READ                        , RULL(0x3305001C), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_TIMESTAMP_COUNTER_READ                        , RULL(0x3405001C), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_TIMESTAMP_COUNTER_READ                        , RULL(0x3505001C), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_TIMESTAMP_COUNTER_READ                        , RULL(0x3605001C), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_TIMESTAMP_COUNTER_READ                        , RULL(0x3705001C), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_TOD_CHIP_CTRL_REG                                  , RULL(0x00040010), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_PIB_TOD_CHIP_CTRL_REG                              , RULL(0x00040010), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_TOD_ERROR_INJECT_REG                               , RULL(0x00040031), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_ERROR_INJECT_REG                           , RULL(0x00040031), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_ERROR_MASK_REG                                 , RULL(0x00040032), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_ERROR_MASK_REG                             , RULL(0x00040032), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_ERROR_REG                                      , RULL(0x00040030), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_ERROR_REG                                  , RULL(0x00040030), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_ERROR_ROUTING_REG                              , RULL(0x00040033), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_ERROR_ROUTING_REG                          , RULL(0x00040033), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_FSM_REG                                        , RULL(0x00040024), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_TOD_FSM_REG                                    , RULL(0x00040024), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_TOD_I_PATH_CTRL_REG                                , RULL(0x00040006), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_TOD_I_PATH_CTRL_REG                            , RULL(0x00040006), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_TOD_LOAD_TOD_MOD_REG                               , RULL(0x00040018), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_LOAD_TOD_MOD_REG                           , RULL(0x00040018), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_LOAD_TOD_REG                                   , RULL(0x00040021), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_LOAD_TOD_REG                               , RULL(0x00040021), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_LOW_ORDER_STEP_REG                             , RULL(0x00040023), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_LOW_ORDER_STEP_REG                         , RULL(0x00040023), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_MISC_RESET_REG                                 , RULL(0x0004000B), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_MISC_RESET_REG                             , RULL(0x0004000B), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_MOVE_TOD_TO_TB_REG                             , RULL(0x00040017), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_MOVE_TOD_TO_TB_REG                         , RULL(0x00040017), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_M_PATH_0_STEP_STEER_REG                        , RULL(0x0004000E), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_M_PATH_0_STEP_STEER_REG                    , RULL(0x0004000E), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_M_PATH_1_STEP_STEER_REG                        , RULL(0x0004000F), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_M_PATH_1_STEP_STEER_REG                    , RULL(0x0004000F), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_M_PATH_CTRL_REG                                , RULL(0x00040000), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_M_PATH_CTRL_REG                            , RULL(0x00040000), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_M_PATH_STATUS_REG                              , RULL(0x00040009), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_M_PATH_STATUS_REG                          , RULL(0x00040009), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_PRI_PORT_0_CTRL_REG                            , RULL(0x00040001), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_PRI_PORT_0_CTRL_REG                        , RULL(0x00040001), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_PRI_PORT_1_CTRL_REG                            , RULL(0x00040002), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_PRI_PORT_1_CTRL_REG                        , RULL(0x00040002), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_PROBE_SELECT_REG                               , RULL(0x0004000C), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_PROBE_SELECT_REG                           , RULL(0x0004000C), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_PSS_MSS_CTRL_REG                               , RULL(0x00040007), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_PSS_MSS_CTRL_REG                           , RULL(0x00040007), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_PSS_MSS_STATUS_REG                             , RULL(0x00040008), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_PIB_TOD_PSS_MSS_STATUS_REG                         , RULL(0x00040008), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_TOD_RX_TTYPE_CTRL_REG                              , RULL(0x00040029), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_RX_TTYPE_CTRL_REG                          , RULL(0x00040029), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_SEC_PORT_0_CTRL_REG                            , RULL(0x00040003), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_SEC_PORT_0_CTRL_REG                        , RULL(0x00040003), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_SEC_PORT_1_CTRL_REG                            , RULL(0x00040004), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_SEC_PORT_1_CTRL_REG                        , RULL(0x00040004), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_START_TOD_REG                                  , RULL(0x00040022), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_TOD_START_TOD_REG                              , RULL(0x00040022), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_TOD_S_PATH_CTRL_REG                                , RULL(0x00040005), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_S_PATH_CTRL_REG                            , RULL(0x00040005), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_S_PATH_STATUS_REG                              , RULL(0x0004000A), SH_UNT_PERV     ,
+       SH_ACS_SCOM_RW   ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_PIB_TOD_S_PATH_STATUS_REG                          , RULL(0x0004000A), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_TIMER_REG                                      , RULL(0x0004000D), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_TOD_TIMER_REG                                  , RULL(0x0004000D), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_TOD_TRACE_DATA_1_REG                               , RULL(0x0004001D), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_TRACE_DATA_1_REG                           , RULL(0x0004001D), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_TRACE_DATA_2_REG                               , RULL(0x0004001E), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_TRACE_DATA_2_REG                           , RULL(0x0004001E), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_TRACE_DATA_3_REG                               , RULL(0x0004001F), SH_UNT_PERV     , SH_ACS_SCOM_RW   );
+REG64( PERV_PIB_TOD_TRACE_DATA_3_REG                           , RULL(0x0004001F), SH_UNT_PERV_0   , SH_ACS_SCOM_RW   );
+
+REG64( PERV_TOD_TX_TTYPE_0_REG                                 , RULL(0x00040011), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_TX_TTYPE_0_REG                             , RULL(0x00040011), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_TX_TTYPE_1_REG                                 , RULL(0x00040012), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_TX_TTYPE_1_REG                             , RULL(0x00040012), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_TX_TTYPE_2_REG                                 , RULL(0x00040013), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_TX_TTYPE_2_REG                             , RULL(0x00040013), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_TX_TTYPE_3_REG                                 , RULL(0x00040014), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_TX_TTYPE_3_REG                             , RULL(0x00040014), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_TX_TTYPE_4_REG                                 , RULL(0x00040015), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_TX_TTYPE_4_REG                             , RULL(0x00040015), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_TX_TTYPE_5_REG                                 , RULL(0x00040016), SH_UNT_PERV     , SH_ACS_SCOM_WO   );
+REG64( PERV_PIB_TOD_TX_TTYPE_5_REG                             , RULL(0x00040016), SH_UNT_PERV_0   , SH_ACS_SCOM_WO   );
+
+REG64( PERV_TOD_TX_TTYPE_CTRL_REG                              , RULL(0x00040027), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_TOD_TX_TTYPE_CTRL_REG                          , RULL(0x00040027), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_TOD_VALUE_REG                                      , RULL(0x00040020), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_PIB_TOD_VALUE_REG                                  , RULL(0x00040020), SH_UNT_PERV_0   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG                  , RULL(0x00010400), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG               , RULL(0x01010400), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG                  , RULL(0x00010401), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG               , RULL(0x01010401), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG                , RULL(0x00010402), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG             , RULL(0x01010402), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_0              , RULL(0x00010403), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_0           , RULL(0x01010403), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_1              , RULL(0x00010404), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_1           , RULL(0x01010404), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2              , RULL(0x00010405), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2           , RULL(0x01010405), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3              , RULL(0x00010406), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3           , RULL(0x01010406), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4              , RULL(0x00010407), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4           , RULL(0x01010407), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5              , RULL(0x00010408), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5           , RULL(0x01010408), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9              , RULL(0x00010409), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9           , RULL(0x01010409), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR1_TRACE_HI_DATA_REG                  , RULL(0x00010440), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_HI_DATA_REG               , RULL(0x01010440), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG                  , RULL(0x00010441), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG               , RULL(0x01010441), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG                , RULL(0x00010442), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG             , RULL(0x01010442), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_0              , RULL(0x00010443), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_0           , RULL(0x01010443), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_1              , RULL(0x00010444), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_1           , RULL(0x01010444), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2              , RULL(0x00010445), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2           , RULL(0x01010445), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3              , RULL(0x00010446), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3           , RULL(0x01010446), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4              , RULL(0x00010447), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4           , RULL(0x01010447), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5              , RULL(0x00010448), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5           , RULL(0x01010448), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9              , RULL(0x00010449), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9           , RULL(0x01010449), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG32( PERV_FSI2PIB_TRUE_MASK_FSI                              , RULL(0x0000100D), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI       );
+REG32( PERV_FSI2PIB_TRUE_MASK_FSI_BYTE                         , RULL(0x00001034), SH_UNT_PERV_FSI2PIB,
+       SH_ACS_FSI_BYTE  );
+REG32( PERV_FSISHIFT_TRUE_MASK_FSI                             , RULL(0x00000C0D), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI       );
+REG32( PERV_FSISHIFT_TRUE_MASK_FSI_BYTE                        , RULL(0x00000C34), SH_UNT_PERV_FSISHIFT,
+       SH_ACS_FSI_BYTE  );
+
+REG64( PERV_VITAL_SCAN_OUT                                     , RULL(0x000F0017), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_VITAL_SCAN_OUT                                  , RULL(0x010F0017), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+REG64( PERV_N0_VITAL_SCAN_OUT                                  , RULL(0x020F0017), SH_UNT_PERV_2   , SH_ACS_SCOM_RO   );
+REG64( PERV_N1_VITAL_SCAN_OUT                                  , RULL(0x030F0017), SH_UNT_PERV_3   , SH_ACS_SCOM_RO   );
+REG64( PERV_N2_VITAL_SCAN_OUT                                  , RULL(0x040F0017), SH_UNT_PERV_4   , SH_ACS_SCOM_RO   );
+REG64( PERV_N3_VITAL_SCAN_OUT                                  , RULL(0x050F0017), SH_UNT_PERV_5   , SH_ACS_SCOM_RO   );
+REG64( PERV_XB_VITAL_SCAN_OUT                                  , RULL(0x060F0017), SH_UNT_PERV_6   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC01_VITAL_SCAN_OUT                                , RULL(0x070F0017), SH_UNT_PERV_7   , SH_ACS_SCOM_RO   );
+REG64( PERV_MC23_VITAL_SCAN_OUT                                , RULL(0x080F0017), SH_UNT_PERV_8   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB0_VITAL_SCAN_OUT                                 , RULL(0x090F0017), SH_UNT_PERV_9   , SH_ACS_SCOM_RO   );
+REG64( PERV_OB3_VITAL_SCAN_OUT                                 , RULL(0x0C0F0017), SH_UNT_PERV_12  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI0_VITAL_SCAN_OUT                                , RULL(0x0D0F0017), SH_UNT_PERV_13  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI1_VITAL_SCAN_OUT                                , RULL(0x0E0F0017), SH_UNT_PERV_14  , SH_ACS_SCOM_RO   );
+REG64( PERV_PCI2_VITAL_SCAN_OUT                                , RULL(0x0F0F0017), SH_UNT_PERV_15  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP00_VITAL_SCAN_OUT                                , RULL(0x100F0017), SH_UNT_PERV_16  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP01_VITAL_SCAN_OUT                                , RULL(0x110F0017), SH_UNT_PERV_17  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP02_VITAL_SCAN_OUT                                , RULL(0x120F0017), SH_UNT_PERV_18  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP03_VITAL_SCAN_OUT                                , RULL(0x130F0017), SH_UNT_PERV_19  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP04_VITAL_SCAN_OUT                                , RULL(0x140F0017), SH_UNT_PERV_20  , SH_ACS_SCOM_RO   );
+REG64( PERV_EP05_VITAL_SCAN_OUT                                , RULL(0x150F0017), SH_UNT_PERV_21  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC00_VITAL_SCAN_OUT                                , RULL(0x200F0017), SH_UNT_PERV_32  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC01_VITAL_SCAN_OUT                                , RULL(0x210F0017), SH_UNT_PERV_33  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC02_VITAL_SCAN_OUT                                , RULL(0x220F0017), SH_UNT_PERV_34  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC03_VITAL_SCAN_OUT                                , RULL(0x230F0017), SH_UNT_PERV_35  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC04_VITAL_SCAN_OUT                                , RULL(0x240F0017), SH_UNT_PERV_36  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC05_VITAL_SCAN_OUT                                , RULL(0x250F0017), SH_UNT_PERV_37  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC06_VITAL_SCAN_OUT                                , RULL(0x260F0017), SH_UNT_PERV_38  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC07_VITAL_SCAN_OUT                                , RULL(0x270F0017), SH_UNT_PERV_39  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC08_VITAL_SCAN_OUT                                , RULL(0x280F0017), SH_UNT_PERV_40  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC09_VITAL_SCAN_OUT                                , RULL(0x290F0017), SH_UNT_PERV_41  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC10_VITAL_SCAN_OUT                                , RULL(0x2A0F0017), SH_UNT_PERV_42  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC11_VITAL_SCAN_OUT                                , RULL(0x2B0F0017), SH_UNT_PERV_43  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC12_VITAL_SCAN_OUT                                , RULL(0x2C0F0017), SH_UNT_PERV_44  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC13_VITAL_SCAN_OUT                                , RULL(0x2D0F0017), SH_UNT_PERV_45  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC14_VITAL_SCAN_OUT                                , RULL(0x2E0F0017), SH_UNT_PERV_46  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC15_VITAL_SCAN_OUT                                , RULL(0x2F0F0017), SH_UNT_PERV_47  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC16_VITAL_SCAN_OUT                                , RULL(0x300F0017), SH_UNT_PERV_48  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC17_VITAL_SCAN_OUT                                , RULL(0x310F0017), SH_UNT_PERV_49  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC18_VITAL_SCAN_OUT                                , RULL(0x320F0017), SH_UNT_PERV_50  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC19_VITAL_SCAN_OUT                                , RULL(0x330F0017), SH_UNT_PERV_51  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC20_VITAL_SCAN_OUT                                , RULL(0x340F0017), SH_UNT_PERV_52  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC21_VITAL_SCAN_OUT                                , RULL(0x350F0017), SH_UNT_PERV_53  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC22_VITAL_SCAN_OUT                                , RULL(0x360F0017), SH_UNT_PERV_54  , SH_ACS_SCOM_RO   );
+REG64( PERV_EC23_VITAL_SCAN_OUT                                , RULL(0x370F0017), SH_UNT_PERV_55  , SH_ACS_SCOM_RO   );
+
+REG64( PERV_VMEAS_RESULT_REG                                   , RULL(0x00020006), SH_UNT_PERV     , SH_ACS_SCOM_RO   );
+REG64( PERV_TP_VMEAS_RESULT_REG                                , RULL(0x01020006), SH_UNT_PERV_1   , SH_ACS_SCOM_RO   );
+
+REG64( PERV_0_FSII2C_WATER_MARK_REGISTER_A                     , RULL(0x00001803), SH_UNT_PERV_0_FSII2C,
+       SH_ACS_SCOM      );
+REG32( PERV_FSII2C_WATER_MARK_REGISTER_A                       , RULL(0x00001803), SH_UNT_PERV_FSII2C,
+       SH_ACS_SCOM      );
+
+REG64( PERV_WRITE_PROTECT_ENABLE_REG                           , RULL(0x00010005), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_WRITE_PROTECT_ENABLE_REG                        , RULL(0x01010005), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_WRITE_PROTECT_RINGS_REG                            , RULL(0x00010006), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_WRITE_PROTECT_RINGS_REG                         , RULL(0x01010006), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+
+REG64( PERV_XFIR                                               , RULL(0x00040000), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_XFIR                                            , RULL(0x01040000), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_XFIR                                            , RULL(0x02040000), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_XFIR                                            , RULL(0x03040000), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_XFIR                                            , RULL(0x04040000), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_XFIR                                            , RULL(0x05040000), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_XFIR                                            , RULL(0x06040000), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_XFIR                                          , RULL(0x07040000), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_XFIR                                          , RULL(0x08040000), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_XFIR                                           , RULL(0x09040000), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_XFIR                                           , RULL(0x0C040000), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_XFIR                                          , RULL(0x0D040000), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_XFIR                                          , RULL(0x0E040000), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_XFIR                                          , RULL(0x0F040000), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_XFIR                                          , RULL(0x10040000), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_XFIR                                          , RULL(0x11040000), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_XFIR                                          , RULL(0x12040000), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_XFIR                                          , RULL(0x13040000), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_XFIR                                          , RULL(0x14040000), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_XFIR                                          , RULL(0x15040000), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_XFIR                                          , RULL(0x20040000), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_XFIR                                          , RULL(0x21040000), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_XFIR                                          , RULL(0x22040000), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_XFIR                                          , RULL(0x23040000), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_XFIR                                          , RULL(0x24040000), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_XFIR                                          , RULL(0x25040000), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_XFIR                                          , RULL(0x26040000), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_XFIR                                          , RULL(0x27040000), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_XFIR                                          , RULL(0x28040000), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_XFIR                                          , RULL(0x29040000), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_XFIR                                          , RULL(0x2A040000), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_XFIR                                          , RULL(0x2B040000), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_XFIR                                          , RULL(0x2C040000), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_XFIR                                          , RULL(0x2D040000), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_XFIR                                          , RULL(0x2E040000), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_XFIR                                          , RULL(0x2F040000), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_XFIR                                          , RULL(0x30040000), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_XFIR                                          , RULL(0x31040000), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_XFIR                                          , RULL(0x32040000), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_XFIR                                          , RULL(0x33040000), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_XFIR                                          , RULL(0x34040000), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_XFIR                                          , RULL(0x35040000), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_XFIR                                          , RULL(0x36040000), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_XFIR                                          , RULL(0x37040000), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_XSTOP1                                             , RULL(0x0003000C), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_XSTOP1                                          , RULL(0x0103000C), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_XSTOP1                                          , RULL(0x0203000C), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_XSTOP1                                          , RULL(0x0303000C), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_XSTOP1                                          , RULL(0x0403000C), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_XSTOP1                                          , RULL(0x0503000C), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_XSTOP1                                          , RULL(0x0603000C), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_XSTOP1                                        , RULL(0x0703000C), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_XSTOP1                                        , RULL(0x0803000C), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_XSTOP1                                         , RULL(0x0903000C), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_XSTOP1                                         , RULL(0x0C03000C), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_XSTOP1                                        , RULL(0x0D03000C), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_XSTOP1                                        , RULL(0x0E03000C), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_XSTOP1                                        , RULL(0x0F03000C), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_XSTOP1                                        , RULL(0x1003000C), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_XSTOP1                                        , RULL(0x1103000C), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_XSTOP1                                        , RULL(0x1203000C), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_XSTOP1                                        , RULL(0x1303000C), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_XSTOP1                                        , RULL(0x1403000C), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_XSTOP1                                        , RULL(0x1503000C), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_XSTOP1                                        , RULL(0x2003000C), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_XSTOP1                                        , RULL(0x2103000C), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_XSTOP1                                        , RULL(0x2203000C), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_XSTOP1                                        , RULL(0x2303000C), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_XSTOP1                                        , RULL(0x2403000C), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_XSTOP1                                        , RULL(0x2503000C), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_XSTOP1                                        , RULL(0x2603000C), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_XSTOP1                                        , RULL(0x2703000C), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_XSTOP1                                        , RULL(0x2803000C), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_XSTOP1                                        , RULL(0x2903000C), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_XSTOP1                                        , RULL(0x2A03000C), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_XSTOP1                                        , RULL(0x2B03000C), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_XSTOP1                                        , RULL(0x2C03000C), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_XSTOP1                                        , RULL(0x2D03000C), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_XSTOP1                                        , RULL(0x2E03000C), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_XSTOP1                                        , RULL(0x2F03000C), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_XSTOP1                                        , RULL(0x3003000C), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_XSTOP1                                        , RULL(0x3103000C), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_XSTOP1                                        , RULL(0x3203000C), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_XSTOP1                                        , RULL(0x3303000C), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_XSTOP1                                        , RULL(0x3403000C), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_XSTOP1                                        , RULL(0x3503000C), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_XSTOP1                                        , RULL(0x3603000C), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_XSTOP1                                        , RULL(0x3703000C), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_XSTOP2                                             , RULL(0x0003000D), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_XSTOP2                                          , RULL(0x0103000D), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_XSTOP2                                          , RULL(0x0203000D), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_XSTOP2                                          , RULL(0x0303000D), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_XSTOP2                                          , RULL(0x0403000D), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_XSTOP2                                          , RULL(0x0503000D), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_XSTOP2                                          , RULL(0x0603000D), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_XSTOP2                                        , RULL(0x0703000D), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_XSTOP2                                        , RULL(0x0803000D), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_XSTOP2                                         , RULL(0x0903000D), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_XSTOP2                                         , RULL(0x0C03000D), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_XSTOP2                                        , RULL(0x0D03000D), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_XSTOP2                                        , RULL(0x0E03000D), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_XSTOP2                                        , RULL(0x0F03000D), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_XSTOP2                                        , RULL(0x1003000D), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_XSTOP2                                        , RULL(0x1103000D), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_XSTOP2                                        , RULL(0x1203000D), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_XSTOP2                                        , RULL(0x1303000D), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_XSTOP2                                        , RULL(0x1403000D), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_XSTOP2                                        , RULL(0x1503000D), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_XSTOP2                                        , RULL(0x2003000D), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_XSTOP2                                        , RULL(0x2103000D), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_XSTOP2                                        , RULL(0x2203000D), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_XSTOP2                                        , RULL(0x2303000D), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_XSTOP2                                        , RULL(0x2403000D), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_XSTOP2                                        , RULL(0x2503000D), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_XSTOP2                                        , RULL(0x2603000D), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_XSTOP2                                        , RULL(0x2703000D), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_XSTOP2                                        , RULL(0x2803000D), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_XSTOP2                                        , RULL(0x2903000D), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_XSTOP2                                        , RULL(0x2A03000D), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_XSTOP2                                        , RULL(0x2B03000D), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_XSTOP2                                        , RULL(0x2C03000D), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_XSTOP2                                        , RULL(0x2D03000D), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_XSTOP2                                        , RULL(0x2E03000D), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_XSTOP2                                        , RULL(0x2F03000D), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_XSTOP2                                        , RULL(0x3003000D), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_XSTOP2                                        , RULL(0x3103000D), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_XSTOP2                                        , RULL(0x3203000D), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_XSTOP2                                        , RULL(0x3303000D), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_XSTOP2                                        , RULL(0x3403000D), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_XSTOP2                                        , RULL(0x3503000D), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_XSTOP2                                        , RULL(0x3603000D), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_XSTOP2                                        , RULL(0x3703000D), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_XSTOP3                                             , RULL(0x0003000E), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_XSTOP3                                          , RULL(0x0103000E), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_XSTOP3                                          , RULL(0x0203000E), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_XSTOP3                                          , RULL(0x0303000E), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_XSTOP3                                          , RULL(0x0403000E), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_XSTOP3                                          , RULL(0x0503000E), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_XSTOP3                                          , RULL(0x0603000E), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_XSTOP3                                        , RULL(0x0703000E), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_XSTOP3                                        , RULL(0x0803000E), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_XSTOP3                                         , RULL(0x0903000E), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_XSTOP3                                         , RULL(0x0C03000E), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_XSTOP3                                        , RULL(0x0D03000E), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_XSTOP3                                        , RULL(0x0E03000E), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_XSTOP3                                        , RULL(0x0F03000E), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_XSTOP3                                        , RULL(0x1003000E), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_XSTOP3                                        , RULL(0x1103000E), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_XSTOP3                                        , RULL(0x1203000E), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_XSTOP3                                        , RULL(0x1303000E), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_XSTOP3                                        , RULL(0x1403000E), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_XSTOP3                                        , RULL(0x1503000E), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_XSTOP3                                        , RULL(0x2003000E), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_XSTOP3                                        , RULL(0x2103000E), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_XSTOP3                                        , RULL(0x2203000E), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_XSTOP3                                        , RULL(0x2303000E), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_XSTOP3                                        , RULL(0x2403000E), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_XSTOP3                                        , RULL(0x2503000E), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_XSTOP3                                        , RULL(0x2603000E), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_XSTOP3                                        , RULL(0x2703000E), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_XSTOP3                                        , RULL(0x2803000E), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_XSTOP3                                        , RULL(0x2903000E), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_XSTOP3                                        , RULL(0x2A03000E), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_XSTOP3                                        , RULL(0x2B03000E), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_XSTOP3                                        , RULL(0x2C03000E), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_XSTOP3                                        , RULL(0x2D03000E), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_XSTOP3                                        , RULL(0x2E03000E), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_XSTOP3                                        , RULL(0x2F03000E), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_XSTOP3                                        , RULL(0x3003000E), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_XSTOP3                                        , RULL(0x3103000E), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_XSTOP3                                        , RULL(0x3203000E), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_XSTOP3                                        , RULL(0x3303000E), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_XSTOP3                                        , RULL(0x3403000E), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_XSTOP3                                        , RULL(0x3503000E), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_XSTOP3                                        , RULL(0x3603000E), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_XSTOP3                                        , RULL(0x3703000E), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_XSTOP_INTERRUPT_REG                                , RULL(0x000F001C), SH_UNT_PERV     ,
+       SH_ACS_SCOM      ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( PERV_TP_XSTOP_INTERRUPT_REG                             , RULL(0x010F001C), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+REG64( PERV_N0_XSTOP_INTERRUPT_REG                             , RULL(0x020F001C), SH_UNT_PERV_2   , SH_ACS_SCOM      );
+REG64( PERV_N1_XSTOP_INTERRUPT_REG                             , RULL(0x030F001C), SH_UNT_PERV_3   , SH_ACS_SCOM      );
+REG64( PERV_N2_XSTOP_INTERRUPT_REG                             , RULL(0x040F001C), SH_UNT_PERV_4   , SH_ACS_SCOM      );
+REG64( PERV_N3_XSTOP_INTERRUPT_REG                             , RULL(0x050F001C), SH_UNT_PERV_5   , SH_ACS_SCOM      );
+REG64( PERV_XB_XSTOP_INTERRUPT_REG                             , RULL(0x060F001C), SH_UNT_PERV_6   , SH_ACS_SCOM      );
+REG64( PERV_MC01_XSTOP_INTERRUPT_REG                           , RULL(0x070F001C), SH_UNT_PERV_7   , SH_ACS_SCOM      );
+REG64( PERV_MC23_XSTOP_INTERRUPT_REG                           , RULL(0x080F001C), SH_UNT_PERV_8   , SH_ACS_SCOM      );
+REG64( PERV_OB0_XSTOP_INTERRUPT_REG                            , RULL(0x090F001C), SH_UNT_PERV_9   , SH_ACS_SCOM      );
+REG64( PERV_OB3_XSTOP_INTERRUPT_REG                            , RULL(0x0C0F001C), SH_UNT_PERV_12  , SH_ACS_SCOM      );
+REG64( PERV_PCI0_XSTOP_INTERRUPT_REG                           , RULL(0x0D0F001C), SH_UNT_PERV_13  , SH_ACS_SCOM      );
+REG64( PERV_PCI1_XSTOP_INTERRUPT_REG                           , RULL(0x0E0F001C), SH_UNT_PERV_14  , SH_ACS_SCOM      );
+REG64( PERV_PCI2_XSTOP_INTERRUPT_REG                           , RULL(0x0F0F001C), SH_UNT_PERV_15  , SH_ACS_SCOM      );
+REG64( PERV_EP00_XSTOP_INTERRUPT_REG                           , RULL(0x100F001C), SH_UNT_PERV_16  , SH_ACS_SCOM      );
+REG64( PERV_EP01_XSTOP_INTERRUPT_REG                           , RULL(0x110F001C), SH_UNT_PERV_17  , SH_ACS_SCOM      );
+REG64( PERV_EP02_XSTOP_INTERRUPT_REG                           , RULL(0x120F001C), SH_UNT_PERV_18  , SH_ACS_SCOM      );
+REG64( PERV_EP03_XSTOP_INTERRUPT_REG                           , RULL(0x130F001C), SH_UNT_PERV_19  , SH_ACS_SCOM      );
+REG64( PERV_EP04_XSTOP_INTERRUPT_REG                           , RULL(0x140F001C), SH_UNT_PERV_20  , SH_ACS_SCOM      );
+REG64( PERV_EP05_XSTOP_INTERRUPT_REG                           , RULL(0x150F001C), SH_UNT_PERV_21  , SH_ACS_SCOM      );
+REG64( PERV_EC00_XSTOP_INTERRUPT_REG                           , RULL(0x200F001C), SH_UNT_PERV_32  , SH_ACS_SCOM      );
+REG64( PERV_EC01_XSTOP_INTERRUPT_REG                           , RULL(0x210F001C), SH_UNT_PERV_33  , SH_ACS_SCOM      );
+REG64( PERV_EC02_XSTOP_INTERRUPT_REG                           , RULL(0x220F001C), SH_UNT_PERV_34  , SH_ACS_SCOM      );
+REG64( PERV_EC03_XSTOP_INTERRUPT_REG                           , RULL(0x230F001C), SH_UNT_PERV_35  , SH_ACS_SCOM      );
+REG64( PERV_EC04_XSTOP_INTERRUPT_REG                           , RULL(0x240F001C), SH_UNT_PERV_36  , SH_ACS_SCOM      );
+REG64( PERV_EC05_XSTOP_INTERRUPT_REG                           , RULL(0x250F001C), SH_UNT_PERV_37  , SH_ACS_SCOM      );
+REG64( PERV_EC06_XSTOP_INTERRUPT_REG                           , RULL(0x260F001C), SH_UNT_PERV_38  , SH_ACS_SCOM      );
+REG64( PERV_EC07_XSTOP_INTERRUPT_REG                           , RULL(0x270F001C), SH_UNT_PERV_39  , SH_ACS_SCOM      );
+REG64( PERV_EC08_XSTOP_INTERRUPT_REG                           , RULL(0x280F001C), SH_UNT_PERV_40  , SH_ACS_SCOM      );
+REG64( PERV_EC09_XSTOP_INTERRUPT_REG                           , RULL(0x290F001C), SH_UNT_PERV_41  , SH_ACS_SCOM      );
+REG64( PERV_EC10_XSTOP_INTERRUPT_REG                           , RULL(0x2A0F001C), SH_UNT_PERV_42  , SH_ACS_SCOM      );
+REG64( PERV_EC11_XSTOP_INTERRUPT_REG                           , RULL(0x2B0F001C), SH_UNT_PERV_43  , SH_ACS_SCOM      );
+REG64( PERV_EC12_XSTOP_INTERRUPT_REG                           , RULL(0x2C0F001C), SH_UNT_PERV_44  , SH_ACS_SCOM      );
+REG64( PERV_EC13_XSTOP_INTERRUPT_REG                           , RULL(0x2D0F001C), SH_UNT_PERV_45  , SH_ACS_SCOM      );
+REG64( PERV_EC14_XSTOP_INTERRUPT_REG                           , RULL(0x2E0F001C), SH_UNT_PERV_46  , SH_ACS_SCOM      );
+REG64( PERV_EC15_XSTOP_INTERRUPT_REG                           , RULL(0x2F0F001C), SH_UNT_PERV_47  , SH_ACS_SCOM      );
+REG64( PERV_EC16_XSTOP_INTERRUPT_REG                           , RULL(0x300F001C), SH_UNT_PERV_48  , SH_ACS_SCOM      );
+REG64( PERV_EC17_XSTOP_INTERRUPT_REG                           , RULL(0x310F001C), SH_UNT_PERV_49  , SH_ACS_SCOM      );
+REG64( PERV_EC18_XSTOP_INTERRUPT_REG                           , RULL(0x320F001C), SH_UNT_PERV_50  , SH_ACS_SCOM      );
+REG64( PERV_EC19_XSTOP_INTERRUPT_REG                           , RULL(0x330F001C), SH_UNT_PERV_51  , SH_ACS_SCOM      );
+REG64( PERV_EC20_XSTOP_INTERRUPT_REG                           , RULL(0x340F001C), SH_UNT_PERV_52  , SH_ACS_SCOM      );
+REG64( PERV_EC21_XSTOP_INTERRUPT_REG                           , RULL(0x350F001C), SH_UNT_PERV_53  , SH_ACS_SCOM      );
+REG64( PERV_EC22_XSTOP_INTERRUPT_REG                           , RULL(0x360F001C), SH_UNT_PERV_54  , SH_ACS_SCOM      );
+REG64( PERV_EC23_XSTOP_INTERRUPT_REG                           , RULL(0x370F001C), SH_UNT_PERV_55  , SH_ACS_SCOM      );
+
+REG64( PERV_XTRA_TRACE_MODE                                    , RULL(0x000107D1), SH_UNT_PERV     , SH_ACS_SCOM      );
+REG64( PERV_TP_XTRA_TRACE_MODE                                 , RULL(0x010107D1), SH_UNT_PERV_1   , SH_ACS_SCOM      );
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9_perv_scom_addresses_fixes.H b/src/import/chips/p9/common/include/p9_perv_scom_addresses_fixes.H
new file mode 100644
index 00000000..f835e4d8
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_perv_scom_addresses_fixes.H
@@ -0,0 +1,75 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_perv_scom_addresses_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file perv_scom_addresses_fixes.H
+/// @brief The *scom_addresses.H files are  generated form figtree, but
+///        the figree can be wrong.  This file is included at the end
+///        of scom_addresses.H and allows incorrect constants to be
+///        fixed manually.
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SAO
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+
+#ifndef __P9_PERV_SCOM_ADDRESSES_FIXES_H
+#define __P9_PERV_SCOM_ADDRESSES_FIXES_H
+
+
+
+//Example,
+//Copy the whole line from the *scom_addresses.H file.  Then add
+//FIX in front of REG, and add another paramter that is the new
+//corrected value.
+//FIXREG64( PU_ALTD_ADDR_REG,
+//          RULL(0x05022800), SH_UNT, SH_ACS_SCOM,
+//          RULL(0x00090000)
+//        );
+
+static const uint64_t SH_UNT_PERV_10 = 512;
+static const uint64_t SH_UNT_PERV_11 = 513;
+static const uint64_t SH_UNT_PERV_CBS_ENVSTAT = 514;
+
+REG64( PERV_OB1_CPLT_CONF1,
+       RULL(0x0A000009), SH_UNT_PERV_10, SH_ACS_SCOM_RW);
+REG64( PERV_OB1_CPLT_CONF1_OR,
+       RULL(0x0A000019), SH_UNT_PERV_10, SH_ACS_SCOM1_OR);
+REG64( PERV_OB1_CPLT_CONF1_CLEAR,
+       RULL(0x0A000029), SH_UNT_PERV_10, SH_ACS_SCOM2_CLEAR);
+
+REG64( PERV_OB2_CPLT_CONF1,
+       RULL(0x0B000009), SH_UNT_PERV_11, SH_ACS_SCOM_RW);
+REG64( PERV_OB2_CPLT_CONF1_OR,
+       RULL(0x0B000019), SH_UNT_PERV_11, SH_ACS_SCOM1_OR);
+REG64( PERV_OB2_CPLT_CONF1_CLEAR,
+       RULL(0x0B000029), SH_UNT_PERV_11, SH_ACS_SCOM2_CLEAR);
+
+REG32( PERV_CBS_ENVSTAT_FSI, RULL(0x00002804), SH_UNT_PERV_CBS_ENVSTAT, SH_ACS_FSI);
+REG64( PERV_CBS_ENVSTAT_FSI_BYTE, RULL(0x00002810), SH_UNT_PERV_CBS_ENVSTAT, SH_ACS_FSI_BYTE);
+REG64( PERV_CBS_ENVSTAT_SCOM, RULL(0x00050004), SH_UNT_PERV_CBS_ENVSTAT, SH_ACS_SCOM);
+
+#endif
diff --git a/src/import/chips/p9/common/include/p9_perv_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_perv_scom_addresses_fld.H
new file mode 100644
index 00000000..78b6cf8d
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_perv_scom_addresses_fld.H
@@ -0,0 +1,8954 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_perv_scom_addresses_fld.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_perv_scom_addresses_fld.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#include <p9_const_common.H>
+
+#ifndef __P9_PERV_SCOM_ADDRESSES_FLD_H
+#define __P9_PERV_SCOM_ADDRESSES_FLD_H
+
+
+#include <p9_scom_template_consts.H>
+#include <p9_perv_scom_addresses_fld_fixes.H>
+
+REG64_FLD( PERV_1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( PERV_1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN );
+REG64_FLD( PERV_1_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( PERV_1_ADDR_TRAP_REG_RESERVED_LAST_LT                   , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LAST_LT );
+REG64_FLD( PERV_1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR );
+REG64_FLD( PERV_1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN );
+REG64_FLD( PERV_1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY );
+REG64_FLD( PERV_1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR );
+REG64_FLD( PERV_1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION );
+REG64_FLD( PERV_1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER );
+
+REG64_FLD( PERV_1_ATOMIC_LOCK_MASK_LATCH_REG_MASK                  , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASK       );
+REG64_FLD( PERV_1_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN              , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( PERV_1_ATOMIC_LOCK_REG_ENABLE                           , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PERV_1_ATOMIC_LOCK_REG_ID                               , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( PERV_1_ATOMIC_LOCK_REG_ID_LEN                           , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ID_LEN     );
+REG64_FLD( PERV_1_ATOMIC_LOCK_REG_ACTIVITY                         , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY   );
+REG64_FLD( PERV_1_ATOMIC_LOCK_REG_ACTIVITY_LEN                     , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( PERV_1_BIST_TC_START_TEST_DC                            , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TC_START_TEST_DC );
+REG64_FLD( PERV_1_BIST_TC_SRAM_ABIST_MODE_DC                       , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TC_SRAM_ABIST_MODE_DC );
+REG64_FLD( PERV_1_BIST_TC_EDRAM_ABIST_MODE_DC                      , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TC_EDRAM_ABIST_MODE_DC );
+REG64_FLD( PERV_1_BIST_TC_IOBIST_MODE_DC                           , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TC_IOBIST_MODE_DC );
+REG64_FLD( PERV_1_BIST_PERV                                        , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( PERV_1_BIST_UNIT1                                       , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( PERV_1_BIST_UNIT2                                       , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( PERV_1_BIST_UNIT3                                       , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( PERV_1_BIST_UNIT4                                       , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( PERV_1_BIST_UNIT5                                       , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( PERV_1_BIST_UNIT6                                       , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( PERV_1_BIST_UNIT7                                       , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( PERV_1_BIST_UNIT8                                       , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( PERV_1_BIST_UNIT9                                       , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( PERV_1_BIST_UNIT10                                      , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( PERV_1_BIST_STROBE_WINDOW_EN                            , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STROBE_WINDOW_EN );
+
+REG64_FLD( PERV_BIT_SEL_REG_2_SELECT_REGISTER_FSP2PIB              , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SELECT_REGISTER_FSP2PIB );
+REG64_FLD( PERV_BIT_SEL_REG_2_SELECT_REGISTER_FSP2PIB_LEN          , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SELECT_REGISTER_FSP2PIB_LEN );
+
+REG64_FLD( PERV_CBS_CS_START_BOOT_SEQUENCER                        , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_START_BOOT_SEQUENCER );
+REG64_FLD( PERV_CBS_CS_1_UNUSED                                    , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_1_UNUSED   );
+REG64_FLD( PERV_CBS_CS_OPTION_SKIP_SCAN0_CLOCKSTART                , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OPTION_SKIP_SCAN0_CLOCKSTART );
+REG64_FLD( PERV_CBS_CS_OPTION_PREVENT_SBE_START                    , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OPTION_PREVENT_SBE_START );
+REG64_FLD( PERV_CBS_CS_SECURE_ACCESS_BIT                           , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SECURE_ACCESS_BIT );
+REG64_FLD( PERV_CBS_CS_SAMPLED_SMD_PIN                             , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLED_SMD_PIN );
+REG64_FLD( PERV_CBS_CS_STATE_MACHINE_TRANSITION_DELAY              , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_STATE_MACHINE_TRANSITION_DELAY );
+REG64_FLD( PERV_CBS_CS_STATE_MACHINE_TRANSITION_DELAY_LEN          , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_STATE_MACHINE_TRANSITION_DELAY_LEN );
+REG64_FLD( PERV_CBS_CS_INTERNAL_STATE_VECTOR                       , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_INTERNAL_STATE_VECTOR );
+REG64_FLD( PERV_CBS_CS_INTERNAL_STATE_VECTOR_LEN                   , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_INTERNAL_STATE_VECTOR_LEN );
+
+REG64_FLD( PERV_CBS_STAT_DBG_RESET_EP                              , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_RESET_EP );
+REG64_FLD( PERV_CBS_STAT_DBG_OPCG_IP                               , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_OPCG_IP );
+REG64_FLD( PERV_CBS_STAT_DBG_VITL_CLKOFF                           , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_VITL_CLKOFF );
+REG64_FLD( PERV_CBS_STAT_DBG_TEST_ENABLE                           , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_TEST_ENABLE );
+REG64_FLD( PERV_CBS_STAT_DBG_REQ                                   , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_REQ    );
+REG64_FLD( PERV_CBS_STAT_DBG_CMD                                   , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_CMD    );
+REG64_FLD( PERV_CBS_STAT_DBG_CMD_LEN                               , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_CMD_LEN );
+REG64_FLD( PERV_CBS_STAT_DBG_STATE                                 , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_STATE  );
+REG64_FLD( PERV_CBS_STAT_DBG_STATE_LEN                             , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_STATE_LEN );
+REG64_FLD( PERV_CBS_STAT_DBG_SECURITY_DEBUG_MODE                   , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_SECURITY_DEBUG_MODE );
+REG64_FLD( PERV_CBS_STAT_DBG_PROTOCOL_ERROR                        , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_PROTOCOL_ERROR );
+REG64_FLD( PERV_CBS_STAT_DBG_PCB_IDLE                              , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_PCB_IDLE );
+REG64_FLD( PERV_CBS_STAT_DBG_CURRENT_OPCG_MODE                     , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_CURRENT_OPCG_MODE );
+REG64_FLD( PERV_CBS_STAT_DBG_CURRENT_OPCG_MODE_LEN                 , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_CURRENT_OPCG_MODE_LEN );
+REG64_FLD( PERV_CBS_STAT_DBG_LAST_OPCG_MODE                        , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_LAST_OPCG_MODE );
+REG64_FLD( PERV_CBS_STAT_DBG_LAST_OPCG_MODE_LEN                    , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_LAST_OPCG_MODE_LEN );
+REG64_FLD( PERV_CBS_STAT_DBG_PCB_ERROR                             , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_PCB_ERROR );
+REG64_FLD( PERV_CBS_STAT_DBG_PARITY_ERROR                          , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_PARITY_ERROR );
+REG64_FLD( PERV_CBS_STAT_DBG_CC_ERROR                              , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_CC_ERROR );
+REG64_FLD( PERV_CBS_STAT_DBG_CHIPLET_IS_ALIGNED                    , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_CHIPLET_IS_ALIGNED );
+REG64_FLD( PERV_CBS_STAT_DBG_PCB_REQUEST_SINCE_RESET               , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_PCB_REQUEST_SINCE_RESET );
+REG64_FLD( PERV_CBS_STAT_DBG_PARANOIA_TEST_ENABLE_CHANGE           , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_PARANOIA_TEST_ENABLE_CHANGE );
+REG64_FLD( PERV_CBS_STAT_DBG_PARANOIA_VITL_CLKOFF_CHANGE           , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_PARANOIA_VITL_CLKOFF_CHANGE );
+REG64_FLD( PERV_CBS_STAT_DBG_TP_TPFSI_ACK                          , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DBG_TP_TPFSI_ACK );
+
+REG64_FLD( PERV_CBS_TR_SIGNATURE                                   , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SIGNATURE  );
+REG64_FLD( PERV_CBS_TR_SIGNATURE_LEN                               , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SIGNATURE_LEN );
+REG64_FLD( PERV_CBS_TR_UNUSED                                      , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PERV_CBS_TR_UNUSED_LEN                                  , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PERV_CBS_TR_TRANS_DELAY                                 , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TRANS_DELAY );
+REG64_FLD( PERV_CBS_TR_TRANS_DELAY_LEN                             , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TRANS_DELAY_LEN );
+
+REG64_FLD( PERV_1_CC_ATOMIC_LOCK_REG_ENABLE                        , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PERV_1_CC_ATOMIC_LOCK_REG_ID                            , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( PERV_1_CC_ATOMIC_LOCK_REG_ID_LEN                        , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ID_LEN     );
+REG64_FLD( PERV_1_CC_ATOMIC_LOCK_REG_ACTIVITY                      , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY   );
+REG64_FLD( PERV_1_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN                  , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( PERV_1_CC_PROTECT_MODE_REG_READ_ENABLE                  , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_READ_ENABLE );
+REG64_FLD( PERV_1_CC_PROTECT_MODE_REG_WRITE_ENABLE                 , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_CMD                             , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_CMD  );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_CMD_LEN                         , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_CMD_LEN );
+REG64_FLD( PERV_1_CLK_REGION_SLAVE_MODE                            , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE_MODE );
+REG64_FLD( PERV_1_CLK_REGION_MASTER_MODE                           , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_MODE );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_PERV                            , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_PERV );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT1                           , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT1 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT2                           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT2 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT3                           , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT3 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT4                           , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT4 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT5                           , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT5 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT6                           , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT6 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT7                           , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT7 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT8                           , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT8 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT9                           , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT9 );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_UNIT10                          , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT10 );
+REG64_FLD( PERV_1_CLK_REGION_SEL_THOLD_SL                          , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_SL );
+REG64_FLD( PERV_1_CLK_REGION_SEL_THOLD_NSL                         , 49  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_NSL );
+REG64_FLD( PERV_1_CLK_REGION_SEL_THOLD_ARY                         , 50  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_ARY );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_PULSE_USE_EVEN                  , 52  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_PULSE_USE_EVEN );
+
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_PERV                       , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_PERV );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT1                      , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT1 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT2                      , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT2 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT3                      , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT3 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT4                      , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT4 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT5                      , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT5 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT6                      , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT6 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT7                      , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT7 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT8                      , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT8 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT9                      , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT9 );
+REG64_FLD( PERV_1_CLOCK_STAT_ARY_STATUS_UNIT10                     , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_PERV                       , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_PERV );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT1                      , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT1 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT2                      , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT2 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT3                      , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT3 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT4                      , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT4 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT5                      , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT5 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT6                      , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT6 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT7                      , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT7 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT8                      , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT8 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT9                      , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT9 );
+REG64_FLD( PERV_1_CLOCK_STAT_NSL_STATUS_UNIT10                     , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_PERV                        , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_PERV );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT1                       , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT1 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT2                       , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT2 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT3                       , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT3 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT4                       , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT4 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT5                       , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT5 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT6                       , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT6 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT7                       , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT7 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT8                       , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT8 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT9                       , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT9 );
+REG64_FLD( PERV_1_CLOCK_STAT_SL_STATUS_UNIT10                      , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( PERV_PIB2OPB1_CMD_WRDAT_WRITE_NOT_READ                  , 0   , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM     ,
+           SH_FLD_WRITE_NOT_READ );
+
+REG64_FLD( PERV_CMD_WRDAT_WRITE_NOT_READ                           , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_NOT_READ );
+
+REG64_FLD( PERV_PIB2OPB0_CMD_WRDAT_WRITE_NOT_READ                  , 0   , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM     ,
+           SH_FLD_WRITE_NOT_READ );
+
+REG32_FLD( PERV_FSI2PIB_COMMAND_REGISTER_CMD_REG                   , 0   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_CMD_REG    );
+REG32_FLD( PERV_FSI2PIB_COMMAND_REGISTER_CMD_REG_LEN               , 32  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_CMD_REG_LEN );
+
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_WRITE_FLAG        , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_CMDREG_WRITE_FLAG );
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_BROADCAST_FLAG    , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_CMDREG_BROADCAST_FLAG );
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_ADDRESS      , 2   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_CMDREG_SCAN_ADDRESS );
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_ADDRESS_LEN  , 14  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_CMDREG_SCAN_ADDRESS_LEN );
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_REGION       , 16  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_CMDREG_SCAN_REGION );
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_REGION_LEN   , 12  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_CMDREG_SCAN_REGION_LEN );
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_TYPE         , 28  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_CMDREG_SCAN_TYPE );
+REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_TYPE_LEN     , 4   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_CMDREG_SCAN_TYPE_LEN );
+
+REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_WITH_START_0             , 0   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_WITH_START_0 );
+REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_WITH_ADDRESS_0           , 1   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_WITH_ADDRESS_0 );
+REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_READ_CONTINUE_0          , 2   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_READ_CONTINUE_0 );
+REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_WITH_STOP_0              , 3   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_WITH_STOP_0 );
+REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_NOT_USED_0               , 4   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_NOT_USED_0 );
+REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_NOT_USED_0_LEN           , 4   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_NOT_USED_0_LEN );
+REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_DEVICE_ADDRESS_0         , 8   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_DEVICE_ADDRESS_0 );
+REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_DEVICE_ADDRESS_0_LEN     , 7   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_DEVICE_ADDRESS_0_LEN );
+REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_READ_NOT_WRITE_0         , 15  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_READ_NOT_WRITE_0 );
+REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_LENGTH_IN_BYTES_0        , 16  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_LENGTH_IN_BYTES_0 );
+REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_LENGTH_IN_BYTES_0_LEN    , 16  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_LENGTH_IN_BYTES_0_LEN );
+
+REG32_FLD( PERV_FSI2PIB_COMPLEMENT_MASK_REG                        , 0   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG        );
+REG32_FLD( PERV_FSI2PIB_COMPLEMENT_MASK_REG_LEN                    , 32  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG_LEN    );
+
+REG32_FLD( PERV_FSISHIFT_COMPLEMENT_MASK_REG                       , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG        );
+REG32_FLD( PERV_FSISHIFT_COMPLEMENT_MASK_REG_LEN                   , 32  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG_LEN    );
+
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC               , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE0_SEL_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_6C                           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_6C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_7C                           , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_7C );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC               , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE1_SEL_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_14C                          , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_14C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_15C                          , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_15C );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC               , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE2_SEL_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_22C                          , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_22C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_23C                          , 23  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_23C );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC               , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE3_SEL_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_30C                          , 30  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_30C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_31C                          , 31  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_31C );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC              , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC               , 33  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_SCAN_PROTECT_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_CC_SDIS_DC_N                     , 34  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_SDIS_DC_N );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_TEST_CONTROL_35C             , 35  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_35C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_TEST_CONTROL_36C             , 36  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_36C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_TEST_CONTROL_37C             , 37  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_37C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_TEST_CONTROL_38C             , 38  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_38C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_TEST_CONTROL_39C             , 39  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_39C );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC         , 40  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC    , 41  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_42C                          , 42  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_42C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_43C                          , 43  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_43C );
+REG64_FLD( PERV_1_CPLT_CONF0_FREE_USAGE_44C                        , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_44C );
+REG64_FLD( PERV_1_CPLT_CONF0_FREE_USAGE_45C                        , 45  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_45C );
+REG64_FLD( PERV_1_CPLT_CONF0_FREE_USAGE_46C                        , 46  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_46C );
+REG64_FLD( PERV_1_CPLT_CONF0_FREE_USAGE_47C                        , 47  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_47C );
+REG64_FLD( PERV_1_CPLT_CONF0_TC_UNIT_GROUP_ID_DC                   , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_GROUP_ID_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN               , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_GROUP_ID_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CONF0_TC_UNIT_CHIP_ID_DC                    , 52  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_CHIP_ID_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN                , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_CHIP_ID_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_ID_55C                       , 55  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_55C );
+REG64_FLD( PERV_1_CPLT_CONF0_TC_UNIT_SYS_ID_DC                     , 56  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_SYS_ID_DC );
+REG64_FLD( PERV_1_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN                 , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_SYS_ID_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_ID_61C                       , 61  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_61C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_ID_62C                       , 62  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_62C );
+REG64_FLD( PERV_1_CPLT_CONF0_RESERVED_ID_63C                       , 63  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_63C );
+
+REG64_FLD( PERV_1_CPLT_CONF1_TCPERV_AMUX_VSELECT_CHIP              , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCPERV_AMUX_VSELECT_CHIP );
+REG64_FLD( PERV_1_CPLT_CONF1_TCPERV_AMUX_VSELECT_CHIP_LEN          , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCPERV_AMUX_VSELECT_CHIP_LEN );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_4D                            , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_IOVALID_4D );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_5D                            , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_IOVALID_5D );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_6D                            , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_IOVALID_6D );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_7D                            , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_IOVALID_7D );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_8D                            , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_IOVALID_8D );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_9D                            , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_IOVALID_9D );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_10D                           , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_IOVALID_10D );
+REG64_FLD( PERV_1_CPLT_CONF1_IOVALID_11D                           , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_IOVALID_11D );
+REG64_FLD( PERV_1_CPLT_CONF1_TP_IO_SPI_APSS_MCPRECOMP              , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TP_IO_SPI_APSS_MCPRECOMP );
+REG64_FLD( PERV_1_CPLT_CONF1_TP_IO_SPI_APSS_MCPRECOMP_LEN          , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TP_IO_SPI_APSS_MCPRECOMP_LEN );
+REG64_FLD( PERV_1_CPLT_CONF1_TP_IO_SPARE2_MCPRECOMP                , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TP_IO_SPARE2_MCPRECOMP );
+REG64_FLD( PERV_1_CPLT_CONF1_TP_IO_SPARE2_MCPRECOMP_LEN            , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TP_IO_SPARE2_MCPRECOMP_LEN );
+REG64_FLD( PERV_1_CPLT_CONF1_TP_IO_SPARE3_MCPRECOMP                , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TP_IO_SPARE3_MCPRECOMP );
+REG64_FLD( PERV_1_CPLT_CONF1_TP_IO_SPARE3_MCPRECOMP_LEN            , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TP_IO_SPARE3_MCPRECOMP_LEN );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_18D                        , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_18D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_19D                        , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_19D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_20D                        , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_20D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_21D                        , 21  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_21D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_22D                        , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_22D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_23D                        , 23  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_23D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_24D                        , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_24D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_25D                        , 25  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_25D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_26D                        , 26  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_26D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_27D                        , 27  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_27D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_28D                        , 28  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_28D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_29D                        , 29  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_29D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_30D                        , 30  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_30D );
+REG64_FLD( PERV_1_CPLT_CONF1_FREE_USAGE_31D                        , 31  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_31D );
+
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC             , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC             , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC              , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_FLUSHMODE_INH_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC                , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_FORCE_ALIGN_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC               , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_ARY_WRT_THRU_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_UNIT_AVP_MODE                      , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_AVP_MODE );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_6A                         , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_6A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_7A                         , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_7A );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC        , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_9A                         , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_9A );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC      , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_11A                          , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_11A );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_SKIT_MODE_BIST_DC                  , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_SKIT_MODE_BIST_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC  , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC         , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC           , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_NBTI_HDR_ENABLE_OVR_DC             , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_NBTI_PROBE_GATE_DC                 , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_NBTI_PROBE_GATE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_18A                          , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_18A );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_19A                          , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_19A );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_PSRO_SEL_DC                        , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PSRO_SEL_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_PSRO_SEL_DC_LEN                    , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PSRO_SEL_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_BSC_WRAPSEL_DC                     , 28  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_WRAPSEL_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_BSC_INTMODE_DC                     , 29  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_INTMODE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_BSC_INV_DC                         , 30  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_INV_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_BSC_EXTMODE_DC                     , 31  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_EXTMODE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_REFCLK_DRVR_EN_DC                  , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REFCLK_DRVR_EN_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_33A                          , 33  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_33A );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_34A                          , 34  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_34A );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_35A                          , 35  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_35A );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_OELCC_EDGE_DELAYED_DC              , 36  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_OELCC_EDGE_DELAYED_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_TC_OELCC_ALIGN_FLUSH_DC               , 37  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_OELCC_ALIGN_FLUSH_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_38A                          , 38  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_38A );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_39A                          , 39  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_39A );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC               , 40  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_CLKDIV_SEL_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN           , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_42A                          , 42  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_42A );
+REG64_FLD( PERV_1_CPLT_CTRL0_RESERVED_43A                          , 43  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_43A );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_DCTEST_DC                     , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_DCTEST_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_OTP_PRGMODE_DC                , 45  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_OTP_PRGMODE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_SSS_CALIBRATE_DC              , 46  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_SSS_CALIBRATE_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC                  , 47  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_PIN_LBIST_DC );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_48A                        , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_48A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_49A                        , 49  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_49A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_50A                        , 50  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_50A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_51A                        , 51  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_51A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_52A                        , 52  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_52A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_53A                        , 53  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_53A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_54A                        , 54  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_54A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_55A                        , 55  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_55A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_56A                        , 56  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_56A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_57A                        , 57  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_57A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_58A                        , 58  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_58A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_59A                        , 59  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_59A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_60A                        , 60  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_60A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_61A                        , 61  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_61A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_62A                        , 62  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_62A );
+REG64_FLD( PERV_1_CPLT_CTRL0_FREE_USAGE_63A                        , 63  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_63A );
+
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_0B                             , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_0B  );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_1B                             , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_1B  );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_2B                             , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_2B  );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_VITL_REGION_FENCE                  , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_VITL_REGION_FENCE );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_PERV_REGION_FENCE                  , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PERV_REGION_FENCE );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_5B                             , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_5B  );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_6B                             , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_6B  );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_REGION3_FENCE                      , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION3_FENCE );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_8B                             , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_8B  );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_9B                             , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_9B  );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_10B                            , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_10B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_11B                            , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_11B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_12B                            , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_12B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_13B                            , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_13B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_14B                            , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_14B );
+REG64_FLD( PERV_1_CPLT_CTRL1_RESERVED                              , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED   );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE         , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_17B                            , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_17B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_18B                            , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_18B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_19B                            , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_19B );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_PERV_EXPORT_FREEZE                 , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PERV_EXPORT_FREEZE );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_21B                            , 21  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_21B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_22B                            , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_22B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_23B                            , 23  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_23B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_24B                            , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_24B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_25B                            , 25  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_25B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_26B                            , 26  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_26B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_27B                            , 27  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_27B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_28B                            , 28  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_28B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_29B                            , 29  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_29B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_30B                            , 30  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_30B );
+REG64_FLD( PERV_1_CPLT_CTRL1_UNUSED_31B                            , 31  , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_31B );
+
+REG64_FLD( PERV_1_CPLT_MASK0_CPLTMASK0                             , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CPLTMASK0  );
+REG64_FLD( PERV_1_CPLT_MASK0_CPLTMASK0_LEN                         , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CPLTMASK0_LEN );
+
+REG64_FLD( PERV_1_CPLT_STAT0_SRAM_ABIST_DONE_DC                    , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SRAM_ABIST_DONE_DC );
+REG64_FLD( PERV_1_CPLT_STAT0_DRAM_ABIST_DONE_DC                    , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DRAM_ABIST_DONE_DC );
+REG64_FLD( PERV_1_CPLT_STAT0_RESERVED_2E                           , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_2E );
+REG64_FLD( PERV_1_CPLT_STAT0_RESERVED_3E                           , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_3E );
+REG64_FLD( PERV_1_CPLT_STAT0_TC_DIAG_PORT0_OUT                     , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TC_DIAG_PORT0_OUT );
+REG64_FLD( PERV_1_CPLT_STAT0_TC_DIAG_PORT1_OUT                     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TC_DIAG_PORT1_OUT );
+REG64_FLD( PERV_1_CPLT_STAT0_RESERVED_6E                           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_6E );
+REG64_FLD( PERV_1_CPLT_STAT0_PLL_DESTOUT                           , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PLL_DESTOUT );
+REG64_FLD( PERV_1_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC                  , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CC_CTRL_OPCG_DONE_DC );
+REG64_FLD( PERV_1_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC         , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_10E                        , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_10E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_11E                        , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_11E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_12E                        , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_12E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_13E                        , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_13E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_14E                        , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_14E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_15E                        , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_15E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_16E                        , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_16E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_17E                        , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_17E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_18E                        , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_18E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_19E                        , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_19E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_20E                        , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_20E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_21E                        , 21  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_21E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_22E                        , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_22E );
+REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_23E                        , 23  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_23E );
+
+REG64_FLD( PERV_1_CTRL_ATOMIC_LOCK_REG_ENABLE                      , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PERV_1_CTRL_ATOMIC_LOCK_REG_ID                          , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( PERV_1_CTRL_ATOMIC_LOCK_REG_ID_LEN                      , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ID_LEN     );
+REG64_FLD( PERV_1_CTRL_ATOMIC_LOCK_REG_ACTIVITY                    , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY   );
+REG64_FLD( PERV_1_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN                , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( PERV_1_CTRL_PROTECT_MODE_REG_READ_ENABLE                , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_READ_ENABLE );
+REG64_FLD( PERV_1_CTRL_PROTECT_MODE_REG_WRITE_ENABLE               , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_ENABLE );
+
+REG32_FLD( PERV_FSI2PIB_DATA_REGISTER_0_REG                        , 0   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI      ,
+           SH_FLD_REG        );
+REG32_FLD( PERV_FSI2PIB_DATA_REGISTER_0_REG_LEN                    , 32  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI      ,
+           SH_FLD_REG_LEN    );
+
+REG32_FLD( PERV_FSI2PIB_DATA_REGISTER_1_REG                        , 0   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG        );
+REG32_FLD( PERV_FSI2PIB_DATA_REGISTER_1_REG_LEN                    , 32  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG_LEN    );
+
+REG64_FLD( PERV_1_DBG_CBS_CC_RESET_EP                              , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET_EP   );
+REG64_FLD( PERV_1_DBG_CBS_CC_OPCG_IP                               , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_OPCG_IP    );
+REG64_FLD( PERV_1_DBG_CBS_CC_VITL_CLKOFF                           , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_VITL_CLKOFF );
+REG64_FLD( PERV_1_DBG_CBS_CC_TEST_ENABLE                           , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TEST_ENABLE );
+REG64_FLD( PERV_1_DBG_CBS_CC_REQ                                   , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_REQ        );
+REG64_FLD( PERV_1_DBG_CBS_CC_CMD                                   , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CMD        );
+REG64_FLD( PERV_1_DBG_CBS_CC_CMD_LEN                               , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CMD_LEN    );
+REG64_FLD( PERV_1_DBG_CBS_CC_STATE                                 , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATE      );
+REG64_FLD( PERV_1_DBG_CBS_CC_STATE_LEN                             , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATE_LEN  );
+REG64_FLD( PERV_1_DBG_CBS_CC_SECURITY_DEBUG_MODE                   , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SECURITY_DEBUG_MODE );
+REG64_FLD( PERV_1_DBG_CBS_CC_PROTOCOL_ERROR                        , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PROTOCOL_ERROR );
+REG64_FLD( PERV_1_DBG_CBS_CC_PCB_IDLE                              , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PCB_IDLE   );
+REG64_FLD( PERV_1_DBG_CBS_CC_CURRENT_OPCG_MODE                     , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CURRENT_OPCG_MODE );
+REG64_FLD( PERV_1_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN                 , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CURRENT_OPCG_MODE_LEN );
+REG64_FLD( PERV_1_DBG_CBS_CC_LAST_OPCG_MODE                        , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_LAST_OPCG_MODE );
+REG64_FLD( PERV_1_DBG_CBS_CC_LAST_OPCG_MODE_LEN                    , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_LAST_OPCG_MODE_LEN );
+REG64_FLD( PERV_1_DBG_CBS_CC_PCB_ERROR                             , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ERROR  );
+REG64_FLD( PERV_1_DBG_CBS_CC_PARITY_ERROR                          , 25  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ERROR );
+REG64_FLD( PERV_1_DBG_CBS_CC_ERROR                                 , 26  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERROR      );
+REG64_FLD( PERV_1_DBG_CBS_CC_CHIPLET_IS_ALIGNED                    , 27  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_IS_ALIGNED );
+REG64_FLD( PERV_1_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET               , 28  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PCB_REQUEST_SINCE_RESET );
+REG64_FLD( PERV_1_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE           , 29  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PARANOIA_TEST_ENABLE_CHANGE );
+REG64_FLD( PERV_1_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE           , 30  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE );
+REG64_FLD( PERV_1_DBG_CBS_CC_TP_TPFSI_ACK                          , 31  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TP_TPFSI_ACK );
+
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND1_SEL_A                 , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN             , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND1_SEL_B                 , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN             , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND2_SEL_A                 , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN             , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND2_SEL_B                 , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN             , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_C1_INAROW_MODE              , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1           , 33  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1           , 34  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1          , 35  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_UNUSED                      , 36  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_UNUSED_LEN                  , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_C2_INAROW_MODE              , 39  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2           , 40  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2           , 41  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2          , 42  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_UNUSED_2                    , 43  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_UNUSED_2_LEN                , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET          , 46  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_EXACT_TO_MODE               , 47  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1         , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_RESET_C3_ON_C0              , 49  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_SLOW_TO_MODE                , 50  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO        , 51  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_C1_COUNT_LT                 , 52  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN             , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_C2_COUNT_LT                 , 56  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN             , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_RESET_C3_SELECT             , 60  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN         , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A     , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A       , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN   , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B       , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN   , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_TO_CMP_LT                   , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN               , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_FORCE_TEST_MODE             , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_3_SP_COUNT_LT                 , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( PERV_1_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN             , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND1_SEL_A                 , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN             , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND1_SEL_B                 , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN             , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND2_SEL_A                 , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN             , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND2_SEL_B                 , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN             , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_C1_INAROW_MODE              , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1           , 33  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1           , 34  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1          , 35  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_UNUSED                      , 36  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_UNUSED_LEN                  , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_C2_INAROW_MODE              , 39  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2           , 40  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2           , 41  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2          , 42  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_UNUSED_2                    , 43  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_UNUSED_2_LEN                , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET          , 46  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_EXACT_TO_MODE               , 47  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1         , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_RESET_C3_ON_C0              , 49  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_SLOW_TO_MODE                , 50  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO        , 51  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_C1_COUNT_LT                 , 52  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN             , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_C2_COUNT_LT                 , 56  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN             , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_RESET_C3_SELECT             , 60  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN         , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A     , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A       , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN   , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B       , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN   , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_TO_CMP_LT                   , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN               , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_FORCE_TEST_MODE             , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_3_SP_COUNT_LT                 , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( PERV_1_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN             , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( PERV_1_DBG_MODE_REG_GLB_BRCST                           , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST  );
+REG64_FLD( PERV_1_DBG_MODE_REG_GLB_BRCST_LEN                       , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST_LEN );
+REG64_FLD( PERV_1_DBG_MODE_REG_TRACE_SEL                           , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SEL  );
+REG64_FLD( PERV_1_DBG_MODE_REG_TRIG_SEL                            , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG_SEL   );
+REG64_FLD( PERV_1_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION             , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_XSTOP_SELECTION );
+REG64_FLD( PERV_1_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION         , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_RECOV_ERR_SELECTION );
+REG64_FLD( PERV_1_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION            , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_SPATTN_SELECTION );
+REG64_FLD( PERV_1_DBG_MODE_REG_FREEZE_SEL                          , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_SEL );
+
+REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE    , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE );
+REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_IMM_FREEZE                  , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IMM_FREEZE );
+REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_STOP_ON_ERR                 , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_ERR );
+REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH          , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_BANK_ON_RUNN_MATCH );
+REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_FORCE_TEST                  , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST );
+REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_ACCUM_HIST                  , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACCUM_HIST );
+REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ            , 21  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FRZ_COUNT_ON_FRZ );
+
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_COND3_ENABLE               , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_COND3_ENABLE );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_COND3_ENABLE               , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_COND3_ENABLE );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST3_COND3_ENABLE               , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST3_COND3_ENABLE );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST4_COND3_ENABLE               , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST4_COND3_ENABLE );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE             , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_SLOW_LFSR_MODE );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE             , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_SLOW_LFSR_MODE );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE             , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST3_SLOW_LFSR_MODE );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE             , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST4_SLOW_LFSR_MODE );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL        , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN    , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL        , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN    , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL        , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN    , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL        , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN    , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL        , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN    , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL        , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN    , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP                 , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_STOP );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE               , 33  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_FREEZE );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL               , 34  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN           , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL               , 39  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN           , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL                   , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN               , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_ARM_SEL                          , 46  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL    );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_ARM_SEL_LEN                      , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL                  , 50  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN              , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL                  , 54  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL );
+REG64_FLD( PERV_1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN              , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL_LEN );
+
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO       , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN   , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO       , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN   , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO       , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN   , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO       , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN   , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO       , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN   , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO       , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN   , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN    , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_WAITN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN    , 25  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_WAITN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN    , 26  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN    , 27  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_WAITN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN    , 28  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_WAITN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN    , 29  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK     , 36  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_BANK );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK     , 37  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_BANK );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK     , 38  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK     , 39  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_BANK );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK     , 40  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_BANK );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK     , 41  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT          , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN      , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR    , 51  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT          , 52  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN      , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR    , 55  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR );
+
+REG64_FLD( PERV_DEVICE_ID_REG_SOCKET                               , 36  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SOCKET     );
+REG64_FLD( PERV_DEVICE_ID_REG_SOCKET_LEN                           , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SOCKET_LEN );
+REG64_FLD( PERV_DEVICE_ID_REG_CHIPPOS                              , 39  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_CHIPPOS    );
+
+REG32_FLD( PERV_FSISHIFT_DMA_ERROR_PTR_REGISTER_REG                , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG        );
+REG32_FLD( PERV_FSISHIFT_DMA_ERROR_PTR_REGISTER_REG_LEN            , 32  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG_LEN    );
+
+REG32_FLD( PERV_FSISHIFT_DMA_MODE_REGISTER_REG_ENABLE              , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG_ENABLE );
+REG32_FLD( PERV_FSISHIFT_DMA_MODE_REGISTER_REG_FIFO_SIZE_EQ_1      , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG_FIFO_SIZE_EQ_1 );
+REG32_FLD( PERV_FSISHIFT_DMA_MODE_REGISTER_REG_UNUSED              , 2   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG_UNUSED );
+REG32_FLD( PERV_FSISHIFT_DMA_MODE_REGISTER_REG_UNUSED_LEN          , 30  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG_UNUSED_LEN );
+
+REG32_FLD( PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_OPCODE          , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_OPCODE     );
+REG32_FLD( PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_OPCODE_LEN      , 8   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_OPCODE_LEN );
+REG32_FLD( PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_SIZE            , 8   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_SIZE       );
+REG32_FLD( PERV_FSISHIFT_DMA_OP_BLOCKSIZE_REGISTER_SIZE_LEN        , 24  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_SIZE_LEN   );
+
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER0_REGISTER_BUF0_REG_DATA0 , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_BUF0_REG_DATA0 );
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER0_REGISTER_BUF0_REG_DATA0_LEN , 32  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_BUF0_REG_DATA0_LEN );
+
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER1_REGISTER_BUF1_REG_DATA1 , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_BUF1_REG_DATA1 );
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_RCV_BUFFER1_REGISTER_BUF1_REG_DATA1_LEN , 32  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_BUF1_REG_DATA1_LEN );
+
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_SND_BUFFER0_REGISTER_BUF0_REG_DATA0 , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_BUF0_REG_DATA0 );
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_SND_BUFFER0_REGISTER_BUF0_REG_DATA0_LEN , 32  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_BUF0_REG_DATA0_LEN );
+
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_SND_BUFFER1_REGISTER_BUF1_REG_DATA0 , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_BUF1_REG_DATA0 );
+REG32_FLD( PERV_FSISHIFT_DMA_PIB_SND_BUFFER1_REGISTER_BUF1_REG_DATA0_LEN , 32  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_BUF1_REG_DATA0_LEN );
+
+REG32_FLD( PERV_FSISHIFT_DMA_REM_SIZE_REGISTER_REMAINING_WORDS     , 8   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REMAINING_WORDS );
+REG32_FLD( PERV_FSISHIFT_DMA_REM_SIZE_REGISTER_REMAINING_WORDS_LEN , 24  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REMAINING_WORDS_LEN );
+
+REG32_FLD( PERV_FSISHIFT_DMA_SCOM_CMD_REGISTER_REG                 , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG        );
+REG32_FLD( PERV_FSISHIFT_DMA_SCOM_CMD_REGISTER_REG_LEN             , 32  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG_LEN    );
+
+REG32_FLD( PERV_FSISHIFT_DMA_STAT_COMP_MASK_REGISTER_REG           , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG        );
+REG32_FLD( PERV_FSISHIFT_DMA_STAT_COMP_MASK_REGISTER_REG_LEN       , 32  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG_LEN    );
+
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_PERMISSION_TO_SEND_1 , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_PERMISSION_TO_SEND_1 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_ABORT_1            , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_ABORT_1 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_LBUS_SLAVE_1B_PENDING , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_LBUS_SLAVE_1B_PENDING );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_PIB_SLAVE_PENDING  , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_PIB_SLAVE_PENDING );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_UNUSED_27          , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_UNUSED_27 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_XDN_1              , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_XDN_1 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_XUP_1              , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_XUP_1 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_UNUSED_24          , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_UNUSED_24 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_HEADER_COUNT       , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_HEADER_COUNT );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_HEADER_COUNT_LEN   , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_HEADER_COUNT_LEN );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_DATA_COUNT         , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_DATA_COUNT );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_DATA_COUNT_LEN     , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_DATA_COUNT_LEN );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_HEADER_COUNT_1B    , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_HEADER_COUNT_1B );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_HEADER_COUNT_1B_LEN , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_HEADER_COUNT_1B_LEN );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_DATA_COUNT_1B      , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_DATA_COUNT_1B );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_1A_DSC1_DATA_COUNT_1B_LEN  , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC1_DATA_COUNT_1B_LEN );
+
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_PERMISSION_TO_SEND_2 , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_PERMISSION_TO_SEND_2 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_ABORT_2            , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_ABORT_2 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_LBUS_SLAVE_2B_PENDING , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_LBUS_SLAVE_2B_PENDING );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_PIB_SLAVE_PENDING  , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_PIB_SLAVE_PENDING );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_UNUSED_27          , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_UNUSED_27 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_XDN_2              , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_XDN_2 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_XUP_2              , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_XUP_2 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_UNUSED_24          , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_UNUSED_24 );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_HEADER_COUNT       , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_HEADER_COUNT );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_HEADER_COUNT_LEN   , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_HEADER_COUNT_LEN );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_DATA_COUNT         , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_DATA_COUNT );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_DATA_COUNT_LEN     , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_DATA_COUNT_LEN );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_HEADER_COUNT_2B    , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_HEADER_COUNT_2B );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_HEADER_COUNT_2B_LEN , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_HEADER_COUNT_2B_LEN );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_DATA_COUNT_2B      , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_DATA_COUNT_2B );
+REG64_FLD( PERV_DOORBELL_STATUS_CONTROL_2A_DSC2_DATA_COUNT_2B_LEN  , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DSC2_DATA_COUNT_2B_LEN );
+
+REG64_FLD( PERV_1_DTS_RESULT0_0_RESULT                             , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_0_RESULT   );
+REG64_FLD( PERV_1_DTS_RESULT0_0_RESULT_LEN                         , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_0_RESULT_LEN );
+REG64_FLD( PERV_1_DTS_RESULT0_1_RESULT                             , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_RESULT   );
+REG64_FLD( PERV_1_DTS_RESULT0_1_RESULT_LEN                         , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_RESULT_LEN );
+
+REG64_FLD( PERV_1_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE           , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMESTAMP_COUNTER_VALUE );
+REG64_FLD( PERV_1_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN       , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN );
+REG64_FLD( PERV_1_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR    , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR );
+REG64_FLD( PERV_1_DTS_TRC_RESULT_1                                 , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_1          );
+REG64_FLD( PERV_1_DTS_TRC_RESULT_1_LEN                             , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_LEN      );
+
+REG64_FLD( PERV_ERROR_REG_TIMEOUT_ACTIVE                           , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_ACTIVE );
+REG64_FLD( PERV_ERROR_REG_PARITY_ERR                               , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ERR );
+REG64_FLD( PERV_ERROR_REG_BEAT_NUM_ERR                             , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_BEAT_NUM_ERR );
+REG64_FLD( PERV_ERROR_REG_BEAT_REC_ERR                             , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_BEAT_REC_ERR );
+REG64_FLD( PERV_ERROR_REG_RECEIVED                                 , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_RECEIVED   );
+REG64_FLD( PERV_ERROR_REG_RX_PCB_DATA_P_ERR                        , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_RX_PCB_DATA_P_ERR );
+REG64_FLD( PERV_ERROR_REG_PIB_ADDR_P_ERR                           , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PIB_ADDR_P_ERR );
+REG64_FLD( PERV_ERROR_REG_PIB_DATA_P_ERR                           , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PIB_DATA_P_ERR );
+
+REG64_FLD( PERV_1_ERROR_STATUS_ERRORS                              , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRORS     );
+REG64_FLD( PERV_1_ERROR_STATUS_ERRORS_LEN                          , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRORS_LEN );
+
+REG64_FLD( PERV_1_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK         , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_THERM_MODEREG_PARITY_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK       , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_SKITTER_MODEREG_PARITY_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK      , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_SKITTER_FORCEREG_PARITY_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK     , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_SCAN_INIT_VERSION_PARITY_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK          , 21  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_VOLT_MODEREG_PARITY_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_COUNT_STATE_MASK                  , 23  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_STATE_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_RUN_STATE_MASK                    , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUN_STATE_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_THRES_STATE_MASK                  , 25  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_THRES_STATE_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_OVERFLOW_MASK                     , 26  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_OVERFLOW_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_SHIFTER_PARITY_MASK               , 27  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_SHIFTER_PARITY_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_SHIFTER_VALID_MASK                , 28  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_SHIFTER_VALID_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_TIMEOUT_MASK                      , 29  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMEOUT_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_F_SKITTER_READ_MASK               , 30  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_F_SKITTER_READ_MASK );
+REG64_FLD( PERV_1_ERR_STATUS_REG_PCB_MASK                          , 31  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCB_MASK   );
+
+REG32_FLD( PERV_FSII2C_EXTENDED_STATUS_A_MSM_CURR_STATE_0          , 11  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_MSM_CURR_STATE_0 );
+REG32_FLD( PERV_FSII2C_EXTENDED_STATUS_A_MSM_CURR_STATE_0_LEN      , 5   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_MSM_CURR_STATE_0_LEN );
+REG32_FLD( PERV_FSII2C_EXTENDED_STATUS_A_SELF_BUSY_0               , 25  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_SELF_BUSY_0 );
+
+REG32_FLD( PERV_FSII2C_FIFO1_REGISTER_READ_A_FIFO_BITS_READ0_0     , 0   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_0 );
+REG32_FLD( PERV_FSII2C_FIFO1_REGISTER_READ_A_FIFO_BITS_READ0_0_LEN , 8   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_FIFO_BITS_READ0_0_LEN );
+
+REG64_FLD( PERV_FIRST_ERR_REG_TIMEOUT_ACTIVE                       , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_ACTIVE );
+REG64_FLD( PERV_FIRST_ERR_REG_PARITY                               , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PARITY     );
+REG64_FLD( PERV_FIRST_ERR_REG_BEAT_NUM                             , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_BEAT_NUM   );
+REG64_FLD( PERV_FIRST_ERR_REG_BEAT_REC                             , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_BEAT_REC   );
+REG64_FLD( PERV_FIRST_ERR_REG_RECEIVED_ERROR                       , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_RECEIVED_ERROR );
+REG64_FLD( PERV_FIRST_ERR_REG_RX_PCB_DATA_P                        , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_RX_PCB_DATA_P );
+REG64_FLD( PERV_FIRST_ERR_REG_PIB_ADDR_P                           , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PIB_ADDR_P );
+REG64_FLD( PERV_FIRST_ERR_REG_PIB_DATA_P                           , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PIB_DATA_P );
+
+REG64_FLD( PERV_FIRST_REPLY_REG_REGISTER                           , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_REGISTER   );
+REG64_FLD( PERV_FIRST_REPLY_REG_REGISTER_LEN                       , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_REGISTER_LEN );
+
+REG64_FLD( PERV_1_FIR_MASK_IN0                                     , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( PERV_1_FIR_MASK_IN1                                     , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN1        );
+REG64_FLD( PERV_1_FIR_MASK_IN2                                     , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN2        );
+REG64_FLD( PERV_1_FIR_MASK_IN3                                     , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN3        );
+REG64_FLD( PERV_1_FIR_MASK_IN4                                     , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( PERV_1_FIR_MASK_IN5                                     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( PERV_1_FIR_MASK_IN6                                     , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN6        );
+REG64_FLD( PERV_1_FIR_MASK_IN7                                     , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN7        );
+REG64_FLD( PERV_1_FIR_MASK_IN8                                     , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN8        );
+REG64_FLD( PERV_1_FIR_MASK_IN9                                     , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN9        );
+REG64_FLD( PERV_1_FIR_MASK_IN10                                    , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN10       );
+REG64_FLD( PERV_1_FIR_MASK_IN11                                    , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN11       );
+REG64_FLD( PERV_1_FIR_MASK_IN12                                    , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN12       );
+REG64_FLD( PERV_1_FIR_MASK_IN13                                    , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN13       );
+REG64_FLD( PERV_1_FIR_MASK_IN14                                    , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN14       );
+REG64_FLD( PERV_1_FIR_MASK_IN15                                    , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN15       );
+REG64_FLD( PERV_1_FIR_MASK_IN16                                    , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN16       );
+REG64_FLD( PERV_1_FIR_MASK_IN17                                    , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN17       );
+REG64_FLD( PERV_1_FIR_MASK_IN18                                    , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN18       );
+REG64_FLD( PERV_1_FIR_MASK_IN19                                    , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN19       );
+REG64_FLD( PERV_1_FIR_MASK_IN20                                    , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN20       );
+REG64_FLD( PERV_1_FIR_MASK_IN21                                    , 21  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN21       );
+REG64_FLD( PERV_1_FIR_MASK_IN21_LEN                                , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN21_LEN   );
+REG64_FLD( PERV_1_FIR_MASK_IN26                                    , 26  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN26       );
+
+REG64_FLD( PERV_1_FMU_MODE_REG_TOD_CNTR_REF                        , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TOD_CNTR_REF );
+REG64_FLD( PERV_1_FMU_MODE_REG_TOD_CNTR_REF_LEN                    , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TOD_CNTR_REF_LEN );
+REG64_FLD( PERV_1_FMU_MODE_REG_POWER_UP_CNTR_REF                   , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_POWER_UP_CNTR_REF );
+REG64_FLD( PERV_1_FMU_MODE_REG_POWER_UP_CNTR_REF_LEN               , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_POWER_UP_CNTR_REF_LEN );
+
+REG64_FLD( PERV_1_FMU_OSC_CNTR1_REG_RESULT_AVAILABLE               , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESULT_AVAILABLE );
+REG64_FLD( PERV_1_FMU_OSC_CNTR1_REG_PULSE1_CNTR                    , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PULSE1_CNTR );
+REG64_FLD( PERV_1_FMU_OSC_CNTR1_REG_PULSE1_CNTR_LEN                , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PULSE1_CNTR_LEN );
+
+REG64_FLD( PERV_1_FMU_OSC_CNTR2_REG_RESULT_AVAILABLE               , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESULT_AVAILABLE );
+REG64_FLD( PERV_1_FMU_OSC_CNTR2_REG_PULSE2_CNTR                    , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PULSE2_CNTR );
+REG64_FLD( PERV_1_FMU_OSC_CNTR2_REG_PULSE2_CNTR_LEN                , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PULSE2_CNTR_LEN );
+
+REG64_FLD( PERV_1_FMU_PULSE_GEN_REG_INT_ENA                        , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_ENA    );
+REG64_FLD( PERV_1_FMU_PULSE_GEN_REG_INT_CNTR_REF                   , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_CNTR_REF );
+REG64_FLD( PERV_1_FMU_PULSE_GEN_REG_INT_CNTR_REF_LEN               , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_CNTR_REF_LEN );
+
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SBE    , 6   , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_DNFIFO_REQ_RESET_FR_SBE );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SP     , 7   , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_DNFIFO_REQ_RESET_FR_SP );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_DEQUEUED_EOT_FLAG   , 8   , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_DNFIFO_DEQUEUED_EOT_FLAG );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_FULL           , 10  , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_DNFIFO_FIFO_FULL );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EMPTY          , 11  , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_DNFIFO_FIFO_EMPTY );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT    , 12  , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_DNFIFO_FIFO_ENTRY_COUNT );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT_LEN , 4   , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_DNFIFO_FIFO_ENTRY_COUNT_LEN );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS    , 16  , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_DNFIFO_FIFO_VALID_FLAGS );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS_LEN , 8   , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_DNFIFO_FIFO_VALID_FLAGS_LEN );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS      , 24  , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_DNFIFO_FIFO_EOT_FLAGS );
+REG64_FLD( PERV_FSB_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS_LEN  , 8   , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_DNFIFO_FIFO_EOT_FLAGS_LEN );
+
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_REQ_RESET_FR_SP              , 6   , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_REQ_RESET_FR_SP );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_REQ_RESET_FR_SBE             , 7   , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_REQ_RESET_FR_SBE );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_DEQUEUED_EOT_FLAG            , 8   , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_DEQUEUED_EOT_FLAG );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_FULL                    , 10  , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_FIFO_FULL  );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_EMPTY                   , 11  , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_FIFO_EMPTY );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT             , 12  , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_FIFO_ENTRY_COUNT );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT_LEN         , 4   , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_FIFO_ENTRY_COUNT_LEN );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS             , 16  , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_FIFO_VALID_FLAGS );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS_LEN         , 8   , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_FIFO_VALID_FLAGS_LEN );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS               , 24  , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_FIFO_EOT_FLAGS );
+REG64_FLD( PERV_FSB_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS_LEN           , 8   , SH_UNT_PERV_FSB , SH_ACS_FSI_BYTE ,
+           SH_FLD_FIFO_EOT_FLAGS_LEN );
+
+REG32_FLD( PERV_FSISCRPD1_FSI_SCRATCH_PAD1                         , 0   , SH_UNT_PERV     , SH_ACS_FSI_BYTE ,
+           SH_FLD_FSI_SCRATCH_PAD1 );
+REG32_FLD( PERV_FSISCRPD1_FSI_SCRATCH_PAD1_LEN                     , 32  , SH_UNT_PERV     , SH_ACS_FSI_BYTE ,
+           SH_FLD_FSI_SCRATCH_PAD1_LEN );
+
+REG32_FLD( PERV_FSISCRPD2_FSI_SCRATCH_PAD2                         , 0   , SH_UNT_PERV     , SH_ACS_FSI_BYTE ,
+           SH_FLD_FSI_SCRATCH_PAD2 );
+REG32_FLD( PERV_FSISCRPD2_FSI_SCRATCH_PAD2_LEN                     , 32  , SH_UNT_PERV     , SH_ACS_FSI_BYTE ,
+           SH_FLD_FSI_SCRATCH_PAD2_LEN );
+
+REG32_FLD( PERV_FSISCRPD3_FSI_SCRATCH_PAD3                         , 0   , SH_UNT_PERV     , SH_ACS_FSI_BYTE ,
+           SH_FLD_FSI_SCRATCH_PAD3 );
+REG32_FLD( PERV_FSISCRPD3_FSI_SCRATCH_PAD3_LEN                     , 32  , SH_UNT_PERV     , SH_ACS_FSI_BYTE ,
+           SH_FLD_FSI_SCRATCH_PAD3_LEN );
+
+REG32_FLD( PERV_FSI_A_LLMOD_ASYNC_MODE                             , 31  , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_ASYNC_MODE );
+
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_ENABLE                      , 0   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_1_ENABLE                    , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_1_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_2_ENABLE                    , 2   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_2_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_3_ENABLE                    , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_3_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_4_ENABLE                    , 4   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_4_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_5_ENABLE                    , 5   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_5_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_6_ENABLE                    , 6   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_6_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_0_MENP0_PORT_7_ENABLE                    , 7   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_7_ENABLE );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_ENABLE             , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_1_ENABLE           , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_1_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_2_ENABLE           , 2   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_2_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_3_ENABLE           , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_3_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_4_ENABLE           , 4   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_4_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_5_ENABLE           , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_5_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_6_ENABLE           , 6   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_6_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MENP0_PORT_7_ENABLE           , 7   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_7_ENABLE );
+
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FIRST_ERROR                     , 0   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_FIRST_ERROR );
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FIRST_ERROR_LEN                 , 4   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_FIRST_ERROR_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST         , 17  , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_FAILING_OPB_MASTER_FRST );
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN     , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_FAILING_OPB_MASTER_FRST_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_ACTUAL_ERROR                    , 20  , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_ACTUAL_ERROR );
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_ACTUAL_ERROR_LEN                , 4   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT          , 29  , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_FAILING_OPB_MASTER_ACT );
+REG32_FLD( PERV_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN      , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_FAILING_OPB_MASTER_ACT_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FIRST_ERROR            , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_FIRST_ERROR );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FIRST_ERROR_LEN        , 4   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_FIRST_ERROR_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST , 17  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_FAILING_OPB_MASTER_FRST );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_FAILING_OPB_MASTER_FRST_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_ACTUAL_ERROR           , 20  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_ACTUAL_ERROR );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_ACTUAL_ERROR_LEN       , 4   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT , 29  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_FAILING_OPB_MASTER_ACT );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_FAILING_OPB_MASTER_ACT_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_ENABLE_IPOLL_AND_DMA             , 0   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_ENABLE_IPOLL_AND_DMA );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_ENABLE_HW_ERROR_RECOVERY         , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_ENABLE_HW_ERROR_RECOVERY );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_ENABLE_RELATIVE_ADDRESS_CMDS     , 2   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_ENABLE_PARITY_CHECK              , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_ENABLE_PARITY_CHECK );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION             , 4   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_CLOCK_RATE_SELECTION );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_LEN         , 10  , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_CLOCK_RATE_SELECTION_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_1           , 14  , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_CLOCK_RATE_SELECTION_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_1_LEN       , 10  , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_CLOCK_RATE_SELECTION_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_CLOCK_DIV_4                      , 25  , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_CLOCK_DIV_4 );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_TIMEOUT_SEL                      , 26  , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_TIMEOUT_SEL );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_TIMEOUT_SEL_LEN                  , 2   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_TIMEOUT_SEL_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_RECEIVER_MODE                    , 29  , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_RECEIVER_MODE );
+REG32_FLD( PERV_FSI_A_MST_0_MMODE_RECEIVER_MODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_RECEIVER_MODE_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_ENABLE_IPOLL_AND_DMA    , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_ENABLE_IPOLL_AND_DMA );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_ENABLE_HW_ERROR_RECOVERY , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_ENABLE_HW_ERROR_RECOVERY );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_ENABLE_RELATIVE_ADDRESS_CMDS , 2   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_ENABLE_PARITY_CHECK     , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_ENABLE_PARITY_CHECK );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION    , 4   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_CLOCK_RATE_SELECTION );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_LEN , 10  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_CLOCK_RATE_SELECTION_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_1  , 14  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_CLOCK_RATE_SELECTION_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_CLOCK_RATE_SELECTION_1_LEN , 10  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_CLOCK_RATE_SELECTION_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_CLOCK_DIV_4             , 25  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_CLOCK_DIV_4 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_TIMEOUT_SEL             , 26  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_TIMEOUT_SEL );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_TIMEOUT_SEL_LEN         , 2   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_TIMEOUT_SEL_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_RECEIVER_MODE           , 29  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_RECEIVER_MODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MMODE_RECEIVER_MODE_LEN       , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_RECEIVER_MODE_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MRESP1_PORT_GENERAL_RESET_1            , 0   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_GENERAL_RESET_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MRESP1_PORT_ERROR_RESET_1              , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_ERROR_RESET_1 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP1_PORT_GENERAL_RESET_1   , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_GENERAL_RESET_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP1_PORT_ERROR_RESET_1     , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ERROR_RESET_1 );
+
+REG32_FLD( PERV_FSI_A_MST_0_MRESP2_PORT_GENERAL_RESET_2            , 0   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_GENERAL_RESET_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MRESP2_PORT_ERROR_RESET_2              , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_ERROR_RESET_2 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP2_PORT_GENERAL_RESET_2   , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_GENERAL_RESET_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP2_PORT_ERROR_RESET_2     , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ERROR_RESET_2 );
+
+REG32_FLD( PERV_FSI_A_MST_0_MRESP3_PORT_GENERAL_RESET_3            , 0   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_GENERAL_RESET_3 );
+REG32_FLD( PERV_FSI_A_MST_0_MRESP3_PORT_ERROR_RESET_3              , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_ERROR_RESET_3 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP3_PORT_GENERAL_RESET_3   , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_GENERAL_RESET_3 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP3_PORT_ERROR_RESET_3     , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ERROR_RESET_3 );
+
+REG32_FLD( PERV_FSI_A_MST_0_MRESP4_PORT_GENERAL_RESET_4            , 0   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_GENERAL_RESET_4 );
+REG32_FLD( PERV_FSI_A_MST_0_MRESP4_PORT_ERROR_RESET_4              , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_ERROR_RESET_4 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP4_PORT_GENERAL_RESET_4   , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_GENERAL_RESET_4 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP4_PORT_ERROR_RESET_4     , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ERROR_RESET_4 );
+
+REG32_FLD( PERV_FSI_A_MST_0_MRESP5_PORT_GENERAL_RESET_5            , 0   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_GENERAL_RESET_5 );
+REG32_FLD( PERV_FSI_A_MST_0_MRESP5_PORT_ERROR_RESET_5              , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_ERROR_RESET_5 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP5_PORT_GENERAL_RESET_5   , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_GENERAL_RESET_5 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP5_PORT_ERROR_RESET_5     , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ERROR_RESET_5 );
+
+REG32_FLD( PERV_FSI_A_MST_0_MRESP6_PORT_GENERAL_RESET_6            , 0   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_GENERAL_RESET_6 );
+REG32_FLD( PERV_FSI_A_MST_0_MRESP6_PORT_ERROR_RESET_6              , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_ERROR_RESET_6 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP6_PORT_GENERAL_RESET_6   , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_GENERAL_RESET_6 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP6_PORT_ERROR_RESET_6     , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ERROR_RESET_6 );
+
+REG32_FLD( PERV_FSI_A_MST_0_MRESP7_PORT_GENERAL_RESET_7            , 0   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_GENERAL_RESET_7 );
+REG32_FLD( PERV_FSI_A_MST_0_MRESP7_PORT_ERROR_RESET_7              , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT_ERROR_RESET_7 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP7_PORT_GENERAL_RESET_7   , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_GENERAL_RESET_7 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MRESP7_PORT_ERROR_RESET_7     , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ERROR_RESET_7 );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT0_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT0_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT0_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT0_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT0_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT0_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT0_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT0_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT0_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT0_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT0_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT0_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT1_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT1_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT1_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT1_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT1_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT1_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT1_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT1_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT1_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT1_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT1_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT1_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT2_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT2_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT2_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT2_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT2_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT2_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT2_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT2_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT2_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT2_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT2_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT2_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT3_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT3_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT3_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT3_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT3_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT3_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT3_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT3_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT3_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT3_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT3_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT3_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT4_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT4_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT4_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT4_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT4_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT4_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT4_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT4_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT4_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT4_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT4_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT4_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT5_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT5_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT5_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT5_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT5_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT5_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT5_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT5_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT5_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT5_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT5_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT5_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT6_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT6_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT6_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT6_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT6_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT6_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT6_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT6_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT6_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT6_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT6_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT6_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT7_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT7_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT7_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT7_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT7_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_PORT7_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT7_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT7_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT7_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT7_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT7_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_A_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT7_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_0_ENABLE                    , 0   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_0_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_ENABLE                      , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_2_ENABLE                    , 2   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_2_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_3_ENABLE                    , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_3_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_4_ENABLE                    , 4   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_4_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_5_ENABLE                    , 5   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_5_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_6_ENABLE                    , 6   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_6_ENABLE );
+REG32_FLD( PERV_FSI_A_MST_1_MENP0_PORT_7_ENABLE                    , 7   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_7_ENABLE );
+
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FIRST_ERROR                     , 0   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_FIRST_ERROR );
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FIRST_ERROR_LEN                 , 4   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_FIRST_ERROR_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_FRST         , 17  , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_FAILING_OPB_MASTER_FRST );
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_FRST_LEN     , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_FAILING_OPB_MASTER_FRST_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_ACTUAL_ERROR                    , 20  , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_ACTUAL_ERROR );
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_ACTUAL_ERROR_LEN                , 4   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_ACT          , 29  , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_FAILING_OPB_MASTER_ACT );
+REG32_FLD( PERV_FSI_A_MST_1_MESRB0_FAILING_OPB_MASTER_ACT_LEN      , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_FAILING_OPB_MASTER_ACT_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_ENABLE_IPOLL_AND_DMA             , 0   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_ENABLE_IPOLL_AND_DMA );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_ENABLE_HW_ERROR_RECOVERY         , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_ENABLE_HW_ERROR_RECOVERY );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_ENABLE_RELATIVE_ADDRESS_CMDS     , 2   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_ENABLE_PARITY_CHECK              , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_ENABLE_PARITY_CHECK );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_CLOCK_RATE_SELECTION_0           , 4   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_CLOCK_RATE_SELECTION_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_CLOCK_RATE_SELECTION_0_LEN       , 10  , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_CLOCK_RATE_SELECTION_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_CLOCK_RATE_SELECTION             , 14  , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_CLOCK_RATE_SELECTION );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_CLOCK_RATE_SELECTION_LEN         , 10  , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_CLOCK_RATE_SELECTION_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_CLOCK_DIV_4                      , 25  , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_CLOCK_DIV_4 );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_TIMEOUT_SEL                      , 26  , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_TIMEOUT_SEL );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_TIMEOUT_SEL_LEN                  , 2   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_TIMEOUT_SEL_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_RECEIVER_MODE                    , 29  , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_RECEIVER_MODE );
+REG32_FLD( PERV_FSI_A_MST_1_MMODE_RECEIVER_MODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_RECEIVER_MODE_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MRESP1_PORT_GENERAL_RESET              , 0   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_GENERAL_RESET );
+REG32_FLD( PERV_FSI_A_MST_1_MRESP1_PORT_ERROR_RESET                , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ERROR_RESET );
+
+REG32_FLD( PERV_FSI_A_MST_1_MRESP2_PORT_GENERAL_RESET_2            , 0   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_GENERAL_RESET_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MRESP2_PORT_ERROR_RESET_2              , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ERROR_RESET_2 );
+
+REG32_FLD( PERV_FSI_A_MST_1_MRESP3_PORT_GENERAL_RESET_3            , 0   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_GENERAL_RESET_3 );
+REG32_FLD( PERV_FSI_A_MST_1_MRESP3_PORT_ERROR_RESET_3              , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ERROR_RESET_3 );
+
+REG32_FLD( PERV_FSI_A_MST_1_MRESP4_PORT_GENERAL_RESET_4            , 0   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_GENERAL_RESET_4 );
+REG32_FLD( PERV_FSI_A_MST_1_MRESP4_PORT_ERROR_RESET_4              , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ERROR_RESET_4 );
+
+REG32_FLD( PERV_FSI_A_MST_1_MRESP5_PORT_GENERAL_RESET_5            , 0   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_GENERAL_RESET_5 );
+REG32_FLD( PERV_FSI_A_MST_1_MRESP5_PORT_ERROR_RESET_5              , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ERROR_RESET_5 );
+
+REG32_FLD( PERV_FSI_A_MST_1_MRESP6_PORT_GENERAL_RESET_6            , 0   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_GENERAL_RESET_6 );
+REG32_FLD( PERV_FSI_A_MST_1_MRESP6_PORT_ERROR_RESET_6              , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ERROR_RESET_6 );
+
+REG32_FLD( PERV_FSI_A_MST_1_MRESP7_PORT_GENERAL_RESET_7            , 0   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_GENERAL_RESET_7 );
+REG32_FLD( PERV_FSI_A_MST_1_MRESP7_PORT_ERROR_RESET_7              , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT_ERROR_RESET_7 );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_0              , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT0_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_0_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT0_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE                , 5   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT0_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT0_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT0_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP0_PORT0_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT0_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_0              , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT1_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_0_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT1_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE                , 5   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT1_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT1_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT1_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP1_PORT1_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT1_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_0              , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT2_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_0_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT2_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE                , 5   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT2_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT2_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT2_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP2_PORT2_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT2_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_0              , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT3_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_0_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT3_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE                , 5   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT3_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT3_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT3_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP3_PORT3_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT3_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_0              , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT4_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_0_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT4_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE                , 5   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT4_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT4_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT4_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP4_PORT4_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT4_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_0              , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT5_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_0_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT5_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE                , 5   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT5_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT5_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT5_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP5_PORT5_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT5_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_0              , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT6_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_0_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT6_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE                , 5   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT6_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT6_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT6_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP6_PORT6_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT6_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_0              , 1   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT7_ERROR_CODE_0 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_0_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT7_ERROR_CODE_0_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE                , 5   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT7_ERROR_CODE );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT7_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT7_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_A_MST_1_MSTAP7_PORT7_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOMFSI0 ,
+           SH_FLD_PORT7_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_A_SMODE_WARM_START_COMPLETED                   , 0   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_WARM_START_COMPLETED );
+REG32_FLD( PERV_FSI_A_SMODE_ENABLE_AUX_PORT_UNUSED                 , 1   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_ENABLE_AUX_PORT_UNUSED );
+REG32_FLD( PERV_FSI_A_SMODE_ENABLE_HW_ERROR_RECOVERY               , 2   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_ENABLE_HW_ERROR_RECOVERY );
+REG32_FLD( PERV_FSI_A_SMODE_OWN_ID_THIS_SLAVE                      , 6   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_OWN_ID_THIS_SLAVE );
+REG32_FLD( PERV_FSI_A_SMODE_OWN_ID_THIS_SLAVE_LEN                  , 2   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_OWN_ID_THIS_SLAVE_LEN );
+REG32_FLD( PERV_FSI_A_SMODE_ECHO_DELAY_CYCLES                      , 8   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_ECHO_DELAY_CYCLES );
+REG32_FLD( PERV_FSI_A_SMODE_ECHO_DELAY_CYCLES_LEN                  , 4   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_ECHO_DELAY_CYCLES_LEN );
+REG32_FLD( PERV_FSI_A_SMODE_SEND_DELAY_CYCLES                      , 12  , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_SEND_DELAY_CYCLES );
+REG32_FLD( PERV_FSI_A_SMODE_SEND_DELAY_CYCLES_LEN                  , 4   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_SEND_DELAY_CYCLES_LEN );
+REG32_FLD( PERV_FSI_A_SMODE_LBUS_CLOCK_DIVIDER                     , 20  , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_LBUS_CLOCK_DIVIDER );
+REG32_FLD( PERV_FSI_A_SMODE_LBUS_CLOCK_DIVIDER_LEN                 , 4   , SH_UNT_PERV     , SH_ACS_FSI0     ,
+           SH_FLD_LBUS_CLOCK_DIVIDER_LEN );
+
+REG32_FLD( PERV_FSI_B_LLMOD_ASYNC_MODE                             , 31  , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_ASYNC_MODE );
+
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_ENABLE                      , 0   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_ENABLE );
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_1_ENABLE                    , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_1_ENABLE );
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_2_ENABLE                    , 2   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_2_ENABLE );
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_3_ENABLE                    , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_3_ENABLE );
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_4_ENABLE                    , 4   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_4_ENABLE );
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_5_ENABLE                    , 5   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_5_ENABLE );
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_6_ENABLE                    , 6   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_6_ENABLE );
+REG32_FLD( PERV_FSI_B_MST_0_MENP0_PORT_7_ENABLE                    , 7   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_7_ENABLE );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_ENABLE             , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_1_ENABLE           , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_1_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_2_ENABLE           , 2   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_2_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_3_ENABLE           , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_3_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_4_ENABLE           , 4   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_4_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_5_ENABLE           , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_5_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_6_ENABLE           , 6   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_6_ENABLE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MENP0_PORT_7_ENABLE           , 7   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_7_ENABLE );
+
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FIRST_ERROR                     , 0   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_FIRST_ERROR );
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FIRST_ERROR_LEN                 , 4   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_FIRST_ERROR_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST         , 17  , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_FAILING_OPB_MASTER_FRST );
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN     , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_FAILING_OPB_MASTER_FRST_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_ACTUAL_ERROR                    , 20  , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_ACTUAL_ERROR );
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_ACTUAL_ERROR_LEN                , 4   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT          , 29  , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_FAILING_OPB_MASTER_ACT );
+REG32_FLD( PERV_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN      , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_FAILING_OPB_MASTER_ACT_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FIRST_ERROR            , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_FIRST_ERROR );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FIRST_ERROR_LEN        , 4   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_FIRST_ERROR_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST , 17  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_FAILING_OPB_MASTER_FRST );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_FRST_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_FAILING_OPB_MASTER_FRST_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_ACTUAL_ERROR           , 20  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_ACTUAL_ERROR );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_ACTUAL_ERROR_LEN       , 4   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT , 29  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_FAILING_OPB_MASTER_ACT );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MESRB0_FAILING_OPB_MASTER_ACT_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_FAILING_OPB_MASTER_ACT_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_ENABLE_IPOLL_AND_DMA             , 0   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_ENABLE_IPOLL_AND_DMA );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_ENABLE_HW_ERROR_RECOVERY         , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_ENABLE_HW_ERROR_RECOVERY );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_ENABLE_RELATIVE_ADDRESS_CMDS     , 2   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_ENABLE_PARITY_CHECK              , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_ENABLE_PARITY_CHECK );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION             , 4   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_CLOCK_RATE_SELECTION );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_LEN         , 10  , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_CLOCK_RATE_SELECTION_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_1           , 14  , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_CLOCK_RATE_SELECTION_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_1_LEN       , 10  , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_CLOCK_RATE_SELECTION_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_CLOCK_DIV_4                      , 25  , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_CLOCK_DIV_4 );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_TIMEOUT_SEL                      , 26  , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_TIMEOUT_SEL );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_TIMEOUT_SEL_LEN                  , 2   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_TIMEOUT_SEL_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_RECEIVER_MODE                    , 29  , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_RECEIVER_MODE );
+REG32_FLD( PERV_FSI_B_MST_0_MMODE_RECEIVER_MODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_RECEIVER_MODE_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_ENABLE_IPOLL_AND_DMA    , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_ENABLE_IPOLL_AND_DMA );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_ENABLE_HW_ERROR_RECOVERY , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_ENABLE_HW_ERROR_RECOVERY );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_ENABLE_RELATIVE_ADDRESS_CMDS , 2   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_ENABLE_PARITY_CHECK     , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_ENABLE_PARITY_CHECK );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION    , 4   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_CLOCK_RATE_SELECTION );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_LEN , 10  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_CLOCK_RATE_SELECTION_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_1  , 14  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_CLOCK_RATE_SELECTION_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_CLOCK_RATE_SELECTION_1_LEN , 10  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_CLOCK_RATE_SELECTION_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_CLOCK_DIV_4             , 25  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_CLOCK_DIV_4 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_TIMEOUT_SEL             , 26  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_TIMEOUT_SEL );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_TIMEOUT_SEL_LEN         , 2   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_TIMEOUT_SEL_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_RECEIVER_MODE           , 29  , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_RECEIVER_MODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MMODE_RECEIVER_MODE_LEN       , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_RECEIVER_MODE_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MRESP1_PORT_GENERAL_RESET_1            , 0   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_GENERAL_RESET_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MRESP1_PORT_ERROR_RESET_1              , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_ERROR_RESET_1 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP1_PORT_GENERAL_RESET_1   , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_GENERAL_RESET_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP1_PORT_ERROR_RESET_1     , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_ERROR_RESET_1 );
+
+REG32_FLD( PERV_FSI_B_MST_0_MRESP2_PORT_GENERAL_RESET_2            , 0   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_GENERAL_RESET_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MRESP2_PORT_ERROR_RESET_2              , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_ERROR_RESET_2 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP2_PORT_GENERAL_RESET_2   , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_GENERAL_RESET_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP2_PORT_ERROR_RESET_2     , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_ERROR_RESET_2 );
+
+REG32_FLD( PERV_FSI_B_MST_0_MRESP3_PORT_GENERAL_RESET_3            , 0   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_GENERAL_RESET_3 );
+REG32_FLD( PERV_FSI_B_MST_0_MRESP3_PORT_ERROR_RESET_3              , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_ERROR_RESET_3 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP3_PORT_GENERAL_RESET_3   , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_GENERAL_RESET_3 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP3_PORT_ERROR_RESET_3     , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_ERROR_RESET_3 );
+
+REG32_FLD( PERV_FSI_B_MST_0_MRESP4_PORT_GENERAL_RESET_4            , 0   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_GENERAL_RESET_4 );
+REG32_FLD( PERV_FSI_B_MST_0_MRESP4_PORT_ERROR_RESET_4              , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_ERROR_RESET_4 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP4_PORT_GENERAL_RESET_4   , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_GENERAL_RESET_4 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP4_PORT_ERROR_RESET_4     , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_ERROR_RESET_4 );
+
+REG32_FLD( PERV_FSI_B_MST_0_MRESP5_PORT_GENERAL_RESET_5            , 0   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_GENERAL_RESET_5 );
+REG32_FLD( PERV_FSI_B_MST_0_MRESP5_PORT_ERROR_RESET_5              , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_ERROR_RESET_5 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP5_PORT_GENERAL_RESET_5   , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_GENERAL_RESET_5 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP5_PORT_ERROR_RESET_5     , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_ERROR_RESET_5 );
+
+REG32_FLD( PERV_FSI_B_MST_0_MRESP6_PORT_GENERAL_RESET_6            , 0   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_GENERAL_RESET_6 );
+REG32_FLD( PERV_FSI_B_MST_0_MRESP6_PORT_ERROR_RESET_6              , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_ERROR_RESET_6 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP6_PORT_GENERAL_RESET_6   , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_GENERAL_RESET_6 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP6_PORT_ERROR_RESET_6     , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_ERROR_RESET_6 );
+
+REG32_FLD( PERV_FSI_B_MST_0_MRESP7_PORT_GENERAL_RESET_7            , 0   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_GENERAL_RESET_7 );
+REG32_FLD( PERV_FSI_B_MST_0_MRESP7_PORT_ERROR_RESET_7              , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT_ERROR_RESET_7 );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP7_PORT_GENERAL_RESET_7   , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_GENERAL_RESET_7 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MRESP7_PORT_ERROR_RESET_7     , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT_ERROR_RESET_7 );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT0_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT0_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT0_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT0_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT0_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT0_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT0_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT0_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT0_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT0_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT0_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP0_PORT0_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT0_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT1_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT1_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT1_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT1_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT1_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT1_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT1_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT1_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT1_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT1_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT1_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP1_PORT1_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT1_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT2_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT2_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT2_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT2_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT2_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT2_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT2_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT2_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT2_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT2_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT2_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP2_PORT2_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT2_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT3_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT3_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT3_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT3_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT3_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT3_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT3_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT3_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT3_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT3_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT3_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP3_PORT3_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT3_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT4_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT4_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT4_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT4_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT4_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT4_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT4_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT4_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT4_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT4_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT4_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP4_PORT4_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT4_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT5_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT5_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT5_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT5_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT5_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT5_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT5_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT5_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT5_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT5_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT5_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP5_PORT5_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT5_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT6_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT6_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT6_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT6_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT6_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT6_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT6_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT6_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT6_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT6_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT6_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP6_PORT6_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT6_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE                , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT7_ERROR_CODE );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT7_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_1              , 5   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT7_ERROR_CODE_1 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_1_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT7_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2              , 9   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT7_ERROR_CODE_2 );
+REG32_FLD( PERV_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN          , 3   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_PORT7_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE       , 1   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT7_ERROR_CODE );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_LEN   , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT7_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_1     , 5   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT7_ERROR_CODE_1 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_1_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT7_ERROR_CODE_1_LEN );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2     , 9   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT7_ERROR_CODE_2 );
+REG32_FLD( PERV_FSISHIFT_FSI_B_MST_0_MSTAP7_PORT7_ERROR_CODE_2_LEN , 3   , SH_UNT_PERV_FSISHIFT, SH_ACS_SCOMFSI1 ,
+           SH_FLD_PORT7_ERROR_CODE_2_LEN );
+
+REG32_FLD( PERV_FSI_B_SMODE_WARM_START_COMPLETED                   , 0   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_WARM_START_COMPLETED );
+REG32_FLD( PERV_FSI_B_SMODE_ENABLE_AUX_PORT_UNUSED                 , 1   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_ENABLE_AUX_PORT_UNUSED );
+REG32_FLD( PERV_FSI_B_SMODE_ENABLE_HW_ERROR_RECOVERY               , 2   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_ENABLE_HW_ERROR_RECOVERY );
+REG32_FLD( PERV_FSI_B_SMODE_OWN_ID_THIS_SLAVE                      , 6   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_OWN_ID_THIS_SLAVE );
+REG32_FLD( PERV_FSI_B_SMODE_OWN_ID_THIS_SLAVE_LEN                  , 2   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_OWN_ID_THIS_SLAVE_LEN );
+REG32_FLD( PERV_FSI_B_SMODE_ECHO_DELAY_CYCLES                      , 8   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_ECHO_DELAY_CYCLES );
+REG32_FLD( PERV_FSI_B_SMODE_ECHO_DELAY_CYCLES_LEN                  , 4   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_ECHO_DELAY_CYCLES_LEN );
+REG32_FLD( PERV_FSI_B_SMODE_SEND_DELAY_CYCLES                      , 12  , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_SEND_DELAY_CYCLES );
+REG32_FLD( PERV_FSI_B_SMODE_SEND_DELAY_CYCLES_LEN                  , 4   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_SEND_DELAY_CYCLES_LEN );
+REG32_FLD( PERV_FSI_B_SMODE_LBUS_CLOCK_DIVIDER                     , 20  , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_LBUS_CLOCK_DIVIDER );
+REG32_FLD( PERV_FSI_B_SMODE_LBUS_CLOCK_DIVIDER_LEN                 , 4   , SH_UNT_PERV     , SH_ACS_FSI1     ,
+           SH_FLD_LBUS_CLOCK_DIVIDER_LEN );
+
+REG64_FLD( PERV_GPWRP_MAGIC_COOKIE                                 , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MAGIC_COOKIE );
+REG64_FLD( PERV_GPWRP_MAGIC_COOKIE_LEN                             , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MAGIC_COOKIE_LEN );
+REG64_FLD( PERV_GPWRP_EN_OR_DIS_WRITE_PROTECTION                   , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_EN_OR_DIS_WRITE_PROTECTION );
+REG64_FLD( PERV_GPWRP_EN_OR_DIS_WRITE_PROTECTION_LEN               , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_EN_OR_DIS_WRITE_PROTECTION_LEN );
+
+REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0                 , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN0 );
+REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1                 , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN1 );
+REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2                 , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN2 );
+REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3                 , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN3 );
+REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4                 , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN4 );
+REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5                 , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN5 );
+REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6                 , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN6 );
+REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7                 , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN7 );
+REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8                 , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN8 );
+REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9                 , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN9 );
+REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10                , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN10 );
+REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11                , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN11 );
+
+REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0                 , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN0 );
+REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1                 , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN1 );
+REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2                 , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN2 );
+REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3                 , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN3 );
+REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4                 , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN4 );
+REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5                 , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN5 );
+REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6                 , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN6 );
+REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7                 , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN7 );
+REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8                 , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN8 );
+REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9                 , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN9 );
+REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10                , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN10 );
+REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11                , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN11 );
+
+REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0                 , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN0 );
+REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1                 , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN1 );
+REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2                 , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN2 );
+REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3                 , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN3 );
+REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4                 , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN4 );
+REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5                 , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN5 );
+REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6                 , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN6 );
+REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7                 , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN7 );
+REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8                 , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN8 );
+REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9                 , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN9 );
+REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10                , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN10 );
+REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11                , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN11 );
+
+REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN0                        , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN0  );
+REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN1                        , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN1  );
+REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN2                        , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN2  );
+REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN3                        , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN3  );
+REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN4                        , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN4  );
+REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN5                        , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN5  );
+REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN6                        , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN6  );
+REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN7                        , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN7  );
+REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN8                        , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN8  );
+REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN9                        , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN9  );
+REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN10                       , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN10 );
+REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN11                       , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN11 );
+
+REG64_FLD( PERV_1_HANG_PULSE_0_REG_0                               , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_0          );
+REG64_FLD( PERV_1_HANG_PULSE_0_REG_0_LEN                           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_LEN      );
+REG64_FLD( PERV_1_HANG_PULSE_0_REG_SUPPRESS                        , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( PERV_1_HANG_PULSE_1_REG_1                               , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_1          );
+REG64_FLD( PERV_1_HANG_PULSE_1_REG_1_LEN                           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_LEN      );
+REG64_FLD( PERV_1_HANG_PULSE_1_REG_SUPPRESS                        , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( PERV_1_HANG_PULSE_2_REG_2                               , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_2          );
+REG64_FLD( PERV_1_HANG_PULSE_2_REG_2_LEN                           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_2_LEN      );
+REG64_FLD( PERV_1_HANG_PULSE_2_REG_SUPPRESS                        , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( PERV_1_HANG_PULSE_3_REG_3                               , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_3          );
+REG64_FLD( PERV_1_HANG_PULSE_3_REG_3_LEN                           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_3_LEN      );
+REG64_FLD( PERV_1_HANG_PULSE_3_REG_SUPPRESS                        , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( PERV_1_HANG_PULSE_4_REG_4                               , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_4          );
+REG64_FLD( PERV_1_HANG_PULSE_4_REG_4_LEN                           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LEN      );
+REG64_FLD( PERV_1_HANG_PULSE_4_REG_SUPPRESS                        , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( PERV_1_HANG_PULSE_5_REG_5                               , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_5          );
+REG64_FLD( PERV_1_HANG_PULSE_5_REG_5_LEN                           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_5_LEN      );
+REG64_FLD( PERV_1_HANG_PULSE_5_REG_SUPPRESS                        , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( PERV_1_HANG_PULSE_6_REG_6                               , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_6          );
+REG64_FLD( PERV_1_HANG_PULSE_6_REG_6_LEN                           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_6_LEN      );
+REG64_FLD( PERV_1_HANG_PULSE_6_REG_SUPPRESS                        , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( PERV_1_HEARTBEAT_REG_DEAD                               , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DEAD       );
+
+REG64_FLD( PERV_1_HOSTATTN_IN0                                     , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN0        );
+REG64_FLD( PERV_1_HOSTATTN_IN1                                     , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN1        );
+REG64_FLD( PERV_1_HOSTATTN_IN2                                     , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN2        );
+REG64_FLD( PERV_1_HOSTATTN_IN3                                     , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN3        );
+REG64_FLD( PERV_1_HOSTATTN_IN4                                     , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN4        );
+REG64_FLD( PERV_1_HOSTATTN_IN5                                     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN5        );
+REG64_FLD( PERV_1_HOSTATTN_IN6                                     , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN6        );
+REG64_FLD( PERV_1_HOSTATTN_IN7                                     , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN7        );
+REG64_FLD( PERV_1_HOSTATTN_IN8                                     , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN8        );
+REG64_FLD( PERV_1_HOSTATTN_IN9                                     , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN9        );
+REG64_FLD( PERV_1_HOSTATTN_IN10                                    , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN10       );
+REG64_FLD( PERV_1_HOSTATTN_IN11                                    , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN11       );
+REG64_FLD( PERV_1_HOSTATTN_IN12                                    , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN12       );
+REG64_FLD( PERV_1_HOSTATTN_IN13                                    , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN13       );
+REG64_FLD( PERV_1_HOSTATTN_IN14                                    , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN14       );
+REG64_FLD( PERV_1_HOSTATTN_IN15                                    , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN15       );
+REG64_FLD( PERV_1_HOSTATTN_IN16                                    , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN16       );
+REG64_FLD( PERV_1_HOSTATTN_IN17                                    , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN17       );
+REG64_FLD( PERV_1_HOSTATTN_IN18                                    , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN18       );
+REG64_FLD( PERV_1_HOSTATTN_IN19                                    , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN19       );
+REG64_FLD( PERV_1_HOSTATTN_IN20                                    , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN20       );
+REG64_FLD( PERV_1_HOSTATTN_IN21                                    , 21  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN21       );
+REG64_FLD( PERV_1_HOSTATTN_IN22                                    , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN22       );
+
+REG64_FLD( PERV_1_HOSTATTN_MASK_IN                                 , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( PERV_1_HOSTATTN_MASK_IN_LEN                             , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( PERV_HOST_MASK_REG_IPOLL_0                              , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_IPOLL_0    );
+REG64_FLD( PERV_HOST_MASK_REG_IPOLL_1                              , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_IPOLL_1    );
+REG64_FLD( PERV_HOST_MASK_REG_IPOLL_2                              , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_IPOLL_2    );
+REG64_FLD( PERV_HOST_MASK_REG_IPOLL_3                              , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_IPOLL_3    );
+REG64_FLD( PERV_HOST_MASK_REG_IPOLL_4                              , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_IPOLL_4    );
+REG64_FLD( PERV_HOST_MASK_REG_IPOLL_5                              , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_IPOLL_5    );
+REG64_FLD( PERV_HOST_MASK_REG_ERROR_0                              , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_0    );
+REG64_FLD( PERV_HOST_MASK_REG_ERROR_1                              , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_1    );
+REG64_FLD( PERV_HOST_MASK_REG_ERROR_2                              , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_2    );
+REG64_FLD( PERV_HOST_MASK_REG_ERROR_3                              , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_3    );
+REG64_FLD( PERV_HOST_MASK_REG_ERROR_4                              , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_4    );
+REG64_FLD( PERV_HOST_MASK_REG_ERROR_5                              , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_5    );
+
+REG64_FLD( PERV_IGNORE_PAR_REG_PARITY                              , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PARITY     );
+REG64_FLD( PERV_IGNORE_PAR_REG_DISABLE_ECC_CORRECTION              , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_ECC_CORRECTION );
+REG64_FLD( PERV_IGNORE_PAR_REG_ECC_S_BIT_ERROR                     , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_ECC_S_BIT_ERROR );
+REG64_FLD( PERV_IGNORE_PAR_REG_CHKSW_AR012                         , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_CHKSW_AR012 );
+
+REG64_FLD( PERV_1_INJECT_REG_THERM_TRIP                            , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_THERM_TRIP );
+REG64_FLD( PERV_1_INJECT_REG_THERM_TRIP_LEN                        , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_THERM_TRIP_LEN );
+REG64_FLD( PERV_1_INJECT_REG_THERM_MODE                            , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_THERM_MODE );
+REG64_FLD( PERV_1_INJECT_REG_THERM_MODE_LEN                        , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_THERM_MODE_LEN );
+
+REG32_FLD( PERV_FSI2PIB_INTERRUPT_STATUS_REG                       , 0   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_STATUS_REG );
+REG32_FLD( PERV_FSI2PIB_INTERRUPT_STATUS_REG_LEN                   , 32  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_STATUS_REG_LEN );
+
+REG64_FLD( PERV_INTERRUPT1_REG_INTERRUPT1                          , 0   , SH_UNT_PERV     , SH_ACS_SCOM2_AND,
+           SH_FLD_INTERRUPT1 );
+REG64_FLD( PERV_INTERRUPT1_REG_INTERRUPT1_LEN                      , 56  , SH_UNT_PERV     , SH_ACS_SCOM2_AND,
+           SH_FLD_INTERRUPT1_LEN );
+
+REG64_FLD( PERV_INTERRUPT2_REG_INTERRUPT2                          , 0   , SH_UNT_PERV     , SH_ACS_SCOM2_AND,
+           SH_FLD_INTERRUPT2 );
+REG64_FLD( PERV_INTERRUPT2_REG_INTERRUPT2_LEN                      , 56  , SH_UNT_PERV     , SH_ACS_SCOM2_AND,
+           SH_FLD_INTERRUPT2_LEN );
+
+REG64_FLD( PERV_INTERRUPT3_REG_INTERRUPT3                          , 0   , SH_UNT_PERV     , SH_ACS_SCOM2_AND,
+           SH_FLD_INTERRUPT3 );
+REG64_FLD( PERV_INTERRUPT3_REG_INTERRUPT3_LEN                      , 56  , SH_UNT_PERV     , SH_ACS_SCOM2_AND,
+           SH_FLD_INTERRUPT3_LEN );
+
+REG64_FLD( PERV_INTERRUPT4_REG_INTERRUPT4                          , 0   , SH_UNT_PERV     , SH_ACS_SCOM2_AND,
+           SH_FLD_INTERRUPT4 );
+REG64_FLD( PERV_INTERRUPT4_REG_INTERRUPT4_LEN                      , 56  , SH_UNT_PERV     , SH_ACS_SCOM2_AND,
+           SH_FLD_INTERRUPT4_LEN );
+
+REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_INVALID_CMD_0              , 16  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_INVALID_CMD_0 );
+REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_LBUS_PARITY_ERROR_0        , 17  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERROR_0 );
+REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_BE_OV_ERROR_0              , 18  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_BE_OV_ERROR_0 );
+REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_BE_ACC_ERROR_0             , 19  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_BE_ACC_ERROR_0 );
+REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_ARBITRATION_LOST_ERROR_0   , 20  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_ARBITRATION_LOST_ERROR_0 );
+REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_NACK_RECEIVED_ERROR_0      , 21  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_NACK_RECEIVED_ERROR_0 );
+REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_DATA_REQUEST_0             , 22  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_DATA_REQUEST_0 );
+REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_STOP_ERROR_0               , 24  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_STOP_ERROR_0 );
+
+REG64_FLD( PERV_INTERRUPT_CONF_REG_UNUSED0                         , 0   , SH_UNT_PERV     , SH_ACS_SCOM2_WAND,
+           SH_FLD_UNUSED0    );
+REG64_FLD( PERV_INTERRUPT_CONF_REG_SEL0                            , 1   , SH_UNT_PERV     , SH_ACS_SCOM2_WAND,
+           SH_FLD_SEL0       );
+REG64_FLD( PERV_INTERRUPT_CONF_REG_SEL0_LEN                        , 3   , SH_UNT_PERV     , SH_ACS_SCOM2_WAND,
+           SH_FLD_SEL0_LEN   );
+REG64_FLD( PERV_INTERRUPT_CONF_REG_UNUSED4                         , 4   , SH_UNT_PERV     , SH_ACS_SCOM2_WAND,
+           SH_FLD_UNUSED4    );
+REG64_FLD( PERV_INTERRUPT_CONF_REG_SEL1                            , 5   , SH_UNT_PERV     , SH_ACS_SCOM2_WAND,
+           SH_FLD_SEL1       );
+REG64_FLD( PERV_INTERRUPT_CONF_REG_SEL1_LEN                        , 3   , SH_UNT_PERV     , SH_ACS_SCOM2_WAND,
+           SH_FLD_SEL1_LEN   );
+REG64_FLD( PERV_INTERRUPT_CONF_REG_GP                              , 8   , SH_UNT_PERV     , SH_ACS_SCOM2_WAND,
+           SH_FLD_GP         );
+REG64_FLD( PERV_INTERRUPT_CONF_REG_CC                              , 9   , SH_UNT_PERV     , SH_ACS_SCOM2_WAND,
+           SH_FLD_CC         );
+REG64_FLD( PERV_INTERRUPT_CONF_REG_UNUSED2                         , 10  , SH_UNT_PERV     , SH_ACS_SCOM2_WAND,
+           SH_FLD_UNUSED2    );
+REG64_FLD( PERV_INTERRUPT_CONF_REG_UNUSED3                         , 11  , SH_UNT_PERV     , SH_ACS_SCOM2_WAND,
+           SH_FLD_UNUSED3    );
+
+REG64_FLD( PERV_INTERRUPT_HOLD_REG_HOLD                            , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_HOLD       );
+REG64_FLD( PERV_INTERRUPT_HOLD_REG_HOLD_LEN                        , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_LEN   );
+
+REG32_FLD( PERV_FSII2C_INTERRUPT_MASK_REGISTER_A_INT_0             , 16  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM2_AND,
+           SH_FLD_INT_0      );
+REG32_FLD( PERV_FSII2C_INTERRUPT_MASK_REGISTER_A_INT_0_LEN         , 16  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM2_AND,
+           SH_FLD_INT_0_LEN  );
+
+REG32_FLD( PERV_FSII2C_INTERRUPT_MASK_REGISTER_READ_A_INT_0        , 16  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_INT_0      );
+REG32_FLD( PERV_FSII2C_INTERRUPT_MASK_REGISTER_READ_A_INT_0_LEN    , 16  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_INT_0_LEN  );
+
+REG64_FLD( PERV_INTERRUPT_TYPE_MASK_REG_GP                         , 0   , SH_UNT_PERV     , SH_ACS_SCOM2_WAND,
+           SH_FLD_GP         );
+REG64_FLD( PERV_INTERRUPT_TYPE_MASK_REG_CC                         , 1   , SH_UNT_PERV     , SH_ACS_SCOM2_WAND,
+           SH_FLD_CC         );
+REG64_FLD( PERV_INTERRUPT_TYPE_MASK_REG_UNUSED2                    , 2   , SH_UNT_PERV     , SH_ACS_SCOM2_WAND,
+           SH_FLD_UNUSED2    );
+REG64_FLD( PERV_INTERRUPT_TYPE_MASK_REG_UNUSED3                    , 3   , SH_UNT_PERV     , SH_ACS_SCOM2_WAND,
+           SH_FLD_UNUSED3    );
+
+REG64_FLD( PERV_INTERRUPT_TYPE_REG_ATTENTION                       , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_ATTENTION  );
+REG64_FLD( PERV_INTERRUPT_TYPE_REG_RECOVERABLE_ERROR               , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_RECOVERABLE_ERROR );
+REG64_FLD( PERV_INTERRUPT_TYPE_REG_CHECKSTOP                       , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_CHECKSTOP  );
+
+REG64_FLD( PERV_IODA_TCD_IDIAL_VLD                                 , 0   , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_VLD  );
+REG64_FLD( PERV_IODA_TCD_IDIAL_RSVD0                               , 1   , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RSVD0 );
+REG64_FLD( PERV_IODA_TCD_IDIAL_RSVD0_LEN                           , 5   , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RSVD0_LEN );
+REG64_FLD( PERV_IODA_TCD_IDIAL_PC                                  , 6   , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_PC   );
+REG64_FLD( PERV_IODA_TCD_IDIAL_PC_LEN                              , 2   , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_PC_LEN );
+REG64_FLD( PERV_IODA_TCD_IDIAL_PE                                  , 8   , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_PE   );
+REG64_FLD( PERV_IODA_TCD_IDIAL_PE_LEN                              , 4   , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_PE_LEN );
+REG64_FLD( PERV_IODA_TCD_IDIAL_EA                                  , 12  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_EA   );
+REG64_FLD( PERV_IODA_TCD_IDIAL_EA_LEN                              , 37  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_EA_LEN );
+REG64_FLD( PERV_IODA_TCD_IDIAL_RSVD1                               , 49  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RSVD1 );
+REG64_FLD( PERV_IODA_TCD_IDIAL_RSVD1_LEN                           , 15  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RSVD1_LEN );
+
+REG64_FLD( PERV_IODA_TDR_IDIAL_RA                                  , 0   , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RA   );
+REG64_FLD( PERV_IODA_TDR_IDIAL_RA_LEN                              , 39  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RA_LEN );
+REG64_FLD( PERV_IODA_TDR_IDIAL_RSVD0                               , 39  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RSVD0 );
+REG64_FLD( PERV_IODA_TDR_IDIAL_RSVD0_LEN                           , 2   , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RSVD0_LEN );
+REG64_FLD( PERV_IODA_TDR_IDIAL_PAR                                 , 41  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_PAR  );
+REG64_FLD( PERV_IODA_TDR_IDIAL_PAR_LEN                             , 5   , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_PAR_LEN );
+
+REG64_FLD( PERV_IODA_TDR_MEM_IDIAL_RSVD0                           , 0   , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RSVD0 );
+REG64_FLD( PERV_IODA_TDR_MEM_IDIAL_RSVD0_LEN                       , 13  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RSVD0_LEN );
+REG64_FLD( PERV_IODA_TDR_MEM_IDIAL_RA                              , 13  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RA   );
+REG64_FLD( PERV_IODA_TDR_MEM_IDIAL_RA_LEN                          , 39  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RA_LEN );
+REG64_FLD( PERV_IODA_TDR_MEM_IDIAL_RSVD1                           , 52  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RSVD1 );
+REG64_FLD( PERV_IODA_TDR_MEM_IDIAL_RSVD1_LEN                       , 10  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RSVD1_LEN );
+REG64_FLD( PERV_IODA_TDR_MEM_IDIAL_PC                              , 62  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_PC   );
+REG64_FLD( PERV_IODA_TDR_MEM_IDIAL_PC_LEN                          , 2   , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_PC_LEN );
+
+REG64_FLD( PERV_FSB_IODA_TVT_TVT0_XLAT_ADDR                        , 0   , SH_UNT_PERV_FSB , SH_ACS_IODA     ,
+           SH_FLD_TVT0_XLAT_ADDR );
+REG64_FLD( PERV_FSB_IODA_TVT_TVT0_XLAT_ADDR_LEN                    , 48  , SH_UNT_PERV_FSB , SH_ACS_IODA     ,
+           SH_FLD_TVT0_XLAT_ADDR_LEN );
+REG64_FLD( PERV_FSB_IODA_TVT_TVT0_TABLE_LEVEL                      , 48  , SH_UNT_PERV_FSB , SH_ACS_IODA     ,
+           SH_FLD_TVT0_TABLE_LEVEL );
+REG64_FLD( PERV_FSB_IODA_TVT_TVT0_TABLE_LEVEL_LEN                  , 3   , SH_UNT_PERV_FSB , SH_ACS_IODA     ,
+           SH_FLD_TVT0_TABLE_LEVEL_LEN );
+REG64_FLD( PERV_FSB_IODA_TVT_TVT0_TABLE_SIZE                       , 51  , SH_UNT_PERV_FSB , SH_ACS_IODA     ,
+           SH_FLD_TVT0_TABLE_SIZE );
+REG64_FLD( PERV_FSB_IODA_TVT_TVT0_TABLE_SIZE_LEN                   , 5   , SH_UNT_PERV_FSB , SH_ACS_IODA     ,
+           SH_FLD_TVT0_TABLE_SIZE_LEN );
+REG64_FLD( PERV_FSB_IODA_TVT_TVT0_SPARE                            , 56  , SH_UNT_PERV_FSB , SH_ACS_IODA     ,
+           SH_FLD_TVT0_SPARE );
+REG64_FLD( PERV_FSB_IODA_TVT_TVT0_SPARE_LEN                        , 3   , SH_UNT_PERV_FSB , SH_ACS_IODA     ,
+           SH_FLD_TVT0_SPARE_LEN );
+REG64_FLD( PERV_FSB_IODA_TVT_TVT0_PAGE_SIZE                        , 59  , SH_UNT_PERV_FSB , SH_ACS_IODA     ,
+           SH_FLD_TVT0_PAGE_SIZE );
+REG64_FLD( PERV_FSB_IODA_TVT_TVT0_PAGE_SIZE_LEN                    , 5   , SH_UNT_PERV_FSB , SH_ACS_IODA     ,
+           SH_FLD_TVT0_PAGE_SIZE_LEN );
+
+REG64_FLD( PERV_IODA_XLT_EA_IDIAL_EA                               , 0   , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_EA   );
+REG64_FLD( PERV_IODA_XLT_EA_IDIAL_EA_LEN                           , 37  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_EA_LEN );
+REG64_FLD( PERV_IODA_XLT_EA_IDIAL_PE                               , 37  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_PE   );
+REG64_FLD( PERV_IODA_XLT_EA_IDIAL_PE_LEN                           , 4   , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_PE_LEN );
+REG64_FLD( PERV_IODA_XLT_EA_IDIAL_RNW                              , 41  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RNW  );
+REG64_FLD( PERV_IODA_XLT_EA_IDIAL_TAG                              , 42  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_TAG  );
+REG64_FLD( PERV_IODA_XLT_EA_IDIAL_TAG_LEN                          , 8   , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_TAG_LEN );
+REG64_FLD( PERV_IODA_XLT_EA_IDIAL_RSVD0                            , 50  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RSVD0 );
+REG64_FLD( PERV_IODA_XLT_EA_IDIAL_RSVD0_LEN                        , 14  , SH_UNT_PERV     , SH_ACS_IODA     ,
+           SH_FLD_IDIAL_RSVD0_LEN );
+
+REG64_FLD( PERV_1_LOCAL_FIR_IN0                                    , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN0        );
+REG64_FLD( PERV_1_LOCAL_FIR_IN1                                    , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN1        );
+REG64_FLD( PERV_1_LOCAL_FIR_IN2                                    , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN2        );
+REG64_FLD( PERV_1_LOCAL_FIR_IN3                                    , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN3        );
+REG64_FLD( PERV_1_LOCAL_FIR_IN4                                    , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN4        );
+REG64_FLD( PERV_1_LOCAL_FIR_IN5                                    , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN5        );
+REG64_FLD( PERV_1_LOCAL_FIR_IN6                                    , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN6        );
+REG64_FLD( PERV_1_LOCAL_FIR_IN7                                    , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN7        );
+REG64_FLD( PERV_1_LOCAL_FIR_IN8                                    , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN8        );
+REG64_FLD( PERV_1_LOCAL_FIR_IN9                                    , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN9        );
+REG64_FLD( PERV_1_LOCAL_FIR_IN10                                   , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN10       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN11                                   , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN11       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN12                                   , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN12       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN13                                   , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN13       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN14                                   , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN14       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN15                                   , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN15       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN16                                   , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN16       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN17                                   , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN17       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN18                                   , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN18       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN19                                   , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN19       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN20                                   , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN20       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN21                                   , 21  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN21       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN22                                   , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN22       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN23                                   , 23  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN23       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN24                                   , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN24       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN25                                   , 25  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN25       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN26                                   , 26  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN26       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN27                                   , 27  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN27       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN28                                   , 28  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN28       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN29                                   , 29  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN29       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN30                                   , 30  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN30       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN31                                   , 31  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN31       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN32                                   , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN32       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN33                                   , 33  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN33       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN34                                   , 34  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN34       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN35                                   , 35  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN35       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN36                                   , 36  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN36       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN37                                   , 37  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN37       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN38                                   , 38  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN38       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN39                                   , 39  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN39       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN40                                   , 40  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN40       );
+REG64_FLD( PERV_1_LOCAL_FIR_IN41                                   , 41  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN41       );
+
+REG64_FLD( PERV_1_LOCAL_FIR_ACTION0_IN                             , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( PERV_1_LOCAL_FIR_ACTION0_IN_LEN                         , 42  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( PERV_1_LOCAL_FIR_ACTION1_IN                             , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( PERV_1_LOCAL_FIR_ACTION1_IN_LEN                         , 42  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( PERV_1_LOCAL_FIR_MASK_LFIR_IN                           , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LFIR_IN    );
+REG64_FLD( PERV_1_LOCAL_FIR_MASK_LFIR_IN_LEN                       , 42  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LFIR_IN_LEN );
+
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN0                              , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN0        );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN1                              , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN1        );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN2                              , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN2        );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN3                              , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN3        );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN4                              , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN4        );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN5                              , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN5        );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN6                              , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN6        );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN7                              , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN7        );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN8                              , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN8        );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN9                              , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN9        );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN10                             , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN10       );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN11                             , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN11       );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN12                             , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN12       );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN13                             , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN13       );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN14                             , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN14       );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN15                             , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN15       );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN16                             , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN16       );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN17                             , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN17       );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN18                             , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN18       );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN19                             , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN19       );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN20                             , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN20       );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN21                             , 21  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN21       );
+REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN22                             , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN22       );
+
+REG64_FLD( PERV_1_LOCAL_XSTOP_MASK_IN                              , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( PERV_1_LOCAL_XSTOP_MASK_IN_LEN                          , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_0_A_M1HC0A                , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M1HC0A     );
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_0_A_M1HC0A_LEN            , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M1HC0A_LEN );
+
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_0_B_M1HC0B                , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_M1HC0B     );
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_0_B_M1HC0B_LEN            , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_M1HC0B_LEN );
+
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_1_A_M1HC1A                , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M1HC1A     );
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_1_A_M1HC1A_LEN            , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M1HC1A_LEN );
+
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_1_B_M1HC1B                , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_M1HC1B     );
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_1_B_M1HC1B_LEN            , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_M1HC1B_LEN );
+
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_2_A_M1HC2A                , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M1HC2A     );
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_2_A_M1HC2A_LEN            , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M1HC2A_LEN );
+
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_2_B_M1HC2B                , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_M1HC2B     );
+REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_2_B_M1HC2B_LEN            , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_M1HC2B_LEN );
+
+REG64_FLD( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_M1SASIM1_ENABLE_PIB_ERROR , 29  , SH_UNT_PERV     ,
+           SH_ACS_SCOM1_CLEAR, SH_FLD_M1SASIM1_ENABLE_PIB_ERROR );
+REG64_FLD( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_M1SASIM1_ENABLE_XUP , 30  , SH_UNT_PERV     ,
+           SH_ACS_SCOM1_CLEAR, SH_FLD_M1SASIM1_ENABLE_XUP );
+REG64_FLD( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_M1SASIM1_ENABLE_PIB_PENDING , 31  , SH_UNT_PERV     ,
+           SH_ACS_SCOM1_CLEAR, SH_FLD_M1SASIM1_ENABLE_PIB_PENDING );
+
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_0_A_M2HC0A                , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M2HC0A     );
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_0_A_M2HC0A_LEN            , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M2HC0A_LEN );
+
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_0_B_M2HC0B                , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_M2HC0B     );
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_0_B_M2HC0B_LEN            , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_M2HC0B_LEN );
+
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_1_A_M2HC1A                , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M2HC1A     );
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_1_A_M2HC1A_LEN            , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M2HC1A_LEN );
+
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_1_B_M2HC1B                , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_M2HC1B     );
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_1_B_M2HC1B_LEN            , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_M2HC1B_LEN );
+
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_2_A_M2HC2A                , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M2HC2A     );
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_2_A_M2HC2A_LEN            , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M2HC2A_LEN );
+
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_2_B_M2HC2B                , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_M2HC2B     );
+REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_2_B_M2HC2B_LEN            , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_M2HC2B_LEN );
+
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_31_28 , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MSADES_UNUSED_31_28 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_31_28_LEN , 4   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSADES_UNUSED_31_28_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ILLEGAL_OPERATION_ATTEMPTED_1 , 4   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_WRITE_FULL_PIB_1 , 5   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSADES_WRITE_FULL_PIB_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_READ_EMPTY_PIB_1 , 6   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSADES_READ_EMPTY_PIB_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_LBUS_B_RAM_PARITY_DETECTED_1 , 7   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_1 , 8   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_1_LEN , 7   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_CLEAR_1 , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MSADES_CLEAR_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_15_12 , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MSADES_UNUSED_15_12 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_15_12_LEN , 4   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSADES_UNUSED_15_12_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ILLEGAL_OPERATION_ATTEMPTED_2 , 20  , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_WRITE_FULL_PIB_2 , 21  , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSADES_WRITE_FULL_PIB_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_READ_EMPTY_PIB_2 , 22  , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSADES_READ_EMPTY_PIB_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_LBUS_B_RAM_PARITY_DETECTED_2 , 23  , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_2 , 24  , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_2_LEN , 7   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_CLEAR_2 , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MSADES_CLEAR_2 );
+
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_UNUSED_31_11 , 11  , SH_UNT_PERV     , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_MSADI_UNUSED_31_11 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_UNUSED_31_11_LEN , 10  , SH_UNT_PERV     , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_MSADI_UNUSED_31_11_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_PIB_ERROR_2 , 21  , SH_UNT_PERV     , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_MSADI_PIB_ERROR_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_XUP_2     , 22  , SH_UNT_PERV     , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_MSADI_XUP_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_PIB_PENDING_2 , 23  , SH_UNT_PERV     , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_MSADI_PIB_PENDING_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_UNUSED_7_3 , 24  , SH_UNT_PERV     , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_MSADI_UNUSED_7_3 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_UNUSED_7_3_LEN , 5   , SH_UNT_PERV     , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_MSADI_UNUSED_7_3_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_PIB_ERROR_1 , 29  , SH_UNT_PERV     , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_MSADI_PIB_ERROR_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_XUP_1     , 30  , SH_UNT_PERV     , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_MSADI_XUP_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_PIB_PENDING_1 , 31  , SH_UNT_PERV     , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_MSADI_PIB_PENDING_1 );
+
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_31_28 , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MSBDES_UNUSED_31_28 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_31_28_LEN , 4   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSBDES_UNUSED_31_28_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_1 , 4   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_WRITE_FULL_PIB_A_1 , 5   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSBDES_WRITE_FULL_PIB_A_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_READ_EMPTY_PIB_A_1 , 6   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSBDES_READ_EMPTY_PIB_A_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_PIB_A_RAM_PARITY_DETECTED_1 , 7   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_1 , 8   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_1_LEN , 7   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_CLEAR_1 , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MSBDES_CLEAR_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_15_12 , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MSBDES_UNUSED_15_12 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_15_12_LEN , 4   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSBDES_UNUSED_15_12_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_2 , 20  , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_WRITE_FULL_PIB_A_2 , 21  , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSBDES_WRITE_FULL_PIB_A_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_READ_EMPTY_PIB_A_2 , 22  , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSBDES_READ_EMPTY_PIB_A_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_PIB_A_RAM_PARITY_DETECTED_2 , 23  , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_2 , 24  , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_2_LEN , 7   , SH_UNT_PERV     ,
+           SH_ACS_SCOM     , SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2_LEN );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_CLEAR_2 , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MSBDES_CLEAR_2 );
+
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_ERROR_2 , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MSBDI_LBUS_ERROR_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_ERROR_1 , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MSBDI_LBUS_ERROR_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_XDN_2     , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MSBDI_XDN_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_XDN_1     , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MSBDI_XDN_1 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_PENDING_2 , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MSBDI_LBUS_PENDING_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_PENDING_1 , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MSBDI_LBUS_PENDING_1 );
+
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_LBUS_PENDING , 24  , SH_UNT_PERV     ,
+           SH_ACS_SCOM_RO  , SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_LBUS_PENDING_2 , 25  , SH_UNT_PERV     ,
+           SH_ACS_SCOM_RO  , SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_XDN , 26  , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_MSBDIM1_ENABLE_XDN );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_XDN_2 , 27  , SH_UNT_PERV     ,
+           SH_ACS_SCOM_RO  , SH_FLD_MSBDIM1_ENABLE_XDN_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_LBUS_ERROR , 28  , SH_UNT_PERV     ,
+           SH_ACS_SCOM_RO  , SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_LBUS_ERROR_2 , 29  , SH_UNT_PERV     ,
+           SH_ACS_SCOM_RO  , SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR_2 );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_ABORT , 30  , SH_UNT_PERV     ,
+           SH_ACS_SCOM_RO  , SH_FLD_MSBDIM1_ENABLE_ABORT );
+REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_ABORT_2 , 31  , SH_UNT_PERV     ,
+           SH_ACS_SCOM_RO  , SH_FLD_MSBDIM1_ENABLE_ABORT_2 );
+
+REG64_FLD( PERV_MCAST_COMP_MASK_REG_MULTICAST_COMPARE_REGISTER     , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST_COMPARE_REGISTER );
+REG64_FLD( PERV_MCAST_COMP_MASK_REG_MULTICAST_COMPARE_REGISTER_LEN , 64  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST_COMPARE_REGISTER_LEN );
+
+REG64_FLD( PERV_MCAST_COMP_REG_MULTICAST_COMPARE_REGISTER          , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST_COMPARE_REGISTER );
+REG64_FLD( PERV_MCAST_COMP_REG_MULTICAST_COMPARE_REGISTER_LEN      , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST_COMPARE_REGISTER_LEN );
+
+REG64_FLD( PERV_MCAST_COMP_VAL_REG_MULTICAST_COMPARE_VALUE_REGISTER , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER );
+REG64_FLD( PERV_MCAST_COMP_VAL_REG_MULTICAST_COMPARE_VALUE_REGISTER_LEN , 64  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER_LEN );
+
+REG64_FLD( PERV_MCAST_GRP_0_SLAVES_REG_GROUP                       , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP      );
+REG64_FLD( PERV_MCAST_GRP_0_SLAVES_REG_GROUP_LEN                   , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP_LEN  );
+
+REG64_FLD( PERV_MCAST_GRP_1_SLAVES_REG_GROUP                       , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP      );
+REG64_FLD( PERV_MCAST_GRP_1_SLAVES_REG_GROUP_LEN                   , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP_LEN  );
+
+REG64_FLD( PERV_MCAST_GRP_2_SLAVES_REG_GROUP                       , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP      );
+REG64_FLD( PERV_MCAST_GRP_2_SLAVES_REG_GROUP_LEN                   , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP_LEN  );
+
+REG64_FLD( PERV_MCAST_GRP_3_SLAVES_REG_GROUP                       , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP      );
+REG64_FLD( PERV_MCAST_GRP_3_SLAVES_REG_GROUP_LEN                   , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP_LEN  );
+
+REG64_FLD( PERV_MCAST_GRP_4_SLAVES_REG_GROUP                       , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP      );
+REG64_FLD( PERV_MCAST_GRP_4_SLAVES_REG_GROUP_LEN                   , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP_LEN  );
+
+REG64_FLD( PERV_MCAST_GRP_5_SLAVES_REG_GROUP                       , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP      );
+REG64_FLD( PERV_MCAST_GRP_5_SLAVES_REG_GROUP_LEN                   , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP_LEN  );
+
+REG64_FLD( PERV_MCAST_GRP_6_SLAVES_REG_GROUP                       , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP      );
+REG64_FLD( PERV_MCAST_GRP_6_SLAVES_REG_GROUP_LEN                   , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GROUP_LEN  );
+
+REG64_FLD( PERV_1_MODE_REG_IN0                                     , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( PERV_1_MODE_REG_IN1                                     , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN1        );
+REG64_FLD( PERV_1_MODE_REG_IN2                                     , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN2        );
+REG64_FLD( PERV_1_MODE_REG_IN3                                     , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN3        );
+REG64_FLD( PERV_1_MODE_REG_IN4                                     , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( PERV_1_MODE_REG_IN5                                     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( PERV_1_MODE_REG_IN6                                     , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN6        );
+REG64_FLD( PERV_1_MODE_REG_IN7                                     , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN7        );
+REG64_FLD( PERV_1_MODE_REG_IN8                                     , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN8        );
+REG64_FLD( PERV_1_MODE_REG_IN9                                     , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN9        );
+REG64_FLD( PERV_1_MODE_REG_IN10                                    , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN10       );
+REG64_FLD( PERV_1_MODE_REG_IN11                                    , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN11       );
+REG64_FLD( PERV_1_MODE_REG_IN                                      , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( PERV_1_MODE_REG_IN_LEN                                  , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_BIT_RATE_DIVISOR_0          , 10  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_BIT_RATE_DIVISOR_0 );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_BIT_RATE_DIVISOR_0_LEN      , 6   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_BIT_RATE_DIVISOR_0_LEN );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_PORT_NUMBER_0               , 16  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_PORT_NUMBER_0 );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_PORT_NUMBER_0_LEN           , 6   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_PORT_NUMBER_0_LEN );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_CHKSW_I2C_BUSY_0            , 27  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_CHKSW_I2C_BUSY_0 );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_FGAT_0                      , 28  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_FGAT_0     );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_DIAG_0                      , 29  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_DIAG_0     );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_PACING_ALLOW_0              , 30  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_PACING_ALLOW_0 );
+REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_WRAP_0                      , 31  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_WRAP_0     );
+
+REG64_FLD( PERV_1_MULTICAST_GROUP_1_MULTICAST1                     , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST1 );
+REG64_FLD( PERV_1_MULTICAST_GROUP_1_MULTICAST1_LEN                 , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST1_LEN );
+
+REG64_FLD( PERV_1_MULTICAST_GROUP_2_MULTICAST2                     , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST2 );
+REG64_FLD( PERV_1_MULTICAST_GROUP_2_MULTICAST2_LEN                 , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST2_LEN );
+
+REG64_FLD( PERV_1_MULTICAST_GROUP_3_MULTICAST3                     , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST3 );
+REG64_FLD( PERV_1_MULTICAST_GROUP_3_MULTICAST3_LEN                 , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST3_LEN );
+
+REG64_FLD( PERV_1_MULTICAST_GROUP_4_MULTICAST4                     , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST4 );
+REG64_FLD( PERV_1_MULTICAST_GROUP_4_MULTICAST4_LEN                 , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST4_LEN );
+
+REG64_FLD( PERV_1_NET_CTRL0_CHIPLET_ENABLE                         , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_CHIPLET_ENABLE );
+REG64_FLD( PERV_1_NET_CTRL0_PCB_EP_RESET                           , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_PCB_EP_RESET );
+REG64_FLD( PERV_1_NET_CTRL0_CLK_ASYNC_RESET                        , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_ASYNC_RESET );
+REG64_FLD( PERV_1_NET_CTRL0_PLL_TEST_EN                            , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_TEST_EN );
+REG64_FLD( PERV_1_NET_CTRL0_PLL_RESET                              , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_RESET  );
+REG64_FLD( PERV_1_NET_CTRL0_PLL_BYPASS                             , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_BYPASS );
+REG64_FLD( PERV_1_NET_CTRL0_VITAL_SCAN                             , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_SCAN );
+REG64_FLD( PERV_1_NET_CTRL0_VITAL_SCAN_IN                          , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_SCAN_IN );
+REG64_FLD( PERV_1_NET_CTRL0_VITAL_PHASE                            , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_PHASE );
+REG64_FLD( PERV_1_NET_CTRL0_FLUSH_ALIGN_OVR                        , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_FLUSH_ALIGN_OVR );
+REG64_FLD( PERV_1_NET_CTRL0_VITAL_AL                               , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_AL   );
+REG64_FLD( PERV_1_NET_CTRL0_ACT_DIS                                , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_ACT_DIS    );
+REG64_FLD( PERV_1_NET_CTRL0_MPW1                                   , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_MPW1       );
+REG64_FLD( PERV_1_NET_CTRL0_MPW2                                   , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_MPW2       );
+REG64_FLD( PERV_1_NET_CTRL0_MPW3                                   , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_MPW3       );
+REG64_FLD( PERV_1_NET_CTRL0_DELAY_LCLKR                            , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_DELAY_LCLKR );
+REG64_FLD( PERV_1_NET_CTRL0_VITAL_THOLD                            , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_THOLD );
+REG64_FLD( PERV_1_NET_CTRL0_FLUSH_SCAN_N                           , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_FLUSH_SCAN_N );
+REG64_FLD( PERV_1_NET_CTRL0_FENCE_EN                               , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_FENCE_EN   );
+REG64_FLD( PERV_1_NET_CTRL0_CPLT_RCTRL                             , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_CPLT_RCTRL );
+REG64_FLD( PERV_1_NET_CTRL0_CPLT_DCTRL                             , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_CPLT_DCTRL );
+REG64_FLD( PERV_1_NET_CTRL0_L3_EDRAM_ENABLE0                       , 23  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_L3_EDRAM_ENABLE0 );
+REG64_FLD( PERV_1_NET_CTRL0_L3_EDRAM_ENABLE1                       , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_L3_EDRAM_ENABLE1 );
+REG64_FLD( PERV_1_NET_CTRL0_TP_FENCE_PCB                           , 25  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_TP_FENCE_PCB );
+REG64_FLD( PERV_1_NET_CTRL0_LVLTRANS_FENCE                         , 26  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_LVLTRANS_FENCE );
+REG64_FLD( PERV_1_NET_CTRL0_ARRAY_WRITE_ASSIST_EN                  , 27  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_ARRAY_WRITE_ASSIST_EN );
+REG64_FLD( PERV_1_NET_CTRL0_HTB_INTEST                             , 28  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_HTB_INTEST );
+REG64_FLD( PERV_1_NET_CTRL0_HTB_EXTEST                             , 29  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_HTB_EXTEST );
+REG64_FLD( PERV_1_NET_CTRL0_PLLFORCE_OUT_EN                        , 31  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLLFORCE_OUT_EN );
+
+REG64_FLD( PERV_1_NET_CTRL1_PLL_CLKIN_SEL                          , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_CLKIN_SEL );
+REG64_FLD( PERV_1_NET_CTRL1_CLK_DCC_BYPASS_EN                      , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_DCC_BYPASS_EN );
+REG64_FLD( PERV_1_NET_CTRL1_CLK_PDLY_BYPASS_EN                     , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PDLY_BYPASS_EN );
+REG64_FLD( PERV_1_NET_CTRL1_CLK_DIV_BYPASS_EN                      , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_DIV_BYPASS_EN );
+REG64_FLD( PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL                     , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_REFCLK_CLKMUX0_SEL );
+REG64_FLD( PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL                     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_REFCLK_CLKMUX1_SEL );
+REG64_FLD( PERV_1_NET_CTRL1_PLL_BNDY_BYPASS_EN                     , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_BNDY_BYPASS_EN );
+REG64_FLD( PERV_1_NET_CTRL1_DPLL_TEST_SEL                          , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_DPLL_TEST_SEL );
+REG64_FLD( PERV_1_NET_CTRL1_DPLL_TEST_SEL_LEN                      , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_DPLL_TEST_SEL_LEN );
+REG64_FLD( PERV_1_NET_CTRL1_SB_STRENGTH                            , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_SB_STRENGTH );
+REG64_FLD( PERV_1_NET_CTRL1_SB_STRENGTH_LEN                        , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_SB_STRENGTH_LEN );
+REG64_FLD( PERV_1_NET_CTRL1_ASYNC_TYPE                             , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_ASYNC_TYPE );
+REG64_FLD( PERV_1_NET_CTRL1_ASYNC_OBS                              , 21  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_ASYNC_OBS  );
+REG64_FLD( PERV_1_NET_CTRL1_CPM_CAL_SET                            , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_CPM_CAL_SET );
+REG64_FLD( PERV_1_NET_CTRL1_SENSEADJ_RESET0                        , 23  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_SENSEADJ_RESET0 );
+REG64_FLD( PERV_1_NET_CTRL1_SENSEADJ_RESET1                        , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_SENSEADJ_RESET1 );
+REG64_FLD( PERV_1_NET_CTRL1_CLK_PULSE_EN                           , 25  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PULSE_EN );
+REG64_FLD( PERV_1_NET_CTRL1_CLK_PULSE_MODE                         , 26  , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PULSE_MODE );
+REG64_FLD( PERV_1_NET_CTRL1_CLK_PULSE_MODE_LEN                     , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PULSE_MODE_LEN );
+
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_SRAM_CERRRPT                  , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_SRAM_CERRRPT );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_SRAM_CERRRPT_LEN              , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_SRAM_CERRRPT_LEN );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_JTAGACC_CERRPT                , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_JTAGACC_CERRPT );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_JTAGACC_CERRPT_LEN            , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_JTAGACC_CERRPT_LEN );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_C405_DCU_ECC_UE               , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_C405_DCU_ECC_UE );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_C405_DCU_ECC_CE               , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_C405_DCU_ECC_CE );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_C405_ICU_ECC_UE               , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_C405_ICU_ECC_UE );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_C405_ICU_ECC_CE               , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_C405_ICU_ECC_CE );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE0_OCISLV_ERR               , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_GPE0_OCISLV_ERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE0_OCISLV_ERR_LEN           , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_GPE0_OCISLV_ERR_LEN );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE1_OCISLV_ERR               , 28  , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_GPE1_OCISLV_ERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE1_OCISLV_ERR_LEN           , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_GPE1_OCISLV_ERR_LEN );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE2_OCISLV_ERR               , 36  , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_GPE2_OCISLV_ERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE2_OCISLV_ERR_LEN           , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_GPE2_OCISLV_ERR_LEN );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE3_OCISLV_ERR               , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_GPE3_OCISLV_ERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE3_OCISLV_ERR_LEN           , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_GPE3_OCISLV_ERR_LEN );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_OCB_OCISLV_ERR                , 52  , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_OCB_OCISLV_ERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_OCB_OCISLV_ERR_LEN            , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM_WCLRPART,
+           SH_FLD_OCB_OCISLV_ERR_LEN );
+
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_FW0                             , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FW0        );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_FW1                             , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FW1        );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_CME_ERROR_NOTIFY                , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_ERROR_NOTIFY );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_STOP_RECOVERY_NOTIFY_PRD        , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_STOP_RECOVERY_NOTIFY_PRD );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_HB_ERROR                        , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_HB_ERROR   );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE0_WATCHDOG_TIMEOUT           , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE0_WATCHDOG_TIMEOUT );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE1_WATCHDOG_TIMEOUT           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE1_WATCHDOG_TIMEOUT );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE2_WATCHDOG_TIMEOUT           , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE2_WATCHDOG_TIMEOUT );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE3_WATCHDOG_TIMEOUT           , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE3_WATCHDOG_TIMEOUT );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE0_ERROR                      , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE0_ERROR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE1_ERROR                      , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE1_ERROR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE2_ERROR                      , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE2_ERROR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE3_ERROR                      , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE3_ERROR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_ERROR                       , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_ERROR  );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_UE                          , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_UE     );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_CE                          , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_CE     );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_READ_ERROR                  , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_READ_ERROR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_WRITE_ERROR                 , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_WRITE_ERROR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_DATAOUT_PERR                , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_DATAOUT_PERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_OCI_WRITE_DATA_PARITY       , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_OCI_WRITE_DATA_PARITY );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_OCI_BE_PARITY_ERR           , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_OCI_BE_PARITY_ERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_OCI_ADDR_PARITY_ERR         , 21  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_OCI_ADDR_PARITY_ERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE0_HALTED                     , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE0_HALTED );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE1_HALTED                     , 23  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE1_HALTED );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE2_HALTED                     , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE2_HALTED );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE3_HALTED                     , 25  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE3_HALTED );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_EXTERNAL_TRAP                   , 26  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_EXTERNAL_TRAP );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_PPC405_CORE_RESET               , 27  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPC405_CORE_RESET );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_PPC405_CHIP_RESET               , 28  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPC405_CHIP_RESET );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_PPC405_SYSTEM_RESET             , 29  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPC405_SYSTEM_RESET );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_PPC405_DBGMSRWE                 , 30  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPC405_DBGMSRWE );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_PPC405_DBGSTOPACK               , 31  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPC405_DBGSTOPACK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_DB_OCI_TIMEOUT              , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_DB_OCI_TIMEOUT );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_DB_OCI_READ_DATA_PARITY     , 33  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_DB_OCI_READ_DATA_PARITY );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_DB_OCI_SLAVE_ERROR          , 34  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_DB_OCI_SLAVE_ERROR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_PIB_ADDR_PARITY_ERR         , 35  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_PIB_ADDR_PARITY_ERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_DB_PIB_DATA_PARITY_ERR      , 36  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_DB_PIB_DATA_PARITY_ERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_IDC0_ERROR                  , 37  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_IDC0_ERROR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_IDC1_ERROR                  , 38  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_IDC1_ERROR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_IDC2_ERROR                  , 39  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_IDC2_ERROR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_IDC3_ERROR                  , 40  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_IDC3_ERROR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_FSM_ERR                     , 41  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_FSM_ERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_JTAGACC_ERR                     , 42  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_JTAGACC_ERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SPARE_ERR_38                    , 43  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_ERR_38 );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_C405_ECC_UE                     , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_C405_ECC_UE );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_C405_ECC_CE                     , 45  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_C405_ECC_CE );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_C405_OCI_MACHINECHECK           , 46  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_C405_OCI_MACHINECHECK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRAM_SPARE_DIRECT_ERROR0        , 47  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SPARE_DIRECT_ERROR0 );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRAM_SPARE_DIRECT_ERROR1        , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SPARE_DIRECT_ERROR1 );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRAM_SPARE_DIRECT_ERROR2        , 49  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SPARE_DIRECT_ERROR2 );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRAM_SPARE_DIRECT_ERROR3        , 50  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SPARE_DIRECT_ERROR3 );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE0_OCISLV_ERR                 , 51  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE0_OCISLV_ERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE1_OCISLV_ERR                 , 52  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE1_OCISLV_ERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE2_OCISLV_ERR                 , 53  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE2_OCISLV_ERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE3_OCISLV_ERR                 , 54  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE3_OCISLV_ERR );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_C405ICU_M_TIMEOUT               , 55  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_C405ICU_M_TIMEOUT );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_C405DCU_M_TIMEOUT               , 56  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_C405DCU_M_TIMEOUT );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_COMPLEX_FAULT                   , 57  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMPLEX_FAULT );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_COMPLEX_NOTIFY                  , 58  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMPLEX_NOTIFY );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SPARE_59_61                     , 59  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_59_61 );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SPARE_59_61_LEN                 , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_59_61_LEN );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_FIR_PARITY_ERR_DUP              , 62  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_PARITY_ERR_DUP );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_FIR_PARITY_ERR                  , 63  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_PARITY_ERR );
+
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRACT0_FIR_ACTION0                 , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION0 );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRACT0_FIR_ACTION0_LEN             , 64  , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION0_LEN );
+
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRACT1_FIR_ACTION1                 , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION1 );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRACT1_FIR_ACTION1_LEN             , 64  , SH_UNT_PERV_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION1_LEN );
+
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_FW0_MASK                    , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FW0_MASK   );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_FW1_MASK                    , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FW1_MASK   );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SPARE_2_MASK                , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_2_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SPARE_3_MASK                , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_3_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_HB_MALF_MASK                , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_HB_MALF_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE0_WATCHDOG_TIMEOUT_MASK  , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE0_WATCHDOG_TIMEOUT_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE1_WATCHDOG_TIMEOUT_MASK  , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE1_WATCHDOG_TIMEOUT_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE2_WATCHDOG_TIMEOUT_MASK  , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE2_WATCHDOG_TIMEOUT_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE3_WATCHDOG_TIMEOUT_MASK  , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE3_WATCHDOG_TIMEOUT_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE0_ERROR_MASK             , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE0_ERROR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE1_ERROR_MASK             , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE1_ERROR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE2_ERROR_MASK             , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE2_ERROR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE3_ERROR_MASK             , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE3_ERROR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_ERROR_MASK              , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_ERROR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_UE_MASK                 , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_UE_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_CE_MASK                 , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_CE_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_READ_ERROR_MASK         , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_READ_ERROR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_WRITE_ERROR_MASK        , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_WRITE_ERROR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_DATAOUT_PERR_MASK       , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_DATAOUT_PERR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_OCI_WRITE_DATA_PARITY_MASK , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_OCI_WRITE_DATA_PARITY_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_OCI_BE_PARITY_ERR_MASK  , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_OCI_BE_PARITY_ERR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_OCI_ADDR_PARITY_ERR_MASK , 21  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_OCI_ADDR_PARITY_ERR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE0_HALTED_MASK            , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE0_HALTED_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE1_HALTED_MASK            , 23  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE1_HALTED_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE2_HALTED_MASK            , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE2_HALTED_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE3_HALTED_MASK            , 25  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE3_HALTED_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_EXTERNAL_TRAP_MASK          , 26  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_EXTERNAL_TRAP_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_PPC405_CORE_RESET_MASK      , 27  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPC405_CORE_RESET_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_PPC405_CHIP_RESET_MASK      , 28  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPC405_CHIP_RESET_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_PPC405_SYSTEM_RESET_MASK    , 29  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPC405_SYSTEM_RESET_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_PPC405_DBGMSRWE_MASK        , 30  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPC405_DBGMSRWE_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_PPC405_DBGSTOPACK_MASK      , 31  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPC405_DBGSTOPACK_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_DB_OCI_TIMEOUT_MASK     , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_DB_OCI_TIMEOUT_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_DB_OCI_READ_DATA_PARITY_MASK , 33  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_DB_OCI_READ_DATA_PARITY_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_DB_OCI_SLAVE_ERROR_MASK , 34  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_DB_OCI_SLAVE_ERROR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_PIB_ADDR_PARITY_ERR_MASK , 35  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_PIB_ADDR_PARITY_ERR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_DB_PIB_DATA_PARITY_ERR_MASK , 36  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_DB_PIB_DATA_PARITY_ERR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_IDC0_ERROR_MASK         , 37  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_IDC0_ERROR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_IDC1_ERROR_MASK         , 38  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_IDC1_ERROR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_IDC2_ERROR_MASK         , 39  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_IDC2_ERROR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_IDC3_ERROR_MASK         , 40  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_OCB_IDC3_ERROR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_FSM_ERR_MASK            , 41  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRT_FSM_ERR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_JTAGACC_ERR_MASK            , 42  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_JTAGACC_ERR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SPARE_ERR_38_MASK           , 43  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_ERR_38_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_C405_ECC_UE_MASK            , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_C405_ECC_UE_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_C405_ECC_CE_MASK            , 45  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_C405_ECC_CE_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_C405_OCI_MACHINECHECK_MASK  , 46  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_C405_OCI_MACHINECHECK_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRAM_SPARE_DIRECT_ERROR0_MASK , 47  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SPARE_DIRECT_ERROR0_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRAM_SPARE_DIRECT_ERROR1_MASK , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SPARE_DIRECT_ERROR1_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRAM_SPARE_DIRECT_ERROR2_MASK , 49  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SPARE_DIRECT_ERROR2_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRAM_SPARE_DIRECT_ERROR3_MASK , 50  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SPARE_DIRECT_ERROR3_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE0_OCISLV_ERR_MASK        , 51  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE0_OCISLV_ERR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE1_OCISLV_ERR_MASK        , 52  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE1_OCISLV_ERR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE2_OCISLV_ERR_MASK        , 53  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE2_OCISLV_ERR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE3_OCISLV_ERR_MASK        , 54  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_GPE3_OCISLV_ERR_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_C405ICU_M_TIMEOUT_MASK      , 55  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_C405ICU_M_TIMEOUT_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_C405DCU_M_TIMEOUT_MASK      , 56  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_C405DCU_M_TIMEOUT_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_COMPLEX_FAULT_MASK          , 57  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMPLEX_FAULT_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_COMPLEX_NOTIFY_MASK         , 58  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMPLEX_NOTIFY_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SPARE_59_61                 , 59  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_59_61 );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SPARE_59_61_LEN             , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_59_61_LEN );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_FIR_PARITY_ERR_DUP_MASK     , 62  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_PARITY_ERR_DUP_MASK );
+REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_FIR_PARITY_ERR_MASK         , 63  , SH_UNT_PERV_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_PARITY_ERR_MASK );
+
+REG64_FLD( PERV_1_OPCG_ALIGN_INOP                                  , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INOP       );
+REG64_FLD( PERV_1_OPCG_ALIGN_INOP_LEN                              , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INOP_LEN   );
+REG64_FLD( PERV_1_OPCG_ALIGN_SNOP                                  , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SNOP       );
+REG64_FLD( PERV_1_OPCG_ALIGN_SNOP_LEN                              , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_LEN   );
+REG64_FLD( PERV_1_OPCG_ALIGN_ENOP                                  , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENOP       );
+REG64_FLD( PERV_1_OPCG_ALIGN_ENOP_LEN                              , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_LEN   );
+REG64_FLD( PERV_1_OPCG_ALIGN_INOP_WAIT                             , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INOP_WAIT  );
+REG64_FLD( PERV_1_OPCG_ALIGN_INOP_WAIT_LEN                         , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INOP_WAIT_LEN );
+REG64_FLD( PERV_1_OPCG_ALIGN_SNOP_WAIT                             , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_WAIT  );
+REG64_FLD( PERV_1_OPCG_ALIGN_SNOP_WAIT_LEN                         , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_WAIT_LEN );
+REG64_FLD( PERV_1_OPCG_ALIGN_ENOP_WAIT                             , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_WAIT  );
+REG64_FLD( PERV_1_OPCG_ALIGN_ENOP_WAIT_LEN                         , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_WAIT_LEN );
+REG64_FLD( PERV_1_OPCG_ALIGN_INOP_FORCE_SG                         , 40  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INOP_FORCE_SG );
+REG64_FLD( PERV_1_OPCG_ALIGN_SNOP_FORCE_SG                         , 41  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_FORCE_SG );
+REG64_FLD( PERV_1_OPCG_ALIGN_ENOP_FORCE_SG                         , 42  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_FORCE_SG );
+REG64_FLD( PERV_1_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD                    , 43  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_NO_WAIT_ON_CLK_CMD );
+REG64_FLD( PERV_1_OPCG_ALIGN_SOURCE_SELECT                         , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SOURCE_SELECT );
+REG64_FLD( PERV_1_OPCG_ALIGN_SOURCE_SELECT_LEN                     , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SOURCE_SELECT_LEN );
+REG64_FLD( PERV_1_OPCG_ALIGN_UNUSED46                              , 46  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED46   );
+REG64_FLD( PERV_1_OPCG_ALIGN_SCAN_RATIO                            , 47  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_RATIO );
+REG64_FLD( PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN                        , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_RATIO_LEN );
+REG64_FLD( PERV_1_OPCG_ALIGN_WAIT_CYCLES                           , 52  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( PERV_1_OPCG_ALIGN_WAIT_CYCLES_LEN                       , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( PERV_1_OPCG_CAPT1_COUNT                                 , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COUNT      );
+REG64_FLD( PERV_1_OPCG_CAPT1_COUNT_LEN                             , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COUNT_LEN  );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_01                                , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_01     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_01_LEN                            , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_01_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_02                                , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_02     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_02_LEN                            , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_02_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_03                                , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_03     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_03_LEN                            , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_03_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_04                                , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_04     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_04_LEN                            , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_04_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_05                                , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_05     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_05_LEN                            , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_05_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_06                                , 29  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_06     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_06_LEN                            , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_06_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_07                                , 34  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_07_LEN                            , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_08                                , 39  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_08_LEN                            , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_09                                , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_09_LEN                            , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_10                                , 49  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_10_LEN                            , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_11                                , 54  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_11_LEN                            , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_12                                , 59  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12     );
+REG64_FLD( PERV_1_OPCG_CAPT1_SEQ_12_LEN                            , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12_LEN );
+
+REG64_FLD( PERV_1_OPCG_CAPT2_UNUSED                                , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PERV_1_OPCG_CAPT2_UNUSED_LEN                            , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_13_01EVEN                         , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_13_01EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_13_01EVEN_LEN                     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_13_01EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_14_01ODD                          , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_14_01ODD );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_14_01ODD_LEN                      , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_14_01ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_15_02EVEN                         , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_15_02EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_15_02EVEN_LEN                     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_15_02EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_16_02ODD                          , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_16_02ODD );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_16_02ODD_LEN                      , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_16_02ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_17_03EVEN                         , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_17_03EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_17_03EVEN_LEN                     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_17_03EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_18_03ODD                          , 29  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_18_03ODD );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_18_03ODD_LEN                      , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_18_03ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_19_04EVEN                         , 34  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_19_04EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_19_04EVEN_LEN                     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_19_04EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_20_04ODD                          , 39  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_20_04ODD );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_20_04ODD_LEN                      , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_20_04ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_21_05EVEN                         , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_21_05EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_21_05EVEN_LEN                     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_21_05EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_22_05ODD                          , 49  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_22_05ODD );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_22_05ODD_LEN                      , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_22_05ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_23_06EVEN                         , 54  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_23_06EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_23_06EVEN_LEN                     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_23_06EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_24_06ODD                          , 59  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_24_06ODD );
+REG64_FLD( PERV_1_OPCG_CAPT2_SEQ_24_06ODD_LEN                      , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_24_06ODD_LEN );
+
+REG64_FLD( PERV_1_OPCG_CAPT3_UNUSED                                , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PERV_1_OPCG_CAPT3_UNUSED_LEN                            , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_07EVEN                            , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_07EVEN_LEN                        , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_07ODD                             , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07ODD  );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_07ODD_LEN                         , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_08EVEN                            , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_08EVEN_LEN                        , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_08ODD                             , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08ODD  );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_08ODD_LEN                         , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_09EVEN                            , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_09EVEN_LEN                        , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_09ODD                             , 29  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09ODD  );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_09ODD_LEN                         , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_10EVEN                            , 34  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_10EVEN_LEN                        , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_10ODD                             , 39  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10ODD  );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_10ODD_LEN                         , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_11EVEN                            , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_11EVEN_LEN                        , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_11ODD                             , 49  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11ODD  );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_11ODD_LEN                         , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11ODD_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_12EVEN                            , 54  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12EVEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_12EVEN_LEN                        , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12EVEN_LEN );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_12ODD                             , 59  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12ODD  );
+REG64_FLD( PERV_1_OPCG_CAPT3_SEQ_12ODD_LEN                         , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12ODD_LEN );
+
+REG64_FLD( PERV_1_OPCG_REG0_RUNN_MODE                              , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_MODE  );
+REG64_FLD( PERV_1_OPCG_REG0_GO                                     , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GO         );
+REG64_FLD( PERV_1_OPCG_REG0_RUN_SCAN0                              , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RUN_SCAN0  );
+REG64_FLD( PERV_1_OPCG_REG0_SCAN0_MODE                             , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCAN0_MODE );
+REG64_FLD( PERV_1_OPCG_REG0_IN_SLAVE_MODE                          , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN_SLAVE_MODE );
+REG64_FLD( PERV_1_OPCG_REG0_IN_MASTER_MODE                         , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN_MASTER_MODE );
+REG64_FLD( PERV_1_OPCG_REG0_KEEP_MS_MODE                           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_KEEP_MS_MODE );
+REG64_FLD( PERV_1_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL              , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_ON_UNIT0_SYNC_LVL );
+REG64_FLD( PERV_1_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL              , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_ON_UNIT1_SYNC_LVL );
+REG64_FLD( PERV_1_OPCG_REG0_RUN_CHIPLET_SCAN0                      , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RUN_CHIPLET_SCAN0 );
+REG64_FLD( PERV_1_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL               , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL );
+REG64_FLD( PERV_1_OPCG_REG0_RUN_ON_UPDATE_DR                       , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RUN_ON_UPDATE_DR );
+REG64_FLD( PERV_1_OPCG_REG0_RUN_ON_CAPTURE_DR                      , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RUN_ON_CAPTURE_DR );
+REG64_FLD( PERV_1_OPCG_REG0_STOP_RUNN_ON_XSTOP                     , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STOP_RUNN_ON_XSTOP );
+REG64_FLD( PERV_1_OPCG_REG0_STARTS_BIST                            , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STARTS_BIST );
+REG64_FLD( PERV_1_OPCG_REG0_UNUSED1520                             , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1520 );
+REG64_FLD( PERV_1_OPCG_REG0_UNUSED1520_LEN                         , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1520_LEN );
+REG64_FLD( PERV_1_OPCG_REG0_LOOP_COUNT                             , 21  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_LOOP_COUNT );
+REG64_FLD( PERV_1_OPCG_REG0_LOOP_COUNT_LEN                         , 43  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_LOOP_COUNT_LEN );
+
+REG64_FLD( PERV_1_OPCG_REG1_SCAN_COUNT                             , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_COUNT );
+REG64_FLD( PERV_1_OPCG_REG1_SCAN_COUNT_LEN                         , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_COUNT_LEN );
+REG64_FLD( PERV_1_OPCG_REG1_MISR_A_VAL                             , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MISR_A_VAL );
+REG64_FLD( PERV_1_OPCG_REG1_MISR_A_VAL_LEN                         , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MISR_A_VAL_LEN );
+REG64_FLD( PERV_1_OPCG_REG1_MISR_B_VAL                             , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MISR_B_VAL );
+REG64_FLD( PERV_1_OPCG_REG1_MISR_B_VAL_LEN                         , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MISR_B_VAL_LEN );
+REG64_FLD( PERV_1_OPCG_REG1_MISR_INIT_WAIT                         , 36  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MISR_INIT_WAIT );
+REG64_FLD( PERV_1_OPCG_REG1_MISR_INIT_WAIT_LEN                     , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MISR_INIT_WAIT_LEN );
+REG64_FLD( PERV_1_OPCG_REG1_SUPPRESS_EVEN_CLK                      , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SUPPRESS_EVEN_CLK );
+REG64_FLD( PERV_1_OPCG_REG1_SCAN_CLK_USE_EVEN                      , 49  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_CLK_USE_EVEN );
+REG64_FLD( PERV_1_OPCG_REG1_UNUSED2                                , 50  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2    );
+REG64_FLD( PERV_1_OPCG_REG1_UNUSED2_LEN                            , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2_LEN );
+REG64_FLD( PERV_1_OPCG_REG1_RTIM_THOLD_FORCE                       , 52  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RTIM_THOLD_FORCE );
+REG64_FLD( PERV_1_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL            , 53  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_ARY_CLK_DURING_FILL );
+REG64_FLD( PERV_1_OPCG_REG1_SG_HIGH_DURING_FILL                    , 54  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SG_HIGH_DURING_FILL );
+REG64_FLD( PERV_1_OPCG_REG1_LBIST_SKITTER_CTL                      , 55  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_LBIST_SKITTER_CTL );
+REG64_FLD( PERV_1_OPCG_REG1_LBIST_SKITTER_CTL_LEN                  , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_LBIST_SKITTER_CTL_LEN );
+REG64_FLD( PERV_1_OPCG_REG1_MISR_MODE                              , 57  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MISR_MODE  );
+REG64_FLD( PERV_1_OPCG_REG1_INFINITE_MODE                          , 58  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INFINITE_MODE );
+REG64_FLD( PERV_1_OPCG_REG1_NSL_FILL_COUNT                         , 59  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSL_FILL_COUNT );
+REG64_FLD( PERV_1_OPCG_REG1_NSL_FILL_COUNT_LEN                     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSL_FILL_COUNT_LEN );
+
+REG64_FLD( PERV_1_OPCG_REG2_GO2                                    , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GO2        );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_WEIGHTING                         , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_WEIGHTING );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_WEIGHTING_LEN                     , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_WEIGHTING_LEN );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_VALUE                             , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_VALUE );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_VALUE_LEN                         , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_VALUE_LEN );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_A_VAL                             , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_A_VAL );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_A_VAL_LEN                         , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_A_VAL_LEN );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_B_VAL                             , 28  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_B_VAL );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_B_VAL_LEN                         , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_B_VAL_LEN );
+REG64_FLD( PERV_1_OPCG_REG2_PRPG_MODE                              , 40  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_MODE  );
+REG64_FLD( PERV_1_OPCG_REG2_UNUSED41_63                            , 41  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED41_63 );
+REG64_FLD( PERV_1_OPCG_REG2_UNUSED41_63_LEN                        , 23  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED41_63_LEN );
+
+REG64_FLD( PERV_1_OSCERR_HOLD_CP                                   , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CP         );
+REG64_FLD( PERV_1_OSCERR_HOLD_CP_LEN                               , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CP_LEN     );
+REG64_FLD( PERV_1_OSCERR_HOLD_MEM                                  , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MEM        );
+REG64_FLD( PERV_1_OSCERR_HOLD_MEM_LEN                              , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MEM_LEN    );
+REG64_FLD( PERV_1_OSCERR_HOLD_GX                                   , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GX         );
+REG64_FLD( PERV_1_OSCERR_HOLD_GX_LEN                               , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GX_LEN     );
+REG64_FLD( PERV_1_OSCERR_HOLD_CPLITE                               , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CPLITE     );
+REG64_FLD( PERV_1_OSCERR_HOLD_CPLITE_LEN                           , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CPLITE_LEN );
+
+REG64_FLD( PERV_1_OSCERR_MASK_CP                                   , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CP         );
+REG64_FLD( PERV_1_OSCERR_MASK_CP_LEN                               , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CP_LEN     );
+REG64_FLD( PERV_1_OSCERR_MASK_MEM                                  , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MEM        );
+REG64_FLD( PERV_1_OSCERR_MASK_MEM_LEN                              , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MEM_LEN    );
+REG64_FLD( PERV_1_OSCERR_MASK_GX                                   , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GX         );
+REG64_FLD( PERV_1_OSCERR_MASK_GX_LEN                               , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GX_LEN     );
+REG64_FLD( PERV_1_OSCERR_MASK_CPLITE                               , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CPLITE     );
+REG64_FLD( PERV_1_OSCERR_MASK_CPLITE_LEN                           , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CPLITE_LEN );
+
+REG64_FLD( PERV_1_OSCERR_MCODE_IN                                  , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( PERV_1_OSCERR_MCODE_IN_LEN                              , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_ACTUAL_ERROR                   , 4   , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_0_ACTUAL_ERROR );
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_ACTUAL_ERROR_LEN               , 4   , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_0_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_PORT_0_ENABLE                  , 8   , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_0_PORT_0_ENABLE );
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_PORT_1_ENABLE                  , 12  , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_0_PORT_1_ENABLE );
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_PORT_2_ENABLE                  , 16  , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_0_PORT_2_ENABLE );
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_PORT_3_ENABLE                  , 20  , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_0_PORT_3_ENABLE );
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_PORT_4_ENABLE                  , 24  , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_0_PORT_4_ENABLE );
+REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_PORT_5_ENABLE                  , 28  , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_0_PORT_5_ENABLE );
+
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_0_PORT_6_ENABLE                  , 0   , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_0_PORT_6_ENABLE );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_0_PORT_7_ENABLE                  , 4   , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_0_PORT_7_ENABLE );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_1_ACTUAL_ERROR                   , 8   , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_1_ACTUAL_ERROR );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_1_ACTUAL_ERROR_LEN               , 4   , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_1_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_1_PORT_0_ENABLE                  , 12  , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_1_PORT_0_ENABLE );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_1_PORT_1_ENABLE                  , 16  , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_1_PORT_1_ENABLE );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_1_PORT_2_ENABLE                  , 20  , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_1_PORT_2_ENABLE );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_1_PORT_3_ENABLE                  , 24  , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_1_PORT_3_ENABLE );
+REG32_FLD( PERV_PEEK4A4_FSI_A_MST_1_PORT_4_ENABLE                  , 28  , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_A_MST_1_PORT_4_ENABLE );
+
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_ACTUAL_ERROR                   , 4   , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_B_MST_0_ACTUAL_ERROR );
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_ACTUAL_ERROR_LEN               , 4   , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_B_MST_0_ACTUAL_ERROR_LEN );
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_PORT_0_ENABLE                  , 8   , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_B_MST_0_PORT_0_ENABLE );
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_PORT_1_ENABLE                  , 12  , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_B_MST_0_PORT_1_ENABLE );
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_PORT_2_ENABLE                  , 16  , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_B_MST_0_PORT_2_ENABLE );
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_PORT_3_ENABLE                  , 20  , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_B_MST_0_PORT_3_ENABLE );
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_PORT_4_ENABLE                  , 24  , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_B_MST_0_PORT_4_ENABLE );
+REG32_FLD( PERV_PEEK4A8_FSI_B_MST_0_PORT_5_ENABLE                  , 28  , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_B_MST_0_PORT_5_ENABLE );
+
+REG32_FLD( PERV_PEEK4AC_FSI_B_MST_0_PORT_6_ENABLE                  , 0   , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_B_MST_0_PORT_6_ENABLE );
+REG32_FLD( PERV_PEEK4AC_FSI_B_MST_0_PORT_7_ENABLE                  , 4   , SH_UNT_PERV     , SH_ACS_FSI      ,
+           SH_FLD_FSI_B_MST_0_PORT_7_ENABLE );
+
+REG64_FLD( PERV_PERV_CTRL0_TP_CHIPLET_EN_DC                        , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CHIPLET_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_PCB_EP_RESET_DC                      , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PCB_EP_RESET_DC );
+REG64_FLD( PERV_PERV_CTRL0_2_RESERVED                              , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_2_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_TP_PLL_TEST_EN_DC                       , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_TEST_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_PLLRST_DC                            , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLLRST_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_PLLBYP_DC                            , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLLBYP_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_SCAN_CLK_DC                     , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_SCAN_CLK_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_SCIN_DC                         , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_SCIN_DC );
+REG64_FLD( PERV_PERV_CTRL0_8_RESERVED                              , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_8_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_TP_FLUSH_ALIGN_OVERWRITE                , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FLUSH_ALIGN_OVERWRITE );
+REG64_FLD( PERV_PERV_CTRL0_TP_ARRAY_WRITE_ASSIST_EN_DC             , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_ARRAY_WRITE_ASSIST_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_ACT_DIS_DC                      , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_ACT_DIS_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_MPW1_DC_N                       , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_MPW1_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_MPW2_DC_N                       , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_MPW2_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_MPW3_DC_N                       , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_MPW3_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_DELAY_LCLKR_DC                  , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_DELAY_LCLKR_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_VITL_CLKOFF_DC                       , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_CLKOFF_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_FLUSH_SCAN_DC_N                      , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FLUSH_SCAN_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_TP_FENCE_EN_DC                          , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FENCE_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_RI_DC_N                              , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_RI_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_TP_DI1_DC_N                             , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_DI1_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_TP_DI2_DC_N                             , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_DI2_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_22_RESERVED                             , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_23_RESERVED                             , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_24_RESERVED                             , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_24_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_TP_FENCE_PCB_DC                         , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FENCE_PCB_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_LVLTRANS_FENCE_DC                    , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_LVLTRANS_FENCE_DC );
+REG64_FLD( PERV_PERV_CTRL0_TP_EDRAM_ENABLE_DC                      , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_EDRAM_ENABLE_DC );
+REG64_FLD( PERV_PERV_CTRL0_28_RESERVED_FOR_HTB                     , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_RESERVED_FOR_HTB );
+REG64_FLD( PERV_PERV_CTRL0_29_RESERVED_FOR_HTB                     , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_RESERVED_FOR_HTB );
+REG64_FLD( PERV_PERV_CTRL0_30_RESERVED_FOR_HTB                     , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_RESERVED_FOR_HTB );
+REG64_FLD( PERV_PERV_CTRL0_31_RESERVED_FOR_HTB                     , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_31_RESERVED_FOR_HTB );
+
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_CHIPLET_EN_DC                  , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CHIPLET_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_PCB_EP_RESET_DC                , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PCB_EP_RESET_DC );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_2_RESERVED                        , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_2_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_PLL_TEST_EN_DC                 , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_TEST_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_PLLRST_DC                      , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLLRST_DC );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_PLLBYP_DC                      , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLLBYP_DC );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_SCAN_CLK_DC               , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_SCAN_CLK_DC );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_SCIN_DC                   , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_SCIN_DC );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_8_RESERVED                        , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_8_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_FLUSH_ALIGN_OVERWRITE          , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FLUSH_ALIGN_OVERWRITE );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_ARRAY_WRITE_ASSIST_EN_DC       , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_ARRAY_WRITE_ASSIST_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_ACT_DIS_DC                , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_ACT_DIS_DC );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_MPW1_DC_N                 , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_MPW1_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_MPW2_DC_N                 , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_MPW2_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_MPW3_DC_N                 , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_MPW3_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_DELAY_LCLKR_DC            , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_DELAY_LCLKR_DC );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_CLKOFF_DC                 , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_CLKOFF_DC );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_FLUSH_SCAN_DC_N                , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FLUSH_SCAN_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_FENCE_EN_DC                    , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FENCE_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_RI_DC_N                        , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_RI_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_DI1_DC_N                       , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_DI1_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_DI2_DC_N                       , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_DI2_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_22_RESERVED                       , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_23_RESERVED                       , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_24_RESERVED                       , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_24_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_FENCE_PCB_DC                   , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FENCE_PCB_DC );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_LVLTRANS_FENCE_DC              , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_LVLTRANS_FENCE_DC );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_EDRAM_ENABLE_DC                , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_EDRAM_ENABLE_DC );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_28_RESERVED_FOR_HTB               , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_RESERVED_FOR_HTB );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_29_RESERVED_FOR_HTB               , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_RESERVED_FOR_HTB );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_30_RESERVED_FOR_HTB               , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_RESERVED_FOR_HTB );
+REG64_FLD( PERV_PERV_CTRL0_CLEAR_31_RESERVED_FOR_HTB               , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_31_RESERVED_FOR_HTB );
+
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_CHIPLET_EN_DC                    , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CHIPLET_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_PCB_EP_RESET_DC                  , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PCB_EP_RESET_DC );
+REG64_FLD( PERV_PERV_CTRL0_SET_2_RESERVED                          , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_2_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_PLL_TEST_EN_DC                   , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_TEST_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_PLLRST_DC                        , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLLRST_DC );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_PLLBYP_DC                        , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLLBYP_DC );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_SCAN_CLK_DC                 , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_SCAN_CLK_DC );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_SCIN_DC                     , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_SCIN_DC );
+REG64_FLD( PERV_PERV_CTRL0_SET_8_RESERVED                          , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_8_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_FLUSH_ALIGN_OVERWRITE            , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FLUSH_ALIGN_OVERWRITE );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_ARRAY_WRITE_ASSIST_EN_DC         , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_ARRAY_WRITE_ASSIST_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_ACT_DIS_DC                  , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_ACT_DIS_DC );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_MPW1_DC_N                   , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_MPW1_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_MPW2_DC_N                   , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_MPW2_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_MPW3_DC_N                   , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_MPW3_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_DELAY_LCLKR_DC              , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_DELAY_LCLKR_DC );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_CLKOFF_DC                   , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_VITL_CLKOFF_DC );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_FLUSH_SCAN_DC_N                  , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FLUSH_SCAN_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_FENCE_EN_DC                      , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FENCE_EN_DC );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_RI_DC_N                          , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_RI_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_DI1_DC_N                         , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_DI1_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_DI2_DC_N                         , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_DI2_DC_N );
+REG64_FLD( PERV_PERV_CTRL0_SET_22_RESERVED                         , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_SET_23_RESERVED                         , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_SET_24_RESERVED                         , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_24_RESERVED );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_FENCE_PCB_DC                     , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FENCE_PCB_DC );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_LVLTRANS_FENCE_DC                , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_LVLTRANS_FENCE_DC );
+REG64_FLD( PERV_PERV_CTRL0_SET_TP_EDRAM_ENABLE_DC                  , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_EDRAM_ENABLE_DC );
+REG64_FLD( PERV_PERV_CTRL0_SET_28_RESERVED_FOR_HTB                 , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_RESERVED_FOR_HTB );
+REG64_FLD( PERV_PERV_CTRL0_SET_29_RESERVED_FOR_HTB                 , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_RESERVED_FOR_HTB );
+REG64_FLD( PERV_PERV_CTRL0_SET_30_RESERVED_FOR_HTB                 , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_RESERVED_FOR_HTB );
+REG64_FLD( PERV_PERV_CTRL0_SET_31_RESERVED_FOR_HTB                 , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_31_RESERVED_FOR_HTB );
+
+REG64_FLD( PERV_PERV_CTRL1_UNUSED1                                 , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1    );
+REG64_FLD( PERV_PERV_CTRL1_UNUSED2                                 , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2    );
+REG64_FLD( PERV_PERV_CTRL1_UNUSED3                                 , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED3    );
+REG64_FLD( PERV_PERV_CTRL1_3_RESERVED                              , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_3_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_4_RESERVED                              , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_4_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_5_RESERVED                              , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_5_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_6_RESERVED                              , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_6_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_7_RESERVED                              , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_7_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_8_RESERVED                              , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_8_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_9_RESERVED                              , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_9_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_10_RESERVED                             , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_10_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_11_RESERVED                             , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_11_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_12_RESERVED                             , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_12_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_13_RESERVED                             , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_13_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_14_RESERVED                             , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_14_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_15_RESERVED                             , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_TP_SEC_BUF_DRV_STRENGTH_DC              , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC );
+REG64_FLD( PERV_PERV_CTRL1_TP_SEC_BUF_DRV_STRENGTH_DC_LEN          , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC_LEN );
+REG64_FLD( PERV_PERV_CTRL1_20_RESERVED                             , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_20_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_21_RESERVED                             , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_21_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_22_RESERVED                             , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_23_RESERVED                             , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_24_RESERVED                             , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_24_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_TP_CLK_PULSE_ENABLE_DC                  , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_PULSE_ENABLE_DC );
+REG64_FLD( PERV_PERV_CTRL1_TP_CLK_PULSE_MODE_DC                    , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_PULSE_MODE_DC );
+REG64_FLD( PERV_PERV_CTRL1_TP_CLK_PULSE_MODE_DC_LEN                , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_PULSE_MODE_DC_LEN );
+REG64_FLD( PERV_PERV_CTRL1_TP_RESCLK_DIS_DC                        , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_RESCLK_DIS_DC );
+REG64_FLD( PERV_PERV_CTRL1_TP_CPM_CAL_SET                          , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CPM_CAL_SET );
+REG64_FLD( PERV_PERV_CTRL1_30_RESERVED                             , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_TP_PCB_PM_MUX_SEL_DC                    , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PCB_PM_MUX_SEL_DC );
+
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_UNUSED1                           , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1    );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_UNUSED2                           , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2    );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_UNUSED3                           , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED3    );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_3_RESERVED                        , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_3_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_4_RESERVED                        , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_4_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_5_RESERVED                        , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_5_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_6_RESERVED                        , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_6_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_7_RESERVED                        , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_7_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_8_RESERVED                        , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_8_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_9_RESERVED                        , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_9_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_10_RESERVED                       , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_10_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_11_RESERVED                       , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_11_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_12_RESERVED                       , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_12_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_13_RESERVED                       , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_13_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_14_RESERVED                       , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_14_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_15_RESERVED                       , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_SEC_BUF_DRV_STRENGTH_DC        , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_SEC_BUF_DRV_STRENGTH_DC_LEN    , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC_LEN );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_20_RESERVED                       , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_20_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_21_RESERVED                       , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_21_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_22_RESERVED                       , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_23_RESERVED                       , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_24_RESERVED                       , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_24_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_CLK_PULSE_ENABLE_DC            , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_PULSE_ENABLE_DC );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_CLK_PULSE_MODE_DC              , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_PULSE_MODE_DC );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_CLK_PULSE_MODE_DC_LEN          , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_PULSE_MODE_DC_LEN );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_RESCLK_DIS_DC                  , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_RESCLK_DIS_DC );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_CPM_CAL_SET                    , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CPM_CAL_SET );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_30_RESERVED                       , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_PCB_PM_MUX_SEL_DC              , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PCB_PM_MUX_SEL_DC );
+
+REG64_FLD( PERV_PERV_CTRL1_SET_UNUSED1                             , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1    );
+REG64_FLD( PERV_PERV_CTRL1_SET_UNUSED2                             , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2    );
+REG64_FLD( PERV_PERV_CTRL1_SET_UNUSED3                             , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED3    );
+REG64_FLD( PERV_PERV_CTRL1_SET_3_RESERVED                          , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_3_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_4_RESERVED                          , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_4_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_5_RESERVED                          , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_5_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_6_RESERVED                          , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_6_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_7_RESERVED                          , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_7_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_8_RESERVED                          , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_8_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_9_RESERVED                          , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_9_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_10_RESERVED                         , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_10_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_11_RESERVED                         , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_11_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_12_RESERVED                         , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_12_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_13_RESERVED                         , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_13_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_14_RESERVED                         , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_14_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_15_RESERVED                         , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_TP_SEC_BUF_DRV_STRENGTH_DC          , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC );
+REG64_FLD( PERV_PERV_CTRL1_SET_TP_SEC_BUF_DRV_STRENGTH_DC_LEN      , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC_LEN );
+REG64_FLD( PERV_PERV_CTRL1_SET_20_RESERVED                         , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_20_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_21_RESERVED                         , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_21_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_22_RESERVED                         , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_23_RESERVED                         , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_24_RESERVED                         , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_24_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_TP_CLK_PULSE_ENABLE_DC              , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_PULSE_ENABLE_DC );
+REG64_FLD( PERV_PERV_CTRL1_SET_TP_CLK_PULSE_MODE_DC                , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_PULSE_MODE_DC );
+REG64_FLD( PERV_PERV_CTRL1_SET_TP_CLK_PULSE_MODE_DC_LEN            , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_PULSE_MODE_DC_LEN );
+REG64_FLD( PERV_PERV_CTRL1_SET_TP_RESCLK_DIS_DC                    , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_RESCLK_DIS_DC );
+REG64_FLD( PERV_PERV_CTRL1_SET_TP_CPM_CAL                          , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CPM_CAL );
+REG64_FLD( PERV_PERV_CTRL1_SET_30_RESERVED                         , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_RESERVED );
+REG64_FLD( PERV_PERV_CTRL1_SET_TP_PCB_PM_MUX_SEL_DC                , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PCB_PM_MUX_SEL_DC );
+
+REG64_FLD( PERV_1_PRE_COUNTER_REG_COUNTER                          , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COUNTER    );
+REG64_FLD( PERV_1_PRE_COUNTER_REG_COUNTER_LEN                      , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_COUNTER_LEN );
+
+REG64_FLD( PERV_1_PROTECT_MODE_REG_READ_ENABLE                     , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_READ_ENABLE );
+REG64_FLD( PERV_1_PROTECT_MODE_REG_WRITE_ENABLE                    , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PCB_WDATA_PARITY );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY              , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_PARITY );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY          , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_DL_RETURN_P0                    , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_P0 );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_UL_RDATA_PARITY                 , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UL_RDATA_PARITY );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_UL_P0                           , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UL_P0      );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE     , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE           , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD             , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_WRITE_NVLD );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD              , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_READ_NVLD );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID           , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_ADDR_INVALID );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY              , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PCB_COMMAND_PARITY );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                 , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GENERAL_TIMEOUT );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PERV_1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( PERV_1_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR    , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR );
+REG64_FLD( PERV_1_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR   , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR );
+REG64_FLD( PERV_1_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR       , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR );
+REG64_FLD( PERV_1_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR );
+REG64_FLD( PERV_1_PSCOM_MODE_REG_WATCHDOG_ENABLE                   , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_WATCHDOG_ENABLE );
+REG64_FLD( PERV_1_PSCOM_MODE_REG_SCOM_HANG_LIMIT                   , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT );
+REG64_FLD( PERV_1_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN               , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT_LEN );
+REG64_FLD( PERV_1_PSCOM_MODE_REG_FORCE_ALL_RINGS                   , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ALL_RINGS );
+REG64_FLD( PERV_1_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8   , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE );
+REG64_FLD( PERV_1_PSCOM_MODE_REG_RESERVED_LT                       , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT );
+REG64_FLD( PERV_1_PSCOM_MODE_REG_RESERVED_LT_LEN                   , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT_LEN );
+
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_WDATA_PARITY );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0  , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_P0 );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_RDATA_PARITY );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0         , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_P0 );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6   , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_GENERAL_TIMEOUT );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY  , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_WDATA_PARITY );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_ADDRESS_PARITY );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0      , 21  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_P0 );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY   , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_RDATA_PARITY );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0             , 23  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_P0 );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_READ_NVLD );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_COMMAND_PARITY );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT   , 33  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_GENERAL_TIMEOUT );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG32_FLD( PERV_FSISHIFT_READ_BUFFER_REG                           , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG        );
+REG32_FLD( PERV_FSISHIFT_READ_BUFFER_REG_LEN                       , 32  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG_LEN    );
+
+REG64_FLD( PERV_REC_ACK_REG_RECEIVE_ACKNOWLEDGE_REGISTER           , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER );
+REG64_FLD( PERV_REC_ACK_REG_RECEIVE_ACKNOWLEDGE_REGISTER_LEN       , 64  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER_LEN );
+
+REG64_FLD( PERV_REC_ERR_REG0_MASTER_RESPONSE_BIT                   , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_MASTER_ERROR_CODE                     , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_MASTER_ERROR_CODE_LEN                 , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE1_RESPONSE_BIT                   , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE1_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE1_ERROR_CODE                     , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE1_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE1_ERROR_CODE_LEN                 , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE1_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE2_RESPONSE_BIT                   , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE2_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE2_ERROR_CODE                     , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE2_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE2_ERROR_CODE_LEN                 , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE2_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE3_RESPONSE_BIT                   , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE3_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE3_ERROR_CODE                     , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE3_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE3_ERROR_CODE_LEN                 , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE3_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE4_RESPONSE_BIT                   , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE4_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE4_ERROR_CODE                     , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE4_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE4_ERROR_CODE_LEN                 , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE4_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE5_RESPONSE_BIT                   , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE5_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE5_ERROR_CODE                     , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE5_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE5_ERROR_CODE_LEN                 , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE5_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE6_RESPONSE_BIT                   , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE6_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE6_ERROR_CODE                     , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE6_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE6_ERROR_CODE_LEN                 , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE6_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE7_RESPONSE_BIT                   , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE7_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE7_ERROR_CODE                     , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE7_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE7_ERROR_CODE_LEN                 , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE7_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE8_RESPONSE_BIT                   , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE8_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE8_ERROR_CODE                     , 33  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE8_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE8_ERROR_CODE_LEN                 , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE8_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE9_RESPONSE_BIT                   , 36  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE9_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE9_ERROR_CODE                     , 37  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE9_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE9_ERROR_CODE_LEN                 , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE9_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE10_RESPONSE_BIT                  , 40  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE10_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE10_ERROR_CODE                    , 41  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE10_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE10_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE10_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE11_RESPONSE_BIT                  , 44  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE11_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE11_ERROR_CODE                    , 45  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE11_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE11_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE11_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE12_RESPONSE_BIT                  , 48  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE12_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE12_ERROR_CODE                    , 49  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE12_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE12_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE12_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE13_RESPONSE_BIT                  , 52  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE13_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE13_ERROR_CODE                    , 53  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE13_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE13_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE13_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE14_RESPONSE_BIT                  , 56  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE14_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE14_ERROR_CODE                    , 57  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE14_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE14_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE14_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE15_RESPONSE_BIT                  , 60  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE15_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE15_ERROR_CODE                    , 61  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE15_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG0_SLAVE15_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE15_ERROR_CODE_LEN );
+
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE16_RESPONSE_BIT                  , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE16_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE16_ERROR_CODE                    , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE16_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE16_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE16_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE17_RESPONSE_BIT                  , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE17_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE17_ERROR_CODE                    , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE17_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE17_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE17_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE18_RESPONSE_BIT                  , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE18_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE18_ERROR_CODE                    , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE18_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE18_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE18_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE19_RESPONSE_BIT                  , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE19_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE19_ERROR_CODE                    , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE19_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE19_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE19_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE20_RESPONSE_BIT                  , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE20_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE20_ERROR_CODE                    , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE20_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE20_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE20_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE21_RESPONSE_BIT                  , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE21_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE21_ERROR_CODE                    , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE21_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE21_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE21_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE22_RESPONSE_BIT                  , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE22_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE22_ERROR_CODE                    , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE22_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE22_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE22_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE23_RESPONSE_BIT                  , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE23_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE23_ERROR_CODE                    , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE23_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE23_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE23_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE24_RESPONSE_BIT                  , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE24_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE24_ERROR_CODE                    , 33  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE24_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE24_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE24_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE25_RESPONSE_BIT                  , 36  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE25_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE25_ERROR_CODE                    , 37  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE25_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE25_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE25_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE26_RESPONSE_BIT                  , 40  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE26_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE26_ERROR_CODE                    , 41  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE26_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE26_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE26_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE27_RESPONSE_BIT                  , 44  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE27_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE27_ERROR_CODE                    , 45  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE27_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE27_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE27_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE28_RESPONSE_BIT                  , 48  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE28_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE28_ERROR_CODE                    , 49  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE28_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE28_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE28_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE29_RESPONSE_BIT                  , 52  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE29_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE29_ERROR_CODE                    , 53  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE29_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE29_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE29_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE30_RESPONSE_BIT                  , 56  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE30_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE30_ERROR_CODE                    , 57  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE30_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE30_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE30_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE31_RESPONSE_BIT                  , 60  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE31_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE31_ERROR_CODE                    , 61  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE31_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG1_SLAVE31_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE31_ERROR_CODE_LEN );
+
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE32_RESPONSE_BIT                  , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE32_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE32_ERROR_CODE                    , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE32_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE32_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE32_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE33_RESPONSE_BIT                  , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE33_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE33_ERROR_CODE                    , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE33_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE33_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE33_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE34_RESPONSE_BIT                  , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE34_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE34_ERROR_CODE                    , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE34_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE34_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE34_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE35_RESPONSE_BIT                  , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE35_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE35_ERROR_CODE                    , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE35_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE35_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE35_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE36_RESPONSE_BIT                  , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE36_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE36_ERROR_CODE                    , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE36_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE36_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE36_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE37_RESPONSE_BIT                  , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE37_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE37_ERROR_CODE                    , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE37_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE37_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE37_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE38_RESPONSE_BIT                  , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE38_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE38_ERROR_CODE                    , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE38_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE38_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE38_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE39_RESPONSE_BIT                  , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE39_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE39_ERROR_CODE                    , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE39_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE39_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE39_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE40_RESPONSE_BIT                  , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE40_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE40_ERROR_CODE                    , 33  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE40_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE40_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE40_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE41_RESPONSE_BIT                  , 36  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE41_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE41_ERROR_CODE                    , 37  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE41_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE41_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE41_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE42_RESPONSE_BIT                  , 40  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE42_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE42_ERROR_CODE                    , 41  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE42_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE42_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE42_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE43_RESPONSE_BIT                  , 44  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE43_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE43_ERROR_CODE                    , 45  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE43_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE43_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE43_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE44_RESPONSE_BIT                  , 48  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE44_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE44_ERROR_CODE                    , 49  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE44_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE44_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE44_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE45_RESPONSE_BIT                  , 52  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE45_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE45_ERROR_CODE                    , 53  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE45_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE45_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE45_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE46_RESPONSE_BIT                  , 56  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE46_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE46_ERROR_CODE                    , 57  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE46_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE46_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE46_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE47_RESPONSE_BIT                  , 60  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE47_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE47_ERROR_CODE                    , 61  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE47_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG2_SLAVE47_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE47_ERROR_CODE_LEN );
+
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE48_RESPONSE_BIT                  , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE48_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE48_ERROR_CODE                    , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE48_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE48_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE48_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE49_RESPONSE_BIT                  , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE49_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE49_ERROR_CODE                    , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE49_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE49_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE49_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE50_RESPONSE_BIT                  , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE50_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE50_ERROR_CODE                    , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE50_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE50_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE50_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE51_RESPONSE_BIT                  , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE51_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE51_ERROR_CODE                    , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE51_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE51_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE51_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE52_RESPONSE_BIT                  , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE52_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE52_ERROR_CODE                    , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE52_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE52_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE52_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE53_RESPONSE_BIT                  , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE53_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE53_ERROR_CODE                    , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE53_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE53_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE53_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE54_RESPONSE_BIT                  , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE54_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE54_ERROR_CODE                    , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE54_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE54_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE54_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE55_RESPONSE_BIT                  , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE55_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE55_ERROR_CODE                    , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE55_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE55_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE55_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE56_RESPONSE_BIT                  , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE56_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE56_ERROR_CODE                    , 33  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE56_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE56_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE56_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE57_RESPONSE_BIT                  , 36  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE57_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE57_ERROR_CODE                    , 37  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE57_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE57_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE57_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE58_RESPONSE_BIT                  , 40  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE58_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE58_ERROR_CODE                    , 41  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE58_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE58_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE58_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE59_RESPONSE_BIT                  , 44  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE59_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE59_ERROR_CODE                    , 45  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE59_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE59_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE59_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE60_RESPONSE_BIT                  , 48  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE60_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE60_ERROR_CODE                    , 49  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE60_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE60_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE60_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE61_RESPONSE_BIT                  , 52  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE61_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE61_ERROR_CODE                    , 53  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE61_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE61_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE61_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE62_RESPONSE_BIT                  , 56  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE62_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE62_ERROR_CODE                    , 57  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE62_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE62_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE62_ERROR_CODE_LEN );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE63_RESPONSE_BIT                  , 60  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE63_RESPONSE_BIT );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE63_ERROR_CODE                    , 61  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE63_ERROR_CODE );
+REG64_FLD( PERV_REC_ERR_REG3_SLAVE63_ERROR_CODE_LEN                , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE63_ERROR_CODE_LEN );
+
+REG64_FLD( PERV_RESET_REG_PCB                                      , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PCB        );
+REG64_FLD( PERV_RESET_REG_ENDPOINTS                                , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_ENDPOINTS  );
+REG64_FLD( PERV_RESET_REG_TIMEOUT_EN                               , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_EN );
+
+REG32_FLD( PERV_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH_A_RESID_FE_LEN_0 , 0   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_RESID_FE_LEN_0 );
+REG32_FLD( PERV_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH_A_RESID_FE_LEN_0_LEN , 16  , SH_UNT_PERV_FSII2C,
+           SH_ACS_SCOM     , SH_FLD_RESID_FE_LEN_0_LEN );
+
+REG64_FLD( PERV_1_RFIR_IN0                                         , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( PERV_1_RFIR_LFIR_RECOV_ERR                              , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_LFIR_RECOV_ERR );
+REG64_FLD( PERV_1_RFIR_IN4                                         , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( PERV_1_RFIR_IN5                                         , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( PERV_1_RFIR_IN6                                         , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN6        );
+REG64_FLD( PERV_1_RFIR_IN7                                         , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN7        );
+REG64_FLD( PERV_1_RFIR_IN8                                         , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN8        );
+REG64_FLD( PERV_1_RFIR_IN9                                         , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN9        );
+REG64_FLD( PERV_1_RFIR_IN10                                        , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN10       );
+REG64_FLD( PERV_1_RFIR_IN11                                        , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN11       );
+REG64_FLD( PERV_1_RFIR_IN12                                        , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN12       );
+REG64_FLD( PERV_1_RFIR_IN13                                        , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN13       );
+REG64_FLD( PERV_1_RFIR_IN14                                        , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN14       );
+REG64_FLD( PERV_1_RFIR_IN15                                        , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN15       );
+REG64_FLD( PERV_1_RFIR_IN16                                        , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN16       );
+REG64_FLD( PERV_1_RFIR_IN17                                        , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN17       );
+REG64_FLD( PERV_1_RFIR_IN18                                        , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN18       );
+REG64_FLD( PERV_1_RFIR_IN19                                        , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN19       );
+REG64_FLD( PERV_1_RFIR_IN20                                        , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN20       );
+REG64_FLD( PERV_1_RFIR_IN21                                        , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN21       );
+REG64_FLD( PERV_1_RFIR_IN21_LEN                                    , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN21_LEN   );
+
+REG64_FLD( PERV_1_RING_FENCE_MASK_LATCH_REG_DISABLED               , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED   );
+REG64_FLD( PERV_1_RING_FENCE_MASK_LATCH_REG_ENABLE                 , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( PERV_1_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN             , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( PERV_ROOT_CTRL0_FENCE0_DC                               , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_TPFSI_TP_FENCE_VTLIO_DC                 , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_FENCE_VTLIO_DC );
+REG64_FLD( PERV_ROOT_CTRL0_TPFSI_TPI2C_BUS_FENCE_DC                , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TPI2C_BUS_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_TPCFSI_OPB_SW0_FENCE_DC                 , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPCFSI_OPB_SW0_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_TPCFSI_OPB_SW0_FENCE_DC_LEN             , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPCFSI_OPB_SW0_FENCE_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL0_TPCFSI_OPB_SW1_FENCE_DC                 , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPCFSI_OPB_SW1_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_TPCFSI_OPB_SW1_FENCE_DC_LEN             , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPCFSI_OPB_SW1_FENCE_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL0_FENCE1_DC                               , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_FENCE2_DC                               , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE2_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_FENCE3_DC                               , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE3_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_FENCE4_DC                               , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE4_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_FENCE5_DC                               , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE5_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_FENCE6_DC                               , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE6_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_SPARE_FENCE_CONTROL                     , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_FENCE_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_VDD2VIO_LVL_FENCE_DC                    , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_VDD2VIO_LVL_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_PIB2PCB_DC                              , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PIB2PCB_DC );
+REG64_FLD( PERV_ROOT_CTRL0_OOB_MUX                                 , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OOB_MUX    );
+REG64_FLD( PERV_ROOT_CTRL0_18_SPARE_MUX_CONTROL                    , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_18_SPARE_MUX_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_19_SPARE_MUX_CONTROL                    , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_19_SPARE_MUX_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_FSI_CC_VSB_CBS_REQ                      , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FSI_CC_VSB_CBS_REQ );
+REG64_FLD( PERV_ROOT_CTRL0_FSI_CC_VSB_CBS_CMD                      , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FSI_CC_VSB_CBS_CMD );
+REG64_FLD( PERV_ROOT_CTRL0_FSI_CC_VSB_CBS_CMD_LEN                  , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FSI_CC_VSB_CBS_CMD_LEN );
+REG64_FLD( PERV_ROOT_CTRL0_24_SPARE_CBS_CONTROL                    , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_24_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_25_SPARE_CBS_CONTROL                    , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_25_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_26_SPARE_CBS_CONTROL                    , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_27_SPARE_CBS_CONTROL                    , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_27_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_28_SPARE_RESET                          , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_SPARE_RESET );
+REG64_FLD( PERV_ROOT_CTRL0_29_SPARE_RESET                          , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_SPARE_RESET );
+REG64_FLD( PERV_ROOT_CTRL0_PCB_RESET_DC                            , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PCB_RESET_DC );
+REG64_FLD( PERV_ROOT_CTRL0_GLOBAL_EP_RESET_DC                      , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GLOBAL_EP_RESET_DC );
+
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FENCE0_DC                         , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_TPFSI_TP_FENCE_VTLIO_DC           , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_FENCE_VTLIO_DC );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_TPFSI_TPI2C_BUS_FENCE_DC          , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TPI2C_BUS_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_TPCFSI_OPB_SW0_FENCE_DC           , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPCFSI_OPB_SW0_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_TPCFSI_OPB_SW0_FENCE_DC_LEN       , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPCFSI_OPB_SW0_FENCE_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_TPCFSI_OPB_SW1_FENCE_DC           , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPCFSI_OPB_SW1_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_TPCFSI_OPB_SW1_FENCE_DC_LEN       , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPCFSI_OPB_SW1_FENCE_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FENCE1_DC                         , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FENCE2_DC                         , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE2_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FENCE3_DC                         , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE3_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FENCE4_DC                         , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE4_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FENCE5_DC                         , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE5_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FENCE6_DC                         , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE6_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_SPARE_FENCE_CONTROL               , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_FENCE_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_VDD2VIO_LVL_FENCE_DC              , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_VDD2VIO_LVL_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_PIB2PCB_DC                        , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PIB2PCB_DC );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_OOB_MUX                           , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OOB_MUX    );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_18_SPARE_MUX_CONTROL              , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_18_SPARE_MUX_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_19_SPARE_MUX_CONTROL              , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_19_SPARE_MUX_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FSI_CC_VSB_CBS_REQ                , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FSI_CC_VSB_CBS_REQ );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FSI_CC_VSB_CBS_CMD                , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FSI_CC_VSB_CBS_CMD );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FSI_CC_VSB_CBS_CMD_LEN            , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FSI_CC_VSB_CBS_CMD_LEN );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_24_SPARE_CBS_CONTROL              , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_24_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_25_SPARE_CBS_CONTROL              , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_25_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_26_SPARE_CBS_CONTROL              , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_27_SPARE_CBS_CONTROL              , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_27_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_28_SPARE_RESET                    , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_SPARE_RESET );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_29_SPARE_RESET                    , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_SPARE_RESET );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_PCB_RESET_DC                      , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PCB_RESET_DC );
+REG64_FLD( PERV_ROOT_CTRL0_CLEAR_GLOBAL_EP_RESET_DC                , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GLOBAL_EP_RESET_DC );
+
+REG64_FLD( PERV_ROOT_CTRL0_SET_FENCE0_DC                           , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE0_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_SET_TPFSI_TP_FENCE_VTLIO_DC             , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_FENCE_VTLIO_DC );
+REG64_FLD( PERV_ROOT_CTRL0_SET_TPFSI_TPI2C_BUS_FENCE_DC            , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TPI2C_BUS_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_SET_TPCFSI_OPB_SW0_FENCE_DC             , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPCFSI_OPB_SW0_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_SET_TPCFSI_OPB_SW0_FENCE_DC_LEN         , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPCFSI_OPB_SW0_FENCE_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL0_SET_TPCFSI_OPB_SW1_FENCE_DC             , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPCFSI_OPB_SW1_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_SET_TPCFSI_OPB_SW1_FENCE_DC_LEN         , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPCFSI_OPB_SW1_FENCE_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL0_SET_FENCE1_DC                           , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE1_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_SET_FENCE2_DC                           , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE2_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_SET_FENCE3_DC                           , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE3_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_SET_FENCE4_DC                           , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE4_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_SET_FENCE5_DC                           , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE5_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_SET_FENCE6_DC                           , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FENCE6_DC  );
+REG64_FLD( PERV_ROOT_CTRL0_SET_SPARE_FENCE_CONTROL                 , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_FENCE_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_SET_VDD2VIO_LVL_FENCE_DC                , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_VDD2VIO_LVL_FENCE_DC );
+REG64_FLD( PERV_ROOT_CTRL0_SET_PIB2PCB_DC                          , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PIB2PCB_DC );
+REG64_FLD( PERV_ROOT_CTRL0_SET_OOB_MUX                             , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OOB_MUX    );
+REG64_FLD( PERV_ROOT_CTRL0_SET_18_SPARE_MUX_CONTROL                , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_18_SPARE_MUX_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_SET_19_SPARE_MUX_CONTROL                , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_19_SPARE_MUX_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_SET_FSI_CC_VSB_CBS_REQ                  , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FSI_CC_VSB_CBS_REQ );
+REG64_FLD( PERV_ROOT_CTRL0_SET_FSI_CC_VSB_CBS_CMD                  , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FSI_CC_VSB_CBS_CMD );
+REG64_FLD( PERV_ROOT_CTRL0_SET_FSI_CC_VSB_CBS_CMD_LEN              , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FSI_CC_VSB_CBS_CMD_LEN );
+REG64_FLD( PERV_ROOT_CTRL0_SET_24_SPARE_CBS_CONTROL                , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_24_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_SET_25_SPARE_CBS_CONTROL                , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_25_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_SET_26_SPARE_CBS_CONTROL                , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_SET_27_SPARE_CBS_CONTROL                , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_27_SPARE_CBS_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL0_SET_28_SPARE_RESET                      , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_SPARE_RESET );
+REG64_FLD( PERV_ROOT_CTRL0_SET_29_SPARE_RESET                      , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_SPARE_RESET );
+REG64_FLD( PERV_ROOT_CTRL0_SET_PCB_RESET_DC                        , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PCB_RESET_DC );
+REG64_FLD( PERV_ROOT_CTRL0_SET_GLOBAL_EP_RESET_DC                  , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GLOBAL_EP_RESET_DC );
+
+REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE0_SEL_DC                        , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE0_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE0_SEL_DC_LEN                    , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE0_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE1_SEL_DC                        , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE1_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE1_SEL_DC_LEN                    , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE1_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE_MESH_SEL_DC                    , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE_MESH_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE_DRV_EN_DC                      , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE_DRV_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE_HIGHDRIVE_DC                   , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE_HIGHDRIVE_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TP_FSI_PROBE_SEL_DC                     , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FSI_PROBE_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TP_FSI_PROBE_SEL_DC_LEN                 , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FSI_PROBE_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL1_13_SPARE_PROBE                          , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_13_SPARE_PROBE );
+REG64_FLD( PERV_ROOT_CTRL1_14_SPARE_PROBE                          , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_14_SPARE_PROBE );
+REG64_FLD( PERV_ROOT_CTRL1_15_SPARE_PROBE                          , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_SPARE_PROBE );
+REG64_FLD( PERV_ROOT_CTRL1_TP_IDDQ_DC                              , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_IDDQ_DC );
+REG64_FLD( PERV_ROOT_CTRL1_SPARE_RI_CONTROL                        , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_RI_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_SPARE_DI_CONTROL                        , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_DI_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_TP_RI_DC_B                              , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_RI_DC_B );
+REG64_FLD( PERV_ROOT_CTRL1_TP_DI1_DC_B                             , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_DI1_DC_B );
+REG64_FLD( PERV_ROOT_CTRL1_TP_DI2_DC_B                             , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_DI2_DC_B );
+REG64_FLD( PERV_ROOT_CTRL1_22_SPARE_TEST                           , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_SPARE_TEST );
+REG64_FLD( PERV_ROOT_CTRL1_23_SPARE_TEST                           , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_SPARE_TEST );
+REG64_FLD( PERV_ROOT_CTRL1_TP_TEST_BURNIN_MODE_DC                  , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_TEST_BURNIN_MODE_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TPFSI_ARRAY_SET_VBL_TO_VDD_DC           , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_ARRAY_SET_VBL_TO_VDD_DC );
+REG64_FLD( PERV_ROOT_CTRL1_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED   , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED );
+REG64_FLD( PERV_ROOT_CTRL1_TP_GLBCK_MEM_TESTCLK_SEL_DC             , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_MEM_TESTCLK_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_28_SPARE_TEST_CONTROL                   , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_SPARE_TEST_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_29_SPARE_TEST_CONTROL                   , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_SPARE_TEST_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_30_SPARE_TEST_CONTROL                   , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_SPARE_TEST_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_31_SPARE_TEST_CONTROL                   , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_31_SPARE_TEST_CONTROL );
+
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_PROBE0_SEL_DC                  , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE0_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_PROBE0_SEL_DC_LEN              , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE0_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_PROBE1_SEL_DC                  , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE1_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_PROBE1_SEL_DC_LEN              , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE1_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_PROBE_MESH_SEL_DC              , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE_MESH_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_PROBE_DRV_EN_DC                , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE_DRV_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_PROBE_HIGHDRIVE_DC             , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE_HIGHDRIVE_DC );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_FSI_PROBE_SEL_DC               , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FSI_PROBE_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_FSI_PROBE_SEL_DC_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FSI_PROBE_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_13_SPARE_PROBE                    , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_13_SPARE_PROBE );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_14_SPARE_PROBE                    , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_14_SPARE_PROBE );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_15_SPARE_PROBE                    , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_SPARE_PROBE );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_IDDQ_DC                        , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_IDDQ_DC );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_SPARE_RI_CONTROL                  , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_RI_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_SPARE_DI_CONTROL                  , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_DI_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_RI_DC_B                        , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_RI_DC_B );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_DI1_DC_B                       , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_DI1_DC_B );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_DI2_DC_B                       , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_DI2_DC_B );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_22_SPARE_TEST                     , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_SPARE_TEST );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_23_SPARE_TEST                     , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_SPARE_TEST );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_TEST_BURNIN_MODE_DC            , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_TEST_BURNIN_MODE_DC );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TPFSI_ARRAY_SET_VBL_TO_VDD_DC     , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_ARRAY_SET_VBL_TO_VDD_DC );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_GLBCK_MEM_TESTCLK_SEL_DC       , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_MEM_TESTCLK_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_28_SPARE_TEST_CONTROL             , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_SPARE_TEST_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_29_SPARE_TEST_CONTROL             , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_SPARE_TEST_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_30_SPARE_TEST_CONTROL             , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_SPARE_TEST_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_CLEAR_31_SPARE_TEST_CONTROL             , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_31_SPARE_TEST_CONTROL );
+
+REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE0_SEL_DC                    , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE0_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE0_SEL_DC_LEN                , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE0_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE1_SEL_DC                    , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE1_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE1_SEL_DC_LEN                , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE1_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE_MESH_SEL_DC                , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE_MESH_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE_DRV_EN_DC                  , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE_DRV_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE_HIGHDRIVE_DC               , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PROBE_HIGHDRIVE_DC );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TP_FSI_PROBE_SEL_DC                 , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FSI_PROBE_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TP_FSI_PROBE_SEL_DC_LEN             , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FSI_PROBE_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL1_SET_13_SPARE_PROBE                      , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_13_SPARE_PROBE );
+REG64_FLD( PERV_ROOT_CTRL1_SET_14_SPARE_PROBE                      , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_14_SPARE_PROBE );
+REG64_FLD( PERV_ROOT_CTRL1_SET_15_SPARE_PROBE                      , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_SPARE_PROBE );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TP_IDDQ_DC                          , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_IDDQ_DC );
+REG64_FLD( PERV_ROOT_CTRL1_SET_SPARE_RI_CONTROL                    , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_RI_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_SET_SPARE_DI_CONTROL                    , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_DI_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TP_RI_DC_B                          , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_RI_DC_B );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TP_DI1_DC_B                         , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_DI1_DC_B );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TP_DI2_DC_B                         , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_DI2_DC_B );
+REG64_FLD( PERV_ROOT_CTRL1_SET_22_SPARE_TEST                       , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_SPARE_TEST );
+REG64_FLD( PERV_ROOT_CTRL1_SET_23_SPARE_TEST                       , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_SPARE_TEST );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TP_TEST_BURNIN_MODE_DC              , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_TEST_BURNIN_MODE_DC );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TPFSI_ARRAY_VBL_TO_VDD_DC           , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_ARRAY_VBL_TO_VDD_DC );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED );
+REG64_FLD( PERV_ROOT_CTRL1_SET_TP_GLBCK_MEM_TESTCLK_SEL_DC         , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_MEM_TESTCLK_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL1_SET_28_SPARE_TEST_CONTROL               , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_SPARE_TEST_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_SET_29_SPARE_TEST_CONTROL               , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_SPARE_TEST_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_SET_30_SPARE_TEST_CONTROL               , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_SPARE_TEST_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL1_SET_31_SPARE_TEST_CONTROL               , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_31_SPARE_TEST_CONTROL );
+
+REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC        , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC    , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC    , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC    , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TP_PIB_VSB_DISABLE_PARITY_DC            , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PIB_VSB_DISABLE_PARITY_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TP_PIB_TRACE_MODE_DATA_DC               , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PIB_TRACE_MODE_DATA_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TP_PIB_VSB_SBE_TRACE_MODE               , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PIB_VSB_SBE_TRACE_MODE );
+REG64_FLD( PERV_ROOT_CTRL2_TP_TPCPERV_VSB_TRACE_STOP               , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_TPCPERV_VSB_TRACE_STOP );
+REG64_FLD( PERV_ROOT_CTRL2_TP_GPIO_PIB_TIMEOUT                     , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GPIO_PIB_TIMEOUT );
+REG64_FLD( PERV_ROOT_CTRL2_TP_GPIO_PIB_TIMEOUT_LEN                 , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GPIO_PIB_TIMEOUT_LEN );
+REG64_FLD( PERV_ROOT_CTRL2_SPARE_PIB_CONTROL                       , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_PIB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_TPCFSI_OPB_SW_RESET_DC                  , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPCFSI_OPB_SW_RESET_DC );
+REG64_FLD( PERV_ROOT_CTRL2_13_SPARE_OPB_CONTROL                    , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_13_SPARE_OPB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_14_SPARE_OPB_CONTROL                    , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_14_SPARE_OPB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_15_SPARE_OPB_CONTROL                    , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_SPARE_OPB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_EDRAM_CTRL_GATE                , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_EDRAM_CTRL_GATE );
+REG64_FLD( PERV_ROOT_CTRL2_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC    , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_PFET_FORCE_OFF_DC              , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_PFET_FORCE_OFF_DC );
+REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_PFET_OVERRIDE_ON_DC_N          , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_PFET_OVERRIDE_ON_DC_N );
+REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TC_HSSPORWREN_ALLOW               , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TC_HSSPORWREN_ALLOW );
+REG64_FLD( PERV_ROOT_CTRL2_21_FREE_USAGE                           , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_21_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_22_FREE_USAGE                           , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_23_FREE_USAGE                           , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_TP_IO_VSB_OP0A_V1P8_EN                  , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_IO_VSB_OP0A_V1P8_EN );
+REG64_FLD( PERV_ROOT_CTRL2_TP_IO_VSB_OP0B_V1P8_EN                  , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_IO_VSB_OP0B_V1P8_EN );
+REG64_FLD( PERV_ROOT_CTRL2_26_FREE_USAGE                           , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_27_FREE_USAGE                           , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_27_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_28_FREE_USAGE                           , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_29_FREE_USAGE                           , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_TP_IO_VSB_OP3A_V1P8_EN                  , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_IO_VSB_OP3A_V1P8_EN );
+REG64_FLD( PERV_ROOT_CTRL2_TP_IO_VSB_OP3B_V1P8_EN                  , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_IO_VSB_OP3B_V1P8_EN );
+
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC  , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_PIB_VSB_DISABLE_PARITY_DC      , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PIB_VSB_DISABLE_PARITY_DC );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_PIB_TRACE_MODE_DATA_DC         , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PIB_TRACE_MODE_DATA_DC );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_PIB_VSB_SBE_TRACE_MODE         , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PIB_VSB_SBE_TRACE_MODE );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_TPCPERV_VSB_TRACE_STOP         , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_TPCPERV_VSB_TRACE_STOP );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_GPIO_PIB_TIMEOUT               , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GPIO_PIB_TIMEOUT );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_GPIO_PIB_TIMEOUT_LEN           , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GPIO_PIB_TIMEOUT_LEN );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_SPARE_PIB_CONTROL                 , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_PIB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPCFSI_OPB_SW_RESET_DC            , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPCFSI_OPB_SW_RESET_DC );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_13_SPARE_OPB_CONTROL              , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_13_SPARE_OPB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_14_SPARE_OPB_CONTROL              , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_14_SPARE_OPB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_15_SPARE_OPB_CONTROL              , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_SPARE_OPB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_EDRAM_CTRL_GATE          , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_EDRAM_CTRL_GATE );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_PFET_FORCE_OFF_DC        , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_PFET_FORCE_OFF_DC );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_PFET_OVERRIDE_ON_DC_N    , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_PFET_OVERRIDE_ON_DC_N );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPFSI_TC_HSSPORWREN_ALLOW         , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TC_HSSPORWREN_ALLOW );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_21_FREE_USAGE                     , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_21_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_22_FREE_USAGE                     , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_23_FREE_USAGE                     , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_IO_VSB_OP0A_V1P8_EN            , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_IO_VSB_OP0A_V1P8_EN );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_IO_VSB_OP0B_V1P8_EN            , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_IO_VSB_OP0B_V1P8_EN );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_26_FREE_USAGE                     , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_27_FREE_USAGE                     , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_27_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_28_FREE_USAGE                     , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_29_FREE_USAGE                     , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_IO_VSB_OP3A_V1P8_EN            , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_IO_VSB_OP3A_V1P8_EN );
+REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_IO_VSB_OP3B_V1P8_EN            , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_IO_VSB_OP3B_V1P8_EN );
+
+REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC    , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TP_PIB_VSB_DISABLE_PARITY_DC        , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PIB_VSB_DISABLE_PARITY_DC );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TP_PIB_TRACE_MODE_DATA_DC           , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PIB_TRACE_MODE_DATA_DC );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TP_PIB_VSB_SBE_TRACE_MODE           , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PIB_VSB_SBE_TRACE_MODE );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TP_TPCPERV_VSB_TRACE_STOP           , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_TPCPERV_VSB_TRACE_STOP );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TP_GPIO_PIB_TIMEOUT                 , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GPIO_PIB_TIMEOUT );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TP_GPIO_PIB_TIMEOUT_LEN             , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GPIO_PIB_TIMEOUT_LEN );
+REG64_FLD( PERV_ROOT_CTRL2_SET_SPARE_PIB_CONTROL                   , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_PIB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TPCFSI_OPB_SW_RESET_DC              , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPCFSI_OPB_SW_RESET_DC );
+REG64_FLD( PERV_ROOT_CTRL2_SET_13_SPARE_OPB_CONTROL                , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_13_SPARE_OPB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_SET_14_SPARE_OPB_CONTROL                , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_14_SPARE_OPB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_SET_15_SPARE_OPB_CONTROL                , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_SPARE_OPB_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TP_EDRAM_CTRL_GATE            , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_EDRAM_CTRL_GATE );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TP_PFET_FORCE_OFF_DC          , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_PFET_FORCE_OFF_DC );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TP_PFET_OVERRIDE_ON_DC_N      , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TP_PFET_OVERRIDE_ON_DC_N );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TC_HSSPORWREN_ALLOW           , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_TC_HSSPORWREN_ALLOW );
+REG64_FLD( PERV_ROOT_CTRL2_SET_21_FREE_USAGE                       , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_21_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_SET_22_FREE_USAGE                       , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_SET_23_FREE_USAGE                       , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TP_IO_VSB_OP0A_V1P8_EN              , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_IO_VSB_OP0A_V1P8_EN );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TP_IO_VSB_OP0B_V1P8_EN              , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_IO_VSB_OP0B_V1P8_EN );
+REG64_FLD( PERV_ROOT_CTRL2_SET_26_FREE_USAGE                       , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_SET_27_FREE_USAGE                       , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_27_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_SET_28_FREE_USAGE                       , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_SET_29_FREE_USAGE                       , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_FREE_USAGE );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TP_IO_VSB_OP3A_V1P8_EN              , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_IO_VSB_OP3A_V1P8_EN );
+REG64_FLD( PERV_ROOT_CTRL2_SET_TP_IO_VSB_OP3B_V1P8_EN              , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_IO_VSB_OP3B_V1P8_EN );
+
+REG64_FLD( PERV_ROOT_CTRL3_OSCSWITCH_CNTL0_DC                      , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OSCSWITCH_CNTL0_DC );
+REG64_FLD( PERV_ROOT_CTRL3_OSCSWITCH_CNTL0_DC_LEN                  , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OSCSWITCH_CNTL0_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL3_TP_GLBCK_VSB_PCIESW_USEOSC_DC           , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC );
+REG64_FLD( PERV_ROOT_CTRL3_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN       , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL3_TP_GLBCK_VSB_PCIESW_TWEAK_DC            , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC );
+REG64_FLD( PERV_ROOT_CTRL3_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN        , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL3_OSCSWITCH_CNTL1_DC                      , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OSCSWITCH_CNTL1_DC );
+REG64_FLD( PERV_ROOT_CTRL3_OSCSWITCH_CNTL1_DC_LEN                  , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OSCSWITCH_CNTL1_DC_LEN );
+
+REG64_FLD( PERV_ROOT_CTRL3_CLEAR_OSCSWITCH_CNTL0_DC                , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OSCSWITCH_CNTL0_DC );
+REG64_FLD( PERV_ROOT_CTRL3_CLEAR_OSCSWITCH_CNTL0_DC_LEN            , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OSCSWITCH_CNTL0_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL3_CLEAR_TP_GLBCK_VSB_PCIESW_USEOSC_DC     , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC );
+REG64_FLD( PERV_ROOT_CTRL3_CLEAR_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL3_CLEAR_TP_GLBCK_VSB_PCIESW_TWEAK_DC      , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC );
+REG64_FLD( PERV_ROOT_CTRL3_CLEAR_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN  , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL3_CLEAR_OSCSWITCH_CNTL1_DC                , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OSCSWITCH_CNTL1_DC );
+REG64_FLD( PERV_ROOT_CTRL3_CLEAR_OSCSWITCH_CNTL1_DC_LEN            , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OSCSWITCH_CNTL1_DC_LEN );
+
+REG64_FLD( PERV_ROOT_CTRL3_SET_OSCSWITCH_CNTL0_DC                  , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OSCSWITCH_CNTL0_DC );
+REG64_FLD( PERV_ROOT_CTRL3_SET_OSCSWITCH_CNTL0_DC_LEN              , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OSCSWITCH_CNTL0_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL3_SET_TP_GLBCK_VSB_PCIESW_USEOSC_DC       , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC );
+REG64_FLD( PERV_ROOT_CTRL3_SET_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN   , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL3_SET_TP_GLBCK_VSB_PCIESW_TWEAK_DC        , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC );
+REG64_FLD( PERV_ROOT_CTRL3_SET_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN    , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL3_SET_OSCSWITCH_CNTL1_DC                  , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OSCSWITCH_CNTL1_DC );
+REG64_FLD( PERV_ROOT_CTRL3_SET_OSCSWITCH_CNTL1_DC_LEN              , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_OSCSWITCH_CNTL1_DC_LEN );
+
+REG64_FLD( PERV_ROOT_CTRL4_TP_OSCSWITCH_VSB                        , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_OSCSWITCH_VSB );
+REG64_FLD( PERV_ROOT_CTRL4_TP_OSCSWITCH_VSB_LEN                    , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_OSCSWITCH_VSB_LEN );
+
+REG64_FLD( PERV_ROOT_CTRL4_CLEAR_TP_OSCSWITCH_VSB                  , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_OSCSWITCH_VSB );
+REG64_FLD( PERV_ROOT_CTRL4_CLEAR_TP_OSCSWITCH_VSB_LEN              , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_OSCSWITCH_VSB_LEN );
+
+REG64_FLD( PERV_ROOT_CTRL4_SET_TP_OSCSWITCH_VSB                    , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_OSCSWITCH_VSB );
+REG64_FLD( PERV_ROOT_CTRL4_SET_TP_OSCSWITCH_VSB_LEN                , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_OSCSWITCH_VSB_LEN );
+
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_ERRINJ0_DC                  , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_ERRINJ0_DC );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_ERRINJ0_DC_LEN              , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_ERRINJ0_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_ERRINJ1_DC                  , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_ERRINJ1_DC );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_ERRINJ1_DC_LEN              , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_ERRINJ1_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_TWEAK_DC                    , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_TWEAK_DC );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_TWEAK_DC_LEN                , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_TWEAK_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_SKEW_ADJUST_DC              , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN          , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_SNS_CONTENT_SEL_DC          , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN      , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_15_SPARE_OSC                            , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_16_SPARE_OSC                            , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_16_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_17_SPARE_OSC                            , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_17_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_18_SPARE_OSC                            , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_18_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_19_SPARE_OSC                            , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_19_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_20_SPARE_OSC                            , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_20_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_21_SPARE_OSC                            , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_21_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_22_SPARE_OSC                            , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_23_SPARE_OSC                            , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_24_SPARE_OSC                            , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_24_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_25_SPARE_OSC                            , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_25_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_26_SPARE_OSC                            , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_27_SPARE_OSC                            , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_27_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_28_SPARE_OSC                            , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_29_SPARE_OSC                            , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_30_SPARE_OSC                            , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_31_SPARE_OSC                            , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_31_SPARE_OSC );
+
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_ERRINJ0_DC            , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_ERRINJ0_DC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_ERRINJ0_DC_LEN        , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_ERRINJ0_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_ERRINJ1_DC            , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_ERRINJ1_DC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_ERRINJ1_DC_LEN        , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_ERRINJ1_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_TWEAK_DC              , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_TWEAK_DC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_TWEAK_DC_LEN          , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_TWEAK_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_SKEW_ADJUST_DC        , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN    , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_SNS_CONTENT_SEL_DC    , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_15_SPARE_OSC                      , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_16_SPARE_OSC                      , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_16_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_17_SPARE_OSC                      , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_17_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_18_SPARE_OSC                      , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_18_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_19_SPARE_OSC                      , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_19_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_20_SPARE_OSC                      , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_20_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_21_SPARE_OSC                      , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_21_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_22_SPARE_OSC                      , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_23_SPARE_OSC                      , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_24_SPARE_OSC                      , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_24_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_25_SPARE_OSC                      , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_25_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_26_SPARE_OSC                      , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_27_SPARE_OSC                      , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_27_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_28_SPARE_OSC                      , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_29_SPARE_OSC                      , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_30_SPARE_OSC                      , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_CLEAR_31_SPARE_OSC                      , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_31_SPARE_OSC );
+
+REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_ERRINJ0_DC              , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_ERRINJ0_DC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_ERRINJ0_DC_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_ERRINJ0_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_ERRINJ1_DC              , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_ERRINJ1_DC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_ERRINJ1_DC_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_ERRINJ1_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_TWEAK_DC                , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_TWEAK_DC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_TWEAK_DC_LEN            , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_TWEAK_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_SKEW_ADJUST_DC          , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN      , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_SNS_CONTENT_SEL_DC      , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN  , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL5_SET_15_SPARE_OSC                        , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_16_SPARE_OSC                        , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_16_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_17_SPARE_OSC                        , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_17_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_18_SPARE_OSC                        , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_18_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_19_SPARE_OSC                        , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_19_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_20_SPARE_OSC                        , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_20_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_21_SPARE_OSC                        , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_21_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_22_SPARE_OSC                        , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_23_SPARE_OSC                        , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_24_SPARE_OSC                        , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_24_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_25_SPARE_OSC                        , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_25_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_26_SPARE_OSC                        , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_27_SPARE_OSC                        , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_27_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_28_SPARE_OSC                        , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_29_SPARE_OSC                        , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_30_SPARE_OSC                        , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_SPARE_OSC );
+REG64_FLD( PERV_ROOT_CTRL5_SET_31_SPARE_OSC                        , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_31_SPARE_OSC );
+
+REG64_FLD( PERV_ROOT_CTRL6_TP_PLLREFCLK_RCVR_TERM_DC               , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC );
+REG64_FLD( PERV_ROOT_CTRL6_TP_PLLREFCLK_RCVR_TERM_DC_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL6_TP_PCIREFCLK_RCVR_TERM_DC               , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC );
+REG64_FLD( PERV_ROOT_CTRL6_TP_PCIREFCLK_RCVR_TERM_DC_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL6_REFCLK_0_TERM_DIS_DC                    , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_REFCLK_0_TERM_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL6_REFCLK_1_TERM_DIS_DC                    , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_REFCLK_1_TERM_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL6_6_SPARE_TERM_DIS                        , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_6_SPARE_TERM_DIS );
+REG64_FLD( PERV_ROOT_CTRL6_7_SPARE_TERM_DIS                        , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_7_SPARE_TERM_DIS );
+REG64_FLD( PERV_ROOT_CTRL6_TPFSI_OSCSW0_PGOOD_N                    , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW0_PGOOD_N );
+REG64_FLD( PERV_ROOT_CTRL6_TPFSI_OSCSW1_PGOOD                      , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW1_PGOOD );
+REG64_FLD( PERV_ROOT_CTRL6_10_SPARE_REFCLOCK                       , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_10_SPARE_REFCLOCK );
+REG64_FLD( PERV_ROOT_CTRL6_11_SPARE_REFCLOCK                       , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_11_SPARE_REFCLOCK );
+REG64_FLD( PERV_ROOT_CTRL6_TPFSI_OFFCHIP_REFCLK_EN_DC              , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL6_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN          , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL6_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC        , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL6_25_SPARE_REFCLOCK_CONTROL               , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_25_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_26_SPARE_REFCLOCK_CONTROL               , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_TPFSI_ALTREFCLK_SEL                     , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_ALTREFCLK_SEL );
+REG64_FLD( PERV_ROOT_CTRL6_TPFSI_ALTREFCLK_SE1                     , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_ALTREFCLK_SE1 );
+REG64_FLD( PERV_ROOT_CTRL6_29_SPARE_REFCLOCK_CONTROL               , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_30_SPARE_REFCLOCK_CONTROL               , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_31_SPARE_REFCLOCK_CONTROL               , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_31_SPARE_REFCLOCK_CONTROL );
+
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TP_PLLREFCLK_RCVR_TERM_DC         , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TP_PLLREFCLK_RCVR_TERM_DC_LEN     , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TP_PCIREFCLK_RCVR_TERM_DC         , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TP_PCIREFCLK_RCVR_TERM_DC_LEN     , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_REFCLK_0_TERM_DIS_DC              , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_REFCLK_0_TERM_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_REFCLK_1_TERM_DIS_DC              , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_REFCLK_1_TERM_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_6_SPARE_TERM_DIS                  , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_6_SPARE_TERM_DIS );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_7_SPARE_TERM_DIS                  , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_7_SPARE_TERM_DIS );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TPFSI_OSCSW0_PGOOD_N              , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW0_PGOOD_N );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TPFSI_OSCSW1_PGOOD                , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW1_PGOOD );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_10_SPARE_REFCLOCK                 , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_10_SPARE_REFCLOCK );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_11_SPARE_REFCLOCK                 , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_11_SPARE_REFCLOCK );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TPFSI_OFFCHIP_REFCLK_EN_DC        , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN    , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC  , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_25_SPARE_REFCLOCK_CONTROL         , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_25_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_26_SPARE_REFCLOCK_CONTROL         , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TPFSI_ALTREFCLK_SEL               , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_ALTREFCLK_SEL );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TPFSI_ALTREFCLK_SE1               , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_ALTREFCLK_SE1 );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_29_SPARE_REFCLOCK_CONTROL         , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_30_SPARE_REFCLOCK_CONTROL         , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_CLEAR_31_SPARE_REFCLOCK_CONTROL         , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_31_SPARE_REFCLOCK_CONTROL );
+
+REG64_FLD( PERV_ROOT_CTRL6_SET_TP_PLLREFCLK_RCVR_TERM_DC           , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC );
+REG64_FLD( PERV_ROOT_CTRL6_SET_TP_PLLREFCLK_RCVR_TERM_DC_LEN       , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL6_SET_TP_PCIREFCLK_RCVR_TERM_DC           , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC );
+REG64_FLD( PERV_ROOT_CTRL6_SET_TP_PCIREFCLK_RCVR_TERM_DC_LEN       , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL6_SET_REFCLK_0_TERM_DIS_DC                , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_REFCLK_0_TERM_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL6_SET_REFCLK_1_TERM_DIS_DC                , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_REFCLK_1_TERM_DIS_DC );
+REG64_FLD( PERV_ROOT_CTRL6_SET_6_SPARE_TERM_DIS                    , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_6_SPARE_TERM_DIS );
+REG64_FLD( PERV_ROOT_CTRL6_SET_7_SPARE_TERM_DIS                    , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_7_SPARE_TERM_DIS );
+REG64_FLD( PERV_ROOT_CTRL6_SET_TPFSI_OSCSW0_PGOOD_N                , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW0_PGOOD_N );
+REG64_FLD( PERV_ROOT_CTRL6_SET_TPFSI_OSCSW1_PGOOD                  , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OSCSW1_PGOOD );
+REG64_FLD( PERV_ROOT_CTRL6_SET_10_SPARE_REFCLOCK                   , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_10_SPARE_REFCLOCK );
+REG64_FLD( PERV_ROOT_CTRL6_SET_11_SPARE_REFCLOCK                   , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_11_SPARE_REFCLOCK );
+REG64_FLD( PERV_ROOT_CTRL6_SET_TPFSI_OFFCHIP_REFCLK_EN_DC          , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL6_SET_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN      , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN );
+REG64_FLD( PERV_ROOT_CTRL6_SET_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC    , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL6_SET_25_SPARE_REFCLOCK_CONTROL           , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_25_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_SET_26_SPARE_REFCLOCK_CONTROL           , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_SET_TPFSI_ALTREFCLK_SEL                 , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_ALTREFCLK_SEL );
+REG64_FLD( PERV_ROOT_CTRL6_SET_TPFSI_ALTREFCLK_SE1                 , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TPFSI_ALTREFCLK_SE1 );
+REG64_FLD( PERV_ROOT_CTRL6_SET_29_SPARE_REFCLOCK_CONTROL           , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_SET_30_SPARE_REFCLOCK_CONTROL           , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_SPARE_REFCLOCK_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL6_SET_31_SPARE_REFCLOCK_CONTROL           , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_31_SPARE_REFCLOCK_CONTROL );
+
+REG64_FLD( PERV_ROOT_CTRL7_0_SPARE_SECTOR_BUFFER_CONTROL           , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_1_SPARE_SECTOR_BUFFER_CONTROL           , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_1_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_2_SPARE_SECTOR_BUFFER_CONTROL           , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_2_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_3_SPARE_SECTOR_BUFFER_CONTROL           , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_3_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_4_SPARE_SECTOR_BUFFER_CONTROL           , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_4_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_5_SPARE_SECTOR_BUFFER_CONTROL           , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_5_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_6_SPARE_SECTOR_BUFFER_CONTROL           , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_6_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_7_SPARE_SECTOR_BUFFER_CONTROL           , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_7_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_8_SPARE_SECTOR_BUFFER_CONTROL           , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_8_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_9_SPARE_SECTOR_BUFFER_CONTROL           , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_9_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_10_SPARE_SECTOR_BUFFER_CONTROL          , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_10_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_11_SPARE_SECTOR_BUFFER_CONTROL          , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_11_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_12_SPARE_SECTOR_BUFFER_CONTROL          , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_12_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_13_SPARE_SECTOR_BUFFER_CONTROL          , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_13_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_14_SPARE_SECTOR_BUFFER_CONTROL          , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_14_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_15_SPARE_SECTOR_BUFFER_CONTROL          , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_16_SPARE_RESONANT_CLOCKING_CONTROL      , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_16_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_17_SPARE_RESONANT_CLOCKING_CONTROL      , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_17_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_18_SPARE_RESONANT_CLOCKING_CONTROL      , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_18_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_19_SPARE_RESONANT_CLOCKING_CONTROL      , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_19_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_20_SPARE_RESONANT_CLOCKING_CONTROL      , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_20_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_21_SPARE_RESONANT_CLOCKING_CONTROL      , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_21_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_22_SPARE_RESONANT_CLOCKING_CONTROL      , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_23_SPARE_RESONANT_CLOCKING_CONTROL      , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_24_SPARE_RESONANT_CLOCKING_CONTROL      , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_24_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_25_SPARE_RESONANT_CLOCKING_CONTROL      , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_25_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_26_SPARE_RESONANT_CLOCKING_CONTROL      , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_27_SPARE_RESONANT_CLOCKING_CONTROL      , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_27_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_28_SPARE_RESONANT_CLOCKING_CONTROL      , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_29_SPARE_RESONANT_CLOCKING_CONTROL      , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_30_SPARE_RESONANT_CLOCKING_CONTROL      , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_31_SPARE_RESONANT_CLOCKING_CONTROL      , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_31_SPARE_RESONANT_CLOCKING_CONTROL );
+
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_0_SPARE_SECTOR_BUFFER_CONTROL     , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_1_SPARE_SECTOR_BUFFER_CONTROL     , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_1_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_2_SPARE_SECTOR_BUFFER_CONTROL     , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_2_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_3_SPARE_SECTOR_BUFFER_CONTROL     , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_3_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_4_SPARE_SECTOR_BUFFER_CONTROL     , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_4_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_5_SPARE_SECTOR_BUFFER_CONTROL     , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_5_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_6_SPARE_SECTOR_BUFFER_CONTROL     , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_6_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_7_SPARE_SECTOR_BUFFER_CONTROL     , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_7_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_8_SPARE_SECTOR_BUFFER_CONTROL     , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_8_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_9_SPARE_SECTOR_BUFFER_CONTROL     , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_9_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_10_SPARE_SECTOR_BUFFER_CONTROL    , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_10_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_11_SPARE_SECTOR_BUFFER_CONTROL    , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_11_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_12_SPARE_SECTOR_BUFFER_CONTROL    , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_12_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_13_SPARE_SECTOR_BUFFER_CONTROL    , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_13_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_14_SPARE_SECTOR_BUFFER_CONTROL    , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_14_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_15_SPARE_SECTOR_BUFFER_CONTROL    , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_16_SPARE_RESONANT_CLOCKING_CONTROL , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_16_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_17_SPARE_RESONANT_CLOCKING_CONTROL , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_17_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_18_SPARE_RESONANT_CLOCKING_CONTROL , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_18_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_19_SPARE_RESONANT_CLOCKING_CONTROL , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_19_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_20_SPARE_RESONANT_CLOCKING_CONTROL , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_20_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_21_SPARE_RESONANT_CLOCKING_CONTROL , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_21_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_22_SPARE_RESONANT_CLOCKING_CONTROL , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_23_SPARE_RESONANT_CLOCKING_CONTROL , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_24_SPARE_RESONANT_CLOCKING_CONTROL , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_24_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_25_SPARE_RESONANT_CLOCKING_CONTROL , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_25_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_26_SPARE_RESONANT_CLOCKING_CONTROL , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_27_SPARE_RESONANT_CLOCKING_CONTROL , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_27_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_28_SPARE_RESONANT_CLOCKING_CONTROL , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_29_SPARE_RESONANT_CLOCKING_CONTROL , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_30_SPARE_RESONANT_CLOCKING_CONTROL , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_CLEAR_31_SPARE_RESONANT_CLOCKING_CONTROL , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_31_SPARE_RESONANT_CLOCKING_CONTROL );
+
+REG64_FLD( PERV_ROOT_CTRL7_SET_0_SPARE_SECTOR_BUFFER_CONTROL       , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_1_SPARE_SECTOR_BUFFER_CONTROL       , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_1_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_2_SPARE_SECTOR_BUFFER_CONTROL       , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_2_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_3_SPARE_SECTOR_BUFFER_CONTROL       , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_3_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_4_SPARE_SECTOR_BUFFER_CONTROL       , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_4_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_5_SPARE_SECTOR_BUFFER_CONTROL       , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_5_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_6_SPARE_SECTOR_BUFFER_CONTROL       , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_6_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_7_SPARE_SECTOR_BUFFER_CONTROL       , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_7_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_8_SPARE_SECTOR_BUFFER_CONTROL       , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_8_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_9_SPARE_SECTOR_BUFFER_CONTROL       , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_9_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_10_SPARE_SECTOR_BUFFER_CONTROL      , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_10_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_11_SPARE_SECTOR_BUFFER_CONTROL      , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_11_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_12_SPARE_SECTOR_BUFFER_CONTROL      , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_12_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_13_SPARE_SECTOR_BUFFER_CONTROL      , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_13_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_14_SPARE_SECTOR_BUFFER_CONTROL      , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_14_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_15_SPARE_SECTOR_BUFFER_CONTROL      , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_SPARE_SECTOR_BUFFER_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_16_SPARE_RESONANT_CLOCKING_CONTROL  , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_16_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_17_SPARE_RESONANT_CLOCKING_CONTROL  , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_17_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_18_SPARE_RESONANT_CLOCKING_CONTROL  , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_18_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_19_SPARE_RESONANT_CLOCKING_CONTROL  , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_19_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_20_SPARE_RESONANT_CLOCKING_CONTROL  , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_20_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_21_SPARE_RESONANT_CLOCKING_CONTROL  , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_21_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_22_SPARE_RESONANT_CLOCKING_CONTROL  , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_23_SPARE_RESONANT_CLOCKING_CONTROL  , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_24_SPARE_RESONANT_CLOCKING_CONTROL  , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_24_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_25_SPARE_RESONANT_CLOCKING_CONTROL  , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_25_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_26_SPARE_RESONANT_CLOCKING_CONTROL  , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_27_SPARE_RESONANT_CLOCKING_CONTROL  , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_27_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_28_SPARE_RESONANT_CLOCKING_CONTROL  , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_28_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_29_SPARE_RESONANT_CLOCKING_CONTROL  , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_29_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_30_SPARE_RESONANT_CLOCKING_CONTROL  , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_30_SPARE_RESONANT_CLOCKING_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL7_SET_31_SPARE_RESONANT_CLOCKING_CONTROL  , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_31_SPARE_RESONANT_CLOCKING_CONTROL );
+
+REG64_FLD( PERV_ROOT_CTRL8_TP_SS0_PLL_RESET                        , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_SS0_PLL_RESET );
+REG64_FLD( PERV_ROOT_CTRL8_TP_SS0_PLL_BYPASS                       , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_SS0_PLL_BYPASS );
+REG64_FLD( PERV_ROOT_CTRL8_TP_SS0_PLL_TEST_EN                      , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_SS0_PLL_TEST_EN );
+REG64_FLD( PERV_ROOT_CTRL8_3_SPARE_SS_PLL_CONTROL                  , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_3_SPARE_SS_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_TP_FILT0_PLL_RESET                      , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT0_PLL_RESET );
+REG64_FLD( PERV_ROOT_CTRL8_TP_FILT0_PLL_BYPASS                     , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT0_PLL_BYPASS );
+REG64_FLD( PERV_ROOT_CTRL8_TP_FILT0_PLL_TEST_EN                    , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT0_PLL_TEST_EN );
+REG64_FLD( PERV_ROOT_CTRL8_SPARE_FILT0_PLL                         , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_FILT0_PLL );
+REG64_FLD( PERV_ROOT_CTRL8_TP_FILT1_PLL_RESET                      , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT1_PLL_RESET );
+REG64_FLD( PERV_ROOT_CTRL8_TP_FILT1_PLL_BYPASS                     , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT1_PLL_BYPASS );
+REG64_FLD( PERV_ROOT_CTRL8_TP_FILT1_PLL_TEST_EN                    , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT1_PLL_TEST_EN );
+REG64_FLD( PERV_ROOT_CTRL8_SPARE_FILT1_PLL                         , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_FILT1_PLL );
+REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_TEST_EN                          , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_TEST_EN );
+REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_FORCE_OUT_EN_DC                  , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_FORCE_OUT_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_14_SPARE_PLL                            , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_14_SPARE_PLL );
+REG64_FLD( PERV_ROOT_CTRL8_15_SPARE_PLL                            , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_SPARE_PLL );
+REG64_FLD( PERV_ROOT_CTRL8_TP_CLK_ASYNC_RESET_DC                   , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_ASYNC_RESET_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_CLK_DIV_BYPASS_EN_DC                 , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_DIV_BYPASS_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_CLK_PDLY_BYPASS1_EN_DC               , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_PDLY_BYPASS1_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_CLK_PDLY_BYPASS2_EN_DC               , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_PDLY_BYPASS2_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_20_SPARE_PLL_CONTROL                    , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_20_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_21_SPARE_PLL_CONTROL                    , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_21_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_22_SPARE_PLL_CONTROL                    , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_23_SPARE_PLL_CONTROL                    , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_TP_FSI_CLKIN_SEL_DC                     , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FSI_CLKIN_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL8_25_SPARE_CLKIN_CONTROL                  , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_25_SPARE_CLKIN_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_26_SPARE_CLKIN_CONTROL                  , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_SPARE_CLKIN_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_27_SPARE_CLKIN_CONTROL                  , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_27_SPARE_CLKIN_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL1_DC                    , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_CLKIN_SEL1_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL2_DC                    , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_CLKIN_SEL2_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL3_DC                    , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_CLKIN_SEL3_DC );
+REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL4_DC                    , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_CLKIN_SEL4_DC );
+
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_SS0_PLL_RESET                  , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_SS0_PLL_RESET );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_SS0_PLL_BYPASS                 , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_SS0_PLL_BYPASS );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_SS0_PLL_TEST_EN                , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_SS0_PLL_TEST_EN );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_3_SPARE_SS_PLL_CONTROL            , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_3_SPARE_SS_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_FILT0_PLL_RESET                , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT0_PLL_RESET );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_FILT0_PLL_BYPASS               , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT0_PLL_BYPASS );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_FILT0_PLL_TEST_EN              , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT0_PLL_TEST_EN );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_SPARE_FILT0_PLL                   , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_FILT0_PLL );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_FILT1_PLL_RESET                , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT1_PLL_RESET );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_FILT1_PLL_BYPASS               , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT1_PLL_BYPASS );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_FILT1_PLL_TEST_EN              , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT1_PLL_TEST_EN );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_SPARE_FILT1_PLL                   , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_FILT1_PLL );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_PLL_TEST_EN                    , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_TEST_EN );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_PLL_FORCE_OUT_EN_DC            , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_FORCE_OUT_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_14_SPARE_PLL                      , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_14_SPARE_PLL );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_15_SPARE_PLL                      , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_SPARE_PLL );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_CLK_ASYNC_RESET_DC             , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_ASYNC_RESET_DC );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_CLK_DIV_BYPASS_EN_DC           , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_DIV_BYPASS_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_CLK_PDLY_BYPASS1_EN_DC         , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_PDLY_BYPASS1_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_CLK_PDLY_BYPASS2_EN_DC         , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_PDLY_BYPASS2_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_20_SPARE_PLL_CONTROL              , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_20_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_21_SPARE_PLL_CONTROL              , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_21_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_22_SPARE_PLL_CONTROL              , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_23_SPARE_PLL_CONTROL              , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_FSI_CLKIN_SEL_DC               , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FSI_CLKIN_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_25_SPARE_CLKIN_CONTROL            , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_25_SPARE_CLKIN_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_26_SPARE_CLKIN_CONTROL            , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_SPARE_CLKIN_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_27_SPARE_CLKIN_CONTROL            , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_27_SPARE_CLKIN_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_PLL_CLKIN_SEL1_DC              , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_CLKIN_SEL1_DC );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_PLL_CLKIN_SEL2_DC              , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_CLKIN_SEL2_DC );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_PLL_CLKIN_SEL3_DC              , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_CLKIN_SEL3_DC );
+REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_PLL_CLKIN_SEL4_DC              , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_CLKIN_SEL4_DC );
+
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_SS0_PLL_RESET                    , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_SS0_PLL_RESET );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_SS0_PLL_BYPASS                   , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_SS0_PLL_BYPASS );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_SS0_PLL_TEST_EN                  , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_SS0_PLL_TEST_EN );
+REG64_FLD( PERV_ROOT_CTRL8_SET_3_SPARE_SS_PLL_CONTROL              , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_3_SPARE_SS_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_RESET                  , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT0_PLL_RESET );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_BYPASS                 , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT0_PLL_BYPASS );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_TEST_EN                , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT0_PLL_TEST_EN );
+REG64_FLD( PERV_ROOT_CTRL8_SET_SPARE_FILT0_PLL                     , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_FILT0_PLL );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_RESET                  , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT1_PLL_RESET );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_BYPASS                 , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT1_PLL_BYPASS );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_TEST_EN                , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FILT1_PLL_TEST_EN );
+REG64_FLD( PERV_ROOT_CTRL8_SET_SPARE_FILT1_PLL                     , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_FILT1_PLL );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_PLL_TEST_EN                      , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_TEST_EN );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_PLL_FORCE_OUT_EN_DC              , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_FORCE_OUT_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_SET_14_SPARE_PLL                        , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_14_SPARE_PLL );
+REG64_FLD( PERV_ROOT_CTRL8_SET_15_SPARE_PLL                        , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_15_SPARE_PLL );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_CLK_ASYNC_RESET_DC               , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_ASYNC_RESET_DC );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_CLK_DIV_BYPASS_EN_DC             , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_DIV_BYPASS_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_CLK_PDLY_BYPASS1_EN_DC           , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_PDLY_BYPASS1_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_CLK_PDLY_BYPASS2_EN_DC           , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_CLK_PDLY_BYPASS2_EN_DC );
+REG64_FLD( PERV_ROOT_CTRL8_SET_20_SPARE_PLL_CONTROL                , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_20_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_SET_21_SPARE_PLL_CONTROL                , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_21_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_SET_22_SPARE_PLL_CONTROL                , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_22_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_SET_23_SPARE_PLL_CONTROL                , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_23_SPARE_PLL_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_FSI_CLKIN_SEL_DC                 , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_FSI_CLKIN_SEL_DC );
+REG64_FLD( PERV_ROOT_CTRL8_SET_25_SPARE_CLKIN_CONTROL              , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_25_SPARE_CLKIN_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_SET_26_SPARE_CLKIN_CONTROL              , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_26_SPARE_CLKIN_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_SET_27_SPARE_CLKIN_CONTROL              , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_27_SPARE_CLKIN_CONTROL );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL1_DC                , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_CLKIN_SEL1_DC );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL2_DC                , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_CLKIN_SEL2_DC );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL3_DC                , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_CLKIN_SEL3_DC );
+REG64_FLD( PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL4_DC                , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TP_PLL_CLKIN_SEL4_DC );
+
+REG64_FLD( PERV_SBE_LCL_DBG_EN                                     , 0   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_EN         );
+REG64_FLD( PERV_SBE_LCL_DBG_HALT_ON_XSTOP                          , 1   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( PERV_SBE_LCL_DBG_HALT_ON_TRIG                           , 2   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( PERV_SBE_LCL_DBG_EN_RISCTRACE                           , 3   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_EN_RISCTRACE );
+REG64_FLD( PERV_SBE_LCL_DBG_EN_TRACE_FULL_IVA                      , 4   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_EN_TRACE_FULL_IVA );
+REG64_FLD( PERV_SBE_LCL_DBG_DIS_TRACE_EXTRA                        , 5   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_DIS_TRACE_EXTRA );
+REG64_FLD( PERV_SBE_LCL_DBG_DIS_TRACE_STALL                        , 6   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_DIS_TRACE_STALL );
+REG64_FLD( PERV_SBE_LCL_DBG_HTM_TRACE_MODE                         , 7   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_HTM_TRACE_MODE );
+REG64_FLD( PERV_SBE_LCL_DBG_SYNC_TIMER_SEL                         , 8   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_SYNC_TIMER_SEL );
+REG64_FLD( PERV_SBE_LCL_DBG_SYNC_TIMER_SEL_LEN                     , 4   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_SYNC_TIMER_SEL_LEN );
+REG64_FLD( PERV_SBE_LCL_DBG_FIR_TRIGGER                            , 12  , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( PERV_SBE_LCL_DBG_MIB_GPIO                               , 13  , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_MIB_GPIO   );
+REG64_FLD( PERV_SBE_LCL_DBG_MIB_GPIO_LEN                           , 3   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( PERV_SBE_LCL_DBG_HALT_INPUT                             , 16  , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_HALT_INPUT );
+
+REG64_FLD( PERV_SBE_LCL_EIMR_START0                                , 0   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_START0     );
+REG64_FLD( PERV_SBE_LCL_EIMR_START1                                , 1   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_START1     );
+REG64_FLD( PERV_SBE_LCL_EIMR_INTR0                                 , 2   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_INTR0      );
+REG64_FLD( PERV_SBE_LCL_EIMR_INTR1                                 , 3   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_INTR1      );
+REG64_FLD( PERV_SBE_LCL_EIMR_DRTM_REQ                              , 4   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_DRTM_REQ   );
+REG64_FLD( PERV_SBE_LCL_EIMR_SBEFIFO_RESET                         , 5   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_SBEFIFO_RESET );
+REG64_FLD( PERV_SBE_LCL_EIMR_SBEFIFO_DATA                          , 6   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_SBEFIFO_DATA );
+REG64_FLD( PERV_SBE_LCL_EIMR_SPARE                                 , 7   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PERV_SBE_LCL_EIMR_TRIG                                  , 8   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_TRIG       );
+REG64_FLD( PERV_SBE_LCL_EIMR_XSTOP                                 , 9   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_XSTOP      );
+
+REG64_FLD( PERV_SBE_LCL_EINR_START0                                , 0   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_START0     );
+REG64_FLD( PERV_SBE_LCL_EINR_START1                                , 1   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_START1     );
+REG64_FLD( PERV_SBE_LCL_EINR_INTR0                                 , 2   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_INTR0      );
+REG64_FLD( PERV_SBE_LCL_EINR_INTR1                                 , 3   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_INTR1      );
+REG64_FLD( PERV_SBE_LCL_EINR_DRTM_REQ                              , 4   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_DRTM_REQ   );
+REG64_FLD( PERV_SBE_LCL_EINR_SBEFIFO_RESET                         , 5   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_SBEFIFO_RESET );
+REG64_FLD( PERV_SBE_LCL_EINR_SBEFIFO_DATA                          , 6   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_SBEFIFO_DATA );
+REG64_FLD( PERV_SBE_LCL_EINR_SPARE                                 , 7   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_SPARE      );
+REG64_FLD( PERV_SBE_LCL_EINR_TRIG                                  , 8   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_TRIG       );
+REG64_FLD( PERV_SBE_LCL_EINR_XSTOP                                 , 9   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_XSTOP      );
+
+REG64_FLD( PERV_SBE_LCL_EIPR_START0                                , 0   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_START0     );
+REG64_FLD( PERV_SBE_LCL_EIPR_START1                                , 1   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_START1     );
+REG64_FLD( PERV_SBE_LCL_EIPR_INTR0                                 , 2   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_INTR0      );
+REG64_FLD( PERV_SBE_LCL_EIPR_INTR1                                 , 3   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_INTR1      );
+REG64_FLD( PERV_SBE_LCL_EIPR_DRTM_REQ                              , 4   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_DRTM_REQ   );
+REG64_FLD( PERV_SBE_LCL_EIPR_SBEFIFO_RESET                         , 5   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_SBEFIFO_RESET );
+REG64_FLD( PERV_SBE_LCL_EIPR_SBEFIFO_DATA                          , 6   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_SBEFIFO_DATA );
+REG64_FLD( PERV_SBE_LCL_EIPR_SPARE                                 , 7   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PERV_SBE_LCL_EIPR_TRIG                                  , 8   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_TRIG       );
+REG64_FLD( PERV_SBE_LCL_EIPR_XSTOP                                 , 9   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_XSTOP      );
+
+REG64_FLD( PERV_SBE_LCL_EISR_START0                                , 0   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_START0     );
+REG64_FLD( PERV_SBE_LCL_EISR_START1                                , 1   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_START1     );
+REG64_FLD( PERV_SBE_LCL_EISR_INTR0                                 , 2   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_INTR0      );
+REG64_FLD( PERV_SBE_LCL_EISR_INTR1                                 , 3   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_INTR1      );
+REG64_FLD( PERV_SBE_LCL_EISR_DRTM_REQ                              , 4   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_DRTM_REQ   );
+REG64_FLD( PERV_SBE_LCL_EISR_SBEFIFO_RESET                         , 5   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_SBEFIFO_RESET );
+REG64_FLD( PERV_SBE_LCL_EISR_SBEFIFO_DATA                          , 6   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_SBEFIFO_DATA );
+REG64_FLD( PERV_SBE_LCL_EISR_SPARE                                 , 7   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PERV_SBE_LCL_EISR_TRIG                                  , 8   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_TRIG       );
+REG64_FLD( PERV_SBE_LCL_EISR_XSTOP                                 , 9   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_XSTOP      );
+
+REG64_FLD( PERV_SBE_LCL_EITR_START0                                , 0   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_START0     );
+REG64_FLD( PERV_SBE_LCL_EITR_START1                                , 1   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_START1     );
+REG64_FLD( PERV_SBE_LCL_EITR_INTR0                                 , 2   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_INTR0      );
+REG64_FLD( PERV_SBE_LCL_EITR_INTR1                                 , 3   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_INTR1      );
+REG64_FLD( PERV_SBE_LCL_EITR_DRTM_REQ                              , 4   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_DRTM_REQ   );
+REG64_FLD( PERV_SBE_LCL_EITR_SBEFIFO_RESET                         , 5   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_SBEFIFO_RESET );
+REG64_FLD( PERV_SBE_LCL_EITR_SBEFIFO_DATA                          , 6   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_SBEFIFO_DATA );
+REG64_FLD( PERV_SBE_LCL_EITR_SPARE                                 , 7   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_SPARE      );
+REG64_FLD( PERV_SBE_LCL_EITR_TRIG                                  , 8   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_TRIG       );
+REG64_FLD( PERV_SBE_LCL_EITR_XSTOP                                 , 9   , SH_UNT_PERV     , SH_ACS_PPE2     ,
+           SH_FLD_XSTOP      );
+
+REG64_FLD( PERV_SBE_LCL_IVPR_IVPR                                  , 0   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_IVPR       );
+REG64_FLD( PERV_SBE_LCL_IVPR_IVPR_LEN                              , 23  , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_IVPR_LEN   );
+
+REG64_FLD( PERV_SBE_LCL_TBR_TIMEBASE                               , 0   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( PERV_SBE_LCL_TBR_TIMEBASE_LEN                           , 32  , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_TIMEBASE_LEN );
+
+REG64_FLD( PERV_SBE_LCL_TSEL_FIT_SEL                               , 0   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( PERV_SBE_LCL_TSEL_FIT_SEL_LEN                           , 4   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( PERV_SBE_LCL_TSEL_WATCHDOG_SEL                          , 4   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( PERV_SBE_LCL_TSEL_WATCHDOG_SEL_LEN                      , 4   , SH_UNT_PERV     , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( PERV_SB_CS_SECURE_DEBUG_MODE                            , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SECURE_DEBUG_MODE );
+REG64_FLD( PERV_SB_CS_START_RESTART_VECTOR0                        , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_START_RESTART_VECTOR0 );
+REG64_FLD( PERV_SB_CS_START_RESTART_VECTOR1                        , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_START_RESTART_VECTOR1 );
+REG64_FLD( PERV_SB_CS_INTERRUPT_S0                                 , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_S0 );
+REG64_FLD( PERV_SB_CS_INTERRUPT_S1                                 , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT_S1 );
+REG64_FLD( PERV_SB_CS_BYPASSING_RESET_SEQUENCE_PIB_I2CM            , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_BYPASSING_RESET_SEQUENCE_PIB_I2CM );
+REG64_FLD( PERV_SB_CS_SELECT_SECONDARY_SEEPROM                     , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SELECT_SECONDARY_SEEPROM );
+REG64_FLD( PERV_SB_CS_DEBUG_BOLT_ON_CONTROL_BITS                   , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS );
+REG64_FLD( PERV_SB_CS_DEBUG_BOLT_ON_CONTROL_BITS_LEN               , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS_LEN );
+
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_SYSTEM_FAST_INIT                , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SYSTEM_FAST_INIT );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_VITL                            , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_VITL       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_PERV                            , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT1                           , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT2                           , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT3                           , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT4                           , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT5                           , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT6                           , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT7                           , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT8                           , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT9                           , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_UNIT10                          , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_FUNC                            , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FUNC       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_CFG                             , 49  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CFG        );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_CCFG_GPTR                       , 50  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CCFG_GPTR  );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_REGF                            , 51  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_REGF       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_LBIST                           , 52  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_LBIST      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_ABIST                           , 53  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ABIST      );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_REPR                            , 54  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPR       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_TIME                            , 55  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TIME       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_BNDY                            , 56  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_BNDY       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_FARR                            , 57  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FARR       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_CMSK                            , 58  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CMSK       );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_INEX                            , 59  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_INEX       );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_1_SR                              , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_1_SR_LEN                          , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR_LEN     );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_2_SR                              , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_2_SR_LEN                          , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR_LEN     );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_3_SR                              , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_3_SR_LEN                          , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR_LEN     );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_4_SR                              , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_4_SR_LEN                          , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR_LEN     );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_5_SR                              , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_5_SR_LEN                          , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR_LEN     );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_6_SR                              , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_6_SR_LEN                          , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR_LEN     );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_7_SR                              , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_7_SR_LEN                          , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR_LEN     );
+
+REG64_FLD( PERV_SCRATCH_REGISTER_8_SR                              , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR         );
+REG64_FLD( PERV_SCRATCH_REGISTER_8_SR_LEN                          , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SR_LEN     );
+
+REG32_FLD( PERV_FSISHIFT_SHIFT_CONTROL_REGISTER_2_REGISTER         , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REGISTER   );
+REG32_FLD( PERV_FSISHIFT_SHIFT_CONTROL_REGISTER_2_REGISTER_LEN     , 32  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REGISTER_LEN );
+
+REG64_FLD( PERV_1_SKITTER_CLKSRC_REG_SKITTER0                      , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0   );
+REG64_FLD( PERV_1_SKITTER_CLKSRC_REG_SKITTER0_LEN                  , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0_LEN );
+REG64_FLD( PERV_1_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT         , 36  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0_DELAY_SELECT );
+REG64_FLD( PERV_1_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN     , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0_DELAY_SELECT_LEN );
+
+REG64_FLD( PERV_1_SKITTER_FORCE_REG_F_READ                         , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_F_READ     );
+
+REG64_FLD( PERV_1_SKITTER_MODE_REG_HOLD_SAMPLE                     , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_SAMPLE );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_DISABLE_STICKINESS              , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_STICKINESS );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_UNUSED1                         , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1    );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_UNUSED1_LEN                     , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1_LEN );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL                , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_DBGTRIG_SEL );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN            , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_DBGTRIG_SEL_LEN );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_RESET_TRIG_SEL                  , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET_TRIG_SEL );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN              , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET_TRIG_SEL_LEN );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_SAMPLE_GUTS                     , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_GUTS );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_SAMPLE_GUTS_LEN                 , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_GUTS_LEN );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER        , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_SAMPLE_WITH_TRIGGER );
+REG64_FLD( PERV_1_SKITTER_MODE_REG_DATA_V_LT                       , 45  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DATA_V_LT  );
+
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK    , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN      , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_MALF_PULSE_GEN );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP      , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK      , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT           , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_HEARTBEAT );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO       , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_FORCE_TO_ZERO );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_PM_DISABLE                  , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PM_DISABLE );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE              , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PM_MUX_DISABLE );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_ERROR_MASK                      , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_MASK );
+REG64_FLD( PERV_1_SLAVE_CONFIG_REG_ERROR_MASK_LEN                  , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_MASK_LEN );
+
+REG64_FLD( PERV_SNS1LTH_SNS1_UNUSED_0_31                           , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SNS1_UNUSED_0_31 );
+REG64_FLD( PERV_SNS1LTH_SNS1_UNUSED_0_31_LEN                       , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SNS1_UNUSED_0_31_LEN );
+
+REG64_FLD( PERV_SNS2LTH_SNS2_UNUSED_0_31                           , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SNS2_UNUSED_0_31 );
+REG64_FLD( PERV_SNS2LTH_SNS2_UNUSED_0_31_LEN                       , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SNS2_UNUSED_0_31_LEN );
+
+REG64_FLD( PERV_1_SPATTN_IN0                                       , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN0        );
+REG64_FLD( PERV_1_SPATTN_IN1                                       , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN1        );
+REG64_FLD( PERV_1_SPATTN_IN2                                       , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN2        );
+REG64_FLD( PERV_1_SPATTN_IN3                                       , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN3        );
+REG64_FLD( PERV_1_SPATTN_IN4                                       , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN4        );
+REG64_FLD( PERV_1_SPATTN_IN5                                       , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN5        );
+REG64_FLD( PERV_1_SPATTN_IN6                                       , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN6        );
+REG64_FLD( PERV_1_SPATTN_IN7                                       , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN7        );
+REG64_FLD( PERV_1_SPATTN_IN8                                       , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN8        );
+REG64_FLD( PERV_1_SPATTN_IN9                                       , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN9        );
+
+REG64_FLD( PERV_1_SPA_MASK_IN                                      , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( PERV_1_SPA_MASK_IN_LEN                                  , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG32_FLD( PERV_FSI2PIB_STATUS_ANY_ERROR                           , 0   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_ANY_ERROR  );
+REG32_FLD( PERV_FSI2PIB_STATUS_SYSTEM_CHECKSTOP                    , 1   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_SYSTEM_CHECKSTOP );
+REG32_FLD( PERV_FSI2PIB_STATUS_SPECIAL_ATTENTION                   , 2   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_SPECIAL_ATTENTION );
+REG32_FLD( PERV_FSI2PIB_STATUS_RECOVERABLE_ERROR                   , 3   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_RECOVERABLE_ERROR );
+REG32_FLD( PERV_FSI2PIB_STATUS_CHIPLET_INTERRUPT_FROM_HOST         , 4   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_CHIPLET_INTERRUPT_FROM_HOST );
+REG32_FLD( PERV_FSI2PIB_STATUS_PARITY_CHECK                        , 5   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_PARITY_CHECK );
+REG32_FLD( PERV_FSI2PIB_STATUS_POWER_MANAGEMENT_INTERRUPT          , 6   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_POWER_MANAGEMENT_INTERRUPT );
+REG32_FLD( PERV_FSI2PIB_STATUS_PROTECTION_CHECK                    , 7   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_PROTECTION_CHECK );
+REG32_FLD( PERV_FSI2PIB_STATUS_SELFBOOT_DONE                       , 8   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_SELFBOOT_DONE );
+REG32_FLD( PERV_FSI2PIB_STATUS_RESERVED_9                          , 9   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_RESERVED_9 );
+REG32_FLD( PERV_FSI2PIB_STATUS_IDLE_INDICATION                     , 10  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_IDLE_INDICATION );
+REG32_FLD( PERV_FSI2PIB_STATUS_PIB_ABORT                           , 11  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_PIB_ABORT  );
+REG32_FLD( PERV_FSI2PIB_STATUS_USE_OSC_OBSERVATION                 , 12  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_USE_OSC_OBSERVATION );
+REG32_FLD( PERV_FSI2PIB_STATUS_USE_OSC_OBSERVATION_LEN             , 4   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_USE_OSC_OBSERVATION_LEN );
+REG32_FLD( PERV_FSI2PIB_STATUS_VDD_NEST_OBSERVE                    , 16  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_VDD_NEST_OBSERVE );
+REG32_FLD( PERV_FSI2PIB_STATUS_PIB_ERROR_CODE                      , 17  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_PIB_ERROR_CODE );
+REG32_FLD( PERV_FSI2PIB_STATUS_PIB_ERROR_CODE_LEN                  , 3   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_PIB_ERROR_CODE_LEN );
+REG32_FLD( PERV_FSI2PIB_STATUS_OSCILLATOR                          , 20  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_OSCILLATOR );
+REG32_FLD( PERV_FSI2PIB_STATUS_OSCILLATOR_LEN                      , 4   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_OSCILLATOR_LEN );
+REG32_FLD( PERV_FSI2PIB_STATUS_PLLLOCK_0_FILTER_PLL_NEST           , 24  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_PLLLOCK_0_FILTER_PLL_NEST );
+REG32_FLD( PERV_FSI2PIB_STATUS_PLLLOCK_1_FILTER_PLL_MC             , 25  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_PLLLOCK_1_FILTER_PLL_MC );
+REG32_FLD( PERV_FSI2PIB_STATUS_PLLLOCK_2_XBUS                      , 26  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_PLLLOCK_2_XBUS );
+REG32_FLD( PERV_FSI2PIB_STATUS_PLLLOCK_3_NEST                      , 27  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_PLLLOCK_3_NEST );
+REG32_FLD( PERV_FSI2PIB_STATUS_INTERRUPT_CONDITION_PENDING         , 28  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_INTERRUPT_CONDITION_PENDING );
+REG32_FLD( PERV_FSI2PIB_STATUS_INTERRUPT_ENABLED                   , 29  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_INTERRUPT_ENABLED );
+REG32_FLD( PERV_FSI2PIB_STATUS_SELFBOOT_ENGINE_ATTENTION           , 30  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_SELFBOOT_ENGINE_ATTENTION );
+REG32_FLD( PERV_FSI2PIB_STATUS_RESERVED_31                         , 31  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_RESERVED_31 );
+
+REG32_FLD( PERV_FSISHIFT_STATUS_4                                  , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_4          );
+REG32_FLD( PERV_FSISHIFT_STATUS_4_LEN                              , 32  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_4_LEN      );
+
+REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_INVALID_CMD_0      , 0   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_INVALID_CMD_0 );
+REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_LBUS_PARITY_ERROR_0 , 1   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_LBUS_PARITY_ERROR_0 );
+REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_BE_OV_ERROR_0      , 2   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_BE_OV_ERROR_0 );
+REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_BE_ACC_ERROR_0     , 3   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_BE_ACC_ERROR_0 );
+REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_ARBITRATION_LOST_ERROR_0 , 4   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_ARBITRATION_LOST_ERROR_0 );
+REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_NACK_RECEIVED_ERROR_0 , 5   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_NACK_RECEIVED_ERROR_0 );
+REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_DATA_REQUEST_0     , 6   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_DATA_REQUEST_0 );
+REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_STOP_ERROR_0       , 8   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_STOP_ERROR_0 );
+REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_BUSY               , 22  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_BUSY       );
+REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_SELF_BUSY_0        , 23  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_SELF_BUSY_0 );
+REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_FIFO_ENTRY_COUNT_0 , 28  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_FIFO_ENTRY_COUNT_0 );
+REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_FIFO_ENTRY_COUNT_0_LEN , 4   , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_FIFO_ENTRY_COUNT_0_LEN );
+
+REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_CMD_PARITY_ERROR         , 1   , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO  ,
+           SH_FLD_CMD_PARITY_ERROR );
+REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_WR_DATA_PARITY_ERROR     , 2   , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_DATA_PARITY_ERROR );
+REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_RD_DATA_PARITY_ERROR     , 3   , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_DATA_PARITY_ERROR );
+REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_LCK_STATUS_PARITY_ERROR  , 4   , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO  ,
+           SH_FLD_LCK_STATUS_PARITY_ERROR );
+REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_FSM_PARITY_ERROR         , 5   , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO  ,
+           SH_FLD_FSM_PARITY_ERROR );
+REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_OPB_PARITY_ERROR         , 8   , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO  ,
+           SH_FLD_OPB_PARITY_ERROR );
+
+REG64_FLD( PERV_STAT_RDDAT_ERRES_CMD_PARITY_ERROR                  , 1   , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_CMD_PARITY_ERROR );
+REG64_FLD( PERV_STAT_RDDAT_ERRES_WR_DATA_PARITY_ERROR              , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_DATA_PARITY_ERROR );
+REG64_FLD( PERV_STAT_RDDAT_ERRES_RD_DATA_PARITY_ERROR              , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_DATA_PARITY_ERROR );
+REG64_FLD( PERV_STAT_RDDAT_ERRES_LCK_STATUS_PARITY_ERROR           , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LCK_STATUS_PARITY_ERROR );
+REG64_FLD( PERV_STAT_RDDAT_ERRES_FSM_PARITY_ERROR                  , 5   , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_FSM_PARITY_ERROR );
+REG64_FLD( PERV_STAT_RDDAT_ERRES_OPB_PARITY_ERROR                  , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RO  ,
+           SH_FLD_OPB_PARITY_ERROR );
+
+REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_CMD_PARITY_ERROR         , 1   , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO  ,
+           SH_FLD_CMD_PARITY_ERROR );
+REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_WR_DATA_PARITY_ERROR     , 2   , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO  ,
+           SH_FLD_WR_DATA_PARITY_ERROR );
+REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_RD_DATA_PARITY_ERROR     , 3   , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO  ,
+           SH_FLD_RD_DATA_PARITY_ERROR );
+REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_LCK_STATUS_PARITY_ERROR  , 4   , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO  ,
+           SH_FLD_LCK_STATUS_PARITY_ERROR );
+REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_FSM_PARITY_ERROR         , 5   , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO  ,
+           SH_FLD_FSM_PARITY_ERROR );
+REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_OPB_PARITY_ERROR         , 8   , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO  ,
+           SH_FLD_OPB_PARITY_ERROR );
+
+REG64_FLD( PERV_1_SUM_MASK_REG_SMASK_IN0                           , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN0  );
+REG64_FLD( PERV_1_SUM_MASK_REG_SMASK_IN1                           , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN1  );
+REG64_FLD( PERV_1_SUM_MASK_REG_SMASK_IN2                           , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN2  );
+REG64_FLD( PERV_1_SUM_MASK_REG_SMASK_IN3                           , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN3  );
+REG64_FLD( PERV_1_SUM_MASK_REG_SMASK_IN4                           , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN4  );
+
+REG64_FLD( PERV_1_SYNC_CONFIG_PULSE_DELAY                          , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PULSE_DELAY );
+REG64_FLD( PERV_1_SYNC_CONFIG_PULSE_DELAY_LEN                      , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PULSE_DELAY_LEN );
+REG64_FLD( PERV_1_SYNC_CONFIG_LISTEN_TO_PULSE_DIS                  , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_LISTEN_TO_PULSE_DIS );
+REG64_FLD( PERV_1_SYNC_CONFIG_PULSE_INPUT_SEL                      , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PULSE_INPUT_SEL );
+REG64_FLD( PERV_1_SYNC_CONFIG_USE_FOR_SCAN                         , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_USE_FOR_SCAN );
+REG64_FLD( PERV_1_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED             , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLEAR_CHIPLET_IS_ALIGNED );
+REG64_FLD( PERV_1_SYNC_CONFIG_UNIT_REGION_CLKCMD_DISABLE           , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT_REGION_CLKCMD_DISABLE );
+REG64_FLD( PERV_1_SYNC_CONFIG_DISABLE_PCB_ITR                      , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_PCB_ITR );
+REG64_FLD( PERV_1_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK              , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_VITL_ALIGN_CHECK );
+REG64_FLD( PERV_1_SYNC_CONFIG_UNUSED1119                           , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1119 );
+REG64_FLD( PERV_1_SYNC_CONFIG_UNUSED1119_LEN                       , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1119_LEN );
+
+REG64_FLD( PERV_1_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR               , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DIS_CPM_BUBBLE_CORR );
+REG64_FLD( PERV_1_THERM_MODE_REG_FORCE_THRES_ACT                   , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_THRES_ACT );
+REG64_FLD( PERV_1_THERM_MODE_REG_THRES_TRIP_ENA                    , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRES_TRIP_ENA );
+REG64_FLD( PERV_1_THERM_MODE_REG_THRES_TRIP_ENA_LEN                , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRES_TRIP_ENA_LEN );
+REG64_FLD( PERV_1_THERM_MODE_REG_DTS_SAMPLE_ENA                    , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DTS_SAMPLE_ENA );
+REG64_FLD( PERV_1_THERM_MODE_REG_SAMPLE_PULSE_CNT                  , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_PULSE_CNT );
+REG64_FLD( PERV_1_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN              , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_PULSE_CNT_LEN );
+REG64_FLD( PERV_1_THERM_MODE_REG_THRES_ENA                         , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRES_ENA  );
+REG64_FLD( PERV_1_THERM_MODE_REG_THRES_ENA_LEN                     , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRES_ENA_LEN );
+REG64_FLD( PERV_1_THERM_MODE_REG_DTS_TRIGGER                       , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DTS_TRIGGER );
+REG64_FLD( PERV_1_THERM_MODE_REG_DTS_TRIGGER_SEL                   , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DTS_TRIGGER_SEL );
+REG64_FLD( PERV_1_THERM_MODE_REG_THRES_OVERFLOW_MASK               , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRES_OVERFLOW_MASK );
+REG64_FLD( PERV_1_THERM_MODE_REG_UNUSED                            , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PERV_1_THERM_MODE_REG_DTS_READ_SEL                      , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DTS_READ_SEL );
+REG64_FLD( PERV_1_THERM_MODE_REG_DTS_READ_SEL_LEN                  , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DTS_READ_SEL_LEN );
+REG64_FLD( PERV_1_THERM_MODE_REG_DTS_ENABLE_L1                     , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DTS_ENABLE_L1 );
+REG64_FLD( PERV_1_THERM_MODE_REG_DTS_ENABLE_L1_LEN                 , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DTS_ENABLE_L1_LEN );
+
+REG64_FLD( PERV_TIMEOUT_REG_REGISTER                               , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_REGISTER   );
+REG64_FLD( PERV_TIMEOUT_REG_REGISTER_LEN                           , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_REGISTER_LEN );
+
+REG64_FLD( PERV_1_TIMESTAMP_COUNTER_READ_VALUE                     , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_VALUE      );
+REG64_FLD( PERV_1_TIMESTAMP_COUNTER_READ_VALUE_LEN                 , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_VALUE_LEN  );
+REG64_FLD( PERV_1_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR              , 44  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_OVERFLOW_ERR );
+
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_TIMEBASE_ENABLE                  , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TIMEBASE_ENABLE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SELECT   , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SELECT_LEN , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT_LEN );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_I_PATH_SYNC_CHECK_DISABLE        , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_I_PATH_SYNC_CHECK_DISABLE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_TX_TTYPE_PIB_MST_FSM_STATE_DISABLE , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TX_TTYPE_PIB_MST_FSM_STATE_DISABLE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_RX_TTYPE_1_ON_STEP_ENABLE        , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_RX_TTYPE_1_ON_STEP_ENABLE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_MOVE_TO_TB_ON_2X_SYNC_ENABLE     , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MOVE_TO_TB_ON_2X_SYNC_ENABLE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_USE_TB_SYNC_MECHANISM            , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_USE_TB_SYNC_MECHANISM );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_USE_TB_STEP_SYNC                 , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_USE_TB_STEP_SYNC );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VALUE             , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_LOW_ORDER_STEP_VALUE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VALUE_LEN         , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_LOW_ORDER_STEP_VALUE_LEN );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_DISTRIBUTION_BROADCAST_MODE_ENABLE , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DISTRIBUTION_BROADCAST_MODE_ENABLE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_17_18                 , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X10_SPARE_17_18 );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_17_18_LEN             , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X10_SPARE_17_18_LEN );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_19_23                 , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X10_SPARE_19_23 );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_19_23_LEN             , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X10_SPARE_19_23_LEN );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_24_25                 , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X10_SPARE_24_25 );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_24_25_LEN             , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X10_SPARE_24_25_LEN );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_TX_TTYPE_PIB_MST_IF_RESET        , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_TX_TTYPE_PIB_MST_IF_RESET );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_27                    , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X10_SPARE_27 );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_M_PATH_CLOCK_OFF_ENABLE          , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_M_PATH_CLOCK_OFF_ENABLE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_0X10_SPARE_29                    , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X10_SPARE_29 );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_XSTOP_GATE                       , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_XSTOP_GATE );
+REG64_FLD( PERV_TOD_CHIP_CTRL_REG_STICKY_ERROR_INJECT_ENABLE       , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_STICKY_ERROR_INJECT_ENABLE );
+
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X00_DATA_PARITY              , 0   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X00_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_M_PATH_0_PARITY               , 1   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_M_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_M_PATH_1_PARITY               , 2   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_M_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X01_DATA_PARITY              , 3   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X01_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X02_DATA_PARITY              , 4   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X02_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X03_DATA_PARITY              , 5   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X03_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X04_DATA_PARITY              , 6   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X04_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X05_DATA_PARITY              , 7   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X05_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X06_DATA_PARITY              , 8   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X06_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X07_DATA_PARITY              , 9   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X07_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_S_PATH_0_PARITY               , 10  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_S_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X08_DATA_PARITY              , 11  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X08_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X09_DATA_PARITY              , 12  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X09_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X0A_DATA_PARITY              , 13  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X0A_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_M_PATH_0_STEP_CHECK           , 14  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_M_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_M_PATH_1_STEP_CHECK           , 15  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_M_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_S_PATH_0_STEP_CHECK           , 16  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_S_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_I_PATH_STEP_CHECK             , 17  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_I_PATH_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PSS_HAM                       , 18  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_PSS_HAM    );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X0B_DATA_PARITY              , 19  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X0B_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_S_PATH_1_PARITY               , 20  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_S_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_S_PATH_1_STEP_CHECK           , 21  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_S_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_I_PATH_DELAY_STEP_CHECK_PARITY , 22  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_I_PATH_DELAY_STEP_CHECK_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X0C_DATA_PARITY              , 23  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X0C_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY , 24  , SH_UNT_PERV     ,
+           SH_ACS_SCOM_WO  , SH_FLD_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X17_0X18_0X21_0X22_DATA_PARITY , 25  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X17_0X18_0X21_0X22_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X1D_0X1E_0X1F_DATA_PARITY    , 26  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X1D_0X1E_0X1F_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X20_DATA_PARITY              , 27  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X20_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X23_DATA_PARITY              , 28  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X23_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X24_DATA_PARITY              , 29  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X24_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X29_DATA_PARITY              , 30  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X29_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X30_0X31_0X32_0X33_DATA_PARITY , 31  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X30_0X31_0X32_0X33_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X10_DATA_PARITY              , 32  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X10_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_I_PATH_SYNC_CHECK             , 33  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_I_PATH_SYNC_CHECK );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_I_PATH_FSM_STATE_PARITY       , 34  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_I_PATH_FSM_STATE_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_I_PATH_TIME_PARITY            , 35  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_I_PATH_TIME_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_I_PATH_TIME_OVERFLOW          , 36  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_I_PATH_TIME_OVERFLOW );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_WOF_LOW_ORDER_STEP_COUNTER_PARITY , 37  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_WOF_LOW_ORDER_STEP_COUNTER_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_0                    , 38  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_RX_TTYPE_0 );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_1                    , 39  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_RX_TTYPE_1 );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_2                    , 40  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_RX_TTYPE_2 );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_3                    , 41  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_RX_TTYPE_3 );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_4                    , 42  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_RX_TTYPE_4 );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_5                    , 43  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_RX_TTYPE_5 );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_SLAVE_ADDR_INVALID        , 44  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_PIB_SLAVE_ADDR_INVALID );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_SLAVE_WRITE_INVALID       , 45  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_PIB_SLAVE_WRITE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_SLAVE_READ_INVALID        , 46  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_PIB_SLAVE_READ_INVALID );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_SLAVE_ADDR_PARITY         , 47  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_PIB_SLAVE_ADDR_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_SLAVE_DATA_PARITY         , 48  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_PIB_SLAVE_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_0X27_DATA_PARITY              , 49  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_0X27_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_MASTER_RSP_INFO           , 50  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_PIB_MASTER_RSP_INFO );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_MASTER_RSP_INFO_LEN       , 3   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_PIB_MASTER_RSP_INFO_LEN );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_INVALID              , 53  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_RX_TTYPE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_RX_TTYPE_4_DATA_PARITY        , 54  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_RX_TTYPE_4_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_MASTER_REQUEST            , 55  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_PIB_MASTER_REQUEST );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_PIB_RESET_DURING_PIB_ACCESS   , 56  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_PIB_RESET_DURING_PIB_ACCESS );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_EXTERNAL_XSTOP                , 57  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_EXTERNAL_XSTOP );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_SPARE_58                      , 58  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPARE_58   );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_SPARE_59                      , 59  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPARE_59   );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_SPARE_60                      , 60  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPARE_60   );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_SPARE_61                      , 61  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPARE_61   );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_OSCSWITCH_INTERRUPT           , 62  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_OSCSWITCH_INTERRUPT );
+REG64_FLD( PERV_TOD_ERROR_INJECT_REG_CORE_STEP                     , 63  , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_CORE_STEP  );
+
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X00_DATA_PARITY                , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X00_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_M_PATH_0_PARITY                 , 1   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_M_PATH_1_PARITY                 , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X01_DATA_PARITY                , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X01_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X02_DATA_PARITY                , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X02_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X03_DATA_PARITY                , 5   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X03_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X04_DATA_PARITY                , 6   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X04_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X05_DATA_PARITY                , 7   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X05_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X06_DATA_PARITY                , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X06_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X07_DATA_PARITY                , 9   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X07_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_S_PATH_0_PARITY                 , 10  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_S_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X08_DATA_PARITY                , 11  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X08_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X09_DATA_PARITY                , 12  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X09_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X0A_DATA_PARITY                , 13  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0A_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_M_PATH_0_STEP_CHECK             , 14  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_M_PATH_1_STEP_CHECK             , 15  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_S_PATH_0_STEP_CHECK             , 16  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_S_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_I_PATH_STEP_CHECK               , 17  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PSS_HAM                         , 18  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PSS_HAM    );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X0B_DATA_PARITY                , 19  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0B_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_S_PATH_1_PARITY                 , 20  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_S_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_S_PATH_1_STEP_CHECK             , 21  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_S_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_I_PATH_DELAY_STEP_CHECK_PARITY  , 22  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_DELAY_STEP_CHECK_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X0C_DATA_PARITY                , 23  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0C_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY , 24  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X17_0X18_0X21_0X22_DATA_PARITY , 25  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X17_0X18_0X21_0X22_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X1D_0X1E_0X1F_DATA_PARITY      , 26  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X1D_0X1E_0X1F_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X20_DATA_PARITY                , 27  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X20_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X23_DATA_PARITY                , 28  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X23_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X24_DATA_PARITY                , 29  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X24_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X29_DATA_PARITY                , 30  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X29_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X30_0X31_0X32_0X33_DATA_PARITY , 31  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X30_0X31_0X32_0X33_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X10_DATA_PARITY                , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X10_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_I_PATH_SYNC_CHECK               , 33  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_SYNC_CHECK );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_I_PATH_FSM_STATE_PARITY         , 34  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_FSM_STATE_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_I_PATH_TIME_PARITY              , 35  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_TIME_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_I_PATH_TIME_OVERFLOW            , 36  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_TIME_OVERFLOW );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_WOF_LOW_ORDER_STEP_COUNTER_PARITY , 37  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_WOF_LOW_ORDER_STEP_COUNTER_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_0                      , 38  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_0 );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_1                      , 39  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_1 );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_2                      , 40  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_2 );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_3                      , 41  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_3 );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_4                      , 42  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_4 );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_5                      , 43  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_5 );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_SLAVE_ADDR_INVALID          , 44  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_SLAVE_ADDR_INVALID );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_SLAVE_WRITE_INVALID         , 45  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_SLAVE_WRITE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_SLAVE_READ_INVALID          , 46  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_SLAVE_READ_INVALID );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_SLAVE_ADDR_PARITY           , 47  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_SLAVE_ADDR_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_SLAVE_DATA_PARITY           , 48  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_SLAVE_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_0X27_DATA_PARITY                , 49  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X27_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_MASTER_RSP_INFO             , 50  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_MASTER_RSP_INFO );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_MASTER_RSP_INFO_LEN         , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_MASTER_RSP_INFO_LEN );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_INVALID                , 53  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_RX_TTYPE_4_DATA_PARITY          , 54  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_4_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_MASTER_REQUEST              , 55  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_MASTER_REQUEST );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_PIB_RESET_DURING_PIB_ACCESS     , 56  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_RESET_DURING_PIB_ACCESS );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_EXTERNAL_XSTOP                  , 57  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXTERNAL_XSTOP );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_SPARE_58                        , 58  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_58   );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_SPARE_59                        , 59  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_59   );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_SPARE_60                        , 60  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_60   );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_SPARE_61                        , 61  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_61   );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_OSCSWITCH_INTERRUPT             , 62  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_OSCSWITCH_INTERRUPT );
+REG64_FLD( PERV_TOD_ERROR_MASK_REG_SPARE_63                        , 63  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_63   );
+
+REG64_FLD( PERV_TOD_ERROR_REG_0X00_DATA_PARITY                     , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X00_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_M_PATH_0_PARITY                      , 1   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_M_PATH_1_PARITY                      , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X01_DATA_PARITY                     , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X01_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X02_DATA_PARITY                     , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X02_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X03_DATA_PARITY                     , 5   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X03_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X04_DATA_PARITY                     , 6   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X04_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X05_DATA_PARITY                     , 7   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X05_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X06_DATA_PARITY                     , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X06_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X07_DATA_PARITY                     , 9   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X07_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_S_PATH_0_PARITY                      , 10  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_S_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X08_DATA_PARITY                     , 11  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X08_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X09_DATA_PARITY                     , 12  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X09_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X0A_DATA_PARITY                     , 13  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0A_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_M_PATH_0_STEP_CHECK                  , 14  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_REG_M_PATH_1_STEP_CHECK                  , 15  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_REG_S_PATH_0_STEP_CHECK                  , 16  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_S_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_REG_I_PATH_STEP_CHECK                    , 17  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_REG_PSS_HAM                              , 18  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PSS_HAM    );
+REG64_FLD( PERV_TOD_ERROR_REG_0X0B_DATA_PARITY                     , 19  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0B_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_S_PATH_1_PARITY                      , 20  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_S_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_S_PATH_1_STEP_CHECK                  , 21  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_S_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_REG_I_PATH_DELAY_STEP_CHECK_PARITY       , 22  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_DELAY_STEP_CHECK_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X0C_DATA_PARITY                     , 23  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0C_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY , 24  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X17_0X18_0X21_0X22_DATA_PARITY      , 25  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X17_0X18_0X21_0X22_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X1D_0X1E_0X1F_DATA_PARITY           , 26  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X1D_0X1E_0X1F_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X20_DATA_PARITY                     , 27  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X20_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X23_DATA_PARITY                     , 28  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X23_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X24_DATA_PARITY                     , 29  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X24_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X29_DATA_PARITY                     , 30  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X29_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X30_0X31_0X32_0X33_DATA_PARITY      , 31  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X30_0X31_0X32_0X33_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X10_DATA_PARITY                     , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X10_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_I_PATH_SYNC_CHECK                    , 33  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_SYNC_CHECK );
+REG64_FLD( PERV_TOD_ERROR_REG_I_PATH_FSM_STATE_PARITY              , 34  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_FSM_STATE_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_I_PATH_TIME_PARITY                   , 35  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_TIME_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_I_PATH_TIME_OVERFLOW                 , 36  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_TIME_OVERFLOW );
+REG64_FLD( PERV_TOD_ERROR_REG_WOF_LOW_ORDER_STEP_COUNTER_PARITY    , 37  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_WOF_LOW_ORDER_STEP_COUNTER_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_0                           , 38  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_0 );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_1                           , 39  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_1 );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_2                           , 40  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_2 );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_3                           , 41  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_3 );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_4                           , 42  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_4 );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_5                           , 43  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_5 );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_SLAVE_ADDR_INVALID               , 44  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_SLAVE_ADDR_INVALID );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_SLAVE_WRITE_INVALID              , 45  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_SLAVE_WRITE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_SLAVE_READ_INVALID               , 46  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_SLAVE_READ_INVALID );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_SLAVE_ADDR_PARITY                , 47  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_SLAVE_ADDR_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_SLAVE_DATA_PARITY                , 48  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_SLAVE_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_0X27_DATA_PARITY                     , 49  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X27_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_MASTER_RSP_INFO                  , 50  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_MASTER_RSP_INFO );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_MASTER_RSP_INFO_LEN              , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_MASTER_RSP_INFO_LEN );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_INVALID                     , 53  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_REG_RX_TTYPE_4_DATA_PARITY               , 54  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_4_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_MASTER_REQUEST                   , 55  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_MASTER_REQUEST );
+REG64_FLD( PERV_TOD_ERROR_REG_PIB_RESET_DURING_PIB_ACCESS          , 56  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_RESET_DURING_PIB_ACCESS );
+REG64_FLD( PERV_TOD_ERROR_REG_EXTERNAL_XSTOP                       , 57  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXTERNAL_XSTOP );
+REG64_FLD( PERV_TOD_ERROR_REG_SPARE_58                             , 58  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_58   );
+REG64_FLD( PERV_TOD_ERROR_REG_SPARE_59                             , 59  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_59   );
+REG64_FLD( PERV_TOD_ERROR_REG_SPARE_60                             , 60  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_60   );
+REG64_FLD( PERV_TOD_ERROR_REG_SPARE_61                             , 61  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_61   );
+REG64_FLD( PERV_TOD_ERROR_REG_OSCSWITCH_INTERRUPT                  , 62  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_OSCSWITCH_INTERRUPT );
+REG64_FLD( PERV_TOD_ERROR_REG_SPARE_63                             , 63  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_63   );
+
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X00_DATA_PARITY             , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X00_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_M_PATH_0_PARITY              , 1   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_M_PATH_1_PARITY              , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X01_DATA_PARITY             , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X01_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X02_DATA_PARITY             , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X02_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X03_DATA_PARITY             , 5   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X03_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X04_DATA_PARITY             , 6   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X04_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X05_DATA_PARITY             , 7   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X05_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X06_DATA_PARITY             , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X06_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X07_DATA_PARITY             , 9   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X07_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_S_PATH_0_PARITY              , 10  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_S_PATH_0_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X08_DATA_PARITY             , 11  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X08_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X09_DATA_PARITY             , 12  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X09_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X0A_DATA_PARITY             , 13  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0A_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_M_PATH_0_STEP_CHECK          , 14  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_M_PATH_1_STEP_CHECK          , 15  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_S_PATH_0_STEP_CHECK          , 16  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_S_PATH_0_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_I_PATH_STEP_CHECK            , 17  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PSS_HAM_CORE_INTERRUPT_MASK  , 18  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PSS_HAM_CORE_INTERRUPT_MASK );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X0B_DATA_PARITY             , 19  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0B_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_S_PATH_1_PARITY              , 20  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_S_PATH_1_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_S_PATH_1_STEP_CHECK          , 21  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_S_PATH_1_STEP_CHECK );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_I_PATH_DELAY_STEP_CHECK_PARITY , 22  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_DELAY_STEP_CHECK_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X0C_DATA_PARITY             , 23  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0C_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY , 24  , SH_UNT_PERV     ,
+           SH_ACS_SCOM_RW  , SH_FLD_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X17_0X18_0X21_0X22_DATA_PARITY , 25  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X17_0X18_0X21_0X22_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X1D_0X1E_0X1F_DATA_PARITY   , 26  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X1D_0X1E_0X1F_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X20_DATA_PARITY             , 27  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X20_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X23_DATA_PARITY             , 28  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X23_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X24_DATA_PARITY             , 29  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X24_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X29_DATA_PARITY             , 30  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X29_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X30_0X31_0X32_0X33_DATA_PARITY , 31  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X30_0X31_0X32_0X33_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X10_DATA_PARITY             , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X10_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_I_PATH_SYNC_CHECK            , 33  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_SYNC_CHECK );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_I_PATH_FSM_STATE_PARITY      , 34  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_FSM_STATE_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_I_PATH_TIME_PARITY           , 35  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_TIME_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_I_PATH_TIME_OVERFLOW_CORE_INTERRUPT , 36  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_TIME_OVERFLOW_CORE_INTERRUPT );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_WOF_LOW_ORDER_STEP_COUNTER_PARITY , 37  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_WOF_LOW_ORDER_STEP_COUNTER_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_0                   , 38  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_0 );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_1                   , 39  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_1 );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_2                   , 40  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_2 );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_3                   , 41  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_3 );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_4                   , 42  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_4 );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_5                   , 43  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_5 );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_SLAVE_ADDR_INVALID       , 44  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_SLAVE_ADDR_INVALID );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_SLAVE_WRITE_INVALID      , 45  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_SLAVE_WRITE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_SLAVE_READ_INVALID       , 46  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_SLAVE_READ_INVALID );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_SLAVE_ADDR_PARITY        , 47  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_SLAVE_ADDR_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_SLAVE_DATA_PARITY        , 48  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_SLAVE_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_0X27_DATA_PARITY             , 49  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X27_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_MASTER_RSP_INFO          , 50  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_MASTER_RSP_INFO );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_MASTER_RSP_INFO_LEN      , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_MASTER_RSP_INFO_LEN );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_INVALID             , 53  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_INVALID );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_RX_TTYPE_4_DATA_PARITY       , 54  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_TTYPE_4_DATA_PARITY );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_MASTER_REQUEST           , 55  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_MASTER_REQUEST );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_PIB_RESET_DURING_PIB_ACCESS  , 56  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PIB_RESET_DURING_PIB_ACCESS );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_EXTERNAL_XSTOP               , 57  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXTERNAL_XSTOP );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_SPARE_58                     , 58  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_58   );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_SPARE_59                     , 59  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_59   );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_SPARE_60                     , 60  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_60   );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_SPARE_61                     , 61  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_61   );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_OSCSWITCH_INTERRUPT          , 62  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_OSCSWITCH_INTERRUPT );
+REG64_FLD( PERV_TOD_ERROR_ROUTING_REG_SPARE_63                     , 63  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE_63   );
+
+REG64_FLD( PERV_TOD_FSM_REG_I_PATH_STATE                           , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_I_PATH_STATE );
+REG64_FLD( PERV_TOD_FSM_REG_I_PATH_STATE_LEN                       , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_I_PATH_STATE_LEN );
+REG64_FLD( PERV_TOD_FSM_REG_IS_RUNNING                             , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_IS_RUNNING );
+REG64_FLD( PERV_TOD_FSM_REG_0X24_SPARE_05_07                       , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X24_SPARE_05_07 );
+REG64_FLD( PERV_TOD_FSM_REG_0X24_SPARE_05_07_LEN                   , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X24_SPARE_05_07_LEN );
+
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_DELAY_DISABLE                  , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DELAY_DISABLE );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_DELAY_ADJUST_DISABLE           , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DELAY_ADJUST_DISABLE );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_0X06_SPARE_02_04               , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X06_SPARE_02_04 );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_0X06_SPARE_02_04_LEN           , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X06_SPARE_02_04_LEN );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_STEP_SELECT         , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_STEP_CHECK_STEP_SELECT );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION       , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_STEP_CHECK_CPS_DEVIATION );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_LEN   , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_STEP_CHECK_CPS_DEVIATION_LEN );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_CONSTANT_CPS_ENABLE , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_STEP_CHECK_CONSTANT_CPS_ENABLE );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_VALIDITY_COUNT      , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_STEP_CHECK_VALIDITY_COUNT );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_STEP_CHECK_VALIDITY_COUNT_LEN  , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_STEP_CHECK_VALIDITY_COUNT_LEN );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_0X06_SPARE_16_21               , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X06_SPARE_16_21 );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_0X06_SPARE_16_21_LEN           , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X06_SPARE_16_21_LEN );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_DELAY_ADJUST_VALUE             , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DELAY_ADJUST_VALUE );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_DELAY_ADJUST_VALUE_LEN         , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_DELAY_ADJUST_VALUE_LEN );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_CPS                            , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_CPS        );
+REG64_FLD( PERV_TOD_I_PATH_CTRL_REG_CPS_LEN                        , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_CPS_LEN    );
+
+REG64_FLD( PERV_TOD_LOAD_TOD_MOD_REG_FSM_TRIGGER                   , 0   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_FSM_TRIGGER );
+REG64_FLD( PERV_TOD_LOAD_TOD_MOD_REG_FSM_SYNC_ENABLE               , 1   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_FSM_SYNC_ENABLE );
+
+REG64_FLD( PERV_TOD_LOAD_TOD_REG_VALUE                             , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUE      );
+REG64_FLD( PERV_TOD_LOAD_TOD_REG_VALUE_LEN                         , 60  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_VALUE_LEN  );
+REG64_FLD( PERV_TOD_LOAD_TOD_REG_WOF                               , 60  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_WOF        );
+REG64_FLD( PERV_TOD_LOAD_TOD_REG_WOF_LEN                           , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_WOF_LEN    );
+
+REG64_FLD( PERV_TOD_LOW_ORDER_STEP_REG_COUNTER_VALUE               , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_COUNTER_VALUE );
+REG64_FLD( PERV_TOD_LOW_ORDER_STEP_REG_COUNTER_VALUE_LEN           , 6   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_COUNTER_VALUE_LEN );
+REG64_FLD( PERV_TOD_LOW_ORDER_STEP_REG_0X23_SPARE_06_07            , 6   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X23_SPARE_06_07 );
+REG64_FLD( PERV_TOD_LOW_ORDER_STEP_REG_0X23_SPARE_06_07_LEN        , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X23_SPARE_06_07_LEN );
+
+REG64_FLD( PERV_TOD_MISC_RESET_REG_M_PATH_0_STEP_CREATE_THRESHOLD_ENABLE , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_0_STEP_CREATE_THRESHOLD_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_M_PATH_0_STEP_ALIGN_THRESHOLD_ENABLE , 1   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_0_STEP_ALIGN_THRESHOLD_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_M_PATH_1_STEP_CREATE_THRESHOLD_ENABLE , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_1_STEP_CREATE_THRESHOLD_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_M_PATH_1_STEP_ALIGN_THRESHOLD_ENABLE , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_1_STEP_ALIGN_THRESHOLD_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_0X0B_SPARE_04_05                , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0B_SPARE_04_05 );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_0X0B_SPARE_04_05_LEN            , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0B_SPARE_04_05_LEN );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_DISTR_STEP_SYNC_TX_SYNC_DISABLE , 6   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISTR_STEP_SYNC_TX_SYNC_DISABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_CORE_STEP_SYNC_TX_SYNC_DISABLE  , 7   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_CORE_STEP_SYNC_TX_SYNC_DISABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_PROBE_0_TOGGLE_ENABLE           , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PROBE_0_TOGGLE_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_PROBE_1_TOGGLE_ENABLE           , 9   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PROBE_1_TOGGLE_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_PROBE_2_TOGGLE_ENABLE           , 10  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PROBE_2_TOGGLE_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_PROBE_3_TOGGLE_ENABLE           , 11  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PROBE_3_TOGGLE_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_DISTR_STEP_SYNC_TX_DISABLE      , 12  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISTR_STEP_SYNC_TX_DISABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_DISTR_STEP_SYNC_TX_TRIGGER      , 13  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_DISTR_STEP_SYNC_TX_TRIGGER );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_CORE_STEP_SYNC_TX_ENABLE        , 14  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_CORE_STEP_SYNC_TX_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_CORE_STEP_SYNC_TX_TRIGGER       , 15  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_CORE_STEP_SYNC_TX_TRIGGER );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_TRACE_ENABLE                    , 16  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRACE_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_0X0B_SPARE_17                   , 17  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0B_SPARE_17 );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_TRACE_DATA_SELECT               , 18  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRACE_DATA_SELECT );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_TRACE_DATA_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRACE_DATA_SELECT_LEN );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_M_PATH_0_SYNC_CREATE_COUNTER_ENABLE , 20  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_0_SYNC_CREATE_COUNTER_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_M_PATH_1_SYNC_CREATE_COUNTER_ENABLE , 21  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_PATH_1_SYNC_CREATE_COUNTER_ENABLE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_I_PATH_DELAY_TWOS_COMPL_LOAD    , 22  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_I_PATH_DELAY_ADJUST             , 23  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_DELAY_ADJUST );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE , 24  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE_LEN , 9   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE_LEN );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_0X0B_SPARE_33_39                , 33  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0B_SPARE_33_39 );
+REG64_FLD( PERV_TOD_MISC_RESET_REG_0X0B_SPARE_33_39_LEN            , 7   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0B_SPARE_33_39_LEN );
+
+REG64_FLD( PERV_TOD_MOVE_TOD_TO_TB_REG_TRIGGER                     , 0   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_TRIGGER    );
+
+REG64_FLD( PERV_TOD_M_PATH_0_STEP_STEER_REG_MODE                   , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE       );
+REG64_FLD( PERV_TOD_M_PATH_0_STEP_STEER_REG_RATE                   , 1   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RATE       );
+REG64_FLD( PERV_TOD_M_PATH_0_STEP_STEER_REG_RATE_LEN               , 31  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RATE_LEN   );
+REG64_FLD( PERV_TOD_M_PATH_0_STEP_STEER_REG_COUNTER_LOAD_FLAG      , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_COUNTER_LOAD_FLAG );
+REG64_FLD( PERV_TOD_M_PATH_0_STEP_STEER_REG_COUNTER_LOAD_VALUE     , 33  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_COUNTER_LOAD_VALUE );
+REG64_FLD( PERV_TOD_M_PATH_0_STEP_STEER_REG_COUNTER_LOAD_VALUE_LEN , 31  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_COUNTER_LOAD_VALUE_LEN );
+
+REG64_FLD( PERV_TOD_M_PATH_1_STEP_STEER_REG_MODE                   , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE       );
+REG64_FLD( PERV_TOD_M_PATH_1_STEP_STEER_REG_RATE                   , 1   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RATE       );
+REG64_FLD( PERV_TOD_M_PATH_1_STEP_STEER_REG_RATE_LEN               , 31  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RATE_LEN   );
+REG64_FLD( PERV_TOD_M_PATH_1_STEP_STEER_REG_COUNTER_LOAD_FLAG      , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_COUNTER_LOAD_FLAG );
+REG64_FLD( PERV_TOD_M_PATH_1_STEP_STEER_REG_COUNTER_LOAD_VALUE     , 33  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_COUNTER_LOAD_VALUE );
+REG64_FLD( PERV_TOD_M_PATH_1_STEP_STEER_REG_COUNTER_LOAD_VALUE_LEN , 31  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_COUNTER_LOAD_VALUE_LEN );
+
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_OSC_NOT_VALID                , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_OSC_NOT_VALID );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_OSC_NOT_VALID                , 1   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_OSC_NOT_VALID );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_STEP_ALIGN_DISABLE           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_STEP_ALIGN_DISABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_STEP_ALIGN_DISABLE           , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_STEP_ALIGN_DISABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_STEP_CREATE_DUAL_EDGE_DISABLE  , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_STEP_CREATE_DUAL_EDGE_DISABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_SYNC_CREATE_SPS_SELECT         , 5   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_CREATE_SPS_SELECT );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_SYNC_CREATE_SPS_SELECT_LEN     , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SYNC_CREATE_SPS_SELECT_LEN );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION     , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_STEP_CHECK_CPS_DEVIATION );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION_LEN , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_STEP_CHECK_CPS_DEVIATION_LEN );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_CONSTANT_CPS_ENABLE , 12  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_STEP_CHECK_CONSTANT_CPS_ENABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT    , 13  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_STEP_CHECK_VALIDITY_COUNT );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT_LEN , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_STEP_CHECK_VALIDITY_COUNT_LEN );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION     , 16  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_STEP_CHECK_CPS_DEVIATION );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION_LEN , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_STEP_CHECK_CPS_DEVIATION_LEN );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_CONSTANT_CPS_ENABLE , 20  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_STEP_CHECK_CONSTANT_CPS_ENABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT    , 21  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_STEP_CHECK_VALIDITY_COUNT );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT_LEN , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_STEP_CHECK_VALIDITY_COUNT_LEN );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR , 24  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_LOCAL_STEP_MODE_ENABLE       , 26  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_LOCAL_STEP_MODE_ENABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_LOCAL_STEP_MODE_ENABLE       , 27  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_LOCAL_STEP_MODE_ENABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0_STEP_STEER_ENABLE            , 28  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_STEP_STEER_ENABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_1_STEP_STEER_ENABLE            , 29  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_STEP_STEER_ENABLE );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0X00_SPARE_30_31               , 30  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X00_SPARE_30_31 );
+REG64_FLD( PERV_TOD_M_PATH_CTRL_REG_0X00_SPARE_30_31_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X00_SPARE_30_31_LEN );
+
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_0_STEP_ALIGN_THRESHOLD       , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_STEP_ALIGN_THRESHOLD );
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_0_STEP_ALIGN_THRESHOLD_LEN   , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_STEP_ALIGN_THRESHOLD_LEN );
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_0_CPS                        , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_CPS      );
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_0_CPS_LEN                    , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_CPS_LEN  );
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_1_STEP_ALIGN_THRESHOLD       , 16  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_STEP_ALIGN_THRESHOLD );
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_1_STEP_ALIGN_THRESHOLD_LEN   , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_STEP_ALIGN_THRESHOLD_LEN );
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_1_CPS                        , 24  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_CPS      );
+REG64_FLD( PERV_TOD_M_PATH_STATUS_REG_1_CPS_LEN                    , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_CPS_LEN  );
+
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_RX_SELECT                  , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_SELECT  );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_RX_SELECT_LEN              , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_0X01_SPARE_03              , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X01_SPARE_03 );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X0_TX_SELECT               , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X0_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X1_TX_SELECT               , 6   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X1_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X2_TX_SELECT               , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X2_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X3_TX_SELECT               , 10  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X3_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X3_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X3_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X4_TX_SELECT               , 12  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X4_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X4_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X4_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X5_TX_SELECT               , 14  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X5_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X5_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X5_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X6_TX_SELECT               , 16  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X6_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X6_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X6_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X7_TX_SELECT               , 18  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X7_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X7_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X7_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X0_TX_ENABLE               , 20  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X1_TX_ENABLE               , 21  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X2_TX_ENABLE               , 22  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X3_TX_ENABLE               , 23  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X3_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X4_TX_ENABLE               , 24  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X4_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X5_TX_ENABLE               , 25  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X5_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X6_TX_ENABLE               , 26  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X6_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_X7_TX_ENABLE               , 27  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X7_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_0X01_SPARE_28_31           , 28  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X01_SPARE_28_31 );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_0X01_SPARE_28_31_LEN       , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X01_SPARE_28_31_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_I_PATH_DELAY_VALUE         , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_DELAY_VALUE );
+REG64_FLD( PERV_TOD_PRI_PORT_0_CTRL_REG_I_PATH_DELAY_VALUE_LEN     , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_DELAY_VALUE_LEN );
+
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_RX_SELECT                  , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_SELECT  );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_RX_SELECT_LEN              , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_0X02_SPARE_03              , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X02_SPARE_03 );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X0_TX_SELECT               , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X0_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X1_TX_SELECT               , 6   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X1_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X2_TX_SELECT               , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X2_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X3_TX_SELECT               , 10  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X3_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X3_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X3_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X4_TX_SELECT               , 12  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X4_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X4_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X4_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X5_TX_SELECT               , 14  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X5_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X5_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X5_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X6_TX_SELECT               , 16  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X6_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X6_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X6_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X7_TX_SELECT               , 18  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X7_TX_SELECT );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X7_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X7_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X0_TX_ENABLE               , 20  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X1_TX_ENABLE               , 21  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X2_TX_ENABLE               , 22  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X3_TX_ENABLE               , 23  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X3_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X4_TX_ENABLE               , 24  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X4_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X5_TX_ENABLE               , 25  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X5_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X6_TX_ENABLE               , 26  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X6_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_X7_TX_ENABLE               , 27  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X7_TX_ENABLE );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_0X02_SPARE_28_31           , 28  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X02_SPARE_28_31 );
+REG64_FLD( PERV_TOD_PRI_PORT_1_CTRL_REG_0X02_SPARE_28_31_LEN       , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X02_SPARE_28_31_LEN );
+
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_0_DATA                        , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_DATA     );
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_0_DATA_LEN                    , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_DATA_LEN );
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_1_DATA                        , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_DATA     );
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_1_DATA_LEN                    , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_DATA_LEN );
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_2_DATA                        , 16  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_2_DATA     );
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_2_DATA_LEN                    , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_2_DATA_LEN );
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_3_DATA                        , 24  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_3_DATA     );
+REG64_FLD( PERV_TOD_PROBE_SELECT_REG_3_DATA_LEN                    , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_3_DATA_LEN );
+
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_M_PATH_SELECT             , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRI_M_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_M_S_SELECT                , 1   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRI_M_S_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_M_S_DRAWER_SELECT         , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRI_M_S_DRAWER_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_S_PATH_1_STEP_CHECK_ENABLE , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRI_S_PATH_1_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_M_PATH_0_STEP_CHECK_ENABLE , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRI_M_PATH_0_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_M_PATH_1_STEP_CHECK_ENABLE , 5   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRI_M_PATH_1_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_S_PATH_0_STEP_CHECK_ENABLE , 6   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRI_S_PATH_0_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_PRI_I_PATH_STEP_CHECK_ENABLE  , 7   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRI_I_PATH_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_M_PATH_SELECT             , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEC_M_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_M_S_SELECT                , 9   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEC_M_S_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_M_S_DRAWER_SELECT         , 10  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEC_M_S_DRAWER_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_S_PATH_1_STEP_CHECK_ENABLE , 11  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEC_S_PATH_1_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_M_PATH_0_STEP_CHECK_ENABLE , 12  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEC_M_PATH_0_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_M_PATH_1_STEP_CHECK_ENABLE , 13  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEC_M_PATH_1_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_S_PATH_0_STEP_CHECK_ENABLE , 14  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEC_S_PATH_0_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SEC_I_PATH_STEP_CHECK_ENABLE  , 15  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEC_I_PATH_STEP_CHECK_ENABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_SWITCH_SYNC_ERROR_DISABLE     , 16  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SWITCH_SYNC_ERROR_DISABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_I_PATH_STEP_CHECK_CPS_DEVIATION_X_DISABLE , 17  , SH_UNT_PERV     ,
+           SH_ACS_SCOM_RW  , SH_FLD_I_PATH_STEP_CHECK_CPS_DEVIATION_X_DISABLE );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_STEP_CHECK_ENABLE_CHICKEN_SWITCH , 18  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_STEP_CHECK_ENABLE_CHICKEN_SWITCH );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_0X07_SPARE_19                 , 19  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X07_SPARE_19 );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_0X07_SPARE_20                 , 20  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X07_SPARE_20 );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_MISC_RESYNC_OSC_FROM          , 21  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_MISC_RESYNC_OSC_FROM );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_0X07_SPARE_22_31              , 22  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X07_SPARE_22_31 );
+REG64_FLD( PERV_TOD_PSS_MSS_CTRL_REG_0X07_SPARE_22_31_LEN          , 10  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X07_SPARE_22_31_LEN );
+
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_PRI_SEC_SELECT              , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PRI_SEC_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_PRI_SEC_SELECT_LEN          , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PRI_SEC_SELECT_LEN );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_0X08_SPARE_03               , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X08_SPARE_03 );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_0_OSC_NOT_VALID      , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_M_PATH_0_OSC_NOT_VALID );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_1_OSC_NOT_VALID      , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_M_PATH_1_OSC_NOT_VALID );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_0_STEP_CHECK_VALID   , 6   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_M_PATH_0_STEP_CHECK_VALID );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_1_STEP_CHECK_VALID   , 7   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_M_PATH_1_STEP_CHECK_VALID );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_S_PATH_0_STEP_CHECK_VALID   , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_S_PATH_0_STEP_CHECK_VALID );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_I_PATH_STEP_CHECK_VALID     , 9   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_I_PATH_STEP_CHECK_VALID );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_S_PATH_1_STEP_CHECK_VALID   , 10  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_S_PATH_1_STEP_CHECK_VALID );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_IS_SPECIAL                  , 11  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_IS_SPECIAL );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_PRI_M_PATH_SELECT           , 12  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PRI_M_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_PRI_M_S_SELECT              , 13  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PRI_M_S_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_PRI_M_S_DRAWER_SELECT       , 14  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PRI_M_S_DRAWER_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_PRI_S_PATH_SELECT           , 15  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PRI_S_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_SEC_M_PATH_SELECT           , 16  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SEC_M_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_SEC_M_S_SELECT              , 17  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SEC_M_S_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_SEC_M_S_DRAWER_SELECT       , 18  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SEC_M_S_DRAWER_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_SEC_S_PATH_SELECT           , 19  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_SEC_S_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_IS_RUNNING                  , 20  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_IS_RUNNING );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_IS_PRIMARY                  , 21  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_IS_PRIMARY );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_IS_SECONDARY                , 22  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_IS_SECONDARY );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_IS_ACTIVE_MASTER            , 23  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_IS_ACTIVE_MASTER );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_IS_BACKUP_MASTER            , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_IS_BACKUP_MASTER );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_IS_SLAVE                    , 25  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_IS_SLAVE   );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_SELECT               , 26  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_M_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_S_PATH_SELECT               , 27  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_S_PATH_SELECT );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_0_STEP_ALIGN_VALID_SWITCH , 28  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_M_PATH_0_STEP_ALIGN_VALID_SWITCH );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_1_STEP_ALIGN_VALID_SWITCH , 29  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_M_PATH_1_STEP_ALIGN_VALID_SWITCH );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_0X08_SPARE_30               , 30  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X08_SPARE_30 );
+REG64_FLD( PERV_TOD_PSS_MSS_STATUS_REG_M_PATH_SWITCH_TRIGGER       , 31  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_M_PATH_SWITCH_TRIGGER );
+
+REG64_FLD( PERV_TOD_RX_TTYPE_CTRL_REG_DATA                         , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( PERV_TOD_RX_TTYPE_CTRL_REG_DATA_LEN                     , 64  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_RX_SELECT                  , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_SELECT  );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_RX_SELECT_LEN              , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_0X03_SPARE_03              , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X03_SPARE_03 );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X0_TX_SELECT               , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X0_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X1_TX_SELECT               , 6   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X1_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X2_TX_SELECT               , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X2_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X3_TX_SELECT               , 10  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X3_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X3_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X3_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X4_TX_SELECT               , 12  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X4_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X4_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X4_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X5_TX_SELECT               , 14  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X5_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X5_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X5_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X6_TX_SELECT               , 16  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X6_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X6_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X6_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X7_TX_SELECT               , 18  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X7_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X7_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X7_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X0_TX_ENABLE               , 20  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X1_TX_ENABLE               , 21  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X2_TX_ENABLE               , 22  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X3_TX_ENABLE               , 23  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X3_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X4_TX_ENABLE               , 24  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X4_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X5_TX_ENABLE               , 25  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X5_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X6_TX_ENABLE               , 26  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X6_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_X7_TX_ENABLE               , 27  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X7_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_0X03_SPARE_28_31           , 28  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X03_SPARE_28_31 );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_0X03_SPARE_28_31_LEN       , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X03_SPARE_28_31_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_I_PATH_DELAY_VALUE         , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_DELAY_VALUE );
+REG64_FLD( PERV_TOD_SEC_PORT_0_CTRL_REG_I_PATH_DELAY_VALUE_LEN     , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_PATH_DELAY_VALUE_LEN );
+
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_RX_SELECT                  , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_SELECT  );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_RX_SELECT_LEN              , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_0X04_SPARE_03              , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X04_SPARE_03 );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X0_TX_SELECT               , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X0_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X1_TX_SELECT               , 6   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X1_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X2_TX_SELECT               , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X2_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X3_TX_SELECT               , 10  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X3_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X3_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X3_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X4_TX_SELECT               , 12  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X4_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X4_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X4_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X5_TX_SELECT               , 14  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X5_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X5_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X5_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X6_TX_SELECT               , 16  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X6_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X6_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X6_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X7_TX_SELECT               , 18  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X7_TX_SELECT );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X7_TX_SELECT_LEN           , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X7_TX_SELECT_LEN );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X0_TX_ENABLE               , 20  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X0_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X1_TX_ENABLE               , 21  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X1_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X2_TX_ENABLE               , 22  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X2_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X3_TX_ENABLE               , 23  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X3_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X4_TX_ENABLE               , 24  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X4_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X5_TX_ENABLE               , 25  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X5_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X6_TX_ENABLE               , 26  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X6_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_X7_TX_ENABLE               , 27  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_X7_TX_ENABLE );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_0X04_SPARE_28_31           , 28  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X04_SPARE_28_31 );
+REG64_FLD( PERV_TOD_SEC_PORT_1_CTRL_REG_0X04_SPARE_28_31_LEN       , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X04_SPARE_28_31_LEN );
+
+REG64_FLD( PERV_TOD_START_TOD_REG_FSM_TRIGGER                      , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FSM_TRIGGER );
+REG64_FLD( PERV_TOD_START_TOD_REG_0X22_SPARE_01                    , 1   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X22_SPARE_01 );
+REG64_FLD( PERV_TOD_START_TOD_REG_FSM_DATA02                       , 2   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_FSM_DATA02 );
+REG64_FLD( PERV_TOD_START_TOD_REG_0X22_SPARE_03_07                 , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X22_SPARE_03_07 );
+REG64_FLD( PERV_TOD_START_TOD_REG_0X22_SPARE_03_07_LEN             , 5   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X22_SPARE_03_07_LEN );
+
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_PRI_SELECT                     , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PRI_SELECT );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_0X05_SPARE_01                  , 1   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X05_SPARE_01 );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_M_CPS_ENABLE                   , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_CPS_ENABLE );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_DISABLE            , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_REMOTE_SYNC_DISABLE );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_SEC_SELECT                     , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SEC_SELECT );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_0X05_SPARE_05                  , 5   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X05_SPARE_05 );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR , 6   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN , 2   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION     , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_STEP_CHECK_CPS_DEVIATION );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION_LEN , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_STEP_CHECK_CPS_DEVIATION_LEN );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_0_STEP_CHECK_CONSTANT_CPS_ENABLE , 12  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_STEP_CHECK_CONSTANT_CPS_ENABLE );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT    , 13  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_STEP_CHECK_VALIDITY_COUNT );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT_LEN , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_STEP_CHECK_VALIDITY_COUNT_LEN );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION     , 16  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_STEP_CHECK_CPS_DEVIATION );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION_LEN , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_STEP_CHECK_CPS_DEVIATION_LEN );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_1_STEP_CHECK_CONSTANT_CPS_ENABLE , 20  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_STEP_CHECK_CONSTANT_CPS_ENABLE );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT    , 21  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_STEP_CHECK_VALIDITY_COUNT );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT_LEN , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_STEP_CHECK_VALIDITY_COUNT_LEN );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_ERROR_DISABLE      , 24  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_REMOTE_SYNC_ERROR_DISABLE );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_CHECK_M_CPS_DISABLE , 25  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_REMOTE_SYNC_CHECK_M_CPS_DISABLE );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR , 26  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR_LEN , 2   , SH_UNT_PERV     ,
+           SH_ACS_SCOM_RW  , SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR_LEN );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_CHECK_CPS_DEVIATION , 28  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_CHECK_CPS_DEVIATION_LEN , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_LEN );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_MISS_COUNT_MAX     , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX );
+REG64_FLD( PERV_TOD_S_PATH_CTRL_REG_REMOTE_SYNC_MISS_COUNT_MAX_LEN , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX_LEN );
+
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_M_0_STEP_ALIGN_FSM_STATE     , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_0_STEP_ALIGN_FSM_STATE );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_M_0_STEP_ALIGN_FSM_STATE_LEN , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_0_STEP_ALIGN_FSM_STATE_LEN );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_M_1_STEP_ALIGN_FSM_STATE     , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_1_STEP_ALIGN_FSM_STATE );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_M_1_STEP_ALIGN_FSM_STATE_LEN , 4   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_M_1_STEP_ALIGN_FSM_STATE_LEN );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_I_DELAY_ADJUST_RATIO         , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_DELAY_ADJUST_RATIO );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_I_DELAY_ADJUST_RATIO_LEN     , 5   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_I_DELAY_ADJUST_RATIO_LEN );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_0X0A_SPARE_13_15             , 13  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0A_SPARE_13_15 );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_0X0A_SPARE_13_15_LEN         , 3   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0X0A_SPARE_13_15_LEN );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_0_CPS                        , 16  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_CPS      );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_0_CPS_LEN                    , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_CPS_LEN  );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_1_CPS                        , 24  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_CPS      );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_1_CPS_LEN                    , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_CPS_LEN  );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_0_REMOTE_SYNC_LATE_SYNC_COUNT , 32  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_0_REMOTE_SYNC_LATE_SYNC_COUNT_LEN , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT_LEN );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_1_REMOTE_SYNC_LATE_SYNC_COUNT , 40  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT );
+REG64_FLD( PERV_TOD_S_PATH_STATUS_REG_1_REMOTE_SYNC_LATE_SYNC_COUNT_LEN , 8   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT_LEN );
+
+REG64_FLD( PERV_TOD_TIMER_REG_VALUE                                , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_VALUE      );
+REG64_FLD( PERV_TOD_TIMER_REG_VALUE_LEN                            , 60  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_VALUE_LEN  );
+REG64_FLD( PERV_TOD_TIMER_REG_0X0D_SPARE_60_62                     , 60  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X0D_SPARE_60_62 );
+REG64_FLD( PERV_TOD_TIMER_REG_0X0D_SPARE_60_62_LEN                 , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X0D_SPARE_60_62_LEN );
+REG64_FLD( PERV_TOD_TIMER_REG_STATUS                               , 63  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_STATUS     );
+
+REG64_FLD( PERV_TOD_TRACE_DATA_1_REG_SET                           , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET        );
+REG64_FLD( PERV_TOD_TRACE_DATA_1_REG_SET_LEN                       , 64  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_LEN    );
+
+REG64_FLD( PERV_TOD_TRACE_DATA_2_REG_SET                           , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET        );
+REG64_FLD( PERV_TOD_TRACE_DATA_2_REG_SET_LEN                       , 64  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_LEN    );
+
+REG64_FLD( PERV_TOD_TRACE_DATA_3_REG_SET                           , 0   , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET        );
+REG64_FLD( PERV_TOD_TRACE_DATA_3_REG_SET_LEN                       , 64  , SH_UNT_PERV     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SET_LEN    );
+
+REG64_FLD( PERV_TOD_TX_TTYPE_0_REG_TRIGGER                         , 0   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_TRIGGER    );
+
+REG64_FLD( PERV_TOD_TX_TTYPE_1_REG_TRIGGER                         , 0   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_TRIGGER    );
+
+REG64_FLD( PERV_TOD_TX_TTYPE_2_REG_TRIGGER                         , 0   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_TRIGGER    );
+
+REG64_FLD( PERV_TOD_TX_TTYPE_3_REG_TRIGGER                         , 0   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_TRIGGER    );
+
+REG64_FLD( PERV_TOD_TX_TTYPE_4_REG_TRIGGER                         , 0   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_TRIGGER    );
+
+REG64_FLD( PERV_TOD_TX_TTYPE_5_REG_TRIGGER                         , 0   , SH_UNT_PERV     , SH_ACS_SCOM_WO  ,
+           SH_FLD_TRIGGER    );
+
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_MOVE_TO_TB_CORE_ADDRESS      , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MOVE_TO_TB_CORE_ADDRESS );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_MOVE_TO_TB_CORE_ADDRESS_LEN  , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MOVE_TO_TB_CORE_ADDRESS_LEN );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_MOVE_TO_TB_CORE_ID           , 24  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MOVE_TO_TB_CORE_ID );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_MOVE_TO_TB_CORE_ID_LEN       , 8   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MOVE_TO_TB_CORE_ID_LEN );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_4_SEND_MODE                  , 32  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_4_SEND_MODE );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_4_SEND_ENABLE                , 33  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_4_SEND_ENABLE );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_0X27_SPARE_34                , 34  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X27_SPARE_34 );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_MOVE_TO_TB_CORE_ADDRESS_ENABLE , 35  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_MOVE_TO_TB_CORE_ADDRESS_ENABLE );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_0X27_SPARE_36                , 36  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_0X27_SPARE_36 );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_PIB_FSM_STATE                , 37  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PIB_FSM_STATE );
+REG64_FLD( PERV_TOD_TX_TTYPE_CTRL_REG_PIB_FSM_STATE_LEN            , 3   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_PIB_FSM_STATE_LEN );
+
+REG64_FLD( PERV_TOD_VALUE_REG_VALUE                                , 0   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_VALUE      );
+REG64_FLD( PERV_TOD_VALUE_REG_VALUE_LEN                            , 60  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_VALUE_LEN  );
+REG64_FLD( PERV_TOD_VALUE_REG_WOF_COUNTER                          , 60  , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_WOF_COUNTER );
+REG64_FLD( PERV_TOD_VALUE_REG_WOF_COUNTER_LEN                      , 4   , SH_UNT_PERV     , SH_ACS_SCOM     ,
+           SH_FLD_WOF_COUNTER_LEN );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG_DATA           , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN       , 64  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_DATA           , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN       , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS        , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN    , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK      , 42  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN  , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN   , 52  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING        , 53  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS   , 54  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA   , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB   , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC   , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND   , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA      , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN  , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB      , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN  , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC      , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN  , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD      , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN  , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_HI_DATA_REG_DATA           , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN       , 64  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_DATA           , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN       , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS        , 32  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN    , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK      , 42  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN  , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN   , 52  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING        , 53  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS   , 54  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA   , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB   , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC   , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND   , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA      , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN  , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB      , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN  , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC      , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN  , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD      , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN  , 24  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_PERV_1   ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG32_FLD( PERV_FSI2PIB_TRUE_MASK_REG                              , 0   , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG        );
+REG32_FLD( PERV_FSI2PIB_TRUE_MASK_REG_LEN                          , 32  , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG_LEN    );
+
+REG32_FLD( PERV_FSISHIFT_TRUE_MASK_REG                             , 0   , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG        );
+REG32_FLD( PERV_FSISHIFT_TRUE_MASK_REG_LEN                         , 32  , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ,
+           SH_FLD_REG_LEN    );
+
+REG32_FLD( PERV_FSII2C_WATER_MARK_REGISTER_A_WATERMARK_REG_0       , 16  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_WATERMARK_REG_0 );
+REG32_FLD( PERV_FSII2C_WATER_MARK_REGISTER_A_WATERMARK_REG_0_LEN   , 16  , SH_UNT_PERV_FSII2C, SH_ACS_SCOM     ,
+           SH_FLD_WATERMARK_REG_0_LEN );
+
+REG64_FLD( PERV_1_WRITE_PROTECT_ENABLE_REG_RING_LOCKING            , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RING_LOCKING );
+REG64_FLD( PERV_1_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING   , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_RING_LOCKING );
+
+REG64_FLD( PERV_1_WRITE_PROTECT_RINGS_REG_RINGS                    , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RINGS      );
+REG64_FLD( PERV_1_WRITE_PROTECT_RINGS_REG_RINGS_LEN                , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_RINGS_LEN  );
+
+REG64_FLD( PERV_1_XFIR_IN0                                         , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( PERV_1_XFIR_IN1                                         , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN1        );
+REG64_FLD( PERV_1_XFIR_IN2                                         , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN2        );
+REG64_FLD( PERV_1_XFIR_IN3                                         , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN3        );
+REG64_FLD( PERV_1_XFIR_IN4                                         , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( PERV_1_XFIR_IN5                                         , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( PERV_1_XFIR_IN6                                         , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN6        );
+REG64_FLD( PERV_1_XFIR_IN7                                         , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN7        );
+REG64_FLD( PERV_1_XFIR_IN8                                         , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN8        );
+REG64_FLD( PERV_1_XFIR_IN9                                         , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN9        );
+REG64_FLD( PERV_1_XFIR_IN10                                        , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN10       );
+REG64_FLD( PERV_1_XFIR_IN11                                        , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN11       );
+REG64_FLD( PERV_1_XFIR_IN12                                        , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN12       );
+REG64_FLD( PERV_1_XFIR_IN13                                        , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN13       );
+REG64_FLD( PERV_1_XFIR_IN14                                        , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN14       );
+REG64_FLD( PERV_1_XFIR_IN15                                        , 15  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN15       );
+REG64_FLD( PERV_1_XFIR_IN16                                        , 16  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN16       );
+REG64_FLD( PERV_1_XFIR_IN17                                        , 17  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN17       );
+REG64_FLD( PERV_1_XFIR_IN18                                        , 18  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN18       );
+REG64_FLD( PERV_1_XFIR_IN19                                        , 19  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN19       );
+REG64_FLD( PERV_1_XFIR_IN20                                        , 20  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN20       );
+REG64_FLD( PERV_1_XFIR_IN21                                        , 21  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN21       );
+REG64_FLD( PERV_1_XFIR_IN21_LEN                                    , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN21_LEN   );
+REG64_FLD( PERV_1_XFIR_IN26                                        , 26  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_IN26       );
+
+REG64_FLD( PERV_1_XSTOP1_MASK_B                                    , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASK_B     );
+REG64_FLD( PERV_1_XSTOP1_UNUSED                                    , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PERV_1_XSTOP1_TRIGGER_OPCG_ON                           , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( PERV_1_XSTOP1_WAIT_ALLWAYS                              , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( PERV_1_XSTOP1_PERV                                      , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( PERV_1_XSTOP1_UNIT1                                     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( PERV_1_XSTOP1_UNIT2                                     , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( PERV_1_XSTOP1_UNIT3                                     , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( PERV_1_XSTOP1_UNIT4                                     , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( PERV_1_XSTOP1_UNIT5                                     , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( PERV_1_XSTOP1_UNIT6                                     , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( PERV_1_XSTOP1_UNIT7                                     , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( PERV_1_XSTOP1_UNIT8                                     , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( PERV_1_XSTOP1_UNIT9                                     , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( PERV_1_XSTOP1_UNIT10                                    , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( PERV_1_XSTOP1_WAIT_CYCLES                               , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( PERV_1_XSTOP1_WAIT_CYCLES_LEN                           , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( PERV_1_XSTOP2_MASK_B                                    , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASK_B     );
+REG64_FLD( PERV_1_XSTOP2_UNUSED                                    , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PERV_1_XSTOP2_TRIGGER_OPCG_ON                           , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( PERV_1_XSTOP2_WAIT_ALLWAYS                              , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( PERV_1_XSTOP2_PERV                                      , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( PERV_1_XSTOP2_UNIT1                                     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( PERV_1_XSTOP2_UNIT2                                     , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( PERV_1_XSTOP2_UNIT3                                     , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( PERV_1_XSTOP2_UNIT4                                     , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( PERV_1_XSTOP2_UNIT5                                     , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( PERV_1_XSTOP2_UNIT6                                     , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( PERV_1_XSTOP2_UNIT7                                     , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( PERV_1_XSTOP2_UNIT8                                     , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( PERV_1_XSTOP2_UNIT9                                     , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( PERV_1_XSTOP2_UNIT10                                    , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( PERV_1_XSTOP2_WAIT_CYCLES                               , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( PERV_1_XSTOP2_WAIT_CYCLES_LEN                           , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( PERV_1_XSTOP3_MASK_B                                    , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASK_B     );
+REG64_FLD( PERV_1_XSTOP3_UNUSED                                    , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( PERV_1_XSTOP3_TRIGGER_OPCG_ON                           , 2   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( PERV_1_XSTOP3_WAIT_ALLWAYS                              , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( PERV_1_XSTOP3_PERV                                      , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( PERV_1_XSTOP3_UNIT1                                     , 5   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( PERV_1_XSTOP3_UNIT2                                     , 6   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( PERV_1_XSTOP3_UNIT3                                     , 7   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( PERV_1_XSTOP3_UNIT4                                     , 8   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( PERV_1_XSTOP3_UNIT5                                     , 9   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( PERV_1_XSTOP3_UNIT6                                     , 10  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( PERV_1_XSTOP3_UNIT7                                     , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( PERV_1_XSTOP3_UNIT8                                     , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( PERV_1_XSTOP3_UNIT9                                     , 13  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( PERV_1_XSTOP3_UNIT10                                    , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( PERV_1_XSTOP3_WAIT_CYCLES                               , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( PERV_1_XSTOP3_WAIT_CYCLES_LEN                           , 12  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( PERV_1_XTRA_TRACE_MODE_DATA                             , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DATA       );
+REG64_FLD( PERV_1_XTRA_TRACE_MODE_DATA_LEN                         , 38  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_DATA_LEN   );
+
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9_perv_scom_addresses_fld_fixes.H b/src/import/chips/p9/common/include/p9_perv_scom_addresses_fld_fixes.H
new file mode 100644
index 00000000..5baf3510
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_perv_scom_addresses_fld_fixes.H
@@ -0,0 +1,133 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_perv_scom_addresses_fld_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file perv_scom_addresses_fld_fixes.H
+/// @brief The *scom_addresses_fld.H files are generated form figtree,
+///        but the figree can be wrong.  This file is included in
+///        *_scom_addresses_fld.H and allows incorrect constants to be
+///        fixed manually.
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SAO
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#include <p9_const_common.H>
+
+#ifndef __P9_PERV_SCOM_ADDRESSES_FLD_FIXES_H
+#define __P9_PERV_SCOM_ADDRESSES_FLD_FIXES_H
+
+#include <p9_perv_scom_addresses_fixes.H>
+
+//Example
+//Copy the whole line from the *scom_addresses_fld.H file.  Then add FIX in front of REG
+//and add another paramter that is the new value you want.
+//
+//FIXREG64_FLD( PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE, 24, SH_UNT, SH_ACS_SCOM, SH_FLD_FBC_WITH_TM_QUIESCE,
+//              12);
+
+//static const uint64_t SH_UNT_PERV_CBS_ENVSTAT = 514;
+static const uint64_t SH_FLD_C4_TEST_ENABLE = 32000;
+static const uint64_t SH_FLD_C4_CARD_TEST_BSC = 32001;
+static const uint64_t SH_FLD_C4_VDN_GPOOD = 32002;
+static const uint64_t SH_FLD_C4_FSI_IN_ENA = 32003;
+static const uint64_t SH_FLD_C4_CHIP_MASTER = 32004;
+static const uint64_t SH_FLD_C4_SMD = 32005;
+static const uint64_t SH_FLD_CLOCK_REGION_ALL_UNITS = 32006;
+static const uint64_t SH_FLD_CLOCK_REGION_ALL_UNITS_LEN = 32007;
+static const uint64_t SH_FLD_SEL_THOLD_ALL = 32008;
+static const uint64_t SH_FLD_SEL_THOLD_ALL_LEN = 32009;
+static const uint64_t SH_FLD_ALL_UNITS = 32010;
+static const uint64_t SH_FLD_ALL_UNITS_LEN = 32011;
+static const uint64_t SH_FLD_TC_ALL_REGIONS_FENCE = 32012;
+static const uint64_t SH_FLD_TC_ALL_REGIONS_FENCE_LEN = 32013;
+static const uint64_t SH_FLD_SCAN_REGION_ALL_UNITS = 32014;
+static const uint64_t SH_FLD_SCAN_REGION_ALL_UNITS_LEN = 32015;
+static const uint64_t SH_FLD_SCAN_ALL_TYPES = 32016;
+static const uint64_t SH_FLD_SCAN_ALL_TYPES_LEN = 32017;
+
+REG64_FLD( PERV_CBS_ENVSTAT_C4_TEST_ENABLE                        , 0   , SH_UNT_PERV_CBS_ENVSTAT     ,
+           SH_ACS_SCOM     ,
+           SH_FLD_C4_TEST_ENABLE );
+REG64_FLD( PERV_CBS_ENVSTAT_C4_CARD_TEST_BSC                      , 1   , SH_UNT_PERV_CBS_ENVSTAT     ,
+           SH_ACS_SCOM     ,
+           SH_FLD_C4_CARD_TEST_BSC );
+REG64_FLD( PERV_CBS_ENVSTAT_C4_VDN_GPOOD                          , 2   , SH_UNT_PERV_CBS_ENVSTAT     ,
+           SH_ACS_SCOM     ,
+           SH_FLD_C4_VDN_GPOOD );
+REG64_FLD( PERV_CBS_ENVSTAT_C4_FSI_IN_ENA                         , 3   , SH_UNT_PERV_CBS_ENVSTAT     ,
+           SH_ACS_SCOM     ,
+           SH_FLD_C4_FSI_IN_ENA );
+REG64_FLD( PERV_CBS_ENVSTAT_C4_CHIP_MASTER                        , 4   , SH_UNT_PERV_CBS_ENVSTAT     ,
+           SH_ACS_SCOM     ,
+           SH_FLD_C4_CHIP_MASTER );
+REG64_FLD( PERV_CBS_ENVSTAT_C4_SMD                                , 5   , SH_UNT_PERV_CBS_ENVSTAT     ,
+           SH_ACS_SCOM     ,
+           SH_FLD_C4_SMD );
+
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_REGION_ALL_UNITS           , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_REGION_ALL_UNITS );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_REGION_ALL_UNITS_LEN       , 11  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_REGION_ALL_UNITS_LEN );
+REG64_FLD( PERV_1_CLK_REGION_SEL_THOLD_ALL                    , 48  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_ALL );
+REG64_FLD( PERV_1_CLK_REGION_SEL_THOLD_ALL_LEN                , 3   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_ALL_LEN );
+REG64_FLD( PERV_1_CLK_REGION_CLOCK_REGION_PERV                , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_PERV );
+
+REG64_FLD( PERV_1_BIST_TC_BIST_START_TEST_DC                      , 0   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_TC_START_TEST_DC );
+REG64_FLD( PERV_1_BIST_BIST_ALL_UNITS                             , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ALL_UNITS );
+REG64_FLD( PERV_1_BIST_BIST_ALL_UNITS_LEN                         , 11   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_ALL_UNITS_LEN );
+
+REG64_FLD( PERV_1_OPCG_GO                                         , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GO );
+REG64_FLD( PERV_1_OPCG_STARTS_BIST                                , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STARTS_BIST );
+
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_ALL_REGIONS_FENCE                 , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_ALL_REGIONS_FENCE );
+REG64_FLD( PERV_1_CPLT_CTRL1_TC_ALL_REGIONS_FENCE_LEN             , 11   , SH_UNT_PERV_1   , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_ALL_REGIONS_FENCE_LEN );
+
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_SCAN_REGION_ALL_UNITS          , 4   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_REGION_ALL_UNITS );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_SCAN_REGION_ALL_UNITS_LEN      , 11   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_REGION_ALL_UNITS_LEN );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_SCAN_ALL_TYPES                 , 48   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_ALL_TYPES );
+REG64_FLD( PERV_1_SCAN_REGION_TYPE_SCAN_ALL_TYPES_LEN             , 12   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_ALL_TYPES_LEN );
+
+REG64_FLD( PERV_1_OPCG_REG0_OPCG_STARTS_BIST                       , 14  , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_STARTS_BIST );
+REG64_FLD( PERV_1_OPCG_REG0_OPCG_GO                                , 1   , SH_UNT_PERV_1   , SH_ACS_SCOM     ,
+           SH_FLD_GO         );
+
+#endif
diff --git a/src/import/chips/p9/common/include/p9_quad_scom_addresses.H b/src/import/chips/p9/common/include/p9_quad_scom_addresses.H
new file mode 100644
index 00000000..878f0e6b
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_quad_scom_addresses.H
@@ -0,0 +1,24050 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_quad_scom_addresses.H $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_quad_scom_addresses.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+/*---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ *
+ *  Issues:
+ *
+ * Closed
+ *    TOD reg same address.             HW323439
+ *       - Issue was closed with the explaination "same as p8"
+ *    IO0 registers need fixed.         HW320437
+ *    PHB registers need fixed.         HW320416  ( all regs commented out now )
+ *    OSC/perv regs same address.       HW323437
+ *    MC regs with same address.        HW323435 (matteo)
+ *         Duplicate IOM registers.          HW320456 (designers)
+ *    PEC Sat_id issue                  HW329652
+ *    PB.PB_PPE registers need fixed.   HW320435
+ *    EX05 registers need fixed.        HW320427  (9020) - L2 ring id's are incorrect
+ *    IOFPPE registers need fixed.      HW320424  (9020) - Investigate NULL scope
+ *    PEC addresses are wrong.          HW322598  (9020)
+ *    MC registers need fixed.          HW320433
+ *    VA.VA_NORTH registers need fixed. HW320436
+ *
+ * Format:
+ *
+ *  <UNIT>_<SUBUNIT>_<INSTANCE>_<REGISTER>_<ACCESS/TYPE>
+ *
+ *  Notes: Subunits are only added to make names unique when
+ *  there are name collisions.
+ *  Only units with more than one instance has instance numbers.
+ *  If there is only one, the instance number is omitted.
+ *
+ *  Instance numbers are chiplet id's for the PERV unit.  The
+ *  chiplet id's are mapped to their name and used instead of
+ *  instance numbers.  See bellow.
+ *
+ *  For registers with a single access type the type and access
+ *  methods are omitted.
+ *
+ *  For access types where all bits have the same access methods, the
+ *  access method is appended to the name.  If the access methods
+ *  are different for some bits, the access type is appended to the
+ *  name _SCOM instead of _RO.  The _RW(X) access method is omitted
+ *  and assumed to be default.
+ *
+ *  Valid units / subunits
+ *    PU                    : No unit chip level
+ *        MCD0[0..1]        : mcd subunit
+ *        PIB2OPB[0..1]     : PIB2OPB subunit
+ *        OTPROM[0..1]      : otprom subunit
+ *        NPU               : common npu subunit
+ *        NPU[0..2]         : Npu stacks 0 to 2
+ *          CTL             : Npu CTL subunit
+ *          DAT             : Npu DAT subunit
+ *          SM[0..3]        : Npu SM subunits
+ *          NTL[0..1]       : Npu NTL subunit
+ *    PERV                  : Pervasive
+ *        FSI2PIB           : subunit
+ *        FSISHIFT          : subunit
+ *        FSII2C            : subunit
+ *        FSB               : subunit
+ *    EX                    : Ex unit (1/2 quad, 2 cores)
+ *        L2                : L2 subunit
+ *        L3                : L3 subunit
+ *    PEC                   : PCI Pec unit
+ *        STACK0            : subunit
+ *        STACK1            : subunit
+ *        STACK2            : subunit
+ *    C                     : core
+ *    EQ                    : quad
+ *    OBUS                  : obus
+ *    CAPP                  : capp
+ *    MCBIST                : mcbist
+ *    MCA                   : mca
+ *    NVBUS                 : (not implemented yet)
+ *    PHB                   : (not implemented yet)
+ *    MI                    : (not implemented yet)
+ *    DMI                   : (not implemented yet)
+ *    MCS                   : (not implemented yet)
+ *    OCC                   : (not implemented yet)
+ *    PPE                   : (not implemented yet)
+ *    SBE                   : (not implemented yet)
+ *    XBUS                  : (not implemented yet)
+ *
+ * Pervasive instance names follow chiplet id.
+ *
+ * Instance/  | Chiplet
+ * Chiplet    | name
+ * -----------+-----------
+ * 0x00       | PIB
+ * 0x01       | TP
+ * 0x02       | N0
+ * 0x03       | N1
+ * 0x04       | N2
+ * 0x05       | N3
+ * 0x06       | XB
+ * 0x07       | MC01
+ * 0x08       | MC23
+ * 0x09       | OB0
+ * 0x0A       | OB1
+ * 0x0B       | OB2
+ * 0x0C       | OB3
+ * 0x0D       | PCI0
+ * 0x0E       | PCI1
+ * 0x0F       | PCI2
+ * 0x10       | EP00
+ * 0x11       | EP01
+ * 0x12       | EP02
+ * 0x13       | EP03
+ * 0x14       | EP04
+ * 0x15       | EP05
+ * 0x20       | EC00
+ * 0x21       | EC01
+ * 0x22       | EC02
+ * 0x23       | EC03
+ * 0x24       | EC04
+ * 0x25       | EC05
+ * 0x26       | EC06
+ * 0x27       | EC07
+ * 0x28       | EC08
+ * 0x29       | EC09
+ * 0x2A       | EC10
+ * 0x2B       | EC11
+ * 0x2C       | EC12
+ * 0x2D       | EC13
+ * 0x2E       | EC14
+ * 0x2F       | EC15
+ * 0x30       | EC16
+ * 0x31       | EC17
+ * 0x32       | EC18
+ * 0x33       | EC19
+ * 0x34       | EC20
+ * 0x35       | EC21
+ * 0x36       | EC22
+ * 0x37       | EC23
+ *
+ *
+ *---------------------------------------------------------------
+ *
+ * NOTES:
+ *
+ * there is a SPR ring that goes around the chip with an
+ * address(0:9)/tid(0:1) (thread id)/mfspr_data(0:63) and return mfspr_data_v/mfspr_data(0:63)
+ *
+ *    Add PU_<SUBUNITS>  (only if there are conflicts on these registers)
+ *       0x0001XXXX OTPROM
+ *       0x0002XXXX FSIM0
+ *       0x0003XXXX FSIM1
+ *       0x0004XXXX TOD
+ *       0x0005XXXX FSI_MBOX
+ *       0x0006XXXX OCI_BRIDGE
+ *       0x0007XXXX SPI_ADC
+ *       0x0008XXXX PIBMEM
+ *       0x0009XXXX ADU
+ *       0x000AXXXX I2CM
+ *       0x000BXXXX SBE_FIFO
+ *       0x000DXXXX PSU
+ *       0x000EXXXX SBE
+ *
+ * 0x0000100A for FSI2PIB  => PERV_FSI2PIB
+ * 0x00000Cxx for FSISHIFT =>  PERV_FSISHIFT
+ * 0x000018xx for FSI I2C =>  PERV_FSII2C
+ * 0x000024xx for FSI SBEFIFO => PERV_FSB
+ *
+ * 0x00000400 PEEK_TABLE
+ * 0x00000800 FSI_SLAVE
+ * 0x00000C00 FSI_SHIFT
+ * 0x00001000 FSI2PIB
+ * 0x00001400 FSI_SCRATCHPAD
+ * 0x00001800 FSI_I2CM
+ * 0x00002400 FSI_SBE_FIFO
+ *
+ * address fields
+ * 0xCCRPxxxx
+ *
+ * CC=chiplet
+ * R=always 0?
+ * P=port
+ *   0=gpregs
+ *   1=normal unit scom ring (exclude)
+ *   3=clock controller
+ *   4=firs
+ *   5=cpm
+ *
+ * =============================================================================
+ * Compiling
+ *
+ * Precompile the header to save time on subsquent compiles:
+ * g++ -I. -c scom_addresses.H
+ *
+ * Use these options to help reduce the binary size
+ * g++ -I. -Os -fdata-sections -ffunction-sections <file>.C -o <output> -Wl,--gc-sections
+ *
+ *
+ *---------------------------------------------------------------
+ */
+
+#include <p9_const_common.H>
+
+
+#ifndef __P9_QUAD_SCOM_ADDRESSES_H
+#define __P9_QUAD_SCOM_ADDRESSES_H
+
+
+#include <p9_scom_template_consts.H>
+#include <p9_quad_scom_addresses_fixes.H>
+
+
+REG64( C_ADDR_TRAP_REG                                         , RULL(0x20010003), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_ADDR_TRAP_REG                                       , RULL(0x20010003), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_ADDR_TRAP_REG                                       , RULL(0x21010003), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_ADDR_TRAP_REG                                       , RULL(0x22010003), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_ADDR_TRAP_REG                                       , RULL(0x23010003), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_ADDR_TRAP_REG                                       , RULL(0x24010003), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_ADDR_TRAP_REG                                       , RULL(0x25010003), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_ADDR_TRAP_REG                                       , RULL(0x26010003), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_ADDR_TRAP_REG                                       , RULL(0x27010003), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_ADDR_TRAP_REG                                       , RULL(0x28010003), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_ADDR_TRAP_REG                                       , RULL(0x29010003), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_ADDR_TRAP_REG                                      , RULL(0x2A010003), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_ADDR_TRAP_REG                                      , RULL(0x2B010003), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_ADDR_TRAP_REG                                      , RULL(0x2C010003), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_ADDR_TRAP_REG                                      , RULL(0x2D010003), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_ADDR_TRAP_REG                                      , RULL(0x2E010003), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_ADDR_TRAP_REG                                      , RULL(0x2F010003), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_ADDR_TRAP_REG                                      , RULL(0x30010003), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_ADDR_TRAP_REG                                      , RULL(0x31010003), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_ADDR_TRAP_REG                                      , RULL(0x32010003), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_ADDR_TRAP_REG                                      , RULL(0x33010003), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_ADDR_TRAP_REG                                      , RULL(0x34010003), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_ADDR_TRAP_REG                                      , RULL(0x35010003), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_ADDR_TRAP_REG                                      , RULL(0x36010003), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_ADDR_TRAP_REG                                      , RULL(0x37010003), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_ADDR_TRAP_REG                                        , RULL(0x10010003), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_ADDR_TRAP_REG                                      , RULL(0x10010003), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_ADDR_TRAP_REG                                      , RULL(0x11010003), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_ADDR_TRAP_REG                                      , RULL(0x12010003), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_ADDR_TRAP_REG                                      , RULL(0x13010003), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_ADDR_TRAP_REG                                      , RULL(0x14010003), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_ADDR_TRAP_REG                                      , RULL(0x15010003), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_ADDR_TRAP_REG                                        , RULL(0x20010003), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21010003,
+REG64( EX_0_ADDR_TRAP_REG                                      , RULL(0x20010003), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21010003,
+REG64( EX_1_ADDR_TRAP_REG                                      , RULL(0x22010003), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23010003,
+REG64( EX_2_ADDR_TRAP_REG                                      , RULL(0x24010003), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25010003,
+REG64( EX_3_ADDR_TRAP_REG                                      , RULL(0x26010003), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27010003,
+REG64( EX_4_ADDR_TRAP_REG                                      , RULL(0x28010003), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29010003,
+REG64( EX_5_ADDR_TRAP_REG                                      , RULL(0x2A010003), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B010003,
+REG64( EX_6_ADDR_TRAP_REG                                      , RULL(0x2C010003), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D010003,
+REG64( EX_7_ADDR_TRAP_REG                                      , RULL(0x2E010003), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F010003,
+REG64( EX_8_ADDR_TRAP_REG                                      , RULL(0x30010003), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31010003,
+REG64( EX_9_ADDR_TRAP_REG                                      , RULL(0x32010003), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33010003,
+REG64( EX_10_ADDR_TRAP_REG                                     , RULL(0x34010003), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35010003,
+REG64( EX_11_ADDR_TRAP_REG                                     , RULL(0x36010003), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37010003,
+
+REG64( C_ASSIST_INTERRUPT_REG                                  , RULL(0x200F0011), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_ASSIST_INTERRUPT_REG                                , RULL(0x200F0011), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_ASSIST_INTERRUPT_REG                                , RULL(0x210F0011), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_ASSIST_INTERRUPT_REG                                , RULL(0x220F0011), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_ASSIST_INTERRUPT_REG                                , RULL(0x230F0011), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_ASSIST_INTERRUPT_REG                                , RULL(0x240F0011), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_ASSIST_INTERRUPT_REG                                , RULL(0x250F0011), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_ASSIST_INTERRUPT_REG                                , RULL(0x260F0011), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_ASSIST_INTERRUPT_REG                                , RULL(0x270F0011), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_ASSIST_INTERRUPT_REG                                , RULL(0x280F0011), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_ASSIST_INTERRUPT_REG                                , RULL(0x290F0011), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_ASSIST_INTERRUPT_REG                               , RULL(0x2A0F0011), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_ASSIST_INTERRUPT_REG                               , RULL(0x2B0F0011), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_ASSIST_INTERRUPT_REG                               , RULL(0x2C0F0011), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_ASSIST_INTERRUPT_REG                               , RULL(0x2D0F0011), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_ASSIST_INTERRUPT_REG                               , RULL(0x2E0F0011), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_ASSIST_INTERRUPT_REG                               , RULL(0x2F0F0011), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_ASSIST_INTERRUPT_REG                               , RULL(0x300F0011), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_ASSIST_INTERRUPT_REG                               , RULL(0x310F0011), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_ASSIST_INTERRUPT_REG                               , RULL(0x320F0011), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_ASSIST_INTERRUPT_REG                               , RULL(0x330F0011), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_ASSIST_INTERRUPT_REG                               , RULL(0x340F0011), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_ASSIST_INTERRUPT_REG                               , RULL(0x350F0011), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_ASSIST_INTERRUPT_REG                               , RULL(0x360F0011), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_ASSIST_INTERRUPT_REG                               , RULL(0x370F0011), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_ASSIST_INTERRUPT_REG                                 , RULL(0x100F0011), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_ASSIST_INTERRUPT_REG                               , RULL(0x100F0011), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_ASSIST_INTERRUPT_REG                               , RULL(0x110F0011), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_ASSIST_INTERRUPT_REG                               , RULL(0x120F0011), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_ASSIST_INTERRUPT_REG                               , RULL(0x130F0011), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_ASSIST_INTERRUPT_REG                               , RULL(0x140F0011), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_ASSIST_INTERRUPT_REG                               , RULL(0x150F0011), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_ASSIST_INTERRUPT_REG                                 , RULL(0x200F0011), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0011,
+REG64( EX_0_ASSIST_INTERRUPT_REG                               , RULL(0x200F0011), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0011,
+REG64( EX_1_ASSIST_INTERRUPT_REG                               , RULL(0x230F0011), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0011,
+REG64( EX_2_ASSIST_INTERRUPT_REG                               , RULL(0x240F0011), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0011,
+REG64( EX_3_ASSIST_INTERRUPT_REG                               , RULL(0x260F0011), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0011,
+REG64( EX_4_ASSIST_INTERRUPT_REG                               , RULL(0x280F0011), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0011,
+REG64( EX_5_ASSIST_INTERRUPT_REG                               , RULL(0x2A0F0011), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0011,
+REG64( EX_6_ASSIST_INTERRUPT_REG                               , RULL(0x2C0F0011), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0011,
+REG64( EX_7_ASSIST_INTERRUPT_REG                               , RULL(0x2E0F0011), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0011,
+REG64( EX_8_ASSIST_INTERRUPT_REG                               , RULL(0x300F0011), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0011,
+REG64( EX_9_ASSIST_INTERRUPT_REG                               , RULL(0x320F0011), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0011,
+REG64( EX_10_ASSIST_INTERRUPT_REG                              , RULL(0x340F0011), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0011,
+REG64( EX_11_ASSIST_INTERRUPT_REG                              , RULL(0x360F0011), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0011,
+
+REG64( C_ATOMIC_LOCK_MASK_LATCH_REG                            , RULL(0x20010007), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_ATOMIC_LOCK_MASK_LATCH_REG                          , RULL(0x20010007), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_ATOMIC_LOCK_MASK_LATCH_REG                          , RULL(0x21010007), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_ATOMIC_LOCK_MASK_LATCH_REG                          , RULL(0x22010007), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_ATOMIC_LOCK_MASK_LATCH_REG                          , RULL(0x23010007), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_ATOMIC_LOCK_MASK_LATCH_REG                          , RULL(0x24010007), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_ATOMIC_LOCK_MASK_LATCH_REG                          , RULL(0x25010007), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_ATOMIC_LOCK_MASK_LATCH_REG                          , RULL(0x26010007), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_ATOMIC_LOCK_MASK_LATCH_REG                          , RULL(0x27010007), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_ATOMIC_LOCK_MASK_LATCH_REG                          , RULL(0x28010007), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_ATOMIC_LOCK_MASK_LATCH_REG                          , RULL(0x29010007), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x2A010007), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x2B010007), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x2C010007), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x2D010007), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x2E010007), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x2F010007), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x30010007), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x31010007), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x32010007), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x33010007), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x34010007), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x35010007), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x36010007), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x37010007), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_ATOMIC_LOCK_MASK_LATCH_REG                           , RULL(0x10010007), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x10010007), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x11010007), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x12010007), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x13010007), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x14010007), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x15010007), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_ATOMIC_LOCK_MASK_LATCH_REG                           , RULL(0x20010007), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21010007,
+REG64( EX_0_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x20010007), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21010007,
+REG64( EX_1_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x22010007), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23010007,
+REG64( EX_2_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x24010007), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25010007,
+REG64( EX_3_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x26010007), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27010007,
+REG64( EX_4_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x28010007), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29010007,
+REG64( EX_5_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x2A010007), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B010007,
+REG64( EX_6_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x2C010007), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D010007,
+REG64( EX_7_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x2E010007), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F010007,
+REG64( EX_8_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x30010007), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31010007,
+REG64( EX_9_ATOMIC_LOCK_MASK_LATCH_REG                         , RULL(0x32010007), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33010007,
+REG64( EX_10_ATOMIC_LOCK_MASK_LATCH_REG                        , RULL(0x34010007), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35010007,
+REG64( EX_11_ATOMIC_LOCK_MASK_LATCH_REG                        , RULL(0x36010007), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37010007,
+
+REG64( C_ATOMIC_LOCK_REG                                       , RULL(0x200F03FF), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_ATOMIC_LOCK_REG                                     , RULL(0x200F03FF), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_ATOMIC_LOCK_REG                                     , RULL(0x210F03FF), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_ATOMIC_LOCK_REG                                     , RULL(0x220F03FF), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_ATOMIC_LOCK_REG                                     , RULL(0x230F03FF), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_ATOMIC_LOCK_REG                                     , RULL(0x240F03FF), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_ATOMIC_LOCK_REG                                     , RULL(0x250F03FF), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_ATOMIC_LOCK_REG                                     , RULL(0x260F03FF), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_ATOMIC_LOCK_REG                                     , RULL(0x270F03FF), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_ATOMIC_LOCK_REG                                     , RULL(0x280F03FF), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_ATOMIC_LOCK_REG                                     , RULL(0x290F03FF), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_ATOMIC_LOCK_REG                                    , RULL(0x2A0F03FF), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_ATOMIC_LOCK_REG                                    , RULL(0x2B0F03FF), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_ATOMIC_LOCK_REG                                    , RULL(0x2C0F03FF), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_ATOMIC_LOCK_REG                                    , RULL(0x2D0F03FF), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_ATOMIC_LOCK_REG                                    , RULL(0x2E0F03FF), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_ATOMIC_LOCK_REG                                    , RULL(0x2F0F03FF), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_ATOMIC_LOCK_REG                                    , RULL(0x300F03FF), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_ATOMIC_LOCK_REG                                    , RULL(0x310F03FF), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_ATOMIC_LOCK_REG                                    , RULL(0x320F03FF), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_ATOMIC_LOCK_REG                                    , RULL(0x330F03FF), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_ATOMIC_LOCK_REG                                    , RULL(0x340F03FF), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_ATOMIC_LOCK_REG                                    , RULL(0x350F03FF), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_ATOMIC_LOCK_REG                                    , RULL(0x360F03FF), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_ATOMIC_LOCK_REG                                    , RULL(0x370F03FF), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_ATOMIC_LOCK_REG                                      , RULL(0x100F03FF), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_ATOMIC_LOCK_REG                                    , RULL(0x100F03FF), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_ATOMIC_LOCK_REG                                    , RULL(0x110F03FF), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_ATOMIC_LOCK_REG                                    , RULL(0x120F03FF), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_ATOMIC_LOCK_REG                                    , RULL(0x130F03FF), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_ATOMIC_LOCK_REG                                    , RULL(0x140F03FF), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_ATOMIC_LOCK_REG                                    , RULL(0x150F03FF), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_ATOMIC_LOCK_REG                                      , RULL(0x200F03FF), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F03FF,
+REG64( EX_0_ATOMIC_LOCK_REG                                    , RULL(0x200F03FF), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F03FF,
+REG64( EX_1_ATOMIC_LOCK_REG                                    , RULL(0x230F03FF), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F03FF,
+REG64( EX_2_ATOMIC_LOCK_REG                                    , RULL(0x240F03FF), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F03FF,
+REG64( EX_3_ATOMIC_LOCK_REG                                    , RULL(0x260F03FF), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F03FF,
+REG64( EX_4_ATOMIC_LOCK_REG                                    , RULL(0x280F03FF), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F03FF,
+REG64( EX_5_ATOMIC_LOCK_REG                                    , RULL(0x2A0F03FF), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F03FF,
+REG64( EX_6_ATOMIC_LOCK_REG                                    , RULL(0x2C0F03FF), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F03FF,
+REG64( EX_7_ATOMIC_LOCK_REG                                    , RULL(0x2E0F03FF), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F03FF,
+REG64( EX_8_ATOMIC_LOCK_REG                                    , RULL(0x300F03FF), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F03FF,
+REG64( EX_9_ATOMIC_LOCK_REG                                    , RULL(0x320F03FF), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F03FF,
+REG64( EX_10_ATOMIC_LOCK_REG                                   , RULL(0x340F03FF), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F03FF,
+REG64( EX_11_ATOMIC_LOCK_REG                                   , RULL(0x360F03FF), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F03FF,
+
+REG64( C_ATTN_INTERRUPT_REG                                    , RULL(0x200F001A), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_ATTN_INTERRUPT_REG                                  , RULL(0x200F001A), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_ATTN_INTERRUPT_REG                                  , RULL(0x210F001A), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_ATTN_INTERRUPT_REG                                  , RULL(0x220F001A), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_ATTN_INTERRUPT_REG                                  , RULL(0x230F001A), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_ATTN_INTERRUPT_REG                                  , RULL(0x240F001A), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_ATTN_INTERRUPT_REG                                  , RULL(0x250F001A), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_ATTN_INTERRUPT_REG                                  , RULL(0x260F001A), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_ATTN_INTERRUPT_REG                                  , RULL(0x270F001A), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_ATTN_INTERRUPT_REG                                  , RULL(0x280F001A), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_ATTN_INTERRUPT_REG                                  , RULL(0x290F001A), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_ATTN_INTERRUPT_REG                                 , RULL(0x2A0F001A), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_ATTN_INTERRUPT_REG                                 , RULL(0x2B0F001A), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_ATTN_INTERRUPT_REG                                 , RULL(0x2C0F001A), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_ATTN_INTERRUPT_REG                                 , RULL(0x2D0F001A), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_ATTN_INTERRUPT_REG                                 , RULL(0x2E0F001A), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_ATTN_INTERRUPT_REG                                 , RULL(0x2F0F001A), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_ATTN_INTERRUPT_REG                                 , RULL(0x300F001A), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_ATTN_INTERRUPT_REG                                 , RULL(0x310F001A), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_ATTN_INTERRUPT_REG                                 , RULL(0x320F001A), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_ATTN_INTERRUPT_REG                                 , RULL(0x330F001A), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_ATTN_INTERRUPT_REG                                 , RULL(0x340F001A), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_ATTN_INTERRUPT_REG                                 , RULL(0x350F001A), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_ATTN_INTERRUPT_REG                                 , RULL(0x360F001A), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_ATTN_INTERRUPT_REG                                 , RULL(0x370F001A), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_ATTN_INTERRUPT_REG                                   , RULL(0x100F001A), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_ATTN_INTERRUPT_REG                                 , RULL(0x100F001A), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_ATTN_INTERRUPT_REG                                 , RULL(0x110F001A), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_ATTN_INTERRUPT_REG                                 , RULL(0x120F001A), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_ATTN_INTERRUPT_REG                                 , RULL(0x130F001A), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_ATTN_INTERRUPT_REG                                 , RULL(0x140F001A), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_ATTN_INTERRUPT_REG                                 , RULL(0x150F001A), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_ATTN_INTERRUPT_REG                                   , RULL(0x200F001A), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F001A,
+REG64( EX_0_ATTN_INTERRUPT_REG                                 , RULL(0x200F001A), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F001A,
+REG64( EX_1_ATTN_INTERRUPT_REG                                 , RULL(0x230F001A), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F001A,
+REG64( EX_2_ATTN_INTERRUPT_REG                                 , RULL(0x240F001A), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F001A,
+REG64( EX_3_ATTN_INTERRUPT_REG                                 , RULL(0x260F001A), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F001A,
+REG64( EX_4_ATTN_INTERRUPT_REG                                 , RULL(0x280F001A), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F001A,
+REG64( EX_5_ATTN_INTERRUPT_REG                                 , RULL(0x2A0F001A), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F001A,
+REG64( EX_6_ATTN_INTERRUPT_REG                                 , RULL(0x2C0F001A), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F001A,
+REG64( EX_7_ATTN_INTERRUPT_REG                                 , RULL(0x2E0F001A), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F001A,
+REG64( EX_8_ATTN_INTERRUPT_REG                                 , RULL(0x300F001A), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F001A,
+REG64( EX_9_ATTN_INTERRUPT_REG                                 , RULL(0x320F001A), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F001A,
+REG64( EX_10_ATTN_INTERRUPT_REG                                , RULL(0x340F001A), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F001A,
+REG64( EX_11_ATTN_INTERRUPT_REG                                , RULL(0x360F001A), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F001A,
+
+REG64( C_BIST                                                  , RULL(0x2003000B), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_BIST                                                , RULL(0x2003000B), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_BIST                                                , RULL(0x2103000B), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_BIST                                                , RULL(0x2203000B), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_BIST                                                , RULL(0x2303000B), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_BIST                                                , RULL(0x2403000B), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_BIST                                                , RULL(0x2503000B), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_BIST                                                , RULL(0x2603000B), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_BIST                                                , RULL(0x2703000B), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_BIST                                                , RULL(0x2803000B), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_BIST                                                , RULL(0x2903000B), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_BIST                                               , RULL(0x2A03000B), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_BIST                                               , RULL(0x2B03000B), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_BIST                                               , RULL(0x2C03000B), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_BIST                                               , RULL(0x2D03000B), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_BIST                                               , RULL(0x2E03000B), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_BIST                                               , RULL(0x2F03000B), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_BIST                                               , RULL(0x3003000B), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_BIST                                               , RULL(0x3103000B), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_BIST                                               , RULL(0x3203000B), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_BIST                                               , RULL(0x3303000B), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_BIST                                               , RULL(0x3403000B), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_BIST                                               , RULL(0x3503000B), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_BIST                                               , RULL(0x3603000B), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_BIST                                               , RULL(0x3703000B), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_BIST                                                 , RULL(0x1003000B), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_BIST                                               , RULL(0x1003000B), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_BIST                                               , RULL(0x1103000B), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_BIST                                               , RULL(0x1203000B), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_BIST                                               , RULL(0x1303000B), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_BIST                                               , RULL(0x1403000B), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_BIST                                               , RULL(0x1503000B), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_BIST                                                 , RULL(0x2003000B), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 2103000B,
+REG64( EX_0_BIST                                               , RULL(0x2003000B), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 2103000B,
+REG64( EX_1_BIST                                               , RULL(0x2203000B), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 2303000B,
+REG64( EX_2_BIST                                               , RULL(0x2403000B), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 2503000B,
+REG64( EX_3_BIST                                               , RULL(0x2603000B), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 2703000B,
+REG64( EX_4_BIST                                               , RULL(0x2803000B), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 2903000B,
+REG64( EX_5_BIST                                               , RULL(0x2A03000B), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B03000B,
+REG64( EX_6_BIST                                               , RULL(0x2C03000B), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D03000B,
+REG64( EX_7_BIST                                               , RULL(0x2E03000B), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F03000B,
+REG64( EX_8_BIST                                               , RULL(0x3003000B), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 3103000B,
+REG64( EX_9_BIST                                               , RULL(0x3203000B), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 3303000B,
+REG64( EX_10_BIST                                              , RULL(0x3403000B), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 3503000B,
+REG64( EX_11_BIST                                              , RULL(0x3603000B), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 3703000B,
+
+REG64( C_CC_ATOMIC_LOCK_REG                                    , RULL(0x200303FF), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_CC_ATOMIC_LOCK_REG                                  , RULL(0x200303FF), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_CC_ATOMIC_LOCK_REG                                  , RULL(0x210303FF), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_CC_ATOMIC_LOCK_REG                                  , RULL(0x220303FF), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_CC_ATOMIC_LOCK_REG                                  , RULL(0x230303FF), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_CC_ATOMIC_LOCK_REG                                  , RULL(0x240303FF), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_CC_ATOMIC_LOCK_REG                                  , RULL(0x250303FF), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_CC_ATOMIC_LOCK_REG                                  , RULL(0x260303FF), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_CC_ATOMIC_LOCK_REG                                  , RULL(0x270303FF), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_CC_ATOMIC_LOCK_REG                                  , RULL(0x280303FF), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_CC_ATOMIC_LOCK_REG                                  , RULL(0x290303FF), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_CC_ATOMIC_LOCK_REG                                 , RULL(0x2A0303FF), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_CC_ATOMIC_LOCK_REG                                 , RULL(0x2B0303FF), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_CC_ATOMIC_LOCK_REG                                 , RULL(0x2C0303FF), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_CC_ATOMIC_LOCK_REG                                 , RULL(0x2D0303FF), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_CC_ATOMIC_LOCK_REG                                 , RULL(0x2E0303FF), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_CC_ATOMIC_LOCK_REG                                 , RULL(0x2F0303FF), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_CC_ATOMIC_LOCK_REG                                 , RULL(0x300303FF), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_CC_ATOMIC_LOCK_REG                                 , RULL(0x310303FF), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_CC_ATOMIC_LOCK_REG                                 , RULL(0x320303FF), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_CC_ATOMIC_LOCK_REG                                 , RULL(0x330303FF), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_CC_ATOMIC_LOCK_REG                                 , RULL(0x340303FF), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_CC_ATOMIC_LOCK_REG                                 , RULL(0x350303FF), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_CC_ATOMIC_LOCK_REG                                 , RULL(0x360303FF), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_CC_ATOMIC_LOCK_REG                                 , RULL(0x370303FF), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_CC_ATOMIC_LOCK_REG                                   , RULL(0x100303FF), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_CC_ATOMIC_LOCK_REG                                 , RULL(0x100303FF), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_CC_ATOMIC_LOCK_REG                                 , RULL(0x110303FF), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_CC_ATOMIC_LOCK_REG                                 , RULL(0x120303FF), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_CC_ATOMIC_LOCK_REG                                 , RULL(0x130303FF), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_CC_ATOMIC_LOCK_REG                                 , RULL(0x140303FF), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_CC_ATOMIC_LOCK_REG                                 , RULL(0x150303FF), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_CC_ATOMIC_LOCK_REG                                   , RULL(0x200303FF), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210303FF,
+REG64( EX_0_CC_ATOMIC_LOCK_REG                                 , RULL(0x200303FF), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210303FF,
+REG64( EX_1_CC_ATOMIC_LOCK_REG                                 , RULL(0x220303FF), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230303FF,
+REG64( EX_2_CC_ATOMIC_LOCK_REG                                 , RULL(0x240303FF), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250303FF,
+REG64( EX_3_CC_ATOMIC_LOCK_REG                                 , RULL(0x260303FF), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270303FF,
+REG64( EX_4_CC_ATOMIC_LOCK_REG                                 , RULL(0x280303FF), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290303FF,
+REG64( EX_5_CC_ATOMIC_LOCK_REG                                 , RULL(0x2A0303FF), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0303FF,
+REG64( EX_6_CC_ATOMIC_LOCK_REG                                 , RULL(0x2C0303FF), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0303FF,
+REG64( EX_7_CC_ATOMIC_LOCK_REG                                 , RULL(0x2E0303FF), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0303FF,
+REG64( EX_8_CC_ATOMIC_LOCK_REG                                 , RULL(0x300303FF), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310303FF,
+REG64( EX_9_CC_ATOMIC_LOCK_REG                                 , RULL(0x320303FF), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330303FF,
+REG64( EX_10_CC_ATOMIC_LOCK_REG                                , RULL(0x340303FF), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350303FF,
+REG64( EX_11_CC_ATOMIC_LOCK_REG                                , RULL(0x360303FF), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370303FF,
+
+REG64( C_CC_PROTECT_MODE_REG                                   , RULL(0x200303FE), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_CC_PROTECT_MODE_REG                                 , RULL(0x200303FE), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_CC_PROTECT_MODE_REG                                 , RULL(0x210303FE), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_CC_PROTECT_MODE_REG                                 , RULL(0x220303FE), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_CC_PROTECT_MODE_REG                                 , RULL(0x230303FE), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_CC_PROTECT_MODE_REG                                 , RULL(0x240303FE), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_CC_PROTECT_MODE_REG                                 , RULL(0x250303FE), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_CC_PROTECT_MODE_REG                                 , RULL(0x260303FE), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_CC_PROTECT_MODE_REG                                 , RULL(0x270303FE), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_CC_PROTECT_MODE_REG                                 , RULL(0x280303FE), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_CC_PROTECT_MODE_REG                                 , RULL(0x290303FE), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_CC_PROTECT_MODE_REG                                , RULL(0x2A0303FE), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_CC_PROTECT_MODE_REG                                , RULL(0x2B0303FE), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_CC_PROTECT_MODE_REG                                , RULL(0x2C0303FE), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_CC_PROTECT_MODE_REG                                , RULL(0x2D0303FE), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_CC_PROTECT_MODE_REG                                , RULL(0x2E0303FE), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_CC_PROTECT_MODE_REG                                , RULL(0x2F0303FE), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_CC_PROTECT_MODE_REG                                , RULL(0x300303FE), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_CC_PROTECT_MODE_REG                                , RULL(0x310303FE), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_CC_PROTECT_MODE_REG                                , RULL(0x320303FE), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_CC_PROTECT_MODE_REG                                , RULL(0x330303FE), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_CC_PROTECT_MODE_REG                                , RULL(0x340303FE), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_CC_PROTECT_MODE_REG                                , RULL(0x350303FE), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_CC_PROTECT_MODE_REG                                , RULL(0x360303FE), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_CC_PROTECT_MODE_REG                                , RULL(0x370303FE), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_CC_PROTECT_MODE_REG                                  , RULL(0x100303FE), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_CC_PROTECT_MODE_REG                                , RULL(0x100303FE), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_CC_PROTECT_MODE_REG                                , RULL(0x110303FE), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_CC_PROTECT_MODE_REG                                , RULL(0x120303FE), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_CC_PROTECT_MODE_REG                                , RULL(0x130303FE), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_CC_PROTECT_MODE_REG                                , RULL(0x140303FE), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_CC_PROTECT_MODE_REG                                , RULL(0x150303FE), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_CC_PROTECT_MODE_REG                                  , RULL(0x200303FE), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210303FE,
+REG64( EX_0_CC_PROTECT_MODE_REG                                , RULL(0x200303FE), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210303FE,
+REG64( EX_1_CC_PROTECT_MODE_REG                                , RULL(0x220303FE), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230303FE,
+REG64( EX_2_CC_PROTECT_MODE_REG                                , RULL(0x240303FE), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250303FE,
+REG64( EX_3_CC_PROTECT_MODE_REG                                , RULL(0x260303FE), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270303FE,
+REG64( EX_4_CC_PROTECT_MODE_REG                                , RULL(0x280303FE), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290303FE,
+REG64( EX_5_CC_PROTECT_MODE_REG                                , RULL(0x2A0303FE), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0303FE,
+REG64( EX_6_CC_PROTECT_MODE_REG                                , RULL(0x2C0303FE), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0303FE,
+REG64( EX_7_CC_PROTECT_MODE_REG                                , RULL(0x2E0303FE), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0303FE,
+REG64( EX_8_CC_PROTECT_MODE_REG                                , RULL(0x300303FE), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310303FE,
+REG64( EX_9_CC_PROTECT_MODE_REG                                , RULL(0x320303FE), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330303FE,
+REG64( EX_10_CC_PROTECT_MODE_REG                               , RULL(0x340303FE), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350303FE,
+REG64( EX_11_CC_PROTECT_MODE_REG                               , RULL(0x360303FE), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370303FE,
+
+REG64( C_CLK_REGION                                            , RULL(0x20030006), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_CLK_REGION                                          , RULL(0x20030006), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_CLK_REGION                                          , RULL(0x21030006), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_CLK_REGION                                          , RULL(0x22030006), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_CLK_REGION                                          , RULL(0x23030006), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_CLK_REGION                                          , RULL(0x24030006), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_CLK_REGION                                          , RULL(0x25030006), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_CLK_REGION                                          , RULL(0x26030006), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_CLK_REGION                                          , RULL(0x27030006), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_CLK_REGION                                          , RULL(0x28030006), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_CLK_REGION                                          , RULL(0x29030006), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_CLK_REGION                                         , RULL(0x2A030006), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_CLK_REGION                                         , RULL(0x2B030006), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_CLK_REGION                                         , RULL(0x2C030006), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_CLK_REGION                                         , RULL(0x2D030006), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_CLK_REGION                                         , RULL(0x2E030006), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_CLK_REGION                                         , RULL(0x2F030006), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_CLK_REGION                                         , RULL(0x30030006), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_CLK_REGION                                         , RULL(0x31030006), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_CLK_REGION                                         , RULL(0x32030006), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_CLK_REGION                                         , RULL(0x33030006), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_CLK_REGION                                         , RULL(0x34030006), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_CLK_REGION                                         , RULL(0x35030006), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_CLK_REGION                                         , RULL(0x36030006), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_CLK_REGION                                         , RULL(0x37030006), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_CLK_REGION                                           , RULL(0x10030006), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_CLK_REGION                                         , RULL(0x10030006), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_CLK_REGION                                         , RULL(0x11030006), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_CLK_REGION                                         , RULL(0x12030006), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_CLK_REGION                                         , RULL(0x13030006), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_CLK_REGION                                         , RULL(0x14030006), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_CLK_REGION                                         , RULL(0x15030006), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_CLK_REGION                                           , RULL(0x20030006), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21030006,
+REG64( EX_0_CLK_REGION                                         , RULL(0x20030006), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21030006,
+REG64( EX_1_CLK_REGION                                         , RULL(0x22030006), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23030006,
+REG64( EX_2_CLK_REGION                                         , RULL(0x24030006), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25030006,
+REG64( EX_3_CLK_REGION                                         , RULL(0x26030006), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27030006,
+REG64( EX_4_CLK_REGION                                         , RULL(0x28030006), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29030006,
+REG64( EX_5_CLK_REGION                                         , RULL(0x2A030006), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B030006,
+REG64( EX_6_CLK_REGION                                         , RULL(0x2C030006), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D030006,
+REG64( EX_7_CLK_REGION                                         , RULL(0x2E030006), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F030006,
+REG64( EX_8_CLK_REGION                                         , RULL(0x30030006), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31030006,
+REG64( EX_9_CLK_REGION                                         , RULL(0x32030006), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33030006,
+REG64( EX_10_CLK_REGION                                        , RULL(0x34030006), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35030006,
+REG64( EX_11_CLK_REGION                                        , RULL(0x36030006), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37030006,
+
+REG64( C_CLOCK_STAT_ARY                                        , RULL(0x2003000A), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_CLOCK_STAT_ARY                                      , RULL(0x2003000A), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_CLOCK_STAT_ARY                                      , RULL(0x2103000A), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_CLOCK_STAT_ARY                                      , RULL(0x2203000A), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_CLOCK_STAT_ARY                                      , RULL(0x2303000A), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_CLOCK_STAT_ARY                                      , RULL(0x2403000A), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_CLOCK_STAT_ARY                                      , RULL(0x2503000A), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_CLOCK_STAT_ARY                                      , RULL(0x2603000A), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_CLOCK_STAT_ARY                                      , RULL(0x2703000A), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_CLOCK_STAT_ARY                                      , RULL(0x2803000A), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_CLOCK_STAT_ARY                                      , RULL(0x2903000A), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_CLOCK_STAT_ARY                                     , RULL(0x2A03000A), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_CLOCK_STAT_ARY                                     , RULL(0x2B03000A), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_CLOCK_STAT_ARY                                     , RULL(0x2C03000A), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_CLOCK_STAT_ARY                                     , RULL(0x2D03000A), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_CLOCK_STAT_ARY                                     , RULL(0x2E03000A), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_CLOCK_STAT_ARY                                     , RULL(0x2F03000A), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_CLOCK_STAT_ARY                                     , RULL(0x3003000A), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_CLOCK_STAT_ARY                                     , RULL(0x3103000A), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_CLOCK_STAT_ARY                                     , RULL(0x3203000A), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_CLOCK_STAT_ARY                                     , RULL(0x3303000A), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_CLOCK_STAT_ARY                                     , RULL(0x3403000A), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_CLOCK_STAT_ARY                                     , RULL(0x3503000A), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_CLOCK_STAT_ARY                                     , RULL(0x3603000A), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_CLOCK_STAT_ARY                                     , RULL(0x3703000A), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_CLOCK_STAT_ARY                                       , RULL(0x1003000A), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_CLOCK_STAT_ARY                                     , RULL(0x1003000A), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_CLOCK_STAT_ARY                                     , RULL(0x1103000A), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_CLOCK_STAT_ARY                                     , RULL(0x1203000A), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_CLOCK_STAT_ARY                                     , RULL(0x1303000A), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_CLOCK_STAT_ARY                                     , RULL(0x1403000A), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_CLOCK_STAT_ARY                                     , RULL(0x1503000A), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_CLOCK_STAT_ARY                                       , RULL(0x2003000A), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 2103000A,
+REG64( EX_0_CLOCK_STAT_ARY                                     , RULL(0x2003000A), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 2103000A,
+REG64( EX_1_CLOCK_STAT_ARY                                     , RULL(0x2203000A), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 2303000A,
+REG64( EX_2_CLOCK_STAT_ARY                                     , RULL(0x2403000A), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 2503000A,
+REG64( EX_3_CLOCK_STAT_ARY                                     , RULL(0x2603000A), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 2703000A,
+REG64( EX_4_CLOCK_STAT_ARY                                     , RULL(0x2803000A), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 2903000A,
+REG64( EX_5_CLOCK_STAT_ARY                                     , RULL(0x2A03000A), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B03000A,
+REG64( EX_6_CLOCK_STAT_ARY                                     , RULL(0x2C03000A), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D03000A,
+REG64( EX_7_CLOCK_STAT_ARY                                     , RULL(0x2E03000A), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F03000A,
+REG64( EX_8_CLOCK_STAT_ARY                                     , RULL(0x3003000A), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 3103000A,
+REG64( EX_9_CLOCK_STAT_ARY                                     , RULL(0x3203000A), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 3303000A,
+REG64( EX_10_CLOCK_STAT_ARY                                    , RULL(0x3403000A), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 3503000A,
+REG64( EX_11_CLOCK_STAT_ARY                                    , RULL(0x3603000A), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 3703000A,
+
+REG64( C_CLOCK_STAT_NSL                                        , RULL(0x20030009), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_CLOCK_STAT_NSL                                      , RULL(0x20030009), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_CLOCK_STAT_NSL                                      , RULL(0x21030009), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_CLOCK_STAT_NSL                                      , RULL(0x22030009), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_CLOCK_STAT_NSL                                      , RULL(0x23030009), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_CLOCK_STAT_NSL                                      , RULL(0x24030009), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_CLOCK_STAT_NSL                                      , RULL(0x25030009), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_CLOCK_STAT_NSL                                      , RULL(0x26030009), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_CLOCK_STAT_NSL                                      , RULL(0x27030009), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_CLOCK_STAT_NSL                                      , RULL(0x28030009), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_CLOCK_STAT_NSL                                      , RULL(0x29030009), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_CLOCK_STAT_NSL                                     , RULL(0x2A030009), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_CLOCK_STAT_NSL                                     , RULL(0x2B030009), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_CLOCK_STAT_NSL                                     , RULL(0x2C030009), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_CLOCK_STAT_NSL                                     , RULL(0x2D030009), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_CLOCK_STAT_NSL                                     , RULL(0x2E030009), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_CLOCK_STAT_NSL                                     , RULL(0x2F030009), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_CLOCK_STAT_NSL                                     , RULL(0x30030009), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_CLOCK_STAT_NSL                                     , RULL(0x31030009), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_CLOCK_STAT_NSL                                     , RULL(0x32030009), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_CLOCK_STAT_NSL                                     , RULL(0x33030009), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_CLOCK_STAT_NSL                                     , RULL(0x34030009), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_CLOCK_STAT_NSL                                     , RULL(0x35030009), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_CLOCK_STAT_NSL                                     , RULL(0x36030009), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_CLOCK_STAT_NSL                                     , RULL(0x37030009), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_CLOCK_STAT_NSL                                       , RULL(0x10030009), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_CLOCK_STAT_NSL                                     , RULL(0x10030009), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_CLOCK_STAT_NSL                                     , RULL(0x11030009), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_CLOCK_STAT_NSL                                     , RULL(0x12030009), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_CLOCK_STAT_NSL                                     , RULL(0x13030009), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_CLOCK_STAT_NSL                                     , RULL(0x14030009), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_CLOCK_STAT_NSL                                     , RULL(0x15030009), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_CLOCK_STAT_NSL                                       , RULL(0x20030009), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21030009,
+REG64( EX_0_CLOCK_STAT_NSL                                     , RULL(0x20030009), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21030009,
+REG64( EX_1_CLOCK_STAT_NSL                                     , RULL(0x22030009), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23030009,
+REG64( EX_2_CLOCK_STAT_NSL                                     , RULL(0x24030009), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25030009,
+REG64( EX_3_CLOCK_STAT_NSL                                     , RULL(0x26030009), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27030009,
+REG64( EX_4_CLOCK_STAT_NSL                                     , RULL(0x28030009), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29030009,
+REG64( EX_5_CLOCK_STAT_NSL                                     , RULL(0x2A030009), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B030009,
+REG64( EX_6_CLOCK_STAT_NSL                                     , RULL(0x2C030009), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D030009,
+REG64( EX_7_CLOCK_STAT_NSL                                     , RULL(0x2E030009), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F030009,
+REG64( EX_8_CLOCK_STAT_NSL                                     , RULL(0x30030009), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31030009,
+REG64( EX_9_CLOCK_STAT_NSL                                     , RULL(0x32030009), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33030009,
+REG64( EX_10_CLOCK_STAT_NSL                                    , RULL(0x34030009), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35030009,
+REG64( EX_11_CLOCK_STAT_NSL                                    , RULL(0x36030009), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37030009,
+
+REG64( C_CLOCK_STAT_SL                                         , RULL(0x20030008), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_CLOCK_STAT_SL                                       , RULL(0x20030008), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_CLOCK_STAT_SL                                       , RULL(0x21030008), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_CLOCK_STAT_SL                                       , RULL(0x22030008), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_CLOCK_STAT_SL                                       , RULL(0x23030008), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_CLOCK_STAT_SL                                       , RULL(0x24030008), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_CLOCK_STAT_SL                                       , RULL(0x25030008), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_CLOCK_STAT_SL                                       , RULL(0x26030008), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_CLOCK_STAT_SL                                       , RULL(0x27030008), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_CLOCK_STAT_SL                                       , RULL(0x28030008), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_CLOCK_STAT_SL                                       , RULL(0x29030008), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_CLOCK_STAT_SL                                      , RULL(0x2A030008), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_CLOCK_STAT_SL                                      , RULL(0x2B030008), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_CLOCK_STAT_SL                                      , RULL(0x2C030008), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_CLOCK_STAT_SL                                      , RULL(0x2D030008), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_CLOCK_STAT_SL                                      , RULL(0x2E030008), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_CLOCK_STAT_SL                                      , RULL(0x2F030008), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_CLOCK_STAT_SL                                      , RULL(0x30030008), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_CLOCK_STAT_SL                                      , RULL(0x31030008), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_CLOCK_STAT_SL                                      , RULL(0x32030008), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_CLOCK_STAT_SL                                      , RULL(0x33030008), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_CLOCK_STAT_SL                                      , RULL(0x34030008), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_CLOCK_STAT_SL                                      , RULL(0x35030008), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_CLOCK_STAT_SL                                      , RULL(0x36030008), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_CLOCK_STAT_SL                                      , RULL(0x37030008), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_CLOCK_STAT_SL                                        , RULL(0x10030008), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_CLOCK_STAT_SL                                      , RULL(0x10030008), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_CLOCK_STAT_SL                                      , RULL(0x11030008), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_CLOCK_STAT_SL                                      , RULL(0x12030008), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_CLOCK_STAT_SL                                      , RULL(0x13030008), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_CLOCK_STAT_SL                                      , RULL(0x14030008), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_CLOCK_STAT_SL                                      , RULL(0x15030008), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_CLOCK_STAT_SL                                        , RULL(0x20030008), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21030008,
+REG64( EX_0_CLOCK_STAT_SL                                      , RULL(0x20030008), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21030008,
+REG64( EX_1_CLOCK_STAT_SL                                      , RULL(0x22030008), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23030008,
+REG64( EX_2_CLOCK_STAT_SL                                      , RULL(0x24030008), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25030008,
+REG64( EX_3_CLOCK_STAT_SL                                      , RULL(0x26030008), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27030008,
+REG64( EX_4_CLOCK_STAT_SL                                      , RULL(0x28030008), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29030008,
+REG64( EX_5_CLOCK_STAT_SL                                      , RULL(0x2A030008), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B030008,
+REG64( EX_6_CLOCK_STAT_SL                                      , RULL(0x2C030008), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D030008,
+REG64( EX_7_CLOCK_STAT_SL                                      , RULL(0x2E030008), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F030008,
+REG64( EX_8_CLOCK_STAT_SL                                      , RULL(0x30030008), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31030008,
+REG64( EX_9_CLOCK_STAT_SL                                      , RULL(0x32030008), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33030008,
+REG64( EX_10_CLOCK_STAT_SL                                     , RULL(0x34030008), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35030008,
+REG64( EX_11_CLOCK_STAT_SL                                     , RULL(0x36030008), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37030008,
+
+REG64( EX_CME_LCL_DBG_PPE                                      , RULL(0x109010120), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_LCL_DBG_PPE1                                     , RULL(0x109010138), SH_UNT_EX       ,
+       SH_ACS_PPE1      );
+REG64( EX_CME_LCL_DBG_PPE2                                     , RULL(0x109010130), SH_UNT_EX       ,
+       SH_ACS_PPE2      );
+REG64( EX_0_CME_LCL_DBG_PPE                                    , RULL(0x109010120), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_LCL_DBG_PPE1                                   , RULL(0x109010138), SH_UNT_EX_0     ,
+       SH_ACS_PPE1      );
+REG64( EX_0_CME_LCL_DBG_PPE2                                   , RULL(0x109010130), SH_UNT_EX_0     ,
+       SH_ACS_PPE2      );
+REG64( EX_1_CME_LCL_DBG_PPE                                    , RULL(0x109020120), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_LCL_DBG_PPE1                                   , RULL(0x109020138), SH_UNT_EX_1     ,
+       SH_ACS_PPE1      );
+REG64( EX_1_CME_LCL_DBG_PPE2                                   , RULL(0x109020130), SH_UNT_EX_1     ,
+       SH_ACS_PPE2      );
+REG64( EX_2_CME_LCL_DBG_PPE                                    , RULL(0x10A010120), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_LCL_DBG_PPE1                                   , RULL(0x10A010138), SH_UNT_EX_2     ,
+       SH_ACS_PPE1      );
+REG64( EX_2_CME_LCL_DBG_PPE2                                   , RULL(0x10A010130), SH_UNT_EX_2     ,
+       SH_ACS_PPE2      );
+REG64( EX_3_CME_LCL_DBG_PPE                                    , RULL(0x10A020120), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_LCL_DBG_PPE1                                   , RULL(0x10A020138), SH_UNT_EX_3     ,
+       SH_ACS_PPE1      );
+REG64( EX_3_CME_LCL_DBG_PPE2                                   , RULL(0x10A020130), SH_UNT_EX_3     ,
+       SH_ACS_PPE2      );
+REG64( EX_4_CME_LCL_DBG_PPE                                    , RULL(0x10B010120), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_LCL_DBG_PPE1                                   , RULL(0x10B010138), SH_UNT_EX_4     ,
+       SH_ACS_PPE1      );
+REG64( EX_4_CME_LCL_DBG_PPE2                                   , RULL(0x10B010130), SH_UNT_EX_4     ,
+       SH_ACS_PPE2      );
+REG64( EX_5_CME_LCL_DBG_PPE                                    , RULL(0x10B020120), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_LCL_DBG_PPE1                                   , RULL(0x10B020138), SH_UNT_EX_5     ,
+       SH_ACS_PPE1      );
+REG64( EX_5_CME_LCL_DBG_PPE2                                   , RULL(0x10B020130), SH_UNT_EX_5     ,
+       SH_ACS_PPE2      );
+REG64( EX_6_CME_LCL_DBG_PPE                                    , RULL(0x10C010120), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_LCL_DBG_PPE1                                   , RULL(0x10C010138), SH_UNT_EX_6     ,
+       SH_ACS_PPE1      );
+REG64( EX_6_CME_LCL_DBG_PPE2                                   , RULL(0x10C010130), SH_UNT_EX_6     ,
+       SH_ACS_PPE2      );
+REG64( EX_7_CME_LCL_DBG_PPE                                    , RULL(0x10C020120), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_LCL_DBG_PPE1                                   , RULL(0x10C020138), SH_UNT_EX_7     ,
+       SH_ACS_PPE1      );
+REG64( EX_7_CME_LCL_DBG_PPE2                                   , RULL(0x10C020130), SH_UNT_EX_7     ,
+       SH_ACS_PPE2      );
+REG64( EX_8_CME_LCL_DBG_PPE                                    , RULL(0x10D010120), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_LCL_DBG_PPE1                                   , RULL(0x10D010138), SH_UNT_EX_8     ,
+       SH_ACS_PPE1      );
+REG64( EX_8_CME_LCL_DBG_PPE2                                   , RULL(0x10D010130), SH_UNT_EX_8     ,
+       SH_ACS_PPE2      );
+REG64( EX_9_CME_LCL_DBG_PPE                                    , RULL(0x10D020120), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_LCL_DBG_PPE1                                   , RULL(0x10D020138), SH_UNT_EX_9     ,
+       SH_ACS_PPE1      );
+REG64( EX_9_CME_LCL_DBG_PPE2                                   , RULL(0x10D020130), SH_UNT_EX_9     ,
+       SH_ACS_PPE2      );
+REG64( EX_10_CME_LCL_DBG_PPE                                   , RULL(0x10E010120), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_LCL_DBG_PPE1                                  , RULL(0x10E010138), SH_UNT_EX_10    ,
+       SH_ACS_PPE1      );
+REG64( EX_10_CME_LCL_DBG_PPE2                                  , RULL(0x10E010130), SH_UNT_EX_10    ,
+       SH_ACS_PPE2      );
+REG64( EX_11_CME_LCL_DBG_PPE                                   , RULL(0x10E020120), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_LCL_DBG_PPE1                                  , RULL(0x10E020138), SH_UNT_EX_11    ,
+       SH_ACS_PPE1      );
+REG64( EX_11_CME_LCL_DBG_PPE2                                  , RULL(0x10E020130), SH_UNT_EX_11    ,
+       SH_ACS_PPE2      );
+
+REG64( EQ_CME_LCL_EIMR                                         , RULL(0x10012426), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012026,
+REG64( EQ_0_CME_LCL_EIMR                                       , RULL(0x10012426), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012026,
+REG64( EQ_1_CME_LCL_EIMR                                       , RULL(0x11012426), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012026,
+REG64( EQ_2_CME_LCL_EIMR                                       , RULL(0x12012426), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012026,
+REG64( EQ_3_CME_LCL_EIMR                                       , RULL(0x13012426), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012026,
+REG64( EQ_4_CME_LCL_EIMR                                       , RULL(0x14012426), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012026,
+REG64( EQ_5_CME_LCL_EIMR                                       , RULL(0x15012426), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012026,
+REG64( EX_CME_LCL_EIMR_PPE                                     , RULL(0x109010020), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_LCL_EIMR_PPE1                                    , RULL(0x109010038), SH_UNT_EX       ,
+       SH_ACS_PPE1      );
+REG64( EX_CME_LCL_EIMR_PPE2                                    , RULL(0x109010030), SH_UNT_EX       ,
+       SH_ACS_PPE2      );
+REG64( EX_CME_LCL_EIMR_SCOM                                    , RULL(0x10012026), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_LCL_EIMR_PPE                                   , RULL(0x109010020), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_LCL_EIMR_PPE1                                  , RULL(0x109010038), SH_UNT_EX_0     ,
+       SH_ACS_PPE1      );
+REG64( EX_0_CME_LCL_EIMR_PPE2                                  , RULL(0x109010030), SH_UNT_EX_0     ,
+       SH_ACS_PPE2      );
+REG64( EX_0_CME_LCL_EIMR_SCOM                                  , RULL(0x10012026), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_LCL_EIMR_PPE                                   , RULL(0x109020020), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_LCL_EIMR_PPE1                                  , RULL(0x109020038), SH_UNT_EX_1     ,
+       SH_ACS_PPE1      );
+REG64( EX_1_CME_LCL_EIMR_PPE2                                  , RULL(0x109020030), SH_UNT_EX_1     ,
+       SH_ACS_PPE2      );
+REG64( EX_1_CME_LCL_EIMR_SCOM                                  , RULL(0x10012426), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_LCL_EIMR_PPE                                   , RULL(0x10A010020), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_LCL_EIMR_PPE1                                  , RULL(0x10A010038), SH_UNT_EX_2     ,
+       SH_ACS_PPE1      );
+REG64( EX_2_CME_LCL_EIMR_PPE2                                  , RULL(0x10A010030), SH_UNT_EX_2     ,
+       SH_ACS_PPE2      );
+REG64( EX_2_CME_LCL_EIMR_SCOM                                  , RULL(0x11012026), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_LCL_EIMR_PPE                                   , RULL(0x10A020020), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_LCL_EIMR_PPE1                                  , RULL(0x10A020038), SH_UNT_EX_3     ,
+       SH_ACS_PPE1      );
+REG64( EX_3_CME_LCL_EIMR_PPE2                                  , RULL(0x10A020030), SH_UNT_EX_3     ,
+       SH_ACS_PPE2      );
+REG64( EX_3_CME_LCL_EIMR_SCOM                                  , RULL(0x11012426), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_LCL_EIMR_PPE                                   , RULL(0x10B010020), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_LCL_EIMR_PPE1                                  , RULL(0x10B010038), SH_UNT_EX_4     ,
+       SH_ACS_PPE1      );
+REG64( EX_4_CME_LCL_EIMR_PPE2                                  , RULL(0x10B010030), SH_UNT_EX_4     ,
+       SH_ACS_PPE2      );
+REG64( EX_4_CME_LCL_EIMR_SCOM                                  , RULL(0x12012026), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_LCL_EIMR_PPE                                   , RULL(0x10B020020), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_LCL_EIMR_PPE1                                  , RULL(0x10B020038), SH_UNT_EX_5     ,
+       SH_ACS_PPE1      );
+REG64( EX_5_CME_LCL_EIMR_PPE2                                  , RULL(0x10B020030), SH_UNT_EX_5     ,
+       SH_ACS_PPE2      );
+REG64( EX_5_CME_LCL_EIMR_SCOM                                  , RULL(0x12012426), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_LCL_EIMR_PPE                                   , RULL(0x10C010020), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_LCL_EIMR_PPE1                                  , RULL(0x10C010038), SH_UNT_EX_6     ,
+       SH_ACS_PPE1      );
+REG64( EX_6_CME_LCL_EIMR_PPE2                                  , RULL(0x10C010030), SH_UNT_EX_6     ,
+       SH_ACS_PPE2      );
+REG64( EX_6_CME_LCL_EIMR_SCOM                                  , RULL(0x13012026), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_LCL_EIMR_PPE                                   , RULL(0x10C020020), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_LCL_EIMR_PPE1                                  , RULL(0x10C020038), SH_UNT_EX_7     ,
+       SH_ACS_PPE1      );
+REG64( EX_7_CME_LCL_EIMR_PPE2                                  , RULL(0x10C020030), SH_UNT_EX_7     ,
+       SH_ACS_PPE2      );
+REG64( EX_7_CME_LCL_EIMR_SCOM                                  , RULL(0x13012426), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_LCL_EIMR_PPE                                   , RULL(0x10D010020), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_LCL_EIMR_PPE1                                  , RULL(0x10D010038), SH_UNT_EX_8     ,
+       SH_ACS_PPE1      );
+REG64( EX_8_CME_LCL_EIMR_PPE2                                  , RULL(0x10D010030), SH_UNT_EX_8     ,
+       SH_ACS_PPE2      );
+REG64( EX_8_CME_LCL_EIMR_SCOM                                  , RULL(0x14012026), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_LCL_EIMR_PPE                                   , RULL(0x10D020020), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_LCL_EIMR_PPE1                                  , RULL(0x10D020038), SH_UNT_EX_9     ,
+       SH_ACS_PPE1      );
+REG64( EX_9_CME_LCL_EIMR_PPE2                                  , RULL(0x10D020030), SH_UNT_EX_9     ,
+       SH_ACS_PPE2      );
+REG64( EX_9_CME_LCL_EIMR_SCOM                                  , RULL(0x14012426), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_LCL_EIMR_PPE                                  , RULL(0x10E010020), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_LCL_EIMR_PPE1                                 , RULL(0x10E010038), SH_UNT_EX_10    ,
+       SH_ACS_PPE1      );
+REG64( EX_10_CME_LCL_EIMR_PPE2                                 , RULL(0x10E010030), SH_UNT_EX_10    ,
+       SH_ACS_PPE2      );
+REG64( EX_10_CME_LCL_EIMR_SCOM                                 , RULL(0x15012026), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_LCL_EIMR_PPE                                  , RULL(0x10E020020), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_LCL_EIMR_PPE1                                 , RULL(0x10E020038), SH_UNT_EX_11    ,
+       SH_ACS_PPE1      );
+REG64( EX_11_CME_LCL_EIMR_PPE2                                 , RULL(0x10E020030), SH_UNT_EX_11    ,
+       SH_ACS_PPE2      );
+REG64( EX_11_CME_LCL_EIMR_SCOM                                 , RULL(0x15012426), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_LCL_EINR                                         , RULL(0x1001242A), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001202A,
+REG64( EQ_0_CME_LCL_EINR                                       , RULL(0x1001242A), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001202A,
+REG64( EQ_1_CME_LCL_EINR                                       , RULL(0x1101242A), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1101202A,
+REG64( EQ_2_CME_LCL_EINR                                       , RULL(0x1201242A), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1201202A,
+REG64( EQ_3_CME_LCL_EINR                                       , RULL(0x1301242A), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1301202A,
+REG64( EQ_4_CME_LCL_EINR                                       , RULL(0x1401242A), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1401202A,
+REG64( EQ_5_CME_LCL_EINR                                       , RULL(0x1501242A), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1501202A,
+REG64( EX_CME_LCL_EINR_PPE                                     , RULL(0x1090100A0), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_LCL_EINR_SCOM                                    , RULL(0x1001202A), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_LCL_EINR_PPE                                   , RULL(0x1090100A0), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_LCL_EINR_SCOM                                  , RULL(0x1001202A), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_LCL_EINR_PPE                                   , RULL(0x1090200A0), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_LCL_EINR_SCOM                                  , RULL(0x1001242A), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_LCL_EINR_PPE                                   , RULL(0x10A0100A0), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_LCL_EINR_SCOM                                  , RULL(0x1101202A), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_LCL_EINR_PPE                                   , RULL(0x10A0200A0), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_LCL_EINR_SCOM                                  , RULL(0x1101242A), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_LCL_EINR_PPE                                   , RULL(0x10B0100A0), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_LCL_EINR_SCOM                                  , RULL(0x1201202A), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_LCL_EINR_PPE                                   , RULL(0x10B0200A0), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_LCL_EINR_SCOM                                  , RULL(0x1201242A), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_LCL_EINR_PPE                                   , RULL(0x10C0100A0), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_LCL_EINR_SCOM                                  , RULL(0x1301202A), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_LCL_EINR_PPE                                   , RULL(0x10C0200A0), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_LCL_EINR_SCOM                                  , RULL(0x1301242A), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_LCL_EINR_PPE                                   , RULL(0x10D0100A0), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_LCL_EINR_SCOM                                  , RULL(0x1401202A), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_LCL_EINR_PPE                                   , RULL(0x10D0200A0), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_LCL_EINR_SCOM                                  , RULL(0x1401242A), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_LCL_EINR_PPE                                  , RULL(0x10E0100A0), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_LCL_EINR_SCOM                                 , RULL(0x1501202A), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_LCL_EINR_PPE                                  , RULL(0x10E0200A0), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_LCL_EINR_SCOM                                 , RULL(0x1501242A), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_LCL_EIPR                                         , RULL(0x10012427), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012027,
+REG64( EQ_0_CME_LCL_EIPR                                       , RULL(0x10012427), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012027,
+REG64( EQ_1_CME_LCL_EIPR                                       , RULL(0x11012427), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012027,
+REG64( EQ_2_CME_LCL_EIPR                                       , RULL(0x12012427), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012027,
+REG64( EQ_3_CME_LCL_EIPR                                       , RULL(0x13012427), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012027,
+REG64( EQ_4_CME_LCL_EIPR                                       , RULL(0x14012427), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012027,
+REG64( EQ_5_CME_LCL_EIPR                                       , RULL(0x15012427), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012027,
+REG64( EX_CME_LCL_EIPR_PPE                                     , RULL(0x109010040), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_LCL_EIPR_PPE1                                    , RULL(0x109010058), SH_UNT_EX       ,
+       SH_ACS_PPE1      );
+REG64( EX_CME_LCL_EIPR_PPE2                                    , RULL(0x109010050), SH_UNT_EX       ,
+       SH_ACS_PPE2      );
+REG64( EX_CME_LCL_EIPR_SCOM                                    , RULL(0x10012027), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_LCL_EIPR_PPE                                   , RULL(0x109010040), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_LCL_EIPR_PPE1                                  , RULL(0x109010058), SH_UNT_EX_0     ,
+       SH_ACS_PPE1      );
+REG64( EX_0_CME_LCL_EIPR_PPE2                                  , RULL(0x109010050), SH_UNT_EX_0     ,
+       SH_ACS_PPE2      );
+REG64( EX_0_CME_LCL_EIPR_SCOM                                  , RULL(0x10012027), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_LCL_EIPR_PPE                                   , RULL(0x109020040), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_LCL_EIPR_PPE1                                  , RULL(0x109020058), SH_UNT_EX_1     ,
+       SH_ACS_PPE1      );
+REG64( EX_1_CME_LCL_EIPR_PPE2                                  , RULL(0x109020050), SH_UNT_EX_1     ,
+       SH_ACS_PPE2      );
+REG64( EX_1_CME_LCL_EIPR_SCOM                                  , RULL(0x10012427), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_LCL_EIPR_PPE                                   , RULL(0x10A010040), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_LCL_EIPR_PPE1                                  , RULL(0x10A010058), SH_UNT_EX_2     ,
+       SH_ACS_PPE1      );
+REG64( EX_2_CME_LCL_EIPR_PPE2                                  , RULL(0x10A010050), SH_UNT_EX_2     ,
+       SH_ACS_PPE2      );
+REG64( EX_2_CME_LCL_EIPR_SCOM                                  , RULL(0x11012027), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_LCL_EIPR_PPE                                   , RULL(0x10A020040), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_LCL_EIPR_PPE1                                  , RULL(0x10A020058), SH_UNT_EX_3     ,
+       SH_ACS_PPE1      );
+REG64( EX_3_CME_LCL_EIPR_PPE2                                  , RULL(0x10A020050), SH_UNT_EX_3     ,
+       SH_ACS_PPE2      );
+REG64( EX_3_CME_LCL_EIPR_SCOM                                  , RULL(0x11012427), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_LCL_EIPR_PPE                                   , RULL(0x10B010040), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_LCL_EIPR_PPE1                                  , RULL(0x10B010058), SH_UNT_EX_4     ,
+       SH_ACS_PPE1      );
+REG64( EX_4_CME_LCL_EIPR_PPE2                                  , RULL(0x10B010050), SH_UNT_EX_4     ,
+       SH_ACS_PPE2      );
+REG64( EX_4_CME_LCL_EIPR_SCOM                                  , RULL(0x12012027), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_LCL_EIPR_PPE                                   , RULL(0x10B020040), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_LCL_EIPR_PPE1                                  , RULL(0x10B020058), SH_UNT_EX_5     ,
+       SH_ACS_PPE1      );
+REG64( EX_5_CME_LCL_EIPR_PPE2                                  , RULL(0x10B020050), SH_UNT_EX_5     ,
+       SH_ACS_PPE2      );
+REG64( EX_5_CME_LCL_EIPR_SCOM                                  , RULL(0x12012427), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_LCL_EIPR_PPE                                   , RULL(0x10C010040), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_LCL_EIPR_PPE1                                  , RULL(0x10C010058), SH_UNT_EX_6     ,
+       SH_ACS_PPE1      );
+REG64( EX_6_CME_LCL_EIPR_PPE2                                  , RULL(0x10C010050), SH_UNT_EX_6     ,
+       SH_ACS_PPE2      );
+REG64( EX_6_CME_LCL_EIPR_SCOM                                  , RULL(0x13012027), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_LCL_EIPR_PPE                                   , RULL(0x10C020040), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_LCL_EIPR_PPE1                                  , RULL(0x10C020058), SH_UNT_EX_7     ,
+       SH_ACS_PPE1      );
+REG64( EX_7_CME_LCL_EIPR_PPE2                                  , RULL(0x10C020050), SH_UNT_EX_7     ,
+       SH_ACS_PPE2      );
+REG64( EX_7_CME_LCL_EIPR_SCOM                                  , RULL(0x13012427), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_LCL_EIPR_PPE                                   , RULL(0x10D010040), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_LCL_EIPR_PPE1                                  , RULL(0x10D010058), SH_UNT_EX_8     ,
+       SH_ACS_PPE1      );
+REG64( EX_8_CME_LCL_EIPR_PPE2                                  , RULL(0x10D010050), SH_UNT_EX_8     ,
+       SH_ACS_PPE2      );
+REG64( EX_8_CME_LCL_EIPR_SCOM                                  , RULL(0x14012027), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_LCL_EIPR_PPE                                   , RULL(0x10D020040), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_LCL_EIPR_PPE1                                  , RULL(0x10D020058), SH_UNT_EX_9     ,
+       SH_ACS_PPE1      );
+REG64( EX_9_CME_LCL_EIPR_PPE2                                  , RULL(0x10D020050), SH_UNT_EX_9     ,
+       SH_ACS_PPE2      );
+REG64( EX_9_CME_LCL_EIPR_SCOM                                  , RULL(0x14012427), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_LCL_EIPR_PPE                                  , RULL(0x10E010040), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_LCL_EIPR_PPE1                                 , RULL(0x10E010058), SH_UNT_EX_10    ,
+       SH_ACS_PPE1      );
+REG64( EX_10_CME_LCL_EIPR_PPE2                                 , RULL(0x10E010050), SH_UNT_EX_10    ,
+       SH_ACS_PPE2      );
+REG64( EX_10_CME_LCL_EIPR_SCOM                                 , RULL(0x15012027), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_LCL_EIPR_PPE                                  , RULL(0x10E020040), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_LCL_EIPR_PPE1                                 , RULL(0x10E020058), SH_UNT_EX_11    ,
+       SH_ACS_PPE1      );
+REG64( EX_11_CME_LCL_EIPR_PPE2                                 , RULL(0x10E020050), SH_UNT_EX_11    ,
+       SH_ACS_PPE2      );
+REG64( EX_11_CME_LCL_EIPR_SCOM                                 , RULL(0x15012427), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_LCL_EISR                                         , RULL(0x10012425), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012025,
+REG64( EQ_0_CME_LCL_EISR                                       , RULL(0x10012425), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012025,
+REG64( EQ_1_CME_LCL_EISR                                       , RULL(0x11012425), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012025,
+REG64( EQ_2_CME_LCL_EISR                                       , RULL(0x12012425), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012025,
+REG64( EQ_3_CME_LCL_EISR                                       , RULL(0x13012425), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012025,
+REG64( EQ_4_CME_LCL_EISR                                       , RULL(0x14012425), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012025,
+REG64( EQ_5_CME_LCL_EISR                                       , RULL(0x15012425), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012025,
+REG64( EX_CME_LCL_EISR_PPE                                     , RULL(0x109010000), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_LCL_EISR_PPE1                                    , RULL(0x109010018), SH_UNT_EX       ,
+       SH_ACS_PPE1      );
+REG64( EX_CME_LCL_EISR_PPE2                                    , RULL(0x109010010), SH_UNT_EX       ,
+       SH_ACS_PPE2      );
+REG64( EX_CME_LCL_EISR_SCOM                                    , RULL(0x10012025), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_LCL_EISR_PPE                                   , RULL(0x109010000), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_LCL_EISR_PPE1                                  , RULL(0x109010018), SH_UNT_EX_0     ,
+       SH_ACS_PPE1      );
+REG64( EX_0_CME_LCL_EISR_PPE2                                  , RULL(0x109010010), SH_UNT_EX_0     ,
+       SH_ACS_PPE2      );
+REG64( EX_0_CME_LCL_EISR_SCOM                                  , RULL(0x10012025), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_LCL_EISR_PPE                                   , RULL(0x109020000), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_LCL_EISR_PPE1                                  , RULL(0x109020018), SH_UNT_EX_1     ,
+       SH_ACS_PPE1      );
+REG64( EX_1_CME_LCL_EISR_PPE2                                  , RULL(0x109020010), SH_UNT_EX_1     ,
+       SH_ACS_PPE2      );
+REG64( EX_1_CME_LCL_EISR_SCOM                                  , RULL(0x10012425), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_LCL_EISR_PPE                                   , RULL(0x10A010000), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_LCL_EISR_PPE1                                  , RULL(0x10A010018), SH_UNT_EX_2     ,
+       SH_ACS_PPE1      );
+REG64( EX_2_CME_LCL_EISR_PPE2                                  , RULL(0x10A010010), SH_UNT_EX_2     ,
+       SH_ACS_PPE2      );
+REG64( EX_2_CME_LCL_EISR_SCOM                                  , RULL(0x11012025), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_LCL_EISR_PPE                                   , RULL(0x10A020000), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_LCL_EISR_PPE1                                  , RULL(0x10A020018), SH_UNT_EX_3     ,
+       SH_ACS_PPE1      );
+REG64( EX_3_CME_LCL_EISR_PPE2                                  , RULL(0x10A020010), SH_UNT_EX_3     ,
+       SH_ACS_PPE2      );
+REG64( EX_3_CME_LCL_EISR_SCOM                                  , RULL(0x11012425), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_LCL_EISR_PPE                                   , RULL(0x10B010000), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_LCL_EISR_PPE1                                  , RULL(0x10B010018), SH_UNT_EX_4     ,
+       SH_ACS_PPE1      );
+REG64( EX_4_CME_LCL_EISR_PPE2                                  , RULL(0x10B010010), SH_UNT_EX_4     ,
+       SH_ACS_PPE2      );
+REG64( EX_4_CME_LCL_EISR_SCOM                                  , RULL(0x12012025), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_LCL_EISR_PPE                                   , RULL(0x10B020000), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_LCL_EISR_PPE1                                  , RULL(0x10B020018), SH_UNT_EX_5     ,
+       SH_ACS_PPE1      );
+REG64( EX_5_CME_LCL_EISR_PPE2                                  , RULL(0x10B020010), SH_UNT_EX_5     ,
+       SH_ACS_PPE2      );
+REG64( EX_5_CME_LCL_EISR_SCOM                                  , RULL(0x12012425), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_LCL_EISR_PPE                                   , RULL(0x10C010000), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_LCL_EISR_PPE1                                  , RULL(0x10C010018), SH_UNT_EX_6     ,
+       SH_ACS_PPE1      );
+REG64( EX_6_CME_LCL_EISR_PPE2                                  , RULL(0x10C010010), SH_UNT_EX_6     ,
+       SH_ACS_PPE2      );
+REG64( EX_6_CME_LCL_EISR_SCOM                                  , RULL(0x13012025), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_LCL_EISR_PPE                                   , RULL(0x10C020000), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_LCL_EISR_PPE1                                  , RULL(0x10C020018), SH_UNT_EX_7     ,
+       SH_ACS_PPE1      );
+REG64( EX_7_CME_LCL_EISR_PPE2                                  , RULL(0x10C020010), SH_UNT_EX_7     ,
+       SH_ACS_PPE2      );
+REG64( EX_7_CME_LCL_EISR_SCOM                                  , RULL(0x13012425), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_LCL_EISR_PPE                                   , RULL(0x10D010000), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_LCL_EISR_PPE1                                  , RULL(0x10D010018), SH_UNT_EX_8     ,
+       SH_ACS_PPE1      );
+REG64( EX_8_CME_LCL_EISR_PPE2                                  , RULL(0x10D010010), SH_UNT_EX_8     ,
+       SH_ACS_PPE2      );
+REG64( EX_8_CME_LCL_EISR_SCOM                                  , RULL(0x14012025), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_LCL_EISR_PPE                                   , RULL(0x10D020000), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_LCL_EISR_PPE1                                  , RULL(0x10D020018), SH_UNT_EX_9     ,
+       SH_ACS_PPE1      );
+REG64( EX_9_CME_LCL_EISR_PPE2                                  , RULL(0x10D020010), SH_UNT_EX_9     ,
+       SH_ACS_PPE2      );
+REG64( EX_9_CME_LCL_EISR_SCOM                                  , RULL(0x14012425), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_LCL_EISR_PPE                                  , RULL(0x10E010000), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_LCL_EISR_PPE1                                 , RULL(0x10E010018), SH_UNT_EX_10    ,
+       SH_ACS_PPE1      );
+REG64( EX_10_CME_LCL_EISR_PPE2                                 , RULL(0x10E010010), SH_UNT_EX_10    ,
+       SH_ACS_PPE2      );
+REG64( EX_10_CME_LCL_EISR_SCOM                                 , RULL(0x15012025), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_LCL_EISR_PPE                                  , RULL(0x10E020000), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_LCL_EISR_PPE1                                 , RULL(0x10E020018), SH_UNT_EX_11    ,
+       SH_ACS_PPE1      );
+REG64( EX_11_CME_LCL_EISR_PPE2                                 , RULL(0x10E020010), SH_UNT_EX_11    ,
+       SH_ACS_PPE2      );
+REG64( EX_11_CME_LCL_EISR_SCOM                                 , RULL(0x15012425), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_LCL_EISTR                                        , RULL(0x10012429), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012029,
+REG64( EQ_0_CME_LCL_EISTR                                      , RULL(0x10012429), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012029,
+REG64( EQ_1_CME_LCL_EISTR                                      , RULL(0x11012429), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012029,
+REG64( EQ_2_CME_LCL_EISTR                                      , RULL(0x12012429), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012029,
+REG64( EQ_3_CME_LCL_EISTR                                      , RULL(0x13012429), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012029,
+REG64( EQ_4_CME_LCL_EISTR                                      , RULL(0x14012429), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012029,
+REG64( EQ_5_CME_LCL_EISTR                                      , RULL(0x15012429), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012029,
+REG64( EX_CME_LCL_EISTR_PPE                                    , RULL(0x109010080), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_LCL_EISTR_SCOM                                   , RULL(0x10012029), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_LCL_EISTR_PPE                                  , RULL(0x109010080), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_LCL_EISTR_SCOM                                 , RULL(0x10012029), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_LCL_EISTR_PPE                                  , RULL(0x109020080), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_LCL_EISTR_SCOM                                 , RULL(0x10012429), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_LCL_EISTR_PPE                                  , RULL(0x10A010080), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_LCL_EISTR_SCOM                                 , RULL(0x11012029), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_LCL_EISTR_PPE                                  , RULL(0x10A020080), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_LCL_EISTR_SCOM                                 , RULL(0x11012429), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_LCL_EISTR_PPE                                  , RULL(0x10B010080), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_LCL_EISTR_SCOM                                 , RULL(0x12012029), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_LCL_EISTR_PPE                                  , RULL(0x10B020080), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_LCL_EISTR_SCOM                                 , RULL(0x12012429), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_LCL_EISTR_PPE                                  , RULL(0x10C010080), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_LCL_EISTR_SCOM                                 , RULL(0x13012029), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_LCL_EISTR_PPE                                  , RULL(0x10C020080), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_LCL_EISTR_SCOM                                 , RULL(0x13012429), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_LCL_EISTR_PPE                                  , RULL(0x10D010080), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_LCL_EISTR_SCOM                                 , RULL(0x14012029), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_LCL_EISTR_PPE                                  , RULL(0x10D020080), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_LCL_EISTR_SCOM                                 , RULL(0x14012429), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_LCL_EISTR_PPE                                 , RULL(0x10E010080), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_LCL_EISTR_SCOM                                , RULL(0x15012029), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_LCL_EISTR_PPE                                 , RULL(0x10E020080), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_LCL_EISTR_SCOM                                , RULL(0x15012429), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_LCL_EITR                                         , RULL(0x10012428), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012028,
+REG64( EQ_0_CME_LCL_EITR                                       , RULL(0x10012428), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012028,
+REG64( EQ_1_CME_LCL_EITR                                       , RULL(0x11012428), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012028,
+REG64( EQ_2_CME_LCL_EITR                                       , RULL(0x12012428), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012028,
+REG64( EQ_3_CME_LCL_EITR                                       , RULL(0x13012428), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012028,
+REG64( EQ_4_CME_LCL_EITR                                       , RULL(0x14012428), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012028,
+REG64( EQ_5_CME_LCL_EITR                                       , RULL(0x15012428), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012028,
+REG64( EX_CME_LCL_EITR_PPE                                     , RULL(0x109010060), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_LCL_EITR_PPE1                                    , RULL(0x109010078), SH_UNT_EX       ,
+       SH_ACS_PPE1      );
+REG64( EX_CME_LCL_EITR_PPE2                                    , RULL(0x109010070), SH_UNT_EX       ,
+       SH_ACS_PPE2      );
+REG64( EX_CME_LCL_EITR_SCOM                                    , RULL(0x10012028), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_LCL_EITR_PPE                                   , RULL(0x109010060), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_LCL_EITR_PPE1                                  , RULL(0x109010078), SH_UNT_EX_0     ,
+       SH_ACS_PPE1      );
+REG64( EX_0_CME_LCL_EITR_PPE2                                  , RULL(0x109010070), SH_UNT_EX_0     ,
+       SH_ACS_PPE2      );
+REG64( EX_0_CME_LCL_EITR_SCOM                                  , RULL(0x10012028), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_LCL_EITR_PPE                                   , RULL(0x109020060), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_LCL_EITR_PPE1                                  , RULL(0x109020078), SH_UNT_EX_1     ,
+       SH_ACS_PPE1      );
+REG64( EX_1_CME_LCL_EITR_PPE2                                  , RULL(0x109020070), SH_UNT_EX_1     ,
+       SH_ACS_PPE2      );
+REG64( EX_1_CME_LCL_EITR_SCOM                                  , RULL(0x10012428), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_LCL_EITR_PPE                                   , RULL(0x10A010060), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_LCL_EITR_PPE1                                  , RULL(0x10A010078), SH_UNT_EX_2     ,
+       SH_ACS_PPE1      );
+REG64( EX_2_CME_LCL_EITR_PPE2                                  , RULL(0x10A010070), SH_UNT_EX_2     ,
+       SH_ACS_PPE2      );
+REG64( EX_2_CME_LCL_EITR_SCOM                                  , RULL(0x11012028), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_LCL_EITR_PPE                                   , RULL(0x10A020060), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_LCL_EITR_PPE1                                  , RULL(0x10A020078), SH_UNT_EX_3     ,
+       SH_ACS_PPE1      );
+REG64( EX_3_CME_LCL_EITR_PPE2                                  , RULL(0x10A020070), SH_UNT_EX_3     ,
+       SH_ACS_PPE2      );
+REG64( EX_3_CME_LCL_EITR_SCOM                                  , RULL(0x11012428), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_LCL_EITR_PPE                                   , RULL(0x10B010060), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_LCL_EITR_PPE1                                  , RULL(0x10B010078), SH_UNT_EX_4     ,
+       SH_ACS_PPE1      );
+REG64( EX_4_CME_LCL_EITR_PPE2                                  , RULL(0x10B010070), SH_UNT_EX_4     ,
+       SH_ACS_PPE2      );
+REG64( EX_4_CME_LCL_EITR_SCOM                                  , RULL(0x12012028), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_LCL_EITR_PPE                                   , RULL(0x10B020060), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_LCL_EITR_PPE1                                  , RULL(0x10B020078), SH_UNT_EX_5     ,
+       SH_ACS_PPE1      );
+REG64( EX_5_CME_LCL_EITR_PPE2                                  , RULL(0x10B020070), SH_UNT_EX_5     ,
+       SH_ACS_PPE2      );
+REG64( EX_5_CME_LCL_EITR_SCOM                                  , RULL(0x12012428), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_LCL_EITR_PPE                                   , RULL(0x10C010060), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_LCL_EITR_PPE1                                  , RULL(0x10C010078), SH_UNT_EX_6     ,
+       SH_ACS_PPE1      );
+REG64( EX_6_CME_LCL_EITR_PPE2                                  , RULL(0x10C010070), SH_UNT_EX_6     ,
+       SH_ACS_PPE2      );
+REG64( EX_6_CME_LCL_EITR_SCOM                                  , RULL(0x13012028), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_LCL_EITR_PPE                                   , RULL(0x10C020060), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_LCL_EITR_PPE1                                  , RULL(0x10C020078), SH_UNT_EX_7     ,
+       SH_ACS_PPE1      );
+REG64( EX_7_CME_LCL_EITR_PPE2                                  , RULL(0x10C020070), SH_UNT_EX_7     ,
+       SH_ACS_PPE2      );
+REG64( EX_7_CME_LCL_EITR_SCOM                                  , RULL(0x13012428), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_LCL_EITR_PPE                                   , RULL(0x10D010060), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_LCL_EITR_PPE1                                  , RULL(0x10D010078), SH_UNT_EX_8     ,
+       SH_ACS_PPE1      );
+REG64( EX_8_CME_LCL_EITR_PPE2                                  , RULL(0x10D010070), SH_UNT_EX_8     ,
+       SH_ACS_PPE2      );
+REG64( EX_8_CME_LCL_EITR_SCOM                                  , RULL(0x14012028), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_LCL_EITR_PPE                                   , RULL(0x10D020060), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_LCL_EITR_PPE1                                  , RULL(0x10D020078), SH_UNT_EX_9     ,
+       SH_ACS_PPE1      );
+REG64( EX_9_CME_LCL_EITR_PPE2                                  , RULL(0x10D020070), SH_UNT_EX_9     ,
+       SH_ACS_PPE2      );
+REG64( EX_9_CME_LCL_EITR_SCOM                                  , RULL(0x14012428), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_LCL_EITR_PPE                                  , RULL(0x10E010060), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_LCL_EITR_PPE1                                 , RULL(0x10E010078), SH_UNT_EX_10    ,
+       SH_ACS_PPE1      );
+REG64( EX_10_CME_LCL_EITR_PPE2                                 , RULL(0x10E010070), SH_UNT_EX_10    ,
+       SH_ACS_PPE2      );
+REG64( EX_10_CME_LCL_EITR_SCOM                                 , RULL(0x15012028), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_LCL_EITR_PPE                                  , RULL(0x10E020060), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_LCL_EITR_PPE1                                 , RULL(0x10E020078), SH_UNT_EX_11    ,
+       SH_ACS_PPE1      );
+REG64( EX_11_CME_LCL_EITR_PPE2                                 , RULL(0x10E020070), SH_UNT_EX_11    ,
+       SH_ACS_PPE2      );
+REG64( EX_11_CME_LCL_EITR_SCOM                                 , RULL(0x15012428), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EX_CME_LCL_ICCR_PPE                                     , RULL(0x109010700), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_LCL_ICCR_PPE1                                    , RULL(0x109010718), SH_UNT_EX       ,
+       SH_ACS_PPE1      );
+REG64( EX_CME_LCL_ICCR_PPE2                                    , RULL(0x109010710), SH_UNT_EX       ,
+       SH_ACS_PPE2      );
+REG64( EX_0_CME_LCL_ICCR_PPE                                   , RULL(0x109010700), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_LCL_ICCR_PPE1                                  , RULL(0x109010718), SH_UNT_EX_0     ,
+       SH_ACS_PPE1      );
+REG64( EX_0_CME_LCL_ICCR_PPE2                                  , RULL(0x109010710), SH_UNT_EX_0     ,
+       SH_ACS_PPE2      );
+REG64( EX_1_CME_LCL_ICCR_PPE                                   , RULL(0x109020700), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_LCL_ICCR_PPE1                                  , RULL(0x109020718), SH_UNT_EX_1     ,
+       SH_ACS_PPE1      );
+REG64( EX_1_CME_LCL_ICCR_PPE2                                  , RULL(0x109020710), SH_UNT_EX_1     ,
+       SH_ACS_PPE2      );
+REG64( EX_2_CME_LCL_ICCR_PPE                                   , RULL(0x10A010700), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_LCL_ICCR_PPE1                                  , RULL(0x10A010718), SH_UNT_EX_2     ,
+       SH_ACS_PPE1      );
+REG64( EX_2_CME_LCL_ICCR_PPE2                                  , RULL(0x10A010710), SH_UNT_EX_2     ,
+       SH_ACS_PPE2      );
+REG64( EX_3_CME_LCL_ICCR_PPE                                   , RULL(0x10A020700), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_LCL_ICCR_PPE1                                  , RULL(0x10A020718), SH_UNT_EX_3     ,
+       SH_ACS_PPE1      );
+REG64( EX_3_CME_LCL_ICCR_PPE2                                  , RULL(0x10A020710), SH_UNT_EX_3     ,
+       SH_ACS_PPE2      );
+REG64( EX_4_CME_LCL_ICCR_PPE                                   , RULL(0x10B010700), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_LCL_ICCR_PPE1                                  , RULL(0x10B010718), SH_UNT_EX_4     ,
+       SH_ACS_PPE1      );
+REG64( EX_4_CME_LCL_ICCR_PPE2                                  , RULL(0x10B010710), SH_UNT_EX_4     ,
+       SH_ACS_PPE2      );
+REG64( EX_5_CME_LCL_ICCR_PPE                                   , RULL(0x10B020700), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_LCL_ICCR_PPE1                                  , RULL(0x10B020718), SH_UNT_EX_5     ,
+       SH_ACS_PPE1      );
+REG64( EX_5_CME_LCL_ICCR_PPE2                                  , RULL(0x10B020710), SH_UNT_EX_5     ,
+       SH_ACS_PPE2      );
+REG64( EX_6_CME_LCL_ICCR_PPE                                   , RULL(0x10C010700), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_LCL_ICCR_PPE1                                  , RULL(0x10C010718), SH_UNT_EX_6     ,
+       SH_ACS_PPE1      );
+REG64( EX_6_CME_LCL_ICCR_PPE2                                  , RULL(0x10C010710), SH_UNT_EX_6     ,
+       SH_ACS_PPE2      );
+REG64( EX_7_CME_LCL_ICCR_PPE                                   , RULL(0x10C020700), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_LCL_ICCR_PPE1                                  , RULL(0x10C020718), SH_UNT_EX_7     ,
+       SH_ACS_PPE1      );
+REG64( EX_7_CME_LCL_ICCR_PPE2                                  , RULL(0x10C020710), SH_UNT_EX_7     ,
+       SH_ACS_PPE2      );
+REG64( EX_8_CME_LCL_ICCR_PPE                                   , RULL(0x10D010700), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_LCL_ICCR_PPE1                                  , RULL(0x10D010718), SH_UNT_EX_8     ,
+       SH_ACS_PPE1      );
+REG64( EX_8_CME_LCL_ICCR_PPE2                                  , RULL(0x10D010710), SH_UNT_EX_8     ,
+       SH_ACS_PPE2      );
+REG64( EX_9_CME_LCL_ICCR_PPE                                   , RULL(0x10D020700), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_LCL_ICCR_PPE1                                  , RULL(0x10D020718), SH_UNT_EX_9     ,
+       SH_ACS_PPE1      );
+REG64( EX_9_CME_LCL_ICCR_PPE2                                  , RULL(0x10D020710), SH_UNT_EX_9     ,
+       SH_ACS_PPE2      );
+REG64( EX_10_CME_LCL_ICCR_PPE                                  , RULL(0x10E010700), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_LCL_ICCR_PPE1                                 , RULL(0x10E010718), SH_UNT_EX_10    ,
+       SH_ACS_PPE1      );
+REG64( EX_10_CME_LCL_ICCR_PPE2                                 , RULL(0x10E010710), SH_UNT_EX_10    ,
+       SH_ACS_PPE2      );
+REG64( EX_11_CME_LCL_ICCR_PPE                                  , RULL(0x10E020700), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_LCL_ICCR_PPE1                                 , RULL(0x10E020718), SH_UNT_EX_11    ,
+       SH_ACS_PPE1      );
+REG64( EX_11_CME_LCL_ICCR_PPE2                                 , RULL(0x10E020710), SH_UNT_EX_11    ,
+       SH_ACS_PPE2      );
+
+REG64( EQ_CME_LCL_ICRR                                         , RULL(0x1001244D), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001204D,
+REG64( EQ_0_CME_LCL_ICRR                                       , RULL(0x1001244D), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001204D,
+REG64( EQ_1_CME_LCL_ICRR                                       , RULL(0x1101244D), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1101204D,
+REG64( EQ_2_CME_LCL_ICRR                                       , RULL(0x1201244D), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1201204D,
+REG64( EQ_3_CME_LCL_ICRR                                       , RULL(0x1301244D), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1301204D,
+REG64( EQ_4_CME_LCL_ICRR                                       , RULL(0x1401244D), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1401204D,
+REG64( EQ_5_CME_LCL_ICRR                                       , RULL(0x1501244D), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1501204D,
+REG64( EX_CME_LCL_ICRR_PPE                                     , RULL(0x109010740), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_LCL_ICRR_SCOM                                    , RULL(0x1001204D), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_LCL_ICRR_PPE                                   , RULL(0x109010740), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_LCL_ICRR_SCOM                                  , RULL(0x1001204D), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_LCL_ICRR_PPE                                   , RULL(0x109020740), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_LCL_ICRR_SCOM                                  , RULL(0x1001244D), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_LCL_ICRR_PPE                                   , RULL(0x10A010740), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_LCL_ICRR_SCOM                                  , RULL(0x1101204D), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_LCL_ICRR_PPE                                   , RULL(0x10A020740), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_LCL_ICRR_SCOM                                  , RULL(0x1101244D), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_LCL_ICRR_PPE                                   , RULL(0x10B010740), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_LCL_ICRR_SCOM                                  , RULL(0x1201204D), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_LCL_ICRR_PPE                                   , RULL(0x10B020740), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_LCL_ICRR_SCOM                                  , RULL(0x1201244D), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_LCL_ICRR_PPE                                   , RULL(0x10C010740), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_LCL_ICRR_SCOM                                  , RULL(0x1301204D), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_LCL_ICRR_PPE                                   , RULL(0x10C020740), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_LCL_ICRR_SCOM                                  , RULL(0x1301244D), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_LCL_ICRR_PPE                                   , RULL(0x10D010740), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_LCL_ICRR_SCOM                                  , RULL(0x1401204D), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_LCL_ICRR_PPE                                   , RULL(0x10D020740), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_LCL_ICRR_SCOM                                  , RULL(0x1401244D), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_LCL_ICRR_PPE                                  , RULL(0x10E010740), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_LCL_ICRR_SCOM                                 , RULL(0x1501204D), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_LCL_ICRR_PPE                                  , RULL(0x10E020740), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_LCL_ICRR_SCOM                                 , RULL(0x1501244D), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EX_CME_LCL_ICSR_PPE                                     , RULL(0x109010720), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_LCL_ICSR_PPE                                   , RULL(0x109010720), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_LCL_ICSR_PPE                                   , RULL(0x109020720), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_LCL_ICSR_PPE                                   , RULL(0x10A010720), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_LCL_ICSR_PPE                                   , RULL(0x10A020720), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_LCL_ICSR_PPE                                   , RULL(0x10B010720), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_LCL_ICSR_PPE                                   , RULL(0x10B020720), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_LCL_ICSR_PPE                                   , RULL(0x10C010720), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_LCL_ICSR_PPE                                   , RULL(0x10C020720), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_LCL_ICSR_PPE                                   , RULL(0x10D010720), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_LCL_ICSR_PPE                                   , RULL(0x10D020720), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_LCL_ICSR_PPE                                  , RULL(0x10E010720), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_LCL_ICSR_PPE                                  , RULL(0x10E020720), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+
+REG64( EX_CME_LCL_LMCR_PPE                                     , RULL(0x1090101A0), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_LCL_LMCR_PPE                                   , RULL(0x1090101A0), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_LCL_LMCR_PPE                                   , RULL(0x1090201A0), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_LCL_LMCR_PPE                                   , RULL(0x10A0101A0), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_LCL_LMCR_PPE                                   , RULL(0x10A0201A0), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_LCL_LMCR_PPE                                   , RULL(0x10B0101A0), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_LCL_LMCR_PPE                                   , RULL(0x10B0201A0), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_LCL_LMCR_PPE                                   , RULL(0x10C0101A0), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_LCL_LMCR_PPE                                   , RULL(0x10C0201A0), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_LCL_LMCR_PPE                                   , RULL(0x10D0101A0), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_LCL_LMCR_PPE                                   , RULL(0x10D0201A0), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_LCL_LMCR_PPE                                  , RULL(0x10E0101A0), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_LCL_LMCR_PPE                                  , RULL(0x10E0201A0), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+
+REG64( EX_CME_LCL_PECESR0_PPE                                  , RULL(0x109010280), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_LCL_PECESR0_PPE                                , RULL(0x109010280), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_LCL_PECESR0_PPE                                , RULL(0x109020280), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_LCL_PECESR0_PPE                                , RULL(0x10A010280), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_LCL_PECESR0_PPE                                , RULL(0x10A020280), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_LCL_PECESR0_PPE                                , RULL(0x10B010280), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_LCL_PECESR0_PPE                                , RULL(0x10B020280), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_LCL_PECESR0_PPE                                , RULL(0x10C010280), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_LCL_PECESR0_PPE                                , RULL(0x10C020280), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_LCL_PECESR0_PPE                                , RULL(0x10D010280), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_LCL_PECESR0_PPE                                , RULL(0x10D020280), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_LCL_PECESR0_PPE                               , RULL(0x10E010280), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_LCL_PECESR0_PPE                               , RULL(0x10E020280), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+
+REG64( EX_CME_LCL_PECESR1_PPE                                  , RULL(0x1090102A0), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_LCL_PECESR1_PPE                                , RULL(0x1090102A0), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_LCL_PECESR1_PPE                                , RULL(0x1090202A0), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_LCL_PECESR1_PPE                                , RULL(0x10A0102A0), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_LCL_PECESR1_PPE                                , RULL(0x10A0202A0), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_LCL_PECESR1_PPE                                , RULL(0x10B0102A0), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_LCL_PECESR1_PPE                                , RULL(0x10B0202A0), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_LCL_PECESR1_PPE                                , RULL(0x10C0102A0), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_LCL_PECESR1_PPE                                , RULL(0x10C0202A0), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_LCL_PECESR1_PPE                                , RULL(0x10D0102A0), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_LCL_PECESR1_PPE                                , RULL(0x10D0202A0), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_LCL_PECESR1_PPE                               , RULL(0x10E0102A0), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_LCL_PECESR1_PPE                               , RULL(0x10E0202A0), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+
+REG64( EQ_CME_LCL_SISR                                         , RULL(0x1001244C), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001204C,
+REG64( EQ_0_CME_LCL_SISR                                       , RULL(0x1001244C), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001204C,
+REG64( EQ_1_CME_LCL_SISR                                       , RULL(0x1101244C), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1101204C,
+REG64( EQ_2_CME_LCL_SISR                                       , RULL(0x1201244C), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1201204C,
+REG64( EQ_3_CME_LCL_SISR                                       , RULL(0x1301244C), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1301204C,
+REG64( EQ_4_CME_LCL_SISR                                       , RULL(0x1401244C), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1401204C,
+REG64( EQ_5_CME_LCL_SISR                                       , RULL(0x1501244C), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1501204C,
+REG64( EX_CME_LCL_SISR_PPE                                     , RULL(0x109010520), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_LCL_SISR_SCOM                                    , RULL(0x1001204C), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_LCL_SISR_PPE                                   , RULL(0x109010520), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_LCL_SISR_SCOM                                  , RULL(0x1001204C), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_LCL_SISR_PPE                                   , RULL(0x109020520), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_LCL_SISR_SCOM                                  , RULL(0x1001244C), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_LCL_SISR_PPE                                   , RULL(0x10A010520), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_LCL_SISR_SCOM                                  , RULL(0x1101204C), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_LCL_SISR_PPE                                   , RULL(0x10A020520), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_LCL_SISR_SCOM                                  , RULL(0x1101244C), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_LCL_SISR_PPE                                   , RULL(0x10B010520), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_LCL_SISR_SCOM                                  , RULL(0x1201204C), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_LCL_SISR_PPE                                   , RULL(0x10B020520), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_LCL_SISR_SCOM                                  , RULL(0x1201244C), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_LCL_SISR_PPE                                   , RULL(0x10C010520), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_LCL_SISR_SCOM                                  , RULL(0x1301204C), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_LCL_SISR_PPE                                   , RULL(0x10C020520), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_LCL_SISR_SCOM                                  , RULL(0x1301244C), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_LCL_SISR_PPE                                   , RULL(0x10D010520), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_LCL_SISR_SCOM                                  , RULL(0x1401204C), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_LCL_SISR_PPE                                   , RULL(0x10D020520), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_LCL_SISR_SCOM                                  , RULL(0x1401244C), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_LCL_SISR_PPE                                  , RULL(0x10E010520), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_LCL_SISR_SCOM                                 , RULL(0x1501204C), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_LCL_SISR_PPE                                  , RULL(0x10E020520), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_LCL_SISR_SCOM                                 , RULL(0x1501244C), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EX_CME_LCL_TSEL_PPE                                     , RULL(0x109010100), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_LCL_TSEL_PPE                                   , RULL(0x109010100), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_LCL_TSEL_PPE                                   , RULL(0x109020100), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_LCL_TSEL_PPE                                   , RULL(0x10A010100), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_LCL_TSEL_PPE                                   , RULL(0x10A020100), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_LCL_TSEL_PPE                                   , RULL(0x10B010100), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_LCL_TSEL_PPE                                   , RULL(0x10B020100), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_LCL_TSEL_PPE                                   , RULL(0x10C010100), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_LCL_TSEL_PPE                                   , RULL(0x10C020100), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_LCL_TSEL_PPE                                   , RULL(0x10D010100), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_LCL_TSEL_PPE                                   , RULL(0x10D020100), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_LCL_TSEL_PPE                                  , RULL(0x10E010100), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_LCL_TSEL_PPE                                  , RULL(0x10E020100), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+
+REG64( EQ_CME_SCOM_AFSR                                        , RULL(0x10012433), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10012033,
+REG64( EQ_0_CME_SCOM_AFSR                                      , RULL(0x10012433), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10012033,
+REG64( EQ_1_CME_SCOM_AFSR                                      , RULL(0x11012433), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11012033,
+REG64( EQ_2_CME_SCOM_AFSR                                      , RULL(0x12012433), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12012033,
+REG64( EQ_3_CME_SCOM_AFSR                                      , RULL(0x13012433), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13012033,
+REG64( EQ_4_CME_SCOM_AFSR                                      , RULL(0x14012433), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14012033,
+REG64( EQ_5_CME_SCOM_AFSR                                      , RULL(0x15012433), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15012033,
+REG64( EX_CME_SCOM_AFSR_PPE                                    , RULL(0x109010160), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_AFSR_SCOM                                   , RULL(0x10012033), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_CME_SCOM_AFSR_PPE                                  , RULL(0x109010160), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_AFSR_SCOM                                 , RULL(0x10012033), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_CME_SCOM_AFSR_PPE                                  , RULL(0x109020160), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_AFSR_SCOM                                 , RULL(0x10012433), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_CME_SCOM_AFSR_PPE                                  , RULL(0x10A010160), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_AFSR_SCOM                                 , RULL(0x11012033), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_CME_SCOM_AFSR_PPE                                  , RULL(0x10A020160), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_AFSR_SCOM                                 , RULL(0x11012433), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_CME_SCOM_AFSR_PPE                                  , RULL(0x10B010160), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_AFSR_SCOM                                 , RULL(0x12012033), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_CME_SCOM_AFSR_PPE                                  , RULL(0x10B020160), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_AFSR_SCOM                                 , RULL(0x12012433), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_CME_SCOM_AFSR_PPE                                  , RULL(0x10C010160), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_AFSR_SCOM                                 , RULL(0x13012033), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_CME_SCOM_AFSR_PPE                                  , RULL(0x10C020160), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_AFSR_SCOM                                 , RULL(0x13012433), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_CME_SCOM_AFSR_PPE                                  , RULL(0x10D010160), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_AFSR_SCOM                                 , RULL(0x14012033), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_CME_SCOM_AFSR_PPE                                  , RULL(0x10D020160), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_AFSR_SCOM                                 , RULL(0x14012433), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_CME_SCOM_AFSR_PPE                                 , RULL(0x10E010160), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_AFSR_SCOM                                , RULL(0x15012033), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_CME_SCOM_AFSR_PPE                                 , RULL(0x10E020160), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_AFSR_SCOM                                , RULL(0x15012433), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_CME_SCOM_AFTR                                        , RULL(0x10012434), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012034,
+REG64( EQ_0_CME_SCOM_AFTR                                      , RULL(0x10012434), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012034,
+REG64( EQ_1_CME_SCOM_AFTR                                      , RULL(0x11012434), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012034,
+REG64( EQ_2_CME_SCOM_AFTR                                      , RULL(0x12012434), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012034,
+REG64( EQ_3_CME_SCOM_AFTR                                      , RULL(0x13012434), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012034,
+REG64( EQ_4_CME_SCOM_AFTR                                      , RULL(0x14012434), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012034,
+REG64( EQ_5_CME_SCOM_AFTR                                      , RULL(0x15012434), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012034,
+REG64( EX_CME_SCOM_AFTR_PPE                                    , RULL(0x109010180), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_AFTR_SCOM                                   , RULL(0x10012034), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_SCOM_AFTR_PPE                                  , RULL(0x109010180), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_AFTR_SCOM                                 , RULL(0x10012034), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_SCOM_AFTR_PPE                                  , RULL(0x109020180), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_AFTR_SCOM                                 , RULL(0x10012434), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_SCOM_AFTR_PPE                                  , RULL(0x10A010180), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_AFTR_SCOM                                 , RULL(0x11012034), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_SCOM_AFTR_PPE                                  , RULL(0x10A020180), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_AFTR_SCOM                                 , RULL(0x11012434), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_SCOM_AFTR_PPE                                  , RULL(0x10B010180), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_AFTR_SCOM                                 , RULL(0x12012034), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_SCOM_AFTR_PPE                                  , RULL(0x10B020180), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_AFTR_SCOM                                 , RULL(0x12012434), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_SCOM_AFTR_PPE                                  , RULL(0x10C010180), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_AFTR_SCOM                                 , RULL(0x13012034), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_SCOM_AFTR_PPE                                  , RULL(0x10C020180), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_AFTR_SCOM                                 , RULL(0x13012434), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_SCOM_AFTR_PPE                                  , RULL(0x10D010180), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_AFTR_SCOM                                 , RULL(0x14012034), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_SCOM_AFTR_PPE                                  , RULL(0x10D020180), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_AFTR_SCOM                                 , RULL(0x14012434), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_SCOM_AFTR_PPE                                 , RULL(0x10E010180), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_AFTR_SCOM                                , RULL(0x15012034), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_SCOM_AFTR_PPE                                 , RULL(0x10E020180), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_AFTR_SCOM                                , RULL(0x15012434), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_SCOM_BCEBAR0                                     , RULL(0x10012430), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012030,
+REG64( EQ_0_CME_SCOM_BCEBAR0                                   , RULL(0x10012430), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012030,
+REG64( EQ_1_CME_SCOM_BCEBAR0                                   , RULL(0x11012430), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012030,
+REG64( EQ_2_CME_SCOM_BCEBAR0                                   , RULL(0x12012430), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012030,
+REG64( EQ_3_CME_SCOM_BCEBAR0                                   , RULL(0x13012430), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012030,
+REG64( EQ_4_CME_SCOM_BCEBAR0                                   , RULL(0x14012430), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012030,
+REG64( EQ_5_CME_SCOM_BCEBAR0                                   , RULL(0x15012430), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012030,
+REG64( EX_CME_SCOM_BCEBAR0                                     , RULL(0x10012030), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_BCEBAR0                                   , RULL(0x10012030), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_BCEBAR0                                   , RULL(0x10012430), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_BCEBAR0                                   , RULL(0x11012030), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_BCEBAR0                                   , RULL(0x11012430), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_BCEBAR0                                   , RULL(0x12012030), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_BCEBAR0                                   , RULL(0x12012430), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_BCEBAR0                                   , RULL(0x13012030), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_BCEBAR0                                   , RULL(0x13012430), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_BCEBAR0                                   , RULL(0x14012030), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_BCEBAR0                                   , RULL(0x14012430), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_BCEBAR0                                  , RULL(0x15012030), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_BCEBAR0                                  , RULL(0x15012430), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_BCEBAR1                                     , RULL(0x10012431), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012031,
+REG64( EQ_0_CME_SCOM_BCEBAR1                                   , RULL(0x10012431), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012031,
+REG64( EQ_1_CME_SCOM_BCEBAR1                                   , RULL(0x11012431), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012031,
+REG64( EQ_2_CME_SCOM_BCEBAR1                                   , RULL(0x12012431), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012031,
+REG64( EQ_3_CME_SCOM_BCEBAR1                                   , RULL(0x13012431), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012031,
+REG64( EQ_4_CME_SCOM_BCEBAR1                                   , RULL(0x14012431), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012031,
+REG64( EQ_5_CME_SCOM_BCEBAR1                                   , RULL(0x15012431), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012031,
+REG64( EX_CME_SCOM_BCEBAR1                                     , RULL(0x10012031), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_BCEBAR1                                   , RULL(0x10012031), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_BCEBAR1                                   , RULL(0x10012431), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_BCEBAR1                                   , RULL(0x11012031), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_BCEBAR1                                   , RULL(0x11012431), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_BCEBAR1                                   , RULL(0x12012031), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_BCEBAR1                                   , RULL(0x12012431), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_BCEBAR1                                   , RULL(0x13012031), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_BCEBAR1                                   , RULL(0x13012431), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_BCEBAR1                                   , RULL(0x14012031), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_BCEBAR1                                   , RULL(0x14012431), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_BCEBAR1                                  , RULL(0x15012031), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_BCEBAR1                                  , RULL(0x15012431), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_BCECSR                                      , RULL(0x1001240F), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 1001200F,
+REG64( EQ_0_CME_SCOM_BCECSR                                    , RULL(0x1001240F), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 1001200F,
+REG64( EQ_1_CME_SCOM_BCECSR                                    , RULL(0x1101240F), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 1101200F,
+REG64( EQ_2_CME_SCOM_BCECSR                                    , RULL(0x1201240F), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 1201200F,
+REG64( EQ_3_CME_SCOM_BCECSR                                    , RULL(0x1301240F), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 1301200F,
+REG64( EQ_4_CME_SCOM_BCECSR                                    , RULL(0x1401240F), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 1401200F,
+REG64( EQ_5_CME_SCOM_BCECSR                                    , RULL(0x1501240F), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 1501200F,
+REG64( EX_CME_SCOM_BCECSR_PPE                                  , RULL(0x1090101E0), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_BCECSR_SCOM                                 , RULL(0x1001200F), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_CME_SCOM_BCECSR_PPE                                , RULL(0x1090101E0), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_BCECSR_SCOM                               , RULL(0x1001200F), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_CME_SCOM_BCECSR_PPE                                , RULL(0x1090201E0), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_BCECSR_SCOM                               , RULL(0x1001240F), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_CME_SCOM_BCECSR_PPE                                , RULL(0x10A0101E0), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_BCECSR_SCOM                               , RULL(0x1101200F), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_CME_SCOM_BCECSR_PPE                                , RULL(0x10A0201E0), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_BCECSR_SCOM                               , RULL(0x1101240F), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_CME_SCOM_BCECSR_PPE                                , RULL(0x10B0101E0), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_BCECSR_SCOM                               , RULL(0x1201200F), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_CME_SCOM_BCECSR_PPE                                , RULL(0x10B0201E0), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_BCECSR_SCOM                               , RULL(0x1201240F), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_CME_SCOM_BCECSR_PPE                                , RULL(0x10C0101E0), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_BCECSR_SCOM                               , RULL(0x1301200F), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_CME_SCOM_BCECSR_PPE                                , RULL(0x10C0201E0), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_BCECSR_SCOM                               , RULL(0x1301240F), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_CME_SCOM_BCECSR_PPE                                , RULL(0x10D0101E0), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_BCECSR_SCOM                               , RULL(0x1401200F), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_CME_SCOM_BCECSR_PPE                                , RULL(0x10D0201E0), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_BCECSR_SCOM                               , RULL(0x1401240F), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_CME_SCOM_BCECSR_PPE                               , RULL(0x10E0101E0), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_BCECSR_SCOM                              , RULL(0x1501200F), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_CME_SCOM_BCECSR_PPE                               , RULL(0x10E0201E0), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_BCECSR_SCOM                              , RULL(0x1501240F), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_CME_SCOM_CIDSR                                       , RULL(0x1001242E), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001202E,
+REG64( EQ_0_CME_SCOM_CIDSR                                     , RULL(0x1001242E), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001202E,
+REG64( EQ_1_CME_SCOM_CIDSR                                     , RULL(0x1101242E), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1101202E,
+REG64( EQ_2_CME_SCOM_CIDSR                                     , RULL(0x1201242E), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1201202E,
+REG64( EQ_3_CME_SCOM_CIDSR                                     , RULL(0x1301242E), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1301202E,
+REG64( EQ_4_CME_SCOM_CIDSR                                     , RULL(0x1401242E), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1401202E,
+REG64( EQ_5_CME_SCOM_CIDSR                                     , RULL(0x1501242E), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1501202E,
+REG64( EX_CME_SCOM_CIDSR_PPE                                   , RULL(0x1090106C0), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_CIDSR_SCOM                                  , RULL(0x1001202E), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_SCOM_CIDSR_PPE                                 , RULL(0x1090106C0), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_CIDSR_SCOM                                , RULL(0x1001202E), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_SCOM_CIDSR_PPE                                 , RULL(0x1090206C0), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_CIDSR_SCOM                                , RULL(0x1001242E), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_SCOM_CIDSR_PPE                                 , RULL(0x10A0106C0), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_CIDSR_SCOM                                , RULL(0x1101202E), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_SCOM_CIDSR_PPE                                 , RULL(0x10A0206C0), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_CIDSR_SCOM                                , RULL(0x1101242E), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_SCOM_CIDSR_PPE                                 , RULL(0x10B0106C0), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_CIDSR_SCOM                                , RULL(0x1201202E), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_SCOM_CIDSR_PPE                                 , RULL(0x10B0206C0), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_CIDSR_SCOM                                , RULL(0x1201242E), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_SCOM_CIDSR_PPE                                 , RULL(0x10C0106C0), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_CIDSR_SCOM                                , RULL(0x1301202E), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_SCOM_CIDSR_PPE                                 , RULL(0x10C0206C0), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_CIDSR_SCOM                                , RULL(0x1301242E), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_SCOM_CIDSR_PPE                                 , RULL(0x10D0106C0), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_CIDSR_SCOM                                , RULL(0x1401202E), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_SCOM_CIDSR_PPE                                 , RULL(0x10D0206C0), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_CIDSR_SCOM                                , RULL(0x1401242E), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_SCOM_CIDSR_PPE                                , RULL(0x10E0106C0), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_CIDSR_SCOM                               , RULL(0x1501202E), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_SCOM_CIDSR_PPE                                , RULL(0x10E0206C0), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_CIDSR_SCOM                               , RULL(0x1501242E), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_SCOM_EIIR                                        , RULL(0x1001242B), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 1001202B,
+REG64( EQ_0_CME_SCOM_EIIR                                      , RULL(0x1001242B), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 1001202B,
+REG64( EQ_1_CME_SCOM_EIIR                                      , RULL(0x1101242B), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 1101202B,
+REG64( EQ_2_CME_SCOM_EIIR                                      , RULL(0x1201242B), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 1201202B,
+REG64( EQ_3_CME_SCOM_EIIR                                      , RULL(0x1301242B), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 1301202B,
+REG64( EQ_4_CME_SCOM_EIIR                                      , RULL(0x1401242B), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 1401202B,
+REG64( EQ_5_CME_SCOM_EIIR                                      , RULL(0x1501242B), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 1501202B,
+REG64( EX_CME_SCOM_EIIR                                        , RULL(0x1001202B), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_CME_SCOM_EIIR                                      , RULL(0x1001202B), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_CME_SCOM_EIIR                                      , RULL(0x1001242B), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_CME_SCOM_EIIR                                      , RULL(0x1101202B), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_CME_SCOM_EIIR                                      , RULL(0x1101242B), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_CME_SCOM_EIIR                                      , RULL(0x1201202B), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_CME_SCOM_EIIR                                      , RULL(0x1201242B), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_CME_SCOM_EIIR                                      , RULL(0x1301202B), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_CME_SCOM_EIIR                                      , RULL(0x1301242B), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_CME_SCOM_EIIR                                      , RULL(0x1401202B), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_CME_SCOM_EIIR                                      , RULL(0x1401242B), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_CME_SCOM_EIIR                                     , RULL(0x1501202B), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_CME_SCOM_EIIR                                     , RULL(0x1501242B), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_CME_SCOM_FLAGS                                       , RULL(0x10012420), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012020,
+REG64( EQ_CME_SCOM_FLAGS_CLEAR                                 , RULL(0x10012421), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 10012021,
+REG64( EQ_CME_SCOM_FLAGS_OR                                    , RULL(0x10012422), SH_UNT_EQ       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 10012022,
+REG64( EQ_0_CME_SCOM_FLAGS                                     , RULL(0x10012420), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012020,
+REG64( EQ_0_CME_SCOM_FLAGS_CLEAR                               , RULL(0x10012421), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 10012021,
+REG64( EQ_0_CME_SCOM_FLAGS_OR                                  , RULL(0x10012422), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 10012022,
+REG64( EQ_1_CME_SCOM_FLAGS                                     , RULL(0x11012420), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012020,
+REG64( EQ_1_CME_SCOM_FLAGS_CLEAR                               , RULL(0x11012421), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 11012021,
+REG64( EQ_1_CME_SCOM_FLAGS_OR                                  , RULL(0x11012422), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 11012022,
+REG64( EQ_2_CME_SCOM_FLAGS                                     , RULL(0x12012420), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012020,
+REG64( EQ_2_CME_SCOM_FLAGS_CLEAR                               , RULL(0x12012421), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 12012021,
+REG64( EQ_2_CME_SCOM_FLAGS_OR                                  , RULL(0x12012422), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 12012022,
+REG64( EQ_3_CME_SCOM_FLAGS                                     , RULL(0x13012420), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012020,
+REG64( EQ_3_CME_SCOM_FLAGS_CLEAR                               , RULL(0x13012421), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 13012021,
+REG64( EQ_3_CME_SCOM_FLAGS_OR                                  , RULL(0x13012422), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 13012022,
+REG64( EQ_4_CME_SCOM_FLAGS                                     , RULL(0x14012420), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012020,
+REG64( EQ_4_CME_SCOM_FLAGS_CLEAR                               , RULL(0x14012421), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 14012021,
+REG64( EQ_4_CME_SCOM_FLAGS_OR                                  , RULL(0x14012422), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 14012022,
+REG64( EQ_5_CME_SCOM_FLAGS                                     , RULL(0x15012420), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012020,
+REG64( EQ_5_CME_SCOM_FLAGS_CLEAR                               , RULL(0x15012421), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 15012021,
+REG64( EQ_5_CME_SCOM_FLAGS_OR                                  , RULL(0x15012422), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 15012022,
+REG64( EX_CME_SCOM_FLAGS_PPE                                   , RULL(0x109010400), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_FLAGS_PPE1                                  , RULL(0x109010418), SH_UNT_EX       ,
+       SH_ACS_PPE1      );
+REG64( EX_CME_SCOM_FLAGS_PPE2                                  , RULL(0x109010410), SH_UNT_EX       ,
+       SH_ACS_PPE2      );
+REG64( EX_CME_SCOM_FLAGS_SCOM                                  , RULL(0x10012020), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_CME_SCOM_FLAGS_SCOM1                                 , RULL(0x10012021), SH_UNT_EX       ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_CME_SCOM_FLAGS_SCOM2                                 , RULL(0x10012022), SH_UNT_EX       , SH_ACS_SCOM2_OR  );
+REG64( EX_0_CME_SCOM_FLAGS_PPE                                 , RULL(0x109010400), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_FLAGS_PPE1                                , RULL(0x109010418), SH_UNT_EX_0     ,
+       SH_ACS_PPE1      );
+REG64( EX_0_CME_SCOM_FLAGS_PPE2                                , RULL(0x109010410), SH_UNT_EX_0     ,
+       SH_ACS_PPE2      );
+REG64( EX_0_CME_SCOM_FLAGS_SCOM                                , RULL(0x10012020), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_FLAGS_SCOM1                               , RULL(0x10012021), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_0_CME_SCOM_FLAGS_SCOM2                               , RULL(0x10012022), SH_UNT_EX_0     , SH_ACS_SCOM2_OR  );
+REG64( EX_1_CME_SCOM_FLAGS_PPE                                 , RULL(0x109020400), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_FLAGS_PPE1                                , RULL(0x109020418), SH_UNT_EX_1     ,
+       SH_ACS_PPE1      );
+REG64( EX_1_CME_SCOM_FLAGS_PPE2                                , RULL(0x109020410), SH_UNT_EX_1     ,
+       SH_ACS_PPE2      );
+REG64( EX_1_CME_SCOM_FLAGS_SCOM                                , RULL(0x10012420), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_FLAGS_SCOM1                               , RULL(0x10012421), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_1_CME_SCOM_FLAGS_SCOM2                               , RULL(0x10012422), SH_UNT_EX_1     , SH_ACS_SCOM2_OR  );
+REG64( EX_2_CME_SCOM_FLAGS_PPE                                 , RULL(0x10A010400), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_FLAGS_PPE1                                , RULL(0x10A010418), SH_UNT_EX_2     ,
+       SH_ACS_PPE1      );
+REG64( EX_2_CME_SCOM_FLAGS_PPE2                                , RULL(0x10A010410), SH_UNT_EX_2     ,
+       SH_ACS_PPE2      );
+REG64( EX_2_CME_SCOM_FLAGS_SCOM                                , RULL(0x11012020), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_FLAGS_SCOM1                               , RULL(0x11012021), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_2_CME_SCOM_FLAGS_SCOM2                               , RULL(0x11012022), SH_UNT_EX_2     , SH_ACS_SCOM2_OR  );
+REG64( EX_3_CME_SCOM_FLAGS_PPE                                 , RULL(0x10A020400), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_FLAGS_PPE1                                , RULL(0x10A020418), SH_UNT_EX_3     ,
+       SH_ACS_PPE1      );
+REG64( EX_3_CME_SCOM_FLAGS_PPE2                                , RULL(0x10A020410), SH_UNT_EX_3     ,
+       SH_ACS_PPE2      );
+REG64( EX_3_CME_SCOM_FLAGS_SCOM                                , RULL(0x11012420), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_FLAGS_SCOM1                               , RULL(0x11012421), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_3_CME_SCOM_FLAGS_SCOM2                               , RULL(0x11012422), SH_UNT_EX_3     , SH_ACS_SCOM2_OR  );
+REG64( EX_4_CME_SCOM_FLAGS_PPE                                 , RULL(0x10B010400), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_FLAGS_PPE1                                , RULL(0x10B010418), SH_UNT_EX_4     ,
+       SH_ACS_PPE1      );
+REG64( EX_4_CME_SCOM_FLAGS_PPE2                                , RULL(0x10B010410), SH_UNT_EX_4     ,
+       SH_ACS_PPE2      );
+REG64( EX_4_CME_SCOM_FLAGS_SCOM                                , RULL(0x12012020), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_FLAGS_SCOM1                               , RULL(0x12012021), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_4_CME_SCOM_FLAGS_SCOM2                               , RULL(0x12012022), SH_UNT_EX_4     , SH_ACS_SCOM2_OR  );
+REG64( EX_5_CME_SCOM_FLAGS_PPE                                 , RULL(0x10B020400), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_FLAGS_PPE1                                , RULL(0x10B020418), SH_UNT_EX_5     ,
+       SH_ACS_PPE1      );
+REG64( EX_5_CME_SCOM_FLAGS_PPE2                                , RULL(0x10B020410), SH_UNT_EX_5     ,
+       SH_ACS_PPE2      );
+REG64( EX_5_CME_SCOM_FLAGS_SCOM                                , RULL(0x12012420), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_FLAGS_SCOM1                               , RULL(0x12012421), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_5_CME_SCOM_FLAGS_SCOM2                               , RULL(0x12012422), SH_UNT_EX_5     , SH_ACS_SCOM2_OR  );
+REG64( EX_6_CME_SCOM_FLAGS_PPE                                 , RULL(0x10C010400), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_FLAGS_PPE1                                , RULL(0x10C010418), SH_UNT_EX_6     ,
+       SH_ACS_PPE1      );
+REG64( EX_6_CME_SCOM_FLAGS_PPE2                                , RULL(0x10C010410), SH_UNT_EX_6     ,
+       SH_ACS_PPE2      );
+REG64( EX_6_CME_SCOM_FLAGS_SCOM                                , RULL(0x13012020), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_FLAGS_SCOM1                               , RULL(0x13012021), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_6_CME_SCOM_FLAGS_SCOM2                               , RULL(0x13012022), SH_UNT_EX_6     , SH_ACS_SCOM2_OR  );
+REG64( EX_7_CME_SCOM_FLAGS_PPE                                 , RULL(0x10C020400), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_FLAGS_PPE1                                , RULL(0x10C020418), SH_UNT_EX_7     ,
+       SH_ACS_PPE1      );
+REG64( EX_7_CME_SCOM_FLAGS_PPE2                                , RULL(0x10C020410), SH_UNT_EX_7     ,
+       SH_ACS_PPE2      );
+REG64( EX_7_CME_SCOM_FLAGS_SCOM                                , RULL(0x13012420), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_FLAGS_SCOM1                               , RULL(0x13012421), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_7_CME_SCOM_FLAGS_SCOM2                               , RULL(0x13012422), SH_UNT_EX_7     , SH_ACS_SCOM2_OR  );
+REG64( EX_8_CME_SCOM_FLAGS_PPE                                 , RULL(0x10D010400), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_FLAGS_PPE1                                , RULL(0x10D010418), SH_UNT_EX_8     ,
+       SH_ACS_PPE1      );
+REG64( EX_8_CME_SCOM_FLAGS_PPE2                                , RULL(0x10D010410), SH_UNT_EX_8     ,
+       SH_ACS_PPE2      );
+REG64( EX_8_CME_SCOM_FLAGS_SCOM                                , RULL(0x14012020), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_FLAGS_SCOM1                               , RULL(0x14012021), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_8_CME_SCOM_FLAGS_SCOM2                               , RULL(0x14012022), SH_UNT_EX_8     , SH_ACS_SCOM2_OR  );
+REG64( EX_9_CME_SCOM_FLAGS_PPE                                 , RULL(0x10D020400), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_FLAGS_PPE1                                , RULL(0x10D020418), SH_UNT_EX_9     ,
+       SH_ACS_PPE1      );
+REG64( EX_9_CME_SCOM_FLAGS_PPE2                                , RULL(0x10D020410), SH_UNT_EX_9     ,
+       SH_ACS_PPE2      );
+REG64( EX_9_CME_SCOM_FLAGS_SCOM                                , RULL(0x14012420), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_FLAGS_SCOM1                               , RULL(0x14012421), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_9_CME_SCOM_FLAGS_SCOM2                               , RULL(0x14012422), SH_UNT_EX_9     , SH_ACS_SCOM2_OR  );
+REG64( EX_10_CME_SCOM_FLAGS_PPE                                , RULL(0x10E010400), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_FLAGS_PPE1                               , RULL(0x10E010418), SH_UNT_EX_10    ,
+       SH_ACS_PPE1      );
+REG64( EX_10_CME_SCOM_FLAGS_PPE2                               , RULL(0x10E010410), SH_UNT_EX_10    ,
+       SH_ACS_PPE2      );
+REG64( EX_10_CME_SCOM_FLAGS_SCOM                               , RULL(0x15012020), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_FLAGS_SCOM1                              , RULL(0x15012021), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_10_CME_SCOM_FLAGS_SCOM2                              , RULL(0x15012022), SH_UNT_EX_10    , SH_ACS_SCOM2_OR  );
+REG64( EX_11_CME_SCOM_FLAGS_PPE                                , RULL(0x10E020400), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_FLAGS_PPE1                               , RULL(0x10E020418), SH_UNT_EX_11    ,
+       SH_ACS_PPE1      );
+REG64( EX_11_CME_SCOM_FLAGS_PPE2                               , RULL(0x10E020410), SH_UNT_EX_11    ,
+       SH_ACS_PPE2      );
+REG64( EX_11_CME_SCOM_FLAGS_SCOM                               , RULL(0x15012420), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_FLAGS_SCOM1                              , RULL(0x15012421), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_11_CME_SCOM_FLAGS_SCOM2                              , RULL(0x15012422), SH_UNT_EX_11    , SH_ACS_SCOM2_OR  );
+
+REG64( EQ_CME_SCOM_FWMR                                        , RULL(0x1001243A), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001203A,
+REG64( EQ_CME_SCOM_FWMR_CLEAR                                  , RULL(0x1001243B), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 1001203B,
+REG64( EQ_CME_SCOM_FWMR_OR                                     , RULL(0x1001243C), SH_UNT_EQ       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 1001203C,
+REG64( EQ_0_CME_SCOM_FWMR                                      , RULL(0x1001243A), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001203A,
+REG64( EQ_0_CME_SCOM_FWMR_CLEAR                                , RULL(0x1001243B), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 1001203B,
+REG64( EQ_0_CME_SCOM_FWMR_OR                                   , RULL(0x1001243C), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 1001203C,
+REG64( EQ_1_CME_SCOM_FWMR                                      , RULL(0x1101243A), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1101203A,
+REG64( EQ_1_CME_SCOM_FWMR_CLEAR                                , RULL(0x1101243B), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 1101203B,
+REG64( EQ_1_CME_SCOM_FWMR_OR                                   , RULL(0x1101243C), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 1101203C,
+REG64( EQ_2_CME_SCOM_FWMR                                      , RULL(0x1201243A), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1201203A,
+REG64( EQ_2_CME_SCOM_FWMR_CLEAR                                , RULL(0x1201243B), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 1201203B,
+REG64( EQ_2_CME_SCOM_FWMR_OR                                   , RULL(0x1201243C), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 1201203C,
+REG64( EQ_3_CME_SCOM_FWMR                                      , RULL(0x1301243A), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1301203A,
+REG64( EQ_3_CME_SCOM_FWMR_CLEAR                                , RULL(0x1301243B), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 1301203B,
+REG64( EQ_3_CME_SCOM_FWMR_OR                                   , RULL(0x1301243C), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 1301203C,
+REG64( EQ_4_CME_SCOM_FWMR                                      , RULL(0x1401243A), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1401203A,
+REG64( EQ_4_CME_SCOM_FWMR_CLEAR                                , RULL(0x1401243B), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 1401203B,
+REG64( EQ_4_CME_SCOM_FWMR_OR                                   , RULL(0x1401243C), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 1401203C,
+REG64( EQ_5_CME_SCOM_FWMR                                      , RULL(0x1501243A), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1501203A,
+REG64( EQ_5_CME_SCOM_FWMR_CLEAR                                , RULL(0x1501243B), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 1501203B,
+REG64( EQ_5_CME_SCOM_FWMR_OR                                   , RULL(0x1501243C), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 1501203C,
+REG64( EX_CME_SCOM_FWMR                                        , RULL(0x1001203A), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_CME_SCOM_FWMR_CLEAR                                  , RULL(0x1001203B), SH_UNT_EX       ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_CME_SCOM_FWMR_OR                                     , RULL(0x1001203C), SH_UNT_EX       , SH_ACS_SCOM2_OR  );
+REG64( EX_0_CME_SCOM_FWMR                                      , RULL(0x1001203A), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_FWMR_CLEAR                                , RULL(0x1001203B), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_0_CME_SCOM_FWMR_OR                                   , RULL(0x1001203C), SH_UNT_EX_0     , SH_ACS_SCOM2_OR  );
+REG64( EX_1_CME_SCOM_FWMR                                      , RULL(0x1001243A), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_FWMR_CLEAR                                , RULL(0x1001243B), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_1_CME_SCOM_FWMR_OR                                   , RULL(0x1001243C), SH_UNT_EX_1     , SH_ACS_SCOM2_OR  );
+REG64( EX_2_CME_SCOM_FWMR                                      , RULL(0x1101203A), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_FWMR_CLEAR                                , RULL(0x1101203B), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_2_CME_SCOM_FWMR_OR                                   , RULL(0x1101203C), SH_UNT_EX_2     , SH_ACS_SCOM2_OR  );
+REG64( EX_3_CME_SCOM_FWMR                                      , RULL(0x1101243A), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_FWMR_CLEAR                                , RULL(0x1101243B), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_3_CME_SCOM_FWMR_OR                                   , RULL(0x1101243C), SH_UNT_EX_3     , SH_ACS_SCOM2_OR  );
+REG64( EX_4_CME_SCOM_FWMR                                      , RULL(0x1201203A), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_FWMR_CLEAR                                , RULL(0x1201203B), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_4_CME_SCOM_FWMR_OR                                   , RULL(0x1201203C), SH_UNT_EX_4     , SH_ACS_SCOM2_OR  );
+REG64( EX_5_CME_SCOM_FWMR                                      , RULL(0x1201243A), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_FWMR_CLEAR                                , RULL(0x1201243B), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_5_CME_SCOM_FWMR_OR                                   , RULL(0x1201243C), SH_UNT_EX_5     , SH_ACS_SCOM2_OR  );
+REG64( EX_6_CME_SCOM_FWMR                                      , RULL(0x1301203A), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_FWMR_CLEAR                                , RULL(0x1301203B), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_6_CME_SCOM_FWMR_OR                                   , RULL(0x1301203C), SH_UNT_EX_6     , SH_ACS_SCOM2_OR  );
+REG64( EX_7_CME_SCOM_FWMR                                      , RULL(0x1301243A), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_FWMR_CLEAR                                , RULL(0x1301243B), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_7_CME_SCOM_FWMR_OR                                   , RULL(0x1301243C), SH_UNT_EX_7     , SH_ACS_SCOM2_OR  );
+REG64( EX_8_CME_SCOM_FWMR                                      , RULL(0x1401203A), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_FWMR_CLEAR                                , RULL(0x1401203B), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_8_CME_SCOM_FWMR_OR                                   , RULL(0x1401203C), SH_UNT_EX_8     , SH_ACS_SCOM2_OR  );
+REG64( EX_9_CME_SCOM_FWMR                                      , RULL(0x1401243A), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_FWMR_CLEAR                                , RULL(0x1401243B), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_9_CME_SCOM_FWMR_OR                                   , RULL(0x1401243C), SH_UNT_EX_9     , SH_ACS_SCOM2_OR  );
+REG64( EX_10_CME_SCOM_FWMR                                     , RULL(0x1501203A), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_FWMR_CLEAR                               , RULL(0x1501203B), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_10_CME_SCOM_FWMR_OR                                  , RULL(0x1501203C), SH_UNT_EX_10    , SH_ACS_SCOM2_OR  );
+REG64( EX_11_CME_SCOM_FWMR                                     , RULL(0x1501243A), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_FWMR_CLEAR                               , RULL(0x1501243B), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_11_CME_SCOM_FWMR_OR                                  , RULL(0x1501243C), SH_UNT_EX_11    , SH_ACS_SCOM2_OR  );
+
+REG64( EQ_CME_SCOM_IDCR                                        , RULL(0x1001242D), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001202D,
+REG64( EQ_0_CME_SCOM_IDCR                                      , RULL(0x1001242D), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001202D,
+REG64( EQ_1_CME_SCOM_IDCR                                      , RULL(0x1101242D), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1101202D,
+REG64( EQ_2_CME_SCOM_IDCR                                      , RULL(0x1201242D), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1201202D,
+REG64( EQ_3_CME_SCOM_IDCR                                      , RULL(0x1301242D), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1301202D,
+REG64( EQ_4_CME_SCOM_IDCR                                      , RULL(0x1401242D), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1401202D,
+REG64( EQ_5_CME_SCOM_IDCR                                      , RULL(0x1501242D), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1501202D,
+REG64( EX_CME_SCOM_IDCR_PPE                                    , RULL(0x1090106A0), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_IDCR_SCOM                                   , RULL(0x1001202D), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_IDCR_PPE                                  , RULL(0x1090106A0), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_IDCR_SCOM                                 , RULL(0x1001202D), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_IDCR_PPE                                  , RULL(0x1090206A0), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_IDCR_SCOM                                 , RULL(0x1001242D), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_IDCR_PPE                                  , RULL(0x10A0106A0), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_IDCR_SCOM                                 , RULL(0x1101202D), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_IDCR_PPE                                  , RULL(0x10A0206A0), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_IDCR_SCOM                                 , RULL(0x1101242D), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_IDCR_PPE                                  , RULL(0x10B0106A0), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_IDCR_SCOM                                 , RULL(0x1201202D), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_IDCR_PPE                                  , RULL(0x10B0206A0), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_IDCR_SCOM                                 , RULL(0x1201242D), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_IDCR_PPE                                  , RULL(0x10C0106A0), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_IDCR_SCOM                                 , RULL(0x1301202D), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_IDCR_PPE                                  , RULL(0x10C0206A0), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_IDCR_SCOM                                 , RULL(0x1301242D), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_IDCR_PPE                                  , RULL(0x10D0106A0), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_IDCR_SCOM                                 , RULL(0x1401202D), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_IDCR_PPE                                  , RULL(0x10D0206A0), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_IDCR_SCOM                                 , RULL(0x1401242D), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_IDCR_PPE                                 , RULL(0x10E0106A0), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_IDCR_SCOM                                , RULL(0x1501202D), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_IDCR_PPE                                 , RULL(0x10E0206A0), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_IDCR_SCOM                                , RULL(0x1501242D), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_LFIR                                        , RULL(0x10012400), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012000,
+REG64( EQ_CME_SCOM_LFIR_AND                                    , RULL(0x10012401), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_AND ); //DUPS: 10012001,
+REG64( EQ_CME_SCOM_LFIR_OR                                     , RULL(0x10012402), SH_UNT_EQ       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 10012002,
+REG64( EQ_0_CME_SCOM_LFIR                                      , RULL(0x10012400), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012000,
+REG64( EQ_0_CME_SCOM_LFIR_AND                                  , RULL(0x10012401), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 10012001,
+REG64( EQ_0_CME_SCOM_LFIR_OR                                   , RULL(0x10012402), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 10012002,
+REG64( EQ_1_CME_SCOM_LFIR                                      , RULL(0x11012400), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012000,
+REG64( EQ_1_CME_SCOM_LFIR_AND                                  , RULL(0x11012401), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 11012001,
+REG64( EQ_1_CME_SCOM_LFIR_OR                                   , RULL(0x11012402), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 11012002,
+REG64( EQ_2_CME_SCOM_LFIR                                      , RULL(0x12012400), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012000,
+REG64( EQ_2_CME_SCOM_LFIR_AND                                  , RULL(0x12012401), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 12012001,
+REG64( EQ_2_CME_SCOM_LFIR_OR                                   , RULL(0x12012402), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 12012002,
+REG64( EQ_3_CME_SCOM_LFIR                                      , RULL(0x13012400), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012000,
+REG64( EQ_3_CME_SCOM_LFIR_AND                                  , RULL(0x13012401), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 13012001,
+REG64( EQ_3_CME_SCOM_LFIR_OR                                   , RULL(0x13012402), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 13012002,
+REG64( EQ_4_CME_SCOM_LFIR                                      , RULL(0x14012400), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012000,
+REG64( EQ_4_CME_SCOM_LFIR_AND                                  , RULL(0x14012401), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 14012001,
+REG64( EQ_4_CME_SCOM_LFIR_OR                                   , RULL(0x14012402), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 14012002,
+REG64( EQ_5_CME_SCOM_LFIR                                      , RULL(0x15012400), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012000,
+REG64( EQ_5_CME_SCOM_LFIR_AND                                  , RULL(0x15012401), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 15012001,
+REG64( EQ_5_CME_SCOM_LFIR_OR                                   , RULL(0x15012402), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 15012002,
+REG64( EX_CME_SCOM_LFIR                                        , RULL(0x10012000), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_CME_SCOM_LFIR_AND                                    , RULL(0x10012001), SH_UNT_EX       , SH_ACS_SCOM1_AND );
+REG64( EX_CME_SCOM_LFIR_OR                                     , RULL(0x10012002), SH_UNT_EX       , SH_ACS_SCOM2_OR  );
+REG64( EX_0_CME_SCOM_LFIR                                      , RULL(0x10012000), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_LFIR_AND                                  , RULL(0x10012001), SH_UNT_EX_0     , SH_ACS_SCOM1_AND );
+REG64( EX_0_CME_SCOM_LFIR_OR                                   , RULL(0x10012002), SH_UNT_EX_0     , SH_ACS_SCOM2_OR  );
+REG64( EX_1_CME_SCOM_LFIR                                      , RULL(0x10012400), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_LFIR_AND                                  , RULL(0x10012401), SH_UNT_EX_1     , SH_ACS_SCOM1_AND );
+REG64( EX_1_CME_SCOM_LFIR_OR                                   , RULL(0x10012402), SH_UNT_EX_1     , SH_ACS_SCOM2_OR  );
+REG64( EX_2_CME_SCOM_LFIR                                      , RULL(0x11012000), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_LFIR_AND                                  , RULL(0x11012001), SH_UNT_EX_2     , SH_ACS_SCOM1_AND );
+REG64( EX_2_CME_SCOM_LFIR_OR                                   , RULL(0x11012002), SH_UNT_EX_2     , SH_ACS_SCOM2_OR  );
+REG64( EX_3_CME_SCOM_LFIR                                      , RULL(0x11012400), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_LFIR_AND                                  , RULL(0x11012401), SH_UNT_EX_3     , SH_ACS_SCOM1_AND );
+REG64( EX_3_CME_SCOM_LFIR_OR                                   , RULL(0x11012402), SH_UNT_EX_3     , SH_ACS_SCOM2_OR  );
+REG64( EX_4_CME_SCOM_LFIR                                      , RULL(0x12012000), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_LFIR_AND                                  , RULL(0x12012001), SH_UNT_EX_4     , SH_ACS_SCOM1_AND );
+REG64( EX_4_CME_SCOM_LFIR_OR                                   , RULL(0x12012002), SH_UNT_EX_4     , SH_ACS_SCOM2_OR  );
+REG64( EX_5_CME_SCOM_LFIR                                      , RULL(0x12012400), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_LFIR_AND                                  , RULL(0x12012401), SH_UNT_EX_5     , SH_ACS_SCOM1_AND );
+REG64( EX_5_CME_SCOM_LFIR_OR                                   , RULL(0x12012402), SH_UNT_EX_5     , SH_ACS_SCOM2_OR  );
+REG64( EX_6_CME_SCOM_LFIR                                      , RULL(0x13012000), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_LFIR_AND                                  , RULL(0x13012001), SH_UNT_EX_6     , SH_ACS_SCOM1_AND );
+REG64( EX_6_CME_SCOM_LFIR_OR                                   , RULL(0x13012002), SH_UNT_EX_6     , SH_ACS_SCOM2_OR  );
+REG64( EX_7_CME_SCOM_LFIR                                      , RULL(0x13012400), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_LFIR_AND                                  , RULL(0x13012401), SH_UNT_EX_7     , SH_ACS_SCOM1_AND );
+REG64( EX_7_CME_SCOM_LFIR_OR                                   , RULL(0x13012402), SH_UNT_EX_7     , SH_ACS_SCOM2_OR  );
+REG64( EX_8_CME_SCOM_LFIR                                      , RULL(0x14012000), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_LFIR_AND                                  , RULL(0x14012001), SH_UNT_EX_8     , SH_ACS_SCOM1_AND );
+REG64( EX_8_CME_SCOM_LFIR_OR                                   , RULL(0x14012002), SH_UNT_EX_8     , SH_ACS_SCOM2_OR  );
+REG64( EX_9_CME_SCOM_LFIR                                      , RULL(0x14012400), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_LFIR_AND                                  , RULL(0x14012401), SH_UNT_EX_9     , SH_ACS_SCOM1_AND );
+REG64( EX_9_CME_SCOM_LFIR_OR                                   , RULL(0x14012402), SH_UNT_EX_9     , SH_ACS_SCOM2_OR  );
+REG64( EX_10_CME_SCOM_LFIR                                     , RULL(0x15012000), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_LFIR_AND                                 , RULL(0x15012001), SH_UNT_EX_10    , SH_ACS_SCOM1_AND );
+REG64( EX_10_CME_SCOM_LFIR_OR                                  , RULL(0x15012002), SH_UNT_EX_10    , SH_ACS_SCOM2_OR  );
+REG64( EX_11_CME_SCOM_LFIR                                     , RULL(0x15012400), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_LFIR_AND                                 , RULL(0x15012401), SH_UNT_EX_11    , SH_ACS_SCOM1_AND );
+REG64( EX_11_CME_SCOM_LFIR_OR                                  , RULL(0x15012402), SH_UNT_EX_11    , SH_ACS_SCOM2_OR  );
+
+REG64( EQ_CME_SCOM_LFIRACT0                                    , RULL(0x10012406), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012006,
+REG64( EQ_0_CME_SCOM_LFIRACT0                                  , RULL(0x10012406), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012006,
+REG64( EQ_1_CME_SCOM_LFIRACT0                                  , RULL(0x11012406), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012006,
+REG64( EQ_2_CME_SCOM_LFIRACT0                                  , RULL(0x12012406), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012006,
+REG64( EQ_3_CME_SCOM_LFIRACT0                                  , RULL(0x13012406), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012006,
+REG64( EQ_4_CME_SCOM_LFIRACT0                                  , RULL(0x14012406), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012006,
+REG64( EQ_5_CME_SCOM_LFIRACT0                                  , RULL(0x15012406), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012006,
+REG64( EX_CME_SCOM_LFIRACT0                                    , RULL(0x10012006), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_LFIRACT0                                  , RULL(0x10012006), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_LFIRACT0                                  , RULL(0x10012406), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_LFIRACT0                                  , RULL(0x11012006), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_LFIRACT0                                  , RULL(0x11012406), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_LFIRACT0                                  , RULL(0x12012006), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_LFIRACT0                                  , RULL(0x12012406), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_LFIRACT0                                  , RULL(0x13012006), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_LFIRACT0                                  , RULL(0x13012406), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_LFIRACT0                                  , RULL(0x14012006), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_LFIRACT0                                  , RULL(0x14012406), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_LFIRACT0                                 , RULL(0x15012006), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_LFIRACT0                                 , RULL(0x15012406), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_LFIRACT1                                    , RULL(0x10012407), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012007,
+REG64( EQ_0_CME_SCOM_LFIRACT1                                  , RULL(0x10012407), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012007,
+REG64( EQ_1_CME_SCOM_LFIRACT1                                  , RULL(0x11012407), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012007,
+REG64( EQ_2_CME_SCOM_LFIRACT1                                  , RULL(0x12012407), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012007,
+REG64( EQ_3_CME_SCOM_LFIRACT1                                  , RULL(0x13012407), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012007,
+REG64( EQ_4_CME_SCOM_LFIRACT1                                  , RULL(0x14012407), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012007,
+REG64( EQ_5_CME_SCOM_LFIRACT1                                  , RULL(0x15012407), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012007,
+REG64( EX_CME_SCOM_LFIRACT1                                    , RULL(0x10012007), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_LFIRACT1                                  , RULL(0x10012007), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_LFIRACT1                                  , RULL(0x10012407), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_LFIRACT1                                  , RULL(0x11012007), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_LFIRACT1                                  , RULL(0x11012407), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_LFIRACT1                                  , RULL(0x12012007), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_LFIRACT1                                  , RULL(0x12012407), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_LFIRACT1                                  , RULL(0x13012007), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_LFIRACT1                                  , RULL(0x13012407), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_LFIRACT1                                  , RULL(0x14012007), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_LFIRACT1                                  , RULL(0x14012407), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_LFIRACT1                                 , RULL(0x15012007), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_LFIRACT1                                 , RULL(0x15012407), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_LFIRMASK                                    , RULL(0x10012403), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012003,
+REG64( EQ_CME_SCOM_LFIRMASK_AND                                , RULL(0x10012404), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_AND ); //DUPS: 10012004,
+REG64( EQ_CME_SCOM_LFIRMASK_OR                                 , RULL(0x10012405), SH_UNT_EQ       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 10012005,
+REG64( EQ_0_CME_SCOM_LFIRMASK                                  , RULL(0x10012403), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012003,
+REG64( EQ_0_CME_SCOM_LFIRMASK_AND                              , RULL(0x10012404), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 10012004,
+REG64( EQ_0_CME_SCOM_LFIRMASK_OR                               , RULL(0x10012405), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 10012005,
+REG64( EQ_1_CME_SCOM_LFIRMASK                                  , RULL(0x11012403), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012003,
+REG64( EQ_1_CME_SCOM_LFIRMASK_AND                              , RULL(0x11012404), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 11012004,
+REG64( EQ_1_CME_SCOM_LFIRMASK_OR                               , RULL(0x11012405), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 11012005,
+REG64( EQ_2_CME_SCOM_LFIRMASK                                  , RULL(0x12012403), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012003,
+REG64( EQ_2_CME_SCOM_LFIRMASK_AND                              , RULL(0x12012404), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 12012004,
+REG64( EQ_2_CME_SCOM_LFIRMASK_OR                               , RULL(0x12012405), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 12012005,
+REG64( EQ_3_CME_SCOM_LFIRMASK                                  , RULL(0x13012403), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012003,
+REG64( EQ_3_CME_SCOM_LFIRMASK_AND                              , RULL(0x13012404), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 13012004,
+REG64( EQ_3_CME_SCOM_LFIRMASK_OR                               , RULL(0x13012405), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 13012005,
+REG64( EQ_4_CME_SCOM_LFIRMASK                                  , RULL(0x14012403), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012003,
+REG64( EQ_4_CME_SCOM_LFIRMASK_AND                              , RULL(0x14012404), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 14012004,
+REG64( EQ_4_CME_SCOM_LFIRMASK_OR                               , RULL(0x14012405), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 14012005,
+REG64( EQ_5_CME_SCOM_LFIRMASK                                  , RULL(0x15012403), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012003,
+REG64( EQ_5_CME_SCOM_LFIRMASK_AND                              , RULL(0x15012404), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 15012004,
+REG64( EQ_5_CME_SCOM_LFIRMASK_OR                               , RULL(0x15012405), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 15012005,
+REG64( EX_CME_SCOM_LFIRMASK                                    , RULL(0x10012003), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_CME_SCOM_LFIRMASK_AND                                , RULL(0x10012004), SH_UNT_EX       , SH_ACS_SCOM1_AND );
+REG64( EX_CME_SCOM_LFIRMASK_OR                                 , RULL(0x10012005), SH_UNT_EX       , SH_ACS_SCOM2_OR  );
+REG64( EX_0_CME_SCOM_LFIRMASK                                  , RULL(0x10012003), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_LFIRMASK_AND                              , RULL(0x10012004), SH_UNT_EX_0     , SH_ACS_SCOM1_AND );
+REG64( EX_0_CME_SCOM_LFIRMASK_OR                               , RULL(0x10012005), SH_UNT_EX_0     , SH_ACS_SCOM2_OR  );
+REG64( EX_1_CME_SCOM_LFIRMASK                                  , RULL(0x10012403), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_LFIRMASK_AND                              , RULL(0x10012404), SH_UNT_EX_1     , SH_ACS_SCOM1_AND );
+REG64( EX_1_CME_SCOM_LFIRMASK_OR                               , RULL(0x10012405), SH_UNT_EX_1     , SH_ACS_SCOM2_OR  );
+REG64( EX_2_CME_SCOM_LFIRMASK                                  , RULL(0x11012003), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_LFIRMASK_AND                              , RULL(0x11012004), SH_UNT_EX_2     , SH_ACS_SCOM1_AND );
+REG64( EX_2_CME_SCOM_LFIRMASK_OR                               , RULL(0x11012005), SH_UNT_EX_2     , SH_ACS_SCOM2_OR  );
+REG64( EX_3_CME_SCOM_LFIRMASK                                  , RULL(0x11012403), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_LFIRMASK_AND                              , RULL(0x11012404), SH_UNT_EX_3     , SH_ACS_SCOM1_AND );
+REG64( EX_3_CME_SCOM_LFIRMASK_OR                               , RULL(0x11012405), SH_UNT_EX_3     , SH_ACS_SCOM2_OR  );
+REG64( EX_4_CME_SCOM_LFIRMASK                                  , RULL(0x12012003), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_LFIRMASK_AND                              , RULL(0x12012004), SH_UNT_EX_4     , SH_ACS_SCOM1_AND );
+REG64( EX_4_CME_SCOM_LFIRMASK_OR                               , RULL(0x12012005), SH_UNT_EX_4     , SH_ACS_SCOM2_OR  );
+REG64( EX_5_CME_SCOM_LFIRMASK                                  , RULL(0x12012403), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_LFIRMASK_AND                              , RULL(0x12012404), SH_UNT_EX_5     , SH_ACS_SCOM1_AND );
+REG64( EX_5_CME_SCOM_LFIRMASK_OR                               , RULL(0x12012405), SH_UNT_EX_5     , SH_ACS_SCOM2_OR  );
+REG64( EX_6_CME_SCOM_LFIRMASK                                  , RULL(0x13012003), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_LFIRMASK_AND                              , RULL(0x13012004), SH_UNT_EX_6     , SH_ACS_SCOM1_AND );
+REG64( EX_6_CME_SCOM_LFIRMASK_OR                               , RULL(0x13012005), SH_UNT_EX_6     , SH_ACS_SCOM2_OR  );
+REG64( EX_7_CME_SCOM_LFIRMASK                                  , RULL(0x13012403), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_LFIRMASK_AND                              , RULL(0x13012404), SH_UNT_EX_7     , SH_ACS_SCOM1_AND );
+REG64( EX_7_CME_SCOM_LFIRMASK_OR                               , RULL(0x13012405), SH_UNT_EX_7     , SH_ACS_SCOM2_OR  );
+REG64( EX_8_CME_SCOM_LFIRMASK                                  , RULL(0x14012003), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_LFIRMASK_AND                              , RULL(0x14012004), SH_UNT_EX_8     , SH_ACS_SCOM1_AND );
+REG64( EX_8_CME_SCOM_LFIRMASK_OR                               , RULL(0x14012005), SH_UNT_EX_8     , SH_ACS_SCOM2_OR  );
+REG64( EX_9_CME_SCOM_LFIRMASK                                  , RULL(0x14012403), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_LFIRMASK_AND                              , RULL(0x14012404), SH_UNT_EX_9     , SH_ACS_SCOM1_AND );
+REG64( EX_9_CME_SCOM_LFIRMASK_OR                               , RULL(0x14012405), SH_UNT_EX_9     , SH_ACS_SCOM2_OR  );
+REG64( EX_10_CME_SCOM_LFIRMASK                                 , RULL(0x15012003), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_LFIRMASK_AND                             , RULL(0x15012004), SH_UNT_EX_10    , SH_ACS_SCOM1_AND );
+REG64( EX_10_CME_SCOM_LFIRMASK_OR                              , RULL(0x15012005), SH_UNT_EX_10    , SH_ACS_SCOM2_OR  );
+REG64( EX_11_CME_SCOM_LFIRMASK                                 , RULL(0x15012403), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_LFIRMASK_AND                             , RULL(0x15012404), SH_UNT_EX_11    , SH_ACS_SCOM1_AND );
+REG64( EX_11_CME_SCOM_LFIRMASK_OR                              , RULL(0x15012405), SH_UNT_EX_11    , SH_ACS_SCOM2_OR  );
+
+REG64( EQ_CME_SCOM_PMCRS0                                      , RULL(0x10012442), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012042,
+REG64( EQ_0_CME_SCOM_PMCRS0                                    , RULL(0x10012442), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012042,
+REG64( EQ_1_CME_SCOM_PMCRS0                                    , RULL(0x11012442), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012042,
+REG64( EQ_2_CME_SCOM_PMCRS0                                    , RULL(0x12012442), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012042,
+REG64( EQ_3_CME_SCOM_PMCRS0                                    , RULL(0x13012442), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012042,
+REG64( EQ_4_CME_SCOM_PMCRS0                                    , RULL(0x14012442), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012042,
+REG64( EQ_5_CME_SCOM_PMCRS0                                    , RULL(0x15012442), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012042,
+REG64( EX_CME_SCOM_PMCRS0_PPE                                  , RULL(0x109010240), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_PMCRS0_SCOM                                 , RULL(0x10012042), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_PMCRS0_PPE                                , RULL(0x109010240), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_PMCRS0_SCOM                               , RULL(0x10012042), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_PMCRS0_PPE                                , RULL(0x109020240), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_PMCRS0_SCOM                               , RULL(0x10012442), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_PMCRS0_PPE                                , RULL(0x10A010240), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_PMCRS0_SCOM                               , RULL(0x11012042), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_PMCRS0_PPE                                , RULL(0x10A020240), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_PMCRS0_SCOM                               , RULL(0x11012442), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_PMCRS0_PPE                                , RULL(0x10B010240), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_PMCRS0_SCOM                               , RULL(0x12012042), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_PMCRS0_PPE                                , RULL(0x10B020240), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_PMCRS0_SCOM                               , RULL(0x12012442), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_PMCRS0_PPE                                , RULL(0x10C010240), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_PMCRS0_SCOM                               , RULL(0x13012042), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_PMCRS0_PPE                                , RULL(0x10C020240), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_PMCRS0_SCOM                               , RULL(0x13012442), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_PMCRS0_PPE                                , RULL(0x10D010240), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_PMCRS0_SCOM                               , RULL(0x14012042), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_PMCRS0_PPE                                , RULL(0x10D020240), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_PMCRS0_SCOM                               , RULL(0x14012442), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_PMCRS0_PPE                               , RULL(0x10E010240), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_PMCRS0_SCOM                              , RULL(0x15012042), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_PMCRS0_PPE                               , RULL(0x10E020240), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_PMCRS0_SCOM                              , RULL(0x15012442), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_PMCRS1                                      , RULL(0x10012443), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012043,
+REG64( EQ_0_CME_SCOM_PMCRS1                                    , RULL(0x10012443), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012043,
+REG64( EQ_1_CME_SCOM_PMCRS1                                    , RULL(0x11012443), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012043,
+REG64( EQ_2_CME_SCOM_PMCRS1                                    , RULL(0x12012443), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012043,
+REG64( EQ_3_CME_SCOM_PMCRS1                                    , RULL(0x13012443), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012043,
+REG64( EQ_4_CME_SCOM_PMCRS1                                    , RULL(0x14012443), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012043,
+REG64( EQ_5_CME_SCOM_PMCRS1                                    , RULL(0x15012443), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012043,
+REG64( EX_CME_SCOM_PMCRS1_PPE                                  , RULL(0x109010260), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_PMCRS1_SCOM                                 , RULL(0x10012043), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_PMCRS1_PPE                                , RULL(0x109010260), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_PMCRS1_SCOM                               , RULL(0x10012043), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_PMCRS1_PPE                                , RULL(0x109020260), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_PMCRS1_SCOM                               , RULL(0x10012443), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_PMCRS1_PPE                                , RULL(0x10A010260), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_PMCRS1_SCOM                               , RULL(0x11012043), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_PMCRS1_PPE                                , RULL(0x10A020260), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_PMCRS1_SCOM                               , RULL(0x11012443), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_PMCRS1_PPE                                , RULL(0x10B010260), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_PMCRS1_SCOM                               , RULL(0x12012043), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_PMCRS1_PPE                                , RULL(0x10B020260), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_PMCRS1_SCOM                               , RULL(0x12012443), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_PMCRS1_PPE                                , RULL(0x10C010260), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_PMCRS1_SCOM                               , RULL(0x13012043), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_PMCRS1_PPE                                , RULL(0x10C020260), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_PMCRS1_SCOM                               , RULL(0x13012443), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_PMCRS1_PPE                                , RULL(0x10D010260), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_PMCRS1_SCOM                               , RULL(0x14012043), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_PMCRS1_PPE                                , RULL(0x10D020260), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_PMCRS1_SCOM                               , RULL(0x14012443), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_PMCRS1_PPE                               , RULL(0x10E010260), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_PMCRS1_SCOM                              , RULL(0x15012043), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_PMCRS1_PPE                               , RULL(0x10E020260), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_PMCRS1_SCOM                              , RULL(0x15012443), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_PMSRS0                                      , RULL(0x10012440), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012040,
+REG64( EQ_0_CME_SCOM_PMSRS0                                    , RULL(0x10012440), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012040,
+REG64( EQ_1_CME_SCOM_PMSRS0                                    , RULL(0x11012440), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012040,
+REG64( EQ_2_CME_SCOM_PMSRS0                                    , RULL(0x12012440), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012040,
+REG64( EQ_3_CME_SCOM_PMSRS0                                    , RULL(0x13012440), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012040,
+REG64( EQ_4_CME_SCOM_PMSRS0                                    , RULL(0x14012440), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012040,
+REG64( EQ_5_CME_SCOM_PMSRS0                                    , RULL(0x15012440), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012040,
+REG64( EX_CME_SCOM_PMSRS0_PPE                                  , RULL(0x109010200), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_PMSRS0_SCOM                                 , RULL(0x10012040), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_PMSRS0_PPE                                , RULL(0x109010200), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_PMSRS0_SCOM                               , RULL(0x10012040), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_PMSRS0_PPE                                , RULL(0x109020200), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_PMSRS0_SCOM                               , RULL(0x10012440), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_PMSRS0_PPE                                , RULL(0x10A010200), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_PMSRS0_SCOM                               , RULL(0x11012040), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_PMSRS0_PPE                                , RULL(0x10A020200), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_PMSRS0_SCOM                               , RULL(0x11012440), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_PMSRS0_PPE                                , RULL(0x10B010200), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_PMSRS0_SCOM                               , RULL(0x12012040), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_PMSRS0_PPE                                , RULL(0x10B020200), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_PMSRS0_SCOM                               , RULL(0x12012440), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_PMSRS0_PPE                                , RULL(0x10C010200), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_PMSRS0_SCOM                               , RULL(0x13012040), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_PMSRS0_PPE                                , RULL(0x10C020200), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_PMSRS0_SCOM                               , RULL(0x13012440), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_PMSRS0_PPE                                , RULL(0x10D010200), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_PMSRS0_SCOM                               , RULL(0x14012040), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_PMSRS0_PPE                                , RULL(0x10D020200), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_PMSRS0_SCOM                               , RULL(0x14012440), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_PMSRS0_PPE                               , RULL(0x10E010200), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_PMSRS0_SCOM                              , RULL(0x15012040), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_PMSRS0_PPE                               , RULL(0x10E020200), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_PMSRS0_SCOM                              , RULL(0x15012440), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_PMSRS1                                      , RULL(0x10012441), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012041,
+REG64( EQ_0_CME_SCOM_PMSRS1                                    , RULL(0x10012441), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012041,
+REG64( EQ_1_CME_SCOM_PMSRS1                                    , RULL(0x11012441), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012041,
+REG64( EQ_2_CME_SCOM_PMSRS1                                    , RULL(0x12012441), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012041,
+REG64( EQ_3_CME_SCOM_PMSRS1                                    , RULL(0x13012441), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012041,
+REG64( EQ_4_CME_SCOM_PMSRS1                                    , RULL(0x14012441), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012041,
+REG64( EQ_5_CME_SCOM_PMSRS1                                    , RULL(0x15012441), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012041,
+REG64( EX_CME_SCOM_PMSRS1_PPE                                  , RULL(0x109010220), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_PMSRS1_SCOM                                 , RULL(0x10012041), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_PMSRS1_PPE                                , RULL(0x109010220), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_PMSRS1_SCOM                               , RULL(0x10012041), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_PMSRS1_PPE                                , RULL(0x109020220), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_PMSRS1_SCOM                               , RULL(0x10012441), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_PMSRS1_PPE                                , RULL(0x10A010220), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_PMSRS1_SCOM                               , RULL(0x11012041), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_PMSRS1_PPE                                , RULL(0x10A020220), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_PMSRS1_SCOM                               , RULL(0x11012441), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_PMSRS1_PPE                                , RULL(0x10B010220), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_PMSRS1_SCOM                               , RULL(0x12012041), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_PMSRS1_PPE                                , RULL(0x10B020220), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_PMSRS1_SCOM                               , RULL(0x12012441), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_PMSRS1_PPE                                , RULL(0x10C010220), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_PMSRS1_SCOM                               , RULL(0x13012041), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_PMSRS1_PPE                                , RULL(0x10C020220), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_PMSRS1_SCOM                               , RULL(0x13012441), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_PMSRS1_PPE                                , RULL(0x10D010220), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_PMSRS1_SCOM                               , RULL(0x14012041), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_PMSRS1_PPE                                , RULL(0x10D020220), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_PMSRS1_SCOM                               , RULL(0x14012441), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_PMSRS1_PPE                               , RULL(0x10E010220), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_PMSRS1_SCOM                              , RULL(0x15012041), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_PMSRS1_PPE                               , RULL(0x10E020220), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_PMSRS1_SCOM                              , RULL(0x15012441), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_PSCRS00                                     , RULL(0x10012444), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012044,
+REG64( EQ_0_CME_SCOM_PSCRS00                                   , RULL(0x10012444), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012044,
+REG64( EQ_1_CME_SCOM_PSCRS00                                   , RULL(0x11012444), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012044,
+REG64( EQ_2_CME_SCOM_PSCRS00                                   , RULL(0x12012444), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012044,
+REG64( EQ_3_CME_SCOM_PSCRS00                                   , RULL(0x13012444), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012044,
+REG64( EQ_4_CME_SCOM_PSCRS00                                   , RULL(0x14012444), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012044,
+REG64( EQ_5_CME_SCOM_PSCRS00                                   , RULL(0x15012444), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012044,
+REG64( EX_CME_SCOM_PSCRS00_PPE                                 , RULL(0x109010300), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_PSCRS00_SCOM                                , RULL(0x10012044), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_PSCRS00_PPE                               , RULL(0x109010300), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_PSCRS00_SCOM                              , RULL(0x10012044), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_PSCRS00_PPE                               , RULL(0x109020300), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_PSCRS00_SCOM                              , RULL(0x10012444), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_PSCRS00_PPE                               , RULL(0x10A010300), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_PSCRS00_SCOM                              , RULL(0x11012044), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_PSCRS00_PPE                               , RULL(0x10A020300), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_PSCRS00_SCOM                              , RULL(0x11012444), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_PSCRS00_PPE                               , RULL(0x10B010300), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_PSCRS00_SCOM                              , RULL(0x12012044), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_PSCRS00_PPE                               , RULL(0x10B020300), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_PSCRS00_SCOM                              , RULL(0x12012444), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_PSCRS00_PPE                               , RULL(0x10C010300), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_PSCRS00_SCOM                              , RULL(0x13012044), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_PSCRS00_PPE                               , RULL(0x10C020300), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_PSCRS00_SCOM                              , RULL(0x13012444), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_PSCRS00_PPE                               , RULL(0x10D010300), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_PSCRS00_SCOM                              , RULL(0x14012044), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_PSCRS00_PPE                               , RULL(0x10D020300), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_PSCRS00_SCOM                              , RULL(0x14012444), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_PSCRS00_PPE                              , RULL(0x10E010300), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_PSCRS00_SCOM                             , RULL(0x15012044), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_PSCRS00_PPE                              , RULL(0x10E020300), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_PSCRS00_SCOM                             , RULL(0x15012444), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_PSCRS01                                     , RULL(0x10012445), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012045,
+REG64( EQ_0_CME_SCOM_PSCRS01                                   , RULL(0x10012445), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012045,
+REG64( EQ_1_CME_SCOM_PSCRS01                                   , RULL(0x11012445), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012045,
+REG64( EQ_2_CME_SCOM_PSCRS01                                   , RULL(0x12012445), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012045,
+REG64( EQ_3_CME_SCOM_PSCRS01                                   , RULL(0x13012445), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012045,
+REG64( EQ_4_CME_SCOM_PSCRS01                                   , RULL(0x14012445), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012045,
+REG64( EQ_5_CME_SCOM_PSCRS01                                   , RULL(0x15012445), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012045,
+REG64( EX_CME_SCOM_PSCRS01_PPE                                 , RULL(0x109010320), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_PSCRS01_SCOM                                , RULL(0x10012045), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_PSCRS01_PPE                               , RULL(0x109010320), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_PSCRS01_SCOM                              , RULL(0x10012045), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_PSCRS01_PPE                               , RULL(0x109020320), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_PSCRS01_SCOM                              , RULL(0x10012445), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_PSCRS01_PPE                               , RULL(0x10A010320), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_PSCRS01_SCOM                              , RULL(0x11012045), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_PSCRS01_PPE                               , RULL(0x10A020320), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_PSCRS01_SCOM                              , RULL(0x11012445), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_PSCRS01_PPE                               , RULL(0x10B010320), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_PSCRS01_SCOM                              , RULL(0x12012045), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_PSCRS01_PPE                               , RULL(0x10B020320), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_PSCRS01_SCOM                              , RULL(0x12012445), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_PSCRS01_PPE                               , RULL(0x10C010320), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_PSCRS01_SCOM                              , RULL(0x13012045), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_PSCRS01_PPE                               , RULL(0x10C020320), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_PSCRS01_SCOM                              , RULL(0x13012445), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_PSCRS01_PPE                               , RULL(0x10D010320), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_PSCRS01_SCOM                              , RULL(0x14012045), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_PSCRS01_PPE                               , RULL(0x10D020320), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_PSCRS01_SCOM                              , RULL(0x14012445), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_PSCRS01_PPE                              , RULL(0x10E010320), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_PSCRS01_SCOM                             , RULL(0x15012045), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_PSCRS01_PPE                              , RULL(0x10E020320), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_PSCRS01_SCOM                             , RULL(0x15012445), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_PSCRS02                                     , RULL(0x10012446), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012046,
+REG64( EQ_0_CME_SCOM_PSCRS02                                   , RULL(0x10012446), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012046,
+REG64( EQ_1_CME_SCOM_PSCRS02                                   , RULL(0x11012446), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012046,
+REG64( EQ_2_CME_SCOM_PSCRS02                                   , RULL(0x12012446), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012046,
+REG64( EQ_3_CME_SCOM_PSCRS02                                   , RULL(0x13012446), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012046,
+REG64( EQ_4_CME_SCOM_PSCRS02                                   , RULL(0x14012446), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012046,
+REG64( EQ_5_CME_SCOM_PSCRS02                                   , RULL(0x15012446), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012046,
+REG64( EX_CME_SCOM_PSCRS02_PPE                                 , RULL(0x109010340), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_PSCRS02_SCOM                                , RULL(0x10012046), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_PSCRS02_PPE                               , RULL(0x109010340), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_PSCRS02_SCOM                              , RULL(0x10012046), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_PSCRS02_PPE                               , RULL(0x109020340), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_PSCRS02_SCOM                              , RULL(0x10012446), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_PSCRS02_PPE                               , RULL(0x10A010340), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_PSCRS02_SCOM                              , RULL(0x11012046), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_PSCRS02_PPE                               , RULL(0x10A020340), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_PSCRS02_SCOM                              , RULL(0x11012446), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_PSCRS02_PPE                               , RULL(0x10B010340), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_PSCRS02_SCOM                              , RULL(0x12012046), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_PSCRS02_PPE                               , RULL(0x10B020340), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_PSCRS02_SCOM                              , RULL(0x12012446), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_PSCRS02_PPE                               , RULL(0x10C010340), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_PSCRS02_SCOM                              , RULL(0x13012046), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_PSCRS02_PPE                               , RULL(0x10C020340), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_PSCRS02_SCOM                              , RULL(0x13012446), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_PSCRS02_PPE                               , RULL(0x10D010340), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_PSCRS02_SCOM                              , RULL(0x14012046), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_PSCRS02_PPE                               , RULL(0x10D020340), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_PSCRS02_SCOM                              , RULL(0x14012446), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_PSCRS02_PPE                              , RULL(0x10E010340), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_PSCRS02_SCOM                             , RULL(0x15012046), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_PSCRS02_PPE                              , RULL(0x10E020340), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_PSCRS02_SCOM                             , RULL(0x15012446), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_PSCRS03                                     , RULL(0x10012447), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012047,
+REG64( EQ_0_CME_SCOM_PSCRS03                                   , RULL(0x10012447), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012047,
+REG64( EQ_1_CME_SCOM_PSCRS03                                   , RULL(0x11012447), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012047,
+REG64( EQ_2_CME_SCOM_PSCRS03                                   , RULL(0x12012447), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012047,
+REG64( EQ_3_CME_SCOM_PSCRS03                                   , RULL(0x13012447), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012047,
+REG64( EQ_4_CME_SCOM_PSCRS03                                   , RULL(0x14012447), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012047,
+REG64( EQ_5_CME_SCOM_PSCRS03                                   , RULL(0x15012447), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012047,
+REG64( EX_CME_SCOM_PSCRS03_PPE                                 , RULL(0x109010360), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_PSCRS03_SCOM                                , RULL(0x10012047), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_PSCRS03_PPE                               , RULL(0x109010360), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_PSCRS03_SCOM                              , RULL(0x10012047), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_PSCRS03_PPE                               , RULL(0x109020360), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_PSCRS03_SCOM                              , RULL(0x10012447), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_PSCRS03_PPE                               , RULL(0x10A010360), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_PSCRS03_SCOM                              , RULL(0x11012047), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_PSCRS03_PPE                               , RULL(0x10A020360), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_PSCRS03_SCOM                              , RULL(0x11012447), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_PSCRS03_PPE                               , RULL(0x10B010360), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_PSCRS03_SCOM                              , RULL(0x12012047), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_PSCRS03_PPE                               , RULL(0x10B020360), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_PSCRS03_SCOM                              , RULL(0x12012447), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_PSCRS03_PPE                               , RULL(0x10C010360), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_PSCRS03_SCOM                              , RULL(0x13012047), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_PSCRS03_PPE                               , RULL(0x10C020360), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_PSCRS03_SCOM                              , RULL(0x13012447), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_PSCRS03_PPE                               , RULL(0x10D010360), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_PSCRS03_SCOM                              , RULL(0x14012047), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_PSCRS03_PPE                               , RULL(0x10D020360), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_PSCRS03_SCOM                              , RULL(0x14012447), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_PSCRS03_PPE                              , RULL(0x10E010360), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_PSCRS03_SCOM                             , RULL(0x15012047), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_PSCRS03_PPE                              , RULL(0x10E020360), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_PSCRS03_SCOM                             , RULL(0x15012447), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_PSCRS10                                     , RULL(0x10012448), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012048,
+REG64( EQ_0_CME_SCOM_PSCRS10                                   , RULL(0x10012448), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012048,
+REG64( EQ_1_CME_SCOM_PSCRS10                                   , RULL(0x11012448), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012048,
+REG64( EQ_2_CME_SCOM_PSCRS10                                   , RULL(0x12012448), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012048,
+REG64( EQ_3_CME_SCOM_PSCRS10                                   , RULL(0x13012448), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012048,
+REG64( EQ_4_CME_SCOM_PSCRS10                                   , RULL(0x14012448), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012048,
+REG64( EQ_5_CME_SCOM_PSCRS10                                   , RULL(0x15012448), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012048,
+REG64( EX_CME_SCOM_PSCRS10_PPE                                 , RULL(0x109010380), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_PSCRS10_SCOM                                , RULL(0x10012048), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_PSCRS10_PPE                               , RULL(0x109010380), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_PSCRS10_SCOM                              , RULL(0x10012048), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_PSCRS10_PPE                               , RULL(0x109020380), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_PSCRS10_SCOM                              , RULL(0x10012448), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_PSCRS10_PPE                               , RULL(0x10A010380), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_PSCRS10_SCOM                              , RULL(0x11012048), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_PSCRS10_PPE                               , RULL(0x10A020380), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_PSCRS10_SCOM                              , RULL(0x11012448), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_PSCRS10_PPE                               , RULL(0x10B010380), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_PSCRS10_SCOM                              , RULL(0x12012048), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_PSCRS10_PPE                               , RULL(0x10B020380), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_PSCRS10_SCOM                              , RULL(0x12012448), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_PSCRS10_PPE                               , RULL(0x10C010380), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_PSCRS10_SCOM                              , RULL(0x13012048), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_PSCRS10_PPE                               , RULL(0x10C020380), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_PSCRS10_SCOM                              , RULL(0x13012448), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_PSCRS10_PPE                               , RULL(0x10D010380), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_PSCRS10_SCOM                              , RULL(0x14012048), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_PSCRS10_PPE                               , RULL(0x10D020380), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_PSCRS10_SCOM                              , RULL(0x14012448), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_PSCRS10_PPE                              , RULL(0x10E010380), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_PSCRS10_SCOM                             , RULL(0x15012048), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_PSCRS10_PPE                              , RULL(0x10E020380), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_PSCRS10_SCOM                             , RULL(0x15012448), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_PSCRS11                                     , RULL(0x10012449), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012049,
+REG64( EQ_0_CME_SCOM_PSCRS11                                   , RULL(0x10012449), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012049,
+REG64( EQ_1_CME_SCOM_PSCRS11                                   , RULL(0x11012449), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012049,
+REG64( EQ_2_CME_SCOM_PSCRS11                                   , RULL(0x12012449), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012049,
+REG64( EQ_3_CME_SCOM_PSCRS11                                   , RULL(0x13012449), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012049,
+REG64( EQ_4_CME_SCOM_PSCRS11                                   , RULL(0x14012449), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012049,
+REG64( EQ_5_CME_SCOM_PSCRS11                                   , RULL(0x15012449), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012049,
+REG64( EX_CME_SCOM_PSCRS11_PPE                                 , RULL(0x1090103A0), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_PSCRS11_SCOM                                , RULL(0x10012049), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_PSCRS11_PPE                               , RULL(0x1090103A0), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_PSCRS11_SCOM                              , RULL(0x10012049), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_PSCRS11_PPE                               , RULL(0x1090203A0), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_PSCRS11_SCOM                              , RULL(0x10012449), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_PSCRS11_PPE                               , RULL(0x10A0103A0), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_PSCRS11_SCOM                              , RULL(0x11012049), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_PSCRS11_PPE                               , RULL(0x10A0203A0), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_PSCRS11_SCOM                              , RULL(0x11012449), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_PSCRS11_PPE                               , RULL(0x10B0103A0), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_PSCRS11_SCOM                              , RULL(0x12012049), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_PSCRS11_PPE                               , RULL(0x10B0203A0), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_PSCRS11_SCOM                              , RULL(0x12012449), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_PSCRS11_PPE                               , RULL(0x10C0103A0), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_PSCRS11_SCOM                              , RULL(0x13012049), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_PSCRS11_PPE                               , RULL(0x10C0203A0), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_PSCRS11_SCOM                              , RULL(0x13012449), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_PSCRS11_PPE                               , RULL(0x10D0103A0), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_PSCRS11_SCOM                              , RULL(0x14012049), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_PSCRS11_PPE                               , RULL(0x10D0203A0), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_PSCRS11_SCOM                              , RULL(0x14012449), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_PSCRS11_PPE                              , RULL(0x10E0103A0), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_PSCRS11_SCOM                             , RULL(0x15012049), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_PSCRS11_PPE                              , RULL(0x10E0203A0), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_PSCRS11_SCOM                             , RULL(0x15012449), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_PSCRS12                                     , RULL(0x1001244A), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001204A,
+REG64( EQ_0_CME_SCOM_PSCRS12                                   , RULL(0x1001244A), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001204A,
+REG64( EQ_1_CME_SCOM_PSCRS12                                   , RULL(0x1101244A), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1101204A,
+REG64( EQ_2_CME_SCOM_PSCRS12                                   , RULL(0x1201244A), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1201204A,
+REG64( EQ_3_CME_SCOM_PSCRS12                                   , RULL(0x1301244A), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1301204A,
+REG64( EQ_4_CME_SCOM_PSCRS12                                   , RULL(0x1401244A), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1401204A,
+REG64( EQ_5_CME_SCOM_PSCRS12                                   , RULL(0x1501244A), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1501204A,
+REG64( EX_CME_SCOM_PSCRS12_PPE                                 , RULL(0x1090103C0), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_PSCRS12_SCOM                                , RULL(0x1001204A), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_PSCRS12_PPE                               , RULL(0x1090103C0), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_PSCRS12_SCOM                              , RULL(0x1001204A), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_PSCRS12_PPE                               , RULL(0x1090203C0), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_PSCRS12_SCOM                              , RULL(0x1001244A), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_PSCRS12_PPE                               , RULL(0x10A0103C0), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_PSCRS12_SCOM                              , RULL(0x1101204A), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_PSCRS12_PPE                               , RULL(0x10A0203C0), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_PSCRS12_SCOM                              , RULL(0x1101244A), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_PSCRS12_PPE                               , RULL(0x10B0103C0), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_PSCRS12_SCOM                              , RULL(0x1201204A), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_PSCRS12_PPE                               , RULL(0x10B0203C0), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_PSCRS12_SCOM                              , RULL(0x1201244A), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_PSCRS12_PPE                               , RULL(0x10C0103C0), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_PSCRS12_SCOM                              , RULL(0x1301204A), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_PSCRS12_PPE                               , RULL(0x10C0203C0), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_PSCRS12_SCOM                              , RULL(0x1301244A), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_PSCRS12_PPE                               , RULL(0x10D0103C0), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_PSCRS12_SCOM                              , RULL(0x1401204A), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_PSCRS12_PPE                               , RULL(0x10D0203C0), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_PSCRS12_SCOM                              , RULL(0x1401244A), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_PSCRS12_PPE                              , RULL(0x10E0103C0), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_PSCRS12_SCOM                             , RULL(0x1501204A), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_PSCRS12_PPE                              , RULL(0x10E0203C0), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_PSCRS12_SCOM                             , RULL(0x1501244A), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_PSCRS13                                     , RULL(0x1001244B), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001204B,
+REG64( EQ_0_CME_SCOM_PSCRS13                                   , RULL(0x1001244B), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001204B,
+REG64( EQ_1_CME_SCOM_PSCRS13                                   , RULL(0x1101244B), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1101204B,
+REG64( EQ_2_CME_SCOM_PSCRS13                                   , RULL(0x1201244B), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1201204B,
+REG64( EQ_3_CME_SCOM_PSCRS13                                   , RULL(0x1301244B), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1301204B,
+REG64( EQ_4_CME_SCOM_PSCRS13                                   , RULL(0x1401244B), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1401204B,
+REG64( EQ_5_CME_SCOM_PSCRS13                                   , RULL(0x1501244B), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1501204B,
+REG64( EX_CME_SCOM_PSCRS13_PPE                                 , RULL(0x1090103E0), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_PSCRS13_SCOM                                , RULL(0x1001204B), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_PSCRS13_PPE                               , RULL(0x1090103E0), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_PSCRS13_SCOM                              , RULL(0x1001204B), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_PSCRS13_PPE                               , RULL(0x1090203E0), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_PSCRS13_SCOM                              , RULL(0x1001244B), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_PSCRS13_PPE                               , RULL(0x10A0103E0), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_PSCRS13_SCOM                              , RULL(0x1101204B), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_PSCRS13_PPE                               , RULL(0x10A0203E0), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_PSCRS13_SCOM                              , RULL(0x1101244B), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_PSCRS13_PPE                               , RULL(0x10B0103E0), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_PSCRS13_SCOM                              , RULL(0x1201204B), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_PSCRS13_PPE                               , RULL(0x10B0203E0), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_PSCRS13_SCOM                              , RULL(0x1201244B), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_PSCRS13_PPE                               , RULL(0x10C0103E0), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_PSCRS13_SCOM                              , RULL(0x1301204B), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_PSCRS13_PPE                               , RULL(0x10C0203E0), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_PSCRS13_SCOM                              , RULL(0x1301244B), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_PSCRS13_PPE                               , RULL(0x10D0103E0), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_PSCRS13_SCOM                              , RULL(0x1401204B), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_PSCRS13_PPE                               , RULL(0x10D0203E0), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_PSCRS13_SCOM                              , RULL(0x1401244B), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_PSCRS13_PPE                              , RULL(0x10E0103E0), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_PSCRS13_SCOM                             , RULL(0x1501204B), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_PSCRS13_PPE                              , RULL(0x10E0203E0), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_PSCRS13_SCOM                             , RULL(0x1501244B), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_QFMR                                        , RULL(0x10012432), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012032,
+REG64( EQ_0_CME_SCOM_QFMR                                      , RULL(0x10012432), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012032,
+REG64( EQ_1_CME_SCOM_QFMR                                      , RULL(0x11012432), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012032,
+REG64( EQ_2_CME_SCOM_QFMR                                      , RULL(0x12012432), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012032,
+REG64( EQ_3_CME_SCOM_QFMR                                      , RULL(0x13012432), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012032,
+REG64( EQ_4_CME_SCOM_QFMR                                      , RULL(0x14012432), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012032,
+REG64( EQ_5_CME_SCOM_QFMR                                      , RULL(0x15012432), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012032,
+REG64( EX_CME_SCOM_QFMR_PPE                                    , RULL(0x109010140), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_QFMR_SCOM                                   , RULL(0x10012032), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_SCOM_QFMR_PPE                                  , RULL(0x109010140), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_QFMR_SCOM                                 , RULL(0x10012032), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_SCOM_QFMR_PPE                                  , RULL(0x109020140), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_QFMR_SCOM                                 , RULL(0x10012432), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_SCOM_QFMR_PPE                                  , RULL(0x10A010140), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_QFMR_SCOM                                 , RULL(0x11012032), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_SCOM_QFMR_PPE                                  , RULL(0x10A020140), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_QFMR_SCOM                                 , RULL(0x11012432), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_SCOM_QFMR_PPE                                  , RULL(0x10B010140), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_QFMR_SCOM                                 , RULL(0x12012032), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_SCOM_QFMR_PPE                                  , RULL(0x10B020140), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_QFMR_SCOM                                 , RULL(0x12012432), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_SCOM_QFMR_PPE                                  , RULL(0x10C010140), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_QFMR_SCOM                                 , RULL(0x13012032), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_SCOM_QFMR_PPE                                  , RULL(0x10C020140), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_QFMR_SCOM                                 , RULL(0x13012432), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_SCOM_QFMR_PPE                                  , RULL(0x10D010140), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_QFMR_SCOM                                 , RULL(0x14012032), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_SCOM_QFMR_PPE                                  , RULL(0x10D020140), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_QFMR_SCOM                                 , RULL(0x14012432), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_SCOM_QFMR_PPE                                 , RULL(0x10E010140), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_QFMR_SCOM                                , RULL(0x15012032), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_SCOM_QFMR_PPE                                 , RULL(0x10E020140), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_QFMR_SCOM                                , RULL(0x15012432), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_SCOM_QIDSR                                       , RULL(0x1001242F), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001202F,
+REG64( EQ_0_CME_SCOM_QIDSR                                     , RULL(0x1001242F), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001202F,
+REG64( EQ_1_CME_SCOM_QIDSR                                     , RULL(0x1101242F), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1101202F,
+REG64( EQ_2_CME_SCOM_QIDSR                                     , RULL(0x1201242F), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1201202F,
+REG64( EQ_3_CME_SCOM_QIDSR                                     , RULL(0x1301242F), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1301202F,
+REG64( EQ_4_CME_SCOM_QIDSR                                     , RULL(0x1401242F), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1401202F,
+REG64( EQ_5_CME_SCOM_QIDSR                                     , RULL(0x1501242F), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1501202F,
+REG64( EX_CME_SCOM_QIDSR_PPE                                   , RULL(0x1090106E0), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_QIDSR_SCOM                                  , RULL(0x1001202F), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_SCOM_QIDSR_PPE                                 , RULL(0x1090106E0), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_QIDSR_SCOM                                , RULL(0x1001202F), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_SCOM_QIDSR_PPE                                 , RULL(0x1090206E0), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_QIDSR_SCOM                                , RULL(0x1001242F), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_SCOM_QIDSR_PPE                                 , RULL(0x10A0106E0), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_QIDSR_SCOM                                , RULL(0x1101202F), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_SCOM_QIDSR_PPE                                 , RULL(0x10A0206E0), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_QIDSR_SCOM                                , RULL(0x1101242F), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_SCOM_QIDSR_PPE                                 , RULL(0x10B0106E0), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_QIDSR_SCOM                                , RULL(0x1201202F), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_SCOM_QIDSR_PPE                                 , RULL(0x10B0206E0), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_QIDSR_SCOM                                , RULL(0x1201242F), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_SCOM_QIDSR_PPE                                 , RULL(0x10C0106E0), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_QIDSR_SCOM                                , RULL(0x1301202F), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_SCOM_QIDSR_PPE                                 , RULL(0x10C0206E0), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_QIDSR_SCOM                                , RULL(0x1301242F), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_SCOM_QIDSR_PPE                                 , RULL(0x10D0106E0), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_QIDSR_SCOM                                , RULL(0x1401202F), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_SCOM_QIDSR_PPE                                 , RULL(0x10D0206E0), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_QIDSR_SCOM                                , RULL(0x1401242F), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_SCOM_QIDSR_PPE                                , RULL(0x10E0106E0), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_QIDSR_SCOM                               , RULL(0x1501202F), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_SCOM_QIDSR_PPE                                , RULL(0x10E0206E0), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_QIDSR_SCOM                               , RULL(0x1501242F), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_SCOM_SICR_SCOM                                   , RULL(0x1001243D), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 1001203D,
+REG64( EQ_CME_SCOM_SICR_SCOM1                                  , RULL(0x1001243E), SH_UNT_EQ       ,
+       SH_ACS_SCOM1     ); //DUPS: 1001203E,
+REG64( EQ_CME_SCOM_SICR_SCOM2                                  , RULL(0x1001243F), SH_UNT_EQ       ,
+       SH_ACS_SCOM2     ); //DUPS: 1001203F,
+REG64( EQ_0_CME_SCOM_SICR_SCOM                                 , RULL(0x1001243D), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 1001203D,
+REG64( EQ_0_CME_SCOM_SICR_SCOM1                                , RULL(0x1001243E), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1     ); //DUPS: 1001203E,
+REG64( EQ_0_CME_SCOM_SICR_SCOM2                                , RULL(0x1001243F), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM2     ); //DUPS: 1001203F,
+REG64( EQ_1_CME_SCOM_SICR_SCOM                                 , RULL(0x1101243D), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 1101203D,
+REG64( EQ_1_CME_SCOM_SICR_SCOM1                                , RULL(0x1101243E), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1     ); //DUPS: 1101203E,
+REG64( EQ_1_CME_SCOM_SICR_SCOM2                                , RULL(0x1101243F), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM2     ); //DUPS: 1101203F,
+REG64( EQ_2_CME_SCOM_SICR_SCOM                                 , RULL(0x1201243D), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 1201203D,
+REG64( EQ_2_CME_SCOM_SICR_SCOM1                                , RULL(0x1201243E), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1     ); //DUPS: 1201203E,
+REG64( EQ_2_CME_SCOM_SICR_SCOM2                                , RULL(0x1201243F), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM2     ); //DUPS: 1201203F,
+REG64( EQ_3_CME_SCOM_SICR_SCOM                                 , RULL(0x1301243D), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 1301203D,
+REG64( EQ_3_CME_SCOM_SICR_SCOM1                                , RULL(0x1301243E), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1     ); //DUPS: 1301203E,
+REG64( EQ_3_CME_SCOM_SICR_SCOM2                                , RULL(0x1301243F), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM2     ); //DUPS: 1301203F,
+REG64( EQ_4_CME_SCOM_SICR_SCOM                                 , RULL(0x1401243D), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 1401203D,
+REG64( EQ_4_CME_SCOM_SICR_SCOM1                                , RULL(0x1401243E), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1     ); //DUPS: 1401203E,
+REG64( EQ_4_CME_SCOM_SICR_SCOM2                                , RULL(0x1401243F), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM2     ); //DUPS: 1401203F,
+REG64( EQ_5_CME_SCOM_SICR_SCOM                                 , RULL(0x1501243D), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 1501203D,
+REG64( EQ_5_CME_SCOM_SICR_SCOM1                                , RULL(0x1501243E), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1     ); //DUPS: 1501203E,
+REG64( EQ_5_CME_SCOM_SICR_SCOM2                                , RULL(0x1501243F), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM2     ); //DUPS: 1501203F,
+REG64( EX_CME_SCOM_SICR_PPE                                    , RULL(0x109010500), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_SICR_PPE1                                   , RULL(0x109010518), SH_UNT_EX       ,
+       SH_ACS_PPE1      );
+REG64( EX_CME_SCOM_SICR_PPE2                                   , RULL(0x109010510), SH_UNT_EX       ,
+       SH_ACS_PPE2      );
+REG64( EX_CME_SCOM_SICR_SCOM                                   , RULL(0x1001203D), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_CME_SCOM_SICR_SCOM1                                  , RULL(0x1001203E), SH_UNT_EX       , SH_ACS_SCOM1     );
+REG64( EX_CME_SCOM_SICR_SCOM2                                  , RULL(0x1001203F), SH_UNT_EX       , SH_ACS_SCOM2     );
+REG64( EX_0_CME_SCOM_SICR_PPE                                  , RULL(0x109010500), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_SICR_PPE1                                 , RULL(0x109010518), SH_UNT_EX_0     ,
+       SH_ACS_PPE1      );
+REG64( EX_0_CME_SCOM_SICR_PPE2                                 , RULL(0x109010510), SH_UNT_EX_0     ,
+       SH_ACS_PPE2      );
+REG64( EX_0_CME_SCOM_SICR_SCOM                                 , RULL(0x1001203D), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_0_CME_SCOM_SICR_SCOM1                                , RULL(0x1001203E), SH_UNT_EX_0     , SH_ACS_SCOM1     );
+REG64( EX_0_CME_SCOM_SICR_SCOM2                                , RULL(0x1001203F), SH_UNT_EX_0     , SH_ACS_SCOM2     );
+REG64( EX_1_CME_SCOM_SICR_PPE                                  , RULL(0x109020500), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_SICR_PPE1                                 , RULL(0x109020518), SH_UNT_EX_1     ,
+       SH_ACS_PPE1      );
+REG64( EX_1_CME_SCOM_SICR_PPE2                                 , RULL(0x109020510), SH_UNT_EX_1     ,
+       SH_ACS_PPE2      );
+REG64( EX_1_CME_SCOM_SICR_SCOM                                 , RULL(0x1001243D), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_1_CME_SCOM_SICR_SCOM1                                , RULL(0x1001243E), SH_UNT_EX_1     , SH_ACS_SCOM1     );
+REG64( EX_1_CME_SCOM_SICR_SCOM2                                , RULL(0x1001243F), SH_UNT_EX_1     , SH_ACS_SCOM2     );
+REG64( EX_2_CME_SCOM_SICR_PPE                                  , RULL(0x10A010500), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_SICR_PPE1                                 , RULL(0x10A010518), SH_UNT_EX_2     ,
+       SH_ACS_PPE1      );
+REG64( EX_2_CME_SCOM_SICR_PPE2                                 , RULL(0x10A010510), SH_UNT_EX_2     ,
+       SH_ACS_PPE2      );
+REG64( EX_2_CME_SCOM_SICR_SCOM                                 , RULL(0x1101203D), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_2_CME_SCOM_SICR_SCOM1                                , RULL(0x1101203E), SH_UNT_EX_2     , SH_ACS_SCOM1     );
+REG64( EX_2_CME_SCOM_SICR_SCOM2                                , RULL(0x1101203F), SH_UNT_EX_2     , SH_ACS_SCOM2     );
+REG64( EX_3_CME_SCOM_SICR_PPE                                  , RULL(0x10A020500), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_SICR_PPE1                                 , RULL(0x10A020518), SH_UNT_EX_3     ,
+       SH_ACS_PPE1      );
+REG64( EX_3_CME_SCOM_SICR_PPE2                                 , RULL(0x10A020510), SH_UNT_EX_3     ,
+       SH_ACS_PPE2      );
+REG64( EX_3_CME_SCOM_SICR_SCOM                                 , RULL(0x1101243D), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_3_CME_SCOM_SICR_SCOM1                                , RULL(0x1101243E), SH_UNT_EX_3     , SH_ACS_SCOM1     );
+REG64( EX_3_CME_SCOM_SICR_SCOM2                                , RULL(0x1101243F), SH_UNT_EX_3     , SH_ACS_SCOM2     );
+REG64( EX_4_CME_SCOM_SICR_PPE                                  , RULL(0x10B010500), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_SICR_PPE1                                 , RULL(0x10B010518), SH_UNT_EX_4     ,
+       SH_ACS_PPE1      );
+REG64( EX_4_CME_SCOM_SICR_PPE2                                 , RULL(0x10B010510), SH_UNT_EX_4     ,
+       SH_ACS_PPE2      );
+REG64( EX_4_CME_SCOM_SICR_SCOM                                 , RULL(0x1201203D), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_4_CME_SCOM_SICR_SCOM1                                , RULL(0x1201203E), SH_UNT_EX_4     , SH_ACS_SCOM1     );
+REG64( EX_4_CME_SCOM_SICR_SCOM2                                , RULL(0x1201203F), SH_UNT_EX_4     , SH_ACS_SCOM2     );
+REG64( EX_5_CME_SCOM_SICR_PPE                                  , RULL(0x10B020500), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_SICR_PPE1                                 , RULL(0x10B020518), SH_UNT_EX_5     ,
+       SH_ACS_PPE1      );
+REG64( EX_5_CME_SCOM_SICR_PPE2                                 , RULL(0x10B020510), SH_UNT_EX_5     ,
+       SH_ACS_PPE2      );
+REG64( EX_5_CME_SCOM_SICR_SCOM                                 , RULL(0x1201243D), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_5_CME_SCOM_SICR_SCOM1                                , RULL(0x1201243E), SH_UNT_EX_5     , SH_ACS_SCOM1     );
+REG64( EX_5_CME_SCOM_SICR_SCOM2                                , RULL(0x1201243F), SH_UNT_EX_5     , SH_ACS_SCOM2     );
+REG64( EX_6_CME_SCOM_SICR_PPE                                  , RULL(0x10C010500), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_SICR_PPE1                                 , RULL(0x10C010518), SH_UNT_EX_6     ,
+       SH_ACS_PPE1      );
+REG64( EX_6_CME_SCOM_SICR_PPE2                                 , RULL(0x10C010510), SH_UNT_EX_6     ,
+       SH_ACS_PPE2      );
+REG64( EX_6_CME_SCOM_SICR_SCOM                                 , RULL(0x1301203D), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_6_CME_SCOM_SICR_SCOM1                                , RULL(0x1301203E), SH_UNT_EX_6     , SH_ACS_SCOM1     );
+REG64( EX_6_CME_SCOM_SICR_SCOM2                                , RULL(0x1301203F), SH_UNT_EX_6     , SH_ACS_SCOM2     );
+REG64( EX_7_CME_SCOM_SICR_PPE                                  , RULL(0x10C020500), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_SICR_PPE1                                 , RULL(0x10C020518), SH_UNT_EX_7     ,
+       SH_ACS_PPE1      );
+REG64( EX_7_CME_SCOM_SICR_PPE2                                 , RULL(0x10C020510), SH_UNT_EX_7     ,
+       SH_ACS_PPE2      );
+REG64( EX_7_CME_SCOM_SICR_SCOM                                 , RULL(0x1301243D), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_7_CME_SCOM_SICR_SCOM1                                , RULL(0x1301243E), SH_UNT_EX_7     , SH_ACS_SCOM1     );
+REG64( EX_7_CME_SCOM_SICR_SCOM2                                , RULL(0x1301243F), SH_UNT_EX_7     , SH_ACS_SCOM2     );
+REG64( EX_8_CME_SCOM_SICR_PPE                                  , RULL(0x10D010500), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_SICR_PPE1                                 , RULL(0x10D010518), SH_UNT_EX_8     ,
+       SH_ACS_PPE1      );
+REG64( EX_8_CME_SCOM_SICR_PPE2                                 , RULL(0x10D010510), SH_UNT_EX_8     ,
+       SH_ACS_PPE2      );
+REG64( EX_8_CME_SCOM_SICR_SCOM                                 , RULL(0x1401203D), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_8_CME_SCOM_SICR_SCOM1                                , RULL(0x1401203E), SH_UNT_EX_8     , SH_ACS_SCOM1     );
+REG64( EX_8_CME_SCOM_SICR_SCOM2                                , RULL(0x1401203F), SH_UNT_EX_8     , SH_ACS_SCOM2     );
+REG64( EX_9_CME_SCOM_SICR_PPE                                  , RULL(0x10D020500), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_SICR_PPE1                                 , RULL(0x10D020518), SH_UNT_EX_9     ,
+       SH_ACS_PPE1      );
+REG64( EX_9_CME_SCOM_SICR_PPE2                                 , RULL(0x10D020510), SH_UNT_EX_9     ,
+       SH_ACS_PPE2      );
+REG64( EX_9_CME_SCOM_SICR_SCOM                                 , RULL(0x1401243D), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_9_CME_SCOM_SICR_SCOM1                                , RULL(0x1401243E), SH_UNT_EX_9     , SH_ACS_SCOM1     );
+REG64( EX_9_CME_SCOM_SICR_SCOM2                                , RULL(0x1401243F), SH_UNT_EX_9     , SH_ACS_SCOM2     );
+REG64( EX_10_CME_SCOM_SICR_PPE                                 , RULL(0x10E010500), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_SICR_PPE1                                , RULL(0x10E010518), SH_UNT_EX_10    ,
+       SH_ACS_PPE1      );
+REG64( EX_10_CME_SCOM_SICR_PPE2                                , RULL(0x10E010510), SH_UNT_EX_10    ,
+       SH_ACS_PPE2      );
+REG64( EX_10_CME_SCOM_SICR_SCOM                                , RULL(0x1501203D), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_10_CME_SCOM_SICR_SCOM1                               , RULL(0x1501203E), SH_UNT_EX_10    , SH_ACS_SCOM1     );
+REG64( EX_10_CME_SCOM_SICR_SCOM2                               , RULL(0x1501203F), SH_UNT_EX_10    , SH_ACS_SCOM2     );
+REG64( EX_11_CME_SCOM_SICR_PPE                                 , RULL(0x10E020500), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_SICR_PPE1                                , RULL(0x10E020518), SH_UNT_EX_11    ,
+       SH_ACS_PPE1      );
+REG64( EX_11_CME_SCOM_SICR_PPE2                                , RULL(0x10E020510), SH_UNT_EX_11    ,
+       SH_ACS_PPE2      );
+REG64( EX_11_CME_SCOM_SICR_SCOM                                , RULL(0x1501243D), SH_UNT_EX_11    , SH_ACS_SCOM      );
+REG64( EX_11_CME_SCOM_SICR_SCOM1                               , RULL(0x1501243E), SH_UNT_EX_11    , SH_ACS_SCOM1     );
+REG64( EX_11_CME_SCOM_SICR_SCOM2                               , RULL(0x1501243F), SH_UNT_EX_11    , SH_ACS_SCOM2     );
+
+REG64( EQ_CME_SCOM_SRTCH0                                      , RULL(0x10012423), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012023,
+REG64( EQ_0_CME_SCOM_SRTCH0                                    , RULL(0x10012423), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012023,
+REG64( EQ_1_CME_SCOM_SRTCH0                                    , RULL(0x11012423), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012023,
+REG64( EQ_2_CME_SCOM_SRTCH0                                    , RULL(0x12012423), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012023,
+REG64( EQ_3_CME_SCOM_SRTCH0                                    , RULL(0x13012423), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012023,
+REG64( EQ_4_CME_SCOM_SRTCH0                                    , RULL(0x14012423), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012023,
+REG64( EQ_5_CME_SCOM_SRTCH0                                    , RULL(0x15012423), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012023,
+REG64( EX_CME_SCOM_SRTCH0_PPE                                  , RULL(0x109010420), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_SRTCH0_SCOM                                 , RULL(0x10012023), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_SRTCH0_PPE                                , RULL(0x109010420), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_SRTCH0_SCOM                               , RULL(0x10012023), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_SRTCH0_PPE                                , RULL(0x109020420), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_SRTCH0_SCOM                               , RULL(0x10012423), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_SRTCH0_PPE                                , RULL(0x10A010420), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_SRTCH0_SCOM                               , RULL(0x11012023), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_SRTCH0_PPE                                , RULL(0x10A020420), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_SRTCH0_SCOM                               , RULL(0x11012423), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_SRTCH0_PPE                                , RULL(0x10B010420), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_SRTCH0_SCOM                               , RULL(0x12012023), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_SRTCH0_PPE                                , RULL(0x10B020420), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_SRTCH0_SCOM                               , RULL(0x12012423), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_SRTCH0_PPE                                , RULL(0x10C010420), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_SRTCH0_SCOM                               , RULL(0x13012023), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_SRTCH0_PPE                                , RULL(0x10C020420), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_SRTCH0_SCOM                               , RULL(0x13012423), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_SRTCH0_PPE                                , RULL(0x10D010420), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_SRTCH0_SCOM                               , RULL(0x14012023), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_SRTCH0_PPE                                , RULL(0x10D020420), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_SRTCH0_SCOM                               , RULL(0x14012423), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_SRTCH0_PPE                               , RULL(0x10E010420), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_SRTCH0_SCOM                              , RULL(0x15012023), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_SRTCH0_PPE                               , RULL(0x10E020420), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_SRTCH0_SCOM                              , RULL(0x15012423), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_SRTCH1                                      , RULL(0x10012424), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012024,
+REG64( EQ_0_CME_SCOM_SRTCH1                                    , RULL(0x10012424), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012024,
+REG64( EQ_1_CME_SCOM_SRTCH1                                    , RULL(0x11012424), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012024,
+REG64( EQ_2_CME_SCOM_SRTCH1                                    , RULL(0x12012424), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012024,
+REG64( EQ_3_CME_SCOM_SRTCH1                                    , RULL(0x13012424), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012024,
+REG64( EQ_4_CME_SCOM_SRTCH1                                    , RULL(0x14012424), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012024,
+REG64( EQ_5_CME_SCOM_SRTCH1                                    , RULL(0x15012424), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012024,
+REG64( EX_CME_SCOM_SRTCH1_PPE                                  , RULL(0x109010440), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_SRTCH1_SCOM                                 , RULL(0x10012024), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_SRTCH1_PPE                                , RULL(0x109010440), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_SRTCH1_SCOM                               , RULL(0x10012024), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_SRTCH1_PPE                                , RULL(0x109020440), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_SRTCH1_SCOM                               , RULL(0x10012424), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_SRTCH1_PPE                                , RULL(0x10A010440), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_SRTCH1_SCOM                               , RULL(0x11012024), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_SRTCH1_PPE                                , RULL(0x10A020440), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_SRTCH1_SCOM                               , RULL(0x11012424), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_SRTCH1_PPE                                , RULL(0x10B010440), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_SRTCH1_SCOM                               , RULL(0x12012024), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_SRTCH1_PPE                                , RULL(0x10B020440), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_SRTCH1_SCOM                               , RULL(0x12012424), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_SRTCH1_PPE                                , RULL(0x10C010440), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_SRTCH1_SCOM                               , RULL(0x13012024), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_SRTCH1_PPE                                , RULL(0x10C020440), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_SRTCH1_SCOM                               , RULL(0x13012424), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_SRTCH1_PPE                                , RULL(0x10D010440), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_SRTCH1_SCOM                               , RULL(0x14012024), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_SRTCH1_PPE                                , RULL(0x10D020440), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_SRTCH1_SCOM                               , RULL(0x14012424), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_SRTCH1_PPE                               , RULL(0x10E010440), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_SRTCH1_SCOM                              , RULL(0x15012024), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_SRTCH1_PPE                               , RULL(0x10E020440), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_SRTCH1_SCOM                              , RULL(0x15012424), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_VCCR                                        , RULL(0x1001242C), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001202C,
+REG64( EQ_0_CME_SCOM_VCCR                                      , RULL(0x1001242C), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001202C,
+REG64( EQ_1_CME_SCOM_VCCR                                      , RULL(0x1101242C), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1101202C,
+REG64( EQ_2_CME_SCOM_VCCR                                      , RULL(0x1201242C), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1201202C,
+REG64( EQ_3_CME_SCOM_VCCR                                      , RULL(0x1301242C), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1301202C,
+REG64( EQ_4_CME_SCOM_VCCR                                      , RULL(0x1401242C), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1401202C,
+REG64( EQ_5_CME_SCOM_VCCR                                      , RULL(0x1501242C), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1501202C,
+REG64( EX_CME_SCOM_VCCR_PPE                                    , RULL(0x109010680), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_VCCR_SCOM                                   , RULL(0x1001202C), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_VCCR_PPE                                  , RULL(0x109010680), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_VCCR_SCOM                                 , RULL(0x1001202C), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_VCCR_PPE                                  , RULL(0x109020680), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_VCCR_SCOM                                 , RULL(0x1001242C), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_VCCR_PPE                                  , RULL(0x10A010680), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_VCCR_SCOM                                 , RULL(0x1101202C), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_VCCR_PPE                                  , RULL(0x10A020680), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_VCCR_SCOM                                 , RULL(0x1101242C), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_VCCR_PPE                                  , RULL(0x10B010680), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_VCCR_SCOM                                 , RULL(0x1201202C), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_VCCR_PPE                                  , RULL(0x10B020680), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_VCCR_SCOM                                 , RULL(0x1201242C), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_VCCR_PPE                                  , RULL(0x10C010680), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_VCCR_SCOM                                 , RULL(0x1301202C), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_VCCR_PPE                                  , RULL(0x10C020680), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_VCCR_SCOM                                 , RULL(0x1301242C), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_VCCR_PPE                                  , RULL(0x10D010680), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_VCCR_SCOM                                 , RULL(0x1401202C), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_VCCR_PPE                                  , RULL(0x10D020680), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_VCCR_SCOM                                 , RULL(0x1401242C), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_VCCR_PPE                                 , RULL(0x10E010680), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_VCCR_SCOM                                , RULL(0x1501202C), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_VCCR_PPE                                 , RULL(0x10E020680), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_VCCR_SCOM                                , RULL(0x1501242C), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_VCTR                                        , RULL(0x10012439), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012039,
+REG64( EQ_0_CME_SCOM_VCTR                                      , RULL(0x10012439), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012039,
+REG64( EQ_1_CME_SCOM_VCTR                                      , RULL(0x11012439), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012039,
+REG64( EQ_2_CME_SCOM_VCTR                                      , RULL(0x12012439), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012039,
+REG64( EQ_3_CME_SCOM_VCTR                                      , RULL(0x13012439), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012039,
+REG64( EQ_4_CME_SCOM_VCTR                                      , RULL(0x14012439), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012039,
+REG64( EQ_5_CME_SCOM_VCTR                                      , RULL(0x15012439), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012039,
+REG64( EX_CME_SCOM_VCTR                                        , RULL(0x10012039), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CME_SCOM_VCTR                                      , RULL(0x10012039), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CME_SCOM_VCTR                                      , RULL(0x10012439), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CME_SCOM_VCTR                                      , RULL(0x11012039), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CME_SCOM_VCTR                                      , RULL(0x11012439), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CME_SCOM_VCTR                                      , RULL(0x12012039), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CME_SCOM_VCTR                                      , RULL(0x12012439), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CME_SCOM_VCTR                                      , RULL(0x13012039), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CME_SCOM_VCTR                                      , RULL(0x13012439), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CME_SCOM_VCTR                                      , RULL(0x14012039), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CME_SCOM_VCTR                                      , RULL(0x14012439), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CME_SCOM_VCTR                                     , RULL(0x15012039), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CME_SCOM_VCTR                                     , RULL(0x15012439), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CME_SCOM_VDCR                                        , RULL(0x10012435), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012035,
+REG64( EQ_0_CME_SCOM_VDCR                                      , RULL(0x10012435), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012035,
+REG64( EQ_1_CME_SCOM_VDCR                                      , RULL(0x11012435), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012035,
+REG64( EQ_2_CME_SCOM_VDCR                                      , RULL(0x12012435), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012035,
+REG64( EQ_3_CME_SCOM_VDCR                                      , RULL(0x13012435), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012035,
+REG64( EQ_4_CME_SCOM_VDCR                                      , RULL(0x14012435), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012035,
+REG64( EQ_5_CME_SCOM_VDCR                                      , RULL(0x15012435), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012035,
+REG64( EX_CME_SCOM_VDCR_PPE                                    , RULL(0x109010600), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_VDCR_SCOM                                   , RULL(0x10012035), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_SCOM_VDCR_PPE                                  , RULL(0x109010600), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_VDCR_SCOM                                 , RULL(0x10012035), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_SCOM_VDCR_PPE                                  , RULL(0x109020600), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_VDCR_SCOM                                 , RULL(0x10012435), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_SCOM_VDCR_PPE                                  , RULL(0x10A010600), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_VDCR_SCOM                                 , RULL(0x11012035), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_SCOM_VDCR_PPE                                  , RULL(0x10A020600), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_VDCR_SCOM                                 , RULL(0x11012435), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_SCOM_VDCR_PPE                                  , RULL(0x10B010600), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_VDCR_SCOM                                 , RULL(0x12012035), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_SCOM_VDCR_PPE                                  , RULL(0x10B020600), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_VDCR_SCOM                                 , RULL(0x12012435), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_SCOM_VDCR_PPE                                  , RULL(0x10C010600), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_VDCR_SCOM                                 , RULL(0x13012035), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_SCOM_VDCR_PPE                                  , RULL(0x10C020600), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_VDCR_SCOM                                 , RULL(0x13012435), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_SCOM_VDCR_PPE                                  , RULL(0x10D010600), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_VDCR_SCOM                                 , RULL(0x14012035), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_SCOM_VDCR_PPE                                  , RULL(0x10D020600), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_VDCR_SCOM                                 , RULL(0x14012435), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_SCOM_VDCR_PPE                                 , RULL(0x10E010600), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_VDCR_SCOM                                , RULL(0x15012035), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_SCOM_VDCR_PPE                                 , RULL(0x10E020600), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_VDCR_SCOM                                , RULL(0x15012435), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_SCOM_VDSR                                        , RULL(0x10012437), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012037,
+REG64( EQ_0_CME_SCOM_VDSR                                      , RULL(0x10012437), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012037,
+REG64( EQ_1_CME_SCOM_VDSR                                      , RULL(0x11012437), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012037,
+REG64( EQ_2_CME_SCOM_VDSR                                      , RULL(0x12012437), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012037,
+REG64( EQ_3_CME_SCOM_VDSR                                      , RULL(0x13012437), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012037,
+REG64( EQ_4_CME_SCOM_VDSR                                      , RULL(0x14012437), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012037,
+REG64( EQ_5_CME_SCOM_VDSR                                      , RULL(0x15012437), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012037,
+REG64( EX_CME_SCOM_VDSR_PPE                                    , RULL(0x109010640), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_VDSR_SCOM                                   , RULL(0x10012037), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_SCOM_VDSR_PPE                                  , RULL(0x109010640), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_VDSR_SCOM                                 , RULL(0x10012037), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_SCOM_VDSR_PPE                                  , RULL(0x109020640), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_VDSR_SCOM                                 , RULL(0x10012437), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_SCOM_VDSR_PPE                                  , RULL(0x10A010640), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_VDSR_SCOM                                 , RULL(0x11012037), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_SCOM_VDSR_PPE                                  , RULL(0x10A020640), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_VDSR_SCOM                                 , RULL(0x11012437), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_SCOM_VDSR_PPE                                  , RULL(0x10B010640), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_VDSR_SCOM                                 , RULL(0x12012037), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_SCOM_VDSR_PPE                                  , RULL(0x10B020640), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_VDSR_SCOM                                 , RULL(0x12012437), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_SCOM_VDSR_PPE                                  , RULL(0x10C010640), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_VDSR_SCOM                                 , RULL(0x13012037), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_SCOM_VDSR_PPE                                  , RULL(0x10C020640), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_VDSR_SCOM                                 , RULL(0x13012437), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_SCOM_VDSR_PPE                                  , RULL(0x10D010640), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_VDSR_SCOM                                 , RULL(0x14012037), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_SCOM_VDSR_PPE                                  , RULL(0x10D020640), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_VDSR_SCOM                                 , RULL(0x14012437), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_SCOM_VDSR_PPE                                 , RULL(0x10E010640), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_VDSR_SCOM                                , RULL(0x15012037), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_SCOM_VDSR_PPE                                 , RULL(0x10E020640), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_VDSR_SCOM                                , RULL(0x15012437), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_SCOM_VECR                                        , RULL(0x10012438), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012038,
+REG64( EQ_0_CME_SCOM_VECR                                      , RULL(0x10012438), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012038,
+REG64( EQ_1_CME_SCOM_VECR                                      , RULL(0x11012438), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012038,
+REG64( EQ_2_CME_SCOM_VECR                                      , RULL(0x12012438), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012038,
+REG64( EQ_3_CME_SCOM_VECR                                      , RULL(0x13012438), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012038,
+REG64( EQ_4_CME_SCOM_VECR                                      , RULL(0x14012438), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012038,
+REG64( EQ_5_CME_SCOM_VECR                                      , RULL(0x15012438), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012038,
+REG64( EX_CME_SCOM_VECR_PPE                                    , RULL(0x109010660), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_VECR_SCOM                                   , RULL(0x10012038), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_SCOM_VECR_PPE                                  , RULL(0x109010660), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_VECR_SCOM                                 , RULL(0x10012038), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_SCOM_VECR_PPE                                  , RULL(0x109020660), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_VECR_SCOM                                 , RULL(0x10012438), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_SCOM_VECR_PPE                                  , RULL(0x10A010660), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_VECR_SCOM                                 , RULL(0x11012038), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_SCOM_VECR_PPE                                  , RULL(0x10A020660), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_VECR_SCOM                                 , RULL(0x11012438), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_SCOM_VECR_PPE                                  , RULL(0x10B010660), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_VECR_SCOM                                 , RULL(0x12012038), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_SCOM_VECR_PPE                                  , RULL(0x10B020660), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_VECR_SCOM                                 , RULL(0x12012438), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_SCOM_VECR_PPE                                  , RULL(0x10C010660), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_VECR_SCOM                                 , RULL(0x13012038), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_SCOM_VECR_PPE                                  , RULL(0x10C020660), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_VECR_SCOM                                 , RULL(0x13012438), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_SCOM_VECR_PPE                                  , RULL(0x10D010660), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_VECR_SCOM                                 , RULL(0x14012038), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_SCOM_VECR_PPE                                  , RULL(0x10D020660), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_VECR_SCOM                                 , RULL(0x14012438), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_SCOM_VECR_PPE                                 , RULL(0x10E010660), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_VECR_SCOM                                , RULL(0x15012038), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_SCOM_VECR_PPE                                 , RULL(0x10E020660), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_VECR_SCOM                                , RULL(0x15012438), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_SCOM_VNCR                                        , RULL(0x10012436), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012036,
+REG64( EQ_0_CME_SCOM_VNCR                                      , RULL(0x10012436), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012036,
+REG64( EQ_1_CME_SCOM_VNCR                                      , RULL(0x11012436), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012036,
+REG64( EQ_2_CME_SCOM_VNCR                                      , RULL(0x12012436), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012036,
+REG64( EQ_3_CME_SCOM_VNCR                                      , RULL(0x13012436), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012036,
+REG64( EQ_4_CME_SCOM_VNCR                                      , RULL(0x14012436), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012036,
+REG64( EQ_5_CME_SCOM_VNCR                                      , RULL(0x15012436), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012036,
+REG64( EX_CME_SCOM_VNCR_PPE                                    , RULL(0x109010620), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_VNCR_SCOM                                   , RULL(0x10012036), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_SCOM_VNCR_PPE                                  , RULL(0x109010620), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_VNCR_SCOM                                 , RULL(0x10012036), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_SCOM_VNCR_PPE                                  , RULL(0x109020620), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_VNCR_SCOM                                 , RULL(0x10012436), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_SCOM_VNCR_PPE                                  , RULL(0x10A010620), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_VNCR_SCOM                                 , RULL(0x11012036), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_SCOM_VNCR_PPE                                  , RULL(0x10A020620), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_VNCR_SCOM                                 , RULL(0x11012436), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_SCOM_VNCR_PPE                                  , RULL(0x10B010620), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_VNCR_SCOM                                 , RULL(0x12012036), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_SCOM_VNCR_PPE                                  , RULL(0x10B020620), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_VNCR_SCOM                                 , RULL(0x12012436), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_SCOM_VNCR_PPE                                  , RULL(0x10C010620), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_VNCR_SCOM                                 , RULL(0x13012036), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_SCOM_VNCR_PPE                                  , RULL(0x10C020620), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_VNCR_SCOM                                 , RULL(0x13012436), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_SCOM_VNCR_PPE                                  , RULL(0x10D010620), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_VNCR_SCOM                                 , RULL(0x14012036), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_SCOM_VNCR_PPE                                  , RULL(0x10D020620), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_VNCR_SCOM                                 , RULL(0x14012436), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_SCOM_VNCR_PPE                                 , RULL(0x10E010620), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_VNCR_SCOM                                , RULL(0x15012036), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_SCOM_VNCR_PPE                                 , RULL(0x10E020620), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_VNCR_SCOM                                , RULL(0x15012436), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_SCOM_XIPCBMD0                                    , RULL(0x1001241C), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001201C,
+REG64( EQ_0_CME_SCOM_XIPCBMD0                                  , RULL(0x1001241C), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001201C,
+REG64( EQ_1_CME_SCOM_XIPCBMD0                                  , RULL(0x1101241C), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1101201C,
+REG64( EQ_2_CME_SCOM_XIPCBMD0                                  , RULL(0x1201241C), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1201201C,
+REG64( EQ_3_CME_SCOM_XIPCBMD0                                  , RULL(0x1301241C), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1301201C,
+REG64( EQ_4_CME_SCOM_XIPCBMD0                                  , RULL(0x1401241C), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1401201C,
+REG64( EQ_5_CME_SCOM_XIPCBMD0                                  , RULL(0x1501241C), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1501201C,
+REG64( EX_CME_SCOM_XIPCBMD0_PPE                                , RULL(0x109010580), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_XIPCBMD0_SCOM                               , RULL(0x1001201C), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_SCOM_XIPCBMD0_PPE                              , RULL(0x109010580), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_XIPCBMD0_SCOM                             , RULL(0x1001201C), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_SCOM_XIPCBMD0_PPE                              , RULL(0x109020580), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_XIPCBMD0_SCOM                             , RULL(0x1001241C), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_SCOM_XIPCBMD0_PPE                              , RULL(0x10A010580), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_XIPCBMD0_SCOM                             , RULL(0x1101201C), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_SCOM_XIPCBMD0_PPE                              , RULL(0x10A020580), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_XIPCBMD0_SCOM                             , RULL(0x1101241C), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_SCOM_XIPCBMD0_PPE                              , RULL(0x10B010580), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_XIPCBMD0_SCOM                             , RULL(0x1201201C), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_SCOM_XIPCBMD0_PPE                              , RULL(0x10B020580), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_XIPCBMD0_SCOM                             , RULL(0x1201241C), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_SCOM_XIPCBMD0_PPE                              , RULL(0x10C010580), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_XIPCBMD0_SCOM                             , RULL(0x1301201C), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_SCOM_XIPCBMD0_PPE                              , RULL(0x10C020580), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_XIPCBMD0_SCOM                             , RULL(0x1301241C), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_SCOM_XIPCBMD0_PPE                              , RULL(0x10D010580), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_XIPCBMD0_SCOM                             , RULL(0x1401201C), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_SCOM_XIPCBMD0_PPE                              , RULL(0x10D020580), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_XIPCBMD0_SCOM                             , RULL(0x1401241C), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_SCOM_XIPCBMD0_PPE                             , RULL(0x10E010580), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_XIPCBMD0_SCOM                            , RULL(0x1501201C), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_SCOM_XIPCBMD0_PPE                             , RULL(0x10E020580), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_XIPCBMD0_SCOM                            , RULL(0x1501241C), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_SCOM_XIPCBMD1                                    , RULL(0x1001241D), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001201D,
+REG64( EQ_0_CME_SCOM_XIPCBMD1                                  , RULL(0x1001241D), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001201D,
+REG64( EQ_1_CME_SCOM_XIPCBMD1                                  , RULL(0x1101241D), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1101201D,
+REG64( EQ_2_CME_SCOM_XIPCBMD1                                  , RULL(0x1201241D), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1201201D,
+REG64( EQ_3_CME_SCOM_XIPCBMD1                                  , RULL(0x1301241D), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1301201D,
+REG64( EQ_4_CME_SCOM_XIPCBMD1                                  , RULL(0x1401241D), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1401201D,
+REG64( EQ_5_CME_SCOM_XIPCBMD1                                  , RULL(0x1501241D), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1501201D,
+REG64( EX_CME_SCOM_XIPCBMD1_PPE                                , RULL(0x1090105A0), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_XIPCBMD1_SCOM                               , RULL(0x1001201D), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_SCOM_XIPCBMD1_PPE                              , RULL(0x1090105A0), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_XIPCBMD1_SCOM                             , RULL(0x1001201D), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_SCOM_XIPCBMD1_PPE                              , RULL(0x1090205A0), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_XIPCBMD1_SCOM                             , RULL(0x1001241D), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_SCOM_XIPCBMD1_PPE                              , RULL(0x10A0105A0), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_XIPCBMD1_SCOM                             , RULL(0x1101201D), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_SCOM_XIPCBMD1_PPE                              , RULL(0x10A0205A0), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_XIPCBMD1_SCOM                             , RULL(0x1101241D), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_SCOM_XIPCBMD1_PPE                              , RULL(0x10B0105A0), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_XIPCBMD1_SCOM                             , RULL(0x1201201D), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_SCOM_XIPCBMD1_PPE                              , RULL(0x10B0205A0), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_XIPCBMD1_SCOM                             , RULL(0x1201241D), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_SCOM_XIPCBMD1_PPE                              , RULL(0x10C0105A0), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_XIPCBMD1_SCOM                             , RULL(0x1301201D), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_SCOM_XIPCBMD1_PPE                              , RULL(0x10C0205A0), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_XIPCBMD1_SCOM                             , RULL(0x1301241D), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_SCOM_XIPCBMD1_PPE                              , RULL(0x10D0105A0), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_XIPCBMD1_SCOM                             , RULL(0x1401201D), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_SCOM_XIPCBMD1_PPE                              , RULL(0x10D0205A0), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_XIPCBMD1_SCOM                             , RULL(0x1401241D), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_SCOM_XIPCBMD1_PPE                             , RULL(0x10E0105A0), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_XIPCBMD1_SCOM                            , RULL(0x1501201D), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_SCOM_XIPCBMD1_PPE                             , RULL(0x10E0205A0), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_XIPCBMD1_SCOM                            , RULL(0x1501241D), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_SCOM_XIPCBMI0                                    , RULL(0x1001241E), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001201E,
+REG64( EQ_0_CME_SCOM_XIPCBMI0                                  , RULL(0x1001241E), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001201E,
+REG64( EQ_1_CME_SCOM_XIPCBMI0                                  , RULL(0x1101241E), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1101201E,
+REG64( EQ_2_CME_SCOM_XIPCBMI0                                  , RULL(0x1201241E), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1201201E,
+REG64( EQ_3_CME_SCOM_XIPCBMI0                                  , RULL(0x1301241E), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1301201E,
+REG64( EQ_4_CME_SCOM_XIPCBMI0                                  , RULL(0x1401241E), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1401201E,
+REG64( EQ_5_CME_SCOM_XIPCBMI0                                  , RULL(0x1501241E), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1501201E,
+REG64( EX_CME_SCOM_XIPCBMI0_PPE                                , RULL(0x1090105C0), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_XIPCBMI0_SCOM                               , RULL(0x1001201E), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_SCOM_XIPCBMI0_PPE                              , RULL(0x1090105C0), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_XIPCBMI0_SCOM                             , RULL(0x1001201E), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_SCOM_XIPCBMI0_PPE                              , RULL(0x1090205C0), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_XIPCBMI0_SCOM                             , RULL(0x1001241E), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_SCOM_XIPCBMI0_PPE                              , RULL(0x10A0105C0), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_XIPCBMI0_SCOM                             , RULL(0x1101201E), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_SCOM_XIPCBMI0_PPE                              , RULL(0x10A0205C0), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_XIPCBMI0_SCOM                             , RULL(0x1101241E), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_SCOM_XIPCBMI0_PPE                              , RULL(0x10B0105C0), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_XIPCBMI0_SCOM                             , RULL(0x1201201E), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_SCOM_XIPCBMI0_PPE                              , RULL(0x10B0205C0), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_XIPCBMI0_SCOM                             , RULL(0x1201241E), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_SCOM_XIPCBMI0_PPE                              , RULL(0x10C0105C0), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_XIPCBMI0_SCOM                             , RULL(0x1301201E), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_SCOM_XIPCBMI0_PPE                              , RULL(0x10C0205C0), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_XIPCBMI0_SCOM                             , RULL(0x1301241E), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_SCOM_XIPCBMI0_PPE                              , RULL(0x10D0105C0), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_XIPCBMI0_SCOM                             , RULL(0x1401201E), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_SCOM_XIPCBMI0_PPE                              , RULL(0x10D0205C0), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_XIPCBMI0_SCOM                             , RULL(0x1401241E), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_SCOM_XIPCBMI0_PPE                             , RULL(0x10E0105C0), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_XIPCBMI0_SCOM                            , RULL(0x1501201E), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_SCOM_XIPCBMI0_PPE                             , RULL(0x10E0205C0), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_XIPCBMI0_SCOM                            , RULL(0x1501241E), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_SCOM_XIPCBMI1                                    , RULL(0x1001241F), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001201F,
+REG64( EQ_0_CME_SCOM_XIPCBMI1                                  , RULL(0x1001241F), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001201F,
+REG64( EQ_1_CME_SCOM_XIPCBMI1                                  , RULL(0x1101241F), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1101201F,
+REG64( EQ_2_CME_SCOM_XIPCBMI1                                  , RULL(0x1201241F), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1201201F,
+REG64( EQ_3_CME_SCOM_XIPCBMI1                                  , RULL(0x1301241F), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1301201F,
+REG64( EQ_4_CME_SCOM_XIPCBMI1                                  , RULL(0x1401241F), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1401201F,
+REG64( EQ_5_CME_SCOM_XIPCBMI1                                  , RULL(0x1501241F), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1501201F,
+REG64( EX_CME_SCOM_XIPCBMI1_PPE                                , RULL(0x1090105E0), SH_UNT_EX       ,
+       SH_ACS_PPE       );
+REG64( EX_CME_SCOM_XIPCBMI1_SCOM                               , RULL(0x1001201F), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_SCOM_XIPCBMI1_PPE                              , RULL(0x1090105E0), SH_UNT_EX_0     ,
+       SH_ACS_PPE       );
+REG64( EX_0_CME_SCOM_XIPCBMI1_SCOM                             , RULL(0x1001201F), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_SCOM_XIPCBMI1_PPE                              , RULL(0x1090205E0), SH_UNT_EX_1     ,
+       SH_ACS_PPE       );
+REG64( EX_1_CME_SCOM_XIPCBMI1_SCOM                             , RULL(0x1001241F), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_SCOM_XIPCBMI1_PPE                              , RULL(0x10A0105E0), SH_UNT_EX_2     ,
+       SH_ACS_PPE       );
+REG64( EX_2_CME_SCOM_XIPCBMI1_SCOM                             , RULL(0x1101201F), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_SCOM_XIPCBMI1_PPE                              , RULL(0x10A0205E0), SH_UNT_EX_3     ,
+       SH_ACS_PPE       );
+REG64( EX_3_CME_SCOM_XIPCBMI1_SCOM                             , RULL(0x1101241F), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_SCOM_XIPCBMI1_PPE                              , RULL(0x10B0105E0), SH_UNT_EX_4     ,
+       SH_ACS_PPE       );
+REG64( EX_4_CME_SCOM_XIPCBMI1_SCOM                             , RULL(0x1201201F), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_SCOM_XIPCBMI1_PPE                              , RULL(0x10B0205E0), SH_UNT_EX_5     ,
+       SH_ACS_PPE       );
+REG64( EX_5_CME_SCOM_XIPCBMI1_SCOM                             , RULL(0x1201241F), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_SCOM_XIPCBMI1_PPE                              , RULL(0x10C0105E0), SH_UNT_EX_6     ,
+       SH_ACS_PPE       );
+REG64( EX_6_CME_SCOM_XIPCBMI1_SCOM                             , RULL(0x1301201F), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_SCOM_XIPCBMI1_PPE                              , RULL(0x10C0205E0), SH_UNT_EX_7     ,
+       SH_ACS_PPE       );
+REG64( EX_7_CME_SCOM_XIPCBMI1_SCOM                             , RULL(0x1301241F), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_SCOM_XIPCBMI1_PPE                              , RULL(0x10D0105E0), SH_UNT_EX_8     ,
+       SH_ACS_PPE       );
+REG64( EX_8_CME_SCOM_XIPCBMI1_SCOM                             , RULL(0x1401201F), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_SCOM_XIPCBMI1_PPE                              , RULL(0x10D0205E0), SH_UNT_EX_9     ,
+       SH_ACS_PPE       );
+REG64( EX_9_CME_SCOM_XIPCBMI1_SCOM                             , RULL(0x1401241F), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_SCOM_XIPCBMI1_PPE                             , RULL(0x10E0105E0), SH_UNT_EX_10    ,
+       SH_ACS_PPE       );
+REG64( EX_10_CME_SCOM_XIPCBMI1_SCOM                            , RULL(0x1501201F), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_SCOM_XIPCBMI1_PPE                             , RULL(0x10E0205E0), SH_UNT_EX_11    ,
+       SH_ACS_PPE       );
+REG64( EX_11_CME_SCOM_XIPCBMI1_SCOM                            , RULL(0x1501241F), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_SCOM_XIPCBQ0                                     , RULL(0x1001241A), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001201A,
+REG64( EQ_0_CME_SCOM_XIPCBQ0                                   , RULL(0x1001241A), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001201A,
+REG64( EQ_1_CME_SCOM_XIPCBQ0                                   , RULL(0x1101241A), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1101201A,
+REG64( EQ_2_CME_SCOM_XIPCBQ0                                   , RULL(0x1201241A), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1201201A,
+REG64( EQ_3_CME_SCOM_XIPCBQ0                                   , RULL(0x1301241A), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1301201A,
+REG64( EQ_4_CME_SCOM_XIPCBQ0                                   , RULL(0x1401241A), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1401201A,
+REG64( EQ_5_CME_SCOM_XIPCBQ0                                   , RULL(0x1501241A), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1501201A,
+REG64( EX_CME_SCOM_XIPCBQ0                                     , RULL(0x1001201A), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_SCOM_XIPCBQ0                                   , RULL(0x1001201A), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_SCOM_XIPCBQ0                                   , RULL(0x1001241A), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_SCOM_XIPCBQ0                                   , RULL(0x1101201A), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_SCOM_XIPCBQ0                                   , RULL(0x1101241A), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_SCOM_XIPCBQ0                                   , RULL(0x1201201A), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_SCOM_XIPCBQ0                                   , RULL(0x1201241A), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_SCOM_XIPCBQ0                                   , RULL(0x1301201A), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_SCOM_XIPCBQ0                                   , RULL(0x1301241A), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_SCOM_XIPCBQ0                                   , RULL(0x1401201A), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_SCOM_XIPCBQ0                                   , RULL(0x1401241A), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_SCOM_XIPCBQ0                                  , RULL(0x1501201A), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_SCOM_XIPCBQ0                                  , RULL(0x1501241A), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_CME_SCOM_XIPCBQ1                                     , RULL(0x1001241B), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001201B,
+REG64( EQ_0_CME_SCOM_XIPCBQ1                                   , RULL(0x1001241B), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001201B,
+REG64( EQ_1_CME_SCOM_XIPCBQ1                                   , RULL(0x1101241B), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1101201B,
+REG64( EQ_2_CME_SCOM_XIPCBQ1                                   , RULL(0x1201241B), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1201201B,
+REG64( EQ_3_CME_SCOM_XIPCBQ1                                   , RULL(0x1301241B), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1301201B,
+REG64( EQ_4_CME_SCOM_XIPCBQ1                                   , RULL(0x1401241B), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1401201B,
+REG64( EQ_5_CME_SCOM_XIPCBQ1                                   , RULL(0x1501241B), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1501201B,
+REG64( EX_CME_SCOM_XIPCBQ1                                     , RULL(0x1001201B), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_CME_SCOM_XIPCBQ1                                   , RULL(0x1001201B), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_CME_SCOM_XIPCBQ1                                   , RULL(0x1001241B), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_CME_SCOM_XIPCBQ1                                   , RULL(0x1101201B), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_CME_SCOM_XIPCBQ1                                   , RULL(0x1101241B), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_CME_SCOM_XIPCBQ1                                   , RULL(0x1201201B), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_CME_SCOM_XIPCBQ1                                   , RULL(0x1201241B), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_CME_SCOM_XIPCBQ1                                   , RULL(0x1301201B), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_CME_SCOM_XIPCBQ1                                   , RULL(0x1301241B), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_CME_SCOM_XIPCBQ1                                   , RULL(0x1401201B), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_CME_SCOM_XIPCBQ1                                   , RULL(0x1401241B), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_CME_SCOM_XIPCBQ1                                  , RULL(0x1501201B), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_CME_SCOM_XIPCBQ1                                  , RULL(0x1501241B), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( C_CONTROL_REG                                           , RULL(0x20050012), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_CONTROL_REG                                         , RULL(0x20050012), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_CONTROL_REG                                         , RULL(0x21050012), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_CONTROL_REG                                         , RULL(0x22050012), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_CONTROL_REG                                         , RULL(0x23050012), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_CONTROL_REG                                         , RULL(0x24050012), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_CONTROL_REG                                         , RULL(0x25050012), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_CONTROL_REG                                         , RULL(0x26050012), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_CONTROL_REG                                         , RULL(0x27050012), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_CONTROL_REG                                         , RULL(0x28050012), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_CONTROL_REG                                         , RULL(0x29050012), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_CONTROL_REG                                        , RULL(0x2A050012), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_CONTROL_REG                                        , RULL(0x2B050012), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_CONTROL_REG                                        , RULL(0x2C050012), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_CONTROL_REG                                        , RULL(0x2D050012), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_CONTROL_REG                                        , RULL(0x2E050012), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_CONTROL_REG                                        , RULL(0x2F050012), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_CONTROL_REG                                        , RULL(0x30050012), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_CONTROL_REG                                        , RULL(0x31050012), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_CONTROL_REG                                        , RULL(0x32050012), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_CONTROL_REG                                        , RULL(0x33050012), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_CONTROL_REG                                        , RULL(0x34050012), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_CONTROL_REG                                        , RULL(0x35050012), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_CONTROL_REG                                        , RULL(0x36050012), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_CONTROL_REG                                        , RULL(0x37050012), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_CONTROL_REG                                          , RULL(0x10050012), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_CONTROL_REG                                        , RULL(0x10050012), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_CONTROL_REG                                        , RULL(0x11050012), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_CONTROL_REG                                        , RULL(0x12050012), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_CONTROL_REG                                        , RULL(0x13050012), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_CONTROL_REG                                        , RULL(0x14050012), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_CONTROL_REG                                        , RULL(0x15050012), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_CONTROL_REG                                          , RULL(0x20050012), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21050012,
+REG64( EX_0_CONTROL_REG                                        , RULL(0x20050012), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21050012,
+REG64( EX_1_CONTROL_REG                                        , RULL(0x22050012), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23050012,
+REG64( EX_2_CONTROL_REG                                        , RULL(0x24050012), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25050012,
+REG64( EX_3_CONTROL_REG                                        , RULL(0x26050012), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27050012,
+REG64( EX_4_CONTROL_REG                                        , RULL(0x28050012), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29050012,
+REG64( EX_5_CONTROL_REG                                        , RULL(0x2A050012), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B050012,
+REG64( EX_6_CONTROL_REG                                        , RULL(0x2C050012), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D050012,
+REG64( EX_7_CONTROL_REG                                        , RULL(0x2E050012), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F050012,
+REG64( EX_8_CONTROL_REG                                        , RULL(0x30050012), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31050012,
+REG64( EX_9_CONTROL_REG                                        , RULL(0x32050012), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33050012,
+REG64( EX_10_CONTROL_REG                                       , RULL(0x34050012), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35050012,
+REG64( EX_11_CONTROL_REG                                       , RULL(0x36050012), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37050012,
+
+REG64( C_CORE_ACTION0                                          , RULL(0x20010A46), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_CORE_ACTION0                                        , RULL(0x20010A46), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_CORE_ACTION0                                        , RULL(0x21010A46), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_CORE_ACTION0                                        , RULL(0x22010A46), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_CORE_ACTION0                                        , RULL(0x23010A46), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_CORE_ACTION0                                        , RULL(0x24010A46), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_CORE_ACTION0                                        , RULL(0x25010A46), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_CORE_ACTION0                                        , RULL(0x26010A46), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_CORE_ACTION0                                        , RULL(0x27010A46), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_CORE_ACTION0                                        , RULL(0x28010A46), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_CORE_ACTION0                                        , RULL(0x29010A46), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_CORE_ACTION0                                       , RULL(0x2A010A46), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_CORE_ACTION0                                       , RULL(0x2B010A46), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_CORE_ACTION0                                       , RULL(0x2C010A46), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_CORE_ACTION0                                       , RULL(0x2D010A46), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_CORE_ACTION0                                       , RULL(0x2E010A46), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_CORE_ACTION0                                       , RULL(0x2F010A46), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_CORE_ACTION0                                       , RULL(0x30010A46), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_CORE_ACTION0                                       , RULL(0x31010A46), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_CORE_ACTION0                                       , RULL(0x32010A46), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_CORE_ACTION0                                       , RULL(0x33010A46), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_CORE_ACTION0                                       , RULL(0x34010A46), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_CORE_ACTION0                                       , RULL(0x35010A46), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_CORE_ACTION0                                       , RULL(0x36010A46), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_CORE_ACTION0                                       , RULL(0x37010A46), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_CORE_ACTION0                                    , RULL(0x20010A46), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A46,
+REG64( EX_10_L2_CORE_ACTION0                                   , RULL(0x34010A46), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010A46,
+REG64( EX_11_L2_CORE_ACTION0                                   , RULL(0x36010A46), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010A46,
+REG64( EX_1_L2_CORE_ACTION0                                    , RULL(0x22010A46), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010A46,
+REG64( EX_2_L2_CORE_ACTION0                                    , RULL(0x24010A46), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010A46,
+REG64( EX_3_L2_CORE_ACTION0                                    , RULL(0x26010A46), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010A46,
+REG64( EX_4_L2_CORE_ACTION0                                    , RULL(0x28010A46), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010A46,
+REG64( EX_5_L2_CORE_ACTION0                                    , RULL(0x2A010A46), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010A46,
+REG64( EX_6_L2_CORE_ACTION0                                    , RULL(0x2C010A46), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010A46,
+REG64( EX_7_L2_CORE_ACTION0                                    , RULL(0x2E010A46), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010A46,
+REG64( EX_8_L2_CORE_ACTION0                                    , RULL(0x30010A46), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010A46,
+REG64( EX_9_L2_CORE_ACTION0                                    , RULL(0x32010A46), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010A46,
+REG64( EX_L2_CORE_ACTION0                                      , RULL(0x20010A46), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A46,
+
+REG64( C_CORE_ACTION1                                          , RULL(0x20010A47), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_CORE_ACTION1                                        , RULL(0x20010A47), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_CORE_ACTION1                                        , RULL(0x21010A47), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_CORE_ACTION1                                        , RULL(0x22010A47), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_CORE_ACTION1                                        , RULL(0x23010A47), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_CORE_ACTION1                                        , RULL(0x24010A47), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_CORE_ACTION1                                        , RULL(0x25010A47), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_CORE_ACTION1                                        , RULL(0x26010A47), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_CORE_ACTION1                                        , RULL(0x27010A47), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_CORE_ACTION1                                        , RULL(0x28010A47), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_CORE_ACTION1                                        , RULL(0x29010A47), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_CORE_ACTION1                                       , RULL(0x2A010A47), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_CORE_ACTION1                                       , RULL(0x2B010A47), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_CORE_ACTION1                                       , RULL(0x2C010A47), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_CORE_ACTION1                                       , RULL(0x2D010A47), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_CORE_ACTION1                                       , RULL(0x2E010A47), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_CORE_ACTION1                                       , RULL(0x2F010A47), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_CORE_ACTION1                                       , RULL(0x30010A47), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_CORE_ACTION1                                       , RULL(0x31010A47), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_CORE_ACTION1                                       , RULL(0x32010A47), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_CORE_ACTION1                                       , RULL(0x33010A47), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_CORE_ACTION1                                       , RULL(0x34010A47), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_CORE_ACTION1                                       , RULL(0x35010A47), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_CORE_ACTION1                                       , RULL(0x36010A47), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_CORE_ACTION1                                       , RULL(0x37010A47), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_CORE_ACTION1                                    , RULL(0x20010A47), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A47,
+REG64( EX_10_L2_CORE_ACTION1                                   , RULL(0x34010A47), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010A47,
+REG64( EX_11_L2_CORE_ACTION1                                   , RULL(0x36010A47), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010A47,
+REG64( EX_1_L2_CORE_ACTION1                                    , RULL(0x22010A47), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010A47,
+REG64( EX_2_L2_CORE_ACTION1                                    , RULL(0x24010A47), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010A47,
+REG64( EX_3_L2_CORE_ACTION1                                    , RULL(0x26010A47), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010A47,
+REG64( EX_4_L2_CORE_ACTION1                                    , RULL(0x28010A47), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010A47,
+REG64( EX_5_L2_CORE_ACTION1                                    , RULL(0x2A010A47), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010A47,
+REG64( EX_6_L2_CORE_ACTION1                                    , RULL(0x2C010A47), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010A47,
+REG64( EX_7_L2_CORE_ACTION1                                    , RULL(0x2E010A47), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010A47,
+REG64( EX_8_L2_CORE_ACTION1                                    , RULL(0x30010A47), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010A47,
+REG64( EX_9_L2_CORE_ACTION1                                    , RULL(0x32010A47), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010A47,
+REG64( EX_L2_CORE_ACTION1                                      , RULL(0x20010A47), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A47,
+
+REG64( C_CORE_FIR                                              , RULL(0x20010A40), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_CORE_FIR_AND                                          , RULL(0x20010A41), SH_UNT_C        , SH_ACS_SCOM1_AND );
+REG64( C_CORE_FIR_OR                                           , RULL(0x20010A42), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_CORE_FIR                                            , RULL(0x20010A40), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_CORE_FIR_AND                                        , RULL(0x20010A41), SH_UNT_C_0      , SH_ACS_SCOM1_AND );
+REG64( C_0_CORE_FIR_OR                                         , RULL(0x20010A42), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_CORE_FIR                                            , RULL(0x21010A40), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_CORE_FIR_AND                                        , RULL(0x21010A41), SH_UNT_C_1      , SH_ACS_SCOM1_AND );
+REG64( C_1_CORE_FIR_OR                                         , RULL(0x21010A42), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_CORE_FIR                                            , RULL(0x22010A40), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_CORE_FIR_AND                                        , RULL(0x22010A41), SH_UNT_C_2      , SH_ACS_SCOM1_AND );
+REG64( C_2_CORE_FIR_OR                                         , RULL(0x22010A42), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_CORE_FIR                                            , RULL(0x23010A40), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_CORE_FIR_AND                                        , RULL(0x23010A41), SH_UNT_C_3      , SH_ACS_SCOM1_AND );
+REG64( C_3_CORE_FIR_OR                                         , RULL(0x23010A42), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_CORE_FIR                                            , RULL(0x24010A40), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_CORE_FIR_AND                                        , RULL(0x24010A41), SH_UNT_C_4      , SH_ACS_SCOM1_AND );
+REG64( C_4_CORE_FIR_OR                                         , RULL(0x24010A42), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_CORE_FIR                                            , RULL(0x25010A40), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_CORE_FIR_AND                                        , RULL(0x25010A41), SH_UNT_C_5      , SH_ACS_SCOM1_AND );
+REG64( C_5_CORE_FIR_OR                                         , RULL(0x25010A42), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_CORE_FIR                                            , RULL(0x26010A40), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_CORE_FIR_AND                                        , RULL(0x26010A41), SH_UNT_C_6      , SH_ACS_SCOM1_AND );
+REG64( C_6_CORE_FIR_OR                                         , RULL(0x26010A42), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_CORE_FIR                                            , RULL(0x27010A40), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_CORE_FIR_AND                                        , RULL(0x27010A41), SH_UNT_C_7      , SH_ACS_SCOM1_AND );
+REG64( C_7_CORE_FIR_OR                                         , RULL(0x27010A42), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_CORE_FIR                                            , RULL(0x28010A40), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_CORE_FIR_AND                                        , RULL(0x28010A41), SH_UNT_C_8      , SH_ACS_SCOM1_AND );
+REG64( C_8_CORE_FIR_OR                                         , RULL(0x28010A42), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_CORE_FIR                                            , RULL(0x29010A40), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_CORE_FIR_AND                                        , RULL(0x29010A41), SH_UNT_C_9      , SH_ACS_SCOM1_AND );
+REG64( C_9_CORE_FIR_OR                                         , RULL(0x29010A42), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_CORE_FIR                                           , RULL(0x2A010A40), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_CORE_FIR_AND                                       , RULL(0x2A010A41), SH_UNT_C_10     , SH_ACS_SCOM1_AND );
+REG64( C_10_CORE_FIR_OR                                        , RULL(0x2A010A42), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_CORE_FIR                                           , RULL(0x2B010A40), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_CORE_FIR_AND                                       , RULL(0x2B010A41), SH_UNT_C_11     , SH_ACS_SCOM1_AND );
+REG64( C_11_CORE_FIR_OR                                        , RULL(0x2B010A42), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_CORE_FIR                                           , RULL(0x2C010A40), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_CORE_FIR_AND                                       , RULL(0x2C010A41), SH_UNT_C_12     , SH_ACS_SCOM1_AND );
+REG64( C_12_CORE_FIR_OR                                        , RULL(0x2C010A42), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_CORE_FIR                                           , RULL(0x2D010A40), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_CORE_FIR_AND                                       , RULL(0x2D010A41), SH_UNT_C_13     , SH_ACS_SCOM1_AND );
+REG64( C_13_CORE_FIR_OR                                        , RULL(0x2D010A42), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_CORE_FIR                                           , RULL(0x2E010A40), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_CORE_FIR_AND                                       , RULL(0x2E010A41), SH_UNT_C_14     , SH_ACS_SCOM1_AND );
+REG64( C_14_CORE_FIR_OR                                        , RULL(0x2E010A42), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_CORE_FIR                                           , RULL(0x2F010A40), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_CORE_FIR_AND                                       , RULL(0x2F010A41), SH_UNT_C_15     , SH_ACS_SCOM1_AND );
+REG64( C_15_CORE_FIR_OR                                        , RULL(0x2F010A42), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_CORE_FIR                                           , RULL(0x30010A40), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_CORE_FIR_AND                                       , RULL(0x30010A41), SH_UNT_C_16     , SH_ACS_SCOM1_AND );
+REG64( C_16_CORE_FIR_OR                                        , RULL(0x30010A42), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_CORE_FIR                                           , RULL(0x31010A40), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_CORE_FIR_AND                                       , RULL(0x31010A41), SH_UNT_C_17     , SH_ACS_SCOM1_AND );
+REG64( C_17_CORE_FIR_OR                                        , RULL(0x31010A42), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_CORE_FIR                                           , RULL(0x32010A40), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_CORE_FIR_AND                                       , RULL(0x32010A41), SH_UNT_C_18     , SH_ACS_SCOM1_AND );
+REG64( C_18_CORE_FIR_OR                                        , RULL(0x32010A42), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_CORE_FIR                                           , RULL(0x33010A40), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_CORE_FIR_AND                                       , RULL(0x33010A41), SH_UNT_C_19     , SH_ACS_SCOM1_AND );
+REG64( C_19_CORE_FIR_OR                                        , RULL(0x33010A42), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_CORE_FIR                                           , RULL(0x34010A40), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_CORE_FIR_AND                                       , RULL(0x34010A41), SH_UNT_C_20     , SH_ACS_SCOM1_AND );
+REG64( C_20_CORE_FIR_OR                                        , RULL(0x34010A42), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_CORE_FIR                                           , RULL(0x35010A40), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_CORE_FIR_AND                                       , RULL(0x35010A41), SH_UNT_C_21     , SH_ACS_SCOM1_AND );
+REG64( C_21_CORE_FIR_OR                                        , RULL(0x35010A42), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_CORE_FIR                                           , RULL(0x36010A40), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_CORE_FIR_AND                                       , RULL(0x36010A41), SH_UNT_C_22     , SH_ACS_SCOM1_AND );
+REG64( C_22_CORE_FIR_OR                                        , RULL(0x36010A42), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_CORE_FIR                                           , RULL(0x37010A40), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_CORE_FIR_AND                                       , RULL(0x37010A41), SH_UNT_C_23     , SH_ACS_SCOM1_AND );
+REG64( C_23_CORE_FIR_OR                                        , RULL(0x37010A42), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EX_0_L2_CORE_FIR                                        , RULL(0x20010A40), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A40,
+REG64( EX_0_L2_CORE_FIR_AND                                    , RULL(0x20010A41), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 21010A41,
+REG64( EX_0_L2_CORE_FIR_OR                                     , RULL(0x20010A42), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 21010A42,
+REG64( EX_10_L2_CORE_FIR                                       , RULL(0x34010A40), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010A40,
+REG64( EX_10_L2_CORE_FIR_AND                                   , RULL(0x34010A41), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM1_AND ); //DUPS: 35010A41,
+REG64( EX_10_L2_CORE_FIR_OR                                    , RULL(0x34010A42), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 35010A42,
+REG64( EX_11_L2_CORE_FIR                                       , RULL(0x36010A40), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010A40,
+REG64( EX_11_L2_CORE_FIR_AND                                   , RULL(0x36010A41), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM1_AND ); //DUPS: 37010A41,
+REG64( EX_11_L2_CORE_FIR_OR                                    , RULL(0x36010A42), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 37010A42,
+REG64( EX_1_L2_CORE_FIR                                        , RULL(0x22010A40), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010A40,
+REG64( EX_1_L2_CORE_FIR_AND                                    , RULL(0x22010A41), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 23010A41,
+REG64( EX_1_L2_CORE_FIR_OR                                     , RULL(0x22010A42), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 23010A42,
+REG64( EX_2_L2_CORE_FIR                                        , RULL(0x24010A40), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010A40,
+REG64( EX_2_L2_CORE_FIR_AND                                    , RULL(0x24010A41), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 25010A41,
+REG64( EX_2_L2_CORE_FIR_OR                                     , RULL(0x24010A42), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 25010A42,
+REG64( EX_3_L2_CORE_FIR                                        , RULL(0x26010A40), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010A40,
+REG64( EX_3_L2_CORE_FIR_AND                                    , RULL(0x26010A41), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 27010A41,
+REG64( EX_3_L2_CORE_FIR_OR                                     , RULL(0x26010A42), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 27010A42,
+REG64( EX_4_L2_CORE_FIR                                        , RULL(0x28010A40), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010A40,
+REG64( EX_4_L2_CORE_FIR_AND                                    , RULL(0x28010A41), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 29010A41,
+REG64( EX_4_L2_CORE_FIR_OR                                     , RULL(0x28010A42), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 29010A42,
+REG64( EX_5_L2_CORE_FIR                                        , RULL(0x2A010A40), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010A40,
+REG64( EX_5_L2_CORE_FIR_AND                                    , RULL(0x2A010A41), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2B010A41,
+REG64( EX_5_L2_CORE_FIR_OR                                     , RULL(0x2A010A42), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2B010A42,
+REG64( EX_6_L2_CORE_FIR                                        , RULL(0x2C010A40), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010A40,
+REG64( EX_6_L2_CORE_FIR_AND                                    , RULL(0x2C010A41), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2D010A41,
+REG64( EX_6_L2_CORE_FIR_OR                                     , RULL(0x2C010A42), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2D010A42,
+REG64( EX_7_L2_CORE_FIR                                        , RULL(0x2E010A40), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010A40,
+REG64( EX_7_L2_CORE_FIR_AND                                    , RULL(0x2E010A41), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2F010A41,
+REG64( EX_7_L2_CORE_FIR_OR                                     , RULL(0x2E010A42), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2F010A42,
+REG64( EX_8_L2_CORE_FIR                                        , RULL(0x30010A40), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010A40,
+REG64( EX_8_L2_CORE_FIR_AND                                    , RULL(0x30010A41), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 31010A41,
+REG64( EX_8_L2_CORE_FIR_OR                                     , RULL(0x30010A42), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 31010A42,
+REG64( EX_9_L2_CORE_FIR                                        , RULL(0x32010A40), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010A40,
+REG64( EX_9_L2_CORE_FIR_AND                                    , RULL(0x32010A41), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 33010A41,
+REG64( EX_9_L2_CORE_FIR_OR                                     , RULL(0x32010A42), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 33010A42,
+REG64( EX_L2_CORE_FIR                                          , RULL(0x20010A40), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A40,
+REG64( EX_L2_CORE_FIR_AND                                      , RULL(0x20010A41), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM1_AND ); //DUPS: 21010A41,
+REG64( EX_L2_CORE_FIR_OR                                       , RULL(0x20010A42), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 21010A42,
+
+REG64( C_CORE_FIRMASK                                          , RULL(0x20010A43), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_CORE_FIRMASK_AND                                      , RULL(0x20010A44), SH_UNT_C        , SH_ACS_SCOM1_AND );
+REG64( C_CORE_FIRMASK_OR                                       , RULL(0x20010A45), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_CORE_FIRMASK                                        , RULL(0x20010A43), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_CORE_FIRMASK_AND                                    , RULL(0x20010A44), SH_UNT_C_0      , SH_ACS_SCOM1_AND );
+REG64( C_0_CORE_FIRMASK_OR                                     , RULL(0x20010A45), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_CORE_FIRMASK                                        , RULL(0x21010A43), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_CORE_FIRMASK_AND                                    , RULL(0x21010A44), SH_UNT_C_1      , SH_ACS_SCOM1_AND );
+REG64( C_1_CORE_FIRMASK_OR                                     , RULL(0x21010A45), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_CORE_FIRMASK                                        , RULL(0x22010A43), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_CORE_FIRMASK_AND                                    , RULL(0x22010A44), SH_UNT_C_2      , SH_ACS_SCOM1_AND );
+REG64( C_2_CORE_FIRMASK_OR                                     , RULL(0x22010A45), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_CORE_FIRMASK                                        , RULL(0x23010A43), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_CORE_FIRMASK_AND                                    , RULL(0x23010A44), SH_UNT_C_3      , SH_ACS_SCOM1_AND );
+REG64( C_3_CORE_FIRMASK_OR                                     , RULL(0x23010A45), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_CORE_FIRMASK                                        , RULL(0x24010A43), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_CORE_FIRMASK_AND                                    , RULL(0x24010A44), SH_UNT_C_4      , SH_ACS_SCOM1_AND );
+REG64( C_4_CORE_FIRMASK_OR                                     , RULL(0x24010A45), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_CORE_FIRMASK                                        , RULL(0x25010A43), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_CORE_FIRMASK_AND                                    , RULL(0x25010A44), SH_UNT_C_5      , SH_ACS_SCOM1_AND );
+REG64( C_5_CORE_FIRMASK_OR                                     , RULL(0x25010A45), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_CORE_FIRMASK                                        , RULL(0x26010A43), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_CORE_FIRMASK_AND                                    , RULL(0x26010A44), SH_UNT_C_6      , SH_ACS_SCOM1_AND );
+REG64( C_6_CORE_FIRMASK_OR                                     , RULL(0x26010A45), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_CORE_FIRMASK                                        , RULL(0x27010A43), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_CORE_FIRMASK_AND                                    , RULL(0x27010A44), SH_UNT_C_7      , SH_ACS_SCOM1_AND );
+REG64( C_7_CORE_FIRMASK_OR                                     , RULL(0x27010A45), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_CORE_FIRMASK                                        , RULL(0x28010A43), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_CORE_FIRMASK_AND                                    , RULL(0x28010A44), SH_UNT_C_8      , SH_ACS_SCOM1_AND );
+REG64( C_8_CORE_FIRMASK_OR                                     , RULL(0x28010A45), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_CORE_FIRMASK                                        , RULL(0x29010A43), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_CORE_FIRMASK_AND                                    , RULL(0x29010A44), SH_UNT_C_9      , SH_ACS_SCOM1_AND );
+REG64( C_9_CORE_FIRMASK_OR                                     , RULL(0x29010A45), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_CORE_FIRMASK                                       , RULL(0x2A010A43), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_CORE_FIRMASK_AND                                   , RULL(0x2A010A44), SH_UNT_C_10     , SH_ACS_SCOM1_AND );
+REG64( C_10_CORE_FIRMASK_OR                                    , RULL(0x2A010A45), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_CORE_FIRMASK                                       , RULL(0x2B010A43), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_CORE_FIRMASK_AND                                   , RULL(0x2B010A44), SH_UNT_C_11     , SH_ACS_SCOM1_AND );
+REG64( C_11_CORE_FIRMASK_OR                                    , RULL(0x2B010A45), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_CORE_FIRMASK                                       , RULL(0x2C010A43), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_CORE_FIRMASK_AND                                   , RULL(0x2C010A44), SH_UNT_C_12     , SH_ACS_SCOM1_AND );
+REG64( C_12_CORE_FIRMASK_OR                                    , RULL(0x2C010A45), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_CORE_FIRMASK                                       , RULL(0x2D010A43), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_CORE_FIRMASK_AND                                   , RULL(0x2D010A44), SH_UNT_C_13     , SH_ACS_SCOM1_AND );
+REG64( C_13_CORE_FIRMASK_OR                                    , RULL(0x2D010A45), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_CORE_FIRMASK                                       , RULL(0x2E010A43), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_CORE_FIRMASK_AND                                   , RULL(0x2E010A44), SH_UNT_C_14     , SH_ACS_SCOM1_AND );
+REG64( C_14_CORE_FIRMASK_OR                                    , RULL(0x2E010A45), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_CORE_FIRMASK                                       , RULL(0x2F010A43), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_CORE_FIRMASK_AND                                   , RULL(0x2F010A44), SH_UNT_C_15     , SH_ACS_SCOM1_AND );
+REG64( C_15_CORE_FIRMASK_OR                                    , RULL(0x2F010A45), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_CORE_FIRMASK                                       , RULL(0x30010A43), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_CORE_FIRMASK_AND                                   , RULL(0x30010A44), SH_UNT_C_16     , SH_ACS_SCOM1_AND );
+REG64( C_16_CORE_FIRMASK_OR                                    , RULL(0x30010A45), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_CORE_FIRMASK                                       , RULL(0x31010A43), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_CORE_FIRMASK_AND                                   , RULL(0x31010A44), SH_UNT_C_17     , SH_ACS_SCOM1_AND );
+REG64( C_17_CORE_FIRMASK_OR                                    , RULL(0x31010A45), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_CORE_FIRMASK                                       , RULL(0x32010A43), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_CORE_FIRMASK_AND                                   , RULL(0x32010A44), SH_UNT_C_18     , SH_ACS_SCOM1_AND );
+REG64( C_18_CORE_FIRMASK_OR                                    , RULL(0x32010A45), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_CORE_FIRMASK                                       , RULL(0x33010A43), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_CORE_FIRMASK_AND                                   , RULL(0x33010A44), SH_UNT_C_19     , SH_ACS_SCOM1_AND );
+REG64( C_19_CORE_FIRMASK_OR                                    , RULL(0x33010A45), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_CORE_FIRMASK                                       , RULL(0x34010A43), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_CORE_FIRMASK_AND                                   , RULL(0x34010A44), SH_UNT_C_20     , SH_ACS_SCOM1_AND );
+REG64( C_20_CORE_FIRMASK_OR                                    , RULL(0x34010A45), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_CORE_FIRMASK                                       , RULL(0x35010A43), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_CORE_FIRMASK_AND                                   , RULL(0x35010A44), SH_UNT_C_21     , SH_ACS_SCOM1_AND );
+REG64( C_21_CORE_FIRMASK_OR                                    , RULL(0x35010A45), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_CORE_FIRMASK                                       , RULL(0x36010A43), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_CORE_FIRMASK_AND                                   , RULL(0x36010A44), SH_UNT_C_22     , SH_ACS_SCOM1_AND );
+REG64( C_22_CORE_FIRMASK_OR                                    , RULL(0x36010A45), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_CORE_FIRMASK                                       , RULL(0x37010A43), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_CORE_FIRMASK_AND                                   , RULL(0x37010A44), SH_UNT_C_23     , SH_ACS_SCOM1_AND );
+REG64( C_23_CORE_FIRMASK_OR                                    , RULL(0x37010A45), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EX_0_L2_CORE_FIRMASK                                    , RULL(0x20010A43), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A43,
+REG64( EX_0_L2_CORE_FIRMASK_AND                                , RULL(0x20010A44), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 21010A44,
+REG64( EX_0_L2_CORE_FIRMASK_OR                                 , RULL(0x20010A45), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 21010A45,
+REG64( EX_10_L2_CORE_FIRMASK                                   , RULL(0x34010A43), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010A43,
+REG64( EX_10_L2_CORE_FIRMASK_AND                               , RULL(0x34010A44), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM1_AND ); //DUPS: 35010A44,
+REG64( EX_10_L2_CORE_FIRMASK_OR                                , RULL(0x34010A45), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 35010A45,
+REG64( EX_11_L2_CORE_FIRMASK                                   , RULL(0x36010A43), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010A43,
+REG64( EX_11_L2_CORE_FIRMASK_AND                               , RULL(0x36010A44), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM1_AND ); //DUPS: 37010A44,
+REG64( EX_11_L2_CORE_FIRMASK_OR                                , RULL(0x36010A45), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 37010A45,
+REG64( EX_1_L2_CORE_FIRMASK                                    , RULL(0x22010A43), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010A43,
+REG64( EX_1_L2_CORE_FIRMASK_AND                                , RULL(0x22010A44), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 23010A44,
+REG64( EX_1_L2_CORE_FIRMASK_OR                                 , RULL(0x22010A45), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 23010A45,
+REG64( EX_2_L2_CORE_FIRMASK                                    , RULL(0x24010A43), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010A43,
+REG64( EX_2_L2_CORE_FIRMASK_AND                                , RULL(0x24010A44), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 25010A44,
+REG64( EX_2_L2_CORE_FIRMASK_OR                                 , RULL(0x24010A45), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 25010A45,
+REG64( EX_3_L2_CORE_FIRMASK                                    , RULL(0x26010A43), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010A43,
+REG64( EX_3_L2_CORE_FIRMASK_AND                                , RULL(0x26010A44), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 27010A44,
+REG64( EX_3_L2_CORE_FIRMASK_OR                                 , RULL(0x26010A45), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 27010A45,
+REG64( EX_4_L2_CORE_FIRMASK                                    , RULL(0x28010A43), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010A43,
+REG64( EX_4_L2_CORE_FIRMASK_AND                                , RULL(0x28010A44), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 29010A44,
+REG64( EX_4_L2_CORE_FIRMASK_OR                                 , RULL(0x28010A45), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 29010A45,
+REG64( EX_5_L2_CORE_FIRMASK                                    , RULL(0x2A010A43), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010A43,
+REG64( EX_5_L2_CORE_FIRMASK_AND                                , RULL(0x2A010A44), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2B010A44,
+REG64( EX_5_L2_CORE_FIRMASK_OR                                 , RULL(0x2A010A45), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2B010A45,
+REG64( EX_6_L2_CORE_FIRMASK                                    , RULL(0x2C010A43), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010A43,
+REG64( EX_6_L2_CORE_FIRMASK_AND                                , RULL(0x2C010A44), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2D010A44,
+REG64( EX_6_L2_CORE_FIRMASK_OR                                 , RULL(0x2C010A45), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2D010A45,
+REG64( EX_7_L2_CORE_FIRMASK                                    , RULL(0x2E010A43), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010A43,
+REG64( EX_7_L2_CORE_FIRMASK_AND                                , RULL(0x2E010A44), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2F010A44,
+REG64( EX_7_L2_CORE_FIRMASK_OR                                 , RULL(0x2E010A45), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2F010A45,
+REG64( EX_8_L2_CORE_FIRMASK                                    , RULL(0x30010A43), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010A43,
+REG64( EX_8_L2_CORE_FIRMASK_AND                                , RULL(0x30010A44), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 31010A44,
+REG64( EX_8_L2_CORE_FIRMASK_OR                                 , RULL(0x30010A45), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 31010A45,
+REG64( EX_9_L2_CORE_FIRMASK                                    , RULL(0x32010A43), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010A43,
+REG64( EX_9_L2_CORE_FIRMASK_AND                                , RULL(0x32010A44), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM1_AND ); //DUPS: 33010A44,
+REG64( EX_9_L2_CORE_FIRMASK_OR                                 , RULL(0x32010A45), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 33010A45,
+REG64( EX_L2_CORE_FIRMASK                                      , RULL(0x20010A43), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A43,
+REG64( EX_L2_CORE_FIRMASK_AND                                  , RULL(0x20010A44), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM1_AND ); //DUPS: 21010A44,
+REG64( EX_L2_CORE_FIRMASK_OR                                   , RULL(0x20010A45), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 21010A45,
+
+REG64( C_CORE_FUSES                                            , RULL(0x20010AA7), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_CORE_FUSES                                          , RULL(0x20010AA7), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_CORE_FUSES                                          , RULL(0x21010AA7), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_CORE_FUSES                                          , RULL(0x22010AA7), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_CORE_FUSES                                          , RULL(0x23010AA7), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_CORE_FUSES                                          , RULL(0x24010AA7), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_CORE_FUSES                                          , RULL(0x25010AA7), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_CORE_FUSES                                          , RULL(0x26010AA7), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_CORE_FUSES                                          , RULL(0x27010AA7), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_CORE_FUSES                                          , RULL(0x28010AA7), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_CORE_FUSES                                          , RULL(0x29010AA7), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_CORE_FUSES                                         , RULL(0x2A010AA7), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_CORE_FUSES                                         , RULL(0x2B010AA7), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_CORE_FUSES                                         , RULL(0x2C010AA7), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_CORE_FUSES                                         , RULL(0x2D010AA7), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_CORE_FUSES                                         , RULL(0x2E010AA7), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_CORE_FUSES                                         , RULL(0x2F010AA7), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_CORE_FUSES                                         , RULL(0x30010AA7), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_CORE_FUSES                                         , RULL(0x31010AA7), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_CORE_FUSES                                         , RULL(0x32010AA7), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_CORE_FUSES                                         , RULL(0x33010AA7), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_CORE_FUSES                                         , RULL(0x34010AA7), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_CORE_FUSES                                         , RULL(0x35010AA7), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_CORE_FUSES                                         , RULL(0x36010AA7), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_CORE_FUSES                                         , RULL(0x37010AA7), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_0_L2_CORE_FUSES                                      , RULL(0x20010AA7), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010AA7,
+REG64( EX_10_L2_CORE_FUSES                                     , RULL(0x34010AA7), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35010AA7,
+REG64( EX_11_L2_CORE_FUSES                                     , RULL(0x36010AA7), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37010AA7,
+REG64( EX_1_L2_CORE_FUSES                                      , RULL(0x22010AA7), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23010AA7,
+REG64( EX_2_L2_CORE_FUSES                                      , RULL(0x24010AA7), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25010AA7,
+REG64( EX_3_L2_CORE_FUSES                                      , RULL(0x26010AA7), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27010AA7,
+REG64( EX_4_L2_CORE_FUSES                                      , RULL(0x28010AA7), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29010AA7,
+REG64( EX_5_L2_CORE_FUSES                                      , RULL(0x2A010AA7), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B010AA7,
+REG64( EX_6_L2_CORE_FUSES                                      , RULL(0x2C010AA7), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D010AA7,
+REG64( EX_7_L2_CORE_FUSES                                      , RULL(0x2E010AA7), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F010AA7,
+REG64( EX_8_L2_CORE_FUSES                                      , RULL(0x30010AA7), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31010AA7,
+REG64( EX_9_L2_CORE_FUSES                                      , RULL(0x32010AA7), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33010AA7,
+REG64( EX_L2_CORE_FUSES                                        , RULL(0x20010AA7), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010AA7,
+
+REG64( C_CORE_THREAD_STATE                                     , RULL(0x20010AB3), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_CORE_THREAD_STATE                                   , RULL(0x20010AB3), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_CORE_THREAD_STATE                                   , RULL(0x21010AB3), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_CORE_THREAD_STATE                                   , RULL(0x22010AB3), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_CORE_THREAD_STATE                                   , RULL(0x23010AB3), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_CORE_THREAD_STATE                                   , RULL(0x24010AB3), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_CORE_THREAD_STATE                                   , RULL(0x25010AB3), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_CORE_THREAD_STATE                                   , RULL(0x26010AB3), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_CORE_THREAD_STATE                                   , RULL(0x27010AB3), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_CORE_THREAD_STATE                                   , RULL(0x28010AB3), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_CORE_THREAD_STATE                                   , RULL(0x29010AB3), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_CORE_THREAD_STATE                                  , RULL(0x2A010AB3), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_CORE_THREAD_STATE                                  , RULL(0x2B010AB3), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_CORE_THREAD_STATE                                  , RULL(0x2C010AB3), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_CORE_THREAD_STATE                                  , RULL(0x2D010AB3), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_CORE_THREAD_STATE                                  , RULL(0x2E010AB3), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_CORE_THREAD_STATE                                  , RULL(0x2F010AB3), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_CORE_THREAD_STATE                                  , RULL(0x30010AB3), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_CORE_THREAD_STATE                                  , RULL(0x31010AB3), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_CORE_THREAD_STATE                                  , RULL(0x32010AB3), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_CORE_THREAD_STATE                                  , RULL(0x33010AB3), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_CORE_THREAD_STATE                                  , RULL(0x34010AB3), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_CORE_THREAD_STATE                                  , RULL(0x35010AB3), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_CORE_THREAD_STATE                                  , RULL(0x36010AB3), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_CORE_THREAD_STATE                                  , RULL(0x37010AB3), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_0_L2_CORE_THREAD_STATE                               , RULL(0x21010AB3), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 20010AB3,
+REG64( EX_10_L2_CORE_THREAD_STATE                              , RULL(0x35010AB3), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 34010AB3,
+REG64( EX_11_L2_CORE_THREAD_STATE                              , RULL(0x37010AB3), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 36010AB3,
+REG64( EX_1_L2_CORE_THREAD_STATE                               , RULL(0x23010AB3), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 22010AB3,
+REG64( EX_2_L2_CORE_THREAD_STATE                               , RULL(0x25010AB3), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 24010AB3,
+REG64( EX_3_L2_CORE_THREAD_STATE                               , RULL(0x27010AB3), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 26010AB3,
+REG64( EX_4_L2_CORE_THREAD_STATE                               , RULL(0x29010AB3), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 28010AB3,
+REG64( EX_5_L2_CORE_THREAD_STATE                               , RULL(0x2B010AB3), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2A010AB3,
+REG64( EX_6_L2_CORE_THREAD_STATE                               , RULL(0x2D010AB3), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2C010AB3,
+REG64( EX_7_L2_CORE_THREAD_STATE                               , RULL(0x2F010AB3), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2E010AB3,
+REG64( EX_8_L2_CORE_THREAD_STATE                               , RULL(0x31010AB3), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 30010AB3,
+REG64( EX_9_L2_CORE_THREAD_STATE                               , RULL(0x33010AB3), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 32010AB3,
+REG64( EX_L2_CORE_THREAD_STATE                                 , RULL(0x21010AB3), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 20010AB3,
+
+REG64( C_CORE_WOF                                              , RULL(0x20010A48), SH_UNT_C        ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_0_CORE_WOF                                            , RULL(0x20010A48), SH_UNT_C_0      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_1_CORE_WOF                                            , RULL(0x21010A48), SH_UNT_C_1      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_2_CORE_WOF                                            , RULL(0x22010A48), SH_UNT_C_2      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_3_CORE_WOF                                            , RULL(0x23010A48), SH_UNT_C_3      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_4_CORE_WOF                                            , RULL(0x24010A48), SH_UNT_C_4      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_5_CORE_WOF                                            , RULL(0x25010A48), SH_UNT_C_5      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_6_CORE_WOF                                            , RULL(0x26010A48), SH_UNT_C_6      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_7_CORE_WOF                                            , RULL(0x27010A48), SH_UNT_C_7      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_8_CORE_WOF                                            , RULL(0x28010A48), SH_UNT_C_8      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_9_CORE_WOF                                            , RULL(0x29010A48), SH_UNT_C_9      ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_10_CORE_WOF                                           , RULL(0x2A010A48), SH_UNT_C_10     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_11_CORE_WOF                                           , RULL(0x2B010A48), SH_UNT_C_11     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_12_CORE_WOF                                           , RULL(0x2C010A48), SH_UNT_C_12     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_13_CORE_WOF                                           , RULL(0x2D010A48), SH_UNT_C_13     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_14_CORE_WOF                                           , RULL(0x2E010A48), SH_UNT_C_14     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_15_CORE_WOF                                           , RULL(0x2F010A48), SH_UNT_C_15     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_16_CORE_WOF                                           , RULL(0x30010A48), SH_UNT_C_16     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_17_CORE_WOF                                           , RULL(0x31010A48), SH_UNT_C_17     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_18_CORE_WOF                                           , RULL(0x32010A48), SH_UNT_C_18     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_19_CORE_WOF                                           , RULL(0x33010A48), SH_UNT_C_19     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_20_CORE_WOF                                           , RULL(0x34010A48), SH_UNT_C_20     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_21_CORE_WOF                                           , RULL(0x35010A48), SH_UNT_C_21     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_22_CORE_WOF                                           , RULL(0x36010A48), SH_UNT_C_22     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( C_23_CORE_WOF                                           , RULL(0x37010A48), SH_UNT_C_23     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( EX_CORE_WOF                                             , RULL(0x20010A48), SH_UNT_EX       ,
+       SH_ACS_SCOM_WCLRREG ); //DUPS: 21010A48,
+REG64( EX_0_CORE_WOF                                           , RULL(0x20010A48), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_WCLRREG ); //DUPS: 21010A48,
+REG64( EX_1_CORE_WOF                                           , RULL(0x22010A48), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_WCLRREG ); //DUPS: 23010A48,
+REG64( EX_2_CORE_WOF                                           , RULL(0x24010A48), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_WCLRREG ); //DUPS: 25010A48,
+REG64( EX_3_CORE_WOF                                           , RULL(0x26010A48), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_WCLRREG ); //DUPS: 27010A48,
+REG64( EX_4_CORE_WOF                                           , RULL(0x28010A48), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_WCLRREG ); //DUPS: 29010A48,
+REG64( EX_5_CORE_WOF                                           , RULL(0x2A010A48), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_WCLRREG ); //DUPS: 2B010A48,
+REG64( EX_6_CORE_WOF                                           , RULL(0x2C010A48), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_WCLRREG ); //DUPS: 2D010A48,
+REG64( EX_7_CORE_WOF                                           , RULL(0x2E010A48), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_WCLRREG ); //DUPS: 2F010A48,
+REG64( EX_8_CORE_WOF                                           , RULL(0x30010A48), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_WCLRREG ); //DUPS: 31010A48,
+REG64( EX_9_CORE_WOF                                           , RULL(0x32010A48), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_WCLRREG ); //DUPS: 33010A48,
+REG64( EX_10_CORE_WOF                                          , RULL(0x34010A48), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_WCLRREG ); //DUPS: 35010A48,
+REG64( EX_11_CORE_WOF                                          , RULL(0x36010A48), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_WCLRREG ); //DUPS: 37010A48,
+
+REG64( C_CPLT_CONF0                                            , RULL(0x20000008), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_CPLT_CONF0_OR                                         , RULL(0x20000018), SH_UNT_C        , SH_ACS_SCOM1_OR  );
+REG64( C_CPLT_CONF0_CLEAR                                      , RULL(0x20000028), SH_UNT_C        ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_0_CPLT_CONF0                                          , RULL(0x20000008), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_CPLT_CONF0_OR                                       , RULL(0x20000018), SH_UNT_C_0      , SH_ACS_SCOM1_OR  );
+REG64( C_0_CPLT_CONF0_CLEAR                                    , RULL(0x20000028), SH_UNT_C_0      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_1_CPLT_CONF0                                          , RULL(0x21000008), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPLT_CONF0_OR                                       , RULL(0x21000018), SH_UNT_C_1      , SH_ACS_SCOM1_OR  );
+REG64( C_1_CPLT_CONF0_CLEAR                                    , RULL(0x21000028), SH_UNT_C_1      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_2_CPLT_CONF0                                          , RULL(0x22000008), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPLT_CONF0_OR                                       , RULL(0x22000018), SH_UNT_C_2      , SH_ACS_SCOM1_OR  );
+REG64( C_2_CPLT_CONF0_CLEAR                                    , RULL(0x22000028), SH_UNT_C_2      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_3_CPLT_CONF0                                          , RULL(0x23000008), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPLT_CONF0_OR                                       , RULL(0x23000018), SH_UNT_C_3      , SH_ACS_SCOM1_OR  );
+REG64( C_3_CPLT_CONF0_CLEAR                                    , RULL(0x23000028), SH_UNT_C_3      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_4_CPLT_CONF0                                          , RULL(0x24000008), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPLT_CONF0_OR                                       , RULL(0x24000018), SH_UNT_C_4      , SH_ACS_SCOM1_OR  );
+REG64( C_4_CPLT_CONF0_CLEAR                                    , RULL(0x24000028), SH_UNT_C_4      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_5_CPLT_CONF0                                          , RULL(0x25000008), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPLT_CONF0_OR                                       , RULL(0x25000018), SH_UNT_C_5      , SH_ACS_SCOM1_OR  );
+REG64( C_5_CPLT_CONF0_CLEAR                                    , RULL(0x25000028), SH_UNT_C_5      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_6_CPLT_CONF0                                          , RULL(0x26000008), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPLT_CONF0_OR                                       , RULL(0x26000018), SH_UNT_C_6      , SH_ACS_SCOM1_OR  );
+REG64( C_6_CPLT_CONF0_CLEAR                                    , RULL(0x26000028), SH_UNT_C_6      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_7_CPLT_CONF0                                          , RULL(0x27000008), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPLT_CONF0_OR                                       , RULL(0x27000018), SH_UNT_C_7      , SH_ACS_SCOM1_OR  );
+REG64( C_7_CPLT_CONF0_CLEAR                                    , RULL(0x27000028), SH_UNT_C_7      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_8_CPLT_CONF0                                          , RULL(0x28000008), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPLT_CONF0_OR                                       , RULL(0x28000018), SH_UNT_C_8      , SH_ACS_SCOM1_OR  );
+REG64( C_8_CPLT_CONF0_CLEAR                                    , RULL(0x28000028), SH_UNT_C_8      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_9_CPLT_CONF0                                          , RULL(0x29000008), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPLT_CONF0_OR                                       , RULL(0x29000018), SH_UNT_C_9      , SH_ACS_SCOM1_OR  );
+REG64( C_9_CPLT_CONF0_CLEAR                                    , RULL(0x29000028), SH_UNT_C_9      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_10_CPLT_CONF0                                         , RULL(0x2A000008), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_CPLT_CONF0_OR                                      , RULL(0x2A000018), SH_UNT_C_10     , SH_ACS_SCOM1_OR  );
+REG64( C_10_CPLT_CONF0_CLEAR                                   , RULL(0x2A000028), SH_UNT_C_10     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_11_CPLT_CONF0                                         , RULL(0x2B000008), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPLT_CONF0_OR                                      , RULL(0x2B000018), SH_UNT_C_11     , SH_ACS_SCOM1_OR  );
+REG64( C_11_CPLT_CONF0_CLEAR                                   , RULL(0x2B000028), SH_UNT_C_11     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_12_CPLT_CONF0                                         , RULL(0x2C000008), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPLT_CONF0_OR                                      , RULL(0x2C000018), SH_UNT_C_12     , SH_ACS_SCOM1_OR  );
+REG64( C_12_CPLT_CONF0_CLEAR                                   , RULL(0x2C000028), SH_UNT_C_12     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_13_CPLT_CONF0                                         , RULL(0x2D000008), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPLT_CONF0_OR                                      , RULL(0x2D000018), SH_UNT_C_13     , SH_ACS_SCOM1_OR  );
+REG64( C_13_CPLT_CONF0_CLEAR                                   , RULL(0x2D000028), SH_UNT_C_13     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_14_CPLT_CONF0                                         , RULL(0x2E000008), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPLT_CONF0_OR                                      , RULL(0x2E000018), SH_UNT_C_14     , SH_ACS_SCOM1_OR  );
+REG64( C_14_CPLT_CONF0_CLEAR                                   , RULL(0x2E000028), SH_UNT_C_14     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_15_CPLT_CONF0                                         , RULL(0x2F000008), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPLT_CONF0_OR                                      , RULL(0x2F000018), SH_UNT_C_15     , SH_ACS_SCOM1_OR  );
+REG64( C_15_CPLT_CONF0_CLEAR                                   , RULL(0x2F000028), SH_UNT_C_15     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_16_CPLT_CONF0                                         , RULL(0x30000008), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPLT_CONF0_OR                                      , RULL(0x30000018), SH_UNT_C_16     , SH_ACS_SCOM1_OR  );
+REG64( C_16_CPLT_CONF0_CLEAR                                   , RULL(0x30000028), SH_UNT_C_16     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_17_CPLT_CONF0                                         , RULL(0x31000008), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPLT_CONF0_OR                                      , RULL(0x31000018), SH_UNT_C_17     , SH_ACS_SCOM1_OR  );
+REG64( C_17_CPLT_CONF0_CLEAR                                   , RULL(0x31000028), SH_UNT_C_17     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_18_CPLT_CONF0                                         , RULL(0x32000008), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPLT_CONF0_OR                                      , RULL(0x32000018), SH_UNT_C_18     , SH_ACS_SCOM1_OR  );
+REG64( C_18_CPLT_CONF0_CLEAR                                   , RULL(0x32000028), SH_UNT_C_18     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_19_CPLT_CONF0                                         , RULL(0x33000008), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPLT_CONF0_OR                                      , RULL(0x33000018), SH_UNT_C_19     , SH_ACS_SCOM1_OR  );
+REG64( C_19_CPLT_CONF0_CLEAR                                   , RULL(0x33000028), SH_UNT_C_19     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_20_CPLT_CONF0                                         , RULL(0x34000008), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPLT_CONF0_OR                                      , RULL(0x34000018), SH_UNT_C_20     , SH_ACS_SCOM1_OR  );
+REG64( C_20_CPLT_CONF0_CLEAR                                   , RULL(0x34000028), SH_UNT_C_20     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_21_CPLT_CONF0                                         , RULL(0x35000008), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPLT_CONF0_OR                                      , RULL(0x35000018), SH_UNT_C_21     , SH_ACS_SCOM1_OR  );
+REG64( C_21_CPLT_CONF0_CLEAR                                   , RULL(0x35000028), SH_UNT_C_21     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_22_CPLT_CONF0                                         , RULL(0x36000008), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPLT_CONF0_OR                                      , RULL(0x36000018), SH_UNT_C_22     , SH_ACS_SCOM1_OR  );
+REG64( C_22_CPLT_CONF0_CLEAR                                   , RULL(0x36000028), SH_UNT_C_22     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_23_CPLT_CONF0                                         , RULL(0x37000008), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPLT_CONF0_OR                                      , RULL(0x37000018), SH_UNT_C_23     , SH_ACS_SCOM1_OR  );
+REG64( C_23_CPLT_CONF0_CLEAR                                   , RULL(0x37000028), SH_UNT_C_23     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_CPLT_CONF0                                           , RULL(0x10000008), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_CPLT_CONF0_OR                                        , RULL(0x10000018), SH_UNT_EQ       , SH_ACS_SCOM1_OR  );
+REG64( EQ_CPLT_CONF0_CLEAR                                     , RULL(0x10000028), SH_UNT_EQ       ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_0_CPLT_CONF0                                         , RULL(0x10000008), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_0_CPLT_CONF0_OR                                      , RULL(0x10000018), SH_UNT_EQ_0     , SH_ACS_SCOM1_OR  );
+REG64( EQ_0_CPLT_CONF0_CLEAR                                   , RULL(0x10000028), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_1_CPLT_CONF0                                         , RULL(0x11000008), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_CPLT_CONF0_OR                                      , RULL(0x11000018), SH_UNT_EQ_1     , SH_ACS_SCOM1_OR  );
+REG64( EQ_1_CPLT_CONF0_CLEAR                                   , RULL(0x11000028), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_2_CPLT_CONF0                                         , RULL(0x12000008), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_CPLT_CONF0_OR                                      , RULL(0x12000018), SH_UNT_EQ_2     , SH_ACS_SCOM1_OR  );
+REG64( EQ_2_CPLT_CONF0_CLEAR                                   , RULL(0x12000028), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_3_CPLT_CONF0                                         , RULL(0x13000008), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_CPLT_CONF0_OR                                      , RULL(0x13000018), SH_UNT_EQ_3     , SH_ACS_SCOM1_OR  );
+REG64( EQ_3_CPLT_CONF0_CLEAR                                   , RULL(0x13000028), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_4_CPLT_CONF0                                         , RULL(0x14000008), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_CPLT_CONF0_OR                                      , RULL(0x14000018), SH_UNT_EQ_4     , SH_ACS_SCOM1_OR  );
+REG64( EQ_4_CPLT_CONF0_CLEAR                                   , RULL(0x14000028), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_5_CPLT_CONF0                                         , RULL(0x15000008), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_CPLT_CONF0_OR                                      , RULL(0x15000018), SH_UNT_EQ_5     , SH_ACS_SCOM1_OR  );
+REG64( EQ_5_CPLT_CONF0_CLEAR                                   , RULL(0x15000028), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EX_CPLT_CONF0                                           , RULL(0x20000008), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21000008,
+REG64( EX_CPLT_CONF0_OR                                        , RULL(0x20000018), SH_UNT_EX       ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 21000018,
+REG64( EX_CPLT_CONF0_CLEAR                                     , RULL(0x20000028), SH_UNT_EX       ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 21000028,
+REG64( EX_0_CPLT_CONF0                                         , RULL(0x20000008), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21000008,
+REG64( EX_0_CPLT_CONF0_OR                                      , RULL(0x20000018), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 21000018,
+REG64( EX_0_CPLT_CONF0_CLEAR                                   , RULL(0x20000028), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 21000028,
+REG64( EX_1_CPLT_CONF0                                         , RULL(0x22000008), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23000008,
+REG64( EX_1_CPLT_CONF0_OR                                      , RULL(0x22000018), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 23000018,
+REG64( EX_1_CPLT_CONF0_CLEAR                                   , RULL(0x22000028), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 23000028,
+REG64( EX_2_CPLT_CONF0                                         , RULL(0x24000008), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25000008,
+REG64( EX_2_CPLT_CONF0_OR                                      , RULL(0x24000018), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 25000018,
+REG64( EX_2_CPLT_CONF0_CLEAR                                   , RULL(0x24000028), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 25000028,
+REG64( EX_3_CPLT_CONF0                                         , RULL(0x26000008), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27000008,
+REG64( EX_3_CPLT_CONF0_OR                                      , RULL(0x26000018), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 27000018,
+REG64( EX_3_CPLT_CONF0_CLEAR                                   , RULL(0x26000028), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 27000028,
+REG64( EX_4_CPLT_CONF0                                         , RULL(0x28000008), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29000008,
+REG64( EX_4_CPLT_CONF0_OR                                      , RULL(0x28000018), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 29000018,
+REG64( EX_4_CPLT_CONF0_CLEAR                                   , RULL(0x28000028), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 29000028,
+REG64( EX_5_CPLT_CONF0                                         , RULL(0x2A000008), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B000008,
+REG64( EX_5_CPLT_CONF0_OR                                      , RULL(0x2A000018), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 2B000018,
+REG64( EX_5_CPLT_CONF0_CLEAR                                   , RULL(0x2A000028), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 2B000028,
+REG64( EX_6_CPLT_CONF0                                         , RULL(0x2C000008), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D000008,
+REG64( EX_6_CPLT_CONF0_OR                                      , RULL(0x2C000018), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 2D000018,
+REG64( EX_6_CPLT_CONF0_CLEAR                                   , RULL(0x2C000028), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 2D000028,
+REG64( EX_7_CPLT_CONF0                                         , RULL(0x2E000008), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F000008,
+REG64( EX_7_CPLT_CONF0_OR                                      , RULL(0x2E000018), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 2F000018,
+REG64( EX_7_CPLT_CONF0_CLEAR                                   , RULL(0x2E000028), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 2F000028,
+REG64( EX_8_CPLT_CONF0                                         , RULL(0x30000008), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31000008,
+REG64( EX_8_CPLT_CONF0_OR                                      , RULL(0x30000018), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 31000018,
+REG64( EX_8_CPLT_CONF0_CLEAR                                   , RULL(0x30000028), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 31000028,
+REG64( EX_9_CPLT_CONF0                                         , RULL(0x32000008), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33000008,
+REG64( EX_9_CPLT_CONF0_OR                                      , RULL(0x32000018), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 33000018,
+REG64( EX_9_CPLT_CONF0_CLEAR                                   , RULL(0x32000028), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 33000028,
+REG64( EX_10_CPLT_CONF0                                        , RULL(0x34000008), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35000008,
+REG64( EX_10_CPLT_CONF0_OR                                     , RULL(0x34000018), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 35000018,
+REG64( EX_10_CPLT_CONF0_CLEAR                                  , RULL(0x34000028), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 35000028,
+REG64( EX_11_CPLT_CONF0                                        , RULL(0x36000008), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37000008,
+REG64( EX_11_CPLT_CONF0_OR                                     , RULL(0x36000018), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 37000018,
+REG64( EX_11_CPLT_CONF0_CLEAR                                  , RULL(0x36000028), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 37000028,
+
+REG64( C_CPLT_CONF1                                            , RULL(0x20000009), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_CPLT_CONF1_OR                                         , RULL(0x20000019), SH_UNT_C        , SH_ACS_SCOM1_OR  );
+REG64( C_CPLT_CONF1_CLEAR                                      , RULL(0x20000029), SH_UNT_C        ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_0_CPLT_CONF1                                          , RULL(0x20000009), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_CPLT_CONF1_OR                                       , RULL(0x20000019), SH_UNT_C_0      , SH_ACS_SCOM1_OR  );
+REG64( C_0_CPLT_CONF1_CLEAR                                    , RULL(0x20000029), SH_UNT_C_0      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_1_CPLT_CONF1                                          , RULL(0x21000009), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPLT_CONF1_OR                                       , RULL(0x21000019), SH_UNT_C_1      , SH_ACS_SCOM1_OR  );
+REG64( C_1_CPLT_CONF1_CLEAR                                    , RULL(0x21000029), SH_UNT_C_1      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_2_CPLT_CONF1                                          , RULL(0x22000009), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPLT_CONF1_OR                                       , RULL(0x22000019), SH_UNT_C_2      , SH_ACS_SCOM1_OR  );
+REG64( C_2_CPLT_CONF1_CLEAR                                    , RULL(0x22000029), SH_UNT_C_2      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_3_CPLT_CONF1                                          , RULL(0x23000009), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPLT_CONF1_OR                                       , RULL(0x23000019), SH_UNT_C_3      , SH_ACS_SCOM1_OR  );
+REG64( C_3_CPLT_CONF1_CLEAR                                    , RULL(0x23000029), SH_UNT_C_3      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_4_CPLT_CONF1                                          , RULL(0x24000009), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPLT_CONF1_OR                                       , RULL(0x24000019), SH_UNT_C_4      , SH_ACS_SCOM1_OR  );
+REG64( C_4_CPLT_CONF1_CLEAR                                    , RULL(0x24000029), SH_UNT_C_4      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_5_CPLT_CONF1                                          , RULL(0x25000009), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPLT_CONF1_OR                                       , RULL(0x25000019), SH_UNT_C_5      , SH_ACS_SCOM1_OR  );
+REG64( C_5_CPLT_CONF1_CLEAR                                    , RULL(0x25000029), SH_UNT_C_5      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_6_CPLT_CONF1                                          , RULL(0x26000009), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPLT_CONF1_OR                                       , RULL(0x26000019), SH_UNT_C_6      , SH_ACS_SCOM1_OR  );
+REG64( C_6_CPLT_CONF1_CLEAR                                    , RULL(0x26000029), SH_UNT_C_6      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_7_CPLT_CONF1                                          , RULL(0x27000009), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPLT_CONF1_OR                                       , RULL(0x27000019), SH_UNT_C_7      , SH_ACS_SCOM1_OR  );
+REG64( C_7_CPLT_CONF1_CLEAR                                    , RULL(0x27000029), SH_UNT_C_7      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_8_CPLT_CONF1                                          , RULL(0x28000009), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPLT_CONF1_OR                                       , RULL(0x28000019), SH_UNT_C_8      , SH_ACS_SCOM1_OR  );
+REG64( C_8_CPLT_CONF1_CLEAR                                    , RULL(0x28000029), SH_UNT_C_8      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_9_CPLT_CONF1                                          , RULL(0x29000009), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPLT_CONF1_OR                                       , RULL(0x29000019), SH_UNT_C_9      , SH_ACS_SCOM1_OR  );
+REG64( C_9_CPLT_CONF1_CLEAR                                    , RULL(0x29000029), SH_UNT_C_9      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_10_CPLT_CONF1                                         , RULL(0x2A000009), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_CPLT_CONF1_OR                                      , RULL(0x2A000019), SH_UNT_C_10     , SH_ACS_SCOM1_OR  );
+REG64( C_10_CPLT_CONF1_CLEAR                                   , RULL(0x2A000029), SH_UNT_C_10     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_11_CPLT_CONF1                                         , RULL(0x2B000009), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPLT_CONF1_OR                                      , RULL(0x2B000019), SH_UNT_C_11     , SH_ACS_SCOM1_OR  );
+REG64( C_11_CPLT_CONF1_CLEAR                                   , RULL(0x2B000029), SH_UNT_C_11     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_12_CPLT_CONF1                                         , RULL(0x2C000009), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPLT_CONF1_OR                                      , RULL(0x2C000019), SH_UNT_C_12     , SH_ACS_SCOM1_OR  );
+REG64( C_12_CPLT_CONF1_CLEAR                                   , RULL(0x2C000029), SH_UNT_C_12     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_13_CPLT_CONF1                                         , RULL(0x2D000009), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPLT_CONF1_OR                                      , RULL(0x2D000019), SH_UNT_C_13     , SH_ACS_SCOM1_OR  );
+REG64( C_13_CPLT_CONF1_CLEAR                                   , RULL(0x2D000029), SH_UNT_C_13     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_14_CPLT_CONF1                                         , RULL(0x2E000009), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPLT_CONF1_OR                                      , RULL(0x2E000019), SH_UNT_C_14     , SH_ACS_SCOM1_OR  );
+REG64( C_14_CPLT_CONF1_CLEAR                                   , RULL(0x2E000029), SH_UNT_C_14     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_15_CPLT_CONF1                                         , RULL(0x2F000009), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPLT_CONF1_OR                                      , RULL(0x2F000019), SH_UNT_C_15     , SH_ACS_SCOM1_OR  );
+REG64( C_15_CPLT_CONF1_CLEAR                                   , RULL(0x2F000029), SH_UNT_C_15     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_16_CPLT_CONF1                                         , RULL(0x30000009), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPLT_CONF1_OR                                      , RULL(0x30000019), SH_UNT_C_16     , SH_ACS_SCOM1_OR  );
+REG64( C_16_CPLT_CONF1_CLEAR                                   , RULL(0x30000029), SH_UNT_C_16     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_17_CPLT_CONF1                                         , RULL(0x31000009), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPLT_CONF1_OR                                      , RULL(0x31000019), SH_UNT_C_17     , SH_ACS_SCOM1_OR  );
+REG64( C_17_CPLT_CONF1_CLEAR                                   , RULL(0x31000029), SH_UNT_C_17     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_18_CPLT_CONF1                                         , RULL(0x32000009), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPLT_CONF1_OR                                      , RULL(0x32000019), SH_UNT_C_18     , SH_ACS_SCOM1_OR  );
+REG64( C_18_CPLT_CONF1_CLEAR                                   , RULL(0x32000029), SH_UNT_C_18     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_19_CPLT_CONF1                                         , RULL(0x33000009), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPLT_CONF1_OR                                      , RULL(0x33000019), SH_UNT_C_19     , SH_ACS_SCOM1_OR  );
+REG64( C_19_CPLT_CONF1_CLEAR                                   , RULL(0x33000029), SH_UNT_C_19     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_20_CPLT_CONF1                                         , RULL(0x34000009), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPLT_CONF1_OR                                      , RULL(0x34000019), SH_UNT_C_20     , SH_ACS_SCOM1_OR  );
+REG64( C_20_CPLT_CONF1_CLEAR                                   , RULL(0x34000029), SH_UNT_C_20     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_21_CPLT_CONF1                                         , RULL(0x35000009), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPLT_CONF1_OR                                      , RULL(0x35000019), SH_UNT_C_21     , SH_ACS_SCOM1_OR  );
+REG64( C_21_CPLT_CONF1_CLEAR                                   , RULL(0x35000029), SH_UNT_C_21     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_22_CPLT_CONF1                                         , RULL(0x36000009), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPLT_CONF1_OR                                      , RULL(0x36000019), SH_UNT_C_22     , SH_ACS_SCOM1_OR  );
+REG64( C_22_CPLT_CONF1_CLEAR                                   , RULL(0x36000029), SH_UNT_C_22     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_23_CPLT_CONF1                                         , RULL(0x37000009), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPLT_CONF1_OR                                      , RULL(0x37000019), SH_UNT_C_23     , SH_ACS_SCOM1_OR  );
+REG64( C_23_CPLT_CONF1_CLEAR                                   , RULL(0x37000029), SH_UNT_C_23     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_CPLT_CONF1                                           , RULL(0x10000009), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_CPLT_CONF1_OR                                        , RULL(0x10000019), SH_UNT_EQ       , SH_ACS_SCOM1_OR  );
+REG64( EQ_CPLT_CONF1_CLEAR                                     , RULL(0x10000029), SH_UNT_EQ       ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_0_CPLT_CONF1                                         , RULL(0x10000009), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_0_CPLT_CONF1_OR                                      , RULL(0x10000019), SH_UNT_EQ_0     , SH_ACS_SCOM1_OR  );
+REG64( EQ_0_CPLT_CONF1_CLEAR                                   , RULL(0x10000029), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_1_CPLT_CONF1                                         , RULL(0x11000009), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_CPLT_CONF1_OR                                      , RULL(0x11000019), SH_UNT_EQ_1     , SH_ACS_SCOM1_OR  );
+REG64( EQ_1_CPLT_CONF1_CLEAR                                   , RULL(0x11000029), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_2_CPLT_CONF1                                         , RULL(0x12000009), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_CPLT_CONF1_OR                                      , RULL(0x12000019), SH_UNT_EQ_2     , SH_ACS_SCOM1_OR  );
+REG64( EQ_2_CPLT_CONF1_CLEAR                                   , RULL(0x12000029), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_3_CPLT_CONF1                                         , RULL(0x13000009), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_CPLT_CONF1_OR                                      , RULL(0x13000019), SH_UNT_EQ_3     , SH_ACS_SCOM1_OR  );
+REG64( EQ_3_CPLT_CONF1_CLEAR                                   , RULL(0x13000029), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_4_CPLT_CONF1                                         , RULL(0x14000009), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_CPLT_CONF1_OR                                      , RULL(0x14000019), SH_UNT_EQ_4     , SH_ACS_SCOM1_OR  );
+REG64( EQ_4_CPLT_CONF1_CLEAR                                   , RULL(0x14000029), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_5_CPLT_CONF1                                         , RULL(0x15000009), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_CPLT_CONF1_OR                                      , RULL(0x15000019), SH_UNT_EQ_5     , SH_ACS_SCOM1_OR  );
+REG64( EQ_5_CPLT_CONF1_CLEAR                                   , RULL(0x15000029), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EX_CPLT_CONF1                                           , RULL(0x20000009), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21000009,
+REG64( EX_CPLT_CONF1_OR                                        , RULL(0x20000019), SH_UNT_EX       ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 21000019,
+REG64( EX_CPLT_CONF1_CLEAR                                     , RULL(0x20000029), SH_UNT_EX       ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 21000029,
+REG64( EX_0_CPLT_CONF1                                         , RULL(0x20000009), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21000009,
+REG64( EX_0_CPLT_CONF1_OR                                      , RULL(0x20000019), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 21000019,
+REG64( EX_0_CPLT_CONF1_CLEAR                                   , RULL(0x20000029), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 21000029,
+REG64( EX_1_CPLT_CONF1                                         , RULL(0x22000009), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23000009,
+REG64( EX_1_CPLT_CONF1_OR                                      , RULL(0x22000019), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 23000019,
+REG64( EX_1_CPLT_CONF1_CLEAR                                   , RULL(0x22000029), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 23000029,
+REG64( EX_2_CPLT_CONF1                                         , RULL(0x24000009), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25000009,
+REG64( EX_2_CPLT_CONF1_OR                                      , RULL(0x24000019), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 25000019,
+REG64( EX_2_CPLT_CONF1_CLEAR                                   , RULL(0x24000029), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 25000029,
+REG64( EX_3_CPLT_CONF1                                         , RULL(0x26000009), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27000009,
+REG64( EX_3_CPLT_CONF1_OR                                      , RULL(0x26000019), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 27000019,
+REG64( EX_3_CPLT_CONF1_CLEAR                                   , RULL(0x26000029), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 27000029,
+REG64( EX_4_CPLT_CONF1                                         , RULL(0x28000009), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29000009,
+REG64( EX_4_CPLT_CONF1_OR                                      , RULL(0x28000019), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 29000019,
+REG64( EX_4_CPLT_CONF1_CLEAR                                   , RULL(0x28000029), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 29000029,
+REG64( EX_5_CPLT_CONF1                                         , RULL(0x2A000009), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B000009,
+REG64( EX_5_CPLT_CONF1_OR                                      , RULL(0x2A000019), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 2B000019,
+REG64( EX_5_CPLT_CONF1_CLEAR                                   , RULL(0x2A000029), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 2B000029,
+REG64( EX_6_CPLT_CONF1                                         , RULL(0x2C000009), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D000009,
+REG64( EX_6_CPLT_CONF1_OR                                      , RULL(0x2C000019), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 2D000019,
+REG64( EX_6_CPLT_CONF1_CLEAR                                   , RULL(0x2C000029), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 2D000029,
+REG64( EX_7_CPLT_CONF1                                         , RULL(0x2E000009), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F000009,
+REG64( EX_7_CPLT_CONF1_OR                                      , RULL(0x2E000019), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 2F000019,
+REG64( EX_7_CPLT_CONF1_CLEAR                                   , RULL(0x2E000029), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 2F000029,
+REG64( EX_8_CPLT_CONF1                                         , RULL(0x30000009), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31000009,
+REG64( EX_8_CPLT_CONF1_OR                                      , RULL(0x30000019), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 31000019,
+REG64( EX_8_CPLT_CONF1_CLEAR                                   , RULL(0x30000029), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 31000029,
+REG64( EX_9_CPLT_CONF1                                         , RULL(0x32000009), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33000009,
+REG64( EX_9_CPLT_CONF1_OR                                      , RULL(0x32000019), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 33000019,
+REG64( EX_9_CPLT_CONF1_CLEAR                                   , RULL(0x32000029), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 33000029,
+REG64( EX_10_CPLT_CONF1                                        , RULL(0x34000009), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35000009,
+REG64( EX_10_CPLT_CONF1_OR                                     , RULL(0x34000019), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 35000019,
+REG64( EX_10_CPLT_CONF1_CLEAR                                  , RULL(0x34000029), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 35000029,
+REG64( EX_11_CPLT_CONF1                                        , RULL(0x36000009), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37000009,
+REG64( EX_11_CPLT_CONF1_OR                                     , RULL(0x36000019), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 37000019,
+REG64( EX_11_CPLT_CONF1_CLEAR                                  , RULL(0x36000029), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 37000029,
+
+REG64( C_CPLT_CTRL0                                            , RULL(0x20000000), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_CPLT_CTRL0_OR                                         , RULL(0x20000010), SH_UNT_C        , SH_ACS_SCOM1_OR  );
+REG64( C_CPLT_CTRL0_CLEAR                                      , RULL(0x20000020), SH_UNT_C        ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_0_CPLT_CTRL0                                          , RULL(0x20000000), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_CPLT_CTRL0_OR                                       , RULL(0x20000010), SH_UNT_C_0      , SH_ACS_SCOM1_OR  );
+REG64( C_0_CPLT_CTRL0_CLEAR                                    , RULL(0x20000020), SH_UNT_C_0      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_1_CPLT_CTRL0                                          , RULL(0x21000000), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPLT_CTRL0_OR                                       , RULL(0x21000010), SH_UNT_C_1      , SH_ACS_SCOM1_OR  );
+REG64( C_1_CPLT_CTRL0_CLEAR                                    , RULL(0x21000020), SH_UNT_C_1      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_2_CPLT_CTRL0                                          , RULL(0x22000000), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPLT_CTRL0_OR                                       , RULL(0x22000010), SH_UNT_C_2      , SH_ACS_SCOM1_OR  );
+REG64( C_2_CPLT_CTRL0_CLEAR                                    , RULL(0x22000020), SH_UNT_C_2      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_3_CPLT_CTRL0                                          , RULL(0x23000000), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPLT_CTRL0_OR                                       , RULL(0x23000010), SH_UNT_C_3      , SH_ACS_SCOM1_OR  );
+REG64( C_3_CPLT_CTRL0_CLEAR                                    , RULL(0x23000020), SH_UNT_C_3      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_4_CPLT_CTRL0                                          , RULL(0x24000000), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPLT_CTRL0_OR                                       , RULL(0x24000010), SH_UNT_C_4      , SH_ACS_SCOM1_OR  );
+REG64( C_4_CPLT_CTRL0_CLEAR                                    , RULL(0x24000020), SH_UNT_C_4      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_5_CPLT_CTRL0                                          , RULL(0x25000000), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPLT_CTRL0_OR                                       , RULL(0x25000010), SH_UNT_C_5      , SH_ACS_SCOM1_OR  );
+REG64( C_5_CPLT_CTRL0_CLEAR                                    , RULL(0x25000020), SH_UNT_C_5      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_6_CPLT_CTRL0                                          , RULL(0x26000000), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPLT_CTRL0_OR                                       , RULL(0x26000010), SH_UNT_C_6      , SH_ACS_SCOM1_OR  );
+REG64( C_6_CPLT_CTRL0_CLEAR                                    , RULL(0x26000020), SH_UNT_C_6      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_7_CPLT_CTRL0                                          , RULL(0x27000000), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPLT_CTRL0_OR                                       , RULL(0x27000010), SH_UNT_C_7      , SH_ACS_SCOM1_OR  );
+REG64( C_7_CPLT_CTRL0_CLEAR                                    , RULL(0x27000020), SH_UNT_C_7      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_8_CPLT_CTRL0                                          , RULL(0x28000000), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPLT_CTRL0_OR                                       , RULL(0x28000010), SH_UNT_C_8      , SH_ACS_SCOM1_OR  );
+REG64( C_8_CPLT_CTRL0_CLEAR                                    , RULL(0x28000020), SH_UNT_C_8      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_9_CPLT_CTRL0                                          , RULL(0x29000000), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPLT_CTRL0_OR                                       , RULL(0x29000010), SH_UNT_C_9      , SH_ACS_SCOM1_OR  );
+REG64( C_9_CPLT_CTRL0_CLEAR                                    , RULL(0x29000020), SH_UNT_C_9      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_10_CPLT_CTRL0                                         , RULL(0x2A000000), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_CPLT_CTRL0_OR                                      , RULL(0x2A000010), SH_UNT_C_10     , SH_ACS_SCOM1_OR  );
+REG64( C_10_CPLT_CTRL0_CLEAR                                   , RULL(0x2A000020), SH_UNT_C_10     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_11_CPLT_CTRL0                                         , RULL(0x2B000000), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPLT_CTRL0_OR                                      , RULL(0x2B000010), SH_UNT_C_11     , SH_ACS_SCOM1_OR  );
+REG64( C_11_CPLT_CTRL0_CLEAR                                   , RULL(0x2B000020), SH_UNT_C_11     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_12_CPLT_CTRL0                                         , RULL(0x2C000000), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPLT_CTRL0_OR                                      , RULL(0x2C000010), SH_UNT_C_12     , SH_ACS_SCOM1_OR  );
+REG64( C_12_CPLT_CTRL0_CLEAR                                   , RULL(0x2C000020), SH_UNT_C_12     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_13_CPLT_CTRL0                                         , RULL(0x2D000000), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPLT_CTRL0_OR                                      , RULL(0x2D000010), SH_UNT_C_13     , SH_ACS_SCOM1_OR  );
+REG64( C_13_CPLT_CTRL0_CLEAR                                   , RULL(0x2D000020), SH_UNT_C_13     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_14_CPLT_CTRL0                                         , RULL(0x2E000000), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPLT_CTRL0_OR                                      , RULL(0x2E000010), SH_UNT_C_14     , SH_ACS_SCOM1_OR  );
+REG64( C_14_CPLT_CTRL0_CLEAR                                   , RULL(0x2E000020), SH_UNT_C_14     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_15_CPLT_CTRL0                                         , RULL(0x2F000000), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPLT_CTRL0_OR                                      , RULL(0x2F000010), SH_UNT_C_15     , SH_ACS_SCOM1_OR  );
+REG64( C_15_CPLT_CTRL0_CLEAR                                   , RULL(0x2F000020), SH_UNT_C_15     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_16_CPLT_CTRL0                                         , RULL(0x30000000), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPLT_CTRL0_OR                                      , RULL(0x30000010), SH_UNT_C_16     , SH_ACS_SCOM1_OR  );
+REG64( C_16_CPLT_CTRL0_CLEAR                                   , RULL(0x30000020), SH_UNT_C_16     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_17_CPLT_CTRL0                                         , RULL(0x31000000), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPLT_CTRL0_OR                                      , RULL(0x31000010), SH_UNT_C_17     , SH_ACS_SCOM1_OR  );
+REG64( C_17_CPLT_CTRL0_CLEAR                                   , RULL(0x31000020), SH_UNT_C_17     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_18_CPLT_CTRL0                                         , RULL(0x32000000), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPLT_CTRL0_OR                                      , RULL(0x32000010), SH_UNT_C_18     , SH_ACS_SCOM1_OR  );
+REG64( C_18_CPLT_CTRL0_CLEAR                                   , RULL(0x32000020), SH_UNT_C_18     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_19_CPLT_CTRL0                                         , RULL(0x33000000), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPLT_CTRL0_OR                                      , RULL(0x33000010), SH_UNT_C_19     , SH_ACS_SCOM1_OR  );
+REG64( C_19_CPLT_CTRL0_CLEAR                                   , RULL(0x33000020), SH_UNT_C_19     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_20_CPLT_CTRL0                                         , RULL(0x34000000), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPLT_CTRL0_OR                                      , RULL(0x34000010), SH_UNT_C_20     , SH_ACS_SCOM1_OR  );
+REG64( C_20_CPLT_CTRL0_CLEAR                                   , RULL(0x34000020), SH_UNT_C_20     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_21_CPLT_CTRL0                                         , RULL(0x35000000), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPLT_CTRL0_OR                                      , RULL(0x35000010), SH_UNT_C_21     , SH_ACS_SCOM1_OR  );
+REG64( C_21_CPLT_CTRL0_CLEAR                                   , RULL(0x35000020), SH_UNT_C_21     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_22_CPLT_CTRL0                                         , RULL(0x36000000), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPLT_CTRL0_OR                                      , RULL(0x36000010), SH_UNT_C_22     , SH_ACS_SCOM1_OR  );
+REG64( C_22_CPLT_CTRL0_CLEAR                                   , RULL(0x36000020), SH_UNT_C_22     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_23_CPLT_CTRL0                                         , RULL(0x37000000), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPLT_CTRL0_OR                                      , RULL(0x37000010), SH_UNT_C_23     , SH_ACS_SCOM1_OR  );
+REG64( C_23_CPLT_CTRL0_CLEAR                                   , RULL(0x37000020), SH_UNT_C_23     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_CPLT_CTRL0                                           , RULL(0x10000000), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_CPLT_CTRL0_OR                                        , RULL(0x10000010), SH_UNT_EQ       , SH_ACS_SCOM1_OR  );
+REG64( EQ_CPLT_CTRL0_CLEAR                                     , RULL(0x10000020), SH_UNT_EQ       ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_0_CPLT_CTRL0                                         , RULL(0x10000000), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_0_CPLT_CTRL0_OR                                      , RULL(0x10000010), SH_UNT_EQ_0     , SH_ACS_SCOM1_OR  );
+REG64( EQ_0_CPLT_CTRL0_CLEAR                                   , RULL(0x10000020), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_1_CPLT_CTRL0                                         , RULL(0x11000000), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_CPLT_CTRL0_OR                                      , RULL(0x11000010), SH_UNT_EQ_1     , SH_ACS_SCOM1_OR  );
+REG64( EQ_1_CPLT_CTRL0_CLEAR                                   , RULL(0x11000020), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_2_CPLT_CTRL0                                         , RULL(0x12000000), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_CPLT_CTRL0_OR                                      , RULL(0x12000010), SH_UNT_EQ_2     , SH_ACS_SCOM1_OR  );
+REG64( EQ_2_CPLT_CTRL0_CLEAR                                   , RULL(0x12000020), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_3_CPLT_CTRL0                                         , RULL(0x13000000), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_CPLT_CTRL0_OR                                      , RULL(0x13000010), SH_UNT_EQ_3     , SH_ACS_SCOM1_OR  );
+REG64( EQ_3_CPLT_CTRL0_CLEAR                                   , RULL(0x13000020), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_4_CPLT_CTRL0                                         , RULL(0x14000000), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_CPLT_CTRL0_OR                                      , RULL(0x14000010), SH_UNT_EQ_4     , SH_ACS_SCOM1_OR  );
+REG64( EQ_4_CPLT_CTRL0_CLEAR                                   , RULL(0x14000020), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_5_CPLT_CTRL0                                         , RULL(0x15000000), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_CPLT_CTRL0_OR                                      , RULL(0x15000010), SH_UNT_EQ_5     , SH_ACS_SCOM1_OR  );
+REG64( EQ_5_CPLT_CTRL0_CLEAR                                   , RULL(0x15000020), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EX_CPLT_CTRL0                                           , RULL(0x20000000), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21000000,
+REG64( EX_CPLT_CTRL0_OR                                        , RULL(0x20000010), SH_UNT_EX       ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 21000010,
+REG64( EX_CPLT_CTRL0_CLEAR                                     , RULL(0x20000020), SH_UNT_EX       ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 21000020,
+REG64( EX_0_CPLT_CTRL0                                         , RULL(0x20000000), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21000000,
+REG64( EX_0_CPLT_CTRL0_OR                                      , RULL(0x20000010), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 21000010,
+REG64( EX_0_CPLT_CTRL0_CLEAR                                   , RULL(0x20000020), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 21000020,
+REG64( EX_1_CPLT_CTRL0                                         , RULL(0x22000000), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23000000,
+REG64( EX_1_CPLT_CTRL0_OR                                      , RULL(0x22000010), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 23000010,
+REG64( EX_1_CPLT_CTRL0_CLEAR                                   , RULL(0x22000020), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 23000020,
+REG64( EX_2_CPLT_CTRL0                                         , RULL(0x24000000), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25000000,
+REG64( EX_2_CPLT_CTRL0_OR                                      , RULL(0x24000010), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 25000010,
+REG64( EX_2_CPLT_CTRL0_CLEAR                                   , RULL(0x24000020), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 25000020,
+REG64( EX_3_CPLT_CTRL0                                         , RULL(0x26000000), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27000000,
+REG64( EX_3_CPLT_CTRL0_OR                                      , RULL(0x26000010), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 27000010,
+REG64( EX_3_CPLT_CTRL0_CLEAR                                   , RULL(0x26000020), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 27000020,
+REG64( EX_4_CPLT_CTRL0                                         , RULL(0x28000000), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29000000,
+REG64( EX_4_CPLT_CTRL0_OR                                      , RULL(0x28000010), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 29000010,
+REG64( EX_4_CPLT_CTRL0_CLEAR                                   , RULL(0x28000020), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 29000020,
+REG64( EX_5_CPLT_CTRL0                                         , RULL(0x2A000000), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B000000,
+REG64( EX_5_CPLT_CTRL0_OR                                      , RULL(0x2A000010), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 2B000010,
+REG64( EX_5_CPLT_CTRL0_CLEAR                                   , RULL(0x2A000020), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 2B000020,
+REG64( EX_6_CPLT_CTRL0                                         , RULL(0x2C000000), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D000000,
+REG64( EX_6_CPLT_CTRL0_OR                                      , RULL(0x2C000010), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 2D000010,
+REG64( EX_6_CPLT_CTRL0_CLEAR                                   , RULL(0x2C000020), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 2D000020,
+REG64( EX_7_CPLT_CTRL0                                         , RULL(0x2E000000), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F000000,
+REG64( EX_7_CPLT_CTRL0_OR                                      , RULL(0x2E000010), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 2F000010,
+REG64( EX_7_CPLT_CTRL0_CLEAR                                   , RULL(0x2E000020), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 2F000020,
+REG64( EX_8_CPLT_CTRL0                                         , RULL(0x30000000), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31000000,
+REG64( EX_8_CPLT_CTRL0_OR                                      , RULL(0x30000010), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 31000010,
+REG64( EX_8_CPLT_CTRL0_CLEAR                                   , RULL(0x30000020), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 31000020,
+REG64( EX_9_CPLT_CTRL0                                         , RULL(0x32000000), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33000000,
+REG64( EX_9_CPLT_CTRL0_OR                                      , RULL(0x32000010), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 33000010,
+REG64( EX_9_CPLT_CTRL0_CLEAR                                   , RULL(0x32000020), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 33000020,
+REG64( EX_10_CPLT_CTRL0                                        , RULL(0x34000000), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35000000,
+REG64( EX_10_CPLT_CTRL0_OR                                     , RULL(0x34000010), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 35000010,
+REG64( EX_10_CPLT_CTRL0_CLEAR                                  , RULL(0x34000020), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 35000020,
+REG64( EX_11_CPLT_CTRL0                                        , RULL(0x36000000), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37000000,
+REG64( EX_11_CPLT_CTRL0_OR                                     , RULL(0x36000010), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 37000010,
+REG64( EX_11_CPLT_CTRL0_CLEAR                                  , RULL(0x36000020), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 37000020,
+
+REG64( C_CPLT_CTRL1                                            , RULL(0x20000001), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_CPLT_CTRL1_OR                                         , RULL(0x20000011), SH_UNT_C        , SH_ACS_SCOM1_OR  );
+REG64( C_CPLT_CTRL1_CLEAR                                      , RULL(0x20000021), SH_UNT_C        ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_0_CPLT_CTRL1                                          , RULL(0x20000001), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_CPLT_CTRL1_OR                                       , RULL(0x20000011), SH_UNT_C_0      , SH_ACS_SCOM1_OR  );
+REG64( C_0_CPLT_CTRL1_CLEAR                                    , RULL(0x20000021), SH_UNT_C_0      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_1_CPLT_CTRL1                                          , RULL(0x21000001), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPLT_CTRL1_OR                                       , RULL(0x21000011), SH_UNT_C_1      , SH_ACS_SCOM1_OR  );
+REG64( C_1_CPLT_CTRL1_CLEAR                                    , RULL(0x21000021), SH_UNT_C_1      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_2_CPLT_CTRL1                                          , RULL(0x22000001), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPLT_CTRL1_OR                                       , RULL(0x22000011), SH_UNT_C_2      , SH_ACS_SCOM1_OR  );
+REG64( C_2_CPLT_CTRL1_CLEAR                                    , RULL(0x22000021), SH_UNT_C_2      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_3_CPLT_CTRL1                                          , RULL(0x23000001), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPLT_CTRL1_OR                                       , RULL(0x23000011), SH_UNT_C_3      , SH_ACS_SCOM1_OR  );
+REG64( C_3_CPLT_CTRL1_CLEAR                                    , RULL(0x23000021), SH_UNT_C_3      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_4_CPLT_CTRL1                                          , RULL(0x24000001), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPLT_CTRL1_OR                                       , RULL(0x24000011), SH_UNT_C_4      , SH_ACS_SCOM1_OR  );
+REG64( C_4_CPLT_CTRL1_CLEAR                                    , RULL(0x24000021), SH_UNT_C_4      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_5_CPLT_CTRL1                                          , RULL(0x25000001), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPLT_CTRL1_OR                                       , RULL(0x25000011), SH_UNT_C_5      , SH_ACS_SCOM1_OR  );
+REG64( C_5_CPLT_CTRL1_CLEAR                                    , RULL(0x25000021), SH_UNT_C_5      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_6_CPLT_CTRL1                                          , RULL(0x26000001), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPLT_CTRL1_OR                                       , RULL(0x26000011), SH_UNT_C_6      , SH_ACS_SCOM1_OR  );
+REG64( C_6_CPLT_CTRL1_CLEAR                                    , RULL(0x26000021), SH_UNT_C_6      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_7_CPLT_CTRL1                                          , RULL(0x27000001), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPLT_CTRL1_OR                                       , RULL(0x27000011), SH_UNT_C_7      , SH_ACS_SCOM1_OR  );
+REG64( C_7_CPLT_CTRL1_CLEAR                                    , RULL(0x27000021), SH_UNT_C_7      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_8_CPLT_CTRL1                                          , RULL(0x28000001), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPLT_CTRL1_OR                                       , RULL(0x28000011), SH_UNT_C_8      , SH_ACS_SCOM1_OR  );
+REG64( C_8_CPLT_CTRL1_CLEAR                                    , RULL(0x28000021), SH_UNT_C_8      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_9_CPLT_CTRL1                                          , RULL(0x29000001), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPLT_CTRL1_OR                                       , RULL(0x29000011), SH_UNT_C_9      , SH_ACS_SCOM1_OR  );
+REG64( C_9_CPLT_CTRL1_CLEAR                                    , RULL(0x29000021), SH_UNT_C_9      ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_10_CPLT_CTRL1                                         , RULL(0x2A000001), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_CPLT_CTRL1_OR                                      , RULL(0x2A000011), SH_UNT_C_10     , SH_ACS_SCOM1_OR  );
+REG64( C_10_CPLT_CTRL1_CLEAR                                   , RULL(0x2A000021), SH_UNT_C_10     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_11_CPLT_CTRL1                                         , RULL(0x2B000001), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPLT_CTRL1_OR                                      , RULL(0x2B000011), SH_UNT_C_11     , SH_ACS_SCOM1_OR  );
+REG64( C_11_CPLT_CTRL1_CLEAR                                   , RULL(0x2B000021), SH_UNT_C_11     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_12_CPLT_CTRL1                                         , RULL(0x2C000001), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPLT_CTRL1_OR                                      , RULL(0x2C000011), SH_UNT_C_12     , SH_ACS_SCOM1_OR  );
+REG64( C_12_CPLT_CTRL1_CLEAR                                   , RULL(0x2C000021), SH_UNT_C_12     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_13_CPLT_CTRL1                                         , RULL(0x2D000001), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPLT_CTRL1_OR                                      , RULL(0x2D000011), SH_UNT_C_13     , SH_ACS_SCOM1_OR  );
+REG64( C_13_CPLT_CTRL1_CLEAR                                   , RULL(0x2D000021), SH_UNT_C_13     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_14_CPLT_CTRL1                                         , RULL(0x2E000001), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPLT_CTRL1_OR                                      , RULL(0x2E000011), SH_UNT_C_14     , SH_ACS_SCOM1_OR  );
+REG64( C_14_CPLT_CTRL1_CLEAR                                   , RULL(0x2E000021), SH_UNT_C_14     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_15_CPLT_CTRL1                                         , RULL(0x2F000001), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPLT_CTRL1_OR                                      , RULL(0x2F000011), SH_UNT_C_15     , SH_ACS_SCOM1_OR  );
+REG64( C_15_CPLT_CTRL1_CLEAR                                   , RULL(0x2F000021), SH_UNT_C_15     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_16_CPLT_CTRL1                                         , RULL(0x30000001), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPLT_CTRL1_OR                                      , RULL(0x30000011), SH_UNT_C_16     , SH_ACS_SCOM1_OR  );
+REG64( C_16_CPLT_CTRL1_CLEAR                                   , RULL(0x30000021), SH_UNT_C_16     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_17_CPLT_CTRL1                                         , RULL(0x31000001), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPLT_CTRL1_OR                                      , RULL(0x31000011), SH_UNT_C_17     , SH_ACS_SCOM1_OR  );
+REG64( C_17_CPLT_CTRL1_CLEAR                                   , RULL(0x31000021), SH_UNT_C_17     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_18_CPLT_CTRL1                                         , RULL(0x32000001), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPLT_CTRL1_OR                                      , RULL(0x32000011), SH_UNT_C_18     , SH_ACS_SCOM1_OR  );
+REG64( C_18_CPLT_CTRL1_CLEAR                                   , RULL(0x32000021), SH_UNT_C_18     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_19_CPLT_CTRL1                                         , RULL(0x33000001), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPLT_CTRL1_OR                                      , RULL(0x33000011), SH_UNT_C_19     , SH_ACS_SCOM1_OR  );
+REG64( C_19_CPLT_CTRL1_CLEAR                                   , RULL(0x33000021), SH_UNT_C_19     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_20_CPLT_CTRL1                                         , RULL(0x34000001), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPLT_CTRL1_OR                                      , RULL(0x34000011), SH_UNT_C_20     , SH_ACS_SCOM1_OR  );
+REG64( C_20_CPLT_CTRL1_CLEAR                                   , RULL(0x34000021), SH_UNT_C_20     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_21_CPLT_CTRL1                                         , RULL(0x35000001), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPLT_CTRL1_OR                                      , RULL(0x35000011), SH_UNT_C_21     , SH_ACS_SCOM1_OR  );
+REG64( C_21_CPLT_CTRL1_CLEAR                                   , RULL(0x35000021), SH_UNT_C_21     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_22_CPLT_CTRL1                                         , RULL(0x36000001), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPLT_CTRL1_OR                                      , RULL(0x36000011), SH_UNT_C_22     , SH_ACS_SCOM1_OR  );
+REG64( C_22_CPLT_CTRL1_CLEAR                                   , RULL(0x36000021), SH_UNT_C_22     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( C_23_CPLT_CTRL1                                         , RULL(0x37000001), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPLT_CTRL1_OR                                      , RULL(0x37000011), SH_UNT_C_23     , SH_ACS_SCOM1_OR  );
+REG64( C_23_CPLT_CTRL1_CLEAR                                   , RULL(0x37000021), SH_UNT_C_23     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_CPLT_CTRL1                                           , RULL(0x10000001), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_CPLT_CTRL1_OR                                        , RULL(0x10000011), SH_UNT_EQ       , SH_ACS_SCOM1_OR  );
+REG64( EQ_CPLT_CTRL1_CLEAR                                     , RULL(0x10000021), SH_UNT_EQ       ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_0_CPLT_CTRL1                                         , RULL(0x10000001), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_0_CPLT_CTRL1_OR                                      , RULL(0x10000011), SH_UNT_EQ_0     , SH_ACS_SCOM1_OR  );
+REG64( EQ_0_CPLT_CTRL1_CLEAR                                   , RULL(0x10000021), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_1_CPLT_CTRL1                                         , RULL(0x11000001), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_CPLT_CTRL1_OR                                      , RULL(0x11000011), SH_UNT_EQ_1     , SH_ACS_SCOM1_OR  );
+REG64( EQ_1_CPLT_CTRL1_CLEAR                                   , RULL(0x11000021), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_2_CPLT_CTRL1                                         , RULL(0x12000001), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_CPLT_CTRL1_OR                                      , RULL(0x12000011), SH_UNT_EQ_2     , SH_ACS_SCOM1_OR  );
+REG64( EQ_2_CPLT_CTRL1_CLEAR                                   , RULL(0x12000021), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_3_CPLT_CTRL1                                         , RULL(0x13000001), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_CPLT_CTRL1_OR                                      , RULL(0x13000011), SH_UNT_EQ_3     , SH_ACS_SCOM1_OR  );
+REG64( EQ_3_CPLT_CTRL1_CLEAR                                   , RULL(0x13000021), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_4_CPLT_CTRL1                                         , RULL(0x14000001), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_CPLT_CTRL1_OR                                      , RULL(0x14000011), SH_UNT_EQ_4     , SH_ACS_SCOM1_OR  );
+REG64( EQ_4_CPLT_CTRL1_CLEAR                                   , RULL(0x14000021), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EQ_5_CPLT_CTRL1                                         , RULL(0x15000001), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_CPLT_CTRL1_OR                                      , RULL(0x15000011), SH_UNT_EQ_5     , SH_ACS_SCOM1_OR  );
+REG64( EQ_5_CPLT_CTRL1_CLEAR                                   , RULL(0x15000021), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM2_CLEAR );
+REG64( EX_CPLT_CTRL1                                           , RULL(0x20000001), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21000001,
+REG64( EX_CPLT_CTRL1_OR                                        , RULL(0x20000011), SH_UNT_EX       ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 21000011,
+REG64( EX_CPLT_CTRL1_CLEAR                                     , RULL(0x20000021), SH_UNT_EX       ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 21000021,
+REG64( EX_0_CPLT_CTRL1                                         , RULL(0x20000001), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21000001,
+REG64( EX_0_CPLT_CTRL1_OR                                      , RULL(0x20000011), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 21000011,
+REG64( EX_0_CPLT_CTRL1_CLEAR                                   , RULL(0x20000021), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 21000021,
+REG64( EX_1_CPLT_CTRL1                                         , RULL(0x22000001), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23000001,
+REG64( EX_1_CPLT_CTRL1_OR                                      , RULL(0x22000011), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 23000011,
+REG64( EX_1_CPLT_CTRL1_CLEAR                                   , RULL(0x22000021), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 23000021,
+REG64( EX_2_CPLT_CTRL1                                         , RULL(0x24000001), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25000001,
+REG64( EX_2_CPLT_CTRL1_OR                                      , RULL(0x24000011), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 25000011,
+REG64( EX_2_CPLT_CTRL1_CLEAR                                   , RULL(0x24000021), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 25000021,
+REG64( EX_3_CPLT_CTRL1                                         , RULL(0x26000001), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27000001,
+REG64( EX_3_CPLT_CTRL1_OR                                      , RULL(0x26000011), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 27000011,
+REG64( EX_3_CPLT_CTRL1_CLEAR                                   , RULL(0x26000021), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 27000021,
+REG64( EX_4_CPLT_CTRL1                                         , RULL(0x28000001), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29000001,
+REG64( EX_4_CPLT_CTRL1_OR                                      , RULL(0x28000011), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 29000011,
+REG64( EX_4_CPLT_CTRL1_CLEAR                                   , RULL(0x28000021), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 29000021,
+REG64( EX_5_CPLT_CTRL1                                         , RULL(0x2A000001), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B000001,
+REG64( EX_5_CPLT_CTRL1_OR                                      , RULL(0x2A000011), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 2B000011,
+REG64( EX_5_CPLT_CTRL1_CLEAR                                   , RULL(0x2A000021), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 2B000021,
+REG64( EX_6_CPLT_CTRL1                                         , RULL(0x2C000001), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D000001,
+REG64( EX_6_CPLT_CTRL1_OR                                      , RULL(0x2C000011), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 2D000011,
+REG64( EX_6_CPLT_CTRL1_CLEAR                                   , RULL(0x2C000021), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 2D000021,
+REG64( EX_7_CPLT_CTRL1                                         , RULL(0x2E000001), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F000001,
+REG64( EX_7_CPLT_CTRL1_OR                                      , RULL(0x2E000011), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 2F000011,
+REG64( EX_7_CPLT_CTRL1_CLEAR                                   , RULL(0x2E000021), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 2F000021,
+REG64( EX_8_CPLT_CTRL1                                         , RULL(0x30000001), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31000001,
+REG64( EX_8_CPLT_CTRL1_OR                                      , RULL(0x30000011), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 31000011,
+REG64( EX_8_CPLT_CTRL1_CLEAR                                   , RULL(0x30000021), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 31000021,
+REG64( EX_9_CPLT_CTRL1                                         , RULL(0x32000001), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33000001,
+REG64( EX_9_CPLT_CTRL1_OR                                      , RULL(0x32000011), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 33000011,
+REG64( EX_9_CPLT_CTRL1_CLEAR                                   , RULL(0x32000021), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 33000021,
+REG64( EX_10_CPLT_CTRL1                                        , RULL(0x34000001), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35000001,
+REG64( EX_10_CPLT_CTRL1_OR                                     , RULL(0x34000011), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 35000011,
+REG64( EX_10_CPLT_CTRL1_CLEAR                                  , RULL(0x34000021), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 35000021,
+REG64( EX_11_CPLT_CTRL1                                        , RULL(0x36000001), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37000001,
+REG64( EX_11_CPLT_CTRL1_OR                                     , RULL(0x36000011), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_OR  ); //DUPS: 37000011,
+REG64( EX_11_CPLT_CTRL1_CLEAR                                  , RULL(0x36000021), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_CLEAR ); //DUPS: 37000021,
+
+REG64( C_CPLT_MASK0                                            , RULL(0x20000101), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_CPLT_MASK0                                          , RULL(0x20000101), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_CPLT_MASK0                                          , RULL(0x21000101), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_CPLT_MASK0                                          , RULL(0x22000101), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_CPLT_MASK0                                          , RULL(0x23000101), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_CPLT_MASK0                                          , RULL(0x24000101), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_CPLT_MASK0                                          , RULL(0x25000101), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_CPLT_MASK0                                          , RULL(0x26000101), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_CPLT_MASK0                                          , RULL(0x27000101), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_CPLT_MASK0                                          , RULL(0x28000101), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_CPLT_MASK0                                          , RULL(0x29000101), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_CPLT_MASK0                                         , RULL(0x2A000101), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_CPLT_MASK0                                         , RULL(0x2B000101), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_CPLT_MASK0                                         , RULL(0x2C000101), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_CPLT_MASK0                                         , RULL(0x2D000101), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_CPLT_MASK0                                         , RULL(0x2E000101), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_CPLT_MASK0                                         , RULL(0x2F000101), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_CPLT_MASK0                                         , RULL(0x30000101), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_CPLT_MASK0                                         , RULL(0x31000101), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_CPLT_MASK0                                         , RULL(0x32000101), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_CPLT_MASK0                                         , RULL(0x33000101), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_CPLT_MASK0                                         , RULL(0x34000101), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_CPLT_MASK0                                         , RULL(0x35000101), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_CPLT_MASK0                                         , RULL(0x36000101), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_CPLT_MASK0                                         , RULL(0x37000101), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_CPLT_MASK0                                           , RULL(0x10000101), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_CPLT_MASK0                                         , RULL(0x10000101), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_CPLT_MASK0                                         , RULL(0x11000101), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_CPLT_MASK0                                         , RULL(0x12000101), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_CPLT_MASK0                                         , RULL(0x13000101), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_CPLT_MASK0                                         , RULL(0x14000101), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_CPLT_MASK0                                         , RULL(0x15000101), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_CPLT_MASK0                                           , RULL(0x20000101), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21000101,
+REG64( EX_0_CPLT_MASK0                                         , RULL(0x20000101), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21000101,
+REG64( EX_1_CPLT_MASK0                                         , RULL(0x22000101), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23000101,
+REG64( EX_2_CPLT_MASK0                                         , RULL(0x24000101), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25000101,
+REG64( EX_3_CPLT_MASK0                                         , RULL(0x26000101), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27000101,
+REG64( EX_4_CPLT_MASK0                                         , RULL(0x28000101), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29000101,
+REG64( EX_5_CPLT_MASK0                                         , RULL(0x2A000101), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B000101,
+REG64( EX_6_CPLT_MASK0                                         , RULL(0x2C000101), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D000101,
+REG64( EX_7_CPLT_MASK0                                         , RULL(0x2E000101), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F000101,
+REG64( EX_8_CPLT_MASK0                                         , RULL(0x30000101), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31000101,
+REG64( EX_9_CPLT_MASK0                                         , RULL(0x32000101), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33000101,
+REG64( EX_10_CPLT_MASK0                                        , RULL(0x34000101), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35000101,
+REG64( EX_11_CPLT_MASK0                                        , RULL(0x36000101), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37000101,
+
+REG64( C_CPLT_STAT0                                            , RULL(0x20000100), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_CPLT_STAT0                                          , RULL(0x20000100), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_CPLT_STAT0                                          , RULL(0x21000100), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_CPLT_STAT0                                          , RULL(0x22000100), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_CPLT_STAT0                                          , RULL(0x23000100), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_CPLT_STAT0                                          , RULL(0x24000100), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_CPLT_STAT0                                          , RULL(0x25000100), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_CPLT_STAT0                                          , RULL(0x26000100), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_CPLT_STAT0                                          , RULL(0x27000100), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_CPLT_STAT0                                          , RULL(0x28000100), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_CPLT_STAT0                                          , RULL(0x29000100), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_CPLT_STAT0                                         , RULL(0x2A000100), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_CPLT_STAT0                                         , RULL(0x2B000100), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_CPLT_STAT0                                         , RULL(0x2C000100), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_CPLT_STAT0                                         , RULL(0x2D000100), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_CPLT_STAT0                                         , RULL(0x2E000100), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_CPLT_STAT0                                         , RULL(0x2F000100), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_CPLT_STAT0                                         , RULL(0x30000100), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_CPLT_STAT0                                         , RULL(0x31000100), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_CPLT_STAT0                                         , RULL(0x32000100), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_CPLT_STAT0                                         , RULL(0x33000100), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_CPLT_STAT0                                         , RULL(0x34000100), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_CPLT_STAT0                                         , RULL(0x35000100), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_CPLT_STAT0                                         , RULL(0x36000100), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_CPLT_STAT0                                         , RULL(0x37000100), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_CPLT_STAT0                                           , RULL(0x10000100), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_CPLT_STAT0                                         , RULL(0x10000100), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_CPLT_STAT0                                         , RULL(0x11000100), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_CPLT_STAT0                                         , RULL(0x12000100), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_CPLT_STAT0                                         , RULL(0x13000100), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_CPLT_STAT0                                         , RULL(0x14000100), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_CPLT_STAT0                                         , RULL(0x15000100), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_CPLT_STAT0                                           , RULL(0x20000100), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21000100,
+REG64( EX_0_CPLT_STAT0                                         , RULL(0x20000100), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21000100,
+REG64( EX_1_CPLT_STAT0                                         , RULL(0x22000100), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23000100,
+REG64( EX_2_CPLT_STAT0                                         , RULL(0x24000100), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25000100,
+REG64( EX_3_CPLT_STAT0                                         , RULL(0x26000100), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27000100,
+REG64( EX_4_CPLT_STAT0                                         , RULL(0x28000100), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29000100,
+REG64( EX_5_CPLT_STAT0                                         , RULL(0x2A000100), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B000100,
+REG64( EX_6_CPLT_STAT0                                         , RULL(0x2C000100), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D000100,
+REG64( EX_7_CPLT_STAT0                                         , RULL(0x2E000100), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F000100,
+REG64( EX_8_CPLT_STAT0                                         , RULL(0x30000100), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31000100,
+REG64( EX_9_CPLT_STAT0                                         , RULL(0x32000100), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33000100,
+REG64( EX_10_CPLT_STAT0                                        , RULL(0x34000100), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35000100,
+REG64( EX_11_CPLT_STAT0                                        , RULL(0x36000100), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37000100,
+
+REG64( C_CPPM_CACCR                                            , RULL(0x200F0168), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_CPPM_CACCR_CLEAR                                      , RULL(0x200F0169), SH_UNT_C        ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_CPPM_CACCR_OR                                         , RULL(0x200F016A), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_CPPM_CACCR                                          , RULL(0x200F0168), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_CPPM_CACCR_CLEAR                                    , RULL(0x200F0169), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_0_CPPM_CACCR_OR                                       , RULL(0x200F016A), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_CPPM_CACCR                                          , RULL(0x210F0168), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPPM_CACCR_CLEAR                                    , RULL(0x210F0169), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_1_CPPM_CACCR_OR                                       , RULL(0x210F016A), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_CPPM_CACCR                                          , RULL(0x220F0168), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPPM_CACCR_CLEAR                                    , RULL(0x220F0169), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_2_CPPM_CACCR_OR                                       , RULL(0x220F016A), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_CPPM_CACCR                                          , RULL(0x230F0168), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPPM_CACCR_CLEAR                                    , RULL(0x230F0169), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_3_CPPM_CACCR_OR                                       , RULL(0x230F016A), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_CPPM_CACCR                                          , RULL(0x240F0168), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPPM_CACCR_CLEAR                                    , RULL(0x240F0169), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_4_CPPM_CACCR_OR                                       , RULL(0x240F016A), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_CPPM_CACCR                                          , RULL(0x250F0168), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPPM_CACCR_CLEAR                                    , RULL(0x250F0169), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_5_CPPM_CACCR_OR                                       , RULL(0x250F016A), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_CPPM_CACCR                                          , RULL(0x260F0168), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPPM_CACCR_CLEAR                                    , RULL(0x260F0169), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_6_CPPM_CACCR_OR                                       , RULL(0x260F016A), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_CPPM_CACCR                                          , RULL(0x270F0168), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPPM_CACCR_CLEAR                                    , RULL(0x270F0169), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_7_CPPM_CACCR_OR                                       , RULL(0x270F016A), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_CPPM_CACCR                                          , RULL(0x280F0168), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPPM_CACCR_CLEAR                                    , RULL(0x280F0169), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_8_CPPM_CACCR_OR                                       , RULL(0x280F016A), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_CPPM_CACCR                                          , RULL(0x290F0168), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPPM_CACCR_CLEAR                                    , RULL(0x290F0169), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_9_CPPM_CACCR_OR                                       , RULL(0x290F016A), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_CPPM_CACCR                                         , RULL(0x2A0F0168), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_CPPM_CACCR_CLEAR                                   , RULL(0x2A0F0169), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_10_CPPM_CACCR_OR                                      , RULL(0x2A0F016A), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_CPPM_CACCR                                         , RULL(0x2B0F0168), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPPM_CACCR_CLEAR                                   , RULL(0x2B0F0169), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_11_CPPM_CACCR_OR                                      , RULL(0x2B0F016A), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_CPPM_CACCR                                         , RULL(0x2C0F0168), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPPM_CACCR_CLEAR                                   , RULL(0x2C0F0169), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_12_CPPM_CACCR_OR                                      , RULL(0x2C0F016A), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_CPPM_CACCR                                         , RULL(0x2D0F0168), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPPM_CACCR_CLEAR                                   , RULL(0x2D0F0169), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_13_CPPM_CACCR_OR                                      , RULL(0x2D0F016A), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_CPPM_CACCR                                         , RULL(0x2E0F0168), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPPM_CACCR_CLEAR                                   , RULL(0x2E0F0169), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_14_CPPM_CACCR_OR                                      , RULL(0x2E0F016A), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_CPPM_CACCR                                         , RULL(0x2F0F0168), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPPM_CACCR_CLEAR                                   , RULL(0x2F0F0169), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_15_CPPM_CACCR_OR                                      , RULL(0x2F0F016A), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_CPPM_CACCR                                         , RULL(0x300F0168), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPPM_CACCR_CLEAR                                   , RULL(0x300F0169), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_16_CPPM_CACCR_OR                                      , RULL(0x300F016A), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_CPPM_CACCR                                         , RULL(0x310F0168), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPPM_CACCR_CLEAR                                   , RULL(0x310F0169), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_17_CPPM_CACCR_OR                                      , RULL(0x310F016A), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_CPPM_CACCR                                         , RULL(0x320F0168), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPPM_CACCR_CLEAR                                   , RULL(0x320F0169), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_18_CPPM_CACCR_OR                                      , RULL(0x320F016A), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_CPPM_CACCR                                         , RULL(0x330F0168), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPPM_CACCR_CLEAR                                   , RULL(0x330F0169), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_19_CPPM_CACCR_OR                                      , RULL(0x330F016A), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_CPPM_CACCR                                         , RULL(0x340F0168), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPPM_CACCR_CLEAR                                   , RULL(0x340F0169), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_20_CPPM_CACCR_OR                                      , RULL(0x340F016A), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_CPPM_CACCR                                         , RULL(0x350F0168), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPPM_CACCR_CLEAR                                   , RULL(0x350F0169), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_21_CPPM_CACCR_OR                                      , RULL(0x350F016A), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_CPPM_CACCR                                         , RULL(0x360F0168), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPPM_CACCR_CLEAR                                   , RULL(0x360F0169), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_22_CPPM_CACCR_OR                                      , RULL(0x360F016A), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_CPPM_CACCR                                         , RULL(0x370F0168), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPPM_CACCR_CLEAR                                   , RULL(0x370F0169), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_23_CPPM_CACCR_OR                                      , RULL(0x370F016A), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EX_CPPM_CACCR                                           , RULL(0x200F0168), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0168,
+REG64( EX_CPPM_CACCR_CLEAR                                     , RULL(0x200F0169), SH_UNT_EX       ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0169,
+REG64( EX_CPPM_CACCR_OR                                        , RULL(0x200F016A), SH_UNT_EX       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F016A,
+REG64( EX_0_CPPM_CACCR                                         , RULL(0x200F0168), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0168,
+REG64( EX_0_CPPM_CACCR_CLEAR                                   , RULL(0x200F0169), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0169,
+REG64( EX_0_CPPM_CACCR_OR                                      , RULL(0x200F016A), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F016A,
+REG64( EX_1_CPPM_CACCR                                         , RULL(0x230F0168), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0168,
+REG64( EX_1_CPPM_CACCR_CLEAR                                   , RULL(0x230F0169), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 220F0169,
+REG64( EX_1_CPPM_CACCR_OR                                      , RULL(0x230F016A), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 220F016A,
+REG64( EX_2_CPPM_CACCR                                         , RULL(0x240F0168), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0168,
+REG64( EX_2_CPPM_CACCR_CLEAR                                   , RULL(0x240F0169), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 250F0169,
+REG64( EX_2_CPPM_CACCR_OR                                      , RULL(0x240F016A), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 250F016A,
+REG64( EX_3_CPPM_CACCR                                         , RULL(0x260F0168), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0168,
+REG64( EX_3_CPPM_CACCR_CLEAR                                   , RULL(0x260F0169), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 270F0169,
+REG64( EX_3_CPPM_CACCR_OR                                      , RULL(0x260F016A), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 270F016A,
+REG64( EX_4_CPPM_CACCR                                         , RULL(0x280F0168), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0168,
+REG64( EX_4_CPPM_CACCR_CLEAR                                   , RULL(0x280F0169), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 290F0169,
+REG64( EX_4_CPPM_CACCR_OR                                      , RULL(0x280F016A), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 290F016A,
+REG64( EX_5_CPPM_CACCR                                         , RULL(0x2A0F0168), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0168,
+REG64( EX_5_CPPM_CACCR_CLEAR                                   , RULL(0x2A0F0169), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2B0F0169,
+REG64( EX_5_CPPM_CACCR_OR                                      , RULL(0x2A0F016A), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2B0F016A,
+REG64( EX_6_CPPM_CACCR                                         , RULL(0x2C0F0168), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0168,
+REG64( EX_6_CPPM_CACCR_CLEAR                                   , RULL(0x2C0F0169), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2D0F0169,
+REG64( EX_6_CPPM_CACCR_OR                                      , RULL(0x2C0F016A), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2D0F016A,
+REG64( EX_7_CPPM_CACCR                                         , RULL(0x2E0F0168), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0168,
+REG64( EX_7_CPPM_CACCR_CLEAR                                   , RULL(0x2E0F0169), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2F0F0169,
+REG64( EX_7_CPPM_CACCR_OR                                      , RULL(0x2E0F016A), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2F0F016A,
+REG64( EX_8_CPPM_CACCR                                         , RULL(0x300F0168), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0168,
+REG64( EX_8_CPPM_CACCR_CLEAR                                   , RULL(0x300F0169), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 310F0169,
+REG64( EX_8_CPPM_CACCR_OR                                      , RULL(0x300F016A), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 310F016A,
+REG64( EX_9_CPPM_CACCR                                         , RULL(0x320F0168), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0168,
+REG64( EX_9_CPPM_CACCR_CLEAR                                   , RULL(0x320F0169), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 330F0169,
+REG64( EX_9_CPPM_CACCR_OR                                      , RULL(0x320F016A), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 330F016A,
+REG64( EX_10_CPPM_CACCR                                        , RULL(0x340F0168), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0168,
+REG64( EX_10_CPPM_CACCR_CLEAR                                  , RULL(0x340F0169), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 350F0169,
+REG64( EX_10_CPPM_CACCR_OR                                     , RULL(0x340F016A), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 350F016A,
+REG64( EX_11_CPPM_CACCR                                        , RULL(0x360F0168), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0168,
+REG64( EX_11_CPPM_CACCR_CLEAR                                  , RULL(0x360F0169), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 370F0169,
+REG64( EX_11_CPPM_CACCR_OR                                     , RULL(0x360F016A), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 370F016A,
+
+REG64( C_CPPM_CACSR                                            , RULL(0x200F016B), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_CPPM_CACSR                                          , RULL(0x200F016B), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_CPPM_CACSR                                          , RULL(0x210F016B), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_CPPM_CACSR                                          , RULL(0x220F016B), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_CPPM_CACSR                                          , RULL(0x230F016B), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_CPPM_CACSR                                          , RULL(0x240F016B), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_CPPM_CACSR                                          , RULL(0x250F016B), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_CPPM_CACSR                                          , RULL(0x260F016B), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_CPPM_CACSR                                          , RULL(0x270F016B), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_CPPM_CACSR                                          , RULL(0x280F016B), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_CPPM_CACSR                                          , RULL(0x290F016B), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_CPPM_CACSR                                         , RULL(0x2A0F016B), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_CPPM_CACSR                                         , RULL(0x2B0F016B), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_CPPM_CACSR                                         , RULL(0x2C0F016B), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_CPPM_CACSR                                         , RULL(0x2D0F016B), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_CPPM_CACSR                                         , RULL(0x2E0F016B), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_CPPM_CACSR                                         , RULL(0x2F0F016B), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_CPPM_CACSR                                         , RULL(0x300F016B), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_CPPM_CACSR                                         , RULL(0x310F016B), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_CPPM_CACSR                                         , RULL(0x320F016B), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_CPPM_CACSR                                         , RULL(0x330F016B), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_CPPM_CACSR                                         , RULL(0x340F016B), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_CPPM_CACSR                                         , RULL(0x350F016B), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_CPPM_CACSR                                         , RULL(0x360F016B), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_CPPM_CACSR                                         , RULL(0x370F016B), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_CPPM_CACSR                                           , RULL(0x200F016B), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F016B,
+REG64( EX_0_CPPM_CACSR                                         , RULL(0x200F016B), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F016B,
+REG64( EX_1_CPPM_CACSR                                         , RULL(0x230F016B), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 220F016B,
+REG64( EX_2_CPPM_CACSR                                         , RULL(0x240F016B), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 250F016B,
+REG64( EX_3_CPPM_CACSR                                         , RULL(0x260F016B), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 270F016B,
+REG64( EX_4_CPPM_CACSR                                         , RULL(0x280F016B), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 290F016B,
+REG64( EX_5_CPPM_CACSR                                         , RULL(0x2A0F016B), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B0F016B,
+REG64( EX_6_CPPM_CACSR                                         , RULL(0x2C0F016B), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D0F016B,
+REG64( EX_7_CPPM_CACSR                                         , RULL(0x2E0F016B), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F0F016B,
+REG64( EX_8_CPPM_CACSR                                         , RULL(0x300F016B), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 310F016B,
+REG64( EX_9_CPPM_CACSR                                         , RULL(0x320F016B), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 330F016B,
+REG64( EX_10_CPPM_CACSR                                        , RULL(0x340F016B), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 350F016B,
+REG64( EX_11_CPPM_CACSR                                        , RULL(0x360F016B), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 370F016B,
+
+REG64( C_CPPM_CIIR                                             , RULL(0x200F01AD), SH_UNT_C        , SH_ACS_SCOM_4P   );
+REG64( C_0_CPPM_CIIR                                           , RULL(0x200F01AD), SH_UNT_C_0      , SH_ACS_SCOM_4P   );
+REG64( C_1_CPPM_CIIR                                           , RULL(0x210F01AD), SH_UNT_C_1      , SH_ACS_SCOM_4P   );
+REG64( C_2_CPPM_CIIR                                           , RULL(0x220F01AD), SH_UNT_C_2      , SH_ACS_SCOM_4P   );
+REG64( C_3_CPPM_CIIR                                           , RULL(0x230F01AD), SH_UNT_C_3      , SH_ACS_SCOM_4P   );
+REG64( C_4_CPPM_CIIR                                           , RULL(0x240F01AD), SH_UNT_C_4      , SH_ACS_SCOM_4P   );
+REG64( C_5_CPPM_CIIR                                           , RULL(0x250F01AD), SH_UNT_C_5      , SH_ACS_SCOM_4P   );
+REG64( C_6_CPPM_CIIR                                           , RULL(0x260F01AD), SH_UNT_C_6      , SH_ACS_SCOM_4P   );
+REG64( C_7_CPPM_CIIR                                           , RULL(0x270F01AD), SH_UNT_C_7      , SH_ACS_SCOM_4P   );
+REG64( C_8_CPPM_CIIR                                           , RULL(0x280F01AD), SH_UNT_C_8      , SH_ACS_SCOM_4P   );
+REG64( C_9_CPPM_CIIR                                           , RULL(0x290F01AD), SH_UNT_C_9      , SH_ACS_SCOM_4P   );
+REG64( C_10_CPPM_CIIR                                          , RULL(0x2A0F01AD), SH_UNT_C_10     , SH_ACS_SCOM_4P   );
+REG64( C_11_CPPM_CIIR                                          , RULL(0x2B0F01AD), SH_UNT_C_11     , SH_ACS_SCOM_4P   );
+REG64( C_12_CPPM_CIIR                                          , RULL(0x2C0F01AD), SH_UNT_C_12     , SH_ACS_SCOM_4P   );
+REG64( C_13_CPPM_CIIR                                          , RULL(0x2D0F01AD), SH_UNT_C_13     , SH_ACS_SCOM_4P   );
+REG64( C_14_CPPM_CIIR                                          , RULL(0x2E0F01AD), SH_UNT_C_14     , SH_ACS_SCOM_4P   );
+REG64( C_15_CPPM_CIIR                                          , RULL(0x2F0F01AD), SH_UNT_C_15     , SH_ACS_SCOM_4P   );
+REG64( C_16_CPPM_CIIR                                          , RULL(0x300F01AD), SH_UNT_C_16     , SH_ACS_SCOM_4P   );
+REG64( C_17_CPPM_CIIR                                          , RULL(0x310F01AD), SH_UNT_C_17     , SH_ACS_SCOM_4P   );
+REG64( C_18_CPPM_CIIR                                          , RULL(0x320F01AD), SH_UNT_C_18     , SH_ACS_SCOM_4P   );
+REG64( C_19_CPPM_CIIR                                          , RULL(0x330F01AD), SH_UNT_C_19     , SH_ACS_SCOM_4P   );
+REG64( C_20_CPPM_CIIR                                          , RULL(0x340F01AD), SH_UNT_C_20     , SH_ACS_SCOM_4P   );
+REG64( C_21_CPPM_CIIR                                          , RULL(0x350F01AD), SH_UNT_C_21     , SH_ACS_SCOM_4P   );
+REG64( C_22_CPPM_CIIR                                          , RULL(0x360F01AD), SH_UNT_C_22     , SH_ACS_SCOM_4P   );
+REG64( C_23_CPPM_CIIR                                          , RULL(0x370F01AD), SH_UNT_C_23     , SH_ACS_SCOM_4P   );
+REG64( EX_CPPM_CIIR                                            , RULL(0x200F01AD), SH_UNT_EX       ,
+       SH_ACS_SCOM_4P   ); //DUPS: 210F01AD,
+REG64( EX_0_CPPM_CIIR                                          , RULL(0x200F01AD), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_4P   ); //DUPS: 210F01AD,
+REG64( EX_1_CPPM_CIIR                                          , RULL(0x230F01AD), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_4P   ); //DUPS: 220F01AD,
+REG64( EX_2_CPPM_CIIR                                          , RULL(0x240F01AD), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_4P   ); //DUPS: 250F01AD,
+REG64( EX_3_CPPM_CIIR                                          , RULL(0x260F01AD), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_4P   ); //DUPS: 270F01AD,
+REG64( EX_4_CPPM_CIIR                                          , RULL(0x280F01AD), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_4P   ); //DUPS: 290F01AD,
+REG64( EX_5_CPPM_CIIR                                          , RULL(0x2A0F01AD), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_4P   ); //DUPS: 2B0F01AD,
+REG64( EX_6_CPPM_CIIR                                          , RULL(0x2C0F01AD), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_4P   ); //DUPS: 2D0F01AD,
+REG64( EX_7_CPPM_CIIR                                          , RULL(0x2E0F01AD), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_4P   ); //DUPS: 2F0F01AD,
+REG64( EX_8_CPPM_CIIR                                          , RULL(0x300F01AD), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_4P   ); //DUPS: 310F01AD,
+REG64( EX_9_CPPM_CIIR                                          , RULL(0x320F01AD), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_4P   ); //DUPS: 330F01AD,
+REG64( EX_10_CPPM_CIIR                                         , RULL(0x340F01AD), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_4P   ); //DUPS: 350F01AD,
+REG64( EX_11_CPPM_CIIR                                         , RULL(0x360F01AD), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_4P   ); //DUPS: 370F01AD,
+
+REG64( C_CPPM_CISR                                             , RULL(0x200F01AE), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_CPPM_CISR                                           , RULL(0x200F01AE), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_CPPM_CISR                                           , RULL(0x210F01AE), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_CPPM_CISR                                           , RULL(0x220F01AE), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_CPPM_CISR                                           , RULL(0x230F01AE), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_CPPM_CISR                                           , RULL(0x240F01AE), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_CPPM_CISR                                           , RULL(0x250F01AE), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_CPPM_CISR                                           , RULL(0x260F01AE), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_CPPM_CISR                                           , RULL(0x270F01AE), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_CPPM_CISR                                           , RULL(0x280F01AE), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_CPPM_CISR                                           , RULL(0x290F01AE), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_CPPM_CISR                                          , RULL(0x2A0F01AE), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_CPPM_CISR                                          , RULL(0x2B0F01AE), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_CPPM_CISR                                          , RULL(0x2C0F01AE), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_CPPM_CISR                                          , RULL(0x2D0F01AE), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_CPPM_CISR                                          , RULL(0x2E0F01AE), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_CPPM_CISR                                          , RULL(0x2F0F01AE), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_CPPM_CISR                                          , RULL(0x300F01AE), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_CPPM_CISR                                          , RULL(0x310F01AE), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_CPPM_CISR                                          , RULL(0x320F01AE), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_CPPM_CISR                                          , RULL(0x330F01AE), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_CPPM_CISR                                          , RULL(0x340F01AE), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_CPPM_CISR                                          , RULL(0x350F01AE), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_CPPM_CISR                                          , RULL(0x360F01AE), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_CPPM_CISR                                          , RULL(0x370F01AE), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_CPPM_CISR                                            , RULL(0x200F01AE), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F01AE,
+REG64( EX_0_CPPM_CISR                                          , RULL(0x200F01AE), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F01AE,
+REG64( EX_1_CPPM_CISR                                          , RULL(0x230F01AE), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 220F01AE,
+REG64( EX_2_CPPM_CISR                                          , RULL(0x240F01AE), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 250F01AE,
+REG64( EX_3_CPPM_CISR                                          , RULL(0x260F01AE), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 270F01AE,
+REG64( EX_4_CPPM_CISR                                          , RULL(0x280F01AE), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 290F01AE,
+REG64( EX_5_CPPM_CISR                                          , RULL(0x2A0F01AE), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B0F01AE,
+REG64( EX_6_CPPM_CISR                                          , RULL(0x2C0F01AE), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D0F01AE,
+REG64( EX_7_CPPM_CISR                                          , RULL(0x2E0F01AE), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F0F01AE,
+REG64( EX_8_CPPM_CISR                                          , RULL(0x300F01AE), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 310F01AE,
+REG64( EX_9_CPPM_CISR                                          , RULL(0x320F01AE), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 330F01AE,
+REG64( EX_10_CPPM_CISR                                         , RULL(0x340F01AE), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 350F01AE,
+REG64( EX_11_CPPM_CISR                                         , RULL(0x360F01AE), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 370F01AE,
+
+REG64( C_CPPM_CIVRMLCR                                         , RULL(0x200F01B7), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_CPPM_CIVRMLCR                                       , RULL(0x200F01B7), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPPM_CIVRMLCR                                       , RULL(0x210F01B7), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPPM_CIVRMLCR                                       , RULL(0x220F01B7), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPPM_CIVRMLCR                                       , RULL(0x230F01B7), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPPM_CIVRMLCR                                       , RULL(0x240F01B7), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPPM_CIVRMLCR                                       , RULL(0x250F01B7), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPPM_CIVRMLCR                                       , RULL(0x260F01B7), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPPM_CIVRMLCR                                       , RULL(0x270F01B7), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPPM_CIVRMLCR                                       , RULL(0x280F01B7), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPPM_CIVRMLCR                                       , RULL(0x290F01B7), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_CPPM_CIVRMLCR                                      , RULL(0x2A0F01B7), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPPM_CIVRMLCR                                      , RULL(0x2B0F01B7), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPPM_CIVRMLCR                                      , RULL(0x2C0F01B7), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPPM_CIVRMLCR                                      , RULL(0x2D0F01B7), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPPM_CIVRMLCR                                      , RULL(0x2E0F01B7), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPPM_CIVRMLCR                                      , RULL(0x2F0F01B7), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPPM_CIVRMLCR                                      , RULL(0x300F01B7), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPPM_CIVRMLCR                                      , RULL(0x310F01B7), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPPM_CIVRMLCR                                      , RULL(0x320F01B7), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPPM_CIVRMLCR                                      , RULL(0x330F01B7), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPPM_CIVRMLCR                                      , RULL(0x340F01B7), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPPM_CIVRMLCR                                      , RULL(0x350F01B7), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPPM_CIVRMLCR                                      , RULL(0x360F01B7), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPPM_CIVRMLCR                                      , RULL(0x370F01B7), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_CPPM_CIVRMLCR                                        , RULL(0x200F01B7), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01B7,
+REG64( EX_0_CPPM_CIVRMLCR                                      , RULL(0x200F01B7), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01B7,
+REG64( EX_1_CPPM_CIVRMLCR                                      , RULL(0x230F01B7), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F01B7,
+REG64( EX_2_CPPM_CIVRMLCR                                      , RULL(0x240F01B7), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F01B7,
+REG64( EX_3_CPPM_CIVRMLCR                                      , RULL(0x260F01B7), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F01B7,
+REG64( EX_4_CPPM_CIVRMLCR                                      , RULL(0x280F01B7), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F01B7,
+REG64( EX_5_CPPM_CIVRMLCR                                      , RULL(0x2A0F01B7), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F01B7,
+REG64( EX_6_CPPM_CIVRMLCR                                      , RULL(0x2C0F01B7), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F01B7,
+REG64( EX_7_CPPM_CIVRMLCR                                      , RULL(0x2E0F01B7), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F01B7,
+REG64( EX_8_CPPM_CIVRMLCR                                      , RULL(0x300F01B7), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F01B7,
+REG64( EX_9_CPPM_CIVRMLCR                                      , RULL(0x320F01B7), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F01B7,
+REG64( EX_10_CPPM_CIVRMLCR                                     , RULL(0x340F01B7), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F01B7,
+REG64( EX_11_CPPM_CIVRMLCR                                     , RULL(0x360F01B7), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F01B7,
+
+REG64( C_CPPM_CMEDATA                                          , RULL(0x200F01A8), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_CPPM_CMEDATA_CLEAR                                    , RULL(0x200F01A9), SH_UNT_C        ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_CPPM_CMEDATA_OR                                       , RULL(0x200F01AA), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_CPPM_CMEDATA                                        , RULL(0x200F01A8), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_CPPM_CMEDATA_CLEAR                                  , RULL(0x200F01A9), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_0_CPPM_CMEDATA_OR                                     , RULL(0x200F01AA), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_CPPM_CMEDATA                                        , RULL(0x210F01A8), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPPM_CMEDATA_CLEAR                                  , RULL(0x210F01A9), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_1_CPPM_CMEDATA_OR                                     , RULL(0x210F01AA), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_CPPM_CMEDATA                                        , RULL(0x220F01A8), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPPM_CMEDATA_CLEAR                                  , RULL(0x220F01A9), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_2_CPPM_CMEDATA_OR                                     , RULL(0x220F01AA), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_CPPM_CMEDATA                                        , RULL(0x230F01A8), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPPM_CMEDATA_CLEAR                                  , RULL(0x230F01A9), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_3_CPPM_CMEDATA_OR                                     , RULL(0x230F01AA), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_CPPM_CMEDATA                                        , RULL(0x240F01A8), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPPM_CMEDATA_CLEAR                                  , RULL(0x240F01A9), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_4_CPPM_CMEDATA_OR                                     , RULL(0x240F01AA), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_CPPM_CMEDATA                                        , RULL(0x250F01A8), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPPM_CMEDATA_CLEAR                                  , RULL(0x250F01A9), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_5_CPPM_CMEDATA_OR                                     , RULL(0x250F01AA), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_CPPM_CMEDATA                                        , RULL(0x260F01A8), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPPM_CMEDATA_CLEAR                                  , RULL(0x260F01A9), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_6_CPPM_CMEDATA_OR                                     , RULL(0x260F01AA), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_CPPM_CMEDATA                                        , RULL(0x270F01A8), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPPM_CMEDATA_CLEAR                                  , RULL(0x270F01A9), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_7_CPPM_CMEDATA_OR                                     , RULL(0x270F01AA), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_CPPM_CMEDATA                                        , RULL(0x280F01A8), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPPM_CMEDATA_CLEAR                                  , RULL(0x280F01A9), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_8_CPPM_CMEDATA_OR                                     , RULL(0x280F01AA), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_CPPM_CMEDATA                                        , RULL(0x290F01A8), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPPM_CMEDATA_CLEAR                                  , RULL(0x290F01A9), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_9_CPPM_CMEDATA_OR                                     , RULL(0x290F01AA), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_CPPM_CMEDATA                                       , RULL(0x2A0F01A8), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_CPPM_CMEDATA_CLEAR                                 , RULL(0x2A0F01A9), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_10_CPPM_CMEDATA_OR                                    , RULL(0x2A0F01AA), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_CPPM_CMEDATA                                       , RULL(0x2B0F01A8), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPPM_CMEDATA_CLEAR                                 , RULL(0x2B0F01A9), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_11_CPPM_CMEDATA_OR                                    , RULL(0x2B0F01AA), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_CPPM_CMEDATA                                       , RULL(0x2C0F01A8), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPPM_CMEDATA_CLEAR                                 , RULL(0x2C0F01A9), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_12_CPPM_CMEDATA_OR                                    , RULL(0x2C0F01AA), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_CPPM_CMEDATA                                       , RULL(0x2D0F01A8), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPPM_CMEDATA_CLEAR                                 , RULL(0x2D0F01A9), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_13_CPPM_CMEDATA_OR                                    , RULL(0x2D0F01AA), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_CPPM_CMEDATA                                       , RULL(0x2E0F01A8), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPPM_CMEDATA_CLEAR                                 , RULL(0x2E0F01A9), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_14_CPPM_CMEDATA_OR                                    , RULL(0x2E0F01AA), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_CPPM_CMEDATA                                       , RULL(0x2F0F01A8), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPPM_CMEDATA_CLEAR                                 , RULL(0x2F0F01A9), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_15_CPPM_CMEDATA_OR                                    , RULL(0x2F0F01AA), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_CPPM_CMEDATA                                       , RULL(0x300F01A8), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPPM_CMEDATA_CLEAR                                 , RULL(0x300F01A9), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_16_CPPM_CMEDATA_OR                                    , RULL(0x300F01AA), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_CPPM_CMEDATA                                       , RULL(0x310F01A8), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPPM_CMEDATA_CLEAR                                 , RULL(0x310F01A9), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_17_CPPM_CMEDATA_OR                                    , RULL(0x310F01AA), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_CPPM_CMEDATA                                       , RULL(0x320F01A8), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPPM_CMEDATA_CLEAR                                 , RULL(0x320F01A9), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_18_CPPM_CMEDATA_OR                                    , RULL(0x320F01AA), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_CPPM_CMEDATA                                       , RULL(0x330F01A8), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPPM_CMEDATA_CLEAR                                 , RULL(0x330F01A9), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_19_CPPM_CMEDATA_OR                                    , RULL(0x330F01AA), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_CPPM_CMEDATA                                       , RULL(0x340F01A8), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPPM_CMEDATA_CLEAR                                 , RULL(0x340F01A9), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_20_CPPM_CMEDATA_OR                                    , RULL(0x340F01AA), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_CPPM_CMEDATA                                       , RULL(0x350F01A8), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPPM_CMEDATA_CLEAR                                 , RULL(0x350F01A9), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_21_CPPM_CMEDATA_OR                                    , RULL(0x350F01AA), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_CPPM_CMEDATA                                       , RULL(0x360F01A8), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPPM_CMEDATA_CLEAR                                 , RULL(0x360F01A9), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_22_CPPM_CMEDATA_OR                                    , RULL(0x360F01AA), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_CPPM_CMEDATA                                       , RULL(0x370F01A8), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPPM_CMEDATA_CLEAR                                 , RULL(0x370F01A9), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_23_CPPM_CMEDATA_OR                                    , RULL(0x370F01AA), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EX_CPPM_CMEDATA                                         , RULL(0x200F01A8), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01A8,
+REG64( EX_CPPM_CMEDATA_CLEAR                                   , RULL(0x200F01A9), SH_UNT_EX       ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F01A9,
+REG64( EX_CPPM_CMEDATA_OR                                      , RULL(0x200F01AA), SH_UNT_EX       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F01AA,
+REG64( EX_0_CPPM_CMEDATA                                       , RULL(0x200F01A8), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01A8,
+REG64( EX_0_CPPM_CMEDATA_CLEAR                                 , RULL(0x200F01A9), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F01A9,
+REG64( EX_0_CPPM_CMEDATA_OR                                    , RULL(0x200F01AA), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F01AA,
+REG64( EX_1_CPPM_CMEDATA                                       , RULL(0x230F01A8), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F01A8,
+REG64( EX_1_CPPM_CMEDATA_CLEAR                                 , RULL(0x230F01A9), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 220F01A9,
+REG64( EX_1_CPPM_CMEDATA_OR                                    , RULL(0x230F01AA), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 220F01AA,
+REG64( EX_2_CPPM_CMEDATA                                       , RULL(0x240F01A8), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F01A8,
+REG64( EX_2_CPPM_CMEDATA_CLEAR                                 , RULL(0x240F01A9), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 250F01A9,
+REG64( EX_2_CPPM_CMEDATA_OR                                    , RULL(0x240F01AA), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 250F01AA,
+REG64( EX_3_CPPM_CMEDATA                                       , RULL(0x260F01A8), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F01A8,
+REG64( EX_3_CPPM_CMEDATA_CLEAR                                 , RULL(0x260F01A9), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 270F01A9,
+REG64( EX_3_CPPM_CMEDATA_OR                                    , RULL(0x260F01AA), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 270F01AA,
+REG64( EX_4_CPPM_CMEDATA                                       , RULL(0x280F01A8), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F01A8,
+REG64( EX_4_CPPM_CMEDATA_CLEAR                                 , RULL(0x280F01A9), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 290F01A9,
+REG64( EX_4_CPPM_CMEDATA_OR                                    , RULL(0x280F01AA), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 290F01AA,
+REG64( EX_5_CPPM_CMEDATA                                       , RULL(0x2A0F01A8), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F01A8,
+REG64( EX_5_CPPM_CMEDATA_CLEAR                                 , RULL(0x2A0F01A9), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2B0F01A9,
+REG64( EX_5_CPPM_CMEDATA_OR                                    , RULL(0x2A0F01AA), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2B0F01AA,
+REG64( EX_6_CPPM_CMEDATA                                       , RULL(0x2C0F01A8), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F01A8,
+REG64( EX_6_CPPM_CMEDATA_CLEAR                                 , RULL(0x2C0F01A9), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2D0F01A9,
+REG64( EX_6_CPPM_CMEDATA_OR                                    , RULL(0x2C0F01AA), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2D0F01AA,
+REG64( EX_7_CPPM_CMEDATA                                       , RULL(0x2E0F01A8), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F01A8,
+REG64( EX_7_CPPM_CMEDATA_CLEAR                                 , RULL(0x2E0F01A9), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2F0F01A9,
+REG64( EX_7_CPPM_CMEDATA_OR                                    , RULL(0x2E0F01AA), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2F0F01AA,
+REG64( EX_8_CPPM_CMEDATA                                       , RULL(0x300F01A8), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F01A8,
+REG64( EX_8_CPPM_CMEDATA_CLEAR                                 , RULL(0x300F01A9), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 310F01A9,
+REG64( EX_8_CPPM_CMEDATA_OR                                    , RULL(0x300F01AA), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 310F01AA,
+REG64( EX_9_CPPM_CMEDATA                                       , RULL(0x320F01A8), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F01A8,
+REG64( EX_9_CPPM_CMEDATA_CLEAR                                 , RULL(0x320F01A9), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 330F01A9,
+REG64( EX_9_CPPM_CMEDATA_OR                                    , RULL(0x320F01AA), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 330F01AA,
+REG64( EX_10_CPPM_CMEDATA                                      , RULL(0x340F01A8), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F01A8,
+REG64( EX_10_CPPM_CMEDATA_CLEAR                                , RULL(0x340F01A9), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 350F01A9,
+REG64( EX_10_CPPM_CMEDATA_OR                                   , RULL(0x340F01AA), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 350F01AA,
+REG64( EX_11_CPPM_CMEDATA                                      , RULL(0x360F01A8), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F01A8,
+REG64( EX_11_CPPM_CMEDATA_CLEAR                                , RULL(0x360F01A9), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 370F01A9,
+REG64( EX_11_CPPM_CMEDATA_OR                                   , RULL(0x360F01AA), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 370F01AA,
+
+REG64( C_CPPM_CMEDB0                                           , RULL(0x200F0190), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_CPPM_CMEDB0_CLEAR                                     , RULL(0x200F0191), SH_UNT_C        ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_CPPM_CMEDB0_OR                                        , RULL(0x200F0192), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_CPPM_CMEDB0                                         , RULL(0x200F0190), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_CPPM_CMEDB0_CLEAR                                   , RULL(0x200F0191), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_0_CPPM_CMEDB0_OR                                      , RULL(0x200F0192), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_CPPM_CMEDB0                                         , RULL(0x210F0190), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPPM_CMEDB0_CLEAR                                   , RULL(0x210F0191), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_1_CPPM_CMEDB0_OR                                      , RULL(0x210F0192), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_CPPM_CMEDB0                                         , RULL(0x220F0190), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPPM_CMEDB0_CLEAR                                   , RULL(0x220F0191), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_2_CPPM_CMEDB0_OR                                      , RULL(0x220F0192), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_CPPM_CMEDB0                                         , RULL(0x230F0190), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPPM_CMEDB0_CLEAR                                   , RULL(0x230F0191), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_3_CPPM_CMEDB0_OR                                      , RULL(0x230F0192), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_CPPM_CMEDB0                                         , RULL(0x240F0190), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPPM_CMEDB0_CLEAR                                   , RULL(0x240F0191), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_4_CPPM_CMEDB0_OR                                      , RULL(0x240F0192), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_CPPM_CMEDB0                                         , RULL(0x250F0190), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPPM_CMEDB0_CLEAR                                   , RULL(0x250F0191), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_5_CPPM_CMEDB0_OR                                      , RULL(0x250F0192), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_CPPM_CMEDB0                                         , RULL(0x260F0190), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPPM_CMEDB0_CLEAR                                   , RULL(0x260F0191), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_6_CPPM_CMEDB0_OR                                      , RULL(0x260F0192), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_CPPM_CMEDB0                                         , RULL(0x270F0190), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPPM_CMEDB0_CLEAR                                   , RULL(0x270F0191), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_7_CPPM_CMEDB0_OR                                      , RULL(0x270F0192), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_CPPM_CMEDB0                                         , RULL(0x280F0190), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPPM_CMEDB0_CLEAR                                   , RULL(0x280F0191), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_8_CPPM_CMEDB0_OR                                      , RULL(0x280F0192), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_CPPM_CMEDB0                                         , RULL(0x290F0190), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPPM_CMEDB0_CLEAR                                   , RULL(0x290F0191), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_9_CPPM_CMEDB0_OR                                      , RULL(0x290F0192), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_CPPM_CMEDB0                                        , RULL(0x2A0F0190), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_CPPM_CMEDB0_CLEAR                                  , RULL(0x2A0F0191), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_10_CPPM_CMEDB0_OR                                     , RULL(0x2A0F0192), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_CPPM_CMEDB0                                        , RULL(0x2B0F0190), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPPM_CMEDB0_CLEAR                                  , RULL(0x2B0F0191), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_11_CPPM_CMEDB0_OR                                     , RULL(0x2B0F0192), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_CPPM_CMEDB0                                        , RULL(0x2C0F0190), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPPM_CMEDB0_CLEAR                                  , RULL(0x2C0F0191), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_12_CPPM_CMEDB0_OR                                     , RULL(0x2C0F0192), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_CPPM_CMEDB0                                        , RULL(0x2D0F0190), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPPM_CMEDB0_CLEAR                                  , RULL(0x2D0F0191), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_13_CPPM_CMEDB0_OR                                     , RULL(0x2D0F0192), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_CPPM_CMEDB0                                        , RULL(0x2E0F0190), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPPM_CMEDB0_CLEAR                                  , RULL(0x2E0F0191), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_14_CPPM_CMEDB0_OR                                     , RULL(0x2E0F0192), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_CPPM_CMEDB0                                        , RULL(0x2F0F0190), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPPM_CMEDB0_CLEAR                                  , RULL(0x2F0F0191), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_15_CPPM_CMEDB0_OR                                     , RULL(0x2F0F0192), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_CPPM_CMEDB0                                        , RULL(0x300F0190), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPPM_CMEDB0_CLEAR                                  , RULL(0x300F0191), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_16_CPPM_CMEDB0_OR                                     , RULL(0x300F0192), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_CPPM_CMEDB0                                        , RULL(0x310F0190), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPPM_CMEDB0_CLEAR                                  , RULL(0x310F0191), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_17_CPPM_CMEDB0_OR                                     , RULL(0x310F0192), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_CPPM_CMEDB0                                        , RULL(0x320F0190), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPPM_CMEDB0_CLEAR                                  , RULL(0x320F0191), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_18_CPPM_CMEDB0_OR                                     , RULL(0x320F0192), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_CPPM_CMEDB0                                        , RULL(0x330F0190), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPPM_CMEDB0_CLEAR                                  , RULL(0x330F0191), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_19_CPPM_CMEDB0_OR                                     , RULL(0x330F0192), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_CPPM_CMEDB0                                        , RULL(0x340F0190), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPPM_CMEDB0_CLEAR                                  , RULL(0x340F0191), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_20_CPPM_CMEDB0_OR                                     , RULL(0x340F0192), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_CPPM_CMEDB0                                        , RULL(0x350F0190), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPPM_CMEDB0_CLEAR                                  , RULL(0x350F0191), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_21_CPPM_CMEDB0_OR                                     , RULL(0x350F0192), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_CPPM_CMEDB0                                        , RULL(0x360F0190), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPPM_CMEDB0_CLEAR                                  , RULL(0x360F0191), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_22_CPPM_CMEDB0_OR                                     , RULL(0x360F0192), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_CPPM_CMEDB0                                        , RULL(0x370F0190), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPPM_CMEDB0_CLEAR                                  , RULL(0x370F0191), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_23_CPPM_CMEDB0_OR                                     , RULL(0x370F0192), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EX_CPPM_CMEDB0                                          , RULL(0x200F0190), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0190,
+REG64( EX_CPPM_CMEDB0_CLEAR                                    , RULL(0x200F0191), SH_UNT_EX       ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0191,
+REG64( EX_CPPM_CMEDB0_OR                                       , RULL(0x200F0192), SH_UNT_EX       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F0192,
+REG64( EX_0_CPPM_CMEDB0                                        , RULL(0x200F0190), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0190,
+REG64( EX_0_CPPM_CMEDB0_CLEAR                                  , RULL(0x200F0191), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0191,
+REG64( EX_0_CPPM_CMEDB0_OR                                     , RULL(0x200F0192), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F0192,
+REG64( EX_1_CPPM_CMEDB0                                        , RULL(0x230F0190), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0190,
+REG64( EX_1_CPPM_CMEDB0_CLEAR                                  , RULL(0x230F0191), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 220F0191,
+REG64( EX_1_CPPM_CMEDB0_OR                                     , RULL(0x230F0192), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 220F0192,
+REG64( EX_2_CPPM_CMEDB0                                        , RULL(0x240F0190), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0190,
+REG64( EX_2_CPPM_CMEDB0_CLEAR                                  , RULL(0x240F0191), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 250F0191,
+REG64( EX_2_CPPM_CMEDB0_OR                                     , RULL(0x240F0192), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 250F0192,
+REG64( EX_3_CPPM_CMEDB0                                        , RULL(0x260F0190), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0190,
+REG64( EX_3_CPPM_CMEDB0_CLEAR                                  , RULL(0x260F0191), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 270F0191,
+REG64( EX_3_CPPM_CMEDB0_OR                                     , RULL(0x260F0192), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 270F0192,
+REG64( EX_4_CPPM_CMEDB0                                        , RULL(0x280F0190), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0190,
+REG64( EX_4_CPPM_CMEDB0_CLEAR                                  , RULL(0x280F0191), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 290F0191,
+REG64( EX_4_CPPM_CMEDB0_OR                                     , RULL(0x280F0192), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 290F0192,
+REG64( EX_5_CPPM_CMEDB0                                        , RULL(0x2A0F0190), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0190,
+REG64( EX_5_CPPM_CMEDB0_CLEAR                                  , RULL(0x2A0F0191), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2B0F0191,
+REG64( EX_5_CPPM_CMEDB0_OR                                     , RULL(0x2A0F0192), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2B0F0192,
+REG64( EX_6_CPPM_CMEDB0                                        , RULL(0x2C0F0190), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0190,
+REG64( EX_6_CPPM_CMEDB0_CLEAR                                  , RULL(0x2C0F0191), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2D0F0191,
+REG64( EX_6_CPPM_CMEDB0_OR                                     , RULL(0x2C0F0192), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2D0F0192,
+REG64( EX_7_CPPM_CMEDB0                                        , RULL(0x2E0F0190), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0190,
+REG64( EX_7_CPPM_CMEDB0_CLEAR                                  , RULL(0x2E0F0191), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2F0F0191,
+REG64( EX_7_CPPM_CMEDB0_OR                                     , RULL(0x2E0F0192), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2F0F0192,
+REG64( EX_8_CPPM_CMEDB0                                        , RULL(0x300F0190), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0190,
+REG64( EX_8_CPPM_CMEDB0_CLEAR                                  , RULL(0x300F0191), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 310F0191,
+REG64( EX_8_CPPM_CMEDB0_OR                                     , RULL(0x300F0192), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 310F0192,
+REG64( EX_9_CPPM_CMEDB0                                        , RULL(0x320F0190), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0190,
+REG64( EX_9_CPPM_CMEDB0_CLEAR                                  , RULL(0x320F0191), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 330F0191,
+REG64( EX_9_CPPM_CMEDB0_OR                                     , RULL(0x320F0192), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 330F0192,
+REG64( EX_10_CPPM_CMEDB0                                       , RULL(0x340F0190), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0190,
+REG64( EX_10_CPPM_CMEDB0_CLEAR                                 , RULL(0x340F0191), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 350F0191,
+REG64( EX_10_CPPM_CMEDB0_OR                                    , RULL(0x340F0192), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 350F0192,
+REG64( EX_11_CPPM_CMEDB0                                       , RULL(0x360F0190), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0190,
+REG64( EX_11_CPPM_CMEDB0_CLEAR                                 , RULL(0x360F0191), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 370F0191,
+REG64( EX_11_CPPM_CMEDB0_OR                                    , RULL(0x360F0192), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 370F0192,
+
+REG64( C_CPPM_CMEDB1                                           , RULL(0x200F0194), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_CPPM_CMEDB1_CLEAR                                     , RULL(0x200F0195), SH_UNT_C        ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_CPPM_CMEDB1_OR                                        , RULL(0x200F0196), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_CPPM_CMEDB1                                         , RULL(0x200F0194), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_CPPM_CMEDB1_CLEAR                                   , RULL(0x200F0195), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_0_CPPM_CMEDB1_OR                                      , RULL(0x200F0196), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_CPPM_CMEDB1                                         , RULL(0x210F0194), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPPM_CMEDB1_CLEAR                                   , RULL(0x210F0195), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_1_CPPM_CMEDB1_OR                                      , RULL(0x210F0196), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_CPPM_CMEDB1                                         , RULL(0x220F0194), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPPM_CMEDB1_CLEAR                                   , RULL(0x220F0195), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_2_CPPM_CMEDB1_OR                                      , RULL(0x220F0196), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_CPPM_CMEDB1                                         , RULL(0x230F0194), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPPM_CMEDB1_CLEAR                                   , RULL(0x230F0195), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_3_CPPM_CMEDB1_OR                                      , RULL(0x230F0196), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_CPPM_CMEDB1                                         , RULL(0x240F0194), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPPM_CMEDB1_CLEAR                                   , RULL(0x240F0195), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_4_CPPM_CMEDB1_OR                                      , RULL(0x240F0196), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_CPPM_CMEDB1                                         , RULL(0x250F0194), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPPM_CMEDB1_CLEAR                                   , RULL(0x250F0195), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_5_CPPM_CMEDB1_OR                                      , RULL(0x250F0196), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_CPPM_CMEDB1                                         , RULL(0x260F0194), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPPM_CMEDB1_CLEAR                                   , RULL(0x260F0195), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_6_CPPM_CMEDB1_OR                                      , RULL(0x260F0196), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_CPPM_CMEDB1                                         , RULL(0x270F0194), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPPM_CMEDB1_CLEAR                                   , RULL(0x270F0195), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_7_CPPM_CMEDB1_OR                                      , RULL(0x270F0196), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_CPPM_CMEDB1                                         , RULL(0x280F0194), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPPM_CMEDB1_CLEAR                                   , RULL(0x280F0195), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_8_CPPM_CMEDB1_OR                                      , RULL(0x280F0196), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_CPPM_CMEDB1                                         , RULL(0x290F0194), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPPM_CMEDB1_CLEAR                                   , RULL(0x290F0195), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_9_CPPM_CMEDB1_OR                                      , RULL(0x290F0196), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_CPPM_CMEDB1                                        , RULL(0x2A0F0194), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_CPPM_CMEDB1_CLEAR                                  , RULL(0x2A0F0195), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_10_CPPM_CMEDB1_OR                                     , RULL(0x2A0F0196), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_CPPM_CMEDB1                                        , RULL(0x2B0F0194), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPPM_CMEDB1_CLEAR                                  , RULL(0x2B0F0195), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_11_CPPM_CMEDB1_OR                                     , RULL(0x2B0F0196), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_CPPM_CMEDB1                                        , RULL(0x2C0F0194), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPPM_CMEDB1_CLEAR                                  , RULL(0x2C0F0195), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_12_CPPM_CMEDB1_OR                                     , RULL(0x2C0F0196), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_CPPM_CMEDB1                                        , RULL(0x2D0F0194), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPPM_CMEDB1_CLEAR                                  , RULL(0x2D0F0195), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_13_CPPM_CMEDB1_OR                                     , RULL(0x2D0F0196), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_CPPM_CMEDB1                                        , RULL(0x2E0F0194), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPPM_CMEDB1_CLEAR                                  , RULL(0x2E0F0195), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_14_CPPM_CMEDB1_OR                                     , RULL(0x2E0F0196), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_CPPM_CMEDB1                                        , RULL(0x2F0F0194), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPPM_CMEDB1_CLEAR                                  , RULL(0x2F0F0195), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_15_CPPM_CMEDB1_OR                                     , RULL(0x2F0F0196), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_CPPM_CMEDB1                                        , RULL(0x300F0194), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPPM_CMEDB1_CLEAR                                  , RULL(0x300F0195), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_16_CPPM_CMEDB1_OR                                     , RULL(0x300F0196), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_CPPM_CMEDB1                                        , RULL(0x310F0194), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPPM_CMEDB1_CLEAR                                  , RULL(0x310F0195), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_17_CPPM_CMEDB1_OR                                     , RULL(0x310F0196), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_CPPM_CMEDB1                                        , RULL(0x320F0194), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPPM_CMEDB1_CLEAR                                  , RULL(0x320F0195), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_18_CPPM_CMEDB1_OR                                     , RULL(0x320F0196), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_CPPM_CMEDB1                                        , RULL(0x330F0194), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPPM_CMEDB1_CLEAR                                  , RULL(0x330F0195), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_19_CPPM_CMEDB1_OR                                     , RULL(0x330F0196), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_CPPM_CMEDB1                                        , RULL(0x340F0194), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPPM_CMEDB1_CLEAR                                  , RULL(0x340F0195), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_20_CPPM_CMEDB1_OR                                     , RULL(0x340F0196), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_CPPM_CMEDB1                                        , RULL(0x350F0194), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPPM_CMEDB1_CLEAR                                  , RULL(0x350F0195), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_21_CPPM_CMEDB1_OR                                     , RULL(0x350F0196), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_CPPM_CMEDB1                                        , RULL(0x360F0194), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPPM_CMEDB1_CLEAR                                  , RULL(0x360F0195), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_22_CPPM_CMEDB1_OR                                     , RULL(0x360F0196), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_CPPM_CMEDB1                                        , RULL(0x370F0194), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPPM_CMEDB1_CLEAR                                  , RULL(0x370F0195), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_23_CPPM_CMEDB1_OR                                     , RULL(0x370F0196), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EX_CPPM_CMEDB1                                          , RULL(0x200F0194), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0194,
+REG64( EX_CPPM_CMEDB1_CLEAR                                    , RULL(0x200F0195), SH_UNT_EX       ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0195,
+REG64( EX_CPPM_CMEDB1_OR                                       , RULL(0x200F0196), SH_UNT_EX       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F0196,
+REG64( EX_0_CPPM_CMEDB1                                        , RULL(0x200F0194), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0194,
+REG64( EX_0_CPPM_CMEDB1_CLEAR                                  , RULL(0x200F0195), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0195,
+REG64( EX_0_CPPM_CMEDB1_OR                                     , RULL(0x200F0196), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F0196,
+REG64( EX_1_CPPM_CMEDB1                                        , RULL(0x230F0194), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0194,
+REG64( EX_1_CPPM_CMEDB1_CLEAR                                  , RULL(0x230F0195), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 220F0195,
+REG64( EX_1_CPPM_CMEDB1_OR                                     , RULL(0x230F0196), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 220F0196,
+REG64( EX_2_CPPM_CMEDB1                                        , RULL(0x240F0194), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0194,
+REG64( EX_2_CPPM_CMEDB1_CLEAR                                  , RULL(0x240F0195), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 250F0195,
+REG64( EX_2_CPPM_CMEDB1_OR                                     , RULL(0x240F0196), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 250F0196,
+REG64( EX_3_CPPM_CMEDB1                                        , RULL(0x260F0194), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0194,
+REG64( EX_3_CPPM_CMEDB1_CLEAR                                  , RULL(0x260F0195), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 270F0195,
+REG64( EX_3_CPPM_CMEDB1_OR                                     , RULL(0x260F0196), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 270F0196,
+REG64( EX_4_CPPM_CMEDB1                                        , RULL(0x280F0194), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0194,
+REG64( EX_4_CPPM_CMEDB1_CLEAR                                  , RULL(0x280F0195), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 290F0195,
+REG64( EX_4_CPPM_CMEDB1_OR                                     , RULL(0x280F0196), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 290F0196,
+REG64( EX_5_CPPM_CMEDB1                                        , RULL(0x2A0F0194), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0194,
+REG64( EX_5_CPPM_CMEDB1_CLEAR                                  , RULL(0x2A0F0195), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2B0F0195,
+REG64( EX_5_CPPM_CMEDB1_OR                                     , RULL(0x2A0F0196), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2B0F0196,
+REG64( EX_6_CPPM_CMEDB1                                        , RULL(0x2C0F0194), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0194,
+REG64( EX_6_CPPM_CMEDB1_CLEAR                                  , RULL(0x2C0F0195), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2D0F0195,
+REG64( EX_6_CPPM_CMEDB1_OR                                     , RULL(0x2C0F0196), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2D0F0196,
+REG64( EX_7_CPPM_CMEDB1                                        , RULL(0x2E0F0194), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0194,
+REG64( EX_7_CPPM_CMEDB1_CLEAR                                  , RULL(0x2E0F0195), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2F0F0195,
+REG64( EX_7_CPPM_CMEDB1_OR                                     , RULL(0x2E0F0196), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2F0F0196,
+REG64( EX_8_CPPM_CMEDB1                                        , RULL(0x300F0194), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0194,
+REG64( EX_8_CPPM_CMEDB1_CLEAR                                  , RULL(0x300F0195), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 310F0195,
+REG64( EX_8_CPPM_CMEDB1_OR                                     , RULL(0x300F0196), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 310F0196,
+REG64( EX_9_CPPM_CMEDB1                                        , RULL(0x320F0194), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0194,
+REG64( EX_9_CPPM_CMEDB1_CLEAR                                  , RULL(0x320F0195), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 330F0195,
+REG64( EX_9_CPPM_CMEDB1_OR                                     , RULL(0x320F0196), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 330F0196,
+REG64( EX_10_CPPM_CMEDB1                                       , RULL(0x340F0194), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0194,
+REG64( EX_10_CPPM_CMEDB1_CLEAR                                 , RULL(0x340F0195), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 350F0195,
+REG64( EX_10_CPPM_CMEDB1_OR                                    , RULL(0x340F0196), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 350F0196,
+REG64( EX_11_CPPM_CMEDB1                                       , RULL(0x360F0194), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0194,
+REG64( EX_11_CPPM_CMEDB1_CLEAR                                 , RULL(0x360F0195), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 370F0195,
+REG64( EX_11_CPPM_CMEDB1_OR                                    , RULL(0x360F0196), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 370F0196,
+
+REG64( C_CPPM_CMEDB2                                           , RULL(0x200F0198), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_CPPM_CMEDB2_CLEAR                                     , RULL(0x200F0199), SH_UNT_C        ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_CPPM_CMEDB2_OR                                        , RULL(0x200F019A), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_CPPM_CMEDB2                                         , RULL(0x200F0198), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_CPPM_CMEDB2_CLEAR                                   , RULL(0x200F0199), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_0_CPPM_CMEDB2_OR                                      , RULL(0x200F019A), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_CPPM_CMEDB2                                         , RULL(0x210F0198), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPPM_CMEDB2_CLEAR                                   , RULL(0x210F0199), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_1_CPPM_CMEDB2_OR                                      , RULL(0x210F019A), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_CPPM_CMEDB2                                         , RULL(0x220F0198), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPPM_CMEDB2_CLEAR                                   , RULL(0x220F0199), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_2_CPPM_CMEDB2_OR                                      , RULL(0x220F019A), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_CPPM_CMEDB2                                         , RULL(0x230F0198), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPPM_CMEDB2_CLEAR                                   , RULL(0x230F0199), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_3_CPPM_CMEDB2_OR                                      , RULL(0x230F019A), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_CPPM_CMEDB2                                         , RULL(0x240F0198), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPPM_CMEDB2_CLEAR                                   , RULL(0x240F0199), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_4_CPPM_CMEDB2_OR                                      , RULL(0x240F019A), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_CPPM_CMEDB2                                         , RULL(0x250F0198), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPPM_CMEDB2_CLEAR                                   , RULL(0x250F0199), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_5_CPPM_CMEDB2_OR                                      , RULL(0x250F019A), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_CPPM_CMEDB2                                         , RULL(0x260F0198), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPPM_CMEDB2_CLEAR                                   , RULL(0x260F0199), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_6_CPPM_CMEDB2_OR                                      , RULL(0x260F019A), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_CPPM_CMEDB2                                         , RULL(0x270F0198), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPPM_CMEDB2_CLEAR                                   , RULL(0x270F0199), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_7_CPPM_CMEDB2_OR                                      , RULL(0x270F019A), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_CPPM_CMEDB2                                         , RULL(0x280F0198), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPPM_CMEDB2_CLEAR                                   , RULL(0x280F0199), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_8_CPPM_CMEDB2_OR                                      , RULL(0x280F019A), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_CPPM_CMEDB2                                         , RULL(0x290F0198), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPPM_CMEDB2_CLEAR                                   , RULL(0x290F0199), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_9_CPPM_CMEDB2_OR                                      , RULL(0x290F019A), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_CPPM_CMEDB2                                        , RULL(0x2A0F0198), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_CPPM_CMEDB2_CLEAR                                  , RULL(0x2A0F0199), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_10_CPPM_CMEDB2_OR                                     , RULL(0x2A0F019A), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_CPPM_CMEDB2                                        , RULL(0x2B0F0198), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPPM_CMEDB2_CLEAR                                  , RULL(0x2B0F0199), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_11_CPPM_CMEDB2_OR                                     , RULL(0x2B0F019A), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_CPPM_CMEDB2                                        , RULL(0x2C0F0198), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPPM_CMEDB2_CLEAR                                  , RULL(0x2C0F0199), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_12_CPPM_CMEDB2_OR                                     , RULL(0x2C0F019A), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_CPPM_CMEDB2                                        , RULL(0x2D0F0198), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPPM_CMEDB2_CLEAR                                  , RULL(0x2D0F0199), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_13_CPPM_CMEDB2_OR                                     , RULL(0x2D0F019A), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_CPPM_CMEDB2                                        , RULL(0x2E0F0198), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPPM_CMEDB2_CLEAR                                  , RULL(0x2E0F0199), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_14_CPPM_CMEDB2_OR                                     , RULL(0x2E0F019A), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_CPPM_CMEDB2                                        , RULL(0x2F0F0198), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPPM_CMEDB2_CLEAR                                  , RULL(0x2F0F0199), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_15_CPPM_CMEDB2_OR                                     , RULL(0x2F0F019A), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_CPPM_CMEDB2                                        , RULL(0x300F0198), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPPM_CMEDB2_CLEAR                                  , RULL(0x300F0199), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_16_CPPM_CMEDB2_OR                                     , RULL(0x300F019A), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_CPPM_CMEDB2                                        , RULL(0x310F0198), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPPM_CMEDB2_CLEAR                                  , RULL(0x310F0199), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_17_CPPM_CMEDB2_OR                                     , RULL(0x310F019A), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_CPPM_CMEDB2                                        , RULL(0x320F0198), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPPM_CMEDB2_CLEAR                                  , RULL(0x320F0199), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_18_CPPM_CMEDB2_OR                                     , RULL(0x320F019A), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_CPPM_CMEDB2                                        , RULL(0x330F0198), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPPM_CMEDB2_CLEAR                                  , RULL(0x330F0199), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_19_CPPM_CMEDB2_OR                                     , RULL(0x330F019A), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_CPPM_CMEDB2                                        , RULL(0x340F0198), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPPM_CMEDB2_CLEAR                                  , RULL(0x340F0199), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_20_CPPM_CMEDB2_OR                                     , RULL(0x340F019A), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_CPPM_CMEDB2                                        , RULL(0x350F0198), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPPM_CMEDB2_CLEAR                                  , RULL(0x350F0199), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_21_CPPM_CMEDB2_OR                                     , RULL(0x350F019A), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_CPPM_CMEDB2                                        , RULL(0x360F0198), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPPM_CMEDB2_CLEAR                                  , RULL(0x360F0199), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_22_CPPM_CMEDB2_OR                                     , RULL(0x360F019A), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_CPPM_CMEDB2                                        , RULL(0x370F0198), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPPM_CMEDB2_CLEAR                                  , RULL(0x370F0199), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_23_CPPM_CMEDB2_OR                                     , RULL(0x370F019A), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EX_CPPM_CMEDB2                                          , RULL(0x200F0198), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0198,
+REG64( EX_CPPM_CMEDB2_CLEAR                                    , RULL(0x200F0199), SH_UNT_EX       ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0199,
+REG64( EX_CPPM_CMEDB2_OR                                       , RULL(0x200F019A), SH_UNT_EX       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F019A,
+REG64( EX_0_CPPM_CMEDB2                                        , RULL(0x200F0198), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0198,
+REG64( EX_0_CPPM_CMEDB2_CLEAR                                  , RULL(0x200F0199), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0199,
+REG64( EX_0_CPPM_CMEDB2_OR                                     , RULL(0x200F019A), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F019A,
+REG64( EX_1_CPPM_CMEDB2                                        , RULL(0x230F0198), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0198,
+REG64( EX_1_CPPM_CMEDB2_CLEAR                                  , RULL(0x230F0199), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 220F0199,
+REG64( EX_1_CPPM_CMEDB2_OR                                     , RULL(0x230F019A), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 220F019A,
+REG64( EX_2_CPPM_CMEDB2                                        , RULL(0x240F0198), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0198,
+REG64( EX_2_CPPM_CMEDB2_CLEAR                                  , RULL(0x240F0199), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 250F0199,
+REG64( EX_2_CPPM_CMEDB2_OR                                     , RULL(0x240F019A), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 250F019A,
+REG64( EX_3_CPPM_CMEDB2                                        , RULL(0x260F0198), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0198,
+REG64( EX_3_CPPM_CMEDB2_CLEAR                                  , RULL(0x260F0199), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 270F0199,
+REG64( EX_3_CPPM_CMEDB2_OR                                     , RULL(0x260F019A), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 270F019A,
+REG64( EX_4_CPPM_CMEDB2                                        , RULL(0x280F0198), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0198,
+REG64( EX_4_CPPM_CMEDB2_CLEAR                                  , RULL(0x280F0199), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 290F0199,
+REG64( EX_4_CPPM_CMEDB2_OR                                     , RULL(0x280F019A), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 290F019A,
+REG64( EX_5_CPPM_CMEDB2                                        , RULL(0x2A0F0198), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0198,
+REG64( EX_5_CPPM_CMEDB2_CLEAR                                  , RULL(0x2A0F0199), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2B0F0199,
+REG64( EX_5_CPPM_CMEDB2_OR                                     , RULL(0x2A0F019A), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2B0F019A,
+REG64( EX_6_CPPM_CMEDB2                                        , RULL(0x2C0F0198), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0198,
+REG64( EX_6_CPPM_CMEDB2_CLEAR                                  , RULL(0x2C0F0199), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2D0F0199,
+REG64( EX_6_CPPM_CMEDB2_OR                                     , RULL(0x2C0F019A), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2D0F019A,
+REG64( EX_7_CPPM_CMEDB2                                        , RULL(0x2E0F0198), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0198,
+REG64( EX_7_CPPM_CMEDB2_CLEAR                                  , RULL(0x2E0F0199), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2F0F0199,
+REG64( EX_7_CPPM_CMEDB2_OR                                     , RULL(0x2E0F019A), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2F0F019A,
+REG64( EX_8_CPPM_CMEDB2                                        , RULL(0x300F0198), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0198,
+REG64( EX_8_CPPM_CMEDB2_CLEAR                                  , RULL(0x300F0199), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 310F0199,
+REG64( EX_8_CPPM_CMEDB2_OR                                     , RULL(0x300F019A), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 310F019A,
+REG64( EX_9_CPPM_CMEDB2                                        , RULL(0x320F0198), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0198,
+REG64( EX_9_CPPM_CMEDB2_CLEAR                                  , RULL(0x320F0199), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 330F0199,
+REG64( EX_9_CPPM_CMEDB2_OR                                     , RULL(0x320F019A), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 330F019A,
+REG64( EX_10_CPPM_CMEDB2                                       , RULL(0x340F0198), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0198,
+REG64( EX_10_CPPM_CMEDB2_CLEAR                                 , RULL(0x340F0199), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 350F0199,
+REG64( EX_10_CPPM_CMEDB2_OR                                    , RULL(0x340F019A), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 350F019A,
+REG64( EX_11_CPPM_CMEDB2                                       , RULL(0x360F0198), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0198,
+REG64( EX_11_CPPM_CMEDB2_CLEAR                                 , RULL(0x360F0199), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 370F0199,
+REG64( EX_11_CPPM_CMEDB2_OR                                    , RULL(0x360F019A), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 370F019A,
+
+REG64( C_CPPM_CMEDB3                                           , RULL(0x200F019C), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_CPPM_CMEDB3_CLEAR                                     , RULL(0x200F019D), SH_UNT_C        ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_CPPM_CMEDB3_OR                                        , RULL(0x200F019E), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_CPPM_CMEDB3                                         , RULL(0x200F019C), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_CPPM_CMEDB3_CLEAR                                   , RULL(0x200F019D), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_0_CPPM_CMEDB3_OR                                      , RULL(0x200F019E), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_CPPM_CMEDB3                                         , RULL(0x210F019C), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPPM_CMEDB3_CLEAR                                   , RULL(0x210F019D), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_1_CPPM_CMEDB3_OR                                      , RULL(0x210F019E), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_CPPM_CMEDB3                                         , RULL(0x220F019C), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPPM_CMEDB3_CLEAR                                   , RULL(0x220F019D), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_2_CPPM_CMEDB3_OR                                      , RULL(0x220F019E), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_CPPM_CMEDB3                                         , RULL(0x230F019C), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPPM_CMEDB3_CLEAR                                   , RULL(0x230F019D), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_3_CPPM_CMEDB3_OR                                      , RULL(0x230F019E), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_CPPM_CMEDB3                                         , RULL(0x240F019C), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPPM_CMEDB3_CLEAR                                   , RULL(0x240F019D), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_4_CPPM_CMEDB3_OR                                      , RULL(0x240F019E), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_CPPM_CMEDB3                                         , RULL(0x250F019C), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPPM_CMEDB3_CLEAR                                   , RULL(0x250F019D), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_5_CPPM_CMEDB3_OR                                      , RULL(0x250F019E), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_CPPM_CMEDB3                                         , RULL(0x260F019C), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPPM_CMEDB3_CLEAR                                   , RULL(0x260F019D), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_6_CPPM_CMEDB3_OR                                      , RULL(0x260F019E), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_CPPM_CMEDB3                                         , RULL(0x270F019C), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPPM_CMEDB3_CLEAR                                   , RULL(0x270F019D), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_7_CPPM_CMEDB3_OR                                      , RULL(0x270F019E), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_CPPM_CMEDB3                                         , RULL(0x280F019C), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPPM_CMEDB3_CLEAR                                   , RULL(0x280F019D), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_8_CPPM_CMEDB3_OR                                      , RULL(0x280F019E), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_CPPM_CMEDB3                                         , RULL(0x290F019C), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPPM_CMEDB3_CLEAR                                   , RULL(0x290F019D), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_9_CPPM_CMEDB3_OR                                      , RULL(0x290F019E), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_CPPM_CMEDB3                                        , RULL(0x2A0F019C), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_CPPM_CMEDB3_CLEAR                                  , RULL(0x2A0F019D), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_10_CPPM_CMEDB3_OR                                     , RULL(0x2A0F019E), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_CPPM_CMEDB3                                        , RULL(0x2B0F019C), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPPM_CMEDB3_CLEAR                                  , RULL(0x2B0F019D), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_11_CPPM_CMEDB3_OR                                     , RULL(0x2B0F019E), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_CPPM_CMEDB3                                        , RULL(0x2C0F019C), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPPM_CMEDB3_CLEAR                                  , RULL(0x2C0F019D), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_12_CPPM_CMEDB3_OR                                     , RULL(0x2C0F019E), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_CPPM_CMEDB3                                        , RULL(0x2D0F019C), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPPM_CMEDB3_CLEAR                                  , RULL(0x2D0F019D), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_13_CPPM_CMEDB3_OR                                     , RULL(0x2D0F019E), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_CPPM_CMEDB3                                        , RULL(0x2E0F019C), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPPM_CMEDB3_CLEAR                                  , RULL(0x2E0F019D), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_14_CPPM_CMEDB3_OR                                     , RULL(0x2E0F019E), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_CPPM_CMEDB3                                        , RULL(0x2F0F019C), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPPM_CMEDB3_CLEAR                                  , RULL(0x2F0F019D), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_15_CPPM_CMEDB3_OR                                     , RULL(0x2F0F019E), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_CPPM_CMEDB3                                        , RULL(0x300F019C), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPPM_CMEDB3_CLEAR                                  , RULL(0x300F019D), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_16_CPPM_CMEDB3_OR                                     , RULL(0x300F019E), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_CPPM_CMEDB3                                        , RULL(0x310F019C), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPPM_CMEDB3_CLEAR                                  , RULL(0x310F019D), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_17_CPPM_CMEDB3_OR                                     , RULL(0x310F019E), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_CPPM_CMEDB3                                        , RULL(0x320F019C), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPPM_CMEDB3_CLEAR                                  , RULL(0x320F019D), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_18_CPPM_CMEDB3_OR                                     , RULL(0x320F019E), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_CPPM_CMEDB3                                        , RULL(0x330F019C), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPPM_CMEDB3_CLEAR                                  , RULL(0x330F019D), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_19_CPPM_CMEDB3_OR                                     , RULL(0x330F019E), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_CPPM_CMEDB3                                        , RULL(0x340F019C), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPPM_CMEDB3_CLEAR                                  , RULL(0x340F019D), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_20_CPPM_CMEDB3_OR                                     , RULL(0x340F019E), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_CPPM_CMEDB3                                        , RULL(0x350F019C), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPPM_CMEDB3_CLEAR                                  , RULL(0x350F019D), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_21_CPPM_CMEDB3_OR                                     , RULL(0x350F019E), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_CPPM_CMEDB3                                        , RULL(0x360F019C), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPPM_CMEDB3_CLEAR                                  , RULL(0x360F019D), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_22_CPPM_CMEDB3_OR                                     , RULL(0x360F019E), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_CPPM_CMEDB3                                        , RULL(0x370F019C), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPPM_CMEDB3_CLEAR                                  , RULL(0x370F019D), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_23_CPPM_CMEDB3_OR                                     , RULL(0x370F019E), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EX_CPPM_CMEDB3                                          , RULL(0x200F019C), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F019C,
+REG64( EX_CPPM_CMEDB3_CLEAR                                    , RULL(0x200F019D), SH_UNT_EX       ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F019D,
+REG64( EX_CPPM_CMEDB3_OR                                       , RULL(0x200F019E), SH_UNT_EX       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F019E,
+REG64( EX_0_CPPM_CMEDB3                                        , RULL(0x200F019C), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F019C,
+REG64( EX_0_CPPM_CMEDB3_CLEAR                                  , RULL(0x200F019D), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F019D,
+REG64( EX_0_CPPM_CMEDB3_OR                                     , RULL(0x200F019E), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F019E,
+REG64( EX_1_CPPM_CMEDB3                                        , RULL(0x230F019C), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F019C,
+REG64( EX_1_CPPM_CMEDB3_CLEAR                                  , RULL(0x230F019D), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 220F019D,
+REG64( EX_1_CPPM_CMEDB3_OR                                     , RULL(0x230F019E), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 220F019E,
+REG64( EX_2_CPPM_CMEDB3                                        , RULL(0x240F019C), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F019C,
+REG64( EX_2_CPPM_CMEDB3_CLEAR                                  , RULL(0x240F019D), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 250F019D,
+REG64( EX_2_CPPM_CMEDB3_OR                                     , RULL(0x240F019E), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 250F019E,
+REG64( EX_3_CPPM_CMEDB3                                        , RULL(0x260F019C), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F019C,
+REG64( EX_3_CPPM_CMEDB3_CLEAR                                  , RULL(0x260F019D), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 270F019D,
+REG64( EX_3_CPPM_CMEDB3_OR                                     , RULL(0x260F019E), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 270F019E,
+REG64( EX_4_CPPM_CMEDB3                                        , RULL(0x280F019C), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F019C,
+REG64( EX_4_CPPM_CMEDB3_CLEAR                                  , RULL(0x280F019D), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 290F019D,
+REG64( EX_4_CPPM_CMEDB3_OR                                     , RULL(0x280F019E), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 290F019E,
+REG64( EX_5_CPPM_CMEDB3                                        , RULL(0x2A0F019C), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F019C,
+REG64( EX_5_CPPM_CMEDB3_CLEAR                                  , RULL(0x2A0F019D), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2B0F019D,
+REG64( EX_5_CPPM_CMEDB3_OR                                     , RULL(0x2A0F019E), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2B0F019E,
+REG64( EX_6_CPPM_CMEDB3                                        , RULL(0x2C0F019C), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F019C,
+REG64( EX_6_CPPM_CMEDB3_CLEAR                                  , RULL(0x2C0F019D), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2D0F019D,
+REG64( EX_6_CPPM_CMEDB3_OR                                     , RULL(0x2C0F019E), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2D0F019E,
+REG64( EX_7_CPPM_CMEDB3                                        , RULL(0x2E0F019C), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F019C,
+REG64( EX_7_CPPM_CMEDB3_CLEAR                                  , RULL(0x2E0F019D), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2F0F019D,
+REG64( EX_7_CPPM_CMEDB3_OR                                     , RULL(0x2E0F019E), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2F0F019E,
+REG64( EX_8_CPPM_CMEDB3                                        , RULL(0x300F019C), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F019C,
+REG64( EX_8_CPPM_CMEDB3_CLEAR                                  , RULL(0x300F019D), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 310F019D,
+REG64( EX_8_CPPM_CMEDB3_OR                                     , RULL(0x300F019E), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 310F019E,
+REG64( EX_9_CPPM_CMEDB3                                        , RULL(0x320F019C), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F019C,
+REG64( EX_9_CPPM_CMEDB3_CLEAR                                  , RULL(0x320F019D), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 330F019D,
+REG64( EX_9_CPPM_CMEDB3_OR                                     , RULL(0x320F019E), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 330F019E,
+REG64( EX_10_CPPM_CMEDB3                                       , RULL(0x340F019C), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F019C,
+REG64( EX_10_CPPM_CMEDB3_CLEAR                                 , RULL(0x340F019D), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 350F019D,
+REG64( EX_10_CPPM_CMEDB3_OR                                    , RULL(0x340F019E), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 350F019E,
+REG64( EX_11_CPPM_CMEDB3                                       , RULL(0x360F019C), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F019C,
+REG64( EX_11_CPPM_CMEDB3_CLEAR                                 , RULL(0x360F019D), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 370F019D,
+REG64( EX_11_CPPM_CMEDB3_OR                                    , RULL(0x360F019E), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 370F019E,
+
+REG64( C_CPPM_CMEMSG                                           , RULL(0x200F01AB), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_CPPM_CMEMSG                                         , RULL(0x200F01AB), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPPM_CMEMSG                                         , RULL(0x210F01AB), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPPM_CMEMSG                                         , RULL(0x220F01AB), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPPM_CMEMSG                                         , RULL(0x230F01AB), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPPM_CMEMSG                                         , RULL(0x240F01AB), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPPM_CMEMSG                                         , RULL(0x250F01AB), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPPM_CMEMSG                                         , RULL(0x260F01AB), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPPM_CMEMSG                                         , RULL(0x270F01AB), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPPM_CMEMSG                                         , RULL(0x280F01AB), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPPM_CMEMSG                                         , RULL(0x290F01AB), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_CPPM_CMEMSG                                        , RULL(0x2A0F01AB), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPPM_CMEMSG                                        , RULL(0x2B0F01AB), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPPM_CMEMSG                                        , RULL(0x2C0F01AB), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPPM_CMEMSG                                        , RULL(0x2D0F01AB), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPPM_CMEMSG                                        , RULL(0x2E0F01AB), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPPM_CMEMSG                                        , RULL(0x2F0F01AB), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPPM_CMEMSG                                        , RULL(0x300F01AB), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPPM_CMEMSG                                        , RULL(0x310F01AB), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPPM_CMEMSG                                        , RULL(0x320F01AB), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPPM_CMEMSG                                        , RULL(0x330F01AB), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPPM_CMEMSG                                        , RULL(0x340F01AB), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPPM_CMEMSG                                        , RULL(0x350F01AB), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPPM_CMEMSG                                        , RULL(0x360F01AB), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPPM_CMEMSG                                        , RULL(0x370F01AB), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_CPPM_CMEMSG                                          , RULL(0x200F01AB), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01AB,
+REG64( EX_0_CPPM_CMEMSG                                        , RULL(0x200F01AB), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01AB,
+REG64( EX_1_CPPM_CMEMSG                                        , RULL(0x230F01AB), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F01AB,
+REG64( EX_2_CPPM_CMEMSG                                        , RULL(0x240F01AB), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F01AB,
+REG64( EX_3_CPPM_CMEMSG                                        , RULL(0x260F01AB), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F01AB,
+REG64( EX_4_CPPM_CMEMSG                                        , RULL(0x280F01AB), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F01AB,
+REG64( EX_5_CPPM_CMEMSG                                        , RULL(0x2A0F01AB), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F01AB,
+REG64( EX_6_CPPM_CMEMSG                                        , RULL(0x2C0F01AB), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F01AB,
+REG64( EX_7_CPPM_CMEMSG                                        , RULL(0x2E0F01AB), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F01AB,
+REG64( EX_8_CPPM_CMEMSG                                        , RULL(0x300F01AB), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F01AB,
+REG64( EX_9_CPPM_CMEMSG                                        , RULL(0x320F01AB), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F01AB,
+REG64( EX_10_CPPM_CMEMSG                                       , RULL(0x340F01AB), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F01AB,
+REG64( EX_11_CPPM_CMEMSG                                       , RULL(0x360F01AB), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F01AB,
+
+REG64( C_CPPM_CPMMR                                            , RULL(0x200F0106), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_CPPM_CPMMR_CLEAR                                      , RULL(0x200F0107), SH_UNT_C        ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_CPPM_CPMMR_OR                                         , RULL(0x200F0108), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_CPPM_CPMMR                                          , RULL(0x200F0106), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_CPPM_CPMMR_CLEAR                                    , RULL(0x200F0107), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_0_CPPM_CPMMR_OR                                       , RULL(0x200F0108), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_CPPM_CPMMR                                          , RULL(0x210F0106), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPPM_CPMMR_CLEAR                                    , RULL(0x210F0107), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_1_CPPM_CPMMR_OR                                       , RULL(0x210F0108), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_CPPM_CPMMR                                          , RULL(0x220F0106), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPPM_CPMMR_CLEAR                                    , RULL(0x220F0107), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_2_CPPM_CPMMR_OR                                       , RULL(0x220F0108), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_CPPM_CPMMR                                          , RULL(0x230F0106), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPPM_CPMMR_CLEAR                                    , RULL(0x230F0107), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_3_CPPM_CPMMR_OR                                       , RULL(0x230F0108), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_CPPM_CPMMR                                          , RULL(0x240F0106), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPPM_CPMMR_CLEAR                                    , RULL(0x240F0107), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_4_CPPM_CPMMR_OR                                       , RULL(0x240F0108), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_CPPM_CPMMR                                          , RULL(0x250F0106), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPPM_CPMMR_CLEAR                                    , RULL(0x250F0107), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_5_CPPM_CPMMR_OR                                       , RULL(0x250F0108), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_CPPM_CPMMR                                          , RULL(0x260F0106), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPPM_CPMMR_CLEAR                                    , RULL(0x260F0107), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_6_CPPM_CPMMR_OR                                       , RULL(0x260F0108), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_CPPM_CPMMR                                          , RULL(0x270F0106), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPPM_CPMMR_CLEAR                                    , RULL(0x270F0107), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_7_CPPM_CPMMR_OR                                       , RULL(0x270F0108), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_CPPM_CPMMR                                          , RULL(0x280F0106), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPPM_CPMMR_CLEAR                                    , RULL(0x280F0107), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_8_CPPM_CPMMR_OR                                       , RULL(0x280F0108), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_CPPM_CPMMR                                          , RULL(0x290F0106), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPPM_CPMMR_CLEAR                                    , RULL(0x290F0107), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_9_CPPM_CPMMR_OR                                       , RULL(0x290F0108), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_CPPM_CPMMR                                         , RULL(0x2A0F0106), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_CPPM_CPMMR_CLEAR                                   , RULL(0x2A0F0107), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_10_CPPM_CPMMR_OR                                      , RULL(0x2A0F0108), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_CPPM_CPMMR                                         , RULL(0x2B0F0106), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPPM_CPMMR_CLEAR                                   , RULL(0x2B0F0107), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_11_CPPM_CPMMR_OR                                      , RULL(0x2B0F0108), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_CPPM_CPMMR                                         , RULL(0x2C0F0106), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPPM_CPMMR_CLEAR                                   , RULL(0x2C0F0107), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_12_CPPM_CPMMR_OR                                      , RULL(0x2C0F0108), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_CPPM_CPMMR                                         , RULL(0x2D0F0106), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPPM_CPMMR_CLEAR                                   , RULL(0x2D0F0107), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_13_CPPM_CPMMR_OR                                      , RULL(0x2D0F0108), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_CPPM_CPMMR                                         , RULL(0x2E0F0106), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPPM_CPMMR_CLEAR                                   , RULL(0x2E0F0107), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_14_CPPM_CPMMR_OR                                      , RULL(0x2E0F0108), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_CPPM_CPMMR                                         , RULL(0x2F0F0106), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPPM_CPMMR_CLEAR                                   , RULL(0x2F0F0107), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_15_CPPM_CPMMR_OR                                      , RULL(0x2F0F0108), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_CPPM_CPMMR                                         , RULL(0x300F0106), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPPM_CPMMR_CLEAR                                   , RULL(0x300F0107), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_16_CPPM_CPMMR_OR                                      , RULL(0x300F0108), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_CPPM_CPMMR                                         , RULL(0x310F0106), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPPM_CPMMR_CLEAR                                   , RULL(0x310F0107), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_17_CPPM_CPMMR_OR                                      , RULL(0x310F0108), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_CPPM_CPMMR                                         , RULL(0x320F0106), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPPM_CPMMR_CLEAR                                   , RULL(0x320F0107), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_18_CPPM_CPMMR_OR                                      , RULL(0x320F0108), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_CPPM_CPMMR                                         , RULL(0x330F0106), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPPM_CPMMR_CLEAR                                   , RULL(0x330F0107), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_19_CPPM_CPMMR_OR                                      , RULL(0x330F0108), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_CPPM_CPMMR                                         , RULL(0x340F0106), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPPM_CPMMR_CLEAR                                   , RULL(0x340F0107), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_20_CPPM_CPMMR_OR                                      , RULL(0x340F0108), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_CPPM_CPMMR                                         , RULL(0x350F0106), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPPM_CPMMR_CLEAR                                   , RULL(0x350F0107), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_21_CPPM_CPMMR_OR                                      , RULL(0x350F0108), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_CPPM_CPMMR                                         , RULL(0x360F0106), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPPM_CPMMR_CLEAR                                   , RULL(0x360F0107), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_22_CPPM_CPMMR_OR                                      , RULL(0x360F0108), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_CPPM_CPMMR                                         , RULL(0x370F0106), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPPM_CPMMR_CLEAR                                   , RULL(0x370F0107), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_23_CPPM_CPMMR_OR                                      , RULL(0x370F0108), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EX_CPPM_CPMMR                                           , RULL(0x200F0106), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0106,
+REG64( EX_CPPM_CPMMR_CLEAR                                     , RULL(0x200F0107), SH_UNT_EX       ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0107,
+REG64( EX_CPPM_CPMMR_OR                                        , RULL(0x200F0108), SH_UNT_EX       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F0108,
+REG64( EX_0_CPPM_CPMMR                                         , RULL(0x200F0106), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0106,
+REG64( EX_0_CPPM_CPMMR_CLEAR                                   , RULL(0x200F0107), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0107,
+REG64( EX_0_CPPM_CPMMR_OR                                      , RULL(0x200F0108), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F0108,
+REG64( EX_1_CPPM_CPMMR                                         , RULL(0x230F0106), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0106,
+REG64( EX_1_CPPM_CPMMR_CLEAR                                   , RULL(0x230F0107), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 220F0107,
+REG64( EX_1_CPPM_CPMMR_OR                                      , RULL(0x230F0108), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 220F0108,
+REG64( EX_2_CPPM_CPMMR                                         , RULL(0x240F0106), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0106,
+REG64( EX_2_CPPM_CPMMR_CLEAR                                   , RULL(0x240F0107), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 250F0107,
+REG64( EX_2_CPPM_CPMMR_OR                                      , RULL(0x240F0108), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 250F0108,
+REG64( EX_3_CPPM_CPMMR                                         , RULL(0x260F0106), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0106,
+REG64( EX_3_CPPM_CPMMR_CLEAR                                   , RULL(0x260F0107), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 270F0107,
+REG64( EX_3_CPPM_CPMMR_OR                                      , RULL(0x260F0108), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 270F0108,
+REG64( EX_4_CPPM_CPMMR                                         , RULL(0x280F0106), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0106,
+REG64( EX_4_CPPM_CPMMR_CLEAR                                   , RULL(0x280F0107), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 290F0107,
+REG64( EX_4_CPPM_CPMMR_OR                                      , RULL(0x280F0108), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 290F0108,
+REG64( EX_5_CPPM_CPMMR                                         , RULL(0x2A0F0106), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0106,
+REG64( EX_5_CPPM_CPMMR_CLEAR                                   , RULL(0x2A0F0107), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2B0F0107,
+REG64( EX_5_CPPM_CPMMR_OR                                      , RULL(0x2A0F0108), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2B0F0108,
+REG64( EX_6_CPPM_CPMMR                                         , RULL(0x2C0F0106), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0106,
+REG64( EX_6_CPPM_CPMMR_CLEAR                                   , RULL(0x2C0F0107), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2D0F0107,
+REG64( EX_6_CPPM_CPMMR_OR                                      , RULL(0x2C0F0108), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2D0F0108,
+REG64( EX_7_CPPM_CPMMR                                         , RULL(0x2E0F0106), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0106,
+REG64( EX_7_CPPM_CPMMR_CLEAR                                   , RULL(0x2E0F0107), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2F0F0107,
+REG64( EX_7_CPPM_CPMMR_OR                                      , RULL(0x2E0F0108), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2F0F0108,
+REG64( EX_8_CPPM_CPMMR                                         , RULL(0x300F0106), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0106,
+REG64( EX_8_CPPM_CPMMR_CLEAR                                   , RULL(0x300F0107), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 310F0107,
+REG64( EX_8_CPPM_CPMMR_OR                                      , RULL(0x300F0108), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 310F0108,
+REG64( EX_9_CPPM_CPMMR                                         , RULL(0x320F0106), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0106,
+REG64( EX_9_CPPM_CPMMR_CLEAR                                   , RULL(0x320F0107), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 330F0107,
+REG64( EX_9_CPPM_CPMMR_OR                                      , RULL(0x320F0108), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 330F0108,
+REG64( EX_10_CPPM_CPMMR                                        , RULL(0x340F0106), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0106,
+REG64( EX_10_CPPM_CPMMR_CLEAR                                  , RULL(0x340F0107), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 350F0107,
+REG64( EX_10_CPPM_CPMMR_OR                                     , RULL(0x340F0108), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 350F0108,
+REG64( EX_11_CPPM_CPMMR                                        , RULL(0x360F0106), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0106,
+REG64( EX_11_CPPM_CPMMR_CLEAR                                  , RULL(0x360F0107), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 370F0107,
+REG64( EX_11_CPPM_CPMMR_OR                                     , RULL(0x360F0108), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 370F0108,
+
+REG64( C_CPPM_CSAR                                             , RULL(0x200F0138), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_CPPM_CSAR_CLEAR                                       , RULL(0x200F0139), SH_UNT_C        ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_CPPM_CSAR_OR                                          , RULL(0x200F013A), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_CPPM_CSAR                                           , RULL(0x200F0138), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_CPPM_CSAR_CLEAR                                     , RULL(0x200F0139), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_0_CPPM_CSAR_OR                                        , RULL(0x200F013A), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_CPPM_CSAR                                           , RULL(0x210F0138), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPPM_CSAR_CLEAR                                     , RULL(0x210F0139), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_1_CPPM_CSAR_OR                                        , RULL(0x210F013A), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_CPPM_CSAR                                           , RULL(0x220F0138), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPPM_CSAR_CLEAR                                     , RULL(0x220F0139), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_2_CPPM_CSAR_OR                                        , RULL(0x220F013A), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_CPPM_CSAR                                           , RULL(0x230F0138), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPPM_CSAR_CLEAR                                     , RULL(0x230F0139), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_3_CPPM_CSAR_OR                                        , RULL(0x230F013A), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_CPPM_CSAR                                           , RULL(0x240F0138), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPPM_CSAR_CLEAR                                     , RULL(0x240F0139), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_4_CPPM_CSAR_OR                                        , RULL(0x240F013A), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_CPPM_CSAR                                           , RULL(0x250F0138), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPPM_CSAR_CLEAR                                     , RULL(0x250F0139), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_5_CPPM_CSAR_OR                                        , RULL(0x250F013A), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_CPPM_CSAR                                           , RULL(0x260F0138), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPPM_CSAR_CLEAR                                     , RULL(0x260F0139), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_6_CPPM_CSAR_OR                                        , RULL(0x260F013A), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_CPPM_CSAR                                           , RULL(0x270F0138), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPPM_CSAR_CLEAR                                     , RULL(0x270F0139), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_7_CPPM_CSAR_OR                                        , RULL(0x270F013A), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_CPPM_CSAR                                           , RULL(0x280F0138), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPPM_CSAR_CLEAR                                     , RULL(0x280F0139), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_8_CPPM_CSAR_OR                                        , RULL(0x280F013A), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_CPPM_CSAR                                           , RULL(0x290F0138), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPPM_CSAR_CLEAR                                     , RULL(0x290F0139), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_9_CPPM_CSAR_OR                                        , RULL(0x290F013A), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_CPPM_CSAR                                          , RULL(0x2A0F0138), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_CPPM_CSAR_CLEAR                                    , RULL(0x2A0F0139), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_10_CPPM_CSAR_OR                                       , RULL(0x2A0F013A), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_CPPM_CSAR                                          , RULL(0x2B0F0138), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPPM_CSAR_CLEAR                                    , RULL(0x2B0F0139), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_11_CPPM_CSAR_OR                                       , RULL(0x2B0F013A), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_CPPM_CSAR                                          , RULL(0x2C0F0138), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPPM_CSAR_CLEAR                                    , RULL(0x2C0F0139), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_12_CPPM_CSAR_OR                                       , RULL(0x2C0F013A), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_CPPM_CSAR                                          , RULL(0x2D0F0138), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPPM_CSAR_CLEAR                                    , RULL(0x2D0F0139), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_13_CPPM_CSAR_OR                                       , RULL(0x2D0F013A), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_CPPM_CSAR                                          , RULL(0x2E0F0138), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPPM_CSAR_CLEAR                                    , RULL(0x2E0F0139), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_14_CPPM_CSAR_OR                                       , RULL(0x2E0F013A), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_CPPM_CSAR                                          , RULL(0x2F0F0138), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPPM_CSAR_CLEAR                                    , RULL(0x2F0F0139), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_15_CPPM_CSAR_OR                                       , RULL(0x2F0F013A), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_CPPM_CSAR                                          , RULL(0x300F0138), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPPM_CSAR_CLEAR                                    , RULL(0x300F0139), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_16_CPPM_CSAR_OR                                       , RULL(0x300F013A), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_CPPM_CSAR                                          , RULL(0x310F0138), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPPM_CSAR_CLEAR                                    , RULL(0x310F0139), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_17_CPPM_CSAR_OR                                       , RULL(0x310F013A), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_CPPM_CSAR                                          , RULL(0x320F0138), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPPM_CSAR_CLEAR                                    , RULL(0x320F0139), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_18_CPPM_CSAR_OR                                       , RULL(0x320F013A), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_CPPM_CSAR                                          , RULL(0x330F0138), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPPM_CSAR_CLEAR                                    , RULL(0x330F0139), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_19_CPPM_CSAR_OR                                       , RULL(0x330F013A), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_CPPM_CSAR                                          , RULL(0x340F0138), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPPM_CSAR_CLEAR                                    , RULL(0x340F0139), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_20_CPPM_CSAR_OR                                       , RULL(0x340F013A), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_CPPM_CSAR                                          , RULL(0x350F0138), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPPM_CSAR_CLEAR                                    , RULL(0x350F0139), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_21_CPPM_CSAR_OR                                       , RULL(0x350F013A), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_CPPM_CSAR                                          , RULL(0x360F0138), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPPM_CSAR_CLEAR                                    , RULL(0x360F0139), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_22_CPPM_CSAR_OR                                       , RULL(0x360F013A), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_CPPM_CSAR                                          , RULL(0x370F0138), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPPM_CSAR_CLEAR                                    , RULL(0x370F0139), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_23_CPPM_CSAR_OR                                       , RULL(0x370F013A), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EX_CPPM_CSAR                                            , RULL(0x200F0138), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0138,
+REG64( EX_CPPM_CSAR_CLEAR                                      , RULL(0x200F0139), SH_UNT_EX       ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0139,
+REG64( EX_CPPM_CSAR_OR                                         , RULL(0x200F013A), SH_UNT_EX       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F013A,
+REG64( EX_0_CPPM_CSAR                                          , RULL(0x200F0138), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0138,
+REG64( EX_0_CPPM_CSAR_CLEAR                                    , RULL(0x200F0139), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F0139,
+REG64( EX_0_CPPM_CSAR_OR                                       , RULL(0x200F013A), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F013A,
+REG64( EX_1_CPPM_CSAR                                          , RULL(0x230F0138), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0138,
+REG64( EX_1_CPPM_CSAR_CLEAR                                    , RULL(0x230F0139), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 220F0139,
+REG64( EX_1_CPPM_CSAR_OR                                       , RULL(0x230F013A), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 220F013A,
+REG64( EX_2_CPPM_CSAR                                          , RULL(0x240F0138), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0138,
+REG64( EX_2_CPPM_CSAR_CLEAR                                    , RULL(0x240F0139), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 250F0139,
+REG64( EX_2_CPPM_CSAR_OR                                       , RULL(0x240F013A), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 250F013A,
+REG64( EX_3_CPPM_CSAR                                          , RULL(0x260F0138), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0138,
+REG64( EX_3_CPPM_CSAR_CLEAR                                    , RULL(0x260F0139), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 270F0139,
+REG64( EX_3_CPPM_CSAR_OR                                       , RULL(0x260F013A), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 270F013A,
+REG64( EX_4_CPPM_CSAR                                          , RULL(0x280F0138), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0138,
+REG64( EX_4_CPPM_CSAR_CLEAR                                    , RULL(0x280F0139), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 290F0139,
+REG64( EX_4_CPPM_CSAR_OR                                       , RULL(0x280F013A), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 290F013A,
+REG64( EX_5_CPPM_CSAR                                          , RULL(0x2A0F0138), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0138,
+REG64( EX_5_CPPM_CSAR_CLEAR                                    , RULL(0x2A0F0139), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2B0F0139,
+REG64( EX_5_CPPM_CSAR_OR                                       , RULL(0x2A0F013A), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2B0F013A,
+REG64( EX_6_CPPM_CSAR                                          , RULL(0x2C0F0138), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0138,
+REG64( EX_6_CPPM_CSAR_CLEAR                                    , RULL(0x2C0F0139), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2D0F0139,
+REG64( EX_6_CPPM_CSAR_OR                                       , RULL(0x2C0F013A), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2D0F013A,
+REG64( EX_7_CPPM_CSAR                                          , RULL(0x2E0F0138), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0138,
+REG64( EX_7_CPPM_CSAR_CLEAR                                    , RULL(0x2E0F0139), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2F0F0139,
+REG64( EX_7_CPPM_CSAR_OR                                       , RULL(0x2E0F013A), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2F0F013A,
+REG64( EX_8_CPPM_CSAR                                          , RULL(0x300F0138), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0138,
+REG64( EX_8_CPPM_CSAR_CLEAR                                    , RULL(0x300F0139), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 310F0139,
+REG64( EX_8_CPPM_CSAR_OR                                       , RULL(0x300F013A), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 310F013A,
+REG64( EX_9_CPPM_CSAR                                          , RULL(0x320F0138), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0138,
+REG64( EX_9_CPPM_CSAR_CLEAR                                    , RULL(0x320F0139), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 330F0139,
+REG64( EX_9_CPPM_CSAR_OR                                       , RULL(0x320F013A), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 330F013A,
+REG64( EX_10_CPPM_CSAR                                         , RULL(0x340F0138), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0138,
+REG64( EX_10_CPPM_CSAR_CLEAR                                   , RULL(0x340F0139), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 350F0139,
+REG64( EX_10_CPPM_CSAR_OR                                      , RULL(0x340F013A), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 350F013A,
+REG64( EX_11_CPPM_CSAR                                         , RULL(0x360F0138), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0138,
+REG64( EX_11_CPPM_CSAR_CLEAR                                   , RULL(0x360F0139), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 370F0139,
+REG64( EX_11_CPPM_CSAR_OR                                      , RULL(0x360F013A), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 370F013A,
+
+REG64( C_CPPM_ERR                                              , RULL(0x200F0121), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_CPPM_ERR                                            , RULL(0x200F0121), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_CPPM_ERR                                            , RULL(0x210F0121), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_CPPM_ERR                                            , RULL(0x220F0121), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_CPPM_ERR                                            , RULL(0x230F0121), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_CPPM_ERR                                            , RULL(0x240F0121), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_CPPM_ERR                                            , RULL(0x250F0121), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_CPPM_ERR                                            , RULL(0x260F0121), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_CPPM_ERR                                            , RULL(0x270F0121), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_CPPM_ERR                                            , RULL(0x280F0121), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_CPPM_ERR                                            , RULL(0x290F0121), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_CPPM_ERR                                           , RULL(0x2A0F0121), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_CPPM_ERR                                           , RULL(0x2B0F0121), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_CPPM_ERR                                           , RULL(0x2C0F0121), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_CPPM_ERR                                           , RULL(0x2D0F0121), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_CPPM_ERR                                           , RULL(0x2E0F0121), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_CPPM_ERR                                           , RULL(0x2F0F0121), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_CPPM_ERR                                           , RULL(0x300F0121), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_CPPM_ERR                                           , RULL(0x310F0121), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_CPPM_ERR                                           , RULL(0x320F0121), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_CPPM_ERR                                           , RULL(0x330F0121), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_CPPM_ERR                                           , RULL(0x340F0121), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_CPPM_ERR                                           , RULL(0x350F0121), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_CPPM_ERR                                           , RULL(0x360F0121), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_CPPM_ERR                                           , RULL(0x370F0121), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_CPPM_ERR                                             , RULL(0x200F0121), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0121,
+REG64( EX_0_CPPM_ERR                                           , RULL(0x200F0121), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0121,
+REG64( EX_1_CPPM_ERR                                           , RULL(0x230F0121), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0121,
+REG64( EX_2_CPPM_ERR                                           , RULL(0x240F0121), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0121,
+REG64( EX_3_CPPM_ERR                                           , RULL(0x260F0121), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0121,
+REG64( EX_4_CPPM_ERR                                           , RULL(0x280F0121), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0121,
+REG64( EX_5_CPPM_ERR                                           , RULL(0x2A0F0121), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0121,
+REG64( EX_6_CPPM_ERR                                           , RULL(0x2C0F0121), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0121,
+REG64( EX_7_CPPM_ERR                                           , RULL(0x2E0F0121), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0121,
+REG64( EX_8_CPPM_ERR                                           , RULL(0x300F0121), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0121,
+REG64( EX_9_CPPM_ERR                                           , RULL(0x320F0121), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0121,
+REG64( EX_10_CPPM_ERR                                          , RULL(0x340F0121), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0121,
+REG64( EX_11_CPPM_ERR                                          , RULL(0x360F0121), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0121,
+
+REG64( C_CPPM_ERRMSK                                           , RULL(0x200F0122), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_CPPM_ERRMSK                                         , RULL(0x200F0122), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPPM_ERRMSK                                         , RULL(0x210F0122), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPPM_ERRMSK                                         , RULL(0x220F0122), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPPM_ERRMSK                                         , RULL(0x230F0122), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPPM_ERRMSK                                         , RULL(0x240F0122), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPPM_ERRMSK                                         , RULL(0x250F0122), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPPM_ERRMSK                                         , RULL(0x260F0122), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPPM_ERRMSK                                         , RULL(0x270F0122), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPPM_ERRMSK                                         , RULL(0x280F0122), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPPM_ERRMSK                                         , RULL(0x290F0122), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_CPPM_ERRMSK                                        , RULL(0x2A0F0122), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPPM_ERRMSK                                        , RULL(0x2B0F0122), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPPM_ERRMSK                                        , RULL(0x2C0F0122), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPPM_ERRMSK                                        , RULL(0x2D0F0122), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPPM_ERRMSK                                        , RULL(0x2E0F0122), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPPM_ERRMSK                                        , RULL(0x2F0F0122), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPPM_ERRMSK                                        , RULL(0x300F0122), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPPM_ERRMSK                                        , RULL(0x310F0122), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPPM_ERRMSK                                        , RULL(0x320F0122), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPPM_ERRMSK                                        , RULL(0x330F0122), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPPM_ERRMSK                                        , RULL(0x340F0122), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPPM_ERRMSK                                        , RULL(0x350F0122), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPPM_ERRMSK                                        , RULL(0x360F0122), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPPM_ERRMSK                                        , RULL(0x370F0122), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_CPPM_ERRMSK                                          , RULL(0x200F0122), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0122,
+REG64( EX_0_CPPM_ERRMSK                                        , RULL(0x200F0122), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0122,
+REG64( EX_1_CPPM_ERRMSK                                        , RULL(0x230F0122), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0122,
+REG64( EX_2_CPPM_ERRMSK                                        , RULL(0x240F0122), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0122,
+REG64( EX_3_CPPM_ERRMSK                                        , RULL(0x260F0122), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0122,
+REG64( EX_4_CPPM_ERRMSK                                        , RULL(0x280F0122), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0122,
+REG64( EX_5_CPPM_ERRMSK                                        , RULL(0x2A0F0122), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0122,
+REG64( EX_6_CPPM_ERRMSK                                        , RULL(0x2C0F0122), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0122,
+REG64( EX_7_CPPM_ERRMSK                                        , RULL(0x2E0F0122), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0122,
+REG64( EX_8_CPPM_ERRMSK                                        , RULL(0x300F0122), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0122,
+REG64( EX_9_CPPM_ERRMSK                                        , RULL(0x320F0122), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0122,
+REG64( EX_10_CPPM_ERRMSK                                       , RULL(0x340F0122), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0122,
+REG64( EX_11_CPPM_ERRMSK                                       , RULL(0x360F0122), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0122,
+
+REG64( C_CPPM_IPPMCMD                                          , RULL(0x200F01C0), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_CPPM_IPPMCMD                                        , RULL(0x200F01C0), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPPM_IPPMCMD                                        , RULL(0x210F01C0), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPPM_IPPMCMD                                        , RULL(0x220F01C0), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPPM_IPPMCMD                                        , RULL(0x230F01C0), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPPM_IPPMCMD                                        , RULL(0x240F01C0), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPPM_IPPMCMD                                        , RULL(0x250F01C0), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPPM_IPPMCMD                                        , RULL(0x260F01C0), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPPM_IPPMCMD                                        , RULL(0x270F01C0), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPPM_IPPMCMD                                        , RULL(0x280F01C0), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPPM_IPPMCMD                                        , RULL(0x290F01C0), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_CPPM_IPPMCMD                                       , RULL(0x2A0F01C0), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPPM_IPPMCMD                                       , RULL(0x2B0F01C0), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPPM_IPPMCMD                                       , RULL(0x2C0F01C0), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPPM_IPPMCMD                                       , RULL(0x2D0F01C0), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPPM_IPPMCMD                                       , RULL(0x2E0F01C0), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPPM_IPPMCMD                                       , RULL(0x2F0F01C0), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPPM_IPPMCMD                                       , RULL(0x300F01C0), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPPM_IPPMCMD                                       , RULL(0x310F01C0), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPPM_IPPMCMD                                       , RULL(0x320F01C0), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPPM_IPPMCMD                                       , RULL(0x330F01C0), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPPM_IPPMCMD                                       , RULL(0x340F01C0), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPPM_IPPMCMD                                       , RULL(0x350F01C0), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPPM_IPPMCMD                                       , RULL(0x360F01C0), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPPM_IPPMCMD                                       , RULL(0x370F01C0), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_CPPM_IPPMCMD                                         , RULL(0x200F01C0), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01C0,
+REG64( EX_0_CPPM_IPPMCMD                                       , RULL(0x200F01C0), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01C0,
+REG64( EX_1_CPPM_IPPMCMD                                       , RULL(0x230F01C0), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F01C0,
+REG64( EX_2_CPPM_IPPMCMD                                       , RULL(0x240F01C0), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F01C0,
+REG64( EX_3_CPPM_IPPMCMD                                       , RULL(0x260F01C0), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F01C0,
+REG64( EX_4_CPPM_IPPMCMD                                       , RULL(0x280F01C0), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F01C0,
+REG64( EX_5_CPPM_IPPMCMD                                       , RULL(0x2A0F01C0), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F01C0,
+REG64( EX_6_CPPM_IPPMCMD                                       , RULL(0x2C0F01C0), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F01C0,
+REG64( EX_7_CPPM_IPPMCMD                                       , RULL(0x2E0F01C0), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F01C0,
+REG64( EX_8_CPPM_IPPMCMD                                       , RULL(0x300F01C0), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F01C0,
+REG64( EX_9_CPPM_IPPMCMD                                       , RULL(0x320F01C0), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F01C0,
+REG64( EX_10_CPPM_IPPMCMD                                      , RULL(0x340F01C0), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F01C0,
+REG64( EX_11_CPPM_IPPMCMD                                      , RULL(0x360F01C0), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F01C0,
+
+REG64( C_CPPM_IPPMRDATA                                        , RULL(0x200F01C3), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_CPPM_IPPMRDATA                                      , RULL(0x200F01C3), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPPM_IPPMRDATA                                      , RULL(0x210F01C3), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPPM_IPPMRDATA                                      , RULL(0x220F01C3), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPPM_IPPMRDATA                                      , RULL(0x230F01C3), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPPM_IPPMRDATA                                      , RULL(0x240F01C3), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPPM_IPPMRDATA                                      , RULL(0x250F01C3), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPPM_IPPMRDATA                                      , RULL(0x260F01C3), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPPM_IPPMRDATA                                      , RULL(0x270F01C3), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPPM_IPPMRDATA                                      , RULL(0x280F01C3), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPPM_IPPMRDATA                                      , RULL(0x290F01C3), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_CPPM_IPPMRDATA                                     , RULL(0x2A0F01C3), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPPM_IPPMRDATA                                     , RULL(0x2B0F01C3), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPPM_IPPMRDATA                                     , RULL(0x2C0F01C3), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPPM_IPPMRDATA                                     , RULL(0x2D0F01C3), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPPM_IPPMRDATA                                     , RULL(0x2E0F01C3), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPPM_IPPMRDATA                                     , RULL(0x2F0F01C3), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPPM_IPPMRDATA                                     , RULL(0x300F01C3), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPPM_IPPMRDATA                                     , RULL(0x310F01C3), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPPM_IPPMRDATA                                     , RULL(0x320F01C3), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPPM_IPPMRDATA                                     , RULL(0x330F01C3), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPPM_IPPMRDATA                                     , RULL(0x340F01C3), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPPM_IPPMRDATA                                     , RULL(0x350F01C3), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPPM_IPPMRDATA                                     , RULL(0x360F01C3), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPPM_IPPMRDATA                                     , RULL(0x370F01C3), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_CPPM_IPPMRDATA                                       , RULL(0x200F01C3), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01C3,
+REG64( EX_0_CPPM_IPPMRDATA                                     , RULL(0x200F01C3), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01C3,
+REG64( EX_1_CPPM_IPPMRDATA                                     , RULL(0x230F01C3), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F01C3,
+REG64( EX_2_CPPM_IPPMRDATA                                     , RULL(0x240F01C3), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F01C3,
+REG64( EX_3_CPPM_IPPMRDATA                                     , RULL(0x260F01C3), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F01C3,
+REG64( EX_4_CPPM_IPPMRDATA                                     , RULL(0x280F01C3), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F01C3,
+REG64( EX_5_CPPM_IPPMRDATA                                     , RULL(0x2A0F01C3), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F01C3,
+REG64( EX_6_CPPM_IPPMRDATA                                     , RULL(0x2C0F01C3), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F01C3,
+REG64( EX_7_CPPM_IPPMRDATA                                     , RULL(0x2E0F01C3), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F01C3,
+REG64( EX_8_CPPM_IPPMRDATA                                     , RULL(0x300F01C3), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F01C3,
+REG64( EX_9_CPPM_IPPMRDATA                                     , RULL(0x320F01C3), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F01C3,
+REG64( EX_10_CPPM_IPPMRDATA                                    , RULL(0x340F01C3), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F01C3,
+REG64( EX_11_CPPM_IPPMRDATA                                    , RULL(0x360F01C3), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F01C3,
+
+REG64( C_CPPM_IPPMSTAT                                         , RULL(0x200F01C1), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_CPPM_IPPMSTAT                                       , RULL(0x200F01C1), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_CPPM_IPPMSTAT                                       , RULL(0x210F01C1), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_CPPM_IPPMSTAT                                       , RULL(0x220F01C1), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_CPPM_IPPMSTAT                                       , RULL(0x230F01C1), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_CPPM_IPPMSTAT                                       , RULL(0x240F01C1), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_CPPM_IPPMSTAT                                       , RULL(0x250F01C1), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_CPPM_IPPMSTAT                                       , RULL(0x260F01C1), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_CPPM_IPPMSTAT                                       , RULL(0x270F01C1), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_CPPM_IPPMSTAT                                       , RULL(0x280F01C1), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_CPPM_IPPMSTAT                                       , RULL(0x290F01C1), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_CPPM_IPPMSTAT                                      , RULL(0x2A0F01C1), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_CPPM_IPPMSTAT                                      , RULL(0x2B0F01C1), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_CPPM_IPPMSTAT                                      , RULL(0x2C0F01C1), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_CPPM_IPPMSTAT                                      , RULL(0x2D0F01C1), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_CPPM_IPPMSTAT                                      , RULL(0x2E0F01C1), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_CPPM_IPPMSTAT                                      , RULL(0x2F0F01C1), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_CPPM_IPPMSTAT                                      , RULL(0x300F01C1), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_CPPM_IPPMSTAT                                      , RULL(0x310F01C1), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_CPPM_IPPMSTAT                                      , RULL(0x320F01C1), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_CPPM_IPPMSTAT                                      , RULL(0x330F01C1), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_CPPM_IPPMSTAT                                      , RULL(0x340F01C1), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_CPPM_IPPMSTAT                                      , RULL(0x350F01C1), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_CPPM_IPPMSTAT                                      , RULL(0x360F01C1), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_CPPM_IPPMSTAT                                      , RULL(0x370F01C1), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_CPPM_IPPMSTAT                                        , RULL(0x200F01C1), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F01C1,
+REG64( EX_0_CPPM_IPPMSTAT                                      , RULL(0x200F01C1), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F01C1,
+REG64( EX_1_CPPM_IPPMSTAT                                      , RULL(0x230F01C1), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 220F01C1,
+REG64( EX_2_CPPM_IPPMSTAT                                      , RULL(0x240F01C1), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 250F01C1,
+REG64( EX_3_CPPM_IPPMSTAT                                      , RULL(0x260F01C1), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 270F01C1,
+REG64( EX_4_CPPM_IPPMSTAT                                      , RULL(0x280F01C1), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 290F01C1,
+REG64( EX_5_CPPM_IPPMSTAT                                      , RULL(0x2A0F01C1), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B0F01C1,
+REG64( EX_6_CPPM_IPPMSTAT                                      , RULL(0x2C0F01C1), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D0F01C1,
+REG64( EX_7_CPPM_IPPMSTAT                                      , RULL(0x2E0F01C1), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F0F01C1,
+REG64( EX_8_CPPM_IPPMSTAT                                      , RULL(0x300F01C1), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 310F01C1,
+REG64( EX_9_CPPM_IPPMSTAT                                      , RULL(0x320F01C1), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 330F01C1,
+REG64( EX_10_CPPM_IPPMSTAT                                     , RULL(0x340F01C1), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 350F01C1,
+REG64( EX_11_CPPM_IPPMSTAT                                     , RULL(0x360F01C1), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 370F01C1,
+
+REG64( C_CPPM_IPPMWDATA                                        , RULL(0x200F01C2), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_CPPM_IPPMWDATA                                      , RULL(0x200F01C2), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPPM_IPPMWDATA                                      , RULL(0x210F01C2), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPPM_IPPMWDATA                                      , RULL(0x220F01C2), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPPM_IPPMWDATA                                      , RULL(0x230F01C2), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPPM_IPPMWDATA                                      , RULL(0x240F01C2), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPPM_IPPMWDATA                                      , RULL(0x250F01C2), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPPM_IPPMWDATA                                      , RULL(0x260F01C2), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPPM_IPPMWDATA                                      , RULL(0x270F01C2), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPPM_IPPMWDATA                                      , RULL(0x280F01C2), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPPM_IPPMWDATA                                      , RULL(0x290F01C2), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_CPPM_IPPMWDATA                                     , RULL(0x2A0F01C2), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPPM_IPPMWDATA                                     , RULL(0x2B0F01C2), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPPM_IPPMWDATA                                     , RULL(0x2C0F01C2), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPPM_IPPMWDATA                                     , RULL(0x2D0F01C2), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPPM_IPPMWDATA                                     , RULL(0x2E0F01C2), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPPM_IPPMWDATA                                     , RULL(0x2F0F01C2), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPPM_IPPMWDATA                                     , RULL(0x300F01C2), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPPM_IPPMWDATA                                     , RULL(0x310F01C2), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPPM_IPPMWDATA                                     , RULL(0x320F01C2), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPPM_IPPMWDATA                                     , RULL(0x330F01C2), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPPM_IPPMWDATA                                     , RULL(0x340F01C2), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPPM_IPPMWDATA                                     , RULL(0x350F01C2), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPPM_IPPMWDATA                                     , RULL(0x360F01C2), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPPM_IPPMWDATA                                     , RULL(0x370F01C2), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_CPPM_IPPMWDATA                                       , RULL(0x200F01C2), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01C2,
+REG64( EX_0_CPPM_IPPMWDATA                                     , RULL(0x200F01C2), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01C2,
+REG64( EX_1_CPPM_IPPMWDATA                                     , RULL(0x230F01C2), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F01C2,
+REG64( EX_2_CPPM_IPPMWDATA                                     , RULL(0x240F01C2), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F01C2,
+REG64( EX_3_CPPM_IPPMWDATA                                     , RULL(0x260F01C2), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F01C2,
+REG64( EX_4_CPPM_IPPMWDATA                                     , RULL(0x280F01C2), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F01C2,
+REG64( EX_5_CPPM_IPPMWDATA                                     , RULL(0x2A0F01C2), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F01C2,
+REG64( EX_6_CPPM_IPPMWDATA                                     , RULL(0x2C0F01C2), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F01C2,
+REG64( EX_7_CPPM_IPPMWDATA                                     , RULL(0x2E0F01C2), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F01C2,
+REG64( EX_8_CPPM_IPPMWDATA                                     , RULL(0x300F01C2), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F01C2,
+REG64( EX_9_CPPM_IPPMWDATA                                     , RULL(0x320F01C2), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F01C2,
+REG64( EX_10_CPPM_IPPMWDATA                                    , RULL(0x340F01C2), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F01C2,
+REG64( EX_11_CPPM_IPPMWDATA                                    , RULL(0x360F01C2), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F01C2,
+
+REG64( C_CPPM_NC0INDIR_SCOM                                    , RULL(0x200F0130), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_CPPM_NC0INDIR_SCOM1                                   , RULL(0x200F0131), SH_UNT_C        , SH_ACS_SCOM1_NC  );
+REG64( C_CPPM_NC0INDIR_SCOM2                                   , RULL(0x200F0132), SH_UNT_C        , SH_ACS_SCOM2_NC  );
+REG64( C_0_CPPM_NC0INDIR_SCOM                                  , RULL(0x200F0130), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_0_CPPM_NC0INDIR_SCOM1                                 , RULL(0x200F0131), SH_UNT_C_0      , SH_ACS_SCOM1_NC  );
+REG64( C_0_CPPM_NC0INDIR_SCOM2                                 , RULL(0x200F0132), SH_UNT_C_0      , SH_ACS_SCOM2_NC  );
+REG64( C_1_CPPM_NC0INDIR_SCOM                                  , RULL(0x210F0130), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_1_CPPM_NC0INDIR_SCOM1                                 , RULL(0x210F0131), SH_UNT_C_1      , SH_ACS_SCOM1_NC  );
+REG64( C_1_CPPM_NC0INDIR_SCOM2                                 , RULL(0x210F0132), SH_UNT_C_1      , SH_ACS_SCOM2_NC  );
+REG64( C_2_CPPM_NC0INDIR_SCOM                                  , RULL(0x220F0130), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_2_CPPM_NC0INDIR_SCOM1                                 , RULL(0x220F0131), SH_UNT_C_2      , SH_ACS_SCOM1_NC  );
+REG64( C_2_CPPM_NC0INDIR_SCOM2                                 , RULL(0x220F0132), SH_UNT_C_2      , SH_ACS_SCOM2_NC  );
+REG64( C_3_CPPM_NC0INDIR_SCOM                                  , RULL(0x230F0130), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_3_CPPM_NC0INDIR_SCOM1                                 , RULL(0x230F0131), SH_UNT_C_3      , SH_ACS_SCOM1_NC  );
+REG64( C_3_CPPM_NC0INDIR_SCOM2                                 , RULL(0x230F0132), SH_UNT_C_3      , SH_ACS_SCOM2_NC  );
+REG64( C_4_CPPM_NC0INDIR_SCOM                                  , RULL(0x240F0130), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_4_CPPM_NC0INDIR_SCOM1                                 , RULL(0x240F0131), SH_UNT_C_4      , SH_ACS_SCOM1_NC  );
+REG64( C_4_CPPM_NC0INDIR_SCOM2                                 , RULL(0x240F0132), SH_UNT_C_4      , SH_ACS_SCOM2_NC  );
+REG64( C_5_CPPM_NC0INDIR_SCOM                                  , RULL(0x250F0130), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_5_CPPM_NC0INDIR_SCOM1                                 , RULL(0x250F0131), SH_UNT_C_5      , SH_ACS_SCOM1_NC  );
+REG64( C_5_CPPM_NC0INDIR_SCOM2                                 , RULL(0x250F0132), SH_UNT_C_5      , SH_ACS_SCOM2_NC  );
+REG64( C_6_CPPM_NC0INDIR_SCOM                                  , RULL(0x260F0130), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_6_CPPM_NC0INDIR_SCOM1                                 , RULL(0x260F0131), SH_UNT_C_6      , SH_ACS_SCOM1_NC  );
+REG64( C_6_CPPM_NC0INDIR_SCOM2                                 , RULL(0x260F0132), SH_UNT_C_6      , SH_ACS_SCOM2_NC  );
+REG64( C_7_CPPM_NC0INDIR_SCOM                                  , RULL(0x270F0130), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_7_CPPM_NC0INDIR_SCOM1                                 , RULL(0x270F0131), SH_UNT_C_7      , SH_ACS_SCOM1_NC  );
+REG64( C_7_CPPM_NC0INDIR_SCOM2                                 , RULL(0x270F0132), SH_UNT_C_7      , SH_ACS_SCOM2_NC  );
+REG64( C_8_CPPM_NC0INDIR_SCOM                                  , RULL(0x280F0130), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_8_CPPM_NC0INDIR_SCOM1                                 , RULL(0x280F0131), SH_UNT_C_8      , SH_ACS_SCOM1_NC  );
+REG64( C_8_CPPM_NC0INDIR_SCOM2                                 , RULL(0x280F0132), SH_UNT_C_8      , SH_ACS_SCOM2_NC  );
+REG64( C_9_CPPM_NC0INDIR_SCOM                                  , RULL(0x290F0130), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_9_CPPM_NC0INDIR_SCOM1                                 , RULL(0x290F0131), SH_UNT_C_9      , SH_ACS_SCOM1_NC  );
+REG64( C_9_CPPM_NC0INDIR_SCOM2                                 , RULL(0x290F0132), SH_UNT_C_9      , SH_ACS_SCOM2_NC  );
+REG64( C_10_CPPM_NC0INDIR_SCOM                                 , RULL(0x2A0F0130), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_10_CPPM_NC0INDIR_SCOM1                                , RULL(0x2A0F0131), SH_UNT_C_10     , SH_ACS_SCOM1_NC  );
+REG64( C_10_CPPM_NC0INDIR_SCOM2                                , RULL(0x2A0F0132), SH_UNT_C_10     , SH_ACS_SCOM2_NC  );
+REG64( C_11_CPPM_NC0INDIR_SCOM                                 , RULL(0x2B0F0130), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_11_CPPM_NC0INDIR_SCOM1                                , RULL(0x2B0F0131), SH_UNT_C_11     , SH_ACS_SCOM1_NC  );
+REG64( C_11_CPPM_NC0INDIR_SCOM2                                , RULL(0x2B0F0132), SH_UNT_C_11     , SH_ACS_SCOM2_NC  );
+REG64( C_12_CPPM_NC0INDIR_SCOM                                 , RULL(0x2C0F0130), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_12_CPPM_NC0INDIR_SCOM1                                , RULL(0x2C0F0131), SH_UNT_C_12     , SH_ACS_SCOM1_NC  );
+REG64( C_12_CPPM_NC0INDIR_SCOM2                                , RULL(0x2C0F0132), SH_UNT_C_12     , SH_ACS_SCOM2_NC  );
+REG64( C_13_CPPM_NC0INDIR_SCOM                                 , RULL(0x2D0F0130), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_13_CPPM_NC0INDIR_SCOM1                                , RULL(0x2D0F0131), SH_UNT_C_13     , SH_ACS_SCOM1_NC  );
+REG64( C_13_CPPM_NC0INDIR_SCOM2                                , RULL(0x2D0F0132), SH_UNT_C_13     , SH_ACS_SCOM2_NC  );
+REG64( C_14_CPPM_NC0INDIR_SCOM                                 , RULL(0x2E0F0130), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_14_CPPM_NC0INDIR_SCOM1                                , RULL(0x2E0F0131), SH_UNT_C_14     , SH_ACS_SCOM1_NC  );
+REG64( C_14_CPPM_NC0INDIR_SCOM2                                , RULL(0x2E0F0132), SH_UNT_C_14     , SH_ACS_SCOM2_NC  );
+REG64( C_15_CPPM_NC0INDIR_SCOM                                 , RULL(0x2F0F0130), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_15_CPPM_NC0INDIR_SCOM1                                , RULL(0x2F0F0131), SH_UNT_C_15     , SH_ACS_SCOM1_NC  );
+REG64( C_15_CPPM_NC0INDIR_SCOM2                                , RULL(0x2F0F0132), SH_UNT_C_15     , SH_ACS_SCOM2_NC  );
+REG64( C_16_CPPM_NC0INDIR_SCOM                                 , RULL(0x300F0130), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_16_CPPM_NC0INDIR_SCOM1                                , RULL(0x300F0131), SH_UNT_C_16     , SH_ACS_SCOM1_NC  );
+REG64( C_16_CPPM_NC0INDIR_SCOM2                                , RULL(0x300F0132), SH_UNT_C_16     , SH_ACS_SCOM2_NC  );
+REG64( C_17_CPPM_NC0INDIR_SCOM                                 , RULL(0x310F0130), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_17_CPPM_NC0INDIR_SCOM1                                , RULL(0x310F0131), SH_UNT_C_17     , SH_ACS_SCOM1_NC  );
+REG64( C_17_CPPM_NC0INDIR_SCOM2                                , RULL(0x310F0132), SH_UNT_C_17     , SH_ACS_SCOM2_NC  );
+REG64( C_18_CPPM_NC0INDIR_SCOM                                 , RULL(0x320F0130), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_18_CPPM_NC0INDIR_SCOM1                                , RULL(0x320F0131), SH_UNT_C_18     , SH_ACS_SCOM1_NC  );
+REG64( C_18_CPPM_NC0INDIR_SCOM2                                , RULL(0x320F0132), SH_UNT_C_18     , SH_ACS_SCOM2_NC  );
+REG64( C_19_CPPM_NC0INDIR_SCOM                                 , RULL(0x330F0130), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_19_CPPM_NC0INDIR_SCOM1                                , RULL(0x330F0131), SH_UNT_C_19     , SH_ACS_SCOM1_NC  );
+REG64( C_19_CPPM_NC0INDIR_SCOM2                                , RULL(0x330F0132), SH_UNT_C_19     , SH_ACS_SCOM2_NC  );
+REG64( C_20_CPPM_NC0INDIR_SCOM                                 , RULL(0x340F0130), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_20_CPPM_NC0INDIR_SCOM1                                , RULL(0x340F0131), SH_UNT_C_20     , SH_ACS_SCOM1_NC  );
+REG64( C_20_CPPM_NC0INDIR_SCOM2                                , RULL(0x340F0132), SH_UNT_C_20     , SH_ACS_SCOM2_NC  );
+REG64( C_21_CPPM_NC0INDIR_SCOM                                 , RULL(0x350F0130), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_21_CPPM_NC0INDIR_SCOM1                                , RULL(0x350F0131), SH_UNT_C_21     , SH_ACS_SCOM1_NC  );
+REG64( C_21_CPPM_NC0INDIR_SCOM2                                , RULL(0x350F0132), SH_UNT_C_21     , SH_ACS_SCOM2_NC  );
+REG64( C_22_CPPM_NC0INDIR_SCOM                                 , RULL(0x360F0130), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_22_CPPM_NC0INDIR_SCOM1                                , RULL(0x360F0131), SH_UNT_C_22     , SH_ACS_SCOM1_NC  );
+REG64( C_22_CPPM_NC0INDIR_SCOM2                                , RULL(0x360F0132), SH_UNT_C_22     , SH_ACS_SCOM2_NC  );
+REG64( C_23_CPPM_NC0INDIR_SCOM                                 , RULL(0x370F0130), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( C_23_CPPM_NC0INDIR_SCOM1                                , RULL(0x370F0131), SH_UNT_C_23     , SH_ACS_SCOM1_NC  );
+REG64( C_23_CPPM_NC0INDIR_SCOM2                                , RULL(0x370F0132), SH_UNT_C_23     , SH_ACS_SCOM2_NC  );
+REG64( EX_CPPM_NC0INDIR_SCOM                                   , RULL(0x200F0130), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F0130,
+REG64( EX_CPPM_NC0INDIR_SCOM1                                  , RULL(0x200F0131), SH_UNT_EX       ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 210F0131,
+REG64( EX_CPPM_NC0INDIR_SCOM2                                  , RULL(0x200F0132), SH_UNT_EX       ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 210F0132,
+REG64( EX_0_CPPM_NC0INDIR_SCOM                                 , RULL(0x200F0130), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F0130,
+REG64( EX_0_CPPM_NC0INDIR_SCOM1                                , RULL(0x200F0131), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 210F0131,
+REG64( EX_0_CPPM_NC0INDIR_SCOM2                                , RULL(0x200F0132), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 210F0132,
+REG64( EX_1_CPPM_NC0INDIR_SCOM                                 , RULL(0x230F0130), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 220F0130,
+REG64( EX_1_CPPM_NC0INDIR_SCOM1                                , RULL(0x230F0131), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 220F0131,
+REG64( EX_1_CPPM_NC0INDIR_SCOM2                                , RULL(0x230F0132), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 220F0132,
+REG64( EX_2_CPPM_NC0INDIR_SCOM                                 , RULL(0x240F0130), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 250F0130,
+REG64( EX_2_CPPM_NC0INDIR_SCOM1                                , RULL(0x240F0131), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 250F0131,
+REG64( EX_2_CPPM_NC0INDIR_SCOM2                                , RULL(0x240F0132), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 250F0132,
+REG64( EX_3_CPPM_NC0INDIR_SCOM                                 , RULL(0x260F0130), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 270F0130,
+REG64( EX_3_CPPM_NC0INDIR_SCOM1                                , RULL(0x260F0131), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 270F0131,
+REG64( EX_3_CPPM_NC0INDIR_SCOM2                                , RULL(0x260F0132), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 270F0132,
+REG64( EX_4_CPPM_NC0INDIR_SCOM                                 , RULL(0x280F0130), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 290F0130,
+REG64( EX_4_CPPM_NC0INDIR_SCOM1                                , RULL(0x280F0131), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 290F0131,
+REG64( EX_4_CPPM_NC0INDIR_SCOM2                                , RULL(0x280F0132), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 290F0132,
+REG64( EX_5_CPPM_NC0INDIR_SCOM                                 , RULL(0x2A0F0130), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B0F0130,
+REG64( EX_5_CPPM_NC0INDIR_SCOM1                                , RULL(0x2A0F0131), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 2B0F0131,
+REG64( EX_5_CPPM_NC0INDIR_SCOM2                                , RULL(0x2A0F0132), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 2B0F0132,
+REG64( EX_6_CPPM_NC0INDIR_SCOM                                 , RULL(0x2C0F0130), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D0F0130,
+REG64( EX_6_CPPM_NC0INDIR_SCOM1                                , RULL(0x2C0F0131), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 2D0F0131,
+REG64( EX_6_CPPM_NC0INDIR_SCOM2                                , RULL(0x2C0F0132), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 2D0F0132,
+REG64( EX_7_CPPM_NC0INDIR_SCOM                                 , RULL(0x2E0F0130), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F0F0130,
+REG64( EX_7_CPPM_NC0INDIR_SCOM1                                , RULL(0x2E0F0131), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 2F0F0131,
+REG64( EX_7_CPPM_NC0INDIR_SCOM2                                , RULL(0x2E0F0132), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 2F0F0132,
+REG64( EX_8_CPPM_NC0INDIR_SCOM                                 , RULL(0x300F0130), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 310F0130,
+REG64( EX_8_CPPM_NC0INDIR_SCOM1                                , RULL(0x300F0131), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 310F0131,
+REG64( EX_8_CPPM_NC0INDIR_SCOM2                                , RULL(0x300F0132), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 310F0132,
+REG64( EX_9_CPPM_NC0INDIR_SCOM                                 , RULL(0x320F0130), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 330F0130,
+REG64( EX_9_CPPM_NC0INDIR_SCOM1                                , RULL(0x320F0131), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 330F0131,
+REG64( EX_9_CPPM_NC0INDIR_SCOM2                                , RULL(0x320F0132), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 330F0132,
+REG64( EX_10_CPPM_NC0INDIR_SCOM                                , RULL(0x340F0130), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 350F0130,
+REG64( EX_10_CPPM_NC0INDIR_SCOM1                               , RULL(0x340F0131), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 350F0131,
+REG64( EX_10_CPPM_NC0INDIR_SCOM2                               , RULL(0x340F0132), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 350F0132,
+REG64( EX_11_CPPM_NC0INDIR_SCOM                                , RULL(0x360F0130), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 370F0130,
+REG64( EX_11_CPPM_NC0INDIR_SCOM1                               , RULL(0x360F0131), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 370F0131,
+REG64( EX_11_CPPM_NC0INDIR_SCOM2                               , RULL(0x360F0132), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 370F0132,
+
+REG64( C_CPPM_NC1INDIR_SCOM                                    , RULL(0x200F0133), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_CPPM_NC1INDIR_SCOM1                                   , RULL(0x200F0134), SH_UNT_C        , SH_ACS_SCOM1_NC  );
+REG64( C_CPPM_NC1INDIR_SCOM2                                   , RULL(0x200F0135), SH_UNT_C        , SH_ACS_SCOM2_NC  );
+REG64( C_0_CPPM_NC1INDIR_SCOM                                  , RULL(0x200F0133), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_0_CPPM_NC1INDIR_SCOM1                                 , RULL(0x200F0134), SH_UNT_C_0      , SH_ACS_SCOM1_NC  );
+REG64( C_0_CPPM_NC1INDIR_SCOM2                                 , RULL(0x200F0135), SH_UNT_C_0      , SH_ACS_SCOM2_NC  );
+REG64( C_1_CPPM_NC1INDIR_SCOM                                  , RULL(0x210F0133), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_1_CPPM_NC1INDIR_SCOM1                                 , RULL(0x210F0134), SH_UNT_C_1      , SH_ACS_SCOM1_NC  );
+REG64( C_1_CPPM_NC1INDIR_SCOM2                                 , RULL(0x210F0135), SH_UNT_C_1      , SH_ACS_SCOM2_NC  );
+REG64( C_2_CPPM_NC1INDIR_SCOM                                  , RULL(0x220F0133), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_2_CPPM_NC1INDIR_SCOM1                                 , RULL(0x220F0134), SH_UNT_C_2      , SH_ACS_SCOM1_NC  );
+REG64( C_2_CPPM_NC1INDIR_SCOM2                                 , RULL(0x220F0135), SH_UNT_C_2      , SH_ACS_SCOM2_NC  );
+REG64( C_3_CPPM_NC1INDIR_SCOM                                  , RULL(0x230F0133), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_3_CPPM_NC1INDIR_SCOM1                                 , RULL(0x230F0134), SH_UNT_C_3      , SH_ACS_SCOM1_NC  );
+REG64( C_3_CPPM_NC1INDIR_SCOM2                                 , RULL(0x230F0135), SH_UNT_C_3      , SH_ACS_SCOM2_NC  );
+REG64( C_4_CPPM_NC1INDIR_SCOM                                  , RULL(0x240F0133), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_4_CPPM_NC1INDIR_SCOM1                                 , RULL(0x240F0134), SH_UNT_C_4      , SH_ACS_SCOM1_NC  );
+REG64( C_4_CPPM_NC1INDIR_SCOM2                                 , RULL(0x240F0135), SH_UNT_C_4      , SH_ACS_SCOM2_NC  );
+REG64( C_5_CPPM_NC1INDIR_SCOM                                  , RULL(0x250F0133), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_5_CPPM_NC1INDIR_SCOM1                                 , RULL(0x250F0134), SH_UNT_C_5      , SH_ACS_SCOM1_NC  );
+REG64( C_5_CPPM_NC1INDIR_SCOM2                                 , RULL(0x250F0135), SH_UNT_C_5      , SH_ACS_SCOM2_NC  );
+REG64( C_6_CPPM_NC1INDIR_SCOM                                  , RULL(0x260F0133), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_6_CPPM_NC1INDIR_SCOM1                                 , RULL(0x260F0134), SH_UNT_C_6      , SH_ACS_SCOM1_NC  );
+REG64( C_6_CPPM_NC1INDIR_SCOM2                                 , RULL(0x260F0135), SH_UNT_C_6      , SH_ACS_SCOM2_NC  );
+REG64( C_7_CPPM_NC1INDIR_SCOM                                  , RULL(0x270F0133), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_7_CPPM_NC1INDIR_SCOM1                                 , RULL(0x270F0134), SH_UNT_C_7      , SH_ACS_SCOM1_NC  );
+REG64( C_7_CPPM_NC1INDIR_SCOM2                                 , RULL(0x270F0135), SH_UNT_C_7      , SH_ACS_SCOM2_NC  );
+REG64( C_8_CPPM_NC1INDIR_SCOM                                  , RULL(0x280F0133), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_8_CPPM_NC1INDIR_SCOM1                                 , RULL(0x280F0134), SH_UNT_C_8      , SH_ACS_SCOM1_NC  );
+REG64( C_8_CPPM_NC1INDIR_SCOM2                                 , RULL(0x280F0135), SH_UNT_C_8      , SH_ACS_SCOM2_NC  );
+REG64( C_9_CPPM_NC1INDIR_SCOM                                  , RULL(0x290F0133), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_9_CPPM_NC1INDIR_SCOM1                                 , RULL(0x290F0134), SH_UNT_C_9      , SH_ACS_SCOM1_NC  );
+REG64( C_9_CPPM_NC1INDIR_SCOM2                                 , RULL(0x290F0135), SH_UNT_C_9      , SH_ACS_SCOM2_NC  );
+REG64( C_10_CPPM_NC1INDIR_SCOM                                 , RULL(0x2A0F0133), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_10_CPPM_NC1INDIR_SCOM1                                , RULL(0x2A0F0134), SH_UNT_C_10     , SH_ACS_SCOM1_NC  );
+REG64( C_10_CPPM_NC1INDIR_SCOM2                                , RULL(0x2A0F0135), SH_UNT_C_10     , SH_ACS_SCOM2_NC  );
+REG64( C_11_CPPM_NC1INDIR_SCOM                                 , RULL(0x2B0F0133), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_11_CPPM_NC1INDIR_SCOM1                                , RULL(0x2B0F0134), SH_UNT_C_11     , SH_ACS_SCOM1_NC  );
+REG64( C_11_CPPM_NC1INDIR_SCOM2                                , RULL(0x2B0F0135), SH_UNT_C_11     , SH_ACS_SCOM2_NC  );
+REG64( C_12_CPPM_NC1INDIR_SCOM                                 , RULL(0x2C0F0133), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_12_CPPM_NC1INDIR_SCOM1                                , RULL(0x2C0F0134), SH_UNT_C_12     , SH_ACS_SCOM1_NC  );
+REG64( C_12_CPPM_NC1INDIR_SCOM2                                , RULL(0x2C0F0135), SH_UNT_C_12     , SH_ACS_SCOM2_NC  );
+REG64( C_13_CPPM_NC1INDIR_SCOM                                 , RULL(0x2D0F0133), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_13_CPPM_NC1INDIR_SCOM1                                , RULL(0x2D0F0134), SH_UNT_C_13     , SH_ACS_SCOM1_NC  );
+REG64( C_13_CPPM_NC1INDIR_SCOM2                                , RULL(0x2D0F0135), SH_UNT_C_13     , SH_ACS_SCOM2_NC  );
+REG64( C_14_CPPM_NC1INDIR_SCOM                                 , RULL(0x2E0F0133), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_14_CPPM_NC1INDIR_SCOM1                                , RULL(0x2E0F0134), SH_UNT_C_14     , SH_ACS_SCOM1_NC  );
+REG64( C_14_CPPM_NC1INDIR_SCOM2                                , RULL(0x2E0F0135), SH_UNT_C_14     , SH_ACS_SCOM2_NC  );
+REG64( C_15_CPPM_NC1INDIR_SCOM                                 , RULL(0x2F0F0133), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_15_CPPM_NC1INDIR_SCOM1                                , RULL(0x2F0F0134), SH_UNT_C_15     , SH_ACS_SCOM1_NC  );
+REG64( C_15_CPPM_NC1INDIR_SCOM2                                , RULL(0x2F0F0135), SH_UNT_C_15     , SH_ACS_SCOM2_NC  );
+REG64( C_16_CPPM_NC1INDIR_SCOM                                 , RULL(0x300F0133), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_16_CPPM_NC1INDIR_SCOM1                                , RULL(0x300F0134), SH_UNT_C_16     , SH_ACS_SCOM1_NC  );
+REG64( C_16_CPPM_NC1INDIR_SCOM2                                , RULL(0x300F0135), SH_UNT_C_16     , SH_ACS_SCOM2_NC  );
+REG64( C_17_CPPM_NC1INDIR_SCOM                                 , RULL(0x310F0133), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_17_CPPM_NC1INDIR_SCOM1                                , RULL(0x310F0134), SH_UNT_C_17     , SH_ACS_SCOM1_NC  );
+REG64( C_17_CPPM_NC1INDIR_SCOM2                                , RULL(0x310F0135), SH_UNT_C_17     , SH_ACS_SCOM2_NC  );
+REG64( C_18_CPPM_NC1INDIR_SCOM                                 , RULL(0x320F0133), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_18_CPPM_NC1INDIR_SCOM1                                , RULL(0x320F0134), SH_UNT_C_18     , SH_ACS_SCOM1_NC  );
+REG64( C_18_CPPM_NC1INDIR_SCOM2                                , RULL(0x320F0135), SH_UNT_C_18     , SH_ACS_SCOM2_NC  );
+REG64( C_19_CPPM_NC1INDIR_SCOM                                 , RULL(0x330F0133), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_19_CPPM_NC1INDIR_SCOM1                                , RULL(0x330F0134), SH_UNT_C_19     , SH_ACS_SCOM1_NC  );
+REG64( C_19_CPPM_NC1INDIR_SCOM2                                , RULL(0x330F0135), SH_UNT_C_19     , SH_ACS_SCOM2_NC  );
+REG64( C_20_CPPM_NC1INDIR_SCOM                                 , RULL(0x340F0133), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_20_CPPM_NC1INDIR_SCOM1                                , RULL(0x340F0134), SH_UNT_C_20     , SH_ACS_SCOM1_NC  );
+REG64( C_20_CPPM_NC1INDIR_SCOM2                                , RULL(0x340F0135), SH_UNT_C_20     , SH_ACS_SCOM2_NC  );
+REG64( C_21_CPPM_NC1INDIR_SCOM                                 , RULL(0x350F0133), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_21_CPPM_NC1INDIR_SCOM1                                , RULL(0x350F0134), SH_UNT_C_21     , SH_ACS_SCOM1_NC  );
+REG64( C_21_CPPM_NC1INDIR_SCOM2                                , RULL(0x350F0135), SH_UNT_C_21     , SH_ACS_SCOM2_NC  );
+REG64( C_22_CPPM_NC1INDIR_SCOM                                 , RULL(0x360F0133), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_22_CPPM_NC1INDIR_SCOM1                                , RULL(0x360F0134), SH_UNT_C_22     , SH_ACS_SCOM1_NC  );
+REG64( C_22_CPPM_NC1INDIR_SCOM2                                , RULL(0x360F0135), SH_UNT_C_22     , SH_ACS_SCOM2_NC  );
+REG64( C_23_CPPM_NC1INDIR_SCOM                                 , RULL(0x370F0133), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( C_23_CPPM_NC1INDIR_SCOM1                                , RULL(0x370F0134), SH_UNT_C_23     , SH_ACS_SCOM1_NC  );
+REG64( C_23_CPPM_NC1INDIR_SCOM2                                , RULL(0x370F0135), SH_UNT_C_23     , SH_ACS_SCOM2_NC  );
+REG64( EX_CPPM_NC1INDIR_SCOM                                   , RULL(0x200F0133), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F0133,
+REG64( EX_CPPM_NC1INDIR_SCOM1                                  , RULL(0x200F0134), SH_UNT_EX       ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 210F0134,
+REG64( EX_CPPM_NC1INDIR_SCOM2                                  , RULL(0x200F0135), SH_UNT_EX       ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 210F0135,
+REG64( EX_0_CPPM_NC1INDIR_SCOM                                 , RULL(0x200F0133), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F0133,
+REG64( EX_0_CPPM_NC1INDIR_SCOM1                                , RULL(0x200F0134), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 210F0134,
+REG64( EX_0_CPPM_NC1INDIR_SCOM2                                , RULL(0x200F0135), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 210F0135,
+REG64( EX_1_CPPM_NC1INDIR_SCOM                                 , RULL(0x230F0133), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 220F0133,
+REG64( EX_1_CPPM_NC1INDIR_SCOM1                                , RULL(0x230F0134), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 220F0134,
+REG64( EX_1_CPPM_NC1INDIR_SCOM2                                , RULL(0x230F0135), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 220F0135,
+REG64( EX_2_CPPM_NC1INDIR_SCOM                                 , RULL(0x240F0133), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 250F0133,
+REG64( EX_2_CPPM_NC1INDIR_SCOM1                                , RULL(0x240F0134), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 250F0134,
+REG64( EX_2_CPPM_NC1INDIR_SCOM2                                , RULL(0x240F0135), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 250F0135,
+REG64( EX_3_CPPM_NC1INDIR_SCOM                                 , RULL(0x260F0133), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 270F0133,
+REG64( EX_3_CPPM_NC1INDIR_SCOM1                                , RULL(0x260F0134), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 270F0134,
+REG64( EX_3_CPPM_NC1INDIR_SCOM2                                , RULL(0x260F0135), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 270F0135,
+REG64( EX_4_CPPM_NC1INDIR_SCOM                                 , RULL(0x280F0133), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 290F0133,
+REG64( EX_4_CPPM_NC1INDIR_SCOM1                                , RULL(0x280F0134), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 290F0134,
+REG64( EX_4_CPPM_NC1INDIR_SCOM2                                , RULL(0x280F0135), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 290F0135,
+REG64( EX_5_CPPM_NC1INDIR_SCOM                                 , RULL(0x2A0F0133), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B0F0133,
+REG64( EX_5_CPPM_NC1INDIR_SCOM1                                , RULL(0x2A0F0134), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 2B0F0134,
+REG64( EX_5_CPPM_NC1INDIR_SCOM2                                , RULL(0x2A0F0135), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 2B0F0135,
+REG64( EX_6_CPPM_NC1INDIR_SCOM                                 , RULL(0x2C0F0133), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D0F0133,
+REG64( EX_6_CPPM_NC1INDIR_SCOM1                                , RULL(0x2C0F0134), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 2D0F0134,
+REG64( EX_6_CPPM_NC1INDIR_SCOM2                                , RULL(0x2C0F0135), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 2D0F0135,
+REG64( EX_7_CPPM_NC1INDIR_SCOM                                 , RULL(0x2E0F0133), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F0F0133,
+REG64( EX_7_CPPM_NC1INDIR_SCOM1                                , RULL(0x2E0F0134), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 2F0F0134,
+REG64( EX_7_CPPM_NC1INDIR_SCOM2                                , RULL(0x2E0F0135), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 2F0F0135,
+REG64( EX_8_CPPM_NC1INDIR_SCOM                                 , RULL(0x300F0133), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 310F0133,
+REG64( EX_8_CPPM_NC1INDIR_SCOM1                                , RULL(0x300F0134), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 310F0134,
+REG64( EX_8_CPPM_NC1INDIR_SCOM2                                , RULL(0x300F0135), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 310F0135,
+REG64( EX_9_CPPM_NC1INDIR_SCOM                                 , RULL(0x320F0133), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 330F0133,
+REG64( EX_9_CPPM_NC1INDIR_SCOM1                                , RULL(0x320F0134), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 330F0134,
+REG64( EX_9_CPPM_NC1INDIR_SCOM2                                , RULL(0x320F0135), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 330F0135,
+REG64( EX_10_CPPM_NC1INDIR_SCOM                                , RULL(0x340F0133), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 350F0133,
+REG64( EX_10_CPPM_NC1INDIR_SCOM1                               , RULL(0x340F0134), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 350F0134,
+REG64( EX_10_CPPM_NC1INDIR_SCOM2                               , RULL(0x340F0135), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 350F0135,
+REG64( EX_11_CPPM_NC1INDIR_SCOM                                , RULL(0x360F0133), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 370F0133,
+REG64( EX_11_CPPM_NC1INDIR_SCOM1                               , RULL(0x360F0134), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 370F0134,
+REG64( EX_11_CPPM_NC1INDIR_SCOM2                               , RULL(0x360F0135), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 370F0135,
+
+REG64( C_CPPM_PECES                                            , RULL(0x200F01AF), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_CPPM_PECES                                          , RULL(0x200F01AF), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_CPPM_PECES                                          , RULL(0x210F01AF), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_CPPM_PECES                                          , RULL(0x220F01AF), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_CPPM_PECES                                          , RULL(0x230F01AF), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_CPPM_PECES                                          , RULL(0x240F01AF), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_CPPM_PECES                                          , RULL(0x250F01AF), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_CPPM_PECES                                          , RULL(0x260F01AF), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_CPPM_PECES                                          , RULL(0x270F01AF), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_CPPM_PECES                                          , RULL(0x280F01AF), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_CPPM_PECES                                          , RULL(0x290F01AF), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_CPPM_PECES                                         , RULL(0x2A0F01AF), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_CPPM_PECES                                         , RULL(0x2B0F01AF), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_CPPM_PECES                                         , RULL(0x2C0F01AF), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_CPPM_PECES                                         , RULL(0x2D0F01AF), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_CPPM_PECES                                         , RULL(0x2E0F01AF), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_CPPM_PECES                                         , RULL(0x2F0F01AF), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_CPPM_PECES                                         , RULL(0x300F01AF), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_CPPM_PECES                                         , RULL(0x310F01AF), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_CPPM_PECES                                         , RULL(0x320F01AF), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_CPPM_PECES                                         , RULL(0x330F01AF), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_CPPM_PECES                                         , RULL(0x340F01AF), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_CPPM_PECES                                         , RULL(0x350F01AF), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_CPPM_PECES                                         , RULL(0x360F01AF), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_CPPM_PECES                                         , RULL(0x370F01AF), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_CPPM_PECES                                           , RULL(0x200F01AF), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01AF,
+REG64( EX_0_CPPM_PECES                                         , RULL(0x200F01AF), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01AF,
+REG64( EX_1_CPPM_PECES                                         , RULL(0x230F01AF), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F01AF,
+REG64( EX_2_CPPM_PECES                                         , RULL(0x240F01AF), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F01AF,
+REG64( EX_3_CPPM_PECES                                         , RULL(0x260F01AF), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F01AF,
+REG64( EX_4_CPPM_PECES                                         , RULL(0x280F01AF), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F01AF,
+REG64( EX_5_CPPM_PECES                                         , RULL(0x2A0F01AF), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F01AF,
+REG64( EX_6_CPPM_PECES                                         , RULL(0x2C0F01AF), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F01AF,
+REG64( EX_7_CPPM_PECES                                         , RULL(0x2E0F01AF), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F01AF,
+REG64( EX_8_CPPM_PECES                                         , RULL(0x300F01AF), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F01AF,
+REG64( EX_9_CPPM_PECES                                         , RULL(0x320F01AF), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F01AF,
+REG64( EX_10_CPPM_PECES                                        , RULL(0x340F01AF), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F01AF,
+REG64( EX_11_CPPM_PECES                                        , RULL(0x360F01AF), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F01AF,
+
+REG64( C_CPPM_PERRSUM                                          , RULL(0x200F0120), SH_UNT_C        ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_0_CPPM_PERRSUM                                        , RULL(0x200F0120), SH_UNT_C_0      ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_1_CPPM_PERRSUM                                        , RULL(0x210F0120), SH_UNT_C_1      ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_2_CPPM_PERRSUM                                        , RULL(0x220F0120), SH_UNT_C_2      ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_3_CPPM_PERRSUM                                        , RULL(0x230F0120), SH_UNT_C_3      ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_4_CPPM_PERRSUM                                        , RULL(0x240F0120), SH_UNT_C_4      ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_5_CPPM_PERRSUM                                        , RULL(0x250F0120), SH_UNT_C_5      ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_6_CPPM_PERRSUM                                        , RULL(0x260F0120), SH_UNT_C_6      ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_7_CPPM_PERRSUM                                        , RULL(0x270F0120), SH_UNT_C_7      ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_8_CPPM_PERRSUM                                        , RULL(0x280F0120), SH_UNT_C_8      ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_9_CPPM_PERRSUM                                        , RULL(0x290F0120), SH_UNT_C_9      ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_10_CPPM_PERRSUM                                       , RULL(0x2A0F0120), SH_UNT_C_10     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_11_CPPM_PERRSUM                                       , RULL(0x2B0F0120), SH_UNT_C_11     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_12_CPPM_PERRSUM                                       , RULL(0x2C0F0120), SH_UNT_C_12     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_13_CPPM_PERRSUM                                       , RULL(0x2D0F0120), SH_UNT_C_13     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_14_CPPM_PERRSUM                                       , RULL(0x2E0F0120), SH_UNT_C_14     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_15_CPPM_PERRSUM                                       , RULL(0x2F0F0120), SH_UNT_C_15     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_16_CPPM_PERRSUM                                       , RULL(0x300F0120), SH_UNT_C_16     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_17_CPPM_PERRSUM                                       , RULL(0x310F0120), SH_UNT_C_17     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_18_CPPM_PERRSUM                                       , RULL(0x320F0120), SH_UNT_C_18     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_19_CPPM_PERRSUM                                       , RULL(0x330F0120), SH_UNT_C_19     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_20_CPPM_PERRSUM                                       , RULL(0x340F0120), SH_UNT_C_20     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_21_CPPM_PERRSUM                                       , RULL(0x350F0120), SH_UNT_C_21     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_22_CPPM_PERRSUM                                       , RULL(0x360F0120), SH_UNT_C_22     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( C_23_CPPM_PERRSUM                                       , RULL(0x370F0120), SH_UNT_C_23     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( EX_CPPM_PERRSUM                                         , RULL(0x200F0120), SH_UNT_EX       ,
+       SH_ACS_SCOM_WCLEAR ); //DUPS: 210F0120,
+REG64( EX_0_CPPM_PERRSUM                                       , RULL(0x200F0120), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_WCLEAR ); //DUPS: 210F0120,
+REG64( EX_1_CPPM_PERRSUM                                       , RULL(0x230F0120), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_WCLEAR ); //DUPS: 220F0120,
+REG64( EX_2_CPPM_PERRSUM                                       , RULL(0x240F0120), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_WCLEAR ); //DUPS: 250F0120,
+REG64( EX_3_CPPM_PERRSUM                                       , RULL(0x260F0120), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_WCLEAR ); //DUPS: 270F0120,
+REG64( EX_4_CPPM_PERRSUM                                       , RULL(0x280F0120), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_WCLEAR ); //DUPS: 290F0120,
+REG64( EX_5_CPPM_PERRSUM                                       , RULL(0x2A0F0120), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_WCLEAR ); //DUPS: 2B0F0120,
+REG64( EX_6_CPPM_PERRSUM                                       , RULL(0x2C0F0120), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_WCLEAR ); //DUPS: 2D0F0120,
+REG64( EX_7_CPPM_PERRSUM                                       , RULL(0x2E0F0120), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_WCLEAR ); //DUPS: 2F0F0120,
+REG64( EX_8_CPPM_PERRSUM                                       , RULL(0x300F0120), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_WCLEAR ); //DUPS: 310F0120,
+REG64( EX_9_CPPM_PERRSUM                                       , RULL(0x320F0120), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_WCLEAR ); //DUPS: 330F0120,
+REG64( EX_10_CPPM_PERRSUM                                      , RULL(0x340F0120), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_WCLEAR ); //DUPS: 350F0120,
+REG64( EX_11_CPPM_PERRSUM                                      , RULL(0x360F0120), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_WCLEAR ); //DUPS: 370F0120,
+
+REG64( EQ_CSAR                                                 , RULL(0x1001240D), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001200D,
+REG64( EQ_0_CSAR                                               , RULL(0x1001240D), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001200D,
+REG64( EQ_1_CSAR                                               , RULL(0x1101240D), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1101200D,
+REG64( EQ_2_CSAR                                               , RULL(0x1201240D), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1201200D,
+REG64( EQ_3_CSAR                                               , RULL(0x1301240D), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1301200D,
+REG64( EQ_4_CSAR                                               , RULL(0x1401240D), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1401200D,
+REG64( EQ_5_CSAR                                               , RULL(0x1501240D), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1501200D,
+REG64( EX_CSAR                                                 , RULL(0x1001200D), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CSAR                                               , RULL(0x1001200D), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CSAR                                               , RULL(0x1001240D), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CSAR                                               , RULL(0x1101200D), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CSAR                                               , RULL(0x1101240D), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CSAR                                               , RULL(0x1201200D), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CSAR                                               , RULL(0x1201240D), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CSAR                                               , RULL(0x1301200D), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CSAR                                               , RULL(0x1301240D), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CSAR                                               , RULL(0x1401200D), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CSAR                                               , RULL(0x1401240D), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CSAR                                              , RULL(0x1501200D), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CSAR                                              , RULL(0x1501240D), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_CSCR                                                 , RULL(0x1001240A), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001200A,
+REG64( EQ_CSCR_CLEAR                                           , RULL(0x1001240B), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 1001200B,
+REG64( EQ_CSCR_OR                                              , RULL(0x1001240C), SH_UNT_EQ       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 1001200C,
+REG64( EQ_0_CSCR                                               , RULL(0x1001240A), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001200A,
+REG64( EQ_0_CSCR_CLEAR                                         , RULL(0x1001240B), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 1001200B,
+REG64( EQ_0_CSCR_OR                                            , RULL(0x1001240C), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 1001200C,
+REG64( EQ_1_CSCR                                               , RULL(0x1101240A), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1101200A,
+REG64( EQ_1_CSCR_CLEAR                                         , RULL(0x1101240B), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 1101200B,
+REG64( EQ_1_CSCR_OR                                            , RULL(0x1101240C), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 1101200C,
+REG64( EQ_2_CSCR                                               , RULL(0x1201240A), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1201200A,
+REG64( EQ_2_CSCR_CLEAR                                         , RULL(0x1201240B), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 1201200B,
+REG64( EQ_2_CSCR_OR                                            , RULL(0x1201240C), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 1201200C,
+REG64( EQ_3_CSCR                                               , RULL(0x1301240A), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1301200A,
+REG64( EQ_3_CSCR_CLEAR                                         , RULL(0x1301240B), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 1301200B,
+REG64( EQ_3_CSCR_OR                                            , RULL(0x1301240C), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 1301200C,
+REG64( EQ_4_CSCR                                               , RULL(0x1401240A), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1401200A,
+REG64( EQ_4_CSCR_CLEAR                                         , RULL(0x1401240B), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 1401200B,
+REG64( EQ_4_CSCR_OR                                            , RULL(0x1401240C), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 1401200C,
+REG64( EQ_5_CSCR                                               , RULL(0x1501240A), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1501200A,
+REG64( EQ_5_CSCR_CLEAR                                         , RULL(0x1501240B), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 1501200B,
+REG64( EQ_5_CSCR_OR                                            , RULL(0x1501240C), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 1501200C,
+REG64( EX_CSCR                                                 , RULL(0x1001200A), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_CSCR_CLEAR                                           , RULL(0x1001200B), SH_UNT_EX       ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_CSCR_OR                                              , RULL(0x1001200C), SH_UNT_EX       , SH_ACS_SCOM2_OR  );
+REG64( EX_0_CSCR                                               , RULL(0x1001200A), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_0_CSCR_CLEAR                                         , RULL(0x1001200B), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_0_CSCR_OR                                            , RULL(0x1001200C), SH_UNT_EX_0     , SH_ACS_SCOM2_OR  );
+REG64( EX_1_CSCR                                               , RULL(0x1001240A), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CSCR_CLEAR                                         , RULL(0x1001240B), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_1_CSCR_OR                                            , RULL(0x1001240C), SH_UNT_EX_1     , SH_ACS_SCOM2_OR  );
+REG64( EX_2_CSCR                                               , RULL(0x1101200A), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CSCR_CLEAR                                         , RULL(0x1101200B), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_2_CSCR_OR                                            , RULL(0x1101200C), SH_UNT_EX_2     , SH_ACS_SCOM2_OR  );
+REG64( EX_3_CSCR                                               , RULL(0x1101240A), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CSCR_CLEAR                                         , RULL(0x1101240B), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_3_CSCR_OR                                            , RULL(0x1101240C), SH_UNT_EX_3     , SH_ACS_SCOM2_OR  );
+REG64( EX_4_CSCR                                               , RULL(0x1201200A), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CSCR_CLEAR                                         , RULL(0x1201200B), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_4_CSCR_OR                                            , RULL(0x1201200C), SH_UNT_EX_4     , SH_ACS_SCOM2_OR  );
+REG64( EX_5_CSCR                                               , RULL(0x1201240A), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CSCR_CLEAR                                         , RULL(0x1201240B), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_5_CSCR_OR                                            , RULL(0x1201240C), SH_UNT_EX_5     , SH_ACS_SCOM2_OR  );
+REG64( EX_6_CSCR                                               , RULL(0x1301200A), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CSCR_CLEAR                                         , RULL(0x1301200B), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_6_CSCR_OR                                            , RULL(0x1301200C), SH_UNT_EX_6     , SH_ACS_SCOM2_OR  );
+REG64( EX_7_CSCR                                               , RULL(0x1301240A), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CSCR_CLEAR                                         , RULL(0x1301240B), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_7_CSCR_OR                                            , RULL(0x1301240C), SH_UNT_EX_7     , SH_ACS_SCOM2_OR  );
+REG64( EX_8_CSCR                                               , RULL(0x1401200A), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CSCR_CLEAR                                         , RULL(0x1401200B), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_8_CSCR_OR                                            , RULL(0x1401200C), SH_UNT_EX_8     , SH_ACS_SCOM2_OR  );
+REG64( EX_9_CSCR                                               , RULL(0x1401240A), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CSCR_CLEAR                                         , RULL(0x1401240B), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_9_CSCR_OR                                            , RULL(0x1401240C), SH_UNT_EX_9     , SH_ACS_SCOM2_OR  );
+REG64( EX_10_CSCR                                              , RULL(0x1501200A), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_10_CSCR_CLEAR                                        , RULL(0x1501200B), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_10_CSCR_OR                                           , RULL(0x1501200C), SH_UNT_EX_10    , SH_ACS_SCOM2_OR  );
+REG64( EX_11_CSCR                                              , RULL(0x1501240A), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CSCR_CLEAR                                        , RULL(0x1501240B), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EX_11_CSCR_OR                                           , RULL(0x1501240C), SH_UNT_EX_11    , SH_ACS_SCOM2_OR  );
+
+REG64( EQ_CSDR                                                 , RULL(0x1001240E), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001200E,
+REG64( EQ_0_CSDR                                               , RULL(0x1001240E), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001200E,
+REG64( EQ_1_CSDR                                               , RULL(0x1101240E), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1101200E,
+REG64( EQ_2_CSDR                                               , RULL(0x1201240E), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1201200E,
+REG64( EQ_3_CSDR                                               , RULL(0x1301240E), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1301200E,
+REG64( EQ_4_CSDR                                               , RULL(0x1401240E), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1401200E,
+REG64( EQ_5_CSDR                                               , RULL(0x1501240E), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1501200E,
+REG64( EX_CSDR                                                 , RULL(0x1001200E), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_CSDR                                               , RULL(0x1001200E), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_CSDR                                               , RULL(0x1001240E), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_CSDR                                               , RULL(0x1101200E), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_CSDR                                               , RULL(0x1101240E), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_CSDR                                               , RULL(0x1201200E), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_CSDR                                               , RULL(0x1201240E), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_CSDR                                               , RULL(0x1301200E), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_CSDR                                               , RULL(0x1301240E), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_CSDR                                               , RULL(0x1401200E), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_CSDR                                               , RULL(0x1401240E), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_10_CSDR                                              , RULL(0x1501200E), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_CSDR                                              , RULL(0x1501240E), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+
+REG64( C_CTRL                                                  , RULL(0x20010A85), SH_UNT_C        , SH_ACS_SCOM_NC   );
+REG64( C_0_CTRL                                                , RULL(0x20010A85), SH_UNT_C_0      , SH_ACS_SCOM_NC   );
+REG64( C_1_CTRL                                                , RULL(0x21010A85), SH_UNT_C_1      , SH_ACS_SCOM_NC   );
+REG64( C_2_CTRL                                                , RULL(0x22010A85), SH_UNT_C_2      , SH_ACS_SCOM_NC   );
+REG64( C_3_CTRL                                                , RULL(0x23010A85), SH_UNT_C_3      , SH_ACS_SCOM_NC   );
+REG64( C_4_CTRL                                                , RULL(0x24010A85), SH_UNT_C_4      , SH_ACS_SCOM_NC   );
+REG64( C_5_CTRL                                                , RULL(0x25010A85), SH_UNT_C_5      , SH_ACS_SCOM_NC   );
+REG64( C_6_CTRL                                                , RULL(0x26010A85), SH_UNT_C_6      , SH_ACS_SCOM_NC   );
+REG64( C_7_CTRL                                                , RULL(0x27010A85), SH_UNT_C_7      , SH_ACS_SCOM_NC   );
+REG64( C_8_CTRL                                                , RULL(0x28010A85), SH_UNT_C_8      , SH_ACS_SCOM_NC   );
+REG64( C_9_CTRL                                                , RULL(0x29010A85), SH_UNT_C_9      , SH_ACS_SCOM_NC   );
+REG64( C_10_CTRL                                               , RULL(0x2A010A85), SH_UNT_C_10     , SH_ACS_SCOM_NC   );
+REG64( C_11_CTRL                                               , RULL(0x2B010A85), SH_UNT_C_11     , SH_ACS_SCOM_NC   );
+REG64( C_12_CTRL                                               , RULL(0x2C010A85), SH_UNT_C_12     , SH_ACS_SCOM_NC   );
+REG64( C_13_CTRL                                               , RULL(0x2D010A85), SH_UNT_C_13     , SH_ACS_SCOM_NC   );
+REG64( C_14_CTRL                                               , RULL(0x2E010A85), SH_UNT_C_14     , SH_ACS_SCOM_NC   );
+REG64( C_15_CTRL                                               , RULL(0x2F010A85), SH_UNT_C_15     , SH_ACS_SCOM_NC   );
+REG64( C_16_CTRL                                               , RULL(0x30010A85), SH_UNT_C_16     , SH_ACS_SCOM_NC   );
+REG64( C_17_CTRL                                               , RULL(0x31010A85), SH_UNT_C_17     , SH_ACS_SCOM_NC   );
+REG64( C_18_CTRL                                               , RULL(0x32010A85), SH_UNT_C_18     , SH_ACS_SCOM_NC   );
+REG64( C_19_CTRL                                               , RULL(0x33010A85), SH_UNT_C_19     , SH_ACS_SCOM_NC   );
+REG64( C_20_CTRL                                               , RULL(0x34010A85), SH_UNT_C_20     , SH_ACS_SCOM_NC   );
+REG64( C_21_CTRL                                               , RULL(0x35010A85), SH_UNT_C_21     , SH_ACS_SCOM_NC   );
+REG64( C_22_CTRL                                               , RULL(0x36010A85), SH_UNT_C_22     , SH_ACS_SCOM_NC   );
+REG64( C_23_CTRL                                               , RULL(0x37010A85), SH_UNT_C_23     , SH_ACS_SCOM_NC   );
+REG64( EX_0_L2_CTRL                                            , RULL(0x21010A85), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_NC   ); //DUPS: 20010A85,
+REG64( EX_10_L2_CTRL                                           , RULL(0x35010A85), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_NC   ); //DUPS: 34010A85,
+REG64( EX_11_L2_CTRL                                           , RULL(0x37010A85), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_NC   ); //DUPS: 36010A85,
+REG64( EX_1_L2_CTRL                                            , RULL(0x23010A85), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_NC   ); //DUPS: 22010A85,
+REG64( EX_2_L2_CTRL                                            , RULL(0x25010A85), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_NC   ); //DUPS: 24010A85,
+REG64( EX_3_L2_CTRL                                            , RULL(0x27010A85), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_NC   ); //DUPS: 26010A85,
+REG64( EX_4_L2_CTRL                                            , RULL(0x29010A85), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_NC   ); //DUPS: 28010A85,
+REG64( EX_5_L2_CTRL                                            , RULL(0x2B010A85), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_NC   ); //DUPS: 2A010A85,
+REG64( EX_6_L2_CTRL                                            , RULL(0x2D010A85), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_NC   ); //DUPS: 2C010A85,
+REG64( EX_7_L2_CTRL                                            , RULL(0x2F010A85), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_NC   ); //DUPS: 2E010A85,
+REG64( EX_8_L2_CTRL                                            , RULL(0x31010A85), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_NC   ); //DUPS: 30010A85,
+REG64( EX_9_L2_CTRL                                            , RULL(0x33010A85), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_NC   ); //DUPS: 32010A85,
+REG64( EX_L2_CTRL                                              , RULL(0x21010A85), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_NC   ); //DUPS: 20010A85,
+
+REG64( C_CTRL_ATOMIC_LOCK_REG                                  , RULL(0x200003FF), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_CTRL_ATOMIC_LOCK_REG                                , RULL(0x200003FF), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_CTRL_ATOMIC_LOCK_REG                                , RULL(0x210003FF), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_CTRL_ATOMIC_LOCK_REG                                , RULL(0x220003FF), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_CTRL_ATOMIC_LOCK_REG                                , RULL(0x230003FF), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_CTRL_ATOMIC_LOCK_REG                                , RULL(0x240003FF), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_CTRL_ATOMIC_LOCK_REG                                , RULL(0x250003FF), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_CTRL_ATOMIC_LOCK_REG                                , RULL(0x260003FF), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_CTRL_ATOMIC_LOCK_REG                                , RULL(0x270003FF), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_CTRL_ATOMIC_LOCK_REG                                , RULL(0x280003FF), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_CTRL_ATOMIC_LOCK_REG                                , RULL(0x290003FF), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_CTRL_ATOMIC_LOCK_REG                               , RULL(0x2A0003FF), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_CTRL_ATOMIC_LOCK_REG                               , RULL(0x2B0003FF), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_CTRL_ATOMIC_LOCK_REG                               , RULL(0x2C0003FF), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_CTRL_ATOMIC_LOCK_REG                               , RULL(0x2D0003FF), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_CTRL_ATOMIC_LOCK_REG                               , RULL(0x2E0003FF), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_CTRL_ATOMIC_LOCK_REG                               , RULL(0x2F0003FF), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_CTRL_ATOMIC_LOCK_REG                               , RULL(0x300003FF), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_CTRL_ATOMIC_LOCK_REG                               , RULL(0x310003FF), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_CTRL_ATOMIC_LOCK_REG                               , RULL(0x320003FF), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_CTRL_ATOMIC_LOCK_REG                               , RULL(0x330003FF), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_CTRL_ATOMIC_LOCK_REG                               , RULL(0x340003FF), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_CTRL_ATOMIC_LOCK_REG                               , RULL(0x350003FF), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_CTRL_ATOMIC_LOCK_REG                               , RULL(0x360003FF), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_CTRL_ATOMIC_LOCK_REG                               , RULL(0x370003FF), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_CTRL_ATOMIC_LOCK_REG                                 , RULL(0x100003FF), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_CTRL_ATOMIC_LOCK_REG                               , RULL(0x100003FF), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_CTRL_ATOMIC_LOCK_REG                               , RULL(0x110003FF), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_CTRL_ATOMIC_LOCK_REG                               , RULL(0x120003FF), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_CTRL_ATOMIC_LOCK_REG                               , RULL(0x130003FF), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_CTRL_ATOMIC_LOCK_REG                               , RULL(0x140003FF), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_CTRL_ATOMIC_LOCK_REG                               , RULL(0x150003FF), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_CTRL_ATOMIC_LOCK_REG                                 , RULL(0x200003FF), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210003FF,
+REG64( EX_0_CTRL_ATOMIC_LOCK_REG                               , RULL(0x200003FF), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210003FF,
+REG64( EX_1_CTRL_ATOMIC_LOCK_REG                               , RULL(0x220003FF), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230003FF,
+REG64( EX_2_CTRL_ATOMIC_LOCK_REG                               , RULL(0x240003FF), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250003FF,
+REG64( EX_3_CTRL_ATOMIC_LOCK_REG                               , RULL(0x260003FF), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270003FF,
+REG64( EX_4_CTRL_ATOMIC_LOCK_REG                               , RULL(0x280003FF), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290003FF,
+REG64( EX_5_CTRL_ATOMIC_LOCK_REG                               , RULL(0x2A0003FF), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0003FF,
+REG64( EX_6_CTRL_ATOMIC_LOCK_REG                               , RULL(0x2C0003FF), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0003FF,
+REG64( EX_7_CTRL_ATOMIC_LOCK_REG                               , RULL(0x2E0003FF), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0003FF,
+REG64( EX_8_CTRL_ATOMIC_LOCK_REG                               , RULL(0x300003FF), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310003FF,
+REG64( EX_9_CTRL_ATOMIC_LOCK_REG                               , RULL(0x320003FF), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330003FF,
+REG64( EX_10_CTRL_ATOMIC_LOCK_REG                              , RULL(0x340003FF), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350003FF,
+REG64( EX_11_CTRL_ATOMIC_LOCK_REG                              , RULL(0x360003FF), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370003FF,
+
+REG64( C_CTRL_PROTECT_MODE_REG                                 , RULL(0x200003FE), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_CTRL_PROTECT_MODE_REG                               , RULL(0x200003FE), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_CTRL_PROTECT_MODE_REG                               , RULL(0x210003FE), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_CTRL_PROTECT_MODE_REG                               , RULL(0x220003FE), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_CTRL_PROTECT_MODE_REG                               , RULL(0x230003FE), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_CTRL_PROTECT_MODE_REG                               , RULL(0x240003FE), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_CTRL_PROTECT_MODE_REG                               , RULL(0x250003FE), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_CTRL_PROTECT_MODE_REG                               , RULL(0x260003FE), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_CTRL_PROTECT_MODE_REG                               , RULL(0x270003FE), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_CTRL_PROTECT_MODE_REG                               , RULL(0x280003FE), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_CTRL_PROTECT_MODE_REG                               , RULL(0x290003FE), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_CTRL_PROTECT_MODE_REG                              , RULL(0x2A0003FE), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_CTRL_PROTECT_MODE_REG                              , RULL(0x2B0003FE), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_CTRL_PROTECT_MODE_REG                              , RULL(0x2C0003FE), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_CTRL_PROTECT_MODE_REG                              , RULL(0x2D0003FE), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_CTRL_PROTECT_MODE_REG                              , RULL(0x2E0003FE), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_CTRL_PROTECT_MODE_REG                              , RULL(0x2F0003FE), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_CTRL_PROTECT_MODE_REG                              , RULL(0x300003FE), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_CTRL_PROTECT_MODE_REG                              , RULL(0x310003FE), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_CTRL_PROTECT_MODE_REG                              , RULL(0x320003FE), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_CTRL_PROTECT_MODE_REG                              , RULL(0x330003FE), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_CTRL_PROTECT_MODE_REG                              , RULL(0x340003FE), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_CTRL_PROTECT_MODE_REG                              , RULL(0x350003FE), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_CTRL_PROTECT_MODE_REG                              , RULL(0x360003FE), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_CTRL_PROTECT_MODE_REG                              , RULL(0x370003FE), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_CTRL_PROTECT_MODE_REG                                , RULL(0x100003FE), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_CTRL_PROTECT_MODE_REG                              , RULL(0x100003FE), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_CTRL_PROTECT_MODE_REG                              , RULL(0x110003FE), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_CTRL_PROTECT_MODE_REG                              , RULL(0x120003FE), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_CTRL_PROTECT_MODE_REG                              , RULL(0x130003FE), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_CTRL_PROTECT_MODE_REG                              , RULL(0x140003FE), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_CTRL_PROTECT_MODE_REG                              , RULL(0x150003FE), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_CTRL_PROTECT_MODE_REG                                , RULL(0x200003FE), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210003FE,
+REG64( EX_0_CTRL_PROTECT_MODE_REG                              , RULL(0x200003FE), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210003FE,
+REG64( EX_1_CTRL_PROTECT_MODE_REG                              , RULL(0x220003FE), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230003FE,
+REG64( EX_2_CTRL_PROTECT_MODE_REG                              , RULL(0x240003FE), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250003FE,
+REG64( EX_3_CTRL_PROTECT_MODE_REG                              , RULL(0x260003FE), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270003FE,
+REG64( EX_4_CTRL_PROTECT_MODE_REG                              , RULL(0x280003FE), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290003FE,
+REG64( EX_5_CTRL_PROTECT_MODE_REG                              , RULL(0x2A0003FE), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0003FE,
+REG64( EX_6_CTRL_PROTECT_MODE_REG                              , RULL(0x2C0003FE), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0003FE,
+REG64( EX_7_CTRL_PROTECT_MODE_REG                              , RULL(0x2E0003FE), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0003FE,
+REG64( EX_8_CTRL_PROTECT_MODE_REG                              , RULL(0x300003FE), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310003FE,
+REG64( EX_9_CTRL_PROTECT_MODE_REG                              , RULL(0x320003FE), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330003FE,
+REG64( EX_10_CTRL_PROTECT_MODE_REG                             , RULL(0x340003FE), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350003FE,
+REG64( EX_11_CTRL_PROTECT_MODE_REG                             , RULL(0x360003FE), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370003FE,
+
+REG64( C_DBG_CBS_CC                                            , RULL(0x20030013), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_DBG_CBS_CC                                          , RULL(0x20030013), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_DBG_CBS_CC                                          , RULL(0x21030013), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_DBG_CBS_CC                                          , RULL(0x22030013), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_DBG_CBS_CC                                          , RULL(0x23030013), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_DBG_CBS_CC                                          , RULL(0x24030013), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_DBG_CBS_CC                                          , RULL(0x25030013), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_DBG_CBS_CC                                          , RULL(0x26030013), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_DBG_CBS_CC                                          , RULL(0x27030013), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_DBG_CBS_CC                                          , RULL(0x28030013), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_DBG_CBS_CC                                          , RULL(0x29030013), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_DBG_CBS_CC                                         , RULL(0x2A030013), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_DBG_CBS_CC                                         , RULL(0x2B030013), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_DBG_CBS_CC                                         , RULL(0x2C030013), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_DBG_CBS_CC                                         , RULL(0x2D030013), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_DBG_CBS_CC                                         , RULL(0x2E030013), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_DBG_CBS_CC                                         , RULL(0x2F030013), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_DBG_CBS_CC                                         , RULL(0x30030013), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_DBG_CBS_CC                                         , RULL(0x31030013), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_DBG_CBS_CC                                         , RULL(0x32030013), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_DBG_CBS_CC                                         , RULL(0x33030013), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_DBG_CBS_CC                                         , RULL(0x34030013), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_DBG_CBS_CC                                         , RULL(0x35030013), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_DBG_CBS_CC                                         , RULL(0x36030013), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_DBG_CBS_CC                                         , RULL(0x37030013), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_DBG_CBS_CC                                           , RULL(0x10030013), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_DBG_CBS_CC                                         , RULL(0x10030013), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_DBG_CBS_CC                                         , RULL(0x11030013), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_DBG_CBS_CC                                         , RULL(0x12030013), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_DBG_CBS_CC                                         , RULL(0x13030013), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_DBG_CBS_CC                                         , RULL(0x14030013), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_DBG_CBS_CC                                         , RULL(0x15030013), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_DBG_CBS_CC                                           , RULL(0x20030013), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21030013,
+REG64( EX_0_DBG_CBS_CC                                         , RULL(0x20030013), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21030013,
+REG64( EX_1_DBG_CBS_CC                                         , RULL(0x22030013), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23030013,
+REG64( EX_2_DBG_CBS_CC                                         , RULL(0x24030013), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25030013,
+REG64( EX_3_DBG_CBS_CC                                         , RULL(0x26030013), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27030013,
+REG64( EX_4_DBG_CBS_CC                                         , RULL(0x28030013), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29030013,
+REG64( EX_5_DBG_CBS_CC                                         , RULL(0x2A030013), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B030013,
+REG64( EX_6_DBG_CBS_CC                                         , RULL(0x2C030013), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D030013,
+REG64( EX_7_DBG_CBS_CC                                         , RULL(0x2E030013), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F030013,
+REG64( EX_8_DBG_CBS_CC                                         , RULL(0x30030013), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31030013,
+REG64( EX_9_DBG_CBS_CC                                         , RULL(0x32030013), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33030013,
+REG64( EX_10_DBG_CBS_CC                                        , RULL(0x34030013), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35030013,
+REG64( EX_11_DBG_CBS_CC                                        , RULL(0x36030013), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37030013,
+
+REG64( C_DBG_INST1_COND_REG_1                                  , RULL(0x200107C1), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_DBG_INST1_COND_REG_1                                , RULL(0x200107C1), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_DBG_INST1_COND_REG_1                                , RULL(0x210107C1), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_DBG_INST1_COND_REG_1                                , RULL(0x220107C1), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_DBG_INST1_COND_REG_1                                , RULL(0x230107C1), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_DBG_INST1_COND_REG_1                                , RULL(0x240107C1), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_DBG_INST1_COND_REG_1                                , RULL(0x250107C1), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_DBG_INST1_COND_REG_1                                , RULL(0x260107C1), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_DBG_INST1_COND_REG_1                                , RULL(0x270107C1), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_DBG_INST1_COND_REG_1                                , RULL(0x280107C1), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_DBG_INST1_COND_REG_1                                , RULL(0x290107C1), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_DBG_INST1_COND_REG_1                               , RULL(0x2A0107C1), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_DBG_INST1_COND_REG_1                               , RULL(0x2B0107C1), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_DBG_INST1_COND_REG_1                               , RULL(0x2C0107C1), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_DBG_INST1_COND_REG_1                               , RULL(0x2D0107C1), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_DBG_INST1_COND_REG_1                               , RULL(0x2E0107C1), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_DBG_INST1_COND_REG_1                               , RULL(0x2F0107C1), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_DBG_INST1_COND_REG_1                               , RULL(0x300107C1), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_DBG_INST1_COND_REG_1                               , RULL(0x310107C1), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_DBG_INST1_COND_REG_1                               , RULL(0x320107C1), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_DBG_INST1_COND_REG_1                               , RULL(0x330107C1), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_DBG_INST1_COND_REG_1                               , RULL(0x340107C1), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_DBG_INST1_COND_REG_1                               , RULL(0x350107C1), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_DBG_INST1_COND_REG_1                               , RULL(0x360107C1), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_DBG_INST1_COND_REG_1                               , RULL(0x370107C1), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_DBG_INST1_COND_REG_1                                 , RULL(0x100107C1), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_DBG_INST1_COND_REG_1                               , RULL(0x100107C1), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_DBG_INST1_COND_REG_1                               , RULL(0x110107C1), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_DBG_INST1_COND_REG_1                               , RULL(0x120107C1), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_DBG_INST1_COND_REG_1                               , RULL(0x130107C1), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_DBG_INST1_COND_REG_1                               , RULL(0x140107C1), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_DBG_INST1_COND_REG_1                               , RULL(0x150107C1), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_DBG_INST1_COND_REG_1                                 , RULL(0x200107C1), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210107C1,
+REG64( EX_0_DBG_INST1_COND_REG_1                               , RULL(0x200107C1), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210107C1,
+REG64( EX_1_DBG_INST1_COND_REG_1                               , RULL(0x220107C1), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230107C1,
+REG64( EX_2_DBG_INST1_COND_REG_1                               , RULL(0x240107C1), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250107C1,
+REG64( EX_3_DBG_INST1_COND_REG_1                               , RULL(0x260107C1), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270107C1,
+REG64( EX_4_DBG_INST1_COND_REG_1                               , RULL(0x280107C1), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290107C1,
+REG64( EX_5_DBG_INST1_COND_REG_1                               , RULL(0x2A0107C1), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0107C1,
+REG64( EX_6_DBG_INST1_COND_REG_1                               , RULL(0x2C0107C1), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0107C1,
+REG64( EX_7_DBG_INST1_COND_REG_1                               , RULL(0x2E0107C1), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0107C1,
+REG64( EX_8_DBG_INST1_COND_REG_1                               , RULL(0x300107C1), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310107C1,
+REG64( EX_9_DBG_INST1_COND_REG_1                               , RULL(0x320107C1), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330107C1,
+REG64( EX_10_DBG_INST1_COND_REG_1                              , RULL(0x340107C1), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350107C1,
+REG64( EX_11_DBG_INST1_COND_REG_1                              , RULL(0x360107C1), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370107C1,
+
+REG64( C_DBG_INST1_COND_REG_2                                  , RULL(0x200107C2), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_DBG_INST1_COND_REG_2                                , RULL(0x200107C2), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_DBG_INST1_COND_REG_2                                , RULL(0x210107C2), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_DBG_INST1_COND_REG_2                                , RULL(0x220107C2), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_DBG_INST1_COND_REG_2                                , RULL(0x230107C2), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_DBG_INST1_COND_REG_2                                , RULL(0x240107C2), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_DBG_INST1_COND_REG_2                                , RULL(0x250107C2), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_DBG_INST1_COND_REG_2                                , RULL(0x260107C2), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_DBG_INST1_COND_REG_2                                , RULL(0x270107C2), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_DBG_INST1_COND_REG_2                                , RULL(0x280107C2), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_DBG_INST1_COND_REG_2                                , RULL(0x290107C2), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_DBG_INST1_COND_REG_2                               , RULL(0x2A0107C2), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_DBG_INST1_COND_REG_2                               , RULL(0x2B0107C2), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_DBG_INST1_COND_REG_2                               , RULL(0x2C0107C2), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_DBG_INST1_COND_REG_2                               , RULL(0x2D0107C2), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_DBG_INST1_COND_REG_2                               , RULL(0x2E0107C2), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_DBG_INST1_COND_REG_2                               , RULL(0x2F0107C2), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_DBG_INST1_COND_REG_2                               , RULL(0x300107C2), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_DBG_INST1_COND_REG_2                               , RULL(0x310107C2), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_DBG_INST1_COND_REG_2                               , RULL(0x320107C2), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_DBG_INST1_COND_REG_2                               , RULL(0x330107C2), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_DBG_INST1_COND_REG_2                               , RULL(0x340107C2), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_DBG_INST1_COND_REG_2                               , RULL(0x350107C2), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_DBG_INST1_COND_REG_2                               , RULL(0x360107C2), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_DBG_INST1_COND_REG_2                               , RULL(0x370107C2), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_DBG_INST1_COND_REG_2                                 , RULL(0x100107C2), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_DBG_INST1_COND_REG_2                               , RULL(0x100107C2), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_DBG_INST1_COND_REG_2                               , RULL(0x110107C2), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_DBG_INST1_COND_REG_2                               , RULL(0x120107C2), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_DBG_INST1_COND_REG_2                               , RULL(0x130107C2), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_DBG_INST1_COND_REG_2                               , RULL(0x140107C2), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_DBG_INST1_COND_REG_2                               , RULL(0x150107C2), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_DBG_INST1_COND_REG_2                                 , RULL(0x200107C2), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210107C2,
+REG64( EX_0_DBG_INST1_COND_REG_2                               , RULL(0x200107C2), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210107C2,
+REG64( EX_1_DBG_INST1_COND_REG_2                               , RULL(0x220107C2), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230107C2,
+REG64( EX_2_DBG_INST1_COND_REG_2                               , RULL(0x240107C2), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250107C2,
+REG64( EX_3_DBG_INST1_COND_REG_2                               , RULL(0x260107C2), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270107C2,
+REG64( EX_4_DBG_INST1_COND_REG_2                               , RULL(0x280107C2), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290107C2,
+REG64( EX_5_DBG_INST1_COND_REG_2                               , RULL(0x2A0107C2), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0107C2,
+REG64( EX_6_DBG_INST1_COND_REG_2                               , RULL(0x2C0107C2), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0107C2,
+REG64( EX_7_DBG_INST1_COND_REG_2                               , RULL(0x2E0107C2), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0107C2,
+REG64( EX_8_DBG_INST1_COND_REG_2                               , RULL(0x300107C2), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310107C2,
+REG64( EX_9_DBG_INST1_COND_REG_2                               , RULL(0x320107C2), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330107C2,
+REG64( EX_10_DBG_INST1_COND_REG_2                              , RULL(0x340107C2), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350107C2,
+REG64( EX_11_DBG_INST1_COND_REG_2                              , RULL(0x360107C2), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370107C2,
+
+REG64( C_DBG_INST1_COND_REG_3                                  , RULL(0x200107C3), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_DBG_INST1_COND_REG_3                                , RULL(0x200107C3), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_DBG_INST1_COND_REG_3                                , RULL(0x210107C3), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_DBG_INST1_COND_REG_3                                , RULL(0x220107C3), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_DBG_INST1_COND_REG_3                                , RULL(0x230107C3), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_DBG_INST1_COND_REG_3                                , RULL(0x240107C3), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_DBG_INST1_COND_REG_3                                , RULL(0x250107C3), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_DBG_INST1_COND_REG_3                                , RULL(0x260107C3), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_DBG_INST1_COND_REG_3                                , RULL(0x270107C3), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_DBG_INST1_COND_REG_3                                , RULL(0x280107C3), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_DBG_INST1_COND_REG_3                                , RULL(0x290107C3), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_DBG_INST1_COND_REG_3                               , RULL(0x2A0107C3), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_DBG_INST1_COND_REG_3                               , RULL(0x2B0107C3), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_DBG_INST1_COND_REG_3                               , RULL(0x2C0107C3), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_DBG_INST1_COND_REG_3                               , RULL(0x2D0107C3), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_DBG_INST1_COND_REG_3                               , RULL(0x2E0107C3), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_DBG_INST1_COND_REG_3                               , RULL(0x2F0107C3), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_DBG_INST1_COND_REG_3                               , RULL(0x300107C3), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_DBG_INST1_COND_REG_3                               , RULL(0x310107C3), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_DBG_INST1_COND_REG_3                               , RULL(0x320107C3), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_DBG_INST1_COND_REG_3                               , RULL(0x330107C3), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_DBG_INST1_COND_REG_3                               , RULL(0x340107C3), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_DBG_INST1_COND_REG_3                               , RULL(0x350107C3), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_DBG_INST1_COND_REG_3                               , RULL(0x360107C3), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_DBG_INST1_COND_REG_3                               , RULL(0x370107C3), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_DBG_INST1_COND_REG_3                                 , RULL(0x100107C3), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_DBG_INST1_COND_REG_3                               , RULL(0x100107C3), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_DBG_INST1_COND_REG_3                               , RULL(0x110107C3), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_DBG_INST1_COND_REG_3                               , RULL(0x120107C3), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_DBG_INST1_COND_REG_3                               , RULL(0x130107C3), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_DBG_INST1_COND_REG_3                               , RULL(0x140107C3), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_DBG_INST1_COND_REG_3                               , RULL(0x150107C3), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_DBG_INST1_COND_REG_3                                 , RULL(0x200107C3), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210107C3,
+REG64( EX_0_DBG_INST1_COND_REG_3                               , RULL(0x200107C3), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210107C3,
+REG64( EX_1_DBG_INST1_COND_REG_3                               , RULL(0x220107C3), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230107C3,
+REG64( EX_2_DBG_INST1_COND_REG_3                               , RULL(0x240107C3), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250107C3,
+REG64( EX_3_DBG_INST1_COND_REG_3                               , RULL(0x260107C3), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270107C3,
+REG64( EX_4_DBG_INST1_COND_REG_3                               , RULL(0x280107C3), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290107C3,
+REG64( EX_5_DBG_INST1_COND_REG_3                               , RULL(0x2A0107C3), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0107C3,
+REG64( EX_6_DBG_INST1_COND_REG_3                               , RULL(0x2C0107C3), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0107C3,
+REG64( EX_7_DBG_INST1_COND_REG_3                               , RULL(0x2E0107C3), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0107C3,
+REG64( EX_8_DBG_INST1_COND_REG_3                               , RULL(0x300107C3), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310107C3,
+REG64( EX_9_DBG_INST1_COND_REG_3                               , RULL(0x320107C3), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330107C3,
+REG64( EX_10_DBG_INST1_COND_REG_3                              , RULL(0x340107C3), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350107C3,
+REG64( EX_11_DBG_INST1_COND_REG_3                              , RULL(0x360107C3), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370107C3,
+
+REG64( C_DBG_INST2_COND_REG_1                                  , RULL(0x200107C4), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_DBG_INST2_COND_REG_1                                , RULL(0x200107C4), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_DBG_INST2_COND_REG_1                                , RULL(0x210107C4), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_DBG_INST2_COND_REG_1                                , RULL(0x220107C4), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_DBG_INST2_COND_REG_1                                , RULL(0x230107C4), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_DBG_INST2_COND_REG_1                                , RULL(0x240107C4), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_DBG_INST2_COND_REG_1                                , RULL(0x250107C4), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_DBG_INST2_COND_REG_1                                , RULL(0x260107C4), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_DBG_INST2_COND_REG_1                                , RULL(0x270107C4), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_DBG_INST2_COND_REG_1                                , RULL(0x280107C4), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_DBG_INST2_COND_REG_1                                , RULL(0x290107C4), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_DBG_INST2_COND_REG_1                               , RULL(0x2A0107C4), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_DBG_INST2_COND_REG_1                               , RULL(0x2B0107C4), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_DBG_INST2_COND_REG_1                               , RULL(0x2C0107C4), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_DBG_INST2_COND_REG_1                               , RULL(0x2D0107C4), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_DBG_INST2_COND_REG_1                               , RULL(0x2E0107C4), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_DBG_INST2_COND_REG_1                               , RULL(0x2F0107C4), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_DBG_INST2_COND_REG_1                               , RULL(0x300107C4), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_DBG_INST2_COND_REG_1                               , RULL(0x310107C4), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_DBG_INST2_COND_REG_1                               , RULL(0x320107C4), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_DBG_INST2_COND_REG_1                               , RULL(0x330107C4), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_DBG_INST2_COND_REG_1                               , RULL(0x340107C4), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_DBG_INST2_COND_REG_1                               , RULL(0x350107C4), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_DBG_INST2_COND_REG_1                               , RULL(0x360107C4), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_DBG_INST2_COND_REG_1                               , RULL(0x370107C4), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_DBG_INST2_COND_REG_1                                 , RULL(0x100107C4), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_DBG_INST2_COND_REG_1                               , RULL(0x100107C4), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_DBG_INST2_COND_REG_1                               , RULL(0x110107C4), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_DBG_INST2_COND_REG_1                               , RULL(0x120107C4), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_DBG_INST2_COND_REG_1                               , RULL(0x130107C4), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_DBG_INST2_COND_REG_1                               , RULL(0x140107C4), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_DBG_INST2_COND_REG_1                               , RULL(0x150107C4), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_DBG_INST2_COND_REG_1                                 , RULL(0x200107C4), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210107C4,
+REG64( EX_0_DBG_INST2_COND_REG_1                               , RULL(0x200107C4), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210107C4,
+REG64( EX_1_DBG_INST2_COND_REG_1                               , RULL(0x220107C4), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230107C4,
+REG64( EX_2_DBG_INST2_COND_REG_1                               , RULL(0x240107C4), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250107C4,
+REG64( EX_3_DBG_INST2_COND_REG_1                               , RULL(0x260107C4), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270107C4,
+REG64( EX_4_DBG_INST2_COND_REG_1                               , RULL(0x280107C4), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290107C4,
+REG64( EX_5_DBG_INST2_COND_REG_1                               , RULL(0x2A0107C4), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0107C4,
+REG64( EX_6_DBG_INST2_COND_REG_1                               , RULL(0x2C0107C4), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0107C4,
+REG64( EX_7_DBG_INST2_COND_REG_1                               , RULL(0x2E0107C4), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0107C4,
+REG64( EX_8_DBG_INST2_COND_REG_1                               , RULL(0x300107C4), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310107C4,
+REG64( EX_9_DBG_INST2_COND_REG_1                               , RULL(0x320107C4), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330107C4,
+REG64( EX_10_DBG_INST2_COND_REG_1                              , RULL(0x340107C4), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350107C4,
+REG64( EX_11_DBG_INST2_COND_REG_1                              , RULL(0x360107C4), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370107C4,
+
+REG64( C_DBG_INST2_COND_REG_2                                  , RULL(0x200107C5), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_DBG_INST2_COND_REG_2                                , RULL(0x200107C5), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_DBG_INST2_COND_REG_2                                , RULL(0x210107C5), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_DBG_INST2_COND_REG_2                                , RULL(0x220107C5), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_DBG_INST2_COND_REG_2                                , RULL(0x230107C5), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_DBG_INST2_COND_REG_2                                , RULL(0x240107C5), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_DBG_INST2_COND_REG_2                                , RULL(0x250107C5), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_DBG_INST2_COND_REG_2                                , RULL(0x260107C5), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_DBG_INST2_COND_REG_2                                , RULL(0x270107C5), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_DBG_INST2_COND_REG_2                                , RULL(0x280107C5), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_DBG_INST2_COND_REG_2                                , RULL(0x290107C5), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_DBG_INST2_COND_REG_2                               , RULL(0x2A0107C5), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_DBG_INST2_COND_REG_2                               , RULL(0x2B0107C5), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_DBG_INST2_COND_REG_2                               , RULL(0x2C0107C5), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_DBG_INST2_COND_REG_2                               , RULL(0x2D0107C5), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_DBG_INST2_COND_REG_2                               , RULL(0x2E0107C5), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_DBG_INST2_COND_REG_2                               , RULL(0x2F0107C5), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_DBG_INST2_COND_REG_2                               , RULL(0x300107C5), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_DBG_INST2_COND_REG_2                               , RULL(0x310107C5), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_DBG_INST2_COND_REG_2                               , RULL(0x320107C5), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_DBG_INST2_COND_REG_2                               , RULL(0x330107C5), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_DBG_INST2_COND_REG_2                               , RULL(0x340107C5), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_DBG_INST2_COND_REG_2                               , RULL(0x350107C5), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_DBG_INST2_COND_REG_2                               , RULL(0x360107C5), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_DBG_INST2_COND_REG_2                               , RULL(0x370107C5), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_DBG_INST2_COND_REG_2                                 , RULL(0x100107C5), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_DBG_INST2_COND_REG_2                               , RULL(0x100107C5), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_DBG_INST2_COND_REG_2                               , RULL(0x110107C5), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_DBG_INST2_COND_REG_2                               , RULL(0x120107C5), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_DBG_INST2_COND_REG_2                               , RULL(0x130107C5), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_DBG_INST2_COND_REG_2                               , RULL(0x140107C5), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_DBG_INST2_COND_REG_2                               , RULL(0x150107C5), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_DBG_INST2_COND_REG_2                                 , RULL(0x200107C5), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210107C5,
+REG64( EX_0_DBG_INST2_COND_REG_2                               , RULL(0x200107C5), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210107C5,
+REG64( EX_1_DBG_INST2_COND_REG_2                               , RULL(0x220107C5), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230107C5,
+REG64( EX_2_DBG_INST2_COND_REG_2                               , RULL(0x240107C5), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250107C5,
+REG64( EX_3_DBG_INST2_COND_REG_2                               , RULL(0x260107C5), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270107C5,
+REG64( EX_4_DBG_INST2_COND_REG_2                               , RULL(0x280107C5), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290107C5,
+REG64( EX_5_DBG_INST2_COND_REG_2                               , RULL(0x2A0107C5), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0107C5,
+REG64( EX_6_DBG_INST2_COND_REG_2                               , RULL(0x2C0107C5), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0107C5,
+REG64( EX_7_DBG_INST2_COND_REG_2                               , RULL(0x2E0107C5), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0107C5,
+REG64( EX_8_DBG_INST2_COND_REG_2                               , RULL(0x300107C5), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310107C5,
+REG64( EX_9_DBG_INST2_COND_REG_2                               , RULL(0x320107C5), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330107C5,
+REG64( EX_10_DBG_INST2_COND_REG_2                              , RULL(0x340107C5), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350107C5,
+REG64( EX_11_DBG_INST2_COND_REG_2                              , RULL(0x360107C5), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370107C5,
+
+REG64( C_DBG_INST2_COND_REG_3                                  , RULL(0x200107C6), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_DBG_INST2_COND_REG_3                                , RULL(0x200107C6), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_DBG_INST2_COND_REG_3                                , RULL(0x210107C6), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_DBG_INST2_COND_REG_3                                , RULL(0x220107C6), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_DBG_INST2_COND_REG_3                                , RULL(0x230107C6), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_DBG_INST2_COND_REG_3                                , RULL(0x240107C6), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_DBG_INST2_COND_REG_3                                , RULL(0x250107C6), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_DBG_INST2_COND_REG_3                                , RULL(0x260107C6), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_DBG_INST2_COND_REG_3                                , RULL(0x270107C6), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_DBG_INST2_COND_REG_3                                , RULL(0x280107C6), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_DBG_INST2_COND_REG_3                                , RULL(0x290107C6), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_DBG_INST2_COND_REG_3                               , RULL(0x2A0107C6), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_DBG_INST2_COND_REG_3                               , RULL(0x2B0107C6), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_DBG_INST2_COND_REG_3                               , RULL(0x2C0107C6), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_DBG_INST2_COND_REG_3                               , RULL(0x2D0107C6), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_DBG_INST2_COND_REG_3                               , RULL(0x2E0107C6), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_DBG_INST2_COND_REG_3                               , RULL(0x2F0107C6), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_DBG_INST2_COND_REG_3                               , RULL(0x300107C6), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_DBG_INST2_COND_REG_3                               , RULL(0x310107C6), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_DBG_INST2_COND_REG_3                               , RULL(0x320107C6), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_DBG_INST2_COND_REG_3                               , RULL(0x330107C6), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_DBG_INST2_COND_REG_3                               , RULL(0x340107C6), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_DBG_INST2_COND_REG_3                               , RULL(0x350107C6), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_DBG_INST2_COND_REG_3                               , RULL(0x360107C6), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_DBG_INST2_COND_REG_3                               , RULL(0x370107C6), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_DBG_INST2_COND_REG_3                                 , RULL(0x100107C6), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_DBG_INST2_COND_REG_3                               , RULL(0x100107C6), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_DBG_INST2_COND_REG_3                               , RULL(0x110107C6), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_DBG_INST2_COND_REG_3                               , RULL(0x120107C6), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_DBG_INST2_COND_REG_3                               , RULL(0x130107C6), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_DBG_INST2_COND_REG_3                               , RULL(0x140107C6), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_DBG_INST2_COND_REG_3                               , RULL(0x150107C6), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_DBG_INST2_COND_REG_3                                 , RULL(0x200107C6), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210107C6,
+REG64( EX_0_DBG_INST2_COND_REG_3                               , RULL(0x200107C6), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210107C6,
+REG64( EX_1_DBG_INST2_COND_REG_3                               , RULL(0x220107C6), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230107C6,
+REG64( EX_2_DBG_INST2_COND_REG_3                               , RULL(0x240107C6), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250107C6,
+REG64( EX_3_DBG_INST2_COND_REG_3                               , RULL(0x260107C6), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270107C6,
+REG64( EX_4_DBG_INST2_COND_REG_3                               , RULL(0x280107C6), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290107C6,
+REG64( EX_5_DBG_INST2_COND_REG_3                               , RULL(0x2A0107C6), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0107C6,
+REG64( EX_6_DBG_INST2_COND_REG_3                               , RULL(0x2C0107C6), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0107C6,
+REG64( EX_7_DBG_INST2_COND_REG_3                               , RULL(0x2E0107C6), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0107C6,
+REG64( EX_8_DBG_INST2_COND_REG_3                               , RULL(0x300107C6), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310107C6,
+REG64( EX_9_DBG_INST2_COND_REG_3                               , RULL(0x320107C6), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330107C6,
+REG64( EX_10_DBG_INST2_COND_REG_3                              , RULL(0x340107C6), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350107C6,
+REG64( EX_11_DBG_INST2_COND_REG_3                              , RULL(0x360107C6), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370107C6,
+
+REG64( C_DBG_MODE_REG                                          , RULL(0x200107C0), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_DBG_MODE_REG                                        , RULL(0x200107C0), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_DBG_MODE_REG                                        , RULL(0x210107C0), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_DBG_MODE_REG                                        , RULL(0x220107C0), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_DBG_MODE_REG                                        , RULL(0x230107C0), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_DBG_MODE_REG                                        , RULL(0x240107C0), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_DBG_MODE_REG                                        , RULL(0x250107C0), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_DBG_MODE_REG                                        , RULL(0x260107C0), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_DBG_MODE_REG                                        , RULL(0x270107C0), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_DBG_MODE_REG                                        , RULL(0x280107C0), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_DBG_MODE_REG                                        , RULL(0x290107C0), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_DBG_MODE_REG                                       , RULL(0x2A0107C0), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_DBG_MODE_REG                                       , RULL(0x2B0107C0), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_DBG_MODE_REG                                       , RULL(0x2C0107C0), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_DBG_MODE_REG                                       , RULL(0x2D0107C0), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_DBG_MODE_REG                                       , RULL(0x2E0107C0), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_DBG_MODE_REG                                       , RULL(0x2F0107C0), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_DBG_MODE_REG                                       , RULL(0x300107C0), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_DBG_MODE_REG                                       , RULL(0x310107C0), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_DBG_MODE_REG                                       , RULL(0x320107C0), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_DBG_MODE_REG                                       , RULL(0x330107C0), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_DBG_MODE_REG                                       , RULL(0x340107C0), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_DBG_MODE_REG                                       , RULL(0x350107C0), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_DBG_MODE_REG                                       , RULL(0x360107C0), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_DBG_MODE_REG                                       , RULL(0x370107C0), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_DBG_MODE_REG                                         , RULL(0x100107C0), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_DBG_MODE_REG                                       , RULL(0x100107C0), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_DBG_MODE_REG                                       , RULL(0x110107C0), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_DBG_MODE_REG                                       , RULL(0x120107C0), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_DBG_MODE_REG                                       , RULL(0x130107C0), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_DBG_MODE_REG                                       , RULL(0x140107C0), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_DBG_MODE_REG                                       , RULL(0x150107C0), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_DBG_MODE_REG                                         , RULL(0x200107C0), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210107C0,
+REG64( EX_0_DBG_MODE_REG                                       , RULL(0x200107C0), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210107C0,
+REG64( EX_1_DBG_MODE_REG                                       , RULL(0x220107C0), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230107C0,
+REG64( EX_2_DBG_MODE_REG                                       , RULL(0x240107C0), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250107C0,
+REG64( EX_3_DBG_MODE_REG                                       , RULL(0x260107C0), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270107C0,
+REG64( EX_4_DBG_MODE_REG                                       , RULL(0x280107C0), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290107C0,
+REG64( EX_5_DBG_MODE_REG                                       , RULL(0x2A0107C0), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0107C0,
+REG64( EX_6_DBG_MODE_REG                                       , RULL(0x2C0107C0), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0107C0,
+REG64( EX_7_DBG_MODE_REG                                       , RULL(0x2E0107C0), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0107C0,
+REG64( EX_8_DBG_MODE_REG                                       , RULL(0x300107C0), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310107C0,
+REG64( EX_9_DBG_MODE_REG                                       , RULL(0x320107C0), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330107C0,
+REG64( EX_10_DBG_MODE_REG                                      , RULL(0x340107C0), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350107C0,
+REG64( EX_11_DBG_MODE_REG                                      , RULL(0x360107C0), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370107C0,
+
+REG64( C_DBG_TRACE_MODE_REG_2                                  , RULL(0x200107CF), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_DBG_TRACE_MODE_REG_2                                , RULL(0x200107CF), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_DBG_TRACE_MODE_REG_2                                , RULL(0x210107CF), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_DBG_TRACE_MODE_REG_2                                , RULL(0x220107CF), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_DBG_TRACE_MODE_REG_2                                , RULL(0x230107CF), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_DBG_TRACE_MODE_REG_2                                , RULL(0x240107CF), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_DBG_TRACE_MODE_REG_2                                , RULL(0x250107CF), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_DBG_TRACE_MODE_REG_2                                , RULL(0x260107CF), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_DBG_TRACE_MODE_REG_2                                , RULL(0x270107CF), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_DBG_TRACE_MODE_REG_2                                , RULL(0x280107CF), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_DBG_TRACE_MODE_REG_2                                , RULL(0x290107CF), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_DBG_TRACE_MODE_REG_2                               , RULL(0x2A0107CF), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_DBG_TRACE_MODE_REG_2                               , RULL(0x2B0107CF), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_DBG_TRACE_MODE_REG_2                               , RULL(0x2C0107CF), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_DBG_TRACE_MODE_REG_2                               , RULL(0x2D0107CF), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_DBG_TRACE_MODE_REG_2                               , RULL(0x2E0107CF), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_DBG_TRACE_MODE_REG_2                               , RULL(0x2F0107CF), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_DBG_TRACE_MODE_REG_2                               , RULL(0x300107CF), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_DBG_TRACE_MODE_REG_2                               , RULL(0x310107CF), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_DBG_TRACE_MODE_REG_2                               , RULL(0x320107CF), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_DBG_TRACE_MODE_REG_2                               , RULL(0x330107CF), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_DBG_TRACE_MODE_REG_2                               , RULL(0x340107CF), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_DBG_TRACE_MODE_REG_2                               , RULL(0x350107CF), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_DBG_TRACE_MODE_REG_2                               , RULL(0x360107CF), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_DBG_TRACE_MODE_REG_2                               , RULL(0x370107CF), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_DBG_TRACE_MODE_REG_2                                 , RULL(0x100107CF), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_DBG_TRACE_MODE_REG_2                               , RULL(0x100107CF), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_DBG_TRACE_MODE_REG_2                               , RULL(0x110107CF), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_DBG_TRACE_MODE_REG_2                               , RULL(0x120107CF), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_DBG_TRACE_MODE_REG_2                               , RULL(0x130107CF), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_DBG_TRACE_MODE_REG_2                               , RULL(0x140107CF), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_DBG_TRACE_MODE_REG_2                               , RULL(0x150107CF), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_DBG_TRACE_MODE_REG_2                                 , RULL(0x200107CF), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210107CF,
+REG64( EX_0_DBG_TRACE_MODE_REG_2                               , RULL(0x200107CF), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210107CF,
+REG64( EX_1_DBG_TRACE_MODE_REG_2                               , RULL(0x220107CF), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230107CF,
+REG64( EX_2_DBG_TRACE_MODE_REG_2                               , RULL(0x240107CF), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250107CF,
+REG64( EX_3_DBG_TRACE_MODE_REG_2                               , RULL(0x260107CF), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270107CF,
+REG64( EX_4_DBG_TRACE_MODE_REG_2                               , RULL(0x280107CF), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290107CF,
+REG64( EX_5_DBG_TRACE_MODE_REG_2                               , RULL(0x2A0107CF), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0107CF,
+REG64( EX_6_DBG_TRACE_MODE_REG_2                               , RULL(0x2C0107CF), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0107CF,
+REG64( EX_7_DBG_TRACE_MODE_REG_2                               , RULL(0x2E0107CF), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0107CF,
+REG64( EX_8_DBG_TRACE_MODE_REG_2                               , RULL(0x300107CF), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310107CF,
+REG64( EX_9_DBG_TRACE_MODE_REG_2                               , RULL(0x320107CF), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330107CF,
+REG64( EX_10_DBG_TRACE_MODE_REG_2                              , RULL(0x340107CF), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350107CF,
+REG64( EX_11_DBG_TRACE_MODE_REG_2                              , RULL(0x360107CF), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370107CF,
+
+REG64( C_DBG_TRACE_REG_0                                       , RULL(0x200107CD), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_DBG_TRACE_REG_0                                     , RULL(0x200107CD), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_DBG_TRACE_REG_0                                     , RULL(0x210107CD), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_DBG_TRACE_REG_0                                     , RULL(0x220107CD), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_DBG_TRACE_REG_0                                     , RULL(0x230107CD), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_DBG_TRACE_REG_0                                     , RULL(0x240107CD), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_DBG_TRACE_REG_0                                     , RULL(0x250107CD), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_DBG_TRACE_REG_0                                     , RULL(0x260107CD), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_DBG_TRACE_REG_0                                     , RULL(0x270107CD), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_DBG_TRACE_REG_0                                     , RULL(0x280107CD), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_DBG_TRACE_REG_0                                     , RULL(0x290107CD), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_DBG_TRACE_REG_0                                    , RULL(0x2A0107CD), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_DBG_TRACE_REG_0                                    , RULL(0x2B0107CD), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_DBG_TRACE_REG_0                                    , RULL(0x2C0107CD), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_DBG_TRACE_REG_0                                    , RULL(0x2D0107CD), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_DBG_TRACE_REG_0                                    , RULL(0x2E0107CD), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_DBG_TRACE_REG_0                                    , RULL(0x2F0107CD), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_DBG_TRACE_REG_0                                    , RULL(0x300107CD), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_DBG_TRACE_REG_0                                    , RULL(0x310107CD), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_DBG_TRACE_REG_0                                    , RULL(0x320107CD), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_DBG_TRACE_REG_0                                    , RULL(0x330107CD), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_DBG_TRACE_REG_0                                    , RULL(0x340107CD), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_DBG_TRACE_REG_0                                    , RULL(0x350107CD), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_DBG_TRACE_REG_0                                    , RULL(0x360107CD), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_DBG_TRACE_REG_0                                    , RULL(0x370107CD), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_DBG_TRACE_REG_0                                      , RULL(0x100107CD), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_DBG_TRACE_REG_0                                    , RULL(0x100107CD), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_DBG_TRACE_REG_0                                    , RULL(0x110107CD), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_DBG_TRACE_REG_0                                    , RULL(0x120107CD), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_DBG_TRACE_REG_0                                    , RULL(0x130107CD), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_DBG_TRACE_REG_0                                    , RULL(0x140107CD), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_DBG_TRACE_REG_0                                    , RULL(0x150107CD), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_DBG_TRACE_REG_0                                      , RULL(0x200107CD), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210107CD,
+REG64( EX_0_DBG_TRACE_REG_0                                    , RULL(0x200107CD), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210107CD,
+REG64( EX_1_DBG_TRACE_REG_0                                    , RULL(0x220107CD), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230107CD,
+REG64( EX_2_DBG_TRACE_REG_0                                    , RULL(0x240107CD), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250107CD,
+REG64( EX_3_DBG_TRACE_REG_0                                    , RULL(0x260107CD), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270107CD,
+REG64( EX_4_DBG_TRACE_REG_0                                    , RULL(0x280107CD), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290107CD,
+REG64( EX_5_DBG_TRACE_REG_0                                    , RULL(0x2A0107CD), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0107CD,
+REG64( EX_6_DBG_TRACE_REG_0                                    , RULL(0x2C0107CD), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0107CD,
+REG64( EX_7_DBG_TRACE_REG_0                                    , RULL(0x2E0107CD), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0107CD,
+REG64( EX_8_DBG_TRACE_REG_0                                    , RULL(0x300107CD), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310107CD,
+REG64( EX_9_DBG_TRACE_REG_0                                    , RULL(0x320107CD), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330107CD,
+REG64( EX_10_DBG_TRACE_REG_0                                   , RULL(0x340107CD), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350107CD,
+REG64( EX_11_DBG_TRACE_REG_0                                   , RULL(0x360107CD), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370107CD,
+
+REG64( C_DBG_TRACE_REG_1                                       , RULL(0x200107CE), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_DBG_TRACE_REG_1                                     , RULL(0x200107CE), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_DBG_TRACE_REG_1                                     , RULL(0x210107CE), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_DBG_TRACE_REG_1                                     , RULL(0x220107CE), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_DBG_TRACE_REG_1                                     , RULL(0x230107CE), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_DBG_TRACE_REG_1                                     , RULL(0x240107CE), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_DBG_TRACE_REG_1                                     , RULL(0x250107CE), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_DBG_TRACE_REG_1                                     , RULL(0x260107CE), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_DBG_TRACE_REG_1                                     , RULL(0x270107CE), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_DBG_TRACE_REG_1                                     , RULL(0x280107CE), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_DBG_TRACE_REG_1                                     , RULL(0x290107CE), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_DBG_TRACE_REG_1                                    , RULL(0x2A0107CE), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_DBG_TRACE_REG_1                                    , RULL(0x2B0107CE), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_DBG_TRACE_REG_1                                    , RULL(0x2C0107CE), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_DBG_TRACE_REG_1                                    , RULL(0x2D0107CE), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_DBG_TRACE_REG_1                                    , RULL(0x2E0107CE), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_DBG_TRACE_REG_1                                    , RULL(0x2F0107CE), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_DBG_TRACE_REG_1                                    , RULL(0x300107CE), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_DBG_TRACE_REG_1                                    , RULL(0x310107CE), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_DBG_TRACE_REG_1                                    , RULL(0x320107CE), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_DBG_TRACE_REG_1                                    , RULL(0x330107CE), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_DBG_TRACE_REG_1                                    , RULL(0x340107CE), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_DBG_TRACE_REG_1                                    , RULL(0x350107CE), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_DBG_TRACE_REG_1                                    , RULL(0x360107CE), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_DBG_TRACE_REG_1                                    , RULL(0x370107CE), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_DBG_TRACE_REG_1                                      , RULL(0x100107CE), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_DBG_TRACE_REG_1                                    , RULL(0x100107CE), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_DBG_TRACE_REG_1                                    , RULL(0x110107CE), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_DBG_TRACE_REG_1                                    , RULL(0x120107CE), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_DBG_TRACE_REG_1                                    , RULL(0x130107CE), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_DBG_TRACE_REG_1                                    , RULL(0x140107CE), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_DBG_TRACE_REG_1                                    , RULL(0x150107CE), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_DBG_TRACE_REG_1                                      , RULL(0x200107CE), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210107CE,
+REG64( EX_0_DBG_TRACE_REG_1                                    , RULL(0x200107CE), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210107CE,
+REG64( EX_1_DBG_TRACE_REG_1                                    , RULL(0x220107CE), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230107CE,
+REG64( EX_2_DBG_TRACE_REG_1                                    , RULL(0x240107CE), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250107CE,
+REG64( EX_3_DBG_TRACE_REG_1                                    , RULL(0x260107CE), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270107CE,
+REG64( EX_4_DBG_TRACE_REG_1                                    , RULL(0x280107CE), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290107CE,
+REG64( EX_5_DBG_TRACE_REG_1                                    , RULL(0x2A0107CE), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0107CE,
+REG64( EX_6_DBG_TRACE_REG_1                                    , RULL(0x2C0107CE), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0107CE,
+REG64( EX_7_DBG_TRACE_REG_1                                    , RULL(0x2E0107CE), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0107CE,
+REG64( EX_8_DBG_TRACE_REG_1                                    , RULL(0x300107CE), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310107CE,
+REG64( EX_9_DBG_TRACE_REG_1                                    , RULL(0x320107CE), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330107CE,
+REG64( EX_10_DBG_TRACE_REG_1                                   , RULL(0x340107CE), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350107CE,
+REG64( EX_11_DBG_TRACE_REG_1                                   , RULL(0x360107CE), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370107CE,
+
+REG64( C_DEBUG_TRACE_CONTROL                                   , RULL(0x200107D0), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_DEBUG_TRACE_CONTROL                                 , RULL(0x200107D0), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_DEBUG_TRACE_CONTROL                                 , RULL(0x210107D0), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_DEBUG_TRACE_CONTROL                                 , RULL(0x220107D0), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_DEBUG_TRACE_CONTROL                                 , RULL(0x230107D0), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_DEBUG_TRACE_CONTROL                                 , RULL(0x240107D0), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_DEBUG_TRACE_CONTROL                                 , RULL(0x250107D0), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_DEBUG_TRACE_CONTROL                                 , RULL(0x260107D0), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_DEBUG_TRACE_CONTROL                                 , RULL(0x270107D0), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_DEBUG_TRACE_CONTROL                                 , RULL(0x280107D0), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_DEBUG_TRACE_CONTROL                                 , RULL(0x290107D0), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_DEBUG_TRACE_CONTROL                                , RULL(0x2A0107D0), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_DEBUG_TRACE_CONTROL                                , RULL(0x2B0107D0), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_DEBUG_TRACE_CONTROL                                , RULL(0x2C0107D0), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_DEBUG_TRACE_CONTROL                                , RULL(0x2D0107D0), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_DEBUG_TRACE_CONTROL                                , RULL(0x2E0107D0), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_DEBUG_TRACE_CONTROL                                , RULL(0x2F0107D0), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_DEBUG_TRACE_CONTROL                                , RULL(0x300107D0), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_DEBUG_TRACE_CONTROL                                , RULL(0x310107D0), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_DEBUG_TRACE_CONTROL                                , RULL(0x320107D0), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_DEBUG_TRACE_CONTROL                                , RULL(0x330107D0), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_DEBUG_TRACE_CONTROL                                , RULL(0x340107D0), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_DEBUG_TRACE_CONTROL                                , RULL(0x350107D0), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_DEBUG_TRACE_CONTROL                                , RULL(0x360107D0), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_DEBUG_TRACE_CONTROL                                , RULL(0x370107D0), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_DEBUG_TRACE_CONTROL                                  , RULL(0x100107D0), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_DEBUG_TRACE_CONTROL                                , RULL(0x100107D0), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_DEBUG_TRACE_CONTROL                                , RULL(0x110107D0), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_DEBUG_TRACE_CONTROL                                , RULL(0x120107D0), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_DEBUG_TRACE_CONTROL                                , RULL(0x130107D0), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_DEBUG_TRACE_CONTROL                                , RULL(0x140107D0), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_DEBUG_TRACE_CONTROL                                , RULL(0x150107D0), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_DEBUG_TRACE_CONTROL                                  , RULL(0x200107D0), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210107D0,
+REG64( EX_0_DEBUG_TRACE_CONTROL                                , RULL(0x200107D0), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210107D0,
+REG64( EX_1_DEBUG_TRACE_CONTROL                                , RULL(0x220107D0), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230107D0,
+REG64( EX_2_DEBUG_TRACE_CONTROL                                , RULL(0x240107D0), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250107D0,
+REG64( EX_3_DEBUG_TRACE_CONTROL                                , RULL(0x260107D0), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270107D0,
+REG64( EX_4_DEBUG_TRACE_CONTROL                                , RULL(0x280107D0), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290107D0,
+REG64( EX_5_DEBUG_TRACE_CONTROL                                , RULL(0x2A0107D0), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0107D0,
+REG64( EX_6_DEBUG_TRACE_CONTROL                                , RULL(0x2C0107D0), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0107D0,
+REG64( EX_7_DEBUG_TRACE_CONTROL                                , RULL(0x2E0107D0), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0107D0,
+REG64( EX_8_DEBUG_TRACE_CONTROL                                , RULL(0x300107D0), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310107D0,
+REG64( EX_9_DEBUG_TRACE_CONTROL                                , RULL(0x320107D0), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330107D0,
+REG64( EX_10_DEBUG_TRACE_CONTROL                               , RULL(0x340107D0), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350107D0,
+REG64( EX_11_DEBUG_TRACE_CONTROL                               , RULL(0x360107D0), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370107D0,
+
+REG64( C_DIRECT_CONTROLS                                       , RULL(0x20010A9C), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_DIRECT_CONTROLS                                     , RULL(0x20010A9C), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_DIRECT_CONTROLS                                     , RULL(0x21010A9C), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_DIRECT_CONTROLS                                     , RULL(0x22010A9C), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_DIRECT_CONTROLS                                     , RULL(0x23010A9C), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_DIRECT_CONTROLS                                     , RULL(0x24010A9C), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_DIRECT_CONTROLS                                     , RULL(0x25010A9C), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_DIRECT_CONTROLS                                     , RULL(0x26010A9C), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_DIRECT_CONTROLS                                     , RULL(0x27010A9C), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_DIRECT_CONTROLS                                     , RULL(0x28010A9C), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_DIRECT_CONTROLS                                     , RULL(0x29010A9C), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_DIRECT_CONTROLS                                    , RULL(0x2A010A9C), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_DIRECT_CONTROLS                                    , RULL(0x2B010A9C), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_DIRECT_CONTROLS                                    , RULL(0x2C010A9C), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_DIRECT_CONTROLS                                    , RULL(0x2D010A9C), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_DIRECT_CONTROLS                                    , RULL(0x2E010A9C), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_DIRECT_CONTROLS                                    , RULL(0x2F010A9C), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_DIRECT_CONTROLS                                    , RULL(0x30010A9C), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_DIRECT_CONTROLS                                    , RULL(0x31010A9C), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_DIRECT_CONTROLS                                    , RULL(0x32010A9C), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_DIRECT_CONTROLS                                    , RULL(0x33010A9C), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_DIRECT_CONTROLS                                    , RULL(0x34010A9C), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_DIRECT_CONTROLS                                    , RULL(0x35010A9C), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_DIRECT_CONTROLS                                    , RULL(0x36010A9C), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_DIRECT_CONTROLS                                    , RULL(0x37010A9C), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_DIRECT_CONTROLS                                 , RULL(0x21010A9C), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 20010A9C,
+REG64( EX_10_L2_DIRECT_CONTROLS                                , RULL(0x35010A9C), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 34010A9C,
+REG64( EX_11_L2_DIRECT_CONTROLS                                , RULL(0x37010A9C), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 36010A9C,
+REG64( EX_1_L2_DIRECT_CONTROLS                                 , RULL(0x23010A9C), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 22010A9C,
+REG64( EX_2_L2_DIRECT_CONTROLS                                 , RULL(0x25010A9C), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 24010A9C,
+REG64( EX_3_L2_DIRECT_CONTROLS                                 , RULL(0x27010A9C), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 26010A9C,
+REG64( EX_4_L2_DIRECT_CONTROLS                                 , RULL(0x29010A9C), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 28010A9C,
+REG64( EX_5_L2_DIRECT_CONTROLS                                 , RULL(0x2B010A9C), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2A010A9C,
+REG64( EX_6_L2_DIRECT_CONTROLS                                 , RULL(0x2D010A9C), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2C010A9C,
+REG64( EX_7_L2_DIRECT_CONTROLS                                 , RULL(0x2F010A9C), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2E010A9C,
+REG64( EX_8_L2_DIRECT_CONTROLS                                 , RULL(0x31010A9C), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 30010A9C,
+REG64( EX_9_L2_DIRECT_CONTROLS                                 , RULL(0x33010A9C), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 32010A9C,
+REG64( EX_L2_DIRECT_CONTROLS                                   , RULL(0x21010A9C), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 20010A9C,
+
+REG64( EQ_DRAM_REF_REG                                         , RULL(0x1001180F), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C0F,
+REG64( EQ_0_DRAM_REF_REG                                       , RULL(0x1001180F), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C0F,
+REG64( EQ_1_DRAM_REF_REG                                       , RULL(0x1101180F), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C0F,
+REG64( EQ_2_DRAM_REF_REG                                       , RULL(0x1201180F), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C0F,
+REG64( EQ_3_DRAM_REF_REG                                       , RULL(0x1301180F), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C0F,
+REG64( EQ_4_DRAM_REF_REG                                       , RULL(0x1401180F), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C0F,
+REG64( EQ_5_DRAM_REF_REG                                       , RULL(0x1501180F), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C0F,
+REG64( EX_DRAM_REF_REG                                         , RULL(0x1001180F), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_DRAM_REF_REG                                       , RULL(0x1001180F), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_DRAM_REF_REG                                       , RULL(0x10011C0F), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_DRAM_REF_REG                                       , RULL(0x1101180F), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_DRAM_REF_REG                                       , RULL(0x11011C0F), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_DRAM_REF_REG                                       , RULL(0x1201180F), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_DRAM_REF_REG                                       , RULL(0x12011C0F), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_DRAM_REF_REG                                       , RULL(0x1301180F), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_DRAM_REF_REG                                       , RULL(0x13011C0F), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_DRAM_REF_REG                                       , RULL(0x1401180F), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_DRAM_REF_REG                                       , RULL(0x14011C0F), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_DRAM_REF_REG                                      , RULL(0x1501180F), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_DRAM_REF_REG                                      , RULL(0x15011C0F), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( C_DTS_RESULT0                                           , RULL(0x20050000), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_DTS_RESULT0                                         , RULL(0x20050000), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_DTS_RESULT0                                         , RULL(0x21050000), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_DTS_RESULT0                                         , RULL(0x22050000), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_DTS_RESULT0                                         , RULL(0x23050000), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_DTS_RESULT0                                         , RULL(0x24050000), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_DTS_RESULT0                                         , RULL(0x25050000), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_DTS_RESULT0                                         , RULL(0x26050000), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_DTS_RESULT0                                         , RULL(0x27050000), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_DTS_RESULT0                                         , RULL(0x28050000), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_DTS_RESULT0                                         , RULL(0x29050000), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_DTS_RESULT0                                        , RULL(0x2A050000), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_DTS_RESULT0                                        , RULL(0x2B050000), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_DTS_RESULT0                                        , RULL(0x2C050000), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_DTS_RESULT0                                        , RULL(0x2D050000), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_DTS_RESULT0                                        , RULL(0x2E050000), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_DTS_RESULT0                                        , RULL(0x2F050000), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_DTS_RESULT0                                        , RULL(0x30050000), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_DTS_RESULT0                                        , RULL(0x31050000), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_DTS_RESULT0                                        , RULL(0x32050000), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_DTS_RESULT0                                        , RULL(0x33050000), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_DTS_RESULT0                                        , RULL(0x34050000), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_DTS_RESULT0                                        , RULL(0x35050000), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_DTS_RESULT0                                        , RULL(0x36050000), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_DTS_RESULT0                                        , RULL(0x37050000), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EQ_DTS_RESULT0                                          , RULL(0x10050000), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_DTS_RESULT0                                        , RULL(0x10050000), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_DTS_RESULT0                                        , RULL(0x11050000), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_DTS_RESULT0                                        , RULL(0x12050000), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_DTS_RESULT0                                        , RULL(0x13050000), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_DTS_RESULT0                                        , RULL(0x14050000), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_DTS_RESULT0                                        , RULL(0x15050000), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_DTS_RESULT0                                          , RULL(0x20050000), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21050000,
+REG64( EX_0_DTS_RESULT0                                        , RULL(0x20050000), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21050000,
+REG64( EX_1_DTS_RESULT0                                        , RULL(0x22050000), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23050000,
+REG64( EX_2_DTS_RESULT0                                        , RULL(0x24050000), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25050000,
+REG64( EX_3_DTS_RESULT0                                        , RULL(0x26050000), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27050000,
+REG64( EX_4_DTS_RESULT0                                        , RULL(0x28050000), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29050000,
+REG64( EX_5_DTS_RESULT0                                        , RULL(0x2A050000), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B050000,
+REG64( EX_6_DTS_RESULT0                                        , RULL(0x2C050000), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D050000,
+REG64( EX_7_DTS_RESULT0                                        , RULL(0x2E050000), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F050000,
+REG64( EX_8_DTS_RESULT0                                        , RULL(0x30050000), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31050000,
+REG64( EX_9_DTS_RESULT0                                        , RULL(0x32050000), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33050000,
+REG64( EX_10_DTS_RESULT0                                       , RULL(0x34050000), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35050000,
+REG64( EX_11_DTS_RESULT0                                       , RULL(0x36050000), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37050000,
+
+REG64( C_DTS_TRC_RESULT                                        , RULL(0x20050003), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_DTS_TRC_RESULT                                      , RULL(0x20050003), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_DTS_TRC_RESULT                                      , RULL(0x21050003), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_DTS_TRC_RESULT                                      , RULL(0x22050003), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_DTS_TRC_RESULT                                      , RULL(0x23050003), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_DTS_TRC_RESULT                                      , RULL(0x24050003), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_DTS_TRC_RESULT                                      , RULL(0x25050003), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_DTS_TRC_RESULT                                      , RULL(0x26050003), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_DTS_TRC_RESULT                                      , RULL(0x27050003), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_DTS_TRC_RESULT                                      , RULL(0x28050003), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_DTS_TRC_RESULT                                      , RULL(0x29050003), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_DTS_TRC_RESULT                                     , RULL(0x2A050003), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_DTS_TRC_RESULT                                     , RULL(0x2B050003), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_DTS_TRC_RESULT                                     , RULL(0x2C050003), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_DTS_TRC_RESULT                                     , RULL(0x2D050003), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_DTS_TRC_RESULT                                     , RULL(0x2E050003), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_DTS_TRC_RESULT                                     , RULL(0x2F050003), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_DTS_TRC_RESULT                                     , RULL(0x30050003), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_DTS_TRC_RESULT                                     , RULL(0x31050003), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_DTS_TRC_RESULT                                     , RULL(0x32050003), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_DTS_TRC_RESULT                                     , RULL(0x33050003), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_DTS_TRC_RESULT                                     , RULL(0x34050003), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_DTS_TRC_RESULT                                     , RULL(0x35050003), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_DTS_TRC_RESULT                                     , RULL(0x36050003), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_DTS_TRC_RESULT                                     , RULL(0x37050003), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EQ_DTS_TRC_RESULT                                       , RULL(0x10050003), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_DTS_TRC_RESULT                                     , RULL(0x10050003), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_DTS_TRC_RESULT                                     , RULL(0x11050003), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_DTS_TRC_RESULT                                     , RULL(0x12050003), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_DTS_TRC_RESULT                                     , RULL(0x13050003), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_DTS_TRC_RESULT                                     , RULL(0x14050003), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_DTS_TRC_RESULT                                     , RULL(0x15050003), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_DTS_TRC_RESULT                                       , RULL(0x20050003), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21050003,
+REG64( EX_0_DTS_TRC_RESULT                                     , RULL(0x20050003), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21050003,
+REG64( EX_1_DTS_TRC_RESULT                                     , RULL(0x22050003), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23050003,
+REG64( EX_2_DTS_TRC_RESULT                                     , RULL(0x24050003), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25050003,
+REG64( EX_3_DTS_TRC_RESULT                                     , RULL(0x26050003), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27050003,
+REG64( EX_4_DTS_TRC_RESULT                                     , RULL(0x28050003), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29050003,
+REG64( EX_5_DTS_TRC_RESULT                                     , RULL(0x2A050003), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B050003,
+REG64( EX_6_DTS_TRC_RESULT                                     , RULL(0x2C050003), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D050003,
+REG64( EX_7_DTS_TRC_RESULT                                     , RULL(0x2E050003), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F050003,
+REG64( EX_8_DTS_TRC_RESULT                                     , RULL(0x30050003), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31050003,
+REG64( EX_9_DTS_TRC_RESULT                                     , RULL(0x32050003), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33050003,
+REG64( EX_10_DTS_TRC_RESULT                                    , RULL(0x34050003), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35050003,
+REG64( EX_11_DTS_TRC_RESULT                                    , RULL(0x36050003), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37050003,
+
+REG64( EQ_EDRAM_BANK_FAIL_SCOM_RD                              , RULL(0x1001181B), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C1B,
+REG64( EQ_0_EDRAM_BANK_FAIL_SCOM_RD                            , RULL(0x1001181B), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C1B,
+REG64( EQ_1_EDRAM_BANK_FAIL_SCOM_RD                            , RULL(0x1101181B), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C1B,
+REG64( EQ_2_EDRAM_BANK_FAIL_SCOM_RD                            , RULL(0x1201181B), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C1B,
+REG64( EQ_3_EDRAM_BANK_FAIL_SCOM_RD                            , RULL(0x1301181B), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C1B,
+REG64( EQ_4_EDRAM_BANK_FAIL_SCOM_RD                            , RULL(0x1401181B), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C1B,
+REG64( EQ_5_EDRAM_BANK_FAIL_SCOM_RD                            , RULL(0x1501181B), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C1B,
+REG64( EX_0_L3_EDRAM_BANK_FAIL_SCOM_RD                         , RULL(0x1001181B), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_L3_EDRAM_BANK_FAIL_SCOM_RD                        , RULL(0x1501181B), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L3_EDRAM_BANK_FAIL_SCOM_RD                        , RULL(0x15011C1B), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L3_EDRAM_BANK_FAIL_SCOM_RD                         , RULL(0x10011C1B), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L3_EDRAM_BANK_FAIL_SCOM_RD                         , RULL(0x1101181B), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L3_EDRAM_BANK_FAIL_SCOM_RD                         , RULL(0x11011C1B), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L3_EDRAM_BANK_FAIL_SCOM_RD                         , RULL(0x1201181B), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L3_EDRAM_BANK_FAIL_SCOM_RD                         , RULL(0x12011C1B), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L3_EDRAM_BANK_FAIL_SCOM_RD                         , RULL(0x1301181B), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L3_EDRAM_BANK_FAIL_SCOM_RD                         , RULL(0x13011C1B), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L3_EDRAM_BANK_FAIL_SCOM_RD                         , RULL(0x1401181B), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L3_EDRAM_BANK_FAIL_SCOM_RD                         , RULL(0x14011C1B), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L3_EDRAM_BANK_FAIL_SCOM_RD                           , RULL(0x1001181B), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( EQ_EDRAM_BANK_SOFT_DIS                                  , RULL(0x1001180B), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C0B,
+REG64( EQ_0_EDRAM_BANK_SOFT_DIS                                , RULL(0x1001180B), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C0B,
+REG64( EQ_1_EDRAM_BANK_SOFT_DIS                                , RULL(0x1101180B), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C0B,
+REG64( EQ_2_EDRAM_BANK_SOFT_DIS                                , RULL(0x1201180B), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C0B,
+REG64( EQ_3_EDRAM_BANK_SOFT_DIS                                , RULL(0x1301180B), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C0B,
+REG64( EQ_4_EDRAM_BANK_SOFT_DIS                                , RULL(0x1401180B), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C0B,
+REG64( EQ_5_EDRAM_BANK_SOFT_DIS                                , RULL(0x1501180B), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C0B,
+REG64( EX_0_L3_EDRAM_BANK_SOFT_DIS                             , RULL(0x1001180B), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_L3_EDRAM_BANK_SOFT_DIS                            , RULL(0x1501180B), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L3_EDRAM_BANK_SOFT_DIS                            , RULL(0x15011C0B), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L3_EDRAM_BANK_SOFT_DIS                             , RULL(0x10011C0B), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L3_EDRAM_BANK_SOFT_DIS                             , RULL(0x1101180B), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L3_EDRAM_BANK_SOFT_DIS                             , RULL(0x11011C0B), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L3_EDRAM_BANK_SOFT_DIS                             , RULL(0x1201180B), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L3_EDRAM_BANK_SOFT_DIS                             , RULL(0x12011C0B), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L3_EDRAM_BANK_SOFT_DIS                             , RULL(0x1301180B), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L3_EDRAM_BANK_SOFT_DIS                             , RULL(0x13011C0B), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L3_EDRAM_BANK_SOFT_DIS                             , RULL(0x1401180B), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L3_EDRAM_BANK_SOFT_DIS                             , RULL(0x14011C0B), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L3_EDRAM_BANK_SOFT_DIS                               , RULL(0x1001180B), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( EQ_EDRAM_REG                                            , RULL(0x1001180C), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C0C,
+REG64( EQ_0_EDRAM_REG                                          , RULL(0x1001180C), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C0C,
+REG64( EQ_1_EDRAM_REG                                          , RULL(0x1101180C), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C0C,
+REG64( EQ_2_EDRAM_REG                                          , RULL(0x1201180C), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C0C,
+REG64( EQ_3_EDRAM_REG                                          , RULL(0x1301180C), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C0C,
+REG64( EQ_4_EDRAM_REG                                          , RULL(0x1401180C), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C0C,
+REG64( EQ_5_EDRAM_REG                                          , RULL(0x1501180C), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C0C,
+REG64( EX_0_L3_EDRAM_REG                                       , RULL(0x1001180C), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_L3_EDRAM_REG                                      , RULL(0x1501180C), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L3_EDRAM_REG                                      , RULL(0x15011C0C), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L3_EDRAM_REG                                       , RULL(0x10011C0C), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L3_EDRAM_REG                                       , RULL(0x1101180C), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L3_EDRAM_REG                                       , RULL(0x11011C0C), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L3_EDRAM_REG                                       , RULL(0x1201180C), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L3_EDRAM_REG                                       , RULL(0x12011C0C), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L3_EDRAM_REG                                       , RULL(0x1301180C), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L3_EDRAM_REG                                       , RULL(0x13011C0C), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L3_EDRAM_REG                                       , RULL(0x1401180C), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L3_EDRAM_REG                                       , RULL(0x14011C0C), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L3_EDRAM_REG                                         , RULL(0x1001180C), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( EQ_ED_RD_ERR_STAT_REG0                                  , RULL(0x10011819), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C19,
+REG64( EQ_0_ED_RD_ERR_STAT_REG0                                , RULL(0x10011819), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C19,
+REG64( EQ_1_ED_RD_ERR_STAT_REG0                                , RULL(0x11011819), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C19,
+REG64( EQ_2_ED_RD_ERR_STAT_REG0                                , RULL(0x12011819), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C19,
+REG64( EQ_3_ED_RD_ERR_STAT_REG0                                , RULL(0x13011819), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C19,
+REG64( EQ_4_ED_RD_ERR_STAT_REG0                                , RULL(0x14011819), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C19,
+REG64( EQ_5_ED_RD_ERR_STAT_REG0                                , RULL(0x15011819), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C19,
+REG64( EX_ED_RD_ERR_STAT_REG0                                  , RULL(0x10011819), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_ED_RD_ERR_STAT_REG0                                , RULL(0x10011819), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_ED_RD_ERR_STAT_REG0                                , RULL(0x10011C19), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_ED_RD_ERR_STAT_REG0                                , RULL(0x11011819), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_ED_RD_ERR_STAT_REG0                                , RULL(0x11011C19), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_ED_RD_ERR_STAT_REG0                                , RULL(0x12011819), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_ED_RD_ERR_STAT_REG0                                , RULL(0x12011C19), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_ED_RD_ERR_STAT_REG0                                , RULL(0x13011819), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_ED_RD_ERR_STAT_REG0                                , RULL(0x13011C19), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_ED_RD_ERR_STAT_REG0                                , RULL(0x14011819), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_ED_RD_ERR_STAT_REG0                                , RULL(0x14011C19), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_ED_RD_ERR_STAT_REG0                               , RULL(0x15011819), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_ED_RD_ERR_STAT_REG0                               , RULL(0x15011C19), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_ED_RD_ERR_STAT_REG1                                  , RULL(0x1001181A), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C1A,
+REG64( EQ_0_ED_RD_ERR_STAT_REG1                                , RULL(0x1001181A), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C1A,
+REG64( EQ_1_ED_RD_ERR_STAT_REG1                                , RULL(0x1101181A), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C1A,
+REG64( EQ_2_ED_RD_ERR_STAT_REG1                                , RULL(0x1201181A), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C1A,
+REG64( EQ_3_ED_RD_ERR_STAT_REG1                                , RULL(0x1301181A), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C1A,
+REG64( EQ_4_ED_RD_ERR_STAT_REG1                                , RULL(0x1401181A), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C1A,
+REG64( EQ_5_ED_RD_ERR_STAT_REG1                                , RULL(0x1501181A), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C1A,
+REG64( EX_0_L3_ED_RD_ERR_STAT_REG1                             , RULL(0x1001181A), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_L3_ED_RD_ERR_STAT_REG1                            , RULL(0x1501181A), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L3_ED_RD_ERR_STAT_REG1                            , RULL(0x15011C1A), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L3_ED_RD_ERR_STAT_REG1                             , RULL(0x10011C1A), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L3_ED_RD_ERR_STAT_REG1                             , RULL(0x1101181A), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L3_ED_RD_ERR_STAT_REG1                             , RULL(0x11011C1A), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L3_ED_RD_ERR_STAT_REG1                             , RULL(0x1201181A), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L3_ED_RD_ERR_STAT_REG1                             , RULL(0x12011C1A), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L3_ED_RD_ERR_STAT_REG1                             , RULL(0x1301181A), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L3_ED_RD_ERR_STAT_REG1                             , RULL(0x13011C1A), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L3_ED_RD_ERR_STAT_REG1                             , RULL(0x1401181A), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L3_ED_RD_ERR_STAT_REG1                             , RULL(0x14011C1A), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L3_ED_RD_ERR_STAT_REG1                               , RULL(0x1001181A), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( C_ERROR_REG                                             , RULL(0x200F001F), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_ERROR_REG                                           , RULL(0x200F001F), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_ERROR_REG                                           , RULL(0x210F001F), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_ERROR_REG                                           , RULL(0x220F001F), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_ERROR_REG                                           , RULL(0x230F001F), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_ERROR_REG                                           , RULL(0x240F001F), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_ERROR_REG                                           , RULL(0x250F001F), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_ERROR_REG                                           , RULL(0x260F001F), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_ERROR_REG                                           , RULL(0x270F001F), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_ERROR_REG                                           , RULL(0x280F001F), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_ERROR_REG                                           , RULL(0x290F001F), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_ERROR_REG                                          , RULL(0x2A0F001F), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_ERROR_REG                                          , RULL(0x2B0F001F), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_ERROR_REG                                          , RULL(0x2C0F001F), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_ERROR_REG                                          , RULL(0x2D0F001F), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_ERROR_REG                                          , RULL(0x2E0F001F), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_ERROR_REG                                          , RULL(0x2F0F001F), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_ERROR_REG                                          , RULL(0x300F001F), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_ERROR_REG                                          , RULL(0x310F001F), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_ERROR_REG                                          , RULL(0x320F001F), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_ERROR_REG                                          , RULL(0x330F001F), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_ERROR_REG                                          , RULL(0x340F001F), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_ERROR_REG                                          , RULL(0x350F001F), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_ERROR_REG                                          , RULL(0x360F001F), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_ERROR_REG                                          , RULL(0x370F001F), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_ERROR_REG                                            , RULL(0x100F001F), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_ERROR_REG                                          , RULL(0x100F001F), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_ERROR_REG                                          , RULL(0x110F001F), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_ERROR_REG                                          , RULL(0x120F001F), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_ERROR_REG                                          , RULL(0x130F001F), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_ERROR_REG                                          , RULL(0x140F001F), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_ERROR_REG                                          , RULL(0x150F001F), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_ERROR_REG                                            , RULL(0x200F001F), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F001F,
+REG64( EX_0_ERROR_REG                                          , RULL(0x200F001F), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F001F,
+REG64( EX_1_ERROR_REG                                          , RULL(0x230F001F), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F001F,
+REG64( EX_2_ERROR_REG                                          , RULL(0x240F001F), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F001F,
+REG64( EX_3_ERROR_REG                                          , RULL(0x260F001F), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F001F,
+REG64( EX_4_ERROR_REG                                          , RULL(0x280F001F), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F001F,
+REG64( EX_5_ERROR_REG                                          , RULL(0x2A0F001F), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F001F,
+REG64( EX_6_ERROR_REG                                          , RULL(0x2C0F001F), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F001F,
+REG64( EX_7_ERROR_REG                                          , RULL(0x2E0F001F), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F001F,
+REG64( EX_8_ERROR_REG                                          , RULL(0x300F001F), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F001F,
+REG64( EX_9_ERROR_REG                                          , RULL(0x320F001F), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F001F,
+REG64( EX_10_ERROR_REG                                         , RULL(0x340F001F), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F001F,
+REG64( EX_11_ERROR_REG                                         , RULL(0x360F001F), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F001F,
+
+REG64( C_ERROR_STATUS                                          , RULL(0x2003000F), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_ERROR_STATUS                                        , RULL(0x2003000F), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_ERROR_STATUS                                        , RULL(0x2103000F), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_ERROR_STATUS                                        , RULL(0x2203000F), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_ERROR_STATUS                                        , RULL(0x2303000F), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_ERROR_STATUS                                        , RULL(0x2403000F), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_ERROR_STATUS                                        , RULL(0x2503000F), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_ERROR_STATUS                                        , RULL(0x2603000F), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_ERROR_STATUS                                        , RULL(0x2703000F), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_ERROR_STATUS                                        , RULL(0x2803000F), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_ERROR_STATUS                                        , RULL(0x2903000F), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_ERROR_STATUS                                       , RULL(0x2A03000F), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_ERROR_STATUS                                       , RULL(0x2B03000F), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_ERROR_STATUS                                       , RULL(0x2C03000F), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_ERROR_STATUS                                       , RULL(0x2D03000F), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_ERROR_STATUS                                       , RULL(0x2E03000F), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_ERROR_STATUS                                       , RULL(0x2F03000F), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_ERROR_STATUS                                       , RULL(0x3003000F), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_ERROR_STATUS                                       , RULL(0x3103000F), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_ERROR_STATUS                                       , RULL(0x3203000F), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_ERROR_STATUS                                       , RULL(0x3303000F), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_ERROR_STATUS                                       , RULL(0x3403000F), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_ERROR_STATUS                                       , RULL(0x3503000F), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_ERROR_STATUS                                       , RULL(0x3603000F), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_ERROR_STATUS                                       , RULL(0x3703000F), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_ERROR_STATUS                                         , RULL(0x1003000F), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_ERROR_STATUS                                       , RULL(0x1003000F), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_ERROR_STATUS                                       , RULL(0x1103000F), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_ERROR_STATUS                                       , RULL(0x1203000F), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_ERROR_STATUS                                       , RULL(0x1303000F), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_ERROR_STATUS                                       , RULL(0x1403000F), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_ERROR_STATUS                                       , RULL(0x1503000F), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_ERROR_STATUS                                         , RULL(0x2003000F), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 2103000F,
+REG64( EX_0_ERROR_STATUS                                       , RULL(0x2003000F), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 2103000F,
+REG64( EX_1_ERROR_STATUS                                       , RULL(0x2203000F), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 2303000F,
+REG64( EX_2_ERROR_STATUS                                       , RULL(0x2403000F), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 2503000F,
+REG64( EX_3_ERROR_STATUS                                       , RULL(0x2603000F), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 2703000F,
+REG64( EX_4_ERROR_STATUS                                       , RULL(0x2803000F), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 2903000F,
+REG64( EX_5_ERROR_STATUS                                       , RULL(0x2A03000F), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B03000F,
+REG64( EX_6_ERROR_STATUS                                       , RULL(0x2C03000F), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D03000F,
+REG64( EX_7_ERROR_STATUS                                       , RULL(0x2E03000F), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F03000F,
+REG64( EX_8_ERROR_STATUS                                       , RULL(0x3003000F), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 3103000F,
+REG64( EX_9_ERROR_STATUS                                       , RULL(0x3203000F), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 3303000F,
+REG64( EX_10_ERROR_STATUS                                      , RULL(0x3403000F), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 3503000F,
+REG64( EX_11_ERROR_STATUS                                      , RULL(0x3603000F), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 3703000F,
+
+REG64( C_ERR_INJ_REG                                           , RULL(0x20010C04), SH_UNT_C        ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010CBF,
+REG64( C_0_ERR_INJ_REG                                         , RULL(0x20010C04), SH_UNT_C_0      ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010CBF,
+REG64( C_1_ERR_INJ_REG                                         , RULL(0x21010C04), SH_UNT_C_1      ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010CBF,
+REG64( C_2_ERR_INJ_REG                                         , RULL(0x22010C04), SH_UNT_C_2      ,
+       SH_ACS_SCOM_RW   ); //DUPS: 22010CBF,
+REG64( C_3_ERR_INJ_REG                                         , RULL(0x23010C04), SH_UNT_C_3      ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010CBF,
+REG64( C_4_ERR_INJ_REG                                         , RULL(0x24010C04), SH_UNT_C_4      ,
+       SH_ACS_SCOM_RW   ); //DUPS: 24010CBF,
+REG64( C_5_ERR_INJ_REG                                         , RULL(0x25010C04), SH_UNT_C_5      ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010CBF,
+REG64( C_6_ERR_INJ_REG                                         , RULL(0x26010C04), SH_UNT_C_6      ,
+       SH_ACS_SCOM_RW   ); //DUPS: 26010CBF,
+REG64( C_7_ERR_INJ_REG                                         , RULL(0x27010C04), SH_UNT_C_7      ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010CBF,
+REG64( C_8_ERR_INJ_REG                                         , RULL(0x28010C04), SH_UNT_C_8      ,
+       SH_ACS_SCOM_RW   ); //DUPS: 28010CBF,
+REG64( C_9_ERR_INJ_REG                                         , RULL(0x29010C04), SH_UNT_C_9      ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010CBF,
+REG64( C_10_ERR_INJ_REG                                        , RULL(0x2A010C04), SH_UNT_C_10     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2A010CBF,
+REG64( C_11_ERR_INJ_REG                                        , RULL(0x2B010C04), SH_UNT_C_11     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010CBF,
+REG64( C_12_ERR_INJ_REG                                        , RULL(0x2C010C04), SH_UNT_C_12     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2C010CBF,
+REG64( C_13_ERR_INJ_REG                                        , RULL(0x2D010C04), SH_UNT_C_13     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010CBF,
+REG64( C_14_ERR_INJ_REG                                        , RULL(0x2E010C04), SH_UNT_C_14     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2E010CBF,
+REG64( C_15_ERR_INJ_REG                                        , RULL(0x2F010C04), SH_UNT_C_15     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010CBF,
+REG64( C_16_ERR_INJ_REG                                        , RULL(0x30010C04), SH_UNT_C_16     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 30010CBF,
+REG64( C_17_ERR_INJ_REG                                        , RULL(0x31010C04), SH_UNT_C_17     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010CBF,
+REG64( C_18_ERR_INJ_REG                                        , RULL(0x32010C04), SH_UNT_C_18     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 32010CBF,
+REG64( C_19_ERR_INJ_REG                                        , RULL(0x33010C04), SH_UNT_C_19     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010CBF,
+REG64( C_20_ERR_INJ_REG                                        , RULL(0x34010C04), SH_UNT_C_20     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 34010CBF,
+REG64( C_21_ERR_INJ_REG                                        , RULL(0x35010C04), SH_UNT_C_21     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010CBF,
+REG64( C_22_ERR_INJ_REG                                        , RULL(0x36010C04), SH_UNT_C_22     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 36010CBF,
+REG64( C_23_ERR_INJ_REG                                        , RULL(0x37010C04), SH_UNT_C_23     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010CBF,
+REG64( EQ_ERR_INJ_REG                                          , RULL(0x1001080C), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 1001180D, 10010C0C, 10011C0D,
+REG64( EQ_0_ERR_INJ_REG                                        , RULL(0x1001080C), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 1001180D, 10010C0C, 10011C0D,
+REG64( EQ_1_ERR_INJ_REG                                        , RULL(0x1101080C), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 1101180D, 11010C0C, 11011C0D,
+REG64( EQ_2_ERR_INJ_REG                                        , RULL(0x1201080C), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 1201180D, 12010C0C, 12011C0D,
+REG64( EQ_3_ERR_INJ_REG                                        , RULL(0x1301080C), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 1301180D, 13010C0C, 13011C0D,
+REG64( EQ_4_ERR_INJ_REG                                        , RULL(0x1401080C), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 1401180D, 14010C0C, 14011C0D,
+REG64( EQ_5_ERR_INJ_REG                                        , RULL(0x1501080C), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 1501180D, 15010C0C, 15011C0D,
+REG64( EX_ERR_INJ_REG                                          , RULL(0x20010CBF), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010CBF,
+REG64( EX_0_ERR_INJ_REG                                        , RULL(0x20010CBF), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010CBF,
+REG64( EX_1_ERR_INJ_REG                                        , RULL(0x22010CBF), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010CBF,
+REG64( EX_2_ERR_INJ_REG                                        , RULL(0x24010CBF), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010CBF,
+REG64( EX_3_ERR_INJ_REG                                        , RULL(0x26010CBF), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010CBF,
+REG64( EX_4_ERR_INJ_REG                                        , RULL(0x28010CBF), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010CBF,
+REG64( EX_5_ERR_INJ_REG                                        , RULL(0x2A010CBF), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010CBF,
+REG64( EX_6_ERR_INJ_REG                                        , RULL(0x2C010CBF), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010CBF,
+REG64( EX_7_ERR_INJ_REG                                        , RULL(0x2E010CBF), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010CBF,
+REG64( EX_8_ERR_INJ_REG                                        , RULL(0x30010CBF), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010CBF,
+REG64( EX_9_ERR_INJ_REG                                        , RULL(0x32010CBF), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010CBF,
+REG64( EX_0_L2_ERR_INJ_REG                                     , RULL(0x20010C04), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010C04, 1001080C,
+REG64( EX_0_L3_ERR_INJ_REG                                     , RULL(0x1001180D), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_ERR_INJ_REG                                       , RULL(0x34010CBF), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010CBF,
+REG64( EX_11_ERR_INJ_REG                                       , RULL(0x36010CBF), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010CBF,
+REG64( EX_10_L2_ERR_INJ_REG                                    , RULL(0x34010C04), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010C04, 1501080C,
+REG64( EX_10_L3_ERR_INJ_REG                                    , RULL(0x1501180D), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L2_ERR_INJ_REG                                    , RULL(0x36010C04), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010C04, 15010C0C,
+REG64( EX_11_L3_ERR_INJ_REG                                    , RULL(0x15011C0D), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L2_ERR_INJ_REG                                     , RULL(0x22010C04), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010C04, 10010C0C,
+REG64( EX_1_L3_ERR_INJ_REG                                     , RULL(0x10011C0D), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L2_ERR_INJ_REG                                     , RULL(0x24010C04), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010C04, 1101080C,
+REG64( EX_2_L3_ERR_INJ_REG                                     , RULL(0x1101180D), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L2_ERR_INJ_REG                                     , RULL(0x26010C04), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010C04, 11010C0C,
+REG64( EX_3_L3_ERR_INJ_REG                                     , RULL(0x11011C0D), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L2_ERR_INJ_REG                                     , RULL(0x28010C04), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010C04, 1201080C,
+REG64( EX_4_L3_ERR_INJ_REG                                     , RULL(0x1201180D), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L2_ERR_INJ_REG                                     , RULL(0x2A010C04), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010C04, 12010C0C,
+REG64( EX_5_L3_ERR_INJ_REG                                     , RULL(0x12011C0D), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L2_ERR_INJ_REG                                     , RULL(0x2C010C04), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010C04, 1301080C,
+REG64( EX_6_L3_ERR_INJ_REG                                     , RULL(0x1301180D), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L2_ERR_INJ_REG                                     , RULL(0x2E010C04), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010C04, 13010C0C,
+REG64( EX_7_L3_ERR_INJ_REG                                     , RULL(0x13011C0D), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L2_ERR_INJ_REG                                     , RULL(0x30010C04), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010C04, 1401080C,
+REG64( EX_8_L3_ERR_INJ_REG                                     , RULL(0x1401180D), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L2_ERR_INJ_REG                                     , RULL(0x32010C04), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010C04, 14010C0C,
+REG64( EX_9_L3_ERR_INJ_REG                                     , RULL(0x14011C0D), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L2_ERR_INJ_REG                                       , RULL(0x20010C04), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010C04, 1001080C,
+REG64( EX_L3_ERR_INJ_REG                                       , RULL(0x1001180D), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( EQ_ERR_RPT0                                             , RULL(0x10010812), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10010C12,
+REG64( EQ_0_ERR_RPT0                                           , RULL(0x10010812), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10010C12,
+REG64( EQ_1_ERR_RPT0                                           , RULL(0x11010812), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11010C12,
+REG64( EQ_2_ERR_RPT0                                           , RULL(0x12010812), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12010C12,
+REG64( EQ_3_ERR_RPT0                                           , RULL(0x13010812), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13010C12,
+REG64( EQ_4_ERR_RPT0                                           , RULL(0x14010812), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14010C12,
+REG64( EQ_5_ERR_RPT0                                           , RULL(0x15010812), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15010C12,
+REG64( EX_0_L2_ERR_RPT0                                        , RULL(0x10010812), SH_UNT_EX_0_L2  , SH_ACS_SCOM      );
+REG64( EX_10_L2_ERR_RPT0                                       , RULL(0x15010812), SH_UNT_EX_10_L2 , SH_ACS_SCOM      );
+REG64( EX_11_L2_ERR_RPT0                                       , RULL(0x15010C12), SH_UNT_EX_11_L2 , SH_ACS_SCOM      );
+REG64( EX_1_L2_ERR_RPT0                                        , RULL(0x10010C12), SH_UNT_EX_1_L2  , SH_ACS_SCOM      );
+REG64( EX_2_L2_ERR_RPT0                                        , RULL(0x11010812), SH_UNT_EX_2_L2  , SH_ACS_SCOM      );
+REG64( EX_3_L2_ERR_RPT0                                        , RULL(0x11010C12), SH_UNT_EX_3_L2  , SH_ACS_SCOM      );
+REG64( EX_4_L2_ERR_RPT0                                        , RULL(0x12010812), SH_UNT_EX_4_L2  , SH_ACS_SCOM      );
+REG64( EX_5_L2_ERR_RPT0                                        , RULL(0x12010C12), SH_UNT_EX_5_L2  , SH_ACS_SCOM      );
+REG64( EX_6_L2_ERR_RPT0                                        , RULL(0x13010812), SH_UNT_EX_6_L2  , SH_ACS_SCOM      );
+REG64( EX_7_L2_ERR_RPT0                                        , RULL(0x13010C12), SH_UNT_EX_7_L2  , SH_ACS_SCOM      );
+REG64( EX_8_L2_ERR_RPT0                                        , RULL(0x14010812), SH_UNT_EX_8_L2  , SH_ACS_SCOM      );
+REG64( EX_9_L2_ERR_RPT0                                        , RULL(0x14010C12), SH_UNT_EX_9_L2  , SH_ACS_SCOM      );
+REG64( EX_L2_ERR_RPT0                                          , RULL(0x10010812), SH_UNT_EX_L2    , SH_ACS_SCOM      );
+
+REG64( EQ_ERR_RPT1                                             , RULL(0x10010813), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10010C13,
+REG64( EQ_0_ERR_RPT1                                           , RULL(0x10010813), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10010C13,
+REG64( EQ_1_ERR_RPT1                                           , RULL(0x11010813), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11010C13,
+REG64( EQ_2_ERR_RPT1                                           , RULL(0x12010813), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12010C13,
+REG64( EQ_3_ERR_RPT1                                           , RULL(0x13010813), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13010C13,
+REG64( EQ_4_ERR_RPT1                                           , RULL(0x14010813), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14010C13,
+REG64( EQ_5_ERR_RPT1                                           , RULL(0x15010813), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15010C13,
+REG64( EX_0_L2_ERR_RPT1                                        , RULL(0x10010813), SH_UNT_EX_0_L2  , SH_ACS_SCOM      );
+REG64( EX_10_L2_ERR_RPT1                                       , RULL(0x15010813), SH_UNT_EX_10_L2 , SH_ACS_SCOM      );
+REG64( EX_11_L2_ERR_RPT1                                       , RULL(0x15010C13), SH_UNT_EX_11_L2 , SH_ACS_SCOM      );
+REG64( EX_1_L2_ERR_RPT1                                        , RULL(0x10010C13), SH_UNT_EX_1_L2  , SH_ACS_SCOM      );
+REG64( EX_2_L2_ERR_RPT1                                        , RULL(0x11010813), SH_UNT_EX_2_L2  , SH_ACS_SCOM      );
+REG64( EX_3_L2_ERR_RPT1                                        , RULL(0x11010C13), SH_UNT_EX_3_L2  , SH_ACS_SCOM      );
+REG64( EX_4_L2_ERR_RPT1                                        , RULL(0x12010813), SH_UNT_EX_4_L2  , SH_ACS_SCOM      );
+REG64( EX_5_L2_ERR_RPT1                                        , RULL(0x12010C13), SH_UNT_EX_5_L2  , SH_ACS_SCOM      );
+REG64( EX_6_L2_ERR_RPT1                                        , RULL(0x13010813), SH_UNT_EX_6_L2  , SH_ACS_SCOM      );
+REG64( EX_7_L2_ERR_RPT1                                        , RULL(0x13010C13), SH_UNT_EX_7_L2  , SH_ACS_SCOM      );
+REG64( EX_8_L2_ERR_RPT1                                        , RULL(0x14010813), SH_UNT_EX_8_L2  , SH_ACS_SCOM      );
+REG64( EX_9_L2_ERR_RPT1                                        , RULL(0x14010C13), SH_UNT_EX_9_L2  , SH_ACS_SCOM      );
+REG64( EX_L2_ERR_RPT1                                          , RULL(0x10010813), SH_UNT_EX_L2    , SH_ACS_SCOM      );
+
+REG64( EQ_ERR_RPT_REG                                          , RULL(0x1001100E), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 1001140E,
+REG64( EQ_0_ERR_RPT_REG                                        , RULL(0x1001100E), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 1001140E,
+REG64( EQ_1_ERR_RPT_REG                                        , RULL(0x1101100E), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 1101140E,
+REG64( EQ_2_ERR_RPT_REG                                        , RULL(0x1201100E), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 1201140E,
+REG64( EQ_3_ERR_RPT_REG                                        , RULL(0x1301100E), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 1301140E,
+REG64( EQ_4_ERR_RPT_REG                                        , RULL(0x1401100E), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 1401140E,
+REG64( EQ_5_ERR_RPT_REG                                        , RULL(0x1501100E), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 1501140E,
+REG64( EX_ERR_RPT_REG                                          , RULL(0x1001100E), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_ERR_RPT_REG                                        , RULL(0x1001100E), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_ERR_RPT_REG                                        , RULL(0x1001140E), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_ERR_RPT_REG                                        , RULL(0x1101100E), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_ERR_RPT_REG                                        , RULL(0x1101140E), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_ERR_RPT_REG                                        , RULL(0x1201100E), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_ERR_RPT_REG                                        , RULL(0x1201140E), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_ERR_RPT_REG                                        , RULL(0x1301100E), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_ERR_RPT_REG                                        , RULL(0x1301140E), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_ERR_RPT_REG                                        , RULL(0x1401100E), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_ERR_RPT_REG                                        , RULL(0x1401140E), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_ERR_RPT_REG                                       , RULL(0x1501100E), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_ERR_RPT_REG                                       , RULL(0x1501140E), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( C_ERR_STATUS_REG                                        , RULL(0x20050013), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_ERR_STATUS_REG                                      , RULL(0x20050013), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_ERR_STATUS_REG                                      , RULL(0x21050013), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_ERR_STATUS_REG                                      , RULL(0x22050013), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_ERR_STATUS_REG                                      , RULL(0x23050013), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_ERR_STATUS_REG                                      , RULL(0x24050013), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_ERR_STATUS_REG                                      , RULL(0x25050013), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_ERR_STATUS_REG                                      , RULL(0x26050013), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_ERR_STATUS_REG                                      , RULL(0x27050013), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_ERR_STATUS_REG                                      , RULL(0x28050013), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_ERR_STATUS_REG                                      , RULL(0x29050013), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_ERR_STATUS_REG                                     , RULL(0x2A050013), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_ERR_STATUS_REG                                     , RULL(0x2B050013), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_ERR_STATUS_REG                                     , RULL(0x2C050013), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_ERR_STATUS_REG                                     , RULL(0x2D050013), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_ERR_STATUS_REG                                     , RULL(0x2E050013), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_ERR_STATUS_REG                                     , RULL(0x2F050013), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_ERR_STATUS_REG                                     , RULL(0x30050013), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_ERR_STATUS_REG                                     , RULL(0x31050013), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_ERR_STATUS_REG                                     , RULL(0x32050013), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_ERR_STATUS_REG                                     , RULL(0x33050013), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_ERR_STATUS_REG                                     , RULL(0x34050013), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_ERR_STATUS_REG                                     , RULL(0x35050013), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_ERR_STATUS_REG                                     , RULL(0x36050013), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_ERR_STATUS_REG                                     , RULL(0x37050013), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EQ_ERR_STATUS_REG                                       , RULL(0x10050013), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_ERR_STATUS_REG                                     , RULL(0x10050013), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_ERR_STATUS_REG                                     , RULL(0x11050013), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_ERR_STATUS_REG                                     , RULL(0x12050013), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_ERR_STATUS_REG                                     , RULL(0x13050013), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_ERR_STATUS_REG                                     , RULL(0x14050013), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_ERR_STATUS_REG                                     , RULL(0x15050013), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_ERR_STATUS_REG                                       , RULL(0x20050013), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21050013,
+REG64( EX_0_ERR_STATUS_REG                                     , RULL(0x20050013), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21050013,
+REG64( EX_1_ERR_STATUS_REG                                     , RULL(0x22050013), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23050013,
+REG64( EX_2_ERR_STATUS_REG                                     , RULL(0x24050013), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25050013,
+REG64( EX_3_ERR_STATUS_REG                                     , RULL(0x26050013), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27050013,
+REG64( EX_4_ERR_STATUS_REG                                     , RULL(0x28050013), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29050013,
+REG64( EX_5_ERR_STATUS_REG                                     , RULL(0x2A050013), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B050013,
+REG64( EX_6_ERR_STATUS_REG                                     , RULL(0x2C050013), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D050013,
+REG64( EX_7_ERR_STATUS_REG                                     , RULL(0x2E050013), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F050013,
+REG64( EX_8_ERR_STATUS_REG                                     , RULL(0x30050013), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31050013,
+REG64( EX_9_ERR_STATUS_REG                                     , RULL(0x32050013), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33050013,
+REG64( EX_10_ERR_STATUS_REG                                    , RULL(0x34050013), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35050013,
+REG64( EX_11_ERR_STATUS_REG                                    , RULL(0x36050013), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37050013,
+
+REG64( EQ_FIR_ACTION0_REG                                      , RULL(0x10010806), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10011806, 10011006, 10010C06, 10011C06, 10011406,
+REG64( EQ_0_FIR_ACTION0_REG                                    , RULL(0x10010806), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10011806, 10011006, 10010C06, 10011C06, 10011406,
+REG64( EQ_1_FIR_ACTION0_REG                                    , RULL(0x11010806), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11011806, 11011006, 11010C06, 11011C06, 11011406,
+REG64( EQ_2_FIR_ACTION0_REG                                    , RULL(0x12010806), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12011806, 12011006, 12010C06, 12011C06, 12011406,
+REG64( EQ_3_FIR_ACTION0_REG                                    , RULL(0x13010806), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13011806, 13011006, 13010C06, 13011C06, 13011406,
+REG64( EQ_4_FIR_ACTION0_REG                                    , RULL(0x14010806), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14011806, 14011006, 14010C06, 14011C06, 14011406,
+REG64( EQ_5_FIR_ACTION0_REG                                    , RULL(0x15010806), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15011806, 15011006, 15010C06, 15011C06, 15011406,
+REG64( EX_FIR_ACTION0_REG                                      , RULL(0x10011006), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_FIR_ACTION0_REG                                    , RULL(0x10011006), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_FIR_ACTION0_REG                                    , RULL(0x10011406), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_FIR_ACTION0_REG                                    , RULL(0x11011006), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_FIR_ACTION0_REG                                    , RULL(0x11011406), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_FIR_ACTION0_REG                                    , RULL(0x12011006), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_FIR_ACTION0_REG                                    , RULL(0x12011406), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_FIR_ACTION0_REG                                    , RULL(0x13011006), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_FIR_ACTION0_REG                                    , RULL(0x13011406), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_FIR_ACTION0_REG                                    , RULL(0x14011006), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_FIR_ACTION0_REG                                    , RULL(0x14011406), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_FIR_ACTION0_REG                                 , RULL(0x10010806), SH_UNT_EX_0_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_0_L3_FIR_ACTION0_REG                                 , RULL(0x10011806), SH_UNT_EX_0_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_10_FIR_ACTION0_REG                                   , RULL(0x15011006), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_FIR_ACTION0_REG                                   , RULL(0x15011406), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+REG64( EX_10_L2_FIR_ACTION0_REG                                , RULL(0x15010806), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RW   );
+REG64( EX_10_L3_FIR_ACTION0_REG                                , RULL(0x15011806), SH_UNT_EX_10_L3 , SH_ACS_SCOM_RW   );
+REG64( EX_11_L2_FIR_ACTION0_REG                                , RULL(0x15010C06), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RW   );
+REG64( EX_11_L3_FIR_ACTION0_REG                                , RULL(0x15011C06), SH_UNT_EX_11_L3 , SH_ACS_SCOM_RW   );
+REG64( EX_1_L2_FIR_ACTION0_REG                                 , RULL(0x10010C06), SH_UNT_EX_1_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_1_L3_FIR_ACTION0_REG                                 , RULL(0x10011C06), SH_UNT_EX_1_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_2_L2_FIR_ACTION0_REG                                 , RULL(0x11010806), SH_UNT_EX_2_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_2_L3_FIR_ACTION0_REG                                 , RULL(0x11011806), SH_UNT_EX_2_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_3_L2_FIR_ACTION0_REG                                 , RULL(0x11010C06), SH_UNT_EX_3_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_3_L3_FIR_ACTION0_REG                                 , RULL(0x11011C06), SH_UNT_EX_3_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_4_L2_FIR_ACTION0_REG                                 , RULL(0x12010806), SH_UNT_EX_4_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_4_L3_FIR_ACTION0_REG                                 , RULL(0x12011806), SH_UNT_EX_4_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_5_L2_FIR_ACTION0_REG                                 , RULL(0x12010C06), SH_UNT_EX_5_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_5_L3_FIR_ACTION0_REG                                 , RULL(0x12011C06), SH_UNT_EX_5_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_6_L2_FIR_ACTION0_REG                                 , RULL(0x13010806), SH_UNT_EX_6_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_6_L3_FIR_ACTION0_REG                                 , RULL(0x13011806), SH_UNT_EX_6_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_7_L2_FIR_ACTION0_REG                                 , RULL(0x13010C06), SH_UNT_EX_7_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_7_L3_FIR_ACTION0_REG                                 , RULL(0x13011C06), SH_UNT_EX_7_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_8_L2_FIR_ACTION0_REG                                 , RULL(0x14010806), SH_UNT_EX_8_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_8_L3_FIR_ACTION0_REG                                 , RULL(0x14011806), SH_UNT_EX_8_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_9_L2_FIR_ACTION0_REG                                 , RULL(0x14010C06), SH_UNT_EX_9_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_9_L3_FIR_ACTION0_REG                                 , RULL(0x14011C06), SH_UNT_EX_9_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_L2_FIR_ACTION0_REG                                   , RULL(0x10010806), SH_UNT_EX_L2    , SH_ACS_SCOM_RW   );
+REG64( EX_L3_FIR_ACTION0_REG                                   , RULL(0x10011806), SH_UNT_EX_L3    , SH_ACS_SCOM_RW   );
+
+REG64( EQ_FIR_ACTION1_REG                                      , RULL(0x10010807), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10011807, 10011007, 10010C07, 10011C07, 10011407,
+REG64( EQ_0_FIR_ACTION1_REG                                    , RULL(0x10010807), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10011807, 10011007, 10010C07, 10011C07, 10011407,
+REG64( EQ_1_FIR_ACTION1_REG                                    , RULL(0x11010807), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11011807, 11011007, 11010C07, 11011C07, 11011407,
+REG64( EQ_2_FIR_ACTION1_REG                                    , RULL(0x12010807), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12011807, 12011007, 12010C07, 12011C07, 12011407,
+REG64( EQ_3_FIR_ACTION1_REG                                    , RULL(0x13010807), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13011807, 13011007, 13010C07, 13011C07, 13011407,
+REG64( EQ_4_FIR_ACTION1_REG                                    , RULL(0x14010807), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14011807, 14011007, 14010C07, 14011C07, 14011407,
+REG64( EQ_5_FIR_ACTION1_REG                                    , RULL(0x15010807), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15011807, 15011007, 15010C07, 15011C07, 15011407,
+REG64( EX_FIR_ACTION1_REG                                      , RULL(0x10011007), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_0_FIR_ACTION1_REG                                    , RULL(0x10011007), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_1_FIR_ACTION1_REG                                    , RULL(0x10011407), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_2_FIR_ACTION1_REG                                    , RULL(0x11011007), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_3_FIR_ACTION1_REG                                    , RULL(0x11011407), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_4_FIR_ACTION1_REG                                    , RULL(0x12011007), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_5_FIR_ACTION1_REG                                    , RULL(0x12011407), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_6_FIR_ACTION1_REG                                    , RULL(0x13011007), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_7_FIR_ACTION1_REG                                    , RULL(0x13011407), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_8_FIR_ACTION1_REG                                    , RULL(0x14011007), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_9_FIR_ACTION1_REG                                    , RULL(0x14011407), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_FIR_ACTION1_REG                                 , RULL(0x10010807), SH_UNT_EX_0_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_0_L3_FIR_ACTION1_REG                                 , RULL(0x10011807), SH_UNT_EX_0_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_10_FIR_ACTION1_REG                                   , RULL(0x15011007), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_11_FIR_ACTION1_REG                                   , RULL(0x15011407), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+REG64( EX_10_L2_FIR_ACTION1_REG                                , RULL(0x15010807), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RW   );
+REG64( EX_10_L3_FIR_ACTION1_REG                                , RULL(0x15011807), SH_UNT_EX_10_L3 , SH_ACS_SCOM_RW   );
+REG64( EX_11_L2_FIR_ACTION1_REG                                , RULL(0x15010C07), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RW   );
+REG64( EX_11_L3_FIR_ACTION1_REG                                , RULL(0x15011C07), SH_UNT_EX_11_L3 , SH_ACS_SCOM_RW   );
+REG64( EX_1_L2_FIR_ACTION1_REG                                 , RULL(0x10010C07), SH_UNT_EX_1_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_1_L3_FIR_ACTION1_REG                                 , RULL(0x10011C07), SH_UNT_EX_1_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_2_L2_FIR_ACTION1_REG                                 , RULL(0x11010807), SH_UNT_EX_2_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_2_L3_FIR_ACTION1_REG                                 , RULL(0x11011807), SH_UNT_EX_2_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_3_L2_FIR_ACTION1_REG                                 , RULL(0x11010C07), SH_UNT_EX_3_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_3_L3_FIR_ACTION1_REG                                 , RULL(0x11011C07), SH_UNT_EX_3_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_4_L2_FIR_ACTION1_REG                                 , RULL(0x12010807), SH_UNT_EX_4_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_4_L3_FIR_ACTION1_REG                                 , RULL(0x12011807), SH_UNT_EX_4_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_5_L2_FIR_ACTION1_REG                                 , RULL(0x12010C07), SH_UNT_EX_5_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_5_L3_FIR_ACTION1_REG                                 , RULL(0x12011C07), SH_UNT_EX_5_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_6_L2_FIR_ACTION1_REG                                 , RULL(0x13010807), SH_UNT_EX_6_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_6_L3_FIR_ACTION1_REG                                 , RULL(0x13011807), SH_UNT_EX_6_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_7_L2_FIR_ACTION1_REG                                 , RULL(0x13010C07), SH_UNT_EX_7_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_7_L3_FIR_ACTION1_REG                                 , RULL(0x13011C07), SH_UNT_EX_7_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_8_L2_FIR_ACTION1_REG                                 , RULL(0x14010807), SH_UNT_EX_8_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_8_L3_FIR_ACTION1_REG                                 , RULL(0x14011807), SH_UNT_EX_8_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_9_L2_FIR_ACTION1_REG                                 , RULL(0x14010C07), SH_UNT_EX_9_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_9_L3_FIR_ACTION1_REG                                 , RULL(0x14011C07), SH_UNT_EX_9_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_L2_FIR_ACTION1_REG                                   , RULL(0x10010807), SH_UNT_EX_L2    , SH_ACS_SCOM_RW   );
+REG64( EX_L3_FIR_ACTION1_REG                                   , RULL(0x10011807), SH_UNT_EX_L3    , SH_ACS_SCOM_RW   );
+
+REG64( C_FIR_ERR_INJ                                           , RULL(0x20010A4D), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_FIR_ERR_INJ                                         , RULL(0x20010A4D), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_FIR_ERR_INJ                                         , RULL(0x21010A4D), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_FIR_ERR_INJ                                         , RULL(0x22010A4D), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_FIR_ERR_INJ                                         , RULL(0x23010A4D), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_FIR_ERR_INJ                                         , RULL(0x24010A4D), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_FIR_ERR_INJ                                         , RULL(0x25010A4D), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_FIR_ERR_INJ                                         , RULL(0x26010A4D), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_FIR_ERR_INJ                                         , RULL(0x27010A4D), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_FIR_ERR_INJ                                         , RULL(0x28010A4D), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_FIR_ERR_INJ                                         , RULL(0x29010A4D), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_FIR_ERR_INJ                                        , RULL(0x2A010A4D), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_FIR_ERR_INJ                                        , RULL(0x2B010A4D), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_FIR_ERR_INJ                                        , RULL(0x2C010A4D), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_FIR_ERR_INJ                                        , RULL(0x2D010A4D), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_FIR_ERR_INJ                                        , RULL(0x2E010A4D), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_FIR_ERR_INJ                                        , RULL(0x2F010A4D), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_FIR_ERR_INJ                                        , RULL(0x30010A4D), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_FIR_ERR_INJ                                        , RULL(0x31010A4D), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_FIR_ERR_INJ                                        , RULL(0x32010A4D), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_FIR_ERR_INJ                                        , RULL(0x33010A4D), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_FIR_ERR_INJ                                        , RULL(0x34010A4D), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_FIR_ERR_INJ                                        , RULL(0x35010A4D), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_FIR_ERR_INJ                                        , RULL(0x36010A4D), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_FIR_ERR_INJ                                        , RULL(0x37010A4D), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_FIR_ERR_INJ                                     , RULL(0x20010A4D), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A4D,
+REG64( EX_10_L2_FIR_ERR_INJ                                    , RULL(0x34010A4D), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010A4D,
+REG64( EX_11_L2_FIR_ERR_INJ                                    , RULL(0x36010A4D), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010A4D,
+REG64( EX_1_L2_FIR_ERR_INJ                                     , RULL(0x22010A4D), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010A4D,
+REG64( EX_2_L2_FIR_ERR_INJ                                     , RULL(0x24010A4D), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010A4D,
+REG64( EX_3_L2_FIR_ERR_INJ                                     , RULL(0x26010A4D), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010A4D,
+REG64( EX_4_L2_FIR_ERR_INJ                                     , RULL(0x28010A4D), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010A4D,
+REG64( EX_5_L2_FIR_ERR_INJ                                     , RULL(0x2A010A4D), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010A4D,
+REG64( EX_6_L2_FIR_ERR_INJ                                     , RULL(0x2C010A4D), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010A4D,
+REG64( EX_7_L2_FIR_ERR_INJ                                     , RULL(0x2E010A4D), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010A4D,
+REG64( EX_8_L2_FIR_ERR_INJ                                     , RULL(0x30010A4D), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010A4D,
+REG64( EX_9_L2_FIR_ERR_INJ                                     , RULL(0x32010A4D), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010A4D,
+REG64( EX_L2_FIR_ERR_INJ                                       , RULL(0x20010A4D), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A4D,
+
+REG64( C_FIR_HOLD_OUT                                          , RULL(0x20010A51), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_FIR_HOLD_OUT                                        , RULL(0x20010A51), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_FIR_HOLD_OUT                                        , RULL(0x21010A51), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_FIR_HOLD_OUT                                        , RULL(0x22010A51), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_FIR_HOLD_OUT                                        , RULL(0x23010A51), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_FIR_HOLD_OUT                                        , RULL(0x24010A51), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_FIR_HOLD_OUT                                        , RULL(0x25010A51), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_FIR_HOLD_OUT                                        , RULL(0x26010A51), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_FIR_HOLD_OUT                                        , RULL(0x27010A51), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_FIR_HOLD_OUT                                        , RULL(0x28010A51), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_FIR_HOLD_OUT                                        , RULL(0x29010A51), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_FIR_HOLD_OUT                                       , RULL(0x2A010A51), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_FIR_HOLD_OUT                                       , RULL(0x2B010A51), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_FIR_HOLD_OUT                                       , RULL(0x2C010A51), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_FIR_HOLD_OUT                                       , RULL(0x2D010A51), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_FIR_HOLD_OUT                                       , RULL(0x2E010A51), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_FIR_HOLD_OUT                                       , RULL(0x2F010A51), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_FIR_HOLD_OUT                                       , RULL(0x30010A51), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_FIR_HOLD_OUT                                       , RULL(0x31010A51), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_FIR_HOLD_OUT                                       , RULL(0x32010A51), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_FIR_HOLD_OUT                                       , RULL(0x33010A51), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_FIR_HOLD_OUT                                       , RULL(0x34010A51), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_FIR_HOLD_OUT                                       , RULL(0x35010A51), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_FIR_HOLD_OUT                                       , RULL(0x36010A51), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_FIR_HOLD_OUT                                       , RULL(0x37010A51), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_0_L2_FIR_HOLD_OUT                                    , RULL(0x20010A51), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010A51,
+REG64( EX_10_L2_FIR_HOLD_OUT                                   , RULL(0x34010A51), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35010A51,
+REG64( EX_11_L2_FIR_HOLD_OUT                                   , RULL(0x36010A51), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37010A51,
+REG64( EX_1_L2_FIR_HOLD_OUT                                    , RULL(0x22010A51), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23010A51,
+REG64( EX_2_L2_FIR_HOLD_OUT                                    , RULL(0x24010A51), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25010A51,
+REG64( EX_3_L2_FIR_HOLD_OUT                                    , RULL(0x26010A51), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27010A51,
+REG64( EX_4_L2_FIR_HOLD_OUT                                    , RULL(0x28010A51), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29010A51,
+REG64( EX_5_L2_FIR_HOLD_OUT                                    , RULL(0x2A010A51), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B010A51,
+REG64( EX_6_L2_FIR_HOLD_OUT                                    , RULL(0x2C010A51), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D010A51,
+REG64( EX_7_L2_FIR_HOLD_OUT                                    , RULL(0x2E010A51), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F010A51,
+REG64( EX_8_L2_FIR_HOLD_OUT                                    , RULL(0x30010A51), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31010A51,
+REG64( EX_9_L2_FIR_HOLD_OUT                                    , RULL(0x32010A51), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33010A51,
+REG64( EX_L2_FIR_HOLD_OUT                                      , RULL(0x20010A51), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010A51,
+
+REG64( C_FIR_MASK                                              , RULL(0x20040002), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_FIR_MASK                                            , RULL(0x20040002), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_FIR_MASK                                            , RULL(0x21040002), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_FIR_MASK                                            , RULL(0x22040002), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_FIR_MASK                                            , RULL(0x23040002), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_FIR_MASK                                            , RULL(0x24040002), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_FIR_MASK                                            , RULL(0x25040002), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_FIR_MASK                                            , RULL(0x26040002), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_FIR_MASK                                            , RULL(0x27040002), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_FIR_MASK                                            , RULL(0x28040002), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_FIR_MASK                                            , RULL(0x29040002), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_FIR_MASK                                           , RULL(0x2A040002), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_FIR_MASK                                           , RULL(0x2B040002), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_FIR_MASK                                           , RULL(0x2C040002), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_FIR_MASK                                           , RULL(0x2D040002), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_FIR_MASK                                           , RULL(0x2E040002), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_FIR_MASK                                           , RULL(0x2F040002), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_FIR_MASK                                           , RULL(0x30040002), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_FIR_MASK                                           , RULL(0x31040002), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_FIR_MASK                                           , RULL(0x32040002), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_FIR_MASK                                           , RULL(0x33040002), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_FIR_MASK                                           , RULL(0x34040002), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_FIR_MASK                                           , RULL(0x35040002), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_FIR_MASK                                           , RULL(0x36040002), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_FIR_MASK                                           , RULL(0x37040002), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_FIR_MASK                                             , RULL(0x10040002), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_FIR_MASK                                           , RULL(0x10040002), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_FIR_MASK                                           , RULL(0x11040002), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_FIR_MASK                                           , RULL(0x12040002), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_FIR_MASK                                           , RULL(0x13040002), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_FIR_MASK                                           , RULL(0x14040002), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_FIR_MASK                                           , RULL(0x15040002), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_FIR_MASK                                             , RULL(0x20040002), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21040002,
+REG64( EX_0_FIR_MASK                                           , RULL(0x20040002), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21040002,
+REG64( EX_1_FIR_MASK                                           , RULL(0x22040002), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23040002,
+REG64( EX_2_FIR_MASK                                           , RULL(0x24040002), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25040002,
+REG64( EX_3_FIR_MASK                                           , RULL(0x26040002), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27040002,
+REG64( EX_4_FIR_MASK                                           , RULL(0x28040002), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29040002,
+REG64( EX_5_FIR_MASK                                           , RULL(0x2A040002), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B040002,
+REG64( EX_6_FIR_MASK                                           , RULL(0x2C040002), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D040002,
+REG64( EX_7_FIR_MASK                                           , RULL(0x2E040002), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F040002,
+REG64( EX_8_FIR_MASK                                           , RULL(0x30040002), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31040002,
+REG64( EX_9_FIR_MASK                                           , RULL(0x32040002), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33040002,
+REG64( EX_10_FIR_MASK                                          , RULL(0x34040002), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35040002,
+REG64( EX_11_FIR_MASK                                          , RULL(0x36040002), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37040002,
+
+REG64( EQ_FIR_MASK_REG                                         , RULL(0x10010803), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10011803, 10011003, 10010C03, 10011C03, 10011403,
+REG64( EQ_FIR_MASK_REG_AND                                     , RULL(0x10010804), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_AND ); //DUPS: 10011804, 10011004, 10010C04, 10011C04, 10011404,
+REG64( EQ_FIR_MASK_REG_OR                                      , RULL(0x10010805), SH_UNT_EQ       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 10011805, 10011005, 10010C05, 10011C05, 10011405,
+REG64( EQ_0_FIR_MASK_REG                                       , RULL(0x10010803), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10011803, 10011003, 10010C03, 10011C03, 10011403,
+REG64( EQ_0_FIR_MASK_REG_AND                                   , RULL(0x10010804), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 10011804, 10011004, 10010C04, 10011C04, 10011404,
+REG64( EQ_0_FIR_MASK_REG_OR                                    , RULL(0x10010805), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 10011805, 10011005, 10010C05, 10011C05, 10011405,
+REG64( EQ_1_FIR_MASK_REG                                       , RULL(0x11010803), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11011803, 11011003, 11010C03, 11011C03, 11011403,
+REG64( EQ_1_FIR_MASK_REG_AND                                   , RULL(0x11010804), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 11011804, 11011004, 11010C04, 11011C04, 11011404,
+REG64( EQ_1_FIR_MASK_REG_OR                                    , RULL(0x11010805), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 11011805, 11011005, 11010C05, 11011C05, 11011405,
+REG64( EQ_2_FIR_MASK_REG                                       , RULL(0x12010803), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12011803, 12011003, 12010C03, 12011C03, 12011403,
+REG64( EQ_2_FIR_MASK_REG_AND                                   , RULL(0x12010804), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 12011804, 12011004, 12010C04, 12011C04, 12011404,
+REG64( EQ_2_FIR_MASK_REG_OR                                    , RULL(0x12010805), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 12011805, 12011005, 12010C05, 12011C05, 12011405,
+REG64( EQ_3_FIR_MASK_REG                                       , RULL(0x13010803), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13011803, 13011003, 13010C03, 13011C03, 13011403,
+REG64( EQ_3_FIR_MASK_REG_AND                                   , RULL(0x13010804), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 13011804, 13011004, 13010C04, 13011C04, 13011404,
+REG64( EQ_3_FIR_MASK_REG_OR                                    , RULL(0x13010805), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 13011805, 13011005, 13010C05, 13011C05, 13011405,
+REG64( EQ_4_FIR_MASK_REG                                       , RULL(0x14010803), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14011803, 14011003, 14010C03, 14011C03, 14011403,
+REG64( EQ_4_FIR_MASK_REG_AND                                   , RULL(0x14010804), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 14011804, 14011004, 14010C04, 14011C04, 14011404,
+REG64( EQ_4_FIR_MASK_REG_OR                                    , RULL(0x14010805), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 14011805, 14011005, 14010C05, 14011C05, 14011405,
+REG64( EQ_5_FIR_MASK_REG                                       , RULL(0x15010803), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15011803, 15011003, 15010C03, 15011C03, 15011403,
+REG64( EQ_5_FIR_MASK_REG_AND                                   , RULL(0x15010804), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 15011804, 15011004, 15010C04, 15011C04, 15011404,
+REG64( EQ_5_FIR_MASK_REG_OR                                    , RULL(0x15010805), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 15011805, 15011005, 15010C05, 15011C05, 15011405,
+REG64( EX_FIR_MASK_REG                                         , RULL(0x10011003), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_FIR_MASK_REG_AND                                     , RULL(0x10011004), SH_UNT_EX       , SH_ACS_SCOM1_AND );
+REG64( EX_FIR_MASK_REG_OR                                      , RULL(0x10011005), SH_UNT_EX       , SH_ACS_SCOM2_OR  );
+REG64( EX_0_FIR_MASK_REG                                       , RULL(0x10011003), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_0_FIR_MASK_REG_AND                                   , RULL(0x10011004), SH_UNT_EX_0     , SH_ACS_SCOM1_AND );
+REG64( EX_0_FIR_MASK_REG_OR                                    , RULL(0x10011005), SH_UNT_EX_0     , SH_ACS_SCOM2_OR  );
+REG64( EX_1_FIR_MASK_REG                                       , RULL(0x10011403), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_1_FIR_MASK_REG_AND                                   , RULL(0x10011404), SH_UNT_EX_1     , SH_ACS_SCOM1_AND );
+REG64( EX_1_FIR_MASK_REG_OR                                    , RULL(0x10011405), SH_UNT_EX_1     , SH_ACS_SCOM2_OR  );
+REG64( EX_2_FIR_MASK_REG                                       , RULL(0x11011003), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_2_FIR_MASK_REG_AND                                   , RULL(0x11011004), SH_UNT_EX_2     , SH_ACS_SCOM1_AND );
+REG64( EX_2_FIR_MASK_REG_OR                                    , RULL(0x11011005), SH_UNT_EX_2     , SH_ACS_SCOM2_OR  );
+REG64( EX_3_FIR_MASK_REG                                       , RULL(0x11011403), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_3_FIR_MASK_REG_AND                                   , RULL(0x11011404), SH_UNT_EX_3     , SH_ACS_SCOM1_AND );
+REG64( EX_3_FIR_MASK_REG_OR                                    , RULL(0x11011405), SH_UNT_EX_3     , SH_ACS_SCOM2_OR  );
+REG64( EX_4_FIR_MASK_REG                                       , RULL(0x12011003), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_4_FIR_MASK_REG_AND                                   , RULL(0x12011004), SH_UNT_EX_4     , SH_ACS_SCOM1_AND );
+REG64( EX_4_FIR_MASK_REG_OR                                    , RULL(0x12011005), SH_UNT_EX_4     , SH_ACS_SCOM2_OR  );
+REG64( EX_5_FIR_MASK_REG                                       , RULL(0x12011403), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_5_FIR_MASK_REG_AND                                   , RULL(0x12011404), SH_UNT_EX_5     , SH_ACS_SCOM1_AND );
+REG64( EX_5_FIR_MASK_REG_OR                                    , RULL(0x12011405), SH_UNT_EX_5     , SH_ACS_SCOM2_OR  );
+REG64( EX_6_FIR_MASK_REG                                       , RULL(0x13011003), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_6_FIR_MASK_REG_AND                                   , RULL(0x13011004), SH_UNT_EX_6     , SH_ACS_SCOM1_AND );
+REG64( EX_6_FIR_MASK_REG_OR                                    , RULL(0x13011005), SH_UNT_EX_6     , SH_ACS_SCOM2_OR  );
+REG64( EX_7_FIR_MASK_REG                                       , RULL(0x13011403), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_7_FIR_MASK_REG_AND                                   , RULL(0x13011404), SH_UNT_EX_7     , SH_ACS_SCOM1_AND );
+REG64( EX_7_FIR_MASK_REG_OR                                    , RULL(0x13011405), SH_UNT_EX_7     , SH_ACS_SCOM2_OR  );
+REG64( EX_8_FIR_MASK_REG                                       , RULL(0x14011003), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_8_FIR_MASK_REG_AND                                   , RULL(0x14011004), SH_UNT_EX_8     , SH_ACS_SCOM1_AND );
+REG64( EX_8_FIR_MASK_REG_OR                                    , RULL(0x14011005), SH_UNT_EX_8     , SH_ACS_SCOM2_OR  );
+REG64( EX_9_FIR_MASK_REG                                       , RULL(0x14011403), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_9_FIR_MASK_REG_AND                                   , RULL(0x14011404), SH_UNT_EX_9     , SH_ACS_SCOM1_AND );
+REG64( EX_9_FIR_MASK_REG_OR                                    , RULL(0x14011405), SH_UNT_EX_9     , SH_ACS_SCOM2_OR  );
+REG64( EX_0_L2_FIR_MASK_REG                                    , RULL(0x10010803), SH_UNT_EX_0_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_FIR_MASK_REG_AND                                , RULL(0x10010804), SH_UNT_EX_0_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_0_L2_FIR_MASK_REG_OR                                 , RULL(0x10010805), SH_UNT_EX_0_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_0_L3_FIR_MASK_REG                                    , RULL(0x10011803), SH_UNT_EX_0_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_0_L3_FIR_MASK_REG_AND                                , RULL(0x10011804), SH_UNT_EX_0_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_0_L3_FIR_MASK_REG_OR                                 , RULL(0x10011805), SH_UNT_EX_0_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_10_FIR_MASK_REG                                      , RULL(0x15011003), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_10_FIR_MASK_REG_AND                                  , RULL(0x15011004), SH_UNT_EX_10    , SH_ACS_SCOM1_AND );
+REG64( EX_10_FIR_MASK_REG_OR                                   , RULL(0x15011005), SH_UNT_EX_10    , SH_ACS_SCOM2_OR  );
+REG64( EX_11_FIR_MASK_REG                                      , RULL(0x15011403), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+REG64( EX_11_FIR_MASK_REG_AND                                  , RULL(0x15011404), SH_UNT_EX_11    , SH_ACS_SCOM1_AND );
+REG64( EX_11_FIR_MASK_REG_OR                                   , RULL(0x15011405), SH_UNT_EX_11    , SH_ACS_SCOM2_OR  );
+REG64( EX_10_L2_FIR_MASK_REG                                   , RULL(0x15010803), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RW   );
+REG64( EX_10_L2_FIR_MASK_REG_AND                               , RULL(0x15010804), SH_UNT_EX_10_L2 , SH_ACS_SCOM1_AND );
+REG64( EX_10_L2_FIR_MASK_REG_OR                                , RULL(0x15010805), SH_UNT_EX_10_L2 , SH_ACS_SCOM2_OR  );
+REG64( EX_10_L3_FIR_MASK_REG                                   , RULL(0x15011803), SH_UNT_EX_10_L3 , SH_ACS_SCOM_RW   );
+REG64( EX_10_L3_FIR_MASK_REG_AND                               , RULL(0x15011804), SH_UNT_EX_10_L3 , SH_ACS_SCOM1_AND );
+REG64( EX_10_L3_FIR_MASK_REG_OR                                , RULL(0x15011805), SH_UNT_EX_10_L3 , SH_ACS_SCOM2_OR  );
+REG64( EX_11_L2_FIR_MASK_REG                                   , RULL(0x15010C03), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RW   );
+REG64( EX_11_L2_FIR_MASK_REG_AND                               , RULL(0x15010C04), SH_UNT_EX_11_L2 , SH_ACS_SCOM1_AND );
+REG64( EX_11_L2_FIR_MASK_REG_OR                                , RULL(0x15010C05), SH_UNT_EX_11_L2 , SH_ACS_SCOM2_OR  );
+REG64( EX_11_L3_FIR_MASK_REG                                   , RULL(0x15011C03), SH_UNT_EX_11_L3 , SH_ACS_SCOM_RW   );
+REG64( EX_11_L3_FIR_MASK_REG_AND                               , RULL(0x15011C04), SH_UNT_EX_11_L3 , SH_ACS_SCOM1_AND );
+REG64( EX_11_L3_FIR_MASK_REG_OR                                , RULL(0x15011C05), SH_UNT_EX_11_L3 , SH_ACS_SCOM2_OR  );
+REG64( EX_1_L2_FIR_MASK_REG                                    , RULL(0x10010C03), SH_UNT_EX_1_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_1_L2_FIR_MASK_REG_AND                                , RULL(0x10010C04), SH_UNT_EX_1_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_1_L2_FIR_MASK_REG_OR                                 , RULL(0x10010C05), SH_UNT_EX_1_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_1_L3_FIR_MASK_REG                                    , RULL(0x10011C03), SH_UNT_EX_1_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_1_L3_FIR_MASK_REG_AND                                , RULL(0x10011C04), SH_UNT_EX_1_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_1_L3_FIR_MASK_REG_OR                                 , RULL(0x10011C05), SH_UNT_EX_1_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_2_L2_FIR_MASK_REG                                    , RULL(0x11010803), SH_UNT_EX_2_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_2_L2_FIR_MASK_REG_AND                                , RULL(0x11010804), SH_UNT_EX_2_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_2_L2_FIR_MASK_REG_OR                                 , RULL(0x11010805), SH_UNT_EX_2_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_2_L3_FIR_MASK_REG                                    , RULL(0x11011803), SH_UNT_EX_2_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_2_L3_FIR_MASK_REG_AND                                , RULL(0x11011804), SH_UNT_EX_2_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_2_L3_FIR_MASK_REG_OR                                 , RULL(0x11011805), SH_UNT_EX_2_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_3_L2_FIR_MASK_REG                                    , RULL(0x11010C03), SH_UNT_EX_3_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_3_L2_FIR_MASK_REG_AND                                , RULL(0x11010C04), SH_UNT_EX_3_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_3_L2_FIR_MASK_REG_OR                                 , RULL(0x11010C05), SH_UNT_EX_3_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_3_L3_FIR_MASK_REG                                    , RULL(0x11011C03), SH_UNT_EX_3_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_3_L3_FIR_MASK_REG_AND                                , RULL(0x11011C04), SH_UNT_EX_3_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_3_L3_FIR_MASK_REG_OR                                 , RULL(0x11011C05), SH_UNT_EX_3_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_4_L2_FIR_MASK_REG                                    , RULL(0x12010803), SH_UNT_EX_4_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_4_L2_FIR_MASK_REG_AND                                , RULL(0x12010804), SH_UNT_EX_4_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_4_L2_FIR_MASK_REG_OR                                 , RULL(0x12010805), SH_UNT_EX_4_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_4_L3_FIR_MASK_REG                                    , RULL(0x12011803), SH_UNT_EX_4_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_4_L3_FIR_MASK_REG_AND                                , RULL(0x12011804), SH_UNT_EX_4_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_4_L3_FIR_MASK_REG_OR                                 , RULL(0x12011805), SH_UNT_EX_4_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_5_L2_FIR_MASK_REG                                    , RULL(0x12010C03), SH_UNT_EX_5_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_5_L2_FIR_MASK_REG_AND                                , RULL(0x12010C04), SH_UNT_EX_5_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_5_L2_FIR_MASK_REG_OR                                 , RULL(0x12010C05), SH_UNT_EX_5_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_5_L3_FIR_MASK_REG                                    , RULL(0x12011C03), SH_UNT_EX_5_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_5_L3_FIR_MASK_REG_AND                                , RULL(0x12011C04), SH_UNT_EX_5_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_5_L3_FIR_MASK_REG_OR                                 , RULL(0x12011C05), SH_UNT_EX_5_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_6_L2_FIR_MASK_REG                                    , RULL(0x13010803), SH_UNT_EX_6_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_6_L2_FIR_MASK_REG_AND                                , RULL(0x13010804), SH_UNT_EX_6_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_6_L2_FIR_MASK_REG_OR                                 , RULL(0x13010805), SH_UNT_EX_6_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_6_L3_FIR_MASK_REG                                    , RULL(0x13011803), SH_UNT_EX_6_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_6_L3_FIR_MASK_REG_AND                                , RULL(0x13011804), SH_UNT_EX_6_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_6_L3_FIR_MASK_REG_OR                                 , RULL(0x13011805), SH_UNT_EX_6_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_7_L2_FIR_MASK_REG                                    , RULL(0x13010C03), SH_UNT_EX_7_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_7_L2_FIR_MASK_REG_AND                                , RULL(0x13010C04), SH_UNT_EX_7_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_7_L2_FIR_MASK_REG_OR                                 , RULL(0x13010C05), SH_UNT_EX_7_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_7_L3_FIR_MASK_REG                                    , RULL(0x13011C03), SH_UNT_EX_7_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_7_L3_FIR_MASK_REG_AND                                , RULL(0x13011C04), SH_UNT_EX_7_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_7_L3_FIR_MASK_REG_OR                                 , RULL(0x13011C05), SH_UNT_EX_7_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_8_L2_FIR_MASK_REG                                    , RULL(0x14010803), SH_UNT_EX_8_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_8_L2_FIR_MASK_REG_AND                                , RULL(0x14010804), SH_UNT_EX_8_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_8_L2_FIR_MASK_REG_OR                                 , RULL(0x14010805), SH_UNT_EX_8_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_8_L3_FIR_MASK_REG                                    , RULL(0x14011803), SH_UNT_EX_8_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_8_L3_FIR_MASK_REG_AND                                , RULL(0x14011804), SH_UNT_EX_8_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_8_L3_FIR_MASK_REG_OR                                 , RULL(0x14011805), SH_UNT_EX_8_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_9_L2_FIR_MASK_REG                                    , RULL(0x14010C03), SH_UNT_EX_9_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_9_L2_FIR_MASK_REG_AND                                , RULL(0x14010C04), SH_UNT_EX_9_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_9_L2_FIR_MASK_REG_OR                                 , RULL(0x14010C05), SH_UNT_EX_9_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_9_L3_FIR_MASK_REG                                    , RULL(0x14011C03), SH_UNT_EX_9_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_9_L3_FIR_MASK_REG_AND                                , RULL(0x14011C04), SH_UNT_EX_9_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_9_L3_FIR_MASK_REG_OR                                 , RULL(0x14011C05), SH_UNT_EX_9_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_L2_FIR_MASK_REG                                      , RULL(0x10010803), SH_UNT_EX_L2    , SH_ACS_SCOM_RW   );
+REG64( EX_L2_FIR_MASK_REG_AND                                  , RULL(0x10010804), SH_UNT_EX_L2    , SH_ACS_SCOM1_AND );
+REG64( EX_L2_FIR_MASK_REG_OR                                   , RULL(0x10010805), SH_UNT_EX_L2    , SH_ACS_SCOM2_OR  );
+REG64( EX_L3_FIR_MASK_REG                                      , RULL(0x10011803), SH_UNT_EX_L3    , SH_ACS_SCOM_RW   );
+REG64( EX_L3_FIR_MASK_REG_AND                                  , RULL(0x10011804), SH_UNT_EX_L3    , SH_ACS_SCOM1_AND );
+REG64( EX_L3_FIR_MASK_REG_OR                                   , RULL(0x10011805), SH_UNT_EX_L3    , SH_ACS_SCOM2_OR  );
+
+REG64( EQ_FIR_REG                                              , RULL(0x10010800), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10011800, 10011000, 10010C00, 10011C00, 10011400,
+REG64( EQ_FIR_REG_AND                                          , RULL(0x10010801), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_AND ); //DUPS: 10011801, 10011001, 10010C01, 10011C01, 10011401,
+REG64( EQ_FIR_REG_OR                                           , RULL(0x10010802), SH_UNT_EQ       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 10011802, 10011002, 10010C02, 10011C02, 10011402,
+REG64( EQ_0_FIR_REG                                            , RULL(0x10010800), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10011800, 10011000, 10010C00, 10011C00, 10011400,
+REG64( EQ_0_FIR_REG_AND                                        , RULL(0x10010801), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 10011801, 10011001, 10010C01, 10011C01, 10011401,
+REG64( EQ_0_FIR_REG_OR                                         , RULL(0x10010802), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 10011802, 10011002, 10010C02, 10011C02, 10011402,
+REG64( EQ_1_FIR_REG                                            , RULL(0x11010800), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11011800, 11011000, 11010C00, 11011C00, 11011400,
+REG64( EQ_1_FIR_REG_AND                                        , RULL(0x11010801), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 11011801, 11011001, 11010C01, 11011C01, 11011401,
+REG64( EQ_1_FIR_REG_OR                                         , RULL(0x11010802), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 11011802, 11011002, 11010C02, 11011C02, 11011402,
+REG64( EQ_2_FIR_REG                                            , RULL(0x12010800), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12011800, 12011000, 12010C00, 12011C00, 12011400,
+REG64( EQ_2_FIR_REG_AND                                        , RULL(0x12010801), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 12011801, 12011001, 12010C01, 12011C01, 12011401,
+REG64( EQ_2_FIR_REG_OR                                         , RULL(0x12010802), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 12011802, 12011002, 12010C02, 12011C02, 12011402,
+REG64( EQ_3_FIR_REG                                            , RULL(0x13010800), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13011800, 13011000, 13010C00, 13011C00, 13011400,
+REG64( EQ_3_FIR_REG_AND                                        , RULL(0x13010801), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 13011801, 13011001, 13010C01, 13011C01, 13011401,
+REG64( EQ_3_FIR_REG_OR                                         , RULL(0x13010802), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 13011802, 13011002, 13010C02, 13011C02, 13011402,
+REG64( EQ_4_FIR_REG                                            , RULL(0x14010800), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14011800, 14011000, 14010C00, 14011C00, 14011400,
+REG64( EQ_4_FIR_REG_AND                                        , RULL(0x14010801), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 14011801, 14011001, 14010C01, 14011C01, 14011401,
+REG64( EQ_4_FIR_REG_OR                                         , RULL(0x14010802), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 14011802, 14011002, 14010C02, 14011C02, 14011402,
+REG64( EQ_5_FIR_REG                                            , RULL(0x15010800), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15011800, 15011000, 15010C00, 15011C00, 15011400,
+REG64( EQ_5_FIR_REG_AND                                        , RULL(0x15010801), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 15011801, 15011001, 15010C01, 15011C01, 15011401,
+REG64( EQ_5_FIR_REG_OR                                         , RULL(0x15010802), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 15011802, 15011002, 15010C02, 15011C02, 15011402,
+REG64( EX_FIR_REG                                              , RULL(0x10011000), SH_UNT_EX       , SH_ACS_SCOM_RW   );
+REG64( EX_FIR_REG_AND                                          , RULL(0x10011001), SH_UNT_EX       , SH_ACS_SCOM1_AND );
+REG64( EX_FIR_REG_OR                                           , RULL(0x10011002), SH_UNT_EX       , SH_ACS_SCOM2_OR  );
+REG64( EX_0_FIR_REG                                            , RULL(0x10011000), SH_UNT_EX_0     , SH_ACS_SCOM_RW   );
+REG64( EX_0_FIR_REG_AND                                        , RULL(0x10011001), SH_UNT_EX_0     , SH_ACS_SCOM1_AND );
+REG64( EX_0_FIR_REG_OR                                         , RULL(0x10011002), SH_UNT_EX_0     , SH_ACS_SCOM2_OR  );
+REG64( EX_1_FIR_REG                                            , RULL(0x10011400), SH_UNT_EX_1     , SH_ACS_SCOM_RW   );
+REG64( EX_1_FIR_REG_AND                                        , RULL(0x10011401), SH_UNT_EX_1     , SH_ACS_SCOM1_AND );
+REG64( EX_1_FIR_REG_OR                                         , RULL(0x10011402), SH_UNT_EX_1     , SH_ACS_SCOM2_OR  );
+REG64( EX_2_FIR_REG                                            , RULL(0x11011000), SH_UNT_EX_2     , SH_ACS_SCOM_RW   );
+REG64( EX_2_FIR_REG_AND                                        , RULL(0x11011001), SH_UNT_EX_2     , SH_ACS_SCOM1_AND );
+REG64( EX_2_FIR_REG_OR                                         , RULL(0x11011002), SH_UNT_EX_2     , SH_ACS_SCOM2_OR  );
+REG64( EX_3_FIR_REG                                            , RULL(0x11011400), SH_UNT_EX_3     , SH_ACS_SCOM_RW   );
+REG64( EX_3_FIR_REG_AND                                        , RULL(0x11011401), SH_UNT_EX_3     , SH_ACS_SCOM1_AND );
+REG64( EX_3_FIR_REG_OR                                         , RULL(0x11011402), SH_UNT_EX_3     , SH_ACS_SCOM2_OR  );
+REG64( EX_4_FIR_REG                                            , RULL(0x12011000), SH_UNT_EX_4     , SH_ACS_SCOM_RW   );
+REG64( EX_4_FIR_REG_AND                                        , RULL(0x12011001), SH_UNT_EX_4     , SH_ACS_SCOM1_AND );
+REG64( EX_4_FIR_REG_OR                                         , RULL(0x12011002), SH_UNT_EX_4     , SH_ACS_SCOM2_OR  );
+REG64( EX_5_FIR_REG                                            , RULL(0x12011400), SH_UNT_EX_5     , SH_ACS_SCOM_RW   );
+REG64( EX_5_FIR_REG_AND                                        , RULL(0x12011401), SH_UNT_EX_5     , SH_ACS_SCOM1_AND );
+REG64( EX_5_FIR_REG_OR                                         , RULL(0x12011402), SH_UNT_EX_5     , SH_ACS_SCOM2_OR  );
+REG64( EX_6_FIR_REG                                            , RULL(0x13011000), SH_UNT_EX_6     , SH_ACS_SCOM_RW   );
+REG64( EX_6_FIR_REG_AND                                        , RULL(0x13011001), SH_UNT_EX_6     , SH_ACS_SCOM1_AND );
+REG64( EX_6_FIR_REG_OR                                         , RULL(0x13011002), SH_UNT_EX_6     , SH_ACS_SCOM2_OR  );
+REG64( EX_7_FIR_REG                                            , RULL(0x13011400), SH_UNT_EX_7     , SH_ACS_SCOM_RW   );
+REG64( EX_7_FIR_REG_AND                                        , RULL(0x13011401), SH_UNT_EX_7     , SH_ACS_SCOM1_AND );
+REG64( EX_7_FIR_REG_OR                                         , RULL(0x13011402), SH_UNT_EX_7     , SH_ACS_SCOM2_OR  );
+REG64( EX_8_FIR_REG                                            , RULL(0x14011000), SH_UNT_EX_8     , SH_ACS_SCOM_RW   );
+REG64( EX_8_FIR_REG_AND                                        , RULL(0x14011001), SH_UNT_EX_8     , SH_ACS_SCOM1_AND );
+REG64( EX_8_FIR_REG_OR                                         , RULL(0x14011002), SH_UNT_EX_8     , SH_ACS_SCOM2_OR  );
+REG64( EX_9_FIR_REG                                            , RULL(0x14011400), SH_UNT_EX_9     , SH_ACS_SCOM_RW   );
+REG64( EX_9_FIR_REG_AND                                        , RULL(0x14011401), SH_UNT_EX_9     , SH_ACS_SCOM1_AND );
+REG64( EX_9_FIR_REG_OR                                         , RULL(0x14011402), SH_UNT_EX_9     , SH_ACS_SCOM2_OR  );
+REG64( EX_0_L2_FIR_REG                                         , RULL(0x10010800), SH_UNT_EX_0_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_FIR_REG_AND                                     , RULL(0x10010801), SH_UNT_EX_0_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_0_L2_FIR_REG_OR                                      , RULL(0x10010802), SH_UNT_EX_0_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_0_L3_FIR_REG                                         , RULL(0x10011800), SH_UNT_EX_0_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_0_L3_FIR_REG_AND                                     , RULL(0x10011801), SH_UNT_EX_0_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_0_L3_FIR_REG_OR                                      , RULL(0x10011802), SH_UNT_EX_0_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_10_FIR_REG                                           , RULL(0x15011000), SH_UNT_EX_10    , SH_ACS_SCOM_RW   );
+REG64( EX_10_FIR_REG_AND                                       , RULL(0x15011001), SH_UNT_EX_10    , SH_ACS_SCOM1_AND );
+REG64( EX_10_FIR_REG_OR                                        , RULL(0x15011002), SH_UNT_EX_10    , SH_ACS_SCOM2_OR  );
+REG64( EX_11_FIR_REG                                           , RULL(0x15011400), SH_UNT_EX_11    , SH_ACS_SCOM_RW   );
+REG64( EX_11_FIR_REG_AND                                       , RULL(0x15011401), SH_UNT_EX_11    , SH_ACS_SCOM1_AND );
+REG64( EX_11_FIR_REG_OR                                        , RULL(0x15011402), SH_UNT_EX_11    , SH_ACS_SCOM2_OR  );
+REG64( EX_10_L2_FIR_REG                                        , RULL(0x15010800), SH_UNT_EX_10_L2 , SH_ACS_SCOM_RW   );
+REG64( EX_10_L2_FIR_REG_AND                                    , RULL(0x15010801), SH_UNT_EX_10_L2 , SH_ACS_SCOM1_AND );
+REG64( EX_10_L2_FIR_REG_OR                                     , RULL(0x15010802), SH_UNT_EX_10_L2 , SH_ACS_SCOM2_OR  );
+REG64( EX_10_L3_FIR_REG                                        , RULL(0x15011800), SH_UNT_EX_10_L3 , SH_ACS_SCOM_RW   );
+REG64( EX_10_L3_FIR_REG_AND                                    , RULL(0x15011801), SH_UNT_EX_10_L3 , SH_ACS_SCOM1_AND );
+REG64( EX_10_L3_FIR_REG_OR                                     , RULL(0x15011802), SH_UNT_EX_10_L3 , SH_ACS_SCOM2_OR  );
+REG64( EX_11_L2_FIR_REG                                        , RULL(0x15010C00), SH_UNT_EX_11_L2 , SH_ACS_SCOM_RW   );
+REG64( EX_11_L2_FIR_REG_AND                                    , RULL(0x15010C01), SH_UNT_EX_11_L2 , SH_ACS_SCOM1_AND );
+REG64( EX_11_L2_FIR_REG_OR                                     , RULL(0x15010C02), SH_UNT_EX_11_L2 , SH_ACS_SCOM2_OR  );
+REG64( EX_11_L3_FIR_REG                                        , RULL(0x15011C00), SH_UNT_EX_11_L3 , SH_ACS_SCOM_RW   );
+REG64( EX_11_L3_FIR_REG_AND                                    , RULL(0x15011C01), SH_UNT_EX_11_L3 , SH_ACS_SCOM1_AND );
+REG64( EX_11_L3_FIR_REG_OR                                     , RULL(0x15011C02), SH_UNT_EX_11_L3 , SH_ACS_SCOM2_OR  );
+REG64( EX_1_L2_FIR_REG                                         , RULL(0x10010C00), SH_UNT_EX_1_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_1_L2_FIR_REG_AND                                     , RULL(0x10010C01), SH_UNT_EX_1_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_1_L2_FIR_REG_OR                                      , RULL(0x10010C02), SH_UNT_EX_1_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_1_L3_FIR_REG                                         , RULL(0x10011C00), SH_UNT_EX_1_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_1_L3_FIR_REG_AND                                     , RULL(0x10011C01), SH_UNT_EX_1_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_1_L3_FIR_REG_OR                                      , RULL(0x10011C02), SH_UNT_EX_1_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_2_L2_FIR_REG                                         , RULL(0x11010800), SH_UNT_EX_2_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_2_L2_FIR_REG_AND                                     , RULL(0x11010801), SH_UNT_EX_2_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_2_L2_FIR_REG_OR                                      , RULL(0x11010802), SH_UNT_EX_2_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_2_L3_FIR_REG                                         , RULL(0x11011800), SH_UNT_EX_2_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_2_L3_FIR_REG_AND                                     , RULL(0x11011801), SH_UNT_EX_2_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_2_L3_FIR_REG_OR                                      , RULL(0x11011802), SH_UNT_EX_2_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_3_L2_FIR_REG                                         , RULL(0x11010C00), SH_UNT_EX_3_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_3_L2_FIR_REG_AND                                     , RULL(0x11010C01), SH_UNT_EX_3_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_3_L2_FIR_REG_OR                                      , RULL(0x11010C02), SH_UNT_EX_3_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_3_L3_FIR_REG                                         , RULL(0x11011C00), SH_UNT_EX_3_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_3_L3_FIR_REG_AND                                     , RULL(0x11011C01), SH_UNT_EX_3_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_3_L3_FIR_REG_OR                                      , RULL(0x11011C02), SH_UNT_EX_3_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_4_L2_FIR_REG                                         , RULL(0x12010800), SH_UNT_EX_4_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_4_L2_FIR_REG_AND                                     , RULL(0x12010801), SH_UNT_EX_4_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_4_L2_FIR_REG_OR                                      , RULL(0x12010802), SH_UNT_EX_4_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_4_L3_FIR_REG                                         , RULL(0x12011800), SH_UNT_EX_4_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_4_L3_FIR_REG_AND                                     , RULL(0x12011801), SH_UNT_EX_4_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_4_L3_FIR_REG_OR                                      , RULL(0x12011802), SH_UNT_EX_4_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_5_L2_FIR_REG                                         , RULL(0x12010C00), SH_UNT_EX_5_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_5_L2_FIR_REG_AND                                     , RULL(0x12010C01), SH_UNT_EX_5_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_5_L2_FIR_REG_OR                                      , RULL(0x12010C02), SH_UNT_EX_5_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_5_L3_FIR_REG                                         , RULL(0x12011C00), SH_UNT_EX_5_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_5_L3_FIR_REG_AND                                     , RULL(0x12011C01), SH_UNT_EX_5_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_5_L3_FIR_REG_OR                                      , RULL(0x12011C02), SH_UNT_EX_5_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_6_L2_FIR_REG                                         , RULL(0x13010800), SH_UNT_EX_6_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_6_L2_FIR_REG_AND                                     , RULL(0x13010801), SH_UNT_EX_6_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_6_L2_FIR_REG_OR                                      , RULL(0x13010802), SH_UNT_EX_6_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_6_L3_FIR_REG                                         , RULL(0x13011800), SH_UNT_EX_6_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_6_L3_FIR_REG_AND                                     , RULL(0x13011801), SH_UNT_EX_6_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_6_L3_FIR_REG_OR                                      , RULL(0x13011802), SH_UNT_EX_6_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_7_L2_FIR_REG                                         , RULL(0x13010C00), SH_UNT_EX_7_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_7_L2_FIR_REG_AND                                     , RULL(0x13010C01), SH_UNT_EX_7_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_7_L2_FIR_REG_OR                                      , RULL(0x13010C02), SH_UNT_EX_7_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_7_L3_FIR_REG                                         , RULL(0x13011C00), SH_UNT_EX_7_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_7_L3_FIR_REG_AND                                     , RULL(0x13011C01), SH_UNT_EX_7_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_7_L3_FIR_REG_OR                                      , RULL(0x13011C02), SH_UNT_EX_7_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_8_L2_FIR_REG                                         , RULL(0x14010800), SH_UNT_EX_8_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_8_L2_FIR_REG_AND                                     , RULL(0x14010801), SH_UNT_EX_8_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_8_L2_FIR_REG_OR                                      , RULL(0x14010802), SH_UNT_EX_8_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_8_L3_FIR_REG                                         , RULL(0x14011800), SH_UNT_EX_8_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_8_L3_FIR_REG_AND                                     , RULL(0x14011801), SH_UNT_EX_8_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_8_L3_FIR_REG_OR                                      , RULL(0x14011802), SH_UNT_EX_8_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_9_L2_FIR_REG                                         , RULL(0x14010C00), SH_UNT_EX_9_L2  , SH_ACS_SCOM_RW   );
+REG64( EX_9_L2_FIR_REG_AND                                     , RULL(0x14010C01), SH_UNT_EX_9_L2  , SH_ACS_SCOM1_AND );
+REG64( EX_9_L2_FIR_REG_OR                                      , RULL(0x14010C02), SH_UNT_EX_9_L2  , SH_ACS_SCOM2_OR  );
+REG64( EX_9_L3_FIR_REG                                         , RULL(0x14011C00), SH_UNT_EX_9_L3  , SH_ACS_SCOM_RW   );
+REG64( EX_9_L3_FIR_REG_AND                                     , RULL(0x14011C01), SH_UNT_EX_9_L3  , SH_ACS_SCOM1_AND );
+REG64( EX_9_L3_FIR_REG_OR                                      , RULL(0x14011C02), SH_UNT_EX_9_L3  , SH_ACS_SCOM2_OR  );
+REG64( EX_L2_FIR_REG                                           , RULL(0x10010800), SH_UNT_EX_L2    , SH_ACS_SCOM_RW   );
+REG64( EX_L2_FIR_REG_AND                                       , RULL(0x10010801), SH_UNT_EX_L2    , SH_ACS_SCOM1_AND );
+REG64( EX_L2_FIR_REG_OR                                        , RULL(0x10010802), SH_UNT_EX_L2    , SH_ACS_SCOM2_OR  );
+REG64( EX_L3_FIR_REG                                           , RULL(0x10011800), SH_UNT_EX_L3    , SH_ACS_SCOM_RW   );
+REG64( EX_L3_FIR_REG_AND                                       , RULL(0x10011801), SH_UNT_EX_L3    , SH_ACS_SCOM1_AND );
+REG64( EX_L3_FIR_REG_OR                                        , RULL(0x10011802), SH_UNT_EX_L3    , SH_ACS_SCOM2_OR  );
+
+REG64( C_GXSTOP0_MASK_REG                                      , RULL(0x20040014), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_GXSTOP0_MASK_REG                                    , RULL(0x20040014), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_GXSTOP0_MASK_REG                                    , RULL(0x21040014), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_GXSTOP0_MASK_REG                                    , RULL(0x22040014), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_GXSTOP0_MASK_REG                                    , RULL(0x23040014), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_GXSTOP0_MASK_REG                                    , RULL(0x24040014), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_GXSTOP0_MASK_REG                                    , RULL(0x25040014), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_GXSTOP0_MASK_REG                                    , RULL(0x26040014), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_GXSTOP0_MASK_REG                                    , RULL(0x27040014), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_GXSTOP0_MASK_REG                                    , RULL(0x28040014), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_GXSTOP0_MASK_REG                                    , RULL(0x29040014), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_GXSTOP0_MASK_REG                                   , RULL(0x2A040014), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_GXSTOP0_MASK_REG                                   , RULL(0x2B040014), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_GXSTOP0_MASK_REG                                   , RULL(0x2C040014), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_GXSTOP0_MASK_REG                                   , RULL(0x2D040014), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_GXSTOP0_MASK_REG                                   , RULL(0x2E040014), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_GXSTOP0_MASK_REG                                   , RULL(0x2F040014), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_GXSTOP0_MASK_REG                                   , RULL(0x30040014), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_GXSTOP0_MASK_REG                                   , RULL(0x31040014), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_GXSTOP0_MASK_REG                                   , RULL(0x32040014), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_GXSTOP0_MASK_REG                                   , RULL(0x33040014), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_GXSTOP0_MASK_REG                                   , RULL(0x34040014), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_GXSTOP0_MASK_REG                                   , RULL(0x35040014), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_GXSTOP0_MASK_REG                                   , RULL(0x36040014), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_GXSTOP0_MASK_REG                                   , RULL(0x37040014), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_GXSTOP0_MASK_REG                                     , RULL(0x10040014), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_GXSTOP0_MASK_REG                                   , RULL(0x10040014), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_GXSTOP0_MASK_REG                                   , RULL(0x11040014), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_GXSTOP0_MASK_REG                                   , RULL(0x12040014), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_GXSTOP0_MASK_REG                                   , RULL(0x13040014), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_GXSTOP0_MASK_REG                                   , RULL(0x14040014), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_GXSTOP0_MASK_REG                                   , RULL(0x15040014), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_GXSTOP0_MASK_REG                                     , RULL(0x20040014), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21040014,
+REG64( EX_0_GXSTOP0_MASK_REG                                   , RULL(0x20040014), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21040014,
+REG64( EX_1_GXSTOP0_MASK_REG                                   , RULL(0x22040014), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23040014,
+REG64( EX_2_GXSTOP0_MASK_REG                                   , RULL(0x24040014), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25040014,
+REG64( EX_3_GXSTOP0_MASK_REG                                   , RULL(0x26040014), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27040014,
+REG64( EX_4_GXSTOP0_MASK_REG                                   , RULL(0x28040014), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29040014,
+REG64( EX_5_GXSTOP0_MASK_REG                                   , RULL(0x2A040014), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B040014,
+REG64( EX_6_GXSTOP0_MASK_REG                                   , RULL(0x2C040014), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D040014,
+REG64( EX_7_GXSTOP0_MASK_REG                                   , RULL(0x2E040014), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F040014,
+REG64( EX_8_GXSTOP0_MASK_REG                                   , RULL(0x30040014), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31040014,
+REG64( EX_9_GXSTOP0_MASK_REG                                   , RULL(0x32040014), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33040014,
+REG64( EX_10_GXSTOP0_MASK_REG                                  , RULL(0x34040014), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35040014,
+REG64( EX_11_GXSTOP0_MASK_REG                                  , RULL(0x36040014), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37040014,
+
+REG64( C_GXSTOP1_MASK_REG                                      , RULL(0x20040015), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_GXSTOP1_MASK_REG                                    , RULL(0x20040015), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_GXSTOP1_MASK_REG                                    , RULL(0x21040015), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_GXSTOP1_MASK_REG                                    , RULL(0x22040015), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_GXSTOP1_MASK_REG                                    , RULL(0x23040015), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_GXSTOP1_MASK_REG                                    , RULL(0x24040015), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_GXSTOP1_MASK_REG                                    , RULL(0x25040015), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_GXSTOP1_MASK_REG                                    , RULL(0x26040015), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_GXSTOP1_MASK_REG                                    , RULL(0x27040015), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_GXSTOP1_MASK_REG                                    , RULL(0x28040015), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_GXSTOP1_MASK_REG                                    , RULL(0x29040015), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_GXSTOP1_MASK_REG                                   , RULL(0x2A040015), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_GXSTOP1_MASK_REG                                   , RULL(0x2B040015), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_GXSTOP1_MASK_REG                                   , RULL(0x2C040015), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_GXSTOP1_MASK_REG                                   , RULL(0x2D040015), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_GXSTOP1_MASK_REG                                   , RULL(0x2E040015), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_GXSTOP1_MASK_REG                                   , RULL(0x2F040015), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_GXSTOP1_MASK_REG                                   , RULL(0x30040015), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_GXSTOP1_MASK_REG                                   , RULL(0x31040015), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_GXSTOP1_MASK_REG                                   , RULL(0x32040015), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_GXSTOP1_MASK_REG                                   , RULL(0x33040015), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_GXSTOP1_MASK_REG                                   , RULL(0x34040015), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_GXSTOP1_MASK_REG                                   , RULL(0x35040015), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_GXSTOP1_MASK_REG                                   , RULL(0x36040015), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_GXSTOP1_MASK_REG                                   , RULL(0x37040015), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_GXSTOP1_MASK_REG                                     , RULL(0x10040015), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_GXSTOP1_MASK_REG                                   , RULL(0x10040015), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_GXSTOP1_MASK_REG                                   , RULL(0x11040015), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_GXSTOP1_MASK_REG                                   , RULL(0x12040015), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_GXSTOP1_MASK_REG                                   , RULL(0x13040015), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_GXSTOP1_MASK_REG                                   , RULL(0x14040015), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_GXSTOP1_MASK_REG                                   , RULL(0x15040015), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_GXSTOP1_MASK_REG                                     , RULL(0x20040015), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21040015,
+REG64( EX_0_GXSTOP1_MASK_REG                                   , RULL(0x20040015), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21040015,
+REG64( EX_1_GXSTOP1_MASK_REG                                   , RULL(0x22040015), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23040015,
+REG64( EX_2_GXSTOP1_MASK_REG                                   , RULL(0x24040015), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25040015,
+REG64( EX_3_GXSTOP1_MASK_REG                                   , RULL(0x26040015), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27040015,
+REG64( EX_4_GXSTOP1_MASK_REG                                   , RULL(0x28040015), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29040015,
+REG64( EX_5_GXSTOP1_MASK_REG                                   , RULL(0x2A040015), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B040015,
+REG64( EX_6_GXSTOP1_MASK_REG                                   , RULL(0x2C040015), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D040015,
+REG64( EX_7_GXSTOP1_MASK_REG                                   , RULL(0x2E040015), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F040015,
+REG64( EX_8_GXSTOP1_MASK_REG                                   , RULL(0x30040015), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31040015,
+REG64( EX_9_GXSTOP1_MASK_REG                                   , RULL(0x32040015), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33040015,
+REG64( EX_10_GXSTOP1_MASK_REG                                  , RULL(0x34040015), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35040015,
+REG64( EX_11_GXSTOP1_MASK_REG                                  , RULL(0x36040015), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37040015,
+
+REG64( C_GXSTOP2_MASK_REG                                      , RULL(0x20040016), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_GXSTOP2_MASK_REG                                    , RULL(0x20040016), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_GXSTOP2_MASK_REG                                    , RULL(0x21040016), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_GXSTOP2_MASK_REG                                    , RULL(0x22040016), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_GXSTOP2_MASK_REG                                    , RULL(0x23040016), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_GXSTOP2_MASK_REG                                    , RULL(0x24040016), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_GXSTOP2_MASK_REG                                    , RULL(0x25040016), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_GXSTOP2_MASK_REG                                    , RULL(0x26040016), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_GXSTOP2_MASK_REG                                    , RULL(0x27040016), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_GXSTOP2_MASK_REG                                    , RULL(0x28040016), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_GXSTOP2_MASK_REG                                    , RULL(0x29040016), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_GXSTOP2_MASK_REG                                   , RULL(0x2A040016), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_GXSTOP2_MASK_REG                                   , RULL(0x2B040016), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_GXSTOP2_MASK_REG                                   , RULL(0x2C040016), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_GXSTOP2_MASK_REG                                   , RULL(0x2D040016), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_GXSTOP2_MASK_REG                                   , RULL(0x2E040016), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_GXSTOP2_MASK_REG                                   , RULL(0x2F040016), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_GXSTOP2_MASK_REG                                   , RULL(0x30040016), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_GXSTOP2_MASK_REG                                   , RULL(0x31040016), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_GXSTOP2_MASK_REG                                   , RULL(0x32040016), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_GXSTOP2_MASK_REG                                   , RULL(0x33040016), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_GXSTOP2_MASK_REG                                   , RULL(0x34040016), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_GXSTOP2_MASK_REG                                   , RULL(0x35040016), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_GXSTOP2_MASK_REG                                   , RULL(0x36040016), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_GXSTOP2_MASK_REG                                   , RULL(0x37040016), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_GXSTOP2_MASK_REG                                     , RULL(0x10040016), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_GXSTOP2_MASK_REG                                   , RULL(0x10040016), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_GXSTOP2_MASK_REG                                   , RULL(0x11040016), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_GXSTOP2_MASK_REG                                   , RULL(0x12040016), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_GXSTOP2_MASK_REG                                   , RULL(0x13040016), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_GXSTOP2_MASK_REG                                   , RULL(0x14040016), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_GXSTOP2_MASK_REG                                   , RULL(0x15040016), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_GXSTOP2_MASK_REG                                     , RULL(0x20040016), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21040016,
+REG64( EX_0_GXSTOP2_MASK_REG                                   , RULL(0x20040016), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21040016,
+REG64( EX_1_GXSTOP2_MASK_REG                                   , RULL(0x22040016), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23040016,
+REG64( EX_2_GXSTOP2_MASK_REG                                   , RULL(0x24040016), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25040016,
+REG64( EX_3_GXSTOP2_MASK_REG                                   , RULL(0x26040016), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27040016,
+REG64( EX_4_GXSTOP2_MASK_REG                                   , RULL(0x28040016), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29040016,
+REG64( EX_5_GXSTOP2_MASK_REG                                   , RULL(0x2A040016), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B040016,
+REG64( EX_6_GXSTOP2_MASK_REG                                   , RULL(0x2C040016), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D040016,
+REG64( EX_7_GXSTOP2_MASK_REG                                   , RULL(0x2E040016), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F040016,
+REG64( EX_8_GXSTOP2_MASK_REG                                   , RULL(0x30040016), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31040016,
+REG64( EX_9_GXSTOP2_MASK_REG                                   , RULL(0x32040016), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33040016,
+REG64( EX_10_GXSTOP2_MASK_REG                                  , RULL(0x34040016), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35040016,
+REG64( EX_11_GXSTOP2_MASK_REG                                  , RULL(0x36040016), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37040016,
+
+REG64( C_GXSTOP_TRIG_REG                                       , RULL(0x20040013), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_GXSTOP_TRIG_REG                                     , RULL(0x20040013), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_GXSTOP_TRIG_REG                                     , RULL(0x21040013), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_GXSTOP_TRIG_REG                                     , RULL(0x22040013), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_GXSTOP_TRIG_REG                                     , RULL(0x23040013), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_GXSTOP_TRIG_REG                                     , RULL(0x24040013), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_GXSTOP_TRIG_REG                                     , RULL(0x25040013), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_GXSTOP_TRIG_REG                                     , RULL(0x26040013), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_GXSTOP_TRIG_REG                                     , RULL(0x27040013), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_GXSTOP_TRIG_REG                                     , RULL(0x28040013), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_GXSTOP_TRIG_REG                                     , RULL(0x29040013), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_GXSTOP_TRIG_REG                                    , RULL(0x2A040013), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_GXSTOP_TRIG_REG                                    , RULL(0x2B040013), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_GXSTOP_TRIG_REG                                    , RULL(0x2C040013), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_GXSTOP_TRIG_REG                                    , RULL(0x2D040013), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_GXSTOP_TRIG_REG                                    , RULL(0x2E040013), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_GXSTOP_TRIG_REG                                    , RULL(0x2F040013), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_GXSTOP_TRIG_REG                                    , RULL(0x30040013), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_GXSTOP_TRIG_REG                                    , RULL(0x31040013), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_GXSTOP_TRIG_REG                                    , RULL(0x32040013), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_GXSTOP_TRIG_REG                                    , RULL(0x33040013), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_GXSTOP_TRIG_REG                                    , RULL(0x34040013), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_GXSTOP_TRIG_REG                                    , RULL(0x35040013), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_GXSTOP_TRIG_REG                                    , RULL(0x36040013), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_GXSTOP_TRIG_REG                                    , RULL(0x37040013), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_GXSTOP_TRIG_REG                                      , RULL(0x10040013), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_GXSTOP_TRIG_REG                                    , RULL(0x10040013), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_GXSTOP_TRIG_REG                                    , RULL(0x11040013), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_GXSTOP_TRIG_REG                                    , RULL(0x12040013), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_GXSTOP_TRIG_REG                                    , RULL(0x13040013), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_GXSTOP_TRIG_REG                                    , RULL(0x14040013), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_GXSTOP_TRIG_REG                                    , RULL(0x15040013), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_GXSTOP_TRIG_REG                                      , RULL(0x20040013), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21040013,
+REG64( EX_0_GXSTOP_TRIG_REG                                    , RULL(0x20040013), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21040013,
+REG64( EX_1_GXSTOP_TRIG_REG                                    , RULL(0x22040013), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23040013,
+REG64( EX_2_GXSTOP_TRIG_REG                                    , RULL(0x24040013), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25040013,
+REG64( EX_3_GXSTOP_TRIG_REG                                    , RULL(0x26040013), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27040013,
+REG64( EX_4_GXSTOP_TRIG_REG                                    , RULL(0x28040013), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29040013,
+REG64( EX_5_GXSTOP_TRIG_REG                                    , RULL(0x2A040013), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B040013,
+REG64( EX_6_GXSTOP_TRIG_REG                                    , RULL(0x2C040013), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D040013,
+REG64( EX_7_GXSTOP_TRIG_REG                                    , RULL(0x2E040013), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F040013,
+REG64( EX_8_GXSTOP_TRIG_REG                                    , RULL(0x30040013), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31040013,
+REG64( EX_9_GXSTOP_TRIG_REG                                    , RULL(0x32040013), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33040013,
+REG64( EX_10_GXSTOP_TRIG_REG                                   , RULL(0x34040013), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35040013,
+REG64( EX_11_GXSTOP_TRIG_REG                                   , RULL(0x36040013), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37040013,
+
+REG64( C_HANG_CONTROL                                          , RULL(0x20010A00), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_HANG_CONTROL                                        , RULL(0x20010A00), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_HANG_CONTROL                                        , RULL(0x21010A00), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_HANG_CONTROL                                        , RULL(0x22010A00), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_HANG_CONTROL                                        , RULL(0x23010A00), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_HANG_CONTROL                                        , RULL(0x24010A00), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_HANG_CONTROL                                        , RULL(0x25010A00), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_HANG_CONTROL                                        , RULL(0x26010A00), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_HANG_CONTROL                                        , RULL(0x27010A00), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_HANG_CONTROL                                        , RULL(0x28010A00), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_HANG_CONTROL                                        , RULL(0x29010A00), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_HANG_CONTROL                                       , RULL(0x2A010A00), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_HANG_CONTROL                                       , RULL(0x2B010A00), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_HANG_CONTROL                                       , RULL(0x2C010A00), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_HANG_CONTROL                                       , RULL(0x2D010A00), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_HANG_CONTROL                                       , RULL(0x2E010A00), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_HANG_CONTROL                                       , RULL(0x2F010A00), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_HANG_CONTROL                                       , RULL(0x30010A00), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_HANG_CONTROL                                       , RULL(0x31010A00), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_HANG_CONTROL                                       , RULL(0x32010A00), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_HANG_CONTROL                                       , RULL(0x33010A00), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_HANG_CONTROL                                       , RULL(0x34010A00), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_HANG_CONTROL                                       , RULL(0x35010A00), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_HANG_CONTROL                                       , RULL(0x36010A00), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_HANG_CONTROL                                       , RULL(0x37010A00), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_HANG_CONTROL                                    , RULL(0x20010A00), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A00,
+REG64( EX_10_L2_HANG_CONTROL                                   , RULL(0x34010A00), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010A00,
+REG64( EX_11_L2_HANG_CONTROL                                   , RULL(0x36010A00), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010A00,
+REG64( EX_1_L2_HANG_CONTROL                                    , RULL(0x22010A00), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010A00,
+REG64( EX_2_L2_HANG_CONTROL                                    , RULL(0x24010A00), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010A00,
+REG64( EX_3_L2_HANG_CONTROL                                    , RULL(0x26010A00), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010A00,
+REG64( EX_4_L2_HANG_CONTROL                                    , RULL(0x28010A00), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010A00,
+REG64( EX_5_L2_HANG_CONTROL                                    , RULL(0x2A010A00), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010A00,
+REG64( EX_6_L2_HANG_CONTROL                                    , RULL(0x2C010A00), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010A00,
+REG64( EX_7_L2_HANG_CONTROL                                    , RULL(0x2E010A00), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010A00,
+REG64( EX_8_L2_HANG_CONTROL                                    , RULL(0x30010A00), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010A00,
+REG64( EX_9_L2_HANG_CONTROL                                    , RULL(0x32010A00), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010A00,
+REG64( EX_L2_HANG_CONTROL                                      , RULL(0x20010A00), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A00,
+
+REG64( C_HANG_PULSE_0_REG                                      , RULL(0x200F0020), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_HANG_PULSE_0_REG                                    , RULL(0x200F0020), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_HANG_PULSE_0_REG                                    , RULL(0x210F0020), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_HANG_PULSE_0_REG                                    , RULL(0x220F0020), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_HANG_PULSE_0_REG                                    , RULL(0x230F0020), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_HANG_PULSE_0_REG                                    , RULL(0x240F0020), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_HANG_PULSE_0_REG                                    , RULL(0x250F0020), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_HANG_PULSE_0_REG                                    , RULL(0x260F0020), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_HANG_PULSE_0_REG                                    , RULL(0x270F0020), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_HANG_PULSE_0_REG                                    , RULL(0x280F0020), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_HANG_PULSE_0_REG                                    , RULL(0x290F0020), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_HANG_PULSE_0_REG                                   , RULL(0x2A0F0020), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_HANG_PULSE_0_REG                                   , RULL(0x2B0F0020), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_HANG_PULSE_0_REG                                   , RULL(0x2C0F0020), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_HANG_PULSE_0_REG                                   , RULL(0x2D0F0020), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_HANG_PULSE_0_REG                                   , RULL(0x2E0F0020), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_HANG_PULSE_0_REG                                   , RULL(0x2F0F0020), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_HANG_PULSE_0_REG                                   , RULL(0x300F0020), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_HANG_PULSE_0_REG                                   , RULL(0x310F0020), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_HANG_PULSE_0_REG                                   , RULL(0x320F0020), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_HANG_PULSE_0_REG                                   , RULL(0x330F0020), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_HANG_PULSE_0_REG                                   , RULL(0x340F0020), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_HANG_PULSE_0_REG                                   , RULL(0x350F0020), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_HANG_PULSE_0_REG                                   , RULL(0x360F0020), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_HANG_PULSE_0_REG                                   , RULL(0x370F0020), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_HANG_PULSE_0_REG                                     , RULL(0x100F0020), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_HANG_PULSE_0_REG                                   , RULL(0x100F0020), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_HANG_PULSE_0_REG                                   , RULL(0x110F0020), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_HANG_PULSE_0_REG                                   , RULL(0x120F0020), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_HANG_PULSE_0_REG                                   , RULL(0x130F0020), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_HANG_PULSE_0_REG                                   , RULL(0x140F0020), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_HANG_PULSE_0_REG                                   , RULL(0x150F0020), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_HANG_PULSE_0_REG                                     , RULL(0x200F0020), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0020,
+REG64( EX_0_HANG_PULSE_0_REG                                   , RULL(0x200F0020), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0020,
+REG64( EX_1_HANG_PULSE_0_REG                                   , RULL(0x230F0020), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0020,
+REG64( EX_2_HANG_PULSE_0_REG                                   , RULL(0x240F0020), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0020,
+REG64( EX_3_HANG_PULSE_0_REG                                   , RULL(0x260F0020), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0020,
+REG64( EX_4_HANG_PULSE_0_REG                                   , RULL(0x280F0020), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0020,
+REG64( EX_5_HANG_PULSE_0_REG                                   , RULL(0x2A0F0020), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0020,
+REG64( EX_6_HANG_PULSE_0_REG                                   , RULL(0x2C0F0020), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0020,
+REG64( EX_7_HANG_PULSE_0_REG                                   , RULL(0x2E0F0020), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0020,
+REG64( EX_8_HANG_PULSE_0_REG                                   , RULL(0x300F0020), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0020,
+REG64( EX_9_HANG_PULSE_0_REG                                   , RULL(0x320F0020), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0020,
+REG64( EX_10_HANG_PULSE_0_REG                                  , RULL(0x340F0020), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0020,
+REG64( EX_11_HANG_PULSE_0_REG                                  , RULL(0x360F0020), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0020,
+
+REG64( C_HANG_PULSE_1_REG                                      , RULL(0x200F0021), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_HANG_PULSE_1_REG                                    , RULL(0x200F0021), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_HANG_PULSE_1_REG                                    , RULL(0x210F0021), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_HANG_PULSE_1_REG                                    , RULL(0x220F0021), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_HANG_PULSE_1_REG                                    , RULL(0x230F0021), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_HANG_PULSE_1_REG                                    , RULL(0x240F0021), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_HANG_PULSE_1_REG                                    , RULL(0x250F0021), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_HANG_PULSE_1_REG                                    , RULL(0x260F0021), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_HANG_PULSE_1_REG                                    , RULL(0x270F0021), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_HANG_PULSE_1_REG                                    , RULL(0x280F0021), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_HANG_PULSE_1_REG                                    , RULL(0x290F0021), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_HANG_PULSE_1_REG                                   , RULL(0x2A0F0021), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_HANG_PULSE_1_REG                                   , RULL(0x2B0F0021), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_HANG_PULSE_1_REG                                   , RULL(0x2C0F0021), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_HANG_PULSE_1_REG                                   , RULL(0x2D0F0021), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_HANG_PULSE_1_REG                                   , RULL(0x2E0F0021), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_HANG_PULSE_1_REG                                   , RULL(0x2F0F0021), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_HANG_PULSE_1_REG                                   , RULL(0x300F0021), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_HANG_PULSE_1_REG                                   , RULL(0x310F0021), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_HANG_PULSE_1_REG                                   , RULL(0x320F0021), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_HANG_PULSE_1_REG                                   , RULL(0x330F0021), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_HANG_PULSE_1_REG                                   , RULL(0x340F0021), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_HANG_PULSE_1_REG                                   , RULL(0x350F0021), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_HANG_PULSE_1_REG                                   , RULL(0x360F0021), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_HANG_PULSE_1_REG                                   , RULL(0x370F0021), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_HANG_PULSE_1_REG                                     , RULL(0x100F0021), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_HANG_PULSE_1_REG                                   , RULL(0x100F0021), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_HANG_PULSE_1_REG                                   , RULL(0x110F0021), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_HANG_PULSE_1_REG                                   , RULL(0x120F0021), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_HANG_PULSE_1_REG                                   , RULL(0x130F0021), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_HANG_PULSE_1_REG                                   , RULL(0x140F0021), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_HANG_PULSE_1_REG                                   , RULL(0x150F0021), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_HANG_PULSE_1_REG                                     , RULL(0x200F0021), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0021,
+REG64( EX_0_HANG_PULSE_1_REG                                   , RULL(0x200F0021), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0021,
+REG64( EX_1_HANG_PULSE_1_REG                                   , RULL(0x230F0021), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0021,
+REG64( EX_2_HANG_PULSE_1_REG                                   , RULL(0x240F0021), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0021,
+REG64( EX_3_HANG_PULSE_1_REG                                   , RULL(0x260F0021), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0021,
+REG64( EX_4_HANG_PULSE_1_REG                                   , RULL(0x280F0021), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0021,
+REG64( EX_5_HANG_PULSE_1_REG                                   , RULL(0x2A0F0021), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0021,
+REG64( EX_6_HANG_PULSE_1_REG                                   , RULL(0x2C0F0021), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0021,
+REG64( EX_7_HANG_PULSE_1_REG                                   , RULL(0x2E0F0021), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0021,
+REG64( EX_8_HANG_PULSE_1_REG                                   , RULL(0x300F0021), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0021,
+REG64( EX_9_HANG_PULSE_1_REG                                   , RULL(0x320F0021), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0021,
+REG64( EX_10_HANG_PULSE_1_REG                                  , RULL(0x340F0021), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0021,
+REG64( EX_11_HANG_PULSE_1_REG                                  , RULL(0x360F0021), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0021,
+
+REG64( C_HANG_PULSE_2_REG                                      , RULL(0x200F0022), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_HANG_PULSE_2_REG                                    , RULL(0x200F0022), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_HANG_PULSE_2_REG                                    , RULL(0x210F0022), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_HANG_PULSE_2_REG                                    , RULL(0x220F0022), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_HANG_PULSE_2_REG                                    , RULL(0x230F0022), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_HANG_PULSE_2_REG                                    , RULL(0x240F0022), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_HANG_PULSE_2_REG                                    , RULL(0x250F0022), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_HANG_PULSE_2_REG                                    , RULL(0x260F0022), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_HANG_PULSE_2_REG                                    , RULL(0x270F0022), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_HANG_PULSE_2_REG                                    , RULL(0x280F0022), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_HANG_PULSE_2_REG                                    , RULL(0x290F0022), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_HANG_PULSE_2_REG                                   , RULL(0x2A0F0022), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_HANG_PULSE_2_REG                                   , RULL(0x2B0F0022), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_HANG_PULSE_2_REG                                   , RULL(0x2C0F0022), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_HANG_PULSE_2_REG                                   , RULL(0x2D0F0022), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_HANG_PULSE_2_REG                                   , RULL(0x2E0F0022), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_HANG_PULSE_2_REG                                   , RULL(0x2F0F0022), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_HANG_PULSE_2_REG                                   , RULL(0x300F0022), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_HANG_PULSE_2_REG                                   , RULL(0x310F0022), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_HANG_PULSE_2_REG                                   , RULL(0x320F0022), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_HANG_PULSE_2_REG                                   , RULL(0x330F0022), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_HANG_PULSE_2_REG                                   , RULL(0x340F0022), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_HANG_PULSE_2_REG                                   , RULL(0x350F0022), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_HANG_PULSE_2_REG                                   , RULL(0x360F0022), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_HANG_PULSE_2_REG                                   , RULL(0x370F0022), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_HANG_PULSE_2_REG                                     , RULL(0x100F0022), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_HANG_PULSE_2_REG                                   , RULL(0x100F0022), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_HANG_PULSE_2_REG                                   , RULL(0x110F0022), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_HANG_PULSE_2_REG                                   , RULL(0x120F0022), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_HANG_PULSE_2_REG                                   , RULL(0x130F0022), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_HANG_PULSE_2_REG                                   , RULL(0x140F0022), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_HANG_PULSE_2_REG                                   , RULL(0x150F0022), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_HANG_PULSE_2_REG                                     , RULL(0x200F0022), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0022,
+REG64( EX_0_HANG_PULSE_2_REG                                   , RULL(0x200F0022), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0022,
+REG64( EX_1_HANG_PULSE_2_REG                                   , RULL(0x230F0022), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0022,
+REG64( EX_2_HANG_PULSE_2_REG                                   , RULL(0x240F0022), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0022,
+REG64( EX_3_HANG_PULSE_2_REG                                   , RULL(0x260F0022), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0022,
+REG64( EX_4_HANG_PULSE_2_REG                                   , RULL(0x280F0022), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0022,
+REG64( EX_5_HANG_PULSE_2_REG                                   , RULL(0x2A0F0022), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0022,
+REG64( EX_6_HANG_PULSE_2_REG                                   , RULL(0x2C0F0022), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0022,
+REG64( EX_7_HANG_PULSE_2_REG                                   , RULL(0x2E0F0022), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0022,
+REG64( EX_8_HANG_PULSE_2_REG                                   , RULL(0x300F0022), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0022,
+REG64( EX_9_HANG_PULSE_2_REG                                   , RULL(0x320F0022), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0022,
+REG64( EX_10_HANG_PULSE_2_REG                                  , RULL(0x340F0022), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0022,
+REG64( EX_11_HANG_PULSE_2_REG                                  , RULL(0x360F0022), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0022,
+
+REG64( C_HANG_PULSE_3_REG                                      , RULL(0x200F0023), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_HANG_PULSE_3_REG                                    , RULL(0x200F0023), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_HANG_PULSE_3_REG                                    , RULL(0x210F0023), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_HANG_PULSE_3_REG                                    , RULL(0x220F0023), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_HANG_PULSE_3_REG                                    , RULL(0x230F0023), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_HANG_PULSE_3_REG                                    , RULL(0x240F0023), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_HANG_PULSE_3_REG                                    , RULL(0x250F0023), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_HANG_PULSE_3_REG                                    , RULL(0x260F0023), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_HANG_PULSE_3_REG                                    , RULL(0x270F0023), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_HANG_PULSE_3_REG                                    , RULL(0x280F0023), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_HANG_PULSE_3_REG                                    , RULL(0x290F0023), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_HANG_PULSE_3_REG                                   , RULL(0x2A0F0023), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_HANG_PULSE_3_REG                                   , RULL(0x2B0F0023), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_HANG_PULSE_3_REG                                   , RULL(0x2C0F0023), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_HANG_PULSE_3_REG                                   , RULL(0x2D0F0023), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_HANG_PULSE_3_REG                                   , RULL(0x2E0F0023), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_HANG_PULSE_3_REG                                   , RULL(0x2F0F0023), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_HANG_PULSE_3_REG                                   , RULL(0x300F0023), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_HANG_PULSE_3_REG                                   , RULL(0x310F0023), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_HANG_PULSE_3_REG                                   , RULL(0x320F0023), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_HANG_PULSE_3_REG                                   , RULL(0x330F0023), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_HANG_PULSE_3_REG                                   , RULL(0x340F0023), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_HANG_PULSE_3_REG                                   , RULL(0x350F0023), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_HANG_PULSE_3_REG                                   , RULL(0x360F0023), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_HANG_PULSE_3_REG                                   , RULL(0x370F0023), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_HANG_PULSE_3_REG                                     , RULL(0x100F0023), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_HANG_PULSE_3_REG                                   , RULL(0x100F0023), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_HANG_PULSE_3_REG                                   , RULL(0x110F0023), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_HANG_PULSE_3_REG                                   , RULL(0x120F0023), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_HANG_PULSE_3_REG                                   , RULL(0x130F0023), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_HANG_PULSE_3_REG                                   , RULL(0x140F0023), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_HANG_PULSE_3_REG                                   , RULL(0x150F0023), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_HANG_PULSE_3_REG                                     , RULL(0x200F0023), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0023,
+REG64( EX_0_HANG_PULSE_3_REG                                   , RULL(0x200F0023), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0023,
+REG64( EX_1_HANG_PULSE_3_REG                                   , RULL(0x230F0023), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0023,
+REG64( EX_2_HANG_PULSE_3_REG                                   , RULL(0x240F0023), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0023,
+REG64( EX_3_HANG_PULSE_3_REG                                   , RULL(0x260F0023), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0023,
+REG64( EX_4_HANG_PULSE_3_REG                                   , RULL(0x280F0023), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0023,
+REG64( EX_5_HANG_PULSE_3_REG                                   , RULL(0x2A0F0023), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0023,
+REG64( EX_6_HANG_PULSE_3_REG                                   , RULL(0x2C0F0023), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0023,
+REG64( EX_7_HANG_PULSE_3_REG                                   , RULL(0x2E0F0023), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0023,
+REG64( EX_8_HANG_PULSE_3_REG                                   , RULL(0x300F0023), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0023,
+REG64( EX_9_HANG_PULSE_3_REG                                   , RULL(0x320F0023), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0023,
+REG64( EX_10_HANG_PULSE_3_REG                                  , RULL(0x340F0023), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0023,
+REG64( EX_11_HANG_PULSE_3_REG                                  , RULL(0x360F0023), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0023,
+
+REG64( C_HANG_PULSE_4_REG                                      , RULL(0x200F0024), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_HANG_PULSE_4_REG                                    , RULL(0x200F0024), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_HANG_PULSE_4_REG                                    , RULL(0x210F0024), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_HANG_PULSE_4_REG                                    , RULL(0x220F0024), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_HANG_PULSE_4_REG                                    , RULL(0x230F0024), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_HANG_PULSE_4_REG                                    , RULL(0x240F0024), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_HANG_PULSE_4_REG                                    , RULL(0x250F0024), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_HANG_PULSE_4_REG                                    , RULL(0x260F0024), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_HANG_PULSE_4_REG                                    , RULL(0x270F0024), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_HANG_PULSE_4_REG                                    , RULL(0x280F0024), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_HANG_PULSE_4_REG                                    , RULL(0x290F0024), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_HANG_PULSE_4_REG                                   , RULL(0x2A0F0024), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_HANG_PULSE_4_REG                                   , RULL(0x2B0F0024), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_HANG_PULSE_4_REG                                   , RULL(0x2C0F0024), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_HANG_PULSE_4_REG                                   , RULL(0x2D0F0024), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_HANG_PULSE_4_REG                                   , RULL(0x2E0F0024), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_HANG_PULSE_4_REG                                   , RULL(0x2F0F0024), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_HANG_PULSE_4_REG                                   , RULL(0x300F0024), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_HANG_PULSE_4_REG                                   , RULL(0x310F0024), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_HANG_PULSE_4_REG                                   , RULL(0x320F0024), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_HANG_PULSE_4_REG                                   , RULL(0x330F0024), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_HANG_PULSE_4_REG                                   , RULL(0x340F0024), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_HANG_PULSE_4_REG                                   , RULL(0x350F0024), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_HANG_PULSE_4_REG                                   , RULL(0x360F0024), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_HANG_PULSE_4_REG                                   , RULL(0x370F0024), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_HANG_PULSE_4_REG                                     , RULL(0x100F0024), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_HANG_PULSE_4_REG                                   , RULL(0x100F0024), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_HANG_PULSE_4_REG                                   , RULL(0x110F0024), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_HANG_PULSE_4_REG                                   , RULL(0x120F0024), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_HANG_PULSE_4_REG                                   , RULL(0x130F0024), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_HANG_PULSE_4_REG                                   , RULL(0x140F0024), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_HANG_PULSE_4_REG                                   , RULL(0x150F0024), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_HANG_PULSE_4_REG                                     , RULL(0x200F0024), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0024,
+REG64( EX_0_HANG_PULSE_4_REG                                   , RULL(0x200F0024), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0024,
+REG64( EX_1_HANG_PULSE_4_REG                                   , RULL(0x230F0024), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0024,
+REG64( EX_2_HANG_PULSE_4_REG                                   , RULL(0x240F0024), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0024,
+REG64( EX_3_HANG_PULSE_4_REG                                   , RULL(0x260F0024), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0024,
+REG64( EX_4_HANG_PULSE_4_REG                                   , RULL(0x280F0024), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0024,
+REG64( EX_5_HANG_PULSE_4_REG                                   , RULL(0x2A0F0024), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0024,
+REG64( EX_6_HANG_PULSE_4_REG                                   , RULL(0x2C0F0024), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0024,
+REG64( EX_7_HANG_PULSE_4_REG                                   , RULL(0x2E0F0024), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0024,
+REG64( EX_8_HANG_PULSE_4_REG                                   , RULL(0x300F0024), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0024,
+REG64( EX_9_HANG_PULSE_4_REG                                   , RULL(0x320F0024), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0024,
+REG64( EX_10_HANG_PULSE_4_REG                                  , RULL(0x340F0024), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0024,
+REG64( EX_11_HANG_PULSE_4_REG                                  , RULL(0x360F0024), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0024,
+
+REG64( C_HANG_PULSE_5_REG                                      , RULL(0x200F0025), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_HANG_PULSE_5_REG                                    , RULL(0x200F0025), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_HANG_PULSE_5_REG                                    , RULL(0x210F0025), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_HANG_PULSE_5_REG                                    , RULL(0x220F0025), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_HANG_PULSE_5_REG                                    , RULL(0x230F0025), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_HANG_PULSE_5_REG                                    , RULL(0x240F0025), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_HANG_PULSE_5_REG                                    , RULL(0x250F0025), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_HANG_PULSE_5_REG                                    , RULL(0x260F0025), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_HANG_PULSE_5_REG                                    , RULL(0x270F0025), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_HANG_PULSE_5_REG                                    , RULL(0x280F0025), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_HANG_PULSE_5_REG                                    , RULL(0x290F0025), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_HANG_PULSE_5_REG                                   , RULL(0x2A0F0025), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_HANG_PULSE_5_REG                                   , RULL(0x2B0F0025), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_HANG_PULSE_5_REG                                   , RULL(0x2C0F0025), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_HANG_PULSE_5_REG                                   , RULL(0x2D0F0025), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_HANG_PULSE_5_REG                                   , RULL(0x2E0F0025), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_HANG_PULSE_5_REG                                   , RULL(0x2F0F0025), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_HANG_PULSE_5_REG                                   , RULL(0x300F0025), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_HANG_PULSE_5_REG                                   , RULL(0x310F0025), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_HANG_PULSE_5_REG                                   , RULL(0x320F0025), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_HANG_PULSE_5_REG                                   , RULL(0x330F0025), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_HANG_PULSE_5_REG                                   , RULL(0x340F0025), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_HANG_PULSE_5_REG                                   , RULL(0x350F0025), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_HANG_PULSE_5_REG                                   , RULL(0x360F0025), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_HANG_PULSE_5_REG                                   , RULL(0x370F0025), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_HANG_PULSE_5_REG                                     , RULL(0x100F0025), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_HANG_PULSE_5_REG                                   , RULL(0x100F0025), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_HANG_PULSE_5_REG                                   , RULL(0x110F0025), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_HANG_PULSE_5_REG                                   , RULL(0x120F0025), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_HANG_PULSE_5_REG                                   , RULL(0x130F0025), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_HANG_PULSE_5_REG                                   , RULL(0x140F0025), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_HANG_PULSE_5_REG                                   , RULL(0x150F0025), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_HANG_PULSE_5_REG                                     , RULL(0x200F0025), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0025,
+REG64( EX_0_HANG_PULSE_5_REG                                   , RULL(0x200F0025), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0025,
+REG64( EX_1_HANG_PULSE_5_REG                                   , RULL(0x230F0025), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0025,
+REG64( EX_2_HANG_PULSE_5_REG                                   , RULL(0x240F0025), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0025,
+REG64( EX_3_HANG_PULSE_5_REG                                   , RULL(0x260F0025), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0025,
+REG64( EX_4_HANG_PULSE_5_REG                                   , RULL(0x280F0025), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0025,
+REG64( EX_5_HANG_PULSE_5_REG                                   , RULL(0x2A0F0025), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0025,
+REG64( EX_6_HANG_PULSE_5_REG                                   , RULL(0x2C0F0025), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0025,
+REG64( EX_7_HANG_PULSE_5_REG                                   , RULL(0x2E0F0025), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0025,
+REG64( EX_8_HANG_PULSE_5_REG                                   , RULL(0x300F0025), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0025,
+REG64( EX_9_HANG_PULSE_5_REG                                   , RULL(0x320F0025), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0025,
+REG64( EX_10_HANG_PULSE_5_REG                                  , RULL(0x340F0025), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0025,
+REG64( EX_11_HANG_PULSE_5_REG                                  , RULL(0x360F0025), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0025,
+
+REG64( C_HANG_PULSE_6_REG                                      , RULL(0x200F0026), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_HANG_PULSE_6_REG                                    , RULL(0x200F0026), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_HANG_PULSE_6_REG                                    , RULL(0x210F0026), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_HANG_PULSE_6_REG                                    , RULL(0x220F0026), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_HANG_PULSE_6_REG                                    , RULL(0x230F0026), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_HANG_PULSE_6_REG                                    , RULL(0x240F0026), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_HANG_PULSE_6_REG                                    , RULL(0x250F0026), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_HANG_PULSE_6_REG                                    , RULL(0x260F0026), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_HANG_PULSE_6_REG                                    , RULL(0x270F0026), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_HANG_PULSE_6_REG                                    , RULL(0x280F0026), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_HANG_PULSE_6_REG                                    , RULL(0x290F0026), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_HANG_PULSE_6_REG                                   , RULL(0x2A0F0026), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_HANG_PULSE_6_REG                                   , RULL(0x2B0F0026), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_HANG_PULSE_6_REG                                   , RULL(0x2C0F0026), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_HANG_PULSE_6_REG                                   , RULL(0x2D0F0026), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_HANG_PULSE_6_REG                                   , RULL(0x2E0F0026), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_HANG_PULSE_6_REG                                   , RULL(0x2F0F0026), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_HANG_PULSE_6_REG                                   , RULL(0x300F0026), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_HANG_PULSE_6_REG                                   , RULL(0x310F0026), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_HANG_PULSE_6_REG                                   , RULL(0x320F0026), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_HANG_PULSE_6_REG                                   , RULL(0x330F0026), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_HANG_PULSE_6_REG                                   , RULL(0x340F0026), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_HANG_PULSE_6_REG                                   , RULL(0x350F0026), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_HANG_PULSE_6_REG                                   , RULL(0x360F0026), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_HANG_PULSE_6_REG                                   , RULL(0x370F0026), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_HANG_PULSE_6_REG                                     , RULL(0x100F0026), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_HANG_PULSE_6_REG                                   , RULL(0x100F0026), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_HANG_PULSE_6_REG                                   , RULL(0x110F0026), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_HANG_PULSE_6_REG                                   , RULL(0x120F0026), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_HANG_PULSE_6_REG                                   , RULL(0x130F0026), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_HANG_PULSE_6_REG                                   , RULL(0x140F0026), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_HANG_PULSE_6_REG                                   , RULL(0x150F0026), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_HANG_PULSE_6_REG                                     , RULL(0x200F0026), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0026,
+REG64( EX_0_HANG_PULSE_6_REG                                   , RULL(0x200F0026), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0026,
+REG64( EX_1_HANG_PULSE_6_REG                                   , RULL(0x230F0026), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0026,
+REG64( EX_2_HANG_PULSE_6_REG                                   , RULL(0x240F0026), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0026,
+REG64( EX_3_HANG_PULSE_6_REG                                   , RULL(0x260F0026), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0026,
+REG64( EX_4_HANG_PULSE_6_REG                                   , RULL(0x280F0026), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0026,
+REG64( EX_5_HANG_PULSE_6_REG                                   , RULL(0x2A0F0026), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0026,
+REG64( EX_6_HANG_PULSE_6_REG                                   , RULL(0x2C0F0026), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0026,
+REG64( EX_7_HANG_PULSE_6_REG                                   , RULL(0x2E0F0026), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0026,
+REG64( EX_8_HANG_PULSE_6_REG                                   , RULL(0x300F0026), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0026,
+REG64( EX_9_HANG_PULSE_6_REG                                   , RULL(0x320F0026), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0026,
+REG64( EX_10_HANG_PULSE_6_REG                                  , RULL(0x340F0026), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0026,
+REG64( EX_11_HANG_PULSE_6_REG                                  , RULL(0x360F0026), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0026,
+
+REG64( C_HEARTBEAT_REG                                         , RULL(0x200F0018), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_HEARTBEAT_REG                                       , RULL(0x200F0018), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_HEARTBEAT_REG                                       , RULL(0x210F0018), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_HEARTBEAT_REG                                       , RULL(0x220F0018), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_HEARTBEAT_REG                                       , RULL(0x230F0018), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_HEARTBEAT_REG                                       , RULL(0x240F0018), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_HEARTBEAT_REG                                       , RULL(0x250F0018), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_HEARTBEAT_REG                                       , RULL(0x260F0018), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_HEARTBEAT_REG                                       , RULL(0x270F0018), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_HEARTBEAT_REG                                       , RULL(0x280F0018), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_HEARTBEAT_REG                                       , RULL(0x290F0018), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_HEARTBEAT_REG                                      , RULL(0x2A0F0018), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_HEARTBEAT_REG                                      , RULL(0x2B0F0018), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_HEARTBEAT_REG                                      , RULL(0x2C0F0018), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_HEARTBEAT_REG                                      , RULL(0x2D0F0018), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_HEARTBEAT_REG                                      , RULL(0x2E0F0018), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_HEARTBEAT_REG                                      , RULL(0x2F0F0018), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_HEARTBEAT_REG                                      , RULL(0x300F0018), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_HEARTBEAT_REG                                      , RULL(0x310F0018), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_HEARTBEAT_REG                                      , RULL(0x320F0018), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_HEARTBEAT_REG                                      , RULL(0x330F0018), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_HEARTBEAT_REG                                      , RULL(0x340F0018), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_HEARTBEAT_REG                                      , RULL(0x350F0018), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_HEARTBEAT_REG                                      , RULL(0x360F0018), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_HEARTBEAT_REG                                      , RULL(0x370F0018), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_HEARTBEAT_REG                                        , RULL(0x100F0018), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_HEARTBEAT_REG                                      , RULL(0x100F0018), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_HEARTBEAT_REG                                      , RULL(0x110F0018), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_HEARTBEAT_REG                                      , RULL(0x120F0018), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_HEARTBEAT_REG                                      , RULL(0x130F0018), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_HEARTBEAT_REG                                      , RULL(0x140F0018), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_HEARTBEAT_REG                                      , RULL(0x150F0018), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_HEARTBEAT_REG                                        , RULL(0x200F0018), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0018,
+REG64( EX_0_HEARTBEAT_REG                                      , RULL(0x200F0018), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0018,
+REG64( EX_1_HEARTBEAT_REG                                      , RULL(0x230F0018), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0018,
+REG64( EX_2_HEARTBEAT_REG                                      , RULL(0x240F0018), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0018,
+REG64( EX_3_HEARTBEAT_REG                                      , RULL(0x260F0018), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0018,
+REG64( EX_4_HEARTBEAT_REG                                      , RULL(0x280F0018), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0018,
+REG64( EX_5_HEARTBEAT_REG                                      , RULL(0x2A0F0018), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0018,
+REG64( EX_6_HEARTBEAT_REG                                      , RULL(0x2C0F0018), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0018,
+REG64( EX_7_HEARTBEAT_REG                                      , RULL(0x2E0F0018), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0018,
+REG64( EX_8_HEARTBEAT_REG                                      , RULL(0x300F0018), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0018,
+REG64( EX_9_HEARTBEAT_REG                                      , RULL(0x320F0018), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0018,
+REG64( EX_10_HEARTBEAT_REG                                     , RULL(0x340F0018), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0018,
+REG64( EX_11_HEARTBEAT_REG                                     , RULL(0x360F0018), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0018,
+
+REG64( C_HID                                                   , RULL(0x20010A01), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_HID                                                 , RULL(0x20010A01), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_HID                                                 , RULL(0x21010A01), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_HID                                                 , RULL(0x22010A01), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_HID                                                 , RULL(0x23010A01), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_HID                                                 , RULL(0x24010A01), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_HID                                                 , RULL(0x25010A01), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_HID                                                 , RULL(0x26010A01), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_HID                                                 , RULL(0x27010A01), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_HID                                                 , RULL(0x28010A01), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_HID                                                 , RULL(0x29010A01), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_HID                                                , RULL(0x2A010A01), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_HID                                                , RULL(0x2B010A01), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_HID                                                , RULL(0x2C010A01), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_HID                                                , RULL(0x2D010A01), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_HID                                                , RULL(0x2E010A01), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_HID                                                , RULL(0x2F010A01), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_HID                                                , RULL(0x30010A01), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_HID                                                , RULL(0x31010A01), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_HID                                                , RULL(0x32010A01), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_HID                                                , RULL(0x33010A01), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_HID                                                , RULL(0x34010A01), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_HID                                                , RULL(0x35010A01), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_HID                                                , RULL(0x36010A01), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_HID                                                , RULL(0x37010A01), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_HID                                             , RULL(0x20010A01), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010A01,
+REG64( EX_10_L2_HID                                            , RULL(0x34010A01), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010A01,
+REG64( EX_11_L2_HID                                            , RULL(0x36010A01), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010A01,
+REG64( EX_1_L2_HID                                             , RULL(0x22010A01), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010A01,
+REG64( EX_2_L2_HID                                             , RULL(0x24010A01), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010A01,
+REG64( EX_3_L2_HID                                             , RULL(0x26010A01), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010A01,
+REG64( EX_4_L2_HID                                             , RULL(0x28010A01), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010A01,
+REG64( EX_5_L2_HID                                             , RULL(0x2A010A01), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010A01,
+REG64( EX_6_L2_HID                                             , RULL(0x2C010A01), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010A01,
+REG64( EX_7_L2_HID                                             , RULL(0x2E010A01), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010A01,
+REG64( EX_8_L2_HID                                             , RULL(0x30010A01), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010A01,
+REG64( EX_9_L2_HID                                             , RULL(0x32010A01), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010A01,
+REG64( EX_L2_HID                                               , RULL(0x20010A01), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010A01,
+
+REG64( C_HMEER                                                 , RULL(0x20010A96), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_HMEER                                               , RULL(0x20010A96), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_HMEER                                               , RULL(0x21010A96), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_HMEER                                               , RULL(0x22010A96), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_HMEER                                               , RULL(0x23010A96), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_HMEER                                               , RULL(0x24010A96), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_HMEER                                               , RULL(0x25010A96), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_HMEER                                               , RULL(0x26010A96), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_HMEER                                               , RULL(0x27010A96), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_HMEER                                               , RULL(0x28010A96), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_HMEER                                               , RULL(0x29010A96), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_HMEER                                              , RULL(0x2A010A96), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_HMEER                                              , RULL(0x2B010A96), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_HMEER                                              , RULL(0x2C010A96), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_HMEER                                              , RULL(0x2D010A96), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_HMEER                                              , RULL(0x2E010A96), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_HMEER                                              , RULL(0x2F010A96), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_HMEER                                              , RULL(0x30010A96), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_HMEER                                              , RULL(0x31010A96), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_HMEER                                              , RULL(0x32010A96), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_HMEER                                              , RULL(0x33010A96), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_HMEER                                              , RULL(0x34010A96), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_HMEER                                              , RULL(0x35010A96), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_HMEER                                              , RULL(0x36010A96), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_HMEER                                              , RULL(0x37010A96), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_HMEER                                           , RULL(0x21010A96), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A96,
+REG64( EX_10_L2_HMEER                                          , RULL(0x35010A96), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 34010A96,
+REG64( EX_11_L2_HMEER                                          , RULL(0x37010A96), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 36010A96,
+REG64( EX_1_L2_HMEER                                           , RULL(0x23010A96), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 22010A96,
+REG64( EX_2_L2_HMEER                                           , RULL(0x25010A96), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 24010A96,
+REG64( EX_3_L2_HMEER                                           , RULL(0x27010A96), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 26010A96,
+REG64( EX_4_L2_HMEER                                           , RULL(0x29010A96), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 28010A96,
+REG64( EX_5_L2_HMEER                                           , RULL(0x2B010A96), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2A010A96,
+REG64( EX_6_L2_HMEER                                           , RULL(0x2D010A96), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2C010A96,
+REG64( EX_7_L2_HMEER                                           , RULL(0x2F010A96), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2E010A96,
+REG64( EX_8_L2_HMEER                                           , RULL(0x31010A96), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 30010A96,
+REG64( EX_9_L2_HMEER                                           , RULL(0x33010A96), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 32010A96,
+REG64( EX_L2_HMEER                                             , RULL(0x21010A96), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A96,
+
+REG64( C_HOSTATTN                                              , RULL(0x20040009), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_HOSTATTN                                            , RULL(0x20040009), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_HOSTATTN                                            , RULL(0x21040009), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_HOSTATTN                                            , RULL(0x22040009), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_HOSTATTN                                            , RULL(0x23040009), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_HOSTATTN                                            , RULL(0x24040009), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_HOSTATTN                                            , RULL(0x25040009), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_HOSTATTN                                            , RULL(0x26040009), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_HOSTATTN                                            , RULL(0x27040009), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_HOSTATTN                                            , RULL(0x28040009), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_HOSTATTN                                            , RULL(0x29040009), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_HOSTATTN                                           , RULL(0x2A040009), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_HOSTATTN                                           , RULL(0x2B040009), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_HOSTATTN                                           , RULL(0x2C040009), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_HOSTATTN                                           , RULL(0x2D040009), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_HOSTATTN                                           , RULL(0x2E040009), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_HOSTATTN                                           , RULL(0x2F040009), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_HOSTATTN                                           , RULL(0x30040009), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_HOSTATTN                                           , RULL(0x31040009), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_HOSTATTN                                           , RULL(0x32040009), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_HOSTATTN                                           , RULL(0x33040009), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_HOSTATTN                                           , RULL(0x34040009), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_HOSTATTN                                           , RULL(0x35040009), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_HOSTATTN                                           , RULL(0x36040009), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_HOSTATTN                                           , RULL(0x37040009), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EQ_HOSTATTN                                             , RULL(0x10040009), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_HOSTATTN                                           , RULL(0x10040009), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_HOSTATTN                                           , RULL(0x11040009), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_HOSTATTN                                           , RULL(0x12040009), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_HOSTATTN                                           , RULL(0x13040009), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_HOSTATTN                                           , RULL(0x14040009), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_HOSTATTN                                           , RULL(0x15040009), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_HOSTATTN                                             , RULL(0x20040009), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21040009,
+REG64( EX_0_HOSTATTN                                           , RULL(0x20040009), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21040009,
+REG64( EX_1_HOSTATTN                                           , RULL(0x22040009), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23040009,
+REG64( EX_2_HOSTATTN                                           , RULL(0x24040009), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25040009,
+REG64( EX_3_HOSTATTN                                           , RULL(0x26040009), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27040009,
+REG64( EX_4_HOSTATTN                                           , RULL(0x28040009), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29040009,
+REG64( EX_5_HOSTATTN                                           , RULL(0x2A040009), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B040009,
+REG64( EX_6_HOSTATTN                                           , RULL(0x2C040009), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D040009,
+REG64( EX_7_HOSTATTN                                           , RULL(0x2E040009), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F040009,
+REG64( EX_8_HOSTATTN                                           , RULL(0x30040009), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31040009,
+REG64( EX_9_HOSTATTN                                           , RULL(0x32040009), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33040009,
+REG64( EX_10_HOSTATTN                                          , RULL(0x34040009), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35040009,
+REG64( EX_11_HOSTATTN                                          , RULL(0x36040009), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37040009,
+
+REG64( C_HOSTATTN_MASK                                         , RULL(0x2004001A), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_HOSTATTN_MASK                                       , RULL(0x2004001A), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_HOSTATTN_MASK                                       , RULL(0x2104001A), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_HOSTATTN_MASK                                       , RULL(0x2204001A), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_HOSTATTN_MASK                                       , RULL(0x2304001A), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_HOSTATTN_MASK                                       , RULL(0x2404001A), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_HOSTATTN_MASK                                       , RULL(0x2504001A), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_HOSTATTN_MASK                                       , RULL(0x2604001A), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_HOSTATTN_MASK                                       , RULL(0x2704001A), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_HOSTATTN_MASK                                       , RULL(0x2804001A), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_HOSTATTN_MASK                                       , RULL(0x2904001A), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_HOSTATTN_MASK                                      , RULL(0x2A04001A), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_HOSTATTN_MASK                                      , RULL(0x2B04001A), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_HOSTATTN_MASK                                      , RULL(0x2C04001A), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_HOSTATTN_MASK                                      , RULL(0x2D04001A), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_HOSTATTN_MASK                                      , RULL(0x2E04001A), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_HOSTATTN_MASK                                      , RULL(0x2F04001A), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_HOSTATTN_MASK                                      , RULL(0x3004001A), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_HOSTATTN_MASK                                      , RULL(0x3104001A), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_HOSTATTN_MASK                                      , RULL(0x3204001A), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_HOSTATTN_MASK                                      , RULL(0x3304001A), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_HOSTATTN_MASK                                      , RULL(0x3404001A), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_HOSTATTN_MASK                                      , RULL(0x3504001A), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_HOSTATTN_MASK                                      , RULL(0x3604001A), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_HOSTATTN_MASK                                      , RULL(0x3704001A), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_HOSTATTN_MASK                                        , RULL(0x1004001A), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_HOSTATTN_MASK                                      , RULL(0x1004001A), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_HOSTATTN_MASK                                      , RULL(0x1104001A), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_HOSTATTN_MASK                                      , RULL(0x1204001A), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_HOSTATTN_MASK                                      , RULL(0x1304001A), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_HOSTATTN_MASK                                      , RULL(0x1404001A), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_HOSTATTN_MASK                                      , RULL(0x1504001A), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_HOSTATTN_MASK                                        , RULL(0x2004001A), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 2104001A,
+REG64( EX_0_HOSTATTN_MASK                                      , RULL(0x2004001A), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 2104001A,
+REG64( EX_1_HOSTATTN_MASK                                      , RULL(0x2204001A), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 2304001A,
+REG64( EX_2_HOSTATTN_MASK                                      , RULL(0x2404001A), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 2504001A,
+REG64( EX_3_HOSTATTN_MASK                                      , RULL(0x2604001A), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 2704001A,
+REG64( EX_4_HOSTATTN_MASK                                      , RULL(0x2804001A), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 2904001A,
+REG64( EX_5_HOSTATTN_MASK                                      , RULL(0x2A04001A), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B04001A,
+REG64( EX_6_HOSTATTN_MASK                                      , RULL(0x2C04001A), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D04001A,
+REG64( EX_7_HOSTATTN_MASK                                      , RULL(0x2E04001A), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F04001A,
+REG64( EX_8_HOSTATTN_MASK                                      , RULL(0x3004001A), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 3104001A,
+REG64( EX_9_HOSTATTN_MASK                                      , RULL(0x3204001A), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 3304001A,
+REG64( EX_10_HOSTATTN_MASK                                     , RULL(0x3404001A), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 3504001A,
+REG64( EX_11_HOSTATTN_MASK                                     , RULL(0x3604001A), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 3704001A,
+
+REG64( EQ_HTM_CTRL                                             , RULL(0x10012605), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012705, 10012205, 10012305,
+REG64( EQ_0_HTM_CTRL                                           , RULL(0x10012605), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012705, 10012205, 10012305,
+REG64( EQ_1_HTM_CTRL                                           , RULL(0x11012605), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012705, 11012205, 11012305,
+REG64( EQ_2_HTM_CTRL                                           , RULL(0x12012605), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012705, 12012205, 12012305,
+REG64( EQ_3_HTM_CTRL                                           , RULL(0x13012605), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012705, 13012205, 13012305,
+REG64( EQ_4_HTM_CTRL                                           , RULL(0x14012605), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012705, 14012205, 14012305,
+REG64( EQ_5_HTM_CTRL                                           , RULL(0x15012605), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012705, 15012205, 15012305,
+REG64( EX_HTM_CTRL                                             , RULL(0x10012205), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012305,
+REG64( EX_0_HTM_CTRL                                           , RULL(0x10012205), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012305,
+REG64( EX_2_HTM_CTRL                                           , RULL(0x11012205), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012305,
+REG64( EX_4_HTM_CTRL                                           , RULL(0x12012205), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012305,
+REG64( EX_6_HTM_CTRL                                           , RULL(0x13012205), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012305,
+REG64( EX_8_HTM_CTRL                                           , RULL(0x14012205), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012305,
+REG64( EX_10_HTM_CTRL                                          , RULL(0x15012205), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012305,
+REG64( EX_11_CHTMLBS0_HTM_CTRL                                 , RULL(0x15012605), SH_UNT_EX_11_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_11_CHTMLBS1_HTM_CTRL                                 , RULL(0x15012705), SH_UNT_EX_11_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_1_CHTMLBS0_HTM_CTRL                                  , RULL(0x10012605), SH_UNT_EX_1_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_1_CHTMLBS1_HTM_CTRL                                  , RULL(0x10012705), SH_UNT_EX_1_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_3_CHTMLBS0_HTM_CTRL                                  , RULL(0x11012605), SH_UNT_EX_3_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_3_CHTMLBS1_HTM_CTRL                                  , RULL(0x11012705), SH_UNT_EX_3_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_5_CHTMLBS0_HTM_CTRL                                  , RULL(0x12012605), SH_UNT_EX_5_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_5_CHTMLBS1_HTM_CTRL                                  , RULL(0x12012705), SH_UNT_EX_5_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_7_CHTMLBS0_HTM_CTRL                                  , RULL(0x13012605), SH_UNT_EX_7_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_7_CHTMLBS1_HTM_CTRL                                  , RULL(0x13012705), SH_UNT_EX_7_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_9_CHTMLBS0_HTM_CTRL                                  , RULL(0x14012605), SH_UNT_EX_9_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_9_CHTMLBS1_HTM_CTRL                                  , RULL(0x14012705), SH_UNT_EX_9_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+
+REG64( EQ_HTM_IMA_PDBAR                                        , RULL(0x1001260B), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001270B, 1001220B, 1001230B,
+REG64( EQ_0_HTM_IMA_PDBAR                                      , RULL(0x1001260B), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001270B, 1001220B, 1001230B,
+REG64( EQ_1_HTM_IMA_PDBAR                                      , RULL(0x1101260B), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1101270B, 1101220B, 1101230B,
+REG64( EQ_2_HTM_IMA_PDBAR                                      , RULL(0x1201260B), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1201270B, 1201220B, 1201230B,
+REG64( EQ_3_HTM_IMA_PDBAR                                      , RULL(0x1301260B), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1301270B, 1301220B, 1301230B,
+REG64( EQ_4_HTM_IMA_PDBAR                                      , RULL(0x1401260B), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1401270B, 1401220B, 1401230B,
+REG64( EQ_5_HTM_IMA_PDBAR                                      , RULL(0x1501260B), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1501270B, 1501220B, 1501230B,
+REG64( EX_HTM_IMA_PDBAR                                        , RULL(0x1001220B), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001230B,
+REG64( EX_0_HTM_IMA_PDBAR                                      , RULL(0x1001220B), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1001230B,
+REG64( EX_2_HTM_IMA_PDBAR                                      , RULL(0x1101220B), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1101230B,
+REG64( EX_4_HTM_IMA_PDBAR                                      , RULL(0x1201220B), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1201230B,
+REG64( EX_6_HTM_IMA_PDBAR                                      , RULL(0x1301220B), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1301230B,
+REG64( EX_8_HTM_IMA_PDBAR                                      , RULL(0x1401220B), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1401230B,
+REG64( EX_10_HTM_IMA_PDBAR                                     , RULL(0x1501220B), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 1501230B,
+REG64( EX_11_CHTMLBS0_HTM_IMA_PDBAR                            , RULL(0x1501260B), SH_UNT_EX_11_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_11_CHTMLBS1_HTM_IMA_PDBAR                            , RULL(0x1501270B), SH_UNT_EX_11_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_1_CHTMLBS0_HTM_IMA_PDBAR                             , RULL(0x1001260B), SH_UNT_EX_1_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_1_CHTMLBS1_HTM_IMA_PDBAR                             , RULL(0x1001270B), SH_UNT_EX_1_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_3_CHTMLBS0_HTM_IMA_PDBAR                             , RULL(0x1101260B), SH_UNT_EX_3_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_3_CHTMLBS1_HTM_IMA_PDBAR                             , RULL(0x1101270B), SH_UNT_EX_3_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_5_CHTMLBS0_HTM_IMA_PDBAR                             , RULL(0x1201260B), SH_UNT_EX_5_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_5_CHTMLBS1_HTM_IMA_PDBAR                             , RULL(0x1201270B), SH_UNT_EX_5_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_7_CHTMLBS0_HTM_IMA_PDBAR                             , RULL(0x1301260B), SH_UNT_EX_7_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_7_CHTMLBS1_HTM_IMA_PDBAR                             , RULL(0x1301270B), SH_UNT_EX_7_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_9_CHTMLBS0_HTM_IMA_PDBAR                             , RULL(0x1401260B), SH_UNT_EX_9_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_9_CHTMLBS1_HTM_IMA_PDBAR                             , RULL(0x1401270B), SH_UNT_EX_9_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+
+REG64( EQ_HTM_IMA_STATUS                                       , RULL(0x1001260A), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001270A, 1001220A, 1001230A,
+REG64( EQ_0_HTM_IMA_STATUS                                     , RULL(0x1001260A), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001270A, 1001220A, 1001230A,
+REG64( EQ_1_HTM_IMA_STATUS                                     , RULL(0x1101260A), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1101270A, 1101220A, 1101230A,
+REG64( EQ_2_HTM_IMA_STATUS                                     , RULL(0x1201260A), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1201270A, 1201220A, 1201230A,
+REG64( EQ_3_HTM_IMA_STATUS                                     , RULL(0x1301260A), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1301270A, 1301220A, 1301230A,
+REG64( EQ_4_HTM_IMA_STATUS                                     , RULL(0x1401260A), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1401270A, 1401220A, 1401230A,
+REG64( EQ_5_HTM_IMA_STATUS                                     , RULL(0x1501260A), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1501270A, 1501220A, 1501230A,
+REG64( EX_HTM_IMA_STATUS                                       , RULL(0x1001220A), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001230A,
+REG64( EX_0_HTM_IMA_STATUS                                     , RULL(0x1001220A), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1001230A,
+REG64( EX_2_HTM_IMA_STATUS                                     , RULL(0x1101220A), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1101230A,
+REG64( EX_4_HTM_IMA_STATUS                                     , RULL(0x1201220A), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1201230A,
+REG64( EX_6_HTM_IMA_STATUS                                     , RULL(0x1301220A), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1301230A,
+REG64( EX_8_HTM_IMA_STATUS                                     , RULL(0x1401220A), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1401230A,
+REG64( EX_10_HTM_IMA_STATUS                                    , RULL(0x1501220A), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 1501230A,
+REG64( EX_11_CHTMLBS0_HTM_IMA_STATUS                           , RULL(0x1501260A), SH_UNT_EX_11_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_11_CHTMLBS1_HTM_IMA_STATUS                           , RULL(0x1501270A), SH_UNT_EX_11_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+REG64( EX_1_CHTMLBS0_HTM_IMA_STATUS                            , RULL(0x1001260A), SH_UNT_EX_1_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_1_CHTMLBS1_HTM_IMA_STATUS                            , RULL(0x1001270A), SH_UNT_EX_1_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+REG64( EX_3_CHTMLBS0_HTM_IMA_STATUS                            , RULL(0x1101260A), SH_UNT_EX_3_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_3_CHTMLBS1_HTM_IMA_STATUS                            , RULL(0x1101270A), SH_UNT_EX_3_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+REG64( EX_5_CHTMLBS0_HTM_IMA_STATUS                            , RULL(0x1201260A), SH_UNT_EX_5_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_5_CHTMLBS1_HTM_IMA_STATUS                            , RULL(0x1201270A), SH_UNT_EX_5_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+REG64( EX_7_CHTMLBS0_HTM_IMA_STATUS                            , RULL(0x1301260A), SH_UNT_EX_7_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_7_CHTMLBS1_HTM_IMA_STATUS                            , RULL(0x1301270A), SH_UNT_EX_7_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+REG64( EX_9_CHTMLBS0_HTM_IMA_STATUS                            , RULL(0x1401260A), SH_UNT_EX_9_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_9_CHTMLBS1_HTM_IMA_STATUS                            , RULL(0x1401270A), SH_UNT_EX_9_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+
+REG64( EQ_HTM_LAST                                             , RULL(0x10012603), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012703, 10012203, 10012303,
+REG64( EQ_0_HTM_LAST                                           , RULL(0x10012603), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012703, 10012203, 10012303,
+REG64( EQ_1_HTM_LAST                                           , RULL(0x11012603), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012703, 11012203, 11012303,
+REG64( EQ_2_HTM_LAST                                           , RULL(0x12012603), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012703, 12012203, 12012303,
+REG64( EQ_3_HTM_LAST                                           , RULL(0x13012603), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012703, 13012203, 13012303,
+REG64( EQ_4_HTM_LAST                                           , RULL(0x14012603), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012703, 14012203, 14012303,
+REG64( EQ_5_HTM_LAST                                           , RULL(0x15012603), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012703, 15012203, 15012303,
+REG64( EX_HTM_LAST                                             , RULL(0x10012203), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012303,
+REG64( EX_0_HTM_LAST                                           , RULL(0x10012203), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012303,
+REG64( EX_2_HTM_LAST                                           , RULL(0x11012203), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012303,
+REG64( EX_4_HTM_LAST                                           , RULL(0x12012203), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012303,
+REG64( EX_6_HTM_LAST                                           , RULL(0x13012203), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012303,
+REG64( EX_8_HTM_LAST                                           , RULL(0x14012203), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012303,
+REG64( EX_10_HTM_LAST                                          , RULL(0x15012203), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012303,
+REG64( EX_11_CHTMLBS0_HTM_LAST                                 , RULL(0x15012603), SH_UNT_EX_11_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_11_CHTMLBS1_HTM_LAST                                 , RULL(0x15012703), SH_UNT_EX_11_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+REG64( EX_1_CHTMLBS0_HTM_LAST                                  , RULL(0x10012603), SH_UNT_EX_1_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_1_CHTMLBS1_HTM_LAST                                  , RULL(0x10012703), SH_UNT_EX_1_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+REG64( EX_3_CHTMLBS0_HTM_LAST                                  , RULL(0x11012603), SH_UNT_EX_3_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_3_CHTMLBS1_HTM_LAST                                  , RULL(0x11012703), SH_UNT_EX_3_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+REG64( EX_5_CHTMLBS0_HTM_LAST                                  , RULL(0x12012603), SH_UNT_EX_5_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_5_CHTMLBS1_HTM_LAST                                  , RULL(0x12012703), SH_UNT_EX_5_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+REG64( EX_7_CHTMLBS0_HTM_LAST                                  , RULL(0x13012603), SH_UNT_EX_7_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_7_CHTMLBS1_HTM_LAST                                  , RULL(0x13012703), SH_UNT_EX_7_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+REG64( EX_9_CHTMLBS0_HTM_LAST                                  , RULL(0x14012603), SH_UNT_EX_9_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_9_CHTMLBS1_HTM_LAST                                  , RULL(0x14012703), SH_UNT_EX_9_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+
+REG64( EQ_HTM_MEM                                              , RULL(0x10012601), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012701, 10012201, 10012301,
+REG64( EQ_0_HTM_MEM                                            , RULL(0x10012601), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012701, 10012201, 10012301,
+REG64( EQ_1_HTM_MEM                                            , RULL(0x11012601), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012701, 11012201, 11012301,
+REG64( EQ_2_HTM_MEM                                            , RULL(0x12012601), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012701, 12012201, 12012301,
+REG64( EQ_3_HTM_MEM                                            , RULL(0x13012601), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012701, 13012201, 13012301,
+REG64( EQ_4_HTM_MEM                                            , RULL(0x14012601), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012701, 14012201, 14012301,
+REG64( EQ_5_HTM_MEM                                            , RULL(0x15012601), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012701, 15012201, 15012301,
+REG64( EX_HTM_MEM                                              , RULL(0x10012201), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012301,
+REG64( EX_0_HTM_MEM                                            , RULL(0x10012201), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012301,
+REG64( EX_2_HTM_MEM                                            , RULL(0x11012201), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012301,
+REG64( EX_4_HTM_MEM                                            , RULL(0x12012201), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012301,
+REG64( EX_6_HTM_MEM                                            , RULL(0x13012201), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012301,
+REG64( EX_8_HTM_MEM                                            , RULL(0x14012201), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012301,
+REG64( EX_10_HTM_MEM                                           , RULL(0x15012201), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012301,
+REG64( EX_11_CHTMLBS0_HTM_MEM                                  , RULL(0x15012601), SH_UNT_EX_11_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_11_CHTMLBS1_HTM_MEM                                  , RULL(0x15012701), SH_UNT_EX_11_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_1_CHTMLBS0_HTM_MEM                                   , RULL(0x10012601), SH_UNT_EX_1_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_1_CHTMLBS1_HTM_MEM                                   , RULL(0x10012701), SH_UNT_EX_1_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_3_CHTMLBS0_HTM_MEM                                   , RULL(0x11012601), SH_UNT_EX_3_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_3_CHTMLBS1_HTM_MEM                                   , RULL(0x11012701), SH_UNT_EX_3_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_5_CHTMLBS0_HTM_MEM                                   , RULL(0x12012601), SH_UNT_EX_5_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_5_CHTMLBS1_HTM_MEM                                   , RULL(0x12012701), SH_UNT_EX_5_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_7_CHTMLBS0_HTM_MEM                                   , RULL(0x13012601), SH_UNT_EX_7_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_7_CHTMLBS1_HTM_MEM                                   , RULL(0x13012701), SH_UNT_EX_7_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_9_CHTMLBS0_HTM_MEM                                   , RULL(0x14012601), SH_UNT_EX_9_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_9_CHTMLBS1_HTM_MEM                                   , RULL(0x14012701), SH_UNT_EX_9_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+
+REG64( EQ_HTM_MODE                                             , RULL(0x10012600), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012700, 10012200, 10012300,
+REG64( EQ_0_HTM_MODE                                           , RULL(0x10012600), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012700, 10012200, 10012300,
+REG64( EQ_1_HTM_MODE                                           , RULL(0x11012600), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012700, 11012200, 11012300,
+REG64( EQ_2_HTM_MODE                                           , RULL(0x12012600), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012700, 12012200, 12012300,
+REG64( EQ_3_HTM_MODE                                           , RULL(0x13012600), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012700, 13012200, 13012300,
+REG64( EQ_4_HTM_MODE                                           , RULL(0x14012600), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012700, 14012200, 14012300,
+REG64( EQ_5_HTM_MODE                                           , RULL(0x15012600), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012700, 15012200, 15012300,
+REG64( EX_HTM_MODE                                             , RULL(0x10012200), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012300,
+REG64( EX_0_HTM_MODE                                           , RULL(0x10012200), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012300,
+REG64( EX_2_HTM_MODE                                           , RULL(0x11012200), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012300,
+REG64( EX_4_HTM_MODE                                           , RULL(0x12012200), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012300,
+REG64( EX_6_HTM_MODE                                           , RULL(0x13012200), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012300,
+REG64( EX_8_HTM_MODE                                           , RULL(0x14012200), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012300,
+REG64( EX_10_HTM_MODE                                          , RULL(0x15012200), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012300,
+REG64( EX_11_CHTMLBS0_HTM_MODE                                 , RULL(0x15012600), SH_UNT_EX_11_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_11_CHTMLBS1_HTM_MODE                                 , RULL(0x15012700), SH_UNT_EX_11_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_1_CHTMLBS0_HTM_MODE                                  , RULL(0x10012600), SH_UNT_EX_1_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_1_CHTMLBS1_HTM_MODE                                  , RULL(0x10012700), SH_UNT_EX_1_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_3_CHTMLBS0_HTM_MODE                                  , RULL(0x11012600), SH_UNT_EX_3_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_3_CHTMLBS1_HTM_MODE                                  , RULL(0x11012700), SH_UNT_EX_3_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_5_CHTMLBS0_HTM_MODE                                  , RULL(0x12012600), SH_UNT_EX_5_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_5_CHTMLBS1_HTM_MODE                                  , RULL(0x12012700), SH_UNT_EX_5_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_7_CHTMLBS0_HTM_MODE                                  , RULL(0x13012600), SH_UNT_EX_7_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_7_CHTMLBS1_HTM_MODE                                  , RULL(0x13012700), SH_UNT_EX_7_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_9_CHTMLBS0_HTM_MODE                                  , RULL(0x14012600), SH_UNT_EX_9_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_9_CHTMLBS1_HTM_MODE                                  , RULL(0x14012700), SH_UNT_EX_9_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+
+REG64( EQ_HTM_STAT                                             , RULL(0x10012602), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012702, 10012202, 10012302,
+REG64( EQ_0_HTM_STAT                                           , RULL(0x10012602), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012702, 10012202, 10012302,
+REG64( EQ_1_HTM_STAT                                           , RULL(0x11012602), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012702, 11012202, 11012302,
+REG64( EQ_2_HTM_STAT                                           , RULL(0x12012602), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012702, 12012202, 12012302,
+REG64( EQ_3_HTM_STAT                                           , RULL(0x13012602), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012702, 13012202, 13012302,
+REG64( EQ_4_HTM_STAT                                           , RULL(0x14012602), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012702, 14012202, 14012302,
+REG64( EQ_5_HTM_STAT                                           , RULL(0x15012602), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012702, 15012202, 15012302,
+REG64( EX_HTM_STAT                                             , RULL(0x10012202), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012302,
+REG64( EX_0_HTM_STAT                                           , RULL(0x10012202), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012302,
+REG64( EX_2_HTM_STAT                                           , RULL(0x11012202), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012302,
+REG64( EX_4_HTM_STAT                                           , RULL(0x12012202), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012302,
+REG64( EX_6_HTM_STAT                                           , RULL(0x13012202), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012302,
+REG64( EX_8_HTM_STAT                                           , RULL(0x14012202), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012302,
+REG64( EX_10_HTM_STAT                                          , RULL(0x15012202), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012302,
+REG64( EX_11_CHTMLBS0_HTM_STAT                                 , RULL(0x15012602), SH_UNT_EX_11_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_11_CHTMLBS1_HTM_STAT                                 , RULL(0x15012702), SH_UNT_EX_11_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+REG64( EX_1_CHTMLBS0_HTM_STAT                                  , RULL(0x10012602), SH_UNT_EX_1_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_1_CHTMLBS1_HTM_STAT                                  , RULL(0x10012702), SH_UNT_EX_1_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+REG64( EX_3_CHTMLBS0_HTM_STAT                                  , RULL(0x11012602), SH_UNT_EX_3_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_3_CHTMLBS1_HTM_STAT                                  , RULL(0x11012702), SH_UNT_EX_3_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+REG64( EX_5_CHTMLBS0_HTM_STAT                                  , RULL(0x12012602), SH_UNT_EX_5_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_5_CHTMLBS1_HTM_STAT                                  , RULL(0x12012702), SH_UNT_EX_5_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+REG64( EX_7_CHTMLBS0_HTM_STAT                                  , RULL(0x13012602), SH_UNT_EX_7_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_7_CHTMLBS1_HTM_STAT                                  , RULL(0x13012702), SH_UNT_EX_7_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+REG64( EX_9_CHTMLBS0_HTM_STAT                                  , RULL(0x14012602), SH_UNT_EX_9_CHTMLBS0,
+       SH_ACS_SCOM_RO   );
+REG64( EX_9_CHTMLBS1_HTM_STAT                                  , RULL(0x14012702), SH_UNT_EX_9_CHTMLBS1,
+       SH_ACS_SCOM_RO   );
+
+REG64( EQ_HTM_TRIG                                             , RULL(0x10012604), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012704, 10012204, 10012304,
+REG64( EQ_0_HTM_TRIG                                           , RULL(0x10012604), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012704, 10012204, 10012304,
+REG64( EQ_1_HTM_TRIG                                           , RULL(0x11012604), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012704, 11012204, 11012304,
+REG64( EQ_2_HTM_TRIG                                           , RULL(0x12012604), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012704, 12012204, 12012304,
+REG64( EQ_3_HTM_TRIG                                           , RULL(0x13012604), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012704, 13012204, 13012304,
+REG64( EQ_4_HTM_TRIG                                           , RULL(0x14012604), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012704, 14012204, 14012304,
+REG64( EQ_5_HTM_TRIG                                           , RULL(0x15012604), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012704, 15012204, 15012304,
+REG64( EX_HTM_TRIG                                             , RULL(0x10012204), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012304,
+REG64( EX_0_HTM_TRIG                                           , RULL(0x10012204), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 10012304,
+REG64( EX_2_HTM_TRIG                                           , RULL(0x11012204), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 11012304,
+REG64( EX_4_HTM_TRIG                                           , RULL(0x12012204), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 12012304,
+REG64( EX_6_HTM_TRIG                                           , RULL(0x13012204), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 13012304,
+REG64( EX_8_HTM_TRIG                                           , RULL(0x14012204), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 14012304,
+REG64( EX_10_HTM_TRIG                                          , RULL(0x15012204), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 15012304,
+REG64( EX_11_CHTMLBS0_HTM_TRIG                                 , RULL(0x15012604), SH_UNT_EX_11_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_11_CHTMLBS1_HTM_TRIG                                 , RULL(0x15012704), SH_UNT_EX_11_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_1_CHTMLBS0_HTM_TRIG                                  , RULL(0x10012604), SH_UNT_EX_1_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_1_CHTMLBS1_HTM_TRIG                                  , RULL(0x10012704), SH_UNT_EX_1_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_3_CHTMLBS0_HTM_TRIG                                  , RULL(0x11012604), SH_UNT_EX_3_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_3_CHTMLBS1_HTM_TRIG                                  , RULL(0x11012704), SH_UNT_EX_3_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_5_CHTMLBS0_HTM_TRIG                                  , RULL(0x12012604), SH_UNT_EX_5_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_5_CHTMLBS1_HTM_TRIG                                  , RULL(0x12012704), SH_UNT_EX_5_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_7_CHTMLBS0_HTM_TRIG                                  , RULL(0x13012604), SH_UNT_EX_7_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_7_CHTMLBS1_HTM_TRIG                                  , RULL(0x13012704), SH_UNT_EX_7_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+REG64( EX_9_CHTMLBS0_HTM_TRIG                                  , RULL(0x14012604), SH_UNT_EX_9_CHTMLBS0,
+       SH_ACS_SCOM_RW   );
+REG64( EX_9_CHTMLBS1_HTM_TRIG                                  , RULL(0x14012704), SH_UNT_EX_9_CHTMLBS1,
+       SH_ACS_SCOM_RW   );
+
+REG64( C_HV_STATE                                              , RULL(0x20010AA6), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_HV_STATE                                            , RULL(0x20010AA6), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_HV_STATE                                            , RULL(0x21010AA6), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_HV_STATE                                            , RULL(0x22010AA6), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_HV_STATE                                            , RULL(0x23010AA6), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_HV_STATE                                            , RULL(0x24010AA6), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_HV_STATE                                            , RULL(0x25010AA6), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_HV_STATE                                            , RULL(0x26010AA6), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_HV_STATE                                            , RULL(0x27010AA6), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_HV_STATE                                            , RULL(0x28010AA6), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_HV_STATE                                            , RULL(0x29010AA6), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_HV_STATE                                           , RULL(0x2A010AA6), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_HV_STATE                                           , RULL(0x2B010AA6), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_HV_STATE                                           , RULL(0x2C010AA6), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_HV_STATE                                           , RULL(0x2D010AA6), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_HV_STATE                                           , RULL(0x2E010AA6), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_HV_STATE                                           , RULL(0x2F010AA6), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_HV_STATE                                           , RULL(0x30010AA6), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_HV_STATE                                           , RULL(0x31010AA6), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_HV_STATE                                           , RULL(0x32010AA6), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_HV_STATE                                           , RULL(0x33010AA6), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_HV_STATE                                           , RULL(0x34010AA6), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_HV_STATE                                           , RULL(0x35010AA6), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_HV_STATE                                           , RULL(0x36010AA6), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_HV_STATE                                           , RULL(0x37010AA6), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_0_L2_HV_STATE                                        , RULL(0x20010AA6), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010AA6,
+REG64( EX_10_L2_HV_STATE                                       , RULL(0x34010AA6), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35010AA6,
+REG64( EX_11_L2_HV_STATE                                       , RULL(0x36010AA6), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37010AA6,
+REG64( EX_1_L2_HV_STATE                                        , RULL(0x22010AA6), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23010AA6,
+REG64( EX_2_L2_HV_STATE                                        , RULL(0x24010AA6), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25010AA6,
+REG64( EX_3_L2_HV_STATE                                        , RULL(0x26010AA6), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27010AA6,
+REG64( EX_4_L2_HV_STATE                                        , RULL(0x28010AA6), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29010AA6,
+REG64( EX_5_L2_HV_STATE                                        , RULL(0x2A010AA6), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B010AA6,
+REG64( EX_6_L2_HV_STATE                                        , RULL(0x2C010AA6), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D010AA6,
+REG64( EX_7_L2_HV_STATE                                        , RULL(0x2E010AA6), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F010AA6,
+REG64( EX_8_L2_HV_STATE                                        , RULL(0x30010AA6), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31010AA6,
+REG64( EX_9_L2_HV_STATE                                        , RULL(0x32010AA6), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33010AA6,
+REG64( EX_L2_HV_STATE                                          , RULL(0x20010AA6), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010AA6,
+
+REG64( C_IMA_EVENT_MASK                                        , RULL(0x20010AA8), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_IMA_EVENT_MASK                                      , RULL(0x20010AA8), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_IMA_EVENT_MASK                                      , RULL(0x21010AA8), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_IMA_EVENT_MASK                                      , RULL(0x22010AA8), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_IMA_EVENT_MASK                                      , RULL(0x23010AA8), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_IMA_EVENT_MASK                                      , RULL(0x24010AA8), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_IMA_EVENT_MASK                                      , RULL(0x25010AA8), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_IMA_EVENT_MASK                                      , RULL(0x26010AA8), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_IMA_EVENT_MASK                                      , RULL(0x27010AA8), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_IMA_EVENT_MASK                                      , RULL(0x28010AA8), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_IMA_EVENT_MASK                                      , RULL(0x29010AA8), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_IMA_EVENT_MASK                                     , RULL(0x2A010AA8), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_IMA_EVENT_MASK                                     , RULL(0x2B010AA8), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_IMA_EVENT_MASK                                     , RULL(0x2C010AA8), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_IMA_EVENT_MASK                                     , RULL(0x2D010AA8), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_IMA_EVENT_MASK                                     , RULL(0x2E010AA8), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_IMA_EVENT_MASK                                     , RULL(0x2F010AA8), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_IMA_EVENT_MASK                                     , RULL(0x30010AA8), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_IMA_EVENT_MASK                                     , RULL(0x31010AA8), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_IMA_EVENT_MASK                                     , RULL(0x32010AA8), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_IMA_EVENT_MASK                                     , RULL(0x33010AA8), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_IMA_EVENT_MASK                                     , RULL(0x34010AA8), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_IMA_EVENT_MASK                                     , RULL(0x35010AA8), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_IMA_EVENT_MASK                                     , RULL(0x36010AA8), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_IMA_EVENT_MASK                                     , RULL(0x37010AA8), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_IMA_EVENT_MASK                                       , RULL(0x20010AA8), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010AA8,
+REG64( EX_0_IMA_EVENT_MASK                                     , RULL(0x20010AA8), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010AA8,
+REG64( EX_1_IMA_EVENT_MASK                                     , RULL(0x22010AA8), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010AA8,
+REG64( EX_2_IMA_EVENT_MASK                                     , RULL(0x24010AA8), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010AA8,
+REG64( EX_3_IMA_EVENT_MASK                                     , RULL(0x26010AA8), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010AA8,
+REG64( EX_4_IMA_EVENT_MASK                                     , RULL(0x28010AA8), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010AA8,
+REG64( EX_5_IMA_EVENT_MASK                                     , RULL(0x2A010AA8), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010AA8,
+REG64( EX_6_IMA_EVENT_MASK                                     , RULL(0x2C010AA8), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010AA8,
+REG64( EX_7_IMA_EVENT_MASK                                     , RULL(0x2E010AA8), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010AA8,
+REG64( EX_8_IMA_EVENT_MASK                                     , RULL(0x30010AA8), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010AA8,
+REG64( EX_9_IMA_EVENT_MASK                                     , RULL(0x32010AA8), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010AA8,
+REG64( EX_10_IMA_EVENT_MASK                                    , RULL(0x34010AA8), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010AA8,
+REG64( EX_11_IMA_EVENT_MASK                                    , RULL(0x36010AA8), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010AA8,
+
+REG64( C_IMA_TRACE                                             , RULL(0x20010AA9), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_IMA_TRACE                                           , RULL(0x20010AA9), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_IMA_TRACE                                           , RULL(0x21010AA9), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_IMA_TRACE                                           , RULL(0x22010AA9), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_IMA_TRACE                                           , RULL(0x23010AA9), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_IMA_TRACE                                           , RULL(0x24010AA9), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_IMA_TRACE                                           , RULL(0x25010AA9), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_IMA_TRACE                                           , RULL(0x26010AA9), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_IMA_TRACE                                           , RULL(0x27010AA9), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_IMA_TRACE                                           , RULL(0x28010AA9), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_IMA_TRACE                                           , RULL(0x29010AA9), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_IMA_TRACE                                          , RULL(0x2A010AA9), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_IMA_TRACE                                          , RULL(0x2B010AA9), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_IMA_TRACE                                          , RULL(0x2C010AA9), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_IMA_TRACE                                          , RULL(0x2D010AA9), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_IMA_TRACE                                          , RULL(0x2E010AA9), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_IMA_TRACE                                          , RULL(0x2F010AA9), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_IMA_TRACE                                          , RULL(0x30010AA9), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_IMA_TRACE                                          , RULL(0x31010AA9), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_IMA_TRACE                                          , RULL(0x32010AA9), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_IMA_TRACE                                          , RULL(0x33010AA9), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_IMA_TRACE                                          , RULL(0x34010AA9), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_IMA_TRACE                                          , RULL(0x35010AA9), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_IMA_TRACE                                          , RULL(0x36010AA9), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_IMA_TRACE                                          , RULL(0x37010AA9), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_IMA_TRACE                                            , RULL(0x20010AA9), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010AA9,
+REG64( EX_0_IMA_TRACE                                          , RULL(0x20010AA9), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010AA9,
+REG64( EX_1_IMA_TRACE                                          , RULL(0x22010AA9), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010AA9,
+REG64( EX_2_IMA_TRACE                                          , RULL(0x24010AA9), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010AA9,
+REG64( EX_3_IMA_TRACE                                          , RULL(0x26010AA9), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010AA9,
+REG64( EX_4_IMA_TRACE                                          , RULL(0x28010AA9), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010AA9,
+REG64( EX_5_IMA_TRACE                                          , RULL(0x2A010AA9), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010AA9,
+REG64( EX_6_IMA_TRACE                                          , RULL(0x2C010AA9), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010AA9,
+REG64( EX_7_IMA_TRACE                                          , RULL(0x2E010AA9), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010AA9,
+REG64( EX_8_IMA_TRACE                                          , RULL(0x30010AA9), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010AA9,
+REG64( EX_9_IMA_TRACE                                          , RULL(0x32010AA9), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010AA9,
+REG64( EX_10_IMA_TRACE                                         , RULL(0x34010AA9), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010AA9,
+REG64( EX_11_IMA_TRACE                                         , RULL(0x36010AA9), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010AA9,
+
+REG64( C_INJECT_REG                                            , RULL(0x20050011), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_INJECT_REG                                          , RULL(0x20050011), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_INJECT_REG                                          , RULL(0x21050011), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_INJECT_REG                                          , RULL(0x22050011), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_INJECT_REG                                          , RULL(0x23050011), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_INJECT_REG                                          , RULL(0x24050011), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_INJECT_REG                                          , RULL(0x25050011), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_INJECT_REG                                          , RULL(0x26050011), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_INJECT_REG                                          , RULL(0x27050011), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_INJECT_REG                                          , RULL(0x28050011), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_INJECT_REG                                          , RULL(0x29050011), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_INJECT_REG                                         , RULL(0x2A050011), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_INJECT_REG                                         , RULL(0x2B050011), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_INJECT_REG                                         , RULL(0x2C050011), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_INJECT_REG                                         , RULL(0x2D050011), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_INJECT_REG                                         , RULL(0x2E050011), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_INJECT_REG                                         , RULL(0x2F050011), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_INJECT_REG                                         , RULL(0x30050011), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_INJECT_REG                                         , RULL(0x31050011), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_INJECT_REG                                         , RULL(0x32050011), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_INJECT_REG                                         , RULL(0x33050011), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_INJECT_REG                                         , RULL(0x34050011), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_INJECT_REG                                         , RULL(0x35050011), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_INJECT_REG                                         , RULL(0x36050011), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_INJECT_REG                                         , RULL(0x37050011), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_INJECT_REG                                           , RULL(0x10050011), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_INJECT_REG                                         , RULL(0x10050011), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_INJECT_REG                                         , RULL(0x11050011), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_INJECT_REG                                         , RULL(0x12050011), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_INJECT_REG                                         , RULL(0x13050011), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_INJECT_REG                                         , RULL(0x14050011), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_INJECT_REG                                         , RULL(0x15050011), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_INJECT_REG                                           , RULL(0x20050011), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21050011,
+REG64( EX_0_INJECT_REG                                         , RULL(0x20050011), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21050011,
+REG64( EX_1_INJECT_REG                                         , RULL(0x22050011), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23050011,
+REG64( EX_2_INJECT_REG                                         , RULL(0x24050011), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25050011,
+REG64( EX_3_INJECT_REG                                         , RULL(0x26050011), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27050011,
+REG64( EX_4_INJECT_REG                                         , RULL(0x28050011), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29050011,
+REG64( EX_5_INJECT_REG                                         , RULL(0x2A050011), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B050011,
+REG64( EX_6_INJECT_REG                                         , RULL(0x2C050011), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D050011,
+REG64( EX_7_INJECT_REG                                         , RULL(0x2E050011), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F050011,
+REG64( EX_8_INJECT_REG                                         , RULL(0x30050011), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31050011,
+REG64( EX_9_INJECT_REG                                         , RULL(0x32050011), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33050011,
+REG64( EX_10_INJECT_REG                                        , RULL(0x34050011), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35050011,
+REG64( EX_11_INJECT_REG                                        , RULL(0x36050011), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37050011,
+
+REG64( EQ_INJ_REG                                              , RULL(0x1001100D), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 1001140D,
+REG64( EQ_0_INJ_REG                                            , RULL(0x1001100D), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 1001140D,
+REG64( EQ_1_INJ_REG                                            , RULL(0x1101100D), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 1101140D,
+REG64( EQ_2_INJ_REG                                            , RULL(0x1201100D), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 1201140D,
+REG64( EQ_3_INJ_REG                                            , RULL(0x1301100D), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 1301140D,
+REG64( EQ_4_INJ_REG                                            , RULL(0x1401100D), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 1401140D,
+REG64( EQ_5_INJ_REG                                            , RULL(0x1501100D), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 1501140D,
+REG64( EX_INJ_REG                                              , RULL(0x1001100D), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_INJ_REG                                            , RULL(0x1001100D), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_INJ_REG                                            , RULL(0x1001140D), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_INJ_REG                                            , RULL(0x1101100D), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_INJ_REG                                            , RULL(0x1101140D), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_INJ_REG                                            , RULL(0x1201100D), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_INJ_REG                                            , RULL(0x1201140D), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_INJ_REG                                            , RULL(0x1301100D), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_INJ_REG                                            , RULL(0x1301140D), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_INJ_REG                                            , RULL(0x1401100D), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_INJ_REG                                            , RULL(0x1401140D), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_INJ_REG                                           , RULL(0x1501100D), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_INJ_REG                                           , RULL(0x1501140D), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( C_INV_ERATE                                             , RULL(0x20010AB4), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_INV_ERATE                                           , RULL(0x20010AB4), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_INV_ERATE                                           , RULL(0x21010AB4), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_INV_ERATE                                           , RULL(0x22010AB4), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_INV_ERATE                                           , RULL(0x23010AB4), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_INV_ERATE                                           , RULL(0x24010AB4), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_INV_ERATE                                           , RULL(0x25010AB4), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_INV_ERATE                                           , RULL(0x26010AB4), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_INV_ERATE                                           , RULL(0x27010AB4), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_INV_ERATE                                           , RULL(0x28010AB4), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_INV_ERATE                                           , RULL(0x29010AB4), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_INV_ERATE                                          , RULL(0x2A010AB4), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_INV_ERATE                                          , RULL(0x2B010AB4), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_INV_ERATE                                          , RULL(0x2C010AB4), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_INV_ERATE                                          , RULL(0x2D010AB4), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_INV_ERATE                                          , RULL(0x2E010AB4), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_INV_ERATE                                          , RULL(0x2F010AB4), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_INV_ERATE                                          , RULL(0x30010AB4), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_INV_ERATE                                          , RULL(0x31010AB4), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_INV_ERATE                                          , RULL(0x32010AB4), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_INV_ERATE                                          , RULL(0x33010AB4), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_INV_ERATE                                          , RULL(0x34010AB4), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_INV_ERATE                                          , RULL(0x35010AB4), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_INV_ERATE                                          , RULL(0x36010AB4), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_INV_ERATE                                          , RULL(0x37010AB4), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_INV_ERATE                                       , RULL(0x20010AB4), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010AB4,
+REG64( EX_10_L2_INV_ERATE                                      , RULL(0x34010AB4), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010AB4,
+REG64( EX_11_L2_INV_ERATE                                      , RULL(0x36010AB4), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010AB4,
+REG64( EX_1_L2_INV_ERATE                                       , RULL(0x22010AB4), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010AB4,
+REG64( EX_2_L2_INV_ERATE                                       , RULL(0x24010AB4), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010AB4,
+REG64( EX_3_L2_INV_ERATE                                       , RULL(0x26010AB4), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010AB4,
+REG64( EX_4_L2_INV_ERATE                                       , RULL(0x28010AB4), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010AB4,
+REG64( EX_5_L2_INV_ERATE                                       , RULL(0x2A010AB4), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010AB4,
+REG64( EX_6_L2_INV_ERATE                                       , RULL(0x2C010AB4), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010AB4,
+REG64( EX_7_L2_INV_ERATE                                       , RULL(0x2E010AB4), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010AB4,
+REG64( EX_8_L2_INV_ERATE                                       , RULL(0x30010AB4), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010AB4,
+REG64( EX_9_L2_INV_ERATE                                       , RULL(0x32010AB4), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010AB4,
+REG64( EX_L2_INV_ERATE                                         , RULL(0x20010AB4), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010AB4,
+
+REG64( C_ISU_DEBUG_CTRL                                        , RULL(0x20010C46), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_ISU_DEBUG_CTRL                                      , RULL(0x20010C46), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_ISU_DEBUG_CTRL                                      , RULL(0x21010C46), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_ISU_DEBUG_CTRL                                      , RULL(0x22010C46), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_ISU_DEBUG_CTRL                                      , RULL(0x23010C46), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_ISU_DEBUG_CTRL                                      , RULL(0x24010C46), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_ISU_DEBUG_CTRL                                      , RULL(0x25010C46), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_ISU_DEBUG_CTRL                                      , RULL(0x26010C46), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_ISU_DEBUG_CTRL                                      , RULL(0x27010C46), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_ISU_DEBUG_CTRL                                      , RULL(0x28010C46), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_ISU_DEBUG_CTRL                                      , RULL(0x29010C46), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_ISU_DEBUG_CTRL                                     , RULL(0x2A010C46), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_ISU_DEBUG_CTRL                                     , RULL(0x2B010C46), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_ISU_DEBUG_CTRL                                     , RULL(0x2C010C46), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_ISU_DEBUG_CTRL                                     , RULL(0x2D010C46), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_ISU_DEBUG_CTRL                                     , RULL(0x2E010C46), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_ISU_DEBUG_CTRL                                     , RULL(0x2F010C46), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_ISU_DEBUG_CTRL                                     , RULL(0x30010C46), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_ISU_DEBUG_CTRL                                     , RULL(0x31010C46), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_ISU_DEBUG_CTRL                                     , RULL(0x32010C46), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_ISU_DEBUG_CTRL                                     , RULL(0x33010C46), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_ISU_DEBUG_CTRL                                     , RULL(0x34010C46), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_ISU_DEBUG_CTRL                                     , RULL(0x35010C46), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_ISU_DEBUG_CTRL                                     , RULL(0x36010C46), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_ISU_DEBUG_CTRL                                     , RULL(0x37010C46), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_ISU_DEBUG_CTRL                                  , RULL(0x20010C46), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010C46,
+REG64( EX_10_L2_ISU_DEBUG_CTRL                                 , RULL(0x34010C46), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010C46,
+REG64( EX_11_L2_ISU_DEBUG_CTRL                                 , RULL(0x36010C46), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010C46,
+REG64( EX_1_L2_ISU_DEBUG_CTRL                                  , RULL(0x22010C46), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010C46,
+REG64( EX_2_L2_ISU_DEBUG_CTRL                                  , RULL(0x24010C46), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010C46,
+REG64( EX_3_L2_ISU_DEBUG_CTRL                                  , RULL(0x26010C46), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010C46,
+REG64( EX_4_L2_ISU_DEBUG_CTRL                                  , RULL(0x28010C46), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010C46,
+REG64( EX_5_L2_ISU_DEBUG_CTRL                                  , RULL(0x2A010C46), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010C46,
+REG64( EX_6_L2_ISU_DEBUG_CTRL                                  , RULL(0x2C010C46), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010C46,
+REG64( EX_7_L2_ISU_DEBUG_CTRL                                  , RULL(0x2E010C46), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010C46,
+REG64( EX_8_L2_ISU_DEBUG_CTRL                                  , RULL(0x30010C46), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010C46,
+REG64( EX_9_L2_ISU_DEBUG_CTRL                                  , RULL(0x32010C46), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010C46,
+REG64( EX_L2_ISU_DEBUG_CTRL                                    , RULL(0x20010C46), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010C46,
+
+REG64( C_ISU_REG0_HOLD_OUT                                     , RULL(0x20010C40), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_ISU_REG0_HOLD_OUT                                   , RULL(0x20010C40), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_ISU_REG0_HOLD_OUT                                   , RULL(0x21010C40), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_ISU_REG0_HOLD_OUT                                   , RULL(0x22010C40), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_ISU_REG0_HOLD_OUT                                   , RULL(0x23010C40), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_ISU_REG0_HOLD_OUT                                   , RULL(0x24010C40), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_ISU_REG0_HOLD_OUT                                   , RULL(0x25010C40), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_ISU_REG0_HOLD_OUT                                   , RULL(0x26010C40), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_ISU_REG0_HOLD_OUT                                   , RULL(0x27010C40), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_ISU_REG0_HOLD_OUT                                   , RULL(0x28010C40), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_ISU_REG0_HOLD_OUT                                   , RULL(0x29010C40), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_ISU_REG0_HOLD_OUT                                  , RULL(0x2A010C40), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_ISU_REG0_HOLD_OUT                                  , RULL(0x2B010C40), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_ISU_REG0_HOLD_OUT                                  , RULL(0x2C010C40), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_ISU_REG0_HOLD_OUT                                  , RULL(0x2D010C40), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_ISU_REG0_HOLD_OUT                                  , RULL(0x2E010C40), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_ISU_REG0_HOLD_OUT                                  , RULL(0x2F010C40), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_ISU_REG0_HOLD_OUT                                  , RULL(0x30010C40), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_ISU_REG0_HOLD_OUT                                  , RULL(0x31010C40), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_ISU_REG0_HOLD_OUT                                  , RULL(0x32010C40), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_ISU_REG0_HOLD_OUT                                  , RULL(0x33010C40), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_ISU_REG0_HOLD_OUT                                  , RULL(0x34010C40), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_ISU_REG0_HOLD_OUT                                  , RULL(0x35010C40), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_ISU_REG0_HOLD_OUT                                  , RULL(0x36010C40), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_ISU_REG0_HOLD_OUT                                  , RULL(0x37010C40), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_ISU_REG0_HOLD_OUT                               , RULL(0x20010C40), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010C40,
+REG64( EX_10_L2_ISU_REG0_HOLD_OUT                              , RULL(0x34010C40), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010C40,
+REG64( EX_11_L2_ISU_REG0_HOLD_OUT                              , RULL(0x36010C40), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010C40,
+REG64( EX_1_L2_ISU_REG0_HOLD_OUT                               , RULL(0x22010C40), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010C40,
+REG64( EX_2_L2_ISU_REG0_HOLD_OUT                               , RULL(0x24010C40), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010C40,
+REG64( EX_3_L2_ISU_REG0_HOLD_OUT                               , RULL(0x26010C40), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010C40,
+REG64( EX_4_L2_ISU_REG0_HOLD_OUT                               , RULL(0x28010C40), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010C40,
+REG64( EX_5_L2_ISU_REG0_HOLD_OUT                               , RULL(0x2A010C40), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010C40,
+REG64( EX_6_L2_ISU_REG0_HOLD_OUT                               , RULL(0x2C010C40), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010C40,
+REG64( EX_7_L2_ISU_REG0_HOLD_OUT                               , RULL(0x2E010C40), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010C40,
+REG64( EX_8_L2_ISU_REG0_HOLD_OUT                               , RULL(0x30010C40), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010C40,
+REG64( EX_9_L2_ISU_REG0_HOLD_OUT                               , RULL(0x32010C40), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010C40,
+REG64( EX_L2_ISU_REG0_HOLD_OUT                                 , RULL(0x20010C40), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010C40,
+
+REG64( C_ISU_REG1_HOLD_OUT                                     , RULL(0x20010C41), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_ISU_REG1_HOLD_OUT                                   , RULL(0x20010C41), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_ISU_REG1_HOLD_OUT                                   , RULL(0x21010C41), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_ISU_REG1_HOLD_OUT                                   , RULL(0x22010C41), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_ISU_REG1_HOLD_OUT                                   , RULL(0x23010C41), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_ISU_REG1_HOLD_OUT                                   , RULL(0x24010C41), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_ISU_REG1_HOLD_OUT                                   , RULL(0x25010C41), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_ISU_REG1_HOLD_OUT                                   , RULL(0x26010C41), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_ISU_REG1_HOLD_OUT                                   , RULL(0x27010C41), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_ISU_REG1_HOLD_OUT                                   , RULL(0x28010C41), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_ISU_REG1_HOLD_OUT                                   , RULL(0x29010C41), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_ISU_REG1_HOLD_OUT                                  , RULL(0x2A010C41), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_ISU_REG1_HOLD_OUT                                  , RULL(0x2B010C41), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_ISU_REG1_HOLD_OUT                                  , RULL(0x2C010C41), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_ISU_REG1_HOLD_OUT                                  , RULL(0x2D010C41), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_ISU_REG1_HOLD_OUT                                  , RULL(0x2E010C41), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_ISU_REG1_HOLD_OUT                                  , RULL(0x2F010C41), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_ISU_REG1_HOLD_OUT                                  , RULL(0x30010C41), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_ISU_REG1_HOLD_OUT                                  , RULL(0x31010C41), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_ISU_REG1_HOLD_OUT                                  , RULL(0x32010C41), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_ISU_REG1_HOLD_OUT                                  , RULL(0x33010C41), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_ISU_REG1_HOLD_OUT                                  , RULL(0x34010C41), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_ISU_REG1_HOLD_OUT                                  , RULL(0x35010C41), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_ISU_REG1_HOLD_OUT                                  , RULL(0x36010C41), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_ISU_REG1_HOLD_OUT                                  , RULL(0x37010C41), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_ISU_REG1_HOLD_OUT                               , RULL(0x20010C41), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010C41,
+REG64( EX_10_L2_ISU_REG1_HOLD_OUT                              , RULL(0x34010C41), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010C41,
+REG64( EX_11_L2_ISU_REG1_HOLD_OUT                              , RULL(0x36010C41), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010C41,
+REG64( EX_1_L2_ISU_REG1_HOLD_OUT                               , RULL(0x22010C41), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010C41,
+REG64( EX_2_L2_ISU_REG1_HOLD_OUT                               , RULL(0x24010C41), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010C41,
+REG64( EX_3_L2_ISU_REG1_HOLD_OUT                               , RULL(0x26010C41), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010C41,
+REG64( EX_4_L2_ISU_REG1_HOLD_OUT                               , RULL(0x28010C41), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010C41,
+REG64( EX_5_L2_ISU_REG1_HOLD_OUT                               , RULL(0x2A010C41), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010C41,
+REG64( EX_6_L2_ISU_REG1_HOLD_OUT                               , RULL(0x2C010C41), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010C41,
+REG64( EX_7_L2_ISU_REG1_HOLD_OUT                               , RULL(0x2E010C41), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010C41,
+REG64( EX_8_L2_ISU_REG1_HOLD_OUT                               , RULL(0x30010C41), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010C41,
+REG64( EX_9_L2_ISU_REG1_HOLD_OUT                               , RULL(0x32010C41), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010C41,
+REG64( EX_L2_ISU_REG1_HOLD_OUT                                 , RULL(0x20010C41), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010C41,
+
+REG64( C_ISU_REG2_HOLD_OUT                                     , RULL(0x20010C42), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_ISU_REG2_HOLD_OUT                                   , RULL(0x20010C42), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_ISU_REG2_HOLD_OUT                                   , RULL(0x21010C42), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_ISU_REG2_HOLD_OUT                                   , RULL(0x22010C42), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_ISU_REG2_HOLD_OUT                                   , RULL(0x23010C42), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_ISU_REG2_HOLD_OUT                                   , RULL(0x24010C42), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_ISU_REG2_HOLD_OUT                                   , RULL(0x25010C42), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_ISU_REG2_HOLD_OUT                                   , RULL(0x26010C42), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_ISU_REG2_HOLD_OUT                                   , RULL(0x27010C42), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_ISU_REG2_HOLD_OUT                                   , RULL(0x28010C42), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_ISU_REG2_HOLD_OUT                                   , RULL(0x29010C42), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_ISU_REG2_HOLD_OUT                                  , RULL(0x2A010C42), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_ISU_REG2_HOLD_OUT                                  , RULL(0x2B010C42), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_ISU_REG2_HOLD_OUT                                  , RULL(0x2C010C42), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_ISU_REG2_HOLD_OUT                                  , RULL(0x2D010C42), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_ISU_REG2_HOLD_OUT                                  , RULL(0x2E010C42), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_ISU_REG2_HOLD_OUT                                  , RULL(0x2F010C42), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_ISU_REG2_HOLD_OUT                                  , RULL(0x30010C42), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_ISU_REG2_HOLD_OUT                                  , RULL(0x31010C42), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_ISU_REG2_HOLD_OUT                                  , RULL(0x32010C42), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_ISU_REG2_HOLD_OUT                                  , RULL(0x33010C42), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_ISU_REG2_HOLD_OUT                                  , RULL(0x34010C42), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_ISU_REG2_HOLD_OUT                                  , RULL(0x35010C42), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_ISU_REG2_HOLD_OUT                                  , RULL(0x36010C42), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_ISU_REG2_HOLD_OUT                                  , RULL(0x37010C42), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_ISU_REG2_HOLD_OUT                               , RULL(0x20010C42), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010C42,
+REG64( EX_10_L2_ISU_REG2_HOLD_OUT                              , RULL(0x34010C42), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010C42,
+REG64( EX_11_L2_ISU_REG2_HOLD_OUT                              , RULL(0x36010C42), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010C42,
+REG64( EX_1_L2_ISU_REG2_HOLD_OUT                               , RULL(0x22010C42), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010C42,
+REG64( EX_2_L2_ISU_REG2_HOLD_OUT                               , RULL(0x24010C42), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010C42,
+REG64( EX_3_L2_ISU_REG2_HOLD_OUT                               , RULL(0x26010C42), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010C42,
+REG64( EX_4_L2_ISU_REG2_HOLD_OUT                               , RULL(0x28010C42), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010C42,
+REG64( EX_5_L2_ISU_REG2_HOLD_OUT                               , RULL(0x2A010C42), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010C42,
+REG64( EX_6_L2_ISU_REG2_HOLD_OUT                               , RULL(0x2C010C42), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010C42,
+REG64( EX_7_L2_ISU_REG2_HOLD_OUT                               , RULL(0x2E010C42), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010C42,
+REG64( EX_8_L2_ISU_REG2_HOLD_OUT                               , RULL(0x30010C42), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010C42,
+REG64( EX_9_L2_ISU_REG2_HOLD_OUT                               , RULL(0x32010C42), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010C42,
+REG64( EX_L2_ISU_REG2_HOLD_OUT                                 , RULL(0x20010C42), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010C42,
+
+REG64( C_ISU_REG3_HOLD_OUT                                     , RULL(0x20010C43), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_ISU_REG3_HOLD_OUT                                   , RULL(0x20010C43), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_ISU_REG3_HOLD_OUT                                   , RULL(0x21010C43), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_ISU_REG3_HOLD_OUT                                   , RULL(0x22010C43), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_ISU_REG3_HOLD_OUT                                   , RULL(0x23010C43), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_ISU_REG3_HOLD_OUT                                   , RULL(0x24010C43), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_ISU_REG3_HOLD_OUT                                   , RULL(0x25010C43), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_ISU_REG3_HOLD_OUT                                   , RULL(0x26010C43), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_ISU_REG3_HOLD_OUT                                   , RULL(0x27010C43), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_ISU_REG3_HOLD_OUT                                   , RULL(0x28010C43), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_ISU_REG3_HOLD_OUT                                   , RULL(0x29010C43), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_ISU_REG3_HOLD_OUT                                  , RULL(0x2A010C43), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_ISU_REG3_HOLD_OUT                                  , RULL(0x2B010C43), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_ISU_REG3_HOLD_OUT                                  , RULL(0x2C010C43), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_ISU_REG3_HOLD_OUT                                  , RULL(0x2D010C43), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_ISU_REG3_HOLD_OUT                                  , RULL(0x2E010C43), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_ISU_REG3_HOLD_OUT                                  , RULL(0x2F010C43), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_ISU_REG3_HOLD_OUT                                  , RULL(0x30010C43), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_ISU_REG3_HOLD_OUT                                  , RULL(0x31010C43), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_ISU_REG3_HOLD_OUT                                  , RULL(0x32010C43), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_ISU_REG3_HOLD_OUT                                  , RULL(0x33010C43), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_ISU_REG3_HOLD_OUT                                  , RULL(0x34010C43), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_ISU_REG3_HOLD_OUT                                  , RULL(0x35010C43), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_ISU_REG3_HOLD_OUT                                  , RULL(0x36010C43), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_ISU_REG3_HOLD_OUT                                  , RULL(0x37010C43), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_ISU_REG3_HOLD_OUT                               , RULL(0x20010C43), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010C43,
+REG64( EX_10_L2_ISU_REG3_HOLD_OUT                              , RULL(0x34010C43), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010C43,
+REG64( EX_11_L2_ISU_REG3_HOLD_OUT                              , RULL(0x36010C43), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010C43,
+REG64( EX_1_L2_ISU_REG3_HOLD_OUT                               , RULL(0x22010C43), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010C43,
+REG64( EX_2_L2_ISU_REG3_HOLD_OUT                               , RULL(0x24010C43), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010C43,
+REG64( EX_3_L2_ISU_REG3_HOLD_OUT                               , RULL(0x26010C43), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010C43,
+REG64( EX_4_L2_ISU_REG3_HOLD_OUT                               , RULL(0x28010C43), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010C43,
+REG64( EX_5_L2_ISU_REG3_HOLD_OUT                               , RULL(0x2A010C43), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010C43,
+REG64( EX_6_L2_ISU_REG3_HOLD_OUT                               , RULL(0x2C010C43), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010C43,
+REG64( EX_7_L2_ISU_REG3_HOLD_OUT                               , RULL(0x2E010C43), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010C43,
+REG64( EX_8_L2_ISU_REG3_HOLD_OUT                               , RULL(0x30010C43), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010C43,
+REG64( EX_9_L2_ISU_REG3_HOLD_OUT                               , RULL(0x32010C43), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010C43,
+REG64( EX_L2_ISU_REG3_HOLD_OUT                                 , RULL(0x20010C43), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010C43,
+
+REG64( C_ISU_REG4_HOLD_OUT                                     , RULL(0x20010C44), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_ISU_REG4_HOLD_OUT                                   , RULL(0x20010C44), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_ISU_REG4_HOLD_OUT                                   , RULL(0x21010C44), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_ISU_REG4_HOLD_OUT                                   , RULL(0x22010C44), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_ISU_REG4_HOLD_OUT                                   , RULL(0x23010C44), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_ISU_REG4_HOLD_OUT                                   , RULL(0x24010C44), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_ISU_REG4_HOLD_OUT                                   , RULL(0x25010C44), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_ISU_REG4_HOLD_OUT                                   , RULL(0x26010C44), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_ISU_REG4_HOLD_OUT                                   , RULL(0x27010C44), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_ISU_REG4_HOLD_OUT                                   , RULL(0x28010C44), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_ISU_REG4_HOLD_OUT                                   , RULL(0x29010C44), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_ISU_REG4_HOLD_OUT                                  , RULL(0x2A010C44), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_ISU_REG4_HOLD_OUT                                  , RULL(0x2B010C44), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_ISU_REG4_HOLD_OUT                                  , RULL(0x2C010C44), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_ISU_REG4_HOLD_OUT                                  , RULL(0x2D010C44), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_ISU_REG4_HOLD_OUT                                  , RULL(0x2E010C44), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_ISU_REG4_HOLD_OUT                                  , RULL(0x2F010C44), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_ISU_REG4_HOLD_OUT                                  , RULL(0x30010C44), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_ISU_REG4_HOLD_OUT                                  , RULL(0x31010C44), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_ISU_REG4_HOLD_OUT                                  , RULL(0x32010C44), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_ISU_REG4_HOLD_OUT                                  , RULL(0x33010C44), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_ISU_REG4_HOLD_OUT                                  , RULL(0x34010C44), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_ISU_REG4_HOLD_OUT                                  , RULL(0x35010C44), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_ISU_REG4_HOLD_OUT                                  , RULL(0x36010C44), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_ISU_REG4_HOLD_OUT                                  , RULL(0x37010C44), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_ISU_REG4_HOLD_OUT                               , RULL(0x20010C44), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010C44,
+REG64( EX_10_L2_ISU_REG4_HOLD_OUT                              , RULL(0x34010C44), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010C44,
+REG64( EX_11_L2_ISU_REG4_HOLD_OUT                              , RULL(0x36010C44), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010C44,
+REG64( EX_1_L2_ISU_REG4_HOLD_OUT                               , RULL(0x22010C44), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010C44,
+REG64( EX_2_L2_ISU_REG4_HOLD_OUT                               , RULL(0x24010C44), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010C44,
+REG64( EX_3_L2_ISU_REG4_HOLD_OUT                               , RULL(0x26010C44), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010C44,
+REG64( EX_4_L2_ISU_REG4_HOLD_OUT                               , RULL(0x28010C44), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010C44,
+REG64( EX_5_L2_ISU_REG4_HOLD_OUT                               , RULL(0x2A010C44), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010C44,
+REG64( EX_6_L2_ISU_REG4_HOLD_OUT                               , RULL(0x2C010C44), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010C44,
+REG64( EX_7_L2_ISU_REG4_HOLD_OUT                               , RULL(0x2E010C44), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010C44,
+REG64( EX_8_L2_ISU_REG4_HOLD_OUT                               , RULL(0x30010C44), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010C44,
+REG64( EX_9_L2_ISU_REG4_HOLD_OUT                               , RULL(0x32010C44), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010C44,
+REG64( EX_L2_ISU_REG4_HOLD_OUT                                 , RULL(0x20010C44), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010C44,
+
+REG64( C_ISU_REG5_HOLD_OUT                                     , RULL(0x20010C45), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_ISU_REG5_HOLD_OUT                                   , RULL(0x20010C45), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_ISU_REG5_HOLD_OUT                                   , RULL(0x21010C45), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_ISU_REG5_HOLD_OUT                                   , RULL(0x22010C45), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_ISU_REG5_HOLD_OUT                                   , RULL(0x23010C45), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_ISU_REG5_HOLD_OUT                                   , RULL(0x24010C45), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_ISU_REG5_HOLD_OUT                                   , RULL(0x25010C45), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_ISU_REG5_HOLD_OUT                                   , RULL(0x26010C45), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_ISU_REG5_HOLD_OUT                                   , RULL(0x27010C45), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_ISU_REG5_HOLD_OUT                                   , RULL(0x28010C45), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_ISU_REG5_HOLD_OUT                                   , RULL(0x29010C45), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_ISU_REG5_HOLD_OUT                                  , RULL(0x2A010C45), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_ISU_REG5_HOLD_OUT                                  , RULL(0x2B010C45), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_ISU_REG5_HOLD_OUT                                  , RULL(0x2C010C45), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_ISU_REG5_HOLD_OUT                                  , RULL(0x2D010C45), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_ISU_REG5_HOLD_OUT                                  , RULL(0x2E010C45), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_ISU_REG5_HOLD_OUT                                  , RULL(0x2F010C45), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_ISU_REG5_HOLD_OUT                                  , RULL(0x30010C45), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_ISU_REG5_HOLD_OUT                                  , RULL(0x31010C45), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_ISU_REG5_HOLD_OUT                                  , RULL(0x32010C45), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_ISU_REG5_HOLD_OUT                                  , RULL(0x33010C45), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_ISU_REG5_HOLD_OUT                                  , RULL(0x34010C45), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_ISU_REG5_HOLD_OUT                                  , RULL(0x35010C45), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_ISU_REG5_HOLD_OUT                                  , RULL(0x36010C45), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_ISU_REG5_HOLD_OUT                                  , RULL(0x37010C45), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_ISU_REG5_HOLD_OUT                               , RULL(0x20010C45), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010C45,
+REG64( EX_10_L2_ISU_REG5_HOLD_OUT                              , RULL(0x34010C45), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010C45,
+REG64( EX_11_L2_ISU_REG5_HOLD_OUT                              , RULL(0x36010C45), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010C45,
+REG64( EX_1_L2_ISU_REG5_HOLD_OUT                               , RULL(0x22010C45), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010C45,
+REG64( EX_2_L2_ISU_REG5_HOLD_OUT                               , RULL(0x24010C45), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010C45,
+REG64( EX_3_L2_ISU_REG5_HOLD_OUT                               , RULL(0x26010C45), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010C45,
+REG64( EX_4_L2_ISU_REG5_HOLD_OUT                               , RULL(0x28010C45), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010C45,
+REG64( EX_5_L2_ISU_REG5_HOLD_OUT                               , RULL(0x2A010C45), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010C45,
+REG64( EX_6_L2_ISU_REG5_HOLD_OUT                               , RULL(0x2C010C45), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010C45,
+REG64( EX_7_L2_ISU_REG5_HOLD_OUT                               , RULL(0x2E010C45), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010C45,
+REG64( EX_8_L2_ISU_REG5_HOLD_OUT                               , RULL(0x30010C45), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010C45,
+REG64( EX_9_L2_ISU_REG5_HOLD_OUT                               , RULL(0x32010C45), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010C45,
+REG64( EX_L2_ISU_REG5_HOLD_OUT                                 , RULL(0x20010C45), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010C45,
+
+REG64( EQ_L3TRA0_TR0_TRACE_HI_DATA_REG                         , RULL(0x10010400), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_L3TRA0_TR0_TRACE_HI_DATA_REG                       , RULL(0x10010400), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_L3TRA0_TR0_TRACE_HI_DATA_REG                       , RULL(0x11010400), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_L3TRA0_TR0_TRACE_HI_DATA_REG                       , RULL(0x12010400), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_L3TRA0_TR0_TRACE_HI_DATA_REG                       , RULL(0x13010400), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_L3TRA0_TR0_TRACE_HI_DATA_REG                       , RULL(0x14010400), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_L3TRA0_TR0_TRACE_HI_DATA_REG                       , RULL(0x15010400), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+
+REG64( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG                         , RULL(0x10010401), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_L3TRA0_TR0_TRACE_LO_DATA_REG                       , RULL(0x10010401), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_L3TRA0_TR0_TRACE_LO_DATA_REG                       , RULL(0x11010401), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_L3TRA0_TR0_TRACE_LO_DATA_REG                       , RULL(0x12010401), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_L3TRA0_TR0_TRACE_LO_DATA_REG                       , RULL(0x13010401), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_L3TRA0_TR0_TRACE_LO_DATA_REG                       , RULL(0x14010401), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_L3TRA0_TR0_TRACE_LO_DATA_REG                       , RULL(0x15010401), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+
+REG64( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG                       , RULL(0x10010402), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x10010402), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x11010402), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x12010402), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x13010402), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x14010402), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x15010402), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_0                     , RULL(0x10010403), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x10010403), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x11010403), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x12010403), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x13010403), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x14010403), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x15010403), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_1                     , RULL(0x10010404), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x10010404), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x11010404), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x12010404), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x13010404), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x14010404), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x15010404), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_2                     , RULL(0x10010405), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x10010405), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x11010405), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x12010405), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x13010405), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x14010405), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x15010405), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_3                     , RULL(0x10010406), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x10010406), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x11010406), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x12010406), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x13010406), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x14010406), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x15010406), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_4                     , RULL(0x10010407), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x10010407), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x11010407), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x12010407), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x13010407), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x14010407), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x15010407), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_5                     , RULL(0x10010408), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x10010408), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x11010408), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x12010408), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x13010408), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x14010408), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x15010408), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9                     , RULL(0x10010409), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x10010409), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x11010409), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x12010409), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x13010409), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x14010409), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x15010409), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA0_TR1_TRACE_HI_DATA_REG                         , RULL(0x10010440), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_L3TRA0_TR1_TRACE_HI_DATA_REG                       , RULL(0x10010440), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_L3TRA0_TR1_TRACE_HI_DATA_REG                       , RULL(0x11010440), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_L3TRA0_TR1_TRACE_HI_DATA_REG                       , RULL(0x12010440), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_L3TRA0_TR1_TRACE_HI_DATA_REG                       , RULL(0x13010440), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_L3TRA0_TR1_TRACE_HI_DATA_REG                       , RULL(0x14010440), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_L3TRA0_TR1_TRACE_HI_DATA_REG                       , RULL(0x15010440), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+
+REG64( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG                         , RULL(0x10010441), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_L3TRA0_TR1_TRACE_LO_DATA_REG                       , RULL(0x10010441), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_L3TRA0_TR1_TRACE_LO_DATA_REG                       , RULL(0x11010441), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_L3TRA0_TR1_TRACE_LO_DATA_REG                       , RULL(0x12010441), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_L3TRA0_TR1_TRACE_LO_DATA_REG                       , RULL(0x13010441), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_L3TRA0_TR1_TRACE_LO_DATA_REG                       , RULL(0x14010441), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_L3TRA0_TR1_TRACE_LO_DATA_REG                       , RULL(0x15010441), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+
+REG64( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG                       , RULL(0x10010442), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x10010442), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x11010442), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x12010442), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x13010442), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x14010442), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x15010442), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_0                     , RULL(0x10010443), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x10010443), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x11010443), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x12010443), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x13010443), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x14010443), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x15010443), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_1                     , RULL(0x10010444), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x10010444), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x11010444), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x12010444), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x13010444), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x14010444), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x15010444), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_2                     , RULL(0x10010445), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x10010445), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x11010445), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x12010445), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x13010445), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x14010445), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x15010445), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_3                     , RULL(0x10010446), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x10010446), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x11010446), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x12010446), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x13010446), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x14010446), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x15010446), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_4                     , RULL(0x10010447), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x10010447), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x11010447), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x12010447), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x13010447), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x14010447), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x15010447), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_5                     , RULL(0x10010448), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x10010448), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x11010448), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x12010448), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x13010448), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x14010448), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x15010448), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9                     , RULL(0x10010449), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x10010449), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x11010449), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x12010449), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x13010449), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x14010449), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x15010449), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR0_TRACE_HI_DATA_REG                         , RULL(0x10010480), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_L3TRA1_TR0_TRACE_HI_DATA_REG                       , RULL(0x10010480), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_L3TRA1_TR0_TRACE_HI_DATA_REG                       , RULL(0x11010480), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_L3TRA1_TR0_TRACE_HI_DATA_REG                       , RULL(0x12010480), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_L3TRA1_TR0_TRACE_HI_DATA_REG                       , RULL(0x13010480), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_L3TRA1_TR0_TRACE_HI_DATA_REG                       , RULL(0x14010480), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_L3TRA1_TR0_TRACE_HI_DATA_REG                       , RULL(0x15010480), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+
+REG64( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG                         , RULL(0x10010481), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_L3TRA1_TR0_TRACE_LO_DATA_REG                       , RULL(0x10010481), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_L3TRA1_TR0_TRACE_LO_DATA_REG                       , RULL(0x11010481), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_L3TRA1_TR0_TRACE_LO_DATA_REG                       , RULL(0x12010481), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_L3TRA1_TR0_TRACE_LO_DATA_REG                       , RULL(0x13010481), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_L3TRA1_TR0_TRACE_LO_DATA_REG                       , RULL(0x14010481), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_L3TRA1_TR0_TRACE_LO_DATA_REG                       , RULL(0x15010481), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+
+REG64( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG                       , RULL(0x10010482), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x10010482), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x11010482), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x12010482), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x13010482), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x14010482), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x15010482), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_0                     , RULL(0x10010483), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x10010483), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x11010483), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x12010483), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x13010483), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x14010483), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x15010483), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_1                     , RULL(0x10010484), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x10010484), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x11010484), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x12010484), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x13010484), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x14010484), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x15010484), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_2                     , RULL(0x10010485), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x10010485), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x11010485), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x12010485), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x13010485), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x14010485), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x15010485), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_3                     , RULL(0x10010486), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x10010486), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x11010486), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x12010486), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x13010486), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x14010486), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x15010486), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_4                     , RULL(0x10010487), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x10010487), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x11010487), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x12010487), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x13010487), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x14010487), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x15010487), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_5                     , RULL(0x10010488), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x10010488), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x11010488), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x12010488), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x13010488), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x14010488), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x15010488), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9                     , RULL(0x10010489), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x10010489), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x11010489), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x12010489), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x13010489), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x14010489), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x15010489), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR1_TRACE_HI_DATA_REG                         , RULL(0x100104C0), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_L3TRA1_TR1_TRACE_HI_DATA_REG                       , RULL(0x100104C0), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_L3TRA1_TR1_TRACE_HI_DATA_REG                       , RULL(0x110104C0), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_L3TRA1_TR1_TRACE_HI_DATA_REG                       , RULL(0x120104C0), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_L3TRA1_TR1_TRACE_HI_DATA_REG                       , RULL(0x130104C0), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_L3TRA1_TR1_TRACE_HI_DATA_REG                       , RULL(0x140104C0), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_L3TRA1_TR1_TRACE_HI_DATA_REG                       , RULL(0x150104C0), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+
+REG64( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG                         , RULL(0x100104C1), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_L3TRA1_TR1_TRACE_LO_DATA_REG                       , RULL(0x100104C1), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_L3TRA1_TR1_TRACE_LO_DATA_REG                       , RULL(0x110104C1), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_L3TRA1_TR1_TRACE_LO_DATA_REG                       , RULL(0x120104C1), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_L3TRA1_TR1_TRACE_LO_DATA_REG                       , RULL(0x130104C1), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_L3TRA1_TR1_TRACE_LO_DATA_REG                       , RULL(0x140104C1), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_L3TRA1_TR1_TRACE_LO_DATA_REG                       , RULL(0x150104C1), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+
+REG64( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG                       , RULL(0x100104C2), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x100104C2), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x110104C2), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x120104C2), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x130104C2), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x140104C2), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x150104C2), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_0                     , RULL(0x100104C3), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x100104C3), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x110104C3), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x120104C3), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x130104C3), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x140104C3), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x150104C3), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_1                     , RULL(0x100104C4), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x100104C4), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x110104C4), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x120104C4), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x130104C4), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x140104C4), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x150104C4), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_2                     , RULL(0x100104C5), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x100104C5), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x110104C5), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x120104C5), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x130104C5), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x140104C5), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x150104C5), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_3                     , RULL(0x100104C6), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x100104C6), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x110104C6), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x120104C6), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x130104C6), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x140104C6), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x150104C6), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_4                     , RULL(0x100104C7), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x100104C7), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x110104C7), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x120104C7), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x130104C7), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x140104C7), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x150104C7), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_5                     , RULL(0x100104C8), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x100104C8), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x110104C8), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x120104C8), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x130104C8), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x140104C8), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x150104C8), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9                     , RULL(0x100104C9), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x100104C9), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x110104C9), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x120104C9), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x130104C9), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x140104C9), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x150104C9), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+
+REG64( EQ_L3_ERR_RPT0_REG                                      , RULL(0x10011810), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C10,
+REG64( EQ_0_L3_ERR_RPT0_REG                                    , RULL(0x10011810), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C10,
+REG64( EQ_1_L3_ERR_RPT0_REG                                    , RULL(0x11011810), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C10,
+REG64( EQ_2_L3_ERR_RPT0_REG                                    , RULL(0x12011810), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C10,
+REG64( EQ_3_L3_ERR_RPT0_REG                                    , RULL(0x13011810), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C10,
+REG64( EQ_4_L3_ERR_RPT0_REG                                    , RULL(0x14011810), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C10,
+REG64( EQ_5_L3_ERR_RPT0_REG                                    , RULL(0x15011810), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C10,
+REG64( EX_0_L3_L3_ERR_RPT0_REG                                 , RULL(0x10011810), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_L3_L3_ERR_RPT0_REG                                , RULL(0x15011810), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L3_L3_ERR_RPT0_REG                                , RULL(0x15011C10), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L3_L3_ERR_RPT0_REG                                 , RULL(0x10011C10), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L3_L3_ERR_RPT0_REG                                 , RULL(0x11011810), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L3_L3_ERR_RPT0_REG                                 , RULL(0x11011C10), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L3_L3_ERR_RPT0_REG                                 , RULL(0x12011810), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L3_L3_ERR_RPT0_REG                                 , RULL(0x12011C10), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L3_L3_ERR_RPT0_REG                                 , RULL(0x13011810), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L3_L3_ERR_RPT0_REG                                 , RULL(0x13011C10), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L3_L3_ERR_RPT0_REG                                 , RULL(0x14011810), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L3_L3_ERR_RPT0_REG                                 , RULL(0x14011C10), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L3_L3_ERR_RPT0_REG                                   , RULL(0x10011810), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( EQ_L3_ERR_RPT1_REG                                      , RULL(0x10011817), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C17,
+REG64( EQ_0_L3_ERR_RPT1_REG                                    , RULL(0x10011817), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C17,
+REG64( EQ_1_L3_ERR_RPT1_REG                                    , RULL(0x11011817), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C17,
+REG64( EQ_2_L3_ERR_RPT1_REG                                    , RULL(0x12011817), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C17,
+REG64( EQ_3_L3_ERR_RPT1_REG                                    , RULL(0x13011817), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C17,
+REG64( EQ_4_L3_ERR_RPT1_REG                                    , RULL(0x14011817), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C17,
+REG64( EQ_5_L3_ERR_RPT1_REG                                    , RULL(0x15011817), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C17,
+REG64( EX_0_L3_L3_ERR_RPT1_REG                                 , RULL(0x10011817), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_L3_L3_ERR_RPT1_REG                                , RULL(0x15011817), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L3_L3_ERR_RPT1_REG                                , RULL(0x15011C17), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L3_L3_ERR_RPT1_REG                                 , RULL(0x10011C17), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L3_L3_ERR_RPT1_REG                                 , RULL(0x11011817), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L3_L3_ERR_RPT1_REG                                 , RULL(0x11011C17), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L3_L3_ERR_RPT1_REG                                 , RULL(0x12011817), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L3_L3_ERR_RPT1_REG                                 , RULL(0x12011C17), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L3_L3_ERR_RPT1_REG                                 , RULL(0x13011817), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L3_L3_ERR_RPT1_REG                                 , RULL(0x13011C17), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L3_L3_ERR_RPT1_REG                                 , RULL(0x14011817), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L3_L3_ERR_RPT1_REG                                 , RULL(0x14011C17), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L3_L3_ERR_RPT1_REG                                   , RULL(0x10011817), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( EQ_L3_RD_EPSILON_CFG_REG                                , RULL(0x10011829), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C29,
+REG64( EQ_0_L3_RD_EPSILON_CFG_REG                              , RULL(0x10011829), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C29,
+REG64( EQ_1_L3_RD_EPSILON_CFG_REG                              , RULL(0x11011829), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C29,
+REG64( EQ_2_L3_RD_EPSILON_CFG_REG                              , RULL(0x12011829), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C29,
+REG64( EQ_3_L3_RD_EPSILON_CFG_REG                              , RULL(0x13011829), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C29,
+REG64( EQ_4_L3_RD_EPSILON_CFG_REG                              , RULL(0x14011829), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C29,
+REG64( EQ_5_L3_RD_EPSILON_CFG_REG                              , RULL(0x15011829), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C29,
+REG64( EX_L3_RD_EPSILON_CFG_REG                                , RULL(0x10011829), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_L3_RD_EPSILON_CFG_REG                              , RULL(0x10011829), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_L3_RD_EPSILON_CFG_REG                              , RULL(0x10011C29), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_L3_RD_EPSILON_CFG_REG                              , RULL(0x11011829), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_L3_RD_EPSILON_CFG_REG                              , RULL(0x11011C29), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_L3_RD_EPSILON_CFG_REG                              , RULL(0x12011829), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_L3_RD_EPSILON_CFG_REG                              , RULL(0x12011C29), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_L3_RD_EPSILON_CFG_REG                              , RULL(0x13011829), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_L3_RD_EPSILON_CFG_REG                              , RULL(0x13011C29), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_L3_RD_EPSILON_CFG_REG                              , RULL(0x14011829), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_L3_RD_EPSILON_CFG_REG                              , RULL(0x14011C29), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_L3_RD_EPSILON_CFG_REG                             , RULL(0x15011829), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_L3_RD_EPSILON_CFG_REG                             , RULL(0x15011C29), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_L3_RTIM_PERIOD_MONITOR                               , RULL(0x10011812), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C12,
+REG64( EQ_0_L3_RTIM_PERIOD_MONITOR                             , RULL(0x10011812), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C12,
+REG64( EQ_1_L3_RTIM_PERIOD_MONITOR                             , RULL(0x11011812), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C12,
+REG64( EQ_2_L3_RTIM_PERIOD_MONITOR                             , RULL(0x12011812), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C12,
+REG64( EQ_3_L3_RTIM_PERIOD_MONITOR                             , RULL(0x13011812), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C12,
+REG64( EQ_4_L3_RTIM_PERIOD_MONITOR                             , RULL(0x14011812), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C12,
+REG64( EQ_5_L3_RTIM_PERIOD_MONITOR                             , RULL(0x15011812), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C12,
+REG64( EX_0_L3_L3_RTIM_PERIOD_MONITOR                          , RULL(0x10011812), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_L3_L3_RTIM_PERIOD_MONITOR                         , RULL(0x15011812), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L3_L3_RTIM_PERIOD_MONITOR                         , RULL(0x15011C12), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L3_L3_RTIM_PERIOD_MONITOR                          , RULL(0x10011C12), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L3_L3_RTIM_PERIOD_MONITOR                          , RULL(0x11011812), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L3_L3_RTIM_PERIOD_MONITOR                          , RULL(0x11011C12), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L3_L3_RTIM_PERIOD_MONITOR                          , RULL(0x12011812), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L3_L3_RTIM_PERIOD_MONITOR                          , RULL(0x12011C12), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L3_L3_RTIM_PERIOD_MONITOR                          , RULL(0x13011812), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L3_L3_RTIM_PERIOD_MONITOR                          , RULL(0x13011C12), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L3_L3_RTIM_PERIOD_MONITOR                          , RULL(0x14011812), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L3_L3_RTIM_PERIOD_MONITOR                          , RULL(0x14011C12), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L3_L3_RTIM_PERIOD_MONITOR                            , RULL(0x10011812), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( EQ_L3_WR_EPSILON_CFG_REG                                , RULL(0x1001182A), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C2A,
+REG64( EQ_0_L3_WR_EPSILON_CFG_REG                              , RULL(0x1001182A), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C2A,
+REG64( EQ_1_L3_WR_EPSILON_CFG_REG                              , RULL(0x1101182A), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C2A,
+REG64( EQ_2_L3_WR_EPSILON_CFG_REG                              , RULL(0x1201182A), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C2A,
+REG64( EQ_3_L3_WR_EPSILON_CFG_REG                              , RULL(0x1301182A), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C2A,
+REG64( EQ_4_L3_WR_EPSILON_CFG_REG                              , RULL(0x1401182A), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C2A,
+REG64( EQ_5_L3_WR_EPSILON_CFG_REG                              , RULL(0x1501182A), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C2A,
+REG64( EX_0_L3_L3_WR_EPSILON_CFG_REG                           , RULL(0x1001182A), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_L3_L3_WR_EPSILON_CFG_REG                          , RULL(0x1501182A), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L3_L3_WR_EPSILON_CFG_REG                          , RULL(0x15011C2A), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L3_L3_WR_EPSILON_CFG_REG                           , RULL(0x10011C2A), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L3_L3_WR_EPSILON_CFG_REG                           , RULL(0x1101182A), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L3_L3_WR_EPSILON_CFG_REG                           , RULL(0x11011C2A), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L3_L3_WR_EPSILON_CFG_REG                           , RULL(0x1201182A), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L3_L3_WR_EPSILON_CFG_REG                           , RULL(0x12011C2A), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L3_L3_WR_EPSILON_CFG_REG                           , RULL(0x1301182A), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L3_L3_WR_EPSILON_CFG_REG                           , RULL(0x13011C2A), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L3_L3_WR_EPSILON_CFG_REG                           , RULL(0x1401182A), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L3_L3_WR_EPSILON_CFG_REG                           , RULL(0x14011C2A), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L3_L3_WR_EPSILON_CFG_REG                             , RULL(0x1001182A), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( EQ_LINEDEL_TRIG_REG                                     , RULL(0x1001080D), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10010C0D,
+REG64( EQ_0_LINEDEL_TRIG_REG                                   , RULL(0x1001080D), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10010C0D,
+REG64( EQ_1_LINEDEL_TRIG_REG                                   , RULL(0x1101080D), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11010C0D,
+REG64( EQ_2_LINEDEL_TRIG_REG                                   , RULL(0x1201080D), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12010C0D,
+REG64( EQ_3_LINEDEL_TRIG_REG                                   , RULL(0x1301080D), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13010C0D,
+REG64( EQ_4_LINEDEL_TRIG_REG                                   , RULL(0x1401080D), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14010C0D,
+REG64( EQ_5_LINEDEL_TRIG_REG                                   , RULL(0x1501080D), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15010C0D,
+REG64( EX_0_L2_LINEDEL_TRIG_REG                                , RULL(0x1001080D), SH_UNT_EX_0_L2  , SH_ACS_SCOM      );
+REG64( EX_10_L2_LINEDEL_TRIG_REG                               , RULL(0x1501080D), SH_UNT_EX_10_L2 , SH_ACS_SCOM      );
+REG64( EX_11_L2_LINEDEL_TRIG_REG                               , RULL(0x15010C0D), SH_UNT_EX_11_L2 , SH_ACS_SCOM      );
+REG64( EX_1_L2_LINEDEL_TRIG_REG                                , RULL(0x10010C0D), SH_UNT_EX_1_L2  , SH_ACS_SCOM      );
+REG64( EX_2_L2_LINEDEL_TRIG_REG                                , RULL(0x1101080D), SH_UNT_EX_2_L2  , SH_ACS_SCOM      );
+REG64( EX_3_L2_LINEDEL_TRIG_REG                                , RULL(0x11010C0D), SH_UNT_EX_3_L2  , SH_ACS_SCOM      );
+REG64( EX_4_L2_LINEDEL_TRIG_REG                                , RULL(0x1201080D), SH_UNT_EX_4_L2  , SH_ACS_SCOM      );
+REG64( EX_5_L2_LINEDEL_TRIG_REG                                , RULL(0x12010C0D), SH_UNT_EX_5_L2  , SH_ACS_SCOM      );
+REG64( EX_6_L2_LINEDEL_TRIG_REG                                , RULL(0x1301080D), SH_UNT_EX_6_L2  , SH_ACS_SCOM      );
+REG64( EX_7_L2_LINEDEL_TRIG_REG                                , RULL(0x13010C0D), SH_UNT_EX_7_L2  , SH_ACS_SCOM      );
+REG64( EX_8_L2_LINEDEL_TRIG_REG                                , RULL(0x1401080D), SH_UNT_EX_8_L2  , SH_ACS_SCOM      );
+REG64( EX_9_L2_LINEDEL_TRIG_REG                                , RULL(0x14010C0D), SH_UNT_EX_9_L2  , SH_ACS_SCOM      );
+REG64( EX_L2_LINEDEL_TRIG_REG                                  , RULL(0x1001080D), SH_UNT_EX_L2    , SH_ACS_SCOM      );
+
+REG64( EQ_LINE_DELETED_MEMBERS_REG                             , RULL(0x10011815), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C15,
+REG64( EQ_0_LINE_DELETED_MEMBERS_REG                           , RULL(0x10011815), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C15,
+REG64( EQ_1_LINE_DELETED_MEMBERS_REG                           , RULL(0x11011815), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C15,
+REG64( EQ_2_LINE_DELETED_MEMBERS_REG                           , RULL(0x12011815), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C15,
+REG64( EQ_3_LINE_DELETED_MEMBERS_REG                           , RULL(0x13011815), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C15,
+REG64( EQ_4_LINE_DELETED_MEMBERS_REG                           , RULL(0x14011815), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C15,
+REG64( EQ_5_LINE_DELETED_MEMBERS_REG                           , RULL(0x15011815), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C15,
+REG64( EX_0_L3_LINE_DELETED_MEMBERS_REG                        , RULL(0x10011815), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_L3_LINE_DELETED_MEMBERS_REG                       , RULL(0x15011815), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L3_LINE_DELETED_MEMBERS_REG                       , RULL(0x15011C15), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L3_LINE_DELETED_MEMBERS_REG                        , RULL(0x10011C15), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L3_LINE_DELETED_MEMBERS_REG                        , RULL(0x11011815), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L3_LINE_DELETED_MEMBERS_REG                        , RULL(0x11011C15), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L3_LINE_DELETED_MEMBERS_REG                        , RULL(0x12011815), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L3_LINE_DELETED_MEMBERS_REG                        , RULL(0x12011C15), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L3_LINE_DELETED_MEMBERS_REG                        , RULL(0x13011815), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L3_LINE_DELETED_MEMBERS_REG                        , RULL(0x13011C15), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L3_LINE_DELETED_MEMBERS_REG                        , RULL(0x14011815), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L3_LINE_DELETED_MEMBERS_REG                        , RULL(0x14011C15), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L3_LINE_DELETED_MEMBERS_REG                          , RULL(0x10011815), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( C_LOCAL_FIR                                             , RULL(0x2004000A), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_LOCAL_FIR_AND                                         , RULL(0x2004000B), SH_UNT_C        , SH_ACS_SCOM1_AND );
+REG64( C_LOCAL_FIR_OR                                          , RULL(0x2004000C), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_LOCAL_FIR                                           , RULL(0x2004000A), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_LOCAL_FIR_AND                                       , RULL(0x2004000B), SH_UNT_C_0      , SH_ACS_SCOM1_AND );
+REG64( C_0_LOCAL_FIR_OR                                        , RULL(0x2004000C), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_LOCAL_FIR                                           , RULL(0x2104000A), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_LOCAL_FIR_AND                                       , RULL(0x2104000B), SH_UNT_C_1      , SH_ACS_SCOM1_AND );
+REG64( C_1_LOCAL_FIR_OR                                        , RULL(0x2104000C), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_LOCAL_FIR                                           , RULL(0x2204000A), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_LOCAL_FIR_AND                                       , RULL(0x2204000B), SH_UNT_C_2      , SH_ACS_SCOM1_AND );
+REG64( C_2_LOCAL_FIR_OR                                        , RULL(0x2204000C), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_LOCAL_FIR                                           , RULL(0x2304000A), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_LOCAL_FIR_AND                                       , RULL(0x2304000B), SH_UNT_C_3      , SH_ACS_SCOM1_AND );
+REG64( C_3_LOCAL_FIR_OR                                        , RULL(0x2304000C), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_LOCAL_FIR                                           , RULL(0x2404000A), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_LOCAL_FIR_AND                                       , RULL(0x2404000B), SH_UNT_C_4      , SH_ACS_SCOM1_AND );
+REG64( C_4_LOCAL_FIR_OR                                        , RULL(0x2404000C), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_LOCAL_FIR                                           , RULL(0x2504000A), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_LOCAL_FIR_AND                                       , RULL(0x2504000B), SH_UNT_C_5      , SH_ACS_SCOM1_AND );
+REG64( C_5_LOCAL_FIR_OR                                        , RULL(0x2504000C), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_LOCAL_FIR                                           , RULL(0x2604000A), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_LOCAL_FIR_AND                                       , RULL(0x2604000B), SH_UNT_C_6      , SH_ACS_SCOM1_AND );
+REG64( C_6_LOCAL_FIR_OR                                        , RULL(0x2604000C), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_LOCAL_FIR                                           , RULL(0x2704000A), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_LOCAL_FIR_AND                                       , RULL(0x2704000B), SH_UNT_C_7      , SH_ACS_SCOM1_AND );
+REG64( C_7_LOCAL_FIR_OR                                        , RULL(0x2704000C), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_LOCAL_FIR                                           , RULL(0x2804000A), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_LOCAL_FIR_AND                                       , RULL(0x2804000B), SH_UNT_C_8      , SH_ACS_SCOM1_AND );
+REG64( C_8_LOCAL_FIR_OR                                        , RULL(0x2804000C), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_LOCAL_FIR                                           , RULL(0x2904000A), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_LOCAL_FIR_AND                                       , RULL(0x2904000B), SH_UNT_C_9      , SH_ACS_SCOM1_AND );
+REG64( C_9_LOCAL_FIR_OR                                        , RULL(0x2904000C), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_LOCAL_FIR                                          , RULL(0x2A04000A), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_LOCAL_FIR_AND                                      , RULL(0x2A04000B), SH_UNT_C_10     , SH_ACS_SCOM1_AND );
+REG64( C_10_LOCAL_FIR_OR                                       , RULL(0x2A04000C), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_LOCAL_FIR                                          , RULL(0x2B04000A), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_LOCAL_FIR_AND                                      , RULL(0x2B04000B), SH_UNT_C_11     , SH_ACS_SCOM1_AND );
+REG64( C_11_LOCAL_FIR_OR                                       , RULL(0x2B04000C), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_LOCAL_FIR                                          , RULL(0x2C04000A), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_LOCAL_FIR_AND                                      , RULL(0x2C04000B), SH_UNT_C_12     , SH_ACS_SCOM1_AND );
+REG64( C_12_LOCAL_FIR_OR                                       , RULL(0x2C04000C), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_LOCAL_FIR                                          , RULL(0x2D04000A), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_LOCAL_FIR_AND                                      , RULL(0x2D04000B), SH_UNT_C_13     , SH_ACS_SCOM1_AND );
+REG64( C_13_LOCAL_FIR_OR                                       , RULL(0x2D04000C), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_LOCAL_FIR                                          , RULL(0x2E04000A), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_LOCAL_FIR_AND                                      , RULL(0x2E04000B), SH_UNT_C_14     , SH_ACS_SCOM1_AND );
+REG64( C_14_LOCAL_FIR_OR                                       , RULL(0x2E04000C), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_LOCAL_FIR                                          , RULL(0x2F04000A), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_LOCAL_FIR_AND                                      , RULL(0x2F04000B), SH_UNT_C_15     , SH_ACS_SCOM1_AND );
+REG64( C_15_LOCAL_FIR_OR                                       , RULL(0x2F04000C), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_LOCAL_FIR                                          , RULL(0x3004000A), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_LOCAL_FIR_AND                                      , RULL(0x3004000B), SH_UNT_C_16     , SH_ACS_SCOM1_AND );
+REG64( C_16_LOCAL_FIR_OR                                       , RULL(0x3004000C), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_LOCAL_FIR                                          , RULL(0x3104000A), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_LOCAL_FIR_AND                                      , RULL(0x3104000B), SH_UNT_C_17     , SH_ACS_SCOM1_AND );
+REG64( C_17_LOCAL_FIR_OR                                       , RULL(0x3104000C), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_LOCAL_FIR                                          , RULL(0x3204000A), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_LOCAL_FIR_AND                                      , RULL(0x3204000B), SH_UNT_C_18     , SH_ACS_SCOM1_AND );
+REG64( C_18_LOCAL_FIR_OR                                       , RULL(0x3204000C), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_LOCAL_FIR                                          , RULL(0x3304000A), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_LOCAL_FIR_AND                                      , RULL(0x3304000B), SH_UNT_C_19     , SH_ACS_SCOM1_AND );
+REG64( C_19_LOCAL_FIR_OR                                       , RULL(0x3304000C), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_LOCAL_FIR                                          , RULL(0x3404000A), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_LOCAL_FIR_AND                                      , RULL(0x3404000B), SH_UNT_C_20     , SH_ACS_SCOM1_AND );
+REG64( C_20_LOCAL_FIR_OR                                       , RULL(0x3404000C), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_LOCAL_FIR                                          , RULL(0x3504000A), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_LOCAL_FIR_AND                                      , RULL(0x3504000B), SH_UNT_C_21     , SH_ACS_SCOM1_AND );
+REG64( C_21_LOCAL_FIR_OR                                       , RULL(0x3504000C), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_LOCAL_FIR                                          , RULL(0x3604000A), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_LOCAL_FIR_AND                                      , RULL(0x3604000B), SH_UNT_C_22     , SH_ACS_SCOM1_AND );
+REG64( C_22_LOCAL_FIR_OR                                       , RULL(0x3604000C), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_LOCAL_FIR                                          , RULL(0x3704000A), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_LOCAL_FIR_AND                                      , RULL(0x3704000B), SH_UNT_C_23     , SH_ACS_SCOM1_AND );
+REG64( C_23_LOCAL_FIR_OR                                       , RULL(0x3704000C), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EQ_LOCAL_FIR                                            , RULL(0x1004000A), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_LOCAL_FIR_AND                                        , RULL(0x1004000B), SH_UNT_EQ       , SH_ACS_SCOM1_AND );
+REG64( EQ_LOCAL_FIR_OR                                         , RULL(0x1004000C), SH_UNT_EQ       , SH_ACS_SCOM2_OR  );
+REG64( EQ_0_LOCAL_FIR                                          , RULL(0x1004000A), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_0_LOCAL_FIR_AND                                      , RULL(0x1004000B), SH_UNT_EQ_0     , SH_ACS_SCOM1_AND );
+REG64( EQ_0_LOCAL_FIR_OR                                       , RULL(0x1004000C), SH_UNT_EQ_0     , SH_ACS_SCOM2_OR  );
+REG64( EQ_1_LOCAL_FIR                                          , RULL(0x1104000A), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_LOCAL_FIR_AND                                      , RULL(0x1104000B), SH_UNT_EQ_1     , SH_ACS_SCOM1_AND );
+REG64( EQ_1_LOCAL_FIR_OR                                       , RULL(0x1104000C), SH_UNT_EQ_1     , SH_ACS_SCOM2_OR  );
+REG64( EQ_2_LOCAL_FIR                                          , RULL(0x1204000A), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_LOCAL_FIR_AND                                      , RULL(0x1204000B), SH_UNT_EQ_2     , SH_ACS_SCOM1_AND );
+REG64( EQ_2_LOCAL_FIR_OR                                       , RULL(0x1204000C), SH_UNT_EQ_2     , SH_ACS_SCOM2_OR  );
+REG64( EQ_3_LOCAL_FIR                                          , RULL(0x1304000A), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_LOCAL_FIR_AND                                      , RULL(0x1304000B), SH_UNT_EQ_3     , SH_ACS_SCOM1_AND );
+REG64( EQ_3_LOCAL_FIR_OR                                       , RULL(0x1304000C), SH_UNT_EQ_3     , SH_ACS_SCOM2_OR  );
+REG64( EQ_4_LOCAL_FIR                                          , RULL(0x1404000A), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_LOCAL_FIR_AND                                      , RULL(0x1404000B), SH_UNT_EQ_4     , SH_ACS_SCOM1_AND );
+REG64( EQ_4_LOCAL_FIR_OR                                       , RULL(0x1404000C), SH_UNT_EQ_4     , SH_ACS_SCOM2_OR  );
+REG64( EQ_5_LOCAL_FIR                                          , RULL(0x1504000A), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_LOCAL_FIR_AND                                      , RULL(0x1504000B), SH_UNT_EQ_5     , SH_ACS_SCOM1_AND );
+REG64( EQ_5_LOCAL_FIR_OR                                       , RULL(0x1504000C), SH_UNT_EQ_5     , SH_ACS_SCOM2_OR  );
+REG64( EX_LOCAL_FIR                                            , RULL(0x2004000A), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2104000A,
+REG64( EX_LOCAL_FIR_AND                                        , RULL(0x2004000B), SH_UNT_EX       ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2104000B,
+REG64( EX_LOCAL_FIR_OR                                         , RULL(0x2004000C), SH_UNT_EX       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2104000C,
+REG64( EX_0_LOCAL_FIR                                          , RULL(0x2004000A), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2104000A,
+REG64( EX_0_LOCAL_FIR_AND                                      , RULL(0x2004000B), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2104000B,
+REG64( EX_0_LOCAL_FIR_OR                                       , RULL(0x2004000C), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2104000C,
+REG64( EX_1_LOCAL_FIR                                          , RULL(0x2204000A), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2304000A,
+REG64( EX_1_LOCAL_FIR_AND                                      , RULL(0x2204000B), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2304000B,
+REG64( EX_1_LOCAL_FIR_OR                                       , RULL(0x2204000C), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2304000C,
+REG64( EX_2_LOCAL_FIR                                          , RULL(0x2404000A), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2504000A,
+REG64( EX_2_LOCAL_FIR_AND                                      , RULL(0x2404000B), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2504000B,
+REG64( EX_2_LOCAL_FIR_OR                                       , RULL(0x2404000C), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2504000C,
+REG64( EX_3_LOCAL_FIR                                          , RULL(0x2604000A), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2704000A,
+REG64( EX_3_LOCAL_FIR_AND                                      , RULL(0x2604000B), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2704000B,
+REG64( EX_3_LOCAL_FIR_OR                                       , RULL(0x2604000C), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2704000C,
+REG64( EX_4_LOCAL_FIR                                          , RULL(0x2804000A), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2904000A,
+REG64( EX_4_LOCAL_FIR_AND                                      , RULL(0x2804000B), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2904000B,
+REG64( EX_4_LOCAL_FIR_OR                                       , RULL(0x2804000C), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2904000C,
+REG64( EX_5_LOCAL_FIR                                          , RULL(0x2A04000A), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B04000A,
+REG64( EX_5_LOCAL_FIR_AND                                      , RULL(0x2A04000B), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2B04000B,
+REG64( EX_5_LOCAL_FIR_OR                                       , RULL(0x2A04000C), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2B04000C,
+REG64( EX_6_LOCAL_FIR                                          , RULL(0x2C04000A), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D04000A,
+REG64( EX_6_LOCAL_FIR_AND                                      , RULL(0x2C04000B), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2D04000B,
+REG64( EX_6_LOCAL_FIR_OR                                       , RULL(0x2C04000C), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2D04000C,
+REG64( EX_7_LOCAL_FIR                                          , RULL(0x2E04000A), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F04000A,
+REG64( EX_7_LOCAL_FIR_AND                                      , RULL(0x2E04000B), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2F04000B,
+REG64( EX_7_LOCAL_FIR_OR                                       , RULL(0x2E04000C), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2F04000C,
+REG64( EX_8_LOCAL_FIR                                          , RULL(0x3004000A), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 3104000A,
+REG64( EX_8_LOCAL_FIR_AND                                      , RULL(0x3004000B), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 3104000B,
+REG64( EX_8_LOCAL_FIR_OR                                       , RULL(0x3004000C), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 3104000C,
+REG64( EX_9_LOCAL_FIR                                          , RULL(0x3204000A), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 3304000A,
+REG64( EX_9_LOCAL_FIR_AND                                      , RULL(0x3204000B), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 3304000B,
+REG64( EX_9_LOCAL_FIR_OR                                       , RULL(0x3204000C), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 3304000C,
+REG64( EX_10_LOCAL_FIR                                         , RULL(0x3404000A), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 3504000A,
+REG64( EX_10_LOCAL_FIR_AND                                     , RULL(0x3404000B), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_AND ); //DUPS: 3504000B,
+REG64( EX_10_LOCAL_FIR_OR                                      , RULL(0x3404000C), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 3504000C,
+REG64( EX_11_LOCAL_FIR                                         , RULL(0x3604000A), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 3704000A,
+REG64( EX_11_LOCAL_FIR_AND                                     , RULL(0x3604000B), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_AND ); //DUPS: 3704000B,
+REG64( EX_11_LOCAL_FIR_OR                                      , RULL(0x3604000C), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 3704000C,
+
+REG64( C_LOCAL_FIR_ACTION0                                     , RULL(0x20040010), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_LOCAL_FIR_ACTION0                                   , RULL(0x20040010), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_LOCAL_FIR_ACTION0                                   , RULL(0x21040010), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_LOCAL_FIR_ACTION0                                   , RULL(0x22040010), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_LOCAL_FIR_ACTION0                                   , RULL(0x23040010), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_LOCAL_FIR_ACTION0                                   , RULL(0x24040010), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_LOCAL_FIR_ACTION0                                   , RULL(0x25040010), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_LOCAL_FIR_ACTION0                                   , RULL(0x26040010), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_LOCAL_FIR_ACTION0                                   , RULL(0x27040010), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_LOCAL_FIR_ACTION0                                   , RULL(0x28040010), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_LOCAL_FIR_ACTION0                                   , RULL(0x29040010), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_LOCAL_FIR_ACTION0                                  , RULL(0x2A040010), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_LOCAL_FIR_ACTION0                                  , RULL(0x2B040010), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_LOCAL_FIR_ACTION0                                  , RULL(0x2C040010), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_LOCAL_FIR_ACTION0                                  , RULL(0x2D040010), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_LOCAL_FIR_ACTION0                                  , RULL(0x2E040010), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_LOCAL_FIR_ACTION0                                  , RULL(0x2F040010), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_LOCAL_FIR_ACTION0                                  , RULL(0x30040010), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_LOCAL_FIR_ACTION0                                  , RULL(0x31040010), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_LOCAL_FIR_ACTION0                                  , RULL(0x32040010), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_LOCAL_FIR_ACTION0                                  , RULL(0x33040010), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_LOCAL_FIR_ACTION0                                  , RULL(0x34040010), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_LOCAL_FIR_ACTION0                                  , RULL(0x35040010), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_LOCAL_FIR_ACTION0                                  , RULL(0x36040010), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_LOCAL_FIR_ACTION0                                  , RULL(0x37040010), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_LOCAL_FIR_ACTION0                                    , RULL(0x10040010), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_LOCAL_FIR_ACTION0                                  , RULL(0x10040010), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_LOCAL_FIR_ACTION0                                  , RULL(0x11040010), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_LOCAL_FIR_ACTION0                                  , RULL(0x12040010), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_LOCAL_FIR_ACTION0                                  , RULL(0x13040010), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_LOCAL_FIR_ACTION0                                  , RULL(0x14040010), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_LOCAL_FIR_ACTION0                                  , RULL(0x15040010), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_LOCAL_FIR_ACTION0                                    , RULL(0x20040010), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21040010,
+REG64( EX_0_LOCAL_FIR_ACTION0                                  , RULL(0x20040010), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21040010,
+REG64( EX_1_LOCAL_FIR_ACTION0                                  , RULL(0x22040010), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23040010,
+REG64( EX_2_LOCAL_FIR_ACTION0                                  , RULL(0x24040010), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25040010,
+REG64( EX_3_LOCAL_FIR_ACTION0                                  , RULL(0x26040010), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27040010,
+REG64( EX_4_LOCAL_FIR_ACTION0                                  , RULL(0x28040010), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29040010,
+REG64( EX_5_LOCAL_FIR_ACTION0                                  , RULL(0x2A040010), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B040010,
+REG64( EX_6_LOCAL_FIR_ACTION0                                  , RULL(0x2C040010), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D040010,
+REG64( EX_7_LOCAL_FIR_ACTION0                                  , RULL(0x2E040010), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F040010,
+REG64( EX_8_LOCAL_FIR_ACTION0                                  , RULL(0x30040010), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31040010,
+REG64( EX_9_LOCAL_FIR_ACTION0                                  , RULL(0x32040010), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33040010,
+REG64( EX_10_LOCAL_FIR_ACTION0                                 , RULL(0x34040010), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35040010,
+REG64( EX_11_LOCAL_FIR_ACTION0                                 , RULL(0x36040010), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37040010,
+
+REG64( C_LOCAL_FIR_ACTION1                                     , RULL(0x20040011), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_LOCAL_FIR_ACTION1                                   , RULL(0x20040011), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_LOCAL_FIR_ACTION1                                   , RULL(0x21040011), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_LOCAL_FIR_ACTION1                                   , RULL(0x22040011), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_LOCAL_FIR_ACTION1                                   , RULL(0x23040011), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_LOCAL_FIR_ACTION1                                   , RULL(0x24040011), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_LOCAL_FIR_ACTION1                                   , RULL(0x25040011), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_LOCAL_FIR_ACTION1                                   , RULL(0x26040011), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_LOCAL_FIR_ACTION1                                   , RULL(0x27040011), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_LOCAL_FIR_ACTION1                                   , RULL(0x28040011), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_LOCAL_FIR_ACTION1                                   , RULL(0x29040011), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_LOCAL_FIR_ACTION1                                  , RULL(0x2A040011), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_LOCAL_FIR_ACTION1                                  , RULL(0x2B040011), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_LOCAL_FIR_ACTION1                                  , RULL(0x2C040011), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_LOCAL_FIR_ACTION1                                  , RULL(0x2D040011), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_LOCAL_FIR_ACTION1                                  , RULL(0x2E040011), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_LOCAL_FIR_ACTION1                                  , RULL(0x2F040011), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_LOCAL_FIR_ACTION1                                  , RULL(0x30040011), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_LOCAL_FIR_ACTION1                                  , RULL(0x31040011), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_LOCAL_FIR_ACTION1                                  , RULL(0x32040011), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_LOCAL_FIR_ACTION1                                  , RULL(0x33040011), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_LOCAL_FIR_ACTION1                                  , RULL(0x34040011), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_LOCAL_FIR_ACTION1                                  , RULL(0x35040011), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_LOCAL_FIR_ACTION1                                  , RULL(0x36040011), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_LOCAL_FIR_ACTION1                                  , RULL(0x37040011), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_LOCAL_FIR_ACTION1                                    , RULL(0x10040011), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_LOCAL_FIR_ACTION1                                  , RULL(0x10040011), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_LOCAL_FIR_ACTION1                                  , RULL(0x11040011), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_LOCAL_FIR_ACTION1                                  , RULL(0x12040011), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_LOCAL_FIR_ACTION1                                  , RULL(0x13040011), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_LOCAL_FIR_ACTION1                                  , RULL(0x14040011), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_LOCAL_FIR_ACTION1                                  , RULL(0x15040011), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_LOCAL_FIR_ACTION1                                    , RULL(0x20040011), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21040011,
+REG64( EX_0_LOCAL_FIR_ACTION1                                  , RULL(0x20040011), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21040011,
+REG64( EX_1_LOCAL_FIR_ACTION1                                  , RULL(0x22040011), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23040011,
+REG64( EX_2_LOCAL_FIR_ACTION1                                  , RULL(0x24040011), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25040011,
+REG64( EX_3_LOCAL_FIR_ACTION1                                  , RULL(0x26040011), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27040011,
+REG64( EX_4_LOCAL_FIR_ACTION1                                  , RULL(0x28040011), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29040011,
+REG64( EX_5_LOCAL_FIR_ACTION1                                  , RULL(0x2A040011), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B040011,
+REG64( EX_6_LOCAL_FIR_ACTION1                                  , RULL(0x2C040011), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D040011,
+REG64( EX_7_LOCAL_FIR_ACTION1                                  , RULL(0x2E040011), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F040011,
+REG64( EX_8_LOCAL_FIR_ACTION1                                  , RULL(0x30040011), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31040011,
+REG64( EX_9_LOCAL_FIR_ACTION1                                  , RULL(0x32040011), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33040011,
+REG64( EX_10_LOCAL_FIR_ACTION1                                 , RULL(0x34040011), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35040011,
+REG64( EX_11_LOCAL_FIR_ACTION1                                 , RULL(0x36040011), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37040011,
+
+REG64( C_LOCAL_FIR_MASK                                        , RULL(0x2004000D), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_LOCAL_FIR_MASK_AND                                    , RULL(0x2004000E), SH_UNT_C        , SH_ACS_SCOM1_AND );
+REG64( C_LOCAL_FIR_MASK_OR                                     , RULL(0x2004000F), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_LOCAL_FIR_MASK                                      , RULL(0x2004000D), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_LOCAL_FIR_MASK_AND                                  , RULL(0x2004000E), SH_UNT_C_0      , SH_ACS_SCOM1_AND );
+REG64( C_0_LOCAL_FIR_MASK_OR                                   , RULL(0x2004000F), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_LOCAL_FIR_MASK                                      , RULL(0x2104000D), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_LOCAL_FIR_MASK_AND                                  , RULL(0x2104000E), SH_UNT_C_1      , SH_ACS_SCOM1_AND );
+REG64( C_1_LOCAL_FIR_MASK_OR                                   , RULL(0x2104000F), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_LOCAL_FIR_MASK                                      , RULL(0x2204000D), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_LOCAL_FIR_MASK_AND                                  , RULL(0x2204000E), SH_UNT_C_2      , SH_ACS_SCOM1_AND );
+REG64( C_2_LOCAL_FIR_MASK_OR                                   , RULL(0x2204000F), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_LOCAL_FIR_MASK                                      , RULL(0x2304000D), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_LOCAL_FIR_MASK_AND                                  , RULL(0x2304000E), SH_UNT_C_3      , SH_ACS_SCOM1_AND );
+REG64( C_3_LOCAL_FIR_MASK_OR                                   , RULL(0x2304000F), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_LOCAL_FIR_MASK                                      , RULL(0x2404000D), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_LOCAL_FIR_MASK_AND                                  , RULL(0x2404000E), SH_UNT_C_4      , SH_ACS_SCOM1_AND );
+REG64( C_4_LOCAL_FIR_MASK_OR                                   , RULL(0x2404000F), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_LOCAL_FIR_MASK                                      , RULL(0x2504000D), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_LOCAL_FIR_MASK_AND                                  , RULL(0x2504000E), SH_UNT_C_5      , SH_ACS_SCOM1_AND );
+REG64( C_5_LOCAL_FIR_MASK_OR                                   , RULL(0x2504000F), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_LOCAL_FIR_MASK                                      , RULL(0x2604000D), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_LOCAL_FIR_MASK_AND                                  , RULL(0x2604000E), SH_UNT_C_6      , SH_ACS_SCOM1_AND );
+REG64( C_6_LOCAL_FIR_MASK_OR                                   , RULL(0x2604000F), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_LOCAL_FIR_MASK                                      , RULL(0x2704000D), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_LOCAL_FIR_MASK_AND                                  , RULL(0x2704000E), SH_UNT_C_7      , SH_ACS_SCOM1_AND );
+REG64( C_7_LOCAL_FIR_MASK_OR                                   , RULL(0x2704000F), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_LOCAL_FIR_MASK                                      , RULL(0x2804000D), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_LOCAL_FIR_MASK_AND                                  , RULL(0x2804000E), SH_UNT_C_8      , SH_ACS_SCOM1_AND );
+REG64( C_8_LOCAL_FIR_MASK_OR                                   , RULL(0x2804000F), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_LOCAL_FIR_MASK                                      , RULL(0x2904000D), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_LOCAL_FIR_MASK_AND                                  , RULL(0x2904000E), SH_UNT_C_9      , SH_ACS_SCOM1_AND );
+REG64( C_9_LOCAL_FIR_MASK_OR                                   , RULL(0x2904000F), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_LOCAL_FIR_MASK                                     , RULL(0x2A04000D), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_LOCAL_FIR_MASK_AND                                 , RULL(0x2A04000E), SH_UNT_C_10     , SH_ACS_SCOM1_AND );
+REG64( C_10_LOCAL_FIR_MASK_OR                                  , RULL(0x2A04000F), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_LOCAL_FIR_MASK                                     , RULL(0x2B04000D), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_LOCAL_FIR_MASK_AND                                 , RULL(0x2B04000E), SH_UNT_C_11     , SH_ACS_SCOM1_AND );
+REG64( C_11_LOCAL_FIR_MASK_OR                                  , RULL(0x2B04000F), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_LOCAL_FIR_MASK                                     , RULL(0x2C04000D), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_LOCAL_FIR_MASK_AND                                 , RULL(0x2C04000E), SH_UNT_C_12     , SH_ACS_SCOM1_AND );
+REG64( C_12_LOCAL_FIR_MASK_OR                                  , RULL(0x2C04000F), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_LOCAL_FIR_MASK                                     , RULL(0x2D04000D), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_LOCAL_FIR_MASK_AND                                 , RULL(0x2D04000E), SH_UNT_C_13     , SH_ACS_SCOM1_AND );
+REG64( C_13_LOCAL_FIR_MASK_OR                                  , RULL(0x2D04000F), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_LOCAL_FIR_MASK                                     , RULL(0x2E04000D), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_LOCAL_FIR_MASK_AND                                 , RULL(0x2E04000E), SH_UNT_C_14     , SH_ACS_SCOM1_AND );
+REG64( C_14_LOCAL_FIR_MASK_OR                                  , RULL(0x2E04000F), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_LOCAL_FIR_MASK                                     , RULL(0x2F04000D), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_LOCAL_FIR_MASK_AND                                 , RULL(0x2F04000E), SH_UNT_C_15     , SH_ACS_SCOM1_AND );
+REG64( C_15_LOCAL_FIR_MASK_OR                                  , RULL(0x2F04000F), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_LOCAL_FIR_MASK                                     , RULL(0x3004000D), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_LOCAL_FIR_MASK_AND                                 , RULL(0x3004000E), SH_UNT_C_16     , SH_ACS_SCOM1_AND );
+REG64( C_16_LOCAL_FIR_MASK_OR                                  , RULL(0x3004000F), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_LOCAL_FIR_MASK                                     , RULL(0x3104000D), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_LOCAL_FIR_MASK_AND                                 , RULL(0x3104000E), SH_UNT_C_17     , SH_ACS_SCOM1_AND );
+REG64( C_17_LOCAL_FIR_MASK_OR                                  , RULL(0x3104000F), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_LOCAL_FIR_MASK                                     , RULL(0x3204000D), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_LOCAL_FIR_MASK_AND                                 , RULL(0x3204000E), SH_UNT_C_18     , SH_ACS_SCOM1_AND );
+REG64( C_18_LOCAL_FIR_MASK_OR                                  , RULL(0x3204000F), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_LOCAL_FIR_MASK                                     , RULL(0x3304000D), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_LOCAL_FIR_MASK_AND                                 , RULL(0x3304000E), SH_UNT_C_19     , SH_ACS_SCOM1_AND );
+REG64( C_19_LOCAL_FIR_MASK_OR                                  , RULL(0x3304000F), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_LOCAL_FIR_MASK                                     , RULL(0x3404000D), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_LOCAL_FIR_MASK_AND                                 , RULL(0x3404000E), SH_UNT_C_20     , SH_ACS_SCOM1_AND );
+REG64( C_20_LOCAL_FIR_MASK_OR                                  , RULL(0x3404000F), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_LOCAL_FIR_MASK                                     , RULL(0x3504000D), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_LOCAL_FIR_MASK_AND                                 , RULL(0x3504000E), SH_UNT_C_21     , SH_ACS_SCOM1_AND );
+REG64( C_21_LOCAL_FIR_MASK_OR                                  , RULL(0x3504000F), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_LOCAL_FIR_MASK                                     , RULL(0x3604000D), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_LOCAL_FIR_MASK_AND                                 , RULL(0x3604000E), SH_UNT_C_22     , SH_ACS_SCOM1_AND );
+REG64( C_22_LOCAL_FIR_MASK_OR                                  , RULL(0x3604000F), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_LOCAL_FIR_MASK                                     , RULL(0x3704000D), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_LOCAL_FIR_MASK_AND                                 , RULL(0x3704000E), SH_UNT_C_23     , SH_ACS_SCOM1_AND );
+REG64( C_23_LOCAL_FIR_MASK_OR                                  , RULL(0x3704000F), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EQ_LOCAL_FIR_MASK                                       , RULL(0x1004000D), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_LOCAL_FIR_MASK_AND                                   , RULL(0x1004000E), SH_UNT_EQ       , SH_ACS_SCOM1_AND );
+REG64( EQ_LOCAL_FIR_MASK_OR                                    , RULL(0x1004000F), SH_UNT_EQ       , SH_ACS_SCOM2_OR  );
+REG64( EQ_0_LOCAL_FIR_MASK                                     , RULL(0x1004000D), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_0_LOCAL_FIR_MASK_AND                                 , RULL(0x1004000E), SH_UNT_EQ_0     , SH_ACS_SCOM1_AND );
+REG64( EQ_0_LOCAL_FIR_MASK_OR                                  , RULL(0x1004000F), SH_UNT_EQ_0     , SH_ACS_SCOM2_OR  );
+REG64( EQ_1_LOCAL_FIR_MASK                                     , RULL(0x1104000D), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_LOCAL_FIR_MASK_AND                                 , RULL(0x1104000E), SH_UNT_EQ_1     , SH_ACS_SCOM1_AND );
+REG64( EQ_1_LOCAL_FIR_MASK_OR                                  , RULL(0x1104000F), SH_UNT_EQ_1     , SH_ACS_SCOM2_OR  );
+REG64( EQ_2_LOCAL_FIR_MASK                                     , RULL(0x1204000D), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_LOCAL_FIR_MASK_AND                                 , RULL(0x1204000E), SH_UNT_EQ_2     , SH_ACS_SCOM1_AND );
+REG64( EQ_2_LOCAL_FIR_MASK_OR                                  , RULL(0x1204000F), SH_UNT_EQ_2     , SH_ACS_SCOM2_OR  );
+REG64( EQ_3_LOCAL_FIR_MASK                                     , RULL(0x1304000D), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_LOCAL_FIR_MASK_AND                                 , RULL(0x1304000E), SH_UNT_EQ_3     , SH_ACS_SCOM1_AND );
+REG64( EQ_3_LOCAL_FIR_MASK_OR                                  , RULL(0x1304000F), SH_UNT_EQ_3     , SH_ACS_SCOM2_OR  );
+REG64( EQ_4_LOCAL_FIR_MASK                                     , RULL(0x1404000D), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_LOCAL_FIR_MASK_AND                                 , RULL(0x1404000E), SH_UNT_EQ_4     , SH_ACS_SCOM1_AND );
+REG64( EQ_4_LOCAL_FIR_MASK_OR                                  , RULL(0x1404000F), SH_UNT_EQ_4     , SH_ACS_SCOM2_OR  );
+REG64( EQ_5_LOCAL_FIR_MASK                                     , RULL(0x1504000D), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_LOCAL_FIR_MASK_AND                                 , RULL(0x1504000E), SH_UNT_EQ_5     , SH_ACS_SCOM1_AND );
+REG64( EQ_5_LOCAL_FIR_MASK_OR                                  , RULL(0x1504000F), SH_UNT_EQ_5     , SH_ACS_SCOM2_OR  );
+REG64( EX_LOCAL_FIR_MASK                                       , RULL(0x2004000D), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2104000D,
+REG64( EX_LOCAL_FIR_MASK_AND                                   , RULL(0x2004000E), SH_UNT_EX       ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2104000E,
+REG64( EX_LOCAL_FIR_MASK_OR                                    , RULL(0x2004000F), SH_UNT_EX       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2104000F,
+REG64( EX_0_LOCAL_FIR_MASK                                     , RULL(0x2004000D), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2104000D,
+REG64( EX_0_LOCAL_FIR_MASK_AND                                 , RULL(0x2004000E), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2104000E,
+REG64( EX_0_LOCAL_FIR_MASK_OR                                  , RULL(0x2004000F), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2104000F,
+REG64( EX_1_LOCAL_FIR_MASK                                     , RULL(0x2204000D), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2304000D,
+REG64( EX_1_LOCAL_FIR_MASK_AND                                 , RULL(0x2204000E), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2304000E,
+REG64( EX_1_LOCAL_FIR_MASK_OR                                  , RULL(0x2204000F), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2304000F,
+REG64( EX_2_LOCAL_FIR_MASK                                     , RULL(0x2404000D), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2504000D,
+REG64( EX_2_LOCAL_FIR_MASK_AND                                 , RULL(0x2404000E), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2504000E,
+REG64( EX_2_LOCAL_FIR_MASK_OR                                  , RULL(0x2404000F), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2504000F,
+REG64( EX_3_LOCAL_FIR_MASK                                     , RULL(0x2604000D), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2704000D,
+REG64( EX_3_LOCAL_FIR_MASK_AND                                 , RULL(0x2604000E), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2704000E,
+REG64( EX_3_LOCAL_FIR_MASK_OR                                  , RULL(0x2604000F), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2704000F,
+REG64( EX_4_LOCAL_FIR_MASK                                     , RULL(0x2804000D), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2904000D,
+REG64( EX_4_LOCAL_FIR_MASK_AND                                 , RULL(0x2804000E), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2904000E,
+REG64( EX_4_LOCAL_FIR_MASK_OR                                  , RULL(0x2804000F), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2904000F,
+REG64( EX_5_LOCAL_FIR_MASK                                     , RULL(0x2A04000D), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B04000D,
+REG64( EX_5_LOCAL_FIR_MASK_AND                                 , RULL(0x2A04000E), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2B04000E,
+REG64( EX_5_LOCAL_FIR_MASK_OR                                  , RULL(0x2A04000F), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2B04000F,
+REG64( EX_6_LOCAL_FIR_MASK                                     , RULL(0x2C04000D), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D04000D,
+REG64( EX_6_LOCAL_FIR_MASK_AND                                 , RULL(0x2C04000E), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2D04000E,
+REG64( EX_6_LOCAL_FIR_MASK_OR                                  , RULL(0x2C04000F), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2D04000F,
+REG64( EX_7_LOCAL_FIR_MASK                                     , RULL(0x2E04000D), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F04000D,
+REG64( EX_7_LOCAL_FIR_MASK_AND                                 , RULL(0x2E04000E), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 2F04000E,
+REG64( EX_7_LOCAL_FIR_MASK_OR                                  , RULL(0x2E04000F), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2F04000F,
+REG64( EX_8_LOCAL_FIR_MASK                                     , RULL(0x3004000D), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 3104000D,
+REG64( EX_8_LOCAL_FIR_MASK_AND                                 , RULL(0x3004000E), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 3104000E,
+REG64( EX_8_LOCAL_FIR_MASK_OR                                  , RULL(0x3004000F), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 3104000F,
+REG64( EX_9_LOCAL_FIR_MASK                                     , RULL(0x3204000D), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 3304000D,
+REG64( EX_9_LOCAL_FIR_MASK_AND                                 , RULL(0x3204000E), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_AND ); //DUPS: 3304000E,
+REG64( EX_9_LOCAL_FIR_MASK_OR                                  , RULL(0x3204000F), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 3304000F,
+REG64( EX_10_LOCAL_FIR_MASK                                    , RULL(0x3404000D), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 3504000D,
+REG64( EX_10_LOCAL_FIR_MASK_AND                                , RULL(0x3404000E), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_AND ); //DUPS: 3504000E,
+REG64( EX_10_LOCAL_FIR_MASK_OR                                 , RULL(0x3404000F), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 3504000F,
+REG64( EX_11_LOCAL_FIR_MASK                                    , RULL(0x3604000D), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 3704000D,
+REG64( EX_11_LOCAL_FIR_MASK_AND                                , RULL(0x3604000E), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_AND ); //DUPS: 3704000E,
+REG64( EX_11_LOCAL_FIR_MASK_OR                                 , RULL(0x3604000F), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 3704000F,
+
+REG64( C_LOCAL_XSTOP_ERR                                       , RULL(0x20040018), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_LOCAL_XSTOP_ERR                                     , RULL(0x20040018), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_LOCAL_XSTOP_ERR                                     , RULL(0x21040018), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_LOCAL_XSTOP_ERR                                     , RULL(0x22040018), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_LOCAL_XSTOP_ERR                                     , RULL(0x23040018), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_LOCAL_XSTOP_ERR                                     , RULL(0x24040018), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_LOCAL_XSTOP_ERR                                     , RULL(0x25040018), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_LOCAL_XSTOP_ERR                                     , RULL(0x26040018), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_LOCAL_XSTOP_ERR                                     , RULL(0x27040018), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_LOCAL_XSTOP_ERR                                     , RULL(0x28040018), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_LOCAL_XSTOP_ERR                                     , RULL(0x29040018), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_LOCAL_XSTOP_ERR                                    , RULL(0x2A040018), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_LOCAL_XSTOP_ERR                                    , RULL(0x2B040018), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_LOCAL_XSTOP_ERR                                    , RULL(0x2C040018), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_LOCAL_XSTOP_ERR                                    , RULL(0x2D040018), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_LOCAL_XSTOP_ERR                                    , RULL(0x2E040018), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_LOCAL_XSTOP_ERR                                    , RULL(0x2F040018), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_LOCAL_XSTOP_ERR                                    , RULL(0x30040018), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_LOCAL_XSTOP_ERR                                    , RULL(0x31040018), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_LOCAL_XSTOP_ERR                                    , RULL(0x32040018), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_LOCAL_XSTOP_ERR                                    , RULL(0x33040018), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_LOCAL_XSTOP_ERR                                    , RULL(0x34040018), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_LOCAL_XSTOP_ERR                                    , RULL(0x35040018), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_LOCAL_XSTOP_ERR                                    , RULL(0x36040018), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_LOCAL_XSTOP_ERR                                    , RULL(0x37040018), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EQ_LOCAL_XSTOP_ERR                                      , RULL(0x10040018), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_LOCAL_XSTOP_ERR                                    , RULL(0x10040018), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_LOCAL_XSTOP_ERR                                    , RULL(0x11040018), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_LOCAL_XSTOP_ERR                                    , RULL(0x12040018), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_LOCAL_XSTOP_ERR                                    , RULL(0x13040018), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_LOCAL_XSTOP_ERR                                    , RULL(0x14040018), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_LOCAL_XSTOP_ERR                                    , RULL(0x15040018), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_LOCAL_XSTOP_ERR                                      , RULL(0x20040018), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21040018,
+REG64( EX_0_LOCAL_XSTOP_ERR                                    , RULL(0x20040018), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21040018,
+REG64( EX_1_LOCAL_XSTOP_ERR                                    , RULL(0x22040018), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23040018,
+REG64( EX_2_LOCAL_XSTOP_ERR                                    , RULL(0x24040018), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25040018,
+REG64( EX_3_LOCAL_XSTOP_ERR                                    , RULL(0x26040018), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27040018,
+REG64( EX_4_LOCAL_XSTOP_ERR                                    , RULL(0x28040018), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29040018,
+REG64( EX_5_LOCAL_XSTOP_ERR                                    , RULL(0x2A040018), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B040018,
+REG64( EX_6_LOCAL_XSTOP_ERR                                    , RULL(0x2C040018), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D040018,
+REG64( EX_7_LOCAL_XSTOP_ERR                                    , RULL(0x2E040018), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F040018,
+REG64( EX_8_LOCAL_XSTOP_ERR                                    , RULL(0x30040018), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31040018,
+REG64( EX_9_LOCAL_XSTOP_ERR                                    , RULL(0x32040018), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33040018,
+REG64( EX_10_LOCAL_XSTOP_ERR                                   , RULL(0x34040018), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35040018,
+REG64( EX_11_LOCAL_XSTOP_ERR                                   , RULL(0x36040018), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37040018,
+
+REG64( C_LOCAL_XSTOP_MASK                                      , RULL(0x20040019), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_LOCAL_XSTOP_MASK                                    , RULL(0x20040019), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_LOCAL_XSTOP_MASK                                    , RULL(0x21040019), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_LOCAL_XSTOP_MASK                                    , RULL(0x22040019), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_LOCAL_XSTOP_MASK                                    , RULL(0x23040019), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_LOCAL_XSTOP_MASK                                    , RULL(0x24040019), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_LOCAL_XSTOP_MASK                                    , RULL(0x25040019), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_LOCAL_XSTOP_MASK                                    , RULL(0x26040019), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_LOCAL_XSTOP_MASK                                    , RULL(0x27040019), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_LOCAL_XSTOP_MASK                                    , RULL(0x28040019), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_LOCAL_XSTOP_MASK                                    , RULL(0x29040019), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_LOCAL_XSTOP_MASK                                   , RULL(0x2A040019), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_LOCAL_XSTOP_MASK                                   , RULL(0x2B040019), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_LOCAL_XSTOP_MASK                                   , RULL(0x2C040019), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_LOCAL_XSTOP_MASK                                   , RULL(0x2D040019), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_LOCAL_XSTOP_MASK                                   , RULL(0x2E040019), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_LOCAL_XSTOP_MASK                                   , RULL(0x2F040019), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_LOCAL_XSTOP_MASK                                   , RULL(0x30040019), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_LOCAL_XSTOP_MASK                                   , RULL(0x31040019), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_LOCAL_XSTOP_MASK                                   , RULL(0x32040019), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_LOCAL_XSTOP_MASK                                   , RULL(0x33040019), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_LOCAL_XSTOP_MASK                                   , RULL(0x34040019), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_LOCAL_XSTOP_MASK                                   , RULL(0x35040019), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_LOCAL_XSTOP_MASK                                   , RULL(0x36040019), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_LOCAL_XSTOP_MASK                                   , RULL(0x37040019), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_LOCAL_XSTOP_MASK                                     , RULL(0x10040019), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_LOCAL_XSTOP_MASK                                   , RULL(0x10040019), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_LOCAL_XSTOP_MASK                                   , RULL(0x11040019), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_LOCAL_XSTOP_MASK                                   , RULL(0x12040019), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_LOCAL_XSTOP_MASK                                   , RULL(0x13040019), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_LOCAL_XSTOP_MASK                                   , RULL(0x14040019), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_LOCAL_XSTOP_MASK                                   , RULL(0x15040019), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_LOCAL_XSTOP_MASK                                     , RULL(0x20040019), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21040019,
+REG64( EX_0_LOCAL_XSTOP_MASK                                   , RULL(0x20040019), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21040019,
+REG64( EX_1_LOCAL_XSTOP_MASK                                   , RULL(0x22040019), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23040019,
+REG64( EX_2_LOCAL_XSTOP_MASK                                   , RULL(0x24040019), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25040019,
+REG64( EX_3_LOCAL_XSTOP_MASK                                   , RULL(0x26040019), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27040019,
+REG64( EX_4_LOCAL_XSTOP_MASK                                   , RULL(0x28040019), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29040019,
+REG64( EX_5_LOCAL_XSTOP_MASK                                   , RULL(0x2A040019), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B040019,
+REG64( EX_6_LOCAL_XSTOP_MASK                                   , RULL(0x2C040019), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D040019,
+REG64( EX_7_LOCAL_XSTOP_MASK                                   , RULL(0x2E040019), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F040019,
+REG64( EX_8_LOCAL_XSTOP_MASK                                   , RULL(0x30040019), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31040019,
+REG64( EX_9_LOCAL_XSTOP_MASK                                   , RULL(0x32040019), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33040019,
+REG64( EX_10_LOCAL_XSTOP_MASK                                  , RULL(0x34040019), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35040019,
+REG64( EX_11_LOCAL_XSTOP_MASK                                  , RULL(0x36040019), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37040019,
+
+REG64( EQ_LRU_VIC_ALLOC_REG                                    , RULL(0x10011811), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C11,
+REG64( EQ_0_LRU_VIC_ALLOC_REG                                  , RULL(0x10011811), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C11,
+REG64( EQ_1_LRU_VIC_ALLOC_REG                                  , RULL(0x11011811), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C11,
+REG64( EQ_2_LRU_VIC_ALLOC_REG                                  , RULL(0x12011811), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C11,
+REG64( EQ_3_LRU_VIC_ALLOC_REG                                  , RULL(0x13011811), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C11,
+REG64( EQ_4_LRU_VIC_ALLOC_REG                                  , RULL(0x14011811), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C11,
+REG64( EQ_5_LRU_VIC_ALLOC_REG                                  , RULL(0x15011811), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C11,
+REG64( EX_0_L3_LRU_VIC_ALLOC_REG                               , RULL(0x10011811), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_L3_LRU_VIC_ALLOC_REG                              , RULL(0x15011811), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L3_LRU_VIC_ALLOC_REG                              , RULL(0x15011C11), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L3_LRU_VIC_ALLOC_REG                               , RULL(0x10011C11), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L3_LRU_VIC_ALLOC_REG                               , RULL(0x11011811), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L3_LRU_VIC_ALLOC_REG                               , RULL(0x11011C11), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L3_LRU_VIC_ALLOC_REG                               , RULL(0x12011811), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L3_LRU_VIC_ALLOC_REG                               , RULL(0x12011C11), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L3_LRU_VIC_ALLOC_REG                               , RULL(0x13011811), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L3_LRU_VIC_ALLOC_REG                               , RULL(0x13011C11), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L3_LRU_VIC_ALLOC_REG                               , RULL(0x14011811), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L3_LRU_VIC_ALLOC_REG                               , RULL(0x14011C11), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L3_LRU_VIC_ALLOC_REG                                 , RULL(0x10011811), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( C_LSU_HOLD_OUT_REG0                                     , RULL(0x20010C80), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_LSU_HOLD_OUT_REG0                                   , RULL(0x20010C80), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_LSU_HOLD_OUT_REG0                                   , RULL(0x21010C80), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_LSU_HOLD_OUT_REG0                                   , RULL(0x22010C80), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_LSU_HOLD_OUT_REG0                                   , RULL(0x23010C80), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_LSU_HOLD_OUT_REG0                                   , RULL(0x24010C80), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_LSU_HOLD_OUT_REG0                                   , RULL(0x25010C80), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_LSU_HOLD_OUT_REG0                                   , RULL(0x26010C80), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_LSU_HOLD_OUT_REG0                                   , RULL(0x27010C80), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_LSU_HOLD_OUT_REG0                                   , RULL(0x28010C80), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_LSU_HOLD_OUT_REG0                                   , RULL(0x29010C80), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_LSU_HOLD_OUT_REG0                                  , RULL(0x2A010C80), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_LSU_HOLD_OUT_REG0                                  , RULL(0x2B010C80), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_LSU_HOLD_OUT_REG0                                  , RULL(0x2C010C80), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_LSU_HOLD_OUT_REG0                                  , RULL(0x2D010C80), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_LSU_HOLD_OUT_REG0                                  , RULL(0x2E010C80), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_LSU_HOLD_OUT_REG0                                  , RULL(0x2F010C80), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_LSU_HOLD_OUT_REG0                                  , RULL(0x30010C80), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_LSU_HOLD_OUT_REG0                                  , RULL(0x31010C80), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_LSU_HOLD_OUT_REG0                                  , RULL(0x32010C80), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_LSU_HOLD_OUT_REG0                                  , RULL(0x33010C80), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_LSU_HOLD_OUT_REG0                                  , RULL(0x34010C80), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_LSU_HOLD_OUT_REG0                                  , RULL(0x35010C80), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_LSU_HOLD_OUT_REG0                                  , RULL(0x36010C80), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_LSU_HOLD_OUT_REG0                                  , RULL(0x37010C80), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_0_L2_LSU_HOLD_OUT_REG0                               , RULL(0x20010C80), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010C80,
+REG64( EX_10_L2_LSU_HOLD_OUT_REG0                              , RULL(0x34010C80), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35010C80,
+REG64( EX_11_L2_LSU_HOLD_OUT_REG0                              , RULL(0x36010C80), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37010C80,
+REG64( EX_1_L2_LSU_HOLD_OUT_REG0                               , RULL(0x22010C80), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23010C80,
+REG64( EX_2_L2_LSU_HOLD_OUT_REG0                               , RULL(0x24010C80), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25010C80,
+REG64( EX_3_L2_LSU_HOLD_OUT_REG0                               , RULL(0x26010C80), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27010C80,
+REG64( EX_4_L2_LSU_HOLD_OUT_REG0                               , RULL(0x28010C80), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29010C80,
+REG64( EX_5_L2_LSU_HOLD_OUT_REG0                               , RULL(0x2A010C80), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B010C80,
+REG64( EX_6_L2_LSU_HOLD_OUT_REG0                               , RULL(0x2C010C80), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D010C80,
+REG64( EX_7_L2_LSU_HOLD_OUT_REG0                               , RULL(0x2E010C80), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F010C80,
+REG64( EX_8_L2_LSU_HOLD_OUT_REG0                               , RULL(0x30010C80), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31010C80,
+REG64( EX_9_L2_LSU_HOLD_OUT_REG0                               , RULL(0x32010C80), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33010C80,
+REG64( EX_L2_LSU_HOLD_OUT_REG0                                 , RULL(0x20010C80), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010C80,
+
+REG64( C_LSU_HOLD_OUT_REG1                                     , RULL(0x20010C81), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_LSU_HOLD_OUT_REG1                                   , RULL(0x20010C81), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_LSU_HOLD_OUT_REG1                                   , RULL(0x21010C81), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_LSU_HOLD_OUT_REG1                                   , RULL(0x22010C81), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_LSU_HOLD_OUT_REG1                                   , RULL(0x23010C81), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_LSU_HOLD_OUT_REG1                                   , RULL(0x24010C81), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_LSU_HOLD_OUT_REG1                                   , RULL(0x25010C81), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_LSU_HOLD_OUT_REG1                                   , RULL(0x26010C81), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_LSU_HOLD_OUT_REG1                                   , RULL(0x27010C81), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_LSU_HOLD_OUT_REG1                                   , RULL(0x28010C81), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_LSU_HOLD_OUT_REG1                                   , RULL(0x29010C81), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_LSU_HOLD_OUT_REG1                                  , RULL(0x2A010C81), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_LSU_HOLD_OUT_REG1                                  , RULL(0x2B010C81), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_LSU_HOLD_OUT_REG1                                  , RULL(0x2C010C81), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_LSU_HOLD_OUT_REG1                                  , RULL(0x2D010C81), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_LSU_HOLD_OUT_REG1                                  , RULL(0x2E010C81), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_LSU_HOLD_OUT_REG1                                  , RULL(0x2F010C81), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_LSU_HOLD_OUT_REG1                                  , RULL(0x30010C81), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_LSU_HOLD_OUT_REG1                                  , RULL(0x31010C81), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_LSU_HOLD_OUT_REG1                                  , RULL(0x32010C81), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_LSU_HOLD_OUT_REG1                                  , RULL(0x33010C81), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_LSU_HOLD_OUT_REG1                                  , RULL(0x34010C81), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_LSU_HOLD_OUT_REG1                                  , RULL(0x35010C81), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_LSU_HOLD_OUT_REG1                                  , RULL(0x36010C81), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_LSU_HOLD_OUT_REG1                                  , RULL(0x37010C81), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_0_L2_LSU_HOLD_OUT_REG1                               , RULL(0x20010C81), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010C81,
+REG64( EX_10_L2_LSU_HOLD_OUT_REG1                              , RULL(0x34010C81), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35010C81,
+REG64( EX_11_L2_LSU_HOLD_OUT_REG1                              , RULL(0x36010C81), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37010C81,
+REG64( EX_1_L2_LSU_HOLD_OUT_REG1                               , RULL(0x22010C81), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23010C81,
+REG64( EX_2_L2_LSU_HOLD_OUT_REG1                               , RULL(0x24010C81), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25010C81,
+REG64( EX_3_L2_LSU_HOLD_OUT_REG1                               , RULL(0x26010C81), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27010C81,
+REG64( EX_4_L2_LSU_HOLD_OUT_REG1                               , RULL(0x28010C81), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29010C81,
+REG64( EX_5_L2_LSU_HOLD_OUT_REG1                               , RULL(0x2A010C81), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B010C81,
+REG64( EX_6_L2_LSU_HOLD_OUT_REG1                               , RULL(0x2C010C81), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D010C81,
+REG64( EX_7_L2_LSU_HOLD_OUT_REG1                               , RULL(0x2E010C81), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F010C81,
+REG64( EX_8_L2_LSU_HOLD_OUT_REG1                               , RULL(0x30010C81), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31010C81,
+REG64( EX_9_L2_LSU_HOLD_OUT_REG1                               , RULL(0x32010C81), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33010C81,
+REG64( EX_L2_LSU_HOLD_OUT_REG1                                 , RULL(0x20010C81), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010C81,
+
+REG64( C_LSU_HOLD_OUT_REG2                                     , RULL(0x20010C82), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_LSU_HOLD_OUT_REG2                                   , RULL(0x20010C82), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_LSU_HOLD_OUT_REG2                                   , RULL(0x21010C82), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_LSU_HOLD_OUT_REG2                                   , RULL(0x22010C82), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_LSU_HOLD_OUT_REG2                                   , RULL(0x23010C82), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_LSU_HOLD_OUT_REG2                                   , RULL(0x24010C82), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_LSU_HOLD_OUT_REG2                                   , RULL(0x25010C82), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_LSU_HOLD_OUT_REG2                                   , RULL(0x26010C82), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_LSU_HOLD_OUT_REG2                                   , RULL(0x27010C82), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_LSU_HOLD_OUT_REG2                                   , RULL(0x28010C82), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_LSU_HOLD_OUT_REG2                                   , RULL(0x29010C82), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_LSU_HOLD_OUT_REG2                                  , RULL(0x2A010C82), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_LSU_HOLD_OUT_REG2                                  , RULL(0x2B010C82), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_LSU_HOLD_OUT_REG2                                  , RULL(0x2C010C82), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_LSU_HOLD_OUT_REG2                                  , RULL(0x2D010C82), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_LSU_HOLD_OUT_REG2                                  , RULL(0x2E010C82), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_LSU_HOLD_OUT_REG2                                  , RULL(0x2F010C82), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_LSU_HOLD_OUT_REG2                                  , RULL(0x30010C82), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_LSU_HOLD_OUT_REG2                                  , RULL(0x31010C82), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_LSU_HOLD_OUT_REG2                                  , RULL(0x32010C82), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_LSU_HOLD_OUT_REG2                                  , RULL(0x33010C82), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_LSU_HOLD_OUT_REG2                                  , RULL(0x34010C82), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_LSU_HOLD_OUT_REG2                                  , RULL(0x35010C82), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_LSU_HOLD_OUT_REG2                                  , RULL(0x36010C82), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_LSU_HOLD_OUT_REG2                                  , RULL(0x37010C82), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_0_L2_LSU_HOLD_OUT_REG2                               , RULL(0x20010C82), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010C82,
+REG64( EX_10_L2_LSU_HOLD_OUT_REG2                              , RULL(0x34010C82), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35010C82,
+REG64( EX_11_L2_LSU_HOLD_OUT_REG2                              , RULL(0x36010C82), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37010C82,
+REG64( EX_1_L2_LSU_HOLD_OUT_REG2                               , RULL(0x22010C82), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23010C82,
+REG64( EX_2_L2_LSU_HOLD_OUT_REG2                               , RULL(0x24010C82), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25010C82,
+REG64( EX_3_L2_LSU_HOLD_OUT_REG2                               , RULL(0x26010C82), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27010C82,
+REG64( EX_4_L2_LSU_HOLD_OUT_REG2                               , RULL(0x28010C82), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29010C82,
+REG64( EX_5_L2_LSU_HOLD_OUT_REG2                               , RULL(0x2A010C82), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B010C82,
+REG64( EX_6_L2_LSU_HOLD_OUT_REG2                               , RULL(0x2C010C82), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D010C82,
+REG64( EX_7_L2_LSU_HOLD_OUT_REG2                               , RULL(0x2E010C82), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F010C82,
+REG64( EX_8_L2_LSU_HOLD_OUT_REG2                               , RULL(0x30010C82), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31010C82,
+REG64( EX_9_L2_LSU_HOLD_OUT_REG2                               , RULL(0x32010C82), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33010C82,
+REG64( EX_L2_LSU_HOLD_OUT_REG2                                 , RULL(0x20010C82), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010C82,
+
+REG64( C_LSU_HOLD_OUT_REG3                                     , RULL(0x20010C83), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_LSU_HOLD_OUT_REG3                                   , RULL(0x20010C83), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_LSU_HOLD_OUT_REG3                                   , RULL(0x21010C83), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_LSU_HOLD_OUT_REG3                                   , RULL(0x22010C83), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_LSU_HOLD_OUT_REG3                                   , RULL(0x23010C83), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_LSU_HOLD_OUT_REG3                                   , RULL(0x24010C83), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_LSU_HOLD_OUT_REG3                                   , RULL(0x25010C83), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_LSU_HOLD_OUT_REG3                                   , RULL(0x26010C83), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_LSU_HOLD_OUT_REG3                                   , RULL(0x27010C83), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_LSU_HOLD_OUT_REG3                                   , RULL(0x28010C83), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_LSU_HOLD_OUT_REG3                                   , RULL(0x29010C83), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_LSU_HOLD_OUT_REG3                                  , RULL(0x2A010C83), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_LSU_HOLD_OUT_REG3                                  , RULL(0x2B010C83), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_LSU_HOLD_OUT_REG3                                  , RULL(0x2C010C83), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_LSU_HOLD_OUT_REG3                                  , RULL(0x2D010C83), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_LSU_HOLD_OUT_REG3                                  , RULL(0x2E010C83), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_LSU_HOLD_OUT_REG3                                  , RULL(0x2F010C83), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_LSU_HOLD_OUT_REG3                                  , RULL(0x30010C83), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_LSU_HOLD_OUT_REG3                                  , RULL(0x31010C83), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_LSU_HOLD_OUT_REG3                                  , RULL(0x32010C83), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_LSU_HOLD_OUT_REG3                                  , RULL(0x33010C83), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_LSU_HOLD_OUT_REG3                                  , RULL(0x34010C83), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_LSU_HOLD_OUT_REG3                                  , RULL(0x35010C83), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_LSU_HOLD_OUT_REG3                                  , RULL(0x36010C83), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_LSU_HOLD_OUT_REG3                                  , RULL(0x37010C83), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_0_L2_LSU_HOLD_OUT_REG3                               , RULL(0x20010C83), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010C83,
+REG64( EX_10_L2_LSU_HOLD_OUT_REG3                              , RULL(0x34010C83), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35010C83,
+REG64( EX_11_L2_LSU_HOLD_OUT_REG3                              , RULL(0x36010C83), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37010C83,
+REG64( EX_1_L2_LSU_HOLD_OUT_REG3                               , RULL(0x22010C83), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23010C83,
+REG64( EX_2_L2_LSU_HOLD_OUT_REG3                               , RULL(0x24010C83), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25010C83,
+REG64( EX_3_L2_LSU_HOLD_OUT_REG3                               , RULL(0x26010C83), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27010C83,
+REG64( EX_4_L2_LSU_HOLD_OUT_REG3                               , RULL(0x28010C83), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29010C83,
+REG64( EX_5_L2_LSU_HOLD_OUT_REG3                               , RULL(0x2A010C83), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B010C83,
+REG64( EX_6_L2_LSU_HOLD_OUT_REG3                               , RULL(0x2C010C83), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D010C83,
+REG64( EX_7_L2_LSU_HOLD_OUT_REG3                               , RULL(0x2E010C83), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F010C83,
+REG64( EX_8_L2_LSU_HOLD_OUT_REG3                               , RULL(0x30010C83), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31010C83,
+REG64( EX_9_L2_LSU_HOLD_OUT_REG3                               , RULL(0x32010C83), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33010C83,
+REG64( EX_L2_LSU_HOLD_OUT_REG3                                 , RULL(0x20010C83), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010C83,
+
+REG64( EQ_MIB_XIICAC                                           , RULL(0x10012419), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012019,
+REG64( EQ_0_MIB_XIICAC                                         , RULL(0x10012419), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012019,
+REG64( EQ_1_MIB_XIICAC                                         , RULL(0x11012419), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012019,
+REG64( EQ_2_MIB_XIICAC                                         , RULL(0x12012419), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012019,
+REG64( EQ_3_MIB_XIICAC                                         , RULL(0x13012419), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012019,
+REG64( EQ_4_MIB_XIICAC                                         , RULL(0x14012419), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012019,
+REG64( EQ_5_MIB_XIICAC                                         , RULL(0x15012419), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012019,
+REG64( EX_MIB_XIICAC                                           , RULL(0x10012019), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_MIB_XIICAC                                         , RULL(0x10012019), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_MIB_XIICAC                                         , RULL(0x10012419), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_MIB_XIICAC                                         , RULL(0x11012019), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_MIB_XIICAC                                         , RULL(0x11012419), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_MIB_XIICAC                                         , RULL(0x12012019), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_MIB_XIICAC                                         , RULL(0x12012419), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_MIB_XIICAC                                         , RULL(0x13012019), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_MIB_XIICAC                                         , RULL(0x13012419), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_MIB_XIICAC                                         , RULL(0x14012019), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_MIB_XIICAC                                         , RULL(0x14012419), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_MIB_XIICAC                                        , RULL(0x15012019), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_MIB_XIICAC                                        , RULL(0x15012419), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_MIB_XIMEM                                            , RULL(0x10012417), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012017,
+REG64( EQ_0_MIB_XIMEM                                          , RULL(0x10012417), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012017,
+REG64( EQ_1_MIB_XIMEM                                          , RULL(0x11012417), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012017,
+REG64( EQ_2_MIB_XIMEM                                          , RULL(0x12012417), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012017,
+REG64( EQ_3_MIB_XIMEM                                          , RULL(0x13012417), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012017,
+REG64( EQ_4_MIB_XIMEM                                          , RULL(0x14012417), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012017,
+REG64( EQ_5_MIB_XIMEM                                          , RULL(0x15012417), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012017,
+REG64( EX_MIB_XIMEM                                            , RULL(0x10012017), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_MIB_XIMEM                                          , RULL(0x10012017), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_MIB_XIMEM                                          , RULL(0x10012417), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_MIB_XIMEM                                          , RULL(0x11012017), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_MIB_XIMEM                                          , RULL(0x11012417), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_MIB_XIMEM                                          , RULL(0x12012017), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_MIB_XIMEM                                          , RULL(0x12012417), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_MIB_XIMEM                                          , RULL(0x13012017), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_MIB_XIMEM                                          , RULL(0x13012417), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_MIB_XIMEM                                          , RULL(0x14012017), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_MIB_XIMEM                                          , RULL(0x14012417), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_MIB_XIMEM                                         , RULL(0x15012017), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_MIB_XIMEM                                         , RULL(0x15012417), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_MIB_XISGB                                            , RULL(0x10012418), SH_UNT_EQ       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012018,
+REG64( EQ_0_MIB_XISGB                                          , RULL(0x10012418), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 10012018,
+REG64( EQ_1_MIB_XISGB                                          , RULL(0x11012418), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 11012018,
+REG64( EQ_2_MIB_XISGB                                          , RULL(0x12012418), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 12012018,
+REG64( EQ_3_MIB_XISGB                                          , RULL(0x13012418), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 13012018,
+REG64( EQ_4_MIB_XISGB                                          , RULL(0x14012418), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 14012018,
+REG64( EQ_5_MIB_XISGB                                          , RULL(0x15012418), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 15012018,
+REG64( EX_MIB_XISGB                                            , RULL(0x10012018), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_MIB_XISGB                                          , RULL(0x10012018), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_1_MIB_XISGB                                          , RULL(0x10012418), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_2_MIB_XISGB                                          , RULL(0x11012018), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_3_MIB_XISGB                                          , RULL(0x11012418), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_4_MIB_XISGB                                          , RULL(0x12012018), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_5_MIB_XISGB                                          , RULL(0x12012418), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_6_MIB_XISGB                                          , RULL(0x13012018), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_7_MIB_XISGB                                          , RULL(0x13012418), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_8_MIB_XISGB                                          , RULL(0x14012018), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_9_MIB_XISGB                                          , RULL(0x14012418), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_10_MIB_XISGB                                         , RULL(0x15012018), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+REG64( EX_11_MIB_XISGB                                         , RULL(0x15012418), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( C_MODE_REG                                              , RULL(0x20040008), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_MODE_REG                                            , RULL(0x20040008), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_MODE_REG                                            , RULL(0x21040008), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_MODE_REG                                            , RULL(0x22040008), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_MODE_REG                                            , RULL(0x23040008), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_MODE_REG                                            , RULL(0x24040008), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_MODE_REG                                            , RULL(0x25040008), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_MODE_REG                                            , RULL(0x26040008), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_MODE_REG                                            , RULL(0x27040008), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_MODE_REG                                            , RULL(0x28040008), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_MODE_REG                                            , RULL(0x29040008), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_MODE_REG                                           , RULL(0x2A040008), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_MODE_REG                                           , RULL(0x2B040008), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_MODE_REG                                           , RULL(0x2C040008), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_MODE_REG                                           , RULL(0x2D040008), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_MODE_REG                                           , RULL(0x2E040008), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_MODE_REG                                           , RULL(0x2F040008), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_MODE_REG                                           , RULL(0x30040008), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_MODE_REG                                           , RULL(0x31040008), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_MODE_REG                                           , RULL(0x32040008), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_MODE_REG                                           , RULL(0x33040008), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_MODE_REG                                           , RULL(0x34040008), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_MODE_REG                                           , RULL(0x35040008), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_MODE_REG                                           , RULL(0x36040008), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_MODE_REG                                           , RULL(0x37040008), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_MODE_REG                                             , RULL(0x10040008), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_MODE_REG                                           , RULL(0x10040008), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_MODE_REG                                           , RULL(0x11040008), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_MODE_REG                                           , RULL(0x12040008), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_MODE_REG                                           , RULL(0x13040008), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_MODE_REG                                           , RULL(0x14040008), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_MODE_REG                                           , RULL(0x15040008), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_MODE_REG                                             , RULL(0x20040008), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21040008,
+REG64( EX_0_MODE_REG                                           , RULL(0x20040008), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21040008,
+REG64( EX_1_MODE_REG                                           , RULL(0x22040008), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23040008,
+REG64( EX_2_MODE_REG                                           , RULL(0x24040008), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25040008,
+REG64( EX_3_MODE_REG                                           , RULL(0x26040008), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27040008,
+REG64( EX_4_MODE_REG                                           , RULL(0x28040008), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29040008,
+REG64( EX_5_MODE_REG                                           , RULL(0x2A040008), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B040008,
+REG64( EX_6_MODE_REG                                           , RULL(0x2C040008), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D040008,
+REG64( EX_7_MODE_REG                                           , RULL(0x2E040008), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F040008,
+REG64( EX_8_MODE_REG                                           , RULL(0x30040008), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31040008,
+REG64( EX_9_MODE_REG                                           , RULL(0x32040008), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33040008,
+REG64( EX_10_MODE_REG                                          , RULL(0x34040008), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35040008,
+REG64( EX_11_MODE_REG                                          , RULL(0x36040008), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37040008,
+
+REG64( EQ_MODE_REG0                                            , RULL(0x1001080A), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 1001182B, 10010C0A, 10011C2B,
+REG64( EQ_0_MODE_REG0                                          , RULL(0x1001080A), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 1001182B, 10010C0A, 10011C2B,
+REG64( EQ_1_MODE_REG0                                          , RULL(0x1101080A), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 1101182B, 11010C0A, 11011C2B,
+REG64( EQ_2_MODE_REG0                                          , RULL(0x1201080A), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 1201182B, 12010C0A, 12011C2B,
+REG64( EQ_3_MODE_REG0                                          , RULL(0x1301080A), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 1301182B, 13010C0A, 13011C2B,
+REG64( EQ_4_MODE_REG0                                          , RULL(0x1401080A), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 1401182B, 14010C0A, 14011C2B,
+REG64( EQ_5_MODE_REG0                                          , RULL(0x1501080A), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 1501182B, 15010C0A, 15011C2B,
+REG64( EX_0_L2_MODE_REG0                                       , RULL(0x1001080A), SH_UNT_EX_0_L2  , SH_ACS_SCOM      );
+REG64( EX_0_L3_MODE_REG0                                       , RULL(0x1001182B), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_L2_MODE_REG0                                      , RULL(0x1501080A), SH_UNT_EX_10_L2 , SH_ACS_SCOM      );
+REG64( EX_10_L3_MODE_REG0                                      , RULL(0x1501182B), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L2_MODE_REG0                                      , RULL(0x15010C0A), SH_UNT_EX_11_L2 , SH_ACS_SCOM      );
+REG64( EX_11_L3_MODE_REG0                                      , RULL(0x15011C2B), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L2_MODE_REG0                                       , RULL(0x10010C0A), SH_UNT_EX_1_L2  , SH_ACS_SCOM      );
+REG64( EX_1_L3_MODE_REG0                                       , RULL(0x10011C2B), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L2_MODE_REG0                                       , RULL(0x1101080A), SH_UNT_EX_2_L2  , SH_ACS_SCOM      );
+REG64( EX_2_L3_MODE_REG0                                       , RULL(0x1101182B), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L2_MODE_REG0                                       , RULL(0x11010C0A), SH_UNT_EX_3_L2  , SH_ACS_SCOM      );
+REG64( EX_3_L3_MODE_REG0                                       , RULL(0x11011C2B), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L2_MODE_REG0                                       , RULL(0x1201080A), SH_UNT_EX_4_L2  , SH_ACS_SCOM      );
+REG64( EX_4_L3_MODE_REG0                                       , RULL(0x1201182B), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L2_MODE_REG0                                       , RULL(0x12010C0A), SH_UNT_EX_5_L2  , SH_ACS_SCOM      );
+REG64( EX_5_L3_MODE_REG0                                       , RULL(0x12011C2B), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L2_MODE_REG0                                       , RULL(0x1301080A), SH_UNT_EX_6_L2  , SH_ACS_SCOM      );
+REG64( EX_6_L3_MODE_REG0                                       , RULL(0x1301182B), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L2_MODE_REG0                                       , RULL(0x13010C0A), SH_UNT_EX_7_L2  , SH_ACS_SCOM      );
+REG64( EX_7_L3_MODE_REG0                                       , RULL(0x13011C2B), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L2_MODE_REG0                                       , RULL(0x1401080A), SH_UNT_EX_8_L2  , SH_ACS_SCOM      );
+REG64( EX_8_L3_MODE_REG0                                       , RULL(0x1401182B), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L2_MODE_REG0                                       , RULL(0x14010C0A), SH_UNT_EX_9_L2  , SH_ACS_SCOM      );
+REG64( EX_9_L3_MODE_REG0                                       , RULL(0x14011C2B), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L2_MODE_REG0                                         , RULL(0x1001080A), SH_UNT_EX_L2    , SH_ACS_SCOM      );
+REG64( EX_L3_MODE_REG0                                         , RULL(0x1001182B), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( EQ_MODE_REG1                                            , RULL(0x1001080B), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 1001180A, 10010C0B, 10011C0A,
+REG64( EQ_0_MODE_REG1                                          , RULL(0x1001080B), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 1001180A, 10010C0B, 10011C0A,
+REG64( EQ_1_MODE_REG1                                          , RULL(0x1101080B), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 1101180A, 11010C0B, 11011C0A,
+REG64( EQ_2_MODE_REG1                                          , RULL(0x1201080B), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 1201180A, 12010C0B, 12011C0A,
+REG64( EQ_3_MODE_REG1                                          , RULL(0x1301080B), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 1301180A, 13010C0B, 13011C0A,
+REG64( EQ_4_MODE_REG1                                          , RULL(0x1401080B), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 1401180A, 14010C0B, 14011C0A,
+REG64( EQ_5_MODE_REG1                                          , RULL(0x1501080B), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 1501180A, 15010C0B, 15011C0A,
+REG64( EX_0_L2_MODE_REG1                                       , RULL(0x1001080B), SH_UNT_EX_0_L2  , SH_ACS_SCOM      );
+REG64( EX_0_L3_MODE_REG1                                       , RULL(0x1001180A), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_L2_MODE_REG1                                      , RULL(0x1501080B), SH_UNT_EX_10_L2 , SH_ACS_SCOM      );
+REG64( EX_10_L3_MODE_REG1                                      , RULL(0x1501180A), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L2_MODE_REG1                                      , RULL(0x15010C0B), SH_UNT_EX_11_L2 , SH_ACS_SCOM      );
+REG64( EX_11_L3_MODE_REG1                                      , RULL(0x15011C0A), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L2_MODE_REG1                                       , RULL(0x10010C0B), SH_UNT_EX_1_L2  , SH_ACS_SCOM      );
+REG64( EX_1_L3_MODE_REG1                                       , RULL(0x10011C0A), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L2_MODE_REG1                                       , RULL(0x1101080B), SH_UNT_EX_2_L2  , SH_ACS_SCOM      );
+REG64( EX_2_L3_MODE_REG1                                       , RULL(0x1101180A), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L2_MODE_REG1                                       , RULL(0x11010C0B), SH_UNT_EX_3_L2  , SH_ACS_SCOM      );
+REG64( EX_3_L3_MODE_REG1                                       , RULL(0x11011C0A), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L2_MODE_REG1                                       , RULL(0x1201080B), SH_UNT_EX_4_L2  , SH_ACS_SCOM      );
+REG64( EX_4_L3_MODE_REG1                                       , RULL(0x1201180A), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L2_MODE_REG1                                       , RULL(0x12010C0B), SH_UNT_EX_5_L2  , SH_ACS_SCOM      );
+REG64( EX_5_L3_MODE_REG1                                       , RULL(0x12011C0A), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L2_MODE_REG1                                       , RULL(0x1301080B), SH_UNT_EX_6_L2  , SH_ACS_SCOM      );
+REG64( EX_6_L3_MODE_REG1                                       , RULL(0x1301180A), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L2_MODE_REG1                                       , RULL(0x13010C0B), SH_UNT_EX_7_L2  , SH_ACS_SCOM      );
+REG64( EX_7_L3_MODE_REG1                                       , RULL(0x13011C0A), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L2_MODE_REG1                                       , RULL(0x1401080B), SH_UNT_EX_8_L2  , SH_ACS_SCOM      );
+REG64( EX_8_L3_MODE_REG1                                       , RULL(0x1401180A), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L2_MODE_REG1                                       , RULL(0x14010C0B), SH_UNT_EX_9_L2  , SH_ACS_SCOM      );
+REG64( EX_9_L3_MODE_REG1                                       , RULL(0x14011C0A), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L2_MODE_REG1                                         , RULL(0x1001080B), SH_UNT_EX_L2    , SH_ACS_SCOM      );
+REG64( EX_L3_MODE_REG1                                         , RULL(0x1001180A), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( C_MULTICAST_GROUP_1                                     , RULL(0x200F0001), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_MULTICAST_GROUP_1                                   , RULL(0x200F0001), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_MULTICAST_GROUP_1                                   , RULL(0x210F0001), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_MULTICAST_GROUP_1                                   , RULL(0x220F0001), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_MULTICAST_GROUP_1                                   , RULL(0x230F0001), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_MULTICAST_GROUP_1                                   , RULL(0x240F0001), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_MULTICAST_GROUP_1                                   , RULL(0x250F0001), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_MULTICAST_GROUP_1                                   , RULL(0x260F0001), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_MULTICAST_GROUP_1                                   , RULL(0x270F0001), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_MULTICAST_GROUP_1                                   , RULL(0x280F0001), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_MULTICAST_GROUP_1                                   , RULL(0x290F0001), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_MULTICAST_GROUP_1                                  , RULL(0x2A0F0001), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_MULTICAST_GROUP_1                                  , RULL(0x2B0F0001), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_MULTICAST_GROUP_1                                  , RULL(0x2C0F0001), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_MULTICAST_GROUP_1                                  , RULL(0x2D0F0001), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_MULTICAST_GROUP_1                                  , RULL(0x2E0F0001), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_MULTICAST_GROUP_1                                  , RULL(0x2F0F0001), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_MULTICAST_GROUP_1                                  , RULL(0x300F0001), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_MULTICAST_GROUP_1                                  , RULL(0x310F0001), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_MULTICAST_GROUP_1                                  , RULL(0x320F0001), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_MULTICAST_GROUP_1                                  , RULL(0x330F0001), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_MULTICAST_GROUP_1                                  , RULL(0x340F0001), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_MULTICAST_GROUP_1                                  , RULL(0x350F0001), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_MULTICAST_GROUP_1                                  , RULL(0x360F0001), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_MULTICAST_GROUP_1                                  , RULL(0x370F0001), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_MULTICAST_GROUP_1                                    , RULL(0x100F0001), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_MULTICAST_GROUP_1                                  , RULL(0x100F0001), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_MULTICAST_GROUP_1                                  , RULL(0x110F0001), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_MULTICAST_GROUP_1                                  , RULL(0x120F0001), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_MULTICAST_GROUP_1                                  , RULL(0x130F0001), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_MULTICAST_GROUP_1                                  , RULL(0x140F0001), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_MULTICAST_GROUP_1                                  , RULL(0x150F0001), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_MULTICAST_GROUP_1                                    , RULL(0x200F0001), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0001,
+REG64( EX_0_MULTICAST_GROUP_1                                  , RULL(0x200F0001), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0001,
+REG64( EX_1_MULTICAST_GROUP_1                                  , RULL(0x230F0001), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0001,
+REG64( EX_2_MULTICAST_GROUP_1                                  , RULL(0x240F0001), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0001,
+REG64( EX_3_MULTICAST_GROUP_1                                  , RULL(0x260F0001), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0001,
+REG64( EX_4_MULTICAST_GROUP_1                                  , RULL(0x280F0001), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0001,
+REG64( EX_5_MULTICAST_GROUP_1                                  , RULL(0x2A0F0001), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0001,
+REG64( EX_6_MULTICAST_GROUP_1                                  , RULL(0x2C0F0001), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0001,
+REG64( EX_7_MULTICAST_GROUP_1                                  , RULL(0x2E0F0001), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0001,
+REG64( EX_8_MULTICAST_GROUP_1                                  , RULL(0x300F0001), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0001,
+REG64( EX_9_MULTICAST_GROUP_1                                  , RULL(0x320F0001), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0001,
+REG64( EX_10_MULTICAST_GROUP_1                                 , RULL(0x340F0001), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0001,
+REG64( EX_11_MULTICAST_GROUP_1                                 , RULL(0x360F0001), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0001,
+
+REG64( C_MULTICAST_GROUP_2                                     , RULL(0x200F0002), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_MULTICAST_GROUP_2                                   , RULL(0x200F0002), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_MULTICAST_GROUP_2                                   , RULL(0x210F0002), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_MULTICAST_GROUP_2                                   , RULL(0x220F0002), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_MULTICAST_GROUP_2                                   , RULL(0x230F0002), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_MULTICAST_GROUP_2                                   , RULL(0x240F0002), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_MULTICAST_GROUP_2                                   , RULL(0x250F0002), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_MULTICAST_GROUP_2                                   , RULL(0x260F0002), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_MULTICAST_GROUP_2                                   , RULL(0x270F0002), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_MULTICAST_GROUP_2                                   , RULL(0x280F0002), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_MULTICAST_GROUP_2                                   , RULL(0x290F0002), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_MULTICAST_GROUP_2                                  , RULL(0x2A0F0002), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_MULTICAST_GROUP_2                                  , RULL(0x2B0F0002), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_MULTICAST_GROUP_2                                  , RULL(0x2C0F0002), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_MULTICAST_GROUP_2                                  , RULL(0x2D0F0002), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_MULTICAST_GROUP_2                                  , RULL(0x2E0F0002), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_MULTICAST_GROUP_2                                  , RULL(0x2F0F0002), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_MULTICAST_GROUP_2                                  , RULL(0x300F0002), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_MULTICAST_GROUP_2                                  , RULL(0x310F0002), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_MULTICAST_GROUP_2                                  , RULL(0x320F0002), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_MULTICAST_GROUP_2                                  , RULL(0x330F0002), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_MULTICAST_GROUP_2                                  , RULL(0x340F0002), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_MULTICAST_GROUP_2                                  , RULL(0x350F0002), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_MULTICAST_GROUP_2                                  , RULL(0x360F0002), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_MULTICAST_GROUP_2                                  , RULL(0x370F0002), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_MULTICAST_GROUP_2                                    , RULL(0x100F0002), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_MULTICAST_GROUP_2                                  , RULL(0x100F0002), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_MULTICAST_GROUP_2                                  , RULL(0x110F0002), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_MULTICAST_GROUP_2                                  , RULL(0x120F0002), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_MULTICAST_GROUP_2                                  , RULL(0x130F0002), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_MULTICAST_GROUP_2                                  , RULL(0x140F0002), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_MULTICAST_GROUP_2                                  , RULL(0x150F0002), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_MULTICAST_GROUP_2                                    , RULL(0x200F0002), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0002,
+REG64( EX_0_MULTICAST_GROUP_2                                  , RULL(0x200F0002), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0002,
+REG64( EX_1_MULTICAST_GROUP_2                                  , RULL(0x230F0002), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0002,
+REG64( EX_2_MULTICAST_GROUP_2                                  , RULL(0x240F0002), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0002,
+REG64( EX_3_MULTICAST_GROUP_2                                  , RULL(0x260F0002), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0002,
+REG64( EX_4_MULTICAST_GROUP_2                                  , RULL(0x280F0002), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0002,
+REG64( EX_5_MULTICAST_GROUP_2                                  , RULL(0x2A0F0002), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0002,
+REG64( EX_6_MULTICAST_GROUP_2                                  , RULL(0x2C0F0002), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0002,
+REG64( EX_7_MULTICAST_GROUP_2                                  , RULL(0x2E0F0002), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0002,
+REG64( EX_8_MULTICAST_GROUP_2                                  , RULL(0x300F0002), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0002,
+REG64( EX_9_MULTICAST_GROUP_2                                  , RULL(0x320F0002), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0002,
+REG64( EX_10_MULTICAST_GROUP_2                                 , RULL(0x340F0002), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0002,
+REG64( EX_11_MULTICAST_GROUP_2                                 , RULL(0x360F0002), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0002,
+
+REG64( C_MULTICAST_GROUP_3                                     , RULL(0x200F0003), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_MULTICAST_GROUP_3                                   , RULL(0x200F0003), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_MULTICAST_GROUP_3                                   , RULL(0x210F0003), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_MULTICAST_GROUP_3                                   , RULL(0x220F0003), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_MULTICAST_GROUP_3                                   , RULL(0x230F0003), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_MULTICAST_GROUP_3                                   , RULL(0x240F0003), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_MULTICAST_GROUP_3                                   , RULL(0x250F0003), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_MULTICAST_GROUP_3                                   , RULL(0x260F0003), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_MULTICAST_GROUP_3                                   , RULL(0x270F0003), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_MULTICAST_GROUP_3                                   , RULL(0x280F0003), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_MULTICAST_GROUP_3                                   , RULL(0x290F0003), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_MULTICAST_GROUP_3                                  , RULL(0x2A0F0003), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_MULTICAST_GROUP_3                                  , RULL(0x2B0F0003), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_MULTICAST_GROUP_3                                  , RULL(0x2C0F0003), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_MULTICAST_GROUP_3                                  , RULL(0x2D0F0003), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_MULTICAST_GROUP_3                                  , RULL(0x2E0F0003), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_MULTICAST_GROUP_3                                  , RULL(0x2F0F0003), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_MULTICAST_GROUP_3                                  , RULL(0x300F0003), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_MULTICAST_GROUP_3                                  , RULL(0x310F0003), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_MULTICAST_GROUP_3                                  , RULL(0x320F0003), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_MULTICAST_GROUP_3                                  , RULL(0x330F0003), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_MULTICAST_GROUP_3                                  , RULL(0x340F0003), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_MULTICAST_GROUP_3                                  , RULL(0x350F0003), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_MULTICAST_GROUP_3                                  , RULL(0x360F0003), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_MULTICAST_GROUP_3                                  , RULL(0x370F0003), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_MULTICAST_GROUP_3                                    , RULL(0x100F0003), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_MULTICAST_GROUP_3                                  , RULL(0x100F0003), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_MULTICAST_GROUP_3                                  , RULL(0x110F0003), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_MULTICAST_GROUP_3                                  , RULL(0x120F0003), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_MULTICAST_GROUP_3                                  , RULL(0x130F0003), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_MULTICAST_GROUP_3                                  , RULL(0x140F0003), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_MULTICAST_GROUP_3                                  , RULL(0x150F0003), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_MULTICAST_GROUP_3                                    , RULL(0x200F0003), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0003,
+REG64( EX_0_MULTICAST_GROUP_3                                  , RULL(0x200F0003), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0003,
+REG64( EX_1_MULTICAST_GROUP_3                                  , RULL(0x230F0003), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0003,
+REG64( EX_2_MULTICAST_GROUP_3                                  , RULL(0x240F0003), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0003,
+REG64( EX_3_MULTICAST_GROUP_3                                  , RULL(0x260F0003), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0003,
+REG64( EX_4_MULTICAST_GROUP_3                                  , RULL(0x280F0003), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0003,
+REG64( EX_5_MULTICAST_GROUP_3                                  , RULL(0x2A0F0003), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0003,
+REG64( EX_6_MULTICAST_GROUP_3                                  , RULL(0x2C0F0003), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0003,
+REG64( EX_7_MULTICAST_GROUP_3                                  , RULL(0x2E0F0003), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0003,
+REG64( EX_8_MULTICAST_GROUP_3                                  , RULL(0x300F0003), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0003,
+REG64( EX_9_MULTICAST_GROUP_3                                  , RULL(0x320F0003), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0003,
+REG64( EX_10_MULTICAST_GROUP_3                                 , RULL(0x340F0003), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0003,
+REG64( EX_11_MULTICAST_GROUP_3                                 , RULL(0x360F0003), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0003,
+
+REG64( C_MULTICAST_GROUP_4                                     , RULL(0x200F0004), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_MULTICAST_GROUP_4                                   , RULL(0x200F0004), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_MULTICAST_GROUP_4                                   , RULL(0x210F0004), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_MULTICAST_GROUP_4                                   , RULL(0x220F0004), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_MULTICAST_GROUP_4                                   , RULL(0x230F0004), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_MULTICAST_GROUP_4                                   , RULL(0x240F0004), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_MULTICAST_GROUP_4                                   , RULL(0x250F0004), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_MULTICAST_GROUP_4                                   , RULL(0x260F0004), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_MULTICAST_GROUP_4                                   , RULL(0x270F0004), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_MULTICAST_GROUP_4                                   , RULL(0x280F0004), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_MULTICAST_GROUP_4                                   , RULL(0x290F0004), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_MULTICAST_GROUP_4                                  , RULL(0x2A0F0004), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_MULTICAST_GROUP_4                                  , RULL(0x2B0F0004), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_MULTICAST_GROUP_4                                  , RULL(0x2C0F0004), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_MULTICAST_GROUP_4                                  , RULL(0x2D0F0004), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_MULTICAST_GROUP_4                                  , RULL(0x2E0F0004), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_MULTICAST_GROUP_4                                  , RULL(0x2F0F0004), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_MULTICAST_GROUP_4                                  , RULL(0x300F0004), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_MULTICAST_GROUP_4                                  , RULL(0x310F0004), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_MULTICAST_GROUP_4                                  , RULL(0x320F0004), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_MULTICAST_GROUP_4                                  , RULL(0x330F0004), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_MULTICAST_GROUP_4                                  , RULL(0x340F0004), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_MULTICAST_GROUP_4                                  , RULL(0x350F0004), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_MULTICAST_GROUP_4                                  , RULL(0x360F0004), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_MULTICAST_GROUP_4                                  , RULL(0x370F0004), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_MULTICAST_GROUP_4                                    , RULL(0x100F0004), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_MULTICAST_GROUP_4                                  , RULL(0x100F0004), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_MULTICAST_GROUP_4                                  , RULL(0x110F0004), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_MULTICAST_GROUP_4                                  , RULL(0x120F0004), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_MULTICAST_GROUP_4                                  , RULL(0x130F0004), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_MULTICAST_GROUP_4                                  , RULL(0x140F0004), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_MULTICAST_GROUP_4                                  , RULL(0x150F0004), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_MULTICAST_GROUP_4                                    , RULL(0x200F0004), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0004,
+REG64( EX_0_MULTICAST_GROUP_4                                  , RULL(0x200F0004), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0004,
+REG64( EX_1_MULTICAST_GROUP_4                                  , RULL(0x230F0004), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0004,
+REG64( EX_2_MULTICAST_GROUP_4                                  , RULL(0x240F0004), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0004,
+REG64( EX_3_MULTICAST_GROUP_4                                  , RULL(0x260F0004), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0004,
+REG64( EX_4_MULTICAST_GROUP_4                                  , RULL(0x280F0004), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0004,
+REG64( EX_5_MULTICAST_GROUP_4                                  , RULL(0x2A0F0004), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0004,
+REG64( EX_6_MULTICAST_GROUP_4                                  , RULL(0x2C0F0004), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0004,
+REG64( EX_7_MULTICAST_GROUP_4                                  , RULL(0x2E0F0004), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0004,
+REG64( EX_8_MULTICAST_GROUP_4                                  , RULL(0x300F0004), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0004,
+REG64( EX_9_MULTICAST_GROUP_4                                  , RULL(0x320F0004), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0004,
+REG64( EX_10_MULTICAST_GROUP_4                                 , RULL(0x340F0004), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0004,
+REG64( EX_11_MULTICAST_GROUP_4                                 , RULL(0x360F0004), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0004,
+
+REG64( EQ_NCU_DARN_BAR_REG                                     , RULL(0x10011011), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011411,
+REG64( EQ_0_NCU_DARN_BAR_REG                                   , RULL(0x10011011), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011411,
+REG64( EQ_1_NCU_DARN_BAR_REG                                   , RULL(0x11011011), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011411,
+REG64( EQ_2_NCU_DARN_BAR_REG                                   , RULL(0x12011011), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011411,
+REG64( EQ_3_NCU_DARN_BAR_REG                                   , RULL(0x13011011), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011411,
+REG64( EQ_4_NCU_DARN_BAR_REG                                   , RULL(0x14011011), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011411,
+REG64( EQ_5_NCU_DARN_BAR_REG                                   , RULL(0x15011011), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011411,
+REG64( EX_NCU_DARN_BAR_REG                                     , RULL(0x10011011), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_NCU_DARN_BAR_REG                                   , RULL(0x10011011), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_NCU_DARN_BAR_REG                                   , RULL(0x10011411), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_NCU_DARN_BAR_REG                                   , RULL(0x11011011), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_NCU_DARN_BAR_REG                                   , RULL(0x11011411), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_NCU_DARN_BAR_REG                                   , RULL(0x12011011), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_NCU_DARN_BAR_REG                                   , RULL(0x12011411), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_NCU_DARN_BAR_REG                                   , RULL(0x13011011), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_NCU_DARN_BAR_REG                                   , RULL(0x13011411), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_NCU_DARN_BAR_REG                                   , RULL(0x14011011), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_NCU_DARN_BAR_REG                                   , RULL(0x14011411), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_NCU_DARN_BAR_REG                                  , RULL(0x15011011), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_NCU_DARN_BAR_REG                                  , RULL(0x15011411), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_NCU_MODE_REG                                         , RULL(0x1001100A), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 1001140A,
+REG64( EQ_0_NCU_MODE_REG                                       , RULL(0x1001100A), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 1001140A,
+REG64( EQ_1_NCU_MODE_REG                                       , RULL(0x1101100A), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 1101140A,
+REG64( EQ_2_NCU_MODE_REG                                       , RULL(0x1201100A), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 1201140A,
+REG64( EQ_3_NCU_MODE_REG                                       , RULL(0x1301100A), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 1301140A,
+REG64( EQ_4_NCU_MODE_REG                                       , RULL(0x1401100A), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 1401140A,
+REG64( EQ_5_NCU_MODE_REG                                       , RULL(0x1501100A), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 1501140A,
+REG64( EX_NCU_MODE_REG                                         , RULL(0x1001100A), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_NCU_MODE_REG                                       , RULL(0x1001100A), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_NCU_MODE_REG                                       , RULL(0x1001140A), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_NCU_MODE_REG                                       , RULL(0x1101100A), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_NCU_MODE_REG                                       , RULL(0x1101140A), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_NCU_MODE_REG                                       , RULL(0x1201100A), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_NCU_MODE_REG                                       , RULL(0x1201140A), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_NCU_MODE_REG                                       , RULL(0x1301100A), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_NCU_MODE_REG                                       , RULL(0x1301140A), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_NCU_MODE_REG                                       , RULL(0x1401100A), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_NCU_MODE_REG                                       , RULL(0x1401140A), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_NCU_MODE_REG                                      , RULL(0x1501100A), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_NCU_MODE_REG                                      , RULL(0x1501140A), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_NCU_MODE_REG2                                        , RULL(0x1001100B), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 1001140B,
+REG64( EQ_0_NCU_MODE_REG2                                      , RULL(0x1001100B), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 1001140B,
+REG64( EQ_1_NCU_MODE_REG2                                      , RULL(0x1101100B), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 1101140B,
+REG64( EQ_2_NCU_MODE_REG2                                      , RULL(0x1201100B), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 1201140B,
+REG64( EQ_3_NCU_MODE_REG2                                      , RULL(0x1301100B), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 1301140B,
+REG64( EQ_4_NCU_MODE_REG2                                      , RULL(0x1401100B), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 1401140B,
+REG64( EQ_5_NCU_MODE_REG2                                      , RULL(0x1501100B), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 1501140B,
+REG64( EX_NCU_MODE_REG2                                        , RULL(0x1001100B), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_NCU_MODE_REG2                                      , RULL(0x1001100B), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_NCU_MODE_REG2                                      , RULL(0x1001140B), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_NCU_MODE_REG2                                      , RULL(0x1101100B), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_NCU_MODE_REG2                                      , RULL(0x1101140B), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_NCU_MODE_REG2                                      , RULL(0x1201100B), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_NCU_MODE_REG2                                      , RULL(0x1201140B), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_NCU_MODE_REG2                                      , RULL(0x1301100B), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_NCU_MODE_REG2                                      , RULL(0x1301140B), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_NCU_MODE_REG2                                      , RULL(0x1401100B), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_NCU_MODE_REG2                                      , RULL(0x1401140B), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_NCU_MODE_REG2                                     , RULL(0x1501100B), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_NCU_MODE_REG2                                     , RULL(0x1501140B), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_NCU_MODE_REG3                                        , RULL(0x1001100C), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 1001140C,
+REG64( EQ_0_NCU_MODE_REG3                                      , RULL(0x1001100C), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 1001140C,
+REG64( EQ_1_NCU_MODE_REG3                                      , RULL(0x1101100C), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 1101140C,
+REG64( EQ_2_NCU_MODE_REG3                                      , RULL(0x1201100C), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 1201140C,
+REG64( EQ_3_NCU_MODE_REG3                                      , RULL(0x1301100C), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 1301140C,
+REG64( EQ_4_NCU_MODE_REG3                                      , RULL(0x1401100C), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 1401140C,
+REG64( EQ_5_NCU_MODE_REG3                                      , RULL(0x1501100C), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 1501140C,
+REG64( EX_NCU_MODE_REG3                                        , RULL(0x1001100C), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_NCU_MODE_REG3                                      , RULL(0x1001100C), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_NCU_MODE_REG3                                      , RULL(0x1001140C), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_NCU_MODE_REG3                                      , RULL(0x1101100C), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_NCU_MODE_REG3                                      , RULL(0x1101140C), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_NCU_MODE_REG3                                      , RULL(0x1201100C), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_NCU_MODE_REG3                                      , RULL(0x1201140C), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_NCU_MODE_REG3                                      , RULL(0x1301100C), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_NCU_MODE_REG3                                      , RULL(0x1301140C), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_NCU_MODE_REG3                                      , RULL(0x1401100C), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_NCU_MODE_REG3                                      , RULL(0x1401140C), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_NCU_MODE_REG3                                     , RULL(0x1501100C), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_NCU_MODE_REG3                                     , RULL(0x1501140C), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_NCU_SLOW_LPAR_REG0                                   , RULL(0x10011012), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011412,
+REG64( EQ_0_NCU_SLOW_LPAR_REG0                                 , RULL(0x10011012), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011412,
+REG64( EQ_1_NCU_SLOW_LPAR_REG0                                 , RULL(0x11011012), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011412,
+REG64( EQ_2_NCU_SLOW_LPAR_REG0                                 , RULL(0x12011012), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011412,
+REG64( EQ_3_NCU_SLOW_LPAR_REG0                                 , RULL(0x13011012), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011412,
+REG64( EQ_4_NCU_SLOW_LPAR_REG0                                 , RULL(0x14011012), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011412,
+REG64( EQ_5_NCU_SLOW_LPAR_REG0                                 , RULL(0x15011012), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011412,
+REG64( EX_NCU_SLOW_LPAR_REG0                                   , RULL(0x10011012), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_NCU_SLOW_LPAR_REG0                                 , RULL(0x10011012), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_NCU_SLOW_LPAR_REG0                                 , RULL(0x10011412), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_NCU_SLOW_LPAR_REG0                                 , RULL(0x11011012), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_NCU_SLOW_LPAR_REG0                                 , RULL(0x11011412), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_NCU_SLOW_LPAR_REG0                                 , RULL(0x12011012), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_NCU_SLOW_LPAR_REG0                                 , RULL(0x12011412), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_NCU_SLOW_LPAR_REG0                                 , RULL(0x13011012), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_NCU_SLOW_LPAR_REG0                                 , RULL(0x13011412), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_NCU_SLOW_LPAR_REG0                                 , RULL(0x14011012), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_NCU_SLOW_LPAR_REG0                                 , RULL(0x14011412), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_NCU_SLOW_LPAR_REG0                                , RULL(0x15011012), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_NCU_SLOW_LPAR_REG0                                , RULL(0x15011412), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_NCU_SLOW_LPAR_REG1                                   , RULL(0x10011013), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011413,
+REG64( EQ_0_NCU_SLOW_LPAR_REG1                                 , RULL(0x10011013), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011413,
+REG64( EQ_1_NCU_SLOW_LPAR_REG1                                 , RULL(0x11011013), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011413,
+REG64( EQ_2_NCU_SLOW_LPAR_REG1                                 , RULL(0x12011013), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011413,
+REG64( EQ_3_NCU_SLOW_LPAR_REG1                                 , RULL(0x13011013), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011413,
+REG64( EQ_4_NCU_SLOW_LPAR_REG1                                 , RULL(0x14011013), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011413,
+REG64( EQ_5_NCU_SLOW_LPAR_REG1                                 , RULL(0x15011013), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011413,
+REG64( EX_NCU_SLOW_LPAR_REG1                                   , RULL(0x10011013), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_NCU_SLOW_LPAR_REG1                                 , RULL(0x10011013), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_NCU_SLOW_LPAR_REG1                                 , RULL(0x10011413), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_NCU_SLOW_LPAR_REG1                                 , RULL(0x11011013), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_NCU_SLOW_LPAR_REG1                                 , RULL(0x11011413), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_NCU_SLOW_LPAR_REG1                                 , RULL(0x12011013), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_NCU_SLOW_LPAR_REG1                                 , RULL(0x12011413), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_NCU_SLOW_LPAR_REG1                                 , RULL(0x13011013), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_NCU_SLOW_LPAR_REG1                                 , RULL(0x13011413), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_NCU_SLOW_LPAR_REG1                                 , RULL(0x14011013), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_NCU_SLOW_LPAR_REG1                                 , RULL(0x14011413), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_NCU_SLOW_LPAR_REG1                                , RULL(0x15011013), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_NCU_SLOW_LPAR_REG1                                , RULL(0x15011413), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_NCU_SPEC_BAR_REG                                     , RULL(0x10011010), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011410,
+REG64( EQ_0_NCU_SPEC_BAR_REG                                   , RULL(0x10011010), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011410,
+REG64( EQ_1_NCU_SPEC_BAR_REG                                   , RULL(0x11011010), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011410,
+REG64( EQ_2_NCU_SPEC_BAR_REG                                   , RULL(0x12011010), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011410,
+REG64( EQ_3_NCU_SPEC_BAR_REG                                   , RULL(0x13011010), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011410,
+REG64( EQ_4_NCU_SPEC_BAR_REG                                   , RULL(0x14011010), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011410,
+REG64( EQ_5_NCU_SPEC_BAR_REG                                   , RULL(0x15011010), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011410,
+REG64( EX_NCU_SPEC_BAR_REG                                     , RULL(0x10011010), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_NCU_SPEC_BAR_REG                                   , RULL(0x10011010), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_NCU_SPEC_BAR_REG                                   , RULL(0x10011410), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_NCU_SPEC_BAR_REG                                   , RULL(0x11011010), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_NCU_SPEC_BAR_REG                                   , RULL(0x11011410), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_NCU_SPEC_BAR_REG                                   , RULL(0x12011010), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_NCU_SPEC_BAR_REG                                   , RULL(0x12011410), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_NCU_SPEC_BAR_REG                                   , RULL(0x13011010), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_NCU_SPEC_BAR_REG                                   , RULL(0x13011410), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_NCU_SPEC_BAR_REG                                   , RULL(0x14011010), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_NCU_SPEC_BAR_REG                                   , RULL(0x14011410), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_NCU_SPEC_BAR_REG                                  , RULL(0x15011010), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_NCU_SPEC_BAR_REG                                  , RULL(0x15011410), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_NCU_STATUS_REG                                       , RULL(0x1001100F), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 1001140F,
+REG64( EQ_0_NCU_STATUS_REG                                     , RULL(0x1001100F), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 1001140F,
+REG64( EQ_1_NCU_STATUS_REG                                     , RULL(0x1101100F), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 1101140F,
+REG64( EQ_2_NCU_STATUS_REG                                     , RULL(0x1201100F), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 1201140F,
+REG64( EQ_3_NCU_STATUS_REG                                     , RULL(0x1301100F), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 1301140F,
+REG64( EQ_4_NCU_STATUS_REG                                     , RULL(0x1401100F), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 1401140F,
+REG64( EQ_5_NCU_STATUS_REG                                     , RULL(0x1501100F), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 1501140F,
+REG64( EX_NCU_STATUS_REG                                       , RULL(0x1001100F), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_NCU_STATUS_REG                                     , RULL(0x1001100F), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_NCU_STATUS_REG                                     , RULL(0x1001140F), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_NCU_STATUS_REG                                     , RULL(0x1101100F), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_NCU_STATUS_REG                                     , RULL(0x1101140F), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_NCU_STATUS_REG                                     , RULL(0x1201100F), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_NCU_STATUS_REG                                     , RULL(0x1201140F), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_NCU_STATUS_REG                                     , RULL(0x1301100F), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_NCU_STATUS_REG                                     , RULL(0x1301140F), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_NCU_STATUS_REG                                     , RULL(0x1401100F), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_NCU_STATUS_REG                                     , RULL(0x1401140F), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_NCU_STATUS_REG                                    , RULL(0x1501100F), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_NCU_STATUS_REG                                    , RULL(0x1501140F), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( C_NET_CTRL0                                             , RULL(0x200F0040), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_NET_CTRL0_WAND                                        , RULL(0x200F0041), SH_UNT_C        ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_NET_CTRL0_WOR                                         , RULL(0x200F0042), SH_UNT_C        , SH_ACS_SCOM2_WOR );
+REG64( C_0_NET_CTRL0                                           , RULL(0x200F0040), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_NET_CTRL0_WAND                                      , RULL(0x200F0041), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_0_NET_CTRL0_WOR                                       , RULL(0x200F0042), SH_UNT_C_0      , SH_ACS_SCOM2_WOR );
+REG64( C_1_NET_CTRL0                                           , RULL(0x210F0040), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_NET_CTRL0_WAND                                      , RULL(0x210F0041), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_1_NET_CTRL0_WOR                                       , RULL(0x210F0042), SH_UNT_C_1      , SH_ACS_SCOM2_WOR );
+REG64( C_2_NET_CTRL0                                           , RULL(0x220F0040), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_NET_CTRL0_WAND                                      , RULL(0x220F0041), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_2_NET_CTRL0_WOR                                       , RULL(0x220F0042), SH_UNT_C_2      , SH_ACS_SCOM2_WOR );
+REG64( C_3_NET_CTRL0                                           , RULL(0x230F0040), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_NET_CTRL0_WAND                                      , RULL(0x230F0041), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_3_NET_CTRL0_WOR                                       , RULL(0x230F0042), SH_UNT_C_3      , SH_ACS_SCOM2_WOR );
+REG64( C_4_NET_CTRL0                                           , RULL(0x240F0040), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_NET_CTRL0_WAND                                      , RULL(0x240F0041), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_4_NET_CTRL0_WOR                                       , RULL(0x240F0042), SH_UNT_C_4      , SH_ACS_SCOM2_WOR );
+REG64( C_5_NET_CTRL0                                           , RULL(0x250F0040), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_NET_CTRL0_WAND                                      , RULL(0x250F0041), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_5_NET_CTRL0_WOR                                       , RULL(0x250F0042), SH_UNT_C_5      , SH_ACS_SCOM2_WOR );
+REG64( C_6_NET_CTRL0                                           , RULL(0x260F0040), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_NET_CTRL0_WAND                                      , RULL(0x260F0041), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_6_NET_CTRL0_WOR                                       , RULL(0x260F0042), SH_UNT_C_6      , SH_ACS_SCOM2_WOR );
+REG64( C_7_NET_CTRL0                                           , RULL(0x270F0040), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_NET_CTRL0_WAND                                      , RULL(0x270F0041), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_7_NET_CTRL0_WOR                                       , RULL(0x270F0042), SH_UNT_C_7      , SH_ACS_SCOM2_WOR );
+REG64( C_8_NET_CTRL0                                           , RULL(0x280F0040), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_NET_CTRL0_WAND                                      , RULL(0x280F0041), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_8_NET_CTRL0_WOR                                       , RULL(0x280F0042), SH_UNT_C_8      , SH_ACS_SCOM2_WOR );
+REG64( C_9_NET_CTRL0                                           , RULL(0x290F0040), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_NET_CTRL0_WAND                                      , RULL(0x290F0041), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_9_NET_CTRL0_WOR                                       , RULL(0x290F0042), SH_UNT_C_9      , SH_ACS_SCOM2_WOR );
+REG64( C_10_NET_CTRL0                                          , RULL(0x2A0F0040), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_NET_CTRL0_WAND                                     , RULL(0x2A0F0041), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_10_NET_CTRL0_WOR                                      , RULL(0x2A0F0042), SH_UNT_C_10     , SH_ACS_SCOM2_WOR );
+REG64( C_11_NET_CTRL0                                          , RULL(0x2B0F0040), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_NET_CTRL0_WAND                                     , RULL(0x2B0F0041), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_11_NET_CTRL0_WOR                                      , RULL(0x2B0F0042), SH_UNT_C_11     , SH_ACS_SCOM2_WOR );
+REG64( C_12_NET_CTRL0                                          , RULL(0x2C0F0040), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_NET_CTRL0_WAND                                     , RULL(0x2C0F0041), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_12_NET_CTRL0_WOR                                      , RULL(0x2C0F0042), SH_UNT_C_12     , SH_ACS_SCOM2_WOR );
+REG64( C_13_NET_CTRL0                                          , RULL(0x2D0F0040), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_NET_CTRL0_WAND                                     , RULL(0x2D0F0041), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_13_NET_CTRL0_WOR                                      , RULL(0x2D0F0042), SH_UNT_C_13     , SH_ACS_SCOM2_WOR );
+REG64( C_14_NET_CTRL0                                          , RULL(0x2E0F0040), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_NET_CTRL0_WAND                                     , RULL(0x2E0F0041), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_14_NET_CTRL0_WOR                                      , RULL(0x2E0F0042), SH_UNT_C_14     , SH_ACS_SCOM2_WOR );
+REG64( C_15_NET_CTRL0                                          , RULL(0x2F0F0040), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_NET_CTRL0_WAND                                     , RULL(0x2F0F0041), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_15_NET_CTRL0_WOR                                      , RULL(0x2F0F0042), SH_UNT_C_15     , SH_ACS_SCOM2_WOR );
+REG64( C_16_NET_CTRL0                                          , RULL(0x300F0040), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_NET_CTRL0_WAND                                     , RULL(0x300F0041), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_16_NET_CTRL0_WOR                                      , RULL(0x300F0042), SH_UNT_C_16     , SH_ACS_SCOM2_WOR );
+REG64( C_17_NET_CTRL0                                          , RULL(0x310F0040), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_NET_CTRL0_WAND                                     , RULL(0x310F0041), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_17_NET_CTRL0_WOR                                      , RULL(0x310F0042), SH_UNT_C_17     , SH_ACS_SCOM2_WOR );
+REG64( C_18_NET_CTRL0                                          , RULL(0x320F0040), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_NET_CTRL0_WAND                                     , RULL(0x320F0041), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_18_NET_CTRL0_WOR                                      , RULL(0x320F0042), SH_UNT_C_18     , SH_ACS_SCOM2_WOR );
+REG64( C_19_NET_CTRL0                                          , RULL(0x330F0040), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_NET_CTRL0_WAND                                     , RULL(0x330F0041), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_19_NET_CTRL0_WOR                                      , RULL(0x330F0042), SH_UNT_C_19     , SH_ACS_SCOM2_WOR );
+REG64( C_20_NET_CTRL0                                          , RULL(0x340F0040), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_NET_CTRL0_WAND                                     , RULL(0x340F0041), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_20_NET_CTRL0_WOR                                      , RULL(0x340F0042), SH_UNT_C_20     , SH_ACS_SCOM2_WOR );
+REG64( C_21_NET_CTRL0                                          , RULL(0x350F0040), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_NET_CTRL0_WAND                                     , RULL(0x350F0041), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_21_NET_CTRL0_WOR                                      , RULL(0x350F0042), SH_UNT_C_21     , SH_ACS_SCOM2_WOR );
+REG64( C_22_NET_CTRL0                                          , RULL(0x360F0040), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_NET_CTRL0_WAND                                     , RULL(0x360F0041), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_22_NET_CTRL0_WOR                                      , RULL(0x360F0042), SH_UNT_C_22     , SH_ACS_SCOM2_WOR );
+REG64( C_23_NET_CTRL0                                          , RULL(0x370F0040), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_NET_CTRL0_WAND                                     , RULL(0x370F0041), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_23_NET_CTRL0_WOR                                      , RULL(0x370F0042), SH_UNT_C_23     , SH_ACS_SCOM2_WOR );
+REG64( EQ_NET_CTRL0                                            , RULL(0x100F0040), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_NET_CTRL0_WAND                                       , RULL(0x100F0041), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_WAND );
+REG64( EQ_NET_CTRL0_WOR                                        , RULL(0x100F0042), SH_UNT_EQ       , SH_ACS_SCOM2_WOR );
+REG64( EQ_0_NET_CTRL0                                          , RULL(0x100F0040), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_0_NET_CTRL0_WAND                                     , RULL(0x100F0041), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1_WAND );
+REG64( EQ_0_NET_CTRL0_WOR                                      , RULL(0x100F0042), SH_UNT_EQ_0     , SH_ACS_SCOM2_WOR );
+REG64( EQ_1_NET_CTRL0                                          , RULL(0x110F0040), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_NET_CTRL0_WAND                                     , RULL(0x110F0041), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1_WAND );
+REG64( EQ_1_NET_CTRL0_WOR                                      , RULL(0x110F0042), SH_UNT_EQ_1     , SH_ACS_SCOM2_WOR );
+REG64( EQ_2_NET_CTRL0                                          , RULL(0x120F0040), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_NET_CTRL0_WAND                                     , RULL(0x120F0041), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1_WAND );
+REG64( EQ_2_NET_CTRL0_WOR                                      , RULL(0x120F0042), SH_UNT_EQ_2     , SH_ACS_SCOM2_WOR );
+REG64( EQ_3_NET_CTRL0                                          , RULL(0x130F0040), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_NET_CTRL0_WAND                                     , RULL(0x130F0041), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1_WAND );
+REG64( EQ_3_NET_CTRL0_WOR                                      , RULL(0x130F0042), SH_UNT_EQ_3     , SH_ACS_SCOM2_WOR );
+REG64( EQ_4_NET_CTRL0                                          , RULL(0x140F0040), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_NET_CTRL0_WAND                                     , RULL(0x140F0041), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1_WAND );
+REG64( EQ_4_NET_CTRL0_WOR                                      , RULL(0x140F0042), SH_UNT_EQ_4     , SH_ACS_SCOM2_WOR );
+REG64( EQ_5_NET_CTRL0                                          , RULL(0x150F0040), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_NET_CTRL0_WAND                                     , RULL(0x150F0041), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1_WAND );
+REG64( EQ_5_NET_CTRL0_WOR                                      , RULL(0x150F0042), SH_UNT_EQ_5     , SH_ACS_SCOM2_WOR );
+REG64( EX_NET_CTRL0                                            , RULL(0x200F0040), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0040,
+REG64( EX_NET_CTRL0_WAND                                       , RULL(0x200F0041), SH_UNT_EX       ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 210F0041,
+REG64( EX_NET_CTRL0_WOR                                        , RULL(0x200F0042), SH_UNT_EX       ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 210F0042,
+REG64( EX_0_NET_CTRL0                                          , RULL(0x200F0040), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0040,
+REG64( EX_0_NET_CTRL0_WAND                                     , RULL(0x200F0041), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 210F0041,
+REG64( EX_0_NET_CTRL0_WOR                                      , RULL(0x200F0042), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 210F0042,
+REG64( EX_1_NET_CTRL0                                          , RULL(0x230F0040), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0040,
+REG64( EX_1_NET_CTRL0_WAND                                     , RULL(0x230F0041), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 220F0041,
+REG64( EX_1_NET_CTRL0_WOR                                      , RULL(0x230F0042), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 220F0042,
+REG64( EX_2_NET_CTRL0                                          , RULL(0x240F0040), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0040,
+REG64( EX_2_NET_CTRL0_WAND                                     , RULL(0x240F0041), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 250F0041,
+REG64( EX_2_NET_CTRL0_WOR                                      , RULL(0x240F0042), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 250F0042,
+REG64( EX_3_NET_CTRL0                                          , RULL(0x260F0040), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0040,
+REG64( EX_3_NET_CTRL0_WAND                                     , RULL(0x260F0041), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 270F0041,
+REG64( EX_3_NET_CTRL0_WOR                                      , RULL(0x260F0042), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 270F0042,
+REG64( EX_4_NET_CTRL0                                          , RULL(0x280F0040), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0040,
+REG64( EX_4_NET_CTRL0_WAND                                     , RULL(0x280F0041), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 290F0041,
+REG64( EX_4_NET_CTRL0_WOR                                      , RULL(0x280F0042), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 290F0042,
+REG64( EX_5_NET_CTRL0                                          , RULL(0x2A0F0040), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0040,
+REG64( EX_5_NET_CTRL0_WAND                                     , RULL(0x2A0F0041), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2B0F0041,
+REG64( EX_5_NET_CTRL0_WOR                                      , RULL(0x2A0F0042), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 2B0F0042,
+REG64( EX_6_NET_CTRL0                                          , RULL(0x2C0F0040), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0040,
+REG64( EX_6_NET_CTRL0_WAND                                     , RULL(0x2C0F0041), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2D0F0041,
+REG64( EX_6_NET_CTRL0_WOR                                      , RULL(0x2C0F0042), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 2D0F0042,
+REG64( EX_7_NET_CTRL0                                          , RULL(0x2E0F0040), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0040,
+REG64( EX_7_NET_CTRL0_WAND                                     , RULL(0x2E0F0041), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2F0F0041,
+REG64( EX_7_NET_CTRL0_WOR                                      , RULL(0x2E0F0042), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 2F0F0042,
+REG64( EX_8_NET_CTRL0                                          , RULL(0x300F0040), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0040,
+REG64( EX_8_NET_CTRL0_WAND                                     , RULL(0x300F0041), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 310F0041,
+REG64( EX_8_NET_CTRL0_WOR                                      , RULL(0x300F0042), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 310F0042,
+REG64( EX_9_NET_CTRL0                                          , RULL(0x320F0040), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0040,
+REG64( EX_9_NET_CTRL0_WAND                                     , RULL(0x320F0041), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 330F0041,
+REG64( EX_9_NET_CTRL0_WOR                                      , RULL(0x320F0042), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 330F0042,
+REG64( EX_10_NET_CTRL0                                         , RULL(0x340F0040), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0040,
+REG64( EX_10_NET_CTRL0_WAND                                    , RULL(0x340F0041), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 350F0041,
+REG64( EX_10_NET_CTRL0_WOR                                     , RULL(0x340F0042), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 350F0042,
+REG64( EX_11_NET_CTRL0                                         , RULL(0x360F0040), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0040,
+REG64( EX_11_NET_CTRL0_WAND                                    , RULL(0x360F0041), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 370F0041,
+REG64( EX_11_NET_CTRL0_WOR                                     , RULL(0x360F0042), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 370F0042,
+
+REG64( C_NET_CTRL1                                             , RULL(0x200F0044), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_NET_CTRL1_WAND                                        , RULL(0x200F0045), SH_UNT_C        ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_NET_CTRL1_WOR                                         , RULL(0x200F0046), SH_UNT_C        , SH_ACS_SCOM2_WOR );
+REG64( C_0_NET_CTRL1                                           , RULL(0x200F0044), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_NET_CTRL1_WAND                                      , RULL(0x200F0045), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_0_NET_CTRL1_WOR                                       , RULL(0x200F0046), SH_UNT_C_0      , SH_ACS_SCOM2_WOR );
+REG64( C_1_NET_CTRL1                                           , RULL(0x210F0044), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_NET_CTRL1_WAND                                      , RULL(0x210F0045), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_1_NET_CTRL1_WOR                                       , RULL(0x210F0046), SH_UNT_C_1      , SH_ACS_SCOM2_WOR );
+REG64( C_2_NET_CTRL1                                           , RULL(0x220F0044), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_NET_CTRL1_WAND                                      , RULL(0x220F0045), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_2_NET_CTRL1_WOR                                       , RULL(0x220F0046), SH_UNT_C_2      , SH_ACS_SCOM2_WOR );
+REG64( C_3_NET_CTRL1                                           , RULL(0x230F0044), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_NET_CTRL1_WAND                                      , RULL(0x230F0045), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_3_NET_CTRL1_WOR                                       , RULL(0x230F0046), SH_UNT_C_3      , SH_ACS_SCOM2_WOR );
+REG64( C_4_NET_CTRL1                                           , RULL(0x240F0044), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_NET_CTRL1_WAND                                      , RULL(0x240F0045), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_4_NET_CTRL1_WOR                                       , RULL(0x240F0046), SH_UNT_C_4      , SH_ACS_SCOM2_WOR );
+REG64( C_5_NET_CTRL1                                           , RULL(0x250F0044), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_NET_CTRL1_WAND                                      , RULL(0x250F0045), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_5_NET_CTRL1_WOR                                       , RULL(0x250F0046), SH_UNT_C_5      , SH_ACS_SCOM2_WOR );
+REG64( C_6_NET_CTRL1                                           , RULL(0x260F0044), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_NET_CTRL1_WAND                                      , RULL(0x260F0045), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_6_NET_CTRL1_WOR                                       , RULL(0x260F0046), SH_UNT_C_6      , SH_ACS_SCOM2_WOR );
+REG64( C_7_NET_CTRL1                                           , RULL(0x270F0044), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_NET_CTRL1_WAND                                      , RULL(0x270F0045), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_7_NET_CTRL1_WOR                                       , RULL(0x270F0046), SH_UNT_C_7      , SH_ACS_SCOM2_WOR );
+REG64( C_8_NET_CTRL1                                           , RULL(0x280F0044), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_NET_CTRL1_WAND                                      , RULL(0x280F0045), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_8_NET_CTRL1_WOR                                       , RULL(0x280F0046), SH_UNT_C_8      , SH_ACS_SCOM2_WOR );
+REG64( C_9_NET_CTRL1                                           , RULL(0x290F0044), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_NET_CTRL1_WAND                                      , RULL(0x290F0045), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_9_NET_CTRL1_WOR                                       , RULL(0x290F0046), SH_UNT_C_9      , SH_ACS_SCOM2_WOR );
+REG64( C_10_NET_CTRL1                                          , RULL(0x2A0F0044), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_NET_CTRL1_WAND                                     , RULL(0x2A0F0045), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_10_NET_CTRL1_WOR                                      , RULL(0x2A0F0046), SH_UNT_C_10     , SH_ACS_SCOM2_WOR );
+REG64( C_11_NET_CTRL1                                          , RULL(0x2B0F0044), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_NET_CTRL1_WAND                                     , RULL(0x2B0F0045), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_11_NET_CTRL1_WOR                                      , RULL(0x2B0F0046), SH_UNT_C_11     , SH_ACS_SCOM2_WOR );
+REG64( C_12_NET_CTRL1                                          , RULL(0x2C0F0044), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_NET_CTRL1_WAND                                     , RULL(0x2C0F0045), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_12_NET_CTRL1_WOR                                      , RULL(0x2C0F0046), SH_UNT_C_12     , SH_ACS_SCOM2_WOR );
+REG64( C_13_NET_CTRL1                                          , RULL(0x2D0F0044), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_NET_CTRL1_WAND                                     , RULL(0x2D0F0045), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_13_NET_CTRL1_WOR                                      , RULL(0x2D0F0046), SH_UNT_C_13     , SH_ACS_SCOM2_WOR );
+REG64( C_14_NET_CTRL1                                          , RULL(0x2E0F0044), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_NET_CTRL1_WAND                                     , RULL(0x2E0F0045), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_14_NET_CTRL1_WOR                                      , RULL(0x2E0F0046), SH_UNT_C_14     , SH_ACS_SCOM2_WOR );
+REG64( C_15_NET_CTRL1                                          , RULL(0x2F0F0044), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_NET_CTRL1_WAND                                     , RULL(0x2F0F0045), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_15_NET_CTRL1_WOR                                      , RULL(0x2F0F0046), SH_UNT_C_15     , SH_ACS_SCOM2_WOR );
+REG64( C_16_NET_CTRL1                                          , RULL(0x300F0044), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_NET_CTRL1_WAND                                     , RULL(0x300F0045), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_16_NET_CTRL1_WOR                                      , RULL(0x300F0046), SH_UNT_C_16     , SH_ACS_SCOM2_WOR );
+REG64( C_17_NET_CTRL1                                          , RULL(0x310F0044), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_NET_CTRL1_WAND                                     , RULL(0x310F0045), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_17_NET_CTRL1_WOR                                      , RULL(0x310F0046), SH_UNT_C_17     , SH_ACS_SCOM2_WOR );
+REG64( C_18_NET_CTRL1                                          , RULL(0x320F0044), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_NET_CTRL1_WAND                                     , RULL(0x320F0045), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_18_NET_CTRL1_WOR                                      , RULL(0x320F0046), SH_UNT_C_18     , SH_ACS_SCOM2_WOR );
+REG64( C_19_NET_CTRL1                                          , RULL(0x330F0044), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_NET_CTRL1_WAND                                     , RULL(0x330F0045), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_19_NET_CTRL1_WOR                                      , RULL(0x330F0046), SH_UNT_C_19     , SH_ACS_SCOM2_WOR );
+REG64( C_20_NET_CTRL1                                          , RULL(0x340F0044), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_NET_CTRL1_WAND                                     , RULL(0x340F0045), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_20_NET_CTRL1_WOR                                      , RULL(0x340F0046), SH_UNT_C_20     , SH_ACS_SCOM2_WOR );
+REG64( C_21_NET_CTRL1                                          , RULL(0x350F0044), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_NET_CTRL1_WAND                                     , RULL(0x350F0045), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_21_NET_CTRL1_WOR                                      , RULL(0x350F0046), SH_UNT_C_21     , SH_ACS_SCOM2_WOR );
+REG64( C_22_NET_CTRL1                                          , RULL(0x360F0044), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_NET_CTRL1_WAND                                     , RULL(0x360F0045), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_22_NET_CTRL1_WOR                                      , RULL(0x360F0046), SH_UNT_C_22     , SH_ACS_SCOM2_WOR );
+REG64( C_23_NET_CTRL1                                          , RULL(0x370F0044), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_NET_CTRL1_WAND                                     , RULL(0x370F0045), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_23_NET_CTRL1_WOR                                      , RULL(0x370F0046), SH_UNT_C_23     , SH_ACS_SCOM2_WOR );
+REG64( EQ_NET_CTRL1                                            , RULL(0x100F0044), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_NET_CTRL1_WAND                                       , RULL(0x100F0045), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_WAND );
+REG64( EQ_NET_CTRL1_WOR                                        , RULL(0x100F0046), SH_UNT_EQ       , SH_ACS_SCOM2_WOR );
+REG64( EQ_0_NET_CTRL1                                          , RULL(0x100F0044), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_0_NET_CTRL1_WAND                                     , RULL(0x100F0045), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1_WAND );
+REG64( EQ_0_NET_CTRL1_WOR                                      , RULL(0x100F0046), SH_UNT_EQ_0     , SH_ACS_SCOM2_WOR );
+REG64( EQ_1_NET_CTRL1                                          , RULL(0x110F0044), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_NET_CTRL1_WAND                                     , RULL(0x110F0045), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1_WAND );
+REG64( EQ_1_NET_CTRL1_WOR                                      , RULL(0x110F0046), SH_UNT_EQ_1     , SH_ACS_SCOM2_WOR );
+REG64( EQ_2_NET_CTRL1                                          , RULL(0x120F0044), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_NET_CTRL1_WAND                                     , RULL(0x120F0045), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1_WAND );
+REG64( EQ_2_NET_CTRL1_WOR                                      , RULL(0x120F0046), SH_UNT_EQ_2     , SH_ACS_SCOM2_WOR );
+REG64( EQ_3_NET_CTRL1                                          , RULL(0x130F0044), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_NET_CTRL1_WAND                                     , RULL(0x130F0045), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1_WAND );
+REG64( EQ_3_NET_CTRL1_WOR                                      , RULL(0x130F0046), SH_UNT_EQ_3     , SH_ACS_SCOM2_WOR );
+REG64( EQ_4_NET_CTRL1                                          , RULL(0x140F0044), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_NET_CTRL1_WAND                                     , RULL(0x140F0045), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1_WAND );
+REG64( EQ_4_NET_CTRL1_WOR                                      , RULL(0x140F0046), SH_UNT_EQ_4     , SH_ACS_SCOM2_WOR );
+REG64( EQ_5_NET_CTRL1                                          , RULL(0x150F0044), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_NET_CTRL1_WAND                                     , RULL(0x150F0045), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1_WAND );
+REG64( EQ_5_NET_CTRL1_WOR                                      , RULL(0x150F0046), SH_UNT_EQ_5     , SH_ACS_SCOM2_WOR );
+REG64( EX_NET_CTRL1                                            , RULL(0x200F0044), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0044,
+REG64( EX_NET_CTRL1_WAND                                       , RULL(0x200F0045), SH_UNT_EX       ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 210F0045,
+REG64( EX_NET_CTRL1_WOR                                        , RULL(0x200F0046), SH_UNT_EX       ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 210F0046,
+REG64( EX_0_NET_CTRL1                                          , RULL(0x200F0044), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0044,
+REG64( EX_0_NET_CTRL1_WAND                                     , RULL(0x200F0045), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 210F0045,
+REG64( EX_0_NET_CTRL1_WOR                                      , RULL(0x200F0046), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 210F0046,
+REG64( EX_1_NET_CTRL1                                          , RULL(0x230F0044), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0044,
+REG64( EX_1_NET_CTRL1_WAND                                     , RULL(0x230F0045), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 220F0045,
+REG64( EX_1_NET_CTRL1_WOR                                      , RULL(0x230F0046), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 220F0046,
+REG64( EX_2_NET_CTRL1                                          , RULL(0x240F0044), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0044,
+REG64( EX_2_NET_CTRL1_WAND                                     , RULL(0x240F0045), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 250F0045,
+REG64( EX_2_NET_CTRL1_WOR                                      , RULL(0x240F0046), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 250F0046,
+REG64( EX_3_NET_CTRL1                                          , RULL(0x260F0044), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0044,
+REG64( EX_3_NET_CTRL1_WAND                                     , RULL(0x260F0045), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 270F0045,
+REG64( EX_3_NET_CTRL1_WOR                                      , RULL(0x260F0046), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 270F0046,
+REG64( EX_4_NET_CTRL1                                          , RULL(0x280F0044), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0044,
+REG64( EX_4_NET_CTRL1_WAND                                     , RULL(0x280F0045), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 290F0045,
+REG64( EX_4_NET_CTRL1_WOR                                      , RULL(0x280F0046), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 290F0046,
+REG64( EX_5_NET_CTRL1                                          , RULL(0x2A0F0044), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0044,
+REG64( EX_5_NET_CTRL1_WAND                                     , RULL(0x2A0F0045), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2B0F0045,
+REG64( EX_5_NET_CTRL1_WOR                                      , RULL(0x2A0F0046), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 2B0F0046,
+REG64( EX_6_NET_CTRL1                                          , RULL(0x2C0F0044), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0044,
+REG64( EX_6_NET_CTRL1_WAND                                     , RULL(0x2C0F0045), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2D0F0045,
+REG64( EX_6_NET_CTRL1_WOR                                      , RULL(0x2C0F0046), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 2D0F0046,
+REG64( EX_7_NET_CTRL1                                          , RULL(0x2E0F0044), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0044,
+REG64( EX_7_NET_CTRL1_WAND                                     , RULL(0x2E0F0045), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2F0F0045,
+REG64( EX_7_NET_CTRL1_WOR                                      , RULL(0x2E0F0046), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 2F0F0046,
+REG64( EX_8_NET_CTRL1                                          , RULL(0x300F0044), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0044,
+REG64( EX_8_NET_CTRL1_WAND                                     , RULL(0x300F0045), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 310F0045,
+REG64( EX_8_NET_CTRL1_WOR                                      , RULL(0x300F0046), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 310F0046,
+REG64( EX_9_NET_CTRL1                                          , RULL(0x320F0044), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0044,
+REG64( EX_9_NET_CTRL1_WAND                                     , RULL(0x320F0045), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 330F0045,
+REG64( EX_9_NET_CTRL1_WOR                                      , RULL(0x320F0046), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 330F0046,
+REG64( EX_10_NET_CTRL1                                         , RULL(0x340F0044), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0044,
+REG64( EX_10_NET_CTRL1_WAND                                    , RULL(0x340F0045), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 350F0045,
+REG64( EX_10_NET_CTRL1_WOR                                     , RULL(0x340F0046), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 350F0046,
+REG64( EX_11_NET_CTRL1                                         , RULL(0x360F0044), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0044,
+REG64( EX_11_NET_CTRL1_WAND                                    , RULL(0x360F0045), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 370F0045,
+REG64( EX_11_NET_CTRL1_WOR                                     , RULL(0x360F0046), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_WOR ); //DUPS: 370F0046,
+
+REG64( C_OCC_SCOMC                                             , RULL(0x20010A82), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_OCC_SCOMC                                           , RULL(0x20010A82), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_OCC_SCOMC                                           , RULL(0x21010A82), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_OCC_SCOMC                                           , RULL(0x22010A82), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_OCC_SCOMC                                           , RULL(0x23010A82), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_OCC_SCOMC                                           , RULL(0x24010A82), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_OCC_SCOMC                                           , RULL(0x25010A82), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_OCC_SCOMC                                           , RULL(0x26010A82), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_OCC_SCOMC                                           , RULL(0x27010A82), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_OCC_SCOMC                                           , RULL(0x28010A82), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_OCC_SCOMC                                           , RULL(0x29010A82), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_OCC_SCOMC                                          , RULL(0x2A010A82), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_OCC_SCOMC                                          , RULL(0x2B010A82), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_OCC_SCOMC                                          , RULL(0x2C010A82), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_OCC_SCOMC                                          , RULL(0x2D010A82), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_OCC_SCOMC                                          , RULL(0x2E010A82), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_OCC_SCOMC                                          , RULL(0x2F010A82), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_OCC_SCOMC                                          , RULL(0x30010A82), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_OCC_SCOMC                                          , RULL(0x31010A82), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_OCC_SCOMC                                          , RULL(0x32010A82), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_OCC_SCOMC                                          , RULL(0x33010A82), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_OCC_SCOMC                                          , RULL(0x34010A82), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_OCC_SCOMC                                          , RULL(0x35010A82), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_OCC_SCOMC                                          , RULL(0x36010A82), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_OCC_SCOMC                                          , RULL(0x37010A82), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_OCC_SCOMC                                       , RULL(0x21010A82), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A82,
+REG64( EX_10_L2_OCC_SCOMC                                      , RULL(0x35010A82), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 34010A82,
+REG64( EX_11_L2_OCC_SCOMC                                      , RULL(0x37010A82), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 36010A82,
+REG64( EX_1_L2_OCC_SCOMC                                       , RULL(0x23010A82), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 22010A82,
+REG64( EX_2_L2_OCC_SCOMC                                       , RULL(0x25010A82), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 24010A82,
+REG64( EX_3_L2_OCC_SCOMC                                       , RULL(0x27010A82), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 26010A82,
+REG64( EX_4_L2_OCC_SCOMC                                       , RULL(0x29010A82), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 28010A82,
+REG64( EX_5_L2_OCC_SCOMC                                       , RULL(0x2B010A82), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2A010A82,
+REG64( EX_6_L2_OCC_SCOMC                                       , RULL(0x2D010A82), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2C010A82,
+REG64( EX_7_L2_OCC_SCOMC                                       , RULL(0x2F010A82), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2E010A82,
+REG64( EX_8_L2_OCC_SCOMC                                       , RULL(0x31010A82), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 30010A82,
+REG64( EX_9_L2_OCC_SCOMC                                       , RULL(0x33010A82), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 32010A82,
+REG64( EX_L2_OCC_SCOMC                                         , RULL(0x21010A82), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A82,
+
+REG64( C_OPCG_ALIGN                                            , RULL(0x20030001), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_OPCG_ALIGN                                          , RULL(0x20030001), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_OPCG_ALIGN                                          , RULL(0x21030001), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_OPCG_ALIGN                                          , RULL(0x22030001), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_OPCG_ALIGN                                          , RULL(0x23030001), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_OPCG_ALIGN                                          , RULL(0x24030001), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_OPCG_ALIGN                                          , RULL(0x25030001), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_OPCG_ALIGN                                          , RULL(0x26030001), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_OPCG_ALIGN                                          , RULL(0x27030001), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_OPCG_ALIGN                                          , RULL(0x28030001), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_OPCG_ALIGN                                          , RULL(0x29030001), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_OPCG_ALIGN                                         , RULL(0x2A030001), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_OPCG_ALIGN                                         , RULL(0x2B030001), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_OPCG_ALIGN                                         , RULL(0x2C030001), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_OPCG_ALIGN                                         , RULL(0x2D030001), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_OPCG_ALIGN                                         , RULL(0x2E030001), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_OPCG_ALIGN                                         , RULL(0x2F030001), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_OPCG_ALIGN                                         , RULL(0x30030001), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_OPCG_ALIGN                                         , RULL(0x31030001), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_OPCG_ALIGN                                         , RULL(0x32030001), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_OPCG_ALIGN                                         , RULL(0x33030001), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_OPCG_ALIGN                                         , RULL(0x34030001), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_OPCG_ALIGN                                         , RULL(0x35030001), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_OPCG_ALIGN                                         , RULL(0x36030001), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_OPCG_ALIGN                                         , RULL(0x37030001), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_OPCG_ALIGN                                           , RULL(0x10030001), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_OPCG_ALIGN                                         , RULL(0x10030001), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_OPCG_ALIGN                                         , RULL(0x11030001), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_OPCG_ALIGN                                         , RULL(0x12030001), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_OPCG_ALIGN                                         , RULL(0x13030001), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_OPCG_ALIGN                                         , RULL(0x14030001), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_OPCG_ALIGN                                         , RULL(0x15030001), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_OPCG_ALIGN                                           , RULL(0x20030001), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21030001,
+REG64( EX_0_OPCG_ALIGN                                         , RULL(0x20030001), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21030001,
+REG64( EX_1_OPCG_ALIGN                                         , RULL(0x22030001), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23030001,
+REG64( EX_2_OPCG_ALIGN                                         , RULL(0x24030001), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25030001,
+REG64( EX_3_OPCG_ALIGN                                         , RULL(0x26030001), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27030001,
+REG64( EX_4_OPCG_ALIGN                                         , RULL(0x28030001), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29030001,
+REG64( EX_5_OPCG_ALIGN                                         , RULL(0x2A030001), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B030001,
+REG64( EX_6_OPCG_ALIGN                                         , RULL(0x2C030001), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D030001,
+REG64( EX_7_OPCG_ALIGN                                         , RULL(0x2E030001), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F030001,
+REG64( EX_8_OPCG_ALIGN                                         , RULL(0x30030001), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31030001,
+REG64( EX_9_OPCG_ALIGN                                         , RULL(0x32030001), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33030001,
+REG64( EX_10_OPCG_ALIGN                                        , RULL(0x34030001), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35030001,
+REG64( EX_11_OPCG_ALIGN                                        , RULL(0x36030001), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37030001,
+
+REG64( C_OPCG_CAPT1                                            , RULL(0x20030010), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_OPCG_CAPT1                                          , RULL(0x20030010), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_OPCG_CAPT1                                          , RULL(0x21030010), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_OPCG_CAPT1                                          , RULL(0x22030010), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_OPCG_CAPT1                                          , RULL(0x23030010), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_OPCG_CAPT1                                          , RULL(0x24030010), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_OPCG_CAPT1                                          , RULL(0x25030010), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_OPCG_CAPT1                                          , RULL(0x26030010), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_OPCG_CAPT1                                          , RULL(0x27030010), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_OPCG_CAPT1                                          , RULL(0x28030010), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_OPCG_CAPT1                                          , RULL(0x29030010), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_OPCG_CAPT1                                         , RULL(0x2A030010), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_OPCG_CAPT1                                         , RULL(0x2B030010), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_OPCG_CAPT1                                         , RULL(0x2C030010), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_OPCG_CAPT1                                         , RULL(0x2D030010), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_OPCG_CAPT1                                         , RULL(0x2E030010), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_OPCG_CAPT1                                         , RULL(0x2F030010), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_OPCG_CAPT1                                         , RULL(0x30030010), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_OPCG_CAPT1                                         , RULL(0x31030010), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_OPCG_CAPT1                                         , RULL(0x32030010), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_OPCG_CAPT1                                         , RULL(0x33030010), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_OPCG_CAPT1                                         , RULL(0x34030010), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_OPCG_CAPT1                                         , RULL(0x35030010), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_OPCG_CAPT1                                         , RULL(0x36030010), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_OPCG_CAPT1                                         , RULL(0x37030010), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_OPCG_CAPT1                                           , RULL(0x10030010), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_OPCG_CAPT1                                         , RULL(0x10030010), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_OPCG_CAPT1                                         , RULL(0x11030010), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_OPCG_CAPT1                                         , RULL(0x12030010), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_OPCG_CAPT1                                         , RULL(0x13030010), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_OPCG_CAPT1                                         , RULL(0x14030010), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_OPCG_CAPT1                                         , RULL(0x15030010), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_OPCG_CAPT1                                           , RULL(0x20030010), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21030010,
+REG64( EX_0_OPCG_CAPT1                                         , RULL(0x20030010), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21030010,
+REG64( EX_1_OPCG_CAPT1                                         , RULL(0x22030010), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23030010,
+REG64( EX_2_OPCG_CAPT1                                         , RULL(0x24030010), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25030010,
+REG64( EX_3_OPCG_CAPT1                                         , RULL(0x26030010), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27030010,
+REG64( EX_4_OPCG_CAPT1                                         , RULL(0x28030010), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29030010,
+REG64( EX_5_OPCG_CAPT1                                         , RULL(0x2A030010), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B030010,
+REG64( EX_6_OPCG_CAPT1                                         , RULL(0x2C030010), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D030010,
+REG64( EX_7_OPCG_CAPT1                                         , RULL(0x2E030010), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F030010,
+REG64( EX_8_OPCG_CAPT1                                         , RULL(0x30030010), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31030010,
+REG64( EX_9_OPCG_CAPT1                                         , RULL(0x32030010), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33030010,
+REG64( EX_10_OPCG_CAPT1                                        , RULL(0x34030010), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35030010,
+REG64( EX_11_OPCG_CAPT1                                        , RULL(0x36030010), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37030010,
+
+REG64( C_OPCG_CAPT2                                            , RULL(0x20030011), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_OPCG_CAPT2                                          , RULL(0x20030011), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_OPCG_CAPT2                                          , RULL(0x21030011), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_OPCG_CAPT2                                          , RULL(0x22030011), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_OPCG_CAPT2                                          , RULL(0x23030011), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_OPCG_CAPT2                                          , RULL(0x24030011), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_OPCG_CAPT2                                          , RULL(0x25030011), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_OPCG_CAPT2                                          , RULL(0x26030011), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_OPCG_CAPT2                                          , RULL(0x27030011), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_OPCG_CAPT2                                          , RULL(0x28030011), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_OPCG_CAPT2                                          , RULL(0x29030011), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_OPCG_CAPT2                                         , RULL(0x2A030011), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_OPCG_CAPT2                                         , RULL(0x2B030011), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_OPCG_CAPT2                                         , RULL(0x2C030011), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_OPCG_CAPT2                                         , RULL(0x2D030011), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_OPCG_CAPT2                                         , RULL(0x2E030011), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_OPCG_CAPT2                                         , RULL(0x2F030011), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_OPCG_CAPT2                                         , RULL(0x30030011), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_OPCG_CAPT2                                         , RULL(0x31030011), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_OPCG_CAPT2                                         , RULL(0x32030011), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_OPCG_CAPT2                                         , RULL(0x33030011), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_OPCG_CAPT2                                         , RULL(0x34030011), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_OPCG_CAPT2                                         , RULL(0x35030011), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_OPCG_CAPT2                                         , RULL(0x36030011), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_OPCG_CAPT2                                         , RULL(0x37030011), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_OPCG_CAPT2                                           , RULL(0x10030011), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_OPCG_CAPT2                                         , RULL(0x10030011), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_OPCG_CAPT2                                         , RULL(0x11030011), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_OPCG_CAPT2                                         , RULL(0x12030011), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_OPCG_CAPT2                                         , RULL(0x13030011), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_OPCG_CAPT2                                         , RULL(0x14030011), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_OPCG_CAPT2                                         , RULL(0x15030011), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_OPCG_CAPT2                                           , RULL(0x20030011), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21030011,
+REG64( EX_0_OPCG_CAPT2                                         , RULL(0x20030011), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21030011,
+REG64( EX_1_OPCG_CAPT2                                         , RULL(0x22030011), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23030011,
+REG64( EX_2_OPCG_CAPT2                                         , RULL(0x24030011), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25030011,
+REG64( EX_3_OPCG_CAPT2                                         , RULL(0x26030011), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27030011,
+REG64( EX_4_OPCG_CAPT2                                         , RULL(0x28030011), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29030011,
+REG64( EX_5_OPCG_CAPT2                                         , RULL(0x2A030011), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B030011,
+REG64( EX_6_OPCG_CAPT2                                         , RULL(0x2C030011), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D030011,
+REG64( EX_7_OPCG_CAPT2                                         , RULL(0x2E030011), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F030011,
+REG64( EX_8_OPCG_CAPT2                                         , RULL(0x30030011), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31030011,
+REG64( EX_9_OPCG_CAPT2                                         , RULL(0x32030011), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33030011,
+REG64( EX_10_OPCG_CAPT2                                        , RULL(0x34030011), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35030011,
+REG64( EX_11_OPCG_CAPT2                                        , RULL(0x36030011), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37030011,
+
+REG64( C_OPCG_CAPT3                                            , RULL(0x20030012), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_OPCG_CAPT3                                          , RULL(0x20030012), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_OPCG_CAPT3                                          , RULL(0x21030012), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_OPCG_CAPT3                                          , RULL(0x22030012), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_OPCG_CAPT3                                          , RULL(0x23030012), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_OPCG_CAPT3                                          , RULL(0x24030012), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_OPCG_CAPT3                                          , RULL(0x25030012), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_OPCG_CAPT3                                          , RULL(0x26030012), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_OPCG_CAPT3                                          , RULL(0x27030012), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_OPCG_CAPT3                                          , RULL(0x28030012), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_OPCG_CAPT3                                          , RULL(0x29030012), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_OPCG_CAPT3                                         , RULL(0x2A030012), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_OPCG_CAPT3                                         , RULL(0x2B030012), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_OPCG_CAPT3                                         , RULL(0x2C030012), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_OPCG_CAPT3                                         , RULL(0x2D030012), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_OPCG_CAPT3                                         , RULL(0x2E030012), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_OPCG_CAPT3                                         , RULL(0x2F030012), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_OPCG_CAPT3                                         , RULL(0x30030012), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_OPCG_CAPT3                                         , RULL(0x31030012), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_OPCG_CAPT3                                         , RULL(0x32030012), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_OPCG_CAPT3                                         , RULL(0x33030012), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_OPCG_CAPT3                                         , RULL(0x34030012), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_OPCG_CAPT3                                         , RULL(0x35030012), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_OPCG_CAPT3                                         , RULL(0x36030012), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_OPCG_CAPT3                                         , RULL(0x37030012), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_OPCG_CAPT3                                           , RULL(0x10030012), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_OPCG_CAPT3                                         , RULL(0x10030012), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_OPCG_CAPT3                                         , RULL(0x11030012), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_OPCG_CAPT3                                         , RULL(0x12030012), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_OPCG_CAPT3                                         , RULL(0x13030012), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_OPCG_CAPT3                                         , RULL(0x14030012), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_OPCG_CAPT3                                         , RULL(0x15030012), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_OPCG_CAPT3                                           , RULL(0x20030012), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21030012,
+REG64( EX_0_OPCG_CAPT3                                         , RULL(0x20030012), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21030012,
+REG64( EX_1_OPCG_CAPT3                                         , RULL(0x22030012), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23030012,
+REG64( EX_2_OPCG_CAPT3                                         , RULL(0x24030012), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25030012,
+REG64( EX_3_OPCG_CAPT3                                         , RULL(0x26030012), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27030012,
+REG64( EX_4_OPCG_CAPT3                                         , RULL(0x28030012), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29030012,
+REG64( EX_5_OPCG_CAPT3                                         , RULL(0x2A030012), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B030012,
+REG64( EX_6_OPCG_CAPT3                                         , RULL(0x2C030012), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D030012,
+REG64( EX_7_OPCG_CAPT3                                         , RULL(0x2E030012), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F030012,
+REG64( EX_8_OPCG_CAPT3                                         , RULL(0x30030012), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31030012,
+REG64( EX_9_OPCG_CAPT3                                         , RULL(0x32030012), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33030012,
+REG64( EX_10_OPCG_CAPT3                                        , RULL(0x34030012), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35030012,
+REG64( EX_11_OPCG_CAPT3                                        , RULL(0x36030012), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37030012,
+
+REG64( C_OPCG_REG0                                             , RULL(0x20030002), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_OPCG_REG0                                           , RULL(0x20030002), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_OPCG_REG0                                           , RULL(0x21030002), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_OPCG_REG0                                           , RULL(0x22030002), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_OPCG_REG0                                           , RULL(0x23030002), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_OPCG_REG0                                           , RULL(0x24030002), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_OPCG_REG0                                           , RULL(0x25030002), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_OPCG_REG0                                           , RULL(0x26030002), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_OPCG_REG0                                           , RULL(0x27030002), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_OPCG_REG0                                           , RULL(0x28030002), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_OPCG_REG0                                           , RULL(0x29030002), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_OPCG_REG0                                          , RULL(0x2A030002), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_OPCG_REG0                                          , RULL(0x2B030002), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_OPCG_REG0                                          , RULL(0x2C030002), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_OPCG_REG0                                          , RULL(0x2D030002), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_OPCG_REG0                                          , RULL(0x2E030002), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_OPCG_REG0                                          , RULL(0x2F030002), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_OPCG_REG0                                          , RULL(0x30030002), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_OPCG_REG0                                          , RULL(0x31030002), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_OPCG_REG0                                          , RULL(0x32030002), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_OPCG_REG0                                          , RULL(0x33030002), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_OPCG_REG0                                          , RULL(0x34030002), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_OPCG_REG0                                          , RULL(0x35030002), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_OPCG_REG0                                          , RULL(0x36030002), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_OPCG_REG0                                          , RULL(0x37030002), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_OPCG_REG0                                            , RULL(0x10030002), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_OPCG_REG0                                          , RULL(0x10030002), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_OPCG_REG0                                          , RULL(0x11030002), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_OPCG_REG0                                          , RULL(0x12030002), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_OPCG_REG0                                          , RULL(0x13030002), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_OPCG_REG0                                          , RULL(0x14030002), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_OPCG_REG0                                          , RULL(0x15030002), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_OPCG_REG0                                            , RULL(0x20030002), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21030002,
+REG64( EX_0_OPCG_REG0                                          , RULL(0x20030002), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21030002,
+REG64( EX_1_OPCG_REG0                                          , RULL(0x22030002), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23030002,
+REG64( EX_2_OPCG_REG0                                          , RULL(0x24030002), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25030002,
+REG64( EX_3_OPCG_REG0                                          , RULL(0x26030002), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27030002,
+REG64( EX_4_OPCG_REG0                                          , RULL(0x28030002), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29030002,
+REG64( EX_5_OPCG_REG0                                          , RULL(0x2A030002), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B030002,
+REG64( EX_6_OPCG_REG0                                          , RULL(0x2C030002), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D030002,
+REG64( EX_7_OPCG_REG0                                          , RULL(0x2E030002), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F030002,
+REG64( EX_8_OPCG_REG0                                          , RULL(0x30030002), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31030002,
+REG64( EX_9_OPCG_REG0                                          , RULL(0x32030002), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33030002,
+REG64( EX_10_OPCG_REG0                                         , RULL(0x34030002), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35030002,
+REG64( EX_11_OPCG_REG0                                         , RULL(0x36030002), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37030002,
+
+REG64( C_OPCG_REG1                                             , RULL(0x20030003), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_OPCG_REG1                                           , RULL(0x20030003), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_OPCG_REG1                                           , RULL(0x21030003), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_OPCG_REG1                                           , RULL(0x22030003), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_OPCG_REG1                                           , RULL(0x23030003), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_OPCG_REG1                                           , RULL(0x24030003), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_OPCG_REG1                                           , RULL(0x25030003), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_OPCG_REG1                                           , RULL(0x26030003), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_OPCG_REG1                                           , RULL(0x27030003), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_OPCG_REG1                                           , RULL(0x28030003), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_OPCG_REG1                                           , RULL(0x29030003), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_OPCG_REG1                                          , RULL(0x2A030003), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_OPCG_REG1                                          , RULL(0x2B030003), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_OPCG_REG1                                          , RULL(0x2C030003), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_OPCG_REG1                                          , RULL(0x2D030003), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_OPCG_REG1                                          , RULL(0x2E030003), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_OPCG_REG1                                          , RULL(0x2F030003), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_OPCG_REG1                                          , RULL(0x30030003), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_OPCG_REG1                                          , RULL(0x31030003), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_OPCG_REG1                                          , RULL(0x32030003), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_OPCG_REG1                                          , RULL(0x33030003), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_OPCG_REG1                                          , RULL(0x34030003), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_OPCG_REG1                                          , RULL(0x35030003), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_OPCG_REG1                                          , RULL(0x36030003), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_OPCG_REG1                                          , RULL(0x37030003), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_OPCG_REG1                                            , RULL(0x10030003), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_OPCG_REG1                                          , RULL(0x10030003), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_OPCG_REG1                                          , RULL(0x11030003), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_OPCG_REG1                                          , RULL(0x12030003), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_OPCG_REG1                                          , RULL(0x13030003), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_OPCG_REG1                                          , RULL(0x14030003), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_OPCG_REG1                                          , RULL(0x15030003), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_OPCG_REG1                                            , RULL(0x20030003), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21030003,
+REG64( EX_0_OPCG_REG1                                          , RULL(0x20030003), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21030003,
+REG64( EX_1_OPCG_REG1                                          , RULL(0x22030003), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23030003,
+REG64( EX_2_OPCG_REG1                                          , RULL(0x24030003), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25030003,
+REG64( EX_3_OPCG_REG1                                          , RULL(0x26030003), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27030003,
+REG64( EX_4_OPCG_REG1                                          , RULL(0x28030003), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29030003,
+REG64( EX_5_OPCG_REG1                                          , RULL(0x2A030003), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B030003,
+REG64( EX_6_OPCG_REG1                                          , RULL(0x2C030003), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D030003,
+REG64( EX_7_OPCG_REG1                                          , RULL(0x2E030003), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F030003,
+REG64( EX_8_OPCG_REG1                                          , RULL(0x30030003), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31030003,
+REG64( EX_9_OPCG_REG1                                          , RULL(0x32030003), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33030003,
+REG64( EX_10_OPCG_REG1                                         , RULL(0x34030003), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35030003,
+REG64( EX_11_OPCG_REG1                                         , RULL(0x36030003), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37030003,
+
+REG64( C_OPCG_REG2                                             , RULL(0x20030004), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_OPCG_REG2                                           , RULL(0x20030004), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_OPCG_REG2                                           , RULL(0x21030004), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_OPCG_REG2                                           , RULL(0x22030004), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_OPCG_REG2                                           , RULL(0x23030004), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_OPCG_REG2                                           , RULL(0x24030004), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_OPCG_REG2                                           , RULL(0x25030004), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_OPCG_REG2                                           , RULL(0x26030004), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_OPCG_REG2                                           , RULL(0x27030004), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_OPCG_REG2                                           , RULL(0x28030004), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_OPCG_REG2                                           , RULL(0x29030004), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_OPCG_REG2                                          , RULL(0x2A030004), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_OPCG_REG2                                          , RULL(0x2B030004), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_OPCG_REG2                                          , RULL(0x2C030004), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_OPCG_REG2                                          , RULL(0x2D030004), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_OPCG_REG2                                          , RULL(0x2E030004), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_OPCG_REG2                                          , RULL(0x2F030004), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_OPCG_REG2                                          , RULL(0x30030004), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_OPCG_REG2                                          , RULL(0x31030004), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_OPCG_REG2                                          , RULL(0x32030004), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_OPCG_REG2                                          , RULL(0x33030004), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_OPCG_REG2                                          , RULL(0x34030004), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_OPCG_REG2                                          , RULL(0x35030004), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_OPCG_REG2                                          , RULL(0x36030004), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_OPCG_REG2                                          , RULL(0x37030004), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_OPCG_REG2                                            , RULL(0x10030004), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_OPCG_REG2                                          , RULL(0x10030004), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_OPCG_REG2                                          , RULL(0x11030004), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_OPCG_REG2                                          , RULL(0x12030004), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_OPCG_REG2                                          , RULL(0x13030004), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_OPCG_REG2                                          , RULL(0x14030004), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_OPCG_REG2                                          , RULL(0x15030004), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_OPCG_REG2                                            , RULL(0x20030004), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21030004,
+REG64( EX_0_OPCG_REG2                                          , RULL(0x20030004), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21030004,
+REG64( EX_1_OPCG_REG2                                          , RULL(0x22030004), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23030004,
+REG64( EX_2_OPCG_REG2                                          , RULL(0x24030004), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25030004,
+REG64( EX_3_OPCG_REG2                                          , RULL(0x26030004), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27030004,
+REG64( EX_4_OPCG_REG2                                          , RULL(0x28030004), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29030004,
+REG64( EX_5_OPCG_REG2                                          , RULL(0x2A030004), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B030004,
+REG64( EX_6_OPCG_REG2                                          , RULL(0x2C030004), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D030004,
+REG64( EX_7_OPCG_REG2                                          , RULL(0x2E030004), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F030004,
+REG64( EX_8_OPCG_REG2                                          , RULL(0x30030004), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31030004,
+REG64( EX_9_OPCG_REG2                                          , RULL(0x32030004), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33030004,
+REG64( EX_10_OPCG_REG2                                         , RULL(0x34030004), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35030004,
+REG64( EX_11_OPCG_REG2                                         , RULL(0x36030004), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37030004,
+
+REG64( EQ_PHYP_PURGE_CMD_REG                                   , RULL(0x1001080F), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10010C0F,
+REG64( EQ_0_PHYP_PURGE_CMD_REG                                 , RULL(0x1001080F), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10010C0F,
+REG64( EQ_1_PHYP_PURGE_CMD_REG                                 , RULL(0x1101080F), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11010C0F,
+REG64( EQ_2_PHYP_PURGE_CMD_REG                                 , RULL(0x1201080F), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12010C0F,
+REG64( EQ_3_PHYP_PURGE_CMD_REG                                 , RULL(0x1301080F), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13010C0F,
+REG64( EQ_4_PHYP_PURGE_CMD_REG                                 , RULL(0x1401080F), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14010C0F,
+REG64( EQ_5_PHYP_PURGE_CMD_REG                                 , RULL(0x1501080F), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15010C0F,
+REG64( EX_PHYP_PURGE_CMD_REG                                   , RULL(0x1001080F), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_PHYP_PURGE_CMD_REG                                 , RULL(0x1001080F), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_PHYP_PURGE_CMD_REG                                 , RULL(0x10010C0F), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_PHYP_PURGE_CMD_REG                                 , RULL(0x1101080F), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_PHYP_PURGE_CMD_REG                                 , RULL(0x11010C0F), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_PHYP_PURGE_CMD_REG                                 , RULL(0x1201080F), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_PHYP_PURGE_CMD_REG                                 , RULL(0x12010C0F), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_PHYP_PURGE_CMD_REG                                 , RULL(0x1301080F), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_PHYP_PURGE_CMD_REG                                 , RULL(0x13010C0F), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_PHYP_PURGE_CMD_REG                                 , RULL(0x1401080F), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_PHYP_PURGE_CMD_REG                                 , RULL(0x14010C0F), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_PHYP_PURGE_CMD_REG                                , RULL(0x1501080F), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_PHYP_PURGE_CMD_REG                                , RULL(0x15010C0F), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_PHYP_PURGE_REG                                       , RULL(0x10011814), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C14,
+REG64( EQ_0_PHYP_PURGE_REG                                     , RULL(0x10011814), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C14,
+REG64( EQ_1_PHYP_PURGE_REG                                     , RULL(0x11011814), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C14,
+REG64( EQ_2_PHYP_PURGE_REG                                     , RULL(0x12011814), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C14,
+REG64( EQ_3_PHYP_PURGE_REG                                     , RULL(0x13011814), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C14,
+REG64( EQ_4_PHYP_PURGE_REG                                     , RULL(0x14011814), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C14,
+REG64( EQ_5_PHYP_PURGE_REG                                     , RULL(0x15011814), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C14,
+REG64( EX_0_L3_PHYP_PURGE_REG                                  , RULL(0x10011814), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_L3_PHYP_PURGE_REG                                 , RULL(0x15011814), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L3_PHYP_PURGE_REG                                 , RULL(0x15011C14), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L3_PHYP_PURGE_REG                                  , RULL(0x10011C14), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L3_PHYP_PURGE_REG                                  , RULL(0x11011814), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L3_PHYP_PURGE_REG                                  , RULL(0x11011C14), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L3_PHYP_PURGE_REG                                  , RULL(0x12011814), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L3_PHYP_PURGE_REG                                  , RULL(0x12011C14), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L3_PHYP_PURGE_REG                                  , RULL(0x13011814), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L3_PHYP_PURGE_REG                                  , RULL(0x13011C14), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L3_PHYP_PURGE_REG                                  , RULL(0x14011814), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L3_PHYP_PURGE_REG                                  , RULL(0x14011C14), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L3_PHYP_PURGE_REG                                    , RULL(0x10011814), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( C_PLL_LOCK_REG                                          , RULL(0x200F0019), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_PLL_LOCK_REG                                        , RULL(0x200F0019), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_PLL_LOCK_REG                                        , RULL(0x210F0019), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_PLL_LOCK_REG                                        , RULL(0x220F0019), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_PLL_LOCK_REG                                        , RULL(0x230F0019), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_PLL_LOCK_REG                                        , RULL(0x240F0019), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_PLL_LOCK_REG                                        , RULL(0x250F0019), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_PLL_LOCK_REG                                        , RULL(0x260F0019), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_PLL_LOCK_REG                                        , RULL(0x270F0019), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_PLL_LOCK_REG                                        , RULL(0x280F0019), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_PLL_LOCK_REG                                        , RULL(0x290F0019), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_PLL_LOCK_REG                                       , RULL(0x2A0F0019), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_PLL_LOCK_REG                                       , RULL(0x2B0F0019), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_PLL_LOCK_REG                                       , RULL(0x2C0F0019), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_PLL_LOCK_REG                                       , RULL(0x2D0F0019), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_PLL_LOCK_REG                                       , RULL(0x2E0F0019), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_PLL_LOCK_REG                                       , RULL(0x2F0F0019), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_PLL_LOCK_REG                                       , RULL(0x300F0019), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_PLL_LOCK_REG                                       , RULL(0x310F0019), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_PLL_LOCK_REG                                       , RULL(0x320F0019), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_PLL_LOCK_REG                                       , RULL(0x330F0019), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_PLL_LOCK_REG                                       , RULL(0x340F0019), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_PLL_LOCK_REG                                       , RULL(0x350F0019), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_PLL_LOCK_REG                                       , RULL(0x360F0019), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_PLL_LOCK_REG                                       , RULL(0x370F0019), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_PLL_LOCK_REG                                         , RULL(0x100F0019), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_PLL_LOCK_REG                                       , RULL(0x100F0019), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_PLL_LOCK_REG                                       , RULL(0x110F0019), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_PLL_LOCK_REG                                       , RULL(0x120F0019), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_PLL_LOCK_REG                                       , RULL(0x130F0019), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_PLL_LOCK_REG                                       , RULL(0x140F0019), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_PLL_LOCK_REG                                       , RULL(0x150F0019), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_PLL_LOCK_REG                                         , RULL(0x200F0019), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0019,
+REG64( EX_0_PLL_LOCK_REG                                       , RULL(0x200F0019), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0019,
+REG64( EX_1_PLL_LOCK_REG                                       , RULL(0x230F0019), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0019,
+REG64( EX_2_PLL_LOCK_REG                                       , RULL(0x240F0019), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0019,
+REG64( EX_3_PLL_LOCK_REG                                       , RULL(0x260F0019), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0019,
+REG64( EX_4_PLL_LOCK_REG                                       , RULL(0x280F0019), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0019,
+REG64( EX_5_PLL_LOCK_REG                                       , RULL(0x2A0F0019), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0019,
+REG64( EX_6_PLL_LOCK_REG                                       , RULL(0x2C0F0019), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0019,
+REG64( EX_7_PLL_LOCK_REG                                       , RULL(0x2E0F0019), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0019,
+REG64( EX_8_PLL_LOCK_REG                                       , RULL(0x300F0019), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0019,
+REG64( EX_9_PLL_LOCK_REG                                       , RULL(0x320F0019), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0019,
+REG64( EX_10_PLL_LOCK_REG                                      , RULL(0x340F0019), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0019,
+REG64( EX_11_PLL_LOCK_REG                                      , RULL(0x360F0019), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0019,
+
+REG64( C_PMU_HOLD_OUT                                          , RULL(0x20010AB6), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_PMU_HOLD_OUT                                        , RULL(0x20010AB6), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_PMU_HOLD_OUT                                        , RULL(0x21010AB6), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_PMU_HOLD_OUT                                        , RULL(0x22010AB6), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_PMU_HOLD_OUT                                        , RULL(0x23010AB6), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_PMU_HOLD_OUT                                        , RULL(0x24010AB6), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_PMU_HOLD_OUT                                        , RULL(0x25010AB6), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_PMU_HOLD_OUT                                        , RULL(0x26010AB6), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_PMU_HOLD_OUT                                        , RULL(0x27010AB6), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_PMU_HOLD_OUT                                        , RULL(0x28010AB6), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_PMU_HOLD_OUT                                        , RULL(0x29010AB6), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_PMU_HOLD_OUT                                       , RULL(0x2A010AB6), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_PMU_HOLD_OUT                                       , RULL(0x2B010AB6), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_PMU_HOLD_OUT                                       , RULL(0x2C010AB6), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_PMU_HOLD_OUT                                       , RULL(0x2D010AB6), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_PMU_HOLD_OUT                                       , RULL(0x2E010AB6), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_PMU_HOLD_OUT                                       , RULL(0x2F010AB6), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_PMU_HOLD_OUT                                       , RULL(0x30010AB6), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_PMU_HOLD_OUT                                       , RULL(0x31010AB6), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_PMU_HOLD_OUT                                       , RULL(0x32010AB6), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_PMU_HOLD_OUT                                       , RULL(0x33010AB6), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_PMU_HOLD_OUT                                       , RULL(0x34010AB6), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_PMU_HOLD_OUT                                       , RULL(0x35010AB6), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_PMU_HOLD_OUT                                       , RULL(0x36010AB6), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_PMU_HOLD_OUT                                       , RULL(0x37010AB6), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_PMU_HOLD_OUT                                    , RULL(0x20010AB6), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010AB6,
+REG64( EX_10_L2_PMU_HOLD_OUT                                   , RULL(0x34010AB6), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010AB6,
+REG64( EX_11_L2_PMU_HOLD_OUT                                   , RULL(0x36010AB6), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010AB6,
+REG64( EX_1_L2_PMU_HOLD_OUT                                    , RULL(0x22010AB6), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010AB6,
+REG64( EX_2_L2_PMU_HOLD_OUT                                    , RULL(0x24010AB6), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010AB6,
+REG64( EX_3_L2_PMU_HOLD_OUT                                    , RULL(0x26010AB6), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010AB6,
+REG64( EX_4_L2_PMU_HOLD_OUT                                    , RULL(0x28010AB6), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010AB6,
+REG64( EX_5_L2_PMU_HOLD_OUT                                    , RULL(0x2A010AB6), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010AB6,
+REG64( EX_6_L2_PMU_HOLD_OUT                                    , RULL(0x2C010AB6), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010AB6,
+REG64( EX_7_L2_PMU_HOLD_OUT                                    , RULL(0x2E010AB6), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010AB6,
+REG64( EX_8_L2_PMU_HOLD_OUT                                    , RULL(0x30010AB6), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010AB6,
+REG64( EX_9_L2_PMU_HOLD_OUT                                    , RULL(0x32010AB6), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010AB6,
+REG64( EX_L2_PMU_HOLD_OUT                                      , RULL(0x20010AB6), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010AB6,
+
+REG64( C_PMU_SCOMC                                             , RULL(0x20010AB0), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_PMU_SCOMC                                           , RULL(0x20010AB0), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_PMU_SCOMC                                           , RULL(0x21010AB0), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_PMU_SCOMC                                           , RULL(0x22010AB0), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_PMU_SCOMC                                           , RULL(0x23010AB0), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_PMU_SCOMC                                           , RULL(0x24010AB0), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_PMU_SCOMC                                           , RULL(0x25010AB0), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_PMU_SCOMC                                           , RULL(0x26010AB0), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_PMU_SCOMC                                           , RULL(0x27010AB0), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_PMU_SCOMC                                           , RULL(0x28010AB0), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_PMU_SCOMC                                           , RULL(0x29010AB0), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_PMU_SCOMC                                          , RULL(0x2A010AB0), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_PMU_SCOMC                                          , RULL(0x2B010AB0), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_PMU_SCOMC                                          , RULL(0x2C010AB0), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_PMU_SCOMC                                          , RULL(0x2D010AB0), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_PMU_SCOMC                                          , RULL(0x2E010AB0), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_PMU_SCOMC                                          , RULL(0x2F010AB0), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_PMU_SCOMC                                          , RULL(0x30010AB0), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_PMU_SCOMC                                          , RULL(0x31010AB0), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_PMU_SCOMC                                          , RULL(0x32010AB0), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_PMU_SCOMC                                          , RULL(0x33010AB0), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_PMU_SCOMC                                          , RULL(0x34010AB0), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_PMU_SCOMC                                          , RULL(0x35010AB0), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_PMU_SCOMC                                          , RULL(0x36010AB0), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_PMU_SCOMC                                          , RULL(0x37010AB0), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_PMU_SCOMC                                       , RULL(0x20010AB0), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010AB0,
+REG64( EX_10_L2_PMU_SCOMC                                      , RULL(0x34010AB0), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010AB0,
+REG64( EX_11_L2_PMU_SCOMC                                      , RULL(0x36010AB0), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010AB0,
+REG64( EX_1_L2_PMU_SCOMC                                       , RULL(0x22010AB0), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010AB0,
+REG64( EX_2_L2_PMU_SCOMC                                       , RULL(0x24010AB0), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010AB0,
+REG64( EX_3_L2_PMU_SCOMC                                       , RULL(0x26010AB0), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010AB0,
+REG64( EX_4_L2_PMU_SCOMC                                       , RULL(0x28010AB0), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010AB0,
+REG64( EX_5_L2_PMU_SCOMC                                       , RULL(0x2A010AB0), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010AB0,
+REG64( EX_6_L2_PMU_SCOMC                                       , RULL(0x2C010AB0), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010AB0,
+REG64( EX_7_L2_PMU_SCOMC                                       , RULL(0x2E010AB0), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010AB0,
+REG64( EX_8_L2_PMU_SCOMC                                       , RULL(0x30010AB0), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010AB0,
+REG64( EX_9_L2_PMU_SCOMC                                       , RULL(0x32010AB0), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010AB0,
+REG64( EX_L2_PMU_SCOMC                                         , RULL(0x20010AB0), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010AB0,
+
+REG64( C_PMU_SCOMC_EN                                          , RULL(0x20010AB2), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_PMU_SCOMC_EN                                        , RULL(0x20010AB2), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_PMU_SCOMC_EN                                        , RULL(0x21010AB2), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_PMU_SCOMC_EN                                        , RULL(0x22010AB2), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_PMU_SCOMC_EN                                        , RULL(0x23010AB2), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_PMU_SCOMC_EN                                        , RULL(0x24010AB2), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_PMU_SCOMC_EN                                        , RULL(0x25010AB2), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_PMU_SCOMC_EN                                        , RULL(0x26010AB2), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_PMU_SCOMC_EN                                        , RULL(0x27010AB2), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_PMU_SCOMC_EN                                        , RULL(0x28010AB2), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_PMU_SCOMC_EN                                        , RULL(0x29010AB2), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_PMU_SCOMC_EN                                       , RULL(0x2A010AB2), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_PMU_SCOMC_EN                                       , RULL(0x2B010AB2), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_PMU_SCOMC_EN                                       , RULL(0x2C010AB2), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_PMU_SCOMC_EN                                       , RULL(0x2D010AB2), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_PMU_SCOMC_EN                                       , RULL(0x2E010AB2), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_PMU_SCOMC_EN                                       , RULL(0x2F010AB2), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_PMU_SCOMC_EN                                       , RULL(0x30010AB2), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_PMU_SCOMC_EN                                       , RULL(0x31010AB2), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_PMU_SCOMC_EN                                       , RULL(0x32010AB2), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_PMU_SCOMC_EN                                       , RULL(0x33010AB2), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_PMU_SCOMC_EN                                       , RULL(0x34010AB2), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_PMU_SCOMC_EN                                       , RULL(0x35010AB2), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_PMU_SCOMC_EN                                       , RULL(0x36010AB2), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_PMU_SCOMC_EN                                       , RULL(0x37010AB2), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_PMU_SCOMC_EN                                    , RULL(0x20010AB2), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010AB2,
+REG64( EX_10_L2_PMU_SCOMC_EN                                   , RULL(0x34010AB2), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010AB2,
+REG64( EX_11_L2_PMU_SCOMC_EN                                   , RULL(0x36010AB2), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010AB2,
+REG64( EX_1_L2_PMU_SCOMC_EN                                    , RULL(0x22010AB2), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010AB2,
+REG64( EX_2_L2_PMU_SCOMC_EN                                    , RULL(0x24010AB2), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010AB2,
+REG64( EX_3_L2_PMU_SCOMC_EN                                    , RULL(0x26010AB2), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010AB2,
+REG64( EX_4_L2_PMU_SCOMC_EN                                    , RULL(0x28010AB2), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010AB2,
+REG64( EX_5_L2_PMU_SCOMC_EN                                    , RULL(0x2A010AB2), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010AB2,
+REG64( EX_6_L2_PMU_SCOMC_EN                                    , RULL(0x2C010AB2), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010AB2,
+REG64( EX_7_L2_PMU_SCOMC_EN                                    , RULL(0x2E010AB2), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010AB2,
+REG64( EX_8_L2_PMU_SCOMC_EN                                    , RULL(0x30010AB2), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010AB2,
+REG64( EX_9_L2_PMU_SCOMC_EN                                    , RULL(0x32010AB2), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010AB2,
+REG64( EX_L2_PMU_SCOMC_EN                                      , RULL(0x20010AB2), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010AB2,
+
+REG64( EQ_PM_L2_RCMD_DIS_REG                                   , RULL(0x10011818), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C18,
+REG64( EQ_0_PM_L2_RCMD_DIS_REG                                 , RULL(0x10011818), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C18,
+REG64( EQ_1_PM_L2_RCMD_DIS_REG                                 , RULL(0x11011818), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C18,
+REG64( EQ_2_PM_L2_RCMD_DIS_REG                                 , RULL(0x12011818), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C18,
+REG64( EQ_3_PM_L2_RCMD_DIS_REG                                 , RULL(0x13011818), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C18,
+REG64( EQ_4_PM_L2_RCMD_DIS_REG                                 , RULL(0x14011818), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C18,
+REG64( EQ_5_PM_L2_RCMD_DIS_REG                                 , RULL(0x15011818), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C18,
+REG64( EX_PM_L2_RCMD_DIS_REG                                   , RULL(0x10011818), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_PM_L2_RCMD_DIS_REG                                 , RULL(0x10011818), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_PM_L2_RCMD_DIS_REG                                 , RULL(0x10011C18), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_PM_L2_RCMD_DIS_REG                                 , RULL(0x11011818), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_PM_L2_RCMD_DIS_REG                                 , RULL(0x11011C18), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_PM_L2_RCMD_DIS_REG                                 , RULL(0x12011818), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_PM_L2_RCMD_DIS_REG                                 , RULL(0x12011C18), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_PM_L2_RCMD_DIS_REG                                 , RULL(0x13011818), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_PM_L2_RCMD_DIS_REG                                 , RULL(0x13011C18), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_PM_L2_RCMD_DIS_REG                                 , RULL(0x14011818), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_PM_L2_RCMD_DIS_REG                                 , RULL(0x14011C18), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_PM_L2_RCMD_DIS_REG                                , RULL(0x15011818), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_PM_L2_RCMD_DIS_REG                                , RULL(0x15011C18), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_PM_LCO_DIS_REG                                       , RULL(0x10011816), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C16,
+REG64( EQ_0_PM_LCO_DIS_REG                                     , RULL(0x10011816), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C16,
+REG64( EQ_1_PM_LCO_DIS_REG                                     , RULL(0x11011816), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C16,
+REG64( EQ_2_PM_LCO_DIS_REG                                     , RULL(0x12011816), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C16,
+REG64( EQ_3_PM_LCO_DIS_REG                                     , RULL(0x13011816), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C16,
+REG64( EQ_4_PM_LCO_DIS_REG                                     , RULL(0x14011816), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C16,
+REG64( EQ_5_PM_LCO_DIS_REG                                     , RULL(0x15011816), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C16,
+REG64( EX_0_L3_PM_LCO_DIS_REG                                  , RULL(0x10011816), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_L3_PM_LCO_DIS_REG                                 , RULL(0x15011816), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L3_PM_LCO_DIS_REG                                 , RULL(0x15011C16), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L3_PM_LCO_DIS_REG                                  , RULL(0x10011C16), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L3_PM_LCO_DIS_REG                                  , RULL(0x11011816), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L3_PM_LCO_DIS_REG                                  , RULL(0x11011C16), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L3_PM_LCO_DIS_REG                                  , RULL(0x12011816), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L3_PM_LCO_DIS_REG                                  , RULL(0x12011C16), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L3_PM_LCO_DIS_REG                                  , RULL(0x13011816), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L3_PM_LCO_DIS_REG                                  , RULL(0x13011C16), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L3_PM_LCO_DIS_REG                                  , RULL(0x14011816), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L3_PM_LCO_DIS_REG                                  , RULL(0x14011C16), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L3_PM_LCO_DIS_REG                                    , RULL(0x10011816), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( EQ_PM_PURGE_REG                                         , RULL(0x10011813), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C13,
+REG64( EQ_0_PM_PURGE_REG                                       , RULL(0x10011813), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C13,
+REG64( EQ_1_PM_PURGE_REG                                       , RULL(0x11011813), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C13,
+REG64( EQ_2_PM_PURGE_REG                                       , RULL(0x12011813), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C13,
+REG64( EQ_3_PM_PURGE_REG                                       , RULL(0x13011813), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C13,
+REG64( EQ_4_PM_PURGE_REG                                       , RULL(0x14011813), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C13,
+REG64( EQ_5_PM_PURGE_REG                                       , RULL(0x15011813), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C13,
+REG64( EX_0_L3_PM_PURGE_REG                                    , RULL(0x10011813), SH_UNT_EX_0_L3  , SH_ACS_SCOM      );
+REG64( EX_10_L3_PM_PURGE_REG                                   , RULL(0x15011813), SH_UNT_EX_10_L3 , SH_ACS_SCOM      );
+REG64( EX_11_L3_PM_PURGE_REG                                   , RULL(0x15011C13), SH_UNT_EX_11_L3 , SH_ACS_SCOM      );
+REG64( EX_1_L3_PM_PURGE_REG                                    , RULL(0x10011C13), SH_UNT_EX_1_L3  , SH_ACS_SCOM      );
+REG64( EX_2_L3_PM_PURGE_REG                                    , RULL(0x11011813), SH_UNT_EX_2_L3  , SH_ACS_SCOM      );
+REG64( EX_3_L3_PM_PURGE_REG                                    , RULL(0x11011C13), SH_UNT_EX_3_L3  , SH_ACS_SCOM      );
+REG64( EX_4_L3_PM_PURGE_REG                                    , RULL(0x12011813), SH_UNT_EX_4_L3  , SH_ACS_SCOM      );
+REG64( EX_5_L3_PM_PURGE_REG                                    , RULL(0x12011C13), SH_UNT_EX_5_L3  , SH_ACS_SCOM      );
+REG64( EX_6_L3_PM_PURGE_REG                                    , RULL(0x13011813), SH_UNT_EX_6_L3  , SH_ACS_SCOM      );
+REG64( EX_7_L3_PM_PURGE_REG                                    , RULL(0x13011C13), SH_UNT_EX_7_L3  , SH_ACS_SCOM      );
+REG64( EX_8_L3_PM_PURGE_REG                                    , RULL(0x14011813), SH_UNT_EX_8_L3  , SH_ACS_SCOM      );
+REG64( EX_9_L3_PM_PURGE_REG                                    , RULL(0x14011C13), SH_UNT_EX_9_L3  , SH_ACS_SCOM      );
+REG64( EX_L3_PM_PURGE_REG                                      , RULL(0x10011813), SH_UNT_EX_L3    , SH_ACS_SCOM      );
+
+REG64( EQ_PPE_XIDBGPRO                                         , RULL(0x10012415), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10012015,
+REG64( EQ_0_PPE_XIDBGPRO                                       , RULL(0x10012415), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10012015,
+REG64( EQ_1_PPE_XIDBGPRO                                       , RULL(0x11012415), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11012015,
+REG64( EQ_2_PPE_XIDBGPRO                                       , RULL(0x12012415), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12012015,
+REG64( EQ_3_PPE_XIDBGPRO                                       , RULL(0x13012415), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13012015,
+REG64( EQ_4_PPE_XIDBGPRO                                       , RULL(0x14012415), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14012015,
+REG64( EQ_5_PPE_XIDBGPRO                                       , RULL(0x15012415), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15012015,
+REG64( EX_PPE_XIDBGPRO                                         , RULL(0x10012015), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_PPE_XIDBGPRO                                       , RULL(0x10012015), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_PPE_XIDBGPRO                                       , RULL(0x10012415), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_PPE_XIDBGPRO                                       , RULL(0x11012015), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_PPE_XIDBGPRO                                       , RULL(0x11012415), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_PPE_XIDBGPRO                                       , RULL(0x12012015), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_PPE_XIDBGPRO                                       , RULL(0x12012415), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_PPE_XIDBGPRO                                       , RULL(0x13012015), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_PPE_XIDBGPRO                                       , RULL(0x13012415), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_PPE_XIDBGPRO                                       , RULL(0x14012015), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_PPE_XIDBGPRO                                       , RULL(0x14012415), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_PPE_XIDBGPRO                                      , RULL(0x15012015), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_PPE_XIDBGPRO                                      , RULL(0x15012415), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_PPE_XIRAMDBG                                         , RULL(0x10012413), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10012013,
+REG64( EQ_0_PPE_XIRAMDBG                                       , RULL(0x10012413), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10012013,
+REG64( EQ_1_PPE_XIRAMDBG                                       , RULL(0x11012413), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11012013,
+REG64( EQ_2_PPE_XIRAMDBG                                       , RULL(0x12012413), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12012013,
+REG64( EQ_3_PPE_XIRAMDBG                                       , RULL(0x13012413), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13012013,
+REG64( EQ_4_PPE_XIRAMDBG                                       , RULL(0x14012413), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14012013,
+REG64( EQ_5_PPE_XIRAMDBG                                       , RULL(0x15012413), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15012013,
+REG64( EX_PPE_XIRAMDBG                                         , RULL(0x10012013), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_PPE_XIRAMDBG                                       , RULL(0x10012013), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_PPE_XIRAMDBG                                       , RULL(0x10012413), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_PPE_XIRAMDBG                                       , RULL(0x11012013), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_PPE_XIRAMDBG                                       , RULL(0x11012413), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_PPE_XIRAMDBG                                       , RULL(0x12012013), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_PPE_XIRAMDBG                                       , RULL(0x12012413), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_PPE_XIRAMDBG                                       , RULL(0x13012013), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_PPE_XIRAMDBG                                       , RULL(0x13012413), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_PPE_XIRAMDBG                                       , RULL(0x14012013), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_PPE_XIRAMDBG                                       , RULL(0x14012413), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_PPE_XIRAMDBG                                      , RULL(0x15012013), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_PPE_XIRAMDBG                                      , RULL(0x15012413), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_PPE_XIRAMEDR                                         , RULL(0x10012414), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10012014,
+REG64( EQ_0_PPE_XIRAMEDR                                       , RULL(0x10012414), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10012014,
+REG64( EQ_1_PPE_XIRAMEDR                                       , RULL(0x11012414), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11012014,
+REG64( EQ_2_PPE_XIRAMEDR                                       , RULL(0x12012414), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12012014,
+REG64( EQ_3_PPE_XIRAMEDR                                       , RULL(0x13012414), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13012014,
+REG64( EQ_4_PPE_XIRAMEDR                                       , RULL(0x14012414), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14012014,
+REG64( EQ_5_PPE_XIRAMEDR                                       , RULL(0x15012414), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15012014,
+REG64( EX_PPE_XIRAMEDR                                         , RULL(0x10012014), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_PPE_XIRAMEDR                                       , RULL(0x10012014), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_PPE_XIRAMEDR                                       , RULL(0x10012414), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_PPE_XIRAMEDR                                       , RULL(0x11012014), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_PPE_XIRAMEDR                                       , RULL(0x11012414), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_PPE_XIRAMEDR                                       , RULL(0x12012014), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_PPE_XIRAMEDR                                       , RULL(0x12012414), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_PPE_XIRAMEDR                                       , RULL(0x13012014), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_PPE_XIRAMEDR                                       , RULL(0x13012414), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_PPE_XIRAMEDR                                       , RULL(0x14012014), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_PPE_XIRAMEDR                                       , RULL(0x14012414), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_PPE_XIRAMEDR                                      , RULL(0x15012014), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_PPE_XIRAMEDR                                      , RULL(0x15012414), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_PPE_XIRAMGA                                          , RULL(0x10012412), SH_UNT_EQ       ,
+       SH_ACS_SCOM_WO   ); //DUPS: 10012012,
+REG64( EQ_0_PPE_XIRAMGA                                        , RULL(0x10012412), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 10012012,
+REG64( EQ_1_PPE_XIRAMGA                                        , RULL(0x11012412), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 11012012,
+REG64( EQ_2_PPE_XIRAMGA                                        , RULL(0x12012412), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 12012012,
+REG64( EQ_3_PPE_XIRAMGA                                        , RULL(0x13012412), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 13012012,
+REG64( EQ_4_PPE_XIRAMGA                                        , RULL(0x14012412), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 14012012,
+REG64( EQ_5_PPE_XIRAMGA                                        , RULL(0x15012412), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 15012012,
+REG64( EX_PPE_XIRAMGA                                          , RULL(0x10012012), SH_UNT_EX       , SH_ACS_SCOM_WO   );
+REG64( EX_0_PPE_XIRAMGA                                        , RULL(0x10012012), SH_UNT_EX_0     , SH_ACS_SCOM_WO   );
+REG64( EX_1_PPE_XIRAMGA                                        , RULL(0x10012412), SH_UNT_EX_1     , SH_ACS_SCOM_WO   );
+REG64( EX_2_PPE_XIRAMGA                                        , RULL(0x11012012), SH_UNT_EX_2     , SH_ACS_SCOM_WO   );
+REG64( EX_3_PPE_XIRAMGA                                        , RULL(0x11012412), SH_UNT_EX_3     , SH_ACS_SCOM_WO   );
+REG64( EX_4_PPE_XIRAMGA                                        , RULL(0x12012012), SH_UNT_EX_4     , SH_ACS_SCOM_WO   );
+REG64( EX_5_PPE_XIRAMGA                                        , RULL(0x12012412), SH_UNT_EX_5     , SH_ACS_SCOM_WO   );
+REG64( EX_6_PPE_XIRAMGA                                        , RULL(0x13012012), SH_UNT_EX_6     , SH_ACS_SCOM_WO   );
+REG64( EX_7_PPE_XIRAMGA                                        , RULL(0x13012412), SH_UNT_EX_7     , SH_ACS_SCOM_WO   );
+REG64( EX_8_PPE_XIRAMGA                                        , RULL(0x14012012), SH_UNT_EX_8     , SH_ACS_SCOM_WO   );
+REG64( EX_9_PPE_XIRAMGA                                        , RULL(0x14012412), SH_UNT_EX_9     , SH_ACS_SCOM_WO   );
+REG64( EX_10_PPE_XIRAMGA                                       , RULL(0x15012012), SH_UNT_EX_10    , SH_ACS_SCOM_WO   );
+REG64( EX_11_PPE_XIRAMGA                                       , RULL(0x15012412), SH_UNT_EX_11    , SH_ACS_SCOM_WO   );
+
+REG64( EQ_PPE_XIRAMRA                                          , RULL(0x10012411), SH_UNT_EQ       ,
+       SH_ACS_SCOM_WO   ); //DUPS: 10012011,
+REG64( EQ_0_PPE_XIRAMRA                                        , RULL(0x10012411), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 10012011,
+REG64( EQ_1_PPE_XIRAMRA                                        , RULL(0x11012411), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 11012011,
+REG64( EQ_2_PPE_XIRAMRA                                        , RULL(0x12012411), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 12012011,
+REG64( EQ_3_PPE_XIRAMRA                                        , RULL(0x13012411), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 13012011,
+REG64( EQ_4_PPE_XIRAMRA                                        , RULL(0x14012411), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 14012011,
+REG64( EQ_5_PPE_XIRAMRA                                        , RULL(0x15012411), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 15012011,
+REG64( EX_PPE_XIRAMRA                                          , RULL(0x10012011), SH_UNT_EX       , SH_ACS_SCOM_WO   );
+REG64( EX_0_PPE_XIRAMRA                                        , RULL(0x10012011), SH_UNT_EX_0     , SH_ACS_SCOM_WO   );
+REG64( EX_1_PPE_XIRAMRA                                        , RULL(0x10012411), SH_UNT_EX_1     , SH_ACS_SCOM_WO   );
+REG64( EX_2_PPE_XIRAMRA                                        , RULL(0x11012011), SH_UNT_EX_2     , SH_ACS_SCOM_WO   );
+REG64( EX_3_PPE_XIRAMRA                                        , RULL(0x11012411), SH_UNT_EX_3     , SH_ACS_SCOM_WO   );
+REG64( EX_4_PPE_XIRAMRA                                        , RULL(0x12012011), SH_UNT_EX_4     , SH_ACS_SCOM_WO   );
+REG64( EX_5_PPE_XIRAMRA                                        , RULL(0x12012411), SH_UNT_EX_5     , SH_ACS_SCOM_WO   );
+REG64( EX_6_PPE_XIRAMRA                                        , RULL(0x13012011), SH_UNT_EX_6     , SH_ACS_SCOM_WO   );
+REG64( EX_7_PPE_XIRAMRA                                        , RULL(0x13012411), SH_UNT_EX_7     , SH_ACS_SCOM_WO   );
+REG64( EX_8_PPE_XIRAMRA                                        , RULL(0x14012011), SH_UNT_EX_8     , SH_ACS_SCOM_WO   );
+REG64( EX_9_PPE_XIRAMRA                                        , RULL(0x14012411), SH_UNT_EX_9     , SH_ACS_SCOM_WO   );
+REG64( EX_10_PPE_XIRAMRA                                       , RULL(0x15012011), SH_UNT_EX_10    , SH_ACS_SCOM_WO   );
+REG64( EX_11_PPE_XIRAMRA                                       , RULL(0x15012411), SH_UNT_EX_11    , SH_ACS_SCOM_WO   );
+
+REG64( EQ_PPE_XIXCR                                            , RULL(0x10012410), SH_UNT_EQ       ,
+       SH_ACS_SCOM_WO   ); //DUPS: 10012010,
+REG64( EQ_0_PPE_XIXCR                                          , RULL(0x10012410), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 10012010,
+REG64( EQ_1_PPE_XIXCR                                          , RULL(0x11012410), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 11012010,
+REG64( EQ_2_PPE_XIXCR                                          , RULL(0x12012410), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 12012010,
+REG64( EQ_3_PPE_XIXCR                                          , RULL(0x13012410), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 13012010,
+REG64( EQ_4_PPE_XIXCR                                          , RULL(0x14012410), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 14012010,
+REG64( EQ_5_PPE_XIXCR                                          , RULL(0x15012410), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_WO   ); //DUPS: 15012010,
+REG64( EX_PPE_XIXCR                                            , RULL(0x10012010), SH_UNT_EX       , SH_ACS_SCOM_WO   );
+REG64( EX_0_PPE_XIXCR                                          , RULL(0x10012010), SH_UNT_EX_0     , SH_ACS_SCOM_WO   );
+REG64( EX_1_PPE_XIXCR                                          , RULL(0x10012410), SH_UNT_EX_1     , SH_ACS_SCOM_WO   );
+REG64( EX_2_PPE_XIXCR                                          , RULL(0x11012010), SH_UNT_EX_2     , SH_ACS_SCOM_WO   );
+REG64( EX_3_PPE_XIXCR                                          , RULL(0x11012410), SH_UNT_EX_3     , SH_ACS_SCOM_WO   );
+REG64( EX_4_PPE_XIXCR                                          , RULL(0x12012010), SH_UNT_EX_4     , SH_ACS_SCOM_WO   );
+REG64( EX_5_PPE_XIXCR                                          , RULL(0x12012410), SH_UNT_EX_5     , SH_ACS_SCOM_WO   );
+REG64( EX_6_PPE_XIXCR                                          , RULL(0x13012010), SH_UNT_EX_6     , SH_ACS_SCOM_WO   );
+REG64( EX_7_PPE_XIXCR                                          , RULL(0x13012410), SH_UNT_EX_7     , SH_ACS_SCOM_WO   );
+REG64( EX_8_PPE_XIXCR                                          , RULL(0x14012010), SH_UNT_EX_8     , SH_ACS_SCOM_WO   );
+REG64( EX_9_PPE_XIXCR                                          , RULL(0x14012410), SH_UNT_EX_9     , SH_ACS_SCOM_WO   );
+REG64( EX_10_PPE_XIXCR                                         , RULL(0x15012010), SH_UNT_EX_10    , SH_ACS_SCOM_WO   );
+REG64( EX_11_PPE_XIXCR                                         , RULL(0x15012410), SH_UNT_EX_11    , SH_ACS_SCOM_WO   );
+
+REG64( C_PPM_CGCR                                              , RULL(0x200F0164), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_PPM_CGCR                                            , RULL(0x200F0164), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_PPM_CGCR                                            , RULL(0x210F0164), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_PPM_CGCR                                            , RULL(0x220F0164), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_PPM_CGCR                                            , RULL(0x230F0164), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_PPM_CGCR                                            , RULL(0x240F0164), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_PPM_CGCR                                            , RULL(0x250F0164), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_PPM_CGCR                                            , RULL(0x260F0164), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_PPM_CGCR                                            , RULL(0x270F0164), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_PPM_CGCR                                            , RULL(0x280F0164), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_PPM_CGCR                                            , RULL(0x290F0164), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_PPM_CGCR                                           , RULL(0x2A0F0164), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_PPM_CGCR                                           , RULL(0x2B0F0164), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_PPM_CGCR                                           , RULL(0x2C0F0164), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_PPM_CGCR                                           , RULL(0x2D0F0164), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_PPM_CGCR                                           , RULL(0x2E0F0164), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_PPM_CGCR                                           , RULL(0x2F0F0164), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_PPM_CGCR                                           , RULL(0x300F0164), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_PPM_CGCR                                           , RULL(0x310F0164), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_PPM_CGCR                                           , RULL(0x320F0164), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_PPM_CGCR                                           , RULL(0x330F0164), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_PPM_CGCR                                           , RULL(0x340F0164), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_PPM_CGCR                                           , RULL(0x350F0164), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_PPM_CGCR                                           , RULL(0x360F0164), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_PPM_CGCR                                           , RULL(0x370F0164), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_PPM_CGCR                                             , RULL(0x100F0164), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_PPM_CGCR                                           , RULL(0x100F0164), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_PPM_CGCR                                           , RULL(0x110F0164), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_PPM_CGCR                                           , RULL(0x120F0164), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_PPM_CGCR                                           , RULL(0x130F0164), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_PPM_CGCR                                           , RULL(0x140F0164), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_PPM_CGCR                                           , RULL(0x150F0164), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_PPM_CGCR                                             , RULL(0x200F0164), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0164,
+REG64( EX_0_PPM_CGCR                                           , RULL(0x200F0164), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F0164,
+REG64( EX_1_PPM_CGCR                                           , RULL(0x230F0164), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F0164,
+REG64( EX_2_PPM_CGCR                                           , RULL(0x240F0164), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F0164,
+REG64( EX_3_PPM_CGCR                                           , RULL(0x260F0164), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F0164,
+REG64( EX_4_PPM_CGCR                                           , RULL(0x280F0164), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F0164,
+REG64( EX_5_PPM_CGCR                                           , RULL(0x2A0F0164), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F0164,
+REG64( EX_6_PPM_CGCR                                           , RULL(0x2C0F0164), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F0164,
+REG64( EX_7_PPM_CGCR                                           , RULL(0x2E0F0164), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F0164,
+REG64( EX_8_PPM_CGCR                                           , RULL(0x300F0164), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F0164,
+REG64( EX_9_PPM_CGCR                                           , RULL(0x320F0164), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F0164,
+REG64( EX_10_PPM_CGCR                                          , RULL(0x340F0164), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F0164,
+REG64( EX_11_PPM_CGCR                                          , RULL(0x360F0164), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F0164,
+
+REG64( C_PPM_GPMMR_SCOM                                        , RULL(0x200F0100), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_PPM_GPMMR_SCOM1                                       , RULL(0x200F0101), SH_UNT_C        , SH_ACS_SCOM1     );
+REG64( C_PPM_GPMMR_SCOM2                                       , RULL(0x200F0102), SH_UNT_C        , SH_ACS_SCOM2     );
+REG64( C_0_PPM_GPMMR_SCOM                                      , RULL(0x200F0100), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_0_PPM_GPMMR_SCOM1                                     , RULL(0x200F0101), SH_UNT_C_0      , SH_ACS_SCOM1     );
+REG64( C_0_PPM_GPMMR_SCOM2                                     , RULL(0x200F0102), SH_UNT_C_0      , SH_ACS_SCOM2     );
+REG64( C_1_PPM_GPMMR_SCOM                                      , RULL(0x210F0100), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_1_PPM_GPMMR_SCOM1                                     , RULL(0x210F0101), SH_UNT_C_1      , SH_ACS_SCOM1     );
+REG64( C_1_PPM_GPMMR_SCOM2                                     , RULL(0x210F0102), SH_UNT_C_1      , SH_ACS_SCOM2     );
+REG64( C_2_PPM_GPMMR_SCOM                                      , RULL(0x220F0100), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_2_PPM_GPMMR_SCOM1                                     , RULL(0x220F0101), SH_UNT_C_2      , SH_ACS_SCOM1     );
+REG64( C_2_PPM_GPMMR_SCOM2                                     , RULL(0x220F0102), SH_UNT_C_2      , SH_ACS_SCOM2     );
+REG64( C_3_PPM_GPMMR_SCOM                                      , RULL(0x230F0100), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_3_PPM_GPMMR_SCOM1                                     , RULL(0x230F0101), SH_UNT_C_3      , SH_ACS_SCOM1     );
+REG64( C_3_PPM_GPMMR_SCOM2                                     , RULL(0x230F0102), SH_UNT_C_3      , SH_ACS_SCOM2     );
+REG64( C_4_PPM_GPMMR_SCOM                                      , RULL(0x240F0100), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_4_PPM_GPMMR_SCOM1                                     , RULL(0x240F0101), SH_UNT_C_4      , SH_ACS_SCOM1     );
+REG64( C_4_PPM_GPMMR_SCOM2                                     , RULL(0x240F0102), SH_UNT_C_4      , SH_ACS_SCOM2     );
+REG64( C_5_PPM_GPMMR_SCOM                                      , RULL(0x250F0100), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_5_PPM_GPMMR_SCOM1                                     , RULL(0x250F0101), SH_UNT_C_5      , SH_ACS_SCOM1     );
+REG64( C_5_PPM_GPMMR_SCOM2                                     , RULL(0x250F0102), SH_UNT_C_5      , SH_ACS_SCOM2     );
+REG64( C_6_PPM_GPMMR_SCOM                                      , RULL(0x260F0100), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_6_PPM_GPMMR_SCOM1                                     , RULL(0x260F0101), SH_UNT_C_6      , SH_ACS_SCOM1     );
+REG64( C_6_PPM_GPMMR_SCOM2                                     , RULL(0x260F0102), SH_UNT_C_6      , SH_ACS_SCOM2     );
+REG64( C_7_PPM_GPMMR_SCOM                                      , RULL(0x270F0100), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_7_PPM_GPMMR_SCOM1                                     , RULL(0x270F0101), SH_UNT_C_7      , SH_ACS_SCOM1     );
+REG64( C_7_PPM_GPMMR_SCOM2                                     , RULL(0x270F0102), SH_UNT_C_7      , SH_ACS_SCOM2     );
+REG64( C_8_PPM_GPMMR_SCOM                                      , RULL(0x280F0100), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_8_PPM_GPMMR_SCOM1                                     , RULL(0x280F0101), SH_UNT_C_8      , SH_ACS_SCOM1     );
+REG64( C_8_PPM_GPMMR_SCOM2                                     , RULL(0x280F0102), SH_UNT_C_8      , SH_ACS_SCOM2     );
+REG64( C_9_PPM_GPMMR_SCOM                                      , RULL(0x290F0100), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_9_PPM_GPMMR_SCOM1                                     , RULL(0x290F0101), SH_UNT_C_9      , SH_ACS_SCOM1     );
+REG64( C_9_PPM_GPMMR_SCOM2                                     , RULL(0x290F0102), SH_UNT_C_9      , SH_ACS_SCOM2     );
+REG64( C_10_PPM_GPMMR_SCOM                                     , RULL(0x2A0F0100), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_10_PPM_GPMMR_SCOM1                                    , RULL(0x2A0F0101), SH_UNT_C_10     , SH_ACS_SCOM1     );
+REG64( C_10_PPM_GPMMR_SCOM2                                    , RULL(0x2A0F0102), SH_UNT_C_10     , SH_ACS_SCOM2     );
+REG64( C_11_PPM_GPMMR_SCOM                                     , RULL(0x2B0F0100), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_11_PPM_GPMMR_SCOM1                                    , RULL(0x2B0F0101), SH_UNT_C_11     , SH_ACS_SCOM1     );
+REG64( C_11_PPM_GPMMR_SCOM2                                    , RULL(0x2B0F0102), SH_UNT_C_11     , SH_ACS_SCOM2     );
+REG64( C_12_PPM_GPMMR_SCOM                                     , RULL(0x2C0F0100), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_12_PPM_GPMMR_SCOM1                                    , RULL(0x2C0F0101), SH_UNT_C_12     , SH_ACS_SCOM1     );
+REG64( C_12_PPM_GPMMR_SCOM2                                    , RULL(0x2C0F0102), SH_UNT_C_12     , SH_ACS_SCOM2     );
+REG64( C_13_PPM_GPMMR_SCOM                                     , RULL(0x2D0F0100), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_13_PPM_GPMMR_SCOM1                                    , RULL(0x2D0F0101), SH_UNT_C_13     , SH_ACS_SCOM1     );
+REG64( C_13_PPM_GPMMR_SCOM2                                    , RULL(0x2D0F0102), SH_UNT_C_13     , SH_ACS_SCOM2     );
+REG64( C_14_PPM_GPMMR_SCOM                                     , RULL(0x2E0F0100), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_14_PPM_GPMMR_SCOM1                                    , RULL(0x2E0F0101), SH_UNT_C_14     , SH_ACS_SCOM1     );
+REG64( C_14_PPM_GPMMR_SCOM2                                    , RULL(0x2E0F0102), SH_UNT_C_14     , SH_ACS_SCOM2     );
+REG64( C_15_PPM_GPMMR_SCOM                                     , RULL(0x2F0F0100), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_15_PPM_GPMMR_SCOM1                                    , RULL(0x2F0F0101), SH_UNT_C_15     , SH_ACS_SCOM1     );
+REG64( C_15_PPM_GPMMR_SCOM2                                    , RULL(0x2F0F0102), SH_UNT_C_15     , SH_ACS_SCOM2     );
+REG64( C_16_PPM_GPMMR_SCOM                                     , RULL(0x300F0100), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_16_PPM_GPMMR_SCOM1                                    , RULL(0x300F0101), SH_UNT_C_16     , SH_ACS_SCOM1     );
+REG64( C_16_PPM_GPMMR_SCOM2                                    , RULL(0x300F0102), SH_UNT_C_16     , SH_ACS_SCOM2     );
+REG64( C_17_PPM_GPMMR_SCOM                                     , RULL(0x310F0100), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_17_PPM_GPMMR_SCOM1                                    , RULL(0x310F0101), SH_UNT_C_17     , SH_ACS_SCOM1     );
+REG64( C_17_PPM_GPMMR_SCOM2                                    , RULL(0x310F0102), SH_UNT_C_17     , SH_ACS_SCOM2     );
+REG64( C_18_PPM_GPMMR_SCOM                                     , RULL(0x320F0100), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_18_PPM_GPMMR_SCOM1                                    , RULL(0x320F0101), SH_UNT_C_18     , SH_ACS_SCOM1     );
+REG64( C_18_PPM_GPMMR_SCOM2                                    , RULL(0x320F0102), SH_UNT_C_18     , SH_ACS_SCOM2     );
+REG64( C_19_PPM_GPMMR_SCOM                                     , RULL(0x330F0100), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_19_PPM_GPMMR_SCOM1                                    , RULL(0x330F0101), SH_UNT_C_19     , SH_ACS_SCOM1     );
+REG64( C_19_PPM_GPMMR_SCOM2                                    , RULL(0x330F0102), SH_UNT_C_19     , SH_ACS_SCOM2     );
+REG64( C_20_PPM_GPMMR_SCOM                                     , RULL(0x340F0100), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_20_PPM_GPMMR_SCOM1                                    , RULL(0x340F0101), SH_UNT_C_20     , SH_ACS_SCOM1     );
+REG64( C_20_PPM_GPMMR_SCOM2                                    , RULL(0x340F0102), SH_UNT_C_20     , SH_ACS_SCOM2     );
+REG64( C_21_PPM_GPMMR_SCOM                                     , RULL(0x350F0100), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_21_PPM_GPMMR_SCOM1                                    , RULL(0x350F0101), SH_UNT_C_21     , SH_ACS_SCOM1     );
+REG64( C_21_PPM_GPMMR_SCOM2                                    , RULL(0x350F0102), SH_UNT_C_21     , SH_ACS_SCOM2     );
+REG64( C_22_PPM_GPMMR_SCOM                                     , RULL(0x360F0100), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_22_PPM_GPMMR_SCOM1                                    , RULL(0x360F0101), SH_UNT_C_22     , SH_ACS_SCOM1     );
+REG64( C_22_PPM_GPMMR_SCOM2                                    , RULL(0x360F0102), SH_UNT_C_22     , SH_ACS_SCOM2     );
+REG64( C_23_PPM_GPMMR_SCOM                                     , RULL(0x370F0100), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( C_23_PPM_GPMMR_SCOM1                                    , RULL(0x370F0101), SH_UNT_C_23     , SH_ACS_SCOM1     );
+REG64( C_23_PPM_GPMMR_SCOM2                                    , RULL(0x370F0102), SH_UNT_C_23     , SH_ACS_SCOM2     );
+REG64( EQ_PPM_GPMMR_SCOM                                       , RULL(0x100F0100), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_PPM_GPMMR_SCOM1                                      , RULL(0x100F0101), SH_UNT_EQ       , SH_ACS_SCOM1     );
+REG64( EQ_PPM_GPMMR_SCOM2                                      , RULL(0x100F0102), SH_UNT_EQ       , SH_ACS_SCOM2     );
+REG64( EQ_0_PPM_GPMMR_SCOM                                     , RULL(0x100F0100), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_0_PPM_GPMMR_SCOM1                                    , RULL(0x100F0101), SH_UNT_EQ_0     , SH_ACS_SCOM1     );
+REG64( EQ_0_PPM_GPMMR_SCOM2                                    , RULL(0x100F0102), SH_UNT_EQ_0     , SH_ACS_SCOM2     );
+REG64( EQ_1_PPM_GPMMR_SCOM                                     , RULL(0x110F0100), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_1_PPM_GPMMR_SCOM1                                    , RULL(0x110F0101), SH_UNT_EQ_1     , SH_ACS_SCOM1     );
+REG64( EQ_1_PPM_GPMMR_SCOM2                                    , RULL(0x110F0102), SH_UNT_EQ_1     , SH_ACS_SCOM2     );
+REG64( EQ_2_PPM_GPMMR_SCOM                                     , RULL(0x120F0100), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_2_PPM_GPMMR_SCOM1                                    , RULL(0x120F0101), SH_UNT_EQ_2     , SH_ACS_SCOM1     );
+REG64( EQ_2_PPM_GPMMR_SCOM2                                    , RULL(0x120F0102), SH_UNT_EQ_2     , SH_ACS_SCOM2     );
+REG64( EQ_3_PPM_GPMMR_SCOM                                     , RULL(0x130F0100), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_3_PPM_GPMMR_SCOM1                                    , RULL(0x130F0101), SH_UNT_EQ_3     , SH_ACS_SCOM1     );
+REG64( EQ_3_PPM_GPMMR_SCOM2                                    , RULL(0x130F0102), SH_UNT_EQ_3     , SH_ACS_SCOM2     );
+REG64( EQ_4_PPM_GPMMR_SCOM                                     , RULL(0x140F0100), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_4_PPM_GPMMR_SCOM1                                    , RULL(0x140F0101), SH_UNT_EQ_4     , SH_ACS_SCOM1     );
+REG64( EQ_4_PPM_GPMMR_SCOM2                                    , RULL(0x140F0102), SH_UNT_EQ_4     , SH_ACS_SCOM2     );
+REG64( EQ_5_PPM_GPMMR_SCOM                                     , RULL(0x150F0100), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EQ_5_PPM_GPMMR_SCOM1                                    , RULL(0x150F0101), SH_UNT_EQ_5     , SH_ACS_SCOM1     );
+REG64( EQ_5_PPM_GPMMR_SCOM2                                    , RULL(0x150F0102), SH_UNT_EQ_5     , SH_ACS_SCOM2     );
+REG64( EX_PPM_GPMMR_SCOM                                       , RULL(0x200F0100), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0100,
+REG64( EX_PPM_GPMMR_SCOM1                                      , RULL(0x200F0101), SH_UNT_EX       ,
+       SH_ACS_SCOM1     ); //DUPS: 210F0101,
+REG64( EX_PPM_GPMMR_SCOM2                                      , RULL(0x200F0102), SH_UNT_EX       ,
+       SH_ACS_SCOM2     ); //DUPS: 210F0102,
+REG64( EX_0_PPM_GPMMR_SCOM                                     , RULL(0x200F0100), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0100,
+REG64( EX_0_PPM_GPMMR_SCOM1                                    , RULL(0x200F0101), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1     ); //DUPS: 210F0101,
+REG64( EX_0_PPM_GPMMR_SCOM2                                    , RULL(0x200F0102), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2     ); //DUPS: 210F0102,
+REG64( EX_1_PPM_GPMMR_SCOM                                     , RULL(0x230F0100), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0100,
+REG64( EX_1_PPM_GPMMR_SCOM1                                    , RULL(0x230F0101), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1     ); //DUPS: 220F0101,
+REG64( EX_1_PPM_GPMMR_SCOM2                                    , RULL(0x230F0102), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2     ); //DUPS: 220F0102,
+REG64( EX_2_PPM_GPMMR_SCOM                                     , RULL(0x240F0100), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0100,
+REG64( EX_2_PPM_GPMMR_SCOM1                                    , RULL(0x240F0101), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1     ); //DUPS: 250F0101,
+REG64( EX_2_PPM_GPMMR_SCOM2                                    , RULL(0x240F0102), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2     ); //DUPS: 250F0102,
+REG64( EX_3_PPM_GPMMR_SCOM                                     , RULL(0x260F0100), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0100,
+REG64( EX_3_PPM_GPMMR_SCOM1                                    , RULL(0x260F0101), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1     ); //DUPS: 270F0101,
+REG64( EX_3_PPM_GPMMR_SCOM2                                    , RULL(0x260F0102), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2     ); //DUPS: 270F0102,
+REG64( EX_4_PPM_GPMMR_SCOM                                     , RULL(0x280F0100), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0100,
+REG64( EX_4_PPM_GPMMR_SCOM1                                    , RULL(0x280F0101), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1     ); //DUPS: 290F0101,
+REG64( EX_4_PPM_GPMMR_SCOM2                                    , RULL(0x280F0102), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2     ); //DUPS: 290F0102,
+REG64( EX_5_PPM_GPMMR_SCOM                                     , RULL(0x2A0F0100), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0100,
+REG64( EX_5_PPM_GPMMR_SCOM1                                    , RULL(0x2A0F0101), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1     ); //DUPS: 2B0F0101,
+REG64( EX_5_PPM_GPMMR_SCOM2                                    , RULL(0x2A0F0102), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2     ); //DUPS: 2B0F0102,
+REG64( EX_6_PPM_GPMMR_SCOM                                     , RULL(0x2C0F0100), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0100,
+REG64( EX_6_PPM_GPMMR_SCOM1                                    , RULL(0x2C0F0101), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1     ); //DUPS: 2D0F0101,
+REG64( EX_6_PPM_GPMMR_SCOM2                                    , RULL(0x2C0F0102), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2     ); //DUPS: 2D0F0102,
+REG64( EX_7_PPM_GPMMR_SCOM                                     , RULL(0x2E0F0100), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0100,
+REG64( EX_7_PPM_GPMMR_SCOM1                                    , RULL(0x2E0F0101), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1     ); //DUPS: 2F0F0101,
+REG64( EX_7_PPM_GPMMR_SCOM2                                    , RULL(0x2E0F0102), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2     ); //DUPS: 2F0F0102,
+REG64( EX_8_PPM_GPMMR_SCOM                                     , RULL(0x300F0100), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0100,
+REG64( EX_8_PPM_GPMMR_SCOM1                                    , RULL(0x300F0101), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1     ); //DUPS: 310F0101,
+REG64( EX_8_PPM_GPMMR_SCOM2                                    , RULL(0x300F0102), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2     ); //DUPS: 310F0102,
+REG64( EX_9_PPM_GPMMR_SCOM                                     , RULL(0x320F0100), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0100,
+REG64( EX_9_PPM_GPMMR_SCOM1                                    , RULL(0x320F0101), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1     ); //DUPS: 330F0101,
+REG64( EX_9_PPM_GPMMR_SCOM2                                    , RULL(0x320F0102), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2     ); //DUPS: 330F0102,
+REG64( EX_10_PPM_GPMMR_SCOM                                    , RULL(0x340F0100), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0100,
+REG64( EX_10_PPM_GPMMR_SCOM1                                   , RULL(0x340F0101), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1     ); //DUPS: 350F0101,
+REG64( EX_10_PPM_GPMMR_SCOM2                                   , RULL(0x340F0102), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2     ); //DUPS: 350F0102,
+REG64( EX_11_PPM_GPMMR_SCOM                                    , RULL(0x360F0100), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0100,
+REG64( EX_11_PPM_GPMMR_SCOM1                                   , RULL(0x360F0101), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1     ); //DUPS: 370F0101,
+REG64( EX_11_PPM_GPMMR_SCOM2                                   , RULL(0x360F0102), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2     ); //DUPS: 370F0102,
+
+REG64( C_PPM_IVRMAVR                                           , RULL(0x200F01B5), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_PPM_IVRMAVR                                         , RULL(0x200F01B5), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_PPM_IVRMAVR                                         , RULL(0x210F01B5), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_PPM_IVRMAVR                                         , RULL(0x220F01B5), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_PPM_IVRMAVR                                         , RULL(0x230F01B5), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_PPM_IVRMAVR                                         , RULL(0x240F01B5), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_PPM_IVRMAVR                                         , RULL(0x250F01B5), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_PPM_IVRMAVR                                         , RULL(0x260F01B5), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_PPM_IVRMAVR                                         , RULL(0x270F01B5), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_PPM_IVRMAVR                                         , RULL(0x280F01B5), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_PPM_IVRMAVR                                         , RULL(0x290F01B5), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_PPM_IVRMAVR                                        , RULL(0x2A0F01B5), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_PPM_IVRMAVR                                        , RULL(0x2B0F01B5), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_PPM_IVRMAVR                                        , RULL(0x2C0F01B5), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_PPM_IVRMAVR                                        , RULL(0x2D0F01B5), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_PPM_IVRMAVR                                        , RULL(0x2E0F01B5), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_PPM_IVRMAVR                                        , RULL(0x2F0F01B5), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_PPM_IVRMAVR                                        , RULL(0x300F01B5), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_PPM_IVRMAVR                                        , RULL(0x310F01B5), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_PPM_IVRMAVR                                        , RULL(0x320F01B5), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_PPM_IVRMAVR                                        , RULL(0x330F01B5), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_PPM_IVRMAVR                                        , RULL(0x340F01B5), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_PPM_IVRMAVR                                        , RULL(0x350F01B5), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_PPM_IVRMAVR                                        , RULL(0x360F01B5), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_PPM_IVRMAVR                                        , RULL(0x370F01B5), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EQ_PPM_IVRMAVR                                          , RULL(0x100F01B5), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_PPM_IVRMAVR                                        , RULL(0x100F01B5), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_PPM_IVRMAVR                                        , RULL(0x110F01B5), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_PPM_IVRMAVR                                        , RULL(0x120F01B5), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_PPM_IVRMAVR                                        , RULL(0x130F01B5), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_PPM_IVRMAVR                                        , RULL(0x140F01B5), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_PPM_IVRMAVR                                        , RULL(0x150F01B5), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_PPM_IVRMAVR                                          , RULL(0x200F01B5), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F01B5,
+REG64( EX_0_PPM_IVRMAVR                                        , RULL(0x200F01B5), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F01B5,
+REG64( EX_1_PPM_IVRMAVR                                        , RULL(0x230F01B5), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 220F01B5,
+REG64( EX_2_PPM_IVRMAVR                                        , RULL(0x240F01B5), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 250F01B5,
+REG64( EX_3_PPM_IVRMAVR                                        , RULL(0x260F01B5), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 270F01B5,
+REG64( EX_4_PPM_IVRMAVR                                        , RULL(0x280F01B5), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 290F01B5,
+REG64( EX_5_PPM_IVRMAVR                                        , RULL(0x2A0F01B5), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B0F01B5,
+REG64( EX_6_PPM_IVRMAVR                                        , RULL(0x2C0F01B5), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D0F01B5,
+REG64( EX_7_PPM_IVRMAVR                                        , RULL(0x2E0F01B5), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F0F01B5,
+REG64( EX_8_PPM_IVRMAVR                                        , RULL(0x300F01B5), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 310F01B5,
+REG64( EX_9_PPM_IVRMAVR                                        , RULL(0x320F01B5), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 330F01B5,
+REG64( EX_10_PPM_IVRMAVR                                       , RULL(0x340F01B5), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 350F01B5,
+REG64( EX_11_PPM_IVRMAVR                                       , RULL(0x360F01B5), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 370F01B5,
+
+REG64( C_PPM_IVRMCR                                            , RULL(0x200F01B0), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_PPM_IVRMCR_CLEAR                                      , RULL(0x200F01B1), SH_UNT_C        ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_PPM_IVRMCR_OR                                         , RULL(0x200F01B2), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_PPM_IVRMCR                                          , RULL(0x200F01B0), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_PPM_IVRMCR_CLEAR                                    , RULL(0x200F01B1), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_0_PPM_IVRMCR_OR                                       , RULL(0x200F01B2), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_PPM_IVRMCR                                          , RULL(0x210F01B0), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_PPM_IVRMCR_CLEAR                                    , RULL(0x210F01B1), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_1_PPM_IVRMCR_OR                                       , RULL(0x210F01B2), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_PPM_IVRMCR                                          , RULL(0x220F01B0), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_PPM_IVRMCR_CLEAR                                    , RULL(0x220F01B1), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_2_PPM_IVRMCR_OR                                       , RULL(0x220F01B2), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_PPM_IVRMCR                                          , RULL(0x230F01B0), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_PPM_IVRMCR_CLEAR                                    , RULL(0x230F01B1), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_3_PPM_IVRMCR_OR                                       , RULL(0x230F01B2), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_PPM_IVRMCR                                          , RULL(0x240F01B0), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_PPM_IVRMCR_CLEAR                                    , RULL(0x240F01B1), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_4_PPM_IVRMCR_OR                                       , RULL(0x240F01B2), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_PPM_IVRMCR                                          , RULL(0x250F01B0), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_PPM_IVRMCR_CLEAR                                    , RULL(0x250F01B1), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_5_PPM_IVRMCR_OR                                       , RULL(0x250F01B2), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_PPM_IVRMCR                                          , RULL(0x260F01B0), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_PPM_IVRMCR_CLEAR                                    , RULL(0x260F01B1), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_6_PPM_IVRMCR_OR                                       , RULL(0x260F01B2), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_PPM_IVRMCR                                          , RULL(0x270F01B0), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_PPM_IVRMCR_CLEAR                                    , RULL(0x270F01B1), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_7_PPM_IVRMCR_OR                                       , RULL(0x270F01B2), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_PPM_IVRMCR                                          , RULL(0x280F01B0), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_PPM_IVRMCR_CLEAR                                    , RULL(0x280F01B1), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_8_PPM_IVRMCR_OR                                       , RULL(0x280F01B2), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_PPM_IVRMCR                                          , RULL(0x290F01B0), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_PPM_IVRMCR_CLEAR                                    , RULL(0x290F01B1), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_9_PPM_IVRMCR_OR                                       , RULL(0x290F01B2), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_PPM_IVRMCR                                         , RULL(0x2A0F01B0), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_PPM_IVRMCR_CLEAR                                   , RULL(0x2A0F01B1), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_10_PPM_IVRMCR_OR                                      , RULL(0x2A0F01B2), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_PPM_IVRMCR                                         , RULL(0x2B0F01B0), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_PPM_IVRMCR_CLEAR                                   , RULL(0x2B0F01B1), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_11_PPM_IVRMCR_OR                                      , RULL(0x2B0F01B2), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_PPM_IVRMCR                                         , RULL(0x2C0F01B0), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_PPM_IVRMCR_CLEAR                                   , RULL(0x2C0F01B1), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_12_PPM_IVRMCR_OR                                      , RULL(0x2C0F01B2), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_PPM_IVRMCR                                         , RULL(0x2D0F01B0), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_PPM_IVRMCR_CLEAR                                   , RULL(0x2D0F01B1), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_13_PPM_IVRMCR_OR                                      , RULL(0x2D0F01B2), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_PPM_IVRMCR                                         , RULL(0x2E0F01B0), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_PPM_IVRMCR_CLEAR                                   , RULL(0x2E0F01B1), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_14_PPM_IVRMCR_OR                                      , RULL(0x2E0F01B2), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_PPM_IVRMCR                                         , RULL(0x2F0F01B0), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_PPM_IVRMCR_CLEAR                                   , RULL(0x2F0F01B1), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_15_PPM_IVRMCR_OR                                      , RULL(0x2F0F01B2), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_PPM_IVRMCR                                         , RULL(0x300F01B0), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_PPM_IVRMCR_CLEAR                                   , RULL(0x300F01B1), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_16_PPM_IVRMCR_OR                                      , RULL(0x300F01B2), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_PPM_IVRMCR                                         , RULL(0x310F01B0), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_PPM_IVRMCR_CLEAR                                   , RULL(0x310F01B1), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_17_PPM_IVRMCR_OR                                      , RULL(0x310F01B2), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_PPM_IVRMCR                                         , RULL(0x320F01B0), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_PPM_IVRMCR_CLEAR                                   , RULL(0x320F01B1), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_18_PPM_IVRMCR_OR                                      , RULL(0x320F01B2), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_PPM_IVRMCR                                         , RULL(0x330F01B0), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_PPM_IVRMCR_CLEAR                                   , RULL(0x330F01B1), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_19_PPM_IVRMCR_OR                                      , RULL(0x330F01B2), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_PPM_IVRMCR                                         , RULL(0x340F01B0), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_PPM_IVRMCR_CLEAR                                   , RULL(0x340F01B1), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_20_PPM_IVRMCR_OR                                      , RULL(0x340F01B2), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_PPM_IVRMCR                                         , RULL(0x350F01B0), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_PPM_IVRMCR_CLEAR                                   , RULL(0x350F01B1), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_21_PPM_IVRMCR_OR                                      , RULL(0x350F01B2), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_PPM_IVRMCR                                         , RULL(0x360F01B0), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_PPM_IVRMCR_CLEAR                                   , RULL(0x360F01B1), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_22_PPM_IVRMCR_OR                                      , RULL(0x360F01B2), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_PPM_IVRMCR                                         , RULL(0x370F01B0), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_PPM_IVRMCR_CLEAR                                   , RULL(0x370F01B1), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_23_PPM_IVRMCR_OR                                      , RULL(0x370F01B2), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EQ_PPM_IVRMCR                                           , RULL(0x100F01B0), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_PPM_IVRMCR_CLEAR                                     , RULL(0x100F01B1), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_PPM_IVRMCR_OR                                        , RULL(0x100F01B2), SH_UNT_EQ       , SH_ACS_SCOM2_OR  );
+REG64( EQ_0_PPM_IVRMCR                                         , RULL(0x100F01B0), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_0_PPM_IVRMCR_CLEAR                                   , RULL(0x100F01B1), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_0_PPM_IVRMCR_OR                                      , RULL(0x100F01B2), SH_UNT_EQ_0     , SH_ACS_SCOM2_OR  );
+REG64( EQ_1_PPM_IVRMCR                                         , RULL(0x110F01B0), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_PPM_IVRMCR_CLEAR                                   , RULL(0x110F01B1), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_1_PPM_IVRMCR_OR                                      , RULL(0x110F01B2), SH_UNT_EQ_1     , SH_ACS_SCOM2_OR  );
+REG64( EQ_2_PPM_IVRMCR                                         , RULL(0x120F01B0), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_PPM_IVRMCR_CLEAR                                   , RULL(0x120F01B1), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_2_PPM_IVRMCR_OR                                      , RULL(0x120F01B2), SH_UNT_EQ_2     , SH_ACS_SCOM2_OR  );
+REG64( EQ_3_PPM_IVRMCR                                         , RULL(0x130F01B0), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_PPM_IVRMCR_CLEAR                                   , RULL(0x130F01B1), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_3_PPM_IVRMCR_OR                                      , RULL(0x130F01B2), SH_UNT_EQ_3     , SH_ACS_SCOM2_OR  );
+REG64( EQ_4_PPM_IVRMCR                                         , RULL(0x140F01B0), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_PPM_IVRMCR_CLEAR                                   , RULL(0x140F01B1), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_4_PPM_IVRMCR_OR                                      , RULL(0x140F01B2), SH_UNT_EQ_4     , SH_ACS_SCOM2_OR  );
+REG64( EQ_5_PPM_IVRMCR                                         , RULL(0x150F01B0), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_PPM_IVRMCR_CLEAR                                   , RULL(0x150F01B1), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_5_PPM_IVRMCR_OR                                      , RULL(0x150F01B2), SH_UNT_EQ_5     , SH_ACS_SCOM2_OR  );
+REG64( EX_PPM_IVRMCR                                           , RULL(0x200F01B0), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01B0,
+REG64( EX_PPM_IVRMCR_CLEAR                                     , RULL(0x200F01B1), SH_UNT_EX       ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F01B1,
+REG64( EX_PPM_IVRMCR_OR                                        , RULL(0x200F01B2), SH_UNT_EX       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F01B2,
+REG64( EX_0_PPM_IVRMCR                                         , RULL(0x200F01B0), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01B0,
+REG64( EX_0_PPM_IVRMCR_CLEAR                                   , RULL(0x200F01B1), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F01B1,
+REG64( EX_0_PPM_IVRMCR_OR                                      , RULL(0x200F01B2), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F01B2,
+REG64( EX_1_PPM_IVRMCR                                         , RULL(0x230F01B0), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F01B0,
+REG64( EX_1_PPM_IVRMCR_CLEAR                                   , RULL(0x230F01B1), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 220F01B1,
+REG64( EX_1_PPM_IVRMCR_OR                                      , RULL(0x230F01B2), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 220F01B2,
+REG64( EX_2_PPM_IVRMCR                                         , RULL(0x240F01B0), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F01B0,
+REG64( EX_2_PPM_IVRMCR_CLEAR                                   , RULL(0x240F01B1), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 250F01B1,
+REG64( EX_2_PPM_IVRMCR_OR                                      , RULL(0x240F01B2), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 250F01B2,
+REG64( EX_3_PPM_IVRMCR                                         , RULL(0x260F01B0), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F01B0,
+REG64( EX_3_PPM_IVRMCR_CLEAR                                   , RULL(0x260F01B1), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 270F01B1,
+REG64( EX_3_PPM_IVRMCR_OR                                      , RULL(0x260F01B2), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 270F01B2,
+REG64( EX_4_PPM_IVRMCR                                         , RULL(0x280F01B0), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F01B0,
+REG64( EX_4_PPM_IVRMCR_CLEAR                                   , RULL(0x280F01B1), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 290F01B1,
+REG64( EX_4_PPM_IVRMCR_OR                                      , RULL(0x280F01B2), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 290F01B2,
+REG64( EX_5_PPM_IVRMCR                                         , RULL(0x2A0F01B0), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F01B0,
+REG64( EX_5_PPM_IVRMCR_CLEAR                                   , RULL(0x2A0F01B1), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2B0F01B1,
+REG64( EX_5_PPM_IVRMCR_OR                                      , RULL(0x2A0F01B2), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2B0F01B2,
+REG64( EX_6_PPM_IVRMCR                                         , RULL(0x2C0F01B0), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F01B0,
+REG64( EX_6_PPM_IVRMCR_CLEAR                                   , RULL(0x2C0F01B1), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2D0F01B1,
+REG64( EX_6_PPM_IVRMCR_OR                                      , RULL(0x2C0F01B2), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2D0F01B2,
+REG64( EX_7_PPM_IVRMCR                                         , RULL(0x2E0F01B0), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F01B0,
+REG64( EX_7_PPM_IVRMCR_CLEAR                                   , RULL(0x2E0F01B1), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2F0F01B1,
+REG64( EX_7_PPM_IVRMCR_OR                                      , RULL(0x2E0F01B2), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2F0F01B2,
+REG64( EX_8_PPM_IVRMCR                                         , RULL(0x300F01B0), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F01B0,
+REG64( EX_8_PPM_IVRMCR_CLEAR                                   , RULL(0x300F01B1), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 310F01B1,
+REG64( EX_8_PPM_IVRMCR_OR                                      , RULL(0x300F01B2), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 310F01B2,
+REG64( EX_9_PPM_IVRMCR                                         , RULL(0x320F01B0), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F01B0,
+REG64( EX_9_PPM_IVRMCR_CLEAR                                   , RULL(0x320F01B1), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 330F01B1,
+REG64( EX_9_PPM_IVRMCR_OR                                      , RULL(0x320F01B2), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 330F01B2,
+REG64( EX_10_PPM_IVRMCR                                        , RULL(0x340F01B0), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F01B0,
+REG64( EX_10_PPM_IVRMCR_CLEAR                                  , RULL(0x340F01B1), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 350F01B1,
+REG64( EX_10_PPM_IVRMCR_OR                                     , RULL(0x340F01B2), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 350F01B2,
+REG64( EX_11_PPM_IVRMCR                                        , RULL(0x360F01B0), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F01B0,
+REG64( EX_11_PPM_IVRMCR_CLEAR                                  , RULL(0x360F01B1), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 370F01B1,
+REG64( EX_11_PPM_IVRMCR_OR                                     , RULL(0x360F01B2), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 370F01B2,
+
+REG64( C_PPM_IVRMDVR                                           , RULL(0x200F01B4), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_PPM_IVRMDVR                                         , RULL(0x200F01B4), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_PPM_IVRMDVR                                         , RULL(0x210F01B4), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_PPM_IVRMDVR                                         , RULL(0x220F01B4), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_PPM_IVRMDVR                                         , RULL(0x230F01B4), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_PPM_IVRMDVR                                         , RULL(0x240F01B4), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_PPM_IVRMDVR                                         , RULL(0x250F01B4), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_PPM_IVRMDVR                                         , RULL(0x260F01B4), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_PPM_IVRMDVR                                         , RULL(0x270F01B4), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_PPM_IVRMDVR                                         , RULL(0x280F01B4), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_PPM_IVRMDVR                                         , RULL(0x290F01B4), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_PPM_IVRMDVR                                        , RULL(0x2A0F01B4), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_PPM_IVRMDVR                                        , RULL(0x2B0F01B4), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_PPM_IVRMDVR                                        , RULL(0x2C0F01B4), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_PPM_IVRMDVR                                        , RULL(0x2D0F01B4), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_PPM_IVRMDVR                                        , RULL(0x2E0F01B4), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_PPM_IVRMDVR                                        , RULL(0x2F0F01B4), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_PPM_IVRMDVR                                        , RULL(0x300F01B4), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_PPM_IVRMDVR                                        , RULL(0x310F01B4), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_PPM_IVRMDVR                                        , RULL(0x320F01B4), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_PPM_IVRMDVR                                        , RULL(0x330F01B4), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_PPM_IVRMDVR                                        , RULL(0x340F01B4), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_PPM_IVRMDVR                                        , RULL(0x350F01B4), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_PPM_IVRMDVR                                        , RULL(0x360F01B4), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_PPM_IVRMDVR                                        , RULL(0x370F01B4), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_PPM_IVRMDVR                                          , RULL(0x100F01B4), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_PPM_IVRMDVR                                        , RULL(0x100F01B4), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_PPM_IVRMDVR                                        , RULL(0x110F01B4), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_PPM_IVRMDVR                                        , RULL(0x120F01B4), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_PPM_IVRMDVR                                        , RULL(0x130F01B4), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_PPM_IVRMDVR                                        , RULL(0x140F01B4), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_PPM_IVRMDVR                                        , RULL(0x150F01B4), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_PPM_IVRMDVR                                          , RULL(0x200F01B4), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01B4,
+REG64( EX_0_PPM_IVRMDVR                                        , RULL(0x200F01B4), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01B4,
+REG64( EX_1_PPM_IVRMDVR                                        , RULL(0x230F01B4), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F01B4,
+REG64( EX_2_PPM_IVRMDVR                                        , RULL(0x240F01B4), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F01B4,
+REG64( EX_3_PPM_IVRMDVR                                        , RULL(0x260F01B4), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F01B4,
+REG64( EX_4_PPM_IVRMDVR                                        , RULL(0x280F01B4), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F01B4,
+REG64( EX_5_PPM_IVRMDVR                                        , RULL(0x2A0F01B4), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F01B4,
+REG64( EX_6_PPM_IVRMDVR                                        , RULL(0x2C0F01B4), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F01B4,
+REG64( EX_7_PPM_IVRMDVR                                        , RULL(0x2E0F01B4), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F01B4,
+REG64( EX_8_PPM_IVRMDVR                                        , RULL(0x300F01B4), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F01B4,
+REG64( EX_9_PPM_IVRMDVR                                        , RULL(0x320F01B4), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F01B4,
+REG64( EX_10_PPM_IVRMDVR                                       , RULL(0x340F01B4), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F01B4,
+REG64( EX_11_PPM_IVRMDVR                                       , RULL(0x360F01B4), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F01B4,
+
+REG64( C_PPM_IVRMST                                            , RULL(0x200F01B3), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_PPM_IVRMST                                          , RULL(0x200F01B3), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_PPM_IVRMST                                          , RULL(0x210F01B3), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_PPM_IVRMST                                          , RULL(0x220F01B3), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_PPM_IVRMST                                          , RULL(0x230F01B3), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_PPM_IVRMST                                          , RULL(0x240F01B3), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_PPM_IVRMST                                          , RULL(0x250F01B3), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_PPM_IVRMST                                          , RULL(0x260F01B3), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_PPM_IVRMST                                          , RULL(0x270F01B3), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_PPM_IVRMST                                          , RULL(0x280F01B3), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_PPM_IVRMST                                          , RULL(0x290F01B3), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_PPM_IVRMST                                         , RULL(0x2A0F01B3), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_PPM_IVRMST                                         , RULL(0x2B0F01B3), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_PPM_IVRMST                                         , RULL(0x2C0F01B3), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_PPM_IVRMST                                         , RULL(0x2D0F01B3), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_PPM_IVRMST                                         , RULL(0x2E0F01B3), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_PPM_IVRMST                                         , RULL(0x2F0F01B3), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_PPM_IVRMST                                         , RULL(0x300F01B3), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_PPM_IVRMST                                         , RULL(0x310F01B3), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_PPM_IVRMST                                         , RULL(0x320F01B3), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_PPM_IVRMST                                         , RULL(0x330F01B3), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_PPM_IVRMST                                         , RULL(0x340F01B3), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_PPM_IVRMST                                         , RULL(0x350F01B3), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_PPM_IVRMST                                         , RULL(0x360F01B3), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_PPM_IVRMST                                         , RULL(0x370F01B3), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EQ_PPM_IVRMST                                           , RULL(0x100F01B3), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_PPM_IVRMST                                         , RULL(0x100F01B3), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_PPM_IVRMST                                         , RULL(0x110F01B3), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_PPM_IVRMST                                         , RULL(0x120F01B3), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_PPM_IVRMST                                         , RULL(0x130F01B3), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_PPM_IVRMST                                         , RULL(0x140F01B3), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_PPM_IVRMST                                         , RULL(0x150F01B3), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_PPM_IVRMST                                           , RULL(0x200F01B3), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F01B3,
+REG64( EX_0_PPM_IVRMST                                         , RULL(0x200F01B3), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F01B3,
+REG64( EX_1_PPM_IVRMST                                         , RULL(0x230F01B3), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 220F01B3,
+REG64( EX_2_PPM_IVRMST                                         , RULL(0x240F01B3), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 250F01B3,
+REG64( EX_3_PPM_IVRMST                                         , RULL(0x260F01B3), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 270F01B3,
+REG64( EX_4_PPM_IVRMST                                         , RULL(0x280F01B3), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 290F01B3,
+REG64( EX_5_PPM_IVRMST                                         , RULL(0x2A0F01B3), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B0F01B3,
+REG64( EX_6_PPM_IVRMST                                         , RULL(0x2C0F01B3), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D0F01B3,
+REG64( EX_7_PPM_IVRMST                                         , RULL(0x2E0F01B3), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F0F01B3,
+REG64( EX_8_PPM_IVRMST                                         , RULL(0x300F01B3), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 310F01B3,
+REG64( EX_9_PPM_IVRMST                                         , RULL(0x320F01B3), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 330F01B3,
+REG64( EX_10_PPM_IVRMST                                        , RULL(0x340F01B3), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 350F01B3,
+REG64( EX_11_PPM_IVRMST                                        , RULL(0x360F01B3), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 370F01B3,
+
+REG64( C_PPM_PFCS_SCOM                                         , RULL(0x200F0118), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_PPM_PFCS_SCOM1                                        , RULL(0x200F0119), SH_UNT_C        , SH_ACS_SCOM1     );
+REG64( C_PPM_PFCS_SCOM2                                        , RULL(0x200F011A), SH_UNT_C        , SH_ACS_SCOM2     );
+REG64( C_0_PPM_PFCS_SCOM                                       , RULL(0x200F0118), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_0_PPM_PFCS_SCOM1                                      , RULL(0x200F0119), SH_UNT_C_0      , SH_ACS_SCOM1     );
+REG64( C_0_PPM_PFCS_SCOM2                                      , RULL(0x200F011A), SH_UNT_C_0      , SH_ACS_SCOM2     );
+REG64( C_1_PPM_PFCS_SCOM                                       , RULL(0x210F0118), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_1_PPM_PFCS_SCOM1                                      , RULL(0x210F0119), SH_UNT_C_1      , SH_ACS_SCOM1     );
+REG64( C_1_PPM_PFCS_SCOM2                                      , RULL(0x210F011A), SH_UNT_C_1      , SH_ACS_SCOM2     );
+REG64( C_2_PPM_PFCS_SCOM                                       , RULL(0x220F0118), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_2_PPM_PFCS_SCOM1                                      , RULL(0x220F0119), SH_UNT_C_2      , SH_ACS_SCOM1     );
+REG64( C_2_PPM_PFCS_SCOM2                                      , RULL(0x220F011A), SH_UNT_C_2      , SH_ACS_SCOM2     );
+REG64( C_3_PPM_PFCS_SCOM                                       , RULL(0x230F0118), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_3_PPM_PFCS_SCOM1                                      , RULL(0x230F0119), SH_UNT_C_3      , SH_ACS_SCOM1     );
+REG64( C_3_PPM_PFCS_SCOM2                                      , RULL(0x230F011A), SH_UNT_C_3      , SH_ACS_SCOM2     );
+REG64( C_4_PPM_PFCS_SCOM                                       , RULL(0x240F0118), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_4_PPM_PFCS_SCOM1                                      , RULL(0x240F0119), SH_UNT_C_4      , SH_ACS_SCOM1     );
+REG64( C_4_PPM_PFCS_SCOM2                                      , RULL(0x240F011A), SH_UNT_C_4      , SH_ACS_SCOM2     );
+REG64( C_5_PPM_PFCS_SCOM                                       , RULL(0x250F0118), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_5_PPM_PFCS_SCOM1                                      , RULL(0x250F0119), SH_UNT_C_5      , SH_ACS_SCOM1     );
+REG64( C_5_PPM_PFCS_SCOM2                                      , RULL(0x250F011A), SH_UNT_C_5      , SH_ACS_SCOM2     );
+REG64( C_6_PPM_PFCS_SCOM                                       , RULL(0x260F0118), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_6_PPM_PFCS_SCOM1                                      , RULL(0x260F0119), SH_UNT_C_6      , SH_ACS_SCOM1     );
+REG64( C_6_PPM_PFCS_SCOM2                                      , RULL(0x260F011A), SH_UNT_C_6      , SH_ACS_SCOM2     );
+REG64( C_7_PPM_PFCS_SCOM                                       , RULL(0x270F0118), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_7_PPM_PFCS_SCOM1                                      , RULL(0x270F0119), SH_UNT_C_7      , SH_ACS_SCOM1     );
+REG64( C_7_PPM_PFCS_SCOM2                                      , RULL(0x270F011A), SH_UNT_C_7      , SH_ACS_SCOM2     );
+REG64( C_8_PPM_PFCS_SCOM                                       , RULL(0x280F0118), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_8_PPM_PFCS_SCOM1                                      , RULL(0x280F0119), SH_UNT_C_8      , SH_ACS_SCOM1     );
+REG64( C_8_PPM_PFCS_SCOM2                                      , RULL(0x280F011A), SH_UNT_C_8      , SH_ACS_SCOM2     );
+REG64( C_9_PPM_PFCS_SCOM                                       , RULL(0x290F0118), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_9_PPM_PFCS_SCOM1                                      , RULL(0x290F0119), SH_UNT_C_9      , SH_ACS_SCOM1     );
+REG64( C_9_PPM_PFCS_SCOM2                                      , RULL(0x290F011A), SH_UNT_C_9      , SH_ACS_SCOM2     );
+REG64( C_10_PPM_PFCS_SCOM                                      , RULL(0x2A0F0118), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_10_PPM_PFCS_SCOM1                                     , RULL(0x2A0F0119), SH_UNT_C_10     , SH_ACS_SCOM1     );
+REG64( C_10_PPM_PFCS_SCOM2                                     , RULL(0x2A0F011A), SH_UNT_C_10     , SH_ACS_SCOM2     );
+REG64( C_11_PPM_PFCS_SCOM                                      , RULL(0x2B0F0118), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_11_PPM_PFCS_SCOM1                                     , RULL(0x2B0F0119), SH_UNT_C_11     , SH_ACS_SCOM1     );
+REG64( C_11_PPM_PFCS_SCOM2                                     , RULL(0x2B0F011A), SH_UNT_C_11     , SH_ACS_SCOM2     );
+REG64( C_12_PPM_PFCS_SCOM                                      , RULL(0x2C0F0118), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_12_PPM_PFCS_SCOM1                                     , RULL(0x2C0F0119), SH_UNT_C_12     , SH_ACS_SCOM1     );
+REG64( C_12_PPM_PFCS_SCOM2                                     , RULL(0x2C0F011A), SH_UNT_C_12     , SH_ACS_SCOM2     );
+REG64( C_13_PPM_PFCS_SCOM                                      , RULL(0x2D0F0118), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_13_PPM_PFCS_SCOM1                                     , RULL(0x2D0F0119), SH_UNT_C_13     , SH_ACS_SCOM1     );
+REG64( C_13_PPM_PFCS_SCOM2                                     , RULL(0x2D0F011A), SH_UNT_C_13     , SH_ACS_SCOM2     );
+REG64( C_14_PPM_PFCS_SCOM                                      , RULL(0x2E0F0118), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_14_PPM_PFCS_SCOM1                                     , RULL(0x2E0F0119), SH_UNT_C_14     , SH_ACS_SCOM1     );
+REG64( C_14_PPM_PFCS_SCOM2                                     , RULL(0x2E0F011A), SH_UNT_C_14     , SH_ACS_SCOM2     );
+REG64( C_15_PPM_PFCS_SCOM                                      , RULL(0x2F0F0118), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_15_PPM_PFCS_SCOM1                                     , RULL(0x2F0F0119), SH_UNT_C_15     , SH_ACS_SCOM1     );
+REG64( C_15_PPM_PFCS_SCOM2                                     , RULL(0x2F0F011A), SH_UNT_C_15     , SH_ACS_SCOM2     );
+REG64( C_16_PPM_PFCS_SCOM                                      , RULL(0x300F0118), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_16_PPM_PFCS_SCOM1                                     , RULL(0x300F0119), SH_UNT_C_16     , SH_ACS_SCOM1     );
+REG64( C_16_PPM_PFCS_SCOM2                                     , RULL(0x300F011A), SH_UNT_C_16     , SH_ACS_SCOM2     );
+REG64( C_17_PPM_PFCS_SCOM                                      , RULL(0x310F0118), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_17_PPM_PFCS_SCOM1                                     , RULL(0x310F0119), SH_UNT_C_17     , SH_ACS_SCOM1     );
+REG64( C_17_PPM_PFCS_SCOM2                                     , RULL(0x310F011A), SH_UNT_C_17     , SH_ACS_SCOM2     );
+REG64( C_18_PPM_PFCS_SCOM                                      , RULL(0x320F0118), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_18_PPM_PFCS_SCOM1                                     , RULL(0x320F0119), SH_UNT_C_18     , SH_ACS_SCOM1     );
+REG64( C_18_PPM_PFCS_SCOM2                                     , RULL(0x320F011A), SH_UNT_C_18     , SH_ACS_SCOM2     );
+REG64( C_19_PPM_PFCS_SCOM                                      , RULL(0x330F0118), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_19_PPM_PFCS_SCOM1                                     , RULL(0x330F0119), SH_UNT_C_19     , SH_ACS_SCOM1     );
+REG64( C_19_PPM_PFCS_SCOM2                                     , RULL(0x330F011A), SH_UNT_C_19     , SH_ACS_SCOM2     );
+REG64( C_20_PPM_PFCS_SCOM                                      , RULL(0x340F0118), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_20_PPM_PFCS_SCOM1                                     , RULL(0x340F0119), SH_UNT_C_20     , SH_ACS_SCOM1     );
+REG64( C_20_PPM_PFCS_SCOM2                                     , RULL(0x340F011A), SH_UNT_C_20     , SH_ACS_SCOM2     );
+REG64( C_21_PPM_PFCS_SCOM                                      , RULL(0x350F0118), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_21_PPM_PFCS_SCOM1                                     , RULL(0x350F0119), SH_UNT_C_21     , SH_ACS_SCOM1     );
+REG64( C_21_PPM_PFCS_SCOM2                                     , RULL(0x350F011A), SH_UNT_C_21     , SH_ACS_SCOM2     );
+REG64( C_22_PPM_PFCS_SCOM                                      , RULL(0x360F0118), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_22_PPM_PFCS_SCOM1                                     , RULL(0x360F0119), SH_UNT_C_22     , SH_ACS_SCOM1     );
+REG64( C_22_PPM_PFCS_SCOM2                                     , RULL(0x360F011A), SH_UNT_C_22     , SH_ACS_SCOM2     );
+REG64( C_23_PPM_PFCS_SCOM                                      , RULL(0x370F0118), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( C_23_PPM_PFCS_SCOM1                                     , RULL(0x370F0119), SH_UNT_C_23     , SH_ACS_SCOM1     );
+REG64( C_23_PPM_PFCS_SCOM2                                     , RULL(0x370F011A), SH_UNT_C_23     , SH_ACS_SCOM2     );
+REG64( EQ_PPM_PFCS_SCOM                                        , RULL(0x100F0118), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_PPM_PFCS_SCOM1                                       , RULL(0x100F0119), SH_UNT_EQ       , SH_ACS_SCOM1     );
+REG64( EQ_PPM_PFCS_SCOM2                                       , RULL(0x100F011A), SH_UNT_EQ       , SH_ACS_SCOM2     );
+REG64( EQ_0_PPM_PFCS_SCOM                                      , RULL(0x100F0118), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_0_PPM_PFCS_SCOM1                                     , RULL(0x100F0119), SH_UNT_EQ_0     , SH_ACS_SCOM1     );
+REG64( EQ_0_PPM_PFCS_SCOM2                                     , RULL(0x100F011A), SH_UNT_EQ_0     , SH_ACS_SCOM2     );
+REG64( EQ_1_PPM_PFCS_SCOM                                      , RULL(0x110F0118), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_1_PPM_PFCS_SCOM1                                     , RULL(0x110F0119), SH_UNT_EQ_1     , SH_ACS_SCOM1     );
+REG64( EQ_1_PPM_PFCS_SCOM2                                     , RULL(0x110F011A), SH_UNT_EQ_1     , SH_ACS_SCOM2     );
+REG64( EQ_2_PPM_PFCS_SCOM                                      , RULL(0x120F0118), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_2_PPM_PFCS_SCOM1                                     , RULL(0x120F0119), SH_UNT_EQ_2     , SH_ACS_SCOM1     );
+REG64( EQ_2_PPM_PFCS_SCOM2                                     , RULL(0x120F011A), SH_UNT_EQ_2     , SH_ACS_SCOM2     );
+REG64( EQ_3_PPM_PFCS_SCOM                                      , RULL(0x130F0118), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_3_PPM_PFCS_SCOM1                                     , RULL(0x130F0119), SH_UNT_EQ_3     , SH_ACS_SCOM1     );
+REG64( EQ_3_PPM_PFCS_SCOM2                                     , RULL(0x130F011A), SH_UNT_EQ_3     , SH_ACS_SCOM2     );
+REG64( EQ_4_PPM_PFCS_SCOM                                      , RULL(0x140F0118), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_4_PPM_PFCS_SCOM1                                     , RULL(0x140F0119), SH_UNT_EQ_4     , SH_ACS_SCOM1     );
+REG64( EQ_4_PPM_PFCS_SCOM2                                     , RULL(0x140F011A), SH_UNT_EQ_4     , SH_ACS_SCOM2     );
+REG64( EQ_5_PPM_PFCS_SCOM                                      , RULL(0x150F0118), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EQ_5_PPM_PFCS_SCOM1                                     , RULL(0x150F0119), SH_UNT_EQ_5     , SH_ACS_SCOM1     );
+REG64( EQ_5_PPM_PFCS_SCOM2                                     , RULL(0x150F011A), SH_UNT_EQ_5     , SH_ACS_SCOM2     );
+REG64( EX_PPM_PFCS_SCOM                                        , RULL(0x200F0118), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0118,
+REG64( EX_PPM_PFCS_SCOM1                                       , RULL(0x200F0119), SH_UNT_EX       ,
+       SH_ACS_SCOM1     ); //DUPS: 210F0119,
+REG64( EX_PPM_PFCS_SCOM2                                       , RULL(0x200F011A), SH_UNT_EX       ,
+       SH_ACS_SCOM2     ); //DUPS: 210F011A,
+REG64( EX_0_PPM_PFCS_SCOM                                      , RULL(0x200F0118), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0118,
+REG64( EX_0_PPM_PFCS_SCOM1                                     , RULL(0x200F0119), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1     ); //DUPS: 210F0119,
+REG64( EX_0_PPM_PFCS_SCOM2                                     , RULL(0x200F011A), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2     ); //DUPS: 210F011A,
+REG64( EX_1_PPM_PFCS_SCOM                                      , RULL(0x230F0118), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0118,
+REG64( EX_1_PPM_PFCS_SCOM1                                     , RULL(0x230F0119), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1     ); //DUPS: 220F0119,
+REG64( EX_1_PPM_PFCS_SCOM2                                     , RULL(0x230F011A), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2     ); //DUPS: 220F011A,
+REG64( EX_2_PPM_PFCS_SCOM                                      , RULL(0x240F0118), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0118,
+REG64( EX_2_PPM_PFCS_SCOM1                                     , RULL(0x240F0119), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1     ); //DUPS: 250F0119,
+REG64( EX_2_PPM_PFCS_SCOM2                                     , RULL(0x240F011A), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2     ); //DUPS: 250F011A,
+REG64( EX_3_PPM_PFCS_SCOM                                      , RULL(0x260F0118), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0118,
+REG64( EX_3_PPM_PFCS_SCOM1                                     , RULL(0x260F0119), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1     ); //DUPS: 270F0119,
+REG64( EX_3_PPM_PFCS_SCOM2                                     , RULL(0x260F011A), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2     ); //DUPS: 270F011A,
+REG64( EX_4_PPM_PFCS_SCOM                                      , RULL(0x280F0118), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0118,
+REG64( EX_4_PPM_PFCS_SCOM1                                     , RULL(0x280F0119), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1     ); //DUPS: 290F0119,
+REG64( EX_4_PPM_PFCS_SCOM2                                     , RULL(0x280F011A), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2     ); //DUPS: 290F011A,
+REG64( EX_5_PPM_PFCS_SCOM                                      , RULL(0x2A0F0118), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0118,
+REG64( EX_5_PPM_PFCS_SCOM1                                     , RULL(0x2A0F0119), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1     ); //DUPS: 2B0F0119,
+REG64( EX_5_PPM_PFCS_SCOM2                                     , RULL(0x2A0F011A), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2     ); //DUPS: 2B0F011A,
+REG64( EX_6_PPM_PFCS_SCOM                                      , RULL(0x2C0F0118), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0118,
+REG64( EX_6_PPM_PFCS_SCOM1                                     , RULL(0x2C0F0119), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1     ); //DUPS: 2D0F0119,
+REG64( EX_6_PPM_PFCS_SCOM2                                     , RULL(0x2C0F011A), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2     ); //DUPS: 2D0F011A,
+REG64( EX_7_PPM_PFCS_SCOM                                      , RULL(0x2E0F0118), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0118,
+REG64( EX_7_PPM_PFCS_SCOM1                                     , RULL(0x2E0F0119), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1     ); //DUPS: 2F0F0119,
+REG64( EX_7_PPM_PFCS_SCOM2                                     , RULL(0x2E0F011A), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2     ); //DUPS: 2F0F011A,
+REG64( EX_8_PPM_PFCS_SCOM                                      , RULL(0x300F0118), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0118,
+REG64( EX_8_PPM_PFCS_SCOM1                                     , RULL(0x300F0119), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1     ); //DUPS: 310F0119,
+REG64( EX_8_PPM_PFCS_SCOM2                                     , RULL(0x300F011A), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2     ); //DUPS: 310F011A,
+REG64( EX_9_PPM_PFCS_SCOM                                      , RULL(0x320F0118), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0118,
+REG64( EX_9_PPM_PFCS_SCOM1                                     , RULL(0x320F0119), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1     ); //DUPS: 330F0119,
+REG64( EX_9_PPM_PFCS_SCOM2                                     , RULL(0x320F011A), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2     ); //DUPS: 330F011A,
+REG64( EX_10_PPM_PFCS_SCOM                                     , RULL(0x340F0118), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0118,
+REG64( EX_10_PPM_PFCS_SCOM1                                    , RULL(0x340F0119), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1     ); //DUPS: 350F0119,
+REG64( EX_10_PPM_PFCS_SCOM2                                    , RULL(0x340F011A), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2     ); //DUPS: 350F011A,
+REG64( EX_11_PPM_PFCS_SCOM                                     , RULL(0x360F0118), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0118,
+REG64( EX_11_PPM_PFCS_SCOM1                                    , RULL(0x360F0119), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1     ); //DUPS: 370F0119,
+REG64( EX_11_PPM_PFCS_SCOM2                                    , RULL(0x360F011A), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2     ); //DUPS: 370F011A,
+
+REG64( C_PPM_PFDLY                                             , RULL(0x200F011B), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_PPM_PFDLY                                           , RULL(0x200F011B), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_PPM_PFDLY                                           , RULL(0x210F011B), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_PPM_PFDLY                                           , RULL(0x220F011B), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_PPM_PFDLY                                           , RULL(0x230F011B), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_PPM_PFDLY                                           , RULL(0x240F011B), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_PPM_PFDLY                                           , RULL(0x250F011B), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_PPM_PFDLY                                           , RULL(0x260F011B), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_PPM_PFDLY                                           , RULL(0x270F011B), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_PPM_PFDLY                                           , RULL(0x280F011B), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_PPM_PFDLY                                           , RULL(0x290F011B), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_PPM_PFDLY                                          , RULL(0x2A0F011B), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_PPM_PFDLY                                          , RULL(0x2B0F011B), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_PPM_PFDLY                                          , RULL(0x2C0F011B), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_PPM_PFDLY                                          , RULL(0x2D0F011B), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_PPM_PFDLY                                          , RULL(0x2E0F011B), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_PPM_PFDLY                                          , RULL(0x2F0F011B), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_PPM_PFDLY                                          , RULL(0x300F011B), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_PPM_PFDLY                                          , RULL(0x310F011B), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_PPM_PFDLY                                          , RULL(0x320F011B), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_PPM_PFDLY                                          , RULL(0x330F011B), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_PPM_PFDLY                                          , RULL(0x340F011B), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_PPM_PFDLY                                          , RULL(0x350F011B), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_PPM_PFDLY                                          , RULL(0x360F011B), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_PPM_PFDLY                                          , RULL(0x370F011B), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_PPM_PFDLY                                            , RULL(0x100F011B), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_PPM_PFDLY                                          , RULL(0x100F011B), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_PPM_PFDLY                                          , RULL(0x110F011B), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_PPM_PFDLY                                          , RULL(0x120F011B), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_PPM_PFDLY                                          , RULL(0x130F011B), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_PPM_PFDLY                                          , RULL(0x140F011B), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_PPM_PFDLY                                          , RULL(0x150F011B), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_PPM_PFDLY                                            , RULL(0x200F011B), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F011B,
+REG64( EX_0_PPM_PFDLY                                          , RULL(0x200F011B), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F011B,
+REG64( EX_1_PPM_PFDLY                                          , RULL(0x230F011B), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F011B,
+REG64( EX_2_PPM_PFDLY                                          , RULL(0x240F011B), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F011B,
+REG64( EX_3_PPM_PFDLY                                          , RULL(0x260F011B), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F011B,
+REG64( EX_4_PPM_PFDLY                                          , RULL(0x280F011B), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F011B,
+REG64( EX_5_PPM_PFDLY                                          , RULL(0x2A0F011B), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F011B,
+REG64( EX_6_PPM_PFDLY                                          , RULL(0x2C0F011B), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F011B,
+REG64( EX_7_PPM_PFDLY                                          , RULL(0x2E0F011B), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F011B,
+REG64( EX_8_PPM_PFDLY                                          , RULL(0x300F011B), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F011B,
+REG64( EX_9_PPM_PFDLY                                          , RULL(0x320F011B), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F011B,
+REG64( EX_10_PPM_PFDLY                                         , RULL(0x340F011B), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F011B,
+REG64( EX_11_PPM_PFDLY                                         , RULL(0x360F011B), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F011B,
+
+REG64( C_PPM_PFOFF                                             , RULL(0x200F011D), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_PPM_PFOFF                                           , RULL(0x200F011D), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_PPM_PFOFF                                           , RULL(0x210F011D), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_PPM_PFOFF                                           , RULL(0x220F011D), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_PPM_PFOFF                                           , RULL(0x230F011D), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_PPM_PFOFF                                           , RULL(0x240F011D), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_PPM_PFOFF                                           , RULL(0x250F011D), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_PPM_PFOFF                                           , RULL(0x260F011D), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_PPM_PFOFF                                           , RULL(0x270F011D), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_PPM_PFOFF                                           , RULL(0x280F011D), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_PPM_PFOFF                                           , RULL(0x290F011D), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_PPM_PFOFF                                          , RULL(0x2A0F011D), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_PPM_PFOFF                                          , RULL(0x2B0F011D), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_PPM_PFOFF                                          , RULL(0x2C0F011D), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_PPM_PFOFF                                          , RULL(0x2D0F011D), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_PPM_PFOFF                                          , RULL(0x2E0F011D), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_PPM_PFOFF                                          , RULL(0x2F0F011D), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_PPM_PFOFF                                          , RULL(0x300F011D), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_PPM_PFOFF                                          , RULL(0x310F011D), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_PPM_PFOFF                                          , RULL(0x320F011D), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_PPM_PFOFF                                          , RULL(0x330F011D), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_PPM_PFOFF                                          , RULL(0x340F011D), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_PPM_PFOFF                                          , RULL(0x350F011D), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_PPM_PFOFF                                          , RULL(0x360F011D), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_PPM_PFOFF                                          , RULL(0x370F011D), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_PPM_PFOFF                                            , RULL(0x100F011D), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_PPM_PFOFF                                          , RULL(0x100F011D), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_PPM_PFOFF                                          , RULL(0x110F011D), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_PPM_PFOFF                                          , RULL(0x120F011D), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_PPM_PFOFF                                          , RULL(0x130F011D), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_PPM_PFOFF                                          , RULL(0x140F011D), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_PPM_PFOFF                                          , RULL(0x150F011D), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_PPM_PFOFF                                            , RULL(0x200F011D), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F011D,
+REG64( EX_0_PPM_PFOFF                                          , RULL(0x200F011D), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F011D,
+REG64( EX_1_PPM_PFOFF                                          , RULL(0x230F011D), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F011D,
+REG64( EX_2_PPM_PFOFF                                          , RULL(0x240F011D), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F011D,
+REG64( EX_3_PPM_PFOFF                                          , RULL(0x260F011D), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F011D,
+REG64( EX_4_PPM_PFOFF                                          , RULL(0x280F011D), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F011D,
+REG64( EX_5_PPM_PFOFF                                          , RULL(0x2A0F011D), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F011D,
+REG64( EX_6_PPM_PFOFF                                          , RULL(0x2C0F011D), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F011D,
+REG64( EX_7_PPM_PFOFF                                          , RULL(0x2E0F011D), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F011D,
+REG64( EX_8_PPM_PFOFF                                          , RULL(0x300F011D), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F011D,
+REG64( EX_9_PPM_PFOFF                                          , RULL(0x320F011D), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F011D,
+REG64( EX_10_PPM_PFOFF                                         , RULL(0x340F011D), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F011D,
+REG64( EX_11_PPM_PFOFF                                         , RULL(0x360F011D), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F011D,
+
+REG64( C_PPM_PFSNS                                             , RULL(0x200F011C), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_PPM_PFSNS                                           , RULL(0x200F011C), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_PPM_PFSNS                                           , RULL(0x210F011C), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_PPM_PFSNS                                           , RULL(0x220F011C), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_PPM_PFSNS                                           , RULL(0x230F011C), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_PPM_PFSNS                                           , RULL(0x240F011C), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_PPM_PFSNS                                           , RULL(0x250F011C), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_PPM_PFSNS                                           , RULL(0x260F011C), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_PPM_PFSNS                                           , RULL(0x270F011C), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_PPM_PFSNS                                           , RULL(0x280F011C), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_PPM_PFSNS                                           , RULL(0x290F011C), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_PPM_PFSNS                                          , RULL(0x2A0F011C), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_PPM_PFSNS                                          , RULL(0x2B0F011C), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_PPM_PFSNS                                          , RULL(0x2C0F011C), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_PPM_PFSNS                                          , RULL(0x2D0F011C), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_PPM_PFSNS                                          , RULL(0x2E0F011C), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_PPM_PFSNS                                          , RULL(0x2F0F011C), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_PPM_PFSNS                                          , RULL(0x300F011C), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_PPM_PFSNS                                          , RULL(0x310F011C), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_PPM_PFSNS                                          , RULL(0x320F011C), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_PPM_PFSNS                                          , RULL(0x330F011C), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_PPM_PFSNS                                          , RULL(0x340F011C), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_PPM_PFSNS                                          , RULL(0x350F011C), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_PPM_PFSNS                                          , RULL(0x360F011C), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_PPM_PFSNS                                          , RULL(0x370F011C), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EQ_PPM_PFSNS                                            , RULL(0x100F011C), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_PPM_PFSNS                                          , RULL(0x100F011C), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_PPM_PFSNS                                          , RULL(0x110F011C), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_PPM_PFSNS                                          , RULL(0x120F011C), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_PPM_PFSNS                                          , RULL(0x130F011C), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_PPM_PFSNS                                          , RULL(0x140F011C), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_PPM_PFSNS                                          , RULL(0x150F011C), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_PPM_PFSNS                                            , RULL(0x200F011C), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F011C,
+REG64( EX_0_PPM_PFSNS                                          , RULL(0x200F011C), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F011C,
+REG64( EX_1_PPM_PFSNS                                          , RULL(0x230F011C), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 220F011C,
+REG64( EX_2_PPM_PFSNS                                          , RULL(0x240F011C), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 250F011C,
+REG64( EX_3_PPM_PFSNS                                          , RULL(0x260F011C), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 270F011C,
+REG64( EX_4_PPM_PFSNS                                          , RULL(0x280F011C), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 290F011C,
+REG64( EX_5_PPM_PFSNS                                          , RULL(0x2A0F011C), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B0F011C,
+REG64( EX_6_PPM_PFSNS                                          , RULL(0x2C0F011C), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D0F011C,
+REG64( EX_7_PPM_PFSNS                                          , RULL(0x2E0F011C), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F0F011C,
+REG64( EX_8_PPM_PFSNS                                          , RULL(0x300F011C), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 310F011C,
+REG64( EX_9_PPM_PFSNS                                          , RULL(0x320F011C), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 330F011C,
+REG64( EX_10_PPM_PFSNS                                         , RULL(0x340F011C), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 350F011C,
+REG64( EX_11_PPM_PFSNS                                         , RULL(0x360F011C), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 370F011C,
+
+REG64( C_PPM_PIG                                               , RULL(0x200F0180), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_PPM_PIG                                             , RULL(0x200F0180), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_PPM_PIG                                             , RULL(0x210F0180), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_PPM_PIG                                             , RULL(0x220F0180), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_PPM_PIG                                             , RULL(0x230F0180), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_PPM_PIG                                             , RULL(0x240F0180), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_PPM_PIG                                             , RULL(0x250F0180), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_PPM_PIG                                             , RULL(0x260F0180), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_PPM_PIG                                             , RULL(0x270F0180), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_PPM_PIG                                             , RULL(0x280F0180), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_PPM_PIG                                             , RULL(0x290F0180), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_PPM_PIG                                            , RULL(0x2A0F0180), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_PPM_PIG                                            , RULL(0x2B0F0180), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_PPM_PIG                                            , RULL(0x2C0F0180), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_PPM_PIG                                            , RULL(0x2D0F0180), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_PPM_PIG                                            , RULL(0x2E0F0180), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_PPM_PIG                                            , RULL(0x2F0F0180), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_PPM_PIG                                            , RULL(0x300F0180), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_PPM_PIG                                            , RULL(0x310F0180), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_PPM_PIG                                            , RULL(0x320F0180), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_PPM_PIG                                            , RULL(0x330F0180), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_PPM_PIG                                            , RULL(0x340F0180), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_PPM_PIG                                            , RULL(0x350F0180), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_PPM_PIG                                            , RULL(0x360F0180), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_PPM_PIG                                            , RULL(0x370F0180), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_PPM_PIG                                              , RULL(0x100F0180), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_PPM_PIG                                            , RULL(0x100F0180), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_PPM_PIG                                            , RULL(0x110F0180), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_PPM_PIG                                            , RULL(0x120F0180), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_PPM_PIG                                            , RULL(0x130F0180), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_PPM_PIG                                            , RULL(0x140F0180), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_PPM_PIG                                            , RULL(0x150F0180), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_PPM_PIG                                              , RULL(0x200F0180), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0180,
+REG64( EX_0_PPM_PIG                                            , RULL(0x200F0180), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0180,
+REG64( EX_1_PPM_PIG                                            , RULL(0x230F0180), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0180,
+REG64( EX_2_PPM_PIG                                            , RULL(0x240F0180), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0180,
+REG64( EX_3_PPM_PIG                                            , RULL(0x260F0180), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0180,
+REG64( EX_4_PPM_PIG                                            , RULL(0x280F0180), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0180,
+REG64( EX_5_PPM_PIG                                            , RULL(0x2A0F0180), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0180,
+REG64( EX_6_PPM_PIG                                            , RULL(0x2C0F0180), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0180,
+REG64( EX_7_PPM_PIG                                            , RULL(0x2E0F0180), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0180,
+REG64( EX_8_PPM_PIG                                            , RULL(0x300F0180), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0180,
+REG64( EX_9_PPM_PIG                                            , RULL(0x320F0180), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0180,
+REG64( EX_10_PPM_PIG                                           , RULL(0x340F0180), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0180,
+REG64( EX_11_PPM_PIG                                           , RULL(0x360F0180), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0180,
+
+REG64( C_PPM_SCRATCH0                                          , RULL(0x200F011E), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_PPM_SCRATCH0                                        , RULL(0x200F011E), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_PPM_SCRATCH0                                        , RULL(0x210F011E), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_PPM_SCRATCH0                                        , RULL(0x220F011E), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_PPM_SCRATCH0                                        , RULL(0x230F011E), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_PPM_SCRATCH0                                        , RULL(0x240F011E), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_PPM_SCRATCH0                                        , RULL(0x250F011E), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_PPM_SCRATCH0                                        , RULL(0x260F011E), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_PPM_SCRATCH0                                        , RULL(0x270F011E), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_PPM_SCRATCH0                                        , RULL(0x280F011E), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_PPM_SCRATCH0                                        , RULL(0x290F011E), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_PPM_SCRATCH0                                       , RULL(0x2A0F011E), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_PPM_SCRATCH0                                       , RULL(0x2B0F011E), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_PPM_SCRATCH0                                       , RULL(0x2C0F011E), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_PPM_SCRATCH0                                       , RULL(0x2D0F011E), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_PPM_SCRATCH0                                       , RULL(0x2E0F011E), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_PPM_SCRATCH0                                       , RULL(0x2F0F011E), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_PPM_SCRATCH0                                       , RULL(0x300F011E), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_PPM_SCRATCH0                                       , RULL(0x310F011E), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_PPM_SCRATCH0                                       , RULL(0x320F011E), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_PPM_SCRATCH0                                       , RULL(0x330F011E), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_PPM_SCRATCH0                                       , RULL(0x340F011E), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_PPM_SCRATCH0                                       , RULL(0x350F011E), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_PPM_SCRATCH0                                       , RULL(0x360F011E), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_PPM_SCRATCH0                                       , RULL(0x370F011E), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_PPM_SCRATCH0                                         , RULL(0x100F011E), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_PPM_SCRATCH0                                       , RULL(0x100F011E), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_PPM_SCRATCH0                                       , RULL(0x110F011E), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_PPM_SCRATCH0                                       , RULL(0x120F011E), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_PPM_SCRATCH0                                       , RULL(0x130F011E), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_PPM_SCRATCH0                                       , RULL(0x140F011E), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_PPM_SCRATCH0                                       , RULL(0x150F011E), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_PPM_SCRATCH0                                         , RULL(0x200F011E), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F011E,
+REG64( EX_0_PPM_SCRATCH0                                       , RULL(0x200F011E), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F011E,
+REG64( EX_1_PPM_SCRATCH0                                       , RULL(0x230F011E), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F011E,
+REG64( EX_2_PPM_SCRATCH0                                       , RULL(0x240F011E), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F011E,
+REG64( EX_3_PPM_SCRATCH0                                       , RULL(0x260F011E), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F011E,
+REG64( EX_4_PPM_SCRATCH0                                       , RULL(0x280F011E), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F011E,
+REG64( EX_5_PPM_SCRATCH0                                       , RULL(0x2A0F011E), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F011E,
+REG64( EX_6_PPM_SCRATCH0                                       , RULL(0x2C0F011E), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F011E,
+REG64( EX_7_PPM_SCRATCH0                                       , RULL(0x2E0F011E), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F011E,
+REG64( EX_8_PPM_SCRATCH0                                       , RULL(0x300F011E), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F011E,
+REG64( EX_9_PPM_SCRATCH0                                       , RULL(0x320F011E), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F011E,
+REG64( EX_10_PPM_SCRATCH0                                      , RULL(0x340F011E), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F011E,
+REG64( EX_11_PPM_SCRATCH0                                      , RULL(0x360F011E), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F011E,
+
+REG64( C_PPM_SCRATCH1                                          , RULL(0x200F011F), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_PPM_SCRATCH1                                        , RULL(0x200F011F), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_PPM_SCRATCH1                                        , RULL(0x210F011F), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_PPM_SCRATCH1                                        , RULL(0x220F011F), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_PPM_SCRATCH1                                        , RULL(0x230F011F), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_PPM_SCRATCH1                                        , RULL(0x240F011F), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_PPM_SCRATCH1                                        , RULL(0x250F011F), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_PPM_SCRATCH1                                        , RULL(0x260F011F), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_PPM_SCRATCH1                                        , RULL(0x270F011F), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_PPM_SCRATCH1                                        , RULL(0x280F011F), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_PPM_SCRATCH1                                        , RULL(0x290F011F), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_PPM_SCRATCH1                                       , RULL(0x2A0F011F), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_PPM_SCRATCH1                                       , RULL(0x2B0F011F), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_PPM_SCRATCH1                                       , RULL(0x2C0F011F), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_PPM_SCRATCH1                                       , RULL(0x2D0F011F), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_PPM_SCRATCH1                                       , RULL(0x2E0F011F), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_PPM_SCRATCH1                                       , RULL(0x2F0F011F), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_PPM_SCRATCH1                                       , RULL(0x300F011F), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_PPM_SCRATCH1                                       , RULL(0x310F011F), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_PPM_SCRATCH1                                       , RULL(0x320F011F), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_PPM_SCRATCH1                                       , RULL(0x330F011F), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_PPM_SCRATCH1                                       , RULL(0x340F011F), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_PPM_SCRATCH1                                       , RULL(0x350F011F), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_PPM_SCRATCH1                                       , RULL(0x360F011F), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_PPM_SCRATCH1                                       , RULL(0x370F011F), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_PPM_SCRATCH1                                         , RULL(0x100F011F), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_PPM_SCRATCH1                                       , RULL(0x100F011F), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_PPM_SCRATCH1                                       , RULL(0x110F011F), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_PPM_SCRATCH1                                       , RULL(0x120F011F), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_PPM_SCRATCH1                                       , RULL(0x130F011F), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_PPM_SCRATCH1                                       , RULL(0x140F011F), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_PPM_SCRATCH1                                       , RULL(0x150F011F), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_PPM_SCRATCH1                                         , RULL(0x200F011F), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F011F,
+REG64( EX_0_PPM_SCRATCH1                                       , RULL(0x200F011F), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F011F,
+REG64( EX_1_PPM_SCRATCH1                                       , RULL(0x230F011F), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F011F,
+REG64( EX_2_PPM_SCRATCH1                                       , RULL(0x240F011F), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F011F,
+REG64( EX_3_PPM_SCRATCH1                                       , RULL(0x260F011F), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F011F,
+REG64( EX_4_PPM_SCRATCH1                                       , RULL(0x280F011F), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F011F,
+REG64( EX_5_PPM_SCRATCH1                                       , RULL(0x2A0F011F), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F011F,
+REG64( EX_6_PPM_SCRATCH1                                       , RULL(0x2C0F011F), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F011F,
+REG64( EX_7_PPM_SCRATCH1                                       , RULL(0x2E0F011F), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F011F,
+REG64( EX_8_PPM_SCRATCH1                                       , RULL(0x300F011F), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F011F,
+REG64( EX_9_PPM_SCRATCH1                                       , RULL(0x320F011F), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F011F,
+REG64( EX_10_PPM_SCRATCH1                                      , RULL(0x340F011F), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F011F,
+REG64( EX_11_PPM_SCRATCH1                                      , RULL(0x360F011F), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F011F,
+
+REG64( C_PPM_SPWKUP_FSP                                        , RULL(0x200F010B), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_PPM_SPWKUP_FSP                                      , RULL(0x200F010B), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_PPM_SPWKUP_FSP                                      , RULL(0x210F010B), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_PPM_SPWKUP_FSP                                      , RULL(0x220F010B), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_PPM_SPWKUP_FSP                                      , RULL(0x230F010B), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_PPM_SPWKUP_FSP                                      , RULL(0x240F010B), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_PPM_SPWKUP_FSP                                      , RULL(0x250F010B), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_PPM_SPWKUP_FSP                                      , RULL(0x260F010B), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_PPM_SPWKUP_FSP                                      , RULL(0x270F010B), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_PPM_SPWKUP_FSP                                      , RULL(0x280F010B), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_PPM_SPWKUP_FSP                                      , RULL(0x290F010B), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_PPM_SPWKUP_FSP                                     , RULL(0x2A0F010B), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_PPM_SPWKUP_FSP                                     , RULL(0x2B0F010B), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_PPM_SPWKUP_FSP                                     , RULL(0x2C0F010B), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_PPM_SPWKUP_FSP                                     , RULL(0x2D0F010B), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_PPM_SPWKUP_FSP                                     , RULL(0x2E0F010B), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_PPM_SPWKUP_FSP                                     , RULL(0x2F0F010B), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_PPM_SPWKUP_FSP                                     , RULL(0x300F010B), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_PPM_SPWKUP_FSP                                     , RULL(0x310F010B), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_PPM_SPWKUP_FSP                                     , RULL(0x320F010B), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_PPM_SPWKUP_FSP                                     , RULL(0x330F010B), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_PPM_SPWKUP_FSP                                     , RULL(0x340F010B), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_PPM_SPWKUP_FSP                                     , RULL(0x350F010B), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_PPM_SPWKUP_FSP                                     , RULL(0x360F010B), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_PPM_SPWKUP_FSP                                     , RULL(0x370F010B), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_PPM_SPWKUP_FSP                                       , RULL(0x100F010B), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_PPM_SPWKUP_FSP                                     , RULL(0x100F010B), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_PPM_SPWKUP_FSP                                     , RULL(0x110F010B), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_PPM_SPWKUP_FSP                                     , RULL(0x120F010B), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_PPM_SPWKUP_FSP                                     , RULL(0x130F010B), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_PPM_SPWKUP_FSP                                     , RULL(0x140F010B), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_PPM_SPWKUP_FSP                                     , RULL(0x150F010B), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_PPM_SPWKUP_FSP                                       , RULL(0x200F010B), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F010B,
+REG64( EX_0_PPM_SPWKUP_FSP                                     , RULL(0x200F010B), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F010B,
+REG64( EX_1_PPM_SPWKUP_FSP                                     , RULL(0x230F010B), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F010B,
+REG64( EX_2_PPM_SPWKUP_FSP                                     , RULL(0x240F010B), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F010B,
+REG64( EX_3_PPM_SPWKUP_FSP                                     , RULL(0x260F010B), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F010B,
+REG64( EX_4_PPM_SPWKUP_FSP                                     , RULL(0x280F010B), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F010B,
+REG64( EX_5_PPM_SPWKUP_FSP                                     , RULL(0x2A0F010B), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F010B,
+REG64( EX_6_PPM_SPWKUP_FSP                                     , RULL(0x2C0F010B), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F010B,
+REG64( EX_7_PPM_SPWKUP_FSP                                     , RULL(0x2E0F010B), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F010B,
+REG64( EX_8_PPM_SPWKUP_FSP                                     , RULL(0x300F010B), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F010B,
+REG64( EX_9_PPM_SPWKUP_FSP                                     , RULL(0x320F010B), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F010B,
+REG64( EX_10_PPM_SPWKUP_FSP                                    , RULL(0x340F010B), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F010B,
+REG64( EX_11_PPM_SPWKUP_FSP                                    , RULL(0x360F010B), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F010B,
+
+REG64( C_PPM_SPWKUP_HYP                                        , RULL(0x200F010D), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_PPM_SPWKUP_HYP                                      , RULL(0x200F010D), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_PPM_SPWKUP_HYP                                      , RULL(0x210F010D), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_PPM_SPWKUP_HYP                                      , RULL(0x220F010D), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_PPM_SPWKUP_HYP                                      , RULL(0x230F010D), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_PPM_SPWKUP_HYP                                      , RULL(0x240F010D), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_PPM_SPWKUP_HYP                                      , RULL(0x250F010D), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_PPM_SPWKUP_HYP                                      , RULL(0x260F010D), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_PPM_SPWKUP_HYP                                      , RULL(0x270F010D), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_PPM_SPWKUP_HYP                                      , RULL(0x280F010D), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_PPM_SPWKUP_HYP                                      , RULL(0x290F010D), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_PPM_SPWKUP_HYP                                     , RULL(0x2A0F010D), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_PPM_SPWKUP_HYP                                     , RULL(0x2B0F010D), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_PPM_SPWKUP_HYP                                     , RULL(0x2C0F010D), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_PPM_SPWKUP_HYP                                     , RULL(0x2D0F010D), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_PPM_SPWKUP_HYP                                     , RULL(0x2E0F010D), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_PPM_SPWKUP_HYP                                     , RULL(0x2F0F010D), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_PPM_SPWKUP_HYP                                     , RULL(0x300F010D), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_PPM_SPWKUP_HYP                                     , RULL(0x310F010D), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_PPM_SPWKUP_HYP                                     , RULL(0x320F010D), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_PPM_SPWKUP_HYP                                     , RULL(0x330F010D), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_PPM_SPWKUP_HYP                                     , RULL(0x340F010D), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_PPM_SPWKUP_HYP                                     , RULL(0x350F010D), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_PPM_SPWKUP_HYP                                     , RULL(0x360F010D), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_PPM_SPWKUP_HYP                                     , RULL(0x370F010D), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_PPM_SPWKUP_HYP                                       , RULL(0x100F010D), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_PPM_SPWKUP_HYP                                     , RULL(0x100F010D), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_PPM_SPWKUP_HYP                                     , RULL(0x110F010D), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_PPM_SPWKUP_HYP                                     , RULL(0x120F010D), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_PPM_SPWKUP_HYP                                     , RULL(0x130F010D), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_PPM_SPWKUP_HYP                                     , RULL(0x140F010D), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_PPM_SPWKUP_HYP                                     , RULL(0x150F010D), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_PPM_SPWKUP_HYP                                       , RULL(0x200F010D), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F010D,
+REG64( EX_0_PPM_SPWKUP_HYP                                     , RULL(0x200F010D), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F010D,
+REG64( EX_1_PPM_SPWKUP_HYP                                     , RULL(0x230F010D), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F010D,
+REG64( EX_2_PPM_SPWKUP_HYP                                     , RULL(0x240F010D), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F010D,
+REG64( EX_3_PPM_SPWKUP_HYP                                     , RULL(0x260F010D), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F010D,
+REG64( EX_4_PPM_SPWKUP_HYP                                     , RULL(0x280F010D), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F010D,
+REG64( EX_5_PPM_SPWKUP_HYP                                     , RULL(0x2A0F010D), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F010D,
+REG64( EX_6_PPM_SPWKUP_HYP                                     , RULL(0x2C0F010D), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F010D,
+REG64( EX_7_PPM_SPWKUP_HYP                                     , RULL(0x2E0F010D), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F010D,
+REG64( EX_8_PPM_SPWKUP_HYP                                     , RULL(0x300F010D), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F010D,
+REG64( EX_9_PPM_SPWKUP_HYP                                     , RULL(0x320F010D), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F010D,
+REG64( EX_10_PPM_SPWKUP_HYP                                    , RULL(0x340F010D), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F010D,
+REG64( EX_11_PPM_SPWKUP_HYP                                    , RULL(0x360F010D), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F010D,
+
+REG64( C_PPM_SPWKUP_OCC                                        , RULL(0x200F010C), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_PPM_SPWKUP_OCC                                      , RULL(0x200F010C), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_PPM_SPWKUP_OCC                                      , RULL(0x210F010C), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_PPM_SPWKUP_OCC                                      , RULL(0x220F010C), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_PPM_SPWKUP_OCC                                      , RULL(0x230F010C), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_PPM_SPWKUP_OCC                                      , RULL(0x240F010C), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_PPM_SPWKUP_OCC                                      , RULL(0x250F010C), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_PPM_SPWKUP_OCC                                      , RULL(0x260F010C), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_PPM_SPWKUP_OCC                                      , RULL(0x270F010C), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_PPM_SPWKUP_OCC                                      , RULL(0x280F010C), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_PPM_SPWKUP_OCC                                      , RULL(0x290F010C), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_PPM_SPWKUP_OCC                                     , RULL(0x2A0F010C), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_PPM_SPWKUP_OCC                                     , RULL(0x2B0F010C), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_PPM_SPWKUP_OCC                                     , RULL(0x2C0F010C), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_PPM_SPWKUP_OCC                                     , RULL(0x2D0F010C), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_PPM_SPWKUP_OCC                                     , RULL(0x2E0F010C), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_PPM_SPWKUP_OCC                                     , RULL(0x2F0F010C), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_PPM_SPWKUP_OCC                                     , RULL(0x300F010C), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_PPM_SPWKUP_OCC                                     , RULL(0x310F010C), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_PPM_SPWKUP_OCC                                     , RULL(0x320F010C), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_PPM_SPWKUP_OCC                                     , RULL(0x330F010C), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_PPM_SPWKUP_OCC                                     , RULL(0x340F010C), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_PPM_SPWKUP_OCC                                     , RULL(0x350F010C), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_PPM_SPWKUP_OCC                                     , RULL(0x360F010C), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_PPM_SPWKUP_OCC                                     , RULL(0x370F010C), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_PPM_SPWKUP_OCC                                       , RULL(0x100F010C), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_PPM_SPWKUP_OCC                                     , RULL(0x100F010C), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_PPM_SPWKUP_OCC                                     , RULL(0x110F010C), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_PPM_SPWKUP_OCC                                     , RULL(0x120F010C), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_PPM_SPWKUP_OCC                                     , RULL(0x130F010C), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_PPM_SPWKUP_OCC                                     , RULL(0x140F010C), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_PPM_SPWKUP_OCC                                     , RULL(0x150F010C), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_PPM_SPWKUP_OCC                                       , RULL(0x200F010C), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F010C,
+REG64( EX_0_PPM_SPWKUP_OCC                                     , RULL(0x200F010C), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F010C,
+REG64( EX_1_PPM_SPWKUP_OCC                                     , RULL(0x230F010C), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F010C,
+REG64( EX_2_PPM_SPWKUP_OCC                                     , RULL(0x240F010C), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F010C,
+REG64( EX_3_PPM_SPWKUP_OCC                                     , RULL(0x260F010C), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F010C,
+REG64( EX_4_PPM_SPWKUP_OCC                                     , RULL(0x280F010C), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F010C,
+REG64( EX_5_PPM_SPWKUP_OCC                                     , RULL(0x2A0F010C), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F010C,
+REG64( EX_6_PPM_SPWKUP_OCC                                     , RULL(0x2C0F010C), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F010C,
+REG64( EX_7_PPM_SPWKUP_OCC                                     , RULL(0x2E0F010C), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F010C,
+REG64( EX_8_PPM_SPWKUP_OCC                                     , RULL(0x300F010C), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F010C,
+REG64( EX_9_PPM_SPWKUP_OCC                                     , RULL(0x320F010C), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F010C,
+REG64( EX_10_PPM_SPWKUP_OCC                                    , RULL(0x340F010C), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F010C,
+REG64( EX_11_PPM_SPWKUP_OCC                                    , RULL(0x360F010C), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F010C,
+
+REG64( C_PPM_SPWKUP_OTR                                        , RULL(0x200F010A), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_PPM_SPWKUP_OTR                                      , RULL(0x200F010A), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_PPM_SPWKUP_OTR                                      , RULL(0x210F010A), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_PPM_SPWKUP_OTR                                      , RULL(0x220F010A), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_PPM_SPWKUP_OTR                                      , RULL(0x230F010A), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_PPM_SPWKUP_OTR                                      , RULL(0x240F010A), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_PPM_SPWKUP_OTR                                      , RULL(0x250F010A), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_PPM_SPWKUP_OTR                                      , RULL(0x260F010A), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_PPM_SPWKUP_OTR                                      , RULL(0x270F010A), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_PPM_SPWKUP_OTR                                      , RULL(0x280F010A), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_PPM_SPWKUP_OTR                                      , RULL(0x290F010A), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_PPM_SPWKUP_OTR                                     , RULL(0x2A0F010A), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_PPM_SPWKUP_OTR                                     , RULL(0x2B0F010A), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_PPM_SPWKUP_OTR                                     , RULL(0x2C0F010A), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_PPM_SPWKUP_OTR                                     , RULL(0x2D0F010A), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_PPM_SPWKUP_OTR                                     , RULL(0x2E0F010A), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_PPM_SPWKUP_OTR                                     , RULL(0x2F0F010A), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_PPM_SPWKUP_OTR                                     , RULL(0x300F010A), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_PPM_SPWKUP_OTR                                     , RULL(0x310F010A), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_PPM_SPWKUP_OTR                                     , RULL(0x320F010A), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_PPM_SPWKUP_OTR                                     , RULL(0x330F010A), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_PPM_SPWKUP_OTR                                     , RULL(0x340F010A), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_PPM_SPWKUP_OTR                                     , RULL(0x350F010A), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_PPM_SPWKUP_OTR                                     , RULL(0x360F010A), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_PPM_SPWKUP_OTR                                     , RULL(0x370F010A), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EQ_PPM_SPWKUP_OTR                                       , RULL(0x100F010A), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_PPM_SPWKUP_OTR                                     , RULL(0x100F010A), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_PPM_SPWKUP_OTR                                     , RULL(0x110F010A), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_PPM_SPWKUP_OTR                                     , RULL(0x120F010A), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_PPM_SPWKUP_OTR                                     , RULL(0x130F010A), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_PPM_SPWKUP_OTR                                     , RULL(0x140F010A), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_PPM_SPWKUP_OTR                                     , RULL(0x150F010A), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EX_PPM_SPWKUP_OTR                                       , RULL(0x200F010A), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F010A,
+REG64( EX_0_PPM_SPWKUP_OTR                                     , RULL(0x200F010A), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F010A,
+REG64( EX_1_PPM_SPWKUP_OTR                                     , RULL(0x230F010A), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F010A,
+REG64( EX_2_PPM_SPWKUP_OTR                                     , RULL(0x240F010A), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F010A,
+REG64( EX_3_PPM_SPWKUP_OTR                                     , RULL(0x260F010A), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F010A,
+REG64( EX_4_PPM_SPWKUP_OTR                                     , RULL(0x280F010A), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F010A,
+REG64( EX_5_PPM_SPWKUP_OTR                                     , RULL(0x2A0F010A), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F010A,
+REG64( EX_6_PPM_SPWKUP_OTR                                     , RULL(0x2C0F010A), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F010A,
+REG64( EX_7_PPM_SPWKUP_OTR                                     , RULL(0x2E0F010A), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F010A,
+REG64( EX_8_PPM_SPWKUP_OTR                                     , RULL(0x300F010A), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F010A,
+REG64( EX_9_PPM_SPWKUP_OTR                                     , RULL(0x320F010A), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F010A,
+REG64( EX_10_PPM_SPWKUP_OTR                                    , RULL(0x340F010A), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F010A,
+REG64( EX_11_PPM_SPWKUP_OTR                                    , RULL(0x360F010A), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F010A,
+
+REG64( C_PPM_SSHFSP                                            , RULL(0x200F0111), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_PPM_SSHFSP                                          , RULL(0x200F0111), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_PPM_SSHFSP                                          , RULL(0x210F0111), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_PPM_SSHFSP                                          , RULL(0x220F0111), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_PPM_SSHFSP                                          , RULL(0x230F0111), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_PPM_SSHFSP                                          , RULL(0x240F0111), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_PPM_SSHFSP                                          , RULL(0x250F0111), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_PPM_SSHFSP                                          , RULL(0x260F0111), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_PPM_SSHFSP                                          , RULL(0x270F0111), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_PPM_SSHFSP                                          , RULL(0x280F0111), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_PPM_SSHFSP                                          , RULL(0x290F0111), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_PPM_SSHFSP                                         , RULL(0x2A0F0111), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_PPM_SSHFSP                                         , RULL(0x2B0F0111), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_PPM_SSHFSP                                         , RULL(0x2C0F0111), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_PPM_SSHFSP                                         , RULL(0x2D0F0111), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_PPM_SSHFSP                                         , RULL(0x2E0F0111), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_PPM_SSHFSP                                         , RULL(0x2F0F0111), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_PPM_SSHFSP                                         , RULL(0x300F0111), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_PPM_SSHFSP                                         , RULL(0x310F0111), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_PPM_SSHFSP                                         , RULL(0x320F0111), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_PPM_SSHFSP                                         , RULL(0x330F0111), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_PPM_SSHFSP                                         , RULL(0x340F0111), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_PPM_SSHFSP                                         , RULL(0x350F0111), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_PPM_SSHFSP                                         , RULL(0x360F0111), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_PPM_SSHFSP                                         , RULL(0x370F0111), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_PPM_SSHFSP                                           , RULL(0x100F0111), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_PPM_SSHFSP                                         , RULL(0x100F0111), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_PPM_SSHFSP                                         , RULL(0x110F0111), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_PPM_SSHFSP                                         , RULL(0x120F0111), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_PPM_SSHFSP                                         , RULL(0x130F0111), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_PPM_SSHFSP                                         , RULL(0x140F0111), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_PPM_SSHFSP                                         , RULL(0x150F0111), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_PPM_SSHFSP                                           , RULL(0x200F0111), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0111,
+REG64( EX_0_PPM_SSHFSP                                         , RULL(0x200F0111), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0111,
+REG64( EX_1_PPM_SSHFSP                                         , RULL(0x230F0111), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0111,
+REG64( EX_2_PPM_SSHFSP                                         , RULL(0x240F0111), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0111,
+REG64( EX_3_PPM_SSHFSP                                         , RULL(0x260F0111), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0111,
+REG64( EX_4_PPM_SSHFSP                                         , RULL(0x280F0111), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0111,
+REG64( EX_5_PPM_SSHFSP                                         , RULL(0x2A0F0111), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0111,
+REG64( EX_6_PPM_SSHFSP                                         , RULL(0x2C0F0111), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0111,
+REG64( EX_7_PPM_SSHFSP                                         , RULL(0x2E0F0111), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0111,
+REG64( EX_8_PPM_SSHFSP                                         , RULL(0x300F0111), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0111,
+REG64( EX_9_PPM_SSHFSP                                         , RULL(0x320F0111), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0111,
+REG64( EX_10_PPM_SSHFSP                                        , RULL(0x340F0111), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0111,
+REG64( EX_11_PPM_SSHFSP                                        , RULL(0x360F0111), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0111,
+
+REG64( C_PPM_SSHHYP                                            , RULL(0x200F0114), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_PPM_SSHHYP                                          , RULL(0x200F0114), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_PPM_SSHHYP                                          , RULL(0x210F0114), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_PPM_SSHHYP                                          , RULL(0x220F0114), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_PPM_SSHHYP                                          , RULL(0x230F0114), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_PPM_SSHHYP                                          , RULL(0x240F0114), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_PPM_SSHHYP                                          , RULL(0x250F0114), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_PPM_SSHHYP                                          , RULL(0x260F0114), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_PPM_SSHHYP                                          , RULL(0x270F0114), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_PPM_SSHHYP                                          , RULL(0x280F0114), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_PPM_SSHHYP                                          , RULL(0x290F0114), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_PPM_SSHHYP                                         , RULL(0x2A0F0114), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_PPM_SSHHYP                                         , RULL(0x2B0F0114), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_PPM_SSHHYP                                         , RULL(0x2C0F0114), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_PPM_SSHHYP                                         , RULL(0x2D0F0114), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_PPM_SSHHYP                                         , RULL(0x2E0F0114), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_PPM_SSHHYP                                         , RULL(0x2F0F0114), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_PPM_SSHHYP                                         , RULL(0x300F0114), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_PPM_SSHHYP                                         , RULL(0x310F0114), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_PPM_SSHHYP                                         , RULL(0x320F0114), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_PPM_SSHHYP                                         , RULL(0x330F0114), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_PPM_SSHHYP                                         , RULL(0x340F0114), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_PPM_SSHHYP                                         , RULL(0x350F0114), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_PPM_SSHHYP                                         , RULL(0x360F0114), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_PPM_SSHHYP                                         , RULL(0x370F0114), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_PPM_SSHHYP                                           , RULL(0x100F0114), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_PPM_SSHHYP                                         , RULL(0x100F0114), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_PPM_SSHHYP                                         , RULL(0x110F0114), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_PPM_SSHHYP                                         , RULL(0x120F0114), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_PPM_SSHHYP                                         , RULL(0x130F0114), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_PPM_SSHHYP                                         , RULL(0x140F0114), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_PPM_SSHHYP                                         , RULL(0x150F0114), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_PPM_SSHHYP                                           , RULL(0x200F0114), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0114,
+REG64( EX_0_PPM_SSHHYP                                         , RULL(0x200F0114), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0114,
+REG64( EX_1_PPM_SSHHYP                                         , RULL(0x230F0114), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0114,
+REG64( EX_2_PPM_SSHHYP                                         , RULL(0x240F0114), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0114,
+REG64( EX_3_PPM_SSHHYP                                         , RULL(0x260F0114), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0114,
+REG64( EX_4_PPM_SSHHYP                                         , RULL(0x280F0114), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0114,
+REG64( EX_5_PPM_SSHHYP                                         , RULL(0x2A0F0114), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0114,
+REG64( EX_6_PPM_SSHHYP                                         , RULL(0x2C0F0114), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0114,
+REG64( EX_7_PPM_SSHHYP                                         , RULL(0x2E0F0114), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0114,
+REG64( EX_8_PPM_SSHHYP                                         , RULL(0x300F0114), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0114,
+REG64( EX_9_PPM_SSHHYP                                         , RULL(0x320F0114), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0114,
+REG64( EX_10_PPM_SSHHYP                                        , RULL(0x340F0114), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0114,
+REG64( EX_11_PPM_SSHHYP                                        , RULL(0x360F0114), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0114,
+
+REG64( C_PPM_SSHOCC                                            , RULL(0x200F0112), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_PPM_SSHOCC                                          , RULL(0x200F0112), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_PPM_SSHOCC                                          , RULL(0x210F0112), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_PPM_SSHOCC                                          , RULL(0x220F0112), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_PPM_SSHOCC                                          , RULL(0x230F0112), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_PPM_SSHOCC                                          , RULL(0x240F0112), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_PPM_SSHOCC                                          , RULL(0x250F0112), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_PPM_SSHOCC                                          , RULL(0x260F0112), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_PPM_SSHOCC                                          , RULL(0x270F0112), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_PPM_SSHOCC                                          , RULL(0x280F0112), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_PPM_SSHOCC                                          , RULL(0x290F0112), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_PPM_SSHOCC                                         , RULL(0x2A0F0112), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_PPM_SSHOCC                                         , RULL(0x2B0F0112), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_PPM_SSHOCC                                         , RULL(0x2C0F0112), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_PPM_SSHOCC                                         , RULL(0x2D0F0112), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_PPM_SSHOCC                                         , RULL(0x2E0F0112), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_PPM_SSHOCC                                         , RULL(0x2F0F0112), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_PPM_SSHOCC                                         , RULL(0x300F0112), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_PPM_SSHOCC                                         , RULL(0x310F0112), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_PPM_SSHOCC                                         , RULL(0x320F0112), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_PPM_SSHOCC                                         , RULL(0x330F0112), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_PPM_SSHOCC                                         , RULL(0x340F0112), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_PPM_SSHOCC                                         , RULL(0x350F0112), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_PPM_SSHOCC                                         , RULL(0x360F0112), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_PPM_SSHOCC                                         , RULL(0x370F0112), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_PPM_SSHOCC                                           , RULL(0x100F0112), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_PPM_SSHOCC                                         , RULL(0x100F0112), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_PPM_SSHOCC                                         , RULL(0x110F0112), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_PPM_SSHOCC                                         , RULL(0x120F0112), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_PPM_SSHOCC                                         , RULL(0x130F0112), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_PPM_SSHOCC                                         , RULL(0x140F0112), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_PPM_SSHOCC                                         , RULL(0x150F0112), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_PPM_SSHOCC                                           , RULL(0x200F0112), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0112,
+REG64( EX_0_PPM_SSHOCC                                         , RULL(0x200F0112), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0112,
+REG64( EX_1_PPM_SSHOCC                                         , RULL(0x230F0112), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0112,
+REG64( EX_2_PPM_SSHOCC                                         , RULL(0x240F0112), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0112,
+REG64( EX_3_PPM_SSHOCC                                         , RULL(0x260F0112), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0112,
+REG64( EX_4_PPM_SSHOCC                                         , RULL(0x280F0112), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0112,
+REG64( EX_5_PPM_SSHOCC                                         , RULL(0x2A0F0112), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0112,
+REG64( EX_6_PPM_SSHOCC                                         , RULL(0x2C0F0112), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0112,
+REG64( EX_7_PPM_SSHOCC                                         , RULL(0x2E0F0112), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0112,
+REG64( EX_8_PPM_SSHOCC                                         , RULL(0x300F0112), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0112,
+REG64( EX_9_PPM_SSHOCC                                         , RULL(0x320F0112), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0112,
+REG64( EX_10_PPM_SSHOCC                                        , RULL(0x340F0112), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0112,
+REG64( EX_11_PPM_SSHOCC                                        , RULL(0x360F0112), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0112,
+
+REG64( C_PPM_SSHOTR                                            , RULL(0x200F0113), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_PPM_SSHOTR                                          , RULL(0x200F0113), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_PPM_SSHOTR                                          , RULL(0x210F0113), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_PPM_SSHOTR                                          , RULL(0x220F0113), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_PPM_SSHOTR                                          , RULL(0x230F0113), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_PPM_SSHOTR                                          , RULL(0x240F0113), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_PPM_SSHOTR                                          , RULL(0x250F0113), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_PPM_SSHOTR                                          , RULL(0x260F0113), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_PPM_SSHOTR                                          , RULL(0x270F0113), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_PPM_SSHOTR                                          , RULL(0x280F0113), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_PPM_SSHOTR                                          , RULL(0x290F0113), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_PPM_SSHOTR                                         , RULL(0x2A0F0113), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_PPM_SSHOTR                                         , RULL(0x2B0F0113), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_PPM_SSHOTR                                         , RULL(0x2C0F0113), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_PPM_SSHOTR                                         , RULL(0x2D0F0113), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_PPM_SSHOTR                                         , RULL(0x2E0F0113), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_PPM_SSHOTR                                         , RULL(0x2F0F0113), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_PPM_SSHOTR                                         , RULL(0x300F0113), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_PPM_SSHOTR                                         , RULL(0x310F0113), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_PPM_SSHOTR                                         , RULL(0x320F0113), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_PPM_SSHOTR                                         , RULL(0x330F0113), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_PPM_SSHOTR                                         , RULL(0x340F0113), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_PPM_SSHOTR                                         , RULL(0x350F0113), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_PPM_SSHOTR                                         , RULL(0x360F0113), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_PPM_SSHOTR                                         , RULL(0x370F0113), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_PPM_SSHOTR                                           , RULL(0x100F0113), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_PPM_SSHOTR                                         , RULL(0x100F0113), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_PPM_SSHOTR                                         , RULL(0x110F0113), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_PPM_SSHOTR                                         , RULL(0x120F0113), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_PPM_SSHOTR                                         , RULL(0x130F0113), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_PPM_SSHOTR                                         , RULL(0x140F0113), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_PPM_SSHOTR                                         , RULL(0x150F0113), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_PPM_SSHOTR                                           , RULL(0x200F0113), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0113,
+REG64( EX_0_PPM_SSHOTR                                         , RULL(0x200F0113), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0113,
+REG64( EX_1_PPM_SSHOTR                                         , RULL(0x230F0113), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0113,
+REG64( EX_2_PPM_SSHOTR                                         , RULL(0x240F0113), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0113,
+REG64( EX_3_PPM_SSHOTR                                         , RULL(0x260F0113), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0113,
+REG64( EX_4_PPM_SSHOTR                                         , RULL(0x280F0113), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0113,
+REG64( EX_5_PPM_SSHOTR                                         , RULL(0x2A0F0113), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0113,
+REG64( EX_6_PPM_SSHOTR                                         , RULL(0x2C0F0113), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0113,
+REG64( EX_7_PPM_SSHOTR                                         , RULL(0x2E0F0113), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0113,
+REG64( EX_8_PPM_SSHOTR                                         , RULL(0x300F0113), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0113,
+REG64( EX_9_PPM_SSHOTR                                         , RULL(0x320F0113), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0113,
+REG64( EX_10_PPM_SSHOTR                                        , RULL(0x340F0113), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0113,
+REG64( EX_11_PPM_SSHOTR                                        , RULL(0x360F0113), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0113,
+
+REG64( C_PPM_SSHSRC                                            , RULL(0x200F0110), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_PPM_SSHSRC                                          , RULL(0x200F0110), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_PPM_SSHSRC                                          , RULL(0x210F0110), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_PPM_SSHSRC                                          , RULL(0x220F0110), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_PPM_SSHSRC                                          , RULL(0x230F0110), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_PPM_SSHSRC                                          , RULL(0x240F0110), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_PPM_SSHSRC                                          , RULL(0x250F0110), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_PPM_SSHSRC                                          , RULL(0x260F0110), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_PPM_SSHSRC                                          , RULL(0x270F0110), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_PPM_SSHSRC                                          , RULL(0x280F0110), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_PPM_SSHSRC                                          , RULL(0x290F0110), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_PPM_SSHSRC                                         , RULL(0x2A0F0110), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_PPM_SSHSRC                                         , RULL(0x2B0F0110), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_PPM_SSHSRC                                         , RULL(0x2C0F0110), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_PPM_SSHSRC                                         , RULL(0x2D0F0110), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_PPM_SSHSRC                                         , RULL(0x2E0F0110), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_PPM_SSHSRC                                         , RULL(0x2F0F0110), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_PPM_SSHSRC                                         , RULL(0x300F0110), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_PPM_SSHSRC                                         , RULL(0x310F0110), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_PPM_SSHSRC                                         , RULL(0x320F0110), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_PPM_SSHSRC                                         , RULL(0x330F0110), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_PPM_SSHSRC                                         , RULL(0x340F0110), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_PPM_SSHSRC                                         , RULL(0x350F0110), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_PPM_SSHSRC                                         , RULL(0x360F0110), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_PPM_SSHSRC                                         , RULL(0x370F0110), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_PPM_SSHSRC                                           , RULL(0x100F0110), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_PPM_SSHSRC                                         , RULL(0x100F0110), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_PPM_SSHSRC                                         , RULL(0x110F0110), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_PPM_SSHSRC                                         , RULL(0x120F0110), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_PPM_SSHSRC                                         , RULL(0x130F0110), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_PPM_SSHSRC                                         , RULL(0x140F0110), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_PPM_SSHSRC                                         , RULL(0x150F0110), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_PPM_SSHSRC                                           , RULL(0x200F0110), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0110,
+REG64( EX_0_PPM_SSHSRC                                         , RULL(0x200F0110), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0110,
+REG64( EX_1_PPM_SSHSRC                                         , RULL(0x230F0110), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0110,
+REG64( EX_2_PPM_SSHSRC                                         , RULL(0x240F0110), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0110,
+REG64( EX_3_PPM_SSHSRC                                         , RULL(0x260F0110), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0110,
+REG64( EX_4_PPM_SSHSRC                                         , RULL(0x280F0110), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0110,
+REG64( EX_5_PPM_SSHSRC                                         , RULL(0x2A0F0110), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0110,
+REG64( EX_6_PPM_SSHSRC                                         , RULL(0x2C0F0110), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0110,
+REG64( EX_7_PPM_SSHSRC                                         , RULL(0x2E0F0110), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0110,
+REG64( EX_8_PPM_SSHSRC                                         , RULL(0x300F0110), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0110,
+REG64( EX_9_PPM_SSHSRC                                         , RULL(0x320F0110), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0110,
+REG64( EX_10_PPM_SSHSRC                                        , RULL(0x340F0110), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0110,
+REG64( EX_11_PPM_SSHSRC                                        , RULL(0x360F0110), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0110,
+
+REG64( C_PPM_VDMCR                                             , RULL(0x200F01B8), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_PPM_VDMCR_CLEAR                                       , RULL(0x200F01B9), SH_UNT_C        ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_PPM_VDMCR_OR                                          , RULL(0x200F01BA), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_PPM_VDMCR                                           , RULL(0x200F01B8), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_0_PPM_VDMCR_CLEAR                                     , RULL(0x200F01B9), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_0_PPM_VDMCR_OR                                        , RULL(0x200F01BA), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_PPM_VDMCR                                           , RULL(0x210F01B8), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_1_PPM_VDMCR_CLEAR                                     , RULL(0x210F01B9), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_1_PPM_VDMCR_OR                                        , RULL(0x210F01BA), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_PPM_VDMCR                                           , RULL(0x220F01B8), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_2_PPM_VDMCR_CLEAR                                     , RULL(0x220F01B9), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_2_PPM_VDMCR_OR                                        , RULL(0x220F01BA), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_PPM_VDMCR                                           , RULL(0x230F01B8), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_3_PPM_VDMCR_CLEAR                                     , RULL(0x230F01B9), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_3_PPM_VDMCR_OR                                        , RULL(0x230F01BA), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_PPM_VDMCR                                           , RULL(0x240F01B8), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_4_PPM_VDMCR_CLEAR                                     , RULL(0x240F01B9), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_4_PPM_VDMCR_OR                                        , RULL(0x240F01BA), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_PPM_VDMCR                                           , RULL(0x250F01B8), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_5_PPM_VDMCR_CLEAR                                     , RULL(0x250F01B9), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_5_PPM_VDMCR_OR                                        , RULL(0x250F01BA), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_PPM_VDMCR                                           , RULL(0x260F01B8), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_6_PPM_VDMCR_CLEAR                                     , RULL(0x260F01B9), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_6_PPM_VDMCR_OR                                        , RULL(0x260F01BA), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_PPM_VDMCR                                           , RULL(0x270F01B8), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_7_PPM_VDMCR_CLEAR                                     , RULL(0x270F01B9), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_7_PPM_VDMCR_OR                                        , RULL(0x270F01BA), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_PPM_VDMCR                                           , RULL(0x280F01B8), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_8_PPM_VDMCR_CLEAR                                     , RULL(0x280F01B9), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_8_PPM_VDMCR_OR                                        , RULL(0x280F01BA), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_PPM_VDMCR                                           , RULL(0x290F01B8), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_9_PPM_VDMCR_CLEAR                                     , RULL(0x290F01B9), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_9_PPM_VDMCR_OR                                        , RULL(0x290F01BA), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_PPM_VDMCR                                          , RULL(0x2A0F01B8), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_10_PPM_VDMCR_CLEAR                                    , RULL(0x2A0F01B9), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_10_PPM_VDMCR_OR                                       , RULL(0x2A0F01BA), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_PPM_VDMCR                                          , RULL(0x2B0F01B8), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_11_PPM_VDMCR_CLEAR                                    , RULL(0x2B0F01B9), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_11_PPM_VDMCR_OR                                       , RULL(0x2B0F01BA), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_PPM_VDMCR                                          , RULL(0x2C0F01B8), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_12_PPM_VDMCR_CLEAR                                    , RULL(0x2C0F01B9), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_12_PPM_VDMCR_OR                                       , RULL(0x2C0F01BA), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_PPM_VDMCR                                          , RULL(0x2D0F01B8), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_13_PPM_VDMCR_CLEAR                                    , RULL(0x2D0F01B9), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_13_PPM_VDMCR_OR                                       , RULL(0x2D0F01BA), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_PPM_VDMCR                                          , RULL(0x2E0F01B8), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_14_PPM_VDMCR_CLEAR                                    , RULL(0x2E0F01B9), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_14_PPM_VDMCR_OR                                       , RULL(0x2E0F01BA), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_PPM_VDMCR                                          , RULL(0x2F0F01B8), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_15_PPM_VDMCR_CLEAR                                    , RULL(0x2F0F01B9), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_15_PPM_VDMCR_OR                                       , RULL(0x2F0F01BA), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_PPM_VDMCR                                          , RULL(0x300F01B8), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_16_PPM_VDMCR_CLEAR                                    , RULL(0x300F01B9), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_16_PPM_VDMCR_OR                                       , RULL(0x300F01BA), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_PPM_VDMCR                                          , RULL(0x310F01B8), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_17_PPM_VDMCR_CLEAR                                    , RULL(0x310F01B9), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_17_PPM_VDMCR_OR                                       , RULL(0x310F01BA), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_PPM_VDMCR                                          , RULL(0x320F01B8), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_18_PPM_VDMCR_CLEAR                                    , RULL(0x320F01B9), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_18_PPM_VDMCR_OR                                       , RULL(0x320F01BA), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_PPM_VDMCR                                          , RULL(0x330F01B8), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_19_PPM_VDMCR_CLEAR                                    , RULL(0x330F01B9), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_19_PPM_VDMCR_OR                                       , RULL(0x330F01BA), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_PPM_VDMCR                                          , RULL(0x340F01B8), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_20_PPM_VDMCR_CLEAR                                    , RULL(0x340F01B9), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_20_PPM_VDMCR_OR                                       , RULL(0x340F01BA), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_PPM_VDMCR                                          , RULL(0x350F01B8), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_21_PPM_VDMCR_CLEAR                                    , RULL(0x350F01B9), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_21_PPM_VDMCR_OR                                       , RULL(0x350F01BA), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_PPM_VDMCR                                          , RULL(0x360F01B8), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_22_PPM_VDMCR_CLEAR                                    , RULL(0x360F01B9), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_22_PPM_VDMCR_OR                                       , RULL(0x360F01BA), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_PPM_VDMCR                                          , RULL(0x370F01B8), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( C_23_PPM_VDMCR_CLEAR                                    , RULL(0x370F01B9), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( C_23_PPM_VDMCR_OR                                       , RULL(0x370F01BA), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EQ_PPM_VDMCR                                            , RULL(0x100F01B8), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_PPM_VDMCR_CLEAR                                      , RULL(0x100F01B9), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_PPM_VDMCR_OR                                         , RULL(0x100F01BA), SH_UNT_EQ       , SH_ACS_SCOM2_OR  );
+REG64( EQ_0_PPM_VDMCR                                          , RULL(0x100F01B8), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_0_PPM_VDMCR_CLEAR                                    , RULL(0x100F01B9), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_0_PPM_VDMCR_OR                                       , RULL(0x100F01BA), SH_UNT_EQ_0     , SH_ACS_SCOM2_OR  );
+REG64( EQ_1_PPM_VDMCR                                          , RULL(0x110F01B8), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_PPM_VDMCR_CLEAR                                    , RULL(0x110F01B9), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_1_PPM_VDMCR_OR                                       , RULL(0x110F01BA), SH_UNT_EQ_1     , SH_ACS_SCOM2_OR  );
+REG64( EQ_2_PPM_VDMCR                                          , RULL(0x120F01B8), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_PPM_VDMCR_CLEAR                                    , RULL(0x120F01B9), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_2_PPM_VDMCR_OR                                       , RULL(0x120F01BA), SH_UNT_EQ_2     , SH_ACS_SCOM2_OR  );
+REG64( EQ_3_PPM_VDMCR                                          , RULL(0x130F01B8), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_PPM_VDMCR_CLEAR                                    , RULL(0x130F01B9), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_3_PPM_VDMCR_OR                                       , RULL(0x130F01BA), SH_UNT_EQ_3     , SH_ACS_SCOM2_OR  );
+REG64( EQ_4_PPM_VDMCR                                          , RULL(0x140F01B8), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_PPM_VDMCR_CLEAR                                    , RULL(0x140F01B9), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_4_PPM_VDMCR_OR                                       , RULL(0x140F01BA), SH_UNT_EQ_4     , SH_ACS_SCOM2_OR  );
+REG64( EQ_5_PPM_VDMCR                                          , RULL(0x150F01B8), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_PPM_VDMCR_CLEAR                                    , RULL(0x150F01B9), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_5_PPM_VDMCR_OR                                       , RULL(0x150F01BA), SH_UNT_EQ_5     , SH_ACS_SCOM2_OR  );
+REG64( EX_PPM_VDMCR                                            , RULL(0x200F01B8), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01B8,
+REG64( EX_PPM_VDMCR_CLEAR                                      , RULL(0x200F01B9), SH_UNT_EX       ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F01B9,
+REG64( EX_PPM_VDMCR_OR                                         , RULL(0x200F01BA), SH_UNT_EX       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F01BA,
+REG64( EX_0_PPM_VDMCR                                          , RULL(0x200F01B8), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 210F01B8,
+REG64( EX_0_PPM_VDMCR_CLEAR                                    , RULL(0x200F01B9), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 210F01B9,
+REG64( EX_0_PPM_VDMCR_OR                                       , RULL(0x200F01BA), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 210F01BA,
+REG64( EX_1_PPM_VDMCR                                          , RULL(0x230F01B8), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 220F01B8,
+REG64( EX_1_PPM_VDMCR_CLEAR                                    , RULL(0x230F01B9), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 220F01B9,
+REG64( EX_1_PPM_VDMCR_OR                                       , RULL(0x230F01BA), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 220F01BA,
+REG64( EX_2_PPM_VDMCR                                          , RULL(0x240F01B8), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 250F01B8,
+REG64( EX_2_PPM_VDMCR_CLEAR                                    , RULL(0x240F01B9), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 250F01B9,
+REG64( EX_2_PPM_VDMCR_OR                                       , RULL(0x240F01BA), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 250F01BA,
+REG64( EX_3_PPM_VDMCR                                          , RULL(0x260F01B8), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 270F01B8,
+REG64( EX_3_PPM_VDMCR_CLEAR                                    , RULL(0x260F01B9), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 270F01B9,
+REG64( EX_3_PPM_VDMCR_OR                                       , RULL(0x260F01BA), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 270F01BA,
+REG64( EX_4_PPM_VDMCR                                          , RULL(0x280F01B8), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 290F01B8,
+REG64( EX_4_PPM_VDMCR_CLEAR                                    , RULL(0x280F01B9), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 290F01B9,
+REG64( EX_4_PPM_VDMCR_OR                                       , RULL(0x280F01BA), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 290F01BA,
+REG64( EX_5_PPM_VDMCR                                          , RULL(0x2A0F01B8), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B0F01B8,
+REG64( EX_5_PPM_VDMCR_CLEAR                                    , RULL(0x2A0F01B9), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2B0F01B9,
+REG64( EX_5_PPM_VDMCR_OR                                       , RULL(0x2A0F01BA), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2B0F01BA,
+REG64( EX_6_PPM_VDMCR                                          , RULL(0x2C0F01B8), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D0F01B8,
+REG64( EX_6_PPM_VDMCR_CLEAR                                    , RULL(0x2C0F01B9), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2D0F01B9,
+REG64( EX_6_PPM_VDMCR_OR                                       , RULL(0x2C0F01BA), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2D0F01BA,
+REG64( EX_7_PPM_VDMCR                                          , RULL(0x2E0F01B8), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F0F01B8,
+REG64( EX_7_PPM_VDMCR_CLEAR                                    , RULL(0x2E0F01B9), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 2F0F01B9,
+REG64( EX_7_PPM_VDMCR_OR                                       , RULL(0x2E0F01BA), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2F0F01BA,
+REG64( EX_8_PPM_VDMCR                                          , RULL(0x300F01B8), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 310F01B8,
+REG64( EX_8_PPM_VDMCR_CLEAR                                    , RULL(0x300F01B9), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 310F01B9,
+REG64( EX_8_PPM_VDMCR_OR                                       , RULL(0x300F01BA), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 310F01BA,
+REG64( EX_9_PPM_VDMCR                                          , RULL(0x320F01B8), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 330F01B8,
+REG64( EX_9_PPM_VDMCR_CLEAR                                    , RULL(0x320F01B9), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 330F01B9,
+REG64( EX_9_PPM_VDMCR_OR                                       , RULL(0x320F01BA), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 330F01BA,
+REG64( EX_10_PPM_VDMCR                                         , RULL(0x340F01B8), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 350F01B8,
+REG64( EX_10_PPM_VDMCR_CLEAR                                   , RULL(0x340F01B9), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 350F01B9,
+REG64( EX_10_PPM_VDMCR_OR                                      , RULL(0x340F01BA), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 350F01BA,
+REG64( EX_11_PPM_VDMCR                                         , RULL(0x360F01B8), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 370F01B8,
+REG64( EX_11_PPM_VDMCR_CLEAR                                   , RULL(0x360F01B9), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_CLEAR ); //DUPS: 370F01B9,
+REG64( EX_11_PPM_VDMCR_OR                                      , RULL(0x360F01BA), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 370F01BA,
+
+REG64( EQ_PRD_PURGE_CMD_REG                                    , RULL(0x1001080E), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10010C0E,
+REG64( EQ_0_PRD_PURGE_CMD_REG                                  , RULL(0x1001080E), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10010C0E,
+REG64( EQ_1_PRD_PURGE_CMD_REG                                  , RULL(0x1101080E), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11010C0E,
+REG64( EQ_2_PRD_PURGE_CMD_REG                                  , RULL(0x1201080E), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12010C0E,
+REG64( EQ_3_PRD_PURGE_CMD_REG                                  , RULL(0x1301080E), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13010C0E,
+REG64( EQ_4_PRD_PURGE_CMD_REG                                  , RULL(0x1401080E), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14010C0E,
+REG64( EQ_5_PRD_PURGE_CMD_REG                                  , RULL(0x1501080E), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15010C0E,
+REG64( EX_PRD_PURGE_CMD_REG                                    , RULL(0x1001080E), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_PRD_PURGE_CMD_REG                                  , RULL(0x1001080E), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_PRD_PURGE_CMD_REG                                  , RULL(0x10010C0E), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_PRD_PURGE_CMD_REG                                  , RULL(0x1101080E), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_PRD_PURGE_CMD_REG                                  , RULL(0x11010C0E), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_PRD_PURGE_CMD_REG                                  , RULL(0x1201080E), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_PRD_PURGE_CMD_REG                                  , RULL(0x12010C0E), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_PRD_PURGE_CMD_REG                                  , RULL(0x1301080E), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_PRD_PURGE_CMD_REG                                  , RULL(0x13010C0E), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_PRD_PURGE_CMD_REG                                  , RULL(0x1401080E), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_PRD_PURGE_CMD_REG                                  , RULL(0x14010C0E), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_PRD_PURGE_CMD_REG                                 , RULL(0x1501080E), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_PRD_PURGE_CMD_REG                                 , RULL(0x15010C0E), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_PRD_PURGE_REG                                        , RULL(0x1001180E), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10011C0E,
+REG64( EQ_0_PRD_PURGE_REG                                      , RULL(0x1001180E), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10011C0E,
+REG64( EQ_1_PRD_PURGE_REG                                      , RULL(0x1101180E), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11011C0E,
+REG64( EQ_2_PRD_PURGE_REG                                      , RULL(0x1201180E), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12011C0E,
+REG64( EQ_3_PRD_PURGE_REG                                      , RULL(0x1301180E), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13011C0E,
+REG64( EQ_4_PRD_PURGE_REG                                      , RULL(0x1401180E), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14011C0E,
+REG64( EQ_5_PRD_PURGE_REG                                      , RULL(0x1501180E), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15011C0E,
+REG64( EX_PRD_PURGE_REG                                        , RULL(0x1001180E), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_PRD_PURGE_REG                                      , RULL(0x1001180E), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_1_PRD_PURGE_REG                                      , RULL(0x10011C0E), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_2_PRD_PURGE_REG                                      , RULL(0x1101180E), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_3_PRD_PURGE_REG                                      , RULL(0x11011C0E), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_4_PRD_PURGE_REG                                      , RULL(0x1201180E), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_5_PRD_PURGE_REG                                      , RULL(0x12011C0E), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_6_PRD_PURGE_REG                                      , RULL(0x1301180E), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_7_PRD_PURGE_REG                                      , RULL(0x13011C0E), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_8_PRD_PURGE_REG                                      , RULL(0x1401180E), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_9_PRD_PURGE_REG                                      , RULL(0x14011C0E), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_10_PRD_PURGE_REG                                     , RULL(0x1501180E), SH_UNT_EX_10    , SH_ACS_SCOM      );
+REG64( EX_11_PRD_PURGE_REG                                     , RULL(0x15011C0E), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( C_PRE_COUNTER_REG                                       , RULL(0x200F0028), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_PRE_COUNTER_REG                                     , RULL(0x200F0028), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_PRE_COUNTER_REG                                     , RULL(0x210F0028), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_PRE_COUNTER_REG                                     , RULL(0x220F0028), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_PRE_COUNTER_REG                                     , RULL(0x230F0028), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_PRE_COUNTER_REG                                     , RULL(0x240F0028), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_PRE_COUNTER_REG                                     , RULL(0x250F0028), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_PRE_COUNTER_REG                                     , RULL(0x260F0028), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_PRE_COUNTER_REG                                     , RULL(0x270F0028), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_PRE_COUNTER_REG                                     , RULL(0x280F0028), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_PRE_COUNTER_REG                                     , RULL(0x290F0028), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_PRE_COUNTER_REG                                    , RULL(0x2A0F0028), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_PRE_COUNTER_REG                                    , RULL(0x2B0F0028), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_PRE_COUNTER_REG                                    , RULL(0x2C0F0028), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_PRE_COUNTER_REG                                    , RULL(0x2D0F0028), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_PRE_COUNTER_REG                                    , RULL(0x2E0F0028), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_PRE_COUNTER_REG                                    , RULL(0x2F0F0028), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_PRE_COUNTER_REG                                    , RULL(0x300F0028), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_PRE_COUNTER_REG                                    , RULL(0x310F0028), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_PRE_COUNTER_REG                                    , RULL(0x320F0028), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_PRE_COUNTER_REG                                    , RULL(0x330F0028), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_PRE_COUNTER_REG                                    , RULL(0x340F0028), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_PRE_COUNTER_REG                                    , RULL(0x350F0028), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_PRE_COUNTER_REG                                    , RULL(0x360F0028), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_PRE_COUNTER_REG                                    , RULL(0x370F0028), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_PRE_COUNTER_REG                                      , RULL(0x100F0028), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_PRE_COUNTER_REG                                    , RULL(0x100F0028), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_PRE_COUNTER_REG                                    , RULL(0x110F0028), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_PRE_COUNTER_REG                                    , RULL(0x120F0028), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_PRE_COUNTER_REG                                    , RULL(0x130F0028), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_PRE_COUNTER_REG                                    , RULL(0x140F0028), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_PRE_COUNTER_REG                                    , RULL(0x150F0028), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_PRE_COUNTER_REG                                      , RULL(0x200F0028), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0028,
+REG64( EX_0_PRE_COUNTER_REG                                    , RULL(0x200F0028), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0028,
+REG64( EX_1_PRE_COUNTER_REG                                    , RULL(0x230F0028), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0028,
+REG64( EX_2_PRE_COUNTER_REG                                    , RULL(0x240F0028), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0028,
+REG64( EX_3_PRE_COUNTER_REG                                    , RULL(0x260F0028), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0028,
+REG64( EX_4_PRE_COUNTER_REG                                    , RULL(0x280F0028), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0028,
+REG64( EX_5_PRE_COUNTER_REG                                    , RULL(0x2A0F0028), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0028,
+REG64( EX_6_PRE_COUNTER_REG                                    , RULL(0x2C0F0028), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0028,
+REG64( EX_7_PRE_COUNTER_REG                                    , RULL(0x2E0F0028), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0028,
+REG64( EX_8_PRE_COUNTER_REG                                    , RULL(0x300F0028), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0028,
+REG64( EX_9_PRE_COUNTER_REG                                    , RULL(0x320F0028), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0028,
+REG64( EX_10_PRE_COUNTER_REG                                   , RULL(0x340F0028), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0028,
+REG64( EX_11_PRE_COUNTER_REG                                   , RULL(0x360F0028), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0028,
+
+REG64( C_PRIMARY_ADDRESS_REG                                   , RULL(0x200F0000), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_PRIMARY_ADDRESS_REG                                 , RULL(0x200F0000), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_PRIMARY_ADDRESS_REG                                 , RULL(0x210F0000), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_PRIMARY_ADDRESS_REG                                 , RULL(0x220F0000), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_PRIMARY_ADDRESS_REG                                 , RULL(0x230F0000), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_PRIMARY_ADDRESS_REG                                 , RULL(0x240F0000), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_PRIMARY_ADDRESS_REG                                 , RULL(0x250F0000), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_PRIMARY_ADDRESS_REG                                 , RULL(0x260F0000), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_PRIMARY_ADDRESS_REG                                 , RULL(0x270F0000), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_PRIMARY_ADDRESS_REG                                 , RULL(0x280F0000), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_PRIMARY_ADDRESS_REG                                 , RULL(0x290F0000), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_PRIMARY_ADDRESS_REG                                , RULL(0x2A0F0000), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_PRIMARY_ADDRESS_REG                                , RULL(0x2B0F0000), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_PRIMARY_ADDRESS_REG                                , RULL(0x2C0F0000), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_PRIMARY_ADDRESS_REG                                , RULL(0x2D0F0000), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_PRIMARY_ADDRESS_REG                                , RULL(0x2E0F0000), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_PRIMARY_ADDRESS_REG                                , RULL(0x2F0F0000), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_PRIMARY_ADDRESS_REG                                , RULL(0x300F0000), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_PRIMARY_ADDRESS_REG                                , RULL(0x310F0000), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_PRIMARY_ADDRESS_REG                                , RULL(0x320F0000), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_PRIMARY_ADDRESS_REG                                , RULL(0x330F0000), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_PRIMARY_ADDRESS_REG                                , RULL(0x340F0000), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_PRIMARY_ADDRESS_REG                                , RULL(0x350F0000), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_PRIMARY_ADDRESS_REG                                , RULL(0x360F0000), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_PRIMARY_ADDRESS_REG                                , RULL(0x370F0000), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_PRIMARY_ADDRESS_REG                                  , RULL(0x100F0000), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_PRIMARY_ADDRESS_REG                                , RULL(0x100F0000), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_PRIMARY_ADDRESS_REG                                , RULL(0x110F0000), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_PRIMARY_ADDRESS_REG                                , RULL(0x120F0000), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_PRIMARY_ADDRESS_REG                                , RULL(0x130F0000), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_PRIMARY_ADDRESS_REG                                , RULL(0x140F0000), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_PRIMARY_ADDRESS_REG                                , RULL(0x150F0000), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_PRIMARY_ADDRESS_REG                                  , RULL(0x200F0000), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0000,
+REG64( EX_0_PRIMARY_ADDRESS_REG                                , RULL(0x200F0000), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0000,
+REG64( EX_1_PRIMARY_ADDRESS_REG                                , RULL(0x230F0000), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0000,
+REG64( EX_2_PRIMARY_ADDRESS_REG                                , RULL(0x240F0000), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0000,
+REG64( EX_3_PRIMARY_ADDRESS_REG                                , RULL(0x260F0000), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0000,
+REG64( EX_4_PRIMARY_ADDRESS_REG                                , RULL(0x280F0000), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0000,
+REG64( EX_5_PRIMARY_ADDRESS_REG                                , RULL(0x2A0F0000), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0000,
+REG64( EX_6_PRIMARY_ADDRESS_REG                                , RULL(0x2C0F0000), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0000,
+REG64( EX_7_PRIMARY_ADDRESS_REG                                , RULL(0x2E0F0000), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0000,
+REG64( EX_8_PRIMARY_ADDRESS_REG                                , RULL(0x300F0000), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0000,
+REG64( EX_9_PRIMARY_ADDRESS_REG                                , RULL(0x320F0000), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0000,
+REG64( EX_10_PRIMARY_ADDRESS_REG                               , RULL(0x340F0000), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0000,
+REG64( EX_11_PRIMARY_ADDRESS_REG                               , RULL(0x360F0000), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0000,
+
+REG64( C_PROTECT_MODE_REG                                      , RULL(0x200F03FE), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_PROTECT_MODE_REG                                    , RULL(0x200F03FE), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_PROTECT_MODE_REG                                    , RULL(0x210F03FE), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_PROTECT_MODE_REG                                    , RULL(0x220F03FE), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_PROTECT_MODE_REG                                    , RULL(0x230F03FE), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_PROTECT_MODE_REG                                    , RULL(0x240F03FE), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_PROTECT_MODE_REG                                    , RULL(0x250F03FE), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_PROTECT_MODE_REG                                    , RULL(0x260F03FE), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_PROTECT_MODE_REG                                    , RULL(0x270F03FE), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_PROTECT_MODE_REG                                    , RULL(0x280F03FE), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_PROTECT_MODE_REG                                    , RULL(0x290F03FE), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_PROTECT_MODE_REG                                   , RULL(0x2A0F03FE), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_PROTECT_MODE_REG                                   , RULL(0x2B0F03FE), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_PROTECT_MODE_REG                                   , RULL(0x2C0F03FE), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_PROTECT_MODE_REG                                   , RULL(0x2D0F03FE), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_PROTECT_MODE_REG                                   , RULL(0x2E0F03FE), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_PROTECT_MODE_REG                                   , RULL(0x2F0F03FE), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_PROTECT_MODE_REG                                   , RULL(0x300F03FE), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_PROTECT_MODE_REG                                   , RULL(0x310F03FE), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_PROTECT_MODE_REG                                   , RULL(0x320F03FE), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_PROTECT_MODE_REG                                   , RULL(0x330F03FE), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_PROTECT_MODE_REG                                   , RULL(0x340F03FE), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_PROTECT_MODE_REG                                   , RULL(0x350F03FE), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_PROTECT_MODE_REG                                   , RULL(0x360F03FE), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_PROTECT_MODE_REG                                   , RULL(0x370F03FE), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_PROTECT_MODE_REG                                     , RULL(0x100F03FE), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_PROTECT_MODE_REG                                   , RULL(0x100F03FE), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_PROTECT_MODE_REG                                   , RULL(0x110F03FE), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_PROTECT_MODE_REG                                   , RULL(0x120F03FE), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_PROTECT_MODE_REG                                   , RULL(0x130F03FE), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_PROTECT_MODE_REG                                   , RULL(0x140F03FE), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_PROTECT_MODE_REG                                   , RULL(0x150F03FE), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_PROTECT_MODE_REG                                     , RULL(0x200F03FE), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F03FE,
+REG64( EX_0_PROTECT_MODE_REG                                   , RULL(0x200F03FE), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F03FE,
+REG64( EX_1_PROTECT_MODE_REG                                   , RULL(0x230F03FE), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F03FE,
+REG64( EX_2_PROTECT_MODE_REG                                   , RULL(0x240F03FE), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F03FE,
+REG64( EX_3_PROTECT_MODE_REG                                   , RULL(0x260F03FE), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F03FE,
+REG64( EX_4_PROTECT_MODE_REG                                   , RULL(0x280F03FE), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F03FE,
+REG64( EX_5_PROTECT_MODE_REG                                   , RULL(0x2A0F03FE), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F03FE,
+REG64( EX_6_PROTECT_MODE_REG                                   , RULL(0x2C0F03FE), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F03FE,
+REG64( EX_7_PROTECT_MODE_REG                                   , RULL(0x2E0F03FE), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F03FE,
+REG64( EX_8_PROTECT_MODE_REG                                   , RULL(0x300F03FE), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F03FE,
+REG64( EX_9_PROTECT_MODE_REG                                   , RULL(0x320F03FE), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F03FE,
+REG64( EX_10_PROTECT_MODE_REG                                  , RULL(0x340F03FE), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F03FE,
+REG64( EX_11_PROTECT_MODE_REG                                  , RULL(0x360F03FE), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F03FE,
+
+REG64( C_PSCOM_ERROR_MASK                                      , RULL(0x20010002), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_PSCOM_ERROR_MASK                                    , RULL(0x20010002), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_PSCOM_ERROR_MASK                                    , RULL(0x21010002), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_PSCOM_ERROR_MASK                                    , RULL(0x22010002), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_PSCOM_ERROR_MASK                                    , RULL(0x23010002), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_PSCOM_ERROR_MASK                                    , RULL(0x24010002), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_PSCOM_ERROR_MASK                                    , RULL(0x25010002), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_PSCOM_ERROR_MASK                                    , RULL(0x26010002), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_PSCOM_ERROR_MASK                                    , RULL(0x27010002), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_PSCOM_ERROR_MASK                                    , RULL(0x28010002), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_PSCOM_ERROR_MASK                                    , RULL(0x29010002), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_PSCOM_ERROR_MASK                                   , RULL(0x2A010002), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_PSCOM_ERROR_MASK                                   , RULL(0x2B010002), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_PSCOM_ERROR_MASK                                   , RULL(0x2C010002), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_PSCOM_ERROR_MASK                                   , RULL(0x2D010002), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_PSCOM_ERROR_MASK                                   , RULL(0x2E010002), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_PSCOM_ERROR_MASK                                   , RULL(0x2F010002), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_PSCOM_ERROR_MASK                                   , RULL(0x30010002), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_PSCOM_ERROR_MASK                                   , RULL(0x31010002), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_PSCOM_ERROR_MASK                                   , RULL(0x32010002), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_PSCOM_ERROR_MASK                                   , RULL(0x33010002), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_PSCOM_ERROR_MASK                                   , RULL(0x34010002), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_PSCOM_ERROR_MASK                                   , RULL(0x35010002), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_PSCOM_ERROR_MASK                                   , RULL(0x36010002), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_PSCOM_ERROR_MASK                                   , RULL(0x37010002), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_PSCOM_ERROR_MASK                                     , RULL(0x10010002), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_PSCOM_ERROR_MASK                                   , RULL(0x10010002), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_PSCOM_ERROR_MASK                                   , RULL(0x11010002), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_PSCOM_ERROR_MASK                                   , RULL(0x12010002), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_PSCOM_ERROR_MASK                                   , RULL(0x13010002), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_PSCOM_ERROR_MASK                                   , RULL(0x14010002), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_PSCOM_ERROR_MASK                                   , RULL(0x15010002), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_PSCOM_ERROR_MASK                                     , RULL(0x20010002), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21010002,
+REG64( EX_0_PSCOM_ERROR_MASK                                   , RULL(0x20010002), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21010002,
+REG64( EX_1_PSCOM_ERROR_MASK                                   , RULL(0x22010002), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23010002,
+REG64( EX_2_PSCOM_ERROR_MASK                                   , RULL(0x24010002), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25010002,
+REG64( EX_3_PSCOM_ERROR_MASK                                   , RULL(0x26010002), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27010002,
+REG64( EX_4_PSCOM_ERROR_MASK                                   , RULL(0x28010002), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29010002,
+REG64( EX_5_PSCOM_ERROR_MASK                                   , RULL(0x2A010002), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B010002,
+REG64( EX_6_PSCOM_ERROR_MASK                                   , RULL(0x2C010002), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D010002,
+REG64( EX_7_PSCOM_ERROR_MASK                                   , RULL(0x2E010002), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F010002,
+REG64( EX_8_PSCOM_ERROR_MASK                                   , RULL(0x30010002), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31010002,
+REG64( EX_9_PSCOM_ERROR_MASK                                   , RULL(0x32010002), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33010002,
+REG64( EX_10_PSCOM_ERROR_MASK                                  , RULL(0x34010002), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35010002,
+REG64( EX_11_PSCOM_ERROR_MASK                                  , RULL(0x36010002), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37010002,
+
+REG64( C_PSCOM_MODE_REG                                        , RULL(0x20010000), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_PSCOM_MODE_REG                                      , RULL(0x20010000), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_PSCOM_MODE_REG                                      , RULL(0x21010000), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_PSCOM_MODE_REG                                      , RULL(0x22010000), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_PSCOM_MODE_REG                                      , RULL(0x23010000), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_PSCOM_MODE_REG                                      , RULL(0x24010000), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_PSCOM_MODE_REG                                      , RULL(0x25010000), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_PSCOM_MODE_REG                                      , RULL(0x26010000), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_PSCOM_MODE_REG                                      , RULL(0x27010000), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_PSCOM_MODE_REG                                      , RULL(0x28010000), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_PSCOM_MODE_REG                                      , RULL(0x29010000), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_PSCOM_MODE_REG                                     , RULL(0x2A010000), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_PSCOM_MODE_REG                                     , RULL(0x2B010000), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_PSCOM_MODE_REG                                     , RULL(0x2C010000), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_PSCOM_MODE_REG                                     , RULL(0x2D010000), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_PSCOM_MODE_REG                                     , RULL(0x2E010000), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_PSCOM_MODE_REG                                     , RULL(0x2F010000), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_PSCOM_MODE_REG                                     , RULL(0x30010000), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_PSCOM_MODE_REG                                     , RULL(0x31010000), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_PSCOM_MODE_REG                                     , RULL(0x32010000), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_PSCOM_MODE_REG                                     , RULL(0x33010000), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_PSCOM_MODE_REG                                     , RULL(0x34010000), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_PSCOM_MODE_REG                                     , RULL(0x35010000), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_PSCOM_MODE_REG                                     , RULL(0x36010000), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_PSCOM_MODE_REG                                     , RULL(0x37010000), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_PSCOM_MODE_REG                                       , RULL(0x10010000), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_PSCOM_MODE_REG                                     , RULL(0x10010000), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_PSCOM_MODE_REG                                     , RULL(0x11010000), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_PSCOM_MODE_REG                                     , RULL(0x12010000), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_PSCOM_MODE_REG                                     , RULL(0x13010000), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_PSCOM_MODE_REG                                     , RULL(0x14010000), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_PSCOM_MODE_REG                                     , RULL(0x15010000), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_PSCOM_MODE_REG                                       , RULL(0x20010000), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21010000,
+REG64( EX_0_PSCOM_MODE_REG                                     , RULL(0x20010000), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21010000,
+REG64( EX_1_PSCOM_MODE_REG                                     , RULL(0x22010000), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23010000,
+REG64( EX_2_PSCOM_MODE_REG                                     , RULL(0x24010000), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25010000,
+REG64( EX_3_PSCOM_MODE_REG                                     , RULL(0x26010000), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27010000,
+REG64( EX_4_PSCOM_MODE_REG                                     , RULL(0x28010000), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29010000,
+REG64( EX_5_PSCOM_MODE_REG                                     , RULL(0x2A010000), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B010000,
+REG64( EX_6_PSCOM_MODE_REG                                     , RULL(0x2C010000), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D010000,
+REG64( EX_7_PSCOM_MODE_REG                                     , RULL(0x2E010000), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F010000,
+REG64( EX_8_PSCOM_MODE_REG                                     , RULL(0x30010000), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31010000,
+REG64( EX_9_PSCOM_MODE_REG                                     , RULL(0x32010000), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33010000,
+REG64( EX_10_PSCOM_MODE_REG                                    , RULL(0x34010000), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35010000,
+REG64( EX_11_PSCOM_MODE_REG                                    , RULL(0x36010000), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37010000,
+
+REG64( C_PSCOM_STATUS_ERROR_REG                                , RULL(0x20010001), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_PSCOM_STATUS_ERROR_REG                              , RULL(0x20010001), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_PSCOM_STATUS_ERROR_REG                              , RULL(0x21010001), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_PSCOM_STATUS_ERROR_REG                              , RULL(0x22010001), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_PSCOM_STATUS_ERROR_REG                              , RULL(0x23010001), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_PSCOM_STATUS_ERROR_REG                              , RULL(0x24010001), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_PSCOM_STATUS_ERROR_REG                              , RULL(0x25010001), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_PSCOM_STATUS_ERROR_REG                              , RULL(0x26010001), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_PSCOM_STATUS_ERROR_REG                              , RULL(0x27010001), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_PSCOM_STATUS_ERROR_REG                              , RULL(0x28010001), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_PSCOM_STATUS_ERROR_REG                              , RULL(0x29010001), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_PSCOM_STATUS_ERROR_REG                             , RULL(0x2A010001), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_PSCOM_STATUS_ERROR_REG                             , RULL(0x2B010001), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_PSCOM_STATUS_ERROR_REG                             , RULL(0x2C010001), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_PSCOM_STATUS_ERROR_REG                             , RULL(0x2D010001), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_PSCOM_STATUS_ERROR_REG                             , RULL(0x2E010001), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_PSCOM_STATUS_ERROR_REG                             , RULL(0x2F010001), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_PSCOM_STATUS_ERROR_REG                             , RULL(0x30010001), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_PSCOM_STATUS_ERROR_REG                             , RULL(0x31010001), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_PSCOM_STATUS_ERROR_REG                             , RULL(0x32010001), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_PSCOM_STATUS_ERROR_REG                             , RULL(0x33010001), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_PSCOM_STATUS_ERROR_REG                             , RULL(0x34010001), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_PSCOM_STATUS_ERROR_REG                             , RULL(0x35010001), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_PSCOM_STATUS_ERROR_REG                             , RULL(0x36010001), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_PSCOM_STATUS_ERROR_REG                             , RULL(0x37010001), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_PSCOM_STATUS_ERROR_REG                               , RULL(0x10010001), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_PSCOM_STATUS_ERROR_REG                             , RULL(0x10010001), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_PSCOM_STATUS_ERROR_REG                             , RULL(0x11010001), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_PSCOM_STATUS_ERROR_REG                             , RULL(0x12010001), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_PSCOM_STATUS_ERROR_REG                             , RULL(0x13010001), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_PSCOM_STATUS_ERROR_REG                             , RULL(0x14010001), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_PSCOM_STATUS_ERROR_REG                             , RULL(0x15010001), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_PSCOM_STATUS_ERROR_REG                               , RULL(0x20010001), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21010001,
+REG64( EX_0_PSCOM_STATUS_ERROR_REG                             , RULL(0x20010001), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21010001,
+REG64( EX_1_PSCOM_STATUS_ERROR_REG                             , RULL(0x22010001), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23010001,
+REG64( EX_2_PSCOM_STATUS_ERROR_REG                             , RULL(0x24010001), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25010001,
+REG64( EX_3_PSCOM_STATUS_ERROR_REG                             , RULL(0x26010001), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27010001,
+REG64( EX_4_PSCOM_STATUS_ERROR_REG                             , RULL(0x28010001), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29010001,
+REG64( EX_5_PSCOM_STATUS_ERROR_REG                             , RULL(0x2A010001), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B010001,
+REG64( EX_6_PSCOM_STATUS_ERROR_REG                             , RULL(0x2C010001), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D010001,
+REG64( EX_7_PSCOM_STATUS_ERROR_REG                             , RULL(0x2E010001), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F010001,
+REG64( EX_8_PSCOM_STATUS_ERROR_REG                             , RULL(0x30010001), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31010001,
+REG64( EX_9_PSCOM_STATUS_ERROR_REG                             , RULL(0x32010001), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33010001,
+REG64( EX_10_PSCOM_STATUS_ERROR_REG                            , RULL(0x34010001), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35010001,
+REG64( EX_11_PSCOM_STATUS_ERROR_REG                            , RULL(0x36010001), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37010001,
+
+REG64( C_PWM_EVENTS                                            , RULL(0x20010AA2), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_PWM_EVENTS                                          , RULL(0x20010AA2), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_PWM_EVENTS                                          , RULL(0x21010AA2), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_PWM_EVENTS                                          , RULL(0x22010AA2), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_PWM_EVENTS                                          , RULL(0x23010AA2), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_PWM_EVENTS                                          , RULL(0x24010AA2), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_PWM_EVENTS                                          , RULL(0x25010AA2), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_PWM_EVENTS                                          , RULL(0x26010AA2), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_PWM_EVENTS                                          , RULL(0x27010AA2), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_PWM_EVENTS                                          , RULL(0x28010AA2), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_PWM_EVENTS                                          , RULL(0x29010AA2), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_PWM_EVENTS                                         , RULL(0x2A010AA2), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_PWM_EVENTS                                         , RULL(0x2B010AA2), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_PWM_EVENTS                                         , RULL(0x2C010AA2), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_PWM_EVENTS                                         , RULL(0x2D010AA2), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_PWM_EVENTS                                         , RULL(0x2E010AA2), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_PWM_EVENTS                                         , RULL(0x2F010AA2), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_PWM_EVENTS                                         , RULL(0x30010AA2), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_PWM_EVENTS                                         , RULL(0x31010AA2), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_PWM_EVENTS                                         , RULL(0x32010AA2), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_PWM_EVENTS                                         , RULL(0x33010AA2), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_PWM_EVENTS                                         , RULL(0x34010AA2), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_PWM_EVENTS                                         , RULL(0x35010AA2), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_PWM_EVENTS                                         , RULL(0x36010AA2), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_PWM_EVENTS                                         , RULL(0x37010AA2), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_PWM_EVENTS                                      , RULL(0x21010AA2), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010AA2,
+REG64( EX_10_L2_PWM_EVENTS                                     , RULL(0x35010AA2), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 34010AA2,
+REG64( EX_11_L2_PWM_EVENTS                                     , RULL(0x37010AA2), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 36010AA2,
+REG64( EX_1_L2_PWM_EVENTS                                      , RULL(0x23010AA2), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 22010AA2,
+REG64( EX_2_L2_PWM_EVENTS                                      , RULL(0x25010AA2), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 24010AA2,
+REG64( EX_3_L2_PWM_EVENTS                                      , RULL(0x27010AA2), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 26010AA2,
+REG64( EX_4_L2_PWM_EVENTS                                      , RULL(0x29010AA2), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 28010AA2,
+REG64( EX_5_L2_PWM_EVENTS                                      , RULL(0x2B010AA2), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2A010AA2,
+REG64( EX_6_L2_PWM_EVENTS                                      , RULL(0x2D010AA2), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2C010AA2,
+REG64( EX_7_L2_PWM_EVENTS                                      , RULL(0x2F010AA2), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2E010AA2,
+REG64( EX_8_L2_PWM_EVENTS                                      , RULL(0x31010AA2), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 30010AA2,
+REG64( EX_9_L2_PWM_EVENTS                                      , RULL(0x33010AA2), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 32010AA2,
+REG64( EX_L2_PWM_EVENTS                                        , RULL(0x21010AA2), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010AA2,
+
+REG64( EQ_QPPM_DPLL_CTRL                                       , RULL(0x100F0152), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_QPPM_DPLL_CTRL_CLEAR                                 , RULL(0x100F0153), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_QPPM_DPLL_CTRL_OR                                    , RULL(0x100F0154), SH_UNT_EQ       , SH_ACS_SCOM2_OR  );
+REG64( EQ_0_QPPM_DPLL_CTRL                                     , RULL(0x100F0152), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_0_QPPM_DPLL_CTRL_CLEAR                               , RULL(0x100F0153), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_0_QPPM_DPLL_CTRL_OR                                  , RULL(0x100F0154), SH_UNT_EQ_0     , SH_ACS_SCOM2_OR  );
+REG64( EQ_1_QPPM_DPLL_CTRL                                     , RULL(0x110F0152), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_QPPM_DPLL_CTRL_CLEAR                               , RULL(0x110F0153), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_1_QPPM_DPLL_CTRL_OR                                  , RULL(0x110F0154), SH_UNT_EQ_1     , SH_ACS_SCOM2_OR  );
+REG64( EQ_2_QPPM_DPLL_CTRL                                     , RULL(0x120F0152), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_QPPM_DPLL_CTRL_CLEAR                               , RULL(0x120F0153), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_2_QPPM_DPLL_CTRL_OR                                  , RULL(0x120F0154), SH_UNT_EQ_2     , SH_ACS_SCOM2_OR  );
+REG64( EQ_3_QPPM_DPLL_CTRL                                     , RULL(0x130F0152), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_QPPM_DPLL_CTRL_CLEAR                               , RULL(0x130F0153), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_3_QPPM_DPLL_CTRL_OR                                  , RULL(0x130F0154), SH_UNT_EQ_3     , SH_ACS_SCOM2_OR  );
+REG64( EQ_4_QPPM_DPLL_CTRL                                     , RULL(0x140F0152), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_QPPM_DPLL_CTRL_CLEAR                               , RULL(0x140F0153), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_4_QPPM_DPLL_CTRL_OR                                  , RULL(0x140F0154), SH_UNT_EQ_4     , SH_ACS_SCOM2_OR  );
+REG64( EQ_5_QPPM_DPLL_CTRL                                     , RULL(0x150F0152), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_QPPM_DPLL_CTRL_CLEAR                               , RULL(0x150F0153), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_5_QPPM_DPLL_CTRL_OR                                  , RULL(0x150F0154), SH_UNT_EQ_5     , SH_ACS_SCOM2_OR  );
+
+REG64( EQ_QPPM_DPLL_FREQ                                       , RULL(0x100F0151), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_QPPM_DPLL_FREQ                                     , RULL(0x100F0151), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_QPPM_DPLL_FREQ                                     , RULL(0x110F0151), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_QPPM_DPLL_FREQ                                     , RULL(0x120F0151), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_QPPM_DPLL_FREQ                                     , RULL(0x130F0151), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_QPPM_DPLL_FREQ                                     , RULL(0x140F0151), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_QPPM_DPLL_FREQ                                     , RULL(0x150F0151), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+
+REG64( EQ_QPPM_DPLL_ICHAR                                      , RULL(0x100F0157), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_QPPM_DPLL_ICHAR                                    , RULL(0x100F0157), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_QPPM_DPLL_ICHAR                                    , RULL(0x110F0157), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_QPPM_DPLL_ICHAR                                    , RULL(0x120F0157), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_QPPM_DPLL_ICHAR                                    , RULL(0x130F0157), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_QPPM_DPLL_ICHAR                                    , RULL(0x140F0157), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_QPPM_DPLL_ICHAR                                    , RULL(0x150F0157), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+
+REG64( EQ_QPPM_DPLL_OCHAR                                      , RULL(0x100F0156), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_QPPM_DPLL_OCHAR                                    , RULL(0x100F0156), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_QPPM_DPLL_OCHAR                                    , RULL(0x110F0156), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_QPPM_DPLL_OCHAR                                    , RULL(0x120F0156), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_QPPM_DPLL_OCHAR                                    , RULL(0x130F0156), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_QPPM_DPLL_OCHAR                                    , RULL(0x140F0156), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_QPPM_DPLL_OCHAR                                    , RULL(0x150F0156), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+
+REG64( EQ_QPPM_DPLL_STAT                                       , RULL(0x100F0155), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_QPPM_DPLL_STAT                                     , RULL(0x100F0155), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_QPPM_DPLL_STAT                                     , RULL(0x110F0155), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_QPPM_DPLL_STAT                                     , RULL(0x120F0155), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_QPPM_DPLL_STAT                                     , RULL(0x130F0155), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_QPPM_DPLL_STAT                                     , RULL(0x140F0155), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_QPPM_DPLL_STAT                                     , RULL(0x150F0155), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+
+REG64( EQ_QPPM_ERR                                             , RULL(0x100F0121), SH_UNT_EQ       ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( EQ_0_QPPM_ERR                                           , RULL(0x100F0121), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( EQ_1_QPPM_ERR                                           , RULL(0x110F0121), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( EQ_2_QPPM_ERR                                           , RULL(0x120F0121), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( EQ_3_QPPM_ERR                                           , RULL(0x130F0121), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( EQ_4_QPPM_ERR                                           , RULL(0x140F0121), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( EQ_5_QPPM_ERR                                           , RULL(0x150F0121), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_WCLEAR );
+
+REG64( EQ_QPPM_ERRMSK                                          , RULL(0x100F0122), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_QPPM_ERRMSK                                        , RULL(0x100F0122), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_QPPM_ERRMSK                                        , RULL(0x110F0122), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_QPPM_ERRMSK                                        , RULL(0x120F0122), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_QPPM_ERRMSK                                        , RULL(0x130F0122), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_QPPM_ERRMSK                                        , RULL(0x140F0122), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_QPPM_ERRMSK                                        , RULL(0x150F0122), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+
+REG64( EQ_QPPM_ERRSUM                                          , RULL(0x100F0120), SH_UNT_EQ       ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( EQ_0_QPPM_ERRSUM                                        , RULL(0x100F0120), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( EQ_1_QPPM_ERRSUM                                        , RULL(0x110F0120), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( EQ_2_QPPM_ERRSUM                                        , RULL(0x120F0120), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( EQ_3_QPPM_ERRSUM                                        , RULL(0x130F0120), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( EQ_4_QPPM_ERRSUM                                        , RULL(0x140F0120), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM_WCLEAR );
+REG64( EQ_5_QPPM_ERRSUM                                        , RULL(0x150F0120), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM_WCLEAR );
+
+REG64( EQ_QPPM_EXCGCR                                          , RULL(0x100F0165), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_QPPM_EXCGCR_CLEAR                                    , RULL(0x100F0166), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_QPPM_EXCGCR_OR                                       , RULL(0x100F0167), SH_UNT_EQ       , SH_ACS_SCOM2_OR  );
+REG64( EQ_0_QPPM_EXCGCR                                        , RULL(0x100F0165), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_0_QPPM_EXCGCR_CLEAR                                  , RULL(0x100F0166), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_0_QPPM_EXCGCR_OR                                     , RULL(0x100F0167), SH_UNT_EQ_0     , SH_ACS_SCOM2_OR  );
+REG64( EQ_1_QPPM_EXCGCR                                        , RULL(0x110F0165), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_QPPM_EXCGCR_CLEAR                                  , RULL(0x110F0166), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_1_QPPM_EXCGCR_OR                                     , RULL(0x110F0167), SH_UNT_EQ_1     , SH_ACS_SCOM2_OR  );
+REG64( EQ_2_QPPM_EXCGCR                                        , RULL(0x120F0165), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_QPPM_EXCGCR_CLEAR                                  , RULL(0x120F0166), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_2_QPPM_EXCGCR_OR                                     , RULL(0x120F0167), SH_UNT_EQ_2     , SH_ACS_SCOM2_OR  );
+REG64( EQ_3_QPPM_EXCGCR                                        , RULL(0x130F0165), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_QPPM_EXCGCR_CLEAR                                  , RULL(0x130F0166), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_3_QPPM_EXCGCR_OR                                     , RULL(0x130F0167), SH_UNT_EQ_3     , SH_ACS_SCOM2_OR  );
+REG64( EQ_4_QPPM_EXCGCR                                        , RULL(0x140F0165), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_QPPM_EXCGCR_CLEAR                                  , RULL(0x140F0166), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_4_QPPM_EXCGCR_OR                                     , RULL(0x140F0167), SH_UNT_EQ_4     , SH_ACS_SCOM2_OR  );
+REG64( EQ_5_QPPM_EXCGCR                                        , RULL(0x150F0165), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_QPPM_EXCGCR_CLEAR                                  , RULL(0x150F0166), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_5_QPPM_EXCGCR_OR                                     , RULL(0x150F0167), SH_UNT_EQ_5     , SH_ACS_SCOM2_OR  );
+
+REG64( EQ_QPPM_OCCHB                                           , RULL(0x100F015F), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_QPPM_OCCHB                                         , RULL(0x100F015F), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_QPPM_OCCHB                                         , RULL(0x110F015F), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_QPPM_OCCHB                                         , RULL(0x120F015F), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_QPPM_OCCHB                                         , RULL(0x130F015F), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_QPPM_OCCHB                                         , RULL(0x140F015F), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_QPPM_OCCHB                                         , RULL(0x150F015F), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+
+REG64( EQ_QPPM_QACCR                                           , RULL(0x100F0160), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_QPPM_QACCR_CLEAR                                     , RULL(0x100F0161), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_QPPM_QACCR_OR                                        , RULL(0x100F0162), SH_UNT_EQ       , SH_ACS_SCOM2_OR  );
+REG64( EQ_0_QPPM_QACCR                                         , RULL(0x100F0160), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_0_QPPM_QACCR_CLEAR                                   , RULL(0x100F0161), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_0_QPPM_QACCR_OR                                      , RULL(0x100F0162), SH_UNT_EQ_0     , SH_ACS_SCOM2_OR  );
+REG64( EQ_1_QPPM_QACCR                                         , RULL(0x110F0160), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_QPPM_QACCR_CLEAR                                   , RULL(0x110F0161), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_1_QPPM_QACCR_OR                                      , RULL(0x110F0162), SH_UNT_EQ_1     , SH_ACS_SCOM2_OR  );
+REG64( EQ_2_QPPM_QACCR                                         , RULL(0x120F0160), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_QPPM_QACCR_CLEAR                                   , RULL(0x120F0161), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_2_QPPM_QACCR_OR                                      , RULL(0x120F0162), SH_UNT_EQ_2     , SH_ACS_SCOM2_OR  );
+REG64( EQ_3_QPPM_QACCR                                         , RULL(0x130F0160), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_QPPM_QACCR_CLEAR                                   , RULL(0x130F0161), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_3_QPPM_QACCR_OR                                      , RULL(0x130F0162), SH_UNT_EQ_3     , SH_ACS_SCOM2_OR  );
+REG64( EQ_4_QPPM_QACCR                                         , RULL(0x140F0160), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_QPPM_QACCR_CLEAR                                   , RULL(0x140F0161), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_4_QPPM_QACCR_OR                                      , RULL(0x140F0162), SH_UNT_EQ_4     , SH_ACS_SCOM2_OR  );
+REG64( EQ_5_QPPM_QACCR                                         , RULL(0x150F0160), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_QPPM_QACCR_CLEAR                                   , RULL(0x150F0161), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_5_QPPM_QACCR_OR                                      , RULL(0x150F0162), SH_UNT_EQ_5     , SH_ACS_SCOM2_OR  );
+
+REG64( EQ_QPPM_QACSR                                           , RULL(0x100F0163), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_QPPM_QACSR                                         , RULL(0x100F0163), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_QPPM_QACSR                                         , RULL(0x110F0163), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_QPPM_QACSR                                         , RULL(0x120F0163), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_QPPM_QACSR                                         , RULL(0x130F0163), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_QPPM_QACSR                                         , RULL(0x140F0163), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_QPPM_QACSR                                         , RULL(0x150F0163), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+
+REG64( EQ_QPPM_QCCR_SCOM                                       , RULL(0x100F01BD), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_QPPM_QCCR_SCOM1                                      , RULL(0x100F01BE), SH_UNT_EQ       , SH_ACS_SCOM1     );
+REG64( EQ_QPPM_QCCR_SCOM2                                      , RULL(0x100F01BF), SH_UNT_EQ       , SH_ACS_SCOM2     );
+REG64( EQ_0_QPPM_QCCR_SCOM                                     , RULL(0x100F01BD), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_0_QPPM_QCCR_SCOM1                                    , RULL(0x100F01BE), SH_UNT_EQ_0     , SH_ACS_SCOM1     );
+REG64( EQ_0_QPPM_QCCR_SCOM2                                    , RULL(0x100F01BF), SH_UNT_EQ_0     , SH_ACS_SCOM2     );
+REG64( EQ_1_QPPM_QCCR_SCOM                                     , RULL(0x110F01BD), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_1_QPPM_QCCR_SCOM1                                    , RULL(0x110F01BE), SH_UNT_EQ_1     , SH_ACS_SCOM1     );
+REG64( EQ_1_QPPM_QCCR_SCOM2                                    , RULL(0x110F01BF), SH_UNT_EQ_1     , SH_ACS_SCOM2     );
+REG64( EQ_2_QPPM_QCCR_SCOM                                     , RULL(0x120F01BD), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_2_QPPM_QCCR_SCOM1                                    , RULL(0x120F01BE), SH_UNT_EQ_2     , SH_ACS_SCOM1     );
+REG64( EQ_2_QPPM_QCCR_SCOM2                                    , RULL(0x120F01BF), SH_UNT_EQ_2     , SH_ACS_SCOM2     );
+REG64( EQ_3_QPPM_QCCR_SCOM                                     , RULL(0x130F01BD), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_3_QPPM_QCCR_SCOM1                                    , RULL(0x130F01BE), SH_UNT_EQ_3     , SH_ACS_SCOM1     );
+REG64( EQ_3_QPPM_QCCR_SCOM2                                    , RULL(0x130F01BF), SH_UNT_EQ_3     , SH_ACS_SCOM2     );
+REG64( EQ_4_QPPM_QCCR_SCOM                                     , RULL(0x140F01BD), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_4_QPPM_QCCR_SCOM1                                    , RULL(0x140F01BE), SH_UNT_EQ_4     , SH_ACS_SCOM1     );
+REG64( EQ_4_QPPM_QCCR_SCOM2                                    , RULL(0x140F01BF), SH_UNT_EQ_4     , SH_ACS_SCOM2     );
+REG64( EQ_5_QPPM_QCCR_SCOM                                     , RULL(0x150F01BD), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EQ_5_QPPM_QCCR_SCOM1                                    , RULL(0x150F01BE), SH_UNT_EQ_5     , SH_ACS_SCOM1     );
+REG64( EQ_5_QPPM_QCCR_SCOM2                                    , RULL(0x150F01BF), SH_UNT_EQ_5     , SH_ACS_SCOM2     );
+
+REG64( EQ_QPPM_QPMMR                                           , RULL(0x100F0103), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_QPPM_QPMMR_CLEAR                                     , RULL(0x100F0104), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_QPPM_QPMMR_OR                                        , RULL(0x100F0105), SH_UNT_EQ       , SH_ACS_SCOM2_OR  );
+REG64( EQ_0_QPPM_QPMMR                                         , RULL(0x100F0103), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_0_QPPM_QPMMR_CLEAR                                   , RULL(0x100F0104), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_0_QPPM_QPMMR_OR                                      , RULL(0x100F0105), SH_UNT_EQ_0     , SH_ACS_SCOM2_OR  );
+REG64( EQ_1_QPPM_QPMMR                                         , RULL(0x110F0103), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_QPPM_QPMMR_CLEAR                                   , RULL(0x110F0104), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_1_QPPM_QPMMR_OR                                      , RULL(0x110F0105), SH_UNT_EQ_1     , SH_ACS_SCOM2_OR  );
+REG64( EQ_2_QPPM_QPMMR                                         , RULL(0x120F0103), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_QPPM_QPMMR_CLEAR                                   , RULL(0x120F0104), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_2_QPPM_QPMMR_OR                                      , RULL(0x120F0105), SH_UNT_EQ_2     , SH_ACS_SCOM2_OR  );
+REG64( EQ_3_QPPM_QPMMR                                         , RULL(0x130F0103), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_QPPM_QPMMR_CLEAR                                   , RULL(0x130F0104), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_3_QPPM_QPMMR_OR                                      , RULL(0x130F0105), SH_UNT_EQ_3     , SH_ACS_SCOM2_OR  );
+REG64( EQ_4_QPPM_QPMMR                                         , RULL(0x140F0103), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_QPPM_QPMMR_CLEAR                                   , RULL(0x140F0104), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_4_QPPM_QPMMR_OR                                      , RULL(0x140F0105), SH_UNT_EQ_4     , SH_ACS_SCOM2_OR  );
+REG64( EQ_5_QPPM_QPMMR                                         , RULL(0x150F0103), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_QPPM_QPMMR_CLEAR                                   , RULL(0x150F0104), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM1_CLEAR );
+REG64( EQ_5_QPPM_QPMMR_OR                                      , RULL(0x150F0105), SH_UNT_EQ_5     , SH_ACS_SCOM2_OR  );
+
+REG64( EQ_QPPM_VDMCFGR                                         , RULL(0x100F01B6), SH_UNT_EQ       , SH_ACS_SCOM_RW   );
+REG64( EQ_0_QPPM_VDMCFGR                                       , RULL(0x100F01B6), SH_UNT_EQ_0     , SH_ACS_SCOM_RW   );
+REG64( EQ_1_QPPM_VDMCFGR                                       , RULL(0x110F01B6), SH_UNT_EQ_1     , SH_ACS_SCOM_RW   );
+REG64( EQ_2_QPPM_VDMCFGR                                       , RULL(0x120F01B6), SH_UNT_EQ_2     , SH_ACS_SCOM_RW   );
+REG64( EQ_3_QPPM_VDMCFGR                                       , RULL(0x130F01B6), SH_UNT_EQ_3     , SH_ACS_SCOM_RW   );
+REG64( EQ_4_QPPM_VDMCFGR                                       , RULL(0x140F01B6), SH_UNT_EQ_4     , SH_ACS_SCOM_RW   );
+REG64( EQ_5_QPPM_VDMCFGR                                       , RULL(0x150F01B6), SH_UNT_EQ_5     , SH_ACS_SCOM_RW   );
+
+REG64( EQ_QPPM_VOLT_CHAR                                       , RULL(0x100F01BB), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_QPPM_VOLT_CHAR                                     , RULL(0x100F01BB), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_QPPM_VOLT_CHAR                                     , RULL(0x110F01BB), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_QPPM_VOLT_CHAR                                     , RULL(0x120F01BB), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_QPPM_VOLT_CHAR                                     , RULL(0x130F01BB), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_QPPM_VOLT_CHAR                                     , RULL(0x140F01BB), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_QPPM_VOLT_CHAR                                     , RULL(0x150F01BB), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+
+REG64( C_RAM_CTRL                                              , RULL(0x20010A4F), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_RAM_CTRL                                            , RULL(0x20010A4F), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_RAM_CTRL                                            , RULL(0x21010A4F), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_RAM_CTRL                                            , RULL(0x22010A4F), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_RAM_CTRL                                            , RULL(0x23010A4F), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_RAM_CTRL                                            , RULL(0x24010A4F), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_RAM_CTRL                                            , RULL(0x25010A4F), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_RAM_CTRL                                            , RULL(0x26010A4F), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_RAM_CTRL                                            , RULL(0x27010A4F), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_RAM_CTRL                                            , RULL(0x28010A4F), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_RAM_CTRL                                            , RULL(0x29010A4F), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_RAM_CTRL                                           , RULL(0x2A010A4F), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_RAM_CTRL                                           , RULL(0x2B010A4F), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_RAM_CTRL                                           , RULL(0x2C010A4F), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_RAM_CTRL                                           , RULL(0x2D010A4F), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_RAM_CTRL                                           , RULL(0x2E010A4F), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_RAM_CTRL                                           , RULL(0x2F010A4F), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_RAM_CTRL                                           , RULL(0x30010A4F), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_RAM_CTRL                                           , RULL(0x31010A4F), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_RAM_CTRL                                           , RULL(0x32010A4F), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_RAM_CTRL                                           , RULL(0x33010A4F), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_RAM_CTRL                                           , RULL(0x34010A4F), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_RAM_CTRL                                           , RULL(0x35010A4F), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_RAM_CTRL                                           , RULL(0x36010A4F), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_RAM_CTRL                                           , RULL(0x37010A4F), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_RAM_CTRL                                             , RULL(0x20010A4F), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A4F,
+REG64( EX_0_RAM_CTRL                                           , RULL(0x20010A4F), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A4F,
+REG64( EX_1_RAM_CTRL                                           , RULL(0x22010A4F), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010A4F,
+REG64( EX_2_RAM_CTRL                                           , RULL(0x24010A4F), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010A4F,
+REG64( EX_3_RAM_CTRL                                           , RULL(0x26010A4F), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010A4F,
+REG64( EX_4_RAM_CTRL                                           , RULL(0x28010A4F), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010A4F,
+REG64( EX_5_RAM_CTRL                                           , RULL(0x2A010A4F), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010A4F,
+REG64( EX_6_RAM_CTRL                                           , RULL(0x2C010A4F), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010A4F,
+REG64( EX_7_RAM_CTRL                                           , RULL(0x2E010A4F), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010A4F,
+REG64( EX_8_RAM_CTRL                                           , RULL(0x30010A4F), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010A4F,
+REG64( EX_9_RAM_CTRL                                           , RULL(0x32010A4F), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010A4F,
+REG64( EX_10_RAM_CTRL                                          , RULL(0x34010A4F), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010A4F,
+REG64( EX_11_RAM_CTRL                                          , RULL(0x36010A4F), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010A4F,
+
+REG64( C_RAM_MODEREG                                           , RULL(0x20010A4E), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_RAM_MODEREG                                         , RULL(0x20010A4E), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_RAM_MODEREG                                         , RULL(0x21010A4E), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_RAM_MODEREG                                         , RULL(0x22010A4E), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_RAM_MODEREG                                         , RULL(0x23010A4E), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_RAM_MODEREG                                         , RULL(0x24010A4E), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_RAM_MODEREG                                         , RULL(0x25010A4E), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_RAM_MODEREG                                         , RULL(0x26010A4E), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_RAM_MODEREG                                         , RULL(0x27010A4E), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_RAM_MODEREG                                         , RULL(0x28010A4E), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_RAM_MODEREG                                         , RULL(0x29010A4E), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_RAM_MODEREG                                        , RULL(0x2A010A4E), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_RAM_MODEREG                                        , RULL(0x2B010A4E), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_RAM_MODEREG                                        , RULL(0x2C010A4E), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_RAM_MODEREG                                        , RULL(0x2D010A4E), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_RAM_MODEREG                                        , RULL(0x2E010A4E), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_RAM_MODEREG                                        , RULL(0x2F010A4E), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_RAM_MODEREG                                        , RULL(0x30010A4E), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_RAM_MODEREG                                        , RULL(0x31010A4E), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_RAM_MODEREG                                        , RULL(0x32010A4E), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_RAM_MODEREG                                        , RULL(0x33010A4E), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_RAM_MODEREG                                        , RULL(0x34010A4E), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_RAM_MODEREG                                        , RULL(0x35010A4E), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_RAM_MODEREG                                        , RULL(0x36010A4E), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_RAM_MODEREG                                        , RULL(0x37010A4E), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_RAM_MODEREG                                          , RULL(0x20010A4E), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A4E,
+REG64( EX_0_RAM_MODEREG                                        , RULL(0x20010A4E), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A4E,
+REG64( EX_1_RAM_MODEREG                                        , RULL(0x22010A4E), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010A4E,
+REG64( EX_2_RAM_MODEREG                                        , RULL(0x24010A4E), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010A4E,
+REG64( EX_3_RAM_MODEREG                                        , RULL(0x26010A4E), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010A4E,
+REG64( EX_4_RAM_MODEREG                                        , RULL(0x28010A4E), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010A4E,
+REG64( EX_5_RAM_MODEREG                                        , RULL(0x2A010A4E), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010A4E,
+REG64( EX_6_RAM_MODEREG                                        , RULL(0x2C010A4E), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010A4E,
+REG64( EX_7_RAM_MODEREG                                        , RULL(0x2E010A4E), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010A4E,
+REG64( EX_8_RAM_MODEREG                                        , RULL(0x30010A4E), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010A4E,
+REG64( EX_9_RAM_MODEREG                                        , RULL(0x32010A4E), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010A4E,
+REG64( EX_10_RAM_MODEREG                                       , RULL(0x34010A4E), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010A4E,
+REG64( EX_11_RAM_MODEREG                                       , RULL(0x36010A4E), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010A4E,
+
+REG64( C_RAM_STATUS                                            , RULL(0x20010A50), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_RAM_STATUS                                          , RULL(0x20010A50), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_RAM_STATUS                                          , RULL(0x21010A50), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_RAM_STATUS                                          , RULL(0x22010A50), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_RAM_STATUS                                          , RULL(0x23010A50), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_RAM_STATUS                                          , RULL(0x24010A50), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_RAM_STATUS                                          , RULL(0x25010A50), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_RAM_STATUS                                          , RULL(0x26010A50), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_RAM_STATUS                                          , RULL(0x27010A50), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_RAM_STATUS                                          , RULL(0x28010A50), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_RAM_STATUS                                          , RULL(0x29010A50), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_RAM_STATUS                                         , RULL(0x2A010A50), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_RAM_STATUS                                         , RULL(0x2B010A50), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_RAM_STATUS                                         , RULL(0x2C010A50), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_RAM_STATUS                                         , RULL(0x2D010A50), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_RAM_STATUS                                         , RULL(0x2E010A50), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_RAM_STATUS                                         , RULL(0x2F010A50), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_RAM_STATUS                                         , RULL(0x30010A50), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_RAM_STATUS                                         , RULL(0x31010A50), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_RAM_STATUS                                         , RULL(0x32010A50), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_RAM_STATUS                                         , RULL(0x33010A50), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_RAM_STATUS                                         , RULL(0x34010A50), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_RAM_STATUS                                         , RULL(0x35010A50), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_RAM_STATUS                                         , RULL(0x36010A50), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_RAM_STATUS                                         , RULL(0x37010A50), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_RAM_STATUS                                      , RULL(0x20010A50), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010A50,
+REG64( EX_10_L2_RAM_STATUS                                     , RULL(0x34010A50), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010A50,
+REG64( EX_11_L2_RAM_STATUS                                     , RULL(0x36010A50), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010A50,
+REG64( EX_1_L2_RAM_STATUS                                      , RULL(0x22010A50), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010A50,
+REG64( EX_2_L2_RAM_STATUS                                      , RULL(0x24010A50), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010A50,
+REG64( EX_3_L2_RAM_STATUS                                      , RULL(0x26010A50), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010A50,
+REG64( EX_4_L2_RAM_STATUS                                      , RULL(0x28010A50), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010A50,
+REG64( EX_5_L2_RAM_STATUS                                      , RULL(0x2A010A50), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010A50,
+REG64( EX_6_L2_RAM_STATUS                                      , RULL(0x2C010A50), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010A50,
+REG64( EX_7_L2_RAM_STATUS                                      , RULL(0x2E010A50), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010A50,
+REG64( EX_8_L2_RAM_STATUS                                      , RULL(0x30010A50), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010A50,
+REG64( EX_9_L2_RAM_STATUS                                      , RULL(0x32010A50), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010A50,
+REG64( EX_L2_RAM_STATUS                                        , RULL(0x20010A50), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010A50,
+
+REG64( C_RAS_MODEREG                                           , RULL(0x20010A9D), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_RAS_MODEREG                                         , RULL(0x20010A9D), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_RAS_MODEREG                                         , RULL(0x21010A9D), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_RAS_MODEREG                                         , RULL(0x22010A9D), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_RAS_MODEREG                                         , RULL(0x23010A9D), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_RAS_MODEREG                                         , RULL(0x24010A9D), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_RAS_MODEREG                                         , RULL(0x25010A9D), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_RAS_MODEREG                                         , RULL(0x26010A9D), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_RAS_MODEREG                                         , RULL(0x27010A9D), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_RAS_MODEREG                                         , RULL(0x28010A9D), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_RAS_MODEREG                                         , RULL(0x29010A9D), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_RAS_MODEREG                                        , RULL(0x2A010A9D), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_RAS_MODEREG                                        , RULL(0x2B010A9D), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_RAS_MODEREG                                        , RULL(0x2C010A9D), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_RAS_MODEREG                                        , RULL(0x2D010A9D), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_RAS_MODEREG                                        , RULL(0x2E010A9D), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_RAS_MODEREG                                        , RULL(0x2F010A9D), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_RAS_MODEREG                                        , RULL(0x30010A9D), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_RAS_MODEREG                                        , RULL(0x31010A9D), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_RAS_MODEREG                                        , RULL(0x32010A9D), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_RAS_MODEREG                                        , RULL(0x33010A9D), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_RAS_MODEREG                                        , RULL(0x34010A9D), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_RAS_MODEREG                                        , RULL(0x35010A9D), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_RAS_MODEREG                                        , RULL(0x36010A9D), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_RAS_MODEREG                                        , RULL(0x37010A9D), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_RAS_MODEREG                                     , RULL(0x20010A9D), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A9D,
+REG64( EX_10_L2_RAS_MODEREG                                    , RULL(0x34010A9D), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010A9D,
+REG64( EX_11_L2_RAS_MODEREG                                    , RULL(0x36010A9D), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010A9D,
+REG64( EX_1_L2_RAS_MODEREG                                     , RULL(0x22010A9D), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010A9D,
+REG64( EX_2_L2_RAS_MODEREG                                     , RULL(0x24010A9D), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010A9D,
+REG64( EX_3_L2_RAS_MODEREG                                     , RULL(0x26010A9D), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010A9D,
+REG64( EX_4_L2_RAS_MODEREG                                     , RULL(0x28010A9D), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010A9D,
+REG64( EX_5_L2_RAS_MODEREG                                     , RULL(0x2A010A9D), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010A9D,
+REG64( EX_6_L2_RAS_MODEREG                                     , RULL(0x2C010A9D), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010A9D,
+REG64( EX_7_L2_RAS_MODEREG                                     , RULL(0x2E010A9D), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010A9D,
+REG64( EX_8_L2_RAS_MODEREG                                     , RULL(0x30010A9D), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010A9D,
+REG64( EX_9_L2_RAS_MODEREG                                     , RULL(0x32010A9D), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010A9D,
+REG64( EX_L2_RAS_MODEREG                                       , RULL(0x20010A9D), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A9D,
+
+REG64( C_RAS_STATUS                                            , RULL(0x20010A02), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_RAS_STATUS                                          , RULL(0x20010A02), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_RAS_STATUS                                          , RULL(0x21010A02), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_RAS_STATUS                                          , RULL(0x22010A02), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_RAS_STATUS                                          , RULL(0x23010A02), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_RAS_STATUS                                          , RULL(0x24010A02), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_RAS_STATUS                                          , RULL(0x25010A02), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_RAS_STATUS                                          , RULL(0x26010A02), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_RAS_STATUS                                          , RULL(0x27010A02), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_RAS_STATUS                                          , RULL(0x28010A02), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_RAS_STATUS                                          , RULL(0x29010A02), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_RAS_STATUS                                         , RULL(0x2A010A02), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_RAS_STATUS                                         , RULL(0x2B010A02), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_RAS_STATUS                                         , RULL(0x2C010A02), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_RAS_STATUS                                         , RULL(0x2D010A02), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_RAS_STATUS                                         , RULL(0x2E010A02), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_RAS_STATUS                                         , RULL(0x2F010A02), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_RAS_STATUS                                         , RULL(0x30010A02), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_RAS_STATUS                                         , RULL(0x31010A02), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_RAS_STATUS                                         , RULL(0x32010A02), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_RAS_STATUS                                         , RULL(0x33010A02), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_RAS_STATUS                                         , RULL(0x34010A02), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_RAS_STATUS                                         , RULL(0x35010A02), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_RAS_STATUS                                         , RULL(0x36010A02), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_RAS_STATUS                                         , RULL(0x37010A02), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_RAS_STATUS                                      , RULL(0x20010A02), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010A02,
+REG64( EX_10_L2_RAS_STATUS                                     , RULL(0x34010A02), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010A02,
+REG64( EX_11_L2_RAS_STATUS                                     , RULL(0x36010A02), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010A02,
+REG64( EX_1_L2_RAS_STATUS                                      , RULL(0x22010A02), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010A02,
+REG64( EX_2_L2_RAS_STATUS                                      , RULL(0x24010A02), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010A02,
+REG64( EX_3_L2_RAS_STATUS                                      , RULL(0x26010A02), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010A02,
+REG64( EX_4_L2_RAS_STATUS                                      , RULL(0x28010A02), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010A02,
+REG64( EX_5_L2_RAS_STATUS                                      , RULL(0x2A010A02), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010A02,
+REG64( EX_6_L2_RAS_STATUS                                      , RULL(0x2C010A02), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010A02,
+REG64( EX_7_L2_RAS_STATUS                                      , RULL(0x2E010A02), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010A02,
+REG64( EX_8_L2_RAS_STATUS                                      , RULL(0x30010A02), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010A02,
+REG64( EX_9_L2_RAS_STATUS                                      , RULL(0x32010A02), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010A02,
+REG64( EX_L2_RAS_STATUS                                        , RULL(0x20010A02), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010A02,
+
+REG64( EQ_RD_EPS_REG                                           , RULL(0x10010810), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10010C10,
+REG64( EQ_0_RD_EPS_REG                                         , RULL(0x10010810), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10010C10,
+REG64( EQ_1_RD_EPS_REG                                         , RULL(0x11010810), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11010C10,
+REG64( EQ_2_RD_EPS_REG                                         , RULL(0x12010810), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12010C10,
+REG64( EQ_3_RD_EPS_REG                                         , RULL(0x13010810), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13010C10,
+REG64( EQ_4_RD_EPS_REG                                         , RULL(0x14010810), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14010C10,
+REG64( EQ_5_RD_EPS_REG                                         , RULL(0x15010810), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15010C10,
+REG64( EX_0_L2_RD_EPS_REG                                      , RULL(0x10010810), SH_UNT_EX_0_L2  , SH_ACS_SCOM      );
+REG64( EX_10_L2_RD_EPS_REG                                     , RULL(0x15010810), SH_UNT_EX_10_L2 , SH_ACS_SCOM      );
+REG64( EX_11_L2_RD_EPS_REG                                     , RULL(0x15010C10), SH_UNT_EX_11_L2 , SH_ACS_SCOM      );
+REG64( EX_1_L2_RD_EPS_REG                                      , RULL(0x10010C10), SH_UNT_EX_1_L2  , SH_ACS_SCOM      );
+REG64( EX_2_L2_RD_EPS_REG                                      , RULL(0x11010810), SH_UNT_EX_2_L2  , SH_ACS_SCOM      );
+REG64( EX_3_L2_RD_EPS_REG                                      , RULL(0x11010C10), SH_UNT_EX_3_L2  , SH_ACS_SCOM      );
+REG64( EX_4_L2_RD_EPS_REG                                      , RULL(0x12010810), SH_UNT_EX_4_L2  , SH_ACS_SCOM      );
+REG64( EX_5_L2_RD_EPS_REG                                      , RULL(0x12010C10), SH_UNT_EX_5_L2  , SH_ACS_SCOM      );
+REG64( EX_6_L2_RD_EPS_REG                                      , RULL(0x13010810), SH_UNT_EX_6_L2  , SH_ACS_SCOM      );
+REG64( EX_7_L2_RD_EPS_REG                                      , RULL(0x13010C10), SH_UNT_EX_7_L2  , SH_ACS_SCOM      );
+REG64( EX_8_L2_RD_EPS_REG                                      , RULL(0x14010810), SH_UNT_EX_8_L2  , SH_ACS_SCOM      );
+REG64( EX_9_L2_RD_EPS_REG                                      , RULL(0x14010C10), SH_UNT_EX_9_L2  , SH_ACS_SCOM      );
+REG64( EX_L2_RD_EPS_REG                                        , RULL(0x10010810), SH_UNT_EX_L2    , SH_ACS_SCOM      );
+
+REG64( C_RECOV_FWD_PROG_CTRL                                   , RULL(0x20010A4B), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_RECOV_FWD_PROG_CTRL                                 , RULL(0x20010A4B), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_RECOV_FWD_PROG_CTRL                                 , RULL(0x21010A4B), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_RECOV_FWD_PROG_CTRL                                 , RULL(0x22010A4B), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_RECOV_FWD_PROG_CTRL                                 , RULL(0x23010A4B), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_RECOV_FWD_PROG_CTRL                                 , RULL(0x24010A4B), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_RECOV_FWD_PROG_CTRL                                 , RULL(0x25010A4B), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_RECOV_FWD_PROG_CTRL                                 , RULL(0x26010A4B), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_RECOV_FWD_PROG_CTRL                                 , RULL(0x27010A4B), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_RECOV_FWD_PROG_CTRL                                 , RULL(0x28010A4B), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_RECOV_FWD_PROG_CTRL                                 , RULL(0x29010A4B), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_RECOV_FWD_PROG_CTRL                                , RULL(0x2A010A4B), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_RECOV_FWD_PROG_CTRL                                , RULL(0x2B010A4B), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_RECOV_FWD_PROG_CTRL                                , RULL(0x2C010A4B), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_RECOV_FWD_PROG_CTRL                                , RULL(0x2D010A4B), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_RECOV_FWD_PROG_CTRL                                , RULL(0x2E010A4B), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_RECOV_FWD_PROG_CTRL                                , RULL(0x2F010A4B), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_RECOV_FWD_PROG_CTRL                                , RULL(0x30010A4B), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_RECOV_FWD_PROG_CTRL                                , RULL(0x31010A4B), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_RECOV_FWD_PROG_CTRL                                , RULL(0x32010A4B), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_RECOV_FWD_PROG_CTRL                                , RULL(0x33010A4B), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_RECOV_FWD_PROG_CTRL                                , RULL(0x34010A4B), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_RECOV_FWD_PROG_CTRL                                , RULL(0x35010A4B), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_RECOV_FWD_PROG_CTRL                                , RULL(0x36010A4B), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_RECOV_FWD_PROG_CTRL                                , RULL(0x37010A4B), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_RECOV_FWD_PROG_CTRL                             , RULL(0x20010A4B), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010A4B,
+REG64( EX_10_L2_RECOV_FWD_PROG_CTRL                            , RULL(0x34010A4B), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010A4B,
+REG64( EX_11_L2_RECOV_FWD_PROG_CTRL                            , RULL(0x36010A4B), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010A4B,
+REG64( EX_1_L2_RECOV_FWD_PROG_CTRL                             , RULL(0x22010A4B), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010A4B,
+REG64( EX_2_L2_RECOV_FWD_PROG_CTRL                             , RULL(0x24010A4B), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010A4B,
+REG64( EX_3_L2_RECOV_FWD_PROG_CTRL                             , RULL(0x26010A4B), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010A4B,
+REG64( EX_4_L2_RECOV_FWD_PROG_CTRL                             , RULL(0x28010A4B), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010A4B,
+REG64( EX_5_L2_RECOV_FWD_PROG_CTRL                             , RULL(0x2A010A4B), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010A4B,
+REG64( EX_6_L2_RECOV_FWD_PROG_CTRL                             , RULL(0x2C010A4B), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010A4B,
+REG64( EX_7_L2_RECOV_FWD_PROG_CTRL                             , RULL(0x2E010A4B), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010A4B,
+REG64( EX_8_L2_RECOV_FWD_PROG_CTRL                             , RULL(0x30010A4B), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010A4B,
+REG64( EX_9_L2_RECOV_FWD_PROG_CTRL                             , RULL(0x32010A4B), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010A4B,
+REG64( EX_L2_RECOV_FWD_PROG_CTRL                               , RULL(0x20010A4B), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010A4B,
+
+REG64( C_RECOV_INTERRUPT_REG                                   , RULL(0x200F001B), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_RECOV_INTERRUPT_REG                                 , RULL(0x200F001B), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_RECOV_INTERRUPT_REG                                 , RULL(0x210F001B), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_RECOV_INTERRUPT_REG                                 , RULL(0x220F001B), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_RECOV_INTERRUPT_REG                                 , RULL(0x230F001B), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_RECOV_INTERRUPT_REG                                 , RULL(0x240F001B), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_RECOV_INTERRUPT_REG                                 , RULL(0x250F001B), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_RECOV_INTERRUPT_REG                                 , RULL(0x260F001B), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_RECOV_INTERRUPT_REG                                 , RULL(0x270F001B), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_RECOV_INTERRUPT_REG                                 , RULL(0x280F001B), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_RECOV_INTERRUPT_REG                                 , RULL(0x290F001B), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_RECOV_INTERRUPT_REG                                , RULL(0x2A0F001B), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_RECOV_INTERRUPT_REG                                , RULL(0x2B0F001B), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_RECOV_INTERRUPT_REG                                , RULL(0x2C0F001B), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_RECOV_INTERRUPT_REG                                , RULL(0x2D0F001B), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_RECOV_INTERRUPT_REG                                , RULL(0x2E0F001B), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_RECOV_INTERRUPT_REG                                , RULL(0x2F0F001B), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_RECOV_INTERRUPT_REG                                , RULL(0x300F001B), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_RECOV_INTERRUPT_REG                                , RULL(0x310F001B), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_RECOV_INTERRUPT_REG                                , RULL(0x320F001B), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_RECOV_INTERRUPT_REG                                , RULL(0x330F001B), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_RECOV_INTERRUPT_REG                                , RULL(0x340F001B), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_RECOV_INTERRUPT_REG                                , RULL(0x350F001B), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_RECOV_INTERRUPT_REG                                , RULL(0x360F001B), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_RECOV_INTERRUPT_REG                                , RULL(0x370F001B), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_RECOV_INTERRUPT_REG                                  , RULL(0x100F001B), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_RECOV_INTERRUPT_REG                                , RULL(0x100F001B), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_RECOV_INTERRUPT_REG                                , RULL(0x110F001B), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_RECOV_INTERRUPT_REG                                , RULL(0x120F001B), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_RECOV_INTERRUPT_REG                                , RULL(0x130F001B), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_RECOV_INTERRUPT_REG                                , RULL(0x140F001B), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_RECOV_INTERRUPT_REG                                , RULL(0x150F001B), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_RECOV_INTERRUPT_REG                                  , RULL(0x200F001B), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F001B,
+REG64( EX_0_RECOV_INTERRUPT_REG                                , RULL(0x200F001B), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F001B,
+REG64( EX_1_RECOV_INTERRUPT_REG                                , RULL(0x230F001B), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F001B,
+REG64( EX_2_RECOV_INTERRUPT_REG                                , RULL(0x240F001B), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F001B,
+REG64( EX_3_RECOV_INTERRUPT_REG                                , RULL(0x260F001B), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F001B,
+REG64( EX_4_RECOV_INTERRUPT_REG                                , RULL(0x280F001B), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F001B,
+REG64( EX_5_RECOV_INTERRUPT_REG                                , RULL(0x2A0F001B), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F001B,
+REG64( EX_6_RECOV_INTERRUPT_REG                                , RULL(0x2C0F001B), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F001B,
+REG64( EX_7_RECOV_INTERRUPT_REG                                , RULL(0x2E0F001B), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F001B,
+REG64( EX_8_RECOV_INTERRUPT_REG                                , RULL(0x300F001B), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F001B,
+REG64( EX_9_RECOV_INTERRUPT_REG                                , RULL(0x320F001B), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F001B,
+REG64( EX_10_RECOV_INTERRUPT_REG                               , RULL(0x340F001B), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F001B,
+REG64( EX_11_RECOV_INTERRUPT_REG                               , RULL(0x360F001B), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F001B,
+
+REG64( C_RECOV_THOLD                                           , RULL(0x20010A4C), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_RECOV_THOLD                                         , RULL(0x20010A4C), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_RECOV_THOLD                                         , RULL(0x21010A4C), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_RECOV_THOLD                                         , RULL(0x22010A4C), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_RECOV_THOLD                                         , RULL(0x23010A4C), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_RECOV_THOLD                                         , RULL(0x24010A4C), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_RECOV_THOLD                                         , RULL(0x25010A4C), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_RECOV_THOLD                                         , RULL(0x26010A4C), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_RECOV_THOLD                                         , RULL(0x27010A4C), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_RECOV_THOLD                                         , RULL(0x28010A4C), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_RECOV_THOLD                                         , RULL(0x29010A4C), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_RECOV_THOLD                                        , RULL(0x2A010A4C), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_RECOV_THOLD                                        , RULL(0x2B010A4C), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_RECOV_THOLD                                        , RULL(0x2C010A4C), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_RECOV_THOLD                                        , RULL(0x2D010A4C), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_RECOV_THOLD                                        , RULL(0x2E010A4C), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_RECOV_THOLD                                        , RULL(0x2F010A4C), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_RECOV_THOLD                                        , RULL(0x30010A4C), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_RECOV_THOLD                                        , RULL(0x31010A4C), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_RECOV_THOLD                                        , RULL(0x32010A4C), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_RECOV_THOLD                                        , RULL(0x33010A4C), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_RECOV_THOLD                                        , RULL(0x34010A4C), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_RECOV_THOLD                                        , RULL(0x35010A4C), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_RECOV_THOLD                                        , RULL(0x36010A4C), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_RECOV_THOLD                                        , RULL(0x37010A4C), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_RECOV_THOLD                                     , RULL(0x20010A4C), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A4C,
+REG64( EX_10_L2_RECOV_THOLD                                    , RULL(0x34010A4C), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010A4C,
+REG64( EX_11_L2_RECOV_THOLD                                    , RULL(0x36010A4C), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010A4C,
+REG64( EX_1_L2_RECOV_THOLD                                     , RULL(0x22010A4C), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010A4C,
+REG64( EX_2_L2_RECOV_THOLD                                     , RULL(0x24010A4C), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010A4C,
+REG64( EX_3_L2_RECOV_THOLD                                     , RULL(0x26010A4C), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010A4C,
+REG64( EX_4_L2_RECOV_THOLD                                     , RULL(0x28010A4C), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010A4C,
+REG64( EX_5_L2_RECOV_THOLD                                     , RULL(0x2A010A4C), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010A4C,
+REG64( EX_6_L2_RECOV_THOLD                                     , RULL(0x2C010A4C), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010A4C,
+REG64( EX_7_L2_RECOV_THOLD                                     , RULL(0x2E010A4C), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010A4C,
+REG64( EX_8_L2_RECOV_THOLD                                     , RULL(0x30010A4C), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010A4C,
+REG64( EX_9_L2_RECOV_THOLD                                     , RULL(0x32010A4C), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010A4C,
+REG64( EX_L2_RECOV_THOLD                                       , RULL(0x20010A4C), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010A4C,
+
+REG64( C_RESET_KEEPER                                          , RULL(0x20010A4A), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_RESET_KEEPER                                        , RULL(0x20010A4A), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_RESET_KEEPER                                        , RULL(0x21010A4A), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_RESET_KEEPER                                        , RULL(0x22010A4A), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_RESET_KEEPER                                        , RULL(0x23010A4A), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_RESET_KEEPER                                        , RULL(0x24010A4A), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_RESET_KEEPER                                        , RULL(0x25010A4A), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_RESET_KEEPER                                        , RULL(0x26010A4A), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_RESET_KEEPER                                        , RULL(0x27010A4A), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_RESET_KEEPER                                        , RULL(0x28010A4A), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_RESET_KEEPER                                        , RULL(0x29010A4A), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_RESET_KEEPER                                       , RULL(0x2A010A4A), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_RESET_KEEPER                                       , RULL(0x2B010A4A), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_RESET_KEEPER                                       , RULL(0x2C010A4A), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_RESET_KEEPER                                       , RULL(0x2D010A4A), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_RESET_KEEPER                                       , RULL(0x2E010A4A), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_RESET_KEEPER                                       , RULL(0x2F010A4A), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_RESET_KEEPER                                       , RULL(0x30010A4A), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_RESET_KEEPER                                       , RULL(0x31010A4A), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_RESET_KEEPER                                       , RULL(0x32010A4A), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_RESET_KEEPER                                       , RULL(0x33010A4A), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_RESET_KEEPER                                       , RULL(0x34010A4A), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_RESET_KEEPER                                       , RULL(0x35010A4A), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_RESET_KEEPER                                       , RULL(0x36010A4A), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_RESET_KEEPER                                       , RULL(0x37010A4A), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_RESET_KEEPER                                    , RULL(0x20010A4A), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010A4A,
+REG64( EX_10_L2_RESET_KEEPER                                   , RULL(0x34010A4A), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010A4A,
+REG64( EX_11_L2_RESET_KEEPER                                   , RULL(0x36010A4A), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010A4A,
+REG64( EX_1_L2_RESET_KEEPER                                    , RULL(0x22010A4A), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010A4A,
+REG64( EX_2_L2_RESET_KEEPER                                    , RULL(0x24010A4A), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010A4A,
+REG64( EX_3_L2_RESET_KEEPER                                    , RULL(0x26010A4A), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010A4A,
+REG64( EX_4_L2_RESET_KEEPER                                    , RULL(0x28010A4A), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010A4A,
+REG64( EX_5_L2_RESET_KEEPER                                    , RULL(0x2A010A4A), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010A4A,
+REG64( EX_6_L2_RESET_KEEPER                                    , RULL(0x2C010A4A), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010A4A,
+REG64( EX_7_L2_RESET_KEEPER                                    , RULL(0x2E010A4A), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010A4A,
+REG64( EX_8_L2_RESET_KEEPER                                    , RULL(0x30010A4A), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010A4A,
+REG64( EX_9_L2_RESET_KEEPER                                    , RULL(0x32010A4A), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010A4A,
+REG64( EX_L2_RESET_KEEPER                                      , RULL(0x20010A4A), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010A4A,
+
+REG64( C_RFIR                                                  , RULL(0x20040001), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_RFIR                                                , RULL(0x20040001), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_RFIR                                                , RULL(0x21040001), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_RFIR                                                , RULL(0x22040001), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_RFIR                                                , RULL(0x23040001), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_RFIR                                                , RULL(0x24040001), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_RFIR                                                , RULL(0x25040001), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_RFIR                                                , RULL(0x26040001), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_RFIR                                                , RULL(0x27040001), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_RFIR                                                , RULL(0x28040001), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_RFIR                                                , RULL(0x29040001), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_RFIR                                               , RULL(0x2A040001), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_RFIR                                               , RULL(0x2B040001), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_RFIR                                               , RULL(0x2C040001), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_RFIR                                               , RULL(0x2D040001), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_RFIR                                               , RULL(0x2E040001), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_RFIR                                               , RULL(0x2F040001), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_RFIR                                               , RULL(0x30040001), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_RFIR                                               , RULL(0x31040001), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_RFIR                                               , RULL(0x32040001), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_RFIR                                               , RULL(0x33040001), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_RFIR                                               , RULL(0x34040001), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_RFIR                                               , RULL(0x35040001), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_RFIR                                               , RULL(0x36040001), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_RFIR                                               , RULL(0x37040001), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_RFIR                                                 , RULL(0x10040001), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_RFIR                                               , RULL(0x10040001), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_RFIR                                               , RULL(0x11040001), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_RFIR                                               , RULL(0x12040001), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_RFIR                                               , RULL(0x13040001), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_RFIR                                               , RULL(0x14040001), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_RFIR                                               , RULL(0x15040001), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_RFIR                                                 , RULL(0x20040001), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21040001,
+REG64( EX_0_RFIR                                               , RULL(0x20040001), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21040001,
+REG64( EX_1_RFIR                                               , RULL(0x22040001), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23040001,
+REG64( EX_2_RFIR                                               , RULL(0x24040001), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25040001,
+REG64( EX_3_RFIR                                               , RULL(0x26040001), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27040001,
+REG64( EX_4_RFIR                                               , RULL(0x28040001), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29040001,
+REG64( EX_5_RFIR                                               , RULL(0x2A040001), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B040001,
+REG64( EX_6_RFIR                                               , RULL(0x2C040001), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D040001,
+REG64( EX_7_RFIR                                               , RULL(0x2E040001), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F040001,
+REG64( EX_8_RFIR                                               , RULL(0x30040001), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31040001,
+REG64( EX_9_RFIR                                               , RULL(0x32040001), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33040001,
+REG64( EX_10_RFIR                                              , RULL(0x34040001), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35040001,
+REG64( EX_11_RFIR                                              , RULL(0x36040001), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37040001,
+
+REG64( C_RING_FENCE_MASK_LATCH_REG                             , RULL(0x20010008), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_RING_FENCE_MASK_LATCH_REG                           , RULL(0x20010008), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_RING_FENCE_MASK_LATCH_REG                           , RULL(0x21010008), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_RING_FENCE_MASK_LATCH_REG                           , RULL(0x22010008), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_RING_FENCE_MASK_LATCH_REG                           , RULL(0x23010008), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_RING_FENCE_MASK_LATCH_REG                           , RULL(0x24010008), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_RING_FENCE_MASK_LATCH_REG                           , RULL(0x25010008), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_RING_FENCE_MASK_LATCH_REG                           , RULL(0x26010008), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_RING_FENCE_MASK_LATCH_REG                           , RULL(0x27010008), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_RING_FENCE_MASK_LATCH_REG                           , RULL(0x28010008), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_RING_FENCE_MASK_LATCH_REG                           , RULL(0x29010008), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_RING_FENCE_MASK_LATCH_REG                          , RULL(0x2A010008), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_RING_FENCE_MASK_LATCH_REG                          , RULL(0x2B010008), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_RING_FENCE_MASK_LATCH_REG                          , RULL(0x2C010008), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_RING_FENCE_MASK_LATCH_REG                          , RULL(0x2D010008), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_RING_FENCE_MASK_LATCH_REG                          , RULL(0x2E010008), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_RING_FENCE_MASK_LATCH_REG                          , RULL(0x2F010008), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_RING_FENCE_MASK_LATCH_REG                          , RULL(0x30010008), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_RING_FENCE_MASK_LATCH_REG                          , RULL(0x31010008), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_RING_FENCE_MASK_LATCH_REG                          , RULL(0x32010008), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_RING_FENCE_MASK_LATCH_REG                          , RULL(0x33010008), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_RING_FENCE_MASK_LATCH_REG                          , RULL(0x34010008), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_RING_FENCE_MASK_LATCH_REG                          , RULL(0x35010008), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_RING_FENCE_MASK_LATCH_REG                          , RULL(0x36010008), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_RING_FENCE_MASK_LATCH_REG                          , RULL(0x37010008), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_RING_FENCE_MASK_LATCH_REG                            , RULL(0x10010008), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_RING_FENCE_MASK_LATCH_REG                          , RULL(0x10010008), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_RING_FENCE_MASK_LATCH_REG                          , RULL(0x11010008), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_RING_FENCE_MASK_LATCH_REG                          , RULL(0x12010008), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_RING_FENCE_MASK_LATCH_REG                          , RULL(0x13010008), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_RING_FENCE_MASK_LATCH_REG                          , RULL(0x14010008), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_RING_FENCE_MASK_LATCH_REG                          , RULL(0x15010008), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_RING_FENCE_MASK_LATCH_REG                            , RULL(0x20010008), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21010008,
+REG64( EX_0_RING_FENCE_MASK_LATCH_REG                          , RULL(0x20010008), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21010008,
+REG64( EX_1_RING_FENCE_MASK_LATCH_REG                          , RULL(0x22010008), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23010008,
+REG64( EX_2_RING_FENCE_MASK_LATCH_REG                          , RULL(0x24010008), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25010008,
+REG64( EX_3_RING_FENCE_MASK_LATCH_REG                          , RULL(0x26010008), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27010008,
+REG64( EX_4_RING_FENCE_MASK_LATCH_REG                          , RULL(0x28010008), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29010008,
+REG64( EX_5_RING_FENCE_MASK_LATCH_REG                          , RULL(0x2A010008), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B010008,
+REG64( EX_6_RING_FENCE_MASK_LATCH_REG                          , RULL(0x2C010008), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D010008,
+REG64( EX_7_RING_FENCE_MASK_LATCH_REG                          , RULL(0x2E010008), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F010008,
+REG64( EX_8_RING_FENCE_MASK_LATCH_REG                          , RULL(0x30010008), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31010008,
+REG64( EX_9_RING_FENCE_MASK_LATCH_REG                          , RULL(0x32010008), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33010008,
+REG64( EX_10_RING_FENCE_MASK_LATCH_REG                         , RULL(0x34010008), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35010008,
+REG64( EX_11_RING_FENCE_MASK_LATCH_REG                         , RULL(0x36010008), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37010008,
+
+REG64( C_SCAN_REGION_TYPE                                      , RULL(0x20030005), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_SCAN_REGION_TYPE                                    , RULL(0x20030005), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_SCAN_REGION_TYPE                                    , RULL(0x21030005), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_SCAN_REGION_TYPE                                    , RULL(0x22030005), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_SCAN_REGION_TYPE                                    , RULL(0x23030005), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_SCAN_REGION_TYPE                                    , RULL(0x24030005), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_SCAN_REGION_TYPE                                    , RULL(0x25030005), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_SCAN_REGION_TYPE                                    , RULL(0x26030005), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_SCAN_REGION_TYPE                                    , RULL(0x27030005), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_SCAN_REGION_TYPE                                    , RULL(0x28030005), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_SCAN_REGION_TYPE                                    , RULL(0x29030005), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_SCAN_REGION_TYPE                                   , RULL(0x2A030005), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_SCAN_REGION_TYPE                                   , RULL(0x2B030005), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_SCAN_REGION_TYPE                                   , RULL(0x2C030005), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_SCAN_REGION_TYPE                                   , RULL(0x2D030005), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_SCAN_REGION_TYPE                                   , RULL(0x2E030005), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_SCAN_REGION_TYPE                                   , RULL(0x2F030005), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_SCAN_REGION_TYPE                                   , RULL(0x30030005), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_SCAN_REGION_TYPE                                   , RULL(0x31030005), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_SCAN_REGION_TYPE                                   , RULL(0x32030005), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_SCAN_REGION_TYPE                                   , RULL(0x33030005), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_SCAN_REGION_TYPE                                   , RULL(0x34030005), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_SCAN_REGION_TYPE                                   , RULL(0x35030005), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_SCAN_REGION_TYPE                                   , RULL(0x36030005), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_SCAN_REGION_TYPE                                   , RULL(0x37030005), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_SCAN_REGION_TYPE                                     , RULL(0x10030005), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_SCAN_REGION_TYPE                                   , RULL(0x10030005), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_SCAN_REGION_TYPE                                   , RULL(0x11030005), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_SCAN_REGION_TYPE                                   , RULL(0x12030005), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_SCAN_REGION_TYPE                                   , RULL(0x13030005), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_SCAN_REGION_TYPE                                   , RULL(0x14030005), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_SCAN_REGION_TYPE                                   , RULL(0x15030005), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_SCAN_REGION_TYPE                                     , RULL(0x20030005), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21030005,
+REG64( EX_0_SCAN_REGION_TYPE                                   , RULL(0x20030005), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21030005,
+REG64( EX_1_SCAN_REGION_TYPE                                   , RULL(0x22030005), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23030005,
+REG64( EX_2_SCAN_REGION_TYPE                                   , RULL(0x24030005), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25030005,
+REG64( EX_3_SCAN_REGION_TYPE                                   , RULL(0x26030005), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27030005,
+REG64( EX_4_SCAN_REGION_TYPE                                   , RULL(0x28030005), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29030005,
+REG64( EX_5_SCAN_REGION_TYPE                                   , RULL(0x2A030005), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B030005,
+REG64( EX_6_SCAN_REGION_TYPE                                   , RULL(0x2C030005), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D030005,
+REG64( EX_7_SCAN_REGION_TYPE                                   , RULL(0x2E030005), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F030005,
+REG64( EX_8_SCAN_REGION_TYPE                                   , RULL(0x30030005), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31030005,
+REG64( EX_9_SCAN_REGION_TYPE                                   , RULL(0x32030005), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33030005,
+REG64( EX_10_SCAN_REGION_TYPE                                  , RULL(0x34030005), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35030005,
+REG64( EX_11_SCAN_REGION_TYPE                                  , RULL(0x36030005), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37030005,
+
+REG64( C_SCOMC                                                 , RULL(0x20010A80), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_SCOMC                                               , RULL(0x20010A80), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_SCOMC                                               , RULL(0x21010A80), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_SCOMC                                               , RULL(0x22010A80), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_SCOMC                                               , RULL(0x23010A80), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_SCOMC                                               , RULL(0x24010A80), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_SCOMC                                               , RULL(0x25010A80), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_SCOMC                                               , RULL(0x26010A80), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_SCOMC                                               , RULL(0x27010A80), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_SCOMC                                               , RULL(0x28010A80), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_SCOMC                                               , RULL(0x29010A80), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_SCOMC                                              , RULL(0x2A010A80), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_SCOMC                                              , RULL(0x2B010A80), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_SCOMC                                              , RULL(0x2C010A80), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_SCOMC                                              , RULL(0x2D010A80), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_SCOMC                                              , RULL(0x2E010A80), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_SCOMC                                              , RULL(0x2F010A80), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_SCOMC                                              , RULL(0x30010A80), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_SCOMC                                              , RULL(0x31010A80), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_SCOMC                                              , RULL(0x32010A80), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_SCOMC                                              , RULL(0x33010A80), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_SCOMC                                              , RULL(0x34010A80), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_SCOMC                                              , RULL(0x35010A80), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_SCOMC                                              , RULL(0x36010A80), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_SCOMC                                              , RULL(0x37010A80), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_SCOMC                                           , RULL(0x21010A80), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A80,
+REG64( EX_10_L2_SCOMC                                          , RULL(0x35010A80), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 34010A80,
+REG64( EX_11_L2_SCOMC                                          , RULL(0x37010A80), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 36010A80,
+REG64( EX_1_L2_SCOMC                                           , RULL(0x23010A80), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 22010A80,
+REG64( EX_2_L2_SCOMC                                           , RULL(0x25010A80), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 24010A80,
+REG64( EX_3_L2_SCOMC                                           , RULL(0x27010A80), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 26010A80,
+REG64( EX_4_L2_SCOMC                                           , RULL(0x29010A80), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 28010A80,
+REG64( EX_5_L2_SCOMC                                           , RULL(0x2B010A80), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2A010A80,
+REG64( EX_6_L2_SCOMC                                           , RULL(0x2D010A80), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2C010A80,
+REG64( EX_7_L2_SCOMC                                           , RULL(0x2F010A80), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2E010A80,
+REG64( EX_8_L2_SCOMC                                           , RULL(0x31010A80), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 30010A80,
+REG64( EX_9_L2_SCOMC                                           , RULL(0x33010A80), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 32010A80,
+REG64( EX_L2_SCOMC                                             , RULL(0x21010A80), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A80,
+
+REG64( C_SCR0                                                  , RULL(0x20010A86), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_SCR0                                                , RULL(0x20010A86), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_SCR0                                                , RULL(0x21010A86), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_SCR0                                                , RULL(0x22010A86), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_SCR0                                                , RULL(0x23010A86), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_SCR0                                                , RULL(0x24010A86), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_SCR0                                                , RULL(0x25010A86), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_SCR0                                                , RULL(0x26010A86), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_SCR0                                                , RULL(0x27010A86), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_SCR0                                                , RULL(0x28010A86), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_SCR0                                                , RULL(0x29010A86), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_SCR0                                               , RULL(0x2A010A86), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_SCR0                                               , RULL(0x2B010A86), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_SCR0                                               , RULL(0x2C010A86), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_SCR0                                               , RULL(0x2D010A86), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_SCR0                                               , RULL(0x2E010A86), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_SCR0                                               , RULL(0x2F010A86), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_SCR0                                               , RULL(0x30010A86), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_SCR0                                               , RULL(0x31010A86), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_SCR0                                               , RULL(0x32010A86), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_SCR0                                               , RULL(0x33010A86), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_SCR0                                               , RULL(0x34010A86), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_SCR0                                               , RULL(0x35010A86), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_SCR0                                               , RULL(0x36010A86), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_SCR0                                               , RULL(0x37010A86), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_SCR0                                            , RULL(0x21010A86), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A86,
+REG64( EX_10_L2_SCR0                                           , RULL(0x35010A86), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 34010A86,
+REG64( EX_11_L2_SCR0                                           , RULL(0x37010A86), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 36010A86,
+REG64( EX_1_L2_SCR0                                            , RULL(0x23010A86), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 22010A86,
+REG64( EX_2_L2_SCR0                                            , RULL(0x25010A86), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 24010A86,
+REG64( EX_3_L2_SCR0                                            , RULL(0x27010A86), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 26010A86,
+REG64( EX_4_L2_SCR0                                            , RULL(0x29010A86), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 28010A86,
+REG64( EX_5_L2_SCR0                                            , RULL(0x2B010A86), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2A010A86,
+REG64( EX_6_L2_SCR0                                            , RULL(0x2D010A86), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2C010A86,
+REG64( EX_7_L2_SCR0                                            , RULL(0x2F010A86), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2E010A86,
+REG64( EX_8_L2_SCR0                                            , RULL(0x31010A86), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 30010A86,
+REG64( EX_9_L2_SCR0                                            , RULL(0x33010A86), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 32010A86,
+REG64( EX_L2_SCR0                                              , RULL(0x21010A86), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A86,
+
+REG64( C_SCR1                                                  , RULL(0x20010A87), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_SCR1                                                , RULL(0x20010A87), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_SCR1                                                , RULL(0x21010A87), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_SCR1                                                , RULL(0x22010A87), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_SCR1                                                , RULL(0x23010A87), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_SCR1                                                , RULL(0x24010A87), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_SCR1                                                , RULL(0x25010A87), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_SCR1                                                , RULL(0x26010A87), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_SCR1                                                , RULL(0x27010A87), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_SCR1                                                , RULL(0x28010A87), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_SCR1                                                , RULL(0x29010A87), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_SCR1                                               , RULL(0x2A010A87), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_SCR1                                               , RULL(0x2B010A87), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_SCR1                                               , RULL(0x2C010A87), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_SCR1                                               , RULL(0x2D010A87), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_SCR1                                               , RULL(0x2E010A87), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_SCR1                                               , RULL(0x2F010A87), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_SCR1                                               , RULL(0x30010A87), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_SCR1                                               , RULL(0x31010A87), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_SCR1                                               , RULL(0x32010A87), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_SCR1                                               , RULL(0x33010A87), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_SCR1                                               , RULL(0x34010A87), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_SCR1                                               , RULL(0x35010A87), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_SCR1                                               , RULL(0x36010A87), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_SCR1                                               , RULL(0x37010A87), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_SCR1                                            , RULL(0x21010A87), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A87,
+REG64( EX_10_L2_SCR1                                           , RULL(0x35010A87), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 34010A87,
+REG64( EX_11_L2_SCR1                                           , RULL(0x37010A87), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 36010A87,
+REG64( EX_1_L2_SCR1                                            , RULL(0x23010A87), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 22010A87,
+REG64( EX_2_L2_SCR1                                            , RULL(0x25010A87), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 24010A87,
+REG64( EX_3_L2_SCR1                                            , RULL(0x27010A87), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 26010A87,
+REG64( EX_4_L2_SCR1                                            , RULL(0x29010A87), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 28010A87,
+REG64( EX_5_L2_SCR1                                            , RULL(0x2B010A87), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2A010A87,
+REG64( EX_6_L2_SCR1                                            , RULL(0x2D010A87), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2C010A87,
+REG64( EX_7_L2_SCR1                                            , RULL(0x2F010A87), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2E010A87,
+REG64( EX_8_L2_SCR1                                            , RULL(0x31010A87), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 30010A87,
+REG64( EX_9_L2_SCR1                                            , RULL(0x33010A87), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 32010A87,
+REG64( EX_L2_SCR1                                              , RULL(0x21010A87), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A87,
+
+REG64( C_SCR2                                                  , RULL(0x20010A88), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_SCR2                                                , RULL(0x20010A88), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_SCR2                                                , RULL(0x21010A88), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_SCR2                                                , RULL(0x22010A88), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_SCR2                                                , RULL(0x23010A88), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_SCR2                                                , RULL(0x24010A88), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_SCR2                                                , RULL(0x25010A88), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_SCR2                                                , RULL(0x26010A88), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_SCR2                                                , RULL(0x27010A88), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_SCR2                                                , RULL(0x28010A88), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_SCR2                                                , RULL(0x29010A88), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_SCR2                                               , RULL(0x2A010A88), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_SCR2                                               , RULL(0x2B010A88), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_SCR2                                               , RULL(0x2C010A88), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_SCR2                                               , RULL(0x2D010A88), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_SCR2                                               , RULL(0x2E010A88), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_SCR2                                               , RULL(0x2F010A88), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_SCR2                                               , RULL(0x30010A88), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_SCR2                                               , RULL(0x31010A88), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_SCR2                                               , RULL(0x32010A88), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_SCR2                                               , RULL(0x33010A88), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_SCR2                                               , RULL(0x34010A88), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_SCR2                                               , RULL(0x35010A88), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_SCR2                                               , RULL(0x36010A88), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_SCR2                                               , RULL(0x37010A88), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_SCR2                                                 , RULL(0x21010A88), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A88,
+REG64( EX_0_SCR2                                               , RULL(0x21010A88), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A88,
+REG64( EX_1_SCR2                                               , RULL(0x23010A88), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 22010A88,
+REG64( EX_2_SCR2                                               , RULL(0x25010A88), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 24010A88,
+REG64( EX_3_SCR2                                               , RULL(0x27010A88), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 26010A88,
+REG64( EX_4_SCR2                                               , RULL(0x29010A88), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 28010A88,
+REG64( EX_5_SCR2                                               , RULL(0x2B010A88), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2A010A88,
+REG64( EX_6_SCR2                                               , RULL(0x2D010A88), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2C010A88,
+REG64( EX_7_SCR2                                               , RULL(0x2F010A88), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2E010A88,
+REG64( EX_8_SCR2                                               , RULL(0x31010A88), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 30010A88,
+REG64( EX_9_SCR2                                               , RULL(0x33010A88), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 32010A88,
+REG64( EX_10_SCR2                                              , RULL(0x35010A88), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 34010A88,
+REG64( EX_11_SCR2                                              , RULL(0x37010A88), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 36010A88,
+
+REG64( C_SCR3                                                  , RULL(0x20010A89), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_SCR3                                                , RULL(0x20010A89), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_SCR3                                                , RULL(0x21010A89), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_SCR3                                                , RULL(0x22010A89), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_SCR3                                                , RULL(0x23010A89), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_SCR3                                                , RULL(0x24010A89), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_SCR3                                                , RULL(0x25010A89), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_SCR3                                                , RULL(0x26010A89), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_SCR3                                                , RULL(0x27010A89), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_SCR3                                                , RULL(0x28010A89), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_SCR3                                                , RULL(0x29010A89), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_SCR3                                               , RULL(0x2A010A89), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_SCR3                                               , RULL(0x2B010A89), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_SCR3                                               , RULL(0x2C010A89), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_SCR3                                               , RULL(0x2D010A89), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_SCR3                                               , RULL(0x2E010A89), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_SCR3                                               , RULL(0x2F010A89), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_SCR3                                               , RULL(0x30010A89), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_SCR3                                               , RULL(0x31010A89), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_SCR3                                               , RULL(0x32010A89), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_SCR3                                               , RULL(0x33010A89), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_SCR3                                               , RULL(0x34010A89), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_SCR3                                               , RULL(0x35010A89), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_SCR3                                               , RULL(0x36010A89), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_SCR3                                               , RULL(0x37010A89), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_SCR3                                                 , RULL(0x21010A89), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A89,
+REG64( EX_0_SCR3                                               , RULL(0x21010A89), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A89,
+REG64( EX_1_SCR3                                               , RULL(0x23010A89), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 22010A89,
+REG64( EX_2_SCR3                                               , RULL(0x25010A89), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 24010A89,
+REG64( EX_3_SCR3                                               , RULL(0x27010A89), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 26010A89,
+REG64( EX_4_SCR3                                               , RULL(0x29010A89), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 28010A89,
+REG64( EX_5_SCR3                                               , RULL(0x2B010A89), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2A010A89,
+REG64( EX_6_SCR3                                               , RULL(0x2D010A89), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2C010A89,
+REG64( EX_7_SCR3                                               , RULL(0x2F010A89), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2E010A89,
+REG64( EX_8_SCR3                                               , RULL(0x31010A89), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 30010A89,
+REG64( EX_9_SCR3                                               , RULL(0x33010A89), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 32010A89,
+REG64( EX_10_SCR3                                              , RULL(0x35010A89), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 34010A89,
+REG64( EX_11_SCR3                                              , RULL(0x37010A89), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 36010A89,
+
+REG64( C_SHID0                                                 , RULL(0x20010AA5), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_SHID0                                               , RULL(0x20010AA5), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_SHID0                                               , RULL(0x21010AA5), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_SHID0                                               , RULL(0x22010AA5), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_SHID0                                               , RULL(0x23010AA5), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_SHID0                                               , RULL(0x24010AA5), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_SHID0                                               , RULL(0x25010AA5), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_SHID0                                               , RULL(0x26010AA5), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_SHID0                                               , RULL(0x27010AA5), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_SHID0                                               , RULL(0x28010AA5), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_SHID0                                               , RULL(0x29010AA5), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_SHID0                                              , RULL(0x2A010AA5), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_SHID0                                              , RULL(0x2B010AA5), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_SHID0                                              , RULL(0x2C010AA5), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_SHID0                                              , RULL(0x2D010AA5), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_SHID0                                              , RULL(0x2E010AA5), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_SHID0                                              , RULL(0x2F010AA5), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_SHID0                                              , RULL(0x30010AA5), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_SHID0                                              , RULL(0x31010AA5), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_SHID0                                              , RULL(0x32010AA5), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_SHID0                                              , RULL(0x33010AA5), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_SHID0                                              , RULL(0x34010AA5), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_SHID0                                              , RULL(0x35010AA5), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_SHID0                                              , RULL(0x36010AA5), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_SHID0                                              , RULL(0x37010AA5), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_SHID0                                           , RULL(0x20010AA5), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010AA5,
+REG64( EX_10_L2_SHID0                                          , RULL(0x34010AA5), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 35010AA5,
+REG64( EX_11_L2_SHID0                                          , RULL(0x36010AA5), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 37010AA5,
+REG64( EX_1_L2_SHID0                                           , RULL(0x22010AA5), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 23010AA5,
+REG64( EX_2_L2_SHID0                                           , RULL(0x24010AA5), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 25010AA5,
+REG64( EX_3_L2_SHID0                                           , RULL(0x26010AA5), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 27010AA5,
+REG64( EX_4_L2_SHID0                                           , RULL(0x28010AA5), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 29010AA5,
+REG64( EX_5_L2_SHID0                                           , RULL(0x2A010AA5), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2B010AA5,
+REG64( EX_6_L2_SHID0                                           , RULL(0x2C010AA5), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2D010AA5,
+REG64( EX_7_L2_SHID0                                           , RULL(0x2E010AA5), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2F010AA5,
+REG64( EX_8_L2_SHID0                                           , RULL(0x30010AA5), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 31010AA5,
+REG64( EX_9_L2_SHID0                                           , RULL(0x32010AA5), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 33010AA5,
+REG64( EX_L2_SHID0                                             , RULL(0x20010AA5), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 21010AA5,
+
+REG64( C_SIER_MASK                                             , RULL(0x20010AAE), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_SIER_MASK                                           , RULL(0x20010AAE), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_SIER_MASK                                           , RULL(0x21010AAE), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_SIER_MASK                                           , RULL(0x22010AAE), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_SIER_MASK                                           , RULL(0x23010AAE), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_SIER_MASK                                           , RULL(0x24010AAE), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_SIER_MASK                                           , RULL(0x25010AAE), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_SIER_MASK                                           , RULL(0x26010AAE), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_SIER_MASK                                           , RULL(0x27010AAE), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_SIER_MASK                                           , RULL(0x28010AAE), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_SIER_MASK                                           , RULL(0x29010AAE), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_SIER_MASK                                          , RULL(0x2A010AAE), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_SIER_MASK                                          , RULL(0x2B010AAE), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_SIER_MASK                                          , RULL(0x2C010AAE), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_SIER_MASK                                          , RULL(0x2D010AAE), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_SIER_MASK                                          , RULL(0x2E010AAE), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_SIER_MASK                                          , RULL(0x2F010AAE), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_SIER_MASK                                          , RULL(0x30010AAE), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_SIER_MASK                                          , RULL(0x31010AAE), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_SIER_MASK                                          , RULL(0x32010AAE), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_SIER_MASK                                          , RULL(0x33010AAE), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_SIER_MASK                                          , RULL(0x34010AAE), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_SIER_MASK                                          , RULL(0x35010AAE), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_SIER_MASK                                          , RULL(0x36010AAE), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_SIER_MASK                                          , RULL(0x37010AAE), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_SIER_MASK                                            , RULL(0x20010AAE), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21010AAE,
+REG64( EX_0_SIER_MASK                                          , RULL(0x20010AAE), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21010AAE,
+REG64( EX_1_SIER_MASK                                          , RULL(0x22010AAE), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23010AAE,
+REG64( EX_2_SIER_MASK                                          , RULL(0x24010AAE), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25010AAE,
+REG64( EX_3_SIER_MASK                                          , RULL(0x26010AAE), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27010AAE,
+REG64( EX_4_SIER_MASK                                          , RULL(0x28010AAE), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29010AAE,
+REG64( EX_5_SIER_MASK                                          , RULL(0x2A010AAE), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B010AAE,
+REG64( EX_6_SIER_MASK                                          , RULL(0x2C010AAE), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D010AAE,
+REG64( EX_7_SIER_MASK                                          , RULL(0x2E010AAE), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F010AAE,
+REG64( EX_8_SIER_MASK                                          , RULL(0x30010AAE), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31010AAE,
+REG64( EX_9_SIER_MASK                                          , RULL(0x32010AAE), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33010AAE,
+REG64( EX_10_SIER_MASK                                         , RULL(0x34010AAE), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35010AAE,
+REG64( EX_11_SIER_MASK                                         , RULL(0x36010AAE), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37010AAE,
+
+REG64( C_SKITTER_CLKSRC_REG                                    , RULL(0x20050016), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_SKITTER_CLKSRC_REG                                  , RULL(0x20050016), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_SKITTER_CLKSRC_REG                                  , RULL(0x21050016), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_SKITTER_CLKSRC_REG                                  , RULL(0x22050016), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_SKITTER_CLKSRC_REG                                  , RULL(0x23050016), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_SKITTER_CLKSRC_REG                                  , RULL(0x24050016), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_SKITTER_CLKSRC_REG                                  , RULL(0x25050016), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_SKITTER_CLKSRC_REG                                  , RULL(0x26050016), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_SKITTER_CLKSRC_REG                                  , RULL(0x27050016), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_SKITTER_CLKSRC_REG                                  , RULL(0x28050016), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_SKITTER_CLKSRC_REG                                  , RULL(0x29050016), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_SKITTER_CLKSRC_REG                                 , RULL(0x2A050016), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_SKITTER_CLKSRC_REG                                 , RULL(0x2B050016), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_SKITTER_CLKSRC_REG                                 , RULL(0x2C050016), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_SKITTER_CLKSRC_REG                                 , RULL(0x2D050016), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_SKITTER_CLKSRC_REG                                 , RULL(0x2E050016), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_SKITTER_CLKSRC_REG                                 , RULL(0x2F050016), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_SKITTER_CLKSRC_REG                                 , RULL(0x30050016), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_SKITTER_CLKSRC_REG                                 , RULL(0x31050016), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_SKITTER_CLKSRC_REG                                 , RULL(0x32050016), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_SKITTER_CLKSRC_REG                                 , RULL(0x33050016), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_SKITTER_CLKSRC_REG                                 , RULL(0x34050016), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_SKITTER_CLKSRC_REG                                 , RULL(0x35050016), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_SKITTER_CLKSRC_REG                                 , RULL(0x36050016), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_SKITTER_CLKSRC_REG                                 , RULL(0x37050016), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_SKITTER_CLKSRC_REG                                   , RULL(0x10050016), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_SKITTER_CLKSRC_REG                                 , RULL(0x10050016), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_SKITTER_CLKSRC_REG                                 , RULL(0x11050016), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_SKITTER_CLKSRC_REG                                 , RULL(0x12050016), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_SKITTER_CLKSRC_REG                                 , RULL(0x13050016), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_SKITTER_CLKSRC_REG                                 , RULL(0x14050016), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_SKITTER_CLKSRC_REG                                 , RULL(0x15050016), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_SKITTER_CLKSRC_REG                                   , RULL(0x20050016), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21050016,
+REG64( EX_0_SKITTER_CLKSRC_REG                                 , RULL(0x20050016), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21050016,
+REG64( EX_1_SKITTER_CLKSRC_REG                                 , RULL(0x22050016), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23050016,
+REG64( EX_2_SKITTER_CLKSRC_REG                                 , RULL(0x24050016), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25050016,
+REG64( EX_3_SKITTER_CLKSRC_REG                                 , RULL(0x26050016), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27050016,
+REG64( EX_4_SKITTER_CLKSRC_REG                                 , RULL(0x28050016), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29050016,
+REG64( EX_5_SKITTER_CLKSRC_REG                                 , RULL(0x2A050016), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B050016,
+REG64( EX_6_SKITTER_CLKSRC_REG                                 , RULL(0x2C050016), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D050016,
+REG64( EX_7_SKITTER_CLKSRC_REG                                 , RULL(0x2E050016), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F050016,
+REG64( EX_8_SKITTER_CLKSRC_REG                                 , RULL(0x30050016), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31050016,
+REG64( EX_9_SKITTER_CLKSRC_REG                                 , RULL(0x32050016), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33050016,
+REG64( EX_10_SKITTER_CLKSRC_REG                                , RULL(0x34050016), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35050016,
+REG64( EX_11_SKITTER_CLKSRC_REG                                , RULL(0x36050016), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37050016,
+
+REG64( C_SKITTER_DATA0                                         , RULL(0x20050019), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_SKITTER_DATA0                                       , RULL(0x20050019), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_SKITTER_DATA0                                       , RULL(0x21050019), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_SKITTER_DATA0                                       , RULL(0x22050019), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_SKITTER_DATA0                                       , RULL(0x23050019), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_SKITTER_DATA0                                       , RULL(0x24050019), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_SKITTER_DATA0                                       , RULL(0x25050019), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_SKITTER_DATA0                                       , RULL(0x26050019), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_SKITTER_DATA0                                       , RULL(0x27050019), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_SKITTER_DATA0                                       , RULL(0x28050019), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_SKITTER_DATA0                                       , RULL(0x29050019), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_SKITTER_DATA0                                      , RULL(0x2A050019), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_SKITTER_DATA0                                      , RULL(0x2B050019), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_SKITTER_DATA0                                      , RULL(0x2C050019), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_SKITTER_DATA0                                      , RULL(0x2D050019), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_SKITTER_DATA0                                      , RULL(0x2E050019), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_SKITTER_DATA0                                      , RULL(0x2F050019), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_SKITTER_DATA0                                      , RULL(0x30050019), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_SKITTER_DATA0                                      , RULL(0x31050019), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_SKITTER_DATA0                                      , RULL(0x32050019), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_SKITTER_DATA0                                      , RULL(0x33050019), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_SKITTER_DATA0                                      , RULL(0x34050019), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_SKITTER_DATA0                                      , RULL(0x35050019), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_SKITTER_DATA0                                      , RULL(0x36050019), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_SKITTER_DATA0                                      , RULL(0x37050019), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EQ_SKITTER_DATA0                                        , RULL(0x10050019), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_SKITTER_DATA0                                      , RULL(0x10050019), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_SKITTER_DATA0                                      , RULL(0x11050019), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_SKITTER_DATA0                                      , RULL(0x12050019), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_SKITTER_DATA0                                      , RULL(0x13050019), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_SKITTER_DATA0                                      , RULL(0x14050019), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_SKITTER_DATA0                                      , RULL(0x15050019), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_SKITTER_DATA0                                        , RULL(0x20050019), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21050019,
+REG64( EX_0_SKITTER_DATA0                                      , RULL(0x20050019), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21050019,
+REG64( EX_1_SKITTER_DATA0                                      , RULL(0x22050019), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23050019,
+REG64( EX_2_SKITTER_DATA0                                      , RULL(0x24050019), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25050019,
+REG64( EX_3_SKITTER_DATA0                                      , RULL(0x26050019), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27050019,
+REG64( EX_4_SKITTER_DATA0                                      , RULL(0x28050019), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29050019,
+REG64( EX_5_SKITTER_DATA0                                      , RULL(0x2A050019), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B050019,
+REG64( EX_6_SKITTER_DATA0                                      , RULL(0x2C050019), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D050019,
+REG64( EX_7_SKITTER_DATA0                                      , RULL(0x2E050019), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F050019,
+REG64( EX_8_SKITTER_DATA0                                      , RULL(0x30050019), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31050019,
+REG64( EX_9_SKITTER_DATA0                                      , RULL(0x32050019), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33050019,
+REG64( EX_10_SKITTER_DATA0                                     , RULL(0x34050019), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35050019,
+REG64( EX_11_SKITTER_DATA0                                     , RULL(0x36050019), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37050019,
+
+REG64( C_SKITTER_DATA1                                         , RULL(0x2005001A), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_SKITTER_DATA1                                       , RULL(0x2005001A), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_SKITTER_DATA1                                       , RULL(0x2105001A), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_SKITTER_DATA1                                       , RULL(0x2205001A), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_SKITTER_DATA1                                       , RULL(0x2305001A), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_SKITTER_DATA1                                       , RULL(0x2405001A), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_SKITTER_DATA1                                       , RULL(0x2505001A), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_SKITTER_DATA1                                       , RULL(0x2605001A), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_SKITTER_DATA1                                       , RULL(0x2705001A), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_SKITTER_DATA1                                       , RULL(0x2805001A), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_SKITTER_DATA1                                       , RULL(0x2905001A), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_SKITTER_DATA1                                      , RULL(0x2A05001A), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_SKITTER_DATA1                                      , RULL(0x2B05001A), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_SKITTER_DATA1                                      , RULL(0x2C05001A), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_SKITTER_DATA1                                      , RULL(0x2D05001A), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_SKITTER_DATA1                                      , RULL(0x2E05001A), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_SKITTER_DATA1                                      , RULL(0x2F05001A), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_SKITTER_DATA1                                      , RULL(0x3005001A), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_SKITTER_DATA1                                      , RULL(0x3105001A), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_SKITTER_DATA1                                      , RULL(0x3205001A), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_SKITTER_DATA1                                      , RULL(0x3305001A), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_SKITTER_DATA1                                      , RULL(0x3405001A), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_SKITTER_DATA1                                      , RULL(0x3505001A), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_SKITTER_DATA1                                      , RULL(0x3605001A), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_SKITTER_DATA1                                      , RULL(0x3705001A), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EQ_SKITTER_DATA1                                        , RULL(0x1005001A), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_SKITTER_DATA1                                      , RULL(0x1005001A), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_SKITTER_DATA1                                      , RULL(0x1105001A), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_SKITTER_DATA1                                      , RULL(0x1205001A), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_SKITTER_DATA1                                      , RULL(0x1305001A), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_SKITTER_DATA1                                      , RULL(0x1405001A), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_SKITTER_DATA1                                      , RULL(0x1505001A), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_SKITTER_DATA1                                        , RULL(0x2005001A), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2105001A,
+REG64( EX_0_SKITTER_DATA1                                      , RULL(0x2005001A), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2105001A,
+REG64( EX_1_SKITTER_DATA1                                      , RULL(0x2205001A), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2305001A,
+REG64( EX_2_SKITTER_DATA1                                      , RULL(0x2405001A), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2505001A,
+REG64( EX_3_SKITTER_DATA1                                      , RULL(0x2605001A), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2705001A,
+REG64( EX_4_SKITTER_DATA1                                      , RULL(0x2805001A), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2905001A,
+REG64( EX_5_SKITTER_DATA1                                      , RULL(0x2A05001A), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B05001A,
+REG64( EX_6_SKITTER_DATA1                                      , RULL(0x2C05001A), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D05001A,
+REG64( EX_7_SKITTER_DATA1                                      , RULL(0x2E05001A), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F05001A,
+REG64( EX_8_SKITTER_DATA1                                      , RULL(0x3005001A), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 3105001A,
+REG64( EX_9_SKITTER_DATA1                                      , RULL(0x3205001A), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 3305001A,
+REG64( EX_10_SKITTER_DATA1                                     , RULL(0x3405001A), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 3505001A,
+REG64( EX_11_SKITTER_DATA1                                     , RULL(0x3605001A), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 3705001A,
+
+REG64( C_SKITTER_DATA2                                         , RULL(0x2005001B), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_SKITTER_DATA2                                       , RULL(0x2005001B), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_SKITTER_DATA2                                       , RULL(0x2105001B), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_SKITTER_DATA2                                       , RULL(0x2205001B), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_SKITTER_DATA2                                       , RULL(0x2305001B), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_SKITTER_DATA2                                       , RULL(0x2405001B), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_SKITTER_DATA2                                       , RULL(0x2505001B), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_SKITTER_DATA2                                       , RULL(0x2605001B), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_SKITTER_DATA2                                       , RULL(0x2705001B), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_SKITTER_DATA2                                       , RULL(0x2805001B), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_SKITTER_DATA2                                       , RULL(0x2905001B), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_SKITTER_DATA2                                      , RULL(0x2A05001B), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_SKITTER_DATA2                                      , RULL(0x2B05001B), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_SKITTER_DATA2                                      , RULL(0x2C05001B), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_SKITTER_DATA2                                      , RULL(0x2D05001B), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_SKITTER_DATA2                                      , RULL(0x2E05001B), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_SKITTER_DATA2                                      , RULL(0x2F05001B), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_SKITTER_DATA2                                      , RULL(0x3005001B), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_SKITTER_DATA2                                      , RULL(0x3105001B), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_SKITTER_DATA2                                      , RULL(0x3205001B), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_SKITTER_DATA2                                      , RULL(0x3305001B), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_SKITTER_DATA2                                      , RULL(0x3405001B), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_SKITTER_DATA2                                      , RULL(0x3505001B), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_SKITTER_DATA2                                      , RULL(0x3605001B), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_SKITTER_DATA2                                      , RULL(0x3705001B), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EQ_SKITTER_DATA2                                        , RULL(0x1005001B), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_SKITTER_DATA2                                      , RULL(0x1005001B), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_SKITTER_DATA2                                      , RULL(0x1105001B), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_SKITTER_DATA2                                      , RULL(0x1205001B), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_SKITTER_DATA2                                      , RULL(0x1305001B), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_SKITTER_DATA2                                      , RULL(0x1405001B), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_SKITTER_DATA2                                      , RULL(0x1505001B), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_SKITTER_DATA2                                        , RULL(0x2005001B), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2105001B,
+REG64( EX_0_SKITTER_DATA2                                      , RULL(0x2005001B), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2105001B,
+REG64( EX_1_SKITTER_DATA2                                      , RULL(0x2205001B), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2305001B,
+REG64( EX_2_SKITTER_DATA2                                      , RULL(0x2405001B), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2505001B,
+REG64( EX_3_SKITTER_DATA2                                      , RULL(0x2605001B), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2705001B,
+REG64( EX_4_SKITTER_DATA2                                      , RULL(0x2805001B), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2905001B,
+REG64( EX_5_SKITTER_DATA2                                      , RULL(0x2A05001B), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B05001B,
+REG64( EX_6_SKITTER_DATA2                                      , RULL(0x2C05001B), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D05001B,
+REG64( EX_7_SKITTER_DATA2                                      , RULL(0x2E05001B), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F05001B,
+REG64( EX_8_SKITTER_DATA2                                      , RULL(0x3005001B), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 3105001B,
+REG64( EX_9_SKITTER_DATA2                                      , RULL(0x3205001B), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 3305001B,
+REG64( EX_10_SKITTER_DATA2                                     , RULL(0x3405001B), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 3505001B,
+REG64( EX_11_SKITTER_DATA2                                     , RULL(0x3605001B), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 3705001B,
+
+REG64( C_SKITTER_FORCE_REG                                     , RULL(0x20050014), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_SKITTER_FORCE_REG                                   , RULL(0x20050014), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_SKITTER_FORCE_REG                                   , RULL(0x21050014), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_SKITTER_FORCE_REG                                   , RULL(0x22050014), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_SKITTER_FORCE_REG                                   , RULL(0x23050014), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_SKITTER_FORCE_REG                                   , RULL(0x24050014), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_SKITTER_FORCE_REG                                   , RULL(0x25050014), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_SKITTER_FORCE_REG                                   , RULL(0x26050014), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_SKITTER_FORCE_REG                                   , RULL(0x27050014), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_SKITTER_FORCE_REG                                   , RULL(0x28050014), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_SKITTER_FORCE_REG                                   , RULL(0x29050014), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_SKITTER_FORCE_REG                                  , RULL(0x2A050014), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_SKITTER_FORCE_REG                                  , RULL(0x2B050014), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_SKITTER_FORCE_REG                                  , RULL(0x2C050014), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_SKITTER_FORCE_REG                                  , RULL(0x2D050014), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_SKITTER_FORCE_REG                                  , RULL(0x2E050014), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_SKITTER_FORCE_REG                                  , RULL(0x2F050014), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_SKITTER_FORCE_REG                                  , RULL(0x30050014), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_SKITTER_FORCE_REG                                  , RULL(0x31050014), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_SKITTER_FORCE_REG                                  , RULL(0x32050014), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_SKITTER_FORCE_REG                                  , RULL(0x33050014), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_SKITTER_FORCE_REG                                  , RULL(0x34050014), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_SKITTER_FORCE_REG                                  , RULL(0x35050014), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_SKITTER_FORCE_REG                                  , RULL(0x36050014), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_SKITTER_FORCE_REG                                  , RULL(0x37050014), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_SKITTER_FORCE_REG                                    , RULL(0x10050014), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_SKITTER_FORCE_REG                                  , RULL(0x10050014), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_SKITTER_FORCE_REG                                  , RULL(0x11050014), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_SKITTER_FORCE_REG                                  , RULL(0x12050014), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_SKITTER_FORCE_REG                                  , RULL(0x13050014), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_SKITTER_FORCE_REG                                  , RULL(0x14050014), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_SKITTER_FORCE_REG                                  , RULL(0x15050014), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_SKITTER_FORCE_REG                                    , RULL(0x20050014), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21050014,
+REG64( EX_0_SKITTER_FORCE_REG                                  , RULL(0x20050014), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21050014,
+REG64( EX_1_SKITTER_FORCE_REG                                  , RULL(0x22050014), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23050014,
+REG64( EX_2_SKITTER_FORCE_REG                                  , RULL(0x24050014), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25050014,
+REG64( EX_3_SKITTER_FORCE_REG                                  , RULL(0x26050014), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27050014,
+REG64( EX_4_SKITTER_FORCE_REG                                  , RULL(0x28050014), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29050014,
+REG64( EX_5_SKITTER_FORCE_REG                                  , RULL(0x2A050014), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B050014,
+REG64( EX_6_SKITTER_FORCE_REG                                  , RULL(0x2C050014), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D050014,
+REG64( EX_7_SKITTER_FORCE_REG                                  , RULL(0x2E050014), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F050014,
+REG64( EX_8_SKITTER_FORCE_REG                                  , RULL(0x30050014), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31050014,
+REG64( EX_9_SKITTER_FORCE_REG                                  , RULL(0x32050014), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33050014,
+REG64( EX_10_SKITTER_FORCE_REG                                 , RULL(0x34050014), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35050014,
+REG64( EX_11_SKITTER_FORCE_REG                                 , RULL(0x36050014), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37050014,
+
+REG64( C_SKITTER_MODE_REG                                      , RULL(0x20050010), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_SKITTER_MODE_REG                                    , RULL(0x20050010), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_SKITTER_MODE_REG                                    , RULL(0x21050010), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_SKITTER_MODE_REG                                    , RULL(0x22050010), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_SKITTER_MODE_REG                                    , RULL(0x23050010), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_SKITTER_MODE_REG                                    , RULL(0x24050010), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_SKITTER_MODE_REG                                    , RULL(0x25050010), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_SKITTER_MODE_REG                                    , RULL(0x26050010), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_SKITTER_MODE_REG                                    , RULL(0x27050010), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_SKITTER_MODE_REG                                    , RULL(0x28050010), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_SKITTER_MODE_REG                                    , RULL(0x29050010), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_SKITTER_MODE_REG                                   , RULL(0x2A050010), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_SKITTER_MODE_REG                                   , RULL(0x2B050010), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_SKITTER_MODE_REG                                   , RULL(0x2C050010), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_SKITTER_MODE_REG                                   , RULL(0x2D050010), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_SKITTER_MODE_REG                                   , RULL(0x2E050010), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_SKITTER_MODE_REG                                   , RULL(0x2F050010), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_SKITTER_MODE_REG                                   , RULL(0x30050010), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_SKITTER_MODE_REG                                   , RULL(0x31050010), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_SKITTER_MODE_REG                                   , RULL(0x32050010), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_SKITTER_MODE_REG                                   , RULL(0x33050010), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_SKITTER_MODE_REG                                   , RULL(0x34050010), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_SKITTER_MODE_REG                                   , RULL(0x35050010), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_SKITTER_MODE_REG                                   , RULL(0x36050010), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_SKITTER_MODE_REG                                   , RULL(0x37050010), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_SKITTER_MODE_REG                                     , RULL(0x10050010), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_SKITTER_MODE_REG                                   , RULL(0x10050010), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_SKITTER_MODE_REG                                   , RULL(0x11050010), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_SKITTER_MODE_REG                                   , RULL(0x12050010), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_SKITTER_MODE_REG                                   , RULL(0x13050010), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_SKITTER_MODE_REG                                   , RULL(0x14050010), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_SKITTER_MODE_REG                                   , RULL(0x15050010), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_SKITTER_MODE_REG                                     , RULL(0x20050010), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21050010,
+REG64( EX_0_SKITTER_MODE_REG                                   , RULL(0x20050010), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21050010,
+REG64( EX_1_SKITTER_MODE_REG                                   , RULL(0x22050010), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23050010,
+REG64( EX_2_SKITTER_MODE_REG                                   , RULL(0x24050010), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25050010,
+REG64( EX_3_SKITTER_MODE_REG                                   , RULL(0x26050010), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27050010,
+REG64( EX_4_SKITTER_MODE_REG                                   , RULL(0x28050010), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29050010,
+REG64( EX_5_SKITTER_MODE_REG                                   , RULL(0x2A050010), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B050010,
+REG64( EX_6_SKITTER_MODE_REG                                   , RULL(0x2C050010), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D050010,
+REG64( EX_7_SKITTER_MODE_REG                                   , RULL(0x2E050010), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F050010,
+REG64( EX_8_SKITTER_MODE_REG                                   , RULL(0x30050010), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31050010,
+REG64( EX_9_SKITTER_MODE_REG                                   , RULL(0x32050010), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33050010,
+REG64( EX_10_SKITTER_MODE_REG                                  , RULL(0x34050010), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35050010,
+REG64( EX_11_SKITTER_MODE_REG                                  , RULL(0x36050010), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37050010,
+
+REG64( C_SLAVE_CONFIG_REG                                      , RULL(0x200F001E), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_SLAVE_CONFIG_REG                                    , RULL(0x200F001E), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_SLAVE_CONFIG_REG                                    , RULL(0x210F001E), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_SLAVE_CONFIG_REG                                    , RULL(0x220F001E), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_SLAVE_CONFIG_REG                                    , RULL(0x230F001E), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_SLAVE_CONFIG_REG                                    , RULL(0x240F001E), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_SLAVE_CONFIG_REG                                    , RULL(0x250F001E), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_SLAVE_CONFIG_REG                                    , RULL(0x260F001E), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_SLAVE_CONFIG_REG                                    , RULL(0x270F001E), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_SLAVE_CONFIG_REG                                    , RULL(0x280F001E), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_SLAVE_CONFIG_REG                                    , RULL(0x290F001E), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_SLAVE_CONFIG_REG                                   , RULL(0x2A0F001E), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_SLAVE_CONFIG_REG                                   , RULL(0x2B0F001E), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_SLAVE_CONFIG_REG                                   , RULL(0x2C0F001E), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_SLAVE_CONFIG_REG                                   , RULL(0x2D0F001E), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_SLAVE_CONFIG_REG                                   , RULL(0x2E0F001E), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_SLAVE_CONFIG_REG                                   , RULL(0x2F0F001E), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_SLAVE_CONFIG_REG                                   , RULL(0x300F001E), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_SLAVE_CONFIG_REG                                   , RULL(0x310F001E), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_SLAVE_CONFIG_REG                                   , RULL(0x320F001E), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_SLAVE_CONFIG_REG                                   , RULL(0x330F001E), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_SLAVE_CONFIG_REG                                   , RULL(0x340F001E), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_SLAVE_CONFIG_REG                                   , RULL(0x350F001E), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_SLAVE_CONFIG_REG                                   , RULL(0x360F001E), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_SLAVE_CONFIG_REG                                   , RULL(0x370F001E), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_SLAVE_CONFIG_REG                                     , RULL(0x100F001E), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_SLAVE_CONFIG_REG                                   , RULL(0x100F001E), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_SLAVE_CONFIG_REG                                   , RULL(0x110F001E), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_SLAVE_CONFIG_REG                                   , RULL(0x120F001E), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_SLAVE_CONFIG_REG                                   , RULL(0x130F001E), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_SLAVE_CONFIG_REG                                   , RULL(0x140F001E), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_SLAVE_CONFIG_REG                                   , RULL(0x150F001E), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_SLAVE_CONFIG_REG                                     , RULL(0x200F001E), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F001E,
+REG64( EX_0_SLAVE_CONFIG_REG                                   , RULL(0x200F001E), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F001E,
+REG64( EX_1_SLAVE_CONFIG_REG                                   , RULL(0x230F001E), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F001E,
+REG64( EX_2_SLAVE_CONFIG_REG                                   , RULL(0x240F001E), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F001E,
+REG64( EX_3_SLAVE_CONFIG_REG                                   , RULL(0x260F001E), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F001E,
+REG64( EX_4_SLAVE_CONFIG_REG                                   , RULL(0x280F001E), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F001E,
+REG64( EX_5_SLAVE_CONFIG_REG                                   , RULL(0x2A0F001E), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F001E,
+REG64( EX_6_SLAVE_CONFIG_REG                                   , RULL(0x2C0F001E), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F001E,
+REG64( EX_7_SLAVE_CONFIG_REG                                   , RULL(0x2E0F001E), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F001E,
+REG64( EX_8_SLAVE_CONFIG_REG                                   , RULL(0x300F001E), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F001E,
+REG64( EX_9_SLAVE_CONFIG_REG                                   , RULL(0x320F001E), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F001E,
+REG64( EX_10_SLAVE_CONFIG_REG                                  , RULL(0x340F001E), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F001E,
+REG64( EX_11_SLAVE_CONFIG_REG                                  , RULL(0x360F001E), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F001E,
+
+REG64( C_SPATTN_SCOM                                           , RULL(0x20040004), SH_UNT_C        ,
+       SH_ACS_SCOM_RO   ); //DUPS: 20010A99,
+REG64( C_SPATTN_SCOM1                                          , RULL(0x20040005), SH_UNT_C        ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 20010A98,
+REG64( C_SPATTN_SCOM2                                          , RULL(0x20040006), SH_UNT_C        ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 20010A97,
+REG64( C_0_SPATTN_SCOM                                         , RULL(0x20040004), SH_UNT_C_0      ,
+       SH_ACS_SCOM_RO   ); //DUPS: 20010A99,
+REG64( C_0_SPATTN_SCOM1                                        , RULL(0x20040005), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 20010A98,
+REG64( C_0_SPATTN_SCOM2                                        , RULL(0x20040006), SH_UNT_C_0      ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 20010A97,
+REG64( C_1_SPATTN_SCOM                                         , RULL(0x21040004), SH_UNT_C_1      ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010A99,
+REG64( C_1_SPATTN_SCOM1                                        , RULL(0x21040005), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 21010A98,
+REG64( C_1_SPATTN_SCOM2                                        , RULL(0x21040006), SH_UNT_C_1      ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 21010A97,
+REG64( C_2_SPATTN_SCOM                                         , RULL(0x22040004), SH_UNT_C_2      ,
+       SH_ACS_SCOM_RO   ); //DUPS: 22010A99,
+REG64( C_2_SPATTN_SCOM1                                        , RULL(0x22040005), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 22010A98,
+REG64( C_2_SPATTN_SCOM2                                        , RULL(0x22040006), SH_UNT_C_2      ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 22010A97,
+REG64( C_3_SPATTN_SCOM                                         , RULL(0x23040004), SH_UNT_C_3      ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23010A99,
+REG64( C_3_SPATTN_SCOM1                                        , RULL(0x23040005), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 23010A98,
+REG64( C_3_SPATTN_SCOM2                                        , RULL(0x23040006), SH_UNT_C_3      ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 23010A97,
+REG64( C_4_SPATTN_SCOM                                         , RULL(0x24040004), SH_UNT_C_4      ,
+       SH_ACS_SCOM_RO   ); //DUPS: 24010A99,
+REG64( C_4_SPATTN_SCOM1                                        , RULL(0x24040005), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 24010A98,
+REG64( C_4_SPATTN_SCOM2                                        , RULL(0x24040006), SH_UNT_C_4      ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 24010A97,
+REG64( C_5_SPATTN_SCOM                                         , RULL(0x25040004), SH_UNT_C_5      ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25010A99,
+REG64( C_5_SPATTN_SCOM1                                        , RULL(0x25040005), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 25010A98,
+REG64( C_5_SPATTN_SCOM2                                        , RULL(0x25040006), SH_UNT_C_5      ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 25010A97,
+REG64( C_6_SPATTN_SCOM                                         , RULL(0x26040004), SH_UNT_C_6      ,
+       SH_ACS_SCOM_RO   ); //DUPS: 26010A99,
+REG64( C_6_SPATTN_SCOM1                                        , RULL(0x26040005), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 26010A98,
+REG64( C_6_SPATTN_SCOM2                                        , RULL(0x26040006), SH_UNT_C_6      ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 26010A97,
+REG64( C_7_SPATTN_SCOM                                         , RULL(0x27040004), SH_UNT_C_7      ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27010A99,
+REG64( C_7_SPATTN_SCOM1                                        , RULL(0x27040005), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 27010A98,
+REG64( C_7_SPATTN_SCOM2                                        , RULL(0x27040006), SH_UNT_C_7      ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 27010A97,
+REG64( C_8_SPATTN_SCOM                                         , RULL(0x28040004), SH_UNT_C_8      ,
+       SH_ACS_SCOM_RO   ); //DUPS: 28010A99,
+REG64( C_8_SPATTN_SCOM1                                        , RULL(0x28040005), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 28010A98,
+REG64( C_8_SPATTN_SCOM2                                        , RULL(0x28040006), SH_UNT_C_8      ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 28010A97,
+REG64( C_9_SPATTN_SCOM                                         , RULL(0x29040004), SH_UNT_C_9      ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29010A99,
+REG64( C_9_SPATTN_SCOM1                                        , RULL(0x29040005), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 29010A98,
+REG64( C_9_SPATTN_SCOM2                                        , RULL(0x29040006), SH_UNT_C_9      ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 29010A97,
+REG64( C_10_SPATTN_SCOM                                        , RULL(0x2A040004), SH_UNT_C_10     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2A010A99,
+REG64( C_10_SPATTN_SCOM1                                       , RULL(0x2A040005), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 2A010A98,
+REG64( C_10_SPATTN_SCOM2                                       , RULL(0x2A040006), SH_UNT_C_10     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 2A010A97,
+REG64( C_11_SPATTN_SCOM                                        , RULL(0x2B040004), SH_UNT_C_11     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B010A99,
+REG64( C_11_SPATTN_SCOM1                                       , RULL(0x2B040005), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 2B010A98,
+REG64( C_11_SPATTN_SCOM2                                       , RULL(0x2B040006), SH_UNT_C_11     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 2B010A97,
+REG64( C_12_SPATTN_SCOM                                        , RULL(0x2C040004), SH_UNT_C_12     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2C010A99,
+REG64( C_12_SPATTN_SCOM1                                       , RULL(0x2C040005), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 2C010A98,
+REG64( C_12_SPATTN_SCOM2                                       , RULL(0x2C040006), SH_UNT_C_12     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 2C010A97,
+REG64( C_13_SPATTN_SCOM                                        , RULL(0x2D040004), SH_UNT_C_13     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D010A99,
+REG64( C_13_SPATTN_SCOM1                                       , RULL(0x2D040005), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 2D010A98,
+REG64( C_13_SPATTN_SCOM2                                       , RULL(0x2D040006), SH_UNT_C_13     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 2D010A97,
+REG64( C_14_SPATTN_SCOM                                        , RULL(0x2E040004), SH_UNT_C_14     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2E010A99,
+REG64( C_14_SPATTN_SCOM1                                       , RULL(0x2E040005), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 2E010A98,
+REG64( C_14_SPATTN_SCOM2                                       , RULL(0x2E040006), SH_UNT_C_14     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 2E010A97,
+REG64( C_15_SPATTN_SCOM                                        , RULL(0x2F040004), SH_UNT_C_15     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F010A99,
+REG64( C_15_SPATTN_SCOM1                                       , RULL(0x2F040005), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 2F010A98,
+REG64( C_15_SPATTN_SCOM2                                       , RULL(0x2F040006), SH_UNT_C_15     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 2F010A97,
+REG64( C_16_SPATTN_SCOM                                        , RULL(0x30040004), SH_UNT_C_16     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 30010A99,
+REG64( C_16_SPATTN_SCOM1                                       , RULL(0x30040005), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 30010A98,
+REG64( C_16_SPATTN_SCOM2                                       , RULL(0x30040006), SH_UNT_C_16     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 30010A97,
+REG64( C_17_SPATTN_SCOM                                        , RULL(0x31040004), SH_UNT_C_17     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31010A99,
+REG64( C_17_SPATTN_SCOM1                                       , RULL(0x31040005), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 31010A98,
+REG64( C_17_SPATTN_SCOM2                                       , RULL(0x31040006), SH_UNT_C_17     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 31010A97,
+REG64( C_18_SPATTN_SCOM                                        , RULL(0x32040004), SH_UNT_C_18     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 32010A99,
+REG64( C_18_SPATTN_SCOM1                                       , RULL(0x32040005), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 32010A98,
+REG64( C_18_SPATTN_SCOM2                                       , RULL(0x32040006), SH_UNT_C_18     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 32010A97,
+REG64( C_19_SPATTN_SCOM                                        , RULL(0x33040004), SH_UNT_C_19     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33010A99,
+REG64( C_19_SPATTN_SCOM1                                       , RULL(0x33040005), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 33010A98,
+REG64( C_19_SPATTN_SCOM2                                       , RULL(0x33040006), SH_UNT_C_19     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 33010A97,
+REG64( C_20_SPATTN_SCOM                                        , RULL(0x34040004), SH_UNT_C_20     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 34010A99,
+REG64( C_20_SPATTN_SCOM1                                       , RULL(0x34040005), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 34010A98,
+REG64( C_20_SPATTN_SCOM2                                       , RULL(0x34040006), SH_UNT_C_20     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 34010A97,
+REG64( C_21_SPATTN_SCOM                                        , RULL(0x35040004), SH_UNT_C_21     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35010A99,
+REG64( C_21_SPATTN_SCOM1                                       , RULL(0x35040005), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 35010A98,
+REG64( C_21_SPATTN_SCOM2                                       , RULL(0x35040006), SH_UNT_C_21     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 35010A97,
+REG64( C_22_SPATTN_SCOM                                        , RULL(0x36040004), SH_UNT_C_22     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 36010A99,
+REG64( C_22_SPATTN_SCOM1                                       , RULL(0x36040005), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 36010A98,
+REG64( C_22_SPATTN_SCOM2                                       , RULL(0x36040006), SH_UNT_C_22     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 36010A97,
+REG64( C_23_SPATTN_SCOM                                        , RULL(0x37040004), SH_UNT_C_23     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37010A99,
+REG64( C_23_SPATTN_SCOM1                                       , RULL(0x37040005), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 37010A98,
+REG64( C_23_SPATTN_SCOM2                                       , RULL(0x37040006), SH_UNT_C_23     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 37010A97,
+REG64( EQ_SPATTN_SCOM                                          , RULL(0x10040004), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_SPATTN_SCOM1                                         , RULL(0x10040005), SH_UNT_EQ       , SH_ACS_SCOM1_NC  );
+REG64( EQ_SPATTN_SCOM2                                         , RULL(0x10040006), SH_UNT_EQ       , SH_ACS_SCOM2_NC  );
+REG64( EQ_0_SPATTN_SCOM                                        , RULL(0x10040004), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_0_SPATTN_SCOM1                                       , RULL(0x10040005), SH_UNT_EQ_0     , SH_ACS_SCOM1_NC  );
+REG64( EQ_0_SPATTN_SCOM2                                       , RULL(0x10040006), SH_UNT_EQ_0     , SH_ACS_SCOM2_NC  );
+REG64( EQ_1_SPATTN_SCOM                                        , RULL(0x11040004), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_SPATTN_SCOM1                                       , RULL(0x11040005), SH_UNT_EQ_1     , SH_ACS_SCOM1_NC  );
+REG64( EQ_1_SPATTN_SCOM2                                       , RULL(0x11040006), SH_UNT_EQ_1     , SH_ACS_SCOM2_NC  );
+REG64( EQ_2_SPATTN_SCOM                                        , RULL(0x12040004), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_SPATTN_SCOM1                                       , RULL(0x12040005), SH_UNT_EQ_2     , SH_ACS_SCOM1_NC  );
+REG64( EQ_2_SPATTN_SCOM2                                       , RULL(0x12040006), SH_UNT_EQ_2     , SH_ACS_SCOM2_NC  );
+REG64( EQ_3_SPATTN_SCOM                                        , RULL(0x13040004), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_SPATTN_SCOM1                                       , RULL(0x13040005), SH_UNT_EQ_3     , SH_ACS_SCOM1_NC  );
+REG64( EQ_3_SPATTN_SCOM2                                       , RULL(0x13040006), SH_UNT_EQ_3     , SH_ACS_SCOM2_NC  );
+REG64( EQ_4_SPATTN_SCOM                                        , RULL(0x14040004), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_SPATTN_SCOM1                                       , RULL(0x14040005), SH_UNT_EQ_4     , SH_ACS_SCOM1_NC  );
+REG64( EQ_4_SPATTN_SCOM2                                       , RULL(0x14040006), SH_UNT_EQ_4     , SH_ACS_SCOM2_NC  );
+REG64( EQ_5_SPATTN_SCOM                                        , RULL(0x15040004), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_SPATTN_SCOM1                                       , RULL(0x15040005), SH_UNT_EQ_5     , SH_ACS_SCOM1_NC  );
+REG64( EQ_5_SPATTN_SCOM2                                       , RULL(0x15040006), SH_UNT_EQ_5     , SH_ACS_SCOM2_NC  );
+REG64( EX_SPATTN_SCOM                                          , RULL(0x20040004), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21040004, 21010A99, 20010A99,
+REG64( EX_SPATTN_SCOM1                                         , RULL(0x20040005), SH_UNT_EX       ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 21040005, 21010A98, 20010A98,
+REG64( EX_SPATTN_SCOM2                                         , RULL(0x20040006), SH_UNT_EX       ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 21040006,
+REG64( EX_0_SPATTN_SCOM                                        , RULL(0x20040004), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21040004, 21010A99, 20010A99,
+REG64( EX_0_SPATTN_SCOM1                                       , RULL(0x20040005), SH_UNT_EX_0     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 21040005, 21010A98, 20010A98,
+REG64( EX_0_SPATTN_SCOM2                                       , RULL(0x20040006), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 21040006,
+REG64( EX_1_SPATTN_SCOM                                        , RULL(0x22040004), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23040004, 23010A99, 22010A99,
+REG64( EX_1_SPATTN_SCOM1                                       , RULL(0x22040005), SH_UNT_EX_1     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 23040005, 23010A98, 22010A98,
+REG64( EX_1_SPATTN_SCOM2                                       , RULL(0x22040006), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 23040006,
+REG64( EX_2_SPATTN_SCOM                                        , RULL(0x24040004), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25040004, 25010A99, 24010A99,
+REG64( EX_2_SPATTN_SCOM1                                       , RULL(0x24040005), SH_UNT_EX_2     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 25040005, 25010A98, 24010A98,
+REG64( EX_2_SPATTN_SCOM2                                       , RULL(0x24040006), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 25040006,
+REG64( EX_3_SPATTN_SCOM                                        , RULL(0x26040004), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27040004, 27010A99, 26010A99,
+REG64( EX_3_SPATTN_SCOM1                                       , RULL(0x26040005), SH_UNT_EX_3     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 27040005, 27010A98, 26010A98,
+REG64( EX_3_SPATTN_SCOM2                                       , RULL(0x26040006), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 27040006,
+REG64( EX_4_SPATTN_SCOM                                        , RULL(0x28040004), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29040004, 29010A99, 28010A99,
+REG64( EX_4_SPATTN_SCOM1                                       , RULL(0x28040005), SH_UNT_EX_4     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 29040005, 29010A98, 28010A98,
+REG64( EX_4_SPATTN_SCOM2                                       , RULL(0x28040006), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 29040006,
+REG64( EX_5_SPATTN_SCOM                                        , RULL(0x2A040004), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B040004, 2B010A99, 2A010A99,
+REG64( EX_5_SPATTN_SCOM1                                       , RULL(0x2A040005), SH_UNT_EX_5     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 2B040005, 2B010A98, 2A010A98,
+REG64( EX_5_SPATTN_SCOM2                                       , RULL(0x2A040006), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 2B040006,
+REG64( EX_6_SPATTN_SCOM                                        , RULL(0x2C040004), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D040004, 2D010A99, 2C010A99,
+REG64( EX_6_SPATTN_SCOM1                                       , RULL(0x2C040005), SH_UNT_EX_6     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 2D040005, 2D010A98, 2C010A98,
+REG64( EX_6_SPATTN_SCOM2                                       , RULL(0x2C040006), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 2D040006,
+REG64( EX_7_SPATTN_SCOM                                        , RULL(0x2E040004), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F040004, 2F010A99, 2E010A99,
+REG64( EX_7_SPATTN_SCOM1                                       , RULL(0x2E040005), SH_UNT_EX_7     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 2F040005, 2F010A98, 2E010A98,
+REG64( EX_7_SPATTN_SCOM2                                       , RULL(0x2E040006), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 2F040006,
+REG64( EX_8_SPATTN_SCOM                                        , RULL(0x30040004), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31040004, 31010A99, 30010A99,
+REG64( EX_8_SPATTN_SCOM1                                       , RULL(0x30040005), SH_UNT_EX_8     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 31040005, 31010A98, 30010A98,
+REG64( EX_8_SPATTN_SCOM2                                       , RULL(0x30040006), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 31040006,
+REG64( EX_9_SPATTN_SCOM                                        , RULL(0x32040004), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33040004, 33010A99, 32010A99,
+REG64( EX_9_SPATTN_SCOM1                                       , RULL(0x32040005), SH_UNT_EX_9     ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 33040005, 33010A98, 32010A98,
+REG64( EX_9_SPATTN_SCOM2                                       , RULL(0x32040006), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 33040006,
+REG64( EX_0_L2_SPATTN                                          , RULL(0x21010A97), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 20010A97,
+REG64( EX_10_SPATTN_SCOM                                       , RULL(0x34040004), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35040004, 35010A99, 34010A99,
+REG64( EX_10_SPATTN_SCOM1                                      , RULL(0x34040005), SH_UNT_EX_10    ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 35040005, 35010A98, 34010A98,
+REG64( EX_10_SPATTN_SCOM2                                      , RULL(0x34040006), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 35040006,
+REG64( EX_11_SPATTN_SCOM                                       , RULL(0x36040004), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37040004, 37010A99, 36010A99,
+REG64( EX_11_SPATTN_SCOM1                                      , RULL(0x36040005), SH_UNT_EX_11    ,
+       SH_ACS_SCOM1_NC  ); //DUPS: 37040005, 37010A98, 36010A98,
+REG64( EX_11_SPATTN_SCOM2                                      , RULL(0x36040006), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_NC  ); //DUPS: 37040006,
+REG64( EX_10_L2_SPATTN                                         , RULL(0x35010A97), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 34010A97,
+REG64( EX_11_L2_SPATTN                                         , RULL(0x37010A97), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 36010A97,
+REG64( EX_1_L2_SPATTN                                          , RULL(0x23010A97), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 22010A97,
+REG64( EX_2_L2_SPATTN                                          , RULL(0x25010A97), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 24010A97,
+REG64( EX_3_L2_SPATTN                                          , RULL(0x27010A97), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 26010A97,
+REG64( EX_4_L2_SPATTN                                          , RULL(0x29010A97), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 28010A97,
+REG64( EX_5_L2_SPATTN                                          , RULL(0x2B010A97), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2A010A97,
+REG64( EX_6_L2_SPATTN                                          , RULL(0x2D010A97), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2C010A97,
+REG64( EX_7_L2_SPATTN                                          , RULL(0x2F010A97), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2E010A97,
+REG64( EX_8_L2_SPATTN                                          , RULL(0x31010A97), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 30010A97,
+REG64( EX_9_L2_SPATTN                                          , RULL(0x33010A97), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 32010A97,
+REG64( EX_L2_SPATTN                                            , RULL(0x21010A97), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 20010A97,
+
+REG64( C_SPATTN_MASK                                           , RULL(0x20010A9A), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_SPATTN_MASK                                         , RULL(0x20010A9A), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_SPATTN_MASK                                         , RULL(0x21010A9A), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_SPATTN_MASK                                         , RULL(0x22010A9A), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_SPATTN_MASK                                         , RULL(0x23010A9A), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_SPATTN_MASK                                         , RULL(0x24010A9A), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_SPATTN_MASK                                         , RULL(0x25010A9A), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_SPATTN_MASK                                         , RULL(0x26010A9A), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_SPATTN_MASK                                         , RULL(0x27010A9A), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_SPATTN_MASK                                         , RULL(0x28010A9A), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_SPATTN_MASK                                         , RULL(0x29010A9A), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_SPATTN_MASK                                        , RULL(0x2A010A9A), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_SPATTN_MASK                                        , RULL(0x2B010A9A), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_SPATTN_MASK                                        , RULL(0x2C010A9A), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_SPATTN_MASK                                        , RULL(0x2D010A9A), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_SPATTN_MASK                                        , RULL(0x2E010A9A), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_SPATTN_MASK                                        , RULL(0x2F010A9A), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_SPATTN_MASK                                        , RULL(0x30010A9A), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_SPATTN_MASK                                        , RULL(0x31010A9A), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_SPATTN_MASK                                        , RULL(0x32010A9A), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_SPATTN_MASK                                        , RULL(0x33010A9A), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_SPATTN_MASK                                        , RULL(0x34010A9A), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_SPATTN_MASK                                        , RULL(0x35010A9A), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_SPATTN_MASK                                        , RULL(0x36010A9A), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_SPATTN_MASK                                        , RULL(0x37010A9A), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_SPATTN_MASK                                     , RULL(0x21010A9A), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 20010A9A,
+REG64( EX_10_L2_SPATTN_MASK                                    , RULL(0x35010A9A), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 34010A9A,
+REG64( EX_11_L2_SPATTN_MASK                                    , RULL(0x37010A9A), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 36010A9A,
+REG64( EX_1_L2_SPATTN_MASK                                     , RULL(0x23010A9A), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 22010A9A,
+REG64( EX_2_L2_SPATTN_MASK                                     , RULL(0x25010A9A), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 24010A9A,
+REG64( EX_3_L2_SPATTN_MASK                                     , RULL(0x27010A9A), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 26010A9A,
+REG64( EX_4_L2_SPATTN_MASK                                     , RULL(0x29010A9A), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 28010A9A,
+REG64( EX_5_L2_SPATTN_MASK                                     , RULL(0x2B010A9A), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2A010A9A,
+REG64( EX_6_L2_SPATTN_MASK                                     , RULL(0x2D010A9A), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2C010A9A,
+REG64( EX_7_L2_SPATTN_MASK                                     , RULL(0x2F010A9A), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2E010A9A,
+REG64( EX_8_L2_SPATTN_MASK                                     , RULL(0x31010A9A), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 30010A9A,
+REG64( EX_9_L2_SPATTN_MASK                                     , RULL(0x33010A9A), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 32010A9A,
+REG64( EX_L2_SPATTN_MASK                                       , RULL(0x21010A9A), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 20010A9A,
+
+REG64( C_SPA_MASK                                              , RULL(0x20040007), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_SPA_MASK                                            , RULL(0x20040007), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_SPA_MASK                                            , RULL(0x21040007), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_SPA_MASK                                            , RULL(0x22040007), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_SPA_MASK                                            , RULL(0x23040007), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_SPA_MASK                                            , RULL(0x24040007), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_SPA_MASK                                            , RULL(0x25040007), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_SPA_MASK                                            , RULL(0x26040007), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_SPA_MASK                                            , RULL(0x27040007), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_SPA_MASK                                            , RULL(0x28040007), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_SPA_MASK                                            , RULL(0x29040007), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_SPA_MASK                                           , RULL(0x2A040007), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_SPA_MASK                                           , RULL(0x2B040007), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_SPA_MASK                                           , RULL(0x2C040007), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_SPA_MASK                                           , RULL(0x2D040007), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_SPA_MASK                                           , RULL(0x2E040007), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_SPA_MASK                                           , RULL(0x2F040007), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_SPA_MASK                                           , RULL(0x30040007), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_SPA_MASK                                           , RULL(0x31040007), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_SPA_MASK                                           , RULL(0x32040007), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_SPA_MASK                                           , RULL(0x33040007), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_SPA_MASK                                           , RULL(0x34040007), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_SPA_MASK                                           , RULL(0x35040007), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_SPA_MASK                                           , RULL(0x36040007), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_SPA_MASK                                           , RULL(0x37040007), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_SPA_MASK                                             , RULL(0x10040007), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_SPA_MASK                                           , RULL(0x10040007), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_SPA_MASK                                           , RULL(0x11040007), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_SPA_MASK                                           , RULL(0x12040007), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_SPA_MASK                                           , RULL(0x13040007), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_SPA_MASK                                           , RULL(0x14040007), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_SPA_MASK                                           , RULL(0x15040007), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_SPA_MASK                                             , RULL(0x20040007), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21040007,
+REG64( EX_0_SPA_MASK                                           , RULL(0x20040007), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21040007,
+REG64( EX_1_SPA_MASK                                           , RULL(0x22040007), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23040007,
+REG64( EX_2_SPA_MASK                                           , RULL(0x24040007), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25040007,
+REG64( EX_3_SPA_MASK                                           , RULL(0x26040007), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27040007,
+REG64( EX_4_SPA_MASK                                           , RULL(0x28040007), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29040007,
+REG64( EX_5_SPA_MASK                                           , RULL(0x2A040007), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B040007,
+REG64( EX_6_SPA_MASK                                           , RULL(0x2C040007), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D040007,
+REG64( EX_7_SPA_MASK                                           , RULL(0x2E040007), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F040007,
+REG64( EX_8_SPA_MASK                                           , RULL(0x30040007), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31040007,
+REG64( EX_9_SPA_MASK                                           , RULL(0x32040007), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33040007,
+REG64( EX_10_SPA_MASK                                          , RULL(0x34040007), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35040007,
+REG64( EX_11_SPA_MASK                                          , RULL(0x36040007), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37040007,
+
+REG64( C_SPR_COMMON_HOLD_OUT                                   , RULL(0x20010AB8), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_SPR_COMMON_HOLD_OUT                                 , RULL(0x20010AB8), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_SPR_COMMON_HOLD_OUT                                 , RULL(0x21010AB8), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_SPR_COMMON_HOLD_OUT                                 , RULL(0x22010AB8), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_SPR_COMMON_HOLD_OUT                                 , RULL(0x23010AB8), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_SPR_COMMON_HOLD_OUT                                 , RULL(0x24010AB8), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_SPR_COMMON_HOLD_OUT                                 , RULL(0x25010AB8), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_SPR_COMMON_HOLD_OUT                                 , RULL(0x26010AB8), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_SPR_COMMON_HOLD_OUT                                 , RULL(0x27010AB8), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_SPR_COMMON_HOLD_OUT                                 , RULL(0x28010AB8), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_SPR_COMMON_HOLD_OUT                                 , RULL(0x29010AB8), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_SPR_COMMON_HOLD_OUT                                , RULL(0x2A010AB8), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_SPR_COMMON_HOLD_OUT                                , RULL(0x2B010AB8), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_SPR_COMMON_HOLD_OUT                                , RULL(0x2C010AB8), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_SPR_COMMON_HOLD_OUT                                , RULL(0x2D010AB8), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_SPR_COMMON_HOLD_OUT                                , RULL(0x2E010AB8), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_SPR_COMMON_HOLD_OUT                                , RULL(0x2F010AB8), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_SPR_COMMON_HOLD_OUT                                , RULL(0x30010AB8), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_SPR_COMMON_HOLD_OUT                                , RULL(0x31010AB8), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_SPR_COMMON_HOLD_OUT                                , RULL(0x32010AB8), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_SPR_COMMON_HOLD_OUT                                , RULL(0x33010AB8), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_SPR_COMMON_HOLD_OUT                                , RULL(0x34010AB8), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_SPR_COMMON_HOLD_OUT                                , RULL(0x35010AB8), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_SPR_COMMON_HOLD_OUT                                , RULL(0x36010AB8), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_SPR_COMMON_HOLD_OUT                                , RULL(0x37010AB8), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_SPR_COMMON_HOLD_OUT                                  , RULL(0x21010AB8), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 20010AB8,
+REG64( EX_0_SPR_COMMON_HOLD_OUT                                , RULL(0x21010AB8), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 20010AB8,
+REG64( EX_1_SPR_COMMON_HOLD_OUT                                , RULL(0x23010AB8), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 22010AB8,
+REG64( EX_2_SPR_COMMON_HOLD_OUT                                , RULL(0x25010AB8), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 24010AB8,
+REG64( EX_3_SPR_COMMON_HOLD_OUT                                , RULL(0x27010AB8), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 26010AB8,
+REG64( EX_4_SPR_COMMON_HOLD_OUT                                , RULL(0x29010AB8), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 28010AB8,
+REG64( EX_5_SPR_COMMON_HOLD_OUT                                , RULL(0x2B010AB8), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2A010AB8,
+REG64( EX_6_SPR_COMMON_HOLD_OUT                                , RULL(0x2D010AB8), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2C010AB8,
+REG64( EX_7_SPR_COMMON_HOLD_OUT                                , RULL(0x2F010AB8), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2E010AB8,
+REG64( EX_8_SPR_COMMON_HOLD_OUT                                , RULL(0x31010AB8), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 30010AB8,
+REG64( EX_9_SPR_COMMON_HOLD_OUT                                , RULL(0x33010AB8), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 32010AB8,
+REG64( EX_10_SPR_COMMON_HOLD_OUT                               , RULL(0x35010AB8), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 34010AB8,
+REG64( EX_11_SPR_COMMON_HOLD_OUT                               , RULL(0x37010AB8), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 36010AB8,
+
+REG64( C_SPR_CORE_HOLD_OUT                                     , RULL(0x20010AB5), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_SPR_CORE_HOLD_OUT                                   , RULL(0x20010AB5), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_SPR_CORE_HOLD_OUT                                   , RULL(0x21010AB5), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_SPR_CORE_HOLD_OUT                                   , RULL(0x22010AB5), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_SPR_CORE_HOLD_OUT                                   , RULL(0x23010AB5), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_SPR_CORE_HOLD_OUT                                   , RULL(0x24010AB5), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_SPR_CORE_HOLD_OUT                                   , RULL(0x25010AB5), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_SPR_CORE_HOLD_OUT                                   , RULL(0x26010AB5), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_SPR_CORE_HOLD_OUT                                   , RULL(0x27010AB5), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_SPR_CORE_HOLD_OUT                                   , RULL(0x28010AB5), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_SPR_CORE_HOLD_OUT                                   , RULL(0x29010AB5), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_SPR_CORE_HOLD_OUT                                  , RULL(0x2A010AB5), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_SPR_CORE_HOLD_OUT                                  , RULL(0x2B010AB5), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_SPR_CORE_HOLD_OUT                                  , RULL(0x2C010AB5), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_SPR_CORE_HOLD_OUT                                  , RULL(0x2D010AB5), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_SPR_CORE_HOLD_OUT                                  , RULL(0x2E010AB5), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_SPR_CORE_HOLD_OUT                                  , RULL(0x2F010AB5), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_SPR_CORE_HOLD_OUT                                  , RULL(0x30010AB5), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_SPR_CORE_HOLD_OUT                                  , RULL(0x31010AB5), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_SPR_CORE_HOLD_OUT                                  , RULL(0x32010AB5), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_SPR_CORE_HOLD_OUT                                  , RULL(0x33010AB5), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_SPR_CORE_HOLD_OUT                                  , RULL(0x34010AB5), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_SPR_CORE_HOLD_OUT                                  , RULL(0x35010AB5), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_SPR_CORE_HOLD_OUT                                  , RULL(0x36010AB5), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_SPR_CORE_HOLD_OUT                                  , RULL(0x37010AB5), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_0_L2_SPR_CORE_HOLD_OUT                               , RULL(0x20010AB5), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010AB5,
+REG64( EX_10_L2_SPR_CORE_HOLD_OUT                              , RULL(0x34010AB5), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35010AB5,
+REG64( EX_11_L2_SPR_CORE_HOLD_OUT                              , RULL(0x36010AB5), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37010AB5,
+REG64( EX_1_L2_SPR_CORE_HOLD_OUT                               , RULL(0x22010AB5), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23010AB5,
+REG64( EX_2_L2_SPR_CORE_HOLD_OUT                               , RULL(0x24010AB5), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25010AB5,
+REG64( EX_3_L2_SPR_CORE_HOLD_OUT                               , RULL(0x26010AB5), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27010AB5,
+REG64( EX_4_L2_SPR_CORE_HOLD_OUT                               , RULL(0x28010AB5), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29010AB5,
+REG64( EX_5_L2_SPR_CORE_HOLD_OUT                               , RULL(0x2A010AB5), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B010AB5,
+REG64( EX_6_L2_SPR_CORE_HOLD_OUT                               , RULL(0x2C010AB5), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D010AB5,
+REG64( EX_7_L2_SPR_CORE_HOLD_OUT                               , RULL(0x2E010AB5), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F010AB5,
+REG64( EX_8_L2_SPR_CORE_HOLD_OUT                               , RULL(0x30010AB5), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31010AB5,
+REG64( EX_9_L2_SPR_CORE_HOLD_OUT                               , RULL(0x32010AB5), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33010AB5,
+REG64( EX_L2_SPR_CORE_HOLD_OUT                                 , RULL(0x20010AB5), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010AB5,
+
+REG64( C_SPR_MODE                                              , RULL(0x20010A84), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_SPR_MODE                                            , RULL(0x20010A84), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_SPR_MODE                                            , RULL(0x21010A84), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_SPR_MODE                                            , RULL(0x22010A84), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_SPR_MODE                                            , RULL(0x23010A84), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_SPR_MODE                                            , RULL(0x24010A84), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_SPR_MODE                                            , RULL(0x25010A84), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_SPR_MODE                                            , RULL(0x26010A84), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_SPR_MODE                                            , RULL(0x27010A84), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_SPR_MODE                                            , RULL(0x28010A84), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_SPR_MODE                                            , RULL(0x29010A84), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_SPR_MODE                                           , RULL(0x2A010A84), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_SPR_MODE                                           , RULL(0x2B010A84), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_SPR_MODE                                           , RULL(0x2C010A84), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_SPR_MODE                                           , RULL(0x2D010A84), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_SPR_MODE                                           , RULL(0x2E010A84), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_SPR_MODE                                           , RULL(0x2F010A84), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_SPR_MODE                                           , RULL(0x30010A84), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_SPR_MODE                                           , RULL(0x31010A84), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_SPR_MODE                                           , RULL(0x32010A84), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_SPR_MODE                                           , RULL(0x33010A84), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_SPR_MODE                                           , RULL(0x34010A84), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_SPR_MODE                                           , RULL(0x35010A84), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_SPR_MODE                                           , RULL(0x36010A84), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_SPR_MODE                                           , RULL(0x37010A84), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_SPR_MODE                                        , RULL(0x21010A84), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 20010A84,
+REG64( EX_10_L2_SPR_MODE                                       , RULL(0x35010A84), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 34010A84,
+REG64( EX_11_L2_SPR_MODE                                       , RULL(0x37010A84), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 36010A84,
+REG64( EX_1_L2_SPR_MODE                                        , RULL(0x23010A84), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 22010A84,
+REG64( EX_2_L2_SPR_MODE                                        , RULL(0x25010A84), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 24010A84,
+REG64( EX_3_L2_SPR_MODE                                        , RULL(0x27010A84), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 26010A84,
+REG64( EX_4_L2_SPR_MODE                                        , RULL(0x29010A84), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 28010A84,
+REG64( EX_5_L2_SPR_MODE                                        , RULL(0x2B010A84), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2A010A84,
+REG64( EX_6_L2_SPR_MODE                                        , RULL(0x2D010A84), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2C010A84,
+REG64( EX_7_L2_SPR_MODE                                        , RULL(0x2F010A84), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2E010A84,
+REG64( EX_8_L2_SPR_MODE                                        , RULL(0x31010A84), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 30010A84,
+REG64( EX_9_L2_SPR_MODE                                        , RULL(0x33010A84), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 32010A84,
+REG64( EX_L2_SPR_MODE                                          , RULL(0x21010A84), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 20010A84,
+
+REG64( C_SPURR_FREQ_DETECT_CYC_CNT                             , RULL(0x20010A9F), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_SPURR_FREQ_DETECT_CYC_CNT                           , RULL(0x20010A9F), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_SPURR_FREQ_DETECT_CYC_CNT                           , RULL(0x21010A9F), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_SPURR_FREQ_DETECT_CYC_CNT                           , RULL(0x22010A9F), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_SPURR_FREQ_DETECT_CYC_CNT                           , RULL(0x23010A9F), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_SPURR_FREQ_DETECT_CYC_CNT                           , RULL(0x24010A9F), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_SPURR_FREQ_DETECT_CYC_CNT                           , RULL(0x25010A9F), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_SPURR_FREQ_DETECT_CYC_CNT                           , RULL(0x26010A9F), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_SPURR_FREQ_DETECT_CYC_CNT                           , RULL(0x27010A9F), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_SPURR_FREQ_DETECT_CYC_CNT                           , RULL(0x28010A9F), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_SPURR_FREQ_DETECT_CYC_CNT                           , RULL(0x29010A9F), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x2A010A9F), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x2B010A9F), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x2C010A9F), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x2D010A9F), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x2E010A9F), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x2F010A9F), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x30010A9F), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x31010A9F), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x32010A9F), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x33010A9F), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x34010A9F), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x35010A9F), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x36010A9F), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x37010A9F), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_SPURR_FREQ_DETECT_CYC_CNT                            , RULL(0x21010A9F), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 20010A9F,
+REG64( EX_0_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x21010A9F), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 20010A9F,
+REG64( EX_1_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x23010A9F), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 22010A9F,
+REG64( EX_2_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x25010A9F), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 24010A9F,
+REG64( EX_3_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x27010A9F), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 26010A9F,
+REG64( EX_4_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x29010A9F), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 28010A9F,
+REG64( EX_5_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x2B010A9F), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2A010A9F,
+REG64( EX_6_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x2D010A9F), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2C010A9F,
+REG64( EX_7_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x2F010A9F), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2E010A9F,
+REG64( EX_8_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x31010A9F), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 30010A9F,
+REG64( EX_9_SPURR_FREQ_DETECT_CYC_CNT                          , RULL(0x33010A9F), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 32010A9F,
+REG64( EX_10_SPURR_FREQ_DETECT_CYC_CNT                         , RULL(0x35010A9F), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 34010A9F,
+REG64( EX_11_SPURR_FREQ_DETECT_CYC_CNT                         , RULL(0x37010A9F), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 36010A9F,
+
+REG64( C_SPURR_FREQ_REF                                        , RULL(0x20010AA1), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_SPURR_FREQ_REF                                      , RULL(0x20010AA1), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_SPURR_FREQ_REF                                      , RULL(0x21010AA1), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_SPURR_FREQ_REF                                      , RULL(0x22010AA1), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_SPURR_FREQ_REF                                      , RULL(0x23010AA1), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_SPURR_FREQ_REF                                      , RULL(0x24010AA1), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_SPURR_FREQ_REF                                      , RULL(0x25010AA1), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_SPURR_FREQ_REF                                      , RULL(0x26010AA1), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_SPURR_FREQ_REF                                      , RULL(0x27010AA1), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_SPURR_FREQ_REF                                      , RULL(0x28010AA1), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_SPURR_FREQ_REF                                      , RULL(0x29010AA1), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_SPURR_FREQ_REF                                     , RULL(0x2A010AA1), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_SPURR_FREQ_REF                                     , RULL(0x2B010AA1), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_SPURR_FREQ_REF                                     , RULL(0x2C010AA1), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_SPURR_FREQ_REF                                     , RULL(0x2D010AA1), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_SPURR_FREQ_REF                                     , RULL(0x2E010AA1), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_SPURR_FREQ_REF                                     , RULL(0x2F010AA1), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_SPURR_FREQ_REF                                     , RULL(0x30010AA1), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_SPURR_FREQ_REF                                     , RULL(0x31010AA1), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_SPURR_FREQ_REF                                     , RULL(0x32010AA1), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_SPURR_FREQ_REF                                     , RULL(0x33010AA1), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_SPURR_FREQ_REF                                     , RULL(0x34010AA1), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_SPURR_FREQ_REF                                     , RULL(0x35010AA1), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_SPURR_FREQ_REF                                     , RULL(0x36010AA1), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_SPURR_FREQ_REF                                     , RULL(0x37010AA1), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_SPURR_FREQ_REF                                  , RULL(0x21010AA1), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010AA1,
+REG64( EX_10_L2_SPURR_FREQ_REF                                 , RULL(0x35010AA1), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 34010AA1,
+REG64( EX_11_L2_SPURR_FREQ_REF                                 , RULL(0x37010AA1), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 36010AA1,
+REG64( EX_1_L2_SPURR_FREQ_REF                                  , RULL(0x23010AA1), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 22010AA1,
+REG64( EX_2_L2_SPURR_FREQ_REF                                  , RULL(0x25010AA1), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 24010AA1,
+REG64( EX_3_L2_SPURR_FREQ_REF                                  , RULL(0x27010AA1), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 26010AA1,
+REG64( EX_4_L2_SPURR_FREQ_REF                                  , RULL(0x29010AA1), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 28010AA1,
+REG64( EX_5_L2_SPURR_FREQ_REF                                  , RULL(0x2B010AA1), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2A010AA1,
+REG64( EX_6_L2_SPURR_FREQ_REF                                  , RULL(0x2D010AA1), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2C010AA1,
+REG64( EX_7_L2_SPURR_FREQ_REF                                  , RULL(0x2F010AA1), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2E010AA1,
+REG64( EX_8_L2_SPURR_FREQ_REF                                  , RULL(0x31010AA1), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 30010AA1,
+REG64( EX_9_L2_SPURR_FREQ_REF                                  , RULL(0x33010AA1), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 32010AA1,
+REG64( EX_L2_SPURR_FREQ_REF                                    , RULL(0x21010AA1), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010AA1,
+
+REG64( C_SPURR_FREQ_SCALE                                      , RULL(0x20010AA0), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_SPURR_FREQ_SCALE                                    , RULL(0x20010AA0), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_SPURR_FREQ_SCALE                                    , RULL(0x21010AA0), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_SPURR_FREQ_SCALE                                    , RULL(0x22010AA0), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_SPURR_FREQ_SCALE                                    , RULL(0x23010AA0), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_SPURR_FREQ_SCALE                                    , RULL(0x24010AA0), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_SPURR_FREQ_SCALE                                    , RULL(0x25010AA0), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_SPURR_FREQ_SCALE                                    , RULL(0x26010AA0), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_SPURR_FREQ_SCALE                                    , RULL(0x27010AA0), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_SPURR_FREQ_SCALE                                    , RULL(0x28010AA0), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_SPURR_FREQ_SCALE                                    , RULL(0x29010AA0), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_SPURR_FREQ_SCALE                                   , RULL(0x2A010AA0), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_SPURR_FREQ_SCALE                                   , RULL(0x2B010AA0), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_SPURR_FREQ_SCALE                                   , RULL(0x2C010AA0), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_SPURR_FREQ_SCALE                                   , RULL(0x2D010AA0), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_SPURR_FREQ_SCALE                                   , RULL(0x2E010AA0), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_SPURR_FREQ_SCALE                                   , RULL(0x2F010AA0), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_SPURR_FREQ_SCALE                                   , RULL(0x30010AA0), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_SPURR_FREQ_SCALE                                   , RULL(0x31010AA0), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_SPURR_FREQ_SCALE                                   , RULL(0x32010AA0), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_SPURR_FREQ_SCALE                                   , RULL(0x33010AA0), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_SPURR_FREQ_SCALE                                   , RULL(0x34010AA0), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_SPURR_FREQ_SCALE                                   , RULL(0x35010AA0), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_SPURR_FREQ_SCALE                                   , RULL(0x36010AA0), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_SPURR_FREQ_SCALE                                   , RULL(0x37010AA0), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_SPURR_FREQ_SCALE                                , RULL(0x21010AA0), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010AA0,
+REG64( EX_10_L2_SPURR_FREQ_SCALE                               , RULL(0x35010AA0), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 34010AA0,
+REG64( EX_11_L2_SPURR_FREQ_SCALE                               , RULL(0x37010AA0), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 36010AA0,
+REG64( EX_1_L2_SPURR_FREQ_SCALE                                , RULL(0x23010AA0), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 22010AA0,
+REG64( EX_2_L2_SPURR_FREQ_SCALE                                , RULL(0x25010AA0), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 24010AA0,
+REG64( EX_3_L2_SPURR_FREQ_SCALE                                , RULL(0x27010AA0), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 26010AA0,
+REG64( EX_4_L2_SPURR_FREQ_SCALE                                , RULL(0x29010AA0), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 28010AA0,
+REG64( EX_5_L2_SPURR_FREQ_SCALE                                , RULL(0x2B010AA0), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2A010AA0,
+REG64( EX_6_L2_SPURR_FREQ_SCALE                                , RULL(0x2D010AA0), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2C010AA0,
+REG64( EX_7_L2_SPURR_FREQ_SCALE                                , RULL(0x2F010AA0), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2E010AA0,
+REG64( EX_8_L2_SPURR_FREQ_SCALE                                , RULL(0x31010AA0), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 30010AA0,
+REG64( EX_9_L2_SPURR_FREQ_SCALE                                , RULL(0x33010AA0), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 32010AA0,
+REG64( EX_L2_SPURR_FREQ_SCALE                                  , RULL(0x21010AA0), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010AA0,
+
+REG64( C_SRC_MASK                                              , RULL(0x20010AAF), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_SRC_MASK                                            , RULL(0x20010AAF), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_SRC_MASK                                            , RULL(0x21010AAF), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_SRC_MASK                                            , RULL(0x22010AAF), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_SRC_MASK                                            , RULL(0x23010AAF), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_SRC_MASK                                            , RULL(0x24010AAF), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_SRC_MASK                                            , RULL(0x25010AAF), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_SRC_MASK                                            , RULL(0x26010AAF), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_SRC_MASK                                            , RULL(0x27010AAF), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_SRC_MASK                                            , RULL(0x28010AAF), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_SRC_MASK                                            , RULL(0x29010AAF), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_SRC_MASK                                           , RULL(0x2A010AAF), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_SRC_MASK                                           , RULL(0x2B010AAF), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_SRC_MASK                                           , RULL(0x2C010AAF), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_SRC_MASK                                           , RULL(0x2D010AAF), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_SRC_MASK                                           , RULL(0x2E010AAF), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_SRC_MASK                                           , RULL(0x2F010AAF), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_SRC_MASK                                           , RULL(0x30010AAF), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_SRC_MASK                                           , RULL(0x31010AAF), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_SRC_MASK                                           , RULL(0x32010AAF), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_SRC_MASK                                           , RULL(0x33010AAF), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_SRC_MASK                                           , RULL(0x34010AAF), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_SRC_MASK                                           , RULL(0x35010AAF), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_SRC_MASK                                           , RULL(0x36010AAF), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_SRC_MASK                                           , RULL(0x37010AAF), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_SRC_MASK                                             , RULL(0x20010AAF), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21010AAF,
+REG64( EX_0_SRC_MASK                                           , RULL(0x20010AAF), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21010AAF,
+REG64( EX_1_SRC_MASK                                           , RULL(0x22010AAF), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23010AAF,
+REG64( EX_2_SRC_MASK                                           , RULL(0x24010AAF), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25010AAF,
+REG64( EX_3_SRC_MASK                                           , RULL(0x26010AAF), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27010AAF,
+REG64( EX_4_SRC_MASK                                           , RULL(0x28010AAF), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29010AAF,
+REG64( EX_5_SRC_MASK                                           , RULL(0x2A010AAF), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B010AAF,
+REG64( EX_6_SRC_MASK                                           , RULL(0x2C010AAF), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D010AAF,
+REG64( EX_7_SRC_MASK                                           , RULL(0x2E010AAF), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F010AAF,
+REG64( EX_8_SRC_MASK                                           , RULL(0x30010AAF), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31010AAF,
+REG64( EX_9_SRC_MASK                                           , RULL(0x32010AAF), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33010AAF,
+REG64( EX_10_SRC_MASK                                          , RULL(0x34010AAF), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35010AAF,
+REG64( EX_11_SRC_MASK                                          , RULL(0x36010AAF), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37010AAF,
+
+REG64( C_SUM_MASK_REG                                          , RULL(0x20040017), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_SUM_MASK_REG                                        , RULL(0x20040017), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_SUM_MASK_REG                                        , RULL(0x21040017), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_SUM_MASK_REG                                        , RULL(0x22040017), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_SUM_MASK_REG                                        , RULL(0x23040017), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_SUM_MASK_REG                                        , RULL(0x24040017), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_SUM_MASK_REG                                        , RULL(0x25040017), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_SUM_MASK_REG                                        , RULL(0x26040017), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_SUM_MASK_REG                                        , RULL(0x27040017), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_SUM_MASK_REG                                        , RULL(0x28040017), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_SUM_MASK_REG                                        , RULL(0x29040017), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_SUM_MASK_REG                                       , RULL(0x2A040017), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_SUM_MASK_REG                                       , RULL(0x2B040017), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_SUM_MASK_REG                                       , RULL(0x2C040017), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_SUM_MASK_REG                                       , RULL(0x2D040017), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_SUM_MASK_REG                                       , RULL(0x2E040017), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_SUM_MASK_REG                                       , RULL(0x2F040017), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_SUM_MASK_REG                                       , RULL(0x30040017), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_SUM_MASK_REG                                       , RULL(0x31040017), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_SUM_MASK_REG                                       , RULL(0x32040017), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_SUM_MASK_REG                                       , RULL(0x33040017), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_SUM_MASK_REG                                       , RULL(0x34040017), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_SUM_MASK_REG                                       , RULL(0x35040017), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_SUM_MASK_REG                                       , RULL(0x36040017), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_SUM_MASK_REG                                       , RULL(0x37040017), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_SUM_MASK_REG                                         , RULL(0x10040017), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_SUM_MASK_REG                                       , RULL(0x10040017), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_SUM_MASK_REG                                       , RULL(0x11040017), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_SUM_MASK_REG                                       , RULL(0x12040017), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_SUM_MASK_REG                                       , RULL(0x13040017), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_SUM_MASK_REG                                       , RULL(0x14040017), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_SUM_MASK_REG                                       , RULL(0x15040017), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_SUM_MASK_REG                                         , RULL(0x20040017), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21040017,
+REG64( EX_0_SUM_MASK_REG                                       , RULL(0x20040017), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21040017,
+REG64( EX_1_SUM_MASK_REG                                       , RULL(0x22040017), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23040017,
+REG64( EX_2_SUM_MASK_REG                                       , RULL(0x24040017), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25040017,
+REG64( EX_3_SUM_MASK_REG                                       , RULL(0x26040017), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27040017,
+REG64( EX_4_SUM_MASK_REG                                       , RULL(0x28040017), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29040017,
+REG64( EX_5_SUM_MASK_REG                                       , RULL(0x2A040017), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B040017,
+REG64( EX_6_SUM_MASK_REG                                       , RULL(0x2C040017), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D040017,
+REG64( EX_7_SUM_MASK_REG                                       , RULL(0x2E040017), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F040017,
+REG64( EX_8_SUM_MASK_REG                                       , RULL(0x30040017), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31040017,
+REG64( EX_9_SUM_MASK_REG                                       , RULL(0x32040017), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33040017,
+REG64( EX_10_SUM_MASK_REG                                      , RULL(0x34040017), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35040017,
+REG64( EX_11_SUM_MASK_REG                                      , RULL(0x36040017), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37040017,
+
+REG64( C_SYNC_CONFIG                                           , RULL(0x20030000), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_SYNC_CONFIG                                         , RULL(0x20030000), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_SYNC_CONFIG                                         , RULL(0x21030000), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_SYNC_CONFIG                                         , RULL(0x22030000), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_SYNC_CONFIG                                         , RULL(0x23030000), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_SYNC_CONFIG                                         , RULL(0x24030000), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_SYNC_CONFIG                                         , RULL(0x25030000), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_SYNC_CONFIG                                         , RULL(0x26030000), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_SYNC_CONFIG                                         , RULL(0x27030000), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_SYNC_CONFIG                                         , RULL(0x28030000), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_SYNC_CONFIG                                         , RULL(0x29030000), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_SYNC_CONFIG                                        , RULL(0x2A030000), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_SYNC_CONFIG                                        , RULL(0x2B030000), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_SYNC_CONFIG                                        , RULL(0x2C030000), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_SYNC_CONFIG                                        , RULL(0x2D030000), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_SYNC_CONFIG                                        , RULL(0x2E030000), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_SYNC_CONFIG                                        , RULL(0x2F030000), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_SYNC_CONFIG                                        , RULL(0x30030000), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_SYNC_CONFIG                                        , RULL(0x31030000), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_SYNC_CONFIG                                        , RULL(0x32030000), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_SYNC_CONFIG                                        , RULL(0x33030000), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_SYNC_CONFIG                                        , RULL(0x34030000), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_SYNC_CONFIG                                        , RULL(0x35030000), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_SYNC_CONFIG                                        , RULL(0x36030000), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_SYNC_CONFIG                                        , RULL(0x37030000), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_SYNC_CONFIG                                          , RULL(0x10030000), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_SYNC_CONFIG                                        , RULL(0x10030000), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_SYNC_CONFIG                                        , RULL(0x11030000), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_SYNC_CONFIG                                        , RULL(0x12030000), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_SYNC_CONFIG                                        , RULL(0x13030000), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_SYNC_CONFIG                                        , RULL(0x14030000), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_SYNC_CONFIG                                        , RULL(0x15030000), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_SYNC_CONFIG                                          , RULL(0x20030000), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21030000,
+REG64( EX_0_SYNC_CONFIG                                        , RULL(0x20030000), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21030000,
+REG64( EX_1_SYNC_CONFIG                                        , RULL(0x22030000), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23030000,
+REG64( EX_2_SYNC_CONFIG                                        , RULL(0x24030000), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25030000,
+REG64( EX_3_SYNC_CONFIG                                        , RULL(0x26030000), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27030000,
+REG64( EX_4_SYNC_CONFIG                                        , RULL(0x28030000), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29030000,
+REG64( EX_5_SYNC_CONFIG                                        , RULL(0x2A030000), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B030000,
+REG64( EX_6_SYNC_CONFIG                                        , RULL(0x2C030000), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D030000,
+REG64( EX_7_SYNC_CONFIG                                        , RULL(0x2E030000), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F030000,
+REG64( EX_8_SYNC_CONFIG                                        , RULL(0x30030000), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31030000,
+REG64( EX_9_SYNC_CONFIG                                        , RULL(0x32030000), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33030000,
+REG64( EX_10_SYNC_CONFIG                                       , RULL(0x34030000), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35030000,
+REG64( EX_11_SYNC_CONFIG                                       , RULL(0x36030000), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37030000,
+
+REG64( C_T0_PMU_SCOM                                           , RULL(0x20010AAA), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_T0_PMU_SCOM                                         , RULL(0x20010AAA), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_T0_PMU_SCOM                                         , RULL(0x21010AAA), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_T0_PMU_SCOM                                         , RULL(0x22010AAA), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_T0_PMU_SCOM                                         , RULL(0x23010AAA), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_T0_PMU_SCOM                                         , RULL(0x24010AAA), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_T0_PMU_SCOM                                         , RULL(0x25010AAA), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_T0_PMU_SCOM                                         , RULL(0x26010AAA), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_T0_PMU_SCOM                                         , RULL(0x27010AAA), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_T0_PMU_SCOM                                         , RULL(0x28010AAA), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_T0_PMU_SCOM                                         , RULL(0x29010AAA), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_T0_PMU_SCOM                                        , RULL(0x2A010AAA), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_T0_PMU_SCOM                                        , RULL(0x2B010AAA), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_T0_PMU_SCOM                                        , RULL(0x2C010AAA), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_T0_PMU_SCOM                                        , RULL(0x2D010AAA), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_T0_PMU_SCOM                                        , RULL(0x2E010AAA), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_T0_PMU_SCOM                                        , RULL(0x2F010AAA), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_T0_PMU_SCOM                                        , RULL(0x30010AAA), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_T0_PMU_SCOM                                        , RULL(0x31010AAA), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_T0_PMU_SCOM                                        , RULL(0x32010AAA), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_T0_PMU_SCOM                                        , RULL(0x33010AAA), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_T0_PMU_SCOM                                        , RULL(0x34010AAA), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_T0_PMU_SCOM                                        , RULL(0x35010AAA), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_T0_PMU_SCOM                                        , RULL(0x36010AAA), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_T0_PMU_SCOM                                        , RULL(0x37010AAA), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_T0_PMU_SCOM                                     , RULL(0x20010AAA), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010AAA,
+REG64( EX_10_L2_T0_PMU_SCOM                                    , RULL(0x34010AAA), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010AAA,
+REG64( EX_11_L2_T0_PMU_SCOM                                    , RULL(0x36010AAA), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010AAA,
+REG64( EX_1_L2_T0_PMU_SCOM                                     , RULL(0x22010AAA), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010AAA,
+REG64( EX_2_L2_T0_PMU_SCOM                                     , RULL(0x24010AAA), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010AAA,
+REG64( EX_3_L2_T0_PMU_SCOM                                     , RULL(0x26010AAA), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010AAA,
+REG64( EX_4_L2_T0_PMU_SCOM                                     , RULL(0x28010AAA), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010AAA,
+REG64( EX_5_L2_T0_PMU_SCOM                                     , RULL(0x2A010AAA), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010AAA,
+REG64( EX_6_L2_T0_PMU_SCOM                                     , RULL(0x2C010AAA), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010AAA,
+REG64( EX_7_L2_T0_PMU_SCOM                                     , RULL(0x2E010AAA), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010AAA,
+REG64( EX_8_L2_T0_PMU_SCOM                                     , RULL(0x30010AAA), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010AAA,
+REG64( EX_9_L2_T0_PMU_SCOM                                     , RULL(0x32010AAA), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010AAA,
+REG64( EX_L2_T0_PMU_SCOM                                       , RULL(0x20010AAA), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010AAA,
+
+REG64( C_T1_PMU_SCOM                                           , RULL(0x20010AAB), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_T1_PMU_SCOM                                         , RULL(0x20010AAB), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_T1_PMU_SCOM                                         , RULL(0x21010AAB), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_T1_PMU_SCOM                                         , RULL(0x22010AAB), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_T1_PMU_SCOM                                         , RULL(0x23010AAB), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_T1_PMU_SCOM                                         , RULL(0x24010AAB), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_T1_PMU_SCOM                                         , RULL(0x25010AAB), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_T1_PMU_SCOM                                         , RULL(0x26010AAB), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_T1_PMU_SCOM                                         , RULL(0x27010AAB), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_T1_PMU_SCOM                                         , RULL(0x28010AAB), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_T1_PMU_SCOM                                         , RULL(0x29010AAB), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_T1_PMU_SCOM                                        , RULL(0x2A010AAB), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_T1_PMU_SCOM                                        , RULL(0x2B010AAB), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_T1_PMU_SCOM                                        , RULL(0x2C010AAB), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_T1_PMU_SCOM                                        , RULL(0x2D010AAB), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_T1_PMU_SCOM                                        , RULL(0x2E010AAB), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_T1_PMU_SCOM                                        , RULL(0x2F010AAB), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_T1_PMU_SCOM                                        , RULL(0x30010AAB), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_T1_PMU_SCOM                                        , RULL(0x31010AAB), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_T1_PMU_SCOM                                        , RULL(0x32010AAB), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_T1_PMU_SCOM                                        , RULL(0x33010AAB), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_T1_PMU_SCOM                                        , RULL(0x34010AAB), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_T1_PMU_SCOM                                        , RULL(0x35010AAB), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_T1_PMU_SCOM                                        , RULL(0x36010AAB), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_T1_PMU_SCOM                                        , RULL(0x37010AAB), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_T1_PMU_SCOM                                     , RULL(0x20010AAB), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010AAB,
+REG64( EX_10_L2_T1_PMU_SCOM                                    , RULL(0x34010AAB), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010AAB,
+REG64( EX_11_L2_T1_PMU_SCOM                                    , RULL(0x36010AAB), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010AAB,
+REG64( EX_1_L2_T1_PMU_SCOM                                     , RULL(0x22010AAB), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010AAB,
+REG64( EX_2_L2_T1_PMU_SCOM                                     , RULL(0x24010AAB), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010AAB,
+REG64( EX_3_L2_T1_PMU_SCOM                                     , RULL(0x26010AAB), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010AAB,
+REG64( EX_4_L2_T1_PMU_SCOM                                     , RULL(0x28010AAB), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010AAB,
+REG64( EX_5_L2_T1_PMU_SCOM                                     , RULL(0x2A010AAB), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010AAB,
+REG64( EX_6_L2_T1_PMU_SCOM                                     , RULL(0x2C010AAB), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010AAB,
+REG64( EX_7_L2_T1_PMU_SCOM                                     , RULL(0x2E010AAB), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010AAB,
+REG64( EX_8_L2_T1_PMU_SCOM                                     , RULL(0x30010AAB), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010AAB,
+REG64( EX_9_L2_T1_PMU_SCOM                                     , RULL(0x32010AAB), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010AAB,
+REG64( EX_L2_T1_PMU_SCOM                                       , RULL(0x20010AAB), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010AAB,
+
+REG64( C_T2_PMU_SCOM                                           , RULL(0x20010AAC), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_T2_PMU_SCOM                                         , RULL(0x20010AAC), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_T2_PMU_SCOM                                         , RULL(0x21010AAC), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_T2_PMU_SCOM                                         , RULL(0x22010AAC), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_T2_PMU_SCOM                                         , RULL(0x23010AAC), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_T2_PMU_SCOM                                         , RULL(0x24010AAC), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_T2_PMU_SCOM                                         , RULL(0x25010AAC), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_T2_PMU_SCOM                                         , RULL(0x26010AAC), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_T2_PMU_SCOM                                         , RULL(0x27010AAC), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_T2_PMU_SCOM                                         , RULL(0x28010AAC), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_T2_PMU_SCOM                                         , RULL(0x29010AAC), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_T2_PMU_SCOM                                        , RULL(0x2A010AAC), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_T2_PMU_SCOM                                        , RULL(0x2B010AAC), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_T2_PMU_SCOM                                        , RULL(0x2C010AAC), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_T2_PMU_SCOM                                        , RULL(0x2D010AAC), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_T2_PMU_SCOM                                        , RULL(0x2E010AAC), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_T2_PMU_SCOM                                        , RULL(0x2F010AAC), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_T2_PMU_SCOM                                        , RULL(0x30010AAC), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_T2_PMU_SCOM                                        , RULL(0x31010AAC), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_T2_PMU_SCOM                                        , RULL(0x32010AAC), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_T2_PMU_SCOM                                        , RULL(0x33010AAC), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_T2_PMU_SCOM                                        , RULL(0x34010AAC), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_T2_PMU_SCOM                                        , RULL(0x35010AAC), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_T2_PMU_SCOM                                        , RULL(0x36010AAC), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_T2_PMU_SCOM                                        , RULL(0x37010AAC), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_T2_PMU_SCOM                                     , RULL(0x20010AAC), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010AAC,
+REG64( EX_10_L2_T2_PMU_SCOM                                    , RULL(0x34010AAC), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010AAC,
+REG64( EX_11_L2_T2_PMU_SCOM                                    , RULL(0x36010AAC), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010AAC,
+REG64( EX_1_L2_T2_PMU_SCOM                                     , RULL(0x22010AAC), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010AAC,
+REG64( EX_2_L2_T2_PMU_SCOM                                     , RULL(0x24010AAC), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010AAC,
+REG64( EX_3_L2_T2_PMU_SCOM                                     , RULL(0x26010AAC), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010AAC,
+REG64( EX_4_L2_T2_PMU_SCOM                                     , RULL(0x28010AAC), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010AAC,
+REG64( EX_5_L2_T2_PMU_SCOM                                     , RULL(0x2A010AAC), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010AAC,
+REG64( EX_6_L2_T2_PMU_SCOM                                     , RULL(0x2C010AAC), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010AAC,
+REG64( EX_7_L2_T2_PMU_SCOM                                     , RULL(0x2E010AAC), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010AAC,
+REG64( EX_8_L2_T2_PMU_SCOM                                     , RULL(0x30010AAC), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010AAC,
+REG64( EX_9_L2_T2_PMU_SCOM                                     , RULL(0x32010AAC), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010AAC,
+REG64( EX_L2_T2_PMU_SCOM                                       , RULL(0x20010AAC), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010AAC,
+
+REG64( C_T3_PMU_SCOM                                           , RULL(0x20010AAD), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_T3_PMU_SCOM                                         , RULL(0x20010AAD), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_T3_PMU_SCOM                                         , RULL(0x21010AAD), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_T3_PMU_SCOM                                         , RULL(0x22010AAD), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_T3_PMU_SCOM                                         , RULL(0x23010AAD), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_T3_PMU_SCOM                                         , RULL(0x24010AAD), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_T3_PMU_SCOM                                         , RULL(0x25010AAD), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_T3_PMU_SCOM                                         , RULL(0x26010AAD), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_T3_PMU_SCOM                                         , RULL(0x27010AAD), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_T3_PMU_SCOM                                         , RULL(0x28010AAD), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_T3_PMU_SCOM                                         , RULL(0x29010AAD), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_T3_PMU_SCOM                                        , RULL(0x2A010AAD), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_T3_PMU_SCOM                                        , RULL(0x2B010AAD), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_T3_PMU_SCOM                                        , RULL(0x2C010AAD), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_T3_PMU_SCOM                                        , RULL(0x2D010AAD), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_T3_PMU_SCOM                                        , RULL(0x2E010AAD), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_T3_PMU_SCOM                                        , RULL(0x2F010AAD), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_T3_PMU_SCOM                                        , RULL(0x30010AAD), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_T3_PMU_SCOM                                        , RULL(0x31010AAD), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_T3_PMU_SCOM                                        , RULL(0x32010AAD), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_T3_PMU_SCOM                                        , RULL(0x33010AAD), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_T3_PMU_SCOM                                        , RULL(0x34010AAD), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_T3_PMU_SCOM                                        , RULL(0x35010AAD), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_T3_PMU_SCOM                                        , RULL(0x36010AAD), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_T3_PMU_SCOM                                        , RULL(0x37010AAD), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_T3_PMU_SCOM                                     , RULL(0x20010AAD), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 21010AAD,
+REG64( EX_10_L2_T3_PMU_SCOM                                    , RULL(0x34010AAD), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 35010AAD,
+REG64( EX_11_L2_T3_PMU_SCOM                                    , RULL(0x36010AAD), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 37010AAD,
+REG64( EX_1_L2_T3_PMU_SCOM                                     , RULL(0x22010AAD), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 23010AAD,
+REG64( EX_2_L2_T3_PMU_SCOM                                     , RULL(0x24010AAD), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 25010AAD,
+REG64( EX_3_L2_T3_PMU_SCOM                                     , RULL(0x26010AAD), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 27010AAD,
+REG64( EX_4_L2_T3_PMU_SCOM                                     , RULL(0x28010AAD), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 29010AAD,
+REG64( EX_5_L2_T3_PMU_SCOM                                     , RULL(0x2A010AAD), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2B010AAD,
+REG64( EX_6_L2_T3_PMU_SCOM                                     , RULL(0x2C010AAD), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2D010AAD,
+REG64( EX_7_L2_T3_PMU_SCOM                                     , RULL(0x2E010AAD), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2F010AAD,
+REG64( EX_8_L2_T3_PMU_SCOM                                     , RULL(0x30010AAD), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 31010AAD,
+REG64( EX_9_L2_T3_PMU_SCOM                                     , RULL(0x32010AAD), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 33010AAD,
+REG64( EX_L2_T3_PMU_SCOM                                       , RULL(0x20010AAD), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 21010AAD,
+
+REG64( C_TFAC_HOLD_OUT                                         , RULL(0x20010AB7), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_TFAC_HOLD_OUT                                       , RULL(0x20010AB7), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_TFAC_HOLD_OUT                                       , RULL(0x21010AB7), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_TFAC_HOLD_OUT                                       , RULL(0x22010AB7), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_TFAC_HOLD_OUT                                       , RULL(0x23010AB7), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_TFAC_HOLD_OUT                                       , RULL(0x24010AB7), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_TFAC_HOLD_OUT                                       , RULL(0x25010AB7), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_TFAC_HOLD_OUT                                       , RULL(0x26010AB7), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_TFAC_HOLD_OUT                                       , RULL(0x27010AB7), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_TFAC_HOLD_OUT                                       , RULL(0x28010AB7), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_TFAC_HOLD_OUT                                       , RULL(0x29010AB7), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_TFAC_HOLD_OUT                                      , RULL(0x2A010AB7), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_TFAC_HOLD_OUT                                      , RULL(0x2B010AB7), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_TFAC_HOLD_OUT                                      , RULL(0x2C010AB7), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_TFAC_HOLD_OUT                                      , RULL(0x2D010AB7), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_TFAC_HOLD_OUT                                      , RULL(0x2E010AB7), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_TFAC_HOLD_OUT                                      , RULL(0x2F010AB7), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_TFAC_HOLD_OUT                                      , RULL(0x30010AB7), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_TFAC_HOLD_OUT                                      , RULL(0x31010AB7), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_TFAC_HOLD_OUT                                      , RULL(0x32010AB7), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_TFAC_HOLD_OUT                                      , RULL(0x33010AB7), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_TFAC_HOLD_OUT                                      , RULL(0x34010AB7), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_TFAC_HOLD_OUT                                      , RULL(0x35010AB7), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_TFAC_HOLD_OUT                                      , RULL(0x36010AB7), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_TFAC_HOLD_OUT                                      , RULL(0x37010AB7), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_0_L2_TFAC_HOLD_OUT                                   , RULL(0x21010AB7), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 20010AB7,
+REG64( EX_10_L2_TFAC_HOLD_OUT                                  , RULL(0x35010AB7), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 34010AB7,
+REG64( EX_11_L2_TFAC_HOLD_OUT                                  , RULL(0x37010AB7), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 36010AB7,
+REG64( EX_1_L2_TFAC_HOLD_OUT                                   , RULL(0x23010AB7), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 22010AB7,
+REG64( EX_2_L2_TFAC_HOLD_OUT                                   , RULL(0x25010AB7), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 24010AB7,
+REG64( EX_3_L2_TFAC_HOLD_OUT                                   , RULL(0x27010AB7), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 26010AB7,
+REG64( EX_4_L2_TFAC_HOLD_OUT                                   , RULL(0x29010AB7), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 28010AB7,
+REG64( EX_5_L2_TFAC_HOLD_OUT                                   , RULL(0x2B010AB7), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2A010AB7,
+REG64( EX_6_L2_TFAC_HOLD_OUT                                   , RULL(0x2D010AB7), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2C010AB7,
+REG64( EX_7_L2_TFAC_HOLD_OUT                                   , RULL(0x2F010AB7), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2E010AB7,
+REG64( EX_8_L2_TFAC_HOLD_OUT                                   , RULL(0x31010AB7), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 30010AB7,
+REG64( EX_9_L2_TFAC_HOLD_OUT                                   , RULL(0x33010AB7), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 32010AB7,
+REG64( EX_L2_TFAC_HOLD_OUT                                     , RULL(0x21010AB7), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 20010AB7,
+
+REG64( C_THERM_MODE_REG                                        , RULL(0x2005000F), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_THERM_MODE_REG                                      , RULL(0x2005000F), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_THERM_MODE_REG                                      , RULL(0x2105000F), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_THERM_MODE_REG                                      , RULL(0x2205000F), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_THERM_MODE_REG                                      , RULL(0x2305000F), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_THERM_MODE_REG                                      , RULL(0x2405000F), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_THERM_MODE_REG                                      , RULL(0x2505000F), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_THERM_MODE_REG                                      , RULL(0x2605000F), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_THERM_MODE_REG                                      , RULL(0x2705000F), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_THERM_MODE_REG                                      , RULL(0x2805000F), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_THERM_MODE_REG                                      , RULL(0x2905000F), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_THERM_MODE_REG                                     , RULL(0x2A05000F), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_THERM_MODE_REG                                     , RULL(0x2B05000F), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_THERM_MODE_REG                                     , RULL(0x2C05000F), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_THERM_MODE_REG                                     , RULL(0x2D05000F), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_THERM_MODE_REG                                     , RULL(0x2E05000F), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_THERM_MODE_REG                                     , RULL(0x2F05000F), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_THERM_MODE_REG                                     , RULL(0x3005000F), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_THERM_MODE_REG                                     , RULL(0x3105000F), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_THERM_MODE_REG                                     , RULL(0x3205000F), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_THERM_MODE_REG                                     , RULL(0x3305000F), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_THERM_MODE_REG                                     , RULL(0x3405000F), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_THERM_MODE_REG                                     , RULL(0x3505000F), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_THERM_MODE_REG                                     , RULL(0x3605000F), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_THERM_MODE_REG                                     , RULL(0x3705000F), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_THERM_MODE_REG                                       , RULL(0x1005000F), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_THERM_MODE_REG                                     , RULL(0x1005000F), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_THERM_MODE_REG                                     , RULL(0x1105000F), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_THERM_MODE_REG                                     , RULL(0x1205000F), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_THERM_MODE_REG                                     , RULL(0x1305000F), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_THERM_MODE_REG                                     , RULL(0x1405000F), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_THERM_MODE_REG                                     , RULL(0x1505000F), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_THERM_MODE_REG                                       , RULL(0x2005000F), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 2105000F,
+REG64( EX_0_THERM_MODE_REG                                     , RULL(0x2005000F), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 2105000F,
+REG64( EX_1_THERM_MODE_REG                                     , RULL(0x2205000F), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 2305000F,
+REG64( EX_2_THERM_MODE_REG                                     , RULL(0x2405000F), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 2505000F,
+REG64( EX_3_THERM_MODE_REG                                     , RULL(0x2605000F), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 2705000F,
+REG64( EX_4_THERM_MODE_REG                                     , RULL(0x2805000F), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 2905000F,
+REG64( EX_5_THERM_MODE_REG                                     , RULL(0x2A05000F), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B05000F,
+REG64( EX_6_THERM_MODE_REG                                     , RULL(0x2C05000F), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D05000F,
+REG64( EX_7_THERM_MODE_REG                                     , RULL(0x2E05000F), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F05000F,
+REG64( EX_8_THERM_MODE_REG                                     , RULL(0x3005000F), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 3105000F,
+REG64( EX_9_THERM_MODE_REG                                     , RULL(0x3205000F), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 3305000F,
+REG64( EX_10_THERM_MODE_REG                                    , RULL(0x3405000F), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 3505000F,
+REG64( EX_11_THERM_MODE_REG                                    , RULL(0x3605000F), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 3705000F,
+
+REG64( C_THRCTL_HOLD_OUT                                       , RULL(0x20010A03), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_THRCTL_HOLD_OUT                                     , RULL(0x20010A03), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_THRCTL_HOLD_OUT                                     , RULL(0x21010A03), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_THRCTL_HOLD_OUT                                     , RULL(0x22010A03), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_THRCTL_HOLD_OUT                                     , RULL(0x23010A03), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_THRCTL_HOLD_OUT                                     , RULL(0x24010A03), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_THRCTL_HOLD_OUT                                     , RULL(0x25010A03), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_THRCTL_HOLD_OUT                                     , RULL(0x26010A03), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_THRCTL_HOLD_OUT                                     , RULL(0x27010A03), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_THRCTL_HOLD_OUT                                     , RULL(0x28010A03), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_THRCTL_HOLD_OUT                                     , RULL(0x29010A03), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_THRCTL_HOLD_OUT                                    , RULL(0x2A010A03), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_THRCTL_HOLD_OUT                                    , RULL(0x2B010A03), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_THRCTL_HOLD_OUT                                    , RULL(0x2C010A03), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_THRCTL_HOLD_OUT                                    , RULL(0x2D010A03), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_THRCTL_HOLD_OUT                                    , RULL(0x2E010A03), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_THRCTL_HOLD_OUT                                    , RULL(0x2F010A03), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_THRCTL_HOLD_OUT                                    , RULL(0x30010A03), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_THRCTL_HOLD_OUT                                    , RULL(0x31010A03), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_THRCTL_HOLD_OUT                                    , RULL(0x32010A03), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_THRCTL_HOLD_OUT                                    , RULL(0x33010A03), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_THRCTL_HOLD_OUT                                    , RULL(0x34010A03), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_THRCTL_HOLD_OUT                                    , RULL(0x35010A03), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_THRCTL_HOLD_OUT                                    , RULL(0x36010A03), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_THRCTL_HOLD_OUT                                    , RULL(0x37010A03), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_0_L2_THRCTL_HOLD_OUT                                 , RULL(0x20010A03), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010A03,
+REG64( EX_10_L2_THRCTL_HOLD_OUT                                , RULL(0x34010A03), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 35010A03,
+REG64( EX_11_L2_THRCTL_HOLD_OUT                                , RULL(0x36010A03), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 37010A03,
+REG64( EX_1_L2_THRCTL_HOLD_OUT                                 , RULL(0x22010A03), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 23010A03,
+REG64( EX_2_L2_THRCTL_HOLD_OUT                                 , RULL(0x24010A03), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 25010A03,
+REG64( EX_3_L2_THRCTL_HOLD_OUT                                 , RULL(0x26010A03), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 27010A03,
+REG64( EX_4_L2_THRCTL_HOLD_OUT                                 , RULL(0x28010A03), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 29010A03,
+REG64( EX_5_L2_THRCTL_HOLD_OUT                                 , RULL(0x2A010A03), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B010A03,
+REG64( EX_6_L2_THRCTL_HOLD_OUT                                 , RULL(0x2C010A03), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D010A03,
+REG64( EX_7_L2_THRCTL_HOLD_OUT                                 , RULL(0x2E010A03), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F010A03,
+REG64( EX_8_L2_THRCTL_HOLD_OUT                                 , RULL(0x30010A03), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 31010A03,
+REG64( EX_9_L2_THRCTL_HOLD_OUT                                 , RULL(0x32010A03), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 33010A03,
+REG64( EX_L2_THRCTL_HOLD_OUT                                   , RULL(0x20010A03), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 21010A03,
+
+REG64( C_THREAD_INFO                                           , RULL(0x20010A9B), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_THREAD_INFO                                         , RULL(0x20010A9B), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_THREAD_INFO                                         , RULL(0x21010A9B), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_THREAD_INFO                                         , RULL(0x22010A9B), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_THREAD_INFO                                         , RULL(0x23010A9B), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_THREAD_INFO                                         , RULL(0x24010A9B), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_THREAD_INFO                                         , RULL(0x25010A9B), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_THREAD_INFO                                         , RULL(0x26010A9B), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_THREAD_INFO                                         , RULL(0x27010A9B), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_THREAD_INFO                                         , RULL(0x28010A9B), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_THREAD_INFO                                         , RULL(0x29010A9B), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_THREAD_INFO                                        , RULL(0x2A010A9B), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_THREAD_INFO                                        , RULL(0x2B010A9B), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_THREAD_INFO                                        , RULL(0x2C010A9B), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_THREAD_INFO                                        , RULL(0x2D010A9B), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_THREAD_INFO                                        , RULL(0x2E010A9B), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_THREAD_INFO                                        , RULL(0x2F010A9B), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_THREAD_INFO                                        , RULL(0x30010A9B), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_THREAD_INFO                                        , RULL(0x31010A9B), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_THREAD_INFO                                        , RULL(0x32010A9B), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_THREAD_INFO                                        , RULL(0x33010A9B), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_THREAD_INFO                                        , RULL(0x34010A9B), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_THREAD_INFO                                        , RULL(0x35010A9B), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_THREAD_INFO                                        , RULL(0x36010A9B), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_THREAD_INFO                                        , RULL(0x37010A9B), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EX_0_L2_THREAD_INFO                                     , RULL(0x21010A9B), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 20010A9B,
+REG64( EX_10_L2_THREAD_INFO                                    , RULL(0x35010A9B), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 34010A9B,
+REG64( EX_11_L2_THREAD_INFO                                    , RULL(0x37010A9B), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM      ); //DUPS: 36010A9B,
+REG64( EX_1_L2_THREAD_INFO                                     , RULL(0x23010A9B), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 22010A9B,
+REG64( EX_2_L2_THREAD_INFO                                     , RULL(0x25010A9B), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 24010A9B,
+REG64( EX_3_L2_THREAD_INFO                                     , RULL(0x27010A9B), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 26010A9B,
+REG64( EX_4_L2_THREAD_INFO                                     , RULL(0x29010A9B), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 28010A9B,
+REG64( EX_5_L2_THREAD_INFO                                     , RULL(0x2B010A9B), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2A010A9B,
+REG64( EX_6_L2_THREAD_INFO                                     , RULL(0x2D010A9B), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2C010A9B,
+REG64( EX_7_L2_THREAD_INFO                                     , RULL(0x2F010A9B), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 2E010A9B,
+REG64( EX_8_L2_THREAD_INFO                                     , RULL(0x31010A9B), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 30010A9B,
+REG64( EX_9_L2_THREAD_INFO                                     , RULL(0x33010A9B), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM      ); //DUPS: 32010A9B,
+REG64( EX_L2_THREAD_INFO                                       , RULL(0x21010A9B), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM      ); //DUPS: 20010A9B,
+
+REG64( C_THROTTLE_CONTROL                                      , RULL(0x20010A9E), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_THROTTLE_CONTROL                                    , RULL(0x20010A9E), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_THROTTLE_CONTROL                                    , RULL(0x21010A9E), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_THROTTLE_CONTROL                                    , RULL(0x22010A9E), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_THROTTLE_CONTROL                                    , RULL(0x23010A9E), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_THROTTLE_CONTROL                                    , RULL(0x24010A9E), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_THROTTLE_CONTROL                                    , RULL(0x25010A9E), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_THROTTLE_CONTROL                                    , RULL(0x26010A9E), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_THROTTLE_CONTROL                                    , RULL(0x27010A9E), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_THROTTLE_CONTROL                                    , RULL(0x28010A9E), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_THROTTLE_CONTROL                                    , RULL(0x29010A9E), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_THROTTLE_CONTROL                                   , RULL(0x2A010A9E), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_THROTTLE_CONTROL                                   , RULL(0x2B010A9E), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_THROTTLE_CONTROL                                   , RULL(0x2C010A9E), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_THROTTLE_CONTROL                                   , RULL(0x2D010A9E), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_THROTTLE_CONTROL                                   , RULL(0x2E010A9E), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_THROTTLE_CONTROL                                   , RULL(0x2F010A9E), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_THROTTLE_CONTROL                                   , RULL(0x30010A9E), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_THROTTLE_CONTROL                                   , RULL(0x31010A9E), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_THROTTLE_CONTROL                                   , RULL(0x32010A9E), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_THROTTLE_CONTROL                                   , RULL(0x33010A9E), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_THROTTLE_CONTROL                                   , RULL(0x34010A9E), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_THROTTLE_CONTROL                                   , RULL(0x35010A9E), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_THROTTLE_CONTROL                                   , RULL(0x36010A9E), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_THROTTLE_CONTROL                                   , RULL(0x37010A9E), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_THROTTLE_CONTROL                                     , RULL(0x21010A9E), SH_UNT_EX       ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A9E,
+REG64( EX_0_THROTTLE_CONTROL                                   , RULL(0x21010A9E), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010A9E,
+REG64( EX_1_THROTTLE_CONTROL                                   , RULL(0x23010A9E), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 22010A9E,
+REG64( EX_2_THROTTLE_CONTROL                                   , RULL(0x25010A9E), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 24010A9E,
+REG64( EX_3_THROTTLE_CONTROL                                   , RULL(0x27010A9E), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 26010A9E,
+REG64( EX_4_THROTTLE_CONTROL                                   , RULL(0x29010A9E), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 28010A9E,
+REG64( EX_5_THROTTLE_CONTROL                                   , RULL(0x2B010A9E), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2A010A9E,
+REG64( EX_6_THROTTLE_CONTROL                                   , RULL(0x2D010A9E), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2C010A9E,
+REG64( EX_7_THROTTLE_CONTROL                                   , RULL(0x2F010A9E), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2E010A9E,
+REG64( EX_8_THROTTLE_CONTROL                                   , RULL(0x31010A9E), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 30010A9E,
+REG64( EX_9_THROTTLE_CONTROL                                   , RULL(0x33010A9E), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RW   ); //DUPS: 32010A9E,
+REG64( EX_10_THROTTLE_CONTROL                                  , RULL(0x35010A9E), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 34010A9E,
+REG64( EX_11_THROTTLE_CONTROL                                  , RULL(0x37010A9E), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 36010A9E,
+
+REG64( C_TIMEOUT_REG                                           , RULL(0x200F0010), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_TIMEOUT_REG                                         , RULL(0x200F0010), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_TIMEOUT_REG                                         , RULL(0x210F0010), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_TIMEOUT_REG                                         , RULL(0x220F0010), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_TIMEOUT_REG                                         , RULL(0x230F0010), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_TIMEOUT_REG                                         , RULL(0x240F0010), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_TIMEOUT_REG                                         , RULL(0x250F0010), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_TIMEOUT_REG                                         , RULL(0x260F0010), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_TIMEOUT_REG                                         , RULL(0x270F0010), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_TIMEOUT_REG                                         , RULL(0x280F0010), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_TIMEOUT_REG                                         , RULL(0x290F0010), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_TIMEOUT_REG                                        , RULL(0x2A0F0010), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_TIMEOUT_REG                                        , RULL(0x2B0F0010), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_TIMEOUT_REG                                        , RULL(0x2C0F0010), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_TIMEOUT_REG                                        , RULL(0x2D0F0010), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_TIMEOUT_REG                                        , RULL(0x2E0F0010), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_TIMEOUT_REG                                        , RULL(0x2F0F0010), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_TIMEOUT_REG                                        , RULL(0x300F0010), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_TIMEOUT_REG                                        , RULL(0x310F0010), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_TIMEOUT_REG                                        , RULL(0x320F0010), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_TIMEOUT_REG                                        , RULL(0x330F0010), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_TIMEOUT_REG                                        , RULL(0x340F0010), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_TIMEOUT_REG                                        , RULL(0x350F0010), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_TIMEOUT_REG                                        , RULL(0x360F0010), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_TIMEOUT_REG                                        , RULL(0x370F0010), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_TIMEOUT_REG                                          , RULL(0x100F0010), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TIMEOUT_REG                                        , RULL(0x100F0010), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TIMEOUT_REG                                        , RULL(0x110F0010), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TIMEOUT_REG                                        , RULL(0x120F0010), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TIMEOUT_REG                                        , RULL(0x130F0010), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TIMEOUT_REG                                        , RULL(0x140F0010), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TIMEOUT_REG                                        , RULL(0x150F0010), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TIMEOUT_REG                                          , RULL(0x200F0010), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F0010,
+REG64( EX_0_TIMEOUT_REG                                        , RULL(0x200F0010), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F0010,
+REG64( EX_1_TIMEOUT_REG                                        , RULL(0x230F0010), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F0010,
+REG64( EX_2_TIMEOUT_REG                                        , RULL(0x240F0010), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F0010,
+REG64( EX_3_TIMEOUT_REG                                        , RULL(0x260F0010), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F0010,
+REG64( EX_4_TIMEOUT_REG                                        , RULL(0x280F0010), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F0010,
+REG64( EX_5_TIMEOUT_REG                                        , RULL(0x2A0F0010), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F0010,
+REG64( EX_6_TIMEOUT_REG                                        , RULL(0x2C0F0010), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F0010,
+REG64( EX_7_TIMEOUT_REG                                        , RULL(0x2E0F0010), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F0010,
+REG64( EX_8_TIMEOUT_REG                                        , RULL(0x300F0010), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F0010,
+REG64( EX_9_TIMEOUT_REG                                        , RULL(0x320F0010), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F0010,
+REG64( EX_10_TIMEOUT_REG                                       , RULL(0x340F0010), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F0010,
+REG64( EX_11_TIMEOUT_REG                                       , RULL(0x360F0010), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F0010,
+
+REG64( C_TIMESTAMP_COUNTER_READ                                , RULL(0x2005001C), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_TIMESTAMP_COUNTER_READ                              , RULL(0x2005001C), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_TIMESTAMP_COUNTER_READ                              , RULL(0x2105001C), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_TIMESTAMP_COUNTER_READ                              , RULL(0x2205001C), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_TIMESTAMP_COUNTER_READ                              , RULL(0x2305001C), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_TIMESTAMP_COUNTER_READ                              , RULL(0x2405001C), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_TIMESTAMP_COUNTER_READ                              , RULL(0x2505001C), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_TIMESTAMP_COUNTER_READ                              , RULL(0x2605001C), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_TIMESTAMP_COUNTER_READ                              , RULL(0x2705001C), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_TIMESTAMP_COUNTER_READ                              , RULL(0x2805001C), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_TIMESTAMP_COUNTER_READ                              , RULL(0x2905001C), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_TIMESTAMP_COUNTER_READ                             , RULL(0x2A05001C), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_TIMESTAMP_COUNTER_READ                             , RULL(0x2B05001C), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_TIMESTAMP_COUNTER_READ                             , RULL(0x2C05001C), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_TIMESTAMP_COUNTER_READ                             , RULL(0x2D05001C), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_TIMESTAMP_COUNTER_READ                             , RULL(0x2E05001C), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_TIMESTAMP_COUNTER_READ                             , RULL(0x2F05001C), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_TIMESTAMP_COUNTER_READ                             , RULL(0x3005001C), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_TIMESTAMP_COUNTER_READ                             , RULL(0x3105001C), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_TIMESTAMP_COUNTER_READ                             , RULL(0x3205001C), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_TIMESTAMP_COUNTER_READ                             , RULL(0x3305001C), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_TIMESTAMP_COUNTER_READ                             , RULL(0x3405001C), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_TIMESTAMP_COUNTER_READ                             , RULL(0x3505001C), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_TIMESTAMP_COUNTER_READ                             , RULL(0x3605001C), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_TIMESTAMP_COUNTER_READ                             , RULL(0x3705001C), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EQ_TIMESTAMP_COUNTER_READ                               , RULL(0x1005001C), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_TIMESTAMP_COUNTER_READ                             , RULL(0x1005001C), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_TIMESTAMP_COUNTER_READ                             , RULL(0x1105001C), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_TIMESTAMP_COUNTER_READ                             , RULL(0x1205001C), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_TIMESTAMP_COUNTER_READ                             , RULL(0x1305001C), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_TIMESTAMP_COUNTER_READ                             , RULL(0x1405001C), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_TIMESTAMP_COUNTER_READ                             , RULL(0x1505001C), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_TIMESTAMP_COUNTER_READ                               , RULL(0x2005001C), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2105001C,
+REG64( EX_0_TIMESTAMP_COUNTER_READ                             , RULL(0x2005001C), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2105001C,
+REG64( EX_1_TIMESTAMP_COUNTER_READ                             , RULL(0x2205001C), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2305001C,
+REG64( EX_2_TIMESTAMP_COUNTER_READ                             , RULL(0x2405001C), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2505001C,
+REG64( EX_3_TIMESTAMP_COUNTER_READ                             , RULL(0x2605001C), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2705001C,
+REG64( EX_4_TIMESTAMP_COUNTER_READ                             , RULL(0x2805001C), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2905001C,
+REG64( EX_5_TIMESTAMP_COUNTER_READ                             , RULL(0x2A05001C), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B05001C,
+REG64( EX_6_TIMESTAMP_COUNTER_READ                             , RULL(0x2C05001C), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D05001C,
+REG64( EX_7_TIMESTAMP_COUNTER_READ                             , RULL(0x2E05001C), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F05001C,
+REG64( EX_8_TIMESTAMP_COUNTER_READ                             , RULL(0x3005001C), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 3105001C,
+REG64( EX_9_TIMESTAMP_COUNTER_READ                             , RULL(0x3205001C), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 3305001C,
+REG64( EX_10_TIMESTAMP_COUNTER_READ                            , RULL(0x3405001C), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 3505001C,
+REG64( EX_11_TIMESTAMP_COUNTER_READ                            , RULL(0x3605001C), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 3705001C,
+
+REG64( C_TOD_READ                                              , RULL(0x20010AA3), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_TOD_READ                                            , RULL(0x20010AA3), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_TOD_READ                                            , RULL(0x21010AA3), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_TOD_READ                                            , RULL(0x22010AA3), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_TOD_READ                                            , RULL(0x23010AA3), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_TOD_READ                                            , RULL(0x24010AA3), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_TOD_READ                                            , RULL(0x25010AA3), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_TOD_READ                                            , RULL(0x26010AA3), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_TOD_READ                                            , RULL(0x27010AA3), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_TOD_READ                                            , RULL(0x28010AA3), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_TOD_READ                                            , RULL(0x29010AA3), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_TOD_READ                                           , RULL(0x2A010AA3), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_TOD_READ                                           , RULL(0x2B010AA3), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_TOD_READ                                           , RULL(0x2C010AA3), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_TOD_READ                                           , RULL(0x2D010AA3), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_TOD_READ                                           , RULL(0x2E010AA3), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_TOD_READ                                           , RULL(0x2F010AA3), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_TOD_READ                                           , RULL(0x30010AA3), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_TOD_READ                                           , RULL(0x31010AA3), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_TOD_READ                                           , RULL(0x32010AA3), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_TOD_READ                                           , RULL(0x33010AA3), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_TOD_READ                                           , RULL(0x34010AA3), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_TOD_READ                                           , RULL(0x35010AA3), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_TOD_READ                                           , RULL(0x36010AA3), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_TOD_READ                                           , RULL(0x37010AA3), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EX_0_L2_TOD_READ                                        , RULL(0x21010AA3), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 20010AA3,
+REG64( EX_10_L2_TOD_READ                                       , RULL(0x35010AA3), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 34010AA3,
+REG64( EX_11_L2_TOD_READ                                       , RULL(0x37010AA3), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RO   ); //DUPS: 36010AA3,
+REG64( EX_1_L2_TOD_READ                                        , RULL(0x23010AA3), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 22010AA3,
+REG64( EX_2_L2_TOD_READ                                        , RULL(0x25010AA3), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 24010AA3,
+REG64( EX_3_L2_TOD_READ                                        , RULL(0x27010AA3), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 26010AA3,
+REG64( EX_4_L2_TOD_READ                                        , RULL(0x29010AA3), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 28010AA3,
+REG64( EX_5_L2_TOD_READ                                        , RULL(0x2B010AA3), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2A010AA3,
+REG64( EX_6_L2_TOD_READ                                        , RULL(0x2D010AA3), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2C010AA3,
+REG64( EX_7_L2_TOD_READ                                        , RULL(0x2F010AA3), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2E010AA3,
+REG64( EX_8_L2_TOD_READ                                        , RULL(0x31010AA3), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 30010AA3,
+REG64( EX_9_L2_TOD_READ                                        , RULL(0x33010AA3), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RO   ); //DUPS: 32010AA3,
+REG64( EX_L2_TOD_READ                                          , RULL(0x21010AA3), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 20010AA3,
+
+REG64( C_TOD_STEP_CHECK                                        , RULL(0x20010AA4), SH_UNT_C        , SH_ACS_SCOM_RW   );
+REG64( C_0_TOD_STEP_CHECK                                      , RULL(0x20010AA4), SH_UNT_C_0      , SH_ACS_SCOM_RW   );
+REG64( C_1_TOD_STEP_CHECK                                      , RULL(0x21010AA4), SH_UNT_C_1      , SH_ACS_SCOM_RW   );
+REG64( C_2_TOD_STEP_CHECK                                      , RULL(0x22010AA4), SH_UNT_C_2      , SH_ACS_SCOM_RW   );
+REG64( C_3_TOD_STEP_CHECK                                      , RULL(0x23010AA4), SH_UNT_C_3      , SH_ACS_SCOM_RW   );
+REG64( C_4_TOD_STEP_CHECK                                      , RULL(0x24010AA4), SH_UNT_C_4      , SH_ACS_SCOM_RW   );
+REG64( C_5_TOD_STEP_CHECK                                      , RULL(0x25010AA4), SH_UNT_C_5      , SH_ACS_SCOM_RW   );
+REG64( C_6_TOD_STEP_CHECK                                      , RULL(0x26010AA4), SH_UNT_C_6      , SH_ACS_SCOM_RW   );
+REG64( C_7_TOD_STEP_CHECK                                      , RULL(0x27010AA4), SH_UNT_C_7      , SH_ACS_SCOM_RW   );
+REG64( C_8_TOD_STEP_CHECK                                      , RULL(0x28010AA4), SH_UNT_C_8      , SH_ACS_SCOM_RW   );
+REG64( C_9_TOD_STEP_CHECK                                      , RULL(0x29010AA4), SH_UNT_C_9      , SH_ACS_SCOM_RW   );
+REG64( C_10_TOD_STEP_CHECK                                     , RULL(0x2A010AA4), SH_UNT_C_10     , SH_ACS_SCOM_RW   );
+REG64( C_11_TOD_STEP_CHECK                                     , RULL(0x2B010AA4), SH_UNT_C_11     , SH_ACS_SCOM_RW   );
+REG64( C_12_TOD_STEP_CHECK                                     , RULL(0x2C010AA4), SH_UNT_C_12     , SH_ACS_SCOM_RW   );
+REG64( C_13_TOD_STEP_CHECK                                     , RULL(0x2D010AA4), SH_UNT_C_13     , SH_ACS_SCOM_RW   );
+REG64( C_14_TOD_STEP_CHECK                                     , RULL(0x2E010AA4), SH_UNT_C_14     , SH_ACS_SCOM_RW   );
+REG64( C_15_TOD_STEP_CHECK                                     , RULL(0x2F010AA4), SH_UNT_C_15     , SH_ACS_SCOM_RW   );
+REG64( C_16_TOD_STEP_CHECK                                     , RULL(0x30010AA4), SH_UNT_C_16     , SH_ACS_SCOM_RW   );
+REG64( C_17_TOD_STEP_CHECK                                     , RULL(0x31010AA4), SH_UNT_C_17     , SH_ACS_SCOM_RW   );
+REG64( C_18_TOD_STEP_CHECK                                     , RULL(0x32010AA4), SH_UNT_C_18     , SH_ACS_SCOM_RW   );
+REG64( C_19_TOD_STEP_CHECK                                     , RULL(0x33010AA4), SH_UNT_C_19     , SH_ACS_SCOM_RW   );
+REG64( C_20_TOD_STEP_CHECK                                     , RULL(0x34010AA4), SH_UNT_C_20     , SH_ACS_SCOM_RW   );
+REG64( C_21_TOD_STEP_CHECK                                     , RULL(0x35010AA4), SH_UNT_C_21     , SH_ACS_SCOM_RW   );
+REG64( C_22_TOD_STEP_CHECK                                     , RULL(0x36010AA4), SH_UNT_C_22     , SH_ACS_SCOM_RW   );
+REG64( C_23_TOD_STEP_CHECK                                     , RULL(0x37010AA4), SH_UNT_C_23     , SH_ACS_SCOM_RW   );
+REG64( EX_0_L2_TOD_STEP_CHECK                                  , RULL(0x21010AA4), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010AA4,
+REG64( EX_10_L2_TOD_STEP_CHECK                                 , RULL(0x35010AA4), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 34010AA4,
+REG64( EX_11_L2_TOD_STEP_CHECK                                 , RULL(0x37010AA4), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM_RW   ); //DUPS: 36010AA4,
+REG64( EX_1_L2_TOD_STEP_CHECK                                  , RULL(0x23010AA4), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 22010AA4,
+REG64( EX_2_L2_TOD_STEP_CHECK                                  , RULL(0x25010AA4), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 24010AA4,
+REG64( EX_3_L2_TOD_STEP_CHECK                                  , RULL(0x27010AA4), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 26010AA4,
+REG64( EX_4_L2_TOD_STEP_CHECK                                  , RULL(0x29010AA4), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 28010AA4,
+REG64( EX_5_L2_TOD_STEP_CHECK                                  , RULL(0x2B010AA4), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2A010AA4,
+REG64( EX_6_L2_TOD_STEP_CHECK                                  , RULL(0x2D010AA4), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2C010AA4,
+REG64( EX_7_L2_TOD_STEP_CHECK                                  , RULL(0x2F010AA4), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 2E010AA4,
+REG64( EX_8_L2_TOD_STEP_CHECK                                  , RULL(0x31010AA4), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 30010AA4,
+REG64( EX_9_L2_TOD_STEP_CHECK                                  , RULL(0x33010AA4), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM_RW   ); //DUPS: 32010AA4,
+REG64( EX_L2_TOD_STEP_CHECK                                    , RULL(0x21010AA4), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM_RW   ); //DUPS: 20010AA4,
+
+REG64( C_TOD_SYNC000                                           , RULL(0x20010AA3), SH_UNT_C        , SH_ACS_SCOM1_WO  );
+
+REG64( C_0_TOD_SYNC000                                         , RULL(0x20010AA3), SH_UNT_C_0      , SH_ACS_SCOM1_WO  );
+REG64( C_1_TOD_SYNC000                                         , RULL(0x21010AA3), SH_UNT_C_1      , SH_ACS_SCOM1_WO  );
+REG64( C_2_TOD_SYNC000                                         , RULL(0x22010AA3), SH_UNT_C_2      , SH_ACS_SCOM1_WO  );
+REG64( C_3_TOD_SYNC000                                         , RULL(0x23010AA3), SH_UNT_C_3      , SH_ACS_SCOM1_WO  );
+REG64( C_4_TOD_SYNC000                                         , RULL(0x24010AA3), SH_UNT_C_4      , SH_ACS_SCOM1_WO  );
+REG64( C_5_TOD_SYNC000                                         , RULL(0x25010AA3), SH_UNT_C_5      , SH_ACS_SCOM1_WO  );
+REG64( C_6_TOD_SYNC000                                         , RULL(0x26010AA3), SH_UNT_C_6      , SH_ACS_SCOM1_WO  );
+REG64( C_7_TOD_SYNC000                                         , RULL(0x27010AA3), SH_UNT_C_7      , SH_ACS_SCOM1_WO  );
+REG64( C_8_TOD_SYNC000                                         , RULL(0x28010AA3), SH_UNT_C_8      , SH_ACS_SCOM1_WO  );
+REG64( C_9_TOD_SYNC000                                         , RULL(0x29010AA3), SH_UNT_C_9      , SH_ACS_SCOM1_WO  );
+REG64( C_10_TOD_SYNC000                                        , RULL(0x2A010AA3), SH_UNT_C_10     , SH_ACS_SCOM1_WO  );
+REG64( C_11_TOD_SYNC000                                        , RULL(0x2B010AA3), SH_UNT_C_11     , SH_ACS_SCOM1_WO  );
+REG64( C_12_TOD_SYNC000                                        , RULL(0x2C010AA3), SH_UNT_C_12     , SH_ACS_SCOM1_WO  );
+REG64( C_13_TOD_SYNC000                                        , RULL(0x2D010AA3), SH_UNT_C_13     , SH_ACS_SCOM1_WO  );
+REG64( C_14_TOD_SYNC000                                        , RULL(0x2E010AA3), SH_UNT_C_14     , SH_ACS_SCOM1_WO  );
+REG64( C_15_TOD_SYNC000                                        , RULL(0x2F010AA3), SH_UNT_C_15     , SH_ACS_SCOM1_WO  );
+REG64( C_16_TOD_SYNC000                                        , RULL(0x30010AA3), SH_UNT_C_16     , SH_ACS_SCOM1_WO  );
+REG64( C_17_TOD_SYNC000                                        , RULL(0x31010AA3), SH_UNT_C_17     , SH_ACS_SCOM1_WO  );
+REG64( C_18_TOD_SYNC000                                        , RULL(0x32010AA3), SH_UNT_C_18     , SH_ACS_SCOM1_WO  );
+REG64( C_19_TOD_SYNC000                                        , RULL(0x33010AA3), SH_UNT_C_19     , SH_ACS_SCOM1_WO  );
+REG64( C_20_TOD_SYNC000                                        , RULL(0x34010AA3), SH_UNT_C_20     , SH_ACS_SCOM1_WO  );
+REG64( C_21_TOD_SYNC000                                        , RULL(0x35010AA3), SH_UNT_C_21     , SH_ACS_SCOM1_WO  );
+REG64( C_22_TOD_SYNC000                                        , RULL(0x36010AA3), SH_UNT_C_22     , SH_ACS_SCOM1_WO  );
+REG64( C_23_TOD_SYNC000                                        , RULL(0x37010AA3), SH_UNT_C_23     , SH_ACS_SCOM1_WO  );
+REG64( EX_0_L2_TOD_SYNC000                                     , RULL(0x21010AA3), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM1_WO  ); //DUPS: 20010AA3,
+REG64( EX_10_L2_TOD_SYNC000                                    , RULL(0x35010AA3), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM1_WO  ); //DUPS: 34010AA3,
+REG64( EX_11_L2_TOD_SYNC000                                    , RULL(0x37010AA3), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM1_WO  ); //DUPS: 36010AA3,
+REG64( EX_1_L2_TOD_SYNC000                                     , RULL(0x23010AA3), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM1_WO  ); //DUPS: 22010AA3,
+REG64( EX_2_L2_TOD_SYNC000                                     , RULL(0x25010AA3), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM1_WO  ); //DUPS: 24010AA3,
+REG64( EX_3_L2_TOD_SYNC000                                     , RULL(0x27010AA3), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM1_WO  ); //DUPS: 26010AA3,
+REG64( EX_4_L2_TOD_SYNC000                                     , RULL(0x29010AA3), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM1_WO  ); //DUPS: 28010AA3,
+REG64( EX_5_L2_TOD_SYNC000                                     , RULL(0x2B010AA3), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM1_WO  ); //DUPS: 2A010AA3,
+REG64( EX_6_L2_TOD_SYNC000                                     , RULL(0x2D010AA3), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM1_WO  ); //DUPS: 2C010AA3,
+REG64( EX_7_L2_TOD_SYNC000                                     , RULL(0x2F010AA3), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM1_WO  ); //DUPS: 2E010AA3,
+REG64( EX_8_L2_TOD_SYNC000                                     , RULL(0x31010AA3), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM1_WO  ); //DUPS: 30010AA3,
+REG64( EX_9_L2_TOD_SYNC000                                     , RULL(0x33010AA3), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM1_WO  ); //DUPS: 32010AA3,
+REG64( EX_L2_TOD_SYNC000                                       , RULL(0x21010AA3), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM1_WO  ); //DUPS: 20010AA3,
+
+REG64( C_TOD_SYNC001                                           , RULL(0x20010AA3), SH_UNT_C        ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_0_TOD_SYNC001                                         , RULL(0x20010AA3), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_1_TOD_SYNC001                                         , RULL(0x21010AA3), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_2_TOD_SYNC001                                         , RULL(0x22010AA3), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_3_TOD_SYNC001                                         , RULL(0x23010AA3), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_4_TOD_SYNC001                                         , RULL(0x24010AA3), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_5_TOD_SYNC001                                         , RULL(0x25010AA3), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_6_TOD_SYNC001                                         , RULL(0x26010AA3), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_7_TOD_SYNC001                                         , RULL(0x27010AA3), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_8_TOD_SYNC001                                         , RULL(0x28010AA3), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_9_TOD_SYNC001                                         , RULL(0x29010AA3), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_10_TOD_SYNC001                                        , RULL(0x2A010AA3), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_11_TOD_SYNC001                                        , RULL(0x2B010AA3), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_12_TOD_SYNC001                                        , RULL(0x2C010AA3), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_13_TOD_SYNC001                                        , RULL(0x2D010AA3), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_14_TOD_SYNC001                                        , RULL(0x2E010AA3), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_15_TOD_SYNC001                                        , RULL(0x2F010AA3), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_16_TOD_SYNC001                                        , RULL(0x30010AA3), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_17_TOD_SYNC001                                        , RULL(0x31010AA3), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_18_TOD_SYNC001                                        , RULL(0x32010AA3), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_19_TOD_SYNC001                                        , RULL(0x33010AA3), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_20_TOD_SYNC001                                        , RULL(0x34010AA3), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_21_TOD_SYNC001                                        , RULL(0x35010AA3), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_22_TOD_SYNC001                                        , RULL(0x36010AA3), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_23_TOD_SYNC001                                        , RULL(0x37010AA3), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( EX_0_L2_TOD_SYNC001                                     , RULL(0x21010AA3), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+REG64( EX_10_L2_TOD_SYNC001                                    , RULL(0x35010AA3), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3,
+REG64( EX_11_L2_TOD_SYNC001                                    , RULL(0x37010AA3), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3,
+REG64( EX_1_L2_TOD_SYNC001                                     , RULL(0x23010AA3), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3,
+REG64( EX_2_L2_TOD_SYNC001                                     , RULL(0x25010AA3), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3,
+REG64( EX_3_L2_TOD_SYNC001                                     , RULL(0x27010AA3), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3,
+REG64( EX_4_L2_TOD_SYNC001                                     , RULL(0x29010AA3), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3,
+REG64( EX_5_L2_TOD_SYNC001                                     , RULL(0x2B010AA3), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3,
+REG64( EX_6_L2_TOD_SYNC001                                     , RULL(0x2D010AA3), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3,
+REG64( EX_7_L2_TOD_SYNC001                                     , RULL(0x2F010AA3), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3,
+REG64( EX_8_L2_TOD_SYNC001                                     , RULL(0x31010AA3), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3,
+REG64( EX_9_L2_TOD_SYNC001                                     , RULL(0x33010AA3), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3,
+REG64( EX_L2_TOD_SYNC001                                       , RULL(0x21010AA3), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+
+REG64( C_TOD_SYNC010                                           , RULL(0x20010AA3), SH_UNT_C        ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_0_TOD_SYNC010                                         , RULL(0x20010AA3), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_1_TOD_SYNC010                                         , RULL(0x21010AA3), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_2_TOD_SYNC010                                         , RULL(0x22010AA3), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_3_TOD_SYNC010                                         , RULL(0x23010AA3), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_4_TOD_SYNC010                                         , RULL(0x24010AA3), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_5_TOD_SYNC010                                         , RULL(0x25010AA3), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_6_TOD_SYNC010                                         , RULL(0x26010AA3), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_7_TOD_SYNC010                                         , RULL(0x27010AA3), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_8_TOD_SYNC010                                         , RULL(0x28010AA3), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_9_TOD_SYNC010                                         , RULL(0x29010AA3), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_10_TOD_SYNC010                                        , RULL(0x2A010AA3), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_11_TOD_SYNC010                                        , RULL(0x2B010AA3), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_12_TOD_SYNC010                                        , RULL(0x2C010AA3), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_13_TOD_SYNC010                                        , RULL(0x2D010AA3), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_14_TOD_SYNC010                                        , RULL(0x2E010AA3), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_15_TOD_SYNC010                                        , RULL(0x2F010AA3), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_16_TOD_SYNC010                                        , RULL(0x30010AA3), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_17_TOD_SYNC010                                        , RULL(0x31010AA3), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_18_TOD_SYNC010                                        , RULL(0x32010AA3), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_19_TOD_SYNC010                                        , RULL(0x33010AA3), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_20_TOD_SYNC010                                        , RULL(0x34010AA3), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_21_TOD_SYNC010                                        , RULL(0x35010AA3), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_22_TOD_SYNC010                                        , RULL(0x36010AA3), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_23_TOD_SYNC010                                        , RULL(0x37010AA3), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( EX_0_L2_TOD_SYNC010                                     , RULL(0x21010AA3), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+REG64( EX_10_L2_TOD_SYNC010                                    , RULL(0x35010AA3), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3,
+REG64( EX_11_L2_TOD_SYNC010                                    , RULL(0x37010AA3), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3,
+REG64( EX_1_L2_TOD_SYNC010                                     , RULL(0x23010AA3), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3,
+REG64( EX_2_L2_TOD_SYNC010                                     , RULL(0x25010AA3), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3,
+REG64( EX_3_L2_TOD_SYNC010                                     , RULL(0x27010AA3), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3,
+REG64( EX_4_L2_TOD_SYNC010                                     , RULL(0x29010AA3), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3,
+REG64( EX_5_L2_TOD_SYNC010                                     , RULL(0x2B010AA3), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3,
+REG64( EX_6_L2_TOD_SYNC010                                     , RULL(0x2D010AA3), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3,
+REG64( EX_7_L2_TOD_SYNC010                                     , RULL(0x2F010AA3), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3,
+REG64( EX_8_L2_TOD_SYNC010                                     , RULL(0x31010AA3), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3,
+REG64( EX_9_L2_TOD_SYNC010                                     , RULL(0x33010AA3), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3,
+REG64( EX_L2_TOD_SYNC010                                       , RULL(0x21010AA3), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+
+REG64( C_TOD_SYNC011                                           , RULL(0x20010AA3), SH_UNT_C        ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_0_TOD_SYNC011                                         , RULL(0x20010AA3), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_1_TOD_SYNC011                                         , RULL(0x21010AA3), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_2_TOD_SYNC011                                         , RULL(0x22010AA3), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_3_TOD_SYNC011                                         , RULL(0x23010AA3), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_4_TOD_SYNC011                                         , RULL(0x24010AA3), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_5_TOD_SYNC011                                         , RULL(0x25010AA3), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_6_TOD_SYNC011                                         , RULL(0x26010AA3), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_7_TOD_SYNC011                                         , RULL(0x27010AA3), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_8_TOD_SYNC011                                         , RULL(0x28010AA3), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_9_TOD_SYNC011                                         , RULL(0x29010AA3), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_10_TOD_SYNC011                                        , RULL(0x2A010AA3), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_11_TOD_SYNC011                                        , RULL(0x2B010AA3), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_12_TOD_SYNC011                                        , RULL(0x2C010AA3), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_13_TOD_SYNC011                                        , RULL(0x2D010AA3), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_14_TOD_SYNC011                                        , RULL(0x2E010AA3), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_15_TOD_SYNC011                                        , RULL(0x2F010AA3), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_16_TOD_SYNC011                                        , RULL(0x30010AA3), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_17_TOD_SYNC011                                        , RULL(0x31010AA3), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_18_TOD_SYNC011                                        , RULL(0x32010AA3), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_19_TOD_SYNC011                                        , RULL(0x33010AA3), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_20_TOD_SYNC011                                        , RULL(0x34010AA3), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_21_TOD_SYNC011                                        , RULL(0x35010AA3), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_22_TOD_SYNC011                                        , RULL(0x36010AA3), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_23_TOD_SYNC011                                        , RULL(0x37010AA3), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( EX_0_L2_TOD_SYNC011                                     , RULL(0x21010AA3), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+REG64( EX_10_L2_TOD_SYNC011                                    , RULL(0x35010AA3), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3,
+REG64( EX_11_L2_TOD_SYNC011                                    , RULL(0x37010AA3), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3,
+REG64( EX_1_L2_TOD_SYNC011                                     , RULL(0x23010AA3), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3,
+REG64( EX_2_L2_TOD_SYNC011                                     , RULL(0x25010AA3), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3,
+REG64( EX_3_L2_TOD_SYNC011                                     , RULL(0x27010AA3), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3,
+REG64( EX_4_L2_TOD_SYNC011                                     , RULL(0x29010AA3), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3,
+REG64( EX_5_L2_TOD_SYNC011                                     , RULL(0x2B010AA3), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3,
+REG64( EX_6_L2_TOD_SYNC011                                     , RULL(0x2D010AA3), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3,
+REG64( EX_7_L2_TOD_SYNC011                                     , RULL(0x2F010AA3), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3,
+REG64( EX_8_L2_TOD_SYNC011                                     , RULL(0x31010AA3), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3,
+REG64( EX_9_L2_TOD_SYNC011                                     , RULL(0x33010AA3), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3,
+REG64( EX_L2_TOD_SYNC011                                       , RULL(0x21010AA3), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+
+REG64( C_TOD_SYNC100                                           , RULL(0x20010AA3), SH_UNT_C        ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_0_TOD_SYNC100                                         , RULL(0x20010AA3), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_1_TOD_SYNC100                                         , RULL(0x21010AA3), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_2_TOD_SYNC100                                         , RULL(0x22010AA3), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_3_TOD_SYNC100                                         , RULL(0x23010AA3), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_4_TOD_SYNC100                                         , RULL(0x24010AA3), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_5_TOD_SYNC100                                         , RULL(0x25010AA3), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_6_TOD_SYNC100                                         , RULL(0x26010AA3), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_7_TOD_SYNC100                                         , RULL(0x27010AA3), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_8_TOD_SYNC100                                         , RULL(0x28010AA3), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_9_TOD_SYNC100                                         , RULL(0x29010AA3), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_10_TOD_SYNC100                                        , RULL(0x2A010AA3), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_11_TOD_SYNC100                                        , RULL(0x2B010AA3), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_12_TOD_SYNC100                                        , RULL(0x2C010AA3), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_13_TOD_SYNC100                                        , RULL(0x2D010AA3), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_14_TOD_SYNC100                                        , RULL(0x2E010AA3), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_15_TOD_SYNC100                                        , RULL(0x2F010AA3), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_16_TOD_SYNC100                                        , RULL(0x30010AA3), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_17_TOD_SYNC100                                        , RULL(0x31010AA3), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_18_TOD_SYNC100                                        , RULL(0x32010AA3), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_19_TOD_SYNC100                                        , RULL(0x33010AA3), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_20_TOD_SYNC100                                        , RULL(0x34010AA3), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_21_TOD_SYNC100                                        , RULL(0x35010AA3), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_22_TOD_SYNC100                                        , RULL(0x36010AA3), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_23_TOD_SYNC100                                        , RULL(0x37010AA3), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( EX_0_L2_TOD_SYNC100                                     , RULL(0x21010AA3), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+REG64( EX_10_L2_TOD_SYNC100                                    , RULL(0x35010AA3), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3,
+REG64( EX_11_L2_TOD_SYNC100                                    , RULL(0x37010AA3), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3,
+REG64( EX_1_L2_TOD_SYNC100                                     , RULL(0x23010AA3), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3,
+REG64( EX_2_L2_TOD_SYNC100                                     , RULL(0x25010AA3), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3,
+REG64( EX_3_L2_TOD_SYNC100                                     , RULL(0x27010AA3), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3,
+REG64( EX_4_L2_TOD_SYNC100                                     , RULL(0x29010AA3), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3,
+REG64( EX_5_L2_TOD_SYNC100                                     , RULL(0x2B010AA3), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3,
+REG64( EX_6_L2_TOD_SYNC100                                     , RULL(0x2D010AA3), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3,
+REG64( EX_7_L2_TOD_SYNC100                                     , RULL(0x2F010AA3), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3,
+REG64( EX_8_L2_TOD_SYNC100                                     , RULL(0x31010AA3), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3,
+REG64( EX_9_L2_TOD_SYNC100                                     , RULL(0x33010AA3), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3,
+REG64( EX_L2_TOD_SYNC100                                       , RULL(0x21010AA3), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+
+REG64( C_TOD_SYNC101                                           , RULL(0x20010AA3), SH_UNT_C        ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_0_TOD_SYNC101                                         , RULL(0x20010AA3), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_1_TOD_SYNC101                                         , RULL(0x21010AA3), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_2_TOD_SYNC101                                         , RULL(0x22010AA3), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_3_TOD_SYNC101                                         , RULL(0x23010AA3), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_4_TOD_SYNC101                                         , RULL(0x24010AA3), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_5_TOD_SYNC101                                         , RULL(0x25010AA3), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_6_TOD_SYNC101                                         , RULL(0x26010AA3), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_7_TOD_SYNC101                                         , RULL(0x27010AA3), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_8_TOD_SYNC101                                         , RULL(0x28010AA3), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_9_TOD_SYNC101                                         , RULL(0x29010AA3), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_10_TOD_SYNC101                                        , RULL(0x2A010AA3), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_11_TOD_SYNC101                                        , RULL(0x2B010AA3), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_12_TOD_SYNC101                                        , RULL(0x2C010AA3), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_13_TOD_SYNC101                                        , RULL(0x2D010AA3), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_14_TOD_SYNC101                                        , RULL(0x2E010AA3), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_15_TOD_SYNC101                                        , RULL(0x2F010AA3), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_16_TOD_SYNC101                                        , RULL(0x30010AA3), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_17_TOD_SYNC101                                        , RULL(0x31010AA3), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_18_TOD_SYNC101                                        , RULL(0x32010AA3), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_19_TOD_SYNC101                                        , RULL(0x33010AA3), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_20_TOD_SYNC101                                        , RULL(0x34010AA3), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_21_TOD_SYNC101                                        , RULL(0x35010AA3), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_22_TOD_SYNC101                                        , RULL(0x36010AA3), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_23_TOD_SYNC101                                        , RULL(0x37010AA3), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( EX_0_L2_TOD_SYNC101                                     , RULL(0x21010AA3), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+REG64( EX_10_L2_TOD_SYNC101                                    , RULL(0x35010AA3), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3,
+REG64( EX_11_L2_TOD_SYNC101                                    , RULL(0x37010AA3), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3,
+REG64( EX_1_L2_TOD_SYNC101                                     , RULL(0x23010AA3), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3,
+REG64( EX_2_L2_TOD_SYNC101                                     , RULL(0x25010AA3), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3,
+REG64( EX_3_L2_TOD_SYNC101                                     , RULL(0x27010AA3), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3,
+REG64( EX_4_L2_TOD_SYNC101                                     , RULL(0x29010AA3), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3,
+REG64( EX_5_L2_TOD_SYNC101                                     , RULL(0x2B010AA3), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3,
+REG64( EX_6_L2_TOD_SYNC101                                     , RULL(0x2D010AA3), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3,
+REG64( EX_7_L2_TOD_SYNC101                                     , RULL(0x2F010AA3), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3,
+REG64( EX_8_L2_TOD_SYNC101                                     , RULL(0x31010AA3), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3,
+REG64( EX_9_L2_TOD_SYNC101                                     , RULL(0x33010AA3), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3,
+REG64( EX_L2_TOD_SYNC101                                       , RULL(0x21010AA3), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+
+REG64( C_TOD_SYNC110                                           , RULL(0x20010AA3), SH_UNT_C        ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_0_TOD_SYNC110                                         , RULL(0x20010AA3), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_1_TOD_SYNC110                                         , RULL(0x21010AA3), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_2_TOD_SYNC110                                         , RULL(0x22010AA3), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_3_TOD_SYNC110                                         , RULL(0x23010AA3), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_4_TOD_SYNC110                                         , RULL(0x24010AA3), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_5_TOD_SYNC110                                         , RULL(0x25010AA3), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_6_TOD_SYNC110                                         , RULL(0x26010AA3), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_7_TOD_SYNC110                                         , RULL(0x27010AA3), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_8_TOD_SYNC110                                         , RULL(0x28010AA3), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_9_TOD_SYNC110                                         , RULL(0x29010AA3), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_10_TOD_SYNC110                                        , RULL(0x2A010AA3), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_11_TOD_SYNC110                                        , RULL(0x2B010AA3), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_12_TOD_SYNC110                                        , RULL(0x2C010AA3), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_13_TOD_SYNC110                                        , RULL(0x2D010AA3), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_14_TOD_SYNC110                                        , RULL(0x2E010AA3), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_15_TOD_SYNC110                                        , RULL(0x2F010AA3), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_16_TOD_SYNC110                                        , RULL(0x30010AA3), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_17_TOD_SYNC110                                        , RULL(0x31010AA3), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_18_TOD_SYNC110                                        , RULL(0x32010AA3), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_19_TOD_SYNC110                                        , RULL(0x33010AA3), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_20_TOD_SYNC110                                        , RULL(0x34010AA3), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_21_TOD_SYNC110                                        , RULL(0x35010AA3), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_22_TOD_SYNC110                                        , RULL(0x36010AA3), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_23_TOD_SYNC110                                        , RULL(0x37010AA3), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( EX_0_L2_TOD_SYNC110                                     , RULL(0x21010AA3), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+REG64( EX_10_L2_TOD_SYNC110                                    , RULL(0x35010AA3), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3,
+REG64( EX_11_L2_TOD_SYNC110                                    , RULL(0x37010AA3), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3,
+REG64( EX_1_L2_TOD_SYNC110                                     , RULL(0x23010AA3), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3,
+REG64( EX_2_L2_TOD_SYNC110                                     , RULL(0x25010AA3), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3,
+REG64( EX_3_L2_TOD_SYNC110                                     , RULL(0x27010AA3), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3,
+REG64( EX_4_L2_TOD_SYNC110                                     , RULL(0x29010AA3), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3,
+REG64( EX_5_L2_TOD_SYNC110                                     , RULL(0x2B010AA3), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3,
+REG64( EX_6_L2_TOD_SYNC110                                     , RULL(0x2D010AA3), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3,
+REG64( EX_7_L2_TOD_SYNC110                                     , RULL(0x2F010AA3), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3,
+REG64( EX_8_L2_TOD_SYNC110                                     , RULL(0x31010AA3), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3,
+REG64( EX_9_L2_TOD_SYNC110                                     , RULL(0x33010AA3), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3,
+REG64( EX_L2_TOD_SYNC110                                       , RULL(0x21010AA3), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+
+REG64( C_TOD_SYNC111                                           , RULL(0x20010AA3), SH_UNT_C        ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_0_TOD_SYNC111                                         , RULL(0x20010AA3), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_1_TOD_SYNC111                                         , RULL(0x21010AA3), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_2_TOD_SYNC111                                         , RULL(0x22010AA3), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_3_TOD_SYNC111                                         , RULL(0x23010AA3), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_4_TOD_SYNC111                                         , RULL(0x24010AA3), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_5_TOD_SYNC111                                         , RULL(0x25010AA3), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_6_TOD_SYNC111                                         , RULL(0x26010AA3), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_7_TOD_SYNC111                                         , RULL(0x27010AA3), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_8_TOD_SYNC111                                         , RULL(0x28010AA3), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_9_TOD_SYNC111                                         , RULL(0x29010AA3), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_10_TOD_SYNC111                                        , RULL(0x2A010AA3), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_11_TOD_SYNC111                                        , RULL(0x2B010AA3), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_12_TOD_SYNC111                                        , RULL(0x2C010AA3), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_13_TOD_SYNC111                                        , RULL(0x2D010AA3), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_14_TOD_SYNC111                                        , RULL(0x2E010AA3), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_15_TOD_SYNC111                                        , RULL(0x2F010AA3), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_16_TOD_SYNC111                                        , RULL(0x30010AA3), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_17_TOD_SYNC111                                        , RULL(0x31010AA3), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_18_TOD_SYNC111                                        , RULL(0x32010AA3), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_19_TOD_SYNC111                                        , RULL(0x33010AA3), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_20_TOD_SYNC111                                        , RULL(0x34010AA3), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_21_TOD_SYNC111                                        , RULL(0x35010AA3), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_22_TOD_SYNC111                                        , RULL(0x36010AA3), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( C_23_TOD_SYNC111                                        , RULL(0x37010AA3), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG
+REG64( EX_0_L2_TOD_SYNC111                                     , RULL(0x21010AA3), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+REG64( EX_10_L2_TOD_SYNC111                                    , RULL(0x35010AA3), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 34010AA3,
+REG64( EX_11_L2_TOD_SYNC111                                    , RULL(0x37010AA3), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 36010AA3,
+REG64( EX_1_L2_TOD_SYNC111                                     , RULL(0x23010AA3), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 22010AA3,
+REG64( EX_2_L2_TOD_SYNC111                                     , RULL(0x25010AA3), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 24010AA3,
+REG64( EX_3_L2_TOD_SYNC111                                     , RULL(0x27010AA3), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 26010AA3,
+REG64( EX_4_L2_TOD_SYNC111                                     , RULL(0x29010AA3), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 28010AA3,
+REG64( EX_5_L2_TOD_SYNC111                                     , RULL(0x2B010AA3), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2A010AA3,
+REG64( EX_6_L2_TOD_SYNC111                                     , RULL(0x2D010AA3), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2C010AA3,
+REG64( EX_7_L2_TOD_SYNC111                                     , RULL(0x2F010AA3), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 2E010AA3,
+REG64( EX_8_L2_TOD_SYNC111                                     , RULL(0x31010AA3), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 30010AA3,
+REG64( EX_9_L2_TOD_SYNC111                                     , RULL(0x33010AA3), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 32010AA3,
+REG64( EX_L2_TOD_SYNC111                                       , RULL(0x21010AA3), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM1_WO  ); //WARNING - VALUE SET SAME AS ANOTHER REG //DUPS: 20010AA3,
+
+REG64( EQ_TPLC20_TR0_TRACE_HI_DATA_REG                         , RULL(0x10012800), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_TPLC20_TR0_TRACE_HI_DATA_REG                       , RULL(0x10012800), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_TPLC20_TR0_TRACE_HI_DATA_REG                       , RULL(0x11012800), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_TPLC20_TR0_TRACE_HI_DATA_REG                       , RULL(0x12012800), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_TPLC20_TR0_TRACE_HI_DATA_REG                       , RULL(0x13012800), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_TPLC20_TR0_TRACE_HI_DATA_REG                       , RULL(0x14012800), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_TPLC20_TR0_TRACE_HI_DATA_REG                       , RULL(0x15012800), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_TPLC20_TR0_TRACE_HI_DATA_REG                         , RULL(0x10012800), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_TPLC20_TR0_TRACE_HI_DATA_REG                       , RULL(0x10012800), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_2_TPLC20_TR0_TRACE_HI_DATA_REG                       , RULL(0x11012800), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_4_TPLC20_TR0_TRACE_HI_DATA_REG                       , RULL(0x12012800), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_6_TPLC20_TR0_TRACE_HI_DATA_REG                       , RULL(0x13012800), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_8_TPLC20_TR0_TRACE_HI_DATA_REG                       , RULL(0x14012800), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_10_TPLC20_TR0_TRACE_HI_DATA_REG                      , RULL(0x15012800), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_TPLC20_TR0_TRACE_LO_DATA_REG                         , RULL(0x10012801), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_TPLC20_TR0_TRACE_LO_DATA_REG                       , RULL(0x10012801), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_TPLC20_TR0_TRACE_LO_DATA_REG                       , RULL(0x11012801), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_TPLC20_TR0_TRACE_LO_DATA_REG                       , RULL(0x12012801), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_TPLC20_TR0_TRACE_LO_DATA_REG                       , RULL(0x13012801), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_TPLC20_TR0_TRACE_LO_DATA_REG                       , RULL(0x14012801), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_TPLC20_TR0_TRACE_LO_DATA_REG                       , RULL(0x15012801), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_TPLC20_TR0_TRACE_LO_DATA_REG                         , RULL(0x10012801), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_TPLC20_TR0_TRACE_LO_DATA_REG                       , RULL(0x10012801), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_2_TPLC20_TR0_TRACE_LO_DATA_REG                       , RULL(0x11012801), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_4_TPLC20_TR0_TRACE_LO_DATA_REG                       , RULL(0x12012801), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_6_TPLC20_TR0_TRACE_LO_DATA_REG                       , RULL(0x13012801), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_8_TPLC20_TR0_TRACE_LO_DATA_REG                       , RULL(0x14012801), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_10_TPLC20_TR0_TRACE_LO_DATA_REG                      , RULL(0x15012801), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG                       , RULL(0x10012802), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x10012802), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x11012802), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x12012802), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x13012802), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x14012802), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x15012802), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG                       , RULL(0x10012802), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x10012802), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x11012802), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x12012802), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x13012802), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x14012802), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x15012802), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_0                     , RULL(0x10012803), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x10012803), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x11012803), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x12012803), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x13012803), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x14012803), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x15012803), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_0                     , RULL(0x10012803), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x10012803), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x11012803), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x12012803), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x13012803), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x14012803), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x15012803), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_1                     , RULL(0x10012804), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x10012804), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x11012804), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x12012804), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x13012804), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x14012804), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x15012804), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_1                     , RULL(0x10012804), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x10012804), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x11012804), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x12012804), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x13012804), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x14012804), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x15012804), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_2                     , RULL(0x10012805), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x10012805), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x11012805), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x12012805), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x13012805), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x14012805), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x15012805), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_2                     , RULL(0x10012805), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x10012805), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x11012805), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x12012805), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x13012805), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x14012805), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x15012805), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_3                     , RULL(0x10012806), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x10012806), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x11012806), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x12012806), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x13012806), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x14012806), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x15012806), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_3                     , RULL(0x10012806), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x10012806), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x11012806), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x12012806), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x13012806), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x14012806), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x15012806), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_4                     , RULL(0x10012807), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x10012807), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x11012807), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x12012807), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x13012807), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x14012807), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x15012807), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_4                     , RULL(0x10012807), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x10012807), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x11012807), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x12012807), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x13012807), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x14012807), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x15012807), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_5                     , RULL(0x10012808), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x10012808), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x11012808), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x12012808), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x13012808), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x14012808), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x15012808), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_5                     , RULL(0x10012808), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x10012808), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x11012808), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x12012808), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x13012808), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x14012808), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x15012808), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9                     , RULL(0x10012809), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x10012809), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x11012809), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x12012809), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x13012809), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x14012809), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x15012809), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9                     , RULL(0x10012809), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x10012809), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x11012809), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x12012809), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x13012809), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x14012809), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x15012809), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC20_TR1_TRACE_HI_DATA_REG                         , RULL(0x10012840), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_TPLC20_TR1_TRACE_HI_DATA_REG                       , RULL(0x10012840), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_TPLC20_TR1_TRACE_HI_DATA_REG                       , RULL(0x11012840), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_TPLC20_TR1_TRACE_HI_DATA_REG                       , RULL(0x12012840), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_TPLC20_TR1_TRACE_HI_DATA_REG                       , RULL(0x13012840), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_TPLC20_TR1_TRACE_HI_DATA_REG                       , RULL(0x14012840), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_TPLC20_TR1_TRACE_HI_DATA_REG                       , RULL(0x15012840), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_TPLC20_TR1_TRACE_HI_DATA_REG                         , RULL(0x10012840), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_TPLC20_TR1_TRACE_HI_DATA_REG                       , RULL(0x10012840), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_2_TPLC20_TR1_TRACE_HI_DATA_REG                       , RULL(0x11012840), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_4_TPLC20_TR1_TRACE_HI_DATA_REG                       , RULL(0x12012840), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_6_TPLC20_TR1_TRACE_HI_DATA_REG                       , RULL(0x13012840), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_8_TPLC20_TR1_TRACE_HI_DATA_REG                       , RULL(0x14012840), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_10_TPLC20_TR1_TRACE_HI_DATA_REG                      , RULL(0x15012840), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_TPLC20_TR1_TRACE_LO_DATA_REG                         , RULL(0x10012841), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_TPLC20_TR1_TRACE_LO_DATA_REG                       , RULL(0x10012841), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_TPLC20_TR1_TRACE_LO_DATA_REG                       , RULL(0x11012841), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_TPLC20_TR1_TRACE_LO_DATA_REG                       , RULL(0x12012841), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_TPLC20_TR1_TRACE_LO_DATA_REG                       , RULL(0x13012841), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_TPLC20_TR1_TRACE_LO_DATA_REG                       , RULL(0x14012841), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_TPLC20_TR1_TRACE_LO_DATA_REG                       , RULL(0x15012841), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_TPLC20_TR1_TRACE_LO_DATA_REG                         , RULL(0x10012841), SH_UNT_EX       , SH_ACS_SCOM_RO   );
+REG64( EX_0_TPLC20_TR1_TRACE_LO_DATA_REG                       , RULL(0x10012841), SH_UNT_EX_0     , SH_ACS_SCOM_RO   );
+REG64( EX_2_TPLC20_TR1_TRACE_LO_DATA_REG                       , RULL(0x11012841), SH_UNT_EX_2     , SH_ACS_SCOM_RO   );
+REG64( EX_4_TPLC20_TR1_TRACE_LO_DATA_REG                       , RULL(0x12012841), SH_UNT_EX_4     , SH_ACS_SCOM_RO   );
+REG64( EX_6_TPLC20_TR1_TRACE_LO_DATA_REG                       , RULL(0x13012841), SH_UNT_EX_6     , SH_ACS_SCOM_RO   );
+REG64( EX_8_TPLC20_TR1_TRACE_LO_DATA_REG                       , RULL(0x14012841), SH_UNT_EX_8     , SH_ACS_SCOM_RO   );
+REG64( EX_10_TPLC20_TR1_TRACE_LO_DATA_REG                      , RULL(0x15012841), SH_UNT_EX_10    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG                       , RULL(0x10012842), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x10012842), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x11012842), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x12012842), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x13012842), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x14012842), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x15012842), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG                       , RULL(0x10012842), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x10012842), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x11012842), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x12012842), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x13012842), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x14012842), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR1_TRACE_TRCTRL_CONFIG                    , RULL(0x15012842), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_0                     , RULL(0x10012843), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x10012843), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x11012843), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x12012843), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x13012843), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x14012843), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x15012843), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_0                     , RULL(0x10012843), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x10012843), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x11012843), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x12012843), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x13012843), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x14012843), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_0                  , RULL(0x15012843), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_1                     , RULL(0x10012844), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x10012844), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x11012844), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x12012844), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x13012844), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x14012844), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x15012844), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_1                     , RULL(0x10012844), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x10012844), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x11012844), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x12012844), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x13012844), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x14012844), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_1                  , RULL(0x15012844), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_2                     , RULL(0x10012845), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x10012845), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x11012845), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x12012845), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x13012845), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x14012845), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x15012845), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_2                     , RULL(0x10012845), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x10012845), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x11012845), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x12012845), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x13012845), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x14012845), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_2                  , RULL(0x15012845), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_3                     , RULL(0x10012846), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x10012846), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x11012846), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x12012846), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x13012846), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x14012846), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x15012846), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_3                     , RULL(0x10012846), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x10012846), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x11012846), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x12012846), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x13012846), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x14012846), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_3                  , RULL(0x15012846), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_4                     , RULL(0x10012847), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x10012847), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x11012847), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x12012847), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x13012847), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x14012847), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x15012847), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_4                     , RULL(0x10012847), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x10012847), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x11012847), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x12012847), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x13012847), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x14012847), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_4                  , RULL(0x15012847), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_5                     , RULL(0x10012848), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x10012848), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x11012848), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x12012848), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x13012848), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x14012848), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x15012848), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_5                     , RULL(0x10012848), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x10012848), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x11012848), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x12012848), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x13012848), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x14012848), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_5                  , RULL(0x15012848), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9                     , RULL(0x10012849), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x10012849), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC20_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x11012849), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x12012849), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC20_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x13012849), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x14012849), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC20_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x15012849), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9                     , RULL(0x10012849), SH_UNT_EX       , SH_ACS_SCOM      );
+REG64( EX_0_TPLC20_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x10012849), SH_UNT_EX_0     , SH_ACS_SCOM      );
+REG64( EX_2_TPLC20_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x11012849), SH_UNT_EX_2     , SH_ACS_SCOM      );
+REG64( EX_4_TPLC20_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x12012849), SH_UNT_EX_4     , SH_ACS_SCOM      );
+REG64( EX_6_TPLC20_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x13012849), SH_UNT_EX_6     , SH_ACS_SCOM      );
+REG64( EX_8_TPLC20_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x14012849), SH_UNT_EX_8     , SH_ACS_SCOM      );
+REG64( EX_10_TPLC20_TR1_TRACE_TRDATA_CONFIG_9                  , RULL(0x15012849), SH_UNT_EX_10    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR0_TRACE_HI_DATA_REG                         , RULL(0x10012C00), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_TPLC21_TR0_TRACE_HI_DATA_REG                       , RULL(0x10012C00), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_TPLC21_TR0_TRACE_HI_DATA_REG                       , RULL(0x11012C00), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_TPLC21_TR0_TRACE_HI_DATA_REG                       , RULL(0x12012C00), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_TPLC21_TR0_TRACE_HI_DATA_REG                       , RULL(0x13012C00), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_TPLC21_TR0_TRACE_HI_DATA_REG                       , RULL(0x14012C00), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_TPLC21_TR0_TRACE_HI_DATA_REG                       , RULL(0x15012C00), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_1_TPLC21_TR0_TRACE_HI_DATA_REG                       , RULL(0x10012C00), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_3_TPLC21_TR0_TRACE_HI_DATA_REG                       , RULL(0x11012C00), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_5_TPLC21_TR0_TRACE_HI_DATA_REG                       , RULL(0x12012C00), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_7_TPLC21_TR0_TRACE_HI_DATA_REG                       , RULL(0x13012C00), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_9_TPLC21_TR0_TRACE_HI_DATA_REG                       , RULL(0x14012C00), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_11_TPLC21_TR0_TRACE_HI_DATA_REG                      , RULL(0x15012C00), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_TPLC21_TR0_TRACE_LO_DATA_REG                         , RULL(0x10012C01), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_TPLC21_TR0_TRACE_LO_DATA_REG                       , RULL(0x10012C01), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_TPLC21_TR0_TRACE_LO_DATA_REG                       , RULL(0x11012C01), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_TPLC21_TR0_TRACE_LO_DATA_REG                       , RULL(0x12012C01), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_TPLC21_TR0_TRACE_LO_DATA_REG                       , RULL(0x13012C01), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_TPLC21_TR0_TRACE_LO_DATA_REG                       , RULL(0x14012C01), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_TPLC21_TR0_TRACE_LO_DATA_REG                       , RULL(0x15012C01), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_1_TPLC21_TR0_TRACE_LO_DATA_REG                       , RULL(0x10012C01), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_3_TPLC21_TR0_TRACE_LO_DATA_REG                       , RULL(0x11012C01), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_5_TPLC21_TR0_TRACE_LO_DATA_REG                       , RULL(0x12012C01), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_7_TPLC21_TR0_TRACE_LO_DATA_REG                       , RULL(0x13012C01), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_9_TPLC21_TR0_TRACE_LO_DATA_REG                       , RULL(0x14012C01), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_11_TPLC21_TR0_TRACE_LO_DATA_REG                      , RULL(0x15012C01), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG                       , RULL(0x10012C02), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x10012C02), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x11012C02), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x12012C02), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x13012C02), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x14012C02), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x15012C02), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x10012C02), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x11012C02), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x12012C02), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x13012C02), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR0_TRACE_TRCTRL_CONFIG                     , RULL(0x14012C02), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR0_TRACE_TRCTRL_CONFIG                    , RULL(0x15012C02), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_0                     , RULL(0x10012C03), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x10012C03), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x11012C03), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x12012C03), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x13012C03), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x14012C03), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x15012C03), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x10012C03), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x11012C03), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x12012C03), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x13012C03), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_0                   , RULL(0x14012C03), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_0                  , RULL(0x15012C03), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_1                     , RULL(0x10012C04), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x10012C04), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x11012C04), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x12012C04), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x13012C04), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x14012C04), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x15012C04), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x10012C04), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x11012C04), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x12012C04), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x13012C04), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_1                   , RULL(0x14012C04), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_1                  , RULL(0x15012C04), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_2                     , RULL(0x10012C05), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x10012C05), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x11012C05), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x12012C05), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x13012C05), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x14012C05), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x15012C05), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x10012C05), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x11012C05), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x12012C05), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x13012C05), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_2                   , RULL(0x14012C05), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_2                  , RULL(0x15012C05), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_3                     , RULL(0x10012C06), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x10012C06), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x11012C06), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x12012C06), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x13012C06), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x14012C06), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x15012C06), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x10012C06), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x11012C06), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x12012C06), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x13012C06), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_3                   , RULL(0x14012C06), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_3                  , RULL(0x15012C06), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_4                     , RULL(0x10012C07), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x10012C07), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x11012C07), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x12012C07), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x13012C07), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x14012C07), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x15012C07), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x10012C07), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x11012C07), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x12012C07), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x13012C07), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_4                   , RULL(0x14012C07), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_4                  , RULL(0x15012C07), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_5                     , RULL(0x10012C08), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x10012C08), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x11012C08), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x12012C08), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x13012C08), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x14012C08), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x15012C08), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x10012C08), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x11012C08), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x12012C08), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x13012C08), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_5                   , RULL(0x14012C08), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_5                  , RULL(0x15012C08), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9                     , RULL(0x10012C09), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x10012C09), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x11012C09), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x12012C09), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x13012C09), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x14012C09), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x15012C09), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x10012C09), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x11012C09), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x12012C09), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x13012C09), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR0_TRACE_TRDATA_CONFIG_9                   , RULL(0x14012C09), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR0_TRACE_TRDATA_CONFIG_9                  , RULL(0x15012C09), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR1_TRACE_HI_DATA_REG                         , RULL(0x10012C40), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_TPLC21_TR1_TRACE_HI_DATA_REG                       , RULL(0x10012C40), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_TPLC21_TR1_TRACE_HI_DATA_REG                       , RULL(0x11012C40), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_TPLC21_TR1_TRACE_HI_DATA_REG                       , RULL(0x12012C40), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_TPLC21_TR1_TRACE_HI_DATA_REG                       , RULL(0x13012C40), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_TPLC21_TR1_TRACE_HI_DATA_REG                       , RULL(0x14012C40), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_TPLC21_TR1_TRACE_HI_DATA_REG                       , RULL(0x15012C40), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_1_TPLC21_TR1_TRACE_HI_DATA_REG                       , RULL(0x10012C40), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_3_TPLC21_TR1_TRACE_HI_DATA_REG                       , RULL(0x11012C40), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_5_TPLC21_TR1_TRACE_HI_DATA_REG                       , RULL(0x12012C40), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_7_TPLC21_TR1_TRACE_HI_DATA_REG                       , RULL(0x13012C40), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_9_TPLC21_TR1_TRACE_HI_DATA_REG                       , RULL(0x14012C40), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_11_TPLC21_TR1_TRACE_HI_DATA_REG                      , RULL(0x15012C40), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_TPLC21_TR1_TRACE_LO_DATA_REG                         , RULL(0x10012C41), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_TPLC21_TR1_TRACE_LO_DATA_REG                       , RULL(0x10012C41), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_TPLC21_TR1_TRACE_LO_DATA_REG                       , RULL(0x11012C41), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_TPLC21_TR1_TRACE_LO_DATA_REG                       , RULL(0x12012C41), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_TPLC21_TR1_TRACE_LO_DATA_REG                       , RULL(0x13012C41), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_TPLC21_TR1_TRACE_LO_DATA_REG                       , RULL(0x14012C41), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_TPLC21_TR1_TRACE_LO_DATA_REG                       , RULL(0x15012C41), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_1_TPLC21_TR1_TRACE_LO_DATA_REG                       , RULL(0x10012C41), SH_UNT_EX_1     , SH_ACS_SCOM_RO   );
+REG64( EX_3_TPLC21_TR1_TRACE_LO_DATA_REG                       , RULL(0x11012C41), SH_UNT_EX_3     , SH_ACS_SCOM_RO   );
+REG64( EX_5_TPLC21_TR1_TRACE_LO_DATA_REG                       , RULL(0x12012C41), SH_UNT_EX_5     , SH_ACS_SCOM_RO   );
+REG64( EX_7_TPLC21_TR1_TRACE_LO_DATA_REG                       , RULL(0x13012C41), SH_UNT_EX_7     , SH_ACS_SCOM_RO   );
+REG64( EX_9_TPLC21_TR1_TRACE_LO_DATA_REG                       , RULL(0x14012C41), SH_UNT_EX_9     , SH_ACS_SCOM_RO   );
+REG64( EX_11_TPLC21_TR1_TRACE_LO_DATA_REG                      , RULL(0x15012C41), SH_UNT_EX_11    , SH_ACS_SCOM_RO   );
+
+REG64( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG                       , RULL(0x10012C42), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x10012C42), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x11012C42), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x12012C42), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x13012C42), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x14012C42), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x15012C42), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x10012C42), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x11012C42), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x12012C42), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x13012C42), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR1_TRACE_TRCTRL_CONFIG                     , RULL(0x14012C42), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR1_TRACE_TRCTRL_CONFIG                    , RULL(0x15012C42), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_0                     , RULL(0x10012C43), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x10012C43), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x11012C43), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x12012C43), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x13012C43), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x14012C43), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x15012C43), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x10012C43), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x11012C43), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x12012C43), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x13012C43), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_0                   , RULL(0x14012C43), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_0                  , RULL(0x15012C43), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_1                     , RULL(0x10012C44), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x10012C44), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x11012C44), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x12012C44), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x13012C44), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x14012C44), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x15012C44), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x10012C44), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x11012C44), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x12012C44), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x13012C44), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_1                   , RULL(0x14012C44), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_1                  , RULL(0x15012C44), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_2                     , RULL(0x10012C45), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x10012C45), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x11012C45), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x12012C45), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x13012C45), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x14012C45), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x15012C45), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x10012C45), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x11012C45), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x12012C45), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x13012C45), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_2                   , RULL(0x14012C45), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_2                  , RULL(0x15012C45), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_3                     , RULL(0x10012C46), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x10012C46), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x11012C46), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x12012C46), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x13012C46), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x14012C46), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x15012C46), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x10012C46), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x11012C46), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x12012C46), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x13012C46), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_3                   , RULL(0x14012C46), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_3                  , RULL(0x15012C46), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_4                     , RULL(0x10012C47), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x10012C47), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x11012C47), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x12012C47), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x13012C47), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x14012C47), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x15012C47), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x10012C47), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x11012C47), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x12012C47), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x13012C47), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_4                   , RULL(0x14012C47), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_4                  , RULL(0x15012C47), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_5                     , RULL(0x10012C48), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x10012C48), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x11012C48), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x12012C48), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x13012C48), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x14012C48), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x15012C48), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x10012C48), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x11012C48), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x12012C48), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x13012C48), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_5                   , RULL(0x14012C48), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_5                  , RULL(0x15012C48), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9                     , RULL(0x10012C49), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_TPLC21_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x10012C49), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x11012C49), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_TPLC21_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x12012C49), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x13012C49), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_TPLC21_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x14012C49), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x15012C49), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_1_TPLC21_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x10012C49), SH_UNT_EX_1     , SH_ACS_SCOM      );
+REG64( EX_3_TPLC21_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x11012C49), SH_UNT_EX_3     , SH_ACS_SCOM      );
+REG64( EX_5_TPLC21_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x12012C49), SH_UNT_EX_5     , SH_ACS_SCOM      );
+REG64( EX_7_TPLC21_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x13012C49), SH_UNT_EX_7     , SH_ACS_SCOM      );
+REG64( EX_9_TPLC21_TR1_TRACE_TRDATA_CONFIG_9                   , RULL(0x14012C49), SH_UNT_EX_9     , SH_ACS_SCOM      );
+REG64( EX_11_TPLC21_TR1_TRACE_TRDATA_CONFIG_9                  , RULL(0x15012C49), SH_UNT_EX_11    , SH_ACS_SCOM      );
+
+REG64( C_V0_HMER_WAND                                          , RULL(0x20010A92), SH_UNT_C        ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_V0_HMER_OR                                            , RULL(0x20010A8E), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_V0_HMER_WAND                                        , RULL(0x20010A92), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_0_V0_HMER_OR                                          , RULL(0x20010A8E), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_V0_HMER_WAND                                        , RULL(0x21010A92), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_1_V0_HMER_OR                                          , RULL(0x21010A8E), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_V0_HMER_WAND                                        , RULL(0x22010A92), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_2_V0_HMER_OR                                          , RULL(0x22010A8E), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_V0_HMER_WAND                                        , RULL(0x23010A92), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_3_V0_HMER_OR                                          , RULL(0x23010A8E), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_V0_HMER_WAND                                        , RULL(0x24010A92), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_4_V0_HMER_OR                                          , RULL(0x24010A8E), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_V0_HMER_WAND                                        , RULL(0x25010A92), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_5_V0_HMER_OR                                          , RULL(0x25010A8E), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_V0_HMER_WAND                                        , RULL(0x26010A92), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_6_V0_HMER_OR                                          , RULL(0x26010A8E), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_V0_HMER_WAND                                        , RULL(0x27010A92), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_7_V0_HMER_OR                                          , RULL(0x27010A8E), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_V0_HMER_WAND                                        , RULL(0x28010A92), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_8_V0_HMER_OR                                          , RULL(0x28010A8E), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_V0_HMER_WAND                                        , RULL(0x29010A92), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_9_V0_HMER_OR                                          , RULL(0x29010A8E), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_V0_HMER_WAND                                       , RULL(0x2A010A92), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_10_V0_HMER_OR                                         , RULL(0x2A010A8E), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_V0_HMER_WAND                                       , RULL(0x2B010A92), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_11_V0_HMER_OR                                         , RULL(0x2B010A8E), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_V0_HMER_WAND                                       , RULL(0x2C010A92), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_12_V0_HMER_OR                                         , RULL(0x2C010A8E), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_V0_HMER_WAND                                       , RULL(0x2D010A92), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_13_V0_HMER_OR                                         , RULL(0x2D010A8E), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_V0_HMER_WAND                                       , RULL(0x2E010A92), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_14_V0_HMER_OR                                         , RULL(0x2E010A8E), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_V0_HMER_WAND                                       , RULL(0x2F010A92), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_15_V0_HMER_OR                                         , RULL(0x2F010A8E), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_V0_HMER_WAND                                       , RULL(0x30010A92), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_16_V0_HMER_OR                                         , RULL(0x30010A8E), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_V0_HMER_WAND                                       , RULL(0x31010A92), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_17_V0_HMER_OR                                         , RULL(0x31010A8E), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_V0_HMER_WAND                                       , RULL(0x32010A92), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_18_V0_HMER_OR                                         , RULL(0x32010A8E), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_V0_HMER_WAND                                       , RULL(0x33010A92), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_19_V0_HMER_OR                                         , RULL(0x33010A8E), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_V0_HMER_WAND                                       , RULL(0x34010A92), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_20_V0_HMER_OR                                         , RULL(0x34010A8E), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_V0_HMER_WAND                                       , RULL(0x35010A92), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_21_V0_HMER_OR                                         , RULL(0x35010A8E), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_V0_HMER_WAND                                       , RULL(0x36010A92), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_22_V0_HMER_OR                                         , RULL(0x36010A8E), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_V0_HMER_WAND                                       , RULL(0x37010A92), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_23_V0_HMER_OR                                         , RULL(0x37010A8E), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EX_V0_HMER                                              , RULL(0x21010A8E), SH_UNT_EX       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 20010A8E,
+REG64( EX_0_V0_HMER                                            , RULL(0x21010A8E), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 20010A8E,
+REG64( EX_1_V0_HMER                                            , RULL(0x23010A8E), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 22010A8E,
+REG64( EX_2_V0_HMER                                            , RULL(0x25010A8E), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 24010A8E,
+REG64( EX_3_V0_HMER                                            , RULL(0x27010A8E), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 26010A8E,
+REG64( EX_4_V0_HMER                                            , RULL(0x29010A8E), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 28010A8E,
+REG64( EX_5_V0_HMER                                            , RULL(0x2B010A8E), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2A010A8E,
+REG64( EX_6_V0_HMER                                            , RULL(0x2D010A8E), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2C010A8E,
+REG64( EX_7_V0_HMER                                            , RULL(0x2F010A8E), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2E010A8E,
+REG64( EX_8_V0_HMER                                            , RULL(0x31010A8E), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 30010A8E,
+REG64( EX_9_V0_HMER                                            , RULL(0x33010A8E), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 32010A8E,
+REG64( EX_0_L2_V0_HMER                                         , RULL(0x21010A92), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 20010A92,
+REG64( EX_10_V0_HMER                                           , RULL(0x35010A8E), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 34010A8E,
+REG64( EX_11_V0_HMER                                           , RULL(0x37010A8E), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 36010A8E,
+REG64( EX_10_L2_V0_HMER                                        , RULL(0x35010A92), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 34010A92,
+REG64( EX_11_L2_V0_HMER                                        , RULL(0x37010A92), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 36010A92,
+REG64( EX_1_L2_V0_HMER                                         , RULL(0x23010A92), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 22010A92,
+REG64( EX_2_L2_V0_HMER                                         , RULL(0x25010A92), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 24010A92,
+REG64( EX_3_L2_V0_HMER                                         , RULL(0x27010A92), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 26010A92,
+REG64( EX_4_L2_V0_HMER                                         , RULL(0x29010A92), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 28010A92,
+REG64( EX_5_L2_V0_HMER                                         , RULL(0x2B010A92), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2A010A92,
+REG64( EX_6_L2_V0_HMER                                         , RULL(0x2D010A92), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2C010A92,
+REG64( EX_7_L2_V0_HMER                                         , RULL(0x2F010A92), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2E010A92,
+REG64( EX_8_L2_V0_HMER                                         , RULL(0x31010A92), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 30010A92,
+REG64( EX_9_L2_V0_HMER                                         , RULL(0x33010A92), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 32010A92,
+REG64( EX_L2_V0_HMER                                           , RULL(0x21010A92), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 20010A92,
+
+REG64( C_V1_HMER_WAND                                          , RULL(0x20010A93), SH_UNT_C        ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_V1_HMER_OR                                            , RULL(0x20010A8F), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_V1_HMER_WAND                                        , RULL(0x20010A93), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_0_V1_HMER_OR                                          , RULL(0x20010A8F), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_V1_HMER_WAND                                        , RULL(0x21010A93), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_1_V1_HMER_OR                                          , RULL(0x21010A8F), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_V1_HMER_WAND                                        , RULL(0x22010A93), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_2_V1_HMER_OR                                          , RULL(0x22010A8F), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_V1_HMER_WAND                                        , RULL(0x23010A93), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_3_V1_HMER_OR                                          , RULL(0x23010A8F), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_V1_HMER_WAND                                        , RULL(0x24010A93), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_4_V1_HMER_OR                                          , RULL(0x24010A8F), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_V1_HMER_WAND                                        , RULL(0x25010A93), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_5_V1_HMER_OR                                          , RULL(0x25010A8F), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_V1_HMER_WAND                                        , RULL(0x26010A93), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_6_V1_HMER_OR                                          , RULL(0x26010A8F), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_V1_HMER_WAND                                        , RULL(0x27010A93), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_7_V1_HMER_OR                                          , RULL(0x27010A8F), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_V1_HMER_WAND                                        , RULL(0x28010A93), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_8_V1_HMER_OR                                          , RULL(0x28010A8F), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_V1_HMER_WAND                                        , RULL(0x29010A93), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_9_V1_HMER_OR                                          , RULL(0x29010A8F), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_V1_HMER_WAND                                       , RULL(0x2A010A93), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_10_V1_HMER_OR                                         , RULL(0x2A010A8F), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_V1_HMER_WAND                                       , RULL(0x2B010A93), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_11_V1_HMER_OR                                         , RULL(0x2B010A8F), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_V1_HMER_WAND                                       , RULL(0x2C010A93), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_12_V1_HMER_OR                                         , RULL(0x2C010A8F), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_V1_HMER_WAND                                       , RULL(0x2D010A93), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_13_V1_HMER_OR                                         , RULL(0x2D010A8F), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_V1_HMER_WAND                                       , RULL(0x2E010A93), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_14_V1_HMER_OR                                         , RULL(0x2E010A8F), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_V1_HMER_WAND                                       , RULL(0x2F010A93), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_15_V1_HMER_OR                                         , RULL(0x2F010A8F), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_V1_HMER_WAND                                       , RULL(0x30010A93), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_16_V1_HMER_OR                                         , RULL(0x30010A8F), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_V1_HMER_WAND                                       , RULL(0x31010A93), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_17_V1_HMER_OR                                         , RULL(0x31010A8F), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_V1_HMER_WAND                                       , RULL(0x32010A93), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_18_V1_HMER_OR                                         , RULL(0x32010A8F), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_V1_HMER_WAND                                       , RULL(0x33010A93), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_19_V1_HMER_OR                                         , RULL(0x33010A8F), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_V1_HMER_WAND                                       , RULL(0x34010A93), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_20_V1_HMER_OR                                         , RULL(0x34010A8F), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_V1_HMER_WAND                                       , RULL(0x35010A93), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_21_V1_HMER_OR                                         , RULL(0x35010A8F), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_V1_HMER_WAND                                       , RULL(0x36010A93), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_22_V1_HMER_OR                                         , RULL(0x36010A8F), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_V1_HMER_WAND                                       , RULL(0x37010A93), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_23_V1_HMER_OR                                         , RULL(0x37010A8F), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EX_V1_HMER                                              , RULL(0x21010A8F), SH_UNT_EX       ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 20010A8F,
+REG64( EX_0_V1_HMER                                            , RULL(0x21010A8F), SH_UNT_EX_0     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 20010A8F,
+REG64( EX_1_V1_HMER                                            , RULL(0x23010A8F), SH_UNT_EX_1     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 22010A8F,
+REG64( EX_2_V1_HMER                                            , RULL(0x25010A8F), SH_UNT_EX_2     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 24010A8F,
+REG64( EX_3_V1_HMER                                            , RULL(0x27010A8F), SH_UNT_EX_3     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 26010A8F,
+REG64( EX_4_V1_HMER                                            , RULL(0x29010A8F), SH_UNT_EX_4     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 28010A8F,
+REG64( EX_5_V1_HMER                                            , RULL(0x2B010A8F), SH_UNT_EX_5     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2A010A8F,
+REG64( EX_6_V1_HMER                                            , RULL(0x2D010A8F), SH_UNT_EX_6     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2C010A8F,
+REG64( EX_7_V1_HMER                                            , RULL(0x2F010A8F), SH_UNT_EX_7     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2E010A8F,
+REG64( EX_8_V1_HMER                                            , RULL(0x31010A8F), SH_UNT_EX_8     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 30010A8F,
+REG64( EX_9_V1_HMER                                            , RULL(0x33010A8F), SH_UNT_EX_9     ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 32010A8F,
+REG64( EX_0_L2_V1_HMER                                         , RULL(0x21010A93), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 20010A93,
+REG64( EX_10_V1_HMER                                           , RULL(0x35010A8F), SH_UNT_EX_10    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 34010A8F,
+REG64( EX_11_V1_HMER                                           , RULL(0x37010A8F), SH_UNT_EX_11    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 36010A8F,
+REG64( EX_10_L2_V1_HMER                                        , RULL(0x35010A93), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 34010A93,
+REG64( EX_11_L2_V1_HMER                                        , RULL(0x37010A93), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 36010A93,
+REG64( EX_1_L2_V1_HMER                                         , RULL(0x23010A93), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 22010A93,
+REG64( EX_2_L2_V1_HMER                                         , RULL(0x25010A93), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 24010A93,
+REG64( EX_3_L2_V1_HMER                                         , RULL(0x27010A93), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 26010A93,
+REG64( EX_4_L2_V1_HMER                                         , RULL(0x29010A93), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 28010A93,
+REG64( EX_5_L2_V1_HMER                                         , RULL(0x2B010A93), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2A010A93,
+REG64( EX_6_L2_V1_HMER                                         , RULL(0x2D010A93), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2C010A93,
+REG64( EX_7_L2_V1_HMER                                         , RULL(0x2F010A93), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2E010A93,
+REG64( EX_8_L2_V1_HMER                                         , RULL(0x31010A93), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 30010A93,
+REG64( EX_9_L2_V1_HMER                                         , RULL(0x33010A93), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 32010A93,
+REG64( EX_L2_V1_HMER                                           , RULL(0x21010A93), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 20010A93,
+
+REG64( C_V2_HMER_WAND                                          , RULL(0x20010A94), SH_UNT_C        ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_V2_HMER_OR                                            , RULL(0x20010A90), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_V2_HMER_WAND                                        , RULL(0x20010A94), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_0_V2_HMER_OR                                          , RULL(0x20010A90), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_V2_HMER_WAND                                        , RULL(0x21010A94), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_1_V2_HMER_OR                                          , RULL(0x21010A90), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_V2_HMER_WAND                                        , RULL(0x22010A94), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_2_V2_HMER_OR                                          , RULL(0x22010A90), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_V2_HMER_WAND                                        , RULL(0x23010A94), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_3_V2_HMER_OR                                          , RULL(0x23010A90), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_V2_HMER_WAND                                        , RULL(0x24010A94), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_4_V2_HMER_OR                                          , RULL(0x24010A90), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_V2_HMER_WAND                                        , RULL(0x25010A94), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_5_V2_HMER_OR                                          , RULL(0x25010A90), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_V2_HMER_WAND                                        , RULL(0x26010A94), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_6_V2_HMER_OR                                          , RULL(0x26010A90), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_V2_HMER_WAND                                        , RULL(0x27010A94), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_7_V2_HMER_OR                                          , RULL(0x27010A90), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_V2_HMER_WAND                                        , RULL(0x28010A94), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_8_V2_HMER_OR                                          , RULL(0x28010A90), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_V2_HMER_WAND                                        , RULL(0x29010A94), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_9_V2_HMER_OR                                          , RULL(0x29010A90), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_V2_HMER_WAND                                       , RULL(0x2A010A94), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_10_V2_HMER_OR                                         , RULL(0x2A010A90), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_V2_HMER_WAND                                       , RULL(0x2B010A94), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_11_V2_HMER_OR                                         , RULL(0x2B010A90), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_V2_HMER_WAND                                       , RULL(0x2C010A94), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_12_V2_HMER_OR                                         , RULL(0x2C010A90), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_V2_HMER_WAND                                       , RULL(0x2D010A94), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_13_V2_HMER_OR                                         , RULL(0x2D010A90), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_V2_HMER_WAND                                       , RULL(0x2E010A94), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_14_V2_HMER_OR                                         , RULL(0x2E010A90), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_V2_HMER_WAND                                       , RULL(0x2F010A94), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_15_V2_HMER_OR                                         , RULL(0x2F010A90), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_V2_HMER_WAND                                       , RULL(0x30010A94), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_16_V2_HMER_OR                                         , RULL(0x30010A90), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_V2_HMER_WAND                                       , RULL(0x31010A94), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_17_V2_HMER_OR                                         , RULL(0x31010A90), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_V2_HMER_WAND                                       , RULL(0x32010A94), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_18_V2_HMER_OR                                         , RULL(0x32010A90), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_V2_HMER_WAND                                       , RULL(0x33010A94), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_19_V2_HMER_OR                                         , RULL(0x33010A90), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_V2_HMER_WAND                                       , RULL(0x34010A94), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_20_V2_HMER_OR                                         , RULL(0x34010A90), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_V2_HMER_WAND                                       , RULL(0x35010A94), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_21_V2_HMER_OR                                         , RULL(0x35010A90), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_V2_HMER_WAND                                       , RULL(0x36010A94), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_22_V2_HMER_OR                                         , RULL(0x36010A90), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_V2_HMER_WAND                                       , RULL(0x37010A94), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_23_V2_HMER_OR                                         , RULL(0x37010A90), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EX_0_L2_V2_HMER_WAND                                    , RULL(0x21010A94), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 20010A94,
+REG64( EX_0_L2_V2_HMER_OR                                      , RULL(0x21010A90), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 20010A90,
+REG64( EX_10_L2_V2_HMER_WAND                                   , RULL(0x35010A94), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 34010A94,
+REG64( EX_10_L2_V2_HMER_OR                                     , RULL(0x35010A90), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 34010A90,
+REG64( EX_11_L2_V2_HMER_WAND                                   , RULL(0x37010A94), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 36010A94,
+REG64( EX_11_L2_V2_HMER_OR                                     , RULL(0x37010A90), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 36010A90,
+REG64( EX_1_L2_V2_HMER_WAND                                    , RULL(0x23010A94), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 22010A94,
+REG64( EX_1_L2_V2_HMER_OR                                      , RULL(0x23010A90), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 22010A90,
+REG64( EX_2_L2_V2_HMER_WAND                                    , RULL(0x25010A94), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 24010A94,
+REG64( EX_2_L2_V2_HMER_OR                                      , RULL(0x25010A90), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 24010A90,
+REG64( EX_3_L2_V2_HMER_WAND                                    , RULL(0x27010A94), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 26010A94,
+REG64( EX_3_L2_V2_HMER_OR                                      , RULL(0x27010A90), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 26010A90,
+REG64( EX_4_L2_V2_HMER_WAND                                    , RULL(0x29010A94), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 28010A94,
+REG64( EX_4_L2_V2_HMER_OR                                      , RULL(0x29010A90), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 28010A90,
+REG64( EX_5_L2_V2_HMER_WAND                                    , RULL(0x2B010A94), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2A010A94,
+REG64( EX_5_L2_V2_HMER_OR                                      , RULL(0x2B010A90), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2A010A90,
+REG64( EX_6_L2_V2_HMER_WAND                                    , RULL(0x2D010A94), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2C010A94,
+REG64( EX_6_L2_V2_HMER_OR                                      , RULL(0x2D010A90), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2C010A90,
+REG64( EX_7_L2_V2_HMER_WAND                                    , RULL(0x2F010A94), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2E010A94,
+REG64( EX_7_L2_V2_HMER_OR                                      , RULL(0x2F010A90), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2E010A90,
+REG64( EX_8_L2_V2_HMER_WAND                                    , RULL(0x31010A94), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 30010A94,
+REG64( EX_8_L2_V2_HMER_OR                                      , RULL(0x31010A90), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 30010A90,
+REG64( EX_9_L2_V2_HMER_WAND                                    , RULL(0x33010A94), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 32010A94,
+REG64( EX_9_L2_V2_HMER_OR                                      , RULL(0x33010A90), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 32010A90,
+REG64( EX_L2_V2_HMER_WAND                                      , RULL(0x21010A94), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 20010A94,
+REG64( EX_L2_V2_HMER_OR                                        , RULL(0x21010A90), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 20010A90,
+
+REG64( C_V3_HMER_WAND                                          , RULL(0x20010A95), SH_UNT_C        ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_V3_HMER_OR                                            , RULL(0x20010A91), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+REG64( C_0_V3_HMER_WAND                                        , RULL(0x20010A95), SH_UNT_C_0      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_0_V3_HMER_OR                                          , RULL(0x20010A91), SH_UNT_C_0      , SH_ACS_SCOM2_OR  );
+REG64( C_1_V3_HMER_WAND                                        , RULL(0x21010A95), SH_UNT_C_1      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_1_V3_HMER_OR                                          , RULL(0x21010A91), SH_UNT_C_1      , SH_ACS_SCOM2_OR  );
+REG64( C_2_V3_HMER_WAND                                        , RULL(0x22010A95), SH_UNT_C_2      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_2_V3_HMER_OR                                          , RULL(0x22010A91), SH_UNT_C_2      , SH_ACS_SCOM2_OR  );
+REG64( C_3_V3_HMER_WAND                                        , RULL(0x23010A95), SH_UNT_C_3      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_3_V3_HMER_OR                                          , RULL(0x23010A91), SH_UNT_C_3      , SH_ACS_SCOM2_OR  );
+REG64( C_4_V3_HMER_WAND                                        , RULL(0x24010A95), SH_UNT_C_4      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_4_V3_HMER_OR                                          , RULL(0x24010A91), SH_UNT_C_4      , SH_ACS_SCOM2_OR  );
+REG64( C_5_V3_HMER_WAND                                        , RULL(0x25010A95), SH_UNT_C_5      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_5_V3_HMER_OR                                          , RULL(0x25010A91), SH_UNT_C_5      , SH_ACS_SCOM2_OR  );
+REG64( C_6_V3_HMER_WAND                                        , RULL(0x26010A95), SH_UNT_C_6      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_6_V3_HMER_OR                                          , RULL(0x26010A91), SH_UNT_C_6      , SH_ACS_SCOM2_OR  );
+REG64( C_7_V3_HMER_WAND                                        , RULL(0x27010A95), SH_UNT_C_7      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_7_V3_HMER_OR                                          , RULL(0x27010A91), SH_UNT_C_7      , SH_ACS_SCOM2_OR  );
+REG64( C_8_V3_HMER_WAND                                        , RULL(0x28010A95), SH_UNT_C_8      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_8_V3_HMER_OR                                          , RULL(0x28010A91), SH_UNT_C_8      , SH_ACS_SCOM2_OR  );
+REG64( C_9_V3_HMER_WAND                                        , RULL(0x29010A95), SH_UNT_C_9      ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_9_V3_HMER_OR                                          , RULL(0x29010A91), SH_UNT_C_9      , SH_ACS_SCOM2_OR  );
+REG64( C_10_V3_HMER_WAND                                       , RULL(0x2A010A95), SH_UNT_C_10     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_10_V3_HMER_OR                                         , RULL(0x2A010A91), SH_UNT_C_10     , SH_ACS_SCOM2_OR  );
+REG64( C_11_V3_HMER_WAND                                       , RULL(0x2B010A95), SH_UNT_C_11     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_11_V3_HMER_OR                                         , RULL(0x2B010A91), SH_UNT_C_11     , SH_ACS_SCOM2_OR  );
+REG64( C_12_V3_HMER_WAND                                       , RULL(0x2C010A95), SH_UNT_C_12     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_12_V3_HMER_OR                                         , RULL(0x2C010A91), SH_UNT_C_12     , SH_ACS_SCOM2_OR  );
+REG64( C_13_V3_HMER_WAND                                       , RULL(0x2D010A95), SH_UNT_C_13     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_13_V3_HMER_OR                                         , RULL(0x2D010A91), SH_UNT_C_13     , SH_ACS_SCOM2_OR  );
+REG64( C_14_V3_HMER_WAND                                       , RULL(0x2E010A95), SH_UNT_C_14     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_14_V3_HMER_OR                                         , RULL(0x2E010A91), SH_UNT_C_14     , SH_ACS_SCOM2_OR  );
+REG64( C_15_V3_HMER_WAND                                       , RULL(0x2F010A95), SH_UNT_C_15     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_15_V3_HMER_OR                                         , RULL(0x2F010A91), SH_UNT_C_15     , SH_ACS_SCOM2_OR  );
+REG64( C_16_V3_HMER_WAND                                       , RULL(0x30010A95), SH_UNT_C_16     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_16_V3_HMER_OR                                         , RULL(0x30010A91), SH_UNT_C_16     , SH_ACS_SCOM2_OR  );
+REG64( C_17_V3_HMER_WAND                                       , RULL(0x31010A95), SH_UNT_C_17     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_17_V3_HMER_OR                                         , RULL(0x31010A91), SH_UNT_C_17     , SH_ACS_SCOM2_OR  );
+REG64( C_18_V3_HMER_WAND                                       , RULL(0x32010A95), SH_UNT_C_18     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_18_V3_HMER_OR                                         , RULL(0x32010A91), SH_UNT_C_18     , SH_ACS_SCOM2_OR  );
+REG64( C_19_V3_HMER_WAND                                       , RULL(0x33010A95), SH_UNT_C_19     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_19_V3_HMER_OR                                         , RULL(0x33010A91), SH_UNT_C_19     , SH_ACS_SCOM2_OR  );
+REG64( C_20_V3_HMER_WAND                                       , RULL(0x34010A95), SH_UNT_C_20     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_20_V3_HMER_OR                                         , RULL(0x34010A91), SH_UNT_C_20     , SH_ACS_SCOM2_OR  );
+REG64( C_21_V3_HMER_WAND                                       , RULL(0x35010A95), SH_UNT_C_21     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_21_V3_HMER_OR                                         , RULL(0x35010A91), SH_UNT_C_21     , SH_ACS_SCOM2_OR  );
+REG64( C_22_V3_HMER_WAND                                       , RULL(0x36010A95), SH_UNT_C_22     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_22_V3_HMER_OR                                         , RULL(0x36010A91), SH_UNT_C_22     , SH_ACS_SCOM2_OR  );
+REG64( C_23_V3_HMER_WAND                                       , RULL(0x37010A95), SH_UNT_C_23     ,
+       SH_ACS_SCOM1_WAND );
+REG64( C_23_V3_HMER_OR                                         , RULL(0x37010A91), SH_UNT_C_23     , SH_ACS_SCOM2_OR  );
+REG64( EX_0_L2_V3_HMER_WAND                                    , RULL(0x21010A95), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 20010A95,
+REG64( EX_0_L2_V3_HMER_OR                                      , RULL(0x21010A91), SH_UNT_EX_0_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 20010A91,
+REG64( EX_10_L2_V3_HMER_WAND                                   , RULL(0x35010A95), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 34010A95,
+REG64( EX_10_L2_V3_HMER_OR                                     , RULL(0x35010A91), SH_UNT_EX_10_L2 ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 34010A91,
+REG64( EX_11_L2_V3_HMER_WAND                                   , RULL(0x37010A95), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 36010A95,
+REG64( EX_11_L2_V3_HMER_OR                                     , RULL(0x37010A91), SH_UNT_EX_11_L2 ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 36010A91,
+REG64( EX_1_L2_V3_HMER_WAND                                    , RULL(0x23010A95), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 22010A95,
+REG64( EX_1_L2_V3_HMER_OR                                      , RULL(0x23010A91), SH_UNT_EX_1_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 22010A91,
+REG64( EX_2_L2_V3_HMER_WAND                                    , RULL(0x25010A95), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 24010A95,
+REG64( EX_2_L2_V3_HMER_OR                                      , RULL(0x25010A91), SH_UNT_EX_2_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 24010A91,
+REG64( EX_3_L2_V3_HMER_WAND                                    , RULL(0x27010A95), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 26010A95,
+REG64( EX_3_L2_V3_HMER_OR                                      , RULL(0x27010A91), SH_UNT_EX_3_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 26010A91,
+REG64( EX_4_L2_V3_HMER_WAND                                    , RULL(0x29010A95), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 28010A95,
+REG64( EX_4_L2_V3_HMER_OR                                      , RULL(0x29010A91), SH_UNT_EX_4_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 28010A91,
+REG64( EX_5_L2_V3_HMER_WAND                                    , RULL(0x2B010A95), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2A010A95,
+REG64( EX_5_L2_V3_HMER_OR                                      , RULL(0x2B010A91), SH_UNT_EX_5_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2A010A91,
+REG64( EX_6_L2_V3_HMER_WAND                                    , RULL(0x2D010A95), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2C010A95,
+REG64( EX_6_L2_V3_HMER_OR                                      , RULL(0x2D010A91), SH_UNT_EX_6_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2C010A91,
+REG64( EX_7_L2_V3_HMER_WAND                                    , RULL(0x2F010A95), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 2E010A95,
+REG64( EX_7_L2_V3_HMER_OR                                      , RULL(0x2F010A91), SH_UNT_EX_7_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 2E010A91,
+REG64( EX_8_L2_V3_HMER_WAND                                    , RULL(0x31010A95), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 30010A95,
+REG64( EX_8_L2_V3_HMER_OR                                      , RULL(0x31010A91), SH_UNT_EX_8_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 30010A91,
+REG64( EX_9_L2_V3_HMER_WAND                                    , RULL(0x33010A95), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 32010A95,
+REG64( EX_9_L2_V3_HMER_OR                                      , RULL(0x33010A91), SH_UNT_EX_9_L2  ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 32010A91,
+REG64( EX_L2_V3_HMER_WAND                                      , RULL(0x21010A95), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM1_WAND ); //DUPS: 20010A95,
+REG64( EX_L2_V3_HMER_OR                                        , RULL(0x21010A91), SH_UNT_EX_L2    ,
+       SH_ACS_SCOM2_OR  ); //DUPS: 20010A91,
+
+REG64( C_VITAL_SCAN_OUT                                        , RULL(0x200F0017), SH_UNT_C        , SH_ACS_SCOM_RO   );
+REG64( C_0_VITAL_SCAN_OUT                                      , RULL(0x200F0017), SH_UNT_C_0      , SH_ACS_SCOM_RO   );
+REG64( C_1_VITAL_SCAN_OUT                                      , RULL(0x210F0017), SH_UNT_C_1      , SH_ACS_SCOM_RO   );
+REG64( C_2_VITAL_SCAN_OUT                                      , RULL(0x220F0017), SH_UNT_C_2      , SH_ACS_SCOM_RO   );
+REG64( C_3_VITAL_SCAN_OUT                                      , RULL(0x230F0017), SH_UNT_C_3      , SH_ACS_SCOM_RO   );
+REG64( C_4_VITAL_SCAN_OUT                                      , RULL(0x240F0017), SH_UNT_C_4      , SH_ACS_SCOM_RO   );
+REG64( C_5_VITAL_SCAN_OUT                                      , RULL(0x250F0017), SH_UNT_C_5      , SH_ACS_SCOM_RO   );
+REG64( C_6_VITAL_SCAN_OUT                                      , RULL(0x260F0017), SH_UNT_C_6      , SH_ACS_SCOM_RO   );
+REG64( C_7_VITAL_SCAN_OUT                                      , RULL(0x270F0017), SH_UNT_C_7      , SH_ACS_SCOM_RO   );
+REG64( C_8_VITAL_SCAN_OUT                                      , RULL(0x280F0017), SH_UNT_C_8      , SH_ACS_SCOM_RO   );
+REG64( C_9_VITAL_SCAN_OUT                                      , RULL(0x290F0017), SH_UNT_C_9      , SH_ACS_SCOM_RO   );
+REG64( C_10_VITAL_SCAN_OUT                                     , RULL(0x2A0F0017), SH_UNT_C_10     , SH_ACS_SCOM_RO   );
+REG64( C_11_VITAL_SCAN_OUT                                     , RULL(0x2B0F0017), SH_UNT_C_11     , SH_ACS_SCOM_RO   );
+REG64( C_12_VITAL_SCAN_OUT                                     , RULL(0x2C0F0017), SH_UNT_C_12     , SH_ACS_SCOM_RO   );
+REG64( C_13_VITAL_SCAN_OUT                                     , RULL(0x2D0F0017), SH_UNT_C_13     , SH_ACS_SCOM_RO   );
+REG64( C_14_VITAL_SCAN_OUT                                     , RULL(0x2E0F0017), SH_UNT_C_14     , SH_ACS_SCOM_RO   );
+REG64( C_15_VITAL_SCAN_OUT                                     , RULL(0x2F0F0017), SH_UNT_C_15     , SH_ACS_SCOM_RO   );
+REG64( C_16_VITAL_SCAN_OUT                                     , RULL(0x300F0017), SH_UNT_C_16     , SH_ACS_SCOM_RO   );
+REG64( C_17_VITAL_SCAN_OUT                                     , RULL(0x310F0017), SH_UNT_C_17     , SH_ACS_SCOM_RO   );
+REG64( C_18_VITAL_SCAN_OUT                                     , RULL(0x320F0017), SH_UNT_C_18     , SH_ACS_SCOM_RO   );
+REG64( C_19_VITAL_SCAN_OUT                                     , RULL(0x330F0017), SH_UNT_C_19     , SH_ACS_SCOM_RO   );
+REG64( C_20_VITAL_SCAN_OUT                                     , RULL(0x340F0017), SH_UNT_C_20     , SH_ACS_SCOM_RO   );
+REG64( C_21_VITAL_SCAN_OUT                                     , RULL(0x350F0017), SH_UNT_C_21     , SH_ACS_SCOM_RO   );
+REG64( C_22_VITAL_SCAN_OUT                                     , RULL(0x360F0017), SH_UNT_C_22     , SH_ACS_SCOM_RO   );
+REG64( C_23_VITAL_SCAN_OUT                                     , RULL(0x370F0017), SH_UNT_C_23     , SH_ACS_SCOM_RO   );
+REG64( EQ_VITAL_SCAN_OUT                                       , RULL(0x100F0017), SH_UNT_EQ       , SH_ACS_SCOM_RO   );
+REG64( EQ_0_VITAL_SCAN_OUT                                     , RULL(0x100F0017), SH_UNT_EQ_0     , SH_ACS_SCOM_RO   );
+REG64( EQ_1_VITAL_SCAN_OUT                                     , RULL(0x110F0017), SH_UNT_EQ_1     , SH_ACS_SCOM_RO   );
+REG64( EQ_2_VITAL_SCAN_OUT                                     , RULL(0x120F0017), SH_UNT_EQ_2     , SH_ACS_SCOM_RO   );
+REG64( EQ_3_VITAL_SCAN_OUT                                     , RULL(0x130F0017), SH_UNT_EQ_3     , SH_ACS_SCOM_RO   );
+REG64( EQ_4_VITAL_SCAN_OUT                                     , RULL(0x140F0017), SH_UNT_EQ_4     , SH_ACS_SCOM_RO   );
+REG64( EQ_5_VITAL_SCAN_OUT                                     , RULL(0x150F0017), SH_UNT_EQ_5     , SH_ACS_SCOM_RO   );
+REG64( EX_VITAL_SCAN_OUT                                       , RULL(0x200F0017), SH_UNT_EX       ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F0017,
+REG64( EX_0_VITAL_SCAN_OUT                                     , RULL(0x200F0017), SH_UNT_EX_0     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 210F0017,
+REG64( EX_1_VITAL_SCAN_OUT                                     , RULL(0x230F0017), SH_UNT_EX_1     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 220F0017,
+REG64( EX_2_VITAL_SCAN_OUT                                     , RULL(0x240F0017), SH_UNT_EX_2     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 250F0017,
+REG64( EX_3_VITAL_SCAN_OUT                                     , RULL(0x260F0017), SH_UNT_EX_3     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 270F0017,
+REG64( EX_4_VITAL_SCAN_OUT                                     , RULL(0x280F0017), SH_UNT_EX_4     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 290F0017,
+REG64( EX_5_VITAL_SCAN_OUT                                     , RULL(0x2A0F0017), SH_UNT_EX_5     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2B0F0017,
+REG64( EX_6_VITAL_SCAN_OUT                                     , RULL(0x2C0F0017), SH_UNT_EX_6     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2D0F0017,
+REG64( EX_7_VITAL_SCAN_OUT                                     , RULL(0x2E0F0017), SH_UNT_EX_7     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 2F0F0017,
+REG64( EX_8_VITAL_SCAN_OUT                                     , RULL(0x300F0017), SH_UNT_EX_8     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 310F0017,
+REG64( EX_9_VITAL_SCAN_OUT                                     , RULL(0x320F0017), SH_UNT_EX_9     ,
+       SH_ACS_SCOM_RO   ); //DUPS: 330F0017,
+REG64( EX_10_VITAL_SCAN_OUT                                    , RULL(0x340F0017), SH_UNT_EX_10    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 350F0017,
+REG64( EX_11_VITAL_SCAN_OUT                                    , RULL(0x360F0017), SH_UNT_EX_11    ,
+       SH_ACS_SCOM_RO   ); //DUPS: 370F0017,
+
+REG64( C_WRITE_PROTECT_ENABLE_REG                              , RULL(0x20010005), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_WRITE_PROTECT_ENABLE_REG                            , RULL(0x20010005), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_WRITE_PROTECT_ENABLE_REG                            , RULL(0x21010005), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_WRITE_PROTECT_ENABLE_REG                            , RULL(0x22010005), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_WRITE_PROTECT_ENABLE_REG                            , RULL(0x23010005), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_WRITE_PROTECT_ENABLE_REG                            , RULL(0x24010005), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_WRITE_PROTECT_ENABLE_REG                            , RULL(0x25010005), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_WRITE_PROTECT_ENABLE_REG                            , RULL(0x26010005), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_WRITE_PROTECT_ENABLE_REG                            , RULL(0x27010005), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_WRITE_PROTECT_ENABLE_REG                            , RULL(0x28010005), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_WRITE_PROTECT_ENABLE_REG                            , RULL(0x29010005), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_WRITE_PROTECT_ENABLE_REG                           , RULL(0x2A010005), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_WRITE_PROTECT_ENABLE_REG                           , RULL(0x2B010005), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_WRITE_PROTECT_ENABLE_REG                           , RULL(0x2C010005), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_WRITE_PROTECT_ENABLE_REG                           , RULL(0x2D010005), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_WRITE_PROTECT_ENABLE_REG                           , RULL(0x2E010005), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_WRITE_PROTECT_ENABLE_REG                           , RULL(0x2F010005), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_WRITE_PROTECT_ENABLE_REG                           , RULL(0x30010005), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_WRITE_PROTECT_ENABLE_REG                           , RULL(0x31010005), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_WRITE_PROTECT_ENABLE_REG                           , RULL(0x32010005), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_WRITE_PROTECT_ENABLE_REG                           , RULL(0x33010005), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_WRITE_PROTECT_ENABLE_REG                           , RULL(0x34010005), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_WRITE_PROTECT_ENABLE_REG                           , RULL(0x35010005), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_WRITE_PROTECT_ENABLE_REG                           , RULL(0x36010005), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_WRITE_PROTECT_ENABLE_REG                           , RULL(0x37010005), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_WRITE_PROTECT_ENABLE_REG                             , RULL(0x10010005), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_WRITE_PROTECT_ENABLE_REG                           , RULL(0x10010005), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_WRITE_PROTECT_ENABLE_REG                           , RULL(0x11010005), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_WRITE_PROTECT_ENABLE_REG                           , RULL(0x12010005), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_WRITE_PROTECT_ENABLE_REG                           , RULL(0x13010005), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_WRITE_PROTECT_ENABLE_REG                           , RULL(0x14010005), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_WRITE_PROTECT_ENABLE_REG                           , RULL(0x15010005), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_WRITE_PROTECT_ENABLE_REG                             , RULL(0x20010005), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21010005,
+REG64( EX_0_WRITE_PROTECT_ENABLE_REG                           , RULL(0x20010005), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21010005,
+REG64( EX_1_WRITE_PROTECT_ENABLE_REG                           , RULL(0x22010005), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23010005,
+REG64( EX_2_WRITE_PROTECT_ENABLE_REG                           , RULL(0x24010005), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25010005,
+REG64( EX_3_WRITE_PROTECT_ENABLE_REG                           , RULL(0x26010005), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27010005,
+REG64( EX_4_WRITE_PROTECT_ENABLE_REG                           , RULL(0x28010005), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29010005,
+REG64( EX_5_WRITE_PROTECT_ENABLE_REG                           , RULL(0x2A010005), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B010005,
+REG64( EX_6_WRITE_PROTECT_ENABLE_REG                           , RULL(0x2C010005), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D010005,
+REG64( EX_7_WRITE_PROTECT_ENABLE_REG                           , RULL(0x2E010005), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F010005,
+REG64( EX_8_WRITE_PROTECT_ENABLE_REG                           , RULL(0x30010005), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31010005,
+REG64( EX_9_WRITE_PROTECT_ENABLE_REG                           , RULL(0x32010005), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33010005,
+REG64( EX_10_WRITE_PROTECT_ENABLE_REG                          , RULL(0x34010005), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35010005,
+REG64( EX_11_WRITE_PROTECT_ENABLE_REG                          , RULL(0x36010005), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37010005,
+
+REG64( C_WRITE_PROTECT_RINGS_REG                               , RULL(0x20010006), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_WRITE_PROTECT_RINGS_REG                             , RULL(0x20010006), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_WRITE_PROTECT_RINGS_REG                             , RULL(0x21010006), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_WRITE_PROTECT_RINGS_REG                             , RULL(0x22010006), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_WRITE_PROTECT_RINGS_REG                             , RULL(0x23010006), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_WRITE_PROTECT_RINGS_REG                             , RULL(0x24010006), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_WRITE_PROTECT_RINGS_REG                             , RULL(0x25010006), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_WRITE_PROTECT_RINGS_REG                             , RULL(0x26010006), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_WRITE_PROTECT_RINGS_REG                             , RULL(0x27010006), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_WRITE_PROTECT_RINGS_REG                             , RULL(0x28010006), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_WRITE_PROTECT_RINGS_REG                             , RULL(0x29010006), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_WRITE_PROTECT_RINGS_REG                            , RULL(0x2A010006), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_WRITE_PROTECT_RINGS_REG                            , RULL(0x2B010006), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_WRITE_PROTECT_RINGS_REG                            , RULL(0x2C010006), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_WRITE_PROTECT_RINGS_REG                            , RULL(0x2D010006), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_WRITE_PROTECT_RINGS_REG                            , RULL(0x2E010006), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_WRITE_PROTECT_RINGS_REG                            , RULL(0x2F010006), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_WRITE_PROTECT_RINGS_REG                            , RULL(0x30010006), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_WRITE_PROTECT_RINGS_REG                            , RULL(0x31010006), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_WRITE_PROTECT_RINGS_REG                            , RULL(0x32010006), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_WRITE_PROTECT_RINGS_REG                            , RULL(0x33010006), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_WRITE_PROTECT_RINGS_REG                            , RULL(0x34010006), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_WRITE_PROTECT_RINGS_REG                            , RULL(0x35010006), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_WRITE_PROTECT_RINGS_REG                            , RULL(0x36010006), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_WRITE_PROTECT_RINGS_REG                            , RULL(0x37010006), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_WRITE_PROTECT_RINGS_REG                              , RULL(0x10010006), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_WRITE_PROTECT_RINGS_REG                            , RULL(0x10010006), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_WRITE_PROTECT_RINGS_REG                            , RULL(0x11010006), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_WRITE_PROTECT_RINGS_REG                            , RULL(0x12010006), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_WRITE_PROTECT_RINGS_REG                            , RULL(0x13010006), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_WRITE_PROTECT_RINGS_REG                            , RULL(0x14010006), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_WRITE_PROTECT_RINGS_REG                            , RULL(0x15010006), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_WRITE_PROTECT_RINGS_REG                              , RULL(0x20010006), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21010006,
+REG64( EX_0_WRITE_PROTECT_RINGS_REG                            , RULL(0x20010006), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21010006,
+REG64( EX_1_WRITE_PROTECT_RINGS_REG                            , RULL(0x22010006), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23010006,
+REG64( EX_2_WRITE_PROTECT_RINGS_REG                            , RULL(0x24010006), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25010006,
+REG64( EX_3_WRITE_PROTECT_RINGS_REG                            , RULL(0x26010006), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27010006,
+REG64( EX_4_WRITE_PROTECT_RINGS_REG                            , RULL(0x28010006), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29010006,
+REG64( EX_5_WRITE_PROTECT_RINGS_REG                            , RULL(0x2A010006), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B010006,
+REG64( EX_6_WRITE_PROTECT_RINGS_REG                            , RULL(0x2C010006), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D010006,
+REG64( EX_7_WRITE_PROTECT_RINGS_REG                            , RULL(0x2E010006), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F010006,
+REG64( EX_8_WRITE_PROTECT_RINGS_REG                            , RULL(0x30010006), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31010006,
+REG64( EX_9_WRITE_PROTECT_RINGS_REG                            , RULL(0x32010006), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33010006,
+REG64( EX_10_WRITE_PROTECT_RINGS_REG                           , RULL(0x34010006), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35010006,
+REG64( EX_11_WRITE_PROTECT_RINGS_REG                           , RULL(0x36010006), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37010006,
+
+REG64( EQ_WR_EPS_REG                                           , RULL(0x10010811), SH_UNT_EQ       ,
+       SH_ACS_SCOM      ); //DUPS: 10010C11,
+REG64( EQ_0_WR_EPS_REG                                         , RULL(0x10010811), SH_UNT_EQ_0     ,
+       SH_ACS_SCOM      ); //DUPS: 10010C11,
+REG64( EQ_1_WR_EPS_REG                                         , RULL(0x11010811), SH_UNT_EQ_1     ,
+       SH_ACS_SCOM      ); //DUPS: 11010C11,
+REG64( EQ_2_WR_EPS_REG                                         , RULL(0x12010811), SH_UNT_EQ_2     ,
+       SH_ACS_SCOM      ); //DUPS: 12010C11,
+REG64( EQ_3_WR_EPS_REG                                         , RULL(0x13010811), SH_UNT_EQ_3     ,
+       SH_ACS_SCOM      ); //DUPS: 13010C11,
+REG64( EQ_4_WR_EPS_REG                                         , RULL(0x14010811), SH_UNT_EQ_4     ,
+       SH_ACS_SCOM      ); //DUPS: 14010C11,
+REG64( EQ_5_WR_EPS_REG                                         , RULL(0x15010811), SH_UNT_EQ_5     ,
+       SH_ACS_SCOM      ); //DUPS: 15010C11,
+REG64( EX_0_L2_WR_EPS_REG                                      , RULL(0x10010811), SH_UNT_EX_0_L2  , SH_ACS_SCOM      );
+REG64( EX_10_L2_WR_EPS_REG                                     , RULL(0x15010811), SH_UNT_EX_10_L2 , SH_ACS_SCOM      );
+REG64( EX_11_L2_WR_EPS_REG                                     , RULL(0x15010C11), SH_UNT_EX_11_L2 , SH_ACS_SCOM      );
+REG64( EX_1_L2_WR_EPS_REG                                      , RULL(0x10010C11), SH_UNT_EX_1_L2  , SH_ACS_SCOM      );
+REG64( EX_2_L2_WR_EPS_REG                                      , RULL(0x11010811), SH_UNT_EX_2_L2  , SH_ACS_SCOM      );
+REG64( EX_3_L2_WR_EPS_REG                                      , RULL(0x11010C11), SH_UNT_EX_3_L2  , SH_ACS_SCOM      );
+REG64( EX_4_L2_WR_EPS_REG                                      , RULL(0x12010811), SH_UNT_EX_4_L2  , SH_ACS_SCOM      );
+REG64( EX_5_L2_WR_EPS_REG                                      , RULL(0x12010C11), SH_UNT_EX_5_L2  , SH_ACS_SCOM      );
+REG64( EX_6_L2_WR_EPS_REG                                      , RULL(0x13010811), SH_UNT_EX_6_L2  , SH_ACS_SCOM      );
+REG64( EX_7_L2_WR_EPS_REG                                      , RULL(0x13010C11), SH_UNT_EX_7_L2  , SH_ACS_SCOM      );
+REG64( EX_8_L2_WR_EPS_REG                                      , RULL(0x14010811), SH_UNT_EX_8_L2  , SH_ACS_SCOM      );
+REG64( EX_9_L2_WR_EPS_REG                                      , RULL(0x14010C11), SH_UNT_EX_9_L2  , SH_ACS_SCOM      );
+REG64( EX_L2_WR_EPS_REG                                        , RULL(0x10010811), SH_UNT_EX_L2    , SH_ACS_SCOM      );
+
+REG64( C_XFIR                                                  , RULL(0x20040000), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_XFIR                                                , RULL(0x20040000), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_XFIR                                                , RULL(0x21040000), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_XFIR                                                , RULL(0x22040000), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_XFIR                                                , RULL(0x23040000), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_XFIR                                                , RULL(0x24040000), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_XFIR                                                , RULL(0x25040000), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_XFIR                                                , RULL(0x26040000), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_XFIR                                                , RULL(0x27040000), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_XFIR                                                , RULL(0x28040000), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_XFIR                                                , RULL(0x29040000), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_XFIR                                               , RULL(0x2A040000), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_XFIR                                               , RULL(0x2B040000), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_XFIR                                               , RULL(0x2C040000), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_XFIR                                               , RULL(0x2D040000), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_XFIR                                               , RULL(0x2E040000), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_XFIR                                               , RULL(0x2F040000), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_XFIR                                               , RULL(0x30040000), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_XFIR                                               , RULL(0x31040000), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_XFIR                                               , RULL(0x32040000), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_XFIR                                               , RULL(0x33040000), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_XFIR                                               , RULL(0x34040000), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_XFIR                                               , RULL(0x35040000), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_XFIR                                               , RULL(0x36040000), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_XFIR                                               , RULL(0x37040000), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_XFIR                                                 , RULL(0x10040000), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_XFIR                                               , RULL(0x10040000), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_XFIR                                               , RULL(0x11040000), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_XFIR                                               , RULL(0x12040000), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_XFIR                                               , RULL(0x13040000), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_XFIR                                               , RULL(0x14040000), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_XFIR                                               , RULL(0x15040000), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_XFIR                                                 , RULL(0x20040000), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 21040000,
+REG64( EX_0_XFIR                                               , RULL(0x20040000), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 21040000,
+REG64( EX_1_XFIR                                               , RULL(0x22040000), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 23040000,
+REG64( EX_2_XFIR                                               , RULL(0x24040000), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 25040000,
+REG64( EX_3_XFIR                                               , RULL(0x26040000), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 27040000,
+REG64( EX_4_XFIR                                               , RULL(0x28040000), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 29040000,
+REG64( EX_5_XFIR                                               , RULL(0x2A040000), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B040000,
+REG64( EX_6_XFIR                                               , RULL(0x2C040000), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D040000,
+REG64( EX_7_XFIR                                               , RULL(0x2E040000), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F040000,
+REG64( EX_8_XFIR                                               , RULL(0x30040000), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 31040000,
+REG64( EX_9_XFIR                                               , RULL(0x32040000), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 33040000,
+REG64( EX_10_XFIR                                              , RULL(0x34040000), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 35040000,
+REG64( EX_11_XFIR                                              , RULL(0x36040000), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 37040000,
+
+REG64( C_XSTOP1                                                , RULL(0x2003000C), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_XSTOP1                                              , RULL(0x2003000C), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_XSTOP1                                              , RULL(0x2103000C), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_XSTOP1                                              , RULL(0x2203000C), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_XSTOP1                                              , RULL(0x2303000C), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_XSTOP1                                              , RULL(0x2403000C), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_XSTOP1                                              , RULL(0x2503000C), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_XSTOP1                                              , RULL(0x2603000C), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_XSTOP1                                              , RULL(0x2703000C), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_XSTOP1                                              , RULL(0x2803000C), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_XSTOP1                                              , RULL(0x2903000C), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_XSTOP1                                             , RULL(0x2A03000C), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_XSTOP1                                             , RULL(0x2B03000C), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_XSTOP1                                             , RULL(0x2C03000C), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_XSTOP1                                             , RULL(0x2D03000C), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_XSTOP1                                             , RULL(0x2E03000C), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_XSTOP1                                             , RULL(0x2F03000C), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_XSTOP1                                             , RULL(0x3003000C), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_XSTOP1                                             , RULL(0x3103000C), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_XSTOP1                                             , RULL(0x3203000C), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_XSTOP1                                             , RULL(0x3303000C), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_XSTOP1                                             , RULL(0x3403000C), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_XSTOP1                                             , RULL(0x3503000C), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_XSTOP1                                             , RULL(0x3603000C), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_XSTOP1                                             , RULL(0x3703000C), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_XSTOP1                                               , RULL(0x1003000C), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_XSTOP1                                             , RULL(0x1003000C), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_XSTOP1                                             , RULL(0x1103000C), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_XSTOP1                                             , RULL(0x1203000C), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_XSTOP1                                             , RULL(0x1303000C), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_XSTOP1                                             , RULL(0x1403000C), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_XSTOP1                                             , RULL(0x1503000C), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_XSTOP1                                               , RULL(0x2003000C), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 2103000C,
+REG64( EX_0_XSTOP1                                             , RULL(0x2003000C), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 2103000C,
+REG64( EX_1_XSTOP1                                             , RULL(0x2203000C), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 2303000C,
+REG64( EX_2_XSTOP1                                             , RULL(0x2403000C), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 2503000C,
+REG64( EX_3_XSTOP1                                             , RULL(0x2603000C), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 2703000C,
+REG64( EX_4_XSTOP1                                             , RULL(0x2803000C), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 2903000C,
+REG64( EX_5_XSTOP1                                             , RULL(0x2A03000C), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B03000C,
+REG64( EX_6_XSTOP1                                             , RULL(0x2C03000C), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D03000C,
+REG64( EX_7_XSTOP1                                             , RULL(0x2E03000C), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F03000C,
+REG64( EX_8_XSTOP1                                             , RULL(0x3003000C), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 3103000C,
+REG64( EX_9_XSTOP1                                             , RULL(0x3203000C), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 3303000C,
+REG64( EX_10_XSTOP1                                            , RULL(0x3403000C), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 3503000C,
+REG64( EX_11_XSTOP1                                            , RULL(0x3603000C), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 3703000C,
+
+REG64( C_XSTOP2                                                , RULL(0x2003000D), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_XSTOP2                                              , RULL(0x2003000D), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_XSTOP2                                              , RULL(0x2103000D), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_XSTOP2                                              , RULL(0x2203000D), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_XSTOP2                                              , RULL(0x2303000D), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_XSTOP2                                              , RULL(0x2403000D), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_XSTOP2                                              , RULL(0x2503000D), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_XSTOP2                                              , RULL(0x2603000D), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_XSTOP2                                              , RULL(0x2703000D), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_XSTOP2                                              , RULL(0x2803000D), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_XSTOP2                                              , RULL(0x2903000D), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_XSTOP2                                             , RULL(0x2A03000D), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_XSTOP2                                             , RULL(0x2B03000D), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_XSTOP2                                             , RULL(0x2C03000D), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_XSTOP2                                             , RULL(0x2D03000D), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_XSTOP2                                             , RULL(0x2E03000D), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_XSTOP2                                             , RULL(0x2F03000D), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_XSTOP2                                             , RULL(0x3003000D), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_XSTOP2                                             , RULL(0x3103000D), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_XSTOP2                                             , RULL(0x3203000D), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_XSTOP2                                             , RULL(0x3303000D), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_XSTOP2                                             , RULL(0x3403000D), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_XSTOP2                                             , RULL(0x3503000D), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_XSTOP2                                             , RULL(0x3603000D), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_XSTOP2                                             , RULL(0x3703000D), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_XSTOP2                                               , RULL(0x1003000D), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_XSTOP2                                             , RULL(0x1003000D), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_XSTOP2                                             , RULL(0x1103000D), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_XSTOP2                                             , RULL(0x1203000D), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_XSTOP2                                             , RULL(0x1303000D), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_XSTOP2                                             , RULL(0x1403000D), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_XSTOP2                                             , RULL(0x1503000D), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_XSTOP2                                               , RULL(0x2003000D), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 2103000D,
+REG64( EX_0_XSTOP2                                             , RULL(0x2003000D), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 2103000D,
+REG64( EX_1_XSTOP2                                             , RULL(0x2203000D), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 2303000D,
+REG64( EX_2_XSTOP2                                             , RULL(0x2403000D), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 2503000D,
+REG64( EX_3_XSTOP2                                             , RULL(0x2603000D), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 2703000D,
+REG64( EX_4_XSTOP2                                             , RULL(0x2803000D), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 2903000D,
+REG64( EX_5_XSTOP2                                             , RULL(0x2A03000D), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B03000D,
+REG64( EX_6_XSTOP2                                             , RULL(0x2C03000D), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D03000D,
+REG64( EX_7_XSTOP2                                             , RULL(0x2E03000D), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F03000D,
+REG64( EX_8_XSTOP2                                             , RULL(0x3003000D), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 3103000D,
+REG64( EX_9_XSTOP2                                             , RULL(0x3203000D), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 3303000D,
+REG64( EX_10_XSTOP2                                            , RULL(0x3403000D), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 3503000D,
+REG64( EX_11_XSTOP2                                            , RULL(0x3603000D), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 3703000D,
+
+REG64( C_XSTOP3                                                , RULL(0x2003000E), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_XSTOP3                                              , RULL(0x2003000E), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_XSTOP3                                              , RULL(0x2103000E), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_XSTOP3                                              , RULL(0x2203000E), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_XSTOP3                                              , RULL(0x2303000E), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_XSTOP3                                              , RULL(0x2403000E), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_XSTOP3                                              , RULL(0x2503000E), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_XSTOP3                                              , RULL(0x2603000E), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_XSTOP3                                              , RULL(0x2703000E), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_XSTOP3                                              , RULL(0x2803000E), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_XSTOP3                                              , RULL(0x2903000E), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_XSTOP3                                             , RULL(0x2A03000E), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_XSTOP3                                             , RULL(0x2B03000E), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_XSTOP3                                             , RULL(0x2C03000E), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_XSTOP3                                             , RULL(0x2D03000E), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_XSTOP3                                             , RULL(0x2E03000E), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_XSTOP3                                             , RULL(0x2F03000E), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_XSTOP3                                             , RULL(0x3003000E), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_XSTOP3                                             , RULL(0x3103000E), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_XSTOP3                                             , RULL(0x3203000E), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_XSTOP3                                             , RULL(0x3303000E), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_XSTOP3                                             , RULL(0x3403000E), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_XSTOP3                                             , RULL(0x3503000E), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_XSTOP3                                             , RULL(0x3603000E), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_XSTOP3                                             , RULL(0x3703000E), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_XSTOP3                                               , RULL(0x1003000E), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_XSTOP3                                             , RULL(0x1003000E), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_XSTOP3                                             , RULL(0x1103000E), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_XSTOP3                                             , RULL(0x1203000E), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_XSTOP3                                             , RULL(0x1303000E), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_XSTOP3                                             , RULL(0x1403000E), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_XSTOP3                                             , RULL(0x1503000E), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_XSTOP3                                               , RULL(0x2003000E), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 2103000E,
+REG64( EX_0_XSTOP3                                             , RULL(0x2003000E), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 2103000E,
+REG64( EX_1_XSTOP3                                             , RULL(0x2203000E), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 2303000E,
+REG64( EX_2_XSTOP3                                             , RULL(0x2403000E), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 2503000E,
+REG64( EX_3_XSTOP3                                             , RULL(0x2603000E), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 2703000E,
+REG64( EX_4_XSTOP3                                             , RULL(0x2803000E), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 2903000E,
+REG64( EX_5_XSTOP3                                             , RULL(0x2A03000E), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B03000E,
+REG64( EX_6_XSTOP3                                             , RULL(0x2C03000E), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D03000E,
+REG64( EX_7_XSTOP3                                             , RULL(0x2E03000E), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F03000E,
+REG64( EX_8_XSTOP3                                             , RULL(0x3003000E), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 3103000E,
+REG64( EX_9_XSTOP3                                             , RULL(0x3203000E), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 3303000E,
+REG64( EX_10_XSTOP3                                            , RULL(0x3403000E), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 3503000E,
+REG64( EX_11_XSTOP3                                            , RULL(0x3603000E), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 3703000E,
+
+REG64( C_XSTOP_INTERRUPT_REG                                   , RULL(0x200F001C), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_XSTOP_INTERRUPT_REG                                 , RULL(0x200F001C), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_XSTOP_INTERRUPT_REG                                 , RULL(0x210F001C), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_XSTOP_INTERRUPT_REG                                 , RULL(0x220F001C), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_XSTOP_INTERRUPT_REG                                 , RULL(0x230F001C), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_XSTOP_INTERRUPT_REG                                 , RULL(0x240F001C), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_XSTOP_INTERRUPT_REG                                 , RULL(0x250F001C), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_XSTOP_INTERRUPT_REG                                 , RULL(0x260F001C), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_XSTOP_INTERRUPT_REG                                 , RULL(0x270F001C), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_XSTOP_INTERRUPT_REG                                 , RULL(0x280F001C), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_XSTOP_INTERRUPT_REG                                 , RULL(0x290F001C), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_XSTOP_INTERRUPT_REG                                , RULL(0x2A0F001C), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_XSTOP_INTERRUPT_REG                                , RULL(0x2B0F001C), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_XSTOP_INTERRUPT_REG                                , RULL(0x2C0F001C), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_XSTOP_INTERRUPT_REG                                , RULL(0x2D0F001C), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_XSTOP_INTERRUPT_REG                                , RULL(0x2E0F001C), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_XSTOP_INTERRUPT_REG                                , RULL(0x2F0F001C), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_XSTOP_INTERRUPT_REG                                , RULL(0x300F001C), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_XSTOP_INTERRUPT_REG                                , RULL(0x310F001C), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_XSTOP_INTERRUPT_REG                                , RULL(0x320F001C), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_XSTOP_INTERRUPT_REG                                , RULL(0x330F001C), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_XSTOP_INTERRUPT_REG                                , RULL(0x340F001C), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_XSTOP_INTERRUPT_REG                                , RULL(0x350F001C), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_XSTOP_INTERRUPT_REG                                , RULL(0x360F001C), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_XSTOP_INTERRUPT_REG                                , RULL(0x370F001C), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_XSTOP_INTERRUPT_REG                                  , RULL(0x100F001C), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_XSTOP_INTERRUPT_REG                                , RULL(0x100F001C), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_XSTOP_INTERRUPT_REG                                , RULL(0x110F001C), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_XSTOP_INTERRUPT_REG                                , RULL(0x120F001C), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_XSTOP_INTERRUPT_REG                                , RULL(0x130F001C), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_XSTOP_INTERRUPT_REG                                , RULL(0x140F001C), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_XSTOP_INTERRUPT_REG                                , RULL(0x150F001C), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_XSTOP_INTERRUPT_REG                                  , RULL(0x200F001C), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210F001C,
+REG64( EX_0_XSTOP_INTERRUPT_REG                                , RULL(0x200F001C), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210F001C,
+REG64( EX_1_XSTOP_INTERRUPT_REG                                , RULL(0x230F001C), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 220F001C,
+REG64( EX_2_XSTOP_INTERRUPT_REG                                , RULL(0x240F001C), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250F001C,
+REG64( EX_3_XSTOP_INTERRUPT_REG                                , RULL(0x260F001C), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270F001C,
+REG64( EX_4_XSTOP_INTERRUPT_REG                                , RULL(0x280F001C), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290F001C,
+REG64( EX_5_XSTOP_INTERRUPT_REG                                , RULL(0x2A0F001C), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0F001C,
+REG64( EX_6_XSTOP_INTERRUPT_REG                                , RULL(0x2C0F001C), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0F001C,
+REG64( EX_7_XSTOP_INTERRUPT_REG                                , RULL(0x2E0F001C), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0F001C,
+REG64( EX_8_XSTOP_INTERRUPT_REG                                , RULL(0x300F001C), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310F001C,
+REG64( EX_9_XSTOP_INTERRUPT_REG                                , RULL(0x320F001C), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330F001C,
+REG64( EX_10_XSTOP_INTERRUPT_REG                               , RULL(0x340F001C), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350F001C,
+REG64( EX_11_XSTOP_INTERRUPT_REG                               , RULL(0x360F001C), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370F001C,
+
+REG64( C_XTRA_TRACE_MODE                                       , RULL(0x200107D1), SH_UNT_C        , SH_ACS_SCOM      );
+REG64( C_0_XTRA_TRACE_MODE                                     , RULL(0x200107D1), SH_UNT_C_0      , SH_ACS_SCOM      );
+REG64( C_1_XTRA_TRACE_MODE                                     , RULL(0x210107D1), SH_UNT_C_1      , SH_ACS_SCOM      );
+REG64( C_2_XTRA_TRACE_MODE                                     , RULL(0x220107D1), SH_UNT_C_2      , SH_ACS_SCOM      );
+REG64( C_3_XTRA_TRACE_MODE                                     , RULL(0x230107D1), SH_UNT_C_3      , SH_ACS_SCOM      );
+REG64( C_4_XTRA_TRACE_MODE                                     , RULL(0x240107D1), SH_UNT_C_4      , SH_ACS_SCOM      );
+REG64( C_5_XTRA_TRACE_MODE                                     , RULL(0x250107D1), SH_UNT_C_5      , SH_ACS_SCOM      );
+REG64( C_6_XTRA_TRACE_MODE                                     , RULL(0x260107D1), SH_UNT_C_6      , SH_ACS_SCOM      );
+REG64( C_7_XTRA_TRACE_MODE                                     , RULL(0x270107D1), SH_UNT_C_7      , SH_ACS_SCOM      );
+REG64( C_8_XTRA_TRACE_MODE                                     , RULL(0x280107D1), SH_UNT_C_8      , SH_ACS_SCOM      );
+REG64( C_9_XTRA_TRACE_MODE                                     , RULL(0x290107D1), SH_UNT_C_9      , SH_ACS_SCOM      );
+REG64( C_10_XTRA_TRACE_MODE                                    , RULL(0x2A0107D1), SH_UNT_C_10     , SH_ACS_SCOM      );
+REG64( C_11_XTRA_TRACE_MODE                                    , RULL(0x2B0107D1), SH_UNT_C_11     , SH_ACS_SCOM      );
+REG64( C_12_XTRA_TRACE_MODE                                    , RULL(0x2C0107D1), SH_UNT_C_12     , SH_ACS_SCOM      );
+REG64( C_13_XTRA_TRACE_MODE                                    , RULL(0x2D0107D1), SH_UNT_C_13     , SH_ACS_SCOM      );
+REG64( C_14_XTRA_TRACE_MODE                                    , RULL(0x2E0107D1), SH_UNT_C_14     , SH_ACS_SCOM      );
+REG64( C_15_XTRA_TRACE_MODE                                    , RULL(0x2F0107D1), SH_UNT_C_15     , SH_ACS_SCOM      );
+REG64( C_16_XTRA_TRACE_MODE                                    , RULL(0x300107D1), SH_UNT_C_16     , SH_ACS_SCOM      );
+REG64( C_17_XTRA_TRACE_MODE                                    , RULL(0x310107D1), SH_UNT_C_17     , SH_ACS_SCOM      );
+REG64( C_18_XTRA_TRACE_MODE                                    , RULL(0x320107D1), SH_UNT_C_18     , SH_ACS_SCOM      );
+REG64( C_19_XTRA_TRACE_MODE                                    , RULL(0x330107D1), SH_UNT_C_19     , SH_ACS_SCOM      );
+REG64( C_20_XTRA_TRACE_MODE                                    , RULL(0x340107D1), SH_UNT_C_20     , SH_ACS_SCOM      );
+REG64( C_21_XTRA_TRACE_MODE                                    , RULL(0x350107D1), SH_UNT_C_21     , SH_ACS_SCOM      );
+REG64( C_22_XTRA_TRACE_MODE                                    , RULL(0x360107D1), SH_UNT_C_22     , SH_ACS_SCOM      );
+REG64( C_23_XTRA_TRACE_MODE                                    , RULL(0x370107D1), SH_UNT_C_23     , SH_ACS_SCOM      );
+REG64( EQ_XTRA_TRACE_MODE                                      , RULL(0x100107D1), SH_UNT_EQ       , SH_ACS_SCOM      );
+REG64( EQ_0_XTRA_TRACE_MODE                                    , RULL(0x100107D1), SH_UNT_EQ_0     , SH_ACS_SCOM      );
+REG64( EQ_1_XTRA_TRACE_MODE                                    , RULL(0x110107D1), SH_UNT_EQ_1     , SH_ACS_SCOM      );
+REG64( EQ_2_XTRA_TRACE_MODE                                    , RULL(0x120107D1), SH_UNT_EQ_2     , SH_ACS_SCOM      );
+REG64( EQ_3_XTRA_TRACE_MODE                                    , RULL(0x130107D1), SH_UNT_EQ_3     , SH_ACS_SCOM      );
+REG64( EQ_4_XTRA_TRACE_MODE                                    , RULL(0x140107D1), SH_UNT_EQ_4     , SH_ACS_SCOM      );
+REG64( EQ_5_XTRA_TRACE_MODE                                    , RULL(0x150107D1), SH_UNT_EQ_5     , SH_ACS_SCOM      );
+REG64( EX_XTRA_TRACE_MODE                                      , RULL(0x200107D1), SH_UNT_EX       ,
+       SH_ACS_SCOM      ); //DUPS: 210107D1,
+REG64( EX_0_XTRA_TRACE_MODE                                    , RULL(0x200107D1), SH_UNT_EX_0     ,
+       SH_ACS_SCOM      ); //DUPS: 210107D1,
+REG64( EX_1_XTRA_TRACE_MODE                                    , RULL(0x220107D1), SH_UNT_EX_1     ,
+       SH_ACS_SCOM      ); //DUPS: 230107D1,
+REG64( EX_2_XTRA_TRACE_MODE                                    , RULL(0x240107D1), SH_UNT_EX_2     ,
+       SH_ACS_SCOM      ); //DUPS: 250107D1,
+REG64( EX_3_XTRA_TRACE_MODE                                    , RULL(0x260107D1), SH_UNT_EX_3     ,
+       SH_ACS_SCOM      ); //DUPS: 270107D1,
+REG64( EX_4_XTRA_TRACE_MODE                                    , RULL(0x280107D1), SH_UNT_EX_4     ,
+       SH_ACS_SCOM      ); //DUPS: 290107D1,
+REG64( EX_5_XTRA_TRACE_MODE                                    , RULL(0x2A0107D1), SH_UNT_EX_5     ,
+       SH_ACS_SCOM      ); //DUPS: 2B0107D1,
+REG64( EX_6_XTRA_TRACE_MODE                                    , RULL(0x2C0107D1), SH_UNT_EX_6     ,
+       SH_ACS_SCOM      ); //DUPS: 2D0107D1,
+REG64( EX_7_XTRA_TRACE_MODE                                    , RULL(0x2E0107D1), SH_UNT_EX_7     ,
+       SH_ACS_SCOM      ); //DUPS: 2F0107D1,
+REG64( EX_8_XTRA_TRACE_MODE                                    , RULL(0x300107D1), SH_UNT_EX_8     ,
+       SH_ACS_SCOM      ); //DUPS: 310107D1,
+REG64( EX_9_XTRA_TRACE_MODE                                    , RULL(0x320107D1), SH_UNT_EX_9     ,
+       SH_ACS_SCOM      ); //DUPS: 330107D1,
+REG64( EX_10_XTRA_TRACE_MODE                                   , RULL(0x340107D1), SH_UNT_EX_10    ,
+       SH_ACS_SCOM      ); //DUPS: 350107D1,
+REG64( EX_11_XTRA_TRACE_MODE                                   , RULL(0x360107D1), SH_UNT_EX_11    ,
+       SH_ACS_SCOM      ); //DUPS: 370107D1,
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9_quad_scom_addresses_fixes.H b/src/import/chips/p9/common/include/p9_quad_scom_addresses_fixes.H
new file mode 100644
index 00000000..5e132947
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_quad_scom_addresses_fixes.H
@@ -0,0 +1,68 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_quad_scom_addresses_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file quad_scom_addresses_fixes.H
+/// @brief The *scom_addresses.H files are  generated form figtree, but
+///        the figree can be wrong.  This file is included at the end
+///        of scom_addresses.H and allows incorrect constants to be
+///        fixed manually.
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SAO
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __P9_QUAD_SCOM_ADDRESSES_FIXES_H
+#define __P9_QUAD_SCOM_ADDRESSES_FIXES_H
+
+//Example,
+//Copy the whole line from the *scom_addresses.H file.  Then add
+//FIX in front of REG, and add another paramter that is the new
+//corrected value.
+//FIXREG64( PU_ALTD_ADDR_REG,
+//          RULL(0x05022800), SH_UNT, SH_ACS_SCOM,
+//          RULL(0x00090000)
+//        );
+
+//L2 laoder
+REG64( EQ_QPPM_QACCR_SCOM2                                     , RULL(0x100F0162), SH_UNT_EQ       , SH_ACS_SCOM2     );
+REG64( EQ_PPM_CGCR_OR                                          , RULL(0x100F0167), SH_UNT_EQ       , SH_ACS_SCOM2_OR  );
+
+REG64( EQ_PPM_CGCR_CLEAR                                       , RULL(0x100F0166), SH_UNT_EQ       ,
+       SH_ACS_SCOM1_CLEAR );
+
+REG64( C_PPM_CGCR_CLEAR                                        , RULL(0x200F0166), SH_UNT_C        ,
+       SH_ACS_SCOM1_CLEAR );
+
+REG64( C_PPM_CGCR_OR                                           , RULL(0x200F0167), SH_UNT_C        , SH_ACS_SCOM2_OR  );
+
+FIXREG64( EQ_TPLC20_TR0_TRACE_HI_DATA_REG, RULL(0x10012800), SH_UNT_EQ, SH_ACS_SCOM_RO, RULL(0x10012900));
+FIXREG64( EQ_TPLC20_TR1_TRACE_HI_DATA_REG, RULL(0x10012840), SH_UNT_EQ, SH_ACS_SCOM_RO, RULL(0x10012940));
+FIXREG64( EQ_TPLC21_TR0_TRACE_HI_DATA_REG, RULL(0x10012C00), SH_UNT_EQ, SH_ACS_SCOM_RO, RULL(0x10012D00));
+FIXREG64( EQ_TPLC21_TR1_TRACE_HI_DATA_REG, RULL(0x10012C40), SH_UNT_EQ, SH_ACS_SCOM_RO, RULL(0x10012D40));
+
+
+#endif
diff --git a/src/import/chips/p9/common/include/p9_quad_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_quad_scom_addresses_fld.H
new file mode 100644
index 00000000..80fc95e8
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_quad_scom_addresses_fld.H
@@ -0,0 +1,15610 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_quad_scom_addresses_fld.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_quad_scom_addresses_fld.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#include <p9_const_common.H>
+
+#ifndef __P9_QUAD_SCOM_ADDRESSES_FLD_H
+#define __P9_QUAD_SCOM_ADDRESSES_FLD_H
+
+
+#include <p9_scom_template_consts.H>
+#include <p9_quad_scom_addresses_fld_fixes.H>
+
+REG64_FLD( EQ_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( EQ_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN );
+REG64_FLD( EQ_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( EQ_ADDR_TRAP_REG_RESERVED_LAST_LT                       , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LAST_LT );
+REG64_FLD( EQ_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR );
+REG64_FLD( EQ_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13  , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN );
+REG64_FLD( EQ_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY );
+REG64_FLD( EQ_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR );
+REG64_FLD( EQ_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION );
+REG64_FLD( EQ_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER );
+
+REG64_FLD( EX_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( EX_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN );
+REG64_FLD( EX_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( EX_ADDR_TRAP_REG_RESERVED_LAST_LT                       , 17  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LAST_LT );
+REG64_FLD( EX_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR );
+REG64_FLD( EX_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13  , SH_UNT_EX       ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN );
+REG64_FLD( EX_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY );
+REG64_FLD( EX_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR );
+REG64_FLD( EX_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION );
+REG64_FLD( EX_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER );
+
+REG64_FLD( C_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( C_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN );
+REG64_FLD( C_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR );
+REG64_FLD( C_ADDR_TRAP_REG_RESERVED_LAST_LT                        , 17  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LAST_LT );
+REG64_FLD( C_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR );
+REG64_FLD( C_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13  , SH_UNT_C        ,
+           SH_ACS_SCOM     , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN );
+REG64_FLD( C_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY );
+REG64_FLD( C_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR );
+REG64_FLD( C_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION );
+REG64_FLD( C_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER );
+
+REG64_FLD( EQ_ATOMIC_LOCK_MASK_LATCH_REG_MASK                      , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASK       );
+REG64_FLD( EQ_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN                  , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( EX_ATOMIC_LOCK_MASK_LATCH_REG_MASK                      , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASK       );
+REG64_FLD( EX_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN                  , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( C_ATOMIC_LOCK_MASK_LATCH_REG_MASK                       , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MASK       );
+REG64_FLD( C_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN                   , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( EQ_ATOMIC_LOCK_REG_ENABLE                               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( EQ_ATOMIC_LOCK_REG_ID                                   , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( EQ_ATOMIC_LOCK_REG_ID_LEN                               , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ID_LEN     );
+REG64_FLD( EQ_ATOMIC_LOCK_REG_ACTIVITY                             , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY   );
+REG64_FLD( EQ_ATOMIC_LOCK_REG_ACTIVITY_LEN                         , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( EX_ATOMIC_LOCK_REG_ENABLE                               , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( EX_ATOMIC_LOCK_REG_ID                                   , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( EX_ATOMIC_LOCK_REG_ID_LEN                               , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ID_LEN     );
+REG64_FLD( EX_ATOMIC_LOCK_REG_ACTIVITY                             , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY   );
+REG64_FLD( EX_ATOMIC_LOCK_REG_ACTIVITY_LEN                         , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( C_ATOMIC_LOCK_REG_ENABLE                                , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( C_ATOMIC_LOCK_REG_ID                                    , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( C_ATOMIC_LOCK_REG_ID_LEN                                , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ID_LEN     );
+REG64_FLD( C_ATOMIC_LOCK_REG_ACTIVITY                              , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY   );
+REG64_FLD( C_ATOMIC_LOCK_REG_ACTIVITY_LEN                          , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( EQ_BIST_TC_START_TEST_DC                                , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TC_START_TEST_DC );
+REG64_FLD( EQ_BIST_TC_SRAM_ABIST_MODE_DC                           , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TC_SRAM_ABIST_MODE_DC );
+REG64_FLD( EQ_BIST_TC_EDRAM_ABIST_MODE_DC                          , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TC_EDRAM_ABIST_MODE_DC );
+REG64_FLD( EQ_BIST_TC_IOBIST_MODE_DC                               , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TC_IOBIST_MODE_DC );
+REG64_FLD( EQ_BIST_PERV                                            , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( EQ_BIST_UNIT1                                           , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( EQ_BIST_UNIT2                                           , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( EQ_BIST_UNIT3                                           , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( EQ_BIST_UNIT4                                           , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( EQ_BIST_UNIT5                                           , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( EQ_BIST_UNIT6                                           , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( EQ_BIST_UNIT7                                           , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( EQ_BIST_UNIT8                                           , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( EQ_BIST_UNIT9                                           , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( EQ_BIST_UNIT10                                          , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( EQ_BIST_STROBE_WINDOW_EN                                , 48  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STROBE_WINDOW_EN );
+
+REG64_FLD( EX_BIST_TC_START_TEST_DC                                , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TC_START_TEST_DC );
+REG64_FLD( EX_BIST_TC_SRAM_ABIST_MODE_DC                           , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TC_SRAM_ABIST_MODE_DC );
+REG64_FLD( EX_BIST_TC_EDRAM_ABIST_MODE_DC                          , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TC_EDRAM_ABIST_MODE_DC );
+REG64_FLD( EX_BIST_TC_IOBIST_MODE_DC                               , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TC_IOBIST_MODE_DC );
+REG64_FLD( EX_BIST_PERV                                            , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( EX_BIST_UNIT1                                           , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( EX_BIST_UNIT2                                           , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( EX_BIST_UNIT3                                           , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( EX_BIST_UNIT4                                           , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( EX_BIST_UNIT5                                           , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( EX_BIST_UNIT6                                           , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( EX_BIST_UNIT7                                           , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( EX_BIST_UNIT8                                           , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( EX_BIST_UNIT9                                           , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( EX_BIST_UNIT10                                          , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( EX_BIST_STROBE_WINDOW_EN                                , 48  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STROBE_WINDOW_EN );
+
+REG64_FLD( C_BIST_TC_START_TEST_DC                                 , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TC_START_TEST_DC );
+REG64_FLD( C_BIST_TC_SRAM_ABIST_MODE_DC                            , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TC_SRAM_ABIST_MODE_DC );
+REG64_FLD( C_BIST_TC_EDRAM_ABIST_MODE_DC                           , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TC_EDRAM_ABIST_MODE_DC );
+REG64_FLD( C_BIST_TC_IOBIST_MODE_DC                                , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TC_IOBIST_MODE_DC );
+REG64_FLD( C_BIST_PERV                                             , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( C_BIST_UNIT1                                            , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( C_BIST_UNIT2                                            , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( C_BIST_UNIT3                                            , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( C_BIST_UNIT4                                            , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( C_BIST_UNIT5                                            , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( C_BIST_UNIT6                                            , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( C_BIST_UNIT7                                            , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( C_BIST_UNIT8                                            , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( C_BIST_UNIT9                                            , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( C_BIST_UNIT10                                           , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( C_BIST_STROBE_WINDOW_EN                                 , 48  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STROBE_WINDOW_EN );
+
+REG64_FLD( EQ_CC_ATOMIC_LOCK_REG_ENABLE                            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( EQ_CC_ATOMIC_LOCK_REG_ID                                , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( EQ_CC_ATOMIC_LOCK_REG_ID_LEN                            , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ID_LEN     );
+REG64_FLD( EQ_CC_ATOMIC_LOCK_REG_ACTIVITY                          , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY   );
+REG64_FLD( EQ_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN                      , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( EX_CC_ATOMIC_LOCK_REG_ENABLE                            , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( EX_CC_ATOMIC_LOCK_REG_ID                                , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( EX_CC_ATOMIC_LOCK_REG_ID_LEN                            , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ID_LEN     );
+REG64_FLD( EX_CC_ATOMIC_LOCK_REG_ACTIVITY                          , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY   );
+REG64_FLD( EX_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN                      , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( C_CC_ATOMIC_LOCK_REG_ENABLE                             , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( C_CC_ATOMIC_LOCK_REG_ID                                 , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( C_CC_ATOMIC_LOCK_REG_ID_LEN                             , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ID_LEN     );
+REG64_FLD( C_CC_ATOMIC_LOCK_REG_ACTIVITY                           , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY   );
+REG64_FLD( C_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN                       , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( EQ_CC_PROTECT_MODE_REG_READ_ENABLE                      , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_READ_ENABLE );
+REG64_FLD( EQ_CC_PROTECT_MODE_REG_WRITE_ENABLE                     , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( EX_CC_PROTECT_MODE_REG_READ_ENABLE                      , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_READ_ENABLE );
+REG64_FLD( EX_CC_PROTECT_MODE_REG_WRITE_ENABLE                     , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( C_CC_PROTECT_MODE_REG_READ_ENABLE                       , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_READ_ENABLE );
+REG64_FLD( C_CC_PROTECT_MODE_REG_WRITE_ENABLE                      , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( EQ_CLK_REGION_CLOCK_CMD                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_CMD  );
+REG64_FLD( EQ_CLK_REGION_CLOCK_CMD_LEN                             , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_CMD_LEN );
+REG64_FLD( EQ_CLK_REGION_SLAVE_MODE                                , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE_MODE );
+REG64_FLD( EQ_CLK_REGION_MASTER_MODE                               , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_MODE );
+REG64_FLD( EQ_CLK_REGION_CLOCK_PERV                                , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_PERV );
+REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT1                               , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT1 );
+REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT2                               , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT2 );
+REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT3                               , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT3 );
+REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT4                               , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT4 );
+REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT5                               , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT5 );
+REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT6                               , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT6 );
+REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT7                               , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT7 );
+REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT8                               , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT8 );
+REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT9                               , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT9 );
+REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT10                              , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT10 );
+REG64_FLD( EQ_CLK_REGION_SEL_THOLD_SL                              , 48  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_SL );
+REG64_FLD( EQ_CLK_REGION_SEL_THOLD_NSL                             , 49  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_NSL );
+REG64_FLD( EQ_CLK_REGION_SEL_THOLD_ARY                             , 50  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_ARY );
+REG64_FLD( EQ_CLK_REGION_CLOCK_PULSE_USE_EVEN                      , 52  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_PULSE_USE_EVEN );
+
+REG64_FLD( EX_CLK_REGION_CLOCK_CMD                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_CMD  );
+REG64_FLD( EX_CLK_REGION_CLOCK_CMD_LEN                             , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_CMD_LEN );
+REG64_FLD( EX_CLK_REGION_SLAVE_MODE                                , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE_MODE );
+REG64_FLD( EX_CLK_REGION_MASTER_MODE                               , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_MODE );
+REG64_FLD( EX_CLK_REGION_CLOCK_PERV                                , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_PERV );
+REG64_FLD( EX_CLK_REGION_CLOCK_UNIT1                               , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT1 );
+REG64_FLD( EX_CLK_REGION_CLOCK_UNIT2                               , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT2 );
+REG64_FLD( EX_CLK_REGION_CLOCK_UNIT3                               , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT3 );
+REG64_FLD( EX_CLK_REGION_CLOCK_UNIT4                               , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT4 );
+REG64_FLD( EX_CLK_REGION_CLOCK_UNIT5                               , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT5 );
+REG64_FLD( EX_CLK_REGION_CLOCK_UNIT6                               , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT6 );
+REG64_FLD( EX_CLK_REGION_CLOCK_UNIT7                               , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT7 );
+REG64_FLD( EX_CLK_REGION_CLOCK_UNIT8                               , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT8 );
+REG64_FLD( EX_CLK_REGION_CLOCK_UNIT9                               , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT9 );
+REG64_FLD( EX_CLK_REGION_CLOCK_UNIT10                              , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT10 );
+REG64_FLD( EX_CLK_REGION_SEL_THOLD_SL                              , 48  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_SL );
+REG64_FLD( EX_CLK_REGION_SEL_THOLD_NSL                             , 49  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_NSL );
+REG64_FLD( EX_CLK_REGION_SEL_THOLD_ARY                             , 50  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_ARY );
+REG64_FLD( EX_CLK_REGION_CLOCK_PULSE_USE_EVEN                      , 52  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_PULSE_USE_EVEN );
+
+REG64_FLD( C_CLK_REGION_CLOCK_CMD                                  , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_CMD  );
+REG64_FLD( C_CLK_REGION_CLOCK_CMD_LEN                              , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_CMD_LEN );
+REG64_FLD( C_CLK_REGION_SLAVE_MODE                                 , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SLAVE_MODE );
+REG64_FLD( C_CLK_REGION_MASTER_MODE                                , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_MODE );
+REG64_FLD( C_CLK_REGION_CLOCK_PERV                                 , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_PERV );
+REG64_FLD( C_CLK_REGION_CLOCK_UNIT1                                , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT1 );
+REG64_FLD( C_CLK_REGION_CLOCK_UNIT2                                , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT2 );
+REG64_FLD( C_CLK_REGION_CLOCK_UNIT3                                , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT3 );
+REG64_FLD( C_CLK_REGION_CLOCK_UNIT4                                , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT4 );
+REG64_FLD( C_CLK_REGION_CLOCK_UNIT5                                , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT5 );
+REG64_FLD( C_CLK_REGION_CLOCK_UNIT6                                , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT6 );
+REG64_FLD( C_CLK_REGION_CLOCK_UNIT7                                , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT7 );
+REG64_FLD( C_CLK_REGION_CLOCK_UNIT8                                , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT8 );
+REG64_FLD( C_CLK_REGION_CLOCK_UNIT9                                , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT9 );
+REG64_FLD( C_CLK_REGION_CLOCK_UNIT10                               , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_UNIT10 );
+REG64_FLD( C_CLK_REGION_SEL_THOLD_SL                               , 48  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_SL );
+REG64_FLD( C_CLK_REGION_SEL_THOLD_NSL                              , 49  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_NSL );
+REG64_FLD( C_CLK_REGION_SEL_THOLD_ARY                              , 50  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEL_THOLD_ARY );
+REG64_FLD( C_CLK_REGION_CLOCK_PULSE_USE_EVEN                       , 52  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLOCK_PULSE_USE_EVEN );
+
+REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_PERV                           , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_PERV );
+REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT1                          , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT1 );
+REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT2                          , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT2 );
+REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT3                          , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT3 );
+REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT4                          , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT4 );
+REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT5                          , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT5 );
+REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT6                          , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT6 );
+REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT7                          , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT7 );
+REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT8                          , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT8 );
+REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT9                          , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT9 );
+REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT10                         , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_PERV                           , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_PERV );
+REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT1                          , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT1 );
+REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT2                          , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT2 );
+REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT3                          , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT3 );
+REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT4                          , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT4 );
+REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT5                          , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT5 );
+REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT6                          , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT6 );
+REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT7                          , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT7 );
+REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT8                          , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT8 );
+REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT9                          , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT9 );
+REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT10                         , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( C_CLOCK_STAT_ARY_STATUS_PERV                            , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_PERV );
+REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT1                           , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT1 );
+REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT2                           , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT2 );
+REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT3                           , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT3 );
+REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT4                           , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT4 );
+REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT5                           , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT5 );
+REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT6                           , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT6 );
+REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT7                           , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT7 );
+REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT8                           , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT8 );
+REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT9                           , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT9 );
+REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT10                          , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_PERV                           , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_PERV );
+REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT1                          , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT1 );
+REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT2                          , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT2 );
+REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT3                          , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT3 );
+REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT4                          , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT4 );
+REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT5                          , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT5 );
+REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT6                          , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT6 );
+REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT7                          , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT7 );
+REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT8                          , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT8 );
+REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT9                          , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT9 );
+REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT10                         , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_PERV                           , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_PERV );
+REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT1                          , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT1 );
+REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT2                          , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT2 );
+REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT3                          , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT3 );
+REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT4                          , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT4 );
+REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT5                          , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT5 );
+REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT6                          , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT6 );
+REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT7                          , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT7 );
+REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT8                          , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT8 );
+REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT9                          , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT9 );
+REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT10                         , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( C_CLOCK_STAT_NSL_STATUS_PERV                            , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_PERV );
+REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT1                           , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT1 );
+REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT2                           , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT2 );
+REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT3                           , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT3 );
+REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT4                           , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT4 );
+REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT5                           , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT5 );
+REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT6                           , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT6 );
+REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT7                           , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT7 );
+REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT8                           , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT8 );
+REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT9                           , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT9 );
+REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT10                          , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_PERV                            , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_PERV );
+REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT1                           , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT1 );
+REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT2                           , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT2 );
+REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT3                           , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT3 );
+REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT4                           , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT4 );
+REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT5                           , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT5 );
+REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT6                           , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT6 );
+REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT7                           , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT7 );
+REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT8                           , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT8 );
+REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT9                           , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT9 );
+REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT10                          , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( EX_CLOCK_STAT_SL_STATUS_PERV                            , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_PERV );
+REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT1                           , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT1 );
+REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT2                           , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT2 );
+REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT3                           , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT3 );
+REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT4                           , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT4 );
+REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT5                           , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT5 );
+REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT6                           , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT6 );
+REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT7                           , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT7 );
+REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT8                           , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT8 );
+REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT9                           , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT9 );
+REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT10                          , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( C_CLOCK_STAT_SL_STATUS_PERV                             , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_PERV );
+REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT1                            , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT1 );
+REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT2                            , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT2 );
+REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT3                            , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT3 );
+REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT4                            , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT4 );
+REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT5                            , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT5 );
+REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT6                            , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT6 );
+REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT7                            , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT7 );
+REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT8                            , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT8 );
+REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT9                            , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT9 );
+REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT10                           , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATUS_UNIT10 );
+
+REG64_FLD( EX_CME_LCL_DBG_EN                                       , 0   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_EN         );
+REG64_FLD( EX_CME_LCL_DBG_HALT_ON_XSTOP                            , 1   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_XSTOP );
+REG64_FLD( EX_CME_LCL_DBG_HALT_ON_TRIG                             , 2   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_HALT_ON_TRIG );
+REG64_FLD( EX_CME_LCL_DBG_RESERVED3                                , 3   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED3  );
+REG64_FLD( EX_CME_LCL_DBG_EN_INTR_ADDR                             , 4   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_EN_INTR_ADDR );
+REG64_FLD( EX_CME_LCL_DBG_EN_TRACE_EXTRA                           , 5   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_EXTRA );
+REG64_FLD( EX_CME_LCL_DBG_EN_TRACE_STALL                           , 6   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_EN_TRACE_STALL );
+REG64_FLD( EX_CME_LCL_DBG_EN_WAIT_CYCLES                           , 7   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_EN_WAIT_CYCLES );
+REG64_FLD( EX_CME_LCL_DBG_EN_FULL_SPEED                            , 8   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_EN_FULL_SPEED );
+REG64_FLD( EX_CME_LCL_DBG_RESERVED9                                , 9   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_RESERVED9  );
+REG64_FLD( EX_CME_LCL_DBG_TRACE_MODE_SEL                           , 10  , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL );
+REG64_FLD( EX_CME_LCL_DBG_TRACE_MODE_SEL_LEN                       , 2   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_MODE_SEL_LEN );
+REG64_FLD( EX_CME_LCL_DBG_FIR_TRIGGER                              , 16  , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_FIR_TRIGGER );
+REG64_FLD( EX_CME_LCL_DBG_MIB_GPIO                                 , 17  , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO   );
+REG64_FLD( EX_CME_LCL_DBG_MIB_GPIO_LEN                             , 3   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_MIB_GPIO_LEN );
+REG64_FLD( EX_CME_LCL_DBG_TRACE_DATA_SEL                           , 20  , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL );
+REG64_FLD( EX_CME_LCL_DBG_TRACE_DATA_SEL_LEN                       , 4   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_TRACE_DATA_SEL_LEN );
+
+REG64_FLD( EQ_CME_LCL_EIMR_INTERRUPT_MASK                          , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_MASK );
+REG64_FLD( EQ_CME_LCL_EIMR_INTERRUPT_MASK_LEN                      , 44  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( EX_CME_LCL_EIMR_INTERRUPT_MASK                          , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_MASK );
+REG64_FLD( EX_CME_LCL_EIMR_INTERRUPT_MASK_LEN                      , 44  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_MASK_LEN );
+
+REG64_FLD( EQ_CME_LCL_EINR_INTERRUPT_INPUT                         , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( EQ_CME_LCL_EINR_INTERRUPT_INPUT_LEN                     , 44  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( EX_CME_LCL_EINR_INTERRUPT_INPUT                         , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_INPUT );
+REG64_FLD( EX_CME_LCL_EINR_INTERRUPT_INPUT_LEN                     , 44  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_INPUT_LEN );
+
+REG64_FLD( EQ_CME_LCL_EIPR_INTERRUPT_POLARITY                      , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( EQ_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN                  , 44  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( EX_CME_LCL_EIPR_INTERRUPT_POLARITY                      , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_POLARITY );
+REG64_FLD( EX_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN                  , 44  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_POLARITY_LEN );
+
+REG64_FLD( EQ_CME_LCL_EISR_DEBUGGER                                , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( EQ_CME_LCL_EISR_DEBUG_TRIGGER                           , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( EQ_CME_LCL_EISR_QUAD_CHECKSTOP                          , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( EQ_CME_LCL_EISR_PVREF_FAIL                              , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PVREF_FAIL );
+REG64_FLD( EQ_CME_LCL_EISR_OCC_HEARTBEAT_LOST                      , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( EQ_CME_LCL_EISR_CORE_CHECKSTOP                          , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( EQ_CME_LCL_EISR_DROPOUT_DETECT                          , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DROPOUT_DETECT );
+REG64_FLD( EQ_CME_LCL_EISR_INTERCME_DIRECT_IN_0                    , 7   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERCME_DIRECT_IN_0 );
+REG64_FLD( EQ_CME_LCL_EISR_BCE_BUSY_HIGH                           , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( EQ_CME_LCL_EISR_BCE_TIMEOUT                             , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( EQ_CME_LCL_EISR_DOORBELL3_C0                            , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL3_C0 );
+REG64_FLD( EQ_CME_LCL_EISR_DOORBELL3_C1                            , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL3_C1 );
+REG64_FLD( EQ_CME_LCL_EISR_PC_INTR_PENDING_C0                      , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( EQ_CME_LCL_EISR_PC_INTR_PENDING_C1                      , 13  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( EQ_CME_LCL_EISR_SPECIAL_WAKEUP_C0                       , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( EQ_CME_LCL_EISR_SPECIAL_WAKEUP_C1                       , 15  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( EQ_CME_LCL_EISR_REG_WAKEUP_C0                           , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( EQ_CME_LCL_EISR_REG_WAKEUP_C1                           , 17  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( EQ_CME_LCL_EISR_DOORBELL2_C0                            , 18  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL2_C0 );
+REG64_FLD( EQ_CME_LCL_EISR_DOORBELL2_C1                            , 19  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL2_C1 );
+REG64_FLD( EQ_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0                   , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( EQ_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1                   , 21  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( EQ_CME_LCL_EISR_L2_PURGE_DONE                           , 22  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( EQ_CME_LCL_EISR_NCU_PURGE_DONE                          , 23  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( EQ_CME_LCL_EISR_CHTM_PURGE_DONE_C0                      , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( EQ_CME_LCL_EISR_CHTM_PURGE_DONE_C1                      , 25  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( EQ_CME_LCL_EISR_BCE_BUSY_LOW                            , 26  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( EQ_CME_LCL_EISR_FINAL_VDM_DATA01                        , 27  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FINAL_VDM_DATA01 );
+REG64_FLD( EQ_CME_LCL_EISR_FINAL_VDM_DATA01_LEN                    , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FINAL_VDM_DATA01_LEN );
+REG64_FLD( EQ_CME_LCL_EISR_COMM_RECVD                              , 29  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_COMM_RECVD );
+REG64_FLD( EQ_CME_LCL_EISR_COMM_SEND_ACK                           , 30  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_COMM_SEND_ACK );
+REG64_FLD( EQ_CME_LCL_EISR_COMM_SEND_NACK                          , 31  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_COMM_SEND_NACK );
+REG64_FLD( EQ_CME_LCL_EISR_SPARE_32_33                             , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE_32_33 );
+REG64_FLD( EQ_CME_LCL_EISR_SPARE_32_33_LEN                         , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( EQ_CME_LCL_EISR_PMCR_UPDATE_C0                          , 34  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( EQ_CME_LCL_EISR_PMCR_UPDATE_C1                          , 35  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( EQ_CME_LCL_EISR_DOORBELL0_C0                            , 36  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL0_C0 );
+REG64_FLD( EQ_CME_LCL_EISR_DOORBELL0_C1                            , 37  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL0_C1 );
+REG64_FLD( EQ_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2                  , 38  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2 );
+REG64_FLD( EQ_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN              , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2_LEN );
+REG64_FLD( EQ_CME_LCL_EISR_DOORBELL1_C0                            , 40  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL1_C0 );
+REG64_FLD( EQ_CME_LCL_EISR_DOORBELL1_C1                            , 41  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL1_C1 );
+REG64_FLD( EQ_CME_LCL_EISR_RESERVED_42_43                          , 42  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_42_43 );
+REG64_FLD( EQ_CME_LCL_EISR_RESERVED_42_43_LEN                      , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( EX_CME_LCL_EISR_DEBUGGER                                , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( EX_CME_LCL_EISR_DEBUG_TRIGGER                           , 1   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( EX_CME_LCL_EISR_QUAD_CHECKSTOP                          , 2   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_QUAD_CHECKSTOP );
+REG64_FLD( EX_CME_LCL_EISR_PVREF_FAIL                              , 3   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PVREF_FAIL );
+REG64_FLD( EX_CME_LCL_EISR_OCC_HEARTBEAT_LOST                      , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_OCC_HEARTBEAT_LOST );
+REG64_FLD( EX_CME_LCL_EISR_CORE_CHECKSTOP                          , 5   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CORE_CHECKSTOP );
+REG64_FLD( EX_CME_LCL_EISR_DROPOUT_DETECT                          , 6   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DROPOUT_DETECT );
+REG64_FLD( EX_CME_LCL_EISR_INTERCME_DIRECT_IN_0                    , 7   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERCME_DIRECT_IN_0 );
+REG64_FLD( EX_CME_LCL_EISR_BCE_BUSY_HIGH                           , 8   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_BCE_BUSY_HIGH );
+REG64_FLD( EX_CME_LCL_EISR_BCE_TIMEOUT                             , 9   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( EX_CME_LCL_EISR_DOORBELL3_C0                            , 10  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL3_C0 );
+REG64_FLD( EX_CME_LCL_EISR_DOORBELL3_C1                            , 11  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL3_C1 );
+REG64_FLD( EX_CME_LCL_EISR_PC_INTR_PENDING_C0                      , 12  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( EX_CME_LCL_EISR_PC_INTR_PENDING_C1                      , 13  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( EX_CME_LCL_EISR_SPECIAL_WAKEUP_C0                       , 14  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( EX_CME_LCL_EISR_SPECIAL_WAKEUP_C1                       , 15  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( EX_CME_LCL_EISR_REG_WAKEUP_C0                           , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( EX_CME_LCL_EISR_REG_WAKEUP_C1                           , 17  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( EX_CME_LCL_EISR_DOORBELL2_C0                            , 18  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL2_C0 );
+REG64_FLD( EX_CME_LCL_EISR_DOORBELL2_C1                            , 19  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL2_C1 );
+REG64_FLD( EX_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0                   , 20  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( EX_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1                   , 21  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( EX_CME_LCL_EISR_L2_PURGE_DONE                           , 22  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( EX_CME_LCL_EISR_NCU_PURGE_DONE                          , 23  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( EX_CME_LCL_EISR_CHTM_PURGE_DONE_C0                      , 24  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( EX_CME_LCL_EISR_CHTM_PURGE_DONE_C1                      , 25  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+REG64_FLD( EX_CME_LCL_EISR_BCE_BUSY_LOW                            , 26  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_BCE_BUSY_LOW );
+REG64_FLD( EX_CME_LCL_EISR_FINAL_VDM_DATA01                        , 27  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FINAL_VDM_DATA01 );
+REG64_FLD( EX_CME_LCL_EISR_FINAL_VDM_DATA01_LEN                    , 2   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FINAL_VDM_DATA01_LEN );
+REG64_FLD( EX_CME_LCL_EISR_COMM_RECVD                              , 29  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_COMM_RECVD );
+REG64_FLD( EX_CME_LCL_EISR_COMM_SEND_ACK                           , 30  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_COMM_SEND_ACK );
+REG64_FLD( EX_CME_LCL_EISR_COMM_SEND_NACK                          , 31  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_COMM_SEND_NACK );
+REG64_FLD( EX_CME_LCL_EISR_SPARE_32_33                             , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE_32_33 );
+REG64_FLD( EX_CME_LCL_EISR_SPARE_32_33_LEN                         , 2   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPARE_32_33_LEN );
+REG64_FLD( EX_CME_LCL_EISR_PMCR_UPDATE_C0                          , 34  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PMCR_UPDATE_C0 );
+REG64_FLD( EX_CME_LCL_EISR_PMCR_UPDATE_C1                          , 35  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PMCR_UPDATE_C1 );
+REG64_FLD( EX_CME_LCL_EISR_DOORBELL0_C0                            , 36  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL0_C0 );
+REG64_FLD( EX_CME_LCL_EISR_DOORBELL0_C1                            , 37  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL0_C1 );
+REG64_FLD( EX_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2                  , 38  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2 );
+REG64_FLD( EX_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN              , 2   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERCME_DIRECT_IN_1_2_LEN );
+REG64_FLD( EX_CME_LCL_EISR_DOORBELL1_C0                            , 40  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL1_C0 );
+REG64_FLD( EX_CME_LCL_EISR_DOORBELL1_C1                            , 41  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DOORBELL1_C1 );
+REG64_FLD( EX_CME_LCL_EISR_RESERVED_42_43                          , 42  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_42_43 );
+REG64_FLD( EX_CME_LCL_EISR_RESERVED_42_43_LEN                      , 2   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_42_43_LEN );
+
+REG64_FLD( EQ_CME_LCL_EITR_INTERRUPT_TYPE                          , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( EQ_CME_LCL_EITR_INTERRUPT_TYPE_LEN                      , 44  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( EX_CME_LCL_EITR_INTERRUPT_TYPE                          , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_TYPE );
+REG64_FLD( EX_CME_LCL_EITR_INTERRUPT_TYPE_LEN                      , 44  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INTERRUPT_TYPE_LEN );
+
+REG64_FLD( EX_CME_LCL_ICCR_COMM_ACK                                , 0   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_COMM_ACK   );
+REG64_FLD( EX_CME_LCL_ICCR_COMM_NACK                               , 1   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_COMM_NACK  );
+REG64_FLD( EX_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT                , 5   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT );
+REG64_FLD( EX_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN            , 3   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN );
+REG64_FLD( EX_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN                 , 9   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN );
+REG64_FLD( EX_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN             , 3   , SH_UNT_EX       , SH_ACS_PPE2     ,
+           SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN );
+
+REG64_FLD( EQ_CME_LCL_ICRR_COMM_RECV                               , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_COMM_RECV  );
+REG64_FLD( EQ_CME_LCL_ICRR_COMM_RECV_LEN                           , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( EX_CME_LCL_ICRR_COMM_RECV                               , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_COMM_RECV  );
+REG64_FLD( EX_CME_LCL_ICRR_COMM_RECV_LEN                           , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_COMM_RECV_LEN );
+
+REG64_FLD( EX_CME_LCL_ICSR_COMM_SEND                               , 0   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND  );
+REG64_FLD( EX_CME_LCL_ICSR_COMM_SEND_LEN                           , 32  , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_COMM_SEND_LEN );
+
+REG64_FLD( EX_CME_LCL_LMCR_RESET_IMPRECISE_QERR                    , 32  , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_RESET_IMPRECISE_QERR );
+REG64_FLD( EX_CME_LCL_LMCR_SET_ECC_INJECT_ERR                      , 33  , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_SET_ECC_INJECT_ERR );
+REG64_FLD( EX_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE         , 34  , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( EX_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE         , 35  , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE );
+REG64_FLD( EX_CME_LCL_LMCR_FENCE_EISR                              , 36  , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_FENCE_EISR );
+REG64_FLD( EX_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE            , 37  , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE );
+REG64_FLD( EX_CME_LCL_LMCR_PC_DISABLE_DROOP                        , 38  , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PC_DISABLE_DROOP );
+
+REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T0                          , 0   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T0_LEN                      , 6   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T1                          , 8   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T1_LEN                      , 6   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T2                          , 16  , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T2_LEN                      , 6   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T3                          , 24  , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T3_LEN                      , 6   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( EX_CME_LCL_PECESR0_USE_PECE                             , 32  , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( EX_CME_LCL_PECESR0_USE_PECE_LEN                         , 4   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T0                          , 0   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0 );
+REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T0_LEN                      , 6   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T0_LEN );
+REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T1                          , 8   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1 );
+REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T1_LEN                      , 6   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T1_LEN );
+REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T2                          , 16  , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2 );
+REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T2_LEN                      , 6   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T2_LEN );
+REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T3                          , 24  , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3 );
+REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T3_LEN                      , 6   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_PECE_C_N_T3_LEN );
+REG64_FLD( EX_CME_LCL_PECESR1_USE_PECE                             , 32  , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE   );
+REG64_FLD( EX_CME_LCL_PECESR1_USE_PECE_LEN                         , 4   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_USE_PECE_LEN );
+
+REG64_FLD( EQ_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_ENTRY_ACK_C0_ACTUAL );
+REG64_FLD( EQ_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL                  , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_ENTRY_ACK_C1_ACTUAL );
+REG64_FLD( EQ_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL           , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL );
+REG64_FLD( EQ_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL           , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL );
+REG64_FLD( EQ_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                       , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_EXIT_C0_ACTUAL );
+REG64_FLD( EQ_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                       , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_EXIT_C1_ACTUAL );
+REG64_FLD( EQ_CME_LCL_SISR_RESERVED_6_8                            , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_6_8 );
+REG64_FLD( EQ_CME_LCL_SISR_RESERVED_6_8_LEN                        , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_6_8_LEN );
+REG64_FLD( EQ_CME_LCL_SISR_PC_FUSED_CORE_MODE                      , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_FUSED_CORE_MODE );
+REG64_FLD( EQ_CME_LCL_SISR_PCBMUX_GRANT_C0                         , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( EQ_CME_LCL_SISR_PCBMUX_GRANT_C1                         , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( EQ_CME_LCL_SISR_RESERVED_12_15                          , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( EQ_CME_LCL_SISR_RESERVED_12_15_LEN                      , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( EQ_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL           , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL );
+REG64_FLD( EQ_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL           , 17  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL );
+REG64_FLD( EQ_CME_LCL_SISR_RESERVED_18_29                          , 18  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_18_29 );
+REG64_FLD( EQ_CME_LCL_SISR_RESERVED_18_29_LEN                      , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_18_29_LEN );
+REG64_FLD( EQ_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1            , 30  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 );
+REG64_FLD( EQ_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN        , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN );
+REG64_FLD( EQ_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                     , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( EQ_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                     , 33  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_ACTIVE_C0                      , 34  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_ACTIVE_C1                      , 35  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_C0                             , 36  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_C0 );
+REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_C0_LEN                         , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_C1                             , 40  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_C1 );
+REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_C1_LEN                         , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_ALL_HV_C0                      , 44  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_ALL_HV_C1                      , 45  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( EQ_CME_LCL_SISR_PC_INSTR_RUNNING_C0                     , 46  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( EQ_CME_LCL_SISR_PC_INSTR_RUNNING_C1                     , 47  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( EQ_CME_LCL_SISR_PC_NON_HV_RUNNING_C0                    , 48  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( EQ_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN                , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( EQ_CME_LCL_SISR_PC_NON_HV_RUNNING_C1                    , 52  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( EQ_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN                , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+REG64_FLD( EQ_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                     , 56  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( EQ_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                     , 57  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ALLOW_REG_WAKEUP_C1 );
+
+REG64_FLD( EX_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL                  , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_ENTRY_ACK_C0_ACTUAL );
+REG64_FLD( EX_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL                  , 1   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_ENTRY_ACK_C1_ACTUAL );
+REG64_FLD( EX_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL           , 2   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL );
+REG64_FLD( EX_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL           , 3   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL );
+REG64_FLD( EX_CME_LCL_SISR_PM_EXIT_C0_ACTUAL                       , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_EXIT_C0_ACTUAL );
+REG64_FLD( EX_CME_LCL_SISR_PM_EXIT_C1_ACTUAL                       , 5   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_EXIT_C1_ACTUAL );
+REG64_FLD( EX_CME_LCL_SISR_RESERVED_6_8                            , 6   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_6_8 );
+REG64_FLD( EX_CME_LCL_SISR_RESERVED_6_8_LEN                        , 3   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_6_8_LEN );
+REG64_FLD( EX_CME_LCL_SISR_PC_FUSED_CORE_MODE                      , 9   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_FUSED_CORE_MODE );
+REG64_FLD( EX_CME_LCL_SISR_PCBMUX_GRANT_C0                         , 10  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCBMUX_GRANT_C0 );
+REG64_FLD( EX_CME_LCL_SISR_PCBMUX_GRANT_C1                         , 11  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCBMUX_GRANT_C1 );
+REG64_FLD( EX_CME_LCL_SISR_RESERVED_12_15                          , 12  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( EX_CME_LCL_SISR_RESERVED_12_15_LEN                      , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( EX_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL           , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL );
+REG64_FLD( EX_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL           , 17  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL );
+REG64_FLD( EX_CME_LCL_SISR_RESERVED_18_29                          , 18  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_18_29 );
+REG64_FLD( EX_CME_LCL_SISR_RESERVED_18_29_LEN                      , 12  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_18_29_LEN );
+REG64_FLD( EX_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1            , 30  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 );
+REG64_FLD( EX_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN        , 2   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN );
+REG64_FLD( EX_CME_LCL_SISR_PC_UNMASKED_ATTN_C0                     , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_UNMASKED_ATTN_C0 );
+REG64_FLD( EX_CME_LCL_SISR_PC_UNMASKED_ATTN_C1                     , 33  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_UNMASKED_ATTN_C1 );
+REG64_FLD( EX_CME_LCL_SISR_PM_STATE_ACTIVE_C0                      , 34  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_ACTIVE_C0 );
+REG64_FLD( EX_CME_LCL_SISR_PM_STATE_ACTIVE_C1                      , 35  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_ACTIVE_C1 );
+REG64_FLD( EX_CME_LCL_SISR_PM_STATE_C0                             , 36  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_C0 );
+REG64_FLD( EX_CME_LCL_SISR_PM_STATE_C0_LEN                         , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_C0_LEN );
+REG64_FLD( EX_CME_LCL_SISR_PM_STATE_C1                             , 40  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_C1 );
+REG64_FLD( EX_CME_LCL_SISR_PM_STATE_C1_LEN                         , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_C1_LEN );
+REG64_FLD( EX_CME_LCL_SISR_PM_STATE_ALL_HV_C0                      , 44  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_ALL_HV_C0 );
+REG64_FLD( EX_CME_LCL_SISR_PM_STATE_ALL_HV_C1                      , 45  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PM_STATE_ALL_HV_C1 );
+REG64_FLD( EX_CME_LCL_SISR_PC_INSTR_RUNNING_C0                     , 46  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_INSTR_RUNNING_C0 );
+REG64_FLD( EX_CME_LCL_SISR_PC_INSTR_RUNNING_C1                     , 47  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_INSTR_RUNNING_C1 );
+REG64_FLD( EX_CME_LCL_SISR_PC_NON_HV_RUNNING_C0                    , 48  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_NON_HV_RUNNING_C0 );
+REG64_FLD( EX_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN                , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_NON_HV_RUNNING_C0_LEN );
+REG64_FLD( EX_CME_LCL_SISR_PC_NON_HV_RUNNING_C1                    , 52  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_NON_HV_RUNNING_C1 );
+REG64_FLD( EX_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN                , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PC_NON_HV_RUNNING_C1_LEN );
+REG64_FLD( EX_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0                     , 56  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ALLOW_REG_WAKEUP_C0 );
+REG64_FLD( EX_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1                     , 57  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ALLOW_REG_WAKEUP_C1 );
+
+REG64_FLD( EX_CME_LCL_TSEL_FIT_SEL                                 , 0   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL    );
+REG64_FLD( EX_CME_LCL_TSEL_FIT_SEL_LEN                             , 4   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_FIT_SEL_LEN );
+REG64_FLD( EX_CME_LCL_TSEL_WATCHDOG_SEL                            , 4   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL );
+REG64_FLD( EX_CME_LCL_TSEL_WATCHDOG_SEL_LEN                        , 4   , SH_UNT_EX       , SH_ACS_PPE      ,
+           SH_FLD_WATCHDOG_SEL_LEN );
+
+REG64_FLD( EQ_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                      , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( EQ_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN                  , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( EQ_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                       , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( EQ_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN                   , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( EQ_CME_SCOM_AFSR_SAMPLE_VALID                           , 63  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( EX_CME_SCOM_AFSR_INST_CYCLE_SAMPLE                      , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST_CYCLE_SAMPLE );
+REG64_FLD( EX_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN                  , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST_CYCLE_SAMPLE_LEN );
+REG64_FLD( EX_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE                       , 32  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_AVG_CYCLE_SAMPLE );
+REG64_FLD( EX_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN                   , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_AVG_CYCLE_SAMPLE_LEN );
+REG64_FLD( EX_CME_SCOM_AFSR_SAMPLE_VALID                           , 63  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_VALID );
+
+REG64_FLD( EQ_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                       , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( EQ_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN                   , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( EQ_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                       , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( EQ_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN                   , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( EX_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE                       , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_CYCLE_SAMPLE );
+REG64_FLD( EX_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN                   , 20  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MAX_CYCLE_SAMPLE_LEN );
+REG64_FLD( EX_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE                       , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MIN_CYCLE_SAMPLE );
+REG64_FLD( EX_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN                   , 20  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MIN_CYCLE_SAMPLE_LEN );
+
+REG64_FLD( EQ_CME_SCOM_BCEBAR0_BASE                                , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_BASE       );
+REG64_FLD( EQ_CME_SCOM_BCEBAR0_BASE_LEN                            , 36  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_BASE_LEN   );
+REG64_FLD( EQ_CME_SCOM_BCEBAR0_RD_SCOPE                            , 57  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RD_SCOPE   );
+REG64_FLD( EQ_CME_SCOM_BCEBAR0_RD_SCOPE_LEN                        , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RD_SCOPE_LEN );
+REG64_FLD( EQ_CME_SCOM_BCEBAR0_WR_SCOPE                            , 59  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_WR_SCOPE   );
+REG64_FLD( EQ_CME_SCOM_BCEBAR0_VG_TARGET_SEL                       , 60  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VG_TARGET_SEL );
+REG64_FLD( EQ_CME_SCOM_BCEBAR0_SIZE                                , 61  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE       );
+REG64_FLD( EQ_CME_SCOM_BCEBAR0_SIZE_LEN                            , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_LEN   );
+
+REG64_FLD( EX_CME_SCOM_BCEBAR0_BASE                                , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_BASE       );
+REG64_FLD( EX_CME_SCOM_BCEBAR0_BASE_LEN                            , 36  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_BASE_LEN   );
+REG64_FLD( EX_CME_SCOM_BCEBAR0_RD_SCOPE                            , 57  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RD_SCOPE   );
+REG64_FLD( EX_CME_SCOM_BCEBAR0_RD_SCOPE_LEN                        , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RD_SCOPE_LEN );
+REG64_FLD( EX_CME_SCOM_BCEBAR0_WR_SCOPE                            , 59  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_WR_SCOPE   );
+REG64_FLD( EX_CME_SCOM_BCEBAR0_VG_TARGET_SEL                       , 60  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VG_TARGET_SEL );
+REG64_FLD( EX_CME_SCOM_BCEBAR0_SIZE                                , 61  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE       );
+REG64_FLD( EX_CME_SCOM_BCEBAR0_SIZE_LEN                            , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_LEN   );
+
+REG64_FLD( EQ_CME_SCOM_BCEBAR1_BASE                                , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_BASE       );
+REG64_FLD( EQ_CME_SCOM_BCEBAR1_BASE_LEN                            , 36  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_BASE_LEN   );
+REG64_FLD( EQ_CME_SCOM_BCEBAR1_RD_SCOPE                            , 57  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RD_SCOPE   );
+REG64_FLD( EQ_CME_SCOM_BCEBAR1_RD_SCOPE_LEN                        , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RD_SCOPE_LEN );
+REG64_FLD( EQ_CME_SCOM_BCEBAR1_WR_SCOPE                            , 59  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_WR_SCOPE   );
+REG64_FLD( EQ_CME_SCOM_BCEBAR1_VG_TARGET_SEL                       , 60  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VG_TARGET_SEL );
+REG64_FLD( EQ_CME_SCOM_BCEBAR1_SIZE                                , 61  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE       );
+REG64_FLD( EQ_CME_SCOM_BCEBAR1_SIZE_LEN                            , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_LEN   );
+
+REG64_FLD( EX_CME_SCOM_BCEBAR1_BASE                                , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_BASE       );
+REG64_FLD( EX_CME_SCOM_BCEBAR1_BASE_LEN                            , 36  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_BASE_LEN   );
+REG64_FLD( EX_CME_SCOM_BCEBAR1_RD_SCOPE                            , 57  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RD_SCOPE   );
+REG64_FLD( EX_CME_SCOM_BCEBAR1_RD_SCOPE_LEN                        , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RD_SCOPE_LEN );
+REG64_FLD( EX_CME_SCOM_BCEBAR1_WR_SCOPE                            , 59  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_WR_SCOPE   );
+REG64_FLD( EX_CME_SCOM_BCEBAR1_VG_TARGET_SEL                       , 60  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VG_TARGET_SEL );
+REG64_FLD( EX_CME_SCOM_BCEBAR1_SIZE                                , 61  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE       );
+REG64_FLD( EX_CME_SCOM_BCEBAR1_SIZE_LEN                            , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_LEN   );
+
+REG64_FLD( EQ_CME_SCOM_BCECSR_BUSY                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_BUSY       );
+REG64_FLD( EQ_CME_SCOM_BCECSR_ERROR                                , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ERROR      );
+REG64_FLD( EQ_CME_SCOM_BCECSR_RNW                                  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RNW        );
+REG64_FLD( EQ_CME_SCOM_BCECSR_BARSEL                               , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_BARSEL     );
+REG64_FLD( EQ_CME_SCOM_BCECSR_PRIORITY                             , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( EQ_CME_SCOM_BCECSR_INJECT_ERR                           , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INJECT_ERR );
+REG64_FLD( EQ_CME_SCOM_BCECSR_TYPE                                 , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TYPE       );
+REG64_FLD( EQ_CME_SCOM_BCECSR_TYPE_LEN                             , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( EQ_CME_SCOM_BCECSR_NUM_BLOCKS                           , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NUM_BLOCKS );
+REG64_FLD( EQ_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                       , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( EQ_CME_SCOM_BCECSR_SBASE                                , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SBASE      );
+REG64_FLD( EQ_CME_SCOM_BCECSR_SBASE_LEN                            , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SBASE_LEN  );
+REG64_FLD( EQ_CME_SCOM_BCECSR_MBASE                                , 42  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MBASE      );
+REG64_FLD( EQ_CME_SCOM_BCECSR_MBASE_LEN                            , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MBASE_LEN  );
+
+REG64_FLD( EX_CME_SCOM_BCECSR_BUSY                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_BUSY       );
+REG64_FLD( EX_CME_SCOM_BCECSR_ERROR                                , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ERROR      );
+REG64_FLD( EX_CME_SCOM_BCECSR_RNW                                  , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RNW        );
+REG64_FLD( EX_CME_SCOM_BCECSR_BARSEL                               , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_BARSEL     );
+REG64_FLD( EX_CME_SCOM_BCECSR_PRIORITY                             , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PRIORITY   );
+REG64_FLD( EX_CME_SCOM_BCECSR_INJECT_ERR                           , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INJECT_ERR );
+REG64_FLD( EX_CME_SCOM_BCECSR_TYPE                                 , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TYPE       );
+REG64_FLD( EX_CME_SCOM_BCECSR_TYPE_LEN                             , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( EX_CME_SCOM_BCECSR_NUM_BLOCKS                           , 17  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NUM_BLOCKS );
+REG64_FLD( EX_CME_SCOM_BCECSR_NUM_BLOCKS_LEN                       , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NUM_BLOCKS_LEN );
+REG64_FLD( EX_CME_SCOM_BCECSR_SBASE                                , 28  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SBASE      );
+REG64_FLD( EX_CME_SCOM_BCECSR_SBASE_LEN                            , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SBASE_LEN  );
+REG64_FLD( EX_CME_SCOM_BCECSR_MBASE                                , 42  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MBASE      );
+REG64_FLD( EX_CME_SCOM_BCECSR_MBASE_LEN                            , 22  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MBASE_LEN  );
+
+REG64_FLD( EQ_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT                , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT );
+REG64_FLD( EQ_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN            , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( EQ_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT               , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT );
+REG64_FLD( EQ_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN           , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( EQ_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT                , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT );
+REG64_FLD( EQ_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN            , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( EQ_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT               , 56  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT );
+REG64_FLD( EQ_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN           , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN );
+
+REG64_FLD( EX_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT                , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT );
+REG64_FLD( EX_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN            , 24  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( EX_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT               , 24  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT );
+REG64_FLD( EX_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN           , 8   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( EX_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT                , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT );
+REG64_FLD( EX_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN            , 24  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( EX_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT               , 56  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT );
+REG64_FLD( EX_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN           , 8   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN );
+
+REG64_FLD( EQ_CME_SCOM_EIIR_DEBUGGER                               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( EQ_CME_SCOM_EIIR_DEBUG_TRIGGER                          , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( EQ_CME_SCOM_EIIR_BCE_TIMEOUT                            , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( EQ_CME_SCOM_EIIR_PC_INTR_PENDING_C0                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( EQ_CME_SCOM_EIIR_PC_INTR_PENDING_C1                     , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( EQ_CME_SCOM_EIIR_SPECIAL_WAKEUP_C0                      , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( EQ_CME_SCOM_EIIR_SPECIAL_WAKEUP_C1                      , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( EQ_CME_SCOM_EIIR_REG_WAKEUP_C0                          , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( EQ_CME_SCOM_EIIR_REG_WAKEUP_C1                          , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( EQ_CME_SCOM_EIIR_PC_PM_STATE_ACTIVE_C0                  , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( EQ_CME_SCOM_EIIR_PC_PM_STATE_ACTIVE_C1                  , 21  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( EQ_CME_SCOM_EIIR_L2_PURGE_DONE                          , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( EQ_CME_SCOM_EIIR_NCU_PURGE_DONE                         , 23  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( EQ_CME_SCOM_EIIR_CHTM_PURGE_DONE_C0                     , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( EQ_CME_SCOM_EIIR_CHTM_PURGE_DONE_C1                     , 25  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+
+REG64_FLD( EX_CME_SCOM_EIIR_DEBUGGER                               , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DEBUGGER   );
+REG64_FLD( EX_CME_SCOM_EIIR_DEBUG_TRIGGER                          , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DEBUG_TRIGGER );
+REG64_FLD( EX_CME_SCOM_EIIR_BCE_TIMEOUT                            , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_BCE_TIMEOUT );
+REG64_FLD( EX_CME_SCOM_EIIR_PC_INTR_PENDING_C0                     , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PC_INTR_PENDING_C0 );
+REG64_FLD( EX_CME_SCOM_EIIR_PC_INTR_PENDING_C1                     , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PC_INTR_PENDING_C1 );
+REG64_FLD( EX_CME_SCOM_EIIR_SPECIAL_WAKEUP_C0                      , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SPECIAL_WAKEUP_C0 );
+REG64_FLD( EX_CME_SCOM_EIIR_SPECIAL_WAKEUP_C1                      , 15  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SPECIAL_WAKEUP_C1 );
+REG64_FLD( EX_CME_SCOM_EIIR_REG_WAKEUP_C0                          , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_REG_WAKEUP_C0 );
+REG64_FLD( EX_CME_SCOM_EIIR_REG_WAKEUP_C1                          , 17  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_REG_WAKEUP_C1 );
+REG64_FLD( EX_CME_SCOM_EIIR_PC_PM_STATE_ACTIVE_C0                  , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C0 );
+REG64_FLD( EX_CME_SCOM_EIIR_PC_PM_STATE_ACTIVE_C1                  , 21  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PC_PM_STATE_ACTIVE_C1 );
+REG64_FLD( EX_CME_SCOM_EIIR_L2_PURGE_DONE                          , 22  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L2_PURGE_DONE );
+REG64_FLD( EX_CME_SCOM_EIIR_NCU_PURGE_DONE                         , 23  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NCU_PURGE_DONE );
+REG64_FLD( EX_CME_SCOM_EIIR_CHTM_PURGE_DONE_C0                     , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CHTM_PURGE_DONE_C0 );
+REG64_FLD( EX_CME_SCOM_EIIR_CHTM_PURGE_DONE_C1                     , 25  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CHTM_PURGE_DONE_C1 );
+
+REG64_FLD( EQ_CME_SCOM_FLAGS_DATA                                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_CME_SCOM_FLAGS_DATA_LEN                              , 32  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EX_CME_SCOM_FLAGS_DATA                                  , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA       );
+REG64_FLD( EX_CME_SCOM_FLAGS_DATA_LEN                              , 32  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_CME_SCOM_FWMR_PMCR_OVERRIDE_EN                       , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMCR_OVERRIDE_EN );
+REG64_FLD( EQ_CME_SCOM_FWMR_PSCR_OVERRIDE_EN                       , 1   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSCR_OVERRIDE_EN );
+REG64_FLD( EQ_CME_SCOM_FWMR_PMSR_OVERRIDE_EN                       , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMSR_OVERRIDE_EN );
+REG64_FLD( EQ_CME_SCOM_FWMR_BCESCR_OVERRIDE_EN                     , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCESCR_OVERRIDE_EN );
+REG64_FLD( EQ_CME_SCOM_FWMR_IDR_LCL_SAMPLE_EN                      , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IDR_LCL_SAMPLE_EN );
+REG64_FLD( EQ_CME_SCOM_FWMR_VDM_LCL_SAMPLE_EN                      , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_VDM_LCL_SAMPLE_EN );
+REG64_FLD( EQ_CME_SCOM_FWMR_FREQ_LCL_SAMPLE_EN                     , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FREQ_LCL_SAMPLE_EN );
+REG64_FLD( EQ_CME_SCOM_FWMR_LOCK_PCB_ON_ERR                        , 7   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_LOCK_PCB_ON_ERR );
+REG64_FLD( EQ_CME_SCOM_FWMR_QUEUED_WR_EN                           , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_QUEUED_WR_EN );
+REG64_FLD( EQ_CME_SCOM_FWMR_QUEUED_RD_EN                           , 9   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_QUEUED_RD_EN );
+REG64_FLD( EQ_CME_SCOM_FWMR_MASK_PURGE_INTERFACE                   , 10  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASK_PURGE_INTERFACE );
+REG64_FLD( EQ_CME_SCOM_FWMR_IGNORE_PECE                            , 11  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IGNORE_PECE );
+REG64_FLD( EQ_CME_SCOM_FWMR_STOP_OVERRIDE_MODE                     , 16  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_STOP_OVERRIDE_MODE );
+REG64_FLD( EQ_CME_SCOM_FWMR_STOP_ACTIVE_MASK                       , 17  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_STOP_ACTIVE_MASK );
+REG64_FLD( EQ_CME_SCOM_FWMR_AUTO_STOP1_DISABLE                     , 18  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_AUTO_STOP1_DISABLE );
+REG64_FLD( EQ_CME_SCOM_FWMR_STOP1_ACTIVE_ENABLE                    , 19  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_STOP1_ACTIVE_ENABLE );
+REG64_FLD( EQ_CME_SCOM_FWMR_FENCE_EISR                             , 20  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FENCE_EISR );
+REG64_FLD( EQ_CME_SCOM_FWMR_PC_DISABLE_DROOP                       , 21  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PC_DISABLE_DROOP );
+REG64_FLD( EQ_CME_SCOM_FWMR_SPARE_22_23                            , 22  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_22_23 );
+REG64_FLD( EQ_CME_SCOM_FWMR_SPARE_22_23_LEN                        , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_22_23_LEN );
+REG64_FLD( EQ_CME_SCOM_FWMR_AVG_FREQ_TSEL                          , 24  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_AVG_FREQ_TSEL );
+REG64_FLD( EQ_CME_SCOM_FWMR_AVG_FREQ_TSEL_LEN                      , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_AVG_FREQ_TSEL_LEN );
+
+REG64_FLD( EX_CME_SCOM_FWMR_PMCR_OVERRIDE_EN                       , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMCR_OVERRIDE_EN );
+REG64_FLD( EX_CME_SCOM_FWMR_PSCR_OVERRIDE_EN                       , 1   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSCR_OVERRIDE_EN );
+REG64_FLD( EX_CME_SCOM_FWMR_PMSR_OVERRIDE_EN                       , 2   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMSR_OVERRIDE_EN );
+REG64_FLD( EX_CME_SCOM_FWMR_BCESCR_OVERRIDE_EN                     , 3   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCESCR_OVERRIDE_EN );
+REG64_FLD( EX_CME_SCOM_FWMR_IDR_LCL_SAMPLE_EN                      , 4   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IDR_LCL_SAMPLE_EN );
+REG64_FLD( EX_CME_SCOM_FWMR_VDM_LCL_SAMPLE_EN                      , 5   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_VDM_LCL_SAMPLE_EN );
+REG64_FLD( EX_CME_SCOM_FWMR_FREQ_LCL_SAMPLE_EN                     , 6   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FREQ_LCL_SAMPLE_EN );
+REG64_FLD( EX_CME_SCOM_FWMR_LOCK_PCB_ON_ERR                        , 7   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_LOCK_PCB_ON_ERR );
+REG64_FLD( EX_CME_SCOM_FWMR_QUEUED_WR_EN                           , 8   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_QUEUED_WR_EN );
+REG64_FLD( EX_CME_SCOM_FWMR_QUEUED_RD_EN                           , 9   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_QUEUED_RD_EN );
+REG64_FLD( EX_CME_SCOM_FWMR_MASK_PURGE_INTERFACE                   , 10  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASK_PURGE_INTERFACE );
+REG64_FLD( EX_CME_SCOM_FWMR_IGNORE_PECE                            , 11  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IGNORE_PECE );
+REG64_FLD( EX_CME_SCOM_FWMR_STOP_OVERRIDE_MODE                     , 16  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_STOP_OVERRIDE_MODE );
+REG64_FLD( EX_CME_SCOM_FWMR_STOP_ACTIVE_MASK                       , 17  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_STOP_ACTIVE_MASK );
+REG64_FLD( EX_CME_SCOM_FWMR_AUTO_STOP1_DISABLE                     , 18  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_AUTO_STOP1_DISABLE );
+REG64_FLD( EX_CME_SCOM_FWMR_STOP1_ACTIVE_ENABLE                    , 19  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_STOP1_ACTIVE_ENABLE );
+REG64_FLD( EX_CME_SCOM_FWMR_FENCE_EISR                             , 20  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FENCE_EISR );
+REG64_FLD( EX_CME_SCOM_FWMR_PC_DISABLE_DROOP                       , 21  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PC_DISABLE_DROOP );
+REG64_FLD( EX_CME_SCOM_FWMR_SPARE_22_23                            , 22  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_22_23 );
+REG64_FLD( EX_CME_SCOM_FWMR_SPARE_22_23_LEN                        , 2   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_22_23_LEN );
+REG64_FLD( EX_CME_SCOM_FWMR_AVG_FREQ_TSEL                          , 24  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_AVG_FREQ_TSEL );
+REG64_FLD( EX_CME_SCOM_FWMR_AVG_FREQ_TSEL_LEN                      , 4   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_AVG_FREQ_TSEL_LEN );
+
+REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD                , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD );
+REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN            , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN );
+REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD               , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD );
+REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN           , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN );
+REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                     , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_TIMER_MODE );
+REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                      , 33  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_CHAR_MODE );
+REG64_FLD( EQ_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE            , 34  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN        , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( EQ_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE                    , 36  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_CORE_DROPOUT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN                , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( EQ_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE                   , 38  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_CACHE_DROPOUT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_IDCR_SPARE                                  , 39  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE      );
+REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE                  , 40  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_NOTIFY_ENABLE );
+REG64_FLD( EQ_CME_SCOM_IDCR_SPARE41_43                             , 41  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( EQ_CME_SCOM_IDCR_SPARE41_43_LEN                         , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE                    , 59  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_SAMPLE_RATE );
+REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN                , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_SAMPLE_RATE_LEN );
+
+REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD                , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD );
+REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN            , 24  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN );
+REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD               , 24  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD );
+REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN           , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN );
+REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_TIMER_MODE                     , 32  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_TIMER_MODE );
+REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_CHAR_MODE                      , 33  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_CHAR_MODE );
+REG64_FLD( EX_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE            , 34  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE );
+REG64_FLD( EX_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN        , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( EX_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE                    , 36  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_CORE_DROPOUT_ENABLE );
+REG64_FLD( EX_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN                , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_CORE_DROPOUT_ENABLE_LEN );
+REG64_FLD( EX_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE                   , 38  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_CACHE_DROPOUT_ENABLE );
+REG64_FLD( EX_CME_SCOM_IDCR_SPARE                                  , 39  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE      );
+REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE                  , 40  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_NOTIFY_ENABLE );
+REG64_FLD( EX_CME_SCOM_IDCR_SPARE41_43                             , 41  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( EX_CME_SCOM_IDCR_SPARE41_43_LEN                         , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE                    , 59  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_SAMPLE_RATE );
+REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN                , 5   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROPOUT_SAMPLE_RATE_LEN );
+
+REG64_FLD( EQ_CME_SCOM_LFIR_PPE_INTERNAL_ERROR                     , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_INTERNAL_ERROR );
+REG64_FLD( EQ_CME_SCOM_LFIR_PPE_EXTERNAL_ERROR                     , 1   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_EXTERNAL_ERROR );
+REG64_FLD( EQ_CME_SCOM_LFIR_PPE_PROGRESS_ERROR                     , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_PROGRESS_ERROR );
+REG64_FLD( EQ_CME_SCOM_LFIR_PPE_BREAKPOINT_ERROR                   , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_BREAKPOINT_ERROR );
+REG64_FLD( EQ_CME_SCOM_LFIR_PPE_WATCHDOG                           , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_WATCHDOG );
+REG64_FLD( EQ_CME_SCOM_LFIR_PPE_HALTED                             , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_HALTED );
+REG64_FLD( EQ_CME_SCOM_LFIR_PPE_DEBUG_TRIGGER                      , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_DEBUG_TRIGGER );
+REG64_FLD( EQ_CME_SCOM_LFIR_SRAM_UE                                , 7   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_UE    );
+REG64_FLD( EQ_CME_SCOM_LFIR_SRAM_CE                                , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_CE    );
+REG64_FLD( EQ_CME_SCOM_LFIR_SRAM_SCRUB_ERR                         , 9   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SCRUB_ERR );
+REG64_FLD( EQ_CME_SCOM_LFIR_BCE_ERROR                              , 10  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCE_ERROR  );
+REG64_FLD( EQ_CME_SCOM_LFIR_SPARE11                                , 11  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE11    );
+REG64_FLD( EQ_CME_SCOM_LFIR_FIR_PARITY_ERR_DUP                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_PARITY_ERR_DUP );
+REG64_FLD( EQ_CME_SCOM_LFIR_FIR_PARITY_ERR                         , 13  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_PARITY_ERR );
+
+REG64_FLD( EX_CME_SCOM_LFIR_PPE_INTERNAL_ERROR                     , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_INTERNAL_ERROR );
+REG64_FLD( EX_CME_SCOM_LFIR_PPE_EXTERNAL_ERROR                     , 1   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_EXTERNAL_ERROR );
+REG64_FLD( EX_CME_SCOM_LFIR_PPE_PROGRESS_ERROR                     , 2   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_PROGRESS_ERROR );
+REG64_FLD( EX_CME_SCOM_LFIR_PPE_BREAKPOINT_ERROR                   , 3   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_BREAKPOINT_ERROR );
+REG64_FLD( EX_CME_SCOM_LFIR_PPE_WATCHDOG                           , 4   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_WATCHDOG );
+REG64_FLD( EX_CME_SCOM_LFIR_PPE_HALTED                             , 5   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_HALTED );
+REG64_FLD( EX_CME_SCOM_LFIR_PPE_DEBUG_TRIGGER                      , 6   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_DEBUG_TRIGGER );
+REG64_FLD( EX_CME_SCOM_LFIR_SRAM_UE                                , 7   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_UE    );
+REG64_FLD( EX_CME_SCOM_LFIR_SRAM_CE                                , 8   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_CE    );
+REG64_FLD( EX_CME_SCOM_LFIR_SRAM_SCRUB_ERR                         , 9   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SCRUB_ERR );
+REG64_FLD( EX_CME_SCOM_LFIR_BCE_ERROR                              , 10  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_BCE_ERROR  );
+REG64_FLD( EX_CME_SCOM_LFIR_SPARE11                                , 11  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE11    );
+REG64_FLD( EX_CME_SCOM_LFIR_FIR_PARITY_ERR_DUP                     , 12  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_PARITY_ERR_DUP );
+REG64_FLD( EX_CME_SCOM_LFIR_FIR_PARITY_ERR                         , 13  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_PARITY_ERR );
+
+REG64_FLD( EQ_CME_SCOM_LFIRACT0_FIR_ACTION0                        , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION0 );
+REG64_FLD( EQ_CME_SCOM_LFIRACT0_FIR_ACTION0_LEN                    , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION0_LEN );
+
+REG64_FLD( EX_CME_SCOM_LFIRACT0_FIR_ACTION0                        , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION0 );
+REG64_FLD( EX_CME_SCOM_LFIRACT0_FIR_ACTION0_LEN                    , 14  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION0_LEN );
+
+REG64_FLD( EQ_CME_SCOM_LFIRACT1_FIR_ACTION1                        , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION1 );
+REG64_FLD( EQ_CME_SCOM_LFIRACT1_FIR_ACTION1_LEN                    , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION1_LEN );
+
+REG64_FLD( EX_CME_SCOM_LFIRACT1_FIR_ACTION1                        , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION1 );
+REG64_FLD( EX_CME_SCOM_LFIRACT1_FIR_ACTION1_LEN                    , 14  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FIR_ACTION1_LEN );
+
+REG64_FLD( EQ_CME_SCOM_LFIRMASK_FIR_MASK                           , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_MASK   );
+REG64_FLD( EQ_CME_SCOM_LFIRMASK_FIR_MASK_LEN                       , 14  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_MASK_LEN );
+
+REG64_FLD( EX_CME_SCOM_LFIRMASK_FIR_MASK                           , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_MASK   );
+REG64_FLD( EX_CME_SCOM_LFIRMASK_FIR_MASK_LEN                       , 14  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FIR_MASK_LEN );
+
+REG64_FLD( EQ_CME_SCOM_PMCRS0_DATA                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_CME_SCOM_PMCRS0_DATA_LEN                             , 64  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EX_CME_SCOM_PMCRS0_DATA                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EX_CME_SCOM_PMCRS0_DATA_LEN                             , 64  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_CME_SCOM_PMCRS1_DATA                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_CME_SCOM_PMCRS1_DATA_LEN                             , 64  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EX_CME_SCOM_PMCRS1_DATA                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EX_CME_SCOM_PMCRS1_DATA_LEN                             , 64  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_CME_SCOM_PMSRS0_DATA                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_CME_SCOM_PMSRS0_DATA_LEN                             , 64  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EX_CME_SCOM_PMSRS0_DATA                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EX_CME_SCOM_PMSRS0_DATA_LEN                             , 64  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_CME_SCOM_PMSRS1_DATA                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_CME_SCOM_PMSRS1_DATA_LEN                             , 64  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EX_CME_SCOM_PMSRS1_DATA                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EX_CME_SCOM_PMSRS1_DATA_LEN                             , 64  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_CME_SCOM_PSCRS00_SPARE0                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EX_CME_SCOM_PSCRS00_SPARE0                              , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EX_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EQ_CME_SCOM_PSCRS01_SPARE0                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EX_CME_SCOM_PSCRS01_SPARE0                              , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EX_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EQ_CME_SCOM_PSCRS02_SPARE0                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EX_CME_SCOM_PSCRS02_SPARE0                              , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EX_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EQ_CME_SCOM_PSCRS03_SPARE0                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EX_CME_SCOM_PSCRS03_SPARE0                              , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EX_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EQ_CME_SCOM_PSCRS10_SPARE0                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EX_CME_SCOM_PSCRS10_SPARE0                              , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EX_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EQ_CME_SCOM_PSCRS11_SPARE0                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EX_CME_SCOM_PSCRS11_SPARE0                              , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EX_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EQ_CME_SCOM_PSCRS12_SPARE0                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EX_CME_SCOM_PSCRS12_SPARE0                              , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EX_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EQ_CME_SCOM_PSCRS13_SPARE0                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EQ_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EX_CME_SCOM_PSCRS13_SPARE0                              , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE0     );
+REG64_FLD( EX_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N               , 1   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OS_STATUS_DISABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N               , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STATE_LOSS_ENABLE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N                  , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXIT_CRITERION_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N              , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWER_SAVING_LIMIT_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE                , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_VIRT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE                 , 9   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EBB_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE              , 10  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_RESUME_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE                     , 11  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXT_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE                     , 12  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DEC_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE                     , 13  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HMI_EXIT_ENABLE );
+REG64_FLD( EX_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N           , 14  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN       , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N               , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN           , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN );
+REG64_FLD( EX_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N              , 20  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N );
+REG64_FLD( EX_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN );
+
+REG64_FLD( EQ_CME_SCOM_QFMR_TIMEBASE                               , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( EQ_CME_SCOM_QFMR_TIMEBASE_LEN                           , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( EQ_CME_SCOM_QFMR_CYCLES                                 , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CYCLES     );
+REG64_FLD( EQ_CME_SCOM_QFMR_CYCLES_LEN                             , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CYCLES_LEN );
+
+REG64_FLD( EX_CME_SCOM_QFMR_TIMEBASE                               , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( EX_CME_SCOM_QFMR_TIMEBASE_LEN                           , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( EX_CME_SCOM_QFMR_CYCLES                                 , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CYCLES     );
+REG64_FLD( EX_CME_SCOM_QFMR_CYCLES_LEN                             , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CYCLES_LEN );
+
+REG64_FLD( EQ_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT             , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT );
+REG64_FLD( EQ_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN         , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( EQ_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT            , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT );
+REG64_FLD( EQ_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN        , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( EQ_CME_SCOM_QIDSR_DROPOUT_SAMPLE                        , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DROPOUT_SAMPLE );
+REG64_FLD( EQ_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN                    , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DROPOUT_SAMPLE_LEN );
+
+REG64_FLD( EX_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT             , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT );
+REG64_FLD( EX_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN         , 24  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN );
+REG64_FLD( EX_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT            , 24  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT );
+REG64_FLD( EX_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN        , 8   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN );
+REG64_FLD( EX_CME_SCOM_QIDSR_DROPOUT_SAMPLE                        , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DROPOUT_SAMPLE );
+REG64_FLD( EX_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN                    , 3   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DROPOUT_SAMPLE_LEN );
+
+REG64_FLD( EQ_CME_SCOM_SICR_PM_ENTRY_ACK_C0                        , 0   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PM_ENTRY_ACK_C0 );
+REG64_FLD( EQ_CME_SCOM_SICR_PM_ENTRY_ACK_C1                        , 1   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PM_ENTRY_ACK_C1 );
+REG64_FLD( EQ_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0                 , 2   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( EQ_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1                 , 3   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( EQ_CME_SCOM_SICR_PM_EXIT_C0                             , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PM_EXIT_C0 );
+REG64_FLD( EQ_CME_SCOM_SICR_PM_EXIT_C1                             , 5   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PM_EXIT_C1 );
+REG64_FLD( EQ_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0               , 6   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( EQ_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1               , 7   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( EQ_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0                , 8   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( EQ_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1                , 9   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( EQ_CME_SCOM_SICR_PCBMUX_REQ_C0                          , 10  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( EQ_CME_SCOM_SICR_PCBMUX_REQ_C1                          , 11  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( EQ_CME_SCOM_SICR_RESERVED_12_15                         , 12  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( EQ_CME_SCOM_SICR_RESERVED_12_15_LEN                     , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( EQ_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0                   , 16  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_SPECIAL_WKUP_DONE_C0 );
+REG64_FLD( EQ_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1                   , 17  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_SPECIAL_WKUP_DONE_C1 );
+REG64_FLD( EQ_CME_SCOM_SICR_L2_PURGE                               , 18  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L2_PURGE   );
+REG64_FLD( EQ_CME_SCOM_SICR_L2_PURGE_ABORT                         , 19  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( EQ_CME_SCOM_SICR_RESERVED20                             , 20  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED20 );
+REG64_FLD( EQ_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                      , 21  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( EQ_CME_SCOM_SICR_NCU_PURGE                              , 22  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_NCU_PURGE  );
+REG64_FLD( EQ_CME_SCOM_SICR_NCU_PURGE_ABORT                        , 23  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( EQ_CME_SCOM_SICR_CHTM_PURGE_C0                          , 24  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( EQ_CME_SCOM_SICR_CHTM_PURGE_C1                          , 25  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( EQ_CME_SCOM_SICR_HMI_REQUEST_C0                         , 26  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( EQ_CME_SCOM_SICR_HMI_REQUEST_C1                         , 27  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( EQ_CME_SCOM_SICR_PPM_SPARE_OUT_C0                       , 28  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( EQ_CME_SCOM_SICR_PPM_SPARE_OUT_C1                       , 29  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( EQ_CME_SCOM_SICR_RESERVED_30_31                         , 30  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED_30_31 );
+REG64_FLD( EQ_CME_SCOM_SICR_RESERVED_30_31_LEN                     , 2   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED_30_31_LEN );
+
+REG64_FLD( EX_CME_SCOM_SICR_PM_ENTRY_ACK_C0                        , 0   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_PM_ENTRY_ACK_C0 );
+REG64_FLD( EX_CME_SCOM_SICR_PM_ENTRY_ACK_C1                        , 1   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_PM_ENTRY_ACK_C1 );
+REG64_FLD( EX_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0                 , 2   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C0 );
+REG64_FLD( EX_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1                 , 3   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_PM_BLOCK_INTERRUPTS_C1 );
+REG64_FLD( EX_CME_SCOM_SICR_PM_EXIT_C0                             , 4   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_PM_EXIT_C0 );
+REG64_FLD( EX_CME_SCOM_SICR_PM_EXIT_C1                             , 5   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_PM_EXIT_C1 );
+REG64_FLD( EX_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0               , 6   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( EX_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1               , 7   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_PCC_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( EX_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0                , 8   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C0 );
+REG64_FLD( EX_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1                , 9   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_L2_CORE_INTF_QUIESCE_C1 );
+REG64_FLD( EX_CME_SCOM_SICR_PCBMUX_REQ_C0                          , 10  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_PCBMUX_REQ_C0 );
+REG64_FLD( EX_CME_SCOM_SICR_PCBMUX_REQ_C1                          , 11  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_PCBMUX_REQ_C1 );
+REG64_FLD( EX_CME_SCOM_SICR_RESERVED_12_15                         , 12  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED_12_15 );
+REG64_FLD( EX_CME_SCOM_SICR_RESERVED_12_15_LEN                     , 4   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED_12_15_LEN );
+REG64_FLD( EX_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0                   , 16  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_SPECIAL_WKUP_DONE_C0 );
+REG64_FLD( EX_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1                   , 17  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_SPECIAL_WKUP_DONE_C1 );
+REG64_FLD( EX_CME_SCOM_SICR_L2_PURGE                               , 18  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_L2_PURGE   );
+REG64_FLD( EX_CME_SCOM_SICR_L2_PURGE_ABORT                         , 19  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_L2_PURGE_ABORT );
+REG64_FLD( EX_CME_SCOM_SICR_RESERVED20                             , 20  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED20 );
+REG64_FLD( EX_CME_SCOM_SICR_NCU_TLBIE_QUIESCE                      , 21  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_NCU_TLBIE_QUIESCE );
+REG64_FLD( EX_CME_SCOM_SICR_NCU_PURGE                              , 22  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_NCU_PURGE  );
+REG64_FLD( EX_CME_SCOM_SICR_NCU_PURGE_ABORT                        , 23  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_NCU_PURGE_ABORT );
+REG64_FLD( EX_CME_SCOM_SICR_CHTM_PURGE_C0                          , 24  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_CHTM_PURGE_C0 );
+REG64_FLD( EX_CME_SCOM_SICR_CHTM_PURGE_C1                          , 25  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_CHTM_PURGE_C1 );
+REG64_FLD( EX_CME_SCOM_SICR_HMI_REQUEST_C0                         , 26  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_HMI_REQUEST_C0 );
+REG64_FLD( EX_CME_SCOM_SICR_HMI_REQUEST_C1                         , 27  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_HMI_REQUEST_C1 );
+REG64_FLD( EX_CME_SCOM_SICR_PPM_SPARE_OUT_C0                       , 28  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_PPM_SPARE_OUT_C0 );
+REG64_FLD( EX_CME_SCOM_SICR_PPM_SPARE_OUT_C1                       , 29  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_PPM_SPARE_OUT_C1 );
+REG64_FLD( EX_CME_SCOM_SICR_RESERVED_30_31                         , 30  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED_30_31 );
+REG64_FLD( EX_CME_SCOM_SICR_RESERVED_30_31_LEN                     , 2   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED_30_31_LEN );
+
+REG64_FLD( EQ_CME_SCOM_SRTCH0_DATA                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_CME_SCOM_SRTCH0_DATA_LEN                             , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EX_CME_SCOM_SRTCH0_DATA                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EX_CME_SCOM_SRTCH0_DATA_LEN                             , 32  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_CME_SCOM_SRTCH1_DATA                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_CME_SCOM_SRTCH1_DATA_LEN                             , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EX_CME_SCOM_SRTCH1_DATA                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EX_CME_SCOM_SRTCH1_DATA_LEN                             , 32  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SMALL_EVENT_THRESHOLD );
+REG64_FLD( EQ_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN              , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SMALL_EVENT_THRESHOLD_LEN );
+REG64_FLD( EQ_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD                  , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LARGE_EVENT_THRESHOLD );
+REG64_FLD( EQ_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN              , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LARGE_EVENT_THRESHOLD_LEN );
+REG64_FLD( EQ_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD                , 28  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD );
+REG64_FLD( EQ_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN            , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD_LEN );
+REG64_FLD( EQ_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                     , 36  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROOP_PROFILE_TYPE );
+REG64_FLD( EQ_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN                 , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROOP_PROFILE_TYPE_LEN );
+REG64_FLD( EQ_CME_SCOM_VCCR_DROOP_TIMER_MODE                       , 38  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROOP_TIMER_MODE );
+REG64_FLD( EQ_CME_SCOM_VCCR_DROOP_CHAR_MODE                        , 39  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROOP_CHAR_MODE );
+REG64_FLD( EQ_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE                    , 40  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROOP_NOTIFY_ENABLE );
+REG64_FLD( EQ_CME_SCOM_VCCR_SPARE41_43                             , 41  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( EQ_CME_SCOM_VCCR_SPARE41_43_LEN                         , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( EQ_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                      , 59  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROOP_SAMPLE_RATE );
+REG64_FLD( EQ_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN                  , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROOP_SAMPLE_RATE_LEN );
+
+REG64_FLD( EX_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD                  , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SMALL_EVENT_THRESHOLD );
+REG64_FLD( EX_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN              , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SMALL_EVENT_THRESHOLD_LEN );
+REG64_FLD( EX_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD                  , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LARGE_EVENT_THRESHOLD );
+REG64_FLD( EX_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN              , 12  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_LARGE_EVENT_THRESHOLD_LEN );
+REG64_FLD( EX_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD                , 28  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD );
+REG64_FLD( EX_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN            , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_EXTREME_EVENT_THRESHOLD_LEN );
+REG64_FLD( EX_CME_SCOM_VCCR_DROOP_PROFILE_TYPE                     , 36  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROOP_PROFILE_TYPE );
+REG64_FLD( EX_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN                 , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROOP_PROFILE_TYPE_LEN );
+REG64_FLD( EX_CME_SCOM_VCCR_DROOP_TIMER_MODE                       , 38  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROOP_TIMER_MODE );
+REG64_FLD( EX_CME_SCOM_VCCR_DROOP_CHAR_MODE                        , 39  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROOP_CHAR_MODE );
+REG64_FLD( EX_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE                    , 40  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROOP_NOTIFY_ENABLE );
+REG64_FLD( EX_CME_SCOM_VCCR_SPARE41_43                             , 41  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE41_43 );
+REG64_FLD( EX_CME_SCOM_VCCR_SPARE41_43_LEN                         , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SPARE41_43_LEN );
+REG64_FLD( EX_CME_SCOM_VCCR_DROOP_SAMPLE_RATE                      , 59  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROOP_SAMPLE_RATE );
+REG64_FLD( EX_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN                  , 5   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DROOP_SAMPLE_RATE_LEN );
+
+REG64_FLD( EQ_CME_SCOM_VCTR_VDM_EXTREME_DROOP_THRESHOLD            , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_EXTREME_DROOP_THRESHOLD );
+REG64_FLD( EQ_CME_SCOM_VCTR_VDM_EXTREME_DROOP_THRESHOLD_LEN        , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_EXTREME_DROOP_THRESHOLD_LEN );
+REG64_FLD( EQ_CME_SCOM_VCTR_VDM_LARGE_DROOP_THRESHOLD              , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_LARGE_DROOP_THRESHOLD );
+REG64_FLD( EQ_CME_SCOM_VCTR_VDM_LARGE_DROOP_THRESHOLD_LEN          , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_LARGE_DROOP_THRESHOLD_LEN );
+REG64_FLD( EQ_CME_SCOM_VCTR_VDM_SMALL_DROOP_THRESHOLD              , 40  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_SMALL_DROOP_THRESHOLD );
+REG64_FLD( EQ_CME_SCOM_VCTR_VDM_SMALL_DROOP_THRESHOLD_LEN          , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_SMALL_DROOP_THRESHOLD_LEN );
+
+REG64_FLD( EX_CME_SCOM_VCTR_VDM_EXTREME_DROOP_THRESHOLD            , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_EXTREME_DROOP_THRESHOLD );
+REG64_FLD( EX_CME_SCOM_VCTR_VDM_EXTREME_DROOP_THRESHOLD_LEN        , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_EXTREME_DROOP_THRESHOLD_LEN );
+REG64_FLD( EX_CME_SCOM_VCTR_VDM_LARGE_DROOP_THRESHOLD              , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_LARGE_DROOP_THRESHOLD );
+REG64_FLD( EX_CME_SCOM_VCTR_VDM_LARGE_DROOP_THRESHOLD_LEN          , 24  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_LARGE_DROOP_THRESHOLD_LEN );
+REG64_FLD( EX_CME_SCOM_VCTR_VDM_SMALL_DROOP_THRESHOLD              , 40  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_SMALL_DROOP_THRESHOLD );
+REG64_FLD( EX_CME_SCOM_VCTR_VDM_SMALL_DROOP_THRESHOLD_LEN          , 24  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_SMALL_DROOP_THRESHOLD_LEN );
+
+REG64_FLD( EQ_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR );
+REG64_FLD( EQ_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN              , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR_LEN );
+REG64_FLD( EQ_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR                    , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( EQ_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN                , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( EQ_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR                    , 40  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( EQ_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN                , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( EX_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR                  , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR );
+REG64_FLD( EX_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN              , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_EXTREME_DROOP_CTR_LEN );
+REG64_FLD( EX_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR                    , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_LARGE_DROOP_CTR );
+REG64_FLD( EX_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN                , 24  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_LARGE_DROOP_CTR_LEN );
+REG64_FLD( EX_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR                    , 40  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_SMALL_DROOP_CTR );
+REG64_FLD( EX_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN                , 24  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_SMALL_DROOP_CTR_LEN );
+
+REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY            , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN        , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA                 , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN             , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA                 , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN             , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA                 , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN             , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA                 , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN             , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA                 , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN             , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY             , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN         , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA                  , 36  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN              , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA                  , 40  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN              , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA                  , 44  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN              , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA                  , 48  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN              , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA                  , 52  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN              , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY            , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY );
+REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN        , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA                 , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA );
+REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN             , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CACHE_VDM_DATA_LEN );
+REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA                 , 8   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA );
+REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN             , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE0_VDM_DATA_LEN );
+REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA                 , 12  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA );
+REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN             , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE1_VDM_DATA_LEN );
+REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA                 , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA );
+REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN             , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE2_VDM_DATA_LEN );
+REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA                 , 20  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA );
+REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN             , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_INSTANT_CORE3_VDM_DATA_LEN );
+REG64_FLD( EX_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY             , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY );
+REG64_FLD( EX_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN         , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN );
+REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA                  , 36  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CACHE_VDM_DATA );
+REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN              , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CACHE_VDM_DATA_LEN );
+REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA                  , 40  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE0_VDM_DATA );
+REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN              , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE0_VDM_DATA_LEN );
+REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA                  , 44  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE1_VDM_DATA );
+REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN              , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE1_VDM_DATA_LEN );
+REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA                  , 48  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE2_VDM_DATA );
+REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN              , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE2_VDM_DATA_LEN );
+REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA                  , 52  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE3_VDM_DATA );
+REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN              , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STICKY_CORE3_VDM_DATA_LEN );
+
+REG64_FLD( EQ_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR );
+REG64_FLD( EQ_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN              , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN );
+REG64_FLD( EQ_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR                , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR );
+REG64_FLD( EQ_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN            , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( EQ_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR                 , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR );
+REG64_FLD( EQ_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN             , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR_LEN );
+REG64_FLD( EQ_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR                , 44  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR );
+REG64_FLD( EQ_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN            , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( EQ_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR                , 56  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR );
+REG64_FLD( EQ_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN            , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN );
+
+REG64_FLD( EX_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR                  , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR );
+REG64_FLD( EX_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN              , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN );
+REG64_FLD( EX_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR                , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR );
+REG64_FLD( EX_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN            , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( EX_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR                 , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR );
+REG64_FLD( EX_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN             , 12  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LARGER_DROOP_EVENT_CTR_LEN );
+REG64_FLD( EX_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR                , 44  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR );
+REG64_FLD( EX_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN            , 12  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN );
+REG64_FLD( EX_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR                , 56  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR );
+REG64_FLD( EX_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN            , 8   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN );
+
+REG64_FLD( EQ_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                       , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( EQ_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN                   , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( EQ_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                       , 40  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( EQ_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN                   , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( EX_CME_SCOM_VNCR_VDM_NO_DROOP_CTR                       , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_NO_DROOP_CTR );
+REG64_FLD( EX_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN                   , 24  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_NO_DROOP_CTR_LEN );
+REG64_FLD( EX_CME_SCOM_VNCR_VDM_OVERVOLT_CTR                       , 40  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_OVERVOLT_CTR );
+REG64_FLD( EX_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN                   , 24  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VDM_OVERVOLT_CTR_LEN );
+
+REG64_FLD( EQ_CME_SCOM_XIPCBQ0_PCBQ_N_INFO                         , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCBQ_N_INFO );
+REG64_FLD( EQ_CME_SCOM_XIPCBQ0_PCBQ_N_INFO_LEN                     , 26  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCBQ_N_INFO_LEN );
+
+REG64_FLD( EX_CME_SCOM_XIPCBQ0_PCBQ_N_INFO                         , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCBQ_N_INFO );
+REG64_FLD( EX_CME_SCOM_XIPCBQ0_PCBQ_N_INFO_LEN                     , 26  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCBQ_N_INFO_LEN );
+
+REG64_FLD( EQ_CME_SCOM_XIPCBQ1_PCBQ_N_INFO                         , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCBQ_N_INFO );
+REG64_FLD( EQ_CME_SCOM_XIPCBQ1_PCBQ_N_INFO_LEN                     , 26  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCBQ_N_INFO_LEN );
+
+REG64_FLD( EX_CME_SCOM_XIPCBQ1_PCBQ_N_INFO                         , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCBQ_N_INFO );
+REG64_FLD( EX_CME_SCOM_XIPCBQ1_PCBQ_N_INFO_LEN                     , 26  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCBQ_N_INFO_LEN );
+
+REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC                   , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE0_SEL_DC );
+REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN               , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_6C                               , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_6C );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_7C                               , 7   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_7C );
+REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC                   , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE1_SEL_DC );
+REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN               , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_14C                              , 14  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_14C );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_15C                              , 15  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_15C );
+REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC                   , 16  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE2_SEL_DC );
+REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN               , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_22C                              , 22  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_22C );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_23C                              , 23  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_23C );
+REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC                   , 24  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE3_SEL_DC );
+REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN               , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_30C                              , 30  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_30C );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_31C                              , 31  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_31C );
+REG64_FLD( EQ_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC                  , 32  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC );
+REG64_FLD( EQ_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC                   , 33  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_SCAN_PROTECT_DC );
+REG64_FLD( EQ_CPLT_CONF0_CTRL_CC_SDIS_DC_N                         , 34  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_SDIS_DC_N );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_TEST_CONTROL_35C                 , 35  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_35C );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_TEST_CONTROL_36C                 , 36  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_36C );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_TEST_CONTROL_37C                 , 37  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_37C );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_TEST_CONTROL_38C                 , 38  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_38C );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_TEST_CONTROL_39C                 , 39  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_39C );
+REG64_FLD( EQ_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC             , 40  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC );
+REG64_FLD( EQ_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC        , 41  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_42C                              , 42  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_42C );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_43C                              , 43  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_43C );
+REG64_FLD( EQ_CPLT_CONF0_FREE_USAGE_44C                            , 44  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_44C );
+REG64_FLD( EQ_CPLT_CONF0_FREE_USAGE_45C                            , 45  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_45C );
+REG64_FLD( EQ_CPLT_CONF0_FREE_USAGE_46C                            , 46  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_46C );
+REG64_FLD( EQ_CPLT_CONF0_FREE_USAGE_47C                            , 47  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_47C );
+REG64_FLD( EQ_CPLT_CONF0_TC_UNIT_GROUP_ID_DC                       , 48  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_GROUP_ID_DC );
+REG64_FLD( EQ_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN                   , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_GROUP_ID_DC_LEN );
+REG64_FLD( EQ_CPLT_CONF0_TC_UNIT_CHIP_ID_DC                        , 52  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_CHIP_ID_DC );
+REG64_FLD( EQ_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN                    , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_CHIP_ID_DC_LEN );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_ID_55C                           , 55  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_55C );
+REG64_FLD( EQ_CPLT_CONF0_TC_UNIT_SYS_ID_DC                         , 56  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_SYS_ID_DC );
+REG64_FLD( EQ_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN                     , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_SYS_ID_DC_LEN );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_ID_61C                           , 61  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_61C );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_ID_62C                           , 62  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_62C );
+REG64_FLD( EQ_CPLT_CONF0_RESERVED_ID_63C                           , 63  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_63C );
+
+REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC                   , 0   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE0_SEL_DC );
+REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN               , 6   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_6C                               , 6   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_6C );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_7C                               , 7   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_7C );
+REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC                   , 8   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE1_SEL_DC );
+REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN               , 6   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_14C                              , 14  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_14C );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_15C                              , 15  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_15C );
+REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC                   , 16  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE2_SEL_DC );
+REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN               , 6   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_22C                              , 22  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_22C );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_23C                              , 23  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_23C );
+REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC                   , 24  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE3_SEL_DC );
+REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN               , 6   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_30C                              , 30  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_30C );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_31C                              , 31  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_31C );
+REG64_FLD( EX_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC                  , 32  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC );
+REG64_FLD( EX_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC                   , 33  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_SCAN_PROTECT_DC );
+REG64_FLD( EX_CPLT_CONF0_CTRL_CC_SDIS_DC_N                         , 34  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_SDIS_DC_N );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_TEST_CONTROL_35C                 , 35  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_35C );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_TEST_CONTROL_36C                 , 36  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_36C );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_TEST_CONTROL_37C                 , 37  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_37C );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_TEST_CONTROL_38C                 , 38  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_38C );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_TEST_CONTROL_39C                 , 39  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_39C );
+REG64_FLD( EX_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC             , 40  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC );
+REG64_FLD( EX_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC        , 41  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_42C                              , 42  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_42C );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_43C                              , 43  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_43C );
+REG64_FLD( EX_CPLT_CONF0_FREE_USAGE_44C                            , 44  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_44C );
+REG64_FLD( EX_CPLT_CONF0_FREE_USAGE_45C                            , 45  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_45C );
+REG64_FLD( EX_CPLT_CONF0_FREE_USAGE_46C                            , 46  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_46C );
+REG64_FLD( EX_CPLT_CONF0_FREE_USAGE_47C                            , 47  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_47C );
+REG64_FLD( EX_CPLT_CONF0_TC_UNIT_GROUP_ID_DC                       , 48  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_GROUP_ID_DC );
+REG64_FLD( EX_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN                   , 4   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_GROUP_ID_DC_LEN );
+REG64_FLD( EX_CPLT_CONF0_TC_UNIT_CHIP_ID_DC                        , 52  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_CHIP_ID_DC );
+REG64_FLD( EX_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN                    , 3   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_CHIP_ID_DC_LEN );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_ID_55C                           , 55  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_55C );
+REG64_FLD( EX_CPLT_CONF0_TC_UNIT_SYS_ID_DC                         , 56  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_SYS_ID_DC );
+REG64_FLD( EX_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN                     , 5   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_SYS_ID_DC_LEN );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_ID_61C                           , 61  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_61C );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_ID_62C                           , 62  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_62C );
+REG64_FLD( EX_CPLT_CONF0_RESERVED_ID_63C                           , 63  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_63C );
+
+REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC                    , 0   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE0_SEL_DC );
+REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN                , 6   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN );
+REG64_FLD( C_CPLT_CONF0_RESERVED_6C                                , 6   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_6C );
+REG64_FLD( C_CPLT_CONF0_RESERVED_7C                                , 7   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_7C );
+REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC                    , 8   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE1_SEL_DC );
+REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN                , 6   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN );
+REG64_FLD( C_CPLT_CONF0_RESERVED_14C                               , 14  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_14C );
+REG64_FLD( C_CPLT_CONF0_RESERVED_15C                               , 15  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_15C );
+REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC                    , 16  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE2_SEL_DC );
+REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN                , 6   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN );
+REG64_FLD( C_CPLT_CONF0_RESERVED_22C                               , 22  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_22C );
+REG64_FLD( C_CPLT_CONF0_RESERVED_23C                               , 23  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_23C );
+REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC                    , 24  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE3_SEL_DC );
+REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN                , 6   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN );
+REG64_FLD( C_CPLT_CONF0_RESERVED_30C                               , 30  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_30C );
+REG64_FLD( C_CPLT_CONF0_RESERVED_31C                               , 31  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_31C );
+REG64_FLD( C_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC                   , 32  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC );
+REG64_FLD( C_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC                    , 33  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_SCAN_PROTECT_DC );
+REG64_FLD( C_CPLT_CONF0_CTRL_CC_SDIS_DC_N                          , 34  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_SDIS_DC_N );
+REG64_FLD( C_CPLT_CONF0_RESERVED_TEST_CONTROL_35C                  , 35  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_35C );
+REG64_FLD( C_CPLT_CONF0_RESERVED_TEST_CONTROL_36C                  , 36  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_36C );
+REG64_FLD( C_CPLT_CONF0_RESERVED_TEST_CONTROL_37C                  , 37  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_37C );
+REG64_FLD( C_CPLT_CONF0_RESERVED_TEST_CONTROL_38C                  , 38  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_38C );
+REG64_FLD( C_CPLT_CONF0_RESERVED_TEST_CONTROL_39C                  , 39  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_TEST_CONTROL_39C );
+REG64_FLD( C_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC              , 40  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC );
+REG64_FLD( C_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC         , 41  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC );
+REG64_FLD( C_CPLT_CONF0_RESERVED_42C                               , 42  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_42C );
+REG64_FLD( C_CPLT_CONF0_RESERVED_43C                               , 43  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_43C );
+REG64_FLD( C_CPLT_CONF0_FREE_USAGE_44C                             , 44  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_44C );
+REG64_FLD( C_CPLT_CONF0_FREE_USAGE_45C                             , 45  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_45C );
+REG64_FLD( C_CPLT_CONF0_FREE_USAGE_46C                             , 46  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_46C );
+REG64_FLD( C_CPLT_CONF0_FREE_USAGE_47C                             , 47  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_47C );
+REG64_FLD( C_CPLT_CONF0_TC_UNIT_GROUP_ID_DC                        , 48  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_GROUP_ID_DC );
+REG64_FLD( C_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN                    , 4   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_GROUP_ID_DC_LEN );
+REG64_FLD( C_CPLT_CONF0_TC_UNIT_CHIP_ID_DC                         , 52  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_CHIP_ID_DC );
+REG64_FLD( C_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN                     , 3   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_CHIP_ID_DC_LEN );
+REG64_FLD( C_CPLT_CONF0_RESERVED_ID_55C                            , 55  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_55C );
+REG64_FLD( C_CPLT_CONF0_TC_UNIT_SYS_ID_DC                          , 56  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_SYS_ID_DC );
+REG64_FLD( C_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN                      , 5   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_SYS_ID_DC_LEN );
+REG64_FLD( C_CPLT_CONF0_RESERVED_ID_61C                            , 61  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_61C );
+REG64_FLD( C_CPLT_CONF0_RESERVED_ID_62C                            , 62  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_62C );
+REG64_FLD( C_CPLT_CONF0_RESERVED_ID_63C                            , 63  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_ID_63C );
+
+REG64_FLD( EQ_CPLT_CONF1_UNUSED_0D                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_0D  );
+REG64_FLD( EQ_CPLT_CONF1_UNUSED_1D                                 , 1   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_1D  );
+REG64_FLD( EQ_CPLT_CONF1_UNUSED_2D                                 , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_2D  );
+REG64_FLD( EQ_CPLT_CONF1_UNUSED_3D                                 , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_3D  );
+REG64_FLD( EQ_CPLT_CONF1_TC_PBIOO0_IOVALID                         , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PBIOO0_IOVALID );
+REG64_FLD( EQ_CPLT_CONF1_TC_PBIOO1_IOVALID                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PBIOO1_IOVALID );
+REG64_FLD( EQ_CPLT_CONF1_IOVALID_6D                                , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_IOVALID_6D );
+REG64_FLD( EQ_CPLT_CONF1_IOVALID_7D                                , 7   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_IOVALID_7D );
+REG64_FLD( EQ_CPLT_CONF1_IOVALID_8D                                , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_IOVALID_8D );
+REG64_FLD( EQ_CPLT_CONF1_IOVALID_9D                                , 9   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_IOVALID_9D );
+REG64_FLD( EQ_CPLT_CONF1_IOVALID_10D                               , 10  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_IOVALID_10D );
+REG64_FLD( EQ_CPLT_CONF1_IOVALID_11D                               , 11  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_IOVALID_11D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_12D                            , 12  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_12D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_13D                            , 13  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_13D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_14D                            , 14  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_14D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_15D                            , 15  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_15D );
+REG64_FLD( EQ_CPLT_CONF1_TC_OB_RATIO_DC                            , 16  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_OB_RATIO_DC );
+REG64_FLD( EQ_CPLT_CONF1_TC_OB_RATIO_DC_LEN                        , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_OB_RATIO_DC_LEN );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_18D                            , 18  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_18D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_19D                            , 19  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_19D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_20D                            , 20  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_20D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_21D                            , 21  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_21D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_22D                            , 22  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_22D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_23D                            , 23  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_23D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_24D                            , 24  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_24D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_25D                            , 25  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_25D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_26D                            , 26  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_26D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_27D                            , 27  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_27D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_28D                            , 28  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_28D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_29D                            , 29  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_29D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_30D                            , 30  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_30D );
+REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_31D                            , 31  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_31D );
+
+REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_EQ                      , 0   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_EQ );
+REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_EQ_LEN                  , 4   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_EQ_LEN );
+REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_UP                  , 4   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_PWR_UP );
+REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_UP_LEN              , 2   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_PWR_UP_LEN );
+REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_DN                  , 6   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_PWR_DN );
+REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_DN_LEN              , 2   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_PWR_DN_LEN );
+REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_UP                   , 8   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_L3_UP );
+REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_UP_LEN               , 4   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_L3_UP_LEN );
+REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_DN                   , 12  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_L3_DN );
+REG64_FLD( EX_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_DN_LEN               , 4   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_L3_DN_LEN );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_16D                            , 16  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_16D );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_17D                            , 17  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_17D );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_18D                            , 18  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_18D );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_19D                            , 19  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_19D );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_20D                            , 20  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_20D );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_21D                            , 21  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_21D );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_22D                            , 22  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_22D );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_23D                            , 23  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_23D );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_24D                            , 24  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_24D );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_25D                            , 25  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_25D );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_26D                            , 26  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_26D );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_27D                            , 27  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_27D );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_28D                            , 28  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_28D );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_29D                            , 29  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_29D );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_30D                            , 30  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_30D );
+REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_31D                            , 31  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_31D );
+
+REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_EQ                       , 0   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_EQ );
+REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_EQ_LEN                   , 4   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_EQ_LEN );
+REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_UP                   , 4   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_PWR_UP );
+REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_UP_LEN               , 2   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_PWR_UP_LEN );
+REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_DN                   , 6   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_PWR_DN );
+REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_DN_LEN               , 2   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_PWR_DN_LEN );
+REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_UP                    , 8   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_L3_UP );
+REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_UP_LEN                , 4   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_L3_UP_LEN );
+REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_DN                    , 12  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_L3_DN );
+REG64_FLD( C_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_DN_LEN                , 4   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TCEP_AMUX_VSELECT_L3_DN_LEN );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_16D                             , 16  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_16D );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_17D                             , 17  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_17D );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_18D                             , 18  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_18D );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_19D                             , 19  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_19D );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_20D                             , 20  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_20D );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_21D                             , 21  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_21D );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_22D                             , 22  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_22D );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_23D                             , 23  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_23D );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_24D                             , 24  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_24D );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_25D                             , 25  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_25D );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_26D                             , 26  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_26D );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_27D                             , 27  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_27D );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_28D                             , 28  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_28D );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_29D                             , 29  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_29D );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_30D                             , 30  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_30D );
+REG64_FLD( C_CPLT_CONF1_FREE_USAGE_31D                             , 31  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_31D );
+
+REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC );
+REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC                 , 1   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC );
+REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC                  , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_FLUSHMODE_INH_DC );
+REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC                    , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_FORCE_ALIGN_DC );
+REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC                   , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_ARY_WRT_THRU_DC );
+REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_AVP_MODE                          , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_AVP_MODE );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_6A                             , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_6A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_7A                             , 7   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_7A );
+REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC            , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_9A                             , 9   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_9A );
+REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC          , 10  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC );
+REG64_FLD( EQ_CPLT_CTRL0_RESERVED_11A                              , 11  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_11A );
+REG64_FLD( EQ_CPLT_CTRL0_TC_SKIT_MODE_BIST_DC                      , 12  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_SKIT_MODE_BIST_DC );
+REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC      , 13  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC );
+REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC             , 14  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC );
+REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC               , 15  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC );
+REG64_FLD( EQ_CPLT_CTRL0_TC_NBTI_HDR_ENABLE_OVR_DC                 , 16  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC );
+REG64_FLD( EQ_CPLT_CTRL0_TC_NBTI_PROBE_GATE_DC                     , 17  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_NBTI_PROBE_GATE_DC );
+REG64_FLD( EQ_CPLT_CTRL0_RESERVED_18A                              , 18  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_18A );
+REG64_FLD( EQ_CPLT_CTRL0_RESERVED_19A                              , 19  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_19A );
+REG64_FLD( EQ_CPLT_CTRL0_TC_PSRO_SEL_DC                            , 20  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PSRO_SEL_DC );
+REG64_FLD( EQ_CPLT_CTRL0_TC_PSRO_SEL_DC_LEN                        , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PSRO_SEL_DC_LEN );
+REG64_FLD( EQ_CPLT_CTRL0_TC_BSC_WRAPSEL_DC                         , 28  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_WRAPSEL_DC );
+REG64_FLD( EQ_CPLT_CTRL0_TC_BSC_INTMODE_DC                         , 29  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_INTMODE_DC );
+REG64_FLD( EQ_CPLT_CTRL0_TC_BSC_INV_DC                             , 30  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_INV_DC );
+REG64_FLD( EQ_CPLT_CTRL0_TC_BSC_EXTMODE_DC                         , 31  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_EXTMODE_DC );
+REG64_FLD( EQ_CPLT_CTRL0_TC_REFCLK_DRVR_EN_DC                      , 32  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REFCLK_DRVR_EN_DC );
+REG64_FLD( EQ_CPLT_CTRL0_RESERVED_33A                              , 33  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_33A );
+REG64_FLD( EQ_CPLT_CTRL0_RESERVED_34A                              , 34  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_34A );
+REG64_FLD( EQ_CPLT_CTRL0_RESERVED_35A                              , 35  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_35A );
+REG64_FLD( EQ_CPLT_CTRL0_TC_OELCC_EDGE_DELAYED_DC                  , 36  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_OELCC_EDGE_DELAYED_DC );
+REG64_FLD( EQ_CPLT_CTRL0_TC_OELCC_ALIGN_FLUSH_DC                   , 37  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_OELCC_ALIGN_FLUSH_DC );
+REG64_FLD( EQ_CPLT_CTRL0_RESERVED_38A                              , 38  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_38A );
+REG64_FLD( EQ_CPLT_CTRL0_RESERVED_39A                              , 39  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_39A );
+REG64_FLD( EQ_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC                   , 40  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_CLKDIV_SEL_DC );
+REG64_FLD( EQ_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN               , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN );
+REG64_FLD( EQ_CPLT_CTRL0_RESERVED_42A                              , 42  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_42A );
+REG64_FLD( EQ_CPLT_CTRL0_RESERVED_43A                              , 43  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_43A );
+REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_DCTEST_DC                         , 44  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_DCTEST_DC );
+REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_OTP_PRGMODE_DC                    , 45  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_OTP_PRGMODE_DC );
+REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_SSS_CALIBRATE_DC                  , 46  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_SSS_CALIBRATE_DC );
+REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC                      , 47  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_PIN_LBIST_DC );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_48A                            , 48  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_48A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_49A                            , 49  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_49A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_50A                            , 50  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_50A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_51A                            , 51  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_51A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_52A                            , 52  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_52A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_53A                            , 53  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_53A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_54A                            , 54  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_54A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_55A                            , 55  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_55A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_56A                            , 56  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_56A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_57A                            , 57  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_57A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_58A                            , 58  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_58A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_59A                            , 59  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_59A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_60A                            , 60  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_60A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_61A                            , 61  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_61A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_62A                            , 62  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_62A );
+REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_63A                            , 63  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_63A );
+
+REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC                 , 0   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC );
+REG64_FLD( EX_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC                 , 1   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC );
+REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC                  , 2   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_FLUSHMODE_INH_DC );
+REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC                    , 3   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_FORCE_ALIGN_DC );
+REG64_FLD( EX_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC                   , 4   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_ARY_WRT_THRU_DC );
+REG64_FLD( EX_CPLT_CTRL0_TC_UNIT_AVP_MODE                          , 5   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_AVP_MODE );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_6A                             , 6   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_6A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_7A                             , 7   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_7A );
+REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC            , 8   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_9A                             , 9   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_9A );
+REG64_FLD( EX_CPLT_CTRL0_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC          , 10  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC );
+REG64_FLD( EX_CPLT_CTRL0_RESERVED_11A                              , 11  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_11A );
+REG64_FLD( EX_CPLT_CTRL0_TC_SKIT_MODE_BIST_DC                      , 12  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_SKIT_MODE_BIST_DC );
+REG64_FLD( EX_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC      , 13  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC );
+REG64_FLD( EX_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC             , 14  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC );
+REG64_FLD( EX_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC               , 15  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC );
+REG64_FLD( EX_CPLT_CTRL0_TC_NBTI_HDR_ENABLE_OVR_DC                 , 16  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC );
+REG64_FLD( EX_CPLT_CTRL0_TC_NBTI_PROBE_GATE_DC                     , 17  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_NBTI_PROBE_GATE_DC );
+REG64_FLD( EX_CPLT_CTRL0_RESERVED_18A                              , 18  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_18A );
+REG64_FLD( EX_CPLT_CTRL0_RESERVED_19A                              , 19  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_19A );
+REG64_FLD( EX_CPLT_CTRL0_TC_PSRO_SEL_DC                            , 20  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PSRO_SEL_DC );
+REG64_FLD( EX_CPLT_CTRL0_TC_PSRO_SEL_DC_LEN                        , 8   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PSRO_SEL_DC_LEN );
+REG64_FLD( EX_CPLT_CTRL0_TC_BSC_WRAPSEL_DC                         , 28  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_WRAPSEL_DC );
+REG64_FLD( EX_CPLT_CTRL0_TC_BSC_INTMODE_DC                         , 29  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_INTMODE_DC );
+REG64_FLD( EX_CPLT_CTRL0_TC_BSC_INV_DC                             , 30  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_INV_DC );
+REG64_FLD( EX_CPLT_CTRL0_TC_BSC_EXTMODE_DC                         , 31  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_EXTMODE_DC );
+REG64_FLD( EX_CPLT_CTRL0_TC_REFCLK_DRVR_EN_DC                      , 32  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REFCLK_DRVR_EN_DC );
+REG64_FLD( EX_CPLT_CTRL0_RESERVED_33A                              , 33  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_33A );
+REG64_FLD( EX_CPLT_CTRL0_RESERVED_34A                              , 34  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_34A );
+REG64_FLD( EX_CPLT_CTRL0_RESERVED_35A                              , 35  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_35A );
+REG64_FLD( EX_CPLT_CTRL0_TC_OELCC_EDGE_DELAYED_DC                  , 36  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_OELCC_EDGE_DELAYED_DC );
+REG64_FLD( EX_CPLT_CTRL0_TC_OELCC_ALIGN_FLUSH_DC                   , 37  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_OELCC_ALIGN_FLUSH_DC );
+REG64_FLD( EX_CPLT_CTRL0_RESERVED_38A                              , 38  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_38A );
+REG64_FLD( EX_CPLT_CTRL0_RESERVED_39A                              , 39  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_39A );
+REG64_FLD( EX_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC                   , 40  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_CLKDIV_SEL_DC );
+REG64_FLD( EX_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN               , 2   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN );
+REG64_FLD( EX_CPLT_CTRL0_RESERVED_42A                              , 42  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_42A );
+REG64_FLD( EX_CPLT_CTRL0_RESERVED_43A                              , 43  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_43A );
+REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_DCTEST_DC                         , 44  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_DCTEST_DC );
+REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_OTP_PRGMODE_DC                    , 45  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_OTP_PRGMODE_DC );
+REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_SSS_CALIBRATE_DC                  , 46  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_SSS_CALIBRATE_DC );
+REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC                      , 47  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_PIN_LBIST_DC );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_48A                            , 48  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_48A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_49A                            , 49  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_49A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_50A                            , 50  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_50A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_51A                            , 51  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_51A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_52A                            , 52  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_52A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_53A                            , 53  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_53A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_54A                            , 54  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_54A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_55A                            , 55  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_55A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_56A                            , 56  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_56A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_57A                            , 57  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_57A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_58A                            , 58  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_58A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_59A                            , 59  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_59A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_60A                            , 60  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_60A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_61A                            , 61  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_61A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_62A                            , 62  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_62A );
+REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_63A                            , 63  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_63A );
+
+REG64_FLD( C_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC                  , 0   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC );
+REG64_FLD( C_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC                  , 1   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC );
+REG64_FLD( C_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC                   , 2   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_FLUSHMODE_INH_DC );
+REG64_FLD( C_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC                     , 3   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_FORCE_ALIGN_DC );
+REG64_FLD( C_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC                    , 4   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_ARY_WRT_THRU_DC );
+REG64_FLD( C_CPLT_CTRL0_TC_UNIT_AVP_MODE                           , 5   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_AVP_MODE );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_6A                              , 6   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_6A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_7A                              , 7   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_7A );
+REG64_FLD( C_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC             , 8   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_9A                              , 9   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_9A );
+REG64_FLD( C_CPLT_CTRL0_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC           , 10  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC );
+REG64_FLD( C_CPLT_CTRL0_RESERVED_11A                               , 11  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_11A );
+REG64_FLD( C_CPLT_CTRL0_TC_SKIT_MODE_BIST_DC                       , 12  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_SKIT_MODE_BIST_DC );
+REG64_FLD( C_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC       , 13  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC );
+REG64_FLD( C_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC              , 14  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC );
+REG64_FLD( C_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC                , 15  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC );
+REG64_FLD( C_CPLT_CTRL0_TC_NBTI_HDR_ENABLE_OVR_DC                  , 16  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC );
+REG64_FLD( C_CPLT_CTRL0_TC_NBTI_PROBE_GATE_DC                      , 17  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_NBTI_PROBE_GATE_DC );
+REG64_FLD( C_CPLT_CTRL0_RESERVED_18A                               , 18  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_18A );
+REG64_FLD( C_CPLT_CTRL0_RESERVED_19A                               , 19  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_19A );
+REG64_FLD( C_CPLT_CTRL0_TC_PSRO_SEL_DC                             , 20  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PSRO_SEL_DC );
+REG64_FLD( C_CPLT_CTRL0_TC_PSRO_SEL_DC_LEN                         , 8   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PSRO_SEL_DC_LEN );
+REG64_FLD( C_CPLT_CTRL0_TC_BSC_WRAPSEL_DC                          , 28  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_WRAPSEL_DC );
+REG64_FLD( C_CPLT_CTRL0_TC_BSC_INTMODE_DC                          , 29  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_INTMODE_DC );
+REG64_FLD( C_CPLT_CTRL0_TC_BSC_INV_DC                              , 30  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_INV_DC );
+REG64_FLD( C_CPLT_CTRL0_TC_BSC_EXTMODE_DC                          , 31  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_BSC_EXTMODE_DC );
+REG64_FLD( C_CPLT_CTRL0_TC_REFCLK_DRVR_EN_DC                       , 32  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REFCLK_DRVR_EN_DC );
+REG64_FLD( C_CPLT_CTRL0_RESERVED_33A                               , 33  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_33A );
+REG64_FLD( C_CPLT_CTRL0_RESERVED_34A                               , 34  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_34A );
+REG64_FLD( C_CPLT_CTRL0_RESERVED_35A                               , 35  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_35A );
+REG64_FLD( C_CPLT_CTRL0_TC_OELCC_EDGE_DELAYED_DC                   , 36  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_OELCC_EDGE_DELAYED_DC );
+REG64_FLD( C_CPLT_CTRL0_TC_OELCC_ALIGN_FLUSH_DC                    , 37  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_OELCC_ALIGN_FLUSH_DC );
+REG64_FLD( C_CPLT_CTRL0_RESERVED_38A                               , 38  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_38A );
+REG64_FLD( C_CPLT_CTRL0_RESERVED_39A                               , 39  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_39A );
+REG64_FLD( C_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC                    , 40  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_CLKDIV_SEL_DC );
+REG64_FLD( C_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN                , 2   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN );
+REG64_FLD( C_CPLT_CTRL0_RESERVED_42A                               , 42  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_42A );
+REG64_FLD( C_CPLT_CTRL0_RESERVED_43A                               , 43  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED_43A );
+REG64_FLD( C_CPLT_CTRL0_CTRL_CC_DCTEST_DC                          , 44  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_DCTEST_DC );
+REG64_FLD( C_CPLT_CTRL0_CTRL_CC_OTP_PRGMODE_DC                     , 45  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_OTP_PRGMODE_DC );
+REG64_FLD( C_CPLT_CTRL0_CTRL_CC_SSS_CALIBRATE_DC                   , 46  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_SSS_CALIBRATE_DC );
+REG64_FLD( C_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC                       , 47  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_CTRL_CC_PIN_LBIST_DC );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_48A                             , 48  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_48A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_49A                             , 49  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_49A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_50A                             , 50  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_50A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_51A                             , 51  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_51A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_52A                             , 52  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_52A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_53A                             , 53  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_53A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_54A                             , 54  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_54A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_55A                             , 55  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_55A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_56A                             , 56  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_56A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_57A                             , 57  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_57A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_58A                             , 58  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_58A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_59A                             , 59  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_59A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_60A                             , 60  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_60A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_61A                             , 61  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_61A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_62A                             , 62  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_62A );
+REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_63A                             , 63  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FREE_USAGE_63A );
+
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_0B                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_0B  );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_1B                                 , 1   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_1B  );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_2B                                 , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_2B  );
+REG64_FLD( EQ_CPLT_CTRL1_TC_VITL_REGION_FENCE                      , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_VITL_REGION_FENCE );
+REG64_FLD( EQ_CPLT_CTRL1_TC_PERV_REGION_FENCE                      , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PERV_REGION_FENCE );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_5B                                 , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_5B  );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_6B                                 , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_6B  );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_7B                                 , 7   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_7B  );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_8B                                 , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_8B  );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_9B                                 , 9   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_9B  );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_10B                                , 10  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_10B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_11B                                , 11  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_11B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_12B                                , 12  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_12B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_13B                                , 13  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_13B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_14B                                , 14  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_14B );
+REG64_FLD( EQ_CPLT_CTRL1_RESERVED                                  , 15  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED   );
+REG64_FLD( EQ_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE             , 16  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_17B                                , 17  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_17B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_18B                                , 18  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_18B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_19B                                , 19  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_19B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_20B                                , 20  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_20B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_21B                                , 21  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_21B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_22B                                , 22  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_22B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_23B                                , 23  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_23B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_24B                                , 24  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_24B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_25B                                , 25  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_25B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_26B                                , 26  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_26B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_27B                                , 27  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_27B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_28B                                , 28  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_28B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_29B                                , 29  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_29B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_30B                                , 30  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_30B );
+REG64_FLD( EQ_CPLT_CTRL1_UNUSED_31B                                , 31  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_31B );
+
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_0B                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_0B  );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_1B                                 , 1   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_1B  );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_2B                                 , 2   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_2B  );
+REG64_FLD( EX_CPLT_CTRL1_TC_VITL_REGION_FENCE                      , 3   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_VITL_REGION_FENCE );
+REG64_FLD( EX_CPLT_CTRL1_TC_PERV_REGION_FENCE                      , 4   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PERV_REGION_FENCE );
+REG64_FLD( EX_CPLT_CTRL1_TC_REGION1_FENCE                          , 5   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION1_FENCE );
+REG64_FLD( EX_CPLT_CTRL1_TC_REGION2_FENCE                          , 6   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION2_FENCE );
+REG64_FLD( EX_CPLT_CTRL1_TC_REGION3_FENCE                          , 7   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION3_FENCE );
+REG64_FLD( EX_CPLT_CTRL1_TC_REGION4_FENCE                          , 8   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION4_FENCE );
+REG64_FLD( EX_CPLT_CTRL1_TC_REGION5_FENCE                          , 9   , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION5_FENCE );
+REG64_FLD( EX_CPLT_CTRL1_TC_REGION6_FENCE                          , 10  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION6_FENCE );
+REG64_FLD( EX_CPLT_CTRL1_TC_REGION7_FENCE                          , 11  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION7_FENCE );
+REG64_FLD( EX_CPLT_CTRL1_TC_REGION8_FENCE                          , 12  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION8_FENCE );
+REG64_FLD( EX_CPLT_CTRL1_TC_REGION9_FENCE                          , 13  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION9_FENCE );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_14B                                , 14  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_14B );
+REG64_FLD( EX_CPLT_CTRL1_RESERVED                                  , 15  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED   );
+REG64_FLD( EX_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE             , 16  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_17B                                , 17  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_17B );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_18B                                , 18  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_18B );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_19B                                , 19  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_19B );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_20B                                , 20  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_20B );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_21B                                , 21  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_21B );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_22B                                , 22  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_22B );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_23B                                , 23  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_23B );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_24B                                , 24  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_24B );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_25B                                , 25  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_25B );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_26B                                , 26  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_26B );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_27B                                , 27  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_27B );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_28B                                , 28  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_28B );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_29B                                , 29  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_29B );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_30B                                , 30  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_30B );
+REG64_FLD( EX_CPLT_CTRL1_UNUSED_31B                                , 31  , SH_UNT_EX       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_31B );
+
+REG64_FLD( C_CPLT_CTRL1_UNUSED_0B                                  , 0   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_0B  );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_1B                                  , 1   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_1B  );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_2B                                  , 2   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_2B  );
+REG64_FLD( C_CPLT_CTRL1_TC_VITL_REGION_FENCE                       , 3   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_VITL_REGION_FENCE );
+REG64_FLD( C_CPLT_CTRL1_TC_PERV_REGION_FENCE                       , 4   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_PERV_REGION_FENCE );
+REG64_FLD( C_CPLT_CTRL1_TC_REGION1_FENCE                           , 5   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION1_FENCE );
+REG64_FLD( C_CPLT_CTRL1_TC_REGION2_FENCE                           , 6   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION2_FENCE );
+REG64_FLD( C_CPLT_CTRL1_TC_REGION3_FENCE                           , 7   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION3_FENCE );
+REG64_FLD( C_CPLT_CTRL1_TC_REGION4_FENCE                           , 8   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION4_FENCE );
+REG64_FLD( C_CPLT_CTRL1_TC_REGION5_FENCE                           , 9   , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION5_FENCE );
+REG64_FLD( C_CPLT_CTRL1_TC_REGION6_FENCE                           , 10  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION6_FENCE );
+REG64_FLD( C_CPLT_CTRL1_TC_REGION7_FENCE                           , 11  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION7_FENCE );
+REG64_FLD( C_CPLT_CTRL1_TC_REGION8_FENCE                           , 12  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION8_FENCE );
+REG64_FLD( C_CPLT_CTRL1_TC_REGION9_FENCE                           , 13  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION9_FENCE );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_14B                                 , 14  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_14B );
+REG64_FLD( C_CPLT_CTRL1_RESERVED                                   , 15  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_RESERVED   );
+REG64_FLD( C_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE              , 16  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_17B                                 , 17  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_17B );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_18B                                 , 18  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_18B );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_19B                                 , 19  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_19B );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_20B                                 , 20  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_20B );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_21B                                 , 21  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_21B );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_22B                                 , 22  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_22B );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_23B                                 , 23  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_23B );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_24B                                 , 24  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_24B );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_25B                                 , 25  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_25B );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_26B                                 , 26  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_26B );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_27B                                 , 27  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_27B );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_28B                                 , 28  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_28B );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_29B                                 , 29  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_29B );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_30B                                 , 30  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_30B );
+REG64_FLD( C_CPLT_CTRL1_UNUSED_31B                                 , 31  , SH_UNT_C        , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_UNUSED_31B );
+
+REG64_FLD( EQ_CPLT_MASK0_CPLTMASK0                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CPLTMASK0  );
+REG64_FLD( EQ_CPLT_MASK0_CPLTMASK0_LEN                             , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CPLTMASK0_LEN );
+
+REG64_FLD( EX_CPLT_MASK0_CPLTMASK0                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CPLTMASK0  );
+REG64_FLD( EX_CPLT_MASK0_CPLTMASK0_LEN                             , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CPLTMASK0_LEN );
+
+REG64_FLD( C_CPLT_MASK0_CPLTMASK0                                  , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CPLTMASK0  );
+REG64_FLD( C_CPLT_MASK0_CPLTMASK0_LEN                              , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CPLTMASK0_LEN );
+
+REG64_FLD( EQ_CPLT_STAT0_SRAM_ABIST_DONE_DC                        , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SRAM_ABIST_DONE_DC );
+REG64_FLD( EQ_CPLT_STAT0_DRAM_ABIST_DONE_DC                        , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DRAM_ABIST_DONE_DC );
+REG64_FLD( EQ_CPLT_STAT0_RESERVED_2E                               , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_2E );
+REG64_FLD( EQ_CPLT_STAT0_RESERVED_3E                               , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_3E );
+REG64_FLD( EQ_CPLT_STAT0_TC_DIAG_PORT0_OUT                         , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TC_DIAG_PORT0_OUT );
+REG64_FLD( EQ_CPLT_STAT0_TC_DIAG_PORT1_OUT                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TC_DIAG_PORT1_OUT );
+REG64_FLD( EQ_CPLT_STAT0_RESERVED_6E                               , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_6E );
+REG64_FLD( EQ_CPLT_STAT0_PLL_DESTOUT                               , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PLL_DESTOUT );
+REG64_FLD( EQ_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC                      , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CC_CTRL_OPCG_DONE_DC );
+REG64_FLD( EQ_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC             , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC );
+REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_10E                            , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_10E );
+REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_11E                            , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_11E );
+REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_12E                            , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_12E );
+REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_13E                            , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_13E );
+REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_14E                            , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_14E );
+REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_15E                            , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_15E );
+REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_16E                            , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_16E );
+REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_17E                            , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_17E );
+REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_18E                            , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_18E );
+REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_19E                            , 19  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_19E );
+REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_20E                            , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_20E );
+REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_21E                            , 21  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_21E );
+REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_22E                            , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_22E );
+REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_23E                            , 23  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_23E );
+
+REG64_FLD( EX_CPLT_STAT0_SRAM_ABIST_DONE_DC                        , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SRAM_ABIST_DONE_DC );
+REG64_FLD( EX_CPLT_STAT0_DRAM_ABIST_DONE_DC                        , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DRAM_ABIST_DONE_DC );
+REG64_FLD( EX_CPLT_STAT0_RESERVED_2E                               , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_2E );
+REG64_FLD( EX_CPLT_STAT0_RESERVED_3E                               , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_3E );
+REG64_FLD( EX_CPLT_STAT0_TC_DIAG_PORT0_OUT                         , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TC_DIAG_PORT0_OUT );
+REG64_FLD( EX_CPLT_STAT0_TC_DIAG_PORT1_OUT                         , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TC_DIAG_PORT1_OUT );
+REG64_FLD( EX_CPLT_STAT0_RESERVED_6E                               , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_6E );
+REG64_FLD( EX_CPLT_STAT0_PLL_DESTOUT                               , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PLL_DESTOUT );
+REG64_FLD( EX_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC                      , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CC_CTRL_OPCG_DONE_DC );
+REG64_FLD( EX_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC             , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC );
+REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_10E                            , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_10E );
+REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_11E                            , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_11E );
+REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_12E                            , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_12E );
+REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_13E                            , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_13E );
+REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_14E                            , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_14E );
+REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_15E                            , 15  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_15E );
+REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_16E                            , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_16E );
+REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_17E                            , 17  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_17E );
+REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_18E                            , 18  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_18E );
+REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_19E                            , 19  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_19E );
+REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_20E                            , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_20E );
+REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_21E                            , 21  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_21E );
+REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_22E                            , 22  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_22E );
+REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_23E                            , 23  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_23E );
+
+REG64_FLD( C_CPLT_STAT0_SRAM_ABIST_DONE_DC                         , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SRAM_ABIST_DONE_DC );
+REG64_FLD( C_CPLT_STAT0_DRAM_ABIST_DONE_DC                         , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DRAM_ABIST_DONE_DC );
+REG64_FLD( C_CPLT_STAT0_RESERVED_2E                                , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_2E );
+REG64_FLD( C_CPLT_STAT0_RESERVED_3E                                , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_3E );
+REG64_FLD( C_CPLT_STAT0_TC_DIAG_PORT0_OUT                          , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TC_DIAG_PORT0_OUT );
+REG64_FLD( C_CPLT_STAT0_TC_DIAG_PORT1_OUT                          , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TC_DIAG_PORT1_OUT );
+REG64_FLD( C_CPLT_STAT0_RESERVED_6E                                , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_6E );
+REG64_FLD( C_CPLT_STAT0_PLL_DESTOUT                                , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PLL_DESTOUT );
+REG64_FLD( C_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC                       , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CC_CTRL_OPCG_DONE_DC );
+REG64_FLD( C_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC              , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC );
+REG64_FLD( C_CPLT_STAT0_FREE_USAGE_10E                             , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_10E );
+REG64_FLD( C_CPLT_STAT0_FREE_USAGE_11E                             , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_11E );
+REG64_FLD( C_CPLT_STAT0_FREE_USAGE_12E                             , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_12E );
+REG64_FLD( C_CPLT_STAT0_FREE_USAGE_13E                             , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_13E );
+REG64_FLD( C_CPLT_STAT0_FREE_USAGE_14E                             , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_14E );
+REG64_FLD( C_CPLT_STAT0_FREE_USAGE_15E                             , 15  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_15E );
+REG64_FLD( C_CPLT_STAT0_FREE_USAGE_16E                             , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_16E );
+REG64_FLD( C_CPLT_STAT0_FREE_USAGE_17E                             , 17  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_17E );
+REG64_FLD( C_CPLT_STAT0_FREE_USAGE_18E                             , 18  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_18E );
+REG64_FLD( C_CPLT_STAT0_FREE_USAGE_19E                             , 19  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_19E );
+REG64_FLD( C_CPLT_STAT0_FREE_USAGE_20E                             , 20  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_20E );
+REG64_FLD( C_CPLT_STAT0_FREE_USAGE_21E                             , 21  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_21E );
+REG64_FLD( C_CPLT_STAT0_FREE_USAGE_22E                             , 22  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_22E );
+REG64_FLD( C_CPLT_STAT0_FREE_USAGE_23E                             , 23  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FREE_USAGE_23E );
+
+REG64_FLD( EX_CPPM_CACCR_CLK_SB_STRENGTH                           , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SB_STRENGTH );
+REG64_FLD( EX_CPPM_CACCR_CLK_SB_STRENGTH_LEN                       , 4   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SB_STRENGTH_LEN );
+REG64_FLD( EX_CPPM_CACCR_CLK_SB_SPARE                              , 4   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SB_SPARE );
+REG64_FLD( EX_CPPM_CACCR_CLK_SB_PULSE_MODE_EN                      , 5   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SB_PULSE_MODE_EN );
+REG64_FLD( EX_CPPM_CACCR_CLK_SB_PULSE_MODE                         , 6   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SB_PULSE_MODE );
+REG64_FLD( EX_CPPM_CACCR_CLK_SB_PULSE_MODE_LEN                     , 2   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SB_PULSE_MODE_LEN );
+REG64_FLD( EX_CPPM_CACCR_CLK_SW_RESCLK                             , 8   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SW_RESCLK );
+REG64_FLD( EX_CPPM_CACCR_CLK_SW_RESCLK_LEN                         , 4   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SW_RESCLK_LEN );
+REG64_FLD( EX_CPPM_CACCR_CLK_SW_SPARE                              , 12  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SW_SPARE );
+REG64_FLD( EX_CPPM_CACCR_QUAD_CLK_SB_OVERRIDE                      , 13  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_QUAD_CLK_SB_OVERRIDE );
+REG64_FLD( EX_CPPM_CACCR_QUAD_CLK_SW_OVERRIDE                      , 14  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_QUAD_CLK_SW_OVERRIDE );
+REG64_FLD( EX_CPPM_CACCR_CLK_SYNC_ENABLE                           , 15  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SYNC_ENABLE );
+
+REG64_FLD( C_CPPM_CACCR_CLK_SB_STRENGTH                            , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SB_STRENGTH );
+REG64_FLD( C_CPPM_CACCR_CLK_SB_STRENGTH_LEN                        , 4   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SB_STRENGTH_LEN );
+REG64_FLD( C_CPPM_CACCR_CLK_SB_SPARE                               , 4   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SB_SPARE );
+REG64_FLD( C_CPPM_CACCR_CLK_SB_PULSE_MODE_EN                       , 5   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SB_PULSE_MODE_EN );
+REG64_FLD( C_CPPM_CACCR_CLK_SB_PULSE_MODE                          , 6   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SB_PULSE_MODE );
+REG64_FLD( C_CPPM_CACCR_CLK_SB_PULSE_MODE_LEN                      , 2   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SB_PULSE_MODE_LEN );
+REG64_FLD( C_CPPM_CACCR_CLK_SW_RESCLK                              , 8   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SW_RESCLK );
+REG64_FLD( C_CPPM_CACCR_CLK_SW_RESCLK_LEN                          , 4   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SW_RESCLK_LEN );
+REG64_FLD( C_CPPM_CACCR_CLK_SW_SPARE                               , 12  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SW_SPARE );
+REG64_FLD( C_CPPM_CACCR_QUAD_CLK_SB_OVERRIDE                       , 13  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_QUAD_CLK_SB_OVERRIDE );
+REG64_FLD( C_CPPM_CACCR_QUAD_CLK_SW_OVERRIDE                       , 14  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_QUAD_CLK_SW_OVERRIDE );
+REG64_FLD( C_CPPM_CACCR_CLK_SYNC_ENABLE                            , 15  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CLK_SYNC_ENABLE );
+
+REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SB_STRENGTH                    , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SB_STRENGTH );
+REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SB_STRENGTH_LEN                , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SB_STRENGTH_LEN );
+REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SB_SPARE                       , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SB_SPARE );
+REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE_EN               , 5   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_EN );
+REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE                  , 6   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SB_PULSE_MODE );
+REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE_LEN              , 2   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_LEN );
+REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SW_RESCLK                      , 8   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SW_RESCLK );
+REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SW_RESCLK_LEN                  , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SW_RESCLK_LEN );
+REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SW_SPARE                       , 12  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SW_SPARE );
+REG64_FLD( EX_CPPM_CACSR_CLK_SYNC_DONE                             , 13  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CLK_SYNC_DONE );
+
+REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SB_STRENGTH                     , 0   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SB_STRENGTH );
+REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SB_STRENGTH_LEN                 , 4   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SB_STRENGTH_LEN );
+REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SB_SPARE                        , 4   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SB_SPARE );
+REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE_EN                , 5   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_EN );
+REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE                   , 6   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SB_PULSE_MODE );
+REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE_LEN               , 2   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_LEN );
+REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SW_RESCLK                       , 8   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SW_RESCLK );
+REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SW_RESCLK_LEN                   , 4   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SW_RESCLK_LEN );
+REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SW_SPARE                        , 12  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_CLK_SW_SPARE );
+REG64_FLD( C_CPPM_CACSR_CLK_SYNC_DONE                              , 13  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_CLK_SYNC_DONE );
+
+REG64_FLD( EX_CPPM_CIVRMLCR_IVRM_LOCAL_CONTROL                     , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_LOCAL_CONTROL );
+REG64_FLD( EX_CPPM_CIVRMLCR_RESERVED_1_2                           , 1   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_2 );
+REG64_FLD( EX_CPPM_CIVRMLCR_RESERVED_1_2_LEN                       , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_2_LEN );
+REG64_FLD( EX_CPPM_CIVRMLCR_IVRM_UREG_TEST_EN                      , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_UREG_TEST_EN );
+REG64_FLD( EX_CPPM_CIVRMLCR_IVRM_UREG_TEST_ID                      , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_UREG_TEST_ID );
+REG64_FLD( EX_CPPM_CIVRMLCR_IVRM_UREG_TEST_ID_LEN                  , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_UREG_TEST_ID_LEN );
+
+REG64_FLD( C_CPPM_CIVRMLCR_IVRM_LOCAL_CONTROL                      , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_LOCAL_CONTROL );
+REG64_FLD( C_CPPM_CIVRMLCR_RESERVED_1_2                            , 1   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_2 );
+REG64_FLD( C_CPPM_CIVRMLCR_RESERVED_1_2_LEN                        , 2   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_2_LEN );
+REG64_FLD( C_CPPM_CIVRMLCR_IVRM_UREG_TEST_EN                       , 3   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_UREG_TEST_EN );
+REG64_FLD( C_CPPM_CIVRMLCR_IVRM_UREG_TEST_ID                       , 4   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_UREG_TEST_ID );
+REG64_FLD( C_CPPM_CIVRMLCR_IVRM_UREG_TEST_ID_LEN                   , 4   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_UREG_TEST_ID_LEN );
+
+REG64_FLD( EX_CPPM_CMEDATA_DATA                                    , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA       );
+REG64_FLD( EX_CPPM_CMEDATA_DATA_LEN                                , 32  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( C_CPPM_CMEDATA_DATA                                     , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA       );
+REG64_FLD( C_CPPM_CMEDATA_DATA_LEN                                 , 32  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EX_CPPM_CMEDB0_CME_MESSAGE_NUMBER0                      , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER0 );
+REG64_FLD( EX_CPPM_CMEDB0_CME_MESSAGE_NUMBER0_LEN                  , 8   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER0_LEN );
+REG64_FLD( EX_CPPM_CMEDB0_CME_MESSAGE_HI                           , 8   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_HI );
+REG64_FLD( EX_CPPM_CMEDB0_CME_MESSAGE_HI_LEN                       , 56  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_HI_LEN );
+
+REG64_FLD( C_CPPM_CMEDB0_CME_MESSAGE_NUMBER0                       , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER0 );
+REG64_FLD( C_CPPM_CMEDB0_CME_MESSAGE_NUMBER0_LEN                   , 8   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER0_LEN );
+REG64_FLD( C_CPPM_CMEDB0_CME_MESSAGE_HI                            , 8   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_HI );
+REG64_FLD( C_CPPM_CMEDB0_CME_MESSAGE_HI_LEN                        , 56  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_HI_LEN );
+
+REG64_FLD( EX_CPPM_CMEDB1_CME_MESSAGE_NUMBER_N                     , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER_N );
+REG64_FLD( EX_CPPM_CMEDB1_CME_MESSAGE_NUMBER_N_LEN                 , 8   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER_N_LEN );
+
+REG64_FLD( C_CPPM_CMEDB1_CME_MESSAGE_NUMBER_N                      , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER_N );
+REG64_FLD( C_CPPM_CMEDB1_CME_MESSAGE_NUMBER_N_LEN                  , 8   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER_N_LEN );
+
+REG64_FLD( EX_CPPM_CMEDB2_CME_MESSAGE_NUMBER_N                     , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER_N );
+REG64_FLD( EX_CPPM_CMEDB2_CME_MESSAGE_NUMBER_N_LEN                 , 8   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER_N_LEN );
+
+REG64_FLD( C_CPPM_CMEDB2_CME_MESSAGE_NUMBER_N                      , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER_N );
+REG64_FLD( C_CPPM_CMEDB2_CME_MESSAGE_NUMBER_N_LEN                  , 8   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER_N_LEN );
+
+REG64_FLD( EX_CPPM_CMEDB3_CME_MESSAGE_NUMBER_N                     , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER_N );
+REG64_FLD( EX_CPPM_CMEDB3_CME_MESSAGE_NUMBER_N_LEN                 , 8   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER_N_LEN );
+REG64_FLD( EX_CPPM_CMEDB3_CME_MESSAGE_HI                           , 8   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_HI );
+REG64_FLD( EX_CPPM_CMEDB3_CME_MESSAGE_HI_LEN                       , 56  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_HI_LEN );
+
+REG64_FLD( C_CPPM_CMEDB3_CME_MESSAGE_NUMBER_N                      , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER_N );
+REG64_FLD( C_CPPM_CMEDB3_CME_MESSAGE_NUMBER_N_LEN                  , 8   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_NUMBER_N_LEN );
+REG64_FLD( C_CPPM_CMEDB3_CME_MESSAGE_HI                            , 8   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_HI );
+REG64_FLD( C_CPPM_CMEDB3_CME_MESSAGE_HI_LEN                        , 56  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_MESSAGE_HI_LEN );
+
+REG64_FLD( EX_CPPM_CMEMSG_CME_MESSAGE                              , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_CME_MESSAGE );
+REG64_FLD( EX_CPPM_CMEMSG_CME_MESSAGE_LEN                          , 64  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_CME_MESSAGE_LEN );
+
+REG64_FLD( C_CPPM_CMEMSG_CME_MESSAGE                               , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_CME_MESSAGE );
+REG64_FLD( C_CPPM_CMEMSG_CME_MESSAGE_LEN                           , 64  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_CME_MESSAGE_LEN );
+
+REG64_FLD( EX_CPPM_CPMMR_PPM_WRITE_DISABLE                         , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPM_WRITE_DISABLE );
+REG64_FLD( EX_CPPM_CPMMR_PPM_WRITE_OVERRIDE                        , 1   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPM_WRITE_OVERRIDE );
+REG64_FLD( EX_CPPM_CPMMR_RESERVED_2_9                              , 2   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_2_9 );
+REG64_FLD( EX_CPPM_CPMMR_RESERVED_2_9_LEN                          , 7   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_2_9_LEN );
+REG64_FLD( EX_CPPM_CPMMR_FUSED_CORE_MODE                           , 9   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FUSED_CORE_MODE );
+REG64_FLD( EX_CPPM_CPMMR_STOP_EXIT_TYPE_SEL                        , 10  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_STOP_EXIT_TYPE_SEL );
+REG64_FLD( EX_CPPM_CPMMR_BLOCK_INTR_INPUTS                         , 11  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_BLOCK_INTR_INPUTS );
+REG64_FLD( EX_CPPM_CPMMR_CME_ERR_NOTIFY_DIS                        , 12  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_ERR_NOTIFY_DIS );
+REG64_FLD( EX_CPPM_CPMMR_WKUP_NOTIFY_SELECT                        , 13  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_WKUP_NOTIFY_SELECT );
+REG64_FLD( EX_CPPM_CPMMR_ENABLE_PECE                               , 14  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ENABLE_PECE );
+REG64_FLD( EX_CPPM_CPMMR_CME_SPECIAL_WKUP_DONE_DIS                 , 15  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_SPECIAL_WKUP_DONE_DIS );
+
+REG64_FLD( C_CPPM_CPMMR_PPM_WRITE_DISABLE                          , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPM_WRITE_DISABLE );
+REG64_FLD( C_CPPM_CPMMR_PPM_WRITE_OVERRIDE                         , 1   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPM_WRITE_OVERRIDE );
+REG64_FLD( C_CPPM_CPMMR_RESERVED_2_9                               , 2   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_2_9 );
+REG64_FLD( C_CPPM_CPMMR_RESERVED_2_9_LEN                           , 7   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_2_9_LEN );
+REG64_FLD( C_CPPM_CPMMR_FUSED_CORE_MODE                            , 9   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_FUSED_CORE_MODE );
+REG64_FLD( C_CPPM_CPMMR_STOP_EXIT_TYPE_SEL                         , 10  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_STOP_EXIT_TYPE_SEL );
+REG64_FLD( C_CPPM_CPMMR_BLOCK_INTR_INPUTS                          , 11  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_BLOCK_INTR_INPUTS );
+REG64_FLD( C_CPPM_CPMMR_CME_ERR_NOTIFY_DIS                         , 12  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_ERR_NOTIFY_DIS );
+REG64_FLD( C_CPPM_CPMMR_WKUP_NOTIFY_SELECT                         , 13  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_WKUP_NOTIFY_SELECT );
+REG64_FLD( C_CPPM_CPMMR_ENABLE_PECE                                , 14  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_ENABLE_PECE );
+REG64_FLD( C_CPPM_CPMMR_CME_SPECIAL_WKUP_DONE_DIS                  , 15  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_SPECIAL_WKUP_DONE_DIS );
+
+REG64_FLD( EX_CPPM_CSAR_SCRATCH_ATOMIC_DATA                        , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCRATCH_ATOMIC_DATA );
+REG64_FLD( EX_CPPM_CSAR_SCRATCH_ATOMIC_DATA_LEN                    , 32  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCRATCH_ATOMIC_DATA_LEN );
+
+REG64_FLD( C_CPPM_CSAR_SCRATCH_ATOMIC_DATA                         , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCRATCH_ATOMIC_DATA );
+REG64_FLD( C_CPPM_CSAR_SCRATCH_ATOMIC_DATA_LEN                     , 32  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCRATCH_ATOMIC_DATA_LEN );
+
+REG64_FLD( EX_CPPM_ERR_PCB_INTERRUPT_PROTOCOL                      , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_INTERRUPT_PROTOCOL );
+REG64_FLD( EX_CPPM_ERR_SPECIAL_WKUP_PROTOCOL                       , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SPECIAL_WKUP_PROTOCOL );
+REG64_FLD( EX_CPPM_ERR_PFET_SEQ_PROGRAM                            , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PFET_SEQ_PROGRAM );
+REG64_FLD( EX_CPPM_ERR_CLK_SYNC                                    , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLK_SYNC   );
+REG64_FLD( EX_CPPM_ERR_PECE_INTR_DISABLED                          , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PECE_INTR_DISABLED );
+REG64_FLD( EX_CPPM_ERR_DECONFIGURED_INTR                           , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DECONFIGURED_INTR );
+REG64_FLD( EX_CPPM_ERR_RESERVED_6_7                                , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_6_7 );
+REG64_FLD( EX_CPPM_ERR_RESERVED_6_7_LEN                            , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_6_7_LEN );
+
+REG64_FLD( C_CPPM_ERR_PCB_INTERRUPT_PROTOCOL                       , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PCB_INTERRUPT_PROTOCOL );
+REG64_FLD( C_CPPM_ERR_SPECIAL_WKUP_PROTOCOL                        , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SPECIAL_WKUP_PROTOCOL );
+REG64_FLD( C_CPPM_ERR_PFET_SEQ_PROGRAM                             , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PFET_SEQ_PROGRAM );
+REG64_FLD( C_CPPM_ERR_CLK_SYNC                                     , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLK_SYNC   );
+REG64_FLD( C_CPPM_ERR_PECE_INTR_DISABLED                           , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PECE_INTR_DISABLED );
+REG64_FLD( C_CPPM_ERR_DECONFIGURED_INTR                            , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DECONFIGURED_INTR );
+REG64_FLD( C_CPPM_ERR_RESERVED_6_7                                 , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_6_7 );
+REG64_FLD( C_CPPM_ERR_RESERVED_6_7_LEN                             , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_6_7_LEN );
+
+REG64_FLD( EX_CPPM_ERRMSK_RESERVED_0_7                             , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_7 );
+REG64_FLD( EX_CPPM_ERRMSK_RESERVED_0_7_LEN                         , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_7_LEN );
+
+REG64_FLD( C_CPPM_ERRMSK_RESERVED_0_7                              , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_7 );
+REG64_FLD( C_CPPM_ERRMSK_RESERVED_0_7_LEN                          , 8   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_7_LEN );
+
+REG64_FLD( EX_CPPM_IPPMCMD_QPPM_REG                                , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_QPPM_REG   );
+REG64_FLD( EX_CPPM_IPPMCMD_QPPM_REG_LEN                            , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_QPPM_REG_LEN );
+REG64_FLD( EX_CPPM_IPPMCMD_QPPM_RNW                                , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_QPPM_RNW   );
+REG64_FLD( EX_CPPM_IPPMCMD_RESERVED_9                              , 9   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_9 );
+
+REG64_FLD( C_CPPM_IPPMCMD_QPPM_REG                                 , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_QPPM_REG   );
+REG64_FLD( C_CPPM_IPPMCMD_QPPM_REG_LEN                             , 8   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_QPPM_REG_LEN );
+REG64_FLD( C_CPPM_IPPMCMD_QPPM_RNW                                 , 8   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_QPPM_RNW   );
+REG64_FLD( C_CPPM_IPPMCMD_RESERVED_9                               , 9   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_9 );
+
+REG64_FLD( EX_CPPM_IPPMRDATA_QPPM_RDATA                            , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_QPPM_RDATA );
+REG64_FLD( EX_CPPM_IPPMRDATA_QPPM_RDATA_LEN                        , 64  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_QPPM_RDATA_LEN );
+
+REG64_FLD( C_CPPM_IPPMRDATA_QPPM_RDATA                             , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_QPPM_RDATA );
+REG64_FLD( C_CPPM_IPPMRDATA_QPPM_RDATA_LEN                         , 64  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_QPPM_RDATA_LEN );
+
+REG64_FLD( EX_CPPM_IPPMSTAT_QPPM_ONGOING                           , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_QPPM_ONGOING );
+REG64_FLD( EX_CPPM_IPPMSTAT_QPPM_STATUS                            , 1   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_QPPM_STATUS );
+REG64_FLD( EX_CPPM_IPPMSTAT_QPPM_STATUS_LEN                        , 2   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_QPPM_STATUS_LEN );
+
+REG64_FLD( C_CPPM_IPPMSTAT_QPPM_ONGOING                            , 0   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_QPPM_ONGOING );
+REG64_FLD( C_CPPM_IPPMSTAT_QPPM_STATUS                             , 1   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_QPPM_STATUS );
+REG64_FLD( C_CPPM_IPPMSTAT_QPPM_STATUS_LEN                         , 2   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_QPPM_STATUS_LEN );
+
+REG64_FLD( EX_CPPM_IPPMWDATA_QPPM_WDATA                            , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_QPPM_WDATA );
+REG64_FLD( EX_CPPM_IPPMWDATA_QPPM_WDATA_LEN                        , 64  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_QPPM_WDATA_LEN );
+
+REG64_FLD( C_CPPM_IPPMWDATA_QPPM_WDATA                             , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_QPPM_WDATA );
+REG64_FLD( C_CPPM_IPPMWDATA_QPPM_WDATA_LEN                         , 64  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_QPPM_WDATA_LEN );
+
+REG64_FLD( EX_CPPM_PERRSUM_ERROR                                   , 0   , SH_UNT_EX       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_ERROR      );
+
+REG64_FLD( C_CPPM_PERRSUM_ERROR                                    , 0   , SH_UNT_C        , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_ERROR      );
+
+REG64_FLD( EQ_CSAR_SRAM_ADDRESS                                    , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_ADDRESS );
+REG64_FLD( EQ_CSAR_SRAM_ADDRESS_LEN                                , 13  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_ADDRESS_LEN );
+
+REG64_FLD( EX_CSAR_SRAM_ADDRESS                                    , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_ADDRESS );
+REG64_FLD( EX_CSAR_SRAM_ADDRESS_LEN                                , 13  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_ADDRESS_LEN );
+
+REG64_FLD( EQ_CSCR_SRAM_ACCESS_MODE                                , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_ACCESS_MODE );
+REG64_FLD( EQ_CSCR_SRAM_SCRUB_ENABLE                               , 1   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SCRUB_ENABLE );
+REG64_FLD( EQ_CSCR_ECC_CORRECT_DIS                                 , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_CORRECT_DIS );
+REG64_FLD( EQ_CSCR_ECC_DETECT_DIS                                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_DETECT_DIS );
+REG64_FLD( EQ_CSCR_ECC_INJECT_TYPE                                 , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_INJECT_TYPE );
+REG64_FLD( EQ_CSCR_ECC_INJECT_ERR                                  , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_INJECT_ERR );
+REG64_FLD( EQ_CSCR_SPARE_6_7                                       , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_6_7  );
+REG64_FLD( EQ_CSCR_SPARE_6_7_LEN                                   , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( EQ_CSCR_SRAM_SCRUB_INDEX                                , 47  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SCRUB_INDEX );
+REG64_FLD( EQ_CSCR_SRAM_SCRUB_INDEX_LEN                            , 13  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SCRUB_INDEX_LEN );
+
+REG64_FLD( EX_CSCR_SRAM_ACCESS_MODE                                , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_ACCESS_MODE );
+REG64_FLD( EX_CSCR_SRAM_SCRUB_ENABLE                               , 1   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SCRUB_ENABLE );
+REG64_FLD( EX_CSCR_ECC_CORRECT_DIS                                 , 2   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_CORRECT_DIS );
+REG64_FLD( EX_CSCR_ECC_DETECT_DIS                                  , 3   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_DETECT_DIS );
+REG64_FLD( EX_CSCR_ECC_INJECT_TYPE                                 , 4   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_INJECT_TYPE );
+REG64_FLD( EX_CSCR_ECC_INJECT_ERR                                  , 5   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_INJECT_ERR );
+REG64_FLD( EX_CSCR_SPARE_6_7                                       , 6   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_6_7  );
+REG64_FLD( EX_CSCR_SPARE_6_7_LEN                                   , 2   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( EX_CSCR_SRAM_SCRUB_INDEX                                , 47  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SCRUB_INDEX );
+REG64_FLD( EX_CSCR_SRAM_SCRUB_INDEX_LEN                            , 13  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SCRUB_INDEX_LEN );
+
+REG64_FLD( EQ_CSDR_SRAM_DATA                                       , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_DATA  );
+REG64_FLD( EQ_CSDR_SRAM_DATA_LEN                                   , 64  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_DATA_LEN );
+
+REG64_FLD( EX_CSDR_SRAM_DATA                                       , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_DATA  );
+REG64_FLD( EX_CSDR_SRAM_DATA_LEN                                   , 64  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_DATA_LEN );
+
+REG64_FLD( EX_L2_CTRL_T0_RUN_Q                                     , 48  , SH_UNT_EX_L2    , SH_ACS_SCOM_NC  ,
+           SH_FLD_T0_RUN_Q   );
+REG64_FLD( EX_L2_CTRL_T1_RUN_Q                                     , 49  , SH_UNT_EX_L2    , SH_ACS_SCOM_NC  ,
+           SH_FLD_T1_RUN_Q   );
+REG64_FLD( EX_L2_CTRL_T2_RUN_Q                                     , 50  , SH_UNT_EX_L2    , SH_ACS_SCOM_NC  ,
+           SH_FLD_T2_RUN_Q   );
+REG64_FLD( EX_L2_CTRL_T3_RUN_Q                                     , 51  , SH_UNT_EX_L2    , SH_ACS_SCOM_NC  ,
+           SH_FLD_T3_RUN_Q   );
+REG64_FLD( EX_L2_CTRL_T4_RUN_Q                                     , 52  , SH_UNT_EX_L2    , SH_ACS_SCOM_NC  ,
+           SH_FLD_T4_RUN_Q   );
+REG64_FLD( EX_L2_CTRL_T5_RUN_Q                                     , 53  , SH_UNT_EX_L2    , SH_ACS_SCOM_NC  ,
+           SH_FLD_T5_RUN_Q   );
+REG64_FLD( EX_L2_CTRL_T6_RUN_Q                                     , 54  , SH_UNT_EX_L2    , SH_ACS_SCOM_NC  ,
+           SH_FLD_T6_RUN_Q   );
+REG64_FLD( EX_L2_CTRL_T7_RUN_Q                                     , 55  , SH_UNT_EX_L2    , SH_ACS_SCOM_NC  ,
+           SH_FLD_T7_RUN_Q   );
+
+REG64_FLD( C_CTRL_T0_RUN_Q                                         , 48  , SH_UNT_C        , SH_ACS_SCOM_NC  ,
+           SH_FLD_T0_RUN_Q   );
+REG64_FLD( C_CTRL_T1_RUN_Q                                         , 49  , SH_UNT_C        , SH_ACS_SCOM_NC  ,
+           SH_FLD_T1_RUN_Q   );
+REG64_FLD( C_CTRL_T2_RUN_Q                                         , 50  , SH_UNT_C        , SH_ACS_SCOM_NC  ,
+           SH_FLD_T2_RUN_Q   );
+REG64_FLD( C_CTRL_T3_RUN_Q                                         , 51  , SH_UNT_C        , SH_ACS_SCOM_NC  ,
+           SH_FLD_T3_RUN_Q   );
+REG64_FLD( C_CTRL_T4_RUN_Q                                         , 52  , SH_UNT_C        , SH_ACS_SCOM_NC  ,
+           SH_FLD_T4_RUN_Q   );
+REG64_FLD( C_CTRL_T5_RUN_Q                                         , 53  , SH_UNT_C        , SH_ACS_SCOM_NC  ,
+           SH_FLD_T5_RUN_Q   );
+REG64_FLD( C_CTRL_T6_RUN_Q                                         , 54  , SH_UNT_C        , SH_ACS_SCOM_NC  ,
+           SH_FLD_T6_RUN_Q   );
+REG64_FLD( C_CTRL_T7_RUN_Q                                         , 55  , SH_UNT_C        , SH_ACS_SCOM_NC  ,
+           SH_FLD_T7_RUN_Q   );
+
+REG64_FLD( EQ_CTRL_ATOMIC_LOCK_REG_ENABLE                          , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( EQ_CTRL_ATOMIC_LOCK_REG_ID                              , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( EQ_CTRL_ATOMIC_LOCK_REG_ID_LEN                          , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ID_LEN     );
+REG64_FLD( EQ_CTRL_ATOMIC_LOCK_REG_ACTIVITY                        , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY   );
+REG64_FLD( EQ_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN                    , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( EX_CTRL_ATOMIC_LOCK_REG_ENABLE                          , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( EX_CTRL_ATOMIC_LOCK_REG_ID                              , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( EX_CTRL_ATOMIC_LOCK_REG_ID_LEN                          , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ID_LEN     );
+REG64_FLD( EX_CTRL_ATOMIC_LOCK_REG_ACTIVITY                        , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY   );
+REG64_FLD( EX_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN                    , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( C_CTRL_ATOMIC_LOCK_REG_ENABLE                           , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( C_CTRL_ATOMIC_LOCK_REG_ID                               , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ID         );
+REG64_FLD( C_CTRL_ATOMIC_LOCK_REG_ID_LEN                           , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ID_LEN     );
+REG64_FLD( C_CTRL_ATOMIC_LOCK_REG_ACTIVITY                         , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY   );
+REG64_FLD( C_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN                     , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACTIVITY_LEN );
+
+REG64_FLD( EQ_CTRL_PROTECT_MODE_REG_READ_ENABLE                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_READ_ENABLE );
+REG64_FLD( EQ_CTRL_PROTECT_MODE_REG_WRITE_ENABLE                   , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( EX_CTRL_PROTECT_MODE_REG_READ_ENABLE                    , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_READ_ENABLE );
+REG64_FLD( EX_CTRL_PROTECT_MODE_REG_WRITE_ENABLE                   , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( C_CTRL_PROTECT_MODE_REG_READ_ENABLE                     , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_READ_ENABLE );
+REG64_FLD( C_CTRL_PROTECT_MODE_REG_WRITE_ENABLE                    , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( EQ_DBG_CBS_CC_RESET_EP                                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_EP   );
+REG64_FLD( EQ_DBG_CBS_CC_OPCG_IP                                   , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_OPCG_IP    );
+REG64_FLD( EQ_DBG_CBS_CC_VITL_CLKOFF                               , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_VITL_CLKOFF );
+REG64_FLD( EQ_DBG_CBS_CC_TEST_ENABLE                               , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TEST_ENABLE );
+REG64_FLD( EQ_DBG_CBS_CC_REQ                                       , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_REQ        );
+REG64_FLD( EQ_DBG_CBS_CC_CMD                                       , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMD        );
+REG64_FLD( EQ_DBG_CBS_CC_CMD_LEN                                   , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMD_LEN    );
+REG64_FLD( EQ_DBG_CBS_CC_STATE                                     , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATE      );
+REG64_FLD( EQ_DBG_CBS_CC_STATE_LEN                                 , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STATE_LEN  );
+REG64_FLD( EQ_DBG_CBS_CC_SECURITY_DEBUG_MODE                       , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SECURITY_DEBUG_MODE );
+REG64_FLD( EQ_DBG_CBS_CC_PROTOCOL_ERROR                            , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PROTOCOL_ERROR );
+REG64_FLD( EQ_DBG_CBS_CC_PCB_IDLE                                  , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_IDLE   );
+REG64_FLD( EQ_DBG_CBS_CC_CURRENT_OPCG_MODE                         , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CURRENT_OPCG_MODE );
+REG64_FLD( EQ_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN                     , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CURRENT_OPCG_MODE_LEN );
+REG64_FLD( EQ_DBG_CBS_CC_LAST_OPCG_MODE                            , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_LAST_OPCG_MODE );
+REG64_FLD( EQ_DBG_CBS_CC_LAST_OPCG_MODE_LEN                        , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_LAST_OPCG_MODE_LEN );
+REG64_FLD( EQ_DBG_CBS_CC_PCB_ERROR                                 , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ERROR  );
+REG64_FLD( EQ_DBG_CBS_CC_PARITY_ERROR                              , 25  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ERROR );
+REG64_FLD( EQ_DBG_CBS_CC_ERROR                                     , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ERROR      );
+REG64_FLD( EQ_DBG_CBS_CC_CHIPLET_IS_ALIGNED                        , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_IS_ALIGNED );
+REG64_FLD( EQ_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET                   , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_REQUEST_SINCE_RESET );
+REG64_FLD( EQ_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE               , 29  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PARANOIA_TEST_ENABLE_CHANGE );
+REG64_FLD( EQ_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE               , 30  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE );
+REG64_FLD( EQ_DBG_CBS_CC_TP_TPFSI_ACK                              , 31  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TP_TPFSI_ACK );
+
+REG64_FLD( EX_DBG_CBS_CC_RESET_EP                                  , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_EP   );
+REG64_FLD( EX_DBG_CBS_CC_OPCG_IP                                   , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_OPCG_IP    );
+REG64_FLD( EX_DBG_CBS_CC_VITL_CLKOFF                               , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_VITL_CLKOFF );
+REG64_FLD( EX_DBG_CBS_CC_TEST_ENABLE                               , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TEST_ENABLE );
+REG64_FLD( EX_DBG_CBS_CC_REQ                                       , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_REQ        );
+REG64_FLD( EX_DBG_CBS_CC_CMD                                       , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CMD        );
+REG64_FLD( EX_DBG_CBS_CC_CMD_LEN                                   , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CMD_LEN    );
+REG64_FLD( EX_DBG_CBS_CC_STATE                                     , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATE      );
+REG64_FLD( EX_DBG_CBS_CC_STATE_LEN                                 , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STATE_LEN  );
+REG64_FLD( EX_DBG_CBS_CC_SECURITY_DEBUG_MODE                       , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SECURITY_DEBUG_MODE );
+REG64_FLD( EX_DBG_CBS_CC_PROTOCOL_ERROR                            , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PROTOCOL_ERROR );
+REG64_FLD( EX_DBG_CBS_CC_PCB_IDLE                                  , 15  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_IDLE   );
+REG64_FLD( EX_DBG_CBS_CC_CURRENT_OPCG_MODE                         , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CURRENT_OPCG_MODE );
+REG64_FLD( EX_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN                     , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CURRENT_OPCG_MODE_LEN );
+REG64_FLD( EX_DBG_CBS_CC_LAST_OPCG_MODE                            , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_LAST_OPCG_MODE );
+REG64_FLD( EX_DBG_CBS_CC_LAST_OPCG_MODE_LEN                        , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_LAST_OPCG_MODE_LEN );
+REG64_FLD( EX_DBG_CBS_CC_PCB_ERROR                                 , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ERROR  );
+REG64_FLD( EX_DBG_CBS_CC_PARITY_ERROR                              , 25  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ERROR );
+REG64_FLD( EX_DBG_CBS_CC_ERROR                                     , 26  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ERROR      );
+REG64_FLD( EX_DBG_CBS_CC_CHIPLET_IS_ALIGNED                        , 27  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_IS_ALIGNED );
+REG64_FLD( EX_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET                   , 28  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_REQUEST_SINCE_RESET );
+REG64_FLD( EX_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE               , 29  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PARANOIA_TEST_ENABLE_CHANGE );
+REG64_FLD( EX_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE               , 30  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE );
+REG64_FLD( EX_DBG_CBS_CC_TP_TPFSI_ACK                              , 31  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TP_TPFSI_ACK );
+
+REG64_FLD( C_DBG_CBS_CC_RESET_EP                                   , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESET_EP   );
+REG64_FLD( C_DBG_CBS_CC_OPCG_IP                                    , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_OPCG_IP    );
+REG64_FLD( C_DBG_CBS_CC_VITL_CLKOFF                                , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_VITL_CLKOFF );
+REG64_FLD( C_DBG_CBS_CC_TEST_ENABLE                                , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TEST_ENABLE );
+REG64_FLD( C_DBG_CBS_CC_REQ                                        , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_REQ        );
+REG64_FLD( C_DBG_CBS_CC_CMD                                        , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CMD        );
+REG64_FLD( C_DBG_CBS_CC_CMD_LEN                                    , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CMD_LEN    );
+REG64_FLD( C_DBG_CBS_CC_STATE                                      , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATE      );
+REG64_FLD( C_DBG_CBS_CC_STATE_LEN                                  , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STATE_LEN  );
+REG64_FLD( C_DBG_CBS_CC_SECURITY_DEBUG_MODE                        , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SECURITY_DEBUG_MODE );
+REG64_FLD( C_DBG_CBS_CC_PROTOCOL_ERROR                             , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PROTOCOL_ERROR );
+REG64_FLD( C_DBG_CBS_CC_PCB_IDLE                                   , 15  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PCB_IDLE   );
+REG64_FLD( C_DBG_CBS_CC_CURRENT_OPCG_MODE                          , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CURRENT_OPCG_MODE );
+REG64_FLD( C_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN                      , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CURRENT_OPCG_MODE_LEN );
+REG64_FLD( C_DBG_CBS_CC_LAST_OPCG_MODE                             , 20  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_LAST_OPCG_MODE );
+REG64_FLD( C_DBG_CBS_CC_LAST_OPCG_MODE_LEN                         , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_LAST_OPCG_MODE_LEN );
+REG64_FLD( C_DBG_CBS_CC_PCB_ERROR                                  , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ERROR  );
+REG64_FLD( C_DBG_CBS_CC_PARITY_ERROR                               , 25  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ERROR );
+REG64_FLD( C_DBG_CBS_CC_ERROR                                      , 26  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ERROR      );
+REG64_FLD( C_DBG_CBS_CC_CHIPLET_IS_ALIGNED                         , 27  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_IS_ALIGNED );
+REG64_FLD( C_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET                    , 28  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PCB_REQUEST_SINCE_RESET );
+REG64_FLD( C_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE                , 29  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PARANOIA_TEST_ENABLE_CHANGE );
+REG64_FLD( C_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE                , 30  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE );
+REG64_FLD( C_DBG_CBS_CC_TP_TPFSI_ACK                               , 31  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TP_TPFSI_ACK );
+
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND1_SEL_A                     , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN                 , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND1_SEL_B                     , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN                 , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND2_SEL_A                     , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN                 , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND2_SEL_B                     , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN                 , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_C1_INAROW_MODE                  , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1               , 33  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1               , 34  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1              , 35  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_UNUSED                          , 36  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_UNUSED_LEN                      , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_C2_INAROW_MODE                  , 39  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2               , 40  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2               , 41  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2              , 42  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_UNUSED_2                        , 43  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_UNUSED_2_LEN                    , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET              , 46  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_EXACT_TO_MODE                   , 47  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1             , 48  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_RESET_C3_ON_C0                  , 49  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_SLOW_TO_MODE                    , 50  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO            , 51  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_C1_COUNT_LT                     , 52  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN                 , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_C2_COUNT_LT                     , 56  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN                 , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_RESET_C3_SELECT                 , 60  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( EQ_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN             , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( EX_DBG_INST1_COND_REG_1_COND1_SEL_A                     , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN                 , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_COND1_SEL_B                     , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN                 , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_COND2_SEL_A                     , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN                 , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_COND2_SEL_B                     , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN                 , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_C1_INAROW_MODE                  , 32  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1               , 33  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1               , 34  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1              , 35  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_UNUSED                          , 36  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_UNUSED_LEN                      , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_C2_INAROW_MODE                  , 39  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2               , 40  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2               , 41  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2              , 42  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_UNUSED_2                        , 43  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_UNUSED_2_LEN                    , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET              , 46  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_EXACT_TO_MODE                   , 47  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1             , 48  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_RESET_C3_ON_C0                  , 49  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_SLOW_TO_MODE                    , 50  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO            , 51  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_C1_COUNT_LT                     , 52  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN                 , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_C2_COUNT_LT                     , 56  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN                 , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_RESET_C3_SELECT                 , 60  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( EX_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN             , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( C_DBG_INST1_COND_REG_1_COND1_SEL_A                      , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( C_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN                  , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( C_DBG_INST1_COND_REG_1_COND1_SEL_B                      , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( C_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN                  , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( C_DBG_INST1_COND_REG_1_COND2_SEL_A                      , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( C_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN                  , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( C_DBG_INST1_COND_REG_1_COND2_SEL_B                      , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( C_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN                  , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( C_DBG_INST1_COND_REG_1_C1_INAROW_MODE                   , 32  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( C_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1                , 33  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( C_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1                , 34  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( C_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1               , 35  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( C_DBG_INST1_COND_REG_1_UNUSED                           , 36  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( C_DBG_INST1_COND_REG_1_UNUSED_LEN                       , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( C_DBG_INST1_COND_REG_1_C2_INAROW_MODE                   , 39  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( C_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2                , 40  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( C_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2                , 41  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( C_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2               , 42  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( C_DBG_INST1_COND_REG_1_UNUSED_2                         , 43  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( C_DBG_INST1_COND_REG_1_UNUSED_2_LEN                     , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( C_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET               , 46  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( C_DBG_INST1_COND_REG_1_EXACT_TO_MODE                    , 47  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( C_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1              , 48  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( C_DBG_INST1_COND_REG_1_RESET_C3_ON_C0                   , 49  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( C_DBG_INST1_COND_REG_1_SLOW_TO_MODE                     , 50  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( C_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO             , 51  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( C_DBG_INST1_COND_REG_1_C1_COUNT_LT                      , 52  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( C_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN                  , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( C_DBG_INST1_COND_REG_1_C2_COUNT_LT                      , 56  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( C_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN                  , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( C_DBG_INST1_COND_REG_1_RESET_C3_SELECT                  , 60  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( C_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN              , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A         , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN     , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN     , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A           , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN       , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B           , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN       , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( EQ_DBG_INST1_COND_REG_2_TO_CMP_LT                       , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( EQ_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN                   , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( EQ_DBG_INST1_COND_REG_2_FORCE_TEST_MODE                 , 44  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A         , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN     , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B         , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN     , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A           , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN       , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B           , 15  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN       , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( EX_DBG_INST1_COND_REG_2_TO_CMP_LT                       , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( EX_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN                   , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( EX_DBG_INST1_COND_REG_2_FORCE_TEST_MODE                 , 44  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A          , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN      , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B          , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN      , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A            , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN        , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B            , 15  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN        , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( C_DBG_INST1_COND_REG_2_TO_CMP_LT                        , 20  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( C_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN                    , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( C_DBG_INST1_COND_REG_2_FORCE_TEST_MODE                  , 44  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( EQ_DBG_INST1_COND_REG_3_SP_COUNT_LT                     , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( EQ_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN                 , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( EX_DBG_INST1_COND_REG_3_SP_COUNT_LT                     , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( EX_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN                 , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( C_DBG_INST1_COND_REG_3_SP_COUNT_LT                      , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( C_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN                  , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND1_SEL_A                     , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN                 , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND1_SEL_B                     , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN                 , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND2_SEL_A                     , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN                 , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND2_SEL_B                     , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN                 , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_C1_INAROW_MODE                  , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1               , 33  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1               , 34  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1              , 35  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_UNUSED                          , 36  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_UNUSED_LEN                      , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_C2_INAROW_MODE                  , 39  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2               , 40  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2               , 41  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2              , 42  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_UNUSED_2                        , 43  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_UNUSED_2_LEN                    , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET              , 46  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_EXACT_TO_MODE                   , 47  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1             , 48  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_RESET_C3_ON_C0                  , 49  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_SLOW_TO_MODE                    , 50  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO            , 51  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_C1_COUNT_LT                     , 52  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN                 , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_C2_COUNT_LT                     , 56  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN                 , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_RESET_C3_SELECT                 , 60  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( EQ_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN             , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( EX_DBG_INST2_COND_REG_1_COND1_SEL_A                     , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN                 , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_COND1_SEL_B                     , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN                 , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_COND2_SEL_A                     , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN                 , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_COND2_SEL_B                     , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN                 , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_C1_INAROW_MODE                  , 32  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1               , 33  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1               , 34  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1              , 35  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_UNUSED                          , 36  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_UNUSED_LEN                      , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_C2_INAROW_MODE                  , 39  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2               , 40  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2               , 41  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2              , 42  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_UNUSED_2                        , 43  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_UNUSED_2_LEN                    , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET              , 46  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_EXACT_TO_MODE                   , 47  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1             , 48  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_RESET_C3_ON_C0                  , 49  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_SLOW_TO_MODE                    , 50  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO            , 51  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_C1_COUNT_LT                     , 52  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN                 , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_C2_COUNT_LT                     , 56  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN                 , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_RESET_C3_SELECT                 , 60  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( EX_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN             , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( C_DBG_INST2_COND_REG_1_COND1_SEL_A                      , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( C_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN                  , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( C_DBG_INST2_COND_REG_1_COND1_SEL_B                      , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( C_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN                  , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( C_DBG_INST2_COND_REG_1_COND2_SEL_A                      , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( C_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN                  , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( C_DBG_INST2_COND_REG_1_COND2_SEL_B                      , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( C_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN                  , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( C_DBG_INST2_COND_REG_1_C1_INAROW_MODE                   , 32  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( C_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1                , 33  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( C_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1                , 34  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( C_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1               , 35  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( C_DBG_INST2_COND_REG_1_UNUSED                           , 36  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( C_DBG_INST2_COND_REG_1_UNUSED_LEN                       , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( C_DBG_INST2_COND_REG_1_C2_INAROW_MODE                   , 39  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( C_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2                , 40  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( C_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2                , 41  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( C_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2               , 42  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( C_DBG_INST2_COND_REG_1_UNUSED_2                         , 43  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( C_DBG_INST2_COND_REG_1_UNUSED_2_LEN                     , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( C_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET               , 46  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( C_DBG_INST2_COND_REG_1_EXACT_TO_MODE                    , 47  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( C_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1              , 48  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( C_DBG_INST2_COND_REG_1_RESET_C3_ON_C0                   , 49  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( C_DBG_INST2_COND_REG_1_SLOW_TO_MODE                     , 50  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( C_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO             , 51  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( C_DBG_INST2_COND_REG_1_C1_COUNT_LT                      , 52  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( C_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN                  , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( C_DBG_INST2_COND_REG_1_C2_COUNT_LT                      , 56  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( C_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN                  , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( C_DBG_INST2_COND_REG_1_RESET_C3_SELECT                  , 60  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( C_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN              , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A         , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN     , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN     , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A           , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN       , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B           , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN       , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( EQ_DBG_INST2_COND_REG_2_TO_CMP_LT                       , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( EQ_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN                   , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( EQ_DBG_INST2_COND_REG_2_FORCE_TEST_MODE                 , 44  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A         , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN     , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B         , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN     , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A           , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN       , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B           , 15  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN       , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( EX_DBG_INST2_COND_REG_2_TO_CMP_LT                       , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( EX_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN                   , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( EX_DBG_INST2_COND_REG_2_FORCE_TEST_MODE                 , 44  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A          , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN      , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B          , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN      , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A            , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN        , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B            , 15  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN        , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( C_DBG_INST2_COND_REG_2_TO_CMP_LT                        , 20  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( C_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN                    , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( C_DBG_INST2_COND_REG_2_FORCE_TEST_MODE                  , 44  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( EQ_DBG_INST2_COND_REG_3_SP_COUNT_LT                     , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( EQ_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN                 , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( EX_DBG_INST2_COND_REG_3_SP_COUNT_LT                     , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( EX_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN                 , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( C_DBG_INST2_COND_REG_3_SP_COUNT_LT                      , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( C_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN                  , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( EQ_DBG_MODE_REG_GLB_BRCST                               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST  );
+REG64_FLD( EQ_DBG_MODE_REG_GLB_BRCST_LEN                           , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST_LEN );
+REG64_FLD( EQ_DBG_MODE_REG_TRACE_SEL                               , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SEL  );
+REG64_FLD( EQ_DBG_MODE_REG_TRIG_SEL                                , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG_SEL   );
+REG64_FLD( EQ_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION                 , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_XSTOP_SELECTION );
+REG64_FLD( EQ_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION             , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_RECOV_ERR_SELECTION );
+REG64_FLD( EQ_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION                , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_SPATTN_SELECTION );
+REG64_FLD( EQ_DBG_MODE_REG_FREEZE_SEL                              , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_SEL );
+
+REG64_FLD( EX_DBG_MODE_REG_GLB_BRCST                               , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST  );
+REG64_FLD( EX_DBG_MODE_REG_GLB_BRCST_LEN                           , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST_LEN );
+REG64_FLD( EX_DBG_MODE_REG_TRACE_SEL                               , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SEL  );
+REG64_FLD( EX_DBG_MODE_REG_TRIG_SEL                                , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG_SEL   );
+REG64_FLD( EX_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION                 , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_XSTOP_SELECTION );
+REG64_FLD( EX_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION             , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_RECOV_ERR_SELECTION );
+REG64_FLD( EX_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION                , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_SPATTN_SELECTION );
+REG64_FLD( EX_DBG_MODE_REG_FREEZE_SEL                              , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_SEL );
+
+REG64_FLD( C_DBG_MODE_REG_GLB_BRCST                                , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST  );
+REG64_FLD( C_DBG_MODE_REG_GLB_BRCST_LEN                            , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST_LEN );
+REG64_FLD( C_DBG_MODE_REG_TRACE_SEL                                , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SEL  );
+REG64_FLD( C_DBG_MODE_REG_TRIG_SEL                                 , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRIG_SEL   );
+REG64_FLD( C_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION                  , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_XSTOP_SELECTION );
+REG64_FLD( C_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION              , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_RECOV_ERR_SELECTION );
+REG64_FLD( C_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION                 , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_SPATTN_SELECTION );
+REG64_FLD( C_DBG_MODE_REG_FREEZE_SEL                               , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_SEL );
+
+REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE        , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE );
+REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN    , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN );
+REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_IMM_FREEZE                      , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IMM_FREEZE );
+REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_STOP_ON_ERR                     , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_ERR );
+REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH              , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_BANK_ON_RUNN_MATCH );
+REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_FORCE_TEST                      , 19  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST );
+REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_ACCUM_HIST                      , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUM_HIST );
+REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ                , 21  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FRZ_COUNT_ON_FRZ );
+
+REG64_FLD( EX_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE        , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE );
+REG64_FLD( EX_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN    , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN );
+REG64_FLD( EX_DBG_TRACE_MODE_REG_2_IMM_FREEZE                      , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IMM_FREEZE );
+REG64_FLD( EX_DBG_TRACE_MODE_REG_2_STOP_ON_ERR                     , 17  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_ERR );
+REG64_FLD( EX_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH              , 18  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_BANK_ON_RUNN_MATCH );
+REG64_FLD( EX_DBG_TRACE_MODE_REG_2_FORCE_TEST                      , 19  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST );
+REG64_FLD( EX_DBG_TRACE_MODE_REG_2_ACCUM_HIST                      , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUM_HIST );
+REG64_FLD( EX_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ                , 21  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FRZ_COUNT_ON_FRZ );
+
+REG64_FLD( C_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE         , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE );
+REG64_FLD( C_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN     , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN );
+REG64_FLD( C_DBG_TRACE_MODE_REG_2_IMM_FREEZE                       , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IMM_FREEZE );
+REG64_FLD( C_DBG_TRACE_MODE_REG_2_STOP_ON_ERR                      , 17  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_ERR );
+REG64_FLD( C_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH               , 18  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_BANK_ON_RUNN_MATCH );
+REG64_FLD( C_DBG_TRACE_MODE_REG_2_FORCE_TEST                       , 19  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST );
+REG64_FLD( C_DBG_TRACE_MODE_REG_2_ACCUM_HIST                       , 20  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACCUM_HIST );
+REG64_FLD( C_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ                 , 21  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FRZ_COUNT_ON_FRZ );
+
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_COND3_ENABLE                   , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_COND3_ENABLE );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_COND3_ENABLE                   , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_COND3_ENABLE );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST3_COND3_ENABLE                   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST3_COND3_ENABLE );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST4_COND3_ENABLE                   , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST4_COND3_ENABLE );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE                 , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_SLOW_LFSR_MODE );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE                 , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_SLOW_LFSR_MODE );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE                 , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST3_SLOW_LFSR_MODE );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE                 , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST4_SLOW_LFSR_MODE );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL            , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN        , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL            , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN        , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL            , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN        , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL            , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN        , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL            , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN        , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL            , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN        , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP                     , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_STOP );
+REG64_FLD( EQ_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE                   , 33  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_FREEZE );
+REG64_FLD( EQ_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL                   , 34  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL );
+REG64_FLD( EQ_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN               , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL                   , 39  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL );
+REG64_FLD( EQ_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN               , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_0_PC_TP_TRIG_SEL                       , 44  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL );
+REG64_FLD( EQ_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN                   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_0_ARM_SEL                              , 46  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL    );
+REG64_FLD( EQ_DBG_TRACE_REG_0_ARM_SEL_LEN                          , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL                      , 50  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL );
+REG64_FLD( EQ_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN                  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL                      , 54  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL );
+REG64_FLD( EQ_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN                  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL_LEN );
+
+REG64_FLD( EX_DBG_TRACE_REG_0_INST1_COND3_ENABLE                   , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_COND3_ENABLE );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST2_COND3_ENABLE                   , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_COND3_ENABLE );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST3_COND3_ENABLE                   , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST3_COND3_ENABLE );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST4_COND3_ENABLE                   , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST4_COND3_ENABLE );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE                 , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_SLOW_LFSR_MODE );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE                 , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_SLOW_LFSR_MODE );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE                 , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST3_SLOW_LFSR_MODE );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE                 , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST4_SLOW_LFSR_MODE );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL            , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN        , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL            , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN        , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL            , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN        , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL            , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN        , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL            , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN        , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL            , 18  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( EX_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN        , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP                     , 32  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_STOP );
+REG64_FLD( EX_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE                   , 33  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_FREEZE );
+REG64_FLD( EX_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL                   , 34  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL );
+REG64_FLD( EX_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN               , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL                   , 39  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL );
+REG64_FLD( EX_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN               , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_0_PC_TP_TRIG_SEL                       , 44  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL );
+REG64_FLD( EX_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN                   , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_0_ARM_SEL                              , 46  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL    );
+REG64_FLD( EX_DBG_TRACE_REG_0_ARM_SEL_LEN                          , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL                      , 50  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL );
+REG64_FLD( EX_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN                  , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL                      , 54  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL );
+REG64_FLD( EX_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN                  , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL_LEN );
+
+REG64_FLD( C_DBG_TRACE_REG_0_INST1_COND3_ENABLE                    , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_COND3_ENABLE );
+REG64_FLD( C_DBG_TRACE_REG_0_INST2_COND3_ENABLE                    , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_COND3_ENABLE );
+REG64_FLD( C_DBG_TRACE_REG_0_INST3_COND3_ENABLE                    , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST3_COND3_ENABLE );
+REG64_FLD( C_DBG_TRACE_REG_0_INST4_COND3_ENABLE                    , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST4_COND3_ENABLE );
+REG64_FLD( C_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE                  , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_SLOW_LFSR_MODE );
+REG64_FLD( C_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE                  , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_SLOW_LFSR_MODE );
+REG64_FLD( C_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE                  , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST3_SLOW_LFSR_MODE );
+REG64_FLD( C_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE                  , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST4_SLOW_LFSR_MODE );
+REG64_FLD( C_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL             , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL );
+REG64_FLD( C_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN         , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( C_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL             , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL );
+REG64_FLD( C_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN         , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( C_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL             , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( C_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN         , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( C_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL             , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL );
+REG64_FLD( C_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN         , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( C_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL             , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL );
+REG64_FLD( C_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN         , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( C_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL             , 18  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( C_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN         , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( C_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP                      , 32  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_STOP );
+REG64_FLD( C_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE                    , 33  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_FREEZE );
+REG64_FLD( C_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL                    , 34  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL );
+REG64_FLD( C_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN                , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL_LEN );
+REG64_FLD( C_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL                    , 39  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL );
+REG64_FLD( C_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN                , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL_LEN );
+REG64_FLD( C_DBG_TRACE_REG_0_PC_TP_TRIG_SEL                        , 44  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL );
+REG64_FLD( C_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN                    , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL_LEN );
+REG64_FLD( C_DBG_TRACE_REG_0_ARM_SEL                               , 46  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL    );
+REG64_FLD( C_DBG_TRACE_REG_0_ARM_SEL_LEN                           , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL_LEN );
+REG64_FLD( C_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL                       , 50  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL );
+REG64_FLD( C_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN                   , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL_LEN );
+REG64_FLD( C_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL                       , 54  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL );
+REG64_FLD( C_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN                   , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL_LEN );
+
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO           , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO           , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO           , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO           , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO           , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO           , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_WAITN );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN        , 25  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_WAITN );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN        , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN        , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_WAITN );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN        , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_WAITN );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN        , 29  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK         , 36  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_BANK );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK         , 37  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_BANK );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK         , 38  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK         , 39  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_BANK );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK         , 40  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_BANK );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK         , 41  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT              , 48  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN          , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR        , 51  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT              , 52  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN          , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR        , 55  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR );
+
+REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO           , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN       , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO           , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN       , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO           , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN       , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO           , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN       , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO           , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN       , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO           , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN       , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN        , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_WAITN );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN        , 25  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_WAITN );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN        , 26  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN        , 27  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_WAITN );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN        , 28  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_WAITN );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN        , 29  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK         , 36  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_BANK );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK         , 37  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_BANK );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK         , 38  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK         , 39  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_BANK );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK         , 40  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_BANK );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK         , 41  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT              , 48  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN          , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR        , 51  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT              , 52  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN          , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR        , 55  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR );
+
+REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO            , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO );
+REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN        , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO            , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO );
+REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN        , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( C_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO            , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( C_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN        , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO            , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO );
+REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN        , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO            , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO );
+REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN        , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( C_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO            , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( C_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN        , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN         , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_WAITN );
+REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN         , 25  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_WAITN );
+REG64_FLD( C_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN         , 26  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN         , 27  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_WAITN );
+REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN         , 28  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_WAITN );
+REG64_FLD( C_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN         , 29  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK          , 36  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_BANK );
+REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK          , 37  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_BANK );
+REG64_FLD( C_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK          , 38  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK          , 39  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_BANK );
+REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK          , 40  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_BANK );
+REG64_FLD( C_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK          , 41  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( C_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT               , 48  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT );
+REG64_FLD( C_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN           , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( C_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR         , 51  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR );
+REG64_FLD( C_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT               , 52  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT );
+REG64_FLD( C_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN           , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( C_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR         , 55  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR );
+
+REG64_FLD( EQ_DRAM_REF_REG_L3_TIMER_DIVIDE_MAJOR                   , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_TIMER_DIVIDE_MAJOR );
+REG64_FLD( EQ_DRAM_REF_REG_L3_TIMER_DIVIDE_MAJOR_LEN               , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_TIMER_DIVIDE_MAJOR_LEN );
+REG64_FLD( EQ_DRAM_REF_REG_L3_SCOM_INIT                            , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SCOM_INIT );
+REG64_FLD( EQ_DRAM_REF_REG_L3_SCOM_QUIESCE_CACHE                   , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SCOM_QUIESCE_CACHE );
+REG64_FLD( EQ_DRAM_REF_REG_L3_SCOM_QUIESCE_CACHE_LFSR              , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SCOM_QUIESCE_CACHE_LFSR );
+REG64_FLD( EQ_DRAM_REF_REG_L3_SCOM_QUIESCE_REFRESH                 , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SCOM_QUIESCE_REFRESH );
+REG64_FLD( EQ_DRAM_REF_REG_L3_TIMER_DIVIDE_MINOR                   , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_TIMER_DIVIDE_MINOR );
+REG64_FLD( EQ_DRAM_REF_REG_L3_TIMER_DIVIDE_MINOR_LEN               , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_TIMER_DIVIDE_MINOR_LEN );
+
+REG64_FLD( EX_DRAM_REF_REG_L3_TIMER_DIVIDE_MAJOR                   , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_TIMER_DIVIDE_MAJOR );
+REG64_FLD( EX_DRAM_REF_REG_L3_TIMER_DIVIDE_MAJOR_LEN               , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_TIMER_DIVIDE_MAJOR_LEN );
+REG64_FLD( EX_DRAM_REF_REG_L3_SCOM_INIT                            , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SCOM_INIT );
+REG64_FLD( EX_DRAM_REF_REG_L3_SCOM_QUIESCE_CACHE                   , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SCOM_QUIESCE_CACHE );
+REG64_FLD( EX_DRAM_REF_REG_L3_SCOM_QUIESCE_CACHE_LFSR              , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SCOM_QUIESCE_CACHE_LFSR );
+REG64_FLD( EX_DRAM_REF_REG_L3_SCOM_QUIESCE_REFRESH                 , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SCOM_QUIESCE_REFRESH );
+REG64_FLD( EX_DRAM_REF_REG_L3_TIMER_DIVIDE_MINOR                   , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_TIMER_DIVIDE_MINOR );
+REG64_FLD( EX_DRAM_REF_REG_L3_TIMER_DIVIDE_MINOR_LEN               , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_TIMER_DIVIDE_MINOR_LEN );
+
+REG64_FLD( EQ_DTS_RESULT0_0_RESULT                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_0_RESULT   );
+REG64_FLD( EQ_DTS_RESULT0_0_RESULT_LEN                             , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_0_RESULT_LEN );
+REG64_FLD( EQ_DTS_RESULT0_1_RESULT                                 , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_RESULT   );
+REG64_FLD( EQ_DTS_RESULT0_1_RESULT_LEN                             , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_RESULT_LEN );
+
+REG64_FLD( EX_DTS_RESULT0_0_RESULT                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_0_RESULT   );
+REG64_FLD( EX_DTS_RESULT0_0_RESULT_LEN                             , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_0_RESULT_LEN );
+REG64_FLD( EX_DTS_RESULT0_1_RESULT                                 , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_RESULT   );
+REG64_FLD( EX_DTS_RESULT0_1_RESULT_LEN                             , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_RESULT_LEN );
+
+REG64_FLD( C_DTS_RESULT0_0_RESULT                                  , 0   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_0_RESULT   );
+REG64_FLD( C_DTS_RESULT0_0_RESULT_LEN                              , 16  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_0_RESULT_LEN );
+REG64_FLD( C_DTS_RESULT0_1_RESULT                                  , 16  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_RESULT   );
+REG64_FLD( C_DTS_RESULT0_1_RESULT_LEN                              , 16  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_RESULT_LEN );
+
+REG64_FLD( EQ_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE               , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMESTAMP_COUNTER_VALUE );
+REG64_FLD( EQ_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN           , 44  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN );
+REG64_FLD( EQ_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR        , 44  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR );
+REG64_FLD( EQ_DTS_TRC_RESULT_1                                     , 48  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_1          );
+REG64_FLD( EQ_DTS_TRC_RESULT_1_LEN                                 , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_LEN      );
+
+REG64_FLD( EX_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE               , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMESTAMP_COUNTER_VALUE );
+REG64_FLD( EX_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN           , 44  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN );
+REG64_FLD( EX_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR        , 44  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR );
+REG64_FLD( EX_DTS_TRC_RESULT_1                                     , 48  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_1          );
+REG64_FLD( EX_DTS_TRC_RESULT_1_LEN                                 , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_LEN      );
+
+REG64_FLD( C_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE                , 0   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMESTAMP_COUNTER_VALUE );
+REG64_FLD( C_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN            , 44  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN );
+REG64_FLD( C_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR         , 44  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR );
+REG64_FLD( C_DTS_TRC_RESULT_1                                      , 48  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_1          );
+REG64_FLD( C_DTS_TRC_RESULT_1_LEN                                  , 16  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_1_LEN      );
+
+REG64_FLD( EQ_EDRAM_BANK_FAIL_SCOM_RD_L3                           , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3         );
+REG64_FLD( EQ_EDRAM_BANK_FAIL_SCOM_RD_L3_LEN                       , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LEN     );
+
+REG64_FLD( EX_L3_EDRAM_BANK_FAIL_SCOM_RD_L3                        , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3         );
+REG64_FLD( EX_L3_EDRAM_BANK_FAIL_SCOM_RD_L3_LEN                    , 3   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_LEN     );
+
+REG64_FLD( EQ_EDRAM_BANK_SOFT_DIS_L3_CFG                           , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_CFG     );
+REG64_FLD( EQ_EDRAM_BANK_SOFT_DIS_L3_CFG_LEN                       , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_CFG_LEN );
+
+REG64_FLD( EX_L3_EDRAM_BANK_SOFT_DIS_L3_CFG                        , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_CFG     );
+REG64_FLD( EX_L3_EDRAM_BANK_SOFT_DIS_L3_CFG_LEN                    , 10  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_CFG_LEN );
+
+REG64_FLD( EQ_EDRAM_REG_L3_CP_UTIL_EN_DC                           , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_CP_UTIL_EN_DC );
+REG64_FLD( EQ_EDRAM_REG_L3_CP_UTIL_SEL_DC                          , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_CP_UTIL_SEL_DC );
+REG64_FLD( EQ_EDRAM_REG_L3_CP_UTIL_SEL_DC_LEN                      , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_CP_UTIL_SEL_DC_LEN );
+REG64_FLD( EQ_EDRAM_REG_L3_SPARE3                                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SPARE3  );
+REG64_FLD( EQ_EDRAM_REG_L3_CP_UTIL_EXT_SEL                         , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_CP_UTIL_EXT_SEL );
+REG64_FLD( EQ_EDRAM_REG_L3_CP_UTIL_EXT_SEL_LEN                     , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_CP_UTIL_EXT_SEL_LEN );
+REG64_FLD( EQ_EDRAM_REG_L3_UTIL_MON_BITS                           , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_UTIL_MON_BITS );
+REG64_FLD( EQ_EDRAM_REG_L3_UTIL_MON_BITS_LEN                       , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_UTIL_MON_BITS_LEN );
+
+REG64_FLD( EX_L3_EDRAM_REG_L3_CP_UTIL_EN_DC                        , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_CP_UTIL_EN_DC );
+REG64_FLD( EX_L3_EDRAM_REG_L3_CP_UTIL_SEL_DC                       , 1   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_CP_UTIL_SEL_DC );
+REG64_FLD( EX_L3_EDRAM_REG_L3_CP_UTIL_SEL_DC_LEN                   , 2   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_CP_UTIL_SEL_DC_LEN );
+REG64_FLD( EX_L3_EDRAM_REG_L3_SPARE3                               , 3   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_SPARE3  );
+REG64_FLD( EX_L3_EDRAM_REG_L3_CP_UTIL_EXT_SEL                      , 4   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_CP_UTIL_EXT_SEL );
+REG64_FLD( EX_L3_EDRAM_REG_L3_CP_UTIL_EXT_SEL_LEN                  , 3   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_CP_UTIL_EXT_SEL_LEN );
+REG64_FLD( EX_L3_EDRAM_REG_L3_UTIL_MON_BITS                        , 7   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_UTIL_MON_BITS );
+REG64_FLD( EX_L3_EDRAM_REG_L3_UTIL_MON_BITS_LEN                    , 6   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_UTIL_MON_BITS_LEN );
+
+REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_VAL                           , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_VAL     );
+REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_UE                   , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_1ST_BEAT_UE );
+REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_UE                   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_2ND_BEAT_UE );
+REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_SPARE3                        , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SPARE3  );
+REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_SYNDROME             , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_1ST_BEAT_SYNDROME );
+REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_SYNDROME_LEN         , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_1ST_BEAT_SYNDROME_LEN );
+REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_SYNDROME             , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_2ND_BEAT_SYNDROME );
+REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_SYNDROME_LEN         , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_2ND_BEAT_SYNDROME_LEN );
+REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_DW                            , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DW      );
+REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_DW_LEN                        , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DW_LEN  );
+
+REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_VAL                           , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_VAL     );
+REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_UE                   , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_1ST_BEAT_UE );
+REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_UE                   , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_2ND_BEAT_UE );
+REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_SPARE3                        , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SPARE3  );
+REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_SYNDROME             , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_1ST_BEAT_SYNDROME );
+REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_SYNDROME_LEN         , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_1ST_BEAT_SYNDROME_LEN );
+REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_SYNDROME             , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_2ND_BEAT_SYNDROME );
+REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_SYNDROME_LEN         , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_2ND_BEAT_SYNDROME_LEN );
+REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_DW                            , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DW      );
+REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_DW_LEN                        , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DW_LEN  );
+
+REG64_FLD( EQ_ED_RD_ERR_STAT_REG1_L3_RA                            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_RA      );
+REG64_FLD( EQ_ED_RD_ERR_STAT_REG1_L3_RA_LEN                        , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_RA_LEN  );
+REG64_FLD( EQ_ED_RD_ERR_STAT_REG1_L3_BANK                          , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_BANK    );
+REG64_FLD( EQ_ED_RD_ERR_STAT_REG1_L3_BANK_LEN                      , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_BANK_LEN );
+
+REG64_FLD( EX_L3_ED_RD_ERR_STAT_REG1_L3_RA                         , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_RA      );
+REG64_FLD( EX_L3_ED_RD_ERR_STAT_REG1_L3_RA_LEN                     , 14  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_RA_LEN  );
+REG64_FLD( EX_L3_ED_RD_ERR_STAT_REG1_L3_BANK                       , 14  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_BANK    );
+REG64_FLD( EX_L3_ED_RD_ERR_STAT_REG1_L3_BANK_LEN                   , 4   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_BANK_LEN );
+
+REG64_FLD( EQ_ERROR_REG_CE                                         , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CE         );
+REG64_FLD( EQ_ERROR_REG_CHIPLET_ERRORS                             , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_ERRORS );
+REG64_FLD( EQ_ERROR_REG_CHIPLET_ERRORS_LEN                         , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_ERRORS_LEN );
+REG64_FLD( EQ_ERROR_REG_PARITY                                     , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PARITY     );
+REG64_FLD( EQ_ERROR_REG_DATA_BUFFER                                , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DATA_BUFFER );
+REG64_FLD( EQ_ERROR_REG_ADDR_BUFFER                                , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_BUFFER );
+REG64_FLD( EQ_ERROR_REG_PCB_FSM                                    , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_FSM    );
+REG64_FLD( EQ_ERROR_REG_CL_FSM                                     , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CL_FSM     );
+REG64_FLD( EQ_ERROR_REG_INT_RX_FSM                                 , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INT_RX_FSM );
+REG64_FLD( EQ_ERROR_REG_INT_TX_FSM                                 , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INT_TX_FSM );
+REG64_FLD( EQ_ERROR_REG_INT_TYPE                                   , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INT_TYPE   );
+REG64_FLD( EQ_ERROR_REG_CL_DATA                                    , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CL_DATA    );
+REG64_FLD( EQ_ERROR_REG_INFO                                       , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INFO       );
+REG64_FLD( EQ_ERROR_REG_UNUSED_0                                   , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_0   );
+REG64_FLD( EQ_ERROR_REG_CHIPLET_ATOMIC_LOCK                        , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_ATOMIC_LOCK );
+REG64_FLD( EQ_ERROR_REG_PCB_INTERFACE                              , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_INTERFACE );
+REG64_FLD( EQ_ERROR_REG_CHIPLET_OFFLINE                            , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_OFFLINE );
+REG64_FLD( EQ_ERROR_REG_CHIPLET_GRID_SKITTER                       , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_GRID_SKITTER );
+REG64_FLD( EQ_ERROR_REG_CTRL_PARITY                                , 19  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CTRL_PARITY );
+REG64_FLD( EQ_ERROR_REG_ADDRESS_PARITY                             , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ADDRESS_PARITY );
+REG64_FLD( EQ_ERROR_REG_TIMEOUT_PARITY                             , 21  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_PARITY );
+REG64_FLD( EQ_ERROR_REG_CONFIG_PARITY                              , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PARITY );
+REG64_FLD( EQ_ERROR_REG_UNUSED_1                                   , 23  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_1   );
+REG64_FLD( EQ_ERROR_REG_DIV_PARITY                                 , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DIV_PARITY );
+REG64_FLD( EQ_ERROR_REG_PLL_UNLOCK                                 , 25  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PLL_UNLOCK );
+REG64_FLD( EQ_ERROR_REG_PLL_UNLOCK_LEN                             , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PLL_UNLOCK_LEN );
+
+REG64_FLD( EX_ERROR_REG_CE                                         , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CE         );
+REG64_FLD( EX_ERROR_REG_CHIPLET_ERRORS                             , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_ERRORS );
+REG64_FLD( EX_ERROR_REG_CHIPLET_ERRORS_LEN                         , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_ERRORS_LEN );
+REG64_FLD( EX_ERROR_REG_PARITY                                     , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PARITY     );
+REG64_FLD( EX_ERROR_REG_DATA_BUFFER                                , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DATA_BUFFER );
+REG64_FLD( EX_ERROR_REG_ADDR_BUFFER                                , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_BUFFER );
+REG64_FLD( EX_ERROR_REG_PCB_FSM                                    , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_FSM    );
+REG64_FLD( EX_ERROR_REG_CL_FSM                                     , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CL_FSM     );
+REG64_FLD( EX_ERROR_REG_INT_RX_FSM                                 , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INT_RX_FSM );
+REG64_FLD( EX_ERROR_REG_INT_TX_FSM                                 , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INT_TX_FSM );
+REG64_FLD( EX_ERROR_REG_INT_TYPE                                   , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INT_TYPE   );
+REG64_FLD( EX_ERROR_REG_CL_DATA                                    , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CL_DATA    );
+REG64_FLD( EX_ERROR_REG_INFO                                       , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INFO       );
+REG64_FLD( EX_ERROR_REG_UNUSED_0                                   , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_0   );
+REG64_FLD( EX_ERROR_REG_CHIPLET_ATOMIC_LOCK                        , 15  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_ATOMIC_LOCK );
+REG64_FLD( EX_ERROR_REG_PCB_INTERFACE                              , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_INTERFACE );
+REG64_FLD( EX_ERROR_REG_CHIPLET_OFFLINE                            , 17  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_OFFLINE );
+REG64_FLD( EX_ERROR_REG_CHIPLET_GRID_SKITTER                       , 18  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_GRID_SKITTER );
+REG64_FLD( EX_ERROR_REG_CTRL_PARITY                                , 19  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CTRL_PARITY );
+REG64_FLD( EX_ERROR_REG_ADDRESS_PARITY                             , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ADDRESS_PARITY );
+REG64_FLD( EX_ERROR_REG_TIMEOUT_PARITY                             , 21  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_PARITY );
+REG64_FLD( EX_ERROR_REG_CONFIG_PARITY                              , 22  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PARITY );
+REG64_FLD( EX_ERROR_REG_UNUSED_1                                   , 23  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_1   );
+REG64_FLD( EX_ERROR_REG_DIV_PARITY                                 , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DIV_PARITY );
+REG64_FLD( EX_ERROR_REG_PLL_UNLOCK                                 , 25  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PLL_UNLOCK );
+REG64_FLD( EX_ERROR_REG_PLL_UNLOCK_LEN                             , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PLL_UNLOCK_LEN );
+
+REG64_FLD( C_ERROR_REG_CE                                          , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CE         );
+REG64_FLD( C_ERROR_REG_CHIPLET_ERRORS                              , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_ERRORS );
+REG64_FLD( C_ERROR_REG_CHIPLET_ERRORS_LEN                          , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_ERRORS_LEN );
+REG64_FLD( C_ERROR_REG_PARITY                                      , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PARITY     );
+REG64_FLD( C_ERROR_REG_DATA_BUFFER                                 , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DATA_BUFFER );
+REG64_FLD( C_ERROR_REG_ADDR_BUFFER                                 , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_BUFFER );
+REG64_FLD( C_ERROR_REG_PCB_FSM                                     , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PCB_FSM    );
+REG64_FLD( C_ERROR_REG_CL_FSM                                      , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CL_FSM     );
+REG64_FLD( C_ERROR_REG_INT_RX_FSM                                  , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INT_RX_FSM );
+REG64_FLD( C_ERROR_REG_INT_TX_FSM                                  , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INT_TX_FSM );
+REG64_FLD( C_ERROR_REG_INT_TYPE                                    , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INT_TYPE   );
+REG64_FLD( C_ERROR_REG_CL_DATA                                     , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CL_DATA    );
+REG64_FLD( C_ERROR_REG_INFO                                        , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INFO       );
+REG64_FLD( C_ERROR_REG_UNUSED_0                                    , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_0   );
+REG64_FLD( C_ERROR_REG_CHIPLET_ATOMIC_LOCK                         , 15  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_ATOMIC_LOCK );
+REG64_FLD( C_ERROR_REG_PCB_INTERFACE                               , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PCB_INTERFACE );
+REG64_FLD( C_ERROR_REG_CHIPLET_OFFLINE                             , 17  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_OFFLINE );
+REG64_FLD( C_ERROR_REG_CHIPLET_GRID_SKITTER                        , 18  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CHIPLET_GRID_SKITTER );
+REG64_FLD( C_ERROR_REG_CTRL_PARITY                                 , 19  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CTRL_PARITY );
+REG64_FLD( C_ERROR_REG_ADDRESS_PARITY                              , 20  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ADDRESS_PARITY );
+REG64_FLD( C_ERROR_REG_TIMEOUT_PARITY                              , 21  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_PARITY );
+REG64_FLD( C_ERROR_REG_CONFIG_PARITY                               , 22  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CONFIG_PARITY );
+REG64_FLD( C_ERROR_REG_UNUSED_1                                    , 23  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_1   );
+REG64_FLD( C_ERROR_REG_DIV_PARITY                                  , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DIV_PARITY );
+REG64_FLD( C_ERROR_REG_PLL_UNLOCK                                  , 25  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PLL_UNLOCK );
+REG64_FLD( C_ERROR_REG_PLL_UNLOCK_LEN                              , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PLL_UNLOCK_LEN );
+
+REG64_FLD( EQ_ERROR_STATUS_ERRORS                                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ERRORS     );
+REG64_FLD( EQ_ERROR_STATUS_ERRORS_LEN                              , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ERRORS_LEN );
+
+REG64_FLD( EX_ERROR_STATUS_ERRORS                                  , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ERRORS     );
+REG64_FLD( EX_ERROR_STATUS_ERRORS_LEN                              , 32  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ERRORS_LEN );
+
+REG64_FLD( C_ERROR_STATUS_ERRORS                                   , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ERRORS     );
+REG64_FLD( C_ERROR_STATUS_ERRORS_LEN                               , 32  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ERRORS_LEN );
+
+REG64_FLD( EQ_ERR_INJ_REG_L3_SINGLE_CAC                            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SINGLE_CAC );
+REG64_FLD( EQ_ERR_INJ_REG_L3_SOLID_CAC                             , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SOLID_CAC );
+REG64_FLD( EQ_ERR_INJ_REG_L3_CAC_TYPE                              , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_CAC_TYPE );
+REG64_FLD( EQ_ERR_INJ_REG_L3_CAC_TYPE_LEN                          , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_CAC_TYPE_LEN );
+REG64_FLD( EQ_ERR_INJ_REG_L3_SINGLE_DIR                            , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SINGLE_DIR );
+REG64_FLD( EQ_ERR_INJ_REG_L3_SOLID_DIR                             , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SOLID_DIR );
+REG64_FLD( EQ_ERR_INJ_REG_L3_DIR_TYPE                              , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DIR_TYPE );
+REG64_FLD( EQ_ERR_INJ_REG_L3_SINGLE_LRU                            , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SINGLE_LRU );
+REG64_FLD( EQ_ERR_INJ_REG_L3_SOLID_LRU                             , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SOLID_LRU );
+
+REG64_FLD( EX_L2_ERR_INJ_REG_DW_TYPE                               , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_DW_TYPE    );
+REG64_FLD( EX_L2_ERR_INJ_REG_DW_TYPE_LEN                           , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_DW_TYPE_LEN );
+REG64_FLD( EX_L2_ERR_INJ_REG_CW_TYPE                               , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_CW_TYPE    );
+REG64_FLD( EX_L2_ERR_INJ_REG_CW_TYPE_LEN                           , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_CW_TYPE_LEN );
+REG64_FLD( EX_L2_ERR_INJ_REG_STQ_TYPE                              , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_TYPE   );
+REG64_FLD( EX_L2_ERR_INJ_REG_STQ_TYPE_LEN                          , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_STQ_TYPE_LEN );
+REG64_FLD( EX_L2_ERR_INJ_REG_CPI_TYPE                              , 10  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_CPI_TYPE   );
+REG64_FLD( EX_L2_ERR_INJ_REG_CPI_TYPE_LEN                          , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_CPI_TYPE_LEN );
+REG64_FLD( EX_L2_ERR_INJ_REG_LVDIR_EN                              , 13  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_LVDIR_EN   );
+
+REG64_FLD( EX_L3_ERR_INJ_REG_L3_SINGLE_CAC                         , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_SINGLE_CAC );
+REG64_FLD( EX_L3_ERR_INJ_REG_L3_SOLID_CAC                          , 1   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_SOLID_CAC );
+REG64_FLD( EX_L3_ERR_INJ_REG_L3_CAC_TYPE                           , 2   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_CAC_TYPE );
+REG64_FLD( EX_L3_ERR_INJ_REG_L3_CAC_TYPE_LEN                       , 2   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_CAC_TYPE_LEN );
+REG64_FLD( EX_L3_ERR_INJ_REG_L3_SINGLE_DIR                         , 4   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_SINGLE_DIR );
+REG64_FLD( EX_L3_ERR_INJ_REG_L3_SOLID_DIR                          , 5   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_SOLID_DIR );
+REG64_FLD( EX_L3_ERR_INJ_REG_L3_DIR_TYPE                           , 6   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_DIR_TYPE );
+REG64_FLD( EX_L3_ERR_INJ_REG_L3_SINGLE_LRU                         , 7   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_SINGLE_LRU );
+REG64_FLD( EX_L3_ERR_INJ_REG_L3_SOLID_LRU                          , 8   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_SOLID_LRU );
+
+REG64_FLD( EQ_ERR_RPT0_FIR14_NCCTL_RLD_BARRIER                     , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_NCCTL_RLD_BARRIER );
+REG64_FLD( EQ_ERR_RPT0_FIR14_NCCTL_SNP                             , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_NCCTL_SNP );
+REG64_FLD( EQ_ERR_RPT0_FIR14_NCCTL_TLBIE_ACK                       , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_NCCTL_TLBIE_ACK );
+REG64_FLD( EQ_ERR_RPT0_FIR14_NCCTL_SYNC                            , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_NCCTL_SYNC );
+REG64_FLD( EQ_ERR_RPT0_FIR14_NCCTL_VSYNC                           , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_NCCTL_VSYNC );
+REG64_FLD( EQ_ERR_RPT0_FIR14_TMCTL_TIDX_TEND_LDST_SEQ              , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_TMCTL_TIDX_TEND_LDST_SEQ );
+REG64_FLD( EQ_ERR_RPT0_FIR14_RVCTL                                 , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RVCTL );
+REG64_FLD( EQ_ERR_RPT0_FIR14_SRCTL0_BAD_HPC                        , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_SRCTL0_BAD_HPC );
+REG64_FLD( EQ_ERR_RPT0_FIR14_SRCTL1_BAD_HPC                        , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_SRCTL1_BAD_HPC );
+REG64_FLD( EQ_ERR_RPT0_FIR14_SRCTL2_BAD_HPC                        , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_SRCTL2_BAD_HPC );
+REG64_FLD( EQ_ERR_RPT0_FIR14_SRCTL3_BAD_HPC                        , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_SRCTL3_BAD_HPC );
+REG64_FLD( EQ_ERR_RPT0_FIR14_PBARB_FSM_REQ_OVERFLOW                , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_PBARB_FSM_REQ_OVERFLOW );
+REG64_FLD( EQ_ERR_RPT0_FIR14_PBARB_TRASHMODE_PB_REQ                , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_PBARB_TRASHMODE_PB_REQ );
+REG64_FLD( EQ_ERR_RPT0_FIR14_L3PF_MACH_DONE                        , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_L3PF_MACH_DONE );
+REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD0_TTAG_PERR                       , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD0_TTAG_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD1_TTAG_PERR                       , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD1_TTAG_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD2_TTAG_PERR                       , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD2_TTAG_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD3_TTAG_PERR                       , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD3_TTAG_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR14_CR0_TTAG_PERR                         , 19  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR0_TTAG_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR14_CR0_ATAG_PERR                         , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR0_ATAG_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR14_CR1_TTAG_PERR                         , 21  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR1_TTAG_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR14_CR1_ATAG_PERR                         , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR1_ATAG_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR14_CR2_TTAG_PERR                         , 23  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR2_TTAG_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR14_CR2_ATAG_PERR                         , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR2_ATAG_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR14_CR3_TTAG_PERR                         , 25  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR3_TTAG_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR14_CR3_ATAG_PERR                         , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR3_ATAG_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD0_ADDR_PERR                       , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD0_ADDR_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD1_ADDR_PERR                       , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD1_ADDR_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD2_ADDR_PERR                       , 29  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD2_ADDR_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD3_ADDR_PERR                       , 30  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD3_ADDR_PERR );
+REG64_FLD( EQ_ERR_RPT0_FIR9_PEC_PHASE3_TIMEOUT                     , 31  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR9_PEC_PHASE3_TIMEOUT );
+REG64_FLD( EQ_ERR_RPT0_FIR9_PEC_PHASE4_SAME                        , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR9_PEC_PHASE4_SAME );
+REG64_FLD( EQ_ERR_RPT0_FIR9_PEC_PHASE4_RCCO_DISP_FAIL              , 33  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR9_PEC_PHASE4_RCCO_DISP_FAIL );
+REG64_FLD( EQ_ERR_RPT0_FIR9_PEC_PHASE5_TIMEOUT                     , 34  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR9_PEC_PHASE5_TIMEOUT );
+REG64_FLD( EQ_ERR_RPT0_FIR14_B01_BOTH_ACTIVE                       , 35  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_B01_BOTH_ACTIVE );
+REG64_FLD( EQ_ERR_RPT0_FIR14_PHANTOM_B01_REQ                       , 36  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_PHANTOM_B01_REQ );
+REG64_FLD( EQ_ERR_RPT0_FIR14_RC_UNEXP_F2_DATA                      , 37  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RC_UNEXP_F2_DATA );
+REG64_FLD( EQ_ERR_RPT0_FIR14_RC_UNEXP_PURG_HIT                     , 38  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RC_UNEXP_PURG_HIT );
+REG64_FLD( EQ_ERR_RPT0_FIR14_RCX_UNEXP_IDLE_PBL3_DATA              , 39  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCX_UNEXP_IDLE_PBL3_DATA );
+REG64_FLD( EQ_ERR_RPT0_FIR14_RCX_UNEXP_IDLE_PB_CRESP               , 40  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCX_UNEXP_IDLE_PB_CRESP );
+REG64_FLD( EQ_ERR_RPT0_FIR14_COX_UNEXP_IDLE_PB_CRESP               , 41  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_COX_UNEXP_IDLE_PB_CRESP );
+
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_NCCTL_RLD_BARRIER                  , 1   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_NCCTL_RLD_BARRIER );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_NCCTL_SNP                          , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_NCCTL_SNP );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_NCCTL_TLBIE_ACK                    , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_NCCTL_TLBIE_ACK );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_NCCTL_SYNC                         , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_NCCTL_SYNC );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_NCCTL_VSYNC                        , 5   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_NCCTL_VSYNC );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_TMCTL_TIDX_TEND_LDST_SEQ           , 6   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_TMCTL_TIDX_TEND_LDST_SEQ );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_RVCTL                              , 7   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RVCTL );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_SRCTL0_BAD_HPC                     , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_SRCTL0_BAD_HPC );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_SRCTL1_BAD_HPC                     , 9   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_SRCTL1_BAD_HPC );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_SRCTL2_BAD_HPC                     , 10  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_SRCTL2_BAD_HPC );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_SRCTL3_BAD_HPC                     , 11  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_SRCTL3_BAD_HPC );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_PBARB_FSM_REQ_OVERFLOW             , 12  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_PBARB_FSM_REQ_OVERFLOW );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_PBARB_TRASHMODE_PB_REQ             , 13  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_PBARB_TRASHMODE_PB_REQ );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_L3PF_MACH_DONE                     , 14  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_L3PF_MACH_DONE );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD0_TTAG_PERR                    , 15  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD0_TTAG_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD1_TTAG_PERR                    , 16  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD1_TTAG_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD2_TTAG_PERR                    , 17  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD2_TTAG_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD3_TTAG_PERR                    , 18  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD3_TTAG_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR0_TTAG_PERR                      , 19  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR0_TTAG_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR0_ATAG_PERR                      , 20  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR0_ATAG_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR1_TTAG_PERR                      , 21  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR1_TTAG_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR1_ATAG_PERR                      , 22  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR1_ATAG_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR2_TTAG_PERR                      , 23  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR2_TTAG_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR2_ATAG_PERR                      , 24  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR2_ATAG_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR3_TTAG_PERR                      , 25  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR3_TTAG_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR3_ATAG_PERR                      , 26  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_CR3_ATAG_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD0_ADDR_PERR                    , 27  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD0_ADDR_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD1_ADDR_PERR                    , 28  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD1_ADDR_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD2_ADDR_PERR                    , 29  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD2_ADDR_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD3_ADDR_PERR                    , 30  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCMD3_ADDR_PERR );
+REG64_FLD( EX_L2_ERR_RPT0_FIR9_PEC_PHASE3_TIMEOUT                  , 31  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR9_PEC_PHASE3_TIMEOUT );
+REG64_FLD( EX_L2_ERR_RPT0_FIR9_PEC_PHASE4_SAME                     , 32  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR9_PEC_PHASE4_SAME );
+REG64_FLD( EX_L2_ERR_RPT0_FIR9_PEC_PHASE4_RCCO_DISP_FAIL           , 33  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR9_PEC_PHASE4_RCCO_DISP_FAIL );
+REG64_FLD( EX_L2_ERR_RPT0_FIR9_PEC_PHASE5_TIMEOUT                  , 34  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR9_PEC_PHASE5_TIMEOUT );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_B01_BOTH_ACTIVE                    , 35  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_B01_BOTH_ACTIVE );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_PHANTOM_B01_REQ                    , 36  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_PHANTOM_B01_REQ );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_RC_UNEXP_F2_DATA                   , 37  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RC_UNEXP_F2_DATA );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_RC_UNEXP_PURG_HIT                  , 38  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RC_UNEXP_PURG_HIT );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCX_UNEXP_IDLE_PBL3_DATA           , 39  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCX_UNEXP_IDLE_PBL3_DATA );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCX_UNEXP_IDLE_PB_CRESP            , 40  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCX_UNEXP_IDLE_PB_CRESP );
+REG64_FLD( EX_L2_ERR_RPT0_FIR14_COX_UNEXP_IDLE_PB_CRESP            , 41  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_COX_UNEXP_IDLE_PB_CRESP );
+
+REG64_FLD( EQ_ERR_RPT1_FIR14_RCX_UNEXP_IDLE_L3_CRESP               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_CRESP );
+REG64_FLD( EQ_ERR_RPT1_FIR14_RCX_UNEXP_IDLE_L3_DWDONE              , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_DWDONE );
+REG64_FLD( EQ_ERR_RPT1_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK             , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK );
+REG64_FLD( EQ_ERR_RPT1_FIR14_DW_SET_REF_WITH_FLAG_IDLE             , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_DW_SET_REF_WITH_FLAG_IDLE );
+REG64_FLD( EQ_ERR_RPT1_FIR14_KILL_REF_WITH_FLAG_IDLE               , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_KILL_REF_WITH_FLAG_IDLE );
+REG64_FLD( EQ_ERR_RPT1_FIR14_DW_SET_SI_BY_MACH                     , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_DW_SET_SI_BY_MACH );
+REG64_FLD( EQ_ERR_RPT1_FIR14_PD_DIR_MULT_HIT                       , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_PD_DIR_MULT_HIT );
+REG64_FLD( EQ_ERR_RPT1_FIR14_B0_SD_DIR_MULT_HIT                    , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_B0_SD_DIR_MULT_HIT );
+REG64_FLD( EQ_ERR_RPT1_FIR14_B1_SD_DIR_MULT_HIT                    , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_B1_SD_DIR_MULT_HIT );
+REG64_FLD( EQ_ERR_RPT1_FIR14_B2_SD_DIR_MULT_HIT                    , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_B2_SD_DIR_MULT_HIT );
+REG64_FLD( EQ_ERR_RPT1_FIR14_B3_SD_DIR_MULT_HIT                    , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_B3_SD_DIR_MULT_HIT );
+REG64_FLD( EQ_ERR_RPT1_FIR14_INVALID_SNP_CPS_STATU_RTN             , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_INVALID_SNP_CPS_STATU_RTN );
+REG64_FLD( EQ_ERR_RPT1_FIR14_HANG_WAITING_FOR_FP_MATE              , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_HANG_WAITING_FOR_FP_MATE );
+REG64_FLD( EQ_ERR_RPT1_FIR14_BAD_FP_MATE                           , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_BAD_FP_MATE );
+REG64_FLD( EQ_ERR_RPT1_FIR14_LSU_TAG_REUSE                         , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_LSU_TAG_REUSE );
+REG64_FLD( EQ_ERR_RPT1_FIR14_IFU_MULT_REQ                          , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_IFU_MULT_REQ );
+REG64_FLD( EQ_ERR_RPT1_FIR14_XPF_MULT_REQ                          , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_XPF_MULT_REQ );
+REG64_FLD( EQ_ERR_RPT1_FIR14_XLT_QUEUE_OVRFLW                      , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_XLT_QUEUE_OVRFLW );
+REG64_FLD( EQ_ERR_RPT1_FIR14_L3PF_REQ                              , 19  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_L3PF_REQ );
+REG64_FLD( EQ_ERR_RPT1_FIR14_NCU_TID_DONE                          , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_NCU_TID_DONE );
+REG64_FLD( EQ_ERR_RPT1_FIR11_LRU_MEM_INVALID_ABCD                  , 21  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR11_LRU_MEM_INVALID_ABCD );
+REG64_FLD( EQ_ERR_RPT1_FIR11_LRU_MEM_INVALID_EFGH                  , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR11_LRU_MEM_INVALID_EFGH );
+REG64_FLD( EQ_ERR_RPT1_FIR14_STQ_COMING                            , 23  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_STQ_COMING );
+REG64_FLD( EQ_ERR_RPT1_FIR14_STQ_OVERFLOW                          , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_STQ_OVERFLOW );
+REG64_FLD( EQ_ERR_RPT1_FIR14_RC_PBBUS_SFSTAT                       , 25  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RC_PBBUS_SFSTAT );
+REG64_FLD( EQ_ERR_RPT1_FIR14_TMA_LARXA_VS_FRCMISS_SV               , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_TMA_LARXA_VS_FRCMISS_SV );
+REG64_FLD( EQ_ERR_RPT1_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC           , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC );
+REG64_FLD( EQ_ERR_RPT1_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC           , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC );
+REG64_FLD( EQ_ERR_RPT1_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK         , 29  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK );
+
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_RCX_UNEXP_IDLE_L3_CRESP            , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_CRESP );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_RCX_UNEXP_IDLE_L3_DWDONE           , 1   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_DWDONE );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK          , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_DW_SET_REF_WITH_FLAG_IDLE          , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_DW_SET_REF_WITH_FLAG_IDLE );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_KILL_REF_WITH_FLAG_IDLE            , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_KILL_REF_WITH_FLAG_IDLE );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_DW_SET_SI_BY_MACH                  , 6   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_DW_SET_SI_BY_MACH );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_PD_DIR_MULT_HIT                    , 7   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_PD_DIR_MULT_HIT );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_B0_SD_DIR_MULT_HIT                 , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_B0_SD_DIR_MULT_HIT );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_B1_SD_DIR_MULT_HIT                 , 9   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_B1_SD_DIR_MULT_HIT );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_B2_SD_DIR_MULT_HIT                 , 10  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_B2_SD_DIR_MULT_HIT );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_B3_SD_DIR_MULT_HIT                 , 11  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_B3_SD_DIR_MULT_HIT );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_INVALID_SNP_CPS_STATU_RTN          , 12  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_INVALID_SNP_CPS_STATU_RTN );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_HANG_WAITING_FOR_FP_MATE           , 13  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_HANG_WAITING_FOR_FP_MATE );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_BAD_FP_MATE                        , 14  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_BAD_FP_MATE );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_LSU_TAG_REUSE                      , 15  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_LSU_TAG_REUSE );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_IFU_MULT_REQ                       , 16  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_IFU_MULT_REQ );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_XPF_MULT_REQ                       , 17  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_XPF_MULT_REQ );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_XLT_QUEUE_OVRFLW                   , 18  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_XLT_QUEUE_OVRFLW );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_L3PF_REQ                           , 19  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_L3PF_REQ );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_NCU_TID_DONE                       , 20  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_NCU_TID_DONE );
+REG64_FLD( EX_L2_ERR_RPT1_FIR11_LRU_MEM_INVALID_ABCD               , 21  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR11_LRU_MEM_INVALID_ABCD );
+REG64_FLD( EX_L2_ERR_RPT1_FIR11_LRU_MEM_INVALID_EFGH               , 22  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR11_LRU_MEM_INVALID_EFGH );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_STQ_COMING                         , 23  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_STQ_COMING );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_STQ_OVERFLOW                       , 24  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_STQ_OVERFLOW );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_RC_PBBUS_SFSTAT                    , 25  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RC_PBBUS_SFSTAT );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_TMA_LARXA_VS_FRCMISS_SV            , 26  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_TMA_LARXA_VS_FRCMISS_SV );
+REG64_FLD( EX_L2_ERR_RPT1_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC        , 27  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC );
+REG64_FLD( EX_L2_ERR_RPT1_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC        , 28  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC );
+REG64_FLD( EX_L2_ERR_RPT1_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK      , 29  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK );
+
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_OVERFLOW                            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_OVERFLOW );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_ILLEGAL_STORE_SIZE                  , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_ILLEGAL_STORE_SIZE );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_LD_AMO_SEQ                          , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_LD_AMO_SEQ );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR0_TTAG_PERR                       , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR0_TTAG_PERR );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR0_ATAG_PERR                       , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR0_ATAG_PERR );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR1_TTAG_PERR                       , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR1_TTAG_PERR );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR1_ATAG_PERR                       , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR1_ATAG_PERR );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR2_TTAG_PERR                       , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR2_TTAG_PERR );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR2_ATAG_PERR                       , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR2_ATAG_PERR );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR3_TTAG_PERR                       , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR3_TTAG_PERR );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR3_ATAG_PERR                       , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR3_ATAG_PERR );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_SNP0_ADDR_PERR                      , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_SNP0_ADDR_PERR );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_SNP0_TTAG_PERR                      , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_SNP0_TTAG_PERR );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_SNP1_ADDR_PERR                      , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_SNP1_ADDR_PERR );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_SNP1_TTAG_PERR                      , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_SNP1_TTAG_PERR );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_PBARB_TRASHMODE                     , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PBARB_TRASHMODE );
+REG64_FLD( EQ_ERR_RPT_REG_FIR1_TLBIE_BAD_OP                        , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR1_TLBIE_BAD_OP );
+REG64_FLD( EQ_ERR_RPT_REG_FIR1_MASTER_SEQ_ID_PAR                   , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR1_MASTER_SEQ_ID_PAR );
+REG64_FLD( EQ_ERR_RPT_REG_FIR1_SNOOP_TLBIE_SEQ_PARITY              , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR1_SNOOP_TLBIE_SEQ_PARITY );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_PURGE_LVL_ERR1                      , 19  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PURGE_LVL_ERR1 );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_PURGE_LVL_ERR2                      , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PURGE_LVL_ERR2 );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_PURGE_ABORT_LVL_ERR1                , 21  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PURGE_ABORT_LVL_ERR1 );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_PURGE_ABORT_LVL_ERR2                , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PURGE_ABORT_LVL_ERR2 );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_PURGE_DONE_LVL_ERR1                 , 23  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PURGE_DONE_LVL_ERR1 );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_IMA_FSM_TIMEOUT                     , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_IMA_FSM_TIMEOUT );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_PPE_WR_FSM_TIMEOUT                  , 25  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PPE_WR_FSM_TIMEOUT );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_PPE_RD_FSM_TIMEOUT                  , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PPE_RD_FSM_TIMEOUT );
+REG64_FLD( EQ_ERR_RPT_REG_FIR0_TLB_DATA_PAR                        , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_TLB_DATA_PAR );
+REG64_FLD( EQ_ERR_RPT_REG_FIR19_LD_TGT_NODAL_DINC                  , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR19_LD_TGT_NODAL_DINC );
+REG64_FLD( EQ_ERR_RPT_REG_FIR19_ST_TGT_NODAL_DINC                  , 29  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FIR19_ST_TGT_NODAL_DINC );
+
+REG64_FLD( EX_ERR_RPT_REG_FIR0_OVERFLOW                            , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_OVERFLOW );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_ILLEGAL_STORE_SIZE                  , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_ILLEGAL_STORE_SIZE );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_LD_AMO_SEQ                          , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_LD_AMO_SEQ );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_CR0_TTAG_PERR                       , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR0_TTAG_PERR );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_CR0_ATAG_PERR                       , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR0_ATAG_PERR );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_CR1_TTAG_PERR                       , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR1_TTAG_PERR );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_CR1_ATAG_PERR                       , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR1_ATAG_PERR );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_CR2_TTAG_PERR                       , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR2_TTAG_PERR );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_CR2_ATAG_PERR                       , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR2_ATAG_PERR );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_CR3_TTAG_PERR                       , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR3_TTAG_PERR );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_CR3_ATAG_PERR                       , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_CR3_ATAG_PERR );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_SNP0_ADDR_PERR                      , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_SNP0_ADDR_PERR );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_SNP0_TTAG_PERR                      , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_SNP0_TTAG_PERR );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_SNP1_ADDR_PERR                      , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_SNP1_ADDR_PERR );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_SNP1_TTAG_PERR                      , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_SNP1_TTAG_PERR );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_PBARB_TRASHMODE                     , 15  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PBARB_TRASHMODE );
+REG64_FLD( EX_ERR_RPT_REG_FIR1_TLBIE_BAD_OP                        , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR1_TLBIE_BAD_OP );
+REG64_FLD( EX_ERR_RPT_REG_FIR1_MASTER_SEQ_ID_PAR                   , 17  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR1_MASTER_SEQ_ID_PAR );
+REG64_FLD( EX_ERR_RPT_REG_FIR1_SNOOP_TLBIE_SEQ_PARITY              , 18  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR1_SNOOP_TLBIE_SEQ_PARITY );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_PURGE_LVL_ERR1                      , 19  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PURGE_LVL_ERR1 );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_PURGE_LVL_ERR2                      , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PURGE_LVL_ERR2 );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_PURGE_ABORT_LVL_ERR1                , 21  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PURGE_ABORT_LVL_ERR1 );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_PURGE_ABORT_LVL_ERR2                , 22  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PURGE_ABORT_LVL_ERR2 );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_PURGE_DONE_LVL_ERR1                 , 23  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PURGE_DONE_LVL_ERR1 );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_IMA_FSM_TIMEOUT                     , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_IMA_FSM_TIMEOUT );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_PPE_WR_FSM_TIMEOUT                  , 25  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PPE_WR_FSM_TIMEOUT );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_PPE_RD_FSM_TIMEOUT                  , 26  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_PPE_RD_FSM_TIMEOUT );
+REG64_FLD( EX_ERR_RPT_REG_FIR0_TLB_DATA_PAR                        , 27  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR0_TLB_DATA_PAR );
+REG64_FLD( EX_ERR_RPT_REG_FIR19_LD_TGT_NODAL_DINC                  , 28  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR19_LD_TGT_NODAL_DINC );
+REG64_FLD( EX_ERR_RPT_REG_FIR19_ST_TGT_NODAL_DINC                  , 29  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FIR19_ST_TGT_NODAL_DINC );
+
+REG64_FLD( EQ_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK   , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK );
+REG64_FLD( EQ_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK             , 17  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_THERM_MODEREG_PARITY_MASK );
+REG64_FLD( EQ_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK           , 18  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SKITTER_MODEREG_PARITY_MASK );
+REG64_FLD( EQ_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK          , 19  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SKITTER_FORCEREG_PARITY_MASK );
+REG64_FLD( EQ_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK         , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SCAN_INIT_VERSION_PARITY_MASK );
+REG64_FLD( EQ_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK              , 21  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VOLT_MODEREG_PARITY_MASK );
+REG64_FLD( EQ_ERR_STATUS_REG_COUNT_STATE_MASK                      , 23  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_STATE_MASK );
+REG64_FLD( EQ_ERR_STATUS_REG_RUN_STATE_MASK                        , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUN_STATE_MASK );
+REG64_FLD( EQ_ERR_STATUS_REG_THRES_STATE_MASK                      , 25  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_THRES_STATE_MASK );
+REG64_FLD( EQ_ERR_STATUS_REG_OVERFLOW_MASK                         , 26  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_OVERFLOW_MASK );
+REG64_FLD( EQ_ERR_STATUS_REG_SHIFTER_PARITY_MASK                   , 27  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SHIFTER_PARITY_MASK );
+REG64_FLD( EQ_ERR_STATUS_REG_SHIFTER_VALID_MASK                    , 28  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SHIFTER_VALID_MASK );
+REG64_FLD( EQ_ERR_STATUS_REG_TIMEOUT_MASK                          , 29  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMEOUT_MASK );
+REG64_FLD( EQ_ERR_STATUS_REG_F_SKITTER_READ_MASK                   , 30  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_F_SKITTER_READ_MASK );
+REG64_FLD( EQ_ERR_STATUS_REG_PCB_MASK                              , 31  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCB_MASK   );
+
+REG64_FLD( EX_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK   , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK );
+REG64_FLD( EX_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK             , 17  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_THERM_MODEREG_PARITY_MASK );
+REG64_FLD( EX_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK           , 18  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SKITTER_MODEREG_PARITY_MASK );
+REG64_FLD( EX_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK          , 19  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SKITTER_FORCEREG_PARITY_MASK );
+REG64_FLD( EX_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK         , 20  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SCAN_INIT_VERSION_PARITY_MASK );
+REG64_FLD( EX_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK              , 21  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VOLT_MODEREG_PARITY_MASK );
+REG64_FLD( EX_ERR_STATUS_REG_COUNT_STATE_MASK                      , 23  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_STATE_MASK );
+REG64_FLD( EX_ERR_STATUS_REG_RUN_STATE_MASK                        , 24  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUN_STATE_MASK );
+REG64_FLD( EX_ERR_STATUS_REG_THRES_STATE_MASK                      , 25  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_THRES_STATE_MASK );
+REG64_FLD( EX_ERR_STATUS_REG_OVERFLOW_MASK                         , 26  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_OVERFLOW_MASK );
+REG64_FLD( EX_ERR_STATUS_REG_SHIFTER_PARITY_MASK                   , 27  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SHIFTER_PARITY_MASK );
+REG64_FLD( EX_ERR_STATUS_REG_SHIFTER_VALID_MASK                    , 28  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SHIFTER_VALID_MASK );
+REG64_FLD( EX_ERR_STATUS_REG_TIMEOUT_MASK                          , 29  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMEOUT_MASK );
+REG64_FLD( EX_ERR_STATUS_REG_F_SKITTER_READ_MASK                   , 30  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_F_SKITTER_READ_MASK );
+REG64_FLD( EX_ERR_STATUS_REG_PCB_MASK                              , 31  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCB_MASK   );
+
+REG64_FLD( C_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK    , 16  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK );
+REG64_FLD( C_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK              , 17  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_THERM_MODEREG_PARITY_MASK );
+REG64_FLD( C_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK            , 18  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_SKITTER_MODEREG_PARITY_MASK );
+REG64_FLD( C_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK           , 19  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_SKITTER_FORCEREG_PARITY_MASK );
+REG64_FLD( C_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK          , 20  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_SCAN_INIT_VERSION_PARITY_MASK );
+REG64_FLD( C_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK               , 21  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_VOLT_MODEREG_PARITY_MASK );
+REG64_FLD( C_ERR_STATUS_REG_COUNT_STATE_MASK                       , 23  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_COUNT_STATE_MASK );
+REG64_FLD( C_ERR_STATUS_REG_RUN_STATE_MASK                         , 24  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUN_STATE_MASK );
+REG64_FLD( C_ERR_STATUS_REG_THRES_STATE_MASK                       , 25  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_THRES_STATE_MASK );
+REG64_FLD( C_ERR_STATUS_REG_OVERFLOW_MASK                          , 26  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_OVERFLOW_MASK );
+REG64_FLD( C_ERR_STATUS_REG_SHIFTER_PARITY_MASK                    , 27  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_SHIFTER_PARITY_MASK );
+REG64_FLD( C_ERR_STATUS_REG_SHIFTER_VALID_MASK                     , 28  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_SHIFTER_VALID_MASK );
+REG64_FLD( C_ERR_STATUS_REG_TIMEOUT_MASK                           , 29  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMEOUT_MASK );
+REG64_FLD( C_ERR_STATUS_REG_F_SKITTER_READ_MASK                    , 30  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_F_SKITTER_READ_MASK );
+REG64_FLD( C_ERR_STATUS_REG_PCB_MASK                               , 31  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_PCB_MASK   );
+
+REG64_FLD( EQ_FIR_ACTION0_REG_ACTION0                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( EQ_FIR_ACTION0_REG_ACTION0_LEN                          , 31  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( EX_FIR_ACTION0_REG_ACTION0                              , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( EX_FIR_ACTION0_REG_ACTION0_LEN                          , 31  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( EX_L2_FIR_ACTION0_REG_ACTION0                           , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( EX_L2_FIR_ACTION0_REG_ACTION0_LEN                       , 42  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( EX_L3_FIR_ACTION0_REG_ACTION0                           , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( EX_L3_FIR_ACTION0_REG_ACTION0_LEN                       , 31  , SH_UNT_EX_L3    , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( EQ_FIR_ACTION1_REG_ACTION1                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( EQ_FIR_ACTION1_REG_ACTION1_LEN                          , 31  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( EX_FIR_ACTION1_REG_ACTION1                              , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( EX_FIR_ACTION1_REG_ACTION1_LEN                          , 31  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( EX_L2_FIR_ACTION1_REG_ACTION1                           , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( EX_L2_FIR_ACTION1_REG_ACTION1_LEN                       , 42  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( EX_L3_FIR_ACTION1_REG_ACTION1                           , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( EX_L3_FIR_ACTION1_REG_ACTION1_LEN                       , 31  , SH_UNT_EX_L3    , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( EX_L2_FIR_ERR_INJ_TO_LSU                                , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_TO_LSU     );
+REG64_FLD( EX_L2_FIR_ERR_INJ_TO_IFU                                , 1   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_TO_IFU     );
+REG64_FLD( EX_L2_FIR_ERR_INJ_TO_ISU                                , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_TO_ISU     );
+REG64_FLD( EX_L2_FIR_ERR_INJ_TO_VSU                                , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_TO_VSU     );
+REG64_FLD( EX_L2_FIR_ERR_INJ_TO_PC                                 , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_TO_PC      );
+REG64_FLD( EX_L2_FIR_ERR_INJ_ERROR_PULSE_OR_LEVEL                  , 6   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_PULSE_OR_LEVEL );
+REG64_FLD( EX_L2_FIR_ERR_INJ_CLEAR_STICKY_LEVEL                    , 7   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_CLEAR_STICKY_LEVEL );
+REG64_FLD( EX_L2_FIR_ERR_INJ_SCOM_WRITE                            , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_SCOM_WRITE );
+REG64_FLD( EX_L2_FIR_ERR_INJ_TRIGGER                               , 9   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRIGGER    );
+REG64_FLD( EX_L2_FIR_ERR_INJ_TRIGGER1                              , 10  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRIGGER1   );
+REG64_FLD( EX_L2_FIR_ERR_INJ_TOD_TAP                               , 11  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_TOD_TAP    );
+REG64_FLD( EX_L2_FIR_ERR_INJ_BLOCK                                 , 12  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCK      );
+REG64_FLD( EX_L2_FIR_ERR_INJ_BLOCK_LEN                             , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCK_LEN  );
+REG64_FLD( EX_L2_FIR_ERR_INJ_DELAY_AFTER_BLOCK                     , 14  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_DELAY_AFTER_BLOCK );
+REG64_FLD( EX_L2_FIR_ERR_INJ_RECOVERY_BLK                          , 15  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_RECOVERY_BLK );
+REG64_FLD( EX_L2_FIR_ERR_INJ_RECOVERY_BLK_EXTEND                   , 16  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_RECOVERY_BLK_EXTEND );
+REG64_FLD( EX_L2_FIR_ERR_INJ_TAP_SEL                               , 17  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_TAP_SEL    );
+REG64_FLD( EX_L2_FIR_ERR_INJ_TAP_SEL_LEN                           , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_TAP_SEL_LEN );
+REG64_FLD( EX_L2_FIR_ERR_INJ_HYP_BLOCK                             , 21  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_BLOCK  );
+REG64_FLD( EX_L2_FIR_ERR_INJ_HYP_BLOCK_LEN                         , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_BLOCK_LEN );
+
+REG64_FLD( C_FIR_ERR_INJ_TO_LSU                                    , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_TO_LSU     );
+REG64_FLD( C_FIR_ERR_INJ_TO_IFU                                    , 1   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_TO_IFU     );
+REG64_FLD( C_FIR_ERR_INJ_TO_ISU                                    , 2   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_TO_ISU     );
+REG64_FLD( C_FIR_ERR_INJ_TO_VSU                                    , 3   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_TO_VSU     );
+REG64_FLD( C_FIR_ERR_INJ_TO_PC                                     , 4   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_TO_PC      );
+REG64_FLD( C_FIR_ERR_INJ_ERROR_PULSE_OR_LEVEL                      , 6   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_ERROR_PULSE_OR_LEVEL );
+REG64_FLD( C_FIR_ERR_INJ_CLEAR_STICKY_LEVEL                        , 7   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_CLEAR_STICKY_LEVEL );
+REG64_FLD( C_FIR_ERR_INJ_SCOM_WRITE                                , 8   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_SCOM_WRITE );
+REG64_FLD( C_FIR_ERR_INJ_TRIGGER                                   , 9   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRIGGER    );
+REG64_FLD( C_FIR_ERR_INJ_TRIGGER1                                  , 10  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_TRIGGER1   );
+REG64_FLD( C_FIR_ERR_INJ_TOD_TAP                                   , 11  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_TOD_TAP    );
+REG64_FLD( C_FIR_ERR_INJ_BLOCK                                     , 12  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCK      );
+REG64_FLD( C_FIR_ERR_INJ_BLOCK_LEN                                 , 2   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_BLOCK_LEN  );
+REG64_FLD( C_FIR_ERR_INJ_DELAY_AFTER_BLOCK                         , 14  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_DELAY_AFTER_BLOCK );
+REG64_FLD( C_FIR_ERR_INJ_RECOVERY_BLK                              , 15  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RECOVERY_BLK );
+REG64_FLD( C_FIR_ERR_INJ_RECOVERY_BLK_EXTEND                       , 16  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RECOVERY_BLK_EXTEND );
+REG64_FLD( C_FIR_ERR_INJ_TAP_SEL                                   , 17  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_TAP_SEL    );
+REG64_FLD( C_FIR_ERR_INJ_TAP_SEL_LEN                               , 4   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_TAP_SEL_LEN );
+REG64_FLD( C_FIR_ERR_INJ_HYP_BLOCK                                 , 21  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_BLOCK  );
+REG64_FLD( C_FIR_ERR_INJ_HYP_BLOCK_LEN                             , 3   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_BLOCK_LEN );
+
+REG64_FLD( EQ_FIR_MASK_IN0                                         , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( EQ_FIR_MASK_IN1                                         , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN1        );
+REG64_FLD( EQ_FIR_MASK_IN2                                         , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN2        );
+REG64_FLD( EQ_FIR_MASK_IN3                                         , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN3        );
+REG64_FLD( EQ_FIR_MASK_IN4                                         , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( EQ_FIR_MASK_IN5                                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( EQ_FIR_MASK_IN5_LEN                                     , 21  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN5_LEN    );
+REG64_FLD( EQ_FIR_MASK_IN26                                        , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN26       );
+
+REG64_FLD( EX_FIR_MASK_IN0                                         , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( EX_FIR_MASK_IN1                                         , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN1        );
+REG64_FLD( EX_FIR_MASK_IN2                                         , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN2        );
+REG64_FLD( EX_FIR_MASK_IN3                                         , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN3        );
+REG64_FLD( EX_FIR_MASK_IN4                                         , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( EX_FIR_MASK_IN5                                         , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( EX_FIR_MASK_IN5_LEN                                     , 21  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN5_LEN    );
+REG64_FLD( EX_FIR_MASK_IN26                                        , 26  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN26       );
+
+REG64_FLD( C_FIR_MASK_IN0                                          , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( C_FIR_MASK_IN1                                          , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN1        );
+REG64_FLD( C_FIR_MASK_IN2                                          , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN2        );
+REG64_FLD( C_FIR_MASK_IN3                                          , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN3        );
+REG64_FLD( C_FIR_MASK_IN4                                          , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( C_FIR_MASK_IN5                                          , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( C_FIR_MASK_IN5_LEN                                      , 21  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN5_LEN    );
+REG64_FLD( C_FIR_MASK_IN26                                         , 26  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN26       );
+
+REG64_FLD( EQ_FIR_MASK_REG_MASK                                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASK       );
+REG64_FLD( EQ_FIR_MASK_REG_MASK_LEN                                , 31  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( EX_FIR_MASK_REG_MASK                                    , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASK       );
+REG64_FLD( EX_FIR_MASK_REG_MASK_LEN                                , 31  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_MASK_LEN   );
+
+REG64_FLD( EX_L2_FIR_MASK_REG_L2                                   , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2         );
+REG64_FLD( EX_L2_FIR_MASK_REG_L2_LEN                               , 42  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_LEN     );
+
+REG64_FLD( EQ_FIR_REG_CONTROL_ERR                                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CONTROL_ERR );
+REG64_FLD( EQ_FIR_REG_TLBIE_CONTROL_ERR                            , 1   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBIE_CONTROL_ERR );
+REG64_FLD( EQ_FIR_REG_TLBIE_SLBIEG_SW_ERR                          , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBIE_SLBIEG_SW_ERR );
+REG64_FLD( EQ_FIR_REG_ST_ADDR_ERR                                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ST_ADDR_ERR );
+REG64_FLD( EQ_FIR_REG_LD_ADDR_ERR                                  , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_LD_ADDR_ERR );
+REG64_FLD( EQ_FIR_REG_ST_ACK_DEAD                                  , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ST_ACK_DEAD );
+REG64_FLD( EQ_FIR_REG_LD_ACK_DEAD                                  , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_LD_ACK_DEAD );
+REG64_FLD( EQ_FIR_REG_MSG_ADDR_ERR                                 , 7   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_MSG_ADDR_ERR );
+REG64_FLD( EQ_FIR_REG_STQ_DATA_PARITY_ERR                          , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_STQ_DATA_PARITY_ERR );
+REG64_FLD( EQ_FIR_REG_STORE_TIMEOUT                                , 9   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_STORE_TIMEOUT );
+REG64_FLD( EQ_FIR_REG_TLBIE_MASTER_TIMEOUT                         , 10  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBIE_MASTER_TIMEOUT );
+REG64_FLD( EQ_FIR_REG_TLBIE_SNOOP_TIMEOUT                          , 11  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBIE_SNOOP_TIMEOUT );
+REG64_FLD( EQ_FIR_REG_IMA_CRESP_ADDR_ERR                           , 12  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IMA_CRESP_ADDR_ERR );
+REG64_FLD( EQ_FIR_REG_IMA_ACK_DEAD                                 , 13  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IMA_ACK_DEAD );
+REG64_FLD( EQ_FIR_REG_PMISC_CRESP_ADDR_ERR                         , 14  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMISC_CRESP_ADDR_ERR );
+REG64_FLD( EQ_FIR_REG_PPE_RD_CRESP_ADDR_ERR                        , 15  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_RD_CRESP_ADDR_ERR );
+REG64_FLD( EQ_FIR_REG_PPE_WR_CRESP_ADDR_ERR                        , 16  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_WR_CRESP_ADDR_ERR );
+REG64_FLD( EQ_FIR_REG_PPE_RD_ACK_DEAD                              , 17  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_RD_ACK_DEAD );
+REG64_FLD( EQ_FIR_REG_PPE_WR_ACK_DEAD                              , 18  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_WR_ACK_DEAD );
+REG64_FLD( EQ_FIR_REG_TGT_NODAL_DINC_ERR                           , 19  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TGT_NODAL_DINC_ERR );
+REG64_FLD( EQ_FIR_REG_DARN_EN_ERR                                  , 20  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_DARN_EN_ERR );
+REG64_FLD( EQ_FIR_REG_DARN_ADDR_ERR                                , 21  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_DARN_ADDR_ERR );
+REG64_FLD( EQ_FIR_REG_SPARE                                        , 22  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE      );
+REG64_FLD( EQ_FIR_REG_SPARE_LEN                                    , 7   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( EQ_FIR_REG_SCOM_ERR1                                    , 29  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR1  );
+REG64_FLD( EQ_FIR_REG_SCOM_ERR2                                    , 30  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR2  );
+
+REG64_FLD( EX_FIR_REG_CONTROL_ERR                                  , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CONTROL_ERR );
+REG64_FLD( EX_FIR_REG_TLBIE_CONTROL_ERR                            , 1   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBIE_CONTROL_ERR );
+REG64_FLD( EX_FIR_REG_TLBIE_SLBIEG_SW_ERR                          , 2   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBIE_SLBIEG_SW_ERR );
+REG64_FLD( EX_FIR_REG_ST_ADDR_ERR                                  , 3   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ST_ADDR_ERR );
+REG64_FLD( EX_FIR_REG_LD_ADDR_ERR                                  , 4   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_LD_ADDR_ERR );
+REG64_FLD( EX_FIR_REG_ST_ACK_DEAD                                  , 5   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ST_ACK_DEAD );
+REG64_FLD( EX_FIR_REG_LD_ACK_DEAD                                  , 6   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_LD_ACK_DEAD );
+REG64_FLD( EX_FIR_REG_MSG_ADDR_ERR                                 , 7   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_MSG_ADDR_ERR );
+REG64_FLD( EX_FIR_REG_STQ_DATA_PARITY_ERR                          , 8   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_STQ_DATA_PARITY_ERR );
+REG64_FLD( EX_FIR_REG_STORE_TIMEOUT                                , 9   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_STORE_TIMEOUT );
+REG64_FLD( EX_FIR_REG_TLBIE_MASTER_TIMEOUT                         , 10  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBIE_MASTER_TIMEOUT );
+REG64_FLD( EX_FIR_REG_TLBIE_SNOOP_TIMEOUT                          , 11  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TLBIE_SNOOP_TIMEOUT );
+REG64_FLD( EX_FIR_REG_IMA_CRESP_ADDR_ERR                           , 12  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IMA_CRESP_ADDR_ERR );
+REG64_FLD( EX_FIR_REG_IMA_ACK_DEAD                                 , 13  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IMA_ACK_DEAD );
+REG64_FLD( EX_FIR_REG_PMISC_CRESP_ADDR_ERR                         , 14  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PMISC_CRESP_ADDR_ERR );
+REG64_FLD( EX_FIR_REG_PPE_RD_CRESP_ADDR_ERR                        , 15  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_RD_CRESP_ADDR_ERR );
+REG64_FLD( EX_FIR_REG_PPE_WR_CRESP_ADDR_ERR                        , 16  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_WR_CRESP_ADDR_ERR );
+REG64_FLD( EX_FIR_REG_PPE_RD_ACK_DEAD                              , 17  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_RD_ACK_DEAD );
+REG64_FLD( EX_FIR_REG_PPE_WR_ACK_DEAD                              , 18  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PPE_WR_ACK_DEAD );
+REG64_FLD( EX_FIR_REG_TGT_NODAL_DINC_ERR                           , 19  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TGT_NODAL_DINC_ERR );
+REG64_FLD( EX_FIR_REG_DARN_EN_ERR                                  , 20  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_DARN_EN_ERR );
+REG64_FLD( EX_FIR_REG_DARN_ADDR_ERR                                , 21  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_DARN_ADDR_ERR );
+REG64_FLD( EX_FIR_REG_SPARE                                        , 22  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE      );
+REG64_FLD( EX_FIR_REG_SPARE_LEN                                    , 7   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_LEN  );
+REG64_FLD( EX_FIR_REG_SCOM_ERR1                                    , 29  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR1  );
+REG64_FLD( EX_FIR_REG_SCOM_ERR2                                    , 30  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR2  );
+
+REG64_FLD( EX_L2_FIR_REG_CACHE_RD_CE                               , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_CACHE_RD_CE );
+REG64_FLD( EX_L2_FIR_REG_CACHE_RD_UE                               , 1   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_CACHE_RD_UE );
+REG64_FLD( EX_L2_FIR_REG_CACHE_RD_SUE                              , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_CACHE_RD_SUE );
+REG64_FLD( EX_L2_FIR_REG_HW_DIR_INTIATED_LINE_DELETE_OCCURRED      , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_HW_DIR_INTIATED_LINE_DELETE_OCCURRED );
+REG64_FLD( EX_L2_FIR_REG_CACHE_UE_SUE_DETECTED_ON_MODIFIED_LINE_BY_CO , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_CACHE_UE_SUE_DETECTED_ON_MODIFIED_LINE_BY_CO );
+REG64_FLD( EX_L2_FIR_REG_CACHE_UE_SUE_DETECTED_ON_NON_MODIFIED_LINE_BY_CO , 5   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_CACHE_UE_SUE_DETECTED_ON_NON_MODIFIED_LINE_BY_CO );
+REG64_FLD( EX_L2_FIR_REG_DIR_CE_DETECTED                           , 6   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIR_CE_DETECTED );
+REG64_FLD( EX_L2_FIR_REG_DIR_UE_DETECTED                           , 7   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIR_UE_DETECTED );
+REG64_FLD( EX_L2_FIR_REG_DIR_STUCK_BIT_CE                          , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIR_STUCK_BIT_CE );
+REG64_FLD( EX_L2_FIR_REG_DIR_SBCE_REPAIR_FAILED                    , 9   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_DIR_SBCE_REPAIR_FAILED );
+REG64_FLD( EX_L2_FIR_REG_MULTIPLE_DIR_ERRORS_DETECTED              , 10  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_MULTIPLE_DIR_ERRORS_DETECTED );
+REG64_FLD( EX_L2_FIR_REG_LRU_READ_ERROR_DETECTED                   , 11  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_LRU_READ_ERROR_DETECTED );
+REG64_FLD( EX_L2_FIR_REG_RC_POWERBUS_DATA_TIMEOUT                  , 12  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_RC_POWERBUS_DATA_TIMEOUT );
+REG64_FLD( EX_L2_FIR_REG_NCU_POWERBUS_DATA_TIMEOUT                 , 13  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_NCU_POWERBUS_DATA_TIMEOUT );
+REG64_FLD( EX_L2_FIR_REG_HW_CONTROL_ERROR                          , 14  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_HW_CONTROL_ERROR );
+REG64_FLD( EX_L2_FIR_REG_LRU_ALL_MEMBERS_IN_CGC_ARE_LINE_DELETED   , 15  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_LRU_ALL_MEMBERS_IN_CGC_ARE_LINE_DELETED );
+REG64_FLD( EX_L2_FIR_REG_CACHE_INHIBITED_HIT_CACHEABLE_ERROR       , 16  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_CACHE_INHIBITED_HIT_CACHEABLE_ERROR );
+REG64_FLD( EX_L2_FIR_REG_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR         , 17  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR );
+REG64_FLD( EX_L2_FIR_REG_RC_STORE_RECEIVED_PB_CRESP_ADR_ERR        , 18  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_RC_STORE_RECEIVED_PB_CRESP_ADR_ERR );
+REG64_FLD( EX_L2_FIR_REG_RC_POWBUS_DATA_CE_ERR_FROM_F2CHK          , 19  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_RC_POWBUS_DATA_CE_ERR_FROM_F2CHK );
+REG64_FLD( EX_L2_FIR_REG_RC_POWBUS_DATA_UE_ERR_FROM_F2CHK          , 20  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_RC_POWBUS_DATA_UE_ERR_FROM_F2CHK );
+REG64_FLD( EX_L2_FIR_REG_RC_POWBUS_DATA_SUE_ERR_FROM_F2CHK         , 21  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_RC_POWBUS_DATA_SUE_ERR_FROM_F2CHK );
+REG64_FLD( EX_L2_FIR_REG_TGT_NODAL_REQ_DINC_ERR                    , 22  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_TGT_NODAL_REQ_DINC_ERR );
+REG64_FLD( EX_L2_FIR_REG_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR_FOR_HYP , 23  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR_FOR_HYP );
+REG64_FLD( EX_L2_FIR_REG_RCDAT_RD_PARITY_ERR                       , 24  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_RCDAT_RD_PARITY_ERR );
+REG64_FLD( EX_L2_FIR_REG_CO_PSH_RECEIVED_PB_CRESP_ADR_ERR          , 25  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_CO_PSH_RECEIVED_PB_CRESP_ADR_ERR );
+REG64_FLD( EX_L2_FIR_REG_LVDIR_PERR                                , 26  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_LVDIR_PERR );
+REG64_FLD( EX_L2_FIR_REG_RC_LOAD_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV , 27  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_RC_LOAD_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV );
+REG64_FLD( EX_L2_FIR_REG_DARN_DATA_TIMEOUT                         , 28  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_DARN_DATA_TIMEOUT );
+REG64_FLD( EX_L2_FIR_REG_RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV , 29  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV );
+REG64_FLD( EX_L2_FIR_REG_CACHE_RD_CE_AND_UE                        , 36  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_CACHE_RD_CE_AND_UE );
+REG64_FLD( EX_L2_FIR_REG_SCOM_ERR1                                 , 40  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR1  );
+REG64_FLD( EX_L2_FIR_REG_SCOM_ERR2                                 , 41  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR2  );
+
+REG64_FLD( EX_L3_FIR_REG_L3_SPARE0                                 , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_SPARE0  );
+REG64_FLD( EX_L3_FIR_REG_L3_SPARE1                                 , 1   , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_SPARE1  );
+REG64_FLD( EX_L3_FIR_REG_L3_SPARE2                                 , 2   , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_SPARE2  );
+REG64_FLD( EX_L3_FIR_REG_L3_DRAM_POS_WORDLINE_FAIL                 , 3   , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_DRAM_POS_WORDLINE_FAIL );
+REG64_FLD( EX_L3_FIR_REG_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ           , 4   , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ );
+REG64_FLD( EX_L3_FIR_REG_L3_CAC_RD_UE_DET                          , 5   , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_CAC_RD_UE_DET );
+REG64_FLD( EX_L3_FIR_REG_L3_CAC_RD_SUE_DET                         , 6   , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_CAC_RD_SUE_DET );
+REG64_FLD( EX_L3_FIR_REG_L3_CAC_WR_DATA_CE_FROM_PB                 , 7   , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_CAC_WR_DATA_CE_FROM_PB );
+REG64_FLD( EX_L3_FIR_REG_L3_CAC_WR_DATA_UE_FROM_PB                 , 8   , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_CAC_WR_DATA_UE_FROM_PB );
+REG64_FLD( EX_L3_FIR_REG_L3_CAC_WR_DATA_SUE_FROM_PB                , 9   , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_CAC_WR_DATA_SUE_FROM_PB );
+REG64_FLD( EX_L3_FIR_REG_L3_CAC_WR_DATA_CE_FROM_L2                 , 10  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_CAC_WR_DATA_CE_FROM_L2 );
+REG64_FLD( EX_L3_FIR_REG_L3_CAC_WR_DATA_UE_FROM_L2                 , 11  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_CAC_WR_DATA_UE_FROM_L2 );
+REG64_FLD( EX_L3_FIR_REG_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC       , 12  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC );
+REG64_FLD( EX_L3_FIR_REG_L3_DIR_RD_CE_DET                          , 13  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_DIR_RD_CE_DET );
+REG64_FLD( EX_L3_FIR_REG_L3_DIR_RD_UE_DET                          , 14  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_DIR_RD_UE_DET );
+REG64_FLD( EX_L3_FIR_REG_L3_DIR_RD_PHANTOM_ERROR                   , 15  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_DIR_RD_PHANTOM_ERROR );
+REG64_FLD( EX_L3_FIR_REG_L3_PB_MAST_WR_ADDR_ERR                    , 16  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_PB_MAST_WR_ADDR_ERR );
+REG64_FLD( EX_L3_FIR_REG_L3_PB_MAST_RD_ADDR_ERR                    , 17  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_PB_MAST_RD_ADDR_ERR );
+REG64_FLD( EX_L3_FIR_REG_L3_ADDR_HANG_DETECTED                     , 18  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_ADDR_HANG_DETECTED );
+REG64_FLD( EX_L3_FIR_REG_L3_LRU_INVAL_CNT                          , 19  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_LRU_INVAL_CNT );
+REG64_FLD( EX_L3_FIR_REG_L3_PPE_RD_CE_DET                          , 20  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_PPE_RD_CE_DET );
+REG64_FLD( EX_L3_FIR_REG_L3_PPE_RD_UE_DET                          , 21  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_PPE_RD_UE_DET );
+REG64_FLD( EX_L3_FIR_REG_L3_PPE_RD_SUE_DET                         , 22  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_PPE_RD_SUE_DET );
+REG64_FLD( EX_L3_FIR_REG_L3_MACH_HANG_DETECTED                     , 23  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_MACH_HANG_DETECTED );
+REG64_FLD( EX_L3_FIR_REG_L3_HW_CONTROL_ERR                         , 24  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_HW_CONTROL_ERR );
+REG64_FLD( EX_L3_FIR_REG_L3_SNP_CACHE_INHIBIT_ERR                  , 25  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_SNP_CACHE_INHIBIT_ERR );
+REG64_FLD( EX_L3_FIR_REG_L3_LINE_DEL_CE_DONE                       , 26  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_LINE_DEL_CE_DONE );
+REG64_FLD( EX_L3_FIR_REG_L3_DRAM_ERROR                             , 27  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_DRAM_ERROR );
+REG64_FLD( EX_L3_FIR_REG_L3_LRU_ERROR                              , 28  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_LRU_ERROR );
+REG64_FLD( EX_L3_FIR_REG_L3_ALL_MEMBERS_DELETED_ERROR              , 29  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_ALL_MEMBERS_DELETED_ERROR );
+REG64_FLD( EX_L3_FIR_REG_L3_REFRESH_TIMER_ERROR                    , 30  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_REFRESH_TIMER_ERROR );
+REG64_FLD( EX_L3_FIR_REG_L3_PB_MAST_WR_ACK_DEAD                    , 31  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_PB_MAST_WR_ACK_DEAD );
+REG64_FLD( EX_L3_FIR_REG_L3_PB_MAST_RD_ACK_DEAD                    , 32  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_PB_MAST_RD_ACK_DEAD );
+REG64_FLD( EX_L3_FIR_REG_SCOM_ERR1                                 , 33  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR1  );
+REG64_FLD( EX_L3_FIR_REG_SCOM_ERR2                                 , 34  , SH_UNT_EX_L3    , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR2  );
+
+REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0                     , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN0 );
+REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1                     , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN1 );
+REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2                     , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN2 );
+REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3                     , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN3 );
+REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4                     , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN4 );
+REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5                     , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN5 );
+REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6                     , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN6 );
+REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7                     , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN7 );
+REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8                     , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN8 );
+REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9                     , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN9 );
+REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10                    , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN10 );
+REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11                    , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN11 );
+
+REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0                     , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN0 );
+REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1                     , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN1 );
+REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2                     , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN2 );
+REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3                     , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN3 );
+REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4                     , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN4 );
+REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5                     , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN5 );
+REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6                     , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN6 );
+REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7                     , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN7 );
+REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8                     , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN8 );
+REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9                     , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN9 );
+REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10                    , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN10 );
+REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11                    , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN11 );
+
+REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0                      , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN0 );
+REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1                      , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN1 );
+REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2                      , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN2 );
+REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3                      , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN3 );
+REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4                      , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN4 );
+REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5                      , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN5 );
+REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6                      , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN6 );
+REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7                      , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN7 );
+REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8                      , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN8 );
+REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9                      , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN9 );
+REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10                     , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN10 );
+REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11                     , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP0_TRIG_IN11 );
+
+REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0                     , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN0 );
+REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1                     , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN1 );
+REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2                     , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN2 );
+REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3                     , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN3 );
+REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4                     , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN4 );
+REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5                     , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN5 );
+REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6                     , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN6 );
+REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7                     , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN7 );
+REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8                     , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN8 );
+REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9                     , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN9 );
+REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10                    , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN10 );
+REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11                    , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN11 );
+
+REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0                     , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN0 );
+REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1                     , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN1 );
+REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2                     , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN2 );
+REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3                     , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN3 );
+REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4                     , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN4 );
+REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5                     , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN5 );
+REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6                     , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN6 );
+REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7                     , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN7 );
+REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8                     , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN8 );
+REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9                     , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN9 );
+REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10                    , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN10 );
+REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11                    , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN11 );
+
+REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0                      , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN0 );
+REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1                      , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN1 );
+REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2                      , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN2 );
+REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3                      , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN3 );
+REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4                      , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN4 );
+REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5                      , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN5 );
+REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6                      , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN6 );
+REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7                      , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN7 );
+REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8                      , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN8 );
+REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9                      , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN9 );
+REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10                     , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN10 );
+REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11                     , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP1_TRIG_IN11 );
+
+REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0                     , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN0 );
+REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1                     , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN1 );
+REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2                     , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN2 );
+REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3                     , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN3 );
+REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4                     , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN4 );
+REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5                     , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN5 );
+REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6                     , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN6 );
+REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7                     , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN7 );
+REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8                     , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN8 );
+REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9                     , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN9 );
+REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10                    , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN10 );
+REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11                    , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN11 );
+
+REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0                     , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN0 );
+REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1                     , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN1 );
+REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2                     , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN2 );
+REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3                     , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN3 );
+REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4                     , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN4 );
+REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5                     , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN5 );
+REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6                     , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN6 );
+REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7                     , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN7 );
+REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8                     , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN8 );
+REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9                     , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN9 );
+REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10                    , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN10 );
+REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11                    , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN11 );
+
+REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0                      , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN0 );
+REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1                      , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN1 );
+REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2                      , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN2 );
+REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3                      , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN3 );
+REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4                      , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN4 );
+REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5                      , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN5 );
+REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6                      , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN6 );
+REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7                      , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN7 );
+REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8                      , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN8 );
+REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9                      , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN9 );
+REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10                     , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN10 );
+REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11                     , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP2_TRIG_IN11 );
+
+REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN0                            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN0  );
+REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN1                            , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN1  );
+REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN2                            , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN2  );
+REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN3                            , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN3  );
+REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN4                            , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN4  );
+REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN5                            , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN5  );
+REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN6                            , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN6  );
+REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN7                            , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN7  );
+REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN8                            , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN8  );
+REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN9                            , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN9  );
+REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN10                           , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN10 );
+REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN11                           , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN11 );
+
+REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN0                            , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN0  );
+REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN1                            , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN1  );
+REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN2                            , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN2  );
+REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN3                            , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN3  );
+REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN4                            , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN4  );
+REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN5                            , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN5  );
+REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN6                            , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN6  );
+REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN7                            , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN7  );
+REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN8                            , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN8  );
+REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN9                            , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN9  );
+REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN10                           , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN10 );
+REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN11                           , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN11 );
+
+REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN0                             , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN0  );
+REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN1                             , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN1  );
+REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN2                             , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN2  );
+REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN3                             , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN3  );
+REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN4                             , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN4  );
+REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN5                             , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN5  );
+REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN6                             , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN6  );
+REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN7                             , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN7  );
+REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN8                             , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN8  );
+REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN9                             , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN9  );
+REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN10                            , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN10 );
+REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN11                            , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GXSTP_IN11 );
+
+REG64_FLD( EX_L2_HANG_CONTROL_CORE_LIMIT                           , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_CORE_LIMIT );
+REG64_FLD( EX_L2_HANG_CONTROL_CORE_LIMIT_LEN                       , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_CORE_LIMIT_LEN );
+REG64_FLD( EX_L2_HANG_CONTROL_NEST_LIMIT                           , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_NEST_LIMIT );
+REG64_FLD( EX_L2_HANG_CONTROL_NEST_LIMIT_LEN                       , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_NEST_LIMIT_LEN );
+REG64_FLD( EX_L2_HANG_CONTROL_RETURN_GOOD_ON_COMP                  , 16  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_RETURN_GOOD_ON_COMP );
+REG64_FLD( EX_L2_HANG_CONTROL_COMP_CNT_LIMIT                       , 17  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_COMP_CNT_LIMIT );
+REG64_FLD( EX_L2_HANG_CONTROL_COMP_CNT_LIMIT_LEN                   , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_COMP_CNT_LIMIT_LEN );
+REG64_FLD( EX_L2_HANG_CONTROL_REC_LIMIT                            , 25  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_REC_LIMIT  );
+REG64_FLD( EX_L2_HANG_CONTROL_REC_LIMIT_LEN                        , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_REC_LIMIT_LEN );
+REG64_FLD( EX_L2_HANG_CONTROL_USE_REC_LIMIT                        , 28  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_USE_REC_LIMIT );
+REG64_FLD( EX_L2_HANG_CONTROL_ACTIVE_MASK                          , 29  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTIVE_MASK );
+REG64_FLD( EX_L2_HANG_CONTROL_ACTIVE_MASK_LEN                      , 5   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTIVE_MASK_LEN );
+
+REG64_FLD( C_HANG_CONTROL_CORE_LIMIT                               , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_CORE_LIMIT );
+REG64_FLD( C_HANG_CONTROL_CORE_LIMIT_LEN                           , 8   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_CORE_LIMIT_LEN );
+REG64_FLD( C_HANG_CONTROL_NEST_LIMIT                               , 8   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_NEST_LIMIT );
+REG64_FLD( C_HANG_CONTROL_NEST_LIMIT_LEN                           , 8   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_NEST_LIMIT_LEN );
+REG64_FLD( C_HANG_CONTROL_RETURN_GOOD_ON_COMP                      , 16  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RETURN_GOOD_ON_COMP );
+REG64_FLD( C_HANG_CONTROL_COMP_CNT_LIMIT                           , 17  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_COMP_CNT_LIMIT );
+REG64_FLD( C_HANG_CONTROL_COMP_CNT_LIMIT_LEN                       , 8   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_COMP_CNT_LIMIT_LEN );
+REG64_FLD( C_HANG_CONTROL_REC_LIMIT                                , 25  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_REC_LIMIT  );
+REG64_FLD( C_HANG_CONTROL_REC_LIMIT_LEN                            , 3   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_REC_LIMIT_LEN );
+REG64_FLD( C_HANG_CONTROL_USE_REC_LIMIT                            , 28  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_USE_REC_LIMIT );
+REG64_FLD( C_HANG_CONTROL_ACTIVE_MASK                              , 29  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTIVE_MASK );
+REG64_FLD( C_HANG_CONTROL_ACTIVE_MASK_LEN                          , 5   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTIVE_MASK_LEN );
+
+REG64_FLD( EQ_HANG_PULSE_0_REG_0                                   , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_0          );
+REG64_FLD( EQ_HANG_PULSE_0_REG_0_LEN                               , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_LEN      );
+REG64_FLD( EQ_HANG_PULSE_0_REG_SUPPRESS                            , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( EX_HANG_PULSE_0_REG_0                                   , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_0          );
+REG64_FLD( EX_HANG_PULSE_0_REG_0_LEN                               , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_LEN      );
+REG64_FLD( EX_HANG_PULSE_0_REG_SUPPRESS                            , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( C_HANG_PULSE_0_REG_0                                    , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_0          );
+REG64_FLD( C_HANG_PULSE_0_REG_0_LEN                                , 6   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_0_LEN      );
+REG64_FLD( C_HANG_PULSE_0_REG_SUPPRESS                             , 6   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( EQ_HANG_PULSE_1_REG_1                                   , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_1          );
+REG64_FLD( EQ_HANG_PULSE_1_REG_1_LEN                               , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_LEN      );
+REG64_FLD( EQ_HANG_PULSE_1_REG_SUPPRESS                            , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( EX_HANG_PULSE_1_REG_1                                   , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_1          );
+REG64_FLD( EX_HANG_PULSE_1_REG_1_LEN                               , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_LEN      );
+REG64_FLD( EX_HANG_PULSE_1_REG_SUPPRESS                            , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( C_HANG_PULSE_1_REG_1                                    , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_1          );
+REG64_FLD( C_HANG_PULSE_1_REG_1_LEN                                , 6   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_1_LEN      );
+REG64_FLD( C_HANG_PULSE_1_REG_SUPPRESS                             , 6   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( EQ_HANG_PULSE_2_REG_2                                   , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_2          );
+REG64_FLD( EQ_HANG_PULSE_2_REG_2_LEN                               , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_2_LEN      );
+REG64_FLD( EQ_HANG_PULSE_2_REG_SUPPRESS                            , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( EX_HANG_PULSE_2_REG_2                                   , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_2          );
+REG64_FLD( EX_HANG_PULSE_2_REG_2_LEN                               , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_2_LEN      );
+REG64_FLD( EX_HANG_PULSE_2_REG_SUPPRESS                            , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( C_HANG_PULSE_2_REG_2                                    , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_2          );
+REG64_FLD( C_HANG_PULSE_2_REG_2_LEN                                , 6   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_2_LEN      );
+REG64_FLD( C_HANG_PULSE_2_REG_SUPPRESS                             , 6   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( EQ_HANG_PULSE_3_REG_3                                   , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_3          );
+REG64_FLD( EQ_HANG_PULSE_3_REG_3_LEN                               , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_3_LEN      );
+REG64_FLD( EQ_HANG_PULSE_3_REG_SUPPRESS                            , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( EX_HANG_PULSE_3_REG_3                                   , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_3          );
+REG64_FLD( EX_HANG_PULSE_3_REG_3_LEN                               , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_3_LEN      );
+REG64_FLD( EX_HANG_PULSE_3_REG_SUPPRESS                            , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( C_HANG_PULSE_3_REG_3                                    , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_3          );
+REG64_FLD( C_HANG_PULSE_3_REG_3_LEN                                , 6   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_3_LEN      );
+REG64_FLD( C_HANG_PULSE_3_REG_SUPPRESS                             , 6   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( EQ_HANG_PULSE_4_REG_4                                   , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_4          );
+REG64_FLD( EQ_HANG_PULSE_4_REG_4_LEN                               , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LEN      );
+REG64_FLD( EQ_HANG_PULSE_4_REG_SUPPRESS                            , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( EX_HANG_PULSE_4_REG_4                                   , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_4          );
+REG64_FLD( EX_HANG_PULSE_4_REG_4_LEN                               , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LEN      );
+REG64_FLD( EX_HANG_PULSE_4_REG_SUPPRESS                            , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( C_HANG_PULSE_4_REG_4                                    , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_4          );
+REG64_FLD( C_HANG_PULSE_4_REG_4_LEN                                , 6   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_4_LEN      );
+REG64_FLD( C_HANG_PULSE_4_REG_SUPPRESS                             , 6   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( EQ_HANG_PULSE_5_REG_5                                   , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_5          );
+REG64_FLD( EQ_HANG_PULSE_5_REG_5_LEN                               , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_5_LEN      );
+REG64_FLD( EQ_HANG_PULSE_5_REG_SUPPRESS                            , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( EX_HANG_PULSE_5_REG_5                                   , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_5          );
+REG64_FLD( EX_HANG_PULSE_5_REG_5_LEN                               , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_5_LEN      );
+REG64_FLD( EX_HANG_PULSE_5_REG_SUPPRESS                            , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( C_HANG_PULSE_5_REG_5                                    , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_5          );
+REG64_FLD( C_HANG_PULSE_5_REG_5_LEN                                , 6   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_5_LEN      );
+REG64_FLD( C_HANG_PULSE_5_REG_SUPPRESS                             , 6   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( EQ_HANG_PULSE_6_REG_6                                   , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_6          );
+REG64_FLD( EQ_HANG_PULSE_6_REG_6_LEN                               , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_6_LEN      );
+REG64_FLD( EQ_HANG_PULSE_6_REG_SUPPRESS                            , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( EX_HANG_PULSE_6_REG_6                                   , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_6          );
+REG64_FLD( EX_HANG_PULSE_6_REG_6_LEN                               , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_6_LEN      );
+REG64_FLD( EX_HANG_PULSE_6_REG_SUPPRESS                            , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( C_HANG_PULSE_6_REG_6                                    , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_6          );
+REG64_FLD( C_HANG_PULSE_6_REG_6_LEN                                , 6   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_6_LEN      );
+REG64_FLD( C_HANG_PULSE_6_REG_SUPPRESS                             , 6   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_SUPPRESS   );
+
+REG64_FLD( EQ_HEARTBEAT_REG_DEAD                                   , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DEAD       );
+
+REG64_FLD( EX_HEARTBEAT_REG_DEAD                                   , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DEAD       );
+
+REG64_FLD( C_HEARTBEAT_REG_DEAD                                    , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DEAD       );
+
+REG64_FLD( EX_L2_HID_ONE_PPC                                       , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_ONE_PPC    );
+REG64_FLD( EX_L2_HID_EN_INSTRUC_TRACE                              , 1   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_EN_INSTRUC_TRACE );
+REG64_FLD( EX_L2_HID_FLUSH_IC                                      , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_FLUSH_IC   );
+REG64_FLD( EX_L2_HID_EN_ATTN                                       , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_EN_ATTN    );
+REG64_FLD( EX_L2_HID_HILE                                          , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_HILE       );
+REG64_FLD( EX_L2_HID_DIS_RECOVERY                                  , 5   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_DIS_RECOVERY );
+REG64_FLD( EX_L2_HID_MEGAMOUTH                                     , 6   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_MEGAMOUTH  );
+
+REG64_FLD( C_HID_ONE_PPC                                           , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ONE_PPC    );
+REG64_FLD( C_HID_EN_INSTRUC_TRACE                                  , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_EN_INSTRUC_TRACE );
+REG64_FLD( C_HID_FLUSH_IC                                          , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FLUSH_IC   );
+REG64_FLD( C_HID_EN_ATTN                                           , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_EN_ATTN    );
+REG64_FLD( C_HID_HILE                                              , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_HILE       );
+REG64_FLD( C_HID_DIS_RECOVERY                                      , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DIS_RECOVERY );
+REG64_FLD( C_HID_MEGAMOUTH                                         , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MEGAMOUTH  );
+
+REG64_FLD( EQ_HOSTATTN_IN0                                         , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN0        );
+REG64_FLD( EQ_HOSTATTN_IN1                                         , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN1        );
+REG64_FLD( EQ_HOSTATTN_IN2                                         , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN2        );
+REG64_FLD( EQ_HOSTATTN_IN3                                         , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN3        );
+REG64_FLD( EQ_HOSTATTN_IN4                                         , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN4        );
+REG64_FLD( EQ_HOSTATTN_IN5                                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN5        );
+REG64_FLD( EQ_HOSTATTN_IN6                                         , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN6        );
+REG64_FLD( EQ_HOSTATTN_IN7                                         , 7   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN7        );
+REG64_FLD( EQ_HOSTATTN_IN8                                         , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN8        );
+REG64_FLD( EQ_HOSTATTN_IN9                                         , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN9        );
+REG64_FLD( EQ_HOSTATTN_IN10                                        , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN10       );
+REG64_FLD( EQ_HOSTATTN_IN11                                        , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN11       );
+REG64_FLD( EQ_HOSTATTN_IN12                                        , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN12       );
+REG64_FLD( EQ_HOSTATTN_IN13                                        , 13  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN13       );
+REG64_FLD( EQ_HOSTATTN_IN14                                        , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN14       );
+REG64_FLD( EQ_HOSTATTN_IN15                                        , 15  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN15       );
+REG64_FLD( EQ_HOSTATTN_IN16                                        , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN16       );
+REG64_FLD( EQ_HOSTATTN_IN17                                        , 17  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN17       );
+REG64_FLD( EQ_HOSTATTN_IN18                                        , 18  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN18       );
+REG64_FLD( EQ_HOSTATTN_IN19                                        , 19  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN19       );
+REG64_FLD( EQ_HOSTATTN_IN20                                        , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN20       );
+REG64_FLD( EQ_HOSTATTN_IN21                                        , 21  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN21       );
+REG64_FLD( EQ_HOSTATTN_IN22                                        , 22  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN22       );
+
+REG64_FLD( EX_HOSTATTN_IN0                                         , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN0        );
+REG64_FLD( EX_HOSTATTN_IN1                                         , 1   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN1        );
+REG64_FLD( EX_HOSTATTN_IN2                                         , 2   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN2        );
+REG64_FLD( EX_HOSTATTN_IN3                                         , 3   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN3        );
+REG64_FLD( EX_HOSTATTN_IN4                                         , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN4        );
+REG64_FLD( EX_HOSTATTN_IN5                                         , 5   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN5        );
+REG64_FLD( EX_HOSTATTN_IN6                                         , 6   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN6        );
+REG64_FLD( EX_HOSTATTN_IN7                                         , 7   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN7        );
+REG64_FLD( EX_HOSTATTN_IN8                                         , 8   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN8        );
+REG64_FLD( EX_HOSTATTN_IN9                                         , 9   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN9        );
+REG64_FLD( EX_HOSTATTN_IN10                                        , 10  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN10       );
+REG64_FLD( EX_HOSTATTN_IN11                                        , 11  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN11       );
+REG64_FLD( EX_HOSTATTN_IN12                                        , 12  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN12       );
+REG64_FLD( EX_HOSTATTN_IN13                                        , 13  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN13       );
+REG64_FLD( EX_HOSTATTN_IN14                                        , 14  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN14       );
+REG64_FLD( EX_HOSTATTN_IN15                                        , 15  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN15       );
+REG64_FLD( EX_HOSTATTN_IN16                                        , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN16       );
+REG64_FLD( EX_HOSTATTN_IN17                                        , 17  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN17       );
+REG64_FLD( EX_HOSTATTN_IN18                                        , 18  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN18       );
+REG64_FLD( EX_HOSTATTN_IN19                                        , 19  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN19       );
+REG64_FLD( EX_HOSTATTN_IN20                                        , 20  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN20       );
+REG64_FLD( EX_HOSTATTN_IN21                                        , 21  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN21       );
+REG64_FLD( EX_HOSTATTN_IN22                                        , 22  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN22       );
+
+REG64_FLD( C_HOSTATTN_IN0                                          , 0   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN0        );
+REG64_FLD( C_HOSTATTN_IN1                                          , 1   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN1        );
+REG64_FLD( C_HOSTATTN_IN2                                          , 2   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN2        );
+REG64_FLD( C_HOSTATTN_IN3                                          , 3   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN3        );
+REG64_FLD( C_HOSTATTN_IN4                                          , 4   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN4        );
+REG64_FLD( C_HOSTATTN_IN5                                          , 5   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN5        );
+REG64_FLD( C_HOSTATTN_IN6                                          , 6   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN6        );
+REG64_FLD( C_HOSTATTN_IN7                                          , 7   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN7        );
+REG64_FLD( C_HOSTATTN_IN8                                          , 8   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN8        );
+REG64_FLD( C_HOSTATTN_IN9                                          , 9   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN9        );
+REG64_FLD( C_HOSTATTN_IN10                                         , 10  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN10       );
+REG64_FLD( C_HOSTATTN_IN11                                         , 11  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN11       );
+REG64_FLD( C_HOSTATTN_IN12                                         , 12  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN12       );
+REG64_FLD( C_HOSTATTN_IN13                                         , 13  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN13       );
+REG64_FLD( C_HOSTATTN_IN14                                         , 14  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN14       );
+REG64_FLD( C_HOSTATTN_IN15                                         , 15  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN15       );
+REG64_FLD( C_HOSTATTN_IN16                                         , 16  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN16       );
+REG64_FLD( C_HOSTATTN_IN17                                         , 17  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN17       );
+REG64_FLD( C_HOSTATTN_IN18                                         , 18  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN18       );
+REG64_FLD( C_HOSTATTN_IN19                                         , 19  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN19       );
+REG64_FLD( C_HOSTATTN_IN20                                         , 20  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN20       );
+REG64_FLD( C_HOSTATTN_IN21                                         , 21  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN21       );
+REG64_FLD( C_HOSTATTN_IN22                                         , 22  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN22       );
+
+REG64_FLD( EQ_HOSTATTN_MASK_IN                                     , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( EQ_HOSTATTN_MASK_IN_LEN                                 , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( EX_HOSTATTN_MASK_IN                                     , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( EX_HOSTATTN_MASK_IN_LEN                                 , 22  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( C_HOSTATTN_MASK_IN                                      , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( C_HOSTATTN_MASK_IN_LEN                                  , 22  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( EQ_HTM_CTRL_HTMSC_TRIG                                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TRIG );
+REG64_FLD( EQ_HTM_CTRL_HTMSC_TRIG_LEN                              , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TRIG_LEN );
+REG64_FLD( EQ_HTM_CTRL_HTMSC_MTSPR_TRIG                            , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MTSPR_TRIG );
+REG64_FLD( EQ_HTM_CTRL_HTMSC_MTSPR_MARK                            , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MTSPR_MARK );
+REG64_FLD( EQ_HTM_CTRL_HTMSC_MARK                                  , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK );
+REG64_FLD( EQ_HTM_CTRL_HTMSC_MARK_LEN                              , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_LEN );
+REG64_FLD( EQ_HTM_CTRL_HTMSC_DBG0_STOP                             , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DBG0_STOP );
+REG64_FLD( EQ_HTM_CTRL_HTMSC_DBG1_STOP                             , 7   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DBG1_STOP );
+REG64_FLD( EQ_HTM_CTRL_HTMSC_RUN_STOP                              , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_RUN_STOP );
+REG64_FLD( EQ_HTM_CTRL_HTMSC_CHIP0_STOP                            , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CHIP0_STOP );
+REG64_FLD( EQ_HTM_CTRL_HTMSC_CHIP1_STOP                            , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CHIP1_STOP );
+REG64_FLD( EQ_HTM_CTRL_HTMSC_SPARE1112                             , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1112 );
+REG64_FLD( EQ_HTM_CTRL_HTMSC_SPARE1112_LEN                         , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1112_LEN );
+REG64_FLD( EQ_HTM_CTRL_HTMSC_XSTOP_STOP                            , 13  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_XSTOP_STOP );
+REG64_FLD( EQ_HTM_CTRL_HTMSC_SPARE1415                             , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1415 );
+REG64_FLD( EQ_HTM_CTRL_HTMSC_SPARE1415_LEN                         , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1415_LEN );
+
+REG64_FLD( EX_HTM_CTRL_HTMSC_TRIG                                  , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TRIG );
+REG64_FLD( EX_HTM_CTRL_HTMSC_TRIG_LEN                              , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_TRIG_LEN );
+REG64_FLD( EX_HTM_CTRL_HTMSC_MTSPR_TRIG                            , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MTSPR_TRIG );
+REG64_FLD( EX_HTM_CTRL_HTMSC_MTSPR_MARK                            , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MTSPR_MARK );
+REG64_FLD( EX_HTM_CTRL_HTMSC_MARK                                  , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK );
+REG64_FLD( EX_HTM_CTRL_HTMSC_MARK_LEN                              , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_LEN );
+REG64_FLD( EX_HTM_CTRL_HTMSC_DBG0_STOP                             , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DBG0_STOP );
+REG64_FLD( EX_HTM_CTRL_HTMSC_DBG1_STOP                             , 7   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DBG1_STOP );
+REG64_FLD( EX_HTM_CTRL_HTMSC_RUN_STOP                              , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_RUN_STOP );
+REG64_FLD( EX_HTM_CTRL_HTMSC_CHIP0_STOP                            , 9   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CHIP0_STOP );
+REG64_FLD( EX_HTM_CTRL_HTMSC_CHIP1_STOP                            , 10  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CHIP1_STOP );
+REG64_FLD( EX_HTM_CTRL_HTMSC_SPARE1112                             , 11  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1112 );
+REG64_FLD( EX_HTM_CTRL_HTMSC_SPARE1112_LEN                         , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1112_LEN );
+REG64_FLD( EX_HTM_CTRL_HTMSC_XSTOP_STOP                            , 13  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_XSTOP_STOP );
+REG64_FLD( EX_HTM_CTRL_HTMSC_SPARE1415                             , 14  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1415 );
+REG64_FLD( EX_HTM_CTRL_HTMSC_SPARE1415_LEN                         , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE1415_LEN );
+
+REG64_FLD( EQ_HTM_IMA_PDBAR_HTMSC_ENABLE_SPLIT_CORE                , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_ENABLE_SPLIT_CORE );
+REG64_FLD( EQ_HTM_IMA_PDBAR_HTMSC_SPARE2TO4                        , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE2TO4 );
+REG64_FLD( EQ_HTM_IMA_PDBAR_HTMSC_SPARE2TO4_LEN                    , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE2TO4_LEN );
+REG64_FLD( EQ_HTM_IMA_PDBAR_HTMSC_SCOPE                            , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SCOPE );
+REG64_FLD( EQ_HTM_IMA_PDBAR_HTMSC_SCOPE_LEN                        , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SCOPE_LEN );
+REG64_FLD( EQ_HTM_IMA_PDBAR_HTMSC                                  , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC      );
+REG64_FLD( EQ_HTM_IMA_PDBAR_HTMSC_LEN                              , 43  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_LEN  );
+
+REG64_FLD( EX_HTM_IMA_PDBAR_HTMSC_ENABLE_SPLIT_CORE                , 1   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_ENABLE_SPLIT_CORE );
+REG64_FLD( EX_HTM_IMA_PDBAR_HTMSC_SPARE2TO4                        , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE2TO4 );
+REG64_FLD( EX_HTM_IMA_PDBAR_HTMSC_SPARE2TO4_LEN                    , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE2TO4_LEN );
+REG64_FLD( EX_HTM_IMA_PDBAR_HTMSC_SCOPE                            , 5   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SCOPE );
+REG64_FLD( EX_HTM_IMA_PDBAR_HTMSC_SCOPE_LEN                        , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SCOPE_LEN );
+REG64_FLD( EX_HTM_IMA_PDBAR_HTMSC                                  , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC      );
+REG64_FLD( EX_HTM_IMA_PDBAR_HTMSC_LEN                              , 43  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_LEN  );
+
+REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_ERROR                           , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_ERROR );
+REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_TRACE_ACTIVE                    , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_TRACE_ACTIVE );
+REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_PDBAR_ERROR                     , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_PDBAR_ERROR );
+REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_RESERVED                        , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_RESERVED );
+REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_RESERVED_LEN                    , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_RESERVED_LEN );
+REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_FSM                             , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_FSM  );
+REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_FSM_LEN                         , 7   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_FSM_LEN );
+REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_COUNT                           , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_COUNT );
+REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_COUNT_LEN                       , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_COUNT_LEN );
+
+REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_ERROR                           , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_ERROR );
+REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_TRACE_ACTIVE                    , 1   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_TRACE_ACTIVE );
+REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_PDBAR_ERROR                     , 2   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_PDBAR_ERROR );
+REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_RESERVED                        , 3   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_RESERVED );
+REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_RESERVED_LEN                    , 2   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_RESERVED_LEN );
+REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_FSM                             , 5   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_FSM  );
+REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_FSM_LEN                         , 7   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_FSM_LEN );
+REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_COUNT                           , 12  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_COUNT );
+REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_COUNT_LEN                       , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMSC_COUNT_LEN );
+
+REG64_FLD( EQ_HTM_LAST_ADDRESS                                     , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( EQ_HTM_LAST_ADDRESS_LEN                                 , 49  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( EX_HTM_LAST_ADDRESS                                     , 8   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( EX_HTM_LAST_ADDRESS_LEN                                 , 49  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+
+REG64_FLD( EQ_HTM_MEM_HTMSC_ALLOC                                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_ALLOC );
+REG64_FLD( EQ_HTM_MEM_HTMSC_SCOPE                                  , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SCOPE );
+REG64_FLD( EQ_HTM_MEM_HTMSC_SCOPE_LEN                              , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SCOPE_LEN );
+REG64_FLD( EQ_HTM_MEM_HTMSC_PRIORITY                               , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PRIORITY );
+REG64_FLD( EQ_HTM_MEM_HTMSC_SIZE_SMALL                             , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SIZE_SMALL );
+REG64_FLD( EQ_HTM_MEM_HTMSC_SPARE                                  , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE );
+REG64_FLD( EQ_HTM_MEM_HTMSC_SPARE_LEN                              , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE_LEN );
+REG64_FLD( EQ_HTM_MEM_HTMSC_BASE                                   , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_BASE );
+REG64_FLD( EQ_HTM_MEM_HTMSC_BASE_LEN                               , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_BASE_LEN );
+REG64_FLD( EQ_HTM_MEM_HTMSC_SIZE                                   , 40  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SIZE );
+REG64_FLD( EQ_HTM_MEM_HTMSC_SIZE_LEN                               , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SIZE_LEN );
+
+REG64_FLD( EX_HTM_MEM_HTMSC_ALLOC                                  , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_ALLOC );
+REG64_FLD( EX_HTM_MEM_HTMSC_SCOPE                                  , 1   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SCOPE );
+REG64_FLD( EX_HTM_MEM_HTMSC_SCOPE_LEN                              , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SCOPE_LEN );
+REG64_FLD( EX_HTM_MEM_HTMSC_PRIORITY                               , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PRIORITY );
+REG64_FLD( EX_HTM_MEM_HTMSC_SIZE_SMALL                             , 5   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SIZE_SMALL );
+REG64_FLD( EX_HTM_MEM_HTMSC_SPARE                                  , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE );
+REG64_FLD( EX_HTM_MEM_HTMSC_SPARE_LEN                              , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE_LEN );
+REG64_FLD( EX_HTM_MEM_HTMSC_BASE                                   , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_BASE );
+REG64_FLD( EX_HTM_MEM_HTMSC_BASE_LEN                               , 32  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_BASE_LEN );
+REG64_FLD( EX_HTM_MEM_HTMSC_SIZE                                   , 40  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SIZE );
+REG64_FLD( EX_HTM_MEM_HTMSC_SIZE_LEN                               , 9   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SIZE_LEN );
+
+REG64_FLD( EQ_HTM_MODE_HTMSC_ENABLE                                , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_ENABLE );
+REG64_FLD( EQ_HTM_MODE_HTMSC_CONTENT_SEL                           , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CONTENT_SEL );
+REG64_FLD( EQ_HTM_MODE_HTMSC_CONTENT_SEL_LEN                       , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CONTENT_SEL_LEN );
+REG64_FLD( EQ_HTM_MODE_HTMSC_SPARE0                                , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE0 );
+REG64_FLD( EQ_HTM_MODE_HTMSC_CAPTURE                               , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CAPTURE );
+REG64_FLD( EQ_HTM_MODE_HTMSC_CAPTURE_LEN                           , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CAPTURE_LEN );
+REG64_FLD( EQ_HTM_MODE_HTMSC_DD1EQUIV                              , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DD1EQUIV );
+REG64_FLD( EQ_HTM_MODE_HTMSC_SPARE_1TO2                            , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE_1TO2 );
+REG64_FLD( EQ_HTM_MODE_HTMSC_SPARE_1TO2_LEN                        , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE_1TO2_LEN );
+REG64_FLD( EQ_HTM_MODE_HTMSC_WRAP                                  , 13  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_WRAP );
+REG64_FLD( EQ_HTM_MODE_HTMSC_DIS_TSTAMP                            , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_TSTAMP );
+REG64_FLD( EQ_HTM_MODE_HTMSC_SINGLE_TSTAMP                         , 15  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SINGLE_TSTAMP );
+REG64_FLD( EQ_HTM_MODE_HTMSC_DIS_STALL                             , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_STALL );
+REG64_FLD( EQ_HTM_MODE_HTMSC_MARKERS_ONLY                          , 17  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARKERS_ONLY );
+REG64_FLD( EQ_HTM_MODE_HTMSC_DIS_GROUP                             , 18  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_GROUP );
+REG64_FLD( EQ_HTM_MODE_HTMSC_SPARES                                , 19  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARES );
+REG64_FLD( EQ_HTM_MODE_HTMSC_SPARES_LEN                            , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARES_LEN );
+REG64_FLD( EQ_HTM_MODE_HTMSC_VGTARGET                              , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_VGTARGET );
+REG64_FLD( EQ_HTM_MODE_HTMSC_VGTARGET_LEN                          , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_VGTARGET_LEN );
+
+REG64_FLD( EX_HTM_MODE_HTMSC_ENABLE                                , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_ENABLE );
+REG64_FLD( EX_HTM_MODE_HTMSC_CONTENT_SEL                           , 1   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CONTENT_SEL );
+REG64_FLD( EX_HTM_MODE_HTMSC_CONTENT_SEL_LEN                       , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CONTENT_SEL_LEN );
+REG64_FLD( EX_HTM_MODE_HTMSC_SPARE0                                , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE0 );
+REG64_FLD( EX_HTM_MODE_HTMSC_CAPTURE                               , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CAPTURE );
+REG64_FLD( EX_HTM_MODE_HTMSC_CAPTURE_LEN                           , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_CAPTURE_LEN );
+REG64_FLD( EX_HTM_MODE_HTMSC_DD1EQUIV                              , 10  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DD1EQUIV );
+REG64_FLD( EX_HTM_MODE_HTMSC_SPARE_1TO2                            , 11  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE_1TO2 );
+REG64_FLD( EX_HTM_MODE_HTMSC_SPARE_1TO2_LEN                        , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARE_1TO2_LEN );
+REG64_FLD( EX_HTM_MODE_HTMSC_WRAP                                  , 13  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_WRAP );
+REG64_FLD( EX_HTM_MODE_HTMSC_DIS_TSTAMP                            , 14  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_TSTAMP );
+REG64_FLD( EX_HTM_MODE_HTMSC_SINGLE_TSTAMP                         , 15  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SINGLE_TSTAMP );
+REG64_FLD( EX_HTM_MODE_HTMSC_DIS_STALL                             , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_STALL );
+REG64_FLD( EX_HTM_MODE_HTMSC_MARKERS_ONLY                          , 17  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARKERS_ONLY );
+REG64_FLD( EX_HTM_MODE_HTMSC_DIS_GROUP                             , 18  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_DIS_GROUP );
+REG64_FLD( EX_HTM_MODE_HTMSC_SPARES                                , 19  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARES );
+REG64_FLD( EX_HTM_MODE_HTMSC_SPARES_LEN                            , 5   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_SPARES_LEN );
+REG64_FLD( EX_HTM_MODE_HTMSC_VGTARGET                              , 24  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_VGTARGET );
+REG64_FLD( EX_HTM_MODE_HTMSC_VGTARGET_LEN                          , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_VGTARGET_LEN );
+
+REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_PURGE_IN_PROG                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_PURGE_IN_PROG );
+REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_PURGE_DONE                     , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_PURGE_DONE );
+REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_CRESP_OV                       , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_CRESP_OV );
+REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_REPAIR                         , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_REPAIR );
+REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_BUF_WAIT                       , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_BUF_WAIT );
+REG64_FLD( EQ_HTM_STAT_STATUS_TRIG_DROPPED_Q                       , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_TRIG_DROPPED_Q );
+REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_ADDR_ERROR                     , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_ADDR_ERROR );
+REG64_FLD( EQ_HTM_STAT_STATUS_REC_DROPPED_Q                        , 7   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_REC_DROPPED_Q );
+REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_INIT                           , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_INIT );
+REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_PREREQ                         , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_PREREQ );
+REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_READY                          , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_READY );
+REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_TRACING                        , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_TRACING );
+REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_PAUSED                         , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_PAUSED );
+REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_FLUSH                          , 13  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_FLUSH );
+REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_COMPLETE                       , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_COMPLETE );
+REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_ENABLE                         , 15  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_ENABLE );
+REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_STAMP                          , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_STAMP );
+REG64_FLD( EQ_HTM_STAT_STATUS_SCOM_ERROR                           , 17  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_SCOM_ERROR );
+REG64_FLD( EQ_HTM_STAT_STATUS_UNUSED                               , 18  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_UNUSED );
+REG64_FLD( EQ_HTM_STAT_STATUS_UNUSED_LEN                           , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_UNUSED_LEN );
+
+REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_PURGE_IN_PROG                  , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_PURGE_IN_PROG );
+REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_PURGE_DONE                     , 1   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_PURGE_DONE );
+REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_CRESP_OV                       , 2   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_CRESP_OV );
+REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_REPAIR                         , 3   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_REPAIR );
+REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_BUF_WAIT                       , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_BUF_WAIT );
+REG64_FLD( EX_HTM_STAT_STATUS_TRIG_DROPPED_Q                       , 5   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_TRIG_DROPPED_Q );
+REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_ADDR_ERROR                     , 6   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_ADDR_ERROR );
+REG64_FLD( EX_HTM_STAT_STATUS_REC_DROPPED_Q                        , 7   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_REC_DROPPED_Q );
+REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_INIT                           , 8   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_INIT );
+REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_PREREQ                         , 9   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_PREREQ );
+REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_READY                          , 10  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_READY );
+REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_TRACING                        , 11  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_TRACING );
+REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_PAUSED                         , 12  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_PAUSED );
+REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_FLUSH                          , 13  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_FLUSH );
+REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_COMPLETE                       , 14  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_COMPLETE );
+REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_ENABLE                         , 15  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_ENABLE );
+REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_STAMP                          , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HTMCO_STATUS_STAMP );
+REG64_FLD( EX_HTM_STAT_STATUS_SCOM_ERROR                           , 17  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_SCOM_ERROR );
+REG64_FLD( EX_HTM_STAT_STATUS_UNUSED                               , 18  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_UNUSED );
+REG64_FLD( EX_HTM_STAT_STATUS_UNUSED_LEN                           , 2   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STATUS_UNUSED_LEN );
+
+REG64_FLD( EQ_HTM_TRIG_HTMSC_START                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_START );
+REG64_FLD( EQ_HTM_TRIG_HTMSC_STOP                                  , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_STOP );
+REG64_FLD( EQ_HTM_TRIG_HTMSC_PAUSE                                 , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PAUSE );
+REG64_FLD( EQ_HTM_TRIG_HTMSC_STOP_ALT                              , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_STOP_ALT );
+REG64_FLD( EQ_HTM_TRIG_HTMSC_RESET                                 , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_RESET );
+REG64_FLD( EQ_HTM_TRIG_HTMSC_MARK_VALID                            , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_VALID );
+REG64_FLD( EQ_HTM_TRIG_HTMSC_MARK_TYPE                             , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_TYPE );
+REG64_FLD( EQ_HTM_TRIG_HTMSC_MARK_TYPE_LEN                         , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_TYPE_LEN );
+
+REG64_FLD( EX_HTM_TRIG_HTMSC_START                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_START );
+REG64_FLD( EX_HTM_TRIG_HTMSC_STOP                                  , 1   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_STOP );
+REG64_FLD( EX_HTM_TRIG_HTMSC_PAUSE                                 , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_PAUSE );
+REG64_FLD( EX_HTM_TRIG_HTMSC_STOP_ALT                              , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_STOP_ALT );
+REG64_FLD( EX_HTM_TRIG_HTMSC_RESET                                 , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_RESET );
+REG64_FLD( EX_HTM_TRIG_HTMSC_MARK_VALID                            , 5   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_VALID );
+REG64_FLD( EX_HTM_TRIG_HTMSC_MARK_TYPE                             , 6   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_TYPE );
+REG64_FLD( EX_HTM_TRIG_HTMSC_MARK_TYPE_LEN                         , 10  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HTMSC_MARK_TYPE_LEN );
+
+REG64_FLD( EQ_INJECT_REG_THERM_TRIP                                , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_THERM_TRIP );
+REG64_FLD( EQ_INJECT_REG_THERM_TRIP_LEN                            , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_THERM_TRIP_LEN );
+REG64_FLD( EQ_INJECT_REG_THERM_MODE                                , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_THERM_MODE );
+REG64_FLD( EQ_INJECT_REG_THERM_MODE_LEN                            , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_THERM_MODE_LEN );
+
+REG64_FLD( EX_INJECT_REG_THERM_TRIP                                , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_THERM_TRIP );
+REG64_FLD( EX_INJECT_REG_THERM_TRIP_LEN                            , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_THERM_TRIP_LEN );
+REG64_FLD( EX_INJECT_REG_THERM_MODE                                , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_THERM_MODE );
+REG64_FLD( EX_INJECT_REG_THERM_MODE_LEN                            , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_THERM_MODE_LEN );
+
+REG64_FLD( C_INJECT_REG_THERM_TRIP                                 , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_THERM_TRIP );
+REG64_FLD( C_INJECT_REG_THERM_TRIP_LEN                             , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_THERM_TRIP_LEN );
+REG64_FLD( C_INJECT_REG_THERM_MODE                                 , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_THERM_MODE );
+REG64_FLD( C_INJECT_REG_THERM_MODE_LEN                             , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_THERM_MODE_LEN );
+
+REG64_FLD( EQ_INJ_REG_STQ_ERR                                      , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STQ_ERR    );
+REG64_FLD( EQ_INJ_REG_STQ_ERR_LEN                                  , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STQ_ERR_LEN );
+
+REG64_FLD( EX_INJ_REG_STQ_ERR                                      , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STQ_ERR    );
+REG64_FLD( EX_INJ_REG_STQ_ERR_LEN                                  , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STQ_ERR_LEN );
+
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_HI_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN                , 64  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN                , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS                 , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN             , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK               , 42  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN           , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID         , 51  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN            , 52  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_RUNNING                 , 53  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS            , 54  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN        , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE    , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL       , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL       , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL       , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL       , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK       , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK      , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK       , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK      , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE      , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE      , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE      , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_HI_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN                , 64  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN                , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS                 , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN             , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK               , 42  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN           , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID         , 51  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN            , 52  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_RUNNING                 , 53  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS            , 54  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN        , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE    , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL       , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL       , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL       , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL       , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK       , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK      , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK       , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK      , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE      , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE      , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE      , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_HI_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN                , 64  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN                , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS                 , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN             , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK               , 42  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN           , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID         , 51  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN            , 52  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_RUNNING                 , 53  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS            , 54  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN        , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE    , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL       , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL       , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL       , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL       , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK       , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK      , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK       , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK      , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE      , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE      , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE      , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_HI_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_HI_DATA_REG_DATA_LEN                , 64  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_DATA_LEN                , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS                 , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN             , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK               , 42  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN           , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID         , 51  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN            , 52  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_RUNNING                 , 53  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS            , 54  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN        , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE    , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL       , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL       , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL       , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL       , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK       , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK      , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK       , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK      , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE      , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE      , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE      , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL0_BAD_HPC                     , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL0_BAD_HPC );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL1_BAD_HPC                     , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL1_BAD_HPC );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_L3CORTR_NO_LCO_TGTS                  , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3CORTR_NO_LCO_TGTS );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_SN0_RCMD_TTAG_P                      , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN0_RCMD_TTAG_P );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_SN1_RCMD_TTAG_P                      , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN1_RCMD_TTAG_P );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_SN0_RCMD_ADDR_P                      , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN0_RCMD_ADDR_P );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_SN1_RCMD_ADDR_P                      , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN1_RCMD_ADDR_P );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_SN0_CRESP_TTAG_P                     , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN0_CRESP_TTAG_P );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_SN1_CRESP_TTAG_P                     , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN1_CRESP_TTAG_P );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_SN0_CRESP_ATAG_P                     , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN0_CRESP_ATAG_P );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_SN1_CRESP_ATAG_P                     , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN1_CRESP_ATAG_P );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_DATA_RTAG_P                          , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DATA_RTAG_P );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_PF_UNSOLICITED_CRESP                 , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PF_UNSOLICITED_CRESP );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_SN_UNSOLICITED_CRESP                 , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN_UNSOLICITED_CRESP );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_CO_UNSOLICITED_CRESP                 , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CO_UNSOLICITED_CRESP );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_SPARE_15                             , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_15   );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_SPARE_16                             , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_16   );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_SPARE_17                             , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_17   );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_WI_UNSOLICITED_DATA                  , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WI_UNSOLICITED_DATA );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_PF_UNSOLICITED_DATA                  , 19  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PF_UNSOLICITED_DATA );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_TM_CAM                               , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TM_CAM     );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_TM_CAM_LEN                           , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TM_CAM_LEN );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_COFSM_ADDR                           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COFSM_ADDR );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_SNFSM_ADDR                           , 25  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SNFSM_ADDR );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL0_CACHE_INHIBIT               , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL0_CACHE_INHIBIT );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL1_CACHE_INHIBIT               , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL1_CACHE_INHIBIT );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL2_CACHE_INHIBIT               , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL2_CACHE_INHIBIT );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL3_CACHE_INHIBIT               , 29  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL3_CACHE_INHIBIT );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL2_BAD_HPC                     , 30  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL2_BAD_HPC );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL3_BAD_HPC                     , 31  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL3_BAD_HPC );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_SN_MACHINE_HANG                      , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN_MACHINE_HANG );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_RD_MACHINE_HANG                      , 33  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RD_MACHINE_HANG );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_CI_MACHINE_HANG                      , 34  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CI_MACHINE_HANG );
+REG64_FLD( EQ_L3_ERR_RPT0_REG_CO_MACHINE_HANG                      , 35  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CO_MACHINE_HANG );
+
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL0_BAD_HPC                  , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL0_BAD_HPC );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL1_BAD_HPC                  , 1   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL1_BAD_HPC );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3CORTR_NO_LCO_TGTS               , 2   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3CORTR_NO_LCO_TGTS );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN0_RCMD_TTAG_P                   , 3   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN0_RCMD_TTAG_P );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN1_RCMD_TTAG_P                   , 4   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN1_RCMD_TTAG_P );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN0_RCMD_ADDR_P                   , 5   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN0_RCMD_ADDR_P );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN1_RCMD_ADDR_P                   , 6   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN1_RCMD_ADDR_P );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN0_CRESP_TTAG_P                  , 7   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN0_CRESP_TTAG_P );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN1_CRESP_TTAG_P                  , 8   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN1_CRESP_TTAG_P );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN0_CRESP_ATAG_P                  , 9   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN0_CRESP_ATAG_P );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN1_CRESP_ATAG_P                  , 10  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN1_CRESP_ATAG_P );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_DATA_RTAG_P                       , 11  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_DATA_RTAG_P );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_PF_UNSOLICITED_CRESP              , 12  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_PF_UNSOLICITED_CRESP );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN_UNSOLICITED_CRESP              , 13  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN_UNSOLICITED_CRESP );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_CO_UNSOLICITED_CRESP              , 14  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_CO_UNSOLICITED_CRESP );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SPARE_15                          , 15  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_15   );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SPARE_16                          , 16  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_16   );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SPARE_17                          , 17  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_17   );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_WI_UNSOLICITED_DATA               , 18  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_WI_UNSOLICITED_DATA );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_PF_UNSOLICITED_DATA               , 19  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_PF_UNSOLICITED_DATA );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_TM_CAM                            , 20  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_TM_CAM     );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_TM_CAM_LEN                        , 4   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_TM_CAM_LEN );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_COFSM_ADDR                        , 24  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_COFSM_ADDR );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SNFSM_ADDR                        , 25  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SNFSM_ADDR );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL0_CACHE_INHIBIT            , 26  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL0_CACHE_INHIBIT );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL1_CACHE_INHIBIT            , 27  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL1_CACHE_INHIBIT );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL2_CACHE_INHIBIT            , 28  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL2_CACHE_INHIBIT );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL3_CACHE_INHIBIT            , 29  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL3_CACHE_INHIBIT );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL2_BAD_HPC                  , 30  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL2_BAD_HPC );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL3_BAD_HPC                  , 31  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3SDRTL3_BAD_HPC );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN_MACHINE_HANG                   , 32  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN_MACHINE_HANG );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_RD_MACHINE_HANG                   , 33  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_RD_MACHINE_HANG );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_CI_MACHINE_HANG                   , 34  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_CI_MACHINE_HANG );
+REG64_FLD( EX_L3_L3_ERR_RPT0_REG_CO_MACHINE_HANG                   , 35  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_CO_MACHINE_HANG );
+
+REG64_FLD( EQ_L3_ERR_RPT1_REG_PF_MACHINE_HANG                      , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PF_MACHINE_HANG );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_WI_MACHINE_HANG                      , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WI_MACHINE_HANG );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_L3L2CTL_RD_OVERRUN_CK                , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3L2CTL_RD_OVERRUN_CK );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_L3L2CTL_PF_OVERRUN_CK                , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3L2CTL_PF_OVERRUN_CK );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_L3CICTL_CI_OVERRUN_CK                , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3CICTL_CI_OVERRUN_CK );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_L3XMEMA0_DW_DIR_HIT                  , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3XMEMA0_DW_DIR_HIT );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_L3XMEMA1_DW_DIR_HIT                  , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3XMEMA1_DW_DIR_HIT );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_L3XMEMA0_CRW_DIR_HIT                 , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3XMEMA0_CRW_DIR_HIT );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_L3XMEMA1_CRW_DIR_HIT                 , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3XMEMA1_CRW_DIR_HIT );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR0                 , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PBEXCA0_CMD_REQ_ERR0 );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR1                 , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PBEXCA0_CMD_REQ_ERR1 );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR2                 , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PBEXCA0_CMD_REQ_ERR2 );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR0                 , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PBEXCA1_CMD_REQ_ERR0 );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR1                 , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PBEXCA1_CMD_REQ_ERR1 );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR2                 , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PBEXCA1_CMD_REQ_ERR2 );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_MC_FP_MATE_CMD_ERR0                  , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MC_FP_MATE_CMD_ERR0 );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_MC_FP_MATE_CMD_ERR1                  , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MC_FP_MATE_CMD_ERR1 );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_L3PBEXCA0_OVERFLOW                   , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3PBEXCA0_OVERFLOW );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_L3PBEXCA1_OVERFLOW                   , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3PBEXCA1_OVERFLOW );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_L3PBEXCA0_UNDERFLOW                  , 19  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3PBEXCA0_UNDERFLOW );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_L3PBEXCA1_UNDERFLOW                  , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3PBEXCA1_UNDERFLOW );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_PF_MACHINE_W4DT_HANG                 , 21  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PF_MACHINE_W4DT_HANG );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_WI_MACHINE_W4DT_HANG                 , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WI_MACHINE_W4DT_HANG );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_CO_CRESP_ACK_DEAD                    , 23  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CO_CRESP_ACK_DEAD );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_SN_CRESP_ACK_DEAD                    , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN_CRESP_ACK_DEAD );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_SN2_RCMD_TTAG_P                      , 25  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN2_RCMD_TTAG_P );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_SN3_RCMD_TTAG_P                      , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN3_RCMD_TTAG_P );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_SN2_RCMD_ADDR_P                      , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN2_RCMD_ADDR_P );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_SN3_RCMD_ADDR_P                      , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN3_RCMD_ADDR_P );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_SN2_CRESP_TTAG_P                     , 29  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN2_CRESP_TTAG_P );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_SN3_CRESP_TTAG_P                     , 30  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN3_CRESP_TTAG_P );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_SN2_CRESP_ATAG_P                     , 31  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN2_CRESP_ATAG_P );
+REG64_FLD( EQ_L3_ERR_RPT1_REG_SN3_CRESP_ATAG_P                     , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SN3_CRESP_ATAG_P );
+
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PF_MACHINE_HANG                   , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_PF_MACHINE_HANG );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_WI_MACHINE_HANG                   , 1   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_WI_MACHINE_HANG );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3L2CTL_RD_OVERRUN_CK             , 2   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3L2CTL_RD_OVERRUN_CK );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3L2CTL_PF_OVERRUN_CK             , 3   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3L2CTL_PF_OVERRUN_CK );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3CICTL_CI_OVERRUN_CK             , 4   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3CICTL_CI_OVERRUN_CK );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3XMEMA0_DW_DIR_HIT               , 5   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3XMEMA0_DW_DIR_HIT );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3XMEMA1_DW_DIR_HIT               , 6   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3XMEMA1_DW_DIR_HIT );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3XMEMA0_CRW_DIR_HIT              , 7   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3XMEMA0_CRW_DIR_HIT );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3XMEMA1_CRW_DIR_HIT              , 8   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3XMEMA1_CRW_DIR_HIT );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR0              , 9   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_PBEXCA0_CMD_REQ_ERR0 );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR1              , 10  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_PBEXCA0_CMD_REQ_ERR1 );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR2              , 11  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_PBEXCA0_CMD_REQ_ERR2 );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR0              , 12  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_PBEXCA1_CMD_REQ_ERR0 );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR1              , 13  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_PBEXCA1_CMD_REQ_ERR1 );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR2              , 14  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_PBEXCA1_CMD_REQ_ERR2 );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_MC_FP_MATE_CMD_ERR0               , 15  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_MC_FP_MATE_CMD_ERR0 );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_MC_FP_MATE_CMD_ERR1               , 16  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_MC_FP_MATE_CMD_ERR1 );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3PBEXCA0_OVERFLOW                , 17  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3PBEXCA0_OVERFLOW );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3PBEXCA1_OVERFLOW                , 18  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3PBEXCA1_OVERFLOW );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3PBEXCA0_UNDERFLOW               , 19  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3PBEXCA0_UNDERFLOW );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3PBEXCA1_UNDERFLOW               , 20  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3PBEXCA1_UNDERFLOW );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PF_MACHINE_W4DT_HANG              , 21  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_PF_MACHINE_W4DT_HANG );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_WI_MACHINE_W4DT_HANG              , 22  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_WI_MACHINE_W4DT_HANG );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_CO_CRESP_ACK_DEAD                 , 23  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_CO_CRESP_ACK_DEAD );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN_CRESP_ACK_DEAD                 , 24  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN_CRESP_ACK_DEAD );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN2_RCMD_TTAG_P                   , 25  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN2_RCMD_TTAG_P );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN3_RCMD_TTAG_P                   , 26  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN3_RCMD_TTAG_P );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN2_RCMD_ADDR_P                   , 27  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN2_RCMD_ADDR_P );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN3_RCMD_ADDR_P                   , 28  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN3_RCMD_ADDR_P );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN2_CRESP_TTAG_P                  , 29  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN2_CRESP_TTAG_P );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN3_CRESP_TTAG_P                  , 30  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN3_CRESP_TTAG_P );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN2_CRESP_ATAG_P                  , 31  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN2_CRESP_ATAG_P );
+REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN3_CRESP_ATAG_P                  , 32  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_SN3_CRESP_ATAG_P );
+
+REG64_FLD( EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER0_EPS_VAL            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER0_EPS_VAL );
+REG64_FLD( EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER0_EPS_VAL_LEN        , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER0_EPS_VAL_LEN );
+REG64_FLD( EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL            , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER1_EPS_VAL );
+REG64_FLD( EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL_LEN        , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER1_EPS_VAL_LEN );
+REG64_FLD( EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER2_EPS_VAL );
+REG64_FLD( EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL_LEN        , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER2_EPS_VAL_LEN );
+REG64_FLD( EQ_L3_RD_EPSILON_CFG_REG_EPS_MODE_SEL                   , 36  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EPS_MODE_SEL );
+
+REG64_FLD( EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER0_EPS_VAL            , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER0_EPS_VAL );
+REG64_FLD( EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER0_EPS_VAL_LEN        , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER0_EPS_VAL_LEN );
+REG64_FLD( EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL            , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER1_EPS_VAL );
+REG64_FLD( EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL_LEN        , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER1_EPS_VAL_LEN );
+REG64_FLD( EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL            , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER2_EPS_VAL );
+REG64_FLD( EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL_LEN        , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER2_EPS_VAL_LEN );
+REG64_FLD( EX_L3_RD_EPSILON_CFG_REG_EPS_MODE_SEL                   , 36  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_EPS_MODE_SEL );
+
+REG64_FLD( EQ_L3_RTIM_PERIOD_MONITOR_MON                           , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MON        );
+REG64_FLD( EQ_L3_RTIM_PERIOD_MONITOR_MON_LEN                       , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MON_LEN    );
+
+REG64_FLD( EX_L3_L3_RTIM_PERIOD_MONITOR_MON                        , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_MON        );
+REG64_FLD( EX_L3_L3_RTIM_PERIOD_MONITOR_MON_LEN                    , 8   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_MON_LEN    );
+
+REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER1_EPS_VAL );
+REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL_LEN        , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER1_EPS_VAL_LEN );
+REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL            , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER2_EPS_VAL );
+REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL_LEN        , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER2_EPS_VAL_LEN );
+REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_EN_WT4CR_EPS_ON_LCO            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EN_WT4CR_EPS_ON_LCO );
+REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_EN_WT4CR_EXTENDED_MODE         , 25  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EN_WT4CR_EXTENDED_MODE );
+REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_EPS_STEP_MODE                  , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EPS_STEP_MODE );
+REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_EPS_STEP_MODE_LEN              , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EPS_STEP_MODE_LEN );
+REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_EPS_DIVIDER_MODE               , 30  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EPS_DIVIDER_MODE );
+REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_EPS_DIVIDER_MODE_LEN           , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EPS_DIVIDER_MODE_LEN );
+REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_EPS_CNT_USE_DIVIDER_EN         , 34  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EPS_CNT_USE_DIVIDER_EN );
+
+REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL         , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER1_EPS_VAL );
+REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL_LEN     , 12  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER1_EPS_VAL_LEN );
+REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL         , 12  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER2_EPS_VAL );
+REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL_LEN     , 12  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_WT4CR_TIER2_EPS_VAL_LEN );
+REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_EN_WT4CR_EPS_ON_LCO         , 24  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_EN_WT4CR_EPS_ON_LCO );
+REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_EN_WT4CR_EXTENDED_MODE      , 25  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_EN_WT4CR_EXTENDED_MODE );
+REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_EPS_STEP_MODE               , 26  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_EPS_STEP_MODE );
+REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_EPS_STEP_MODE_LEN           , 4   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_EPS_STEP_MODE_LEN );
+REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_EPS_DIVIDER_MODE            , 30  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_EPS_DIVIDER_MODE );
+REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_EPS_DIVIDER_MODE_LEN        , 4   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_EPS_DIVIDER_MODE_LEN );
+REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_EPS_CNT_USE_DIVIDER_EN      , 34  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_EPS_CNT_USE_DIVIDER_EN );
+
+REG64_FLD( EQ_LINEDEL_TRIG_REG_TRIG                                , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG       );
+REG64_FLD( EQ_LINEDEL_TRIG_REG_DONE                                , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DONE       );
+REG64_FLD( EQ_LINEDEL_TRIG_REG_SPARE                               , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( EQ_LINEDEL_TRIG_REG_SPARE_LEN                           , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+
+REG64_FLD( EX_L2_LINEDEL_TRIG_REG_TRIG                             , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_TRIG       );
+REG64_FLD( EX_L2_LINEDEL_TRIG_REG_DONE                             , 1   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_DONE       );
+REG64_FLD( EX_L2_LINEDEL_TRIG_REG_SPARE                            , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_SPARE      );
+REG64_FLD( EX_L2_LINEDEL_TRIG_REG_SPARE_LEN                        , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_LEN  );
+
+REG64_FLD( EQ_LINE_DELETED_MEMBERS_REG_L3                          , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3         );
+REG64_FLD( EQ_LINE_DELETED_MEMBERS_REG_L3_LEN                      , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LEN     );
+
+REG64_FLD( EX_L3_LINE_DELETED_MEMBERS_REG_L3                       , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3         );
+REG64_FLD( EX_L3_LINE_DELETED_MEMBERS_REG_L3_LEN                   , 5   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_LEN     );
+
+REG64_FLD( EQ_LOCAL_FIR_IN0                                        , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN0        );
+REG64_FLD( EQ_LOCAL_FIR_IN1                                        , 1   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN1        );
+REG64_FLD( EQ_LOCAL_FIR_IN2                                        , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN2        );
+REG64_FLD( EQ_LOCAL_FIR_IN3                                        , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN3        );
+REG64_FLD( EQ_LOCAL_FIR_IN4                                        , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN4        );
+REG64_FLD( EQ_LOCAL_FIR_IN5                                        , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN5        );
+REG64_FLD( EQ_LOCAL_FIR_IN6                                        , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN6        );
+REG64_FLD( EQ_LOCAL_FIR_IN7                                        , 7   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN7        );
+REG64_FLD( EQ_LOCAL_FIR_IN8                                        , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN8        );
+REG64_FLD( EQ_LOCAL_FIR_IN9                                        , 9   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN9        );
+REG64_FLD( EQ_LOCAL_FIR_IN10                                       , 10  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN10       );
+REG64_FLD( EQ_LOCAL_FIR_IN11                                       , 11  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN11       );
+REG64_FLD( EQ_LOCAL_FIR_IN12                                       , 12  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN12       );
+REG64_FLD( EQ_LOCAL_FIR_IN13                                       , 13  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN13       );
+REG64_FLD( EQ_LOCAL_FIR_IN14                                       , 14  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN14       );
+REG64_FLD( EQ_LOCAL_FIR_IN15                                       , 15  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN15       );
+REG64_FLD( EQ_LOCAL_FIR_IN16                                       , 16  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN16       );
+REG64_FLD( EQ_LOCAL_FIR_IN17                                       , 17  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN17       );
+REG64_FLD( EQ_LOCAL_FIR_IN18                                       , 18  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN18       );
+REG64_FLD( EQ_LOCAL_FIR_IN19                                       , 19  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN19       );
+REG64_FLD( EQ_LOCAL_FIR_IN20                                       , 20  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN20       );
+REG64_FLD( EQ_LOCAL_FIR_IN21                                       , 21  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN21       );
+REG64_FLD( EQ_LOCAL_FIR_IN22                                       , 22  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN22       );
+REG64_FLD( EQ_LOCAL_FIR_IN23                                       , 23  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN23       );
+REG64_FLD( EQ_LOCAL_FIR_IN24                                       , 24  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN24       );
+REG64_FLD( EQ_LOCAL_FIR_IN25                                       , 25  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN25       );
+REG64_FLD( EQ_LOCAL_FIR_IN26                                       , 26  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN26       );
+REG64_FLD( EQ_LOCAL_FIR_IN27                                       , 27  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN27       );
+REG64_FLD( EQ_LOCAL_FIR_IN28                                       , 28  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN28       );
+REG64_FLD( EQ_LOCAL_FIR_IN29                                       , 29  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN29       );
+REG64_FLD( EQ_LOCAL_FIR_IN30                                       , 30  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN30       );
+REG64_FLD( EQ_LOCAL_FIR_IN31                                       , 31  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN31       );
+REG64_FLD( EQ_LOCAL_FIR_IN32                                       , 32  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN32       );
+REG64_FLD( EQ_LOCAL_FIR_IN33                                       , 33  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN33       );
+REG64_FLD( EQ_LOCAL_FIR_IN34                                       , 34  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN34       );
+REG64_FLD( EQ_LOCAL_FIR_IN35                                       , 35  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN35       );
+REG64_FLD( EQ_LOCAL_FIR_IN36                                       , 36  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN36       );
+REG64_FLD( EQ_LOCAL_FIR_IN37                                       , 37  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN37       );
+REG64_FLD( EQ_LOCAL_FIR_IN38                                       , 38  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN38       );
+REG64_FLD( EQ_LOCAL_FIR_IN39                                       , 39  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN39       );
+REG64_FLD( EQ_LOCAL_FIR_IN40                                       , 40  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN40       );
+REG64_FLD( EQ_LOCAL_FIR_IN41                                       , 41  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN41       );
+
+REG64_FLD( EX_LOCAL_FIR_IN0                                        , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN0        );
+REG64_FLD( EX_LOCAL_FIR_IN1                                        , 1   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN1        );
+REG64_FLD( EX_LOCAL_FIR_IN2                                        , 2   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN2        );
+REG64_FLD( EX_LOCAL_FIR_IN3                                        , 3   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN3        );
+REG64_FLD( EX_LOCAL_FIR_IN4                                        , 4   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN4        );
+REG64_FLD( EX_LOCAL_FIR_IN5                                        , 5   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN5        );
+REG64_FLD( EX_LOCAL_FIR_IN6                                        , 6   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN6        );
+REG64_FLD( EX_LOCAL_FIR_IN7                                        , 7   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN7        );
+REG64_FLD( EX_LOCAL_FIR_IN8                                        , 8   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN8        );
+REG64_FLD( EX_LOCAL_FIR_IN9                                        , 9   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN9        );
+REG64_FLD( EX_LOCAL_FIR_IN10                                       , 10  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN10       );
+REG64_FLD( EX_LOCAL_FIR_IN11                                       , 11  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN11       );
+REG64_FLD( EX_LOCAL_FIR_IN12                                       , 12  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN12       );
+REG64_FLD( EX_LOCAL_FIR_IN13                                       , 13  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN13       );
+REG64_FLD( EX_LOCAL_FIR_IN14                                       , 14  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN14       );
+REG64_FLD( EX_LOCAL_FIR_IN15                                       , 15  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN15       );
+REG64_FLD( EX_LOCAL_FIR_IN16                                       , 16  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN16       );
+REG64_FLD( EX_LOCAL_FIR_IN17                                       , 17  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN17       );
+REG64_FLD( EX_LOCAL_FIR_IN18                                       , 18  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN18       );
+REG64_FLD( EX_LOCAL_FIR_IN19                                       , 19  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN19       );
+REG64_FLD( EX_LOCAL_FIR_IN20                                       , 20  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN20       );
+REG64_FLD( EX_LOCAL_FIR_IN21                                       , 21  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN21       );
+REG64_FLD( EX_LOCAL_FIR_IN22                                       , 22  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN22       );
+REG64_FLD( EX_LOCAL_FIR_IN23                                       , 23  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN23       );
+REG64_FLD( EX_LOCAL_FIR_IN24                                       , 24  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN24       );
+REG64_FLD( EX_LOCAL_FIR_IN25                                       , 25  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN25       );
+REG64_FLD( EX_LOCAL_FIR_IN26                                       , 26  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN26       );
+REG64_FLD( EX_LOCAL_FIR_IN27                                       , 27  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN27       );
+REG64_FLD( EX_LOCAL_FIR_IN28                                       , 28  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN28       );
+REG64_FLD( EX_LOCAL_FIR_IN29                                       , 29  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN29       );
+REG64_FLD( EX_LOCAL_FIR_IN30                                       , 30  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN30       );
+REG64_FLD( EX_LOCAL_FIR_IN31                                       , 31  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN31       );
+REG64_FLD( EX_LOCAL_FIR_IN32                                       , 32  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN32       );
+REG64_FLD( EX_LOCAL_FIR_IN33                                       , 33  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN33       );
+REG64_FLD( EX_LOCAL_FIR_IN34                                       , 34  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN34       );
+REG64_FLD( EX_LOCAL_FIR_IN35                                       , 35  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN35       );
+REG64_FLD( EX_LOCAL_FIR_IN36                                       , 36  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN36       );
+REG64_FLD( EX_LOCAL_FIR_IN37                                       , 37  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN37       );
+REG64_FLD( EX_LOCAL_FIR_IN38                                       , 38  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN38       );
+REG64_FLD( EX_LOCAL_FIR_IN39                                       , 39  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN39       );
+REG64_FLD( EX_LOCAL_FIR_IN40                                       , 40  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN40       );
+REG64_FLD( EX_LOCAL_FIR_IN41                                       , 41  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN41       );
+
+REG64_FLD( C_LOCAL_FIR_IN0                                         , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN0        );
+REG64_FLD( C_LOCAL_FIR_IN1                                         , 1   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN1        );
+REG64_FLD( C_LOCAL_FIR_IN2                                         , 2   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN2        );
+REG64_FLD( C_LOCAL_FIR_IN3                                         , 3   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN3        );
+REG64_FLD( C_LOCAL_FIR_IN4                                         , 4   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN4        );
+REG64_FLD( C_LOCAL_FIR_IN5                                         , 5   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN5        );
+REG64_FLD( C_LOCAL_FIR_IN6                                         , 6   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN6        );
+REG64_FLD( C_LOCAL_FIR_IN7                                         , 7   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN7        );
+REG64_FLD( C_LOCAL_FIR_IN8                                         , 8   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN8        );
+REG64_FLD( C_LOCAL_FIR_IN9                                         , 9   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN9        );
+REG64_FLD( C_LOCAL_FIR_IN10                                        , 10  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN10       );
+REG64_FLD( C_LOCAL_FIR_IN11                                        , 11  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN11       );
+REG64_FLD( C_LOCAL_FIR_IN12                                        , 12  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN12       );
+REG64_FLD( C_LOCAL_FIR_IN13                                        , 13  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN13       );
+REG64_FLD( C_LOCAL_FIR_IN14                                        , 14  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN14       );
+REG64_FLD( C_LOCAL_FIR_IN15                                        , 15  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN15       );
+REG64_FLD( C_LOCAL_FIR_IN16                                        , 16  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN16       );
+REG64_FLD( C_LOCAL_FIR_IN17                                        , 17  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN17       );
+REG64_FLD( C_LOCAL_FIR_IN18                                        , 18  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN18       );
+REG64_FLD( C_LOCAL_FIR_IN19                                        , 19  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN19       );
+REG64_FLD( C_LOCAL_FIR_IN20                                        , 20  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN20       );
+REG64_FLD( C_LOCAL_FIR_IN21                                        , 21  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN21       );
+REG64_FLD( C_LOCAL_FIR_IN22                                        , 22  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN22       );
+REG64_FLD( C_LOCAL_FIR_IN23                                        , 23  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN23       );
+REG64_FLD( C_LOCAL_FIR_IN24                                        , 24  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN24       );
+REG64_FLD( C_LOCAL_FIR_IN25                                        , 25  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN25       );
+REG64_FLD( C_LOCAL_FIR_IN26                                        , 26  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN26       );
+REG64_FLD( C_LOCAL_FIR_IN27                                        , 27  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN27       );
+REG64_FLD( C_LOCAL_FIR_IN28                                        , 28  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN28       );
+REG64_FLD( C_LOCAL_FIR_IN29                                        , 29  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN29       );
+REG64_FLD( C_LOCAL_FIR_IN30                                        , 30  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN30       );
+REG64_FLD( C_LOCAL_FIR_IN31                                        , 31  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN31       );
+REG64_FLD( C_LOCAL_FIR_IN32                                        , 32  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN32       );
+REG64_FLD( C_LOCAL_FIR_IN33                                        , 33  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN33       );
+REG64_FLD( C_LOCAL_FIR_IN34                                        , 34  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN34       );
+REG64_FLD( C_LOCAL_FIR_IN35                                        , 35  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN35       );
+REG64_FLD( C_LOCAL_FIR_IN36                                        , 36  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN36       );
+REG64_FLD( C_LOCAL_FIR_IN37                                        , 37  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN37       );
+REG64_FLD( C_LOCAL_FIR_IN38                                        , 38  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN38       );
+REG64_FLD( C_LOCAL_FIR_IN39                                        , 39  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN39       );
+REG64_FLD( C_LOCAL_FIR_IN40                                        , 40  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN40       );
+REG64_FLD( C_LOCAL_FIR_IN41                                        , 41  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IN41       );
+
+REG64_FLD( EQ_LOCAL_FIR_ACTION0_IN                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( EQ_LOCAL_FIR_ACTION0_IN_LEN                             , 42  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( EX_LOCAL_FIR_ACTION0_IN                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( EX_LOCAL_FIR_ACTION0_IN_LEN                             , 42  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( C_LOCAL_FIR_ACTION0_IN                                  , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( C_LOCAL_FIR_ACTION0_IN_LEN                              , 42  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( EQ_LOCAL_FIR_ACTION1_IN                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( EQ_LOCAL_FIR_ACTION1_IN_LEN                             , 42  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( EX_LOCAL_FIR_ACTION1_IN                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( EX_LOCAL_FIR_ACTION1_IN_LEN                             , 42  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( C_LOCAL_FIR_ACTION1_IN                                  , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( C_LOCAL_FIR_ACTION1_IN_LEN                              , 42  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( EQ_LOCAL_FIR_MASK_LFIR_IN                               , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_LFIR_IN    );
+REG64_FLD( EQ_LOCAL_FIR_MASK_LFIR_IN_LEN                           , 42  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_LFIR_IN_LEN );
+
+REG64_FLD( EX_LOCAL_FIR_MASK_LFIR_IN                               , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_LFIR_IN    );
+REG64_FLD( EX_LOCAL_FIR_MASK_LFIR_IN_LEN                           , 42  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_LFIR_IN_LEN );
+
+REG64_FLD( C_LOCAL_FIR_MASK_LFIR_IN                                , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_LFIR_IN    );
+REG64_FLD( C_LOCAL_FIR_MASK_LFIR_IN_LEN                            , 42  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_LFIR_IN_LEN );
+
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN0                                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN0        );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN1                                  , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN1        );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN2                                  , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN2        );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN3                                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN3        );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN4                                  , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN4        );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN5                                  , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN5        );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN6                                  , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN6        );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN7                                  , 7   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN7        );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN8                                  , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN8        );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN9                                  , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN9        );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN10                                 , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN10       );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN11                                 , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN11       );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN12                                 , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN12       );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN13                                 , 13  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN13       );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN14                                 , 14  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN14       );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN15                                 , 15  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN15       );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN16                                 , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN16       );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN17                                 , 17  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN17       );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN18                                 , 18  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN18       );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN19                                 , 19  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN19       );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN20                                 , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN20       );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN21                                 , 21  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN21       );
+REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN22                                 , 22  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN22       );
+
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN0                                  , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN0        );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN1                                  , 1   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN1        );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN2                                  , 2   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN2        );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN3                                  , 3   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN3        );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN4                                  , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN4        );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN5                                  , 5   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN5        );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN6                                  , 6   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN6        );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN7                                  , 7   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN7        );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN8                                  , 8   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN8        );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN9                                  , 9   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN9        );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN10                                 , 10  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN10       );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN11                                 , 11  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN11       );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN12                                 , 12  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN12       );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN13                                 , 13  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN13       );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN14                                 , 14  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN14       );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN15                                 , 15  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN15       );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN16                                 , 16  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN16       );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN17                                 , 17  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN17       );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN18                                 , 18  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN18       );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN19                                 , 19  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN19       );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN20                                 , 20  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN20       );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN21                                 , 21  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN21       );
+REG64_FLD( EX_LOCAL_XSTOP_ERR_IN22                                 , 22  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN22       );
+
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN0                                   , 0   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN0        );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN1                                   , 1   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN1        );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN2                                   , 2   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN2        );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN3                                   , 3   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN3        );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN4                                   , 4   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN4        );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN5                                   , 5   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN5        );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN6                                   , 6   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN6        );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN7                                   , 7   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN7        );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN8                                   , 8   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN8        );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN9                                   , 9   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN9        );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN10                                  , 10  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN10       );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN11                                  , 11  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN11       );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN12                                  , 12  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN12       );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN13                                  , 13  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN13       );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN14                                  , 14  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN14       );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN15                                  , 15  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN15       );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN16                                  , 16  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN16       );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN17                                  , 17  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN17       );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN18                                  , 18  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN18       );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN19                                  , 19  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN19       );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN20                                  , 20  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN20       );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN21                                  , 21  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN21       );
+REG64_FLD( C_LOCAL_XSTOP_ERR_IN22                                  , 22  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IN22       );
+
+REG64_FLD( EQ_LOCAL_XSTOP_MASK_IN                                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( EQ_LOCAL_XSTOP_MASK_IN_LEN                              , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( EX_LOCAL_XSTOP_MASK_IN                                  , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( EX_LOCAL_XSTOP_MASK_IN_LEN                              , 22  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( C_LOCAL_XSTOP_MASK_IN                                   , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( C_LOCAL_XSTOP_MASK_IN_LEN                               , 22  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( EQ_LRU_VIC_ALLOC_REG_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG   , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG );
+REG64_FLD( EQ_LRU_VIC_ALLOC_REG_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG_LEN , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG_LEN );
+REG64_FLD( EQ_LRU_VIC_ALLOC_REG_L3_COLUMN_MD_CFG                   , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_COLUMN_MD_CFG );
+REG64_FLD( EQ_LRU_VIC_ALLOC_REG_L3_COLUMN_MD_CFG_LEN               , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_COLUMN_MD_CFG_LEN );
+
+REG64_FLD( EX_L3_LRU_VIC_ALLOC_REG_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG );
+REG64_FLD( EX_L3_LRU_VIC_ALLOC_REG_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG_LEN , 20  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG_LEN );
+REG64_FLD( EX_L3_LRU_VIC_ALLOC_REG_L3_COLUMN_MD_CFG                , 20  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_COLUMN_MD_CFG );
+REG64_FLD( EX_L3_LRU_VIC_ALLOC_REG_L3_COLUMN_MD_CFG_LEN            , 2   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_COLUMN_MD_CFG_LEN );
+
+REG64_FLD( EQ_MIB_XIICAC_ICACHE_TAG_ADDR                           , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR );
+REG64_FLD( EQ_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                       , 27  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR_LEN );
+REG64_FLD( EQ_MIB_XIICAC_ICACHE_ERR                                , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_ERR );
+REG64_FLD( EQ_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING                  , 35  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IFETCH_PENDING );
+REG64_FLD( EQ_MIB_XIICAC_ICACHE_VALID                              , 36  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID );
+REG64_FLD( EQ_MIB_XIICAC_ICACHE_VALID_LEN                          , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID_LEN );
+
+REG64_FLD( EX_MIB_XIICAC_ICACHE_TAG_ADDR                           , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR );
+REG64_FLD( EX_MIB_XIICAC_ICACHE_TAG_ADDR_LEN                       , 27  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR_LEN );
+REG64_FLD( EX_MIB_XIICAC_ICACHE_ERR                                , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_ERR );
+REG64_FLD( EX_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING                  , 35  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IFETCH_PENDING );
+REG64_FLD( EX_MIB_XIICAC_ICACHE_VALID                              , 36  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID );
+REG64_FLD( EX_MIB_XIICAC_ICACHE_VALID_LEN                          , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID_LEN );
+
+REG64_FLD( EQ_MIB_XIMEM_MEM_ADDR                                   , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR   );
+REG64_FLD( EQ_MIB_XIMEM_MEM_ADDR_LEN                               , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR_LEN );
+REG64_FLD( EQ_MIB_XIMEM_MEM_R_NW                                   , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_R_NW   );
+REG64_FLD( EQ_MIB_XIMEM_MEM_BUSY                                   , 33  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BUSY   );
+REG64_FLD( EQ_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING                , 34  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( EQ_MIB_XIMEM_MEM_BYTE_ENABLE                            , 35  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE );
+REG64_FLD( EQ_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                        , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE_LEN );
+REG64_FLD( EQ_MIB_XIMEM_MEM_LINE_MODE                              , 43  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_LINE_MODE );
+REG64_FLD( EQ_MIB_XIMEM_MEM_ERROR                                  , 49  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR  );
+REG64_FLD( EQ_MIB_XIMEM_MEM_ERROR_LEN                              , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR_LEN );
+REG64_FLD( EQ_MIB_XIMEM_MEM_IFETCH_PENDING                         , 62  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IFETCH_PENDING );
+REG64_FLD( EQ_MIB_XIMEM_MEM_DATAOP_PENDING                         , 63  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_DATAOP_PENDING );
+
+REG64_FLD( EX_MIB_XIMEM_MEM_ADDR                                   , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR   );
+REG64_FLD( EX_MIB_XIMEM_MEM_ADDR_LEN                               , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR_LEN );
+REG64_FLD( EX_MIB_XIMEM_MEM_R_NW                                   , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_R_NW   );
+REG64_FLD( EX_MIB_XIMEM_MEM_BUSY                                   , 33  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BUSY   );
+REG64_FLD( EX_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING                , 34  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( EX_MIB_XIMEM_MEM_BYTE_ENABLE                            , 35  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE );
+REG64_FLD( EX_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                        , 8   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE_LEN );
+REG64_FLD( EX_MIB_XIMEM_MEM_LINE_MODE                              , 43  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_LINE_MODE );
+REG64_FLD( EX_MIB_XIMEM_MEM_ERROR                                  , 49  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR  );
+REG64_FLD( EX_MIB_XIMEM_MEM_ERROR_LEN                              , 3   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR_LEN );
+REG64_FLD( EX_MIB_XIMEM_MEM_IFETCH_PENDING                         , 62  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IFETCH_PENDING );
+REG64_FLD( EX_MIB_XIMEM_MEM_DATAOP_PENDING                         , 63  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_DATAOP_PENDING );
+
+REG64_FLD( EQ_MIB_XISGB_STORE_ADDRESS                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS );
+REG64_FLD( EQ_MIB_XISGB_STORE_ADDRESS_LEN                          , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS_LEN );
+REG64_FLD( EQ_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING          , 35  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( EQ_MIB_XISGB_SGB_BYTE_VALID                             , 36  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID );
+REG64_FLD( EQ_MIB_XISGB_SGB_BYTE_VALID_LEN                         , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID_LEN );
+REG64_FLD( EQ_MIB_XISGB_SGB_FLUSH_PENDING                          , 63  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_FLUSH_PENDING );
+
+REG64_FLD( EX_MIB_XISGB_STORE_ADDRESS                              , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS );
+REG64_FLD( EX_MIB_XISGB_STORE_ADDRESS_LEN                          , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS_LEN );
+REG64_FLD( EX_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING          , 35  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( EX_MIB_XISGB_SGB_BYTE_VALID                             , 36  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID );
+REG64_FLD( EX_MIB_XISGB_SGB_BYTE_VALID_LEN                         , 4   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID_LEN );
+REG64_FLD( EX_MIB_XISGB_SGB_FLUSH_PENDING                          , 63  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_FLUSH_PENDING );
+
+REG64_FLD( EQ_MODE_REG_IN0                                         , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( EQ_MODE_REG_IN1                                         , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN1        );
+REG64_FLD( EQ_MODE_REG_IN2                                         , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN2        );
+REG64_FLD( EQ_MODE_REG_IN3                                         , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN3        );
+REG64_FLD( EQ_MODE_REG_IN4                                         , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( EQ_MODE_REG_IN5                                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( EQ_MODE_REG_IN6                                         , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN6        );
+REG64_FLD( EQ_MODE_REG_IN7                                         , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN7        );
+REG64_FLD( EQ_MODE_REG_IN8                                         , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN8        );
+REG64_FLD( EQ_MODE_REG_IN9                                         , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN9        );
+REG64_FLD( EQ_MODE_REG_IN10                                        , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN10       );
+REG64_FLD( EQ_MODE_REG_IN11                                        , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN11       );
+REG64_FLD( EQ_MODE_REG_IN                                          , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( EQ_MODE_REG_IN_LEN                                      , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( EX_MODE_REG_IN0                                         , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( EX_MODE_REG_IN1                                         , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN1        );
+REG64_FLD( EX_MODE_REG_IN2                                         , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN2        );
+REG64_FLD( EX_MODE_REG_IN3                                         , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN3        );
+REG64_FLD( EX_MODE_REG_IN4                                         , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( EX_MODE_REG_IN5                                         , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( EX_MODE_REG_IN6                                         , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN6        );
+REG64_FLD( EX_MODE_REG_IN7                                         , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN7        );
+REG64_FLD( EX_MODE_REG_IN8                                         , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN8        );
+REG64_FLD( EX_MODE_REG_IN9                                         , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN9        );
+REG64_FLD( EX_MODE_REG_IN10                                        , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN10       );
+REG64_FLD( EX_MODE_REG_IN11                                        , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN11       );
+REG64_FLD( EX_MODE_REG_IN                                          , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( EX_MODE_REG_IN_LEN                                      , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( C_MODE_REG_IN0                                          , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( C_MODE_REG_IN1                                          , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN1        );
+REG64_FLD( C_MODE_REG_IN2                                          , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN2        );
+REG64_FLD( C_MODE_REG_IN3                                          , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN3        );
+REG64_FLD( C_MODE_REG_IN4                                          , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( C_MODE_REG_IN5                                          , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( C_MODE_REG_IN6                                          , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN6        );
+REG64_FLD( C_MODE_REG_IN7                                          , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN7        );
+REG64_FLD( C_MODE_REG_IN8                                          , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN8        );
+REG64_FLD( C_MODE_REG_IN9                                          , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN9        );
+REG64_FLD( C_MODE_REG_IN10                                         , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN10       );
+REG64_FLD( C_MODE_REG_IN11                                         , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN11       );
+REG64_FLD( C_MODE_REG_IN                                           , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( C_MODE_REG_IN_LEN                                       , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( EQ_MODE_REG0_L3_DISABLED_CFG                            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DISABLED_CFG );
+REG64_FLD( EQ_MODE_REG0_L3_DMAP_CI_EN_CFG                          , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DMAP_CI_EN_CFG );
+REG64_FLD( EQ_MODE_REG0_L3_RDSN_LINEDEL_UE_EN                      , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_RDSN_LINEDEL_UE_EN );
+REG64_FLD( EQ_MODE_REG0_L3_NO_ALLOCATE_EN                          , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_NO_ALLOCATE_EN );
+REG64_FLD( EQ_MODE_REG0_L3_NO_ALLOCATE_ACTIVE                      , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_NO_ALLOCATE_ACTIVE );
+REG64_FLD( EQ_MODE_REG0_L3_SPARE5                                  , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SPARE5  );
+REG64_FLD( EQ_MODE_REG0_L3_SPARE6                                  , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SPARE6  );
+REG64_FLD( EQ_MODE_REG0_L3_SPARE7                                  , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SPARE7  );
+REG64_FLD( EQ_MODE_REG0_L3_LCO_RTY_LIMIT_DISABLE                   , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_RTY_LIMIT_DISABLE );
+REG64_FLD( EQ_MODE_REG0_L3_DYN_LCO_BLK_DIS_CFG                     , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DYN_LCO_BLK_DIS_CFG );
+REG64_FLD( EQ_MODE_REG0_L3_LCO_ADDR_TGT_ENABLE                     , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_ADDR_TGT_ENABLE );
+REG64_FLD( EQ_MODE_REG0_L3_ADDR_HASH_EN_CFG                        , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_ADDR_HASH_EN_CFG );
+REG64_FLD( EQ_MODE_REG0_L3CERRS_CFG_DCACHE_CAPP                    , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3CERRS_CFG_DCACHE_CAPP );
+REG64_FLD( EQ_MODE_REG0_L3CERRS_LCO_RETRY_THROTL_DIS               , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3CERRS_LCO_RETRY_THROTL_DIS );
+REG64_FLD( EQ_MODE_REG0_L3_HANG_POLL_PULSE_DIV                     , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_HANG_POLL_PULSE_DIV );
+REG64_FLD( EQ_MODE_REG0_L3_HANG_POLL_PULSE_DIV_LEN                 , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_HANG_POLL_PULSE_DIV_LEN );
+REG64_FLD( EQ_MODE_REG0_L3_DATA_POLL_PULSE_DIV                     , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DATA_POLL_PULSE_DIV );
+REG64_FLD( EQ_MODE_REG0_L3_DATA_POLL_PULSE_DIV_LEN                 , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DATA_POLL_PULSE_DIV_LEN );
+REG64_FLD( EQ_MODE_REG0_L3_SYSMAP_SM_NOT_LG_SEL                    , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SYSMAP_SM_NOT_LG_SEL );
+
+REG64_FLD( EX_L2_MODE_REG0_CFG_LRU_DIRECT_MAP                      , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LRU_DIRECT_MAP );
+REG64_FLD( EX_L2_MODE_REG0_CFG_RANDOM_EN                           , 1   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_RANDOM_EN );
+REG64_FLD( EX_L2_MODE_REG0_CFG_SINGLE_MEM_EN                       , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SINGLE_MEM_EN );
+REG64_FLD( EX_L2_MODE_REG0_CFG_SINGLE_MEM                          , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SINGLE_MEM );
+REG64_FLD( EX_L2_MODE_REG0_CFG_SINGLE_MEM_LEN                      , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SINGLE_MEM_LEN );
+REG64_FLD( EX_L2_MODE_REG0_CFG_L3_DIS                              , 11  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_L3_DIS );
+REG64_FLD( EX_L2_MODE_REG0_CFG_CO_SOFT_PURGE_ME_SX_EN              , 12  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_CO_SOFT_PURGE_ME_SX_EN );
+REG64_FLD( EX_L2_MODE_REG0_CFG_CO_SOFT_PURGE_ALL_LINES_EN          , 13  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_CO_SOFT_PURGE_ALL_LINES_EN );
+REG64_FLD( EX_L2_MODE_REG0_CFG_DCBZ_TRASHMODE_EN                   , 14  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DCBZ_TRASHMODE_EN );
+REG64_FLD( EX_L2_MODE_REG0_CFG_CAC_ERR_REPAIR_EN                   , 15  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_CAC_ERR_REPAIR_EN );
+REG64_FLD( EX_L2_MODE_REG0_CFG_LINEDEL_ON_CAC_UE_EN                , 16  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_LINEDEL_ON_CAC_UE_EN );
+REG64_FLD( EX_L2_MODE_REG0_CFG_HW_TRIG_LINEDEL_LDDISP_CE_EN        , 17  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_HW_TRIG_LINEDEL_LDDISP_CE_EN );
+REG64_FLD( EX_L2_MODE_REG0_CFG_C0_L2_PB_ARB_RATE_SEL               , 18  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL );
+REG64_FLD( EX_L2_MODE_REG0_CFG_C0_L2_PB_ARB_RATE_SEL_LEN           , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL_LEN );
+REG64_FLD( EX_L2_MODE_REG0_CFG_HASH_L3_ADDR_EN                     , 21  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_HASH_L3_ADDR_EN );
+REG64_FLD( EX_L2_MODE_REG0_CFG_RC_FRC_DISP_EQ_NTM_INIG_SI_TO_RCR_EN , 22  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_RC_FRC_DISP_EQ_NTM_INIG_SI_TO_RCR_EN );
+REG64_FLD( EX_L2_MODE_REG0_CFG_SYSMAP_SM_NOT_LG_SEL                , 23  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_SYSMAP_SM_NOT_LG_SEL );
+REG64_FLD( EX_L2_MODE_REG0_CFG_Q_BIT_TID_MASK                      , 24  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_Q_BIT_TID_MASK );
+REG64_FLD( EX_L2_MODE_REG0_CFG_Q_BIT_TID_MASK_LEN                  , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_Q_BIT_TID_MASK_LEN );
+REG64_FLD( EX_L2_MODE_REG0_CFG_STQ_PF_EN                           , 32  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_STQ_PF_EN );
+REG64_FLD( EX_L2_MODE_REG0_CFG_DCACHE_CAPP_LPC_EN                  , 33  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DCACHE_CAPP_LPC_EN );
+REG64_FLD( EX_L2_MODE_REG0_CFG_PERFMON_INFO_SRC_ED_SEL             , 34  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PERFMON_INFO_SRC_ED_SEL );
+REG64_FLD( EX_L2_MODE_REG0_CFG_C1_L2_PB_ARB_RATE_SEL               , 35  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL );
+REG64_FLD( EX_L2_MODE_REG0_CFG_C1_L2_PB_ARB_RATE_SEL_LEN           , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL_LEN );
+
+REG64_FLD( EX_L3_MODE_REG0_L3_DISABLED_CFG                         , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_DISABLED_CFG );
+REG64_FLD( EX_L3_MODE_REG0_L3_DMAP_CI_EN_CFG                       , 1   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_DMAP_CI_EN_CFG );
+REG64_FLD( EX_L3_MODE_REG0_L3_RDSN_LINEDEL_UE_EN                   , 2   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_RDSN_LINEDEL_UE_EN );
+REG64_FLD( EX_L3_MODE_REG0_L3_NO_ALLOCATE_EN                       , 3   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_NO_ALLOCATE_EN );
+REG64_FLD( EX_L3_MODE_REG0_L3_NO_ALLOCATE_ACTIVE                   , 4   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_NO_ALLOCATE_ACTIVE );
+REG64_FLD( EX_L3_MODE_REG0_L3_SPARE5                               , 5   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_SPARE5  );
+REG64_FLD( EX_L3_MODE_REG0_L3_SPARE6                               , 6   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_SPARE6  );
+REG64_FLD( EX_L3_MODE_REG0_L3_SPARE7                               , 7   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_SPARE7  );
+REG64_FLD( EX_L3_MODE_REG0_L3_LCO_RTY_LIMIT_DISABLE                , 8   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_RTY_LIMIT_DISABLE );
+REG64_FLD( EX_L3_MODE_REG0_L3_DYN_LCO_BLK_DIS_CFG                  , 9   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_DYN_LCO_BLK_DIS_CFG );
+REG64_FLD( EX_L3_MODE_REG0_L3_LCO_ADDR_TGT_ENABLE                  , 10  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_ADDR_TGT_ENABLE );
+REG64_FLD( EX_L3_MODE_REG0_L3_ADDR_HASH_EN_CFG                     , 11  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_ADDR_HASH_EN_CFG );
+REG64_FLD( EX_L3_MODE_REG0_L3CERRS_CFG_DCACHE_CAPP                 , 12  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3CERRS_CFG_DCACHE_CAPP );
+REG64_FLD( EX_L3_MODE_REG0_L3CERRS_LCO_RETRY_THROTL_DIS            , 13  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3CERRS_LCO_RETRY_THROTL_DIS );
+REG64_FLD( EX_L3_MODE_REG0_L3_HANG_POLL_PULSE_DIV                  , 14  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_HANG_POLL_PULSE_DIV );
+REG64_FLD( EX_L3_MODE_REG0_L3_HANG_POLL_PULSE_DIV_LEN              , 4   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_HANG_POLL_PULSE_DIV_LEN );
+REG64_FLD( EX_L3_MODE_REG0_L3_DATA_POLL_PULSE_DIV                  , 18  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_DATA_POLL_PULSE_DIV );
+REG64_FLD( EX_L3_MODE_REG0_L3_DATA_POLL_PULSE_DIV_LEN              , 4   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_DATA_POLL_PULSE_DIV_LEN );
+REG64_FLD( EX_L3_MODE_REG0_L3_SYSMAP_SM_NOT_LG_SEL                 , 22  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_SYSMAP_SM_NOT_LG_SEL );
+
+REG64_FLD( EQ_MODE_REG1_L3_LCO_ENABLE_CFG                          , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_ENABLE_CFG );
+REG64_FLD( EQ_MODE_REG1_L3_LCO_TARGET_GROUP                        , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_TARGET_GROUP );
+REG64_FLD( EQ_MODE_REG1_L3_LCO_TARGET_ID                           , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_TARGET_ID );
+REG64_FLD( EQ_MODE_REG1_L3_LCO_TARGET_ID_LEN                       , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_TARGET_ID_LEN );
+REG64_FLD( EQ_MODE_REG1_L3_LCO_TARGET_VICTIMS                      , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_TARGET_VICTIMS );
+REG64_FLD( EQ_MODE_REG1_L3_LCO_TARGET_VICTIMS_LEN                  , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_TARGET_VICTIMS_LEN );
+REG64_FLD( EQ_MODE_REG1_L3_SCOM_CINJ_LCO_DIS                       , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_SCOM_CINJ_LCO_DIS );
+
+REG64_FLD( EX_L2_MODE_REG1_CFG_ECCCK_CE_UE_SUE_ERR_DET_DIS         , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_ECCCK_CE_UE_SUE_ERR_DET_DIS );
+REG64_FLD( EX_L2_MODE_REG1_CFG_ECCCK_UE_SUE_DET_DIS                , 1   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CFG_ECCCK_UE_SUE_DET_DIS );
+REG64_FLD( EX_L2_MODE_REG1_HANG_POLL_PULSE_DIV                     , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_HANG_POLL_PULSE_DIV );
+REG64_FLD( EX_L2_MODE_REG1_HANG_POLL_PULSE_DIV_LEN                 , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_HANG_POLL_PULSE_DIV_LEN );
+REG64_FLD( EX_L2_MODE_REG1_DATA_POLL_PULSE_DIV                     , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_DATA_POLL_PULSE_DIV );
+REG64_FLD( EX_L2_MODE_REG1_DATA_POLL_PULSE_DIV_LEN                 , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_DATA_POLL_PULSE_DIV_LEN );
+REG64_FLD( EX_L2_MODE_REG1_PM03_SMT_ROTATION_DIS                   , 16  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_PM03_SMT_ROTATION_DIS );
+REG64_FLD( EX_L2_MODE_REG1_PM47_SMT_ROTATION_DIS                   , 17  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_PM47_SMT_ROTATION_DIS );
+REG64_FLD( EX_L2_MODE_REG1_PM07_TID_ROTATE_PLSS_RATE               , 20  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_PM07_TID_ROTATE_PLSS_RATE );
+REG64_FLD( EX_L2_MODE_REG1_PM07_TID_ROTATE_PLSS_RATE_LEN           , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_PM07_TID_ROTATE_PLSS_RATE_LEN );
+REG64_FLD( EX_L2_MODE_REG1_PM03_L23_EVENT_TID_SEL_EN               , 25  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_PM03_L23_EVENT_TID_SEL_EN );
+REG64_FLD( EX_L2_MODE_REG1_PM03_L23_EVENT_TID_SEL_NUM              , 26  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_PM03_L23_EVENT_TID_SEL_NUM );
+REG64_FLD( EX_L2_MODE_REG1_PM03_L23_EVENT_TID_SEL_NUM_LEN          , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_PM03_L23_EVENT_TID_SEL_NUM_LEN );
+REG64_FLD( EX_L2_MODE_REG1_PM47_L23_EVENT_TID_SEL_EN               , 29  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_PM47_L23_EVENT_TID_SEL_EN );
+REG64_FLD( EX_L2_MODE_REG1_PM47_L23_EVENT_TID_SEL_NUM              , 30  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_PM47_L23_EVENT_TID_SEL_NUM );
+REG64_FLD( EX_L2_MODE_REG1_PM47_L23_EVENT_TID_SEL_NUM_LEN          , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_PM47_L23_EVENT_TID_SEL_NUM_LEN );
+
+REG64_FLD( EX_L3_MODE_REG1_L3_LCO_ENABLE_CFG                       , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_ENABLE_CFG );
+REG64_FLD( EX_L3_MODE_REG1_L3_LCO_TARGET_GROUP                     , 1   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_TARGET_GROUP );
+REG64_FLD( EX_L3_MODE_REG1_L3_LCO_TARGET_ID                        , 2   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_TARGET_ID );
+REG64_FLD( EX_L3_MODE_REG1_L3_LCO_TARGET_ID_LEN                    , 4   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_TARGET_ID_LEN );
+REG64_FLD( EX_L3_MODE_REG1_L3_LCO_TARGET_VICTIMS                   , 6   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_TARGET_VICTIMS );
+REG64_FLD( EX_L3_MODE_REG1_L3_LCO_TARGET_VICTIMS_LEN               , 16  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_LCO_TARGET_VICTIMS_LEN );
+REG64_FLD( EX_L3_MODE_REG1_L3_SCOM_CINJ_LCO_DIS                    , 22  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_SCOM_CINJ_LCO_DIS );
+
+REG64_FLD( EQ_MULTICAST_GROUP_1_MULTICAST1                         , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST1 );
+REG64_FLD( EQ_MULTICAST_GROUP_1_MULTICAST1_LEN                     , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST1_LEN );
+
+REG64_FLD( EX_MULTICAST_GROUP_1_MULTICAST1                         , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST1 );
+REG64_FLD( EX_MULTICAST_GROUP_1_MULTICAST1_LEN                     , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST1_LEN );
+
+REG64_FLD( C_MULTICAST_GROUP_1_MULTICAST1                          , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST1 );
+REG64_FLD( C_MULTICAST_GROUP_1_MULTICAST1_LEN                      , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST1_LEN );
+
+REG64_FLD( EQ_MULTICAST_GROUP_2_MULTICAST2                         , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST2 );
+REG64_FLD( EQ_MULTICAST_GROUP_2_MULTICAST2_LEN                     , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST2_LEN );
+
+REG64_FLD( EX_MULTICAST_GROUP_2_MULTICAST2                         , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST2 );
+REG64_FLD( EX_MULTICAST_GROUP_2_MULTICAST2_LEN                     , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST2_LEN );
+
+REG64_FLD( C_MULTICAST_GROUP_2_MULTICAST2                          , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST2 );
+REG64_FLD( C_MULTICAST_GROUP_2_MULTICAST2_LEN                      , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST2_LEN );
+
+REG64_FLD( EQ_MULTICAST_GROUP_3_MULTICAST3                         , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST3 );
+REG64_FLD( EQ_MULTICAST_GROUP_3_MULTICAST3_LEN                     , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST3_LEN );
+
+REG64_FLD( EX_MULTICAST_GROUP_3_MULTICAST3                         , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST3 );
+REG64_FLD( EX_MULTICAST_GROUP_3_MULTICAST3_LEN                     , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST3_LEN );
+
+REG64_FLD( C_MULTICAST_GROUP_3_MULTICAST3                          , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST3 );
+REG64_FLD( C_MULTICAST_GROUP_3_MULTICAST3_LEN                      , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST3_LEN );
+
+REG64_FLD( EQ_MULTICAST_GROUP_4_MULTICAST4                         , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST4 );
+REG64_FLD( EQ_MULTICAST_GROUP_4_MULTICAST4_LEN                     , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST4_LEN );
+
+REG64_FLD( EX_MULTICAST_GROUP_4_MULTICAST4                         , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST4 );
+REG64_FLD( EX_MULTICAST_GROUP_4_MULTICAST4_LEN                     , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST4_LEN );
+
+REG64_FLD( C_MULTICAST_GROUP_4_MULTICAST4                          , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST4 );
+REG64_FLD( C_MULTICAST_GROUP_4_MULTICAST4_LEN                      , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MULTICAST4_LEN );
+
+REG64_FLD( EQ_NCU_DARN_BAR_REG_EN                                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EN         );
+REG64_FLD( EQ_NCU_DARN_BAR_REG_ADDR                                , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ADDR       );
+REG64_FLD( EQ_NCU_DARN_BAR_REG_ADDR_LEN                            , 44  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_LEN   );
+
+REG64_FLD( EX_NCU_DARN_BAR_REG_EN                                  , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_EN         );
+REG64_FLD( EX_NCU_DARN_BAR_REG_ADDR                                , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ADDR       );
+REG64_FLD( EX_NCU_DARN_BAR_REG_ADDR_LEN                            , 44  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_LEN   );
+
+REG64_FLD( EQ_NCU_MODE_REG_HTM_QUEUE_LIMIT                         , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_HTM_QUEUE_LIMIT );
+REG64_FLD( EQ_NCU_MODE_REG_HTM_QUEUE_LIMIT_LEN                     , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_HTM_QUEUE_LIMIT_LEN );
+REG64_FLD( EQ_NCU_MODE_REG_TRASH_EN                                , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRASH_EN   );
+REG64_FLD( EQ_NCU_MODE_REG_FENCE_TLBIE                             , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FENCE_TLBIE );
+REG64_FLD( EQ_NCU_MODE_REG_DROP_PRIORITY_MASK                      , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DROP_PRIORITY_MASK );
+REG64_FLD( EQ_NCU_MODE_REG_DROP_PRIORITY_MASK_LEN                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DROP_PRIORITY_MASK_LEN );
+REG64_FLD( EQ_NCU_MODE_REG_TLBI_GROUP_PUMP_EN                      , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBI_GROUP_PUMP_EN );
+REG64_FLD( EQ_NCU_MODE_REG_SLBI_GROUP_PUMP_EN                      , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SLBI_GROUP_PUMP_EN );
+REG64_FLD( EQ_NCU_MODE_REG_SYSMAP_SM_NOT_LG_SEL                    , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SYSMAP_SM_NOT_LG_SEL );
+REG64_FLD( EQ_NCU_MODE_REG_TLBIE_PACING_CNT_EN                     , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_PACING_CNT_EN );
+REG64_FLD( EQ_NCU_MODE_REG_TLBIE_DEC_RATE                          , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_DEC_RATE );
+REG64_FLD( EQ_NCU_MODE_REG_TLBIE_DEC_RATE_LEN                      , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_DEC_RATE_LEN );
+REG64_FLD( EQ_NCU_MODE_REG_TLBIE_INC_RATE                          , 19  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_INC_RATE );
+REG64_FLD( EQ_NCU_MODE_REG_TLBIE_INC_RATE_LEN                      , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_INC_RATE_LEN );
+REG64_FLD( EQ_NCU_MODE_REG_TLBIE_CNT_THRESH                        , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_CNT_THRESH );
+REG64_FLD( EQ_NCU_MODE_REG_TLBIE_CNT_THRESH_LEN                    , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_CNT_THRESH_LEN );
+REG64_FLD( EQ_NCU_MODE_REG_TLBIE_CNT_WT4TX_CORE_EN                 , 35  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_CNT_WT4TX_CORE_EN );
+REG64_FLD( EQ_NCU_MODE_REG_TLB_CHK_WAIT_DEC                        , 36  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_CHK_WAIT_DEC );
+REG64_FLD( EQ_NCU_MODE_REG_TLB_CHK_WAIT_DEC_LEN                    , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_CHK_WAIT_DEC_LEN );
+
+REG64_FLD( EX_NCU_MODE_REG_HTM_QUEUE_LIMIT                         , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_HTM_QUEUE_LIMIT );
+REG64_FLD( EX_NCU_MODE_REG_HTM_QUEUE_LIMIT_LEN                     , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_HTM_QUEUE_LIMIT_LEN );
+REG64_FLD( EX_NCU_MODE_REG_TRASH_EN                                , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRASH_EN   );
+REG64_FLD( EX_NCU_MODE_REG_FENCE_TLBIE                             , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FENCE_TLBIE );
+REG64_FLD( EX_NCU_MODE_REG_DROP_PRIORITY_MASK                      , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DROP_PRIORITY_MASK );
+REG64_FLD( EX_NCU_MODE_REG_DROP_PRIORITY_MASK_LEN                  , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DROP_PRIORITY_MASK_LEN );
+REG64_FLD( EX_NCU_MODE_REG_TLBI_GROUP_PUMP_EN                      , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBI_GROUP_PUMP_EN );
+REG64_FLD( EX_NCU_MODE_REG_SLBI_GROUP_PUMP_EN                      , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SLBI_GROUP_PUMP_EN );
+REG64_FLD( EX_NCU_MODE_REG_SYSMAP_SM_NOT_LG_SEL                    , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SYSMAP_SM_NOT_LG_SEL );
+REG64_FLD( EX_NCU_MODE_REG_TLBIE_PACING_CNT_EN                     , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_PACING_CNT_EN );
+REG64_FLD( EX_NCU_MODE_REG_TLBIE_DEC_RATE                          , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_DEC_RATE );
+REG64_FLD( EX_NCU_MODE_REG_TLBIE_DEC_RATE_LEN                      , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_DEC_RATE_LEN );
+REG64_FLD( EX_NCU_MODE_REG_TLBIE_INC_RATE                          , 19  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_INC_RATE );
+REG64_FLD( EX_NCU_MODE_REG_TLBIE_INC_RATE_LEN                      , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_INC_RATE_LEN );
+REG64_FLD( EX_NCU_MODE_REG_TLBIE_CNT_THRESH                        , 27  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_CNT_THRESH );
+REG64_FLD( EX_NCU_MODE_REG_TLBIE_CNT_THRESH_LEN                    , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_CNT_THRESH_LEN );
+REG64_FLD( EX_NCU_MODE_REG_TLBIE_CNT_WT4TX_CORE_EN                 , 35  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_CNT_WT4TX_CORE_EN );
+REG64_FLD( EX_NCU_MODE_REG_TLB_CHK_WAIT_DEC                        , 36  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_CHK_WAIT_DEC );
+REG64_FLD( EX_NCU_MODE_REG_TLB_CHK_WAIT_DEC_LEN                    , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_CHK_WAIT_DEC_LEN );
+
+REG64_FLD( EQ_NCU_MODE_REG2_HANG_POLL_PULSE_DIV                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_HANG_POLL_PULSE_DIV );
+REG64_FLD( EQ_NCU_MODE_REG2_HANG_POLL_PULSE_DIV_LEN                , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_HANG_POLL_PULSE_DIV_LEN );
+REG64_FLD( EQ_NCU_MODE_REG2_MASTER_CP_DATA_POLL_PULSE_DIV          , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV );
+REG64_FLD( EQ_NCU_MODE_REG2_MASTER_CP_DATA_POLL_PULSE_DIV_LEN      , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV_LEN );
+REG64_FLD( EQ_NCU_MODE_REG2_TLB_SNOOP_DATA_POLL_PULSE_DIV          , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV );
+REG64_FLD( EQ_NCU_MODE_REG2_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN      , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN );
+REG64_FLD( EQ_NCU_MODE_REG2_TLB_STG1_HANG_POLL_PULSE_DIV           , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV );
+REG64_FLD( EQ_NCU_MODE_REG2_TLB_STG1_HANG_POLL_PULSE_DIV_LEN       , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV_LEN );
+REG64_FLD( EQ_NCU_MODE_REG2_TLB_STG2_HANG_POLL_PULSE_DIV           , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV );
+REG64_FLD( EQ_NCU_MODE_REG2_TLB_STG2_HANG_POLL_PULSE_DIV_LEN       , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV_LEN );
+REG64_FLD( EQ_NCU_MODE_REG2_MASTER_TLB_DATA_POLL_PULSE_DIV         , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV );
+REG64_FLD( EQ_NCU_MODE_REG2_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN     , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN );
+
+REG64_FLD( EX_NCU_MODE_REG2_HANG_POLL_PULSE_DIV                    , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_HANG_POLL_PULSE_DIV );
+REG64_FLD( EX_NCU_MODE_REG2_HANG_POLL_PULSE_DIV_LEN                , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_HANG_POLL_PULSE_DIV_LEN );
+REG64_FLD( EX_NCU_MODE_REG2_MASTER_CP_DATA_POLL_PULSE_DIV          , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV );
+REG64_FLD( EX_NCU_MODE_REG2_MASTER_CP_DATA_POLL_PULSE_DIV_LEN      , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV_LEN );
+REG64_FLD( EX_NCU_MODE_REG2_TLB_SNOOP_DATA_POLL_PULSE_DIV          , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV );
+REG64_FLD( EX_NCU_MODE_REG2_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN      , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN );
+REG64_FLD( EX_NCU_MODE_REG2_TLB_STG1_HANG_POLL_PULSE_DIV           , 18  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV );
+REG64_FLD( EX_NCU_MODE_REG2_TLB_STG1_HANG_POLL_PULSE_DIV_LEN       , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV_LEN );
+REG64_FLD( EX_NCU_MODE_REG2_TLB_STG2_HANG_POLL_PULSE_DIV           , 22  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV );
+REG64_FLD( EX_NCU_MODE_REG2_TLB_STG2_HANG_POLL_PULSE_DIV_LEN       , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV_LEN );
+REG64_FLD( EX_NCU_MODE_REG2_MASTER_TLB_DATA_POLL_PULSE_DIV         , 26  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV );
+REG64_FLD( EX_NCU_MODE_REG2_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN     , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN );
+
+REG64_FLD( EQ_NCU_MODE_REG3_TLBIE_STALL_EN                         , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_EN );
+REG64_FLD( EQ_NCU_MODE_REG3_TLBIE_STALL_THRESHOLD                  , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_THRESHOLD );
+REG64_FLD( EQ_NCU_MODE_REG3_TLBIE_STALL_THRESHOLD_LEN              , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_THRESHOLD_LEN );
+REG64_FLD( EQ_NCU_MODE_REG3_TLBIE_STALL_CMPLT_CNT                  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_CMPLT_CNT );
+REG64_FLD( EQ_NCU_MODE_REG3_TLBIE_STALL_CMPLT_CNT_LEN              , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_CMPLT_CNT_LEN );
+REG64_FLD( EQ_NCU_MODE_REG3_TLBIE_STALL_DELAY_CNT                  , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_DELAY_CNT );
+REG64_FLD( EQ_NCU_MODE_REG3_TLBIE_STALL_DELAY_CNT_LEN              , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_DELAY_CNT_LEN );
+
+REG64_FLD( EX_NCU_MODE_REG3_TLBIE_STALL_EN                         , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_EN );
+REG64_FLD( EX_NCU_MODE_REG3_TLBIE_STALL_THRESHOLD                  , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_THRESHOLD );
+REG64_FLD( EX_NCU_MODE_REG3_TLBIE_STALL_THRESHOLD_LEN              , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_THRESHOLD_LEN );
+REG64_FLD( EX_NCU_MODE_REG3_TLBIE_STALL_CMPLT_CNT                  , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_CMPLT_CNT );
+REG64_FLD( EX_NCU_MODE_REG3_TLBIE_STALL_CMPLT_CNT_LEN              , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_CMPLT_CNT_LEN );
+REG64_FLD( EX_NCU_MODE_REG3_TLBIE_STALL_DELAY_CNT                  , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_DELAY_CNT );
+REG64_FLD( EX_NCU_MODE_REG3_TLBIE_STALL_DELAY_CNT_LEN              , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TLBIE_STALL_DELAY_CNT_LEN );
+
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY8_VALID                      , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY8_VALID );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY8_ID                         , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY8_ID  );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY8_ID_LEN                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY8_ID_LEN );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY7_VALID                      , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY7_VALID );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY7_ID                         , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY7_ID  );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY7_ID_LEN                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY7_ID_LEN );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY6_VALID                      , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY6_VALID );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY6_ID                         , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY6_ID  );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY6_ID_LEN                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY6_ID_LEN );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY5_VALID                      , 39  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY5_VALID );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY5_ID                         , 40  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY5_ID  );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY5_ID_LEN                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY5_ID_LEN );
+
+REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY8_VALID                      , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY8_VALID );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY8_ID                         , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY8_ID  );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY8_ID_LEN                     , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY8_ID_LEN );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY7_VALID                      , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY7_VALID );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY7_ID                         , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY7_ID  );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY7_ID_LEN                     , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY7_ID_LEN );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY6_VALID                      , 26  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY6_VALID );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY6_ID                         , 27  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY6_ID  );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY6_ID_LEN                     , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY6_ID_LEN );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY5_VALID                      , 39  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY5_VALID );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY5_ID                         , 40  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY5_ID  );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY5_ID_LEN                     , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY5_ID_LEN );
+
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY4_VALID                      , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY4_VALID );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY4_ID                         , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY4_ID  );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY4_ID_LEN                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY4_ID_LEN );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY3_VALID                      , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY3_VALID );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY3_ID                         , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY3_ID  );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY3_ID_LEN                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY3_ID_LEN );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY2_VALID                      , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY2_VALID );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY2_ID                         , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY2_ID  );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY2_ID_LEN                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY2_ID_LEN );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY1_VALID                      , 39  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY1_VALID );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY1_ID                         , 40  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY1_ID  );
+REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY1_ID_LEN                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY1_ID_LEN );
+
+REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY4_VALID                      , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY4_VALID );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY4_ID                         , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY4_ID  );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY4_ID_LEN                     , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY4_ID_LEN );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY3_VALID                      , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY3_VALID );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY3_ID                         , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY3_ID  );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY3_ID_LEN                     , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY3_ID_LEN );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY2_VALID                      , 26  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY2_VALID );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY2_ID                         , 27  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY2_ID  );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY2_ID_LEN                     , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY2_ID_LEN );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY1_VALID                      , 39  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY1_VALID );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY1_ID                         , 40  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY1_ID  );
+REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY1_ID_LEN                     , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DELAY1_ID_LEN );
+
+REG64_FLD( EQ_NCU_SPEC_BAR_REG_EN                                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EN         );
+REG64_FLD( EQ_NCU_SPEC_BAR_REG_256K                                , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_256K       );
+REG64_FLD( EQ_NCU_SPEC_BAR_REG_ADDR                                , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ADDR       );
+REG64_FLD( EQ_NCU_SPEC_BAR_REG_ADDR_LEN                            , 42  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_LEN   );
+
+REG64_FLD( EX_NCU_SPEC_BAR_REG_EN                                  , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_EN         );
+REG64_FLD( EX_NCU_SPEC_BAR_REG_256K                                , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_256K       );
+REG64_FLD( EX_NCU_SPEC_BAR_REG_ADDR                                , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ADDR       );
+REG64_FLD( EX_NCU_SPEC_BAR_REG_ADDR_LEN                            , 42  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ADDR_LEN   );
+
+REG64_FLD( EQ_NCU_STATUS_REG_CORE0_REQ_ACTIVE                      , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CORE0_REQ_ACTIVE );
+REG64_FLD( EQ_NCU_STATUS_REG_CORE1_REQ_ACTIVE                      , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CORE1_REQ_ACTIVE );
+REG64_FLD( EQ_NCU_STATUS_REG_CORE_OR_SNP_REQ_ACTIVE                , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CORE_OR_SNP_REQ_ACTIVE );
+REG64_FLD( EQ_NCU_STATUS_REG_ANY_REQ_ACTIVE                        , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ANY_REQ_ACTIVE );
+
+REG64_FLD( EX_NCU_STATUS_REG_CORE0_REQ_ACTIVE                      , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CORE0_REQ_ACTIVE );
+REG64_FLD( EX_NCU_STATUS_REG_CORE1_REQ_ACTIVE                      , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CORE1_REQ_ACTIVE );
+REG64_FLD( EX_NCU_STATUS_REG_CORE_OR_SNP_REQ_ACTIVE                , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CORE_OR_SNP_REQ_ACTIVE );
+REG64_FLD( EX_NCU_STATUS_REG_ANY_REQ_ACTIVE                        , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ANY_REQ_ACTIVE );
+
+REG64_FLD( EQ_NET_CTRL0_CHIPLET_ENABLE                             , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CHIPLET_ENABLE );
+REG64_FLD( EQ_NET_CTRL0_PCB_EP_RESET                               , 1   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_PCB_EP_RESET );
+REG64_FLD( EQ_NET_CTRL0_CLK_ASYNC_RESET                            , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_ASYNC_RESET );
+REG64_FLD( EQ_NET_CTRL0_PLL_TEST_EN                                , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_TEST_EN );
+REG64_FLD( EQ_NET_CTRL0_PLL_RESET                                  , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_RESET  );
+REG64_FLD( EQ_NET_CTRL0_PLL_BYPASS                                 , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_BYPASS );
+REG64_FLD( EQ_NET_CTRL0_VITAL_SCAN                                 , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_SCAN );
+REG64_FLD( EQ_NET_CTRL0_VITAL_SCAN_IN                              , 7   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_SCAN_IN );
+REG64_FLD( EQ_NET_CTRL0_VITAL_PHASE                                , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_PHASE );
+REG64_FLD( EQ_NET_CTRL0_FLUSH_ALIGN_OVR                            , 9   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_FLUSH_ALIGN_OVR );
+REG64_FLD( EQ_NET_CTRL0_VITAL_AL                                   , 10  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_AL   );
+REG64_FLD( EQ_NET_CTRL0_ACT_DIS                                    , 11  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_ACT_DIS    );
+REG64_FLD( EQ_NET_CTRL0_MPW1                                       , 12  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_MPW1       );
+REG64_FLD( EQ_NET_CTRL0_MPW2                                       , 13  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_MPW2       );
+REG64_FLD( EQ_NET_CTRL0_MPW3                                       , 14  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_MPW3       );
+REG64_FLD( EQ_NET_CTRL0_DELAY_LCLKR                                , 15  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_DELAY_LCLKR );
+REG64_FLD( EQ_NET_CTRL0_VITAL_THOLD                                , 16  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_THOLD );
+REG64_FLD( EQ_NET_CTRL0_FLUSH_SCAN_N                               , 17  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_FLUSH_SCAN_N );
+REG64_FLD( EQ_NET_CTRL0_FENCE_EN                                   , 18  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_FENCE_EN   );
+REG64_FLD( EQ_NET_CTRL0_CPLT_RCTRL                                 , 19  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CPLT_RCTRL );
+REG64_FLD( EQ_NET_CTRL0_CPLT_DCTRL                                 , 20  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CPLT_DCTRL );
+REG64_FLD( EQ_NET_CTRL0_L3_EDRAM_ENABLE0                           , 23  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_L3_EDRAM_ENABLE0 );
+REG64_FLD( EQ_NET_CTRL0_L3_EDRAM_ENABLE1                           , 24  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_L3_EDRAM_ENABLE1 );
+REG64_FLD( EQ_NET_CTRL0_TP_FENCE_PCB                               , 25  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_TP_FENCE_PCB );
+REG64_FLD( EQ_NET_CTRL0_LVLTRANS_FENCE                             , 26  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_LVLTRANS_FENCE );
+REG64_FLD( EQ_NET_CTRL0_ARRAY_WRITE_ASSIST_EN                      , 27  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_ARRAY_WRITE_ASSIST_EN );
+REG64_FLD( EQ_NET_CTRL0_HTB_INTEST                                 , 28  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_HTB_INTEST );
+REG64_FLD( EQ_NET_CTRL0_HTB_EXTEST                                 , 29  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_HTB_EXTEST );
+REG64_FLD( EQ_NET_CTRL0_PLLFORCE_OUT_EN                            , 31  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLLFORCE_OUT_EN );
+
+REG64_FLD( EX_NET_CTRL0_CHIPLET_ENABLE                             , 0   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CHIPLET_ENABLE );
+REG64_FLD( EX_NET_CTRL0_PCB_EP_RESET                               , 1   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_PCB_EP_RESET );
+REG64_FLD( EX_NET_CTRL0_CLK_ASYNC_RESET                            , 2   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_ASYNC_RESET );
+REG64_FLD( EX_NET_CTRL0_PLL_TEST_EN                                , 3   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_TEST_EN );
+REG64_FLD( EX_NET_CTRL0_PLL_RESET                                  , 4   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_RESET  );
+REG64_FLD( EX_NET_CTRL0_PLL_BYPASS                                 , 5   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_BYPASS );
+REG64_FLD( EX_NET_CTRL0_VITAL_SCAN                                 , 6   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_SCAN );
+REG64_FLD( EX_NET_CTRL0_VITAL_SCAN_IN                              , 7   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_SCAN_IN );
+REG64_FLD( EX_NET_CTRL0_VITAL_PHASE                                , 8   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_PHASE );
+REG64_FLD( EX_NET_CTRL0_FLUSH_ALIGN_OVR                            , 9   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_FLUSH_ALIGN_OVR );
+REG64_FLD( EX_NET_CTRL0_VITAL_AL                                   , 10  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_AL   );
+REG64_FLD( EX_NET_CTRL0_ACT_DIS                                    , 11  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_ACT_DIS    );
+REG64_FLD( EX_NET_CTRL0_MPW1                                       , 12  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_MPW1       );
+REG64_FLD( EX_NET_CTRL0_MPW2                                       , 13  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_MPW2       );
+REG64_FLD( EX_NET_CTRL0_MPW3                                       , 14  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_MPW3       );
+REG64_FLD( EX_NET_CTRL0_DELAY_LCLKR                                , 15  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_DELAY_LCLKR );
+REG64_FLD( EX_NET_CTRL0_VITAL_THOLD                                , 16  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_THOLD );
+REG64_FLD( EX_NET_CTRL0_FLUSH_SCAN_N                               , 17  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_FLUSH_SCAN_N );
+REG64_FLD( EX_NET_CTRL0_FENCE_EN                                   , 18  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_FENCE_EN   );
+REG64_FLD( EX_NET_CTRL0_CPLT_RCTRL                                 , 19  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CPLT_RCTRL );
+REG64_FLD( EX_NET_CTRL0_CPLT_DCTRL                                 , 20  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CPLT_DCTRL );
+REG64_FLD( EX_NET_CTRL0_L3_EDRAM_ENABLE0                           , 23  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_L3_EDRAM_ENABLE0 );
+REG64_FLD( EX_NET_CTRL0_L3_EDRAM_ENABLE1                           , 24  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_L3_EDRAM_ENABLE1 );
+REG64_FLD( EX_NET_CTRL0_TP_FENCE_PCB                               , 25  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_TP_FENCE_PCB );
+REG64_FLD( EX_NET_CTRL0_LVLTRANS_FENCE                             , 26  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_LVLTRANS_FENCE );
+REG64_FLD( EX_NET_CTRL0_ARRAY_WRITE_ASSIST_EN                      , 27  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_ARRAY_WRITE_ASSIST_EN );
+REG64_FLD( EX_NET_CTRL0_HTB_INTEST                                 , 28  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_HTB_INTEST );
+REG64_FLD( EX_NET_CTRL0_HTB_EXTEST                                 , 29  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_HTB_EXTEST );
+REG64_FLD( EX_NET_CTRL0_PLLFORCE_OUT_EN                            , 31  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLLFORCE_OUT_EN );
+
+REG64_FLD( C_NET_CTRL0_CHIPLET_ENABLE                              , 0   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_CHIPLET_ENABLE );
+REG64_FLD( C_NET_CTRL0_PCB_EP_RESET                                , 1   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_PCB_EP_RESET );
+REG64_FLD( C_NET_CTRL0_CLK_ASYNC_RESET                             , 2   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_ASYNC_RESET );
+REG64_FLD( C_NET_CTRL0_PLL_TEST_EN                                 , 3   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_TEST_EN );
+REG64_FLD( C_NET_CTRL0_PLL_RESET                                   , 4   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_RESET  );
+REG64_FLD( C_NET_CTRL0_PLL_BYPASS                                  , 5   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_BYPASS );
+REG64_FLD( C_NET_CTRL0_VITAL_SCAN                                  , 6   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_SCAN );
+REG64_FLD( C_NET_CTRL0_VITAL_SCAN_IN                               , 7   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_SCAN_IN );
+REG64_FLD( C_NET_CTRL0_VITAL_PHASE                                 , 8   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_PHASE );
+REG64_FLD( C_NET_CTRL0_FLUSH_ALIGN_OVR                             , 9   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_FLUSH_ALIGN_OVR );
+REG64_FLD( C_NET_CTRL0_VITAL_AL                                    , 10  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_AL   );
+REG64_FLD( C_NET_CTRL0_ACT_DIS                                     , 11  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_ACT_DIS    );
+REG64_FLD( C_NET_CTRL0_MPW1                                        , 12  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_MPW1       );
+REG64_FLD( C_NET_CTRL0_MPW2                                        , 13  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_MPW2       );
+REG64_FLD( C_NET_CTRL0_MPW3                                        , 14  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_MPW3       );
+REG64_FLD( C_NET_CTRL0_DELAY_LCLKR                                 , 15  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_DELAY_LCLKR );
+REG64_FLD( C_NET_CTRL0_VITAL_THOLD                                 , 16  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_VITAL_THOLD );
+REG64_FLD( C_NET_CTRL0_FLUSH_SCAN_N                                , 17  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_FLUSH_SCAN_N );
+REG64_FLD( C_NET_CTRL0_FENCE_EN                                    , 18  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_FENCE_EN   );
+REG64_FLD( C_NET_CTRL0_CPLT_RCTRL                                  , 19  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_CPLT_RCTRL );
+REG64_FLD( C_NET_CTRL0_CPLT_DCTRL                                  , 20  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_CPLT_DCTRL );
+REG64_FLD( C_NET_CTRL0_L3_EDRAM_ENABLE0                            , 23  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_L3_EDRAM_ENABLE0 );
+REG64_FLD( C_NET_CTRL0_L3_EDRAM_ENABLE1                            , 24  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_L3_EDRAM_ENABLE1 );
+REG64_FLD( C_NET_CTRL0_TP_FENCE_PCB                                , 25  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_TP_FENCE_PCB );
+REG64_FLD( C_NET_CTRL0_LVLTRANS_FENCE                              , 26  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_LVLTRANS_FENCE );
+REG64_FLD( C_NET_CTRL0_ARRAY_WRITE_ASSIST_EN                       , 27  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_ARRAY_WRITE_ASSIST_EN );
+REG64_FLD( C_NET_CTRL0_HTB_INTEST                                  , 28  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_HTB_INTEST );
+REG64_FLD( C_NET_CTRL0_HTB_EXTEST                                  , 29  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_HTB_EXTEST );
+REG64_FLD( C_NET_CTRL0_PLLFORCE_OUT_EN                             , 31  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLLFORCE_OUT_EN );
+
+REG64_FLD( EQ_NET_CTRL1_PLL_CLKIN_SEL                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_CLKIN_SEL );
+REG64_FLD( EQ_NET_CTRL1_CLK_DCC_BYPASS_EN                          , 1   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_DCC_BYPASS_EN );
+REG64_FLD( EQ_NET_CTRL1_CLK_PDLY_BYPASS_EN                         , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PDLY_BYPASS_EN );
+REG64_FLD( EQ_NET_CTRL1_CLK_DIV_BYPASS_EN                          , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_DIV_BYPASS_EN );
+REG64_FLD( EQ_NET_CTRL1_REFCLK_CLKMUX0_SEL                         , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_REFCLK_CLKMUX0_SEL );
+REG64_FLD( EQ_NET_CTRL1_REFCLK_CLKMUX1_SEL                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_REFCLK_CLKMUX1_SEL );
+REG64_FLD( EQ_NET_CTRL1_PLL_BNDY_BYPASS_EN                         , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_BNDY_BYPASS_EN );
+REG64_FLD( EQ_NET_CTRL1_DPLL_TEST_SEL                              , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_DPLL_TEST_SEL );
+REG64_FLD( EQ_NET_CTRL1_DPLL_TEST_SEL_LEN                          , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_DPLL_TEST_SEL_LEN );
+REG64_FLD( EQ_NET_CTRL1_SB_STRENGTH                                , 16  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_SB_STRENGTH );
+REG64_FLD( EQ_NET_CTRL1_SB_STRENGTH_LEN                            , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_SB_STRENGTH_LEN );
+REG64_FLD( EQ_NET_CTRL1_ASYNC_TYPE                                 , 20  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_ASYNC_TYPE );
+REG64_FLD( EQ_NET_CTRL1_ASYNC_OBS                                  , 21  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_ASYNC_OBS  );
+REG64_FLD( EQ_NET_CTRL1_CPM_CAL_SET                                , 22  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CPM_CAL_SET );
+REG64_FLD( EQ_NET_CTRL1_SENSEADJ_RESET0                            , 23  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_SENSEADJ_RESET0 );
+REG64_FLD( EQ_NET_CTRL1_SENSEADJ_RESET1                            , 24  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_SENSEADJ_RESET1 );
+REG64_FLD( EQ_NET_CTRL1_CLK_PULSE_EN                               , 25  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PULSE_EN );
+REG64_FLD( EQ_NET_CTRL1_CLK_PULSE_MODE                             , 26  , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PULSE_MODE );
+REG64_FLD( EQ_NET_CTRL1_CLK_PULSE_MODE_LEN                         , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PULSE_MODE_LEN );
+
+REG64_FLD( EX_NET_CTRL1_PLL_CLKIN_SEL                              , 0   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_CLKIN_SEL );
+REG64_FLD( EX_NET_CTRL1_CLK_DCC_BYPASS_EN                          , 1   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_DCC_BYPASS_EN );
+REG64_FLD( EX_NET_CTRL1_CLK_PDLY_BYPASS_EN                         , 2   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PDLY_BYPASS_EN );
+REG64_FLD( EX_NET_CTRL1_CLK_DIV_BYPASS_EN                          , 3   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_DIV_BYPASS_EN );
+REG64_FLD( EX_NET_CTRL1_REFCLK_CLKMUX0_SEL                         , 4   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_REFCLK_CLKMUX0_SEL );
+REG64_FLD( EX_NET_CTRL1_REFCLK_CLKMUX1_SEL                         , 5   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_REFCLK_CLKMUX1_SEL );
+REG64_FLD( EX_NET_CTRL1_PLL_BNDY_BYPASS_EN                         , 6   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_BNDY_BYPASS_EN );
+REG64_FLD( EX_NET_CTRL1_DPLL_TEST_SEL                              , 8   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_DPLL_TEST_SEL );
+REG64_FLD( EX_NET_CTRL1_DPLL_TEST_SEL_LEN                          , 8   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_DPLL_TEST_SEL_LEN );
+REG64_FLD( EX_NET_CTRL1_SB_STRENGTH                                , 16  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_SB_STRENGTH );
+REG64_FLD( EX_NET_CTRL1_SB_STRENGTH_LEN                            , 4   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_SB_STRENGTH_LEN );
+REG64_FLD( EX_NET_CTRL1_ASYNC_TYPE                                 , 20  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_ASYNC_TYPE );
+REG64_FLD( EX_NET_CTRL1_ASYNC_OBS                                  , 21  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_ASYNC_OBS  );
+REG64_FLD( EX_NET_CTRL1_CPM_CAL_SET                                , 22  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CPM_CAL_SET );
+REG64_FLD( EX_NET_CTRL1_SENSEADJ_RESET0                            , 23  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_SENSEADJ_RESET0 );
+REG64_FLD( EX_NET_CTRL1_SENSEADJ_RESET1                            , 24  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_SENSEADJ_RESET1 );
+REG64_FLD( EX_NET_CTRL1_CLK_PULSE_EN                               , 25  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PULSE_EN );
+REG64_FLD( EX_NET_CTRL1_CLK_PULSE_MODE                             , 26  , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PULSE_MODE );
+REG64_FLD( EX_NET_CTRL1_CLK_PULSE_MODE_LEN                         , 2   , SH_UNT_EX       , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PULSE_MODE_LEN );
+
+REG64_FLD( C_NET_CTRL1_PLL_CLKIN_SEL                               , 0   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_CLKIN_SEL );
+REG64_FLD( C_NET_CTRL1_CLK_DCC_BYPASS_EN                           , 1   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_DCC_BYPASS_EN );
+REG64_FLD( C_NET_CTRL1_CLK_PDLY_BYPASS_EN                          , 2   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PDLY_BYPASS_EN );
+REG64_FLD( C_NET_CTRL1_CLK_DIV_BYPASS_EN                           , 3   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_DIV_BYPASS_EN );
+REG64_FLD( C_NET_CTRL1_REFCLK_CLKMUX0_SEL                          , 4   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_REFCLK_CLKMUX0_SEL );
+REG64_FLD( C_NET_CTRL1_REFCLK_CLKMUX1_SEL                          , 5   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_REFCLK_CLKMUX1_SEL );
+REG64_FLD( C_NET_CTRL1_PLL_BNDY_BYPASS_EN                          , 6   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_PLL_BNDY_BYPASS_EN );
+REG64_FLD( C_NET_CTRL1_DPLL_TEST_SEL                               , 8   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_DPLL_TEST_SEL );
+REG64_FLD( C_NET_CTRL1_DPLL_TEST_SEL_LEN                           , 8   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_DPLL_TEST_SEL_LEN );
+REG64_FLD( C_NET_CTRL1_SB_STRENGTH                                 , 16  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_SB_STRENGTH );
+REG64_FLD( C_NET_CTRL1_SB_STRENGTH_LEN                             , 4   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_SB_STRENGTH_LEN );
+REG64_FLD( C_NET_CTRL1_ASYNC_TYPE                                  , 20  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_ASYNC_TYPE );
+REG64_FLD( C_NET_CTRL1_ASYNC_OBS                                   , 21  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_ASYNC_OBS  );
+REG64_FLD( C_NET_CTRL1_CPM_CAL_SET                                 , 22  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_CPM_CAL_SET );
+REG64_FLD( C_NET_CTRL1_SENSEADJ_RESET0                             , 23  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_SENSEADJ_RESET0 );
+REG64_FLD( C_NET_CTRL1_SENSEADJ_RESET1                             , 24  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_SENSEADJ_RESET1 );
+REG64_FLD( C_NET_CTRL1_CLK_PULSE_EN                                , 25  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PULSE_EN );
+REG64_FLD( C_NET_CTRL1_CLK_PULSE_MODE                              , 26  , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PULSE_MODE );
+REG64_FLD( C_NET_CTRL1_CLK_PULSE_MODE_LEN                          , 2   , SH_UNT_C        , SH_ACS_SCOM2_WOR,
+           SH_FLD_CLK_PULSE_MODE_LEN );
+
+REG64_FLD( EX_L2_OCC_SCOMC_MODE                                    , 54  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE       );
+REG64_FLD( EX_L2_OCC_SCOMC_MODE_LEN                                , 7   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_LEN   );
+
+REG64_FLD( C_OCC_SCOMC_MODE                                        , 54  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE       );
+REG64_FLD( C_OCC_SCOMC_MODE_LEN                                    , 7   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_LEN   );
+
+REG64_FLD( EQ_OPCG_ALIGN_INOP                                      , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INOP       );
+REG64_FLD( EQ_OPCG_ALIGN_INOP_LEN                                  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INOP_LEN   );
+REG64_FLD( EQ_OPCG_ALIGN_SNOP                                      , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SNOP       );
+REG64_FLD( EQ_OPCG_ALIGN_SNOP_LEN                                  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_LEN   );
+REG64_FLD( EQ_OPCG_ALIGN_ENOP                                      , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ENOP       );
+REG64_FLD( EQ_OPCG_ALIGN_ENOP_LEN                                  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_LEN   );
+REG64_FLD( EQ_OPCG_ALIGN_INOP_WAIT                                 , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INOP_WAIT  );
+REG64_FLD( EQ_OPCG_ALIGN_INOP_WAIT_LEN                             , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INOP_WAIT_LEN );
+REG64_FLD( EQ_OPCG_ALIGN_SNOP_WAIT                                 , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_WAIT  );
+REG64_FLD( EQ_OPCG_ALIGN_SNOP_WAIT_LEN                             , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_WAIT_LEN );
+REG64_FLD( EQ_OPCG_ALIGN_ENOP_WAIT                                 , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_WAIT  );
+REG64_FLD( EQ_OPCG_ALIGN_ENOP_WAIT_LEN                             , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_WAIT_LEN );
+REG64_FLD( EQ_OPCG_ALIGN_INOP_FORCE_SG                             , 40  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INOP_FORCE_SG );
+REG64_FLD( EQ_OPCG_ALIGN_SNOP_FORCE_SG                             , 41  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_FORCE_SG );
+REG64_FLD( EQ_OPCG_ALIGN_ENOP_FORCE_SG                             , 42  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_FORCE_SG );
+REG64_FLD( EQ_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD                        , 43  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NO_WAIT_ON_CLK_CMD );
+REG64_FLD( EQ_OPCG_ALIGN_SOURCE_SELECT                             , 44  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SOURCE_SELECT );
+REG64_FLD( EQ_OPCG_ALIGN_SOURCE_SELECT_LEN                         , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SOURCE_SELECT_LEN );
+REG64_FLD( EQ_OPCG_ALIGN_UNUSED46                                  , 46  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED46   );
+REG64_FLD( EQ_OPCG_ALIGN_SCAN_RATIO                                , 47  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_RATIO );
+REG64_FLD( EQ_OPCG_ALIGN_SCAN_RATIO_LEN                            , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_RATIO_LEN );
+REG64_FLD( EQ_OPCG_ALIGN_WAIT_CYCLES                               , 52  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( EQ_OPCG_ALIGN_WAIT_CYCLES_LEN                           , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( EX_OPCG_ALIGN_INOP                                      , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INOP       );
+REG64_FLD( EX_OPCG_ALIGN_INOP_LEN                                  , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INOP_LEN   );
+REG64_FLD( EX_OPCG_ALIGN_SNOP                                      , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SNOP       );
+REG64_FLD( EX_OPCG_ALIGN_SNOP_LEN                                  , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_LEN   );
+REG64_FLD( EX_OPCG_ALIGN_ENOP                                      , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ENOP       );
+REG64_FLD( EX_OPCG_ALIGN_ENOP_LEN                                  , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_LEN   );
+REG64_FLD( EX_OPCG_ALIGN_INOP_WAIT                                 , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INOP_WAIT  );
+REG64_FLD( EX_OPCG_ALIGN_INOP_WAIT_LEN                             , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INOP_WAIT_LEN );
+REG64_FLD( EX_OPCG_ALIGN_SNOP_WAIT                                 , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_WAIT  );
+REG64_FLD( EX_OPCG_ALIGN_SNOP_WAIT_LEN                             , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_WAIT_LEN );
+REG64_FLD( EX_OPCG_ALIGN_ENOP_WAIT                                 , 32  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_WAIT  );
+REG64_FLD( EX_OPCG_ALIGN_ENOP_WAIT_LEN                             , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_WAIT_LEN );
+REG64_FLD( EX_OPCG_ALIGN_INOP_FORCE_SG                             , 40  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INOP_FORCE_SG );
+REG64_FLD( EX_OPCG_ALIGN_SNOP_FORCE_SG                             , 41  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_FORCE_SG );
+REG64_FLD( EX_OPCG_ALIGN_ENOP_FORCE_SG                             , 42  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_FORCE_SG );
+REG64_FLD( EX_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD                        , 43  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NO_WAIT_ON_CLK_CMD );
+REG64_FLD( EX_OPCG_ALIGN_SOURCE_SELECT                             , 44  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SOURCE_SELECT );
+REG64_FLD( EX_OPCG_ALIGN_SOURCE_SELECT_LEN                         , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SOURCE_SELECT_LEN );
+REG64_FLD( EX_OPCG_ALIGN_UNUSED46                                  , 46  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED46   );
+REG64_FLD( EX_OPCG_ALIGN_SCAN_RATIO                                , 47  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_RATIO );
+REG64_FLD( EX_OPCG_ALIGN_SCAN_RATIO_LEN                            , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_RATIO_LEN );
+REG64_FLD( EX_OPCG_ALIGN_WAIT_CYCLES                               , 52  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( EX_OPCG_ALIGN_WAIT_CYCLES_LEN                           , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( C_OPCG_ALIGN_INOP                                       , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INOP       );
+REG64_FLD( C_OPCG_ALIGN_INOP_LEN                                   , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INOP_LEN   );
+REG64_FLD( C_OPCG_ALIGN_SNOP                                       , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SNOP       );
+REG64_FLD( C_OPCG_ALIGN_SNOP_LEN                                   , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_LEN   );
+REG64_FLD( C_OPCG_ALIGN_ENOP                                       , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ENOP       );
+REG64_FLD( C_OPCG_ALIGN_ENOP_LEN                                   , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_LEN   );
+REG64_FLD( C_OPCG_ALIGN_INOP_WAIT                                  , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INOP_WAIT  );
+REG64_FLD( C_OPCG_ALIGN_INOP_WAIT_LEN                              , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INOP_WAIT_LEN );
+REG64_FLD( C_OPCG_ALIGN_SNOP_WAIT                                  , 20  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_WAIT  );
+REG64_FLD( C_OPCG_ALIGN_SNOP_WAIT_LEN                              , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_WAIT_LEN );
+REG64_FLD( C_OPCG_ALIGN_ENOP_WAIT                                  , 32  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_WAIT  );
+REG64_FLD( C_OPCG_ALIGN_ENOP_WAIT_LEN                              , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_WAIT_LEN );
+REG64_FLD( C_OPCG_ALIGN_INOP_FORCE_SG                              , 40  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INOP_FORCE_SG );
+REG64_FLD( C_OPCG_ALIGN_SNOP_FORCE_SG                              , 41  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SNOP_FORCE_SG );
+REG64_FLD( C_OPCG_ALIGN_ENOP_FORCE_SG                              , 42  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ENOP_FORCE_SG );
+REG64_FLD( C_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD                         , 43  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_NO_WAIT_ON_CLK_CMD );
+REG64_FLD( C_OPCG_ALIGN_SOURCE_SELECT                              , 44  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SOURCE_SELECT );
+REG64_FLD( C_OPCG_ALIGN_SOURCE_SELECT_LEN                          , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SOURCE_SELECT_LEN );
+REG64_FLD( C_OPCG_ALIGN_UNUSED46                                   , 46  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED46   );
+REG64_FLD( C_OPCG_ALIGN_SCAN_RATIO                                 , 47  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_RATIO );
+REG64_FLD( C_OPCG_ALIGN_SCAN_RATIO_LEN                             , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_RATIO_LEN );
+REG64_FLD( C_OPCG_ALIGN_WAIT_CYCLES                                , 52  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( C_OPCG_ALIGN_WAIT_CYCLES_LEN                            , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( EQ_OPCG_CAPT1_COUNT                                     , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COUNT      );
+REG64_FLD( EQ_OPCG_CAPT1_COUNT_LEN                                 , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COUNT_LEN  );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_01                                    , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_01     );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_01_LEN                                , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_01_LEN );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_02                                    , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_02     );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_02_LEN                                , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_02_LEN );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_03                                    , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_03     );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_03_LEN                                , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_03_LEN );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_04                                    , 19  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_04     );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_04_LEN                                , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_04_LEN );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_05                                    , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_05     );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_05_LEN                                , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_05_LEN );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_06                                    , 29  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_06     );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_06_LEN                                , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_06_LEN );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_07                                    , 34  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07     );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_07_LEN                                , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07_LEN );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_08                                    , 39  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08     );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_08_LEN                                , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08_LEN );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_09                                    , 44  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09     );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_09_LEN                                , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09_LEN );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_10                                    , 49  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10     );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_10_LEN                                , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10_LEN );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_11                                    , 54  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11     );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_11_LEN                                , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11_LEN );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_12                                    , 59  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12     );
+REG64_FLD( EQ_OPCG_CAPT1_SEQ_12_LEN                                , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12_LEN );
+
+REG64_FLD( EX_OPCG_CAPT1_COUNT                                     , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COUNT      );
+REG64_FLD( EX_OPCG_CAPT1_COUNT_LEN                                 , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COUNT_LEN  );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_01                                    , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_01     );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_01_LEN                                , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_01_LEN );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_02                                    , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_02     );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_02_LEN                                , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_02_LEN );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_03                                    , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_03     );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_03_LEN                                , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_03_LEN );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_04                                    , 19  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_04     );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_04_LEN                                , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_04_LEN );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_05                                    , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_05     );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_05_LEN                                , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_05_LEN );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_06                                    , 29  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_06     );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_06_LEN                                , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_06_LEN );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_07                                    , 34  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07     );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_07_LEN                                , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07_LEN );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_08                                    , 39  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08     );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_08_LEN                                , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08_LEN );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_09                                    , 44  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09     );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_09_LEN                                , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09_LEN );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_10                                    , 49  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10     );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_10_LEN                                , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10_LEN );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_11                                    , 54  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11     );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_11_LEN                                , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11_LEN );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_12                                    , 59  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12     );
+REG64_FLD( EX_OPCG_CAPT1_SEQ_12_LEN                                , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12_LEN );
+
+REG64_FLD( C_OPCG_CAPT1_COUNT                                      , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COUNT      );
+REG64_FLD( C_OPCG_CAPT1_COUNT_LEN                                  , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COUNT_LEN  );
+REG64_FLD( C_OPCG_CAPT1_SEQ_01                                     , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_01     );
+REG64_FLD( C_OPCG_CAPT1_SEQ_01_LEN                                 , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_01_LEN );
+REG64_FLD( C_OPCG_CAPT1_SEQ_02                                     , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_02     );
+REG64_FLD( C_OPCG_CAPT1_SEQ_02_LEN                                 , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_02_LEN );
+REG64_FLD( C_OPCG_CAPT1_SEQ_03                                     , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_03     );
+REG64_FLD( C_OPCG_CAPT1_SEQ_03_LEN                                 , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_03_LEN );
+REG64_FLD( C_OPCG_CAPT1_SEQ_04                                     , 19  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_04     );
+REG64_FLD( C_OPCG_CAPT1_SEQ_04_LEN                                 , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_04_LEN );
+REG64_FLD( C_OPCG_CAPT1_SEQ_05                                     , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_05     );
+REG64_FLD( C_OPCG_CAPT1_SEQ_05_LEN                                 , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_05_LEN );
+REG64_FLD( C_OPCG_CAPT1_SEQ_06                                     , 29  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_06     );
+REG64_FLD( C_OPCG_CAPT1_SEQ_06_LEN                                 , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_06_LEN );
+REG64_FLD( C_OPCG_CAPT1_SEQ_07                                     , 34  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07     );
+REG64_FLD( C_OPCG_CAPT1_SEQ_07_LEN                                 , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07_LEN );
+REG64_FLD( C_OPCG_CAPT1_SEQ_08                                     , 39  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08     );
+REG64_FLD( C_OPCG_CAPT1_SEQ_08_LEN                                 , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08_LEN );
+REG64_FLD( C_OPCG_CAPT1_SEQ_09                                     , 44  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09     );
+REG64_FLD( C_OPCG_CAPT1_SEQ_09_LEN                                 , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09_LEN );
+REG64_FLD( C_OPCG_CAPT1_SEQ_10                                     , 49  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10     );
+REG64_FLD( C_OPCG_CAPT1_SEQ_10_LEN                                 , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10_LEN );
+REG64_FLD( C_OPCG_CAPT1_SEQ_11                                     , 54  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11     );
+REG64_FLD( C_OPCG_CAPT1_SEQ_11_LEN                                 , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11_LEN );
+REG64_FLD( C_OPCG_CAPT1_SEQ_12                                     , 59  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12     );
+REG64_FLD( C_OPCG_CAPT1_SEQ_12_LEN                                 , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12_LEN );
+
+REG64_FLD( EQ_OPCG_CAPT2_UNUSED                                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EQ_OPCG_CAPT2_UNUSED_LEN                                , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_13_01EVEN                             , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_13_01EVEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_13_01EVEN_LEN                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_13_01EVEN_LEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_14_01ODD                              , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_14_01ODD );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_14_01ODD_LEN                          , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_14_01ODD_LEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_15_02EVEN                             , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_15_02EVEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_15_02EVEN_LEN                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_15_02EVEN_LEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_16_02ODD                              , 19  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_16_02ODD );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_16_02ODD_LEN                          , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_16_02ODD_LEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_17_03EVEN                             , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_17_03EVEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_17_03EVEN_LEN                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_17_03EVEN_LEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_18_03ODD                              , 29  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_18_03ODD );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_18_03ODD_LEN                          , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_18_03ODD_LEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_19_04EVEN                             , 34  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_19_04EVEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_19_04EVEN_LEN                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_19_04EVEN_LEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_20_04ODD                              , 39  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_20_04ODD );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_20_04ODD_LEN                          , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_20_04ODD_LEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_21_05EVEN                             , 44  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_21_05EVEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_21_05EVEN_LEN                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_21_05EVEN_LEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_22_05ODD                              , 49  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_22_05ODD );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_22_05ODD_LEN                          , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_22_05ODD_LEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_23_06EVEN                             , 54  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_23_06EVEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_23_06EVEN_LEN                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_23_06EVEN_LEN );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_24_06ODD                              , 59  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_24_06ODD );
+REG64_FLD( EQ_OPCG_CAPT2_SEQ_24_06ODD_LEN                          , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_24_06ODD_LEN );
+
+REG64_FLD( EX_OPCG_CAPT2_UNUSED                                    , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EX_OPCG_CAPT2_UNUSED_LEN                                , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_13_01EVEN                             , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_13_01EVEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_13_01EVEN_LEN                         , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_13_01EVEN_LEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_14_01ODD                              , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_14_01ODD );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_14_01ODD_LEN                          , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_14_01ODD_LEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_15_02EVEN                             , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_15_02EVEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_15_02EVEN_LEN                         , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_15_02EVEN_LEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_16_02ODD                              , 19  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_16_02ODD );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_16_02ODD_LEN                          , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_16_02ODD_LEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_17_03EVEN                             , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_17_03EVEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_17_03EVEN_LEN                         , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_17_03EVEN_LEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_18_03ODD                              , 29  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_18_03ODD );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_18_03ODD_LEN                          , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_18_03ODD_LEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_19_04EVEN                             , 34  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_19_04EVEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_19_04EVEN_LEN                         , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_19_04EVEN_LEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_20_04ODD                              , 39  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_20_04ODD );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_20_04ODD_LEN                          , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_20_04ODD_LEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_21_05EVEN                             , 44  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_21_05EVEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_21_05EVEN_LEN                         , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_21_05EVEN_LEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_22_05ODD                              , 49  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_22_05ODD );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_22_05ODD_LEN                          , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_22_05ODD_LEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_23_06EVEN                             , 54  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_23_06EVEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_23_06EVEN_LEN                         , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_23_06EVEN_LEN );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_24_06ODD                              , 59  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_24_06ODD );
+REG64_FLD( EX_OPCG_CAPT2_SEQ_24_06ODD_LEN                          , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_24_06ODD_LEN );
+
+REG64_FLD( C_OPCG_CAPT2_UNUSED                                     , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( C_OPCG_CAPT2_UNUSED_LEN                                 , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_13_01EVEN                              , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_13_01EVEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_13_01EVEN_LEN                          , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_13_01EVEN_LEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_14_01ODD                               , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_14_01ODD );
+REG64_FLD( C_OPCG_CAPT2_SEQ_14_01ODD_LEN                           , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_14_01ODD_LEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_15_02EVEN                              , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_15_02EVEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_15_02EVEN_LEN                          , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_15_02EVEN_LEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_16_02ODD                               , 19  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_16_02ODD );
+REG64_FLD( C_OPCG_CAPT2_SEQ_16_02ODD_LEN                           , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_16_02ODD_LEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_17_03EVEN                              , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_17_03EVEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_17_03EVEN_LEN                          , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_17_03EVEN_LEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_18_03ODD                               , 29  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_18_03ODD );
+REG64_FLD( C_OPCG_CAPT2_SEQ_18_03ODD_LEN                           , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_18_03ODD_LEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_19_04EVEN                              , 34  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_19_04EVEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_19_04EVEN_LEN                          , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_19_04EVEN_LEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_20_04ODD                               , 39  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_20_04ODD );
+REG64_FLD( C_OPCG_CAPT2_SEQ_20_04ODD_LEN                           , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_20_04ODD_LEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_21_05EVEN                              , 44  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_21_05EVEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_21_05EVEN_LEN                          , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_21_05EVEN_LEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_22_05ODD                               , 49  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_22_05ODD );
+REG64_FLD( C_OPCG_CAPT2_SEQ_22_05ODD_LEN                           , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_22_05ODD_LEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_23_06EVEN                              , 54  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_23_06EVEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_23_06EVEN_LEN                          , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_23_06EVEN_LEN );
+REG64_FLD( C_OPCG_CAPT2_SEQ_24_06ODD                               , 59  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_24_06ODD );
+REG64_FLD( C_OPCG_CAPT2_SEQ_24_06ODD_LEN                           , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_24_06ODD_LEN );
+
+REG64_FLD( EQ_OPCG_CAPT3_UNUSED                                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EQ_OPCG_CAPT3_UNUSED_LEN                                , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_07EVEN                                , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07EVEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_07EVEN_LEN                            , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07EVEN_LEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_07ODD                                 , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07ODD  );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_07ODD_LEN                             , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07ODD_LEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_08EVEN                                , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08EVEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_08EVEN_LEN                            , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08EVEN_LEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_08ODD                                 , 19  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08ODD  );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_08ODD_LEN                             , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08ODD_LEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_09EVEN                                , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09EVEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_09EVEN_LEN                            , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09EVEN_LEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_09ODD                                 , 29  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09ODD  );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_09ODD_LEN                             , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09ODD_LEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_10EVEN                                , 34  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10EVEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_10EVEN_LEN                            , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10EVEN_LEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_10ODD                                 , 39  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10ODD  );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_10ODD_LEN                             , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10ODD_LEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_11EVEN                                , 44  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11EVEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_11EVEN_LEN                            , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11EVEN_LEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_11ODD                                 , 49  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11ODD  );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_11ODD_LEN                             , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11ODD_LEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_12EVEN                                , 54  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12EVEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_12EVEN_LEN                            , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12EVEN_LEN );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_12ODD                                 , 59  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12ODD  );
+REG64_FLD( EQ_OPCG_CAPT3_SEQ_12ODD_LEN                             , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12ODD_LEN );
+
+REG64_FLD( EX_OPCG_CAPT3_UNUSED                                    , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EX_OPCG_CAPT3_UNUSED_LEN                                , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_07EVEN                                , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07EVEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_07EVEN_LEN                            , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07EVEN_LEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_07ODD                                 , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07ODD  );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_07ODD_LEN                             , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07ODD_LEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_08EVEN                                , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08EVEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_08EVEN_LEN                            , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08EVEN_LEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_08ODD                                 , 19  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08ODD  );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_08ODD_LEN                             , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08ODD_LEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_09EVEN                                , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09EVEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_09EVEN_LEN                            , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09EVEN_LEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_09ODD                                 , 29  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09ODD  );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_09ODD_LEN                             , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09ODD_LEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_10EVEN                                , 34  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10EVEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_10EVEN_LEN                            , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10EVEN_LEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_10ODD                                 , 39  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10ODD  );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_10ODD_LEN                             , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10ODD_LEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_11EVEN                                , 44  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11EVEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_11EVEN_LEN                            , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11EVEN_LEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_11ODD                                 , 49  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11ODD  );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_11ODD_LEN                             , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11ODD_LEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_12EVEN                                , 54  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12EVEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_12EVEN_LEN                            , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12EVEN_LEN );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_12ODD                                 , 59  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12ODD  );
+REG64_FLD( EX_OPCG_CAPT3_SEQ_12ODD_LEN                             , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12ODD_LEN );
+
+REG64_FLD( C_OPCG_CAPT3_UNUSED                                     , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( C_OPCG_CAPT3_UNUSED_LEN                                 , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_07EVEN                                 , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07EVEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_07EVEN_LEN                             , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07EVEN_LEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_07ODD                                  , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07ODD  );
+REG64_FLD( C_OPCG_CAPT3_SEQ_07ODD_LEN                              , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_07ODD_LEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_08EVEN                                 , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08EVEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_08EVEN_LEN                             , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08EVEN_LEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_08ODD                                  , 19  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08ODD  );
+REG64_FLD( C_OPCG_CAPT3_SEQ_08ODD_LEN                              , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_08ODD_LEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_09EVEN                                 , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09EVEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_09EVEN_LEN                             , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09EVEN_LEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_09ODD                                  , 29  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09ODD  );
+REG64_FLD( C_OPCG_CAPT3_SEQ_09ODD_LEN                              , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_09ODD_LEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_10EVEN                                 , 34  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10EVEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_10EVEN_LEN                             , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10EVEN_LEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_10ODD                                  , 39  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10ODD  );
+REG64_FLD( C_OPCG_CAPT3_SEQ_10ODD_LEN                              , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_10ODD_LEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_11EVEN                                 , 44  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11EVEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_11EVEN_LEN                             , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11EVEN_LEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_11ODD                                  , 49  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11ODD  );
+REG64_FLD( C_OPCG_CAPT3_SEQ_11ODD_LEN                              , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_11ODD_LEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_12EVEN                                 , 54  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12EVEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_12EVEN_LEN                             , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12EVEN_LEN );
+REG64_FLD( C_OPCG_CAPT3_SEQ_12ODD                                  , 59  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12ODD  );
+REG64_FLD( C_OPCG_CAPT3_SEQ_12ODD_LEN                              , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SEQ_12ODD_LEN );
+
+REG64_FLD( EQ_OPCG_REG0_RUNN_MODE                                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_MODE  );
+REG64_FLD( EQ_OPCG_REG0_GO                                         , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GO         );
+REG64_FLD( EQ_OPCG_REG0_RUN_SCAN0                                  , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RUN_SCAN0  );
+REG64_FLD( EQ_OPCG_REG0_SCAN0_MODE                                 , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SCAN0_MODE );
+REG64_FLD( EQ_OPCG_REG0_IN_SLAVE_MODE                              , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN_SLAVE_MODE );
+REG64_FLD( EQ_OPCG_REG0_IN_MASTER_MODE                             , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN_MASTER_MODE );
+REG64_FLD( EQ_OPCG_REG0_KEEP_MS_MODE                               , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_KEEP_MS_MODE );
+REG64_FLD( EQ_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL                  , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_ON_UNIT0_SYNC_LVL );
+REG64_FLD( EQ_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL                  , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_ON_UNIT1_SYNC_LVL );
+REG64_FLD( EQ_OPCG_REG0_RUN_CHIPLET_SCAN0                          , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RUN_CHIPLET_SCAN0 );
+REG64_FLD( EQ_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL                   , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL );
+REG64_FLD( EQ_OPCG_REG0_RUN_ON_UPDATE_DR                           , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RUN_ON_UPDATE_DR );
+REG64_FLD( EQ_OPCG_REG0_RUN_ON_CAPTURE_DR                          , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RUN_ON_CAPTURE_DR );
+REG64_FLD( EQ_OPCG_REG0_STOP_RUNN_ON_XSTOP                         , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STOP_RUNN_ON_XSTOP );
+REG64_FLD( EQ_OPCG_REG0_STARTS_BIST                                , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STARTS_BIST );
+REG64_FLD( EQ_OPCG_REG0_UNUSED1520                                 , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1520 );
+REG64_FLD( EQ_OPCG_REG0_UNUSED1520_LEN                             , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1520_LEN );
+REG64_FLD( EQ_OPCG_REG0_LOOP_COUNT                                 , 21  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_LOOP_COUNT );
+REG64_FLD( EQ_OPCG_REG0_LOOP_COUNT_LEN                             , 43  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_LOOP_COUNT_LEN );
+
+REG64_FLD( EX_OPCG_REG0_RUNN_MODE                                  , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_MODE  );
+REG64_FLD( EX_OPCG_REG0_GO                                         , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GO         );
+REG64_FLD( EX_OPCG_REG0_RUN_SCAN0                                  , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RUN_SCAN0  );
+REG64_FLD( EX_OPCG_REG0_SCAN0_MODE                                 , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SCAN0_MODE );
+REG64_FLD( EX_OPCG_REG0_IN_SLAVE_MODE                              , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN_SLAVE_MODE );
+REG64_FLD( EX_OPCG_REG0_IN_MASTER_MODE                             , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN_MASTER_MODE );
+REG64_FLD( EX_OPCG_REG0_KEEP_MS_MODE                               , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_KEEP_MS_MODE );
+REG64_FLD( EX_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL                  , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_ON_UNIT0_SYNC_LVL );
+REG64_FLD( EX_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL                  , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_ON_UNIT1_SYNC_LVL );
+REG64_FLD( EX_OPCG_REG0_RUN_CHIPLET_SCAN0                          , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RUN_CHIPLET_SCAN0 );
+REG64_FLD( EX_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL                   , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL );
+REG64_FLD( EX_OPCG_REG0_RUN_ON_UPDATE_DR                           , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RUN_ON_UPDATE_DR );
+REG64_FLD( EX_OPCG_REG0_RUN_ON_CAPTURE_DR                          , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RUN_ON_CAPTURE_DR );
+REG64_FLD( EX_OPCG_REG0_STOP_RUNN_ON_XSTOP                         , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STOP_RUNN_ON_XSTOP );
+REG64_FLD( EX_OPCG_REG0_STARTS_BIST                                , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STARTS_BIST );
+REG64_FLD( EX_OPCG_REG0_UNUSED1520                                 , 15  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1520 );
+REG64_FLD( EX_OPCG_REG0_UNUSED1520_LEN                             , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1520_LEN );
+REG64_FLD( EX_OPCG_REG0_LOOP_COUNT                                 , 21  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_LOOP_COUNT );
+REG64_FLD( EX_OPCG_REG0_LOOP_COUNT_LEN                             , 43  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_LOOP_COUNT_LEN );
+
+REG64_FLD( C_OPCG_REG0_RUNN_MODE                                   , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RUNN_MODE  );
+REG64_FLD( C_OPCG_REG0_GO                                          , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GO         );
+REG64_FLD( C_OPCG_REG0_RUN_SCAN0                                   , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RUN_SCAN0  );
+REG64_FLD( C_OPCG_REG0_SCAN0_MODE                                  , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SCAN0_MODE );
+REG64_FLD( C_OPCG_REG0_IN_SLAVE_MODE                               , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN_SLAVE_MODE );
+REG64_FLD( C_OPCG_REG0_IN_MASTER_MODE                              , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN_MASTER_MODE );
+REG64_FLD( C_OPCG_REG0_KEEP_MS_MODE                                , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_KEEP_MS_MODE );
+REG64_FLD( C_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL                   , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_ON_UNIT0_SYNC_LVL );
+REG64_FLD( C_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL                   , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_ON_UNIT1_SYNC_LVL );
+REG64_FLD( C_OPCG_REG0_RUN_CHIPLET_SCAN0                           , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RUN_CHIPLET_SCAN0 );
+REG64_FLD( C_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL                    , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL );
+REG64_FLD( C_OPCG_REG0_RUN_ON_UPDATE_DR                            , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RUN_ON_UPDATE_DR );
+REG64_FLD( C_OPCG_REG0_RUN_ON_CAPTURE_DR                           , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RUN_ON_CAPTURE_DR );
+REG64_FLD( C_OPCG_REG0_STOP_RUNN_ON_XSTOP                          , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STOP_RUNN_ON_XSTOP );
+REG64_FLD( C_OPCG_REG0_STARTS_BIST                                 , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_STARTS_BIST );
+REG64_FLD( C_OPCG_REG0_UNUSED1520                                  , 15  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1520 );
+REG64_FLD( C_OPCG_REG0_UNUSED1520_LEN                              , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1520_LEN );
+REG64_FLD( C_OPCG_REG0_LOOP_COUNT                                  , 21  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_LOOP_COUNT );
+REG64_FLD( C_OPCG_REG0_LOOP_COUNT_LEN                              , 43  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_LOOP_COUNT_LEN );
+
+REG64_FLD( EQ_OPCG_REG1_SCAN_COUNT                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_COUNT );
+REG64_FLD( EQ_OPCG_REG1_SCAN_COUNT_LEN                             , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_COUNT_LEN );
+REG64_FLD( EQ_OPCG_REG1_MISR_A_VAL                                 , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MISR_A_VAL );
+REG64_FLD( EQ_OPCG_REG1_MISR_A_VAL_LEN                             , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MISR_A_VAL_LEN );
+REG64_FLD( EQ_OPCG_REG1_MISR_B_VAL                                 , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MISR_B_VAL );
+REG64_FLD( EQ_OPCG_REG1_MISR_B_VAL_LEN                             , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MISR_B_VAL_LEN );
+REG64_FLD( EQ_OPCG_REG1_MISR_INIT_WAIT                             , 36  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MISR_INIT_WAIT );
+REG64_FLD( EQ_OPCG_REG1_MISR_INIT_WAIT_LEN                         , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MISR_INIT_WAIT_LEN );
+REG64_FLD( EQ_OPCG_REG1_SUPPRESS_EVEN_CLK                          , 48  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SUPPRESS_EVEN_CLK );
+REG64_FLD( EQ_OPCG_REG1_SCAN_CLK_USE_EVEN                          , 49  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_CLK_USE_EVEN );
+REG64_FLD( EQ_OPCG_REG1_UNUSED2                                    , 50  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2    );
+REG64_FLD( EQ_OPCG_REG1_UNUSED2_LEN                                , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2_LEN );
+REG64_FLD( EQ_OPCG_REG1_RTIM_THOLD_FORCE                           , 52  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RTIM_THOLD_FORCE );
+REG64_FLD( EQ_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL                , 53  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_ARY_CLK_DURING_FILL );
+REG64_FLD( EQ_OPCG_REG1_SG_HIGH_DURING_FILL                        , 54  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SG_HIGH_DURING_FILL );
+REG64_FLD( EQ_OPCG_REG1_LBIST_SKITTER_CTL                          , 55  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_LBIST_SKITTER_CTL );
+REG64_FLD( EQ_OPCG_REG1_LBIST_SKITTER_CTL_LEN                      , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_LBIST_SKITTER_CTL_LEN );
+REG64_FLD( EQ_OPCG_REG1_MISR_MODE                                  , 57  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MISR_MODE  );
+REG64_FLD( EQ_OPCG_REG1_INFINITE_MODE                              , 58  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INFINITE_MODE );
+REG64_FLD( EQ_OPCG_REG1_NSL_FILL_COUNT                             , 59  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NSL_FILL_COUNT );
+REG64_FLD( EQ_OPCG_REG1_NSL_FILL_COUNT_LEN                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NSL_FILL_COUNT_LEN );
+
+REG64_FLD( EX_OPCG_REG1_SCAN_COUNT                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_COUNT );
+REG64_FLD( EX_OPCG_REG1_SCAN_COUNT_LEN                             , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_COUNT_LEN );
+REG64_FLD( EX_OPCG_REG1_MISR_A_VAL                                 , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MISR_A_VAL );
+REG64_FLD( EX_OPCG_REG1_MISR_A_VAL_LEN                             , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MISR_A_VAL_LEN );
+REG64_FLD( EX_OPCG_REG1_MISR_B_VAL                                 , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MISR_B_VAL );
+REG64_FLD( EX_OPCG_REG1_MISR_B_VAL_LEN                             , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MISR_B_VAL_LEN );
+REG64_FLD( EX_OPCG_REG1_MISR_INIT_WAIT                             , 36  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MISR_INIT_WAIT );
+REG64_FLD( EX_OPCG_REG1_MISR_INIT_WAIT_LEN                         , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MISR_INIT_WAIT_LEN );
+REG64_FLD( EX_OPCG_REG1_SUPPRESS_EVEN_CLK                          , 48  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SUPPRESS_EVEN_CLK );
+REG64_FLD( EX_OPCG_REG1_SCAN_CLK_USE_EVEN                          , 49  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_CLK_USE_EVEN );
+REG64_FLD( EX_OPCG_REG1_UNUSED2                                    , 50  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2    );
+REG64_FLD( EX_OPCG_REG1_UNUSED2_LEN                                , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2_LEN );
+REG64_FLD( EX_OPCG_REG1_RTIM_THOLD_FORCE                           , 52  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RTIM_THOLD_FORCE );
+REG64_FLD( EX_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL                , 53  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_ARY_CLK_DURING_FILL );
+REG64_FLD( EX_OPCG_REG1_SG_HIGH_DURING_FILL                        , 54  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SG_HIGH_DURING_FILL );
+REG64_FLD( EX_OPCG_REG1_LBIST_SKITTER_CTL                          , 55  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_LBIST_SKITTER_CTL );
+REG64_FLD( EX_OPCG_REG1_LBIST_SKITTER_CTL_LEN                      , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_LBIST_SKITTER_CTL_LEN );
+REG64_FLD( EX_OPCG_REG1_MISR_MODE                                  , 57  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MISR_MODE  );
+REG64_FLD( EX_OPCG_REG1_INFINITE_MODE                              , 58  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INFINITE_MODE );
+REG64_FLD( EX_OPCG_REG1_NSL_FILL_COUNT                             , 59  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NSL_FILL_COUNT );
+REG64_FLD( EX_OPCG_REG1_NSL_FILL_COUNT_LEN                         , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NSL_FILL_COUNT_LEN );
+
+REG64_FLD( C_OPCG_REG1_SCAN_COUNT                                  , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_COUNT );
+REG64_FLD( C_OPCG_REG1_SCAN_COUNT_LEN                              , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_COUNT_LEN );
+REG64_FLD( C_OPCG_REG1_MISR_A_VAL                                  , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MISR_A_VAL );
+REG64_FLD( C_OPCG_REG1_MISR_A_VAL_LEN                              , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MISR_A_VAL_LEN );
+REG64_FLD( C_OPCG_REG1_MISR_B_VAL                                  , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MISR_B_VAL );
+REG64_FLD( C_OPCG_REG1_MISR_B_VAL_LEN                              , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MISR_B_VAL_LEN );
+REG64_FLD( C_OPCG_REG1_MISR_INIT_WAIT                              , 36  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MISR_INIT_WAIT );
+REG64_FLD( C_OPCG_REG1_MISR_INIT_WAIT_LEN                          , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MISR_INIT_WAIT_LEN );
+REG64_FLD( C_OPCG_REG1_SUPPRESS_EVEN_CLK                           , 48  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SUPPRESS_EVEN_CLK );
+REG64_FLD( C_OPCG_REG1_SCAN_CLK_USE_EVEN                           , 49  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SCAN_CLK_USE_EVEN );
+REG64_FLD( C_OPCG_REG1_UNUSED2                                     , 50  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2    );
+REG64_FLD( C_OPCG_REG1_UNUSED2_LEN                                 , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2_LEN );
+REG64_FLD( C_OPCG_REG1_RTIM_THOLD_FORCE                            , 52  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RTIM_THOLD_FORCE );
+REG64_FLD( C_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL                 , 53  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_ARY_CLK_DURING_FILL );
+REG64_FLD( C_OPCG_REG1_SG_HIGH_DURING_FILL                         , 54  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SG_HIGH_DURING_FILL );
+REG64_FLD( C_OPCG_REG1_LBIST_SKITTER_CTL                           , 55  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_LBIST_SKITTER_CTL );
+REG64_FLD( C_OPCG_REG1_LBIST_SKITTER_CTL_LEN                       , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_LBIST_SKITTER_CTL_LEN );
+REG64_FLD( C_OPCG_REG1_MISR_MODE                                   , 57  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MISR_MODE  );
+REG64_FLD( C_OPCG_REG1_INFINITE_MODE                               , 58  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INFINITE_MODE );
+REG64_FLD( C_OPCG_REG1_NSL_FILL_COUNT                              , 59  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_NSL_FILL_COUNT );
+REG64_FLD( C_OPCG_REG1_NSL_FILL_COUNT_LEN                          , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_NSL_FILL_COUNT_LEN );
+
+REG64_FLD( EQ_OPCG_REG2_GO2                                        , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GO2        );
+REG64_FLD( EQ_OPCG_REG2_PRPG_WEIGHTING                             , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_WEIGHTING );
+REG64_FLD( EQ_OPCG_REG2_PRPG_WEIGHTING_LEN                         , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_WEIGHTING_LEN );
+REG64_FLD( EQ_OPCG_REG2_PRPG_VALUE                                 , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_VALUE );
+REG64_FLD( EQ_OPCG_REG2_PRPG_VALUE_LEN                             , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_VALUE_LEN );
+REG64_FLD( EQ_OPCG_REG2_PRPG_A_VAL                                 , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_A_VAL );
+REG64_FLD( EQ_OPCG_REG2_PRPG_A_VAL_LEN                             , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_A_VAL_LEN );
+REG64_FLD( EQ_OPCG_REG2_PRPG_B_VAL                                 , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_B_VAL );
+REG64_FLD( EQ_OPCG_REG2_PRPG_B_VAL_LEN                             , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_B_VAL_LEN );
+REG64_FLD( EQ_OPCG_REG2_PRPG_MODE                                  , 40  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_MODE  );
+REG64_FLD( EQ_OPCG_REG2_UNUSED41_63                                , 41  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED41_63 );
+REG64_FLD( EQ_OPCG_REG2_UNUSED41_63_LEN                            , 23  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED41_63_LEN );
+
+REG64_FLD( EX_OPCG_REG2_GO2                                        , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GO2        );
+REG64_FLD( EX_OPCG_REG2_PRPG_WEIGHTING                             , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_WEIGHTING );
+REG64_FLD( EX_OPCG_REG2_PRPG_WEIGHTING_LEN                         , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_WEIGHTING_LEN );
+REG64_FLD( EX_OPCG_REG2_PRPG_VALUE                                 , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_VALUE );
+REG64_FLD( EX_OPCG_REG2_PRPG_VALUE_LEN                             , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_VALUE_LEN );
+REG64_FLD( EX_OPCG_REG2_PRPG_A_VAL                                 , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_A_VAL );
+REG64_FLD( EX_OPCG_REG2_PRPG_A_VAL_LEN                             , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_A_VAL_LEN );
+REG64_FLD( EX_OPCG_REG2_PRPG_B_VAL                                 , 28  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_B_VAL );
+REG64_FLD( EX_OPCG_REG2_PRPG_B_VAL_LEN                             , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_B_VAL_LEN );
+REG64_FLD( EX_OPCG_REG2_PRPG_MODE                                  , 40  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_MODE  );
+REG64_FLD( EX_OPCG_REG2_UNUSED41_63                                , 41  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED41_63 );
+REG64_FLD( EX_OPCG_REG2_UNUSED41_63_LEN                            , 23  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED41_63_LEN );
+
+REG64_FLD( C_OPCG_REG2_GO2                                         , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GO2        );
+REG64_FLD( C_OPCG_REG2_PRPG_WEIGHTING                              , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_WEIGHTING );
+REG64_FLD( C_OPCG_REG2_PRPG_WEIGHTING_LEN                          , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_WEIGHTING_LEN );
+REG64_FLD( C_OPCG_REG2_PRPG_VALUE                                  , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_VALUE );
+REG64_FLD( C_OPCG_REG2_PRPG_VALUE_LEN                              , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_VALUE_LEN );
+REG64_FLD( C_OPCG_REG2_PRPG_A_VAL                                  , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_A_VAL );
+REG64_FLD( C_OPCG_REG2_PRPG_A_VAL_LEN                              , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_A_VAL_LEN );
+REG64_FLD( C_OPCG_REG2_PRPG_B_VAL                                  , 28  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_B_VAL );
+REG64_FLD( C_OPCG_REG2_PRPG_B_VAL_LEN                              , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_B_VAL_LEN );
+REG64_FLD( C_OPCG_REG2_PRPG_MODE                                   , 40  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PRPG_MODE  );
+REG64_FLD( C_OPCG_REG2_UNUSED41_63                                 , 41  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED41_63 );
+REG64_FLD( C_OPCG_REG2_UNUSED41_63_LEN                             , 23  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED41_63_LEN );
+
+REG64_FLD( EQ_PHYP_PURGE_CMD_REG_TRIGGER                           , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER    );
+REG64_FLD( EQ_PHYP_PURGE_CMD_REG_TYPE                              , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TYPE       );
+REG64_FLD( EQ_PHYP_PURGE_CMD_REG_TYPE_LEN                          , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( EQ_PHYP_PURGE_CMD_REG_BUSY                              , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_BUSY       );
+REG64_FLD( EQ_PHYP_PURGE_CMD_REG_PRGSM_BUSY_ON_THIS                , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PRGSM_BUSY_ON_THIS );
+REG64_FLD( EQ_PHYP_PURGE_CMD_REG_PRGSM_BUSY                        , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PRGSM_BUSY );
+REG64_FLD( EQ_PHYP_PURGE_CMD_REG_MEM                               , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MEM        );
+REG64_FLD( EQ_PHYP_PURGE_CMD_REG_MEM_LEN                           , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MEM_LEN    );
+REG64_FLD( EQ_PHYP_PURGE_CMD_REG_CGC                               , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CGC        );
+REG64_FLD( EQ_PHYP_PURGE_CMD_REG_CGC_LEN                           , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CGC_LEN    );
+REG64_FLD( EQ_PHYP_PURGE_CMD_REG_BANK                              , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_BANK       );
+REG64_FLD( EQ_PHYP_PURGE_CMD_REG_ERR                               , 29  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ERR        );
+
+REG64_FLD( EX_PHYP_PURGE_CMD_REG_TRIGGER                           , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER    );
+REG64_FLD( EX_PHYP_PURGE_CMD_REG_TYPE                              , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TYPE       );
+REG64_FLD( EX_PHYP_PURGE_CMD_REG_TYPE_LEN                          , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( EX_PHYP_PURGE_CMD_REG_BUSY                              , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_BUSY       );
+REG64_FLD( EX_PHYP_PURGE_CMD_REG_PRGSM_BUSY_ON_THIS                , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PRGSM_BUSY_ON_THIS );
+REG64_FLD( EX_PHYP_PURGE_CMD_REG_PRGSM_BUSY                        , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PRGSM_BUSY );
+REG64_FLD( EX_PHYP_PURGE_CMD_REG_MEM                               , 17  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MEM        );
+REG64_FLD( EX_PHYP_PURGE_CMD_REG_MEM_LEN                           , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MEM_LEN    );
+REG64_FLD( EX_PHYP_PURGE_CMD_REG_CGC                               , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CGC        );
+REG64_FLD( EX_PHYP_PURGE_CMD_REG_CGC_LEN                           , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CGC_LEN    );
+REG64_FLD( EX_PHYP_PURGE_CMD_REG_BANK                              , 28  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_BANK       );
+REG64_FLD( EX_PHYP_PURGE_CMD_REG_ERR                               , 29  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ERR        );
+
+REG64_FLD( EQ_PHYP_PURGE_REG_L3_REQ                                , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_REQ     );
+REG64_FLD( EQ_PHYP_PURGE_REG_L3_TTYPE                              , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_TTYPE   );
+REG64_FLD( EQ_PHYP_PURGE_REG_L3_TTYPE_LEN                          , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_TTYPE_LEN );
+REG64_FLD( EQ_PHYP_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE                , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LINE_DEL_ON_NEXT_CE );
+REG64_FLD( EQ_PHYP_PURGE_REG_L3_LINE_DEL_ON_ALL_CE                 , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LINE_DEL_ON_ALL_CE );
+REG64_FLD( EQ_PHYP_PURGE_REG_L3_BUSY_ERR                           , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_BUSY_ERR );
+REG64_FLD( EQ_PHYP_PURGE_REG_L3_MEMBER                             , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_MEMBER  );
+REG64_FLD( EQ_PHYP_PURGE_REG_L3_MEMBER_LEN                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_MEMBER_LEN );
+REG64_FLD( EQ_PHYP_PURGE_REG_L3_DIR_ADDR                           , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DIR_ADDR );
+REG64_FLD( EQ_PHYP_PURGE_REG_L3_DIR_ADDR_LEN                       , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DIR_ADDR_LEN );
+
+REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_REQ                             , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_REQ     );
+REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_TTYPE                           , 1   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_TTYPE   );
+REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_TTYPE_LEN                       , 4   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_TTYPE_LEN );
+REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE             , 5   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_LINE_DEL_ON_NEXT_CE );
+REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_LINE_DEL_ON_ALL_CE              , 6   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_LINE_DEL_ON_ALL_CE );
+REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_BUSY_ERR                        , 9   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_BUSY_ERR );
+REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_MEMBER                          , 12  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_MEMBER  );
+REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_MEMBER_LEN                      , 5   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_MEMBER_LEN );
+REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_DIR_ADDR                        , 17  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_DIR_ADDR );
+REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_DIR_ADDR_LEN                    , 12  , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_DIR_ADDR_LEN );
+
+REG64_FLD( EQ_PM_L2_RCMD_DIS_REG_L3_CFG                            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_CFG     );
+
+REG64_FLD( EX_PM_L2_RCMD_DIS_REG_L3_CFG                            , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_CFG     );
+
+REG64_FLD( EQ_PM_LCO_DIS_REG_L3_CFG                                , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_CFG     );
+
+REG64_FLD( EX_L3_PM_LCO_DIS_REG_L3_CFG                             , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_CFG     );
+
+REG64_FLD( EQ_PM_PURGE_REG_L3_REQ                                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_REQ     );
+REG64_FLD( EQ_PM_PURGE_REG_L3_BUSY_ERR                             , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_BUSY_ERR );
+REG64_FLD( EQ_PM_PURGE_REG_L3_ABORT                                , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_ABORT   );
+
+REG64_FLD( EX_L3_PM_PURGE_REG_L3_REQ                               , 0   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_REQ     );
+REG64_FLD( EX_L3_PM_PURGE_REG_L3_BUSY_ERR                          , 1   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_BUSY_ERR );
+REG64_FLD( EX_L3_PM_PURGE_REG_L3_ABORT                             , 2   , SH_UNT_EX_L3    , SH_ACS_SCOM     ,
+           SH_FLD_L3_ABORT   );
+
+REG64_FLD( EQ_PPE_XIDBGPRO_NULL_MSR_SIBRC                          , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( EQ_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                      , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( EQ_PPE_XIDBGPRO_NULL_MSR_WE                             , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( EQ_PPE_XIDBGPRO_NULL_MSR_LP                             , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( EX_PPE_XIDBGPRO_NULL_MSR_SIBRC                          , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( EX_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN                      , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( EX_PPE_XIDBGPRO_NULL_MSR_WE                             , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( EX_PPE_XIDBGPRO_NULL_MSR_LP                             , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( EQ_PPE_XIRAMDBG_NULL_MSR_SIBRC                          , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( EQ_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                      , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( EQ_PPE_XIRAMDBG_NULL_MSR_WE                             , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( EQ_PPE_XIRAMDBG_NULL_MSR_LP                             , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+REG64_FLD( EQ_PPE_XIRAMDBG_XIRAMRA_SPRG0                           , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( EQ_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                       , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( EX_PPE_XIRAMDBG_NULL_MSR_SIBRC                          , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( EX_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN                      , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( EX_PPE_XIRAMDBG_NULL_MSR_WE                             , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( EX_PPE_XIRAMDBG_NULL_MSR_LP                             , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+REG64_FLD( EX_PPE_XIRAMDBG_XIRAMRA_SPRG0                           , 32  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( EX_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN                       , 32  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( EQ_PPE_XIRAMEDR_XIRAMGA_IR                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR );
+REG64_FLD( EQ_PPE_XIRAMEDR_XIRAMGA_IR_LEN                          , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR_LEN );
+REG64_FLD( EQ_PPE_XIRAMEDR_EDR                                     , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EDR        );
+REG64_FLD( EQ_PPE_XIRAMEDR_EDR_LEN                                 , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_EDR_LEN    );
+
+REG64_FLD( EX_PPE_XIRAMEDR_XIRAMGA_IR                              , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR );
+REG64_FLD( EX_PPE_XIRAMEDR_XIRAMGA_IR_LEN                          , 32  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR_LEN );
+REG64_FLD( EX_PPE_XIRAMEDR_EDR                                     , 32  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_EDR        );
+REG64_FLD( EX_PPE_XIRAMEDR_EDR_LEN                                 , 32  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_EDR_LEN    );
+
+REG64_FLD( EQ_PPE_XIRAMGA_IR                                       , 0   , SH_UNT_EQ       , SH_ACS_SCOM_WO  ,
+           SH_FLD_IR         );
+REG64_FLD( EQ_PPE_XIRAMGA_IR_LEN                                   , 32  , SH_UNT_EQ       , SH_ACS_SCOM_WO  ,
+           SH_FLD_IR_LEN     );
+REG64_FLD( EQ_PPE_XIRAMGA_XIRAMRA_SPRG0                            , 32  , SH_UNT_EQ       , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( EQ_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                        , 32  , SH_UNT_EQ       , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( EX_PPE_XIRAMGA_IR                                       , 0   , SH_UNT_EX       , SH_ACS_SCOM_WO  ,
+           SH_FLD_IR         );
+REG64_FLD( EX_PPE_XIRAMGA_IR_LEN                                   , 32  , SH_UNT_EX       , SH_ACS_SCOM_WO  ,
+           SH_FLD_IR_LEN     );
+REG64_FLD( EX_PPE_XIRAMGA_XIRAMRA_SPRG0                            , 32  , SH_UNT_EX       , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( EX_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                        , 32  , SH_UNT_EX       , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( EQ_PPE_XIRAMRA_XIXCR_XCR                                , 1   , SH_UNT_EQ       , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR  );
+REG64_FLD( EQ_PPE_XIRAMRA_XIXCR_XCR_LEN                            , 3   , SH_UNT_EQ       , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR_LEN );
+REG64_FLD( EQ_PPE_XIRAMRA_SPRG0                                    , 32  , SH_UNT_EQ       , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0      );
+REG64_FLD( EQ_PPE_XIRAMRA_SPRG0_LEN                                , 32  , SH_UNT_EQ       , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0_LEN  );
+
+REG64_FLD( EX_PPE_XIRAMRA_XIXCR_XCR                                , 1   , SH_UNT_EX       , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR  );
+REG64_FLD( EX_PPE_XIRAMRA_XIXCR_XCR_LEN                            , 3   , SH_UNT_EX       , SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR_LEN );
+REG64_FLD( EX_PPE_XIRAMRA_SPRG0                                    , 32  , SH_UNT_EX       , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0      );
+REG64_FLD( EX_PPE_XIRAMRA_SPRG0_LEN                                , 32  , SH_UNT_EX       , SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0_LEN  );
+
+REG64_FLD( EQ_PPE_XIXCR_XCR                                        , 1   , SH_UNT_EQ       , SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR        );
+REG64_FLD( EQ_PPE_XIXCR_XCR_LEN                                    , 3   , SH_UNT_EQ       , SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR_LEN    );
+
+REG64_FLD( EX_PPE_XIXCR_XCR                                        , 1   , SH_UNT_EX       , SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR        );
+REG64_FLD( EX_PPE_XIXCR_XCR_LEN                                    , 3   , SH_UNT_EX       , SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR_LEN    );
+
+REG64_FLD( EQ_PPM_CGCR_CLKGLM_ASYNC_RESET                          , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_CLKGLM_ASYNC_RESET );
+REG64_FLD( EQ_PPM_CGCR_RESERVED_1_2                                , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_2 );
+REG64_FLD( EQ_PPM_CGCR_RESERVED_1_2_LEN                            , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_2_LEN );
+REG64_FLD( EQ_PPM_CGCR_CLKGLM_SEL                                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_CLKGLM_SEL );
+
+REG64_FLD( EX_PPM_CGCR_CLKGLM_ASYNC_RESET                          , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_CLKGLM_ASYNC_RESET );
+REG64_FLD( EX_PPM_CGCR_RESERVED_1_2                                , 1   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_2 );
+REG64_FLD( EX_PPM_CGCR_RESERVED_1_2_LEN                            , 2   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_2_LEN );
+REG64_FLD( EX_PPM_CGCR_CLKGLM_SEL                                  , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_CLKGLM_SEL );
+
+REG64_FLD( C_PPM_CGCR_CLKGLM_ASYNC_RESET                           , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_CLKGLM_ASYNC_RESET );
+REG64_FLD( C_PPM_CGCR_RESERVED_1_2                                 , 1   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_2 );
+REG64_FLD( C_PPM_CGCR_RESERVED_1_2_LEN                             , 2   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_1_2_LEN );
+REG64_FLD( C_PPM_CGCR_CLKGLM_SEL                                   , 3   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_CLKGLM_SEL );
+
+REG64_FLD( EQ_PPM_IVRMCR_IVRM_VID_VALID                            , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IVRM_VID_VALID );
+REG64_FLD( EQ_PPM_IVRMCR_IVRM_BYPASS_B                             , 1   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IVRM_BYPASS_B );
+REG64_FLD( EQ_PPM_IVRMCR_IVRM_POWERON                              , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IVRM_POWERON );
+REG64_FLD( EQ_PPM_IVRMCR_IVRM_VREG_SLOW_DC                         , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IVRM_VREG_SLOW_DC );
+REG64_FLD( EQ_PPM_IVRMCR_RESERVED_4_7                              , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_4_7 );
+REG64_FLD( EQ_PPM_IVRMCR_RESERVED_4_7_LEN                          , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_4_7_LEN );
+
+REG64_FLD( EX_PPM_IVRMCR_IVRM_VID_VALID                            , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IVRM_VID_VALID );
+REG64_FLD( EX_PPM_IVRMCR_IVRM_BYPASS_B                             , 1   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IVRM_BYPASS_B );
+REG64_FLD( EX_PPM_IVRMCR_IVRM_POWERON                              , 2   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IVRM_POWERON );
+REG64_FLD( EX_PPM_IVRMCR_IVRM_VREG_SLOW_DC                         , 3   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_IVRM_VREG_SLOW_DC );
+REG64_FLD( EX_PPM_IVRMCR_RESERVED_4_7                              , 4   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_4_7 );
+REG64_FLD( EX_PPM_IVRMCR_RESERVED_4_7_LEN                          , 4   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_4_7_LEN );
+
+REG64_FLD( C_PPM_IVRMCR_IVRM_VID_VALID                             , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IVRM_VID_VALID );
+REG64_FLD( C_PPM_IVRMCR_IVRM_BYPASS_B                              , 1   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IVRM_BYPASS_B );
+REG64_FLD( C_PPM_IVRMCR_IVRM_POWERON                               , 2   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IVRM_POWERON );
+REG64_FLD( C_PPM_IVRMCR_IVRM_VREG_SLOW_DC                          , 3   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_IVRM_VREG_SLOW_DC );
+REG64_FLD( C_PPM_IVRMCR_RESERVED_4_7                               , 4   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_4_7 );
+REG64_FLD( C_PPM_IVRMCR_RESERVED_4_7_LEN                           , 4   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_4_7_LEN );
+
+REG64_FLD( EQ_PPM_IVRMDVR_IVRM_IVID                                , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_IVID  );
+REG64_FLD( EQ_PPM_IVRMDVR_IVRM_IVID_LEN                            , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_IVID_LEN );
+REG64_FLD( EQ_PPM_IVRMDVR_RESERVED_8_10                            , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_10 );
+REG64_FLD( EQ_PPM_IVRMDVR_RESERVED_8_10_LEN                        , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_10_LEN );
+REG64_FLD( EQ_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE                  , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_PFET_STRENGTH_CORE );
+REG64_FLD( EQ_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE_LEN              , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_PFET_STRENGTH_CORE_LEN );
+REG64_FLD( EQ_PPM_IVRMDVR_RESERVED_16_18                           , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16_18 );
+REG64_FLD( EQ_PPM_IVRMDVR_RESERVED_16_18_LEN                       , 3   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16_18_LEN );
+REG64_FLD( EQ_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE                 , 19  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_PFET_STRENGTH_CACHE );
+REG64_FLD( EQ_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE_LEN             , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_PFET_STRENGTH_CACHE_LEN );
+
+REG64_FLD( EX_PPM_IVRMDVR_IVRM_IVID                                , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_IVID  );
+REG64_FLD( EX_PPM_IVRMDVR_IVRM_IVID_LEN                            , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_IVID_LEN );
+REG64_FLD( EX_PPM_IVRMDVR_RESERVED_8_10                            , 8   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_10 );
+REG64_FLD( EX_PPM_IVRMDVR_RESERVED_8_10_LEN                        , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_10_LEN );
+REG64_FLD( EX_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE                  , 11  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_PFET_STRENGTH_CORE );
+REG64_FLD( EX_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE_LEN              , 5   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_PFET_STRENGTH_CORE_LEN );
+REG64_FLD( EX_PPM_IVRMDVR_RESERVED_16_18                           , 16  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16_18 );
+REG64_FLD( EX_PPM_IVRMDVR_RESERVED_16_18_LEN                       , 3   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16_18_LEN );
+REG64_FLD( EX_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE                 , 19  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_PFET_STRENGTH_CACHE );
+REG64_FLD( EX_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE_LEN             , 5   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_PFET_STRENGTH_CACHE_LEN );
+
+REG64_FLD( C_PPM_IVRMDVR_IVRM_IVID                                 , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_IVID  );
+REG64_FLD( C_PPM_IVRMDVR_IVRM_IVID_LEN                             , 8   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_IVID_LEN );
+REG64_FLD( C_PPM_IVRMDVR_RESERVED_8_10                             , 8   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_10 );
+REG64_FLD( C_PPM_IVRMDVR_RESERVED_8_10_LEN                         , 3   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_8_10_LEN );
+REG64_FLD( C_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE                   , 11  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_PFET_STRENGTH_CORE );
+REG64_FLD( C_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE_LEN               , 5   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_PFET_STRENGTH_CORE_LEN );
+REG64_FLD( C_PPM_IVRMDVR_RESERVED_16_18                            , 16  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16_18 );
+REG64_FLD( C_PPM_IVRMDVR_RESERVED_16_18_LEN                        , 3   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_16_18_LEN );
+REG64_FLD( C_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE                  , 19  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_PFET_STRENGTH_CACHE );
+REG64_FLD( C_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE_LEN              , 5   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_IVRM_PFET_STRENGTH_CACHE_LEN );
+
+REG64_FLD( EQ_PPM_IVRMST_IVRM_VID_DONE                             , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IVRM_VID_DONE );
+
+REG64_FLD( EX_PPM_IVRMST_IVRM_VID_DONE                             , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IVRM_VID_DONE );
+
+REG64_FLD( C_PPM_IVRMST_IVRM_VID_DONE                              , 0   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_IVRM_VID_DONE );
+
+REG64_FLD( EQ_PPM_PFCS_VDD_PFET_FORCE_STATE                        , 0   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_FORCE_STATE );
+REG64_FLD( EQ_PPM_PFCS_VDD_PFET_FORCE_STATE_LEN                    , 2   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_FORCE_STATE_LEN );
+REG64_FLD( EQ_PPM_PFCS_VCS_PFET_FORCE_STATE                        , 2   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_FORCE_STATE );
+REG64_FLD( EQ_PPM_PFCS_VCS_PFET_FORCE_STATE_LEN                    , 2   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_FORCE_STATE_LEN );
+REG64_FLD( EQ_PPM_PFCS_VDD_PFET_VAL_OVERRIDE                       , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_VAL_OVERRIDE );
+REG64_FLD( EQ_PPM_PFCS_VDD_PFET_SEL_OVERRIDE                       , 5   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_SEL_OVERRIDE );
+REG64_FLD( EQ_PPM_PFCS_VCS_PFET_VAL_OVERRIDE                       , 6   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_VAL_OVERRIDE );
+REG64_FLD( EQ_PPM_PFCS_VCS_PFET_SEL_OVERRIDE                       , 7   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_SEL_OVERRIDE );
+REG64_FLD( EQ_PPM_PFCS_VDD_PFET_REGULATION_FINGER_EN               , 8   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_REGULATION_FINGER_EN );
+REG64_FLD( EQ_PPM_PFCS_VDD_PFET_REGULATION_FINGER_VALUE            , 9   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_REGULATION_FINGER_VALUE );
+REG64_FLD( EQ_PPM_PFCS_RESERVED_10_11                              , 10  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED_10_11 );
+REG64_FLD( EQ_PPM_PFCS_RESERVED_10_11_LEN                          , 2   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED_10_11_LEN );
+REG64_FLD( EQ_PPM_PFCS_VDD_PFET_ENABLE_VALUE                       , 12  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_ENABLE_VALUE );
+REG64_FLD( EQ_PPM_PFCS_VDD_PFET_ENABLE_VALUE_LEN                   , 8   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_ENABLE_VALUE_LEN );
+REG64_FLD( EQ_PPM_PFCS_VDD_PFET_SEL_VALUE                          , 20  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_SEL_VALUE );
+REG64_FLD( EQ_PPM_PFCS_VDD_PFET_SEL_VALUE_LEN                      , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_SEL_VALUE_LEN );
+REG64_FLD( EQ_PPM_PFCS_VCS_PFET_ENABLE_VALUE                       , 24  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_ENABLE_VALUE );
+REG64_FLD( EQ_PPM_PFCS_VCS_PFET_ENABLE_VALUE_LEN                   , 8   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_ENABLE_VALUE_LEN );
+REG64_FLD( EQ_PPM_PFCS_VCS_PFET_SEL_VALUE                          , 32  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_SEL_VALUE );
+REG64_FLD( EQ_PPM_PFCS_VCS_PFET_SEL_VALUE_LEN                      , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_SEL_VALUE_LEN );
+REG64_FLD( EQ_PPM_PFCS_VDD_PG_STATE                                , 42  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PG_STATE );
+REG64_FLD( EQ_PPM_PFCS_VDD_PG_STATE_LEN                            , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PG_STATE_LEN );
+REG64_FLD( EQ_PPM_PFCS_VDD_PG_SEL                                  , 46  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PG_SEL );
+REG64_FLD( EQ_PPM_PFCS_VDD_PG_SEL_LEN                              , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PG_SEL_LEN );
+REG64_FLD( EQ_PPM_PFCS_VCS_PG_STATE                                , 50  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PG_STATE );
+REG64_FLD( EQ_PPM_PFCS_VCS_PG_STATE_LEN                            , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PG_STATE_LEN );
+REG64_FLD( EQ_PPM_PFCS_VCS_PG_SEL                                  , 54  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PG_SEL );
+REG64_FLD( EQ_PPM_PFCS_VCS_PG_SEL_LEN                              , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PG_SEL_LEN );
+
+REG64_FLD( EX_PPM_PFCS_VDD_PFET_FORCE_STATE                        , 0   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_FORCE_STATE );
+REG64_FLD( EX_PPM_PFCS_VDD_PFET_FORCE_STATE_LEN                    , 2   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_FORCE_STATE_LEN );
+REG64_FLD( EX_PPM_PFCS_VCS_PFET_FORCE_STATE                        , 2   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_FORCE_STATE );
+REG64_FLD( EX_PPM_PFCS_VCS_PFET_FORCE_STATE_LEN                    , 2   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_FORCE_STATE_LEN );
+REG64_FLD( EX_PPM_PFCS_VDD_PFET_VAL_OVERRIDE                       , 4   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_VAL_OVERRIDE );
+REG64_FLD( EX_PPM_PFCS_VDD_PFET_SEL_OVERRIDE                       , 5   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_SEL_OVERRIDE );
+REG64_FLD( EX_PPM_PFCS_VCS_PFET_VAL_OVERRIDE                       , 6   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_VAL_OVERRIDE );
+REG64_FLD( EX_PPM_PFCS_VCS_PFET_SEL_OVERRIDE                       , 7   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_SEL_OVERRIDE );
+REG64_FLD( EX_PPM_PFCS_VDD_PFET_REGULATION_FINGER_EN               , 8   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_REGULATION_FINGER_EN );
+REG64_FLD( EX_PPM_PFCS_VDD_PFET_REGULATION_FINGER_VALUE            , 9   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_REGULATION_FINGER_VALUE );
+REG64_FLD( EX_PPM_PFCS_RESERVED_10_11                              , 10  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED_10_11 );
+REG64_FLD( EX_PPM_PFCS_RESERVED_10_11_LEN                          , 2   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED_10_11_LEN );
+REG64_FLD( EX_PPM_PFCS_VDD_PFET_ENABLE_VALUE                       , 12  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_ENABLE_VALUE );
+REG64_FLD( EX_PPM_PFCS_VDD_PFET_ENABLE_VALUE_LEN                   , 8   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_ENABLE_VALUE_LEN );
+REG64_FLD( EX_PPM_PFCS_VDD_PFET_SEL_VALUE                          , 20  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_SEL_VALUE );
+REG64_FLD( EX_PPM_PFCS_VDD_PFET_SEL_VALUE_LEN                      , 4   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_SEL_VALUE_LEN );
+REG64_FLD( EX_PPM_PFCS_VCS_PFET_ENABLE_VALUE                       , 24  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_ENABLE_VALUE );
+REG64_FLD( EX_PPM_PFCS_VCS_PFET_ENABLE_VALUE_LEN                   , 8   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_ENABLE_VALUE_LEN );
+REG64_FLD( EX_PPM_PFCS_VCS_PFET_SEL_VALUE                          , 32  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_SEL_VALUE );
+REG64_FLD( EX_PPM_PFCS_VCS_PFET_SEL_VALUE_LEN                      , 4   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_SEL_VALUE_LEN );
+REG64_FLD( EX_PPM_PFCS_VDD_PG_STATE                                , 42  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PG_STATE );
+REG64_FLD( EX_PPM_PFCS_VDD_PG_STATE_LEN                            , 4   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PG_STATE_LEN );
+REG64_FLD( EX_PPM_PFCS_VDD_PG_SEL                                  , 46  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PG_SEL );
+REG64_FLD( EX_PPM_PFCS_VDD_PG_SEL_LEN                              , 4   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PG_SEL_LEN );
+REG64_FLD( EX_PPM_PFCS_VCS_PG_STATE                                , 50  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PG_STATE );
+REG64_FLD( EX_PPM_PFCS_VCS_PG_STATE_LEN                            , 4   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PG_STATE_LEN );
+REG64_FLD( EX_PPM_PFCS_VCS_PG_SEL                                  , 54  , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PG_SEL );
+REG64_FLD( EX_PPM_PFCS_VCS_PG_SEL_LEN                              , 4   , SH_UNT_EX       , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PG_SEL_LEN );
+
+REG64_FLD( C_PPM_PFCS_VDD_PFET_FORCE_STATE                         , 0   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_FORCE_STATE );
+REG64_FLD( C_PPM_PFCS_VDD_PFET_FORCE_STATE_LEN                     , 2   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_FORCE_STATE_LEN );
+REG64_FLD( C_PPM_PFCS_VCS_PFET_FORCE_STATE                         , 2   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_FORCE_STATE );
+REG64_FLD( C_PPM_PFCS_VCS_PFET_FORCE_STATE_LEN                     , 2   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_FORCE_STATE_LEN );
+REG64_FLD( C_PPM_PFCS_VDD_PFET_VAL_OVERRIDE                        , 4   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_VAL_OVERRIDE );
+REG64_FLD( C_PPM_PFCS_VDD_PFET_SEL_OVERRIDE                        , 5   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_SEL_OVERRIDE );
+REG64_FLD( C_PPM_PFCS_VCS_PFET_VAL_OVERRIDE                        , 6   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_VAL_OVERRIDE );
+REG64_FLD( C_PPM_PFCS_VCS_PFET_SEL_OVERRIDE                        , 7   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_SEL_OVERRIDE );
+REG64_FLD( C_PPM_PFCS_VDD_PFET_REGULATION_FINGER_EN                , 8   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_REGULATION_FINGER_EN );
+REG64_FLD( C_PPM_PFCS_VDD_PFET_REGULATION_FINGER_VALUE             , 9   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_REGULATION_FINGER_VALUE );
+REG64_FLD( C_PPM_PFCS_RESERVED_10_11                               , 10  , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED_10_11 );
+REG64_FLD( C_PPM_PFCS_RESERVED_10_11_LEN                           , 2   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_RESERVED_10_11_LEN );
+REG64_FLD( C_PPM_PFCS_VDD_PFET_ENABLE_VALUE                        , 12  , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_ENABLE_VALUE );
+REG64_FLD( C_PPM_PFCS_VDD_PFET_ENABLE_VALUE_LEN                    , 8   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_ENABLE_VALUE_LEN );
+REG64_FLD( C_PPM_PFCS_VDD_PFET_SEL_VALUE                           , 20  , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_SEL_VALUE );
+REG64_FLD( C_PPM_PFCS_VDD_PFET_SEL_VALUE_LEN                       , 4   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PFET_SEL_VALUE_LEN );
+REG64_FLD( C_PPM_PFCS_VCS_PFET_ENABLE_VALUE                        , 24  , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_ENABLE_VALUE );
+REG64_FLD( C_PPM_PFCS_VCS_PFET_ENABLE_VALUE_LEN                    , 8   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_ENABLE_VALUE_LEN );
+REG64_FLD( C_PPM_PFCS_VCS_PFET_SEL_VALUE                           , 32  , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_SEL_VALUE );
+REG64_FLD( C_PPM_PFCS_VCS_PFET_SEL_VALUE_LEN                       , 4   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PFET_SEL_VALUE_LEN );
+REG64_FLD( C_PPM_PFCS_VDD_PG_STATE                                 , 42  , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PG_STATE );
+REG64_FLD( C_PPM_PFCS_VDD_PG_STATE_LEN                             , 4   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PG_STATE_LEN );
+REG64_FLD( C_PPM_PFCS_VDD_PG_SEL                                   , 46  , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PG_SEL );
+REG64_FLD( C_PPM_PFCS_VDD_PG_SEL_LEN                               , 4   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VDD_PG_SEL_LEN );
+REG64_FLD( C_PPM_PFCS_VCS_PG_STATE                                 , 50  , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PG_STATE );
+REG64_FLD( C_PPM_PFCS_VCS_PG_STATE_LEN                             , 4   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PG_STATE_LEN );
+REG64_FLD( C_PPM_PFCS_VCS_PG_SEL                                   , 54  , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PG_SEL );
+REG64_FLD( C_PPM_PFCS_VCS_PG_SEL_LEN                               , 4   , SH_UNT_C        , SH_ACS_SCOM2    ,
+           SH_FLD_VCS_PG_SEL_LEN );
+
+REG64_FLD( EQ_PPM_PFDLY_POWDN_DLY                                  , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWDN_DLY  );
+REG64_FLD( EQ_PPM_PFDLY_POWDN_DLY_LEN                              , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWDN_DLY_LEN );
+REG64_FLD( EQ_PPM_PFDLY_POWUP_DLY                                  , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWUP_DLY  );
+REG64_FLD( EQ_PPM_PFDLY_POWUP_DLY_LEN                              , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWUP_DLY_LEN );
+
+REG64_FLD( EX_PPM_PFDLY_POWDN_DLY                                  , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWDN_DLY  );
+REG64_FLD( EX_PPM_PFDLY_POWDN_DLY_LEN                              , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWDN_DLY_LEN );
+REG64_FLD( EX_PPM_PFDLY_POWUP_DLY                                  , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWUP_DLY  );
+REG64_FLD( EX_PPM_PFDLY_POWUP_DLY_LEN                              , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWUP_DLY_LEN );
+
+REG64_FLD( C_PPM_PFDLY_POWDN_DLY                                   , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWDN_DLY  );
+REG64_FLD( C_PPM_PFDLY_POWDN_DLY_LEN                               , 4   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWDN_DLY_LEN );
+REG64_FLD( C_PPM_PFDLY_POWUP_DLY                                   , 4   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWUP_DLY  );
+REG64_FLD( C_PPM_PFDLY_POWUP_DLY_LEN                               , 4   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_POWUP_DLY_LEN );
+
+REG64_FLD( EQ_PPM_PFOFF_VDD_VOFF_SEL                               , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDD_VOFF_SEL );
+REG64_FLD( EQ_PPM_PFOFF_VDD_VOFF_SEL_LEN                           , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDD_VOFF_SEL_LEN );
+REG64_FLD( EQ_PPM_PFOFF_VCS_VOFF_SEL                               , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VCS_VOFF_SEL );
+REG64_FLD( EQ_PPM_PFOFF_VCS_VOFF_SEL_LEN                           , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VCS_VOFF_SEL_LEN );
+
+REG64_FLD( EX_PPM_PFOFF_VDD_VOFF_SEL                               , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDD_VOFF_SEL );
+REG64_FLD( EX_PPM_PFOFF_VDD_VOFF_SEL_LEN                           , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDD_VOFF_SEL_LEN );
+REG64_FLD( EX_PPM_PFOFF_VCS_VOFF_SEL                               , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VCS_VOFF_SEL );
+REG64_FLD( EX_PPM_PFOFF_VCS_VOFF_SEL_LEN                           , 4   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VCS_VOFF_SEL_LEN );
+
+REG64_FLD( C_PPM_PFOFF_VDD_VOFF_SEL                                , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDD_VOFF_SEL );
+REG64_FLD( C_PPM_PFOFF_VDD_VOFF_SEL_LEN                            , 4   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDD_VOFF_SEL_LEN );
+REG64_FLD( C_PPM_PFOFF_VCS_VOFF_SEL                                , 4   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_VCS_VOFF_SEL );
+REG64_FLD( C_PPM_PFOFF_VCS_VOFF_SEL_LEN                            , 4   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_VCS_VOFF_SEL_LEN );
+
+REG64_FLD( EQ_PPM_PIG_REQ_INTR_TYPE                                , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_REQ_INTR_TYPE );
+REG64_FLD( EQ_PPM_PIG_REQ_INTR_TYPE_LEN                            , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_REQ_INTR_TYPE_LEN );
+REG64_FLD( EQ_PPM_PIG_REQ_INTR_PAYLOAD                             , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_REQ_INTR_PAYLOAD );
+REG64_FLD( EQ_PPM_PIG_REQ_INTR_PAYLOAD_LEN                         , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_REQ_INTR_PAYLOAD_LEN );
+REG64_FLD( EQ_PPM_PIG_GRANTED_PACKET                               , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GRANTED_PACKET );
+REG64_FLD( EQ_PPM_PIG_GRANTED_PACKET_LEN                           , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GRANTED_PACKET_LEN );
+REG64_FLD( EQ_PPM_PIG_INTR_GRANTED                                 , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INTR_GRANTED );
+REG64_FLD( EQ_PPM_PIG_GRANTED_SOURCE                               , 34  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GRANTED_SOURCE );
+REG64_FLD( EQ_PPM_PIG_GRANTED_SOURCE_LEN                           , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GRANTED_SOURCE_LEN );
+REG64_FLD( EQ_PPM_PIG_PENDING_SOURCE                               , 37  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PENDING_SOURCE );
+REG64_FLD( EQ_PPM_PIG_PENDING_SOURCE_LEN                           , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PENDING_SOURCE_LEN );
+REG64_FLD( EQ_PPM_PIG_NETWORK_RESET_OCCURRED                       , 40  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_NETWORK_RESET_OCCURRED );
+
+REG64_FLD( EX_PPM_PIG_REQ_INTR_TYPE                                , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_REQ_INTR_TYPE );
+REG64_FLD( EX_PPM_PIG_REQ_INTR_TYPE_LEN                            , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_REQ_INTR_TYPE_LEN );
+REG64_FLD( EX_PPM_PIG_REQ_INTR_PAYLOAD                             , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_REQ_INTR_PAYLOAD );
+REG64_FLD( EX_PPM_PIG_REQ_INTR_PAYLOAD_LEN                         , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_REQ_INTR_PAYLOAD_LEN );
+REG64_FLD( EX_PPM_PIG_GRANTED_PACKET                               , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GRANTED_PACKET );
+REG64_FLD( EX_PPM_PIG_GRANTED_PACKET_LEN                           , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GRANTED_PACKET_LEN );
+REG64_FLD( EX_PPM_PIG_INTR_GRANTED                                 , 32  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INTR_GRANTED );
+REG64_FLD( EX_PPM_PIG_GRANTED_SOURCE                               , 34  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GRANTED_SOURCE );
+REG64_FLD( EX_PPM_PIG_GRANTED_SOURCE_LEN                           , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GRANTED_SOURCE_LEN );
+REG64_FLD( EX_PPM_PIG_PENDING_SOURCE                               , 37  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PENDING_SOURCE );
+REG64_FLD( EX_PPM_PIG_PENDING_SOURCE_LEN                           , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PENDING_SOURCE_LEN );
+REG64_FLD( EX_PPM_PIG_NETWORK_RESET_OCCURRED                       , 40  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_NETWORK_RESET_OCCURRED );
+
+REG64_FLD( C_PPM_PIG_REQ_INTR_TYPE                                 , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_REQ_INTR_TYPE );
+REG64_FLD( C_PPM_PIG_REQ_INTR_TYPE_LEN                             , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_REQ_INTR_TYPE_LEN );
+REG64_FLD( C_PPM_PIG_REQ_INTR_PAYLOAD                              , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_REQ_INTR_PAYLOAD );
+REG64_FLD( C_PPM_PIG_REQ_INTR_PAYLOAD_LEN                          , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_REQ_INTR_PAYLOAD_LEN );
+REG64_FLD( C_PPM_PIG_GRANTED_PACKET                                , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GRANTED_PACKET );
+REG64_FLD( C_PPM_PIG_GRANTED_PACKET_LEN                            , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GRANTED_PACKET_LEN );
+REG64_FLD( C_PPM_PIG_INTR_GRANTED                                  , 32  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INTR_GRANTED );
+REG64_FLD( C_PPM_PIG_GRANTED_SOURCE                                , 34  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GRANTED_SOURCE );
+REG64_FLD( C_PPM_PIG_GRANTED_SOURCE_LEN                            , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GRANTED_SOURCE_LEN );
+REG64_FLD( C_PPM_PIG_PENDING_SOURCE                                , 37  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PENDING_SOURCE );
+REG64_FLD( C_PPM_PIG_PENDING_SOURCE_LEN                            , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PENDING_SOURCE_LEN );
+REG64_FLD( C_PPM_PIG_NETWORK_RESET_OCCURRED                        , 40  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_NETWORK_RESET_OCCURRED );
+
+REG64_FLD( EQ_PPM_SCRATCH0_DATA                                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_PPM_SCRATCH0_DATA_LEN                                , 64  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EX_PPM_SCRATCH0_DATA                                    , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EX_PPM_SCRATCH0_DATA_LEN                                , 64  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( C_PPM_SCRATCH0_DATA                                     , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( C_PPM_SCRATCH0_DATA_LEN                                 , 64  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_PPM_SCRATCH1_DATA                                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_PPM_SCRATCH1_DATA_LEN                                , 64  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EX_PPM_SCRATCH1_DATA                                    , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( EX_PPM_SCRATCH1_DATA_LEN                                , 64  , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( C_PPM_SCRATCH1_DATA                                     , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA       );
+REG64_FLD( C_PPM_SCRATCH1_DATA_LEN                                 , 64  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_PPM_SPWKUP_FSP_FSP_SPECIAL_WKUP                      , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FSP_SPECIAL_WKUP );
+
+REG64_FLD( EX_PPM_SPWKUP_FSP_FSP_SPECIAL_WKUP                      , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FSP_SPECIAL_WKUP );
+
+REG64_FLD( C_PPM_SPWKUP_FSP_FSP_SPECIAL_WKUP                       , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_FSP_SPECIAL_WKUP );
+
+REG64_FLD( EQ_PPM_SPWKUP_HYP_HYP_SPECIAL_WKUP                      , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_SPECIAL_WKUP );
+
+REG64_FLD( EX_PPM_SPWKUP_HYP_HYP_SPECIAL_WKUP                      , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_SPECIAL_WKUP );
+
+REG64_FLD( C_PPM_SPWKUP_HYP_HYP_SPECIAL_WKUP                       , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_HYP_SPECIAL_WKUP );
+
+REG64_FLD( EQ_PPM_SPWKUP_OCC_OCC_SPECIAL_WKUP                      , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_SPECIAL_WKUP );
+
+REG64_FLD( EX_PPM_SPWKUP_OCC_OCC_SPECIAL_WKUP                      , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_SPECIAL_WKUP );
+
+REG64_FLD( C_PPM_SPWKUP_OCC_OCC_SPECIAL_WKUP                       , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_SPECIAL_WKUP );
+
+REG64_FLD( EQ_PPM_SPWKUP_OTR_OTR_SPECIAL_WKUP                      , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OTR_SPECIAL_WKUP );
+
+REG64_FLD( EX_PPM_SPWKUP_OTR_OTR_SPECIAL_WKUP                      , 0   , SH_UNT_EX       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OTR_SPECIAL_WKUP );
+
+REG64_FLD( C_PPM_SPWKUP_OTR_OTR_SPECIAL_WKUP                       , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_OTR_SPECIAL_WKUP );
+
+REG64_FLD( EQ_PPM_VDMCR_VDM_POWERON                                , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_VDM_POWERON );
+REG64_FLD( EQ_PPM_VDMCR_VDM_DISABLE                                , 1   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_VDM_DISABLE );
+
+REG64_FLD( EX_PPM_VDMCR_VDM_POWERON                                , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_VDM_POWERON );
+REG64_FLD( EX_PPM_VDMCR_VDM_DISABLE                                , 1   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_VDM_DISABLE );
+
+REG64_FLD( C_PPM_VDMCR_VDM_POWERON                                 , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_VDM_POWERON );
+REG64_FLD( C_PPM_VDMCR_VDM_DISABLE                                 , 1   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_VDM_DISABLE );
+
+REG64_FLD( EQ_PRD_PURGE_CMD_REG_TRIGGER                            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER    );
+REG64_FLD( EQ_PRD_PURGE_CMD_REG_TYPE                               , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TYPE       );
+REG64_FLD( EQ_PRD_PURGE_CMD_REG_TYPE_LEN                           , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( EQ_PRD_PURGE_CMD_REG_BUSY                               , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_BUSY       );
+REG64_FLD( EQ_PRD_PURGE_CMD_REG_PRGSM_BUSY_ON_THIS                 , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PRGSM_BUSY_ON_THIS );
+REG64_FLD( EQ_PRD_PURGE_CMD_REG_PRGSM_BUSY                         , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PRGSM_BUSY );
+REG64_FLD( EQ_PRD_PURGE_CMD_REG_MEM                                , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MEM        );
+REG64_FLD( EQ_PRD_PURGE_CMD_REG_MEM_LEN                            , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MEM_LEN    );
+REG64_FLD( EQ_PRD_PURGE_CMD_REG_CGC                                , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CGC        );
+REG64_FLD( EQ_PRD_PURGE_CMD_REG_CGC_LEN                            , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CGC_LEN    );
+REG64_FLD( EQ_PRD_PURGE_CMD_REG_BANK                               , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_BANK       );
+REG64_FLD( EQ_PRD_PURGE_CMD_REG_ERR                                , 29  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ERR        );
+
+REG64_FLD( EX_PRD_PURGE_CMD_REG_TRIGGER                            , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER    );
+REG64_FLD( EX_PRD_PURGE_CMD_REG_TYPE                               , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TYPE       );
+REG64_FLD( EX_PRD_PURGE_CMD_REG_TYPE_LEN                           , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TYPE_LEN   );
+REG64_FLD( EX_PRD_PURGE_CMD_REG_BUSY                               , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_BUSY       );
+REG64_FLD( EX_PRD_PURGE_CMD_REG_PRGSM_BUSY_ON_THIS                 , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PRGSM_BUSY_ON_THIS );
+REG64_FLD( EX_PRD_PURGE_CMD_REG_PRGSM_BUSY                         , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PRGSM_BUSY );
+REG64_FLD( EX_PRD_PURGE_CMD_REG_MEM                                , 17  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MEM        );
+REG64_FLD( EX_PRD_PURGE_CMD_REG_MEM_LEN                            , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MEM_LEN    );
+REG64_FLD( EX_PRD_PURGE_CMD_REG_CGC                                , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CGC        );
+REG64_FLD( EX_PRD_PURGE_CMD_REG_CGC_LEN                            , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CGC_LEN    );
+REG64_FLD( EX_PRD_PURGE_CMD_REG_BANK                               , 28  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_BANK       );
+REG64_FLD( EX_PRD_PURGE_CMD_REG_ERR                                , 29  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ERR        );
+
+REG64_FLD( EQ_PRD_PURGE_REG_L3_REQ                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_REQ     );
+REG64_FLD( EQ_PRD_PURGE_REG_L3_TTYPE                               , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_TTYPE   );
+REG64_FLD( EQ_PRD_PURGE_REG_L3_TTYPE_LEN                           , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_TTYPE_LEN );
+REG64_FLD( EQ_PRD_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE                 , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LINE_DEL_ON_NEXT_CE );
+REG64_FLD( EQ_PRD_PURGE_REG_L3_LINE_DEL_ON_ALL_CE                  , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LINE_DEL_ON_ALL_CE );
+REG64_FLD( EQ_PRD_PURGE_REG_L3_BUSY_ERR                            , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_BUSY_ERR );
+REG64_FLD( EQ_PRD_PURGE_REG_L3_MEMBER                              , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_MEMBER  );
+REG64_FLD( EQ_PRD_PURGE_REG_L3_MEMBER_LEN                          , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_MEMBER_LEN );
+REG64_FLD( EQ_PRD_PURGE_REG_L3_DIR_ADDR                            , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DIR_ADDR );
+REG64_FLD( EQ_PRD_PURGE_REG_L3_DIR_ADDR_LEN                        , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DIR_ADDR_LEN );
+
+REG64_FLD( EX_PRD_PURGE_REG_L3_REQ                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_REQ     );
+REG64_FLD( EX_PRD_PURGE_REG_L3_TTYPE                               , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_TTYPE   );
+REG64_FLD( EX_PRD_PURGE_REG_L3_TTYPE_LEN                           , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_TTYPE_LEN );
+REG64_FLD( EX_PRD_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE                 , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LINE_DEL_ON_NEXT_CE );
+REG64_FLD( EX_PRD_PURGE_REG_L3_LINE_DEL_ON_ALL_CE                  , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_LINE_DEL_ON_ALL_CE );
+REG64_FLD( EX_PRD_PURGE_REG_L3_BUSY_ERR                            , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_BUSY_ERR );
+REG64_FLD( EX_PRD_PURGE_REG_L3_MEMBER                              , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_MEMBER  );
+REG64_FLD( EX_PRD_PURGE_REG_L3_MEMBER_LEN                          , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_MEMBER_LEN );
+REG64_FLD( EX_PRD_PURGE_REG_L3_DIR_ADDR                            , 17  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DIR_ADDR );
+REG64_FLD( EX_PRD_PURGE_REG_L3_DIR_ADDR_LEN                        , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_L3_DIR_ADDR_LEN );
+
+REG64_FLD( EQ_PRE_COUNTER_REG_COUNTER                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COUNTER    );
+REG64_FLD( EQ_PRE_COUNTER_REG_COUNTER_LEN                          , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_COUNTER_LEN );
+
+REG64_FLD( EX_PRE_COUNTER_REG_COUNTER                              , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COUNTER    );
+REG64_FLD( EX_PRE_COUNTER_REG_COUNTER_LEN                          , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_COUNTER_LEN );
+
+REG64_FLD( C_PRE_COUNTER_REG_COUNTER                               , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COUNTER    );
+REG64_FLD( C_PRE_COUNTER_REG_COUNTER_LEN                           , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_COUNTER_LEN );
+
+REG64_FLD( EQ_PROTECT_MODE_REG_READ_ENABLE                         , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_READ_ENABLE );
+REG64_FLD( EQ_PROTECT_MODE_REG_WRITE_ENABLE                        , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( EX_PROTECT_MODE_REG_READ_ENABLE                         , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_READ_ENABLE );
+REG64_FLD( EX_PROTECT_MODE_REG_WRITE_ENABLE                        , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( C_PROTECT_MODE_REG_READ_ENABLE                          , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_READ_ENABLE );
+REG64_FLD( C_PROTECT_MODE_REG_WRITE_ENABLE                         , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_WRITE_ENABLE );
+
+REG64_FLD( EQ_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_WDATA_PARITY );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY                  , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_PARITY );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY              , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_WDATA_PARITY );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_DL_RETURN_P0                        , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_P0 );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_UL_RDATA_PARITY                     , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UL_RDATA_PARITY );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_UL_P0                               , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UL_P0      );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE         , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE               , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_P2S_MACHINE );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH     , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH     , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD                 , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_WRITE_NVLD );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD                  , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_READ_NVLD );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID               , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_ADDR_INVALID );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY                  , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_COMMAND_PARITY );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                     , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_GENERAL_TIMEOUT );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( EQ_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( EX_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                    , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_WDATA_PARITY );
+REG64_FLD( EX_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY                  , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_PARITY );
+REG64_FLD( EX_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY              , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_WDATA_PARITY );
+REG64_FLD( EX_PSCOM_ERROR_MASK_DL_RETURN_P0                        , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_P0 );
+REG64_FLD( EX_PSCOM_ERROR_MASK_UL_RDATA_PARITY                     , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UL_RDATA_PARITY );
+REG64_FLD( EX_PSCOM_ERROR_MASK_UL_P0                               , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UL_P0      );
+REG64_FLD( EX_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE         , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( EX_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE               , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_P2S_MACHINE );
+REG64_FLD( EX_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH     , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( EX_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( EX_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH     , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( EX_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD                 , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_WRITE_NVLD );
+REG64_FLD( EX_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD                  , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_READ_NVLD );
+REG64_FLD( EX_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID               , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_ADDR_INVALID );
+REG64_FLD( EX_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY                  , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PCB_COMMAND_PARITY );
+REG64_FLD( EX_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                     , 15  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_GENERAL_TIMEOUT );
+REG64_FLD( EX_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( EX_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( C_PSCOM_ERROR_MASK_PCB_WDATA_PARITY                     , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PCB_WDATA_PARITY );
+REG64_FLD( C_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY                   , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PCB_ADDRESS_PARITY );
+REG64_FLD( C_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY               , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_WDATA_PARITY );
+REG64_FLD( C_PSCOM_ERROR_MASK_DL_RETURN_P0                         , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DL_RETURN_P0 );
+REG64_FLD( C_PSCOM_ERROR_MASK_UL_RDATA_PARITY                      , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UL_RDATA_PARITY );
+REG64_FLD( C_PSCOM_ERROR_MASK_UL_P0                                , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UL_P0      );
+REG64_FLD( C_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE          , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( C_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE                , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PARITY_ON_P2S_MACHINE );
+REG64_FLD( C_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH      , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( C_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( C_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH      , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( C_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD                  , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_WRITE_NVLD );
+REG64_FLD( C_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD                   , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_READ_NVLD );
+REG64_FLD( C_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID                , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PARALLEL_ADDR_INVALID );
+REG64_FLD( C_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY                   , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PCB_COMMAND_PARITY );
+REG64_FLD( C_PSCOM_ERROR_MASK_GENERAL_TIMEOUT                      , 15  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_GENERAL_TIMEOUT );
+REG64_FLD( C_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( C_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( EQ_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR        , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR );
+REG64_FLD( EQ_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR       , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR );
+REG64_FLD( EQ_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR           , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR );
+REG64_FLD( EQ_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR );
+REG64_FLD( EQ_PSCOM_MODE_REG_WATCHDOG_ENABLE                       , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WATCHDOG_ENABLE );
+REG64_FLD( EQ_PSCOM_MODE_REG_SCOM_HANG_LIMIT                       , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT );
+REG64_FLD( EQ_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT_LEN );
+REG64_FLD( EQ_PSCOM_MODE_REG_FORCE_ALL_RINGS                       , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ALL_RINGS );
+REG64_FLD( EQ_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE );
+REG64_FLD( EQ_PSCOM_MODE_REG_RESERVED_LT                           , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT );
+REG64_FLD( EQ_PSCOM_MODE_REG_RESERVED_LT_LEN                       , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT_LEN );
+
+REG64_FLD( EX_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR        , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR );
+REG64_FLD( EX_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR       , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR );
+REG64_FLD( EX_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR           , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR );
+REG64_FLD( EX_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR );
+REG64_FLD( EX_PSCOM_MODE_REG_WATCHDOG_ENABLE                       , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WATCHDOG_ENABLE );
+REG64_FLD( EX_PSCOM_MODE_REG_SCOM_HANG_LIMIT                       , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT );
+REG64_FLD( EX_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                   , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT_LEN );
+REG64_FLD( EX_PSCOM_MODE_REG_FORCE_ALL_RINGS                       , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ALL_RINGS );
+REG64_FLD( EX_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE );
+REG64_FLD( EX_PSCOM_MODE_REG_RESERVED_LT                           , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT );
+REG64_FLD( EX_PSCOM_MODE_REG_RESERVED_LT_LEN                       , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT_LEN );
+
+REG64_FLD( C_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR         , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR );
+REG64_FLD( C_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR        , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR );
+REG64_FLD( C_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR            , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR );
+REG64_FLD( C_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR  , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR );
+REG64_FLD( C_PSCOM_MODE_REG_WATCHDOG_ENABLE                        , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_WATCHDOG_ENABLE );
+REG64_FLD( C_PSCOM_MODE_REG_SCOM_HANG_LIMIT                        , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT );
+REG64_FLD( C_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN                    , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SCOM_HANG_LIMIT_LEN );
+REG64_FLD( C_PSCOM_MODE_REG_FORCE_ALL_RINGS                        , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_ALL_RINGS );
+REG64_FLD( C_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE );
+REG64_FLD( C_PSCOM_MODE_REG_RESERVED_LT                            , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT );
+REG64_FLD( C_PSCOM_MODE_REG_RESERVED_LT_LEN                        , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_LT_LEN );
+
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_WDATA_PARITY );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0      , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_P0 );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_RDATA_PARITY );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0             , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_P0 );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT   , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_GENERAL_TIMEOUT );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY      , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_WDATA_PARITY );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY    , 19  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_ADDRESS_PARITY );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0          , 21  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_P0 );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY       , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_RDATA_PARITY );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0                 , 23  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_P0 );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27  , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD   , 29  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD    , 30  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_READ_NVLD );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY    , 32  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_COMMAND_PARITY );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT       , 33  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_GENERAL_TIMEOUT );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34  , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35  , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY  , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_WDATA_PARITY );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0      , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_P0 );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY   , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_RDATA_PARITY );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0             , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_P0 );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT_EX       ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_EX       ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT_EX       ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT   , 15  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_GENERAL_TIMEOUT );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_EX       ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_EX       ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY      , 18  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_WDATA_PARITY );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY    , 19  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_ADDRESS_PARITY );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0          , 21  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_P0 );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY       , 22  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_RDATA_PARITY );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0                 , 23  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_P0 );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27  , SH_UNT_EX       ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD   , 29  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD    , 30  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_READ_NVLD );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY    , 32  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_COMMAND_PARITY );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT       , 33  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_GENERAL_TIMEOUT );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34  , SH_UNT_EX       ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35  , SH_UNT_EX       ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY   , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_WDATA_PARITY );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0       , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_DL_RETURN_P0 );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY    , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_RDATA_PARITY );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0              , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_UL_P0 );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8   , SH_UNT_C        ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9   , SH_UNT_C        ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10  , SH_UNT_C        ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT    , 15  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ACCUMULATED_GENERAL_TIMEOUT );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16  , SH_UNT_C        ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17  , SH_UNT_C        ,
+           SH_ACS_SCOM     , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY       , 18  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_WDATA_PARITY );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY     , 19  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_ADDRESS_PARITY );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0           , 21  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_DL_RETURN_P0 );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY        , 22  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_RDATA_PARITY );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0                  , 23  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_UL_P0 );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE  , 25  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27  , SH_UNT_C        ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD    , 29  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD     , 30  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_READ_NVLD );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID  , 31  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY     , 32  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_PCB_COMMAND_PARITY );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT        , 33  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRAPPED_GENERAL_TIMEOUT );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34  , SH_UNT_C        ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION );
+REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35  , SH_UNT_C        ,
+           SH_ACS_SCOM     , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER );
+
+REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_32                            , 32  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32 );
+REG64_FLD( EX_L2_PWM_EVENTS_FREQ_SCALE_A_THRESHOLD                 , 33  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_FREQ_SCALE_A_THRESHOLD );
+REG64_FLD( EX_L2_PWM_EVENTS_FREQ_SCALE_A_THRESHOLD_LEN             , 7   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_FREQ_SCALE_A_THRESHOLD_LEN );
+REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_40                            , 40  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40 );
+REG64_FLD( EX_L2_PWM_EVENTS_FREQ_SCALE_B_THRESHOLD                 , 41  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_FREQ_SCALE_B_THRESHOLD );
+REG64_FLD( EX_L2_PWM_EVENTS_FREQ_SCALE_B_THRESHOLD_LEN             , 7   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_FREQ_SCALE_B_THRESHOLD_LEN );
+REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_48                            , 48  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48 );
+REG64_FLD( EX_L2_PWM_EVENTS_PSTATE_A_THRESHOLD                     , 49  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_PSTATE_A_THRESHOLD );
+REG64_FLD( EX_L2_PWM_EVENTS_PSTATE_A_THRESHOLD_LEN                 , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_PSTATE_A_THRESHOLD_LEN );
+REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_52                            , 52  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52 );
+REG64_FLD( EX_L2_PWM_EVENTS_PSTATE_B_THRESHOLD                     , 53  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_PSTATE_B_THRESHOLD );
+REG64_FLD( EX_L2_PWM_EVENTS_PSTATE_B_THRESHOLD_LEN                 , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_PSTATE_B_THRESHOLD_LEN );
+REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_56                            , 56  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56 );
+REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_57                            , 57  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_57 );
+REG64_FLD( EX_L2_PWM_EVENTS_EVENT_MUX_SELECTS                      , 58  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT_MUX_SELECTS );
+REG64_FLD( EX_L2_PWM_EVENTS_EVENT_MUX_SELECTS_LEN                  , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT_MUX_SELECTS_LEN );
+REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_60                            , 60  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_60 );
+REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_61                            , 61  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_61 );
+REG64_FLD( EX_L2_PWM_EVENTS_PMCM_THRESHOLD                         , 62  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMCM_THRESHOLD );
+REG64_FLD( EX_L2_PWM_EVENTS_PMCM_THRESHOLD_LEN                     , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMCM_THRESHOLD_LEN );
+
+REG64_FLD( C_PWM_EVENTS_RESERVED_32                                , 32  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_32 );
+REG64_FLD( C_PWM_EVENTS_FREQ_SCALE_A_THRESHOLD                     , 33  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_FREQ_SCALE_A_THRESHOLD );
+REG64_FLD( C_PWM_EVENTS_FREQ_SCALE_A_THRESHOLD_LEN                 , 7   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_FREQ_SCALE_A_THRESHOLD_LEN );
+REG64_FLD( C_PWM_EVENTS_RESERVED_40                                , 40  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_40 );
+REG64_FLD( C_PWM_EVENTS_FREQ_SCALE_B_THRESHOLD                     , 41  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_FREQ_SCALE_B_THRESHOLD );
+REG64_FLD( C_PWM_EVENTS_FREQ_SCALE_B_THRESHOLD_LEN                 , 7   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_FREQ_SCALE_B_THRESHOLD_LEN );
+REG64_FLD( C_PWM_EVENTS_RESERVED_48                                , 48  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_48 );
+REG64_FLD( C_PWM_EVENTS_PSTATE_A_THRESHOLD                         , 49  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_PSTATE_A_THRESHOLD );
+REG64_FLD( C_PWM_EVENTS_PSTATE_A_THRESHOLD_LEN                     , 3   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_PSTATE_A_THRESHOLD_LEN );
+REG64_FLD( C_PWM_EVENTS_RESERVED_52                                , 52  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_52 );
+REG64_FLD( C_PWM_EVENTS_PSTATE_B_THRESHOLD                         , 53  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_PSTATE_B_THRESHOLD );
+REG64_FLD( C_PWM_EVENTS_PSTATE_B_THRESHOLD_LEN                     , 3   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_PSTATE_B_THRESHOLD_LEN );
+REG64_FLD( C_PWM_EVENTS_RESERVED_56                                , 56  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_56 );
+REG64_FLD( C_PWM_EVENTS_RESERVED_57                                , 57  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_57 );
+REG64_FLD( C_PWM_EVENTS_EVENT_MUX_SELECTS                          , 58  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT_MUX_SELECTS );
+REG64_FLD( C_PWM_EVENTS_EVENT_MUX_SELECTS_LEN                      , 2   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_EVENT_MUX_SELECTS_LEN );
+REG64_FLD( C_PWM_EVENTS_RESERVED_60                                , 60  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_60 );
+REG64_FLD( C_PWM_EVENTS_RESERVED_61                                , 61  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_61 );
+REG64_FLD( C_PWM_EVENTS_PMCM_THRESHOLD                             , 62  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMCM_THRESHOLD );
+REG64_FLD( C_PWM_EVENTS_PMCM_THRESHOLD_LEN                         , 2   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMCM_THRESHOLD_LEN );
+
+REG64_FLD( EQ_QPPM_DPLL_CTRL_LOCK_SEL                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_LOCK_SEL   );
+REG64_FLD( EQ_QPPM_DPLL_CTRL_ENABLE_JUMP_PROTECT                   , 1   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ENABLE_JUMP_PROTECT );
+REG64_FLD( EQ_QPPM_DPLL_CTRL_FF_BYPASS                             , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FF_BYPASS  );
+REG64_FLD( EQ_QPPM_DPLL_CTRL_DCO_OVERRIDE                          , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_DCO_OVERRIDE );
+REG64_FLD( EQ_QPPM_DPLL_CTRL_DCO_INCR                              , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_DCO_INCR   );
+REG64_FLD( EQ_QPPM_DPLL_CTRL_DCO_DECR                              , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_DCO_DECR   );
+REG64_FLD( EQ_QPPM_DPLL_CTRL_FF_SLEWRATE                           , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FF_SLEWRATE );
+REG64_FLD( EQ_QPPM_DPLL_CTRL_FF_SLEWRATE_LEN                       , 10  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FF_SLEWRATE_LEN );
+REG64_FLD( EQ_QPPM_DPLL_CTRL_SS_ENABLE                             , 16  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SS_ENABLE  );
+REG64_FLD( EQ_QPPM_DPLL_CTRL_RESERVED_17_19                        , 17  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_17_19 );
+REG64_FLD( EQ_QPPM_DPLL_CTRL_RESERVED_17_19_LEN                    , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_17_19_LEN );
+REG64_FLD( EQ_QPPM_DPLL_CTRL_SLEW_DN_SEL                           , 20  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SLEW_DN_SEL );
+REG64_FLD( EQ_QPPM_DPLL_CTRL_ENABLE_JUMP_TARGET_UPDATE             , 21  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ENABLE_JUMP_TARGET_UPDATE );
+REG64_FLD( EQ_QPPM_DPLL_CTRL_ENABLE_FMIN_TARGET                    , 22  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ENABLE_FMIN_TARGET );
+REG64_FLD( EQ_QPPM_DPLL_CTRL_ENABLE_FMAX_TARGET                    , 23  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ENABLE_FMAX_TARGET );
+
+REG64_FLD( EQ_QPPM_DPLL_FREQ_FMAX                                  , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FMAX       );
+REG64_FLD( EQ_QPPM_DPLL_FREQ_FMAX_LEN                              , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FMAX_LEN   );
+REG64_FLD( EQ_QPPM_DPLL_FREQ_HIRES_FMAX                            , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HIRES_FMAX );
+REG64_FLD( EQ_QPPM_DPLL_FREQ_HIRES_FMAX_LEN                        , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HIRES_FMAX_LEN );
+REG64_FLD( EQ_QPPM_DPLL_FREQ_FMULT                                 , 17  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FMULT      );
+REG64_FLD( EQ_QPPM_DPLL_FREQ_FMULT_LEN                             , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FMULT_LEN  );
+REG64_FLD( EQ_QPPM_DPLL_FREQ_HIRES_FMULT                           , 28  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HIRES_FMULT );
+REG64_FLD( EQ_QPPM_DPLL_FREQ_HIRES_FMULT_LEN                       , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HIRES_FMULT_LEN );
+REG64_FLD( EQ_QPPM_DPLL_FREQ_FMIN                                  , 33  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FMIN       );
+REG64_FLD( EQ_QPPM_DPLL_FREQ_FMIN_LEN                              , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_FMIN_LEN   );
+REG64_FLD( EQ_QPPM_DPLL_FREQ_HIRES_FMIN                            , 44  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HIRES_FMIN );
+REG64_FLD( EQ_QPPM_DPLL_FREQ_HIRES_FMIN_LEN                        , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_HIRES_FMIN_LEN );
+
+REG64_FLD( EQ_QPPM_DPLL_ICHAR_FREQIN_AVG                           , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FREQIN_AVG );
+REG64_FLD( EQ_QPPM_DPLL_ICHAR_FREQIN_AVG_LEN                       , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FREQIN_AVG_LEN );
+REG64_FLD( EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_AVG                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIRES_FREQIN_AVG );
+REG64_FLD( EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_AVG_LEN                 , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIRES_FREQIN_AVG_LEN );
+REG64_FLD( EQ_QPPM_DPLL_ICHAR_FREQIN_MAX                           , 21  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FREQIN_MAX );
+REG64_FLD( EQ_QPPM_DPLL_ICHAR_FREQIN_MAX_LEN                       , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FREQIN_MAX_LEN );
+REG64_FLD( EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_MAX                     , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIRES_FREQIN_MAX );
+REG64_FLD( EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_MAX_LEN                 , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIRES_FREQIN_MAX_LEN );
+REG64_FLD( EQ_QPPM_DPLL_ICHAR_FREQIN_MIN                           , 41  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FREQIN_MIN );
+REG64_FLD( EQ_QPPM_DPLL_ICHAR_FREQIN_MIN_LEN                       , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FREQIN_MIN_LEN );
+REG64_FLD( EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_MIN                     , 52  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIRES_FREQIN_MIN );
+REG64_FLD( EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_MIN_LEN                 , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIRES_FREQIN_MIN_LEN );
+
+REG64_FLD( EQ_QPPM_DPLL_OCHAR_FREQOUT_MAX                          , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FREQOUT_MAX );
+REG64_FLD( EQ_QPPM_DPLL_OCHAR_FREQOUT_MAX_LEN                      , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FREQOUT_MAX_LEN );
+REG64_FLD( EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_MAX                    , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIRES_FREQOUT_MAX );
+REG64_FLD( EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_MAX_LEN                , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIRES_FREQOUT_MAX_LEN );
+REG64_FLD( EQ_QPPM_DPLL_OCHAR_FREQOUT_AVG                          , 21  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FREQOUT_AVG );
+REG64_FLD( EQ_QPPM_DPLL_OCHAR_FREQOUT_AVG_LEN                      , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FREQOUT_AVG_LEN );
+REG64_FLD( EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_AVG                    , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIRES_FREQOUT_AVG );
+REG64_FLD( EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_AVG_LEN                , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIRES_FREQOUT_AVG_LEN );
+REG64_FLD( EQ_QPPM_DPLL_OCHAR_FREQOUT_MIN                          , 41  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FREQOUT_MIN );
+REG64_FLD( EQ_QPPM_DPLL_OCHAR_FREQOUT_MIN_LEN                      , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FREQOUT_MIN_LEN );
+REG64_FLD( EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_MIN                    , 52  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIRES_FREQOUT_MIN );
+REG64_FLD( EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_MIN_LEN                , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIRES_FREQOUT_MIN_LEN );
+
+REG64_FLD( EQ_QPPM_DPLL_STAT_FREQOUT                               , 1   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FREQOUT    );
+REG64_FLD( EQ_QPPM_DPLL_STAT_FREQOUT_LEN                           , 11  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FREQOUT_LEN );
+REG64_FLD( EQ_QPPM_DPLL_STAT_HIRES_FREQOUT                         , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIRES_FREQOUT );
+REG64_FLD( EQ_QPPM_DPLL_STAT_HIRES_FREQOUT_LEN                     , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HIRES_FREQOUT_LEN );
+REG64_FLD( EQ_QPPM_DPLL_STAT_RESERVED_57_59                        , 57  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_57_59 );
+REG64_FLD( EQ_QPPM_DPLL_STAT_RESERVED_57_59_LEN                    , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RESERVED_57_59_LEN );
+REG64_FLD( EQ_QPPM_DPLL_STAT_FSAFE_ACTIVE                          , 59  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FSAFE_ACTIVE );
+REG64_FLD( EQ_QPPM_DPLL_STAT_UPDATE_COMPLETE                       , 60  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_UPDATE_COMPLETE );
+REG64_FLD( EQ_QPPM_DPLL_STAT_FREQ_CHANGE                           , 61  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_FREQ_CHANGE );
+REG64_FLD( EQ_QPPM_DPLL_STAT_BLOCK_ACTIVE                          , 62  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_BLOCK_ACTIVE );
+REG64_FLD( EQ_QPPM_DPLL_STAT_LOCK                                  , 63  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LOCK       );
+
+REG64_FLD( EQ_QPPM_ERR_PCB_INTERRUPT_PROTOCOL                      , 0   , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_PCB_INTERRUPT_PROTOCOL );
+REG64_FLD( EQ_QPPM_ERR_SPECIAL_WKUP_PROTOCOL                       , 1   , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_SPECIAL_WKUP_PROTOCOL );
+REG64_FLD( EQ_QPPM_ERR_PFET_SEQ_PROGRAM                            , 2   , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_PFET_SEQ_PROGRAM );
+REG64_FLD( EQ_QPPM_ERR_OCC_HEARTBEAT_LOSS                          , 3   , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_OCC_HEARTBEAT_LOSS );
+REG64_FLD( EQ_QPPM_ERR_L2_EX0_CLK_SYNC                             , 4   , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_L2_EX0_CLK_SYNC );
+REG64_FLD( EQ_QPPM_ERR_L2_EX1_CLK_SYNC                             , 5   , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_L2_EX1_CLK_SYNC );
+REG64_FLD( EQ_QPPM_ERR_EDRAM_SEQUENCE                              , 6   , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_EDRAM_SEQUENCE );
+REG64_FLD( EQ_QPPM_ERR_EDRAM_PGATE                                 , 7   , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_EDRAM_PGATE );
+REG64_FLD( EQ_QPPM_ERR_DPLL_INT                                    , 8   , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_DPLL_INT   );
+REG64_FLD( EQ_QPPM_ERR_DPLL_DYN_FMIN                               , 9   , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_DPLL_DYN_FMIN );
+REG64_FLD( EQ_QPPM_ERR_DPLL_DCO_FULL                               , 10  , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_DPLL_DCO_FULL );
+REG64_FLD( EQ_QPPM_ERR_DPLL_DCO_EMPTY                              , 11  , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_DPLL_DCO_EMPTY );
+REG64_FLD( EQ_QPPM_ERR_INVERTED_VDM_DATA                           , 12  , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_INVERTED_VDM_DATA );
+REG64_FLD( EQ_QPPM_ERR_INVERTED_VDM_DATA_LEN                       , 4   , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_INVERTED_VDM_DATA_LEN );
+REG64_FLD( EQ_QPPM_ERR_CME0_IVRM_DROPOUT                           , 16  , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_CME0_IVRM_DROPOUT );
+REG64_FLD( EQ_QPPM_ERR_CME1_IVRM_DROPOUT                           , 17  , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_CME1_IVRM_DROPOUT );
+REG64_FLD( EQ_QPPM_ERR_SPARE_18_19                                 , 18  , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_SPARE_18_19 );
+REG64_FLD( EQ_QPPM_ERR_SPARE_18_19_LEN                             , 2   , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_SPARE_18_19_LEN );
+
+REG64_FLD( EQ_QPPM_ERRMSK_RESERVED_0_19                            , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_19 );
+REG64_FLD( EQ_QPPM_ERRMSK_RESERVED_0_19_LEN                        , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESERVED_0_19_LEN );
+
+REG64_FLD( EQ_QPPM_ERRSUM_PM_ERROR                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM_WCLEAR,
+           SH_FLD_PM_ERROR   );
+
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_STRENGTH                   , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX0_CLK_SB_STRENGTH );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_STRENGTH_LEN               , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX0_CLK_SB_STRENGTH_LEN );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_SPARE0                     , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX0_CLK_SB_SPARE0 );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_PULSE_MODE_EN              , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_EN );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_PULSE_MODE                 , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX0_CLK_SB_PULSE_MODE );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_PULSE_MODE_LEN             , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_LEN );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SW_RESCLK                     , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX0_CLK_SW_RESCLK );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SW_RESCLK_LEN                 , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX0_CLK_SW_RESCLK_LEN );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SW_SPARE1                     , 12  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX0_CLK_SW_SPARE1 );
+REG64_FLD( EQ_QPPM_EXCGCR_RESERVED_13_15                           , 13  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_13_15 );
+REG64_FLD( EQ_QPPM_EXCGCR_RESERVED_13_15_LEN                       , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_13_15_LEN );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_STRENGTH                   , 16  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX1_CLK_SB_STRENGTH );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_STRENGTH_LEN               , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX1_CLK_SB_STRENGTH_LEN );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_SPARE0                     , 20  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX1_CLK_SB_SPARE0 );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_PULSE_MODE_EN              , 21  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_EN );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_PULSE_MODE                 , 22  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX1_CLK_SB_PULSE_MODE );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_PULSE_MODE_LEN             , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_LEN );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SW_RESCLK                     , 24  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX1_CLK_SW_RESCLK );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SW_RESCLK_LEN                 , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX1_CLK_SW_RESCLK_LEN );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SW_SPARE1                     , 28  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX1_CLK_SW_SPARE1 );
+REG64_FLD( EQ_QPPM_EXCGCR_RESERVED_29_31                           , 29  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_29_31 );
+REG64_FLD( EQ_QPPM_EXCGCR_RESERVED_29_31_LEN                       , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_29_31_LEN );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLKGLM_ASYNC_RESET                , 32  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX0_CLKGLM_ASYNC_RESET );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLKGLM_ASYNC_RESET                , 33  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX1_CLKGLM_ASYNC_RESET );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLKGLM_SEL                        , 34  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX0_CLKGLM_SEL );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLKGLM_SEL                        , 35  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX1_CLKGLM_SEL );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SYNC_ENABLE                   , 36  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX0_CLK_SYNC_ENABLE );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SYNC_ENABLE                   , 37  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX1_CLK_SYNC_ENABLE );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_OVERRIDE                   , 38  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX0_CLK_SB_OVERRIDE );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_OVERRIDE                   , 39  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX1_CLK_SB_OVERRIDE );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SW_OVERRIDE                   , 40  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX0_CLK_SW_OVERRIDE );
+REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SW_OVERRIDE                   , 41  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L2_EX1_CLK_SW_OVERRIDE );
+
+REG64_FLD( EQ_QPPM_OCCHB_OCC_HEARTBEAT_COUNT                       , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_HEARTBEAT_COUNT );
+REG64_FLD( EQ_QPPM_OCCHB_OCC_HEARTBEAT_COUNT_LEN                   , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_HEARTBEAT_COUNT_LEN );
+REG64_FLD( EQ_QPPM_OCCHB_OCC_HEARTBEAT_ENABLE                      , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_OCC_HEARTBEAT_ENABLE );
+
+REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SB_STRENGTH                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMMON_CLK_SB_STRENGTH );
+REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SB_STRENGTH_LEN                , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMMON_CLK_SB_STRENGTH_LEN );
+REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SB_SPARE                       , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMMON_CLK_SB_SPARE );
+REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SB_PULSE_MODE_EN               , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMMON_CLK_SB_PULSE_MODE_EN );
+REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SB_PULSE_MODE                  , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMMON_CLK_SB_PULSE_MODE );
+REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SB_PULSE_MODE_LEN              , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMMON_CLK_SB_PULSE_MODE_LEN );
+REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SW_RESCLK                      , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMMON_CLK_SW_RESCLK );
+REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SW_RESCLK_LEN                  , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMMON_CLK_SW_RESCLK_LEN );
+REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SW_SPARE                       , 12  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_COMMON_CLK_SW_SPARE );
+REG64_FLD( EQ_QPPM_QACCR_RESERVED_13_15                            , 13  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_13_15 );
+REG64_FLD( EQ_QPPM_QACCR_RESERVED_13_15_LEN                        , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED_13_15_LEN );
+REG64_FLD( EQ_QPPM_QACCR_L3_CLK_SB_STRENGTH                        , 16  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_CLK_SB_STRENGTH );
+REG64_FLD( EQ_QPPM_QACCR_L3_CLK_SB_STRENGTH_LEN                    , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_CLK_SB_STRENGTH_LEN );
+REG64_FLD( EQ_QPPM_QACCR_L3_CLK_SB_SPARE0                          , 20  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_CLK_SB_SPARE0 );
+REG64_FLD( EQ_QPPM_QACCR_L3_CLK_SB_PULSE_MODE_EN                   , 21  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_CLK_SB_PULSE_MODE_EN );
+REG64_FLD( EQ_QPPM_QACCR_L3_CLK_SB_PULSE_MODE                      , 22  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_CLK_SB_PULSE_MODE );
+REG64_FLD( EQ_QPPM_QACCR_L3_CLK_SB_PULSE_MODE_LEN                  , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_L3_CLK_SB_PULSE_MODE_LEN );
+
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_STRENGTH             , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX0_CLK_SB_STRENGTH );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_STRENGTH_LEN         , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX0_CLK_SB_STRENGTH_LEN );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_SPARE0               , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX0_CLK_SB_SPARE0 );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_EN        , 5   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_EN );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE           , 6   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_LEN );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SW_RESCLK               , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX0_CLK_SW_RESCLK );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SW_RESCLK_LEN           , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX0_CLK_SW_RESCLK_LEN );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SW_SPARE1               , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX0_CLK_SW_SPARE1 );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_STRENGTH             , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX1_CLK_SB_STRENGTH );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_STRENGTH_LEN         , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX1_CLK_SB_STRENGTH_LEN );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_SPARE0               , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX1_CLK_SB_SPARE0 );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_EN        , 21  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_EN );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE           , 22  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_LEN       , 2   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_LEN );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SW_RESCLK               , 24  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX1_CLK_SW_RESCLK );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SW_RESCLK_LEN           , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX1_CLK_SW_RESCLK_LEN );
+REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SW_SPARE1               , 28  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ACTUAL_L2_EX1_CLK_SW_SPARE1 );
+REG64_FLD( EQ_QPPM_QACSR_L2_EX0_CLK_SYNC_DONE                      , 36  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_L2_EX0_CLK_SYNC_DONE );
+REG64_FLD( EQ_QPPM_QACSR_L2_EX1_CLK_SYNC_DONE                      , 37  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_L2_EX1_CLK_SYNC_DONE );
+
+REG64_FLD( EQ_QPPM_QCCR_L3_EX0_EDRAM_ENABLE_ENCODE                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L3_EX0_EDRAM_ENABLE_ENCODE );
+REG64_FLD( EQ_QPPM_QCCR_L3_EX0_EDRAM_ENABLE_ENCODE_LEN             , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L3_EX0_EDRAM_ENABLE_ENCODE_LEN );
+REG64_FLD( EQ_QPPM_QCCR_L3_EX1_EDRAM_ENABLE_ENCODE                 , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L3_EX1_EDRAM_ENABLE_ENCODE );
+REG64_FLD( EQ_QPPM_QCCR_L3_EX1_EDRAM_ENABLE_ENCODE_LEN             , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L3_EX1_EDRAM_ENABLE_ENCODE_LEN );
+REG64_FLD( EQ_QPPM_QCCR_SPARE_8_11                                 , 8   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_SPARE_8_11 );
+REG64_FLD( EQ_QPPM_QCCR_SPARE_8_11_LEN                             , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_SPARE_8_11_LEN );
+REG64_FLD( EQ_QPPM_QCCR_DROOP_PROTECT_DATA                         , 12  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_DROOP_PROTECT_DATA );
+REG64_FLD( EQ_QPPM_QCCR_DROOP_PROTECT_DATA_LEN                     , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_DROOP_PROTECT_DATA_LEN );
+REG64_FLD( EQ_QPPM_QCCR_FORCE_DROOP_DATA                           , 16  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_FORCE_DROOP_DATA );
+REG64_FLD( EQ_QPPM_QCCR_FORCE_DROOP_DATA_LEN                       , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_FORCE_DROOP_DATA_LEN );
+REG64_FLD( EQ_QPPM_QCCR_PULSE_DROOP_DATA                           , 20  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PULSE_DROOP_DATA );
+REG64_FLD( EQ_QPPM_QCCR_PULSE_DROOP_DATA_LEN                       , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PULSE_DROOP_DATA_LEN );
+REG64_FLD( EQ_QPPM_QCCR_PULSE_DROOP_ENABLE                         , 24  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PULSE_DROOP_ENABLE );
+REG64_FLD( EQ_QPPM_QCCR_PB_PURGE_PLS                               , 30  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PB_PURGE_PLS );
+REG64_FLD( EQ_QPPM_QCCR_PB_PURGE_DONE_LVL                          , 31  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_PB_PURGE_DONE_LVL );
+REG64_FLD( EQ_QPPM_QCCR_L3_EX0_EDRAM_ENABLE_ACTUAL                 , 32  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L3_EX0_EDRAM_ENABLE_ACTUAL );
+REG64_FLD( EQ_QPPM_QCCR_L3_EX0_EDRAM_ENABLE_ACTUAL_LEN             , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L3_EX0_EDRAM_ENABLE_ACTUAL_LEN );
+REG64_FLD( EQ_QPPM_QCCR_L3_EX1_EDRAM_ENABLE_ACTUAL                 , 36  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L3_EX1_EDRAM_ENABLE_ACTUAL );
+REG64_FLD( EQ_QPPM_QCCR_L3_EX1_EDRAM_ENABLE_ACTUAL_LEN             , 4   , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L3_EX1_EDRAM_ENABLE_ACTUAL_LEN );
+REG64_FLD( EQ_QPPM_QCCR_L3_EDRAM_SEQ_ERR                           , 40  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L3_EDRAM_SEQ_ERR );
+REG64_FLD( EQ_QPPM_QCCR_L3_EDRAM_PGATE_ERR                         , 41  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L3_EDRAM_PGATE_ERR );
+REG64_FLD( EQ_QPPM_QCCR_L3_EX0_EDRAM_UNLOCKED                      , 42  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L3_EX0_EDRAM_UNLOCKED );
+REG64_FLD( EQ_QPPM_QCCR_L3_EX1_EDRAM_UNLOCKED                      , 43  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L3_EX1_EDRAM_UNLOCKED );
+
+REG64_FLD( EQ_QPPM_QPMMR_FORCE_FSAFE                               , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FORCE_FSAFE );
+REG64_FLD( EQ_QPPM_QPMMR_FSAFE                                     , 1   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FSAFE      );
+REG64_FLD( EQ_QPPM_QPMMR_FSAFE_LEN                                 , 11  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_FSAFE_LEN  );
+REG64_FLD( EQ_QPPM_QPMMR_ENABLE_FSAFE_UPON_HEARTBEAT_LOSS          , 12  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ENABLE_FSAFE_UPON_HEARTBEAT_LOSS );
+REG64_FLD( EQ_QPPM_QPMMR_ENABLE_DROOP_PROTECT_UPON_HEARTBEAT_LOSS  , 13  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ENABLE_DROOP_PROTECT_UPON_HEARTBEAT_LOSS );
+REG64_FLD( EQ_QPPM_QPMMR_ENABLE_PFETS_UPON_IVRM_DROPOUT            , 14  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ENABLE_PFETS_UPON_IVRM_DROPOUT );
+REG64_FLD( EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_HEARTBEAT_LOSS       , 16  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ENABLE_PCB_INTR_UPON_HEARTBEAT_LOSS );
+REG64_FLD( EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_IVRM_DROPOUT         , 17  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ENABLE_PCB_INTR_UPON_IVRM_DROPOUT );
+REG64_FLD( EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_LARGE_DROOP          , 18  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ENABLE_PCB_INTR_UPON_LARGE_DROOP );
+REG64_FLD( EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_EXTREME_DROOP        , 19  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_ENABLE_PCB_INTR_UPON_EXTREME_DROOP );
+REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_IVRM_ENABLE                  , 20  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_INTERPPM_IVRM_ENABLE );
+REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_IVRM_SEL                     , 21  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_INTERPPM_IVRM_SEL );
+REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_ACLK_ENABLE                  , 22  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_INTERPPM_ACLK_ENABLE );
+REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_ACLK_SEL                     , 23  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_INTERPPM_ACLK_SEL );
+REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_VDATA_ENABLE                 , 24  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_INTERPPM_VDATA_ENABLE );
+REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_VDATA_SEL                    , 25  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_INTERPPM_VDATA_SEL );
+REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_DPLL_ENABLE                  , 26  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_INTERPPM_DPLL_ENABLE );
+REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_DPLL_SEL                     , 27  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_INTERPPM_DPLL_SEL );
+REG64_FLD( EQ_QPPM_QPMMR_RESERVED28_31                             , 28  , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED28_31 );
+REG64_FLD( EQ_QPPM_QPMMR_RESERVED28_31_LEN                         , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_OR ,
+           SH_FLD_RESERVED28_31_LEN );
+
+REG64_FLD( EQ_QPPM_VDMCFGR_VDM_VID_COMPARE                         , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_VID_COMPARE );
+REG64_FLD( EQ_QPPM_VDMCFGR_VDM_VID_COMPARE_LEN                     , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_VID_COMPARE_LEN );
+REG64_FLD( EQ_QPPM_VDMCFGR_VDM_OVERVOLT                            , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_OVERVOLT );
+REG64_FLD( EQ_QPPM_VDMCFGR_VDM_OVERVOLT_LEN                        , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_OVERVOLT_LEN );
+REG64_FLD( EQ_QPPM_VDMCFGR_VDM_DROOP_SMALL                         , 12  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_DROOP_SMALL );
+REG64_FLD( EQ_QPPM_VDMCFGR_VDM_DROOP_SMALL_LEN                     , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_DROOP_SMALL_LEN );
+REG64_FLD( EQ_QPPM_VDMCFGR_VDM_DROOP_LARGE                         , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_DROOP_LARGE );
+REG64_FLD( EQ_QPPM_VDMCFGR_VDM_DROOP_LARGE_LEN                     , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_DROOP_LARGE_LEN );
+REG64_FLD( EQ_QPPM_VDMCFGR_VDM_DROOP_XTREME                        , 20  , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_DROOP_XTREME );
+REG64_FLD( EQ_QPPM_VDMCFGR_VDM_DROOP_XTREME_LEN                    , 4   , SH_UNT_EQ       , SH_ACS_SCOM_RW  ,
+           SH_FLD_VDM_DROOP_XTREME_LEN );
+
+REG64_FLD( EQ_QPPM_VOLT_CHAR_VID_COMPARE_MAX                       , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VID_COMPARE_MAX );
+REG64_FLD( EQ_QPPM_VOLT_CHAR_VID_COMPARE_MAX_LEN                   , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VID_COMPARE_MAX_LEN );
+REG64_FLD( EQ_QPPM_VOLT_CHAR_VID_COMPARE_MIN                       , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VID_COMPARE_MIN );
+REG64_FLD( EQ_QPPM_VOLT_CHAR_VID_COMPARE_MIN_LEN                   , 8   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VID_COMPARE_MIN_LEN );
+REG64_FLD( EQ_QPPM_VOLT_CHAR_IVRM_ENABLED_HISTORY                  , 16  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_IVRM_ENABLED_HISTORY );
+
+REG64_FLD( EQ_RD_EPS_REG_TIER0_VALUE                               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TIER0_VALUE );
+REG64_FLD( EQ_RD_EPS_REG_TIER0_VALUE_LEN                           , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TIER0_VALUE_LEN );
+REG64_FLD( EQ_RD_EPS_REG_TIER1_VALUE                               , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TIER1_VALUE );
+REG64_FLD( EQ_RD_EPS_REG_TIER1_VALUE_LEN                           , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TIER1_VALUE_LEN );
+REG64_FLD( EQ_RD_EPS_REG_TIER2_VALUE                               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TIER2_VALUE );
+REG64_FLD( EQ_RD_EPS_REG_TIER2_VALUE_LEN                           , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TIER2_VALUE_LEN );
+
+REG64_FLD( EX_L2_RD_EPS_REG_TIER0_VALUE                            , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_TIER0_VALUE );
+REG64_FLD( EX_L2_RD_EPS_REG_TIER0_VALUE_LEN                        , 12  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_TIER0_VALUE_LEN );
+REG64_FLD( EX_L2_RD_EPS_REG_TIER1_VALUE                            , 12  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_TIER1_VALUE );
+REG64_FLD( EX_L2_RD_EPS_REG_TIER1_VALUE_LEN                        , 12  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_TIER1_VALUE_LEN );
+REG64_FLD( EX_L2_RD_EPS_REG_TIER2_VALUE                            , 24  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_TIER2_VALUE );
+REG64_FLD( EX_L2_RD_EPS_REG_TIER2_VALUE_LEN                        , 12  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_TIER2_VALUE_LEN );
+
+REG64_FLD( EQ_RFIR_IN0                                             , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( EQ_RFIR_LFIR_RECOV_ERR                                  , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_LFIR_RECOV_ERR );
+REG64_FLD( EQ_RFIR_IN4                                             , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( EQ_RFIR_IN5                                             , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( EQ_RFIR_IN6                                             , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN6        );
+REG64_FLD( EQ_RFIR_IN7                                             , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN7        );
+REG64_FLD( EQ_RFIR_IN8                                             , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN8        );
+REG64_FLD( EQ_RFIR_IN9                                             , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN9        );
+REG64_FLD( EQ_RFIR_IN10                                            , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN10       );
+REG64_FLD( EQ_RFIR_IN11                                            , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN11       );
+REG64_FLD( EQ_RFIR_IN12                                            , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN12       );
+REG64_FLD( EQ_RFIR_IN13                                            , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN13       );
+REG64_FLD( EQ_RFIR_IN13_LEN                                        , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN13_LEN   );
+
+REG64_FLD( EX_RFIR_IN0                                             , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( EX_RFIR_LFIR_RECOV_ERR                                  , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_LFIR_RECOV_ERR );
+REG64_FLD( EX_RFIR_IN4                                             , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( EX_RFIR_IN5                                             , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( EX_RFIR_IN5_LEN                                         , 21  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN5_LEN    );
+
+REG64_FLD( C_RFIR_IN0                                              , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( C_RFIR_LFIR_RECOV_ERR                                   , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_LFIR_RECOV_ERR );
+REG64_FLD( C_RFIR_IN4                                              , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( C_RFIR_IN5                                              , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( C_RFIR_IN5_LEN                                          , 21  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN5_LEN    );
+
+REG64_FLD( EQ_RING_FENCE_MASK_LATCH_REG_DISABLED                   , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED   );
+REG64_FLD( EQ_RING_FENCE_MASK_LATCH_REG_ENABLE                     , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( EQ_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN                 , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( EX_RING_FENCE_MASK_LATCH_REG_DISABLED                   , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED   );
+REG64_FLD( EX_RING_FENCE_MASK_LATCH_REG_ENABLE                     , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( EX_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN                 , 15  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( C_RING_FENCE_MASK_LATCH_REG_DISABLED                    , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DISABLED   );
+REG64_FLD( C_RING_FENCE_MASK_LATCH_REG_ENABLE                      , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE     );
+REG64_FLD( C_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN                  , 15  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_LEN );
+
+REG64_FLD( EQ_SCAN_REGION_TYPE_SYSTEM_FAST_INIT                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SYSTEM_FAST_INIT );
+REG64_FLD( EQ_SCAN_REGION_TYPE_VITL                                , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_VITL       );
+REG64_FLD( EQ_SCAN_REGION_TYPE_PERV                                , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT1                               , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT2                               , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT3                               , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT4                               , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT5                               , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT6                               , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT7                               , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT8                               , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT9                               , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT10                              , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( EQ_SCAN_REGION_TYPE_FUNC                                , 48  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FUNC       );
+REG64_FLD( EQ_SCAN_REGION_TYPE_CFG                                 , 49  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CFG        );
+REG64_FLD( EQ_SCAN_REGION_TYPE_CCFG_GPTR                           , 50  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CCFG_GPTR  );
+REG64_FLD( EQ_SCAN_REGION_TYPE_REGF                                , 51  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_REGF       );
+REG64_FLD( EQ_SCAN_REGION_TYPE_LBIST                               , 52  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_LBIST      );
+REG64_FLD( EQ_SCAN_REGION_TYPE_ABIST                               , 53  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ABIST      );
+REG64_FLD( EQ_SCAN_REGION_TYPE_REPR                                , 54  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_REPR       );
+REG64_FLD( EQ_SCAN_REGION_TYPE_TIME                                , 55  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TIME       );
+REG64_FLD( EQ_SCAN_REGION_TYPE_BNDY                                , 56  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_BNDY       );
+REG64_FLD( EQ_SCAN_REGION_TYPE_FARR                                , 57  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FARR       );
+REG64_FLD( EQ_SCAN_REGION_TYPE_CMSK                                , 58  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMSK       );
+REG64_FLD( EQ_SCAN_REGION_TYPE_INEX                                , 59  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_INEX       );
+
+REG64_FLD( EX_SCAN_REGION_TYPE_SYSTEM_FAST_INIT                    , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SYSTEM_FAST_INIT );
+REG64_FLD( EX_SCAN_REGION_TYPE_VITL                                , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_VITL       );
+REG64_FLD( EX_SCAN_REGION_TYPE_PERV                                , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( EX_SCAN_REGION_TYPE_UNIT1                               , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( EX_SCAN_REGION_TYPE_UNIT2                               , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( EX_SCAN_REGION_TYPE_UNIT3                               , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( EX_SCAN_REGION_TYPE_UNIT4                               , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( EX_SCAN_REGION_TYPE_UNIT5                               , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( EX_SCAN_REGION_TYPE_UNIT6                               , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( EX_SCAN_REGION_TYPE_UNIT7                               , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( EX_SCAN_REGION_TYPE_UNIT8                               , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( EX_SCAN_REGION_TYPE_UNIT9                               , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( EX_SCAN_REGION_TYPE_UNIT10                              , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( EX_SCAN_REGION_TYPE_FUNC                                , 48  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FUNC       );
+REG64_FLD( EX_SCAN_REGION_TYPE_CFG                                 , 49  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CFG        );
+REG64_FLD( EX_SCAN_REGION_TYPE_CCFG_GPTR                           , 50  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CCFG_GPTR  );
+REG64_FLD( EX_SCAN_REGION_TYPE_REGF                                , 51  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_REGF       );
+REG64_FLD( EX_SCAN_REGION_TYPE_LBIST                               , 52  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_LBIST      );
+REG64_FLD( EX_SCAN_REGION_TYPE_ABIST                               , 53  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ABIST      );
+REG64_FLD( EX_SCAN_REGION_TYPE_REPR                                , 54  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_REPR       );
+REG64_FLD( EX_SCAN_REGION_TYPE_TIME                                , 55  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TIME       );
+REG64_FLD( EX_SCAN_REGION_TYPE_BNDY                                , 56  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_BNDY       );
+REG64_FLD( EX_SCAN_REGION_TYPE_FARR                                , 57  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FARR       );
+REG64_FLD( EX_SCAN_REGION_TYPE_CMSK                                , 58  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CMSK       );
+REG64_FLD( EX_SCAN_REGION_TYPE_INEX                                , 59  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_INEX       );
+
+REG64_FLD( C_SCAN_REGION_TYPE_SYSTEM_FAST_INIT                     , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SYSTEM_FAST_INIT );
+REG64_FLD( C_SCAN_REGION_TYPE_VITL                                 , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_VITL       );
+REG64_FLD( C_SCAN_REGION_TYPE_PERV                                 , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( C_SCAN_REGION_TYPE_UNIT1                                , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( C_SCAN_REGION_TYPE_UNIT2                                , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( C_SCAN_REGION_TYPE_UNIT3                                , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( C_SCAN_REGION_TYPE_UNIT4                                , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( C_SCAN_REGION_TYPE_UNIT5                                , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( C_SCAN_REGION_TYPE_UNIT6                                , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( C_SCAN_REGION_TYPE_UNIT7                                , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( C_SCAN_REGION_TYPE_UNIT8                                , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( C_SCAN_REGION_TYPE_UNIT9                                , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( C_SCAN_REGION_TYPE_UNIT10                               , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( C_SCAN_REGION_TYPE_FUNC                                 , 48  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FUNC       );
+REG64_FLD( C_SCAN_REGION_TYPE_CFG                                  , 49  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CFG        );
+REG64_FLD( C_SCAN_REGION_TYPE_CCFG_GPTR                            , 50  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CCFG_GPTR  );
+REG64_FLD( C_SCAN_REGION_TYPE_REGF                                 , 51  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_REGF       );
+REG64_FLD( C_SCAN_REGION_TYPE_LBIST                                , 52  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_LBIST      );
+REG64_FLD( C_SCAN_REGION_TYPE_ABIST                                , 53  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ABIST      );
+REG64_FLD( C_SCAN_REGION_TYPE_REPR                                 , 54  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_REPR       );
+REG64_FLD( C_SCAN_REGION_TYPE_TIME                                 , 55  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TIME       );
+REG64_FLD( C_SCAN_REGION_TYPE_BNDY                                 , 56  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_BNDY       );
+REG64_FLD( C_SCAN_REGION_TYPE_FARR                                 , 57  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FARR       );
+REG64_FLD( C_SCAN_REGION_TYPE_CMSK                                 , 58  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CMSK       );
+REG64_FLD( C_SCAN_REGION_TYPE_INEX                                 , 59  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_INEX       );
+
+REG64_FLD( EX_L2_SCOMC_MODE                                        , 54  , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE       );
+REG64_FLD( EX_L2_SCOMC_MODE_LEN                                    , 7   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_LEN   );
+
+REG64_FLD( C_SCOMC_MODE                                            , 54  , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE       );
+REG64_FLD( C_SCOMC_MODE_LEN                                        , 7   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_MODE_LEN   );
+
+REG64_FLD( EQ_SKITTER_CLKSRC_REG_SKITTER0                          , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0   );
+REG64_FLD( EQ_SKITTER_CLKSRC_REG_SKITTER0_LEN                      , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0_LEN );
+REG64_FLD( EQ_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT             , 36  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0_DELAY_SELECT );
+REG64_FLD( EQ_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN         , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0_DELAY_SELECT_LEN );
+
+REG64_FLD( EX_SKITTER_CLKSRC_REG_SKITTER0                          , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0   );
+REG64_FLD( EX_SKITTER_CLKSRC_REG_SKITTER0_LEN                      , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0_LEN );
+REG64_FLD( EX_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT             , 36  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0_DELAY_SELECT );
+REG64_FLD( EX_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN         , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0_DELAY_SELECT_LEN );
+
+REG64_FLD( C_SKITTER_CLKSRC_REG_SKITTER0                           , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0   );
+REG64_FLD( C_SKITTER_CLKSRC_REG_SKITTER0_LEN                       , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0_LEN );
+REG64_FLD( C_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT              , 36  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0_DELAY_SELECT );
+REG64_FLD( C_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN          , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SKITTER0_DELAY_SELECT_LEN );
+
+REG64_FLD( EQ_SKITTER_FORCE_REG_F_READ                             , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_F_READ     );
+
+REG64_FLD( EX_SKITTER_FORCE_REG_F_READ                             , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_F_READ     );
+
+REG64_FLD( C_SKITTER_FORCE_REG_F_READ                              , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_F_READ     );
+
+REG64_FLD( EQ_SKITTER_MODE_REG_HOLD_SAMPLE                         , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_SAMPLE );
+REG64_FLD( EQ_SKITTER_MODE_REG_DISABLE_STICKINESS                  , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_STICKINESS );
+REG64_FLD( EQ_SKITTER_MODE_REG_UNUSED1                             , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1    );
+REG64_FLD( EQ_SKITTER_MODE_REG_UNUSED1_LEN                         , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1_LEN );
+REG64_FLD( EQ_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL                    , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_DBGTRIG_SEL );
+REG64_FLD( EQ_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN                , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_DBGTRIG_SEL_LEN );
+REG64_FLD( EQ_SKITTER_MODE_REG_RESET_TRIG_SEL                      , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_TRIG_SEL );
+REG64_FLD( EQ_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN                  , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_TRIG_SEL_LEN );
+REG64_FLD( EQ_SKITTER_MODE_REG_SAMPLE_GUTS                         , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_GUTS );
+REG64_FLD( EQ_SKITTER_MODE_REG_SAMPLE_GUTS_LEN                     , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_GUTS_LEN );
+REG64_FLD( EQ_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER            , 44  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_SAMPLE_WITH_TRIGGER );
+REG64_FLD( EQ_SKITTER_MODE_REG_DATA_V_LT                           , 45  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DATA_V_LT  );
+
+REG64_FLD( EX_SKITTER_MODE_REG_HOLD_SAMPLE                         , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_SAMPLE );
+REG64_FLD( EX_SKITTER_MODE_REG_DISABLE_STICKINESS                  , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_STICKINESS );
+REG64_FLD( EX_SKITTER_MODE_REG_UNUSED1                             , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1    );
+REG64_FLD( EX_SKITTER_MODE_REG_UNUSED1_LEN                         , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1_LEN );
+REG64_FLD( EX_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL                    , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_DBGTRIG_SEL );
+REG64_FLD( EX_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN                , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_DBGTRIG_SEL_LEN );
+REG64_FLD( EX_SKITTER_MODE_REG_RESET_TRIG_SEL                      , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_TRIG_SEL );
+REG64_FLD( EX_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN                  , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESET_TRIG_SEL_LEN );
+REG64_FLD( EX_SKITTER_MODE_REG_SAMPLE_GUTS                         , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_GUTS );
+REG64_FLD( EX_SKITTER_MODE_REG_SAMPLE_GUTS_LEN                     , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_GUTS_LEN );
+REG64_FLD( EX_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER            , 44  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_SAMPLE_WITH_TRIGGER );
+REG64_FLD( EX_SKITTER_MODE_REG_DATA_V_LT                           , 45  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DATA_V_LT  );
+
+REG64_FLD( C_SKITTER_MODE_REG_HOLD_SAMPLE                          , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_SAMPLE );
+REG64_FLD( C_SKITTER_MODE_REG_DISABLE_STICKINESS                   , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_STICKINESS );
+REG64_FLD( C_SKITTER_MODE_REG_UNUSED1                              , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1    );
+REG64_FLD( C_SKITTER_MODE_REG_UNUSED1_LEN                          , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1_LEN );
+REG64_FLD( C_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL                     , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_DBGTRIG_SEL );
+REG64_FLD( C_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN                 , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_DBGTRIG_SEL_LEN );
+REG64_FLD( C_SKITTER_MODE_REG_RESET_TRIG_SEL                       , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESET_TRIG_SEL );
+REG64_FLD( C_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN                   , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESET_TRIG_SEL_LEN );
+REG64_FLD( C_SKITTER_MODE_REG_SAMPLE_GUTS                          , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_GUTS );
+REG64_FLD( C_SKITTER_MODE_REG_SAMPLE_GUTS_LEN                      , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_GUTS_LEN );
+REG64_FLD( C_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER             , 44  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_HOLD_SAMPLE_WITH_TRIGGER );
+REG64_FLD( C_SKITTER_MODE_REG_DATA_V_LT                            , 45  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DATA_V_LT  );
+
+REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK        , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK );
+REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN          , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_MALF_PULSE_GEN );
+REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP          , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP );
+REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK          , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK );
+REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT               , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_HEARTBEAT );
+REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO           , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_FORCE_TO_ZERO );
+REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_PM_DISABLE                      , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PM_DISABLE );
+REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE                  , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PM_MUX_DISABLE );
+REG64_FLD( EQ_SLAVE_CONFIG_REG_ERROR_MASK                          , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_MASK );
+REG64_FLD( EQ_SLAVE_CONFIG_REG_ERROR_MASK_LEN                      , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_MASK_LEN );
+
+REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK        , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK );
+REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN          , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_MALF_PULSE_GEN );
+REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP          , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP );
+REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK          , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK );
+REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT               , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_HEARTBEAT );
+REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO           , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_FORCE_TO_ZERO );
+REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_PM_DISABLE                      , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PM_DISABLE );
+REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE                  , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PM_MUX_DISABLE );
+REG64_FLD( EX_SLAVE_CONFIG_REG_ERROR_MASK                          , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_MASK );
+REG64_FLD( EX_SLAVE_CONFIG_REG_ERROR_MASK_LEN                      , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_MASK_LEN );
+
+REG64_FLD( C_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK         , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK );
+REG64_FLD( C_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN           , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_MALF_PULSE_GEN );
+REG64_FLD( C_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP           , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP );
+REG64_FLD( C_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK           , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK );
+REG64_FLD( C_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT                , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_HEARTBEAT );
+REG64_FLD( C_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO            , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CFG_DISABLE_FORCE_TO_ZERO );
+REG64_FLD( C_SLAVE_CONFIG_REG_CFG_PM_DISABLE                       , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PM_DISABLE );
+REG64_FLD( C_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE                   , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CFG_PM_MUX_DISABLE );
+REG64_FLD( C_SLAVE_CONFIG_REG_ERROR_MASK                           , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_MASK );
+REG64_FLD( C_SLAVE_CONFIG_REG_ERROR_MASK_LEN                       , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ERROR_MASK_LEN );
+
+REG64_FLD( EQ_SPATTN_IN0                                           , 0   , SH_UNT_EQ       , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN0        );
+REG64_FLD( EQ_SPATTN_IN1                                           , 1   , SH_UNT_EQ       , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN1        );
+REG64_FLD( EQ_SPATTN_IN2                                           , 2   , SH_UNT_EQ       , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN2        );
+REG64_FLD( EQ_SPATTN_IN3                                           , 3   , SH_UNT_EQ       , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN3        );
+REG64_FLD( EQ_SPATTN_IN4                                           , 4   , SH_UNT_EQ       , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN4        );
+REG64_FLD( EQ_SPATTN_IN5                                           , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN5        );
+REG64_FLD( EQ_SPATTN_IN6                                           , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN6        );
+REG64_FLD( EQ_SPATTN_IN7                                           , 7   , SH_UNT_EQ       , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN7        );
+REG64_FLD( EQ_SPATTN_IN8                                           , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN8        );
+REG64_FLD( EQ_SPATTN_IN9                                           , 9   , SH_UNT_EQ       , SH_ACS_SCOM2_NC ,
+           SH_FLD_IN9        );
+
+REG64_FLD( EQ_SPA_MASK_IN                                          , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( EQ_SPA_MASK_IN_LEN                                      , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( EX_SPA_MASK_IN                                          , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( EX_SPA_MASK_IN_LEN                                      , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( C_SPA_MASK_IN                                           , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN         );
+REG64_FLD( C_SPA_MASK_IN_LEN                                       , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN_LEN     );
+
+REG64_FLD( EX_L2_SPR_MODE_MODEREG_TFAC_ERR_INJ                     , 10  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_TFAC_ERR_INJ );
+REG64_FLD( EX_L2_SPR_MODE_MODEREG_TFAC_ERR_INJ_LEN                 , 6   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_TFAC_ERR_INJ_LEN );
+REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT0_SEL                     , 20  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT0_SEL );
+REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT1_SEL                     , 21  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT1_SEL );
+REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT2_SEL                     , 22  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT2_SEL );
+REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT3_SEL                     , 23  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT3_SEL );
+REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT4_SEL                     , 24  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT4_SEL );
+REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT5_SEL                     , 25  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT5_SEL );
+REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT6_SEL                     , 26  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT6_SEL );
+REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT7_SEL                     , 27  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT7_SEL );
+
+REG64_FLD( C_SPR_MODE_MODEREG_TFAC_ERR_INJ                         , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_TFAC_ERR_INJ );
+REG64_FLD( C_SPR_MODE_MODEREG_TFAC_ERR_INJ_LEN                     , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_TFAC_ERR_INJ_LEN );
+REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT0_SEL                         , 20  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT0_SEL );
+REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT1_SEL                         , 21  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT1_SEL );
+REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT2_SEL                         , 22  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT2_SEL );
+REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT3_SEL                         , 23  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT3_SEL );
+REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT4_SEL                         , 24  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT4_SEL );
+REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT5_SEL                         , 25  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT5_SEL );
+REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT6_SEL                         , 26  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT6_SEL );
+REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT7_SEL                         , 27  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MODEREG_SPRC_LT7_SEL );
+
+REG64_FLD( EX_SPURR_FREQ_DETECT_CYC_CNT_CYCLE_COUNT                , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CYCLE_COUNT );
+REG64_FLD( EX_SPURR_FREQ_DETECT_CYC_CNT_CYCLE_COUNT_LEN            , 8   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_CYCLE_COUNT_LEN );
+
+REG64_FLD( C_SPURR_FREQ_DETECT_CYC_CNT_CYCLE_COUNT                 , 0   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_CYCLE_COUNT );
+REG64_FLD( C_SPURR_FREQ_DETECT_CYC_CNT_CYCLE_COUNT_LEN             , 8   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_CYCLE_COUNT_LEN );
+
+REG64_FLD( EX_L2_SPURR_FREQ_REF_FREQUENCY_REFERENCE                , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_FREQUENCY_REFERENCE );
+REG64_FLD( EX_L2_SPURR_FREQ_REF_FREQUENCY_REFERENCE_LEN            , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_FREQUENCY_REFERENCE_LEN );
+
+REG64_FLD( C_SPURR_FREQ_REF_FREQUENCY_REFERENCE                    , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_FREQUENCY_REFERENCE );
+REG64_FLD( C_SPURR_FREQ_REF_FREQUENCY_REFERENCE_LEN                , 8   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_FREQUENCY_REFERENCE_LEN );
+
+REG64_FLD( EX_L2_SPURR_FREQ_SCALE_OVERRIDE_EN                      , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_OVERRIDE_EN );
+REG64_FLD( EX_L2_SPURR_FREQ_SCALE_FACTOR                           , 1   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_FACTOR     );
+REG64_FLD( EX_L2_SPURR_FREQ_SCALE_FACTOR_LEN                       , 7   , SH_UNT_EX_L2    , SH_ACS_SCOM_RW  ,
+           SH_FLD_FACTOR_LEN );
+
+REG64_FLD( C_SPURR_FREQ_SCALE_OVERRIDE_EN                          , 0   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_OVERRIDE_EN );
+REG64_FLD( C_SPURR_FREQ_SCALE_FACTOR                               , 1   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_FACTOR     );
+REG64_FLD( C_SPURR_FREQ_SCALE_FACTOR_LEN                           , 7   , SH_UNT_C        , SH_ACS_SCOM_RW  ,
+           SH_FLD_FACTOR_LEN );
+
+REG64_FLD( EQ_SUM_MASK_REG_SMASK_IN0                               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN0  );
+REG64_FLD( EQ_SUM_MASK_REG_SMASK_IN1                               , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN1  );
+REG64_FLD( EQ_SUM_MASK_REG_SMASK_IN2                               , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN2  );
+REG64_FLD( EQ_SUM_MASK_REG_SMASK_IN3                               , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN3  );
+REG64_FLD( EQ_SUM_MASK_REG_SMASK_IN4                               , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN4  );
+
+REG64_FLD( EX_SUM_MASK_REG_SMASK_IN0                               , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN0  );
+REG64_FLD( EX_SUM_MASK_REG_SMASK_IN1                               , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN1  );
+REG64_FLD( EX_SUM_MASK_REG_SMASK_IN2                               , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN2  );
+REG64_FLD( EX_SUM_MASK_REG_SMASK_IN3                               , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN3  );
+REG64_FLD( EX_SUM_MASK_REG_SMASK_IN4                               , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN4  );
+
+REG64_FLD( C_SUM_MASK_REG_SMASK_IN0                                , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN0  );
+REG64_FLD( C_SUM_MASK_REG_SMASK_IN1                                , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN1  );
+REG64_FLD( C_SUM_MASK_REG_SMASK_IN2                                , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN2  );
+REG64_FLD( C_SUM_MASK_REG_SMASK_IN3                                , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN3  );
+REG64_FLD( C_SUM_MASK_REG_SMASK_IN4                                , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SMASK_IN4  );
+
+REG64_FLD( EQ_SYNC_CONFIG_PULSE_DELAY                              , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PULSE_DELAY );
+REG64_FLD( EQ_SYNC_CONFIG_PULSE_DELAY_LEN                          , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PULSE_DELAY_LEN );
+REG64_FLD( EQ_SYNC_CONFIG_LISTEN_TO_PULSE_DIS                      , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_LISTEN_TO_PULSE_DIS );
+REG64_FLD( EQ_SYNC_CONFIG_PULSE_INPUT_SEL                          , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PULSE_INPUT_SEL );
+REG64_FLD( EQ_SYNC_CONFIG_USE_FOR_SCAN                             , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_USE_FOR_SCAN );
+REG64_FLD( EQ_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED                 , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CLEAR_CHIPLET_IS_ALIGNED );
+REG64_FLD( EQ_SYNC_CONFIG_UNIT_REGION_CLKCMD_DISABLE               , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT_REGION_CLKCMD_DISABLE );
+REG64_FLD( EQ_SYNC_CONFIG_DISABLE_PCB_ITR                          , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_PCB_ITR );
+REG64_FLD( EQ_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK                  , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_VITL_ALIGN_CHECK );
+REG64_FLD( EQ_SYNC_CONFIG_UNUSED1119                               , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1119 );
+REG64_FLD( EQ_SYNC_CONFIG_UNUSED1119_LEN                           , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1119_LEN );
+
+REG64_FLD( EX_SYNC_CONFIG_PULSE_DELAY                              , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PULSE_DELAY );
+REG64_FLD( EX_SYNC_CONFIG_PULSE_DELAY_LEN                          , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PULSE_DELAY_LEN );
+REG64_FLD( EX_SYNC_CONFIG_LISTEN_TO_PULSE_DIS                      , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_LISTEN_TO_PULSE_DIS );
+REG64_FLD( EX_SYNC_CONFIG_PULSE_INPUT_SEL                          , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PULSE_INPUT_SEL );
+REG64_FLD( EX_SYNC_CONFIG_USE_FOR_SCAN                             , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_USE_FOR_SCAN );
+REG64_FLD( EX_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED                 , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CLEAR_CHIPLET_IS_ALIGNED );
+REG64_FLD( EX_SYNC_CONFIG_UNIT_REGION_CLKCMD_DISABLE               , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT_REGION_CLKCMD_DISABLE );
+REG64_FLD( EX_SYNC_CONFIG_DISABLE_PCB_ITR                          , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_PCB_ITR );
+REG64_FLD( EX_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK                  , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_VITL_ALIGN_CHECK );
+REG64_FLD( EX_SYNC_CONFIG_UNUSED1119                               , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1119 );
+REG64_FLD( EX_SYNC_CONFIG_UNUSED1119_LEN                           , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1119_LEN );
+
+REG64_FLD( C_SYNC_CONFIG_PULSE_DELAY                               , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PULSE_DELAY );
+REG64_FLD( C_SYNC_CONFIG_PULSE_DELAY_LEN                           , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PULSE_DELAY_LEN );
+REG64_FLD( C_SYNC_CONFIG_LISTEN_TO_PULSE_DIS                       , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_LISTEN_TO_PULSE_DIS );
+REG64_FLD( C_SYNC_CONFIG_PULSE_INPUT_SEL                           , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PULSE_INPUT_SEL );
+REG64_FLD( C_SYNC_CONFIG_USE_FOR_SCAN                              , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_USE_FOR_SCAN );
+REG64_FLD( C_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED                  , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_CLEAR_CHIPLET_IS_ALIGNED );
+REG64_FLD( C_SYNC_CONFIG_UNIT_REGION_CLKCMD_DISABLE                , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT_REGION_CLKCMD_DISABLE );
+REG64_FLD( C_SYNC_CONFIG_DISABLE_PCB_ITR                           , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_PCB_ITR );
+REG64_FLD( C_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK                   , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_VITL_ALIGN_CHECK );
+REG64_FLD( C_SYNC_CONFIG_UNUSED1119                                , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1119 );
+REG64_FLD( C_SYNC_CONFIG_UNUSED1119_LEN                            , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1119_LEN );
+
+REG64_FLD( EQ_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR                   , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DIS_CPM_BUBBLE_CORR );
+REG64_FLD( EQ_THERM_MODE_REG_FORCE_THRES_ACT                       , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_THRES_ACT );
+REG64_FLD( EQ_THERM_MODE_REG_THRES_TRIP_ENA                        , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_THRES_TRIP_ENA );
+REG64_FLD( EQ_THERM_MODE_REG_THRES_TRIP_ENA_LEN                    , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_THRES_TRIP_ENA_LEN );
+REG64_FLD( EQ_THERM_MODE_REG_DTS_SAMPLE_ENA                        , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DTS_SAMPLE_ENA );
+REG64_FLD( EQ_THERM_MODE_REG_SAMPLE_PULSE_CNT                      , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_PULSE_CNT );
+REG64_FLD( EQ_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN                  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_PULSE_CNT_LEN );
+REG64_FLD( EQ_THERM_MODE_REG_THRES_ENA                             , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_THRES_ENA  );
+REG64_FLD( EQ_THERM_MODE_REG_THRES_ENA_LEN                         , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_THRES_ENA_LEN );
+REG64_FLD( EQ_THERM_MODE_REG_DTS_TRIGGER                           , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DTS_TRIGGER );
+REG64_FLD( EQ_THERM_MODE_REG_DTS_TRIGGER_SEL                       , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DTS_TRIGGER_SEL );
+REG64_FLD( EQ_THERM_MODE_REG_THRES_OVERFLOW_MASK                   , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_THRES_OVERFLOW_MASK );
+REG64_FLD( EQ_THERM_MODE_REG_UNUSED                                , 15  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EQ_THERM_MODE_REG_DTS_READ_SEL                          , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DTS_READ_SEL );
+REG64_FLD( EQ_THERM_MODE_REG_DTS_READ_SEL_LEN                      , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DTS_READ_SEL_LEN );
+REG64_FLD( EQ_THERM_MODE_REG_DTS_ENABLE_L1                         , 20  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DTS_ENABLE_L1 );
+REG64_FLD( EQ_THERM_MODE_REG_DTS_ENABLE_L1_LEN                     , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DTS_ENABLE_L1_LEN );
+
+REG64_FLD( EX_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR                   , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DIS_CPM_BUBBLE_CORR );
+REG64_FLD( EX_THERM_MODE_REG_FORCE_THRES_ACT                       , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_THRES_ACT );
+REG64_FLD( EX_THERM_MODE_REG_THRES_TRIP_ENA                        , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_THRES_TRIP_ENA );
+REG64_FLD( EX_THERM_MODE_REG_THRES_TRIP_ENA_LEN                    , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_THRES_TRIP_ENA_LEN );
+REG64_FLD( EX_THERM_MODE_REG_DTS_SAMPLE_ENA                        , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DTS_SAMPLE_ENA );
+REG64_FLD( EX_THERM_MODE_REG_SAMPLE_PULSE_CNT                      , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_PULSE_CNT );
+REG64_FLD( EX_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN                  , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_PULSE_CNT_LEN );
+REG64_FLD( EX_THERM_MODE_REG_THRES_ENA                             , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_THRES_ENA  );
+REG64_FLD( EX_THERM_MODE_REG_THRES_ENA_LEN                         , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_THRES_ENA_LEN );
+REG64_FLD( EX_THERM_MODE_REG_DTS_TRIGGER                           , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DTS_TRIGGER );
+REG64_FLD( EX_THERM_MODE_REG_DTS_TRIGGER_SEL                       , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DTS_TRIGGER_SEL );
+REG64_FLD( EX_THERM_MODE_REG_THRES_OVERFLOW_MASK                   , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_THRES_OVERFLOW_MASK );
+REG64_FLD( EX_THERM_MODE_REG_UNUSED                                , 15  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EX_THERM_MODE_REG_DTS_READ_SEL                          , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DTS_READ_SEL );
+REG64_FLD( EX_THERM_MODE_REG_DTS_READ_SEL_LEN                      , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DTS_READ_SEL_LEN );
+REG64_FLD( EX_THERM_MODE_REG_DTS_ENABLE_L1                         , 20  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DTS_ENABLE_L1 );
+REG64_FLD( EX_THERM_MODE_REG_DTS_ENABLE_L1_LEN                     , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DTS_ENABLE_L1_LEN );
+
+REG64_FLD( C_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR                    , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DIS_CPM_BUBBLE_CORR );
+REG64_FLD( C_THERM_MODE_REG_FORCE_THRES_ACT                        , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_FORCE_THRES_ACT );
+REG64_FLD( C_THERM_MODE_REG_THRES_TRIP_ENA                         , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_THRES_TRIP_ENA );
+REG64_FLD( C_THERM_MODE_REG_THRES_TRIP_ENA_LEN                     , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_THRES_TRIP_ENA_LEN );
+REG64_FLD( C_THERM_MODE_REG_DTS_SAMPLE_ENA                         , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DTS_SAMPLE_ENA );
+REG64_FLD( C_THERM_MODE_REG_SAMPLE_PULSE_CNT                       , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_PULSE_CNT );
+REG64_FLD( C_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN                   , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_SAMPLE_PULSE_CNT_LEN );
+REG64_FLD( C_THERM_MODE_REG_THRES_ENA                              , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_THRES_ENA  );
+REG64_FLD( C_THERM_MODE_REG_THRES_ENA_LEN                          , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_THRES_ENA_LEN );
+REG64_FLD( C_THERM_MODE_REG_DTS_TRIGGER                            , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DTS_TRIGGER );
+REG64_FLD( C_THERM_MODE_REG_DTS_TRIGGER_SEL                        , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DTS_TRIGGER_SEL );
+REG64_FLD( C_THERM_MODE_REG_THRES_OVERFLOW_MASK                    , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_THRES_OVERFLOW_MASK );
+REG64_FLD( C_THERM_MODE_REG_UNUSED                                 , 15  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( C_THERM_MODE_REG_DTS_READ_SEL                           , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DTS_READ_SEL );
+REG64_FLD( C_THERM_MODE_REG_DTS_READ_SEL_LEN                       , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DTS_READ_SEL_LEN );
+REG64_FLD( C_THERM_MODE_REG_DTS_ENABLE_L1                          , 20  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DTS_ENABLE_L1 );
+REG64_FLD( C_THERM_MODE_REG_DTS_ENABLE_L1_LEN                      , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DTS_ENABLE_L1_LEN );
+
+REG64_FLD( EQ_TIMESTAMP_COUNTER_READ_VALUE                         , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VALUE      );
+REG64_FLD( EQ_TIMESTAMP_COUNTER_READ_VALUE_LEN                     , 44  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VALUE_LEN  );
+REG64_FLD( EQ_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR                  , 44  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_OVERFLOW_ERR );
+
+REG64_FLD( EX_TIMESTAMP_COUNTER_READ_VALUE                         , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VALUE      );
+REG64_FLD( EX_TIMESTAMP_COUNTER_READ_VALUE_LEN                     , 44  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_VALUE_LEN  );
+REG64_FLD( EX_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR                  , 44  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_OVERFLOW_ERR );
+
+REG64_FLD( C_TIMESTAMP_COUNTER_READ_VALUE                          , 0   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_VALUE      );
+REG64_FLD( C_TIMESTAMP_COUNTER_READ_VALUE_LEN                      , 44  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_VALUE_LEN  );
+REG64_FLD( C_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR                   , 44  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_OVERFLOW_ERR );
+
+REG64_FLD( EX_L2_TOD_READ_TIMEBASE                                 , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( EX_L2_TOD_READ_TIMEBASE_LEN                             , 60  , SH_UNT_EX_L2    , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMEBASE_LEN );
+
+REG64_FLD( C_TOD_READ_TIMEBASE                                     , 0   , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( C_TOD_READ_TIMEBASE_LEN                                 , 60  , SH_UNT_C        , SH_ACS_SCOM_RO  ,
+           SH_FLD_TIMEBASE_LEN );
+
+REG64_FLD( EX_L2_TOD_SYNC000_TIMEBASE                              , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( EX_L2_TOD_SYNC000_TIMEBASE_LEN                          , 55  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( EX_L2_TOD_SYNC000_CHIP_STATUS                           , 60  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( EX_L2_TOD_SYNC000_CHIP_STATUS_LEN                       , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( C_TOD_SYNC000_TIMEBASE                                  , 0   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( C_TOD_SYNC000_TIMEBASE_LEN                              , 55  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( C_TOD_SYNC000_CHIP_STATUS                               , 60  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( C_TOD_SYNC000_CHIP_STATUS_LEN                           , 4   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( EX_L2_TOD_SYNC001_TIMEBASE                              , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( EX_L2_TOD_SYNC001_TIMEBASE_LEN                          , 54  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( EX_L2_TOD_SYNC001_CHIP_STATUS                           , 60  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( EX_L2_TOD_SYNC001_CHIP_STATUS_LEN                       , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( C_TOD_SYNC001_TIMEBASE                                  , 0   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( C_TOD_SYNC001_TIMEBASE_LEN                              , 54  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( C_TOD_SYNC001_CHIP_STATUS                               , 60  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( C_TOD_SYNC001_CHIP_STATUS_LEN                           , 4   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( EX_L2_TOD_SYNC010_TIMEBASE                              , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( EX_L2_TOD_SYNC010_TIMEBASE_LEN                          , 53  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( EX_L2_TOD_SYNC010_CHIP_STATUS                           , 60  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( EX_L2_TOD_SYNC010_CHIP_STATUS_LEN                       , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( C_TOD_SYNC010_TIMEBASE                                  , 0   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( C_TOD_SYNC010_TIMEBASE_LEN                              , 53  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( C_TOD_SYNC010_CHIP_STATUS                               , 60  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( C_TOD_SYNC010_CHIP_STATUS_LEN                           , 4   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( EX_L2_TOD_SYNC011_TIMEBASE                              , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( EX_L2_TOD_SYNC011_TIMEBASE_LEN                          , 52  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( EX_L2_TOD_SYNC011_CHIP_STATUS                           , 60  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( EX_L2_TOD_SYNC011_CHIP_STATUS_LEN                       , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( C_TOD_SYNC011_TIMEBASE                                  , 0   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( C_TOD_SYNC011_TIMEBASE_LEN                              , 52  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( C_TOD_SYNC011_CHIP_STATUS                               , 60  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( C_TOD_SYNC011_CHIP_STATUS_LEN                           , 4   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( EX_L2_TOD_SYNC100_TIMEBASE                              , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( EX_L2_TOD_SYNC100_TIMEBASE_LEN                          , 51  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( EX_L2_TOD_SYNC100_CHIP_STATUS                           , 60  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( EX_L2_TOD_SYNC100_CHIP_STATUS_LEN                       , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( C_TOD_SYNC100_TIMEBASE                                  , 0   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( C_TOD_SYNC100_TIMEBASE_LEN                              , 51  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( C_TOD_SYNC100_CHIP_STATUS                               , 60  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( C_TOD_SYNC100_CHIP_STATUS_LEN                           , 4   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( EX_L2_TOD_SYNC101_TIMEBASE                              , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( EX_L2_TOD_SYNC101_TIMEBASE_LEN                          , 50  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( EX_L2_TOD_SYNC101_CHIP_STATUS                           , 60  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( EX_L2_TOD_SYNC101_CHIP_STATUS_LEN                       , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( C_TOD_SYNC101_TIMEBASE                                  , 0   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( C_TOD_SYNC101_TIMEBASE_LEN                              , 50  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( C_TOD_SYNC101_CHIP_STATUS                               , 60  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( C_TOD_SYNC101_CHIP_STATUS_LEN                           , 4   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( EX_L2_TOD_SYNC110_TIMEBASE                              , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( EX_L2_TOD_SYNC110_TIMEBASE_LEN                          , 49  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( EX_L2_TOD_SYNC110_CHIP_STATUS                           , 60  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( EX_L2_TOD_SYNC110_CHIP_STATUS_LEN                       , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( C_TOD_SYNC110_TIMEBASE                                  , 0   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( C_TOD_SYNC110_TIMEBASE_LEN                              , 49  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( C_TOD_SYNC110_CHIP_STATUS                               , 60  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( C_TOD_SYNC110_CHIP_STATUS_LEN                           , 4   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( EX_L2_TOD_SYNC111_TIMEBASE                              , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( EX_L2_TOD_SYNC111_TIMEBASE_LEN                          , 48  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( EX_L2_TOD_SYNC111_CHIP_STATUS                           , 60  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( EX_L2_TOD_SYNC111_CHIP_STATUS_LEN                       , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( C_TOD_SYNC111_TIMEBASE                                  , 0   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE   );
+REG64_FLD( C_TOD_SYNC111_TIMEBASE_LEN                              , 48  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_TIMEBASE_LEN );
+REG64_FLD( C_TOD_SYNC111_CHIP_STATUS                               , 60  , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS );
+REG64_FLD( C_TOD_SYNC111_CHIP_STATUS_LEN                           , 4   , SH_UNT_C        , SH_ACS_SCOM1_WO ,
+           SH_FLD_CHIP_STATUS_LEN );
+
+REG64_FLD( EQ_TPLC20_TR0_TRACE_HI_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_HI_DATA_REG_DATA_LEN                , 64  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EX_TPLC20_TR0_TRACE_HI_DATA_REG_DATA                    , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EX_TPLC20_TR0_TRACE_HI_DATA_REG_DATA_LEN                , 64  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_DATA_LEN                , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_ADDRESS                 , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN             , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_LAST_BANK               , 42  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN           , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID         , 51  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN            , 52  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_RUNNING                 , 53  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS            , 54  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN        , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_DATA                    , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_DATA_LEN                , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_ADDRESS                 , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN             , 10  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_LAST_BANK               , 42  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN           , 9   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID         , 51  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN            , 52  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_RUNNING                 , 53  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS            , 54  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN        , 10  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE    , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE    , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63  , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA            , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN        , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB            , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN        , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERND            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC            , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN        , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERND            , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN        , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKA               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKB               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKA               , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN           , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKB               , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN           , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKC               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKD               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKC               , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN           , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKD               , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN           , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL       , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL       , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL       , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL       , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK       , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK      , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK       , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK      , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE      , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE      , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE      , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_EX       ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL       , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN   , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL       , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN   , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL       , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN   , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL       , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN   , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK       , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN   , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK      , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN  , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK       , 18  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN   , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK      , 22  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN  , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE      , 26  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE      , 27  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE      , 28  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN  , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( EQ_TPLC20_TR1_TRACE_HI_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_HI_DATA_REG_DATA_LEN                , 64  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EX_TPLC20_TR1_TRACE_HI_DATA_REG_DATA                    , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EX_TPLC20_TR1_TRACE_HI_DATA_REG_DATA_LEN                , 64  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_DATA_LEN                , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_ADDRESS                 , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN             , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_LAST_BANK               , 42  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN           , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID         , 51  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN            , 52  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_RUNNING                 , 53  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS            , 54  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN        , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_DATA                    , 0   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_DATA_LEN                , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_ADDRESS                 , 32  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN             , 10  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_LAST_BANK               , 42  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN           , 9   , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID         , 51  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN            , 52  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_RUNNING                 , 53  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS            , 54  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN        , 10  , SH_UNT_EX       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE    , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE    , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63  , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA            , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN        , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB            , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN        , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERND            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC            , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN        , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERND            , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN        , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKA               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKB               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKA               , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN           , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKB               , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN           , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKC               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKD               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKC               , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN           , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKD               , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN           , 24  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL       , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL       , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL       , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL       , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK       , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK      , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK       , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK      , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE      , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE      , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE      , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_EX       ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL       , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN   , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL       , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN   , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL       , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN   , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL       , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN   , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK       , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN   , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK      , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN  , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK       , 18  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN   , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK      , 22  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN  , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE      , 26  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE      , 27  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE      , 28  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN  , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( EQ_TPLC21_TR0_TRACE_HI_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_HI_DATA_REG_DATA_LEN                , 64  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_DATA_LEN                , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_ADDRESS                 , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN             , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_LAST_BANK               , 42  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN           , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID         , 51  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN            , 52  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_RUNNING                 , 53  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS            , 54  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN        , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE    , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_3_PATTERND            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_4_MASKA               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_4_MASKB               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_5_MASKC               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_5_MASKD               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL       , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL       , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL       , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL       , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK       , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK      , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK       , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK      , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE      , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE      , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE      , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( EQ_TPLC21_TR1_TRACE_HI_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_HI_DATA_REG_DATA_LEN                , 64  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_DATA                    , 0   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_DATA_LEN                , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_ADDRESS                 , 32  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN             , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_LAST_BANK               , 42  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN           , 9   , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID         , 51  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN            , 52  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_RUNNING                 , 53  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS            , 54  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN        , 10  , SH_UNT_EQ       , SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE    , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63  , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC            , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_3_PATTERND            , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN        , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_4_MASKA               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_4_MASKB               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_5_MASKC               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_5_MASKD               , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN           , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_EQ       ,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL       , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL       , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL       , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL       , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN   , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK       , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK      , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK       , 18  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN   , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK      , 22  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE      , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE      , 27  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE      , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN  , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( EX_V0_HMER_MALFUNCTION_ALERT                            , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_MALFUNCTION_ALERT );
+REG64_FLD( EX_V0_HMER_CME_REQUEST                                  , 1   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_REQUEST );
+REG64_FLD( EX_V0_HMER_PROC_RCVY_DONE                               , 2   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_DONE );
+REG64_FLD( EX_V0_HMER_TFAC_ERR                                     , 4   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFAC_ERR   );
+REG64_FLD( EX_V0_HMER_TFMR_PARITY_ERR                              , 5   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFMR_PARITY_ERR );
+REG64_FLD( EX_V0_HMER_XSCOM_FAIL                                   , 8   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_FAIL );
+REG64_FLD( EX_V0_HMER_XSCOM_DONE                                   , 9   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_DONE );
+REG64_FLD( EX_V0_HMER_PROC_RCVY_AGAIN                              , 11  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_AGAIN );
+REG64_FLD( EX_V0_HMER_SCOM_FIR_HMI                                 , 16  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_FIR_HMI );
+REG64_FLD( EX_V0_HMER_TRIG_FIR_HMI                                 , 17  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TRIG_FIR_HMI );
+REG64_FLD( EX_V0_HMER_HYP_RECOURCE_ERR                             , 20  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_HYP_RECOURCE_ERR );
+REG64_FLD( EX_V0_HMER_XSCOM_STATUS                                 , 21  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS );
+REG64_FLD( EX_V0_HMER_XSCOM_STATUS_LEN                             , 3   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS_LEN );
+
+REG64_FLD( EX_L2_V0_HMER_MALFUNCTION_ALERT                         , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_MALFUNCTION_ALERT );
+REG64_FLD( EX_L2_V0_HMER_CME_REQUEST                               , 1   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_CME_REQUEST );
+REG64_FLD( EX_L2_V0_HMER_PROC_RCVY_DONE                            , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_PROC_RCVY_DONE );
+REG64_FLD( EX_L2_V0_HMER_TFAC_ERR                                  , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_TFAC_ERR   );
+REG64_FLD( EX_L2_V0_HMER_TFMR_PARITY_ERR                           , 5   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_TFMR_PARITY_ERR );
+REG64_FLD( EX_L2_V0_HMER_XSCOM_FAIL                                , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_XSCOM_FAIL );
+REG64_FLD( EX_L2_V0_HMER_XSCOM_DONE                                , 9   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_XSCOM_DONE );
+REG64_FLD( EX_L2_V0_HMER_PROC_RCVY_AGAIN                           , 11  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_PROC_RCVY_AGAIN );
+REG64_FLD( EX_L2_V0_HMER_SCOM_FIR_HMI                              , 16  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_SCOM_FIR_HMI );
+REG64_FLD( EX_L2_V0_HMER_TRIG_FIR_HMI                              , 17  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_TRIG_FIR_HMI );
+REG64_FLD( EX_L2_V0_HMER_HYP_RECOURCE_ERR                          , 20  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_HYP_RECOURCE_ERR );
+REG64_FLD( EX_L2_V0_HMER_XSCOM_STATUS                              , 21  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_XSCOM_STATUS );
+REG64_FLD( EX_L2_V0_HMER_XSCOM_STATUS_LEN                          , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_XSCOM_STATUS_LEN );
+
+REG64_FLD( C_V0_HMER_MALFUNCTION_ALERT                             , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_MALFUNCTION_ALERT );
+REG64_FLD( C_V0_HMER_CME_REQUEST                                   , 1   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_REQUEST );
+REG64_FLD( C_V0_HMER_PROC_RCVY_DONE                                , 2   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_DONE );
+REG64_FLD( C_V0_HMER_TFAC_ERR                                      , 4   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFAC_ERR   );
+REG64_FLD( C_V0_HMER_TFMR_PARITY_ERR                               , 5   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFMR_PARITY_ERR );
+REG64_FLD( C_V0_HMER_XSCOM_FAIL                                    , 8   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_FAIL );
+REG64_FLD( C_V0_HMER_XSCOM_DONE                                    , 9   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_DONE );
+REG64_FLD( C_V0_HMER_PROC_RCVY_AGAIN                               , 11  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_AGAIN );
+REG64_FLD( C_V0_HMER_SCOM_FIR_HMI                                  , 16  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_FIR_HMI );
+REG64_FLD( C_V0_HMER_TRIG_FIR_HMI                                  , 17  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_TRIG_FIR_HMI );
+REG64_FLD( C_V0_HMER_HYP_RECOURCE_ERR                              , 20  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_HYP_RECOURCE_ERR );
+REG64_FLD( C_V0_HMER_XSCOM_STATUS                                  , 21  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS );
+REG64_FLD( C_V0_HMER_XSCOM_STATUS_LEN                              , 3   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS_LEN );
+
+REG64_FLD( EX_V1_HMER_MALFUNCTION_ALERT                            , 0   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_MALFUNCTION_ALERT );
+REG64_FLD( EX_V1_HMER_CME_REQUEST                                  , 1   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_REQUEST );
+REG64_FLD( EX_V1_HMER_PROC_RCVY_DONE                               , 2   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_DONE );
+REG64_FLD( EX_V1_HMER_TFAC_ERR                                     , 4   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFAC_ERR   );
+REG64_FLD( EX_V1_HMER_TFMR_PARITY_ERR                              , 5   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFMR_PARITY_ERR );
+REG64_FLD( EX_V1_HMER_XSCOM_FAIL                                   , 8   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_FAIL );
+REG64_FLD( EX_V1_HMER_XSCOM_DONE                                   , 9   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_DONE );
+REG64_FLD( EX_V1_HMER_PROC_RCVY_AGAIN                              , 11  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_AGAIN );
+REG64_FLD( EX_V1_HMER_SCOM_FIR_HMI                                 , 16  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_FIR_HMI );
+REG64_FLD( EX_V1_HMER_TRIG_FIR_HMI                                 , 17  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_TRIG_FIR_HMI );
+REG64_FLD( EX_V1_HMER_HYP_RECOURCE_ERR                             , 20  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_HYP_RECOURCE_ERR );
+REG64_FLD( EX_V1_HMER_XSCOM_STATUS                                 , 21  , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS );
+REG64_FLD( EX_V1_HMER_XSCOM_STATUS_LEN                             , 3   , SH_UNT_EX       , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS_LEN );
+
+REG64_FLD( EX_L2_V1_HMER_MALFUNCTION_ALERT                         , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_MALFUNCTION_ALERT );
+REG64_FLD( EX_L2_V1_HMER_CME_REQUEST                               , 1   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_CME_REQUEST );
+REG64_FLD( EX_L2_V1_HMER_PROC_RCVY_DONE                            , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_PROC_RCVY_DONE );
+REG64_FLD( EX_L2_V1_HMER_TFAC_ERR                                  , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_TFAC_ERR   );
+REG64_FLD( EX_L2_V1_HMER_TFMR_PARITY_ERR                           , 5   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_TFMR_PARITY_ERR );
+REG64_FLD( EX_L2_V1_HMER_XSCOM_FAIL                                , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_XSCOM_FAIL );
+REG64_FLD( EX_L2_V1_HMER_XSCOM_DONE                                , 9   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_XSCOM_DONE );
+REG64_FLD( EX_L2_V1_HMER_PROC_RCVY_AGAIN                           , 11  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_PROC_RCVY_AGAIN );
+REG64_FLD( EX_L2_V1_HMER_SCOM_FIR_HMI                              , 16  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_SCOM_FIR_HMI );
+REG64_FLD( EX_L2_V1_HMER_TRIG_FIR_HMI                              , 17  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_TRIG_FIR_HMI );
+REG64_FLD( EX_L2_V1_HMER_HYP_RECOURCE_ERR                          , 20  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_HYP_RECOURCE_ERR );
+REG64_FLD( EX_L2_V1_HMER_XSCOM_STATUS                              , 21  , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_XSCOM_STATUS );
+REG64_FLD( EX_L2_V1_HMER_XSCOM_STATUS_LEN                          , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM1_WAND,
+           SH_FLD_XSCOM_STATUS_LEN );
+
+REG64_FLD( C_V1_HMER_MALFUNCTION_ALERT                             , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_MALFUNCTION_ALERT );
+REG64_FLD( C_V1_HMER_CME_REQUEST                                   , 1   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_REQUEST );
+REG64_FLD( C_V1_HMER_PROC_RCVY_DONE                                , 2   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_DONE );
+REG64_FLD( C_V1_HMER_TFAC_ERR                                      , 4   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFAC_ERR   );
+REG64_FLD( C_V1_HMER_TFMR_PARITY_ERR                               , 5   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFMR_PARITY_ERR );
+REG64_FLD( C_V1_HMER_XSCOM_FAIL                                    , 8   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_FAIL );
+REG64_FLD( C_V1_HMER_XSCOM_DONE                                    , 9   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_DONE );
+REG64_FLD( C_V1_HMER_PROC_RCVY_AGAIN                               , 11  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_AGAIN );
+REG64_FLD( C_V1_HMER_SCOM_FIR_HMI                                  , 16  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_FIR_HMI );
+REG64_FLD( C_V1_HMER_TRIG_FIR_HMI                                  , 17  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_TRIG_FIR_HMI );
+REG64_FLD( C_V1_HMER_HYP_RECOURCE_ERR                              , 20  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_HYP_RECOURCE_ERR );
+REG64_FLD( C_V1_HMER_XSCOM_STATUS                                  , 21  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS );
+REG64_FLD( C_V1_HMER_XSCOM_STATUS_LEN                              , 3   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS_LEN );
+
+REG64_FLD( EX_L2_V2_HMER_MALFUNCTION_ALERT                         , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_MALFUNCTION_ALERT );
+REG64_FLD( EX_L2_V2_HMER_CME_REQUEST                               , 1   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_REQUEST );
+REG64_FLD( EX_L2_V2_HMER_PROC_RCVY_DONE                            , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_DONE );
+REG64_FLD( EX_L2_V2_HMER_TFAC_ERR                                  , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFAC_ERR   );
+REG64_FLD( EX_L2_V2_HMER_TFMR_PARITY_ERR                           , 5   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFMR_PARITY_ERR );
+REG64_FLD( EX_L2_V2_HMER_XSCOM_FAIL                                , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_FAIL );
+REG64_FLD( EX_L2_V2_HMER_XSCOM_DONE                                , 9   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_DONE );
+REG64_FLD( EX_L2_V2_HMER_PROC_RCVY_AGAIN                           , 11  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_AGAIN );
+REG64_FLD( EX_L2_V2_HMER_SCOM_FIR_HMI                              , 16  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_FIR_HMI );
+REG64_FLD( EX_L2_V2_HMER_TRIG_FIR_HMI                              , 17  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_TRIG_FIR_HMI );
+REG64_FLD( EX_L2_V2_HMER_HYP_RECOURCE_ERR                          , 20  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_HYP_RECOURCE_ERR );
+REG64_FLD( EX_L2_V2_HMER_XSCOM_STATUS                              , 21  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS );
+REG64_FLD( EX_L2_V2_HMER_XSCOM_STATUS_LEN                          , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS_LEN );
+
+REG64_FLD( C_V2_HMER_MALFUNCTION_ALERT                             , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_MALFUNCTION_ALERT );
+REG64_FLD( C_V2_HMER_CME_REQUEST                                   , 1   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_REQUEST );
+REG64_FLD( C_V2_HMER_PROC_RCVY_DONE                                , 2   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_DONE );
+REG64_FLD( C_V2_HMER_TFAC_ERR                                      , 4   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFAC_ERR   );
+REG64_FLD( C_V2_HMER_TFMR_PARITY_ERR                               , 5   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFMR_PARITY_ERR );
+REG64_FLD( C_V2_HMER_XSCOM_FAIL                                    , 8   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_FAIL );
+REG64_FLD( C_V2_HMER_XSCOM_DONE                                    , 9   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_DONE );
+REG64_FLD( C_V2_HMER_PROC_RCVY_AGAIN                               , 11  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_AGAIN );
+REG64_FLD( C_V2_HMER_SCOM_FIR_HMI                                  , 16  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_FIR_HMI );
+REG64_FLD( C_V2_HMER_TRIG_FIR_HMI                                  , 17  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_TRIG_FIR_HMI );
+REG64_FLD( C_V2_HMER_HYP_RECOURCE_ERR                              , 20  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_HYP_RECOURCE_ERR );
+REG64_FLD( C_V2_HMER_XSCOM_STATUS                                  , 21  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS );
+REG64_FLD( C_V2_HMER_XSCOM_STATUS_LEN                              , 3   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS_LEN );
+
+REG64_FLD( EX_L2_V3_HMER_MALFUNCTION_ALERT                         , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_MALFUNCTION_ALERT );
+REG64_FLD( EX_L2_V3_HMER_CME_REQUEST                               , 1   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_REQUEST );
+REG64_FLD( EX_L2_V3_HMER_PROC_RCVY_DONE                            , 2   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_DONE );
+REG64_FLD( EX_L2_V3_HMER_TFAC_ERR                                  , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFAC_ERR   );
+REG64_FLD( EX_L2_V3_HMER_TFMR_PARITY_ERR                           , 5   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFMR_PARITY_ERR );
+REG64_FLD( EX_L2_V3_HMER_XSCOM_FAIL                                , 8   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_FAIL );
+REG64_FLD( EX_L2_V3_HMER_XSCOM_DONE                                , 9   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_DONE );
+REG64_FLD( EX_L2_V3_HMER_PROC_RCVY_AGAIN                           , 11  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_AGAIN );
+REG64_FLD( EX_L2_V3_HMER_SCOM_FIR_HMI                              , 16  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_FIR_HMI );
+REG64_FLD( EX_L2_V3_HMER_TRIG_FIR_HMI                              , 17  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_TRIG_FIR_HMI );
+REG64_FLD( EX_L2_V3_HMER_HYP_RECOURCE_ERR                          , 20  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_HYP_RECOURCE_ERR );
+REG64_FLD( EX_L2_V3_HMER_XSCOM_STATUS                              , 21  , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS );
+REG64_FLD( EX_L2_V3_HMER_XSCOM_STATUS_LEN                          , 3   , SH_UNT_EX_L2    , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS_LEN );
+
+REG64_FLD( C_V3_HMER_MALFUNCTION_ALERT                             , 0   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_MALFUNCTION_ALERT );
+REG64_FLD( C_V3_HMER_CME_REQUEST                                   , 1   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_CME_REQUEST );
+REG64_FLD( C_V3_HMER_PROC_RCVY_DONE                                , 2   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_DONE );
+REG64_FLD( C_V3_HMER_TFAC_ERR                                      , 4   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFAC_ERR   );
+REG64_FLD( C_V3_HMER_TFMR_PARITY_ERR                               , 5   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_TFMR_PARITY_ERR );
+REG64_FLD( C_V3_HMER_XSCOM_FAIL                                    , 8   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_FAIL );
+REG64_FLD( C_V3_HMER_XSCOM_DONE                                    , 9   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_DONE );
+REG64_FLD( C_V3_HMER_PROC_RCVY_AGAIN                               , 11  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_PROC_RCVY_AGAIN );
+REG64_FLD( C_V3_HMER_SCOM_FIR_HMI                                  , 16  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_FIR_HMI );
+REG64_FLD( C_V3_HMER_TRIG_FIR_HMI                                  , 17  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_TRIG_FIR_HMI );
+REG64_FLD( C_V3_HMER_HYP_RECOURCE_ERR                              , 20  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_HYP_RECOURCE_ERR );
+REG64_FLD( C_V3_HMER_XSCOM_STATUS                                  , 21  , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS );
+REG64_FLD( C_V3_HMER_XSCOM_STATUS_LEN                              , 3   , SH_UNT_C        , SH_ACS_SCOM2_OR ,
+           SH_FLD_XSCOM_STATUS_LEN );
+
+REG64_FLD( EQ_WRITE_PROTECT_ENABLE_REG_RING_LOCKING                , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RING_LOCKING );
+REG64_FLD( EQ_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING       , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_RING_LOCKING );
+
+REG64_FLD( EX_WRITE_PROTECT_ENABLE_REG_RING_LOCKING                , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RING_LOCKING );
+REG64_FLD( EX_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING       , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_RING_LOCKING );
+
+REG64_FLD( C_WRITE_PROTECT_ENABLE_REG_RING_LOCKING                 , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RING_LOCKING );
+REG64_FLD( C_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING        , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RESERVED_RING_LOCKING );
+
+REG64_FLD( EQ_WRITE_PROTECT_RINGS_REG_RINGS                        , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RINGS      );
+REG64_FLD( EQ_WRITE_PROTECT_RINGS_REG_RINGS_LEN                    , 16  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_RINGS_LEN  );
+
+REG64_FLD( EX_WRITE_PROTECT_RINGS_REG_RINGS                        , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RINGS      );
+REG64_FLD( EX_WRITE_PROTECT_RINGS_REG_RINGS_LEN                    , 16  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_RINGS_LEN  );
+
+REG64_FLD( C_WRITE_PROTECT_RINGS_REG_RINGS                         , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RINGS      );
+REG64_FLD( C_WRITE_PROTECT_RINGS_REG_RINGS_LEN                     , 16  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_RINGS_LEN  );
+
+REG64_FLD( EQ_WR_EPS_REG_TIER1_VALUE                               , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TIER1_VALUE );
+REG64_FLD( EQ_WR_EPS_REG_TIER1_VALUE_LEN                           , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TIER1_VALUE_LEN );
+REG64_FLD( EQ_WR_EPS_REG_TIER2_VALUE                               , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TIER2_VALUE );
+REG64_FLD( EQ_WR_EPS_REG_TIER2_VALUE_LEN                           , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TIER2_VALUE_LEN );
+REG64_FLD( EQ_WR_EPS_REG_DIVIDER_MODE                              , 24  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DIVIDER_MODE );
+REG64_FLD( EQ_WR_EPS_REG_DIVIDER_MODE_LEN                          , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DIVIDER_MODE_LEN );
+REG64_FLD( EQ_WR_EPS_REG_MODE_SEL                                  , 28  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MODE_SEL   );
+REG64_FLD( EQ_WR_EPS_REG_CNT_USE_L2_DIVIDER_EN                     , 29  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_CNT_USE_L2_DIVIDER_EN );
+REG64_FLD( EQ_WR_EPS_REG_L2_STEP_MODE                              , 30  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L2_STEP_MODE );
+REG64_FLD( EQ_WR_EPS_REG_L2_STEP_MODE_LEN                          , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_L2_STEP_MODE_LEN );
+
+REG64_FLD( EX_L2_WR_EPS_REG_TIER1_VALUE                            , 0   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_TIER1_VALUE );
+REG64_FLD( EX_L2_WR_EPS_REG_TIER1_VALUE_LEN                        , 12  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_TIER1_VALUE_LEN );
+REG64_FLD( EX_L2_WR_EPS_REG_TIER2_VALUE                            , 12  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_TIER2_VALUE );
+REG64_FLD( EX_L2_WR_EPS_REG_TIER2_VALUE_LEN                        , 12  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_TIER2_VALUE_LEN );
+REG64_FLD( EX_L2_WR_EPS_REG_DIVIDER_MODE                           , 24  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_DIVIDER_MODE );
+REG64_FLD( EX_L2_WR_EPS_REG_DIVIDER_MODE_LEN                       , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_DIVIDER_MODE_LEN );
+REG64_FLD( EX_L2_WR_EPS_REG_MODE_SEL                               , 28  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_MODE_SEL   );
+REG64_FLD( EX_L2_WR_EPS_REG_CNT_USE_L2_DIVIDER_EN                  , 29  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_CNT_USE_L2_DIVIDER_EN );
+REG64_FLD( EX_L2_WR_EPS_REG_L2_STEP_MODE                           , 30  , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_L2_STEP_MODE );
+REG64_FLD( EX_L2_WR_EPS_REG_L2_STEP_MODE_LEN                       , 4   , SH_UNT_EX_L2    , SH_ACS_SCOM     ,
+           SH_FLD_L2_STEP_MODE_LEN );
+
+REG64_FLD( EQ_XFIR_IN0                                             , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( EQ_XFIR_IN1                                             , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN1        );
+REG64_FLD( EQ_XFIR_IN2                                             , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN2        );
+REG64_FLD( EQ_XFIR_IN3                                             , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN3        );
+REG64_FLD( EQ_XFIR_IN4                                             , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( EQ_XFIR_IN5                                             , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( EQ_XFIR_IN6                                             , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN6        );
+REG64_FLD( EQ_XFIR_IN7                                             , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN7        );
+REG64_FLD( EQ_XFIR_IN8                                             , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN8        );
+REG64_FLD( EQ_XFIR_IN9                                             , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN9        );
+REG64_FLD( EQ_XFIR_IN10                                            , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN10       );
+REG64_FLD( EQ_XFIR_IN11                                            , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN11       );
+REG64_FLD( EQ_XFIR_IN12                                            , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN12       );
+REG64_FLD( EQ_XFIR_IN13                                            , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN13       );
+REG64_FLD( EQ_XFIR_IN13_LEN                                        , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN13_LEN   );
+REG64_FLD( EQ_XFIR_IN26                                            , 26  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_IN26       );
+
+REG64_FLD( EX_XFIR_IN0                                             , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( EX_XFIR_IN1                                             , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN1        );
+REG64_FLD( EX_XFIR_IN2                                             , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN2        );
+REG64_FLD( EX_XFIR_IN3                                             , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN3        );
+REG64_FLD( EX_XFIR_IN4                                             , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( EX_XFIR_IN5                                             , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( EX_XFIR_IN5_LEN                                         , 21  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN5_LEN    );
+REG64_FLD( EX_XFIR_IN26                                            , 26  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_IN26       );
+
+REG64_FLD( C_XFIR_IN0                                              , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN0        );
+REG64_FLD( C_XFIR_IN1                                              , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN1        );
+REG64_FLD( C_XFIR_IN2                                              , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN2        );
+REG64_FLD( C_XFIR_IN3                                              , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN3        );
+REG64_FLD( C_XFIR_IN4                                              , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN4        );
+REG64_FLD( C_XFIR_IN5                                              , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN5        );
+REG64_FLD( C_XFIR_IN5_LEN                                          , 21  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN5_LEN    );
+REG64_FLD( C_XFIR_IN26                                             , 26  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_IN26       );
+
+REG64_FLD( EQ_XSTOP1_MASK_B                                        , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASK_B     );
+REG64_FLD( EQ_XSTOP1_UNUSED                                        , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EQ_XSTOP1_TRIGGER_OPCG_ON                               , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( EQ_XSTOP1_WAIT_ALLWAYS                                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( EQ_XSTOP1_PERV                                          , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( EQ_XSTOP1_UNIT1                                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( EQ_XSTOP1_UNIT2                                         , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( EQ_XSTOP1_UNIT3                                         , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( EQ_XSTOP1_UNIT4                                         , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( EQ_XSTOP1_UNIT5                                         , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( EQ_XSTOP1_UNIT6                                         , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( EQ_XSTOP1_UNIT7                                         , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( EQ_XSTOP1_UNIT8                                         , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( EQ_XSTOP1_UNIT9                                         , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( EQ_XSTOP1_UNIT10                                        , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( EQ_XSTOP1_WAIT_CYCLES                                   , 48  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( EQ_XSTOP1_WAIT_CYCLES_LEN                               , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( EX_XSTOP1_MASK_B                                        , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASK_B     );
+REG64_FLD( EX_XSTOP1_UNUSED                                        , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EX_XSTOP1_TRIGGER_OPCG_ON                               , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( EX_XSTOP1_WAIT_ALLWAYS                                  , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( EX_XSTOP1_PERV                                          , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( EX_XSTOP1_UNIT1                                         , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( EX_XSTOP1_UNIT2                                         , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( EX_XSTOP1_UNIT3                                         , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( EX_XSTOP1_UNIT4                                         , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( EX_XSTOP1_UNIT5                                         , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( EX_XSTOP1_UNIT6                                         , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( EX_XSTOP1_UNIT7                                         , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( EX_XSTOP1_UNIT8                                         , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( EX_XSTOP1_UNIT9                                         , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( EX_XSTOP1_UNIT10                                        , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( EX_XSTOP1_WAIT_CYCLES                                   , 48  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( EX_XSTOP1_WAIT_CYCLES_LEN                               , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( C_XSTOP1_MASK_B                                         , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MASK_B     );
+REG64_FLD( C_XSTOP1_UNUSED                                         , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( C_XSTOP1_TRIGGER_OPCG_ON                                , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( C_XSTOP1_WAIT_ALLWAYS                                   , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( C_XSTOP1_PERV                                           , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( C_XSTOP1_UNIT1                                          , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( C_XSTOP1_UNIT2                                          , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( C_XSTOP1_UNIT3                                          , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( C_XSTOP1_UNIT4                                          , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( C_XSTOP1_UNIT5                                          , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( C_XSTOP1_UNIT6                                          , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( C_XSTOP1_UNIT7                                          , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( C_XSTOP1_UNIT8                                          , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( C_XSTOP1_UNIT9                                          , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( C_XSTOP1_UNIT10                                         , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( C_XSTOP1_WAIT_CYCLES                                    , 48  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( C_XSTOP1_WAIT_CYCLES_LEN                                , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( EQ_XSTOP2_MASK_B                                        , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASK_B     );
+REG64_FLD( EQ_XSTOP2_UNUSED                                        , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EQ_XSTOP2_TRIGGER_OPCG_ON                               , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( EQ_XSTOP2_WAIT_ALLWAYS                                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( EQ_XSTOP2_PERV                                          , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( EQ_XSTOP2_UNIT1                                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( EQ_XSTOP2_UNIT2                                         , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( EQ_XSTOP2_UNIT3                                         , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( EQ_XSTOP2_UNIT4                                         , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( EQ_XSTOP2_UNIT5                                         , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( EQ_XSTOP2_UNIT6                                         , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( EQ_XSTOP2_UNIT7                                         , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( EQ_XSTOP2_UNIT8                                         , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( EQ_XSTOP2_UNIT9                                         , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( EQ_XSTOP2_UNIT10                                        , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( EQ_XSTOP2_WAIT_CYCLES                                   , 48  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( EQ_XSTOP2_WAIT_CYCLES_LEN                               , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( EX_XSTOP2_MASK_B                                        , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASK_B     );
+REG64_FLD( EX_XSTOP2_UNUSED                                        , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EX_XSTOP2_TRIGGER_OPCG_ON                               , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( EX_XSTOP2_WAIT_ALLWAYS                                  , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( EX_XSTOP2_PERV                                          , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( EX_XSTOP2_UNIT1                                         , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( EX_XSTOP2_UNIT2                                         , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( EX_XSTOP2_UNIT3                                         , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( EX_XSTOP2_UNIT4                                         , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( EX_XSTOP2_UNIT5                                         , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( EX_XSTOP2_UNIT6                                         , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( EX_XSTOP2_UNIT7                                         , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( EX_XSTOP2_UNIT8                                         , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( EX_XSTOP2_UNIT9                                         , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( EX_XSTOP2_UNIT10                                        , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( EX_XSTOP2_WAIT_CYCLES                                   , 48  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( EX_XSTOP2_WAIT_CYCLES_LEN                               , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( C_XSTOP2_MASK_B                                         , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MASK_B     );
+REG64_FLD( C_XSTOP2_UNUSED                                         , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( C_XSTOP2_TRIGGER_OPCG_ON                                , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( C_XSTOP2_WAIT_ALLWAYS                                   , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( C_XSTOP2_PERV                                           , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( C_XSTOP2_UNIT1                                          , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( C_XSTOP2_UNIT2                                          , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( C_XSTOP2_UNIT3                                          , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( C_XSTOP2_UNIT4                                          , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( C_XSTOP2_UNIT5                                          , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( C_XSTOP2_UNIT6                                          , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( C_XSTOP2_UNIT7                                          , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( C_XSTOP2_UNIT8                                          , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( C_XSTOP2_UNIT9                                          , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( C_XSTOP2_UNIT10                                         , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( C_XSTOP2_WAIT_CYCLES                                    , 48  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( C_XSTOP2_WAIT_CYCLES_LEN                                , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( EQ_XSTOP3_MASK_B                                        , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_MASK_B     );
+REG64_FLD( EQ_XSTOP3_UNUSED                                        , 1   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EQ_XSTOP3_TRIGGER_OPCG_ON                               , 2   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( EQ_XSTOP3_WAIT_ALLWAYS                                  , 3   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( EQ_XSTOP3_PERV                                          , 4   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( EQ_XSTOP3_UNIT1                                         , 5   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( EQ_XSTOP3_UNIT2                                         , 6   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( EQ_XSTOP3_UNIT3                                         , 7   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( EQ_XSTOP3_UNIT4                                         , 8   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( EQ_XSTOP3_UNIT5                                         , 9   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( EQ_XSTOP3_UNIT6                                         , 10  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( EQ_XSTOP3_UNIT7                                         , 11  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( EQ_XSTOP3_UNIT8                                         , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( EQ_XSTOP3_UNIT9                                         , 13  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( EQ_XSTOP3_UNIT10                                        , 14  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( EQ_XSTOP3_WAIT_CYCLES                                   , 48  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( EQ_XSTOP3_WAIT_CYCLES_LEN                               , 12  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( EX_XSTOP3_MASK_B                                        , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_MASK_B     );
+REG64_FLD( EX_XSTOP3_UNUSED                                        , 1   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( EX_XSTOP3_TRIGGER_OPCG_ON                               , 2   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( EX_XSTOP3_WAIT_ALLWAYS                                  , 3   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( EX_XSTOP3_PERV                                          , 4   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( EX_XSTOP3_UNIT1                                         , 5   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( EX_XSTOP3_UNIT2                                         , 6   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( EX_XSTOP3_UNIT3                                         , 7   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( EX_XSTOP3_UNIT4                                         , 8   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( EX_XSTOP3_UNIT5                                         , 9   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( EX_XSTOP3_UNIT6                                         , 10  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( EX_XSTOP3_UNIT7                                         , 11  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( EX_XSTOP3_UNIT8                                         , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( EX_XSTOP3_UNIT9                                         , 13  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( EX_XSTOP3_UNIT10                                        , 14  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( EX_XSTOP3_WAIT_CYCLES                                   , 48  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( EX_XSTOP3_WAIT_CYCLES_LEN                               , 12  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( C_XSTOP3_MASK_B                                         , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_MASK_B     );
+REG64_FLD( C_XSTOP3_UNUSED                                         , 1   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( C_XSTOP3_TRIGGER_OPCG_ON                                , 2   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_TRIGGER_OPCG_ON );
+REG64_FLD( C_XSTOP3_WAIT_ALLWAYS                                   , 3   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_ALLWAYS );
+REG64_FLD( C_XSTOP3_PERV                                           , 4   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_PERV       );
+REG64_FLD( C_XSTOP3_UNIT1                                          , 5   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT1      );
+REG64_FLD( C_XSTOP3_UNIT2                                          , 6   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT2      );
+REG64_FLD( C_XSTOP3_UNIT3                                          , 7   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT3      );
+REG64_FLD( C_XSTOP3_UNIT4                                          , 8   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT4      );
+REG64_FLD( C_XSTOP3_UNIT5                                          , 9   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT5      );
+REG64_FLD( C_XSTOP3_UNIT6                                          , 10  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT6      );
+REG64_FLD( C_XSTOP3_UNIT7                                          , 11  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT7      );
+REG64_FLD( C_XSTOP3_UNIT8                                          , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT8      );
+REG64_FLD( C_XSTOP3_UNIT9                                          , 13  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT9      );
+REG64_FLD( C_XSTOP3_UNIT10                                         , 14  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_UNIT10     );
+REG64_FLD( C_XSTOP3_WAIT_CYCLES                                    , 48  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES );
+REG64_FLD( C_XSTOP3_WAIT_CYCLES_LEN                                , 12  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_WAIT_CYCLES_LEN );
+
+REG64_FLD( EQ_XTRA_TRACE_MODE_DATA                                 , 0   , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DATA       );
+REG64_FLD( EQ_XTRA_TRACE_MODE_DATA_LEN                             , 38  , SH_UNT_EQ       , SH_ACS_SCOM     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( EX_XTRA_TRACE_MODE_DATA                                 , 0   , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DATA       );
+REG64_FLD( EX_XTRA_TRACE_MODE_DATA_LEN                             , 38  , SH_UNT_EX       , SH_ACS_SCOM     ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( C_XTRA_TRACE_MODE_DATA                                  , 0   , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DATA       );
+REG64_FLD( C_XTRA_TRACE_MODE_DATA_LEN                              , 38  , SH_UNT_C        , SH_ACS_SCOM     ,
+           SH_FLD_DATA_LEN   );
+
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9_quad_scom_addresses_fld_fixes.H b/src/import/chips/p9/common/include/p9_quad_scom_addresses_fld_fixes.H
new file mode 100644
index 00000000..d6383558
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_quad_scom_addresses_fld_fixes.H
@@ -0,0 +1,81 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_quad_scom_addresses_fld_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file quad_scom_addresses_fld_fixes.H
+/// @brief The *scom_addresses_fld.H files are generated form figtree,
+///        but the figree can be wrong.  This file is included in
+///        *_scom_addresses_fld.H and allows incorrect constants to be
+///        fixed manually.
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SAO
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __P9_QUAD_SCOM_ADDRESSES_FLD_FIXES_H
+#define __P9_QUAD_SCOM_ADDRESSES_FLD_FIXES_H
+
+//Example
+//Copy the whole line from the *scom_addresses_fld.H file.  Then add FIX in front of REG
+//and add another paramter that is the new value you want.
+//
+//FIXREG64_FLD( PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE, 24, SH_UNT, SH_ACS_SCOM, SH_FLD_FBC_WITH_TM_QUIESCE,
+//              12);
+
+
+//L2 loader fixes
+REG64_FLD( EQ_QPPM_QACCR_L2_EX0_CLK_SYNC_ENABLE                    , 13  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L2_EX0_CLK_SYNC_ENABLE );
+
+REG64_FLD( EQ_QPPM_QACCR_L2_EX1_CLK_SYNC_ENABLE                    , 33  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L2_EX1_CLK_SYNC_ENABLE );
+
+REG64_FLD( EQ_QPPM_QACCR_L2_EX0_CLKGLM_SEL                         , 19  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L2_EX0_CLKGLM_SEL );
+
+REG64_FLD( EQ_QPPM_QACCR_L2_EX1_CLKGLM_SEL                         , 39  , SH_UNT_EQ       , SH_ACS_SCOM2    ,
+           SH_FLD_L2_EX1_CLKGLM_SEL );
+
+REG64_FLD( EQ_CPLT_CTRL1_TC_REGION1_FENCE                          , 5   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION1_FENCE );
+REG64_FLD( EQ_CPLT_CTRL1_TC_REGION2_FENCE                          , 6   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION2_FENCE );
+REG64_FLD( EQ_CPLT_CTRL1_TC_REGION3_FENCE                          , 7   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION3_FENCE );
+REG64_FLD( EQ_CPLT_CTRL1_TC_REGION4_FENCE                          , 8   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION4_FENCE );
+REG64_FLD( EQ_CPLT_CTRL1_TC_REGION5_FENCE                          , 9   , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION5_FENCE );
+REG64_FLD( EQ_CPLT_CTRL1_TC_REGION6_FENCE                          , 10  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION6_FENCE );
+REG64_FLD( EQ_CPLT_CTRL1_TC_REGION7_FENCE                          , 11  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION7_FENCE );
+REG64_FLD( EQ_CPLT_CTRL1_TC_REGION8_FENCE                          , 12  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION8_FENCE );
+REG64_FLD( EQ_CPLT_CTRL1_TC_REGION9_FENCE                          , 13  , SH_UNT_EQ       , SH_ACS_SCOM2_CLEAR,
+           SH_FLD_TC_REGION9_FENCE );
+
+#endif
diff --git a/src/import/chips/p9/common/include/p9_scom_template_consts.H b/src/import/chips/p9/common/include/p9_scom_template_consts.H
new file mode 100644
index 00000000..e4e8e654
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_scom_template_consts.H
@@ -0,0 +1,19569 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_scom_template_consts.H $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file scom_template_consts.H
+/// @brief  File generated to contain constants used to define templates
+///         for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+#ifndef __P9_SCOM_TEMPLATE_CONSTS_H
+#define __P9_SCOM_TEMPLATE_CONSTS_H
+
+static const uint64_t SH_UNT = 0;
+static const uint64_t SH_UNT_C = 1;
+static const uint64_t SH_UNT_CAPP = 2;
+static const uint64_t SH_UNT_CAPP_0 = 3;
+static const uint64_t SH_UNT_CAPP_1 = 4;
+static const uint64_t SH_UNT_C_0 = 5;
+static const uint64_t SH_UNT_C_1 = 6;
+static const uint64_t SH_UNT_C_10 = 7;
+static const uint64_t SH_UNT_C_11 = 8;
+static const uint64_t SH_UNT_C_12 = 9;
+static const uint64_t SH_UNT_C_13 = 10;
+static const uint64_t SH_UNT_C_14 = 11;
+static const uint64_t SH_UNT_C_15 = 12;
+static const uint64_t SH_UNT_C_16 = 13;
+static const uint64_t SH_UNT_C_17 = 14;
+static const uint64_t SH_UNT_C_18 = 15;
+static const uint64_t SH_UNT_C_19 = 16;
+static const uint64_t SH_UNT_C_2 = 17;
+static const uint64_t SH_UNT_C_20 = 18;
+static const uint64_t SH_UNT_C_21 = 19;
+static const uint64_t SH_UNT_C_22 = 20;
+static const uint64_t SH_UNT_C_23 = 21;
+static const uint64_t SH_UNT_C_3 = 22;
+static const uint64_t SH_UNT_C_4 = 23;
+static const uint64_t SH_UNT_C_5 = 24;
+static const uint64_t SH_UNT_C_6 = 25;
+static const uint64_t SH_UNT_C_7 = 26;
+static const uint64_t SH_UNT_C_8 = 27;
+static const uint64_t SH_UNT_C_9 = 28;
+static const uint64_t SH_UNT_EQ = 29;
+static const uint64_t SH_UNT_EQ_0 = 30;
+static const uint64_t SH_UNT_EQ_1 = 31;
+static const uint64_t SH_UNT_EQ_2 = 32;
+static const uint64_t SH_UNT_EQ_3 = 33;
+static const uint64_t SH_UNT_EQ_4 = 34;
+static const uint64_t SH_UNT_EQ_5 = 35;
+static const uint64_t SH_UNT_EX = 36;
+static const uint64_t SH_UNT_EX_0 = 37;
+static const uint64_t SH_UNT_EX_0_L2 = 38;
+static const uint64_t SH_UNT_EX_0_L3 = 39;
+static const uint64_t SH_UNT_EX_1 = 40;
+static const uint64_t SH_UNT_EX_10 = 41;
+static const uint64_t SH_UNT_EX_10_L2 = 42;
+static const uint64_t SH_UNT_EX_10_L3 = 43;
+static const uint64_t SH_UNT_EX_11 = 44;
+static const uint64_t SH_UNT_EX_11_CHTMLBS0 = 45;
+static const uint64_t SH_UNT_EX_11_CHTMLBS1 = 46;
+static const uint64_t SH_UNT_EX_11_L2 = 47;
+static const uint64_t SH_UNT_EX_11_L3 = 48;
+static const uint64_t SH_UNT_EX_1_CHTMLBS0 = 49;
+static const uint64_t SH_UNT_EX_1_CHTMLBS1 = 50;
+static const uint64_t SH_UNT_EX_1_L2 = 51;
+static const uint64_t SH_UNT_EX_1_L3 = 52;
+static const uint64_t SH_UNT_EX_2 = 53;
+static const uint64_t SH_UNT_EX_2_L2 = 54;
+static const uint64_t SH_UNT_EX_2_L3 = 55;
+static const uint64_t SH_UNT_EX_3 = 56;
+static const uint64_t SH_UNT_EX_3_CHTMLBS0 = 57;
+static const uint64_t SH_UNT_EX_3_CHTMLBS1 = 58;
+static const uint64_t SH_UNT_EX_3_L2 = 59;
+static const uint64_t SH_UNT_EX_3_L3 = 60;
+static const uint64_t SH_UNT_EX_4 = 61;
+static const uint64_t SH_UNT_EX_4_L2 = 62;
+static const uint64_t SH_UNT_EX_4_L3 = 63;
+static const uint64_t SH_UNT_EX_5 = 64;
+static const uint64_t SH_UNT_EX_5_CHTMLBS0 = 65;
+static const uint64_t SH_UNT_EX_5_CHTMLBS1 = 66;
+static const uint64_t SH_UNT_EX_5_L2 = 67;
+static const uint64_t SH_UNT_EX_5_L3 = 68;
+static const uint64_t SH_UNT_EX_6 = 69;
+static const uint64_t SH_UNT_EX_6_L2 = 70;
+static const uint64_t SH_UNT_EX_6_L3 = 71;
+static const uint64_t SH_UNT_EX_7 = 72;
+static const uint64_t SH_UNT_EX_7_CHTMLBS0 = 73;
+static const uint64_t SH_UNT_EX_7_CHTMLBS1 = 74;
+static const uint64_t SH_UNT_EX_7_L2 = 75;
+static const uint64_t SH_UNT_EX_7_L3 = 76;
+static const uint64_t SH_UNT_EX_8 = 77;
+static const uint64_t SH_UNT_EX_8_L2 = 78;
+static const uint64_t SH_UNT_EX_8_L3 = 79;
+static const uint64_t SH_UNT_EX_9 = 80;
+static const uint64_t SH_UNT_EX_9_CHTMLBS0 = 81;
+static const uint64_t SH_UNT_EX_9_CHTMLBS1 = 82;
+static const uint64_t SH_UNT_EX_9_L2 = 83;
+static const uint64_t SH_UNT_EX_9_L3 = 84;
+static const uint64_t SH_UNT_EX_L2 = 85;
+static const uint64_t SH_UNT_EX_L3 = 86;
+static const uint64_t SH_UNT_MCA = 87;
+static const uint64_t SH_UNT_MCA_0 = 88;
+static const uint64_t SH_UNT_MCA_0_WDF = 89;
+static const uint64_t SH_UNT_MCA_0_WREITE = 90;
+static const uint64_t SH_UNT_MCA_1 = 91;
+static const uint64_t SH_UNT_MCA_1_WDF = 92;
+static const uint64_t SH_UNT_MCA_1_WREITE = 93;
+static const uint64_t SH_UNT_MCA_2 = 94;
+static const uint64_t SH_UNT_MCA_2_WDF = 95;
+static const uint64_t SH_UNT_MCA_2_WREITE = 96;
+static const uint64_t SH_UNT_MCA_3 = 97;
+static const uint64_t SH_UNT_MCA_3_WDF = 98;
+static const uint64_t SH_UNT_MCA_3_WREITE = 99;
+static const uint64_t SH_UNT_MCA_4 = 100;
+static const uint64_t SH_UNT_MCA_4_WDF = 101;
+static const uint64_t SH_UNT_MCA_4_WREITE = 102;
+static const uint64_t SH_UNT_MCA_5 = 103;
+static const uint64_t SH_UNT_MCA_5_WDF = 104;
+static const uint64_t SH_UNT_MCA_5_WREITE = 105;
+static const uint64_t SH_UNT_MCA_6 = 106;
+static const uint64_t SH_UNT_MCA_6_WDF = 107;
+static const uint64_t SH_UNT_MCA_6_WREITE = 108;
+static const uint64_t SH_UNT_MCA_7 = 109;
+static const uint64_t SH_UNT_MCA_7_WDF = 110;
+static const uint64_t SH_UNT_MCA_7_WREITE = 111;
+static const uint64_t SH_UNT_MCA_WDF = 112;
+static const uint64_t SH_UNT_MCA_WREITE = 113;
+static const uint64_t SH_UNT_MCBIST = 114;
+static const uint64_t SH_UNT_MCBIST_0 = 115;
+static const uint64_t SH_UNT_MCBIST_1 = 116;
+static const uint64_t SH_UNT_MCS = 117;
+static const uint64_t SH_UNT_MCS_0 = 118;
+static const uint64_t SH_UNT_MCS_0_PORT02 = 119;
+static const uint64_t SH_UNT_MCS_0_PORT13 = 120;
+static const uint64_t SH_UNT_MCS_1 = 121;
+static const uint64_t SH_UNT_MCS_1_PORT02 = 122;
+static const uint64_t SH_UNT_MCS_1_PORT13 = 123;
+static const uint64_t SH_UNT_MCS_2 = 124;
+static const uint64_t SH_UNT_MCS_2_PORT02 = 125;
+static const uint64_t SH_UNT_MCS_2_PORT13 = 126;
+static const uint64_t SH_UNT_MCS_3 = 127;
+static const uint64_t SH_UNT_MCS_3_PORT02 = 128;
+static const uint64_t SH_UNT_MCS_3_PORT13 = 129;
+static const uint64_t SH_UNT_MCS_PORT02 = 130;
+static const uint64_t SH_UNT_MCS_PORT13 = 131;
+static const uint64_t SH_UNT_NV = 132;
+static const uint64_t SH_UNT_NV_0 = 133;
+static const uint64_t SH_UNT_NV_1 = 134;
+static const uint64_t SH_UNT_NV_2 = 135;
+static const uint64_t SH_UNT_NV_3 = 136;
+static const uint64_t SH_UNT_OBUS = 137;
+static const uint64_t SH_UNT_OBUS_0 = 138;
+static const uint64_t SH_UNT_OBUS_3 = 139;
+static const uint64_t SH_UNT_PEC = 140;
+static const uint64_t SH_UNT_PEC_0 = 141;
+static const uint64_t SH_UNT_PEC_0_STACK0 = 142;
+static const uint64_t SH_UNT_PEC_0_STACK1 = 143;
+static const uint64_t SH_UNT_PEC_0_STACK2 = 144;
+static const uint64_t SH_UNT_PEC_1 = 145;
+static const uint64_t SH_UNT_PEC_1_STACK0 = 146;
+static const uint64_t SH_UNT_PEC_1_STACK1 = 147;
+static const uint64_t SH_UNT_PEC_1_STACK2 = 148;
+static const uint64_t SH_UNT_PEC_2 = 149;
+static const uint64_t SH_UNT_PEC_2_STACK0 = 150;
+static const uint64_t SH_UNT_PEC_2_STACK1 = 151;
+static const uint64_t SH_UNT_PEC_2_STACK2 = 152;
+static const uint64_t SH_UNT_PEC_STACK0 = 153;
+static const uint64_t SH_UNT_PEC_STACK1 = 154;
+static const uint64_t SH_UNT_PEC_STACK2 = 155;
+static const uint64_t SH_UNT_PERV = 156;
+static const uint64_t SH_UNT_PERV_0 = 157;
+static const uint64_t SH_UNT_PERV_0_FSII2C = 158;
+static const uint64_t SH_UNT_PERV_0_PIB2OPB0 = 159;
+static const uint64_t SH_UNT_PERV_0_PIB2OPB1 = 160;
+static const uint64_t SH_UNT_PERV_1 = 161;
+static const uint64_t SH_UNT_PERV_12 = 162;
+static const uint64_t SH_UNT_PERV_13 = 163;
+static const uint64_t SH_UNT_PERV_14 = 164;
+static const uint64_t SH_UNT_PERV_15 = 165;
+static const uint64_t SH_UNT_PERV_16 = 166;
+static const uint64_t SH_UNT_PERV_17 = 167;
+static const uint64_t SH_UNT_PERV_18 = 168;
+static const uint64_t SH_UNT_PERV_19 = 169;
+static const uint64_t SH_UNT_PERV_2 = 170;
+static const uint64_t SH_UNT_PERV_20 = 171;
+static const uint64_t SH_UNT_PERV_21 = 172;
+static const uint64_t SH_UNT_PERV_3 = 173;
+static const uint64_t SH_UNT_PERV_32 = 174;
+static const uint64_t SH_UNT_PERV_33 = 175;
+static const uint64_t SH_UNT_PERV_34 = 176;
+static const uint64_t SH_UNT_PERV_35 = 177;
+static const uint64_t SH_UNT_PERV_36 = 178;
+static const uint64_t SH_UNT_PERV_37 = 179;
+static const uint64_t SH_UNT_PERV_38 = 180;
+static const uint64_t SH_UNT_PERV_39 = 181;
+static const uint64_t SH_UNT_PERV_4 = 182;
+static const uint64_t SH_UNT_PERV_40 = 183;
+static const uint64_t SH_UNT_PERV_41 = 184;
+static const uint64_t SH_UNT_PERV_42 = 185;
+static const uint64_t SH_UNT_PERV_43 = 186;
+static const uint64_t SH_UNT_PERV_44 = 187;
+static const uint64_t SH_UNT_PERV_45 = 188;
+static const uint64_t SH_UNT_PERV_46 = 189;
+static const uint64_t SH_UNT_PERV_47 = 190;
+static const uint64_t SH_UNT_PERV_48 = 191;
+static const uint64_t SH_UNT_PERV_49 = 192;
+static const uint64_t SH_UNT_PERV_5 = 193;
+static const uint64_t SH_UNT_PERV_50 = 194;
+static const uint64_t SH_UNT_PERV_51 = 195;
+static const uint64_t SH_UNT_PERV_52 = 196;
+static const uint64_t SH_UNT_PERV_53 = 197;
+static const uint64_t SH_UNT_PERV_54 = 198;
+static const uint64_t SH_UNT_PERV_55 = 199;
+static const uint64_t SH_UNT_PERV_6 = 200;
+static const uint64_t SH_UNT_PERV_7 = 201;
+static const uint64_t SH_UNT_PERV_8 = 202;
+static const uint64_t SH_UNT_PERV_9 = 203;
+static const uint64_t SH_UNT_PERV_FSB = 204;
+static const uint64_t SH_UNT_PERV_FSI2PIB = 205;
+static const uint64_t SH_UNT_PERV_FSII2C = 206;
+static const uint64_t SH_UNT_PERV_FSISHIFT = 207;
+static const uint64_t SH_UNT_PERV_PIB2OPB0 = 208;
+static const uint64_t SH_UNT_PERV_PIB2OPB1 = 209;
+static const uint64_t SH_UNT_PHB = 210;
+static const uint64_t SH_UNT_PHB_0 = 211;
+static const uint64_t SH_UNT_PHB_1 = 212;
+static const uint64_t SH_UNT_PHB_2 = 213;
+static const uint64_t SH_UNT_PHB_3 = 214;
+static const uint64_t SH_UNT_PHB_4 = 215;
+static const uint64_t SH_UNT_PHB_5 = 216;
+static const uint64_t SH_UNT_PU_CME0 = 217;
+static const uint64_t SH_UNT_PU_CME1 = 218;
+static const uint64_t SH_UNT_PU_CME10 = 219;
+static const uint64_t SH_UNT_PU_CME11 = 220;
+static const uint64_t SH_UNT_PU_CME2 = 221;
+static const uint64_t SH_UNT_PU_CME3 = 222;
+static const uint64_t SH_UNT_PU_CME4 = 223;
+static const uint64_t SH_UNT_PU_CME5 = 224;
+static const uint64_t SH_UNT_PU_CME6 = 225;
+static const uint64_t SH_UNT_PU_CME7 = 226;
+static const uint64_t SH_UNT_PU_CME8 = 227;
+static const uint64_t SH_UNT_PU_CME9 = 228;
+static const uint64_t SH_UNT_PU_HTM0 = 229;
+static const uint64_t SH_UNT_PU_HTM1 = 230;
+static const uint64_t SH_UNT_PU_IOE = 231;
+static const uint64_t SH_UNT_PU_MCD1 = 232;
+static const uint64_t SH_UNT_PU_N0 = 233;
+static const uint64_t SH_UNT_PU_N1 = 234;
+static const uint64_t SH_UNT_PU_N2 = 235;
+static const uint64_t SH_UNT_PU_N3 = 236;
+static const uint64_t SH_UNT_PU_NMMU = 237;
+static const uint64_t SH_UNT_PU_NPU = 238;
+static const uint64_t SH_UNT_PU_NPU0 = 239;
+static const uint64_t SH_UNT_PU_NPU0_CTL = 240;
+static const uint64_t SH_UNT_PU_NPU0_DAT = 241;
+static const uint64_t SH_UNT_PU_NPU0_SM0 = 242;
+static const uint64_t SH_UNT_PU_NPU0_SM1 = 243;
+static const uint64_t SH_UNT_PU_NPU0_SM2 = 244;
+static const uint64_t SH_UNT_PU_NPU0_SM3 = 245;
+static const uint64_t SH_UNT_PU_NPU1 = 246;
+static const uint64_t SH_UNT_PU_NPU1_CTL = 247;
+static const uint64_t SH_UNT_PU_NPU1_DAT = 248;
+static const uint64_t SH_UNT_PU_NPU1_SM0 = 249;
+static const uint64_t SH_UNT_PU_NPU1_SM1 = 250;
+static const uint64_t SH_UNT_PU_NPU1_SM2 = 251;
+static const uint64_t SH_UNT_PU_NPU1_SM3 = 252;
+static const uint64_t SH_UNT_PU_NPU2 = 253;
+static const uint64_t SH_UNT_PU_NPU2_CTL = 254;
+static const uint64_t SH_UNT_PU_NPU2_DAT = 255;
+static const uint64_t SH_UNT_PU_NPU2_NTL0 = 256;
+static const uint64_t SH_UNT_PU_NPU2_NTL1 = 257;
+static const uint64_t SH_UNT_PU_NPU2_SM0 = 258;
+static const uint64_t SH_UNT_PU_NPU2_SM1 = 259;
+static const uint64_t SH_UNT_PU_NPU2_SM2 = 260;
+static const uint64_t SH_UNT_PU_NPU2_SM3 = 261;
+static const uint64_t SH_UNT_PU_NPU_CTL = 262;
+static const uint64_t SH_UNT_PU_NPU_DAT = 263;
+static const uint64_t SH_UNT_PU_NPU_MSC_SM0 = 264;
+static const uint64_t SH_UNT_PU_NPU_MSC_SM2 = 265;
+static const uint64_t SH_UNT_PU_NPU_NTL0 = 266;
+static const uint64_t SH_UNT_PU_NPU_NTL1 = 267;
+static const uint64_t SH_UNT_PU_NPU_SM0 = 268;
+static const uint64_t SH_UNT_PU_NPU_SM1 = 269;
+static const uint64_t SH_UNT_PU_NPU_SM2 = 270;
+static const uint64_t SH_UNT_PU_NPU_SM3 = 271;
+static const uint64_t SH_UNT_PU_OTPROM0 = 272;
+static const uint64_t SH_UNT_PU_OTPROM1 = 273;
+static const uint64_t SH_UNT_PU_PBAIB_STACK1 = 274;
+static const uint64_t SH_UNT_PU_PBAIB_STACK2 = 275;
+static const uint64_t SH_UNT_PU_PBAIB_STACK5 = 276;
+static const uint64_t SH_UNT_PU_PB_CENT_SM0 = 277;
+static const uint64_t SH_UNT_PU_PB_CENT_SM1 = 278;
+static const uint64_t SH_UNT_PU_PB_WEST_SM0 = 279;
+static const uint64_t SH_UNT_XBUS = 280;
+static const uint64_t SH_UNT_XBUS_0 = 281;
+static const uint64_t SH_UNT_XBUS_1 = 282;
+static const uint64_t SH_UNT_XBUS_2 = 283;
+static const uint64_t SH_UNT_XBUS_IOPPE = 284;
+static const uint64_t SH_UNT_XBUS_PERV = 285;
+
+
+static const uint64_t SH_ACS_FSI = 0;
+static const uint64_t SH_ACS_FSI0 = 1;
+static const uint64_t SH_ACS_FSI1 = 2;
+static const uint64_t SH_ACS_FSI_BYTE = 3;
+static const uint64_t SH_ACS_IODA = 4;
+static const uint64_t SH_ACS_OCI = 5;
+static const uint64_t SH_ACS_OCI1 = 6;
+static const uint64_t SH_ACS_OCI2 = 7;
+static const uint64_t SH_ACS_PIB = 8;
+static const uint64_t SH_ACS_PPE = 9;
+static const uint64_t SH_ACS_PPE1 = 10;
+static const uint64_t SH_ACS_PPE2 = 11;
+static const uint64_t SH_ACS_SCOM = 12;
+static const uint64_t SH_ACS_SCOM1 = 13;
+static const uint64_t SH_ACS_SCOM1_AND = 14;
+static const uint64_t SH_ACS_SCOM1_CLEAR = 15;
+static const uint64_t SH_ACS_SCOM1_NC = 16;
+static const uint64_t SH_ACS_SCOM1_OR = 17;
+static const uint64_t SH_ACS_SCOM1_RO = 18;
+static const uint64_t SH_ACS_SCOM1_WAND = 19;
+static const uint64_t SH_ACS_SCOM1_WO = 20;
+static const uint64_t SH_ACS_SCOM1_WOR = 21;
+static const uint64_t SH_ACS_SCOM2 = 22;
+static const uint64_t SH_ACS_SCOM2_AND = 23;
+static const uint64_t SH_ACS_SCOM2_CLEAR = 24;
+static const uint64_t SH_ACS_SCOM2_NC = 25;
+static const uint64_t SH_ACS_SCOM2_OR = 26;
+static const uint64_t SH_ACS_SCOM2_WAND = 27;
+static const uint64_t SH_ACS_SCOM2_WOR = 28;
+static const uint64_t SH_ACS_SCOM3 = 29;
+static const uint64_t SH_ACS_SCOM3_RW = 30;
+static const uint64_t SH_ACS_SCOMFSI0 = 31;
+static const uint64_t SH_ACS_SCOMFSI0_CLEAR = 32;
+static const uint64_t SH_ACS_SCOMFSI0_OR = 33;
+static const uint64_t SH_ACS_SCOMFSI0_RO = 34;
+static const uint64_t SH_ACS_SCOMFSI0_RW = 35;
+static const uint64_t SH_ACS_SCOMFSI1 = 36;
+static const uint64_t SH_ACS_SCOMFSI1_CLEAR = 37;
+static const uint64_t SH_ACS_SCOMFSI1_OR = 38;
+static const uint64_t SH_ACS_SCOMFSI1_RO = 39;
+static const uint64_t SH_ACS_SCOMFSI1_RW = 40;
+static const uint64_t SH_ACS_SCOM_4P = 41;
+static const uint64_t SH_ACS_SCOM_CLRPART = 42;
+static const uint64_t SH_ACS_SCOM_NC = 43;
+static const uint64_t SH_ACS_SCOM_RCLRPART = 44;
+static const uint64_t SH_ACS_SCOM_RO = 45;
+static const uint64_t SH_ACS_SCOM_RW = 46;
+static const uint64_t SH_ACS_SCOM_W = 47;
+static const uint64_t SH_ACS_SCOM_WAND = 48;
+static const uint64_t SH_ACS_SCOM_WCLEAR = 49;
+static const uint64_t SH_ACS_SCOM_WCLRPART = 50;
+static const uint64_t SH_ACS_SCOM_WCLRREG = 51;
+static const uint64_t SH_ACS_SCOM_WO = 52;
+static const uint64_t SH_ACS_SCOM_WOR = 53;
+
+
+
+static const uint64_t SH_FLD_0 = 0; // 482
+static const uint64_t SH_FLD_01 = 1; // 128
+static const uint64_t SH_FLD_01_0_11 = 2; // 16
+static const uint64_t SH_FLD_01_0_11_LEN = 3; // 16
+static const uint64_t SH_FLD_01_12_15 = 4; // 16
+static const uint64_t SH_FLD_01_12_15_LEN = 5; // 16
+static const uint64_t SH_FLD_01_1D_EYE_NOISE = 6; // 16
+static const uint64_t SH_FLD_01_1D_EYE_NOISE_ERR0 = 7; // 16
+static const uint64_t SH_FLD_01_1D_EYE_NOISE_ERR1 = 8; // 16
+static const uint64_t SH_FLD_01_1D_EYE_NOISE_ERR2 = 9; // 16
+static const uint64_t SH_FLD_01_1D_EYE_NOISE_ERR3 = 10; // 16
+static const uint64_t SH_FLD_01_1D_EYE_NOISE_MASK1 = 11; // 16
+static const uint64_t SH_FLD_01_1D_EYE_NOISE_MASK2 = 12; // 16
+static const uint64_t SH_FLD_01_1D_EYE_NOISE_MASK3 = 13; // 16
+static const uint64_t SH_FLD_01_ADVANCE_PING_PONG = 14; // 16
+static const uint64_t SH_FLD_01_ADVANCE_PR_VALUE = 15; // 16
+static const uint64_t SH_FLD_01_ATESTSEL_0_4 = 16; // 8
+static const uint64_t SH_FLD_01_ATESTSEL_0_4_LEN = 17; // 8
+static const uint64_t SH_FLD_01_ATESTSEL_4 = 18; // 8
+static const uint64_t SH_FLD_01_ATESTSEL_4_LEN = 19; // 8
+static const uint64_t SH_FLD_01_ATEST_SEL_0 = 20; // 8
+static const uint64_t SH_FLD_01_ATEST_SEL_0_LEN = 21; // 8
+static const uint64_t SH_FLD_01_ATEST_SEL_1 = 22; // 8
+static const uint64_t SH_FLD_01_ATEST_SEL_1_LEN = 23; // 8
+static const uint64_t SH_FLD_01_BAD_BIT = 24; // 16
+static const uint64_t SH_FLD_01_BAD_BIT_ERR0 = 25; // 16
+static const uint64_t SH_FLD_01_BAD_BIT_ERR1 = 26; // 16
+static const uint64_t SH_FLD_01_BAD_BIT_ERR2 = 27; // 16
+static const uint64_t SH_FLD_01_BAD_BIT_ERR3 = 28; // 16
+static const uint64_t SH_FLD_01_BAD_BIT_MASK1 = 29; // 16
+static const uint64_t SH_FLD_01_BAD_BIT_MASK2 = 30; // 16
+static const uint64_t SH_FLD_01_BAD_BIT_MASK3 = 31; // 16
+static const uint64_t SH_FLD_01_BB_LOCK0 = 32; // 16
+static const uint64_t SH_FLD_01_BB_LOCK1 = 33; // 16
+static const uint64_t SH_FLD_01_BIG_STEP_RIGHT = 34; // 16
+static const uint64_t SH_FLD_01_BIT_CENTERED = 35; // 16
+static const uint64_t SH_FLD_01_BIT_CENTERED_LEN = 36; // 16
+static const uint64_t SH_FLD_01_BIT_STEP_DELTA = 37; // 16
+static const uint64_t SH_FLD_01_BIT_STEP_DELTA_ERR0 = 38; // 16
+static const uint64_t SH_FLD_01_BIT_STEP_DELTA_ERR1 = 39; // 16
+static const uint64_t SH_FLD_01_BIT_STEP_DELTA_ERR2 = 40; // 16
+static const uint64_t SH_FLD_01_BIT_STEP_DELTA_ERR3 = 41; // 16
+static const uint64_t SH_FLD_01_BIT_STEP_DELTA_MASK1 = 42; // 16
+static const uint64_t SH_FLD_01_BIT_STEP_DELTA_MASK2 = 43; // 16
+static const uint64_t SH_FLD_01_BIT_STEP_DELTA_MASK3 = 44; // 16
+static const uint64_t SH_FLD_01_BLFIFO_DIS = 45; // 16
+static const uint64_t SH_FLD_01_BUMP = 46; // 16
+static const uint64_t SH_FLD_01_CALGATE_ON = 47; // 16
+static const uint64_t SH_FLD_01_CALIBRATE_BIT = 48; // 16
+static const uint64_t SH_FLD_01_CALIBRATE_BIT_LEN = 49; // 16
+static const uint64_t SH_FLD_01_CAL_CKTS_ACTIVE = 50; // 32
+static const uint64_t SH_FLD_01_CAL_ERROR = 51; // 32
+static const uint64_t SH_FLD_01_CAL_ERROR_FINE = 52; // 32
+static const uint64_t SH_FLD_01_CAL_GOOD = 53; // 32
+static const uint64_t SH_FLD_01_CAL_PD_ENABLE = 54; // 32
+static const uint64_t SH_FLD_01_CHECKER_ENABLE = 55; // 16
+static const uint64_t SH_FLD_01_CHECKER_RESET = 56; // 16
+static const uint64_t SH_FLD_01_CHICKSW_HW278227 = 57; // 16
+static const uint64_t SH_FLD_01_CLK16_SINGLE_ENDED = 58; // 64
+static const uint64_t SH_FLD_01_CLK18_SINGLE_ENDED = 59; // 64
+static const uint64_t SH_FLD_01_CLK20_SINGLE_ENDED = 60; // 64
+static const uint64_t SH_FLD_01_CLK22_SINGLE_ENDED = 61; // 64
+static const uint64_t SH_FLD_01_CLK_LEVEL = 62; // 16
+static const uint64_t SH_FLD_01_CLK_LEVEL_LEN = 63; // 16
+static const uint64_t SH_FLD_01_CNTL_POL = 64; // 16
+static const uint64_t SH_FLD_01_CNTL_SRC = 65; // 16
+static const uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N0 = 66; // 16
+static const uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N0_MASK = 67; // 16
+static const uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N1 = 68; // 16
+static const uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N1_MASK = 69; // 16
+static const uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N2 = 70; // 16
+static const uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N2_MASK = 71; // 16
+static const uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N3 = 72; // 16
+static const uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N3_MASK = 73; // 16
+static const uint64_t SH_FLD_01_CONTINUOUS_UPDATE = 74; // 32
+static const uint64_t SH_FLD_01_CTR_1D_CHICKEN_SWITCH = 75; // 16
+static const uint64_t SH_FLD_01_CTR_2D_BIG_STEP_VAL = 76; // 16
+static const uint64_t SH_FLD_01_CTR_2D_BIG_STEP_VAL_LEN = 77; // 16
+static const uint64_t SH_FLD_01_CTR_2D_SMALL_STEP_VAL = 78; // 16
+static const uint64_t SH_FLD_01_CTR_2D_SMALL_STEP_VAL_LEN = 79; // 16
+static const uint64_t SH_FLD_01_CTR_CUR = 80; // 16
+static const uint64_t SH_FLD_01_CTR_CUR_LEN = 81; // 16
+static const uint64_t SH_FLD_01_CTR_NUM_BITS_TO_SKIP = 82; // 16
+static const uint64_t SH_FLD_01_CTR_NUM_BITS_TO_SKIP_LEN = 83; // 16
+static const uint64_t SH_FLD_01_CTR_NUM_NO_INC_COMP = 84; // 16
+static const uint64_t SH_FLD_01_CTR_NUM_NO_INC_COMP_LEN = 85; // 16
+static const uint64_t SH_FLD_01_CTR_NUM_VREFREQ_CNT = 86; // 16
+static const uint64_t SH_FLD_01_CTR_NUM_VREFREQ_CNT_LEN = 87; // 16
+static const uint64_t SH_FLD_01_CTR_NUM_WRRDREQ_CNT = 88; // 16
+static const uint64_t SH_FLD_01_CTR_NUM_WRRDREQ_CNT_LEN = 89; // 16
+static const uint64_t SH_FLD_01_CTR_RANGE_CROSSOVER = 90; // 16
+static const uint64_t SH_FLD_01_CTR_RANGE_CROSSOVER_LEN = 91; // 16
+static const uint64_t SH_FLD_01_CTR_RANGE_SELECT = 92; // 16
+static const uint64_t SH_FLD_01_CTR_RUN_FULL_1D = 93; // 16
+static const uint64_t SH_FLD_01_CTR_SINGLE_RANGE_MAX = 94; // 16
+static const uint64_t SH_FLD_01_CTR_SINGLE_RANGE_MAX_LEN = 95; // 16
+static const uint64_t SH_FLD_01_DD2_DQS_FIX_DIS = 96; // 16
+static const uint64_t SH_FLD_01_DD2_FIX_DIS = 97; // 16
+static const uint64_t SH_FLD_01_DD2_WTRFL_SYNC_DIS = 98; // 16
+static const uint64_t SH_FLD_01_DELAY1 = 99; // 16
+static const uint64_t SH_FLD_01_DELAY10 = 100; // 16
+static const uint64_t SH_FLD_01_DELAY10_LEN = 101; // 16
+static const uint64_t SH_FLD_01_DELAY11 = 102; // 16
+static const uint64_t SH_FLD_01_DELAY11_LEN = 103; // 16
+static const uint64_t SH_FLD_01_DELAY12 = 104; // 16
+static const uint64_t SH_FLD_01_DELAY12_LEN = 105; // 16
+static const uint64_t SH_FLD_01_DELAY13 = 106; // 16
+static const uint64_t SH_FLD_01_DELAY13_LEN = 107; // 16
+static const uint64_t SH_FLD_01_DELAY14 = 108; // 16
+static const uint64_t SH_FLD_01_DELAY14_LEN = 109; // 16
+static const uint64_t SH_FLD_01_DELAY15 = 110; // 16
+static const uint64_t SH_FLD_01_DELAY15_LEN = 111; // 16
+static const uint64_t SH_FLD_01_DELAY1_LEN = 112; // 16
+static const uint64_t SH_FLD_01_DELAY2 = 113; // 16
+static const uint64_t SH_FLD_01_DELAY2_LEN = 114; // 16
+static const uint64_t SH_FLD_01_DELAY3 = 115; // 16
+static const uint64_t SH_FLD_01_DELAY3_LEN = 116; // 16
+static const uint64_t SH_FLD_01_DELAY4 = 117; // 16
+static const uint64_t SH_FLD_01_DELAY4_LEN = 118; // 16
+static const uint64_t SH_FLD_01_DELAY5 = 119; // 16
+static const uint64_t SH_FLD_01_DELAY5_LEN = 120; // 16
+static const uint64_t SH_FLD_01_DELAY6 = 121; // 16
+static const uint64_t SH_FLD_01_DELAY6_LEN = 122; // 16
+static const uint64_t SH_FLD_01_DELAY7 = 123; // 16
+static const uint64_t SH_FLD_01_DELAY7_LEN = 124; // 16
+static const uint64_t SH_FLD_01_DELAY8 = 125; // 16
+static const uint64_t SH_FLD_01_DELAY8_LEN = 126; // 16
+static const uint64_t SH_FLD_01_DELAY9 = 127; // 16
+static const uint64_t SH_FLD_01_DELAY9_LEN = 128; // 16
+static const uint64_t SH_FLD_01_DELAYG = 129; // 1280
+static const uint64_t SH_FLD_01_DELAYG_LEN = 130; // 1280
+static const uint64_t SH_FLD_01_DELAY_PING_PONG_HALF = 131; // 16
+static const uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH = 132; // 16
+static const uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 133; // 16
+static const uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW = 134; // 16
+static const uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 135; // 16
+static const uint64_t SH_FLD_01_DETECT_REQ = 136; // 32
+static const uint64_t SH_FLD_01_DFT_FORCE_OUTPUTS = 137; // 16
+static const uint64_t SH_FLD_01_DFT_PRBS7_GEN_EN = 138; // 16
+static const uint64_t SH_FLD_01_DIGITAL_EN = 139; // 16
+static const uint64_t SH_FLD_01_DIR_0_15 = 140; // 8
+static const uint64_t SH_FLD_01_DIR_0_15_LEN = 141; // 8
+static const uint64_t SH_FLD_01_DIR_15 = 142; // 8
+static const uint64_t SH_FLD_01_DIR_15_LEN = 143; // 8
+static const uint64_t SH_FLD_01_DISABLE_0_15 = 144; // 32
+static const uint64_t SH_FLD_01_DISABLE_0_15_LEN = 145; // 32
+static const uint64_t SH_FLD_01_DISABLE_15 = 146; // 32
+static const uint64_t SH_FLD_01_DISABLE_15_LEN = 147; // 32
+static const uint64_t SH_FLD_01_DISABLE_16_23 = 148; // 64
+static const uint64_t SH_FLD_01_DISABLE_16_23_LEN = 149; // 64
+static const uint64_t SH_FLD_01_DISABLE_PING_PONG = 150; // 16
+static const uint64_t SH_FLD_01_DISABLE_TERMINATION = 151; // 16
+static const uint64_t SH_FLD_01_DIS_CLK_GATE = 152; // 16
+static const uint64_t SH_FLD_01_DI_ADR0 = 153; // 8
+static const uint64_t SH_FLD_01_DI_ADR1 = 154; // 8
+static const uint64_t SH_FLD_01_DI_ADR10_ADR11 = 155; // 16
+static const uint64_t SH_FLD_01_DI_ADR12_ADR13 = 156; // 16
+static const uint64_t SH_FLD_01_DI_ADR14_ADR15 = 157; // 16
+static const uint64_t SH_FLD_01_DI_ADR2_ADR3 = 158; // 16
+static const uint64_t SH_FLD_01_DI_ADR4_ADR5 = 159; // 16
+static const uint64_t SH_FLD_01_DI_ADR6_ADR7 = 160; // 16
+static const uint64_t SH_FLD_01_DI_ADR8_ADR9 = 161; // 16
+static const uint64_t SH_FLD_01_DLL_ADJUST = 162; // 32
+static const uint64_t SH_FLD_01_DLL_ADJUST_LEN = 163; // 32
+static const uint64_t SH_FLD_01_DLL_COMPARE_OUT = 164; // 32
+static const uint64_t SH_FLD_01_DLL_CORRECT_EN = 165; // 32
+static const uint64_t SH_FLD_01_DLL_ITER_A = 166; // 32
+static const uint64_t SH_FLD_01_DL_FORCE_ON = 167; // 16
+static const uint64_t SH_FLD_01_DONE = 168; // 32
+static const uint64_t SH_FLD_01_DQS = 169; // 16
+static const uint64_t SH_FLD_01_DQSCLK_SELECT0 = 170; // 64
+static const uint64_t SH_FLD_01_DQSCLK_SELECT0_LEN = 171; // 64
+static const uint64_t SH_FLD_01_DQSCLK_SELECT1 = 172; // 64
+static const uint64_t SH_FLD_01_DQSCLK_SELECT1_LEN = 173; // 64
+static const uint64_t SH_FLD_01_DQSCLK_SELECT2 = 174; // 64
+static const uint64_t SH_FLD_01_DQSCLK_SELECT2_LEN = 175; // 64
+static const uint64_t SH_FLD_01_DQSCLK_SELECT3 = 176; // 64
+static const uint64_t SH_FLD_01_DQSCLK_SELECT3_LEN = 177; // 64
+static const uint64_t SH_FLD_01_DQS_ALIGN_CNTR = 178; // 16
+static const uint64_t SH_FLD_01_DQS_ALIGN_CNTR_LEN = 179; // 16
+static const uint64_t SH_FLD_01_DQS_ALIGN_FIX_DIS = 180; // 16
+static const uint64_t SH_FLD_01_DQS_ALIGN_JITTER = 181; // 16
+static const uint64_t SH_FLD_01_DQS_ALIGN_QUAD = 182; // 16
+static const uint64_t SH_FLD_01_DQS_ALIGN_QUAD_LEN = 183; // 16
+static const uint64_t SH_FLD_01_DQS_ALIGN_SM = 184; // 16
+static const uint64_t SH_FLD_01_DQS_ALIGN_SM_LEN = 185; // 16
+static const uint64_t SH_FLD_01_DQS_LEN = 186; // 16
+static const uint64_t SH_FLD_01_DQS_PIPE_FIX_DIS = 187; // 16
+static const uint64_t SH_FLD_01_DQS_PIPE_FIX_DIS_LEN = 188; // 16
+static const uint64_t SH_FLD_01_DQS_QUAD_CONFIG = 189; // 16
+static const uint64_t SH_FLD_01_DQS_QUAD_CONFIG_LEN = 190; // 16
+static const uint64_t SH_FLD_01_DRIFT_ERROR = 191; // 16
+static const uint64_t SH_FLD_01_DRIFT_MASK = 192; // 16
+static const uint64_t SH_FLD_01_DRVREN_MODE = 193; // 32
+static const uint64_t SH_FLD_01_DYN_MCTERM_CNTL_EN = 194; // 16
+static const uint64_t SH_FLD_01_DYN_POWER_CNTL_EN = 195; // 16
+static const uint64_t SH_FLD_01_DYN_RX_GATE_CNTL_EN = 196; // 16
+static const uint64_t SH_FLD_01_ENABLE_0_15 = 197; // 8
+static const uint64_t SH_FLD_01_ENABLE_0_15_LEN = 198; // 8
+static const uint64_t SH_FLD_01_ENABLE_15 = 199; // 8
+static const uint64_t SH_FLD_01_ENABLE_15_LEN = 200; // 8
+static const uint64_t SH_FLD_01_ENABLE_16_23 = 201; // 16
+static const uint64_t SH_FLD_01_ENABLE_16_23_LEN = 202; // 16
+static const uint64_t SH_FLD_01_EN_DQS_OFFSET = 203; // 16
+static const uint64_t SH_FLD_01_EN_DRIVER_INVFB_DC = 204; // 32
+static const uint64_t SH_FLD_01_EN_N_WR = 205; // 16
+static const uint64_t SH_FLD_01_EN_N_WR_LEN = 206; // 16
+static const uint64_t SH_FLD_01_EN_P_WR = 207; // 32
+static const uint64_t SH_FLD_01_EN_P_WR_LEN = 208; // 32
+static const uint64_t SH_FLD_01_ERROR = 209; // 16
+static const uint64_t SH_FLD_01_ERROR_LEN = 210; // 16
+static const uint64_t SH_FLD_01_ERR_CLK22_MASK = 211; // 16
+static const uint64_t SH_FLD_01_EYE_CLIPPING = 212; // 16
+static const uint64_t SH_FLD_01_EYE_CLIPPING_MASK = 213; // 16
+static const uint64_t SH_FLD_01_FINE_STEPPING = 214; // 16
+static const uint64_t SH_FLD_01_FLUSH = 215; // 16
+static const uint64_t SH_FLD_01_FORCE_DQS_LANES_ON = 216; // 16
+static const uint64_t SH_FLD_01_FORCE_FIFO_CAPTURE = 217; // 16
+static const uint64_t SH_FLD_01_FW_LEFT_SIDE = 218; // 16
+static const uint64_t SH_FLD_01_FW_LEFT_SIDE_LEN = 219; // 16
+static const uint64_t SH_FLD_01_FW_RIGHT_SIDE = 220; // 16
+static const uint64_t SH_FLD_01_FW_RIGHT_SIDE_LEN = 221; // 16
+static const uint64_t SH_FLD_01_HS_DLLMUX_SEL_0_0_3 = 222; // 8
+static const uint64_t SH_FLD_01_HS_DLLMUX_SEL_0_0_3_LEN = 223; // 8
+static const uint64_t SH_FLD_01_HS_DLLMUX_SEL_0_3 = 224; // 16
+static const uint64_t SH_FLD_01_HS_DLLMUX_SEL_0_3_LEN = 225; // 16
+static const uint64_t SH_FLD_01_HS_DLLMUX_SEL_1_3 = 226; // 8
+static const uint64_t SH_FLD_01_HS_DLLMUX_SEL_1_3_LEN = 227; // 8
+static const uint64_t SH_FLD_01_HS_PROBE_A = 228; // 16
+static const uint64_t SH_FLD_01_HS_PROBE_A_LEN = 229; // 16
+static const uint64_t SH_FLD_01_HS_PROBE_B = 230; // 16
+static const uint64_t SH_FLD_01_HS_PROBE_B_LEN = 231; // 16
+static const uint64_t SH_FLD_01_HW_VALUE = 232; // 16
+static const uint64_t SH_FLD_01_INCOMPLETE_CAL_N0 = 233; // 16
+static const uint64_t SH_FLD_01_INCOMPLETE_CAL_N0_MASK = 234; // 16
+static const uint64_t SH_FLD_01_INCOMPLETE_CAL_N1 = 235; // 16
+static const uint64_t SH_FLD_01_INCOMPLETE_CAL_N1_MASK = 236; // 16
+static const uint64_t SH_FLD_01_INCOMPLETE_CAL_N2 = 237; // 16
+static const uint64_t SH_FLD_01_INCOMPLETE_CAL_N2_MASK = 238; // 16
+static const uint64_t SH_FLD_01_INCOMPLETE_CAL_N3 = 239; // 16
+static const uint64_t SH_FLD_01_INCOMPLETE_CAL_N3_MASK = 240; // 16
+static const uint64_t SH_FLD_01_INIT_IO = 241; // 16
+static const uint64_t SH_FLD_01_INIT_RXDLL_CAL_RESET = 242; // 32
+static const uint64_t SH_FLD_01_INIT_RXDLL_CAL_UPDATE = 243; // 32
+static const uint64_t SH_FLD_01_INTERP_SIG_SLEW = 244; // 16
+static const uint64_t SH_FLD_01_INTERP_SIG_SLEW_LEN = 245; // 16
+static const uint64_t SH_FLD_01_INVALID_NS_BIG_R = 246; // 16
+static const uint64_t SH_FLD_01_INVALID_NS_BIG_R_MASK = 247; // 16
+static const uint64_t SH_FLD_01_INVALID_NS_SMALL_L = 248; // 16
+static const uint64_t SH_FLD_01_INVALID_NS_SMALL_L_MASK = 249; // 16
+static const uint64_t SH_FLD_01_INVALID_NS_SMALL_R = 250; // 16
+static const uint64_t SH_FLD_01_INVALID_NS_SMALL_R_MASK = 251; // 16
+static const uint64_t SH_FLD_01_ITERATION_CNTR = 252; // 16
+static const uint64_t SH_FLD_01_ITERATION_CNTR_LEN = 253; // 16
+static const uint64_t SH_FLD_01_JUMP_BACK_RIGHT = 254; // 16
+static const uint64_t SH_FLD_01_LANE__0_11_PD = 255; // 16
+static const uint64_t SH_FLD_01_LANE__0_11_PD_LEN = 256; // 16
+static const uint64_t SH_FLD_01_LANE__12_15_PD = 257; // 16
+static const uint64_t SH_FLD_01_LANE__12_15_PD_LEN = 258; // 16
+static const uint64_t SH_FLD_01_LEADING_EDGE_FOUND_MASK = 259; // 16
+static const uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND = 260; // 16
+static const uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_0_15 = 261; // 8
+static const uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_0_15_LEN = 262; // 8
+static const uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_15 = 263; // 8
+static const uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_15_LEN = 264; // 8
+static const uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23 = 265; // 16
+static const uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23_LEN = 266; // 16
+static const uint64_t SH_FLD_01_LEN = 267; // 128
+static const uint64_t SH_FLD_01_LOOPBACK_DLY12 = 268; // 16
+static const uint64_t SH_FLD_01_LOOPBACK_FIX_EN = 269; // 16
+static const uint64_t SH_FLD_01_LOWER = 270; // 32
+static const uint64_t SH_FLD_01_LOWER_LEN = 271; // 32
+static const uint64_t SH_FLD_01_MAIN_PD_ENABLE = 272; // 32
+static const uint64_t SH_FLD_01_MATCH_STEP_RIGHT = 273; // 16
+static const uint64_t SH_FLD_01_MAX_DQS = 274; // 16
+static const uint64_t SH_FLD_01_MAX_DQS_ITER = 275; // 16
+static const uint64_t SH_FLD_01_MAX_DQS_LEN = 276; // 16
+static const uint64_t SH_FLD_01_MAX_RANGE = 277; // 16
+static const uint64_t SH_FLD_01_MAX_RANGE_ERR0 = 278; // 16
+static const uint64_t SH_FLD_01_MAX_RANGE_ERR1 = 279; // 16
+static const uint64_t SH_FLD_01_MAX_RANGE_ERR2 = 280; // 16
+static const uint64_t SH_FLD_01_MAX_RANGE_ERR3 = 281; // 16
+static const uint64_t SH_FLD_01_MAX_RANGE_MASK1 = 282; // 16
+static const uint64_t SH_FLD_01_MAX_RANGE_MASK2 = 283; // 16
+static const uint64_t SH_FLD_01_MAX_RANGE_MASK3 = 284; // 16
+static const uint64_t SH_FLD_01_MEMINTD00 = 285; // 16
+static const uint64_t SH_FLD_01_MEMINTD00_LEN = 286; // 16
+static const uint64_t SH_FLD_01_MEMINTD01 = 287; // 16
+static const uint64_t SH_FLD_01_MEMINTD01_LEN = 288; // 16
+static const uint64_t SH_FLD_01_MEMINTD02 = 289; // 16
+static const uint64_t SH_FLD_01_MEMINTD02_LEN = 290; // 16
+static const uint64_t SH_FLD_01_MEMINTD03 = 291; // 16
+static const uint64_t SH_FLD_01_MEMINTD03_LEN = 292; // 16
+static const uint64_t SH_FLD_01_MEMINTD04 = 293; // 16
+static const uint64_t SH_FLD_01_MEMINTD04_LEN = 294; // 16
+static const uint64_t SH_FLD_01_MEMINTD05 = 295; // 16
+static const uint64_t SH_FLD_01_MEMINTD05_LEN = 296; // 16
+static const uint64_t SH_FLD_01_MEMINTD06 = 297; // 16
+static const uint64_t SH_FLD_01_MEMINTD06_LEN = 298; // 16
+static const uint64_t SH_FLD_01_MEMINTD07 = 299; // 16
+static const uint64_t SH_FLD_01_MEMINTD07_LEN = 300; // 16
+static const uint64_t SH_FLD_01_MEMINTD08 = 301; // 16
+static const uint64_t SH_FLD_01_MEMINTD08_LEN = 302; // 16
+static const uint64_t SH_FLD_01_MEMINTD09 = 303; // 16
+static const uint64_t SH_FLD_01_MEMINTD09_LEN = 304; // 16
+static const uint64_t SH_FLD_01_MEMINTD10 = 305; // 16
+static const uint64_t SH_FLD_01_MEMINTD10_LEN = 306; // 16
+static const uint64_t SH_FLD_01_MEMINTD11 = 307; // 16
+static const uint64_t SH_FLD_01_MEMINTD11_LEN = 308; // 16
+static const uint64_t SH_FLD_01_MEMINTD12 = 309; // 16
+static const uint64_t SH_FLD_01_MEMINTD12_LEN = 310; // 16
+static const uint64_t SH_FLD_01_MEMINTD13 = 311; // 16
+static const uint64_t SH_FLD_01_MEMINTD13_LEN = 312; // 16
+static const uint64_t SH_FLD_01_MEMINTD14 = 313; // 16
+static const uint64_t SH_FLD_01_MEMINTD14_LEN = 314; // 16
+static const uint64_t SH_FLD_01_MEMINTD15 = 315; // 16
+static const uint64_t SH_FLD_01_MEMINTD15_LEN = 316; // 16
+static const uint64_t SH_FLD_01_MEMINTD16 = 317; // 16
+static const uint64_t SH_FLD_01_MEMINTD16_LEN = 318; // 16
+static const uint64_t SH_FLD_01_MEMINTD17 = 319; // 16
+static const uint64_t SH_FLD_01_MEMINTD17_LEN = 320; // 16
+static const uint64_t SH_FLD_01_MEMINTD18 = 321; // 16
+static const uint64_t SH_FLD_01_MEMINTD18_LEN = 322; // 16
+static const uint64_t SH_FLD_01_MEMINTD19 = 323; // 16
+static const uint64_t SH_FLD_01_MEMINTD19_LEN = 324; // 16
+static const uint64_t SH_FLD_01_MEMINTD20 = 325; // 16
+static const uint64_t SH_FLD_01_MEMINTD20_LEN = 326; // 16
+static const uint64_t SH_FLD_01_MEMINTD21 = 327; // 16
+static const uint64_t SH_FLD_01_MEMINTD21_LEN = 328; // 16
+static const uint64_t SH_FLD_01_MEMINTD22 = 329; // 16
+static const uint64_t SH_FLD_01_MEMINTD22_LEN = 330; // 16
+static const uint64_t SH_FLD_01_MEMINTD23 = 331; // 16
+static const uint64_t SH_FLD_01_MEMINTD23_LEN = 332; // 16
+static const uint64_t SH_FLD_01_MIN_EYE = 333; // 16
+static const uint64_t SH_FLD_01_MIN_EYE_MASK = 334; // 16
+static const uint64_t SH_FLD_01_MIN_RANGE = 335; // 16
+static const uint64_t SH_FLD_01_MIN_RANGE_ERR0 = 336; // 16
+static const uint64_t SH_FLD_01_MIN_RANGE_ERR1 = 337; // 16
+static const uint64_t SH_FLD_01_MIN_RANGE_ERR2 = 338; // 16
+static const uint64_t SH_FLD_01_MIN_RANGE_ERR3 = 339; // 16
+static const uint64_t SH_FLD_01_MIN_RANGE_MASK1 = 340; // 16
+static const uint64_t SH_FLD_01_MIN_RANGE_MASK2 = 341; // 16
+static const uint64_t SH_FLD_01_MIN_RANGE_MASK3 = 342; // 16
+static const uint64_t SH_FLD_01_MIN_RD_EYE_SIZE = 343; // 16
+static const uint64_t SH_FLD_01_MIN_RD_EYE_SIZE_LEN = 344; // 16
+static const uint64_t SH_FLD_01_MRS_CMD_N0 = 345; // 16
+static const uint64_t SH_FLD_01_MRS_CMD_N1 = 346; // 16
+static const uint64_t SH_FLD_01_MRS_CMD_N2 = 347; // 16
+static const uint64_t SH_FLD_01_MRS_CMD_N3 = 348; // 16
+static const uint64_t SH_FLD_01_N0 = 349; // 128
+static const uint64_t SH_FLD_01_N0_LEN = 350; // 128
+static const uint64_t SH_FLD_01_N1 = 351; // 128
+static const uint64_t SH_FLD_01_N1_LEN = 352; // 128
+static const uint64_t SH_FLD_01_N2 = 353; // 128
+static const uint64_t SH_FLD_01_N2_LEN = 354; // 128
+static const uint64_t SH_FLD_01_N3 = 355; // 128
+static const uint64_t SH_FLD_01_N3_LEN = 356; // 128
+static const uint64_t SH_FLD_01_NIB0 = 357; // 16
+static const uint64_t SH_FLD_01_NIB0TCFLIP_DC = 358; // 16
+static const uint64_t SH_FLD_01_NIB0_EN_FORCE = 359; // 16
+static const uint64_t SH_FLD_01_NIB0_LEN = 360; // 16
+static const uint64_t SH_FLD_01_NIB1 = 361; // 16
+static const uint64_t SH_FLD_01_NIB1TCFLIP_DC = 362; // 16
+static const uint64_t SH_FLD_01_NIB1_EN_FORCE = 363; // 16
+static const uint64_t SH_FLD_01_NIB1_LEN = 364; // 16
+static const uint64_t SH_FLD_01_NIB2 = 365; // 16
+static const uint64_t SH_FLD_01_NIB2TCFLIP_DC = 366; // 16
+static const uint64_t SH_FLD_01_NIB2_EN_FORCE = 367; // 16
+static const uint64_t SH_FLD_01_NIB2_LEN = 368; // 16
+static const uint64_t SH_FLD_01_NIB3 = 369; // 16
+static const uint64_t SH_FLD_01_NIB3TCFLIP_DC = 370; // 16
+static const uint64_t SH_FLD_01_NIB3_EN_FORCE = 371; // 16
+static const uint64_t SH_FLD_01_NIB3_LEN = 372; // 16
+static const uint64_t SH_FLD_01_NIB_0_2_DQSEL_CAP = 373; // 16
+static const uint64_t SH_FLD_01_NIB_0_2_DQSEL_CAP_LEN = 374; // 16
+static const uint64_t SH_FLD_01_NIB_0_2_DQSEL_RES = 375; // 16
+static const uint64_t SH_FLD_01_NIB_0_2_DQSEL_RES_LEN = 376; // 16
+static const uint64_t SH_FLD_01_NIB_1_3_DQSEL_CAP = 377; // 16
+static const uint64_t SH_FLD_01_NIB_1_3_DQSEL_CAP_LEN = 378; // 16
+static const uint64_t SH_FLD_01_NIB_1_3_DQSEL_RES = 379; // 16
+static const uint64_t SH_FLD_01_NIB_1_3_DQSEL_RES_LEN = 380; // 16
+static const uint64_t SH_FLD_01_NIB_2_DQSEL_CAP = 381; // 16
+static const uint64_t SH_FLD_01_NIB_2_DQSEL_CAP_LEN = 382; // 16
+static const uint64_t SH_FLD_01_NIB_2_DQSEL_RES = 383; // 16
+static const uint64_t SH_FLD_01_NIB_2_DQSEL_RES_LEN = 384; // 16
+static const uint64_t SH_FLD_01_NIB_3_DQSEL_CAP = 385; // 16
+static const uint64_t SH_FLD_01_NIB_3_DQSEL_CAP_LEN = 386; // 16
+static const uint64_t SH_FLD_01_NIB_3_DQSEL_RES = 387; // 16
+static const uint64_t SH_FLD_01_NIB_3_DQSEL_RES_LEN = 388; // 16
+static const uint64_t SH_FLD_01_NO_DQS = 389; // 16
+static const uint64_t SH_FLD_01_NO_DQS_MASK = 390; // 16
+static const uint64_t SH_FLD_01_NO_EYE_DETECTED = 391; // 16
+static const uint64_t SH_FLD_01_NO_EYE_DETECTED_MASK = 392; // 16
+static const uint64_t SH_FLD_01_NO_INCREASE = 393; // 16
+static const uint64_t SH_FLD_01_NO_INCREASE_ERR0 = 394; // 16
+static const uint64_t SH_FLD_01_NO_INCREASE_ERR1 = 395; // 16
+static const uint64_t SH_FLD_01_NO_INCREASE_ERR2 = 396; // 16
+static const uint64_t SH_FLD_01_NO_INCREASE_ERR3 = 397; // 16
+static const uint64_t SH_FLD_01_NO_INCREASE_MASK1 = 398; // 16
+static const uint64_t SH_FLD_01_NO_INCREASE_MASK2 = 399; // 16
+static const uint64_t SH_FLD_01_NO_INCREASE_MASK3 = 400; // 16
+static const uint64_t SH_FLD_01_NO_LOCK = 401; // 16
+static const uint64_t SH_FLD_01_NO_LOCK_MASK = 402; // 16
+static const uint64_t SH_FLD_01_OFFSET0 = 403; // 16
+static const uint64_t SH_FLD_01_OFFSET0_LEN = 404; // 16
+static const uint64_t SH_FLD_01_OFFSET1 = 405; // 16
+static const uint64_t SH_FLD_01_OFFSET1_LEN = 406; // 16
+static const uint64_t SH_FLD_01_OFFSET2 = 407; // 32
+static const uint64_t SH_FLD_01_OFFSET2_LEN = 408; // 32
+static const uint64_t SH_FLD_01_OFFSET3 = 409; // 32
+static const uint64_t SH_FLD_01_OFFSET3_LEN = 410; // 32
+static const uint64_t SH_FLD_01_OFFSET4 = 411; // 32
+static const uint64_t SH_FLD_01_OFFSET4_LEN = 412; // 32
+static const uint64_t SH_FLD_01_OFFSET5 = 413; // 32
+static const uint64_t SH_FLD_01_OFFSET5_LEN = 414; // 32
+static const uint64_t SH_FLD_01_OFFSET6 = 415; // 32
+static const uint64_t SH_FLD_01_OFFSET6_LEN = 416; // 32
+static const uint64_t SH_FLD_01_OFFSET7 = 417; // 32
+static const uint64_t SH_FLD_01_OFFSET7_LEN = 418; // 32
+static const uint64_t SH_FLD_01_OFFSET_ERR = 419; // 16
+static const uint64_t SH_FLD_01_OFFSET_ERR_MASK = 420; // 16
+static const uint64_t SH_FLD_01_OPERATE_MODE = 421; // 16
+static const uint64_t SH_FLD_01_OPERATE_MODE_LEN = 422; // 16
+static const uint64_t SH_FLD_01_OVERRIDE = 423; // 32
+static const uint64_t SH_FLD_01_PERCAL_PWR_DIS = 424; // 16
+static const uint64_t SH_FLD_01_PER_CAL_UPDATE_DISABLE = 425; // 16
+static const uint64_t SH_FLD_01_PHASE_ALIGN_RESET = 426; // 32
+static const uint64_t SH_FLD_01_PHASE_CNTL_EN = 427; // 32
+static const uint64_t SH_FLD_01_PHASE_DEFAULT_EN = 428; // 32
+static const uint64_t SH_FLD_01_POS_EDGE_ALIGN = 429; // 32
+static const uint64_t SH_FLD_01_QUAD0 = 430; // 16
+static const uint64_t SH_FLD_01_QUAD0_CLK16 = 431; // 128
+static const uint64_t SH_FLD_01_QUAD0_CLK18 = 432; // 128
+static const uint64_t SH_FLD_01_QUAD0_LEN = 433; // 16
+static const uint64_t SH_FLD_01_QUAD1 = 434; // 16
+static const uint64_t SH_FLD_01_QUAD1_CLK16 = 435; // 128
+static const uint64_t SH_FLD_01_QUAD1_CLK18 = 436; // 128
+static const uint64_t SH_FLD_01_QUAD1_LEN = 437; // 16
+static const uint64_t SH_FLD_01_QUAD2 = 438; // 16
+static const uint64_t SH_FLD_01_QUAD2_CLK16 = 439; // 64
+static const uint64_t SH_FLD_01_QUAD2_CLK18 = 440; // 64
+static const uint64_t SH_FLD_01_QUAD2_CLK20 = 441; // 128
+static const uint64_t SH_FLD_01_QUAD2_CLK22 = 442; // 128
+static const uint64_t SH_FLD_01_QUAD2_LEN = 443; // 16
+static const uint64_t SH_FLD_01_QUAD3 = 444; // 16
+static const uint64_t SH_FLD_01_QUAD3_CLK16 = 445; // 64
+static const uint64_t SH_FLD_01_QUAD3_CLK18 = 446; // 64
+static const uint64_t SH_FLD_01_QUAD3_CLK20 = 447; // 128
+static const uint64_t SH_FLD_01_QUAD3_CLK22 = 448; // 128
+static const uint64_t SH_FLD_01_QUAD3_LEN = 449; // 16
+static const uint64_t SH_FLD_01_RANGE_DRAM0 = 450; // 64
+static const uint64_t SH_FLD_01_RANGE_DRAM1 = 451; // 64
+static const uint64_t SH_FLD_01_RANGE_DRAM2 = 452; // 64
+static const uint64_t SH_FLD_01_RANGE_DRAM3 = 453; // 64
+static const uint64_t SH_FLD_01_RD = 454; // 272
+static const uint64_t SH_FLD_01_RDCLK_SELECT0 = 455; // 64
+static const uint64_t SH_FLD_01_RDCLK_SELECT0_LEN = 456; // 64
+static const uint64_t SH_FLD_01_RDCLK_SELECT1 = 457; // 64
+static const uint64_t SH_FLD_01_RDCLK_SELECT1_LEN = 458; // 64
+static const uint64_t SH_FLD_01_RDCLK_SELECT2 = 459; // 64
+static const uint64_t SH_FLD_01_RDCLK_SELECT2_LEN = 460; // 64
+static const uint64_t SH_FLD_01_RDCLK_SELECT3 = 461; // 64
+static const uint64_t SH_FLD_01_RDCLK_SELECT3_LEN = 462; // 64
+static const uint64_t SH_FLD_01_RD_DELAY0 = 463; // 112
+static const uint64_t SH_FLD_01_RD_DELAY0_LEN = 464; // 112
+static const uint64_t SH_FLD_01_RD_DELAY1 = 465; // 112
+static const uint64_t SH_FLD_01_RD_DELAY1_LEN = 466; // 112
+static const uint64_t SH_FLD_01_RD_DELAY2 = 467; // 112
+static const uint64_t SH_FLD_01_RD_DELAY2_LEN = 468; // 112
+static const uint64_t SH_FLD_01_RD_DELAY3 = 469; // 112
+static const uint64_t SH_FLD_01_RD_DELAY3_LEN = 470; // 112
+static const uint64_t SH_FLD_01_RD_DELAY4 = 471; // 112
+static const uint64_t SH_FLD_01_RD_DELAY4_LEN = 472; // 112
+static const uint64_t SH_FLD_01_RD_DELAY5 = 473; // 112
+static const uint64_t SH_FLD_01_RD_DELAY5_LEN = 474; // 112
+static const uint64_t SH_FLD_01_RD_DELAY6 = 475; // 112
+static const uint64_t SH_FLD_01_RD_DELAY6_LEN = 476; // 112
+static const uint64_t SH_FLD_01_RD_DELAY7 = 477; // 112
+static const uint64_t SH_FLD_01_RD_DELAY7_LEN = 478; // 112
+static const uint64_t SH_FLD_01_RD_LEN = 479; // 272
+static const uint64_t SH_FLD_01_RD_SIZE0 = 480; // 176
+static const uint64_t SH_FLD_01_RD_SIZE0_LEN = 481; // 176
+static const uint64_t SH_FLD_01_RD_SIZE1 = 482; // 176
+static const uint64_t SH_FLD_01_RD_SIZE1_LEN = 483; // 176
+static const uint64_t SH_FLD_01_RD_SIZE2 = 484; // 176
+static const uint64_t SH_FLD_01_RD_SIZE2_LEN = 485; // 176
+static const uint64_t SH_FLD_01_RD_SIZE3 = 486; // 176
+static const uint64_t SH_FLD_01_RD_SIZE3_LEN = 487; // 176
+static const uint64_t SH_FLD_01_RD_SIZE4 = 488; // 176
+static const uint64_t SH_FLD_01_RD_SIZE4_LEN = 489; // 176
+static const uint64_t SH_FLD_01_RD_SIZE5 = 490; // 176
+static const uint64_t SH_FLD_01_RD_SIZE5_LEN = 491; // 176
+static const uint64_t SH_FLD_01_RD_SIZE6 = 492; // 176
+static const uint64_t SH_FLD_01_RD_SIZE6_LEN = 493; // 176
+static const uint64_t SH_FLD_01_RD_SIZE7 = 494; // 176
+static const uint64_t SH_FLD_01_RD_SIZE7_LEN = 495; // 176
+static const uint64_t SH_FLD_01_READ_CENTERING_MODE = 496; // 16
+static const uint64_t SH_FLD_01_READ_CENTERING_MODE_LEN = 497; // 16
+static const uint64_t SH_FLD_01_REFERENCE1 = 498; // 16
+static const uint64_t SH_FLD_01_REFERENCE1_LEN = 499; // 16
+static const uint64_t SH_FLD_01_REFERENCE2 = 500; // 16
+static const uint64_t SH_FLD_01_REFERENCE2_LEN = 501; // 16
+static const uint64_t SH_FLD_01_REFERENCE3 = 502; // 16
+static const uint64_t SH_FLD_01_REFERENCE3_LEN = 503; // 16
+static const uint64_t SH_FLD_01_REGS_RXDLL_CAL_SKIP = 504; // 32
+static const uint64_t SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN = 505; // 32
+static const uint64_t SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 = 506; // 32
+static const uint64_t SH_FLD_01_REGS_RXDLL_COARSE_EN = 507; // 32
+static const uint64_t SH_FLD_01_REGS_RXDLL_COARSE_EN_LEN = 508; // 32
+static const uint64_t SH_FLD_01_REGS_RXDLL_DAC_COARSE = 509; // 32
+static const uint64_t SH_FLD_01_REGS_RXDLL_DAC_COARSE_LEN = 510; // 32
+static const uint64_t SH_FLD_01_REGS_RXDLL_VREG_LOWER = 511; // 32
+static const uint64_t SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN = 512; // 32
+static const uint64_t SH_FLD_01_REGS_RXDLL_VREG_UPPER = 513; // 32
+static const uint64_t SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN = 514; // 32
+static const uint64_t SH_FLD_01_ROT0 = 515; // 16
+static const uint64_t SH_FLD_01_ROT0_LEN = 516; // 16
+static const uint64_t SH_FLD_01_ROT1 = 517; // 16
+static const uint64_t SH_FLD_01_ROT1_LEN = 518; // 16
+static const uint64_t SH_FLD_01_ROT_CLK_N0 = 519; // 128
+static const uint64_t SH_FLD_01_ROT_CLK_N0_LEN = 520; // 128
+static const uint64_t SH_FLD_01_ROT_CLK_N1 = 521; // 128
+static const uint64_t SH_FLD_01_ROT_CLK_N1_LEN = 522; // 128
+static const uint64_t SH_FLD_01_ROT_N0 = 523; // 128
+static const uint64_t SH_FLD_01_ROT_N0_LEN = 524; // 128
+static const uint64_t SH_FLD_01_ROT_N1 = 525; // 128
+static const uint64_t SH_FLD_01_ROT_N1_LEN = 526; // 128
+static const uint64_t SH_FLD_01_ROT_OVERRIDE = 527; // 32
+static const uint64_t SH_FLD_01_ROT_OVERRIDE_EN = 528; // 32
+static const uint64_t SH_FLD_01_ROT_OVERRIDE_LEN = 529; // 32
+static const uint64_t SH_FLD_01_RXCAL_DETECT_DONE_META = 530; // 32
+static const uint64_t SH_FLD_01_RXCAL_PD_CAL_LAG_META = 531; // 32
+static const uint64_t SH_FLD_01_RXCAL_PD_MAIN_LAG_META = 532; // 32
+static const uint64_t SH_FLD_01_RXCAL_PD_MAIN_LEAD_META = 533; // 32
+static const uint64_t SH_FLD_01_RXREG_COMPCON_DC = 534; // 32
+static const uint64_t SH_FLD_01_RXREG_COMPCON_DC_LEN = 535; // 32
+static const uint64_t SH_FLD_01_RXREG_CON_DC = 536; // 32
+static const uint64_t SH_FLD_01_RXREG_DAC_PULLUP_DC = 537; // 32
+static const uint64_t SH_FLD_01_RXREG_DRVCON_DC = 538; // 32
+static const uint64_t SH_FLD_01_RXREG_DRVCON_DC_LEN = 539; // 32
+static const uint64_t SH_FLD_01_RXREG_FILTER_LENGTH_DC = 540; // 32
+static const uint64_t SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN = 541; // 32
+static const uint64_t SH_FLD_01_RXREG_FINECAL_2XILSB_DC = 542; // 32
+static const uint64_t SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC = 543; // 32
+static const uint64_t SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 544; // 32
+static const uint64_t SH_FLD_01_RXREG_REF_SEL_DC = 545; // 32
+static const uint64_t SH_FLD_01_RXREG_REF_SEL_DC_LEN = 546; // 32
+static const uint64_t SH_FLD_01_S0ACENSLICENDRV_DC = 547; // 16
+static const uint64_t SH_FLD_01_S0ACENSLICENDRV_DC_LEN = 548; // 16
+static const uint64_t SH_FLD_01_S0ACENSLICEPDRV_DC = 549; // 16
+static const uint64_t SH_FLD_01_S0ACENSLICEPDRV_DC_LEN = 550; // 16
+static const uint64_t SH_FLD_01_S0ACENSLICEPTERM_DC = 551; // 16
+static const uint64_t SH_FLD_01_S0ACENSLICEPTERM_DC_LEN = 552; // 16
+static const uint64_t SH_FLD_01_S0INSDLYTAP = 553; // 16
+static const uint64_t SH_FLD_01_S1ACENSLICENDRV_DC = 554; // 16
+static const uint64_t SH_FLD_01_S1ACENSLICENDRV_DC_LEN = 555; // 16
+static const uint64_t SH_FLD_01_S1ACENSLICEPDRV_DC = 556; // 16
+static const uint64_t SH_FLD_01_S1ACENSLICEPDRV_DC_LEN = 557; // 16
+static const uint64_t SH_FLD_01_S1ACENSLICEPTERM_DC = 558; // 16
+static const uint64_t SH_FLD_01_S1ACENSLICEPTERM_DC_LEN = 559; // 16
+static const uint64_t SH_FLD_01_S1INSDLYTAP = 560; // 16
+static const uint64_t SH_FLD_01_SEL0 = 561; // 32
+static const uint64_t SH_FLD_01_SEL0_LEN = 562; // 16
+static const uint64_t SH_FLD_01_SEL1 = 563; // 32
+static const uint64_t SH_FLD_01_SEL10 = 564; // 32
+static const uint64_t SH_FLD_01_SEL10_LEN = 565; // 32
+static const uint64_t SH_FLD_01_SEL11 = 566; // 32
+static const uint64_t SH_FLD_01_SEL11_LEN = 567; // 32
+static const uint64_t SH_FLD_01_SEL12 = 568; // 32
+static const uint64_t SH_FLD_01_SEL12_LEN = 569; // 32
+static const uint64_t SH_FLD_01_SEL13 = 570; // 32
+static const uint64_t SH_FLD_01_SEL13_LEN = 571; // 32
+static const uint64_t SH_FLD_01_SEL14 = 572; // 32
+static const uint64_t SH_FLD_01_SEL14_LEN = 573; // 32
+static const uint64_t SH_FLD_01_SEL15 = 574; // 32
+static const uint64_t SH_FLD_01_SEL15_LEN = 575; // 32
+static const uint64_t SH_FLD_01_SEL1_LEN = 576; // 32
+static const uint64_t SH_FLD_01_SEL2 = 577; // 32
+static const uint64_t SH_FLD_01_SEL2_LEN = 578; // 32
+static const uint64_t SH_FLD_01_SEL3 = 579; // 32
+static const uint64_t SH_FLD_01_SEL3_LEN = 580; // 32
+static const uint64_t SH_FLD_01_SEL4 = 581; // 32
+static const uint64_t SH_FLD_01_SEL4_LEN = 582; // 32
+static const uint64_t SH_FLD_01_SEL5 = 583; // 32
+static const uint64_t SH_FLD_01_SEL5_LEN = 584; // 32
+static const uint64_t SH_FLD_01_SEL6 = 585; // 32
+static const uint64_t SH_FLD_01_SEL6_LEN = 586; // 32
+static const uint64_t SH_FLD_01_SEL7 = 587; // 32
+static const uint64_t SH_FLD_01_SEL7_LEN = 588; // 32
+static const uint64_t SH_FLD_01_SEL8 = 589; // 32
+static const uint64_t SH_FLD_01_SEL8_LEN = 590; // 16
+static const uint64_t SH_FLD_01_SEL9 = 591; // 32
+static const uint64_t SH_FLD_01_SEL9_LEN = 592; // 32
+static const uint64_t SH_FLD_01_SEL_A = 593; // 16
+static const uint64_t SH_FLD_01_SEL_A_LEN = 594; // 16
+static const uint64_t SH_FLD_01_SEL_B = 595; // 16
+static const uint64_t SH_FLD_01_SEL_B_LEN = 596; // 16
+static const uint64_t SH_FLD_01_SLAVE_CAL_CKT_POWERDOWN = 597; // 32
+static const uint64_t SH_FLD_01_SLAVE_VREG_DAC_COARSE = 598; // 32
+static const uint64_t SH_FLD_01_SLAVE_VREG_DAC_COARSE_LEN = 599; // 32
+static const uint64_t SH_FLD_01_SLAVE_VREG_OVERRIDE = 600; // 32
+static const uint64_t SH_FLD_01_SLAVE_VREG_REF_SEL_DC = 601; // 32
+static const uint64_t SH_FLD_01_SLAVE_VREG_REF_SEL_DC_LEN = 602; // 32
+static const uint64_t SH_FLD_01_SMALL_STEP_LEFT = 603; // 16
+static const uint64_t SH_FLD_01_SMALL_STEP_RIGHT = 604; // 16
+static const uint64_t SH_FLD_01_STEP_RANGE_EDGE = 605; // 16
+static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_ERR0 = 606; // 16
+static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_ERR1 = 607; // 16
+static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_ERR2 = 608; // 16
+static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_ERR3 = 609; // 16
+static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_MASK1 = 610; // 16
+static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_MASK2 = 611; // 16
+static const uint64_t SH_FLD_01_STEP_RANGE_EDGE_MASK3 = 612; // 16
+static const uint64_t SH_FLD_01_SYNC = 613; // 16
+static const uint64_t SH_FLD_01_SYNC_LEN = 614; // 16
+static const uint64_t SH_FLD_01_SYSCLK_DQSCLK_OFFSET = 615; // 16
+static const uint64_t SH_FLD_01_SYSCLK_DQSCLK_OFFSET_LEN = 616; // 16
+static const uint64_t SH_FLD_01_SYSCLK_RDCLK_OFFSET = 617; // 16
+static const uint64_t SH_FLD_01_SYSCLK_RDCLK_OFFSET_LEN = 618; // 16
+static const uint64_t SH_FLD_01_TEST_4TO1_MODE = 619; // 16
+static const uint64_t SH_FLD_01_TEST_CHECK_EN = 620; // 16
+static const uint64_t SH_FLD_01_TEST_CLEAR_ERROR = 621; // 16
+static const uint64_t SH_FLD_01_TEST_DATA_EN = 622; // 16
+static const uint64_t SH_FLD_01_TEST_GEN_EN = 623; // 16
+static const uint64_t SH_FLD_01_TEST_LANE_PAIR_FAIL = 624; // 16
+static const uint64_t SH_FLD_01_TEST_LANE_PAIR_FAIL_LEN = 625; // 16
+static const uint64_t SH_FLD_01_TEST_MODE = 626; // 16
+static const uint64_t SH_FLD_01_TEST_MODE_LEN = 627; // 16
+static const uint64_t SH_FLD_01_TEST_RESET = 628; // 16
+static const uint64_t SH_FLD_01_TRAILING_EDGE_FOUND_MASK = 629; // 16
+static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND = 630; // 16
+static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15 = 631; // 8
+static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 632; // 8
+static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15 = 633; // 8
+static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15_LEN = 634; // 8
+static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23 = 635; // 16
+static const uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 636; // 16
+static const uint64_t SH_FLD_01_TRIG_PERIOD = 637; // 16
+static const uint64_t SH_FLD_01_TSYS = 638; // 16
+static const uint64_t SH_FLD_01_TSYS_LEN = 639; // 16
+static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE = 640; // 16
+static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_ERR0 = 641; // 16
+static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_ERR1 = 642; // 16
+static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_ERR2 = 643; // 16
+static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_ERR3 = 644; // 16
+static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_MASK1 = 645; // 16
+static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_MASK2 = 646; // 16
+static const uint64_t SH_FLD_01_TWO_RANGE_BEST_CASE_MASK3 = 647; // 16
+static const uint64_t SH_FLD_01_UPPER = 648; // 32
+static const uint64_t SH_FLD_01_UPPER_LEN = 649; // 32
+static const uint64_t SH_FLD_01_VALID_NS_BIG_L = 650; // 16
+static const uint64_t SH_FLD_01_VALID_NS_BIG_L_MASK = 651; // 16
+static const uint64_t SH_FLD_01_VALID_NS_BIG_R = 652; // 16
+static const uint64_t SH_FLD_01_VALID_NS_BIG_R_MASK = 653; // 16
+static const uint64_t SH_FLD_01_VALID_NS_JUMP_BACK = 654; // 16
+static const uint64_t SH_FLD_01_VALID_NS_JUMP_BACK_MASK = 655; // 16
+static const uint64_t SH_FLD_01_VALUE_DRAM0 = 656; // 64
+static const uint64_t SH_FLD_01_VALUE_DRAM0_LEN = 657; // 64
+static const uint64_t SH_FLD_01_VALUE_DRAM1 = 658; // 64
+static const uint64_t SH_FLD_01_VALUE_DRAM1_LEN = 659; // 64
+static const uint64_t SH_FLD_01_VALUE_DRAM2 = 660; // 64
+static const uint64_t SH_FLD_01_VALUE_DRAM2_LEN = 661; // 64
+static const uint64_t SH_FLD_01_VALUE_DRAM3 = 662; // 64
+static const uint64_t SH_FLD_01_VALUE_DRAM3_LEN = 663; // 64
+static const uint64_t SH_FLD_01_VREG_RXCAL_COMP_OUT_META = 664; // 32
+static const uint64_t SH_FLD_01_VREG_SLAVE_COMP_OUT = 665; // 32
+static const uint64_t SH_FLD_01_WL_ADVANCE_DISABLE = 666; // 16
+static const uint64_t SH_FLD_01_WL_ERR_CLK16 = 667; // 32
+static const uint64_t SH_FLD_01_WL_ERR_CLK16_MASK = 668; // 16
+static const uint64_t SH_FLD_01_WL_ERR_CLK18 = 669; // 32
+static const uint64_t SH_FLD_01_WL_ERR_CLK18_MASK = 670; // 16
+static const uint64_t SH_FLD_01_WL_ERR_CLK20 = 671; // 32
+static const uint64_t SH_FLD_01_WL_ERR_CLK20_MASK = 672; // 16
+static const uint64_t SH_FLD_01_WL_ERR_CLK22 = 673; // 32
+static const uint64_t SH_FLD_01_WRAPSEL = 674; // 16
+static const uint64_t SH_FLD_01_WTRFL_AVE_DIS = 675; // 16
+static const uint64_t SH_FLD_01_ZERO_DETECTED = 676; // 16
+static const uint64_t SH_FLD_0X00_DATA_PARITY = 677; // 4
+static const uint64_t SH_FLD_0X00_SPARE_30_31 = 678; // 1
+static const uint64_t SH_FLD_0X00_SPARE_30_31_LEN = 679; // 1
+static const uint64_t SH_FLD_0X01_DATA_PARITY = 680; // 4
+static const uint64_t SH_FLD_0X01_SPARE_03 = 681; // 1
+static const uint64_t SH_FLD_0X01_SPARE_28_31 = 682; // 1
+static const uint64_t SH_FLD_0X01_SPARE_28_31_LEN = 683; // 1
+static const uint64_t SH_FLD_0X02_DATA_PARITY = 684; // 4
+static const uint64_t SH_FLD_0X02_SPARE_03 = 685; // 1
+static const uint64_t SH_FLD_0X02_SPARE_28_31 = 686; // 1
+static const uint64_t SH_FLD_0X02_SPARE_28_31_LEN = 687; // 1
+static const uint64_t SH_FLD_0X03_DATA_PARITY = 688; // 4
+static const uint64_t SH_FLD_0X03_SPARE_03 = 689; // 1
+static const uint64_t SH_FLD_0X03_SPARE_28_31 = 690; // 1
+static const uint64_t SH_FLD_0X03_SPARE_28_31_LEN = 691; // 1
+static const uint64_t SH_FLD_0X04_DATA_PARITY = 692; // 4
+static const uint64_t SH_FLD_0X04_SPARE_03 = 693; // 1
+static const uint64_t SH_FLD_0X04_SPARE_28_31 = 694; // 1
+static const uint64_t SH_FLD_0X04_SPARE_28_31_LEN = 695; // 1
+static const uint64_t SH_FLD_0X05_DATA_PARITY = 696; // 4
+static const uint64_t SH_FLD_0X05_SPARE_01 = 697; // 1
+static const uint64_t SH_FLD_0X05_SPARE_05 = 698; // 1
+static const uint64_t SH_FLD_0X06_DATA_PARITY = 699; // 4
+static const uint64_t SH_FLD_0X06_SPARE_02_04 = 700; // 1
+static const uint64_t SH_FLD_0X06_SPARE_02_04_LEN = 701; // 1
+static const uint64_t SH_FLD_0X06_SPARE_16_21 = 702; // 1
+static const uint64_t SH_FLD_0X06_SPARE_16_21_LEN = 703; // 1
+static const uint64_t SH_FLD_0X07_DATA_PARITY = 704; // 4
+static const uint64_t SH_FLD_0X07_SPARE_19 = 705; // 1
+static const uint64_t SH_FLD_0X07_SPARE_20 = 706; // 1
+static const uint64_t SH_FLD_0X07_SPARE_22_31 = 707; // 1
+static const uint64_t SH_FLD_0X07_SPARE_22_31_LEN = 708; // 1
+static const uint64_t SH_FLD_0X08_DATA_PARITY = 709; // 4
+static const uint64_t SH_FLD_0X08_SPARE_03 = 710; // 1
+static const uint64_t SH_FLD_0X08_SPARE_30 = 711; // 1
+static const uint64_t SH_FLD_0X09_DATA_PARITY = 712; // 4
+static const uint64_t SH_FLD_0X0A_DATA_PARITY = 713; // 4
+static const uint64_t SH_FLD_0X0A_SPARE_13_15 = 714; // 1
+static const uint64_t SH_FLD_0X0A_SPARE_13_15_LEN = 715; // 1
+static const uint64_t SH_FLD_0X0B_DATA_PARITY = 716; // 4
+static const uint64_t SH_FLD_0X0B_SPARE_04_05 = 717; // 1
+static const uint64_t SH_FLD_0X0B_SPARE_04_05_LEN = 718; // 1
+static const uint64_t SH_FLD_0X0B_SPARE_17 = 719; // 1
+static const uint64_t SH_FLD_0X0B_SPARE_33_39 = 720; // 1
+static const uint64_t SH_FLD_0X0B_SPARE_33_39_LEN = 721; // 1
+static const uint64_t SH_FLD_0X0C_DATA_PARITY = 722; // 4
+static const uint64_t SH_FLD_0X0D_SPARE_60_62 = 723; // 1
+static const uint64_t SH_FLD_0X0D_SPARE_60_62_LEN = 724; // 1
+static const uint64_t SH_FLD_0X10_DATA_PARITY = 725; // 4
+static const uint64_t SH_FLD_0X10_SPARE_17_18 = 726; // 1
+static const uint64_t SH_FLD_0X10_SPARE_17_18_LEN = 727; // 1
+static const uint64_t SH_FLD_0X10_SPARE_19_23 = 728; // 1
+static const uint64_t SH_FLD_0X10_SPARE_19_23_LEN = 729; // 1
+static const uint64_t SH_FLD_0X10_SPARE_24_25 = 730; // 1
+static const uint64_t SH_FLD_0X10_SPARE_24_25_LEN = 731; // 1
+static const uint64_t SH_FLD_0X10_SPARE_27 = 732; // 1
+static const uint64_t SH_FLD_0X10_SPARE_29 = 733; // 1
+static const uint64_t SH_FLD_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY = 734; // 4
+static const uint64_t SH_FLD_0X17_0X18_0X21_0X22_DATA_PARITY = 735; // 4
+static const uint64_t SH_FLD_0X1D_0X1E_0X1F_DATA_PARITY = 736; // 4
+static const uint64_t SH_FLD_0X20_DATA_PARITY = 737; // 4
+static const uint64_t SH_FLD_0X22_SPARE_01 = 738; // 1
+static const uint64_t SH_FLD_0X22_SPARE_03_07 = 739; // 1
+static const uint64_t SH_FLD_0X22_SPARE_03_07_LEN = 740; // 1
+static const uint64_t SH_FLD_0X23_DATA_PARITY = 741; // 4
+static const uint64_t SH_FLD_0X23_SPARE_06_07 = 742; // 1
+static const uint64_t SH_FLD_0X23_SPARE_06_07_LEN = 743; // 1
+static const uint64_t SH_FLD_0X24_DATA_PARITY = 744; // 4
+static const uint64_t SH_FLD_0X24_SPARE_05_07 = 745; // 1
+static const uint64_t SH_FLD_0X24_SPARE_05_07_LEN = 746; // 1
+static const uint64_t SH_FLD_0X27_DATA_PARITY = 747; // 4
+static const uint64_t SH_FLD_0X27_SPARE_34 = 748; // 1
+static const uint64_t SH_FLD_0X27_SPARE_36 = 749; // 1
+static const uint64_t SH_FLD_0X29_DATA_PARITY = 750; // 4
+static const uint64_t SH_FLD_0X30_0X31_0X32_0X33_DATA_PARITY = 751; // 4
+static const uint64_t SH_FLD_0_2 = 752; // 16
+static const uint64_t SH_FLD_0_CANNED_0 = 753; // 2
+static const uint64_t SH_FLD_0_CANNED_0_LEN = 754; // 2
+static const uint64_t SH_FLD_0_CANNED_1 = 755; // 2
+static const uint64_t SH_FLD_0_CANNED_1_LEN = 756; // 2
+static const uint64_t SH_FLD_0_CPS = 757; // 2
+static const uint64_t SH_FLD_0_CPS_LEN = 758; // 2
+static const uint64_t SH_FLD_0_DATA = 759; // 1
+static const uint64_t SH_FLD_0_DATA_LEN = 760; // 1
+static const uint64_t SH_FLD_0_LEN = 761; // 62
+static const uint64_t SH_FLD_0_LOCAL_STEP_MODE_ENABLE = 762; // 1
+static const uint64_t SH_FLD_0_OSC_NOT_VALID = 763; // 1
+static const uint64_t SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT = 764; // 1
+static const uint64_t SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT_LEN = 765; // 1
+static const uint64_t SH_FLD_0_RESULT = 766; // 43
+static const uint64_t SH_FLD_0_RESULT_LEN = 767; // 43
+static const uint64_t SH_FLD_0_SELECT = 768; // 1
+static const uint64_t SH_FLD_0_SELECT_LEN = 769; // 1
+static const uint64_t SH_FLD_0_SPARE_SECTOR_BUFFER_CONTROL = 770; // 3
+static const uint64_t SH_FLD_0_STEP_ALIGN_DISABLE = 771; // 1
+static const uint64_t SH_FLD_0_STEP_ALIGN_THRESHOLD = 772; // 1
+static const uint64_t SH_FLD_0_STEP_ALIGN_THRESHOLD_LEN = 773; // 1
+static const uint64_t SH_FLD_0_STEP_CHECK_CONSTANT_CPS_ENABLE = 774; // 2
+static const uint64_t SH_FLD_0_STEP_CHECK_CPS_DEVIATION = 775; // 2
+static const uint64_t SH_FLD_0_STEP_CHECK_CPS_DEVIATION_LEN = 776; // 2
+static const uint64_t SH_FLD_0_STEP_CHECK_VALIDITY_COUNT = 777; // 2
+static const uint64_t SH_FLD_0_STEP_CHECK_VALIDITY_COUNT_LEN = 778; // 2
+static const uint64_t SH_FLD_0_STEP_STEER_ENABLE = 779; // 1
+static const uint64_t SH_FLD_1 = 780; // 525
+static const uint64_t SH_FLD_10 = 781; // 8
+static const uint64_t SH_FLD_10_RESERVED = 782; // 3
+static const uint64_t SH_FLD_10_SPARE_REFCLOCK = 783; // 3
+static const uint64_t SH_FLD_10_SPARE_SECTOR_BUFFER_CONTROL = 784; // 3
+static const uint64_t SH_FLD_11 = 785; // 8
+static const uint64_t SH_FLD_11_RESERVED = 786; // 3
+static const uint64_t SH_FLD_11_SPARE_REFCLOCK = 787; // 3
+static const uint64_t SH_FLD_11_SPARE_SECTOR_BUFFER_CONTROL = 788; // 3
+static const uint64_t SH_FLD_12 = 789; // 8
+static const uint64_t SH_FLD_12GB_ENABLE = 790; // 8
+static const uint64_t SH_FLD_12_RESERVED = 791; // 3
+static const uint64_t SH_FLD_12_SPARE_SECTOR_BUFFER_CONTROL = 792; // 3
+static const uint64_t SH_FLD_13 = 793; // 8
+static const uint64_t SH_FLD_13_RESERVED = 794; // 3
+static const uint64_t SH_FLD_13_SPARE_OPB_CONTROL = 795; // 3
+static const uint64_t SH_FLD_13_SPARE_PROBE = 796; // 3
+static const uint64_t SH_FLD_13_SPARE_SECTOR_BUFFER_CONTROL = 797; // 3
+static const uint64_t SH_FLD_14 = 798; // 8
+static const uint64_t SH_FLD_14_RESERVED = 799; // 3
+static const uint64_t SH_FLD_14_SPARE_OPB_CONTROL = 800; // 3
+static const uint64_t SH_FLD_14_SPARE_PLL = 801; // 3
+static const uint64_t SH_FLD_14_SPARE_PROBE = 802; // 3
+static const uint64_t SH_FLD_14_SPARE_SECTOR_BUFFER_CONTROL = 803; // 3
+static const uint64_t SH_FLD_15 = 804; // 8
+static const uint64_t SH_FLD_15_RESERVED = 805; // 3
+static const uint64_t SH_FLD_15_SPARE_OPB_CONTROL = 806; // 3
+static const uint64_t SH_FLD_15_SPARE_OSC = 807; // 3
+static const uint64_t SH_FLD_15_SPARE_PLL = 808; // 3
+static const uint64_t SH_FLD_15_SPARE_PROBE = 809; // 3
+static const uint64_t SH_FLD_15_SPARE_SECTOR_BUFFER_CONTROL = 810; // 3
+static const uint64_t SH_FLD_16 = 811; // 6
+static const uint64_t SH_FLD_16_SPARE_OSC = 812; // 3
+static const uint64_t SH_FLD_16_SPARE_RESONANT_CLOCKING_CONTROL = 813; // 3
+static const uint64_t SH_FLD_17 = 814; // 6
+static const uint64_t SH_FLD_17_SPARE_OSC = 815; // 3
+static const uint64_t SH_FLD_17_SPARE_RESONANT_CLOCKING_CONTROL = 816; // 3
+static const uint64_t SH_FLD_18 = 817; // 6
+static const uint64_t SH_FLD_18_31_SPARE = 818; // 8
+static const uint64_t SH_FLD_18_31_SPARE_LEN = 819; // 8
+static const uint64_t SH_FLD_18_SPARE_MUX_CONTROL = 820; // 3
+static const uint64_t SH_FLD_18_SPARE_OSC = 821; // 3
+static const uint64_t SH_FLD_18_SPARE_RESONANT_CLOCKING_CONTROL = 822; // 3
+static const uint64_t SH_FLD_19 = 823; // 6
+static const uint64_t SH_FLD_19_SPARE_MUX_CONTROL = 824; // 3
+static const uint64_t SH_FLD_19_SPARE_OSC = 825; // 3
+static const uint64_t SH_FLD_19_SPARE_RESONANT_CLOCKING_CONTROL = 826; // 3
+static const uint64_t SH_FLD_1_3 = 827; // 16
+static const uint64_t SH_FLD_1_CANNED_0 = 828; // 2
+static const uint64_t SH_FLD_1_CANNED_0_LEN = 829; // 2
+static const uint64_t SH_FLD_1_CANNED_1 = 830; // 2
+static const uint64_t SH_FLD_1_CANNED_1_LEN = 831; // 2
+static const uint64_t SH_FLD_1_CPS = 832; // 2
+static const uint64_t SH_FLD_1_CPS_LEN = 833; // 2
+static const uint64_t SH_FLD_1_DATA = 834; // 1
+static const uint64_t SH_FLD_1_DATA_LEN = 835; // 1
+static const uint64_t SH_FLD_1_LEN = 836; // 105
+static const uint64_t SH_FLD_1_LOCAL_STEP_MODE_ENABLE = 837; // 1
+static const uint64_t SH_FLD_1_OSC_NOT_VALID = 838; // 1
+static const uint64_t SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT = 839; // 1
+static const uint64_t SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT_LEN = 840; // 1
+static const uint64_t SH_FLD_1_RESULT = 841; // 43
+static const uint64_t SH_FLD_1_RESULT_LEN = 842; // 43
+static const uint64_t SH_FLD_1_SELECT = 843; // 1
+static const uint64_t SH_FLD_1_SELECT_LEN = 844; // 1
+static const uint64_t SH_FLD_1_SPARE_SECTOR_BUFFER_CONTROL = 845; // 3
+static const uint64_t SH_FLD_1_STEP_ALIGN_DISABLE = 846; // 1
+static const uint64_t SH_FLD_1_STEP_ALIGN_THRESHOLD = 847; // 1
+static const uint64_t SH_FLD_1_STEP_ALIGN_THRESHOLD_LEN = 848; // 1
+static const uint64_t SH_FLD_1_STEP_CHECK_CONSTANT_CPS_ENABLE = 849; // 2
+static const uint64_t SH_FLD_1_STEP_CHECK_CPS_DEVIATION = 850; // 2
+static const uint64_t SH_FLD_1_STEP_CHECK_CPS_DEVIATION_LEN = 851; // 2
+static const uint64_t SH_FLD_1_STEP_CHECK_VALIDITY_COUNT = 852; // 2
+static const uint64_t SH_FLD_1_STEP_CHECK_VALIDITY_COUNT_LEN = 853; // 2
+static const uint64_t SH_FLD_1_STEP_STEER_ENABLE = 854; // 1
+static const uint64_t SH_FLD_1_UNUSED = 855; // 1
+static const uint64_t SH_FLD_2 = 856; // 466
+static const uint64_t SH_FLD_20 = 857; // 6
+static const uint64_t SH_FLD_20_RESERVED = 858; // 3
+static const uint64_t SH_FLD_20_SPARE_OSC = 859; // 3
+static const uint64_t SH_FLD_20_SPARE_PLL_CONTROL = 860; // 3
+static const uint64_t SH_FLD_20_SPARE_RESONANT_CLOCKING_CONTROL = 861; // 3
+static const uint64_t SH_FLD_21 = 862; // 6
+static const uint64_t SH_FLD_21_FREE_USAGE = 863; // 3
+static const uint64_t SH_FLD_21_RESERVED = 864; // 3
+static const uint64_t SH_FLD_21_SPARE_OSC = 865; // 3
+static const uint64_t SH_FLD_21_SPARE_PLL_CONTROL = 866; // 3
+static const uint64_t SH_FLD_21_SPARE_RESONANT_CLOCKING_CONTROL = 867; // 3
+static const uint64_t SH_FLD_22 = 868; // 6
+static const uint64_t SH_FLD_22_FREE_USAGE = 869; // 3
+static const uint64_t SH_FLD_22_RESERVED = 870; // 6
+static const uint64_t SH_FLD_22_SPARE_OSC = 871; // 3
+static const uint64_t SH_FLD_22_SPARE_PLL_CONTROL = 872; // 3
+static const uint64_t SH_FLD_22_SPARE_RESONANT_CLOCKING_CONTROL = 873; // 3
+static const uint64_t SH_FLD_22_SPARE_TEST = 874; // 3
+static const uint64_t SH_FLD_23 = 875; // 134
+static const uint64_t SH_FLD_23_0_11 = 876; // 16
+static const uint64_t SH_FLD_23_0_11_LEN = 877; // 16
+static const uint64_t SH_FLD_23_12_15 = 878; // 16
+static const uint64_t SH_FLD_23_12_15_LEN = 879; // 16
+static const uint64_t SH_FLD_23_1D_EYE_NOISE = 880; // 16
+static const uint64_t SH_FLD_23_1D_EYE_NOISE_ERR0 = 881; // 16
+static const uint64_t SH_FLD_23_1D_EYE_NOISE_ERR1 = 882; // 16
+static const uint64_t SH_FLD_23_1D_EYE_NOISE_ERR2 = 883; // 16
+static const uint64_t SH_FLD_23_1D_EYE_NOISE_ERR3 = 884; // 16
+static const uint64_t SH_FLD_23_1D_EYE_NOISE_MASK1 = 885; // 16
+static const uint64_t SH_FLD_23_1D_EYE_NOISE_MASK2 = 886; // 16
+static const uint64_t SH_FLD_23_1D_EYE_NOISE_MASK3 = 887; // 16
+static const uint64_t SH_FLD_23_ADVANCE_PING_PONG = 888; // 16
+static const uint64_t SH_FLD_23_ADVANCE_PR_VALUE = 889; // 16
+static const uint64_t SH_FLD_23_ATESTSEL_0_4 = 890; // 16
+static const uint64_t SH_FLD_23_ATESTSEL_0_4_LEN = 891; // 16
+static const uint64_t SH_FLD_23_ATEST_SEL_0_1 = 892; // 16
+static const uint64_t SH_FLD_23_ATEST_SEL_0_1_LEN = 893; // 16
+static const uint64_t SH_FLD_23_BAD_BIT = 894; // 16
+static const uint64_t SH_FLD_23_BAD_BIT_ERR0 = 895; // 16
+static const uint64_t SH_FLD_23_BAD_BIT_ERR1 = 896; // 16
+static const uint64_t SH_FLD_23_BAD_BIT_ERR2 = 897; // 16
+static const uint64_t SH_FLD_23_BAD_BIT_ERR3 = 898; // 16
+static const uint64_t SH_FLD_23_BAD_BIT_MASK1 = 899; // 16
+static const uint64_t SH_FLD_23_BAD_BIT_MASK2 = 900; // 16
+static const uint64_t SH_FLD_23_BAD_BIT_MASK3 = 901; // 16
+static const uint64_t SH_FLD_23_BB_LOCK0 = 902; // 16
+static const uint64_t SH_FLD_23_BB_LOCK1 = 903; // 16
+static const uint64_t SH_FLD_23_BIG_STEP_RIGHT = 904; // 16
+static const uint64_t SH_FLD_23_BIT_CENTERED = 905; // 16
+static const uint64_t SH_FLD_23_BIT_CENTERED_LEN = 906; // 16
+static const uint64_t SH_FLD_23_BIT_STEP_DELTA = 907; // 16
+static const uint64_t SH_FLD_23_BIT_STEP_DELTA_ERR0 = 908; // 16
+static const uint64_t SH_FLD_23_BIT_STEP_DELTA_ERR1 = 909; // 16
+static const uint64_t SH_FLD_23_BIT_STEP_DELTA_ERR2 = 910; // 16
+static const uint64_t SH_FLD_23_BIT_STEP_DELTA_ERR3 = 911; // 16
+static const uint64_t SH_FLD_23_BIT_STEP_DELTA_MASK1 = 912; // 16
+static const uint64_t SH_FLD_23_BIT_STEP_DELTA_MASK2 = 913; // 16
+static const uint64_t SH_FLD_23_BIT_STEP_DELTA_MASK3 = 914; // 16
+static const uint64_t SH_FLD_23_BLFIFO_DIS = 915; // 16
+static const uint64_t SH_FLD_23_BUMP = 916; // 16
+static const uint64_t SH_FLD_23_CALGATE_ON = 917; // 16
+static const uint64_t SH_FLD_23_CALIBRATE_BIT = 918; // 16
+static const uint64_t SH_FLD_23_CALIBRATE_BIT_LEN = 919; // 16
+static const uint64_t SH_FLD_23_CAL_CKTS_ACTIVE = 920; // 32
+static const uint64_t SH_FLD_23_CAL_ERROR = 921; // 32
+static const uint64_t SH_FLD_23_CAL_ERROR_FINE = 922; // 32
+static const uint64_t SH_FLD_23_CAL_GOOD = 923; // 32
+static const uint64_t SH_FLD_23_CAL_PD_ENABLE = 924; // 32
+static const uint64_t SH_FLD_23_CHECKER_ENABLE = 925; // 16
+static const uint64_t SH_FLD_23_CHECKER_RESET = 926; // 16
+static const uint64_t SH_FLD_23_CHICKSW_HW278227 = 927; // 16
+static const uint64_t SH_FLD_23_CLK16_SINGLE_ENDED = 928; // 64
+static const uint64_t SH_FLD_23_CLK18_SINGLE_ENDED = 929; // 64
+static const uint64_t SH_FLD_23_CLK20_SINGLE_ENDED = 930; // 64
+static const uint64_t SH_FLD_23_CLK22_SINGLE_ENDED = 931; // 64
+static const uint64_t SH_FLD_23_CLK_LEVEL = 932; // 16
+static const uint64_t SH_FLD_23_CLK_LEVEL_LEN = 933; // 16
+static const uint64_t SH_FLD_23_CNTL_POL = 934; // 16
+static const uint64_t SH_FLD_23_CNTL_SRC = 935; // 16
+static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N0 = 936; // 16
+static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N0_MASK = 937; // 16
+static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N1 = 938; // 16
+static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N1_MASK = 939; // 16
+static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N2 = 940; // 16
+static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N2_MASK = 941; // 16
+static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N3 = 942; // 16
+static const uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N3_MASK = 943; // 16
+static const uint64_t SH_FLD_23_CONTINUOUS_UPDATE = 944; // 32
+static const uint64_t SH_FLD_23_CTR_1D_CHICKEN_SWITCH = 945; // 16
+static const uint64_t SH_FLD_23_CTR_2D_BIG_STEP_VAL = 946; // 16
+static const uint64_t SH_FLD_23_CTR_2D_BIG_STEP_VAL_LEN = 947; // 16
+static const uint64_t SH_FLD_23_CTR_2D_SMALL_STEP_VAL = 948; // 16
+static const uint64_t SH_FLD_23_CTR_2D_SMALL_STEP_VAL_LEN = 949; // 16
+static const uint64_t SH_FLD_23_CTR_CUR = 950; // 16
+static const uint64_t SH_FLD_23_CTR_CUR_LEN = 951; // 16
+static const uint64_t SH_FLD_23_CTR_NUM_BITS_TO_SKIP = 952; // 16
+static const uint64_t SH_FLD_23_CTR_NUM_BITS_TO_SKIP_LEN = 953; // 16
+static const uint64_t SH_FLD_23_CTR_NUM_NO_INC_COMP = 954; // 16
+static const uint64_t SH_FLD_23_CTR_NUM_NO_INC_COMP_LEN = 955; // 16
+static const uint64_t SH_FLD_23_CTR_NUM_VREFREQ_CNT = 956; // 16
+static const uint64_t SH_FLD_23_CTR_NUM_VREFREQ_CNT_LEN = 957; // 16
+static const uint64_t SH_FLD_23_CTR_NUM_WRRDREQ_CNT = 958; // 16
+static const uint64_t SH_FLD_23_CTR_NUM_WRRDREQ_CNT_LEN = 959; // 16
+static const uint64_t SH_FLD_23_CTR_RANGE_CROSSOVER = 960; // 16
+static const uint64_t SH_FLD_23_CTR_RANGE_CROSSOVER_LEN = 961; // 16
+static const uint64_t SH_FLD_23_CTR_RANGE_SELECT = 962; // 16
+static const uint64_t SH_FLD_23_CTR_RUN_FULL_1D = 963; // 16
+static const uint64_t SH_FLD_23_CTR_SINGLE_RANGE_MAX = 964; // 16
+static const uint64_t SH_FLD_23_CTR_SINGLE_RANGE_MAX_LEN = 965; // 16
+static const uint64_t SH_FLD_23_DD2_DQS_FIX_DIS = 966; // 16
+static const uint64_t SH_FLD_23_DD2_FIX_DIS = 967; // 16
+static const uint64_t SH_FLD_23_DD2_WTRFL_SYNC_DIS = 968; // 16
+static const uint64_t SH_FLD_23_DELAY1 = 969; // 16
+static const uint64_t SH_FLD_23_DELAY10 = 970; // 16
+static const uint64_t SH_FLD_23_DELAY10_LEN = 971; // 16
+static const uint64_t SH_FLD_23_DELAY11 = 972; // 16
+static const uint64_t SH_FLD_23_DELAY11_LEN = 973; // 16
+static const uint64_t SH_FLD_23_DELAY12 = 974; // 16
+static const uint64_t SH_FLD_23_DELAY12_LEN = 975; // 16
+static const uint64_t SH_FLD_23_DELAY13 = 976; // 16
+static const uint64_t SH_FLD_23_DELAY13_LEN = 977; // 16
+static const uint64_t SH_FLD_23_DELAY14 = 978; // 16
+static const uint64_t SH_FLD_23_DELAY14_LEN = 979; // 16
+static const uint64_t SH_FLD_23_DELAY15 = 980; // 16
+static const uint64_t SH_FLD_23_DELAY15_LEN = 981; // 16
+static const uint64_t SH_FLD_23_DELAY1_LEN = 982; // 16
+static const uint64_t SH_FLD_23_DELAY2 = 983; // 16
+static const uint64_t SH_FLD_23_DELAY2_LEN = 984; // 16
+static const uint64_t SH_FLD_23_DELAY3 = 985; // 16
+static const uint64_t SH_FLD_23_DELAY3_LEN = 986; // 16
+static const uint64_t SH_FLD_23_DELAY4 = 987; // 16
+static const uint64_t SH_FLD_23_DELAY4_LEN = 988; // 16
+static const uint64_t SH_FLD_23_DELAY5 = 989; // 16
+static const uint64_t SH_FLD_23_DELAY5_LEN = 990; // 16
+static const uint64_t SH_FLD_23_DELAY6 = 991; // 16
+static const uint64_t SH_FLD_23_DELAY6_LEN = 992; // 16
+static const uint64_t SH_FLD_23_DELAY7 = 993; // 16
+static const uint64_t SH_FLD_23_DELAY7_LEN = 994; // 16
+static const uint64_t SH_FLD_23_DELAY8 = 995; // 16
+static const uint64_t SH_FLD_23_DELAY8_LEN = 996; // 16
+static const uint64_t SH_FLD_23_DELAY9 = 997; // 16
+static const uint64_t SH_FLD_23_DELAY9_LEN = 998; // 16
+static const uint64_t SH_FLD_23_DELAYG = 999; // 1280
+static const uint64_t SH_FLD_23_DELAYG_LEN = 1000; // 1280
+static const uint64_t SH_FLD_23_DELAY_PING_PONG_HALF = 1001; // 16
+static const uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH = 1002; // 16
+static const uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 1003; // 16
+static const uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW = 1004; // 16
+static const uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 1005; // 16
+static const uint64_t SH_FLD_23_DETECT_REQ = 1006; // 32
+static const uint64_t SH_FLD_23_DFT_FORCE_OUTPUTS = 1007; // 16
+static const uint64_t SH_FLD_23_DFT_PRBS7_GEN_EN = 1008; // 16
+static const uint64_t SH_FLD_23_DIGITAL_EN = 1009; // 16
+static const uint64_t SH_FLD_23_DIR_0_15 = 1010; // 16
+static const uint64_t SH_FLD_23_DIR_0_15_LEN = 1011; // 16
+static const uint64_t SH_FLD_23_DISABLE_0_15 = 1012; // 64
+static const uint64_t SH_FLD_23_DISABLE_0_15_LEN = 1013; // 64
+static const uint64_t SH_FLD_23_DISABLE_16_23 = 1014; // 64
+static const uint64_t SH_FLD_23_DISABLE_16_23_LEN = 1015; // 64
+static const uint64_t SH_FLD_23_DISABLE_PING_PONG = 1016; // 16
+static const uint64_t SH_FLD_23_DISABLE_TERMINATION = 1017; // 16
+static const uint64_t SH_FLD_23_DIS_CLK_GATE = 1018; // 16
+static const uint64_t SH_FLD_23_DI_ADR0_ADR1 = 1019; // 16
+static const uint64_t SH_FLD_23_DI_ADR10_ADR11 = 1020; // 16
+static const uint64_t SH_FLD_23_DI_ADR12_ADR13 = 1021; // 16
+static const uint64_t SH_FLD_23_DI_ADR14_ADR15 = 1022; // 16
+static const uint64_t SH_FLD_23_DI_ADR2 = 1023; // 8
+static const uint64_t SH_FLD_23_DI_ADR3 = 1024; // 8
+static const uint64_t SH_FLD_23_DI_ADR4_ADR5 = 1025; // 16
+static const uint64_t SH_FLD_23_DI_ADR6_ADR7 = 1026; // 16
+static const uint64_t SH_FLD_23_DI_ADR8_ADR9 = 1027; // 16
+static const uint64_t SH_FLD_23_DLL_ADJUST = 1028; // 32
+static const uint64_t SH_FLD_23_DLL_ADJUST_LEN = 1029; // 32
+static const uint64_t SH_FLD_23_DLL_COMPARE_OUT = 1030; // 32
+static const uint64_t SH_FLD_23_DLL_CORRECT_EN = 1031; // 32
+static const uint64_t SH_FLD_23_DLL_ITER_A = 1032; // 32
+static const uint64_t SH_FLD_23_DL_FORCE_ON = 1033; // 16
+static const uint64_t SH_FLD_23_DONE = 1034; // 32
+static const uint64_t SH_FLD_23_DQS = 1035; // 16
+static const uint64_t SH_FLD_23_DQSCLK_SELECT0 = 1036; // 64
+static const uint64_t SH_FLD_23_DQSCLK_SELECT0_LEN = 1037; // 64
+static const uint64_t SH_FLD_23_DQSCLK_SELECT1 = 1038; // 64
+static const uint64_t SH_FLD_23_DQSCLK_SELECT1_LEN = 1039; // 64
+static const uint64_t SH_FLD_23_DQSCLK_SELECT2 = 1040; // 64
+static const uint64_t SH_FLD_23_DQSCLK_SELECT2_LEN = 1041; // 64
+static const uint64_t SH_FLD_23_DQSCLK_SELECT3 = 1042; // 64
+static const uint64_t SH_FLD_23_DQSCLK_SELECT3_LEN = 1043; // 64
+static const uint64_t SH_FLD_23_DQS_ALIGN_CNTR = 1044; // 16
+static const uint64_t SH_FLD_23_DQS_ALIGN_CNTR_LEN = 1045; // 16
+static const uint64_t SH_FLD_23_DQS_ALIGN_FIX_DIS = 1046; // 16
+static const uint64_t SH_FLD_23_DQS_ALIGN_JITTER = 1047; // 16
+static const uint64_t SH_FLD_23_DQS_ALIGN_QUAD = 1048; // 16
+static const uint64_t SH_FLD_23_DQS_ALIGN_QUAD_LEN = 1049; // 16
+static const uint64_t SH_FLD_23_DQS_ALIGN_SM = 1050; // 16
+static const uint64_t SH_FLD_23_DQS_ALIGN_SM_LEN = 1051; // 16
+static const uint64_t SH_FLD_23_DQS_LEN = 1052; // 16
+static const uint64_t SH_FLD_23_DQS_PIPE_FIX_DIS = 1053; // 16
+static const uint64_t SH_FLD_23_DQS_PIPE_FIX_DIS_LEN = 1054; // 16
+static const uint64_t SH_FLD_23_DQS_QUAD_CONFIG = 1055; // 16
+static const uint64_t SH_FLD_23_DQS_QUAD_CONFIG_LEN = 1056; // 16
+static const uint64_t SH_FLD_23_DRIFT_ERROR = 1057; // 16
+static const uint64_t SH_FLD_23_DRIFT_MASK = 1058; // 16
+static const uint64_t SH_FLD_23_DRVREN_MODE = 1059; // 32
+static const uint64_t SH_FLD_23_DYN_MCTERM_CNTL_EN = 1060; // 16
+static const uint64_t SH_FLD_23_DYN_POWER_CNTL_EN = 1061; // 16
+static const uint64_t SH_FLD_23_DYN_RX_GATE_CNTL_EN = 1062; // 16
+static const uint64_t SH_FLD_23_ENABLE_0_15 = 1063; // 16
+static const uint64_t SH_FLD_23_ENABLE_0_15_LEN = 1064; // 16
+static const uint64_t SH_FLD_23_ENABLE_16_23 = 1065; // 16
+static const uint64_t SH_FLD_23_ENABLE_16_23_LEN = 1066; // 16
+static const uint64_t SH_FLD_23_EN_DQS_OFFSET = 1067; // 16
+static const uint64_t SH_FLD_23_EN_DRIVER_INVFB_DC = 1068; // 32
+static const uint64_t SH_FLD_23_EN_N_WR = 1069; // 16
+static const uint64_t SH_FLD_23_EN_N_WR_LEN = 1070; // 16
+static const uint64_t SH_FLD_23_EN_P_WR = 1071; // 32
+static const uint64_t SH_FLD_23_EN_P_WR_LEN = 1072; // 32
+static const uint64_t SH_FLD_23_ERROR = 1073; // 16
+static const uint64_t SH_FLD_23_ERROR_LEN = 1074; // 16
+static const uint64_t SH_FLD_23_ERR_CLK22_MASK = 1075; // 16
+static const uint64_t SH_FLD_23_EYE_CLIPPING = 1076; // 16
+static const uint64_t SH_FLD_23_EYE_CLIPPING_MASK = 1077; // 16
+static const uint64_t SH_FLD_23_FINE_STEPPING = 1078; // 16
+static const uint64_t SH_FLD_23_FLUSH = 1079; // 16
+static const uint64_t SH_FLD_23_FORCE_DQS_LANES_ON = 1080; // 16
+static const uint64_t SH_FLD_23_FORCE_FIFO_CAPTURE = 1081; // 16
+static const uint64_t SH_FLD_23_FREE_USAGE = 1082; // 3
+static const uint64_t SH_FLD_23_FW_LEFT_SIDE = 1083; // 16
+static const uint64_t SH_FLD_23_FW_LEFT_SIDE_LEN = 1084; // 16
+static const uint64_t SH_FLD_23_FW_RIGHT_SIDE = 1085; // 16
+static const uint64_t SH_FLD_23_FW_RIGHT_SIDE_LEN = 1086; // 16
+static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0 = 1087; // 8
+static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0_3 = 1088; // 8
+static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0_3_LEN = 1089; // 8
+static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0_LEN = 1090; // 8
+static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0 = 1091; // 8
+static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0_3 = 1092; // 8
+static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0_3_LEN = 1093; // 8
+static const uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0_LEN = 1094; // 8
+static const uint64_t SH_FLD_23_HS_PROBE_A = 1095; // 16
+static const uint64_t SH_FLD_23_HS_PROBE_A_LEN = 1096; // 16
+static const uint64_t SH_FLD_23_HS_PROBE_B = 1097; // 16
+static const uint64_t SH_FLD_23_HS_PROBE_B_LEN = 1098; // 16
+static const uint64_t SH_FLD_23_HW_VALUE = 1099; // 16
+static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N0 = 1100; // 16
+static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N0_MASK = 1101; // 16
+static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N1 = 1102; // 16
+static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N1_MASK = 1103; // 16
+static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N2 = 1104; // 16
+static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N2_MASK = 1105; // 16
+static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N3 = 1106; // 16
+static const uint64_t SH_FLD_23_INCOMPLETE_CAL_N3_MASK = 1107; // 16
+static const uint64_t SH_FLD_23_INIT_IO = 1108; // 16
+static const uint64_t SH_FLD_23_INIT_RXDLL_CAL_RESET = 1109; // 32
+static const uint64_t SH_FLD_23_INIT_RXDLL_CAL_UPDATE = 1110; // 32
+static const uint64_t SH_FLD_23_INTERP_SIG_SLEW = 1111; // 16
+static const uint64_t SH_FLD_23_INTERP_SIG_SLEW_LEN = 1112; // 16
+static const uint64_t SH_FLD_23_INVALID_NS_BIG_R = 1113; // 16
+static const uint64_t SH_FLD_23_INVALID_NS_BIG_R_MASK = 1114; // 16
+static const uint64_t SH_FLD_23_INVALID_NS_SMALL_L = 1115; // 16
+static const uint64_t SH_FLD_23_INVALID_NS_SMALL_L_MASK = 1116; // 16
+static const uint64_t SH_FLD_23_INVALID_NS_SMALL_R = 1117; // 16
+static const uint64_t SH_FLD_23_INVALID_NS_SMALL_R_MASK = 1118; // 16
+static const uint64_t SH_FLD_23_ITERATION_CNTR = 1119; // 16
+static const uint64_t SH_FLD_23_ITERATION_CNTR_LEN = 1120; // 16
+static const uint64_t SH_FLD_23_JUMP_BACK_RIGHT = 1121; // 16
+static const uint64_t SH_FLD_23_LANE__0_11_PD = 1122; // 16
+static const uint64_t SH_FLD_23_LANE__0_11_PD_LEN = 1123; // 16
+static const uint64_t SH_FLD_23_LANE__12_15_PD = 1124; // 16
+static const uint64_t SH_FLD_23_LANE__12_15_PD_LEN = 1125; // 16
+static const uint64_t SH_FLD_23_LEADING_EDGE_FOUND_MASK = 1126; // 16
+static const uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND = 1127; // 16
+static const uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15 = 1128; // 16
+static const uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15_LEN = 1129; // 16
+static const uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23 = 1130; // 16
+static const uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23_LEN = 1131; // 16
+static const uint64_t SH_FLD_23_LEN = 1132; // 128
+static const uint64_t SH_FLD_23_LOOPBACK_DLY12 = 1133; // 16
+static const uint64_t SH_FLD_23_LOOPBACK_FIX_EN = 1134; // 16
+static const uint64_t SH_FLD_23_LOWER = 1135; // 32
+static const uint64_t SH_FLD_23_LOWER_LEN = 1136; // 32
+static const uint64_t SH_FLD_23_MAIN_PD_ENABLE = 1137; // 32
+static const uint64_t SH_FLD_23_MATCH_STEP_RIGHT = 1138; // 16
+static const uint64_t SH_FLD_23_MAX_DQS = 1139; // 16
+static const uint64_t SH_FLD_23_MAX_DQS_ITER = 1140; // 16
+static const uint64_t SH_FLD_23_MAX_DQS_LEN = 1141; // 16
+static const uint64_t SH_FLD_23_MAX_RANGE = 1142; // 16
+static const uint64_t SH_FLD_23_MAX_RANGE_ERR0 = 1143; // 16
+static const uint64_t SH_FLD_23_MAX_RANGE_ERR1 = 1144; // 16
+static const uint64_t SH_FLD_23_MAX_RANGE_ERR2 = 1145; // 16
+static const uint64_t SH_FLD_23_MAX_RANGE_ERR3 = 1146; // 16
+static const uint64_t SH_FLD_23_MAX_RANGE_MASK1 = 1147; // 16
+static const uint64_t SH_FLD_23_MAX_RANGE_MASK2 = 1148; // 16
+static const uint64_t SH_FLD_23_MAX_RANGE_MASK3 = 1149; // 16
+static const uint64_t SH_FLD_23_MEMINTD00 = 1150; // 16
+static const uint64_t SH_FLD_23_MEMINTD00_LEN = 1151; // 16
+static const uint64_t SH_FLD_23_MEMINTD01 = 1152; // 16
+static const uint64_t SH_FLD_23_MEMINTD01_LEN = 1153; // 16
+static const uint64_t SH_FLD_23_MEMINTD02 = 1154; // 16
+static const uint64_t SH_FLD_23_MEMINTD02_LEN = 1155; // 16
+static const uint64_t SH_FLD_23_MEMINTD03 = 1156; // 16
+static const uint64_t SH_FLD_23_MEMINTD03_LEN = 1157; // 16
+static const uint64_t SH_FLD_23_MEMINTD04 = 1158; // 16
+static const uint64_t SH_FLD_23_MEMINTD04_LEN = 1159; // 16
+static const uint64_t SH_FLD_23_MEMINTD05 = 1160; // 16
+static const uint64_t SH_FLD_23_MEMINTD05_LEN = 1161; // 16
+static const uint64_t SH_FLD_23_MEMINTD06 = 1162; // 16
+static const uint64_t SH_FLD_23_MEMINTD06_LEN = 1163; // 16
+static const uint64_t SH_FLD_23_MEMINTD07 = 1164; // 16
+static const uint64_t SH_FLD_23_MEMINTD07_LEN = 1165; // 16
+static const uint64_t SH_FLD_23_MEMINTD08 = 1166; // 16
+static const uint64_t SH_FLD_23_MEMINTD08_LEN = 1167; // 16
+static const uint64_t SH_FLD_23_MEMINTD09 = 1168; // 16
+static const uint64_t SH_FLD_23_MEMINTD09_LEN = 1169; // 16
+static const uint64_t SH_FLD_23_MEMINTD10 = 1170; // 16
+static const uint64_t SH_FLD_23_MEMINTD10_LEN = 1171; // 16
+static const uint64_t SH_FLD_23_MEMINTD11 = 1172; // 16
+static const uint64_t SH_FLD_23_MEMINTD11_LEN = 1173; // 16
+static const uint64_t SH_FLD_23_MEMINTD12 = 1174; // 16
+static const uint64_t SH_FLD_23_MEMINTD12_LEN = 1175; // 16
+static const uint64_t SH_FLD_23_MEMINTD13 = 1176; // 16
+static const uint64_t SH_FLD_23_MEMINTD13_LEN = 1177; // 16
+static const uint64_t SH_FLD_23_MEMINTD14 = 1178; // 16
+static const uint64_t SH_FLD_23_MEMINTD14_LEN = 1179; // 16
+static const uint64_t SH_FLD_23_MEMINTD15 = 1180; // 16
+static const uint64_t SH_FLD_23_MEMINTD15_LEN = 1181; // 16
+static const uint64_t SH_FLD_23_MEMINTD16 = 1182; // 16
+static const uint64_t SH_FLD_23_MEMINTD16_LEN = 1183; // 16
+static const uint64_t SH_FLD_23_MEMINTD17 = 1184; // 16
+static const uint64_t SH_FLD_23_MEMINTD17_LEN = 1185; // 16
+static const uint64_t SH_FLD_23_MEMINTD18 = 1186; // 16
+static const uint64_t SH_FLD_23_MEMINTD18_LEN = 1187; // 16
+static const uint64_t SH_FLD_23_MEMINTD19 = 1188; // 16
+static const uint64_t SH_FLD_23_MEMINTD19_LEN = 1189; // 16
+static const uint64_t SH_FLD_23_MEMINTD20 = 1190; // 16
+static const uint64_t SH_FLD_23_MEMINTD20_LEN = 1191; // 16
+static const uint64_t SH_FLD_23_MEMINTD21 = 1192; // 16
+static const uint64_t SH_FLD_23_MEMINTD21_LEN = 1193; // 16
+static const uint64_t SH_FLD_23_MEMINTD22 = 1194; // 16
+static const uint64_t SH_FLD_23_MEMINTD22_LEN = 1195; // 16
+static const uint64_t SH_FLD_23_MEMINTD23 = 1196; // 16
+static const uint64_t SH_FLD_23_MEMINTD23_LEN = 1197; // 16
+static const uint64_t SH_FLD_23_MIN_EYE = 1198; // 16
+static const uint64_t SH_FLD_23_MIN_EYE_MASK = 1199; // 16
+static const uint64_t SH_FLD_23_MIN_RANGE = 1200; // 16
+static const uint64_t SH_FLD_23_MIN_RANGE_ERR0 = 1201; // 16
+static const uint64_t SH_FLD_23_MIN_RANGE_ERR1 = 1202; // 16
+static const uint64_t SH_FLD_23_MIN_RANGE_ERR2 = 1203; // 16
+static const uint64_t SH_FLD_23_MIN_RANGE_ERR3 = 1204; // 16
+static const uint64_t SH_FLD_23_MIN_RANGE_MASK1 = 1205; // 16
+static const uint64_t SH_FLD_23_MIN_RANGE_MASK2 = 1206; // 16
+static const uint64_t SH_FLD_23_MIN_RANGE_MASK3 = 1207; // 16
+static const uint64_t SH_FLD_23_MIN_RD_EYE_SIZE = 1208; // 16
+static const uint64_t SH_FLD_23_MIN_RD_EYE_SIZE_LEN = 1209; // 16
+static const uint64_t SH_FLD_23_MRS_CMD_N0 = 1210; // 16
+static const uint64_t SH_FLD_23_MRS_CMD_N1 = 1211; // 16
+static const uint64_t SH_FLD_23_MRS_CMD_N2 = 1212; // 16
+static const uint64_t SH_FLD_23_MRS_CMD_N3 = 1213; // 16
+static const uint64_t SH_FLD_23_N0 = 1214; // 128
+static const uint64_t SH_FLD_23_N0_LEN = 1215; // 128
+static const uint64_t SH_FLD_23_N1 = 1216; // 128
+static const uint64_t SH_FLD_23_N1_LEN = 1217; // 128
+static const uint64_t SH_FLD_23_N2 = 1218; // 128
+static const uint64_t SH_FLD_23_N2_LEN = 1219; // 128
+static const uint64_t SH_FLD_23_N3 = 1220; // 128
+static const uint64_t SH_FLD_23_N3_LEN = 1221; // 128
+static const uint64_t SH_FLD_23_NIB0 = 1222; // 16
+static const uint64_t SH_FLD_23_NIB0TCFLIP_DC = 1223; // 16
+static const uint64_t SH_FLD_23_NIB0_EN_FORCE = 1224; // 16
+static const uint64_t SH_FLD_23_NIB0_LEN = 1225; // 16
+static const uint64_t SH_FLD_23_NIB1 = 1226; // 16
+static const uint64_t SH_FLD_23_NIB1TCFLIP_DC = 1227; // 16
+static const uint64_t SH_FLD_23_NIB1_EN_FORCE = 1228; // 16
+static const uint64_t SH_FLD_23_NIB1_LEN = 1229; // 16
+static const uint64_t SH_FLD_23_NIB2 = 1230; // 16
+static const uint64_t SH_FLD_23_NIB2TCFLIP_DC = 1231; // 16
+static const uint64_t SH_FLD_23_NIB2_EN_FORCE = 1232; // 16
+static const uint64_t SH_FLD_23_NIB2_LEN = 1233; // 16
+static const uint64_t SH_FLD_23_NIB3 = 1234; // 16
+static const uint64_t SH_FLD_23_NIB3TCFLIP_DC = 1235; // 16
+static const uint64_t SH_FLD_23_NIB3_EN_FORCE = 1236; // 16
+static const uint64_t SH_FLD_23_NIB3_LEN = 1237; // 16
+static const uint64_t SH_FLD_23_NIB_0_2_DQSEL_CAP = 1238; // 16
+static const uint64_t SH_FLD_23_NIB_0_2_DQSEL_CAP_LEN = 1239; // 16
+static const uint64_t SH_FLD_23_NIB_0_2_DQSEL_RES = 1240; // 16
+static const uint64_t SH_FLD_23_NIB_0_2_DQSEL_RES_LEN = 1241; // 16
+static const uint64_t SH_FLD_23_NIB_0_DQSEL_CAP = 1242; // 16
+static const uint64_t SH_FLD_23_NIB_0_DQSEL_CAP_LEN = 1243; // 16
+static const uint64_t SH_FLD_23_NIB_0_DQSEL_RES = 1244; // 16
+static const uint64_t SH_FLD_23_NIB_0_DQSEL_RES_LEN = 1245; // 16
+static const uint64_t SH_FLD_23_NIB_1_3_DQSEL_CAP = 1246; // 16
+static const uint64_t SH_FLD_23_NIB_1_3_DQSEL_CAP_LEN = 1247; // 16
+static const uint64_t SH_FLD_23_NIB_1_3_DQSEL_RES = 1248; // 16
+static const uint64_t SH_FLD_23_NIB_1_3_DQSEL_RES_LEN = 1249; // 16
+static const uint64_t SH_FLD_23_NIB_1_DQSEL_CAP = 1250; // 16
+static const uint64_t SH_FLD_23_NIB_1_DQSEL_CAP_LEN = 1251; // 16
+static const uint64_t SH_FLD_23_NIB_1_DQSEL_RES = 1252; // 16
+static const uint64_t SH_FLD_23_NIB_1_DQSEL_RES_LEN = 1253; // 16
+static const uint64_t SH_FLD_23_NO_DQS = 1254; // 16
+static const uint64_t SH_FLD_23_NO_DQS_MASK = 1255; // 16
+static const uint64_t SH_FLD_23_NO_EYE_DETECTED = 1256; // 16
+static const uint64_t SH_FLD_23_NO_EYE_DETECTED_MASK = 1257; // 16
+static const uint64_t SH_FLD_23_NO_INCREASE = 1258; // 16
+static const uint64_t SH_FLD_23_NO_INCREASE_ERR0 = 1259; // 16
+static const uint64_t SH_FLD_23_NO_INCREASE_ERR1 = 1260; // 16
+static const uint64_t SH_FLD_23_NO_INCREASE_ERR2 = 1261; // 16
+static const uint64_t SH_FLD_23_NO_INCREASE_ERR3 = 1262; // 16
+static const uint64_t SH_FLD_23_NO_INCREASE_MASK1 = 1263; // 16
+static const uint64_t SH_FLD_23_NO_INCREASE_MASK2 = 1264; // 16
+static const uint64_t SH_FLD_23_NO_INCREASE_MASK3 = 1265; // 16
+static const uint64_t SH_FLD_23_NO_LOCK = 1266; // 16
+static const uint64_t SH_FLD_23_NO_LOCK_MASK = 1267; // 16
+static const uint64_t SH_FLD_23_OFFSET0 = 1268; // 16
+static const uint64_t SH_FLD_23_OFFSET0_LEN = 1269; // 16
+static const uint64_t SH_FLD_23_OFFSET1 = 1270; // 16
+static const uint64_t SH_FLD_23_OFFSET1_LEN = 1271; // 16
+static const uint64_t SH_FLD_23_OFFSET2 = 1272; // 32
+static const uint64_t SH_FLD_23_OFFSET2_LEN = 1273; // 32
+static const uint64_t SH_FLD_23_OFFSET3 = 1274; // 32
+static const uint64_t SH_FLD_23_OFFSET3_LEN = 1275; // 32
+static const uint64_t SH_FLD_23_OFFSET4 = 1276; // 32
+static const uint64_t SH_FLD_23_OFFSET4_LEN = 1277; // 32
+static const uint64_t SH_FLD_23_OFFSET5 = 1278; // 32
+static const uint64_t SH_FLD_23_OFFSET5_LEN = 1279; // 32
+static const uint64_t SH_FLD_23_OFFSET6 = 1280; // 32
+static const uint64_t SH_FLD_23_OFFSET6_LEN = 1281; // 32
+static const uint64_t SH_FLD_23_OFFSET7 = 1282; // 32
+static const uint64_t SH_FLD_23_OFFSET7_LEN = 1283; // 32
+static const uint64_t SH_FLD_23_OFFSET_ERR = 1284; // 16
+static const uint64_t SH_FLD_23_OFFSET_ERR_MASK = 1285; // 16
+static const uint64_t SH_FLD_23_OPERATE_MODE = 1286; // 16
+static const uint64_t SH_FLD_23_OPERATE_MODE_LEN = 1287; // 16
+static const uint64_t SH_FLD_23_OVERRIDE = 1288; // 32
+static const uint64_t SH_FLD_23_PERCAL_PWR_DIS = 1289; // 16
+static const uint64_t SH_FLD_23_PER_CAL_UPDATE_DISABLE = 1290; // 16
+static const uint64_t SH_FLD_23_PHASE_ALIGN_RESET = 1291; // 32
+static const uint64_t SH_FLD_23_PHASE_CNTL_EN = 1292; // 32
+static const uint64_t SH_FLD_23_PHASE_DEFAULT_EN = 1293; // 32
+static const uint64_t SH_FLD_23_POS_EDGE_ALIGN = 1294; // 32
+static const uint64_t SH_FLD_23_QUAD0 = 1295; // 16
+static const uint64_t SH_FLD_23_QUAD0_CLK16 = 1296; // 128
+static const uint64_t SH_FLD_23_QUAD0_CLK18 = 1297; // 128
+static const uint64_t SH_FLD_23_QUAD0_LEN = 1298; // 16
+static const uint64_t SH_FLD_23_QUAD1 = 1299; // 16
+static const uint64_t SH_FLD_23_QUAD1_CLK16 = 1300; // 128
+static const uint64_t SH_FLD_23_QUAD1_CLK18 = 1301; // 128
+static const uint64_t SH_FLD_23_QUAD1_LEN = 1302; // 16
+static const uint64_t SH_FLD_23_QUAD2 = 1303; // 16
+static const uint64_t SH_FLD_23_QUAD2_CLK16 = 1304; // 64
+static const uint64_t SH_FLD_23_QUAD2_CLK18 = 1305; // 64
+static const uint64_t SH_FLD_23_QUAD2_CLK20 = 1306; // 128
+static const uint64_t SH_FLD_23_QUAD2_CLK22 = 1307; // 128
+static const uint64_t SH_FLD_23_QUAD2_LEN = 1308; // 16
+static const uint64_t SH_FLD_23_QUAD3 = 1309; // 16
+static const uint64_t SH_FLD_23_QUAD3_CLK16 = 1310; // 64
+static const uint64_t SH_FLD_23_QUAD3_CLK18 = 1311; // 64
+static const uint64_t SH_FLD_23_QUAD3_CLK20 = 1312; // 128
+static const uint64_t SH_FLD_23_QUAD3_CLK22 = 1313; // 128
+static const uint64_t SH_FLD_23_QUAD3_LEN = 1314; // 16
+static const uint64_t SH_FLD_23_RANGE_DRAM0 = 1315; // 64
+static const uint64_t SH_FLD_23_RANGE_DRAM1 = 1316; // 64
+static const uint64_t SH_FLD_23_RANGE_DRAM2 = 1317; // 64
+static const uint64_t SH_FLD_23_RANGE_DRAM3 = 1318; // 64
+static const uint64_t SH_FLD_23_RD = 1319; // 272
+static const uint64_t SH_FLD_23_RDCLK_SELECT0 = 1320; // 64
+static const uint64_t SH_FLD_23_RDCLK_SELECT0_LEN = 1321; // 64
+static const uint64_t SH_FLD_23_RDCLK_SELECT1 = 1322; // 64
+static const uint64_t SH_FLD_23_RDCLK_SELECT1_LEN = 1323; // 64
+static const uint64_t SH_FLD_23_RDCLK_SELECT2 = 1324; // 64
+static const uint64_t SH_FLD_23_RDCLK_SELECT2_LEN = 1325; // 64
+static const uint64_t SH_FLD_23_RDCLK_SELECT3 = 1326; // 64
+static const uint64_t SH_FLD_23_RDCLK_SELECT3_LEN = 1327; // 64
+static const uint64_t SH_FLD_23_RD_DELAY0 = 1328; // 112
+static const uint64_t SH_FLD_23_RD_DELAY0_LEN = 1329; // 112
+static const uint64_t SH_FLD_23_RD_DELAY1 = 1330; // 112
+static const uint64_t SH_FLD_23_RD_DELAY1_LEN = 1331; // 112
+static const uint64_t SH_FLD_23_RD_DELAY2 = 1332; // 112
+static const uint64_t SH_FLD_23_RD_DELAY2_LEN = 1333; // 112
+static const uint64_t SH_FLD_23_RD_DELAY3 = 1334; // 112
+static const uint64_t SH_FLD_23_RD_DELAY3_LEN = 1335; // 112
+static const uint64_t SH_FLD_23_RD_DELAY4 = 1336; // 112
+static const uint64_t SH_FLD_23_RD_DELAY4_LEN = 1337; // 112
+static const uint64_t SH_FLD_23_RD_DELAY5 = 1338; // 112
+static const uint64_t SH_FLD_23_RD_DELAY5_LEN = 1339; // 112
+static const uint64_t SH_FLD_23_RD_DELAY6 = 1340; // 112
+static const uint64_t SH_FLD_23_RD_DELAY6_LEN = 1341; // 112
+static const uint64_t SH_FLD_23_RD_DELAY7 = 1342; // 112
+static const uint64_t SH_FLD_23_RD_DELAY7_LEN = 1343; // 112
+static const uint64_t SH_FLD_23_RD_LEN = 1344; // 272
+static const uint64_t SH_FLD_23_RD_SIZE0 = 1345; // 176
+static const uint64_t SH_FLD_23_RD_SIZE0_LEN = 1346; // 176
+static const uint64_t SH_FLD_23_RD_SIZE1 = 1347; // 176
+static const uint64_t SH_FLD_23_RD_SIZE1_LEN = 1348; // 176
+static const uint64_t SH_FLD_23_RD_SIZE2 = 1349; // 176
+static const uint64_t SH_FLD_23_RD_SIZE2_LEN = 1350; // 176
+static const uint64_t SH_FLD_23_RD_SIZE3 = 1351; // 176
+static const uint64_t SH_FLD_23_RD_SIZE3_LEN = 1352; // 176
+static const uint64_t SH_FLD_23_RD_SIZE4 = 1353; // 176
+static const uint64_t SH_FLD_23_RD_SIZE4_LEN = 1354; // 176
+static const uint64_t SH_FLD_23_RD_SIZE5 = 1355; // 176
+static const uint64_t SH_FLD_23_RD_SIZE5_LEN = 1356; // 176
+static const uint64_t SH_FLD_23_RD_SIZE6 = 1357; // 176
+static const uint64_t SH_FLD_23_RD_SIZE6_LEN = 1358; // 176
+static const uint64_t SH_FLD_23_RD_SIZE7 = 1359; // 176
+static const uint64_t SH_FLD_23_RD_SIZE7_LEN = 1360; // 176
+static const uint64_t SH_FLD_23_READ_CENTERING_MODE = 1361; // 16
+static const uint64_t SH_FLD_23_READ_CENTERING_MODE_LEN = 1362; // 16
+static const uint64_t SH_FLD_23_REFERENCE1 = 1363; // 16
+static const uint64_t SH_FLD_23_REFERENCE1_LEN = 1364; // 16
+static const uint64_t SH_FLD_23_REFERENCE2 = 1365; // 16
+static const uint64_t SH_FLD_23_REFERENCE2_LEN = 1366; // 16
+static const uint64_t SH_FLD_23_REFERENCE3 = 1367; // 16
+static const uint64_t SH_FLD_23_REFERENCE3_LEN = 1368; // 16
+static const uint64_t SH_FLD_23_REGS_RXDLL_CAL_SKIP = 1369; // 32
+static const uint64_t SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN = 1370; // 32
+static const uint64_t SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 = 1371; // 32
+static const uint64_t SH_FLD_23_REGS_RXDLL_COARSE_EN = 1372; // 32
+static const uint64_t SH_FLD_23_REGS_RXDLL_COARSE_EN_LEN = 1373; // 32
+static const uint64_t SH_FLD_23_REGS_RXDLL_DAC_COARSE = 1374; // 32
+static const uint64_t SH_FLD_23_REGS_RXDLL_DAC_COARSE_LEN = 1375; // 32
+static const uint64_t SH_FLD_23_REGS_RXDLL_VREG_LOWER = 1376; // 32
+static const uint64_t SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN = 1377; // 32
+static const uint64_t SH_FLD_23_REGS_RXDLL_VREG_UPPER = 1378; // 32
+static const uint64_t SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN = 1379; // 32
+static const uint64_t SH_FLD_23_RESERVED = 1380; // 6
+static const uint64_t SH_FLD_23_ROT0 = 1381; // 16
+static const uint64_t SH_FLD_23_ROT0_LEN = 1382; // 16
+static const uint64_t SH_FLD_23_ROT1 = 1383; // 16
+static const uint64_t SH_FLD_23_ROT1_LEN = 1384; // 16
+static const uint64_t SH_FLD_23_ROT_CLK_N0 = 1385; // 128
+static const uint64_t SH_FLD_23_ROT_CLK_N0_LEN = 1386; // 128
+static const uint64_t SH_FLD_23_ROT_CLK_N1 = 1387; // 128
+static const uint64_t SH_FLD_23_ROT_CLK_N1_LEN = 1388; // 128
+static const uint64_t SH_FLD_23_ROT_N0 = 1389; // 128
+static const uint64_t SH_FLD_23_ROT_N0_LEN = 1390; // 128
+static const uint64_t SH_FLD_23_ROT_N1 = 1391; // 128
+static const uint64_t SH_FLD_23_ROT_N1_LEN = 1392; // 128
+static const uint64_t SH_FLD_23_ROT_OVERRIDE = 1393; // 32
+static const uint64_t SH_FLD_23_ROT_OVERRIDE_EN = 1394; // 32
+static const uint64_t SH_FLD_23_ROT_OVERRIDE_LEN = 1395; // 32
+static const uint64_t SH_FLD_23_RXCAL_DETECT_DONE_META = 1396; // 32
+static const uint64_t SH_FLD_23_RXCAL_PD_CAL_LAG_META = 1397; // 32
+static const uint64_t SH_FLD_23_RXCAL_PD_MAIN_LAG_META = 1398; // 32
+static const uint64_t SH_FLD_23_RXCAL_PD_MAIN_LEAD_META = 1399; // 32
+static const uint64_t SH_FLD_23_RXREG_COMPCON_DC = 1400; // 32
+static const uint64_t SH_FLD_23_RXREG_COMPCON_DC_LEN = 1401; // 32
+static const uint64_t SH_FLD_23_RXREG_CON_DC = 1402; // 32
+static const uint64_t SH_FLD_23_RXREG_DAC_PULLUP_DC = 1403; // 32
+static const uint64_t SH_FLD_23_RXREG_DRVCON_DC = 1404; // 32
+static const uint64_t SH_FLD_23_RXREG_DRVCON_DC_LEN = 1405; // 32
+static const uint64_t SH_FLD_23_RXREG_FILTER_LENGTH_DC = 1406; // 32
+static const uint64_t SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN = 1407; // 32
+static const uint64_t SH_FLD_23_RXREG_FINECAL_2XILSB_DC = 1408; // 32
+static const uint64_t SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC = 1409; // 32
+static const uint64_t SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 1410; // 32
+static const uint64_t SH_FLD_23_RXREG_REF_SEL_DC = 1411; // 32
+static const uint64_t SH_FLD_23_RXREG_REF_SEL_DC_LEN = 1412; // 32
+static const uint64_t SH_FLD_23_S0ACENSLICENDRV_DC = 1413; // 16
+static const uint64_t SH_FLD_23_S0ACENSLICENDRV_DC_LEN = 1414; // 16
+static const uint64_t SH_FLD_23_S0ACENSLICEPDRV_DC = 1415; // 16
+static const uint64_t SH_FLD_23_S0ACENSLICEPDRV_DC_LEN = 1416; // 16
+static const uint64_t SH_FLD_23_S0ACENSLICEPTERM_DC = 1417; // 16
+static const uint64_t SH_FLD_23_S0ACENSLICEPTERM_DC_LEN = 1418; // 16
+static const uint64_t SH_FLD_23_S0INSDLYTAP = 1419; // 16
+static const uint64_t SH_FLD_23_S1ACENSLICENDRV_DC = 1420; // 16
+static const uint64_t SH_FLD_23_S1ACENSLICENDRV_DC_LEN = 1421; // 16
+static const uint64_t SH_FLD_23_S1ACENSLICEPDRV_DC = 1422; // 16
+static const uint64_t SH_FLD_23_S1ACENSLICEPDRV_DC_LEN = 1423; // 16
+static const uint64_t SH_FLD_23_S1ACENSLICEPTERM_DC = 1424; // 16
+static const uint64_t SH_FLD_23_S1ACENSLICEPTERM_DC_LEN = 1425; // 16
+static const uint64_t SH_FLD_23_S1INSDLYTAP = 1426; // 16
+static const uint64_t SH_FLD_23_SEL0 = 1427; // 32
+static const uint64_t SH_FLD_23_SEL0_LEN = 1428; // 16
+static const uint64_t SH_FLD_23_SEL1 = 1429; // 32
+static const uint64_t SH_FLD_23_SEL10 = 1430; // 32
+static const uint64_t SH_FLD_23_SEL10_LEN = 1431; // 32
+static const uint64_t SH_FLD_23_SEL11 = 1432; // 32
+static const uint64_t SH_FLD_23_SEL11_LEN = 1433; // 32
+static const uint64_t SH_FLD_23_SEL12 = 1434; // 32
+static const uint64_t SH_FLD_23_SEL12_LEN = 1435; // 32
+static const uint64_t SH_FLD_23_SEL13 = 1436; // 32
+static const uint64_t SH_FLD_23_SEL13_LEN = 1437; // 32
+static const uint64_t SH_FLD_23_SEL14 = 1438; // 32
+static const uint64_t SH_FLD_23_SEL14_LEN = 1439; // 32
+static const uint64_t SH_FLD_23_SEL15 = 1440; // 32
+static const uint64_t SH_FLD_23_SEL15_LEN = 1441; // 32
+static const uint64_t SH_FLD_23_SEL1_LEN = 1442; // 32
+static const uint64_t SH_FLD_23_SEL2 = 1443; // 32
+static const uint64_t SH_FLD_23_SEL2_LEN = 1444; // 32
+static const uint64_t SH_FLD_23_SEL3 = 1445; // 32
+static const uint64_t SH_FLD_23_SEL3_LEN = 1446; // 32
+static const uint64_t SH_FLD_23_SEL4 = 1447; // 32
+static const uint64_t SH_FLD_23_SEL4_LEN = 1448; // 32
+static const uint64_t SH_FLD_23_SEL5 = 1449; // 32
+static const uint64_t SH_FLD_23_SEL5_LEN = 1450; // 32
+static const uint64_t SH_FLD_23_SEL6 = 1451; // 32
+static const uint64_t SH_FLD_23_SEL6_LEN = 1452; // 32
+static const uint64_t SH_FLD_23_SEL7 = 1453; // 32
+static const uint64_t SH_FLD_23_SEL7_LEN = 1454; // 32
+static const uint64_t SH_FLD_23_SEL8 = 1455; // 32
+static const uint64_t SH_FLD_23_SEL8_LEN = 1456; // 16
+static const uint64_t SH_FLD_23_SEL9 = 1457; // 32
+static const uint64_t SH_FLD_23_SEL9_LEN = 1458; // 32
+static const uint64_t SH_FLD_23_SEL_A = 1459; // 16
+static const uint64_t SH_FLD_23_SEL_A_LEN = 1460; // 16
+static const uint64_t SH_FLD_23_SEL_B = 1461; // 16
+static const uint64_t SH_FLD_23_SEL_B_LEN = 1462; // 16
+static const uint64_t SH_FLD_23_SLAVE_CAL_CKT_POWERDOWN = 1463; // 32
+static const uint64_t SH_FLD_23_SLAVE_VREG_DAC_COARSE = 1464; // 32
+static const uint64_t SH_FLD_23_SLAVE_VREG_DAC_COARSE_LEN = 1465; // 32
+static const uint64_t SH_FLD_23_SLAVE_VREG_OVERRIDE = 1466; // 32
+static const uint64_t SH_FLD_23_SLAVE_VREG_REF_SEL_DC = 1467; // 32
+static const uint64_t SH_FLD_23_SLAVE_VREG_REF_SEL_DC_LEN = 1468; // 32
+static const uint64_t SH_FLD_23_SMALL_STEP_LEFT = 1469; // 16
+static const uint64_t SH_FLD_23_SMALL_STEP_RIGHT = 1470; // 16
+static const uint64_t SH_FLD_23_SPARE_OSC = 1471; // 3
+static const uint64_t SH_FLD_23_SPARE_PLL_CONTROL = 1472; // 3
+static const uint64_t SH_FLD_23_SPARE_RESONANT_CLOCKING_CONTROL = 1473; // 3
+static const uint64_t SH_FLD_23_SPARE_TEST = 1474; // 3
+static const uint64_t SH_FLD_23_STEP_RANGE_EDGE = 1475; // 16
+static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_ERR0 = 1476; // 16
+static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_ERR1 = 1477; // 16
+static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_ERR2 = 1478; // 16
+static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_ERR3 = 1479; // 16
+static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_MASK1 = 1480; // 16
+static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_MASK2 = 1481; // 16
+static const uint64_t SH_FLD_23_STEP_RANGE_EDGE_MASK3 = 1482; // 16
+static const uint64_t SH_FLD_23_SYNC = 1483; // 16
+static const uint64_t SH_FLD_23_SYNC_LEN = 1484; // 16
+static const uint64_t SH_FLD_23_SYSCLK_DQSCLK_OFFSET = 1485; // 16
+static const uint64_t SH_FLD_23_SYSCLK_DQSCLK_OFFSET_LEN = 1486; // 16
+static const uint64_t SH_FLD_23_SYSCLK_RDCLK_OFFSET = 1487; // 16
+static const uint64_t SH_FLD_23_SYSCLK_RDCLK_OFFSET_LEN = 1488; // 16
+static const uint64_t SH_FLD_23_TEST_4TO1_MODE = 1489; // 16
+static const uint64_t SH_FLD_23_TEST_CHECK_EN = 1490; // 16
+static const uint64_t SH_FLD_23_TEST_CLEAR_ERROR = 1491; // 16
+static const uint64_t SH_FLD_23_TEST_DATA_EN = 1492; // 16
+static const uint64_t SH_FLD_23_TEST_GEN_EN = 1493; // 16
+static const uint64_t SH_FLD_23_TEST_LANE_PAIR_FAIL = 1494; // 16
+static const uint64_t SH_FLD_23_TEST_LANE_PAIR_FAIL_LEN = 1495; // 16
+static const uint64_t SH_FLD_23_TEST_MODE = 1496; // 16
+static const uint64_t SH_FLD_23_TEST_MODE_LEN = 1497; // 16
+static const uint64_t SH_FLD_23_TEST_RESET = 1498; // 16
+static const uint64_t SH_FLD_23_TRAILING_EDGE_FOUND_MASK = 1499; // 16
+static const uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND = 1500; // 16
+static const uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15 = 1501; // 16
+static const uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 1502; // 16
+static const uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23 = 1503; // 16
+static const uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 1504; // 16
+static const uint64_t SH_FLD_23_TRIG_PERIOD = 1505; // 16
+static const uint64_t SH_FLD_23_TSYS = 1506; // 16
+static const uint64_t SH_FLD_23_TSYS_LEN = 1507; // 16
+static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE = 1508; // 16
+static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_ERR0 = 1509; // 16
+static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_ERR1 = 1510; // 16
+static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_ERR2 = 1511; // 16
+static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_ERR3 = 1512; // 16
+static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_MASK1 = 1513; // 16
+static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_MASK2 = 1514; // 16
+static const uint64_t SH_FLD_23_TWO_RANGE_BEST_CASE_MASK3 = 1515; // 16
+static const uint64_t SH_FLD_23_UPPER = 1516; // 32
+static const uint64_t SH_FLD_23_UPPER_LEN = 1517; // 32
+static const uint64_t SH_FLD_23_VALID_NS_BIG_L = 1518; // 16
+static const uint64_t SH_FLD_23_VALID_NS_BIG_L_MASK = 1519; // 16
+static const uint64_t SH_FLD_23_VALID_NS_BIG_R = 1520; // 16
+static const uint64_t SH_FLD_23_VALID_NS_BIG_R_MASK = 1521; // 16
+static const uint64_t SH_FLD_23_VALID_NS_JUMP_BACK = 1522; // 16
+static const uint64_t SH_FLD_23_VALID_NS_JUMP_BACK_MASK = 1523; // 16
+static const uint64_t SH_FLD_23_VALUE_DRAM0 = 1524; // 64
+static const uint64_t SH_FLD_23_VALUE_DRAM0_LEN = 1525; // 64
+static const uint64_t SH_FLD_23_VALUE_DRAM1 = 1526; // 64
+static const uint64_t SH_FLD_23_VALUE_DRAM1_LEN = 1527; // 64
+static const uint64_t SH_FLD_23_VALUE_DRAM2 = 1528; // 64
+static const uint64_t SH_FLD_23_VALUE_DRAM2_LEN = 1529; // 64
+static const uint64_t SH_FLD_23_VALUE_DRAM3 = 1530; // 64
+static const uint64_t SH_FLD_23_VALUE_DRAM3_LEN = 1531; // 64
+static const uint64_t SH_FLD_23_VREG_RXCAL_COMP_OUT_META = 1532; // 32
+static const uint64_t SH_FLD_23_VREG_SLAVE_COMP_OUT = 1533; // 32
+static const uint64_t SH_FLD_23_WL_ADVANCE_DISABLE = 1534; // 16
+static const uint64_t SH_FLD_23_WL_ERR_CLK16 = 1535; // 32
+static const uint64_t SH_FLD_23_WL_ERR_CLK16_MASK = 1536; // 16
+static const uint64_t SH_FLD_23_WL_ERR_CLK18 = 1537; // 32
+static const uint64_t SH_FLD_23_WL_ERR_CLK18_MASK = 1538; // 16
+static const uint64_t SH_FLD_23_WL_ERR_CLK20 = 1539; // 32
+static const uint64_t SH_FLD_23_WL_ERR_CLK20_MASK = 1540; // 16
+static const uint64_t SH_FLD_23_WL_ERR_CLK22 = 1541; // 32
+static const uint64_t SH_FLD_23_WRAPSEL = 1542; // 16
+static const uint64_t SH_FLD_23_WTRFL_AVE_DIS = 1543; // 16
+static const uint64_t SH_FLD_23_ZERO_DETECTED = 1544; // 16
+static const uint64_t SH_FLD_24 = 1545; // 6
+static const uint64_t SH_FLD_24_RESERVED = 1546; // 6
+static const uint64_t SH_FLD_24_SPARE_CBS_CONTROL = 1547; // 3
+static const uint64_t SH_FLD_24_SPARE_OSC = 1548; // 3
+static const uint64_t SH_FLD_24_SPARE_RESONANT_CLOCKING_CONTROL = 1549; // 3
+static const uint64_t SH_FLD_25 = 1550; // 6
+static const uint64_t SH_FLD_256K = 1551; // 12
+static const uint64_t SH_FLD_25_SPARE_CBS_CONTROL = 1552; // 3
+static const uint64_t SH_FLD_25_SPARE_CLKIN_CONTROL = 1553; // 3
+static const uint64_t SH_FLD_25_SPARE_OSC = 1554; // 3
+static const uint64_t SH_FLD_25_SPARE_REFCLOCK_CONTROL = 1555; // 3
+static const uint64_t SH_FLD_25_SPARE_RESONANT_CLOCKING_CONTROL = 1556; // 3
+static const uint64_t SH_FLD_26 = 1557; // 6
+static const uint64_t SH_FLD_26_FREE_USAGE = 1558; // 3
+static const uint64_t SH_FLD_26_SPARE_CBS_CONTROL = 1559; // 3
+static const uint64_t SH_FLD_26_SPARE_CLKIN_CONTROL = 1560; // 3
+static const uint64_t SH_FLD_26_SPARE_OSC = 1561; // 3
+static const uint64_t SH_FLD_26_SPARE_REFCLOCK_CONTROL = 1562; // 3
+static const uint64_t SH_FLD_26_SPARE_RESONANT_CLOCKING_CONTROL = 1563; // 3
+static const uint64_t SH_FLD_27 = 1564; // 6
+static const uint64_t SH_FLD_27_FREE_USAGE = 1565; // 3
+static const uint64_t SH_FLD_27_SPARE_CBS_CONTROL = 1566; // 3
+static const uint64_t SH_FLD_27_SPARE_CLKIN_CONTROL = 1567; // 3
+static const uint64_t SH_FLD_27_SPARE_OSC = 1568; // 3
+static const uint64_t SH_FLD_27_SPARE_RESONANT_CLOCKING_CONTROL = 1569; // 3
+static const uint64_t SH_FLD_28 = 1570; // 6
+static const uint64_t SH_FLD_28_FREE_USAGE = 1571; // 3
+static const uint64_t SH_FLD_28_RESERVED_FOR_HTB = 1572; // 3
+static const uint64_t SH_FLD_28_SPARE_OSC = 1573; // 3
+static const uint64_t SH_FLD_28_SPARE_RESET = 1574; // 3
+static const uint64_t SH_FLD_28_SPARE_RESONANT_CLOCKING_CONTROL = 1575; // 3
+static const uint64_t SH_FLD_28_SPARE_TEST_CONTROL = 1576; // 3
+static const uint64_t SH_FLD_29 = 1577; // 6
+static const uint64_t SH_FLD_29_FREE_USAGE = 1578; // 3
+static const uint64_t SH_FLD_29_RESERVED_FOR_HTB = 1579; // 3
+static const uint64_t SH_FLD_29_SPARE_OSC = 1580; // 3
+static const uint64_t SH_FLD_29_SPARE_REFCLOCK_CONTROL = 1581; // 3
+static const uint64_t SH_FLD_29_SPARE_RESET = 1582; // 3
+static const uint64_t SH_FLD_29_SPARE_RESONANT_CLOCKING_CONTROL = 1583; // 3
+static const uint64_t SH_FLD_29_SPARE_TEST_CONTROL = 1584; // 3
+static const uint64_t SH_FLD_2_CANNED_0 = 1585; // 2
+static const uint64_t SH_FLD_2_CANNED_0_LEN = 1586; // 2
+static const uint64_t SH_FLD_2_CANNED_1 = 1587; // 2
+static const uint64_t SH_FLD_2_CANNED_1_LEN = 1588; // 2
+static const uint64_t SH_FLD_2_DATA = 1589; // 1
+static const uint64_t SH_FLD_2_DATA_LEN = 1590; // 1
+static const uint64_t SH_FLD_2_LEN = 1591; // 46
+static const uint64_t SH_FLD_2_RESERVED = 1592; // 3
+static const uint64_t SH_FLD_2_SPARE_SECTOR_BUFFER_CONTROL = 1593; // 3
+static const uint64_t SH_FLD_3 = 1594; // 466
+static const uint64_t SH_FLD_30 = 1595; // 6
+static const uint64_t SH_FLD_30_RESERVED = 1596; // 3
+static const uint64_t SH_FLD_30_RESERVED_FOR_HTB = 1597; // 3
+static const uint64_t SH_FLD_30_SPARE_OSC = 1598; // 3
+static const uint64_t SH_FLD_30_SPARE_REFCLOCK_CONTROL = 1599; // 3
+static const uint64_t SH_FLD_30_SPARE_RESONANT_CLOCKING_CONTROL = 1600; // 3
+static const uint64_t SH_FLD_30_SPARE_TEST_CONTROL = 1601; // 3
+static const uint64_t SH_FLD_31 = 1602; // 6
+static const uint64_t SH_FLD_31_RESERVED_FOR_HTB = 1603; // 3
+static const uint64_t SH_FLD_31_SPARE_OSC = 1604; // 3
+static const uint64_t SH_FLD_31_SPARE_REFCLOCK_CONTROL = 1605; // 3
+static const uint64_t SH_FLD_31_SPARE_RESONANT_CLOCKING_CONTROL = 1606; // 3
+static const uint64_t SH_FLD_31_SPARE_TEST_CONTROL = 1607; // 3
+static const uint64_t SH_FLD_3_DATA = 1608; // 1
+static const uint64_t SH_FLD_3_DATA_LEN = 1609; // 1
+static const uint64_t SH_FLD_3_LEN = 1610; // 46
+static const uint64_t SH_FLD_3_RESERVED = 1611; // 3
+static const uint64_t SH_FLD_3_SPARE_SECTOR_BUFFER_CONTROL = 1612; // 3
+static const uint64_t SH_FLD_3_SPARE_SS_PLL_CONTROL = 1613; // 3
+static const uint64_t SH_FLD_4 = 1614; // 520
+static const uint64_t SH_FLD_4X4_MODE = 1615; // 2
+static const uint64_t SH_FLD_4_1D_EYE_NOISE = 1616; // 8
+static const uint64_t SH_FLD_4_1D_EYE_NOISE_ERR0 = 1617; // 8
+static const uint64_t SH_FLD_4_1D_EYE_NOISE_ERR1 = 1618; // 8
+static const uint64_t SH_FLD_4_1D_EYE_NOISE_ERR2 = 1619; // 8
+static const uint64_t SH_FLD_4_1D_EYE_NOISE_ERR3 = 1620; // 8
+static const uint64_t SH_FLD_4_1D_EYE_NOISE_MASK1 = 1621; // 8
+static const uint64_t SH_FLD_4_1D_EYE_NOISE_MASK2 = 1622; // 8
+static const uint64_t SH_FLD_4_1D_EYE_NOISE_MASK3 = 1623; // 8
+static const uint64_t SH_FLD_4_ADVANCE_PING_PONG = 1624; // 8
+static const uint64_t SH_FLD_4_ADVANCE_PR_VALUE = 1625; // 8
+static const uint64_t SH_FLD_4_ATESTSEL_0 = 1626; // 8
+static const uint64_t SH_FLD_4_ATESTSEL_0_LEN = 1627; // 8
+static const uint64_t SH_FLD_4_ATEST_SEL_0_1 = 1628; // 8
+static const uint64_t SH_FLD_4_ATEST_SEL_0_1_LEN = 1629; // 8
+static const uint64_t SH_FLD_4_BAD_BIT = 1630; // 8
+static const uint64_t SH_FLD_4_BAD_BIT_ERR0 = 1631; // 8
+static const uint64_t SH_FLD_4_BAD_BIT_ERR1 = 1632; // 8
+static const uint64_t SH_FLD_4_BAD_BIT_ERR2 = 1633; // 8
+static const uint64_t SH_FLD_4_BAD_BIT_ERR3 = 1634; // 8
+static const uint64_t SH_FLD_4_BAD_BIT_MASK1 = 1635; // 8
+static const uint64_t SH_FLD_4_BAD_BIT_MASK2 = 1636; // 8
+static const uint64_t SH_FLD_4_BAD_BIT_MASK3 = 1637; // 8
+static const uint64_t SH_FLD_4_BB_LOCK0 = 1638; // 8
+static const uint64_t SH_FLD_4_BB_LOCK1 = 1639; // 8
+static const uint64_t SH_FLD_4_BIG_STEP_RIGHT = 1640; // 8
+static const uint64_t SH_FLD_4_BIT_CENTERED = 1641; // 8
+static const uint64_t SH_FLD_4_BIT_CENTERED_LEN = 1642; // 8
+static const uint64_t SH_FLD_4_BIT_STEP_DELTA = 1643; // 8
+static const uint64_t SH_FLD_4_BIT_STEP_DELTA_ERR0 = 1644; // 8
+static const uint64_t SH_FLD_4_BIT_STEP_DELTA_ERR1 = 1645; // 8
+static const uint64_t SH_FLD_4_BIT_STEP_DELTA_ERR2 = 1646; // 8
+static const uint64_t SH_FLD_4_BIT_STEP_DELTA_ERR3 = 1647; // 8
+static const uint64_t SH_FLD_4_BIT_STEP_DELTA_MASK1 = 1648; // 8
+static const uint64_t SH_FLD_4_BIT_STEP_DELTA_MASK2 = 1649; // 8
+static const uint64_t SH_FLD_4_BIT_STEP_DELTA_MASK3 = 1650; // 8
+static const uint64_t SH_FLD_4_BLFIFO_DIS = 1651; // 8
+static const uint64_t SH_FLD_4_BUMP = 1652; // 8
+static const uint64_t SH_FLD_4_CALGATE_ON = 1653; // 8
+static const uint64_t SH_FLD_4_CALIBRATE_BIT = 1654; // 8
+static const uint64_t SH_FLD_4_CALIBRATE_BIT_LEN = 1655; // 8
+static const uint64_t SH_FLD_4_CAL_CKTS_ACTIVE = 1656; // 16
+static const uint64_t SH_FLD_4_CAL_ERROR = 1657; // 16
+static const uint64_t SH_FLD_4_CAL_ERROR_FINE = 1658; // 16
+static const uint64_t SH_FLD_4_CAL_GOOD = 1659; // 16
+static const uint64_t SH_FLD_4_CAL_PD_ENABLE = 1660; // 16
+static const uint64_t SH_FLD_4_CHECKER_ENABLE = 1661; // 8
+static const uint64_t SH_FLD_4_CHECKER_RESET = 1662; // 8
+static const uint64_t SH_FLD_4_CHICKSW_HW278227 = 1663; // 8
+static const uint64_t SH_FLD_4_CLK16_SINGLE_ENDED = 1664; // 32
+static const uint64_t SH_FLD_4_CLK18_SINGLE_ENDED = 1665; // 32
+static const uint64_t SH_FLD_4_CLK20_SINGLE_ENDED = 1666; // 32
+static const uint64_t SH_FLD_4_CLK22_SINGLE_ENDED = 1667; // 32
+static const uint64_t SH_FLD_4_CLK_LEVEL = 1668; // 8
+static const uint64_t SH_FLD_4_CLK_LEVEL_LEN = 1669; // 8
+static const uint64_t SH_FLD_4_CNTL_POL = 1670; // 8
+static const uint64_t SH_FLD_4_CNTL_SRC = 1671; // 8
+static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N0 = 1672; // 8
+static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N0_MASK = 1673; // 8
+static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N1 = 1674; // 8
+static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N1_MASK = 1675; // 8
+static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N2 = 1676; // 8
+static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N2_MASK = 1677; // 8
+static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N3 = 1678; // 8
+static const uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N3_MASK = 1679; // 8
+static const uint64_t SH_FLD_4_CONTINUOUS_UPDATE = 1680; // 16
+static const uint64_t SH_FLD_4_CTR_1D_CHICKEN_SWITCH = 1681; // 8
+static const uint64_t SH_FLD_4_CTR_2D_BIG_STEP_VAL = 1682; // 8
+static const uint64_t SH_FLD_4_CTR_2D_BIG_STEP_VAL_LEN = 1683; // 8
+static const uint64_t SH_FLD_4_CTR_2D_SMALL_STEP_VAL = 1684; // 8
+static const uint64_t SH_FLD_4_CTR_2D_SMALL_STEP_VAL_LEN = 1685; // 8
+static const uint64_t SH_FLD_4_CTR_CUR = 1686; // 8
+static const uint64_t SH_FLD_4_CTR_CUR_LEN = 1687; // 8
+static const uint64_t SH_FLD_4_CTR_NUM_BITS_TO_SKIP = 1688; // 8
+static const uint64_t SH_FLD_4_CTR_NUM_BITS_TO_SKIP_LEN = 1689; // 8
+static const uint64_t SH_FLD_4_CTR_NUM_NO_INC_COMP = 1690; // 8
+static const uint64_t SH_FLD_4_CTR_NUM_NO_INC_COMP_LEN = 1691; // 8
+static const uint64_t SH_FLD_4_CTR_NUM_VREFREQ_CNT = 1692; // 8
+static const uint64_t SH_FLD_4_CTR_NUM_VREFREQ_CNT_LEN = 1693; // 8
+static const uint64_t SH_FLD_4_CTR_NUM_WRRDREQ_CNT = 1694; // 8
+static const uint64_t SH_FLD_4_CTR_NUM_WRRDREQ_CNT_LEN = 1695; // 8
+static const uint64_t SH_FLD_4_CTR_RANGE_CROSSOVER = 1696; // 8
+static const uint64_t SH_FLD_4_CTR_RANGE_CROSSOVER_LEN = 1697; // 8
+static const uint64_t SH_FLD_4_CTR_RANGE_SELECT = 1698; // 8
+static const uint64_t SH_FLD_4_CTR_RUN_FULL_1D = 1699; // 8
+static const uint64_t SH_FLD_4_CTR_SINGLE_RANGE_MAX = 1700; // 8
+static const uint64_t SH_FLD_4_CTR_SINGLE_RANGE_MAX_LEN = 1701; // 8
+static const uint64_t SH_FLD_4_DD2_DQS_FIX_DIS = 1702; // 8
+static const uint64_t SH_FLD_4_DD2_FIX_DIS = 1703; // 8
+static const uint64_t SH_FLD_4_DD2_WTRFL_SYNC_DIS = 1704; // 8
+static const uint64_t SH_FLD_4_DELAYG = 1705; // 608
+static const uint64_t SH_FLD_4_DELAYG_LEN = 1706; // 608
+static const uint64_t SH_FLD_4_DELAY_PING_PONG_HALF = 1707; // 8
+static const uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH = 1708; // 8
+static const uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 1709; // 8
+static const uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW = 1710; // 8
+static const uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 1711; // 8
+static const uint64_t SH_FLD_4_DETECT_REQ = 1712; // 16
+static const uint64_t SH_FLD_4_DFT_FORCE_OUTPUTS = 1713; // 8
+static const uint64_t SH_FLD_4_DFT_PRBS7_GEN_EN = 1714; // 8
+static const uint64_t SH_FLD_4_DIGITAL_EN = 1715; // 8
+static const uint64_t SH_FLD_4_DIR_0_15 = 1716; // 8
+static const uint64_t SH_FLD_4_DIR_0_15_LEN = 1717; // 8
+static const uint64_t SH_FLD_4_DISABLE_0_15 = 1718; // 32
+static const uint64_t SH_FLD_4_DISABLE_0_15_LEN = 1719; // 32
+static const uint64_t SH_FLD_4_DISABLE_16_23 = 1720; // 32
+static const uint64_t SH_FLD_4_DISABLE_16_23_LEN = 1721; // 32
+static const uint64_t SH_FLD_4_DISABLE_PING_PONG = 1722; // 8
+static const uint64_t SH_FLD_4_DISABLE_TERMINATION = 1723; // 8
+static const uint64_t SH_FLD_4_DIS_CLK_GATE = 1724; // 8
+static const uint64_t SH_FLD_4_DLL_ADJUST = 1725; // 16
+static const uint64_t SH_FLD_4_DLL_ADJUST_LEN = 1726; // 16
+static const uint64_t SH_FLD_4_DLL_COMPARE_OUT = 1727; // 16
+static const uint64_t SH_FLD_4_DLL_CORRECT_EN = 1728; // 16
+static const uint64_t SH_FLD_4_DLL_ITER_A = 1729; // 16
+static const uint64_t SH_FLD_4_DL_FORCE_ON = 1730; // 8
+static const uint64_t SH_FLD_4_DONE = 1731; // 16
+static const uint64_t SH_FLD_4_DQS = 1732; // 8
+static const uint64_t SH_FLD_4_DQSCLK_SELECT0 = 1733; // 32
+static const uint64_t SH_FLD_4_DQSCLK_SELECT0_LEN = 1734; // 32
+static const uint64_t SH_FLD_4_DQSCLK_SELECT1 = 1735; // 32
+static const uint64_t SH_FLD_4_DQSCLK_SELECT1_LEN = 1736; // 32
+static const uint64_t SH_FLD_4_DQSCLK_SELECT2 = 1737; // 32
+static const uint64_t SH_FLD_4_DQSCLK_SELECT2_LEN = 1738; // 32
+static const uint64_t SH_FLD_4_DQSCLK_SELECT3 = 1739; // 32
+static const uint64_t SH_FLD_4_DQSCLK_SELECT3_LEN = 1740; // 32
+static const uint64_t SH_FLD_4_DQS_ALIGN_CNTR = 1741; // 8
+static const uint64_t SH_FLD_4_DQS_ALIGN_CNTR_LEN = 1742; // 8
+static const uint64_t SH_FLD_4_DQS_ALIGN_FIX_DIS = 1743; // 8
+static const uint64_t SH_FLD_4_DQS_ALIGN_JITTER = 1744; // 8
+static const uint64_t SH_FLD_4_DQS_ALIGN_QUAD = 1745; // 8
+static const uint64_t SH_FLD_4_DQS_ALIGN_QUAD_LEN = 1746; // 8
+static const uint64_t SH_FLD_4_DQS_ALIGN_SM = 1747; // 8
+static const uint64_t SH_FLD_4_DQS_ALIGN_SM_LEN = 1748; // 8
+static const uint64_t SH_FLD_4_DQS_LEN = 1749; // 8
+static const uint64_t SH_FLD_4_DQS_PIPE_FIX_DIS = 1750; // 8
+static const uint64_t SH_FLD_4_DQS_PIPE_FIX_DIS_LEN = 1751; // 8
+static const uint64_t SH_FLD_4_DQS_QUAD_CONFIG = 1752; // 8
+static const uint64_t SH_FLD_4_DQS_QUAD_CONFIG_LEN = 1753; // 8
+static const uint64_t SH_FLD_4_DRIFT_ERROR = 1754; // 8
+static const uint64_t SH_FLD_4_DRIFT_MASK = 1755; // 8
+static const uint64_t SH_FLD_4_DRVREN_MODE = 1756; // 16
+static const uint64_t SH_FLD_4_DYN_MCTERM_CNTL_EN = 1757; // 8
+static const uint64_t SH_FLD_4_DYN_POWER_CNTL_EN = 1758; // 8
+static const uint64_t SH_FLD_4_DYN_RX_GATE_CNTL_EN = 1759; // 8
+static const uint64_t SH_FLD_4_ENABLE_0_15 = 1760; // 8
+static const uint64_t SH_FLD_4_ENABLE_0_15_LEN = 1761; // 8
+static const uint64_t SH_FLD_4_ENABLE_16_23 = 1762; // 8
+static const uint64_t SH_FLD_4_ENABLE_16_23_LEN = 1763; // 8
+static const uint64_t SH_FLD_4_EN_DQS_OFFSET = 1764; // 8
+static const uint64_t SH_FLD_4_EN_DRIVER_INVFB_DC = 1765; // 16
+static const uint64_t SH_FLD_4_EN_N_WR = 1766; // 8
+static const uint64_t SH_FLD_4_EN_N_WR_LEN = 1767; // 8
+static const uint64_t SH_FLD_4_EN_P_WR = 1768; // 16
+static const uint64_t SH_FLD_4_EN_P_WR_LEN = 1769; // 16
+static const uint64_t SH_FLD_4_ERROR = 1770; // 8
+static const uint64_t SH_FLD_4_ERROR_LEN = 1771; // 8
+static const uint64_t SH_FLD_4_ERR_CLK22_MASK = 1772; // 8
+static const uint64_t SH_FLD_4_EYE_CLIPPING = 1773; // 8
+static const uint64_t SH_FLD_4_EYE_CLIPPING_MASK = 1774; // 8
+static const uint64_t SH_FLD_4_FINE_STEPPING = 1775; // 8
+static const uint64_t SH_FLD_4_FLUSH = 1776; // 8
+static const uint64_t SH_FLD_4_FORCE_DQS_LANES_ON = 1777; // 8
+static const uint64_t SH_FLD_4_FORCE_FIFO_CAPTURE = 1778; // 8
+static const uint64_t SH_FLD_4_FW_LEFT_SIDE = 1779; // 8
+static const uint64_t SH_FLD_4_FW_LEFT_SIDE_LEN = 1780; // 8
+static const uint64_t SH_FLD_4_FW_RIGHT_SIDE = 1781; // 8
+static const uint64_t SH_FLD_4_FW_RIGHT_SIDE_LEN = 1782; // 8
+static const uint64_t SH_FLD_4_HS_DLLMUX_SEL_0_0_3 = 1783; // 8
+static const uint64_t SH_FLD_4_HS_DLLMUX_SEL_0_0_3_LEN = 1784; // 8
+static const uint64_t SH_FLD_4_HS_DLLMUX_SEL_1_0_3 = 1785; // 8
+static const uint64_t SH_FLD_4_HS_DLLMUX_SEL_1_0_3_LEN = 1786; // 8
+static const uint64_t SH_FLD_4_HS_PROBE_A = 1787; // 8
+static const uint64_t SH_FLD_4_HS_PROBE_A_LEN = 1788; // 8
+static const uint64_t SH_FLD_4_HS_PROBE_B = 1789; // 8
+static const uint64_t SH_FLD_4_HS_PROBE_B_LEN = 1790; // 8
+static const uint64_t SH_FLD_4_HW_VALUE = 1791; // 8
+static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N0 = 1792; // 8
+static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N0_MASK = 1793; // 8
+static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N1 = 1794; // 8
+static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N1_MASK = 1795; // 8
+static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N2 = 1796; // 8
+static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N2_MASK = 1797; // 8
+static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N3 = 1798; // 8
+static const uint64_t SH_FLD_4_INCOMPLETE_CAL_N3_MASK = 1799; // 8
+static const uint64_t SH_FLD_4_INIT_IO = 1800; // 8
+static const uint64_t SH_FLD_4_INIT_RXDLL_CAL_RESET = 1801; // 16
+static const uint64_t SH_FLD_4_INIT_RXDLL_CAL_UPDATE = 1802; // 16
+static const uint64_t SH_FLD_4_INTERP_SIG_SLEW = 1803; // 8
+static const uint64_t SH_FLD_4_INTERP_SIG_SLEW_LEN = 1804; // 8
+static const uint64_t SH_FLD_4_INVALID_NS_BIG_R = 1805; // 8
+static const uint64_t SH_FLD_4_INVALID_NS_BIG_R_MASK = 1806; // 8
+static const uint64_t SH_FLD_4_INVALID_NS_SMALL_L = 1807; // 8
+static const uint64_t SH_FLD_4_INVALID_NS_SMALL_L_MASK = 1808; // 8
+static const uint64_t SH_FLD_4_INVALID_NS_SMALL_R = 1809; // 8
+static const uint64_t SH_FLD_4_INVALID_NS_SMALL_R_MASK = 1810; // 8
+static const uint64_t SH_FLD_4_ITERATION_CNTR = 1811; // 8
+static const uint64_t SH_FLD_4_ITERATION_CNTR_LEN = 1812; // 8
+static const uint64_t SH_FLD_4_JUMP_BACK_RIGHT = 1813; // 8
+static const uint64_t SH_FLD_4_LEADING_EDGE_FOUND_MASK = 1814; // 8
+static const uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND = 1815; // 8
+static const uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15 = 1816; // 8
+static const uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15_LEN = 1817; // 8
+static const uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23 = 1818; // 8
+static const uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23_LEN = 1819; // 8
+static const uint64_t SH_FLD_4_LEN = 1820; // 100
+static const uint64_t SH_FLD_4_LOOPBACK_DLY12 = 1821; // 8
+static const uint64_t SH_FLD_4_LOOPBACK_FIX_EN = 1822; // 8
+static const uint64_t SH_FLD_4_LOWER = 1823; // 16
+static const uint64_t SH_FLD_4_LOWER_LEN = 1824; // 16
+static const uint64_t SH_FLD_4_MAIN_PD_ENABLE = 1825; // 16
+static const uint64_t SH_FLD_4_MATCH_STEP_RIGHT = 1826; // 8
+static const uint64_t SH_FLD_4_MAX_DQS = 1827; // 8
+static const uint64_t SH_FLD_4_MAX_DQS_ITER = 1828; // 8
+static const uint64_t SH_FLD_4_MAX_DQS_LEN = 1829; // 8
+static const uint64_t SH_FLD_4_MAX_RANGE = 1830; // 8
+static const uint64_t SH_FLD_4_MAX_RANGE_ERR0 = 1831; // 8
+static const uint64_t SH_FLD_4_MAX_RANGE_ERR1 = 1832; // 8
+static const uint64_t SH_FLD_4_MAX_RANGE_ERR2 = 1833; // 8
+static const uint64_t SH_FLD_4_MAX_RANGE_ERR3 = 1834; // 8
+static const uint64_t SH_FLD_4_MAX_RANGE_MASK1 = 1835; // 8
+static const uint64_t SH_FLD_4_MAX_RANGE_MASK2 = 1836; // 8
+static const uint64_t SH_FLD_4_MAX_RANGE_MASK3 = 1837; // 8
+static const uint64_t SH_FLD_4_MEMINTD00 = 1838; // 8
+static const uint64_t SH_FLD_4_MEMINTD00_LEN = 1839; // 8
+static const uint64_t SH_FLD_4_MEMINTD01 = 1840; // 8
+static const uint64_t SH_FLD_4_MEMINTD01_LEN = 1841; // 8
+static const uint64_t SH_FLD_4_MEMINTD02 = 1842; // 8
+static const uint64_t SH_FLD_4_MEMINTD02_LEN = 1843; // 8
+static const uint64_t SH_FLD_4_MEMINTD03 = 1844; // 8
+static const uint64_t SH_FLD_4_MEMINTD03_LEN = 1845; // 8
+static const uint64_t SH_FLD_4_MEMINTD04 = 1846; // 8
+static const uint64_t SH_FLD_4_MEMINTD04_LEN = 1847; // 8
+static const uint64_t SH_FLD_4_MEMINTD05 = 1848; // 8
+static const uint64_t SH_FLD_4_MEMINTD05_LEN = 1849; // 8
+static const uint64_t SH_FLD_4_MEMINTD06 = 1850; // 8
+static const uint64_t SH_FLD_4_MEMINTD06_LEN = 1851; // 8
+static const uint64_t SH_FLD_4_MEMINTD07 = 1852; // 8
+static const uint64_t SH_FLD_4_MEMINTD07_LEN = 1853; // 8
+static const uint64_t SH_FLD_4_MEMINTD08 = 1854; // 8
+static const uint64_t SH_FLD_4_MEMINTD08_LEN = 1855; // 8
+static const uint64_t SH_FLD_4_MEMINTD09 = 1856; // 8
+static const uint64_t SH_FLD_4_MEMINTD09_LEN = 1857; // 8
+static const uint64_t SH_FLD_4_MEMINTD10 = 1858; // 8
+static const uint64_t SH_FLD_4_MEMINTD10_LEN = 1859; // 8
+static const uint64_t SH_FLD_4_MEMINTD11 = 1860; // 8
+static const uint64_t SH_FLD_4_MEMINTD11_LEN = 1861; // 8
+static const uint64_t SH_FLD_4_MEMINTD12 = 1862; // 8
+static const uint64_t SH_FLD_4_MEMINTD12_LEN = 1863; // 8
+static const uint64_t SH_FLD_4_MEMINTD13 = 1864; // 8
+static const uint64_t SH_FLD_4_MEMINTD13_LEN = 1865; // 8
+static const uint64_t SH_FLD_4_MEMINTD14 = 1866; // 8
+static const uint64_t SH_FLD_4_MEMINTD14_LEN = 1867; // 8
+static const uint64_t SH_FLD_4_MEMINTD15 = 1868; // 8
+static const uint64_t SH_FLD_4_MEMINTD15_LEN = 1869; // 8
+static const uint64_t SH_FLD_4_MEMINTD16 = 1870; // 8
+static const uint64_t SH_FLD_4_MEMINTD16_LEN = 1871; // 8
+static const uint64_t SH_FLD_4_MEMINTD17 = 1872; // 8
+static const uint64_t SH_FLD_4_MEMINTD17_LEN = 1873; // 8
+static const uint64_t SH_FLD_4_MEMINTD18 = 1874; // 8
+static const uint64_t SH_FLD_4_MEMINTD18_LEN = 1875; // 8
+static const uint64_t SH_FLD_4_MEMINTD19 = 1876; // 8
+static const uint64_t SH_FLD_4_MEMINTD19_LEN = 1877; // 8
+static const uint64_t SH_FLD_4_MEMINTD20 = 1878; // 8
+static const uint64_t SH_FLD_4_MEMINTD20_LEN = 1879; // 8
+static const uint64_t SH_FLD_4_MEMINTD21 = 1880; // 8
+static const uint64_t SH_FLD_4_MEMINTD21_LEN = 1881; // 8
+static const uint64_t SH_FLD_4_MEMINTD22 = 1882; // 8
+static const uint64_t SH_FLD_4_MEMINTD22_LEN = 1883; // 8
+static const uint64_t SH_FLD_4_MEMINTD23 = 1884; // 8
+static const uint64_t SH_FLD_4_MEMINTD23_LEN = 1885; // 8
+static const uint64_t SH_FLD_4_MIN_EYE = 1886; // 8
+static const uint64_t SH_FLD_4_MIN_EYE_MASK = 1887; // 8
+static const uint64_t SH_FLD_4_MIN_RANGE = 1888; // 8
+static const uint64_t SH_FLD_4_MIN_RANGE_ERR0 = 1889; // 8
+static const uint64_t SH_FLD_4_MIN_RANGE_ERR1 = 1890; // 8
+static const uint64_t SH_FLD_4_MIN_RANGE_ERR2 = 1891; // 8
+static const uint64_t SH_FLD_4_MIN_RANGE_ERR3 = 1892; // 8
+static const uint64_t SH_FLD_4_MIN_RANGE_MASK1 = 1893; // 8
+static const uint64_t SH_FLD_4_MIN_RANGE_MASK2 = 1894; // 8
+static const uint64_t SH_FLD_4_MIN_RANGE_MASK3 = 1895; // 8
+static const uint64_t SH_FLD_4_MIN_RD_EYE_SIZE = 1896; // 8
+static const uint64_t SH_FLD_4_MIN_RD_EYE_SIZE_LEN = 1897; // 8
+static const uint64_t SH_FLD_4_MRS_CMD_N0 = 1898; // 8
+static const uint64_t SH_FLD_4_MRS_CMD_N1 = 1899; // 8
+static const uint64_t SH_FLD_4_MRS_CMD_N2 = 1900; // 8
+static const uint64_t SH_FLD_4_MRS_CMD_N3 = 1901; // 8
+static const uint64_t SH_FLD_4_N0 = 1902; // 64
+static const uint64_t SH_FLD_4_N0_LEN = 1903; // 64
+static const uint64_t SH_FLD_4_N1 = 1904; // 64
+static const uint64_t SH_FLD_4_N1_LEN = 1905; // 64
+static const uint64_t SH_FLD_4_N2 = 1906; // 64
+static const uint64_t SH_FLD_4_N2_LEN = 1907; // 64
+static const uint64_t SH_FLD_4_N3 = 1908; // 64
+static const uint64_t SH_FLD_4_N3_LEN = 1909; // 64
+static const uint64_t SH_FLD_4_NIB0 = 1910; // 8
+static const uint64_t SH_FLD_4_NIB0TCFLIP_DC = 1911; // 8
+static const uint64_t SH_FLD_4_NIB0_EN_FORCE = 1912; // 8
+static const uint64_t SH_FLD_4_NIB0_LEN = 1913; // 8
+static const uint64_t SH_FLD_4_NIB1 = 1914; // 8
+static const uint64_t SH_FLD_4_NIB1TCFLIP_DC = 1915; // 8
+static const uint64_t SH_FLD_4_NIB1_EN_FORCE = 1916; // 8
+static const uint64_t SH_FLD_4_NIB1_LEN = 1917; // 8
+static const uint64_t SH_FLD_4_NIB2 = 1918; // 8
+static const uint64_t SH_FLD_4_NIB2TCFLIP_DC = 1919; // 8
+static const uint64_t SH_FLD_4_NIB2_EN_FORCE = 1920; // 8
+static const uint64_t SH_FLD_4_NIB2_LEN = 1921; // 8
+static const uint64_t SH_FLD_4_NIB3 = 1922; // 8
+static const uint64_t SH_FLD_4_NIB3TCFLIP_DC = 1923; // 8
+static const uint64_t SH_FLD_4_NIB3_EN_FORCE = 1924; // 8
+static const uint64_t SH_FLD_4_NIB3_LEN = 1925; // 8
+static const uint64_t SH_FLD_4_NIB_0_2_DQSEL_CAP = 1926; // 16
+static const uint64_t SH_FLD_4_NIB_0_2_DQSEL_CAP_LEN = 1927; // 16
+static const uint64_t SH_FLD_4_NIB_0_2_DQSEL_RES = 1928; // 16
+static const uint64_t SH_FLD_4_NIB_0_2_DQSEL_RES_LEN = 1929; // 16
+static const uint64_t SH_FLD_4_NIB_1_3_DQSEL_CAP = 1930; // 16
+static const uint64_t SH_FLD_4_NIB_1_3_DQSEL_CAP_LEN = 1931; // 16
+static const uint64_t SH_FLD_4_NIB_1_3_DQSEL_RES = 1932; // 16
+static const uint64_t SH_FLD_4_NIB_1_3_DQSEL_RES_LEN = 1933; // 16
+static const uint64_t SH_FLD_4_NO_DQS = 1934; // 8
+static const uint64_t SH_FLD_4_NO_DQS_MASK = 1935; // 8
+static const uint64_t SH_FLD_4_NO_EYE_DETECTED = 1936; // 8
+static const uint64_t SH_FLD_4_NO_EYE_DETECTED_MASK = 1937; // 8
+static const uint64_t SH_FLD_4_NO_INCREASE = 1938; // 8
+static const uint64_t SH_FLD_4_NO_INCREASE_ERR0 = 1939; // 8
+static const uint64_t SH_FLD_4_NO_INCREASE_ERR1 = 1940; // 8
+static const uint64_t SH_FLD_4_NO_INCREASE_ERR2 = 1941; // 8
+static const uint64_t SH_FLD_4_NO_INCREASE_ERR3 = 1942; // 8
+static const uint64_t SH_FLD_4_NO_INCREASE_MASK1 = 1943; // 8
+static const uint64_t SH_FLD_4_NO_INCREASE_MASK2 = 1944; // 8
+static const uint64_t SH_FLD_4_NO_INCREASE_MASK3 = 1945; // 8
+static const uint64_t SH_FLD_4_NO_LOCK = 1946; // 8
+static const uint64_t SH_FLD_4_NO_LOCK_MASK = 1947; // 8
+static const uint64_t SH_FLD_4_OFFSET0 = 1948; // 8
+static const uint64_t SH_FLD_4_OFFSET0_LEN = 1949; // 8
+static const uint64_t SH_FLD_4_OFFSET1 = 1950; // 8
+static const uint64_t SH_FLD_4_OFFSET1_LEN = 1951; // 8
+static const uint64_t SH_FLD_4_OFFSET2 = 1952; // 16
+static const uint64_t SH_FLD_4_OFFSET2_LEN = 1953; // 16
+static const uint64_t SH_FLD_4_OFFSET3 = 1954; // 16
+static const uint64_t SH_FLD_4_OFFSET3_LEN = 1955; // 16
+static const uint64_t SH_FLD_4_OFFSET4 = 1956; // 16
+static const uint64_t SH_FLD_4_OFFSET4_LEN = 1957; // 16
+static const uint64_t SH_FLD_4_OFFSET5 = 1958; // 16
+static const uint64_t SH_FLD_4_OFFSET5_LEN = 1959; // 16
+static const uint64_t SH_FLD_4_OFFSET6 = 1960; // 16
+static const uint64_t SH_FLD_4_OFFSET6_LEN = 1961; // 16
+static const uint64_t SH_FLD_4_OFFSET7 = 1962; // 16
+static const uint64_t SH_FLD_4_OFFSET7_LEN = 1963; // 16
+static const uint64_t SH_FLD_4_OFFSET_ERR = 1964; // 8
+static const uint64_t SH_FLD_4_OFFSET_ERR_MASK = 1965; // 8
+static const uint64_t SH_FLD_4_OPERATE_MODE = 1966; // 8
+static const uint64_t SH_FLD_4_OPERATE_MODE_LEN = 1967; // 8
+static const uint64_t SH_FLD_4_OVERRIDE = 1968; // 16
+static const uint64_t SH_FLD_4_PERCAL_PWR_DIS = 1969; // 8
+static const uint64_t SH_FLD_4_PER_CAL_UPDATE_DISABLE = 1970; // 8
+static const uint64_t SH_FLD_4_PHASE_ALIGN_RESET = 1971; // 16
+static const uint64_t SH_FLD_4_PHASE_CNTL_EN = 1972; // 16
+static const uint64_t SH_FLD_4_PHASE_DEFAULT_EN = 1973; // 16
+static const uint64_t SH_FLD_4_POS_EDGE_ALIGN = 1974; // 16
+static const uint64_t SH_FLD_4_QUAD0 = 1975; // 8
+static const uint64_t SH_FLD_4_QUAD0_CLK16 = 1976; // 64
+static const uint64_t SH_FLD_4_QUAD0_CLK18 = 1977; // 64
+static const uint64_t SH_FLD_4_QUAD0_LEN = 1978; // 8
+static const uint64_t SH_FLD_4_QUAD1 = 1979; // 8
+static const uint64_t SH_FLD_4_QUAD1_CLK16 = 1980; // 64
+static const uint64_t SH_FLD_4_QUAD1_CLK18 = 1981; // 64
+static const uint64_t SH_FLD_4_QUAD1_LEN = 1982; // 8
+static const uint64_t SH_FLD_4_QUAD2 = 1983; // 8
+static const uint64_t SH_FLD_4_QUAD2_CLK16 = 1984; // 32
+static const uint64_t SH_FLD_4_QUAD2_CLK18 = 1985; // 32
+static const uint64_t SH_FLD_4_QUAD2_CLK20 = 1986; // 64
+static const uint64_t SH_FLD_4_QUAD2_CLK22 = 1987; // 64
+static const uint64_t SH_FLD_4_QUAD2_LEN = 1988; // 8
+static const uint64_t SH_FLD_4_QUAD3 = 1989; // 8
+static const uint64_t SH_FLD_4_QUAD3_CLK16 = 1990; // 32
+static const uint64_t SH_FLD_4_QUAD3_CLK18 = 1991; // 32
+static const uint64_t SH_FLD_4_QUAD3_CLK20 = 1992; // 64
+static const uint64_t SH_FLD_4_QUAD3_CLK22 = 1993; // 64
+static const uint64_t SH_FLD_4_QUAD3_LEN = 1994; // 8
+static const uint64_t SH_FLD_4_RANGE_DRAM0 = 1995; // 32
+static const uint64_t SH_FLD_4_RANGE_DRAM1 = 1996; // 32
+static const uint64_t SH_FLD_4_RANGE_DRAM2 = 1997; // 32
+static const uint64_t SH_FLD_4_RANGE_DRAM3 = 1998; // 32
+static const uint64_t SH_FLD_4_RD = 1999; // 136
+static const uint64_t SH_FLD_4_RDCLK_SELECT0 = 2000; // 32
+static const uint64_t SH_FLD_4_RDCLK_SELECT0_LEN = 2001; // 32
+static const uint64_t SH_FLD_4_RDCLK_SELECT1 = 2002; // 32
+static const uint64_t SH_FLD_4_RDCLK_SELECT1_LEN = 2003; // 32
+static const uint64_t SH_FLD_4_RDCLK_SELECT2 = 2004; // 32
+static const uint64_t SH_FLD_4_RDCLK_SELECT2_LEN = 2005; // 32
+static const uint64_t SH_FLD_4_RDCLK_SELECT3 = 2006; // 32
+static const uint64_t SH_FLD_4_RDCLK_SELECT3_LEN = 2007; // 32
+static const uint64_t SH_FLD_4_RD_DELAY0 = 2008; // 56
+static const uint64_t SH_FLD_4_RD_DELAY0_LEN = 2009; // 56
+static const uint64_t SH_FLD_4_RD_DELAY1 = 2010; // 56
+static const uint64_t SH_FLD_4_RD_DELAY1_LEN = 2011; // 56
+static const uint64_t SH_FLD_4_RD_DELAY2 = 2012; // 56
+static const uint64_t SH_FLD_4_RD_DELAY2_LEN = 2013; // 56
+static const uint64_t SH_FLD_4_RD_DELAY3 = 2014; // 56
+static const uint64_t SH_FLD_4_RD_DELAY3_LEN = 2015; // 56
+static const uint64_t SH_FLD_4_RD_DELAY4 = 2016; // 56
+static const uint64_t SH_FLD_4_RD_DELAY4_LEN = 2017; // 56
+static const uint64_t SH_FLD_4_RD_DELAY5 = 2018; // 56
+static const uint64_t SH_FLD_4_RD_DELAY5_LEN = 2019; // 56
+static const uint64_t SH_FLD_4_RD_DELAY6 = 2020; // 56
+static const uint64_t SH_FLD_4_RD_DELAY6_LEN = 2021; // 56
+static const uint64_t SH_FLD_4_RD_DELAY7 = 2022; // 56
+static const uint64_t SH_FLD_4_RD_DELAY7_LEN = 2023; // 56
+static const uint64_t SH_FLD_4_RD_LEN = 2024; // 136
+static const uint64_t SH_FLD_4_RD_SIZE0 = 2025; // 88
+static const uint64_t SH_FLD_4_RD_SIZE0_LEN = 2026; // 88
+static const uint64_t SH_FLD_4_RD_SIZE1 = 2027; // 88
+static const uint64_t SH_FLD_4_RD_SIZE1_LEN = 2028; // 88
+static const uint64_t SH_FLD_4_RD_SIZE2 = 2029; // 88
+static const uint64_t SH_FLD_4_RD_SIZE2_LEN = 2030; // 88
+static const uint64_t SH_FLD_4_RD_SIZE3 = 2031; // 88
+static const uint64_t SH_FLD_4_RD_SIZE3_LEN = 2032; // 88
+static const uint64_t SH_FLD_4_RD_SIZE4 = 2033; // 88
+static const uint64_t SH_FLD_4_RD_SIZE4_LEN = 2034; // 88
+static const uint64_t SH_FLD_4_RD_SIZE5 = 2035; // 88
+static const uint64_t SH_FLD_4_RD_SIZE5_LEN = 2036; // 88
+static const uint64_t SH_FLD_4_RD_SIZE6 = 2037; // 88
+static const uint64_t SH_FLD_4_RD_SIZE6_LEN = 2038; // 88
+static const uint64_t SH_FLD_4_RD_SIZE7 = 2039; // 88
+static const uint64_t SH_FLD_4_RD_SIZE7_LEN = 2040; // 88
+static const uint64_t SH_FLD_4_READ_CENTERING_MODE = 2041; // 8
+static const uint64_t SH_FLD_4_READ_CENTERING_MODE_LEN = 2042; // 8
+static const uint64_t SH_FLD_4_REFERENCE1 = 2043; // 8
+static const uint64_t SH_FLD_4_REFERENCE1_LEN = 2044; // 8
+static const uint64_t SH_FLD_4_REFERENCE2 = 2045; // 8
+static const uint64_t SH_FLD_4_REFERENCE2_LEN = 2046; // 8
+static const uint64_t SH_FLD_4_REFERENCE3 = 2047; // 8
+static const uint64_t SH_FLD_4_REFERENCE3_LEN = 2048; // 8
+static const uint64_t SH_FLD_4_REGS_RXDLL_CAL_SKIP = 2049; // 16
+static const uint64_t SH_FLD_4_REGS_RXDLL_CAL_SKIP_LEN = 2050; // 16
+static const uint64_t SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY2 = 2051; // 16
+static const uint64_t SH_FLD_4_REGS_RXDLL_COARSE_EN = 2052; // 16
+static const uint64_t SH_FLD_4_REGS_RXDLL_COARSE_EN_LEN = 2053; // 16
+static const uint64_t SH_FLD_4_REGS_RXDLL_DAC_COARSE = 2054; // 16
+static const uint64_t SH_FLD_4_REGS_RXDLL_DAC_COARSE_LEN = 2055; // 16
+static const uint64_t SH_FLD_4_REGS_RXDLL_VREG_LOWER = 2056; // 16
+static const uint64_t SH_FLD_4_REGS_RXDLL_VREG_LOWER_LEN = 2057; // 16
+static const uint64_t SH_FLD_4_REGS_RXDLL_VREG_UPPER = 2058; // 16
+static const uint64_t SH_FLD_4_REGS_RXDLL_VREG_UPPER_LEN = 2059; // 16
+static const uint64_t SH_FLD_4_RESERVED = 2060; // 3
+static const uint64_t SH_FLD_4_ROT0 = 2061; // 8
+static const uint64_t SH_FLD_4_ROT0_LEN = 2062; // 8
+static const uint64_t SH_FLD_4_ROT1 = 2063; // 8
+static const uint64_t SH_FLD_4_ROT1_LEN = 2064; // 8
+static const uint64_t SH_FLD_4_ROT_CLK_N0 = 2065; // 64
+static const uint64_t SH_FLD_4_ROT_CLK_N0_LEN = 2066; // 64
+static const uint64_t SH_FLD_4_ROT_CLK_N1 = 2067; // 64
+static const uint64_t SH_FLD_4_ROT_CLK_N1_LEN = 2068; // 64
+static const uint64_t SH_FLD_4_ROT_N0 = 2069; // 64
+static const uint64_t SH_FLD_4_ROT_N0_LEN = 2070; // 64
+static const uint64_t SH_FLD_4_ROT_N1 = 2071; // 64
+static const uint64_t SH_FLD_4_ROT_N1_LEN = 2072; // 64
+static const uint64_t SH_FLD_4_ROT_OVERRIDE = 2073; // 16
+static const uint64_t SH_FLD_4_ROT_OVERRIDE_EN = 2074; // 16
+static const uint64_t SH_FLD_4_ROT_OVERRIDE_LEN = 2075; // 16
+static const uint64_t SH_FLD_4_RXCAL_DETECT_DONE_META = 2076; // 16
+static const uint64_t SH_FLD_4_RXCAL_PD_CAL_LAG_META = 2077; // 16
+static const uint64_t SH_FLD_4_RXCAL_PD_MAIN_LAG_META = 2078; // 16
+static const uint64_t SH_FLD_4_RXCAL_PD_MAIN_LEAD_META = 2079; // 16
+static const uint64_t SH_FLD_4_RXREG_COMPCON_DC = 2080; // 16
+static const uint64_t SH_FLD_4_RXREG_COMPCON_DC_LEN = 2081; // 16
+static const uint64_t SH_FLD_4_RXREG_CON_DC = 2082; // 16
+static const uint64_t SH_FLD_4_RXREG_DAC_PULLUP_DC = 2083; // 16
+static const uint64_t SH_FLD_4_RXREG_DRVCON_DC = 2084; // 16
+static const uint64_t SH_FLD_4_RXREG_DRVCON_DC_LEN = 2085; // 16
+static const uint64_t SH_FLD_4_RXREG_FILTER_LENGTH_DC = 2086; // 16
+static const uint64_t SH_FLD_4_RXREG_FILTER_LENGTH_DC_LEN = 2087; // 16
+static const uint64_t SH_FLD_4_RXREG_FINECAL_2XILSB_DC = 2088; // 16
+static const uint64_t SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC = 2089; // 16
+static const uint64_t SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 2090; // 16
+static const uint64_t SH_FLD_4_RXREG_REF_SEL_DC = 2091; // 16
+static const uint64_t SH_FLD_4_RXREG_REF_SEL_DC_LEN = 2092; // 16
+static const uint64_t SH_FLD_4_S0ACENSLICENDRV_DC = 2093; // 8
+static const uint64_t SH_FLD_4_S0ACENSLICENDRV_DC_LEN = 2094; // 8
+static const uint64_t SH_FLD_4_S0ACENSLICEPDRV_DC = 2095; // 8
+static const uint64_t SH_FLD_4_S0ACENSLICEPDRV_DC_LEN = 2096; // 8
+static const uint64_t SH_FLD_4_S0ACENSLICEPTERM_DC = 2097; // 8
+static const uint64_t SH_FLD_4_S0ACENSLICEPTERM_DC_LEN = 2098; // 8
+static const uint64_t SH_FLD_4_S0INSDLYTAP = 2099; // 8
+static const uint64_t SH_FLD_4_S1ACENSLICENDRV_DC = 2100; // 8
+static const uint64_t SH_FLD_4_S1ACENSLICENDRV_DC_LEN = 2101; // 8
+static const uint64_t SH_FLD_4_S1ACENSLICEPDRV_DC = 2102; // 8
+static const uint64_t SH_FLD_4_S1ACENSLICEPDRV_DC_LEN = 2103; // 8
+static const uint64_t SH_FLD_4_S1ACENSLICEPTERM_DC = 2104; // 8
+static const uint64_t SH_FLD_4_S1ACENSLICEPTERM_DC_LEN = 2105; // 8
+static const uint64_t SH_FLD_4_S1INSDLYTAP = 2106; // 8
+static const uint64_t SH_FLD_4_SEL_A = 2107; // 8
+static const uint64_t SH_FLD_4_SEL_A_LEN = 2108; // 8
+static const uint64_t SH_FLD_4_SEL_B = 2109; // 8
+static const uint64_t SH_FLD_4_SEL_B_LEN = 2110; // 8
+static const uint64_t SH_FLD_4_SEND_ENABLE = 2111; // 1
+static const uint64_t SH_FLD_4_SEND_MODE = 2112; // 1
+static const uint64_t SH_FLD_4_SLAVE_CAL_CKT_POWERDOWN = 2113; // 16
+static const uint64_t SH_FLD_4_SLAVE_VREG_DAC_COARSE = 2114; // 16
+static const uint64_t SH_FLD_4_SLAVE_VREG_DAC_COARSE_LEN = 2115; // 16
+static const uint64_t SH_FLD_4_SLAVE_VREG_OVERRIDE = 2116; // 16
+static const uint64_t SH_FLD_4_SLAVE_VREG_REF_SEL_DC = 2117; // 16
+static const uint64_t SH_FLD_4_SLAVE_VREG_REF_SEL_DC_LEN = 2118; // 16
+static const uint64_t SH_FLD_4_SMALL_STEP_LEFT = 2119; // 8
+static const uint64_t SH_FLD_4_SMALL_STEP_RIGHT = 2120; // 8
+static const uint64_t SH_FLD_4_SPARE_SECTOR_BUFFER_CONTROL = 2121; // 3
+static const uint64_t SH_FLD_4_STEP_RANGE_EDGE = 2122; // 8
+static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_ERR0 = 2123; // 8
+static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_ERR1 = 2124; // 8
+static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_ERR2 = 2125; // 8
+static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_ERR3 = 2126; // 8
+static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_MASK1 = 2127; // 8
+static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_MASK2 = 2128; // 8
+static const uint64_t SH_FLD_4_STEP_RANGE_EDGE_MASK3 = 2129; // 8
+static const uint64_t SH_FLD_4_SYNC = 2130; // 8
+static const uint64_t SH_FLD_4_SYNC_LEN = 2131; // 8
+static const uint64_t SH_FLD_4_SYSCLK_DQSCLK_OFFSET = 2132; // 8
+static const uint64_t SH_FLD_4_SYSCLK_DQSCLK_OFFSET_LEN = 2133; // 8
+static const uint64_t SH_FLD_4_SYSCLK_RDCLK_OFFSET = 2134; // 8
+static const uint64_t SH_FLD_4_SYSCLK_RDCLK_OFFSET_LEN = 2135; // 8
+static const uint64_t SH_FLD_4_TRAILING_EDGE_FOUND_MASK = 2136; // 8
+static const uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND = 2137; // 8
+static const uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15 = 2138; // 8
+static const uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 2139; // 8
+static const uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23 = 2140; // 8
+static const uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 2141; // 8
+static const uint64_t SH_FLD_4_TRIG_PERIOD = 2142; // 8
+static const uint64_t SH_FLD_4_TSYS = 2143; // 8
+static const uint64_t SH_FLD_4_TSYS_LEN = 2144; // 8
+static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE = 2145; // 8
+static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_ERR0 = 2146; // 8
+static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_ERR1 = 2147; // 8
+static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_ERR2 = 2148; // 8
+static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_ERR3 = 2149; // 8
+static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_MASK1 = 2150; // 8
+static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_MASK2 = 2151; // 8
+static const uint64_t SH_FLD_4_TWO_RANGE_BEST_CASE_MASK3 = 2152; // 8
+static const uint64_t SH_FLD_4_UPPER = 2153; // 16
+static const uint64_t SH_FLD_4_UPPER_LEN = 2154; // 16
+static const uint64_t SH_FLD_4_VALID_NS_BIG_L = 2155; // 8
+static const uint64_t SH_FLD_4_VALID_NS_BIG_L_MASK = 2156; // 8
+static const uint64_t SH_FLD_4_VALID_NS_BIG_R = 2157; // 8
+static const uint64_t SH_FLD_4_VALID_NS_BIG_R_MASK = 2158; // 8
+static const uint64_t SH_FLD_4_VALID_NS_JUMP_BACK = 2159; // 8
+static const uint64_t SH_FLD_4_VALID_NS_JUMP_BACK_MASK = 2160; // 8
+static const uint64_t SH_FLD_4_VALUE_DRAM0 = 2161; // 32
+static const uint64_t SH_FLD_4_VALUE_DRAM0_LEN = 2162; // 32
+static const uint64_t SH_FLD_4_VALUE_DRAM1 = 2163; // 32
+static const uint64_t SH_FLD_4_VALUE_DRAM1_LEN = 2164; // 32
+static const uint64_t SH_FLD_4_VALUE_DRAM2 = 2165; // 32
+static const uint64_t SH_FLD_4_VALUE_DRAM2_LEN = 2166; // 32
+static const uint64_t SH_FLD_4_VALUE_DRAM3 = 2167; // 32
+static const uint64_t SH_FLD_4_VALUE_DRAM3_LEN = 2168; // 32
+static const uint64_t SH_FLD_4_VREG_RXCAL_COMP_OUT_META = 2169; // 16
+static const uint64_t SH_FLD_4_VREG_SLAVE_COMP_OUT = 2170; // 16
+static const uint64_t SH_FLD_4_WL_ADVANCE_DISABLE = 2171; // 8
+static const uint64_t SH_FLD_4_WL_ERR_CLK16 = 2172; // 16
+static const uint64_t SH_FLD_4_WL_ERR_CLK16_MASK = 2173; // 8
+static const uint64_t SH_FLD_4_WL_ERR_CLK18 = 2174; // 16
+static const uint64_t SH_FLD_4_WL_ERR_CLK18_MASK = 2175; // 8
+static const uint64_t SH_FLD_4_WL_ERR_CLK20 = 2176; // 16
+static const uint64_t SH_FLD_4_WL_ERR_CLK20_MASK = 2177; // 8
+static const uint64_t SH_FLD_4_WL_ERR_CLK22 = 2178; // 16
+static const uint64_t SH_FLD_4_WRAPSEL = 2179; // 8
+static const uint64_t SH_FLD_4_WTRFL_AVE_DIS = 2180; // 8
+static const uint64_t SH_FLD_4_ZERO_DETECTED = 2181; // 8
+static const uint64_t SH_FLD_5 = 2182; // 457
+static const uint64_t SH_FLD_5_LEN = 2183; // 43
+static const uint64_t SH_FLD_5_RESERVED = 2184; // 3
+static const uint64_t SH_FLD_5_SPARE_SECTOR_BUFFER_CONTROL = 2185; // 3
+static const uint64_t SH_FLD_6 = 2186; // 457
+static const uint64_t SH_FLD_6_LEN = 2187; // 43
+static const uint64_t SH_FLD_6_RESERVED = 2188; // 3
+static const uint64_t SH_FLD_6_SPARE_SECTOR_BUFFER_CONTROL = 2189; // 3
+static const uint64_t SH_FLD_6_SPARE_TERM_DIS = 2190; // 3
+static const uint64_t SH_FLD_7 = 2191; // 414
+static const uint64_t SH_FLD_7_RESERVED = 2192; // 3
+static const uint64_t SH_FLD_7_SPARE_SECTOR_BUFFER_CONTROL = 2193; // 3
+static const uint64_t SH_FLD_7_SPARE_TERM_DIS = 2194; // 3
+static const uint64_t SH_FLD_8 = 2195; // 8
+static const uint64_t SH_FLD_842_FC_SELECT = 2196; // 1
+static const uint64_t SH_FLD_842_FC_SELECT_LEN = 2197; // 1
+static const uint64_t SH_FLD_842_LATENCY_CFG = 2198; // 1
+static const uint64_t SH_FLD_8_11_SPARE = 2199; // 8
+static const uint64_t SH_FLD_8_11_SPARE_LEN = 2200; // 8
+static const uint64_t SH_FLD_8_9 = 2201; // 6
+static const uint64_t SH_FLD_8_9_LEN = 2202; // 6
+static const uint64_t SH_FLD_8_RESERVED = 2203; // 6
+static const uint64_t SH_FLD_8_SPARE_SECTOR_BUFFER_CONTROL = 2204; // 3
+static const uint64_t SH_FLD_9 = 2205; // 8
+static const uint64_t SH_FLD_9_RESERVED = 2206; // 3
+static const uint64_t SH_FLD_9_SPARE_SECTOR_BUFFER_CONTROL = 2207; // 3
+static const uint64_t SH_FLD_AACR_PE = 2208; // 8
+static const uint64_t SH_FLD_AADR_PE = 2209; // 8
+static const uint64_t SH_FLD_AAER_PE = 2210; // 8
+static const uint64_t SH_FLD_ABIST = 2211; // 43
+static const uint64_t SH_FLD_ABORT = 2212; // 6
+static const uint64_t SH_FLD_ABORTED_CMD = 2213; // 1
+static const uint64_t SH_FLD_ABORT_CHECK_TIMEOUT_SEL = 2214; // 6
+static const uint64_t SH_FLD_ABORT_CHECK_TIMEOUT_SEL_LEN = 2215; // 6
+static const uint64_t SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR = 2216; // 43
+static const uint64_t SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 2217; // 43
+static const uint64_t SH_FLD_ABORT_ON_ERROR = 2218; // 8
+static const uint64_t SH_FLD_ABORT_ON_ERR_EN = 2219; // 8
+static const uint64_t SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR = 2220; // 43
+static const uint64_t SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR = 2221; // 43
+static const uint64_t SH_FLD_ABUS_LOCK = 2222; // 1
+static const uint64_t SH_FLD_ACCUM = 2223; // 6
+static const uint64_t SH_FLD_ACCUMULATED_DL_RETURN_P0 = 2224; // 43
+static const uint64_t SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY = 2225; // 43
+static const uint64_t SH_FLD_ACCUMULATED_GENERAL_TIMEOUT = 2226; // 43
+static const uint64_t SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID = 2227; // 43
+static const uint64_t SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD = 2228; // 43
+static const uint64_t SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD = 2229; // 43
+static const uint64_t SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 2230; // 43
+static const uint64_t SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE = 2231; // 43
+static const uint64_t SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY = 2232; // 43
+static const uint64_t SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY = 2233; // 43
+static const uint64_t SH_FLD_ACCUMULATED_PCB_WDATA_PARITY = 2234; // 43
+static const uint64_t SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 2235; // 43
+static const uint64_t SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 2236; // 43
+static const uint64_t SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 2237; // 43
+static const uint64_t SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 2238; // 43
+static const uint64_t SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 2239; // 43
+static const uint64_t SH_FLD_ACCUMULATED_UL_P0 = 2240; // 43
+static const uint64_t SH_FLD_ACCUMULATED_UL_RDATA_PARITY = 2241; // 43
+static const uint64_t SH_FLD_ACCUM_HIST = 2242; // 43
+static const uint64_t SH_FLD_ACCUM_LEN = 2243; // 6
+static const uint64_t SH_FLD_ACK = 2244; // 1
+static const uint64_t SH_FLD_ACK_DEAD_CRESP = 2245; // 2
+static const uint64_t SH_FLD_ACK_FIFO_CAP_ADDR = 2246; // 10
+static const uint64_t SH_FLD_ACK_FIFO_CAP_ADDR_LEN = 2247; // 10
+static const uint64_t SH_FLD_ACK_FIFO_CAP_VALID = 2248; // 10
+static const uint64_t SH_FLD_ACK_QUEUE_HIGH = 2249; // 2
+static const uint64_t SH_FLD_ACK_QUEUE_HIGH_LEN = 2250; // 2
+static const uint64_t SH_FLD_ACK_QUEUE_LOW = 2251; // 2
+static const uint64_t SH_FLD_ACK_QUEUE_LOW_LEN = 2252; // 2
+static const uint64_t SH_FLD_ACK_QUEUE_START = 2253; // 2
+static const uint64_t SH_FLD_ACK_QUEUE_START_LEN = 2254; // 2
+static const uint64_t SH_FLD_ACT = 2255; // 63
+static const uint64_t SH_FLD_ACTCYCLECNT = 2256; // 3
+static const uint64_t SH_FLD_ACTCYCLECNT_LEN = 2257; // 3
+static const uint64_t SH_FLD_ACTION0 = 2258; // 60
+static const uint64_t SH_FLD_ACTION0_LEN = 2259; // 60
+static const uint64_t SH_FLD_ACTION1 = 2260; // 60
+static const uint64_t SH_FLD_ACTION1_LEN = 2261; // 60
+static const uint64_t SH_FLD_ACTION_0 = 2262; // 4
+static const uint64_t SH_FLD_ACTION_0_LEN = 2263; // 4
+static const uint64_t SH_FLD_ACTION_1 = 2264; // 4
+static const uint64_t SH_FLD_ACTION_1_LEN = 2265; // 4
+static const uint64_t SH_FLD_ACTIVATE_COUNT = 2266; // 8
+static const uint64_t SH_FLD_ACTIVATE_COUNT_LEN = 2267; // 8
+static const uint64_t SH_FLD_ACTIVE_CHANNEL_CNT = 2268; // 1
+static const uint64_t SH_FLD_ACTIVE_CHANNEL_CNT_LEN = 2269; // 1
+static const uint64_t SH_FLD_ACTIVE_MASK = 2270; // 24
+static const uint64_t SH_FLD_ACTIVE_MASK_LEN = 2271; // 24
+static const uint64_t SH_FLD_ACTIVITY = 2272; // 129
+static const uint64_t SH_FLD_ACTIVITY_LEN = 2273; // 129
+static const uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE = 2274; // 24
+static const uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_EN = 2275; // 24
+static const uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_LEN = 2276; // 24
+static const uint64_t SH_FLD_ACTUAL_CLK_SB_SPARE = 2277; // 24
+static const uint64_t SH_FLD_ACTUAL_CLK_SB_STRENGTH = 2278; // 24
+static const uint64_t SH_FLD_ACTUAL_CLK_SB_STRENGTH_LEN = 2279; // 24
+static const uint64_t SH_FLD_ACTUAL_CLK_SW_RESCLK = 2280; // 24
+static const uint64_t SH_FLD_ACTUAL_CLK_SW_RESCLK_LEN = 2281; // 24
+static const uint64_t SH_FLD_ACTUAL_CLK_SW_SPARE = 2282; // 24
+static const uint64_t SH_FLD_ACTUAL_ERROR = 2283; // 3
+static const uint64_t SH_FLD_ACTUAL_ERROR_LEN = 2284; // 3
+static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE = 2285; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_EN = 2286; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_LEN = 2287; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_SPARE0 = 2288; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_STRENGTH = 2289; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_STRENGTH_LEN = 2290; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SW_RESCLK = 2291; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SW_RESCLK_LEN = 2292; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SW_SPARE1 = 2293; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE = 2294; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_EN = 2295; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_LEN = 2296; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_SPARE0 = 2297; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_STRENGTH = 2298; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_STRENGTH_LEN = 2299; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SW_RESCLK = 2300; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SW_RESCLK_LEN = 2301; // 6
+static const uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SW_SPARE1 = 2302; // 6
+static const uint64_t SH_FLD_ACT_CHECK_TIMEOUT_SEL = 2303; // 4
+static const uint64_t SH_FLD_ACT_CHECK_TIMEOUT_SEL_LEN = 2304; // 4
+static const uint64_t SH_FLD_ACT_DIS = 2305; // 43
+static const uint64_t SH_FLD_AC_COUPLED = 2306; // 2
+static const uint64_t SH_FLD_ADAPTEST_1BIT_ENABLE = 2307; // 1
+static const uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX = 2308; // 1
+static const uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX_LEN = 2309; // 1
+static const uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN = 2310; // 1
+static const uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN_LEN = 2311; // 1
+static const uint64_t SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH = 2312; // 1
+static const uint64_t SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH_LEN = 2313; // 1
+static const uint64_t SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH = 2314; // 1
+static const uint64_t SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH_LEN = 2315; // 1
+static const uint64_t SH_FLD_ADAPTEST_ENABLE = 2316; // 1
+static const uint64_t SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH = 2317; // 1
+static const uint64_t SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH_LEN = 2318; // 1
+static const uint64_t SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH = 2319; // 1
+static const uint64_t SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH_LEN = 2320; // 1
+static const uint64_t SH_FLD_ADAPTEST_SAMPLE_SIZE = 2321; // 1
+static const uint64_t SH_FLD_ADAPTEST_SAMPLE_SIZE_LEN = 2322; // 1
+static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0 = 2323; // 1
+static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0_LEN = 2324; // 1
+static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1 = 2325; // 1
+static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1_LEN = 2326; // 1
+static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0 = 2327; // 1
+static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0_LEN = 2328; // 1
+static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1 = 2329; // 1
+static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1_LEN = 2330; // 1
+static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_TH = 2331; // 1
+static const uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_TH_LEN = 2332; // 1
+static const uint64_t SH_FLD_ADAPTEST_WINDOW_SIZE = 2333; // 1
+static const uint64_t SH_FLD_ADAPTEST_WINDOW_SIZE_LEN = 2334; // 1
+static const uint64_t SH_FLD_ADCFSM_ONGOING = 2335; // 1
+static const uint64_t SH_FLD_ADDR = 2336; // 39
+static const uint64_t SH_FLD_ADDR0 = 2337; // 8
+static const uint64_t SH_FLD_ADDR0_LEN = 2338; // 8
+static const uint64_t SH_FLD_ADDR1 = 2339; // 8
+static const uint64_t SH_FLD_ADDR1_LEN = 2340; // 8
+static const uint64_t SH_FLD_ADDR2 = 2341; // 16
+static const uint64_t SH_FLD_ADDR2_LEN = 2342; // 16
+static const uint64_t SH_FLD_ADDR3 = 2343; // 16
+static const uint64_t SH_FLD_ADDR3_LEN = 2344; // 16
+static const uint64_t SH_FLD_ADDR4 = 2345; // 16
+static const uint64_t SH_FLD_ADDR4_LEN = 2346; // 16
+static const uint64_t SH_FLD_ADDRESS = 2347; // 221
+static const uint64_t SH_FLD_ADDRESS_8_63 = 2348; // 1
+static const uint64_t SH_FLD_ADDRESS_8_63_LEN = 2349; // 1
+static const uint64_t SH_FLD_ADDRESS_LEN = 2350; // 220
+static const uint64_t SH_FLD_ADDRESS_PARITY = 2351; // 43
+static const uint64_t SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT = 2352; // 2
+static const uint64_t SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT_LEN = 2353; // 2
+static const uint64_t SH_FLD_ADDR_21_37 = 2354; // 1
+static const uint64_t SH_FLD_ADDR_21_37_LEN = 2355; // 1
+static const uint64_t SH_FLD_ADDR_26_38 = 2356; // 1
+static const uint64_t SH_FLD_ADDR_26_38_LEN = 2357; // 1
+static const uint64_t SH_FLD_ADDR_8_37 = 2358; // 1
+static const uint64_t SH_FLD_ADDR_8_37_LEN = 2359; // 1
+static const uint64_t SH_FLD_ADDR_8_38 = 2360; // 1
+static const uint64_t SH_FLD_ADDR_8_38_LEN = 2361; // 1
+static const uint64_t SH_FLD_ADDR_8_48 = 2362; // 1
+static const uint64_t SH_FLD_ADDR_8_48_LEN = 2363; // 1
+static const uint64_t SH_FLD_ADDR_8_49 = 2364; // 2
+static const uint64_t SH_FLD_ADDR_8_49_LEN = 2365; // 2
+static const uint64_t SH_FLD_ADDR_BAR = 2366; // 2
+static const uint64_t SH_FLD_ADDR_BAR_MODE = 2367; // 2
+static const uint64_t SH_FLD_ADDR_BUFFER = 2368; // 43
+static const uint64_t SH_FLD_ADDR_ERROR = 2369; // 2
+static const uint64_t SH_FLD_ADDR_ERROR_PULSE = 2370; // 2
+static const uint64_t SH_FLD_ADDR_INVALID_FACES = 2371; // 1
+static const uint64_t SH_FLD_ADDR_INVALID_PIB = 2372; // 1
+static const uint64_t SH_FLD_ADDR_LEN = 2373; // 39
+static const uint64_t SH_FLD_ADDR_MIRROR_A11_A13 = 2374; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_A3_A4 = 2375; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_A5_A6 = 2376; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_A7_A8 = 2377; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_BA0_BA1 = 2378; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_BG0_BG1 = 2379; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP0_PRI = 2380; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP0_QUA = 2381; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP0_SEC = 2382; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP0_TER = 2383; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP1_PRI = 2384; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP1_QUA = 2385; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP1_SEC = 2386; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP1_TER = 2387; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP2_PRI = 2388; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP2_QUA = 2389; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP2_SEC = 2390; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP2_TER = 2391; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP3_PRI = 2392; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP3_QUA = 2393; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP3_SEC = 2394; // 8
+static const uint64_t SH_FLD_ADDR_MIRROR_RP3_TER = 2395; // 8
+static const uint64_t SH_FLD_ADDR_NVLD = 2396; // 1
+static const uint64_t SH_FLD_ADDR_PARITY_ERR = 2397; // 4
+static const uint64_t SH_FLD_ADDR_RESET_INTR_FACES = 2398; // 1
+static const uint64_t SH_FLD_ADDR_RESET_INTR_FACES_LEN = 2399; // 1
+static const uint64_t SH_FLD_ADDR_RESET_INTR_PIB = 2400; // 1
+static const uint64_t SH_FLD_ADDR_RESET_INTR_PIB_LEN = 2401; // 1
+static const uint64_t SH_FLD_ADDR_TAG = 2402; // 1
+static const uint64_t SH_FLD_ADDR_TAG_LEN = 2403; // 1
+static const uint64_t SH_FLD_ADR = 2404; // 4
+static const uint64_t SH_FLD_ADR0 = 2405; // 16
+static const uint64_t SH_FLD_ADR0_ANALOG_WRAPON = 2406; // 8
+static const uint64_t SH_FLD_ADR0_ATESTSEL_0_2 = 2407; // 8
+static const uint64_t SH_FLD_ADR0_ATESTSEL_0_2_LEN = 2408; // 8
+static const uint64_t SH_FLD_ADR0_ATEST_SEL_0 = 2409; // 8
+static const uint64_t SH_FLD_ADR0_ATEST_SEL_0_LEN = 2410; // 8
+static const uint64_t SH_FLD_ADR0_BB_LOCK = 2411; // 8
+static const uint64_t SH_FLD_ADR0_CAL_CKTS_ACTIVE = 2412; // 8
+static const uint64_t SH_FLD_ADR0_CAL_ERROR = 2413; // 8
+static const uint64_t SH_FLD_ADR0_CAL_ERROR_FINE = 2414; // 8
+static const uint64_t SH_FLD_ADR0_CAL_GOOD = 2415; // 8
+static const uint64_t SH_FLD_ADR0_CAL_PD_ENABLE = 2416; // 8
+static const uint64_t SH_FLD_ADR0_CONTINUOUS_UPDATE = 2417; // 8
+static const uint64_t SH_FLD_ADR0_DETECT_REQ = 2418; // 8
+static const uint64_t SH_FLD_ADR0_DLL_ADJUST = 2419; // 8
+static const uint64_t SH_FLD_ADR0_DLL_ADJUST_LEN = 2420; // 8
+static const uint64_t SH_FLD_ADR0_DLL_COMPARE_OUT = 2421; // 8
+static const uint64_t SH_FLD_ADR0_DLL_CORRECT_EN = 2422; // 8
+static const uint64_t SH_FLD_ADR0_DLL_ITER_A = 2423; // 8
+static const uint64_t SH_FLD_ADR0_EN = 2424; // 8
+static const uint64_t SH_FLD_ADR0_EN_DRIVER_INVFB_DC = 2425; // 8
+static const uint64_t SH_FLD_ADR0_FLUSH = 2426; // 8
+static const uint64_t SH_FLD_ADR0_HS_DLLMUX_SEL_0_3 = 2427; // 8
+static const uint64_t SH_FLD_ADR0_HS_DLLMUX_SEL_0_3_LEN = 2428; // 8
+static const uint64_t SH_FLD_ADR0_HS_PROBE_A_SEL_0_3 = 2429; // 8
+static const uint64_t SH_FLD_ADR0_HS_PROBE_A_SEL_0_3_LEN = 2430; // 8
+static const uint64_t SH_FLD_ADR0_HS_PROBE_B_SEL_0_3 = 2431; // 8
+static const uint64_t SH_FLD_ADR0_HS_PROBE_B_SEL_0_3_LEN = 2432; // 8
+static const uint64_t SH_FLD_ADR0_INIT_IO = 2433; // 8
+static const uint64_t SH_FLD_ADR0_INIT_RXDLL_CAL_RESET = 2434; // 8
+static const uint64_t SH_FLD_ADR0_INIT_RXDLL_CAL_UPDATE = 2435; // 8
+static const uint64_t SH_FLD_ADR0_INTERP_SIG_SLEW = 2436; // 8
+static const uint64_t SH_FLD_ADR0_INTERP_SIG_SLEW_LEN = 2437; // 8
+static const uint64_t SH_FLD_ADR0_LEN = 2438; // 16
+static const uint64_t SH_FLD_ADR0_MAIN_PD_ENABLE = 2439; // 8
+static const uint64_t SH_FLD_ADR0_OVERRIDE = 2440; // 16
+static const uint64_t SH_FLD_ADR0_OVERRIDE_EN = 2441; // 8
+static const uint64_t SH_FLD_ADR0_OVERRIDE_LEN = 2442; // 8
+static const uint64_t SH_FLD_ADR0_PHASE_ALIGN_RESET = 2443; // 8
+static const uint64_t SH_FLD_ADR0_PHASE_DEFAULT_EN = 2444; // 8
+static const uint64_t SH_FLD_ADR0_PHASE_EN = 2445; // 8
+static const uint64_t SH_FLD_ADR0_POS_EDGE_ALIGN = 2446; // 8
+static const uint64_t SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP = 2447; // 8
+static const uint64_t SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP_LEN = 2448; // 8
+static const uint64_t SH_FLD_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 = 2449; // 8
+static const uint64_t SH_FLD_ADR0_REGS_RXDLL_DAC = 2450; // 8
+static const uint64_t SH_FLD_ADR0_REGS_RXDLL_DAC_LEN = 2451; // 8
+static const uint64_t SH_FLD_ADR0_REGS_RXDLL_EN = 2452; // 8
+static const uint64_t SH_FLD_ADR0_REGS_RXDLL_EN_LEN = 2453; // 8
+static const uint64_t SH_FLD_ADR0_REGS_RXDLL_VREG = 2454; // 16
+static const uint64_t SH_FLD_ADR0_REGS_RXDLL_VREG_LEN = 2455; // 16
+static const uint64_t SH_FLD_ADR0_ROT = 2456; // 8
+static const uint64_t SH_FLD_ADR0_ROT_LEN = 2457; // 8
+static const uint64_t SH_FLD_ADR0_ROT_OVERRIDE = 2458; // 8
+static const uint64_t SH_FLD_ADR0_ROT_OVERRIDE_EN = 2459; // 8
+static const uint64_t SH_FLD_ADR0_ROT_OVERRIDE_LEN = 2460; // 8
+static const uint64_t SH_FLD_ADR0_RXCAL_DETECT_DONE_META = 2461; // 8
+static const uint64_t SH_FLD_ADR0_RXCAL_PD_CAL_LAG_META = 2462; // 8
+static const uint64_t SH_FLD_ADR0_RXCAL_PD_MAIN_LAG_META = 2463; // 8
+static const uint64_t SH_FLD_ADR0_RXCAL_PD_MAIN_LEAD_META = 2464; // 8
+static const uint64_t SH_FLD_ADR0_RXREG_COMPCON_DC = 2465; // 8
+static const uint64_t SH_FLD_ADR0_RXREG_COMPCON_DC_LEN = 2466; // 8
+static const uint64_t SH_FLD_ADR0_RXREG_CON_DC = 2467; // 8
+static const uint64_t SH_FLD_ADR0_RXREG_DAC_PULLUP_DC = 2468; // 8
+static const uint64_t SH_FLD_ADR0_RXREG_DRVCON_DC = 2469; // 8
+static const uint64_t SH_FLD_ADR0_RXREG_DRVCON_DC_LEN = 2470; // 8
+static const uint64_t SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC = 2471; // 8
+static const uint64_t SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC_LEN = 2472; // 8
+static const uint64_t SH_FLD_ADR0_RXREG_FINECAL_2XILSB_DC = 2473; // 8
+static const uint64_t SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC = 2474; // 8
+static const uint64_t SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 2475; // 8
+static const uint64_t SH_FLD_ADR0_RXREG_REF_SEL_DC = 2476; // 8
+static const uint64_t SH_FLD_ADR0_RXREG_REF_SEL_DC_LEN = 2477; // 8
+static const uint64_t SH_FLD_ADR0_SLAVE_CAL_CKT_POWERDOWN = 2478; // 8
+static const uint64_t SH_FLD_ADR0_SLAVE_VREG_DAC_COARSE = 2479; // 8
+static const uint64_t SH_FLD_ADR0_SLAVE_VREG_DAC_COARSE_LEN = 2480; // 8
+static const uint64_t SH_FLD_ADR0_SLAVE_VREG_OVERRIDE = 2481; // 8
+static const uint64_t SH_FLD_ADR0_SLAVE_VREG_REF_SEL_DC = 2482; // 8
+static const uint64_t SH_FLD_ADR0_SLAVE_VREG_REF_SEL_DC_LEN = 2483; // 8
+static const uint64_t SH_FLD_ADR0_SLEW_DONE_STATUS = 2484; // 8
+static const uint64_t SH_FLD_ADR0_SLEW_DONE_STATUS_LEN = 2485; // 8
+static const uint64_t SH_FLD_ADR0_START = 2486; // 8
+static const uint64_t SH_FLD_ADR0_TARGET_PR_OFFSET = 2487; // 8
+static const uint64_t SH_FLD_ADR0_TARGET_PR_OFFSET_LEN = 2488; // 8
+static const uint64_t SH_FLD_ADR0_TSYS = 2489; // 8
+static const uint64_t SH_FLD_ADR0_TSYS_LEN = 2490; // 8
+static const uint64_t SH_FLD_ADR0_VALUE = 2491; // 16
+static const uint64_t SH_FLD_ADR0_VALUE_LEN = 2492; // 16
+static const uint64_t SH_FLD_ADR0_VREG_RXCAL_COMP_OUT_META = 2493; // 8
+static const uint64_t SH_FLD_ADR0_VREG_SLAVE1_COMP_OUT = 2494; // 8
+static const uint64_t SH_FLD_ADR0_VREG_SLAVE2_COMP_OUT = 2495; // 8
+static const uint64_t SH_FLD_ADR1 = 2496; // 16
+static const uint64_t SH_FLD_ADR1_ANALOG_WRAPON = 2497; // 8
+static const uint64_t SH_FLD_ADR1_ATESTSEL_0_2 = 2498; // 8
+static const uint64_t SH_FLD_ADR1_ATESTSEL_0_2_LEN = 2499; // 8
+static const uint64_t SH_FLD_ADR1_ATEST_SEL_0 = 2500; // 8
+static const uint64_t SH_FLD_ADR1_ATEST_SEL_0_LEN = 2501; // 8
+static const uint64_t SH_FLD_ADR1_BB_LOCK = 2502; // 8
+static const uint64_t SH_FLD_ADR1_CAL_CKTS_ACTIVE = 2503; // 8
+static const uint64_t SH_FLD_ADR1_CAL_ERROR = 2504; // 8
+static const uint64_t SH_FLD_ADR1_CAL_ERROR_FINE = 2505; // 8
+static const uint64_t SH_FLD_ADR1_CAL_GOOD = 2506; // 8
+static const uint64_t SH_FLD_ADR1_CAL_PD_ENABLE = 2507; // 8
+static const uint64_t SH_FLD_ADR1_CONTINUOUS_UPDATE = 2508; // 8
+static const uint64_t SH_FLD_ADR1_DETECT_REQ = 2509; // 8
+static const uint64_t SH_FLD_ADR1_DLL_ADJUST = 2510; // 8
+static const uint64_t SH_FLD_ADR1_DLL_ADJUST_LEN = 2511; // 8
+static const uint64_t SH_FLD_ADR1_DLL_COMPARE_OUT = 2512; // 8
+static const uint64_t SH_FLD_ADR1_DLL_CORRECT_EN = 2513; // 8
+static const uint64_t SH_FLD_ADR1_DLL_ITER_A = 2514; // 8
+static const uint64_t SH_FLD_ADR1_EN = 2515; // 8
+static const uint64_t SH_FLD_ADR1_EN_DRIVER_INVFB_DC = 2516; // 8
+static const uint64_t SH_FLD_ADR1_FLUSH = 2517; // 8
+static const uint64_t SH_FLD_ADR1_HS_DLLMUX_SEL_0_3 = 2518; // 8
+static const uint64_t SH_FLD_ADR1_HS_DLLMUX_SEL_0_3_LEN = 2519; // 8
+static const uint64_t SH_FLD_ADR1_HS_PROBE_A_SEL_0_3 = 2520; // 8
+static const uint64_t SH_FLD_ADR1_HS_PROBE_A_SEL_0_3_LEN = 2521; // 8
+static const uint64_t SH_FLD_ADR1_HS_PROBE_B_SEL_0_3 = 2522; // 8
+static const uint64_t SH_FLD_ADR1_HS_PROBE_B_SEL_0_3_LEN = 2523; // 8
+static const uint64_t SH_FLD_ADR1_INIT_IO = 2524; // 8
+static const uint64_t SH_FLD_ADR1_INIT_RXDLL_CAL_RESET = 2525; // 8
+static const uint64_t SH_FLD_ADR1_INIT_RXDLL_CAL_UPDATE = 2526; // 8
+static const uint64_t SH_FLD_ADR1_INTERP_SIG_SLEW = 2527; // 8
+static const uint64_t SH_FLD_ADR1_INTERP_SIG_SLEW_LEN = 2528; // 8
+static const uint64_t SH_FLD_ADR1_LEN = 2529; // 16
+static const uint64_t SH_FLD_ADR1_MAIN_PD_ENABLE = 2530; // 8
+static const uint64_t SH_FLD_ADR1_OVERRIDE = 2531; // 16
+static const uint64_t SH_FLD_ADR1_OVERRIDE_EN = 2532; // 8
+static const uint64_t SH_FLD_ADR1_OVERRIDE_LEN = 2533; // 8
+static const uint64_t SH_FLD_ADR1_PHASE_ALIGN_RESET = 2534; // 8
+static const uint64_t SH_FLD_ADR1_PHASE_DEFAULT_EN = 2535; // 8
+static const uint64_t SH_FLD_ADR1_PHASE_EN = 2536; // 8
+static const uint64_t SH_FLD_ADR1_POS_EDGE_ALIGN = 2537; // 8
+static const uint64_t SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP = 2538; // 8
+static const uint64_t SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP_LEN = 2539; // 8
+static const uint64_t SH_FLD_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 = 2540; // 8
+static const uint64_t SH_FLD_ADR1_REGS_RXDLL_DAC = 2541; // 8
+static const uint64_t SH_FLD_ADR1_REGS_RXDLL_DAC_LEN = 2542; // 8
+static const uint64_t SH_FLD_ADR1_REGS_RXDLL_EN = 2543; // 8
+static const uint64_t SH_FLD_ADR1_REGS_RXDLL_EN_LEN = 2544; // 8
+static const uint64_t SH_FLD_ADR1_REGS_RXDLL_VREG = 2545; // 16
+static const uint64_t SH_FLD_ADR1_REGS_RXDLL_VREG_LEN = 2546; // 16
+static const uint64_t SH_FLD_ADR1_ROT = 2547; // 8
+static const uint64_t SH_FLD_ADR1_ROT_LEN = 2548; // 8
+static const uint64_t SH_FLD_ADR1_ROT_OVERRIDE = 2549; // 8
+static const uint64_t SH_FLD_ADR1_ROT_OVERRIDE_EN = 2550; // 8
+static const uint64_t SH_FLD_ADR1_ROT_OVERRIDE_LEN = 2551; // 8
+static const uint64_t SH_FLD_ADR1_RXCAL_DETECT_DONE_META = 2552; // 8
+static const uint64_t SH_FLD_ADR1_RXCAL_PD_CAL_LAG_META = 2553; // 8
+static const uint64_t SH_FLD_ADR1_RXCAL_PD_MAIN_LAG_META = 2554; // 8
+static const uint64_t SH_FLD_ADR1_RXCAL_PD_MAIN_LEAD_META = 2555; // 8
+static const uint64_t SH_FLD_ADR1_RXREG_COMPCON_DC = 2556; // 8
+static const uint64_t SH_FLD_ADR1_RXREG_COMPCON_DC_LEN = 2557; // 8
+static const uint64_t SH_FLD_ADR1_RXREG_CON_DC = 2558; // 8
+static const uint64_t SH_FLD_ADR1_RXREG_DAC_PULLUP_DC = 2559; // 8
+static const uint64_t SH_FLD_ADR1_RXREG_DRVCON_DC = 2560; // 8
+static const uint64_t SH_FLD_ADR1_RXREG_DRVCON_DC_LEN = 2561; // 8
+static const uint64_t SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC = 2562; // 8
+static const uint64_t SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC_LEN = 2563; // 8
+static const uint64_t SH_FLD_ADR1_RXREG_FINECAL_2XILSB_DC = 2564; // 8
+static const uint64_t SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC = 2565; // 8
+static const uint64_t SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 2566; // 8
+static const uint64_t SH_FLD_ADR1_RXREG_REF_SEL_DC = 2567; // 8
+static const uint64_t SH_FLD_ADR1_RXREG_REF_SEL_DC_LEN = 2568; // 8
+static const uint64_t SH_FLD_ADR1_SLAVE_CAL_CKT_POWERDOWN = 2569; // 8
+static const uint64_t SH_FLD_ADR1_SLAVE_VREG_DAC_COARSE = 2570; // 8
+static const uint64_t SH_FLD_ADR1_SLAVE_VREG_DAC_COARSE_LEN = 2571; // 8
+static const uint64_t SH_FLD_ADR1_SLAVE_VREG_OVERRIDE = 2572; // 8
+static const uint64_t SH_FLD_ADR1_SLAVE_VREG_REF_SEL_DC = 2573; // 8
+static const uint64_t SH_FLD_ADR1_SLAVE_VREG_REF_SEL_DC_LEN = 2574; // 8
+static const uint64_t SH_FLD_ADR1_SLEW_DONE_STATUS = 2575; // 8
+static const uint64_t SH_FLD_ADR1_SLEW_DONE_STATUS_LEN = 2576; // 8
+static const uint64_t SH_FLD_ADR1_START = 2577; // 8
+static const uint64_t SH_FLD_ADR1_TARGET_PR_OFFSET = 2578; // 8
+static const uint64_t SH_FLD_ADR1_TARGET_PR_OFFSET_LEN = 2579; // 8
+static const uint64_t SH_FLD_ADR1_TSYS = 2580; // 8
+static const uint64_t SH_FLD_ADR1_TSYS_LEN = 2581; // 8
+static const uint64_t SH_FLD_ADR1_VALUE = 2582; // 16
+static const uint64_t SH_FLD_ADR1_VALUE_LEN = 2583; // 16
+static const uint64_t SH_FLD_ADR1_VREG_RXCAL_COMP_OUT_META = 2584; // 8
+static const uint64_t SH_FLD_ADR1_VREG_SLAVE1_COMP_OUT = 2585; // 8
+static const uint64_t SH_FLD_ADR1_VREG_SLAVE2_COMP_OUT = 2586; // 8
+static const uint64_t SH_FLD_ADR_DLL_CAL_ERROR = 2587; // 8
+static const uint64_t SH_FLD_ADR_DLL_CAL_ERROR_FINE = 2588; // 8
+static const uint64_t SH_FLD_ADR_ERROR = 2589; // 8
+static const uint64_t SH_FLD_ADR_ERROR_FINE = 2590; // 8
+static const uint64_t SH_FLD_ADR_GOOD = 2591; // 8
+static const uint64_t SH_FLD_ADR_LEN = 2592; // 4
+static const uint64_t SH_FLD_ADR_SLAVE_SEL = 2593; // 8
+static const uint64_t SH_FLD_ADS_HANG = 2594; // 1
+static const uint64_t SH_FLD_ADU_MALF_ALERT = 2595; // 1
+static const uint64_t SH_FLD_ADVANCE_RD_VALID = 2596; // 8
+static const uint64_t SH_FLD_AECS = 2597; // 6
+static const uint64_t SH_FLD_AECS_LEN = 2598; // 6
+static const uint64_t SH_FLD_AESSHA_LATENCY_CFG = 2599; // 1
+static const uint64_t SH_FLD_AES_LATENCY_CFG = 2600; // 1
+static const uint64_t SH_FLD_AIB_ACCESS_ERROR = 2601; // 6
+static const uint64_t SH_FLD_AIB_ADDRESS_INVALID = 2602; // 6
+static const uint64_t SH_FLD_AIB_COMMAND_INVALID = 2603; // 6
+static const uint64_t SH_FLD_AIB_FATAL_CLASS_ERROR = 2604; // 6
+static const uint64_t SH_FLD_AIB_INF_CLASS_ERROR = 2605; // 6
+static const uint64_t SH_FLD_AIB_IN_CMD_CTL_PERR = 2606; // 1
+static const uint64_t SH_FLD_AIB_IN_CMD_PERR = 2607; // 1
+static const uint64_t SH_FLD_AIB_IN_DAT_CTL_PERR = 2608; // 1
+static const uint64_t SH_FLD_AI_ECC_CE = 2609; // 1
+static const uint64_t SH_FLD_AI_ECC_UE = 2610; // 1
+static const uint64_t SH_FLD_ALIGN_ON_EVEN_CYCLES = 2611; // 8
+static const uint64_t SH_FLD_ALLOC = 2612; // 24
+static const uint64_t SH_FLD_ALLOC_LEN = 2613; // 24
+static const uint64_t SH_FLD_ALLOW_CRYPTO = 2614; // 1
+static const uint64_t SH_FLD_ALLOW_RD_FIFO_AUTO_RESET = 2615; // 8
+static const uint64_t SH_FLD_ALLOW_REG_WAKEUP_C0 = 2616; // 12
+static const uint64_t SH_FLD_ALLOW_REG_WAKEUP_C1 = 2617; // 12
+static const uint64_t SH_FLD_ALTD_DATA_ITAG = 2618; // 1
+static const uint64_t SH_FLD_ALTD_DATA_TX = 2619; // 1
+static const uint64_t SH_FLD_ALTD_DATA_TX_LEN = 2620; // 1
+static const uint64_t SH_FLD_ALTD_DATA_TX_OVERWRITE = 2621; // 1
+static const uint64_t SH_FLD_ALT_M = 2622; // 8
+static const uint64_t SH_FLD_ALT_M_LEN = 2623; // 8
+static const uint64_t SH_FLD_ALT_SEGSZ_DIS = 2624; // 1
+static const uint64_t SH_FLD_ALU_ADR = 2625; // 3
+static const uint64_t SH_FLD_ALU_ADR_LEN = 2626; // 3
+static const uint64_t SH_FLD_ALU_FLIP_ENDIAN_BIG = 2627; // 3
+static const uint64_t SH_FLD_ALU_FLIP_ENDIAN_LITTLE = 2628; // 3
+static const uint64_t SH_FLD_ALU_SAFE_LATENCY = 2629; // 3
+static const uint64_t SH_FLD_ALU_SZ = 2630; // 3
+static const uint64_t SH_FLD_ALU_TYPE = 2631; // 3
+static const uint64_t SH_FLD_ALU_TYPE_LEN = 2632; // 3
+static const uint64_t SH_FLD_ALWAYS_RTY = 2633; // 8
+static const uint64_t SH_FLD_AMAX_HIGH = 2634; // 6
+static const uint64_t SH_FLD_AMAX_HIGH_LEN = 2635; // 6
+static const uint64_t SH_FLD_AMAX_LOW = 2636; // 6
+static const uint64_t SH_FLD_AMAX_LOW_LEN = 2637; // 6
+static const uint64_t SH_FLD_AMIN_CFG = 2638; // 6
+static const uint64_t SH_FLD_AMIN_CFG_LEN = 2639; // 6
+static const uint64_t SH_FLD_AMIN_ENABLE_HDAC = 2640; // 4
+static const uint64_t SH_FLD_AMIN_TIMEOUT = 2641; // 6
+static const uint64_t SH_FLD_AMIN_TIMEOUT_LEN = 2642; // 6
+static const uint64_t SH_FLD_AMO_DRAM_SIZE_128B = 2643; // 8
+static const uint64_t SH_FLD_AMO_LIMIT = 2644; // 8
+static const uint64_t SH_FLD_AMO_LIMIT_LEN = 2645; // 8
+static const uint64_t SH_FLD_AMP0_FILTER_MASK = 2646; // 6
+static const uint64_t SH_FLD_AMP0_FILTER_MASK_LEN = 2647; // 6
+static const uint64_t SH_FLD_AMP1_FILTER_MASK = 2648; // 6
+static const uint64_t SH_FLD_AMP1_FILTER_MASK_LEN = 2649; // 6
+static const uint64_t SH_FLD_AMP_CFG = 2650; // 6
+static const uint64_t SH_FLD_AMP_CFG_LEN = 2651; // 6
+static const uint64_t SH_FLD_AMP_GAIN_CNT_MAX = 2652; // 6
+static const uint64_t SH_FLD_AMP_GAIN_CNT_MAX_LEN = 2653; // 6
+static const uint64_t SH_FLD_AMP_INIT_CFG = 2654; // 6
+static const uint64_t SH_FLD_AMP_INIT_CFG_LEN = 2655; // 6
+static const uint64_t SH_FLD_AMP_INIT_TIMEOUT = 2656; // 6
+static const uint64_t SH_FLD_AMP_INIT_TIMEOUT_LEN = 2657; // 6
+static const uint64_t SH_FLD_AMP_RECAL_CFG = 2658; // 6
+static const uint64_t SH_FLD_AMP_RECAL_CFG_LEN = 2659; // 6
+static const uint64_t SH_FLD_AMP_RECAL_TIMEOUT = 2660; // 6
+static const uint64_t SH_FLD_AMP_RECAL_TIMEOUT_LEN = 2661; // 6
+static const uint64_t SH_FLD_AMP_START_VAL = 2662; // 6
+static const uint64_t SH_FLD_AMP_START_VAL_LEN = 2663; // 6
+static const uint64_t SH_FLD_AMP_TIMEOUT = 2664; // 6
+static const uint64_t SH_FLD_AMP_TIMEOUT_LEN = 2665; // 6
+static const uint64_t SH_FLD_AMP_VAL = 2666; // 120
+static const uint64_t SH_FLD_AMP_VAL_LEN = 2667; // 120
+static const uint64_t SH_FLD_AMR = 2668; // 256
+static const uint64_t SH_FLD_AMR_LEN = 2669; // 256
+static const uint64_t SH_FLD_ANALOGTUNE = 2670; // 20
+static const uint64_t SH_FLD_ANALOGTUNE_LEN = 2671; // 20
+static const uint64_t SH_FLD_ANALOG_INPUT_STAB = 2672; // 8
+static const uint64_t SH_FLD_AND_TRIGGER_MODE1 = 2673; // 86
+static const uint64_t SH_FLD_AND_TRIGGER_MODE2 = 2674; // 86
+static const uint64_t SH_FLD_ANY_ERROR = 2675; // 1
+static const uint64_t SH_FLD_ANY_REQ_ACTIVE = 2676; // 12
+static const uint64_t SH_FLD_AP = 2677; // 8
+static const uint64_t SH_FLD_AP110_AP010_DELTA_MAX = 2678; // 6
+static const uint64_t SH_FLD_AP110_AP010_DELTA_MAX_LEN = 2679; // 6
+static const uint64_t SH_FLD_APB = 2680; // 8
+static const uint64_t SH_FLD_APB_MASK = 2681; // 8
+static const uint64_t SH_FLD_APC0_ENABLE = 2682; // 2
+static const uint64_t SH_FLD_APC0_SC_RDATA_PARITY_ERRHOLD = 2683; // 2
+static const uint64_t SH_FLD_APC1_ENABLE = 2684; // 2
+static const uint64_t SH_FLD_APCARY = 2685; // 4
+static const uint64_t SH_FLD_APCARY_ADDRESS = 2686; // 2
+static const uint64_t SH_FLD_APCARY_ADDRESS_LEN = 2687; // 2
+static const uint64_t SH_FLD_APCARY_LEN = 2688; // 4
+static const uint64_t SH_FLD_APCCTL_ADR_BAR_MODE = 2689; // 2
+static const uint64_t SH_FLD_APCCTL_CFG_BKILL_INC = 2690; // 2
+static const uint64_t SH_FLD_APCCTL_DISABLE_G = 2691; // 2
+static const uint64_t SH_FLD_APCCTL_DISABLE_LN = 2692; // 2
+static const uint64_t SH_FLD_APCCTL_DISABLE_NN_RN = 2693; // 2
+static const uint64_t SH_FLD_APCCTL_DISABLE_PSL_CMDQUEUE = 2694; // 2
+static const uint64_t SH_FLD_APCCTL_DISABLE_VG_NOT_SYS = 2695; // 2
+static const uint64_t SH_FLD_APCCTL_ENABLE_MASTER_RETRY_BACKOFF = 2696; // 2
+static const uint64_t SH_FLD_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT = 2697; // 2
+static const uint64_t SH_FLD_APCCTL_ENB_CRESP_EXAM = 2698; // 2
+static const uint64_t SH_FLD_APCCTL_ENB_FRC_ADDR13 = 2699; // 2
+static const uint64_t SH_FLD_APCCTL_HANG_ARE = 2700; // 2
+static const uint64_t SH_FLD_APCCTL_HANG_DEAD = 2701; // 2
+static const uint64_t SH_FLD_APCCTL_MAX_RETRY = 2702; // 2
+static const uint64_t SH_FLD_APCCTL_MAX_RETRY_LEN = 2703; // 2
+static const uint64_t SH_FLD_APCCTL_MEM_SEL_MODE = 2704; // 2
+static const uint64_t SH_FLD_APCCTL_P9_MODE = 2705; // 2
+static const uint64_t SH_FLD_APCCTL_PHB_SEL = 2706; // 2
+static const uint64_t SH_FLD_APCCTL_PHB_SEL_LEN = 2707; // 2
+static const uint64_t SH_FLD_APCCTL_SKIP_G = 2708; // 2
+static const uint64_t SH_FLD_APCCTL_SYSADDR = 2709; // 2
+static const uint64_t SH_FLD_APCCTL_SYSADDR_LEN = 2710; // 2
+static const uint64_t SH_FLD_APC_ARRAY_CMD_CE_ERPT = 2711; // 4
+static const uint64_t SH_FLD_APC_ARRAY_CMD_UE_ERPT = 2712; // 4
+static const uint64_t SH_FLD_APC_RDFSM_MASK = 2713; // 2
+static const uint64_t SH_FLD_APC_RDFSM_MASK_LEN = 2714; // 2
+static const uint64_t SH_FLD_APC_SC_RDATA_PARITY_ERRHOLD = 2715; // 2
+static const uint64_t SH_FLD_APX111_HIGH = 2716; // 6
+static const uint64_t SH_FLD_APX111_HIGH_LEN = 2717; // 6
+static const uint64_t SH_FLD_APX111_LOW = 2718; // 6
+static const uint64_t SH_FLD_APX111_LOW_LEN = 2719; // 6
+static const uint64_t SH_FLD_AP_LEN = 2720; // 8
+static const uint64_t SH_FLD_ARBITRATION_LOST_ERROR_0 = 2721; // 4
+static const uint64_t SH_FLD_ARBITRATION_LOST_ERROR_1 = 2722; // 2
+static const uint64_t SH_FLD_ARBITRATION_LOST_ERROR_2 = 2723; // 2
+static const uint64_t SH_FLD_ARBITRATION_LOST_ERROR_3 = 2724; // 2
+static const uint64_t SH_FLD_ARB_BLIF_COMPLETION_ERROR = 2725; // 6
+static const uint64_t SH_FLD_ARB_COMMON_FATAL_ERROR = 2726; // 6
+static const uint64_t SH_FLD_ARB_ECC_CORRECTABLE_ERROR = 2727; // 6
+static const uint64_t SH_FLD_ARB_ECC_INJECT_ERR = 2728; // 3
+static const uint64_t SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR = 2729; // 6
+static const uint64_t SH_FLD_ARB_EN_SEND_ALL_WRITES = 2730; // 1
+static const uint64_t SH_FLD_ARB_IODA_FATAL_ERROR = 2731; // 6
+static const uint64_t SH_FLD_ARB_MSI_ADDRESS_ERROR = 2732; // 6
+static const uint64_t SH_FLD_ARB_MSI_PE_MATCH_ERROR = 2733; // 6
+static const uint64_t SH_FLD_ARB_PCT_TIMEOUT_ERROR = 2734; // 6
+static const uint64_t SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG = 2735; // 6
+static const uint64_t SH_FLD_ARB_RCVD_FATAL_ERROR_MSG = 2736; // 6
+static const uint64_t SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG = 2737; // 6
+static const uint64_t SH_FLD_ARB_RTT_PENUM_INVALID_ERROR = 2738; // 6
+static const uint64_t SH_FLD_ARB_STALL = 2739; // 1
+static const uint64_t SH_FLD_ARB_STOP = 2740; // 1
+static const uint64_t SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR = 2741; // 6
+static const uint64_t SH_FLD_ARB_TLP_POISON_SIGNALED = 2742; // 6
+static const uint64_t SH_FLD_ARB_TVT_ERROR = 2743; // 6
+static const uint64_t SH_FLD_ARM_SEL = 2744; // 43
+static const uint64_t SH_FLD_ARM_SEL_LEN = 2745; // 43
+static const uint64_t SH_FLD_ARRAY_ADDR = 2746; // 6
+static const uint64_t SH_FLD_ARRAY_ADDR_LEN = 2747; // 6
+static const uint64_t SH_FLD_ARRAY_ECC_CE = 2748; // 2
+static const uint64_t SH_FLD_ARRAY_ECC_UE = 2749; // 2
+static const uint64_t SH_FLD_ARRAY_POINTER_SELECT = 2750; // 6
+static const uint64_t SH_FLD_ARRAY_POINTER_SELECT_LEN = 2751; // 6
+static const uint64_t SH_FLD_ARRAY_SELECT = 2752; // 1
+static const uint64_t SH_FLD_ARRAY_SELECT_LEN = 2753; // 1
+static const uint64_t SH_FLD_ARRAY_WRITE_ASSIST_EN = 2754; // 43
+static const uint64_t SH_FLD_ARX_TIMEOUT = 2755; // 1
+static const uint64_t SH_FLD_ARX_TIMEOUT_LEN = 2756; // 1
+static const uint64_t SH_FLD_ARY_SELECT_ATX_AIB = 2757; // 1
+static const uint64_t SH_FLD_ARY_SELECT_ATX_AIB_LEN = 2758; // 1
+static const uint64_t SH_FLD_ARY_SELECT_ATX_AT_SSA = 2759; // 1
+static const uint64_t SH_FLD_ARY_SELECT_ATX_BAR_SRAM = 2760; // 1
+static const uint64_t SH_FLD_ARY_SELECT_ATX_CMD_SSA = 2761; // 1
+static const uint64_t SH_FLD_ARY_SELECT_ATX_CMD_SSA_LEN = 2762; // 1
+static const uint64_t SH_FLD_ARY_SELECT_ATX_VPC_SSA = 2763; // 1
+static const uint64_t SH_FLD_ARY_SELECT_ATX_VPC_SSA_LEN = 2764; // 1
+static const uint64_t SH_FLD_ARY_SELECT_CMD_RSP_SRAM = 2765; // 1
+static const uint64_t SH_FLD_ARY_SELECT_CMD_VRQ_SRAM = 2766; // 1
+static const uint64_t SH_FLD_ARY_SELECT_CRESP_SRAM = 2767; // 1
+static const uint64_t SH_FLD_ASSIGN_DONE = 2768; // 1
+static const uint64_t SH_FLD_ASYNC_IF_ERROR = 2769; // 16
+static const uint64_t SH_FLD_ASYNC_INJ = 2770; // 16
+static const uint64_t SH_FLD_ASYNC_INJ_LEN = 2771; // 16
+static const uint64_t SH_FLD_ASYNC_MODE = 2772; // 6
+static const uint64_t SH_FLD_ASYNC_OBS = 2773; // 43
+static const uint64_t SH_FLD_ASYNC_TYPE = 2774; // 43
+static const uint64_t SH_FLD_AS_RCMD0_PARITY_ERR_ERRHOLD = 2775; // 2
+static const uint64_t SH_FLD_AS_REGS_PARITY_ERR_ERRHOLD = 2776; // 2
+static const uint64_t SH_FLD_AS_REG_RDATA_PERR_ERRHOLD = 2777; // 2
+static const uint64_t SH_FLD_AS_SM_ERRHOLD = 2778; // 2
+static const uint64_t SH_FLD_ATAG_0_15 = 2779; // 1
+static const uint64_t SH_FLD_ATAG_0_15_LEN = 2780; // 1
+static const uint64_t SH_FLD_ATOMIC_ALT_CE_INJ = 2781; // 2
+static const uint64_t SH_FLD_ATOMIC_ALT_CHIP_KILL_INJ = 2782; // 2
+static const uint64_t SH_FLD_ATOMIC_ALT_INJ_SYM_SEL = 2783; // 2
+static const uint64_t SH_FLD_ATOMIC_ALT_INJ_SYM_SEL_LEN = 2784; // 2
+static const uint64_t SH_FLD_ATOMIC_ALT_SUE_INJ = 2785; // 2
+static const uint64_t SH_FLD_ATOMIC_ALT_UE_INJ = 2786; // 2
+static const uint64_t SH_FLD_ATRMISS_ADDR = 2787; // 1
+static const uint64_t SH_FLD_ATRMISS_ADDR_LEN = 2788; // 1
+static const uint64_t SH_FLD_ATRMISS_BDF = 2789; // 1
+static const uint64_t SH_FLD_ATRMISS_BDF_LEN = 2790; // 1
+static const uint64_t SH_FLD_ATRMISS_ENA = 2791; // 1
+static const uint64_t SH_FLD_ATRMISS_FLAG_DMD = 2792; // 1
+static const uint64_t SH_FLD_ATRMISS_FLAG_FENCE = 2793; // 1
+static const uint64_t SH_FLD_ATRMISS_FLAG_MAP = 2794; // 1
+static const uint64_t SH_FLD_ATRMISS_FLAG_OTHER = 2795; // 1
+static const uint64_t SH_FLD_ATRMISS_FLAG_PREF = 2796; // 1
+static const uint64_t SH_FLD_ATRMISS_GPA = 2797; // 1
+static const uint64_t SH_FLD_ATRMISS_IRQENA = 2798; // 1
+static const uint64_t SH_FLD_ATRMISS_PASID = 2799; // 1
+static const uint64_t SH_FLD_ATRMISS_PASID_LEN = 2800; // 1
+static const uint64_t SH_FLD_ATRMISS_RETIRE = 2801; // 1
+static const uint64_t SH_FLD_ATRMISS_SECOND = 2802; // 1
+static const uint64_t SH_FLD_ATRMISS_TRIGGERED = 2803; // 1
+static const uint64_t SH_FLD_ATRR = 2804; // 3
+static const uint64_t SH_FLD_ATR_ARBSTATE = 2805; // 1
+static const uint64_t SH_FLD_ATR_ERR_INJ_PEND = 2806; // 1
+static const uint64_t SH_FLD_ATR_MISS_IRQ = 2807; // 1
+static const uint64_t SH_FLD_ATR_SM_STATE = 2808; // 1
+static const uint64_t SH_FLD_ATR_TIMEOUT = 2809; // 2
+static const uint64_t SH_FLD_ATR_TIMEOUT_LEN = 2810; // 1
+static const uint64_t SH_FLD_ATSD_BAD_TAG = 2811; // 1
+static const uint64_t SH_FLD_ATSD_SM_STATE = 2812; // 1
+static const uint64_t SH_FLD_ATSD_TIMEOUT = 2813; // 2
+static const uint64_t SH_FLD_ATSD_TIMEOUT_LEN = 2814; // 1
+static const uint64_t SH_FLD_ATSREQ = 2815; // 3
+static const uint64_t SH_FLD_ATSTSEL = 2816; // 17
+static const uint64_t SH_FLD_ATSTSEL_LEN = 2817; // 17
+static const uint64_t SH_FLD_ATSXLATE = 2818; // 12
+static const uint64_t SH_FLD_ATS_AT_EA_CE = 2819; // 1
+static const uint64_t SH_FLD_ATS_AT_EA_UE = 2820; // 1
+static const uint64_t SH_FLD_ATS_AT_RSPOUT_CE = 2821; // 1
+static const uint64_t SH_FLD_ATS_AT_RSPOUT_UE = 2822; // 1
+static const uint64_t SH_FLD_ATS_AT_TDRMEM_CE = 2823; // 1
+static const uint64_t SH_FLD_ATS_AT_TDRMEM_UE = 2824; // 1
+static const uint64_t SH_FLD_ATS_INVAL_IODA_TBL_SEL = 2825; // 1
+static const uint64_t SH_FLD_ATS_IODA_ADDR_PERR = 2826; // 1
+static const uint64_t SH_FLD_ATS_NPU_CTRL_PERR = 2827; // 1
+static const uint64_t SH_FLD_ATS_NPU_TOR_PERR = 2828; // 1
+static const uint64_t SH_FLD_ATS_RSVD_19 = 2829; // 1
+static const uint64_t SH_FLD_ATS_SYNC = 2830; // 3
+static const uint64_t SH_FLD_ATS_TCD_PERR = 2831; // 1
+static const uint64_t SH_FLD_ATS_TCE_CACHE_MULT_HIT_ERR = 2832; // 1
+static const uint64_t SH_FLD_ATS_TCE_PAGE_ACCESS_CA_ERR = 2833; // 1
+static const uint64_t SH_FLD_ATS_TCE_PAGE_ACCESS_TW_ERR = 2834; // 1
+static const uint64_t SH_FLD_ATS_TCE_REQ_TO_ERR = 2835; // 1
+static const uint64_t SH_FLD_ATS_TDR_PERR = 2836; // 1
+static const uint64_t SH_FLD_ATS_TVT_ADDR_RANGE_ERR = 2837; // 1
+static const uint64_t SH_FLD_ATS_TVT_ENTRY_INVALID = 2838; // 1
+static const uint64_t SH_FLD_ATS_TVT_PERR = 2839; // 1
+static const uint64_t SH_FLD_ATTENTION = 2840; // 1
+static const uint64_t SH_FLD_ATX_FOR_BLCK_UPD = 2841; // 1
+static const uint64_t SH_FLD_ATX_FOR_BLCK_UPD_LEN = 2842; // 1
+static const uint64_t SH_FLD_ATX_FOR_REGS = 2843; // 1
+static const uint64_t SH_FLD_ATX_FOR_REGS_LEN = 2844; // 1
+static const uint64_t SH_FLD_ATX_FOR_TCTXT_RSP_WR = 2845; // 1
+static const uint64_t SH_FLD_ATX_FOR_TCTXT_RSP_WR_LEN = 2846; // 1
+static const uint64_t SH_FLD_ATX_FOR_VPC_CI_LD = 2847; // 1
+static const uint64_t SH_FLD_ATX_FOR_VPC_CI_LD_LEN = 2848; // 1
+static const uint64_t SH_FLD_ATX_FOR_VPC_DMA = 2849; // 1
+static const uint64_t SH_FLD_ATX_FOR_VPC_DMA_LEN = 2850; // 1
+static const uint64_t SH_FLD_ATX_FOR_VPC_LD_RMT = 2851; // 1
+static const uint64_t SH_FLD_ATX_FOR_VPC_LD_RMT_LEN = 2852; // 1
+static const uint64_t SH_FLD_ATX_FOR_VPC_ST_LCL_VC = 2853; // 1
+static const uint64_t SH_FLD_ATX_FOR_VPC_ST_LCL_VC_LEN = 2854; // 1
+static const uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT = 2855; // 1
+static const uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT_LEN = 2856; // 1
+static const uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT_VC = 2857; // 1
+static const uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT_VC_LEN = 2858; // 1
+static const uint64_t SH_FLD_ATX_LIMIT_AT_DEM_IN_PIPE = 2859; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP = 2860; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP_LEN = 2861; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_EQD_DMA = 2862; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_EQD_DMA_LEN = 2863; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_IRQ = 2864; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_IRQ_LEN = 2865; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_IVC = 2866; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_IVC_LEN = 2867; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD = 2868; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD_LEN = 2869; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_REGS = 2870; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_REGS_LEN = 2871; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_SBC_DMA = 2872; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_SBC_DMA_LEN = 2873; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP = 2874; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP_LEN = 2875; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_TRIG_FWD = 2876; // 1
+static const uint64_t SH_FLD_ATX_PRIO_FOR_TRIG_FWD_LEN = 2877; // 1
+static const uint64_t SH_FLD_ATYPE = 2878; // 24
+static const uint64_t SH_FLD_ATYPE_LEN = 2879; // 24
+static const uint64_t SH_FLD_AT_EA_CE_ESR = 2880; // 1
+static const uint64_t SH_FLD_AT_EA_UE_ESR = 2881; // 1
+static const uint64_t SH_FLD_AT_TDRMEM_CE_ESR = 2882; // 1
+static const uint64_t SH_FLD_AT_TDRMEM_UE_ESR = 2883; // 1
+static const uint64_t SH_FLD_AUE = 2884; // 2
+static const uint64_t SH_FLD_AUE_LEN = 2885; // 2
+static const uint64_t SH_FLD_AUTOINC = 2886; // 12
+static const uint64_t SH_FLD_AUTO_INC = 2887; // 7
+static const uint64_t SH_FLD_AUTO_INCREMENT = 2888; // 3
+static const uint64_t SH_FLD_AUTO_INC_TRIG = 2889; // 6
+static const uint64_t SH_FLD_AUTO_INC_TRIG_LEN = 2890; // 6
+static const uint64_t SH_FLD_AUTO_POST_DECREMENT_FACES = 2891; // 1
+static const uint64_t SH_FLD_AUTO_POST_DECREMENT_PIB = 2892; // 1
+static const uint64_t SH_FLD_AUTO_PRE_INCREMENT_FACES = 2893; // 1
+static const uint64_t SH_FLD_AUTO_PRE_INCREMENT_PIB = 2894; // 1
+static const uint64_t SH_FLD_AUTO_RELOAD_N = 2895; // 2
+static const uint64_t SH_FLD_AUTO_STOP1_DISABLE = 2896; // 12
+static const uint64_t SH_FLD_AUTO_TDM_AND_NOT_OR = 2897; // 5
+static const uint64_t SH_FLD_AUTO_TDM_BW_DIFF = 2898; // 5
+static const uint64_t SH_FLD_AUTO_TDM_BW_DIFF_LEN = 2899; // 5
+static const uint64_t SH_FLD_AUTO_TDM_ERROR_RATE = 2900; // 5
+static const uint64_t SH_FLD_AUTO_TDM_ERROR_RATE_LEN = 2901; // 5
+static const uint64_t SH_FLD_AUTO_TDM_RX = 2902; // 5
+static const uint64_t SH_FLD_AUTO_TDM_TX = 2903; // 5
+static const uint64_t SH_FLD_AVA = 2904; // 8
+static const uint64_t SH_FLD_AVAIL_GROUPS = 2905; // 2
+static const uint64_t SH_FLD_AVAIL_GROUPS_LEN = 2906; // 2
+static const uint64_t SH_FLD_AVA_LEN = 2907; // 8
+static const uint64_t SH_FLD_AVG_CYCLE_SAMPLE = 2908; // 12
+static const uint64_t SH_FLD_AVG_CYCLE_SAMPLE_LEN = 2909; // 12
+static const uint64_t SH_FLD_AVG_FREQ_TSEL = 2910; // 12
+static const uint64_t SH_FLD_AVG_FREQ_TSEL_LEN = 2911; // 12
+static const uint64_t SH_FLD_AVS_SLAVE0 = 2912; // 1
+static const uint64_t SH_FLD_AVS_SLAVE1 = 2913; // 1
+static const uint64_t SH_FLD_AXFLOW_ERR = 2914; // 1
+static const uint64_t SH_FLD_AXFLOW_ERR_MASK = 2915; // 1
+static const uint64_t SH_FLD_AXPUSH_WRERR = 2916; // 1
+static const uint64_t SH_FLD_AXPUSH_WRERR_MASK = 2917; // 1
+static const uint64_t SH_FLD_AXRCV_DLO_ERR = 2918; // 1
+static const uint64_t SH_FLD_AXRCV_DLO_ERR_MASK = 2919; // 1
+static const uint64_t SH_FLD_AXRCV_DLO_TO = 2920; // 1
+static const uint64_t SH_FLD_AXRCV_DLO_TO_MASK = 2921; // 1
+static const uint64_t SH_FLD_AXRCV_RSVDATA_TO = 2922; // 1
+static const uint64_t SH_FLD_AXRCV_RSVDATA_TO_MASK = 2923; // 1
+static const uint64_t SH_FLD_AXSND_DHI_RTYTO = 2924; // 1
+static const uint64_t SH_FLD_AXSND_DHI_RTYTO_MASK = 2925; // 1
+static const uint64_t SH_FLD_AXSND_DLO_RTYTO = 2926; // 1
+static const uint64_t SH_FLD_AXSND_DLO_RTYTO_MASK = 2927; // 1
+static const uint64_t SH_FLD_AXSND_RSVERR = 2928; // 1
+static const uint64_t SH_FLD_AXSND_RSVERR_MASK = 2929; // 1
+static const uint64_t SH_FLD_AXSND_RSVTO = 2930; // 1
+static const uint64_t SH_FLD_AXSND_RSVTO_MASK = 2931; // 1
+static const uint64_t SH_FLD_A_AP = 2932; // 144
+static const uint64_t SH_FLD_A_AP_LEN = 2933; // 144
+static const uint64_t SH_FLD_A_BAD_DFE_CONV = 2934; // 144
+static const uint64_t SH_FLD_A_BANK_CONTROLS = 2935; // 48
+static const uint64_t SH_FLD_A_BANK_CONTROLS_LEN = 2936; // 48
+static const uint64_t SH_FLD_A_BIST_EN = 2937; // 6
+static const uint64_t SH_FLD_A_CONTROLS = 2938; // 120
+static const uint64_t SH_FLD_A_CONTROLS_LEN = 2939; // 120
+static const uint64_t SH_FLD_A_CTLE_COARSE = 2940; // 48
+static const uint64_t SH_FLD_A_CTLE_COARSE_LEN = 2941; // 48
+static const uint64_t SH_FLD_A_CTLE_GAIN = 2942; // 120
+static const uint64_t SH_FLD_A_CTLE_GAIN_LEN = 2943; // 120
+static const uint64_t SH_FLD_A_CTLE_PEAK = 2944; // 72
+static const uint64_t SH_FLD_A_CTLE_PEAK_LEN = 2945; // 72
+static const uint64_t SH_FLD_A_EVEN_INTEG_FINE_GAIN = 2946; // 120
+static const uint64_t SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN = 2947; // 120
+static const uint64_t SH_FLD_A_H10_VAL = 2948; // 72
+static const uint64_t SH_FLD_A_H10_VAL_LEN = 2949; // 72
+static const uint64_t SH_FLD_A_H11_VAL = 2950; // 72
+static const uint64_t SH_FLD_A_H11_VAL_LEN = 2951; // 72
+static const uint64_t SH_FLD_A_H12_VAL = 2952; // 72
+static const uint64_t SH_FLD_A_H12_VAL_LEN = 2953; // 72
+static const uint64_t SH_FLD_A_H1AP_AT_LIMIT = 2954; // 144
+static const uint64_t SH_FLD_A_H1ARATIO_VAL = 2955; // 72
+static const uint64_t SH_FLD_A_H1ARATIO_VAL_LEN = 2956; // 72
+static const uint64_t SH_FLD_A_H1CAL_EN = 2957; // 72
+static const uint64_t SH_FLD_A_H1CAL_VAL = 2958; // 72
+static const uint64_t SH_FLD_A_H1CAL_VAL_LEN = 2959; // 72
+static const uint64_t SH_FLD_A_H1E_VAL = 2960; // 120
+static const uint64_t SH_FLD_A_H1E_VAL_LEN = 2961; // 120
+static const uint64_t SH_FLD_A_H1O_VAL = 2962; // 120
+static const uint64_t SH_FLD_A_H1O_VAL_LEN = 2963; // 120
+static const uint64_t SH_FLD_A_H2E_VAL = 2964; // 72
+static const uint64_t SH_FLD_A_H2E_VAL_LEN = 2965; // 72
+static const uint64_t SH_FLD_A_H2O_VAL = 2966; // 72
+static const uint64_t SH_FLD_A_H2O_VAL_LEN = 2967; // 72
+static const uint64_t SH_FLD_A_H3E_VAL = 2968; // 72
+static const uint64_t SH_FLD_A_H3E_VAL_LEN = 2969; // 72
+static const uint64_t SH_FLD_A_H3O_VAL = 2970; // 72
+static const uint64_t SH_FLD_A_H3O_VAL_LEN = 2971; // 72
+static const uint64_t SH_FLD_A_H4E_VAL = 2972; // 72
+static const uint64_t SH_FLD_A_H4E_VAL_LEN = 2973; // 72
+static const uint64_t SH_FLD_A_H4O_VAL = 2974; // 72
+static const uint64_t SH_FLD_A_H4O_VAL_LEN = 2975; // 72
+static const uint64_t SH_FLD_A_H5E_VAL = 2976; // 72
+static const uint64_t SH_FLD_A_H5E_VAL_LEN = 2977; // 72
+static const uint64_t SH_FLD_A_H5O_VAL = 2978; // 72
+static const uint64_t SH_FLD_A_H5O_VAL_LEN = 2979; // 72
+static const uint64_t SH_FLD_A_H6_VAL = 2980; // 72
+static const uint64_t SH_FLD_A_H6_VAL_LEN = 2981; // 72
+static const uint64_t SH_FLD_A_H7_VAL = 2982; // 72
+static const uint64_t SH_FLD_A_H7_VAL_LEN = 2983; // 72
+static const uint64_t SH_FLD_A_H8_VAL = 2984; // 72
+static const uint64_t SH_FLD_A_H8_VAL_LEN = 2985; // 72
+static const uint64_t SH_FLD_A_H9_VAL = 2986; // 72
+static const uint64_t SH_FLD_A_H9_VAL_LEN = 2987; // 72
+static const uint64_t SH_FLD_A_INTEG_COARSE_GAIN = 2988; // 120
+static const uint64_t SH_FLD_A_INTEG_COARSE_GAIN_LEN = 2989; // 120
+static const uint64_t SH_FLD_A_ODD_INTEG_FINE_GAIN = 2990; // 120
+static const uint64_t SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN = 2991; // 120
+static const uint64_t SH_FLD_A_OFFSET_E0 = 2992; // 120
+static const uint64_t SH_FLD_A_OFFSET_E0_LEN = 2993; // 120
+static const uint64_t SH_FLD_A_OFFSET_E1 = 2994; // 120
+static const uint64_t SH_FLD_A_OFFSET_E1_LEN = 2995; // 120
+static const uint64_t SH_FLD_A_OFFSET_O0 = 2996; // 120
+static const uint64_t SH_FLD_A_OFFSET_O0_LEN = 2997; // 120
+static const uint64_t SH_FLD_A_OFFSET_O1 = 2998; // 120
+static const uint64_t SH_FLD_A_OFFSET_O1_LEN = 2999; // 120
+static const uint64_t SH_FLD_A_PATH_OFF_EVEN = 3000; // 144
+static const uint64_t SH_FLD_A_PATH_OFF_EVEN_LEN = 3001; // 144
+static const uint64_t SH_FLD_A_PATH_OFF_ODD = 3002; // 144
+static const uint64_t SH_FLD_A_PATH_OFF_ODD_LEN = 3003; // 144
+static const uint64_t SH_FLD_A_PR_DFE_CLKADJ = 3004; // 120
+static const uint64_t SH_FLD_A_PR_DFE_CLKADJ_LEN = 3005; // 120
+static const uint64_t SH_FLD_B = 3006; // 8
+static const uint64_t SH_FLD_B0_63 = 3007; // 2
+static const uint64_t SH_FLD_B0_63_LEN = 3008; // 2
+static const uint64_t SH_FLD_B64_87 = 3009; // 2
+static const uint64_t SH_FLD_B64_87_LEN = 3010; // 2
+static const uint64_t SH_FLD_BACKUP_SEEPROM_SELECT = 3011; // 1
+static const uint64_t SH_FLD_BAD_128K_VP_OP = 3012; // 1
+static const uint64_t SH_FLD_BAD_ARRAY_ADDRESS_FACES = 3013; // 1
+static const uint64_t SH_FLD_BAD_ARRAY_ADDR_FACES = 3014; // 1
+static const uint64_t SH_FLD_BAD_ARRAY_ADDR_PIB = 3015; // 1
+static const uint64_t SH_FLD_BAD_BLOCK_LOCK = 3016; // 96
+static const uint64_t SH_FLD_BAD_BUS_LANE_ERR_CNTR_DIS_CLR = 3017; // 4
+static const uint64_t SH_FLD_BAD_DESKEW = 3018; // 96
+static const uint64_t SH_FLD_BAD_EYE_OPT_BER = 3019; // 96
+static const uint64_t SH_FLD_BAD_EYE_OPT_DDC = 3020; // 96
+static const uint64_t SH_FLD_BAD_EYE_OPT_HEIGHT = 3021; // 96
+static const uint64_t SH_FLD_BAD_EYE_OPT_WIDTH = 3022; // 96
+static const uint64_t SH_FLD_BAD_LANE1 = 3023; // 4
+static const uint64_t SH_FLD_BAD_LANE1_GCRMSG = 3024; // 4
+static const uint64_t SH_FLD_BAD_LANE1_GCRMSG_LEN = 3025; // 4
+static const uint64_t SH_FLD_BAD_LANE1_LEN = 3026; // 4
+static const uint64_t SH_FLD_BAD_LANE2 = 3027; // 4
+static const uint64_t SH_FLD_BAD_LANE2_GCRMSG = 3028; // 4
+static const uint64_t SH_FLD_BAD_LANE2_GCRMSG_LEN = 3029; // 4
+static const uint64_t SH_FLD_BAD_LANE2_LEN = 3030; // 4
+static const uint64_t SH_FLD_BAD_LANE_CODE = 3031; // 4
+static const uint64_t SH_FLD_BAD_LANE_CODE_GCRMSG = 3032; // 4
+static const uint64_t SH_FLD_BAD_LANE_CODE_GCRMSG_LEN = 3033; // 4
+static const uint64_t SH_FLD_BAD_LANE_CODE_LEN = 3034; // 4
+static const uint64_t SH_FLD_BAD_LANE_DURATION = 3035; // 2
+static const uint64_t SH_FLD_BAD_LANE_DURATION_LEN = 3036; // 2
+static const uint64_t SH_FLD_BAD_LANE_MAX = 3037; // 2
+static const uint64_t SH_FLD_BAD_LANE_MAX_LEN = 3038; // 2
+static const uint64_t SH_FLD_BAD_SKEW = 3039; // 96
+static const uint64_t SH_FLD_BANDSEL = 3040; // 20
+static const uint64_t SH_FLD_BANDSEL_LEN = 3041; // 20
+static const uint64_t SH_FLD_BANK = 3042; // 24
+static const uint64_t SH_FLD_BANK0_BIT_MAP = 3043; // 8
+static const uint64_t SH_FLD_BANK0_BIT_MAP_LEN = 3044; // 8
+static const uint64_t SH_FLD_BANK1_BIT_MAP = 3045; // 8
+static const uint64_t SH_FLD_BANK1_BIT_MAP_LEN = 3046; // 8
+static const uint64_t SH_FLD_BANK2_BIT_MAP = 3047; // 8
+static const uint64_t SH_FLD_BANK2_BIT_MAP_LEN = 3048; // 8
+static const uint64_t SH_FLD_BANK_GROUP0_BIT_MAP = 3049; // 8
+static const uint64_t SH_FLD_BANK_GROUP0_BIT_MAP_LEN = 3050; // 8
+static const uint64_t SH_FLD_BANK_GROUP1_BIT_MAP = 3051; // 8
+static const uint64_t SH_FLD_BANK_GROUP1_BIT_MAP_LEN = 3052; // 8
+static const uint64_t SH_FLD_BANK_ON_RUNN_MATCH = 3053; // 43
+static const uint64_t SH_FLD_BANK_PDWN = 3054; // 48
+static const uint64_t SH_FLD_BANK_PDWN_LEN = 3055; // 48
+static const uint64_t SH_FLD_BANK_SEL_A = 3056; // 48
+static const uint64_t SH_FLD_BAR = 3057; // 6
+static const uint64_t SH_FLD_BAR1_EN = 3058; // 4
+static const uint64_t SH_FLD_BAR1_MS_GROUP_CHIP = 3059; // 2
+static const uint64_t SH_FLD_BAR1_MS_GROUP_CHIP_LEN = 3060; // 2
+static const uint64_t SH_FLD_BAR1_SIZE = 3061; // 2
+static const uint64_t SH_FLD_BAR1_SIZE_LEN = 3062; // 2
+static const uint64_t SH_FLD_BAR1_STARTING_ADDRESS = 3063; // 4
+static const uint64_t SH_FLD_BAR1_STARTING_ADDRESS_LEN = 3064; // 4
+static const uint64_t SH_FLD_BAR1_SYSTEM = 3065; // 2
+static const uint64_t SH_FLD_BAR1_SYSTEM_LEN = 3066; // 2
+static const uint64_t SH_FLD_BARSEL = 3067; // 12
+static const uint64_t SH_FLD_BAR_LEN = 3068; // 6
+static const uint64_t SH_FLD_BAR_PE = 3069; // 4
+static const uint64_t SH_FLD_BAR_PIB_ON_ERROR1 = 3070; // 1
+static const uint64_t SH_FLD_BAR_PIB_ON_ERROR2 = 3071; // 1
+static const uint64_t SH_FLD_BAR_PIB_ON_ERROR3 = 3072; // 1
+static const uint64_t SH_FLD_BAR_PIB_ON_ERROR4 = 3073; // 1
+static const uint64_t SH_FLD_BAR_PIB_ON_ERROR5 = 3074; // 1
+static const uint64_t SH_FLD_BAR_PIB_ON_ERROR6 = 3075; // 1
+static const uint64_t SH_FLD_BAR_PIB_ON_ERROR7 = 3076; // 1
+static const uint64_t SH_FLD_BASE = 3077; // 26
+static const uint64_t SH_FLD_BASE_ADDR = 3078; // 2
+static const uint64_t SH_FLD_BASE_ADDR_LEN = 3079; // 2
+static const uint64_t SH_FLD_BASE_IDLE_COUNT = 3080; // 8
+static const uint64_t SH_FLD_BASE_IDLE_COUNT_LEN = 3081; // 8
+static const uint64_t SH_FLD_BASE_LEN = 3082; // 26
+static const uint64_t SH_FLD_BASE_UPPER_BITS = 3083; // 1
+static const uint64_t SH_FLD_BASE_UPPER_BITS_LEN = 3084; // 1
+static const uint64_t SH_FLD_BBUF_AIDX = 3085; // 3
+static const uint64_t SH_FLD_BBUF_AIDX_LEN = 3086; // 3
+static const uint64_t SH_FLD_BBUF_RSRC = 3087; // 3
+static const uint64_t SH_FLD_BBUF_RSRC_LEN = 3088; // 3
+static const uint64_t SH_FLD_BBUF_WSRC = 3089; // 3
+static const uint64_t SH_FLD_BBUF_WSRC_LEN = 3090; // 3
+static const uint64_t SH_FLD_BBWR_MASK = 3091; // 3
+static const uint64_t SH_FLD_BBWR_MASK_LEN = 3092; // 3
+static const uint64_t SH_FLD_BCAST_DONE = 3093; // 1
+static const uint64_t SH_FLD_BCDE_CE = 3094; // 1
+static const uint64_t SH_FLD_BCDE_CE_MASK = 3095; // 1
+static const uint64_t SH_FLD_BCDE_OCITRANS = 3096; // 1
+static const uint64_t SH_FLD_BCDE_OCITRANS_LEN = 3097; // 1
+static const uint64_t SH_FLD_BCDE_OCI_DATERR = 3098; // 1
+static const uint64_t SH_FLD_BCDE_OCI_DATERR_MASK = 3099; // 1
+static const uint64_t SH_FLD_BCDE_PB_ACK_DEAD = 3100; // 1
+static const uint64_t SH_FLD_BCDE_PB_ACK_DEAD_MASK = 3101; // 1
+static const uint64_t SH_FLD_BCDE_PB_ADRERR = 3102; // 1
+static const uint64_t SH_FLD_BCDE_PB_ADRERR_MASK = 3103; // 1
+static const uint64_t SH_FLD_BCDE_RDDATATO_ERR = 3104; // 1
+static const uint64_t SH_FLD_BCDE_RDDATATO_ERR_MASK = 3105; // 1
+static const uint64_t SH_FLD_BCDE_SETUP_ERR = 3106; // 1
+static const uint64_t SH_FLD_BCDE_SETUP_ERR_MASK = 3107; // 1
+static const uint64_t SH_FLD_BCDE_SUE_ERR = 3108; // 1
+static const uint64_t SH_FLD_BCDE_SUE_ERR_MASK = 3109; // 1
+static const uint64_t SH_FLD_BCDE_UE_ERR = 3110; // 1
+static const uint64_t SH_FLD_BCDE_UE_ERR_MASK = 3111; // 1
+static const uint64_t SH_FLD_BCESCR_OVERRIDE_EN = 3112; // 12
+static const uint64_t SH_FLD_BCE_BUSY_HIGH = 3113; // 12
+static const uint64_t SH_FLD_BCE_BUSY_LOW = 3114; // 12
+static const uint64_t SH_FLD_BCE_ERROR = 3115; // 13
+static const uint64_t SH_FLD_BCE_TIMEOUT = 3116; // 24
+static const uint64_t SH_FLD_BCUE_OCITRANS = 3117; // 1
+static const uint64_t SH_FLD_BCUE_OCITRANS_LEN = 3118; // 1
+static const uint64_t SH_FLD_BCUE_OCI_DATERR = 3119; // 1
+static const uint64_t SH_FLD_BCUE_OCI_DATERR_MASK = 3120; // 1
+static const uint64_t SH_FLD_BCUE_PB_ACK_DEAD = 3121; // 1
+static const uint64_t SH_FLD_BCUE_PB_ACK_DEAD_MASK = 3122; // 1
+static const uint64_t SH_FLD_BCUE_PB_ADRERR = 3123; // 1
+static const uint64_t SH_FLD_BCUE_PB_ADRERR_MASK = 3124; // 1
+static const uint64_t SH_FLD_BCUE_SETUP_ERR = 3125; // 1
+static const uint64_t SH_FLD_BCUE_SETUP_ERR_MASK = 3126; // 1
+static const uint64_t SH_FLD_BDF = 3127; // 52
+static const uint64_t SH_FLD_BDF2PE_00 = 3128; // 1
+static const uint64_t SH_FLD_BDF2PE_01 = 3129; // 1
+static const uint64_t SH_FLD_BDF2PE_02 = 3130; // 1
+static const uint64_t SH_FLD_BDF2PE_10 = 3131; // 1
+static const uint64_t SH_FLD_BDF2PE_11 = 3132; // 1
+static const uint64_t SH_FLD_BDF2PE_12 = 3133; // 1
+static const uint64_t SH_FLD_BDF2PE_20 = 3134; // 1
+static const uint64_t SH_FLD_BDF2PE_21 = 3135; // 1
+static const uint64_t SH_FLD_BDF2PE_22 = 3136; // 1
+static const uint64_t SH_FLD_BDF2PE_30 = 3137; // 1
+static const uint64_t SH_FLD_BDF2PE_31 = 3138; // 1
+static const uint64_t SH_FLD_BDF2PE_32 = 3139; // 1
+static const uint64_t SH_FLD_BDF2PE_40 = 3140; // 1
+static const uint64_t SH_FLD_BDF2PE_41 = 3141; // 1
+static const uint64_t SH_FLD_BDF2PE_42 = 3142; // 1
+static const uint64_t SH_FLD_BDF2PE_50 = 3143; // 1
+static const uint64_t SH_FLD_BDF2PE_51 = 3144; // 1
+static const uint64_t SH_FLD_BDF2PE_52 = 3145; // 1
+static const uint64_t SH_FLD_BDF_LEN = 3146; // 52
+static const uint64_t SH_FLD_BE = 3147; // 6
+static const uint64_t SH_FLD_BEAT_NUM = 3148; // 1
+static const uint64_t SH_FLD_BEAT_NUM_ERR = 3149; // 1
+static const uint64_t SH_FLD_BEAT_REC = 3150; // 1
+static const uint64_t SH_FLD_BEAT_REC_ERR = 3151; // 1
+static const uint64_t SH_FLD_BENIGN_PTR_DATA = 3152; // 2
+static const uint64_t SH_FLD_BER_CFG = 3153; // 120
+static const uint64_t SH_FLD_BER_CFG_LEN = 3154; // 120
+static const uint64_t SH_FLD_BER_CLR_COUNT_ON_READ_EN = 3155; // 6
+static const uint64_t SH_FLD_BER_CLR_TIMER_ON_READ_EN = 3156; // 6
+static const uint64_t SH_FLD_BER_COUNT_FREEZE_EN = 3157; // 6
+static const uint64_t SH_FLD_BER_COUNT_SEL = 3158; // 6
+static const uint64_t SH_FLD_BER_COUNT_SEL_LEN = 3159; // 6
+static const uint64_t SH_FLD_BER_DPIPE_MUX_SEL = 3160; // 120
+static const uint64_t SH_FLD_BER_EN = 3161; // 6
+static const uint64_t SH_FLD_BER_TIMEOUT = 3162; // 6
+static const uint64_t SH_FLD_BER_TIMEOUT_LEN = 3163; // 6
+static const uint64_t SH_FLD_BER_TIMER_FREEZE_EN = 3164; // 6
+static const uint64_t SH_FLD_BER_TIMER_SEL = 3165; // 6
+static const uint64_t SH_FLD_BER_TIMER_SEL_LEN = 3166; // 6
+static const uint64_t SH_FLD_BE_ACC_ERROR_0 = 3167; // 4
+static const uint64_t SH_FLD_BE_ACC_ERROR_1 = 3168; // 2
+static const uint64_t SH_FLD_BE_ACC_ERROR_2 = 3169; // 2
+static const uint64_t SH_FLD_BE_ACC_ERROR_3 = 3170; // 2
+static const uint64_t SH_FLD_BE_OV_ERROR_0 = 3171; // 4
+static const uint64_t SH_FLD_BE_OV_ERROR_1 = 3172; // 2
+static const uint64_t SH_FLD_BE_OV_ERROR_2 = 3173; // 2
+static const uint64_t SH_FLD_BE_OV_ERROR_3 = 3174; // 2
+static const uint64_t SH_FLD_BGOFFSET = 3175; // 14
+static const uint64_t SH_FLD_BGOFFSET_LEN = 3176; // 14
+static const uint64_t SH_FLD_BG_SCAN_RATE = 3177; // 3
+static const uint64_t SH_FLD_BG_SCAN_RATE_LEN = 3178; // 3
+static const uint64_t SH_FLD_BHR_DIR_STATE = 3179; // 2
+static const uint64_t SH_FLD_BHR_DIR_STATE_LEN = 3180; // 2
+static const uint64_t SH_FLD_BIG_RSP = 3181; // 1
+static const uint64_t SH_FLD_BIG_STEP = 3182; // 8
+static const uint64_t SH_FLD_BIG_STEP_LEN = 3183; // 8
+static const uint64_t SH_FLD_BISTCLK_EN = 3184; // 2
+static const uint64_t SH_FLD_BISTCLK_EN_LEN = 3185; // 2
+static const uint64_t SH_FLD_BIST_BIT_FAIL_TH = 3186; // 1
+static const uint64_t SH_FLD_BIST_BIT_FAIL_TH_LEN = 3187; // 1
+static const uint64_t SH_FLD_BIST_BUS_DATA_MODE = 3188; // 6
+static const uint64_t SH_FLD_BIST_COMPLETE = 3189; // 1
+static const uint64_t SH_FLD_BIST_CUPLL_LOCK_CHECK_EN = 3190; // 6
+static const uint64_t SH_FLD_BIST_CU_PLL_ERR = 3191; // 4
+static const uint64_t SH_FLD_BIST_DONE = 3192; // 6
+static const uint64_t SH_FLD_BIST_EN = 3193; // 13
+static const uint64_t SH_FLD_BIST_ENABLE = 3194; // 1
+static const uint64_t SH_FLD_BIST_ERR = 3195; // 96
+static const uint64_t SH_FLD_BIST_ERROR = 3196; // 1
+static const uint64_t SH_FLD_BIST_ERROR_LEN = 3197; // 1
+static const uint64_t SH_FLD_BIST_ERR_A = 3198; // 48
+static const uint64_t SH_FLD_BIST_ERR_B = 3199; // 48
+static const uint64_t SH_FLD_BIST_ERR_E = 3200; // 48
+static const uint64_t SH_FLD_BIST_EXT_START_MODE = 3201; // 6
+static const uint64_t SH_FLD_BIST_EYE_A_WIDTH = 3202; // 6
+static const uint64_t SH_FLD_BIST_EYE_A_WIDTH_LEN = 3203; // 6
+static const uint64_t SH_FLD_BIST_EYE_B_WIDTH = 3204; // 6
+static const uint64_t SH_FLD_BIST_EYE_B_WIDTH_LEN = 3205; // 6
+static const uint64_t SH_FLD_BIST_INIT_DISABLE = 3206; // 6
+static const uint64_t SH_FLD_BIST_INIT_DISABLE_LEN = 3207; // 6
+static const uint64_t SH_FLD_BIST_INIT_DONE = 3208; // 6
+static const uint64_t SH_FLD_BIST_JITTER_PULSE_SEL = 3209; // 4
+static const uint64_t SH_FLD_BIST_JITTER_PULSE_SEL_LEN = 3210; // 4
+static const uint64_t SH_FLD_BIST_LL_ERR = 3211; // 2
+static const uint64_t SH_FLD_BIST_LL_TEST_EN = 3212; // 2
+static const uint64_t SH_FLD_BIST_MIN_EYE_WIDTH = 3213; // 6
+static const uint64_t SH_FLD_BIST_MIN_EYE_WIDTH_LEN = 3214; // 6
+static const uint64_t SH_FLD_BIST_NO_EDGE_DET = 3215; // 6
+static const uint64_t SH_FLD_BIST_PLL_LOCK_TIMEOUT = 3216; // 4
+static const uint64_t SH_FLD_BIST_PLL_LOCK_TIMEOUT_LEN = 3217; // 4
+static const uint64_t SH_FLD_BIST_PRBS_PROP_TIME = 3218; // 6
+static const uint64_t SH_FLD_BIST_PRBS_PROP_TIME_LEN = 3219; // 6
+static const uint64_t SH_FLD_BIST_PRBS_TEST_TIME = 3220; // 6
+static const uint64_t SH_FLD_BIST_PRBS_TEST_TIME_LEN = 3221; // 6
+static const uint64_t SH_FLD_BIST_STORE_EYES_BANK_SEL = 3222; // 6
+static const uint64_t SH_FLD_BIST_STORE_EYES_BANK_SEL_LEN = 3223; // 6
+static const uint64_t SH_FLD_BIST_STORE_EYES_LANE_SEL = 3224; // 6
+static const uint64_t SH_FLD_BIST_STORE_EYES_LANE_SEL_LEN = 3225; // 6
+static const uint64_t SH_FLD_BITS = 3226; // 27
+static const uint64_t SH_FLD_BITSEL = 3227; // 4
+static const uint64_t SH_FLD_BITSEL_LEN = 3228; // 4
+static const uint64_t SH_FLD_BITS_LEN = 3229; // 27
+static const uint64_t SH_FLD_BIT_RATE_DIVISOR_0 = 3230; // 6
+static const uint64_t SH_FLD_BIT_RATE_DIVISOR_0_LEN = 3231; // 6
+static const uint64_t SH_FLD_BIT_RATE_DIVISOR_1 = 3232; // 3
+static const uint64_t SH_FLD_BIT_RATE_DIVISOR_1_LEN = 3233; // 3
+static const uint64_t SH_FLD_BIT_RATE_DIVISOR_2 = 3234; // 3
+static const uint64_t SH_FLD_BIT_RATE_DIVISOR_2_LEN = 3235; // 3
+static const uint64_t SH_FLD_BIT_RATE_DIVISOR_3 = 3236; // 3
+static const uint64_t SH_FLD_BIT_RATE_DIVISOR_3_LEN = 3237; // 3
+static const uint64_t SH_FLD_BIT_RATE_DIVISOR_VALUE = 3238; // 1
+static const uint64_t SH_FLD_BIT_RATE_DIVISOR_VALUE_LEN = 3239; // 1
+static const uint64_t SH_FLD_BKINV_INTERLOCK_DIS = 3240; // 1
+static const uint64_t SH_FLD_BKLG0 = 3241; // 1
+static const uint64_t SH_FLD_BKLG0_LEN = 3242; // 1
+static const uint64_t SH_FLD_BKLG1 = 3243; // 1
+static const uint64_t SH_FLD_BKLG1_LEN = 3244; // 1
+static const uint64_t SH_FLD_BKLG2 = 3245; // 1
+static const uint64_t SH_FLD_BKLG2_LEN = 3246; // 1
+static const uint64_t SH_FLD_BKLG3 = 3247; // 1
+static const uint64_t SH_FLD_BKLG3_LEN = 3248; // 1
+static const uint64_t SH_FLD_BKLG4 = 3249; // 1
+static const uint64_t SH_FLD_BKLG4_LEN = 3250; // 1
+static const uint64_t SH_FLD_BKLG5 = 3251; // 1
+static const uint64_t SH_FLD_BKLG5_LEN = 3252; // 1
+static const uint64_t SH_FLD_BKLG6 = 3253; // 1
+static const uint64_t SH_FLD_BKLG6_LEN = 3254; // 1
+static const uint64_t SH_FLD_BKLG7 = 3255; // 1
+static const uint64_t SH_FLD_BKLG7_LEN = 3256; // 1
+static const uint64_t SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR = 3257; // 6
+static const uint64_t SH_FLD_BLK_UPDT_DONE = 3258; // 1
+static const uint64_t SH_FLD_BLOCK = 3259; // 24
+static const uint64_t SH_FLD_BLOCKID = 3260; // 15
+static const uint64_t SH_FLD_BLOCKID_LEN = 3261; // 15
+static const uint64_t SH_FLD_BLOCKY0 = 3262; // 24
+static const uint64_t SH_FLD_BLOCKY1 = 3263; // 24
+static const uint64_t SH_FLD_BLOCK_ACTIVE = 3264; // 6
+static const uint64_t SH_FLD_BLOCK_CMD_OVERLAP = 3265; // 1
+static const uint64_t SH_FLD_BLOCK_INTR_INPUTS = 3266; // 24
+static const uint64_t SH_FLD_BLOCK_LEN = 3267; // 24
+static const uint64_t SH_FLD_BLOCK_MUX_PORT_SEL = 3268; // 2
+static const uint64_t SH_FLD_BLOCK_MUX_PORT_SEL_LEN = 3269; // 2
+static const uint64_t SH_FLD_BLOCK_SEL = 3270; // 2
+static const uint64_t SH_FLD_BLOCK_SEL_LEN = 3271; // 2
+static const uint64_t SH_FLD_BNDY = 3272; // 43
+static const uint64_t SH_FLD_BOOT_VECTOR_WORD0 = 3273; // 1
+static const uint64_t SH_FLD_BOOT_VECTOR_WORD0_LEN = 3274; // 1
+static const uint64_t SH_FLD_BOOT_VECTOR_WORD1 = 3275; // 1
+static const uint64_t SH_FLD_BOOT_VECTOR_WORD1_LEN = 3276; // 1
+static const uint64_t SH_FLD_BOOT_VECTOR_WORD2 = 3277; // 1
+static const uint64_t SH_FLD_BOOT_VECTOR_WORD2_LEN = 3278; // 1
+static const uint64_t SH_FLD_BOOT_VECTOR_WORD3 = 3279; // 1
+static const uint64_t SH_FLD_BOOT_VECTOR_WORD3_LEN = 3280; // 1
+static const uint64_t SH_FLD_BRAZOS = 3281; // 1
+static const uint64_t SH_FLD_BREAKPOINT_ERROR = 3282; // 1
+static const uint64_t SH_FLD_BRICK = 3283; // 16
+static const uint64_t SH_FLD_BRICK_DEBUG_MODE = 3284; // 6
+static const uint64_t SH_FLD_BRICK_ENABLE = 3285; // 6
+static const uint64_t SH_FLD_BRIDGE_ENABLE = 3286; // 1
+static const uint64_t SH_FLD_BRINGUP = 3287; // 4
+static const uint64_t SH_FLD_BRINGUP_LEN = 3288; // 4
+static const uint64_t SH_FLD_BRK0 = 3289; // 1
+static const uint64_t SH_FLD_BRK0_CLUSTER = 3290; // 1
+static const uint64_t SH_FLD_BRK0_CLUSTER_LEN = 3291; // 1
+static const uint64_t SH_FLD_BRK0_NVL = 3292; // 3
+static const uint64_t SH_FLD_BRK0_RLX = 3293; // 3
+static const uint64_t SH_FLD_BRK1 = 3294; // 1
+static const uint64_t SH_FLD_BRK1_CLUSTER = 3295; // 1
+static const uint64_t SH_FLD_BRK1_CLUSTER_LEN = 3296; // 1
+static const uint64_t SH_FLD_BRK1_NVL = 3297; // 3
+static const uint64_t SH_FLD_BRK1_RLX = 3298; // 3
+static const uint64_t SH_FLD_BRK2 = 3299; // 1
+static const uint64_t SH_FLD_BRK2_CLUSTER = 3300; // 1
+static const uint64_t SH_FLD_BRK2_CLUSTER_LEN = 3301; // 1
+static const uint64_t SH_FLD_BRK3 = 3302; // 1
+static const uint64_t SH_FLD_BRK3_CLUSTER = 3303; // 1
+static const uint64_t SH_FLD_BRK3_CLUSTER_LEN = 3304; // 1
+static const uint64_t SH_FLD_BRK4 = 3305; // 1
+static const uint64_t SH_FLD_BRK4_CLUSTER = 3306; // 1
+static const uint64_t SH_FLD_BRK4_CLUSTER_LEN = 3307; // 1
+static const uint64_t SH_FLD_BRK5 = 3308; // 1
+static const uint64_t SH_FLD_BRK5_CLUSTER = 3309; // 1
+static const uint64_t SH_FLD_BRK5_CLUSTER_LEN = 3310; // 1
+static const uint64_t SH_FLD_BROADCAST_SYNC_EN = 3311; // 2
+static const uint64_t SH_FLD_BROADCAST_SYNC_WAIT = 3312; // 2
+static const uint64_t SH_FLD_BROADCAST_SYNC_WAIT_LEN = 3313; // 2
+static const uint64_t SH_FLD_BUF0_REG_DATA0 = 3314; // 2
+static const uint64_t SH_FLD_BUF0_REG_DATA0_LEN = 3315; // 2
+static const uint64_t SH_FLD_BUF1_REG_DATA0 = 3316; // 1
+static const uint64_t SH_FLD_BUF1_REG_DATA0_LEN = 3317; // 1
+static const uint64_t SH_FLD_BUF1_REG_DATA1 = 3318; // 1
+static const uint64_t SH_FLD_BUF1_REG_DATA1_LEN = 3319; // 1
+static const uint64_t SH_FLD_BUFFER = 3320; // 12
+static const uint64_t SH_FLD_BUFFER_OVERRUN = 3321; // 8
+static const uint64_t SH_FLD_BUFFER_STATUS = 3322; // 6
+static const uint64_t SH_FLD_BUFFER_STATUS_LEN = 3323; // 6
+static const uint64_t SH_FLD_BUF_ALLOC_A = 3324; // 4
+static const uint64_t SH_FLD_BUF_ALLOC_B = 3325; // 4
+static const uint64_t SH_FLD_BUF_ALLOC_C = 3326; // 4
+static const uint64_t SH_FLD_BUF_ALLOC_W = 3327; // 4
+static const uint64_t SH_FLD_BUF_INVALIDATE_CTL = 3328; // 4
+static const uint64_t SH_FLD_BURST_WINDOW = 3329; // 8
+static const uint64_t SH_FLD_BURST_WINDOW_LEN = 3330; // 8
+static const uint64_t SH_FLD_BUSY = 3331; // 44
+static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD0 = 3332; // 8
+static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD0_LEN = 3333; // 8
+static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD1 = 3334; // 8
+static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD1_LEN = 3335; // 8
+static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD2 = 3336; // 8
+static const uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD2_LEN = 3337; // 8
+static const uint64_t SH_FLD_BUSY_COUNTER_WINDOW_SELECT = 3338; // 8
+static const uint64_t SH_FLD_BUSY_COUNTER_WINDOW_SELECT_LEN = 3339; // 8
+static const uint64_t SH_FLD_BUSY_ENABLE = 3340; // 3
+static const uint64_t SH_FLD_BUSY_RESPONSE_CODE = 3341; // 1
+static const uint64_t SH_FLD_BUSY_RESPONSE_CODE_LEN = 3342; // 1
+static const uint64_t SH_FLD_BUSY_RESPONSE_CODE_NO_1 = 3343; // 1
+static const uint64_t SH_FLD_BUSY_RESPONSE_CODE_NO_1_LEN = 3344; // 1
+static const uint64_t SH_FLD_BUSY_STATUS = 3345; // 1
+static const uint64_t SH_FLD_BUSY_STATUS_LEN = 3346; // 1
+static const uint64_t SH_FLD_BUS_ADDR_NVLD_0 = 3347; // 1
+static const uint64_t SH_FLD_BUS_ADDR_NVLD_1 = 3348; // 1
+static const uint64_t SH_FLD_BUS_ADDR_NVLD_2 = 3349; // 1
+static const uint64_t SH_FLD_BUS_ADDR_NVLD_3 = 3350; // 1
+static const uint64_t SH_FLD_BUS_ADDR_P_ERR_0 = 3351; // 1
+static const uint64_t SH_FLD_BUS_ADDR_P_ERR_1 = 3352; // 1
+static const uint64_t SH_FLD_BUS_ADDR_P_ERR_2 = 3353; // 1
+static const uint64_t SH_FLD_BUS_ADDR_P_ERR_3 = 3354; // 1
+static const uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_0 = 3355; // 1
+static const uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_1 = 3356; // 1
+static const uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_2 = 3357; // 1
+static const uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_3 = 3358; // 1
+static const uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_0 = 3359; // 1
+static const uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_1 = 3360; // 1
+static const uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_2 = 3361; // 1
+static const uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_3 = 3362; // 1
+static const uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_0 = 3363; // 1
+static const uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_1 = 3364; // 1
+static const uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_2 = 3365; // 1
+static const uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_3 = 3366; // 1
+static const uint64_t SH_FLD_BUS_BUSY_0 = 3367; // 1
+static const uint64_t SH_FLD_BUS_BUSY_1 = 3368; // 1
+static const uint64_t SH_FLD_BUS_BUSY_2 = 3369; // 1
+static const uint64_t SH_FLD_BUS_BUSY_3 = 3370; // 1
+static const uint64_t SH_FLD_BUS_COMMAND_COMPLETE_0 = 3371; // 1
+static const uint64_t SH_FLD_BUS_COMMAND_COMPLETE_1 = 3372; // 1
+static const uint64_t SH_FLD_BUS_COMMAND_COMPLETE_2 = 3373; // 1
+static const uint64_t SH_FLD_BUS_COMMAND_COMPLETE_3 = 3374; // 1
+static const uint64_t SH_FLD_BUS_DATA_REQUEST_0 = 3375; // 1
+static const uint64_t SH_FLD_BUS_DATA_REQUEST_1 = 3376; // 1
+static const uint64_t SH_FLD_BUS_DATA_REQUEST_2 = 3377; // 1
+static const uint64_t SH_FLD_BUS_DATA_REQUEST_3 = 3378; // 1
+static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_0 = 3379; // 1
+static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_0_LEN = 3380; // 1
+static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_1 = 3381; // 1
+static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_1_LEN = 3382; // 1
+static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_2 = 3383; // 1
+static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_2_LEN = 3384; // 1
+static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_3 = 3385; // 1
+static const uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_3_LEN = 3386; // 1
+static const uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_0 = 3387; // 1
+static const uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_1 = 3388; // 1
+static const uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_2 = 3389; // 1
+static const uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_3 = 3390; // 1
+static const uint64_t SH_FLD_BUS_I2C_PORT_BUSY_0 = 3391; // 1
+static const uint64_t SH_FLD_BUS_I2C_PORT_BUSY_1 = 3392; // 1
+static const uint64_t SH_FLD_BUS_I2C_PORT_BUSY_2 = 3393; // 1
+static const uint64_t SH_FLD_BUS_I2C_PORT_BUSY_3 = 3394; // 1
+static const uint64_t SH_FLD_BUS_ID = 3395; // 12
+static const uint64_t SH_FLD_BUS_ID_LEN = 3396; // 12
+static const uint64_t SH_FLD_BUS_INVALID_COMMAND_0 = 3397; // 1
+static const uint64_t SH_FLD_BUS_INVALID_COMMAND_1 = 3398; // 1
+static const uint64_t SH_FLD_BUS_INVALID_COMMAND_2 = 3399; // 1
+static const uint64_t SH_FLD_BUS_INVALID_COMMAND_3 = 3400; // 1
+static const uint64_t SH_FLD_BUS_LB_PARITY_ERROR_0 = 3401; // 1
+static const uint64_t SH_FLD_BUS_LB_PARITY_ERROR_1 = 3402; // 1
+static const uint64_t SH_FLD_BUS_LB_PARITY_ERROR_2 = 3403; // 1
+static const uint64_t SH_FLD_BUS_LB_PARITY_ERROR_3 = 3404; // 1
+static const uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_0 = 3405; // 1
+static const uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_1 = 3406; // 1
+static const uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_2 = 3407; // 1
+static const uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_3 = 3408; // 1
+static const uint64_t SH_FLD_BUS_PARITY_ERROR_0 = 3409; // 1
+static const uint64_t SH_FLD_BUS_PARITY_ERROR_1 = 3410; // 1
+static const uint64_t SH_FLD_BUS_PARITY_ERROR_2 = 3411; // 1
+static const uint64_t SH_FLD_BUS_PARITY_ERROR_3 = 3412; // 1
+static const uint64_t SH_FLD_BUS_PAR_ERR_0 = 3413; // 1
+static const uint64_t SH_FLD_BUS_PAR_ERR_1 = 3414; // 1
+static const uint64_t SH_FLD_BUS_PAR_ERR_2 = 3415; // 1
+static const uint64_t SH_FLD_BUS_PAR_ERR_3 = 3416; // 1
+static const uint64_t SH_FLD_BUS_READ_NVLD_0 = 3417; // 1
+static const uint64_t SH_FLD_BUS_READ_NVLD_1 = 3418; // 1
+static const uint64_t SH_FLD_BUS_READ_NVLD_2 = 3419; // 1
+static const uint64_t SH_FLD_BUS_READ_NVLD_3 = 3420; // 1
+static const uint64_t SH_FLD_BUS_STOP_ERROR_0 = 3421; // 1
+static const uint64_t SH_FLD_BUS_STOP_ERROR_1 = 3422; // 1
+static const uint64_t SH_FLD_BUS_STOP_ERROR_2 = 3423; // 1
+static const uint64_t SH_FLD_BUS_STOP_ERROR_3 = 3424; // 1
+static const uint64_t SH_FLD_BUS_WIDTH = 3425; // 4
+static const uint64_t SH_FLD_BUS_WIDTH_LEN = 3426; // 4
+static const uint64_t SH_FLD_BUS_WRITE_NVLD_0 = 3427; // 1
+static const uint64_t SH_FLD_BUS_WRITE_NVLD_1 = 3428; // 1
+static const uint64_t SH_FLD_BUS_WRITE_NVLD_2 = 3429; // 1
+static const uint64_t SH_FLD_BUS_WRITE_NVLD_3 = 3430; // 1
+static const uint64_t SH_FLD_BW_SAMPLE_SIZE = 3431; // 5
+static const uint64_t SH_FLD_BW_WINDOW_SIZE = 3432; // 5
+static const uint64_t SH_FLD_BYPASSCLKOUT = 3433; // 3
+static const uint64_t SH_FLD_BYPASSING_RESET_SEQUENCE_PIB_I2CM = 3434; // 1
+static const uint64_t SH_FLD_BYPASSN = 3435; // 10
+static const uint64_t SH_FLD_BYTE0_SEL = 3436; // 8
+static const uint64_t SH_FLD_BYTE0_SEL_LEN = 3437; // 8
+static const uint64_t SH_FLD_BYTE1_SEL = 3438; // 8
+static const uint64_t SH_FLD_BYTE1_SEL_LEN = 3439; // 8
+static const uint64_t SH_FLD_BYTE2_SEL = 3440; // 8
+static const uint64_t SH_FLD_BYTE2_SEL_LEN = 3441; // 8
+static const uint64_t SH_FLD_BYTE3_SEL = 3442; // 8
+static const uint64_t SH_FLD_BYTE3_SEL_LEN = 3443; // 8
+static const uint64_t SH_FLD_B_BAD_DFE_CONV = 3444; // 48
+static const uint64_t SH_FLD_B_BANK_CONTROLS = 3445; // 48
+static const uint64_t SH_FLD_B_BANK_CONTROLS_LEN = 3446; // 48
+static const uint64_t SH_FLD_B_BIST_EN = 3447; // 2
+static const uint64_t SH_FLD_B_CONTROLS = 3448; // 48
+static const uint64_t SH_FLD_B_CONTROLS_LEN = 3449; // 48
+static const uint64_t SH_FLD_B_CTLE_COARSE = 3450; // 48
+static const uint64_t SH_FLD_B_CTLE_COARSE_LEN = 3451; // 48
+static const uint64_t SH_FLD_B_CTLE_GAIN = 3452; // 48
+static const uint64_t SH_FLD_B_CTLE_GAIN_LEN = 3453; // 48
+static const uint64_t SH_FLD_B_EVEN_INTEG_FINE_GAIN = 3454; // 48
+static const uint64_t SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN = 3455; // 48
+static const uint64_t SH_FLD_B_H1AP_AT_LIMIT = 3456; // 48
+static const uint64_t SH_FLD_B_H1E_VAL = 3457; // 48
+static const uint64_t SH_FLD_B_H1E_VAL_LEN = 3458; // 48
+static const uint64_t SH_FLD_B_H1O_VAL = 3459; // 48
+static const uint64_t SH_FLD_B_H1O_VAL_LEN = 3460; // 48
+static const uint64_t SH_FLD_B_INTEG_COARSE_GAIN = 3461; // 48
+static const uint64_t SH_FLD_B_INTEG_COARSE_GAIN_LEN = 3462; // 48
+static const uint64_t SH_FLD_B_ODD_INTEG_FINE_GAIN = 3463; // 48
+static const uint64_t SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN = 3464; // 48
+static const uint64_t SH_FLD_B_OFFSET_E0 = 3465; // 48
+static const uint64_t SH_FLD_B_OFFSET_E0_LEN = 3466; // 48
+static const uint64_t SH_FLD_B_OFFSET_E1 = 3467; // 48
+static const uint64_t SH_FLD_B_OFFSET_E1_LEN = 3468; // 48
+static const uint64_t SH_FLD_B_OFFSET_O0 = 3469; // 48
+static const uint64_t SH_FLD_B_OFFSET_O0_LEN = 3470; // 48
+static const uint64_t SH_FLD_B_OFFSET_O1 = 3471; // 48
+static const uint64_t SH_FLD_B_OFFSET_O1_LEN = 3472; // 48
+static const uint64_t SH_FLD_B_PATH_OFF_EVEN = 3473; // 48
+static const uint64_t SH_FLD_B_PATH_OFF_EVEN_LEN = 3474; // 48
+static const uint64_t SH_FLD_B_PATH_OFF_ODD = 3475; // 48
+static const uint64_t SH_FLD_B_PATH_OFF_ODD_LEN = 3476; // 48
+static const uint64_t SH_FLD_B_PR_DFE_CLKADJ = 3477; // 48
+static const uint64_t SH_FLD_B_PR_DFE_CLKADJ_LEN = 3478; // 48
+static const uint64_t SH_FLD_C0_DROPOUT_EVENT_COUNT = 3479; // 12
+static const uint64_t SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN = 3480; // 12
+static const uint64_t SH_FLD_C0_DROPOUT_INAROW_COUNT = 3481; // 12
+static const uint64_t SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN = 3482; // 12
+static const uint64_t SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE = 3483; // 12
+static const uint64_t SH_FLD_C1_COUNT_LT = 3484; // 86
+static const uint64_t SH_FLD_C1_COUNT_LT_LEN = 3485; // 86
+static const uint64_t SH_FLD_C1_DROPOUT_EVENT_COUNT = 3486; // 12
+static const uint64_t SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN = 3487; // 12
+static const uint64_t SH_FLD_C1_DROPOUT_INAROW_COUNT = 3488; // 12
+static const uint64_t SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN = 3489; // 12
+static const uint64_t SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE = 3490; // 12
+static const uint64_t SH_FLD_C1_INAROW_MODE = 3491; // 86
+static const uint64_t SH_FLD_C2_COUNT_LT = 3492; // 86
+static const uint64_t SH_FLD_C2_COUNT_LT_LEN = 3493; // 86
+static const uint64_t SH_FLD_C2_INAROW_MODE = 3494; // 86
+static const uint64_t SH_FLD_C405DCU_M_TIMEOUT = 3495; // 1
+static const uint64_t SH_FLD_C405DCU_M_TIMEOUT_MASK = 3496; // 1
+static const uint64_t SH_FLD_C405ICU_M_TIMEOUT = 3497; // 1
+static const uint64_t SH_FLD_C405ICU_M_TIMEOUT_MASK = 3498; // 1
+static const uint64_t SH_FLD_C405_DCU_ECC_CE = 3499; // 1
+static const uint64_t SH_FLD_C405_DCU_ECC_UE = 3500; // 1
+static const uint64_t SH_FLD_C405_ECC_CE = 3501; // 1
+static const uint64_t SH_FLD_C405_ECC_CE_MASK = 3502; // 1
+static const uint64_t SH_FLD_C405_ECC_UE = 3503; // 1
+static const uint64_t SH_FLD_C405_ECC_UE_MASK = 3504; // 1
+static const uint64_t SH_FLD_C405_ICU_ECC_CE = 3505; // 1
+static const uint64_t SH_FLD_C405_ICU_ECC_UE = 3506; // 1
+static const uint64_t SH_FLD_C405_OCI_MACHINECHECK = 3507; // 1
+static const uint64_t SH_FLD_C405_OCI_MACHINECHECK_MASK = 3508; // 1
+static const uint64_t SH_FLD_CACHE_CTRL_ARY_SELECT = 3509; // 4
+static const uint64_t SH_FLD_CACHE_CTRL_ARY_SELECT_LEN = 3510; // 4
+static const uint64_t SH_FLD_CACHE_DROPOUT_ENABLE = 3511; // 12
+static const uint64_t SH_FLD_CACHE_DROPOUT_EVENT_COUNT = 3512; // 12
+static const uint64_t SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN = 3513; // 12
+static const uint64_t SH_FLD_CACHE_DROPOUT_INAROW_COUNT = 3514; // 12
+static const uint64_t SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN = 3515; // 12
+static const uint64_t SH_FLD_CACHE_INHIBITED_HIT_CACHEABLE_ERROR = 3516; // 12
+static const uint64_t SH_FLD_CACHE_RD_CE = 3517; // 12
+static const uint64_t SH_FLD_CACHE_RD_CE_AND_UE = 3518; // 12
+static const uint64_t SH_FLD_CACHE_RD_SUE = 3519; // 12
+static const uint64_t SH_FLD_CACHE_RD_UE = 3520; // 12
+static const uint64_t SH_FLD_CACHE_UE_SUE_DETECTED_ON_MODIFIED_LINE_BY_CO = 3521; // 12
+static const uint64_t SH_FLD_CACHE_UE_SUE_DETECTED_ON_NON_MODIFIED_LINE_BY_CO = 3522; // 12
+static const uint64_t SH_FLD_CAC_ALLOC_DIS = 3523; // 2
+static const uint64_t SH_FLD_CAC_PERR_CHK_DIS = 3524; // 2
+static const uint64_t SH_FLD_CAL0_PE = 3525; // 8
+static const uint64_t SH_FLD_CAL1_PE = 3526; // 8
+static const uint64_t SH_FLD_CAL2_PE = 3527; // 8
+static const uint64_t SH_FLD_CAL3_PE = 3528; // 8
+static const uint64_t SH_FLD_CALIBRATION_ENABLE = 3529; // 8
+static const uint64_t SH_FLD_CALRECAL = 3530; // 10
+static const uint64_t SH_FLD_CALREQ = 3531; // 10
+static const uint64_t SH_FLD_CAL_LANE_GCRMSG = 3532; // 4
+static const uint64_t SH_FLD_CAL_LANE_GCRMSG_LEN = 3533; // 4
+static const uint64_t SH_FLD_CAL_LANE_PHY_GCRMSG = 3534; // 6
+static const uint64_t SH_FLD_CAL_LANE_PHY_GCRMSG_LEN = 3535; // 6
+static const uint64_t SH_FLD_CAL_LANE_SEL = 3536; // 188
+static const uint64_t SH_FLD_CAL_LANE_VAL_GCRMSG = 3537; // 4
+static const uint64_t SH_FLD_CAL_SM_1HOT = 3538; // 8
+static const uint64_t SH_FLD_CAM256_MAX_CNT = 3539; // 6
+static const uint64_t SH_FLD_CAM256_MAX_CNT_LEN = 3540; // 6
+static const uint64_t SH_FLD_CAM_DISPLAY_REG_0 = 3541; // 1
+static const uint64_t SH_FLD_CAM_DISPLAY_REG_0_LEN = 3542; // 1
+static const uint64_t SH_FLD_CAM_DISPLAY_REG_1 = 3543; // 1
+static const uint64_t SH_FLD_CAM_DISPLAY_REG_1_LEN = 3544; // 1
+static const uint64_t SH_FLD_CAPP_ERR_STAT_CTL_REG_PARITY_ERRHOLD = 3545; // 2
+static const uint64_t SH_FLD_CAPSEL = 3546; // 4
+static const uint64_t SH_FLD_CASCADE = 3547; // 19
+static const uint64_t SH_FLD_CASCADE_LEN = 3548; // 19
+static const uint64_t SH_FLD_CC = 3549; // 10
+static const uint64_t SH_FLD_CCALBANDSEL = 3550; // 10
+static const uint64_t SH_FLD_CCALBANDSEL_LEN = 3551; // 10
+static const uint64_t SH_FLD_CCALCOMP = 3552; // 10
+static const uint64_t SH_FLD_CCALCVHOLD = 3553; // 10
+static const uint64_t SH_FLD_CCALERR = 3554; // 10
+static const uint64_t SH_FLD_CCALFMAX = 3555; // 10
+static const uint64_t SH_FLD_CCALFMIN = 3556; // 10
+static const uint64_t SH_FLD_CCALLOAD = 3557; // 10
+static const uint64_t SH_FLD_CCALMETH = 3558; // 10
+static const uint64_t SH_FLD_CCFG_GPTR = 3559; // 43
+static const uint64_t SH_FLD_CCS_ARRAY_CE_ERR_INJ = 3560; // 2
+static const uint64_t SH_FLD_CCS_ARRAY_CE_ERR_INJ_MODE = 3561; // 2
+static const uint64_t SH_FLD_CCS_ARRAY_UE_ERR_INJ = 3562; // 2
+static const uint64_t SH_FLD_CCS_ARRAY_UE_ERR_INJ_MODE = 3563; // 2
+static const uint64_t SH_FLD_CCS_CNTLQ_PE_HOLD_OUT = 3564; // 2
+static const uint64_t SH_FLD_CCS_FSM_INJ_MODE = 3565; // 2
+static const uint64_t SH_FLD_CCS_FSM_INJ_REG = 3566; // 2
+static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE0 = 3567; // 2
+static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE0_LEN = 3568; // 2
+static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE1 = 3569; // 2
+static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE1_LEN = 3570; // 2
+static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE2 = 3571; // 2
+static const uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE2_LEN = 3572; // 2
+static const uint64_t SH_FLD_CC_ACTIVITY_0 = 3573; // 1
+static const uint64_t SH_FLD_CC_ACTIVITY_0_LEN = 3574; // 1
+static const uint64_t SH_FLD_CC_ACTIVITY_1 = 3575; // 1
+static const uint64_t SH_FLD_CC_ACTIVITY_1_LEN = 3576; // 1
+static const uint64_t SH_FLD_CC_ACTIVITY_2 = 3577; // 1
+static const uint64_t SH_FLD_CC_ACTIVITY_2_LEN = 3578; // 1
+static const uint64_t SH_FLD_CC_ACTIVITY_3 = 3579; // 1
+static const uint64_t SH_FLD_CC_ACTIVITY_3_LEN = 3580; // 1
+static const uint64_t SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC = 3581; // 43
+static const uint64_t SH_FLD_CC_CTRL_OPCG_DONE_DC = 3582; // 43
+static const uint64_t SH_FLD_CC_ENABLE_0 = 3583; // 1
+static const uint64_t SH_FLD_CC_ENABLE_1 = 3584; // 1
+static const uint64_t SH_FLD_CC_ENABLE_2 = 3585; // 1
+static const uint64_t SH_FLD_CC_ENABLE_3 = 3586; // 1
+static const uint64_t SH_FLD_CC_ID_0 = 3587; // 1
+static const uint64_t SH_FLD_CC_ID_0_LEN = 3588; // 1
+static const uint64_t SH_FLD_CC_ID_1 = 3589; // 1
+static const uint64_t SH_FLD_CC_ID_1_LEN = 3590; // 1
+static const uint64_t SH_FLD_CC_ID_2 = 3591; // 1
+static const uint64_t SH_FLD_CC_ID_2_LEN = 3592; // 1
+static const uint64_t SH_FLD_CC_ID_3 = 3593; // 1
+static const uint64_t SH_FLD_CC_ID_3_LEN = 3594; // 1
+static const uint64_t SH_FLD_CC_MASK = 3595; // 8
+static const uint64_t SH_FLD_CC_READ_ENABLE_0 = 3596; // 1
+static const uint64_t SH_FLD_CC_READ_ENABLE_1 = 3597; // 1
+static const uint64_t SH_FLD_CC_READ_ENABLE_2 = 3598; // 1
+static const uint64_t SH_FLD_CC_READ_ENABLE_3 = 3599; // 1
+static const uint64_t SH_FLD_CC_WRITE_ENABLE_0 = 3600; // 1
+static const uint64_t SH_FLD_CC_WRITE_ENABLE_1 = 3601; // 1
+static const uint64_t SH_FLD_CC_WRITE_ENABLE_2 = 3602; // 1
+static const uint64_t SH_FLD_CC_WRITE_ENABLE_3 = 3603; // 1
+static const uint64_t SH_FLD_CD_ALL_DONE_GCRMSG = 3604; // 4
+static const uint64_t SH_FLD_CD_PREV_DONE_GCRMSG = 3605; // 4
+static const uint64_t SH_FLD_CE = 3606; // 53
+static const uint64_t SH_FLD_CE1_0_OUT = 3607; // 4
+static const uint64_t SH_FLD_CE1_1_OUT = 3608; // 4
+static const uint64_t SH_FLD_CE1_2_OUT = 3609; // 4
+static const uint64_t SH_FLD_CE1_3_OUT = 3610; // 4
+static const uint64_t SH_FLD_CE1_4_OUT = 3611; // 4
+static const uint64_t SH_FLD_CE1_5_OUT = 3612; // 4
+static const uint64_t SH_FLD_CE1_6_OUT = 3613; // 4
+static const uint64_t SH_FLD_CE1_7_OUT = 3614; // 4
+static const uint64_t SH_FLD_CE2_0_OUT = 3615; // 4
+static const uint64_t SH_FLD_CE2_1_OUT = 3616; // 4
+static const uint64_t SH_FLD_CE2_2_OUT = 3617; // 4
+static const uint64_t SH_FLD_CE2_3_OUT = 3618; // 4
+static const uint64_t SH_FLD_CE2_4_OUT = 3619; // 4
+static const uint64_t SH_FLD_CE2_5_OUT = 3620; // 4
+static const uint64_t SH_FLD_CE2_6_OUT = 3621; // 4
+static const uint64_t SH_FLD_CE2_7_OUT = 3622; // 4
+static const uint64_t SH_FLD_CEC_PSI_INTERRUPT = 3623; // 1
+static const uint64_t SH_FLD_CENTAURP_ENABLE_BYPASS_CMD = 3624; // 4
+static const uint64_t SH_FLD_CENTAURP_ENABLE_CENTAURP_CMD = 3625; // 4
+static const uint64_t SH_FLD_CENTAURP_ENABLE_CP_ME = 3626; // 4
+static const uint64_t SH_FLD_CENTAURP_ENABLE_CR_SIDEBAND = 3627; // 4
+static const uint64_t SH_FLD_CENTAURP_ENABLE_DTAG_CR = 3628; // 4
+static const uint64_t SH_FLD_CENTAURP_ENABLE_DYNAMIC_WRBUF_ALLOC = 3629; // 4
+static const uint64_t SH_FLD_CENTAURP_ENABLE_ECRESP = 3630; // 4
+static const uint64_t SH_FLD_CENTAURP_ENABLE_NEW_AMO = 3631; // 4
+static const uint64_t SH_FLD_CENTAURP_INBAND_IS_63 = 3632; // 4
+static const uint64_t SH_FLD_CENTAUR_MODE = 3633; // 4
+static const uint64_t SH_FLD_CENTAUR_SYNC_COMMAND_DETECTED = 3634; // 4
+static const uint64_t SH_FLD_CERR_AXFLOW_ERR = 3635; // 1
+static const uint64_t SH_FLD_CERR_AXFLOW_ERR_LEN = 3636; // 1
+static const uint64_t SH_FLD_CERR_AXPUSH_WRERR = 3637; // 1
+static const uint64_t SH_FLD_CERR_AXPUSH_WRERR_LEN = 3638; // 1
+static const uint64_t SH_FLD_CERR_BAR_PARITY_ERR = 3639; // 1
+static const uint64_t SH_FLD_CERR_BCDE_INTERNAL_ERR = 3640; // 1
+static const uint64_t SH_FLD_CERR_BCDE_INTERNAL_ERR_LEN = 3641; // 1
+static const uint64_t SH_FLD_CERR_BCDE_SETUP_ERR = 3642; // 1
+static const uint64_t SH_FLD_CERR_BCDE_SETUP_ERR_LEN = 3643; // 1
+static const uint64_t SH_FLD_CERR_BCUE_INTERNAL_ERR = 3644; // 1
+static const uint64_t SH_FLD_CERR_BCUE_INTERNAL_ERR_LEN = 3645; // 1
+static const uint64_t SH_FLD_CERR_BCUE_OCI_DATAERR = 3646; // 1
+static const uint64_t SH_FLD_CERR_BCUE_OCI_DATAERR_LEN = 3647; // 1
+static const uint64_t SH_FLD_CERR_BCUE_SETUP_ERR = 3648; // 1
+static const uint64_t SH_FLD_CERR_BCUE_SETUP_ERR_LEN = 3649; // 1
+static const uint64_t SH_FLD_CERR_PBDOUT_PARITY_ERR = 3650; // 1
+static const uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_RD = 3651; // 1
+static const uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_RD_LEN = 3652; // 1
+static const uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_WR = 3653; // 1
+static const uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_WR_LEN = 3654; // 1
+static const uint64_t SH_FLD_CERR_PB_BADCRESP = 3655; // 1
+static const uint64_t SH_FLD_CERR_PB_BADCRESP_LEN = 3656; // 1
+static const uint64_t SH_FLD_CERR_PB_OPERTO = 3657; // 1
+static const uint64_t SH_FLD_CERR_PB_OPERTO_LEN = 3658; // 1
+static const uint64_t SH_FLD_CERR_PB_PARITY_ERR = 3659; // 1
+static const uint64_t SH_FLD_CERR_PB_PARITY_ERR_LEN = 3660; // 1
+static const uint64_t SH_FLD_CERR_PB_RDADRERR_FW = 3661; // 1
+static const uint64_t SH_FLD_CERR_PB_RDADRERR_FW_LEN = 3662; // 1
+static const uint64_t SH_FLD_CERR_PB_RDDATATO_FW = 3663; // 1
+static const uint64_t SH_FLD_CERR_PB_RDDATATO_FW_LEN = 3664; // 1
+static const uint64_t SH_FLD_CERR_PB_UNEXPCRESP = 3665; // 1
+static const uint64_t SH_FLD_CERR_PB_UNEXPCRESP_LEN = 3666; // 1
+static const uint64_t SH_FLD_CERR_PB_UNEXPDATA = 3667; // 1
+static const uint64_t SH_FLD_CERR_PB_UNEXPDATA_LEN = 3668; // 1
+static const uint64_t SH_FLD_CERR_PB_WRADRERR_FW = 3669; // 1
+static const uint64_t SH_FLD_CERR_PB_WRADRERR_FW_LEN = 3670; // 1
+static const uint64_t SH_FLD_CERR_SCOMTB_ERR = 3671; // 1
+static const uint64_t SH_FLD_CERR_SLV_INTERNAL_ERR = 3672; // 1
+static const uint64_t SH_FLD_CERR_SLV_INTERNAL_ERR_LEN = 3673; // 1
+static const uint64_t SH_FLD_CERR_SPARE = 3674; // 1
+static const uint64_t SH_FLD_CERR_SPARE_LEN = 3675; // 1
+static const uint64_t SH_FLD_CE_LEN = 3676; // 10
+static const uint64_t SH_FLD_CFG = 3677; // 46
+static const uint64_t SH_FLD_CFG_0_1_OP = 3678; // 2
+static const uint64_t SH_FLD_CFG_0_1_OP_LEN = 3679; // 2
+static const uint64_t SH_FLD_CFG_10_11_OP = 3680; // 2
+static const uint64_t SH_FLD_CFG_10_11_OP_LEN = 3681; // 2
+static const uint64_t SH_FLD_CFG_12_13_OP = 3682; // 2
+static const uint64_t SH_FLD_CFG_12_13_OP_LEN = 3683; // 2
+static const uint64_t SH_FLD_CFG_14_15_OP = 3684; // 2
+static const uint64_t SH_FLD_CFG_14_15_OP_LEN = 3685; // 2
+static const uint64_t SH_FLD_CFG_16_17_OP = 3686; // 2
+static const uint64_t SH_FLD_CFG_16_17_OP_LEN = 3687; // 2
+static const uint64_t SH_FLD_CFG_18_19_OP = 3688; // 2
+static const uint64_t SH_FLD_CFG_18_19_OP_LEN = 3689; // 2
+static const uint64_t SH_FLD_CFG_20_21_OP = 3690; // 2
+static const uint64_t SH_FLD_CFG_20_21_OP_LEN = 3691; // 2
+static const uint64_t SH_FLD_CFG_22_23_OP = 3692; // 2
+static const uint64_t SH_FLD_CFG_22_23_OP_LEN = 3693; // 2
+static const uint64_t SH_FLD_CFG_24_25_OP = 3694; // 2
+static const uint64_t SH_FLD_CFG_24_25_OP_LEN = 3695; // 2
+static const uint64_t SH_FLD_CFG_26_27_OP = 3696; // 2
+static const uint64_t SH_FLD_CFG_26_27_OP_LEN = 3697; // 2
+static const uint64_t SH_FLD_CFG_28_29_OP = 3698; // 2
+static const uint64_t SH_FLD_CFG_28_29_OP_LEN = 3699; // 2
+static const uint64_t SH_FLD_CFG_2N_ADDR = 3700; // 8
+static const uint64_t SH_FLD_CFG_2_3_OP = 3701; // 2
+static const uint64_t SH_FLD_CFG_2_3_OP_LEN = 3702; // 2
+static const uint64_t SH_FLD_CFG_30_31_OP = 3703; // 2
+static const uint64_t SH_FLD_CFG_30_31_OP_LEN = 3704; // 2
+static const uint64_t SH_FLD_CFG_4_5_OP = 3705; // 2
+static const uint64_t SH_FLD_CFG_4_5_OP_LEN = 3706; // 2
+static const uint64_t SH_FLD_CFG_6_7_OP = 3707; // 2
+static const uint64_t SH_FLD_CFG_6_7_OP_LEN = 3708; // 2
+static const uint64_t SH_FLD_CFG_8_9_OP = 3709; // 2
+static const uint64_t SH_FLD_CFG_8_9_OP_LEN = 3710; // 2
+static const uint64_t SH_FLD_CFG_ACM_EN = 3711; // 1
+static const uint64_t SH_FLD_CFG_ACT_SAME_RANK_HOLD_TIME = 3712; // 8
+static const uint64_t SH_FLD_CFG_ACT_SAME_RANK_HOLD_TIME_LEN = 3713; // 8
+static const uint64_t SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY = 3714; // 8
+static const uint64_t SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY_LEN = 3715; // 8
+static const uint64_t SH_FLD_CFG_ADDRESS_COUNTER = 3716; // 2
+static const uint64_t SH_FLD_CFG_ADDRESS_COUNTER_LEN = 3717; // 2
+static const uint64_t SH_FLD_CFG_ADDR_BAR = 3718; // 6
+static const uint64_t SH_FLD_CFG_ADDR_COUNTER_MODE = 3719; // 2
+static const uint64_t SH_FLD_CFG_ADDR_COUNTER_MODE_LEN = 3720; // 2
+static const uint64_t SH_FLD_CFG_ALL_PERIODIC_LENGTH = 3721; // 8
+static const uint64_t SH_FLD_CFG_ALL_PERIODIC_LENGTH_LEN = 3722; // 8
+static const uint64_t SH_FLD_CFG_ALL_PERIODIC_TB = 3723; // 8
+static const uint64_t SH_FLD_CFG_ALL_PERIODIC_TB_LEN = 3724; // 8
+static const uint64_t SH_FLD_CFG_ALWAYS_WAIT_ACT_TIME = 3725; // 8
+static const uint64_t SH_FLD_CFG_AMAP_BANK0 = 3726; // 2
+static const uint64_t SH_FLD_CFG_AMAP_BANK0_LEN = 3727; // 2
+static const uint64_t SH_FLD_CFG_AMAP_BANK1 = 3728; // 2
+static const uint64_t SH_FLD_CFG_AMAP_BANK1_LEN = 3729; // 2
+static const uint64_t SH_FLD_CFG_AMAP_BANK2 = 3730; // 2
+static const uint64_t SH_FLD_CFG_AMAP_BANK2_LEN = 3731; // 2
+static const uint64_t SH_FLD_CFG_AMAP_BANK_GROUP0 = 3732; // 2
+static const uint64_t SH_FLD_CFG_AMAP_BANK_GROUP0_LEN = 3733; // 2
+static const uint64_t SH_FLD_CFG_AMAP_BANK_GROUP1 = 3734; // 2
+static const uint64_t SH_FLD_CFG_AMAP_BANK_GROUP1_LEN = 3735; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL2 = 3736; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL2_LEN = 3737; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL3 = 3738; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL3_LEN = 3739; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL4 = 3740; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL4_LEN = 3741; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL5 = 3742; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL5_LEN = 3743; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL6 = 3744; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL6_LEN = 3745; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL7 = 3746; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL7_LEN = 3747; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL8 = 3748; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL8_LEN = 3749; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL9 = 3750; // 2
+static const uint64_t SH_FLD_CFG_AMAP_COL9_LEN = 3751; // 2
+static const uint64_t SH_FLD_CFG_AMAP_DIMM_SELECT = 3752; // 2
+static const uint64_t SH_FLD_CFG_AMAP_DIMM_SELECT_LEN = 3753; // 2
+static const uint64_t SH_FLD_CFG_AMAP_MRANK0 = 3754; // 2
+static const uint64_t SH_FLD_CFG_AMAP_MRANK0_LEN = 3755; // 2
+static const uint64_t SH_FLD_CFG_AMAP_MRANK1 = 3756; // 2
+static const uint64_t SH_FLD_CFG_AMAP_MRANK1_LEN = 3757; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW0 = 3758; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW0_LEN = 3759; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW1 = 3760; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW10 = 3761; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW10_LEN = 3762; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW11 = 3763; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW11_LEN = 3764; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW12 = 3765; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW12_LEN = 3766; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW13 = 3767; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW13_LEN = 3768; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW14 = 3769; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW14_LEN = 3770; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW15 = 3771; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW15_LEN = 3772; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW16 = 3773; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW16_LEN = 3774; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW17 = 3775; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW17_LEN = 3776; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW1_LEN = 3777; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW2 = 3778; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW2_LEN = 3779; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW3 = 3780; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW3_LEN = 3781; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW4 = 3782; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW4_LEN = 3783; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW5 = 3784; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW5_LEN = 3785; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW6 = 3786; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW6_LEN = 3787; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW7 = 3788; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW7_LEN = 3789; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW8 = 3790; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW8_LEN = 3791; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW9 = 3792; // 2
+static const uint64_t SH_FLD_CFG_AMAP_ROW9_LEN = 3793; // 2
+static const uint64_t SH_FLD_CFG_AMAP_SRANK0 = 3794; // 2
+static const uint64_t SH_FLD_CFG_AMAP_SRANK0_LEN = 3795; // 2
+static const uint64_t SH_FLD_CFG_AMAP_SRANK1 = 3796; // 2
+static const uint64_t SH_FLD_CFG_AMAP_SRANK1_LEN = 3797; // 2
+static const uint64_t SH_FLD_CFG_AMAP_SRANK2 = 3798; // 2
+static const uint64_t SH_FLD_CFG_AMAP_SRANK2_LEN = 3799; // 2
+static const uint64_t SH_FLD_CFG_APM_DD1_MODE = 3800; // 1
+static const uint64_t SH_FLD_CFG_APM_ENABLE = 3801; // 1
+static const uint64_t SH_FLD_CFG_APM_LM_HI_COMP = 3802; // 2
+static const uint64_t SH_FLD_CFG_APM_LM_HI_COMP_LEN = 3803; // 1
+static const uint64_t SH_FLD_CFG_APM_LM_LO_COMP = 3804; // 2
+static const uint64_t SH_FLD_CFG_APM_LM_LO_COMP_LEN = 3805; // 1
+static const uint64_t SH_FLD_CFG_APM_NM_HI_COMP = 3806; // 2
+static const uint64_t SH_FLD_CFG_APM_NM_HI_COMP_LEN = 3807; // 1
+static const uint64_t SH_FLD_CFG_APM_NM_LO_COMP = 3808; // 2
+static const uint64_t SH_FLD_CFG_APM_NM_LO_COMP_LEN = 3809; // 1
+static const uint64_t SH_FLD_CFG_APM_SAMPLE_SEL = 3810; // 1
+static const uint64_t SH_FLD_CFG_APM_SAMPLE_SEL_LEN = 3811; // 1
+static const uint64_t SH_FLD_CFG_APM_SEL = 3812; // 1
+static const uint64_t SH_FLD_CFG_APM_SEL_LEN = 3813; // 1
+static const uint64_t SH_FLD_CFG_A_AGGREGATE = 3814; // 6
+static const uint64_t SH_FLD_CFG_A_CMD_RATE = 3815; // 6
+static const uint64_t SH_FLD_CFG_A_CMD_RATE_LEN = 3816; // 6
+static const uint64_t SH_FLD_CFG_A_GATHER_ENABLE = 3817; // 6
+static const uint64_t SH_FLD_CFG_BANK_BUSY_FSM_DIS = 3818; // 8
+static const uint64_t SH_FLD_CFG_BANK_BUSY_FSM_DIS_LEN = 3819; // 8
+static const uint64_t SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS = 3820; // 8
+static const uint64_t SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN = 3821; // 8
+static const uint64_t SH_FLD_CFG_BC4_EN = 3822; // 2
+static const uint64_t SH_FLD_CFG_BLOCK_EN = 3823; // 1
+static const uint64_t SH_FLD_CFG_BLOCK_GROUP_EN = 3824; // 1
+static const uint64_t SH_FLD_CFG_BLOCK_RCMD_FILTER_EN = 3825; // 1
+static const uint64_t SH_FLD_CFG_BLOCK_RESET_DELAY = 3826; // 1
+static const uint64_t SH_FLD_CFG_BLOCK_RESET_DELAY_LEN = 3827; // 1
+static const uint64_t SH_FLD_CFG_BLOCK_VPD_EN = 3828; // 1
+static const uint64_t SH_FLD_CFG_BW_SNAPSHOT = 3829; // 8
+static const uint64_t SH_FLD_CFG_BW_SNAPSHOT_LEN = 3830; // 8
+static const uint64_t SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL = 3831; // 12
+static const uint64_t SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL_LEN = 3832; // 12
+static const uint64_t SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL = 3833; // 12
+static const uint64_t SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL_LEN = 3834; // 12
+static const uint64_t SH_FLD_CFG_CAC_ERR_REPAIR_EN = 3835; // 12
+static const uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR0_ENABLE = 3836; // 8
+static const uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR1_ENABLE = 3837; // 8
+static const uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR2_ENABLE = 3838; // 8
+static const uint64_t SH_FLD_CFG_CAL_RANK_ENABLE = 3839; // 8
+static const uint64_t SH_FLD_CFG_CAL_RANK_ENABLE_LEN = 3840; // 8
+static const uint64_t SH_FLD_CFG_CAL_SINGLE_PORT_MODE = 3841; // 8
+static const uint64_t SH_FLD_CFG_CAL_SINGLE_PORT_MODE_LEN = 3842; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_DDR_DONE = 3843; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_ENABLE = 3844; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_TYPE = 3845; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_TYPE_LEN = 3846; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_DDR_DONE = 3847; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_ENABLE = 3848; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_TYPE = 3849; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_TYPE_LEN = 3850; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_DDR_DONE = 3851; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_ENABLE = 3852; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_TYPE = 3853; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_TYPE_LEN = 3854; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_ENABLE = 3855; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR = 3856; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_LEN = 3857; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB = 3858; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB_LEN = 3859; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_SINGLE_RANK = 3860; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_Z_SYNC = 3861; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR0_Z_SYNC_LEN = 3862; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_DDR_DONE = 3863; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_ENABLE = 3864; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_TYPE = 3865; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_TYPE_LEN = 3866; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_DDR_DONE = 3867; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_ENABLE = 3868; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_TYPE = 3869; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_TYPE_LEN = 3870; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_DDR_DONE = 3871; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_ENABLE = 3872; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_TYPE = 3873; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_TYPE_LEN = 3874; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR1_SINGLE_RANK = 3875; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR1_Z_SYNC = 3876; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR1_Z_SYNC_LEN = 3877; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_DDR_DONE = 3878; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_ENABLE = 3879; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_TYPE = 3880; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_TYPE_LEN = 3881; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_DDR_DONE = 3882; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_ENABLE = 3883; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_TYPE = 3884; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_TYPE_LEN = 3885; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_DDR_DONE = 3886; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_ENABLE = 3887; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_TYPE = 3888; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_TYPE_LEN = 3889; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_SINGLE_RANK = 3890; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_WAT_EVENT_ENABLE = 3891; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_Z_SYNC = 3892; // 8
+static const uint64_t SH_FLD_CFG_CAL_TMR2_Z_SYNC_LEN = 3893; // 8
+static const uint64_t SH_FLD_CFG_CAPI = 3894; // 6
+static const uint64_t SH_FLD_CFG_CASCADE_PMU0 = 3895; // 2
+static const uint64_t SH_FLD_CFG_CASCADE_PMU0_LEN = 3896; // 2
+static const uint64_t SH_FLD_CFG_CASCADE_PMU1 = 3897; // 2
+static const uint64_t SH_FLD_CFG_CASCADE_PMU1_LEN = 3898; // 2
+static const uint64_t SH_FLD_CFG_CASCADE_PMU2 = 3899; // 2
+static const uint64_t SH_FLD_CFG_CASCADE_PMU2_LEN = 3900; // 2
+static const uint64_t SH_FLD_CFG_CASCADE_PMU3 = 3901; // 2
+static const uint64_t SH_FLD_CFG_CASCADE_PMU3_LEN = 3902; // 2
+static const uint64_t SH_FLD_CFG_CCS_ADDR_MUX_SEL = 3903; // 8
+static const uint64_t SH_FLD_CFG_CCS_INST_RESET_ENABLE = 3904; // 8
+static const uint64_t SH_FLD_CFG_CCS_RETRY_DIS = 3905; // 2
+static const uint64_t SH_FLD_CFG_CHG_RATE_GP_MASTER = 3906; // 6
+static const uint64_t SH_FLD_CFG_CHG_RATE_SP_MASTER = 3907; // 6
+static const uint64_t SH_FLD_CFG_CHIPID = 3908; // 1
+static const uint64_t SH_FLD_CFG_CHIPID_LEN = 3909; // 1
+static const uint64_t SH_FLD_CFG_CHIPID_OVERRIDE = 3910; // 1
+static const uint64_t SH_FLD_CFG_CHIP_IS_SYSTEM = 3911; // 3
+static const uint64_t SH_FLD_CFG_CKE_PUP_STATE = 3912; // 8
+static const uint64_t SH_FLD_CFG_CKE_PUP_STATE_LEN = 3913; // 8
+static const uint64_t SH_FLD_CFG_CLOCK_MONITOR_EN = 3914; // 2
+static const uint64_t SH_FLD_CFG_CMD0_BANK = 3915; // 8
+static const uint64_t SH_FLD_CFG_CMD0_BANK_LEN = 3916; // 8
+static const uint64_t SH_FLD_CFG_CMD0_BANK_MATCH_EN = 3917; // 8
+static const uint64_t SH_FLD_CFG_CMD0_BG = 3918; // 8
+static const uint64_t SH_FLD_CFG_CMD0_BG_LEN = 3919; // 8
+static const uint64_t SH_FLD_CFG_CMD0_BG_MATCH_EN = 3920; // 8
+static const uint64_t SH_FLD_CFG_CMD0_MRANK = 3921; // 8
+static const uint64_t SH_FLD_CFG_CMD0_MRANK_LEN = 3922; // 8
+static const uint64_t SH_FLD_CFG_CMD0_MRANK_MATCH_EN = 3923; // 8
+static const uint64_t SH_FLD_CFG_CMD0_SRANK = 3924; // 8
+static const uint64_t SH_FLD_CFG_CMD0_SRANK_LEN = 3925; // 8
+static const uint64_t SH_FLD_CFG_CMD0_SRANK_MATCH_EN = 3926; // 8
+static const uint64_t SH_FLD_CFG_CMD0_TYPE = 3927; // 8
+static const uint64_t SH_FLD_CFG_CMD0_TYPE_LEN = 3928; // 8
+static const uint64_t SH_FLD_CFG_CMD1_BANK = 3929; // 8
+static const uint64_t SH_FLD_CFG_CMD1_BANK_LEN = 3930; // 8
+static const uint64_t SH_FLD_CFG_CMD1_BANK_MATCH_EN = 3931; // 8
+static const uint64_t SH_FLD_CFG_CMD1_BG = 3932; // 8
+static const uint64_t SH_FLD_CFG_CMD1_BG_LEN = 3933; // 8
+static const uint64_t SH_FLD_CFG_CMD1_BG_MATCH_EN = 3934; // 8
+static const uint64_t SH_FLD_CFG_CMD1_MRANK = 3935; // 8
+static const uint64_t SH_FLD_CFG_CMD1_MRANK_LEN = 3936; // 8
+static const uint64_t SH_FLD_CFG_CMD1_MRANK_MATCH_EN = 3937; // 8
+static const uint64_t SH_FLD_CFG_CMD1_SRANK = 3938; // 8
+static const uint64_t SH_FLD_CFG_CMD1_SRANK_LEN = 3939; // 8
+static const uint64_t SH_FLD_CFG_CMD1_SRANK_MATCH_EN = 3940; // 8
+static const uint64_t SH_FLD_CFG_CMD1_TYPE = 3941; // 8
+static const uint64_t SH_FLD_CFG_CMD1_TYPE_LEN = 3942; // 8
+static const uint64_t SH_FLD_CFG_CMD2_BANK = 3943; // 8
+static const uint64_t SH_FLD_CFG_CMD2_BANK_LEN = 3944; // 8
+static const uint64_t SH_FLD_CFG_CMD2_BANK_MATCH_EN = 3945; // 8
+static const uint64_t SH_FLD_CFG_CMD2_BG = 3946; // 8
+static const uint64_t SH_FLD_CFG_CMD2_BG_LEN = 3947; // 8
+static const uint64_t SH_FLD_CFG_CMD2_BG_MATCH_EN = 3948; // 8
+static const uint64_t SH_FLD_CFG_CMD2_MRANK = 3949; // 8
+static const uint64_t SH_FLD_CFG_CMD2_MRANK_LEN = 3950; // 8
+static const uint64_t SH_FLD_CFG_CMD2_MRANK_MATCH_EN = 3951; // 8
+static const uint64_t SH_FLD_CFG_CMD2_SRANK = 3952; // 8
+static const uint64_t SH_FLD_CFG_CMD2_SRANK_LEN = 3953; // 8
+static const uint64_t SH_FLD_CFG_CMD2_SRANK_MATCH_EN = 3954; // 8
+static const uint64_t SH_FLD_CFG_CMD2_TYPE = 3955; // 8
+static const uint64_t SH_FLD_CFG_CMD2_TYPE_LEN = 3956; // 8
+static const uint64_t SH_FLD_CFG_CMD_TIMEOUT_MODE = 3957; // 2
+static const uint64_t SH_FLD_CFG_CMD_TIMEOUT_MODE_LEN = 3958; // 2
+static const uint64_t SH_FLD_CFG_CNPME_BITWISE_ENABLE = 3959; // 1
+static const uint64_t SH_FLD_CFG_CNPME_BITWISE_ENABLE_LEN = 3960; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP0_C0 = 3961; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP0_C0_LEN = 3962; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP0_C1 = 3963; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP0_C1_LEN = 3964; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP0_C2 = 3965; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP0_C2_LEN = 3966; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP0_C3 = 3967; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP0_C3_LEN = 3968; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP1_C0 = 3969; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP1_C0_LEN = 3970; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP1_C1 = 3971; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP1_C1_LEN = 3972; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP1_C2 = 3973; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP1_C2_LEN = 3974; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP1_C3 = 3975; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP1_C3_LEN = 3976; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP2_C0 = 3977; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP2_C0_LEN = 3978; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP2_C1 = 3979; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP2_C1_LEN = 3980; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP2_C2 = 3981; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP2_C2_LEN = 3982; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP2_C3 = 3983; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP2_C3_LEN = 3984; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP3_C0 = 3985; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP3_C0_LEN = 3986; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP3_C1 = 3987; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP3_C1_LEN = 3988; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP3_C2 = 3989; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP3_C2_LEN = 3990; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP3_C3 = 3991; // 1
+static const uint64_t SH_FLD_CFG_CNPME_GRP3_C3_LEN = 3992; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_BITWISE_ENABLE = 3993; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_BITWISE_ENABLE_LEN = 3994; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C0 = 3995; // 2
+static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C1 = 3996; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C1_LEN = 3997; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C2 = 3998; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C2_LEN = 3999; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C3 = 4000; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP0_C3_LEN = 4001; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C0 = 4002; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C0_LEN = 4003; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C1 = 4004; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C1_LEN = 4005; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C2 = 4006; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C2_LEN = 4007; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C3 = 4008; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP1_C3_LEN = 4009; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C0 = 4010; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C0_LEN = 4011; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C1 = 4012; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C1_LEN = 4013; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C2 = 4014; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C2_LEN = 4015; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C3 = 4016; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP2_C3_LEN = 4017; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C0 = 4018; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C0_LEN = 4019; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C1 = 4020; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C1_LEN = 4021; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C2 = 4022; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C2_LEN = 4023; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C3 = 4024; // 1
+static const uint64_t SH_FLD_CFG_CNPMW_GRP3_C3_LEN = 4025; // 1
+static const uint64_t SH_FLD_CFG_COMPA_PRESP = 4026; // 1
+static const uint64_t SH_FLD_CFG_COMPA_PRESP_LEN = 4027; // 1
+static const uint64_t SH_FLD_CFG_COMPA_PRESP_MASK = 4028; // 1
+static const uint64_t SH_FLD_CFG_COMPA_PRESP_MASK_LEN = 4029; // 1
+static const uint64_t SH_FLD_CFG_COMPA_SCOPE_MASK = 4030; // 1
+static const uint64_t SH_FLD_CFG_COMPA_SCOPE_MASK_LEN = 4031; // 1
+static const uint64_t SH_FLD_CFG_COMPB_PRESP = 4032; // 1
+static const uint64_t SH_FLD_CFG_COMPB_PRESP_LEN = 4033; // 1
+static const uint64_t SH_FLD_CFG_COMPB_PRESP_MASK = 4034; // 1
+static const uint64_t SH_FLD_CFG_COMPB_PRESP_MASK_LEN = 4035; // 1
+static const uint64_t SH_FLD_CFG_COMPB_SCOPE_MASK = 4036; // 1
+static const uint64_t SH_FLD_CFG_COMPB_SCOPE_MASK_LEN = 4037; // 1
+static const uint64_t SH_FLD_CFG_CORE_PUSH_EN = 4038; // 1
+static const uint64_t SH_FLD_CFG_COUNTER_MODE = 4039; // 2
+static const uint64_t SH_FLD_CFG_CO_SOFT_PURGE_ALL_LINES_EN = 4040; // 12
+static const uint64_t SH_FLD_CFG_CO_SOFT_PURGE_ME_SX_EN = 4041; // 12
+static const uint64_t SH_FLD_CFG_CPU_RATIO_OVERRIDE = 4042; // 1
+static const uint64_t SH_FLD_CFG_CPU_RATIO_OVERRIDE_LEN = 4043; // 1
+static const uint64_t SH_FLD_CFG_CRESP = 4044; // 2
+static const uint64_t SH_FLD_CFG_CRESP_LEN = 4045; // 2
+static const uint64_t SH_FLD_CFG_CRESP_MASK = 4046; // 2
+static const uint64_t SH_FLD_CFG_CRESP_MASK_LEN = 4047; // 2
+static const uint64_t SH_FLD_CFG_CRESP_POLARITY = 4048; // 2
+static const uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP = 4049; // 2
+static const uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP_LEN = 4050; // 2
+static const uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS = 4051; // 2
+static const uint64_t SH_FLD_CFG_CURRENT_DIMM_TRAP = 4052; // 2
+static const uint64_t SH_FLD_CFG_CURRENT_PORT_TRAP = 4053; // 2
+static const uint64_t SH_FLD_CFG_CURRENT_PORT_TRAP_LEN = 4054; // 2
+static const uint64_t SH_FLD_CFG_DATA_ROT = 4055; // 2
+static const uint64_t SH_FLD_CFG_DATA_ROT_LEN = 4056; // 2
+static const uint64_t SH_FLD_CFG_DATA_ROT_SEED = 4057; // 4
+static const uint64_t SH_FLD_CFG_DATA_ROT_SEED_LEN = 4058; // 4
+static const uint64_t SH_FLD_CFG_DATA_SEED_MODE = 4059; // 2
+static const uint64_t SH_FLD_CFG_DATA_SEED_MODE_LEN = 4060; // 2
+static const uint64_t SH_FLD_CFG_DBG_ENABLE = 4061; // 2
+static const uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT01 = 4062; // 2
+static const uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT01_LEN = 4063; // 2
+static const uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT23 = 4064; // 2
+static const uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT23_LEN = 4065; // 2
+static const uint64_t SH_FLD_CFG_DBG_PICK_MCBIST01 = 4066; // 2
+static const uint64_t SH_FLD_CFG_DBG_PICK_MCBIST01_LEN = 4067; // 2
+static const uint64_t SH_FLD_CFG_DBG_PICK_MCBIST23 = 4068; // 2
+static const uint64_t SH_FLD_CFG_DBG_PICK_MCBIST23_LEN = 4069; // 2
+static const uint64_t SH_FLD_CFG_DBG_SRQ_ENABLE = 4070; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL0 = 4071; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL0_LEN = 4072; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL1 = 4073; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL1_LEN = 4074; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL2 = 4075; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL2_LEN = 4076; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL3 = 4077; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL3_LEN = 4078; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL4 = 4079; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL4_LEN = 4080; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL5 = 4081; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL5_LEN = 4082; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL6 = 4083; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL6_LEN = 4084; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL7 = 4085; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL7_LEN = 4086; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL_OTHER_SRQ = 4087; // 8
+static const uint64_t SH_FLD_CFG_DBG_SRQ_SEL_OTHER_SRQ_LEN = 4088; // 8
+static const uint64_t SH_FLD_CFG_DCACHE_CAPP = 4089; // 6
+static const uint64_t SH_FLD_CFG_DCACHE_CAPP_LPC_EN = 4090; // 12
+static const uint64_t SH_FLD_CFG_DCBZ_TRASHMODE_EN = 4091; // 12
+static const uint64_t SH_FLD_CFG_DDR4E_BLIND_STEER_MODE = 4092; // 2
+static const uint64_t SH_FLD_CFG_DDR4_PARITY_ON_CID_DIS = 4093; // 8
+static const uint64_t SH_FLD_CFG_DDR_DPHY_NCLK = 4094; // 8
+static const uint64_t SH_FLD_CFG_DDR_DPHY_NCLK_LEN = 4095; // 8
+static const uint64_t SH_FLD_CFG_DDR_DPHY_PCLK = 4096; // 8
+static const uint64_t SH_FLD_CFG_DDR_DPHY_PCLK_LEN = 4097; // 8
+static const uint64_t SH_FLD_CFG_DDR_RESETN = 4098; // 8
+static const uint64_t SH_FLD_CFG_DGEN_FIXED_MODE = 4099; // 2
+static const uint64_t SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK = 4100; // 43
+static const uint64_t SH_FLD_CFG_DISABLE_FAST_PATH = 4101; // 8
+static const uint64_t SH_FLD_CFG_DISABLE_FORCE_TO_ZERO = 4102; // 43
+static const uint64_t SH_FLD_CFG_DISABLE_HEARTBEAT = 4103; // 43
+static const uint64_t SH_FLD_CFG_DISABLE_MALF_PULSE_GEN = 4104; // 43
+static const uint64_t SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK = 4105; // 43
+static const uint64_t SH_FLD_CFG_DISABLE_RCD_RECOVERY = 4106; // 8
+static const uint64_t SH_FLD_CFG_DISABLE_RD_PG_MODE = 4107; // 8
+static const uint64_t SH_FLD_CFG_DISABLE_RESET_RECOVER = 4108; // 8
+static const uint64_t SH_FLD_CFG_DISABLE_WR_PG_MODE = 4109; // 8
+static const uint64_t SH_FLD_CFG_DIS_CLK_IN_STR = 4110; // 8
+static const uint64_t SH_FLD_CFG_DIS_SMDR = 4111; // 8
+static const uint64_t SH_FLD_CFG_DONE_IACK_PRIO_HYP = 4112; // 1
+static const uint64_t SH_FLD_CFG_DONE_IACK_PRIO_HYP_LEN = 4113; // 1
+static const uint64_t SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL = 4114; // 1
+static const uint64_t SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL_LEN = 4115; // 1
+static const uint64_t SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL = 4116; // 1
+static const uint64_t SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL_LEN = 4117; // 1
+static const uint64_t SH_FLD_CFG_DONE_PRIO_IACK = 4118; // 1
+static const uint64_t SH_FLD_CFG_DONE_PRIO_IACK_LEN = 4119; // 1
+static const uint64_t SH_FLD_CFG_DONE_PULL_PRIO_HYP = 4120; // 1
+static const uint64_t SH_FLD_CFG_DONE_PULL_PRIO_HYP_LEN = 4121; // 1
+static const uint64_t SH_FLD_CFG_DQS_ALIGNMENT_LENGTH = 4122; // 8
+static const uint64_t SH_FLD_CFG_DQS_ALIGNMENT_LENGTH_LEN = 4123; // 8
+static const uint64_t SH_FLD_CFG_DQS_ALIGNMENT_TB = 4124; // 8
+static const uint64_t SH_FLD_CFG_DQS_ALIGNMENT_TB_LEN = 4125; // 8
+static const uint64_t SH_FLD_CFG_ECCCK_CE_UE_SUE_ERR_DET_DIS = 4126; // 12
+static const uint64_t SH_FLD_CFG_ECCCK_UE_SUE_DET_DIS = 4127; // 12
+static const uint64_t SH_FLD_CFG_EMER_MIN_MAX_DOMAIN = 4128; // 8
+static const uint64_t SH_FLD_CFG_EMER_MIN_MAX_DOMAIN_LEN = 4129; // 8
+static const uint64_t SH_FLD_CFG_EN = 4130; // 3
+static const uint64_t SH_FLD_CFG_ENABLE_HOST_ATTN = 4131; // 10
+static const uint64_t SH_FLD_CFG_ENABLE_PERFTRACE_FIXED_WIN = 4132; // 1
+static const uint64_t SH_FLD_CFG_ENABLE_PERFTRACE_PRESCALE = 4133; // 1
+static const uint64_t SH_FLD_CFG_ENABLE_SPEC_ATTN = 4134; // 10
+static const uint64_t SH_FLD_CFG_END_ADDR_0 = 4135; // 2
+static const uint64_t SH_FLD_CFG_END_ADDR_0_LEN = 4136; // 2
+static const uint64_t SH_FLD_CFG_END_ADDR_1 = 4137; // 2
+static const uint64_t SH_FLD_CFG_END_ADDR_1_LEN = 4138; // 2
+static const uint64_t SH_FLD_CFG_END_ADDR_2 = 4139; // 2
+static const uint64_t SH_FLD_CFG_END_ADDR_2_LEN = 4140; // 2
+static const uint64_t SH_FLD_CFG_END_ADDR_3 = 4141; // 2
+static const uint64_t SH_FLD_CFG_END_ADDR_3_LEN = 4142; // 2
+static const uint64_t SH_FLD_CFG_ENTER_STR_TIME = 4143; // 8
+static const uint64_t SH_FLD_CFG_ENTER_STR_TIME_LEN = 4144; // 8
+static const uint64_t SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR = 4145; // 8
+static const uint64_t SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN = 4146; // 8
+static const uint64_t SH_FLD_CFG_EN_RANDCMD_GAP = 4147; // 2
+static const uint64_t SH_FLD_CFG_EVENT0_SELECT = 4148; // 8
+static const uint64_t SH_FLD_CFG_EVENT0_SELECT_LEN = 4149; // 8
+static const uint64_t SH_FLD_CFG_EVENT1_SELECT = 4150; // 8
+static const uint64_t SH_FLD_CFG_EVENT1_SELECT_LEN = 4151; // 8
+static const uint64_t SH_FLD_CFG_EVENT2_SELECT = 4152; // 8
+static const uint64_t SH_FLD_CFG_EVENT2_SELECT_LEN = 4153; // 8
+static const uint64_t SH_FLD_CFG_EVENT3_SELECT = 4154; // 8
+static const uint64_t SH_FLD_CFG_EVENT3_SELECT_LEN = 4155; // 8
+static const uint64_t SH_FLD_CFG_EXTERNAL_FREEZE = 4156; // 2
+static const uint64_t SH_FLD_CFG_EXTERNAL_ZQ_LENGTH = 4157; // 8
+static const uint64_t SH_FLD_CFG_EXTERNAL_ZQ_LENGTH_LEN = 4158; // 8
+static const uint64_t SH_FLD_CFG_EXTERNAL_ZQ_TB = 4159; // 8
+static const uint64_t SH_FLD_CFG_EXTERNAL_ZQ_TB_LEN = 4160; // 8
+static const uint64_t SH_FLD_CFG_FARB_CLOSE_ALL_PAGES = 4161; // 8
+static const uint64_t SH_FLD_CFG_FIXED_SEED = 4162; // 16
+static const uint64_t SH_FLD_CFG_FIXED_SEED1 = 4163; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED1_LEN = 4164; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED2 = 4165; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED2_LEN = 4166; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED3 = 4167; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED3_LEN = 4168; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED4 = 4169; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED4_LEN = 4170; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED5 = 4171; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED5_LEN = 4172; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED6 = 4173; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED6_LEN = 4174; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED7 = 4175; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED7_LEN = 4176; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED8 = 4177; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED8_LEN = 4178; // 2
+static const uint64_t SH_FLD_CFG_FIXED_SEED_LEN = 4179; // 16
+static const uint64_t SH_FLD_CFG_FIXED_WIDTH = 4180; // 2
+static const uint64_t SH_FLD_CFG_FIXED_WIDTH_LEN = 4181; // 2
+static const uint64_t SH_FLD_CFG_FORCE_MCLK_LOW_N = 4182; // 8
+static const uint64_t SH_FLD_CFG_FORCE_SPARE_PUP = 4183; // 8
+static const uint64_t SH_FLD_CFG_FREEZE_ON_PARITY_ERROR_DIS = 4184; // 8
+static const uint64_t SH_FLD_CFG_FUSE_CORE_EN = 4185; // 1
+static const uint64_t SH_FLD_CFG_GLOBAL_PMISC_DIS = 4186; // 2
+static const uint64_t SH_FLD_CFG_GLOBAL_PMISC_MODE = 4187; // 2
+static const uint64_t SH_FLD_CFG_GP_BIT_3_ENABLE = 4188; // 8
+static const uint64_t SH_FLD_CFG_GP_HW_MARK = 4189; // 3
+static const uint64_t SH_FLD_CFG_GP_HW_MARK_LEN = 4190; // 3
+static const uint64_t SH_FLD_CFG_HARD_CHIPID_IN_BLOCK_EN = 4191; // 1
+static const uint64_t SH_FLD_CFG_HASH_L3_ADDR_EN = 4192; // 12
+static const uint64_t SH_FLD_CFG_HNG_CHK_DISABLE = 4193; // 3
+static const uint64_t SH_FLD_CFG_HOP = 4194; // 6
+static const uint64_t SH_FLD_CFG_HW_TRIG_LINEDEL_LDDISP_CE_EN = 4195; // 12
+static const uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_ADDR5 = 4196; // 8
+static const uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_CONSTANT = 4197; // 8
+static const uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_WEN = 4198; // 8
+static const uint64_t SH_FLD_CFG_INJ_CANCEL_ACK_ERR = 4199; // 8
+static const uint64_t SH_FLD_CFG_INTERNAL_ZQ_LENGTH = 4200; // 8
+static const uint64_t SH_FLD_CFG_INTERNAL_ZQ_LENGTH_LEN = 4201; // 8
+static const uint64_t SH_FLD_CFG_INTERNAL_ZQ_TB = 4202; // 8
+static const uint64_t SH_FLD_CFG_INTERNAL_ZQ_TB_LEN = 4203; // 8
+static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR0 = 4204; // 8
+static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR0_LEN = 4205; // 8
+static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR1 = 4206; // 8
+static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR1_LEN = 4207; // 8
+static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR2 = 4208; // 8
+static const uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR2_LEN = 4209; // 8
+static const uint64_t SH_FLD_CFG_INT_MASK = 4210; // 1
+static const uint64_t SH_FLD_CFG_L3_DIS = 4211; // 12
+static const uint64_t SH_FLD_CFG_LCL_HW_MARK = 4212; // 3
+static const uint64_t SH_FLD_CFG_LCL_HW_MARK_LEN = 4213; // 3
+static const uint64_t SH_FLD_CFG_LDST_PRIO_RSP_LD = 4214; // 1
+static const uint64_t SH_FLD_CFG_LDST_PRIO_RSP_LD_LEN = 4215; // 1
+static const uint64_t SH_FLD_CFG_LDST_PRIO_SET_LD = 4216; // 1
+static const uint64_t SH_FLD_CFG_LDST_PRIO_SET_LD_LEN = 4217; // 1
+static const uint64_t SH_FLD_CFG_LFSR_MASK_A0 = 4218; // 2
+static const uint64_t SH_FLD_CFG_LFSR_MASK_A0_LEN = 4219; // 2
+static const uint64_t SH_FLD_CFG_LINEDEL_ON_CAC_UE_EN = 4220; // 12
+static const uint64_t SH_FLD_CFG_LINK_A0_EN = 4221; // 6
+static const uint64_t SH_FLD_CFG_LINK_A0_GROUPID = 4222; // 6
+static const uint64_t SH_FLD_CFG_LINK_A0_GROUPID_LEN = 4223; // 6
+static const uint64_t SH_FLD_CFG_LINK_A1_EN = 4224; // 6
+static const uint64_t SH_FLD_CFG_LINK_A1_GROUPID = 4225; // 6
+static const uint64_t SH_FLD_CFG_LINK_A1_GROUPID_LEN = 4226; // 6
+static const uint64_t SH_FLD_CFG_LINK_A2_EN = 4227; // 6
+static const uint64_t SH_FLD_CFG_LINK_A2_GROUPID = 4228; // 6
+static const uint64_t SH_FLD_CFG_LINK_A2_GROUPID_LEN = 4229; // 6
+static const uint64_t SH_FLD_CFG_LINK_A3_EN = 4230; // 6
+static const uint64_t SH_FLD_CFG_LINK_A3_GROUPID = 4231; // 6
+static const uint64_t SH_FLD_CFG_LINK_A3_GROUPID_LEN = 4232; // 6
+static const uint64_t SH_FLD_CFG_LINK_NA0_ADDR_DIS = 4233; // 6
+static const uint64_t SH_FLD_CFG_LINK_NA1_ADDR_DIS = 4234; // 6
+static const uint64_t SH_FLD_CFG_LINK_NA2_ADDR_DIS = 4235; // 6
+static const uint64_t SH_FLD_CFG_LINK_NA3_ADDR_DIS = 4236; // 6
+static const uint64_t SH_FLD_CFG_LINK_NX0_ADDR_DIS = 4237; // 6
+static const uint64_t SH_FLD_CFG_LINK_NX1_ADDR_DIS = 4238; // 6
+static const uint64_t SH_FLD_CFG_LINK_NX2_ADDR_DIS = 4239; // 6
+static const uint64_t SH_FLD_CFG_LINK_NX3_ADDR_DIS = 4240; // 6
+static const uint64_t SH_FLD_CFG_LINK_NX4_ADDR_DIS = 4241; // 6
+static const uint64_t SH_FLD_CFG_LINK_NX5_ADDR_DIS = 4242; // 6
+static const uint64_t SH_FLD_CFG_LINK_NX6_ADDR_DIS = 4243; // 6
+static const uint64_t SH_FLD_CFG_LINK_X0_CHIPID = 4244; // 6
+static const uint64_t SH_FLD_CFG_LINK_X0_CHIPID_LEN = 4245; // 6
+static const uint64_t SH_FLD_CFG_LINK_X0_EN = 4246; // 6
+static const uint64_t SH_FLD_CFG_LINK_X1_CHIPID = 4247; // 6
+static const uint64_t SH_FLD_CFG_LINK_X1_CHIPID_LEN = 4248; // 6
+static const uint64_t SH_FLD_CFG_LINK_X1_EN = 4249; // 6
+static const uint64_t SH_FLD_CFG_LINK_X2_CHIPID = 4250; // 6
+static const uint64_t SH_FLD_CFG_LINK_X2_CHIPID_LEN = 4251; // 6
+static const uint64_t SH_FLD_CFG_LINK_X2_EN = 4252; // 6
+static const uint64_t SH_FLD_CFG_LINK_X3_CHIPID = 4253; // 6
+static const uint64_t SH_FLD_CFG_LINK_X3_CHIPID_LEN = 4254; // 6
+static const uint64_t SH_FLD_CFG_LINK_X3_EN = 4255; // 6
+static const uint64_t SH_FLD_CFG_LINK_X4_CHIPID = 4256; // 6
+static const uint64_t SH_FLD_CFG_LINK_X4_CHIPID_LEN = 4257; // 6
+static const uint64_t SH_FLD_CFG_LINK_X4_EN = 4258; // 6
+static const uint64_t SH_FLD_CFG_LINK_X5_CHIPID = 4259; // 6
+static const uint64_t SH_FLD_CFG_LINK_X5_CHIPID_LEN = 4260; // 6
+static const uint64_t SH_FLD_CFG_LINK_X5_EN = 4261; // 6
+static const uint64_t SH_FLD_CFG_LINK_X6_CHIPID = 4262; // 6
+static const uint64_t SH_FLD_CFG_LINK_X6_CHIPID_LEN = 4263; // 6
+static const uint64_t SH_FLD_CFG_LINK_X6_EN = 4264; // 6
+static const uint64_t SH_FLD_CFG_LOGIC_SIGNALED_ERROR = 4265; // 6
+static const uint64_t SH_FLD_CFG_LOG_COUNTS_IN_TRACE = 4266; // 2
+static const uint64_t SH_FLD_CFG_LP_SUB_CNT = 4267; // 8
+static const uint64_t SH_FLD_CFG_LP_SUB_CNT_LEN = 4268; // 8
+static const uint64_t SH_FLD_CFG_LRU_DIRECT_MAP = 4269; // 12
+static const uint64_t SH_FLD_CFG_LTE_MC = 4270; // 2
+static const uint64_t SH_FLD_CFG_LTE_MC_LEN = 4271; // 2
+static const uint64_t SH_FLD_CFG_LVL0 = 4272; // 2
+static const uint64_t SH_FLD_CFG_LVL0_LEN = 4273; // 2
+static const uint64_t SH_FLD_CFG_LVL1 = 4274; // 2
+static const uint64_t SH_FLD_CFG_LVL1_LEN = 4275; // 2
+static const uint64_t SH_FLD_CFG_LVL2 = 4276; // 2
+static const uint64_t SH_FLD_CFG_LVL2_LEN = 4277; // 2
+static const uint64_t SH_FLD_CFG_LVL3 = 4278; // 2
+static const uint64_t SH_FLD_CFG_LVL3_LEN = 4279; // 2
+static const uint64_t SH_FLD_CFG_LVL4 = 4280; // 2
+static const uint64_t SH_FLD_CFG_LVL4_LEN = 4281; // 2
+static const uint64_t SH_FLD_CFG_LVL5 = 4282; // 2
+static const uint64_t SH_FLD_CFG_LVL5_LEN = 4283; // 2
+static const uint64_t SH_FLD_CFG_LVL6 = 4284; // 2
+static const uint64_t SH_FLD_CFG_LVL6_LEN = 4285; // 2
+static const uint64_t SH_FLD_CFG_LVL7 = 4286; // 2
+static const uint64_t SH_FLD_CFG_LVL7_LEN = 4287; // 2
+static const uint64_t SH_FLD_CFG_MAINT_ADDR_MODE_EN = 4288; // 2
+static const uint64_t SH_FLD_CFG_MAINT_BROADCAST_MODE_EN = 4289; // 2
+static const uint64_t SH_FLD_CFG_MAINT_DETECT_SRANK_BOUNDARIES = 4290; // 2
+static const uint64_t SH_FLD_CFG_MAINT_RCE_WITH_CE = 4291; // 2
+static const uint64_t SH_FLD_CFG_MASK = 4292; // 2
+static const uint64_t SH_FLD_CFG_MASTER_CHIP = 4293; // 6
+static const uint64_t SH_FLD_CFG_MAX = 4294; // 1
+static const uint64_t SH_FLD_CFG_MAX_LEN = 4295; // 1
+static const uint64_t SH_FLD_CFG_MAX_READS_IN_A_ROW = 4296; // 8
+static const uint64_t SH_FLD_CFG_MAX_READS_IN_A_ROW_LEN = 4297; // 8
+static const uint64_t SH_FLD_CFG_MAX_WRITES_IN_A_ROW = 4298; // 8
+static const uint64_t SH_FLD_CFG_MAX_WRITES_IN_A_ROW_LEN = 4299; // 8
+static const uint64_t SH_FLD_CFG_MC0_MCS0_MASK = 4300; // 1
+static const uint64_t SH_FLD_CFG_MC0_MCS1_MASK = 4301; // 1
+static const uint64_t SH_FLD_CFG_MC1_MCS0_MASK = 4302; // 1
+static const uint64_t SH_FLD_CFG_MC1_MCS1_MASK = 4303; // 1
+static const uint64_t SH_FLD_CFG_MC2_MCS0_MASK = 4304; // 1
+static const uint64_t SH_FLD_CFG_MC2_MCS1_MASK = 4305; // 1
+static const uint64_t SH_FLD_CFG_MC3_MCS0_MASK = 4306; // 1
+static const uint64_t SH_FLD_CFG_MC3_MCS1_MASK = 4307; // 1
+static const uint64_t SH_FLD_CFG_MCB_LEN64 = 4308; // 2
+static const uint64_t SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS = 4309; // 2
+static const uint64_t SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS_LEN = 4310; // 2
+static const uint64_t SH_FLD_CFG_MCD_MASK = 4311; // 1
+static const uint64_t SH_FLD_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE = 4312; // 2
+static const uint64_t SH_FLD_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE = 4313; // 2
+static const uint64_t SH_FLD_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE = 4314; // 2
+static const uint64_t SH_FLD_CFG_MIN_CMD_GAP = 4315; // 2
+static const uint64_t SH_FLD_CFG_MIN_CMD_GAP_BLIND_STEER = 4316; // 2
+static const uint64_t SH_FLD_CFG_MIN_CMD_GAP_BLIND_STEER_LEN = 4317; // 2
+static const uint64_t SH_FLD_CFG_MIN_CMD_GAP_LEN = 4318; // 2
+static const uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_CNT_REFR_INT = 4319; // 8
+static const uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_ENABLE = 4320; // 8
+static const uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME = 4321; // 8
+static const uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN = 4322; // 8
+static const uint64_t SH_FLD_CFG_MIN_GAP_TIMEBASE = 4323; // 2
+static const uint64_t SH_FLD_CFG_MIN_GAP_TIMEBASE_BLIND_STEER = 4324; // 2
+static const uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS = 4325; // 8
+static const uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS_ENABLE = 4326; // 8
+static const uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS_LEN = 4327; // 8
+static const uint64_t SH_FLD_CFG_MISR_BLOCK = 4328; // 8
+static const uint64_t SH_FLD_CFG_MISR_BLOCK_LEN = 4329; // 8
+static const uint64_t SH_FLD_CFG_MISR_FEEDBACK_ENABLE = 4330; // 8
+static const uint64_t SH_FLD_CFG_MPR_READEYE_LENGTH = 4331; // 8
+static const uint64_t SH_FLD_CFG_MPR_READEYE_LENGTH_LEN = 4332; // 8
+static const uint64_t SH_FLD_CFG_MPR_READEYE_TB = 4333; // 8
+static const uint64_t SH_FLD_CFG_MPR_READEYE_TB_LEN = 4334; // 8
+static const uint64_t SH_FLD_CFG_MSGSND = 4335; // 1
+static const uint64_t SH_FLD_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE = 4336; // 2
+static const uint64_t SH_FLD_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE = 4337; // 2
+static const uint64_t SH_FLD_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE = 4338; // 2
+static const uint64_t SH_FLD_CFG_NM_CAS_WEIGHT = 4339; // 8
+static const uint64_t SH_FLD_CFG_NM_CAS_WEIGHT_LEN = 4340; // 8
+static const uint64_t SH_FLD_CFG_NM_CHANGE_AFTER_SYNC = 4341; // 8
+static const uint64_t SH_FLD_CFG_NM_M = 4342; // 8
+static const uint64_t SH_FLD_CFG_NM_M_LEN = 4343; // 8
+static const uint64_t SH_FLD_CFG_NM_N_PER_PORT = 4344; // 8
+static const uint64_t SH_FLD_CFG_NM_N_PER_PORT_LEN = 4345; // 8
+static const uint64_t SH_FLD_CFG_NM_N_PER_SLOT = 4346; // 8
+static const uint64_t SH_FLD_CFG_NM_N_PER_SLOT_LEN = 4347; // 8
+static const uint64_t SH_FLD_CFG_NM_RAS_WEIGHT = 4348; // 8
+static const uint64_t SH_FLD_CFG_NM_RAS_WEIGHT_LEN = 4349; // 8
+static const uint64_t SH_FLD_CFG_NOISE_WAIT_TIME = 4350; // 8
+static const uint64_t SH_FLD_CFG_NOISE_WAIT_TIME_LEN = 4351; // 8
+static const uint64_t SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL = 4352; // 8
+static const uint64_t SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL_LEN = 4353; // 8
+static const uint64_t SH_FLD_CFG_OE_ALL_CKE_POWERED_DOWN = 4354; // 8
+static const uint64_t SH_FLD_CFG_OE_ALWAYS_ON = 4355; // 8
+static const uint64_t SH_FLD_CFG_OPT0 = 4356; // 6
+static const uint64_t SH_FLD_CFG_OPT0_LEN = 4357; // 6
+static const uint64_t SH_FLD_CFG_OPT1 = 4358; // 6
+static const uint64_t SH_FLD_CFG_OPT1_LEN = 4359; // 6
+static const uint64_t SH_FLD_CFG_OPT2 = 4360; // 6
+static const uint64_t SH_FLD_CFG_OPT2_LEN = 4361; // 6
+static const uint64_t SH_FLD_CFG_OPT3 = 4362; // 6
+static const uint64_t SH_FLD_CFG_OPT3_LEN = 4363; // 6
+static const uint64_t SH_FLD_CFG_OPT_RD_SIZE = 4364; // 8
+static const uint64_t SH_FLD_CFG_OPT_RD_SIZE_LEN = 4365; // 8
+static const uint64_t SH_FLD_CFG_PARITY_AFTER_CMD = 4366; // 10
+static const uint64_t SH_FLD_CFG_PARITY_DETECT_TIME = 4367; // 8
+static const uint64_t SH_FLD_CFG_PARITY_DETECT_TIME_LEN = 4368; // 8
+static const uint64_t SH_FLD_CFG_PARSE_PULL_RR_SEL = 4369; // 1
+static const uint64_t SH_FLD_CFG_PARSE_PULL_RR_SEL_LEN = 4370; // 1
+static const uint64_t SH_FLD_CFG_PARSE_PUSH_RR_SEL = 4371; // 1
+static const uint64_t SH_FLD_CFG_PARSE_PUSH_RR_SEL_LEN = 4372; // 1
+static const uint64_t SH_FLD_CFG_PARSE_QUERY_RR_SEL = 4373; // 1
+static const uint64_t SH_FLD_CFG_PAUSE_MCB_ERROR = 4374; // 2
+static const uint64_t SH_FLD_CFG_PAUSE_MCB_LOG_FULL = 4375; // 2
+static const uint64_t SH_FLD_CFG_PAUSE_ON_AUE = 4376; // 2
+static const uint64_t SH_FLD_CFG_PAUSE_ON_ERROR_MODE = 4377; // 2
+static const uint64_t SH_FLD_CFG_PAUSE_ON_ERROR_MODE_LEN = 4378; // 2
+static const uint64_t SH_FLD_CFG_PAUSE_ON_MCE = 4379; // 2
+static const uint64_t SH_FLD_CFG_PAUSE_ON_MPE = 4380; // 2
+static const uint64_t SH_FLD_CFG_PAUSE_ON_RCD = 4381; // 2
+static const uint64_t SH_FLD_CFG_PAUSE_ON_SCE = 4382; // 2
+static const uint64_t SH_FLD_CFG_PAUSE_ON_SUE = 4383; // 2
+static const uint64_t SH_FLD_CFG_PAUSE_ON_UE = 4384; // 2
+static const uint64_t SH_FLD_CFG_PBIEN_DBG_0_SEL = 4385; // 1
+static const uint64_t SH_FLD_CFG_PBIEN_DBG_0_SEL_LEN = 4386; // 1
+static const uint64_t SH_FLD_CFG_PBIEN_DBG_1_SEL = 4387; // 1
+static const uint64_t SH_FLD_CFG_PBIEN_DBG_1_SEL_LEN = 4388; // 1
+static const uint64_t SH_FLD_CFG_PBIES_DBG_0_SEL = 4389; // 1
+static const uint64_t SH_FLD_CFG_PBIES_DBG_0_SEL_LEN = 4390; // 1
+static const uint64_t SH_FLD_CFG_PBIES_DBG_1_SEL = 4391; // 1
+static const uint64_t SH_FLD_CFG_PBIES_DBG_1_SEL_LEN = 4392; // 1
+static const uint64_t SH_FLD_CFG_PBIOT_DBG_0_SEL = 4393; // 1
+static const uint64_t SH_FLD_CFG_PBIOT_DBG_0_SEL_LEN = 4394; // 1
+static const uint64_t SH_FLD_CFG_PBIOT_DBG_1_SEL = 4395; // 1
+static const uint64_t SH_FLD_CFG_PBIOT_DBG_1_SEL_LEN = 4396; // 1
+static const uint64_t SH_FLD_CFG_PBIOT_SEL = 4397; // 1
+static const uint64_t SH_FLD_CFG_PCMD_PRIO_DONE = 4398; // 1
+static const uint64_t SH_FLD_CFG_PCMD_PRIO_DONE_LEN = 4399; // 1
+static const uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_RSP = 4400; // 1
+static const uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_RSP_LEN = 4401; // 1
+static const uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_SET = 4402; // 1
+static const uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_SET_LEN = 4403; // 1
+static const uint64_t SH_FLD_CFG_PCMD_PRIO_RR = 4404; // 1
+static const uint64_t SH_FLD_CFG_PCMD_PRIO_RR_LEN = 4405; // 1
+static const uint64_t SH_FLD_CFG_PDN_PUP = 4406; // 8
+static const uint64_t SH_FLD_CFG_PDN_PUP_LEN = 4407; // 8
+static const uint64_t SH_FLD_CFG_PE0_MASK = 4408; // 2
+static const uint64_t SH_FLD_CFG_PE1_MASK = 4409; // 2
+static const uint64_t SH_FLD_CFG_PE2_MASK = 4410; // 2
+static const uint64_t SH_FLD_CFG_PERFMON_INFO_SRC_ED_SEL = 4411; // 12
+static const uint64_t SH_FLD_CFG_PERFTRACE_COUNTER_MATCH = 4412; // 1
+static const uint64_t SH_FLD_CFG_PERFTRACE_COUNTER_MATCH_LEN = 4413; // 1
+static const uint64_t SH_FLD_CFG_PERFTRACE_COUNTER_SEL = 4414; // 1
+static const uint64_t SH_FLD_CFG_PERFTRACE_COUNTER_SEL_LEN = 4415; // 1
+static const uint64_t SH_FLD_CFG_PERFTRACE_EN = 4416; // 1
+static const uint64_t SH_FLD_CFG_PERFTRACE_GRP1_SEL = 4417; // 1
+static const uint64_t SH_FLD_CFG_PERFTRACE_GRP2_SEL = 4418; // 1
+static const uint64_t SH_FLD_CFG_PERFTRACE_TRIG = 4419; // 1
+static const uint64_t SH_FLD_CFG_PER_BANK_REFRESH = 4420; // 8
+static const uint64_t SH_FLD_CFG_PE_MATCH0 = 4421; // 1
+static const uint64_t SH_FLD_CFG_PE_MATCH0_LEN = 4422; // 1
+static const uint64_t SH_FLD_CFG_PE_MATCH1 = 4423; // 1
+static const uint64_t SH_FLD_CFG_PE_MATCH1_LEN = 4424; // 1
+static const uint64_t SH_FLD_CFG_PHYP_IS_GROUP = 4425; // 6
+static const uint64_t SH_FLD_CFG_PMUCNT_EN = 4426; // 1
+static const uint64_t SH_FLD_CFG_PMUCNT_SEL = 4427; // 1
+static const uint64_t SH_FLD_CFG_PMUCNT_SEL_LEN = 4428; // 1
+static const uint64_t SH_FLD_CFG_PMU_FREEZE_MODE = 4429; // 1
+static const uint64_t SH_FLD_CFG_PMU_PORT = 4430; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL0 = 4431; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL0_LEN = 4432; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL1 = 4433; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL1_LEN = 4434; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL2 = 4435; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL2_LEN = 4436; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL3 = 4437; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL3_LEN = 4438; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL4 = 4439; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL4_LEN = 4440; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL5 = 4441; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL5_LEN = 4442; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL6 = 4443; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL6_LEN = 4444; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL7 = 4445; // 1
+static const uint64_t SH_FLD_CFG_PMU_SEL7_LEN = 4446; // 1
+static const uint64_t SH_FLD_CFG_PM_DISABLE = 4447; // 43
+static const uint64_t SH_FLD_CFG_PM_MUX_DISABLE = 4448; // 43
+static const uint64_t SH_FLD_CFG_PORT_FAIL_DISABLE = 4449; // 8
+static const uint64_t SH_FLD_CFG_PRECHARGE_WAIT_TIME = 4450; // 8
+static const uint64_t SH_FLD_CFG_PRECHARGE_WAIT_TIME_LEN = 4451; // 8
+static const uint64_t SH_FLD_CFG_PRESCALER_C0 = 4452; // 8
+static const uint64_t SH_FLD_CFG_PRESCALER_C0_LEN = 4453; // 8
+static const uint64_t SH_FLD_CFG_PRESCALER_C1 = 4454; // 8
+static const uint64_t SH_FLD_CFG_PRESCALER_C1_LEN = 4455; // 8
+static const uint64_t SH_FLD_CFG_PRESCALER_C2 = 4456; // 8
+static const uint64_t SH_FLD_CFG_PRESCALER_C2_LEN = 4457; // 8
+static const uint64_t SH_FLD_CFG_PRESCALER_C3 = 4458; // 8
+static const uint64_t SH_FLD_CFG_PRESCALER_C3_LEN = 4459; // 8
+static const uint64_t SH_FLD_CFG_PRIO_LSI = 4460; // 1
+static const uint64_t SH_FLD_CFG_PRIO_LSI_LEN = 4461; // 1
+static const uint64_t SH_FLD_CFG_PRIO_MMIO = 4462; // 1
+static const uint64_t SH_FLD_CFG_PRIO_MMIO_LEN = 4463; // 1
+static const uint64_t SH_FLD_CFG_PRIO_PULL = 4464; // 2
+static const uint64_t SH_FLD_CFG_PRIO_PULL_LEN = 4465; // 2
+static const uint64_t SH_FLD_CFG_PRIO_PUSH = 4466; // 1
+static const uint64_t SH_FLD_CFG_PRIO_PUSH_ARX = 4467; // 1
+static const uint64_t SH_FLD_CFG_PRIO_PUSH_ARX_LEN = 4468; // 1
+static const uint64_t SH_FLD_CFG_PRIO_PUSH_LCL = 4469; // 1
+static const uint64_t SH_FLD_CFG_PRIO_PUSH_LCL_LEN = 4470; // 1
+static const uint64_t SH_FLD_CFG_PRIO_PUSH_LEN = 4471; // 1
+static const uint64_t SH_FLD_CFG_PRIO_QUERY = 4472; // 1
+static const uint64_t SH_FLD_CFG_PRIO_QUERY_LEN = 4473; // 1
+static const uint64_t SH_FLD_CFG_PRIO_RR = 4474; // 3
+static const uint64_t SH_FLD_CFG_PRIO_RR_LEN = 4475; // 3
+static const uint64_t SH_FLD_CFG_PRIO_RSVD = 4476; // 1
+static const uint64_t SH_FLD_CFG_PRIO_RSVD_LEN = 4477; // 1
+static const uint64_t SH_FLD_CFG_PRIO_VRQ_REQ = 4478; // 1
+static const uint64_t SH_FLD_CFG_PRIO_VRQ_REQ_LEN = 4479; // 1
+static const uint64_t SH_FLD_CFG_PRIO_VRQ_RSP = 4480; // 1
+static const uint64_t SH_FLD_CFG_PRIO_VRQ_RSP_LEN = 4481; // 1
+static const uint64_t SH_FLD_CFG_PULL_LMIT = 4482; // 1
+static const uint64_t SH_FLD_CFG_PULL_LMIT_LEN = 4483; // 1
+static const uint64_t SH_FLD_CFG_PULL_PRIO_HYP = 4484; // 1
+static const uint64_t SH_FLD_CFG_PULL_PRIO_HYP_LEN = 4485; // 1
+static const uint64_t SH_FLD_CFG_PULL_RSVD = 4486; // 1
+static const uint64_t SH_FLD_CFG_PULL_RSVD_LEN = 4487; // 1
+static const uint64_t SH_FLD_CFG_PULSE_WIDTH = 4488; // 1
+static const uint64_t SH_FLD_CFG_PULSE_WIDTH_LEN = 4489; // 1
+static const uint64_t SH_FLD_CFG_PUMP = 4490; // 8
+static const uint64_t SH_FLD_CFG_PUMP_MODE = 4491; // 1
+static const uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE = 4492; // 8
+static const uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME = 4493; // 8
+static const uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN = 4494; // 8
+static const uint64_t SH_FLD_CFG_PUP_ALL_WRITES_PENDING = 4495; // 8
+static const uint64_t SH_FLD_CFG_PUP_AVAIL = 4496; // 8
+static const uint64_t SH_FLD_CFG_PUP_AVAIL_LEN = 4497; // 8
+static const uint64_t SH_FLD_CFG_PUP_PDN = 4498; // 8
+static const uint64_t SH_FLD_CFG_PUP_PDN_LEN = 4499; // 8
+static const uint64_t SH_FLD_CFG_PUSH_ARX_LMIT = 4500; // 1
+static const uint64_t SH_FLD_CFG_PUSH_ARX_LMIT_LEN = 4501; // 1
+static const uint64_t SH_FLD_CFG_PUSH_ARX_RSVD = 4502; // 1
+static const uint64_t SH_FLD_CFG_PUSH_ARX_RSVD_LEN = 4503; // 1
+static const uint64_t SH_FLD_CFG_PUSH_LCL_LMIT = 4504; // 1
+static const uint64_t SH_FLD_CFG_PUSH_LCL_LMIT_LEN = 4505; // 1
+static const uint64_t SH_FLD_CFG_PUSH_LCL_RSVD = 4506; // 1
+static const uint64_t SH_FLD_CFG_PUSH_LCL_RSVD_LEN = 4507; // 1
+static const uint64_t SH_FLD_CFG_PUSH_PRIO_HYP = 4508; // 1
+static const uint64_t SH_FLD_CFG_PUSH_PRIO_HYP_LEN = 4509; // 1
+static const uint64_t SH_FLD_CFG_QUEUE_SIZE_PULL = 4510; // 1
+static const uint64_t SH_FLD_CFG_QUEUE_SIZE_PULL_LEN = 4511; // 1
+static const uint64_t SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL = 4512; // 1
+static const uint64_t SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL_LEN = 4513; // 1
+static const uint64_t SH_FLD_CFG_Q_BIT_TID_MASK = 4514; // 12
+static const uint64_t SH_FLD_CFG_Q_BIT_TID_MASK_LEN = 4515; // 12
+static const uint64_t SH_FLD_CFG_RANDCMD_WGT = 4516; // 2
+static const uint64_t SH_FLD_CFG_RANDCMD_WGT_LEN = 4517; // 2
+static const uint64_t SH_FLD_CFG_RANDGAP_WGT = 4518; // 2
+static const uint64_t SH_FLD_CFG_RANDGAP_WGT_LEN = 4519; // 2
+static const uint64_t SH_FLD_CFG_RANDOM_EN = 4520; // 12
+static const uint64_t SH_FLD_CFG_RANK0_RD_ODT = 4521; // 8
+static const uint64_t SH_FLD_CFG_RANK0_RD_ODT_LEN = 4522; // 8
+static const uint64_t SH_FLD_CFG_RANK0_WR_ODT = 4523; // 8
+static const uint64_t SH_FLD_CFG_RANK0_WR_ODT_LEN = 4524; // 8
+static const uint64_t SH_FLD_CFG_RANK1_RD_ODT = 4525; // 8
+static const uint64_t SH_FLD_CFG_RANK1_RD_ODT_LEN = 4526; // 8
+static const uint64_t SH_FLD_CFG_RANK1_WR_ODT = 4527; // 8
+static const uint64_t SH_FLD_CFG_RANK1_WR_ODT_LEN = 4528; // 8
+static const uint64_t SH_FLD_CFG_RANK2_RD_ODT = 4529; // 8
+static const uint64_t SH_FLD_CFG_RANK2_RD_ODT_LEN = 4530; // 8
+static const uint64_t SH_FLD_CFG_RANK2_WR_ODT = 4531; // 8
+static const uint64_t SH_FLD_CFG_RANK2_WR_ODT_LEN = 4532; // 8
+static const uint64_t SH_FLD_CFG_RANK3_RD_ODT = 4533; // 8
+static const uint64_t SH_FLD_CFG_RANK3_RD_ODT_LEN = 4534; // 8
+static const uint64_t SH_FLD_CFG_RANK3_WR_ODT = 4535; // 8
+static const uint64_t SH_FLD_CFG_RANK3_WR_ODT_LEN = 4536; // 8
+static const uint64_t SH_FLD_CFG_RANK4_RD_ODT = 4537; // 8
+static const uint64_t SH_FLD_CFG_RANK4_RD_ODT_LEN = 4538; // 8
+static const uint64_t SH_FLD_CFG_RANK4_WR_ODT = 4539; // 8
+static const uint64_t SH_FLD_CFG_RANK4_WR_ODT_LEN = 4540; // 8
+static const uint64_t SH_FLD_CFG_RANK5_RD_ODT = 4541; // 8
+static const uint64_t SH_FLD_CFG_RANK5_RD_ODT_LEN = 4542; // 8
+static const uint64_t SH_FLD_CFG_RANK5_WR_ODT = 4543; // 8
+static const uint64_t SH_FLD_CFG_RANK5_WR_ODT_LEN = 4544; // 8
+static const uint64_t SH_FLD_CFG_RANK6_RD_ODT = 4545; // 8
+static const uint64_t SH_FLD_CFG_RANK6_RD_ODT_LEN = 4546; // 8
+static const uint64_t SH_FLD_CFG_RANK6_WR_ODT = 4547; // 8
+static const uint64_t SH_FLD_CFG_RANK6_WR_ODT_LEN = 4548; // 8
+static const uint64_t SH_FLD_CFG_RANK7_RD_ODT = 4549; // 8
+static const uint64_t SH_FLD_CFG_RANK7_RD_ODT_LEN = 4550; // 8
+static const uint64_t SH_FLD_CFG_RANK7_WR_ODT = 4551; // 8
+static const uint64_t SH_FLD_CFG_RANK7_WR_ODT_LEN = 4552; // 8
+static const uint64_t SH_FLD_CFG_RANK_SM_STALL_DISABLE = 4553; // 8
+static const uint64_t SH_FLD_CFG_RCD_PARITY_DLY = 4554; // 8
+static const uint64_t SH_FLD_CFG_RCD_PARITY_DLY_LEN = 4555; // 8
+static const uint64_t SH_FLD_CFG_RCD_PROTECTION_TIME = 4556; // 8
+static const uint64_t SH_FLD_CFG_RCD_PROTECTION_TIME_LEN = 4557; // 8
+static const uint64_t SH_FLD_CFG_RC_FRC_DISP_EQ_NTM_INIG_SI_TO_RCR_EN = 4558; // 12
+static const uint64_t SH_FLD_CFG_RD2PRE = 4559; // 8
+static const uint64_t SH_FLD_CFG_RD2PRE_LEN = 4560; // 8
+static const uint64_t SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT = 4561; // 8
+static const uint64_t SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT_LEN = 4562; // 8
+static const uint64_t SH_FLD_CFG_RDCLK_SYSCLK_LENGTH = 4563; // 8
+static const uint64_t SH_FLD_CFG_RDCLK_SYSCLK_LENGTH_LEN = 4564; // 8
+static const uint64_t SH_FLD_CFG_RDCLK_SYSCLK_TB = 4565; // 8
+static const uint64_t SH_FLD_CFG_RDCLK_SYSCLK_TB_LEN = 4566; // 8
+static const uint64_t SH_FLD_CFG_RDTAG_DLY = 4567; // 8
+static const uint64_t SH_FLD_CFG_RDTAG_DLY_LEN = 4568; // 8
+static const uint64_t SH_FLD_CFG_RDTAG_MBX_CYCLE = 4569; // 8
+static const uint64_t SH_FLD_CFG_RD_IDLE_ALLOW_WR = 4570; // 8
+static const uint64_t SH_FLD_CFG_RD_IDLE_ALLOW_WR_LEN = 4571; // 8
+static const uint64_t SH_FLD_CFG_REFRESH_DEBUG_SELECT = 4572; // 8
+static const uint64_t SH_FLD_CFG_REFRESH_ENABLE = 4573; // 8
+static const uint64_t SH_FLD_CFG_REFRESH_HP_RANK_BLOCK_ENABLE = 4574; // 8
+static const uint64_t SH_FLD_CFG_REFRESH_INTERVAL = 4575; // 8
+static const uint64_t SH_FLD_CFG_REFRESH_INTERVAL_LEN = 4576; // 8
+static const uint64_t SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT = 4577; // 8
+static const uint64_t SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN = 4578; // 8
+static const uint64_t SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD = 4579; // 8
+static const uint64_t SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD_LEN = 4580; // 8
+static const uint64_t SH_FLD_CFG_REFRESH_RESET_INTERVAL = 4581; // 8
+static const uint64_t SH_FLD_CFG_REFRESH_RESET_INTERVAL_LEN = 4582; // 8
+static const uint64_t SH_FLD_CFG_REFR_CHECK_INTERVAL = 4583; // 8
+static const uint64_t SH_FLD_CFG_REFR_CHECK_INTERVAL_LEN = 4584; // 8
+static const uint64_t SH_FLD_CFG_REFR_TSV_STACK = 4585; // 8
+static const uint64_t SH_FLD_CFG_REFR_TSV_STACK_LEN = 4586; // 8
+static const uint64_t SH_FLD_CFG_REF_BLOCK_STOP_DLY = 4587; // 8
+static const uint64_t SH_FLD_CFG_REF_BLOCK_STOP_DLY_LEN = 4588; // 8
+static const uint64_t SH_FLD_CFG_REG_PARITY_ERRHOLD = 4589; // 2
+static const uint64_t SH_FLD_CFG_REQ_GATHER_ENABLE = 4590; // 3
+static const uint64_t SH_FLD_CFG_RESET_CNTS_START_OF_RANK = 4591; // 2
+static const uint64_t SH_FLD_CFG_RESET_ERROR_CAPTURE = 4592; // 1
+static const uint64_t SH_FLD_CFG_RESET_MODE = 4593; // 2
+static const uint64_t SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT = 4594; // 8
+static const uint64_t SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT_LEN = 4595; // 8
+static const uint64_t SH_FLD_CFG_RNS_LVL0 = 4596; // 2
+static const uint64_t SH_FLD_CFG_RNS_LVL0_LEN = 4597; // 2
+static const uint64_t SH_FLD_CFG_RNS_LVL1 = 4598; // 2
+static const uint64_t SH_FLD_CFG_RNS_LVL1_LEN = 4599; // 2
+static const uint64_t SH_FLD_CFG_RNS_LVL2 = 4600; // 2
+static const uint64_t SH_FLD_CFG_RNS_LVL2_LEN = 4601; // 2
+static const uint64_t SH_FLD_CFG_RNS_LVL3 = 4602; // 2
+static const uint64_t SH_FLD_CFG_RNS_LVL3_LEN = 4603; // 2
+static const uint64_t SH_FLD_CFG_RNS_LVL4 = 4604; // 2
+static const uint64_t SH_FLD_CFG_RNS_LVL4_LEN = 4605; // 2
+static const uint64_t SH_FLD_CFG_RNS_LVL5 = 4606; // 2
+static const uint64_t SH_FLD_CFG_RNS_LVL5_LEN = 4607; // 2
+static const uint64_t SH_FLD_CFG_RNS_LVL6 = 4608; // 2
+static const uint64_t SH_FLD_CFG_RNS_LVL6_LEN = 4609; // 2
+static const uint64_t SH_FLD_CFG_RNS_LVL7 = 4610; // 2
+static const uint64_t SH_FLD_CFG_RNS_LVL7_LEN = 4611; // 2
+static const uint64_t SH_FLD_CFG_RODT_BC4_END_DLY = 4612; // 8
+static const uint64_t SH_FLD_CFG_RODT_BC4_END_DLY_LEN = 4613; // 8
+static const uint64_t SH_FLD_CFG_RODT_END_DLY = 4614; // 8
+static const uint64_t SH_FLD_CFG_RODT_END_DLY_LEN = 4615; // 8
+static const uint64_t SH_FLD_CFG_RODT_START_DLY = 4616; // 8
+static const uint64_t SH_FLD_CFG_RODT_START_DLY_LEN = 4617; // 8
+static const uint64_t SH_FLD_CFG_RQ_HANG_THRESHOLD = 4618; // 8
+static const uint64_t SH_FLD_CFG_RQ_HANG_THRESHOLD_LEN = 4619; // 8
+static const uint64_t SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING = 4620; // 8
+static const uint64_t SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING_LEN = 4621; // 8
+static const uint64_t SH_FLD_CFG_RRQ_DEPTH = 4622; // 8
+static const uint64_t SH_FLD_CFG_RRQ_DEPTH_LEN = 4623; // 8
+static const uint64_t SH_FLD_CFG_RRQ_ENTRY0_ENABLE = 4624; // 8
+static const uint64_t SH_FLD_CFG_RRQ_FIFO_MODE = 4625; // 8
+static const uint64_t SH_FLD_CFG_RRQ_SINGLE_THREAD_MODE = 4626; // 8
+static const uint64_t SH_FLD_CFG_RRQ_SKIP_LIMIT = 4627; // 8
+static const uint64_t SH_FLD_CFG_RRQ_SKIP_LIMIT_LEN = 4628; // 8
+static const uint64_t SH_FLD_CFG_RSV0 = 4629; // 8
+static const uint64_t SH_FLD_CFG_RSV0_LEN = 4630; // 8
+static const uint64_t SH_FLD_CFG_RUNTIME_CTR = 4631; // 2
+static const uint64_t SH_FLD_CFG_RUNTIME_CTR_LEN = 4632; // 2
+static const uint64_t SH_FLD_CFG_RUNTIME_MCBALL = 4633; // 2
+static const uint64_t SH_FLD_CFG_RUNTIME_OVERHEAD = 4634; // 2
+static const uint64_t SH_FLD_CFG_RUNTIME_SUBTEST = 4635; // 2
+static const uint64_t SH_FLD_CFG_RUNTIME_SUBTEST_LEN = 4636; // 2
+static const uint64_t SH_FLD_CFG_SAFE_REFRESH_INTERVAL = 4637; // 8
+static const uint64_t SH_FLD_CFG_SAFE_REFRESH_INTERVAL_LEN = 4638; // 8
+static const uint64_t SH_FLD_CFG_SCOPE = 4639; // 2
+static const uint64_t SH_FLD_CFG_SCOPE_LEN = 4640; // 2
+static const uint64_t SH_FLD_CFG_SELCR0 = 4641; // 1
+static const uint64_t SH_FLD_CFG_SELCR0_LEN = 4642; // 1
+static const uint64_t SH_FLD_CFG_SELCR1 = 4643; // 1
+static const uint64_t SH_FLD_CFG_SELCR1_LEN = 4644; // 1
+static const uint64_t SH_FLD_CFG_SELCR2 = 4645; // 1
+static const uint64_t SH_FLD_CFG_SELCR2_LEN = 4646; // 1
+static const uint64_t SH_FLD_CFG_SELCR3 = 4647; // 1
+static const uint64_t SH_FLD_CFG_SELCR3_LEN = 4648; // 1
+static const uint64_t SH_FLD_CFG_SELECT = 4649; // 3
+static const uint64_t SH_FLD_CFG_SELECT_LEN = 4650; // 3
+static const uint64_t SH_FLD_CFG_SELRT = 4651; // 1
+static const uint64_t SH_FLD_CFG_SELRT_LEN = 4652; // 1
+static const uint64_t SH_FLD_CFG_SELSN0 = 4653; // 1
+static const uint64_t SH_FLD_CFG_SELSN0_LEN = 4654; // 1
+static const uint64_t SH_FLD_CFG_SELSN1 = 4655; // 1
+static const uint64_t SH_FLD_CFG_SELSN1_LEN = 4656; // 1
+static const uint64_t SH_FLD_CFG_SELSN2 = 4657; // 1
+static const uint64_t SH_FLD_CFG_SELSN2_LEN = 4658; // 1
+static const uint64_t SH_FLD_CFG_SELSN3 = 4659; // 1
+static const uint64_t SH_FLD_CFG_SELSN3_LEN = 4660; // 1
+static const uint64_t SH_FLD_CFG_SHIFT_COUNT = 4661; // 3
+static const uint64_t SH_FLD_CFG_SHIFT_COUNT_LEN = 4662; // 3
+static const uint64_t SH_FLD_CFG_SHIFT_DATA = 4663; // 3
+static const uint64_t SH_FLD_CFG_SHIFT_DATA_LEN = 4664; // 3
+static const uint64_t SH_FLD_CFG_SIM_FAST_NOISE_WINDOW = 4665; // 8
+static const uint64_t SH_FLD_CFG_SINGLE_MEM = 4666; // 12
+static const uint64_t SH_FLD_CFG_SINGLE_MEM_EN = 4667; // 12
+static const uint64_t SH_FLD_CFG_SINGLE_MEM_LEN = 4668; // 12
+static const uint64_t SH_FLD_CFG_SLOT0_S0_CID = 4669; // 8
+static const uint64_t SH_FLD_CFG_SLOT0_S0_CID_LEN = 4670; // 8
+static const uint64_t SH_FLD_CFG_SLOT0_S1_CID = 4671; // 8
+static const uint64_t SH_FLD_CFG_SLOT0_S1_CID_LEN = 4672; // 8
+static const uint64_t SH_FLD_CFG_SLOT0_S2_CID = 4673; // 8
+static const uint64_t SH_FLD_CFG_SLOT0_S2_CID_LEN = 4674; // 8
+static const uint64_t SH_FLD_CFG_SLOT0_S3_CID = 4675; // 8
+static const uint64_t SH_FLD_CFG_SLOT0_S3_CID_LEN = 4676; // 8
+static const uint64_t SH_FLD_CFG_SLOT0_S4_CID = 4677; // 8
+static const uint64_t SH_FLD_CFG_SLOT0_S4_CID_LEN = 4678; // 8
+static const uint64_t SH_FLD_CFG_SLOT0_S5_CID = 4679; // 8
+static const uint64_t SH_FLD_CFG_SLOT0_S5_CID_LEN = 4680; // 8
+static const uint64_t SH_FLD_CFG_SLOT0_S6_CID = 4681; // 8
+static const uint64_t SH_FLD_CFG_SLOT0_S6_CID_LEN = 4682; // 8
+static const uint64_t SH_FLD_CFG_SLOT0_S7_CID = 4683; // 8
+static const uint64_t SH_FLD_CFG_SLOT0_S7_CID_LEN = 4684; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S0_CID = 4685; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S0_CID_LEN = 4686; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S1_CID = 4687; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S1_CID_LEN = 4688; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S2_CID = 4689; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S2_CID_LEN = 4690; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S3_CID = 4691; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S3_CID_LEN = 4692; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S4_CID = 4693; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S4_CID_LEN = 4694; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S5_CID = 4695; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S5_CID_LEN = 4696; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S6_CID = 4697; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S6_CID_LEN = 4698; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S7_CID = 4699; // 8
+static const uint64_t SH_FLD_CFG_SLOT1_S7_CID_LEN = 4700; // 8
+static const uint64_t SH_FLD_CFG_SLOW = 4701; // 3
+static const uint64_t SH_FLD_CFG_SMP_OPTICS = 4702; // 6
+static const uint64_t SH_FLD_CFG_SMT_MODE = 4703; // 1
+static const uint64_t SH_FLD_CFG_SMT_MODE_LEN = 4704; // 1
+static const uint64_t SH_FLD_CFG_SP_HW_MARK = 4705; // 3
+static const uint64_t SH_FLD_CFG_SP_HW_MARK_LEN = 4706; // 3
+static const uint64_t SH_FLD_CFG_STALL_PULL = 4707; // 1
+static const uint64_t SH_FLD_CFG_STALL_PUSH_ARX = 4708; // 1
+static const uint64_t SH_FLD_CFG_STALL_PUSH_LCL = 4709; // 1
+static const uint64_t SH_FLD_CFG_START_ADDR_0 = 4710; // 2
+static const uint64_t SH_FLD_CFG_START_ADDR_0_LEN = 4711; // 2
+static const uint64_t SH_FLD_CFG_START_ADDR_1 = 4712; // 2
+static const uint64_t SH_FLD_CFG_START_ADDR_1_LEN = 4713; // 2
+static const uint64_t SH_FLD_CFG_START_ADDR_2 = 4714; // 2
+static const uint64_t SH_FLD_CFG_START_ADDR_2_LEN = 4715; // 2
+static const uint64_t SH_FLD_CFG_START_ADDR_3 = 4716; // 2
+static const uint64_t SH_FLD_CFG_START_ADDR_3_LEN = 4717; // 2
+static const uint64_t SH_FLD_CFG_STATIC_IDLE_DLY = 4718; // 8
+static const uint64_t SH_FLD_CFG_STATIC_IDLE_DLY_LEN = 4719; // 8
+static const uint64_t SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP = 4720; // 43
+static const uint64_t SH_FLD_CFG_STQ_PF_EN = 4721; // 12
+static const uint64_t SH_FLD_CFG_STR_ENABLE = 4722; // 8
+static const uint64_t SH_FLD_CFG_STR_STATE = 4723; // 8
+static const uint64_t SH_FLD_CFG_SWITCH_CD_PULSE = 4724; // 3
+static const uint64_t SH_FLD_CFG_SWITCH_OPTION_AB = 4725; // 3
+static const uint64_t SH_FLD_CFG_SW_AB_WAIT = 4726; // 3
+static const uint64_t SH_FLD_CFG_SW_AB_WAIT_LEN = 4727; // 3
+static const uint64_t SH_FLD_CFG_SYMBOL_COUNTER_MODE = 4728; // 2
+static const uint64_t SH_FLD_CFG_SYMBOL_COUNTER_MODE_LEN = 4729; // 2
+static const uint64_t SH_FLD_CFG_SYSMAP_SM_NOT_LG_SEL = 4730; // 12
+static const uint64_t SH_FLD_CFG_TCKESR = 4731; // 8
+static const uint64_t SH_FLD_CFG_TCKESR_LEN = 4732; // 8
+static const uint64_t SH_FLD_CFG_TCKSRE = 4733; // 8
+static const uint64_t SH_FLD_CFG_TCKSRE_LEN = 4734; // 8
+static const uint64_t SH_FLD_CFG_TCKSRX = 4735; // 8
+static const uint64_t SH_FLD_CFG_TCKSRX_LEN = 4736; // 8
+static const uint64_t SH_FLD_CFG_TFAW = 4737; // 8
+static const uint64_t SH_FLD_CFG_TFAW_LEN = 4738; // 8
+static const uint64_t SH_FLD_CFG_THRD_C0_EN = 4739; // 1
+static const uint64_t SH_FLD_CFG_THRD_C0_EN_LEN = 4740; // 1
+static const uint64_t SH_FLD_CFG_THRD_C10_EN = 4741; // 1
+static const uint64_t SH_FLD_CFG_THRD_C10_EN_LEN = 4742; // 1
+static const uint64_t SH_FLD_CFG_THRD_C11_EN = 4743; // 1
+static const uint64_t SH_FLD_CFG_THRD_C11_EN_LEN = 4744; // 1
+static const uint64_t SH_FLD_CFG_THRD_C1_EN = 4745; // 1
+static const uint64_t SH_FLD_CFG_THRD_C1_EN_LEN = 4746; // 1
+static const uint64_t SH_FLD_CFG_THRD_C2_EN = 4747; // 1
+static const uint64_t SH_FLD_CFG_THRD_C2_EN_LEN = 4748; // 1
+static const uint64_t SH_FLD_CFG_THRD_C3_EN = 4749; // 1
+static const uint64_t SH_FLD_CFG_THRD_C3_EN_LEN = 4750; // 1
+static const uint64_t SH_FLD_CFG_THRD_C4_EN = 4751; // 1
+static const uint64_t SH_FLD_CFG_THRD_C4_EN_LEN = 4752; // 1
+static const uint64_t SH_FLD_CFG_THRD_C5_EN = 4753; // 1
+static const uint64_t SH_FLD_CFG_THRD_C5_EN_LEN = 4754; // 1
+static const uint64_t SH_FLD_CFG_THRD_C6_EN = 4755; // 1
+static const uint64_t SH_FLD_CFG_THRD_C6_EN_LEN = 4756; // 1
+static const uint64_t SH_FLD_CFG_THRD_C7_EN = 4757; // 1
+static const uint64_t SH_FLD_CFG_THRD_C7_EN_LEN = 4758; // 1
+static const uint64_t SH_FLD_CFG_THRD_C8_EN = 4759; // 1
+static const uint64_t SH_FLD_CFG_THRD_C8_EN_LEN = 4760; // 1
+static const uint64_t SH_FLD_CFG_THRD_C9_EN = 4761; // 1
+static const uint64_t SH_FLD_CFG_THRD_C9_EN_LEN = 4762; // 1
+static const uint64_t SH_FLD_CFG_THRESH_MAG_ICE = 4763; // 2
+static const uint64_t SH_FLD_CFG_THRESH_MAG_ICE_LEN = 4764; // 2
+static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_HARD = 4765; // 2
+static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_HARD_LEN = 4766; // 2
+static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_INT = 4767; // 2
+static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_INT_LEN = 4768; // 2
+static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_SOFT = 4769; // 2
+static const uint64_t SH_FLD_CFG_THRESH_MAG_MCE_SOFT_LEN = 4770; // 2
+static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_HARD = 4771; // 2
+static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_HARD_LEN = 4772; // 2
+static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_INT = 4773; // 2
+static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_INT_LEN = 4774; // 2
+static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_SOFT = 4775; // 2
+static const uint64_t SH_FLD_CFG_THRESH_MAG_NCE_SOFT_LEN = 4776; // 2
+static const uint64_t SH_FLD_CFG_THRESH_MAG_RCE = 4777; // 2
+static const uint64_t SH_FLD_CFG_THRESH_MAG_RCE_LEN = 4778; // 2
+static const uint64_t SH_FLD_CFG_TIME_BASE_TMR0 = 4779; // 8
+static const uint64_t SH_FLD_CFG_TIME_BASE_TMR0_LEN = 4780; // 8
+static const uint64_t SH_FLD_CFG_TIME_BASE_TMR1 = 4781; // 8
+static const uint64_t SH_FLD_CFG_TIME_BASE_TMR1_LEN = 4782; // 8
+static const uint64_t SH_FLD_CFG_TIME_BASE_TMR2 = 4783; // 8
+static const uint64_t SH_FLD_CFG_TIME_BASE_TMR2_LEN = 4784; // 8
+static const uint64_t SH_FLD_CFG_TM_MASTER = 4785; // 6
+static const uint64_t SH_FLD_CFG_TRAS = 4786; // 8
+static const uint64_t SH_FLD_CFG_TRAS_LEN = 4787; // 8
+static const uint64_t SH_FLD_CFG_TRCD = 4788; // 8
+static const uint64_t SH_FLD_CFG_TRCD_LEN = 4789; // 8
+static const uint64_t SH_FLD_CFG_TRFC = 4790; // 8
+static const uint64_t SH_FLD_CFG_TRFC_COUNTER_DIS = 4791; // 8
+static const uint64_t SH_FLD_CFG_TRFC_COUNTER_DIS_LEN = 4792; // 8
+static const uint64_t SH_FLD_CFG_TRFC_LEN = 4793; // 8
+static const uint64_t SH_FLD_CFG_TRFC_STACK_GATE_ALL_REF = 4794; // 8
+static const uint64_t SH_FLD_CFG_TRP = 4795; // 8
+static const uint64_t SH_FLD_CFG_TRP_LEN = 4796; // 8
+static const uint64_t SH_FLD_CFG_TSIZE = 4797; // 2
+static const uint64_t SH_FLD_CFG_TSIZE_LEN = 4798; // 2
+static const uint64_t SH_FLD_CFG_TSIZE_MASK = 4799; // 2
+static const uint64_t SH_FLD_CFG_TSIZE_MASK_LEN = 4800; // 2
+static const uint64_t SH_FLD_CFG_TTAG = 4801; // 2
+static const uint64_t SH_FLD_CFG_TTAG_LEN = 4802; // 2
+static const uint64_t SH_FLD_CFG_TTAG_MASK = 4803; // 2
+static const uint64_t SH_FLD_CFG_TTAG_MASK_LEN = 4804; // 2
+static const uint64_t SH_FLD_CFG_TTYPE = 4805; // 2
+static const uint64_t SH_FLD_CFG_TTYPE_LEN = 4806; // 2
+static const uint64_t SH_FLD_CFG_TTYPE_MASK = 4807; // 2
+static const uint64_t SH_FLD_CFG_TTYPE_MASK_LEN = 4808; // 2
+static const uint64_t SH_FLD_CFG_TXSDLL = 4809; // 8
+static const uint64_t SH_FLD_CFG_TXSDLL_LEN = 4810; // 8
+static const uint64_t SH_FLD_CFG_VAS_MASK = 4811; // 1
+static const uint64_t SH_FLD_CFG_VG_LVL0 = 4812; // 2
+static const uint64_t SH_FLD_CFG_VG_LVL0_LEN = 4813; // 2
+static const uint64_t SH_FLD_CFG_VG_LVL1 = 4814; // 2
+static const uint64_t SH_FLD_CFG_VG_LVL1_LEN = 4815; // 2
+static const uint64_t SH_FLD_CFG_VG_LVL2 = 4816; // 2
+static const uint64_t SH_FLD_CFG_VG_LVL2_LEN = 4817; // 2
+static const uint64_t SH_FLD_CFG_VG_LVL3 = 4818; // 2
+static const uint64_t SH_FLD_CFG_VG_LVL3_LEN = 4819; // 2
+static const uint64_t SH_FLD_CFG_VG_LVL4 = 4820; // 2
+static const uint64_t SH_FLD_CFG_VG_LVL4_LEN = 4821; // 2
+static const uint64_t SH_FLD_CFG_VG_LVL5 = 4822; // 2
+static const uint64_t SH_FLD_CFG_VG_LVL5_LEN = 4823; // 2
+static const uint64_t SH_FLD_CFG_VG_LVL6 = 4824; // 2
+static const uint64_t SH_FLD_CFG_VG_LVL6_LEN = 4825; // 2
+static const uint64_t SH_FLD_CFG_VG_LVL7 = 4826; // 2
+static const uint64_t SH_FLD_CFG_VG_LVL7_LEN = 4827; // 2
+static const uint64_t SH_FLD_CFG_WAT_ACT_FRC_TB_PULSE_PULSE = 4828; // 2
+static const uint64_t SH_FLD_CFG_WAT_ACT_FRC_TB_PULSE_PULSE_LEN = 4829; // 2
+static const uint64_t SH_FLD_CFG_WAT_ACT_MNT_GO_IDLE_PULSE = 4830; // 2
+static const uint64_t SH_FLD_CFG_WAT_ACT_MNT_GO_IDLE_PULSE_LEN = 4831; // 2
+static const uint64_t SH_FLD_CFG_WAT_ACT_SET_SPATTN_PULSE = 4832; // 2
+static const uint64_t SH_FLD_CFG_WAT_ACT_SET_SPATTN_PULSE_LEN = 4833; // 2
+static const uint64_t SH_FLD_CFG_WAT_CAL_SYNC = 4834; // 8
+static const uint64_t SH_FLD_CFG_WAT_CAL_SYNC_LEN = 4835; // 8
+static const uint64_t SH_FLD_CFG_WAT_CNTL = 4836; // 8
+static const uint64_t SH_FLD_CFG_WAT_CNTL_LEN = 4837; // 8
+static const uint64_t SH_FLD_CFG_WAT_CNT_VALUE = 4838; // 2
+static const uint64_t SH_FLD_CFG_WAT_CNT_VALUE_LEN = 4839; // 2
+static const uint64_t SH_FLD_CFG_WAT_DIS_RD_PG = 4840; // 8
+static const uint64_t SH_FLD_CFG_WAT_DIS_RD_PG_LEN = 4841; // 8
+static const uint64_t SH_FLD_CFG_WAT_DIS_WR_PG = 4842; // 8
+static const uint64_t SH_FLD_CFG_WAT_DIS_WR_PG_LEN = 4843; // 8
+static const uint64_t SH_FLD_CFG_WAT_EMER_TH = 4844; // 8
+static const uint64_t SH_FLD_CFG_WAT_EMER_TH_LEN = 4845; // 8
+static const uint64_t SH_FLD_CFG_WAT_ENABLE = 4846; // 2
+static const uint64_t SH_FLD_CFG_WAT_EVENT_SEL = 4847; // 8
+static const uint64_t SH_FLD_CFG_WAT_EVENT_SEL_LEN = 4848; // 8
+static const uint64_t SH_FLD_CFG_WAT_EXIT_STR = 4849; // 8
+static const uint64_t SH_FLD_CFG_WAT_EXIT_STR_LEN = 4850; // 8
+static const uint64_t SH_FLD_CFG_WAT_EXT_ARM_SEL = 4851; // 2
+static const uint64_t SH_FLD_CFG_WAT_EXT_ARM_SEL_LEN = 4852; // 2
+static const uint64_t SH_FLD_CFG_WAT_EXT_EVENT_TO_INT = 4853; // 2
+static const uint64_t SH_FLD_CFG_WAT_EXT_EVENT_TO_INT_LEN = 4854; // 2
+static const uint64_t SH_FLD_CFG_WAT_EXT_RESET_SEL = 4855; // 2
+static const uint64_t SH_FLD_CFG_WAT_EXT_RESET_SEL_LEN = 4856; // 2
+static const uint64_t SH_FLD_CFG_WAT_EXT_TRIGGER_SEL = 4857; // 2
+static const uint64_t SH_FLD_CFG_WAT_EXT_TRIGGER_SEL_LEN = 4858; // 2
+static const uint64_t SH_FLD_CFG_WAT_FARB_CAL_GT = 4859; // 8
+static const uint64_t SH_FLD_CFG_WAT_FARB_CAL_GT_LEN = 4860; // 8
+static const uint64_t SH_FLD_CFG_WAT_FARB_REF_GT = 4861; // 8
+static const uint64_t SH_FLD_CFG_WAT_FARB_REF_GT_LEN = 4862; // 8
+static const uint64_t SH_FLD_CFG_WAT_FARB_RRQ_GT = 4863; // 8
+static const uint64_t SH_FLD_CFG_WAT_FARB_RRQ_GT_LEN = 4864; // 8
+static const uint64_t SH_FLD_CFG_WAT_FARB_WRQ_GT = 4865; // 8
+static const uint64_t SH_FLD_CFG_WAT_FARB_WRQ_GT_LEN = 4866; // 8
+static const uint64_t SH_FLD_CFG_WAT_FORCE_RD_ENTRY0_HP = 4867; // 8
+static const uint64_t SH_FLD_CFG_WAT_FORCE_RD_ENTRY0_HP_LEN = 4868; // 8
+static const uint64_t SH_FLD_CFG_WAT_FORCE_WR_ENTRY0_HP = 4869; // 8
+static const uint64_t SH_FLD_CFG_WAT_FORCE_WR_ENTRY0_HP_LEN = 4870; // 8
+static const uint64_t SH_FLD_CFG_WAT_FP_DIS = 4871; // 8
+static const uint64_t SH_FLD_CFG_WAT_FP_DIS_LEN = 4872; // 8
+static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT0_SEL = 4873; // 2
+static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT0_SEL_LEN = 4874; // 2
+static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT1_SEL = 4875; // 2
+static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT1_SEL_LEN = 4876; // 2
+static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT2_SEL = 4877; // 2
+static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT2_SEL_LEN = 4878; // 2
+static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT3_SEL = 4879; // 2
+static const uint64_t SH_FLD_CFG_WAT_GLOB_EVENT3_SEL_LEN = 4880; // 2
+static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT0_SEL = 4881; // 2
+static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT0_SEL_LEN = 4882; // 2
+static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT1_SEL = 4883; // 2
+static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT1_SEL_LEN = 4884; // 2
+static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT2_SEL = 4885; // 2
+static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT2_SEL_LEN = 4886; // 2
+static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT3_SEL = 4887; // 2
+static const uint64_t SH_FLD_CFG_WAT_LOC_EVENT3_SEL_LEN = 4888; // 2
+static const uint64_t SH_FLD_CFG_WAT_MSKA = 4889; // 8
+static const uint64_t SH_FLD_CFG_WAT_MSKA_LEN = 4890; // 8
+static const uint64_t SH_FLD_CFG_WAT_MSKB = 4891; // 8
+static const uint64_t SH_FLD_CFG_WAT_MSKB_LEN = 4892; // 8
+static const uint64_t SH_FLD_CFG_WAT_OUTPUT_PULSE = 4893; // 2
+static const uint64_t SH_FLD_CFG_WAT_PATA = 4894; // 8
+static const uint64_t SH_FLD_CFG_WAT_PATA_LEN = 4895; // 8
+static const uint64_t SH_FLD_CFG_WAT_PATB = 4896; // 8
+static const uint64_t SH_FLD_CFG_WAT_PATB_LEN = 4897; // 8
+static const uint64_t SH_FLD_CFG_WAT_PUP_ALL = 4898; // 8
+static const uint64_t SH_FLD_CFG_WAT_PUP_ALL_LEN = 4899; // 8
+static const uint64_t SH_FLD_CFG_WAT_REF_HP = 4900; // 8
+static const uint64_t SH_FLD_CFG_WAT_REF_HP_LEN = 4901; // 8
+static const uint64_t SH_FLD_CFG_WAT_REF_SAFE = 4902; // 8
+static const uint64_t SH_FLD_CFG_WAT_REF_SAFE_LEN = 4903; // 8
+static const uint64_t SH_FLD_CFG_WAT_REF_SYNC = 4904; // 8
+static const uint64_t SH_FLD_CFG_WAT_REF_SYNC_LEN = 4905; // 8
+static const uint64_t SH_FLD_CFG_WAT_RRQ_MNT_GT = 4906; // 8
+static const uint64_t SH_FLD_CFG_WAT_RRQ_MNT_GT_LEN = 4907; // 8
+static const uint64_t SH_FLD_CFG_WAT_SET_FIR = 4908; // 8
+static const uint64_t SH_FLD_CFG_WAT_SET_FIR_LEN = 4909; // 8
+static const uint64_t SH_FLD_CFG_WAT_START_RECOVERY = 4910; // 8
+static const uint64_t SH_FLD_CFG_WAT_START_RECOVERY_LEN = 4911; // 8
+static const uint64_t SH_FLD_CFG_WAT_TMR_VALUE = 4912; // 2
+static const uint64_t SH_FLD_CFG_WAT_TMR_VALUE_LEN = 4913; // 2
+static const uint64_t SH_FLD_CFG_WAT_WRQ_MNT_GT = 4914; // 8
+static const uint64_t SH_FLD_CFG_WAT_WRQ_MNT_GT_LEN = 4915; // 8
+static const uint64_t SH_FLD_CFG_WDF_SERIAL_SEQ_MODE = 4916; // 8
+static const uint64_t SH_FLD_CFG_WODT_BC4_END_DLY = 4917; // 8
+static const uint64_t SH_FLD_CFG_WODT_BC4_END_DLY_LEN = 4918; // 8
+static const uint64_t SH_FLD_CFG_WODT_END_DLY = 4919; // 8
+static const uint64_t SH_FLD_CFG_WODT_END_DLY_LEN = 4920; // 8
+static const uint64_t SH_FLD_CFG_WODT_START_DLY = 4921; // 8
+static const uint64_t SH_FLD_CFG_WODT_START_DLY_LEN = 4922; // 8
+static const uint64_t SH_FLD_CFG_WR2PRE = 4923; // 8
+static const uint64_t SH_FLD_CFG_WR2PRE_LEN = 4924; // 8
+static const uint64_t SH_FLD_CFG_WRDATA_DLY = 4925; // 8
+static const uint64_t SH_FLD_CFG_WRDATA_DLY_LEN = 4926; // 8
+static const uint64_t SH_FLD_CFG_WRDONE_DLY = 4927; // 8
+static const uint64_t SH_FLD_CFG_WRDONE_DLY_LEN = 4928; // 8
+static const uint64_t SH_FLD_CFG_WRITE_CA_OR_UR_RESPONSE = 4929; // 6
+static const uint64_t SH_FLD_CFG_WRITE_HW_MARK = 4930; // 8
+static const uint64_t SH_FLD_CFG_WRITE_HW_MARK_LEN = 4931; // 8
+static const uint64_t SH_FLD_CFG_WRITE_LW_MARK = 4932; // 8
+static const uint64_t SH_FLD_CFG_WRITE_LW_MARK_LEN = 4933; // 8
+static const uint64_t SH_FLD_CFG_WRITE_MODE_ECC_CHK_DIS = 4934; // 16
+static const uint64_t SH_FLD_CFG_WRITE_MODE_ECC_COR_DIS = 4935; // 16
+static const uint64_t SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING = 4936; // 8
+static const uint64_t SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN = 4937; // 8
+static const uint64_t SH_FLD_CFG_WRQ_DEPTH = 4938; // 8
+static const uint64_t SH_FLD_CFG_WRQ_DEPTH_LEN = 4939; // 8
+static const uint64_t SH_FLD_CFG_WRQ_ENABLE_NON_HP_WR = 4940; // 8
+static const uint64_t SH_FLD_CFG_WRQ_ENTRY0_HP_DLY = 4941; // 8
+static const uint64_t SH_FLD_CFG_WRQ_ENTRY0_HP_DLY_LEN = 4942; // 8
+static const uint64_t SH_FLD_CFG_WRQ_FIFO_MODE = 4943; // 8
+static const uint64_t SH_FLD_CFG_WRQ_FLUSH_WR_RANK = 4944; // 8
+static const uint64_t SH_FLD_CFG_WRQ_SINGLE_THREAD_MODE = 4945; // 8
+static const uint64_t SH_FLD_CFG_WRQ_SKIP_LIMIT = 4946; // 8
+static const uint64_t SH_FLD_CFG_WRQ_SKIP_LIMIT_LEN = 4947; // 8
+static const uint64_t SH_FLD_CFG_XLATE_ADDR_TO_ID = 4948; // 6
+static const uint64_t SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN = 4949; // 6
+static const uint64_t SH_FLD_CFG_X_AGGREGATE = 4950; // 6
+static const uint64_t SH_FLD_CFG_X_CMD_RATE = 4951; // 6
+static const uint64_t SH_FLD_CFG_X_CMD_RATE_LEN = 4952; // 6
+static const uint64_t SH_FLD_CFG_X_FP_DISABLED = 4953; // 6
+static const uint64_t SH_FLD_CFG_X_GATHER_ENABLE = 4954; // 6
+static const uint64_t SH_FLD_CFG_X_INDIRECT_EN = 4955; // 6
+static const uint64_t SH_FLD_CGC = 4956; // 24
+static const uint64_t SH_FLD_CGC_LEN = 4957; // 24
+static const uint64_t SH_FLD_CH0EFT_ACTION = 4958; // 1
+static const uint64_t SH_FLD_CH0EFT_ENA = 4959; // 1
+static const uint64_t SH_FLD_CH0EFT_SELECT = 4960; // 1
+static const uint64_t SH_FLD_CH0EFT_SELECT_LEN = 4961; // 1
+static const uint64_t SH_FLD_CH0EFT_TYPE = 4962; // 1
+static const uint64_t SH_FLD_CH0_842_ECC_CE = 4963; // 1
+static const uint64_t SH_FLD_CH0_842_ECC_UE = 4964; // 1
+static const uint64_t SH_FLD_CH0_CMD_CREDITS_0_5 = 4965; // 1
+static const uint64_t SH_FLD_CH0_CMD_CREDITS_0_5_LEN = 4966; // 1
+static const uint64_t SH_FLD_CH0_EFT = 4967; // 1
+static const uint64_t SH_FLD_CH0_INVALID_STATE = 4968; // 1
+static const uint64_t SH_FLD_CH0_MAX = 4969; // 2
+static const uint64_t SH_FLD_CH0_MAX_LEN = 4970; // 2
+static const uint64_t SH_FLD_CH0_REF_DIV = 4971; // 1
+static const uint64_t SH_FLD_CH0_REF_DIV_LEN = 4972; // 1
+static const uint64_t SH_FLD_CH0_TIMER_ENBL = 4973; // 1
+static const uint64_t SH_FLD_CH1EFT_ACTION = 4974; // 1
+static const uint64_t SH_FLD_CH1EFT_ENA = 4975; // 1
+static const uint64_t SH_FLD_CH1EFT_SELECT = 4976; // 1
+static const uint64_t SH_FLD_CH1EFT_SELECT_LEN = 4977; // 1
+static const uint64_t SH_FLD_CH1EFT_TYPE = 4978; // 1
+static const uint64_t SH_FLD_CH1_842_ECC_CE = 4979; // 1
+static const uint64_t SH_FLD_CH1_842_ECC_UE = 4980; // 1
+static const uint64_t SH_FLD_CH1_CMD_CREDITS_0_5 = 4981; // 1
+static const uint64_t SH_FLD_CH1_CMD_CREDITS_0_5_LEN = 4982; // 1
+static const uint64_t SH_FLD_CH1_DAT_CREDITS_0_5 = 4983; // 1
+static const uint64_t SH_FLD_CH1_DAT_CREDITS_0_5_LEN = 4984; // 1
+static const uint64_t SH_FLD_CH1_EFT = 4985; // 1
+static const uint64_t SH_FLD_CH1_INVALID_STATE = 4986; // 1
+static const uint64_t SH_FLD_CH1_MAX = 4987; // 2
+static const uint64_t SH_FLD_CH1_MAX_LEN = 4988; // 2
+static const uint64_t SH_FLD_CH1_REF_DIV = 4989; // 1
+static const uint64_t SH_FLD_CH1_REF_DIV_LEN = 4990; // 1
+static const uint64_t SH_FLD_CH1_TIMER_ENBL = 4991; // 1
+static const uint64_t SH_FLD_CH2_CMD_CREDITS_PC_0_5 = 4992; // 1
+static const uint64_t SH_FLD_CH2_CMD_CREDITS_PC_0_5_LEN = 4993; // 1
+static const uint64_t SH_FLD_CH2_CMD_CREDITS_VC_0_5 = 4994; // 1
+static const uint64_t SH_FLD_CH2_CMD_CREDITS_VC_0_5_LEN = 4995; // 1
+static const uint64_t SH_FLD_CH2_INVALID_STATE = 4996; // 1
+static const uint64_t SH_FLD_CH2_MAX = 4997; // 2
+static const uint64_t SH_FLD_CH2_MAX_LEN = 4998; // 2
+static const uint64_t SH_FLD_CH2_REF_DIV = 4999; // 1
+static const uint64_t SH_FLD_CH2_REF_DIV_LEN = 5000; // 1
+static const uint64_t SH_FLD_CH2_SYM = 5001; // 1
+static const uint64_t SH_FLD_CH2_TIMER_ENBL = 5002; // 1
+static const uint64_t SH_FLD_CH3_INVALID_STATE = 5003; // 1
+static const uint64_t SH_FLD_CH3_MAX = 5004; // 2
+static const uint64_t SH_FLD_CH3_MAX_LEN = 5005; // 2
+static const uint64_t SH_FLD_CH3_REF_DIV = 5006; // 1
+static const uint64_t SH_FLD_CH3_REF_DIV_LEN = 5007; // 1
+static const uint64_t SH_FLD_CH3_SYM = 5008; // 1
+static const uint64_t SH_FLD_CH3_TIMER_ENBL = 5009; // 1
+static const uint64_t SH_FLD_CH4GZIP_ACTION = 5010; // 1
+static const uint64_t SH_FLD_CH4GZIP_ENA = 5011; // 1
+static const uint64_t SH_FLD_CH4GZIP_SELECT = 5012; // 1
+static const uint64_t SH_FLD_CH4GZIP_SELECT_LEN = 5013; // 1
+static const uint64_t SH_FLD_CH4GZIP_TYPE = 5014; // 1
+static const uint64_t SH_FLD_CH4_AMF_ECC_CE = 5015; // 1
+static const uint64_t SH_FLD_CH4_AMF_ECC_UE = 5016; // 1
+static const uint64_t SH_FLD_CH4_GZIP = 5017; // 1
+static const uint64_t SH_FLD_CH4_INVALID_STATE = 5018; // 1
+static const uint64_t SH_FLD_CH4_REF_DIV = 5019; // 1
+static const uint64_t SH_FLD_CH4_REF_DIV_LEN = 5020; // 1
+static const uint64_t SH_FLD_CH4_TIMER_ENBL = 5021; // 1
+static const uint64_t SH_FLD_CH5_AMF_ECC_CE = 5022; // 1
+static const uint64_t SH_FLD_CH5_AMF_ECC_UE = 5023; // 1
+static const uint64_t SH_FLD_CH5_INVALID_STATE = 5024; // 1
+static const uint64_t SH_FLD_CH6_AMF_ECC_CE = 5025; // 1
+static const uint64_t SH_FLD_CH6_AMF_ECC_UE = 5026; // 1
+static const uint64_t SH_FLD_CH6_INVALID_STATE = 5027; // 1
+static const uint64_t SH_FLD_CH7_AMF_ECC_CE = 5028; // 1
+static const uint64_t SH_FLD_CH7_AMF_ECC_UE = 5029; // 1
+static const uint64_t SH_FLD_CH7_INVALID_STATE = 5030; // 1
+static const uint64_t SH_FLD_CHANGE_IN_PROGRESS = 5031; // 2
+static const uint64_t SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION = 5032; // 4
+static const uint64_t SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION_LEN = 5033; // 4
+static const uint64_t SH_FLD_CHANNEL_0_TIMEOUT_ERROR = 5034; // 4
+static const uint64_t SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION = 5035; // 4
+static const uint64_t SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION_LEN = 5036; // 4
+static const uint64_t SH_FLD_CHANNEL_1_TIMEOUT_ERROR = 5037; // 4
+static const uint64_t SH_FLD_CHANNEL_SELECT = 5038; // 4
+static const uint64_t SH_FLD_CHANNEL_SELECT_LEN = 5039; // 4
+static const uint64_t SH_FLD_CHAN_FAIL_MASK = 5040; // 4
+static const uint64_t SH_FLD_CHAN_FAIL_MASK_LEN = 5041; // 4
+static const uint64_t SH_FLD_CHECKSTOP = 5042; // 1
+static const uint64_t SH_FLD_CHECK_CMDS = 5043; // 2
+static const uint64_t SH_FLD_CHECK_CMDS_EN = 5044; // 2
+static const uint64_t SH_FLD_CHECK_CMDS_LEN = 5045; // 2
+static const uint64_t SH_FLD_CHECK_STOP_GPE0 = 5046; // 1
+static const uint64_t SH_FLD_CHECK_STOP_GPE1 = 5047; // 1
+static const uint64_t SH_FLD_CHECK_STOP_GPE2 = 5048; // 1
+static const uint64_t SH_FLD_CHECK_STOP_GPE3 = 5049; // 1
+static const uint64_t SH_FLD_CHECK_STOP_PPC405 = 5050; // 1
+static const uint64_t SH_FLD_CHGRATE = 5051; // 12
+static const uint64_t SH_FLD_CHICKEN_SWITCH = 5052; // 1
+static const uint64_t SH_FLD_CHIPLET_ATOMIC_LOCK = 5053; // 43
+static const uint64_t SH_FLD_CHIPLET_ENABLE = 5054; // 43
+static const uint64_t SH_FLD_CHIPLET_ERRORS = 5055; // 43
+static const uint64_t SH_FLD_CHIPLET_ERRORS_LEN = 5056; // 43
+static const uint64_t SH_FLD_CHIPLET_GRID_SKITTER = 5057; // 43
+static const uint64_t SH_FLD_CHIPLET_INTERRUPT_FROM_HOST = 5058; // 1
+static const uint64_t SH_FLD_CHIPLET_IS_ALIGNED = 5059; // 43
+static const uint64_t SH_FLD_CHIPLET_OFFLINE = 5060; // 43
+static const uint64_t SH_FLD_CHIPMARK = 5061; // 72
+static const uint64_t SH_FLD_CHIPMARK_LEN = 5062; // 72
+static const uint64_t SH_FLD_CHIPPOS = 5063; // 1
+static const uint64_t SH_FLD_CHIP_INTERFACEMODE = 5064; // 2
+static const uint64_t SH_FLD_CHIP_PERSONALISATION = 5065; // 2
+static const uint64_t SH_FLD_CHIP_RESET = 5066; // 1
+static const uint64_t SH_FLD_CHIP_STATUS = 5067; // 194
+static const uint64_t SH_FLD_CHIP_STATUS_LEN = 5068; // 194
+static const uint64_t SH_FLD_CHIP_TOD_STATUS = 5069; // 98
+static const uint64_t SH_FLD_CHIP_TOD_STATUS_LEN = 5070; // 98
+static const uint64_t SH_FLD_CHKSW_ALLOW1_RD = 5071; // 1
+static const uint64_t SH_FLD_CHKSW_ALLOW1_RDWR = 5072; // 1
+static const uint64_t SH_FLD_CHKSW_ALLOW1_WR = 5073; // 1
+static const uint64_t SH_FLD_CHKSW_AR012 = 5074; // 3
+static const uint64_t SH_FLD_CHKSW_AR012_0 = 5075; // 1
+static const uint64_t SH_FLD_CHKSW_AR012_1 = 5076; // 1
+static const uint64_t SH_FLD_CHKSW_AR012_2 = 5077; // 1
+static const uint64_t SH_FLD_CHKSW_AR012_3 = 5078; // 1
+static const uint64_t SH_FLD_CHKSW_CMDQUEUEING_0 = 5079; // 1
+static const uint64_t SH_FLD_CHKSW_CMDQUEUEING_1 = 5080; // 1
+static const uint64_t SH_FLD_CHKSW_CMDQUEUEING_2 = 5081; // 1
+static const uint64_t SH_FLD_CHKSW_CMDQUEUEING_3 = 5082; // 1
+static const uint64_t SH_FLD_CHKSW_I2C_BUSY_0 = 5083; // 2
+static const uint64_t SH_FLD_CHKSW_I2C_BUSY_1 = 5084; // 1
+static const uint64_t SH_FLD_CHKSW_I2C_BUSY_2 = 5085; // 1
+static const uint64_t SH_FLD_CHKSW_I2C_BUSY_3 = 5086; // 1
+static const uint64_t SH_FLD_CHKSW_OCI_PARCHK_DIS = 5087; // 1
+static const uint64_t SH_FLD_CHKSW_SO_SPARE = 5088; // 1
+static const uint64_t SH_FLD_CHKSW_SO_SPARE_LEN = 5089; // 1
+static const uint64_t SH_FLD_CHKSW_SPARE_6 = 5090; // 1
+static const uint64_t SH_FLD_CHKSW_TANK_RDDATA_PARCHK_DIS = 5091; // 1
+static const uint64_t SH_FLD_CHKSW_VAL_BE_ADDR_CHK_DIS = 5092; // 1
+static const uint64_t SH_FLD_CHKSW_WRFSM_DLY_DIS = 5093; // 1
+static const uint64_t SH_FLD_CHOP1G = 5094; // 1
+static const uint64_t SH_FLD_CHSW_DIS_DATA_HANG = 5095; // 1
+static const uint64_t SH_FLD_CHSW_DIS_ECC_CHECK = 5096; // 1
+static const uint64_t SH_FLD_CHSW_DIS_GROUP_SCOPE = 5097; // 1
+static const uint64_t SH_FLD_CHSW_DIS_OCIABUSPAR_CHECK = 5098; // 1
+static const uint64_t SH_FLD_CHSW_DIS_OCIBEPAR_CHECK = 5099; // 1
+static const uint64_t SH_FLD_CHSW_DIS_OCIDATAPAR_CHECK = 5100; // 1
+static const uint64_t SH_FLD_CHSW_DIS_OCIDATAPAR_GEN = 5101; // 1
+static const uint64_t SH_FLD_CHSW_DIS_OPER_HANG = 5102; // 1
+static const uint64_t SH_FLD_CHSW_DIS_PB_PARITY_CHK = 5103; // 1
+static const uint64_t SH_FLD_CHSW_DIS_RETRY_BACKOFF = 5104; // 1
+static const uint64_t SH_FLD_CHSW_DIS_RTAG_PARITY_CHK = 5105; // 1
+static const uint64_t SH_FLD_CHSW_DIS_WRITE_MATCH_REARB = 5106; // 1
+static const uint64_t SH_FLD_CHSW_EXIT_ON_INVALID_CRESP = 5107; // 1
+static const uint64_t SH_FLD_CHSW_HANG_ON_ADRERROR = 5108; // 1
+static const uint64_t SH_FLD_CHSW_HANG_ON_DERROR = 5109; // 1
+static const uint64_t SH_FLD_CHSW_SKIP_GROUP_SCOPE = 5110; // 1
+static const uint64_t SH_FLD_CHSW_USE_CL_DMA_INJ = 5111; // 1
+static const uint64_t SH_FLD_CHSW_USE_PR_DMA_INJ = 5112; // 1
+static const uint64_t SH_FLD_CHTM_PURGE_C0 = 5113; // 12
+static const uint64_t SH_FLD_CHTM_PURGE_C1 = 5114; // 12
+static const uint64_t SH_FLD_CHTM_PURGE_DONE_C0 = 5115; // 24
+static const uint64_t SH_FLD_CHTM_PURGE_DONE_C1 = 5116; // 24
+static const uint64_t SH_FLD_CI_BUFF_AVAIL = 5117; // 2
+static const uint64_t SH_FLD_CI_BUFF_MIN = 5118; // 2
+static const uint64_t SH_FLD_CI_BUFF_MIN_LEN = 5119; // 2
+static const uint64_t SH_FLD_CI_LOAD = 5120; // 2
+static const uint64_t SH_FLD_CI_LOAD_LEN = 5121; // 2
+static const uint64_t SH_FLD_CI_MACHINE_HANG = 5122; // 12
+static const uint64_t SH_FLD_CI_READ = 5123; // 1
+static const uint64_t SH_FLD_CI_SM_CTL_ERR_DET = 5124; // 1
+static const uint64_t SH_FLD_CI_STORE = 5125; // 1
+static const uint64_t SH_FLD_CI_STORE_BUFFER_THRESHOLD = 5126; // 2
+static const uint64_t SH_FLD_CI_STORE_BUFFER_THRESHOLD_LEN = 5127; // 2
+static const uint64_t SH_FLD_CI_STORE_LEN = 5128; // 1
+static const uint64_t SH_FLD_CI_STORE_RMT = 5129; // 1
+static const uint64_t SH_FLD_CI_STORE_RMT_LEN = 5130; // 1
+static const uint64_t SH_FLD_CI_STORE_RMT_VC = 5131; // 1
+static const uint64_t SH_FLD_CI_STORE_RMT_VC_LEN = 5132; // 1
+static const uint64_t SH_FLD_CI_TIMEOUT_ERR_DET = 5133; // 1
+static const uint64_t SH_FLD_CI_WRITE = 5134; // 1
+static const uint64_t SH_FLD_CKINSM_DIS = 5135; // 1
+static const uint64_t SH_FLD_CKINSM_DIS_LEN = 5136; // 1
+static const uint64_t SH_FLD_CKIN_PROT_ERR_CHK_DIS = 5137; // 1
+static const uint64_t SH_FLD_CKIN_TIMEOUT_CHK_DIS = 5138; // 1
+static const uint64_t SH_FLD_CL = 5139; // 1
+static const uint64_t SH_FLD_CLEAR = 5140; // 1
+static const uint64_t SH_FLD_CLEAR_BAD_LANE_COUNTER = 5141; // 2
+static const uint64_t SH_FLD_CLEAR_CHIPLET_IS_ALIGNED = 5142; // 43
+static const uint64_t SH_FLD_CLEAR_LINK_FAIL_COUNTER = 5143; // 2
+static const uint64_t SH_FLD_CLEAR_STICKY_LEVEL = 5144; // 24
+static const uint64_t SH_FLD_CLKDIST_PDWN = 5145; // 12
+static const uint64_t SH_FLD_CLKDIST_PDWN_LEN = 5146; // 4
+static const uint64_t SH_FLD_CLKGLM_ASYNC_RESET = 5147; // 30
+static const uint64_t SH_FLD_CLKGLM_SEL = 5148; // 30
+static const uint64_t SH_FLD_CLK_ASYNC_RESET = 5149; // 43
+static const uint64_t SH_FLD_CLK_BIST_ACTIVITY_DET = 5150; // 4
+static const uint64_t SH_FLD_CLK_BIST_ERR = 5151; // 4
+static const uint64_t SH_FLD_CLK_DCC_BYPASS_EN = 5152; // 43
+static const uint64_t SH_FLD_CLK_DIV_BYPASS_EN = 5153; // 43
+static const uint64_t SH_FLD_CLK_DLY = 5154; // 1
+static const uint64_t SH_FLD_CLK_DLY_LEN = 5155; // 1
+static const uint64_t SH_FLD_CLK_HALF_WIDTH_MODE = 5156; // 4
+static const uint64_t SH_FLD_CLK_INVERT = 5157; // 6
+static const uint64_t SH_FLD_CLK_PDLY_BYPASS_EN = 5158; // 43
+static const uint64_t SH_FLD_CLK_PULSE_EN = 5159; // 43
+static const uint64_t SH_FLD_CLK_PULSE_MODE = 5160; // 43
+static const uint64_t SH_FLD_CLK_PULSE_MODE_LEN = 5161; // 43
+static const uint64_t SH_FLD_CLK_QUIESCE = 5162; // 4
+static const uint64_t SH_FLD_CLK_QUIESCE_LEN = 5163; // 4
+static const uint64_t SH_FLD_CLK_QUIESCE_N = 5164; // 1
+static const uint64_t SH_FLD_CLK_QUIESCE_N_LEN = 5165; // 1
+static const uint64_t SH_FLD_CLK_QUIESCE_P = 5166; // 1
+static const uint64_t SH_FLD_CLK_QUIESCE_P_LEN = 5167; // 1
+static const uint64_t SH_FLD_CLK_RATE = 5168; // 4
+static const uint64_t SH_FLD_CLK_RATE_LEN = 5169; // 4
+static const uint64_t SH_FLD_CLK_RATE_SEL = 5170; // 1
+static const uint64_t SH_FLD_CLK_RATE_SEL_LEN = 5171; // 1
+static const uint64_t SH_FLD_CLK_RUN_COUNT = 5172; // 4
+static const uint64_t SH_FLD_CLK_SB_PULSE_MODE = 5173; // 24
+static const uint64_t SH_FLD_CLK_SB_PULSE_MODE_EN = 5174; // 24
+static const uint64_t SH_FLD_CLK_SB_PULSE_MODE_LEN = 5175; // 24
+static const uint64_t SH_FLD_CLK_SB_SPARE = 5176; // 24
+static const uint64_t SH_FLD_CLK_SB_STRENGTH = 5177; // 24
+static const uint64_t SH_FLD_CLK_SB_STRENGTH_LEN = 5178; // 24
+static const uint64_t SH_FLD_CLK_SW_RESCLK = 5179; // 24
+static const uint64_t SH_FLD_CLK_SW_RESCLK_LEN = 5180; // 24
+static const uint64_t SH_FLD_CLK_SW_SPARE = 5181; // 24
+static const uint64_t SH_FLD_CLK_SYNC = 5182; // 24
+static const uint64_t SH_FLD_CLK_SYNC_DONE = 5183; // 24
+static const uint64_t SH_FLD_CLK_SYNC_ENABLE = 5184; // 24
+static const uint64_t SH_FLD_CLK_UNLOAD_CLK_DISABLE = 5185; // 4
+static const uint64_t SH_FLD_CLK_UNLOAD_SEL = 5186; // 4
+static const uint64_t SH_FLD_CLK_UNLOAD_SEL_LEN = 5187; // 4
+static const uint64_t SH_FLD_CLOCK_CMD = 5188; // 43
+static const uint64_t SH_FLD_CLOCK_CMD_LEN = 5189; // 43
+static const uint64_t SH_FLD_CLOCK_DIVIDER = 5190; // 1
+static const uint64_t SH_FLD_CLOCK_DIVIDER_LEN = 5191; // 1
+static const uint64_t SH_FLD_CLOCK_DIV_4 = 5192; // 3
+static const uint64_t SH_FLD_CLOCK_PERV = 5193; // 43
+static const uint64_t SH_FLD_CLOCK_PULSE_USE_EVEN = 5194; // 43
+static const uint64_t SH_FLD_CLOCK_RATE_SELECTION = 5195; // 3
+static const uint64_t SH_FLD_CLOCK_RATE_SELECTION_0 = 5196; // 1
+static const uint64_t SH_FLD_CLOCK_RATE_SELECTION_0_LEN = 5197; // 1
+static const uint64_t SH_FLD_CLOCK_RATE_SELECTION_1 = 5198; // 2
+static const uint64_t SH_FLD_CLOCK_RATE_SELECTION_1_LEN = 5199; // 2
+static const uint64_t SH_FLD_CLOCK_RATE_SELECTION_LEN = 5200; // 3
+static const uint64_t SH_FLD_CLOCK_UNIT1 = 5201; // 43
+static const uint64_t SH_FLD_CLOCK_UNIT10 = 5202; // 43
+static const uint64_t SH_FLD_CLOCK_UNIT2 = 5203; // 43
+static const uint64_t SH_FLD_CLOCK_UNIT3 = 5204; // 43
+static const uint64_t SH_FLD_CLOCK_UNIT4 = 5205; // 43
+static const uint64_t SH_FLD_CLOCK_UNIT5 = 5206; // 43
+static const uint64_t SH_FLD_CLOCK_UNIT6 = 5207; // 43
+static const uint64_t SH_FLD_CLOCK_UNIT7 = 5208; // 43
+static const uint64_t SH_FLD_CLOCK_UNIT8 = 5209; // 43
+static const uint64_t SH_FLD_CLOCK_UNIT9 = 5210; // 43
+static const uint64_t SH_FLD_CLONE_CS_MODE = 5211; // 8
+static const uint64_t SH_FLD_CLR_PAR_ERRS = 5212; // 16
+static const uint64_t SH_FLD_CLSTATE_DEBUG_SEL = 5213; // 8
+static const uint64_t SH_FLD_CLSTATE_DEBUG_SEL_LEN = 5214; // 8
+static const uint64_t SH_FLD_CL_DATA = 5215; // 43
+static const uint64_t SH_FLD_CL_ECC_CE = 5216; // 1
+static const uint64_t SH_FLD_CL_ECC_UE = 5217; // 1
+static const uint64_t SH_FLD_CL_FINE_DISABLE = 5218; // 4
+static const uint64_t SH_FLD_CL_FINE_DISABLE_LEN = 5219; // 4
+static const uint64_t SH_FLD_CL_FSM = 5220; // 43
+static const uint64_t SH_FLD_CL_GLOBAL_DISABLE = 5221; // 4
+static const uint64_t SH_FLD_CL_GLOBAL_DISABLE_LEN = 5222; // 4
+static const uint64_t SH_FLD_CL_LEN = 5223; // 1
+static const uint64_t SH_FLD_CL_PROBE_PB_HANG = 5224; // 2
+static const uint64_t SH_FLD_CL_TIMEOUT_SEL = 5225; // 4
+static const uint64_t SH_FLD_CL_TIMEOUT_SEL_LEN = 5226; // 4
+static const uint64_t SH_FLD_CL_WRAP_DEBUG_SEL = 5227; // 8
+static const uint64_t SH_FLD_CL_WRAP_DEBUG_SEL_LEN = 5228; // 8
+static const uint64_t SH_FLD_CMD = 5229; // 43
+static const uint64_t SH_FLD_CMDREG_BROADCAST_FLAG = 5230; // 1
+static const uint64_t SH_FLD_CMDREG_SCAN_ADDRESS = 5231; // 1
+static const uint64_t SH_FLD_CMDREG_SCAN_ADDRESS_LEN = 5232; // 1
+static const uint64_t SH_FLD_CMDREG_SCAN_REGION = 5233; // 1
+static const uint64_t SH_FLD_CMDREG_SCAN_REGION_LEN = 5234; // 1
+static const uint64_t SH_FLD_CMDREG_SCAN_TYPE = 5235; // 1
+static const uint64_t SH_FLD_CMDREG_SCAN_TYPE_LEN = 5236; // 1
+static const uint64_t SH_FLD_CMDREG_WRITE_FLAG = 5237; // 1
+static const uint64_t SH_FLD_CMD_BUFFER_PAR_ERR = 5238; // 4
+static const uint64_t SH_FLD_CMD_COUNT_ERR = 5239; // 1
+static const uint64_t SH_FLD_CMD_EXP_TIME = 5240; // 7
+static const uint64_t SH_FLD_CMD_EXP_TIME_LEN = 5241; // 7
+static const uint64_t SH_FLD_CMD_IN_PROG = 5242; // 1
+static const uint64_t SH_FLD_CMD_LEN = 5243; // 43
+static const uint64_t SH_FLD_CMD_PARITY_ERROR = 5244; // 19
+static const uint64_t SH_FLD_CMD_PRECEDE_TIME = 5245; // 8
+static const uint64_t SH_FLD_CMD_PRECEDE_TIME_LEN = 5246; // 8
+static const uint64_t SH_FLD_CMD_QX_SEVERE_ERR = 5247; // 1
+static const uint64_t SH_FLD_CMD_REG = 5248; // 1
+static const uint64_t SH_FLD_CMD_REG_ADDR_1 = 5249; // 1
+static const uint64_t SH_FLD_CMD_REG_ADDR_1_LEN = 5250; // 1
+static const uint64_t SH_FLD_CMD_REG_ADDR_2 = 5251; // 1
+static const uint64_t SH_FLD_CMD_REG_ADDR_2_LEN = 5252; // 1
+static const uint64_t SH_FLD_CMD_REG_ADDR_3 = 5253; // 1
+static const uint64_t SH_FLD_CMD_REG_ADDR_3_LEN = 5254; // 1
+static const uint64_t SH_FLD_CMD_REG_ADDR_4 = 5255; // 1
+static const uint64_t SH_FLD_CMD_REG_ADDR_4_LEN = 5256; // 1
+static const uint64_t SH_FLD_CMD_REG_BIT_READCONT = 5257; // 1
+static const uint64_t SH_FLD_CMD_REG_BIT_RNW = 5258; // 1
+static const uint64_t SH_FLD_CMD_REG_BIT_WITHADDR = 5259; // 1
+static const uint64_t SH_FLD_CMD_REG_BIT_WITHSTART = 5260; // 1
+static const uint64_t SH_FLD_CMD_REG_BIT_WITHSTOP = 5261; // 1
+static const uint64_t SH_FLD_CMD_REG_LEN = 5262; // 1
+static const uint64_t SH_FLD_CMD_REG_LENGTH = 5263; // 1
+static const uint64_t SH_FLD_CMD_REG_LENGTH_LEN = 5264; // 1
+static const uint64_t SH_FLD_CMD_SCOPE = 5265; // 4
+static const uint64_t SH_FLD_CMD_SCOPE_LEN = 5266; // 4
+static const uint64_t SH_FLD_CMD_STATUS = 5267; // 1
+static const uint64_t SH_FLD_CMD_STATUS_LEN = 5268; // 1
+static const uint64_t SH_FLD_CME0_IVRM_DROPOUT = 5269; // 6
+static const uint64_t SH_FLD_CME1_IVRM_DROPOUT = 5270; // 6
+static const uint64_t SH_FLD_CMETH = 5271; // 6
+static const uint64_t SH_FLD_CMETH_LEN = 5272; // 6
+static const uint64_t SH_FLD_CME_ERROR_NOTIFY = 5273; // 1
+static const uint64_t SH_FLD_CME_ERR_NOTIFY_DIS = 5274; // 24
+static const uint64_t SH_FLD_CME_INTERPPM_ACLK_ENABLE = 5275; // 6
+static const uint64_t SH_FLD_CME_INTERPPM_ACLK_SEL = 5276; // 6
+static const uint64_t SH_FLD_CME_INTERPPM_DPLL_ENABLE = 5277; // 6
+static const uint64_t SH_FLD_CME_INTERPPM_DPLL_SEL = 5278; // 6
+static const uint64_t SH_FLD_CME_INTERPPM_IVRM_ENABLE = 5279; // 6
+static const uint64_t SH_FLD_CME_INTERPPM_IVRM_SEL = 5280; // 6
+static const uint64_t SH_FLD_CME_INTERPPM_VDATA_ENABLE = 5281; // 6
+static const uint64_t SH_FLD_CME_INTERPPM_VDATA_SEL = 5282; // 6
+static const uint64_t SH_FLD_CME_MESSAGE = 5283; // 24
+static const uint64_t SH_FLD_CME_MESSAGE_HI = 5284; // 48
+static const uint64_t SH_FLD_CME_MESSAGE_HI_LEN = 5285; // 48
+static const uint64_t SH_FLD_CME_MESSAGE_LEN = 5286; // 24
+static const uint64_t SH_FLD_CME_MESSAGE_NUMBER0 = 5287; // 24
+static const uint64_t SH_FLD_CME_MESSAGE_NUMBER0_LEN = 5288; // 24
+static const uint64_t SH_FLD_CME_MESSAGE_NUMBER_N = 5289; // 72
+static const uint64_t SH_FLD_CME_MESSAGE_NUMBER_N_LEN = 5290; // 72
+static const uint64_t SH_FLD_CME_REQUEST = 5291; // 96
+static const uint64_t SH_FLD_CME_SPECIAL_WKUP_DONE_DIS = 5292; // 24
+static const uint64_t SH_FLD_CMFSI_ACCESS_PROTCT = 5293; // 1
+static const uint64_t SH_FLD_CMLEN = 5294; // 7
+static const uint64_t SH_FLD_CMLEN100 = 5295; // 3
+static const uint64_t SH_FLD_CMLEN133 = 5296; // 3
+static const uint64_t SH_FLD_CMLEN156 = 5297; // 3
+static const uint64_t SH_FLD_CMP_MSK_LT_B_64_TO_87 = 5298; // 90
+static const uint64_t SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN = 5299; // 90
+static const uint64_t SH_FLD_CMP_MSK_LT_B_TO_63 = 5300; // 90
+static const uint64_t SH_FLD_CMP_MSK_LT_B_TO_63_LEN = 5301; // 90
+static const uint64_t SH_FLD_CMSK = 5302; // 43
+static const uint64_t SH_FLD_CM_CFG = 5303; // 6
+static const uint64_t SH_FLD_CM_CFG_LEN = 5304; // 6
+static const uint64_t SH_FLD_CM_CNTL = 5305; // 120
+static const uint64_t SH_FLD_CM_CNTL_LEN = 5306; // 120
+static const uint64_t SH_FLD_CM_OFFSET_VAL = 5307; // 6
+static const uint64_t SH_FLD_CM_OFFSET_VAL_LEN = 5308; // 6
+static const uint64_t SH_FLD_CM_TIMEOUT = 5309; // 6
+static const uint64_t SH_FLD_CM_TIMEOUT_LEN = 5310; // 6
+static const uint64_t SH_FLD_CND_HWD_DOES_DEM_IVE = 5311; // 1
+static const uint64_t SH_FLD_CND_HWD_DOES_DEM_IVE_LEN = 5312; // 1
+static const uint64_t SH_FLD_CNT0 = 5313; // 2
+static const uint64_t SH_FLD_CNT0_BIT_PAIR_SEL = 5314; // 1
+static const uint64_t SH_FLD_CNT0_BIT_PAIR_SEL_LEN = 5315; // 1
+static const uint64_t SH_FLD_CNT0_ENABLE = 5316; // 1
+static const uint64_t SH_FLD_CNT0_EVENT_SEL = 5317; // 1
+static const uint64_t SH_FLD_CNT0_EVENT_SEL_LEN = 5318; // 1
+static const uint64_t SH_FLD_CNT0_LEN = 5319; // 2
+static const uint64_t SH_FLD_CNT0_MUX_SEL = 5320; // 2
+static const uint64_t SH_FLD_CNT0_MUX_SEL_LEN = 5321; // 2
+static const uint64_t SH_FLD_CNT0_PAIR_OP = 5322; // 2
+static const uint64_t SH_FLD_CNT0_PAIR_OP_LEN = 5323; // 2
+static const uint64_t SH_FLD_CNT0_POSEDGE_SEL = 5324; // 1
+static const uint64_t SH_FLD_CNT1 = 5325; // 2
+static const uint64_t SH_FLD_CNT1_BIT_PAIR_SEL = 5326; // 1
+static const uint64_t SH_FLD_CNT1_BIT_PAIR_SEL_LEN = 5327; // 1
+static const uint64_t SH_FLD_CNT1_ENABLE = 5328; // 1
+static const uint64_t SH_FLD_CNT1_EVENT_SEL = 5329; // 1
+static const uint64_t SH_FLD_CNT1_EVENT_SEL_LEN = 5330; // 1
+static const uint64_t SH_FLD_CNT1_LEN = 5331; // 2
+static const uint64_t SH_FLD_CNT1_MUX_SEL = 5332; // 2
+static const uint64_t SH_FLD_CNT1_MUX_SEL_LEN = 5333; // 2
+static const uint64_t SH_FLD_CNT1_PAIR_OP = 5334; // 2
+static const uint64_t SH_FLD_CNT1_PAIR_OP_LEN = 5335; // 2
+static const uint64_t SH_FLD_CNT1_POSEDGE_SEL = 5336; // 1
+static const uint64_t SH_FLD_CNT2 = 5337; // 2
+static const uint64_t SH_FLD_CNT2_BIT_PAIR_SEL = 5338; // 1
+static const uint64_t SH_FLD_CNT2_BIT_PAIR_SEL_LEN = 5339; // 1
+static const uint64_t SH_FLD_CNT2_ENABLE = 5340; // 1
+static const uint64_t SH_FLD_CNT2_EVENT_SEL = 5341; // 1
+static const uint64_t SH_FLD_CNT2_EVENT_SEL_LEN = 5342; // 1
+static const uint64_t SH_FLD_CNT2_LEN = 5343; // 2
+static const uint64_t SH_FLD_CNT2_MUX_SEL = 5344; // 2
+static const uint64_t SH_FLD_CNT2_MUX_SEL_LEN = 5345; // 2
+static const uint64_t SH_FLD_CNT2_PAIR_OP = 5346; // 2
+static const uint64_t SH_FLD_CNT2_PAIR_OP_LEN = 5347; // 2
+static const uint64_t SH_FLD_CNT2_POSEDGE_SEL = 5348; // 1
+static const uint64_t SH_FLD_CNT3 = 5349; // 2
+static const uint64_t SH_FLD_CNT3_BIT_PAIR_SEL = 5350; // 1
+static const uint64_t SH_FLD_CNT3_BIT_PAIR_SEL_LEN = 5351; // 1
+static const uint64_t SH_FLD_CNT3_ENABLE = 5352; // 1
+static const uint64_t SH_FLD_CNT3_EVENT_SEL = 5353; // 1
+static const uint64_t SH_FLD_CNT3_EVENT_SEL_LEN = 5354; // 1
+static const uint64_t SH_FLD_CNT3_LEN = 5355; // 2
+static const uint64_t SH_FLD_CNT3_MUX_SEL = 5356; // 2
+static const uint64_t SH_FLD_CNT3_MUX_SEL_LEN = 5357; // 2
+static const uint64_t SH_FLD_CNT3_PAIR_OP = 5358; // 2
+static const uint64_t SH_FLD_CNT3_PAIR_OP_LEN = 5359; // 2
+static const uint64_t SH_FLD_CNT3_POSEDGE_SEL = 5360; // 1
+static const uint64_t SH_FLD_CNTL = 5361; // 8
+static const uint64_t SH_FLD_CNTLS_PREV_LDED_GCRMSG = 5362; // 4
+static const uint64_t SH_FLD_CNTL_LEN = 5363; // 8
+static const uint64_t SH_FLD_CNT_BROADCAST = 5364; // 1
+static const uint64_t SH_FLD_CNT_BROADCAST_LEN = 5365; // 1
+static const uint64_t SH_FLD_CNT_CI_STORE_REPLAY = 5366; // 1
+static const uint64_t SH_FLD_CNT_CI_STORE_REPLAY_LEN = 5367; // 1
+static const uint64_t SH_FLD_CNT_DEM_CACHE_HIT = 5368; // 1
+static const uint64_t SH_FLD_CNT_DEM_CACHE_HIT_LEN = 5369; // 1
+static const uint64_t SH_FLD_CNT_DMA_RD = 5370; // 6
+static const uint64_t SH_FLD_CNT_DMA_RD_LEN = 5371; // 6
+static const uint64_t SH_FLD_CNT_DMA_WR = 5372; // 6
+static const uint64_t SH_FLD_CNT_DMA_WR_LEN = 5373; // 6
+static const uint64_t SH_FLD_CNT_EOI_CACHE_HIT = 5374; // 1
+static const uint64_t SH_FLD_CNT_EOI_CACHE_HIT_LEN = 5375; // 1
+static const uint64_t SH_FLD_CNT_EOI_RESP_REPLAY = 5376; // 2
+static const uint64_t SH_FLD_CNT_EOI_RESP_REPLAY_LEN = 5377; // 2
+static const uint64_t SH_FLD_CNT_EQC_COMMAND = 5378; // 1
+static const uint64_t SH_FLD_CNT_EQC_COMMAND_LEN = 5379; // 1
+static const uint64_t SH_FLD_CNT_EQD_FETCH = 5380; // 1
+static const uint64_t SH_FLD_CNT_EQD_FETCH_LEN = 5381; // 1
+static const uint64_t SH_FLD_CNT_EQD_FETCH_REPLAY = 5382; // 1
+static const uint64_t SH_FLD_CNT_EQD_FETCH_REPLAY_LEN = 5383; // 1
+static const uint64_t SH_FLD_CNT_EQP = 5384; // 1
+static const uint64_t SH_FLD_CNT_EQP_LEN = 5385; // 1
+static const uint64_t SH_FLD_CNT_EQP_REPLAY = 5386; // 1
+static const uint64_t SH_FLD_CNT_EQP_REPLAY_LEN = 5387; // 1
+static const uint64_t SH_FLD_CNT_EQ_FWD = 5388; // 1
+static const uint64_t SH_FLD_CNT_EQ_FWD_LEN = 5389; // 1
+static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC = 5390; // 1
+static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC_LEN = 5391; // 1
+static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC = 5392; // 1
+static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC_LEN = 5393; // 1
+static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_HWD = 5394; // 1
+static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_HWD_LEN = 5395; // 1
+static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_IPI = 5396; // 1
+static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_IPI_LEN = 5397; // 1
+static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS = 5398; // 1
+static const uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS_LEN = 5399; // 1
+static const uint64_t SH_FLD_CNT_EQ_TRIG_CACHE_HIT = 5400; // 1
+static const uint64_t SH_FLD_CNT_EQ_TRIG_CACHE_HIT_LEN = 5401; // 1
+static const uint64_t SH_FLD_CNT_ESCALATE = 5402; // 1
+static const uint64_t SH_FLD_CNT_ESCALATE_LEN = 5403; // 1
+static const uint64_t SH_FLD_CNT_FIFO_FULL = 5404; // 6
+static const uint64_t SH_FLD_CNT_FIFO_FULL_LEN = 5405; // 6
+static const uint64_t SH_FLD_CNT_GROUP = 5406; // 1
+static const uint64_t SH_FLD_CNT_GROUP_LEN = 5407; // 1
+static const uint64_t SH_FLD_CNT_GROUP_SCAN_CACHE_HIT = 5408; // 1
+static const uint64_t SH_FLD_CNT_GROUP_SCAN_CACHE_HIT_LEN = 5409; // 1
+static const uint64_t SH_FLD_CNT_HWD_DOES_PRF_IVE = 5410; // 1
+static const uint64_t SH_FLD_CNT_HWD_DOES_PRF_IVE_LEN = 5411; // 1
+static const uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE = 5412; // 1
+static const uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_LEN = 5413; // 1
+static const uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC = 5414; // 1
+static const uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC_LEN = 5415; // 1
+static const uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE = 5416; // 1
+static const uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_LEN = 5417; // 1
+static const uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC = 5418; // 1
+static const uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC_LEN = 5419; // 1
+static const uint64_t SH_FLD_CNT_ISB_FETCH = 5420; // 1
+static const uint64_t SH_FLD_CNT_ISB_FETCH_LEN = 5421; // 1
+static const uint64_t SH_FLD_CNT_ISB_FETCH_REPLAY = 5422; // 1
+static const uint64_t SH_FLD_CNT_ISB_FETCH_REPLAY_LEN = 5423; // 1
+static const uint64_t SH_FLD_CNT_ISB_WRITE = 5424; // 1
+static const uint64_t SH_FLD_CNT_ISB_WRITE_LEN = 5425; // 1
+static const uint64_t SH_FLD_CNT_IVC_DEMAND = 5426; // 1
+static const uint64_t SH_FLD_CNT_IVC_DEMAND_LEN = 5427; // 1
+static const uint64_t SH_FLD_CNT_IVC_PRF = 5428; // 1
+static const uint64_t SH_FLD_CNT_IVC_PRF_LEN = 5429; // 1
+static const uint64_t SH_FLD_CNT_IVC_RESP_REPLAY = 5430; // 1
+static const uint64_t SH_FLD_CNT_IVC_RESP_REPLAY_LEN = 5431; // 1
+static const uint64_t SH_FLD_CNT_IVE_FETCH = 5432; // 1
+static const uint64_t SH_FLD_CNT_IVE_FETCH_LEN = 5433; // 1
+static const uint64_t SH_FLD_CNT_IVE_FETCH_REPLAY = 5434; // 1
+static const uint64_t SH_FLD_CNT_IVE_FETCH_REPLAY_LEN = 5435; // 1
+static const uint64_t SH_FLD_CNT_IVVC_RESP = 5436; // 1
+static const uint64_t SH_FLD_CNT_IVVC_RESP_LEN = 5437; // 1
+static const uint64_t SH_FLD_CNT_LCL_GRPSCAN_REPLAY = 5438; // 1
+static const uint64_t SH_FLD_CNT_LCL_GRPSCAN_REPLAY_LEN = 5439; // 1
+static const uint64_t SH_FLD_CNT_LCL_PRESS_RELIEF = 5440; // 1
+static const uint64_t SH_FLD_CNT_LCL_PRESS_RELIEF_LEN = 5441; // 1
+static const uint64_t SH_FLD_CNT_LCL_REDIST = 5442; // 1
+static const uint64_t SH_FLD_CNT_LCL_REDIST_LEN = 5443; // 1
+static const uint64_t SH_FLD_CNT_LD_CACHE_HIT = 5444; // 1
+static const uint64_t SH_FLD_CNT_LD_CACHE_HIT_LEN = 5445; // 1
+static const uint64_t SH_FLD_CNT_LD_REQ_REPLAY = 5446; // 1
+static const uint64_t SH_FLD_CNT_LD_REQ_REPLAY_LEN = 5447; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_ESCALATE = 5448; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_ESCALATE_LEN = 5449; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_ESC_CACHE_HIT = 5450; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_ESC_CACHE_HIT_LEN = 5451; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_ESC_REPLAY = 5452; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_ESC_REPLAY_LEN = 5453; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_GROUP_SCAN = 5454; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_GROUP_SCAN_LEN = 5455; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_SBC_REPLAY = 5456; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_SBC_REPLAY_LEN = 5457; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_SBC_UPD = 5458; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_SBC_UPD_LEN = 5459; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_VPC_REPLAY = 5460; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_VPC_REPLAY_LEN = 5461; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_VPC_UPD = 5462; // 1
+static const uint64_t SH_FLD_CNT_LOCAL_VPC_UPD_LEN = 5463; // 1
+static const uint64_t SH_FLD_CNT_LS = 5464; // 1
+static const uint64_t SH_FLD_CNT_LS_LEN = 5465; // 1
+static const uint64_t SH_FLD_CNT_NEW_CMD_STALLED = 5466; // 1
+static const uint64_t SH_FLD_CNT_NEW_CMD_STALLED_LEN = 5467; // 1
+static const uint64_t SH_FLD_CNT_NON_SPEC_EOI = 5468; // 1
+static const uint64_t SH_FLD_CNT_NON_SPEC_EOI_LEN = 5469; // 1
+static const uint64_t SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED = 5470; // 1
+static const uint64_t SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED_LEN = 5471; // 1
+static const uint64_t SH_FLD_CNT_NON_SPEC_EOI_OWNED = 5472; // 1
+static const uint64_t SH_FLD_CNT_NON_SPEC_EOI_OWNED_LEN = 5473; // 1
+static const uint64_t SH_FLD_CNT_NON_SPEC_LOAD = 5474; // 1
+static const uint64_t SH_FLD_CNT_NON_SPEC_LOAD_LEN = 5475; // 1
+static const uint64_t SH_FLD_CNT_NON_SPEC_SW_LOAD = 5476; // 1
+static const uint64_t SH_FLD_CNT_NON_SPEC_SW_LOAD_LEN = 5477; // 1
+static const uint64_t SH_FLD_CNT_NON_SPEC_VC_LOAD = 5478; // 1
+static const uint64_t SH_FLD_CNT_NON_SPEC_VC_LOAD_LEN = 5479; // 1
+static const uint64_t SH_FLD_CNT_OTHER_CACHE_HIT = 5480; // 1
+static const uint64_t SH_FLD_CNT_OTHER_CACHE_HIT_LEN = 5481; // 1
+static const uint64_t SH_FLD_CNT_PRF_CACHE_HIT = 5482; // 2
+static const uint64_t SH_FLD_CNT_PRF_CACHE_HIT_LEN = 5483; // 2
+static const uint64_t SH_FLD_CNT_R0 = 5484; // 6
+static const uint64_t SH_FLD_CNT_R0_LEN = 5485; // 6
+static const uint64_t SH_FLD_CNT_R10R = 5486; // 3
+static const uint64_t SH_FLD_CNT_R10R_LEN = 5487; // 3
+static const uint64_t SH_FLD_CNT_R10W = 5488; // 3
+static const uint64_t SH_FLD_CNT_R10W_LEN = 5489; // 3
+static const uint64_t SH_FLD_CNT_R1R = 5490; // 6
+static const uint64_t SH_FLD_CNT_R1R_LEN = 5491; // 6
+static const uint64_t SH_FLD_CNT_R1W = 5492; // 6
+static const uint64_t SH_FLD_CNT_R1W_LEN = 5493; // 6
+static const uint64_t SH_FLD_CNT_R2 = 5494; // 6
+static const uint64_t SH_FLD_CNT_R2_LEN = 5495; // 6
+static const uint64_t SH_FLD_CNT_R3 = 5496; // 6
+static const uint64_t SH_FLD_CNT_R3_LEN = 5497; // 6
+static const uint64_t SH_FLD_CNT_R4 = 5498; // 3
+static const uint64_t SH_FLD_CNT_R4R = 5499; // 3
+static const uint64_t SH_FLD_CNT_R4R_LEN = 5500; // 3
+static const uint64_t SH_FLD_CNT_R4W = 5501; // 3
+static const uint64_t SH_FLD_CNT_R4W_LEN = 5502; // 3
+static const uint64_t SH_FLD_CNT_R4_LEN = 5503; // 3
+static const uint64_t SH_FLD_CNT_R5 = 5504; // 3
+static const uint64_t SH_FLD_CNT_R5R = 5505; // 3
+static const uint64_t SH_FLD_CNT_R5R_LEN = 5506; // 3
+static const uint64_t SH_FLD_CNT_R5W = 5507; // 3
+static const uint64_t SH_FLD_CNT_R5W_LEN = 5508; // 3
+static const uint64_t SH_FLD_CNT_R5_LEN = 5509; // 3
+static const uint64_t SH_FLD_CNT_R6 = 5510; // 6
+static const uint64_t SH_FLD_CNT_R6_LEN = 5511; // 6
+static const uint64_t SH_FLD_CNT_R7 = 5512; // 3
+static const uint64_t SH_FLD_CNT_R7EQP = 5513; // 3
+static const uint64_t SH_FLD_CNT_R7EQP_LEN = 5514; // 3
+static const uint64_t SH_FLD_CNT_R7INT = 5515; // 3
+static const uint64_t SH_FLD_CNT_R7INT_LEN = 5516; // 3
+static const uint64_t SH_FLD_CNT_R7RSP = 5517; // 3
+static const uint64_t SH_FLD_CNT_R7RSP_LEN = 5518; // 3
+static const uint64_t SH_FLD_CNT_R7_LEN = 5519; // 3
+static const uint64_t SH_FLD_CNT_R8 = 5520; // 6
+static const uint64_t SH_FLD_CNT_R8_LEN = 5521; // 6
+static const uint64_t SH_FLD_CNT_R9 = 5522; // 6
+static const uint64_t SH_FLD_CNT_R9_LEN = 5523; // 6
+static const uint64_t SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY = 5524; // 1
+static const uint64_t SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY_LEN = 5525; // 1
+static const uint64_t SH_FLD_CNT_REMOTE_SBC_UPD = 5526; // 1
+static const uint64_t SH_FLD_CNT_REMOTE_SBC_UPD_LEN = 5527; // 1
+static const uint64_t SH_FLD_CNT_REMOTE_VPC_UPD = 5528; // 1
+static const uint64_t SH_FLD_CNT_REMOTE_VPC_UPD_LEN = 5529; // 1
+static const uint64_t SH_FLD_CNT_REPLAY = 5530; // 1
+static const uint64_t SH_FLD_CNT_REPLAY_LEN = 5531; // 1
+static const uint64_t SH_FLD_CNT_RETRY = 5532; // 3
+static const uint64_t SH_FLD_CNT_RETRY_LEN = 5533; // 3
+static const uint64_t SH_FLD_CNT_RMT_PULL_1STGRP = 5534; // 1
+static const uint64_t SH_FLD_CNT_RMT_PULL_1STGRP_LEN = 5535; // 1
+static const uint64_t SH_FLD_CNT_RMT_PULL_1STVP = 5536; // 1
+static const uint64_t SH_FLD_CNT_RMT_PULL_1STVP_LEN = 5537; // 1
+static const uint64_t SH_FLD_CNT_RMT_PULL_GRP = 5538; // 1
+static const uint64_t SH_FLD_CNT_RMT_PULL_GRP_LEN = 5539; // 1
+static const uint64_t SH_FLD_CNT_RMT_PULL_VP = 5540; // 1
+static const uint64_t SH_FLD_CNT_RMT_PULL_VP_LEN = 5541; // 1
+static const uint64_t SH_FLD_CNT_RMT_PUSH = 5542; // 1
+static const uint64_t SH_FLD_CNT_RMT_PUSH_LEN = 5543; // 1
+static const uint64_t SH_FLD_CNT_RMT_PUSH_VC = 5544; // 1
+static const uint64_t SH_FLD_CNT_RMT_PUSH_VC_LEN = 5545; // 1
+static const uint64_t SH_FLD_CNT_RSP_ATX_REPLAY = 5546; // 1
+static const uint64_t SH_FLD_CNT_RSP_ATX_REPLAY_LEN = 5547; // 1
+static const uint64_t SH_FLD_CNT_RSP_LCL_TCTXT = 5548; // 1
+static const uint64_t SH_FLD_CNT_RSP_LCL_TCTXT_LEN = 5549; // 1
+static const uint64_t SH_FLD_CNT_RSP_LCL_VC = 5550; // 1
+static const uint64_t SH_FLD_CNT_RSP_LCL_VC_LEN = 5551; // 1
+static const uint64_t SH_FLD_CNT_RSP_RMT = 5552; // 1
+static const uint64_t SH_FLD_CNT_RSP_RMT_LEN = 5553; // 1
+static const uint64_t SH_FLD_CNT_RSP_RMT_VC = 5554; // 1
+static const uint64_t SH_FLD_CNT_RSP_RMT_VC_LEN = 5555; // 1
+static const uint64_t SH_FLD_CNT_RSP_SW_LD = 5556; // 1
+static const uint64_t SH_FLD_CNT_RSP_SW_LD_LEN = 5557; // 1
+static const uint64_t SH_FLD_CNT_RSP_TCTXT_REPLAY = 5558; // 1
+static const uint64_t SH_FLD_CNT_RSP_TCTXT_REPLAY_LEN = 5559; // 1
+static const uint64_t SH_FLD_CNT_SAME_VPD_REPLAY = 5560; // 1
+static const uint64_t SH_FLD_CNT_SAME_VPD_REPLAY_LEN = 5561; // 1
+static const uint64_t SH_FLD_CNT_SBC_LOOKUP = 5562; // 1
+static const uint64_t SH_FLD_CNT_SBC_LOOKUP_LEN = 5563; // 1
+static const uint64_t SH_FLD_CNT_SBC_LOOKUP_REPLAY = 5564; // 1
+static const uint64_t SH_FLD_CNT_SBC_LOOKUP_REPLAY_LEN = 5565; // 1
+static const uint64_t SH_FLD_CNT_SINGLE_LANE_RECAL = 5566; // 6
+static const uint64_t SH_FLD_CNT_SPEC_EOI = 5567; // 1
+static const uint64_t SH_FLD_CNT_SPEC_EOI_CACHE_HIT = 5568; // 1
+static const uint64_t SH_FLD_CNT_SPEC_EOI_CACHE_HIT_LEN = 5569; // 1
+static const uint64_t SH_FLD_CNT_SPEC_EOI_LEN = 5570; // 1
+static const uint64_t SH_FLD_CNT_ST_LCL_REPLAY = 5571; // 1
+static const uint64_t SH_FLD_CNT_ST_LCL_REPLAY_LEN = 5572; // 1
+static const uint64_t SH_FLD_CNT_ST_RMT_REPLAY = 5573; // 1
+static const uint64_t SH_FLD_CNT_ST_RMT_REPLAY_LEN = 5574; // 1
+static const uint64_t SH_FLD_CNT_ST_RMT_VC_REPLAY = 5575; // 1
+static const uint64_t SH_FLD_CNT_ST_RMT_VC_REPLAY_LEN = 5576; // 1
+static const uint64_t SH_FLD_CNT_TOO_MANY_ENTRIES = 5577; // 3
+static const uint64_t SH_FLD_CNT_TOO_MANY_ENTRIES_LEN = 5578; // 3
+static const uint64_t SH_FLD_CNT_TRIG_DROPPED = 5579; // 6
+static const uint64_t SH_FLD_CNT_TRIG_DROPPED_LEN = 5580; // 6
+static const uint64_t SH_FLD_CNT_TRIG_FROM_AIB = 5581; // 6
+static const uint64_t SH_FLD_CNT_TRIG_FROM_AIB_LEN = 5582; // 6
+static const uint64_t SH_FLD_CNT_TRIG_FWD_TO_EQC = 5583; // 6
+static const uint64_t SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN = 5584; // 6
+static const uint64_t SH_FLD_CNT_USE_L2_DIVIDER_EN = 5585; // 12
+static const uint64_t SH_FLD_CNT_VICTIM_IS_1ST_USABLE = 5586; // 2
+static const uint64_t SH_FLD_CNT_VICTIM_IS_1ST_USABLE_LEN = 5587; // 2
+static const uint64_t SH_FLD_CNT_VICTIM_IS_FIRST_USABLE = 5588; // 2
+static const uint64_t SH_FLD_CNT_VICTIM_IS_FIRST_USABLE_LEN = 5589; // 2
+static const uint64_t SH_FLD_CNT_VICTIM_IS_LRU = 5590; // 4
+static const uint64_t SH_FLD_CNT_VICTIM_IS_LRU_LEN = 5591; // 4
+static const uint64_t SH_FLD_CNT_VP = 5592; // 1
+static const uint64_t SH_FLD_CNT_VPD_FETCH = 5593; // 1
+static const uint64_t SH_FLD_CNT_VPD_FETCH_LEN = 5594; // 1
+static const uint64_t SH_FLD_CNT_VPD_FETCH_REPLAY = 5595; // 1
+static const uint64_t SH_FLD_CNT_VPD_FETCH_REPLAY_LEN = 5596; // 1
+static const uint64_t SH_FLD_CNT_VPD_WB = 5597; // 1
+static const uint64_t SH_FLD_CNT_VPD_WB_LEN = 5598; // 1
+static const uint64_t SH_FLD_CNT_VP_LEN = 5599; // 1
+static const uint64_t SH_FLD_CNT_VRQ_CACHE_HIT = 5600; // 1
+static const uint64_t SH_FLD_CNT_VRQ_CACHE_HIT_LEN = 5601; // 1
+static const uint64_t SH_FLD_CNT_VRQ_PULL = 5602; // 1
+static const uint64_t SH_FLD_CNT_VRQ_PULL_LEN = 5603; // 1
+static const uint64_t SH_FLD_CNT_VRQ_PUSH_LOCAL = 5604; // 1
+static const uint64_t SH_FLD_CNT_VRQ_PUSH_LOCAL_LEN = 5605; // 1
+static const uint64_t SH_FLD_CNT_VRQ_PUSH_REMOTE = 5606; // 1
+static const uint64_t SH_FLD_CNT_VRQ_PUSH_REMOTE_LEN = 5607; // 1
+static const uint64_t SH_FLD_CNT_WAKEUP = 5608; // 1
+static const uint64_t SH_FLD_CNT_WAKEUP_LEN = 5609; // 1
+static const uint64_t SH_FLD_COARSE_CAL_STEP_SIZE = 5610; // 8
+static const uint64_t SH_FLD_COARSE_CAL_STEP_SIZE_LEN = 5611; // 8
+static const uint64_t SH_FLD_COARSE_DIR_ENABLE = 5612; // 2
+static const uint64_t SH_FLD_COARSE_DIR_SECTORS = 5613; // 2
+static const uint64_t SH_FLD_COARSE_RD = 5614; // 8
+static const uint64_t SH_FLD_COFSM_ADDR = 5615; // 12
+static const uint64_t SH_FLD_COHERENCY_ERROR = 5616; // 2
+static const uint64_t SH_FLD_COL4_BIT_MAP = 5617; // 8
+static const uint64_t SH_FLD_COL4_BIT_MAP_LEN = 5618; // 8
+static const uint64_t SH_FLD_COL5_BIT_MAP = 5619; // 8
+static const uint64_t SH_FLD_COL5_BIT_MAP_LEN = 5620; // 8
+static const uint64_t SH_FLD_COL6_BIT_MAP = 5621; // 8
+static const uint64_t SH_FLD_COL6_BIT_MAP_LEN = 5622; // 8
+static const uint64_t SH_FLD_COL7_BIT_MAP = 5623; // 8
+static const uint64_t SH_FLD_COL7_BIT_MAP_LEN = 5624; // 8
+static const uint64_t SH_FLD_COL8_BIT_MAP = 5625; // 8
+static const uint64_t SH_FLD_COL8_BIT_MAP_LEN = 5626; // 8
+static const uint64_t SH_FLD_COL9_BIT_MAP = 5627; // 8
+static const uint64_t SH_FLD_COL9_BIT_MAP_LEN = 5628; // 8
+static const uint64_t SH_FLD_COLLISION_MODES = 5629; // 4
+static const uint64_t SH_FLD_COLLISION_MODES_LEN = 5630; // 4
+static const uint64_t SH_FLD_COLLISON = 5631; // 1
+static const uint64_t SH_FLD_COMMAND_ADDRESS_TIMEOUT = 5632; // 2
+static const uint64_t SH_FLD_COMMAND_COMPLETE = 5633; // 1
+static const uint64_t SH_FLD_COMMAND_LIST_TIMEOUT = 5634; // 4
+static const uint64_t SH_FLD_COMMON_CLK_SB_PULSE_MODE = 5635; // 6
+static const uint64_t SH_FLD_COMMON_CLK_SB_PULSE_MODE_EN = 5636; // 6
+static const uint64_t SH_FLD_COMMON_CLK_SB_PULSE_MODE_LEN = 5637; // 6
+static const uint64_t SH_FLD_COMMON_CLK_SB_SPARE = 5638; // 6
+static const uint64_t SH_FLD_COMMON_CLK_SB_STRENGTH = 5639; // 6
+static const uint64_t SH_FLD_COMMON_CLK_SB_STRENGTH_LEN = 5640; // 6
+static const uint64_t SH_FLD_COMMON_CLK_SW_RESCLK = 5641; // 6
+static const uint64_t SH_FLD_COMMON_CLK_SW_RESCLK_LEN = 5642; // 6
+static const uint64_t SH_FLD_COMMON_CLK_SW_SPARE = 5643; // 6
+static const uint64_t SH_FLD_COMMON_FREEZE_MODE = 5644; // 7
+static const uint64_t SH_FLD_COMM_ACK = 5645; // 12
+static const uint64_t SH_FLD_COMM_NACK = 5646; // 12
+static const uint64_t SH_FLD_COMM_RECV = 5647; // 12
+static const uint64_t SH_FLD_COMM_RECVD = 5648; // 12
+static const uint64_t SH_FLD_COMM_RECV_LEN = 5649; // 12
+static const uint64_t SH_FLD_COMM_SEND = 5650; // 12
+static const uint64_t SH_FLD_COMM_SEND_ACK = 5651; // 12
+static const uint64_t SH_FLD_COMM_SEND_LEN = 5652; // 12
+static const uint64_t SH_FLD_COMM_SEND_NACK = 5653; // 12
+static const uint64_t SH_FLD_COMPLETE = 5654; // 8
+static const uint64_t SH_FLD_COMPLETE_LEN = 5655; // 8
+static const uint64_t SH_FLD_COMPLEX_FAULT = 5656; // 1
+static const uint64_t SH_FLD_COMPLEX_FAULT_MASK = 5657; // 1
+static const uint64_t SH_FLD_COMPLEX_NOTIFY = 5658; // 1
+static const uint64_t SH_FLD_COMPLEX_NOTIFY_MASK = 5659; // 1
+static const uint64_t SH_FLD_COMPRESSED_RSP_ENA = 5660; // 6
+static const uint64_t SH_FLD_COMP_CNT_LIMIT = 5661; // 24
+static const uint64_t SH_FLD_COMP_CNT_LIMIT_LEN = 5662; // 24
+static const uint64_t SH_FLD_COMP_MASK = 5663; // 4
+static const uint64_t SH_FLD_COMP_MASK_LEN = 5664; // 4
+static const uint64_t SH_FLD_COND1_SEL_A = 5665; // 86
+static const uint64_t SH_FLD_COND1_SEL_A_LEN = 5666; // 86
+static const uint64_t SH_FLD_COND1_SEL_B = 5667; // 86
+static const uint64_t SH_FLD_COND1_SEL_B_LEN = 5668; // 86
+static const uint64_t SH_FLD_COND2_SEL_A = 5669; // 86
+static const uint64_t SH_FLD_COND2_SEL_A_LEN = 5670; // 86
+static const uint64_t SH_FLD_COND2_SEL_B = 5671; // 86
+static const uint64_t SH_FLD_COND2_SEL_B_LEN = 5672; // 86
+static const uint64_t SH_FLD_COND3_ENABLE_RESET = 5673; // 86
+static const uint64_t SH_FLD_COND_STARTUP_TEST_FAIL = 5674; // 1
+static const uint64_t SH_FLD_CONFIG = 5675; // 1
+static const uint64_t SH_FLD_CONFIG1_RESERVED0 = 5676; // 3
+static const uint64_t SH_FLD_CONFIG1_RESERVED1 = 5677; // 15
+static const uint64_t SH_FLD_CONFIG1_RESERVED1_LEN = 5678; // 3
+static const uint64_t SH_FLD_CONFIG1_RESERVED2 = 5679; // 15
+static const uint64_t SH_FLD_CONFIG1_RESERVED2_LEN = 5680; // 3
+static const uint64_t SH_FLD_CONFIG_0 = 5681; // 5
+static const uint64_t SH_FLD_CONFIG_0_LEN = 5682; // 5
+static const uint64_t SH_FLD_CONFIG_1 = 5683; // 5
+static const uint64_t SH_FLD_CONFIG_1_LEN = 5684; // 5
+static const uint64_t SH_FLD_CONFIG_ADDR = 5685; // 48
+static const uint64_t SH_FLD_CONFIG_ADDR_LEN = 5686; // 48
+static const uint64_t SH_FLD_CONFIG_ADR_BAR_MODE = 5687; // 15
+static const uint64_t SH_FLD_CONFIG_ARB_NONCRR_SAFETY = 5688; // 12
+static const uint64_t SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN = 5689; // 12
+static const uint64_t SH_FLD_CONFIG_BRAZOS = 5690; // 1
+static const uint64_t SH_FLD_CONFIG_BRAZOS_MODE = 5691; // 15
+static const uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 5692; // 12
+static const uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 5693; // 12
+static const uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 5694; // 12
+static const uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 5695; // 12
+static const uint64_t SH_FLD_CONFIG_CHIP = 5696; // 48
+static const uint64_t SH_FLD_CONFIG_CHIP_LEN = 5697; // 48
+static const uint64_t SH_FLD_CONFIG_DCACHE_MODE = 5698; // 12
+static const uint64_t SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL = 5699; // 12
+static const uint64_t SH_FLD_CONFIG_DISABLE_G = 5700; // 12
+static const uint64_t SH_FLD_CONFIG_DISABLE_INJECT = 5701; // 12
+static const uint64_t SH_FLD_CONFIG_DISABLE_LN = 5702; // 12
+static const uint64_t SH_FLD_CONFIG_DISABLE_NN_RN = 5703; // 12
+static const uint64_t SH_FLD_CONFIG_DISABLE_PBM_ECC_COR = 5704; // 3
+static const uint64_t SH_FLD_CONFIG_DISABLE_VG_NOT_SYS = 5705; // 12
+static const uint64_t SH_FLD_CONFIG_ENABLE = 5706; // 48
+static const uint64_t SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC = 5707; // 12
+static const uint64_t SH_FLD_CONFIG_ENABLE_PBUS = 5708; // 12
+static const uint64_t SH_FLD_CONFIG_ENABLE_SNARF_CPM = 5709; // 12
+static const uint64_t SH_FLD_CONFIG_EPSILON_WLN_COUNT = 5710; // 12
+static const uint64_t SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN = 5711; // 12
+static const uint64_t SH_FLD_CONFIG_EVAPORATE_BY_LCO = 5712; // 12
+static const uint64_t SH_FLD_CONFIG_FORBID_MMIO_ATOMIC = 5713; // 12
+static const uint64_t SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 = 5714; // 12
+static const uint64_t SH_FLD_CONFIG_GEN_HEAD_DELAY = 5715; // 3
+static const uint64_t SH_FLD_CONFIG_GEN_HEAD_DELAY_LEN = 5716; // 3
+static const uint64_t SH_FLD_CONFIG_GPU0_ADDR = 5717; // 12
+static const uint64_t SH_FLD_CONFIG_GPU0_ADDR_LEN = 5718; // 12
+static const uint64_t SH_FLD_CONFIG_GPU0_CHIP = 5719; // 12
+static const uint64_t SH_FLD_CONFIG_GPU0_CHIP_LEN = 5720; // 12
+static const uint64_t SH_FLD_CONFIG_GPU0_ENABLE = 5721; // 12
+static const uint64_t SH_FLD_CONFIG_GPU0_GRANULE = 5722; // 12
+static const uint64_t SH_FLD_CONFIG_GPU0_GROUP = 5723; // 12
+static const uint64_t SH_FLD_CONFIG_GPU0_GROUP_LEN = 5724; // 12
+static const uint64_t SH_FLD_CONFIG_GPU0_MEMTYPE = 5725; // 12
+static const uint64_t SH_FLD_CONFIG_GPU0_MEMTYPE_LEN = 5726; // 12
+static const uint64_t SH_FLD_CONFIG_GPU0_MODE = 5727; // 12
+static const uint64_t SH_FLD_CONFIG_GPU0_MODE_LEN = 5728; // 12
+static const uint64_t SH_FLD_CONFIG_GPU0_RESERVED = 5729; // 12
+static const uint64_t SH_FLD_CONFIG_GPU0_SIZE = 5730; // 12
+static const uint64_t SH_FLD_CONFIG_GPU0_SIZE_LEN = 5731; // 12
+static const uint64_t SH_FLD_CONFIG_GPU1_ADDR = 5732; // 12
+static const uint64_t SH_FLD_CONFIG_GPU1_ADDR_LEN = 5733; // 12
+static const uint64_t SH_FLD_CONFIG_GPU1_CHIP = 5734; // 12
+static const uint64_t SH_FLD_CONFIG_GPU1_CHIP_LEN = 5735; // 12
+static const uint64_t SH_FLD_CONFIG_GPU1_ENABLE = 5736; // 12
+static const uint64_t SH_FLD_CONFIG_GPU1_GRANULE = 5737; // 12
+static const uint64_t SH_FLD_CONFIG_GPU1_GROUP = 5738; // 12
+static const uint64_t SH_FLD_CONFIG_GPU1_GROUP_LEN = 5739; // 12
+static const uint64_t SH_FLD_CONFIG_GPU1_MEMTYPE = 5740; // 12
+static const uint64_t SH_FLD_CONFIG_GPU1_MEMTYPE_LEN = 5741; // 12
+static const uint64_t SH_FLD_CONFIG_GPU1_MODE = 5742; // 12
+static const uint64_t SH_FLD_CONFIG_GPU1_MODE_LEN = 5743; // 12
+static const uint64_t SH_FLD_CONFIG_GPU1_RESERVED = 5744; // 12
+static const uint64_t SH_FLD_CONFIG_GPU1_SIZE = 5745; // 12
+static const uint64_t SH_FLD_CONFIG_GPU1_SIZE_LEN = 5746; // 12
+static const uint64_t SH_FLD_CONFIG_GROUP = 5747; // 48
+static const uint64_t SH_FLD_CONFIG_GROUP_LEN = 5748; // 48
+static const uint64_t SH_FLD_CONFIG_INC_PRI_MASK = 5749; // 12
+static const uint64_t SH_FLD_CONFIG_INC_PRI_MASK_LEN = 5750; // 12
+static const uint64_t SH_FLD_CONFIG_LAB_RANDOMIZE_PE_01 = 5751; // 3
+static const uint64_t SH_FLD_CONFIG_LAB_RANDOMIZE_PE_23 = 5752; // 3
+static const uint64_t SH_FLD_CONFIG_LEN = 5753; // 1
+static const uint64_t SH_FLD_CONFIG_MACH_CORRENAB = 5754; // 12
+static const uint64_t SH_FLD_CONFIG_MACH_INJECT_ENABLE1 = 5755; // 12
+static const uint64_t SH_FLD_CONFIG_MACH_INJECT_ENABLE2 = 5756; // 12
+static const uint64_t SH_FLD_CONFIG_MAX_MACHINES = 5757; // 12
+static const uint64_t SH_FLD_CONFIG_MAX_MACHINES_LEN = 5758; // 12
+static const uint64_t SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR = 5759; // 12
+static const uint64_t SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG = 5760; // 12
+static const uint64_t SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR = 5761; // 12
+static const uint64_t SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE = 5762; // 12
+static const uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA = 5763; // 12
+static const uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ = 5764; // 12
+static const uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_WRP = 5765; // 12
+static const uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_B = 5766; // 12
+static const uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_C = 5767; // 12
+static const uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM = 5768; // 12
+static const uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 5769; // 12
+static const uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_A = 5770; // 12
+static const uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_B = 5771; // 12
+static const uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_C = 5772; // 12
+static const uint64_t SH_FLD_CONFIG_MRBGP_DIS_DYN_ADJ = 5773; // 3
+static const uint64_t SH_FLD_CONFIG_MRBGP_DIS_DYN_LVL_ADJ = 5774; // 3
+static const uint64_t SH_FLD_CONFIG_MRBGP_DIV2_COUNT_AT_EXP = 5775; // 3
+static const uint64_t SH_FLD_CONFIG_MRBGP_MAX_LEVEL = 5776; // 3
+static const uint64_t SH_FLD_CONFIG_MRBGP_MAX_LEVEL_LEN = 5777; // 3
+static const uint64_t SH_FLD_CONFIG_MRBGP_THRESH1 = 5778; // 3
+static const uint64_t SH_FLD_CONFIG_MRBGP_THRESH1_LEN = 5779; // 3
+static const uint64_t SH_FLD_CONFIG_MRBGP_THRESH2 = 5780; // 3
+static const uint64_t SH_FLD_CONFIG_MRBGP_THRESH2_LEN = 5781; // 3
+static const uint64_t SH_FLD_CONFIG_MRBGP_TRACK_ALL = 5782; // 12
+static const uint64_t SH_FLD_CONFIG_MRBSP_DIS_DYN_ADJ = 5783; // 3
+static const uint64_t SH_FLD_CONFIG_MRBSP_DIS_DYN_LVL_ADJ = 5784; // 3
+static const uint64_t SH_FLD_CONFIG_MRBSP_DIV2_COUNT_AT_EXP = 5785; // 3
+static const uint64_t SH_FLD_CONFIG_MRBSP_MAX_LEVEL = 5786; // 3
+static const uint64_t SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN = 5787; // 3
+static const uint64_t SH_FLD_CONFIG_MRBSP_THRESH1 = 5788; // 3
+static const uint64_t SH_FLD_CONFIG_MRBSP_THRESH1_LEN = 5789; // 3
+static const uint64_t SH_FLD_CONFIG_MRBSP_THRESH2 = 5790; // 3
+static const uint64_t SH_FLD_CONFIG_MRBSP_THRESH2_LEN = 5791; // 3
+static const uint64_t SH_FLD_CONFIG_MRBSP_TRACK_ALL = 5792; // 12
+static const uint64_t SH_FLD_CONFIG_OPT_SNOOP_CP = 5793; // 12
+static const uint64_t SH_FLD_CONFIG_P9P9_MODE = 5794; // 12
+static const uint64_t SH_FLD_CONFIG_PARITY = 5795; // 43
+static const uint64_t SH_FLD_CONFIG_PCKT_BLK_PRB = 5796; // 12
+static const uint64_t SH_FLD_CONFIG_PRB0 = 5797; // 24
+static const uint64_t SH_FLD_CONFIG_PRB0_LEN = 5798; // 24
+static const uint64_t SH_FLD_CONFIG_PRB1 = 5799; // 24
+static const uint64_t SH_FLD_CONFIG_PRB1_LEN = 5800; // 24
+static const uint64_t SH_FLD_CONFIG_PREALLOC2_PRB0 = 5801; // 12
+static const uint64_t SH_FLD_CONFIG_PREALLOC2_PRB1 = 5802; // 12
+static const uint64_t SH_FLD_CONFIG_PREALLOC2_REQ0 = 5803; // 12
+static const uint64_t SH_FLD_CONFIG_PREALLOC2_REQ1 = 5804; // 12
+static const uint64_t SH_FLD_CONFIG_PREALLOC2_XATS = 5805; // 12
+static const uint64_t SH_FLD_CONFIG_PWR0 = 5806; // 24
+static const uint64_t SH_FLD_CONFIG_PWR0_LEN = 5807; // 24
+static const uint64_t SH_FLD_CONFIG_PWR1 = 5808; // 24
+static const uint64_t SH_FLD_CONFIG_PWR1_LEN = 5809; // 24
+static const uint64_t SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK = 5810; // 12
+static const uint64_t SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 5811; // 12
+static const uint64_t SH_FLD_CONFIG_REQ0 = 5812; // 24
+static const uint64_t SH_FLD_CONFIG_REQ0_LEN = 5813; // 24
+static const uint64_t SH_FLD_CONFIG_REQ1 = 5814; // 24
+static const uint64_t SH_FLD_CONFIG_REQ1_LEN = 5815; // 24
+static const uint64_t SH_FLD_CONFIG_RESERVED4 = 5816; // 12
+static const uint64_t SH_FLD_CONFIG_RSI_CORRENAB = 5817; // 12
+static const uint64_t SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 5818; // 12
+static const uint64_t SH_FLD_CONFIG_RSI_INJECT_ENABLE1 = 5819; // 12
+static const uint64_t SH_FLD_CONFIG_RSI_INJECT_ENABLE2 = 5820; // 12
+static const uint64_t SH_FLD_CONFIG_RXO_CORRENAB = 5821; // 12
+static const uint64_t SH_FLD_CONFIG_RXO_INJECT_ENABLE1 = 5822; // 12
+static const uint64_t SH_FLD_CONFIG_RXO_INJECT_ENABLE2 = 5823; // 12
+static const uint64_t SH_FLD_CONFIG_SCALE_RPT_HANG_DATA = 5824; // 12
+static const uint64_t SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN = 5825; // 12
+static const uint64_t SH_FLD_CONFIG_SCALE_RPT_HANG_POLL = 5826; // 12
+static const uint64_t SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN = 5827; // 12
+static const uint64_t SH_FLD_CONFIG_SKIP_G = 5828; // 12
+static const uint64_t SH_FLD_CONFIG_SYNC_WAIT = 5829; // 1
+static const uint64_t SH_FLD_CONFIG_SYNC_WAIT_LEN = 5830; // 1
+static const uint64_t SH_FLD_CONFIG_XATS = 5831; // 24
+static const uint64_t SH_FLD_CONFIG_XATS_LEN = 5832; // 24
+static const uint64_t SH_FLD_CONFIRMED = 5833; // 64
+static const uint64_t SH_FLD_CONFLICT = 5834; // 2
+static const uint64_t SH_FLD_CONG = 5835; // 1
+static const uint64_t SH_FLD_CONG_LEN = 5836; // 1
+static const uint64_t SH_FLD_CONSEQ_PASS = 5837; // 8
+static const uint64_t SH_FLD_CONSEQ_PASS_LEN = 5838; // 8
+static const uint64_t SH_FLD_CONSUMED_BUF_COUNT = 5839; // 1
+static const uint64_t SH_FLD_CONSUMED_BUF_COUNT_LEN = 5840; // 1
+static const uint64_t SH_FLD_CONTENT = 5841; // 3
+static const uint64_t SH_FLD_CONTENT_LEN = 5842; // 3
+static const uint64_t SH_FLD_CONTINUOUS = 5843; // 4
+static const uint64_t SH_FLD_CONTROL = 5844; // 15
+static const uint64_t SH_FLD_CONTROL_ERR = 5845; // 12
+static const uint64_t SH_FLD_CONTROL_LEN = 5846; // 15
+static const uint64_t SH_FLD_CONTROL_N = 5847; // 2
+static const uint64_t SH_FLD_CONVERGED_END_COUNT = 5848; // 6
+static const uint64_t SH_FLD_CONVERGED_END_COUNT_LEN = 5849; // 6
+static const uint64_t SH_FLD_COPY_CKE_TO_SPARE_CKE = 5850; // 2
+static const uint64_t SH_FLD_COPY_LENGTH = 5851; // 2
+static const uint64_t SH_FLD_COPY_LENGTH_LEN = 5852; // 2
+static const uint64_t SH_FLD_CORE0_REQ_ACTIVE = 5853; // 12
+static const uint64_t SH_FLD_CORE1_REQ_ACTIVE = 5854; // 12
+static const uint64_t SH_FLD_COREID = 5855; // 1
+static const uint64_t SH_FLD_COREID_LEN = 5856; // 1
+static const uint64_t SH_FLD_CORES_ENABLED_0_23 = 5857; // 1
+static const uint64_t SH_FLD_CORES_ENABLED_0_23_LEN = 5858; // 1
+static const uint64_t SH_FLD_CORE_CHECKSTOP = 5859; // 12
+static const uint64_t SH_FLD_CORE_CONFIG = 5860; // 2
+static const uint64_t SH_FLD_CORE_CONFIG_LEN = 5861; // 2
+static const uint64_t SH_FLD_CORE_DROPOUT_ENABLE = 5862; // 12
+static const uint64_t SH_FLD_CORE_DROPOUT_ENABLE_LEN = 5863; // 12
+static const uint64_t SH_FLD_CORE_EXT_INTR = 5864; // 1
+static const uint64_t SH_FLD_CORE_LIMIT = 5865; // 24
+static const uint64_t SH_FLD_CORE_LIMIT_LEN = 5866; // 24
+static const uint64_t SH_FLD_CORE_OR_SNP_REQ_ACTIVE = 5867; // 12
+static const uint64_t SH_FLD_CORE_RAS0_TRIG_SEL = 5868; // 43
+static const uint64_t SH_FLD_CORE_RAS0_TRIG_SEL_LEN = 5869; // 43
+static const uint64_t SH_FLD_CORE_RAS1_TRIG_SEL = 5870; // 43
+static const uint64_t SH_FLD_CORE_RAS1_TRIG_SEL_LEN = 5871; // 43
+static const uint64_t SH_FLD_CORE_RESET = 5872; // 1
+static const uint64_t SH_FLD_CORE_STEP = 5873; // 1
+static const uint64_t SH_FLD_CORE_STEP_SYNC_TX_ENABLE = 5874; // 1
+static const uint64_t SH_FLD_CORE_STEP_SYNC_TX_SYNC_DISABLE = 5875; // 1
+static const uint64_t SH_FLD_CORE_STEP_SYNC_TX_TRIGGER = 5876; // 1
+static const uint64_t SH_FLD_CORR_DIS_BR = 5877; // 3
+static const uint64_t SH_FLD_CORR_DIS_IR = 5878; // 3
+static const uint64_t SH_FLD_CORR_DIS_OR = 5879; // 3
+static const uint64_t SH_FLD_CORR_DIS_PR = 5880; // 3
+static const uint64_t SH_FLD_CORR_DIS_PT = 5881; // 3
+static const uint64_t SH_FLD_CORR_ERR = 5882; // 1
+static const uint64_t SH_FLD_COUNT = 5883; // 44
+static const uint64_t SH_FLD_COUNTER = 5884; // 43
+static const uint64_t SH_FLD_COUNTER0 = 5885; // 16
+static const uint64_t SH_FLD_COUNTER0_LEN = 5886; // 16
+static const uint64_t SH_FLD_COUNTER1 = 5887; // 16
+static const uint64_t SH_FLD_COUNTER1_LEN = 5888; // 16
+static const uint64_t SH_FLD_COUNTER2 = 5889; // 16
+static const uint64_t SH_FLD_COUNTER2_LEN = 5890; // 16
+static const uint64_t SH_FLD_COUNTER3 = 5891; // 16
+static const uint64_t SH_FLD_COUNTER3_LEN = 5892; // 16
+static const uint64_t SH_FLD_COUNTERA_0 = 5893; // 2
+static const uint64_t SH_FLD_COUNTERA_0_LEN = 5894; // 2
+static const uint64_t SH_FLD_COUNTERA_1 = 5895; // 2
+static const uint64_t SH_FLD_COUNTERA_1_LEN = 5896; // 2
+static const uint64_t SH_FLD_COUNTERA_2 = 5897; // 2
+static const uint64_t SH_FLD_COUNTERA_2_LEN = 5898; // 2
+static const uint64_t SH_FLD_COUNTERA_3 = 5899; // 2
+static const uint64_t SH_FLD_COUNTERA_3_LEN = 5900; // 2
+static const uint64_t SH_FLD_COUNTERB_0 = 5901; // 2
+static const uint64_t SH_FLD_COUNTERB_0_LEN = 5902; // 2
+static const uint64_t SH_FLD_COUNTERB_1 = 5903; // 2
+static const uint64_t SH_FLD_COUNTERB_1_LEN = 5904; // 2
+static const uint64_t SH_FLD_COUNTERB_2 = 5905; // 2
+static const uint64_t SH_FLD_COUNTERB_2_LEN = 5906; // 2
+static const uint64_t SH_FLD_COUNTERB_3 = 5907; // 2
+static const uint64_t SH_FLD_COUNTERB_3_LEN = 5908; // 2
+static const uint64_t SH_FLD_COUNTER_LEN = 5909; // 43
+static const uint64_t SH_FLD_COUNTER_LOAD_FLAG = 5910; // 2
+static const uint64_t SH_FLD_COUNTER_LOAD_VALUE = 5911; // 2
+static const uint64_t SH_FLD_COUNTER_LOAD_VALUE_LEN = 5912; // 2
+static const uint64_t SH_FLD_COUNTER_VALUE = 5913; // 1
+static const uint64_t SH_FLD_COUNTER_VALUE_LEN = 5914; // 1
+static const uint64_t SH_FLD_COUNT_0_47 = 5915; // 7
+static const uint64_t SH_FLD_COUNT_0_47_LEN = 5916; // 7
+static const uint64_t SH_FLD_COUNT_47 = 5917; // 1
+static const uint64_t SH_FLD_COUNT_47_LEN = 5918; // 1
+static const uint64_t SH_FLD_COUNT_LEN = 5919; // 44
+static const uint64_t SH_FLD_COUNT_STATE_MASK = 5920; // 43
+static const uint64_t SH_FLD_COURSE_DIR_FLUSH_FAILED = 5921; // 2
+static const uint64_t SH_FLD_CO_CRESP_ACK_DEAD = 5922; // 12
+static const uint64_t SH_FLD_CO_MACHINE_HANG = 5923; // 12
+static const uint64_t SH_FLD_CO_PROT_ERR_CHK_DIS = 5924; // 1
+static const uint64_t SH_FLD_CO_PSH_RECEIVED_PB_CRESP_ADR_ERR = 5925; // 12
+static const uint64_t SH_FLD_CO_SM_CTL_ERR_DET = 5926; // 1
+static const uint64_t SH_FLD_CO_TIMEOUT_CHK_DIS = 5927; // 1
+static const uint64_t SH_FLD_CO_TIMEOUT_ERR_DET = 5928; // 1
+static const uint64_t SH_FLD_CO_UNSOLICITED_CRESP = 5929; // 12
+static const uint64_t SH_FLD_CP = 5930; // 2
+static const uint64_t SH_FLD_CP0_LXSTOP_ERR_DET = 5931; // 1
+static const uint64_t SH_FLD_CP1_LXSTOP_ERR_DET = 5932; // 1
+static const uint64_t SH_FLD_CPG = 5933; // 8
+static const uint64_t SH_FLD_CPHA = 5934; // 1
+static const uint64_t SH_FLD_CPISEL = 5935; // 20
+static const uint64_t SH_FLD_CPISEL_LEN = 5936; // 20
+static const uint64_t SH_FLD_CPI_TYPE = 5937; // 12
+static const uint64_t SH_FLD_CPI_TYPE_LEN = 5938; // 12
+static const uint64_t SH_FLD_CPLITE = 5939; // 2
+static const uint64_t SH_FLD_CPLITE_LEN = 5940; // 2
+static const uint64_t SH_FLD_CPLTMASK0 = 5941; // 43
+static const uint64_t SH_FLD_CPLTMASK0_LEN = 5942; // 43
+static const uint64_t SH_FLD_CPLT_DCTRL = 5943; // 43
+static const uint64_t SH_FLD_CPLT_RCTRL = 5944; // 43
+static const uint64_t SH_FLD_CPM_CAL_SET = 5945; // 43
+static const uint64_t SH_FLD_CPOL = 5946; // 1
+static const uint64_t SH_FLD_CPS = 5947; // 1
+static const uint64_t SH_FLD_CPS_LEN = 5948; // 1
+static const uint64_t SH_FLD_CP_LEN = 5949; // 2
+static const uint64_t SH_FLD_CP_RETRY_THRESH = 5950; // 4
+static const uint64_t SH_FLD_CP_RETRY_THRESH_LEN = 5951; // 4
+static const uint64_t SH_FLD_CQ_CERR_BIT10 = 5952; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT11 = 5953; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT12 = 5954; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT13 = 5955; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT14 = 5956; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT15 = 5957; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT16 = 5958; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT17 = 5959; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT18 = 5960; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT19 = 5961; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT20 = 5962; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT21 = 5963; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT22 = 5964; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT23 = 5965; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT24 = 5966; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT25 = 5967; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT26 = 5968; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT27 = 5969; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT28 = 5970; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT29 = 5971; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT30 = 5972; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT31 = 5973; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT32 = 5974; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT33 = 5975; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT34 = 5976; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT35 = 5977; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT36 = 5978; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT37 = 5979; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT38 = 5980; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT39 = 5981; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT4 = 5982; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT5 = 5983; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT6 = 5984; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT7 = 5985; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT8 = 5986; // 1
+static const uint64_t SH_FLD_CQ_CERR_BIT9 = 5987; // 1
+static const uint64_t SH_FLD_CQ_CERR_RESET = 5988; // 1
+static const uint64_t SH_FLD_CQ_DRAIN_THRESHOLD = 5989; // 1
+static const uint64_t SH_FLD_CQ_DRAIN_THRESHOLD_LEN = 5990; // 1
+static const uint64_t SH_FLD_CQ_ECC_CE_ERROR = 5991; // 2
+static const uint64_t SH_FLD_CQ_ECC_SUE_ERROR = 5992; // 2
+static const uint64_t SH_FLD_CQ_ECC_UE_ERROR = 5993; // 2
+static const uint64_t SH_FLD_CQ_FILL_THRESHOLD = 5994; // 1
+static const uint64_t SH_FLD_CQ_FILL_THRESHOLD_LEN = 5995; // 1
+static const uint64_t SH_FLD_CQ_LFSR_RESEED_EN = 5996; // 1
+static const uint64_t SH_FLD_CQ_LOGIC_HW_ERROR = 5997; // 2
+static const uint64_t SH_FLD_CQ_PB_LINK_ABORT = 5998; // 2
+static const uint64_t SH_FLD_CQ_PB_MASTER_FSM_HANG = 5999; // 2
+static const uint64_t SH_FLD_CQ_PB_OB_CE_ERROR = 6000; // 2
+static const uint64_t SH_FLD_CQ_PB_OB_UE_ERROR = 6001; // 2
+static const uint64_t SH_FLD_CQ_PB_PARITY_ERROR = 6002; // 2
+static const uint64_t SH_FLD_CQ_PB_RD_ADDR_ERROR = 6003; // 2
+static const uint64_t SH_FLD_CQ_PB_RD_LINK_ERROR = 6004; // 2
+static const uint64_t SH_FLD_CQ_PB_WR_ADDR_ERROR = 6005; // 2
+static const uint64_t SH_FLD_CQ_PB_WR_LINK_ERROR = 6006; // 2
+static const uint64_t SH_FLD_CQ_READ_RTY_RATIO = 6007; // 1
+static const uint64_t SH_FLD_CQ_READ_RTY_RATIO_LEN = 6008; // 1
+static const uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_HI = 6009; // 1
+static const uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_HI_LEN = 6010; // 1
+static const uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_LO = 6011; // 1
+static const uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_LO_LEN = 6012; // 1
+static const uint64_t SH_FLD_CQ_TRACE_INT_DATA_HI = 6013; // 1
+static const uint64_t SH_FLD_CQ_TRACE_INT_DATA_LO = 6014; // 1
+static const uint64_t SH_FLD_CQ_TRACE_INT_TRIG_01 = 6015; // 1
+static const uint64_t SH_FLD_CQ_TRACE_INT_TRIG_23 = 6016; // 1
+static const uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_01 = 6017; // 1
+static const uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_01_LEN = 6018; // 1
+static const uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_23 = 6019; // 1
+static const uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_23_LEN = 6020; // 1
+static const uint64_t SH_FLD_CR0_ATAG_PERR = 6021; // 1
+static const uint64_t SH_FLD_CR0_TTAG_PERR = 6022; // 1
+static const uint64_t SH_FLD_CR1_ATAG_PERR = 6023; // 1
+static const uint64_t SH_FLD_CR1_TTAG_PERR = 6024; // 1
+static const uint64_t SH_FLD_CR2_ATAG_PERR = 6025; // 1
+static const uint64_t SH_FLD_CR2_TTAG_PERR = 6026; // 1
+static const uint64_t SH_FLD_CR3_ATAG_PERR = 6027; // 1
+static const uint64_t SH_FLD_CR3_TTAG_PERR = 6028; // 1
+static const uint64_t SH_FLD_CRB_ECC_SUE = 6029; // 1
+static const uint64_t SH_FLD_CRB_ECC_UE = 6030; // 1
+static const uint64_t SH_FLD_CRB_READS_ENBL = 6031; // 1
+static const uint64_t SH_FLD_CRB_READS_HALTED = 6032; // 1
+static const uint64_t SH_FLD_CRC_LANE_ID = 6033; // 5
+static const uint64_t SH_FLD_CRC_MODE = 6034; // 2
+static const uint64_t SH_FLD_CRD_INIT_REQUEST = 6035; // 1
+static const uint64_t SH_FLD_CRD_REQUEST = 6036; // 1
+static const uint64_t SH_FLD_CREDIT_CUR = 6037; // 36
+static const uint64_t SH_FLD_CREDIT_CUR_LEN = 6038; // 36
+static const uint64_t SH_FLD_CREDIT_MAX = 6039; // 36
+static const uint64_t SH_FLD_CREDIT_MAX_LEN = 6040; // 36
+static const uint64_t SH_FLD_CREDIT_RCV_CUR = 6041; // 12
+static const uint64_t SH_FLD_CREDIT_RCV_CUR_LEN = 6042; // 12
+static const uint64_t SH_FLD_CREDIT_RCV_UPD = 6043; // 12
+static const uint64_t SH_FLD_CREDIT_SEND = 6044; // 36
+static const uint64_t SH_FLD_CREDIT_SEND_LEN = 6045; // 36
+static const uint64_t SH_FLD_CREDIT_TIMEOUT_ERRHOLD = 6046; // 2
+static const uint64_t SH_FLD_CREDIT_UPD = 6047; // 36
+static const uint64_t SH_FLD_CREDIT_UPDATE_PENDING = 6048; // 6
+static const uint64_t SH_FLD_CREQ0 = 6049; // 12
+static const uint64_t SH_FLD_CREQ1 = 6050; // 12
+static const uint64_t SH_FLD_CREQ_AE_ALWAYS = 6051; // 6
+static const uint64_t SH_FLD_CREQ_BE_128 = 6052; // 6
+static const uint64_t SH_FLD_CRESP = 6053; // 24
+static const uint64_t SH_FLD_CRESP_0_4 = 6054; // 1
+static const uint64_t SH_FLD_CRESP_0_4_LEN = 6055; // 1
+static const uint64_t SH_FLD_CRESP_ADDR = 6056; // 2
+static const uint64_t SH_FLD_CRESP_ADDR_ERROR = 6057; // 2
+static const uint64_t SH_FLD_CRESP_ERROR = 6058; // 2
+static const uint64_t SH_FLD_CRESP_HANG = 6059; // 1
+static const uint64_t SH_FLD_CRESP_LEN = 6060; // 24
+static const uint64_t SH_FLD_CRITICAL_INTERRUPT = 6061; // 1
+static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_1_A = 6062; // 86
+static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN = 6063; // 86
+static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_1_B = 6064; // 86
+static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN = 6065; // 86
+static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_A = 6066; // 86
+static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_A_LEN = 6067; // 86
+static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_B = 6068; // 86
+static const uint64_t SH_FLD_CROSS_COUPLE_SELECT_B_LEN = 6069; // 86
+static const uint64_t SH_FLD_CR_ATAG_PAR = 6070; // 1
+static const uint64_t SH_FLD_CR_TTAG_PAR = 6071; // 1
+static const uint64_t SH_FLD_CS = 6072; // 6
+static const uint64_t SH_FLD_CS0_INIT_CAL_VALUE = 6073; // 8
+static const uint64_t SH_FLD_CS1_INIT_CAL_VALUE = 6074; // 8
+static const uint64_t SH_FLD_CS2_INIT_CAL_VALUE = 6075; // 8
+static const uint64_t SH_FLD_CS3_INIT_CAL_VALUE = 6076; // 8
+static const uint64_t SH_FLD_CS4_INIT_CAL_VALUE = 6077; // 8
+static const uint64_t SH_FLD_CS5_INIT_CAL_VALUE = 6078; // 8
+static const uint64_t SH_FLD_CS6_INIT_CAL_VALUE = 6079; // 8
+static const uint64_t SH_FLD_CS7_INIT_CAL_VALUE = 6080; // 8
+static const uint64_t SH_FLD_CSEL = 6081; // 10
+static const uint64_t SH_FLD_CSEL_LEN = 6082; // 10
+static const uint64_t SH_FLD_CS_LEN = 6083; // 6
+static const uint64_t SH_FLD_CTL = 6084; // 1
+static const uint64_t SH_FLD_CTLE_GAIN_MAX = 6085; // 6
+static const uint64_t SH_FLD_CTLE_GAIN_MAX_LEN = 6086; // 6
+static const uint64_t SH_FLD_CTLE_UPDATE_MODE = 6087; // 6
+static const uint64_t SH_FLD_CTLR_HP_THRESH = 6088; // 3
+static const uint64_t SH_FLD_CTLR_HP_THRESH_LEN = 6089; // 3
+static const uint64_t SH_FLD_CTLW_HP_THRESH = 6090; // 3
+static const uint64_t SH_FLD_CTLW_HP_THRESH_LEN = 6091; // 3
+static const uint64_t SH_FLD_CTL_ARRAY_CE = 6092; // 1
+static const uint64_t SH_FLD_CTL_ARRAY_UE = 6093; // 1
+static const uint64_t SH_FLD_CTL_CLKDIST_PDWN = 6094; // 6
+static const uint64_t SH_FLD_CTL_FWD_PROGRESS_ERR = 6095; // 1
+static const uint64_t SH_FLD_CTL_LEN = 6096; // 1
+static const uint64_t SH_FLD_CTL_LOGIC_ERR = 6097; // 1
+static const uint64_t SH_FLD_CTL_MMIO_ST_DATA_UE = 6098; // 1
+static const uint64_t SH_FLD_CTL_NVL_CFG_ERR = 6099; // 1
+static const uint64_t SH_FLD_CTL_NVL_FATAL_ERR = 6100; // 1
+static const uint64_t SH_FLD_CTL_PBUS_CONFIG_ERR = 6101; // 1
+static const uint64_t SH_FLD_CTL_PBUS_FATAL_ERR = 6102; // 1
+static const uint64_t SH_FLD_CTL_PBUS_PERR = 6103; // 1
+static const uint64_t SH_FLD_CTL_PBUS_RECOV_ERR = 6104; // 1
+static const uint64_t SH_FLD_CTL_PEF = 6105; // 1
+static const uint64_t SH_FLD_CTL_PEST_DIS = 6106; // 1
+static const uint64_t SH_FLD_CTL_RING_ERR = 6107; // 1
+static const uint64_t SH_FLD_CTL_RSVD_15 = 6108; // 1
+static const uint64_t SH_FLD_CTL_SM_0 = 6109; // 6
+static const uint64_t SH_FLD_CTL_SM_1 = 6110; // 6
+static const uint64_t SH_FLD_CTL_SM_2 = 6111; // 6
+static const uint64_t SH_FLD_CTL_SM_3 = 6112; // 6
+static const uint64_t SH_FLD_CTL_SM_4 = 6113; // 6
+static const uint64_t SH_FLD_CTL_SM_5 = 6114; // 6
+static const uint64_t SH_FLD_CTL_SM_6 = 6115; // 6
+static const uint64_t SH_FLD_CTL_SM_7 = 6116; // 6
+static const uint64_t SH_FLD_CTL_TICK = 6117; // 12
+static const uint64_t SH_FLD_CTL_TICK_LEN = 6118; // 12
+static const uint64_t SH_FLD_CTL_TRACE_EN = 6119; // 1
+static const uint64_t SH_FLD_CTL_TRACE_SEL = 6120; // 1
+static const uint64_t SH_FLD_CTR = 6121; // 8
+static const uint64_t SH_FLD_CTRLR_PERR_ESR = 6122; // 1
+static const uint64_t SH_FLD_CTRL_BUSY = 6123; // 1
+static const uint64_t SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC = 6124; // 43
+static const uint64_t SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC = 6125; // 43
+static const uint64_t SH_FLD_CTRL_CC_DCTEST_DC = 6126; // 43
+static const uint64_t SH_FLD_CTRL_CC_FLUSHMODE_INH_DC = 6127; // 43
+static const uint64_t SH_FLD_CTRL_CC_FORCE_ALIGN_DC = 6128; // 43
+static const uint64_t SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC = 6129; // 43
+static const uint64_t SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC = 6130; // 43
+static const uint64_t SH_FLD_CTRL_CC_OTP_PRGMODE_DC = 6131; // 43
+static const uint64_t SH_FLD_CTRL_CC_PIN_LBIST_DC = 6132; // 43
+static const uint64_t SH_FLD_CTRL_CC_SCAN_PROTECT_DC = 6133; // 43
+static const uint64_t SH_FLD_CTRL_CC_SDIS_DC_N = 6134; // 43
+static const uint64_t SH_FLD_CTRL_CC_SSS_CALIBRATE_DC = 6135; // 43
+static const uint64_t SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC = 6136; // 43
+static const uint64_t SH_FLD_CTRL_MISC_CLKDIV_SEL_DC = 6137; // 43
+static const uint64_t SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN = 6138; // 43
+static const uint64_t SH_FLD_CTRL_MISC_PROBE0_SEL_DC = 6139; // 43
+static const uint64_t SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN = 6140; // 43
+static const uint64_t SH_FLD_CTRL_MISC_PROBE1_SEL_DC = 6141; // 43
+static const uint64_t SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN = 6142; // 43
+static const uint64_t SH_FLD_CTRL_MISC_PROBE2_SEL_DC = 6143; // 43
+static const uint64_t SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN = 6144; // 43
+static const uint64_t SH_FLD_CTRL_MISC_PROBE3_SEL_DC = 6145; // 43
+static const uint64_t SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN = 6146; // 43
+static const uint64_t SH_FLD_CTRL_PARITY = 6147; // 43
+static const uint64_t SH_FLD_CTR_VREF_COUNTER_RESET_VAL = 6148; // 8
+static const uint64_t SH_FLD_CTR_VREF_COUNTER_RESET_VAL_LEN = 6149; // 8
+static const uint64_t SH_FLD_CT_COMPARE_VECTOR = 6150; // 2
+static const uint64_t SH_FLD_CT_COMPARE_VECTOR_LEN = 6151; // 2
+static const uint64_t SH_FLD_CURRENT_OPCG_MODE = 6152; // 43
+static const uint64_t SH_FLD_CURRENT_OPCG_MODE_LEN = 6153; // 43
+static const uint64_t SH_FLD_CUR_RD_ADDR = 6154; // 6
+static const uint64_t SH_FLD_CUR_RD_ADDR_LEN = 6155; // 6
+static const uint64_t SH_FLD_CUSTOM_INIT_WRITE = 6156; // 8
+static const uint64_t SH_FLD_CUSTOM_RD = 6157; // 8
+static const uint64_t SH_FLD_CUSTOM_WR = 6158; // 8
+static const uint64_t SH_FLD_CW_MIRROR = 6159; // 8
+static const uint64_t SH_FLD_CW_TYPE = 6160; // 12
+static const uint64_t SH_FLD_CW_TYPE_LEN = 6161; // 12
+static const uint64_t SH_FLD_CXACQPB_MUX_ECC_CE_ERRHOLD = 6162; // 2
+static const uint64_t SH_FLD_CXACQPB_MUX_ECC_UE_ERRHOLD = 6163; // 2
+static const uint64_t SH_FLD_CYCLECNT = 6164; // 3
+static const uint64_t SH_FLD_CYCLECNT_LEN = 6165; // 3
+static const uint64_t SH_FLD_CYCLES = 6166; // 12
+static const uint64_t SH_FLD_CYCLES_LEN = 6167; // 12
+static const uint64_t SH_FLD_CYCLE_COUNT = 6168; // 24
+static const uint64_t SH_FLD_CYCLE_COUNT_LEN = 6169; // 24
+static const uint64_t SH_FLD_C_ERR_RPT_HOLD_DATA = 6170; // 2
+static const uint64_t SH_FLD_C_ERR_RPT_HOLD_DATA_LEN = 6171; // 2
+static const uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT = 6172; // 4
+static const uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT_LEN = 6173; // 4
+static const uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT = 6174; // 4
+static const uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT_LEN = 6175; // 4
+static const uint64_t SH_FLD_DACTEST_HLMT = 6176; // 6
+static const uint64_t SH_FLD_DACTEST_HLMT_LEN = 6177; // 6
+static const uint64_t SH_FLD_DACTEST_LLMT = 6178; // 6
+static const uint64_t SH_FLD_DACTEST_LLMT_LEN = 6179; // 6
+static const uint64_t SH_FLD_DACTEST_RESET = 6180; // 6
+static const uint64_t SH_FLD_DACTEST_START = 6181; // 6
+static const uint64_t SH_FLD_DAC_BO_CFG = 6182; // 6
+static const uint64_t SH_FLD_DAC_BO_CFG_LEN = 6183; // 6
+static const uint64_t SH_FLD_DARN_ADDR_ERR = 6184; // 12
+static const uint64_t SH_FLD_DARN_DATA_TIMEOUT = 6185; // 12
+static const uint64_t SH_FLD_DARN_EN_ERR = 6186; // 12
+static const uint64_t SH_FLD_DAT0 = 6187; // 1
+static const uint64_t SH_FLD_DAT0_LEN = 6188; // 1
+static const uint64_t SH_FLD_DAT1 = 6189; // 1
+static const uint64_t SH_FLD_DAT1_LEN = 6190; // 1
+static const uint64_t SH_FLD_DATA = 6191; // 437
+static const uint64_t SH_FLD_DATA0 = 6192; // 6
+static const uint64_t SH_FLD_DATA0_LEN = 6193; // 6
+static const uint64_t SH_FLD_DATA1 = 6194; // 6
+static const uint64_t SH_FLD_DATA1_LEN = 6195; // 6
+static const uint64_t SH_FLD_DATA2 = 6196; // 6
+static const uint64_t SH_FLD_DATA2_LEN = 6197; // 6
+static const uint64_t SH_FLD_DATA_0_63 = 6198; // 2
+static const uint64_t SH_FLD_DATA_0_63_LEN = 6199; // 2
+static const uint64_t SH_FLD_DATA_64_79 = 6200; // 2
+static const uint64_t SH_FLD_DATA_64_79_LEN = 6201; // 2
+static const uint64_t SH_FLD_DATA_ARB_LFSR_CONFIG = 6202; // 1
+static const uint64_t SH_FLD_DATA_ARB_LFSR_CONFIG_LEN = 6203; // 1
+static const uint64_t SH_FLD_DATA_BUFFER = 6204; // 43
+static const uint64_t SH_FLD_DATA_COMPARE_BURST_SEL = 6205; // 2
+static const uint64_t SH_FLD_DATA_COMPARE_BURST_SEL_LEN = 6206; // 2
+static const uint64_t SH_FLD_DATA_DLY = 6207; // 1
+static const uint64_t SH_FLD_DATA_DLY_LEN = 6208; // 1
+static const uint64_t SH_FLD_DATA_HANG_DETECTED = 6209; // 2
+static const uint64_t SH_FLD_DATA_HANG_POLL_SCALE = 6210; // 2
+static const uint64_t SH_FLD_DATA_HANG_POLL_SCALE_LEN = 6211; // 2
+static const uint64_t SH_FLD_DATA_LEN = 6212; // 437
+static const uint64_t SH_FLD_DATA_MUX4_1MODE = 6213; // 8
+static const uint64_t SH_FLD_DATA_PARITY_ERR = 6214; // 4
+static const uint64_t SH_FLD_DATA_PIPE_CLR_ON_READ_MODE = 6215; // 6
+static const uint64_t SH_FLD_DATA_POISON_SUE_ENA = 6216; // 6
+static const uint64_t SH_FLD_DATA_POLL_PULSE_DIV = 6217; // 12
+static const uint64_t SH_FLD_DATA_POLL_PULSE_DIV_LEN = 6218; // 12
+static const uint64_t SH_FLD_DATA_REG0 = 6219; // 8
+static const uint64_t SH_FLD_DATA_REG0_LEN = 6220; // 8
+static const uint64_t SH_FLD_DATA_REG1 = 6221; // 8
+static const uint64_t SH_FLD_DATA_REG1_LEN = 6222; // 8
+static const uint64_t SH_FLD_DATA_REG_0_31 = 6223; // 1
+static const uint64_t SH_FLD_DATA_REG_0_31_LEN = 6224; // 1
+static const uint64_t SH_FLD_DATA_REQUEST_0 = 6225; // 4
+static const uint64_t SH_FLD_DATA_REQUEST_1 = 6226; // 2
+static const uint64_t SH_FLD_DATA_REQUEST_2 = 6227; // 2
+static const uint64_t SH_FLD_DATA_REQUEST_3 = 6228; // 2
+static const uint64_t SH_FLD_DATA_ROUTE_ERROR = 6229; // 2
+static const uint64_t SH_FLD_DATA_RTAG_P = 6230; // 12
+static const uint64_t SH_FLD_DATA_V_LT = 6231; // 43
+static const uint64_t SH_FLD_DAT_ARR_ECC_CORR_ENA = 6232; // 6
+static const uint64_t SH_FLD_DAT_ARR_ECC_SUE_ENA = 6233; // 6
+static const uint64_t SH_FLD_DAT_BUFFER_PAR_ERR = 6234; // 4
+static const uint64_t SH_FLD_DAT_CREG_PERR = 6235; // 1
+static const uint64_t SH_FLD_DAT_DATA_BE_CE = 6236; // 1
+static const uint64_t SH_FLD_DAT_DATA_BE_PERR = 6237; // 1
+static const uint64_t SH_FLD_DAT_DATA_BE_SUE = 6238; // 1
+static const uint64_t SH_FLD_DAT_DATA_BE_UE = 6239; // 1
+static const uint64_t SH_FLD_DAT_LOGIC_ERR = 6240; // 1
+static const uint64_t SH_FLD_DAT_PBRX_SUE = 6241; // 1
+static const uint64_t SH_FLD_DAT_RSVD_10 = 6242; // 1
+static const uint64_t SH_FLD_DAT_RSVD_9 = 6243; // 1
+static const uint64_t SH_FLD_DAT_RTAG_PERR = 6244; // 1
+static const uint64_t SH_FLD_DAT_STATE_PERR = 6245; // 1
+static const uint64_t SH_FLD_DBG_BUS0_STG0_SEL = 6246; // 2
+static const uint64_t SH_FLD_DBG_BUS0_STG0_SEL_LEN = 6247; // 2
+static const uint64_t SH_FLD_DBG_BUS1_STG0_SEL = 6248; // 2
+static const uint64_t SH_FLD_DBG_BUS1_STG0_SEL_LEN = 6249; // 2
+static const uint64_t SH_FLD_DBG_BUS_BIT = 6250; // 8
+static const uint64_t SH_FLD_DBG_CC_ERROR = 6251; // 1
+static const uint64_t SH_FLD_DBG_CHIPLET_IS_ALIGNED = 6252; // 1
+static const uint64_t SH_FLD_DBG_CLR_MAX_HANG_STAGE = 6253; // 3
+static const uint64_t SH_FLD_DBG_CMD = 6254; // 1
+static const uint64_t SH_FLD_DBG_CMD_LEN = 6255; // 1
+static const uint64_t SH_FLD_DBG_CTL_REG_PARITY_ERRHOLD = 6256; // 2
+static const uint64_t SH_FLD_DBG_CURRENT_OPCG_MODE = 6257; // 1
+static const uint64_t SH_FLD_DBG_CURRENT_OPCG_MODE_LEN = 6258; // 1
+static const uint64_t SH_FLD_DBG_HALT = 6259; // 1
+static const uint64_t SH_FLD_DBG_LAST_OPCG_MODE = 6260; // 1
+static const uint64_t SH_FLD_DBG_LAST_OPCG_MODE_LEN = 6261; // 1
+static const uint64_t SH_FLD_DBG_NORTH_UNUSED_BITS0 = 6262; // 1
+static const uint64_t SH_FLD_DBG_NORTH_UNUSED_BITS0_LEN = 6263; // 1
+static const uint64_t SH_FLD_DBG_NORTH_UNUSED_BITS1 = 6264; // 1
+static const uint64_t SH_FLD_DBG_NORTH_UNUSED_BITS1_LEN = 6265; // 1
+static const uint64_t SH_FLD_DBG_OPCG_IP = 6266; // 1
+static const uint64_t SH_FLD_DBG_PARANOIA_TEST_ENABLE_CHANGE = 6267; // 1
+static const uint64_t SH_FLD_DBG_PARANOIA_VITL_CLKOFF_CHANGE = 6268; // 1
+static const uint64_t SH_FLD_DBG_PARITY_ERROR = 6269; // 1
+static const uint64_t SH_FLD_DBG_PCB_ERROR = 6270; // 1
+static const uint64_t SH_FLD_DBG_PCB_IDLE = 6271; // 1
+static const uint64_t SH_FLD_DBG_PCB_REQUEST_SINCE_RESET = 6272; // 1
+static const uint64_t SH_FLD_DBG_PROTOCOL_ERROR = 6273; // 1
+static const uint64_t SH_FLD_DBG_REQ = 6274; // 1
+static const uint64_t SH_FLD_DBG_RESET_EP = 6275; // 1
+static const uint64_t SH_FLD_DBG_SECURITY_DEBUG_MODE = 6276; // 1
+static const uint64_t SH_FLD_DBG_SEL_IN = 6277; // 8
+static const uint64_t SH_FLD_DBG_SEL_PWCTL_DEBUG = 6278; // 8
+static const uint64_t SH_FLD_DBG_SEL_PWSEQ0_DEBUG_0 = 6279; // 8
+static const uint64_t SH_FLD_DBG_SEL_PWSEQ0_DEBUG_1 = 6280; // 8
+static const uint64_t SH_FLD_DBG_SEL_PWSEQ1_DEBUG_0 = 6281; // 8
+static const uint64_t SH_FLD_DBG_SEL_PWSEQ1_DEBUG_1 = 6282; // 8
+static const uint64_t SH_FLD_DBG_SEL_PWSEQ2_DEBUG_0 = 6283; // 8
+static const uint64_t SH_FLD_DBG_SEL_PWSEQ2_DEBUG_1 = 6284; // 8
+static const uint64_t SH_FLD_DBG_SEL_PWSEQ3_DEBUG_0 = 6285; // 8
+static const uint64_t SH_FLD_DBG_SEL_PWSEQ3_DEBUG_1 = 6286; // 8
+static const uint64_t SH_FLD_DBG_SEL_PWSEQ4_DEBUG_0 = 6287; // 8
+static const uint64_t SH_FLD_DBG_SEL_PWSEQ4_DEBUG_1 = 6288; // 8
+static const uint64_t SH_FLD_DBG_SEL_PWSEQ5_DEBUG_0 = 6289; // 8
+static const uint64_t SH_FLD_DBG_SEL_PWSEQ5_DEBUG_1 = 6290; // 8
+static const uint64_t SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_0 = 6291; // 8
+static const uint64_t SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_1 = 6292; // 8
+static const uint64_t SH_FLD_DBG_SEL_WDF = 6293; // 8
+static const uint64_t SH_FLD_DBG_SEL_WDFMGR_DEBUG = 6294; // 8
+static const uint64_t SH_FLD_DBG_SEL_WDFRD_DEBUG_0 = 6295; // 8
+static const uint64_t SH_FLD_DBG_SEL_WDFRD_DEBUG_1 = 6296; // 8
+static const uint64_t SH_FLD_DBG_SEL_WDFWR_DEBUG_0 = 6297; // 8
+static const uint64_t SH_FLD_DBG_SEL_WDFWR_DEBUG_1 = 6298; // 8
+static const uint64_t SH_FLD_DBG_SPARE = 6299; // 8
+static const uint64_t SH_FLD_DBG_SPARE_LEN = 6300; // 8
+static const uint64_t SH_FLD_DBG_SPARE_MCA = 6301; // 8
+static const uint64_t SH_FLD_DBG_SPARE_MCA_LEN = 6302; // 8
+static const uint64_t SH_FLD_DBG_SPARE_NEST = 6303; // 8
+static const uint64_t SH_FLD_DBG_SPARE_NEST_LEN = 6304; // 8
+static const uint64_t SH_FLD_DBG_STATE = 6305; // 1
+static const uint64_t SH_FLD_DBG_STATE_LEN = 6306; // 1
+static const uint64_t SH_FLD_DBG_TEST_ENABLE = 6307; // 1
+static const uint64_t SH_FLD_DBG_TP_TPFSI_ACK = 6308; // 1
+static const uint64_t SH_FLD_DBG_UNCONDITIONAL_EVENT = 6309; // 1
+static const uint64_t SH_FLD_DBG_VITL_CLKOFF = 6310; // 1
+static const uint64_t SH_FLD_DBLERR = 6311; // 2
+static const uint64_t SH_FLD_DCACHE_ERR = 6312; // 4
+static const uint64_t SH_FLD_DCACHE_TAG_ADDR = 6313; // 4
+static const uint64_t SH_FLD_DCACHE_TAG_ADDR_LEN = 6314; // 4
+static const uint64_t SH_FLD_DCLKSEL = 6315; // 6
+static const uint64_t SH_FLD_DCLKSEL_LEN = 6316; // 6
+static const uint64_t SH_FLD_DCOMP_ENABLE = 6317; // 1
+static const uint64_t SH_FLD_DCOMP_ENGINE_BUSY = 6318; // 1
+static const uint64_t SH_FLD_DCOMP_ERR = 6319; // 1
+static const uint64_t SH_FLD_DCO_DECR = 6320; // 6
+static const uint64_t SH_FLD_DCO_INCR = 6321; // 6
+static const uint64_t SH_FLD_DCO_OVERRIDE = 6322; // 6
+static const uint64_t SH_FLD_DCU_RNW = 6323; // 1
+static const uint64_t SH_FLD_DCU_TIMEOUT_ERROR = 6324; // 1
+static const uint64_t SH_FLD_DC_CALIBRATE_DONE = 6325; // 4
+static const uint64_t SH_FLD_DC_ENABLE_CM_COARSE_CAL = 6326; // 6
+static const uint64_t SH_FLD_DC_ENABLE_CM_FINE_CAL = 6327; // 6
+static const uint64_t SH_FLD_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 6328; // 6
+static const uint64_t SH_FLD_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 6329; // 6
+static const uint64_t SH_FLD_DC_ENABLE_DAC_H1_CAL = 6330; // 4
+static const uint64_t SH_FLD_DC_ENABLE_DAC_H1_TO_A_CAL = 6331; // 4
+static const uint64_t SH_FLD_DC_ENABLE_INTEG_LATCH_OFFSET_CAL = 6332; // 6
+static const uint64_t SH_FLD_DD2_FIX_DIS = 6333; // 8
+static const uint64_t SH_FLD_DDC_CFG = 6334; // 120
+static const uint64_t SH_FLD_DDC_CFG_LEN = 6335; // 120
+static const uint64_t SH_FLD_DDC_DFE_OFFSET_SWITCH_SM = 6336; // 72
+static const uint64_t SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN = 6337; // 72
+static const uint64_t SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP = 6338; // 72
+static const uint64_t SH_FLD_DDR0 = 6339; // 24
+static const uint64_t SH_FLD_DDR01_PARITY_ERR = 6340; // 16
+static const uint64_t SH_FLD_DDR0_CALIBRATION_ERROR = 6341; // 16
+static const uint64_t SH_FLD_DDR0_FSM_CKSTP = 6342; // 16
+static const uint64_t SH_FLD_DDR0_FSM_ERR = 6343; // 16
+static const uint64_t SH_FLD_DDR0_LEN = 6344; // 24
+static const uint64_t SH_FLD_DDR0_PARITY_CKSTP = 6345; // 16
+static const uint64_t SH_FLD_DDR0_PARITY_ERR = 6346; // 16
+static const uint64_t SH_FLD_DDR1 = 6347; // 24
+static const uint64_t SH_FLD_DDR1_CALIBRATION_ERROR = 6348; // 16
+static const uint64_t SH_FLD_DDR1_FSM_CKSTP = 6349; // 16
+static const uint64_t SH_FLD_DDR1_FSM_ERR = 6350; // 16
+static const uint64_t SH_FLD_DDR1_LEN = 6351; // 24
+static const uint64_t SH_FLD_DDR1_PARITY_CKSTP = 6352; // 16
+static const uint64_t SH_FLD_DDR1_PARITY_ERR = 6353; // 16
+static const uint64_t SH_FLD_DDR4_CMD_SIG_REDUCTION = 6354; // 8
+static const uint64_t SH_FLD_DDR4_IPW_LOOP_DIS = 6355; // 8
+static const uint64_t SH_FLD_DDR4_LATENCY_SW = 6356; // 8
+static const uint64_t SH_FLD_DDR4_VLEVEL_BANK_GROUP = 6357; // 8
+static const uint64_t SH_FLD_DDR_ACTN = 6358; // 64
+static const uint64_t SH_FLD_DDR_ADDRESS = 6359; // 8
+static const uint64_t SH_FLD_DDR_ADDRESS_0 = 6360; // 2
+static const uint64_t SH_FLD_DDR_ADDRESS_0_13 = 6361; // 62
+static const uint64_t SH_FLD_DDR_ADDRESS_0_13_LEN = 6362; // 62
+static const uint64_t SH_FLD_DDR_ADDRESS_0_LEN = 6363; // 2
+static const uint64_t SH_FLD_DDR_ADDRESS_14 = 6364; // 62
+static const uint64_t SH_FLD_DDR_ADDRESS_15 = 6365; // 62
+static const uint64_t SH_FLD_DDR_ADDRESS_16 = 6366; // 62
+static const uint64_t SH_FLD_DDR_ADDRESS_17 = 6367; // 62
+static const uint64_t SH_FLD_DDR_BANK_0_1 = 6368; // 64
+static const uint64_t SH_FLD_DDR_BANK_0_1_LEN = 6369; // 64
+static const uint64_t SH_FLD_DDR_BANK_2 = 6370; // 64
+static const uint64_t SH_FLD_DDR_BANK_GROUP_0 = 6371; // 64
+static const uint64_t SH_FLD_DDR_BANK_GROUP_1 = 6372; // 64
+static const uint64_t SH_FLD_DDR_CALIBRATION_ENABLE = 6373; // 64
+static const uint64_t SH_FLD_DDR_CAL_RANK = 6374; // 64
+static const uint64_t SH_FLD_DDR_CAL_RANK_LEN = 6375; // 64
+static const uint64_t SH_FLD_DDR_CAL_RESET_TIMEOUT = 6376; // 16
+static const uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT = 6377; // 2
+static const uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_LEN = 6378; // 2
+static const uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT = 6379; // 2
+static const uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT_LEN = 6380; // 2
+static const uint64_t SH_FLD_DDR_CAL_TIMEOUT_ERR = 6381; // 16
+static const uint64_t SH_FLD_DDR_CAL_TYPE = 6382; // 64
+static const uint64_t SH_FLD_DDR_CAL_TYPE_LEN = 6383; // 64
+static const uint64_t SH_FLD_DDR_CID_0_1 = 6384; // 64
+static const uint64_t SH_FLD_DDR_CID_0_1_LEN = 6385; // 64
+static const uint64_t SH_FLD_DDR_CID_2 = 6386; // 64
+static const uint64_t SH_FLD_DDR_CKE = 6387; // 64
+static const uint64_t SH_FLD_DDR_CKE_LEN = 6388; // 64
+static const uint64_t SH_FLD_DDR_CSN_0_1 = 6389; // 64
+static const uint64_t SH_FLD_DDR_CSN_0_1_LEN = 6390; // 64
+static const uint64_t SH_FLD_DDR_CSN_2_3 = 6391; // 64
+static const uint64_t SH_FLD_DDR_CSN_2_3_LEN = 6392; // 64
+static const uint64_t SH_FLD_DDR_IF_SM_1HOT = 6393; // 8
+static const uint64_t SH_FLD_DDR_MBA_EVENT_N = 6394; // 16
+static const uint64_t SH_FLD_DDR_ODT = 6395; // 64
+static const uint64_t SH_FLD_DDR_ODT_LEN = 6396; // 64
+static const uint64_t SH_FLD_DDR_PARITY = 6397; // 64
+static const uint64_t SH_FLD_DDR_PARITY_ENABLE = 6398; // 2
+static const uint64_t SH_FLD_DDR_RESETN = 6399; // 64
+static const uint64_t SH_FLD_DEAD = 6400; // 43
+static const uint64_t SH_FLD_DEBUG = 6401; // 2
+static const uint64_t SH_FLD_DEBUG0_CONFIG_P = 6402; // 1
+static const uint64_t SH_FLD_DEBUG1_CONFIG_P = 6403; // 1
+static const uint64_t SH_FLD_DEBUGGER = 6404; // 25
+static const uint64_t SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS = 6405; // 1
+static const uint64_t SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS_LEN = 6406; // 1
+static const uint64_t SH_FLD_DEBUG_BUS_0_63 = 6407; // 4
+static const uint64_t SH_FLD_DEBUG_BUS_0_63_LEN = 6408; // 4
+static const uint64_t SH_FLD_DEBUG_BUS_64_87 = 6409; // 4
+static const uint64_t SH_FLD_DEBUG_BUS_64_87_LEN = 6410; // 4
+static const uint64_t SH_FLD_DEBUG_BUS_SEL = 6411; // 8
+static const uint64_t SH_FLD_DEBUG_BUS_SEL2 = 6412; // 8
+static const uint64_t SH_FLD_DEBUG_BUS_SEL2_LEN = 6413; // 8
+static const uint64_t SH_FLD_DEBUG_BUS_SEL_LEN = 6414; // 8
+static const uint64_t SH_FLD_DEBUG_LEN = 6415; // 2
+static const uint64_t SH_FLD_DEBUG_OCI_MODE = 6416; // 1
+static const uint64_t SH_FLD_DEBUG_OCI_MODE_LEN = 6417; // 1
+static const uint64_t SH_FLD_DEBUG_PB_NOT_OCI = 6418; // 1
+static const uint64_t SH_FLD_DEBUG_TRIGGER = 6419; // 25
+static const uint64_t SH_FLD_DECONFIGURED_INTR = 6420; // 24
+static const uint64_t SH_FLD_DECOUPLE_EDGE_A = 6421; // 48
+static const uint64_t SH_FLD_DECOUPLE_EDGE_B = 6422; // 48
+static const uint64_t SH_FLD_DEC_EXIT_ENABLE = 6423; // 96
+static const uint64_t SH_FLD_DEF_VALUES = 6424; // 8
+static const uint64_t SH_FLD_DEF_VALUES_LEN = 6425; // 8
+static const uint64_t SH_FLD_DEGLITCH_CLK_DLY = 6426; // 1
+static const uint64_t SH_FLD_DEGLITCH_CLK_DLY_LEN = 6427; // 1
+static const uint64_t SH_FLD_DEGLITCH_DATA_DLY = 6428; // 1
+static const uint64_t SH_FLD_DEGLITCH_DATA_DLY_LEN = 6429; // 1
+static const uint64_t SH_FLD_DELAY = 6430; // 1
+static const uint64_t SH_FLD_DELAY1_ID = 6431; // 12
+static const uint64_t SH_FLD_DELAY1_ID_LEN = 6432; // 12
+static const uint64_t SH_FLD_DELAY1_VALID = 6433; // 12
+static const uint64_t SH_FLD_DELAY2_ID = 6434; // 12
+static const uint64_t SH_FLD_DELAY2_ID_LEN = 6435; // 12
+static const uint64_t SH_FLD_DELAY2_VALID = 6436; // 12
+static const uint64_t SH_FLD_DELAY3_ID = 6437; // 12
+static const uint64_t SH_FLD_DELAY3_ID_LEN = 6438; // 12
+static const uint64_t SH_FLD_DELAY3_VALID = 6439; // 12
+static const uint64_t SH_FLD_DELAY4_ID = 6440; // 12
+static const uint64_t SH_FLD_DELAY4_ID_LEN = 6441; // 12
+static const uint64_t SH_FLD_DELAY4_VALID = 6442; // 12
+static const uint64_t SH_FLD_DELAY5_ID = 6443; // 12
+static const uint64_t SH_FLD_DELAY5_ID_LEN = 6444; // 12
+static const uint64_t SH_FLD_DELAY5_VALID = 6445; // 12
+static const uint64_t SH_FLD_DELAY6_ID = 6446; // 12
+static const uint64_t SH_FLD_DELAY6_ID_LEN = 6447; // 12
+static const uint64_t SH_FLD_DELAY6_VALID = 6448; // 12
+static const uint64_t SH_FLD_DELAY7_ID = 6449; // 12
+static const uint64_t SH_FLD_DELAY7_ID_LEN = 6450; // 12
+static const uint64_t SH_FLD_DELAY7_VALID = 6451; // 12
+static const uint64_t SH_FLD_DELAY8_ID = 6452; // 12
+static const uint64_t SH_FLD_DELAY8_ID_LEN = 6453; // 12
+static const uint64_t SH_FLD_DELAY8_VALID = 6454; // 12
+static const uint64_t SH_FLD_DELAYED_PAR = 6455; // 8
+static const uint64_t SH_FLD_DELAYG = 6456; // 32
+static const uint64_t SH_FLD_DELAYG_LEN = 6457; // 32
+static const uint64_t SH_FLD_DELAY_ADJUST_DISABLE = 6458; // 1
+static const uint64_t SH_FLD_DELAY_ADJUST_VALUE = 6459; // 1
+static const uint64_t SH_FLD_DELAY_ADJUST_VALUE_LEN = 6460; // 1
+static const uint64_t SH_FLD_DELAY_AFTER_BLOCK = 6461; // 24
+static const uint64_t SH_FLD_DELAY_DISABLE = 6462; // 1
+static const uint64_t SH_FLD_DELAY_LCLKR = 6463; // 43
+static const uint64_t SH_FLD_DELAY_LEN = 6464; // 1
+static const uint64_t SH_FLD_DELAY_LINE_CTL_OVERRIDE = 6465; // 8
+static const uint64_t SH_FLD_DEQUEUED_EOT_FLAG = 6466; // 1
+static const uint64_t SH_FLD_DESKEW_BUMP_AFTER = 6467; // 4
+static const uint64_t SH_FLD_DESKEW_DONE = 6468; // 4
+static const uint64_t SH_FLD_DESKEW_FAILED = 6469; // 4
+static const uint64_t SH_FLD_DESKEW_MAXSKEW_GRP = 6470; // 4
+static const uint64_t SH_FLD_DESKEW_MAXSKEW_GRP_LEN = 6471; // 4
+static const uint64_t SH_FLD_DESKEW_MAX_LIMIT = 6472; // 4
+static const uint64_t SH_FLD_DESKEW_MAX_LIMIT_LEN = 6473; // 4
+static const uint64_t SH_FLD_DESKEW_MINSKEW_GRP = 6474; // 4
+static const uint64_t SH_FLD_DESKEW_MINSKEW_GRP_LEN = 6475; // 4
+static const uint64_t SH_FLD_DESKEW_PATTCHK_TIMEOUT_SEL = 6476; // 4
+static const uint64_t SH_FLD_DESKEW_PATTCHK_TIMEOUT_SEL_LEN = 6477; // 4
+static const uint64_t SH_FLD_DESKEW_RATE = 6478; // 8
+static const uint64_t SH_FLD_DESKEW_SEQ_GCRMSG = 6479; // 4
+static const uint64_t SH_FLD_DESKEW_SEQ_GCRMSG_LEN = 6480; // 4
+static const uint64_t SH_FLD_DESKEW_SKMAX_GCRMSG = 6481; // 4
+static const uint64_t SH_FLD_DESKEW_SKMAX_GCRMSG_LEN = 6482; // 4
+static const uint64_t SH_FLD_DESKEW_SKMIN_GCRMSG = 6483; // 4
+static const uint64_t SH_FLD_DESKEW_SKMIN_GCRMSG_LEN = 6484; // 4
+static const uint64_t SH_FLD_DEST = 6485; // 1
+static const uint64_t SH_FLD_DEST0 = 6486; // 24
+static const uint64_t SH_FLD_DEST0_LEN = 6487; // 24
+static const uint64_t SH_FLD_DEST1 = 6488; // 24
+static const uint64_t SH_FLD_DEST1_LEN = 6489; // 24
+static const uint64_t SH_FLD_DEST_CHIPID = 6490; // 1
+static const uint64_t SH_FLD_DEST_CHIPID_LEN = 6491; // 1
+static const uint64_t SH_FLD_DEST_GROUPID = 6492; // 1
+static const uint64_t SH_FLD_DEST_GROUPID_LEN = 6493; // 1
+static const uint64_t SH_FLD_DEST_LEN = 6494; // 1
+static const uint64_t SH_FLD_DETAIL = 6495; // 2
+static const uint64_t SH_FLD_DETAIL_LEN = 6496; // 2
+static const uint64_t SH_FLD_DEVICE = 6497; // 1
+static const uint64_t SH_FLD_DEVICE_ADDRESS_0 = 6498; // 2
+static const uint64_t SH_FLD_DEVICE_ADDRESS_0_LEN = 6499; // 2
+static const uint64_t SH_FLD_DEVICE_ADDRESS_1 = 6500; // 1
+static const uint64_t SH_FLD_DEVICE_ADDRESS_1_LEN = 6501; // 1
+static const uint64_t SH_FLD_DEVICE_ADDRESS_2 = 6502; // 1
+static const uint64_t SH_FLD_DEVICE_ADDRESS_2_LEN = 6503; // 1
+static const uint64_t SH_FLD_DEVICE_ADDRESS_3 = 6504; // 1
+static const uint64_t SH_FLD_DEVICE_ADDRESS_3_LEN = 6505; // 1
+static const uint64_t SH_FLD_DEVICE_ID = 6506; // 4
+static const uint64_t SH_FLD_DEVICE_ID_LEN = 6507; // 4
+static const uint64_t SH_FLD_DFE12_EN = 6508; // 4
+static const uint64_t SH_FLD_DFEHISPD_EN = 6509; // 4
+static const uint64_t SH_FLD_DFE_CA_CFG = 6510; // 6
+static const uint64_t SH_FLD_DFE_CA_CFG_LEN = 6511; // 6
+static const uint64_t SH_FLD_DFE_CONVERGED_CNT_MAX = 6512; // 6
+static const uint64_t SH_FLD_DFE_CONVERGED_CNT_MAX_LEN = 6513; // 6
+static const uint64_t SH_FLD_DFE_FORCE_LOAD_SEED = 6514; // 72
+static const uint64_t SH_FLD_DFE_HTAP_CFG = 6515; // 4
+static const uint64_t SH_FLD_DFE_HTAP_CFG_LEN = 6516; // 4
+static const uint64_t SH_FLD_DFE_INIT_TIMEOUT = 6517; // 4
+static const uint64_t SH_FLD_DFE_INIT_TIMEOUT_LEN = 6518; // 4
+static const uint64_t SH_FLD_DFE_RECAL_TIMEOUT = 6519; // 4
+static const uint64_t SH_FLD_DFE_RECAL_TIMEOUT_LEN = 6520; // 4
+static const uint64_t SH_FLD_DFREEZE = 6521; // 9
+static const uint64_t SH_FLD_DFREEZE_LEN = 6522; // 9
+static const uint64_t SH_FLD_DFS_SM_ERRHOLD = 6523; // 2
+static const uint64_t SH_FLD_DGD_AE_ALWAYS = 6524; // 6
+static const uint64_t SH_FLD_DGD_BE_128 = 6525; // 6
+static const uint64_t SH_FLD_DGEN_RNDD_DATA_MAPPING = 6526; // 2
+static const uint64_t SH_FLD_DGEN_RNDD_DATA_MAPPING_LEN = 6527; // 2
+static const uint64_t SH_FLD_DGEN_RNDD_SEED0 = 6528; // 2
+static const uint64_t SH_FLD_DGEN_RNDD_SEED0_LEN = 6529; // 2
+static const uint64_t SH_FLD_DGEN_RNDD_SEED1 = 6530; // 2
+static const uint64_t SH_FLD_DGEN_RNDD_SEED1_LEN = 6531; // 2
+static const uint64_t SH_FLD_DGEN_RNDD_SEED2 = 6532; // 2
+static const uint64_t SH_FLD_DGEN_RNDD_SEED2_LEN = 6533; // 2
+static const uint64_t SH_FLD_DIAG_0 = 6534; // 2
+static const uint64_t SH_FLD_DIAG_1 = 6535; // 1
+static const uint64_t SH_FLD_DIAG_2 = 6536; // 1
+static const uint64_t SH_FLD_DIAG_3 = 6537; // 1
+static const uint64_t SH_FLD_DIB01_ERR = 6538; // 4
+static const uint64_t SH_FLD_DIB01_SPARE = 6539; // 1
+static const uint64_t SH_FLD_DIB01_SPARE_LEN = 6540; // 1
+static const uint64_t SH_FLD_DIB23_ERR = 6541; // 4
+static const uint64_t SH_FLD_DIB45_ERR = 6542; // 4
+static const uint64_t SH_FLD_DIB67_ERR = 6543; // 2
+static const uint64_t SH_FLD_DIB67_SPARE = 6544; // 1
+static const uint64_t SH_FLD_DIB67_SPARE_LEN = 6545; // 1
+static const uint64_t SH_FLD_DIGITAL_EYE = 6546; // 8
+static const uint64_t SH_FLD_DIRECT_BRIDGE_SOURCE = 6547; // 1
+static const uint64_t SH_FLD_DIR_CE_DETECTED = 6548; // 12
+static const uint64_t SH_FLD_DIR_PERR_CHK_DIS = 6549; // 2
+static const uint64_t SH_FLD_DIR_SBCE_REPAIR_FAILED = 6550; // 12
+static const uint64_t SH_FLD_DIR_STUCK_BIT_CE = 6551; // 12
+static const uint64_t SH_FLD_DIR_UE_DETECTED = 6552; // 12
+static const uint64_t SH_FLD_DISABLE = 6553; // 2
+static const uint64_t SH_FLD_DISABLED = 6554; // 47
+static const uint64_t SH_FLD_DISABLED_LEN = 6555; // 4
+static const uint64_t SH_FLD_DISABLE_1 = 6556; // 1
+static const uint64_t SH_FLD_DISABLE_1_LEN = 6557; // 1
+static const uint64_t SH_FLD_DISABLE_2 = 6558; // 1
+static const uint64_t SH_FLD_DISABLE_2K_SPEC_FILTER = 6559; // 4
+static const uint64_t SH_FLD_DISABLE_2N_MODE = 6560; // 2
+static const uint64_t SH_FLD_DISABLE_2TO12_CLEAR = 6561; // 4
+static const uint64_t SH_FLD_DISABLE_2_LEN = 6562; // 1
+static const uint64_t SH_FLD_DISABLE_ALL_SPEC_OPS = 6563; // 4
+static const uint64_t SH_FLD_DISABLE_ARY_CLK_DURING_FILL = 6564; // 43
+static const uint64_t SH_FLD_DISABLE_BAD_LANE_COUNT = 6565; // 2
+static const uint64_t SH_FLD_DISABLE_BANK_PDWN = 6566; // 2
+static const uint64_t SH_FLD_DISABLE_BYPASS_IN_READ_DATAFLOW = 6567; // 4
+static const uint64_t SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH = 6568; // 4
+static const uint64_t SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH_LEN = 6569; // 4
+static const uint64_t SH_FLD_DISABLE_CHARB_BYPASS = 6570; // 4
+static const uint64_t SH_FLD_DISABLE_CHECKIN_HANG_TIMER = 6571; // 1
+static const uint64_t SH_FLD_DISABLE_CHECKOUT_HANG_TIMER = 6572; // 1
+static const uint64_t SH_FLD_DISABLE_CHECKSTOP = 6573; // 1
+static const uint64_t SH_FLD_DISABLE_CI = 6574; // 4
+static const uint64_t SH_FLD_DISABLE_CI_LEN = 6575; // 4
+static const uint64_t SH_FLD_DISABLE_CLEAR_BAD_LANE_COUNT = 6576; // 2
+static const uint64_t SH_FLD_DISABLE_COMMAND_BYPASS = 6577; // 4
+static const uint64_t SH_FLD_DISABLE_COMMAND_BYPASS_LEN = 6578; // 4
+static const uint64_t SH_FLD_DISABLE_COMPRESSION = 6579; // 90
+static const uint64_t SH_FLD_DISABLE_CRC_ECC_BYPASS = 6580; // 4
+static const uint64_t SH_FLD_DISABLE_CRC_ECC_BYPASS_LEN = 6581; // 4
+static const uint64_t SH_FLD_DISABLE_CRC_ECC_FP_BYPASS = 6582; // 4
+static const uint64_t SH_FLD_DISABLE_DROPABLE = 6583; // 8
+static const uint64_t SH_FLD_DISABLE_ECC = 6584; // 1
+static const uint64_t SH_FLD_DISABLE_ECC_ARRAY_CHK = 6585; // 2
+static const uint64_t SH_FLD_DISABLE_ECC_ARRAY_CORRECTION = 6586; // 2
+static const uint64_t SH_FLD_DISABLE_ECC_CHK = 6587; // 1
+static const uint64_t SH_FLD_DISABLE_ECC_CORRECTION = 6588; // 1
+static const uint64_t SH_FLD_DISABLE_ECC_COR_GXC_PSI = 6589; // 1
+static const uint64_t SH_FLD_DISABLE_ECC_COR_RXRF_PSI = 6590; // 1
+static const uint64_t SH_FLD_DISABLE_ECC_COR_TXRF_PSI = 6591; // 1
+static const uint64_t SH_FLD_DISABLE_ERR_CMD = 6592; // 1
+static const uint64_t SH_FLD_DISABLE_EXTRA_FIFO_ACCESSES = 6593; // 1
+static const uint64_t SH_FLD_DISABLE_EXTRA_HASH_ACCESSES = 6594; // 1
+static const uint64_t SH_FLD_DISABLE_FAR_HISTORY = 6595; // 1
+static const uint64_t SH_FLD_DISABLE_FASTPATH = 6596; // 4
+static const uint64_t SH_FLD_DISABLE_FENCE_RESET = 6597; // 4
+static const uint64_t SH_FLD_DISABLE_FLOW_SCOPE = 6598; // 1
+static const uint64_t SH_FLD_DISABLE_FP_COMMAND_BYPASS = 6599; // 4
+static const uint64_t SH_FLD_DISABLE_FP_M_BIT = 6600; // 4
+static const uint64_t SH_FLD_DISABLE_G = 6601; // 1
+static const uint64_t SH_FLD_DISABLE_G_RD = 6602; // 1
+static const uint64_t SH_FLD_DISABLE_G_WR = 6603; // 1
+static const uint64_t SH_FLD_DISABLE_H1_CLEAR = 6604; // 6
+static const uint64_t SH_FLD_DISABLE_HIGH_PRIORITY = 6605; // 4
+static const uint64_t SH_FLD_DISABLE_HIGH_PRIORITY_LEN = 6606; // 4
+static const uint64_t SH_FLD_DISABLE_HIT_UNDER_BARRIER = 6607; // 1
+static const uint64_t SH_FLD_DISABLE_HTM_CMD = 6608; // 1
+static const uint64_t SH_FLD_DISABLE_INJECT = 6609; // 1
+static const uint64_t SH_FLD_DISABLE_LFSR = 6610; // 1
+static const uint64_t SH_FLD_DISABLE_LINK_FAIL_COUNT = 6611; // 2
+static const uint64_t SH_FLD_DISABLE_LN = 6612; // 1
+static const uint64_t SH_FLD_DISABLE_LN_RD = 6613; // 1
+static const uint64_t SH_FLD_DISABLE_LN_WR = 6614; // 1
+static const uint64_t SH_FLD_DISABLE_LPC_CMDS = 6615; // 3
+static const uint64_t SH_FLD_DISABLE_MDI0 = 6616; // 4
+static const uint64_t SH_FLD_DISABLE_MDI0_LEN = 6617; // 4
+static const uint64_t SH_FLD_DISABLE_MEMCTL_CAL = 6618; // 8
+static const uint64_t SH_FLD_DISABLE_NEAR_HISTORY = 6619; // 1
+static const uint64_t SH_FLD_DISABLE_NN_RD = 6620; // 1
+static const uint64_t SH_FLD_DISABLE_NN_RN = 6621; // 1
+static const uint64_t SH_FLD_DISABLE_NN_WR = 6622; // 1
+static const uint64_t SH_FLD_DISABLE_PARITY_CHECKER = 6623; // 8
+static const uint64_t SH_FLD_DISABLE_PCB_ITR = 6624; // 43
+static const uint64_t SH_FLD_DISABLE_PERFMON_RESET_ON_START = 6625; // 4
+static const uint64_t SH_FLD_DISABLE_PMISC = 6626; // 9
+static const uint64_t SH_FLD_DISABLE_PMU_SNOOPING = 6627; // 1
+static const uint64_t SH_FLD_DISABLE_PROMOTE = 6628; // 1
+static const uint64_t SH_FLD_DISABLE_PTAG_IN_AIBTAG = 6629; // 1
+static const uint64_t SH_FLD_DISABLE_RCMD_CLKGATE = 6630; // 3
+static const uint64_t SH_FLD_DISABLE_RESET_2K_COUNT_IF_HINT_BIT_SET = 6631; // 4
+static const uint64_t SH_FLD_DISABLE_RETRY_LOST_CLAIM = 6632; // 4
+static const uint64_t SH_FLD_DISABLE_SHARD_PRESP_ABORT = 6633; // 4
+static const uint64_t SH_FLD_DISABLE_SL_ECC = 6634; // 5
+static const uint64_t SH_FLD_DISABLE_SPEC_DISABLE_HINT_BIT = 6635; // 4
+static const uint64_t SH_FLD_DISABLE_SPEC_OP = 6636; // 4
+static const uint64_t SH_FLD_DISABLE_SPEC_OP_LEN = 6637; // 4
+static const uint64_t SH_FLD_DISABLE_SPEC_SOURCE_SCOPE = 6638; // 4
+static const uint64_t SH_FLD_DISABLE_SPEC_SOURCE_SCOPE_LEN = 6639; // 4
+static const uint64_t SH_FLD_DISABLE_STICKINESS = 6640; // 43
+static const uint64_t SH_FLD_DISABLE_TIMEOUT = 6641; // 1
+static const uint64_t SH_FLD_DISABLE_TIMEOUT_AND_RETRY = 6642; // 1
+static const uint64_t SH_FLD_DISABLE_TOD_CMD = 6643; // 1
+static const uint64_t SH_FLD_DISABLE_TRACE_CMD = 6644; // 1
+static const uint64_t SH_FLD_DISABLE_VG_NOT_SYS = 6645; // 1
+static const uint64_t SH_FLD_DISABLE_VG_RD = 6646; // 1
+static const uint64_t SH_FLD_DISABLE_VG_WR = 6647; // 1
+static const uint64_t SH_FLD_DISABLE_WRP = 6648; // 1
+static const uint64_t SH_FLD_DISABLE_XSCOM_CMD = 6649; // 1
+static const uint64_t SH_FLD_DISPATCH_SLOT_KILLED_CNT = 6650; // 1
+static const uint64_t SH_FLD_DISPATCH_SLOT_KILLED_CNT_LEN = 6651; // 1
+static const uint64_t SH_FLD_DISP_DEBUG_SEL = 6652; // 8
+static const uint64_t SH_FLD_DISP_DEBUG_SEL_LEN = 6653; // 8
+static const uint64_t SH_FLD_DISTRIBUTION_BROADCAST_MODE_ENABLE = 6654; // 1
+static const uint64_t SH_FLD_DISTR_STEP_SYNC_TX_DISABLE = 6655; // 1
+static const uint64_t SH_FLD_DISTR_STEP_SYNC_TX_SYNC_DISABLE = 6656; // 1
+static const uint64_t SH_FLD_DISTR_STEP_SYNC_TX_TRIGGER = 6657; // 1
+static const uint64_t SH_FLD_DIS_AIB_IN_ECC_CORRECTION = 6658; // 1
+static const uint64_t SH_FLD_DIS_ARX_DAT_CORR = 6659; // 1
+static const uint64_t SH_FLD_DIS_ARX_DAT_CORR_LEN = 6660; // 1
+static const uint64_t SH_FLD_DIS_ARX_ECC_CORRECTION = 6661; // 1
+static const uint64_t SH_FLD_DIS_ARX_TAG_CORR = 6662; // 1
+static const uint64_t SH_FLD_DIS_ATX_AT_CORR = 6663; // 1
+static const uint64_t SH_FLD_DIS_ATX_BAR_CORR = 6664; // 1
+static const uint64_t SH_FLD_DIS_ATX_CMD_CORR = 6665; // 1
+static const uint64_t SH_FLD_DIS_AT_SRAM_ECC_CORRECTION = 6666; // 1
+static const uint64_t SH_FLD_DIS_AVX_CORR = 6667; // 1
+static const uint64_t SH_FLD_DIS_BAR_SRAM_ECC_CORRECTION = 6668; // 1
+static const uint64_t SH_FLD_DIS_CHGRATE_COUNT = 6669; // 1
+static const uint64_t SH_FLD_DIS_CPM_BUBBLE_CORR = 6670; // 43
+static const uint64_t SH_FLD_DIS_CRESP_CORR = 6671; // 1
+static const uint64_t SH_FLD_DIS_CTRLBUF_ECC_CORRECTION = 6672; // 1
+static const uint64_t SH_FLD_DIS_DATA_ECC_CORRECTION = 6673; // 4
+static const uint64_t SH_FLD_DIS_DATA_ECC_CORRECTION_LEN = 6674; // 4
+static const uint64_t SH_FLD_DIS_DMA_W = 6675; // 1
+static const uint64_t SH_FLD_DIS_DROPABLE_HP = 6676; // 8
+static const uint64_t SH_FLD_DIS_ECCCHK = 6677; // 1
+static const uint64_t SH_FLD_DIS_ECCCHK_CLO = 6678; // 1
+static const uint64_t SH_FLD_DIS_ECCCHK_IN = 6679; // 1
+static const uint64_t SH_FLD_DIS_ECCCHK_LDO = 6680; // 1
+static const uint64_t SH_FLD_DIS_ECCCHK_STO = 6681; // 1
+static const uint64_t SH_FLD_DIS_ECCCHK_WRO = 6682; // 1
+static const uint64_t SH_FLD_DIS_GLOB_SCOM = 6683; // 2
+static const uint64_t SH_FLD_DIS_IRQ_ECC_CORRECTION = 6684; // 1
+static const uint64_t SH_FLD_DIS_LD_ECC_CORRECTION = 6685; // 1
+static const uint64_t SH_FLD_DIS_MASTER_RD_PIPE = 6686; // 1
+static const uint64_t SH_FLD_DIS_MASTER_WR_PIPE = 6687; // 1
+static const uint64_t SH_FLD_DIS_MMIO_LDST_CORR = 6688; // 1
+static const uint64_t SH_FLD_DIS_MMIO_RSP_CORR = 6689; // 1
+static const uint64_t SH_FLD_DIS_MSTID_MATCH_PREF_INV = 6690; // 1
+static const uint64_t SH_FLD_DIS_NCNP = 6691; // 1
+static const uint64_t SH_FLD_DIS_PTAG_ECC_CORRECTION = 6692; // 1
+static const uint64_t SH_FLD_DIS_PTAG_ECC_CORRECTION_LEN = 6693; // 1
+static const uint64_t SH_FLD_DIS_REARB = 6694; // 1
+static const uint64_t SH_FLD_DIS_RECOVERY = 6695; // 24
+static const uint64_t SH_FLD_DIS_REREQUEST_TO = 6696; // 1
+static const uint64_t SH_FLD_DIS_SLAVE_RDPIPE = 6697; // 1
+static const uint64_t SH_FLD_DIS_SLAVE_WRPIPE = 6698; // 1
+static const uint64_t SH_FLD_DIS_STATE_ECC_CORRECTION = 6699; // 4
+static const uint64_t SH_FLD_DIS_STATE_ECC_CORRECTION_LEN = 6700; // 2
+static const uint64_t SH_FLD_DIS_SYND_TALLYING = 6701; // 4
+static const uint64_t SH_FLD_DIS_TAG_ECC_CORRECTION = 6702; // 4
+static const uint64_t SH_FLD_DIS_TAG_ECC_CORRECTION_LEN = 6703; // 4
+static const uint64_t SH_FLD_DIS_TAG_SRAM_ECC_CORRECTION = 6704; // 1
+static const uint64_t SH_FLD_DIS_TRACE_EXTRA = 6705; // 1
+static const uint64_t SH_FLD_DIS_TRACE_STALL = 6706; // 1
+static const uint64_t SH_FLD_DIS_VRQ_QUEUE_CORR = 6707; // 1
+static const uint64_t SH_FLD_DIS_WRITE_GATHER = 6708; // 4
+static const uint64_t SH_FLD_DIVIDER_MODE = 6709; // 12
+static const uint64_t SH_FLD_DIVIDER_MODE_LEN = 6710; // 12
+static const uint64_t SH_FLD_DIVSELB = 6711; // 10
+static const uint64_t SH_FLD_DIVSELB_LEN = 6712; // 10
+static const uint64_t SH_FLD_DIVSELFB = 6713; // 10
+static const uint64_t SH_FLD_DIVSELFB_LEN = 6714; // 10
+static const uint64_t SH_FLD_DIV_PARITY = 6715; // 43
+static const uint64_t SH_FLD_DLL = 6716; // 8
+static const uint64_t SH_FLD_DLL_CLOCK_GATE = 6717; // 8
+static const uint64_t SH_FLD_DL_RETURN_P0 = 6718; // 43
+static const uint64_t SH_FLD_DL_RETURN_WDATA_PARITY = 6719; // 43
+static const uint64_t SH_FLD_DMAP_MODE_EN = 6720; // 2
+static const uint64_t SH_FLD_DMA_CH0_IDLE = 6721; // 1
+static const uint64_t SH_FLD_DMA_CH1_IDLE = 6722; // 1
+static const uint64_t SH_FLD_DMA_CH2_IDLE = 6723; // 1
+static const uint64_t SH_FLD_DMA_CH3_IDLE = 6724; // 1
+static const uint64_t SH_FLD_DMA_CH4_IDLE = 6725; // 1
+static const uint64_t SH_FLD_DMA_CRBARRAY_ACTION = 6726; // 1
+static const uint64_t SH_FLD_DMA_CRBARRAY_ENA = 6727; // 1
+static const uint64_t SH_FLD_DMA_CRBARRAY_SELECT = 6728; // 1
+static const uint64_t SH_FLD_DMA_CRBARRAY_TYPE = 6729; // 1
+static const uint64_t SH_FLD_DMA_EGRARRAY_ACTION = 6730; // 1
+static const uint64_t SH_FLD_DMA_EGRARRAY_ENA = 6731; // 1
+static const uint64_t SH_FLD_DMA_EGRARRAY_SELECT = 6732; // 1
+static const uint64_t SH_FLD_DMA_EGRARRAY_SELECT_LEN = 6733; // 1
+static const uint64_t SH_FLD_DMA_EGRARRAY_TYPE = 6734; // 1
+static const uint64_t SH_FLD_DMA_INGARRAY_ACTION = 6735; // 1
+static const uint64_t SH_FLD_DMA_INGARRAY_ENA = 6736; // 1
+static const uint64_t SH_FLD_DMA_INGARRAY_SELECT = 6737; // 1
+static const uint64_t SH_FLD_DMA_INGARRAY_SELECT_LEN = 6738; // 1
+static const uint64_t SH_FLD_DMA_INGARRAY_TYPE = 6739; // 1
+static const uint64_t SH_FLD_DMA_INWR_ACTION = 6740; // 1
+static const uint64_t SH_FLD_DMA_INWR_ENA = 6741; // 1
+static const uint64_t SH_FLD_DMA_INWR_TYPE = 6742; // 1
+static const uint64_t SH_FLD_DMA_MUX_SELECT = 6743; // 1
+static const uint64_t SH_FLD_DMA_MUX_SELECT_LEN = 6744; // 1
+static const uint64_t SH_FLD_DMA_OUTWR_ACTION = 6745; // 1
+static const uint64_t SH_FLD_DMA_OUTWR_ENA = 6746; // 1
+static const uint64_t SH_FLD_DMA_OUTWR_QW0_UEINJ_ENA = 6747; // 1
+static const uint64_t SH_FLD_DMA_OUTWR_QW4_UEINJ_ENA = 6748; // 1
+static const uint64_t SH_FLD_DMA_OUTWR_TYPE = 6749; // 1
+static const uint64_t SH_FLD_DMA_PARTIAL_WRT_NOT_INJECT = 6750; // 1
+static const uint64_t SH_FLD_DMA_PART_WR_NOT_INJ = 6751; // 1
+static const uint64_t SH_FLD_DMA_RD_DISABLE_GROUP = 6752; // 2
+static const uint64_t SH_FLD_DMA_RD_DISABLE_LN = 6753; // 2
+static const uint64_t SH_FLD_DMA_RD_DISABLE_NN_RN = 6754; // 2
+static const uint64_t SH_FLD_DMA_RD_DISABLE_VG_NOT_SYS = 6755; // 2
+static const uint64_t SH_FLD_DMA_RD_VG_RESET_TIMER_MASK = 6756; // 2
+static const uint64_t SH_FLD_DMA_RD_VG_RESET_TIMER_MASK_LEN = 6757; // 2
+static const uint64_t SH_FLD_DMA_RD_VG_RST_TMASK = 6758; // 1
+static const uint64_t SH_FLD_DMA_RD_VG_RST_TMASK_LEN = 6759; // 1
+static const uint64_t SH_FLD_DMA_READ = 6760; // 3
+static const uint64_t SH_FLD_DMA_READ_LEN = 6761; // 3
+static const uint64_t SH_FLD_DMA_STOPPED_STATE = 6762; // 32
+static const uint64_t SH_FLD_DMA_STOPPED_STATE_LEN = 6763; // 16
+static const uint64_t SH_FLD_DMA_TIMER_ENBL = 6764; // 1
+static const uint64_t SH_FLD_DMA_TIMER_REF_DIV = 6765; // 1
+static const uint64_t SH_FLD_DMA_TIMER_REF_DIV_LEN = 6766; // 1
+static const uint64_t SH_FLD_DMA_WRITE = 6767; // 3
+static const uint64_t SH_FLD_DMA_WRITE_LEN = 6768; // 2
+static const uint64_t SH_FLD_DMA_WR_DISABLE_GROUP = 6769; // 2
+static const uint64_t SH_FLD_DMA_WR_DISABLE_LN = 6770; // 2
+static const uint64_t SH_FLD_DMA_WR_DISABLE_NN_RN = 6771; // 2
+static const uint64_t SH_FLD_DMA_WR_DISABLE_VG_NOT_SYS = 6772; // 2
+static const uint64_t SH_FLD_DMA_WR_NOT_INJ = 6773; // 1
+static const uint64_t SH_FLD_DMA_WR_NOT_INJECT = 6774; // 1
+static const uint64_t SH_FLD_DMA_WR_VG_RESET_TIMER_MASK = 6775; // 2
+static const uint64_t SH_FLD_DMA_WR_VG_RESET_TIMER_MASK_LEN = 6776; // 2
+static const uint64_t SH_FLD_DMA_WR_VG_RST_TMASK = 6777; // 1
+static const uint64_t SH_FLD_DMA_WR_VG_RST_TMASK_LEN = 6778; // 1
+static const uint64_t SH_FLD_DNFIFO_DEQUEUED_EOT_FLAG = 6779; // 1
+static const uint64_t SH_FLD_DNFIFO_FIFO_EMPTY = 6780; // 1
+static const uint64_t SH_FLD_DNFIFO_FIFO_ENTRY_COUNT = 6781; // 1
+static const uint64_t SH_FLD_DNFIFO_FIFO_ENTRY_COUNT_LEN = 6782; // 1
+static const uint64_t SH_FLD_DNFIFO_FIFO_EOT_FLAGS = 6783; // 1
+static const uint64_t SH_FLD_DNFIFO_FIFO_EOT_FLAGS_LEN = 6784; // 1
+static const uint64_t SH_FLD_DNFIFO_FIFO_FULL = 6785; // 1
+static const uint64_t SH_FLD_DNFIFO_FIFO_VALID_FLAGS = 6786; // 1
+static const uint64_t SH_FLD_DNFIFO_FIFO_VALID_FLAGS_LEN = 6787; // 1
+static const uint64_t SH_FLD_DNFIFO_REQ_RESET_FR_SBE = 6788; // 1
+static const uint64_t SH_FLD_DNFIFO_REQ_RESET_FR_SP = 6789; // 1
+static const uint64_t SH_FLD_DOB01_CE = 6790; // 4
+static const uint64_t SH_FLD_DOB01_ERR = 6791; // 4
+static const uint64_t SH_FLD_DOB01_SUE = 6792; // 4
+static const uint64_t SH_FLD_DOB01_UE = 6793; // 4
+static const uint64_t SH_FLD_DOB23_CE = 6794; // 4
+static const uint64_t SH_FLD_DOB23_ERR = 6795; // 4
+static const uint64_t SH_FLD_DOB23_SUE = 6796; // 4
+static const uint64_t SH_FLD_DOB23_UE = 6797; // 4
+static const uint64_t SH_FLD_DOB45_CE = 6798; // 4
+static const uint64_t SH_FLD_DOB45_ERR = 6799; // 4
+static const uint64_t SH_FLD_DOB45_SUE = 6800; // 4
+static const uint64_t SH_FLD_DOB45_UE = 6801; // 4
+static const uint64_t SH_FLD_DOB67_CE = 6802; // 2
+static const uint64_t SH_FLD_DOB67_ERR = 6803; // 2
+static const uint64_t SH_FLD_DOB67_SUE = 6804; // 2
+static const uint64_t SH_FLD_DOB67_UE = 6805; // 2
+static const uint64_t SH_FLD_DONE = 6806; // 31
+static const uint64_t SH_FLD_DOORBELL0_C0 = 6807; // 12
+static const uint64_t SH_FLD_DOORBELL0_C1 = 6808; // 12
+static const uint64_t SH_FLD_DOORBELL1_C0 = 6809; // 12
+static const uint64_t SH_FLD_DOORBELL1_C1 = 6810; // 12
+static const uint64_t SH_FLD_DOORBELL2_C0 = 6811; // 12
+static const uint64_t SH_FLD_DOORBELL2_C1 = 6812; // 12
+static const uint64_t SH_FLD_DOORBELL3_C0 = 6813; // 12
+static const uint64_t SH_FLD_DOORBELL3_C1 = 6814; // 12
+static const uint64_t SH_FLD_DOUBLE_EPSILON_LENGTH = 6815; // 4
+static const uint64_t SH_FLD_DO_DR = 6816; // 1
+static const uint64_t SH_FLD_DO_IR = 6817; // 1
+static const uint64_t SH_FLD_DO_TAP_RESET = 6818; // 1
+static const uint64_t SH_FLD_DPLL_DCO_EMPTY = 6819; // 6
+static const uint64_t SH_FLD_DPLL_DCO_FULL = 6820; // 6
+static const uint64_t SH_FLD_DPLL_DYN_FMIN = 6821; // 6
+static const uint64_t SH_FLD_DPLL_INT = 6822; // 6
+static const uint64_t SH_FLD_DPLL_TEST_SEL = 6823; // 43
+static const uint64_t SH_FLD_DPLL_TEST_SEL_LEN = 6824; // 43
+static const uint64_t SH_FLD_DP_DLL_CAL_ERROR = 6825; // 8
+static const uint64_t SH_FLD_DP_DLL_CAL_ERROR_FINE = 6826; // 8
+static const uint64_t SH_FLD_DP_ERROR = 6827; // 8
+static const uint64_t SH_FLD_DP_ERROR_FINE = 6828; // 8
+static const uint64_t SH_FLD_DP_GOOD = 6829; // 8
+static const uint64_t SH_FLD_DQS = 6830; // 8
+static const uint64_t SH_FLD_DQS_ALIGN = 6831; // 8
+static const uint64_t SH_FLD_DQ_SEL_LANE = 6832; // 8
+static const uint64_t SH_FLD_DQ_SEL_LANE_LEN = 6833; // 8
+static const uint64_t SH_FLD_DQ_SEL_QUAD = 6834; // 8
+static const uint64_t SH_FLD_DQ_SEL_QUAD_LEN = 6835; // 8
+static const uint64_t SH_FLD_DRAM_ABIST_DONE_DC = 6836; // 43
+static const uint64_t SH_FLD_DROOP_CHAR_MODE = 6837; // 12
+static const uint64_t SH_FLD_DROOP_NOTIFY_ENABLE = 6838; // 12
+static const uint64_t SH_FLD_DROOP_PROFILE_TYPE = 6839; // 12
+static const uint64_t SH_FLD_DROOP_PROFILE_TYPE_LEN = 6840; // 12
+static const uint64_t SH_FLD_DROOP_PROTECT_DATA = 6841; // 6
+static const uint64_t SH_FLD_DROOP_PROTECT_DATA_LEN = 6842; // 6
+static const uint64_t SH_FLD_DROOP_SAMPLE_RATE = 6843; // 12
+static const uint64_t SH_FLD_DROOP_SAMPLE_RATE_LEN = 6844; // 12
+static const uint64_t SH_FLD_DROOP_TIMER_MODE = 6845; // 12
+static const uint64_t SH_FLD_DROPOUT_CHAR_MODE = 6846; // 12
+static const uint64_t SH_FLD_DROPOUT_DETECT = 6847; // 12
+static const uint64_t SH_FLD_DROPOUT_EVENT_THRESHOLD = 6848; // 12
+static const uint64_t SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN = 6849; // 12
+static const uint64_t SH_FLD_DROPOUT_INAROW_THRESHOLD = 6850; // 12
+static const uint64_t SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN = 6851; // 12
+static const uint64_t SH_FLD_DROPOUT_NOTIFY_ENABLE = 6852; // 12
+static const uint64_t SH_FLD_DROPOUT_SAMPLE = 6853; // 12
+static const uint64_t SH_FLD_DROPOUT_SAMPLE_LEN = 6854; // 12
+static const uint64_t SH_FLD_DROPOUT_SAMPLE_RATE = 6855; // 12
+static const uint64_t SH_FLD_DROPOUT_SAMPLE_RATE_LEN = 6856; // 12
+static const uint64_t SH_FLD_DROPOUT_TIMER_MODE = 6857; // 12
+static const uint64_t SH_FLD_DROP_COUNTER_FULL = 6858; // 4
+static const uint64_t SH_FLD_DROP_MASK_0_5 = 6859; // 1
+static const uint64_t SH_FLD_DROP_MASK_0_5_LEN = 6860; // 1
+static const uint64_t SH_FLD_DROP_PLS_DIV00 = 6861; // 8
+static const uint64_t SH_FLD_DROP_PLS_DIV00_LEN = 6862; // 8
+static const uint64_t SH_FLD_DROP_PLS_DIV01 = 6863; // 8
+static const uint64_t SH_FLD_DROP_PLS_DIV01_LEN = 6864; // 8
+static const uint64_t SH_FLD_DROP_PLS_DIV10 = 6865; // 8
+static const uint64_t SH_FLD_DROP_PLS_DIV10_LEN = 6866; // 8
+static const uint64_t SH_FLD_DROP_PLS_DIV11 = 6867; // 8
+static const uint64_t SH_FLD_DROP_PLS_DIV11_LEN = 6868; // 8
+static const uint64_t SH_FLD_DROP_PRIORITY_MASK = 6869; // 12
+static const uint64_t SH_FLD_DROP_PRIORITY_MASK_LEN = 6870; // 12
+static const uint64_t SH_FLD_DROP_PRIORITY_MODE = 6871; // 2
+static const uint64_t SH_FLD_DROP_PRI_DMA = 6872; // 1
+static const uint64_t SH_FLD_DROP_PRI_HPC_READ = 6873; // 1
+static const uint64_t SH_FLD_DROP_PRI_INTRP = 6874; // 1
+static const uint64_t SH_FLD_DRTM_REQ = 6875; // 5
+static const uint64_t SH_FLD_DRV_CLK_PATTERN_GCRMSG = 6876; // 4
+static const uint64_t SH_FLD_DRV_CLK_PATTERN_GCRMSG_LEN = 6877; // 4
+static const uint64_t SH_FLD_DRV_DATA_PATTERN_GCRMSG = 6878; // 6
+static const uint64_t SH_FLD_DRV_DATA_PATTERN_GCRMSG_LEN = 6879; // 6
+static const uint64_t SH_FLD_DRV_PATTERN_EN = 6880; // 1
+static const uint64_t SH_FLD_DSC1_ABORT_1 = 6881; // 1
+static const uint64_t SH_FLD_DSC1_DATA_COUNT = 6882; // 1
+static const uint64_t SH_FLD_DSC1_DATA_COUNT_1B = 6883; // 1
+static const uint64_t SH_FLD_DSC1_DATA_COUNT_1B_LEN = 6884; // 1
+static const uint64_t SH_FLD_DSC1_DATA_COUNT_LEN = 6885; // 1
+static const uint64_t SH_FLD_DSC1_HEADER_COUNT = 6886; // 1
+static const uint64_t SH_FLD_DSC1_HEADER_COUNT_1B = 6887; // 1
+static const uint64_t SH_FLD_DSC1_HEADER_COUNT_1B_LEN = 6888; // 1
+static const uint64_t SH_FLD_DSC1_HEADER_COUNT_LEN = 6889; // 1
+static const uint64_t SH_FLD_DSC1_LBUS_SLAVE_1B_PENDING = 6890; // 1
+static const uint64_t SH_FLD_DSC1_PERMISSION_TO_SEND_1 = 6891; // 1
+static const uint64_t SH_FLD_DSC1_PIB_SLAVE_PENDING = 6892; // 1
+static const uint64_t SH_FLD_DSC1_UNUSED_24 = 6893; // 1
+static const uint64_t SH_FLD_DSC1_UNUSED_27 = 6894; // 1
+static const uint64_t SH_FLD_DSC1_XDN_1 = 6895; // 1
+static const uint64_t SH_FLD_DSC1_XUP_1 = 6896; // 1
+static const uint64_t SH_FLD_DSC2_ABORT_2 = 6897; // 1
+static const uint64_t SH_FLD_DSC2_DATA_COUNT = 6898; // 1
+static const uint64_t SH_FLD_DSC2_DATA_COUNT_2B = 6899; // 1
+static const uint64_t SH_FLD_DSC2_DATA_COUNT_2B_LEN = 6900; // 1
+static const uint64_t SH_FLD_DSC2_DATA_COUNT_LEN = 6901; // 1
+static const uint64_t SH_FLD_DSC2_HEADER_COUNT = 6902; // 1
+static const uint64_t SH_FLD_DSC2_HEADER_COUNT_2B = 6903; // 1
+static const uint64_t SH_FLD_DSC2_HEADER_COUNT_2B_LEN = 6904; // 1
+static const uint64_t SH_FLD_DSC2_HEADER_COUNT_LEN = 6905; // 1
+static const uint64_t SH_FLD_DSC2_LBUS_SLAVE_2B_PENDING = 6906; // 1
+static const uint64_t SH_FLD_DSC2_PERMISSION_TO_SEND_2 = 6907; // 1
+static const uint64_t SH_FLD_DSC2_PIB_SLAVE_PENDING = 6908; // 1
+static const uint64_t SH_FLD_DSC2_UNUSED_24 = 6909; // 1
+static const uint64_t SH_FLD_DSC2_UNUSED_27 = 6910; // 1
+static const uint64_t SH_FLD_DSC2_XDN_2 = 6911; // 1
+static const uint64_t SH_FLD_DSC2_XUP_2 = 6912; // 1
+static const uint64_t SH_FLD_DSM_CMD_PE_HOLD_OUT = 6913; // 8
+static const uint64_t SH_FLD_DSM_PE = 6914; // 8
+static const uint64_t SH_FLD_DS_SKEW_TIMEOUT_SEL = 6915; // 4
+static const uint64_t SH_FLD_DS_SKEW_TIMEOUT_SEL_LEN = 6916; // 4
+static const uint64_t SH_FLD_DS_TIMEOUT_SEL = 6917; // 4
+static const uint64_t SH_FLD_DS_TIMEOUT_SEL_LEN = 6918; // 4
+static const uint64_t SH_FLD_DTS_ENABLE_L1 = 6919; // 43
+static const uint64_t SH_FLD_DTS_ENABLE_L1_LEN = 6920; // 43
+static const uint64_t SH_FLD_DTS_READ_SEL = 6921; // 43
+static const uint64_t SH_FLD_DTS_READ_SEL_LEN = 6922; // 43
+static const uint64_t SH_FLD_DTS_SAMPLE_ENA = 6923; // 43
+static const uint64_t SH_FLD_DTS_TRIGGER = 6924; // 43
+static const uint64_t SH_FLD_DTS_TRIGGER_SEL = 6925; // 43
+static const uint64_t SH_FLD_DW0_ERR_TYPE = 6926; // 16
+static const uint64_t SH_FLD_DW0_ERR_TYPE_LEN = 6927; // 16
+static const uint64_t SH_FLD_DW0_SYNDROME = 6928; // 16
+static const uint64_t SH_FLD_DW0_SYNDROME_LEN = 6929; // 16
+static const uint64_t SH_FLD_DW1_ERR_TYPE = 6930; // 16
+static const uint64_t SH_FLD_DW1_ERR_TYPE_LEN = 6931; // 16
+static const uint64_t SH_FLD_DW1_SYNDROME = 6932; // 16
+static const uint64_t SH_FLD_DW1_SYNDROME_LEN = 6933; // 16
+static const uint64_t SH_FLD_DW2_ERR_TYPE = 6934; // 16
+static const uint64_t SH_FLD_DW2_ERR_TYPE_LEN = 6935; // 16
+static const uint64_t SH_FLD_DW2_SYNDROME = 6936; // 16
+static const uint64_t SH_FLD_DW2_SYNDROME_LEN = 6937; // 16
+static const uint64_t SH_FLD_DW3_ERR_TYPE = 6938; // 16
+static const uint64_t SH_FLD_DW3_ERR_TYPE_LEN = 6939; // 16
+static const uint64_t SH_FLD_DW3_SYNDROME = 6940; // 16
+static const uint64_t SH_FLD_DW3_SYNDROME_LEN = 6941; // 16
+static const uint64_t SH_FLD_DW_TYPE = 6942; // 12
+static const uint64_t SH_FLD_DW_TYPE_LEN = 6943; // 12
+static const uint64_t SH_FLD_DYNAMIC_MAX_SPARES_EXCEEDED = 6944; // 8
+static const uint64_t SH_FLD_DYNAMIC_REPAIR_ERROR = 6945; // 8
+static const uint64_t SH_FLD_DYNAMIC_SPARE_DEPLOYED = 6946; // 8
+static const uint64_t SH_FLD_DYNAMIC_WINDOW_SELECT = 6947; // 8
+static const uint64_t SH_FLD_DYNAMIC_WINDOW_SELECT_LEN = 6948; // 8
+static const uint64_t SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL = 6949; // 8
+static const uint64_t SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN = 6950; // 8
+static const uint64_t SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL = 6951; // 4
+static const uint64_t SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL_LEN = 6952; // 4
+static const uint64_t SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL = 6953; // 8
+static const uint64_t SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN = 6954; // 8
+static const uint64_t SH_FLD_DYN_RECAL_SUSPEND = 6955; // 4
+static const uint64_t SH_FLD_DYN_RECAL_TSR_IGNORE_GCRMSG = 6956; // 4
+static const uint64_t SH_FLD_DYN_RPR_BAD_BUS_MAX = 6957; // 4
+static const uint64_t SH_FLD_DYN_RPR_BAD_BUS_MAX_LEN = 6958; // 4
+static const uint64_t SH_FLD_DYN_RPR_BAD_LANE_MAX = 6959; // 4
+static const uint64_t SH_FLD_DYN_RPR_BAD_LANE_MAX_LEN = 6960; // 4
+static const uint64_t SH_FLD_DYN_RPR_CLR_ERR_CNTR1 = 6961; // 4
+static const uint64_t SH_FLD_DYN_RPR_CLR_ERR_CNTR2 = 6962; // 4
+static const uint64_t SH_FLD_DYN_RPR_COMPLETE_GCRMSG = 6963; // 4
+static const uint64_t SH_FLD_DYN_RPR_DISABLE = 6964; // 4
+static const uint64_t SH_FLD_DYN_RPR_DISABLE2 = 6965; // 4
+static const uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT = 6966; // 4
+static const uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT_LEN = 6967; // 4
+static const uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH = 6968; // 4
+static const uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH_LEN = 6969; // 4
+static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_DURATION = 6970; // 4
+static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_DURATION_LEN = 6971; // 4
+static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_FILTER_MODE = 6972; // 4
+static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_FILTER_MODE_LEN = 6973; // 4
+static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR2_DURATION = 6974; // 4
+static const uint64_t SH_FLD_DYN_RPR_ERR_CNTR2_DURATION_LEN = 6975; // 4
+static const uint64_t SH_FLD_DYN_RPR_IP_GCRMSG = 6976; // 4
+static const uint64_t SH_FLD_DYN_RPR_LANE2RPR_GCRMSG = 6977; // 4
+static const uint64_t SH_FLD_DYN_RPR_LANE2RPR_GCRMSG_LEN = 6978; // 4
+static const uint64_t SH_FLD_DYN_RPR_REQ_GCRMSG = 6979; // 4
+static const uint64_t SH_FLD_DYN_RPR_REQ_MANUAL = 6980; // 4
+static const uint64_t SH_FLD_DYN_RPR_SM_MANUAL = 6981; // 4
+static const uint64_t SH_FLD_DYN_ST_FREQ_MULT = 6982; // 2
+static const uint64_t SH_FLD_DYN_ST_FREQ_MULT_LEN = 6983; // 1
+static const uint64_t SH_FLD_DYN_ST_MODE_EN = 6984; // 1
+static const uint64_t SH_FLD_DYN_ST_MODE_HANGP_EN = 6985; // 1
+static const uint64_t SH_FLD_DYN_ST_MODE_THRESHOLD = 6986; // 2
+static const uint64_t SH_FLD_DYN_ST_MODE_THRESHOLD_LEN = 6987; // 2
+static const uint64_t SH_FLD_D_BIT_MAP = 6988; // 8
+static const uint64_t SH_FLD_D_BIT_MAP_LEN = 6989; // 8
+static const uint64_t SH_FLD_EAINJ = 6990; // 1
+static const uint64_t SH_FLD_EARLY_REQ = 6991; // 8
+static const uint64_t SH_FLD_EARLY_REQ_ERR_MASK = 6992; // 8
+static const uint64_t SH_FLD_EARLY_REQ_SOURCE = 6993; // 8
+static const uint64_t SH_FLD_EARLY_REQ_SOURCE_LEN = 6994; // 8
+static const uint64_t SH_FLD_EA_RANGE_CHK_DIS = 6995; // 1
+static const uint64_t SH_FLD_EBUS_ENABLE_0_15 = 6996; // 1
+static const uint64_t SH_FLD_EBUS_ENABLE_0_15_LEN = 6997; // 1
+static const uint64_t SH_FLD_ECC = 6998; // 3
+static const uint64_t SH_FLD_ECCCHK_DISABLE_0 = 6999; // 1
+static const uint64_t SH_FLD_ECCCHK_DISABLE_1 = 7000; // 1
+static const uint64_t SH_FLD_ECCCHK_DISABLE_2 = 7001; // 1
+static const uint64_t SH_FLD_ECCCHK_DISABLE_3 = 7002; // 1
+static const uint64_t SH_FLD_ECCGEN = 7003; // 8
+static const uint64_t SH_FLD_ECC_CE = 7004; // 3
+static const uint64_t SH_FLD_ECC_CHK_DISABLE = 7005; // 1
+static const uint64_t SH_FLD_ECC_CLEAR = 7006; // 2
+static const uint64_t SH_FLD_ECC_CONFIG_ERROR_0 = 7007; // 1
+static const uint64_t SH_FLD_ECC_CONFIG_ERROR_1 = 7008; // 1
+static const uint64_t SH_FLD_ECC_CONFIG_ERROR_2 = 7009; // 1
+static const uint64_t SH_FLD_ECC_CONFIG_ERROR_3 = 7010; // 1
+static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_0 = 7011; // 1
+static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_1 = 7012; // 1
+static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_2 = 7013; // 1
+static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_3 = 7014; // 1
+static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_FACES = 7015; // 1
+static const uint64_t SH_FLD_ECC_CORRECTED_ERROR_PIB = 7016; // 1
+static const uint64_t SH_FLD_ECC_CORRECTOR_INTERNAL_PARITY_ERROR = 7017; // 8
+static const uint64_t SH_FLD_ECC_CORRECT_DIS = 7018; // 16
+static const uint64_t SH_FLD_ECC_CTL_AF_PERR = 7019; // 8
+static const uint64_t SH_FLD_ECC_CTL_CMPMODE_ERR = 7020; // 8
+static const uint64_t SH_FLD_ECC_CTL_PCTL_PERR = 7021; // 8
+static const uint64_t SH_FLD_ECC_CTL_RPTR_PERR = 7022; // 8
+static const uint64_t SH_FLD_ECC_CTL_SCH_PERR = 7023; // 8
+static const uint64_t SH_FLD_ECC_CTL_TCHN_PERR = 7024; // 8
+static const uint64_t SH_FLD_ECC_CTL_TGST_PERR = 7025; // 8
+static const uint64_t SH_FLD_ECC_DEBUG_CHUNK_SELECT = 7026; // 8
+static const uint64_t SH_FLD_ECC_DEBUG_CHUNK_SELECT_LEN = 7027; // 8
+static const uint64_t SH_FLD_ECC_DEBUG_ENABLE = 7028; // 8
+static const uint64_t SH_FLD_ECC_DEBUG_PRIMARY_SELECT = 7029; // 8
+static const uint64_t SH_FLD_ECC_DEBUG_PRIMARY_SELECT_LEN = 7030; // 8
+static const uint64_t SH_FLD_ECC_DEBUG_SECONDARY_SELECT = 7031; // 8
+static const uint64_t SH_FLD_ECC_DEBUG_SECONDARY_SELECT_LEN = 7032; // 8
+static const uint64_t SH_FLD_ECC_DETECT_DIS = 7033; // 16
+static const uint64_t SH_FLD_ECC_ENABLE = 7034; // 6
+static const uint64_t SH_FLD_ECC_ENABLE_0 = 7035; // 1
+static const uint64_t SH_FLD_ECC_ENABLE_1 = 7036; // 1
+static const uint64_t SH_FLD_ECC_ENABLE_2 = 7037; // 1
+static const uint64_t SH_FLD_ECC_ENABLE_3 = 7038; // 1
+static const uint64_t SH_FLD_ECC_ERROR_ADDR = 7039; // 2
+static const uint64_t SH_FLD_ECC_ERROR_ADDR_LEN = 7040; // 2
+static const uint64_t SH_FLD_ECC_ERROR_COUNT = 7041; // 2
+static const uint64_t SH_FLD_ECC_ERROR_COUNT_LEN = 7042; // 2
+static const uint64_t SH_FLD_ECC_ERR_INJ_ARRAY_SEL = 7043; // 4
+static const uint64_t SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN = 7044; // 4
+static const uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_ENA = 7045; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_FRQ = 7046; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_TYP = 7047; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_UNUSED = 7048; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_UNUSED_LEN = 7049; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_PARTITION_SEL = 7050; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_PARTITION_SEL_LEN = 7051; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_SELECTION = 7052; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_SELECTION_LEN = 7053; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_ENA = 7054; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_FRQ = 7055; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_SEL = 7056; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_TYP = 7057; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_UNUSED = 7058; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_UNUSED_LEN = 7059; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_ENA = 7060; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_FRQ = 7061; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_SEL = 7062; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_SEL_LEN = 7063; // 1
+static const uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_TYP = 7064; // 1
+static const uint64_t SH_FLD_ECC_GENERATOR_INTERNAL_PARITY_ERROR = 7065; // 8
+static const uint64_t SH_FLD_ECC_INJECT_ERR = 7066; // 16
+static const uint64_t SH_FLD_ECC_INJECT_TYPE = 7067; // 16
+static const uint64_t SH_FLD_ECC_LEN = 7068; // 3
+static const uint64_t SH_FLD_ECC_MCBIST_OUT_OF_SYNC_HOLD_OUT = 7069; // 2
+static const uint64_t SH_FLD_ECC_PIPE_PARITY_ERROR_0 = 7070; // 8
+static const uint64_t SH_FLD_ECC_PIPE_PARITY_ERROR_1 = 7071; // 8
+static const uint64_t SH_FLD_ECC_PIPE_PARITY_ERROR_2 = 7072; // 8
+static const uint64_t SH_FLD_ECC_PIPE_PARITY_ERROR_3 = 7073; // 8
+static const uint64_t SH_FLD_ECC_SYNDROME = 7074; // 2
+static const uint64_t SH_FLD_ECC_SYNDROME_LEN = 7075; // 2
+static const uint64_t SH_FLD_ECC_S_BIT_ERROR = 7076; // 1
+static const uint64_t SH_FLD_ECC_UE = 7077; // 3
+static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_0 = 7078; // 1
+static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_1 = 7079; // 1
+static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_2 = 7080; // 1
+static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_3 = 7081; // 1
+static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_FACES = 7082; // 1
+static const uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_PIB = 7083; // 1
+static const uint64_t SH_FLD_ECC_UNCORRECTED_ERR_FACES = 7084; // 1
+static const uint64_t SH_FLD_ECC_UNCORRECTED_ERR_PIB = 7085; // 1
+static const uint64_t SH_FLD_ECC_WAT_ACTION_SELECT = 7086; // 8
+static const uint64_t SH_FLD_ECC_WAT_ENABLE = 7087; // 8
+static const uint64_t SH_FLD_ECC_WAT_SOURCE = 7088; // 8
+static const uint64_t SH_FLD_ECC_WAT_SOURCE_LEN = 7089; // 8
+static const uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE = 7090; // 8
+static const uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_LEN = 7091; // 8
+static const uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT = 7092; // 8
+static const uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT_LEN = 7093; // 8
+static const uint64_t SH_FLD_ECHO_DELAY_CYCLES = 7094; // 2
+static const uint64_t SH_FLD_ECHO_DELAY_CYCLES_LEN = 7095; // 2
+static const uint64_t SH_FLD_ECRESP_HASH_MODE = 7096; // 4
+static const uint64_t SH_FLD_EDGE_TRIGGER_MODE1 = 7097; // 86
+static const uint64_t SH_FLD_EDGE_TRIGGER_MODE2 = 7098; // 86
+static const uint64_t SH_FLD_EDPL_LANE_ID = 7099; // 5
+static const uint64_t SH_FLD_EDPL_RATE = 7100; // 5
+static const uint64_t SH_FLD_EDPL_RATE_LEN = 7101; // 5
+static const uint64_t SH_FLD_EDR = 7102; // 21
+static const uint64_t SH_FLD_EDRAM_PGATE = 7103; // 6
+static const uint64_t SH_FLD_EDRAM_SEQUENCE = 7104; // 6
+static const uint64_t SH_FLD_EDR_LEN = 7105; // 21
+static const uint64_t SH_FLD_EFTCOMP_MAX_INRD = 7106; // 1
+static const uint64_t SH_FLD_EFTCOMP_MAX_INRD_LEN = 7107; // 1
+static const uint64_t SH_FLD_EFTDECOMP_MAX_INRD = 7108; // 1
+static const uint64_t SH_FLD_EFTDECOMP_MAX_INRD_LEN = 7109; // 1
+static const uint64_t SH_FLD_EFT_COMP_PREFETCH_ENABLE = 7110; // 1
+static const uint64_t SH_FLD_EFT_DECOMP_PREFETCH_ENABLE = 7111; // 1
+static const uint64_t SH_FLD_EFT_MUX_SELECT = 7112; // 1
+static const uint64_t SH_FLD_EFT_MUX_SELECT_LEN = 7113; // 1
+static const uint64_t SH_FLD_EFT_SPBC_ENABLE = 7114; // 1
+static const uint64_t SH_FLD_EG_CERR_BIT10 = 7115; // 1
+static const uint64_t SH_FLD_EG_CERR_BIT11 = 7116; // 1
+static const uint64_t SH_FLD_EG_CERR_BIT4 = 7117; // 1
+static const uint64_t SH_FLD_EG_CERR_BIT5 = 7118; // 1
+static const uint64_t SH_FLD_EG_CERR_BIT6 = 7119; // 1
+static const uint64_t SH_FLD_EG_CERR_BIT7 = 7120; // 1
+static const uint64_t SH_FLD_EG_CERR_BIT8 = 7121; // 1
+static const uint64_t SH_FLD_EG_CERR_BIT9 = 7122; // 1
+static const uint64_t SH_FLD_EG_CERR_RESET = 7123; // 1
+static const uint64_t SH_FLD_EG_CERR_UNUSEDBITS = 7124; // 1
+static const uint64_t SH_FLD_EG_CERR_UNUSEDBITS_LEN = 7125; // 1
+static const uint64_t SH_FLD_EG_ECC_CE_ERROR = 7126; // 2
+static const uint64_t SH_FLD_EG_ECC_SUE_ERROR = 7127; // 2
+static const uint64_t SH_FLD_EG_ECC_UE_ERROR = 7128; // 2
+static const uint64_t SH_FLD_EG_LOGIC_HW_ERROR = 7129; // 2
+static const uint64_t SH_FLD_EG_TRACE_GROUP_SEL_HI = 7130; // 1
+static const uint64_t SH_FLD_EG_TRACE_GROUP_SEL_HI_LEN = 7131; // 1
+static const uint64_t SH_FLD_EG_TRACE_GROUP_SEL_LO = 7132; // 1
+static const uint64_t SH_FLD_EG_TRACE_GROUP_SEL_LO_LEN = 7133; // 1
+static const uint64_t SH_FLD_EG_TRACE_INT_DATA_HI = 7134; // 2
+static const uint64_t SH_FLD_EG_TRACE_INT_DATA_LO = 7135; // 2
+static const uint64_t SH_FLD_EG_TRACE_INT_TRIG_01 = 7136; // 2
+static const uint64_t SH_FLD_EG_TRACE_INT_TRIG_23 = 7137; // 2
+static const uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_01 = 7138; // 1
+static const uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_01_LEN = 7139; // 1
+static const uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_23 = 7140; // 1
+static const uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_23_LEN = 7141; // 1
+static const uint64_t SH_FLD_EICR_PE = 7142; // 8
+static const uint64_t SH_FLD_ELEVEN_LANE_MODE = 7143; // 2
+static const uint64_t SH_FLD_EMERGENCY_M = 7144; // 8
+static const uint64_t SH_FLD_EMERGENCY_M_LEN = 7145; // 8
+static const uint64_t SH_FLD_EMERGENCY_N = 7146; // 8
+static const uint64_t SH_FLD_EMERGENCY_N_LEN = 7147; // 8
+static const uint64_t SH_FLD_EMERGENCY_THROTTLE = 7148; // 16
+static const uint64_t SH_FLD_EMER_THROTTLE_IP = 7149; // 8
+static const uint64_t SH_FLD_EN = 7150; // 53
+static const uint64_t SH_FLD_ENA = 7151; // 1
+static const uint64_t SH_FLD_ENABLE = 7152; // 259
+static const uint64_t SH_FLD_ENABLE_0 = 7153; // 5
+static const uint64_t SH_FLD_ENABLE_0_7 = 7154; // 1
+static const uint64_t SH_FLD_ENABLE_0_7_LEN = 7155; // 1
+static const uint64_t SH_FLD_ENABLE_0_LEN = 7156; // 5
+static const uint64_t SH_FLD_ENABLE_1 = 7157; // 5
+static const uint64_t SH_FLD_ENABLE_1_LEN = 7158; // 5
+static const uint64_t SH_FLD_ENABLE_2 = 7159; // 5
+static const uint64_t SH_FLD_ENABLE_2_LEN = 7160; // 5
+static const uint64_t SH_FLD_ENABLE_3 = 7161; // 5
+static const uint64_t SH_FLD_ENABLE_3_LEN = 7162; // 5
+static const uint64_t SH_FLD_ENABLE_4 = 7163; // 5
+static const uint64_t SH_FLD_ENABLE_4_LEN = 7164; // 5
+static const uint64_t SH_FLD_ENABLE_5 = 7165; // 5
+static const uint64_t SH_FLD_ENABLE_5_LEN = 7166; // 5
+static const uint64_t SH_FLD_ENABLE_6 = 7167; // 5
+static const uint64_t SH_FLD_ENABLE_64_128B_READ = 7168; // 4
+static const uint64_t SH_FLD_ENABLE_6_LEN = 7169; // 5
+static const uint64_t SH_FLD_ENABLE_7 = 7170; // 5
+static const uint64_t SH_FLD_ENABLE_7_LEN = 7171; // 5
+static const uint64_t SH_FLD_ENABLE_AGGRESSIVE_BUSY = 7172; // 8
+static const uint64_t SH_FLD_ENABLE_APO_HANG = 7173; // 4
+static const uint64_t SH_FLD_ENABLE_AUX_PORT_UNUSED = 7174; // 2
+static const uint64_t SH_FLD_ENABLE_BER_TEST = 7175; // 4
+static const uint64_t SH_FLD_ENABLE_BUSY_COUNTERS = 7176; // 8
+static const uint64_t SH_FLD_ENABLE_CENTAUR_CHECKSTOP_COMMAND = 7177; // 4
+static const uint64_t SH_FLD_ENABLE_CENTAUR_PERFMON_START_COMMAND = 7178; // 4
+static const uint64_t SH_FLD_ENABLE_CENTAUR_PERFMON_STOP_COMMAND = 7179; // 4
+static const uint64_t SH_FLD_ENABLE_CENTAUR_SYNC = 7180; // 4
+static const uint64_t SH_FLD_ENABLE_CENTAUR_TRACESTOP_COMMAND = 7181; // 4
+static const uint64_t SH_FLD_ENABLE_CLEAN = 7182; // 8
+static const uint64_t SH_FLD_ENABLE_CLIB_HANG = 7183; // 4
+static const uint64_t SH_FLD_ENABLE_CLR_ERR_CMD = 7184; // 1
+static const uint64_t SH_FLD_ENABLE_CM_COARSE_CAL = 7185; // 6
+static const uint64_t SH_FLD_ENABLE_CM_FINE_CAL = 7186; // 6
+static const uint64_t SH_FLD_ENABLE_CQ_PMU_COUNTING = 7187; // 1
+static const uint64_t SH_FLD_ENABLE_CQ_TRACE = 7188; // 1
+static const uint64_t SH_FLD_ENABLE_CRC_ECC_BPASS_NODAL_ONLY = 7189; // 4
+static const uint64_t SH_FLD_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 7190; // 6
+static const uint64_t SH_FLD_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 7191; // 6
+static const uint64_t SH_FLD_ENABLE_CTLE_COARSE_CAL = 7192; // 6
+static const uint64_t SH_FLD_ENABLE_CTLE_EDGE_OFFSET_CAL = 7193; // 2
+static const uint64_t SH_FLD_ENABLE_CTLE_EDGE_TRACK_ONLY = 7194; // 4
+static const uint64_t SH_FLD_ENABLE_DAC_H1_CAL = 7195; // 6
+static const uint64_t SH_FLD_ENABLE_DAC_H1_TO_A_CAL = 7196; // 4
+static const uint64_t SH_FLD_ENABLE_DDC = 7197; // 6
+static const uint64_t SH_FLD_ENABLE_DEBUG_BUS = 7198; // 1
+static const uint64_t SH_FLD_ENABLE_DFE_H1_CAL = 7199; // 6
+static const uint64_t SH_FLD_ENABLE_DFE_H2_H12_CAL = 7200; // 4
+static const uint64_t SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP = 7201; // 4
+static const uint64_t SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 7202; // 4
+static const uint64_t SH_FLD_ENABLE_DFE_H6_H12_FAST_MODE = 7203; // 4
+static const uint64_t SH_FLD_ENABLE_DFE_VOLTAGE_MODE = 7204; // 4
+static const uint64_t SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ = 7205; // 4
+static const uint64_t SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ = 7206; // 4
+static const uint64_t SH_FLD_ENABLE_DONE_SIGNALING = 7207; // 4
+static const uint64_t SH_FLD_ENABLE_DROOP_PROTECT_UPON_HEARTBEAT_LOSS = 7208; // 6
+static const uint64_t SH_FLD_ENABLE_DYNAMIC_PF_USAGE = 7209; // 8
+static const uint64_t SH_FLD_ENABLE_DYNAMIC_WR_USAGE = 7210; // 8
+static const uint64_t SH_FLD_ENABLE_EG_PMU_COUNTING = 7211; // 1
+static const uint64_t SH_FLD_ENABLE_EG_TRACE = 7212; // 1
+static const uint64_t SH_FLD_ENABLE_EMER_THROTTLE = 7213; // 4
+static const uint64_t SH_FLD_ENABLE_ENABLE_CRESP_PE = 7214; // 4
+static const uint64_t SH_FLD_ENABLE_ERR_INJ = 7215; // 5
+static const uint64_t SH_FLD_ENABLE_FINAL_L2U_ADJ = 7216; // 4
+static const uint64_t SH_FLD_ENABLE_FIR_HOST_ATTN = 7217; // 4
+static const uint64_t SH_FLD_ENABLE_FIR_SPEC_ATTN = 7218; // 4
+static const uint64_t SH_FLD_ENABLE_FMAX_TARGET = 7219; // 6
+static const uint64_t SH_FLD_ENABLE_FMIN_TARGET = 7220; // 6
+static const uint64_t SH_FLD_ENABLE_FSAFE_UPON_HEARTBEAT_LOSS = 7221; // 6
+static const uint64_t SH_FLD_ENABLE_GCR_OFL_BUFF = 7222; // 4
+static const uint64_t SH_FLD_ENABLE_GLB_PULSE = 7223; // 1
+static const uint64_t SH_FLD_ENABLE_GLOBAL_RUN = 7224; // 2
+static const uint64_t SH_FLD_ENABLE_H1AP_TWEAK = 7225; // 6
+static const uint64_t SH_FLD_ENABLE_HW_ERROR_RECOVERY = 7226; // 5
+static const uint64_t SH_FLD_ENABLE_INTEG_LATCH_OFFSET_CAL = 7227; // 6
+static const uint64_t SH_FLD_ENABLE_IN_PMU_COUNTING = 7228; // 1
+static const uint64_t SH_FLD_ENABLE_IN_TRACE = 7229; // 1
+static const uint64_t SH_FLD_ENABLE_IPOLL_AND_DMA = 7230; // 3
+static const uint64_t SH_FLD_ENABLE_JUMP_PROTECT = 7231; // 6
+static const uint64_t SH_FLD_ENABLE_JUMP_TARGET_UPDATE = 7232; // 6
+static const uint64_t SH_FLD_ENABLE_LEN = 7233; // 47
+static const uint64_t SH_FLD_ENABLE_MEMORY_BACKING = 7234; // 6
+static const uint64_t SH_FLD_ENABLE_MIRROR_HANG = 7235; // 4
+static const uint64_t SH_FLD_ENABLE_NONMIRROR_HANG = 7236; // 4
+static const uint64_t SH_FLD_ENABLE_OP_HIT_ERROR = 7237; // 4
+static const uint64_t SH_FLD_ENABLE_PARITY_CHECK = 7238; // 3
+static const uint64_t SH_FLD_ENABLE_PB_SWITCH_AB = 7239; // 1
+static const uint64_t SH_FLD_ENABLE_PB_SWITCH_CD = 7240; // 1
+static const uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_EXTREME_DROOP = 7241; // 6
+static const uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_HEARTBEAT_LOSS = 7242; // 6
+static const uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_IVRM_DROPOUT = 7243; // 6
+static const uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_LARGE_DROOP = 7244; // 6
+static const uint64_t SH_FLD_ENABLE_PECE = 7245; // 24
+static const uint64_t SH_FLD_ENABLE_PFETS_UPON_IVRM_DROPOUT = 7246; // 6
+static const uint64_t SH_FLD_ENABLE_PF_DROP_CMDLIST = 7247; // 4
+static const uint64_t SH_FLD_ENABLE_PF_DROP_SRQ = 7248; // 4
+static const uint64_t SH_FLD_ENABLE_PREFETCH_PROMOTE = 7249; // 4
+static const uint64_t SH_FLD_ENABLE_READ_DATA_FROM_AMOC = 7250; // 8
+static const uint64_t SH_FLD_ENABLE_READ_DATA_FROM_AMOC_LEN = 7251; // 8
+static const uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TOD = 7252; // 1
+static const uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER = 7253; // 1
+static const uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER_LEN = 7254; // 1
+static const uint64_t SH_FLD_ENABLE_REDUCE_SPEC = 7255; // 24
+static const uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_DISP = 7256; // 8
+static const uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_NSQ = 7257; // 8
+static const uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_SQ = 7258; // 8
+static const uint64_t SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS = 7259; // 3
+static const uint64_t SH_FLD_ENABLE_REMAP = 7260; // 1
+static const uint64_t SH_FLD_ENABLE_RESULT_CHECK = 7261; // 4
+static const uint64_t SH_FLD_ENABLE_RG_PMU_COUNTING = 7262; // 1
+static const uint64_t SH_FLD_ENABLE_RG_TRACE = 7263; // 1
+static const uint64_t SH_FLD_ENABLE_SCRD_FR_RXRF = 7264; // 1
+static const uint64_t SH_FLD_ENABLE_SCWR_TO_RXRF = 7265; // 1
+static const uint64_t SH_FLD_ENABLE_SCWR_TO_TXRF = 7266; // 1
+static const uint64_t SH_FLD_ENABLE_STREAMING_MODE = 7267; // 2
+static const uint64_t SH_FLD_ENABLE_TRC_GLB_TRIG0 = 7268; // 1
+static const uint64_t SH_FLD_ENABLE_TRC_GLB_TRIG1 = 7269; // 1
+static const uint64_t SH_FLD_ENABLE_TTYPE_DECODE = 7270; // 2
+static const uint64_t SH_FLD_ENABLE_VGA_AMAX_MODE = 7271; // 6
+static const uint64_t SH_FLD_ENABLE_VGA_CAL = 7272; // 6
+static const uint64_t SH_FLD_ENABLE_VGA_EDGE_OFFSET_CAL = 7273; // 2
+static const uint64_t SH_FLD_ENABLE_VITL_ALIGN_CHECK = 7274; // 43
+static const uint64_t SH_FLD_ENABLE_WAT = 7275; // 4
+static const uint64_t SH_FLD_ENABLE_WC_TRACE = 7276; // 1
+static const uint64_t SH_FLD_ENABLE_ZCAL = 7277; // 8
+static const uint64_t SH_FLD_ENA_COARSE_RD = 7278; // 8
+static const uint64_t SH_FLD_ENA_CUSTOM_RD = 7279; // 8
+static const uint64_t SH_FLD_ENA_CUSTOM_WR = 7280; // 8
+static const uint64_t SH_FLD_ENA_DIGITAL_EYE = 7281; // 8
+static const uint64_t SH_FLD_ENA_DQS_ALIGN = 7282; // 16
+static const uint64_t SH_FLD_ENA_INITIAL_COARSE_WR = 7283; // 8
+static const uint64_t SH_FLD_ENA_INITIAL_PAT_WR = 7284; // 8
+static const uint64_t SH_FLD_ENA_RANK = 7285; // 8
+static const uint64_t SH_FLD_ENA_RANK_LEN = 7286; // 8
+static const uint64_t SH_FLD_ENA_RANK_PAIR = 7287; // 16
+static const uint64_t SH_FLD_ENA_RANK_PAIR_LEN = 7288; // 16
+static const uint64_t SH_FLD_ENA_RDCLK_ALIGN = 7289; // 16
+static const uint64_t SH_FLD_ENA_READ_CTR = 7290; // 16
+static const uint64_t SH_FLD_ENA_SYSCLK_ALIGN = 7291; // 8
+static const uint64_t SH_FLD_ENA_WRITE_CTR = 7292; // 8
+static const uint64_t SH_FLD_ENA_WR_LEVEL = 7293; // 8
+static const uint64_t SH_FLD_ENA_ZCAL = 7294; // 8
+static const uint64_t SH_FLD_ENC_BUS_LANE2RPR_MANUAL = 7295; // 4
+static const uint64_t SH_FLD_ENC_BUS_LANE2RPR_MANUAL_LEN = 7296; // 4
+static const uint64_t SH_FLD_END = 7297; // 100
+static const uint64_t SH_FLD_ENDABLE_PMU_CNT_RESET = 7298; // 1
+static const uint64_t SH_FLD_ENDPOINTS = 7299; // 1
+static const uint64_t SH_FLD_END_LANE_ID = 7300; // 8
+static const uint64_t SH_FLD_END_LANE_ID_LEN = 7301; // 8
+static const uint64_t SH_FLD_END_LEN = 7302; // 36
+static const uint64_t SH_FLD_ENH_MODE_0 = 7303; // 1
+static const uint64_t SH_FLD_ENH_MODE_1 = 7304; // 1
+static const uint64_t SH_FLD_ENH_MODE_2 = 7305; // 1
+static const uint64_t SH_FLD_ENH_MODE_3 = 7306; // 1
+static const uint64_t SH_FLD_ENOP = 7307; // 43
+static const uint64_t SH_FLD_ENOP_FORCE_SG = 7308; // 43
+static const uint64_t SH_FLD_ENOP_LEN = 7309; // 43
+static const uint64_t SH_FLD_ENOP_WAIT = 7310; // 43
+static const uint64_t SH_FLD_ENOP_WAIT_LEN = 7311; // 43
+static const uint64_t SH_FLD_ENTRIES = 7312; // 1
+static const uint64_t SH_FLD_ENTRIES_LEN = 7313; // 1
+static const uint64_t SH_FLD_ENTRY = 7314; // 3
+static const uint64_t SH_FLD_ENTRY_LEN = 7315; // 3
+static const uint64_t SH_FLD_ENTRY_SEL_0_5 = 7316; // 1
+static const uint64_t SH_FLD_ENTRY_SEL_0_5_LEN = 7317; // 1
+static const uint64_t SH_FLD_EN_64_128_PB_READ = 7318; // 8
+static const uint64_t SH_FLD_EN_ALT_CR = 7319; // 8
+static const uint64_t SH_FLD_EN_ALT_ECR_ERR = 7320; // 8
+static const uint64_t SH_FLD_EN_ALT_ECR_NO_ERR = 7321; // 8
+static const uint64_t SH_FLD_EN_ATTN = 7322; // 24
+static const uint64_t SH_FLD_EN_CHARB_CMD_STALL = 7323; // 8
+static const uint64_t SH_FLD_EN_CHARB_MERGE_STALL = 7324; // 8
+static const uint64_t SH_FLD_EN_CHARB_RRQ_STALL = 7325; // 8
+static const uint64_t SH_FLD_EN_CHARB_STALL = 7326; // 4
+static const uint64_t SH_FLD_EN_CHARB_WRQ_STALL = 7327; // 8
+static const uint64_t SH_FLD_EN_DBG = 7328; // 4
+static const uint64_t SH_FLD_EN_DROP_PLS_F_FULL = 7329; // 8
+static const uint64_t SH_FLD_EN_EVENT_COUNT = 7330; // 1
+static const uint64_t SH_FLD_EN_FULL_SPEED = 7331; // 16
+static const uint64_t SH_FLD_EN_INSTRUC_TRACE = 7332; // 24
+static const uint64_t SH_FLD_EN_INTR_ADDR = 7333; // 16
+static const uint64_t SH_FLD_EN_MARKER_ACK = 7334; // 1
+static const uint64_t SH_FLD_EN_OR_DIS_WRITE_PROTECTION = 7335; // 1
+static const uint64_t SH_FLD_EN_OR_DIS_WRITE_PROTECTION_LEN = 7336; // 1
+static const uint64_t SH_FLD_EN_PF_CONF_RETRY = 7337; // 8
+static const uint64_t SH_FLD_EN_POLL_BACKOFF = 7338; // 1
+static const uint64_t SH_FLD_EN_RANDOM_BACKOFF = 7339; // 1
+static const uint64_t SH_FLD_EN_RESET_DD2_FIX_DIS = 7340; // 8
+static const uint64_t SH_FLD_EN_RESET_WR_DELAY_WL = 7341; // 8
+static const uint64_t SH_FLD_EN_RISCTRACE = 7342; // 1
+static const uint64_t SH_FLD_EN_SECOND_WRBUF = 7343; // 1
+static const uint64_t SH_FLD_EN_SLV_FAIRNESS = 7344; // 1
+static const uint64_t SH_FLD_EN_SPEC_CILD_EQD = 7345; // 1
+static const uint64_t SH_FLD_EN_SPEC_CILD_IVE = 7346; // 1
+static const uint64_t SH_FLD_EN_SPEC_CILD_VPC_HW = 7347; // 1
+static const uint64_t SH_FLD_EN_SPEC_CILD_VPC_SW = 7348; // 1
+static const uint64_t SH_FLD_EN_TRACE_EXTRA = 7349; // 16
+static const uint64_t SH_FLD_EN_TRACE_FULL_IVA = 7350; // 1
+static const uint64_t SH_FLD_EN_TRACE_STALL = 7351; // 16
+static const uint64_t SH_FLD_EN_WAIT_CYCLES = 7352; // 16
+static const uint64_t SH_FLD_EN_WT4CR_EPS_ON_LCO = 7353; // 12
+static const uint64_t SH_FLD_EN_WT4CR_EXTENDED_MODE = 7354; // 12
+static const uint64_t SH_FLD_EPH_REC_TMR_CNTL_REG_PARITY_ERRHOLD = 7355; // 2
+static const uint64_t SH_FLD_EPOCH_TEST_VECTOR = 7356; // 2
+static const uint64_t SH_FLD_EPOCH_TEST_VECTOR_LEN = 7357; // 2
+static const uint64_t SH_FLD_EPOCH_VALUE = 7358; // 2
+static const uint64_t SH_FLD_EPOCH_VALUE_LEN = 7359; // 2
+static const uint64_t SH_FLD_EPS_CNT_USE_DIVIDER_EN = 7360; // 12
+static const uint64_t SH_FLD_EPS_DIVIDER_MODE = 7361; // 12
+static const uint64_t SH_FLD_EPS_DIVIDER_MODE_LEN = 7362; // 12
+static const uint64_t SH_FLD_EPS_MODE_SEL = 7363; // 12
+static const uint64_t SH_FLD_EPS_STEP_MODE = 7364; // 12
+static const uint64_t SH_FLD_EPS_STEP_MODE_LEN = 7365; // 12
+static const uint64_t SH_FLD_EQC_CILOAD = 7366; // 1
+static const uint64_t SH_FLD_EQC_CILOAD_LEN = 7367; // 1
+static const uint64_t SH_FLD_EQC_CISTORE = 7368; // 1
+static const uint64_t SH_FLD_EQC_CISTORE_LEN = 7369; // 1
+static const uint64_t SH_FLD_EQC_DMA = 7370; // 1
+static const uint64_t SH_FLD_EQC_DMA_LEN = 7371; // 1
+static const uint64_t SH_FLD_EQC_EOI_EQP = 7372; // 1
+static const uint64_t SH_FLD_EQC_EOI_EQP_LEN = 7373; // 1
+static const uint64_t SH_FLD_EQC_EOI_ESBE = 7374; // 1
+static const uint64_t SH_FLD_EQC_EOI_ESBE_LEN = 7375; // 1
+static const uint64_t SH_FLD_EQD_BLOCK = 7376; // 1
+static const uint64_t SH_FLD_EQD_BLOCK_LEN = 7377; // 1
+static const uint64_t SH_FLD_EQD_DMA_READ = 7378; // 1
+static const uint64_t SH_FLD_EQD_DMA_READ_LEN = 7379; // 1
+static const uint64_t SH_FLD_EQD_DMA_WRITE = 7380; // 1
+static const uint64_t SH_FLD_EQD_DMA_WRITE_LEN = 7381; // 1
+static const uint64_t SH_FLD_EQD_INDEX = 7382; // 1
+static const uint64_t SH_FLD_EQD_INDEX_LEN = 7383; // 1
+static const uint64_t SH_FLD_EQ_POST = 7384; // 1
+static const uint64_t SH_FLD_EQ_POST_LEN = 7385; // 1
+static const uint64_t SH_FLD_ERAT_ARRAY_CE = 7386; // 1
+static const uint64_t SH_FLD_ERAT_ARRAY_PE = 7387; // 1
+static const uint64_t SH_FLD_ERAT_ARRAY_SUE = 7388; // 1
+static const uint64_t SH_FLD_ERAT_ARRAY_UE = 7389; // 1
+static const uint64_t SH_FLD_ERAT_CICO_HANG = 7390; // 1
+static const uint64_t SH_FLD_ERAT_CNTRL_ERR = 7391; // 1
+static const uint64_t SH_FLD_ERAT_DATA_POLL_SCALE = 7392; // 1
+static const uint64_t SH_FLD_ERAT_DATA_POLL_SCALE_LEN = 7393; // 1
+static const uint64_t SH_FLD_ERAT_LOCAL_CSTOP = 7394; // 1
+static const uint64_t SH_FLD_ERAT_MUX_SELECT = 7395; // 1
+static const uint64_t SH_FLD_ERAT_MUX_SELECT_LEN = 7396; // 1
+static const uint64_t SH_FLD_ERR = 7397; // 24
+static const uint64_t SH_FLD_ERR0_REG_DP16 = 7398; // 8
+static const uint64_t SH_FLD_ERR0_REG_DP16_LEN = 7399; // 8
+static const uint64_t SH_FLD_ERR1_REG_DP16 = 7400; // 8
+static const uint64_t SH_FLD_ERR1_REG_DP16_LEN = 7401; // 8
+static const uint64_t SH_FLD_ERR4_REG_DP16 = 7402; // 8
+static const uint64_t SH_FLD_ERR4_REG_DP16_LEN = 7403; // 8
+static const uint64_t SH_FLD_ERR5_REG_DP16 = 7404; // 8
+static const uint64_t SH_FLD_ERR5_REG_DP16_LEN = 7405; // 8
+static const uint64_t SH_FLD_ERROR = 7406; // 121
+static const uint64_t SH_FLD_ERRORS = 7407; // 43
+static const uint64_t SH_FLD_ERRORS_LEN = 7408; // 43
+static const uint64_t SH_FLD_ERROR_0 = 7409; // 1
+static const uint64_t SH_FLD_ERROR_1 = 7410; // 1
+static const uint64_t SH_FLD_ERROR_2 = 7411; // 1
+static const uint64_t SH_FLD_ERROR_3 = 7412; // 1
+static const uint64_t SH_FLD_ERROR_4 = 7413; // 1
+static const uint64_t SH_FLD_ERROR_5 = 7414; // 1
+static const uint64_t SH_FLD_ERROR_ADDR = 7415; // 4
+static const uint64_t SH_FLD_ERROR_ADDRESS = 7416; // 2
+static const uint64_t SH_FLD_ERROR_ADDRESS_LEN = 7417; // 2
+static const uint64_t SH_FLD_ERROR_ADDR_LEN = 7418; // 4
+static const uint64_t SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK = 7419; // 90
+static const uint64_t SH_FLD_ERROR_COARSE_RD = 7420; // 8
+static const uint64_t SH_FLD_ERROR_CONFIG = 7421; // 6
+static const uint64_t SH_FLD_ERROR_CONFIG0 = 7422; // 4
+static const uint64_t SH_FLD_ERROR_CONFIG0_LEN = 7423; // 4
+static const uint64_t SH_FLD_ERROR_CONFIG_LEN = 7424; // 6
+static const uint64_t SH_FLD_ERROR_COUNT_0 = 7425; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_0_LEN = 7426; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_1 = 7427; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_10 = 7428; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_10_LEN = 7429; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_11 = 7430; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_11_LEN = 7431; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_1_LEN = 7432; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_2 = 7433; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_2_LEN = 7434; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_3 = 7435; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_3_LEN = 7436; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_4 = 7437; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_4_LEN = 7438; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_5 = 7439; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_5_LEN = 7440; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_6 = 7441; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_6_LEN = 7442; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_7 = 7443; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_7_LEN = 7444; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_8 = 7445; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_8_LEN = 7446; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_9 = 7447; // 10
+static const uint64_t SH_FLD_ERROR_COUNT_9_LEN = 7448; // 10
+static const uint64_t SH_FLD_ERROR_CUSTOM_RD = 7449; // 8
+static const uint64_t SH_FLD_ERROR_CUSTOM_WR = 7450; // 8
+static const uint64_t SH_FLD_ERROR_DIGITAL_EYE = 7451; // 8
+static const uint64_t SH_FLD_ERROR_DQS_ALIGN = 7452; // 8
+static const uint64_t SH_FLD_ERROR_INITIAL_COARSE_WR = 7453; // 8
+static const uint64_t SH_FLD_ERROR_INITIAL_PAT_WRITE = 7454; // 8
+static const uint64_t SH_FLD_ERROR_INJECT = 7455; // 1
+static const uint64_t SH_FLD_ERROR_INJECT_ENABLE = 7456; // 1
+static const uint64_t SH_FLD_ERROR_INJECT_LEN = 7457; // 1
+static const uint64_t SH_FLD_ERROR_LEN = 7458; // 23
+static const uint64_t SH_FLD_ERROR_MASK = 7459; // 43
+static const uint64_t SH_FLD_ERROR_MASK_LEN = 7460; // 43
+static const uint64_t SH_FLD_ERROR_PULSE_OR_LEVEL = 7461; // 24
+static const uint64_t SH_FLD_ERROR_RATE = 7462; // 10
+static const uint64_t SH_FLD_ERROR_RATE_LEN = 7463; // 10
+static const uint64_t SH_FLD_ERROR_RDCLK_ALIGN = 7464; // 8
+static const uint64_t SH_FLD_ERROR_READ_CTR = 7465; // 8
+static const uint64_t SH_FLD_ERROR_RECOVERY_COMPLETE = 7466; // 2
+static const uint64_t SH_FLD_ERROR_RECOVERY_INITIATED = 7467; // 2
+static const uint64_t SH_FLD_ERROR_STATE = 7468; // 4
+static const uint64_t SH_FLD_ERROR_VREF = 7469; // 8
+static const uint64_t SH_FLD_ERROR_WRITE_CTR = 7470; // 8
+static const uint64_t SH_FLD_ERROR_WR_LEVEL = 7471; // 8
+static const uint64_t SH_FLD_ERRS = 7472; // 256
+static const uint64_t SH_FLD_ERRS_INJ = 7473; // 4
+static const uint64_t SH_FLD_ERRS_INJ_LEN = 7474; // 4
+static const uint64_t SH_FLD_ERRS_LEN = 7475; // 140
+static const uint64_t SH_FLD_ERR_ADDR_BEYOND_RANGE = 7476; // 1
+static const uint64_t SH_FLD_ERR_ADDR_OVERLAP = 7477; // 1
+static const uint64_t SH_FLD_ERR_BRK0 = 7478; // 1
+static const uint64_t SH_FLD_ERR_BRK0_LEN = 7479; // 1
+static const uint64_t SH_FLD_ERR_BRK1 = 7480; // 1
+static const uint64_t SH_FLD_ERR_BRK1_LEN = 7481; // 1
+static const uint64_t SH_FLD_ERR_BRK2 = 7482; // 1
+static const uint64_t SH_FLD_ERR_BRK2_LEN = 7483; // 1
+static const uint64_t SH_FLD_ERR_BRK3 = 7484; // 1
+static const uint64_t SH_FLD_ERR_BRK3_LEN = 7485; // 1
+static const uint64_t SH_FLD_ERR_BRK4 = 7486; // 1
+static const uint64_t SH_FLD_ERR_BRK4_LEN = 7487; // 1
+static const uint64_t SH_FLD_ERR_BRK5 = 7488; // 1
+static const uint64_t SH_FLD_ERR_BRK5_LEN = 7489; // 1
+static const uint64_t SH_FLD_ERR_CMD_OVERRUN = 7490; // 1
+static const uint64_t SH_FLD_ERR_CQ = 7491; // 16
+static const uint64_t SH_FLD_ERR_CQ_LEN = 7492; // 16
+static const uint64_t SH_FLD_ERR_DETAIL = 7493; // 16
+static const uint64_t SH_FLD_ERR_DETAIL_LEN = 7494; // 16
+static const uint64_t SH_FLD_ERR_FSM_DP16 = 7495; // 8
+static const uint64_t SH_FLD_ERR_FSM_DP16_LEN = 7496; // 8
+static const uint64_t SH_FLD_ERR_INJ = 7497; // 252
+static const uint64_t SH_FLD_ERR_INJ_ACTION = 7498; // 2
+static const uint64_t SH_FLD_ERR_INJ_ARRAY_SEL = 7499; // 2
+static const uint64_t SH_FLD_ERR_INJ_ARRAY_SEL_LEN = 7500; // 2
+static const uint64_t SH_FLD_ERR_INJ_A_BER_SEL = 7501; // 6
+static const uint64_t SH_FLD_ERR_INJ_A_BER_SEL_LEN = 7502; // 6
+static const uint64_t SH_FLD_ERR_INJ_A_COARSE_SEL = 7503; // 6
+static const uint64_t SH_FLD_ERR_INJ_A_COARSE_SEL_LEN = 7504; // 6
+static const uint64_t SH_FLD_ERR_INJ_A_ENABLE = 7505; // 116
+static const uint64_t SH_FLD_ERR_INJ_A_FINE_SEL = 7506; // 6
+static const uint64_t SH_FLD_ERR_INJ_A_FINE_SEL_LEN = 7507; // 6
+static const uint64_t SH_FLD_ERR_INJ_B_BER_SEL = 7508; // 6
+static const uint64_t SH_FLD_ERR_INJ_B_BER_SEL_LEN = 7509; // 6
+static const uint64_t SH_FLD_ERR_INJ_B_COARSE_SEL = 7510; // 6
+static const uint64_t SH_FLD_ERR_INJ_B_COARSE_SEL_LEN = 7511; // 6
+static const uint64_t SH_FLD_ERR_INJ_B_ENABLE = 7512; // 116
+static const uint64_t SH_FLD_ERR_INJ_B_FINE_SEL = 7513; // 6
+static const uint64_t SH_FLD_ERR_INJ_B_FINE_SEL_LEN = 7514; // 6
+static const uint64_t SH_FLD_ERR_INJ_CLOCK_ENABLE = 7515; // 6
+static const uint64_t SH_FLD_ERR_INJ_ENABLE = 7516; // 8
+static const uint64_t SH_FLD_ERR_INJ_LEN = 7517; // 136
+static const uint64_t SH_FLD_ERR_INJ_SLS_ALL_CMD = 7518; // 4
+static const uint64_t SH_FLD_ERR_INJ_SLS_CMD = 7519; // 4
+static const uint64_t SH_FLD_ERR_INJ_SLS_CMD_LEN = 7520; // 4
+static const uint64_t SH_FLD_ERR_INJ_SLS_MODE = 7521; // 4
+static const uint64_t SH_FLD_ERR_INJ_SLS_RECAL = 7522; // 4
+static const uint64_t SH_FLD_ERR_INJ_STATUS = 7523; // 2
+static const uint64_t SH_FLD_ERR_INJ_TYPE = 7524; // 2
+static const uint64_t SH_FLD_ERR_LVL = 7525; // 16
+static const uint64_t SH_FLD_ERR_LVL_LEN = 7526; // 16
+static const uint64_t SH_FLD_ERR_RSVD0 = 7527; // 16
+static const uint64_t SH_FLD_ERR_RSVD0_LEN = 7528; // 16
+static const uint64_t SH_FLD_ERR_SET0 = 7529; // 8
+static const uint64_t SH_FLD_ERR_SET1 = 7530; // 8
+static const uint64_t SH_FLD_ERR_SET2 = 7531; // 8
+static const uint64_t SH_FLD_ERR_SET3 = 7532; // 8
+static const uint64_t SH_FLD_ERR_SET4 = 7533; // 8
+static const uint64_t SH_FLD_ERR_SET5 = 7534; // 8
+static const uint64_t SH_FLD_ERR_VLD = 7535; // 16
+static const uint64_t SH_FLD_ESB_OR_LSI_INTERRUPTS = 7536; // 1
+static const uint64_t SH_FLD_ESC1_PRIORITY = 7537; // 1
+static const uint64_t SH_FLD_ESC1_PRIORITY_LEN = 7538; // 1
+static const uint64_t SH_FLD_ESC1_RSD = 7539; // 1
+static const uint64_t SH_FLD_ESC1_RSD_LEN = 7540; // 1
+static const uint64_t SH_FLD_ESC2_PRIORITY = 7541; // 1
+static const uint64_t SH_FLD_ESC2_PRIORITY_LEN = 7542; // 1
+static const uint64_t SH_FLD_ESC2_RSD = 7543; // 1
+static const uint64_t SH_FLD_ESC2_RSD_LEN = 7544; // 1
+static const uint64_t SH_FLD_ESCAPE_ADDRESS = 7545; // 1
+static const uint64_t SH_FLD_ESCAPE_ADDRESS_LEN = 7546; // 1
+static const uint64_t SH_FLD_ESR_RSVD_19 = 7547; // 1
+static const uint64_t SH_FLD_EVENT = 7548; // 6
+static const uint64_t SH_FLD_EVENT0 = 7549; // 21
+static const uint64_t SH_FLD_EVENT0_COUNTER = 7550; // 8
+static const uint64_t SH_FLD_EVENT0_COUNTER_LEN = 7551; // 8
+static const uint64_t SH_FLD_EVENT0_LEN = 7552; // 21
+static const uint64_t SH_FLD_EVENT0_SEL = 7553; // 2
+static const uint64_t SH_FLD_EVENT1 = 7554; // 21
+static const uint64_t SH_FLD_EVENT1_COUNTER = 7555; // 8
+static const uint64_t SH_FLD_EVENT1_COUNTER_LEN = 7556; // 8
+static const uint64_t SH_FLD_EVENT1_LEN = 7557; // 21
+static const uint64_t SH_FLD_EVENT1_SEL = 7558; // 2
+static const uint64_t SH_FLD_EVENT1_SEL_LEN = 7559; // 2
+static const uint64_t SH_FLD_EVENT2 = 7560; // 21
+static const uint64_t SH_FLD_EVENT2HALT_DELAY = 7561; // 1
+static const uint64_t SH_FLD_EVENT2HALT_DELAY_LEN = 7562; // 1
+static const uint64_t SH_FLD_EVENT2HALT_EN = 7563; // 1
+static const uint64_t SH_FLD_EVENT2HALT_EN_LEN = 7564; // 1
+static const uint64_t SH_FLD_EVENT2HALT_GPE0 = 7565; // 1
+static const uint64_t SH_FLD_EVENT2HALT_GPE1 = 7566; // 1
+static const uint64_t SH_FLD_EVENT2HALT_GPE2 = 7567; // 1
+static const uint64_t SH_FLD_EVENT2HALT_GPE3 = 7568; // 1
+static const uint64_t SH_FLD_EVENT2HALT_HALT_STATE = 7569; // 1
+static const uint64_t SH_FLD_EVENT2HALT_MODE = 7570; // 1
+static const uint64_t SH_FLD_EVENT2HALT_MODE_LEN = 7571; // 1
+static const uint64_t SH_FLD_EVENT2HALT_OCC = 7572; // 1
+static const uint64_t SH_FLD_EVENT2_COUNTER = 7573; // 8
+static const uint64_t SH_FLD_EVENT2_COUNTER_LEN = 7574; // 8
+static const uint64_t SH_FLD_EVENT2_LEN = 7575; // 21
+static const uint64_t SH_FLD_EVENT2_SEL = 7576; // 2
+static const uint64_t SH_FLD_EVENT2_SEL_LEN = 7577; // 2
+static const uint64_t SH_FLD_EVENT3 = 7578; // 21
+static const uint64_t SH_FLD_EVENT3_COUNTER = 7579; // 8
+static const uint64_t SH_FLD_EVENT3_COUNTER_LEN = 7580; // 8
+static const uint64_t SH_FLD_EVENT3_LEN = 7581; // 21
+static const uint64_t SH_FLD_EVENT3_SEL = 7582; // 2
+static const uint64_t SH_FLD_EVENT3_SEL_LEN = 7583; // 2
+static const uint64_t SH_FLD_EVENTCNT = 7584; // 3
+static const uint64_t SH_FLD_EVENTCNT_LEN = 7585; // 3
+static const uint64_t SH_FLD_EVENT_BUS_EN = 7586; // 4
+static const uint64_t SH_FLD_EVENT_BUS_ENABLE = 7587; // 4
+static const uint64_t SH_FLD_EVENT_BUS_EN_LEN = 7588; // 4
+static const uint64_t SH_FLD_EVENT_BUS_SELECTS = 7589; // 12
+static const uint64_t SH_FLD_EVENT_BUS_SELECTS_LEN = 7590; // 12
+static const uint64_t SH_FLD_EVENT_LEN = 7591; // 6
+static const uint64_t SH_FLD_EVENT_MUX_SELECTS = 7592; // 24
+static const uint64_t SH_FLD_EVENT_MUX_SELECTS_LEN = 7593; // 24
+static const uint64_t SH_FLD_EXACT_RESET_C3_ON_TO = 7594; // 86
+static const uint64_t SH_FLD_EXACT_TO_MODE = 7595; // 86
+static const uint64_t SH_FLD_EXBIST_MODE = 7596; // 6
+static const uint64_t SH_FLD_EXIT_1 = 7597; // 128
+static const uint64_t SH_FLD_EXIT_CRITERION_A_N = 7598; // 96
+static const uint64_t SH_FLD_EXTADDR = 7599; // 6
+static const uint64_t SH_FLD_EXTADDR_LEN = 7600; // 6
+static const uint64_t SH_FLD_EXTERNAL_ERROR = 7601; // 1
+static const uint64_t SH_FLD_EXTERNAL_TRAP = 7602; // 2
+static const uint64_t SH_FLD_EXTERNAL_TRAP_MASK = 7603; // 1
+static const uint64_t SH_FLD_EXTERNAL_XSTOP = 7604; // 4
+static const uint64_t SH_FLD_EXTRA_CMD_SPACING_0_2 = 7605; // 1
+static const uint64_t SH_FLD_EXTRA_CMD_SPACING_0_2_LEN = 7606; // 1
+static const uint64_t SH_FLD_EXTRA_DAT_SPACING_0_3 = 7607; // 1
+static const uint64_t SH_FLD_EXTRA_DAT_SPACING_0_3_LEN = 7608; // 1
+static const uint64_t SH_FLD_EXTREME_DROOP_EVENT_CTR = 7609; // 12
+static const uint64_t SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN = 7610; // 12
+static const uint64_t SH_FLD_EXTREME_EVENT_THRESHOLD = 7611; // 12
+static const uint64_t SH_FLD_EXTREME_EVENT_THRESHOLD_LEN = 7612; // 12
+static const uint64_t SH_FLD_EXT_EBB_EXIT_ENABLE = 7613; // 96
+static const uint64_t SH_FLD_EXT_EXIT_ENABLE = 7614; // 96
+static const uint64_t SH_FLD_EXT_INTERRUPT = 7615; // 1
+static const uint64_t SH_FLD_EXT_RESUME_EXIT_ENABLE = 7616; // 96
+static const uint64_t SH_FLD_EXT_TRIG_ON_FREEZE = 7617; // 43
+static const uint64_t SH_FLD_EXT_TRIG_ON_STOP = 7618; // 43
+static const uint64_t SH_FLD_EYE_OPT_DONE = 7619; // 4
+static const uint64_t SH_FLD_EYE_OPT_FAILED = 7620; // 4
+static const uint64_t SH_FLD_E_BIST_EN = 7621; // 2
+static const uint64_t SH_FLD_E_CONTROLS = 7622; // 48
+static const uint64_t SH_FLD_E_CONTROLS_LEN = 7623; // 48
+static const uint64_t SH_FLD_E_CTLE_COARSE = 7624; // 48
+static const uint64_t SH_FLD_E_CTLE_COARSE_LEN = 7625; // 48
+static const uint64_t SH_FLD_E_CTLE_GAIN = 7626; // 48
+static const uint64_t SH_FLD_E_CTLE_GAIN_LEN = 7627; // 48
+static const uint64_t SH_FLD_E_EVEN_INTEG_FINE_GAIN = 7628; // 48
+static const uint64_t SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN = 7629; // 48
+static const uint64_t SH_FLD_E_INTEG_COARSE_GAIN = 7630; // 48
+static const uint64_t SH_FLD_E_INTEG_COARSE_GAIN_LEN = 7631; // 48
+static const uint64_t SH_FLD_E_ODD_INTEG_FINE_GAIN = 7632; // 48
+static const uint64_t SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN = 7633; // 48
+static const uint64_t SH_FLD_E_OFFSET = 7634; // 48
+static const uint64_t SH_FLD_E_OFFSET_E = 7635; // 48
+static const uint64_t SH_FLD_E_OFFSET_E_LEN = 7636; // 48
+static const uint64_t SH_FLD_E_OFFSET_LEN = 7637; // 48
+static const uint64_t SH_FLD_E_TARG_MIN = 7638; // 1
+static const uint64_t SH_FLD_E_TARG_MIN_LEN = 7639; // 1
+static const uint64_t SH_FLD_FACTOR = 7640; // 24
+static const uint64_t SH_FLD_FACTOR_LEN = 7641; // 24
+static const uint64_t SH_FLD_FAIL = 7642; // 4
+static const uint64_t SH_FLD_FAILED = 7643; // 8
+static const uint64_t SH_FLD_FAILED_LEN = 7644; // 8
+static const uint64_t SH_FLD_FAILED_LINK_ON_INTERRUPT = 7645; // 1
+static const uint64_t SH_FLD_FAILING_OPB_MASTER_ACT = 7646; // 3
+static const uint64_t SH_FLD_FAILING_OPB_MASTER_ACT_LEN = 7647; // 3
+static const uint64_t SH_FLD_FAILING_OPB_MASTER_FRST = 7648; // 3
+static const uint64_t SH_FLD_FAILING_OPB_MASTER_FRST_LEN = 7649; // 3
+static const uint64_t SH_FLD_FAIL_RCD = 7650; // 2
+static const uint64_t SH_FLD_FAIL_REG = 7651; // 1
+static const uint64_t SH_FLD_FAIL_REG_LEN = 7652; // 1
+static const uint64_t SH_FLD_FAIL_TYPE = 7653; // 2
+static const uint64_t SH_FLD_FAIL_TYPE_LEN = 7654; // 2
+static const uint64_t SH_FLD_FARB_CAL_RECVFSM_1HOT = 7655; // 8
+static const uint64_t SH_FLD_FARB_CMD_PE_HOLD_OUT = 7656; // 8
+static const uint64_t SH_FLD_FARB_PE = 7657; // 8
+static const uint64_t SH_FLD_FARR = 7658; // 43
+static const uint64_t SH_FLD_FASTPATH_LIMIT = 7659; // 8
+static const uint64_t SH_FLD_FASTPATH_LIMIT_LEN = 7660; // 8
+static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_0 = 7661; // 1
+static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_0_LEN = 7662; // 1
+static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_1 = 7663; // 1
+static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_1_LEN = 7664; // 1
+static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_2 = 7665; // 1
+static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_2_LEN = 7666; // 1
+static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_3 = 7667; // 1
+static const uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_3_LEN = 7668; // 1
+static const uint64_t SH_FLD_FAST_SB_LOOKUP_DISABLE = 7669; // 1
+static const uint64_t SH_FLD_FAST_SIM_CNTR = 7670; // 8
+static const uint64_t SH_FLD_FATAL_CNFG_HOLD_OUT = 7671; // 2
+static const uint64_t SH_FLD_FBC = 7672; // 2
+static const uint64_t SH_FLD_FBC_ADDRESS = 7673; // 1
+static const uint64_t SH_FLD_FBC_ADDRESS_ERROR = 7674; // 1
+static const uint64_t SH_FLD_FBC_ADDRESS_LEN = 7675; // 1
+static const uint64_t SH_FLD_FBC_ADDR_DONE = 7676; // 1
+static const uint64_t SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT = 7677; // 1
+static const uint64_t SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN = 7678; // 1
+static const uint64_t SH_FLD_FBC_AUTOINC_ERROR = 7679; // 1
+static const uint64_t SH_FLD_FBC_AUTO_INC = 7680; // 1
+static const uint64_t SH_FLD_FBC_AXTYPE = 7681; // 1
+static const uint64_t SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT = 7682; // 1
+static const uint64_t SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT_LEN = 7683; // 1
+static const uint64_t SH_FLD_FBC_BUS0_STG0_SEL = 7684; // 1
+static const uint64_t SH_FLD_FBC_BUS0_STG0_SEL_LEN = 7685; // 1
+static const uint64_t SH_FLD_FBC_BUS0_STG1_SEL = 7686; // 1
+static const uint64_t SH_FLD_FBC_BUS0_STG2_SEL = 7687; // 1
+static const uint64_t SH_FLD_FBC_BUS1_STG0_SEL = 7688; // 1
+static const uint64_t SH_FLD_FBC_BUS1_STG0_SEL_LEN = 7689; // 1
+static const uint64_t SH_FLD_FBC_BUS1_STG1_SEL = 7690; // 1
+static const uint64_t SH_FLD_FBC_BUS1_STG2_SEL = 7691; // 1
+static const uint64_t SH_FLD_FBC_CLEAR_STATUS = 7692; // 1
+static const uint64_t SH_FLD_FBC_CMD_PROT_ERR_CHK_DIS = 7693; // 1
+static const uint64_t SH_FLD_FBC_COMMAND_ERROR = 7694; // 1
+static const uint64_t SH_FLD_FBC_CQRD_ARY_ECC_CE_DET = 7695; // 1
+static const uint64_t SH_FLD_FBC_CQRD_ARY_ECC_SUE_DET = 7696; // 1
+static const uint64_t SH_FLD_FBC_CQRD_ARY_ECC_UE_DET = 7697; // 1
+static const uint64_t SH_FLD_FBC_CRESP_VALUE = 7698; // 1
+static const uint64_t SH_FLD_FBC_CRESP_VALUE_LEN = 7699; // 1
+static const uint64_t SH_FLD_FBC_DATA_DONE = 7700; // 1
+static const uint64_t SH_FLD_FBC_DATA_ONLY = 7701; // 1
+static const uint64_t SH_FLD_FBC_DIN_ECC_CHK_DIS = 7702; // 1
+static const uint64_t SH_FLD_FBC_DISABLE = 7703; // 1
+static const uint64_t SH_FLD_FBC_DISABLE_LOCAL_SHORTCUT = 7704; // 1
+static const uint64_t SH_FLD_FBC_DROP_PRIORITY = 7705; // 1
+static const uint64_t SH_FLD_FBC_DROP_PRIORITY_MAX = 7706; // 1
+static const uint64_t SH_FLD_FBC_ECC_CE = 7707; // 1
+static const uint64_t SH_FLD_FBC_ECC_SUE = 7708; // 1
+static const uint64_t SH_FLD_FBC_ECC_UE = 7709; // 1
+static const uint64_t SH_FLD_FBC_INV_AMORT_DIS = 7710; // 1
+static const uint64_t SH_FLD_FBC_LEN = 7711; // 2
+static const uint64_t SH_FLD_FBC_LFSR_DIS = 7712; // 1
+static const uint64_t SH_FLD_FBC_LOCKED = 7713; // 1
+static const uint64_t SH_FLD_FBC_LOCK_ID = 7714; // 1
+static const uint64_t SH_FLD_FBC_LOCK_ID_LEN = 7715; // 1
+static const uint64_t SH_FLD_FBC_LXSTOP_ERR_DET = 7716; // 1
+static const uint64_t SH_FLD_FBC_OVERRUN_ERROR = 7717; // 1
+static const uint64_t SH_FLD_FBC_OVERWRITE_PBINIT = 7718; // 1
+static const uint64_t SH_FLD_FBC_PBINIT_MISSING = 7719; // 1
+static const uint64_t SH_FLD_FBC_PB_DATA_HANG_ERR = 7720; // 1
+static const uint64_t SH_FLD_FBC_PB_OP_HANG_ERR = 7721; // 1
+static const uint64_t SH_FLD_FBC_PB_UNEXPECT_CRESP_ERR = 7722; // 1
+static const uint64_t SH_FLD_FBC_PB_UNEXPECT_DATA_ERR = 7723; // 1
+static const uint64_t SH_FLD_FBC_PIB_DIRECT = 7724; // 1
+static const uint64_t SH_FLD_FBC_PIB_DIRECT_DONE = 7725; // 1
+static const uint64_t SH_FLD_FBC_PIB_ERROR = 7726; // 1
+static const uint64_t SH_FLD_FBC_PIB_ERROR_LEN = 7727; // 1
+static const uint64_t SH_FLD_FBC_RESET = 7728; // 1
+static const uint64_t SH_FLD_FBC_RESET_FSM = 7729; // 1
+static const uint64_t SH_FLD_FBC_RNW = 7730; // 1
+static const uint64_t SH_FLD_FBC_SCOPE = 7731; // 1
+static const uint64_t SH_FLD_FBC_SCOPE_LEN = 7732; // 1
+static const uint64_t SH_FLD_FBC_SNP_PROT_ERR_CHK_DIS = 7733; // 1
+static const uint64_t SH_FLD_FBC_SNP_TIMEOUT_CHK_DIS = 7734; // 1
+static const uint64_t SH_FLD_FBC_START_OP = 7735; // 1
+static const uint64_t SH_FLD_FBC_TSIZE = 7736; // 1
+static const uint64_t SH_FLD_FBC_TSIZE_LEN = 7737; // 1
+static const uint64_t SH_FLD_FBC_TTYPE = 7738; // 1
+static const uint64_t SH_FLD_FBC_TTYPE_LEN = 7739; // 1
+static const uint64_t SH_FLD_FBC_WAIT_CMD_ARBIT = 7740; // 1
+static const uint64_t SH_FLD_FBC_WAIT_PIB_DIRECT = 7741; // 1
+static const uint64_t SH_FLD_FBC_WAIT_RESP = 7742; // 1
+static const uint64_t SH_FLD_FBC_WITH_PBINIT_LOW_WAIT = 7743; // 1
+static const uint64_t SH_FLD_FBC_WITH_POST_INIT = 7744; // 1
+static const uint64_t SH_FLD_FBC_WITH_PRE_QUIESCE = 7745; // 1
+static const uint64_t SH_FLD_FBC_WITH_TM_QUIESCE = 7746; // 1
+static const uint64_t SH_FLD_FBC_XLAT_ARY_ECC_CE_DET = 7747; // 1
+static const uint64_t SH_FLD_FBC_XLAT_ARY_ECC_SUE_DET = 7748; // 1
+static const uint64_t SH_FLD_FBC_XLAT_ARY_ECC_UE_DET = 7749; // 1
+static const uint64_t SH_FLD_FBC_XLAT_ECC_CHK_DIS = 7750; // 1
+static const uint64_t SH_FLD_FBC_XLAT_PROT_ERR_CHK_DIS = 7751; // 1
+static const uint64_t SH_FLD_FBC_XLAT_PROT_ERR_DET = 7752; // 1
+static const uint64_t SH_FLD_FBC_XLAT_TIMEOUT_CHK_DIS = 7753; // 1
+static const uint64_t SH_FLD_FBC_XLAT_TIMEOUT_DET = 7754; // 1
+static const uint64_t SH_FLD_FENCE = 7755; // 4
+static const uint64_t SH_FLD_FENCE0 = 7756; // 15
+static const uint64_t SH_FLD_FENCE0_DC = 7757; // 3
+static const uint64_t SH_FLD_FENCE0_LEN = 7758; // 15
+static const uint64_t SH_FLD_FENCE1 = 7759; // 15
+static const uint64_t SH_FLD_FENCE1_DC = 7760; // 3
+static const uint64_t SH_FLD_FENCE1_LEN = 7761; // 15
+static const uint64_t SH_FLD_FENCE2_DC = 7762; // 3
+static const uint64_t SH_FLD_FENCE3_DC = 7763; // 3
+static const uint64_t SH_FLD_FENCE4_DC = 7764; // 3
+static const uint64_t SH_FLD_FENCE5_DC = 7765; // 3
+static const uint64_t SH_FLD_FENCE6_DC = 7766; // 3
+static const uint64_t SH_FLD_FENCE_EISR = 7767; // 24
+static const uint64_t SH_FLD_FENCE_EN = 7768; // 43
+static const uint64_t SH_FLD_FENCE_GX_INTERFACE = 7769; // 1
+static const uint64_t SH_FLD_FENCE_IO_INTERFACE = 7770; // 1
+static const uint64_t SH_FLD_FENCE_TLBIE = 7771; // 12
+static const uint64_t SH_FLD_FFE_BOOST_EN = 7772; // 6
+static const uint64_t SH_FLD_FF_BYPASS = 7773; // 6
+static const uint64_t SH_FLD_FF_SLEWRATE = 7774; // 6
+static const uint64_t SH_FLD_FF_SLEWRATE_LEN = 7775; // 6
+static const uint64_t SH_FLD_FGAT_0 = 7776; // 2
+static const uint64_t SH_FLD_FGAT_1 = 7777; // 1
+static const uint64_t SH_FLD_FGAT_2 = 7778; // 1
+static const uint64_t SH_FLD_FGAT_3 = 7779; // 1
+static const uint64_t SH_FLD_FIELD = 7780; // 9
+static const uint64_t SH_FLD_FIELD_LEN = 7781; // 9
+static const uint64_t SH_FLD_FIFO_BITS_READ0_0 = 7782; // 3
+static const uint64_t SH_FLD_FIFO_BITS_READ0_0_LEN = 7783; // 3
+static const uint64_t SH_FLD_FIFO_BITS_READ0_1 = 7784; // 2
+static const uint64_t SH_FLD_FIFO_BITS_READ0_1_LEN = 7785; // 2
+static const uint64_t SH_FLD_FIFO_BITS_READ0_2 = 7786; // 2
+static const uint64_t SH_FLD_FIFO_BITS_READ0_2_LEN = 7787; // 2
+static const uint64_t SH_FLD_FIFO_BITS_READ0_3 = 7788; // 2
+static const uint64_t SH_FLD_FIFO_BITS_READ0_3_LEN = 7789; // 2
+static const uint64_t SH_FLD_FIFO_DLY_CFG = 7790; // 120
+static const uint64_t SH_FLD_FIFO_DLY_CFG_LEN = 7791; // 120
+static const uint64_t SH_FLD_FIFO_EMPTY = 7792; // 1
+static const uint64_t SH_FLD_FIFO_ENTRY_COUNT = 7793; // 1
+static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_0 = 7794; // 2
+static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_0_LEN = 7795; // 2
+static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_1 = 7796; // 1
+static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_1_LEN = 7797; // 1
+static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_2 = 7798; // 1
+static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_2_LEN = 7799; // 1
+static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_3 = 7800; // 1
+static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_3_LEN = 7801; // 1
+static const uint64_t SH_FLD_FIFO_ENTRY_COUNT_LEN = 7802; // 1
+static const uint64_t SH_FLD_FIFO_EOT_FLAGS = 7803; // 1
+static const uint64_t SH_FLD_FIFO_EOT_FLAGS_LEN = 7804; // 1
+static const uint64_t SH_FLD_FIFO_FINAL_L2U_DLY = 7805; // 4
+static const uint64_t SH_FLD_FIFO_FINAL_L2U_DLY_LEN = 7806; // 4
+static const uint64_t SH_FLD_FIFO_FULL = 7807; // 7
+static const uint64_t SH_FLD_FIFO_HALF_WIDTH_MODE = 7808; // 140
+static const uint64_t SH_FLD_FIFO_INITIAL_L2U_DLY = 7809; // 4
+static const uint64_t SH_FLD_FIFO_INITIAL_L2U_DLY_LEN = 7810; // 4
+static const uint64_t SH_FLD_FIFO_L2U_DLY = 7811; // 188
+static const uint64_t SH_FLD_FIFO_L2U_DLY_LEN = 7812; // 188
+static const uint64_t SH_FLD_FIFO_VALID_FLAGS = 7813; // 1
+static const uint64_t SH_FLD_FIFO_VALID_FLAGS_LEN = 7814; // 1
+static const uint64_t SH_FLD_FILTDIVSEL = 7815; // 3
+static const uint64_t SH_FLD_FILTDIVSEL_LEN = 7816; // 3
+static const uint64_t SH_FLD_FILTER = 7817; // 2
+static const uint64_t SH_FLD_FILTER_LEN = 7818; // 2
+static const uint64_t SH_FLD_FILTER_MODE = 7819; // 6
+static const uint64_t SH_FLD_FILTER_MODE_LEN = 7820; // 6
+static const uint64_t SH_FLD_FINAL_VDM_DATA01 = 7821; // 12
+static const uint64_t SH_FLD_FINAL_VDM_DATA01_LEN = 7822; // 12
+static const uint64_t SH_FLD_FINE_CAL_STEP_SIZE = 7823; // 8
+static const uint64_t SH_FLD_FINE_CAL_STEP_SIZE_LEN = 7824; // 8
+static const uint64_t SH_FLD_FIR = 7825; // 48
+static const uint64_t SH_FLD_FIR0_CR0_ATAG_PERR = 7826; // 12
+static const uint64_t SH_FLD_FIR0_CR0_TTAG_PERR = 7827; // 12
+static const uint64_t SH_FLD_FIR0_CR1_ATAG_PERR = 7828; // 12
+static const uint64_t SH_FLD_FIR0_CR1_TTAG_PERR = 7829; // 12
+static const uint64_t SH_FLD_FIR0_CR2_ATAG_PERR = 7830; // 12
+static const uint64_t SH_FLD_FIR0_CR2_TTAG_PERR = 7831; // 12
+static const uint64_t SH_FLD_FIR0_CR3_ATAG_PERR = 7832; // 12
+static const uint64_t SH_FLD_FIR0_CR3_TTAG_PERR = 7833; // 12
+static const uint64_t SH_FLD_FIR0_ILLEGAL_STORE_SIZE = 7834; // 12
+static const uint64_t SH_FLD_FIR0_IMA_FSM_TIMEOUT = 7835; // 12
+static const uint64_t SH_FLD_FIR0_LD_AMO_SEQ = 7836; // 12
+static const uint64_t SH_FLD_FIR0_OVERFLOW = 7837; // 12
+static const uint64_t SH_FLD_FIR0_PBARB_TRASHMODE = 7838; // 12
+static const uint64_t SH_FLD_FIR0_PPE_RD_FSM_TIMEOUT = 7839; // 12
+static const uint64_t SH_FLD_FIR0_PPE_WR_FSM_TIMEOUT = 7840; // 12
+static const uint64_t SH_FLD_FIR0_PURGE_ABORT_LVL_ERR1 = 7841; // 12
+static const uint64_t SH_FLD_FIR0_PURGE_ABORT_LVL_ERR2 = 7842; // 12
+static const uint64_t SH_FLD_FIR0_PURGE_DONE_LVL_ERR1 = 7843; // 12
+static const uint64_t SH_FLD_FIR0_PURGE_LVL_ERR1 = 7844; // 12
+static const uint64_t SH_FLD_FIR0_PURGE_LVL_ERR2 = 7845; // 12
+static const uint64_t SH_FLD_FIR0_SNP0_ADDR_PERR = 7846; // 12
+static const uint64_t SH_FLD_FIR0_SNP0_TTAG_PERR = 7847; // 12
+static const uint64_t SH_FLD_FIR0_SNP1_ADDR_PERR = 7848; // 12
+static const uint64_t SH_FLD_FIR0_SNP1_TTAG_PERR = 7849; // 12
+static const uint64_t SH_FLD_FIR0_TLB_DATA_PAR = 7850; // 12
+static const uint64_t SH_FLD_FIR11_LRU_MEM_INVALID_ABCD = 7851; // 12
+static const uint64_t SH_FLD_FIR11_LRU_MEM_INVALID_EFGH = 7852; // 12
+static const uint64_t SH_FLD_FIR14_B01_BOTH_ACTIVE = 7853; // 12
+static const uint64_t SH_FLD_FIR14_B0_SD_DIR_MULT_HIT = 7854; // 12
+static const uint64_t SH_FLD_FIR14_B1_SD_DIR_MULT_HIT = 7855; // 12
+static const uint64_t SH_FLD_FIR14_B2_SD_DIR_MULT_HIT = 7856; // 12
+static const uint64_t SH_FLD_FIR14_B3_SD_DIR_MULT_HIT = 7857; // 12
+static const uint64_t SH_FLD_FIR14_BAD_FP_MATE = 7858; // 12
+static const uint64_t SH_FLD_FIR14_COX_UNEXP_IDLE_PB_CRESP = 7859; // 12
+static const uint64_t SH_FLD_FIR14_CR0_ATAG_PERR = 7860; // 12
+static const uint64_t SH_FLD_FIR14_CR0_TTAG_PERR = 7861; // 12
+static const uint64_t SH_FLD_FIR14_CR1_ATAG_PERR = 7862; // 12
+static const uint64_t SH_FLD_FIR14_CR1_TTAG_PERR = 7863; // 12
+static const uint64_t SH_FLD_FIR14_CR2_ATAG_PERR = 7864; // 12
+static const uint64_t SH_FLD_FIR14_CR2_TTAG_PERR = 7865; // 12
+static const uint64_t SH_FLD_FIR14_CR3_ATAG_PERR = 7866; // 12
+static const uint64_t SH_FLD_FIR14_CR3_TTAG_PERR = 7867; // 12
+static const uint64_t SH_FLD_FIR14_DW_SET_REF_WITH_FLAG_IDLE = 7868; // 12
+static const uint64_t SH_FLD_FIR14_DW_SET_SI_BY_MACH = 7869; // 12
+static const uint64_t SH_FLD_FIR14_HANG_WAITING_FOR_FP_MATE = 7870; // 12
+static const uint64_t SH_FLD_FIR14_IFU_MULT_REQ = 7871; // 12
+static const uint64_t SH_FLD_FIR14_INVALID_SNP_CPS_STATU_RTN = 7872; // 12
+static const uint64_t SH_FLD_FIR14_KILL_REF_WITH_FLAG_IDLE = 7873; // 12
+static const uint64_t SH_FLD_FIR14_L3PF_MACH_DONE = 7874; // 12
+static const uint64_t SH_FLD_FIR14_L3PF_REQ = 7875; // 12
+static const uint64_t SH_FLD_FIR14_LSU_TAG_REUSE = 7876; // 12
+static const uint64_t SH_FLD_FIR14_NCCTL_RLD_BARRIER = 7877; // 12
+static const uint64_t SH_FLD_FIR14_NCCTL_SNP = 7878; // 12
+static const uint64_t SH_FLD_FIR14_NCCTL_SYNC = 7879; // 12
+static const uint64_t SH_FLD_FIR14_NCCTL_TLBIE_ACK = 7880; // 12
+static const uint64_t SH_FLD_FIR14_NCCTL_VSYNC = 7881; // 12
+static const uint64_t SH_FLD_FIR14_NCU_TID_DONE = 7882; // 12
+static const uint64_t SH_FLD_FIR14_PBARB_FSM_REQ_OVERFLOW = 7883; // 12
+static const uint64_t SH_FLD_FIR14_PBARB_TRASHMODE_PB_REQ = 7884; // 12
+static const uint64_t SH_FLD_FIR14_PD_DIR_MULT_HIT = 7885; // 12
+static const uint64_t SH_FLD_FIR14_PHANTOM_B01_REQ = 7886; // 12
+static const uint64_t SH_FLD_FIR14_RCMD0_ADDR_PERR = 7887; // 12
+static const uint64_t SH_FLD_FIR14_RCMD0_TTAG_PERR = 7888; // 12
+static const uint64_t SH_FLD_FIR14_RCMD1_ADDR_PERR = 7889; // 12
+static const uint64_t SH_FLD_FIR14_RCMD1_TTAG_PERR = 7890; // 12
+static const uint64_t SH_FLD_FIR14_RCMD2_ADDR_PERR = 7891; // 12
+static const uint64_t SH_FLD_FIR14_RCMD2_TTAG_PERR = 7892; // 12
+static const uint64_t SH_FLD_FIR14_RCMD3_ADDR_PERR = 7893; // 12
+static const uint64_t SH_FLD_FIR14_RCMD3_TTAG_PERR = 7894; // 12
+static const uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_CRESP = 7895; // 12
+static const uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_DWDONE = 7896; // 12
+static const uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_PBL3_DATA = 7897; // 12
+static const uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_PB_CRESP = 7898; // 12
+static const uint64_t SH_FLD_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK = 7899; // 12
+static const uint64_t SH_FLD_FIR14_RC_PBBUS_SFSTAT = 7900; // 12
+static const uint64_t SH_FLD_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK = 7901; // 12
+static const uint64_t SH_FLD_FIR14_RC_UNEXP_F2_DATA = 7902; // 12
+static const uint64_t SH_FLD_FIR14_RC_UNEXP_PURG_HIT = 7903; // 12
+static const uint64_t SH_FLD_FIR14_RVCTL = 7904; // 12
+static const uint64_t SH_FLD_FIR14_SRCTL0_BAD_HPC = 7905; // 12
+static const uint64_t SH_FLD_FIR14_SRCTL1_BAD_HPC = 7906; // 12
+static const uint64_t SH_FLD_FIR14_SRCTL2_BAD_HPC = 7907; // 12
+static const uint64_t SH_FLD_FIR14_SRCTL3_BAD_HPC = 7908; // 12
+static const uint64_t SH_FLD_FIR14_STQ_COMING = 7909; // 12
+static const uint64_t SH_FLD_FIR14_STQ_OVERFLOW = 7910; // 12
+static const uint64_t SH_FLD_FIR14_TMA_LARXA_VS_FRCMISS_SV = 7911; // 12
+static const uint64_t SH_FLD_FIR14_TMCTL_TIDX_TEND_LDST_SEQ = 7912; // 12
+static const uint64_t SH_FLD_FIR14_XLT_QUEUE_OVRFLW = 7913; // 12
+static const uint64_t SH_FLD_FIR14_XPF_MULT_REQ = 7914; // 12
+static const uint64_t SH_FLD_FIR19_LD_TGT_NODAL_DINC = 7915; // 12
+static const uint64_t SH_FLD_FIR19_ST_TGT_NODAL_DINC = 7916; // 12
+static const uint64_t SH_FLD_FIR1_MASTER_SEQ_ID_PAR = 7917; // 12
+static const uint64_t SH_FLD_FIR1_RSVD_37 = 7918; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_38 = 7919; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_39 = 7920; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_40 = 7921; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_41 = 7922; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_42 = 7923; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_43 = 7924; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_44 = 7925; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_45 = 7926; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_46 = 7927; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_47 = 7928; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_48 = 7929; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_49 = 7930; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_50 = 7931; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_51 = 7932; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_52 = 7933; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_53 = 7934; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_54 = 7935; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_55 = 7936; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_56 = 7937; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_57 = 7938; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_58 = 7939; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_59 = 7940; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_60 = 7941; // 1
+static const uint64_t SH_FLD_FIR1_RSVD_61 = 7942; // 1
+static const uint64_t SH_FLD_FIR1_SNOOP_TLBIE_SEQ_PARITY = 7943; // 12
+static const uint64_t SH_FLD_FIR1_TLBIE_BAD_OP = 7944; // 12
+static const uint64_t SH_FLD_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC = 7945; // 12
+static const uint64_t SH_FLD_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC = 7946; // 12
+static const uint64_t SH_FLD_FIR9_PEC_PHASE3_TIMEOUT = 7947; // 12
+static const uint64_t SH_FLD_FIR9_PEC_PHASE4_RCCO_DISP_FAIL = 7948; // 12
+static const uint64_t SH_FLD_FIR9_PEC_PHASE4_SAME = 7949; // 12
+static const uint64_t SH_FLD_FIR9_PEC_PHASE5_TIMEOUT = 7950; // 12
+static const uint64_t SH_FLD_FIRMWARE_FAULT = 7951; // 1
+static const uint64_t SH_FLD_FIRMWARE_NOTIFY = 7952; // 1
+static const uint64_t SH_FLD_FIRST_ERROR = 7953; // 3
+static const uint64_t SH_FLD_FIRST_ERROR_CAPTURED = 7954; // 1
+static const uint64_t SH_FLD_FIRST_ERROR_DECODE = 7955; // 1
+static const uint64_t SH_FLD_FIRST_ERROR_DECODE_LEN = 7956; // 1
+static const uint64_t SH_FLD_FIRST_ERROR_INFO = 7957; // 1
+static const uint64_t SH_FLD_FIRST_ERROR_INFO_LEN = 7958; // 1
+static const uint64_t SH_FLD_FIRST_ERROR_LEN = 7959; // 3
+static const uint64_t SH_FLD_FIRST_ERROR_SPARE = 7960; // 1
+static const uint64_t SH_FLD_FIRST_ERROR_SPARE_LEN = 7961; // 1
+static const uint64_t SH_FLD_FIR_ACTION0 = 7962; // 17
+static const uint64_t SH_FLD_FIR_ACTION0_LEN = 7963; // 17
+static const uint64_t SH_FLD_FIR_ACTION1 = 7964; // 17
+static const uint64_t SH_FLD_FIR_ACTION1_LEN = 7965; // 17
+static const uint64_t SH_FLD_FIR_LEN = 7966; // 48
+static const uint64_t SH_FLD_FIR_MASK = 7967; // 20
+static const uint64_t SH_FLD_FIR_MASK_LEN = 7968; // 20
+static const uint64_t SH_FLD_FIR_PARITY_ERR = 7969; // 16
+static const uint64_t SH_FLD_FIR_PARITY_ERR2 = 7970; // 1
+static const uint64_t SH_FLD_FIR_PARITY_ERR2_MASK = 7971; // 1
+static const uint64_t SH_FLD_FIR_PARITY_ERR_DUP = 7972; // 14
+static const uint64_t SH_FLD_FIR_PARITY_ERR_DUP_MASK = 7973; // 1
+static const uint64_t SH_FLD_FIR_PARITY_ERR_MASK = 7974; // 2
+static const uint64_t SH_FLD_FIR_RESET = 7975; // 6
+static const uint64_t SH_FLD_FIR_TRIGGER = 7976; // 17
+static const uint64_t SH_FLD_FIT_SEL = 7977; // 17
+static const uint64_t SH_FLD_FIT_SEL_LEN = 7978; // 17
+static const uint64_t SH_FLD_FLAG_DMD = 7979; // 1
+static const uint64_t SH_FLD_FLAG_FENCE = 7980; // 1
+static const uint64_t SH_FLD_FLAG_MAP = 7981; // 1
+static const uint64_t SH_FLD_FLAG_OTHER = 7982; // 1
+static const uint64_t SH_FLD_FLAG_PREF = 7983; // 1
+static const uint64_t SH_FLD_FLUSH_ALIGN_OVR = 7984; // 43
+static const uint64_t SH_FLD_FLUSH_CP_IG_STATE_MAP = 7985; // 2
+static const uint64_t SH_FLD_FLUSH_CP_IG_STATE_MAP_LEN = 7986; // 2
+static const uint64_t SH_FLD_FLUSH_IC = 7987; // 24
+static const uint64_t SH_FLD_FLUSH_SCAN_N = 7988; // 43
+static const uint64_t SH_FLD_FLUSH_SUE_STATE_MAP = 7989; // 2
+static const uint64_t SH_FLD_FLUSH_SUE_STATE_MAP_LEN = 7990; // 2
+static const uint64_t SH_FLD_FMAX = 7991; // 6
+static const uint64_t SH_FLD_FMAX_LEN = 7992; // 6
+static const uint64_t SH_FLD_FMIN = 7993; // 6
+static const uint64_t SH_FLD_FMIN_LEN = 7994; // 6
+static const uint64_t SH_FLD_FMR00_TRAINED = 7995; // 4
+static const uint64_t SH_FLD_FMR01_TRAINED = 7996; // 4
+static const uint64_t SH_FLD_FMR02_TRAINED = 7997; // 4
+static const uint64_t SH_FLD_FMR03_TRAINED = 7998; // 4
+static const uint64_t SH_FLD_FMR04_TRAINED = 7999; // 4
+static const uint64_t SH_FLD_FMR05_TRAINED = 8000; // 4
+static const uint64_t SH_FLD_FMR06_TRAINED = 8001; // 2
+static const uint64_t SH_FLD_FMR07_TRAINED = 8002; // 2
+static const uint64_t SH_FLD_FMULT = 8003; // 6
+static const uint64_t SH_FLD_FMULT_LEN = 8004; // 6
+static const uint64_t SH_FLD_FORCE_ALL_RINGS = 8005; // 43
+static const uint64_t SH_FLD_FORCE_ANY_BAR_ACTIVE = 8006; // 4
+static const uint64_t SH_FLD_FORCE_ANY_CL_ACTIVE = 8007; // 4
+static const uint64_t SH_FLD_FORCE_BYPASS = 8008; // 1
+static const uint64_t SH_FLD_FORCE_CL_INJECT = 8009; // 1
+static const uint64_t SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR = 8010; // 5
+static const uint64_t SH_FLD_FORCE_DOUBLE_BIT_ERR = 8011; // 1
+static const uint64_t SH_FLD_FORCE_DROOP_DATA = 8012; // 6
+static const uint64_t SH_FLD_FORCE_DROOP_DATA_LEN = 8013; // 6
+static const uint64_t SH_FLD_FORCE_ECC_CE = 8014; // 2
+static const uint64_t SH_FLD_FORCE_ECC_SEL = 8015; // 1
+static const uint64_t SH_FLD_FORCE_ECC_SEL_0_1 = 8016; // 1
+static const uint64_t SH_FLD_FORCE_ECC_SEL_0_1_LEN = 8017; // 1
+static const uint64_t SH_FLD_FORCE_ECC_UE = 8018; // 2
+static const uint64_t SH_FLD_FORCE_FSAFE = 8019; // 6
+static const uint64_t SH_FLD_FORCE_MAX_SCOPE_INTRP = 8020; // 1
+static const uint64_t SH_FLD_FORCE_MPR = 8021; // 8
+static const uint64_t SH_FLD_FORCE_MP_IPL = 8022; // 2
+static const uint64_t SH_FLD_FORCE_ON_CLK_GATE = 8023; // 8
+static const uint64_t SH_FLD_FORCE_PR_INJECT = 8024; // 1
+static const uint64_t SH_FLD_FORCE_QUIESCE = 8025; // 2
+static const uint64_t SH_FLD_FORCE_RESERVED = 8026; // 8
+static const uint64_t SH_FLD_FORCE_RESET = 8027; // 1
+static const uint64_t SH_FLD_FORCE_SFSTAT_ACTIVE = 8028; // 4
+static const uint64_t SH_FLD_FORCE_SINGLE_BIT_ECC_ERR = 8029; // 5
+static const uint64_t SH_FLD_FORCE_SINGLE_BIT_ERR = 8030; // 1
+static const uint64_t SH_FLD_FORCE_TEST = 8031; // 43
+static const uint64_t SH_FLD_FORCE_TEST_MODE = 8032; // 86
+static const uint64_t SH_FLD_FORCE_THRES_ACT = 8033; // 43
+static const uint64_t SH_FLD_FORCE_VG_SYS_INTRP = 8034; // 1
+static const uint64_t SH_FLD_FOREIGN_LINK_HANG_ERROR = 8035; // 4
+static const uint64_t SH_FLD_FP0_CREDIT_PRIORITY_4_NOT_8 = 8036; // 2
+static const uint64_t SH_FLD_FP0_DISABLE_CMD_COMPRESSION = 8037; // 2
+static const uint64_t SH_FLD_FP0_DISABLE_GATHERING = 8038; // 2
+static const uint64_t SH_FLD_FP0_DISABLE_PRSP_COMPRESSION = 8039; // 2
+static const uint64_t SH_FLD_FP0_FMR_DISABLE = 8040; // 2
+static const uint64_t SH_FLD_FP0_FMR_SPARE = 8041; // 2
+static const uint64_t SH_FLD_FP0_LL_CREDIT_HI_LIMIT = 8042; // 2
+static const uint64_t SH_FLD_FP0_LL_CREDIT_HI_LIMIT_LEN = 8043; // 2
+static const uint64_t SH_FLD_FP0_LL_CREDIT_LO_LIMIT = 8044; // 2
+static const uint64_t SH_FLD_FP0_LL_CREDIT_LO_LIMIT_LEN = 8045; // 2
+static const uint64_t SH_FLD_FP0_PRS_DISABLE = 8046; // 2
+static const uint64_t SH_FLD_FP0_PRS_SPARE = 8047; // 2
+static const uint64_t SH_FLD_FP0_PRS_SPARE_LEN = 8048; // 2
+static const uint64_t SH_FLD_FP0_RUN_AFTER_FRAME_ERROR = 8049; // 2
+static const uint64_t SH_FLD_FP1_CREDIT_PRIORITY_4_NOT_8 = 8050; // 2
+static const uint64_t SH_FLD_FP1_DISABLE_CMD_COMPRESSION = 8051; // 2
+static const uint64_t SH_FLD_FP1_DISABLE_GATHERING = 8052; // 2
+static const uint64_t SH_FLD_FP1_DISABLE_PRSP_COMPRESSION = 8053; // 2
+static const uint64_t SH_FLD_FP1_FMR_DISABLE = 8054; // 2
+static const uint64_t SH_FLD_FP1_FMR_SPARE = 8055; // 2
+static const uint64_t SH_FLD_FP1_FMR_SPARE_LEN = 8056; // 2
+static const uint64_t SH_FLD_FP1_LL_CREDIT_HI_LIMIT = 8057; // 2
+static const uint64_t SH_FLD_FP1_LL_CREDIT_HI_LIMIT_LEN = 8058; // 2
+static const uint64_t SH_FLD_FP1_LL_CREDIT_LO_LIMIT = 8059; // 2
+static const uint64_t SH_FLD_FP1_LL_CREDIT_LO_LIMIT_LEN = 8060; // 2
+static const uint64_t SH_FLD_FP1_PRS_DISABLE = 8061; // 2
+static const uint64_t SH_FLD_FP1_PRS_SPARE = 8062; // 2
+static const uint64_t SH_FLD_FP1_PRS_SPARE_LEN = 8063; // 2
+static const uint64_t SH_FLD_FP1_RUN_AFTER_FRAME_ERROR = 8064; // 2
+static const uint64_t SH_FLD_FP2_CREDIT_PRIORITY_4_NOT_8 = 8065; // 2
+static const uint64_t SH_FLD_FP2_DISABLE_CMD_COMPRESSION = 8066; // 2
+static const uint64_t SH_FLD_FP2_DISABLE_GATHERING = 8067; // 2
+static const uint64_t SH_FLD_FP2_DISABLE_PRSP_COMPRESSION = 8068; // 2
+static const uint64_t SH_FLD_FP2_FMR_DISABLE = 8069; // 2
+static const uint64_t SH_FLD_FP2_FMR_SPARE = 8070; // 2
+static const uint64_t SH_FLD_FP2_LL_CREDIT_HI_LIMIT = 8071; // 2
+static const uint64_t SH_FLD_FP2_LL_CREDIT_HI_LIMIT_LEN = 8072; // 2
+static const uint64_t SH_FLD_FP2_LL_CREDIT_LO_LIMIT = 8073; // 2
+static const uint64_t SH_FLD_FP2_LL_CREDIT_LO_LIMIT_LEN = 8074; // 2
+static const uint64_t SH_FLD_FP2_PRS_DISABLE = 8075; // 2
+static const uint64_t SH_FLD_FP2_PRS_SPARE = 8076; // 2
+static const uint64_t SH_FLD_FP2_PRS_SPARE_LEN = 8077; // 2
+static const uint64_t SH_FLD_FP2_RUN_AFTER_FRAME_ERROR = 8078; // 2
+static const uint64_t SH_FLD_FP3_CREDIT_PRIORITY_4_NOT_8 = 8079; // 2
+static const uint64_t SH_FLD_FP3_DISABLE_CMD_COMPRESSION = 8080; // 2
+static const uint64_t SH_FLD_FP3_DISABLE_GATHERING = 8081; // 2
+static const uint64_t SH_FLD_FP3_DISABLE_PRSP_COMPRESSION = 8082; // 2
+static const uint64_t SH_FLD_FP3_FMR_DISABLE = 8083; // 2
+static const uint64_t SH_FLD_FP3_FMR_SPARE = 8084; // 2
+static const uint64_t SH_FLD_FP3_FMR_SPARE_LEN = 8085; // 2
+static const uint64_t SH_FLD_FP3_LL_CREDIT_HI_LIMIT = 8086; // 2
+static const uint64_t SH_FLD_FP3_LL_CREDIT_HI_LIMIT_LEN = 8087; // 2
+static const uint64_t SH_FLD_FP3_LL_CREDIT_LO_LIMIT = 8088; // 2
+static const uint64_t SH_FLD_FP3_LL_CREDIT_LO_LIMIT_LEN = 8089; // 2
+static const uint64_t SH_FLD_FP3_PRS_DISABLE = 8090; // 2
+static const uint64_t SH_FLD_FP3_PRS_SPARE = 8091; // 2
+static const uint64_t SH_FLD_FP3_PRS_SPARE_LEN = 8092; // 2
+static const uint64_t SH_FLD_FP3_RUN_AFTER_FRAME_ERROR = 8093; // 2
+static const uint64_t SH_FLD_FP4_CREDIT_PRIORITY_4_NOT_8 = 8094; // 2
+static const uint64_t SH_FLD_FP4_DISABLE_CMD_COMPRESSION = 8095; // 2
+static const uint64_t SH_FLD_FP4_DISABLE_GATHERING = 8096; // 2
+static const uint64_t SH_FLD_FP4_DISABLE_PRSP_COMPRESSION = 8097; // 2
+static const uint64_t SH_FLD_FP4_FMR_DISABLE = 8098; // 2
+static const uint64_t SH_FLD_FP4_FMR_SPARE = 8099; // 2
+static const uint64_t SH_FLD_FP4_LL_CREDIT_HI_LIMIT = 8100; // 2
+static const uint64_t SH_FLD_FP4_LL_CREDIT_HI_LIMIT_LEN = 8101; // 2
+static const uint64_t SH_FLD_FP4_LL_CREDIT_LO_LIMIT = 8102; // 2
+static const uint64_t SH_FLD_FP4_LL_CREDIT_LO_LIMIT_LEN = 8103; // 2
+static const uint64_t SH_FLD_FP4_PRS_DISABLE = 8104; // 2
+static const uint64_t SH_FLD_FP4_PRS_SPARE = 8105; // 2
+static const uint64_t SH_FLD_FP4_PRS_SPARE_LEN = 8106; // 2
+static const uint64_t SH_FLD_FP4_RUN_AFTER_FRAME_ERROR = 8107; // 2
+static const uint64_t SH_FLD_FP5_CREDIT_PRIORITY_4_NOT_8 = 8108; // 2
+static const uint64_t SH_FLD_FP5_DISABLE_CMD_COMPRESSION = 8109; // 2
+static const uint64_t SH_FLD_FP5_DISABLE_GATHERING = 8110; // 2
+static const uint64_t SH_FLD_FP5_DISABLE_PRSP_COMPRESSION = 8111; // 2
+static const uint64_t SH_FLD_FP5_FMR_DISABLE = 8112; // 2
+static const uint64_t SH_FLD_FP5_FMR_SPARE = 8113; // 2
+static const uint64_t SH_FLD_FP5_FMR_SPARE_LEN = 8114; // 2
+static const uint64_t SH_FLD_FP5_LL_CREDIT_HI_LIMIT = 8115; // 2
+static const uint64_t SH_FLD_FP5_LL_CREDIT_HI_LIMIT_LEN = 8116; // 2
+static const uint64_t SH_FLD_FP5_LL_CREDIT_LO_LIMIT = 8117; // 2
+static const uint64_t SH_FLD_FP5_LL_CREDIT_LO_LIMIT_LEN = 8118; // 2
+static const uint64_t SH_FLD_FP5_PRS_DISABLE = 8119; // 2
+static const uint64_t SH_FLD_FP5_PRS_SPARE = 8120; // 2
+static const uint64_t SH_FLD_FP5_PRS_SPARE_LEN = 8121; // 2
+static const uint64_t SH_FLD_FP5_RUN_AFTER_FRAME_ERROR = 8122; // 2
+static const uint64_t SH_FLD_FP6_CREDIT_PRIORITY_4_NOT_8 = 8123; // 1
+static const uint64_t SH_FLD_FP6_DISABLE_CMD_COMPRESSION = 8124; // 1
+static const uint64_t SH_FLD_FP6_DISABLE_GATHERING = 8125; // 1
+static const uint64_t SH_FLD_FP6_DISABLE_PRSP_COMPRESSION = 8126; // 1
+static const uint64_t SH_FLD_FP6_FMR_DISABLE = 8127; // 1
+static const uint64_t SH_FLD_FP6_FMR_SPARE = 8128; // 1
+static const uint64_t SH_FLD_FP6_LL_CREDIT_HI_LIMIT = 8129; // 1
+static const uint64_t SH_FLD_FP6_LL_CREDIT_HI_LIMIT_LEN = 8130; // 1
+static const uint64_t SH_FLD_FP6_LL_CREDIT_LO_LIMIT = 8131; // 1
+static const uint64_t SH_FLD_FP6_LL_CREDIT_LO_LIMIT_LEN = 8132; // 1
+static const uint64_t SH_FLD_FP6_PRS_DISABLE = 8133; // 1
+static const uint64_t SH_FLD_FP6_PRS_SPARE = 8134; // 1
+static const uint64_t SH_FLD_FP6_PRS_SPARE_LEN = 8135; // 1
+static const uint64_t SH_FLD_FP6_RUN_AFTER_FRAME_ERROR = 8136; // 1
+static const uint64_t SH_FLD_FP7_CREDIT_PRIORITY_4_NOT_8 = 8137; // 1
+static const uint64_t SH_FLD_FP7_DISABLE_CMD_COMPRESSION = 8138; // 1
+static const uint64_t SH_FLD_FP7_DISABLE_GATHERING = 8139; // 1
+static const uint64_t SH_FLD_FP7_DISABLE_PRSP_COMPRESSION = 8140; // 1
+static const uint64_t SH_FLD_FP7_FMR_DISABLE = 8141; // 1
+static const uint64_t SH_FLD_FP7_FMR_SPARE = 8142; // 1
+static const uint64_t SH_FLD_FP7_FMR_SPARE_LEN = 8143; // 1
+static const uint64_t SH_FLD_FP7_LL_CREDIT_HI_LIMIT = 8144; // 1
+static const uint64_t SH_FLD_FP7_LL_CREDIT_HI_LIMIT_LEN = 8145; // 1
+static const uint64_t SH_FLD_FP7_LL_CREDIT_LO_LIMIT = 8146; // 1
+static const uint64_t SH_FLD_FP7_LL_CREDIT_LO_LIMIT_LEN = 8147; // 1
+static const uint64_t SH_FLD_FP7_PRS_DISABLE = 8148; // 1
+static const uint64_t SH_FLD_FP7_PRS_SPARE = 8149; // 1
+static const uint64_t SH_FLD_FP7_PRS_SPARE_LEN = 8150; // 1
+static const uint64_t SH_FLD_FP7_RUN_AFTER_FRAME_ERROR = 8151; // 1
+static const uint64_t SH_FLD_FRAC1 = 8152; // 3
+static const uint64_t SH_FLD_FRAC1_LEN = 8153; // 3
+static const uint64_t SH_FLD_FRAC2 = 8154; // 3
+static const uint64_t SH_FLD_FRAC2_LEN = 8155; // 3
+static const uint64_t SH_FLD_FRAMER00_ATTN = 8156; // 4
+static const uint64_t SH_FLD_FRAMER01_ATTN = 8157; // 4
+static const uint64_t SH_FLD_FRAMER02_ATTN = 8158; // 4
+static const uint64_t SH_FLD_FRAMER03_ATTN = 8159; // 4
+static const uint64_t SH_FLD_FRAMER04_ATTN = 8160; // 4
+static const uint64_t SH_FLD_FRAMER05_ATTN = 8161; // 4
+static const uint64_t SH_FLD_FRAMER06_ATTN = 8162; // 2
+static const uint64_t SH_FLD_FRAMER07_ATTN = 8163; // 2
+static const uint64_t SH_FLD_FRAME_CAP_ADDR = 8164; // 10
+static const uint64_t SH_FLD_FRAME_CAP_ADDR_LEN = 8165; // 10
+static const uint64_t SH_FLD_FRAME_CAP_INST = 8166; // 10
+static const uint64_t SH_FLD_FRAME_CAP_SYN = 8167; // 10
+static const uint64_t SH_FLD_FRAME_CAP_SYN_LEN = 8168; // 10
+static const uint64_t SH_FLD_FRAME_CAP_VALID = 8169; // 10
+static const uint64_t SH_FLD_FRAME_COUNT = 8170; // 8
+static const uint64_t SH_FLD_FRAME_COUNT_LEN = 8171; // 8
+static const uint64_t SH_FLD_FRAME_SIZE = 8172; // 1
+static const uint64_t SH_FLD_FRAME_SIZE_LEN = 8173; // 1
+static const uint64_t SH_FLD_FREE = 8174; // 12
+static const uint64_t SH_FLD_FREEZE = 8175; // 10
+static const uint64_t SH_FLD_FREEZEMODE = 8176; // 9
+static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR1 = 8177; // 1
+static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR2 = 8178; // 1
+static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR3 = 8179; // 1
+static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR4 = 8180; // 1
+static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR5 = 8181; // 1
+static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR6 = 8182; // 1
+static const uint64_t SH_FLD_FREEZE_LOG_ON_ERROR7 = 8183; // 1
+static const uint64_t SH_FLD_FREEZE_ON_OVERFLOW = 8184; // 2
+static const uint64_t SH_FLD_FREEZE_SEL = 8185; // 43
+static const uint64_t SH_FLD_FREE_USAGE = 8186; // 2
+static const uint64_t SH_FLD_FREE_USAGE_10E = 8187; // 43
+static const uint64_t SH_FLD_FREE_USAGE_11E = 8188; // 43
+static const uint64_t SH_FLD_FREE_USAGE_12D = 8189; // 11
+static const uint64_t SH_FLD_FREE_USAGE_12E = 8190; // 38
+static const uint64_t SH_FLD_FREE_USAGE_13D = 8191; // 12
+static const uint64_t SH_FLD_FREE_USAGE_13E = 8192; // 38
+static const uint64_t SH_FLD_FREE_USAGE_14D = 8193; // 12
+static const uint64_t SH_FLD_FREE_USAGE_14E = 8194; // 40
+static const uint64_t SH_FLD_FREE_USAGE_15D = 8195; // 12
+static const uint64_t SH_FLD_FREE_USAGE_15E = 8196; // 40
+static const uint64_t SH_FLD_FREE_USAGE_16D = 8197; // 30
+static const uint64_t SH_FLD_FREE_USAGE_16E = 8198; // 40
+static const uint64_t SH_FLD_FREE_USAGE_17D = 8199; // 32
+static const uint64_t SH_FLD_FREE_USAGE_17E = 8200; // 40
+static const uint64_t SH_FLD_FREE_USAGE_18D = 8201; // 39
+static const uint64_t SH_FLD_FREE_USAGE_18E = 8202; // 40
+static const uint64_t SH_FLD_FREE_USAGE_19D = 8203; // 40
+static const uint64_t SH_FLD_FREE_USAGE_19E = 8204; // 40
+static const uint64_t SH_FLD_FREE_USAGE_20D = 8205; // 40
+static const uint64_t SH_FLD_FREE_USAGE_20E = 8206; // 41
+static const uint64_t SH_FLD_FREE_USAGE_21D = 8207; // 40
+static const uint64_t SH_FLD_FREE_USAGE_21E = 8208; // 43
+static const uint64_t SH_FLD_FREE_USAGE_22D = 8209; // 40
+static const uint64_t SH_FLD_FREE_USAGE_22E = 8210; // 43
+static const uint64_t SH_FLD_FREE_USAGE_23D = 8211; // 40
+static const uint64_t SH_FLD_FREE_USAGE_23E = 8212; // 43
+static const uint64_t SH_FLD_FREE_USAGE_24D = 8213; // 40
+static const uint64_t SH_FLD_FREE_USAGE_25D = 8214; // 40
+static const uint64_t SH_FLD_FREE_USAGE_26D = 8215; // 41
+static const uint64_t SH_FLD_FREE_USAGE_27D = 8216; // 41
+static const uint64_t SH_FLD_FREE_USAGE_28D = 8217; // 39
+static const uint64_t SH_FLD_FREE_USAGE_29D = 8218; // 39
+static const uint64_t SH_FLD_FREE_USAGE_30D = 8219; // 39
+static const uint64_t SH_FLD_FREE_USAGE_31D = 8220; // 41
+static const uint64_t SH_FLD_FREE_USAGE_44C = 8221; // 43
+static const uint64_t SH_FLD_FREE_USAGE_45C = 8222; // 43
+static const uint64_t SH_FLD_FREE_USAGE_46C = 8223; // 43
+static const uint64_t SH_FLD_FREE_USAGE_47C = 8224; // 43
+static const uint64_t SH_FLD_FREE_USAGE_48A = 8225; // 43
+static const uint64_t SH_FLD_FREE_USAGE_49A = 8226; // 43
+static const uint64_t SH_FLD_FREE_USAGE_50A = 8227; // 43
+static const uint64_t SH_FLD_FREE_USAGE_51A = 8228; // 43
+static const uint64_t SH_FLD_FREE_USAGE_52A = 8229; // 43
+static const uint64_t SH_FLD_FREE_USAGE_53A = 8230; // 43
+static const uint64_t SH_FLD_FREE_USAGE_54A = 8231; // 43
+static const uint64_t SH_FLD_FREE_USAGE_55A = 8232; // 43
+static const uint64_t SH_FLD_FREE_USAGE_56A = 8233; // 43
+static const uint64_t SH_FLD_FREE_USAGE_57A = 8234; // 43
+static const uint64_t SH_FLD_FREE_USAGE_58A = 8235; // 43
+static const uint64_t SH_FLD_FREE_USAGE_59A = 8236; // 43
+static const uint64_t SH_FLD_FREE_USAGE_60A = 8237; // 43
+static const uint64_t SH_FLD_FREE_USAGE_61A = 8238; // 43
+static const uint64_t SH_FLD_FREE_USAGE_62A = 8239; // 43
+static const uint64_t SH_FLD_FREE_USAGE_63A = 8240; // 43
+static const uint64_t SH_FLD_FREE_USAGE_6A = 8241; // 43
+static const uint64_t SH_FLD_FREE_USAGE_7A = 8242; // 43
+static const uint64_t SH_FLD_FREE_USAGE_9A = 8243; // 43
+static const uint64_t SH_FLD_FREQIN_AVG = 8244; // 6
+static const uint64_t SH_FLD_FREQIN_AVG_LEN = 8245; // 6
+static const uint64_t SH_FLD_FREQIN_MAX = 8246; // 6
+static const uint64_t SH_FLD_FREQIN_MAX_LEN = 8247; // 6
+static const uint64_t SH_FLD_FREQIN_MIN = 8248; // 6
+static const uint64_t SH_FLD_FREQIN_MIN_LEN = 8249; // 6
+static const uint64_t SH_FLD_FREQOUT = 8250; // 6
+static const uint64_t SH_FLD_FREQOUT_AVG = 8251; // 6
+static const uint64_t SH_FLD_FREQOUT_AVG_LEN = 8252; // 6
+static const uint64_t SH_FLD_FREQOUT_LEN = 8253; // 6
+static const uint64_t SH_FLD_FREQOUT_MAX = 8254; // 6
+static const uint64_t SH_FLD_FREQOUT_MAX_LEN = 8255; // 6
+static const uint64_t SH_FLD_FREQOUT_MIN = 8256; // 6
+static const uint64_t SH_FLD_FREQOUT_MIN_LEN = 8257; // 6
+static const uint64_t SH_FLD_FREQUENCY_REFERENCE = 8258; // 24
+static const uint64_t SH_FLD_FREQUENCY_REFERENCE_LEN = 8259; // 24
+static const uint64_t SH_FLD_FREQ_CHANGE = 8260; // 6
+static const uint64_t SH_FLD_FREQ_LCL_SAMPLE_EN = 8261; // 12
+static const uint64_t SH_FLD_FREQ_SCALE_A_THRESHOLD = 8262; // 24
+static const uint64_t SH_FLD_FREQ_SCALE_A_THRESHOLD_LEN = 8263; // 24
+static const uint64_t SH_FLD_FREQ_SCALE_B_THRESHOLD = 8264; // 24
+static const uint64_t SH_FLD_FREQ_SCALE_B_THRESHOLD_LEN = 8265; // 24
+static const uint64_t SH_FLD_FRZ_COUNT_ON_FRZ = 8266; // 43
+static const uint64_t SH_FLD_FSAFE = 8267; // 6
+static const uint64_t SH_FLD_FSAFE_ACTIVE = 8268; // 6
+static const uint64_t SH_FLD_FSAFE_LEN = 8269; // 6
+static const uint64_t SH_FLD_FSI_A_MST_0_ACTUAL_ERROR = 8270; // 1
+static const uint64_t SH_FLD_FSI_A_MST_0_ACTUAL_ERROR_LEN = 8271; // 1
+static const uint64_t SH_FLD_FSI_A_MST_0_PORT_0_ENABLE = 8272; // 1
+static const uint64_t SH_FLD_FSI_A_MST_0_PORT_1_ENABLE = 8273; // 1
+static const uint64_t SH_FLD_FSI_A_MST_0_PORT_2_ENABLE = 8274; // 1
+static const uint64_t SH_FLD_FSI_A_MST_0_PORT_3_ENABLE = 8275; // 1
+static const uint64_t SH_FLD_FSI_A_MST_0_PORT_4_ENABLE = 8276; // 1
+static const uint64_t SH_FLD_FSI_A_MST_0_PORT_5_ENABLE = 8277; // 1
+static const uint64_t SH_FLD_FSI_A_MST_0_PORT_6_ENABLE = 8278; // 1
+static const uint64_t SH_FLD_FSI_A_MST_0_PORT_7_ENABLE = 8279; // 1
+static const uint64_t SH_FLD_FSI_A_MST_1_ACTUAL_ERROR = 8280; // 1
+static const uint64_t SH_FLD_FSI_A_MST_1_ACTUAL_ERROR_LEN = 8281; // 1
+static const uint64_t SH_FLD_FSI_A_MST_1_PORT_0_ENABLE = 8282; // 1
+static const uint64_t SH_FLD_FSI_A_MST_1_PORT_1_ENABLE = 8283; // 1
+static const uint64_t SH_FLD_FSI_A_MST_1_PORT_2_ENABLE = 8284; // 1
+static const uint64_t SH_FLD_FSI_A_MST_1_PORT_3_ENABLE = 8285; // 1
+static const uint64_t SH_FLD_FSI_A_MST_1_PORT_4_ENABLE = 8286; // 1
+static const uint64_t SH_FLD_FSI_B_MST_0_ACTUAL_ERROR = 8287; // 1
+static const uint64_t SH_FLD_FSI_B_MST_0_ACTUAL_ERROR_LEN = 8288; // 1
+static const uint64_t SH_FLD_FSI_B_MST_0_PORT_0_ENABLE = 8289; // 1
+static const uint64_t SH_FLD_FSI_B_MST_0_PORT_1_ENABLE = 8290; // 1
+static const uint64_t SH_FLD_FSI_B_MST_0_PORT_2_ENABLE = 8291; // 1
+static const uint64_t SH_FLD_FSI_B_MST_0_PORT_3_ENABLE = 8292; // 1
+static const uint64_t SH_FLD_FSI_B_MST_0_PORT_4_ENABLE = 8293; // 1
+static const uint64_t SH_FLD_FSI_B_MST_0_PORT_5_ENABLE = 8294; // 1
+static const uint64_t SH_FLD_FSI_B_MST_0_PORT_6_ENABLE = 8295; // 1
+static const uint64_t SH_FLD_FSI_B_MST_0_PORT_7_ENABLE = 8296; // 1
+static const uint64_t SH_FLD_FSI_CC_VSB_CBS_CMD = 8297; // 3
+static const uint64_t SH_FLD_FSI_CC_VSB_CBS_CMD_LEN = 8298; // 3
+static const uint64_t SH_FLD_FSI_CC_VSB_CBS_REQ = 8299; // 3
+static const uint64_t SH_FLD_FSI_SCRATCH_PAD1 = 8300; // 1
+static const uint64_t SH_FLD_FSI_SCRATCH_PAD1_LEN = 8301; // 1
+static const uint64_t SH_FLD_FSI_SCRATCH_PAD2 = 8302; // 1
+static const uint64_t SH_FLD_FSI_SCRATCH_PAD2_LEN = 8303; // 1
+static const uint64_t SH_FLD_FSI_SCRATCH_PAD3 = 8304; // 1
+static const uint64_t SH_FLD_FSI_SCRATCH_PAD3_LEN = 8305; // 1
+static const uint64_t SH_FLD_FSMJ_EVENT = 8306; // 2
+static const uint64_t SH_FLD_FSMJ_EVENT_LEN = 8307; // 2
+static const uint64_t SH_FLD_FSMJ_EVENT_SEL = 8308; // 2
+static const uint64_t SH_FLD_FSMJ_EVENT_SEL_LEN = 8309; // 2
+static const uint64_t SH_FLD_FSMJ_FSM = 8310; // 2
+static const uint64_t SH_FLD_FSMJ_FSM_LEN = 8311; // 2
+static const uint64_t SH_FLD_FSMJ_FSM_SEL = 8312; // 2
+static const uint64_t SH_FLD_FSMJ_FSM_SEL_LEN = 8313; // 2
+static const uint64_t SH_FLD_FSM_DATA02 = 8314; // 1
+static const uint64_t SH_FLD_FSM_ERR = 8315; // 5
+static const uint64_t SH_FLD_FSM_ERROR = 8316; // 1
+static const uint64_t SH_FLD_FSM_PARITY_ERROR = 8317; // 3
+static const uint64_t SH_FLD_FSM_PERR = 8318; // 1
+static const uint64_t SH_FLD_FSM_PRESENT_STATE = 8319; // 1
+static const uint64_t SH_FLD_FSM_PRESENT_STATE_LEN = 8320; // 1
+static const uint64_t SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8321; // 43
+static const uint64_t SH_FLD_FSM_SYNC_ENABLE = 8322; // 1
+static const uint64_t SH_FLD_FSM_TRIGGER = 8323; // 2
+static const uint64_t SH_FLD_FSP_ACCESS_TRUSTED_SPACE = 8324; // 4
+static const uint64_t SH_FLD_FSP_CMD_ENABLE = 8325; // 1
+static const uint64_t SH_FLD_FSP_ECC_ERR_CE = 8326; // 4
+static const uint64_t SH_FLD_FSP_ECC_ERR_UE = 8327; // 4
+static const uint64_t SH_FLD_FSP_ERR_RSP_ENABLE = 8328; // 1
+static const uint64_t SH_FLD_FSP_INBOUND_ACTIVE = 8329; // 1
+static const uint64_t SH_FLD_FSP_INTERRUPT = 8330; // 1
+static const uint64_t SH_FLD_FSP_INT_ENABLE = 8331; // 1
+static const uint64_t SH_FLD_FSP_INV_READ = 8332; // 1
+static const uint64_t SH_FLD_FSP_LINK_ACTIVE = 8333; // 1
+static const uint64_t SH_FLD_FSP_MMIO_ENABLE = 8334; // 1
+static const uint64_t SH_FLD_FSP_MMIO_MASK = 8335; // 1
+static const uint64_t SH_FLD_FSP_MMIO_MASK_LEN = 8336; // 1
+static const uint64_t SH_FLD_FSP_OUTBOUND_ACTIVE = 8337; // 1
+static const uint64_t SH_FLD_FSP_RESET = 8338; // 1
+static const uint64_t SH_FLD_FSP_SPECIAL_WKUP = 8339; // 30
+static const uint64_t SH_FLD_FSP_TCE_ENABLE = 8340; // 1
+static const uint64_t SH_FLD_FULL = 8341; // 2
+static const uint64_t SH_FLD_FULLMASK = 8342; // 1
+static const uint64_t SH_FLD_FULLMASK_LEN = 8343; // 1
+static const uint64_t SH_FLD_FULL_WRITEBACK_ENABLE = 8344; // 6
+static const uint64_t SH_FLD_FUNC = 8345; // 43
+static const uint64_t SH_FLD_FUNCTION = 8346; // 6
+static const uint64_t SH_FLD_FUNCTION_LEN = 8347; // 6
+static const uint64_t SH_FLD_FUNC_MODE_DONE = 8348; // 4
+static const uint64_t SH_FLD_FUSED_CORE_MODE = 8349; // 24
+static const uint64_t SH_FLD_FW0 = 8350; // 1
+static const uint64_t SH_FLD_FW0_MASK = 8351; // 1
+static const uint64_t SH_FLD_FW1 = 8352; // 1
+static const uint64_t SH_FLD_FW1_MASK = 8353; // 1
+static const uint64_t SH_FLD_FWD_PROG_RATE2 = 8354; // 12
+static const uint64_t SH_FLD_FWD_PROG_RATE2_LEN = 8355; // 12
+static const uint64_t SH_FLD_FWMSX_PE = 8356; // 8
+static const uint64_t SH_FLD_FWMSX_PE_LEN = 8357; // 8
+static const uint64_t SH_FLD_FW_RD_WR = 8358; // 8
+static const uint64_t SH_FLD_FW_RD_WR_LEN = 8359; // 8
+static const uint64_t SH_FLD_FW_WR_RD = 8360; // 8
+static const uint64_t SH_FLD_FW_WR_RD_LEN = 8361; // 8
+static const uint64_t SH_FLD_F_READ = 8362; // 43
+static const uint64_t SH_FLD_F_SKITTER_READ_MASK = 8363; // 43
+static const uint64_t SH_FLD_GCR_BUFFER_ENABLED_RO_SIGNAL = 8364; // 4
+static const uint64_t SH_FLD_GCR_HANG_DET_SEL = 8365; // 4
+static const uint64_t SH_FLD_GCR_HANG_DET_SEL_LEN = 8366; // 4
+static const uint64_t SH_FLD_GCR_HANG_ERROR_INJ = 8367; // 4
+static const uint64_t SH_FLD_GCR_HANG_ERROR_MASK = 8368; // 4
+static const uint64_t SH_FLD_GCR_TEST = 8369; // 4
+static const uint64_t SH_FLD_GENERAL_TIMEOUT = 8370; // 43
+static const uint64_t SH_FLD_GENERATE_MPIPL_SEQUENCE = 8371; // 4
+static const uint64_t SH_FLD_GLB_BRCST = 8372; // 43
+static const uint64_t SH_FLD_GLB_BRCST_LEN = 8373; // 43
+static const uint64_t SH_FLD_GLOBAL_EP_RESET_DC = 8374; // 3
+static const uint64_t SH_FLD_GLOBAL_PHY_OFFSET = 8375; // 8
+static const uint64_t SH_FLD_GLOBAL_PHY_OFFSET_LEN = 8376; // 8
+static const uint64_t SH_FLD_GLOBAL_RUN_MODE = 8377; // 2
+static const uint64_t SH_FLD_GO = 8378; // 43
+static const uint64_t SH_FLD_GO2 = 8379; // 43
+static const uint64_t SH_FLD_GOTO_CMD = 8380; // 64
+static const uint64_t SH_FLD_GOTO_CMD_LEN = 8381; // 64
+static const uint64_t SH_FLD_GP = 8382; // 2
+static const uint64_t SH_FLD_GPE0_ERROR = 8383; // 2
+static const uint64_t SH_FLD_GPE0_ERROR_MASK = 8384; // 1
+static const uint64_t SH_FLD_GPE0_HALTED = 8385; // 1
+static const uint64_t SH_FLD_GPE0_HALTED_MASK = 8386; // 1
+static const uint64_t SH_FLD_GPE0_OCISLV_ERR = 8387; // 2
+static const uint64_t SH_FLD_GPE0_OCISLV_ERR_LEN = 8388; // 1
+static const uint64_t SH_FLD_GPE0_OCISLV_ERR_MASK = 8389; // 1
+static const uint64_t SH_FLD_GPE0_WATCHDOG_TIMEOUT = 8390; // 1
+static const uint64_t SH_FLD_GPE0_WATCHDOG_TIMEOUT_MASK = 8391; // 1
+static const uint64_t SH_FLD_GPE1_ERROR = 8392; // 2
+static const uint64_t SH_FLD_GPE1_ERROR_MASK = 8393; // 1
+static const uint64_t SH_FLD_GPE1_HALTED = 8394; // 1
+static const uint64_t SH_FLD_GPE1_HALTED_MASK = 8395; // 1
+static const uint64_t SH_FLD_GPE1_OCISLV_ERR = 8396; // 2
+static const uint64_t SH_FLD_GPE1_OCISLV_ERR_LEN = 8397; // 1
+static const uint64_t SH_FLD_GPE1_OCISLV_ERR_MASK = 8398; // 1
+static const uint64_t SH_FLD_GPE1_WATCHDOG_TIMEOUT = 8399; // 1
+static const uint64_t SH_FLD_GPE1_WATCHDOG_TIMEOUT_MASK = 8400; // 1
+static const uint64_t SH_FLD_GPE2_ERROR = 8401; // 2
+static const uint64_t SH_FLD_GPE2_ERROR_MASK = 8402; // 1
+static const uint64_t SH_FLD_GPE2_HALTED = 8403; // 1
+static const uint64_t SH_FLD_GPE2_HALTED_MASK = 8404; // 1
+static const uint64_t SH_FLD_GPE2_OCISLV_ERR = 8405; // 2
+static const uint64_t SH_FLD_GPE2_OCISLV_ERR_LEN = 8406; // 1
+static const uint64_t SH_FLD_GPE2_OCISLV_ERR_MASK = 8407; // 1
+static const uint64_t SH_FLD_GPE2_WATCHDOG_TIMEOUT = 8408; // 1
+static const uint64_t SH_FLD_GPE2_WATCHDOG_TIMEOUT_MASK = 8409; // 1
+static const uint64_t SH_FLD_GPE3_ERROR = 8410; // 2
+static const uint64_t SH_FLD_GPE3_ERROR_MASK = 8411; // 1
+static const uint64_t SH_FLD_GPE3_HALTED = 8412; // 1
+static const uint64_t SH_FLD_GPE3_HALTED_MASK = 8413; // 1
+static const uint64_t SH_FLD_GPE3_OCISLV_ERR = 8414; // 2
+static const uint64_t SH_FLD_GPE3_OCISLV_ERR_LEN = 8415; // 1
+static const uint64_t SH_FLD_GPE3_OCISLV_ERR_MASK = 8416; // 1
+static const uint64_t SH_FLD_GPE3_WATCHDOG_TIMEOUT = 8417; // 1
+static const uint64_t SH_FLD_GPE3_WATCHDOG_TIMEOUT_MASK = 8418; // 1
+static const uint64_t SH_FLD_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC = 8419; // 3
+static const uint64_t SH_FLD_GRANTED_PACKET = 8420; // 30
+static const uint64_t SH_FLD_GRANTED_PACKET_LEN = 8421; // 30
+static const uint64_t SH_FLD_GRANTED_SOURCE = 8422; // 30
+static const uint64_t SH_FLD_GRANTED_SOURCE_LEN = 8423; // 30
+static const uint64_t SH_FLD_GROUP = 8424; // 9
+static const uint64_t SH_FLD_GROUPING = 8425; // 8
+static const uint64_t SH_FLD_GROUPING_LEN = 8426; // 8
+static const uint64_t SH_FLD_GROUP_BASE_ADDRESS = 8427; // 8
+static const uint64_t SH_FLD_GROUP_BASE_ADDRESS_LEN = 8428; // 8
+static const uint64_t SH_FLD_GROUP_EPSILON = 8429; // 8
+static const uint64_t SH_FLD_GROUP_EPSILON_LEN = 8430; // 8
+static const uint64_t SH_FLD_GROUP_LEN = 8431; // 9
+static const uint64_t SH_FLD_GROUP_SEL_0_4 = 8432; // 1
+static const uint64_t SH_FLD_GROUP_SEL_0_4_LEN = 8433; // 1
+static const uint64_t SH_FLD_GROUP_SIZE = 8434; // 8
+static const uint64_t SH_FLD_GROUP_SIZE_LEN = 8435; // 8
+static const uint64_t SH_FLD_GRPSEL = 8436; // 2
+static const uint64_t SH_FLD_GRPSEL_LEN = 8437; // 2
+static const uint64_t SH_FLD_GRP_BASE = 8438; // 8
+static const uint64_t SH_FLD_GRP_BASE_LEN = 8439; // 8
+static const uint64_t SH_FLD_GRP_MBR_ID = 8440; // 8
+static const uint64_t SH_FLD_GRP_SIZE = 8441; // 8
+static const uint64_t SH_FLD_GRP_SIZE_LEN = 8442; // 8
+static const uint64_t SH_FLD_GUESS_WAIT_TIME = 8443; // 8
+static const uint64_t SH_FLD_GUESS_WAIT_TIME_LEN = 8444; // 8
+static const uint64_t SH_FLD_GUEST_PREF_PGSZ = 8445; // 1
+static const uint64_t SH_FLD_GUEST_PREF_PGSZ_LEN = 8446; // 1
+static const uint64_t SH_FLD_GX = 8447; // 2
+static const uint64_t SH_FLD_GXSTP0_TRIG_IN0 = 8448; // 43
+static const uint64_t SH_FLD_GXSTP0_TRIG_IN1 = 8449; // 43
+static const uint64_t SH_FLD_GXSTP0_TRIG_IN10 = 8450; // 43
+static const uint64_t SH_FLD_GXSTP0_TRIG_IN11 = 8451; // 43
+static const uint64_t SH_FLD_GXSTP0_TRIG_IN2 = 8452; // 43
+static const uint64_t SH_FLD_GXSTP0_TRIG_IN3 = 8453; // 43
+static const uint64_t SH_FLD_GXSTP0_TRIG_IN4 = 8454; // 43
+static const uint64_t SH_FLD_GXSTP0_TRIG_IN5 = 8455; // 43
+static const uint64_t SH_FLD_GXSTP0_TRIG_IN6 = 8456; // 43
+static const uint64_t SH_FLD_GXSTP0_TRIG_IN7 = 8457; // 43
+static const uint64_t SH_FLD_GXSTP0_TRIG_IN8 = 8458; // 43
+static const uint64_t SH_FLD_GXSTP0_TRIG_IN9 = 8459; // 43
+static const uint64_t SH_FLD_GXSTP1_TRIG_IN0 = 8460; // 43
+static const uint64_t SH_FLD_GXSTP1_TRIG_IN1 = 8461; // 43
+static const uint64_t SH_FLD_GXSTP1_TRIG_IN10 = 8462; // 43
+static const uint64_t SH_FLD_GXSTP1_TRIG_IN11 = 8463; // 43
+static const uint64_t SH_FLD_GXSTP1_TRIG_IN2 = 8464; // 43
+static const uint64_t SH_FLD_GXSTP1_TRIG_IN3 = 8465; // 43
+static const uint64_t SH_FLD_GXSTP1_TRIG_IN4 = 8466; // 43
+static const uint64_t SH_FLD_GXSTP1_TRIG_IN5 = 8467; // 43
+static const uint64_t SH_FLD_GXSTP1_TRIG_IN6 = 8468; // 43
+static const uint64_t SH_FLD_GXSTP1_TRIG_IN7 = 8469; // 43
+static const uint64_t SH_FLD_GXSTP1_TRIG_IN8 = 8470; // 43
+static const uint64_t SH_FLD_GXSTP1_TRIG_IN9 = 8471; // 43
+static const uint64_t SH_FLD_GXSTP2_TRIG_IN0 = 8472; // 43
+static const uint64_t SH_FLD_GXSTP2_TRIG_IN1 = 8473; // 43
+static const uint64_t SH_FLD_GXSTP2_TRIG_IN10 = 8474; // 43
+static const uint64_t SH_FLD_GXSTP2_TRIG_IN11 = 8475; // 43
+static const uint64_t SH_FLD_GXSTP2_TRIG_IN2 = 8476; // 43
+static const uint64_t SH_FLD_GXSTP2_TRIG_IN3 = 8477; // 43
+static const uint64_t SH_FLD_GXSTP2_TRIG_IN4 = 8478; // 43
+static const uint64_t SH_FLD_GXSTP2_TRIG_IN5 = 8479; // 43
+static const uint64_t SH_FLD_GXSTP2_TRIG_IN6 = 8480; // 43
+static const uint64_t SH_FLD_GXSTP2_TRIG_IN7 = 8481; // 43
+static const uint64_t SH_FLD_GXSTP2_TRIG_IN8 = 8482; // 43
+static const uint64_t SH_FLD_GXSTP2_TRIG_IN9 = 8483; // 43
+static const uint64_t SH_FLD_GXSTP_IN0 = 8484; // 43
+static const uint64_t SH_FLD_GXSTP_IN1 = 8485; // 43
+static const uint64_t SH_FLD_GXSTP_IN10 = 8486; // 43
+static const uint64_t SH_FLD_GXSTP_IN11 = 8487; // 43
+static const uint64_t SH_FLD_GXSTP_IN2 = 8488; // 43
+static const uint64_t SH_FLD_GXSTP_IN3 = 8489; // 43
+static const uint64_t SH_FLD_GXSTP_IN4 = 8490; // 43
+static const uint64_t SH_FLD_GXSTP_IN5 = 8491; // 43
+static const uint64_t SH_FLD_GXSTP_IN6 = 8492; // 43
+static const uint64_t SH_FLD_GXSTP_IN7 = 8493; // 43
+static const uint64_t SH_FLD_GXSTP_IN8 = 8494; // 43
+static const uint64_t SH_FLD_GXSTP_IN9 = 8495; // 43
+static const uint64_t SH_FLD_GX_ENABLE_OVERWRITE = 8496; // 1
+static const uint64_t SH_FLD_GX_LEN = 8497; // 2
+static const uint64_t SH_FLD_GZIPCOMP_MAX_INRD = 8498; // 1
+static const uint64_t SH_FLD_GZIPCOMP_MAX_INRD_LEN = 8499; // 1
+static const uint64_t SH_FLD_GZIPDECOMP_MAX_INRD = 8500; // 1
+static const uint64_t SH_FLD_GZIPDECOMP_MAX_INRD_LEN = 8501; // 1
+static const uint64_t SH_FLD_GZIP_COMP_PREFETCH_ENABLE = 8502; // 1
+static const uint64_t SH_FLD_GZIP_DECOMP_PREFETCH_ENABLE = 8503; // 1
+static const uint64_t SH_FLD_GZIP_FC_SELECT = 8504; // 1
+static const uint64_t SH_FLD_GZIP_FC_SELECT_LEN = 8505; // 1
+static const uint64_t SH_FLD_GZIP_LATENCY_CFG = 8506; // 1
+static const uint64_t SH_FLD_GZIP_MUX_SELECT = 8507; // 1
+static const uint64_t SH_FLD_GZIP_MUX_SELECT_LEN = 8508; // 1
+static const uint64_t SH_FLD_H1AP_CFG = 8509; // 6
+static const uint64_t SH_FLD_H1AP_CFG_LEN = 8510; // 6
+static const uint64_t SH_FLD_HALTED = 8511; // 1
+static const uint64_t SH_FLD_HALT_INPUT = 8512; // 1
+static const uint64_t SH_FLD_HALT_ON_TRIG = 8513; // 17
+static const uint64_t SH_FLD_HALT_ON_XSTOP = 8514; // 17
+static const uint64_t SH_FLD_HALT_ROTATION = 8515; // 8
+static const uint64_t SH_FLD_HANG_DATA_SCALE = 8516; // 5
+static const uint64_t SH_FLD_HANG_DATA_SCALE_LEN = 8517; // 5
+static const uint64_t SH_FLD_HANG_ON_ACK_DEAD = 8518; // 1
+static const uint64_t SH_FLD_HANG_ON_ADDR_ERROR = 8519; // 1
+static const uint64_t SH_FLD_HANG_PE_SCALE = 8520; // 3
+static const uint64_t SH_FLD_HANG_PE_SCALE_LEN = 8521; // 3
+static const uint64_t SH_FLD_HANG_PIB_RESET = 8522; // 1
+static const uint64_t SH_FLD_HANG_PLS_MULT = 8523; // 1
+static const uint64_t SH_FLD_HANG_PLS_MULT_LEN = 8524; // 1
+static const uint64_t SH_FLD_HANG_POLL_ENABLE = 8525; // 2
+static const uint64_t SH_FLD_HANG_POLL_PULSE_DIV = 8526; // 24
+static const uint64_t SH_FLD_HANG_POLL_PULSE_DIV_LEN = 8527; // 24
+static const uint64_t SH_FLD_HANG_POLL_SCALE = 8528; // 7
+static const uint64_t SH_FLD_HANG_POLL_SCALE_LEN = 8529; // 7
+static const uint64_t SH_FLD_HANG_RECOVERY_GTE_LEVEL1 = 8530; // 2
+static const uint64_t SH_FLD_HANG_RECOVERY_LIMIT_ERROR = 8531; // 2
+static const uint64_t SH_FLD_HANG_RESET = 8532; // 1
+static const uint64_t SH_FLD_HANG_SHM_SCALE = 8533; // 2
+static const uint64_t SH_FLD_HANG_SHM_SCALE_LEN = 8534; // 2
+static const uint64_t SH_FLD_HANG_SM_ON_ARE = 8535; // 2
+static const uint64_t SH_FLD_HANG_SM_ON_LINK_FAIL = 8536; // 2
+static const uint64_t SH_FLD_HARD_CE_COUNT = 8537; // 2
+static const uint64_t SH_FLD_HARD_CE_COUNT_LEN = 8538; // 2
+static const uint64_t SH_FLD_HARD_MCE_COUNT = 8539; // 2
+static const uint64_t SH_FLD_HARD_MCE_COUNT_LEN = 8540; // 2
+static const uint64_t SH_FLD_HARD_NCE_ETE_ATTN = 8541; // 2
+static const uint64_t SH_FLD_HASH_LPID_DIS = 8542; // 1
+static const uint64_t SH_FLD_HASH_PID_DIS = 8543; // 1
+static const uint64_t SH_FLD_HASH_SIZE_MASK = 8544; // 1
+static const uint64_t SH_FLD_HASH_SIZE_MASK_LEN = 8545; // 1
+static const uint64_t SH_FLD_HA_ILLEGAL_CONSUMER_ACCESS = 8546; // 4
+static const uint64_t SH_FLD_HA_ILLEGAL_PRODUCER_ACCESS = 8547; // 4
+static const uint64_t SH_FLD_HB_ERROR = 8548; // 1
+static const uint64_t SH_FLD_HB_MALF_MASK = 8549; // 1
+static const uint64_t SH_FLD_HDICE = 8550; // 96
+static const uint64_t SH_FLD_HDR_ARR_ECC_CORR_ENA = 8551; // 6
+static const uint64_t SH_FLD_HDR_ARR_ECC_SUE_ENA = 8552; // 6
+static const uint64_t SH_FLD_HI = 8553; // 1
+static const uint64_t SH_FLD_HIGH = 8554; // 1
+static const uint64_t SH_FLD_HIGH_IDLE_COUNT = 8555; // 8
+static const uint64_t SH_FLD_HIGH_IDLE_COUNT_LEN = 8556; // 8
+static const uint64_t SH_FLD_HIGH_IDLE_THRESHOLD = 8557; // 8
+static const uint64_t SH_FLD_HIGH_IDLE_THRESHOLD_LEN = 8558; // 8
+static const uint64_t SH_FLD_HIGH_LEN = 8559; // 1
+static const uint64_t SH_FLD_HILE = 8560; // 24
+static const uint64_t SH_FLD_HIRES_FMAX = 8561; // 6
+static const uint64_t SH_FLD_HIRES_FMAX_LEN = 8562; // 6
+static const uint64_t SH_FLD_HIRES_FMIN = 8563; // 6
+static const uint64_t SH_FLD_HIRES_FMIN_LEN = 8564; // 6
+static const uint64_t SH_FLD_HIRES_FMULT = 8565; // 6
+static const uint64_t SH_FLD_HIRES_FMULT_LEN = 8566; // 6
+static const uint64_t SH_FLD_HIRES_FREQIN_AVG = 8567; // 6
+static const uint64_t SH_FLD_HIRES_FREQIN_AVG_LEN = 8568; // 6
+static const uint64_t SH_FLD_HIRES_FREQIN_MAX = 8569; // 6
+static const uint64_t SH_FLD_HIRES_FREQIN_MAX_LEN = 8570; // 6
+static const uint64_t SH_FLD_HIRES_FREQIN_MIN = 8571; // 6
+static const uint64_t SH_FLD_HIRES_FREQIN_MIN_LEN = 8572; // 6
+static const uint64_t SH_FLD_HIRES_FREQOUT = 8573; // 6
+static const uint64_t SH_FLD_HIRES_FREQOUT_AVG = 8574; // 6
+static const uint64_t SH_FLD_HIRES_FREQOUT_AVG_LEN = 8575; // 6
+static const uint64_t SH_FLD_HIRES_FREQOUT_LEN = 8576; // 6
+static const uint64_t SH_FLD_HIRES_FREQOUT_MAX = 8577; // 6
+static const uint64_t SH_FLD_HIRES_FREQOUT_MAX_LEN = 8578; // 6
+static const uint64_t SH_FLD_HIRES_FREQOUT_MIN = 8579; // 6
+static const uint64_t SH_FLD_HIRES_FREQOUT_MIN_LEN = 8580; // 6
+static const uint64_t SH_FLD_HIST = 8581; // 6
+static const uint64_t SH_FLD_HISTORY_PRBS_POWER_UP = 8582; // 72
+static const uint64_t SH_FLD_HIST_ADDRESS = 8583; // 1
+static const uint64_t SH_FLD_HIST_ADDRESS_LEN = 8584; // 1
+static const uint64_t SH_FLD_HIST_DONE = 8585; // 1
+static const uint64_t SH_FLD_HIST_FREEZE_HISTORY = 8586; // 1
+static const uint64_t SH_FLD_HIST_LEN = 8587; // 6
+static const uint64_t SH_FLD_HIST_MANUAL_MODE_EN = 8588; // 1
+static const uint64_t SH_FLD_HIST_MASK = 8589; // 1
+static const uint64_t SH_FLD_HIST_MASK_LEN = 8590; // 1
+static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT = 8591; // 6
+static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LANE = 8592; // 6
+static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LANE_LEN = 8593; // 6
+static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LEN = 8594; // 6
+static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_MODE = 8595; // 6
+static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_MODE_LEN = 8596; // 6
+static const uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_VALID = 8597; // 6
+static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH = 8598; // 6
+static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LANE = 8599; // 6
+static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LANE_LEN = 8600; // 6
+static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LEN = 8601; // 6
+static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_MODE = 8602; // 6
+static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_MODE_LEN = 8603; // 6
+static const uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_VALID = 8604; // 6
+static const uint64_t SH_FLD_HIST_RESERVED = 8605; // 1
+static const uint64_t SH_FLD_HIST_RESERVED_LEN = 8606; // 1
+static const uint64_t SH_FLD_HIST_RESET_HISTORY = 8607; // 1
+static const uint64_t SH_FLD_HIST_START_NOT_STOP = 8608; // 1
+static const uint64_t SH_FLD_HIST_STOP_ON_ERROR_GT = 8609; // 1
+static const uint64_t SH_FLD_HIST_STOP_ON_ERROR_GT_LEN = 8610; // 1
+static const uint64_t SH_FLD_HIST_TRACE_TRAFFIC = 8611; // 1
+static const uint64_t SH_FLD_HI_ENABLE = 8612; // 2
+static const uint64_t SH_FLD_HI_FIXED_WINDOW_MODE = 8613; // 2
+static const uint64_t SH_FLD_HI_PRESCALE_MODE = 8614; // 2
+static const uint64_t SH_FLD_HI_SELECT = 8615; // 2
+static const uint64_t SH_FLD_HI_SELECT_LEN = 8616; // 2
+static const uint64_t SH_FLD_HMI_ACTIVE = 8617; // 1
+static const uint64_t SH_FLD_HMI_EXIT_ENABLE = 8618; // 96
+static const uint64_t SH_FLD_HMI_REQUEST_C0 = 8619; // 12
+static const uint64_t SH_FLD_HMI_REQUEST_C1 = 8620; // 12
+static const uint64_t SH_FLD_HOLD = 8621; // 2
+static const uint64_t SH_FLD_HOLD_0 = 8622; // 8
+static const uint64_t SH_FLD_HOLD_0_48 = 8623; // 1
+static const uint64_t SH_FLD_HOLD_0_48_LEN = 8624; // 1
+static const uint64_t SH_FLD_HOLD_1 = 8625; // 8
+static const uint64_t SH_FLD_HOLD_ADDRESS = 8626; // 90
+static const uint64_t SH_FLD_HOLD_ADDRESS_LEN = 8627; // 90
+static const uint64_t SH_FLD_HOLD_DBGTRIG_SEL = 8628; // 43
+static const uint64_t SH_FLD_HOLD_DBGTRIG_SEL_LEN = 8629; // 43
+static const uint64_t SH_FLD_HOLD_LEN = 8630; // 2
+static const uint64_t SH_FLD_HOLD_SAMPLE = 8631; // 43
+static const uint64_t SH_FLD_HOLD_SAMPLE_WITH_TRIGGER = 8632; // 43
+static const uint64_t SH_FLD_HOLE0_LOWER_ADDRESS = 8633; // 8
+static const uint64_t SH_FLD_HOLE0_LOWER_ADDRESS_LEN = 8634; // 8
+static const uint64_t SH_FLD_HOLE0_UPPER_ADDRESS = 8635; // 8
+static const uint64_t SH_FLD_HOLE0_UPPER_ADDRESS_LEN = 8636; // 8
+static const uint64_t SH_FLD_HOLE0_VALID = 8637; // 8
+static const uint64_t SH_FLD_HOLE1_LOWER_ADDRESS = 8638; // 8
+static const uint64_t SH_FLD_HOLE1_LOWER_ADDRESS_LEN = 8639; // 8
+static const uint64_t SH_FLD_HOLE1_UPPER_ADDRESS = 8640; // 8
+static const uint64_t SH_FLD_HOLE1_UPPER_ADDRESS_LEN = 8641; // 8
+static const uint64_t SH_FLD_HOLE1_VALID = 8642; // 8
+static const uint64_t SH_FLD_HOST_PREF_PGSZ = 8643; // 1
+static const uint64_t SH_FLD_HOST_PREF_PGSZ_LEN = 8644; // 1
+static const uint64_t SH_FLD_HRMOR = 8645; // 1
+static const uint64_t SH_FLD_HRMOR_LEN = 8646; // 1
+static const uint64_t SH_FLD_HSSCALERR = 8647; // 6
+static const uint64_t SH_FLD_HSSPLLAERR = 8648; // 6
+static const uint64_t SH_FLD_HSSPLLBERR = 8649; // 6
+static const uint64_t SH_FLD_HS_PROBE_TOP_SEL = 8650; // 8
+static const uint64_t SH_FLD_HTB_EXTEST = 8651; // 43
+static const uint64_t SH_FLD_HTB_INTEST = 8652; // 43
+static const uint64_t SH_FLD_HTMCO_STATUS_ADDR_ERROR = 8653; // 26
+static const uint64_t SH_FLD_HTMCO_STATUS_BUF_WAIT = 8654; // 26
+static const uint64_t SH_FLD_HTMCO_STATUS_COMPLETE = 8655; // 26
+static const uint64_t SH_FLD_HTMCO_STATUS_CRESP_OV = 8656; // 26
+static const uint64_t SH_FLD_HTMCO_STATUS_ENABLE = 8657; // 26
+static const uint64_t SH_FLD_HTMCO_STATUS_FLUSH = 8658; // 26
+static const uint64_t SH_FLD_HTMCO_STATUS_INIT = 8659; // 26
+static const uint64_t SH_FLD_HTMCO_STATUS_PAUSED = 8660; // 26
+static const uint64_t SH_FLD_HTMCO_STATUS_PREREQ = 8661; // 26
+static const uint64_t SH_FLD_HTMCO_STATUS_PURGE_DONE = 8662; // 24
+static const uint64_t SH_FLD_HTMCO_STATUS_PURGE_IN_PROG = 8663; // 24
+static const uint64_t SH_FLD_HTMCO_STATUS_READY = 8664; // 26
+static const uint64_t SH_FLD_HTMCO_STATUS_REPAIR = 8665; // 26
+static const uint64_t SH_FLD_HTMCO_STATUS_SPARE = 8666; // 2
+static const uint64_t SH_FLD_HTMCO_STATUS_SPARE_LEN = 8667; // 2
+static const uint64_t SH_FLD_HTMCO_STATUS_STAMP = 8668; // 26
+static const uint64_t SH_FLD_HTMCO_STATUS_TRACING = 8669; // 26
+static const uint64_t SH_FLD_HTMSC = 8670; // 24
+static const uint64_t SH_FLD_HTMSC_ALLOC = 8671; // 26
+static const uint64_t SH_FLD_HTMSC_BASE = 8672; // 26
+static const uint64_t SH_FLD_HTMSC_BASE_LEN = 8673; // 26
+static const uint64_t SH_FLD_HTMSC_CAPTURE = 8674; // 26
+static const uint64_t SH_FLD_HTMSC_CAPTURE_LEN = 8675; // 26
+static const uint64_t SH_FLD_HTMSC_CHIP0_STOP = 8676; // 24
+static const uint64_t SH_FLD_HTMSC_CHIP1_STOP = 8677; // 24
+static const uint64_t SH_FLD_HTMSC_CONTENT_SEL = 8678; // 26
+static const uint64_t SH_FLD_HTMSC_CONTENT_SEL_LEN = 8679; // 26
+static const uint64_t SH_FLD_HTMSC_COUNT = 8680; // 24
+static const uint64_t SH_FLD_HTMSC_COUNT_LEN = 8681; // 24
+static const uint64_t SH_FLD_HTMSC_CRESPFILT_INVERT = 8682; // 2
+static const uint64_t SH_FLD_HTMSC_CRESP_MASK = 8683; // 2
+static const uint64_t SH_FLD_HTMSC_CRESP_MASK_LEN = 8684; // 2
+static const uint64_t SH_FLD_HTMSC_CRESP_PAT = 8685; // 2
+static const uint64_t SH_FLD_HTMSC_CRESP_PAT_LEN = 8686; // 2
+static const uint64_t SH_FLD_HTMSC_DBG0_STOP = 8687; // 26
+static const uint64_t SH_FLD_HTMSC_DBG1_STOP = 8688; // 26
+static const uint64_t SH_FLD_HTMSC_DD1EQUIV = 8689; // 24
+static const uint64_t SH_FLD_HTMSC_DIS_DRP_PRIORITY_INCR = 8690; // 2
+static const uint64_t SH_FLD_HTMSC_DIS_FORCE_GROUP_SCOPE = 8691; // 2
+static const uint64_t SH_FLD_HTMSC_DIS_GROUP = 8692; // 24
+static const uint64_t SH_FLD_HTMSC_DIS_OPER_HANG = 8693; // 2
+static const uint64_t SH_FLD_HTMSC_DIS_RETRY_BACKOFF = 8694; // 2
+static const uint64_t SH_FLD_HTMSC_DIS_STALL = 8695; // 24
+static const uint64_t SH_FLD_HTMSC_DIS_TSTAMP = 8696; // 26
+static const uint64_t SH_FLD_HTMSC_ENABLE = 8697; // 26
+static const uint64_t SH_FLD_HTMSC_ENABLE_SPLIT_CORE = 8698; // 24
+static const uint64_t SH_FLD_HTMSC_ERROR = 8699; // 24
+static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL0 = 8700; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL0_LEN = 8701; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL1 = 8702; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL1_LEN = 8703; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL2 = 8704; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL2_LEN = 8705; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL0 = 8706; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL0_LEN = 8707; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL1 = 8708; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL1_LEN = 8709; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL2 = 8710; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL2_LEN = 8711; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL3 = 8712; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL3_LEN = 8713; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL4 = 8714; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL4_LEN = 8715; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL5 = 8716; // 2
+static const uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL5_LEN = 8717; // 2
+static const uint64_t SH_FLD_HTMSC_FSM = 8718; // 24
+static const uint64_t SH_FLD_HTMSC_FSM_LEN = 8719; // 24
+static const uint64_t SH_FLD_HTMSC_INVERT = 8720; // 2
+static const uint64_t SH_FLD_HTMSC_LEN = 8721; // 24
+static const uint64_t SH_FLD_HTMSC_MARK = 8722; // 26
+static const uint64_t SH_FLD_HTMSC_MARKERS_ONLY = 8723; // 26
+static const uint64_t SH_FLD_HTMSC_MARK_LEN = 8724; // 26
+static const uint64_t SH_FLD_HTMSC_MARK_TYPE = 8725; // 26
+static const uint64_t SH_FLD_HTMSC_MARK_TYPE_LEN = 8726; // 26
+static const uint64_t SH_FLD_HTMSC_MARK_VALID = 8727; // 26
+static const uint64_t SH_FLD_HTMSC_MASK = 8728; // 4
+static const uint64_t SH_FLD_HTMSC_MASK_LEN = 8729; // 4
+static const uint64_t SH_FLD_HTMSC_MTSPR_MARK = 8730; // 24
+static const uint64_t SH_FLD_HTMSC_MTSPR_TRIG = 8731; // 24
+static const uint64_t SH_FLD_HTMSC_OPER_HANG_DIV_RATIO = 8732; // 2
+static const uint64_t SH_FLD_HTMSC_OPER_HANG_DIV_RATIO_LEN = 8733; // 2
+static const uint64_t SH_FLD_HTMSC_OTHER_DBG0_STOP = 8734; // 2
+static const uint64_t SH_FLD_HTMSC_PAT = 8735; // 4
+static const uint64_t SH_FLD_HTMSC_PAT_LEN = 8736; // 4
+static const uint64_t SH_FLD_HTMSC_PAUSE = 8737; // 26
+static const uint64_t SH_FLD_HTMSC_PDBAR_ERROR = 8738; // 24
+static const uint64_t SH_FLD_HTMSC_PRIORITY = 8739; // 26
+static const uint64_t SH_FLD_HTMSC_RESERVED = 8740; // 24
+static const uint64_t SH_FLD_HTMSC_RESERVED_LEN = 8741; // 24
+static const uint64_t SH_FLD_HTMSC_RESET = 8742; // 26
+static const uint64_t SH_FLD_HTMSC_RTY_DRP_COUNT = 8743; // 2
+static const uint64_t SH_FLD_HTMSC_RTY_DRP_COUNT_LEN = 8744; // 2
+static const uint64_t SH_FLD_HTMSC_RUN_STOP = 8745; // 26
+static const uint64_t SH_FLD_HTMSC_SCOPE = 8746; // 50
+static const uint64_t SH_FLD_HTMSC_SCOPE_LEN = 8747; // 50
+static const uint64_t SH_FLD_HTMSC_SINGLE_TSTAMP = 8748; // 26
+static const uint64_t SH_FLD_HTMSC_SIZE = 8749; // 26
+static const uint64_t SH_FLD_HTMSC_SIZE_LEN = 8750; // 26
+static const uint64_t SH_FLD_HTMSC_SIZE_SMALL = 8751; // 26
+static const uint64_t SH_FLD_HTMSC_SPARE = 8752; // 24
+static const uint64_t SH_FLD_HTMSC_SPARE0 = 8753; // 24
+static const uint64_t SH_FLD_HTMSC_SPARE1012 = 8754; // 2
+static const uint64_t SH_FLD_HTMSC_SPARE1012_LEN = 8755; // 2
+static const uint64_t SH_FLD_HTMSC_SPARE1112 = 8756; // 24
+static const uint64_t SH_FLD_HTMSC_SPARE1112_LEN = 8757; // 24
+static const uint64_t SH_FLD_HTMSC_SPARE1415 = 8758; // 26
+static const uint64_t SH_FLD_HTMSC_SPARE1415_LEN = 8759; // 26
+static const uint64_t SH_FLD_HTMSC_SPARE16 = 8760; // 2
+static const uint64_t SH_FLD_HTMSC_SPARE23 = 8761; // 2
+static const uint64_t SH_FLD_HTMSC_SPARE2TO4 = 8762; // 24
+static const uint64_t SH_FLD_HTMSC_SPARE2TO4_LEN = 8763; // 24
+static const uint64_t SH_FLD_HTMSC_SPARE3 = 8764; // 2
+static const uint64_t SH_FLD_HTMSC_SPARE4043 = 8765; // 2
+static const uint64_t SH_FLD_HTMSC_SPARE4043_LEN = 8766; // 2
+static const uint64_t SH_FLD_HTMSC_SPARE67 = 8767; // 2
+static const uint64_t SH_FLD_HTMSC_SPARE67_LEN = 8768; // 2
+static const uint64_t SH_FLD_HTMSC_SPARES = 8769; // 24
+static const uint64_t SH_FLD_HTMSC_SPARES_LEN = 8770; // 24
+static const uint64_t SH_FLD_HTMSC_SPARE_1TO2 = 8771; // 24
+static const uint64_t SH_FLD_HTMSC_SPARE_1TO2_LEN = 8772; // 24
+static const uint64_t SH_FLD_HTMSC_SPARE_LEN = 8773; // 24
+static const uint64_t SH_FLD_HTMSC_START = 8774; // 26
+static const uint64_t SH_FLD_HTMSC_STOP = 8775; // 26
+static const uint64_t SH_FLD_HTMSC_STOP_ALT = 8776; // 26
+static const uint64_t SH_FLD_HTMSC_SYNC_STAMP_FORCE = 8777; // 2
+static const uint64_t SH_FLD_HTMSC_SYNC_STAMP_FORCE_LEN = 8778; // 2
+static const uint64_t SH_FLD_HTMSC_TRACE_ACTIVE = 8779; // 24
+static const uint64_t SH_FLD_HTMSC_TRIG = 8780; // 26
+static const uint64_t SH_FLD_HTMSC_TRIG_LEN = 8781; // 26
+static const uint64_t SH_FLD_HTMSC_TSIZEFILT_MASK = 8782; // 2
+static const uint64_t SH_FLD_HTMSC_TSIZEFILT_MASK_LEN = 8783; // 2
+static const uint64_t SH_FLD_HTMSC_TSIZEFILT_PAT = 8784; // 2
+static const uint64_t SH_FLD_HTMSC_TSIZEFILT_PAT_LEN = 8785; // 2
+static const uint64_t SH_FLD_HTMSC_VGTARGET = 8786; // 26
+static const uint64_t SH_FLD_HTMSC_VGTARGET_LEN = 8787; // 26
+static const uint64_t SH_FLD_HTMSC_WRAP = 8788; // 26
+static const uint64_t SH_FLD_HTMSC_WRITETOIO = 8789; // 2
+static const uint64_t SH_FLD_HTMSC_XSTOP_STOP = 8790; // 26
+static const uint64_t SH_FLD_HTM_CMD_OVERRUN = 8791; // 1
+static const uint64_t SH_FLD_HTM_GPE_SRC_SEL = 8792; // 1
+static const uint64_t SH_FLD_HTM_GPE_SRC_SEL_LEN = 8793; // 1
+static const uint64_t SH_FLD_HTM_MARKER_SLAVE_ADRS = 8794; // 1
+static const uint64_t SH_FLD_HTM_MARKER_SLAVE_ADRS_LEN = 8795; // 1
+static const uint64_t SH_FLD_HTM_QUEUE_LIMIT = 8796; // 12
+static const uint64_t SH_FLD_HTM_QUEUE_LIMIT_LEN = 8797; // 12
+static const uint64_t SH_FLD_HTM_SRC_SEL = 8798; // 1
+static const uint64_t SH_FLD_HTM_SRC_SEL_LEN = 8799; // 1
+static const uint64_t SH_FLD_HTM_STOP = 8800; // 1
+static const uint64_t SH_FLD_HTM_TRACE_MODE = 8801; // 1
+static const uint64_t SH_FLD_HUC = 8802; // 1
+static const uint64_t SH_FLD_HUC_LEN = 8803; // 1
+static const uint64_t SH_FLD_HUT = 8804; // 1
+static const uint64_t SH_FLD_HUT_LEN = 8805; // 1
+static const uint64_t SH_FLD_HWCTRL = 8806; // 2
+static const uint64_t SH_FLD_HWCTRL_CLOCK_DIVIDER = 8807; // 1
+static const uint64_t SH_FLD_HWCTRL_CLOCK_DIVIDER_LEN = 8808; // 1
+static const uint64_t SH_FLD_HWCTRL_CPHA = 8809; // 1
+static const uint64_t SH_FLD_HWCTRL_CPOL = 8810; // 1
+static const uint64_t SH_FLD_HWCTRL_DEVICE = 8811; // 1
+static const uint64_t SH_FLD_HWCTRL_FRAME_SIZE = 8812; // 1
+static const uint64_t SH_FLD_HWCTRL_FRAME_SIZE_LEN = 8813; // 1
+static const uint64_t SH_FLD_HWCTRL_FSM_ENABLE = 8814; // 1
+static const uint64_t SH_FLD_HWCTRL_FSM_ERR = 8815; // 1
+static const uint64_t SH_FLD_HWCTRL_INTER_FRAME_DELAY = 8816; // 1
+static const uint64_t SH_FLD_HWCTRL_INTER_FRAME_DELAY_LEN = 8817; // 1
+static const uint64_t SH_FLD_HWCTRL_INVALID_NUMBER_OF_FRAMES = 8818; // 1
+static const uint64_t SH_FLD_HWCTRL_IN_COUNT = 8819; // 1
+static const uint64_t SH_FLD_HWCTRL_IN_COUNT_LEN = 8820; // 1
+static const uint64_t SH_FLD_HWCTRL_IN_DELAY = 8821; // 1
+static const uint64_t SH_FLD_HWCTRL_IN_DELAY_LEN = 8822; // 1
+static const uint64_t SH_FLD_HWCTRL_LEN = 8823; // 2
+static const uint64_t SH_FLD_HWCTRL_NR_OF_FRAMES = 8824; // 1
+static const uint64_t SH_FLD_HWCTRL_NR_OF_FRAMES_LEN = 8825; // 1
+static const uint64_t SH_FLD_HWCTRL_ONGOING = 8826; // 1
+static const uint64_t SH_FLD_HWCTRL_OUT_COUNT = 8827; // 1
+static const uint64_t SH_FLD_HWCTRL_OUT_COUNT_LEN = 8828; // 1
+static const uint64_t SH_FLD_HWCTRL_RDATA0 = 8829; // 1
+static const uint64_t SH_FLD_HWCTRL_RDATA0_LEN = 8830; // 1
+static const uint64_t SH_FLD_HWCTRL_RDATA1 = 8831; // 1
+static const uint64_t SH_FLD_HWCTRL_RDATA1_LEN = 8832; // 1
+static const uint64_t SH_FLD_HWCTRL_RDATA2 = 8833; // 1
+static const uint64_t SH_FLD_HWCTRL_RDATA2_LEN = 8834; // 1
+static const uint64_t SH_FLD_HWCTRL_RDATA3 = 8835; // 1
+static const uint64_t SH_FLD_HWCTRL_RDATA3_LEN = 8836; // 1
+static const uint64_t SH_FLD_HWCTRL_START_SAMPLING = 8837; // 1
+static const uint64_t SH_FLD_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN = 8838; // 1
+static const uint64_t SH_FLD_HWCTRL_WRITE_WHILE_FSM_BUSY_ERR = 8839; // 1
+static const uint64_t SH_FLD_HWD = 8840; // 1
+static const uint64_t SH_FLD_HWD_0 = 8841; // 1
+static const uint64_t SH_FLD_HWD_0_LEN = 8842; // 1
+static const uint64_t SH_FLD_HWD_10 = 8843; // 1
+static const uint64_t SH_FLD_HWD_10_LEN = 8844; // 1
+static const uint64_t SH_FLD_HWD_11 = 8845; // 1
+static const uint64_t SH_FLD_HWD_11_LEN = 8846; // 1
+static const uint64_t SH_FLD_HWD_12 = 8847; // 1
+static const uint64_t SH_FLD_HWD_12_LEN = 8848; // 1
+static const uint64_t SH_FLD_HWD_13 = 8849; // 1
+static const uint64_t SH_FLD_HWD_13_LEN = 8850; // 1
+static const uint64_t SH_FLD_HWD_14 = 8851; // 1
+static const uint64_t SH_FLD_HWD_14_LEN = 8852; // 1
+static const uint64_t SH_FLD_HWD_15 = 8853; // 1
+static const uint64_t SH_FLD_HWD_15_LEN = 8854; // 1
+static const uint64_t SH_FLD_HWD_2 = 8855; // 1
+static const uint64_t SH_FLD_HWD_2_LEN = 8856; // 1
+static const uint64_t SH_FLD_HWD_3 = 8857; // 1
+static const uint64_t SH_FLD_HWD_3_LEN = 8858; // 1
+static const uint64_t SH_FLD_HWD_4 = 8859; // 1
+static const uint64_t SH_FLD_HWD_4_LEN = 8860; // 1
+static const uint64_t SH_FLD_HWD_5 = 8861; // 1
+static const uint64_t SH_FLD_HWD_5_LEN = 8862; // 1
+static const uint64_t SH_FLD_HWD_6 = 8863; // 1
+static const uint64_t SH_FLD_HWD_6_LEN = 8864; // 1
+static const uint64_t SH_FLD_HWD_7 = 8865; // 1
+static const uint64_t SH_FLD_HWD_7_LEN = 8866; // 1
+static const uint64_t SH_FLD_HWD_8 = 8867; // 1
+static const uint64_t SH_FLD_HWD_8_LEN = 8868; // 1
+static const uint64_t SH_FLD_HWD_9 = 8869; // 1
+static const uint64_t SH_FLD_HWD_9_LEN = 8870; // 1
+static const uint64_t SH_FLD_HWD_LEN = 8871; // 1
+static const uint64_t SH_FLD_HWD_PRIORITY = 8872; // 1
+static const uint64_t SH_FLD_HWD_PRIORITY_LEN = 8873; // 1
+static const uint64_t SH_FLD_HWD_RSD = 8874; // 1
+static const uint64_t SH_FLD_HWD_RSD_LEN = 8875; // 1
+static const uint64_t SH_FLD_HWMSX_PE = 8876; // 8
+static const uint64_t SH_FLD_HWMSX_PE_LEN = 8877; // 8
+static const uint64_t SH_FLD_HW_CONTROL_ERROR = 8878; // 12
+static const uint64_t SH_FLD_HW_DIR_INTIATED_LINE_DELETE_OCCURRED = 8879; // 12
+static const uint64_t SH_FLD_HW_PARITY_ERROR = 8880; // 2
+static const uint64_t SH_FLD_HYPERVISOR = 8881; // 4
+static const uint64_t SH_FLD_HYP_BLOCK = 8882; // 24
+static const uint64_t SH_FLD_HYP_BLOCK_LEN = 8883; // 24
+static const uint64_t SH_FLD_HYP_RECOURCE_ERR = 8884; // 96
+static const uint64_t SH_FLD_HYP_SPECIAL_WKUP = 8885; // 30
+static const uint64_t SH_FLD_HYP_VIRT_EXIT_ENABLE = 8886; // 96
+static const uint64_t SH_FLD_I2CM_ECC_ERRORS = 8887; // 1
+static const uint64_t SH_FLD_I2CM_ECC_ERRORS_LEN = 8888; // 1
+static const uint64_t SH_FLD_I2CM_I2C_ERRORS = 8889; // 1
+static const uint64_t SH_FLD_I2CM_I2C_ERRORS_LEN = 8890; // 1
+static const uint64_t SH_FLD_I2CM_INTER = 8891; // 1
+static const uint64_t SH_FLD_I2CM_INTR_STATUS = 8892; // 1
+static const uint64_t SH_FLD_I2CM_INTR_STATUS_LEN = 8893; // 1
+static const uint64_t SH_FLD_I2CM_PIB_ERRORS = 8894; // 1
+static const uint64_t SH_FLD_I2CM_PIB_ERRORS_LEN = 8895; // 1
+static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_0 = 8896; // 1
+static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_0_LEN = 8897; // 1
+static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_1 = 8898; // 1
+static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_1_LEN = 8899; // 1
+static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_2 = 8900; // 1
+static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_2_LEN = 8901; // 1
+static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_3 = 8902; // 1
+static const uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_3_LEN = 8903; // 1
+static const uint64_t SH_FLD_I2CM_TPM_DECONFIG_PROTECT = 8904; // 1
+static const uint64_t SH_FLD_I2C_BUS_HELD_MODE_ENABLE = 8905; // 1
+static const uint64_t SH_FLD_I2C_SPEED_MUX = 8906; // 1
+static const uint64_t SH_FLD_I2C_SPEED_MUX_LEN = 8907; // 1
+static const uint64_t SH_FLD_I2C_TIMEOUT_VALUE = 8908; // 1
+static const uint64_t SH_FLD_I2C_TIMEOUT_VALUE_LEN = 8909; // 1
+static const uint64_t SH_FLD_IBUF_ABANK = 8910; // 3
+static const uint64_t SH_FLD_IBUF_ABANK_LEN = 8911; // 3
+static const uint64_t SH_FLD_IBUF_AIDX = 8912; // 3
+static const uint64_t SH_FLD_IBUF_AIDX_LEN = 8913; // 3
+static const uint64_t SH_FLD_IBUF_RSRC = 8914; // 3
+static const uint64_t SH_FLD_IBUF_RSRC_LEN = 8915; // 3
+static const uint64_t SH_FLD_IBUF_WSRC = 8916; // 3
+static const uint64_t SH_FLD_IBUF_WSRC_LEN = 8917; // 3
+static const uint64_t SH_FLD_IBWR_MASK = 8918; // 3
+static const uint64_t SH_FLD_IBWR_MASK_LEN = 8919; // 3
+static const uint64_t SH_FLD_ICACHE_ERR = 8920; // 21
+static const uint64_t SH_FLD_ICACHE_PARITY_ERROR_INJECT = 8921; // 24
+static const uint64_t SH_FLD_ICACHE_TAG_ADDR = 8922; // 21
+static const uint64_t SH_FLD_ICACHE_TAG_ADDR_LEN = 8923; // 21
+static const uint64_t SH_FLD_ICACHE_VALID = 8924; // 21
+static const uint64_t SH_FLD_ICACHE_VALID_LEN = 8925; // 21
+static const uint64_t SH_FLD_ICE_COUNT = 8926; // 2
+static const uint64_t SH_FLD_ICE_COUNT_LEN = 8927; // 2
+static const uint64_t SH_FLD_ICE_ETE_ATTN = 8928; // 2
+static const uint64_t SH_FLD_ICRR_INTERCME_DIRECT_IN = 8929; // 12
+static const uint64_t SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN = 8930; // 12
+static const uint64_t SH_FLD_ICRR_INTERCME_DIRECT_OUT = 8931; // 12
+static const uint64_t SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN = 8932; // 12
+static const uint64_t SH_FLD_ICS_INVALID_STATE = 8933; // 1
+static const uint64_t SH_FLD_ICU_RNW = 8934; // 1
+static const uint64_t SH_FLD_ICU_TIMEOUT_ERROR = 8935; // 1
+static const uint64_t SH_FLD_ID = 8936; // 131
+static const uint64_t SH_FLD_IDIAL = 8937; // 35
+static const uint64_t SH_FLD_IDIAL_AMO_ADDR = 8938; // 3
+static const uint64_t SH_FLD_IDIAL_ATS = 8939; // 1
+static const uint64_t SH_FLD_IDIAL_ATS_ESR_MSK = 8940; // 1
+static const uint64_t SH_FLD_IDIAL_ATS_ESR_MSK_LEN = 8941; // 1
+static const uint64_t SH_FLD_IDIAL_ATS_FER_MSK = 8942; // 1
+static const uint64_t SH_FLD_IDIAL_ATS_FER_MSK_LEN = 8943; // 1
+static const uint64_t SH_FLD_IDIAL_ATS_LEN = 8944; // 1
+static const uint64_t SH_FLD_IDIAL_BBRD = 8945; // 3
+static const uint64_t SH_FLD_IDIAL_BBRD_LEN = 8946; // 3
+static const uint64_t SH_FLD_IDIAL_BBUF_RDWR = 8947; // 3
+static const uint64_t SH_FLD_IDIAL_BR_CE = 8948; // 3
+static const uint64_t SH_FLD_IDIAL_BR_CE_LEN = 8949; // 3
+static const uint64_t SH_FLD_IDIAL_BR_SUE = 8950; // 3
+static const uint64_t SH_FLD_IDIAL_BR_SUE_LEN = 8951; // 3
+static const uint64_t SH_FLD_IDIAL_BR_UE = 8952; // 3
+static const uint64_t SH_FLD_IDIAL_BR_UE_LEN = 8953; // 3
+static const uint64_t SH_FLD_IDIAL_CNTL_ERRP = 8954; // 1
+static const uint64_t SH_FLD_IDIAL_CONFIG1 = 8955; // 3
+static const uint64_t SH_FLD_IDIAL_COUNT0 = 8956; // 9
+static const uint64_t SH_FLD_IDIAL_COUNT0_LEN = 8957; // 9
+static const uint64_t SH_FLD_IDIAL_COUNT1 = 8958; // 9
+static const uint64_t SH_FLD_IDIAL_COUNT1_LEN = 8959; // 9
+static const uint64_t SH_FLD_IDIAL_COUNT2 = 8960; // 9
+static const uint64_t SH_FLD_IDIAL_COUNT2_LEN = 8961; // 9
+static const uint64_t SH_FLD_IDIAL_COUNT3 = 8962; // 9
+static const uint64_t SH_FLD_IDIAL_COUNT3_LEN = 8963; // 9
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_0 = 8964; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_1 = 8965; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_2 = 8966; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_3 = 8967; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_4 = 8968; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_5 = 8969; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_6 = 8970; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_7 = 8971; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_0 = 8972; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_1 = 8973; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_2 = 8974; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_3 = 8975; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_4 = 8976; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_5 = 8977; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_6 = 8978; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_7 = 8979; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_0 = 8980; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_1 = 8981; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_2 = 8982; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_3 = 8983; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_0 = 8984; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_1 = 8985; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_2 = 8986; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_3 = 8987; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_4 = 8988; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_5 = 8989; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_6 = 8990; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_7 = 8991; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_0 = 8992; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_1 = 8993; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_2 = 8994; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_3 = 8995; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_4 = 8996; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_5 = 8997; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_6 = 8998; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_7 = 8999; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_0 = 9000; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_1 = 9001; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_10 = 9002; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_11 = 9003; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_12 = 9004; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_13 = 9005; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_14 = 9006; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_15 = 9007; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_2 = 9008; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_3 = 9009; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_4 = 9010; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_5 = 9011; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_6 = 9012; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_7 = 9013; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_8 = 9014; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_9 = 9015; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_0 = 9016; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_1 = 9017; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_10 = 9018; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_11 = 9019; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_12 = 9020; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_13 = 9021; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_14 = 9022; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_15 = 9023; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_16 = 9024; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_17 = 9025; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_18 = 9026; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_19 = 9027; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_2 = 9028; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_20 = 9029; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_21 = 9030; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_22 = 9031; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_23 = 9032; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_3 = 9033; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_4 = 9034; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_5 = 9035; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_6 = 9036; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_7 = 9037; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_8 = 9038; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_9 = 9039; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_0 = 9040; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_1 = 9041; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_2 = 9042; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_3 = 9043; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_4 = 9044; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_5 = 9045; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_6 = 9046; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_7 = 9047; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_0 = 9048; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_1 = 9049; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_2 = 9050; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_3 = 9051; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_4 = 9052; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_5 = 9053; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_6 = 9054; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_7 = 9055; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_0 = 9056; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_1 = 9057; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_2 = 9058; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_3 = 9059; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_4 = 9060; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_5 = 9061; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_6 = 9062; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_7 = 9063; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_0 = 9064; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_1 = 9065; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_2 = 9066; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_3 = 9067; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_4 = 9068; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_5 = 9069; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_6 = 9070; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_7 = 9071; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_0 = 9072; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_1 = 9073; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_2 = 9074; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_3 = 9075; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_0 = 9076; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_1 = 9077; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_2 = 9078; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_3 = 9079; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_0 = 9080; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_1 = 9081; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_2 = 9082; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_3 = 9083; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_0 = 9084; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_1 = 9085; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_2 = 9086; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_3 = 9087; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_0 = 9088; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_1 = 9089; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_2 = 9090; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_3 = 9091; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_0 = 9092; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_1 = 9093; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_2 = 9094; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_3 = 9095; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_4 = 9096; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_5 = 9097; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_6 = 9098; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_7 = 9099; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_0 = 9100; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_1 = 9101; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_2 = 9102; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_3 = 9103; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_4 = 9104; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_5 = 9105; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_6 = 9106; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_7 = 9107; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_0 = 9108; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_1 = 9109; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_2 = 9110; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_3 = 9111; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_0 = 9112; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_1 = 9113; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_2 = 9114; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_3 = 9115; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_4 = 9116; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_5 = 9117; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_6 = 9118; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_7 = 9119; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_0 = 9120; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_1 = 9121; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_2 = 9122; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_3 = 9123; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_4 = 9124; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_5 = 9125; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_6 = 9126; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_7 = 9127; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_0 = 9128; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_1 = 9129; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_10 = 9130; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_11 = 9131; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_12 = 9132; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_13 = 9133; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_14 = 9134; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_15 = 9135; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_2 = 9136; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_3 = 9137; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_4 = 9138; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_5 = 9139; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_6 = 9140; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_7 = 9141; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_8 = 9142; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_9 = 9143; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_0 = 9144; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_1 = 9145; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_10 = 9146; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_11 = 9147; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_12 = 9148; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_13 = 9149; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_14 = 9150; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_15 = 9151; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_16 = 9152; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_17 = 9153; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_18 = 9154; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_19 = 9155; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_2 = 9156; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_20 = 9157; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_21 = 9158; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_22 = 9159; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_23 = 9160; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_3 = 9161; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_4 = 9162; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_5 = 9163; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_6 = 9164; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_7 = 9165; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_8 = 9166; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_9 = 9167; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_0 = 9168; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_1 = 9169; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_2 = 9170; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_3 = 9171; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_4 = 9172; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_5 = 9173; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_6 = 9174; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_7 = 9175; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_0 = 9176; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_1 = 9177; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_2 = 9178; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_3 = 9179; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_4 = 9180; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_5 = 9181; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_6 = 9182; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_7 = 9183; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_0 = 9184; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_1 = 9185; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_2 = 9186; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_3 = 9187; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_4 = 9188; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_5 = 9189; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_6 = 9190; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_7 = 9191; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_0 = 9192; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_1 = 9193; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_2 = 9194; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_3 = 9195; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_4 = 9196; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_5 = 9197; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_6 = 9198; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_7 = 9199; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_0 = 9200; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_1 = 9201; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_2 = 9202; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_3 = 9203; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_0 = 9204; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_1 = 9205; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_2 = 9206; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_3 = 9207; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_0 = 9208; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_1 = 9209; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_2 = 9210; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_3 = 9211; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_0 = 9212; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_1 = 9213; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_2 = 9214; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_3 = 9215; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_0 = 9216; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_1 = 9217; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_2 = 9218; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_3 = 9219; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_0 = 9220; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_1 = 9221; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_2 = 9222; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_3 = 9223; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_4 = 9224; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_5 = 9225; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_6 = 9226; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_7 = 9227; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_0 = 9228; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_1 = 9229; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_2 = 9230; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_3 = 9231; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_4 = 9232; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_5 = 9233; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_6 = 9234; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_7 = 9235; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_0 = 9236; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_1 = 9237; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_2 = 9238; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_3 = 9239; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_0 = 9240; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_1 = 9241; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_2 = 9242; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_3 = 9243; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_4 = 9244; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_5 = 9245; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_6 = 9246; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_7 = 9247; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_0 = 9248; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_1 = 9249; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_2 = 9250; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_3 = 9251; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_4 = 9252; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_5 = 9253; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_6 = 9254; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_7 = 9255; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_0 = 9256; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_1 = 9257; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_10 = 9258; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_11 = 9259; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_12 = 9260; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_13 = 9261; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_14 = 9262; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_15 = 9263; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_2 = 9264; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_3 = 9265; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_4 = 9266; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_5 = 9267; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_6 = 9268; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_7 = 9269; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_8 = 9270; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_9 = 9271; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_0 = 9272; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_1 = 9273; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_10 = 9274; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_11 = 9275; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_12 = 9276; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_13 = 9277; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_14 = 9278; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_15 = 9279; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_16 = 9280; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_17 = 9281; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_18 = 9282; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_19 = 9283; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_2 = 9284; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_20 = 9285; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_21 = 9286; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_22 = 9287; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_23 = 9288; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_3 = 9289; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_4 = 9290; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_5 = 9291; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_6 = 9292; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_7 = 9293; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_8 = 9294; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_9 = 9295; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_0 = 9296; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_1 = 9297; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_2 = 9298; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_3 = 9299; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_4 = 9300; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_5 = 9301; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_6 = 9302; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_7 = 9303; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_0 = 9304; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_1 = 9305; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_2 = 9306; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_3 = 9307; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_4 = 9308; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_5 = 9309; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_6 = 9310; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_7 = 9311; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_0 = 9312; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_1 = 9313; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_2 = 9314; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_3 = 9315; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_4 = 9316; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_5 = 9317; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_6 = 9318; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_7 = 9319; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_0 = 9320; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_1 = 9321; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_2 = 9322; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_3 = 9323; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_4 = 9324; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_5 = 9325; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_6 = 9326; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_7 = 9327; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_0 = 9328; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_1 = 9329; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_2 = 9330; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_3 = 9331; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_REG_0 = 9332; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_REG_1 = 9333; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_REG_2 = 9334; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_REG_3 = 9335; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_0 = 9336; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_1 = 9337; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_2 = 9338; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_3 = 9339; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_0 = 9340; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_1 = 9341; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_2 = 9342; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_3 = 9343; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_0 = 9344; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_1 = 9345; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_2 = 9346; // 3
+static const uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_3 = 9347; // 3
+static const uint64_t SH_FLD_IDIAL_DEBUG0_CONFIG = 9348; // 3
+static const uint64_t SH_FLD_IDIAL_DEBUG1_CONFIG = 9349; // 3
+static const uint64_t SH_FLD_IDIAL_EA = 9350; // 2
+static const uint64_t SH_FLD_IDIAL_EA_LEN = 9351; // 2
+static const uint64_t SH_FLD_IDIAL_ECC_CONFIG = 9352; // 3
+static const uint64_t SH_FLD_IDIAL_ERRINJ = 9353; // 3
+static const uint64_t SH_FLD_IDIAL_IBAR_ERRP = 9354; // 1
+static const uint64_t SH_FLD_IDIAL_IBRD = 9355; // 3
+static const uint64_t SH_FLD_IDIAL_IBRD_LEN = 9356; // 3
+static const uint64_t SH_FLD_IDIAL_IBUF_CTL_PIPE = 9357; // 3
+static const uint64_t SH_FLD_IDIAL_IBUF_RDWR = 9358; // 3
+static const uint64_t SH_FLD_IDIAL_IBUF_STATE = 9359; // 3
+static const uint64_t SH_FLD_IDIAL_IBUF_WARB = 9360; // 3
+static const uint64_t SH_FLD_IDIAL_IBUF_WRITE = 9361; // 3
+static const uint64_t SH_FLD_IDIAL_INHIBIT_CONFIG = 9362; // 3
+static const uint64_t SH_FLD_IDIAL_IR_CE = 9363; // 3
+static const uint64_t SH_FLD_IDIAL_IR_CE_LEN = 9364; // 3
+static const uint64_t SH_FLD_IDIAL_IR_SUE = 9365; // 3
+static const uint64_t SH_FLD_IDIAL_IR_SUE_LEN = 9366; // 3
+static const uint64_t SH_FLD_IDIAL_IR_UE = 9367; // 3
+static const uint64_t SH_FLD_IDIAL_IR_UE_LEN = 9368; // 3
+static const uint64_t SH_FLD_IDIAL_ISSYNC = 9369; // 1
+static const uint64_t SH_FLD_IDIAL_ISSYNC_LEN = 9370; // 1
+static const uint64_t SH_FLD_IDIAL_LEN = 9371; // 35
+static const uint64_t SH_FLD_IDIAL_MISC_STATE = 9372; // 3
+static const uint64_t SH_FLD_IDIAL_MM_LOCAL_XSTOP = 9373; // 1
+static const uint64_t SH_FLD_IDIAL_MRG_IR_PIPE = 9374; // 3
+static const uint64_t SH_FLD_IDIAL_MRG_OR_PIPE = 9375; // 3
+static const uint64_t SH_FLD_IDIAL_MRG_STATE = 9376; // 3
+static const uint64_t SH_FLD_IDIAL_NDL0_NOSTALL = 9377; // 1
+static const uint64_t SH_FLD_IDIAL_NDL0_STALL = 9378; // 1
+static const uint64_t SH_FLD_IDIAL_NDL1_NOSTALL = 9379; // 1
+static const uint64_t SH_FLD_IDIAL_NDL1_STALL = 9380; // 1
+static const uint64_t SH_FLD_IDIAL_NDL2_NOSTALL = 9381; // 1
+static const uint64_t SH_FLD_IDIAL_NDL2_STALL = 9382; // 1
+static const uint64_t SH_FLD_IDIAL_NDL3_NOSTALL = 9383; // 1
+static const uint64_t SH_FLD_IDIAL_NDL3_STALL = 9384; // 1
+static const uint64_t SH_FLD_IDIAL_NDL4_NOSTALL = 9385; // 1
+static const uint64_t SH_FLD_IDIAL_NDL4_STALL = 9386; // 1
+static const uint64_t SH_FLD_IDIAL_NDL5_NOSTALL = 9387; // 1
+static const uint64_t SH_FLD_IDIAL_NDL5_STALL = 9388; // 1
+static const uint64_t SH_FLD_IDIAL_OBRD = 9389; // 3
+static const uint64_t SH_FLD_IDIAL_OBRD_LEN = 9390; // 3
+static const uint64_t SH_FLD_IDIAL_OBUF_RDWR = 9391; // 3
+static const uint64_t SH_FLD_IDIAL_OBUF_STATE = 9392; // 3
+static const uint64_t SH_FLD_IDIAL_OR_CE = 9393; // 3
+static const uint64_t SH_FLD_IDIAL_OR_CE_LEN = 9394; // 3
+static const uint64_t SH_FLD_IDIAL_OR_SUE = 9395; // 3
+static const uint64_t SH_FLD_IDIAL_OR_SUE_LEN = 9396; // 3
+static const uint64_t SH_FLD_IDIAL_OR_UE = 9397; // 3
+static const uint64_t SH_FLD_IDIAL_OR_UE_LEN = 9398; // 3
+static const uint64_t SH_FLD_IDIAL_PAR = 9399; // 1
+static const uint64_t SH_FLD_IDIAL_PAR_LEN = 9400; // 1
+static const uint64_t SH_FLD_IDIAL_PBRX_RTAG = 9401; // 6
+static const uint64_t SH_FLD_IDIAL_PBTX_AMO = 9402; // 3
+static const uint64_t SH_FLD_IDIAL_PBTX_AMO_LEN = 9403; // 3
+static const uint64_t SH_FLD_IDIAL_PBTX_PIPE = 9404; // 3
+static const uint64_t SH_FLD_IDIAL_PBTX_STATE = 9405; // 3
+static const uint64_t SH_FLD_IDIAL_PC = 9406; // 2
+static const uint64_t SH_FLD_IDIAL_PC_LEN = 9407; // 2
+static const uint64_t SH_FLD_IDIAL_PE = 9408; // 2
+static const uint64_t SH_FLD_IDIAL_PE_LEN = 9409; // 2
+static const uint64_t SH_FLD_IDIAL_PR_CE = 9410; // 3
+static const uint64_t SH_FLD_IDIAL_PR_CE_LEN = 9411; // 3
+static const uint64_t SH_FLD_IDIAL_PR_SUE = 9412; // 3
+static const uint64_t SH_FLD_IDIAL_PR_SUE_LEN = 9413; // 3
+static const uint64_t SH_FLD_IDIAL_PR_UE = 9414; // 3
+static const uint64_t SH_FLD_IDIAL_PR_UE_LEN = 9415; // 3
+static const uint64_t SH_FLD_IDIAL_PT_CE = 9416; // 3
+static const uint64_t SH_FLD_IDIAL_PT_CE_LEN = 9417; // 3
+static const uint64_t SH_FLD_IDIAL_PT_SUE = 9418; // 3
+static const uint64_t SH_FLD_IDIAL_PT_SUE_LEN = 9419; // 3
+static const uint64_t SH_FLD_IDIAL_PT_UE = 9420; // 3
+static const uint64_t SH_FLD_IDIAL_PT_UE_LEN = 9421; // 3
+static const uint64_t SH_FLD_IDIAL_RA = 9422; // 2
+static const uint64_t SH_FLD_IDIAL_RA_LEN = 9423; // 2
+static const uint64_t SH_FLD_IDIAL_RING_ERRP = 9424; // 1
+static const uint64_t SH_FLD_IDIAL_RNW = 9425; // 1
+static const uint64_t SH_FLD_IDIAL_RQIN_OVF = 9426; // 3
+static const uint64_t SH_FLD_IDIAL_RQIN_OVF_LEN = 9427; // 3
+static const uint64_t SH_FLD_IDIAL_RQIN_STATE = 9428; // 3
+static const uint64_t SH_FLD_IDIAL_RSVD0 = 9429; // 4
+static const uint64_t SH_FLD_IDIAL_RSVD0_LEN = 9430; // 4
+static const uint64_t SH_FLD_IDIAL_RSVD1 = 9431; // 2
+static const uint64_t SH_FLD_IDIAL_RSVD1_LEN = 9432; // 2
+static const uint64_t SH_FLD_IDIAL_SCOMDAA_ERRP = 9433; // 1
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_0 = 9434; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_1 = 9435; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_2 = 9436; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_3 = 9437; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_0 = 9438; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_1 = 9439; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_2 = 9440; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_3 = 9441; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_0 = 9442; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_1 = 9443; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_2 = 9444; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_3 = 9445; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_0 = 9446; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_1 = 9447; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_2 = 9448; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_3 = 9449; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_4 = 9450; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_5 = 9451; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_6 = 9452; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_7 = 9453; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_0 = 9454; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_1 = 9455; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_10 = 9456; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_11 = 9457; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_12 = 9458; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_13 = 9459; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_14 = 9460; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_15 = 9461; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_2 = 9462; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_3 = 9463; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_4 = 9464; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_5 = 9465; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_6 = 9466; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_7 = 9467; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_8 = 9468; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_9 = 9469; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_0 = 9470; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_1 = 9471; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_10 = 9472; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_11 = 9473; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_12 = 9474; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_13 = 9475; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_14 = 9476; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_15 = 9477; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_16 = 9478; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_17 = 9479; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_18 = 9480; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_19 = 9481; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_2 = 9482; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_20 = 9483; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_21 = 9484; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_22 = 9485; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_23 = 9486; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_24 = 9487; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_25 = 9488; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_26 = 9489; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_27 = 9490; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_28 = 9491; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_29 = 9492; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_3 = 9493; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_30 = 9494; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_31 = 9495; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_32 = 9496; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_33 = 9497; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_34 = 9498; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_35 = 9499; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_36 = 9500; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_37 = 9501; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_38 = 9502; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_39 = 9503; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_4 = 9504; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_40 = 9505; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_41 = 9506; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_42 = 9507; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_43 = 9508; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_44 = 9509; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_45 = 9510; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_46 = 9511; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_47 = 9512; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_48 = 9513; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_49 = 9514; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_5 = 9515; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_50 = 9516; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_51 = 9517; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_52 = 9518; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_53 = 9519; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_54 = 9520; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_55 = 9521; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_56 = 9522; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_57 = 9523; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_58 = 9524; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_59 = 9525; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_6 = 9526; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_60 = 9527; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_61 = 9528; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_62 = 9529; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_63 = 9530; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_7 = 9531; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_8 = 9532; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_9 = 9533; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_0 = 9534; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_1 = 9535; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_10 = 9536; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_11 = 9537; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_12 = 9538; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_13 = 9539; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_14 = 9540; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_15 = 9541; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_16 = 9542; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_17 = 9543; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_18 = 9544; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_19 = 9545; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_2 = 9546; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_20 = 9547; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_21 = 9548; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_22 = 9549; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_23 = 9550; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_24 = 9551; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_25 = 9552; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_26 = 9553; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_27 = 9554; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_28 = 9555; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_29 = 9556; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_3 = 9557; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_30 = 9558; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_31 = 9559; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_4 = 9560; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_5 = 9561; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_6 = 9562; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_7 = 9563; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_8 = 9564; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_9 = 9565; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_0 = 9566; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_1 = 9567; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_10 = 9568; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_11 = 9569; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_2 = 9570; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_3 = 9571; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_4 = 9572; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_5 = 9573; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_6 = 9574; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_7 = 9575; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_8 = 9576; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_9 = 9577; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_0 = 9578; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_1 = 9579; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_10 = 9580; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_11 = 9581; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_2 = 9582; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_3 = 9583; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_4 = 9584; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_5 = 9585; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_6 = 9586; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_7 = 9587; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_8 = 9588; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_9 = 9589; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_0 = 9590; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_1 = 9591; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_2 = 9592; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_3 = 9593; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_4 = 9594; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_5 = 9595; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_6 = 9596; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_7 = 9597; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_0 = 9598; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_1 = 9599; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_2 = 9600; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_3 = 9601; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_4 = 9602; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_5 = 9603; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_6 = 9604; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_7 = 9605; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_REG_0 = 9606; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_REG_1 = 9607; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_REG_2 = 9608; // 12
+static const uint64_t SH_FLD_IDIAL_SM_FIRST_REG_3 = 9609; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_0 = 9610; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_1 = 9611; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_2 = 9612; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_3 = 9613; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_0 = 9614; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_1 = 9615; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_2 = 9616; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_3 = 9617; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_0 = 9618; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_1 = 9619; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_2 = 9620; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_3 = 9621; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_0 = 9622; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_1 = 9623; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_2 = 9624; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_3 = 9625; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_4 = 9626; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_5 = 9627; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_6 = 9628; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_7 = 9629; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_0 = 9630; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_1 = 9631; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_10 = 9632; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_11 = 9633; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_12 = 9634; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_13 = 9635; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_14 = 9636; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_15 = 9637; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_2 = 9638; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_3 = 9639; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_4 = 9640; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_5 = 9641; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_6 = 9642; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_7 = 9643; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_8 = 9644; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_9 = 9645; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_0 = 9646; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_1 = 9647; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_10 = 9648; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_11 = 9649; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_12 = 9650; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_13 = 9651; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_14 = 9652; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_15 = 9653; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_16 = 9654; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_17 = 9655; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_18 = 9656; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_19 = 9657; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_2 = 9658; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_20 = 9659; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_21 = 9660; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_22 = 9661; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_23 = 9662; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_24 = 9663; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_25 = 9664; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_26 = 9665; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_27 = 9666; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_28 = 9667; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_29 = 9668; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_3 = 9669; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_30 = 9670; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_31 = 9671; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_32 = 9672; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_33 = 9673; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_34 = 9674; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_35 = 9675; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_36 = 9676; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_37 = 9677; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_38 = 9678; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_39 = 9679; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_4 = 9680; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_40 = 9681; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_41 = 9682; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_42 = 9683; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_43 = 9684; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_44 = 9685; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_45 = 9686; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_46 = 9687; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_47 = 9688; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_48 = 9689; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_49 = 9690; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_5 = 9691; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_50 = 9692; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_51 = 9693; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_52 = 9694; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_53 = 9695; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_54 = 9696; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_55 = 9697; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_56 = 9698; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_57 = 9699; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_58 = 9700; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_59 = 9701; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_6 = 9702; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_60 = 9703; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_61 = 9704; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_62 = 9705; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_63 = 9706; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_7 = 9707; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_8 = 9708; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_9 = 9709; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_0 = 9710; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_1 = 9711; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_10 = 9712; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_11 = 9713; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_12 = 9714; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_13 = 9715; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_14 = 9716; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_15 = 9717; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_16 = 9718; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_17 = 9719; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_18 = 9720; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_19 = 9721; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_2 = 9722; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_20 = 9723; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_21 = 9724; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_22 = 9725; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_23 = 9726; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_24 = 9727; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_25 = 9728; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_26 = 9729; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_27 = 9730; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_28 = 9731; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_29 = 9732; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_3 = 9733; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_30 = 9734; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_31 = 9735; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_4 = 9736; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_5 = 9737; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_6 = 9738; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_7 = 9739; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_8 = 9740; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_9 = 9741; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_0 = 9742; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_1 = 9743; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_10 = 9744; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_11 = 9745; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_2 = 9746; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_3 = 9747; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_4 = 9748; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_5 = 9749; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_6 = 9750; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_7 = 9751; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_8 = 9752; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_9 = 9753; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_0 = 9754; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_1 = 9755; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_10 = 9756; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_11 = 9757; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_2 = 9758; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_3 = 9759; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_4 = 9760; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_5 = 9761; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_6 = 9762; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_7 = 9763; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_8 = 9764; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_9 = 9765; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_0 = 9766; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_1 = 9767; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_2 = 9768; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_3 = 9769; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_4 = 9770; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_5 = 9771; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_6 = 9772; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_7 = 9773; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_0 = 9774; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_1 = 9775; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_2 = 9776; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_3 = 9777; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_4 = 9778; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_5 = 9779; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_6 = 9780; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_7 = 9781; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_REG_0 = 9782; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_REG_1 = 9783; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_REG_2 = 9784; // 12
+static const uint64_t SH_FLD_IDIAL_SM_HOLD_REG_3 = 9785; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_0 = 9786; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_1 = 9787; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_2 = 9788; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_3 = 9789; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_AUE_0 = 9790; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_AUE_1 = 9791; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_AUE_2 = 9792; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_AUE_3 = 9793; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_FWD_0 = 9794; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_FWD_1 = 9795; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_FWD_2 = 9796; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_FWD_3 = 9797; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_0 = 9798; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_1 = 9799; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_2 = 9800; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_3 = 9801; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_4 = 9802; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_5 = 9803; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_6 = 9804; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NCF_7 = 9805; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_0 = 9806; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_1 = 9807; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_10 = 9808; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_11 = 9809; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_12 = 9810; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_13 = 9811; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_14 = 9812; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_15 = 9813; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_2 = 9814; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_3 = 9815; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_4 = 9816; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_5 = 9817; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_6 = 9818; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_7 = 9819; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_8 = 9820; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_9 = 9821; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_0 = 9822; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_1 = 9823; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_10 = 9824; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_11 = 9825; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_12 = 9826; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_13 = 9827; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_14 = 9828; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_15 = 9829; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_16 = 9830; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_17 = 9831; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_18 = 9832; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_19 = 9833; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_2 = 9834; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_20 = 9835; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_21 = 9836; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_22 = 9837; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_23 = 9838; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_24 = 9839; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_25 = 9840; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_26 = 9841; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_27 = 9842; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_28 = 9843; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_29 = 9844; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_3 = 9845; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_30 = 9846; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_31 = 9847; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_32 = 9848; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_33 = 9849; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_34 = 9850; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_35 = 9851; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_36 = 9852; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_37 = 9853; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_38 = 9854; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_39 = 9855; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_4 = 9856; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_40 = 9857; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_41 = 9858; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_42 = 9859; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_43 = 9860; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_44 = 9861; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_45 = 9862; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_46 = 9863; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_47 = 9864; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_48 = 9865; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_49 = 9866; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_5 = 9867; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_50 = 9868; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_51 = 9869; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_52 = 9870; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_53 = 9871; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_54 = 9872; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_55 = 9873; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_56 = 9874; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_57 = 9875; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_58 = 9876; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_59 = 9877; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_6 = 9878; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_60 = 9879; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_61 = 9880; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_62 = 9881; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_63 = 9882; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_7 = 9883; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_8 = 9884; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NLG_9 = 9885; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_0 = 9886; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_1 = 9887; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_10 = 9888; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_11 = 9889; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_12 = 9890; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_13 = 9891; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_14 = 9892; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_15 = 9893; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_16 = 9894; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_17 = 9895; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_18 = 9896; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_19 = 9897; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_2 = 9898; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_20 = 9899; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_21 = 9900; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_22 = 9901; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_23 = 9902; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_24 = 9903; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_25 = 9904; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_26 = 9905; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_27 = 9906; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_28 = 9907; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_29 = 9908; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_3 = 9909; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_30 = 9910; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_31 = 9911; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_4 = 9912; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_5 = 9913; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_6 = 9914; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_7 = 9915; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_8 = 9916; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_NVF_9 = 9917; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_0 = 9918; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_1 = 9919; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_10 = 9920; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_11 = 9921; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_2 = 9922; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_3 = 9923; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_4 = 9924; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_5 = 9925; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_6 = 9926; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_7 = 9927; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_8 = 9928; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBC_9 = 9929; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_0 = 9930; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_1 = 9931; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_10 = 9932; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_11 = 9933; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_2 = 9934; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_3 = 9935; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_4 = 9936; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_5 = 9937; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_6 = 9938; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_7 = 9939; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_8 = 9940; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBF_9 = 9941; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_0 = 9942; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_1 = 9943; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_2 = 9944; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_3 = 9945; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_4 = 9946; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_5 = 9947; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_6 = 9948; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBP_7 = 9949; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_0 = 9950; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_1 = 9951; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_2 = 9952; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_3 = 9953; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_4 = 9954; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_5 = 9955; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_6 = 9956; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_PBR_7 = 9957; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_REG_0 = 9958; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_REG_1 = 9959; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_REG_2 = 9960; // 12
+static const uint64_t SH_FLD_IDIAL_SM_MASK_REG_3 = 9961; // 12
+static const uint64_t SH_FLD_IDIAL_TAG = 9962; // 1
+static const uint64_t SH_FLD_IDIAL_TAG_LEN = 9963; // 1
+static const uint64_t SH_FLD_IDIAL_VLD = 9964; // 1
+static const uint64_t SH_FLD_IDIR_ERROR_INJECT = 9965; // 24
+static const uint64_t SH_FLD_IDLE = 9966; // 2
+static const uint64_t SH_FLD_IDLES = 9967; // 64
+static const uint64_t SH_FLD_IDLES_LEN = 9968; // 64
+static const uint64_t SH_FLD_IDLE_INDICATION = 9969; // 1
+static const uint64_t SH_FLD_IDLE_PAT_ACTN = 9970; // 2
+static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_0_13 = 9971; // 2
+static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_0_13_LEN = 9972; // 2
+static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_14 = 9973; // 2
+static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_15 = 9974; // 2
+static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_16 = 9975; // 2
+static const uint64_t SH_FLD_IDLE_PAT_ADDRESS_17 = 9976; // 2
+static const uint64_t SH_FLD_IDLE_PAT_BANK_0_1 = 9977; // 2
+static const uint64_t SH_FLD_IDLE_PAT_BANK_0_1_LEN = 9978; // 2
+static const uint64_t SH_FLD_IDLE_PAT_BANK_2 = 9979; // 2
+static const uint64_t SH_FLD_IDLE_PAT_BANK_GROUP_0 = 9980; // 2
+static const uint64_t SH_FLD_IDLE_PAT_BANK_GROUP_1 = 9981; // 2
+static const uint64_t SH_FLD_IDLE_PAT_PARITY = 9982; // 2
+static const uint64_t SH_FLD_IDR_LCL_SAMPLE_EN = 9983; // 12
+static const uint64_t SH_FLD_ID_LEN = 9984; // 129
+static const uint64_t SH_FLD_IERAT_EA_INJECT = 9985; // 24
+static const uint64_t SH_FLD_IERAT_RA_INJECT = 9986; // 24
+static const uint64_t SH_FLD_IFC_REG_CERR0 = 9987; // 1
+static const uint64_t SH_FLD_IFC_REG_CERR1 = 9988; // 1
+static const uint64_t SH_FLD_IFC_REG_CERR2 = 9989; // 1
+static const uint64_t SH_FLD_IFC_REG_ERR0 = 9990; // 1
+static const uint64_t SH_FLD_IFC_REG_ERR1 = 9991; // 1
+static const uint64_t SH_FLD_IFC_REG_ERR2 = 9992; // 1
+static const uint64_t SH_FLD_IFC_REG_ERR3 = 9993; // 1
+static const uint64_t SH_FLD_IFC_REG_ERR4 = 9994; // 1
+static const uint64_t SH_FLD_IFC_REG_ERR5 = 9995; // 1
+static const uint64_t SH_FLD_IFC_REG_ERR6 = 9996; // 1
+static const uint64_t SH_FLD_IFC_REG_ERR7 = 9997; // 1
+static const uint64_t SH_FLD_IFC_REG_ERR8 = 9998; // 1
+static const uint64_t SH_FLD_IFREQ = 9999; // 1
+static const uint64_t SH_FLD_IGNORE_PECE = 10000; // 12
+static const uint64_t SH_FLD_ILLEGAL_CACHE_OP = 10001; // 1
+static const uint64_t SH_FLD_ILLEGAL_CACHE_OP_MASK = 10002; // 1
+static const uint64_t SH_FLD_ILLEGAL_LPC_BAR_ACCESS = 10003; // 4
+static const uint64_t SH_FLD_ILL_CRESP = 10004; // 1
+static const uint64_t SH_FLD_IMA_ACK_DEAD = 10005; // 12
+static const uint64_t SH_FLD_IMA_CRESP_ADDR_ERR = 10006; // 12
+static const uint64_t SH_FLD_IMM_FREEZE = 10007; // 43
+static const uint64_t SH_FLD_IN = 10008; // 264
+static const uint64_t SH_FLD_IN0 = 10009; // 339
+static const uint64_t SH_FLD_IN1 = 10010; // 296
+static const uint64_t SH_FLD_IN10 = 10011; // 208
+static const uint64_t SH_FLD_IN11 = 10012; // 208
+static const uint64_t SH_FLD_IN11_LEN = 10013; // 3
+static const uint64_t SH_FLD_IN12 = 10014; // 162
+static const uint64_t SH_FLD_IN12_LEN = 10015; // 6
+static const uint64_t SH_FLD_IN13 = 10016; // 156
+static const uint64_t SH_FLD_IN13_LEN = 10017; // 12
+static const uint64_t SH_FLD_IN14 = 10018; // 144
+static const uint64_t SH_FLD_IN14_LEN = 10019; // 3
+static const uint64_t SH_FLD_IN15 = 10020; // 141
+static const uint64_t SH_FLD_IN16 = 10021; // 141
+static const uint64_t SH_FLD_IN17 = 10022; // 141
+static const uint64_t SH_FLD_IN17_LEN = 10023; // 6
+static const uint64_t SH_FLD_IN18 = 10024; // 135
+static const uint64_t SH_FLD_IN18_LEN = 10025; // 3
+static const uint64_t SH_FLD_IN19 = 10026; // 132
+static const uint64_t SH_FLD_IN2 = 10027; // 296
+static const uint64_t SH_FLD_IN20 = 10028; // 132
+static const uint64_t SH_FLD_IN21 = 10029; // 132
+static const uint64_t SH_FLD_IN21_LEN = 10030; // 3
+static const uint64_t SH_FLD_IN22 = 10031; // 129
+static const uint64_t SH_FLD_IN23 = 10032; // 43
+static const uint64_t SH_FLD_IN24 = 10033; // 43
+static const uint64_t SH_FLD_IN25 = 10034; // 43
+static const uint64_t SH_FLD_IN26 = 10035; // 129
+static const uint64_t SH_FLD_IN27 = 10036; // 43
+static const uint64_t SH_FLD_IN28 = 10037; // 43
+static const uint64_t SH_FLD_IN29 = 10038; // 43
+static const uint64_t SH_FLD_IN3 = 10039; // 296
+static const uint64_t SH_FLD_IN30 = 10040; // 43
+static const uint64_t SH_FLD_IN31 = 10041; // 43
+static const uint64_t SH_FLD_IN32 = 10042; // 43
+static const uint64_t SH_FLD_IN33 = 10043; // 43
+static const uint64_t SH_FLD_IN34 = 10044; // 43
+static const uint64_t SH_FLD_IN35 = 10045; // 43
+static const uint64_t SH_FLD_IN36 = 10046; // 43
+static const uint64_t SH_FLD_IN37 = 10047; // 43
+static const uint64_t SH_FLD_IN38 = 10048; // 43
+static const uint64_t SH_FLD_IN39 = 10049; // 43
+static const uint64_t SH_FLD_IN3_LEN = 10050; // 1
+static const uint64_t SH_FLD_IN4 = 10051; // 338
+static const uint64_t SH_FLD_IN40 = 10052; // 43
+static const uint64_t SH_FLD_IN41 = 10053; // 43
+static const uint64_t SH_FLD_IN4_LEN = 10054; // 1
+static const uint64_t SH_FLD_IN5 = 10055; // 337
+static const uint64_t SH_FLD_IN5_LEN = 10056; // 78
+static const uint64_t SH_FLD_IN6 = 10057; // 260
+static const uint64_t SH_FLD_IN6_LEN = 10058; // 3
+static const uint64_t SH_FLD_IN7 = 10059; // 257
+static const uint64_t SH_FLD_IN7_LEN = 10060; // 9
+static const uint64_t SH_FLD_IN8 = 10061; // 248
+static const uint64_t SH_FLD_IN8_LEN = 10062; // 3
+static const uint64_t SH_FLD_IN9 = 10063; // 245
+static const uint64_t SH_FLD_INBAND_BAR_HIT_WITH_INCORRECT_TTYPE = 10064; // 4
+static const uint64_t SH_FLD_INBD_ARRAY_ECC_CE = 10065; // 2
+static const uint64_t SH_FLD_INBD_ARRAY_ECC_UE = 10066; // 2
+static const uint64_t SH_FLD_INBD_LCO_ARRAY_ECC_CE = 10067; // 1
+static const uint64_t SH_FLD_INBD_LCO_ARRAY_ECC_SUE = 10068; // 1
+static const uint64_t SH_FLD_INBD_LCO_ARRAY_ECC_UE = 10069; // 1
+static const uint64_t SH_FLD_INCLUDE_TRAFFIC = 10070; // 1
+static const uint64_t SH_FLD_INCOMING_PB_PARITY_ERR = 10071; // 2
+static const uint64_t SH_FLD_INDEX = 10072; // 1
+static const uint64_t SH_FLD_INDEX_LEN = 10073; // 1
+static const uint64_t SH_FLD_INDIRECT_BRIDGE_0_SOURCE = 10074; // 1
+static const uint64_t SH_FLD_INDIRECT_BRIDGE_1_SOURCE = 10075; // 1
+static const uint64_t SH_FLD_INDIRECT_BRIDGE_2_SOURCE = 10076; // 1
+static const uint64_t SH_FLD_INDIRECT_BRIDGE_3_SOURCE = 10077; // 1
+static const uint64_t SH_FLD_INDIRECT_MODE = 10078; // 2
+static const uint64_t SH_FLD_INDIR_THRDID = 10079; // 4
+static const uint64_t SH_FLD_INDIR_THRDID_LEN = 10080; // 4
+static const uint64_t SH_FLD_INDIR_VLD = 10081; // 4
+static const uint64_t SH_FLD_INEX = 10082; // 43
+static const uint64_t SH_FLD_INFINITE_MODE = 10083; // 43
+static const uint64_t SH_FLD_INFO = 10084; // 43
+static const uint64_t SH_FLD_INFORMATION = 10085; // 8
+static const uint64_t SH_FLD_INFORMATION_LEN = 10086; // 8
+static const uint64_t SH_FLD_INFO_CAPTURED = 10087; // 4
+static const uint64_t SH_FLD_INH0_TICK = 10088; // 12
+static const uint64_t SH_FLD_INH0_TICK_LEN = 10089; // 12
+static const uint64_t SH_FLD_INH1_TICK = 10090; // 12
+static const uint64_t SH_FLD_INH1_TICK_LEN = 10091; // 12
+static const uint64_t SH_FLD_INIT = 10092; // 1
+static const uint64_t SH_FLD_INITIAL_COARSE_WR = 10093; // 8
+static const uint64_t SH_FLD_INITIAL_PAT_WRITE = 10094; // 8
+static const uint64_t SH_FLD_INIT_DONE_DL_MASK = 10095; // 2
+static const uint64_t SH_FLD_INIT_REQUEST = 10096; // 1
+static const uint64_t SH_FLD_INIT_TIMER = 10097; // 1
+static const uint64_t SH_FLD_INIT_TIMER_LEN = 10098; // 1
+static const uint64_t SH_FLD_INIT_TMR_CFG = 10099; // 72
+static const uint64_t SH_FLD_INIT_TMR_CFG_LEN = 10100; // 72
+static const uint64_t SH_FLD_INJ = 10101; // 1
+static const uint64_t SH_FLD_INJECT_1HOT_SM_ERROR = 10102; // 8
+static const uint64_t SH_FLD_INJECT_ENABLE = 10103; // 1
+static const uint64_t SH_FLD_INJECT_ERR = 10104; // 12
+static const uint64_t SH_FLD_INJECT_FIR_ERR0 = 10105; // 8
+static const uint64_t SH_FLD_INJECT_FIR_ERR1 = 10106; // 8
+static const uint64_t SH_FLD_INJECT_FIR_ERR2 = 10107; // 8
+static const uint64_t SH_FLD_INJECT_FIR_ERR3 = 10108; // 8
+static const uint64_t SH_FLD_INJECT_FIR_ERR4 = 10109; // 8
+static const uint64_t SH_FLD_INJECT_MODE = 10110; // 2
+static const uint64_t SH_FLD_INJECT_MODE_LEN = 10111; // 2
+static const uint64_t SH_FLD_INJECT_TYPE = 10112; // 2
+static const uint64_t SH_FLD_INJECT_TYPE_LEN = 10113; // 2
+static const uint64_t SH_FLD_INJ_LEN = 10114; // 1
+static const uint64_t SH_FLD_INOP = 10115; // 43
+static const uint64_t SH_FLD_INOP_FORCE_SG = 10116; // 43
+static const uint64_t SH_FLD_INOP_LEN = 10117; // 43
+static const uint64_t SH_FLD_INOP_WAIT = 10118; // 43
+static const uint64_t SH_FLD_INOP_WAIT_LEN = 10119; // 43
+static const uint64_t SH_FLD_INPROG_WR_ERR = 10120; // 1
+static const uint64_t SH_FLD_INRD_DONE_ERR = 10121; // 1
+static const uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK = 10122; // 43
+static const uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_DO = 10123; // 43
+static const uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN = 10124; // 43
+static const uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN = 10125; // 43
+static const uint64_t SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL = 10126; // 43
+static const uint64_t SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 10127; // 43
+static const uint64_t SH_FLD_INST1_CHECKSTOP_MODE_LT = 10128; // 43
+static const uint64_t SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN = 10129; // 43
+static const uint64_t SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR = 10130; // 43
+static const uint64_t SH_FLD_INST1_COND3_ENABLE = 10131; // 43
+static const uint64_t SH_FLD_INST1_CONDITION1_ACTION_BANK = 10132; // 43
+static const uint64_t SH_FLD_INST1_CONDITION1_ACTION_DO = 10133; // 43
+static const uint64_t SH_FLD_INST1_CONDITION1_ACTION_DO_LEN = 10134; // 43
+static const uint64_t SH_FLD_INST1_CONDITION1_ACTION_WAITN = 10135; // 43
+static const uint64_t SH_FLD_INST1_CONDITION1_TRIG_SEL = 10136; // 43
+static const uint64_t SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN = 10137; // 43
+static const uint64_t SH_FLD_INST1_CONDITION2_ACTION_BANK = 10138; // 43
+static const uint64_t SH_FLD_INST1_CONDITION2_ACTION_DO = 10139; // 43
+static const uint64_t SH_FLD_INST1_CONDITION2_ACTION_DO_LEN = 10140; // 43
+static const uint64_t SH_FLD_INST1_CONDITION2_ACTION_WAITN = 10141; // 43
+static const uint64_t SH_FLD_INST1_CONDITION2_TRIG_SEL = 10142; // 43
+static const uint64_t SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN = 10143; // 43
+static const uint64_t SH_FLD_INST1_SLOW_LFSR_MODE = 10144; // 43
+static const uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK = 10145; // 43
+static const uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_DO = 10146; // 43
+static const uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN = 10147; // 43
+static const uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN = 10148; // 43
+static const uint64_t SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL = 10149; // 43
+static const uint64_t SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 10150; // 43
+static const uint64_t SH_FLD_INST2_CHECKSTOP_MODE_LT = 10151; // 43
+static const uint64_t SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN = 10152; // 43
+static const uint64_t SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR = 10153; // 43
+static const uint64_t SH_FLD_INST2_COND3_ENABLE = 10154; // 43
+static const uint64_t SH_FLD_INST2_CONDITION1_ACTION_BANK = 10155; // 43
+static const uint64_t SH_FLD_INST2_CONDITION1_ACTION_DO = 10156; // 43
+static const uint64_t SH_FLD_INST2_CONDITION1_ACTION_DO_LEN = 10157; // 43
+static const uint64_t SH_FLD_INST2_CONDITION1_ACTION_WAITN = 10158; // 43
+static const uint64_t SH_FLD_INST2_CONDITION1_TRIG_SEL = 10159; // 43
+static const uint64_t SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN = 10160; // 43
+static const uint64_t SH_FLD_INST2_CONDITION2_ACTION_BANK = 10161; // 43
+static const uint64_t SH_FLD_INST2_CONDITION2_ACTION_DO = 10162; // 43
+static const uint64_t SH_FLD_INST2_CONDITION2_ACTION_DO_LEN = 10163; // 43
+static const uint64_t SH_FLD_INST2_CONDITION2_ACTION_WAITN = 10164; // 43
+static const uint64_t SH_FLD_INST2_CONDITION2_TRIG_SEL = 10165; // 43
+static const uint64_t SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN = 10166; // 43
+static const uint64_t SH_FLD_INST2_SLOW_LFSR_MODE = 10167; // 43
+static const uint64_t SH_FLD_INST3_COND3_ENABLE = 10168; // 43
+static const uint64_t SH_FLD_INST3_SLOW_LFSR_MODE = 10169; // 43
+static const uint64_t SH_FLD_INST4_COND3_ENABLE = 10170; // 43
+static const uint64_t SH_FLD_INST4_SLOW_LFSR_MODE = 10171; // 43
+static const uint64_t SH_FLD_INSTANT_CACHE_VDM_DATA = 10172; // 12
+static const uint64_t SH_FLD_INSTANT_CACHE_VDM_DATA_LEN = 10173; // 12
+static const uint64_t SH_FLD_INSTANT_CORE0_VDM_DATA = 10174; // 12
+static const uint64_t SH_FLD_INSTANT_CORE0_VDM_DATA_LEN = 10175; // 12
+static const uint64_t SH_FLD_INSTANT_CORE1_VDM_DATA = 10176; // 12
+static const uint64_t SH_FLD_INSTANT_CORE1_VDM_DATA_LEN = 10177; // 12
+static const uint64_t SH_FLD_INSTANT_CORE2_VDM_DATA = 10178; // 12
+static const uint64_t SH_FLD_INSTANT_CORE2_VDM_DATA_LEN = 10179; // 12
+static const uint64_t SH_FLD_INSTANT_CORE3_VDM_DATA = 10180; // 12
+static const uint64_t SH_FLD_INSTANT_CORE3_VDM_DATA_LEN = 10181; // 12
+static const uint64_t SH_FLD_INSTANT_VDM_CONTROL_SUMMARY = 10182; // 12
+static const uint64_t SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN = 10183; // 12
+static const uint64_t SH_FLD_INSTR0_BUSYCNT_RUNNING = 10184; // 1
+static const uint64_t SH_FLD_INSTR0_CYCLECNT_RUNNING = 10185; // 1
+static const uint64_t SH_FLD_INSTR0_MODE = 10186; // 1
+static const uint64_t SH_FLD_INSTR0_MODE_LEN = 10187; // 1
+static const uint64_t SH_FLD_INSTR0_RESET = 10188; // 1
+static const uint64_t SH_FLD_INSTR0_START = 10189; // 1
+static const uint64_t SH_FLD_INSTR0_STOP = 10190; // 1
+static const uint64_t SH_FLD_INSTR0_STOPPED_ON_ERROR = 10191; // 1
+static const uint64_t SH_FLD_INSTR0_STOP_ON_ERROR_GT = 10192; // 1
+static const uint64_t SH_FLD_INSTR0_STOP_ON_ERROR_GT_LEN = 10193; // 1
+static const uint64_t SH_FLD_INSTR0_STOP_TIMER_EN = 10194; // 1
+static const uint64_t SH_FLD_INSTR1_BUSYCNT_RUNNING = 10195; // 1
+static const uint64_t SH_FLD_INSTR1_CYCLECNT_RUNNING = 10196; // 1
+static const uint64_t SH_FLD_INSTR1_MODE = 10197; // 1
+static const uint64_t SH_FLD_INSTR1_MODE_LEN = 10198; // 1
+static const uint64_t SH_FLD_INSTR1_RESET = 10199; // 1
+static const uint64_t SH_FLD_INSTR1_START = 10200; // 1
+static const uint64_t SH_FLD_INSTR1_STOP = 10201; // 1
+static const uint64_t SH_FLD_INSTR1_STOPPED_ON_ERROR = 10202; // 1
+static const uint64_t SH_FLD_INSTR1_STOP_ON_ERROR_GT = 10203; // 1
+static const uint64_t SH_FLD_INSTR1_STOP_ON_ERROR_GT_LEN = 10204; // 1
+static const uint64_t SH_FLD_INSTR1_STOP_TIMER_EN = 10205; // 1
+static const uint64_t SH_FLD_INSTR2_BUSYCNT_RUNNING = 10206; // 1
+static const uint64_t SH_FLD_INSTR2_CYCLECNT_RUNNING = 10207; // 1
+static const uint64_t SH_FLD_INSTR2_MODE = 10208; // 1
+static const uint64_t SH_FLD_INSTR2_MODE_LEN = 10209; // 1
+static const uint64_t SH_FLD_INSTR2_RESET = 10210; // 1
+static const uint64_t SH_FLD_INSTR2_START = 10211; // 1
+static const uint64_t SH_FLD_INSTR2_STOP = 10212; // 1
+static const uint64_t SH_FLD_INSTR2_STOPPED_ON_ERROR = 10213; // 1
+static const uint64_t SH_FLD_INSTR2_STOP_ON_ERROR_GT = 10214; // 1
+static const uint64_t SH_FLD_INSTR2_STOP_ON_ERROR_GT_LEN = 10215; // 1
+static const uint64_t SH_FLD_INSTR2_STOP_TIMER_EN = 10216; // 1
+static const uint64_t SH_FLD_INST_CYCLE_SAMPLE = 10217; // 12
+static const uint64_t SH_FLD_INST_CYCLE_SAMPLE_LEN = 10218; // 12
+static const uint64_t SH_FLD_INTERCME_DIRECT_IN_0 = 10219; // 12
+static const uint64_t SH_FLD_INTERCME_DIRECT_IN_1_2 = 10220; // 12
+static const uint64_t SH_FLD_INTERCME_DIRECT_IN_1_2_LEN = 10221; // 12
+static const uint64_t SH_FLD_INTERMITTENT_CE_COUNT = 10222; // 2
+static const uint64_t SH_FLD_INTERMITTENT_CE_COUNT_LEN = 10223; // 2
+static const uint64_t SH_FLD_INTERMITTENT_MCE_COUNT = 10224; // 2
+static const uint64_t SH_FLD_INTERMITTENT_MCE_COUNT_LEN = 10225; // 2
+static const uint64_t SH_FLD_INTERNAL = 10226; // 14
+static const uint64_t SH_FLD_INTERNAL_ERR = 10227; // 1
+static const uint64_t SH_FLD_INTERNAL_ERROR = 10228; // 5
+static const uint64_t SH_FLD_INTERNAL_ERR_MASK = 10229; // 1
+static const uint64_t SH_FLD_INTERNAL_FSM_ERROR = 10230; // 2
+static const uint64_t SH_FLD_INTERNAL_LEN = 10231; // 14
+static const uint64_t SH_FLD_INTERNAL_PARITY_ERROR = 10232; // 6
+static const uint64_t SH_FLD_INTERNAL_SCOM_ERROR = 10233; // 32
+static const uint64_t SH_FLD_INTERNAL_SCOM_ERROR_CLONE = 10234; // 8
+static const uint64_t SH_FLD_INTERNAL_SCOM_ERROR_COPY = 10235; // 24
+static const uint64_t SH_FLD_INTERNAL_STATE_VECTOR = 10236; // 1
+static const uint64_t SH_FLD_INTERNAL_STATE_VECTOR_LEN = 10237; // 1
+static const uint64_t SH_FLD_INTERRUPT = 10238; // 3
+static const uint64_t SH_FLD_INTERRUPT0_ADDRESS_ERROR = 10239; // 4
+static const uint64_t SH_FLD_INTERRUPT1 = 10240; // 1
+static const uint64_t SH_FLD_INTERRUPT1_ADDRESS_ERROR = 10241; // 4
+static const uint64_t SH_FLD_INTERRUPT1_LEN = 10242; // 1
+static const uint64_t SH_FLD_INTERRUPT2 = 10243; // 1
+static const uint64_t SH_FLD_INTERRUPT2_ADDRESS_ERROR = 10244; // 4
+static const uint64_t SH_FLD_INTERRUPT2_LEN = 10245; // 1
+static const uint64_t SH_FLD_INTERRUPT3 = 10246; // 1
+static const uint64_t SH_FLD_INTERRUPT3_ADDRESS_ERROR = 10247; // 4
+static const uint64_t SH_FLD_INTERRUPT3_LEN = 10248; // 1
+static const uint64_t SH_FLD_INTERRUPT4 = 10249; // 1
+static const uint64_t SH_FLD_INTERRUPT4_ADDRESS_ERROR = 10250; // 4
+static const uint64_t SH_FLD_INTERRUPT4_LEN = 10251; // 1
+static const uint64_t SH_FLD_INTERRUPT5_ADDRESS_ERROR = 10252; // 4
+static const uint64_t SH_FLD_INTERRUPT_00 = 10253; // 1
+static const uint64_t SH_FLD_INTERRUPT_01 = 10254; // 1
+static const uint64_t SH_FLD_INTERRUPT_02 = 10255; // 1
+static const uint64_t SH_FLD_INTERRUPT_03 = 10256; // 1
+static const uint64_t SH_FLD_INTERRUPT_04 = 10257; // 1
+static const uint64_t SH_FLD_INTERRUPT_05 = 10258; // 1
+static const uint64_t SH_FLD_INTERRUPT_06 = 10259; // 1
+static const uint64_t SH_FLD_INTERRUPT_07 = 10260; // 1
+static const uint64_t SH_FLD_INTERRUPT_08 = 10261; // 1
+static const uint64_t SH_FLD_INTERRUPT_09 = 10262; // 1
+static const uint64_t SH_FLD_INTERRUPT_10 = 10263; // 1
+static const uint64_t SH_FLD_INTERRUPT_11 = 10264; // 1
+static const uint64_t SH_FLD_INTERRUPT_12 = 10265; // 1
+static const uint64_t SH_FLD_INTERRUPT_13 = 10266; // 1
+static const uint64_t SH_FLD_INTERRUPT_14 = 10267; // 1
+static const uint64_t SH_FLD_INTERRUPT_15 = 10268; // 1
+static const uint64_t SH_FLD_INTERRUPT_16 = 10269; // 1
+static const uint64_t SH_FLD_INTERRUPT_17 = 10270; // 1
+static const uint64_t SH_FLD_INTERRUPT_18 = 10271; // 1
+static const uint64_t SH_FLD_INTERRUPT_19 = 10272; // 1
+static const uint64_t SH_FLD_INTERRUPT_20 = 10273; // 1
+static const uint64_t SH_FLD_INTERRUPT_21 = 10274; // 1
+static const uint64_t SH_FLD_INTERRUPT_22 = 10275; // 1
+static const uint64_t SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE = 10276; // 4
+static const uint64_t SH_FLD_INTERRUPT_CONDITION_PENDING = 10277; // 1
+static const uint64_t SH_FLD_INTERRUPT_DISABLE = 10278; // 1
+static const uint64_t SH_FLD_INTERRUPT_DISABLE_LEN = 10279; // 1
+static const uint64_t SH_FLD_INTERRUPT_EDGE_POL_N = 10280; // 2
+static const uint64_t SH_FLD_INTERRUPT_EDGE_POL_N_LEN = 10281; // 2
+static const uint64_t SH_FLD_INTERRUPT_ENABLED = 10282; // 1
+static const uint64_t SH_FLD_INTERRUPT_FROM_ERROR = 10283; // 4
+static const uint64_t SH_FLD_INTERRUPT_FROM_FSP = 10284; // 4
+static const uint64_t SH_FLD_INTERRUPT_INPUT = 10285; // 12
+static const uint64_t SH_FLD_INTERRUPT_INPUT_LEN = 10286; // 12
+static const uint64_t SH_FLD_INTERRUPT_MASK = 10287; // 12
+static const uint64_t SH_FLD_INTERRUPT_MASK_LEN = 10288; // 12
+static const uint64_t SH_FLD_INTERRUPT_MASK_N = 10289; // 2
+static const uint64_t SH_FLD_INTERRUPT_MASK_N_LEN = 10290; // 2
+static const uint64_t SH_FLD_INTERRUPT_POLARITY = 10291; // 12
+static const uint64_t SH_FLD_INTERRUPT_POLARITY_LEN = 10292; // 12
+static const uint64_t SH_FLD_INTERRUPT_ROUTE_A_N = 10293; // 6
+static const uint64_t SH_FLD_INTERRUPT_ROUTE_A_N_LEN = 10294; // 6
+static const uint64_t SH_FLD_INTERRUPT_S0 = 10295; // 1
+static const uint64_t SH_FLD_INTERRUPT_S1 = 10296; // 1
+static const uint64_t SH_FLD_INTERRUPT_SENT = 10297; // 1
+static const uint64_t SH_FLD_INTERRUPT_TYPE = 10298; // 12
+static const uint64_t SH_FLD_INTERRUPT_TYPE_LEN = 10299; // 12
+static const uint64_t SH_FLD_INTERRUPT_TYPE_N = 10300; // 2
+static const uint64_t SH_FLD_INTERRUPT_TYPE_N_LEN = 10301; // 2
+static const uint64_t SH_FLD_INTER_FRAME_DELAY = 10302; // 1
+static const uint64_t SH_FLD_INTER_FRAME_DELAY_LEN = 10303; // 1
+static const uint64_t SH_FLD_INTQ_BAD_CRESP = 10304; // 1
+static const uint64_t SH_FLD_INTQ_FSM_PERR = 10305; // 1
+static const uint64_t SH_FLD_INTQ_OP_HANG = 10306; // 1
+static const uint64_t SH_FLD_INTQ_OVERFLOW = 10307; // 1
+static const uint64_t SH_FLD_INTR0 = 10308; // 5
+static const uint64_t SH_FLD_INTR1 = 10309; // 5
+static const uint64_t SH_FLD_INTR_GRANTED = 10310; // 30
+static const uint64_t SH_FLD_INT_0 = 10311; // 4
+static const uint64_t SH_FLD_INT_0_LEN = 10312; // 4
+static const uint64_t SH_FLD_INT_1 = 10313; // 2
+static const uint64_t SH_FLD_INT_1_LEN = 10314; // 2
+static const uint64_t SH_FLD_INT_2 = 10315; // 2
+static const uint64_t SH_FLD_INT_2_LEN = 10316; // 2
+static const uint64_t SH_FLD_INT_3 = 10317; // 2
+static const uint64_t SH_FLD_INT_3_LEN = 10318; // 2
+static const uint64_t SH_FLD_INT_CNTR_REF = 10319; // 1
+static const uint64_t SH_FLD_INT_CNTR_REF_LEN = 10320; // 1
+static const uint64_t SH_FLD_INT_CURRENT_STATE = 10321; // 6
+static const uint64_t SH_FLD_INT_CURRENT_STATE_LEN = 10322; // 6
+static const uint64_t SH_FLD_INT_ENA = 10323; // 1
+static const uint64_t SH_FLD_INT_ENABLE_ENC = 10324; // 6
+static const uint64_t SH_FLD_INT_ENABLE_ENC_LEN = 10325; // 6
+static const uint64_t SH_FLD_INT_GOTO_STATE = 10326; // 6
+static const uint64_t SH_FLD_INT_GOTO_STATE_LEN = 10327; // 6
+static const uint64_t SH_FLD_INT_MODE = 10328; // 6
+static const uint64_t SH_FLD_INT_MODE_LEN = 10329; // 6
+static const uint64_t SH_FLD_INT_NCE_ETE_ATTN = 10330; // 2
+static const uint64_t SH_FLD_INT_NEXT_STATE = 10331; // 6
+static const uint64_t SH_FLD_INT_NEXT_STATE_LEN = 10332; // 6
+static const uint64_t SH_FLD_INT_RETURN_STATE = 10333; // 6
+static const uint64_t SH_FLD_INT_RETURN_STATE_LEN = 10334; // 6
+static const uint64_t SH_FLD_INT_RX_FSM = 10335; // 43
+static const uint64_t SH_FLD_INT_STATE_ERR = 10336; // 1
+static const uint64_t SH_FLD_INT_TX_FSM = 10337; // 43
+static const uint64_t SH_FLD_INT_TYPE = 10338; // 43
+static const uint64_t SH_FLD_INVALIDATE_ADDRESS = 10339; // 1
+static const uint64_t SH_FLD_INVALIDATE_ADDRESS_LEN = 10340; // 1
+static const uint64_t SH_FLD_INVALIDATE_ALL = 10341; // 1
+static const uint64_t SH_FLD_INVALIDATE_ONE = 10342; // 1
+static const uint64_t SH_FLD_INVALIDATE_PE_NUMBER = 10343; // 1
+static const uint64_t SH_FLD_INVALIDATE_PE_NUMBER_LEN = 10344; // 1
+static const uint64_t SH_FLD_INVALID_ADDRESS = 10345; // 12
+static const uint64_t SH_FLD_INVALID_ADDRESS_ALIGNMENT = 10346; // 4
+static const uint64_t SH_FLD_INVALID_ADDRESS_MASK = 10347; // 8
+static const uint64_t SH_FLD_INVALID_CMD_0 = 10348; // 4
+static const uint64_t SH_FLD_INVALID_CMD_1 = 10349; // 2
+static const uint64_t SH_FLD_INVALID_CMD_2 = 10350; // 2
+static const uint64_t SH_FLD_INVALID_CMD_3 = 10351; // 2
+static const uint64_t SH_FLD_INVALID_COMMAND = 10352; // 4
+static const uint64_t SH_FLD_INVALID_CRESP = 10353; // 4
+static const uint64_t SH_FLD_INVALID_CRESP_ERR = 10354; // 1
+static const uint64_t SH_FLD_INVALID_CRESP_ERROR = 10355; // 2
+static const uint64_t SH_FLD_INVALID_MAINT_ADDRESS = 10356; // 4
+static const uint64_t SH_FLD_INVALID_MAINT_ADDRESS_LEN = 10357; // 2
+static const uint64_t SH_FLD_INVALID_REQTYPE = 10358; // 16
+static const uint64_t SH_FLD_INVALID_REQTYPE_ERR_MASK = 10359; // 8
+static const uint64_t SH_FLD_INVALID_REQTYPE_LEN = 10360; // 8
+static const uint64_t SH_FLD_INVALID_REQ_SOURCE = 10361; // 8
+static const uint64_t SH_FLD_INVALID_REQ_SOURCE_LEN = 10362; // 8
+static const uint64_t SH_FLD_INVALID_STATE_RECOV = 10363; // 1
+static const uint64_t SH_FLD_INVALID_STATE_UNRECOV = 10364; // 1
+static const uint64_t SH_FLD_INVALID_TRANSFER_SIZE = 10365; // 4
+static const uint64_t SH_FLD_INVALID_TTYPE = 10366; // 4
+static const uint64_t SH_FLD_INVAL_IODA_TBL_SEL_ESR = 10367; // 1
+static const uint64_t SH_FLD_INVERTED_VDM_DATA = 10368; // 6
+static const uint64_t SH_FLD_INVERTED_VDM_DATA_LEN = 10369; // 6
+static const uint64_t SH_FLD_INVLD_CMD_ERR = 10370; // 1
+static const uint64_t SH_FLD_INVLD_PRGM_ERR = 10371; // 1
+static const uint64_t SH_FLD_INV_PROT_ERR_CHK_DIS = 10372; // 1
+static const uint64_t SH_FLD_INV_SH_ERROR_RATE = 10373; // 2
+static const uint64_t SH_FLD_INV_SH_ERROR_RATE_LEN = 10374; // 2
+static const uint64_t SH_FLD_INV_SINGLE_THREAD_EN = 10375; // 1
+static const uint64_t SH_FLD_INV_SM_CTL_ERR_DET = 10376; // 1
+static const uint64_t SH_FLD_INV_TIMEOUT_CHK_DIS = 10377; // 1
+static const uint64_t SH_FLD_INV_TIMEOUT_ERR_DET = 10378; // 1
+static const uint64_t SH_FLD_IN_BAD_OP_ERR = 10379; // 2
+static const uint64_t SH_FLD_IN_CERR_BIT10 = 10380; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT11 = 10381; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT12 = 10382; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT13 = 10383; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT14 = 10384; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT15 = 10385; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT16 = 10386; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT17 = 10387; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT18 = 10388; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT19 = 10389; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT20 = 10390; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT21 = 10391; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT22 = 10392; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT23 = 10393; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT24 = 10394; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT25 = 10395; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT26 = 10396; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT27 = 10397; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT28 = 10398; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT29 = 10399; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT30 = 10400; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT31 = 10401; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT4 = 10402; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT5 = 10403; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT6 = 10404; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT7 = 10405; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT8 = 10406; // 1
+static const uint64_t SH_FLD_IN_CERR_BIT9 = 10407; // 1
+static const uint64_t SH_FLD_IN_CERR_RESET = 10408; // 1
+static const uint64_t SH_FLD_IN_COUNT1 = 10409; // 1
+static const uint64_t SH_FLD_IN_COUNT1_LEN = 10410; // 1
+static const uint64_t SH_FLD_IN_COUNT2 = 10411; // 1
+static const uint64_t SH_FLD_IN_COUNT2_LEN = 10412; // 1
+static const uint64_t SH_FLD_IN_DELAY1 = 10413; // 1
+static const uint64_t SH_FLD_IN_DELAY1_LEN = 10414; // 1
+static const uint64_t SH_FLD_IN_DELAY2 = 10415; // 1
+static const uint64_t SH_FLD_IN_DELAY2_LEN = 10416; // 1
+static const uint64_t SH_FLD_IN_ECC_CE_ERROR = 10417; // 2
+static const uint64_t SH_FLD_IN_ECC_SUE_ERROR = 10418; // 2
+static const uint64_t SH_FLD_IN_ECC_UE_ERROR = 10419; // 2
+static const uint64_t SH_FLD_IN_LEN = 10420; // 264
+static const uint64_t SH_FLD_IN_LOGIC_HW_ERROR = 10421; // 2
+static const uint64_t SH_FLD_IN_MASTER_MODE = 10422; // 43
+static const uint64_t SH_FLD_IN_PARITY_ERROR = 10423; // 2
+static const uint64_t SH_FLD_IN_PROG = 10424; // 1
+static const uint64_t SH_FLD_IN_PROG_LEN = 10425; // 1
+static const uint64_t SH_FLD_IN_SEQ_ERR = 10426; // 2
+static const uint64_t SH_FLD_IN_SEQ_PERR = 10427; // 2
+static const uint64_t SH_FLD_IN_SLAVE_MODE = 10428; // 43
+static const uint64_t SH_FLD_IN_SNP_ADDR_PERR = 10429; // 2
+static const uint64_t SH_FLD_IN_SNP_TTAG_PERR = 10430; // 2
+static const uint64_t SH_FLD_IN_SW_CAST_ERROR = 10431; // 2
+static const uint64_t SH_FLD_IN_TIMEOUT = 10432; // 2
+static const uint64_t SH_FLD_IN_TRACE_GROUP_SEL_HI = 10433; // 1
+static const uint64_t SH_FLD_IN_TRACE_GROUP_SEL_HI_LEN = 10434; // 1
+static const uint64_t SH_FLD_IN_TRACE_GROUP_SEL_LO = 10435; // 1
+static const uint64_t SH_FLD_IN_TRACE_GROUP_SEL_LO_LEN = 10436; // 1
+static const uint64_t SH_FLD_IN_TRACE_INT_DATA_HI = 10437; // 1
+static const uint64_t SH_FLD_IN_TRACE_INT_DATA_LO = 10438; // 1
+static const uint64_t SH_FLD_IN_TRACE_INT_TRIG_01 = 10439; // 1
+static const uint64_t SH_FLD_IN_TRACE_INT_TRIG_23 = 10440; // 1
+static const uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_01 = 10441; // 1
+static const uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_01_LEN = 10442; // 1
+static const uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_23 = 10443; // 1
+static const uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_23_LEN = 10444; // 1
+static const uint64_t SH_FLD_IOCLK_SLIP = 10445; // 72
+static const uint64_t SH_FLD_IOCLK_SLIP_LEN = 10446; // 72
+static const uint64_t SH_FLD_IOCLK_SLIP_STROBE = 10447; // 72
+static const uint64_t SH_FLD_IODA_ADDR_PERR_ESR = 10448; // 1
+static const uint64_t SH_FLD_IOE01_IS_LOGICAL_PAIR = 10449; // 1
+static const uint64_t SH_FLD_IOE23_IS_LOGICAL_PAIR = 10450; // 1
+static const uint64_t SH_FLD_IOE45_IS_LOGICAL_PAIR = 10451; // 1
+static const uint64_t SH_FLD_IOO01_IS_LOGICAL_PAIR = 10452; // 1
+static const uint64_t SH_FLD_IOO23_IS_LOGICAL_PAIR = 10453; // 1
+static const uint64_t SH_FLD_IOO45_IS_LOGICAL_PAIR = 10454; // 1
+static const uint64_t SH_FLD_IOO67_IS_LOGICAL_PAIR = 10455; // 1
+static const uint64_t SH_FLD_IORESET = 10456; // 107
+static const uint64_t SH_FLD_IORESET_HARD_BUS0 = 10457; // 4
+static const uint64_t SH_FLD_IOVALID = 10458; // 1
+static const uint64_t SH_FLD_IOVALID_10D = 10459; // 16
+static const uint64_t SH_FLD_IOVALID_11D = 10460; // 16
+static const uint64_t SH_FLD_IOVALID_4D = 10461; // 8
+static const uint64_t SH_FLD_IOVALID_5D = 10462; // 9
+static const uint64_t SH_FLD_IOVALID_6D = 10463; // 16
+static const uint64_t SH_FLD_IOVALID_7D = 10464; // 16
+static const uint64_t SH_FLD_IOVALID_8D = 10465; // 16
+static const uint64_t SH_FLD_IOVALID_9D = 10466; // 16
+static const uint64_t SH_FLD_IP = 10467; // 4
+static const uint64_t SH_FLD_IPB = 10468; // 1
+static const uint64_t SH_FLD_IPB_LEN = 10469; // 1
+static const uint64_t SH_FLD_IPI = 10470; // 1
+static const uint64_t SH_FLD_IPI0_HI_PRIORITY = 10471; // 1
+static const uint64_t SH_FLD_IPI0_LO_PRIORITY = 10472; // 1
+static const uint64_t SH_FLD_IPI1_HI_PRIORITY = 10473; // 1
+static const uint64_t SH_FLD_IPI1_LO_PRIORITY = 10474; // 1
+static const uint64_t SH_FLD_IPI2_HI_PRIORITY = 10475; // 1
+static const uint64_t SH_FLD_IPI2_LO_PRIORITY = 10476; // 1
+static const uint64_t SH_FLD_IPI3_HI_PRIORITY = 10477; // 1
+static const uint64_t SH_FLD_IPI3_LO_PRIORITY = 10478; // 1
+static const uint64_t SH_FLD_IPI4_HI_PRIORITY = 10479; // 1
+static const uint64_t SH_FLD_IPI4_LO_PRIORITY = 10480; // 1
+static const uint64_t SH_FLD_IPI_LEN = 10481; // 1
+static const uint64_t SH_FLD_IPI_PRIORITY = 10482; // 1
+static const uint64_t SH_FLD_IPI_PRIORITY_LEN = 10483; // 1
+static const uint64_t SH_FLD_IPI_RSD = 10484; // 1
+static const uint64_t SH_FLD_IPI_RSD_LEN = 10485; // 1
+static const uint64_t SH_FLD_IPOLL_0 = 10486; // 1
+static const uint64_t SH_FLD_IPOLL_1 = 10487; // 1
+static const uint64_t SH_FLD_IPOLL_2 = 10488; // 1
+static const uint64_t SH_FLD_IPOLL_3 = 10489; // 1
+static const uint64_t SH_FLD_IPOLL_4 = 10490; // 1
+static const uint64_t SH_FLD_IPOLL_5 = 10491; // 1
+static const uint64_t SH_FLD_IPW_SIDEAB_SEL = 10492; // 8
+static const uint64_t SH_FLD_IPW_WR_WR = 10493; // 8
+static const uint64_t SH_FLD_IPW_WR_WR_LEN = 10494; // 8
+static const uint64_t SH_FLD_IQSPD_CFG = 10495; // 4
+static const uint64_t SH_FLD_IQSPD_CFG_LEN = 10496; // 4
+static const uint64_t SH_FLD_IR = 10497; // 21
+static const uint64_t SH_FLD_IREF_BYPASS = 10498; // 2
+static const uint64_t SH_FLD_IREF_PDWN_B = 10499; // 2
+static const uint64_t SH_FLD_IREF_RES_DAC = 10500; // 2
+static const uint64_t SH_FLD_IREF_RES_DAC_LEN = 10501; // 2
+static const uint64_t SH_FLD_IRQ = 10502; // 1
+static const uint64_t SH_FLD_IRQENA = 10503; // 1
+static const uint64_t SH_FLD_IRQ_LEN = 10504; // 1
+static const uint64_t SH_FLD_IRQ_TRACE_ENABLE = 10505; // 1
+static const uint64_t SH_FLD_IR_DR_EQ0_ERR = 10506; // 1
+static const uint64_t SH_FLD_IR_LEN = 10507; // 21
+static const uint64_t SH_FLD_IS = 10508; // 8
+static const uint64_t SH_FLD_IS_ACTIVE_MASTER = 10509; // 1
+static const uint64_t SH_FLD_IS_BACKUP_MASTER = 10510; // 1
+static const uint64_t SH_FLD_IS_LEN = 10511; // 8
+static const uint64_t SH_FLD_IS_PRIMARY = 10512; // 1
+static const uint64_t SH_FLD_IS_RUNNING = 10513; // 2
+static const uint64_t SH_FLD_IS_SECONDARY = 10514; // 1
+static const uint64_t SH_FLD_IS_SLAVE = 10515; // 1
+static const uint64_t SH_FLD_IS_SPECIAL = 10516; // 1
+static const uint64_t SH_FLD_ITUNE = 10517; // 4
+static const uint64_t SH_FLD_ITUNE_LEN = 10518; // 4
+static const uint64_t SH_FLD_IVC = 10519; // 1
+static const uint64_t SH_FLD_IVC_INTF_DISABLE = 10520; // 6
+static const uint64_t SH_FLD_IVC_LEN = 10521; // 1
+static const uint64_t SH_FLD_IVE_BLOCK = 10522; // 1
+static const uint64_t SH_FLD_IVE_BLOCK_LEN = 10523; // 1
+static const uint64_t SH_FLD_IVE_INDEX = 10524; // 1
+static const uint64_t SH_FLD_IVE_INDEX_LEN = 10525; // 1
+static const uint64_t SH_FLD_IVPR = 10526; // 5
+static const uint64_t SH_FLD_IVPR_LEN = 10527; // 5
+static const uint64_t SH_FLD_IVRM_BYPASS_B = 10528; // 30
+static const uint64_t SH_FLD_IVRM_ENABLED_HISTORY = 10529; // 6
+static const uint64_t SH_FLD_IVRM_IVID = 10530; // 30
+static const uint64_t SH_FLD_IVRM_IVID_LEN = 10531; // 30
+static const uint64_t SH_FLD_IVRM_LOCAL_CONTROL = 10532; // 24
+static const uint64_t SH_FLD_IVRM_PFET_STRENGTH_CACHE = 10533; // 30
+static const uint64_t SH_FLD_IVRM_PFET_STRENGTH_CACHE_LEN = 10534; // 30
+static const uint64_t SH_FLD_IVRM_PFET_STRENGTH_CORE = 10535; // 30
+static const uint64_t SH_FLD_IVRM_PFET_STRENGTH_CORE_LEN = 10536; // 30
+static const uint64_t SH_FLD_IVRM_POWERON = 10537; // 30
+static const uint64_t SH_FLD_IVRM_PVREF_ERROR = 10538; // 1
+static const uint64_t SH_FLD_IVRM_UREG_TEST_EN = 10539; // 24
+static const uint64_t SH_FLD_IVRM_UREG_TEST_ID = 10540; // 24
+static const uint64_t SH_FLD_IVRM_UREG_TEST_ID_LEN = 10541; // 24
+static const uint64_t SH_FLD_IVRM_VID_DONE = 10542; // 30
+static const uint64_t SH_FLD_IVRM_VID_VALID = 10543; // 30
+static const uint64_t SH_FLD_IVRM_VREG_SLOW_DC = 10544; // 30
+static const uint64_t SH_FLD_I_DELAY_ADJUST_RATIO = 10545; // 1
+static const uint64_t SH_FLD_I_DELAY_ADJUST_RATIO_LEN = 10546; // 1
+static const uint64_t SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT = 10547; // 1
+static const uint64_t SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT_LEN = 10548; // 1
+static const uint64_t SH_FLD_I_PATH_DELAY_ADJUST = 10549; // 1
+static const uint64_t SH_FLD_I_PATH_DELAY_STEP_CHECK_PARITY = 10550; // 4
+static const uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD = 10551; // 1
+static const uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE = 10552; // 1
+static const uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE_LEN = 10553; // 1
+static const uint64_t SH_FLD_I_PATH_DELAY_VALUE = 10554; // 2
+static const uint64_t SH_FLD_I_PATH_DELAY_VALUE_LEN = 10555; // 2
+static const uint64_t SH_FLD_I_PATH_FSM_STATE_PARITY = 10556; // 4
+static const uint64_t SH_FLD_I_PATH_STATE = 10557; // 1
+static const uint64_t SH_FLD_I_PATH_STATE_LEN = 10558; // 1
+static const uint64_t SH_FLD_I_PATH_STEP_CHECK = 10559; // 4
+static const uint64_t SH_FLD_I_PATH_STEP_CHECK_CPS_DEVIATION_X_DISABLE = 10560; // 1
+static const uint64_t SH_FLD_I_PATH_STEP_CHECK_VALID = 10561; // 1
+static const uint64_t SH_FLD_I_PATH_SYNC_CHECK = 10562; // 4
+static const uint64_t SH_FLD_I_PATH_SYNC_CHECK_DISABLE = 10563; // 1
+static const uint64_t SH_FLD_I_PATH_TIME_OVERFLOW = 10564; // 3
+static const uint64_t SH_FLD_I_PATH_TIME_OVERFLOW_CORE_INTERRUPT = 10565; // 1
+static const uint64_t SH_FLD_I_PATH_TIME_PARITY = 10566; // 4
+static const uint64_t SH_FLD_JITTER_EPSILON = 10567; // 8
+static const uint64_t SH_FLD_JITTER_EPSILON_LEN = 10568; // 8
+static const uint64_t SH_FLD_JTAGACC_CERRPT = 10569; // 1
+static const uint64_t SH_FLD_JTAGACC_CERRPT_LEN = 10570; // 1
+static const uint64_t SH_FLD_JTAGACC_ERR = 10571; // 1
+static const uint64_t SH_FLD_JTAGACC_ERR_MASK = 10572; // 1
+static const uint64_t SH_FLD_JTAG_INPROG = 10573; // 1
+static const uint64_t SH_FLD_JTAG_INSTR = 10574; // 1
+static const uint64_t SH_FLD_JTAG_INSTR_LEN = 10575; // 1
+static const uint64_t SH_FLD_JTAG_SRC_SEL = 10576; // 1
+static const uint64_t SH_FLD_JTAG_TDI = 10577; // 1
+static const uint64_t SH_FLD_JTAG_TDI_LEN = 10578; // 1
+static const uint64_t SH_FLD_JTAG_TDO = 10579; // 1
+static const uint64_t SH_FLD_JTAG_TDO_LEN = 10580; // 1
+static const uint64_t SH_FLD_JTAG_TRST_B = 10581; // 1
+static const uint64_t SH_FLD_KEEP_MS_MODE = 10582; // 43
+static const uint64_t SH_FLD_KPRIME = 10583; // 8
+static const uint64_t SH_FLD_L = 10584; // 8
+static const uint64_t SH_FLD_L2 = 10585; // 12
+static const uint64_t SH_FLD_L2_CORE_INTF_QUIESCE_C0 = 10586; // 12
+static const uint64_t SH_FLD_L2_CORE_INTF_QUIESCE_C1 = 10587; // 12
+static const uint64_t SH_FLD_L2_EX0_CLKGLM_ASYNC_RESET = 10588; // 6
+static const uint64_t SH_FLD_L2_EX0_CLKGLM_SEL = 10589; // 6
+static const uint64_t SH_FLD_L2_EX0_CLK_SB_OVERRIDE = 10590; // 6
+static const uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE = 10591; // 6
+static const uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_EN = 10592; // 6
+static const uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_LEN = 10593; // 6
+static const uint64_t SH_FLD_L2_EX0_CLK_SB_SPARE0 = 10594; // 6
+static const uint64_t SH_FLD_L2_EX0_CLK_SB_STRENGTH = 10595; // 6
+static const uint64_t SH_FLD_L2_EX0_CLK_SB_STRENGTH_LEN = 10596; // 6
+static const uint64_t SH_FLD_L2_EX0_CLK_SW_OVERRIDE = 10597; // 6
+static const uint64_t SH_FLD_L2_EX0_CLK_SW_RESCLK = 10598; // 6
+static const uint64_t SH_FLD_L2_EX0_CLK_SW_RESCLK_LEN = 10599; // 6
+static const uint64_t SH_FLD_L2_EX0_CLK_SW_SPARE1 = 10600; // 6
+static const uint64_t SH_FLD_L2_EX0_CLK_SYNC = 10601; // 6
+static const uint64_t SH_FLD_L2_EX0_CLK_SYNC_DONE = 10602; // 6
+static const uint64_t SH_FLD_L2_EX0_CLK_SYNC_ENABLE = 10603; // 6
+static const uint64_t SH_FLD_L2_EX1_CLKGLM_ASYNC_RESET = 10604; // 6
+static const uint64_t SH_FLD_L2_EX1_CLKGLM_SEL = 10605; // 6
+static const uint64_t SH_FLD_L2_EX1_CLK_SB_OVERRIDE = 10606; // 6
+static const uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE = 10607; // 6
+static const uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_EN = 10608; // 6
+static const uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_LEN = 10609; // 6
+static const uint64_t SH_FLD_L2_EX1_CLK_SB_SPARE0 = 10610; // 6
+static const uint64_t SH_FLD_L2_EX1_CLK_SB_STRENGTH = 10611; // 6
+static const uint64_t SH_FLD_L2_EX1_CLK_SB_STRENGTH_LEN = 10612; // 6
+static const uint64_t SH_FLD_L2_EX1_CLK_SW_OVERRIDE = 10613; // 6
+static const uint64_t SH_FLD_L2_EX1_CLK_SW_RESCLK = 10614; // 6
+static const uint64_t SH_FLD_L2_EX1_CLK_SW_RESCLK_LEN = 10615; // 6
+static const uint64_t SH_FLD_L2_EX1_CLK_SW_SPARE1 = 10616; // 6
+static const uint64_t SH_FLD_L2_EX1_CLK_SYNC = 10617; // 6
+static const uint64_t SH_FLD_L2_EX1_CLK_SYNC_DONE = 10618; // 6
+static const uint64_t SH_FLD_L2_EX1_CLK_SYNC_ENABLE = 10619; // 6
+static const uint64_t SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 = 10620; // 12
+static const uint64_t SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN = 10621; // 12
+static const uint64_t SH_FLD_L2_LEN = 10622; // 12
+static const uint64_t SH_FLD_L2_PURGE = 10623; // 12
+static const uint64_t SH_FLD_L2_PURGE_ABORT = 10624; // 12
+static const uint64_t SH_FLD_L2_PURGE_DONE = 10625; // 24
+static const uint64_t SH_FLD_L2_STEP_MODE = 10626; // 12
+static const uint64_t SH_FLD_L2_STEP_MODE_LEN = 10627; // 12
+static const uint64_t SH_FLD_L2_STOPPED = 10628; // 1
+static const uint64_t SH_FLD_L2_STOPPED_LEN = 10629; // 1
+static const uint64_t SH_FLD_L3 = 10630; // 24
+static const uint64_t SH_FLD_L3CERRS_CFG_DCACHE_CAPP = 10631; // 12
+static const uint64_t SH_FLD_L3CERRS_LCO_RETRY_THROTL_DIS = 10632; // 12
+static const uint64_t SH_FLD_L3CICTL_CI_OVERRUN_CK = 10633; // 12
+static const uint64_t SH_FLD_L3CORTR_NO_LCO_TGTS = 10634; // 12
+static const uint64_t SH_FLD_L3L2CTL_PF_OVERRUN_CK = 10635; // 12
+static const uint64_t SH_FLD_L3L2CTL_RD_OVERRUN_CK = 10636; // 12
+static const uint64_t SH_FLD_L3PBEXCA0_OVERFLOW = 10637; // 12
+static const uint64_t SH_FLD_L3PBEXCA0_UNDERFLOW = 10638; // 12
+static const uint64_t SH_FLD_L3PBEXCA1_OVERFLOW = 10639; // 12
+static const uint64_t SH_FLD_L3PBEXCA1_UNDERFLOW = 10640; // 12
+static const uint64_t SH_FLD_L3SDRTL0_BAD_HPC = 10641; // 12
+static const uint64_t SH_FLD_L3SDRTL0_CACHE_INHIBIT = 10642; // 12
+static const uint64_t SH_FLD_L3SDRTL1_BAD_HPC = 10643; // 12
+static const uint64_t SH_FLD_L3SDRTL1_CACHE_INHIBIT = 10644; // 12
+static const uint64_t SH_FLD_L3SDRTL2_BAD_HPC = 10645; // 12
+static const uint64_t SH_FLD_L3SDRTL2_CACHE_INHIBIT = 10646; // 12
+static const uint64_t SH_FLD_L3SDRTL3_BAD_HPC = 10647; // 12
+static const uint64_t SH_FLD_L3SDRTL3_CACHE_INHIBIT = 10648; // 12
+static const uint64_t SH_FLD_L3XMEMA0_CRW_DIR_HIT = 10649; // 12
+static const uint64_t SH_FLD_L3XMEMA0_DW_DIR_HIT = 10650; // 12
+static const uint64_t SH_FLD_L3XMEMA1_CRW_DIR_HIT = 10651; // 12
+static const uint64_t SH_FLD_L3XMEMA1_DW_DIR_HIT = 10652; // 12
+static const uint64_t SH_FLD_L3_1ST_BEAT_SYNDROME = 10653; // 12
+static const uint64_t SH_FLD_L3_1ST_BEAT_SYNDROME_LEN = 10654; // 12
+static const uint64_t SH_FLD_L3_1ST_BEAT_UE = 10655; // 12
+static const uint64_t SH_FLD_L3_2ND_BEAT_SYNDROME = 10656; // 12
+static const uint64_t SH_FLD_L3_2ND_BEAT_SYNDROME_LEN = 10657; // 12
+static const uint64_t SH_FLD_L3_2ND_BEAT_UE = 10658; // 12
+static const uint64_t SH_FLD_L3_ABORT = 10659; // 12
+static const uint64_t SH_FLD_L3_ADDR_HANG_DETECTED = 10660; // 12
+static const uint64_t SH_FLD_L3_ADDR_HASH_EN_CFG = 10661; // 12
+static const uint64_t SH_FLD_L3_ALL_MEMBERS_DELETED_ERROR = 10662; // 12
+static const uint64_t SH_FLD_L3_BANK = 10663; // 12
+static const uint64_t SH_FLD_L3_BANK_LEN = 10664; // 12
+static const uint64_t SH_FLD_L3_BUSY_ERR = 10665; // 36
+static const uint64_t SH_FLD_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ = 10666; // 12
+static const uint64_t SH_FLD_L3_CAC_RD_SUE_DET = 10667; // 12
+static const uint64_t SH_FLD_L3_CAC_RD_UE_DET = 10668; // 12
+static const uint64_t SH_FLD_L3_CAC_TYPE = 10669; // 12
+static const uint64_t SH_FLD_L3_CAC_TYPE_LEN = 10670; // 12
+static const uint64_t SH_FLD_L3_CAC_WR_DATA_CE_FROM_L2 = 10671; // 12
+static const uint64_t SH_FLD_L3_CAC_WR_DATA_CE_FROM_PB = 10672; // 12
+static const uint64_t SH_FLD_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC = 10673; // 12
+static const uint64_t SH_FLD_L3_CAC_WR_DATA_SUE_FROM_PB = 10674; // 12
+static const uint64_t SH_FLD_L3_CAC_WR_DATA_UE_FROM_L2 = 10675; // 12
+static const uint64_t SH_FLD_L3_CAC_WR_DATA_UE_FROM_PB = 10676; // 12
+static const uint64_t SH_FLD_L3_CFG = 10677; // 36
+static const uint64_t SH_FLD_L3_CFG_LEN = 10678; // 12
+static const uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE = 10679; // 6
+static const uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE_EN = 10680; // 6
+static const uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE_LEN = 10681; // 6
+static const uint64_t SH_FLD_L3_CLK_SB_SPARE0 = 10682; // 6
+static const uint64_t SH_FLD_L3_CLK_SB_STRENGTH = 10683; // 6
+static const uint64_t SH_FLD_L3_CLK_SB_STRENGTH_LEN = 10684; // 6
+static const uint64_t SH_FLD_L3_COLUMN_MD_CFG = 10685; // 12
+static const uint64_t SH_FLD_L3_COLUMN_MD_CFG_LEN = 10686; // 12
+static const uint64_t SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG = 10687; // 12
+static const uint64_t SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG_LEN = 10688; // 12
+static const uint64_t SH_FLD_L3_CP_UTIL_EN_DC = 10689; // 12
+static const uint64_t SH_FLD_L3_CP_UTIL_EXT_SEL = 10690; // 12
+static const uint64_t SH_FLD_L3_CP_UTIL_EXT_SEL_LEN = 10691; // 12
+static const uint64_t SH_FLD_L3_CP_UTIL_SEL_DC = 10692; // 12
+static const uint64_t SH_FLD_L3_CP_UTIL_SEL_DC_LEN = 10693; // 12
+static const uint64_t SH_FLD_L3_DATA_POLL_PULSE_DIV = 10694; // 12
+static const uint64_t SH_FLD_L3_DATA_POLL_PULSE_DIV_LEN = 10695; // 12
+static const uint64_t SH_FLD_L3_DIR_ADDR = 10696; // 24
+static const uint64_t SH_FLD_L3_DIR_ADDR_LEN = 10697; // 24
+static const uint64_t SH_FLD_L3_DIR_RD_CE_DET = 10698; // 12
+static const uint64_t SH_FLD_L3_DIR_RD_PHANTOM_ERROR = 10699; // 12
+static const uint64_t SH_FLD_L3_DIR_RD_UE_DET = 10700; // 12
+static const uint64_t SH_FLD_L3_DIR_TYPE = 10701; // 12
+static const uint64_t SH_FLD_L3_DISABLED_CFG = 10702; // 12
+static const uint64_t SH_FLD_L3_DMAP_CI_EN_CFG = 10703; // 12
+static const uint64_t SH_FLD_L3_DRAM_ERROR = 10704; // 12
+static const uint64_t SH_FLD_L3_DRAM_POS_WORDLINE_FAIL = 10705; // 12
+static const uint64_t SH_FLD_L3_DW = 10706; // 12
+static const uint64_t SH_FLD_L3_DW_LEN = 10707; // 12
+static const uint64_t SH_FLD_L3_DYN_LCO_BLK_DIS_CFG = 10708; // 12
+static const uint64_t SH_FLD_L3_EDRAM_ENABLE0 = 10709; // 43
+static const uint64_t SH_FLD_L3_EDRAM_ENABLE1 = 10710; // 43
+static const uint64_t SH_FLD_L3_EDRAM_PGATE_ERR = 10711; // 6
+static const uint64_t SH_FLD_L3_EDRAM_SEQ_ERR = 10712; // 6
+static const uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ACTUAL = 10713; // 6
+static const uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ACTUAL_LEN = 10714; // 6
+static const uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ENCODE = 10715; // 6
+static const uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ENCODE_LEN = 10716; // 6
+static const uint64_t SH_FLD_L3_EX0_EDRAM_UNLOCKED = 10717; // 6
+static const uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ACTUAL = 10718; // 6
+static const uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ACTUAL_LEN = 10719; // 6
+static const uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ENCODE = 10720; // 6
+static const uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ENCODE_LEN = 10721; // 6
+static const uint64_t SH_FLD_L3_EX1_EDRAM_UNLOCKED = 10722; // 6
+static const uint64_t SH_FLD_L3_HANG_POLL_PULSE_DIV = 10723; // 12
+static const uint64_t SH_FLD_L3_HANG_POLL_PULSE_DIV_LEN = 10724; // 12
+static const uint64_t SH_FLD_L3_HW_CONTROL_ERR = 10725; // 12
+static const uint64_t SH_FLD_L3_LCO_ADDR_TGT_ENABLE = 10726; // 12
+static const uint64_t SH_FLD_L3_LCO_ENABLE_CFG = 10727; // 12
+static const uint64_t SH_FLD_L3_LCO_RTY_LIMIT_DISABLE = 10728; // 12
+static const uint64_t SH_FLD_L3_LCO_TARGET_GROUP = 10729; // 12
+static const uint64_t SH_FLD_L3_LCO_TARGET_ID = 10730; // 12
+static const uint64_t SH_FLD_L3_LCO_TARGET_ID_LEN = 10731; // 12
+static const uint64_t SH_FLD_L3_LCO_TARGET_VICTIMS = 10732; // 12
+static const uint64_t SH_FLD_L3_LCO_TARGET_VICTIMS_LEN = 10733; // 12
+static const uint64_t SH_FLD_L3_LEN = 10734; // 24
+static const uint64_t SH_FLD_L3_LINE_DEL_CE_DONE = 10735; // 12
+static const uint64_t SH_FLD_L3_LINE_DEL_ON_ALL_CE = 10736; // 24
+static const uint64_t SH_FLD_L3_LINE_DEL_ON_NEXT_CE = 10737; // 24
+static const uint64_t SH_FLD_L3_LRU_ERROR = 10738; // 12
+static const uint64_t SH_FLD_L3_LRU_INVAL_CNT = 10739; // 12
+static const uint64_t SH_FLD_L3_MACH_HANG_DETECTED = 10740; // 12
+static const uint64_t SH_FLD_L3_MEMBER = 10741; // 24
+static const uint64_t SH_FLD_L3_MEMBER_LEN = 10742; // 24
+static const uint64_t SH_FLD_L3_NO_ALLOCATE_ACTIVE = 10743; // 12
+static const uint64_t SH_FLD_L3_NO_ALLOCATE_EN = 10744; // 12
+static const uint64_t SH_FLD_L3_PB_MAST_RD_ACK_DEAD = 10745; // 12
+static const uint64_t SH_FLD_L3_PB_MAST_RD_ADDR_ERR = 10746; // 12
+static const uint64_t SH_FLD_L3_PB_MAST_WR_ACK_DEAD = 10747; // 12
+static const uint64_t SH_FLD_L3_PB_MAST_WR_ADDR_ERR = 10748; // 12
+static const uint64_t SH_FLD_L3_PPE_RD_CE_DET = 10749; // 12
+static const uint64_t SH_FLD_L3_PPE_RD_SUE_DET = 10750; // 12
+static const uint64_t SH_FLD_L3_PPE_RD_UE_DET = 10751; // 12
+static const uint64_t SH_FLD_L3_RA = 10752; // 12
+static const uint64_t SH_FLD_L3_RA_LEN = 10753; // 12
+static const uint64_t SH_FLD_L3_RDSN_LINEDEL_UE_EN = 10754; // 12
+static const uint64_t SH_FLD_L3_REFRESH_TIMER_ERROR = 10755; // 12
+static const uint64_t SH_FLD_L3_REQ = 10756; // 36
+static const uint64_t SH_FLD_L3_SCOM_CINJ_LCO_DIS = 10757; // 12
+static const uint64_t SH_FLD_L3_SCOM_INIT = 10758; // 12
+static const uint64_t SH_FLD_L3_SCOM_QUIESCE_CACHE = 10759; // 12
+static const uint64_t SH_FLD_L3_SCOM_QUIESCE_CACHE_LFSR = 10760; // 12
+static const uint64_t SH_FLD_L3_SCOM_QUIESCE_REFRESH = 10761; // 12
+static const uint64_t SH_FLD_L3_SINGLE_CAC = 10762; // 12
+static const uint64_t SH_FLD_L3_SINGLE_DIR = 10763; // 12
+static const uint64_t SH_FLD_L3_SINGLE_LRU = 10764; // 12
+static const uint64_t SH_FLD_L3_SNP_CACHE_INHIBIT_ERR = 10765; // 12
+static const uint64_t SH_FLD_L3_SOLID_CAC = 10766; // 12
+static const uint64_t SH_FLD_L3_SOLID_DIR = 10767; // 12
+static const uint64_t SH_FLD_L3_SOLID_LRU = 10768; // 12
+static const uint64_t SH_FLD_L3_SPARE0 = 10769; // 12
+static const uint64_t SH_FLD_L3_SPARE1 = 10770; // 12
+static const uint64_t SH_FLD_L3_SPARE2 = 10771; // 12
+static const uint64_t SH_FLD_L3_SPARE3 = 10772; // 24
+static const uint64_t SH_FLD_L3_SPARE5 = 10773; // 12
+static const uint64_t SH_FLD_L3_SPARE6 = 10774; // 12
+static const uint64_t SH_FLD_L3_SPARE7 = 10775; // 12
+static const uint64_t SH_FLD_L3_STOPPED = 10776; // 1
+static const uint64_t SH_FLD_L3_STOPPED_LEN = 10777; // 1
+static const uint64_t SH_FLD_L3_SYSMAP_SM_NOT_LG_SEL = 10778; // 12
+static const uint64_t SH_FLD_L3_TIMER_DIVIDE_MAJOR = 10779; // 12
+static const uint64_t SH_FLD_L3_TIMER_DIVIDE_MAJOR_LEN = 10780; // 12
+static const uint64_t SH_FLD_L3_TIMER_DIVIDE_MINOR = 10781; // 12
+static const uint64_t SH_FLD_L3_TIMER_DIVIDE_MINOR_LEN = 10782; // 12
+static const uint64_t SH_FLD_L3_TTYPE = 10783; // 24
+static const uint64_t SH_FLD_L3_TTYPE_LEN = 10784; // 24
+static const uint64_t SH_FLD_L3_UTIL_MON_BITS = 10785; // 12
+static const uint64_t SH_FLD_L3_UTIL_MON_BITS_LEN = 10786; // 12
+static const uint64_t SH_FLD_L3_VAL = 10787; // 12
+static const uint64_t SH_FLD_LANE00 = 10788; // 4
+static const uint64_t SH_FLD_LANE00_LEN = 10789; // 4
+static const uint64_t SH_FLD_LANE01 = 10790; // 4
+static const uint64_t SH_FLD_LANE01_LEN = 10791; // 4
+static const uint64_t SH_FLD_LANE02 = 10792; // 4
+static const uint64_t SH_FLD_LANE02_LEN = 10793; // 4
+static const uint64_t SH_FLD_LANE03 = 10794; // 4
+static const uint64_t SH_FLD_LANE03_LEN = 10795; // 4
+static const uint64_t SH_FLD_LANE04 = 10796; // 4
+static const uint64_t SH_FLD_LANE04_LEN = 10797; // 4
+static const uint64_t SH_FLD_LANE05 = 10798; // 4
+static const uint64_t SH_FLD_LANE05_LEN = 10799; // 4
+static const uint64_t SH_FLD_LANE06 = 10800; // 4
+static const uint64_t SH_FLD_LANE06_LEN = 10801; // 4
+static const uint64_t SH_FLD_LANE07 = 10802; // 4
+static const uint64_t SH_FLD_LANE07_LEN = 10803; // 4
+static const uint64_t SH_FLD_LANE08 = 10804; // 4
+static const uint64_t SH_FLD_LANE08_LEN = 10805; // 4
+static const uint64_t SH_FLD_LANE09 = 10806; // 4
+static const uint64_t SH_FLD_LANE09_LEN = 10807; // 4
+static const uint64_t SH_FLD_LANE10 = 10808; // 4
+static const uint64_t SH_FLD_LANE10_LEN = 10809; // 4
+static const uint64_t SH_FLD_LANE11 = 10810; // 4
+static const uint64_t SH_FLD_LANE11_LEN = 10811; // 4
+static const uint64_t SH_FLD_LANE_ANA_PDWN = 10812; // 120
+static const uint64_t SH_FLD_LANE_BAD_VEC_0_15 = 10813; // 4
+static const uint64_t SH_FLD_LANE_BAD_VEC_0_15_LEN = 10814; // 4
+static const uint64_t SH_FLD_LANE_BAD_VEC_16_23 = 10815; // 4
+static const uint64_t SH_FLD_LANE_BAD_VEC_16_23_LEN = 10816; // 4
+static const uint64_t SH_FLD_LANE_BIST_ACTVITY_DET = 10817; // 116
+static const uint64_t SH_FLD_LANE_BIST_ERR = 10818; // 116
+static const uint64_t SH_FLD_LANE_DIG_PDWN = 10819; // 120
+static const uint64_t SH_FLD_LANE_DISABLED = 10820; // 48
+static const uint64_t SH_FLD_LANE_DISABLED_VEC_0_15 = 10821; // 8
+static const uint64_t SH_FLD_LANE_DISABLED_VEC_0_15_LEN = 10822; // 8
+static const uint64_t SH_FLD_LANE_DISABLED_VEC_16_23 = 10823; // 8
+static const uint64_t SH_FLD_LANE_DISABLED_VEC_16_23_LEN = 10824; // 8
+static const uint64_t SH_FLD_LANE_INVALID = 10825; // 72
+static const uint64_t SH_FLD_LANE_INVERT = 10826; // 190
+static const uint64_t SH_FLD_LANE_PDWN = 10827; // 116
+static const uint64_t SH_FLD_LANE_QUIESCE = 10828; // 117
+static const uint64_t SH_FLD_LANE_QUIESCE_LEN = 10829; // 117
+static const uint64_t SH_FLD_LANE_SCRAMBLE_DISABLE = 10830; // 140
+static const uint64_t SH_FLD_LARGER_DROOP_EVENT_CTR = 10831; // 12
+static const uint64_t SH_FLD_LARGER_DROOP_EVENT_CTR_LEN = 10832; // 12
+static const uint64_t SH_FLD_LARGE_EVENT_PROFILE_CTR = 10833; // 12
+static const uint64_t SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN = 10834; // 12
+static const uint64_t SH_FLD_LARGE_EVENT_THRESHOLD = 10835; // 12
+static const uint64_t SH_FLD_LARGE_EVENT_THRESHOLD_LEN = 10836; // 12
+static const uint64_t SH_FLD_LAST_BANK = 10837; // 90
+static const uint64_t SH_FLD_LAST_BANK_LEN = 10838; // 90
+static const uint64_t SH_FLD_LAST_BANK_VALID = 10839; // 90
+static const uint64_t SH_FLD_LAST_OPCG_MODE = 10840; // 43
+static const uint64_t SH_FLD_LAST_OPCG_MODE_LEN = 10841; // 43
+static const uint64_t SH_FLD_LATCANCEL = 10842; // 15
+static const uint64_t SH_FLD_LATCANCEL_LEN = 10843; // 15
+static const uint64_t SH_FLD_LATENCY = 10844; // 6
+static const uint64_t SH_FLD_LATENCY_LEN = 10845; // 6
+static const uint64_t SH_FLD_LATE_LAUNCH_PRIMARY = 10846; // 1
+static const uint64_t SH_FLD_LATE_LAUNCH_SECONDARY = 10847; // 1
+static const uint64_t SH_FLD_LATFINISH = 10848; // 15
+static const uint64_t SH_FLD_LATFINISH_LEN = 10849; // 15
+static const uint64_t SH_FLD_LATSTART = 10850; // 15
+static const uint64_t SH_FLD_LATSTART_LEN = 10851; // 15
+static const uint64_t SH_FLD_LAT_THRESHA = 10852; // 8
+static const uint64_t SH_FLD_LAT_THRESHA_LEN = 10853; // 8
+static const uint64_t SH_FLD_LAT_THRESHB = 10854; // 8
+static const uint64_t SH_FLD_LAT_THRESHB_LEN = 10855; // 8
+static const uint64_t SH_FLD_LAT_THRESHC = 10856; // 8
+static const uint64_t SH_FLD_LAT_THRESHC_LEN = 10857; // 8
+static const uint64_t SH_FLD_LBIST = 10858; // 43
+static const uint64_t SH_FLD_LBIST_SKITTER_CTL = 10859; // 43
+static const uint64_t SH_FLD_LBIST_SKITTER_CTL_LEN = 10860; // 43
+static const uint64_t SH_FLD_LBUS_CLOCK_DIVIDER = 10861; // 2
+static const uint64_t SH_FLD_LBUS_CLOCK_DIVIDER_LEN = 10862; // 2
+static const uint64_t SH_FLD_LBUS_PARITY_ERR1_0 = 10863; // 12
+static const uint64_t SH_FLD_LBUS_PARITY_ERR1_1 = 10864; // 12
+static const uint64_t SH_FLD_LBUS_PARITY_ERR1_2 = 10865; // 12
+static const uint64_t SH_FLD_LBUS_PARITY_ERR1_3 = 10866; // 12
+static const uint64_t SH_FLD_LBUS_PARITY_ERROR_0 = 10867; // 4
+static const uint64_t SH_FLD_LBUS_PARITY_ERROR_1 = 10868; // 2
+static const uint64_t SH_FLD_LBUS_PARITY_ERROR_2 = 10869; // 2
+static const uint64_t SH_FLD_LBUS_PARITY_ERROR_3 = 10870; // 2
+static const uint64_t SH_FLD_LCK_STATUS_PARITY_ERROR = 10871; // 3
+static const uint64_t SH_FLD_LCL_FIRST_GRPSCAN_ENA = 10872; // 1
+static const uint64_t SH_FLD_LCL_FIRST_GRPSCAN_RMT_ENA = 10873; // 1
+static const uint64_t SH_FLD_LCO_CRED_MASK = 10874; // 1
+static const uint64_t SH_FLD_LCO_CRED_MASK_LEN = 10875; // 1
+static const uint64_t SH_FLD_LCO_TARG_CONFIG = 10876; // 1
+static const uint64_t SH_FLD_LCO_TARG_CONFIG_LEN = 10877; // 1
+static const uint64_t SH_FLD_LCO_TARG_MIN = 10878; // 1
+static const uint64_t SH_FLD_LCO_TARG_MIN_LEN = 10879; // 1
+static const uint64_t SH_FLD_LD = 10880; // 96
+static const uint64_t SH_FLD_LDQ_DATA_HANG = 10881; // 1
+static const uint64_t SH_FLD_LDQ_EQD_MAX_0_4 = 10882; // 1
+static const uint64_t SH_FLD_LDQ_EQD_MAX_0_4_LEN = 10883; // 1
+static const uint64_t SH_FLD_LDQ_EQD_MIN_0_4 = 10884; // 1
+static const uint64_t SH_FLD_LDQ_EQD_MIN_0_4_LEN = 10885; // 1
+static const uint64_t SH_FLD_LDQ_FSM_PERR = 10886; // 1
+static const uint64_t SH_FLD_LDQ_IVE_MAX_0_4 = 10887; // 1
+static const uint64_t SH_FLD_LDQ_IVE_MAX_0_4_LEN = 10888; // 1
+static const uint64_t SH_FLD_LDQ_IVE_MIN_0_4 = 10889; // 1
+static const uint64_t SH_FLD_LDQ_IVE_MIN_0_4_LEN = 10890; // 1
+static const uint64_t SH_FLD_LDQ_REG_MAX_0_4 = 10891; // 1
+static const uint64_t SH_FLD_LDQ_REG_MAX_0_4_LEN = 10892; // 1
+static const uint64_t SH_FLD_LDQ_REG_MIN_0_4 = 10893; // 1
+static const uint64_t SH_FLD_LDQ_REG_MIN_0_4_LEN = 10894; // 1
+static const uint64_t SH_FLD_LDQ_REG_ORDER_ALL = 10895; // 1
+static const uint64_t SH_FLD_LDQ_THR_MAX_0_4 = 10896; // 1
+static const uint64_t SH_FLD_LDQ_THR_MAX_0_4_LEN = 10897; // 1
+static const uint64_t SH_FLD_LDQ_THR_MIN_0_4 = 10898; // 1
+static const uint64_t SH_FLD_LDQ_THR_MIN_0_4_LEN = 10899; // 1
+static const uint64_t SH_FLD_LDQ_VPC_MAX_0_4 = 10900; // 1
+static const uint64_t SH_FLD_LDQ_VPC_MAX_0_4_LEN = 10901; // 1
+static const uint64_t SH_FLD_LDQ_VPC_MIN_0_4 = 10902; // 1
+static const uint64_t SH_FLD_LDQ_VPC_MIN_0_4_LEN = 10903; // 1
+static const uint64_t SH_FLD_LD_ACK_DEAD = 10904; // 12
+static const uint64_t SH_FLD_LD_ADDR_ERR = 10905; // 12
+static const uint64_t SH_FLD_LD_CLASS_CMD_ADDR_ERR = 10906; // 4
+static const uint64_t SH_FLD_LD_CLASS_CMD_FOREIGN_LINK_FAIL = 10907; // 4
+static const uint64_t SH_FLD_LD_ECC_CE = 10908; // 1
+static const uint64_t SH_FLD_LD_ECC_UE = 10909; // 1
+static const uint64_t SH_FLD_LD_UNLD_DLY = 10910; // 1
+static const uint64_t SH_FLD_LD_UNLD_DLY_LEN = 10911; // 1
+static const uint64_t SH_FLD_LENGTH_IN_BYTES_0 = 10912; // 2
+static const uint64_t SH_FLD_LENGTH_IN_BYTES_0_LEN = 10913; // 2
+static const uint64_t SH_FLD_LENGTH_IN_BYTES_1 = 10914; // 1
+static const uint64_t SH_FLD_LENGTH_IN_BYTES_1_LEN = 10915; // 1
+static const uint64_t SH_FLD_LENGTH_IN_BYTES_2 = 10916; // 1
+static const uint64_t SH_FLD_LENGTH_IN_BYTES_2_LEN = 10917; // 1
+static const uint64_t SH_FLD_LENGTH_IN_BYTES_3 = 10918; // 1
+static const uint64_t SH_FLD_LENGTH_IN_BYTES_3_LEN = 10919; // 1
+static const uint64_t SH_FLD_LEVEL_TRANSITION_RATE_A_N = 10920; // 96
+static const uint64_t SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN = 10921; // 96
+static const uint64_t SH_FLD_LFIR_IN = 10922; // 43
+static const uint64_t SH_FLD_LFIR_IN_LEN = 10923; // 43
+static const uint64_t SH_FLD_LFIR_RECOV_ERR = 10924; // 43
+static const uint64_t SH_FLD_LFREQ = 10925; // 1
+static const uint64_t SH_FLD_LFREQ0 = 10926; // 24
+static const uint64_t SH_FLD_LFREQ0_LEN = 10927; // 24
+static const uint64_t SH_FLD_LFREQ1 = 10928; // 24
+static const uint64_t SH_FLD_LFREQ1_LEN = 10929; // 24
+static const uint64_t SH_FLD_LFREQ_LEN = 10930; // 1
+static const uint64_t SH_FLD_LFSR = 10931; // 5
+static const uint64_t SH_FLD_LFSR_ARB_MODE = 10932; // 3
+static const uint64_t SH_FLD_LFSR_DIS = 10933; // 1
+static const uint64_t SH_FLD_LFSR_FAIRNESS_MASK = 10934; // 1
+static const uint64_t SH_FLD_LFSR_FAIRNESS_MASK_LEN = 10935; // 1
+static const uint64_t SH_FLD_LFSR_LEN = 10936; // 5
+static const uint64_t SH_FLD_LIMIT = 10937; // 2
+static const uint64_t SH_FLD_LIMIT_LEN = 10938; // 2
+static const uint64_t SH_FLD_LIM_PS = 10939; // 1
+static const uint64_t SH_FLD_LINEAR_WINDOW_BAR = 10940; // 4
+static const uint64_t SH_FLD_LINEAR_WINDOW_BAR_LEN = 10941; // 4
+static const uint64_t SH_FLD_LINEAR_WINDOW_BASE = 10942; // 4
+static const uint64_t SH_FLD_LINEAR_WINDOW_BASE_LEN = 10943; // 4
+static const uint64_t SH_FLD_LINEAR_WINDOW_ENABLE = 10944; // 4
+static const uint64_t SH_FLD_LINEAR_WINDOW_MASK = 10945; // 4
+static const uint64_t SH_FLD_LINEAR_WINDOW_MASK_LEN = 10946; // 4
+static const uint64_t SH_FLD_LINEAR_WINDOW_REGION = 10947; // 4
+static const uint64_t SH_FLD_LINEAR_WINDOW_REGION_LEN = 10948; // 4
+static const uint64_t SH_FLD_LINEAR_WINDOW_SCRESP = 10949; // 4
+static const uint64_t SH_FLD_LINEAR_WINDOW_SCRESP_LEN = 10950; // 4
+static const uint64_t SH_FLD_LINK00_HI = 10951; // 2
+static const uint64_t SH_FLD_LINK00_HI_LEN = 10952; // 2
+static const uint64_t SH_FLD_LINK00_LO = 10953; // 2
+static const uint64_t SH_FLD_LINK00_LO_LEN = 10954; // 2
+static const uint64_t SH_FLD_LINK01_CAPP_MODE = 10955; // 1
+static const uint64_t SH_FLD_LINK01_DIB_VC_LIMIT = 10956; // 2
+static const uint64_t SH_FLD_LINK01_DIB_VC_LIMIT_LEN = 10957; // 2
+static const uint64_t SH_FLD_LINK01_HI = 10958; // 2
+static const uint64_t SH_FLD_LINK01_HI_LEN = 10959; // 2
+static const uint64_t SH_FLD_LINK01_HRB_INIT_STATE = 10960; // 1
+static const uint64_t SH_FLD_LINK01_LO = 10961; // 2
+static const uint64_t SH_FLD_LINK01_LO_LEN = 10962; // 2
+static const uint64_t SH_FLD_LINK02_HI = 10963; // 2
+static const uint64_t SH_FLD_LINK02_HI_LEN = 10964; // 2
+static const uint64_t SH_FLD_LINK02_LO = 10965; // 2
+static const uint64_t SH_FLD_LINK02_LO_LEN = 10966; // 2
+static const uint64_t SH_FLD_LINK03_HI = 10967; // 2
+static const uint64_t SH_FLD_LINK03_HI_LEN = 10968; // 2
+static const uint64_t SH_FLD_LINK03_LO = 10969; // 2
+static const uint64_t SH_FLD_LINK03_LO_LEN = 10970; // 2
+static const uint64_t SH_FLD_LINK04_HI = 10971; // 2
+static const uint64_t SH_FLD_LINK04_HI_LEN = 10972; // 2
+static const uint64_t SH_FLD_LINK04_LO = 10973; // 2
+static const uint64_t SH_FLD_LINK04_LO_LEN = 10974; // 2
+static const uint64_t SH_FLD_LINK05_HI = 10975; // 2
+static const uint64_t SH_FLD_LINK05_HI_LEN = 10976; // 2
+static const uint64_t SH_FLD_LINK05_LO = 10977; // 2
+static const uint64_t SH_FLD_LINK05_LO_LEN = 10978; // 2
+static const uint64_t SH_FLD_LINK06_HI = 10979; // 1
+static const uint64_t SH_FLD_LINK06_HI_LEN = 10980; // 1
+static const uint64_t SH_FLD_LINK06_LO = 10981; // 1
+static const uint64_t SH_FLD_LINK06_LO_LEN = 10982; // 1
+static const uint64_t SH_FLD_LINK07_HI = 10983; // 1
+static const uint64_t SH_FLD_LINK07_HI_LEN = 10984; // 1
+static const uint64_t SH_FLD_LINK07_LO = 10985; // 1
+static const uint64_t SH_FLD_LINK07_LO_LEN = 10986; // 1
+static const uint64_t SH_FLD_LINK0_ACK_QUEUE_OVERFLOW = 10987; // 4
+static const uint64_t SH_FLD_LINK0_ACK_QUEUE_UNDERFLOW = 10988; // 4
+static const uint64_t SH_FLD_LINK0_COMMAND = 10989; // 5
+static const uint64_t SH_FLD_LINK0_COMMAND_LEN = 10990; // 5
+static const uint64_t SH_FLD_LINK0_CORRECTABLE_ARRAY_ERROR = 10991; // 10
+static const uint64_t SH_FLD_LINK0_CRC_ERROR = 10992; // 10
+static const uint64_t SH_FLD_LINK0_CURRENT_STATE = 10993; // 5
+static const uint64_t SH_FLD_LINK0_CURRENT_STATE_LEN = 10994; // 5
+static const uint64_t SH_FLD_LINK0_DESKEW_ERROR = 10995; // 4
+static const uint64_t SH_FLD_LINK0_DESKEW_OVERFLOW = 10996; // 4
+static const uint64_t SH_FLD_LINK0_DOB_LIMIT = 10997; // 1
+static const uint64_t SH_FLD_LINK0_DOB_LIMIT_LEN = 10998; // 1
+static const uint64_t SH_FLD_LINK0_DOB_VC0_LIMIT = 10999; // 2
+static const uint64_t SH_FLD_LINK0_DOB_VC0_LIMIT_LEN = 11000; // 2
+static const uint64_t SH_FLD_LINK0_DOB_VC1_LIMIT = 11001; // 2
+static const uint64_t SH_FLD_LINK0_DOB_VC1_LIMIT_LEN = 11002; // 2
+static const uint64_t SH_FLD_LINK0_ELEVEN_LANE_SHIFT = 11003; // 2
+static const uint64_t SH_FLD_LINK0_ERR_INJ_COMMAND = 11004; // 5
+static const uint64_t SH_FLD_LINK0_ERR_INJ_COMMAND_LANES = 11005; // 5
+static const uint64_t SH_FLD_LINK0_ERR_INJ_COMMAND_LANES_LEN = 11006; // 5
+static const uint64_t SH_FLD_LINK0_ERR_INJ_COMMAND_LEN = 11007; // 5
+static const uint64_t SH_FLD_LINK0_HOLD_PATT_A = 11008; // 2
+static const uint64_t SH_FLD_LINK0_HOLD_PATT_B = 11009; // 2
+static const uint64_t SH_FLD_LINK0_IGNORE_FENCE = 11010; // 2
+static const uint64_t SH_FLD_LINK0_IGNORE_PHY = 11011; // 2
+static const uint64_t SH_FLD_LINK0_INTERNAL_ERROR = 11012; // 10
+static const uint64_t SH_FLD_LINK0_INVALID_BLOCK = 11013; // 4
+static const uint64_t SH_FLD_LINK0_LOSS_BLOCK_ALIGN = 11014; // 4
+static const uint64_t SH_FLD_LINK0_MAX_PKT_TIMER = 11015; // 5
+static const uint64_t SH_FLD_LINK0_MAX_PKT_TIMER_LEN = 11016; // 5
+static const uint64_t SH_FLD_LINK0_NAK_RECEIVED = 11017; // 10
+static const uint64_t SH_FLD_LINK0_NPU_ERROR = 11018; // 4
+static const uint64_t SH_FLD_LINK0_NUM_REPLAY = 11019; // 4
+static const uint64_t SH_FLD_LINK0_OLL_ENABLED = 11020; // 2
+static const uint64_t SH_FLD_LINK0_OPTICS_IRQ = 11021; // 2
+static const uint64_t SH_FLD_LINK0_OPTICS_RST_B = 11022; // 2
+static const uint64_t SH_FLD_LINK0_OP_IRQ = 11023; // 4
+static const uint64_t SH_FLD_LINK0_PHY_TRAINING = 11024; // 2
+static const uint64_t SH_FLD_LINK0_PRBS_SELECT_ERROR = 11025; // 4
+static const uint64_t SH_FLD_LINK0_PRIOR_STATE = 11026; // 5
+static const uint64_t SH_FLD_LINK0_PRIOR_STATE_LEN = 11027; // 5
+static const uint64_t SH_FLD_LINK0_REPLAY_BUFFER_FULL = 11028; // 10
+static const uint64_t SH_FLD_LINK0_REPLAY_THRESHOLD = 11029; // 10
+static const uint64_t SH_FLD_LINK0_RETRAIN_THRESHOLD = 11030; // 4
+static const uint64_t SH_FLD_LINK0_ROUND_TRIP = 11031; // 5
+static const uint64_t SH_FLD_LINK0_ROUND_TRIP_LEN = 11032; // 5
+static const uint64_t SH_FLD_LINK0_ROUND_TRIP_VALID = 11033; // 5
+static const uint64_t SH_FLD_LINK0_RUN_LANE_DISABLE = 11034; // 2
+static const uint64_t SH_FLD_LINK0_RUN_LANE_OVERRIDE = 11035; // 2
+static const uint64_t SH_FLD_LINK0_RX_LANE_SWAP = 11036; // 2
+static const uint64_t SH_FLD_LINK0_SL_ECC_CORRECTABLE = 11037; // 10
+static const uint64_t SH_FLD_LINK0_SL_ECC_THRESHOLD = 11038; // 10
+static const uint64_t SH_FLD_LINK0_SL_ECC_UE = 11039; // 10
+static const uint64_t SH_FLD_LINK0_SPARE = 11040; // 1
+static const uint64_t SH_FLD_LINK0_SPARE_DONE = 11041; // 10
+static const uint64_t SH_FLD_LINK0_SPARE_LEN = 11042; // 1
+static const uint64_t SH_FLD_LINK0_STARTUP = 11043; // 5
+static const uint64_t SH_FLD_LINK0_SW_RETRAIN = 11044; // 4
+static const uint64_t SH_FLD_LINK0_TCOMPLETE_BAD = 11045; // 10
+static const uint64_t SH_FLD_LINK0_TOD_LATENCY = 11046; // 5
+static const uint64_t SH_FLD_LINK0_TOD_LATENCY_LEN = 11047; // 5
+static const uint64_t SH_FLD_LINK0_TOO_MANY_CRC_ERRORS = 11048; // 10
+static const uint64_t SH_FLD_LINK0_TRAINED = 11049; // 10
+static const uint64_t SH_FLD_LINK0_TRAINING = 11050; // 2
+static const uint64_t SH_FLD_LINK0_TRAINING_FAILED = 11051; // 10
+static const uint64_t SH_FLD_LINK0_TRAINING_SET_RECEIVED = 11052; // 4
+static const uint64_t SH_FLD_LINK0_TX_LANE_SWAP = 11053; // 2
+static const uint64_t SH_FLD_LINK0_UNCORRECTABLE_ARRAY_ERROR = 11054; // 10
+static const uint64_t SH_FLD_LINK0_UNRECOVERABLE_ERROR = 11055; // 10
+static const uint64_t SH_FLD_LINK1_ACK_QUEUE_OVERFLOW = 11056; // 4
+static const uint64_t SH_FLD_LINK1_ACK_QUEUE_UNDERFLOW = 11057; // 4
+static const uint64_t SH_FLD_LINK1_COMMAND = 11058; // 5
+static const uint64_t SH_FLD_LINK1_COMMAND_LEN = 11059; // 5
+static const uint64_t SH_FLD_LINK1_CORRECTABLE_ARRAY_ERROR = 11060; // 10
+static const uint64_t SH_FLD_LINK1_CRC_ERROR = 11061; // 10
+static const uint64_t SH_FLD_LINK1_CURRENT_STATE = 11062; // 5
+static const uint64_t SH_FLD_LINK1_CURRENT_STATE_LEN = 11063; // 5
+static const uint64_t SH_FLD_LINK1_DESKEW_ERROR = 11064; // 4
+static const uint64_t SH_FLD_LINK1_DESKEW_OVERFLOW = 11065; // 4
+static const uint64_t SH_FLD_LINK1_DOB_LIMIT = 11066; // 1
+static const uint64_t SH_FLD_LINK1_DOB_LIMIT_LEN = 11067; // 1
+static const uint64_t SH_FLD_LINK1_DOB_VC0_LIMIT = 11068; // 2
+static const uint64_t SH_FLD_LINK1_DOB_VC0_LIMIT_LEN = 11069; // 2
+static const uint64_t SH_FLD_LINK1_DOB_VC1_LIMIT = 11070; // 2
+static const uint64_t SH_FLD_LINK1_DOB_VC1_LIMIT_LEN = 11071; // 2
+static const uint64_t SH_FLD_LINK1_ELEVEN_LANE_SHIFT = 11072; // 2
+static const uint64_t SH_FLD_LINK1_ERR_INJ_COMMAND = 11073; // 5
+static const uint64_t SH_FLD_LINK1_ERR_INJ_COMMAND_LANES = 11074; // 5
+static const uint64_t SH_FLD_LINK1_ERR_INJ_COMMAND_LANES_LEN = 11075; // 5
+static const uint64_t SH_FLD_LINK1_ERR_INJ_COMMAND_LEN = 11076; // 5
+static const uint64_t SH_FLD_LINK1_HOLD_PATT_A = 11077; // 2
+static const uint64_t SH_FLD_LINK1_HOLD_PATT_B = 11078; // 2
+static const uint64_t SH_FLD_LINK1_IGNORE_FENCE = 11079; // 2
+static const uint64_t SH_FLD_LINK1_IGNORE_PHY = 11080; // 2
+static const uint64_t SH_FLD_LINK1_INTERNAL_ERROR = 11081; // 10
+static const uint64_t SH_FLD_LINK1_INVALID_BLOCK = 11082; // 4
+static const uint64_t SH_FLD_LINK1_LOSS_BLOCK_ALIGN = 11083; // 4
+static const uint64_t SH_FLD_LINK1_MAX_PKT_TIMER = 11084; // 5
+static const uint64_t SH_FLD_LINK1_MAX_PKT_TIMER_LEN = 11085; // 5
+static const uint64_t SH_FLD_LINK1_NAK_RECEIVED = 11086; // 10
+static const uint64_t SH_FLD_LINK1_NPU_ERROR = 11087; // 4
+static const uint64_t SH_FLD_LINK1_NUM_REPLAY = 11088; // 4
+static const uint64_t SH_FLD_LINK1_OLL_ENABLED = 11089; // 2
+static const uint64_t SH_FLD_LINK1_OPTICS_IRQ = 11090; // 2
+static const uint64_t SH_FLD_LINK1_OPTICS_RST_B = 11091; // 2
+static const uint64_t SH_FLD_LINK1_OP_IRQ = 11092; // 4
+static const uint64_t SH_FLD_LINK1_PHY_TRAINING = 11093; // 2
+static const uint64_t SH_FLD_LINK1_PRBS_SELECT_ERROR = 11094; // 4
+static const uint64_t SH_FLD_LINK1_PRIOR_STATE = 11095; // 5
+static const uint64_t SH_FLD_LINK1_PRIOR_STATE_LEN = 11096; // 5
+static const uint64_t SH_FLD_LINK1_REPLAY_BUFFER_FULL = 11097; // 10
+static const uint64_t SH_FLD_LINK1_REPLAY_THRESHOLD = 11098; // 10
+static const uint64_t SH_FLD_LINK1_RETRAIN_THRESHOLD = 11099; // 4
+static const uint64_t SH_FLD_LINK1_ROUND_TRIP = 11100; // 5
+static const uint64_t SH_FLD_LINK1_ROUND_TRIP_LEN = 11101; // 5
+static const uint64_t SH_FLD_LINK1_ROUND_TRIP_VALID = 11102; // 5
+static const uint64_t SH_FLD_LINK1_RUN_LANE_DISABLE = 11103; // 2
+static const uint64_t SH_FLD_LINK1_RUN_LANE_OVERRIDE = 11104; // 2
+static const uint64_t SH_FLD_LINK1_RX_LANE_SWAP = 11105; // 2
+static const uint64_t SH_FLD_LINK1_SL_ECC_CORRECTABLE = 11106; // 10
+static const uint64_t SH_FLD_LINK1_SL_ECC_THRESHOLD = 11107; // 10
+static const uint64_t SH_FLD_LINK1_SL_ECC_UE = 11108; // 10
+static const uint64_t SH_FLD_LINK1_SPARE = 11109; // 1
+static const uint64_t SH_FLD_LINK1_SPARE_DONE = 11110; // 10
+static const uint64_t SH_FLD_LINK1_SPARE_LEN = 11111; // 1
+static const uint64_t SH_FLD_LINK1_STARTUP = 11112; // 5
+static const uint64_t SH_FLD_LINK1_SW_RETRAIN = 11113; // 4
+static const uint64_t SH_FLD_LINK1_TCOMPLETE_BAD = 11114; // 10
+static const uint64_t SH_FLD_LINK1_TOD_LATENCY = 11115; // 5
+static const uint64_t SH_FLD_LINK1_TOD_LATENCY_LEN = 11116; // 5
+static const uint64_t SH_FLD_LINK1_TOO_MANY_CRC_ERRORS = 11117; // 10
+static const uint64_t SH_FLD_LINK1_TRAINED = 11118; // 10
+static const uint64_t SH_FLD_LINK1_TRAINING = 11119; // 2
+static const uint64_t SH_FLD_LINK1_TRAINING_FAILED = 11120; // 10
+static const uint64_t SH_FLD_LINK1_TRAINING_SET_RECEIVED = 11121; // 4
+static const uint64_t SH_FLD_LINK1_TX_LANE_SWAP = 11122; // 2
+static const uint64_t SH_FLD_LINK1_UNCORRECTABLE_ARRAY_ERROR = 11123; // 10
+static const uint64_t SH_FLD_LINK1_UNRECOVERABLE_ERROR = 11124; // 10
+static const uint64_t SH_FLD_LINK23_DIB_VC_LIMIT = 11125; // 2
+static const uint64_t SH_FLD_LINK23_DIB_VC_LIMIT_LEN = 11126; // 2
+static const uint64_t SH_FLD_LINK2_DOB_LIMIT = 11127; // 2
+static const uint64_t SH_FLD_LINK2_DOB_LIMIT_LEN = 11128; // 2
+static const uint64_t SH_FLD_LINK2_DOB_VC0_LIMIT = 11129; // 2
+static const uint64_t SH_FLD_LINK2_DOB_VC0_LIMIT_LEN = 11130; // 2
+static const uint64_t SH_FLD_LINK2_DOB_VC1_LIMIT = 11131; // 2
+static const uint64_t SH_FLD_LINK2_DOB_VC1_LIMIT_LEN = 11132; // 2
+static const uint64_t SH_FLD_LINK3_DOB_LIMIT = 11133; // 2
+static const uint64_t SH_FLD_LINK3_DOB_LIMIT_LEN = 11134; // 2
+static const uint64_t SH_FLD_LINK3_DOB_VC0_LIMIT = 11135; // 2
+static const uint64_t SH_FLD_LINK3_DOB_VC0_LIMIT_LEN = 11136; // 2
+static const uint64_t SH_FLD_LINK3_DOB_VC1_LIMIT = 11137; // 2
+static const uint64_t SH_FLD_LINK3_DOB_VC1_LIMIT_LEN = 11138; // 2
+static const uint64_t SH_FLD_LINK45_DIB_VC_LIMIT = 11139; // 2
+static const uint64_t SH_FLD_LINK45_DIB_VC_LIMIT_LEN = 11140; // 2
+static const uint64_t SH_FLD_LINK4_DOB_LIMIT = 11141; // 2
+static const uint64_t SH_FLD_LINK4_DOB_LIMIT_LEN = 11142; // 2
+static const uint64_t SH_FLD_LINK4_DOB_VC0_LIMIT = 11143; // 2
+static const uint64_t SH_FLD_LINK4_DOB_VC0_LIMIT_LEN = 11144; // 2
+static const uint64_t SH_FLD_LINK4_DOB_VC1_LIMIT = 11145; // 2
+static const uint64_t SH_FLD_LINK4_DOB_VC1_LIMIT_LEN = 11146; // 2
+static const uint64_t SH_FLD_LINK5_DOB_LIMIT = 11147; // 2
+static const uint64_t SH_FLD_LINK5_DOB_LIMIT_LEN = 11148; // 2
+static const uint64_t SH_FLD_LINK5_DOB_VC0_LIMIT = 11149; // 2
+static const uint64_t SH_FLD_LINK5_DOB_VC0_LIMIT_LEN = 11150; // 2
+static const uint64_t SH_FLD_LINK5_DOB_VC1_LIMIT = 11151; // 2
+static const uint64_t SH_FLD_LINK5_DOB_VC1_LIMIT_LEN = 11152; // 2
+static const uint64_t SH_FLD_LINK67_CAPP_MODE = 11153; // 1
+static const uint64_t SH_FLD_LINK67_DIB_VC_LIMIT = 11154; // 1
+static const uint64_t SH_FLD_LINK67_DIB_VC_LIMIT_LEN = 11155; // 1
+static const uint64_t SH_FLD_LINK67_HRB_INIT_STATE = 11156; // 1
+static const uint64_t SH_FLD_LINK6_DOB_VC0_LIMIT = 11157; // 1
+static const uint64_t SH_FLD_LINK6_DOB_VC0_LIMIT_LEN = 11158; // 1
+static const uint64_t SH_FLD_LINK6_DOB_VC1_LIMIT = 11159; // 1
+static const uint64_t SH_FLD_LINK6_DOB_VC1_LIMIT_LEN = 11160; // 1
+static const uint64_t SH_FLD_LINK6_SPARE = 11161; // 1
+static const uint64_t SH_FLD_LINK6_SPARE_LEN = 11162; // 1
+static const uint64_t SH_FLD_LINK7_DOB_VC0_LIMIT = 11163; // 1
+static const uint64_t SH_FLD_LINK7_DOB_VC0_LIMIT_LEN = 11164; // 1
+static const uint64_t SH_FLD_LINK7_DOB_VC1_LIMIT = 11165; // 1
+static const uint64_t SH_FLD_LINK7_DOB_VC1_LIMIT_LEN = 11166; // 1
+static const uint64_t SH_FLD_LINK7_SPARE = 11167; // 1
+static const uint64_t SH_FLD_LINK7_SPARE_LEN = 11168; // 1
+static const uint64_t SH_FLD_LINKS01_TOD_ENABLE = 11169; // 1
+static const uint64_t SH_FLD_LINKS23_TOD_ENABLE = 11170; // 1
+static const uint64_t SH_FLD_LINKS45_TOD_ENABLE = 11171; // 1
+static const uint64_t SH_FLD_LINKS67_TOD_ENABLE = 11172; // 1
+static const uint64_t SH_FLD_LINKX_NPU_ERROR = 11173; // 4
+static const uint64_t SH_FLD_LINK_AVP_MODE = 11174; // 2
+static const uint64_t SH_FLD_LINK_CAP_CRC = 11175; // 10
+static const uint64_t SH_FLD_LINK_CAP_CRC_LANE = 11176; // 10
+static const uint64_t SH_FLD_LINK_CAP_CRC_LANE_LEN = 11177; // 10
+static const uint64_t SH_FLD_LINK_CAP_CRC_LEN = 11178; // 10
+static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED1 = 11179; // 6
+static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED1_LEN = 11180; // 6
+static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED2 = 11181; // 6
+static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED2_LEN = 11182; // 6
+static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED3 = 11183; // 6
+static const uint64_t SH_FLD_LINK_CAP_CRC_UNUSED3_LEN = 11184; // 6
+static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN0 = 11185; // 10
+static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN0_LEN = 11186; // 10
+static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN1 = 11187; // 10
+static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN1_LEN = 11188; // 10
+static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN2 = 11189; // 4
+static const uint64_t SH_FLD_LINK_CAP_SLECC_SYN2_LEN = 11190; // 4
+static const uint64_t SH_FLD_LINK_CAP_VALID = 11191; // 6
+static const uint64_t SH_FLD_LINK_FAIL_DURATION = 11192; // 2
+static const uint64_t SH_FLD_LINK_FAIL_DURATION_LEN = 11193; // 2
+static const uint64_t SH_FLD_LINK_FAIL_MAX = 11194; // 2
+static const uint64_t SH_FLD_LINK_FAIL_MAX_LEN = 11195; // 2
+static const uint64_t SH_FLD_LINK_PAIR = 11196; // 5
+static const uint64_t SH_FLD_LINUX_TRIG_MODE = 11197; // 1
+static const uint64_t SH_FLD_LISTEN_TO_PULSE_DIS = 11198; // 43
+static const uint64_t SH_FLD_LNK_RSP_PKT_DISCARDED_ERRHOLD = 11199; // 2
+static const uint64_t SH_FLD_LO = 11200; // 1
+static const uint64_t SH_FLD_LOAD_CI_BUFF = 11201; // 2
+static const uint64_t SH_FLD_LOAD_RSVD_VALUES = 11202; // 8
+static const uint64_t SH_FLD_LOCALITY_4_ACCESS = 11203; // 1
+static const uint64_t SH_FLD_LOCAL_HANG_COMP = 11204; // 4
+static const uint64_t SH_FLD_LOCAL_HANG_COMP_LEN = 11205; // 4
+static const uint64_t SH_FLD_LOCAL_HIGH_PRIORITY = 11206; // 4
+static const uint64_t SH_FLD_LOCAL_HIGH_PRIORITY_LEN = 11207; // 4
+static const uint64_t SH_FLD_LOCAL_LATENCY_DIFFERENCE = 11208; // 5
+static const uint64_t SH_FLD_LOCAL_LATENCY_DIFFERENCE_LEN = 11209; // 5
+static const uint64_t SH_FLD_LOCAL_LATENCY_DIFFERENCE_VALID = 11210; // 5
+static const uint64_t SH_FLD_LOCAL_LATENCY_LONGER_LINK = 11211; // 5
+static const uint64_t SH_FLD_LOCAL_LOW_PRIORITY = 11212; // 4
+static const uint64_t SH_FLD_LOCAL_LOW_PRIORITY_LEN = 11213; // 4
+static const uint64_t SH_FLD_LOCAL_NODE_EPSILON = 11214; // 8
+static const uint64_t SH_FLD_LOCAL_NODE_EPSILON_LEN = 11215; // 8
+static const uint64_t SH_FLD_LOCAL_QUIESCE_ACHIEVED = 11216; // 1
+static const uint64_t SH_FLD_LOCK = 11217; // 16
+static const uint64_t SH_FLD_LOCKED = 11218; // 4
+static const uint64_t SH_FLD_LOCKED_FSM_RESET_ONGOING = 11219; // 1
+static const uint64_t SH_FLD_LOCKED_FSM_STATE = 11220; // 1
+static const uint64_t SH_FLD_LOCKED_FSM_STATE_LEN = 11221; // 1
+static const uint64_t SH_FLD_LOCKED_LEN = 11222; // 4
+static const uint64_t SH_FLD_LOCKED_PIBM_ADDR = 11223; // 1
+static const uint64_t SH_FLD_LOCKED_PIBM_ADDR_LEN = 11224; // 1
+static const uint64_t SH_FLD_LOCKED_SEEPROM_ADDRESS = 11225; // 1
+static const uint64_t SH_FLD_LOCKED_SEEPROM_ADDRESS_LEN = 11226; // 1
+static const uint64_t SH_FLD_LOCK_PCB_ON_ERR = 11227; // 12
+static const uint64_t SH_FLD_LOCK_SEL = 11228; // 6
+static const uint64_t SH_FLD_LOFF_AMP_EN = 11229; // 6
+static const uint64_t SH_FLD_LOG = 11230; // 1
+static const uint64_t SH_FLD_LOG_FULL = 11231; // 8
+static const uint64_t SH_FLD_LOG_LEN = 11232; // 1
+static const uint64_t SH_FLD_LOG_POINTER = 11233; // 8
+static const uint64_t SH_FLD_LOG_POINTER_LEN = 11234; // 8
+static const uint64_t SH_FLD_LOOP_BREAK_MODE = 11235; // 64
+static const uint64_t SH_FLD_LOOP_BREAK_MODE_LEN = 11236; // 64
+static const uint64_t SH_FLD_LOOP_COUNT = 11237; // 43
+static const uint64_t SH_FLD_LOOP_COUNT_LEN = 11238; // 43
+static const uint64_t SH_FLD_LOW = 11239; // 1
+static const uint64_t SH_FLD_LOW_IDLE_COUNT = 11240; // 8
+static const uint64_t SH_FLD_LOW_IDLE_COUNT_LEN = 11241; // 8
+static const uint64_t SH_FLD_LOW_IDLE_THRESHOLD = 11242; // 8
+static const uint64_t SH_FLD_LOW_IDLE_THRESHOLD_LEN = 11243; // 8
+static const uint64_t SH_FLD_LOW_LATENCY = 11244; // 8
+static const uint64_t SH_FLD_LOW_LEN = 11245; // 1
+static const uint64_t SH_FLD_LOW_ORDER_STEP_VALUE = 11246; // 1
+static const uint64_t SH_FLD_LOW_ORDER_STEP_VALUE_LEN = 11247; // 1
+static const uint64_t SH_FLD_LOW_PROBE_TRACE_GATE = 11248; // 8
+static const uint64_t SH_FLD_LO_ENABLE = 11249; // 2
+static const uint64_t SH_FLD_LO_FIXED_WINDOW_MODE = 11250; // 2
+static const uint64_t SH_FLD_LO_PRESCALE_MODE = 11251; // 2
+static const uint64_t SH_FLD_LO_SELECT = 11252; // 2
+static const uint64_t SH_FLD_LO_SELECT_LEN = 11253; // 2
+static const uint64_t SH_FLD_LP = 11254; // 8
+static const uint64_t SH_FLD_LPARID = 11255; // 24
+static const uint64_t SH_FLD_LPARID_LEN = 11256; // 24
+static const uint64_t SH_FLD_LPARSHORT = 11257; // 272
+static const uint64_t SH_FLD_LPARSHORT_LEN = 11258; // 272
+static const uint64_t SH_FLD_LPCR_BOT = 11259; // 16
+static const uint64_t SH_FLD_LPCR_ISL = 11260; // 16
+static const uint64_t SH_FLD_LPCR_PS = 11261; // 16
+static const uint64_t SH_FLD_LPCR_PS_LEN = 11262; // 16
+static const uint64_t SH_FLD_LPCR_SC = 11263; // 16
+static const uint64_t SH_FLD_LPCR_TC = 11264; // 16
+static const uint64_t SH_FLD_LPCTH = 11265; // 3
+static const uint64_t SH_FLD_LPCTH_LEN = 11266; // 3
+static const uint64_t SH_FLD_LPC_MODE = 11267; // 2
+static const uint64_t SH_FLD_LPC_MODE_LEN = 11268; // 2
+static const uint64_t SH_FLD_LPID = 11269; // 9
+static const uint64_t SH_FLD_LPID_LEN = 11270; // 9
+static const uint64_t SH_FLD_LPID_MASK = 11271; // 1
+static const uint64_t SH_FLD_LPID_MASK_LEN = 11272; // 1
+static const uint64_t SH_FLD_LP_CNT_THRESH = 11273; // 6
+static const uint64_t SH_FLD_LP_CNT_THRESH_LEN = 11274; // 6
+static const uint64_t SH_FLD_LP_LEN = 11275; // 8
+static const uint64_t SH_FLD_LP_MAX_CRED_THRESH = 11276; // 6
+static const uint64_t SH_FLD_LP_MAX_CRED_THRESH_LEN = 11277; // 6
+static const uint64_t SH_FLD_LP_MIN_CRED_THRESH = 11278; // 6
+static const uint64_t SH_FLD_LP_MIN_CRED_THRESH_LEN = 11279; // 6
+static const uint64_t SH_FLD_LP_MODE_ENABLE = 11280; // 6
+static const uint64_t SH_FLD_LP_ONLY_MODE = 11281; // 6
+static const uint64_t SH_FLD_LP_TIMER_TICK_CONFIG = 11282; // 6
+static const uint64_t SH_FLD_LP_TIMER_TICK_CONFIG_LEN = 11283; // 6
+static const uint64_t SH_FLD_LRDIMM = 11284; // 2
+static const uint64_t SH_FLD_LRDIMM_CONTEXT = 11285; // 8
+static const uint64_t SH_FLD_LRDIMM_LEN = 11286; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD1 = 11287; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD10 = 11288; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD10_LEN = 11289; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD11 = 11290; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD11_LEN = 11291; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD12 = 11292; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD12_LEN = 11293; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD13 = 11294; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD13_LEN = 11295; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD14 = 11296; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD14_LEN = 11297; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD15 = 11298; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD15_LEN = 11299; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD1_LEN = 11300; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD2 = 11301; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD2_LEN = 11302; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD3 = 11303; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD3_LEN = 11304; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD4 = 11305; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD4_LEN = 11306; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD5 = 11307; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD5_LEN = 11308; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD6 = 11309; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD6_LEN = 11310; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD7 = 11311; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD7_LEN = 11312; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD8 = 11313; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD8_LEN = 11314; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD9 = 11315; // 2
+static const uint64_t SH_FLD_LRDIMM_WORD9_LEN = 11316; // 2
+static const uint64_t SH_FLD_LRU_ALL_MEMBERS_IN_CGC_ARE_LINE_DELETED = 11317; // 12
+static const uint64_t SH_FLD_LRU_PERR_CHK_DIS = 11318; // 2
+static const uint64_t SH_FLD_LRU_READ_ERROR_DETECTED = 11319; // 12
+static const uint64_t SH_FLD_LSMFB_SCAN_ALL_PRIO_ENA = 11320; // 1
+static const uint64_t SH_FLD_LTE_EN = 11321; // 4
+static const uint64_t SH_FLD_LUC = 11322; // 1
+static const uint64_t SH_FLD_LUC_LEN = 11323; // 1
+static const uint64_t SH_FLD_LUT = 11324; // 1
+static const uint64_t SH_FLD_LUT_LEN = 11325; // 1
+static const uint64_t SH_FLD_LVDIR_EN = 11326; // 12
+static const uint64_t SH_FLD_LVDIR_PERR = 11327; // 12
+static const uint64_t SH_FLD_LVLTRANS_FENCE = 11328; // 43
+static const uint64_t SH_FLD_M = 11329; // 1
+static const uint64_t SH_FLD_M0_BIT_MAP = 11330; // 8
+static const uint64_t SH_FLD_M0_BIT_MAP_LEN = 11331; // 8
+static const uint64_t SH_FLD_M0_PRIORITY = 11332; // 1
+static const uint64_t SH_FLD_M0_PRIORITY_LEN = 11333; // 1
+static const uint64_t SH_FLD_M0_PRIORITY_SEL = 11334; // 1
+static const uint64_t SH_FLD_M1HC0A = 11335; // 1
+static const uint64_t SH_FLD_M1HC0A_LEN = 11336; // 1
+static const uint64_t SH_FLD_M1HC0B = 11337; // 1
+static const uint64_t SH_FLD_M1HC0B_LEN = 11338; // 1
+static const uint64_t SH_FLD_M1HC1A = 11339; // 1
+static const uint64_t SH_FLD_M1HC1A_LEN = 11340; // 1
+static const uint64_t SH_FLD_M1HC1B = 11341; // 1
+static const uint64_t SH_FLD_M1HC1B_LEN = 11342; // 1
+static const uint64_t SH_FLD_M1HC2A = 11343; // 1
+static const uint64_t SH_FLD_M1HC2A_LEN = 11344; // 1
+static const uint64_t SH_FLD_M1HC2B = 11345; // 1
+static const uint64_t SH_FLD_M1HC2B_LEN = 11346; // 1
+static const uint64_t SH_FLD_M1SASIM1_ENABLE_PIB_ERROR = 11347; // 1
+static const uint64_t SH_FLD_M1SASIM1_ENABLE_PIB_PENDING = 11348; // 1
+static const uint64_t SH_FLD_M1SASIM1_ENABLE_XUP = 11349; // 1
+static const uint64_t SH_FLD_M1_BIT_MAP = 11350; // 8
+static const uint64_t SH_FLD_M1_BIT_MAP_LEN = 11351; // 8
+static const uint64_t SH_FLD_M1_PRIORITY = 11352; // 1
+static const uint64_t SH_FLD_M1_PRIORITY_LEN = 11353; // 1
+static const uint64_t SH_FLD_M1_PRIORITY_SEL = 11354; // 1
+static const uint64_t SH_FLD_M2HC0A = 11355; // 1
+static const uint64_t SH_FLD_M2HC0A_LEN = 11356; // 1
+static const uint64_t SH_FLD_M2HC0B = 11357; // 1
+static const uint64_t SH_FLD_M2HC0B_LEN = 11358; // 1
+static const uint64_t SH_FLD_M2HC1A = 11359; // 1
+static const uint64_t SH_FLD_M2HC1A_LEN = 11360; // 1
+static const uint64_t SH_FLD_M2HC1B = 11361; // 1
+static const uint64_t SH_FLD_M2HC1B_LEN = 11362; // 1
+static const uint64_t SH_FLD_M2HC2A = 11363; // 1
+static const uint64_t SH_FLD_M2HC2A_LEN = 11364; // 1
+static const uint64_t SH_FLD_M2HC2B = 11365; // 1
+static const uint64_t SH_FLD_M2HC2B_LEN = 11366; // 1
+static const uint64_t SH_FLD_M2_PRIORITY = 11367; // 1
+static const uint64_t SH_FLD_M2_PRIORITY_LEN = 11368; // 1
+static const uint64_t SH_FLD_M2_PRIORITY_SEL = 11369; // 1
+static const uint64_t SH_FLD_M3_PRIORITY = 11370; // 1
+static const uint64_t SH_FLD_M3_PRIORITY_LEN = 11371; // 1
+static const uint64_t SH_FLD_M3_PRIORITY_SEL = 11372; // 1
+static const uint64_t SH_FLD_M4_PRIORITY = 11373; // 1
+static const uint64_t SH_FLD_M4_PRIORITY_LEN = 11374; // 1
+static const uint64_t SH_FLD_M5_PRIORITY = 11375; // 1
+static const uint64_t SH_FLD_M5_PRIORITY_LEN = 11376; // 1
+static const uint64_t SH_FLD_M5_PRIORITY_SEL = 11377; // 1
+static const uint64_t SH_FLD_M6_PRIORITY = 11378; // 1
+static const uint64_t SH_FLD_M6_PRIORITY_LEN = 11379; // 1
+static const uint64_t SH_FLD_M7_PRIORITY = 11380; // 1
+static const uint64_t SH_FLD_M7_PRIORITY_LEN = 11381; // 1
+static const uint64_t SH_FLD_M7_PRIORITY_SEL = 11382; // 1
+static const uint64_t SH_FLD_MAGIC_COOKIE = 11383; // 1
+static const uint64_t SH_FLD_MAGIC_COOKIE_LEN = 11384; // 1
+static const uint64_t SH_FLD_MAINLINE_AUE = 11385; // 8
+static const uint64_t SH_FLD_MAINLINE_IAUE = 11386; // 8
+static const uint64_t SH_FLD_MAINLINE_IMPE = 11387; // 8
+static const uint64_t SH_FLD_MAINLINE_IRCD = 11388; // 8
+static const uint64_t SH_FLD_MAINLINE_IUE = 11389; // 8
+static const uint64_t SH_FLD_MAINLINE_MCE = 11390; // 8
+static const uint64_t SH_FLD_MAINLINE_MPE_RANK_0_TO_7 = 11391; // 8
+static const uint64_t SH_FLD_MAINLINE_MPE_RANK_0_TO_7_LEN = 11392; // 8
+static const uint64_t SH_FLD_MAINLINE_NCE = 11393; // 8
+static const uint64_t SH_FLD_MAINLINE_RCD = 11394; // 8
+static const uint64_t SH_FLD_MAINLINE_SCE = 11395; // 8
+static const uint64_t SH_FLD_MAINLINE_SUE = 11396; // 8
+static const uint64_t SH_FLD_MAINLINE_TCE = 11397; // 8
+static const uint64_t SH_FLD_MAINLINE_UE = 11398; // 8
+static const uint64_t SH_FLD_MAINTENANCE_AUE = 11399; // 8
+static const uint64_t SH_FLD_MAINTENANCE_IAUE = 11400; // 8
+static const uint64_t SH_FLD_MAINTENANCE_IMPE = 11401; // 8
+static const uint64_t SH_FLD_MAINTENANCE_IRCD = 11402; // 8
+static const uint64_t SH_FLD_MAINTENANCE_IUE = 11403; // 8
+static const uint64_t SH_FLD_MAINTENANCE_MCE = 11404; // 8
+static const uint64_t SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7 = 11405; // 8
+static const uint64_t SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7_LEN = 11406; // 8
+static const uint64_t SH_FLD_MAINTENANCE_NCE = 11407; // 8
+static const uint64_t SH_FLD_MAINTENANCE_RCD = 11408; // 8
+static const uint64_t SH_FLD_MAINTENANCE_SCE = 11409; // 8
+static const uint64_t SH_FLD_MAINTENANCE_SUE = 11410; // 8
+static const uint64_t SH_FLD_MAINTENANCE_TCE = 11411; // 8
+static const uint64_t SH_FLD_MAINTENANCE_UE = 11412; // 8
+static const uint64_t SH_FLD_MAINT_CCS_PE_HOLD_OUT = 11413; // 2
+static const uint64_t SH_FLD_MAIN_SLICE_EN_ENC = 11414; // 1
+static const uint64_t SH_FLD_MAIN_SLICE_EN_ENC_LEN = 11415; // 1
+static const uint64_t SH_FLD_MAJOR = 11416; // 1
+static const uint64_t SH_FLD_MAJOR_LEN = 11417; // 1
+static const uint64_t SH_FLD_MALFUNCTION_ALERT = 11418; // 96
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP0 = 11419; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP0_LEN = 11420; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP1 = 11421; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP10 = 11422; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP10_LEN = 11423; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP11 = 11424; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP11_LEN = 11425; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP12 = 11426; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP12_LEN = 11427; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP13 = 11428; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP13_LEN = 11429; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP14 = 11430; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP14_LEN = 11431; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP15 = 11432; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP15_LEN = 11433; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP1_LEN = 11434; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP2 = 11435; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP2_LEN = 11436; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP3 = 11437; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP3_LEN = 11438; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP4 = 11439; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP4_LEN = 11440; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP5 = 11441; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP5_LEN = 11442; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP6 = 11443; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP6_LEN = 11444; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP7 = 11445; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP7_LEN = 11446; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP8 = 11447; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP8_LEN = 11448; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP9 = 11449; // 1
+static const uint64_t SH_FLD_MALF_ERR_FROM_GROUP9_LEN = 11450; // 1
+static const uint64_t SH_FLD_MANUAL_CLR_PB_STOP = 11451; // 1
+static const uint64_t SH_FLD_MANUAL_PB_SWITCH_ABCD = 11452; // 1
+static const uint64_t SH_FLD_MANUAL_RECAL_LANE = 11453; // 6
+static const uint64_t SH_FLD_MANUAL_RECAL_LANE_LEN = 11454; // 6
+static const uint64_t SH_FLD_MANUAL_RECAL_REQUEST = 11455; // 6
+static const uint64_t SH_FLD_MANUAL_SET_PB_STOP = 11456; // 1
+static const uint64_t SH_FLD_MAP_ERR_INJ_PEND = 11457; // 1
+static const uint64_t SH_FLD_MAP_REG_CERR0 = 11458; // 1
+static const uint64_t SH_FLD_MAP_REG_CERR1 = 11459; // 1
+static const uint64_t SH_FLD_MAP_REG_ERR0 = 11460; // 1
+static const uint64_t SH_FLD_MAP_REG_ERR1 = 11461; // 1
+static const uint64_t SH_FLD_MAP_REG_ERR2 = 11462; // 1
+static const uint64_t SH_FLD_MAP_REG_ERR3 = 11463; // 1
+static const uint64_t SH_FLD_MAP_REG_ERR4 = 11464; // 1
+static const uint64_t SH_FLD_MARGINPD_SEL = 11465; // 6
+static const uint64_t SH_FLD_MARGINPD_SEL_LEN = 11466; // 6
+static const uint64_t SH_FLD_MARGINPU_SEL = 11467; // 6
+static const uint64_t SH_FLD_MARGINPU_SEL_LEN = 11468; // 6
+static const uint64_t SH_FLD_MARK = 11469; // 64
+static const uint64_t SH_FLD_MARK_LEN = 11470; // 64
+static const uint64_t SH_FLD_MASK = 11471; // 69
+static const uint64_t SH_FLD_MASKA = 11472; // 90
+static const uint64_t SH_FLD_MASKA_LEN = 11473; // 90
+static const uint64_t SH_FLD_MASKB = 11474; // 90
+static const uint64_t SH_FLD_MASKB_LEN = 11475; // 90
+static const uint64_t SH_FLD_MASKC = 11476; // 90
+static const uint64_t SH_FLD_MASKC_LEN = 11477; // 90
+static const uint64_t SH_FLD_MASKD = 11478; // 90
+static const uint64_t SH_FLD_MASKD_LEN = 11479; // 90
+static const uint64_t SH_FLD_MASK_AGV_DISABLE_MODE = 11480; // 2
+static const uint64_t SH_FLD_MASK_B = 11481; // 129
+static const uint64_t SH_FLD_MASK_LEN = 11482; // 61
+static const uint64_t SH_FLD_MASK_PURGE_INTERFACE = 11483; // 12
+static const uint64_t SH_FLD_MASK_TOGGLE_ENABLE = 11484; // 1
+static const uint64_t SH_FLD_MASTER = 11485; // 8
+static const uint64_t SH_FLD_MASTERID = 11486; // 6
+static const uint64_t SH_FLD_MASTERID_LEN = 11487; // 6
+static const uint64_t SH_FLD_MASTER_ARRAY_CE = 11488; // 4
+static const uint64_t SH_FLD_MASTER_ARRAY_UE = 11489; // 4
+static const uint64_t SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV = 11490; // 12
+static const uint64_t SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV_LEN = 11491; // 12
+static const uint64_t SH_FLD_MASTER_ERROR_CODE = 11492; // 1
+static const uint64_t SH_FLD_MASTER_ERROR_CODE_LEN = 11493; // 1
+static const uint64_t SH_FLD_MASTER_IDLE = 11494; // 1
+static const uint64_t SH_FLD_MASTER_MODE = 11495; // 47
+static const uint64_t SH_FLD_MASTER_RECOVERABLE_ERROR = 11496; // 4
+static const uint64_t SH_FLD_MASTER_RESPONSE_BIT = 11497; // 1
+static const uint64_t SH_FLD_MASTER_SYS_XSTOP_ERROR = 11498; // 4
+static const uint64_t SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV = 11499; // 12
+static const uint64_t SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN = 11500; // 12
+static const uint64_t SH_FLD_MATCH = 11501; // 12
+static const uint64_t SH_FLD_MATCHA_MUXSEL = 11502; // 90
+static const uint64_t SH_FLD_MATCHA_MUXSEL_LEN = 11503; // 90
+static const uint64_t SH_FLD_MATCHB_MUXSEL = 11504; // 90
+static const uint64_t SH_FLD_MATCHB_MUXSEL_LEN = 11505; // 90
+static const uint64_t SH_FLD_MATCHC_MUXSEL = 11506; // 90
+static const uint64_t SH_FLD_MATCHC_MUXSEL_LEN = 11507; // 90
+static const uint64_t SH_FLD_MATCHD_MUXSEL = 11508; // 90
+static const uint64_t SH_FLD_MATCHD_MUXSEL_LEN = 11509; // 90
+static const uint64_t SH_FLD_MATCH_LEN = 11510; // 12
+static const uint64_t SH_FLD_MATCH_NOT_MODE = 11511; // 90
+static const uint64_t SH_FLD_MATCH_NOT_MODE_LEN = 11512; // 90
+static const uint64_t SH_FLD_MAXCYCLECNT = 11513; // 3
+static const uint64_t SH_FLD_MAXCYCLECNT_LEN = 11514; // 3
+static const uint64_t SH_FLD_MAX_BAD_LANES = 11515; // 4
+static const uint64_t SH_FLD_MAX_BAD_LANES_LEN = 11516; // 4
+static const uint64_t SH_FLD_MAX_BER_CHECK_COUNT = 11517; // 4
+static const uint64_t SH_FLD_MAX_BER_CHECK_COUNT_LEN = 11518; // 4
+static const uint64_t SH_FLD_MAX_CRD_TO_CQ = 11519; // 6
+static const uint64_t SH_FLD_MAX_CRD_TO_CQ_LEN = 11520; // 6
+static const uint64_t SH_FLD_MAX_CRD_TO_PC = 11521; // 6
+static const uint64_t SH_FLD_MAX_CRD_TO_PC_LEN = 11522; // 6
+static const uint64_t SH_FLD_MAX_CYCLE_SAMPLE = 11523; // 12
+static const uint64_t SH_FLD_MAX_CYCLE_SAMPLE_LEN = 11524; // 12
+static const uint64_t SH_FLD_MAX_ENTRIES_IN_MODIFIED = 11525; // 3
+static const uint64_t SH_FLD_MAX_ENTRIES_IN_MODIFIED_LEN = 11526; // 3
+static const uint64_t SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS = 11527; // 2
+static const uint64_t SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS_LEN = 11528; // 2
+static const uint64_t SH_FLD_MAX_OUTSTANDING = 11529; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_CI_LOAD = 11530; // 2
+static const uint64_t SH_FLD_MAX_OUTSTANDING_CI_LOAD_LEN = 11531; // 2
+static const uint64_t SH_FLD_MAX_OUTSTANDING_CI_STORE = 11532; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_CI_STORE_LEN = 11533; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_EOI = 11534; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_EOI_LEN = 11535; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_EQD_FETCH = 11536; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_EQD_FETCH_LEN = 11537; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_EQD_WRITE = 11538; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_EQD_WRITE_LEN = 11539; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_EQP = 11540; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_EQP_LEN = 11541; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_ISB_FETCH = 11542; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_ISB_FETCH_LEN = 11543; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_ISB_WRITE = 11544; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_ISB_WRITE_LEN = 11545; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_IVE_FETCH = 11546; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_IVE_FETCH_LEN = 11547; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_LEN = 11548; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP = 11549; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP_LEN = 11550; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_SOFT_EOI = 11551; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_SOFT_EOI_LEN = 11552; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT = 11553; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT_LEN = 11554; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT_VC = 11555; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT_VC_LEN = 11556; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_VPD_FETCH = 11557; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_VPD_FETCH_LEN = 11558; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_WB = 11559; // 1
+static const uint64_t SH_FLD_MAX_OUTSTANDING_WB_LEN = 11560; // 1
+static const uint64_t SH_FLD_MAX_POLL_BCAST_1_0_4 = 11561; // 1
+static const uint64_t SH_FLD_MAX_POLL_BCAST_1_0_4_LEN = 11562; // 1
+static const uint64_t SH_FLD_MAX_POLL_BCAST_2_0_4 = 11563; // 1
+static const uint64_t SH_FLD_MAX_POLL_BCAST_2_0_4_LEN = 11564; // 1
+static const uint64_t SH_FLD_MAX_POLL_BCAST_3_0_4 = 11565; // 1
+static const uint64_t SH_FLD_MAX_POLL_BCAST_3_0_4_LEN = 11566; // 1
+static const uint64_t SH_FLD_MAX_PROMOTE_LEVEL_A_N = 11567; // 96
+static const uint64_t SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN = 11568; // 96
+static const uint64_t SH_FLD_MAX_PTAG_IN_USE = 11569; // 7
+static const uint64_t SH_FLD_MAX_PTAG_IN_USE_LEN = 11570; // 7
+static const uint64_t SH_FLD_MAX_TIMEOUT = 11571; // 10
+static const uint64_t SH_FLD_MAX_TIMEOUT_LEN = 11572; // 10
+static const uint64_t SH_FLD_MAX_UNLOCK_IN_FIFO = 11573; // 4
+static const uint64_t SH_FLD_MAX_UNLOCK_IN_FIFO_LEN = 11574; // 4
+static const uint64_t SH_FLD_MB00_SPATTN = 11575; // 4
+static const uint64_t SH_FLD_MB01_SPATTN = 11576; // 4
+static const uint64_t SH_FLD_MB10_SPATTN = 11577; // 4
+static const uint64_t SH_FLD_MB11_SPATTN = 11578; // 4
+static const uint64_t SH_FLD_MB20_SPATTN = 11579; // 4
+static const uint64_t SH_FLD_MB21_SPATTN = 11580; // 4
+static const uint64_t SH_FLD_MB30_SPATTN = 11581; // 4
+static const uint64_t SH_FLD_MB31_SPATTN = 11582; // 4
+static const uint64_t SH_FLD_MB40_SPATTN = 11583; // 4
+static const uint64_t SH_FLD_MB41_SPATTN = 11584; // 4
+static const uint64_t SH_FLD_MB50_SPATTN = 11585; // 4
+static const uint64_t SH_FLD_MB51_SPATTN = 11586; // 4
+static const uint64_t SH_FLD_MB60_SPATTN = 11587; // 2
+static const uint64_t SH_FLD_MB61_SPATTN = 11588; // 2
+static const uint64_t SH_FLD_MB70_SPATTN = 11589; // 2
+static const uint64_t SH_FLD_MB71_SPATTN = 11590; // 2
+static const uint64_t SH_FLD_MBACALFIRQ_PORT_FAIL = 11591; // 8
+static const uint64_t SH_FLD_MBACALFIRQ_RCD_CAL_PARITY_ERROR = 11592; // 8
+static const uint64_t SH_FLD_MBASE = 11593; // 12
+static const uint64_t SH_FLD_MBASE_LEN = 11594; // 12
+static const uint64_t SH_FLD_MBA_NONRECOVERABLE_ERROR = 11595; // 16
+static const uint64_t SH_FLD_MBA_RECOVERABLE_ERROR = 11596; // 16
+static const uint64_t SH_FLD_MBA_WRD_MODE_CFG_CAW2_CE_UE_ERR_DETECT_EN = 11597; // 8
+static const uint64_t SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_EN = 11598; // 8
+static const uint64_t SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_X8 = 11599; // 8
+static const uint64_t SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_CHK_DISABLE = 11600; // 8
+static const uint64_t SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_COR_DISABLE = 11601; // 8
+static const uint64_t SH_FLD_MBA_WRD_MODE_RESERVED_4 = 11602; // 8
+static const uint64_t SH_FLD_MBOX0 = 11603; // 1
+static const uint64_t SH_FLD_MBOX0_LEN = 11604; // 1
+static const uint64_t SH_FLD_MBOX1 = 11605; // 1
+static const uint64_t SH_FLD_MBOX1_LEN = 11606; // 1
+static const uint64_t SH_FLD_MBOX2 = 11607; // 1
+static const uint64_t SH_FLD_MBOX2_LEN = 11608; // 1
+static const uint64_t SH_FLD_MBOX3 = 11609; // 1
+static const uint64_t SH_FLD_MBOX3_LEN = 11610; // 1
+static const uint64_t SH_FLD_MBOX4 = 11611; // 1
+static const uint64_t SH_FLD_MBOX4_LEN = 11612; // 1
+static const uint64_t SH_FLD_MBOX5 = 11613; // 1
+static const uint64_t SH_FLD_MBOX5_LEN = 11614; // 1
+static const uint64_t SH_FLD_MBOX6 = 11615; // 1
+static const uint64_t SH_FLD_MBOX6_LEN = 11616; // 1
+static const uint64_t SH_FLD_MBOX7 = 11617; // 1
+static const uint64_t SH_FLD_MBOX7_LEN = 11618; // 1
+static const uint64_t SH_FLD_MBR_DIS = 11619; // 2
+static const uint64_t SH_FLD_MBR_DIS_LEN = 11620; // 2
+static const uint64_t SH_FLD_MBSECCQ_DATA_GENERATOR_OVERRIDE = 11621; // 8
+static const uint64_t SH_FLD_MBSECCQ_DATA_INVERSION = 11622; // 8
+static const uint64_t SH_FLD_MBSECCQ_DATA_INVERSION_LEN = 11623; // 8
+static const uint64_t SH_FLD_MBSECCQ_DELAY_NONBYPASS = 11624; // 8
+static const uint64_t SH_FLD_MBSECCQ_DELAY_VALID_1X = 11625; // 8
+static const uint64_t SH_FLD_MBSECCQ_DISABLE_MARK_STORE_WRITE = 11626; // 8
+static const uint64_t SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT = 11627; // 8
+static const uint64_t SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT = 11628; // 8
+static const uint64_t SH_FLD_MBSECCQ_DISABLE_MPE_CONFIRM = 11629; // 8
+static const uint64_t SH_FLD_MBSECCQ_DISABLE_PIPE_NOERR_CLOCK_GATING = 11630; // 8
+static const uint64_t SH_FLD_MBSECCQ_DISABLE_UE_RETRY = 11631; // 8
+static const uint64_t SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY = 11632; // 8
+static const uint64_t SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY_LEN = 11633; // 8
+static const uint64_t SH_FLD_MBSECCQ_ENABLE_CHIPMARKED_SCE_NCE = 11634; // 8
+static const uint64_t SH_FLD_MBSECCQ_ENABLE_HOST_ATTENTION = 11635; // 8
+static const uint64_t SH_FLD_MBSECCQ_ENABLE_SPECIAL_ATTENTION = 11636; // 8
+static const uint64_t SH_FLD_MBSECCQ_ENABLE_TCE_CORRECTION = 11637; // 8
+static const uint64_t SH_FLD_MBSECCQ_ENABLE_UE_NOISE_WINDOW = 11638; // 8
+static const uint64_t SH_FLD_MBSECCQ_EXIT_OVERRIDE = 11639; // 8
+static const uint64_t SH_FLD_MBSECCQ_EXIT_OVERRIDE_LEN = 11640; // 8
+static const uint64_t SH_FLD_MBSECCQ_HWMARK_EXIT1 = 11641; // 8
+static const uint64_t SH_FLD_MBSECCQ_ITAG_METADATA_ENABLE = 11642; // 8
+static const uint64_t SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY = 11643; // 8
+static const uint64_t SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY_LEN = 11644; // 8
+static const uint64_t SH_FLD_MBSECCQ_READ_POINTER_DELAY = 11645; // 8
+static const uint64_t SH_FLD_MBSECCQ_READ_POINTER_DELAY_LEN = 11646; // 8
+static const uint64_t SH_FLD_MBSECCQ_RESERVED_33_39 = 11647; // 8
+static const uint64_t SH_FLD_MBSECCQ_RESERVED_33_39_LEN = 11648; // 8
+static const uint64_t SH_FLD_MBSECCQ_RESERVED_5 = 11649; // 8
+static const uint64_t SH_FLD_MBSECCQ_USE_ADDRESS_HASH = 11650; // 8
+static const uint64_t SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY = 11651; // 8
+static const uint64_t SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY_LEN = 11652; // 8
+static const uint64_t SH_FLD_MB_BAD_ADDR = 11653; // 2
+static const uint64_t SH_FLD_MB_BAD_WRITE = 11654; // 2
+static const uint64_t SH_FLD_MB_CORRUPT = 11655; // 2
+static const uint64_t SH_FLD_MB_LINK_DOWN = 11656; // 2
+static const uint64_t SH_FLD_MB_LINK_ID = 11657; // 2
+static const uint64_t SH_FLD_MB_LINK_ID_LEN = 11658; // 2
+static const uint64_t SH_FLD_MB_RESET = 11659; // 2
+static const uint64_t SH_FLD_MB_SENT = 11660; // 2
+static const uint64_t SH_FLD_MB_SPARE = 11661; // 2
+static const uint64_t SH_FLD_MB_SPARE_LEN = 11662; // 2
+static const uint64_t SH_FLD_MB_VALID = 11663; // 2
+static const uint64_t SH_FLD_MB_WR_NOT_RD = 11664; // 2
+static const uint64_t SH_FLD_MCA_DBG_SEL_IN = 11665; // 8
+static const uint64_t SH_FLD_MCA_DBG_SEL_WRT = 11666; // 8
+static const uint64_t SH_FLD_MCBAGEN_PE_HOLD_OUT = 11667; // 2
+static const uint64_t SH_FLD_MCBCM_PE = 11668; // 8
+static const uint64_t SH_FLD_MCBCNTL_PE_HOLD_OUT = 11669; // 2
+static const uint64_t SH_FLD_MCBCNTL_PORT_SEL = 11670; // 2
+static const uint64_t SH_FLD_MCBCNTL_PORT_SEL_LEN = 11671; // 2
+static const uint64_t SH_FLD_MCBDGEN_PE_HOLD_OUT = 11672; // 2
+static const uint64_t SH_FLD_MCBERR_SCOM_PE_HOLD_OUT = 11673; // 2
+static const uint64_t SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC = 11674; // 2
+static const uint64_t SH_FLD_MCBIST_CCS_SUBTEST_DONE = 11675; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR = 11676; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST = 11677; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST = 11678; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_REF_WAIT_TIME = 11679; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_REF_WAIT_TIME_LEN = 11680; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_RAND_MODE = 11681; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_REV_MODE = 11682; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL = 11683; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL_LEN = 11684; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_1ST_CMD = 11685; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_2ND_CMD = 11686; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_3RD_CMD = 11687; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST00_DATA_MODE = 11688; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST00_DATA_MODE_LEN = 11689; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST00_DONE = 11690; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST00_ECC_MODE = 11691; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST00_OP_TYPE = 11692; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST00_OP_TYPE_LEN = 11693; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_RAND_MODE = 11694; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_REV_MODE = 11695; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL = 11696; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL_LEN = 11697; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_1ST_CMD = 11698; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_2ND_CMD = 11699; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_3RD_CMD = 11700; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST01_DATA_MODE = 11701; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST01_DATA_MODE_LEN = 11702; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST01_DONE = 11703; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST01_ECC_MODE = 11704; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST01_OP_TYPE = 11705; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST01_OP_TYPE_LEN = 11706; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_RAND_MODE = 11707; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_REV_MODE = 11708; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL = 11709; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL_LEN = 11710; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_1ST_CMD = 11711; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_2ND_CMD = 11712; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_3RD_CMD = 11713; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST02_DATA_MODE = 11714; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST02_DATA_MODE_LEN = 11715; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST02_DONE = 11716; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST02_ECC_MODE = 11717; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST02_OP_TYPE = 11718; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST02_OP_TYPE_LEN = 11719; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_RAND_MODE = 11720; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_REV_MODE = 11721; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL = 11722; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL_LEN = 11723; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_1ST_CMD = 11724; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_2ND_CMD = 11725; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_3RD_CMD = 11726; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST03_DATA_MODE = 11727; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST03_DATA_MODE_LEN = 11728; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST03_DONE = 11729; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST03_ECC_MODE = 11730; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST03_OP_TYPE = 11731; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST03_OP_TYPE_LEN = 11732; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_RAND_MODE = 11733; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_REV_MODE = 11734; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL = 11735; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL_LEN = 11736; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_1ST_CMD = 11737; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_2ND_CMD = 11738; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_3RD_CMD = 11739; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST04_DATA_MODE = 11740; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST04_DATA_MODE_LEN = 11741; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST04_DONE = 11742; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST04_ECC_MODE = 11743; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST04_OP_TYPE = 11744; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST04_OP_TYPE_LEN = 11745; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_RAND_MODE = 11746; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_REV_MODE = 11747; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL = 11748; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL_LEN = 11749; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_1ST_CMD = 11750; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_2ND_CMD = 11751; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_3RD_CMD = 11752; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST05_DATA_MODE = 11753; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST05_DATA_MODE_LEN = 11754; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST05_DONE = 11755; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST05_ECC_MODE = 11756; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST05_OP_TYPE = 11757; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST05_OP_TYPE_LEN = 11758; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_RAND_MODE = 11759; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_REV_MODE = 11760; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL = 11761; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL_LEN = 11762; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_1ST_CMD = 11763; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_2ND_CMD = 11764; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_3RD_CMD = 11765; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST06_DATA_MODE = 11766; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST06_DATA_MODE_LEN = 11767; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST06_DONE = 11768; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST06_ECC_MODE = 11769; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST06_OP_TYPE = 11770; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST06_OP_TYPE_LEN = 11771; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_RAND_MODE = 11772; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_REV_MODE = 11773; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL = 11774; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL_LEN = 11775; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_1ST_CMD = 11776; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_2ND_CMD = 11777; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_3RD_CMD = 11778; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST07_DATA_MODE = 11779; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST07_DATA_MODE_LEN = 11780; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST07_DONE = 11781; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST07_ECC_MODE = 11782; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST07_OP_TYPE = 11783; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST07_OP_TYPE_LEN = 11784; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_RAND_MODE = 11785; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_REV_MODE = 11786; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL = 11787; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL_LEN = 11788; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_1ST_CMD = 11789; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_2ND_CMD = 11790; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_3RD_CMD = 11791; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST08_DATA_MODE = 11792; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST08_DATA_MODE_LEN = 11793; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST08_DONE = 11794; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST08_ECC_MODE = 11795; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST08_OP_TYPE = 11796; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST08_OP_TYPE_LEN = 11797; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_RAND_MODE = 11798; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_REV_MODE = 11799; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL = 11800; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL_LEN = 11801; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_1ST_CMD = 11802; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_2ND_CMD = 11803; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_3RD_CMD = 11804; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST09_DATA_MODE = 11805; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST09_DATA_MODE_LEN = 11806; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST09_DONE = 11807; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST09_ECC_MODE = 11808; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST09_OP_TYPE = 11809; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST09_OP_TYPE_LEN = 11810; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_RAND_MODE = 11811; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_REV_MODE = 11812; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL = 11813; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL_LEN = 11814; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_1ST_CMD = 11815; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_2ND_CMD = 11816; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_3RD_CMD = 11817; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST10_DATA_MODE = 11818; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST10_DATA_MODE_LEN = 11819; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST10_DONE = 11820; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST10_ECC_MODE = 11821; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST10_OP_TYPE = 11822; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST10_OP_TYPE_LEN = 11823; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_RAND_MODE = 11824; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_REV_MODE = 11825; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL = 11826; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL_LEN = 11827; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_1ST_CMD = 11828; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_2ND_CMD = 11829; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_3RD_CMD = 11830; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST11_DATA_MODE = 11831; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST11_DATA_MODE_LEN = 11832; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST11_DONE = 11833; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST11_ECC_MODE = 11834; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST11_OP_TYPE = 11835; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST11_OP_TYPE_LEN = 11836; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_RAND_MODE = 11837; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_REV_MODE = 11838; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL = 11839; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL_LEN = 11840; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_1ST_CMD = 11841; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_2ND_CMD = 11842; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_3RD_CMD = 11843; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST12_DATA_MODE = 11844; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST12_DATA_MODE_LEN = 11845; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST12_DONE = 11846; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST12_ECC_MODE = 11847; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST12_OP_TYPE = 11848; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST12_OP_TYPE_LEN = 11849; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_RAND_MODE = 11850; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_REV_MODE = 11851; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL = 11852; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL_LEN = 11853; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_1ST_CMD = 11854; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_2ND_CMD = 11855; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_3RD_CMD = 11856; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST13_DATA_MODE = 11857; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST13_DATA_MODE_LEN = 11858; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST13_DONE = 11859; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST13_ECC_MODE = 11860; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST13_OP_TYPE = 11861; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST13_OP_TYPE_LEN = 11862; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_RAND_MODE = 11863; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_REV_MODE = 11864; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL = 11865; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL_LEN = 11866; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_1ST_CMD = 11867; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_2ND_CMD = 11868; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_3RD_CMD = 11869; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST14_DATA_MODE = 11870; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST14_DATA_MODE_LEN = 11871; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST14_DONE = 11872; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST14_ECC_MODE = 11873; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST14_OP_TYPE = 11874; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST14_OP_TYPE_LEN = 11875; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_RAND_MODE = 11876; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_REV_MODE = 11877; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL = 11878; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL_LEN = 11879; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_1ST_CMD = 11880; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_2ND_CMD = 11881; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_3RD_CMD = 11882; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST15_DATA_MODE = 11883; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST15_DATA_MODE_LEN = 11884; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST15_DONE = 11885; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST15_ECC_MODE = 11886; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST15_OP_TYPE = 11887; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST15_OP_TYPE_LEN = 11888; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_RAND_MODE = 11889; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_REV_MODE = 11890; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL = 11891; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL_LEN = 11892; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_1ST_CMD = 11893; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_2ND_CMD = 11894; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_3RD_CMD = 11895; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST16_DATA_MODE = 11896; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST16_DATA_MODE_LEN = 11897; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST16_DONE = 11898; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST16_ECC_MODE = 11899; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST16_OP_TYPE = 11900; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST16_OP_TYPE_LEN = 11901; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_RAND_MODE = 11902; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_REV_MODE = 11903; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL = 11904; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL_LEN = 11905; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_1ST_CMD = 11906; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_2ND_CMD = 11907; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_3RD_CMD = 11908; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST17_DATA_MODE = 11909; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST17_DATA_MODE_LEN = 11910; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST17_DONE = 11911; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST17_ECC_MODE = 11912; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST17_OP_TYPE = 11913; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST17_OP_TYPE_LEN = 11914; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_RAND_MODE = 11915; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_REV_MODE = 11916; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL = 11917; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL_LEN = 11918; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_1ST_CMD = 11919; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_2ND_CMD = 11920; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_3RD_CMD = 11921; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST18_DATA_MODE = 11922; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST18_DATA_MODE_LEN = 11923; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST18_DONE = 11924; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST18_ECC_MODE = 11925; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST18_OP_TYPE = 11926; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST18_OP_TYPE_LEN = 11927; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_RAND_MODE = 11928; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_REV_MODE = 11929; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL = 11930; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL_LEN = 11931; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_1ST_CMD = 11932; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_2ND_CMD = 11933; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_3RD_CMD = 11934; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST19_DATA_MODE = 11935; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST19_DATA_MODE_LEN = 11936; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST19_DONE = 11937; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST19_ECC_MODE = 11938; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST19_OP_TYPE = 11939; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST19_OP_TYPE_LEN = 11940; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_RAND_MODE = 11941; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_REV_MODE = 11942; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL = 11943; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL_LEN = 11944; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_1ST_CMD = 11945; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_2ND_CMD = 11946; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_3RD_CMD = 11947; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST20_DATA_MODE = 11948; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST20_DATA_MODE_LEN = 11949; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST20_DONE = 11950; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST20_ECC_MODE = 11951; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST20_OP_TYPE = 11952; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST20_OP_TYPE_LEN = 11953; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_RAND_MODE = 11954; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_REV_MODE = 11955; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL = 11956; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL_LEN = 11957; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_1ST_CMD = 11958; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_2ND_CMD = 11959; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_3RD_CMD = 11960; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST21_DATA_MODE = 11961; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST21_DATA_MODE_LEN = 11962; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST21_DONE = 11963; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST21_ECC_MODE = 11964; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST21_OP_TYPE = 11965; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST21_OP_TYPE_LEN = 11966; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_RAND_MODE = 11967; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_REV_MODE = 11968; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL = 11969; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL_LEN = 11970; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_1ST_CMD = 11971; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_2ND_CMD = 11972; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_3RD_CMD = 11973; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST22_DATA_MODE = 11974; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST22_DATA_MODE_LEN = 11975; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST22_DONE = 11976; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST22_ECC_MODE = 11977; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST22_OP_TYPE = 11978; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST22_OP_TYPE_LEN = 11979; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_RAND_MODE = 11980; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_REV_MODE = 11981; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL = 11982; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL_LEN = 11983; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_1ST_CMD = 11984; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_2ND_CMD = 11985; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_3RD_CMD = 11986; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST23_DATA_MODE = 11987; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST23_DATA_MODE_LEN = 11988; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST23_DONE = 11989; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST23_ECC_MODE = 11990; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST23_OP_TYPE = 11991; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST23_OP_TYPE_LEN = 11992; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_RAND_MODE = 11993; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_REV_MODE = 11994; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL = 11995; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL_LEN = 11996; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_1ST_CMD = 11997; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_2ND_CMD = 11998; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_3RD_CMD = 11999; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST24_DATA_MODE = 12000; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST24_DATA_MODE_LEN = 12001; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST24_DONE = 12002; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST24_ECC_MODE = 12003; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST24_OP_TYPE = 12004; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST24_OP_TYPE_LEN = 12005; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_RAND_MODE = 12006; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_REV_MODE = 12007; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL = 12008; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL_LEN = 12009; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_1ST_CMD = 12010; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_2ND_CMD = 12011; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_3RD_CMD = 12012; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST25_DATA_MODE = 12013; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST25_DATA_MODE_LEN = 12014; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST25_DONE = 12015; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST25_ECC_MODE = 12016; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST25_OP_TYPE = 12017; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST25_OP_TYPE_LEN = 12018; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_RAND_MODE = 12019; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_REV_MODE = 12020; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL = 12021; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL_LEN = 12022; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_1ST_CMD = 12023; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_2ND_CMD = 12024; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_3RD_CMD = 12025; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST26_DATA_MODE = 12026; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST26_DATA_MODE_LEN = 12027; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST26_DONE = 12028; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST26_ECC_MODE = 12029; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST26_OP_TYPE = 12030; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST26_OP_TYPE_LEN = 12031; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_RAND_MODE = 12032; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_REV_MODE = 12033; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL = 12034; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL_LEN = 12035; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_1ST_CMD = 12036; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_2ND_CMD = 12037; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_3RD_CMD = 12038; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST27_DATA_MODE = 12039; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST27_DATA_MODE_LEN = 12040; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST27_DONE = 12041; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST27_ECC_MODE = 12042; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST27_OP_TYPE = 12043; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST27_OP_TYPE_LEN = 12044; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_RAND_MODE = 12045; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_REV_MODE = 12046; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL = 12047; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL_LEN = 12048; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_1ST_CMD = 12049; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_2ND_CMD = 12050; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_3RD_CMD = 12051; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST28_DATA_MODE = 12052; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST28_DATA_MODE_LEN = 12053; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST28_DONE = 12054; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST28_ECC_MODE = 12055; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST28_OP_TYPE = 12056; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST28_OP_TYPE_LEN = 12057; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_RAND_MODE = 12058; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_REV_MODE = 12059; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL = 12060; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL_LEN = 12061; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_1ST_CMD = 12062; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_2ND_CMD = 12063; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_3RD_CMD = 12064; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST29_DATA_MODE = 12065; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST29_DATA_MODE_LEN = 12066; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST29_DONE = 12067; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST29_ECC_MODE = 12068; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST29_OP_TYPE = 12069; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST29_OP_TYPE_LEN = 12070; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_RAND_MODE = 12071; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_REV_MODE = 12072; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL = 12073; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL_LEN = 12074; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_1ST_CMD = 12075; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_2ND_CMD = 12076; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_3RD_CMD = 12077; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST30_DATA_MODE = 12078; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST30_DATA_MODE_LEN = 12079; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST30_DONE = 12080; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST30_ECC_MODE = 12081; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST30_OP_TYPE = 12082; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST30_OP_TYPE_LEN = 12083; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_RAND_MODE = 12084; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_REV_MODE = 12085; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL = 12086; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL_LEN = 12087; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_1ST_CMD = 12088; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_2ND_CMD = 12089; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_3RD_CMD = 12090; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST31_DATA_MODE = 12091; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST31_DATA_MODE_LEN = 12092; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST31_DONE = 12093; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST31_ECC_MODE = 12094; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST31_OP_TYPE = 12095; // 2
+static const uint64_t SH_FLD_MCBIST_CFG_TEST31_OP_TYPE_LEN = 12096; // 2
+static const uint64_t SH_FLD_MCBIST_DATA_ERROR = 12097; // 2
+static const uint64_t SH_FLD_MCBIST_FSM_INJ_MODE = 12098; // 2
+static const uint64_t SH_FLD_MCBIST_FSM_INJ_REG = 12099; // 2
+static const uint64_t SH_FLD_MCBIST_HALF_COMPARE_MASK = 12100; // 8
+static const uint64_t SH_FLD_MCBIST_HALF_COMPARE_MASK_LEN = 12101; // 8
+static const uint64_t SH_FLD_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR = 12102; // 2
+static const uint64_t SH_FLD_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR_LEN = 12103; // 2
+static const uint64_t SH_FLD_MCBIST_MASK_COVERAGE_SELECTOR = 12104; // 8
+static const uint64_t SH_FLD_MCBIST_PROGRAM_COMPLETE = 12105; // 2
+static const uint64_t SH_FLD_MCBIST_SUBTEST_IP = 12106; // 2
+static const uint64_t SH_FLD_MCBIST_SUBTEST_NUM_INDICATOR = 12107; // 2
+static const uint64_t SH_FLD_MCBIST_SUBTEST_NUM_INDICATOR_LEN = 12108; // 2
+static const uint64_t SH_FLD_MCBIST_TRAP_CE_ENABLE = 12109; // 8
+static const uint64_t SH_FLD_MCBIST_TRAP_MPE_ENABLE = 12110; // 8
+static const uint64_t SH_FLD_MCBIST_TRAP_NONSTOP = 12111; // 8
+static const uint64_t SH_FLD_MCBIST_TRAP_UE_ENABLE = 12112; // 8
+static const uint64_t SH_FLD_MCB_CNTLQ_PE_HOLD_OUT = 12113; // 2
+static const uint64_t SH_FLD_MCB_FIR_CCS_ERR_HOLD_OUT = 12114; // 2
+static const uint64_t SH_FLD_MCB_FIR_MCBFSM_ERR_HOLD_OUT = 12115; // 2
+static const uint64_t SH_FLD_MCD_ACK_DEAD_CRESP_ERR = 12116; // 2
+static const uint64_t SH_FLD_MCD_ARRAY_ECC_CE_ERR = 12117; // 2
+static const uint64_t SH_FLD_MCD_ARRAY_ECC_UE_ERR = 12118; // 2
+static const uint64_t SH_FLD_MCD_CHICKEN_SWITCH = 12119; // 2
+static const uint64_t SH_FLD_MCD_CL_PROBE_PB_HANG_ERR = 12120; // 2
+static const uint64_t SH_FLD_MCD_CRESP_ADDR_ERR = 12121; // 2
+static const uint64_t SH_FLD_MCD_PB_ADDR_PARITY_ERR = 12122; // 2
+static const uint64_t SH_FLD_MCD_SCOM_ERR = 12123; // 2
+static const uint64_t SH_FLD_MCD_SCOM_ERR_DUP = 12124; // 2
+static const uint64_t SH_FLD_MCD_SM_OR_CASE_ERR = 12125; // 2
+static const uint64_t SH_FLD_MCD_TTAG_PARITY_ERR = 12126; // 2
+static const uint64_t SH_FLD_MCD_UNSOLICITED_CRESP_ERR = 12127; // 2
+static const uint64_t SH_FLD_MCD_UPDATE_ERR = 12128; // 2
+static const uint64_t SH_FLD_MCE_SYMBOL0_COUNT = 12129; // 2
+static const uint64_t SH_FLD_MCE_SYMBOL0_COUNT_LEN = 12130; // 2
+static const uint64_t SH_FLD_MCE_SYMBOL1_COUNT = 12131; // 2
+static const uint64_t SH_FLD_MCE_SYMBOL1_COUNT_LEN = 12132; // 2
+static const uint64_t SH_FLD_MCE_SYMBOL2_COUNT = 12133; // 2
+static const uint64_t SH_FLD_MCE_SYMBOL2_COUNT_LEN = 12134; // 2
+static const uint64_t SH_FLD_MCE_SYMBOL3_COUNT = 12135; // 2
+static const uint64_t SH_FLD_MCE_SYMBOL3_COUNT_LEN = 12136; // 2
+static const uint64_t SH_FLD_MCMD = 12137; // 24
+static const uint64_t SH_FLD_MCMD_LEN = 12138; // 24
+static const uint64_t SH_FLD_MCMODE0_64B_WR_IS_PWRT = 12139; // 4
+static const uint64_t SH_FLD_MCPERF1_DISABLE_FASTPATH_QOS = 12140; // 4
+static const uint64_t SH_FLD_MCS01_TC_0_FIR_HOST_ATTN = 12141; // 1
+static const uint64_t SH_FLD_MCS01_TC_1_FIR_HOST_ATTN = 12142; // 1
+static const uint64_t SH_FLD_MCS23_TC_0_FIR_HOST_ATTN = 12143; // 1
+static const uint64_t SH_FLD_MCS23_TC_1_FIR_HOST_ATTN = 12144; // 1
+static const uint64_t SH_FLD_MCS_RESET_KEEPER = 12145; // 4
+static const uint64_t SH_FLD_MCS_WAT0 = 12146; // 4
+static const uint64_t SH_FLD_MCS_WAT1 = 12147; // 4
+static const uint64_t SH_FLD_MCS_WAT2 = 12148; // 4
+static const uint64_t SH_FLD_MCS_WAT3 = 12149; // 4
+static const uint64_t SH_FLD_MCWATDATA0 = 12150; // 4
+static const uint64_t SH_FLD_MCWATDATA0_LEN = 12151; // 4
+static const uint64_t SH_FLD_MC_CHANNELS_PER_GROUP = 12152; // 4
+static const uint64_t SH_FLD_MC_CHANNELS_PER_GROUP_LEN = 12153; // 4
+static const uint64_t SH_FLD_MC_FP_MATE_CMD_ERR0 = 12154; // 12
+static const uint64_t SH_FLD_MC_FP_MATE_CMD_ERR1 = 12155; // 12
+static const uint64_t SH_FLD_MC_INTERNAL_NONRECOVERABLE_ERROR = 12156; // 4
+static const uint64_t SH_FLD_MC_INTERNAL_RECOVERABLE_ERROR = 12157; // 4
+static const uint64_t SH_FLD_MC_TC_0_FIR_HOST_ATTN = 12158; // 3
+static const uint64_t SH_FLD_MC_TC_1_FIR_HOST_ATTN = 12159; // 3
+static const uint64_t SH_FLD_MC_TC_2_FIR_HOST_ATTN = 12160; // 3
+static const uint64_t SH_FLD_MC_TC_3_FIR_HOST_ATTN = 12161; // 3
+static const uint64_t SH_FLD_MC_TC_4_FIR_HOST_ATTN = 12162; // 3
+static const uint64_t SH_FLD_MC_TC_5_FIR_HOST_ATTN = 12163; // 3
+static const uint64_t SH_FLD_MC_TC_6_FIR_HOST_ATTN = 12164; // 3
+static const uint64_t SH_FLD_MC_TC_7_FIR_HOST_ATTN = 12165; // 3
+static const uint64_t SH_FLD_MC_TC_8_FIR_HOST_ATTN = 12166; // 2
+static const uint64_t SH_FLD_MD5_LATENCY_CFG = 12167; // 1
+static const uint64_t SH_FLD_MDI_0 = 12168; // 8
+static const uint64_t SH_FLD_MDI_1 = 12169; // 8
+static const uint64_t SH_FLD_MED_IDLE_COUNT = 12170; // 8
+static const uint64_t SH_FLD_MED_IDLE_COUNT_LEN = 12171; // 8
+static const uint64_t SH_FLD_MED_IDLE_THRESHOLD = 12172; // 8
+static const uint64_t SH_FLD_MED_IDLE_THRESHOLD_LEN = 12173; // 8
+static const uint64_t SH_FLD_MEGAMOUTH = 12174; // 24
+static const uint64_t SH_FLD_MEM = 12175; // 26
+static const uint64_t SH_FLD_MEMCTL_CIC_FAST = 12176; // 8
+static const uint64_t SH_FLD_MEMCTL_CTRN_IGNORE = 12177; // 8
+static const uint64_t SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP = 12178; // 4
+static const uint64_t SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN = 12179; // 4
+static const uint64_t SH_FLD_MEMORY_TYPE = 12180; // 8
+static const uint64_t SH_FLD_MEMORY_TYPE_LEN = 12181; // 8
+static const uint64_t SH_FLD_MEM_ADDR = 12182; // 21
+static const uint64_t SH_FLD_MEM_ADDR_LEN = 12183; // 21
+static const uint64_t SH_FLD_MEM_BUSY = 12184; // 21
+static const uint64_t SH_FLD_MEM_BYTE_ENABLE = 12185; // 21
+static const uint64_t SH_FLD_MEM_BYTE_ENABLE_LEN = 12186; // 21
+static const uint64_t SH_FLD_MEM_DATAOP_PENDING = 12187; // 21
+static const uint64_t SH_FLD_MEM_ERROR = 12188; // 21
+static const uint64_t SH_FLD_MEM_ERROR_LEN = 12189; // 21
+static const uint64_t SH_FLD_MEM_HIGH_PRIORITY = 12190; // 4
+static const uint64_t SH_FLD_MEM_HIGH_PRIORITY_LEN = 12191; // 4
+static const uint64_t SH_FLD_MEM_IFETCH_PENDING = 12192; // 21
+static const uint64_t SH_FLD_MEM_IMPRECISE_ERROR_PENDING = 12193; // 21
+static const uint64_t SH_FLD_MEM_LEN = 12194; // 26
+static const uint64_t SH_FLD_MEM_LINE_MODE = 12195; // 21
+static const uint64_t SH_FLD_MEM_LOW_PRIORITY = 12196; // 4
+static const uint64_t SH_FLD_MEM_LOW_PRIORITY_LEN = 12197; // 4
+static const uint64_t SH_FLD_MEM_R_NW = 12198; // 21
+static const uint64_t SH_FLD_MEM_SIZE = 12199; // 6
+static const uint64_t SH_FLD_MEM_SIZE_LEN = 12200; // 6
+static const uint64_t SH_FLD_MERGE_CAPACITY_LIMIT = 12201; // 12
+static const uint64_t SH_FLD_MERGE_CAPACITY_LIMIT_LEN = 12202; // 12
+static const uint64_t SH_FLD_MESSAGE_BITS0 = 12203; // 15
+static const uint64_t SH_FLD_MESSAGE_BITS0_LEN = 12204; // 15
+static const uint64_t SH_FLD_MESSAGE_BITS1 = 12205; // 15
+static const uint64_t SH_FLD_MESSAGE_BITS1_LEN = 12206; // 15
+static const uint64_t SH_FLD_MESSAGE_BITS2 = 12207; // 12
+static const uint64_t SH_FLD_MESSAGE_BITS2_LEN = 12208; // 12
+static const uint64_t SH_FLD_MESSAGE_BITS3 = 12209; // 12
+static const uint64_t SH_FLD_MESSAGE_BITS3_LEN = 12210; // 12
+static const uint64_t SH_FLD_MESSAGE_BITS4 = 12211; // 12
+static const uint64_t SH_FLD_MESSAGE_BITS4_LEN = 12212; // 12
+static const uint64_t SH_FLD_MGR_CREDIT = 12213; // 3
+static const uint64_t SH_FLD_MGR_CREDIT_LEN = 12214; // 3
+static const uint64_t SH_FLD_MIB_GPIO = 12215; // 13
+static const uint64_t SH_FLD_MIB_GPIO_LEN = 12216; // 13
+static const uint64_t SH_FLD_MID_CARE_MASK = 12217; // 4
+static const uint64_t SH_FLD_MID_CARE_MASK_LEN = 12218; // 4
+static const uint64_t SH_FLD_MID_MATCH_VALUE = 12219; // 4
+static const uint64_t SH_FLD_MID_MATCH_VALUE_LEN = 12220; // 4
+static const uint64_t SH_FLD_MIG_REG = 12221; // 1
+static const uint64_t SH_FLD_MIG_REG_LEN = 12222; // 1
+static const uint64_t SH_FLD_MINCYCLECNT = 12223; // 3
+static const uint64_t SH_FLD_MINCYCLECNT_LEN = 12224; // 3
+static const uint64_t SH_FLD_MINIKERF = 12225; // 2
+static const uint64_t SH_FLD_MINIKERF_LEN = 12226; // 2
+static const uint64_t SH_FLD_MINOR = 12227; // 1
+static const uint64_t SH_FLD_MINOR_LEN = 12228; // 1
+static const uint64_t SH_FLD_MIN_CYCLE_SAMPLE = 12229; // 12
+static const uint64_t SH_FLD_MIN_CYCLE_SAMPLE_LEN = 12230; // 12
+static const uint64_t SH_FLD_MIN_EYE_HEIGHT = 12231; // 6
+static const uint64_t SH_FLD_MIN_EYE_HEIGHT_LEN = 12232; // 6
+static const uint64_t SH_FLD_MIN_EYE_WIDTH = 12233; // 6
+static const uint64_t SH_FLD_MIN_EYE_WIDTH_LEN = 12234; // 6
+static const uint64_t SH_FLD_MIRROR_ACTION_OCCURRED = 12235; // 4
+static const uint64_t SH_FLD_MISC = 12236; // 10
+static const uint64_t SH_FLD_MISC_BUS0BYTE0 = 12237; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE0_LEN = 12238; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE1 = 12239; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE10 = 12240; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE10_LEN = 12241; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE1_LEN = 12242; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE2 = 12243; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE2_LEN = 12244; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE3 = 12245; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE3_LEN = 12246; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE4 = 12247; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE4_LEN = 12248; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE5 = 12249; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE5_LEN = 12250; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE6 = 12251; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE6_LEN = 12252; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE7 = 12253; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE7_LEN = 12254; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE8 = 12255; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE8_LEN = 12256; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE9 = 12257; // 1
+static const uint64_t SH_FLD_MISC_BUS0BYTE9_LEN = 12258; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE0 = 12259; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE0_LEN = 12260; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE1 = 12261; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE10 = 12262; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE10_LEN = 12263; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE1_LEN = 12264; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE2 = 12265; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE2_LEN = 12266; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE3 = 12267; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE3_LEN = 12268; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE4 = 12269; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE4_LEN = 12270; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE5 = 12271; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE5_LEN = 12272; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE6 = 12273; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE6_LEN = 12274; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE7 = 12275; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE7_LEN = 12276; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE8 = 12277; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE8_LEN = 12278; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE9 = 12279; // 1
+static const uint64_t SH_FLD_MISC_BUS1BYTE9_LEN = 12280; // 1
+static const uint64_t SH_FLD_MISC_CFG = 12281; // 6
+static const uint64_t SH_FLD_MISC_CFG_LEN = 12282; // 6
+static const uint64_t SH_FLD_MISC_CTL_4VS64 = 12283; // 1
+static const uint64_t SH_FLD_MISC_CTL_ACCEPT_PASTE = 12284; // 1
+static const uint64_t SH_FLD_MISC_CTL_CAM_INVAL_DONE = 12285; // 1
+static const uint64_t SH_FLD_MISC_CTL_CAM_LOCATION = 12286; // 1
+static const uint64_t SH_FLD_MISC_CTL_CAM_LOCATION_LEN = 12287; // 1
+static const uint64_t SH_FLD_MISC_CTL_DISABLE_PUSH2MEM_LIMIT = 12288; // 1
+static const uint64_t SH_FLD_MISC_CTL_ENABLE_WRMON = 12289; // 1
+static const uint64_t SH_FLD_MISC_CTL_HMI_ACTIVE = 12290; // 1
+static const uint64_t SH_FLD_MISC_CTL_INVALIDATE_CAM_ALL = 12291; // 1
+static const uint64_t SH_FLD_MISC_CTL_INVALIDATE_CAM_LOC = 12292; // 1
+static const uint64_t SH_FLD_MISC_CTL_PREFETCH_DISABLE = 12293; // 1
+static const uint64_t SH_FLD_MISC_CTL_QUIESCE_REQUEST = 12294; // 1
+static const uint64_t SH_FLD_MISC_CTL_RG_IS_IDLE = 12295; // 1
+static const uint64_t SH_FLD_MISC_CTL_UNUSED_BITS = 12296; // 1
+static const uint64_t SH_FLD_MISC_CTL_UNUSED_BITS2 = 12297; // 1
+static const uint64_t SH_FLD_MISC_CTL_UNUSED_BITS_LEN = 12298; // 1
+static const uint64_t SH_FLD_MISC_CTRL_PERR = 12299; // 1
+static const uint64_t SH_FLD_MISC_DA_ADDR_PERR = 12300; // 1
+static const uint64_t SH_FLD_MISC_DA_OP = 12301; // 1
+static const uint64_t SH_FLD_MISC_INT_RA_PERR = 12302; // 1
+static const uint64_t SH_FLD_MISC_LEN = 12303; // 10
+static const uint64_t SH_FLD_MISC_LENGTH = 12304; // 1
+static const uint64_t SH_FLD_MISC_LENGTH_LEN = 12305; // 1
+static const uint64_t SH_FLD_MISC_LENR = 12306; // 1
+static const uint64_t SH_FLD_MISC_LENR_LEN = 12307; // 1
+static const uint64_t SH_FLD_MISC_NMMU_ERR = 12308; // 1
+static const uint64_t SH_FLD_MISC_RESYNC_OSC_FROM = 12309; // 1
+static const uint64_t SH_FLD_MISC_RING_ERR = 12310; // 1
+static const uint64_t SH_FLD_MISC_RNW = 12311; // 1
+static const uint64_t SH_FLD_MISC_RSVD = 12312; // 1
+static const uint64_t SH_FLD_MISC_RSVD_LEN = 12313; // 1
+static const uint64_t SH_FLD_MISR_A_VAL = 12314; // 43
+static const uint64_t SH_FLD_MISR_A_VAL_LEN = 12315; // 43
+static const uint64_t SH_FLD_MISR_B_VAL = 12316; // 43
+static const uint64_t SH_FLD_MISR_B_VAL_LEN = 12317; // 43
+static const uint64_t SH_FLD_MISR_INIT_WAIT = 12318; // 43
+static const uint64_t SH_FLD_MISR_INIT_WAIT_LEN = 12319; // 43
+static const uint64_t SH_FLD_MISR_MODE = 12320; // 43
+static const uint64_t SH_FLD_MLC_ACCESS_ERR_ESR = 12321; // 1
+static const uint64_t SH_FLD_MMIO = 12322; // 15
+static const uint64_t SH_FLD_MMIOSD = 12323; // 1
+static const uint64_t SH_FLD_MMIO_BAR_PE = 12324; // 1
+static const uint64_t SH_FLD_MMIO_CTL_ACTYPE = 12325; // 1
+static const uint64_t SH_FLD_MMIO_CTL_COMP = 12326; // 1
+static const uint64_t SH_FLD_MMIO_CTL_INIT = 12327; // 1
+static const uint64_t SH_FLD_MMIO_CTL_OFFSET = 12328; // 1
+static const uint64_t SH_FLD_MMIO_CTL_OFFSET_LEN = 12329; // 1
+static const uint64_t SH_FLD_MMIO_CTL_OPTYPE = 12330; // 1
+static const uint64_t SH_FLD_MMIO_CTL_OP_ERR = 12331; // 1
+static const uint64_t SH_FLD_MMIO_CTL_UNUSED = 12332; // 1
+static const uint64_t SH_FLD_MMIO_CTL_UNUSED_LEN = 12333; // 1
+static const uint64_t SH_FLD_MMIO_CTL_WINID = 12334; // 1
+static const uint64_t SH_FLD_MMIO_CTL_WINID_LEN = 12335; // 1
+static const uint64_t SH_FLD_MMIO_DATA = 12336; // 1
+static const uint64_t SH_FLD_MMIO_DATA_LEN = 12337; // 1
+static const uint64_t SH_FLD_MMIO_ECC = 12338; // 1
+static const uint64_t SH_FLD_MMIO_ECC_LEN = 12339; // 1
+static const uint64_t SH_FLD_MMIO_HYP_RD_ADDR_ERR = 12340; // 2
+static const uint64_t SH_FLD_MMIO_HYP_WR_ADDR_ERR = 12341; // 2
+static const uint64_t SH_FLD_MMIO_LDST_TIMEOUT = 12342; // 1
+static const uint64_t SH_FLD_MMIO_LDST_TIMEOUT_LEN = 12343; // 1
+static const uint64_t SH_FLD_MMIO_NON8B_HYP_ERR = 12344; // 2
+static const uint64_t SH_FLD_MMIO_NON8B_OS_ERR = 12345; // 2
+static const uint64_t SH_FLD_MMIO_OS_RD_ADDR_ERR = 12346; // 2
+static const uint64_t SH_FLD_MMIO_OS_WR_ADDR_ERR = 12347; // 2
+static const uint64_t SH_FLD_MMIO_PG_REG_ACCESS = 12348; // 4
+static const uint64_t SH_FLD_MMIO_REQUEST_TIMEOUT = 12349; // 6
+static const uint64_t SH_FLD_MMR = 12350; // 1
+static const uint64_t SH_FLD_MMR_LEN = 12351; // 1
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_00 = 12352; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_00_LEN = 12353; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_01 = 12354; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_01_LEN = 12355; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_02 = 12356; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_02_LEN = 12357; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_03 = 12358; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_03_LEN = 12359; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_04 = 12360; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_04_LEN = 12361; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_05 = 12362; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_05_LEN = 12363; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_06 = 12364; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_06_LEN = 12365; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_07 = 12366; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_07_LEN = 12367; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_08 = 12368; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_08_LEN = 12369; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_09 = 12370; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_09_LEN = 12371; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_10 = 12372; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_10_LEN = 12373; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_11 = 12374; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_11_LEN = 12375; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_12 = 12376; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_12_LEN = 12377; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_13 = 12378; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_13_LEN = 12379; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_14 = 12380; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_14_LEN = 12381; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_15 = 12382; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_15_LEN = 12383; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_16 = 12384; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_16_LEN = 12385; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_17 = 12386; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_17_LEN = 12387; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_18 = 12388; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_18_LEN = 12389; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_19 = 12390; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_19_LEN = 12391; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_20 = 12392; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_20_LEN = 12393; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_21 = 12394; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_21_LEN = 12395; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_22 = 12396; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_22_LEN = 12397; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_23 = 12398; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_23_LEN = 12399; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_24 = 12400; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_24_LEN = 12401; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_25 = 12402; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_25_LEN = 12403; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_26 = 12404; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_26_LEN = 12405; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_27 = 12406; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_27_LEN = 12407; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_28 = 12408; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_28_LEN = 12409; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_29 = 12410; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_29_LEN = 12411; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_30 = 12412; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_30_LEN = 12413; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_31 = 12414; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_31_LEN = 12415; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_32 = 12416; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_32_LEN = 12417; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_33 = 12418; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_33_LEN = 12419; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_34 = 12420; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_34_LEN = 12421; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_35 = 12422; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_35_LEN = 12423; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_36 = 12424; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_36_LEN = 12425; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_37 = 12426; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_37_LEN = 12427; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_38 = 12428; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_38_LEN = 12429; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_39 = 12430; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_39_LEN = 12431; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_40 = 12432; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_40_LEN = 12433; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_41 = 12434; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_41_LEN = 12435; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_42 = 12436; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_42_LEN = 12437; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_43 = 12438; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_43_LEN = 12439; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_44 = 12440; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_44_LEN = 12441; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_45 = 12442; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_45_LEN = 12443; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_46 = 12444; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_46_LEN = 12445; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_47 = 12446; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_47_LEN = 12447; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_48 = 12448; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_48_LEN = 12449; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_49 = 12450; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_49_LEN = 12451; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_50 = 12452; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_50_LEN = 12453; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_51 = 12454; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_51_LEN = 12455; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_52 = 12456; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_52_LEN = 12457; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_53 = 12458; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_53_LEN = 12459; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_54 = 12460; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_54_LEN = 12461; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_55 = 12462; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_55_LEN = 12463; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_56 = 12464; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_56_LEN = 12465; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_57 = 12466; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_57_LEN = 12467; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_58 = 12468; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_58_LEN = 12469; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_59 = 12470; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_59_LEN = 12471; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_60 = 12472; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_60_LEN = 12473; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_61 = 12474; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_61_LEN = 12475; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_62 = 12476; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_62_LEN = 12477; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_63 = 12478; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_63_LEN = 12479; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_64 = 12480; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_64_LEN = 12481; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_65 = 12482; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_65_LEN = 12483; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_66 = 12484; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_66_LEN = 12485; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_67 = 12486; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_67_LEN = 12487; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_68 = 12488; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_68_LEN = 12489; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_69 = 12490; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_69_LEN = 12491; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_70 = 12492; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_70_LEN = 12493; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_71 = 12494; // 2
+static const uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_71_LEN = 12495; // 2
+static const uint64_t SH_FLD_MODE = 12496; // 153
+static const uint64_t SH_FLD_MODEREG_SPRC_LT0_SEL = 12497; // 24
+static const uint64_t SH_FLD_MODEREG_SPRC_LT1_SEL = 12498; // 24
+static const uint64_t SH_FLD_MODEREG_SPRC_LT2_SEL = 12499; // 24
+static const uint64_t SH_FLD_MODEREG_SPRC_LT3_SEL = 12500; // 24
+static const uint64_t SH_FLD_MODEREG_SPRC_LT4_SEL = 12501; // 24
+static const uint64_t SH_FLD_MODEREG_SPRC_LT5_SEL = 12502; // 24
+static const uint64_t SH_FLD_MODEREG_SPRC_LT6_SEL = 12503; // 24
+static const uint64_t SH_FLD_MODEREG_SPRC_LT7_SEL = 12504; // 24
+static const uint64_t SH_FLD_MODEREG_TFAC_ERR_INJ = 12505; // 24
+static const uint64_t SH_FLD_MODEREG_TFAC_ERR_INJ_LEN = 12506; // 24
+static const uint64_t SH_FLD_MODE_128K_VP = 12507; // 1
+static const uint64_t SH_FLD_MODE_LEN = 12508; // 151
+static const uint64_t SH_FLD_MODE_REGISTER_0_VALUE = 12509; // 64
+static const uint64_t SH_FLD_MODE_REGISTER_0_VALUE_LEN = 12510; // 64
+static const uint64_t SH_FLD_MODE_REGISTER_1_VALUE = 12511; // 64
+static const uint64_t SH_FLD_MODE_REGISTER_1_VALUE_LEN = 12512; // 64
+static const uint64_t SH_FLD_MODE_REGISTER_2_VALUE = 12513; // 64
+static const uint64_t SH_FLD_MODE_REGISTER_2_VALUE_LEN = 12514; // 64
+static const uint64_t SH_FLD_MODE_REGISTER_3_VALUE = 12515; // 64
+static const uint64_t SH_FLD_MODE_REGISTER_3_VALUE_LEN = 12516; // 64
+static const uint64_t SH_FLD_MODE_SEL = 12517; // 12
+static const uint64_t SH_FLD_MON = 12518; // 12
+static const uint64_t SH_FLD_MON_LEN = 12519; // 12
+static const uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS = 12520; // 1
+static const uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS_ENABLE = 12521; // 1
+static const uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS_LEN = 12522; // 1
+static const uint64_t SH_FLD_MOVE_TO_TB_CORE_ID = 12523; // 1
+static const uint64_t SH_FLD_MOVE_TO_TB_CORE_ID_LEN = 12524; // 1
+static const uint64_t SH_FLD_MOVE_TO_TB_ON_2X_SYNC_ENABLE = 12525; // 1
+static const uint64_t SH_FLD_MPR_PAGE = 12526; // 8
+static const uint64_t SH_FLD_MPR_PAGE_LEN = 12527; // 8
+static const uint64_t SH_FLD_MPR_PATTERN_BIT = 12528; // 8
+static const uint64_t SH_FLD_MPSS_DIS = 12529; // 1
+static const uint64_t SH_FLD_MPW1 = 12530; // 43
+static const uint64_t SH_FLD_MPW2 = 12531; // 43
+static const uint64_t SH_FLD_MPW3 = 12532; // 43
+static const uint64_t SH_FLD_MRBGP = 12533; // 15
+static const uint64_t SH_FLD_MRBGP_LEN = 12534; // 15
+static const uint64_t SH_FLD_MRBSP = 12535; // 15
+static const uint64_t SH_FLD_MRBSP_LEN = 12536; // 15
+static const uint64_t SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR = 12537; // 6
+static const uint64_t SH_FLD_MRG_BBRD_NBUF = 12538; // 3
+static const uint64_t SH_FLD_MRG_BBRD_NBUF_LEN = 12539; // 3
+static const uint64_t SH_FLD_MRG_COMMON_FATAL_ERROR = 12540; // 6
+static const uint64_t SH_FLD_MRG_CR_DIS = 12541; // 3
+static const uint64_t SH_FLD_MRG_CTLW_CR_DIS = 12542; // 3
+static const uint64_t SH_FLD_MRG_ECC_CORRECTABLE_ERROR = 12543; // 6
+static const uint64_t SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR = 12544; // 6
+static const uint64_t SH_FLD_MRG_IBRD_NBUF = 12545; // 3
+static const uint64_t SH_FLD_MRG_IBRD_NBUF_LEN = 12546; // 3
+static const uint64_t SH_FLD_MRG_IBWR_NBUF = 12547; // 3
+static const uint64_t SH_FLD_MRG_IBWR_NBUF_LEN = 12548; // 3
+static const uint64_t SH_FLD_MRG_MRT_ERROR = 12549; // 6
+static const uint64_t SH_FLD_MRG_OBRD_NBUF = 12550; // 3
+static const uint64_t SH_FLD_MRG_OBRD_NBUF_LEN = 12551; // 3
+static const uint64_t SH_FLD_MRG_PBTX_NBUF = 12552; // 3
+static const uint64_t SH_FLD_MRG_PBTX_NBUF_LEN = 12553; // 3
+static const uint64_t SH_FLD_MRG_RDBF_NBUF = 12554; // 3
+static const uint64_t SH_FLD_MRG_RDBF_NBUF_LEN = 12555; // 3
+static const uint64_t SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR = 12556; // 6
+static const uint64_t SH_FLD_MRS_CMD_DQ_OFF = 12557; // 8
+static const uint64_t SH_FLD_MRS_CMD_DQ_OFF_LEN = 12558; // 8
+static const uint64_t SH_FLD_MRS_CMD_DQ_ON = 12559; // 8
+static const uint64_t SH_FLD_MRS_CMD_DQ_ON_LEN = 12560; // 8
+static const uint64_t SH_FLD_MRT_ERR_NOT_VALID = 12561; // 1
+static const uint64_t SH_FLD_MRT_ERR_PSIZE = 12562; // 1
+static const uint64_t SH_FLD_MR_MASK_EN = 12563; // 8
+static const uint64_t SH_FLD_MR_MASK_EN_LEN = 12564; // 8
+static const uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1 = 12565; // 1
+static const uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1_LEN = 12566; // 1
+static const uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2 = 12567; // 1
+static const uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2_LEN = 12568; // 1
+static const uint64_t SH_FLD_MSADES_CLEAR_1 = 12569; // 1
+static const uint64_t SH_FLD_MSADES_CLEAR_2 = 12570; // 1
+static const uint64_t SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_1 = 12571; // 1
+static const uint64_t SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_2 = 12572; // 1
+static const uint64_t SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_1 = 12573; // 1
+static const uint64_t SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_2 = 12574; // 1
+static const uint64_t SH_FLD_MSADES_READ_EMPTY_PIB_1 = 12575; // 1
+static const uint64_t SH_FLD_MSADES_READ_EMPTY_PIB_2 = 12576; // 1
+static const uint64_t SH_FLD_MSADES_UNUSED_15_12 = 12577; // 1
+static const uint64_t SH_FLD_MSADES_UNUSED_15_12_LEN = 12578; // 1
+static const uint64_t SH_FLD_MSADES_UNUSED_31_28 = 12579; // 1
+static const uint64_t SH_FLD_MSADES_UNUSED_31_28_LEN = 12580; // 1
+static const uint64_t SH_FLD_MSADES_WRITE_FULL_PIB_1 = 12581; // 1
+static const uint64_t SH_FLD_MSADES_WRITE_FULL_PIB_2 = 12582; // 1
+static const uint64_t SH_FLD_MSADI_PIB_ERROR_1 = 12583; // 1
+static const uint64_t SH_FLD_MSADI_PIB_ERROR_2 = 12584; // 1
+static const uint64_t SH_FLD_MSADI_PIB_PENDING_1 = 12585; // 1
+static const uint64_t SH_FLD_MSADI_PIB_PENDING_2 = 12586; // 1
+static const uint64_t SH_FLD_MSADI_UNUSED_31_11 = 12587; // 4
+static const uint64_t SH_FLD_MSADI_UNUSED_31_11_LEN = 12588; // 4
+static const uint64_t SH_FLD_MSADI_UNUSED_7_3 = 12589; // 1
+static const uint64_t SH_FLD_MSADI_UNUSED_7_3_LEN = 12590; // 1
+static const uint64_t SH_FLD_MSADI_XUP_1 = 12591; // 1
+static const uint64_t SH_FLD_MSADI_XUP_2 = 12592; // 1
+static const uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1 = 12593; // 1
+static const uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1_LEN = 12594; // 1
+static const uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2 = 12595; // 1
+static const uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2_LEN = 12596; // 1
+static const uint64_t SH_FLD_MSBDES_CLEAR_1 = 12597; // 1
+static const uint64_t SH_FLD_MSBDES_CLEAR_2 = 12598; // 1
+static const uint64_t SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_1 = 12599; // 1
+static const uint64_t SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_2 = 12600; // 1
+static const uint64_t SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_1 = 12601; // 1
+static const uint64_t SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_2 = 12602; // 1
+static const uint64_t SH_FLD_MSBDES_READ_EMPTY_PIB_A_1 = 12603; // 1
+static const uint64_t SH_FLD_MSBDES_READ_EMPTY_PIB_A_2 = 12604; // 1
+static const uint64_t SH_FLD_MSBDES_UNUSED_15_12 = 12605; // 1
+static const uint64_t SH_FLD_MSBDES_UNUSED_15_12_LEN = 12606; // 1
+static const uint64_t SH_FLD_MSBDES_UNUSED_31_28 = 12607; // 1
+static const uint64_t SH_FLD_MSBDES_UNUSED_31_28_LEN = 12608; // 1
+static const uint64_t SH_FLD_MSBDES_WRITE_FULL_PIB_A_1 = 12609; // 1
+static const uint64_t SH_FLD_MSBDES_WRITE_FULL_PIB_A_2 = 12610; // 1
+static const uint64_t SH_FLD_MSBDIM1_ENABLE_ABORT = 12611; // 1
+static const uint64_t SH_FLD_MSBDIM1_ENABLE_ABORT_2 = 12612; // 1
+static const uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR = 12613; // 1
+static const uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR_2 = 12614; // 1
+static const uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING = 12615; // 1
+static const uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING_2 = 12616; // 1
+static const uint64_t SH_FLD_MSBDIM1_ENABLE_XDN = 12617; // 1
+static const uint64_t SH_FLD_MSBDIM1_ENABLE_XDN_2 = 12618; // 1
+static const uint64_t SH_FLD_MSBDI_LBUS_ERROR_1 = 12619; // 1
+static const uint64_t SH_FLD_MSBDI_LBUS_ERROR_2 = 12620; // 1
+static const uint64_t SH_FLD_MSBDI_LBUS_PENDING_1 = 12621; // 1
+static const uint64_t SH_FLD_MSBDI_LBUS_PENDING_2 = 12622; // 1
+static const uint64_t SH_FLD_MSBDI_XDN_1 = 12623; // 1
+static const uint64_t SH_FLD_MSBDI_XDN_2 = 12624; // 1
+static const uint64_t SH_FLD_MSBSWAP = 12625; // 4
+static const uint64_t SH_FLD_MSC_BUS0_STG0_SEL = 12626; // 1
+static const uint64_t SH_FLD_MSC_BUS0_STG0_SEL_LEN = 12627; // 1
+static const uint64_t SH_FLD_MSC_BUS0_STG1_SEL = 12628; // 1
+static const uint64_t SH_FLD_MSC_BUS0_STG2_SEL = 12629; // 1
+static const uint64_t SH_FLD_MSC_BUS1_STG0_SEL = 12630; // 1
+static const uint64_t SH_FLD_MSC_BUS1_STG0_SEL_LEN = 12631; // 1
+static const uint64_t SH_FLD_MSC_BUS1_STG1_SEL = 12632; // 1
+static const uint64_t SH_FLD_MSC_BUS1_STG2_SEL = 12633; // 1
+static const uint64_t SH_FLD_MSG_ADDR_ERR = 12634; // 12
+static const uint64_t SH_FLD_MSK = 12635; // 5
+static const uint64_t SH_FLD_MSK_LEN = 12636; // 5
+static const uint64_t SH_FLD_MSM_CURR_STATE_0 = 12637; // 2
+static const uint64_t SH_FLD_MSM_CURR_STATE_0_LEN = 12638; // 2
+static const uint64_t SH_FLD_MSM_CURR_STATE_1 = 12639; // 1
+static const uint64_t SH_FLD_MSM_CURR_STATE_1_LEN = 12640; // 1
+static const uint64_t SH_FLD_MSM_CURR_STATE_2 = 12641; // 1
+static const uint64_t SH_FLD_MSM_CURR_STATE_2_LEN = 12642; // 1
+static const uint64_t SH_FLD_MSM_CURR_STATE_3 = 12643; // 1
+static const uint64_t SH_FLD_MSM_CURR_STATE_3_LEN = 12644; // 1
+static const uint64_t SH_FLD_MSR_DR = 12645; // 256
+static const uint64_t SH_FLD_MSR_HV = 12646; // 256
+static const uint64_t SH_FLD_MSR_PE = 12647; // 8
+static const uint64_t SH_FLD_MSR_PR = 12648; // 256
+static const uint64_t SH_FLD_MSR_SF = 12649; // 256
+static const uint64_t SH_FLD_MSR_TA = 12650; // 256
+static const uint64_t SH_FLD_MSR_US = 12651; // 256
+static const uint64_t SH_FLD_MSR_UV = 12652; // 256
+static const uint64_t SH_FLD_MST_DIS_ABUSPAREN = 12653; // 1
+static const uint64_t SH_FLD_MST_DIS_BEPAREN = 12654; // 1
+static const uint64_t SH_FLD_MST_DIS_RDDBUSPAR = 12655; // 1
+static const uint64_t SH_FLD_MST_DIS_WRDBUSPAREN = 12656; // 1
+static const uint64_t SH_FLD_MST_SPARE = 12657; // 1
+static const uint64_t SH_FLD_MS_GROUP_CHIP = 12658; // 2
+static const uint64_t SH_FLD_MS_GROUP_CHIP_LEN = 12659; // 2
+static const uint64_t SH_FLD_MS_WAT_DEBUG_CONFIG_REG_ERROR = 12660; // 4
+static const uint64_t SH_FLD_MULTICAST1 = 12661; // 43
+static const uint64_t SH_FLD_MULTICAST1_LEN = 12662; // 43
+static const uint64_t SH_FLD_MULTICAST2 = 12663; // 43
+static const uint64_t SH_FLD_MULTICAST2_LEN = 12664; // 43
+static const uint64_t SH_FLD_MULTICAST3 = 12665; // 43
+static const uint64_t SH_FLD_MULTICAST3_LEN = 12666; // 43
+static const uint64_t SH_FLD_MULTICAST4 = 12667; // 43
+static const uint64_t SH_FLD_MULTICAST4_LEN = 12668; // 43
+static const uint64_t SH_FLD_MULTICAST_COMPARE_REGISTER = 12669; // 2
+static const uint64_t SH_FLD_MULTICAST_COMPARE_REGISTER_LEN = 12670; // 2
+static const uint64_t SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER = 12671; // 1
+static const uint64_t SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER_LEN = 12672; // 1
+static const uint64_t SH_FLD_MULTIHIT_CHK_DIS = 12673; // 1
+static const uint64_t SH_FLD_MULTIPLE_BAR = 12674; // 4
+static const uint64_t SH_FLD_MULTIPLE_DIR_ERRORS_DETECTED = 12675; // 12
+static const uint64_t SH_FLD_MULTIPLE_REQ = 12676; // 8
+static const uint64_t SH_FLD_MULTIPLE_REQ_SOURCE = 12677; // 8
+static const uint64_t SH_FLD_MULTIPLE_REQ_SOURCE_LEN = 12678; // 8
+static const uint64_t SH_FLD_MULT_REQ_ERR_MASK = 12679; // 8
+static const uint64_t SH_FLD_MUOP_ERROR_1 = 12680; // 4
+static const uint64_t SH_FLD_MUOP_ERROR_2 = 12681; // 4
+static const uint64_t SH_FLD_MUOP_ERROR_3 = 12682; // 4
+static const uint64_t SH_FLD_MUXEN = 12683; // 4
+static const uint64_t SH_FLD_MUXSEL = 12684; // 4
+static const uint64_t SH_FLD_MUXSEL_LEN = 12685; // 4
+static const uint64_t SH_FLD_M_0_STEP_ALIGN_FSM_STATE = 12686; // 1
+static const uint64_t SH_FLD_M_0_STEP_ALIGN_FSM_STATE_LEN = 12687; // 1
+static const uint64_t SH_FLD_M_1_STEP_ALIGN_FSM_STATE = 12688; // 1
+static const uint64_t SH_FLD_M_1_STEP_ALIGN_FSM_STATE_LEN = 12689; // 1
+static const uint64_t SH_FLD_M_CPS_ENABLE = 12690; // 1
+static const uint64_t SH_FLD_M_PATH_0_OSC_NOT_VALID = 12691; // 1
+static const uint64_t SH_FLD_M_PATH_0_PARITY = 12692; // 4
+static const uint64_t SH_FLD_M_PATH_0_STEP_ALIGN_THRESHOLD_ENABLE = 12693; // 1
+static const uint64_t SH_FLD_M_PATH_0_STEP_ALIGN_VALID_SWITCH = 12694; // 1
+static const uint64_t SH_FLD_M_PATH_0_STEP_CHECK = 12695; // 4
+static const uint64_t SH_FLD_M_PATH_0_STEP_CHECK_VALID = 12696; // 1
+static const uint64_t SH_FLD_M_PATH_0_STEP_CREATE_THRESHOLD_ENABLE = 12697; // 1
+static const uint64_t SH_FLD_M_PATH_0_SYNC_CREATE_COUNTER_ENABLE = 12698; // 1
+static const uint64_t SH_FLD_M_PATH_1_OSC_NOT_VALID = 12699; // 1
+static const uint64_t SH_FLD_M_PATH_1_PARITY = 12700; // 4
+static const uint64_t SH_FLD_M_PATH_1_STEP_ALIGN_THRESHOLD_ENABLE = 12701; // 1
+static const uint64_t SH_FLD_M_PATH_1_STEP_ALIGN_VALID_SWITCH = 12702; // 1
+static const uint64_t SH_FLD_M_PATH_1_STEP_CHECK = 12703; // 4
+static const uint64_t SH_FLD_M_PATH_1_STEP_CHECK_VALID = 12704; // 1
+static const uint64_t SH_FLD_M_PATH_1_STEP_CREATE_THRESHOLD_ENABLE = 12705; // 1
+static const uint64_t SH_FLD_M_PATH_1_SYNC_CREATE_COUNTER_ENABLE = 12706; // 1
+static const uint64_t SH_FLD_M_PATH_CLOCK_OFF_ENABLE = 12707; // 1
+static const uint64_t SH_FLD_M_PATH_SELECT = 12708; // 1
+static const uint64_t SH_FLD_M_PATH_SWITCH_TRIGGER = 12709; // 1
+static const uint64_t SH_FLD_N0DGD = 12710; // 12
+static const uint64_t SH_FLD_N0REQ = 12711; // 12
+static const uint64_t SH_FLD_N0RSP = 12712; // 12
+static const uint64_t SH_FLD_N1DGD = 12713; // 12
+static const uint64_t SH_FLD_N1REQ = 12714; // 12
+static const uint64_t SH_FLD_N1RSP = 12715; // 12
+static const uint64_t SH_FLD_NACK_RECEIVED_ERROR_0 = 12716; // 4
+static const uint64_t SH_FLD_NACK_RECEIVED_ERROR_1 = 12717; // 2
+static const uint64_t SH_FLD_NACK_RECEIVED_ERROR_2 = 12718; // 2
+static const uint64_t SH_FLD_NACK_RECEIVED_ERROR_3 = 12719; // 2
+static const uint64_t SH_FLD_NB_CLEAN_SLOT = 12720; // 6
+static const uint64_t SH_FLD_NB_CLEAN_SLOT_LEN = 12721; // 6
+static const uint64_t SH_FLD_NB_WRITE_SLOT = 12722; // 6
+static const uint64_t SH_FLD_NB_WRITE_SLOT_LEN = 12723; // 6
+static const uint64_t SH_FLD_NCU_POWERBUS_DATA_TIMEOUT = 12724; // 12
+static const uint64_t SH_FLD_NCU_PURGE = 12725; // 12
+static const uint64_t SH_FLD_NCU_PURGE_ABORT = 12726; // 12
+static const uint64_t SH_FLD_NCU_PURGE_DONE = 12727; // 24
+static const uint64_t SH_FLD_NCU_SNP_TLBIE_CNT_THRESH = 12728; // 1
+static const uint64_t SH_FLD_NCU_SNP_TLBIE_CNT_THRESH_LEN = 12729; // 1
+static const uint64_t SH_FLD_NCU_SNP_TLBIE_DEC_RATE = 12730; // 1
+static const uint64_t SH_FLD_NCU_SNP_TLBIE_DEC_RATE_LEN = 12731; // 1
+static const uint64_t SH_FLD_NCU_SNP_TLBIE_INC_RATE = 12732; // 1
+static const uint64_t SH_FLD_NCU_SNP_TLBIE_INC_RATE_LEN = 12733; // 1
+static const uint64_t SH_FLD_NCU_SNP_TLBIE_PACING_CNT_EN = 12734; // 1
+static const uint64_t SH_FLD_NCU_TLBIE_QUIESCE = 12735; // 12
+static const uint64_t SH_FLD_NDL = 12736; // 6
+static const uint64_t SH_FLD_NDLMUX_BRK0TO2 = 12737; // 1
+static const uint64_t SH_FLD_NDLMUX_BRK0TO2_LEN = 12738; // 1
+static const uint64_t SH_FLD_NDL_BRK0_NOSTALL = 12739; // 1
+static const uint64_t SH_FLD_NDL_BRK0_STALL = 12740; // 1
+static const uint64_t SH_FLD_NDL_BRK1_NOSTALL = 12741; // 1
+static const uint64_t SH_FLD_NDL_BRK1_STALL = 12742; // 1
+static const uint64_t SH_FLD_NDL_BRK2_NOSTALL = 12743; // 1
+static const uint64_t SH_FLD_NDL_BRK2_STALL = 12744; // 1
+static const uint64_t SH_FLD_NDL_BRK3_NOSTALL = 12745; // 1
+static const uint64_t SH_FLD_NDL_BRK3_STALL = 12746; // 1
+static const uint64_t SH_FLD_NDL_BRK4_NOSTALL = 12747; // 1
+static const uint64_t SH_FLD_NDL_BRK4_STALL = 12748; // 1
+static const uint64_t SH_FLD_NDL_BRK5_NOSTALL = 12749; // 1
+static const uint64_t SH_FLD_NDL_BRK5_STALL = 12750; // 1
+static const uint64_t SH_FLD_NDL_LEN = 12751; // 6
+static const uint64_t SH_FLD_NDL_PRI_PARITY_ENA = 12752; // 6
+static const uint64_t SH_FLD_NDL_RX_PARITY_ENA = 12753; // 6
+static const uint64_t SH_FLD_NDL_TX_PARITY_ENA = 12754; // 6
+static const uint64_t SH_FLD_NEAR_NODAL_EPSILON = 12755; // 8
+static const uint64_t SH_FLD_NEAR_NODAL_EPSILON_LEN = 12756; // 8
+static const uint64_t SH_FLD_NEST_DBG_SEL_IN = 12757; // 8
+static const uint64_t SH_FLD_NEST_DBG_SEL_WRT = 12758; // 8
+static const uint64_t SH_FLD_NEST_LIMIT = 12759; // 24
+static const uint64_t SH_FLD_NEST_LIMIT_LEN = 12760; // 24
+static const uint64_t SH_FLD_NETWORK_RESET_OCCURRED = 12761; // 30
+static const uint64_t SH_FLD_NEXT_CAL_LANE_SEL = 12762; // 68
+static const uint64_t SH_FLD_NEXT_RANK = 12763; // 8
+static const uint64_t SH_FLD_NEXT_RANK_LEN = 12764; // 8
+static const uint64_t SH_FLD_NEXT_RANK_PAIR = 12765; // 8
+static const uint64_t SH_FLD_NEXT_RANK_PAIR_LEN = 12766; // 8
+static const uint64_t SH_FLD_NFIRACTION0 = 12767; // 9
+static const uint64_t SH_FLD_NFIRACTION0_LEN = 12768; // 9
+static const uint64_t SH_FLD_NFIRACTION1 = 12769; // 9
+static const uint64_t SH_FLD_NFIRACTION1_LEN = 12770; // 9
+static const uint64_t SH_FLD_NFIRMASK = 12771; // 9
+static const uint64_t SH_FLD_NFIRMASK_LEN = 12772; // 9
+static const uint64_t SH_FLD_NFIRNFIR = 12773; // 9
+static const uint64_t SH_FLD_NFIRNFIR_LEN = 12774; // 9
+static const uint64_t SH_FLD_NMCMD = 12775; // 6
+static const uint64_t SH_FLD_NMCMD_LEN = 12776; // 6
+static const uint64_t SH_FLD_NMEXCMD = 12777; // 6
+static const uint64_t SH_FLD_NMEXCMD_LEN = 12778; // 6
+static const uint64_t SH_FLD_NMMU = 12779; // 3
+static const uint64_t SH_FLD_NMMU_LOCAL_XSTOP = 12780; // 1
+static const uint64_t SH_FLD_NONSLS_CNTR_TAP_PTS = 12781; // 4
+static const uint64_t SH_FLD_NONSLS_CNTR_TAP_PTS_LEN = 12782; // 4
+static const uint64_t SH_FLD_NONZERO_CSB_CC = 12783; // 1
+static const uint64_t SH_FLD_NOTIFY_FAILED_ERR = 12784; // 2
+static const uint64_t SH_FLD_NOT_TRIGGER_MODE1 = 12785; // 86
+static const uint64_t SH_FLD_NOT_TRIGGER_MODE2 = 12786; // 86
+static const uint64_t SH_FLD_NOT_USED_0 = 12787; // 2
+static const uint64_t SH_FLD_NOT_USED_0_LEN = 12788; // 2
+static const uint64_t SH_FLD_NOT_USED_1 = 12789; // 1
+static const uint64_t SH_FLD_NOT_USED_1_LEN = 12790; // 1
+static const uint64_t SH_FLD_NOT_USED_2 = 12791; // 1
+static const uint64_t SH_FLD_NOT_USED_2_LEN = 12792; // 1
+static const uint64_t SH_FLD_NOT_USED_3 = 12793; // 1
+static const uint64_t SH_FLD_NOT_USED_3_LEN = 12794; // 1
+static const uint64_t SH_FLD_NO_WAIT_ON_CLK_CMD = 12795; // 43
+static const uint64_t SH_FLD_NPU_LXSTOP_ERR_DET = 12796; // 1
+static const uint64_t SH_FLD_NPU_TRANSPORT_SWAP = 12797; // 2
+static const uint64_t SH_FLD_NR_OF_FRAMES = 12798; // 1
+static const uint64_t SH_FLD_NSEG_MAIN_EN = 12799; // 6
+static const uint64_t SH_FLD_NSEG_MAIN_EN_LEN = 12800; // 6
+static const uint64_t SH_FLD_NSEG_MARGINPD_EN = 12801; // 6
+static const uint64_t SH_FLD_NSEG_MARGINPD_EN_LEN = 12802; // 6
+static const uint64_t SH_FLD_NSEG_MARGINPU_EN = 12803; // 6
+static const uint64_t SH_FLD_NSEG_MARGINPU_EN_LEN = 12804; // 6
+static const uint64_t SH_FLD_NSEG_POST_EN = 12805; // 2
+static const uint64_t SH_FLD_NSEG_POST_EN_LEN = 12806; // 2
+static const uint64_t SH_FLD_NSEG_POST_SEL = 12807; // 2
+static const uint64_t SH_FLD_NSEG_POST_SEL_LEN = 12808; // 2
+static const uint64_t SH_FLD_NSEG_PRE_EN = 12809; // 6
+static const uint64_t SH_FLD_NSEG_PRE_EN_LEN = 12810; // 6
+static const uint64_t SH_FLD_NSEG_PRE_SEL = 12811; // 6
+static const uint64_t SH_FLD_NSEG_PRE_SEL_LEN = 12812; // 6
+static const uint64_t SH_FLD_NSL_FILL_COUNT = 12813; // 43
+static const uint64_t SH_FLD_NSL_FILL_COUNT_LEN = 12814; // 43
+static const uint64_t SH_FLD_NSQ_LFSR_CNTL = 12815; // 8
+static const uint64_t SH_FLD_NSQ_LFSR_CNTL_LEN = 12816; // 8
+static const uint64_t SH_FLD_NTLR_PAUSE_THRESH = 12817; // 3
+static const uint64_t SH_FLD_NTLR_PAUSE_THRESH_LEN = 12818; // 3
+static const uint64_t SH_FLD_NTLW_PAUSE_THRESH = 12819; // 3
+static const uint64_t SH_FLD_NTLW_PAUSE_THRESH_LEN = 12820; // 3
+static const uint64_t SH_FLD_NTL_0 = 12821; // 48
+static const uint64_t SH_FLD_NTL_1 = 12822; // 48
+static const uint64_t SH_FLD_NTL_10 = 12823; // 48
+static const uint64_t SH_FLD_NTL_11 = 12824; // 48
+static const uint64_t SH_FLD_NTL_12 = 12825; // 48
+static const uint64_t SH_FLD_NTL_13 = 12826; // 48
+static const uint64_t SH_FLD_NTL_14 = 12827; // 48
+static const uint64_t SH_FLD_NTL_15 = 12828; // 48
+static const uint64_t SH_FLD_NTL_16 = 12829; // 48
+static const uint64_t SH_FLD_NTL_17 = 12830; // 48
+static const uint64_t SH_FLD_NTL_18 = 12831; // 48
+static const uint64_t SH_FLD_NTL_19 = 12832; // 48
+static const uint64_t SH_FLD_NTL_2 = 12833; // 48
+static const uint64_t SH_FLD_NTL_20 = 12834; // 48
+static const uint64_t SH_FLD_NTL_21 = 12835; // 48
+static const uint64_t SH_FLD_NTL_22 = 12836; // 48
+static const uint64_t SH_FLD_NTL_23 = 12837; // 48
+static const uint64_t SH_FLD_NTL_24 = 12838; // 48
+static const uint64_t SH_FLD_NTL_25 = 12839; // 48
+static const uint64_t SH_FLD_NTL_26 = 12840; // 48
+static const uint64_t SH_FLD_NTL_27 = 12841; // 48
+static const uint64_t SH_FLD_NTL_28 = 12842; // 48
+static const uint64_t SH_FLD_NTL_29 = 12843; // 48
+static const uint64_t SH_FLD_NTL_3 = 12844; // 48
+static const uint64_t SH_FLD_NTL_30 = 12845; // 48
+static const uint64_t SH_FLD_NTL_31 = 12846; // 48
+static const uint64_t SH_FLD_NTL_32 = 12847; // 48
+static const uint64_t SH_FLD_NTL_33 = 12848; // 48
+static const uint64_t SH_FLD_NTL_34 = 12849; // 48
+static const uint64_t SH_FLD_NTL_35 = 12850; // 48
+static const uint64_t SH_FLD_NTL_36 = 12851; // 48
+static const uint64_t SH_FLD_NTL_37 = 12852; // 48
+static const uint64_t SH_FLD_NTL_38 = 12853; // 48
+static const uint64_t SH_FLD_NTL_39 = 12854; // 48
+static const uint64_t SH_FLD_NTL_4 = 12855; // 48
+static const uint64_t SH_FLD_NTL_40 = 12856; // 48
+static const uint64_t SH_FLD_NTL_41 = 12857; // 48
+static const uint64_t SH_FLD_NTL_42 = 12858; // 48
+static const uint64_t SH_FLD_NTL_43 = 12859; // 48
+static const uint64_t SH_FLD_NTL_44 = 12860; // 48
+static const uint64_t SH_FLD_NTL_45 = 12861; // 48
+static const uint64_t SH_FLD_NTL_46 = 12862; // 48
+static const uint64_t SH_FLD_NTL_47 = 12863; // 48
+static const uint64_t SH_FLD_NTL_48 = 12864; // 48
+static const uint64_t SH_FLD_NTL_49 = 12865; // 48
+static const uint64_t SH_FLD_NTL_5 = 12866; // 48
+static const uint64_t SH_FLD_NTL_50 = 12867; // 48
+static const uint64_t SH_FLD_NTL_51 = 12868; // 48
+static const uint64_t SH_FLD_NTL_52 = 12869; // 48
+static const uint64_t SH_FLD_NTL_53 = 12870; // 48
+static const uint64_t SH_FLD_NTL_54 = 12871; // 48
+static const uint64_t SH_FLD_NTL_55 = 12872; // 48
+static const uint64_t SH_FLD_NTL_56 = 12873; // 48
+static const uint64_t SH_FLD_NTL_57 = 12874; // 48
+static const uint64_t SH_FLD_NTL_58 = 12875; // 48
+static const uint64_t SH_FLD_NTL_59 = 12876; // 48
+static const uint64_t SH_FLD_NTL_6 = 12877; // 48
+static const uint64_t SH_FLD_NTL_60 = 12878; // 48
+static const uint64_t SH_FLD_NTL_61 = 12879; // 48
+static const uint64_t SH_FLD_NTL_62 = 12880; // 48
+static const uint64_t SH_FLD_NTL_63 = 12881; // 48
+static const uint64_t SH_FLD_NTL_7 = 12882; // 48
+static const uint64_t SH_FLD_NTL_8 = 12883; // 48
+static const uint64_t SH_FLD_NTL_9 = 12884; // 48
+static const uint64_t SH_FLD_NTL_ARRAY_CE = 12885; // 1
+static const uint64_t SH_FLD_NTL_ARRAY_DATA_SUE = 12886; // 1
+static const uint64_t SH_FLD_NTL_ARRAY_DATA_UE = 12887; // 1
+static const uint64_t SH_FLD_NTL_ARRAY_HDR_UE = 12888; // 1
+static const uint64_t SH_FLD_NTL_LMD_POISON = 12889; // 1
+static const uint64_t SH_FLD_NTL_LOGIC_ERR = 12890; // 1
+static const uint64_t SH_FLD_NTL_NVL_CONFIG_ERR = 12891; // 1
+static const uint64_t SH_FLD_NTL_NVL_CRC_ERR = 12892; // 1
+static const uint64_t SH_FLD_NTL_NVL_DATA_PERR = 12893; // 1
+static const uint64_t SH_FLD_NTL_NVL_FLIT_PERR = 12894; // 1
+static const uint64_t SH_FLD_NTL_NVL_PKT_MALFOR = 12895; // 1
+static const uint64_t SH_FLD_NTL_NVL_PKT_UNSUPPORTED = 12896; // 1
+static const uint64_t SH_FLD_NTL_PRI_ERR = 12897; // 1
+static const uint64_t SH_FLD_NTL_RESET = 12898; // 6
+static const uint64_t SH_FLD_NTL_RESET_LEN = 12899; // 6
+static const uint64_t SH_FLD_NTTM_MODE = 12900; // 2
+static const uint64_t SH_FLD_NTTM_RW_DATA_DLY = 12901; // 2
+static const uint64_t SH_FLD_NTTM_RW_DATA_DLY_LEN = 12902; // 2
+static const uint64_t SH_FLD_NULL_MSR_LP = 12903; // 46
+static const uint64_t SH_FLD_NULL_MSR_SIBRC = 12904; // 46
+static const uint64_t SH_FLD_NULL_MSR_SIBRC_LEN = 12905; // 46
+static const uint64_t SH_FLD_NULL_MSR_WE = 12906; // 46
+static const uint64_t SH_FLD_NUM_BLOCKS = 12907; // 12
+static const uint64_t SH_FLD_NUM_BLOCKS_LEN = 12908; // 12
+static const uint64_t SH_FLD_NUM_CLEAN = 12909; // 8
+static const uint64_t SH_FLD_NUM_CLEAN_LEN = 12910; // 8
+static const uint64_t SH_FLD_NUM_CL_ACTIVE = 12911; // 8
+static const uint64_t SH_FLD_NUM_CL_ACTIVE_LEN = 12912; // 8
+static const uint64_t SH_FLD_NUM_HA_RSVD = 12913; // 8
+static const uint64_t SH_FLD_NUM_HA_RSVD_LEN = 12914; // 8
+static const uint64_t SH_FLD_NUM_HA_RSVD_SEL = 12915; // 8
+static const uint64_t SH_FLD_NUM_HA_RSVD_SEL_LEN = 12916; // 8
+static const uint64_t SH_FLD_NUM_HPC_RD_RSVD = 12917; // 8
+static const uint64_t SH_FLD_NUM_HPC_RD_RSVD_LEN = 12918; // 8
+static const uint64_t SH_FLD_NUM_HTM_RSVD = 12919; // 8
+static const uint64_t SH_FLD_NUM_HTM_RSVD_LEN = 12920; // 8
+static const uint64_t SH_FLD_NUM_HTM_RSVD_SEL = 12921; // 8
+static const uint64_t SH_FLD_NUM_HTM_RSVD_SEL_LEN = 12922; // 8
+static const uint64_t SH_FLD_NUM_RMW_BUF = 12923; // 8
+static const uint64_t SH_FLD_NUM_RMW_BUF_LEN = 12924; // 8
+static const uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD = 12925; // 8
+static const uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_LEN = 12926; // 8
+static const uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_SEL = 12927; // 8
+static const uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_SEL_LEN = 12928; // 8
+static const uint64_t SH_FLD_NUM_VALID_SAMPLES = 12929; // 8
+static const uint64_t SH_FLD_NUM_VALID_SAMPLES_LEN = 12930; // 8
+static const uint64_t SH_FLD_NV0_NPU_ENABLED = 12931; // 2
+static const uint64_t SH_FLD_NV1_NPU_ENABLED = 12932; // 2
+static const uint64_t SH_FLD_NV2_NPU_ENABLED = 12933; // 2
+static const uint64_t SH_FLD_NVBE = 12934; // 24
+static const uint64_t SH_FLD_NVDGD0 = 12935; // 3
+static const uint64_t SH_FLD_NVDGD1 = 12936; // 3
+static const uint64_t SH_FLD_NVREQ0 = 12937; // 3
+static const uint64_t SH_FLD_NVREQ1 = 12938; // 3
+static const uint64_t SH_FLD_NVRS0 = 12939; // 3
+static const uint64_t SH_FLD_NVRS1 = 12940; // 3
+static const uint64_t SH_FLD_NV_RESP_RATE1 = 12941; // 12
+static const uint64_t SH_FLD_NV_RESP_RATE1_LEN = 12942; // 12
+static const uint64_t SH_FLD_NV_RESP_RATE2 = 12943; // 12
+static const uint64_t SH_FLD_NV_RESP_RATE2_LEN = 12944; // 12
+static const uint64_t SH_FLD_NX0_LXSTOP_ERR_DET = 12945; // 1
+static const uint64_t SH_FLD_NXCQ_ERAT_ARRAY_ACTION = 12946; // 1
+static const uint64_t SH_FLD_NXCQ_ERAT_ARRAY_ENABLE = 12947; // 1
+static const uint64_t SH_FLD_NXCQ_ERAT_ARRAY_SELECT = 12948; // 1
+static const uint64_t SH_FLD_NXCQ_ERAT_ARRAY_SELECT_LEN = 12949; // 1
+static const uint64_t SH_FLD_NXCQ_ERAT_ARRAY_TYPE = 12950; // 1
+static const uint64_t SH_FLD_NXCQ_HANG_SM_ON_ARE = 12951; // 1
+static const uint64_t SH_FLD_NXCQ_HANG_SM_ON_LINK_FAIL = 12952; // 1
+static const uint64_t SH_FLD_NXCQ_INJECT_MODE = 12953; // 2
+static const uint64_t SH_FLD_NXCQ_INJECT_MODE_LEN = 12954; // 2
+static const uint64_t SH_FLD_NXCQ_INJECT_TYPE = 12955; // 2
+static const uint64_t SH_FLD_NXCQ_INJECT_TYPE_LEN = 12956; // 2
+static const uint64_t SH_FLD_NXCQ_PBCQ_ARRAY = 12957; // 2
+static const uint64_t SH_FLD_NXCQ_PBCQ_ARRAY_LEN = 12958; // 2
+static const uint64_t SH_FLD_NXCQ_PBCQ_INJECT_ENABLE = 12959; // 2
+static const uint64_t SH_FLD_NXCQ_RNG_INJECT_ACTION = 12960; // 1
+static const uint64_t SH_FLD_NXCQ_RNG_INJECT_ENABLE = 12961; // 1
+static const uint64_t SH_FLD_NXCQ_TRACE_CNTL = 12962; // 2
+static const uint64_t SH_FLD_NXCQ_TRACE_CNTL_LEN = 12963; // 2
+static const uint64_t SH_FLD_NXPBXPT_PBRCV_ECC_CE_ERRHOLD = 12964; // 2
+static const uint64_t SH_FLD_NXPBXPT_PBRCV_ECC_SUE_ERRHOLD = 12965; // 2
+static const uint64_t SH_FLD_NXPBXPT_PBRCV_ECC_UE_ERRHOLD = 12966; // 2
+static const uint64_t SH_FLD_NXPBXPT_PBRCV_LNK_RSP_ECC_SUE_ERRHOLD = 12967; // 2
+static const uint64_t SH_FLD_NXPBXPT_PBRCV_LNK_RSP_ECC_UE_ERRHOLD = 12968; // 2
+static const uint64_t SH_FLD_NX_DATA_RTAG_PARITY_ERRHOLD = 12969; // 2
+static const uint64_t SH_FLD_NX_FREEZE_MODES = 12970; // 2
+static const uint64_t SH_FLD_NX_FREEZE_MODES_LEN = 12971; // 2
+static const uint64_t SH_FLD_NX_LOCAL_XSTOP = 12972; // 2
+static const uint64_t SH_FLD_NX_RAND_NUM_GEN_LOCK = 12973; // 1
+static const uint64_t SH_FLD_O = 12974; // 1
+static const uint64_t SH_FLD_O2SCMD_A_N_RESERVED_0 = 12975; // 4
+static const uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_1 = 12976; // 4
+static const uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 = 12977; // 4
+static const uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN = 12978; // 4
+static const uint64_t SH_FLD_O2SST_A_N_RESERVED_1_4 = 12979; // 4
+static const uint64_t SH_FLD_O2SST_A_N_RESERVED_1_4_LEN = 12980; // 4
+static const uint64_t SH_FLD_O2SST_A_N_RESERVED_6 = 12981; // 4
+static const uint64_t SH_FLD_O2S_BRIDGE_ENABLE_A_N = 12982; // 4
+static const uint64_t SH_FLD_O2S_CLEAR_STICKY_BITS_A_N = 12983; // 4
+static const uint64_t SH_FLD_O2S_CLOCK_DIVIDER_A_N = 12984; // 4
+static const uint64_t SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN = 12985; // 4
+static const uint64_t SH_FLD_O2S_CPHA_A_N = 12986; // 4
+static const uint64_t SH_FLD_O2S_CPOL_A_N = 12987; // 4
+static const uint64_t SH_FLD_O2S_FRAME_SIZE_A_N = 12988; // 4
+static const uint64_t SH_FLD_O2S_FRAME_SIZE_A_N_LEN = 12989; // 4
+static const uint64_t SH_FLD_O2S_FSM_ERR_A_N = 12990; // 4
+static const uint64_t SH_FLD_O2S_INTER_FRAME_DELAY_A_N = 12991; // 4
+static const uint64_t SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN = 12992; // 4
+static const uint64_t SH_FLD_O2S_IN_COUNT1_A_N = 12993; // 4
+static const uint64_t SH_FLD_O2S_IN_COUNT1_A_N_LEN = 12994; // 4
+static const uint64_t SH_FLD_O2S_IN_COUNT2_A_N = 12995; // 4
+static const uint64_t SH_FLD_O2S_IN_COUNT2_A_N_LEN = 12996; // 4
+static const uint64_t SH_FLD_O2S_IN_DELAY1_A_N = 12997; // 4
+static const uint64_t SH_FLD_O2S_IN_DELAY1_A_N_LEN = 12998; // 4
+static const uint64_t SH_FLD_O2S_IN_DELAY2_A_N = 12999; // 4
+static const uint64_t SH_FLD_O2S_IN_DELAY2_A_N_LEN = 13000; // 4
+static const uint64_t SH_FLD_O2S_NR_OF_FRAMES_A_N = 13001; // 4
+static const uint64_t SH_FLD_O2S_ONGOING_A_N = 13002; // 4
+static const uint64_t SH_FLD_O2S_OUT_COUNT1_A_N = 13003; // 4
+static const uint64_t SH_FLD_O2S_OUT_COUNT1_A_N_LEN = 13004; // 4
+static const uint64_t SH_FLD_O2S_OUT_COUNT2_A_N = 13005; // 4
+static const uint64_t SH_FLD_O2S_OUT_COUNT2_A_N_LEN = 13006; // 4
+static const uint64_t SH_FLD_O2S_RDATA_A_N = 13007; // 4
+static const uint64_t SH_FLD_O2S_RDATA_A_N_LEN = 13008; // 4
+static const uint64_t SH_FLD_O2S_WDATA_A_N = 13009; // 4
+static const uint64_t SH_FLD_O2S_WDATA_A_N_LEN = 13010; // 4
+static const uint64_t SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N = 13011; // 4
+static const uint64_t SH_FLD_OBUF_ABANK = 13012; // 3
+static const uint64_t SH_FLD_OBUF_ABANK_LEN = 13013; // 3
+static const uint64_t SH_FLD_OBUF_AIDX = 13014; // 3
+static const uint64_t SH_FLD_OBUF_AIDX_LEN = 13015; // 3
+static const uint64_t SH_FLD_OBUF_RSRC = 13016; // 3
+static const uint64_t SH_FLD_OBUF_RSRC_LEN = 13017; // 3
+static const uint64_t SH_FLD_OBUF_WSRC = 13018; // 3
+static const uint64_t SH_FLD_OBUF_WSRC_LEN = 13019; // 3
+static const uint64_t SH_FLD_OBWR_MASK = 13020; // 3
+static const uint64_t SH_FLD_OBWR_MASK_LEN = 13021; // 3
+static const uint64_t SH_FLD_OCB_DB_OCI_READ_DATA_PARITY = 13022; // 1
+static const uint64_t SH_FLD_OCB_DB_OCI_READ_DATA_PARITY_MASK = 13023; // 1
+static const uint64_t SH_FLD_OCB_DB_OCI_SLAVE_ERROR = 13024; // 1
+static const uint64_t SH_FLD_OCB_DB_OCI_SLAVE_ERROR_MASK = 13025; // 1
+static const uint64_t SH_FLD_OCB_DB_OCI_TIMEOUT = 13026; // 1
+static const uint64_t SH_FLD_OCB_DB_OCI_TIMEOUT_MASK = 13027; // 1
+static const uint64_t SH_FLD_OCB_DB_PIB_DATA_PARITY_ERR = 13028; // 1
+static const uint64_t SH_FLD_OCB_DB_PIB_DATA_PARITY_ERR_MASK = 13029; // 1
+static const uint64_t SH_FLD_OCB_ERROR = 13030; // 1
+static const uint64_t SH_FLD_OCB_ERROR_MASK = 13031; // 1
+static const uint64_t SH_FLD_OCB_IDC0_ERROR = 13032; // 1
+static const uint64_t SH_FLD_OCB_IDC0_ERROR_MASK = 13033; // 1
+static const uint64_t SH_FLD_OCB_IDC1_ERROR = 13034; // 1
+static const uint64_t SH_FLD_OCB_IDC1_ERROR_MASK = 13035; // 1
+static const uint64_t SH_FLD_OCB_IDC2_ERROR = 13036; // 1
+static const uint64_t SH_FLD_OCB_IDC2_ERROR_MASK = 13037; // 1
+static const uint64_t SH_FLD_OCB_IDC3_ERROR = 13038; // 1
+static const uint64_t SH_FLD_OCB_IDC3_ERROR_MASK = 13039; // 1
+static const uint64_t SH_FLD_OCB_OCISLV_ERR = 13040; // 1
+static const uint64_t SH_FLD_OCB_OCISLV_ERR_LEN = 13041; // 1
+static const uint64_t SH_FLD_OCB_PIB_ADDR_PARITY_ERR = 13042; // 1
+static const uint64_t SH_FLD_OCB_PIB_ADDR_PARITY_ERR_MASK = 13043; // 1
+static const uint64_t SH_FLD_OCC_ACTION_SET = 13044; // 1
+static const uint64_t SH_FLD_OCC_ACTION_SET_LEN = 13045; // 1
+static const uint64_t SH_FLD_OCC_ERROR = 13046; // 1
+static const uint64_t SH_FLD_OCC_FLAGS = 13047; // 1
+static const uint64_t SH_FLD_OCC_FLAGS_LEN = 13048; // 1
+static const uint64_t SH_FLD_OCC_HEARTBEAT_COUNT = 13049; // 7
+static const uint64_t SH_FLD_OCC_HEARTBEAT_COUNT_LEN = 13050; // 7
+static const uint64_t SH_FLD_OCC_HEARTBEAT_EN = 13051; // 1
+static const uint64_t SH_FLD_OCC_HEARTBEAT_ENABLE = 13052; // 6
+static const uint64_t SH_FLD_OCC_HEARTBEAT_LOSS = 13053; // 6
+static const uint64_t SH_FLD_OCC_HEARTBEAT_LOST = 13054; // 12
+static const uint64_t SH_FLD_OCC_MALF_ALERT = 13055; // 1
+static const uint64_t SH_FLD_OCC_SCRATCH_N = 13056; // 3
+static const uint64_t SH_FLD_OCC_SCRATCH_N_LEN = 13057; // 3
+static const uint64_t SH_FLD_OCC_SPCL_TIMEOUT_ADDR = 13058; // 1
+static const uint64_t SH_FLD_OCC_SPCL_TIMEOUT_ADDR_LEN = 13059; // 1
+static const uint64_t SH_FLD_OCC_SPECIAL_WKUP = 13060; // 30
+static const uint64_t SH_FLD_OCC_STRM0_PULL = 13061; // 1
+static const uint64_t SH_FLD_OCC_STRM0_PUSH = 13062; // 1
+static const uint64_t SH_FLD_OCC_STRM1_PULL = 13063; // 1
+static const uint64_t SH_FLD_OCC_STRM1_PUSH = 13064; // 1
+static const uint64_t SH_FLD_OCC_STRM2_PULL = 13065; // 1
+static const uint64_t SH_FLD_OCC_STRM2_PUSH = 13066; // 1
+static const uint64_t SH_FLD_OCC_STRM3_PULL = 13067; // 1
+static const uint64_t SH_FLD_OCC_STRM3_PUSH = 13068; // 1
+static const uint64_t SH_FLD_OCC_TIMER0 = 13069; // 1
+static const uint64_t SH_FLD_OCC_TIMER1 = 13070; // 1
+static const uint64_t SH_FLD_OCC_TRACE_MUX_SEL = 13071; // 1
+static const uint64_t SH_FLD_OCC_TRACE_MUX_SEL_LEN = 13072; // 1
+static const uint64_t SH_FLD_OCICFG_RESERVED_20 = 13073; // 1
+static const uint64_t SH_FLD_OCICFG_RESERVED_23 = 13074; // 1
+static const uint64_t SH_FLD_OCISLV_FAIRNESS_MASK = 13075; // 1
+static const uint64_t SH_FLD_OCISLV_FAIRNESS_MASK_LEN = 13076; // 1
+static const uint64_t SH_FLD_OCISLV_REREQ_HANG_DIV = 13077; // 1
+static const uint64_t SH_FLD_OCISLV_REREQ_HANG_DIV_LEN = 13078; // 1
+static const uint64_t SH_FLD_OCI_APAR_ERR = 13079; // 1
+static const uint64_t SH_FLD_OCI_APAR_ERR_MASK = 13080; // 1
+static const uint64_t SH_FLD_OCI_ARB_RESET = 13081; // 1
+static const uint64_t SH_FLD_OCI_BAD_REG_ADDR = 13082; // 1
+static const uint64_t SH_FLD_OCI_BAD_REG_ADDR_MASK = 13083; // 1
+static const uint64_t SH_FLD_OCI_ERR_INJ_CE_UE = 13084; // 1
+static const uint64_t SH_FLD_OCI_ERR_INJ_DCU = 13085; // 1
+static const uint64_t SH_FLD_OCI_ERR_INJ_ICU = 13086; // 1
+static const uint64_t SH_FLD_OCI_ERR_INJ_SINGL_CONT = 13087; // 1
+static const uint64_t SH_FLD_OCI_HI_BUS_MODE = 13088; // 1
+static const uint64_t SH_FLD_OCI_M0_FLCK = 13089; // 1
+static const uint64_t SH_FLD_OCI_M0_OEAR_LOCK = 13090; // 1
+static const uint64_t SH_FLD_OCI_M0_RW_STATUS = 13091; // 1
+static const uint64_t SH_FLD_OCI_M0_TIMEOUT_ERROR = 13092; // 1
+static const uint64_t SH_FLD_OCI_M1_FLCK = 13093; // 1
+static const uint64_t SH_FLD_OCI_M1_OEAR_LOCK = 13094; // 1
+static const uint64_t SH_FLD_OCI_M1_RW_STATUS = 13095; // 1
+static const uint64_t SH_FLD_OCI_M1_TIMEOUT_ERROR = 13096; // 1
+static const uint64_t SH_FLD_OCI_M2_FLCK = 13097; // 1
+static const uint64_t SH_FLD_OCI_M2_OEAR_LOCK = 13098; // 1
+static const uint64_t SH_FLD_OCI_M2_RW_STATUS = 13099; // 1
+static const uint64_t SH_FLD_OCI_M2_TIMEOUT_ERROR = 13100; // 1
+static const uint64_t SH_FLD_OCI_M3_FLCK = 13101; // 1
+static const uint64_t SH_FLD_OCI_M3_OEAR_LOCK = 13102; // 1
+static const uint64_t SH_FLD_OCI_M3_RW_STATUS = 13103; // 1
+static const uint64_t SH_FLD_OCI_M3_TIMEOUT_ERROR = 13104; // 1
+static const uint64_t SH_FLD_OCI_M4_FLCK = 13105; // 1
+static const uint64_t SH_FLD_OCI_M4_OEAR_LOCK = 13106; // 1
+static const uint64_t SH_FLD_OCI_M4_RW_STATUS = 13107; // 1
+static const uint64_t SH_FLD_OCI_M4_TIMEOUT_ERROR = 13108; // 1
+static const uint64_t SH_FLD_OCI_M5_FLCK = 13109; // 1
+static const uint64_t SH_FLD_OCI_M5_OEAR_LOCK = 13110; // 1
+static const uint64_t SH_FLD_OCI_M5_RW_STATUS = 13111; // 1
+static const uint64_t SH_FLD_OCI_M5_TIMEOUT_ERROR = 13112; // 1
+static const uint64_t SH_FLD_OCI_M6_FLCK = 13113; // 1
+static const uint64_t SH_FLD_OCI_M6_OEAR_LOCK = 13114; // 1
+static const uint64_t SH_FLD_OCI_M6_RW_STATUS = 13115; // 1
+static const uint64_t SH_FLD_OCI_M6_TIMEOUT_ERROR = 13116; // 1
+static const uint64_t SH_FLD_OCI_M7_FLCK = 13117; // 1
+static const uint64_t SH_FLD_OCI_M7_OEAR_LOCK = 13118; // 1
+static const uint64_t SH_FLD_OCI_M7_RW_STATUS = 13119; // 1
+static const uint64_t SH_FLD_OCI_M7_TIMEOUT_ERROR = 13120; // 1
+static const uint64_t SH_FLD_OCI_MARKER_SPACE = 13121; // 1
+static const uint64_t SH_FLD_OCI_MARKER_SPACE_LEN = 13122; // 1
+static const uint64_t SH_FLD_OCI_PRIORITY_MODE = 13123; // 1
+static const uint64_t SH_FLD_OCI_PRIORITY_ORDER = 13124; // 1
+static const uint64_t SH_FLD_OCI_PRIORITY_ORDER_LEN = 13125; // 1
+static const uint64_t SH_FLD_OCI_READ_DATA_PARITY = 13126; // 4
+static const uint64_t SH_FLD_OCI_READ_PIPELINE_CONTROL = 13127; // 1
+static const uint64_t SH_FLD_OCI_READ_PIPELINE_CONTROL_LEN = 13128; // 1
+static const uint64_t SH_FLD_OCI_REGION = 13129; // 4
+static const uint64_t SH_FLD_OCI_REGION_LEN = 13130; // 4
+static const uint64_t SH_FLD_OCI_SLAVE_ERROR = 13131; // 4
+static const uint64_t SH_FLD_OCI_SLAVE_INIT = 13132; // 1
+static const uint64_t SH_FLD_OCI_SLAVE_INIT_MASK = 13133; // 1
+static const uint64_t SH_FLD_OCI_TIMEOUT = 13134; // 4
+static const uint64_t SH_FLD_OCI_TIMEOUT_ADDR = 13135; // 1
+static const uint64_t SH_FLD_OCI_TIMEOUT_ADDR_LEN = 13136; // 1
+static const uint64_t SH_FLD_OCI_TRACE_MUX_SEL = 13137; // 1
+static const uint64_t SH_FLD_OCI_TRACE_MUX_SEL_LEN = 13138; // 1
+static const uint64_t SH_FLD_OCI_WRITE_PIPELINE_CONTROL = 13139; // 1
+static const uint64_t SH_FLD_OCI_WRPAR_ERR = 13140; // 1
+static const uint64_t SH_FLD_OCI_WRPAR_ERR_MASK = 13141; // 1
+static const uint64_t SH_FLD_OCR_DBG_HALT = 13142; // 1
+static const uint64_t SH_FLD_OCTANT_SELECT = 13143; // 2
+static const uint64_t SH_FLD_OCTANT_SELECT_LEN = 13144; // 2
+static const uint64_t SH_FLD_OFFSET = 13145; // 15
+static const uint64_t SH_FLD_OFFSET_LEN = 13146; // 15
+static const uint64_t SH_FLD_OFF_INIT_CFG = 13147; // 6
+static const uint64_t SH_FLD_OFF_INIT_CFG_LEN = 13148; // 6
+static const uint64_t SH_FLD_OFF_INIT_TIMEOUT = 13149; // 6
+static const uint64_t SH_FLD_OFF_INIT_TIMEOUT_LEN = 13150; // 6
+static const uint64_t SH_FLD_OFF_RECAL_CFG = 13151; // 6
+static const uint64_t SH_FLD_OFF_RECAL_CFG_LEN = 13152; // 6
+static const uint64_t SH_FLD_OFF_RECAL_TIMEOUT = 13153; // 6
+static const uint64_t SH_FLD_OFF_RECAL_TIMEOUT_LEN = 13154; // 6
+static const uint64_t SH_FLD_OJCFG_DBG_HALT = 13155; // 1
+static const uint64_t SH_FLD_OJCFG_JTAG_SRC_SEL = 13156; // 1
+static const uint64_t SH_FLD_OJCFG_JTAG_TRST_B = 13157; // 1
+static const uint64_t SH_FLD_OJCFG_RUN_TCK = 13158; // 1
+static const uint64_t SH_FLD_OJCFG_TCK_WIDTH = 13159; // 1
+static const uint64_t SH_FLD_OJCFG_TCK_WIDTH_LEN = 13160; // 1
+static const uint64_t SH_FLD_OJIC_DO_DR = 13161; // 1
+static const uint64_t SH_FLD_OJIC_DO_IR = 13162; // 1
+static const uint64_t SH_FLD_OJIC_DO_TAP_RESET = 13163; // 1
+static const uint64_t SH_FLD_OJIC_JTAG_INSTR = 13164; // 1
+static const uint64_t SH_FLD_OJIC_JTAG_INSTR_LEN = 13165; // 1
+static const uint64_t SH_FLD_OJIC_WR_VALID = 13166; // 1
+static const uint64_t SH_FLD_OJSTAT_FSM_ERROR = 13167; // 1
+static const uint64_t SH_FLD_OJSTAT_INPROG_WR_ERR = 13168; // 1
+static const uint64_t SH_FLD_OJSTAT_IR_DR_EQ0_ERR = 13169; // 1
+static const uint64_t SH_FLD_OJSTAT_JTAG_INPROG = 13170; // 1
+static const uint64_t SH_FLD_OJSTAT_RUN_TCK_EQ0_ERR = 13171; // 1
+static const uint64_t SH_FLD_OJSTAT_SRC_SEL_EQ1_ERR = 13172; // 1
+static const uint64_t SH_FLD_OJSTAT_TRST_B_EQ0_ERR = 13173; // 1
+static const uint64_t SH_FLD_ONESHOT0 = 13174; // 24
+static const uint64_t SH_FLD_ONESHOT1 = 13175; // 24
+static const uint64_t SH_FLD_ONE_PPC = 13176; // 24
+static const uint64_t SH_FLD_ONGOING = 13177; // 1
+static const uint64_t SH_FLD_ONL = 13178; // 96
+static const uint64_t SH_FLD_OOB_MUX = 13179; // 3
+static const uint64_t SH_FLD_OPB_ERROR = 13180; // 4
+static const uint64_t SH_FLD_OPB_MASTER_HANG_TIMEOUT = 13181; // 4
+static const uint64_t SH_FLD_OPB_PARITY_ERROR = 13182; // 3
+static const uint64_t SH_FLD_OPB_TIMEOUT = 13183; // 4
+static const uint64_t SH_FLD_OPCG_IP = 13184; // 43
+static const uint64_t SH_FLD_OPCODE = 13185; // 1
+static const uint64_t SH_FLD_OPCODE_LEN = 13186; // 1
+static const uint64_t SH_FLD_OPER = 13187; // 1
+static const uint64_t SH_FLD_OPER_LEN = 13188; // 1
+static const uint64_t SH_FLD_OPTION_PREVENT_SBE_START = 13189; // 1
+static const uint64_t SH_FLD_OPTION_SKIP_SCAN0_CLOCKSTART = 13190; // 1
+static const uint64_t SH_FLD_OPT_UNUSED1 = 13191; // 2
+static const uint64_t SH_FLD_OPT_UNUSED1_LEN = 13192; // 2
+static const uint64_t SH_FLD_OPT_UNUSED2 = 13193; // 2
+static const uint64_t SH_FLD_OPT_UNUSED3 = 13194; // 2
+static const uint64_t SH_FLD_OPT_UNUSED3_LEN = 13195; // 2
+static const uint64_t SH_FLD_OPT_UNUSED4 = 13196; // 2
+static const uint64_t SH_FLD_OPT_UNUSED5 = 13197; // 2
+static const uint64_t SH_FLD_OPT_UNUSED5_LEN = 13198; // 2
+static const uint64_t SH_FLD_OSC = 13199; // 4
+static const uint64_t SH_FLD_OSCILLATOR = 13200; // 1
+static const uint64_t SH_FLD_OSCILLATOR_LEN = 13201; // 1
+static const uint64_t SH_FLD_OSCSWITCH_CNTL0_DC = 13202; // 3
+static const uint64_t SH_FLD_OSCSWITCH_CNTL0_DC_LEN = 13203; // 3
+static const uint64_t SH_FLD_OSCSWITCH_CNTL1_DC = 13204; // 3
+static const uint64_t SH_FLD_OSCSWITCH_CNTL1_DC_LEN = 13205; // 3
+static const uint64_t SH_FLD_OSCSWITCH_INTERRUPT = 13206; // 4
+static const uint64_t SH_FLD_OSC_LEN = 13207; // 4
+static const uint64_t SH_FLD_OSC_SWITCH = 13208; // 4
+static const uint64_t SH_FLD_OS_STATUS_DISABLE_A_N = 13209; // 96
+static const uint64_t SH_FLD_OTHER_SCOM_SAT = 13210; // 1
+static const uint64_t SH_FLD_OTP = 13211; // 1
+static const uint64_t SH_FLD_OTP_LEN = 13212; // 1
+static const uint64_t SH_FLD_OTR_SPECIAL_WKUP = 13213; // 30
+static const uint64_t SH_FLD_OUT = 13214; // 1
+static const uint64_t SH_FLD_OUTER_LOOP_CNT = 13215; // 8
+static const uint64_t SH_FLD_OUTER_LOOP_CNT_LEN = 13216; // 8
+static const uint64_t SH_FLD_OUTWR_INRD_ECC_CE = 13217; // 1
+static const uint64_t SH_FLD_OUTWR_INRD_ECC_SUE = 13218; // 1
+static const uint64_t SH_FLD_OUTWR_INRD_ECC_UE = 13219; // 1
+static const uint64_t SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR = 13220; // 6
+static const uint64_t SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR = 13221; // 6
+static const uint64_t SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR = 13222; // 6
+static const uint64_t SH_FLD_OUT_COUNT1 = 13223; // 1
+static const uint64_t SH_FLD_OUT_COUNT1_LEN = 13224; // 1
+static const uint64_t SH_FLD_OUT_COUNT2 = 13225; // 1
+static const uint64_t SH_FLD_OUT_COUNT2_LEN = 13226; // 1
+static const uint64_t SH_FLD_OUT_LEN = 13227; // 1
+static const uint64_t SH_FLD_OUT_RRB_SOURCED_ERROR = 13228; // 6
+static const uint64_t SH_FLD_OVERFLOW_CHECKSTOP = 13229; // 2
+static const uint64_t SH_FLD_OVERFLOW_ERR = 13230; // 43
+static const uint64_t SH_FLD_OVERFLOW_ERROR = 13231; // 2
+static const uint64_t SH_FLD_OVERFLOW_MASK = 13232; // 43
+static const uint64_t SH_FLD_OVERRIDE_EN = 13233; // 24
+static const uint64_t SH_FLD_OVERRIDE_PBINIT_ERR_CMD = 13234; // 1
+static const uint64_t SH_FLD_OVERRIDE_PBINIT_HTM_CMD = 13235; // 1
+static const uint64_t SH_FLD_OVERRIDE_PBINIT_TOD_CMD = 13236; // 1
+static const uint64_t SH_FLD_OVERRIDE_PBINIT_TRACE_CMD = 13237; // 1
+static const uint64_t SH_FLD_OVERRIDE_PBINIT_XSCOM_CMD = 13238; // 1
+static const uint64_t SH_FLD_OVERRUN = 13239; // 8
+static const uint64_t SH_FLD_OVER_OR_UNDERRUN_ERR = 13240; // 1
+static const uint64_t SH_FLD_OVR_PM = 13241; // 1
+static const uint64_t SH_FLD_OWN_ID_THIS_SLAVE = 13242; // 2
+static const uint64_t SH_FLD_OWN_ID_THIS_SLAVE_LEN = 13243; // 2
+static const uint64_t SH_FLD_P0_BACK2BACK_MODE_ENA = 13244; // 1
+static const uint64_t SH_FLD_P0_BACK2BACK_MODE_ENA_LEN = 13245; // 1
+static const uint64_t SH_FLD_P0_IS_IDLE = 13246; // 4
+static const uint64_t SH_FLD_P1_IS_IDLE = 13247; // 4
+static const uint64_t SH_FLD_P9_TO_P9_MODE = 13248; // 6
+static const uint64_t SH_FLD_PACE = 13249; // 2
+static const uint64_t SH_FLD_PACE_LEN = 13250; // 2
+static const uint64_t SH_FLD_PACE_RATE = 13251; // 1
+static const uint64_t SH_FLD_PACE_RATE_LEN = 13252; // 1
+static const uint64_t SH_FLD_PACING_ALLOW_0 = 13253; // 2
+static const uint64_t SH_FLD_PACING_ALLOW_1 = 13254; // 1
+static const uint64_t SH_FLD_PACING_ALLOW_2 = 13255; // 1
+static const uint64_t SH_FLD_PACING_ALLOW_3 = 13256; // 1
+static const uint64_t SH_FLD_PACKET_DELAY_LIMIT = 13257; // 5
+static const uint64_t SH_FLD_PACKET_DELAY_LIMIT_LEN = 13258; // 5
+static const uint64_t SH_FLD_PAGE_OFFSET_CFG = 13259; // 1
+static const uint64_t SH_FLD_PAGE_OFFSET_CFG_LEN = 13260; // 1
+static const uint64_t SH_FLD_PAGE_SIZE_64K = 13261; // 4
+static const uint64_t SH_FLD_PAGE_SIZE_64K_PC = 13262; // 1
+static const uint64_t SH_FLD_PAGE_SIZE_64K_VC = 13263; // 1
+static const uint64_t SH_FLD_PAIR0_QUA = 13264; // 8
+static const uint64_t SH_FLD_PAIR0_QUA_LEN = 13265; // 8
+static const uint64_t SH_FLD_PAIR0_QUA_V = 13266; // 8
+static const uint64_t SH_FLD_PAIR0_TER = 13267; // 8
+static const uint64_t SH_FLD_PAIR0_TER_LEN = 13268; // 8
+static const uint64_t SH_FLD_PAIR0_TER_V = 13269; // 8
+static const uint64_t SH_FLD_PAIR1_PRI = 13270; // 8
+static const uint64_t SH_FLD_PAIR1_PRI_LEN = 13271; // 8
+static const uint64_t SH_FLD_PAIR1_PRI_V = 13272; // 8
+static const uint64_t SH_FLD_PAIR1_QUA = 13273; // 8
+static const uint64_t SH_FLD_PAIR1_QUA_LEN = 13274; // 8
+static const uint64_t SH_FLD_PAIR1_QUA_V = 13275; // 8
+static const uint64_t SH_FLD_PAIR1_SEC = 13276; // 8
+static const uint64_t SH_FLD_PAIR1_SEC_LEN = 13277; // 8
+static const uint64_t SH_FLD_PAIR1_SEC_V = 13278; // 8
+static const uint64_t SH_FLD_PAIR1_TER = 13279; // 8
+static const uint64_t SH_FLD_PAIR1_TER_LEN = 13280; // 8
+static const uint64_t SH_FLD_PAIR1_TER_V = 13281; // 8
+static const uint64_t SH_FLD_PAIR2_PRI = 13282; // 8
+static const uint64_t SH_FLD_PAIR2_PRI_LEN = 13283; // 8
+static const uint64_t SH_FLD_PAIR2_PRI_V = 13284; // 8
+static const uint64_t SH_FLD_PAIR2_QUA = 13285; // 8
+static const uint64_t SH_FLD_PAIR2_QUA_LEN = 13286; // 8
+static const uint64_t SH_FLD_PAIR2_QUA_V = 13287; // 8
+static const uint64_t SH_FLD_PAIR2_SEC = 13288; // 8
+static const uint64_t SH_FLD_PAIR2_SEC_LEN = 13289; // 8
+static const uint64_t SH_FLD_PAIR2_SEC_V = 13290; // 8
+static const uint64_t SH_FLD_PAIR2_TER = 13291; // 8
+static const uint64_t SH_FLD_PAIR2_TER_LEN = 13292; // 8
+static const uint64_t SH_FLD_PAIR2_TER_V = 13293; // 8
+static const uint64_t SH_FLD_PAIR3_PRI = 13294; // 8
+static const uint64_t SH_FLD_PAIR3_PRI_LEN = 13295; // 8
+static const uint64_t SH_FLD_PAIR3_PRI_V = 13296; // 8
+static const uint64_t SH_FLD_PAIR3_SEC = 13297; // 8
+static const uint64_t SH_FLD_PAIR3_SEC_LEN = 13298; // 8
+static const uint64_t SH_FLD_PAIR3_SEC_V = 13299; // 8
+static const uint64_t SH_FLD_PAPR_INBOUND_INJECT_ERROR = 13300; // 6
+static const uint64_t SH_FLD_PAPR_OUTBOUND_INJECT_ERROR = 13301; // 6
+static const uint64_t SH_FLD_PARALLEL_ADDR_INVALID = 13302; // 43
+static const uint64_t SH_FLD_PARALLEL_READ_NVLD = 13303; // 43
+static const uint64_t SH_FLD_PARALLEL_WRITE_NVLD = 13304; // 43
+static const uint64_t SH_FLD_PARANOIA_TEST_ENABLE_CHANGE = 13305; // 43
+static const uint64_t SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE = 13306; // 43
+static const uint64_t SH_FLD_PARITY = 13307; // 45
+static const uint64_t SH_FLD_PARITY_CHECK = 13308; // 1
+static const uint64_t SH_FLD_PARITY_ERR = 13309; // 4
+static const uint64_t SH_FLD_PARITY_ERR2 = 13310; // 3
+static const uint64_t SH_FLD_PARITY_ERROR = 13311; // 51
+static const uint64_t SH_FLD_PARITY_ERROR_SUE_ENA = 13312; // 6
+static const uint64_t SH_FLD_PARITY_ON_INTERFACE_MACHINE = 13313; // 43
+static const uint64_t SH_FLD_PARITY_ON_P2S_MACHINE = 13314; // 43
+static const uint64_t SH_FLD_PARSER00_ATTN = 13315; // 4
+static const uint64_t SH_FLD_PARSER01_ATTN = 13316; // 4
+static const uint64_t SH_FLD_PARSER02_ATTN = 13317; // 4
+static const uint64_t SH_FLD_PARSER03_ATTN = 13318; // 4
+static const uint64_t SH_FLD_PARSER04_ATTN = 13319; // 4
+static const uint64_t SH_FLD_PARSER05_ATTN = 13320; // 4
+static const uint64_t SH_FLD_PARSER06_ATTN = 13321; // 2
+static const uint64_t SH_FLD_PARSER07_ATTN = 13322; // 2
+static const uint64_t SH_FLD_PART_0 = 13323; // 2
+static const uint64_t SH_FLD_PART_0_LEN = 13324; // 2
+static const uint64_t SH_FLD_PART_1 = 13325; // 2
+static const uint64_t SH_FLD_PART_10 = 13326; // 2
+static const uint64_t SH_FLD_PART_10_LEN = 13327; // 2
+static const uint64_t SH_FLD_PART_11 = 13328; // 2
+static const uint64_t SH_FLD_PART_11_LEN = 13329; // 2
+static const uint64_t SH_FLD_PART_12 = 13330; // 2
+static const uint64_t SH_FLD_PART_12_LEN = 13331; // 2
+static const uint64_t SH_FLD_PART_13 = 13332; // 2
+static const uint64_t SH_FLD_PART_13_LEN = 13333; // 2
+static const uint64_t SH_FLD_PART_14 = 13334; // 2
+static const uint64_t SH_FLD_PART_14_LEN = 13335; // 2
+static const uint64_t SH_FLD_PART_15 = 13336; // 2
+static const uint64_t SH_FLD_PART_15_LEN = 13337; // 2
+static const uint64_t SH_FLD_PART_16 = 13338; // 2
+static const uint64_t SH_FLD_PART_16_LEN = 13339; // 2
+static const uint64_t SH_FLD_PART_17 = 13340; // 2
+static const uint64_t SH_FLD_PART_17_LEN = 13341; // 2
+static const uint64_t SH_FLD_PART_18 = 13342; // 2
+static const uint64_t SH_FLD_PART_18_LEN = 13343; // 2
+static const uint64_t SH_FLD_PART_19 = 13344; // 2
+static const uint64_t SH_FLD_PART_19_LEN = 13345; // 2
+static const uint64_t SH_FLD_PART_1_LEN = 13346; // 2
+static const uint64_t SH_FLD_PART_2 = 13347; // 2
+static const uint64_t SH_FLD_PART_20 = 13348; // 2
+static const uint64_t SH_FLD_PART_20_LEN = 13349; // 2
+static const uint64_t SH_FLD_PART_21 = 13350; // 2
+static const uint64_t SH_FLD_PART_21_LEN = 13351; // 2
+static const uint64_t SH_FLD_PART_22 = 13352; // 2
+static const uint64_t SH_FLD_PART_22_LEN = 13353; // 2
+static const uint64_t SH_FLD_PART_23 = 13354; // 2
+static const uint64_t SH_FLD_PART_23_LEN = 13355; // 2
+static const uint64_t SH_FLD_PART_24 = 13356; // 2
+static const uint64_t SH_FLD_PART_24_LEN = 13357; // 2
+static const uint64_t SH_FLD_PART_25 = 13358; // 2
+static const uint64_t SH_FLD_PART_25_LEN = 13359; // 2
+static const uint64_t SH_FLD_PART_26 = 13360; // 2
+static const uint64_t SH_FLD_PART_26_LEN = 13361; // 2
+static const uint64_t SH_FLD_PART_27 = 13362; // 2
+static const uint64_t SH_FLD_PART_27_LEN = 13363; // 2
+static const uint64_t SH_FLD_PART_28 = 13364; // 2
+static const uint64_t SH_FLD_PART_28_LEN = 13365; // 2
+static const uint64_t SH_FLD_PART_29 = 13366; // 2
+static const uint64_t SH_FLD_PART_29_LEN = 13367; // 2
+static const uint64_t SH_FLD_PART_2_LEN = 13368; // 2
+static const uint64_t SH_FLD_PART_3 = 13369; // 2
+static const uint64_t SH_FLD_PART_30 = 13370; // 2
+static const uint64_t SH_FLD_PART_30_LEN = 13371; // 2
+static const uint64_t SH_FLD_PART_31 = 13372; // 2
+static const uint64_t SH_FLD_PART_31_LEN = 13373; // 2
+static const uint64_t SH_FLD_PART_32 = 13374; // 2
+static const uint64_t SH_FLD_PART_32_LEN = 13375; // 2
+static const uint64_t SH_FLD_PART_33 = 13376; // 2
+static const uint64_t SH_FLD_PART_33_LEN = 13377; // 2
+static const uint64_t SH_FLD_PART_34 = 13378; // 2
+static const uint64_t SH_FLD_PART_34_LEN = 13379; // 2
+static const uint64_t SH_FLD_PART_35 = 13380; // 2
+static const uint64_t SH_FLD_PART_35_LEN = 13381; // 2
+static const uint64_t SH_FLD_PART_36 = 13382; // 2
+static const uint64_t SH_FLD_PART_36_LEN = 13383; // 2
+static const uint64_t SH_FLD_PART_37 = 13384; // 2
+static const uint64_t SH_FLD_PART_37_LEN = 13385; // 2
+static const uint64_t SH_FLD_PART_38 = 13386; // 2
+static const uint64_t SH_FLD_PART_38_LEN = 13387; // 2
+static const uint64_t SH_FLD_PART_39 = 13388; // 2
+static const uint64_t SH_FLD_PART_39_LEN = 13389; // 2
+static const uint64_t SH_FLD_PART_3_LEN = 13390; // 2
+static const uint64_t SH_FLD_PART_4 = 13391; // 2
+static const uint64_t SH_FLD_PART_40 = 13392; // 2
+static const uint64_t SH_FLD_PART_40_LEN = 13393; // 2
+static const uint64_t SH_FLD_PART_41 = 13394; // 2
+static const uint64_t SH_FLD_PART_41_LEN = 13395; // 2
+static const uint64_t SH_FLD_PART_42 = 13396; // 2
+static const uint64_t SH_FLD_PART_42_LEN = 13397; // 2
+static const uint64_t SH_FLD_PART_43 = 13398; // 2
+static const uint64_t SH_FLD_PART_43_LEN = 13399; // 2
+static const uint64_t SH_FLD_PART_44 = 13400; // 2
+static const uint64_t SH_FLD_PART_44_LEN = 13401; // 2
+static const uint64_t SH_FLD_PART_45 = 13402; // 2
+static const uint64_t SH_FLD_PART_45_LEN = 13403; // 2
+static const uint64_t SH_FLD_PART_46 = 13404; // 2
+static const uint64_t SH_FLD_PART_46_LEN = 13405; // 2
+static const uint64_t SH_FLD_PART_47 = 13406; // 2
+static const uint64_t SH_FLD_PART_47_LEN = 13407; // 2
+static const uint64_t SH_FLD_PART_48 = 13408; // 2
+static const uint64_t SH_FLD_PART_48_LEN = 13409; // 2
+static const uint64_t SH_FLD_PART_49 = 13410; // 2
+static const uint64_t SH_FLD_PART_49_LEN = 13411; // 2
+static const uint64_t SH_FLD_PART_4_LEN = 13412; // 2
+static const uint64_t SH_FLD_PART_5 = 13413; // 2
+static const uint64_t SH_FLD_PART_50 = 13414; // 2
+static const uint64_t SH_FLD_PART_50_LEN = 13415; // 2
+static const uint64_t SH_FLD_PART_51 = 13416; // 2
+static const uint64_t SH_FLD_PART_51_LEN = 13417; // 2
+static const uint64_t SH_FLD_PART_52 = 13418; // 2
+static const uint64_t SH_FLD_PART_52_LEN = 13419; // 2
+static const uint64_t SH_FLD_PART_53 = 13420; // 2
+static const uint64_t SH_FLD_PART_53_LEN = 13421; // 2
+static const uint64_t SH_FLD_PART_54 = 13422; // 2
+static const uint64_t SH_FLD_PART_54_LEN = 13423; // 2
+static const uint64_t SH_FLD_PART_55 = 13424; // 2
+static const uint64_t SH_FLD_PART_55_LEN = 13425; // 2
+static const uint64_t SH_FLD_PART_56 = 13426; // 2
+static const uint64_t SH_FLD_PART_56_LEN = 13427; // 2
+static const uint64_t SH_FLD_PART_57 = 13428; // 2
+static const uint64_t SH_FLD_PART_57_LEN = 13429; // 2
+static const uint64_t SH_FLD_PART_58 = 13430; // 2
+static const uint64_t SH_FLD_PART_58_LEN = 13431; // 2
+static const uint64_t SH_FLD_PART_59 = 13432; // 2
+static const uint64_t SH_FLD_PART_59_LEN = 13433; // 2
+static const uint64_t SH_FLD_PART_5_LEN = 13434; // 2
+static const uint64_t SH_FLD_PART_6 = 13435; // 2
+static const uint64_t SH_FLD_PART_60 = 13436; // 2
+static const uint64_t SH_FLD_PART_60_LEN = 13437; // 2
+static const uint64_t SH_FLD_PART_61 = 13438; // 2
+static const uint64_t SH_FLD_PART_61_LEN = 13439; // 2
+static const uint64_t SH_FLD_PART_62 = 13440; // 2
+static const uint64_t SH_FLD_PART_62_LEN = 13441; // 2
+static const uint64_t SH_FLD_PART_63 = 13442; // 2
+static const uint64_t SH_FLD_PART_63_LEN = 13443; // 2
+static const uint64_t SH_FLD_PART_6_LEN = 13444; // 2
+static const uint64_t SH_FLD_PART_7 = 13445; // 2
+static const uint64_t SH_FLD_PART_7_LEN = 13446; // 2
+static const uint64_t SH_FLD_PART_8 = 13447; // 2
+static const uint64_t SH_FLD_PART_8_LEN = 13448; // 2
+static const uint64_t SH_FLD_PART_9 = 13449; // 2
+static const uint64_t SH_FLD_PART_9_LEN = 13450; // 2
+static const uint64_t SH_FLD_PAR_17_MASK = 13451; // 8
+static const uint64_t SH_FLD_PAR_ERR_ONLY = 13452; // 8
+static const uint64_t SH_FLD_PAR_INVERT = 13453; // 8
+static const uint64_t SH_FLD_PASS_CQ_INT_PMU_DATA_HI = 13454; // 1
+static const uint64_t SH_FLD_PASS_CQ_INT_PMU_DATA_LO = 13455; // 1
+static const uint64_t SH_FLD_PASS_CQ_INT_TRACE_DATA_HI = 13456; // 1
+static const uint64_t SH_FLD_PASS_CQ_INT_TRACE_DATA_LO = 13457; // 1
+static const uint64_t SH_FLD_PASS_CQ_INT_TRACE_TRIG_01 = 13458; // 1
+static const uint64_t SH_FLD_PASS_CQ_INT_TRACE_TRIG_23 = 13459; // 1
+static const uint64_t SH_FLD_PASS_WC_INT_TRACE_DATA_HI = 13460; // 1
+static const uint64_t SH_FLD_PASS_WC_INT_TRACE_DATA_LO = 13461; // 1
+static const uint64_t SH_FLD_PASS_WC_INT_TRACE_TRIG_01 = 13462; // 1
+static const uint64_t SH_FLD_PASS_WC_INT_TRACE_TRIG_23 = 13463; // 1
+static const uint64_t SH_FLD_PASTE_ADDR_ALIGN = 13464; // 1
+static const uint64_t SH_FLD_PASTE_REJECT = 13465; // 1
+static const uint64_t SH_FLD_PATTERNA = 13466; // 90
+static const uint64_t SH_FLD_PATTERNA_LEN = 13467; // 90
+static const uint64_t SH_FLD_PATTERNB = 13468; // 90
+static const uint64_t SH_FLD_PATTERNB_LEN = 13469; // 90
+static const uint64_t SH_FLD_PATTERNC = 13470; // 90
+static const uint64_t SH_FLD_PATTERNC_LEN = 13471; // 90
+static const uint64_t SH_FLD_PATTERND = 13472; // 90
+static const uint64_t SH_FLD_PATTERND_LEN = 13473; // 90
+static const uint64_t SH_FLD_PATTERN_CHECK_EN = 13474; // 1
+static const uint64_t SH_FLD_PATTERN_SEL = 13475; // 2
+static const uint64_t SH_FLD_PATTERN_SEL_LEN = 13476; // 2
+static const uint64_t SH_FLD_PAYLOAD = 13477; // 1
+static const uint64_t SH_FLD_PAYLOAD_LEN = 13478; // 1
+static const uint64_t SH_FLD_PBASE = 13479; // 4
+static const uint64_t SH_FLD_PBASE_LEN = 13480; // 4
+static const uint64_t SH_FLD_PBAX_EN = 13481; // 1
+static const uint64_t SH_FLD_PBAX_OCC_PUSH0 = 13482; // 1
+static const uint64_t SH_FLD_PBAX_OCC_PUSH1 = 13483; // 1
+static const uint64_t SH_FLD_PBAX_OCC_SEND_ATTN = 13484; // 1
+static const uint64_t SH_FLD_PBA_BCDE_ATTN = 13485; // 1
+static const uint64_t SH_FLD_PBA_BCUE_ATTN = 13486; // 1
+static const uint64_t SH_FLD_PBA_ERROR = 13487; // 1
+static const uint64_t SH_FLD_PBA_REGION = 13488; // 1
+static const uint64_t SH_FLD_PBA_REGION_LEN = 13489; // 1
+static const uint64_t SH_FLD_PBCFG_0_DISABLE_WR_RD_PUSH = 13490; // 1
+static const uint64_t SH_FLD_PBCFG_0_EPSILON = 13491; // 1
+static const uint64_t SH_FLD_PBCFG_0_EPSILON_LEN = 13492; // 1
+static const uint64_t SH_FLD_PBCFG_0_HANG_NX_MAX_CNT = 13493; // 1
+static const uint64_t SH_FLD_PBCFG_0_HANG_NX_MAX_CNT_LEN = 13494; // 1
+static const uint64_t SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT = 13495; // 1
+static const uint64_t SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT_LEN = 13496; // 1
+static const uint64_t SH_FLD_PBCFG_0_INJ_ARRAY_SEL = 13497; // 1
+static const uint64_t SH_FLD_PBCFG_0_INJ_CE = 13498; // 1
+static const uint64_t SH_FLD_PBCFG_0_INJ_FREQ = 13499; // 1
+static const uint64_t SH_FLD_PBCFG_0_INJ_SUE = 13500; // 1
+static const uint64_t SH_FLD_PBCFG_0_INJ_UE = 13501; // 1
+static const uint64_t SH_FLD_PBCFG_0_UNUSED1 = 13502; // 1
+static const uint64_t SH_FLD_PBCFG_0_UNUSED1_LEN = 13503; // 1
+static const uint64_t SH_FLD_PBCFG_0_UNUSED2 = 13504; // 1
+static const uint64_t SH_FLD_PBCFG_0_UNUSED2_LEN = 13505; // 1
+static const uint64_t SH_FLD_PBCFG_1_UNUSED1 = 13506; // 1
+static const uint64_t SH_FLD_PBCFG_1_UNUSED1_LEN = 13507; // 1
+static const uint64_t SH_FLD_PBCFG_1_UNUSED2 = 13508; // 1
+static const uint64_t SH_FLD_PBCFG_1_UNUSED2_LEN = 13509; // 1
+static const uint64_t SH_FLD_PBCQ_CNTRL_LOGIC_ERR = 13510; // 1
+static const uint64_t SH_FLD_PBDATA_HANG = 13511; // 1
+static const uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR0 = 13512; // 12
+static const uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR1 = 13513; // 12
+static const uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR2 = 13514; // 12
+static const uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR0 = 13515; // 12
+static const uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR1 = 13516; // 12
+static const uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR2 = 13517; // 12
+static const uint64_t SH_FLD_PBIEQ00_PBH_HW1_ERROR = 13518; // 2
+static const uint64_t SH_FLD_PBIEQ00_PBH_HW2_ERROR = 13519; // 2
+static const uint64_t SH_FLD_PBIEQ00_PBH_OVERFLOW_ERROR = 13520; // 2
+static const uint64_t SH_FLD_PBIEQ00_PBH_PROTOCOL_ERROR = 13521; // 2
+static const uint64_t SH_FLD_PBIEQ01_PBH_HW1_ERROR = 13522; // 2
+static const uint64_t SH_FLD_PBIEQ01_PBH_HW2_ERROR = 13523; // 2
+static const uint64_t SH_FLD_PBIEQ01_PBH_OVERFLOW_ERROR = 13524; // 2
+static const uint64_t SH_FLD_PBIEQ01_PBH_PROTOCOL_ERROR = 13525; // 2
+static const uint64_t SH_FLD_PBIEQ02_PBH_HW1_ERROR = 13526; // 2
+static const uint64_t SH_FLD_PBIEQ02_PBH_HW2_ERROR = 13527; // 2
+static const uint64_t SH_FLD_PBIEQ02_PBH_OVERFLOW_ERROR = 13528; // 2
+static const uint64_t SH_FLD_PBIEQ02_PBH_PROTOCOL_ERROR = 13529; // 2
+static const uint64_t SH_FLD_PBIEQ03_PBH_HW1_ERROR = 13530; // 2
+static const uint64_t SH_FLD_PBIEQ03_PBH_HW2_ERROR = 13531; // 2
+static const uint64_t SH_FLD_PBIEQ03_PBH_OVERFLOW_ERROR = 13532; // 2
+static const uint64_t SH_FLD_PBIEQ03_PBH_PROTOCOL_ERROR = 13533; // 2
+static const uint64_t SH_FLD_PBIEQ04_PBH_HW1_ERROR = 13534; // 2
+static const uint64_t SH_FLD_PBIEQ04_PBH_HW2_ERROR = 13535; // 2
+static const uint64_t SH_FLD_PBIEQ04_PBH_OVERFLOW_ERROR = 13536; // 2
+static const uint64_t SH_FLD_PBIEQ04_PBH_PROTOCOL_ERROR = 13537; // 2
+static const uint64_t SH_FLD_PBIEQ05_PBH_HW1_ERROR = 13538; // 2
+static const uint64_t SH_FLD_PBIEQ05_PBH_HW2_ERROR = 13539; // 2
+static const uint64_t SH_FLD_PBIEQ05_PBH_OVERFLOW_ERROR = 13540; // 2
+static const uint64_t SH_FLD_PBIEQ05_PBH_PROTOCOL_ERROR = 13541; // 2
+static const uint64_t SH_FLD_PBI_DEBUG_SEL = 13542; // 4
+static const uint64_t SH_FLD_PBI_DEBUG_SEL_LEN = 13543; // 4
+static const uint64_t SH_FLD_PBI_IDLE = 13544; // 1
+static const uint64_t SH_FLD_PBI_INTERNAL_HANG = 13545; // 1
+static const uint64_t SH_FLD_PBI_MUX_SELECT = 13546; // 1
+static const uint64_t SH_FLD_PBI_MUX_SELECT_LEN = 13547; // 1
+static const uint64_t SH_FLD_PBI_PE = 13548; // 2
+static const uint64_t SH_FLD_PBI_WRITE_IDLE = 13549; // 2
+static const uint64_t SH_FLD_PBLN = 13550; // 15
+static const uint64_t SH_FLD_PBM_STATE = 13551; // 3
+static const uint64_t SH_FLD_PBM_STATE_LEN = 13552; // 3
+static const uint64_t SH_FLD_PBNNG = 13553; // 15
+static const uint64_t SH_FLD_PBREQ_BCE_MAX_PRIORITY = 13554; // 1
+static const uint64_t SH_FLD_PBREQ_DATA_HANG_DIV = 13555; // 1
+static const uint64_t SH_FLD_PBREQ_DATA_HANG_DIV_LEN = 13556; // 1
+static const uint64_t SH_FLD_PBREQ_DROP_PRIORITY_MASK = 13557; // 1
+static const uint64_t SH_FLD_PBREQ_DROP_PRIORITY_MASK_LEN = 13558; // 1
+static const uint64_t SH_FLD_PBREQ_EVENT_MUX = 13559; // 1
+static const uint64_t SH_FLD_PBREQ_EVENT_MUX_LEN = 13560; // 1
+static const uint64_t SH_FLD_PBREQ_EXIT_HANG_DIV = 13561; // 1
+static const uint64_t SH_FLD_PBREQ_EXIT_HANG_DIV_LEN = 13562; // 1
+static const uint64_t SH_FLD_PBREQ_EXIT_ON_HANG = 13563; // 1
+static const uint64_t SH_FLD_PBREQ_EXIT_ON_HANG_PBAX = 13564; // 1
+static const uint64_t SH_FLD_PBREQ_OPER_HANG_DIV = 13565; // 1
+static const uint64_t SH_FLD_PBREQ_OPER_HANG_DIV_LEN = 13566; // 1
+static const uint64_t SH_FLD_PBREQ_SLVFW_MAX_PRIORITY = 13567; // 1
+static const uint64_t SH_FLD_PBRNVG = 13568; // 15
+static const uint64_t SH_FLD_PBRS = 13569; // 3
+static const uint64_t SH_FLD_PBRSP = 13570; // 12
+static const uint64_t SH_FLD_PBRX_MASK = 13571; // 3
+static const uint64_t SH_FLD_PBRX_MASK_LEN = 13572; // 3
+static const uint64_t SH_FLD_PBRX_RTAG = 13573; // 3
+static const uint64_t SH_FLD_PBRX_RTAG_LEN = 13574; // 3
+static const uint64_t SH_FLD_PBTX_AMO_IGNORE_XUE = 13575; // 3
+static const uint64_t SH_FLD_PBTX_DELAY_BDONE = 13576; // 3
+static const uint64_t SH_FLD_PBTX_EARLY_AFTAG = 13577; // 3
+static const uint64_t SH_FLD_PBTX_FLIP_IMIN_BIG = 13578; // 3
+static const uint64_t SH_FLD_PBTX_FLIP_IMIN_LITTLE = 13579; // 3
+static const uint64_t SH_FLD_PBTX_REDUCE_RTAG = 13580; // 3
+static const uint64_t SH_FLD_PBUS_CMD_HANG = 13581; // 2
+static const uint64_t SH_FLD_PBUS_ECC_CE = 13582; // 2
+static const uint64_t SH_FLD_PBUS_ECC_SUE = 13583; // 2
+static const uint64_t SH_FLD_PBUS_ECC_UE = 13584; // 2
+static const uint64_t SH_FLD_PBUS_LINK_ABORT = 13585; // 2
+static const uint64_t SH_FLD_PBUS_LOAD_LINK_ERR = 13586; // 2
+static const uint64_t SH_FLD_PBUS_MISC_HW = 13587; // 2
+static const uint64_t SH_FLD_PBUS_READ_ARE = 13588; // 2
+static const uint64_t SH_FLD_PBUS_STORE_LINK_ERR = 13589; // 2
+static const uint64_t SH_FLD_PBUS_WRITE_ARE = 13590; // 2
+static const uint64_t SH_FLD_PBUS_XLAT_ECC_SUE = 13591; // 1
+static const uint64_t SH_FLD_PBUS_XLAT_ECC_UE = 13592; // 1
+static const uint64_t SH_FLD_PBXMIT_DXMIT_SEQ_ERRHOLD = 13593; // 2
+static const uint64_t SH_FLD_PBXMIT_MSGQ_SEQ_ERRHOLD = 13594; // 2
+static const uint64_t SH_FLD_PB_ACKDEAD_FW_RD = 13595; // 1
+static const uint64_t SH_FLD_PB_ACKDEAD_FW_RD_MASK = 13596; // 1
+static const uint64_t SH_FLD_PB_ACKDEAD_FW_WR = 13597; // 1
+static const uint64_t SH_FLD_PB_ACKDEAD_FW_WR_MASK = 13598; // 1
+static const uint64_t SH_FLD_PB_ADDR_PARITY = 13599; // 2
+static const uint64_t SH_FLD_PB_BADCRESP = 13600; // 1
+static const uint64_t SH_FLD_PB_BADCRESP_MASK = 13601; // 1
+static const uint64_t SH_FLD_PB_BAR_RESET = 13602; // 1
+static const uint64_t SH_FLD_PB_CE_FW = 13603; // 1
+static const uint64_t SH_FLD_PB_CE_FW_MASK = 13604; // 1
+static const uint64_t SH_FLD_PB_DATA_TIME_OUT = 13605; // 4
+static const uint64_t SH_FLD_PB_ECC_CE = 13606; // 1
+static const uint64_t SH_FLD_PB_ECC_ERR_CE = 13607; // 4
+static const uint64_t SH_FLD_PB_ECC_ERR_SUE = 13608; // 4
+static const uint64_t SH_FLD_PB_ECC_ERR_UE = 13609; // 4
+static const uint64_t SH_FLD_PB_ECC_SUE = 13610; // 1
+static const uint64_t SH_FLD_PB_ECC_UE = 13611; // 1
+static const uint64_t SH_FLD_PB_NOCI_EVENT_SEL = 13612; // 1
+static const uint64_t SH_FLD_PB_OFFSET = 13613; // 2
+static const uint64_t SH_FLD_PB_OFFSET_LEN = 13614; // 2
+static const uint64_t SH_FLD_PB_OPERTO = 13615; // 1
+static const uint64_t SH_FLD_PB_OPERTO_MASK = 13616; // 1
+static const uint64_t SH_FLD_PB_OP_HANG_ERR = 13617; // 1
+static const uint64_t SH_FLD_PB_PARITY_ERR = 13618; // 1
+static const uint64_t SH_FLD_PB_PARITY_ERROR = 13619; // 5
+static const uint64_t SH_FLD_PB_PARITY_ERR_MASK = 13620; // 1
+static const uint64_t SH_FLD_PB_PURGE_DONE_LVL = 13621; // 6
+static const uint64_t SH_FLD_PB_PURGE_PLS = 13622; // 6
+static const uint64_t SH_FLD_PB_RCMDX_CI_ERR1 = 13623; // 1
+static const uint64_t SH_FLD_PB_RCMDX_CI_ERR2 = 13624; // 1
+static const uint64_t SH_FLD_PB_RCMDX_CI_ERR3 = 13625; // 1
+static const uint64_t SH_FLD_PB_RDADRERR_FW = 13626; // 1
+static const uint64_t SH_FLD_PB_RDADRERR_FW_MASK = 13627; // 1
+static const uint64_t SH_FLD_PB_RDDATATO_FW = 13628; // 1
+static const uint64_t SH_FLD_PB_RDDATATO_FW_MASK = 13629; // 1
+static const uint64_t SH_FLD_PB_STOP = 13630; // 1
+static const uint64_t SH_FLD_PB_SUE_FW = 13631; // 1
+static const uint64_t SH_FLD_PB_SUE_FW_MASK = 13632; // 1
+static const uint64_t SH_FLD_PB_UE_FW = 13633; // 1
+static const uint64_t SH_FLD_PB_UE_FW_MASK = 13634; // 1
+static const uint64_t SH_FLD_PB_UNEXPCRESP = 13635; // 1
+static const uint64_t SH_FLD_PB_UNEXPCRESP_MASK = 13636; // 1
+static const uint64_t SH_FLD_PB_UNEXPDATA = 13637; // 1
+static const uint64_t SH_FLD_PB_UNEXPDATA_MASK = 13638; // 1
+static const uint64_t SH_FLD_PB_WRADRERR_FW = 13639; // 1
+static const uint64_t SH_FLD_PB_WRADRERR_FW_MASK = 13640; // 1
+static const uint64_t SH_FLD_PB_X0_FIR_ERR = 13641; // 2
+static const uint64_t SH_FLD_PB_X1_FIR_ERR = 13642; // 2
+static const uint64_t SH_FLD_PB_X2_FIR_ERR = 13643; // 2
+static const uint64_t SH_FLD_PB_X3_FIR_ERR = 13644; // 2
+static const uint64_t SH_FLD_PB_X4_FIR_ERR = 13645; // 2
+static const uint64_t SH_FLD_PB_X5_FIR_ERR = 13646; // 2
+static const uint64_t SH_FLD_PB_X6_FIR_ERR = 13647; // 2
+static const uint64_t SH_FLD_PB_XLAT_DATA_SUE = 13648; // 1
+static const uint64_t SH_FLD_PB_XLAT_DATA_UE = 13649; // 1
+static const uint64_t SH_FLD_PCB = 13650; // 3
+static const uint64_t SH_FLD_PCBMUX_GRANT_C0 = 13651; // 12
+static const uint64_t SH_FLD_PCBMUX_GRANT_C1 = 13652; // 12
+static const uint64_t SH_FLD_PCBMUX_REQ_C0 = 13653; // 12
+static const uint64_t SH_FLD_PCBMUX_REQ_C1 = 13654; // 12
+static const uint64_t SH_FLD_PCBQ_N_INFO = 13655; // 24
+static const uint64_t SH_FLD_PCBQ_N_INFO_LEN = 13656; // 24
+static const uint64_t SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 13657; // 43
+static const uint64_t SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 13658; // 43
+static const uint64_t SH_FLD_PCB_ADDRESS_PARITY = 13659; // 43
+static const uint64_t SH_FLD_PCB_COMMAND_PARITY = 13660; // 43
+static const uint64_t SH_FLD_PCB_EP_RESET = 13661; // 43
+static const uint64_t SH_FLD_PCB_ERROR = 13662; // 43
+static const uint64_t SH_FLD_PCB_FSM = 13663; // 43
+static const uint64_t SH_FLD_PCB_IDLE = 13664; // 43
+static const uint64_t SH_FLD_PCB_INTERFACE = 13665; // 43
+static const uint64_t SH_FLD_PCB_INTERRUPT_PROTOCOL = 13666; // 30
+static const uint64_t SH_FLD_PCB_INTR_TYPE_A_CORE_N = 13667; // 144
+static const uint64_t SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN = 13668; // 144
+static const uint64_t SH_FLD_PCB_INTR_TYPE_A_QUAD_N = 13669; // 12
+static const uint64_t SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN = 13670; // 12
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_0 = 13671; // 8
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_1 = 13672; // 8
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_10 = 13673; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_11 = 13674; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_12 = 13675; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_13 = 13676; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_14 = 13677; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_15 = 13678; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_16 = 13679; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_17 = 13680; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_18 = 13681; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_19 = 13682; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_2 = 13683; // 8
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_20 = 13684; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_21 = 13685; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_22 = 13686; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_23 = 13687; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_3 = 13688; // 8
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_4 = 13689; // 8
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_5 = 13690; // 8
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_6 = 13691; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_7 = 13692; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_8 = 13693; // 6
+static const uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_9 = 13694; // 6
+static const uint64_t SH_FLD_PCB_LEN = 13695; // 2
+static const uint64_t SH_FLD_PCB_MASK = 13696; // 43
+static const uint64_t SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 13697; // 43
+static const uint64_t SH_FLD_PCB_REQUEST_SINCE_RESET = 13698; // 43
+static const uint64_t SH_FLD_PCB_RESET_DC = 13699; // 3
+static const uint64_t SH_FLD_PCB_TMP = 13700; // 1
+static const uint64_t SH_FLD_PCB_TMP_LEN = 13701; // 1
+static const uint64_t SH_FLD_PCB_WDATA_PARITY = 13702; // 43
+static const uint64_t SH_FLD_PCC_CORE_INTF_QUIESCE_C0 = 13703; // 12
+static const uint64_t SH_FLD_PCC_CORE_INTF_QUIESCE_C1 = 13704; // 12
+static const uint64_t SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS = 13705; // 6
+static const uint64_t SH_FLD_PCIE_REQUEST_ACCESS_ERROR = 13706; // 6
+static const uint64_t SH_FLD_PCLKDIFSEL = 13707; // 10
+static const uint64_t SH_FLD_PCLKSEL = 13708; // 14
+static const uint64_t SH_FLD_PCLKSEL_LEN = 13709; // 14
+static const uint64_t SH_FLD_PC_CAL_PCFSM_1HOT = 13710; // 8
+static const uint64_t SH_FLD_PC_CRD_AVAIL_PERR = 13711; // 1
+static const uint64_t SH_FLD_PC_CRD_PERR = 13712; // 1
+static const uint64_t SH_FLD_PC_DISABLE_DROOP = 13713; // 24
+static const uint64_t SH_FLD_PC_ERR_STATUS0 = 13714; // 8
+static const uint64_t SH_FLD_PC_ERR_STATUS0_LEN = 13715; // 8
+static const uint64_t SH_FLD_PC_FATAL_ERROR_0_2 = 13716; // 1
+static const uint64_t SH_FLD_PC_FATAL_ERROR_0_2_LEN = 13717; // 1
+static const uint64_t SH_FLD_PC_FUSED_CORE_MODE = 13718; // 12
+static const uint64_t SH_FLD_PC_INFO_ERROR_0_2 = 13719; // 1
+static const uint64_t SH_FLD_PC_INFO_ERROR_0_2_LEN = 13720; // 1
+static const uint64_t SH_FLD_PC_INIT_CAL_ERR = 13721; // 8
+static const uint64_t SH_FLD_PC_INIT_CAL_ERR_LEN = 13722; // 8
+static const uint64_t SH_FLD_PC_INSTR_RUNNING_C0 = 13723; // 12
+static const uint64_t SH_FLD_PC_INSTR_RUNNING_C1 = 13724; // 12
+static const uint64_t SH_FLD_PC_INTR_PENDING_C0 = 13725; // 24
+static const uint64_t SH_FLD_PC_INTR_PENDING_C1 = 13726; // 24
+static const uint64_t SH_FLD_PC_NON_HV_RUNNING_C0 = 13727; // 12
+static const uint64_t SH_FLD_PC_NON_HV_RUNNING_C0_LEN = 13728; // 12
+static const uint64_t SH_FLD_PC_NON_HV_RUNNING_C1 = 13729; // 12
+static const uint64_t SH_FLD_PC_NON_HV_RUNNING_C1_LEN = 13730; // 12
+static const uint64_t SH_FLD_PC_PE = 13731; // 8
+static const uint64_t SH_FLD_PC_PM_STATE_ACTIVE_C0 = 13732; // 24
+static const uint64_t SH_FLD_PC_PM_STATE_ACTIVE_C1 = 13733; // 24
+static const uint64_t SH_FLD_PC_PRIORITY_LIMIT_0_3 = 13734; // 1
+static const uint64_t SH_FLD_PC_PRIORITY_LIMIT_0_3_LEN = 13735; // 1
+static const uint64_t SH_FLD_PC_RECOV_ERROR_0_2 = 13736; // 1
+static const uint64_t SH_FLD_PC_RECOV_ERROR_0_2_LEN = 13737; // 1
+static const uint64_t SH_FLD_PC_SLICE_EN_ENC = 13738; // 1
+static const uint64_t SH_FLD_PC_SLICE_EN_ENC_LEN = 13739; // 1
+static const uint64_t SH_FLD_PC_TEST = 13740; // 1
+static const uint64_t SH_FLD_PC_TP_TRIG_SEL = 13741; // 43
+static const uint64_t SH_FLD_PC_TP_TRIG_SEL_LEN = 13742; // 43
+static const uint64_t SH_FLD_PC_UNMASKED_ATTN_C0 = 13743; // 12
+static const uint64_t SH_FLD_PC_UNMASKED_ATTN_C1 = 13744; // 12
+static const uint64_t SH_FLD_PDWN = 13745; // 5
+static const uint64_t SH_FLD_PDWN_LITE = 13746; // 140
+static const uint64_t SH_FLD_PDWN_LITE_CONTROLS = 13747; // 72
+static const uint64_t SH_FLD_PDWN_LITE_CONTROLS_LEN = 13748; // 72
+static const uint64_t SH_FLD_PDWN_LITE_DISABLE = 13749; // 8
+static const uint64_t SH_FLD_PE = 13750; // 45
+static const uint64_t SH_FLD_PE0_CXA_LINKDOWN_ERRHOLD = 13751; // 2
+static const uint64_t SH_FLD_PE1_CXA_LINKDOWN_ERRHOLD = 13752; // 2
+static const uint64_t SH_FLD_PEAK_ENABLE_DAC_CFG = 13753; // 4
+static const uint64_t SH_FLD_PEAK_INIT_CFG = 13754; // 6
+static const uint64_t SH_FLD_PEAK_INIT_CFG_LEN = 13755; // 6
+static const uint64_t SH_FLD_PEAK_INIT_TIMEOUT = 13756; // 6
+static const uint64_t SH_FLD_PEAK_INIT_TIMEOUT_LEN = 13757; // 6
+static const uint64_t SH_FLD_PEAK_RECAL_CFG = 13758; // 6
+static const uint64_t SH_FLD_PEAK_RECAL_CFG_LEN = 13759; // 6
+static const uint64_t SH_FLD_PEAK_RECAL_TIMEOUT = 13760; // 6
+static const uint64_t SH_FLD_PEAK_RECAL_TIMEOUT_LEN = 13761; // 6
+static const uint64_t SH_FLD_PEAK_TUNE = 13762; // 4
+static const uint64_t SH_FLD_PECE_C_N_T0 = 13763; // 24
+static const uint64_t SH_FLD_PECE_C_N_T0_LEN = 13764; // 24
+static const uint64_t SH_FLD_PECE_C_N_T1 = 13765; // 24
+static const uint64_t SH_FLD_PECE_C_N_T1_LEN = 13766; // 24
+static const uint64_t SH_FLD_PECE_C_N_T2 = 13767; // 24
+static const uint64_t SH_FLD_PECE_C_N_T2_LEN = 13768; // 24
+static const uint64_t SH_FLD_PECE_C_N_T3 = 13769; // 24
+static const uint64_t SH_FLD_PECE_C_N_T3_LEN = 13770; // 24
+static const uint64_t SH_FLD_PECE_DECR = 13771; // 96
+static const uint64_t SH_FLD_PECE_DHDES = 13772; // 96
+static const uint64_t SH_FLD_PECE_DPDES = 13773; // 96
+static const uint64_t SH_FLD_PECE_HMAINT = 13774; // 96
+static const uint64_t SH_FLD_PECE_HYPV = 13775; // 96
+static const uint64_t SH_FLD_PECE_INTR_DISABLED = 13776; // 24
+static const uint64_t SH_FLD_PECE_OS_EXT = 13777; // 96
+static const uint64_t SH_FLD_PEEK_DATA1_0 = 13778; // 12
+static const uint64_t SH_FLD_PEEK_DATA1_0_LEN = 13779; // 12
+static const uint64_t SH_FLD_PEEK_DATA1_1 = 13780; // 12
+static const uint64_t SH_FLD_PEEK_DATA1_1_LEN = 13781; // 12
+static const uint64_t SH_FLD_PEEK_DATA1_2 = 13782; // 12
+static const uint64_t SH_FLD_PEEK_DATA1_2_LEN = 13783; // 12
+static const uint64_t SH_FLD_PEEK_DATA1_3 = 13784; // 12
+static const uint64_t SH_FLD_PEEK_DATA1_3_LEN = 13785; // 12
+static const uint64_t SH_FLD_PEND = 13786; // 8
+static const uint64_t SH_FLD_PENDING_SOURCE = 13787; // 30
+static const uint64_t SH_FLD_PENDING_SOURCE_LEN = 13788; // 30
+static const uint64_t SH_FLD_PERFMON_COUNTER = 13789; // 5
+static const uint64_t SH_FLD_PERFMON_COUNTER_1 = 13790; // 5
+static const uint64_t SH_FLD_PERFMON_COUNTER_1_LEN = 13791; // 5
+static const uint64_t SH_FLD_PERFMON_COUNTER_2 = 13792; // 5
+static const uint64_t SH_FLD_PERFMON_COUNTER_2_LEN = 13793; // 5
+static const uint64_t SH_FLD_PERFMON_COUNTER_3 = 13794; // 5
+static const uint64_t SH_FLD_PERFMON_COUNTER_3_LEN = 13795; // 5
+static const uint64_t SH_FLD_PERFMON_COUNTER_4 = 13796; // 5
+static const uint64_t SH_FLD_PERFMON_COUNTER_4_LEN = 13797; // 5
+static const uint64_t SH_FLD_PERFMON_COUNTER_5 = 13798; // 5
+static const uint64_t SH_FLD_PERFMON_COUNTER_5_LEN = 13799; // 5
+static const uint64_t SH_FLD_PERFMON_COUNTER_6 = 13800; // 5
+static const uint64_t SH_FLD_PERFMON_COUNTER_6_LEN = 13801; // 5
+static const uint64_t SH_FLD_PERFMON_COUNTER_7 = 13802; // 5
+static const uint64_t SH_FLD_PERFMON_COUNTER_7_LEN = 13803; // 5
+static const uint64_t SH_FLD_PERFMON_COUNTER_LEN = 13804; // 5
+static const uint64_t SH_FLD_PERFORM_RDCLK_ALIGN = 13805; // 8
+static const uint64_t SH_FLD_PERFTRACE_ENABLE = 13806; // 5
+static const uint64_t SH_FLD_PERFTRACE_FIXED_WINDOW = 13807; // 5
+static const uint64_t SH_FLD_PERFTRACE_MODE = 13808; // 5
+static const uint64_t SH_FLD_PERFTRACE_MODE_LEN = 13809; // 5
+static const uint64_t SH_FLD_PERFTRACE_PRESCALE = 13810; // 5
+static const uint64_t SH_FLD_PERF_CASCADE = 13811; // 1
+static const uint64_t SH_FLD_PERF_CASCADE_LEN = 13812; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_CASCADE = 13813; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_CASCADE_LEN = 13814; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_DISABLE_PMISC = 13815; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_ENABLE = 13816; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_EVENTS = 13817; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_EVENTS_LEN = 13818; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_FREEZEMODE = 13819; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C0 = 13820; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C0_LEN = 13821; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C1 = 13822; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C1_LEN = 13823; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C2 = 13824; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C2_LEN = 13825; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C3 = 13826; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_OPERATION_C3_LEN = 13827; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_PMISC_MODE = 13828; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C0 = 13829; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C0_LEN = 13830; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C1 = 13831; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C1_LEN = 13832; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C2 = 13833; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C2_LEN = 13834; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C3 = 13835; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C3_LEN = 13836; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_RESETMODE = 13837; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_SPARE = 13838; // 1
+static const uint64_t SH_FLD_PERF_CONFIG_SPARE_LEN = 13839; // 1
+static const uint64_t SH_FLD_PERF_DISABLE_PMISC = 13840; // 1
+static const uint64_t SH_FLD_PERF_ENABLE = 13841; // 2
+static const uint64_t SH_FLD_PERF_EVENT0 = 13842; // 1
+static const uint64_t SH_FLD_PERF_EVENT0_LEN = 13843; // 1
+static const uint64_t SH_FLD_PERF_EVENT1 = 13844; // 1
+static const uint64_t SH_FLD_PERF_EVENT1_LEN = 13845; // 1
+static const uint64_t SH_FLD_PERF_EVENT2 = 13846; // 1
+static const uint64_t SH_FLD_PERF_EVENT2_LEN = 13847; // 1
+static const uint64_t SH_FLD_PERF_EVENT3 = 13848; // 1
+static const uint64_t SH_FLD_PERF_EVENT3_LEN = 13849; // 1
+static const uint64_t SH_FLD_PERF_FREEZEMODE = 13850; // 1
+static const uint64_t SH_FLD_PERF_PE_MASK = 13851; // 1
+static const uint64_t SH_FLD_PERF_PE_MATCH = 13852; // 1
+static const uint64_t SH_FLD_PERF_PE_MATCH_LEN = 13853; // 1
+static const uint64_t SH_FLD_PERF_PMISC_MODE = 13854; // 1
+static const uint64_t SH_FLD_PERF_PRESCALE_C0 = 13855; // 1
+static const uint64_t SH_FLD_PERF_PRESCALE_C0_LEN = 13856; // 1
+static const uint64_t SH_FLD_PERF_PRESCALE_C1 = 13857; // 1
+static const uint64_t SH_FLD_PERF_PRESCALE_C1_LEN = 13858; // 1
+static const uint64_t SH_FLD_PERF_PRESCALE_C2 = 13859; // 1
+static const uint64_t SH_FLD_PERF_PRESCALE_C2_LEN = 13860; // 1
+static const uint64_t SH_FLD_PERF_PRESCALE_C3 = 13861; // 1
+static const uint64_t SH_FLD_PERF_PRESCALE_C3_LEN = 13862; // 1
+static const uint64_t SH_FLD_PERF_RESETMODE = 13863; // 1
+static const uint64_t SH_FLD_PERF_THRESH = 13864; // 8
+static const uint64_t SH_FLD_PERF_THRESH_LEN = 13865; // 8
+static const uint64_t SH_FLD_PERIODIC = 13866; // 56
+static const uint64_t SH_FLD_PERIODIC_CAL_REQ_EN = 13867; // 8
+static const uint64_t SH_FLD_PERIODIC_LEN = 13868; // 56
+static const uint64_t SH_FLD_PERSIST = 13869; // 8
+static const uint64_t SH_FLD_PERSIST_LEN = 13870; // 8
+static const uint64_t SH_FLD_PERV = 13871; // 215
+static const uint64_t SH_FLD_PERVASIVE_CAPT = 13872; // 6
+static const uint64_t SH_FLD_PER_ABORT = 13873; // 8
+static const uint64_t SH_FLD_PER_DUTY_CYCLE_SW = 13874; // 8
+static const uint64_t SH_FLD_PER_REPEAT_COUNT = 13875; // 8
+static const uint64_t SH_FLD_PER_REPEAT_COUNT_LEN = 13876; // 8
+static const uint64_t SH_FLD_PE_ADR_BAR_MODE = 13877; // 3
+static const uint64_t SH_FLD_PE_BLOCK_CQPB_PB_INIT = 13878; // 3
+static const uint64_t SH_FLD_PE_CAPP = 13879; // 3
+static const uint64_t SH_FLD_PE_CAPP_APC_ENG = 13880; // 3
+static const uint64_t SH_FLD_PE_CAPP_APC_ENG_LEN = 13881; // 3
+static const uint64_t SH_FLD_PE_CAPP_EN = 13882; // 3
+static const uint64_t SH_FLD_PE_CAPP_LEN = 13883; // 3
+static const uint64_t SH_FLD_PE_CAPP_NUM_MSG_ENG = 13884; // 3
+static const uint64_t SH_FLD_PE_CAPP_NUM_MSG_ENG_LEN = 13885; // 3
+static const uint64_t SH_FLD_PE_CAPP_P8_MODE = 13886; // 3
+static const uint64_t SH_FLD_PE_CHANNEL_STREAMING_EN = 13887; // 3
+static const uint64_t SH_FLD_PE_CONSTANT_EINJ = 13888; // 3
+static const uint64_t SH_FLD_PE_CQ_ECC_INJECT_ENABLE = 13889; // 3
+static const uint64_t SH_FLD_PE_CQ_PAR_INJECT_ENABLE = 13890; // 3
+static const uint64_t SH_FLD_PE_CQ_REGISTER_ARRAY = 13891; // 3
+static const uint64_t SH_FLD_PE_CQ_REGISTER_ARRAY_LEN = 13892; // 3
+static const uint64_t SH_FLD_PE_CQ_SRAM_ARRAY = 13893; // 3
+static const uint64_t SH_FLD_PE_CQ_SRAM_ARRAY_LEN = 13894; // 3
+static const uint64_t SH_FLD_PE_DISABLE_CQ_TCE_ARBITRATION = 13895; // 3
+static const uint64_t SH_FLD_PE_DISABLE_INJ_ON_RESEND = 13896; // 3
+static const uint64_t SH_FLD_PE_DISABLE_INTWR_SCOPE_GROUP = 13897; // 3
+static const uint64_t SH_FLD_PE_DISABLE_INTWR_SCOPE_NODE = 13898; // 3
+static const uint64_t SH_FLD_PE_DISABLE_INTWR_VG = 13899; // 3
+static const uint64_t SH_FLD_PE_DISABLE_MC_PREFETCH = 13900; // 3
+static const uint64_t SH_FLD_PE_DISABLE_OOO_MODE = 13901; // 3
+static const uint64_t SH_FLD_PE_DISABLE_PCI_CLK_CHECK = 13902; // 3
+static const uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_GROUP = 13903; // 3
+static const uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_NODAL = 13904; // 3
+static const uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_RNNN = 13905; // 3
+static const uint64_t SH_FLD_PE_DISABLE_RD_VG = 13906; // 3
+static const uint64_t SH_FLD_PE_DISABLE_TCE_ARBITRATION = 13907; // 3
+static const uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_GROUP = 13908; // 3
+static const uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_NODAL = 13909; // 3
+static const uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_RNNN = 13910; // 3
+static const uint64_t SH_FLD_PE_DISABLE_TCE_VG = 13911; // 3
+static const uint64_t SH_FLD_PE_DISABLE_WR_SCOPE_GROUP = 13912; // 3
+static const uint64_t SH_FLD_PE_DISABLE_WR_VG = 13913; // 3
+static const uint64_t SH_FLD_PE_DROPPACECOUNT = 13914; // 3
+static const uint64_t SH_FLD_PE_DROPPACECOUNT_LEN = 13915; // 3
+static const uint64_t SH_FLD_PE_DROPPACEINC = 13916; // 3
+static const uint64_t SH_FLD_PE_DROPPACEINC_LEN = 13917; // 3
+static const uint64_t SH_FLD_PE_DROPPRIORITYMASK = 13918; // 3
+static const uint64_t SH_FLD_PE_DROPPRIORITYMASK_LEN = 13919; // 3
+static const uint64_t SH_FLD_PE_ECC_INJECT_TYPE = 13920; // 3
+static const uint64_t SH_FLD_PE_ECC_INJECT_TYPE_LEN = 13921; // 3
+static const uint64_t SH_FLD_PE_ENABLE_CTAG_DROP_PRIORITY = 13922; // 3
+static const uint64_t SH_FLD_PE_ENABLE_DMAR_IOPACING = 13923; // 3
+static const uint64_t SH_FLD_PE_ENABLE_DMAW_IOPACING = 13924; // 3
+static const uint64_t SH_FLD_PE_ENABLE_ENH_FLOW = 13925; // 3
+static const uint64_t SH_FLD_PE_ENABLE_IO_CMD_PACING = 13926; // 3
+static const uint64_t SH_FLD_PE_ENABLE_NEW_FLOW_CACHE_INJECT = 13927; // 3
+static const uint64_t SH_FLD_PE_ENABLE_RD_SKIP_GROUP = 13928; // 3
+static const uint64_t SH_FLD_PE_ENABLE_TCE_SKIP_GROUP = 13929; // 3
+static const uint64_t SH_FLD_PE_ENHANCED_PEER2PEER_MODDE = 13930; // 9
+static const uint64_t SH_FLD_PE_ETU_RESET = 13931; // 9
+static const uint64_t SH_FLD_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW = 13932; // 3
+static const uint64_t SH_FLD_PE_HANG_SM_ON_ARE = 13933; // 3
+static const uint64_t SH_FLD_PE_IGNORE_SFSTAT = 13934; // 3
+static const uint64_t SH_FLD_PE_INBOUND_ACTIVE = 13935; // 9
+static const uint64_t SH_FLD_PE_INT_BAR = 13936; // 9
+static const uint64_t SH_FLD_PE_INT_BAR_EN = 13937; // 9
+static const uint64_t SH_FLD_PE_INT_BAR_LEN = 13938; // 9
+static const uint64_t SH_FLD_PE_ISMB_ERROR_INJECT = 13939; // 3
+static const uint64_t SH_FLD_PE_ISMB_ERROR_INJECT_LEN = 13940; // 3
+static const uint64_t SH_FLD_PE_LEN = 13941; // 45
+static const uint64_t SH_FLD_PE_MMIO_BAR0 = 13942; // 9
+static const uint64_t SH_FLD_PE_MMIO_BAR0_EN = 13943; // 9
+static const uint64_t SH_FLD_PE_MMIO_BAR0_LEN = 13944; // 9
+static const uint64_t SH_FLD_PE_MMIO_BAR1 = 13945; // 9
+static const uint64_t SH_FLD_PE_MMIO_BAR1_EN = 13946; // 9
+static const uint64_t SH_FLD_PE_MMIO_BAR1_LEN = 13947; // 9
+static const uint64_t SH_FLD_PE_MMIO_MASK0 = 13948; // 9
+static const uint64_t SH_FLD_PE_MMIO_MASK0_LEN = 13949; // 9
+static const uint64_t SH_FLD_PE_MMIO_MASK1 = 13950; // 9
+static const uint64_t SH_FLD_PE_MMIO_MASK1_LEN = 13951; // 9
+static const uint64_t SH_FLD_PE_OSMB_DATASTART_MODE = 13952; // 3
+static const uint64_t SH_FLD_PE_OSMB_DATASTART_MODE_LEN = 13953; // 3
+static const uint64_t SH_FLD_PE_OSMB_EARLYEMPTY_MODE = 13954; // 3
+static const uint64_t SH_FLD_PE_OSMB_EARLYEMPTY_MODE_LEN = 13955; // 3
+static const uint64_t SH_FLD_PE_OSMB_EARLY_START = 13956; // 3
+static const uint64_t SH_FLD_PE_OSMB_EARLY_START_LEN = 13957; // 3
+static const uint64_t SH_FLD_PE_OSMB_HOL_BLK_CNT = 13958; // 3
+static const uint64_t SH_FLD_PE_OSMB_HOL_BLK_CNT_LEN = 13959; // 3
+static const uint64_t SH_FLD_PE_OUTBOUND_ACTIVE = 13960; // 9
+static const uint64_t SH_FLD_PE_PCIE_CLK_TRACE_EN = 13961; // 3
+static const uint64_t SH_FLD_PE_PCI_CLK_TRACE_SEL = 13962; // 3
+static const uint64_t SH_FLD_PE_PCI_CLK_TRACE_SEL_LEN = 13963; // 3
+static const uint64_t SH_FLD_PE_PEER2PEER_MODDE = 13964; // 9
+static const uint64_t SH_FLD_PE_PERFMON_EN = 13965; // 3
+static const uint64_t SH_FLD_PE_PERFMON_EN_LEN = 13966; // 3
+static const uint64_t SH_FLD_PE_PERFMON_READ_TYPE = 13967; // 3
+static const uint64_t SH_FLD_PE_PERFMON_READ_TYPE_LEN = 13968; // 3
+static const uint64_t SH_FLD_PE_PHB_BAR = 13969; // 9
+static const uint64_t SH_FLD_PE_PHB_BAR_EN = 13970; // 9
+static const uint64_t SH_FLD_PE_PHB_BAR_LEN = 13971; // 9
+static const uint64_t SH_FLD_PE_PMON_MUX_BYTE0 = 13972; // 3
+static const uint64_t SH_FLD_PE_PMON_MUX_BYTE0_LEN = 13973; // 3
+static const uint64_t SH_FLD_PE_PMON_MUX_BYTE1 = 13974; // 3
+static const uint64_t SH_FLD_PE_PMON_MUX_BYTE1_LEN = 13975; // 3
+static const uint64_t SH_FLD_PE_PMON_MUX_BYTE2 = 13976; // 3
+static const uint64_t SH_FLD_PE_PMON_MUX_BYTE2_LEN = 13977; // 3
+static const uint64_t SH_FLD_PE_PMON_MUX_BYTE3 = 13978; // 3
+static const uint64_t SH_FLD_PE_PMON_MUX_BYTE3_LEN = 13979; // 3
+static const uint64_t SH_FLD_PE_QFIFO_HOLD_MODE = 13980; // 3
+static const uint64_t SH_FLD_PE_QFIFO_HOLD_MODE_LEN = 13981; // 3
+static const uint64_t SH_FLD_PE_RD_TIMEOUT_MASK = 13982; // 3
+static const uint64_t SH_FLD_PE_RD_TIMEOUT_MASK_LEN = 13983; // 3
+static const uint64_t SH_FLD_PE_RD_WRITE_ORDERING = 13984; // 3
+static const uint64_t SH_FLD_PE_RD_WRITE_ORDERING_LEN = 13985; // 3
+static const uint64_t SH_FLD_PE_RTYDROPDIVIDER = 13986; // 3
+static const uint64_t SH_FLD_PE_RTYDROPDIVIDER_LEN = 13987; // 3
+static const uint64_t SH_FLD_PE_SELECT_ETU_TRACE = 13988; // 3
+static const uint64_t SH_FLD_PE_STOP_STATE_SIGNALED = 13989; // 6
+static const uint64_t SH_FLD_PE_STQ_ALLOCATION = 13990; // 3
+static const uint64_t SH_FLD_PE_TX_RESP_HWM = 13991; // 3
+static const uint64_t SH_FLD_PE_TX_RESP_HWM_LEN = 13992; // 3
+static const uint64_t SH_FLD_PE_TX_RESP_LWM = 13993; // 3
+static const uint64_t SH_FLD_PE_TX_RESP_LWM_LEN = 13994; // 3
+static const uint64_t SH_FLD_PE_WR_CACHE_INJECT_MODE = 13995; // 3
+static const uint64_t SH_FLD_PE_WR_CACHE_INJECT_MODE_LEN = 13996; // 3
+static const uint64_t SH_FLD_PE_WR_STRICT_ORDER_MODE = 13997; // 3
+static const uint64_t SH_FLD_PE_WR_TIMEOUT_MASK = 13998; // 3
+static const uint64_t SH_FLD_PE_WR_TIMEOUT_MASK_LEN = 13999; // 3
+static const uint64_t SH_FLD_PFD360SEL = 14000; // 4
+static const uint64_t SH_FLD_PFET_SEQ_PROGRAM = 14001; // 30
+static const uint64_t SH_FLD_PFIRACTION0 = 14002; // 9
+static const uint64_t SH_FLD_PFIRACTION0_LEN = 14003; // 9
+static const uint64_t SH_FLD_PFIRACTION1 = 14004; // 9
+static const uint64_t SH_FLD_PFIRACTION1_LEN = 14005; // 9
+static const uint64_t SH_FLD_PFIRMASK = 14006; // 9
+static const uint64_t SH_FLD_PFIRMASK_LEN = 14007; // 9
+static const uint64_t SH_FLD_PFIRPFIR = 14008; // 9
+static const uint64_t SH_FLD_PFIRPFIR_LEN = 14009; // 9
+static const uint64_t SH_FLD_PFREQ0 = 14010; // 24
+static const uint64_t SH_FLD_PFREQ0_LEN = 14011; // 24
+static const uint64_t SH_FLD_PFREQ1 = 14012; // 24
+static const uint64_t SH_FLD_PFREQ1_LEN = 14013; // 24
+static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH0 = 14014; // 8
+static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH0_LEN = 14015; // 8
+static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH1 = 14016; // 8
+static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH1_LEN = 14017; // 8
+static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH2 = 14018; // 8
+static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH2_LEN = 14019; // 8
+static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH3 = 14020; // 8
+static const uint64_t SH_FLD_PF_CONF_RETRY_THRESH3_LEN = 14021; // 8
+static const uint64_t SH_FLD_PF_DROP_CNT_THRESH = 14022; // 4
+static const uint64_t SH_FLD_PF_DROP_CNT_THRESH_LEN = 14023; // 4
+static const uint64_t SH_FLD_PF_DROP_VALUE0 = 14024; // 8
+static const uint64_t SH_FLD_PF_DROP_VALUE0_LEN = 14025; // 8
+static const uint64_t SH_FLD_PF_DROP_VALUE1 = 14026; // 8
+static const uint64_t SH_FLD_PF_DROP_VALUE1_LEN = 14027; // 8
+static const uint64_t SH_FLD_PF_DROP_VALUE2 = 14028; // 8
+static const uint64_t SH_FLD_PF_DROP_VALUE2_LEN = 14029; // 8
+static const uint64_t SH_FLD_PF_DROP_VALUE3 = 14030; // 8
+static const uint64_t SH_FLD_PF_DROP_VALUE3_LEN = 14031; // 8
+static const uint64_t SH_FLD_PF_MACHINE_HANG = 14032; // 12
+static const uint64_t SH_FLD_PF_MACHINE_W4DT_HANG = 14033; // 12
+static const uint64_t SH_FLD_PF_PROMOTE_ASYNC_IF = 14034; // 8
+static const uint64_t SH_FLD_PF_PROMOTE_ERR_INJ = 14035; // 8
+static const uint64_t SH_FLD_PF_UNSOLICITED_CRESP = 14036; // 12
+static const uint64_t SH_FLD_PF_UNSOLICITED_DATA = 14037; // 12
+static const uint64_t SH_FLD_PGMIGR1_BAR = 14038; // 1
+static const uint64_t SH_FLD_PGMIGR1_BAR_LEN = 14039; // 1
+static const uint64_t SH_FLD_PGMIGR1_PGSZ = 14040; // 1
+static const uint64_t SH_FLD_PGMIGR1_PGSZ_LEN = 14041; // 1
+static const uint64_t SH_FLD_PGMIGR1_VAL = 14042; // 1
+static const uint64_t SH_FLD_PGMIGR2_BAR = 14043; // 1
+static const uint64_t SH_FLD_PGMIGR2_BAR_LEN = 14044; // 1
+static const uint64_t SH_FLD_PGMIGR2_PGSZ = 14045; // 1
+static const uint64_t SH_FLD_PGMIGR2_PGSZ_LEN = 14046; // 1
+static const uint64_t SH_FLD_PGMIGR2_VAL = 14047; // 1
+static const uint64_t SH_FLD_PGMIGR3_BAR = 14048; // 1
+static const uint64_t SH_FLD_PGMIGR3_BAR_LEN = 14049; // 1
+static const uint64_t SH_FLD_PGMIGR3_PGSZ = 14050; // 1
+static const uint64_t SH_FLD_PGMIGR3_PGSZ_LEN = 14051; // 1
+static const uint64_t SH_FLD_PGMIGR3_VAL = 14052; // 1
+static const uint64_t SH_FLD_PGMIGR4_BAR = 14053; // 1
+static const uint64_t SH_FLD_PGMIGR4_BAR_LEN = 14054; // 1
+static const uint64_t SH_FLD_PGMIGR4_PGSZ = 14055; // 1
+static const uint64_t SH_FLD_PGMIGR4_PGSZ_LEN = 14056; // 1
+static const uint64_t SH_FLD_PGMIGR4_VAL = 14057; // 1
+static const uint64_t SH_FLD_PGMIGR5_BAR = 14058; // 1
+static const uint64_t SH_FLD_PGMIGR5_BAR_LEN = 14059; // 1
+static const uint64_t SH_FLD_PGMIGR5_PGSZ = 14060; // 1
+static const uint64_t SH_FLD_PGMIGR5_PGSZ_LEN = 14061; // 1
+static const uint64_t SH_FLD_PGMIGR5_VAL = 14062; // 1
+static const uint64_t SH_FLD_PGMIGR6_BAR = 14063; // 1
+static const uint64_t SH_FLD_PGMIGR6_BAR_LEN = 14064; // 1
+static const uint64_t SH_FLD_PGMIGR6_PGSZ = 14065; // 1
+static const uint64_t SH_FLD_PGMIGR6_PGSZ_LEN = 14066; // 1
+static const uint64_t SH_FLD_PGMIGR6_VAL = 14067; // 1
+static const uint64_t SH_FLD_PGMIGR7_BAR = 14068; // 1
+static const uint64_t SH_FLD_PGMIGR7_BAR_LEN = 14069; // 1
+static const uint64_t SH_FLD_PGMIGR7_PGSZ = 14070; // 1
+static const uint64_t SH_FLD_PGMIGR7_PGSZ_LEN = 14071; // 1
+static const uint64_t SH_FLD_PGMIGR7_VAL = 14072; // 1
+static const uint64_t SH_FLD_PGOFFIRSTLS = 14073; // 1
+static const uint64_t SH_FLD_PGOFFIRSTLS_LEN = 14074; // 1
+static const uint64_t SH_FLD_PGOFNEXTLS = 14075; // 1
+static const uint64_t SH_FLD_PGOFNEXTLS_LEN = 14076; // 1
+static const uint64_t SH_FLD_PGOOD_TIMEOUT_SEL = 14077; // 4
+static const uint64_t SH_FLD_PGOOD_TIMEOUT_SEL_LEN = 14078; // 4
+static const uint64_t SH_FLD_PG_MIG_DISABLED_ERR = 14079; // 2
+static const uint64_t SH_FLD_PG_MIG_SIZE_MISMATCH_ERR = 14080; // 2
+static const uint64_t SH_FLD_PHASEFB = 14081; // 4
+static const uint64_t SH_FLD_PHASEFB_LEN = 14082; // 4
+static const uint64_t SH_FLD_PHBCSR_SPARE = 14083; // 1
+static const uint64_t SH_FLD_PHB_FILTER_CNTL = 14084; // 2
+static const uint64_t SH_FLD_PHB_FILTER_CNTL_LEN = 14085; // 2
+static const uint64_t SH_FLD_PHB_LINK_DOWN = 14086; // 4
+static const uint64_t SH_FLD_PHY = 14087; // 6
+static const uint64_t SH_FLD_PHYP_SCOPE = 14088; // 1
+static const uint64_t SH_FLD_PHY_LEN = 14089; // 6
+static const uint64_t SH_FLD_PHY_PARITY_HOLD_OUT = 14090; // 8
+static const uint64_t SH_FLD_PIB2PCB_DC = 14091; // 3
+static const uint64_t SH_FLD_PIBI2CM_PIB_SLAVE_ID = 14092; // 1
+static const uint64_t SH_FLD_PIBI2CM_PIB_SLAVE_ID_LEN = 14093; // 1
+static const uint64_t SH_FLD_PIB_0 = 14094; // 2
+static const uint64_t SH_FLD_PIB_0_LEN = 14095; // 2
+static const uint64_t SH_FLD_PIB_1 = 14096; // 2
+static const uint64_t SH_FLD_PIB_1_LEN = 14097; // 2
+static const uint64_t SH_FLD_PIB_2 = 14098; // 2
+static const uint64_t SH_FLD_PIB_2_LEN = 14099; // 2
+static const uint64_t SH_FLD_PIB_3 = 14100; // 2
+static const uint64_t SH_FLD_PIB_3_LEN = 14101; // 2
+static const uint64_t SH_FLD_PIB_ABORT = 14102; // 2
+static const uint64_t SH_FLD_PIB_ADDR = 14103; // 2
+static const uint64_t SH_FLD_PIB_ADDR_LEN = 14104; // 2
+static const uint64_t SH_FLD_PIB_ADDR_P = 14105; // 1
+static const uint64_t SH_FLD_PIB_ADDR_P_ERR = 14106; // 1
+static const uint64_t SH_FLD_PIB_BUSY = 14107; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_0 = 14108; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_0_LEN = 14109; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_1 = 14110; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_1_LEN = 14111; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_2 = 14112; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_2_LEN = 14113; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_3 = 14114; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_ADDR_3_LEN = 14115; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_0 = 14116; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_1 = 14117; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_2 = 14118; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_3 = 14119; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_0 = 14120; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_1 = 14121; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_2 = 14122; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_3 = 14123; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_0 = 14124; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_1 = 14125; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_2 = 14126; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_3 = 14127; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_0 = 14128; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_1 = 14129; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_2 = 14130; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_3 = 14131; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_0 = 14132; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_1 = 14133; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_2 = 14134; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_3 = 14135; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_0 = 14136; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_0_LEN = 14137; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_1 = 14138; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_1_LEN = 14139; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_2 = 14140; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_2_LEN = 14141; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_3 = 14142; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_3_LEN = 14143; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_0 = 14144; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_0_LEN = 14145; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_1 = 14146; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_1_LEN = 14147; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_2 = 14148; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_2_LEN = 14149; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_3 = 14150; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_3_LEN = 14151; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_0 = 14152; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_0_LEN = 14153; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_1 = 14154; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_1_LEN = 14155; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_2 = 14156; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_2_LEN = 14157; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_3 = 14158; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_3_LEN = 14159; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_0 = 14160; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_0_LEN = 14161; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_1 = 14162; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_1_LEN = 14163; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_2 = 14164; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_2_LEN = 14165; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_3 = 14166; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_3_LEN = 14167; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_0 = 14168; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_0_LEN = 14169; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_1 = 14170; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_1_LEN = 14171; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_2 = 14172; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_2_LEN = 14173; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_3 = 14174; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_3_LEN = 14175; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0 = 14176; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0_LEN = 14177; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1 = 14178; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1_LEN = 14179; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2 = 14180; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2_LEN = 14181; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3 = 14182; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3_LEN = 14183; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_0 = 14184; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_0_LEN = 14185; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_1 = 14186; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_1_LEN = 14187; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_2 = 14188; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_2_LEN = 14189; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_3 = 14190; // 1
+static const uint64_t SH_FLD_PIB_CNTR_REG_SPEED_3_LEN = 14191; // 1
+static const uint64_t SH_FLD_PIB_COMPONENT_BUSY = 14192; // 1
+static const uint64_t SH_FLD_PIB_DATA0TO7_0 = 14193; // 1
+static const uint64_t SH_FLD_PIB_DATA0TO7_0_LEN = 14194; // 1
+static const uint64_t SH_FLD_PIB_DATA0TO7_1 = 14195; // 1
+static const uint64_t SH_FLD_PIB_DATA0TO7_1_LEN = 14196; // 1
+static const uint64_t SH_FLD_PIB_DATA0TO7_2 = 14197; // 1
+static const uint64_t SH_FLD_PIB_DATA0TO7_2_LEN = 14198; // 1
+static const uint64_t SH_FLD_PIB_DATA0TO7_3 = 14199; // 1
+static const uint64_t SH_FLD_PIB_DATA0TO7_3_LEN = 14200; // 1
+static const uint64_t SH_FLD_PIB_DATAOP_PENDING = 14201; // 1
+static const uint64_t SH_FLD_PIB_DATA_P = 14202; // 1
+static const uint64_t SH_FLD_PIB_DATA_P_ERR = 14203; // 1
+static const uint64_t SH_FLD_PIB_ERROR_CODE = 14204; // 1
+static const uint64_t SH_FLD_PIB_ERROR_CODE_LEN = 14205; // 1
+static const uint64_t SH_FLD_PIB_FSM_STATE = 14206; // 1
+static const uint64_t SH_FLD_PIB_FSM_STATE_LEN = 14207; // 1
+static const uint64_t SH_FLD_PIB_HANG = 14208; // 1
+static const uint64_t SH_FLD_PIB_IFETCH_PENDING = 14209; // 1
+static const uint64_t SH_FLD_PIB_IMPRECISE_ERROR_PENDING = 14210; // 1
+static const uint64_t SH_FLD_PIB_MASTER_REQUEST = 14211; // 4
+static const uint64_t SH_FLD_PIB_MASTER_RSP_INFO = 14212; // 4
+static const uint64_t SH_FLD_PIB_MASTER_RSP_INFO_LEN = 14213; // 4
+static const uint64_t SH_FLD_PIB_RESET_DURING_PIB_ACCESS = 14214; // 4
+static const uint64_t SH_FLD_PIB_RESPONSE_INFO = 14215; // 1
+static const uint64_t SH_FLD_PIB_RESPONSE_INFO_LEN = 14216; // 1
+static const uint64_t SH_FLD_PIB_RSP_INFO = 14217; // 1
+static const uint64_t SH_FLD_PIB_RSP_INFO_LEN = 14218; // 1
+static const uint64_t SH_FLD_PIB_R_NW = 14219; // 1
+static const uint64_t SH_FLD_PIB_SLAVE_ADDR_INVALID = 14220; // 4
+static const uint64_t SH_FLD_PIB_SLAVE_ADDR_PARITY = 14221; // 4
+static const uint64_t SH_FLD_PIB_SLAVE_DATA_PARITY = 14222; // 4
+static const uint64_t SH_FLD_PIB_SLAVE_READ_INVALID = 14223; // 4
+static const uint64_t SH_FLD_PIB_SLAVE_WRITE_INVALID = 14224; // 4
+static const uint64_t SH_FLD_PID = 14225; // 273
+static const uint64_t SH_FLD_PID_LEN = 14226; // 273
+static const uint64_t SH_FLD_PID_MASK = 14227; // 1
+static const uint64_t SH_FLD_PID_MASK_LEN = 14228; // 1
+static const uint64_t SH_FLD_PIPELINE_ENABLE = 14229; // 1
+static const uint64_t SH_FLD_PIPE_COUNTER = 14230; // 1
+static const uint64_t SH_FLD_PIPE_COUNTER_LEN = 14231; // 1
+static const uint64_t SH_FLD_PIPE_MARGIN = 14232; // 48
+static const uint64_t SH_FLD_PIPE_SEL = 14233; // 120
+static const uint64_t SH_FLD_PIPE_SEL_LEN = 14234; // 48
+static const uint64_t SH_FLD_PI_ECC_CE = 14235; // 1
+static const uint64_t SH_FLD_PI_ECC_SUE = 14236; // 1
+static const uint64_t SH_FLD_PI_ECC_UE = 14237; // 1
+static const uint64_t SH_FLD_PLBARB_LOCKERR = 14238; // 1
+static const uint64_t SH_FLD_PLLCVHOLD = 14239; // 6
+static const uint64_t SH_FLD_PLLFMAX = 14240; // 6
+static const uint64_t SH_FLD_PLLFMIN = 14241; // 6
+static const uint64_t SH_FLD_PLLFORCE_OUT_EN = 14242; // 43
+static const uint64_t SH_FLD_PLLLOCK = 14243; // 4
+static const uint64_t SH_FLD_PLLLOCK_0_FILTER_PLL_NEST = 14244; // 1
+static const uint64_t SH_FLD_PLLLOCK_1_FILTER_PLL_MC = 14245; // 1
+static const uint64_t SH_FLD_PLLLOCK_2_XBUS = 14246; // 1
+static const uint64_t SH_FLD_PLLLOCK_3_NEST = 14247; // 1
+static const uint64_t SH_FLD_PLLREFSEL = 14248; // 3
+static const uint64_t SH_FLD_PLLREFSEL_LEN = 14249; // 3
+static const uint64_t SH_FLD_PLLRESET = 14250; // 6
+static const uint64_t SH_FLD_PLL_BNDY_BYPASS_EN = 14251; // 43
+static const uint64_t SH_FLD_PLL_BYPASS = 14252; // 43
+static const uint64_t SH_FLD_PLL_CLKIN_SEL = 14253; // 43
+static const uint64_t SH_FLD_PLL_DESTOUT = 14254; // 43
+static const uint64_t SH_FLD_PLL_LOCK_TIMEOUT_SEL = 14255; // 4
+static const uint64_t SH_FLD_PLL_LOCK_TIMEOUT_SEL_LEN = 14256; // 4
+static const uint64_t SH_FLD_PLL_REFCLKSEL_SCOM_EN = 14257; // 4
+static const uint64_t SH_FLD_PLL_RESET = 14258; // 43
+static const uint64_t SH_FLD_PLL_TEST_EN = 14259; // 43
+static const uint64_t SH_FLD_PLL_UNLOCK = 14260; // 43
+static const uint64_t SH_FLD_PLL_UNLOCK_LEN = 14261; // 43
+static const uint64_t SH_FLD_PL_ERR = 14262; // 6
+static const uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_EN = 14263; // 12
+static const uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_NUM = 14264; // 12
+static const uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_NUM_LEN = 14265; // 12
+static const uint64_t SH_FLD_PM03_SMT_ROTATION_DIS = 14266; // 12
+static const uint64_t SH_FLD_PM07_TID_ROTATE_PLSS_RATE = 14267; // 12
+static const uint64_t SH_FLD_PM07_TID_ROTATE_PLSS_RATE_LEN = 14268; // 12
+static const uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_EN = 14269; // 12
+static const uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_NUM = 14270; // 12
+static const uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_NUM_LEN = 14271; // 12
+static const uint64_t SH_FLD_PM47_SMT_ROTATION_DIS = 14272; // 12
+static const uint64_t SH_FLD_PMCM_THRESHOLD = 14273; // 24
+static const uint64_t SH_FLD_PMCM_THRESHOLD_LEN = 14274; // 24
+static const uint64_t SH_FLD_PMCR_OVERRIDE_EN = 14275; // 12
+static const uint64_t SH_FLD_PMCR_UPDATE_C0 = 14276; // 12
+static const uint64_t SH_FLD_PMCR_UPDATE_C1 = 14277; // 12
+static const uint64_t SH_FLD_PMC_ENABLE = 14278; // 1
+static const uint64_t SH_FLD_PMC_O2S_0A_ONGOING = 14279; // 1
+static const uint64_t SH_FLD_PMC_O2S_0B_ONGOING = 14280; // 1
+static const uint64_t SH_FLD_PMC_O2S_1A_ONGOING = 14281; // 1
+static const uint64_t SH_FLD_PMC_O2S_1B_ONGOING = 14282; // 1
+static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE0_PENDING = 14283; // 1
+static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE1_PENDING = 14284; // 1
+static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE2_PENDING = 14285; // 1
+static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE3_PENDING = 14286; // 1
+static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE4_PENDING = 14287; // 1
+static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE5_PENDING = 14288; // 1
+static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE6_PENDING = 14289; // 1
+static const uint64_t SH_FLD_PMC_PCB_INTR_TYPE7_PENDING = 14290; // 1
+static const uint64_t SH_FLD_PMISC_CRESP_ADDR_ERR = 14291; // 12
+static const uint64_t SH_FLD_PMISC_MODE = 14292; // 9
+static const uint64_t SH_FLD_PMON_GROUP_SELECT = 14293; // 2
+static const uint64_t SH_FLD_PMON_GROUP_SELECT_LEN = 14294; // 2
+static const uint64_t SH_FLD_PMON_MUX_BYTE0_0_2 = 14295; // 1
+static const uint64_t SH_FLD_PMON_MUX_BYTE0_0_2_LEN = 14296; // 1
+static const uint64_t SH_FLD_PMON_MUX_BYTE1_0_2 = 14297; // 1
+static const uint64_t SH_FLD_PMON_MUX_BYTE1_0_2_LEN = 14298; // 1
+static const uint64_t SH_FLD_PMON_MUX_BYTE2_0_2 = 14299; // 1
+static const uint64_t SH_FLD_PMON_MUX_BYTE2_0_2_LEN = 14300; // 1
+static const uint64_t SH_FLD_PMON_MUX_BYTE3_0_2 = 14301; // 1
+static const uint64_t SH_FLD_PMON_MUX_BYTE3_0_2_LEN = 14302; // 1
+static const uint64_t SH_FLD_PMSR_OVERRIDE_EN = 14303; // 12
+static const uint64_t SH_FLD_PMU0145_EVENT0_MODE = 14304; // 2
+static const uint64_t SH_FLD_PMU0145_EVENT0_MODE_LEN = 14305; // 2
+static const uint64_t SH_FLD_PMU0145_EVENT1_MODE = 14306; // 2
+static const uint64_t SH_FLD_PMU0145_EVENT1_MODE_LEN = 14307; // 2
+static const uint64_t SH_FLD_PMU0145_EVENT2_MODE = 14308; // 2
+static const uint64_t SH_FLD_PMU0145_EVENT2_MODE_LEN = 14309; // 2
+static const uint64_t SH_FLD_PMU0145_EVENT3_MODE = 14310; // 2
+static const uint64_t SH_FLD_PMU0145_EVENT3_MODE_LEN = 14311; // 2
+static const uint64_t SH_FLD_PMU01_LINK_SELECT = 14312; // 2
+static const uint64_t SH_FLD_PMU0_ENABLE = 14313; // 2
+static const uint64_t SH_FLD_PMU0_SIZE = 14314; // 2
+static const uint64_t SH_FLD_PMU0_SIZE_LEN = 14315; // 2
+static const uint64_t SH_FLD_PMU1_ENABLE = 14316; // 2
+static const uint64_t SH_FLD_PMU1_SIZE = 14317; // 2
+static const uint64_t SH_FLD_PMU1_SIZE_LEN = 14318; // 2
+static const uint64_t SH_FLD_PMU2367_EVENT0_MODE = 14319; // 2
+static const uint64_t SH_FLD_PMU2367_EVENT0_MODE_LEN = 14320; // 2
+static const uint64_t SH_FLD_PMU2367_EVENT1_MODE = 14321; // 2
+static const uint64_t SH_FLD_PMU2367_EVENT1_MODE_LEN = 14322; // 2
+static const uint64_t SH_FLD_PMU2367_EVENT2_MODE = 14323; // 2
+static const uint64_t SH_FLD_PMU2367_EVENT2_MODE_LEN = 14324; // 2
+static const uint64_t SH_FLD_PMU2367_EVENT3_MODE = 14325; // 2
+static const uint64_t SH_FLD_PMU2367_EVENT3_MODE_LEN = 14326; // 2
+static const uint64_t SH_FLD_PMU23_LINK_SELECT = 14327; // 2
+static const uint64_t SH_FLD_PMU2_ENABLE = 14328; // 2
+static const uint64_t SH_FLD_PMU2_SIZE = 14329; // 2
+static const uint64_t SH_FLD_PMU2_SIZE_LEN = 14330; // 2
+static const uint64_t SH_FLD_PMU3_ENABLE = 14331; // 2
+static const uint64_t SH_FLD_PMU3_SIZE = 14332; // 2
+static const uint64_t SH_FLD_PMU3_SIZE_LEN = 14333; // 2
+static const uint64_t SH_FLD_PMU45_LINK_SELECT = 14334; // 2
+static const uint64_t SH_FLD_PMU4_ENABLE = 14335; // 2
+static const uint64_t SH_FLD_PMU5_ENABLE = 14336; // 2
+static const uint64_t SH_FLD_PMU67_LINK_SELECT = 14337; // 2
+static const uint64_t SH_FLD_PMU6_ENABLE = 14338; // 2
+static const uint64_t SH_FLD_PMU7_ENABLE = 14339; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT = 14340; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT_LEN = 14341; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER0_ENABLE = 14342; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER0_EVENT_SELECT = 14343; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER0_EVENT_SELECT_LEN = 14344; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER0_POSEDGE_SELECT = 14345; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT = 14346; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT_LEN = 14347; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER1_ENABLE = 14348; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER1_EVENT_SELECT = 14349; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER1_EVENT_SELECT_LEN = 14350; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER1_POSEDGE_SELECT = 14351; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT = 14352; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT_LEN = 14353; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER2_ENABLE = 14354; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER2_EVENT_SELECT = 14355; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER2_EVENT_SELECT_LEN = 14356; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER2_POSEDGE_SELECT = 14357; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT = 14358; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT_LEN = 14359; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER3_ENABLE = 14360; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER3_EVENT_SELECT = 14361; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER3_EVENT_SELECT_LEN = 14362; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER3_POSEDGE_SELECT = 14363; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER_FREEZE_MODE = 14364; // 2
+static const uint64_t SH_FLD_PMUA_COUNTER_RESET_MODE = 14365; // 2
+static const uint64_t SH_FLD_PMUA_PORT_SELECT = 14366; // 2
+static const uint64_t SH_FLD_PMUA_PORT_SELECT_LEN = 14367; // 2
+static const uint64_t SH_FLD_PMUA_PRESCALER_SELECT = 14368; // 2
+static const uint64_t SH_FLD_PMUA_PRESCALER_SELECT_LEN = 14369; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT = 14370; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT_LEN = 14371; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER0_ENABLE = 14372; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER0_EVENT_SELECT = 14373; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER0_EVENT_SELECT_LEN = 14374; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER0_POSEDGE_SELECT = 14375; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT = 14376; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT_LEN = 14377; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER1_ENABLE = 14378; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER1_EVENT_SELECT = 14379; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER1_EVENT_SELECT_LEN = 14380; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER1_POSEDGE_SELECT = 14381; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT = 14382; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT_LEN = 14383; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER2_ENABLE = 14384; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER2_EVENT_SELECT = 14385; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER2_EVENT_SELECT_LEN = 14386; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER2_POSEDGE_SELECT = 14387; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT = 14388; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT_LEN = 14389; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER3_ENABLE = 14390; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER3_EVENT_SELECT = 14391; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER3_EVENT_SELECT_LEN = 14392; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER3_POSEDGE_SELECT = 14393; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER_FREEZE_MODE = 14394; // 2
+static const uint64_t SH_FLD_PMUB_COUNTER_RESET_MODE = 14395; // 2
+static const uint64_t SH_FLD_PMUB_PORT_SELECT = 14396; // 2
+static const uint64_t SH_FLD_PMUB_PORT_SELECT_LEN = 14397; // 2
+static const uint64_t SH_FLD_PMUB_PRESCALER_SELECT = 14398; // 2
+static const uint64_t SH_FLD_PMUB_PRESCALER_SELECT_LEN = 14399; // 2
+static const uint64_t SH_FLD_PMULET_FREEZE_MODE = 14400; // 7
+static const uint64_t SH_FLD_PMULET_RESET_MODE = 14401; // 2
+static const uint64_t SH_FLD_PMU_BUS_ENABLE = 14402; // 2
+static const uint64_t SH_FLD_PMU_BUS_ENABLE_LEN = 14403; // 2
+static const uint64_t SH_FLD_PMU_CNTRA_CFG_REG_PARITY_ERRHOLD = 14404; // 2
+static const uint64_t SH_FLD_PMU_CNTRB_CFG_REG_PARITY_ERRHOLD = 14405; // 2
+static const uint64_t SH_FLD_PMU_ENABLE = 14406; // 2
+static const uint64_t SH_FLD_PMU_EVENT_SEL_REG_PARITY_ERRHOLD = 14407; // 2
+static const uint64_t SH_FLD_PMU_SELECT_HIGH = 14408; // 2
+static const uint64_t SH_FLD_PMU_SELECT_HIGH_LEN = 14409; // 2
+static const uint64_t SH_FLD_PMU_SELECT_LOW = 14410; // 2
+static const uint64_t SH_FLD_PMU_SELECT_LOW_LEN = 14411; // 2
+static const uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C0 = 14412; // 12
+static const uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 14413; // 12
+static const uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C1 = 14414; // 12
+static const uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 14415; // 12
+static const uint64_t SH_FLD_PM_ENTRY_ACK_C0 = 14416; // 12
+static const uint64_t SH_FLD_PM_ENTRY_ACK_C0_ACTUAL = 14417; // 12
+static const uint64_t SH_FLD_PM_ENTRY_ACK_C1 = 14418; // 12
+static const uint64_t SH_FLD_PM_ENTRY_ACK_C1_ACTUAL = 14419; // 12
+static const uint64_t SH_FLD_PM_ERROR = 14420; // 6
+static const uint64_t SH_FLD_PM_EXIT_C0 = 14421; // 12
+static const uint64_t SH_FLD_PM_EXIT_C0_ACTUAL = 14422; // 12
+static const uint64_t SH_FLD_PM_EXIT_C1 = 14423; // 12
+static const uint64_t SH_FLD_PM_EXIT_C1_ACTUAL = 14424; // 12
+static const uint64_t SH_FLD_PM_STATE_ACTIVE_C0 = 14425; // 12
+static const uint64_t SH_FLD_PM_STATE_ACTIVE_C1 = 14426; // 12
+static const uint64_t SH_FLD_PM_STATE_ALL_HV_C0 = 14427; // 12
+static const uint64_t SH_FLD_PM_STATE_ALL_HV_C1 = 14428; // 12
+static const uint64_t SH_FLD_PM_STATE_C0 = 14429; // 12
+static const uint64_t SH_FLD_PM_STATE_C0_LEN = 14430; // 12
+static const uint64_t SH_FLD_PM_STATE_C1 = 14431; // 12
+static const uint64_t SH_FLD_PM_STATE_C1_LEN = 14432; // 12
+static const uint64_t SH_FLD_POCKET_ND_RATE1 = 14433; // 12
+static const uint64_t SH_FLD_POCKET_ND_RATE1_LEN = 14434; // 12
+static const uint64_t SH_FLD_POCKET_RATE1 = 14435; // 12
+static const uint64_t SH_FLD_POCKET_RATE1_LEN = 14436; // 12
+static const uint64_t SH_FLD_POCKET_RATE2 = 14437; // 12
+static const uint64_t SH_FLD_POCKET_RATE2_LEN = 14438; // 12
+static const uint64_t SH_FLD_POCKET_RATE3 = 14439; // 12
+static const uint64_t SH_FLD_POCKET_RATE3_LEN = 14440; // 12
+static const uint64_t SH_FLD_POD0 = 14441; // 50
+static const uint64_t SH_FLD_POD0_LEN = 14442; // 50
+static const uint64_t SH_FLD_POD1 = 14443; // 50
+static const uint64_t SH_FLD_POD10 = 14444; // 50
+static const uint64_t SH_FLD_POD10_LEN = 14445; // 50
+static const uint64_t SH_FLD_POD1_LEN = 14446; // 50
+static const uint64_t SH_FLD_POD2 = 14447; // 50
+static const uint64_t SH_FLD_POD2_LEN = 14448; // 50
+static const uint64_t SH_FLD_POD3 = 14449; // 50
+static const uint64_t SH_FLD_POD3_LEN = 14450; // 50
+static const uint64_t SH_FLD_POD4 = 14451; // 50
+static const uint64_t SH_FLD_POD4_LEN = 14452; // 50
+static const uint64_t SH_FLD_POD5 = 14453; // 50
+static const uint64_t SH_FLD_POD5_LEN = 14454; // 50
+static const uint64_t SH_FLD_POD6 = 14455; // 50
+static const uint64_t SH_FLD_POD6_LEN = 14456; // 50
+static const uint64_t SH_FLD_POD7 = 14457; // 50
+static const uint64_t SH_FLD_POD7_LEN = 14458; // 50
+static const uint64_t SH_FLD_POD8 = 14459; // 50
+static const uint64_t SH_FLD_POD8_LEN = 14460; // 50
+static const uint64_t SH_FLD_POD9 = 14461; // 50
+static const uint64_t SH_FLD_POD9_LEN = 14462; // 50
+static const uint64_t SH_FLD_POINTER = 14463; // 2
+static const uint64_t SH_FLD_POINTER_LEN = 14464; // 2
+static const uint64_t SH_FLD_POLLING_TIMEOUT_SEL = 14465; // 6
+static const uint64_t SH_FLD_POLLING_TIMEOUT_SEL_LEN = 14466; // 6
+static const uint64_t SH_FLD_POLL_BCST_RTY_MON = 14467; // 1
+static const uint64_t SH_FLD_POLL_DONE = 14468; // 1
+static const uint64_t SH_FLD_POOL = 14469; // 1
+static const uint64_t SH_FLD_POOL_LEN = 14470; // 1
+static const uint64_t SH_FLD_PORT0_ERROR_CODE = 14471; // 3
+static const uint64_t SH_FLD_PORT0_ERROR_CODE_0 = 14472; // 1
+static const uint64_t SH_FLD_PORT0_ERROR_CODE_0_LEN = 14473; // 1
+static const uint64_t SH_FLD_PORT0_ERROR_CODE_1 = 14474; // 2
+static const uint64_t SH_FLD_PORT0_ERROR_CODE_1_LEN = 14475; // 2
+static const uint64_t SH_FLD_PORT0_ERROR_CODE_2 = 14476; // 3
+static const uint64_t SH_FLD_PORT0_ERROR_CODE_2_LEN = 14477; // 3
+static const uint64_t SH_FLD_PORT0_ERROR_CODE_LEN = 14478; // 3
+static const uint64_t SH_FLD_PORT1_ERROR_CODE = 14479; // 3
+static const uint64_t SH_FLD_PORT1_ERROR_CODE_0 = 14480; // 1
+static const uint64_t SH_FLD_PORT1_ERROR_CODE_0_LEN = 14481; // 1
+static const uint64_t SH_FLD_PORT1_ERROR_CODE_1 = 14482; // 2
+static const uint64_t SH_FLD_PORT1_ERROR_CODE_1_LEN = 14483; // 2
+static const uint64_t SH_FLD_PORT1_ERROR_CODE_2 = 14484; // 3
+static const uint64_t SH_FLD_PORT1_ERROR_CODE_2_LEN = 14485; // 3
+static const uint64_t SH_FLD_PORT1_ERROR_CODE_LEN = 14486; // 3
+static const uint64_t SH_FLD_PORT2_ERROR_CODE = 14487; // 3
+static const uint64_t SH_FLD_PORT2_ERROR_CODE_0 = 14488; // 1
+static const uint64_t SH_FLD_PORT2_ERROR_CODE_0_LEN = 14489; // 1
+static const uint64_t SH_FLD_PORT2_ERROR_CODE_1 = 14490; // 2
+static const uint64_t SH_FLD_PORT2_ERROR_CODE_1_LEN = 14491; // 2
+static const uint64_t SH_FLD_PORT2_ERROR_CODE_2 = 14492; // 3
+static const uint64_t SH_FLD_PORT2_ERROR_CODE_2_LEN = 14493; // 3
+static const uint64_t SH_FLD_PORT2_ERROR_CODE_LEN = 14494; // 3
+static const uint64_t SH_FLD_PORT3_ERROR_CODE = 14495; // 3
+static const uint64_t SH_FLD_PORT3_ERROR_CODE_0 = 14496; // 1
+static const uint64_t SH_FLD_PORT3_ERROR_CODE_0_LEN = 14497; // 1
+static const uint64_t SH_FLD_PORT3_ERROR_CODE_1 = 14498; // 2
+static const uint64_t SH_FLD_PORT3_ERROR_CODE_1_LEN = 14499; // 2
+static const uint64_t SH_FLD_PORT3_ERROR_CODE_2 = 14500; // 3
+static const uint64_t SH_FLD_PORT3_ERROR_CODE_2_LEN = 14501; // 3
+static const uint64_t SH_FLD_PORT3_ERROR_CODE_LEN = 14502; // 3
+static const uint64_t SH_FLD_PORT4_ERROR_CODE = 14503; // 3
+static const uint64_t SH_FLD_PORT4_ERROR_CODE_0 = 14504; // 1
+static const uint64_t SH_FLD_PORT4_ERROR_CODE_0_LEN = 14505; // 1
+static const uint64_t SH_FLD_PORT4_ERROR_CODE_1 = 14506; // 2
+static const uint64_t SH_FLD_PORT4_ERROR_CODE_1_LEN = 14507; // 2
+static const uint64_t SH_FLD_PORT4_ERROR_CODE_2 = 14508; // 3
+static const uint64_t SH_FLD_PORT4_ERROR_CODE_2_LEN = 14509; // 3
+static const uint64_t SH_FLD_PORT4_ERROR_CODE_LEN = 14510; // 3
+static const uint64_t SH_FLD_PORT5_ERROR_CODE = 14511; // 3
+static const uint64_t SH_FLD_PORT5_ERROR_CODE_0 = 14512; // 1
+static const uint64_t SH_FLD_PORT5_ERROR_CODE_0_LEN = 14513; // 1
+static const uint64_t SH_FLD_PORT5_ERROR_CODE_1 = 14514; // 2
+static const uint64_t SH_FLD_PORT5_ERROR_CODE_1_LEN = 14515; // 2
+static const uint64_t SH_FLD_PORT5_ERROR_CODE_2 = 14516; // 3
+static const uint64_t SH_FLD_PORT5_ERROR_CODE_2_LEN = 14517; // 3
+static const uint64_t SH_FLD_PORT5_ERROR_CODE_LEN = 14518; // 3
+static const uint64_t SH_FLD_PORT6_ERROR_CODE = 14519; // 3
+static const uint64_t SH_FLD_PORT6_ERROR_CODE_0 = 14520; // 1
+static const uint64_t SH_FLD_PORT6_ERROR_CODE_0_LEN = 14521; // 1
+static const uint64_t SH_FLD_PORT6_ERROR_CODE_1 = 14522; // 2
+static const uint64_t SH_FLD_PORT6_ERROR_CODE_1_LEN = 14523; // 2
+static const uint64_t SH_FLD_PORT6_ERROR_CODE_2 = 14524; // 3
+static const uint64_t SH_FLD_PORT6_ERROR_CODE_2_LEN = 14525; // 3
+static const uint64_t SH_FLD_PORT6_ERROR_CODE_LEN = 14526; // 3
+static const uint64_t SH_FLD_PORT7_ERROR_CODE = 14527; // 3
+static const uint64_t SH_FLD_PORT7_ERROR_CODE_0 = 14528; // 1
+static const uint64_t SH_FLD_PORT7_ERROR_CODE_0_LEN = 14529; // 1
+static const uint64_t SH_FLD_PORT7_ERROR_CODE_1 = 14530; // 2
+static const uint64_t SH_FLD_PORT7_ERROR_CODE_1_LEN = 14531; // 2
+static const uint64_t SH_FLD_PORT7_ERROR_CODE_2 = 14532; // 3
+static const uint64_t SH_FLD_PORT7_ERROR_CODE_2_LEN = 14533; // 3
+static const uint64_t SH_FLD_PORT7_ERROR_CODE_LEN = 14534; // 3
+static const uint64_t SH_FLD_PORTPOWERDOWN = 14535; // 8
+static const uint64_t SH_FLD_PORTSEL = 14536; // 2
+static const uint64_t SH_FLD_PORTSEL_LEN = 14537; // 2
+static const uint64_t SH_FLD_PORT_0_ENABLE = 14538; // 1
+static const uint64_t SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP = 14539; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN = 14540; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP = 14541; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN = 14542; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ON_RCE = 14543; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP = 14544; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN = 14545; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD = 14546; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN = 14547; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_IS_TCE = 14548; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD = 14549; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 14550; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ON_RCE = 14551; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP = 14552; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN = 14553; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD = 14554; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN = 14555; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD = 14556; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 14557; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP = 14558; // 2
+static const uint64_t SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN = 14559; // 2
+static const uint64_t SH_FLD_PORT_1_ENABLE = 14560; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP = 14561; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP_LEN = 14562; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP = 14563; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP_LEN = 14564; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ON_RCE = 14565; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP = 14566; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP_LEN = 14567; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD = 14568; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD_LEN = 14569; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_IS_TCE = 14570; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD = 14571; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 14572; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ON_RCE = 14573; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP = 14574; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP_LEN = 14575; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD = 14576; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD_LEN = 14577; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD = 14578; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 14579; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP = 14580; // 2
+static const uint64_t SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP_LEN = 14581; // 2
+static const uint64_t SH_FLD_PORT_2_ENABLE = 14582; // 3
+static const uint64_t SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP = 14583; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP_LEN = 14584; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP = 14585; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP_LEN = 14586; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ON_RCE = 14587; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP = 14588; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP_LEN = 14589; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD = 14590; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD_LEN = 14591; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_IS_TCE = 14592; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD = 14593; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 14594; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ON_RCE = 14595; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP = 14596; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP_LEN = 14597; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD = 14598; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD_LEN = 14599; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD = 14600; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 14601; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP = 14602; // 2
+static const uint64_t SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP_LEN = 14603; // 2
+static const uint64_t SH_FLD_PORT_3_ENABLE = 14604; // 3
+static const uint64_t SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP = 14605; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP_LEN = 14606; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP = 14607; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP_LEN = 14608; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ON_RCE = 14609; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP = 14610; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP_LEN = 14611; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD = 14612; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD_LEN = 14613; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_IS_TCE = 14614; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD = 14615; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 14616; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ON_RCE = 14617; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP = 14618; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP_LEN = 14619; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD = 14620; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD_LEN = 14621; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD = 14622; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 14623; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP = 14624; // 2
+static const uint64_t SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP_LEN = 14625; // 2
+static const uint64_t SH_FLD_PORT_4_ENABLE = 14626; // 3
+static const uint64_t SH_FLD_PORT_5_ENABLE = 14627; // 3
+static const uint64_t SH_FLD_PORT_6_ENABLE = 14628; // 3
+static const uint64_t SH_FLD_PORT_7_ENABLE = 14629; // 3
+static const uint64_t SH_FLD_PORT_ENABLE = 14630; // 3
+static const uint64_t SH_FLD_PORT_ERROR_RESET = 14631; // 1
+static const uint64_t SH_FLD_PORT_ERROR_RESET_1 = 14632; // 2
+static const uint64_t SH_FLD_PORT_ERROR_RESET_2 = 14633; // 3
+static const uint64_t SH_FLD_PORT_ERROR_RESET_3 = 14634; // 3
+static const uint64_t SH_FLD_PORT_ERROR_RESET_4 = 14635; // 3
+static const uint64_t SH_FLD_PORT_ERROR_RESET_5 = 14636; // 3
+static const uint64_t SH_FLD_PORT_ERROR_RESET_6 = 14637; // 3
+static const uint64_t SH_FLD_PORT_ERROR_RESET_7 = 14638; // 3
+static const uint64_t SH_FLD_PORT_FAIL = 14639; // 8
+static const uint64_t SH_FLD_PORT_GENERAL_RESET = 14640; // 1
+static const uint64_t SH_FLD_PORT_GENERAL_RESET_1 = 14641; // 2
+static const uint64_t SH_FLD_PORT_GENERAL_RESET_2 = 14642; // 3
+static const uint64_t SH_FLD_PORT_GENERAL_RESET_3 = 14643; // 3
+static const uint64_t SH_FLD_PORT_GENERAL_RESET_4 = 14644; // 3
+static const uint64_t SH_FLD_PORT_GENERAL_RESET_5 = 14645; // 3
+static const uint64_t SH_FLD_PORT_GENERAL_RESET_6 = 14646; // 3
+static const uint64_t SH_FLD_PORT_GENERAL_RESET_7 = 14647; // 3
+static const uint64_t SH_FLD_PORT_NUMBER_0 = 14648; // 2
+static const uint64_t SH_FLD_PORT_NUMBER_0_LEN = 14649; // 2
+static const uint64_t SH_FLD_PORT_NUMBER_1 = 14650; // 1
+static const uint64_t SH_FLD_PORT_NUMBER_1_LEN = 14651; // 1
+static const uint64_t SH_FLD_PORT_NUMBER_2 = 14652; // 1
+static const uint64_t SH_FLD_PORT_NUMBER_2_LEN = 14653; // 1
+static const uint64_t SH_FLD_PORT_NUMBER_3 = 14654; // 1
+static const uint64_t SH_FLD_PORT_NUMBER_3_LEN = 14655; // 1
+static const uint64_t SH_FLD_PORT_SEL = 14656; // 1
+static const uint64_t SH_FLD_PORT_SEL_LEN = 14657; // 1
+static const uint64_t SH_FLD_POWDN_DLY = 14658; // 30
+static const uint64_t SH_FLD_POWDN_DLY_LEN = 14659; // 30
+static const uint64_t SH_FLD_POWERBUS_DATA_HANG_ERROR = 14660; // 4
+static const uint64_t SH_FLD_POWERBUS_HANG_ERROR = 14661; // 4
+static const uint64_t SH_FLD_POWERBUS_INTERFACE_PE = 14662; // 4
+static const uint64_t SH_FLD_POWERBUS_MISC_ERROR = 14663; // 4
+static const uint64_t SH_FLD_POWERBUS_PROTOCOL_ERROR = 14664; // 4
+static const uint64_t SH_FLD_POWER_MANAGEMENT_INTERRUPT = 14665; // 1
+static const uint64_t SH_FLD_POWER_SAVING_LIMIT_A_N = 14666; // 96
+static const uint64_t SH_FLD_POWER_SAVING_LIMIT_A_N_LEN = 14667; // 96
+static const uint64_t SH_FLD_POWER_UP_CNTR_REF = 14668; // 1
+static const uint64_t SH_FLD_POWER_UP_CNTR_REF_LEN = 14669; // 1
+static const uint64_t SH_FLD_POWUP_DLY = 14670; // 30
+static const uint64_t SH_FLD_POWUP_DLY_LEN = 14671; // 30
+static const uint64_t SH_FLD_PPC405_CHIP_RESET = 14672; // 1
+static const uint64_t SH_FLD_PPC405_CHIP_RESET_MASK = 14673; // 1
+static const uint64_t SH_FLD_PPC405_CORE_RESET = 14674; // 1
+static const uint64_t SH_FLD_PPC405_CORE_RESET_MASK = 14675; // 1
+static const uint64_t SH_FLD_PPC405_DBGMSRWE = 14676; // 1
+static const uint64_t SH_FLD_PPC405_DBGMSRWE_MASK = 14677; // 1
+static const uint64_t SH_FLD_PPC405_DBGSTOPACK = 14678; // 1
+static const uint64_t SH_FLD_PPC405_DBGSTOPACK_MASK = 14679; // 1
+static const uint64_t SH_FLD_PPC405_HALT = 14680; // 1
+static const uint64_t SH_FLD_PPC405_SYSTEM_RESET = 14681; // 1
+static const uint64_t SH_FLD_PPC405_SYSTEM_RESET_MASK = 14682; // 1
+static const uint64_t SH_FLD_PPE_BREAKPOINT_ERROR = 14683; // 12
+static const uint64_t SH_FLD_PPE_DEBUG_TRIGGER = 14684; // 12
+static const uint64_t SH_FLD_PPE_EXTERNAL_ERROR = 14685; // 12
+static const uint64_t SH_FLD_PPE_GCR = 14686; // 4
+static const uint64_t SH_FLD_PPE_HALTED = 14687; // 12
+static const uint64_t SH_FLD_PPE_INTERNAL_ERROR = 14688; // 12
+static const uint64_t SH_FLD_PPE_PROGRESS_ERROR = 14689; // 12
+static const uint64_t SH_FLD_PPE_RD_ACK_DEAD = 14690; // 12
+static const uint64_t SH_FLD_PPE_RD_CRESP_ADDR_ERR = 14691; // 12
+static const uint64_t SH_FLD_PPE_WATCHDOG = 14692; // 12
+static const uint64_t SH_FLD_PPE_WR_ACK_DEAD = 14693; // 12
+static const uint64_t SH_FLD_PPE_WR_CRESP_ADDR_ERR = 14694; // 12
+static const uint64_t SH_FLD_PPE_XIRAMEDR_EDR = 14695; // 4
+static const uint64_t SH_FLD_PPE_XIRAMEDR_EDR_LEN = 14696; // 4
+static const uint64_t SH_FLD_PPE_XIRAMGA_IR = 14697; // 4
+static const uint64_t SH_FLD_PPE_XIRAMGA_IR_LEN = 14698; // 4
+static const uint64_t SH_FLD_PPE_XIRAMRA_SPRG0 = 14699; // 4
+static const uint64_t SH_FLD_PPE_XIRAMRA_SPRG0_LEN = 14700; // 4
+static const uint64_t SH_FLD_PPE_XIXCR_XCR = 14701; // 8
+static const uint64_t SH_FLD_PPE_XIXCR_XCR_LEN = 14702; // 8
+static const uint64_t SH_FLD_PPM_SPARE_OUT_C0 = 14703; // 12
+static const uint64_t SH_FLD_PPM_SPARE_OUT_C1 = 14704; // 12
+static const uint64_t SH_FLD_PPM_WRITE_DISABLE = 14705; // 24
+static const uint64_t SH_FLD_PPM_WRITE_OVERRIDE = 14706; // 24
+static const uint64_t SH_FLD_PQ_STATE = 14707; // 1
+static const uint64_t SH_FLD_PQ_STATE_LEN = 14708; // 1
+static const uint64_t SH_FLD_PRB0 = 14709; // 12
+static const uint64_t SH_FLD_PRB1 = 14710; // 12
+static const uint64_t SH_FLD_PRBS = 14711; // 2
+static const uint64_t SH_FLD_PRBS_CHECK_SYNC = 14712; // 72
+static const uint64_t SH_FLD_PRBS_INVERT = 14713; // 2
+static const uint64_t SH_FLD_PRBS_LEN = 14714; // 2
+static const uint64_t SH_FLD_PRBS_PHASE_SELECT = 14715; // 2
+static const uint64_t SH_FLD_PRBS_PHASE_SELECT_LEN = 14716; // 2
+static const uint64_t SH_FLD_PRBS_RXBIST_MODE = 14717; // 72
+static const uint64_t SH_FLD_PRBS_SCRAMBLE_MODE = 14718; // 144
+static const uint64_t SH_FLD_PRBS_SCRAMBLE_MODE_LEN = 14719; // 144
+static const uint64_t SH_FLD_PRBS_SEED_DDC = 14720; // 72
+static const uint64_t SH_FLD_PRBS_SEED_DFE = 14721; // 72
+static const uint64_t SH_FLD_PRBS_SEED_MODE = 14722; // 4
+static const uint64_t SH_FLD_PRBS_SEED_VALUE_0_15 = 14723; // 140
+static const uint64_t SH_FLD_PRBS_SEED_VALUE_0_15_LEN = 14724; // 140
+static const uint64_t SH_FLD_PRBS_SEED_VALUE_16_22 = 14725; // 140
+static const uint64_t SH_FLD_PRBS_SEED_VALUE_16_22_LEN = 14726; // 140
+static const uint64_t SH_FLD_PRBS_SLS_EXPECT = 14727; // 4
+static const uint64_t SH_FLD_PRBS_SLS_EXPECT_LEN = 14728; // 4
+static const uint64_t SH_FLD_PRBS_SYNC_MODE = 14729; // 72
+static const uint64_t SH_FLD_PRBS_TEST_DATA = 14730; // 120
+static const uint64_t SH_FLD_PRBS_TEST_DATA_LEN = 14731; // 120
+static const uint64_t SH_FLD_PRECISE_DIR_FLUSH_FAILED = 14732; // 2
+static const uint64_t SH_FLD_PRECISE_DIR_SIZE = 14733; // 2
+static const uint64_t SH_FLD_PRECISE_DIR_SIZE_LEN = 14734; // 2
+static const uint64_t SH_FLD_PRECLUDE = 14735; // 1
+static const uint64_t SH_FLD_PREF2DMD = 14736; // 1
+static const uint64_t SH_FLD_PREFETCH = 14737; // 6
+static const uint64_t SH_FLD_PREFETCH_CHANNEL_CNT = 14738; // 1
+static const uint64_t SH_FLD_PREFETCH_CHANNEL_CNT_LEN = 14739; // 1
+static const uint64_t SH_FLD_PREFETCH_DISABLE = 14740; // 6
+static const uint64_t SH_FLD_PREFETCH_DISTANCE = 14741; // 6
+static const uint64_t SH_FLD_PREFETCH_DISTANCE_LEN = 14742; // 6
+static const uint64_t SH_FLD_PREFETCH_LIMIT = 14743; // 8
+static const uint64_t SH_FLD_PREFETCH_LIMIT_LEN = 14744; // 8
+static const uint64_t SH_FLD_PREFEVOD = 14745; // 1
+static const uint64_t SH_FLD_PREF_DEPTH = 14746; // 1
+static const uint64_t SH_FLD_PREF_DEPTH_LEN = 14747; // 1
+static const uint64_t SH_FLD_PREF_THRSH0 = 14748; // 1
+static const uint64_t SH_FLD_PREF_THRSH0_LEN = 14749; // 1
+static const uint64_t SH_FLD_PREF_THRSH1 = 14750; // 1
+static const uint64_t SH_FLD_PREF_THRSH1_LEN = 14751; // 1
+static const uint64_t SH_FLD_PREF_THRSH2 = 14752; // 1
+static const uint64_t SH_FLD_PREF_THRSH2_LEN = 14753; // 1
+static const uint64_t SH_FLD_PREF_THRSH3 = 14754; // 1
+static const uint64_t SH_FLD_PREF_THRSH3_LEN = 14755; // 1
+static const uint64_t SH_FLD_PREF_TIMEOUT = 14756; // 1
+static const uint64_t SH_FLD_PREF_TIMEOUT_LEN = 14757; // 1
+static const uint64_t SH_FLD_PRESCALAR_SEL0 = 14758; // 2
+static const uint64_t SH_FLD_PRESCALAR_SEL0_LEN = 14759; // 2
+static const uint64_t SH_FLD_PRESCALAR_SEL1 = 14760; // 2
+static const uint64_t SH_FLD_PRESCALAR_SEL1_LEN = 14761; // 2
+static const uint64_t SH_FLD_PRESCALAR_SEL2 = 14762; // 2
+static const uint64_t SH_FLD_PRESCALAR_SEL2_LEN = 14763; // 2
+static const uint64_t SH_FLD_PRESCALAR_SEL3 = 14764; // 2
+static const uint64_t SH_FLD_PRESCALAR_SEL3_LEN = 14765; // 2
+static const uint64_t SH_FLD_PRESCALER_SEL = 14766; // 1
+static const uint64_t SH_FLD_PRESCALER_SEL_LEN = 14767; // 1
+static const uint64_t SH_FLD_PRESCALE_C0 = 14768; // 9
+static const uint64_t SH_FLD_PRESCALE_C0_LEN = 14769; // 9
+static const uint64_t SH_FLD_PRESCALE_C1 = 14770; // 9
+static const uint64_t SH_FLD_PRESCALE_C1_LEN = 14771; // 9
+static const uint64_t SH_FLD_PRESCALE_C2 = 14772; // 9
+static const uint64_t SH_FLD_PRESCALE_C2_LEN = 14773; // 9
+static const uint64_t SH_FLD_PRESCALE_C3 = 14774; // 9
+static const uint64_t SH_FLD_PRESCALE_C3_LEN = 14775; // 9
+static const uint64_t SH_FLD_PRESP_RTY_OTHER = 14776; // 2
+static const uint64_t SH_FLD_PREVENT_MTP_AT_DEM_IN_PIPE = 14777; // 1
+static const uint64_t SH_FLD_PRGM_ADDR = 14778; // 1
+static const uint64_t SH_FLD_PRGM_ADDR_LEN = 14779; // 1
+static const uint64_t SH_FLD_PRGSM_BUSY = 14780; // 24
+static const uint64_t SH_FLD_PRGSM_BUSY_ON_THIS = 14781; // 24
+static const uint64_t SH_FLD_PRG_BIT_LOCATION = 14782; // 1
+static const uint64_t SH_FLD_PRG_BIT_LOCATION_LEN = 14783; // 1
+static const uint64_t SH_FLD_PRI = 14784; // 8
+static const uint64_t SH_FLD_PRIORITY = 14785; // 18
+static const uint64_t SH_FLD_PRIORITY_ENABLE = 14786; // 6
+static const uint64_t SH_FLD_PRIORITY_LEN = 14787; // 6
+static const uint64_t SH_FLD_PRIORITY_LIMIT_0_3 = 14788; // 1
+static const uint64_t SH_FLD_PRIORITY_LIMIT_0_3_LEN = 14789; // 1
+static const uint64_t SH_FLD_PRIORITY_LPID = 14790; // 6
+static const uint64_t SH_FLD_PRIORITY_LPID_LEN = 14791; // 6
+static const uint64_t SH_FLD_PRIORITY_PID = 14792; // 6
+static const uint64_t SH_FLD_PRIORITY_PID_LEN = 14793; // 6
+static const uint64_t SH_FLD_PRIORITY_PRIMAX = 14794; // 3
+static const uint64_t SH_FLD_PRIORITY_PRIMAX_LEN = 14795; // 3
+static const uint64_t SH_FLD_PRIORITY_QUEUED = 14796; // 6
+static const uint64_t SH_FLD_PRIORITY_QUEUED_LEN = 14797; // 6
+static const uint64_t SH_FLD_PRIORITY_READ_OFFSET = 14798; // 6
+static const uint64_t SH_FLD_PRIORITY_READ_OFFSET_LEN = 14799; // 6
+static const uint64_t SH_FLD_PRIORITY_SIZE = 14800; // 6
+static const uint64_t SH_FLD_PRIORITY_SIZE_LEN = 14801; // 6
+static const uint64_t SH_FLD_PRIORITY_TID = 14802; // 6
+static const uint64_t SH_FLD_PRIORITY_TID_LEN = 14803; // 6
+static const uint64_t SH_FLD_PRI_I_PATH_STEP_CHECK_ENABLE = 14804; // 1
+static const uint64_t SH_FLD_PRI_LEN = 14805; // 8
+static const uint64_t SH_FLD_PRI_M_PATH_0_STEP_CHECK_ENABLE = 14806; // 1
+static const uint64_t SH_FLD_PRI_M_PATH_1_STEP_CHECK_ENABLE = 14807; // 1
+static const uint64_t SH_FLD_PRI_M_PATH_SELECT = 14808; // 2
+static const uint64_t SH_FLD_PRI_M_S_DRAWER_SELECT = 14809; // 2
+static const uint64_t SH_FLD_PRI_M_S_SELECT = 14810; // 2
+static const uint64_t SH_FLD_PRI_SEC_SELECT = 14811; // 1
+static const uint64_t SH_FLD_PRI_SEC_SELECT_LEN = 14812; // 1
+static const uint64_t SH_FLD_PRI_SELECT = 14813; // 1
+static const uint64_t SH_FLD_PRI_STATE_MACHINE_RESET = 14814; // 6
+static const uint64_t SH_FLD_PRI_S_PATH_0_STEP_CHECK_ENABLE = 14815; // 1
+static const uint64_t SH_FLD_PRI_S_PATH_1_STEP_CHECK_ENABLE = 14816; // 1
+static const uint64_t SH_FLD_PRI_S_PATH_SELECT = 14817; // 1
+static const uint64_t SH_FLD_PRI_V = 14818; // 8
+static const uint64_t SH_FLD_PROBE_0_TOGGLE_ENABLE = 14819; // 1
+static const uint64_t SH_FLD_PROBE_1_TOGGLE_ENABLE = 14820; // 1
+static const uint64_t SH_FLD_PROBE_2_TOGGLE_ENABLE = 14821; // 1
+static const uint64_t SH_FLD_PROBE_3_TOGGLE_ENABLE = 14822; // 1
+static const uint64_t SH_FLD_PROC_RCVY_AGAIN = 14823; // 96
+static const uint64_t SH_FLD_PROC_RCVY_DONE = 14824; // 96
+static const uint64_t SH_FLD_PROGRAM_ENABLE = 14825; // 1
+static const uint64_t SH_FLD_PROGRESS_ERROR = 14826; // 1
+static const uint64_t SH_FLD_PROG_REQ_DELAY = 14827; // 1
+static const uint64_t SH_FLD_PROG_REQ_DELAY_LEN = 14828; // 1
+static const uint64_t SH_FLD_PROTECTION_CHECK = 14829; // 1
+static const uint64_t SH_FLD_PROTOCOL = 14830; // 8
+static const uint64_t SH_FLD_PROTOCOL_CHECKSTOP = 14831; // 2
+static const uint64_t SH_FLD_PROTOCOL_ERROR = 14832; // 45
+static const uint64_t SH_FLD_PROTOCOL_LEN = 14833; // 8
+static const uint64_t SH_FLD_PROT_EX_SPARE0 = 14834; // 1
+static const uint64_t SH_FLD_PROT_EX_SPARE1 = 14835; // 1
+static const uint64_t SH_FLD_PROT_TP_SPARE0 = 14836; // 1
+static const uint64_t SH_FLD_PROT_TP_SPARE1 = 14837; // 1
+static const uint64_t SH_FLD_PROT_TP_SPARE2 = 14838; // 1
+static const uint64_t SH_FLD_PRPG_A_VAL = 14839; // 43
+static const uint64_t SH_FLD_PRPG_A_VAL_LEN = 14840; // 43
+static const uint64_t SH_FLD_PRPG_B_VAL = 14841; // 43
+static const uint64_t SH_FLD_PRPG_B_VAL_LEN = 14842; // 43
+static const uint64_t SH_FLD_PRPG_MODE = 14843; // 43
+static const uint64_t SH_FLD_PRPG_VALUE = 14844; // 43
+static const uint64_t SH_FLD_PRPG_VALUE_LEN = 14845; // 43
+static const uint64_t SH_FLD_PRPG_WEIGHTING = 14846; // 43
+static const uint64_t SH_FLD_PRPG_WEIGHTING_LEN = 14847; // 43
+static const uint64_t SH_FLD_PRS = 14848; // 8
+static const uint64_t SH_FLD_PRV_BUS0_STG2_SEL = 14849; // 1
+static const uint64_t SH_FLD_PRV_BUS1_STG2_SEL = 14850; // 1
+static const uint64_t SH_FLD_PR_BUMP_SL_1UI = 14851; // 120
+static const uint64_t SH_FLD_PR_BUMP_SR_1UI = 14852; // 120
+static const uint64_t SH_FLD_PR_BUMP_TO_CENTER = 14853; // 72
+static const uint64_t SH_FLD_PR_BUMP_TO_EDGE_A = 14854; // 120
+static const uint64_t SH_FLD_PR_BUMP_TO_EDGE_B = 14855; // 48
+static const uint64_t SH_FLD_PR_COARSE_MODE_EN = 14856; // 48
+static const uint64_t SH_FLD_PR_COARSE_MODE_TIMER_SEL = 14857; // 48
+static const uint64_t SH_FLD_PR_COARSE_MODE_TIMER_SEL_LEN = 14858; // 48
+static const uint64_t SH_FLD_PR_DATA_A_OFFSET = 14859; // 120
+static const uint64_t SH_FLD_PR_DATA_A_OFFSET_LEN = 14860; // 120
+static const uint64_t SH_FLD_PR_DATA_B_OFFSET = 14861; // 48
+static const uint64_t SH_FLD_PR_DATA_B_OFFSET_LEN = 14862; // 48
+static const uint64_t SH_FLD_PR_DDC_A = 14863; // 120
+static const uint64_t SH_FLD_PR_DDC_B = 14864; // 48
+static const uint64_t SH_FLD_PR_EDGE_TRACK_CNTL = 14865; // 120
+static const uint64_t SH_FLD_PR_EDGE_TRACK_CNTL_LEN = 14866; // 120
+static const uint64_t SH_FLD_PR_FW_INERTIA_AMT = 14867; // 48
+static const uint64_t SH_FLD_PR_FW_INERTIA_AMT_COARSE = 14868; // 48
+static const uint64_t SH_FLD_PR_FW_INERTIA_AMT_COARSE_LEN = 14869; // 48
+static const uint64_t SH_FLD_PR_FW_INERTIA_AMT_LEN = 14870; // 48
+static const uint64_t SH_FLD_PR_FW_OFF = 14871; // 48
+static const uint64_t SH_FLD_PR_HALFRATE_MODE = 14872; // 48
+static const uint64_t SH_FLD_PR_INVALID_LOCK_BUMP_SIZE = 14873; // 120
+static const uint64_t SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN = 14874; // 120
+static const uint64_t SH_FLD_PR_INVALID_LOCK_COARSE_EN = 14875; // 48
+static const uint64_t SH_FLD_PR_INVALID_LOCK_FILTER_EN = 14876; // 120
+static const uint64_t SH_FLD_PR_IQ_RES_SEL = 14877; // 120
+static const uint64_t SH_FLD_PR_IQ_RES_SEL_LEN = 14878; // 120
+static const uint64_t SH_FLD_PR_LOCK_DONE = 14879; // 120
+static const uint64_t SH_FLD_PR_PHASE_STEP = 14880; // 120
+static const uint64_t SH_FLD_PR_PHASE_STEP_COARSE = 14881; // 48
+static const uint64_t SH_FLD_PR_PHASE_STEP_COARSE_LEN = 14882; // 48
+static const uint64_t SH_FLD_PR_PHASE_STEP_LEN = 14883; // 120
+static const uint64_t SH_FLD_PR_RESET = 14884; // 48
+static const uint64_t SH_FLD_PR_TRACE_DDC_SM = 14885; // 120
+static const uint64_t SH_FLD_PR_TRACE_DDC_SM_LEN = 14886; // 120
+static const uint64_t SH_FLD_PR_TRACE_DDC_STOP = 14887; // 120
+static const uint64_t SH_FLD_PR_TRACE_WOBBLE_SM = 14888; // 120
+static const uint64_t SH_FLD_PR_TRACE_WOBBLE_SM_LEN = 14889; // 120
+static const uint64_t SH_FLD_PR_TRACE_WOBBLE_STOP = 14890; // 120
+static const uint64_t SH_FLD_PR_USE_DFE_CLOCK_A = 14891; // 120
+static const uint64_t SH_FLD_PR_USE_DFE_CLOCK_B = 14892; // 48
+static const uint64_t SH_FLD_PR_WOBBLE_A = 14893; // 120
+static const uint64_t SH_FLD_PR_WOBBLE_B = 14894; // 48
+static const uint64_t SH_FLD_PR_WOBBLE_EDGE = 14895; // 48
+static const uint64_t SH_FLD_PSAVE_ANA_REQ_DIS = 14896; // 48
+static const uint64_t SH_FLD_PSAVE_DIG_REQ_DIS = 14897; // 48
+static const uint64_t SH_FLD_PSAVE_FENCE_ENABLE = 14898; // 4
+static const uint64_t SH_FLD_PSAVE_INVALID_STATE = 14899; // 6
+static const uint64_t SH_FLD_PSAVE_MODE_DISABLE = 14900; // 140
+static const uint64_t SH_FLD_PSAVE_MODE_TIMEOUT_SEL = 14901; // 4
+static const uint64_t SH_FLD_PSAVE_MODE_TIMEOUT_SEL_LEN = 14902; // 4
+static const uint64_t SH_FLD_PSAVE_REQ_DIS = 14903; // 48
+static const uint64_t SH_FLD_PSAVE_RESYNC_DISABLE = 14904; // 72
+static const uint64_t SH_FLD_PSAVE_TIMER_WAKEUP_MODE = 14905; // 4
+static const uint64_t SH_FLD_PSAVE_WAKEUP_LANE0_ENABLE = 14906; // 8
+static const uint64_t SH_FLD_PSCR_OVERRIDE_EN = 14907; // 12
+static const uint64_t SH_FLD_PSEG_MAIN_EN = 14908; // 6
+static const uint64_t SH_FLD_PSEG_MAIN_EN_LEN = 14909; // 6
+static const uint64_t SH_FLD_PSEG_MARGINPD_EN = 14910; // 6
+static const uint64_t SH_FLD_PSEG_MARGINPD_EN_LEN = 14911; // 6
+static const uint64_t SH_FLD_PSEG_MARGINPU_EN = 14912; // 6
+static const uint64_t SH_FLD_PSEG_MARGINPU_EN_LEN = 14913; // 6
+static const uint64_t SH_FLD_PSEG_POST_EN = 14914; // 2
+static const uint64_t SH_FLD_PSEG_POST_EN_LEN = 14915; // 2
+static const uint64_t SH_FLD_PSEG_POST_SEL = 14916; // 2
+static const uint64_t SH_FLD_PSEG_POST_SEL_LEN = 14917; // 2
+static const uint64_t SH_FLD_PSEG_PRE_EN = 14918; // 6
+static const uint64_t SH_FLD_PSEG_PRE_EN_LEN = 14919; // 6
+static const uint64_t SH_FLD_PSEG_PRE_SEL = 14920; // 6
+static const uint64_t SH_FLD_PSEG_PRE_SEL_LEN = 14921; // 6
+static const uint64_t SH_FLD_PSIFSP_ACK_TIMEOUT = 14922; // 1
+static const uint64_t SH_FLD_PSIFSP_DMAR_OUTSTANDING = 14923; // 1
+static const uint64_t SH_FLD_PSIFSP_DMA_ADDR_ERR = 14924; // 1
+static const uint64_t SH_FLD_PSIFSP_DMA_ERR = 14925; // 1
+static const uint64_t SH_FLD_PSIFSP_INT_BUSY = 14926; // 1
+static const uint64_t SH_FLD_PSIFSP_INV_OP = 14927; // 1
+static const uint64_t SH_FLD_PSIFSP_LOAD_OUTSTANDING = 14928; // 1
+static const uint64_t SH_FLD_PSIFSP_MMIO_ADDR_ERR = 14929; // 1
+static const uint64_t SH_FLD_PSIFSP_MMIO_LENGTH_ERR = 14930; // 1
+static const uint64_t SH_FLD_PSIFSP_MMIO_LOAD_TIMEOUT = 14931; // 1
+static const uint64_t SH_FLD_PSIFSP_MMIO_TYPE_ERR = 14932; // 1
+static const uint64_t SH_FLD_PSIFSP_PAGE_FAULT = 14933; // 1
+static const uint64_t SH_FLD_PSIFSP_PERR = 14934; // 1
+static const uint64_t SH_FLD_PSIFSP_TCE_EXTENT_ERR = 14935; // 1
+static const uint64_t SH_FLD_PSIHB2FSP_INJ_CONST = 14936; // 1
+static const uint64_t SH_FLD_PSIHB2FSP_INJ_ERR_BITS = 14937; // 1
+static const uint64_t SH_FLD_PSIHB2FSP_INJ_ERR_BITS_LEN = 14938; // 1
+static const uint64_t SH_FLD_PSIHB2FSP_INJ_ONCE = 14939; // 1
+static const uint64_t SH_FLD_PSIHB2PB_INJ_CONST = 14940; // 1
+static const uint64_t SH_FLD_PSIHB2PB_INJ_ERR_BITS = 14941; // 1
+static const uint64_t SH_FLD_PSIHB2PB_INJ_ERR_BITS_LEN = 14942; // 1
+static const uint64_t SH_FLD_PSIHB2PB_INJ_ONCE = 14943; // 1
+static const uint64_t SH_FLD_PSIHBC_RESET = 14944; // 1
+static const uint64_t SH_FLD_PSIRFACC_C_RXDATA_RDY_ERR = 14945; // 1
+static const uint64_t SH_FLD_PSIRFACC_RADDR_PCK = 14946; // 1
+static const uint64_t SH_FLD_PSIRFACC_RCTRL_PCK = 14947; // 1
+static const uint64_t SH_FLD_PSIRFACC_RDL_FSM_PCK = 14948; // 1
+static const uint64_t SH_FLD_PSIRFACC_RFSM_PCK = 14949; // 1
+static const uint64_t SH_FLD_PSIRFACC_RLINK_STATE_LT_02 = 14950; // 1
+static const uint64_t SH_FLD_PSIRFACC_RXSC_PCK = 14951; // 1
+static const uint64_t SH_FLD_PSIRFACC_TADDR_PCK = 14952; // 1
+static const uint64_t SH_FLD_PSIRFACC_TCTRL_PCK = 14953; // 1
+static const uint64_t SH_FLD_PSIRFACC_TDL_CMD_CTRL_PCK = 14954; // 1
+static const uint64_t SH_FLD_PSIRFACC_TDL_FSM_PCK = 14955; // 1
+static const uint64_t SH_FLD_PSIRFACC_TDL_RETRY_ERR = 14956; // 1
+static const uint64_t SH_FLD_PSIRFACC_TDL_RSP_CTRL_PCK = 14957; // 1
+static const uint64_t SH_FLD_PSIRFACC_TFSM_PCK = 14958; // 1
+static const uint64_t SH_FLD_PSIRFACC_TXSC_PCK = 14959; // 1
+static const uint64_t SH_FLD_PSIRXBFF_DATAO_PCK = 14960; // 1
+static const uint64_t SH_FLD_PSIRXBFF_DATA_PCK = 14961; // 1
+static const uint64_t SH_FLD_PSIRXBFF_RFC_PCK = 14962; // 1
+static const uint64_t SH_FLD_PSIRXEI_SHIFT_PCK = 14963; // 1
+static const uint64_t SH_FLD_PSIRXEI_TRANSMIT_PCK = 14964; // 1
+static const uint64_t SH_FLD_PSIRXINS_DATA_PCK = 14965; // 1
+static const uint64_t SH_FLD_PSIRXINS_OVERRUN = 14966; // 1
+static const uint64_t SH_FLD_PSIRXINS_RFGSHIFT_PCK = 14967; // 1
+static const uint64_t SH_FLD_PSIRXINS_RZRTMP_PCK = 14968; // 1
+static const uint64_t SH_FLD_PSIRXLC_CE_RF = 14969; // 1
+static const uint64_t SH_FLD_PSIRXLC_DATA_BUFF_PCK = 14970; // 1
+static const uint64_t SH_FLD_PSIRXLC_DATA_GXST1_PCK_2N = 14971; // 1
+static const uint64_t SH_FLD_PSIRXLC_DATA_PCK = 14972; // 1
+static const uint64_t SH_FLD_PSIRXLC_FSM_PCK = 14973; // 1
+static const uint64_t SH_FLD_PSIRXLC_RADDR_PCK = 14974; // 1
+static const uint64_t SH_FLD_PSIRXLC_RCTRL_PCK = 14975; // 1
+static const uint64_t SH_FLD_PSIRXLC_UE_RF = 14976; // 1
+static const uint64_t SH_FLD_PSITXBFF_DATA_PCK = 14977; // 1
+static const uint64_t SH_FLD_PSITXBFF_TDO_PCK = 14978; // 1
+static const uint64_t SH_FLD_PSITXBFF_TFC_PCK = 14979; // 1
+static const uint64_t SH_FLD_PSITXEI_SHIFT_PCK = 14980; // 1
+static const uint64_t SH_FLD_PSITXEI_TRANSMIT_PCK = 14981; // 1
+static const uint64_t SH_FLD_PSITXINS_DATA_PCK = 14982; // 1
+static const uint64_t SH_FLD_PSITXINS_PARITY = 14983; // 1
+static const uint64_t SH_FLD_PSITXINS_TZRTMP_PCK = 14984; // 1
+static const uint64_t SH_FLD_PSITXINS_UNDERRUN = 14985; // 1
+static const uint64_t SH_FLD_PSITXLC_CE_GX_2N = 14986; // 1
+static const uint64_t SH_FLD_PSITXLC_CE_RF = 14987; // 1
+static const uint64_t SH_FLD_PSITXLC_DATA_BUFF_PCK = 14988; // 1
+static const uint64_t SH_FLD_PSITXLC_DATA_GXST2_PCK_2N = 14989; // 1
+static const uint64_t SH_FLD_PSITXLC_DATA_GXST3_PCK_2N = 14990; // 1
+static const uint64_t SH_FLD_PSITXLC_FSM_PCK = 14991; // 1
+static const uint64_t SH_FLD_PSITXLC_TADDR_PCK = 14992; // 1
+static const uint64_t SH_FLD_PSITXLC_TCTRL_PCK = 14993; // 1
+static const uint64_t SH_FLD_PSITXLC_TDO_PCK = 14994; // 1
+static const uint64_t SH_FLD_PSITXLC_UE_GX_2N = 14995; // 1
+static const uint64_t SH_FLD_PSITXLC_UE_RF = 14996; // 1
+static const uint64_t SH_FLD_PSI_ALERT1 = 14997; // 1
+static const uint64_t SH_FLD_PSI_ALERT2 = 14998; // 1
+static const uint64_t SH_FLD_PSI_LINK_ENABLE = 14999; // 1
+static const uint64_t SH_FLD_PSI_LINK_INACTIVE_TRANS = 15000; // 1
+static const uint64_t SH_FLD_PSI_RESERVED0 = 15001; // 2
+static const uint64_t SH_FLD_PSI_RESERVED1 = 15002; // 2
+static const uint64_t SH_FLD_PSI_RESERVED2 = 15003; // 2
+static const uint64_t SH_FLD_PSI_RESERVED3 = 15004; // 2
+static const uint64_t SH_FLD_PSI_RESERVED4 = 15005; // 2
+static const uint64_t SH_FLD_PSI_UE = 15006; // 1
+static const uint64_t SH_FLD_PSI_XMIT_ERROR = 15007; // 1
+static const uint64_t SH_FLD_PSL_CMD_SUE = 15008; // 4
+static const uint64_t SH_FLD_PSL_CMD_SUE_ERRHOLD = 15009; // 2
+static const uint64_t SH_FLD_PSL_CMD_UE = 15010; // 4
+static const uint64_t SH_FLD_PSL_CMD_UE_ERRHOLD = 15011; // 2
+static const uint64_t SH_FLD_PSL_CREDIT_TIMEOUT_ERR = 15012; // 4
+static const uint64_t SH_FLD_PSSBRIDGE_ONGOING = 15013; // 1
+static const uint64_t SH_FLD_PSS_HAM = 15014; // 3
+static const uint64_t SH_FLD_PSS_HAM_CORE_INTERRUPT_MASK = 15015; // 1
+static const uint64_t SH_FLD_PSTATE_A_THRESHOLD = 15016; // 24
+static const uint64_t SH_FLD_PSTATE_A_THRESHOLD_LEN = 15017; // 24
+static const uint64_t SH_FLD_PSTATE_B_THRESHOLD = 15018; // 24
+static const uint64_t SH_FLD_PSTATE_B_THRESHOLD_LEN = 15019; // 24
+static const uint64_t SH_FLD_PS_SPARE1 = 15020; // 1
+static const uint64_t SH_FLD_PTAG_MAX_IN_USE = 15021; // 1
+static const uint64_t SH_FLD_PTAG_MAX_IN_USE_LEN = 15022; // 1
+static const uint64_t SH_FLD_PTCR = 15023; // 1
+static const uint64_t SH_FLD_PTCR_LEN = 15024; // 1
+static const uint64_t SH_FLD_PTSPARE6 = 15025; // 2
+static const uint64_t SH_FLD_PTSPARE7 = 15026; // 2
+static const uint64_t SH_FLD_PULL_EMPTY = 15027; // 4
+static const uint64_t SH_FLD_PULL_ENABLE = 15028; // 4
+static const uint64_t SH_FLD_PULL_FULL = 15029; // 4
+static const uint64_t SH_FLD_PULL_INTR_ACTION_0_1 = 15030; // 4
+static const uint64_t SH_FLD_PULL_INTR_ACTION_0_1_LEN = 15031; // 4
+static const uint64_t SH_FLD_PULL_LENGTH = 15032; // 4
+static const uint64_t SH_FLD_PULL_LENGTH_LEN = 15033; // 4
+static const uint64_t SH_FLD_PULL_READ_PTR = 15034; // 4
+static const uint64_t SH_FLD_PULL_READ_PTR_LEN = 15035; // 4
+static const uint64_t SH_FLD_PULL_READ_UNDERFLOW = 15036; // 4
+static const uint64_t SH_FLD_PULL_READ_UNDERFLOW_EN = 15037; // 4
+static const uint64_t SH_FLD_PULL_REGION = 15038; // 4
+static const uint64_t SH_FLD_PULL_REGION_LEN = 15039; // 4
+static const uint64_t SH_FLD_PULL_START = 15040; // 4
+static const uint64_t SH_FLD_PULL_START_LEN = 15041; // 4
+static const uint64_t SH_FLD_PULL_WRITE_OVERFLOW = 15042; // 4
+static const uint64_t SH_FLD_PULL_WRITE_PTR = 15043; // 4
+static const uint64_t SH_FLD_PULL_WRITE_PTR_LEN = 15044; // 4
+static const uint64_t SH_FLD_PULSE1_CNTR = 15045; // 1
+static const uint64_t SH_FLD_PULSE1_CNTR_LEN = 15046; // 1
+static const uint64_t SH_FLD_PULSE2_CNTR = 15047; // 1
+static const uint64_t SH_FLD_PULSE2_CNTR_LEN = 15048; // 1
+static const uint64_t SH_FLD_PULSE_DELAY = 15049; // 43
+static const uint64_t SH_FLD_PULSE_DELAY_LEN = 15050; // 43
+static const uint64_t SH_FLD_PULSE_DROOP_DATA = 15051; // 6
+static const uint64_t SH_FLD_PULSE_DROOP_DATA_LEN = 15052; // 6
+static const uint64_t SH_FLD_PULSE_DROOP_ENABLE = 15053; // 6
+static const uint64_t SH_FLD_PULSE_INPUT_SEL = 15054; // 43
+static const uint64_t SH_FLD_PUMP_MODE = 15055; // 1
+static const uint64_t SH_FLD_PUP_LITE_WAIT_SEL = 15056; // 4
+static const uint64_t SH_FLD_PUP_LITE_WAIT_SEL_LEN = 15057; // 4
+static const uint64_t SH_FLD_PUSH_EMPTY = 15058; // 6
+static const uint64_t SH_FLD_PUSH_ENABLE = 15059; // 6
+static const uint64_t SH_FLD_PUSH_FULL = 15060; // 6
+static const uint64_t SH_FLD_PUSH_INTR_ACTION_0_1 = 15061; // 6
+static const uint64_t SH_FLD_PUSH_INTR_ACTION_0_1_LEN = 15062; // 6
+static const uint64_t SH_FLD_PUSH_LENGTH = 15063; // 6
+static const uint64_t SH_FLD_PUSH_LENGTH_LEN = 15064; // 6
+static const uint64_t SH_FLD_PUSH_READ_PTR = 15065; // 6
+static const uint64_t SH_FLD_PUSH_READ_PTR_LEN = 15066; // 6
+static const uint64_t SH_FLD_PUSH_READ_UNDERFLOW = 15067; // 4
+static const uint64_t SH_FLD_PUSH_REGION = 15068; // 4
+static const uint64_t SH_FLD_PUSH_REGION_LEN = 15069; // 4
+static const uint64_t SH_FLD_PUSH_START = 15070; // 6
+static const uint64_t SH_FLD_PUSH_START_LEN = 15071; // 6
+static const uint64_t SH_FLD_PUSH_WRITE_OVERFLOW = 15072; // 4
+static const uint64_t SH_FLD_PUSH_WRITE_OVERFLOW_EN = 15073; // 4
+static const uint64_t SH_FLD_PUSH_WRITE_PTR = 15074; // 6
+static const uint64_t SH_FLD_PUSH_WRITE_PTR_LEN = 15075; // 6
+static const uint64_t SH_FLD_PU_BIT_ENABLES = 15076; // 1
+static const uint64_t SH_FLD_PU_BIT_ENABLES_LEN = 15077; // 1
+static const uint64_t SH_FLD_PU_CNTL_UNUSED = 15078; // 1
+static const uint64_t SH_FLD_PU_CNTL_UNUSED_LEN = 15079; // 1
+static const uint64_t SH_FLD_PU_COUNTS = 15080; // 8
+static const uint64_t SH_FLD_PU_COUNTS_LEN = 15081; // 8
+static const uint64_t SH_FLD_PVREF_ERROR_EN = 15082; // 1
+static const uint64_t SH_FLD_PVREF_ERROR_EN_LEN = 15083; // 1
+static const uint64_t SH_FLD_PVREF_ERROR_FINE = 15084; // 1
+static const uint64_t SH_FLD_PVREF_ERROR_GROSS = 15085; // 1
+static const uint64_t SH_FLD_PVREF_FAIL = 15086; // 12
+static const uint64_t SH_FLD_PVTN = 15087; // 8
+static const uint64_t SH_FLD_PVTNB = 15088; // 16
+static const uint64_t SH_FLD_PVTNL = 15089; // 8
+static const uint64_t SH_FLD_PVTNL_ENC = 15090; // 1
+static const uint64_t SH_FLD_PVTNL_ENC_LEN = 15091; // 1
+static const uint64_t SH_FLD_PVTNL_LEN = 15092; // 8
+static const uint64_t SH_FLD_PVTN_LEN = 15093; // 8
+static const uint64_t SH_FLD_PVTPB = 15094; // 16
+static const uint64_t SH_FLD_PVTPL = 15095; // 16
+static const uint64_t SH_FLD_PVTPL_ENC = 15096; // 1
+static const uint64_t SH_FLD_PVTPL_ENC_LEN = 15097; // 1
+static const uint64_t SH_FLD_PVTPL_LEN = 15098; // 16
+static const uint64_t SH_FLD_PVT_OVERRIDE = 15099; // 8
+static const uint64_t SH_FLD_PWR0 = 15100; // 12
+static const uint64_t SH_FLD_PWR1 = 15101; // 12
+static const uint64_t SH_FLD_QPPM_ONGOING = 15102; // 24
+static const uint64_t SH_FLD_QPPM_RDATA = 15103; // 24
+static const uint64_t SH_FLD_QPPM_RDATA_LEN = 15104; // 24
+static const uint64_t SH_FLD_QPPM_REG = 15105; // 24
+static const uint64_t SH_FLD_QPPM_REG_LEN = 15106; // 24
+static const uint64_t SH_FLD_QPPM_RNW = 15107; // 24
+static const uint64_t SH_FLD_QPPM_STATUS = 15108; // 24
+static const uint64_t SH_FLD_QPPM_STATUS_LEN = 15109; // 24
+static const uint64_t SH_FLD_QPPM_WDATA = 15110; // 24
+static const uint64_t SH_FLD_QPPM_WDATA_LEN = 15111; // 24
+static const uint64_t SH_FLD_QUA = 15112; // 8
+static const uint64_t SH_FLD_QUAD_CHECKSTOP = 15113; // 12
+static const uint64_t SH_FLD_QUAD_CLK_SB_OVERRIDE = 15114; // 24
+static const uint64_t SH_FLD_QUAD_CLK_SW_OVERRIDE = 15115; // 24
+static const uint64_t SH_FLD_QUAD_SEL = 15116; // 6
+static const uint64_t SH_FLD_QUAD_SEL_LEN = 15117; // 6
+static const uint64_t SH_FLD_QUAD_STOPPED = 15118; // 1
+static const uint64_t SH_FLD_QUAD_STOPPED_LEN = 15119; // 1
+static const uint64_t SH_FLD_QUA_LEN = 15120; // 8
+static const uint64_t SH_FLD_QUA_V = 15121; // 8
+static const uint64_t SH_FLD_QUEUED_RD_EN = 15122; // 12
+static const uint64_t SH_FLD_QUEUED_WR_EN = 15123; // 12
+static const uint64_t SH_FLD_QUEUE_DISABLE = 15124; // 6
+static const uint64_t SH_FLD_QUEUE_NOT_EMPTY = 15125; // 6
+static const uint64_t SH_FLD_QUIESCE = 15126; // 1
+static const uint64_t SH_FLD_QUIESCED = 15127; // 1
+static const uint64_t SH_FLD_QUIESCE_ACHEIVED = 15128; // 1
+static const uint64_t SH_FLD_QUIESCE_AUTO_RESET = 15129; // 1
+static const uint64_t SH_FLD_QUIESCE_DONE = 15130; // 2
+static const uint64_t SH_FLD_QUIESCE_FAILED = 15131; // 1
+static const uint64_t SH_FLD_QUIESCE_PB = 15132; // 1
+static const uint64_t SH_FLD_QUIESCE_REQUEST = 15133; // 1
+static const uint64_t SH_FLD_R = 15134; // 8
+static const uint64_t SH_FLD_R0_COUNT = 15135; // 12
+static const uint64_t SH_FLD_R0_COUNT_LEN = 15136; // 12
+static const uint64_t SH_FLD_R15_BIT_MAP = 15137; // 8
+static const uint64_t SH_FLD_R15_BIT_MAP_LEN = 15138; // 8
+static const uint64_t SH_FLD_R16_BIT_MAP = 15139; // 8
+static const uint64_t SH_FLD_R16_BIT_MAP_LEN = 15140; // 8
+static const uint64_t SH_FLD_R17_BIT_MAP = 15141; // 8
+static const uint64_t SH_FLD_R17_BIT_MAP_LEN = 15142; // 8
+static const uint64_t SH_FLD_R1_COUNT = 15143; // 12
+static const uint64_t SH_FLD_R1_COUNT_LEN = 15144; // 12
+static const uint64_t SH_FLD_R2_COUNT = 15145; // 12
+static const uint64_t SH_FLD_R2_COUNT_LEN = 15146; // 12
+static const uint64_t SH_FLD_RAND_ADDR_ALL_ADDR_MODE_EN = 15147; // 2
+static const uint64_t SH_FLD_RAND_ERROR_RATE = 15148; // 5
+static const uint64_t SH_FLD_RAND_ERROR_RATE_LEN = 15149; // 5
+static const uint64_t SH_FLD_RAND_EVENT = 15150; // 1
+static const uint64_t SH_FLD_RAND_EVENT_LEN = 15151; // 1
+static const uint64_t SH_FLD_RANGE = 15152; // 1
+static const uint64_t SH_FLD_RANGE_LEN = 15153; // 1
+static const uint64_t SH_FLD_RANK = 15154; // 8
+static const uint64_t SH_FLD_RANK_LEN = 15155; // 8
+static const uint64_t SH_FLD_RANK_OVERRIDE = 15156; // 8
+static const uint64_t SH_FLD_RANK_OVERRIDE_VALUE = 15157; // 8
+static const uint64_t SH_FLD_RANK_OVERRIDE_VALUE_LEN = 15158; // 8
+static const uint64_t SH_FLD_RANK_PAIR = 15159; // 8
+static const uint64_t SH_FLD_RANK_PAIR_LEN = 15160; // 8
+static const uint64_t SH_FLD_RANK_SM_1HOT = 15161; // 8
+static const uint64_t SH_FLD_RATE = 15162; // 14
+static const uint64_t SH_FLD_RATE_LEN = 15163; // 14
+static const uint64_t SH_FLD_RATIO = 15164; // 2
+static const uint64_t SH_FLD_RATIO_LEN = 15165; // 2
+static const uint64_t SH_FLD_RC = 15166; // 8
+static const uint64_t SH_FLD_RCDAT_RD_PARITY_ERR = 15167; // 12
+static const uint64_t SH_FLD_RCD_CAL_PARITY_ERROR = 15168; // 8
+static const uint64_t SH_FLD_RCD_PARITY_ERROR = 15169; // 16
+static const uint64_t SH_FLD_RCE_COUNT = 15170; // 2
+static const uint64_t SH_FLD_RCE_COUNT_LEN = 15171; // 2
+static const uint64_t SH_FLD_RCE_ETE_ATTN = 15172; // 2
+static const uint64_t SH_FLD_RCMD0_ADDR_PARITY_ERROR = 15173; // 2
+static const uint64_t SH_FLD_RCMD0_ADDR_PERR = 15174; // 1
+static const uint64_t SH_FLD_RCMD0_TTAG_PERR = 15175; // 1
+static const uint64_t SH_FLD_RCMD1_ADDR_PARITY_ERROR = 15176; // 2
+static const uint64_t SH_FLD_RCMD1_ADDR_PERR = 15177; // 1
+static const uint64_t SH_FLD_RCMD1_TTAG_PERR = 15178; // 1
+static const uint64_t SH_FLD_RCMD2_ADDR_PARITY_ERROR = 15179; // 2
+static const uint64_t SH_FLD_RCMD2_ADDR_PERR = 15180; // 1
+static const uint64_t SH_FLD_RCMD2_TTAG_PERR = 15181; // 1
+static const uint64_t SH_FLD_RCMD3_ADDR_PARITY_ERROR = 15182; // 2
+static const uint64_t SH_FLD_RCMD3_ADDR_PERR = 15183; // 1
+static const uint64_t SH_FLD_RCMD3_TTAG_PERR = 15184; // 1
+static const uint64_t SH_FLD_RCMD_ASYNC_IF = 15185; // 8
+static const uint64_t SH_FLD_RCMD_ERR_INJ = 15186; // 8
+static const uint64_t SH_FLD_RCS_RECOVERY_FAILED_ERRHOLD = 15187; // 2
+static const uint64_t SH_FLD_RCS_RECOVERY_TIMEOUT_ERRHOLD = 15188; // 2
+static const uint64_t SH_FLD_RCS_STATE_MACHINE_ERRHOLD = 15189; // 2
+static const uint64_t SH_FLD_RCTRL_CONFIG = 15190; // 8
+static const uint64_t SH_FLD_RCTRL_CONFIG_LEN = 15191; // 8
+static const uint64_t SH_FLD_RCTRL_DEBUG_SEL = 15192; // 4
+static const uint64_t SH_FLD_RCTRL_DEBUG_SEL_LEN = 15193; // 4
+static const uint64_t SH_FLD_RCTRL_WAT_ACTION_SEL = 15194; // 4
+static const uint64_t SH_FLD_RCTRL_WAT_ACTION_SEL_LEN = 15195; // 4
+static const uint64_t SH_FLD_RCVD_POISONED_CIST_DATA = 15196; // 1
+static const uint64_t SH_FLD_RCV_BRDCST_GROUP = 15197; // 1
+static const uint64_t SH_FLD_RCV_BRDCST_GROUP_LEN = 15198; // 1
+static const uint64_t SH_FLD_RCV_CAPTURE = 15199; // 1
+static const uint64_t SH_FLD_RCV_CAPTURE_LEN = 15200; // 1
+static const uint64_t SH_FLD_RCV_CHIPID = 15201; // 1
+static const uint64_t SH_FLD_RCV_CHIPID_LEN = 15202; // 1
+static const uint64_t SH_FLD_RCV_CREDIT_OVERFLOW_ENA = 15203; // 6
+static const uint64_t SH_FLD_RCV_DATATO_DIV = 15204; // 1
+static const uint64_t SH_FLD_RCV_DATATO_DIV_LEN = 15205; // 1
+static const uint64_t SH_FLD_RCV_ERROR = 15206; // 1
+static const uint64_t SH_FLD_RCV_GROUPID = 15207; // 1
+static const uint64_t SH_FLD_RCV_GROUPID_LEN = 15208; // 1
+static const uint64_t SH_FLD_RCV_IN_PROGRESS = 15209; // 1
+static const uint64_t SH_FLD_RCV_PB_OP_HANG_ERR = 15210; // 1
+static const uint64_t SH_FLD_RCV_RESERVATION_SET = 15211; // 1
+static const uint64_t SH_FLD_RCV_RESET = 15212; // 1
+static const uint64_t SH_FLD_RCV_TOD_STATE = 15213; // 1
+static const uint64_t SH_FLD_RCV_TOD_STATE_LEN = 15214; // 1
+static const uint64_t SH_FLD_RCV_TTAG_PARITY_ERR = 15215; // 1
+static const uint64_t SH_FLD_RCV_WRITE_IN_PROGRESS = 15216; // 1
+static const uint64_t SH_FLD_RC_ADDR_PAR = 15217; // 1
+static const uint64_t SH_FLD_RC_ENABLE_AUTO_RECAL = 15218; // 2
+static const uint64_t SH_FLD_RC_ENABLE_BER_TEST = 15219; // 4
+static const uint64_t SH_FLD_RC_ENABLE_CM_COARSE_CAL = 15220; // 6
+static const uint64_t SH_FLD_RC_ENABLE_CM_FINE_CAL = 15221; // 6
+static const uint64_t SH_FLD_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 15222; // 6
+static const uint64_t SH_FLD_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 15223; // 6
+static const uint64_t SH_FLD_RC_ENABLE_CTLE_COARSE_CAL = 15224; // 6
+static const uint64_t SH_FLD_RC_ENABLE_CTLE_EDGE_OFFSET_CAL = 15225; // 2
+static const uint64_t SH_FLD_RC_ENABLE_CTLE_EDGE_TRACK_ONLY = 15226; // 4
+static const uint64_t SH_FLD_RC_ENABLE_DAC_H1_CAL = 15227; // 6
+static const uint64_t SH_FLD_RC_ENABLE_DAC_H1_TO_A_CAL = 15228; // 4
+static const uint64_t SH_FLD_RC_ENABLE_DDC = 15229; // 6
+static const uint64_t SH_FLD_RC_ENABLE_DFE_H1_CAL = 15230; // 6
+static const uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_CAL = 15231; // 4
+static const uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP = 15232; // 4
+static const uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 15233; // 4
+static const uint64_t SH_FLD_RC_ENABLE_DFE_H6_H12_FAST_MODE = 15234; // 4
+static const uint64_t SH_FLD_RC_ENABLE_DFE_VOLTAGE_MODE = 15235; // 4
+static const uint64_t SH_FLD_RC_ENABLE_H1AP_TWEAK = 15236; // 6
+static const uint64_t SH_FLD_RC_ENABLE_INTEG_LATCH_OFFSET_CAL = 15237; // 6
+static const uint64_t SH_FLD_RC_ENABLE_RESULT_CHECK = 15238; // 4
+static const uint64_t SH_FLD_RC_ENABLE_VGA_AMAX_MODE = 15239; // 6
+static const uint64_t SH_FLD_RC_ENABLE_VGA_CAL = 15240; // 6
+static const uint64_t SH_FLD_RC_ENABLE_VGA_EDGE_OFFSET_CAL = 15241; // 2
+static const uint64_t SH_FLD_RC_LOAD_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV = 15242; // 12
+static const uint64_t SH_FLD_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR = 15243; // 12
+static const uint64_t SH_FLD_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR_FOR_HYP = 15244; // 12
+static const uint64_t SH_FLD_RC_MASK = 15245; // 8
+static const uint64_t SH_FLD_RC_POWBUS_DATA_CE_ERR_FROM_F2CHK = 15246; // 12
+static const uint64_t SH_FLD_RC_POWBUS_DATA_SUE_ERR_FROM_F2CHK = 15247; // 12
+static const uint64_t SH_FLD_RC_POWBUS_DATA_UE_ERR_FROM_F2CHK = 15248; // 12
+static const uint64_t SH_FLD_RC_POWERBUS_DATA_TIMEOUT = 15249; // 12
+static const uint64_t SH_FLD_RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV = 15250; // 12
+static const uint64_t SH_FLD_RC_STORE_RECEIVED_PB_CRESP_ADR_ERR = 15251; // 12
+static const uint64_t SH_FLD_RC_TTAG_PAR = 15252; // 1
+static const uint64_t SH_FLD_RDADDR_ARB_BAD_HAND = 15253; // 2
+static const uint64_t SH_FLD_RDATA = 15254; // 1
+static const uint64_t SH_FLD_RDATA_LEN = 15255; // 1
+static const uint64_t SH_FLD_RDCLK_ALIGN = 15256; // 8
+static const uint64_t SH_FLD_RDCMP = 15257; // 2
+static const uint64_t SH_FLD_RDCMP_LEN = 15258; // 2
+static const uint64_t SH_FLD_RDIV = 15259; // 14
+static const uint64_t SH_FLD_RDIV_LEN = 15260; // 10
+static const uint64_t SH_FLD_RDQ_ABORT_OP = 15261; // 1
+static const uint64_t SH_FLD_RDQ_ABORT_TRM = 15262; // 1
+static const uint64_t SH_FLD_RDQ_BAD_CRESP = 15263; // 1
+static const uint64_t SH_FLD_RDQ_DATA_HANG = 15264; // 1
+static const uint64_t SH_FLD_RDQ_FSM_PERR = 15265; // 1
+static const uint64_t SH_FLD_RDQ_OP_HANG = 15266; // 1
+static const uint64_t SH_FLD_RDQ_OVERFLOW = 15267; // 1
+static const uint64_t SH_FLD_RDWR_ACCESS_EN = 15268; // 2
+static const uint64_t SH_FLD_RDWR_ADDR = 15269; // 2
+static const uint64_t SH_FLD_RDWR_ADDR_LEN = 15270; // 2
+static const uint64_t SH_FLD_RDWR_OP_BUSY = 15271; // 1
+static const uint64_t SH_FLD_RDWR_RDWR_DATA = 15272; // 2
+static const uint64_t SH_FLD_RDWR_RDWR_DATA_LEN = 15273; // 2
+static const uint64_t SH_FLD_RDWR_READ_STATUS = 15274; // 2
+static const uint64_t SH_FLD_RDWR_REQ_PEND = 15275; // 2
+static const uint64_t SH_FLD_RDWR_UPDATE_ERROR = 15276; // 2
+static const uint64_t SH_FLD_RDWR_WRITE_MODE = 15277; // 2
+static const uint64_t SH_FLD_RDWR_WRITE_STATUS = 15278; // 2
+static const uint64_t SH_FLD_RDWR_WR_ENABLE = 15279; // 2
+static const uint64_t SH_FLD_RDX_BUS0_STG0_SEL = 15280; // 1
+static const uint64_t SH_FLD_RDX_BUS0_STG0_SEL_LEN = 15281; // 1
+static const uint64_t SH_FLD_RDX_BUS0_STG1_SEL = 15282; // 1
+static const uint64_t SH_FLD_RDX_BUS0_STG2_SEL = 15283; // 1
+static const uint64_t SH_FLD_RDX_BUS1_STG0_SEL = 15284; // 1
+static const uint64_t SH_FLD_RDX_BUS1_STG0_SEL_LEN = 15285; // 1
+static const uint64_t SH_FLD_RDX_BUS1_STG1_SEL = 15286; // 1
+static const uint64_t SH_FLD_RDX_BUS1_STG2_SEL = 15287; // 1
+static const uint64_t SH_FLD_RD_ADDR_0_7 = 15288; // 1
+static const uint64_t SH_FLD_RD_ADDR_0_7_LEN = 15289; // 1
+static const uint64_t SH_FLD_RD_CNTL = 15290; // 8
+static const uint64_t SH_FLD_RD_CNTL_MASK = 15291; // 8
+static const uint64_t SH_FLD_RD_DATA_COUNT = 15292; // 1
+static const uint64_t SH_FLD_RD_DATA_COUNT_LEN = 15293; // 1
+static const uint64_t SH_FLD_RD_DATA_PARITY_ERROR = 15294; // 3
+static const uint64_t SH_FLD_RD_ECC_CE = 15295; // 1
+static const uint64_t SH_FLD_RD_ECC_UE = 15296; // 1
+static const uint64_t SH_FLD_RD_GO_M_QOS = 15297; // 2
+static const uint64_t SH_FLD_RD_MACHINE_HANG = 15298; // 12
+static const uint64_t SH_FLD_RD_RST_INTRPT_FACES = 15299; // 1
+static const uint64_t SH_FLD_RD_RST_INTRPT_PIB = 15300; // 1
+static const uint64_t SH_FLD_RD_SCOPE = 15301; // 24
+static const uint64_t SH_FLD_RD_SCOPE_LEN = 15302; // 24
+static const uint64_t SH_FLD_RD_SLVNUM = 15303; // 6
+static const uint64_t SH_FLD_RD_SLVNUM_LEN = 15304; // 6
+static const uint64_t SH_FLD_READ_ASYNC_INTERFACE_PARITY_ERROR = 15305; // 8
+static const uint64_t SH_FLD_READ_ASYNC_INTERFACE_SEQUENCE_ERROR = 15306; // 8
+static const uint64_t SH_FLD_READ_BUFFER_OVERFLOW_ERROR = 15307; // 8
+static const uint64_t SH_FLD_READ_COMPARE_REQUIRED = 15308; // 64
+static const uint64_t SH_FLD_READ_COMPLETE = 15309; // 1
+static const uint64_t SH_FLD_READ_CONTINUE_0 = 15310; // 2
+static const uint64_t SH_FLD_READ_CONTINUE_1 = 15311; // 1
+static const uint64_t SH_FLD_READ_CONTINUE_2 = 15312; // 1
+static const uint64_t SH_FLD_READ_CONTINUE_3 = 15313; // 1
+static const uint64_t SH_FLD_READ_CONTROL_OVERFLOW_ERROR = 15314; // 8
+static const uint64_t SH_FLD_READ_COUNT = 15315; // 8
+static const uint64_t SH_FLD_READ_COUNT_LEN = 15316; // 8
+static const uint64_t SH_FLD_READ_CRD_POOL = 15317; // 1
+static const uint64_t SH_FLD_READ_CRD_POOL_LEN = 15318; // 1
+static const uint64_t SH_FLD_READ_CTR = 15319; // 8
+static const uint64_t SH_FLD_READ_DEBUG_SELECT = 15320; // 8
+static const uint64_t SH_FLD_READ_DEBUG_SELECT_LEN = 15321; // 8
+static const uint64_t SH_FLD_READ_ECC_DATAPATH_PARITY_ERROR = 15322; // 8
+static const uint64_t SH_FLD_READ_ENABLE = 15323; // 129
+static const uint64_t SH_FLD_READ_EPSILON_MODE = 15324; // 2
+static const uint64_t SH_FLD_READ_EPSILON_TIER0 = 15325; // 2
+static const uint64_t SH_FLD_READ_EPSILON_TIER0_LEN = 15326; // 2
+static const uint64_t SH_FLD_READ_EPSILON_TIER1 = 15327; // 2
+static const uint64_t SH_FLD_READ_EPSILON_TIER1_LEN = 15328; // 2
+static const uint64_t SH_FLD_READ_EPSILON_TIER2 = 15329; // 2
+static const uint64_t SH_FLD_READ_EPSILON_TIER2_LEN = 15330; // 2
+static const uint64_t SH_FLD_READ_ERR_INJECT0 = 15331; // 8
+static const uint64_t SH_FLD_READ_ERR_INJECT0_LEN = 15332; // 8
+static const uint64_t SH_FLD_READ_INVALID_FACES = 15333; // 1
+static const uint64_t SH_FLD_READ_INVALID_PIB = 15334; // 1
+static const uint64_t SH_FLD_READ_LATENCY_OFFSET = 15335; // 8
+static const uint64_t SH_FLD_READ_LATENCY_OFFSET_LEN = 15336; // 8
+static const uint64_t SH_FLD_READ_NOT_WRITE_0 = 15337; // 2
+static const uint64_t SH_FLD_READ_NOT_WRITE_1 = 15338; // 1
+static const uint64_t SH_FLD_READ_NOT_WRITE_2 = 15339; // 1
+static const uint64_t SH_FLD_READ_NOT_WRITE_3 = 15340; // 1
+static const uint64_t SH_FLD_READ_NVLD = 15341; // 1
+static const uint64_t SH_FLD_READ_OR_WRITE_DATA = 15342; // 64
+static const uint64_t SH_FLD_READ_OR_WRITE_DATA_LEN = 15343; // 64
+static const uint64_t SH_FLD_READ_PAR_NOT_SEQ = 15344; // 8
+static const uint64_t SH_FLD_READ_POOL = 15345; // 1
+static const uint64_t SH_FLD_READ_POOL_LEN = 15346; // 1
+static const uint64_t SH_FLD_READ_PREFETCH_CTL = 15347; // 4
+static const uint64_t SH_FLD_READ_PREFETCH_CTL_LEN = 15348; // 4
+static const uint64_t SH_FLD_READ_RESPONSE_DELAY_ENABLE = 15349; // 2
+static const uint64_t SH_FLD_READ_RST_INTERRUPT_FACES = 15350; // 1
+static const uint64_t SH_FLD_READ_RST_INTERRUPT_PIB = 15351; // 1
+static const uint64_t SH_FLD_READ_TTYPE = 15352; // 4
+static const uint64_t SH_FLD_RECAL_ABORT = 15353; // 48
+static const uint64_t SH_FLD_RECAL_ABORT_DL_MASK = 15354; // 2
+static const uint64_t SH_FLD_RECAL_DONE_DL_MASK = 15355; // 2
+static const uint64_t SH_FLD_RECAL_ERROR = 15356; // 8
+static const uint64_t SH_FLD_RECAL_LANE_TO_MONITOR = 15357; // 6
+static const uint64_t SH_FLD_RECAL_LANE_TO_MONITOR_LEN = 15358; // 6
+static const uint64_t SH_FLD_RECAL_MAX_SPARES_EXCEEDED = 15359; // 8
+static const uint64_t SH_FLD_RECAL_REQ = 15360; // 48
+static const uint64_t SH_FLD_RECAL_REQ_DL_MASK = 15361; // 2
+static const uint64_t SH_FLD_RECAL_SPARE_DEPLOYED = 15362; // 8
+static const uint64_t SH_FLD_RECEIVED = 15363; // 1
+static const uint64_t SH_FLD_RECEIVED_ERROR = 15364; // 1
+static const uint64_t SH_FLD_RECEIVER_MODE = 15365; // 3
+static const uint64_t SH_FLD_RECEIVER_MODE_LEN = 15366; // 3
+static const uint64_t SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER = 15367; // 1
+static const uint64_t SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER_LEN = 15368; // 1
+static const uint64_t SH_FLD_RECOVERABLE_ERROR = 15369; // 2
+static const uint64_t SH_FLD_RECOVERY_BLK = 15370; // 24
+static const uint64_t SH_FLD_RECOVERY_BLK_EXTEND = 15371; // 24
+static const uint64_t SH_FLD_RECOVERY_FAILED = 15372; // 6
+static const uint64_t SH_FLD_RECOVERY_HANG_DETECTED = 15373; // 2
+static const uint64_t SH_FLD_RECR_PE = 15374; // 8
+static const uint64_t SH_FLD_REC_ACK_DEAD_ERROR = 15375; // 2
+static const uint64_t SH_FLD_REC_LIMIT = 15376; // 24
+static const uint64_t SH_FLD_REC_LIMIT_LEN = 15377; // 24
+static const uint64_t SH_FLD_REC_PB_SM_ERROR_ERR = 15378; // 2
+static const uint64_t SH_FLD_REC_SM_ERROR_ERR = 15379; // 2
+static const uint64_t SH_FLD_REC_UPDATE_ERROR = 15380; // 2
+static const uint64_t SH_FLD_REDIS_PRIORITY = 15381; // 1
+static const uint64_t SH_FLD_REDIS_PRIORITY_LEN = 15382; // 1
+static const uint64_t SH_FLD_REDIS_RSD = 15383; // 1
+static const uint64_t SH_FLD_REDIS_RSD_LEN = 15384; // 1
+static const uint64_t SH_FLD_REFCLKSEL = 15385; // 4
+static const uint64_t SH_FLD_REFCLK_0_TERM_DIS_DC = 15386; // 3
+static const uint64_t SH_FLD_REFCLK_1_TERM_DIS_DC = 15387; // 3
+static const uint64_t SH_FLD_REFCLK_CLKMUX0_SEL = 15388; // 43
+static const uint64_t SH_FLD_REFCLK_CLKMUX1_SEL = 15389; // 43
+static const uint64_t SH_FLD_REFISINK = 15390; // 3
+static const uint64_t SH_FLD_REFISINK_LEN = 15391; // 3
+static const uint64_t SH_FLD_REFISRC = 15392; // 3
+static const uint64_t SH_FLD_REFISRC_LEN = 15393; // 3
+static const uint64_t SH_FLD_REFRESH_ALL_RANKS = 15394; // 8
+static const uint64_t SH_FLD_REFRESH_BLOCK_CONFIG = 15395; // 8
+static const uint64_t SH_FLD_REFRESH_BLOCK_CONFIG_LEN = 15396; // 8
+static const uint64_t SH_FLD_REFRESH_CONTROL = 15397; // 8
+static const uint64_t SH_FLD_REFRESH_CONTROL_LEN = 15398; // 8
+static const uint64_t SH_FLD_REFRESH_COUNT = 15399; // 8
+static const uint64_t SH_FLD_REFRESH_COUNT_LEN = 15400; // 8
+static const uint64_t SH_FLD_REFRESH_INTERVAL = 15401; // 8
+static const uint64_t SH_FLD_REFRESH_INTERVAL_LEN = 15402; // 8
+static const uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_EN = 15403; // 2
+static const uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL = 15404; // 2
+static const uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN = 15405; // 2
+static const uint64_t SH_FLD_REFRESH_OVERRUN = 15406; // 16
+static const uint64_t SH_FLD_REFVREG = 15407; // 3
+static const uint64_t SH_FLD_REFVREG_LEN = 15408; // 3
+static const uint64_t SH_FLD_REG = 15409; // 19
+static const uint64_t SH_FLD_REGF = 15410; // 43
+static const uint64_t SH_FLD_REGION = 15411; // 72
+static const uint64_t SH_FLD_REGION_LEN = 15412; // 72
+static const uint64_t SH_FLD_REGISTER = 15413; // 3
+static const uint64_t SH_FLD_REGISTER_LEN = 15414; // 3
+static const uint64_t SH_FLD_REGISTER_PE = 15415; // 4
+static const uint64_t SH_FLD_REGISTER_VALID = 15416; // 4
+static const uint64_t SH_FLD_REGS = 15417; // 1
+static const uint64_t SH_FLD_REGSEL = 15418; // 4
+static const uint64_t SH_FLD_REGSEL_LEN = 15419; // 4
+static const uint64_t SH_FLD_REGS_IORESET = 15420; // 48
+static const uint64_t SH_FLD_REGS_LEN = 15421; // 1
+static const uint64_t SH_FLD_REGS_ORDERING_TAG = 15422; // 1
+static const uint64_t SH_FLD_REGS_ORDERING_TAG_LEN = 15423; // 1
+static const uint64_t SH_FLD_REG_ADDR_LENGTH = 15424; // 1
+static const uint64_t SH_FLD_REG_ADDR_LENGTH_LEN = 15425; // 1
+static const uint64_t SH_FLD_REG_ADDR_LEN_0 = 15426; // 1
+static const uint64_t SH_FLD_REG_ADDR_LEN_0_LEN = 15427; // 1
+static const uint64_t SH_FLD_REG_ADDR_LEN_1 = 15428; // 1
+static const uint64_t SH_FLD_REG_ADDR_LEN_1_LEN = 15429; // 1
+static const uint64_t SH_FLD_REG_ADDR_LEN_2 = 15430; // 1
+static const uint64_t SH_FLD_REG_ADDR_LEN_2_LEN = 15431; // 1
+static const uint64_t SH_FLD_REG_ADDR_LEN_3 = 15432; // 1
+static const uint64_t SH_FLD_REG_ADDR_LEN_3_LEN = 15433; // 1
+static const uint64_t SH_FLD_REG_DP16 = 15434; // 16
+static const uint64_t SH_FLD_REG_DP16_LEN = 15435; // 16
+static const uint64_t SH_FLD_REG_ENABLE = 15436; // 1
+static const uint64_t SH_FLD_REG_FIFO_SIZE_EQ_1 = 15437; // 1
+static const uint64_t SH_FLD_REG_LEN = 15438; // 19
+static const uint64_t SH_FLD_REG_UNUSED = 15439; // 1
+static const uint64_t SH_FLD_REG_UNUSED_LEN = 15440; // 1
+static const uint64_t SH_FLD_REG_WAKEUP_C0 = 15441; // 24
+static const uint64_t SH_FLD_REG_WAKEUP_C1 = 15442; // 24
+static const uint64_t SH_FLD_REINIT_CREDITS = 15443; // 1
+static const uint64_t SH_FLD_REJECTED_PASTE_CMD = 15444; // 2
+static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_ADD = 15445; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_AND = 15446; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_E = 15447; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S = 15448; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U = 15449; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S = 15450; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U = 15451; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_U = 15452; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_OR = 15453; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMWF_XOR = 15454; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMW_ADD = 15455; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMW_AND = 15456; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S = 15457; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U = 15458; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S = 15459; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U = 15460; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMW_OR = 15461; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_ARMW_XOR = 15462; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_CL_DMA_INJ = 15463; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_CL_DMA_W = 15464; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_CL_DMA_W_HP = 15465; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_CL_RD_NC_F0 = 15466; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_DMA_PR_W = 15467; // 12
+static const uint64_t SH_FLD_RELAXED_CMD_PR_DMA_INJ = 15468; // 12
+static const uint64_t SH_FLD_RELAXED_RESERVED0 = 15469; // 12
+static const uint64_t SH_FLD_RELAXED_RESERVED0_LEN = 15470; // 12
+static const uint64_t SH_FLD_RELAXED_RESERVED1 = 15471; // 12
+static const uint64_t SH_FLD_RELAXED_RESERVED1_LEN = 15472; // 12
+static const uint64_t SH_FLD_RELAXED_RESERVED2 = 15473; // 12
+static const uint64_t SH_FLD_RELAXED_RESERVED2_LEN = 15474; // 12
+static const uint64_t SH_FLD_RELAXED_RESERVED3 = 15475; // 12
+static const uint64_t SH_FLD_RELAXED_RESERVED3_LEN = 15476; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE0_MASK = 15477; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE0_MASK_LEN = 15478; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE0_MATCH = 15479; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE0_MATCH_LEN = 15480; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE0_RDENA = 15481; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE0_WRENA = 15482; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE1_MASK = 15483; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE1_MASK_LEN = 15484; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE1_MATCH = 15485; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE1_MATCH_LEN = 15486; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE1_RDENA = 15487; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE1_WRENA = 15488; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE2_MASK = 15489; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE2_MASK_LEN = 15490; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE2_MATCH = 15491; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE2_MATCH_LEN = 15492; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE2_RDENA = 15493; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE2_WRENA = 15494; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE3_MASK = 15495; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE3_MASK_LEN = 15496; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE3_MATCH = 15497; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE3_MATCH_LEN = 15498; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE3_RDENA = 15499; // 12
+static const uint64_t SH_FLD_RELAXED_SOURCE3_WRENA = 15500; // 12
+static const uint64_t SH_FLD_RELAXED_WR = 15501; // 1
+static const uint64_t SH_FLD_RELAXED_WR_ORDERING = 15502; // 1
+static const uint64_t SH_FLD_REL_ASYNC_PARITY_ERROR = 15503; // 8
+static const uint64_t SH_FLD_REL_ASYNC_SEQUENCE_ERROR = 15504; // 8
+static const uint64_t SH_FLD_REL_MERGE_ASYNC_PARITY_ERROR = 15505; // 8
+static const uint64_t SH_FLD_REL_MERGE_ASYNC_SEQUENCE_ERROR = 15506; // 8
+static const uint64_t SH_FLD_REMAINING_WORDS = 15507; // 1
+static const uint64_t SH_FLD_REMAINING_WORDS_LEN = 15508; // 1
+static const uint64_t SH_FLD_REMAP_DEST = 15509; // 1
+static const uint64_t SH_FLD_REMAP_DEST_LEN = 15510; // 1
+static const uint64_t SH_FLD_REMAP_SOURCE = 15511; // 1
+static const uint64_t SH_FLD_REMAP_SOURCE_LEN = 15512; // 1
+static const uint64_t SH_FLD_REMOTE_LATENCY_DIFFERENCE = 15513; // 5
+static const uint64_t SH_FLD_REMOTE_LATENCY_DIFFERENCE_LEN = 15514; // 5
+static const uint64_t SH_FLD_REMOTE_LATENCY_DIFFERENCE_VALID = 15515; // 5
+static const uint64_t SH_FLD_REMOTE_LATENCY_LONGER_LINK = 15516; // 5
+static const uint64_t SH_FLD_REMOTE_NODAL_EPSILON = 15517; // 8
+static const uint64_t SH_FLD_REMOTE_NODAL_EPSILON_LEN = 15518; // 8
+static const uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION = 15519; // 1
+static const uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR = 15520; // 1
+static const uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR_LEN = 15521; // 1
+static const uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_LEN = 15522; // 1
+static const uint64_t SH_FLD_REMOTE_SYNC_CHECK_M_CPS_DISABLE = 15523; // 1
+static const uint64_t SH_FLD_REMOTE_SYNC_DISABLE = 15524; // 1
+static const uint64_t SH_FLD_REMOTE_SYNC_ERROR_DISABLE = 15525; // 1
+static const uint64_t SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX = 15526; // 1
+static const uint64_t SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX_LEN = 15527; // 1
+static const uint64_t SH_FLD_REM_0 = 15528; // 6
+static const uint64_t SH_FLD_REM_0_LEN = 15529; // 6
+static const uint64_t SH_FLD_REM_1 = 15530; // 6
+static const uint64_t SH_FLD_REM_1_LEN = 15531; // 6
+static const uint64_t SH_FLD_REM_2 = 15532; // 6
+static const uint64_t SH_FLD_REM_2_LEN = 15533; // 6
+static const uint64_t SH_FLD_REM_3 = 15534; // 6
+static const uint64_t SH_FLD_REM_3_LEN = 15535; // 6
+static const uint64_t SH_FLD_REPAIR_DONE = 15536; // 4
+static const uint64_t SH_FLD_REPAIR_FAILED = 15537; // 4
+static const uint64_t SH_FLD_REPEAT_CMD_CNT = 15538; // 64
+static const uint64_t SH_FLD_REPEAT_CMD_CNT_LEN = 15539; // 64
+static const uint64_t SH_FLD_REPLAY_BUFFER_SIZE = 15540; // 2
+static const uint64_t SH_FLD_REPLAY_BUFFER_SIZE_LEN = 15541; // 2
+static const uint64_t SH_FLD_REPLAY_CAP_ADDR = 15542; // 10
+static const uint64_t SH_FLD_REPLAY_CAP_ADDR_LEN = 15543; // 10
+static const uint64_t SH_FLD_REPLAY_CAP_INST = 15544; // 10
+static const uint64_t SH_FLD_REPLAY_CAP_INST_LEN = 15545; // 4
+static const uint64_t SH_FLD_REPLAY_CAP_SYN = 15546; // 10
+static const uint64_t SH_FLD_REPLAY_CAP_SYN_LEN = 15547; // 10
+static const uint64_t SH_FLD_REPLAY_CAP_VALID = 15548; // 10
+static const uint64_t SH_FLD_REPORT_SL_CHKBIT_ERR = 15549; // 5
+static const uint64_t SH_FLD_REPR = 15550; // 43
+static const uint64_t SH_FLD_REPTEST_ENABLE = 15551; // 1
+static const uint64_t SH_FLD_REPTEST_MATCH_TH = 15552; // 1
+static const uint64_t SH_FLD_REPTEST_MATCH_TH_LEN = 15553; // 1
+static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0 = 15554; // 1
+static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0_LEN = 15555; // 1
+static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1 = 15556; // 1
+static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN = 15557; // 1
+static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_TH = 15558; // 1
+static const uint64_t SH_FLD_REPTEST_SOFT_FAIL_TH_LEN = 15559; // 1
+static const uint64_t SH_FLD_REQ = 15560; // 43
+static const uint64_t SH_FLD_REQUEST = 15561; // 1
+static const uint64_t SH_FLD_REQUEST_LEN = 15562; // 1
+static const uint64_t SH_FLD_REQ_INTR_PAYLOAD = 15563; // 30
+static const uint64_t SH_FLD_REQ_INTR_PAYLOAD_LEN = 15564; // 30
+static const uint64_t SH_FLD_REQ_INTR_TYPE = 15565; // 30
+static const uint64_t SH_FLD_REQ_INTR_TYPE_LEN = 15566; // 30
+static const uint64_t SH_FLD_REQ_RESET_FR_SBE = 15567; // 1
+static const uint64_t SH_FLD_REQ_RESET_FR_SP = 15568; // 1
+static const uint64_t SH_FLD_RESERVATION_EN = 15569; // 1
+static const uint64_t SH_FLD_RESERVED = 15570; // 134
+static const uint64_t SH_FLD_RESERVED0 = 15571; // 9
+static const uint64_t SH_FLD_RESERVED0_3 = 15572; // 4
+static const uint64_t SH_FLD_RESERVED0_3_LEN = 15573; // 4
+static const uint64_t SH_FLD_RESERVED0_LEN = 15574; // 9
+static const uint64_t SH_FLD_RESERVED1 = 15575; // 267
+static const uint64_t SH_FLD_RESERVED12_15 = 15576; // 4
+static const uint64_t SH_FLD_RESERVED12_15_LEN = 15577; // 4
+static const uint64_t SH_FLD_RESERVED14 = 15578; // 4
+static const uint64_t SH_FLD_RESERVED15 = 15579; // 4
+static const uint64_t SH_FLD_RESERVED18 = 15580; // 4
+static const uint64_t SH_FLD_RESERVED19 = 15581; // 4
+static const uint64_t SH_FLD_RESERVED19_22 = 15582; // 4
+static const uint64_t SH_FLD_RESERVED19_22_LEN = 15583; // 4
+static const uint64_t SH_FLD_RESERVED19_31 = 15584; // 4
+static const uint64_t SH_FLD_RESERVED19_31_LEN = 15585; // 4
+static const uint64_t SH_FLD_RESERVED1_2 = 15586; // 4
+static const uint64_t SH_FLD_RESERVED1_2_LEN = 15587; // 4
+static const uint64_t SH_FLD_RESERVED1_LEN = 15588; // 248
+static const uint64_t SH_FLD_RESERVED2 = 15589; // 114
+static const uint64_t SH_FLD_RESERVED20 = 15590; // 16
+static const uint64_t SH_FLD_RESERVED21 = 15591; // 4
+static const uint64_t SH_FLD_RESERVED22 = 15592; // 4
+static const uint64_t SH_FLD_RESERVED22_31 = 15593; // 8
+static const uint64_t SH_FLD_RESERVED22_31_LEN = 15594; // 8
+static const uint64_t SH_FLD_RESERVED23 = 15595; // 4
+static const uint64_t SH_FLD_RESERVED25 = 15596; // 4
+static const uint64_t SH_FLD_RESERVED26 = 15597; // 4
+static const uint64_t SH_FLD_RESERVED27 = 15598; // 4
+static const uint64_t SH_FLD_RESERVED28 = 15599; // 4
+static const uint64_t SH_FLD_RESERVED28_31 = 15600; // 10
+static const uint64_t SH_FLD_RESERVED28_31_LEN = 15601; // 10
+static const uint64_t SH_FLD_RESERVED2_15 = 15602; // 4
+static const uint64_t SH_FLD_RESERVED2_15_LEN = 15603; // 4
+static const uint64_t SH_FLD_RESERVED2_LEN = 15604; // 54
+static const uint64_t SH_FLD_RESERVED3 = 15605; // 40
+static const uint64_t SH_FLD_RESERVED31 = 15606; // 8
+static const uint64_t SH_FLD_RESERVED36_47 = 15607; // 4
+static const uint64_t SH_FLD_RESERVED36_47_LEN = 15608; // 4
+static const uint64_t SH_FLD_RESERVED3_LEN = 15609; // 24
+static const uint64_t SH_FLD_RESERVED4 = 15610; // 18
+static const uint64_t SH_FLD_RESERVED4_LEN = 15611; // 6
+static const uint64_t SH_FLD_RESERVED52_55 = 15612; // 4
+static const uint64_t SH_FLD_RESERVED52_55_LEN = 15613; // 4
+static const uint64_t SH_FLD_RESERVED57_63 = 15614; // 4
+static const uint64_t SH_FLD_RESERVED57_63_LEN = 15615; // 4
+static const uint64_t SH_FLD_RESERVED6 = 15616; // 1
+static const uint64_t SH_FLD_RESERVED63 = 15617; // 4
+static const uint64_t SH_FLD_RESERVED8_9 = 15618; // 8
+static const uint64_t SH_FLD_RESERVED8_9_LEN = 15619; // 8
+static const uint64_t SH_FLD_RESERVED9 = 15620; // 16
+static const uint64_t SH_FLD_RESERVED_0 = 15621; // 6
+static const uint64_t SH_FLD_RESERVED_00 = 15622; // 1
+static const uint64_t SH_FLD_RESERVED_02 = 15623; // 1
+static const uint64_t SH_FLD_RESERVED_03 = 15624; // 1
+static const uint64_t SH_FLD_RESERVED_0_1 = 15625; // 17
+static const uint64_t SH_FLD_RESERVED_0_15 = 15626; // 1
+static const uint64_t SH_FLD_RESERVED_0_15_LEN = 15627; // 1
+static const uint64_t SH_FLD_RESERVED_0_17 = 15628; // 2
+static const uint64_t SH_FLD_RESERVED_0_17_LEN = 15629; // 2
+static const uint64_t SH_FLD_RESERVED_0_19 = 15630; // 6
+static const uint64_t SH_FLD_RESERVED_0_19_LEN = 15631; // 6
+static const uint64_t SH_FLD_RESERVED_0_1_LEN = 15632; // 17
+static const uint64_t SH_FLD_RESERVED_0_20 = 15633; // 5
+static const uint64_t SH_FLD_RESERVED_0_20_LEN = 15634; // 5
+static const uint64_t SH_FLD_RESERVED_0_25 = 15635; // 1
+static const uint64_t SH_FLD_RESERVED_0_25_LEN = 15636; // 1
+static const uint64_t SH_FLD_RESERVED_0_29 = 15637; // 1
+static const uint64_t SH_FLD_RESERVED_0_29_LEN = 15638; // 1
+static const uint64_t SH_FLD_RESERVED_0_3 = 15639; // 1
+static const uint64_t SH_FLD_RESERVED_0_31 = 15640; // 2
+static const uint64_t SH_FLD_RESERVED_0_31_LEN = 15641; // 2
+static const uint64_t SH_FLD_RESERVED_0_32 = 15642; // 1
+static const uint64_t SH_FLD_RESERVED_0_32_LEN = 15643; // 1
+static const uint64_t SH_FLD_RESERVED_0_3_LEN = 15644; // 1
+static const uint64_t SH_FLD_RESERVED_0_7 = 15645; // 24
+static const uint64_t SH_FLD_RESERVED_0_7_LEN = 15646; // 24
+static const uint64_t SH_FLD_RESERVED_1 = 15647; // 13
+static const uint64_t SH_FLD_RESERVED_10 = 15648; // 1
+static const uint64_t SH_FLD_RESERVED_10_11 = 15649; // 31
+static const uint64_t SH_FLD_RESERVED_10_11_LEN = 15650; // 31
+static const uint64_t SH_FLD_RESERVED_10_LEN = 15651; // 1
+static const uint64_t SH_FLD_RESERVED_11 = 15652; // 2
+static const uint64_t SH_FLD_RESERVED_11A = 15653; // 43
+static const uint64_t SH_FLD_RESERVED_11_12 = 15654; // 4
+static const uint64_t SH_FLD_RESERVED_11_12_LEN = 15655; // 4
+static const uint64_t SH_FLD_RESERVED_11_14 = 15656; // 4
+static const uint64_t SH_FLD_RESERVED_11_14_LEN = 15657; // 4
+static const uint64_t SH_FLD_RESERVED_11_15 = 15658; // 1
+static const uint64_t SH_FLD_RESERVED_11_15_LEN = 15659; // 1
+static const uint64_t SH_FLD_RESERVED_11_LEN = 15660; // 1
+static const uint64_t SH_FLD_RESERVED_12 = 15661; // 3
+static const uint64_t SH_FLD_RESERVED_12_13 = 15662; // 9
+static const uint64_t SH_FLD_RESERVED_12_13_LEN = 15663; // 9
+static const uint64_t SH_FLD_RESERVED_12_15 = 15664; // 25
+static const uint64_t SH_FLD_RESERVED_12_15_LEN = 15665; // 25
+static const uint64_t SH_FLD_RESERVED_12_16 = 15666; // 1
+static const uint64_t SH_FLD_RESERVED_12_16_LEN = 15667; // 1
+static const uint64_t SH_FLD_RESERVED_12_23 = 15668; // 1
+static const uint64_t SH_FLD_RESERVED_12_23_LEN = 15669; // 1
+static const uint64_t SH_FLD_RESERVED_13 = 15670; // 2
+static const uint64_t SH_FLD_RESERVED_13_15 = 15671; // 12
+static const uint64_t SH_FLD_RESERVED_13_15_LEN = 15672; // 12
+static const uint64_t SH_FLD_RESERVED_13_31 = 15673; // 2
+static const uint64_t SH_FLD_RESERVED_13_31_LEN = 15674; // 2
+static const uint64_t SH_FLD_RESERVED_13_34 = 15675; // 2
+static const uint64_t SH_FLD_RESERVED_13_34_LEN = 15676; // 2
+static const uint64_t SH_FLD_RESERVED_13_LEN = 15677; // 1
+static const uint64_t SH_FLD_RESERVED_14 = 15678; // 1
+static const uint64_t SH_FLD_RESERVED_14C = 15679; // 43
+static const uint64_t SH_FLD_RESERVED_14_LEN = 15680; // 1
+static const uint64_t SH_FLD_RESERVED_15 = 15681; // 10
+static const uint64_t SH_FLD_RESERVED_15C = 15682; // 43
+static const uint64_t SH_FLD_RESERVED_16 = 15683; // 8
+static const uint64_t SH_FLD_RESERVED_16_17 = 15684; // 4
+static const uint64_t SH_FLD_RESERVED_16_17_LEN = 15685; // 4
+static const uint64_t SH_FLD_RESERVED_16_18 = 15686; // 30
+static const uint64_t SH_FLD_RESERVED_16_18_LEN = 15687; // 30
+static const uint64_t SH_FLD_RESERVED_16_26 = 15688; // 1
+static const uint64_t SH_FLD_RESERVED_16_26_LEN = 15689; // 1
+static const uint64_t SH_FLD_RESERVED_16_27 = 15690; // 1
+static const uint64_t SH_FLD_RESERVED_16_27_LEN = 15691; // 1
+static const uint64_t SH_FLD_RESERVED_16_LEN = 15692; // 1
+static const uint64_t SH_FLD_RESERVED_17 = 15693; // 3
+static const uint64_t SH_FLD_RESERVED_17_19 = 15694; // 6
+static const uint64_t SH_FLD_RESERVED_17_19_LEN = 15695; // 6
+static const uint64_t SH_FLD_RESERVED_17_LEN = 15696; // 1
+static const uint64_t SH_FLD_RESERVED_18 = 15697; // 1
+static const uint64_t SH_FLD_RESERVED_18A = 15698; // 43
+static const uint64_t SH_FLD_RESERVED_18_19 = 15699; // 9
+static const uint64_t SH_FLD_RESERVED_18_19_LEN = 15700; // 9
+static const uint64_t SH_FLD_RESERVED_18_23 = 15701; // 10
+static const uint64_t SH_FLD_RESERVED_18_23_LEN = 15702; // 10
+static const uint64_t SH_FLD_RESERVED_18_29 = 15703; // 12
+static const uint64_t SH_FLD_RESERVED_18_29_LEN = 15704; // 12
+static const uint64_t SH_FLD_RESERVED_18_31 = 15705; // 2
+static const uint64_t SH_FLD_RESERVED_18_31_LEN = 15706; // 2
+static const uint64_t SH_FLD_RESERVED_18_LEN = 15707; // 1
+static const uint64_t SH_FLD_RESERVED_19 = 15708; // 2
+static const uint64_t SH_FLD_RESERVED_19A = 15709; // 43
+static const uint64_t SH_FLD_RESERVED_1_12 = 15710; // 4
+static const uint64_t SH_FLD_RESERVED_1_12_LEN = 15711; // 4
+static const uint64_t SH_FLD_RESERVED_1_2 = 15712; // 55
+static const uint64_t SH_FLD_RESERVED_1_2_LEN = 15713; // 55
+static const uint64_t SH_FLD_RESERVED_1_3 = 15714; // 1
+static const uint64_t SH_FLD_RESERVED_1_3_LEN = 15715; // 1
+static const uint64_t SH_FLD_RESERVED_1_5 = 15716; // 1
+static const uint64_t SH_FLD_RESERVED_1_5_LEN = 15717; // 1
+static const uint64_t SH_FLD_RESERVED_1_7 = 15718; // 3
+static const uint64_t SH_FLD_RESERVED_1_7_LEN = 15719; // 3
+static const uint64_t SH_FLD_RESERVED_2 = 15720; // 3
+static const uint64_t SH_FLD_RESERVED_20 = 15721; // 5
+static const uint64_t SH_FLD_RESERVED_20_21 = 15722; // 1
+static const uint64_t SH_FLD_RESERVED_20_21_LEN = 15723; // 1
+static const uint64_t SH_FLD_RESERVED_20_31 = 15724; // 1
+static const uint64_t SH_FLD_RESERVED_20_31_LEN = 15725; // 1
+static const uint64_t SH_FLD_RESERVED_20_LEN = 15726; // 1
+static const uint64_t SH_FLD_RESERVED_21 = 15727; // 8
+static const uint64_t SH_FLD_RESERVED_21_31 = 15728; // 1
+static const uint64_t SH_FLD_RESERVED_21_31_LEN = 15729; // 1
+static const uint64_t SH_FLD_RESERVED_22C = 15730; // 43
+static const uint64_t SH_FLD_RESERVED_22_31 = 15731; // 1
+static const uint64_t SH_FLD_RESERVED_22_31_LEN = 15732; // 1
+static const uint64_t SH_FLD_RESERVED_23 = 15733; // 4
+static const uint64_t SH_FLD_RESERVED_23C = 15734; // 43
+static const uint64_t SH_FLD_RESERVED_23_26 = 15735; // 8
+static const uint64_t SH_FLD_RESERVED_23_26_LEN = 15736; // 8
+static const uint64_t SH_FLD_RESERVED_23_63 = 15737; // 2
+static const uint64_t SH_FLD_RESERVED_23_63_LEN = 15738; // 2
+static const uint64_t SH_FLD_RESERVED_24 = 15739; // 5
+static const uint64_t SH_FLD_RESERVED_24_25 = 15740; // 7
+static const uint64_t SH_FLD_RESERVED_24_25_LEN = 15741; // 7
+static const uint64_t SH_FLD_RESERVED_24_26 = 15742; // 3
+static const uint64_t SH_FLD_RESERVED_24_26_LEN = 15743; // 3
+static const uint64_t SH_FLD_RESERVED_24_29 = 15744; // 1
+static const uint64_t SH_FLD_RESERVED_24_29_LEN = 15745; // 1
+static const uint64_t SH_FLD_RESERVED_24_31 = 15746; // 1
+static const uint64_t SH_FLD_RESERVED_24_31_LEN = 15747; // 1
+static const uint64_t SH_FLD_RESERVED_24_LEN = 15748; // 1
+static const uint64_t SH_FLD_RESERVED_25 = 15749; // 12
+static const uint64_t SH_FLD_RESERVED_25_26 = 15750; // 3
+static const uint64_t SH_FLD_RESERVED_25_26_LEN = 15751; // 3
+static const uint64_t SH_FLD_RESERVED_25_33 = 15752; // 8
+static const uint64_t SH_FLD_RESERVED_25_33_LEN = 15753; // 8
+static const uint64_t SH_FLD_RESERVED_26 = 15754; // 8
+static const uint64_t SH_FLD_RESERVED_26_49 = 15755; // 2
+static const uint64_t SH_FLD_RESERVED_26_49_LEN = 15756; // 2
+static const uint64_t SH_FLD_RESERVED_28 = 15757; // 5
+static const uint64_t SH_FLD_RESERVED_28_31 = 15758; // 64
+static const uint64_t SH_FLD_RESERVED_28_31_LEN = 15759; // 64
+static const uint64_t SH_FLD_RESERVED_28_LEN = 15760; // 2
+static const uint64_t SH_FLD_RESERVED_29_30 = 15761; // 8
+static const uint64_t SH_FLD_RESERVED_29_30_LEN = 15762; // 8
+static const uint64_t SH_FLD_RESERVED_29_31 = 15763; // 6
+static const uint64_t SH_FLD_RESERVED_29_31_LEN = 15764; // 6
+static const uint64_t SH_FLD_RESERVED_2E = 15765; // 43
+static const uint64_t SH_FLD_RESERVED_2_3 = 15766; // 4
+static const uint64_t SH_FLD_RESERVED_2_3_LEN = 15767; // 4
+static const uint64_t SH_FLD_RESERVED_2_9 = 15768; // 25
+static const uint64_t SH_FLD_RESERVED_2_9_LEN = 15769; // 25
+static const uint64_t SH_FLD_RESERVED_3 = 15770; // 9
+static const uint64_t SH_FLD_RESERVED_30 = 15771; // 1
+static const uint64_t SH_FLD_RESERVED_30C = 15772; // 43
+static const uint64_t SH_FLD_RESERVED_30_31 = 15773; // 13
+static const uint64_t SH_FLD_RESERVED_30_31_LEN = 15774; // 13
+static const uint64_t SH_FLD_RESERVED_31 = 15775; // 11
+static const uint64_t SH_FLD_RESERVED_31C = 15776; // 43
+static const uint64_t SH_FLD_RESERVED_31_LEN = 15777; // 2
+static const uint64_t SH_FLD_RESERVED_32 = 15778; // 28
+static const uint64_t SH_FLD_RESERVED_32_33 = 15779; // 6
+static const uint64_t SH_FLD_RESERVED_32_33_LEN = 15780; // 6
+static const uint64_t SH_FLD_RESERVED_32_34 = 15781; // 8
+static const uint64_t SH_FLD_RESERVED_32_34_LEN = 15782; // 8
+static const uint64_t SH_FLD_RESERVED_32_35 = 15783; // 3
+static const uint64_t SH_FLD_RESERVED_32_35_LEN = 15784; // 3
+static const uint64_t SH_FLD_RESERVED_32_39 = 15785; // 3
+static const uint64_t SH_FLD_RESERVED_32_39_LEN = 15786; // 3
+static const uint64_t SH_FLD_RESERVED_32_40 = 15787; // 10
+static const uint64_t SH_FLD_RESERVED_32_40_LEN = 15788; // 10
+static const uint64_t SH_FLD_RESERVED_32_44 = 15789; // 3
+static const uint64_t SH_FLD_RESERVED_32_44_LEN = 15790; // 3
+static const uint64_t SH_FLD_RESERVED_32_63 = 15791; // 8
+static const uint64_t SH_FLD_RESERVED_32_63_LEN = 15792; // 8
+static const uint64_t SH_FLD_RESERVED_33A = 15793; // 43
+static const uint64_t SH_FLD_RESERVED_33_39 = 15794; // 1
+static const uint64_t SH_FLD_RESERVED_33_39_LEN = 15795; // 1
+static const uint64_t SH_FLD_RESERVED_33_43 = 15796; // 1
+static const uint64_t SH_FLD_RESERVED_33_43_LEN = 15797; // 1
+static const uint64_t SH_FLD_RESERVED_33_63 = 15798; // 1
+static const uint64_t SH_FLD_RESERVED_33_63_LEN = 15799; // 1
+static const uint64_t SH_FLD_RESERVED_34 = 15800; // 1
+static const uint64_t SH_FLD_RESERVED_34A = 15801; // 43
+static const uint64_t SH_FLD_RESERVED_35 = 15802; // 1
+static const uint64_t SH_FLD_RESERVED_35A = 15803; // 43
+static const uint64_t SH_FLD_RESERVED_36_37 = 15804; // 8
+static const uint64_t SH_FLD_RESERVED_36_37_LEN = 15805; // 8
+static const uint64_t SH_FLD_RESERVED_36_39 = 15806; // 1
+static const uint64_t SH_FLD_RESERVED_36_39_LEN = 15807; // 1
+static const uint64_t SH_FLD_RESERVED_37 = 15808; // 1
+static const uint64_t SH_FLD_RESERVED_37_45 = 15809; // 1
+static const uint64_t SH_FLD_RESERVED_37_45_LEN = 15810; // 1
+static const uint64_t SH_FLD_RESERVED_37_56 = 15811; // 8
+static const uint64_t SH_FLD_RESERVED_37_56_LEN = 15812; // 8
+static const uint64_t SH_FLD_RESERVED_38 = 15813; // 1
+static const uint64_t SH_FLD_RESERVED_38A = 15814; // 43
+static const uint64_t SH_FLD_RESERVED_38_39 = 15815; // 24
+static const uint64_t SH_FLD_RESERVED_38_39_LEN = 15816; // 24
+static const uint64_t SH_FLD_RESERVED_38_41 = 15817; // 1
+static const uint64_t SH_FLD_RESERVED_38_41_LEN = 15818; // 1
+static const uint64_t SH_FLD_RESERVED_38_63 = 15819; // 2
+static const uint64_t SH_FLD_RESERVED_38_63_LEN = 15820; // 2
+static const uint64_t SH_FLD_RESERVED_39 = 15821; // 12
+static const uint64_t SH_FLD_RESERVED_39A = 15822; // 43
+static const uint64_t SH_FLD_RESERVED_39_47 = 15823; // 64
+static const uint64_t SH_FLD_RESERVED_39_47_LEN = 15824; // 64
+static const uint64_t SH_FLD_RESERVED_39_63 = 15825; // 4
+static const uint64_t SH_FLD_RESERVED_39_63_LEN = 15826; // 4
+static const uint64_t SH_FLD_RESERVED_3E = 15827; // 43
+static const uint64_t SH_FLD_RESERVED_3_9 = 15828; // 1
+static const uint64_t SH_FLD_RESERVED_3_9_LEN = 15829; // 1
+static const uint64_t SH_FLD_RESERVED_4 = 15830; // 10
+static const uint64_t SH_FLD_RESERVED_40 = 15831; // 35
+static const uint64_t SH_FLD_RESERVED_40_41 = 15832; // 9
+static const uint64_t SH_FLD_RESERVED_40_41_LEN = 15833; // 9
+static const uint64_t SH_FLD_RESERVED_40_42 = 15834; // 1
+static const uint64_t SH_FLD_RESERVED_40_42_LEN = 15835; // 1
+static const uint64_t SH_FLD_RESERVED_40_47 = 15836; // 2
+static const uint64_t SH_FLD_RESERVED_40_47_LEN = 15837; // 2
+static const uint64_t SH_FLD_RESERVED_41 = 15838; // 2
+static const uint64_t SH_FLD_RESERVED_41_42 = 15839; // 10
+static const uint64_t SH_FLD_RESERVED_41_42_LEN = 15840; // 10
+static const uint64_t SH_FLD_RESERVED_41_43 = 15841; // 2
+static const uint64_t SH_FLD_RESERVED_41_43_LEN = 15842; // 2
+static const uint64_t SH_FLD_RESERVED_41_63 = 15843; // 8
+static const uint64_t SH_FLD_RESERVED_41_63_LEN = 15844; // 8
+static const uint64_t SH_FLD_RESERVED_42 = 15845; // 2
+static const uint64_t SH_FLD_RESERVED_42A = 15846; // 43
+static const uint64_t SH_FLD_RESERVED_42C = 15847; // 43
+static const uint64_t SH_FLD_RESERVED_42_43 = 15848; // 12
+static const uint64_t SH_FLD_RESERVED_42_43_LEN = 15849; // 12
+static const uint64_t SH_FLD_RESERVED_42_47 = 15850; // 8
+static const uint64_t SH_FLD_RESERVED_42_47_LEN = 15851; // 8
+static const uint64_t SH_FLD_RESERVED_43 = 15852; // 2
+static const uint64_t SH_FLD_RESERVED_43A = 15853; // 43
+static const uint64_t SH_FLD_RESERVED_43C = 15854; // 43
+static const uint64_t SH_FLD_RESERVED_43_44 = 15855; // 2
+static const uint64_t SH_FLD_RESERVED_43_44_LEN = 15856; // 2
+static const uint64_t SH_FLD_RESERVED_44 = 15857; // 1
+static const uint64_t SH_FLD_RESERVED_44_46 = 15858; // 1
+static const uint64_t SH_FLD_RESERVED_44_46_LEN = 15859; // 1
+static const uint64_t SH_FLD_RESERVED_44_47 = 15860; // 1
+static const uint64_t SH_FLD_RESERVED_44_47_LEN = 15861; // 1
+static const uint64_t SH_FLD_RESERVED_45 = 15862; // 1
+static const uint64_t SH_FLD_RESERVED_46 = 15863; // 1
+static const uint64_t SH_FLD_RESERVED_47 = 15864; // 2
+static const uint64_t SH_FLD_RESERVED_47_48 = 15865; // 2
+static const uint64_t SH_FLD_RESERVED_47_48_LEN = 15866; // 2
+static const uint64_t SH_FLD_RESERVED_47_51 = 15867; // 1
+static const uint64_t SH_FLD_RESERVED_47_51_LEN = 15868; // 1
+static const uint64_t SH_FLD_RESERVED_48 = 15869; // 27
+static const uint64_t SH_FLD_RESERVED_48_49 = 15870; // 3
+static const uint64_t SH_FLD_RESERVED_48_49_LEN = 15871; // 3
+static const uint64_t SH_FLD_RESERVED_48_50 = 15872; // 2
+static const uint64_t SH_FLD_RESERVED_48_50_LEN = 15873; // 2
+static const uint64_t SH_FLD_RESERVED_48_63 = 15874; // 10
+static const uint64_t SH_FLD_RESERVED_48_63_LEN = 15875; // 10
+static const uint64_t SH_FLD_RESERVED_49_63 = 15876; // 8
+static const uint64_t SH_FLD_RESERVED_49_63_LEN = 15877; // 8
+static const uint64_t SH_FLD_RESERVED_4_5 = 15878; // 1
+static const uint64_t SH_FLD_RESERVED_4_5_LEN = 15879; // 1
+static const uint64_t SH_FLD_RESERVED_4_7 = 15880; // 32
+static const uint64_t SH_FLD_RESERVED_4_7_LEN = 15881; // 32
+static const uint64_t SH_FLD_RESERVED_4_LEN = 15882; // 1
+static const uint64_t SH_FLD_RESERVED_5 = 15883; // 2
+static const uint64_t SH_FLD_RESERVED_50 = 15884; // 4
+static const uint64_t SH_FLD_RESERVED_50_51 = 15885; // 3
+static const uint64_t SH_FLD_RESERVED_50_51_LEN = 15886; // 3
+static const uint64_t SH_FLD_RESERVED_50_63 = 15887; // 1
+static const uint64_t SH_FLD_RESERVED_50_63_LEN = 15888; // 1
+static const uint64_t SH_FLD_RESERVED_51 = 15889; // 16
+static const uint64_t SH_FLD_RESERVED_51_63 = 15890; // 9
+static const uint64_t SH_FLD_RESERVED_51_63_LEN = 15891; // 9
+static const uint64_t SH_FLD_RESERVED_52 = 15892; // 38
+static const uint64_t SH_FLD_RESERVED_52_55 = 15893; // 64
+static const uint64_t SH_FLD_RESERVED_52_55_LEN = 15894; // 64
+static const uint64_t SH_FLD_RESERVED_52_56 = 15895; // 8
+static const uint64_t SH_FLD_RESERVED_52_56_LEN = 15896; // 8
+static const uint64_t SH_FLD_RESERVED_53_54 = 15897; // 8
+static const uint64_t SH_FLD_RESERVED_53_54_LEN = 15898; // 8
+static const uint64_t SH_FLD_RESERVED_53_58 = 15899; // 2
+static const uint64_t SH_FLD_RESERVED_53_58_LEN = 15900; // 2
+static const uint64_t SH_FLD_RESERVED_53_63 = 15901; // 1
+static const uint64_t SH_FLD_RESERVED_53_63_LEN = 15902; // 1
+static const uint64_t SH_FLD_RESERVED_54_63 = 15903; // 8
+static const uint64_t SH_FLD_RESERVED_54_63_LEN = 15904; // 8
+static const uint64_t SH_FLD_RESERVED_55_63 = 15905; // 8
+static const uint64_t SH_FLD_RESERVED_55_63_LEN = 15906; // 8
+static const uint64_t SH_FLD_RESERVED_56 = 15907; // 32
+static const uint64_t SH_FLD_RESERVED_56_57 = 15908; // 2
+static const uint64_t SH_FLD_RESERVED_56_57_LEN = 15909; // 2
+static const uint64_t SH_FLD_RESERVED_56_58 = 15910; // 5
+static const uint64_t SH_FLD_RESERVED_56_58_LEN = 15911; // 5
+static const uint64_t SH_FLD_RESERVED_56_59 = 15912; // 1
+static const uint64_t SH_FLD_RESERVED_56_59_LEN = 15913; // 1
+static const uint64_t SH_FLD_RESERVED_56_63 = 15914; // 18
+static const uint64_t SH_FLD_RESERVED_56_63_LEN = 15915; // 18
+static const uint64_t SH_FLD_RESERVED_57 = 15916; // 24
+static const uint64_t SH_FLD_RESERVED_57_58 = 15917; // 2
+static const uint64_t SH_FLD_RESERVED_57_58_LEN = 15918; // 2
+static const uint64_t SH_FLD_RESERVED_57_59 = 15919; // 7
+static const uint64_t SH_FLD_RESERVED_57_59_LEN = 15920; // 7
+static const uint64_t SH_FLD_RESERVED_58 = 15921; // 1
+static const uint64_t SH_FLD_RESERVED_58_59 = 15922; // 1
+static const uint64_t SH_FLD_RESERVED_58_59_LEN = 15923; // 1
+static const uint64_t SH_FLD_RESERVED_58_63 = 15924; // 8
+static const uint64_t SH_FLD_RESERVED_58_63_LEN = 15925; // 8
+static const uint64_t SH_FLD_RESERVED_59 = 15926; // 1
+static const uint64_t SH_FLD_RESERVED_59_63 = 15927; // 8
+static const uint64_t SH_FLD_RESERVED_59_63_LEN = 15928; // 8
+static const uint64_t SH_FLD_RESERVED_5_15 = 15929; // 1
+static const uint64_t SH_FLD_RESERVED_5_15_LEN = 15930; // 1
+static const uint64_t SH_FLD_RESERVED_5_7 = 15931; // 1
+static const uint64_t SH_FLD_RESERVED_5_7_LEN = 15932; // 1
+static const uint64_t SH_FLD_RESERVED_5_LEN = 15933; // 1
+static const uint64_t SH_FLD_RESERVED_6 = 15934; // 2
+static const uint64_t SH_FLD_RESERVED_60 = 15935; // 24
+static const uint64_t SH_FLD_RESERVED_60_61 = 15936; // 8
+static const uint64_t SH_FLD_RESERVED_60_61_LEN = 15937; // 8
+static const uint64_t SH_FLD_RESERVED_60_63 = 15938; // 9
+static const uint64_t SH_FLD_RESERVED_60_63_LEN = 15939; // 9
+static const uint64_t SH_FLD_RESERVED_61 = 15940; // 24
+static const uint64_t SH_FLD_RESERVED_61_63 = 15941; // 18
+static const uint64_t SH_FLD_RESERVED_61_63_LEN = 15942; // 18
+static const uint64_t SH_FLD_RESERVED_62 = 15943; // 1
+static const uint64_t SH_FLD_RESERVED_62_63 = 15944; // 16
+static const uint64_t SH_FLD_RESERVED_62_63_LEN = 15945; // 16
+static const uint64_t SH_FLD_RESERVED_63 = 15946; // 20
+static const uint64_t SH_FLD_RESERVED_6C = 15947; // 43
+static const uint64_t SH_FLD_RESERVED_6E = 15948; // 43
+static const uint64_t SH_FLD_RESERVED_6_14 = 15949; // 2
+static const uint64_t SH_FLD_RESERVED_6_14_LEN = 15950; // 2
+static const uint64_t SH_FLD_RESERVED_6_7 = 15951; // 27
+static const uint64_t SH_FLD_RESERVED_6_7_LEN = 15952; // 27
+static const uint64_t SH_FLD_RESERVED_6_8 = 15953; // 12
+static const uint64_t SH_FLD_RESERVED_6_8_LEN = 15954; // 12
+static const uint64_t SH_FLD_RESERVED_7 = 15955; // 2
+static const uint64_t SH_FLD_RESERVED_7C = 15956; // 43
+static const uint64_t SH_FLD_RESERVED_7_9 = 15957; // 8
+static const uint64_t SH_FLD_RESERVED_7_9_LEN = 15958; // 8
+static const uint64_t SH_FLD_RESERVED_7_LEN = 15959; // 1
+static const uint64_t SH_FLD_RESERVED_8 = 15960; // 6
+static const uint64_t SH_FLD_RESERVED_8_10 = 15961; // 39
+static const uint64_t SH_FLD_RESERVED_8_10_LEN = 15962; // 39
+static const uint64_t SH_FLD_RESERVED_8_9 = 15963; // 6
+static const uint64_t SH_FLD_RESERVED_8_9_LEN = 15964; // 6
+static const uint64_t SH_FLD_RESERVED_8_LEN = 15965; // 1
+static const uint64_t SH_FLD_RESERVED_9 = 15966; // 27
+static const uint64_t SH_FLD_RESERVED_9_15 = 15967; // 2
+static const uint64_t SH_FLD_RESERVED_9_15_LEN = 15968; // 2
+static const uint64_t SH_FLD_RESERVED_9_26 = 15969; // 1
+static const uint64_t SH_FLD_RESERVED_9_26_LEN = 15970; // 1
+static const uint64_t SH_FLD_RESERVED_9_27 = 15971; // 1
+static const uint64_t SH_FLD_RESERVED_9_27_LEN = 15972; // 1
+static const uint64_t SH_FLD_RESERVED_FOR_ADDRESS = 15973; // 1
+static const uint64_t SH_FLD_RESERVED_FOR_ADDRESS_LEN = 15974; // 1
+static const uint64_t SH_FLD_RESERVED_FOR_CONFIGS = 15975; // 1
+static const uint64_t SH_FLD_RESERVED_FOR_CONFIGS_LEN = 15976; // 1
+static const uint64_t SH_FLD_RESERVED_FOR_ERRS = 15977; // 1
+static const uint64_t SH_FLD_RESERVED_FOR_ERRS_LEN = 15978; // 1
+static const uint64_t SH_FLD_RESERVED_ID_55C = 15979; // 43
+static const uint64_t SH_FLD_RESERVED_ID_61C = 15980; // 43
+static const uint64_t SH_FLD_RESERVED_ID_62C = 15981; // 43
+static const uint64_t SH_FLD_RESERVED_ID_63C = 15982; // 43
+static const uint64_t SH_FLD_RESERVED_LAST_LT = 15983; // 43
+static const uint64_t SH_FLD_RESERVED_LEN = 15984; // 76
+static const uint64_t SH_FLD_RESERVED_LT = 15985; // 43
+static const uint64_t SH_FLD_RESERVED_LT_LEN = 15986; // 43
+static const uint64_t SH_FLD_RESERVED_RING_LOCKING = 15987; // 43
+static const uint64_t SH_FLD_RESERVED_TEST_CONTROL_35C = 15988; // 43
+static const uint64_t SH_FLD_RESERVED_TEST_CONTROL_36C = 15989; // 43
+static const uint64_t SH_FLD_RESERVED_TEST_CONTROL_37C = 15990; // 43
+static const uint64_t SH_FLD_RESERVED_TEST_CONTROL_38C = 15991; // 43
+static const uint64_t SH_FLD_RESERVED_TEST_CONTROL_39C = 15992; // 43
+static const uint64_t SH_FLD_RESERVE_11 = 15993; // 2
+static const uint64_t SH_FLD_RESERVE_39_52 = 15994; // 2
+static const uint64_t SH_FLD_RESERVE_39_52_LEN = 15995; // 2
+static const uint64_t SH_FLD_RESERVE_5_15 = 15996; // 2
+static const uint64_t SH_FLD_RESERVE_5_15_LEN = 15997; // 2
+static const uint64_t SH_FLD_RESET = 15998; // 27
+static const uint64_t SH_FLD_RESETMODE = 15999; // 9
+static const uint64_t SH_FLD_RESET_0 = 16000; // 8
+static const uint64_t SH_FLD_RESET_0_7 = 16001; // 1
+static const uint64_t SH_FLD_RESET_0_7_LEN = 16002; // 1
+static const uint64_t SH_FLD_RESET_1 = 16003; // 8
+static const uint64_t SH_FLD_RESET_C2TIMER_ON_C1 = 16004; // 86
+static const uint64_t SH_FLD_RESET_C3_ON_C0 = 16005; // 86
+static const uint64_t SH_FLD_RESET_C3_SELECT = 16006; // 86
+static const uint64_t SH_FLD_RESET_C3_SELECT_LEN = 16007; // 86
+static const uint64_t SH_FLD_RESET_EP = 16008; // 43
+static const uint64_t SH_FLD_RESET_ERROR_LOGS = 16009; // 2
+static const uint64_t SH_FLD_RESET_ERR_RPT = 16010; // 8
+static const uint64_t SH_FLD_RESET_IMPRECISE_QERR = 16011; // 12
+static const uint64_t SH_FLD_RESET_KEEPER = 16012; // 38
+static const uint64_t SH_FLD_RESET_LEN = 16013; // 2
+static const uint64_t SH_FLD_RESET_MODE = 16014; // 5
+static const uint64_t SH_FLD_RESET_ON_PARITY = 16015; // 1
+static const uint64_t SH_FLD_RESET_PIB = 16016; // 1
+static const uint64_t SH_FLD_RESET_RECOVER = 16017; // 8
+static const uint64_t SH_FLD_RESET_TOD_STATE = 16018; // 1
+static const uint64_t SH_FLD_RESET_TRAP_CNFG = 16019; // 2
+static const uint64_t SH_FLD_RESET_TRIG_SEL = 16020; // 43
+static const uint64_t SH_FLD_RESET_TRIG_SEL_LEN = 16021; // 43
+static const uint64_t SH_FLD_RESID_FE_LEN_0 = 16022; // 2
+static const uint64_t SH_FLD_RESID_FE_LEN_0_LEN = 16023; // 2
+static const uint64_t SH_FLD_RESID_FE_LEN_1 = 16024; // 1
+static const uint64_t SH_FLD_RESID_FE_LEN_1_LEN = 16025; // 1
+static const uint64_t SH_FLD_RESID_FE_LEN_2 = 16026; // 1
+static const uint64_t SH_FLD_RESID_FE_LEN_2_LEN = 16027; // 1
+static const uint64_t SH_FLD_RESID_FE_LEN_3 = 16028; // 1
+static const uint64_t SH_FLD_RESID_FE_LEN_3_LEN = 16029; // 1
+static const uint64_t SH_FLD_RESPONSE = 16030; // 1
+static const uint64_t SH_FLD_RESP_PKT_RCV = 16031; // 2
+static const uint64_t SH_FLD_RESSEL = 16032; // 4
+static const uint64_t SH_FLD_RESULT = 16033; // 1
+static const uint64_t SH_FLD_RESULT_AVAILABLE = 16034; // 2
+static const uint64_t SH_FLD_RESULT_LEN = 16035; // 1
+static const uint64_t SH_FLD_RESUME_FROM_PAUSE = 16036; // 2
+static const uint64_t SH_FLD_RETIRE = 16037; // 1
+static const uint64_t SH_FLD_RETRAIN_PERCAL_SW = 16038; // 8
+static const uint64_t SH_FLD_RETRY_LPC_LFSR_SELECT = 16039; // 4
+static const uint64_t SH_FLD_RETRY_LPC_LFSR_SELECT_LEN = 16040; // 4
+static const uint64_t SH_FLD_RETRY_VALUE = 16041; // 1
+static const uint64_t SH_FLD_RETRY_VALUE_LEN = 16042; // 1
+static const uint64_t SH_FLD_RETURNQ_ERR = 16043; // 4
+static const uint64_t SH_FLD_RETURN_GOOD_ON_COMP = 16044; // 24
+static const uint64_t SH_FLD_RG_CERR_BIT10 = 16045; // 1
+static const uint64_t SH_FLD_RG_CERR_BIT11 = 16046; // 1
+static const uint64_t SH_FLD_RG_CERR_BIT12 = 16047; // 1
+static const uint64_t SH_FLD_RG_CERR_BIT13 = 16048; // 1
+static const uint64_t SH_FLD_RG_CERR_BIT4 = 16049; // 1
+static const uint64_t SH_FLD_RG_CERR_BIT5 = 16050; // 1
+static const uint64_t SH_FLD_RG_CERR_BIT6 = 16051; // 1
+static const uint64_t SH_FLD_RG_CERR_BIT7 = 16052; // 1
+static const uint64_t SH_FLD_RG_CERR_BIT8 = 16053; // 1
+static const uint64_t SH_FLD_RG_CERR_BIT9 = 16054; // 1
+static const uint64_t SH_FLD_RG_CERR_RESET = 16055; // 1
+static const uint64_t SH_FLD_RG_CERR_UNUSED_BITS = 16056; // 1
+static const uint64_t SH_FLD_RG_CERR_UNUSED_BITS_LEN = 16057; // 1
+static const uint64_t SH_FLD_RG_ECC_CE_ERROR = 16058; // 2
+static const uint64_t SH_FLD_RG_ECC_SUE_ERROR = 16059; // 2
+static const uint64_t SH_FLD_RG_ECC_UE_ERROR = 16060; // 2
+static const uint64_t SH_FLD_RG_LOGIC_HW_ERROR = 16061; // 2
+static const uint64_t SH_FLD_RG_TRACE_GROUP_SEL_HI = 16062; // 1
+static const uint64_t SH_FLD_RG_TRACE_GROUP_SEL_HI_LEN = 16063; // 1
+static const uint64_t SH_FLD_RG_TRACE_GROUP_SEL_LO = 16064; // 1
+static const uint64_t SH_FLD_RG_TRACE_GROUP_SEL_LO_LEN = 16065; // 1
+static const uint64_t SH_FLD_RG_TRACE_INT_DATA_HI = 16066; // 1
+static const uint64_t SH_FLD_RG_TRACE_INT_DATA_LO = 16067; // 1
+static const uint64_t SH_FLD_RG_TRACE_INT_TRIG_01 = 16068; // 1
+static const uint64_t SH_FLD_RG_TRACE_INT_TRIG_23 = 16069; // 1
+static const uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_01 = 16070; // 1
+static const uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_01_LEN = 16071; // 1
+static const uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_23 = 16072; // 1
+static const uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_23_LEN = 16073; // 1
+static const uint64_t SH_FLD_RIC = 16074; // 8
+static const uint64_t SH_FLD_RIC_LEN = 16075; // 8
+static const uint64_t SH_FLD_RINGS = 16076; // 43
+static const uint64_t SH_FLD_RINGS_LEN = 16077; // 43
+static const uint64_t SH_FLD_RING_LOCKING = 16078; // 43
+static const uint64_t SH_FLD_RMA_BAR = 16079; // 1
+static const uint64_t SH_FLD_RMA_BAR_LEN = 16080; // 1
+static const uint64_t SH_FLD_RMA_BAR_MASK = 16081; // 1
+static const uint64_t SH_FLD_RMA_BAR_MASK_LEN = 16082; // 1
+static const uint64_t SH_FLD_RMT_FIRST_GRPSCAN_ENA = 16083; // 1
+static const uint64_t SH_FLD_RMW_BUF_THRESH = 16084; // 8
+static const uint64_t SH_FLD_RMW_BUF_THRESH_LEN = 16085; // 8
+static const uint64_t SH_FLD_RND_BACKOFF_ENABLE = 16086; // 2
+static const uint64_t SH_FLD_RNG0_BIST_FAIL = 16087; // 1
+static const uint64_t SH_FLD_RNG0_FAIL = 16088; // 1
+static const uint64_t SH_FLD_RNG0_INJ_CONTINOUS_ERROR = 16089; // 1
+static const uint64_t SH_FLD_RNG1_BIST_FAIL = 16090; // 1
+static const uint64_t SH_FLD_RNG1_FAIL = 16091; // 1
+static const uint64_t SH_FLD_RNG1_INJ_CONTINOUS_ERROR = 16092; // 1
+static const uint64_t SH_FLD_RNG_CNTRL_LOGIC_ERR = 16093; // 1
+static const uint64_t SH_FLD_RNG_FIRST_FAIL = 16094; // 1
+static const uint64_t SH_FLD_RNG_SECOND_FAIL = 16095; // 1
+static const uint64_t SH_FLD_RNG_WR_ENBL_REG_PERR_ERRHOLD = 16096; // 2
+static const uint64_t SH_FLD_RNW = 16097; // 15
+static const uint64_t SH_FLD_ROUTE_CHECKSTOP = 16098; // 2
+static const uint64_t SH_FLD_RPT = 16099; // 2
+static const uint64_t SH_FLD_RPT1 = 16100; // 1
+static const uint64_t SH_FLD_RPT1_LEN = 16101; // 1
+static const uint64_t SH_FLD_RPTHANG_SELECT = 16102; // 4
+static const uint64_t SH_FLD_RPTHANG_SELECT_LEN = 16103; // 4
+static const uint64_t SH_FLD_RPT_LEN = 16104; // 2
+static const uint64_t SH_FLD_RRDM_DLY = 16105; // 8
+static const uint64_t SH_FLD_RRDM_DLY_LEN = 16106; // 8
+static const uint64_t SH_FLD_RRN_BYPASS_ENABLE = 16107; // 1
+static const uint64_t SH_FLD_RRN_DATA = 16108; // 1
+static const uint64_t SH_FLD_RRN_DATA_LEN = 16109; // 1
+static const uint64_t SH_FLD_RROP_DLY = 16110; // 8
+static const uint64_t SH_FLD_RROP_DLY_LEN = 16111; // 8
+static const uint64_t SH_FLD_RRQ_CAPACITY_LIMIT = 16112; // 4
+static const uint64_t SH_FLD_RRQ_CAPACITY_LIMIT_LEN = 16113; // 4
+static const uint64_t SH_FLD_RRQ_HANG = 16114; // 8
+static const uint64_t SH_FLD_RRQ_PE = 16115; // 8
+static const uint64_t SH_FLD_RRSBG_DLY = 16116; // 8
+static const uint64_t SH_FLD_RRSBG_DLY_LEN = 16117; // 8
+static const uint64_t SH_FLD_RRSMDR_DLY = 16118; // 8
+static const uint64_t SH_FLD_RRSMDR_DLY_LEN = 16119; // 8
+static const uint64_t SH_FLD_RRSMSR_DLY = 16120; // 8
+static const uint64_t SH_FLD_RRSMSR_DLY_LEN = 16121; // 8
+static const uint64_t SH_FLD_RSB_BUS_LOGIC_ERROR = 16122; // 6
+static const uint64_t SH_FLD_RSB_DBG_FATAL_ERROR = 16123; // 6
+static const uint64_t SH_FLD_RSB_DBG_INF_ERROR = 16124; // 6
+static const uint64_t SH_FLD_RSB_ERR_FATAL_ERROR = 16125; // 6
+static const uint64_t SH_FLD_RSB_ERR_INF_ERROR = 16126; // 6
+static const uint64_t SH_FLD_RSB_FDA_FATAL_ERROR = 16127; // 6
+static const uint64_t SH_FLD_RSB_FDA_INF_ERROR = 16128; // 6
+static const uint64_t SH_FLD_RSB_FDB_FATAL_ERROR = 16129; // 6
+static const uint64_t SH_FLD_RSB_FDB_INF_ERROR = 16130; // 6
+static const uint64_t SH_FLD_RSB_REQUEST_ADDRESS_ERROR = 16131; // 6
+static const uint64_t SH_FLD_RSB_UVI_FATAL_ERROR = 16132; // 6
+static const uint64_t SH_FLD_RSB_UVI_INF_ERROR = 16133; // 6
+static const uint64_t SH_FLD_RSD_AT_MACRO = 16134; // 1
+static const uint64_t SH_FLD_RSD_AT_MACRO_LEN = 16135; // 1
+static const uint64_t SH_FLD_RSD_CRD_AT_MACRO = 16136; // 1
+static const uint64_t SH_FLD_RSD_CRD_AT_MACRO_LEN = 16137; // 1
+static const uint64_t SH_FLD_RSD_CRD_DMA_READ = 16138; // 1
+static const uint64_t SH_FLD_RSD_CRD_DMA_READ_LEN = 16139; // 1
+static const uint64_t SH_FLD_RSD_CRD_DMA_WRITE = 16140; // 1
+static const uint64_t SH_FLD_RSD_CRD_DMA_WRITE_LEN = 16141; // 1
+static const uint64_t SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD = 16142; // 1
+static const uint64_t SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD_LEN = 16143; // 1
+static const uint64_t SH_FLD_RSD_CRD_EQ_POST = 16144; // 1
+static const uint64_t SH_FLD_RSD_CRD_EQ_POST_LEN = 16145; // 1
+static const uint64_t SH_FLD_RSD_CRD_TRIG_FWD_1 = 16146; // 1
+static const uint64_t SH_FLD_RSD_CRD_TRIG_FWD_1_LEN = 16147; // 1
+static const uint64_t SH_FLD_RSD_CRD_TRIG_FWD_2 = 16148; // 1
+static const uint64_t SH_FLD_RSD_CRD_TRIG_FWD_2_LEN = 16149; // 1
+static const uint64_t SH_FLD_RSD_DMA_READ = 16150; // 1
+static const uint64_t SH_FLD_RSD_DMA_READ_LEN = 16151; // 1
+static const uint64_t SH_FLD_RSD_DMA_WRITE = 16152; // 1
+static const uint64_t SH_FLD_RSD_DMA_WRITE_LEN = 16153; // 1
+static const uint64_t SH_FLD_RSD_TCTXT_WRITE = 16154; // 1
+static const uint64_t SH_FLD_RSD_TCTXT_WRITE_LEN = 16155; // 1
+static const uint64_t SH_FLD_RSD_VPC_LD_RMT = 16156; // 1
+static const uint64_t SH_FLD_RSD_VPC_LD_RMT_LEN = 16157; // 1
+static const uint64_t SH_FLD_RSD_VPC_ST_RMT = 16158; // 1
+static const uint64_t SH_FLD_RSD_VPC_ST_RMT_LEN = 16159; // 1
+static const uint64_t SH_FLD_RSD_VPC_ST_RMT_VC = 16160; // 1
+static const uint64_t SH_FLD_RSD_VPC_ST_RMT_VC_LEN = 16161; // 1
+static const uint64_t SH_FLD_RSEL = 16162; // 10
+static const uint64_t SH_FLD_RSEL_LEN = 16163; // 10
+static const uint64_t SH_FLD_RSPOUT_CE_ESR = 16164; // 1
+static const uint64_t SH_FLD_RSPOUT_UE_ESR = 16165; // 1
+static const uint64_t SH_FLD_RSP_AE_ALWAYS = 16166; // 6
+static const uint64_t SH_FLD_RSP_CTL_CRED_SINGLE_ENA = 16167; // 6
+static const uint64_t SH_FLD_RSV17 = 16168; // 2
+static const uint64_t SH_FLD_RSV18 = 16169; // 2
+static const uint64_t SH_FLD_RSV19 = 16170; // 2
+static const uint64_t SH_FLD_RSV26 = 16171; // 2
+static const uint64_t SH_FLD_RSV27 = 16172; // 2
+static const uint64_t SH_FLD_RSV34 = 16173; // 2
+static const uint64_t SH_FLD_RSV35 = 16174; // 2
+static const uint64_t SH_FLD_RSV6 = 16175; // 2
+static const uint64_t SH_FLD_RSV7 = 16176; // 2
+static const uint64_t SH_FLD_RSVD = 16177; // 2
+static const uint64_t SH_FLD_RSVD0 = 16178; // 1
+static const uint64_t SH_FLD_RSVD0_LEN = 16179; // 1
+static const uint64_t SH_FLD_RSVD1 = 16180; // 1
+static const uint64_t SH_FLD_RSVD1_LEN = 16181; // 1
+static const uint64_t SH_FLD_RSVD_35_43 = 16182; // 8
+static const uint64_t SH_FLD_RSVD_35_43_LEN = 16183; // 8
+static const uint64_t SH_FLD_RSVD_LEN = 16184; // 1
+static const uint64_t SH_FLD_RTAGFLUSH_FAILED = 16185; // 2
+static const uint64_t SH_FLD_RTAG_PARITY = 16186; // 1
+static const uint64_t SH_FLD_RTAG_PERR = 16187; // 1
+static const uint64_t SH_FLD_RTIM_THOLD_FORCE = 16188; // 43
+static const uint64_t SH_FLD_RTT_WR0_NOM_VALUE = 16189; // 8
+static const uint64_t SH_FLD_RTT_WR0_NOM_VALUE_LEN = 16190; // 8
+static const uint64_t SH_FLD_RTT_WR1_NOM_VALUE = 16191; // 8
+static const uint64_t SH_FLD_RTT_WR1_NOM_VALUE_LEN = 16192; // 8
+static const uint64_t SH_FLD_RTT_WR2_NOM_VALUE = 16193; // 8
+static const uint64_t SH_FLD_RTT_WR2_NOM_VALUE_LEN = 16194; // 8
+static const uint64_t SH_FLD_RTT_WR3_NOM_VALUE = 16195; // 8
+static const uint64_t SH_FLD_RTT_WR3_NOM_VALUE_LEN = 16196; // 8
+static const uint64_t SH_FLD_RTT_WR4_NOM_VALUE = 16197; // 8
+static const uint64_t SH_FLD_RTT_WR4_NOM_VALUE_LEN = 16198; // 8
+static const uint64_t SH_FLD_RTT_WR5_NOM_VALUE = 16199; // 8
+static const uint64_t SH_FLD_RTT_WR5_NOM_VALUE_LEN = 16200; // 8
+static const uint64_t SH_FLD_RTT_WR6_NOM_VALUE = 16201; // 8
+static const uint64_t SH_FLD_RTT_WR6_NOM_VALUE_LEN = 16202; // 8
+static const uint64_t SH_FLD_RTT_WR7_NOM_VALUE = 16203; // 8
+static const uint64_t SH_FLD_RTT_WR7_NOM_VALUE_LEN = 16204; // 8
+static const uint64_t SH_FLD_RTY_COUNT = 16205; // 2
+static const uint64_t SH_FLD_RTY_COUNT_LEN = 16206; // 2
+static const uint64_t SH_FLD_RUNNING = 16207; // 92
+static const uint64_t SH_FLD_RUNN_COUNT_COMPARE_VALUE = 16208; // 43
+static const uint64_t SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN = 16209; // 43
+static const uint64_t SH_FLD_RUNN_MODE = 16210; // 43
+static const uint64_t SH_FLD_RUN_CHIPLET_SCAN0 = 16211; // 43
+static const uint64_t SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL = 16212; // 43
+static const uint64_t SH_FLD_RUN_DCCAL = 16213; // 48
+static const uint64_t SH_FLD_RUN_DYN_RECAL_TIMER = 16214; // 4
+static const uint64_t SH_FLD_RUN_LANE = 16215; // 48
+static const uint64_t SH_FLD_RUN_LANE_DL_MASK = 16216; // 2
+static const uint64_t SH_FLD_RUN_ON_CAPTURE_DR = 16217; // 43
+static const uint64_t SH_FLD_RUN_ON_UPDATE_DR = 16218; // 43
+static const uint64_t SH_FLD_RUN_SCAN0 = 16219; // 43
+static const uint64_t SH_FLD_RUN_STATE_MASK = 16220; // 43
+static const uint64_t SH_FLD_RUN_TCK = 16221; // 1
+static const uint64_t SH_FLD_RUN_TCK_EQ0_ERR = 16222; // 1
+static const uint64_t SH_FLD_RWDM_DLY = 16223; // 8
+static const uint64_t SH_FLD_RWDM_DLY_LEN = 16224; // 8
+static const uint64_t SH_FLD_RWSMDR_DLY = 16225; // 8
+static const uint64_t SH_FLD_RWSMDR_DLY_LEN = 16226; // 8
+static const uint64_t SH_FLD_RWSMSR_DLY = 16227; // 8
+static const uint64_t SH_FLD_RWSMSR_DLY_LEN = 16228; // 8
+static const uint64_t SH_FLD_RX = 16229; // 8
+static const uint64_t SH_FLD_RXAERR = 16230; // 6
+static const uint64_t SH_FLD_RXBERR = 16231; // 6
+static const uint64_t SH_FLD_RXCAL = 16232; // 116
+static const uint64_t SH_FLD_RXCERR = 16233; // 6
+static const uint64_t SH_FLD_RXDERR = 16234; // 6
+static const uint64_t SH_FLD_RXEERR = 16235; // 6
+static const uint64_t SH_FLD_RXFERR = 16236; // 6
+static const uint64_t SH_FLD_RXGERR = 16237; // 6
+static const uint64_t SH_FLD_RXHERR = 16238; // 6
+static const uint64_t SH_FLD_RXIERR = 16239; // 6
+static const uint64_t SH_FLD_RXJERR = 16240; // 6
+static const uint64_t SH_FLD_RXKERR = 16241; // 6
+static const uint64_t SH_FLD_RXLERR = 16242; // 6
+static const uint64_t SH_FLD_RXMERR = 16243; // 6
+static const uint64_t SH_FLD_RXNERR = 16244; // 6
+static const uint64_t SH_FLD_RXOERR = 16245; // 6
+static const uint64_t SH_FLD_RXPERR = 16246; // 6
+static const uint64_t SH_FLD_RX_BUS_WIDTH = 16247; // 4
+static const uint64_t SH_FLD_RX_BUS_WIDTH_LEN = 16248; // 4
+static const uint64_t SH_FLD_RX_BW = 16249; // 10
+static const uint64_t SH_FLD_RX_BW_LEN = 16250; // 10
+static const uint64_t SH_FLD_RX_PCB_DATA_P = 16251; // 1
+static const uint64_t SH_FLD_RX_PCB_DATA_P_ERR = 16252; // 1
+static const uint64_t SH_FLD_RX_SELECT = 16253; // 4
+static const uint64_t SH_FLD_RX_SELECT_LEN = 16254; // 4
+static const uint64_t SH_FLD_RX_TTYPE_0 = 16255; // 4
+static const uint64_t SH_FLD_RX_TTYPE_1 = 16256; // 4
+static const uint64_t SH_FLD_RX_TTYPE_1_ON_STEP_ENABLE = 16257; // 1
+static const uint64_t SH_FLD_RX_TTYPE_2 = 16258; // 4
+static const uint64_t SH_FLD_RX_TTYPE_3 = 16259; // 4
+static const uint64_t SH_FLD_RX_TTYPE_4 = 16260; // 4
+static const uint64_t SH_FLD_RX_TTYPE_4_DATA_PARITY = 16261; // 4
+static const uint64_t SH_FLD_RX_TTYPE_5 = 16262; // 4
+static const uint64_t SH_FLD_RX_TTYPE_INVALID = 16263; // 4
+static const uint64_t SH_FLD_S0_BIT_MAP = 16264; // 8
+static const uint64_t SH_FLD_S0_BIT_MAP_LEN = 16265; // 8
+static const uint64_t SH_FLD_S1_BIT_MAP = 16266; // 8
+static const uint64_t SH_FLD_S1_BIT_MAP_LEN = 16267; // 8
+static const uint64_t SH_FLD_S2_BIT_MAP = 16268; // 8
+static const uint64_t SH_FLD_S2_BIT_MAP_LEN = 16269; // 8
+static const uint64_t SH_FLD_SACOLL = 16270; // 12
+static const uint64_t SH_FLD_SAFE_REFRESH_MODE = 16271; // 8
+static const uint64_t SH_FLD_SAMPLED_SMD_PIN = 16272; // 1
+static const uint64_t SH_FLD_SAMPLE_GUTS = 16273; // 43
+static const uint64_t SH_FLD_SAMPLE_GUTS_LEN = 16274; // 43
+static const uint64_t SH_FLD_SAMPLE_PULSE_CNT = 16275; // 43
+static const uint64_t SH_FLD_SAMPLE_PULSE_CNT_LEN = 16276; // 43
+static const uint64_t SH_FLD_SAMPLE_VALID = 16277; // 12
+static const uint64_t SH_FLD_SAMPTEST_ENABLE = 16278; // 1
+static const uint64_t SH_FLD_SAMPTEST_MATCH_TH_MAX = 16279; // 1
+static const uint64_t SH_FLD_SAMPTEST_MATCH_TH_MAX_LEN = 16280; // 1
+static const uint64_t SH_FLD_SAMPTEST_MATCH_TH_MIN = 16281; // 1
+static const uint64_t SH_FLD_SAMPTEST_MATCH_TH_MIN_LEN = 16282; // 1
+static const uint64_t SH_FLD_SAMPTEST_RRN_ENABLE = 16283; // 1
+static const uint64_t SH_FLD_SAMPTEST_WINDOW_SIZE = 16284; // 1
+static const uint64_t SH_FLD_SAMPTEST_WINDOW_SIZE_LEN = 16285; // 1
+static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16286; // 43
+static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 16287; // 43
+static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 16288; // 43
+static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 16289; // 43
+static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 16290; // 43
+static const uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 16291; // 43
+static const uint64_t SH_FLD_SBASE = 16292; // 12
+static const uint64_t SH_FLD_SBASE_LEN = 16293; // 12
+static const uint64_t SH_FLD_SBC_DMA = 16294; // 1
+static const uint64_t SH_FLD_SBC_DMA_LEN = 16295; // 1
+static const uint64_t SH_FLD_SBC_EOI = 16296; // 1
+static const uint64_t SH_FLD_SBC_EOI_LEN = 16297; // 1
+static const uint64_t SH_FLD_SBC_LOOKUP = 16298; // 1
+static const uint64_t SH_FLD_SBC_LOOKUP_LEN = 16299; // 1
+static const uint64_t SH_FLD_SBEFIFO_DATA = 16300; // 5
+static const uint64_t SH_FLD_SBEFIFO_RESET = 16301; // 5
+static const uint64_t SH_FLD_SBE_ERROR_RATE = 16302; // 5
+static const uint64_t SH_FLD_SBE_ERROR_RATE_LEN = 16303; // 5
+static const uint64_t SH_FLD_SBE_EXTERNAL_FIRS = 16304; // 1
+static const uint64_t SH_FLD_SBE_EXTERNAL_FIRS_LEN = 16305; // 1
+static const uint64_t SH_FLD_SB_SCOM_ERRHOLD = 16306; // 2
+static const uint64_t SH_FLD_SB_STRENGTH = 16307; // 43
+static const uint64_t SH_FLD_SB_STRENGTH_LEN = 16308; // 43
+static const uint64_t SH_FLD_SCAN0_MODE = 16309; // 43
+static const uint64_t SH_FLD_SCAN_CLK_USE_EVEN = 16310; // 43
+static const uint64_t SH_FLD_SCAN_COUNT = 16311; // 43
+static const uint64_t SH_FLD_SCAN_COUNT_LEN = 16312; // 43
+static const uint64_t SH_FLD_SCAN_INIT_VERSION_PARITY_MASK = 16313; // 43
+static const uint64_t SH_FLD_SCAN_RATIO = 16314; // 43
+static const uint64_t SH_FLD_SCAN_RATIO_LEN = 16315; // 43
+static const uint64_t SH_FLD_SCOM1_SAT_ERR = 16316; // 2
+static const uint64_t SH_FLD_SCOM20A_SEL = 16317; // 8
+static const uint64_t SH_FLD_SCOMFIR_INT_ERR_0 = 16318; // 2
+static const uint64_t SH_FLD_SCOMFIR_INT_ERR_1 = 16319; // 2
+static const uint64_t SH_FLD_SCOMSAT00_ERR = 16320; // 1
+static const uint64_t SH_FLD_SCOMSAT01_ERR = 16321; // 1
+static const uint64_t SH_FLD_SCOM_CMD_REG_INJ = 16322; // 2
+static const uint64_t SH_FLD_SCOM_CMD_REG_INJ_MODE = 16323; // 2
+static const uint64_t SH_FLD_SCOM_ERR = 16324; // 26
+static const uint64_t SH_FLD_SCOM_ERR1 = 16325; // 36
+static const uint64_t SH_FLD_SCOM_ERR2 = 16326; // 40
+static const uint64_t SH_FLD_SCOM_ERROR = 16327; // 10
+static const uint64_t SH_FLD_SCOM_ERR_DUP = 16328; // 22
+static const uint64_t SH_FLD_SCOM_FATAL_ERROR = 16329; // 6
+static const uint64_t SH_FLD_SCOM_FATAL_REG_PE = 16330; // 2
+static const uint64_t SH_FLD_SCOM_FIR_HMI = 16331; // 96
+static const uint64_t SH_FLD_SCOM_HANG_LIMIT = 16332; // 43
+static const uint64_t SH_FLD_SCOM_HANG_LIMIT_LEN = 16333; // 43
+static const uint64_t SH_FLD_SCOM_INF_ERROR = 16334; // 6
+static const uint64_t SH_FLD_SCOM_LINK01_RESET_KEEPER = 16335; // 2
+static const uint64_t SH_FLD_SCOM_LINK23_RESET_KEEPER = 16336; // 2
+static const uint64_t SH_FLD_SCOM_LINK45_RESET_KEEPER = 16337; // 2
+static const uint64_t SH_FLD_SCOM_LINK67_RESET_KEEPER = 16338; // 1
+static const uint64_t SH_FLD_SCOM_MMIO_ADDR_ERR = 16339; // 2
+static const uint64_t SH_FLD_SCOM_PARITY_CLASS_RECOVERABLE = 16340; // 8
+static const uint64_t SH_FLD_SCOM_PARITY_CLASS_STATUS = 16341; // 8
+static const uint64_t SH_FLD_SCOM_PARITY_CLASS_UNRECOVERABLE = 16342; // 8
+static const uint64_t SH_FLD_SCOM_PARITY_ERR = 16343; // 3
+static const uint64_t SH_FLD_SCOM_PARITY_ERR2 = 16344; // 3
+static const uint64_t SH_FLD_SCOM_PE = 16345; // 3
+static const uint64_t SH_FLD_SCOM_PERFMON_START_COMMAND = 16346; // 4
+static const uint64_t SH_FLD_SCOM_PERFMON_STOP_COMMAND = 16347; // 4
+static const uint64_t SH_FLD_SCOM_PERR0 = 16348; // 6
+static const uint64_t SH_FLD_SCOM_PERR1 = 16349; // 6
+static const uint64_t SH_FLD_SCOM_PE_DUP = 16350; // 3
+static const uint64_t SH_FLD_SCOM_PE_DUP_FIR = 16351; // 1
+static const uint64_t SH_FLD_SCOM_PE_FIR = 16352; // 1
+static const uint64_t SH_FLD_SCOM_RECOVERABLE_REG_PE = 16353; // 2
+static const uint64_t SH_FLD_SCOM_SET_WAT_EXT_ARM = 16354; // 2
+static const uint64_t SH_FLD_SCOM_SET_WAT_EXT_RESET = 16355; // 2
+static const uint64_t SH_FLD_SCOM_SET_WAT_EXT_TRIGGER = 16356; // 2
+static const uint64_t SH_FLD_SCOM_S_ERR = 16357; // 1
+static const uint64_t SH_FLD_SCOM_WRITE = 16358; // 24
+static const uint64_t SH_FLD_SCOPE = 16359; // 24
+static const uint64_t SH_FLD_SCOPE_ATTN_BAR = 16360; // 1
+static const uint64_t SH_FLD_SCOPE_ATTN_BAR_LEN = 16361; // 1
+static const uint64_t SH_FLD_SCOPE_CONTROL = 16362; // 6
+static const uint64_t SH_FLD_SCOPE_CONTROL_LEN = 16363; // 6
+static const uint64_t SH_FLD_SCOPE_LEN = 16364; // 24
+static const uint64_t SH_FLD_SCOPE_MODE = 16365; // 48
+static const uint64_t SH_FLD_SCOPE_MODE_LEN = 16366; // 48
+static const uint64_t SH_FLD_SCPTGT_LFSR_MODE = 16367; // 2
+static const uint64_t SH_FLD_SCPTGT_LFSR_MODE_LEN = 16368; // 2
+static const uint64_t SH_FLD_SCRATCH_ATOMIC_DATA = 16369; // 24
+static const uint64_t SH_FLD_SCRATCH_ATOMIC_DATA_LEN = 16370; // 24
+static const uint64_t SH_FLD_SCRATCH_N = 16371; // 4
+static const uint64_t SH_FLD_SCRATCH_N_LEN = 16372; // 4
+static const uint64_t SH_FLD_SC_RDATA_PARITY_ERRHOLD = 16373; // 2
+static const uint64_t SH_FLD_SEC = 16374; // 8
+static const uint64_t SH_FLD_SECOND = 16375; // 1
+static const uint64_t SH_FLD_SECURE = 16376; // 1
+static const uint64_t SH_FLD_SECURE_ACCESS = 16377; // 1
+static const uint64_t SH_FLD_SECURE_ACCESS_BIT = 16378; // 1
+static const uint64_t SH_FLD_SECURE_DEBUG = 16379; // 1
+static const uint64_t SH_FLD_SECURE_DEBUG_MODE = 16380; // 1
+static const uint64_t SH_FLD_SECURE_ERR = 16381; // 2
+static const uint64_t SH_FLD_SECURE_LNK_RSP_PKT_NOT_VALID_ERRHOLD = 16382; // 2
+static const uint64_t SH_FLD_SECURE_LNK_SCOM_CONFLICT_ERRHOLD = 16383; // 2
+static const uint64_t SH_FLD_SECURE_SCOM_ERROR = 16384; // 4
+static const uint64_t SH_FLD_SECURITY_DEBUG_MODE = 16385; // 43
+static const uint64_t SH_FLD_SEC_I_PATH_STEP_CHECK_ENABLE = 16386; // 1
+static const uint64_t SH_FLD_SEC_LEN = 16387; // 8
+static const uint64_t SH_FLD_SEC_M_PATH_0_STEP_CHECK_ENABLE = 16388; // 1
+static const uint64_t SH_FLD_SEC_M_PATH_1_STEP_CHECK_ENABLE = 16389; // 1
+static const uint64_t SH_FLD_SEC_M_PATH_SELECT = 16390; // 2
+static const uint64_t SH_FLD_SEC_M_S_DRAWER_SELECT = 16391; // 2
+static const uint64_t SH_FLD_SEC_M_S_SELECT = 16392; // 2
+static const uint64_t SH_FLD_SEC_SELECT = 16393; // 1
+static const uint64_t SH_FLD_SEC_S_PATH_0_STEP_CHECK_ENABLE = 16394; // 1
+static const uint64_t SH_FLD_SEC_S_PATH_1_STEP_CHECK_ENABLE = 16395; // 1
+static const uint64_t SH_FLD_SEC_S_PATH_SELECT = 16396; // 1
+static const uint64_t SH_FLD_SEC_V = 16397; // 8
+static const uint64_t SH_FLD_SEC_WBRD_DEBUG_0_SELECT = 16398; // 8
+static const uint64_t SH_FLD_SEC_WBRD_DEBUG_1_SELECT = 16399; // 8
+static const uint64_t SH_FLD_SEEPROM_UPDATE_LOCK = 16400; // 1
+static const uint64_t SH_FLD_SEG_TEST_CLK_STATUS = 16401; // 4
+static const uint64_t SH_FLD_SEG_TEST_CLK_STATUS_LEN = 16402; // 4
+static const uint64_t SH_FLD_SEG_TEST_LEAKAGE_CTRL = 16403; // 6
+static const uint64_t SH_FLD_SEG_TEST_MODE = 16404; // 6
+static const uint64_t SH_FLD_SEG_TEST_MODE_LEN = 16405; // 6
+static const uint64_t SH_FLD_SEG_TEST_STATUS = 16406; // 116
+static const uint64_t SH_FLD_SEG_TEST_STATUS_LEN = 16407; // 116
+static const uint64_t SH_FLD_SEIDBAR = 16408; // 1
+static const uint64_t SH_FLD_SEIDBAR_LEN = 16409; // 1
+static const uint64_t SH_FLD_SEIDR = 16410; // 256
+static const uint64_t SH_FLD_SEIDR_LEN = 16411; // 256
+static const uint64_t SH_FLD_SEL = 16412; // 10
+static const uint64_t SH_FLD_SEL0 = 16413; // 1
+static const uint64_t SH_FLD_SEL0_LEN = 16414; // 1
+static const uint64_t SH_FLD_SEL1 = 16415; // 1
+static const uint64_t SH_FLD_SEL1_LEN = 16416; // 1
+static const uint64_t SH_FLD_SELD2SPR = 16417; // 10
+static const uint64_t SH_FLD_SELECT = 16418; // 2
+static const uint64_t SH_FLD_SELECT_0 = 16419; // 5
+static const uint64_t SH_FLD_SELECT_0_LEN = 16420; // 5
+static const uint64_t SH_FLD_SELECT_1 = 16421; // 5
+static const uint64_t SH_FLD_SELECT_1_LEN = 16422; // 5
+static const uint64_t SH_FLD_SELECT_2 = 16423; // 5
+static const uint64_t SH_FLD_SELECT_2_LEN = 16424; // 5
+static const uint64_t SH_FLD_SELECT_3 = 16425; // 5
+static const uint64_t SH_FLD_SELECT_3_LEN = 16426; // 5
+static const uint64_t SH_FLD_SELECT_4 = 16427; // 5
+static const uint64_t SH_FLD_SELECT_4_LEN = 16428; // 5
+static const uint64_t SH_FLD_SELECT_5 = 16429; // 5
+static const uint64_t SH_FLD_SELECT_5_LEN = 16430; // 5
+static const uint64_t SH_FLD_SELECT_6 = 16431; // 5
+static const uint64_t SH_FLD_SELECT_6_LEN = 16432; // 5
+static const uint64_t SH_FLD_SELECT_7 = 16433; // 5
+static const uint64_t SH_FLD_SELECT_7_LEN = 16434; // 5
+static const uint64_t SH_FLD_SELECT_LEN = 16435; // 2
+static const uint64_t SH_FLD_SELECT_LOCAL_HANG_PULSE = 16436; // 4
+static const uint64_t SH_FLD_SELECT_PB_HANG_PULSE = 16437; // 4
+static const uint64_t SH_FLD_SELECT_REGISTER_FSP2PIB = 16438; // 1
+static const uint64_t SH_FLD_SELECT_REGISTER_FSP2PIB_LEN = 16439; // 1
+static const uint64_t SH_FLD_SELECT_SECONDARY_SEEPROM = 16440; // 1
+static const uint64_t SH_FLD_SELFBOOT_DONE = 16441; // 1
+static const uint64_t SH_FLD_SELFBOOT_ENGINE_ATTENTION = 16442; // 1
+static const uint64_t SH_FLD_SELF_BUSY_0 = 16443; // 4
+static const uint64_t SH_FLD_SELF_BUSY_1 = 16444; // 2
+static const uint64_t SH_FLD_SELF_BUSY_2 = 16445; // 2
+static const uint64_t SH_FLD_SELF_BUSY_3 = 16446; // 2
+static const uint64_t SH_FLD_SELPFDPW = 16447; // 10
+static const uint64_t SH_FLD_SELPREFB = 16448; // 10
+static const uint64_t SH_FLD_SELPRESPE = 16449; // 10
+static const uint64_t SH_FLD_SEL_03_NPU_NOT = 16450; // 1
+static const uint64_t SH_FLD_SEL_04_NPU_NOT = 16451; // 1
+static const uint64_t SH_FLD_SEL_05_NPU_NOT = 16452; // 1
+static const uint64_t SH_FLD_SEL_0_2 = 16453; // 16
+static const uint64_t SH_FLD_SEL_0_2_LEN = 16454; // 16
+static const uint64_t SH_FLD_SEL_1_3 = 16455; // 16
+static const uint64_t SH_FLD_SEL_1_3_LEN = 16456; // 16
+static const uint64_t SH_FLD_SEL_LEN = 16457; // 10
+static const uint64_t SH_FLD_SEL_RG_PMU_DATA = 16458; // 1
+static const uint64_t SH_FLD_SEL_RG_TRACE_DATA_HI = 16459; // 1
+static const uint64_t SH_FLD_SEL_RG_TRACE_DATA_HI_LEN = 16460; // 1
+static const uint64_t SH_FLD_SEL_RG_TRACE_DATA_LO = 16461; // 1
+static const uint64_t SH_FLD_SEL_RG_TRACE_DATA_LO_LEN = 16462; // 1
+static const uint64_t SH_FLD_SEL_RG_TRIGGERS_01 = 16463; // 1
+static const uint64_t SH_FLD_SEL_RG_TRIGGERS_01_LEN = 16464; // 1
+static const uint64_t SH_FLD_SEL_RG_TRIGGERS_23 = 16465; // 1
+static const uint64_t SH_FLD_SEL_RG_TRIGGERS_23_LEN = 16466; // 1
+static const uint64_t SH_FLD_SEL_THOLD_ARY = 16467; // 43
+static const uint64_t SH_FLD_SEL_THOLD_NSL = 16468; // 43
+static const uint64_t SH_FLD_SEL_THOLD_SL = 16469; // 43
+static const uint64_t SH_FLD_SEL_TYPE_0_2 = 16470; // 16
+static const uint64_t SH_FLD_SEL_TYPE_1_3 = 16471; // 16
+static const uint64_t SH_FLD_SEND_DELAY_CYCLES = 16472; // 2
+static const uint64_t SH_FLD_SEND_DELAY_CYCLES_LEN = 16473; // 2
+static const uint64_t SH_FLD_SEND_PACKET_TIMER_VALUE = 16474; // 2
+static const uint64_t SH_FLD_SEND_PACKET_TIMER_VALUE_LEN = 16475; // 2
+static const uint64_t SH_FLD_SENSEADJ_RESET0 = 16476; // 43
+static const uint64_t SH_FLD_SENSEADJ_RESET1 = 16477; // 43
+static const uint64_t SH_FLD_SEQ = 16478; // 8
+static const uint64_t SH_FLD_SEQ_01 = 16479; // 43
+static const uint64_t SH_FLD_SEQ_01_LEN = 16480; // 43
+static const uint64_t SH_FLD_SEQ_02 = 16481; // 43
+static const uint64_t SH_FLD_SEQ_02_LEN = 16482; // 43
+static const uint64_t SH_FLD_SEQ_03 = 16483; // 43
+static const uint64_t SH_FLD_SEQ_03_LEN = 16484; // 43
+static const uint64_t SH_FLD_SEQ_04 = 16485; // 43
+static const uint64_t SH_FLD_SEQ_04_LEN = 16486; // 43
+static const uint64_t SH_FLD_SEQ_05 = 16487; // 43
+static const uint64_t SH_FLD_SEQ_05_LEN = 16488; // 43
+static const uint64_t SH_FLD_SEQ_06 = 16489; // 43
+static const uint64_t SH_FLD_SEQ_06_LEN = 16490; // 43
+static const uint64_t SH_FLD_SEQ_07 = 16491; // 43
+static const uint64_t SH_FLD_SEQ_07EVEN = 16492; // 43
+static const uint64_t SH_FLD_SEQ_07EVEN_LEN = 16493; // 43
+static const uint64_t SH_FLD_SEQ_07ODD = 16494; // 43
+static const uint64_t SH_FLD_SEQ_07ODD_LEN = 16495; // 43
+static const uint64_t SH_FLD_SEQ_07_LEN = 16496; // 43
+static const uint64_t SH_FLD_SEQ_08 = 16497; // 43
+static const uint64_t SH_FLD_SEQ_08EVEN = 16498; // 43
+static const uint64_t SH_FLD_SEQ_08EVEN_LEN = 16499; // 43
+static const uint64_t SH_FLD_SEQ_08ODD = 16500; // 43
+static const uint64_t SH_FLD_SEQ_08ODD_LEN = 16501; // 43
+static const uint64_t SH_FLD_SEQ_08_LEN = 16502; // 43
+static const uint64_t SH_FLD_SEQ_09 = 16503; // 43
+static const uint64_t SH_FLD_SEQ_09EVEN = 16504; // 43
+static const uint64_t SH_FLD_SEQ_09EVEN_LEN = 16505; // 43
+static const uint64_t SH_FLD_SEQ_09ODD = 16506; // 43
+static const uint64_t SH_FLD_SEQ_09ODD_LEN = 16507; // 43
+static const uint64_t SH_FLD_SEQ_09_LEN = 16508; // 43
+static const uint64_t SH_FLD_SEQ_10 = 16509; // 43
+static const uint64_t SH_FLD_SEQ_10EVEN = 16510; // 43
+static const uint64_t SH_FLD_SEQ_10EVEN_LEN = 16511; // 43
+static const uint64_t SH_FLD_SEQ_10ODD = 16512; // 43
+static const uint64_t SH_FLD_SEQ_10ODD_LEN = 16513; // 43
+static const uint64_t SH_FLD_SEQ_10_LEN = 16514; // 43
+static const uint64_t SH_FLD_SEQ_11 = 16515; // 43
+static const uint64_t SH_FLD_SEQ_11EVEN = 16516; // 43
+static const uint64_t SH_FLD_SEQ_11EVEN_LEN = 16517; // 43
+static const uint64_t SH_FLD_SEQ_11ODD = 16518; // 43
+static const uint64_t SH_FLD_SEQ_11ODD_LEN = 16519; // 43
+static const uint64_t SH_FLD_SEQ_11_LEN = 16520; // 43
+static const uint64_t SH_FLD_SEQ_12 = 16521; // 43
+static const uint64_t SH_FLD_SEQ_12EVEN = 16522; // 43
+static const uint64_t SH_FLD_SEQ_12EVEN_LEN = 16523; // 43
+static const uint64_t SH_FLD_SEQ_12ODD = 16524; // 43
+static const uint64_t SH_FLD_SEQ_12ODD_LEN = 16525; // 43
+static const uint64_t SH_FLD_SEQ_12_LEN = 16526; // 43
+static const uint64_t SH_FLD_SEQ_13_01EVEN = 16527; // 43
+static const uint64_t SH_FLD_SEQ_13_01EVEN_LEN = 16528; // 43
+static const uint64_t SH_FLD_SEQ_14_01ODD = 16529; // 43
+static const uint64_t SH_FLD_SEQ_14_01ODD_LEN = 16530; // 43
+static const uint64_t SH_FLD_SEQ_15_02EVEN = 16531; // 43
+static const uint64_t SH_FLD_SEQ_15_02EVEN_LEN = 16532; // 43
+static const uint64_t SH_FLD_SEQ_16_02ODD = 16533; // 43
+static const uint64_t SH_FLD_SEQ_16_02ODD_LEN = 16534; // 43
+static const uint64_t SH_FLD_SEQ_17_03EVEN = 16535; // 43
+static const uint64_t SH_FLD_SEQ_17_03EVEN_LEN = 16536; // 43
+static const uint64_t SH_FLD_SEQ_18_03ODD = 16537; // 43
+static const uint64_t SH_FLD_SEQ_18_03ODD_LEN = 16538; // 43
+static const uint64_t SH_FLD_SEQ_19_04EVEN = 16539; // 43
+static const uint64_t SH_FLD_SEQ_19_04EVEN_LEN = 16540; // 43
+static const uint64_t SH_FLD_SEQ_20_04ODD = 16541; // 43
+static const uint64_t SH_FLD_SEQ_20_04ODD_LEN = 16542; // 43
+static const uint64_t SH_FLD_SEQ_21_05EVEN = 16543; // 43
+static const uint64_t SH_FLD_SEQ_21_05EVEN_LEN = 16544; // 43
+static const uint64_t SH_FLD_SEQ_22_05ODD = 16545; // 43
+static const uint64_t SH_FLD_SEQ_22_05ODD_LEN = 16546; // 43
+static const uint64_t SH_FLD_SEQ_23_06EVEN = 16547; // 43
+static const uint64_t SH_FLD_SEQ_23_06EVEN_LEN = 16548; // 43
+static const uint64_t SH_FLD_SEQ_24_06ODD = 16549; // 43
+static const uint64_t SH_FLD_SEQ_24_06ODD_LEN = 16550; // 43
+static const uint64_t SH_FLD_SEQ_MASK = 16551; // 8
+static const uint64_t SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 16552; // 43
+static const uint64_t SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 16553; // 43
+static const uint64_t SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK = 16554; // 43
+static const uint64_t SH_FLD_SERVO_CHG_CFG = 16555; // 6
+static const uint64_t SH_FLD_SERVO_CHG_CFG_LEN = 16556; // 6
+static const uint64_t SH_FLD_SERVO_CONFIG = 16557; // 6
+static const uint64_t SH_FLD_SERVO_CONFIG_LEN = 16558; // 6
+static const uint64_t SH_FLD_SERVO_DONE = 16559; // 6
+static const uint64_t SH_FLD_SERVO_OP = 16560; // 6
+static const uint64_t SH_FLD_SERVO_OP_LEN = 16561; // 6
+static const uint64_t SH_FLD_SERVO_RECAL_IP = 16562; // 4
+static const uint64_t SH_FLD_SERVO_RESULT = 16563; // 6
+static const uint64_t SH_FLD_SERVO_RESULT_LEN = 16564; // 6
+static const uint64_t SH_FLD_SERVO_THRESH1 = 16565; // 6
+static const uint64_t SH_FLD_SERVO_THRESH1_LEN = 16566; // 6
+static const uint64_t SH_FLD_SERVO_THRESH2 = 16567; // 6
+static const uint64_t SH_FLD_SERVO_THRESH2_LEN = 16568; // 6
+static const uint64_t SH_FLD_SERVO_THRESH3 = 16569; // 4
+static const uint64_t SH_FLD_SERVO_THRESH3_LEN = 16570; // 4
+static const uint64_t SH_FLD_SET = 16571; // 6
+static const uint64_t SH_FLD_SET_CMDS = 16572; // 2
+static const uint64_t SH_FLD_SET_CMDS_EN = 16573; // 2
+static const uint64_t SH_FLD_SET_CMDS_LEN = 16574; // 2
+static const uint64_t SH_FLD_SET_ECC_INJECT_ERR = 16575; // 12
+static const uint64_t SH_FLD_SET_EXT_ARM = 16576; // 4
+static const uint64_t SH_FLD_SET_EXT_RESET = 16577; // 4
+static const uint64_t SH_FLD_SET_EXT_TRIGGER = 16578; // 4
+static const uint64_t SH_FLD_SET_INDEX = 16579; // 2
+static const uint64_t SH_FLD_SET_INDEX_LEN = 16580; // 2
+static const uint64_t SH_FLD_SET_LEN = 16581; // 6
+static const uint64_t SH_FLD_SGB_BYTE_VALID = 16582; // 21
+static const uint64_t SH_FLD_SGB_BYTE_VALID_LEN = 16583; // 21
+static const uint64_t SH_FLD_SGB_FLUSH_PENDING = 16584; // 21
+static const uint64_t SH_FLD_SG_HIGH_DURING_FILL = 16585; // 43
+static const uint64_t SH_FLD_SHADOW_ANALOGTUNE = 16586; // 14
+static const uint64_t SH_FLD_SHADOW_ANALOGTUNE_LEN = 16587; // 14
+static const uint64_t SH_FLD_SHADOW_ATSTSEL = 16588; // 14
+static const uint64_t SH_FLD_SHADOW_ATSTSEL_LEN = 16589; // 14
+static const uint64_t SH_FLD_SHADOW_BANDSEL = 16590; // 14
+static const uint64_t SH_FLD_SHADOW_BANDSEL_LEN = 16591; // 14
+static const uint64_t SH_FLD_SHADOW_BGOFFSET = 16592; // 14
+static const uint64_t SH_FLD_SHADOW_BGOFFSET_LEN = 16593; // 14
+static const uint64_t SH_FLD_SHADOW_BYPASSN = 16594; // 10
+static const uint64_t SH_FLD_SHADOW_CALRECAL = 16595; // 10
+static const uint64_t SH_FLD_SHADOW_CALREQ = 16596; // 10
+static const uint64_t SH_FLD_SHADOW_CAPSEL = 16597; // 4
+static const uint64_t SH_FLD_SHADOW_CCALBANDSEL = 16598; // 10
+static const uint64_t SH_FLD_SHADOW_CCALBANDSEL_LEN = 16599; // 10
+static const uint64_t SH_FLD_SHADOW_CCALCOMP = 16600; // 10
+static const uint64_t SH_FLD_SHADOW_CCALCVHOLD = 16601; // 10
+static const uint64_t SH_FLD_SHADOW_CCALERR = 16602; // 10
+static const uint64_t SH_FLD_SHADOW_CCALFMAX = 16603; // 10
+static const uint64_t SH_FLD_SHADOW_CCALFMIN = 16604; // 10
+static const uint64_t SH_FLD_SHADOW_CCALLOAD = 16605; // 10
+static const uint64_t SH_FLD_SHADOW_CCALMETH = 16606; // 10
+static const uint64_t SH_FLD_SHADOW_CMLEN = 16607; // 7
+static const uint64_t SH_FLD_SHADOW_CMLEN100 = 16608; // 3
+static const uint64_t SH_FLD_SHADOW_CMLEN133 = 16609; // 3
+static const uint64_t SH_FLD_SHADOW_CMLEN156 = 16610; // 3
+static const uint64_t SH_FLD_SHADOW_CPISEL = 16611; // 14
+static const uint64_t SH_FLD_SHADOW_CPISEL_LEN = 16612; // 14
+static const uint64_t SH_FLD_SHADOW_CSEL = 16613; // 10
+static const uint64_t SH_FLD_SHADOW_CSEL_LEN = 16614; // 10
+static const uint64_t SH_FLD_SHADOW_DIVSELB = 16615; // 10
+static const uint64_t SH_FLD_SHADOW_DIVSELB_LEN = 16616; // 10
+static const uint64_t SH_FLD_SHADOW_DIVSELFB = 16617; // 4
+static const uint64_t SH_FLD_SHADOW_DIVSELFB_LEN = 16618; // 4
+static const uint64_t SH_FLD_SHADOW_EN = 16619; // 10
+static const uint64_t SH_FLD_SHADOW_ENABLE = 16620; // 10
+static const uint64_t SH_FLD_SHADOW_FILTDIVSEL = 16621; // 3
+static const uint64_t SH_FLD_SHADOW_FILTDIVSEL_LEN = 16622; // 3
+static const uint64_t SH_FLD_SHADOW_FRAC1 = 16623; // 3
+static const uint64_t SH_FLD_SHADOW_FRAC1_LEN = 16624; // 3
+static const uint64_t SH_FLD_SHADOW_FRAC2 = 16625; // 3
+static const uint64_t SH_FLD_SHADOW_FRAC2_LEN = 16626; // 3
+static const uint64_t SH_FLD_SHADOW_ITUNE = 16627; // 4
+static const uint64_t SH_FLD_SHADOW_ITUNE_LEN = 16628; // 4
+static const uint64_t SH_FLD_SHADOW_LOCK = 16629; // 10
+static const uint64_t SH_FLD_SHADOW_MUXEN = 16630; // 4
+static const uint64_t SH_FLD_SHADOW_MUXSEL = 16631; // 4
+static const uint64_t SH_FLD_SHADOW_MUXSEL_LEN = 16632; // 4
+static const uint64_t SH_FLD_SHADOW_PCLKDIFSEL = 16633; // 10
+static const uint64_t SH_FLD_SHADOW_PCLKSEL = 16634; // 14
+static const uint64_t SH_FLD_SHADOW_PCLKSEL_LEN = 16635; // 14
+static const uint64_t SH_FLD_SHADOW_PFD360SEL = 16636; // 4
+static const uint64_t SH_FLD_SHADOW_PHASEFB = 16637; // 4
+static const uint64_t SH_FLD_SHADOW_PHASEFB_LEN = 16638; // 4
+static const uint64_t SH_FLD_SHADOW_PLLLOCK = 16639; // 4
+static const uint64_t SH_FLD_SHADOW_RDIV = 16640; // 14
+static const uint64_t SH_FLD_SHADOW_RDIV_LEN = 16641; // 10
+static const uint64_t SH_FLD_SHADOW_REFCLKSEL = 16642; // 4
+static const uint64_t SH_FLD_SHADOW_RESET = 16643; // 10
+static const uint64_t SH_FLD_SHADOW_RESSEL = 16644; // 4
+static const uint64_t SH_FLD_SHADOW_RSEL = 16645; // 10
+static const uint64_t SH_FLD_SHADOW_RSEL_LEN = 16646; // 10
+static const uint64_t SH_FLD_SHADOW_SEL = 16647; // 10
+static const uint64_t SH_FLD_SHADOW_SELD2SPR = 16648; // 10
+static const uint64_t SH_FLD_SHADOW_SELPFDPW = 16649; // 10
+static const uint64_t SH_FLD_SHADOW_SELPREFB = 16650; // 10
+static const uint64_t SH_FLD_SHADOW_SELPRESPE = 16651; // 10
+static const uint64_t SH_FLD_SHADOW_SEL_LEN = 16652; // 10
+static const uint64_t SH_FLD_SHADOW_SPARE = 16653; // 7
+static const uint64_t SH_FLD_SHADOW_SPARE_LEN = 16654; // 3
+static const uint64_t SH_FLD_SHADOW_SPEDIV = 16655; // 10
+static const uint64_t SH_FLD_SHADOW_SPEDIV_LEN = 16656; // 10
+static const uint64_t SH_FLD_SHADOW_SSCGEN = 16657; // 3
+static const uint64_t SH_FLD_SHADOW_SYNCEN = 16658; // 7
+static const uint64_t SH_FLD_SHADOW_UNUSED23_31 = 16659; // 7
+static const uint64_t SH_FLD_SHADOW_UNUSED23_31_LEN = 16660; // 7
+static const uint64_t SH_FLD_SHADOW_UNUSED4 = 16661; // 7
+static const uint64_t SH_FLD_SHADOW_UNUSED5 = 16662; // 7
+static const uint64_t SH_FLD_SHADOW_UNUSED63 = 16663; // 3
+static const uint64_t SH_FLD_SHADOW_UNUSED88 = 16664; // 3
+static const uint64_t SH_FLD_SHADOW_UNUSED88_LEN = 16665; // 3
+static const uint64_t SH_FLD_SHADOW_VCORANGE = 16666; // 10
+static const uint64_t SH_FLD_SHADOW_VCORANGE_LEN = 16667; // 10
+static const uint64_t SH_FLD_SHADOW_VCOSEL = 16668; // 10
+static const uint64_t SH_FLD_SHADOW_VREGBYPASS = 16669; // 4
+static const uint64_t SH_FLD_SHADOW_VREGENABLE_N = 16670; // 4
+static const uint64_t SH_FLD_SHADOW_VSEL = 16671; // 10
+static const uint64_t SH_FLD_SHADOW_VSEL_LEN = 16672; // 10
+static const uint64_t SH_FLD_SHA_LATENCY_CFG = 16673; // 1
+static const uint64_t SH_FLD_SHIFTER_PARITY_MASK = 16674; // 43
+static const uint64_t SH_FLD_SHIFTER_VALID_MASK = 16675; // 43
+static const uint64_t SH_FLD_SIBLING_CORE_DROPOUT_ENABLE = 16676; // 12
+static const uint64_t SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN = 16677; // 12
+static const uint64_t SH_FLD_SIGNATURE = 16678; // 1
+static const uint64_t SH_FLD_SIGNATURE_LEN = 16679; // 1
+static const uint64_t SH_FLD_SINGLE_BIT_MPR_RP0 = 16680; // 8
+static const uint64_t SH_FLD_SINGLE_BIT_MPR_RP1 = 16681; // 8
+static const uint64_t SH_FLD_SINGLE_BIT_MPR_RP2 = 16682; // 8
+static const uint64_t SH_FLD_SINGLE_BIT_MPR_RP3 = 16683; // 8
+static const uint64_t SH_FLD_SINGLE_OUTSTANDING_CMD = 16684; // 1
+static const uint64_t SH_FLD_SIZE = 16685; // 45
+static const uint64_t SH_FLD_SIZE_0 = 16686; // 5
+static const uint64_t SH_FLD_SIZE_0_LEN = 16687; // 5
+static const uint64_t SH_FLD_SIZE_1 = 16688; // 5
+static const uint64_t SH_FLD_SIZE_1_LEN = 16689; // 5
+static const uint64_t SH_FLD_SIZE_2 = 16690; // 5
+static const uint64_t SH_FLD_SIZE_2_LEN = 16691; // 5
+static const uint64_t SH_FLD_SIZE_3 = 16692; // 5
+static const uint64_t SH_FLD_SIZE_3_LEN = 16693; // 5
+static const uint64_t SH_FLD_SIZE_4 = 16694; // 5
+static const uint64_t SH_FLD_SIZE_4_LEN = 16695; // 5
+static const uint64_t SH_FLD_SIZE_5 = 16696; // 5
+static const uint64_t SH_FLD_SIZE_5_LEN = 16697; // 5
+static const uint64_t SH_FLD_SIZE_6 = 16698; // 5
+static const uint64_t SH_FLD_SIZE_6_LEN = 16699; // 5
+static const uint64_t SH_FLD_SIZE_7 = 16700; // 5
+static const uint64_t SH_FLD_SIZE_7_LEN = 16701; // 5
+static const uint64_t SH_FLD_SIZE_LEN = 16702; // 45
+static const uint64_t SH_FLD_SKIP_G = 16703; // 4
+static const uint64_t SH_FLD_SKIP_INVALID_ADDR_DIMM_DIS = 16704; // 2
+static const uint64_t SH_FLD_SKIP_RDCENTERING = 16705; // 8
+static const uint64_t SH_FLD_SKITTER0 = 16706; // 43
+static const uint64_t SH_FLD_SKITTER0_DELAY_SELECT = 16707; // 43
+static const uint64_t SH_FLD_SKITTER0_DELAY_SELECT_LEN = 16708; // 43
+static const uint64_t SH_FLD_SKITTER0_LEN = 16709; // 43
+static const uint64_t SH_FLD_SKITTER_FORCEREG_PARITY_MASK = 16710; // 43
+static const uint64_t SH_FLD_SKITTER_MODEREG_PARITY_MASK = 16711; // 43
+static const uint64_t SH_FLD_SLAVE10_ERROR_CODE = 16712; // 1
+static const uint64_t SH_FLD_SLAVE10_ERROR_CODE_LEN = 16713; // 1
+static const uint64_t SH_FLD_SLAVE10_RESPONSE_BIT = 16714; // 1
+static const uint64_t SH_FLD_SLAVE11_ERROR_CODE = 16715; // 1
+static const uint64_t SH_FLD_SLAVE11_ERROR_CODE_LEN = 16716; // 1
+static const uint64_t SH_FLD_SLAVE11_RESPONSE_BIT = 16717; // 1
+static const uint64_t SH_FLD_SLAVE12_ERROR_CODE = 16718; // 1
+static const uint64_t SH_FLD_SLAVE12_ERROR_CODE_LEN = 16719; // 1
+static const uint64_t SH_FLD_SLAVE12_RESPONSE_BIT = 16720; // 1
+static const uint64_t SH_FLD_SLAVE13_ERROR_CODE = 16721; // 1
+static const uint64_t SH_FLD_SLAVE13_ERROR_CODE_LEN = 16722; // 1
+static const uint64_t SH_FLD_SLAVE13_RESPONSE_BIT = 16723; // 1
+static const uint64_t SH_FLD_SLAVE14_ERROR_CODE = 16724; // 1
+static const uint64_t SH_FLD_SLAVE14_ERROR_CODE_LEN = 16725; // 1
+static const uint64_t SH_FLD_SLAVE14_RESPONSE_BIT = 16726; // 1
+static const uint64_t SH_FLD_SLAVE15_ERROR_CODE = 16727; // 1
+static const uint64_t SH_FLD_SLAVE15_ERROR_CODE_LEN = 16728; // 1
+static const uint64_t SH_FLD_SLAVE15_RESPONSE_BIT = 16729; // 1
+static const uint64_t SH_FLD_SLAVE16_ERROR_CODE = 16730; // 1
+static const uint64_t SH_FLD_SLAVE16_ERROR_CODE_LEN = 16731; // 1
+static const uint64_t SH_FLD_SLAVE16_RESPONSE_BIT = 16732; // 1
+static const uint64_t SH_FLD_SLAVE17_ERROR_CODE = 16733; // 1
+static const uint64_t SH_FLD_SLAVE17_ERROR_CODE_LEN = 16734; // 1
+static const uint64_t SH_FLD_SLAVE17_RESPONSE_BIT = 16735; // 1
+static const uint64_t SH_FLD_SLAVE18_ERROR_CODE = 16736; // 1
+static const uint64_t SH_FLD_SLAVE18_ERROR_CODE_LEN = 16737; // 1
+static const uint64_t SH_FLD_SLAVE18_RESPONSE_BIT = 16738; // 1
+static const uint64_t SH_FLD_SLAVE19_ERROR_CODE = 16739; // 1
+static const uint64_t SH_FLD_SLAVE19_ERROR_CODE_LEN = 16740; // 1
+static const uint64_t SH_FLD_SLAVE19_RESPONSE_BIT = 16741; // 1
+static const uint64_t SH_FLD_SLAVE1_ERROR_CODE = 16742; // 1
+static const uint64_t SH_FLD_SLAVE1_ERROR_CODE_LEN = 16743; // 1
+static const uint64_t SH_FLD_SLAVE1_RESPONSE_BIT = 16744; // 1
+static const uint64_t SH_FLD_SLAVE20_ERROR_CODE = 16745; // 1
+static const uint64_t SH_FLD_SLAVE20_ERROR_CODE_LEN = 16746; // 1
+static const uint64_t SH_FLD_SLAVE20_RESPONSE_BIT = 16747; // 1
+static const uint64_t SH_FLD_SLAVE21_ERROR_CODE = 16748; // 1
+static const uint64_t SH_FLD_SLAVE21_ERROR_CODE_LEN = 16749; // 1
+static const uint64_t SH_FLD_SLAVE21_RESPONSE_BIT = 16750; // 1
+static const uint64_t SH_FLD_SLAVE22_ERROR_CODE = 16751; // 1
+static const uint64_t SH_FLD_SLAVE22_ERROR_CODE_LEN = 16752; // 1
+static const uint64_t SH_FLD_SLAVE22_RESPONSE_BIT = 16753; // 1
+static const uint64_t SH_FLD_SLAVE23_ERROR_CODE = 16754; // 1
+static const uint64_t SH_FLD_SLAVE23_ERROR_CODE_LEN = 16755; // 1
+static const uint64_t SH_FLD_SLAVE23_RESPONSE_BIT = 16756; // 1
+static const uint64_t SH_FLD_SLAVE24_ERROR_CODE = 16757; // 1
+static const uint64_t SH_FLD_SLAVE24_ERROR_CODE_LEN = 16758; // 1
+static const uint64_t SH_FLD_SLAVE24_RESPONSE_BIT = 16759; // 1
+static const uint64_t SH_FLD_SLAVE25_ERROR_CODE = 16760; // 1
+static const uint64_t SH_FLD_SLAVE25_ERROR_CODE_LEN = 16761; // 1
+static const uint64_t SH_FLD_SLAVE25_RESPONSE_BIT = 16762; // 1
+static const uint64_t SH_FLD_SLAVE26_ERROR_CODE = 16763; // 1
+static const uint64_t SH_FLD_SLAVE26_ERROR_CODE_LEN = 16764; // 1
+static const uint64_t SH_FLD_SLAVE26_RESPONSE_BIT = 16765; // 1
+static const uint64_t SH_FLD_SLAVE27_ERROR_CODE = 16766; // 1
+static const uint64_t SH_FLD_SLAVE27_ERROR_CODE_LEN = 16767; // 1
+static const uint64_t SH_FLD_SLAVE27_RESPONSE_BIT = 16768; // 1
+static const uint64_t SH_FLD_SLAVE28_ERROR_CODE = 16769; // 1
+static const uint64_t SH_FLD_SLAVE28_ERROR_CODE_LEN = 16770; // 1
+static const uint64_t SH_FLD_SLAVE28_RESPONSE_BIT = 16771; // 1
+static const uint64_t SH_FLD_SLAVE29_ERROR_CODE = 16772; // 1
+static const uint64_t SH_FLD_SLAVE29_ERROR_CODE_LEN = 16773; // 1
+static const uint64_t SH_FLD_SLAVE29_RESPONSE_BIT = 16774; // 1
+static const uint64_t SH_FLD_SLAVE2_ERROR_CODE = 16775; // 1
+static const uint64_t SH_FLD_SLAVE2_ERROR_CODE_LEN = 16776; // 1
+static const uint64_t SH_FLD_SLAVE2_RESPONSE_BIT = 16777; // 1
+static const uint64_t SH_FLD_SLAVE30_ERROR_CODE = 16778; // 1
+static const uint64_t SH_FLD_SLAVE30_ERROR_CODE_LEN = 16779; // 1
+static const uint64_t SH_FLD_SLAVE30_RESPONSE_BIT = 16780; // 1
+static const uint64_t SH_FLD_SLAVE31_ERROR_CODE = 16781; // 1
+static const uint64_t SH_FLD_SLAVE31_ERROR_CODE_LEN = 16782; // 1
+static const uint64_t SH_FLD_SLAVE31_RESPONSE_BIT = 16783; // 1
+static const uint64_t SH_FLD_SLAVE32_ERROR_CODE = 16784; // 1
+static const uint64_t SH_FLD_SLAVE32_ERROR_CODE_LEN = 16785; // 1
+static const uint64_t SH_FLD_SLAVE32_RESPONSE_BIT = 16786; // 1
+static const uint64_t SH_FLD_SLAVE33_ERROR_CODE = 16787; // 1
+static const uint64_t SH_FLD_SLAVE33_ERROR_CODE_LEN = 16788; // 1
+static const uint64_t SH_FLD_SLAVE33_RESPONSE_BIT = 16789; // 1
+static const uint64_t SH_FLD_SLAVE34_ERROR_CODE = 16790; // 1
+static const uint64_t SH_FLD_SLAVE34_ERROR_CODE_LEN = 16791; // 1
+static const uint64_t SH_FLD_SLAVE34_RESPONSE_BIT = 16792; // 1
+static const uint64_t SH_FLD_SLAVE35_ERROR_CODE = 16793; // 1
+static const uint64_t SH_FLD_SLAVE35_ERROR_CODE_LEN = 16794; // 1
+static const uint64_t SH_FLD_SLAVE35_RESPONSE_BIT = 16795; // 1
+static const uint64_t SH_FLD_SLAVE36_ERROR_CODE = 16796; // 1
+static const uint64_t SH_FLD_SLAVE36_ERROR_CODE_LEN = 16797; // 1
+static const uint64_t SH_FLD_SLAVE36_RESPONSE_BIT = 16798; // 1
+static const uint64_t SH_FLD_SLAVE37_ERROR_CODE = 16799; // 1
+static const uint64_t SH_FLD_SLAVE37_ERROR_CODE_LEN = 16800; // 1
+static const uint64_t SH_FLD_SLAVE37_RESPONSE_BIT = 16801; // 1
+static const uint64_t SH_FLD_SLAVE38_ERROR_CODE = 16802; // 1
+static const uint64_t SH_FLD_SLAVE38_ERROR_CODE_LEN = 16803; // 1
+static const uint64_t SH_FLD_SLAVE38_RESPONSE_BIT = 16804; // 1
+static const uint64_t SH_FLD_SLAVE39_ERROR_CODE = 16805; // 1
+static const uint64_t SH_FLD_SLAVE39_ERROR_CODE_LEN = 16806; // 1
+static const uint64_t SH_FLD_SLAVE39_RESPONSE_BIT = 16807; // 1
+static const uint64_t SH_FLD_SLAVE3_ERROR_CODE = 16808; // 1
+static const uint64_t SH_FLD_SLAVE3_ERROR_CODE_LEN = 16809; // 1
+static const uint64_t SH_FLD_SLAVE3_RESPONSE_BIT = 16810; // 1
+static const uint64_t SH_FLD_SLAVE40_ERROR_CODE = 16811; // 1
+static const uint64_t SH_FLD_SLAVE40_ERROR_CODE_LEN = 16812; // 1
+static const uint64_t SH_FLD_SLAVE40_RESPONSE_BIT = 16813; // 1
+static const uint64_t SH_FLD_SLAVE41_ERROR_CODE = 16814; // 1
+static const uint64_t SH_FLD_SLAVE41_ERROR_CODE_LEN = 16815; // 1
+static const uint64_t SH_FLD_SLAVE41_RESPONSE_BIT = 16816; // 1
+static const uint64_t SH_FLD_SLAVE42_ERROR_CODE = 16817; // 1
+static const uint64_t SH_FLD_SLAVE42_ERROR_CODE_LEN = 16818; // 1
+static const uint64_t SH_FLD_SLAVE42_RESPONSE_BIT = 16819; // 1
+static const uint64_t SH_FLD_SLAVE43_ERROR_CODE = 16820; // 1
+static const uint64_t SH_FLD_SLAVE43_ERROR_CODE_LEN = 16821; // 1
+static const uint64_t SH_FLD_SLAVE43_RESPONSE_BIT = 16822; // 1
+static const uint64_t SH_FLD_SLAVE44_ERROR_CODE = 16823; // 1
+static const uint64_t SH_FLD_SLAVE44_ERROR_CODE_LEN = 16824; // 1
+static const uint64_t SH_FLD_SLAVE44_RESPONSE_BIT = 16825; // 1
+static const uint64_t SH_FLD_SLAVE45_ERROR_CODE = 16826; // 1
+static const uint64_t SH_FLD_SLAVE45_ERROR_CODE_LEN = 16827; // 1
+static const uint64_t SH_FLD_SLAVE45_RESPONSE_BIT = 16828; // 1
+static const uint64_t SH_FLD_SLAVE46_ERROR_CODE = 16829; // 1
+static const uint64_t SH_FLD_SLAVE46_ERROR_CODE_LEN = 16830; // 1
+static const uint64_t SH_FLD_SLAVE46_RESPONSE_BIT = 16831; // 1
+static const uint64_t SH_FLD_SLAVE47_ERROR_CODE = 16832; // 1
+static const uint64_t SH_FLD_SLAVE47_ERROR_CODE_LEN = 16833; // 1
+static const uint64_t SH_FLD_SLAVE47_RESPONSE_BIT = 16834; // 1
+static const uint64_t SH_FLD_SLAVE48_ERROR_CODE = 16835; // 1
+static const uint64_t SH_FLD_SLAVE48_ERROR_CODE_LEN = 16836; // 1
+static const uint64_t SH_FLD_SLAVE48_RESPONSE_BIT = 16837; // 1
+static const uint64_t SH_FLD_SLAVE49_ERROR_CODE = 16838; // 1
+static const uint64_t SH_FLD_SLAVE49_ERROR_CODE_LEN = 16839; // 1
+static const uint64_t SH_FLD_SLAVE49_RESPONSE_BIT = 16840; // 1
+static const uint64_t SH_FLD_SLAVE4_ERROR_CODE = 16841; // 1
+static const uint64_t SH_FLD_SLAVE4_ERROR_CODE_LEN = 16842; // 1
+static const uint64_t SH_FLD_SLAVE4_RESPONSE_BIT = 16843; // 1
+static const uint64_t SH_FLD_SLAVE50_ERROR_CODE = 16844; // 1
+static const uint64_t SH_FLD_SLAVE50_ERROR_CODE_LEN = 16845; // 1
+static const uint64_t SH_FLD_SLAVE50_RESPONSE_BIT = 16846; // 1
+static const uint64_t SH_FLD_SLAVE51_ERROR_CODE = 16847; // 1
+static const uint64_t SH_FLD_SLAVE51_ERROR_CODE_LEN = 16848; // 1
+static const uint64_t SH_FLD_SLAVE51_RESPONSE_BIT = 16849; // 1
+static const uint64_t SH_FLD_SLAVE52_ERROR_CODE = 16850; // 1
+static const uint64_t SH_FLD_SLAVE52_ERROR_CODE_LEN = 16851; // 1
+static const uint64_t SH_FLD_SLAVE52_RESPONSE_BIT = 16852; // 1
+static const uint64_t SH_FLD_SLAVE53_ERROR_CODE = 16853; // 1
+static const uint64_t SH_FLD_SLAVE53_ERROR_CODE_LEN = 16854; // 1
+static const uint64_t SH_FLD_SLAVE53_RESPONSE_BIT = 16855; // 1
+static const uint64_t SH_FLD_SLAVE54_ERROR_CODE = 16856; // 1
+static const uint64_t SH_FLD_SLAVE54_ERROR_CODE_LEN = 16857; // 1
+static const uint64_t SH_FLD_SLAVE54_RESPONSE_BIT = 16858; // 1
+static const uint64_t SH_FLD_SLAVE55_ERROR_CODE = 16859; // 1
+static const uint64_t SH_FLD_SLAVE55_ERROR_CODE_LEN = 16860; // 1
+static const uint64_t SH_FLD_SLAVE55_RESPONSE_BIT = 16861; // 1
+static const uint64_t SH_FLD_SLAVE56_ERROR_CODE = 16862; // 1
+static const uint64_t SH_FLD_SLAVE56_ERROR_CODE_LEN = 16863; // 1
+static const uint64_t SH_FLD_SLAVE56_RESPONSE_BIT = 16864; // 1
+static const uint64_t SH_FLD_SLAVE57_ERROR_CODE = 16865; // 1
+static const uint64_t SH_FLD_SLAVE57_ERROR_CODE_LEN = 16866; // 1
+static const uint64_t SH_FLD_SLAVE57_RESPONSE_BIT = 16867; // 1
+static const uint64_t SH_FLD_SLAVE58_ERROR_CODE = 16868; // 1
+static const uint64_t SH_FLD_SLAVE58_ERROR_CODE_LEN = 16869; // 1
+static const uint64_t SH_FLD_SLAVE58_RESPONSE_BIT = 16870; // 1
+static const uint64_t SH_FLD_SLAVE59_ERROR_CODE = 16871; // 1
+static const uint64_t SH_FLD_SLAVE59_ERROR_CODE_LEN = 16872; // 1
+static const uint64_t SH_FLD_SLAVE59_RESPONSE_BIT = 16873; // 1
+static const uint64_t SH_FLD_SLAVE5_ERROR_CODE = 16874; // 1
+static const uint64_t SH_FLD_SLAVE5_ERROR_CODE_LEN = 16875; // 1
+static const uint64_t SH_FLD_SLAVE5_RESPONSE_BIT = 16876; // 1
+static const uint64_t SH_FLD_SLAVE60_ERROR_CODE = 16877; // 1
+static const uint64_t SH_FLD_SLAVE60_ERROR_CODE_LEN = 16878; // 1
+static const uint64_t SH_FLD_SLAVE60_RESPONSE_BIT = 16879; // 1
+static const uint64_t SH_FLD_SLAVE61_ERROR_CODE = 16880; // 1
+static const uint64_t SH_FLD_SLAVE61_ERROR_CODE_LEN = 16881; // 1
+static const uint64_t SH_FLD_SLAVE61_RESPONSE_BIT = 16882; // 1
+static const uint64_t SH_FLD_SLAVE62_ERROR_CODE = 16883; // 1
+static const uint64_t SH_FLD_SLAVE62_ERROR_CODE_LEN = 16884; // 1
+static const uint64_t SH_FLD_SLAVE62_RESPONSE_BIT = 16885; // 1
+static const uint64_t SH_FLD_SLAVE63_ERROR_CODE = 16886; // 1
+static const uint64_t SH_FLD_SLAVE63_ERROR_CODE_LEN = 16887; // 1
+static const uint64_t SH_FLD_SLAVE63_RESPONSE_BIT = 16888; // 1
+static const uint64_t SH_FLD_SLAVE6_ERROR_CODE = 16889; // 1
+static const uint64_t SH_FLD_SLAVE6_ERROR_CODE_LEN = 16890; // 1
+static const uint64_t SH_FLD_SLAVE6_RESPONSE_BIT = 16891; // 1
+static const uint64_t SH_FLD_SLAVE7_ERROR_CODE = 16892; // 1
+static const uint64_t SH_FLD_SLAVE7_ERROR_CODE_LEN = 16893; // 1
+static const uint64_t SH_FLD_SLAVE7_RESPONSE_BIT = 16894; // 1
+static const uint64_t SH_FLD_SLAVE8_ERROR_CODE = 16895; // 1
+static const uint64_t SH_FLD_SLAVE8_ERROR_CODE_LEN = 16896; // 1
+static const uint64_t SH_FLD_SLAVE8_RESPONSE_BIT = 16897; // 1
+static const uint64_t SH_FLD_SLAVE9_ERROR_CODE = 16898; // 1
+static const uint64_t SH_FLD_SLAVE9_ERROR_CODE_LEN = 16899; // 1
+static const uint64_t SH_FLD_SLAVE9_RESPONSE_BIT = 16900; // 1
+static const uint64_t SH_FLD_SLAVE_IDLE = 16901; // 1
+static const uint64_t SH_FLD_SLAVE_MODE = 16902; // 43
+static const uint64_t SH_FLD_SLAVE_RESET_TO_405_ENABLE = 16903; // 1
+static const uint64_t SH_FLD_SLBI_GROUP_PUMP_EN = 16904; // 12
+static const uint64_t SH_FLD_SLB_BUS0_STG1_SEL = 16905; // 1
+static const uint64_t SH_FLD_SLB_BUS0_STG2_SEL = 16906; // 1
+static const uint64_t SH_FLD_SLB_BUS1_STG1_SEL = 16907; // 1
+static const uint64_t SH_FLD_SLB_BUS1_STG2_SEL = 16908; // 1
+static const uint64_t SH_FLD_SLB_CAC_PERR_DET = 16909; // 1
+static const uint64_t SH_FLD_SLB_DIR_PERR_DET = 16910; // 1
+static const uint64_t SH_FLD_SLB_LRU_PERR_DET = 16911; // 1
+static const uint64_t SH_FLD_SLB_MULTIHIT_DET = 16912; // 1
+static const uint64_t SH_FLD_SLEWCTL = 16913; // 1
+static const uint64_t SH_FLD_SLEWCTL_LEN = 16914; // 1
+static const uint64_t SH_FLD_SLEW_DN_SEL = 16915; // 6
+static const uint64_t SH_FLD_SLICE = 16916; // 3
+static const uint64_t SH_FLD_SLICE0_CFG_ECC_CE_ERR = 16917; // 2
+static const uint64_t SH_FLD_SLICE0_CFG_ECC_UE_ERR = 16918; // 2
+static const uint64_t SH_FLD_SLICE1_CFG_ECC_CE_ERR = 16919; // 2
+static const uint64_t SH_FLD_SLICE1_CFG_ECC_UE_ERR = 16920; // 2
+static const uint64_t SH_FLD_SLICE2_CFG_ECC_CE_ERR = 16921; // 2
+static const uint64_t SH_FLD_SLICE2_CFG_ECC_UE_ERR = 16922; // 2
+static const uint64_t SH_FLD_SLICE3_CFG_ECC_CE_ERR = 16923; // 2
+static const uint64_t SH_FLD_SLICE3_CFG_ECC_UE_ERR = 16924; // 2
+static const uint64_t SH_FLD_SLICE_LEN = 16925; // 3
+static const uint64_t SH_FLD_SLOT0_B2_VALID = 16926; // 8
+static const uint64_t SH_FLD_SLOT0_D_VALUE = 16927; // 8
+static const uint64_t SH_FLD_SLOT0_M0_VALID = 16928; // 8
+static const uint64_t SH_FLD_SLOT0_M1_VALID = 16929; // 8
+static const uint64_t SH_FLD_SLOT0_ROW15_VALID = 16930; // 8
+static const uint64_t SH_FLD_SLOT0_ROW16_VALID = 16931; // 8
+static const uint64_t SH_FLD_SLOT0_ROW17_VALID = 16932; // 8
+static const uint64_t SH_FLD_SLOT0_S0_VALID = 16933; // 8
+static const uint64_t SH_FLD_SLOT0_S1_VALID = 16934; // 8
+static const uint64_t SH_FLD_SLOT0_S2_VALID = 16935; // 8
+static const uint64_t SH_FLD_SLOT0_VALID = 16936; // 8
+static const uint64_t SH_FLD_SLOT1_B2_VALID = 16937; // 8
+static const uint64_t SH_FLD_SLOT1_D_VALUE = 16938; // 8
+static const uint64_t SH_FLD_SLOT1_M0_VALID = 16939; // 8
+static const uint64_t SH_FLD_SLOT1_M1_VALID = 16940; // 8
+static const uint64_t SH_FLD_SLOT1_ROW15_VALID = 16941; // 8
+static const uint64_t SH_FLD_SLOT1_ROW16_VALID = 16942; // 8
+static const uint64_t SH_FLD_SLOT1_ROW17_VALID = 16943; // 8
+static const uint64_t SH_FLD_SLOT1_S0_VALID = 16944; // 8
+static const uint64_t SH_FLD_SLOT1_S1_VALID = 16945; // 8
+static const uint64_t SH_FLD_SLOT1_S2_VALID = 16946; // 8
+static const uint64_t SH_FLD_SLOT1_VALID = 16947; // 8
+static const uint64_t SH_FLD_SLOW_CMD_RATE = 16948; // 1
+static const uint64_t SH_FLD_SLOW_TO_MODE = 16949; // 86
+static const uint64_t SH_FLD_SLS_CMD_GCRMSG = 16950; // 4
+static const uint64_t SH_FLD_SLS_CMD_GCRMSG_LEN = 16951; // 4
+static const uint64_t SH_FLD_SLS_CNTR_TAP_PTS = 16952; // 4
+static const uint64_t SH_FLD_SLS_CNTR_TAP_PTS_LEN = 16953; // 4
+static const uint64_t SH_FLD_SLS_DISABLE = 16954; // 4
+static const uint64_t SH_FLD_SLS_EXCEPTION2_CS = 16955; // 4
+static const uint64_t SH_FLD_SLS_EXTEND_SEL = 16956; // 4
+static const uint64_t SH_FLD_SLS_EXTEND_SEL_LEN = 16957; // 4
+static const uint64_t SH_FLD_SLS_LANE_GCRMSG = 16958; // 4
+static const uint64_t SH_FLD_SLS_LANE_GCRMSG_LEN = 16959; // 4
+static const uint64_t SH_FLD_SLS_LANE_SEL_LG_GCRMSG = 16960; // 4
+static const uint64_t SH_FLD_SLS_LANE_SHDW_GCRMSG = 16961; // 4
+static const uint64_t SH_FLD_SLS_LANE_UNSEL_LG_GCRMSG = 16962; // 4
+static const uint64_t SH_FLD_SLS_LANE_VAL_GCRMSG = 16963; // 4
+static const uint64_t SH_FLD_SLS_RCVY_DISABLE = 16964; // 4
+static const uint64_t SH_FLD_SLS_SCRAMBLE_MODE = 16965; // 4
+static const uint64_t SH_FLD_SLS_SCRAMBLE_MODE_LEN = 16966; // 4
+static const uint64_t SH_FLD_SLS_TIMEOUT_SEL = 16967; // 4
+static const uint64_t SH_FLD_SLS_TIMEOUT_SEL_LEN = 16968; // 4
+static const uint64_t SH_FLD_SLV_DIS_ABUSPAR = 16969; // 1
+static const uint64_t SH_FLD_SLV_DIS_BE = 16970; // 1
+static const uint64_t SH_FLD_SLV_DIS_BEPAR = 16971; // 1
+static const uint64_t SH_FLD_SLV_DIS_RDDBUSPAREN = 16972; // 1
+static const uint64_t SH_FLD_SLV_DIS_SACK = 16973; // 1
+static const uint64_t SH_FLD_SLV_DIS_WRDBUSPAR = 16974; // 1
+static const uint64_t SH_FLD_SLV_EVENT_MUX = 16975; // 1
+static const uint64_t SH_FLD_SLV_EVENT_MUX_LEN = 16976; // 1
+static const uint64_t SH_FLD_SLV_LGL_RPR_REQ_GCRMSG = 16977; // 4
+static const uint64_t SH_FLD_SLV_MV_SLS_RPR_REQ_GCRMSG = 16978; // 4
+static const uint64_t SH_FLD_SLV_MV_SLS_SHDW_REQ_GCRMSG = 16979; // 4
+static const uint64_t SH_FLD_SLV_MV_SLS_SHDW_RPR_REQ_GCRMSG = 16980; // 4
+static const uint64_t SH_FLD_SLV_MV_SLS_UNSHDW_REQ_GCRMSG = 16981; // 4
+static const uint64_t SH_FLD_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG = 16982; // 4
+static const uint64_t SH_FLD_SLV_RECAL_ABORT_ACK_FIN_GCRMSG = 16983; // 4
+static const uint64_t SH_FLD_SLV_RECAL_ABORT_MNOP_FIN_GCRMSG = 16984; // 4
+static const uint64_t SH_FLD_SLV_RECAL_ABORT_SNOP_FIN_GCRMSG = 16985; // 4
+static const uint64_t SH_FLD_SLV_RECAL_DONE_NOP_FIN_GCRMSG = 16986; // 4
+static const uint64_t SH_FLD_SLV_RECAL_FAIL_NOP_FIN_GCRMSG = 16987; // 4
+static const uint64_t SH_FLD_SLV_RECAL_FRESULTS_FIN_GCRMSG = 16988; // 4
+static const uint64_t SH_FLD_SLV_SHDW_DONE_FIN_GCRMSG = 16989; // 4
+static const uint64_t SH_FLD_SLV_SHDW_NOP_FIN_GCRMSG = 16990; // 4
+static const uint64_t SH_FLD_SLV_SHDW_RPR_DONE_FIN_GCRMSG = 16991; // 4
+static const uint64_t SH_FLD_SLV_SHDW_RPR_NOP_FIN_GCRMSG = 16992; // 4
+static const uint64_t SH_FLD_SLV_SPARE = 16993; // 1
+static const uint64_t SH_FLD_SLV_UNSHDW_DONE_FIN_GCRMSG = 16994; // 4
+static const uint64_t SH_FLD_SLV_UNSHDW_NOP_FIN_GCRMSG = 16995; // 4
+static const uint64_t SH_FLD_SLV_UNSHDW_RPR_DONE_FIN_GCRMSG = 16996; // 4
+static const uint64_t SH_FLD_SLV_UNSHDW_RPR_NOP_FIN_GCRMSG = 16997; // 4
+static const uint64_t SH_FLD_SL_UE_CRC_ERR = 16998; // 5
+static const uint64_t SH_FLD_SMALL_EVENT_PROFILE_CTR = 16999; // 12
+static const uint64_t SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN = 17000; // 12
+static const uint64_t SH_FLD_SMALL_EVENT_THRESHOLD = 17001; // 12
+static const uint64_t SH_FLD_SMALL_EVENT_THRESHOLD_LEN = 17002; // 12
+static const uint64_t SH_FLD_SMALL_STEP = 17003; // 8
+static const uint64_t SH_FLD_SMALL_STEP_LEN = 17004; // 8
+static const uint64_t SH_FLD_SMASK_IN0 = 17005; // 43
+static const uint64_t SH_FLD_SMASK_IN1 = 17006; // 43
+static const uint64_t SH_FLD_SMASK_IN2 = 17007; // 43
+static const uint64_t SH_FLD_SMASK_IN3 = 17008; // 43
+static const uint64_t SH_FLD_SMASK_IN4 = 17009; // 43
+static const uint64_t SH_FLD_SM_1HOT_ERR = 17010; // 16
+static const uint64_t SH_FLD_SM_MMIO0 = 17011; // 3
+static const uint64_t SH_FLD_SM_MMIO1 = 17012; // 3
+static const uint64_t SH_FLD_SM_MMIO2 = 17013; // 3
+static const uint64_t SH_FLD_SM_MMIO3 = 17014; // 3
+static const uint64_t SH_FLD_SM_OR_CASE = 17015; // 2
+static const uint64_t SH_FLD_SM_RESET = 17016; // 1
+static const uint64_t SH_FLD_SN0_CRESP_ATAG_P = 17017; // 12
+static const uint64_t SH_FLD_SN0_CRESP_TTAG_P = 17018; // 12
+static const uint64_t SH_FLD_SN0_RCMD_ADDR_P = 17019; // 12
+static const uint64_t SH_FLD_SN0_RCMD_TTAG_P = 17020; // 12
+static const uint64_t SH_FLD_SN1_CRESP_ATAG_P = 17021; // 12
+static const uint64_t SH_FLD_SN1_CRESP_TTAG_P = 17022; // 12
+static const uint64_t SH_FLD_SN1_RCMD_ADDR_P = 17023; // 12
+static const uint64_t SH_FLD_SN1_RCMD_TTAG_P = 17024; // 12
+static const uint64_t SH_FLD_SN2_CRESP_ATAG_P = 17025; // 12
+static const uint64_t SH_FLD_SN2_CRESP_TTAG_P = 17026; // 12
+static const uint64_t SH_FLD_SN2_RCMD_ADDR_P = 17027; // 12
+static const uint64_t SH_FLD_SN2_RCMD_TTAG_P = 17028; // 12
+static const uint64_t SH_FLD_SN3_CRESP_ATAG_P = 17029; // 12
+static const uint64_t SH_FLD_SN3_CRESP_TTAG_P = 17030; // 12
+static const uint64_t SH_FLD_SN3_RCMD_ADDR_P = 17031; // 12
+static const uint64_t SH_FLD_SN3_RCMD_TTAG_P = 17032; // 12
+static const uint64_t SH_FLD_SND_CHIPID = 17033; // 1
+static const uint64_t SH_FLD_SND_CHIPID_LEN = 17034; // 1
+static const uint64_t SH_FLD_SND_CNT = 17035; // 1
+static const uint64_t SH_FLD_SND_CNT_LEN = 17036; // 1
+static const uint64_t SH_FLD_SND_CNT_STATUS = 17037; // 1
+static const uint64_t SH_FLD_SND_CNT_STATUS_LEN = 17038; // 1
+static const uint64_t SH_FLD_SND_ERROR = 17039; // 1
+static const uint64_t SH_FLD_SND_GROUPID = 17040; // 1
+static const uint64_t SH_FLD_SND_GROUPID_LEN = 17041; // 1
+static const uint64_t SH_FLD_SND_IN_PROGRESS = 17042; // 1
+static const uint64_t SH_FLD_SND_PHASE_STATUS = 17043; // 1
+static const uint64_t SH_FLD_SND_PHASE_STATUS_LEN = 17044; // 1
+static const uint64_t SH_FLD_SND_QID = 17045; // 1
+static const uint64_t SH_FLD_SND_RESERVATION = 17046; // 1
+static const uint64_t SH_FLD_SND_RESET = 17047; // 1
+static const uint64_t SH_FLD_SND_RETRY_COUNT = 17048; // 1
+static const uint64_t SH_FLD_SND_RETRY_COUNT_LEN = 17049; // 1
+static const uint64_t SH_FLD_SND_RETRY_COUNT_OVERCOM = 17050; // 1
+static const uint64_t SH_FLD_SND_RETRY_THRESH = 17051; // 1
+static const uint64_t SH_FLD_SND_RETRY_THRESH_LEN = 17052; // 1
+static const uint64_t SH_FLD_SND_RSVTO_DIV = 17053; // 1
+static const uint64_t SH_FLD_SND_RSVTO_DIV_LEN = 17054; // 1
+static const uint64_t SH_FLD_SND_SCOPE = 17055; // 1
+static const uint64_t SH_FLD_SND_SCOPE_LEN = 17056; // 1
+static const uint64_t SH_FLD_SND_SLS_CMD_GCRMSG = 17057; // 4
+static const uint64_t SH_FLD_SND_SLS_CMD_PREV_GCRMSG = 17058; // 4
+static const uint64_t SH_FLD_SND_SLS_USING_REG_SCRAMBLE = 17059; // 4
+static const uint64_t SH_FLD_SND_STOP = 17060; // 1
+static const uint64_t SH_FLD_SND_TYPE = 17061; // 1
+static const uint64_t SH_FLD_SNFSM_ADDR = 17062; // 12
+static const uint64_t SH_FLD_SNGL_THD_EN = 17063; // 2
+static const uint64_t SH_FLD_SNOOPER_RECOVERABLE_ERROR = 17064; // 4
+static const uint64_t SH_FLD_SNOOPER_SYS_XSTOP_ERROR = 17065; // 4
+static const uint64_t SH_FLD_SNOOP_ARRAY_CE = 17066; // 4
+static const uint64_t SH_FLD_SNOOP_ARRAY_UE = 17067; // 4
+static const uint64_t SH_FLD_SNOOP_DIS = 17068; // 8
+static const uint64_t SH_FLD_SNOP = 17069; // 43
+static const uint64_t SH_FLD_SNOP_FORCE_SG = 17070; // 43
+static const uint64_t SH_FLD_SNOP_LEN = 17071; // 43
+static const uint64_t SH_FLD_SNOP_WAIT = 17072; // 43
+static const uint64_t SH_FLD_SNOP_WAIT_LEN = 17073; // 43
+static const uint64_t SH_FLD_SNPBE_TRIGGER_ENABLE = 17074; // 2
+static const uint64_t SH_FLD_SNPBE_UOP_TRIGGER_ENABLE = 17075; // 2
+static const uint64_t SH_FLD_SNPFE_DIR_TRIGGER_ENABLE = 17076; // 2
+static const uint64_t SH_FLD_SNPFE_TRIGGER_ENABLE = 17077; // 2
+static const uint64_t SH_FLD_SNP_ERROR_INJECT_ENABLE = 17078; // 2
+static const uint64_t SH_FLD_SNP_ERROR_INJECT_TARGET = 17079; // 2
+static const uint64_t SH_FLD_SNP_ERROR_INJECT_TARGET_LEN = 17080; // 2
+static const uint64_t SH_FLD_SNP_INJECT_CONTINOUS_ERROR = 17081; // 2
+static const uint64_t SH_FLD_SNP_INJECT_DBL_ECC_ERROR = 17082; // 2
+static const uint64_t SH_FLD_SNP_MUX_PORT_SEL = 17083; // 2
+static const uint64_t SH_FLD_SNP_MUX_PORT_SEL_LEN = 17084; // 2
+static const uint64_t SH_FLD_SNP_REG_ERR0 = 17085; // 1
+static const uint64_t SH_FLD_SNP_REG_ERR1 = 17086; // 1
+static const uint64_t SH_FLD_SNP_REG_ERR2 = 17087; // 1
+static const uint64_t SH_FLD_SNP_REG_ERR3 = 17088; // 1
+static const uint64_t SH_FLD_SNP_REG_ERR4 = 17089; // 1
+static const uint64_t SH_FLD_SNP_REG_ERR5 = 17090; // 1
+static const uint64_t SH_FLD_SNP_REG_ERR6 = 17091; // 1
+static const uint64_t SH_FLD_SNS1_UNUSED_0_31 = 17092; // 1
+static const uint64_t SH_FLD_SNS1_UNUSED_0_31_LEN = 17093; // 1
+static const uint64_t SH_FLD_SNS2_UNUSED_0_31 = 17094; // 1
+static const uint64_t SH_FLD_SNS2_UNUSED_0_31_LEN = 17095; // 1
+static const uint64_t SH_FLD_SN_CRESP_ACK_DEAD = 17096; // 12
+static const uint64_t SH_FLD_SN_MACHINE_HANG = 17097; // 12
+static const uint64_t SH_FLD_SN_MSG_MAX_CREDIT = 17098; // 2
+static const uint64_t SH_FLD_SN_MSG_MAX_CREDIT_LEN = 17099; // 2
+static const uint64_t SH_FLD_SN_SC_RDATA_PARITY_ERRHOLD = 17100; // 2
+static const uint64_t SH_FLD_SN_UNSOLICITED_CRESP = 17101; // 12
+static const uint64_t SH_FLD_SN_WRT_DBUF_MAX_CREDIT = 17102; // 2
+static const uint64_t SH_FLD_SN_WRT_DBUF_MAX_CREDIT_LEN = 17103; // 2
+static const uint64_t SH_FLD_SOCKET = 17104; // 1
+static const uint64_t SH_FLD_SOCKET_LEN = 17105; // 1
+static const uint64_t SH_FLD_SOFT_CE_COUNT = 17106; // 2
+static const uint64_t SH_FLD_SOFT_CE_COUNT_LEN = 17107; // 2
+static const uint64_t SH_FLD_SOFT_MCE_COUNT = 17108; // 2
+static const uint64_t SH_FLD_SOFT_MCE_COUNT_LEN = 17109; // 2
+static const uint64_t SH_FLD_SOFT_NCE_ETE_ATTN = 17110; // 2
+static const uint64_t SH_FLD_SOURCE_SELECT = 17111; // 43
+static const uint64_t SH_FLD_SOURCE_SELECT_LEN = 17112; // 43
+static const uint64_t SH_FLD_SOURCE_SUBUNIT_0_1 = 17113; // 1
+static const uint64_t SH_FLD_SOURCE_SUBUNIT_0_1_LEN = 17114; // 1
+static const uint64_t SH_FLD_SOUTH_CTL_CQ_IDLE_BIT = 17115; // 1
+static const uint64_t SH_FLD_SOUTH_CTL_DISABLE_WC_ECC = 17116; // 1
+static const uint64_t SH_FLD_SOUTH_CTL_DISABLE_WC_SCRUB = 17117; // 1
+static const uint64_t SH_FLD_SOUTH_CTL_DIS_SIMULT_RD_WR = 17118; // 1
+static const uint64_t SH_FLD_SOUTH_CTL_EG_IDLE_BIT = 17119; // 1
+static const uint64_t SH_FLD_SOUTH_CTL_EG_SINGLE_THREAD = 17120; // 1
+static const uint64_t SH_FLD_SOUTH_CTL_EG_STAMP_DEBUG = 17121; // 1
+static const uint64_t SH_FLD_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE = 17122; // 1
+static const uint64_t SH_FLD_SOUTH_CTL_ENA_NOTIFY_ORDER = 17123; // 1
+static const uint64_t SH_FLD_SOUTH_CTL_EN_FAST_SCRUB = 17124; // 1
+static const uint64_t SH_FLD_SOUTH_CTL_UNUSED = 17125; // 1
+static const uint64_t SH_FLD_SOUTH_CTL_UNUSED_LEN = 17126; // 1
+static const uint64_t SH_FLD_SOUTH_CTL_WC_IDLE_BIT = 17127; // 1
+static const uint64_t SH_FLD_SPARE = 17128; // 87
+static const uint64_t SH_FLD_SPARE0 = 17129; // 105
+static const uint64_t SH_FLD_SPARE0_LEN = 17130; // 8
+static const uint64_t SH_FLD_SPARE1 = 17131; // 5
+static const uint64_t SH_FLD_SPARE10 = 17132; // 1
+static const uint64_t SH_FLD_SPARE11 = 17133; // 14
+static const uint64_t SH_FLD_SPARE13 = 17134; // 1
+static const uint64_t SH_FLD_SPARE14 = 17135; // 1
+static const uint64_t SH_FLD_SPARE15 = 17136; // 1
+static const uint64_t SH_FLD_SPARE2 = 17137; // 4
+static const uint64_t SH_FLD_SPARE3 = 17138; // 1
+static const uint64_t SH_FLD_SPARE41_43 = 17139; // 24
+static const uint64_t SH_FLD_SPARE41_43_LEN = 17140; // 24
+static const uint64_t SH_FLD_SPARE4_TIMEOUT = 17141; // 6
+static const uint64_t SH_FLD_SPARE4_TIMEOUT_LEN = 17142; // 6
+static const uint64_t SH_FLD_SPARE7 = 17143; // 1
+static const uint64_t SH_FLD_SPARE8 = 17144; // 1
+static const uint64_t SH_FLD_SPARE9 = 17145; // 1
+static const uint64_t SH_FLD_SPARED = 17146; // 4
+static const uint64_t SH_FLD_SPARED_LEN = 17147; // 4
+static const uint64_t SH_FLD_SPARES = 17148; // 3
+static const uint64_t SH_FLD_SPARES1 = 17149; // 4
+static const uint64_t SH_FLD_SPARES1_LEN = 17150; // 4
+static const uint64_t SH_FLD_SPARES2 = 17151; // 4
+static const uint64_t SH_FLD_SPARES2_LEN = 17152; // 4
+static const uint64_t SH_FLD_SPARES_LEN = 17153; // 3
+static const uint64_t SH_FLD_SPARE_0 = 17154; // 4
+static const uint64_t SH_FLD_SPARE_0_LEN = 17155; // 4
+static const uint64_t SH_FLD_SPARE_10 = 17156; // 2
+static const uint64_t SH_FLD_SPARE_11 = 17157; // 5
+static const uint64_t SH_FLD_SPARE_12 = 17158; // 4
+static const uint64_t SH_FLD_SPARE_13 = 17159; // 4
+static const uint64_t SH_FLD_SPARE_14 = 17160; // 4
+static const uint64_t SH_FLD_SPARE_15 = 17161; // 16
+static const uint64_t SH_FLD_SPARE_16 = 17162; // 14
+static const uint64_t SH_FLD_SPARE_17 = 17163; // 14
+static const uint64_t SH_FLD_SPARE_18 = 17164; // 2
+static const uint64_t SH_FLD_SPARE_18_19 = 17165; // 6
+static const uint64_t SH_FLD_SPARE_18_19_LEN = 17166; // 6
+static const uint64_t SH_FLD_SPARE_19 = 17167; // 4
+static const uint64_t SH_FLD_SPARE_1_3 = 17168; // 1
+static const uint64_t SH_FLD_SPARE_1_3_LEN = 17169; // 1
+static const uint64_t SH_FLD_SPARE_2 = 17170; // 4
+static const uint64_t SH_FLD_SPARE_20 = 17171; // 4
+static const uint64_t SH_FLD_SPARE_21 = 17172; // 4
+static const uint64_t SH_FLD_SPARE_22 = 17173; // 4
+static const uint64_t SH_FLD_SPARE_22_23 = 17174; // 12
+static const uint64_t SH_FLD_SPARE_22_23_LEN = 17175; // 12
+static const uint64_t SH_FLD_SPARE_23 = 17176; // 4
+static const uint64_t SH_FLD_SPARE_24 = 17177; // 4
+static const uint64_t SH_FLD_SPARE_24_31 = 17178; // 1
+static const uint64_t SH_FLD_SPARE_24_31_LEN = 17179; // 1
+static const uint64_t SH_FLD_SPARE_25 = 17180; // 4
+static const uint64_t SH_FLD_SPARE_26 = 17181; // 4
+static const uint64_t SH_FLD_SPARE_27 = 17182; // 4
+static const uint64_t SH_FLD_SPARE_28 = 17183; // 4
+static const uint64_t SH_FLD_SPARE_29 = 17184; // 4
+static const uint64_t SH_FLD_SPARE_2_MASK = 17185; // 1
+static const uint64_t SH_FLD_SPARE_3 = 17186; // 6
+static const uint64_t SH_FLD_SPARE_30 = 17187; // 4
+static const uint64_t SH_FLD_SPARE_31 = 17188; // 5
+static const uint64_t SH_FLD_SPARE_32_33 = 17189; // 12
+static const uint64_t SH_FLD_SPARE_32_33_LEN = 17190; // 12
+static const uint64_t SH_FLD_SPARE_3_MASK = 17191; // 1
+static const uint64_t SH_FLD_SPARE_58 = 17192; // 4
+static const uint64_t SH_FLD_SPARE_59 = 17193; // 4
+static const uint64_t SH_FLD_SPARE_59_61 = 17194; // 2
+static const uint64_t SH_FLD_SPARE_59_61_LEN = 17195; // 2
+static const uint64_t SH_FLD_SPARE_60 = 17196; // 4
+static const uint64_t SH_FLD_SPARE_61 = 17197; // 4
+static const uint64_t SH_FLD_SPARE_63 = 17198; // 3
+static const uint64_t SH_FLD_SPARE_6_7 = 17199; // 16
+static const uint64_t SH_FLD_SPARE_6_7_LEN = 17200; // 16
+static const uint64_t SH_FLD_SPARE_8 = 17201; // 2
+static const uint64_t SH_FLD_SPARE_8_11 = 17202; // 6
+static const uint64_t SH_FLD_SPARE_8_11_LEN = 17203; // 6
+static const uint64_t SH_FLD_SPARE_9 = 17204; // 2
+static const uint64_t SH_FLD_SPARE_DI_CONTROL = 17205; // 3
+static const uint64_t SH_FLD_SPARE_ERR_38 = 17206; // 1
+static const uint64_t SH_FLD_SPARE_ERR_38_MASK = 17207; // 1
+static const uint64_t SH_FLD_SPARE_FENCE_CONTROL = 17208; // 3
+static const uint64_t SH_FLD_SPARE_FILT0_PLL = 17209; // 3
+static const uint64_t SH_FLD_SPARE_FILT1_PLL = 17210; // 3
+static const uint64_t SH_FLD_SPARE_LEN = 17211; // 57
+static const uint64_t SH_FLD_SPARE_MODE_0 = 17212; // 116
+static const uint64_t SH_FLD_SPARE_MODE_1 = 17213; // 116
+static const uint64_t SH_FLD_SPARE_MODE_2 = 17214; // 116
+static const uint64_t SH_FLD_SPARE_MODE_3 = 17215; // 116
+static const uint64_t SH_FLD_SPARE_N = 17216; // 2
+static const uint64_t SH_FLD_SPARE_N_LEN = 17217; // 2
+static const uint64_t SH_FLD_SPARE_PIB_CONTROL = 17218; // 3
+static const uint64_t SH_FLD_SPARE_RI_CONTROL = 17219; // 3
+static const uint64_t SH_FLD_SPECIAL_ATTENTION = 17220; // 1
+static const uint64_t SH_FLD_SPECIAL_WAKEUP_C0 = 17221; // 24
+static const uint64_t SH_FLD_SPECIAL_WAKEUP_C1 = 17222; // 24
+static const uint64_t SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 17223; // 12
+static const uint64_t SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 17224; // 12
+static const uint64_t SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE = 17225; // 12
+static const uint64_t SH_FLD_SPECIAL_WKUP_DONE_C0 = 17226; // 12
+static const uint64_t SH_FLD_SPECIAL_WKUP_DONE_C1 = 17227; // 12
+static const uint64_t SH_FLD_SPECIAL_WKUP_PROTOCOL = 17228; // 30
+static const uint64_t SH_FLD_SPECULATIVE_CHECKIN_COUNT = 17229; // 1
+static const uint64_t SH_FLD_SPECULATIVE_CHECKIN_COUNT_LEN = 17230; // 1
+static const uint64_t SH_FLD_SPEC_CILD_G = 17231; // 1
+static const uint64_t SH_FLD_SPEC_HPC_DIR_STATE = 17232; // 2
+static const uint64_t SH_FLD_SPEC_HPC_DIR_STATE_LEN = 17233; // 2
+static const uint64_t SH_FLD_SPEC_READ_FILTER_NO_HASH_MODE = 17234; // 4
+static const uint64_t SH_FLD_SPEDIV = 17235; // 20
+static const uint64_t SH_FLD_SPEDIV_LEN = 17236; // 20
+static const uint64_t SH_FLD_SPEED_SELECT = 17237; // 2
+static const uint64_t SH_FLD_SPEED_SELECT_LEN = 17238; // 2
+static const uint64_t SH_FLD_SPLURGE = 17239; // 1
+static const uint64_t SH_FLD_SPRG0 = 17240; // 21
+static const uint64_t SH_FLD_SPRG0_LEN = 17241; // 21
+static const uint64_t SH_FLD_SPR_LNS_PDWN_LITE_GCRMSG = 17242; // 4
+static const uint64_t SH_FLD_SP_COUNT_LT = 17243; // 86
+static const uint64_t SH_FLD_SP_COUNT_LT_LEN = 17244; // 86
+static const uint64_t SH_FLD_SQ_LFSR_CNTL = 17245; // 8
+static const uint64_t SH_FLD_SQ_LFSR_CNTL_LEN = 17246; // 8
+static const uint64_t SH_FLD_SR = 17247; // 8
+static const uint64_t SH_FLD_SRAM_ABIST_DONE_DC = 17248; // 43
+static const uint64_t SH_FLD_SRAM_ACCESS_MODE = 17249; // 16
+static const uint64_t SH_FLD_SRAM_ADDRESS = 17250; // 16
+static const uint64_t SH_FLD_SRAM_ADDRESS_LEN = 17251; // 16
+static const uint64_t SH_FLD_SRAM_CE = 17252; // 13
+static const uint64_t SH_FLD_SRAM_CERRRPT = 17253; // 1
+static const uint64_t SH_FLD_SRAM_CERRRPT_LEN = 17254; // 1
+static const uint64_t SH_FLD_SRAM_DATA = 17255; // 16
+static const uint64_t SH_FLD_SRAM_DATA_LEN = 17256; // 16
+static const uint64_t SH_FLD_SRAM_HIGH_PRIORITY = 17257; // 4
+static const uint64_t SH_FLD_SRAM_HIGH_PRIORITY_LEN = 17258; // 4
+static const uint64_t SH_FLD_SRAM_LOW_PRIORITY = 17259; // 4
+static const uint64_t SH_FLD_SRAM_LOW_PRIORITY_LEN = 17260; // 4
+static const uint64_t SH_FLD_SRAM_SCRUB_ENABLE = 17261; // 16
+static const uint64_t SH_FLD_SRAM_SCRUB_ERR = 17262; // 13
+static const uint64_t SH_FLD_SRAM_SCRUB_INDEX = 17263; // 16
+static const uint64_t SH_FLD_SRAM_SCRUB_INDEX_LEN = 17264; // 16
+static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR0 = 17265; // 1
+static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR0_MASK = 17266; // 1
+static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR1 = 17267; // 1
+static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR1_MASK = 17268; // 1
+static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR2 = 17269; // 1
+static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR2_MASK = 17270; // 1
+static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR3 = 17271; // 1
+static const uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR3_MASK = 17272; // 1
+static const uint64_t SH_FLD_SRAM_UE = 17273; // 13
+static const uint64_t SH_FLD_SRC_BUS = 17274; // 24
+static const uint64_t SH_FLD_SRC_BUS_LEN = 17275; // 24
+static const uint64_t SH_FLD_SRC_DDE = 17276; // 3
+static const uint64_t SH_FLD_SRC_DDE_LEN = 17277; // 3
+static const uint64_t SH_FLD_SRC_SEL_EQ1_ERR = 17278; // 1
+static const uint64_t SH_FLD_SRQ_CCS_UNEXPECTED_PORT_ACTIVE_HOLD_OUT = 17279; // 2
+static const uint64_t SH_FLD_SRQ_MCBIST_OUT_OF_SYNC_HOLD_OUT = 17280; // 2
+static const uint64_t SH_FLD_SRT_CE = 17281; // 1
+static const uint64_t SH_FLD_SRT_CE_MASK = 17282; // 1
+static const uint64_t SH_FLD_SRT_DATAOUT_PERR = 17283; // 1
+static const uint64_t SH_FLD_SRT_DATAOUT_PERR_MASK = 17284; // 1
+static const uint64_t SH_FLD_SRT_ERROR = 17285; // 1
+static const uint64_t SH_FLD_SRT_FSM_ERR = 17286; // 1
+static const uint64_t SH_FLD_SRT_FSM_ERR_MASK = 17287; // 1
+static const uint64_t SH_FLD_SRT_OCI_ADDR_PARITY_ERR = 17288; // 1
+static const uint64_t SH_FLD_SRT_OCI_ADDR_PARITY_ERR_MASK = 17289; // 1
+static const uint64_t SH_FLD_SRT_OCI_BE_PARITY_ERR = 17290; // 1
+static const uint64_t SH_FLD_SRT_OCI_BE_PARITY_ERR_MASK = 17291; // 1
+static const uint64_t SH_FLD_SRT_OCI_WRITE_DATA_PARITY = 17292; // 1
+static const uint64_t SH_FLD_SRT_OCI_WRITE_DATA_PARITY_MASK = 17293; // 1
+static const uint64_t SH_FLD_SRT_READ_ERROR = 17294; // 1
+static const uint64_t SH_FLD_SRT_READ_ERROR_MASK = 17295; // 1
+static const uint64_t SH_FLD_SRT_UE = 17296; // 1
+static const uint64_t SH_FLD_SRT_UE_MASK = 17297; // 1
+static const uint64_t SH_FLD_SRT_WRITE_ERROR = 17298; // 1
+static const uint64_t SH_FLD_SRT_WRITE_ERROR_MASK = 17299; // 1
+static const uint64_t SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL = 17300; // 4
+static const uint64_t SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL_LEN = 17301; // 4
+static const uint64_t SH_FLD_SR_LEN = 17302; // 8
+static const uint64_t SH_FLD_SSA_ECC_HI_CE_ERRHOLD = 17303; // 2
+static const uint64_t SH_FLD_SSA_ECC_HI_SUE_ERRHOLD = 17304; // 2
+static const uint64_t SH_FLD_SSA_ECC_HI_UE_ERRHOLD = 17305; // 2
+static const uint64_t SH_FLD_SSA_ECC_LO_CE_ERRHOLD = 17306; // 2
+static const uint64_t SH_FLD_SSA_ECC_LO_SUE_ERRHOLD = 17307; // 2
+static const uint64_t SH_FLD_SSA_ECC_LO_UE_ERRHOLD = 17308; // 2
+static const uint64_t SH_FLD_SSCGEN = 17309; // 3
+static const uint64_t SH_FLD_SS_ENABLE = 17310; // 6
+static const uint64_t SH_FLD_ST2_RESET_PERIOD = 17311; // 1
+static const uint64_t SH_FLD_ST2_RESET_PERIOD_LEN = 17312; // 1
+static const uint64_t SH_FLD_STACK = 17313; // 16
+static const uint64_t SH_FLD_STACK_LEN = 17314; // 16
+static const uint64_t SH_FLD_STAGGERED_PATTERN = 17315; // 8
+static const uint64_t SH_FLD_START = 17316; // 59
+static const uint64_t SH_FLD_START0 = 17317; // 5
+static const uint64_t SH_FLD_START1 = 17318; // 5
+static const uint64_t SH_FLD_STARTING_ADDRESS = 17319; // 4
+static const uint64_t SH_FLD_STARTING_ADDRESS_LEN = 17320; // 4
+static const uint64_t SH_FLD_STARTS_BIST = 17321; // 43
+static const uint64_t SH_FLD_START_BOOT_SEQUENCER = 17322; // 1
+static const uint64_t SH_FLD_START_DC_CALIBRATE = 17323; // 4
+static const uint64_t SH_FLD_START_DESKEW = 17324; // 4
+static const uint64_t SH_FLD_START_EYE_OPT = 17325; // 4
+static const uint64_t SH_FLD_START_FUNC_MODE = 17326; // 4
+static const uint64_t SH_FLD_START_INIT = 17327; // 8
+static const uint64_t SH_FLD_START_JTAG_CMD = 17328; // 1
+static const uint64_t SH_FLD_START_LANE_ID = 17329; // 8
+static const uint64_t SH_FLD_START_LANE_ID_LEN = 17330; // 8
+static const uint64_t SH_FLD_START_LEN = 17331; // 36
+static const uint64_t SH_FLD_START_PPE_ADDR = 17332; // 4
+static const uint64_t SH_FLD_START_PPE_ADDR_LEN = 17333; // 4
+static const uint64_t SH_FLD_START_READ = 17334; // 1
+static const uint64_t SH_FLD_START_REPAIR = 17335; // 4
+static const uint64_t SH_FLD_START_RESTART_VECTOR0 = 17336; // 1
+static const uint64_t SH_FLD_START_RESTART_VECTOR1 = 17337; // 1
+static const uint64_t SH_FLD_START_SEEPROM_ADDRESS = 17338; // 4
+static const uint64_t SH_FLD_START_SEEPROM_ADDRESS_LEN = 17339; // 4
+static const uint64_t SH_FLD_START_WIRETEST = 17340; // 4
+static const uint64_t SH_FLD_START_WRITE = 17341; // 1
+static const uint64_t SH_FLD_START_WR_ADDR = 17342; // 2
+static const uint64_t SH_FLD_START_WR_ADDR_LEN = 17343; // 2
+static const uint64_t SH_FLD_STAT = 17344; // 2
+static const uint64_t SH_FLD_STATE = 17345; // 44
+static const uint64_t SH_FLD_STATE_LEN = 17346; // 43
+static const uint64_t SH_FLD_STATE_LOSS_ENABLE_A_N = 17347; // 96
+static const uint64_t SH_FLD_STATE_MACHINE_TRANSITION_DELAY = 17348; // 1
+static const uint64_t SH_FLD_STATE_MACHINE_TRANSITION_DELAY_LEN = 17349; // 1
+static const uint64_t SH_FLD_STATIC_MAX_SPARES_EXCEEDED = 17350; // 8
+static const uint64_t SH_FLD_STATIC_SPARE_DEPLOYED = 17351; // 8
+static const uint64_t SH_FLD_STATUS = 17352; // 5
+static const uint64_t SH_FLD_STATUS_INVALID_CRESP = 17353; // 2
+static const uint64_t SH_FLD_STATUS_LEN = 17354; // 2
+static const uint64_t SH_FLD_STATUS_PARITY_ERROR = 17355; // 2
+static const uint64_t SH_FLD_STATUS_PERV = 17356; // 129
+static const uint64_t SH_FLD_STATUS_REC_DROPPED_Q = 17357; // 26
+static const uint64_t SH_FLD_STATUS_REG = 17358; // 1
+static const uint64_t SH_FLD_STATUS_REG_LEN = 17359; // 1
+static const uint64_t SH_FLD_STATUS_SCOM_ERROR = 17360; // 26
+static const uint64_t SH_FLD_STATUS_TRIG_DROPPED_Q = 17361; // 26
+static const uint64_t SH_FLD_STATUS_UNIT1 = 17362; // 129
+static const uint64_t SH_FLD_STATUS_UNIT10 = 17363; // 129
+static const uint64_t SH_FLD_STATUS_UNIT2 = 17364; // 129
+static const uint64_t SH_FLD_STATUS_UNIT3 = 17365; // 129
+static const uint64_t SH_FLD_STATUS_UNIT4 = 17366; // 129
+static const uint64_t SH_FLD_STATUS_UNIT5 = 17367; // 129
+static const uint64_t SH_FLD_STATUS_UNIT6 = 17368; // 129
+static const uint64_t SH_FLD_STATUS_UNIT7 = 17369; // 129
+static const uint64_t SH_FLD_STATUS_UNIT8 = 17370; // 129
+static const uint64_t SH_FLD_STATUS_UNIT9 = 17371; // 129
+static const uint64_t SH_FLD_STATUS_UNUSED = 17372; // 24
+static const uint64_t SH_FLD_STATUS_UNUSED_LEN = 17373; // 24
+static const uint64_t SH_FLD_STAT_LEN = 17374; // 2
+static const uint64_t SH_FLD_STEP_CHECK_CONSTANT_CPS_ENABLE = 17375; // 1
+static const uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION = 17376; // 1
+static const uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR = 17377; // 3
+static const uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN = 17378; // 3
+static const uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_LEN = 17379; // 1
+static const uint64_t SH_FLD_STEP_CHECK_ENABLE_CHICKEN_SWITCH = 17380; // 1
+static const uint64_t SH_FLD_STEP_CHECK_STEP_SELECT = 17381; // 1
+static const uint64_t SH_FLD_STEP_CHECK_VALIDITY_COUNT = 17382; // 1
+static const uint64_t SH_FLD_STEP_CHECK_VALIDITY_COUNT_LEN = 17383; // 1
+static const uint64_t SH_FLD_STEP_CREATE_DUAL_EDGE_DISABLE = 17384; // 1
+static const uint64_t SH_FLD_STICKY_CACHE_VDM_DATA = 17385; // 12
+static const uint64_t SH_FLD_STICKY_CACHE_VDM_DATA_LEN = 17386; // 12
+static const uint64_t SH_FLD_STICKY_CORE0_VDM_DATA = 17387; // 12
+static const uint64_t SH_FLD_STICKY_CORE0_VDM_DATA_LEN = 17388; // 12
+static const uint64_t SH_FLD_STICKY_CORE1_VDM_DATA = 17389; // 12
+static const uint64_t SH_FLD_STICKY_CORE1_VDM_DATA_LEN = 17390; // 12
+static const uint64_t SH_FLD_STICKY_CORE2_VDM_DATA = 17391; // 12
+static const uint64_t SH_FLD_STICKY_CORE2_VDM_DATA_LEN = 17392; // 12
+static const uint64_t SH_FLD_STICKY_CORE3_VDM_DATA = 17393; // 12
+static const uint64_t SH_FLD_STICKY_CORE3_VDM_DATA_LEN = 17394; // 12
+static const uint64_t SH_FLD_STICKY_ERROR_INJECT_ENABLE = 17395; // 1
+static const uint64_t SH_FLD_STICKY_VDM_CONTROL_SUMMARY = 17396; // 12
+static const uint64_t SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN = 17397; // 12
+static const uint64_t SH_FLD_STOP = 17398; // 6
+static const uint64_t SH_FLD_STOP1_ACTIVE_ENABLE = 17399; // 12
+static const uint64_t SH_FLD_STOPPED = 17400; // 2
+static const uint64_t SH_FLD_STOP_ACTIVE_MASK = 17401; // 12
+static const uint64_t SH_FLD_STOP_ERROR_0 = 17402; // 4
+static const uint64_t SH_FLD_STOP_ERROR_1 = 17403; // 2
+static const uint64_t SH_FLD_STOP_ERROR_2 = 17404; // 2
+static const uint64_t SH_FLD_STOP_ERROR_3 = 17405; // 2
+static const uint64_t SH_FLD_STOP_EXIT_TYPE_SEL = 17406; // 24
+static const uint64_t SH_FLD_STOP_ON_ERR = 17407; // 45
+static const uint64_t SH_FLD_STOP_ON_RECOV_ERR_SELECTION = 17408; // 43
+static const uint64_t SH_FLD_STOP_ON_SPATTN_SELECTION = 17409; // 43
+static const uint64_t SH_FLD_STOP_ON_XSTOP_SELECTION = 17410; // 43
+static const uint64_t SH_FLD_STOP_OVERRIDE_MODE = 17411; // 12
+static const uint64_t SH_FLD_STOP_RECOVERY_NOTIFY_PRD = 17412; // 1
+static const uint64_t SH_FLD_STOP_REQUEST_LEVEL_A_N = 17413; // 96
+static const uint64_t SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN = 17414; // 96
+static const uint64_t SH_FLD_STOP_RUNN_ON_XSTOP = 17415; // 43
+static const uint64_t SH_FLD_STORE_ADDRESS = 17416; // 21
+static const uint64_t SH_FLD_STORE_ADDRESS_LEN = 17417; // 21
+static const uint64_t SH_FLD_STORE_ON_TRIG_MODE = 17418; // 90
+static const uint64_t SH_FLD_STORE_ON_TRIG_MODE_LEN = 17419; // 90
+static const uint64_t SH_FLD_STORE_TIMEOUT = 17420; // 12
+static const uint64_t SH_FLD_STQ_DATA_HANG = 17421; // 1
+static const uint64_t SH_FLD_STQ_DATA_PARITY_ERR = 17422; // 12
+static const uint64_t SH_FLD_STQ_ERR = 17423; // 12
+static const uint64_t SH_FLD_STQ_ERR_LEN = 17424; // 12
+static const uint64_t SH_FLD_STQ_FSM_PERR = 17425; // 1
+static const uint64_t SH_FLD_STQ_HW_MAX_0_4 = 17426; // 1
+static const uint64_t SH_FLD_STQ_HW_MAX_0_4_LEN = 17427; // 1
+static const uint64_t SH_FLD_STQ_HW_MIN_0_4 = 17428; // 1
+static const uint64_t SH_FLD_STQ_HW_MIN_0_4_LEN = 17429; // 1
+static const uint64_t SH_FLD_STQ_HYP_MAX_0_4 = 17430; // 1
+static const uint64_t SH_FLD_STQ_HYP_MAX_0_4_LEN = 17431; // 1
+static const uint64_t SH_FLD_STQ_HYP_MIN_0_4 = 17432; // 1
+static const uint64_t SH_FLD_STQ_HYP_MIN_0_4_LEN = 17433; // 1
+static const uint64_t SH_FLD_STQ_IPI_MAX_0_4 = 17434; // 1
+static const uint64_t SH_FLD_STQ_IPI_MAX_0_4_LEN = 17435; // 1
+static const uint64_t SH_FLD_STQ_IPI_MIN_0_4 = 17436; // 1
+static const uint64_t SH_FLD_STQ_IPI_MIN_0_4_LEN = 17437; // 1
+static const uint64_t SH_FLD_STQ_OS_MAX_0_4 = 17438; // 1
+static const uint64_t SH_FLD_STQ_OS_MAX_0_4_LEN = 17439; // 1
+static const uint64_t SH_FLD_STQ_OS_MIN_0_4 = 17440; // 1
+static const uint64_t SH_FLD_STQ_OS_MIN_0_4_LEN = 17441; // 1
+static const uint64_t SH_FLD_STQ_RDI_MAX_0_4 = 17442; // 1
+static const uint64_t SH_FLD_STQ_RDI_MAX_0_4_LEN = 17443; // 1
+static const uint64_t SH_FLD_STQ_RDI_MIN_0_4 = 17444; // 1
+static const uint64_t SH_FLD_STQ_RDI_MIN_0_4_LEN = 17445; // 1
+static const uint64_t SH_FLD_STQ_REG_MAX_0_4 = 17446; // 1
+static const uint64_t SH_FLD_STQ_REG_MAX_0_4_LEN = 17447; // 1
+static const uint64_t SH_FLD_STQ_REG_MIN_0_4 = 17448; // 1
+static const uint64_t SH_FLD_STQ_REG_MIN_0_4_LEN = 17449; // 1
+static const uint64_t SH_FLD_STQ_THR_MAX_0_4 = 17450; // 1
+static const uint64_t SH_FLD_STQ_THR_MAX_0_4_LEN = 17451; // 1
+static const uint64_t SH_FLD_STQ_THR_MIN_0_4 = 17452; // 1
+static const uint64_t SH_FLD_STQ_THR_MIN_0_4_LEN = 17453; // 1
+static const uint64_t SH_FLD_STQ_TYPE = 17454; // 12
+static const uint64_t SH_FLD_STQ_TYPE_LEN = 17455; // 12
+static const uint64_t SH_FLD_STQ_VPC_MAX_0_4 = 17456; // 1
+static const uint64_t SH_FLD_STQ_VPC_MAX_0_4_LEN = 17457; // 1
+static const uint64_t SH_FLD_STQ_VPC_MIN_0_4 = 17458; // 1
+static const uint64_t SH_FLD_STQ_VPC_MIN_0_4_LEN = 17459; // 1
+static const uint64_t SH_FLD_STREAM_MODE = 17460; // 4
+static const uint64_t SH_FLD_STREAM_TYPE = 17461; // 4
+static const uint64_t SH_FLD_STRICT_IPI_RULES = 17462; // 1
+static const uint64_t SH_FLD_STRICT_ORDER = 17463; // 1
+static const uint64_t SH_FLD_STROBE_WINDOW_EN = 17464; // 43
+static const uint64_t SH_FLD_ST_ACK_DEAD = 17465; // 12
+static const uint64_t SH_FLD_ST_ADDR_ERR = 17466; // 12
+static const uint64_t SH_FLD_ST_CLASS_CMD_ADDR_ERR = 17467; // 4
+static const uint64_t SH_FLD_ST_CLASS_CMD_FOREIGN_LINK_FAIL = 17468; // 4
+static const uint64_t SH_FLD_ST_ECC_CE = 17469; // 1
+static const uint64_t SH_FLD_ST_ECC_UE = 17470; // 1
+static const uint64_t SH_FLD_SUE_0 = 17471; // 8
+static const uint64_t SH_FLD_SUE_1 = 17472; // 8
+static const uint64_t SH_FLD_SUE_DIS_BR = 17473; // 3
+static const uint64_t SH_FLD_SUE_DIS_BR_PERR = 17474; // 3
+static const uint64_t SH_FLD_SUE_DIS_IR = 17475; // 3
+static const uint64_t SH_FLD_SUE_DIS_IR_PERR = 17476; // 3
+static const uint64_t SH_FLD_SUE_DIS_OR = 17477; // 3
+static const uint64_t SH_FLD_SUE_DIS_OR_PERR = 17478; // 3
+static const uint64_t SH_FLD_SUE_DIS_PR = 17479; // 3
+static const uint64_t SH_FLD_SUE_DIS_PT = 17480; // 3
+static const uint64_t SH_FLD_SUMMARY = 17481; // 1
+static const uint64_t SH_FLD_SUOP_ERROR_1 = 17482; // 4
+static const uint64_t SH_FLD_SUOP_ERROR_2 = 17483; // 4
+static const uint64_t SH_FLD_SUOP_ERROR_3 = 17484; // 4
+static const uint64_t SH_FLD_SUPPRESS = 17485; // 301
+static const uint64_t SH_FLD_SUPPRESS_EVEN_CLK = 17486; // 43
+static const uint64_t SH_FLD_SWC_VALUE = 17487; // 1
+static const uint64_t SH_FLD_SWC_VALUE_LEN = 17488; // 1
+static const uint64_t SH_FLD_SWITCH_SYNC_ERROR_DISABLE = 17489; // 1
+static const uint64_t SH_FLD_SYM_CPB_CHECK_DISABLE = 17490; // 1
+static const uint64_t SH_FLD_SYM_MAX_INRD = 17491; // 1
+static const uint64_t SH_FLD_SYM_MAX_INRD_LEN = 17492; // 1
+static const uint64_t SH_FLD_SYNCEN = 17493; // 7
+static const uint64_t SH_FLD_SYNC_BRK = 17494; // 1
+static const uint64_t SH_FLD_SYNC_BRK_LEN = 17495; // 1
+static const uint64_t SH_FLD_SYNC_CREATE_SPS_SELECT = 17496; // 1
+static const uint64_t SH_FLD_SYNC_CREATE_SPS_SELECT_LEN = 17497; // 1
+static const uint64_t SH_FLD_SYNC_DONE = 17498; // 2
+static const uint64_t SH_FLD_SYNC_DONE_LEN = 17499; // 2
+static const uint64_t SH_FLD_SYNC_FENCE = 17500; // 4
+static const uint64_t SH_FLD_SYNC_GO_CH0 = 17501; // 4
+static const uint64_t SH_FLD_SYNC_GO_CH1 = 17502; // 4
+static const uint64_t SH_FLD_SYNC_HEADER_ERROR_RATE = 17503; // 2
+static const uint64_t SH_FLD_SYNC_HEADER_ERROR_RATE_LEN = 17504; // 2
+static const uint64_t SH_FLD_SYNC_MODE = 17505; // 4
+static const uint64_t SH_FLD_SYNC_REPLAY_COUNT = 17506; // 4
+static const uint64_t SH_FLD_SYNC_REPLAY_COUNT_LEN = 17507; // 4
+static const uint64_t SH_FLD_SYNC_RESERVED = 17508; // 4
+static const uint64_t SH_FLD_SYNC_RESERVED_LEN = 17509; // 4
+static const uint64_t SH_FLD_SYNC_RESET = 17510; // 1
+static const uint64_t SH_FLD_SYNC_TIMER_SEL = 17511; // 1
+static const uint64_t SH_FLD_SYNC_TIMER_SEL_LEN = 17512; // 1
+static const uint64_t SH_FLD_SYNC_TYPE = 17513; // 4
+static const uint64_t SH_FLD_SYNC_TYPE_LEN = 17514; // 4
+static const uint64_t SH_FLD_SYNC_WAIT = 17515; // 1
+static const uint64_t SH_FLD_SYNC_WAIT_LEN = 17516; // 1
+static const uint64_t SH_FLD_SYNDROME = 17517; // 8
+static const uint64_t SH_FLD_SYNDROME_LEN = 17518; // 8
+static const uint64_t SH_FLD_SYN_HI_0_7 = 17519; // 1
+static const uint64_t SH_FLD_SYN_HI_0_7_LEN = 17520; // 1
+static const uint64_t SH_FLD_SYN_LO_0_7 = 17521; // 1
+static const uint64_t SH_FLD_SYN_LO_0_7_LEN = 17522; // 1
+static const uint64_t SH_FLD_SYSCLK_2X_MEMINTCLKO = 17523; // 8
+static const uint64_t SH_FLD_SYSCLK_RESET = 17524; // 8
+static const uint64_t SH_FLD_SYSMAP_SM_NOT_LG_SEL = 17525; // 12
+static const uint64_t SH_FLD_SYSTEM = 17526; // 2
+static const uint64_t SH_FLD_SYSTEM_CHECKSTOP = 17527; // 1
+static const uint64_t SH_FLD_SYSTEM_FAST_INIT = 17528; // 43
+static const uint64_t SH_FLD_SYSTEM_LEN = 17529; // 2
+static const uint64_t SH_FLD_SYSTEM_RESET = 17530; // 1
+static const uint64_t SH_FLD_S_PATH_0_PARITY = 17531; // 4
+static const uint64_t SH_FLD_S_PATH_0_STEP_CHECK = 17532; // 4
+static const uint64_t SH_FLD_S_PATH_0_STEP_CHECK_VALID = 17533; // 1
+static const uint64_t SH_FLD_S_PATH_1_PARITY = 17534; // 4
+static const uint64_t SH_FLD_S_PATH_1_STEP_CHECK = 17535; // 4
+static const uint64_t SH_FLD_S_PATH_1_STEP_CHECK_VALID = 17536; // 1
+static const uint64_t SH_FLD_S_PATH_SELECT = 17537; // 1
+static const uint64_t SH_FLD_T0_RUN_Q = 17538; // 24
+static const uint64_t SH_FLD_T1_RUN_Q = 17539; // 24
+static const uint64_t SH_FLD_T2_RUN_Q = 17540; // 24
+static const uint64_t SH_FLD_T3_RUN_Q = 17541; // 24
+static const uint64_t SH_FLD_T4_RUN_Q = 17542; // 24
+static const uint64_t SH_FLD_T5_RUN_Q = 17543; // 24
+static const uint64_t SH_FLD_T6_RUN_Q = 17544; // 24
+static const uint64_t SH_FLD_T7_RUN_Q = 17545; // 24
+static const uint64_t SH_FLD_TABLE_ADDRESS = 17546; // 1
+static const uint64_t SH_FLD_TABLE_ADDRESS_LEN = 17547; // 1
+static const uint64_t SH_FLD_TABLE_DATA = 17548; // 1
+static const uint64_t SH_FLD_TABLE_DATA_LEN = 17549; // 1
+static const uint64_t SH_FLD_TABLE_SELECT = 17550; // 1
+static const uint64_t SH_FLD_TABLE_SELECT_LEN = 17551; // 1
+static const uint64_t SH_FLD_TABLE_SEL_0_3 = 17552; // 1
+static const uint64_t SH_FLD_TABLE_SEL_0_3_LEN = 17553; // 1
+static const uint64_t SH_FLD_TAG_ECC = 17554; // 12
+static const uint64_t SH_FLD_TAG_ECC_LEN = 17555; // 12
+static const uint64_t SH_FLD_TAP_SEL = 17556; // 24
+static const uint64_t SH_FLD_TAP_SEL_LEN = 17557; // 24
+static const uint64_t SH_FLD_TARGET = 17558; // 2
+static const uint64_t SH_FLD_TARGET_DDE = 17559; // 3
+static const uint64_t SH_FLD_TARGET_DDE_LEN = 17560; // 3
+static const uint64_t SH_FLD_TARGET_ID0 = 17561; // 2
+static const uint64_t SH_FLD_TARGET_LEN = 17562; // 2
+static const uint64_t SH_FLD_TARGET_MIN = 17563; // 2
+static const uint64_t SH_FLD_TARGET_MIN_LEN = 17564; // 2
+static const uint64_t SH_FLD_TARGET_VALID = 17565; // 2
+static const uint64_t SH_FLD_TARGET_VALID_LEN = 17566; // 2
+static const uint64_t SH_FLD_TBST0_BADIN_ERRHOLD = 17567; // 2
+static const uint64_t SH_FLD_TBST6_BADIN_ERRHOLD = 17568; // 2
+static const uint64_t SH_FLD_TBST7_BADIN_ERRHOLD = 17569; // 2
+static const uint64_t SH_FLD_TBST9_BADIN_ERRHOLD = 17570; // 2
+static const uint64_t SH_FLD_TBST_CORRUPT_ERRHOLD = 17571; // 2
+static const uint64_t SH_FLD_TB_CMD_DISCARDED_ERRHOLD = 17572; // 2
+static const uint64_t SH_FLD_TB_FIR_ERR_ERRHOLD = 17573; // 2
+static const uint64_t SH_FLD_TB_MISSING_STEP_ERRHOLD = 17574; // 2
+static const uint64_t SH_FLD_TB_MISSING_SYNC_ERRHOLD = 17575; // 2
+static const uint64_t SH_FLD_TB_REG_RDATA_PERR_ERRHOLD = 17576; // 2
+static const uint64_t SH_FLD_TB_RESIDUE_ERR_ERRHOLD = 17577; // 2
+static const uint64_t SH_FLD_TCBR_TP_PSI_GLB_ERR_0 = 17578; // 4
+static const uint64_t SH_FLD_TCBR_TP_PSI_GLB_ERR_1 = 17579; // 4
+static const uint64_t SH_FLD_TCD_PERR_ESR = 17580; // 1
+static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_EQ = 17581; // 24
+static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_EQ_LEN = 17582; // 24
+static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_DN = 17583; // 24
+static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_DN_LEN = 17584; // 24
+static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_UP = 17585; // 24
+static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_UP_LEN = 17586; // 24
+static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_DN = 17587; // 24
+static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_DN_LEN = 17588; // 24
+static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_UP = 17589; // 24
+static const uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_UP_LEN = 17590; // 24
+static const uint64_t SH_FLD_TCE_CACHE_1W = 17591; // 1
+static const uint64_t SH_FLD_TCE_CACHE_DISABLE = 17592; // 1
+static const uint64_t SH_FLD_TCE_CACHE_MULT_HIT_ERR_ESR = 17593; // 1
+static const uint64_t SH_FLD_TCE_COMMON_FATAL_ERROR = 17594; // 6
+static const uint64_t SH_FLD_TCE_ECC_CORRECTABLE_ERROR = 17595; // 6
+static const uint64_t SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR = 17596; // 6
+static const uint64_t SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR = 17597; // 6
+static const uint64_t SH_FLD_TCE_PAGE_ACCESS_ERR_ESR = 17598; // 1
+static const uint64_t SH_FLD_TCE_REQUEST_TIMEOUT_ERROR = 17599; // 6
+static const uint64_t SH_FLD_TCE_REQ_TO_ERR_ESR = 17600; // 1
+static const uint64_t SH_FLD_TCE_RESPONSE = 17601; // 1
+static const uint64_t SH_FLD_TCE_TIMEOUT = 17602; // 1
+static const uint64_t SH_FLD_TCE_TIMEOUT_LEN = 17603; // 1
+static const uint64_t SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR = 17604; // 6
+static const uint64_t SH_FLD_TCK_WIDTH = 17605; // 1
+static const uint64_t SH_FLD_TCK_WIDTH_LEN = 17606; // 1
+static const uint64_t SH_FLD_TCPERV_AMUX_VSELECT_CHIP = 17607; // 1
+static const uint64_t SH_FLD_TCPERV_AMUX_VSELECT_CHIP_LEN = 17608; // 1
+static const uint64_t SH_FLD_TCTXT_PRESP_ERROR = 17609; // 1
+static const uint64_t SH_FLD_TC_BSC_EXTMODE_DC = 17610; // 43
+static const uint64_t SH_FLD_TC_BSC_INTMODE_DC = 17611; // 43
+static const uint64_t SH_FLD_TC_BSC_INV_DC = 17612; // 43
+static const uint64_t SH_FLD_TC_BSC_WRAPSEL_DC = 17613; // 43
+static const uint64_t SH_FLD_TC_DIAG_PORT0_OUT = 17614; // 43
+static const uint64_t SH_FLD_TC_DIAG_PORT1_OUT = 17615; // 43
+static const uint64_t SH_FLD_TC_EDRAM_ABIST_MODE_DC = 17616; // 43
+static const uint64_t SH_FLD_TC_IOBIST_MODE_DC = 17617; // 43
+static const uint64_t SH_FLD_TC_IOM01_DDR0_DFI_RESET_ALL = 17618; // 2
+static const uint64_t SH_FLD_TC_IOM01_DDR1_DFI_RESET_ALL = 17619; // 2
+static const uint64_t SH_FLD_TC_IOM01_DDR2_DFI_RESET_ALL = 17620; // 2
+static const uint64_t SH_FLD_TC_IOM01_DDR3_DFI_RESET_ALL = 17621; // 2
+static const uint64_t SH_FLD_TC_IOM01_FORCETOKNOWN_DC = 17622; // 2
+static const uint64_t SH_FLD_TC_IOP_HSSPORWREN = 17623; // 4
+static const uint64_t SH_FLD_TC_IOP_SYS_RESET_PCS = 17624; // 4
+static const uint64_t SH_FLD_TC_IOP_SYS_RESET_PMA = 17625; // 4
+static const uint64_t SH_FLD_TC_IOX_MUX_VSEL = 17626; // 1
+static const uint64_t SH_FLD_TC_IOX_MUX_VSEL_LEN = 17627; // 1
+static const uint64_t SH_FLD_TC_LP_RESET = 17628; // 1
+static const uint64_t SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC = 17629; // 43
+static const uint64_t SH_FLD_TC_NBTI_PROBE_GATE_DC = 17630; // 43
+static const uint64_t SH_FLD_TC_OB_RATIO_DC = 17631; // 6
+static const uint64_t SH_FLD_TC_OB_RATIO_DC_LEN = 17632; // 6
+static const uint64_t SH_FLD_TC_OELCC_ALIGN_FLUSH_DC = 17633; // 43
+static const uint64_t SH_FLD_TC_OELCC_EDGE_DELAYED_DC = 17634; // 43
+static const uint64_t SH_FLD_TC_PBE0_IOVALID_DC = 17635; // 1
+static const uint64_t SH_FLD_TC_PBE1_IOVALID_DC = 17636; // 1
+static const uint64_t SH_FLD_TC_PBE2_IOVALID_DC = 17637; // 1
+static const uint64_t SH_FLD_TC_PBE3_IOVALID_DC = 17638; // 1
+static const uint64_t SH_FLD_TC_PBE4_IOVALID_DC = 17639; // 1
+static const uint64_t SH_FLD_TC_PBE5_IOVALID_DC = 17640; // 1
+static const uint64_t SH_FLD_TC_PBIOO0_IOVALID = 17641; // 6
+static const uint64_t SH_FLD_TC_PBIOO1_IOVALID = 17642; // 6
+static const uint64_t SH_FLD_TC_PCI0_IOVALID = 17643; // 1
+static const uint64_t SH_FLD_TC_PCI0_LANE_CFG_DC = 17644; // 1
+static const uint64_t SH_FLD_TC_PCI0_LANE_CFG_DC_LEN = 17645; // 1
+static const uint64_t SH_FLD_TC_PCI0_RATIO_DC = 17646; // 1
+static const uint64_t SH_FLD_TC_PCI0_RATIO_DC_LEN = 17647; // 1
+static const uint64_t SH_FLD_TC_PCI0_RATIO_OVERRIDE = 17648; // 1
+static const uint64_t SH_FLD_TC_PCI0_SWAP_DC = 17649; // 1
+static const uint64_t SH_FLD_TC_PCI1X_IOVALID = 17650; // 1
+static const uint64_t SH_FLD_TC_PCI1X_IOVALID_LEN = 17651; // 1
+static const uint64_t SH_FLD_TC_PCI1_LANE_CFG_DC = 17652; // 1
+static const uint64_t SH_FLD_TC_PCI1_LANE_CFG_DC_LEN = 17653; // 1
+static const uint64_t SH_FLD_TC_PCI1_PIPE1_RATIO_DC = 17654; // 1
+static const uint64_t SH_FLD_TC_PCI1_PIPE1_RATIO_DC_LEN = 17655; // 1
+static const uint64_t SH_FLD_TC_PCI1_PIPE2_RATIO_DC = 17656; // 1
+static const uint64_t SH_FLD_TC_PCI1_PIPE2_RATIO_DC_LEN = 17657; // 1
+static const uint64_t SH_FLD_TC_PCI1_RATIO_OVERRIDE = 17658; // 1
+static const uint64_t SH_FLD_TC_PCI1_RATIO_OVERRIDE_LEN = 17659; // 1
+static const uint64_t SH_FLD_TC_PCI1_SWAP_DC = 17660; // 1
+static const uint64_t SH_FLD_TC_PCI1_SWAP_DC_LEN = 17661; // 1
+static const uint64_t SH_FLD_TC_PCI2_IOVALID = 17662; // 2
+static const uint64_t SH_FLD_TC_PCI2_IOVALID_LEN = 17663; // 2
+static const uint64_t SH_FLD_TC_PCI2_LANE_CFG_DC = 17664; // 2
+static const uint64_t SH_FLD_TC_PCI2_LANE_CFG_DC_LEN = 17665; // 2
+static const uint64_t SH_FLD_TC_PCI2_PIPE1_RATIO_DC = 17666; // 2
+static const uint64_t SH_FLD_TC_PCI2_PIPE1_RATIO_DC_LEN = 17667; // 2
+static const uint64_t SH_FLD_TC_PCI2_PIPE2_RATIO_DC = 17668; // 2
+static const uint64_t SH_FLD_TC_PCI2_PIPE2_RATIO_DC_LEN = 17669; // 2
+static const uint64_t SH_FLD_TC_PCI2_PIPE3_RATIO_DC = 17670; // 2
+static const uint64_t SH_FLD_TC_PCI2_PIPE3_RATIO_DC_LEN = 17671; // 2
+static const uint64_t SH_FLD_TC_PCI2_RATIO_OVERRIDE = 17672; // 2
+static const uint64_t SH_FLD_TC_PCI2_RATIO_OVERRIDE_LEN = 17673; // 2
+static const uint64_t SH_FLD_TC_PCI2_SWAP_DC = 17674; // 2
+static const uint64_t SH_FLD_TC_PCI2_SWAP_DC_LEN = 17675; // 2
+static const uint64_t SH_FLD_TC_PERV_EXPORT_FREEZE = 17676; // 1
+static const uint64_t SH_FLD_TC_PERV_REGION_FENCE = 17677; // 43
+static const uint64_t SH_FLD_TC_PSI_IOVALID_DC = 17678; // 1
+static const uint64_t SH_FLD_TC_PSRO_SEL_DC = 17679; // 43
+static const uint64_t SH_FLD_TC_PSRO_SEL_DC_LEN = 17680; // 43
+static const uint64_t SH_FLD_TC_REFCLK_DRVR_EN_DC = 17681; // 43
+static const uint64_t SH_FLD_TC_REGION1_FENCE = 17682; // 36
+static const uint64_t SH_FLD_TC_REGION2_FENCE = 17683; // 36
+static const uint64_t SH_FLD_TC_REGION3_FENCE = 17684; // 36
+static const uint64_t SH_FLD_TC_REGION4_FENCE = 17685; // 31
+static const uint64_t SH_FLD_TC_REGION5_FENCE = 17686; // 28
+static const uint64_t SH_FLD_TC_REGION6_FENCE = 17687; // 26
+static const uint64_t SH_FLD_TC_REGION7_FENCE = 17688; // 25
+static const uint64_t SH_FLD_TC_REGION8_FENCE = 17689; // 24
+static const uint64_t SH_FLD_TC_REGION9_FENCE = 17690; // 24
+static const uint64_t SH_FLD_TC_SKIT_MODE_BIST_DC = 17691; // 43
+static const uint64_t SH_FLD_TC_SRAM_ABIST_MODE_DC = 17692; // 43
+static const uint64_t SH_FLD_TC_START_TEST_DC = 17693; // 43
+static const uint64_t SH_FLD_TC_UNIT_ARY_WRT_THRU_DC = 17694; // 43
+static const uint64_t SH_FLD_TC_UNIT_AVP_MODE = 17695; // 43
+static const uint64_t SH_FLD_TC_UNIT_CHIP_ID_DC = 17696; // 43
+static const uint64_t SH_FLD_TC_UNIT_CHIP_ID_DC_LEN = 17697; // 43
+static const uint64_t SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC = 17698; // 43
+static const uint64_t SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC = 17699; // 43
+static const uint64_t SH_FLD_TC_UNIT_GROUP_ID_DC = 17700; // 43
+static const uint64_t SH_FLD_TC_UNIT_GROUP_ID_DC_LEN = 17701; // 43
+static const uint64_t SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC = 17702; // 43
+static const uint64_t SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE = 17703; // 43
+static const uint64_t SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC = 17704; // 43
+static const uint64_t SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC = 17705; // 43
+static const uint64_t SH_FLD_TC_UNIT_SYS_ID_DC = 17706; // 43
+static const uint64_t SH_FLD_TC_UNIT_SYS_ID_DC_LEN = 17707; // 43
+static const uint64_t SH_FLD_TC_VITL_REGION_FENCE = 17708; // 43
+static const uint64_t SH_FLD_TDM_DELAY = 17709; // 5
+static const uint64_t SH_FLD_TDM_DELAY_LEN = 17710; // 5
+static const uint64_t SH_FLD_TDR_DAC_CNTL = 17711; // 6
+static const uint64_t SH_FLD_TDR_DAC_CNTL_LEN = 17712; // 6
+static const uint64_t SH_FLD_TDR_ENABLE = 17713; // 116
+static const uint64_t SH_FLD_TDR_PERR_ESR = 17714; // 1
+static const uint64_t SH_FLD_TDR_PHASE_SEL = 17715; // 6
+static const uint64_t SH_FLD_TDR_PULSE_OFFSET = 17716; // 6
+static const uint64_t SH_FLD_TDR_PULSE_OFFSET_LEN = 17717; // 6
+static const uint64_t SH_FLD_TDR_PULSE_WIDTH = 17718; // 6
+static const uint64_t SH_FLD_TDR_PULSE_WIDTH_LEN = 17719; // 6
+static const uint64_t SH_FLD_TER = 17720; // 8
+static const uint64_t SH_FLD_TERM_ENC = 17721; // 1
+static const uint64_t SH_FLD_TERM_ENC_LEN = 17722; // 1
+static const uint64_t SH_FLD_TERM_TEST = 17723; // 1
+static const uint64_t SH_FLD_TER_LEN = 17724; // 8
+static const uint64_t SH_FLD_TER_V = 17725; // 8
+static const uint64_t SH_FLD_TEST_ENABLE = 17726; // 43
+static const uint64_t SH_FLD_TFAC_ERR = 17727; // 96
+static const uint64_t SH_FLD_TFMR_PARITY_ERR = 17728; // 96
+static const uint64_t SH_FLD_TFREQ0 = 17729; // 9
+static const uint64_t SH_FLD_TFREQ0_LEN = 17730; // 9
+static const uint64_t SH_FLD_TFREQ1 = 17731; // 9
+static const uint64_t SH_FLD_TFREQ1_LEN = 17732; // 9
+static const uint64_t SH_FLD_TGT_NODAL_DINC_ERR = 17733; // 12
+static const uint64_t SH_FLD_TGT_NODAL_REQ_DINC_ERR = 17734; // 12
+static const uint64_t SH_FLD_THERM_MODE = 17735; // 43
+static const uint64_t SH_FLD_THERM_MODEREG_PARITY_MASK = 17736; // 43
+static const uint64_t SH_FLD_THERM_MODE_LEN = 17737; // 43
+static const uint64_t SH_FLD_THERM_TRIP = 17738; // 43
+static const uint64_t SH_FLD_THERM_TRIP_LEN = 17739; // 43
+static const uint64_t SH_FLD_THRESHOLD = 17740; // 1
+static const uint64_t SH_FLD_THRESH_0 = 17741; // 3
+static const uint64_t SH_FLD_THRESH_0_LEN = 17742; // 3
+static const uint64_t SH_FLD_THRESH_1 = 17743; // 3
+static const uint64_t SH_FLD_THRESH_1_LEN = 17744; // 3
+static const uint64_t SH_FLD_THRESH_2 = 17745; // 3
+static const uint64_t SH_FLD_THRESH_2_LEN = 17746; // 3
+static const uint64_t SH_FLD_THRESH_DIS_TAP_CLEAR = 17747; // 12
+static const uint64_t SH_FLD_THRESH_DIS_TAP_STOP = 17748; // 12
+static const uint64_t SH_FLD_THRESH_DIS_TB_CLEAR = 17749; // 12
+static const uint64_t SH_FLD_THRESH_ENABLE = 17750; // 12
+static const uint64_t SH_FLD_THRESH_ENABLE_LEN = 17751; // 12
+static const uint64_t SH_FLD_THRESH_LINK0_CLEAR = 17752; // 12
+static const uint64_t SH_FLD_THRESH_LINK0_COUNT = 17753; // 12
+static const uint64_t SH_FLD_THRESH_LINK0_COUNT_LEN = 17754; // 12
+static const uint64_t SH_FLD_THRESH_LINK1_CLEAR = 17755; // 12
+static const uint64_t SH_FLD_THRESH_LINK1_COUNT = 17756; // 12
+static const uint64_t SH_FLD_THRESH_LINK1_COUNT_LEN = 17757; // 12
+static const uint64_t SH_FLD_THRESH_TAP_SEL = 17758; // 12
+static const uint64_t SH_FLD_THRESH_TAP_SEL_LEN = 17759; // 12
+static const uint64_t SH_FLD_THRESH_TB_SEL = 17760; // 12
+static const uint64_t SH_FLD_THRESH_TB_SEL_LEN = 17761; // 12
+static const uint64_t SH_FLD_THRESH_UNUSED1 = 17762; // 12
+static const uint64_t SH_FLD_THRESH_UNUSED1_LEN = 17763; // 12
+static const uint64_t SH_FLD_THRESH_UNUSED2 = 17764; // 12
+static const uint64_t SH_FLD_THRES_ENA = 17765; // 43
+static const uint64_t SH_FLD_THRES_ENA_LEN = 17766; // 43
+static const uint64_t SH_FLD_THRES_OVERFLOW_MASK = 17767; // 43
+static const uint64_t SH_FLD_THRES_STATE_MASK = 17768; // 43
+static const uint64_t SH_FLD_THRES_TRIP_ENA = 17769; // 43
+static const uint64_t SH_FLD_THRES_TRIP_ENA_LEN = 17770; // 43
+static const uint64_t SH_FLD_THRID = 17771; // 1
+static const uint64_t SH_FLD_THRID_LEN = 17772; // 1
+static const uint64_t SH_FLD_THR_ID = 17773; // 1
+static const uint64_t SH_FLD_THR_ID_LEN = 17774; // 1
+static const uint64_t SH_FLD_TID = 17775; // 8
+static const uint64_t SH_FLD_TID_LEN = 17776; // 8
+static const uint64_t SH_FLD_TIER0_VALUE = 17777; // 12
+static const uint64_t SH_FLD_TIER0_VALUE_LEN = 17778; // 12
+static const uint64_t SH_FLD_TIER1_VALUE = 17779; // 24
+static const uint64_t SH_FLD_TIER1_VALUE_LEN = 17780; // 24
+static const uint64_t SH_FLD_TIER2_VALUE = 17781; // 24
+static const uint64_t SH_FLD_TIER2_VALUE_LEN = 17782; // 24
+static const uint64_t SH_FLD_TIME = 17783; // 43
+static const uint64_t SH_FLD_TIMEBASE = 17784; // 330
+static const uint64_t SH_FLD_TIMEBASE_ENABLE = 17785; // 1
+static const uint64_t SH_FLD_TIMEBASE_LEN = 17786; // 330
+static const uint64_t SH_FLD_TIMEOUT = 17787; // 5
+static const uint64_t SH_FLD_TIMEOUT_ACTIVE = 17788; // 2
+static const uint64_t SH_FLD_TIMEOUT_EN = 17789; // 1
+static const uint64_t SH_FLD_TIMEOUT_LEN = 17790; // 5
+static const uint64_t SH_FLD_TIMEOUT_MASK = 17791; // 43
+static const uint64_t SH_FLD_TIMEOUT_N = 17792; // 2
+static const uint64_t SH_FLD_TIMEOUT_ON_I2C_STATUS_RD = 17793; // 1
+static const uint64_t SH_FLD_TIMEOUT_PARITY = 17794; // 43
+static const uint64_t SH_FLD_TIMEOUT_SEL = 17795; // 3
+static const uint64_t SH_FLD_TIMEOUT_SEL_LEN = 17796; // 3
+static const uint64_t SH_FLD_TIMEOUT_VALUE = 17797; // 5
+static const uint64_t SH_FLD_TIMEOUT_VALUE_LEN = 17798; // 5
+static const uint64_t SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 17799; // 43
+static const uint64_t SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 17800; // 43
+static const uint64_t SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 17801; // 43
+static const uint64_t SH_FLD_TIMER = 17802; // 3
+static const uint64_t SH_FLD_TIMER_1US = 17803; // 5
+static const uint64_t SH_FLD_TIMER_1US_LEN = 17804; // 5
+static const uint64_t SH_FLD_TIMER_ENABLE = 17805; // 4
+static const uint64_t SH_FLD_TIMER_EXPIRED_RECOV_ERROR = 17806; // 4
+static const uint64_t SH_FLD_TIMER_EXPIRED_XSTOP_ERROR = 17807; // 4
+static const uint64_t SH_FLD_TIMER_LEN = 17808; // 3
+static const uint64_t SH_FLD_TIMER_N = 17809; // 2
+static const uint64_t SH_FLD_TIMER_N_LEN = 17810; // 2
+static const uint64_t SH_FLD_TIMER_PERIOD_MASK = 17811; // 4
+static const uint64_t SH_FLD_TIMER_PERIOD_MASK_LEN = 17812; // 4
+static const uint64_t SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR = 17813; // 43
+static const uint64_t SH_FLD_TIMESTAMP_COUNTER_VALUE = 17814; // 43
+static const uint64_t SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN = 17815; // 43
+static const uint64_t SH_FLD_TIME_BASE_ERR = 17816; // 4
+static const uint64_t SH_FLD_TLBIE_CNT_THRESH = 17817; // 13
+static const uint64_t SH_FLD_TLBIE_CNT_THRESH_LEN = 17818; // 13
+static const uint64_t SH_FLD_TLBIE_CNT_WT4TX_CORE_EN = 17819; // 12
+static const uint64_t SH_FLD_TLBIE_CONTROL_ERR = 17820; // 12
+static const uint64_t SH_FLD_TLBIE_DEC_RATE = 17821; // 13
+static const uint64_t SH_FLD_TLBIE_DEC_RATE_LEN = 17822; // 13
+static const uint64_t SH_FLD_TLBIE_INC_RATE = 17823; // 13
+static const uint64_t SH_FLD_TLBIE_INC_RATE_LEN = 17824; // 13
+static const uint64_t SH_FLD_TLBIE_MASTER_TIMEOUT = 17825; // 12
+static const uint64_t SH_FLD_TLBIE_PACING_CNT_EN = 17826; // 12
+static const uint64_t SH_FLD_TLBIE_SLBIEG_SW_ERR = 17827; // 12
+static const uint64_t SH_FLD_TLBIE_SNOOP_TIMEOUT = 17828; // 12
+static const uint64_t SH_FLD_TLBIE_STALL_CMPLT_CNT = 17829; // 14
+static const uint64_t SH_FLD_TLBIE_STALL_CMPLT_CNT_LEN = 17830; // 14
+static const uint64_t SH_FLD_TLBIE_STALL_DELAY_CNT = 17831; // 14
+static const uint64_t SH_FLD_TLBIE_STALL_DELAY_CNT_LEN = 17832; // 14
+static const uint64_t SH_FLD_TLBIE_STALL_EN = 17833; // 14
+static const uint64_t SH_FLD_TLBIE_STALL_THRESHOLD = 17834; // 14
+static const uint64_t SH_FLD_TLBIE_STALL_THRESHOLD_LEN = 17835; // 14
+static const uint64_t SH_FLD_TLBI_BAD_OP_ERR = 17836; // 4
+static const uint64_t SH_FLD_TLBI_DATA_POLL_PULSE_DIV = 17837; // 2
+static const uint64_t SH_FLD_TLBI_DATA_POLL_PULSE_DIV_LEN = 17838; // 2
+static const uint64_t SH_FLD_TLBI_FENCE = 17839; // 2
+static const uint64_t SH_FLD_TLBI_GROUP_PUMP_EN = 17840; // 12
+static const uint64_t SH_FLD_TLBI_PSL_DEAD = 17841; // 2
+static const uint64_t SH_FLD_TLBI_REGS_PARITY_ERRHOLD = 17842; // 2
+static const uint64_t SH_FLD_TLBI_SC_RDATA_PARITY_ERRHOLD = 17843; // 2
+static const uint64_t SH_FLD_TLBI_SEQ_NUM_PARITY_ERR = 17844; // 4
+static const uint64_t SH_FLD_TLBI_SOT_ERR = 17845; // 4
+static const uint64_t SH_FLD_TLBI_TIMEOUT = 17846; // 4
+static const uint64_t SH_FLD_TLB_BUS0_STG1_SEL = 17847; // 1
+static const uint64_t SH_FLD_TLB_BUS0_STG2_SEL = 17848; // 1
+static const uint64_t SH_FLD_TLB_BUS1_STG1_SEL = 17849; // 1
+static const uint64_t SH_FLD_TLB_BUS1_STG2_SEL = 17850; // 1
+static const uint64_t SH_FLD_TLB_CAC_PERR_DET = 17851; // 1
+static const uint64_t SH_FLD_TLB_CHK_WAIT_DEC = 17852; // 12
+static const uint64_t SH_FLD_TLB_CHK_WAIT_DEC_LEN = 17853; // 12
+static const uint64_t SH_FLD_TLB_DIR_PERR_DET = 17854; // 1
+static const uint64_t SH_FLD_TLB_LRU_PERR_DET = 17855; // 1
+static const uint64_t SH_FLD_TLB_MULTIHIT_DET = 17856; // 1
+static const uint64_t SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV = 17857; // 12
+static const uint64_t SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN = 17858; // 12
+static const uint64_t SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV = 17859; // 12
+static const uint64_t SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV_LEN = 17860; // 12
+static const uint64_t SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV = 17861; // 12
+static const uint64_t SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV_LEN = 17862; // 12
+static const uint64_t SH_FLD_TMOD_CYCLES = 17863; // 8
+static const uint64_t SH_FLD_TMOD_CYCLES_LEN = 17864; // 8
+static const uint64_t SH_FLD_TMRSC_CYCLES = 17865; // 8
+static const uint64_t SH_FLD_TMRSC_CYCLES_LEN = 17866; // 8
+static const uint64_t SH_FLD_TMR_PE = 17867; // 8
+static const uint64_t SH_FLD_TM_CAM = 17868; // 12
+static const uint64_t SH_FLD_TM_CAM_LEN = 17869; // 12
+static const uint64_t SH_FLD_TODTLON_OFF_CYCLES = 17870; // 8
+static const uint64_t SH_FLD_TODTLON_OFF_CYCLES_LEN = 17871; // 8
+static const uint64_t SH_FLD_TOD_CMD_OVERRUN = 17872; // 1
+static const uint64_t SH_FLD_TOD_CNTR_REF = 17873; // 1
+static const uint64_t SH_FLD_TOD_CNTR_REF_LEN = 17874; // 1
+static const uint64_t SH_FLD_TOD_HANG_ERR = 17875; // 1
+static const uint64_t SH_FLD_TOD_TAP = 17876; // 24
+static const uint64_t SH_FLD_TOO_MANY_BUS_ERRORS = 17877; // 8
+static const uint64_t SH_FLD_TOR_PERR_ESR = 17878; // 1
+static const uint64_t SH_FLD_TOTAL_DROOP_EVENT_CTR = 17879; // 12
+static const uint64_t SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN = 17880; // 12
+static const uint64_t SH_FLD_TOTAL_FREE_BUF_COUNT = 17881; // 1
+static const uint64_t SH_FLD_TOTAL_FREE_BUF_COUNT_LEN = 17882; // 1
+static const uint64_t SH_FLD_TO_CMP_LT = 17883; // 86
+static const uint64_t SH_FLD_TO_CMP_LT_LEN = 17884; // 86
+static const uint64_t SH_FLD_TO_IFU = 17885; // 24
+static const uint64_t SH_FLD_TO_ISU = 17886; // 24
+static const uint64_t SH_FLD_TO_LSU = 17887; // 24
+static const uint64_t SH_FLD_TO_PC = 17888; // 24
+static const uint64_t SH_FLD_TO_VSU = 17889; // 24
+static const uint64_t SH_FLD_TPCFSI_OPB_SW0_FENCE_DC = 17890; // 3
+static const uint64_t SH_FLD_TPCFSI_OPB_SW0_FENCE_DC_LEN = 17891; // 3
+static const uint64_t SH_FLD_TPCFSI_OPB_SW1_FENCE_DC = 17892; // 3
+static const uint64_t SH_FLD_TPCFSI_OPB_SW1_FENCE_DC_LEN = 17893; // 3
+static const uint64_t SH_FLD_TPCFSI_OPB_SW_RESET_DC = 17894; // 3
+static const uint64_t SH_FLD_TPFSI_ALTREFCLK_SE1 = 17895; // 3
+static const uint64_t SH_FLD_TPFSI_ALTREFCLK_SEL = 17896; // 3
+static const uint64_t SH_FLD_TPFSI_ARRAY_SET_VBL_TO_VDD_DC = 17897; // 2
+static const uint64_t SH_FLD_TPFSI_ARRAY_VBL_TO_VDD_DC = 17898; // 1
+static const uint64_t SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC = 17899; // 3
+static const uint64_t SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN = 17900; // 3
+static const uint64_t SH_FLD_TPFSI_OSCSW0_PGOOD_N = 17901; // 3
+static const uint64_t SH_FLD_TPFSI_OSCSW1_PGOOD = 17902; // 3
+static const uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ0_DC = 17903; // 3
+static const uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ0_DC_LEN = 17904; // 3
+static const uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ1_DC = 17905; // 3
+static const uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ1_DC_LEN = 17906; // 3
+static const uint64_t SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC = 17907; // 3
+static const uint64_t SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN = 17908; // 3
+static const uint64_t SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC = 17909; // 3
+static const uint64_t SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN = 17910; // 3
+static const uint64_t SH_FLD_TPFSI_OSCSW_TWEAK_DC = 17911; // 3
+static const uint64_t SH_FLD_TPFSI_OSCSW_TWEAK_DC_LEN = 17912; // 3
+static const uint64_t SH_FLD_TPFSI_TC_HSSPORWREN_ALLOW = 17913; // 3
+static const uint64_t SH_FLD_TPFSI_TPI2C_BUS_FENCE_DC = 17914; // 3
+static const uint64_t SH_FLD_TPFSI_TP_EDRAM_CTRL_GATE = 17915; // 3
+static const uint64_t SH_FLD_TPFSI_TP_FENCE_VTLIO_DC = 17916; // 3
+static const uint64_t SH_FLD_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED = 17917; // 3
+static const uint64_t SH_FLD_TPFSI_TP_PFET_FORCE_OFF_DC = 17918; // 3
+static const uint64_t SH_FLD_TPFSI_TP_PFET_OVERRIDE_ON_DC_N = 17919; // 3
+static const uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC = 17920; // 3
+static const uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC = 17921; // 3
+static const uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC = 17922; // 3
+static const uint64_t SH_FLD_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC = 17923; // 3
+static const uint64_t SH_FLD_TPSBE_TPBR_SBE_INTR = 17924; // 1
+static const uint64_t SH_FLD_TPSBE_TPIO_TPM_RESET = 17925; // 1
+static const uint64_t SH_FLD_TPSBE_TPOCC_HALT_COMPLEX = 17926; // 1
+static const uint64_t SH_FLD_TP_ARRAY_WRITE_ASSIST_EN_DC = 17927; // 3
+static const uint64_t SH_FLD_TP_CHIPLET_EN_DC = 17928; // 3
+static const uint64_t SH_FLD_TP_CLK_ASYNC_RESET_DC = 17929; // 3
+static const uint64_t SH_FLD_TP_CLK_DIV_BYPASS_EN_DC = 17930; // 3
+static const uint64_t SH_FLD_TP_CLK_PDLY_BYPASS1_EN_DC = 17931; // 3
+static const uint64_t SH_FLD_TP_CLK_PDLY_BYPASS2_EN_DC = 17932; // 3
+static const uint64_t SH_FLD_TP_CLK_PULSE_ENABLE_DC = 17933; // 3
+static const uint64_t SH_FLD_TP_CLK_PULSE_MODE_DC = 17934; // 3
+static const uint64_t SH_FLD_TP_CLK_PULSE_MODE_DC_LEN = 17935; // 3
+static const uint64_t SH_FLD_TP_CPM_CAL = 17936; // 1
+static const uint64_t SH_FLD_TP_CPM_CAL_SET = 17937; // 2
+static const uint64_t SH_FLD_TP_DI1_DC_B = 17938; // 3
+static const uint64_t SH_FLD_TP_DI1_DC_N = 17939; // 3
+static const uint64_t SH_FLD_TP_DI2_DC_B = 17940; // 3
+static const uint64_t SH_FLD_TP_DI2_DC_N = 17941; // 3
+static const uint64_t SH_FLD_TP_EDRAM_ENABLE_DC = 17942; // 3
+static const uint64_t SH_FLD_TP_EX_FUSE_FP_THROTTLE_EN_DC = 17943; // 1
+static const uint64_t SH_FLD_TP_EX_FUSE_VMX_CRYPTO_DIS_DC = 17944; // 1
+static const uint64_t SH_FLD_TP_FENCE_EN_DC = 17945; // 3
+static const uint64_t SH_FLD_TP_FENCE_PCB = 17946; // 43
+static const uint64_t SH_FLD_TP_FENCE_PCB_DC = 17947; // 3
+static const uint64_t SH_FLD_TP_FILT0_PLL_BYPASS = 17948; // 3
+static const uint64_t SH_FLD_TP_FILT0_PLL_RESET = 17949; // 3
+static const uint64_t SH_FLD_TP_FILT0_PLL_TEST_EN = 17950; // 3
+static const uint64_t SH_FLD_TP_FILT1_PLL_BYPASS = 17951; // 3
+static const uint64_t SH_FLD_TP_FILT1_PLL_RESET = 17952; // 3
+static const uint64_t SH_FLD_TP_FILT1_PLL_TEST_EN = 17953; // 3
+static const uint64_t SH_FLD_TP_FLUSH_ALIGN_OVERWRITE = 17954; // 3
+static const uint64_t SH_FLD_TP_FLUSH_SCAN_DC_N = 17955; // 3
+static const uint64_t SH_FLD_TP_FSI_CLKIN_SEL_DC = 17956; // 3
+static const uint64_t SH_FLD_TP_FSI_PROBE_SEL_DC = 17957; // 3
+static const uint64_t SH_FLD_TP_FSI_PROBE_SEL_DC_LEN = 17958; // 3
+static const uint64_t SH_FLD_TP_GLBCK_MEM_TESTCLK_SEL_DC = 17959; // 3
+static const uint64_t SH_FLD_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC = 17960; // 3
+static const uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC = 17961; // 3
+static const uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN = 17962; // 3
+static const uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC = 17963; // 3
+static const uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN = 17964; // 3
+static const uint64_t SH_FLD_TP_GPIO_PIB_TIMEOUT = 17965; // 3
+static const uint64_t SH_FLD_TP_GPIO_PIB_TIMEOUT_LEN = 17966; // 3
+static const uint64_t SH_FLD_TP_IDDQ_DC = 17967; // 3
+static const uint64_t SH_FLD_TP_IO_SPARE2_MCPRECOMP = 17968; // 1
+static const uint64_t SH_FLD_TP_IO_SPARE2_MCPRECOMP_LEN = 17969; // 1
+static const uint64_t SH_FLD_TP_IO_SPARE3_MCPRECOMP = 17970; // 1
+static const uint64_t SH_FLD_TP_IO_SPARE3_MCPRECOMP_LEN = 17971; // 1
+static const uint64_t SH_FLD_TP_IO_SPI_APSS_MCPRECOMP = 17972; // 1
+static const uint64_t SH_FLD_TP_IO_SPI_APSS_MCPRECOMP_LEN = 17973; // 1
+static const uint64_t SH_FLD_TP_IO_VSB_OP0A_V1P8_EN = 17974; // 3
+static const uint64_t SH_FLD_TP_IO_VSB_OP0B_V1P8_EN = 17975; // 3
+static const uint64_t SH_FLD_TP_IO_VSB_OP3A_V1P8_EN = 17976; // 3
+static const uint64_t SH_FLD_TP_IO_VSB_OP3B_V1P8_EN = 17977; // 3
+static const uint64_t SH_FLD_TP_LVLTRANS_FENCE_DC = 17978; // 3
+static const uint64_t SH_FLD_TP_NX_ALLOW_CRYPTO_DC = 17979; // 1
+static const uint64_t SH_FLD_TP_OSCSWITCH_VSB = 17980; // 3
+static const uint64_t SH_FLD_TP_OSCSWITCH_VSB_LEN = 17981; // 3
+static const uint64_t SH_FLD_TP_PB_FUSE_SPARE = 17982; // 1
+static const uint64_t SH_FLD_TP_PB_FUSE_TOPOLOGY_2CHIP = 17983; // 1
+static const uint64_t SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP = 17984; // 1
+static const uint64_t SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP_LEN = 17985; // 1
+static const uint64_t SH_FLD_TP_PCB_EP_RESET_DC = 17986; // 3
+static const uint64_t SH_FLD_TP_PCB_PM_MUX_SEL_DC = 17987; // 3
+static const uint64_t SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC = 17988; // 3
+static const uint64_t SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC_LEN = 17989; // 3
+static const uint64_t SH_FLD_TP_PIB_TRACE_MODE_DATA_DC = 17990; // 3
+static const uint64_t SH_FLD_TP_PIB_VSB_DISABLE_PARITY_DC = 17991; // 3
+static const uint64_t SH_FLD_TP_PIB_VSB_SBE_TRACE_MODE = 17992; // 3
+static const uint64_t SH_FLD_TP_PLLBYP_DC = 17993; // 3
+static const uint64_t SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC = 17994; // 3
+static const uint64_t SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC_LEN = 17995; // 3
+static const uint64_t SH_FLD_TP_PLLRST_DC = 17996; // 3
+static const uint64_t SH_FLD_TP_PLL_CLKIN_SEL1_DC = 17997; // 3
+static const uint64_t SH_FLD_TP_PLL_CLKIN_SEL2_DC = 17998; // 3
+static const uint64_t SH_FLD_TP_PLL_CLKIN_SEL3_DC = 17999; // 3
+static const uint64_t SH_FLD_TP_PLL_CLKIN_SEL4_DC = 18000; // 3
+static const uint64_t SH_FLD_TP_PLL_FORCE_OUT_EN_DC = 18001; // 3
+static const uint64_t SH_FLD_TP_PLL_TEST_EN = 18002; // 3
+static const uint64_t SH_FLD_TP_PLL_TEST_EN_DC = 18003; // 3
+static const uint64_t SH_FLD_TP_PROBE0_SEL_DC = 18004; // 3
+static const uint64_t SH_FLD_TP_PROBE0_SEL_DC_LEN = 18005; // 3
+static const uint64_t SH_FLD_TP_PROBE1_SEL_DC = 18006; // 3
+static const uint64_t SH_FLD_TP_PROBE1_SEL_DC_LEN = 18007; // 3
+static const uint64_t SH_FLD_TP_PROBE_DRV_EN_DC = 18008; // 3
+static const uint64_t SH_FLD_TP_PROBE_HIGHDRIVE_DC = 18009; // 3
+static const uint64_t SH_FLD_TP_PROBE_MESH_SEL_DC = 18010; // 3
+static const uint64_t SH_FLD_TP_RESCLK_DIS_DC = 18011; // 3
+static const uint64_t SH_FLD_TP_RI_DC_B = 18012; // 3
+static const uint64_t SH_FLD_TP_RI_DC_N = 18013; // 3
+static const uint64_t SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC = 18014; // 3
+static const uint64_t SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC_LEN = 18015; // 3
+static const uint64_t SH_FLD_TP_SS0_PLL_BYPASS = 18016; // 3
+static const uint64_t SH_FLD_TP_SS0_PLL_RESET = 18017; // 3
+static const uint64_t SH_FLD_TP_SS0_PLL_TEST_EN = 18018; // 3
+static const uint64_t SH_FLD_TP_TEST_BURNIN_MODE_DC = 18019; // 3
+static const uint64_t SH_FLD_TP_TPCPERV_VSB_TRACE_STOP = 18020; // 3
+static const uint64_t SH_FLD_TP_TPFSI_ACK = 18021; // 43
+static const uint64_t SH_FLD_TP_VITL_ACT_DIS_DC = 18022; // 3
+static const uint64_t SH_FLD_TP_VITL_CLKOFF_DC = 18023; // 3
+static const uint64_t SH_FLD_TP_VITL_DELAY_LCLKR_DC = 18024; // 3
+static const uint64_t SH_FLD_TP_VITL_MPW1_DC_N = 18025; // 3
+static const uint64_t SH_FLD_TP_VITL_MPW2_DC_N = 18026; // 3
+static const uint64_t SH_FLD_TP_VITL_MPW3_DC_N = 18027; // 3
+static const uint64_t SH_FLD_TP_VITL_SCAN_CLK_DC = 18028; // 3
+static const uint64_t SH_FLD_TP_VITL_SCIN_DC = 18029; // 3
+static const uint64_t SH_FLD_TRACE_BUS_BITS_0_63 = 18030; // 1
+static const uint64_t SH_FLD_TRACE_BUS_BITS_0_63_LEN = 18031; // 1
+static const uint64_t SH_FLD_TRACE_BUS_BITS_64_87 = 18032; // 1
+static const uint64_t SH_FLD_TRACE_BUS_BITS_64_87_LEN = 18033; // 1
+static const uint64_t SH_FLD_TRACE_BUS_EN = 18034; // 1
+static const uint64_t SH_FLD_TRACE_BUS_SEL_0_1 = 18035; // 1
+static const uint64_t SH_FLD_TRACE_BUS_SEL_0_1_LEN = 18036; // 1
+static const uint64_t SH_FLD_TRACE_BUS_TRIGGER_BITS = 18037; // 1
+static const uint64_t SH_FLD_TRACE_BUS_TRIGGER_BITS_LEN = 18038; // 1
+static const uint64_t SH_FLD_TRACE_DATA_SEL = 18039; // 16
+static const uint64_t SH_FLD_TRACE_DATA_SELECT = 18040; // 1
+static const uint64_t SH_FLD_TRACE_DATA_SELECT_LEN = 18041; // 1
+static const uint64_t SH_FLD_TRACE_DATA_SEL_LEN = 18042; // 16
+static const uint64_t SH_FLD_TRACE_DISABLE = 18043; // 1
+static const uint64_t SH_FLD_TRACE_ENABLE = 18044; // 7
+static const uint64_t SH_FLD_TRACE_EVENT = 18045; // 1
+static const uint64_t SH_FLD_TRACE_MODE_SEL = 18046; // 16
+static const uint64_t SH_FLD_TRACE_MODE_SEL_LEN = 18047; // 16
+static const uint64_t SH_FLD_TRACE_MUX_SEL = 18048; // 1
+static const uint64_t SH_FLD_TRACE_SEL = 18049; // 87
+static const uint64_t SH_FLD_TRACE_SELECT = 18050; // 2
+static const uint64_t SH_FLD_TRACE_SELECT_LEN = 18051; // 2
+static const uint64_t SH_FLD_TRACE_SEL_0_1 = 18052; // 1
+static const uint64_t SH_FLD_TRACE_SEL_0_1_LEN = 18053; // 1
+static const uint64_t SH_FLD_TRACE_SEL_LEN = 18054; // 44
+static const uint64_t SH_FLD_TRACE_TRIGGER = 18055; // 1
+static const uint64_t SH_FLD_TRACKING_TIMEOUT_SEL = 18056; // 6
+static const uint64_t SH_FLD_TRACKING_TIMEOUT_SEL_LEN = 18057; // 6
+static const uint64_t SH_FLD_TRAIN = 18058; // 10
+static const uint64_t SH_FLD_TRAIN_A_ADJ = 18059; // 2
+static const uint64_t SH_FLD_TRAIN_A_ADJ_LEN = 18060; // 2
+static const uint64_t SH_FLD_TRAIN_A_HYST = 18061; // 2
+static const uint64_t SH_FLD_TRAIN_A_HYST_LEN = 18062; // 2
+static const uint64_t SH_FLD_TRAIN_B_ADJ = 18063; // 2
+static const uint64_t SH_FLD_TRAIN_B_ADJ_LEN = 18064; // 2
+static const uint64_t SH_FLD_TRAIN_B_HYST = 18065; // 2
+static const uint64_t SH_FLD_TRAIN_B_HYST_LEN = 18066; // 2
+static const uint64_t SH_FLD_TRAIN_LEN = 18067; // 10
+static const uint64_t SH_FLD_TRAIN_TIME = 18068; // 2
+static const uint64_t SH_FLD_TRAIN_TIME_LEN = 18069; // 2
+static const uint64_t SH_FLD_TRANSPORT_INFORMATIONAL_ERR = 18070; // 4
+static const uint64_t SH_FLD_TRANS_DELAY = 18071; // 1
+static const uint64_t SH_FLD_TRANS_DELAY_LEN = 18072; // 1
+static const uint64_t SH_FLD_TRAPPED_DL_RETURN_P0 = 18073; // 43
+static const uint64_t SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY = 18074; // 43
+static const uint64_t SH_FLD_TRAPPED_GENERAL_TIMEOUT = 18075; // 43
+static const uint64_t SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID = 18076; // 43
+static const uint64_t SH_FLD_TRAPPED_PARALLEL_READ_NVLD = 18077; // 43
+static const uint64_t SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD = 18078; // 43
+static const uint64_t SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 18079; // 43
+static const uint64_t SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE = 18080; // 43
+static const uint64_t SH_FLD_TRAPPED_PCB_ADDRESS_PARITY = 18081; // 43
+static const uint64_t SH_FLD_TRAPPED_PCB_COMMAND_PARITY = 18082; // 43
+static const uint64_t SH_FLD_TRAPPED_PCB_WDATA_PARITY = 18083; // 43
+static const uint64_t SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 18084; // 43
+static const uint64_t SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 18085; // 43
+static const uint64_t SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 18086; // 43
+static const uint64_t SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 18087; // 43
+static const uint64_t SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 18088; // 43
+static const uint64_t SH_FLD_TRAPPED_UL_P0 = 18089; // 43
+static const uint64_t SH_FLD_TRAPPED_UL_RDATA_PARITY = 18090; // 43
+static const uint64_t SH_FLD_TRASH_EN = 18091; // 12
+static const uint64_t SH_FLD_TRCD_CYCLES = 18092; // 8
+static const uint64_t SH_FLD_TRCD_CYCLES_LEN = 18093; // 8
+static const uint64_t SH_FLD_TRC_CMD_OVERRUN = 18094; // 1
+static const uint64_t SH_FLD_TRC_CYCLES = 18095; // 8
+static const uint64_t SH_FLD_TRC_CYCLES_LEN = 18096; // 8
+static const uint64_t SH_FLD_TRC_MODE = 18097; // 6
+static const uint64_t SH_FLD_TRC_MODE_LEN = 18098; // 6
+static const uint64_t SH_FLD_TRFC_CYCLES = 18099; // 8
+static const uint64_t SH_FLD_TRFC_CYCLES_LEN = 18100; // 8
+static const uint64_t SH_FLD_TRIG = 18101; // 17
+static const uint64_t SH_FLD_TRIG0_AND_MASK = 18102; // 90
+static const uint64_t SH_FLD_TRIG0_AND_MASK_LEN = 18103; // 90
+static const uint64_t SH_FLD_TRIG0_LEVEL_SEL = 18104; // 43
+static const uint64_t SH_FLD_TRIG0_LEVEL_SEL_LEN = 18105; // 43
+static const uint64_t SH_FLD_TRIG0_NOT_MODE = 18106; // 90
+static const uint64_t SH_FLD_TRIG0_OR_MASK = 18107; // 90
+static const uint64_t SH_FLD_TRIG0_OR_MASK_LEN = 18108; // 90
+static const uint64_t SH_FLD_TRIG1_AND_MASK = 18109; // 90
+static const uint64_t SH_FLD_TRIG1_AND_MASK_LEN = 18110; // 90
+static const uint64_t SH_FLD_TRIG1_LEVEL_SEL = 18111; // 43
+static const uint64_t SH_FLD_TRIG1_LEVEL_SEL_LEN = 18112; // 43
+static const uint64_t SH_FLD_TRIG1_NOT_MODE = 18113; // 90
+static const uint64_t SH_FLD_TRIG1_OR_MASK = 18114; // 90
+static const uint64_t SH_FLD_TRIG1_OR_MASK_LEN = 18115; // 90
+static const uint64_t SH_FLD_TRIGGER = 18116; // 55
+static const uint64_t SH_FLD_TRIGGER1 = 18117; // 24
+static const uint64_t SH_FLD_TRIGGERED = 18118; // 1
+static const uint64_t SH_FLD_TRIGGER_ON_UNIT0_SYNC_LVL = 18119; // 43
+static const uint64_t SH_FLD_TRIGGER_ON_UNIT1_SYNC_LVL = 18120; // 43
+static const uint64_t SH_FLD_TRIGGER_OPCG_ON = 18121; // 129
+static const uint64_t SH_FLD_TRIG_FIR_HMI = 18122; // 96
+static const uint64_t SH_FLD_TRIG_SEL = 18123; // 86
+static const uint64_t SH_FLD_TRP_CYCLES = 18124; // 8
+static const uint64_t SH_FLD_TRP_CYCLES_LEN = 18125; // 8
+static const uint64_t SH_FLD_TRRD = 18126; // 8
+static const uint64_t SH_FLD_TRRD_LEN = 18127; // 8
+static const uint64_t SH_FLD_TRRD_SBG = 18128; // 8
+static const uint64_t SH_FLD_TRRD_SBG_LEN = 18129; // 8
+static const uint64_t SH_FLD_TRST_B_EQ0_ERR = 18130; // 1
+static const uint64_t SH_FLD_TRY_ATR_RO = 18131; // 1
+static const uint64_t SH_FLD_TSIZE = 18132; // 25
+static const uint64_t SH_FLD_TSIZE_4_6 = 18133; // 1
+static const uint64_t SH_FLD_TSIZE_4_6_LEN = 18134; // 1
+static const uint64_t SH_FLD_TSIZE_LEN = 18135; // 24
+static const uint64_t SH_FLD_TSIZE_MASK = 18136; // 8
+static const uint64_t SH_FLD_TSIZE_MASK_LEN = 18137; // 8
+static const uint64_t SH_FLD_TSIZE_MATCH = 18138; // 8
+static const uint64_t SH_FLD_TSIZE_MATCH_LEN = 18139; // 8
+static const uint64_t SH_FLD_TTAG_PARITY = 18140; // 2
+static const uint64_t SH_FLD_TTAG_PARITY_ERROR = 18141; // 2
+static const uint64_t SH_FLD_TTYPE = 18142; // 24
+static const uint64_t SH_FLD_TTYPE_LEN = 18143; // 24
+static const uint64_t SH_FLD_TTYPE_MATCH = 18144; // 8
+static const uint64_t SH_FLD_TTYPE_MATCH_LEN = 18145; // 8
+static const uint64_t SH_FLD_TTYPE_REPLACE = 18146; // 8
+static const uint64_t SH_FLD_TTYPE_REPLACE_LEN = 18147; // 8
+static const uint64_t SH_FLD_TVT0_PAGE_SIZE = 18148; // 1
+static const uint64_t SH_FLD_TVT0_PAGE_SIZE_LEN = 18149; // 1
+static const uint64_t SH_FLD_TVT0_SPARE = 18150; // 1
+static const uint64_t SH_FLD_TVT0_SPARE_LEN = 18151; // 1
+static const uint64_t SH_FLD_TVT0_TABLE_LEVEL = 18152; // 1
+static const uint64_t SH_FLD_TVT0_TABLE_LEVEL_LEN = 18153; // 1
+static const uint64_t SH_FLD_TVT0_TABLE_SIZE = 18154; // 1
+static const uint64_t SH_FLD_TVT0_TABLE_SIZE_LEN = 18155; // 1
+static const uint64_t SH_FLD_TVT0_XLAT_ADDR = 18156; // 1
+static const uint64_t SH_FLD_TVT0_XLAT_ADDR_LEN = 18157; // 1
+static const uint64_t SH_FLD_TVT_ADDR_RANGE_ERR_ESR = 18158; // 1
+static const uint64_t SH_FLD_TVT_ENTRY_INVALID_ESR = 18159; // 1
+static const uint64_t SH_FLD_TVT_PERR_ESR = 18160; // 1
+static const uint64_t SH_FLD_TWLDQSEN_CYCLES = 18161; // 8
+static const uint64_t SH_FLD_TWLDQSEN_CYCLES_LEN = 18162; // 8
+static const uint64_t SH_FLD_TWLO_TWLOE = 18163; // 8
+static const uint64_t SH_FLD_TWLO_TWLOE_LEN = 18164; // 8
+static const uint64_t SH_FLD_TWO_CYCLE_ADDR_EN = 18165; // 8
+static const uint64_t SH_FLD_TWO_TFMRCMDS_ERR_ERRHOLD = 18166; // 2
+static const uint64_t SH_FLD_TWRMRD_CYCLES = 18167; // 8
+static const uint64_t SH_FLD_TWRMRD_CYCLES_LEN = 18168; // 8
+static const uint64_t SH_FLD_TWSM_DIS = 18169; // 1
+static const uint64_t SH_FLD_TWSM_DIS_LEN = 18170; // 1
+static const uint64_t SH_FLD_TW_ADD_ERR_CR_RD_DET = 18171; // 1
+static const uint64_t SH_FLD_TW_ADD_ERR_CR_WR_DET = 18172; // 1
+static const uint64_t SH_FLD_TW_ATT_HPT_SAO_FOLD_DIS = 18173; // 1
+static const uint64_t SH_FLD_TW_ATT_RDX_NIO_FOLD_DIS = 18174; // 1
+static const uint64_t SH_FLD_TW_ATT_RDX_SAO_FOLD_DIS = 18175; // 1
+static const uint64_t SH_FLD_TW_ATT_RDX_TIO_FOLD_DIS = 18176; // 1
+static const uint64_t SH_FLD_TW_BUS0_STG0_SEL = 18177; // 1
+static const uint64_t SH_FLD_TW_BUS0_STG0_SEL_LEN = 18178; // 1
+static const uint64_t SH_FLD_TW_BUS0_STG1_SEL = 18179; // 1
+static const uint64_t SH_FLD_TW_BUS0_STG2_SEL = 18180; // 1
+static const uint64_t SH_FLD_TW_BUS1_STG0_SEL = 18181; // 1
+static const uint64_t SH_FLD_TW_BUS1_STG0_SEL_LEN = 18182; // 1
+static const uint64_t SH_FLD_TW_BUS1_STG1_SEL = 18183; // 1
+static const uint64_t SH_FLD_TW_BUS1_STG2_SEL = 18184; // 1
+static const uint64_t SH_FLD_TW_CXT_CAC_DIS = 18185; // 1
+static const uint64_t SH_FLD_TW_CXT_CAC_PERR_DET = 18186; // 1
+static const uint64_t SH_FLD_TW_FOREIGN_ADDR_DET = 18187; // 1
+static const uint64_t SH_FLD_TW_INVALID_WIMG_DET = 18188; // 1
+static const uint64_t SH_FLD_TW_INV_RDX_QUAD_DET = 18189; // 1
+static const uint64_t SH_FLD_TW_LCO_RDX_C_DIS = 18190; // 1
+static const uint64_t SH_FLD_TW_LCO_RDX_EN = 18191; // 1
+static const uint64_t SH_FLD_TW_LCO_RDX_PDE_EN = 18192; // 1
+static const uint64_t SH_FLD_TW_LCO_RDX_PWC_L2_DIS = 18193; // 1
+static const uint64_t SH_FLD_TW_LCO_RDX_PWC_L3_DIS = 18194; // 1
+static const uint64_t SH_FLD_TW_LCO_RDX_PWC_L4_DIS = 18195; // 1
+static const uint64_t SH_FLD_TW_LCO_RDX_P_DIS = 18196; // 1
+static const uint64_t SH_FLD_TW_MPSS_DIS = 18197; // 1
+static const uint64_t SH_FLD_TW_PG_FAULT_BPCHK_DET = 18198; // 1
+static const uint64_t SH_FLD_TW_PG_FAULT_NOPTE_DET = 18199; // 1
+static const uint64_t SH_FLD_TW_PG_FAULT_SEID_DET = 18200; // 1
+static const uint64_t SH_FLD_TW_PG_FAULT_VPCHK_DET = 18201; // 1
+static const uint64_t SH_FLD_TW_PREFETCH_ABT_DET = 18202; // 1
+static const uint64_t SH_FLD_TW_PROT_ERR_CHK_DIS = 18203; // 1
+static const uint64_t SH_FLD_TW_PTE_UPD_FAIL_DET = 18204; // 1
+static const uint64_t SH_FLD_TW_PTE_UPD_INTR_EN = 18205; // 1
+static const uint64_t SH_FLD_TW_RDX_CFG_GUEST_DET = 18206; // 1
+static const uint64_t SH_FLD_TW_RDX_CFG_HOST_DET = 18207; // 1
+static const uint64_t SH_FLD_TW_RDX_INT_PWC_DIS = 18208; // 1
+static const uint64_t SH_FLD_TW_RDX_INT_TLB_DIS = 18209; // 1
+static const uint64_t SH_FLD_TW_RDX_PWC_DIS = 18210; // 1
+static const uint64_t SH_FLD_TW_RDX_PWC_PERR_DET = 18211; // 1
+static const uint64_t SH_FLD_TW_RDX_PWC_SPLIT_EN = 18212; // 1
+static const uint64_t SH_FLD_TW_RDX_PWC_VA_HASH = 18213; // 1
+static const uint64_t SH_FLD_TW_SEG_FAULT_DET = 18214; // 1
+static const uint64_t SH_FLD_TW_SM_CTL_ERR_DET = 18215; // 1
+static const uint64_t SH_FLD_TW_TIMEOUT_CHK_DIS = 18216; // 1
+static const uint64_t SH_FLD_TW_TIMEOUT_ERR_DET = 18217; // 1
+static const uint64_t SH_FLD_TXAERR = 18218; // 6
+static const uint64_t SH_FLD_TXBERR = 18219; // 6
+static const uint64_t SH_FLD_TXCERR = 18220; // 6
+static const uint64_t SH_FLD_TXDERR = 18221; // 6
+static const uint64_t SH_FLD_TXEERR = 18222; // 6
+static const uint64_t SH_FLD_TXFERR = 18223; // 6
+static const uint64_t SH_FLD_TXGERR = 18224; // 6
+static const uint64_t SH_FLD_TXHERR = 18225; // 6
+static const uint64_t SH_FLD_TXIERR = 18226; // 6
+static const uint64_t SH_FLD_TXJERR = 18227; // 6
+static const uint64_t SH_FLD_TXKERR = 18228; // 6
+static const uint64_t SH_FLD_TXLERR = 18229; // 6
+static const uint64_t SH_FLD_TXMERR = 18230; // 6
+static const uint64_t SH_FLD_TXNERR = 18231; // 6
+static const uint64_t SH_FLD_TXOERR = 18232; // 6
+static const uint64_t SH_FLD_TXPERR = 18233; // 6
+static const uint64_t SH_FLD_TX_BUS_WIDTH = 18234; // 4
+static const uint64_t SH_FLD_TX_BUS_WIDTH_LEN = 18235; // 4
+static const uint64_t SH_FLD_TX_BW = 18236; // 10
+static const uint64_t SH_FLD_TX_BW_LEN = 18237; // 10
+static const uint64_t SH_FLD_TX_DATA_ECC_CORR_ENA = 18238; // 6
+static const uint64_t SH_FLD_TX_ECC_DATA_POISON_ENA = 18239; // 6
+static const uint64_t SH_FLD_TX_SLS_DISABLE = 18240; // 4
+static const uint64_t SH_FLD_TX_TFMR_CORRUPT_ERRHOLD = 18241; // 2
+static const uint64_t SH_FLD_TX_TRISTATE = 18242; // 8
+static const uint64_t SH_FLD_TX_TTYPE_PIB_MST_FSM_STATE_DISABLE = 18243; // 1
+static const uint64_t SH_FLD_TX_TTYPE_PIB_MST_IF_RESET = 18244; // 1
+static const uint64_t SH_FLD_TYPE = 18245; // 108
+static const uint64_t SH_FLD_TYPE_LEN = 18246; // 44
+static const uint64_t SH_FLD_TZQCS_CYCLES = 18247; // 8
+static const uint64_t SH_FLD_TZQCS_CYCLES_LEN = 18248; // 8
+static const uint64_t SH_FLD_TZQINIT_CYCLES = 18249; // 8
+static const uint64_t SH_FLD_TZQINIT_CYCLES_LEN = 18250; // 8
+static const uint64_t SH_FLD_UE = 18251; // 10
+static const uint64_t SH_FLD_UE1_0_OUT = 18252; // 4
+static const uint64_t SH_FLD_UE1_1_OUT = 18253; // 4
+static const uint64_t SH_FLD_UE1_2_OUT = 18254; // 4
+static const uint64_t SH_FLD_UE1_3_OUT = 18255; // 4
+static const uint64_t SH_FLD_UE1_4_OUT = 18256; // 4
+static const uint64_t SH_FLD_UE1_5_OUT = 18257; // 4
+static const uint64_t SH_FLD_UE1_6_OUT = 18258; // 4
+static const uint64_t SH_FLD_UE1_7_OUT = 18259; // 4
+static const uint64_t SH_FLD_UE2_0_OUT = 18260; // 4
+static const uint64_t SH_FLD_UE2_1_OUT = 18261; // 4
+static const uint64_t SH_FLD_UE2_2_OUT = 18262; // 4
+static const uint64_t SH_FLD_UE2_3_OUT = 18263; // 4
+static const uint64_t SH_FLD_UE2_4_OUT = 18264; // 4
+static const uint64_t SH_FLD_UE2_5_OUT = 18265; // 4
+static const uint64_t SH_FLD_UE2_6_OUT = 18266; // 4
+static const uint64_t SH_FLD_UE2_7_OUT = 18267; // 4
+static const uint64_t SH_FLD_UE_COUNT = 18268; // 2
+static const uint64_t SH_FLD_UE_COUNT_LEN = 18269; // 2
+static const uint64_t SH_FLD_UE_DISABLE = 18270; // 2
+static const uint64_t SH_FLD_UE_LEN = 18271; // 10
+static const uint64_t SH_FLD_UL_P0 = 18272; // 43
+static const uint64_t SH_FLD_UL_RDATA_PARITY = 18273; // 43
+static const uint64_t SH_FLD_UMAC_CRB_SUE = 18274; // 1
+static const uint64_t SH_FLD_UMAC_CRB_UE = 18275; // 1
+static const uint64_t SH_FLD_UMAC_LD_LINK_ERR = 18276; // 1
+static const uint64_t SH_FLD_UMAC_LINK_ABORT = 18277; // 1
+static const uint64_t SH_FLD_UMAC_MUX_SELECT = 18278; // 1
+static const uint64_t SH_FLD_UMAC_MUX_SELECT_LEN = 18279; // 1
+static const uint64_t SH_FLD_UMAC_RD_DISABLE_GROUP = 18280; // 1
+static const uint64_t SH_FLD_UMAC_RD_DISABLE_LN = 18281; // 1
+static const uint64_t SH_FLD_UMAC_RD_DISABLE_NN_RN = 18282; // 1
+static const uint64_t SH_FLD_UMAC_RD_DISABLE_VG_NOT_SYS = 18283; // 1
+static const uint64_t SH_FLD_UMAC_WC_INT_ADDR_UE = 18284; // 1
+static const uint64_t SH_FLD_UMAC_WR_DISABLE_GROUP = 18285; // 1
+static const uint64_t SH_FLD_UMAC_WR_DISABLE_LN = 18286; // 1
+static const uint64_t SH_FLD_UMAC_WR_DISABLE_NN_RN = 18287; // 1
+static const uint64_t SH_FLD_UMAC_WR_DISABLE_VG_NOT_SYS = 18288; // 1
+static const uint64_t SH_FLD_UNCORR_ERROR = 18289; // 1
+static const uint64_t SH_FLD_UNEXPECTED_PB = 18290; // 4
+static const uint64_t SH_FLD_UNEXPECT_DATA = 18291; // 1
+static const uint64_t SH_FLD_UNIT1 = 18292; // 215
+static const uint64_t SH_FLD_UNIT10 = 18293; // 215
+static const uint64_t SH_FLD_UNIT2 = 18294; // 215
+static const uint64_t SH_FLD_UNIT3 = 18295; // 215
+static const uint64_t SH_FLD_UNIT4 = 18296; // 215
+static const uint64_t SH_FLD_UNIT5 = 18297; // 215
+static const uint64_t SH_FLD_UNIT6 = 18298; // 215
+static const uint64_t SH_FLD_UNIT7 = 18299; // 215
+static const uint64_t SH_FLD_UNIT8 = 18300; // 215
+static const uint64_t SH_FLD_UNIT9 = 18301; // 215
+static const uint64_t SH_FLD_UNIT_REGION_CLKCMD_DISABLE = 18302; // 43
+static const uint64_t SH_FLD_UNLOAD_CLK_DISABLE = 18303; // 116
+static const uint64_t SH_FLD_UNLOAD_SEL = 18304; // 116
+static const uint64_t SH_FLD_UNLOAD_SEL_LEN = 18305; // 116
+static const uint64_t SH_FLD_UNRECOV = 18306; // 10
+static const uint64_t SH_FLD_UNRECOV_LEN = 18307; // 10
+static const uint64_t SH_FLD_UNSOLICITED_CRESP = 18308; // 3
+static const uint64_t SH_FLD_UNSOLICITED_DATA_RCV_ERRHOLD = 18309; // 2
+static const uint64_t SH_FLD_UNSOLICITED_PBDATA = 18310; // 1
+static const uint64_t SH_FLD_UNTRUSTED = 18311; // 4
+static const uint64_t SH_FLD_UNTRUSTED_LEN = 18312; // 4
+static const uint64_t SH_FLD_UNUSED = 18313; // 351
+static const uint64_t SH_FLD_UNUSED0 = 18314; // 3
+static const uint64_t SH_FLD_UNUSED0A = 18315; // 3
+static const uint64_t SH_FLD_UNUSED0B = 18316; // 3
+static const uint64_t SH_FLD_UNUSED0B_LEN = 18317; // 3
+static const uint64_t SH_FLD_UNUSED0_LEN = 18318; // 2
+static const uint64_t SH_FLD_UNUSED1 = 18319; // 55
+static const uint64_t SH_FLD_UNUSED1119 = 18320; // 43
+static const uint64_t SH_FLD_UNUSED1119_LEN = 18321; // 43
+static const uint64_t SH_FLD_UNUSED1520 = 18322; // 43
+static const uint64_t SH_FLD_UNUSED1520_LEN = 18323; // 43
+static const uint64_t SH_FLD_UNUSED1A = 18324; // 3
+static const uint64_t SH_FLD_UNUSED1B = 18325; // 3
+static const uint64_t SH_FLD_UNUSED1B_LEN = 18326; // 3
+static const uint64_t SH_FLD_UNUSED1_LEN = 18327; // 52
+static const uint64_t SH_FLD_UNUSED2 = 18328; // 55
+static const uint64_t SH_FLD_UNUSED23_31 = 18329; // 7
+static const uint64_t SH_FLD_UNUSED23_31_LEN = 18330; // 7
+static const uint64_t SH_FLD_UNUSED2_LEN = 18331; // 44
+static const uint64_t SH_FLD_UNUSED3 = 18332; // 11
+static const uint64_t SH_FLD_UNUSED3_LEN = 18333; // 6
+static const uint64_t SH_FLD_UNUSED4 = 18334; // 14
+static const uint64_t SH_FLD_UNUSED41_63 = 18335; // 43
+static const uint64_t SH_FLD_UNUSED41_63_LEN = 18336; // 43
+static const uint64_t SH_FLD_UNUSED46 = 18337; // 43
+static const uint64_t SH_FLD_UNUSED4_LEN = 18338; // 6
+static const uint64_t SH_FLD_UNUSED5 = 18339; // 12
+static const uint64_t SH_FLD_UNUSED50 = 18340; // 2
+static const uint64_t SH_FLD_UNUSED51 = 18341; // 2
+static const uint64_t SH_FLD_UNUSED5_LEN = 18342; // 5
+static const uint64_t SH_FLD_UNUSED63 = 18343; // 3
+static const uint64_t SH_FLD_UNUSED88 = 18344; // 3
+static const uint64_t SH_FLD_UNUSED88_LEN = 18345; // 3
+static const uint64_t SH_FLD_UNUSED_0 = 18346; // 44
+static const uint64_t SH_FLD_UNUSED_0B = 18347; // 43
+static const uint64_t SH_FLD_UNUSED_0D = 18348; // 17
+static const uint64_t SH_FLD_UNUSED_1 = 18349; // 44
+static const uint64_t SH_FLD_UNUSED_10B = 18350; // 17
+static const uint64_t SH_FLD_UNUSED_11B = 18351; // 18
+static const uint64_t SH_FLD_UNUSED_12B = 18352; // 19
+static const uint64_t SH_FLD_UNUSED_13B = 18353; // 19
+static const uint64_t SH_FLD_UNUSED_14B = 18354; // 43
+static const uint64_t SH_FLD_UNUSED_16_22 = 18355; // 1
+static const uint64_t SH_FLD_UNUSED_16_22_LEN = 18356; // 1
+static const uint64_t SH_FLD_UNUSED_17B = 18357; // 43
+static const uint64_t SH_FLD_UNUSED_18B = 18358; // 43
+static const uint64_t SH_FLD_UNUSED_19B = 18359; // 43
+static const uint64_t SH_FLD_UNUSED_1B = 18360; // 43
+static const uint64_t SH_FLD_UNUSED_1D = 18361; // 17
+static const uint64_t SH_FLD_UNUSED_2 = 18362; // 87
+static const uint64_t SH_FLD_UNUSED_20B = 18363; // 42
+static const uint64_t SH_FLD_UNUSED_21B = 18364; // 43
+static const uint64_t SH_FLD_UNUSED_22B = 18365; // 43
+static const uint64_t SH_FLD_UNUSED_23B = 18366; // 43
+static const uint64_t SH_FLD_UNUSED_24B = 18367; // 43
+static const uint64_t SH_FLD_UNUSED_25B = 18368; // 43
+static const uint64_t SH_FLD_UNUSED_26B = 18369; // 43
+static const uint64_t SH_FLD_UNUSED_26_31 = 18370; // 1
+static const uint64_t SH_FLD_UNUSED_26_31_LEN = 18371; // 1
+static const uint64_t SH_FLD_UNUSED_27B = 18372; // 43
+static const uint64_t SH_FLD_UNUSED_28B = 18373; // 43
+static const uint64_t SH_FLD_UNUSED_29B = 18374; // 43
+static const uint64_t SH_FLD_UNUSED_2B = 18375; // 43
+static const uint64_t SH_FLD_UNUSED_2D = 18376; // 17
+static const uint64_t SH_FLD_UNUSED_2_LEN = 18377; // 86
+static const uint64_t SH_FLD_UNUSED_3 = 18378; // 1
+static const uint64_t SH_FLD_UNUSED_30B = 18379; // 43
+static const uint64_t SH_FLD_UNUSED_31B = 18380; // 43
+static const uint64_t SH_FLD_UNUSED_39_43 = 18381; // 1
+static const uint64_t SH_FLD_UNUSED_39_43_LEN = 18382; // 1
+static const uint64_t SH_FLD_UNUSED_3D = 18383; // 17
+static const uint64_t SH_FLD_UNUSED_47_51 = 18384; // 1
+static const uint64_t SH_FLD_UNUSED_47_51_LEN = 18385; // 1
+static const uint64_t SH_FLD_UNUSED_4_15 = 18386; // 1
+static const uint64_t SH_FLD_UNUSED_4_15_LEN = 18387; // 1
+static const uint64_t SH_FLD_UNUSED_53 = 18388; // 1
+static const uint64_t SH_FLD_UNUSED_5B = 18389; // 7
+static const uint64_t SH_FLD_UNUSED_6B = 18390; // 7
+static const uint64_t SH_FLD_UNUSED_7B = 18391; // 7
+static const uint64_t SH_FLD_UNUSED_8B = 18392; // 12
+static const uint64_t SH_FLD_UNUSED_8_14 = 18393; // 1
+static const uint64_t SH_FLD_UNUSED_8_14_LEN = 18394; // 1
+static const uint64_t SH_FLD_UNUSED_9B = 18395; // 15
+static const uint64_t SH_FLD_UNUSED_LEN = 18396; // 178
+static const uint64_t SH_FLD_UPDATE_COMPLETE = 18397; // 6
+static const uint64_t SH_FLD_UPDATE_ERR = 18398; // 2
+static const uint64_t SH_FLD_UPSTREAM = 18399; // 4
+static const uint64_t SH_FLD_USERDEF_CFG = 18400; // 6
+static const uint64_t SH_FLD_USERDEF_CFG_LEN = 18401; // 6
+static const uint64_t SH_FLD_USERDEF_TIMEOUT = 18402; // 6
+static const uint64_t SH_FLD_USERDEF_TIMEOUT_LEN = 18403; // 6
+static const uint64_t SH_FLD_USER_FILTER_MASK = 18404; // 6
+static const uint64_t SH_FLD_USER_FILTER_MASK_LEN = 18405; // 6
+static const uint64_t SH_FLD_USE_FOR_SCAN = 18406; // 43
+static const uint64_t SH_FLD_USE_OSC_OBSERVATION = 18407; // 1
+static const uint64_t SH_FLD_USE_OSC_OBSERVATION_LEN = 18408; // 1
+static const uint64_t SH_FLD_USE_PECE = 18409; // 24
+static const uint64_t SH_FLD_USE_PECE_LEN = 18410; // 24
+static const uint64_t SH_FLD_USE_PREV_COARSE_VAL = 18411; // 4
+static const uint64_t SH_FLD_USE_REC_LIMIT = 18412; // 24
+static const uint64_t SH_FLD_USE_SLS_AS_SPR = 18413; // 4
+static const uint64_t SH_FLD_USE_TB_STEP_SYNC = 18414; // 1
+static const uint64_t SH_FLD_USE_TB_SYNC_MECHANISM = 18415; // 1
+static const uint64_t SH_FLD_USE_WATCH_TO_READ_CTRL_ARY = 18416; // 2
+static const uint64_t SH_FLD_UT = 18417; // 24
+static const uint64_t SH_FLD_VALID = 18418; // 68
+static const uint64_t SH_FLD_VALID_ATRGPA0 = 18419; // 256
+static const uint64_t SH_FLD_VALID_ATRGPA1 = 18420; // 256
+static const uint64_t SH_FLD_VALID_ATSD = 18421; // 256
+static const uint64_t SH_FLD_VALID_ENTRY = 18422; // 1
+static const uint64_t SH_FLD_VALUE = 18423; // 48
+static const uint64_t SH_FLD_VALUES0 = 18424; // 16
+static const uint64_t SH_FLD_VALUES0_LEN = 18425; // 16
+static const uint64_t SH_FLD_VALUES1 = 18426; // 16
+static const uint64_t SH_FLD_VALUES1_LEN = 18427; // 16
+static const uint64_t SH_FLD_VALUES2 = 18428; // 16
+static const uint64_t SH_FLD_VALUES2_LEN = 18429; // 16
+static const uint64_t SH_FLD_VALUES3 = 18430; // 16
+static const uint64_t SH_FLD_VALUES3_LEN = 18431; // 16
+static const uint64_t SH_FLD_VALUES4 = 18432; // 16
+static const uint64_t SH_FLD_VALUES4_LEN = 18433; // 16
+static const uint64_t SH_FLD_VALUES5 = 18434; // 16
+static const uint64_t SH_FLD_VALUES5_LEN = 18435; // 16
+static const uint64_t SH_FLD_VALUES6 = 18436; // 16
+static const uint64_t SH_FLD_VALUES6_LEN = 18437; // 16
+static const uint64_t SH_FLD_VALUES7 = 18438; // 16
+static const uint64_t SH_FLD_VALUES7_LEN = 18439; // 16
+static const uint64_t SH_FLD_VALUE_LEN = 18440; // 48
+static const uint64_t SH_FLD_VAS_LOCAL_XSTOP = 18441; // 1
+static const uint64_t SH_FLD_VBGENDOC = 18442; // 3
+static const uint64_t SH_FLD_VBGENDOC_LEN = 18443; // 3
+static const uint64_t SH_FLD_VCORANGE = 18444; // 10
+static const uint64_t SH_FLD_VCORANGE_LEN = 18445; // 10
+static const uint64_t SH_FLD_VCOSEL = 18446; // 10
+static const uint64_t SH_FLD_VCS_PFET_ENABLE_VALUE = 18447; // 30
+static const uint64_t SH_FLD_VCS_PFET_ENABLE_VALUE_LEN = 18448; // 30
+static const uint64_t SH_FLD_VCS_PFET_FORCE_STATE = 18449; // 30
+static const uint64_t SH_FLD_VCS_PFET_FORCE_STATE_LEN = 18450; // 30
+static const uint64_t SH_FLD_VCS_PFET_SEL_OVERRIDE = 18451; // 30
+static const uint64_t SH_FLD_VCS_PFET_SEL_VALUE = 18452; // 30
+static const uint64_t SH_FLD_VCS_PFET_SEL_VALUE_LEN = 18453; // 30
+static const uint64_t SH_FLD_VCS_PFET_VAL_OVERRIDE = 18454; // 30
+static const uint64_t SH_FLD_VCS_PG_SEL = 18455; // 30
+static const uint64_t SH_FLD_VCS_PG_SEL_LEN = 18456; // 30
+static const uint64_t SH_FLD_VCS_PG_STATE = 18457; // 30
+static const uint64_t SH_FLD_VCS_PG_STATE_LEN = 18458; // 30
+static const uint64_t SH_FLD_VCS_VOFF_SEL = 18459; // 30
+static const uint64_t SH_FLD_VCS_VOFF_SEL_LEN = 18460; // 30
+static const uint64_t SH_FLD_VC_CRD_AVAIL_PERR = 18461; // 1
+static const uint64_t SH_FLD_VC_CRD_PERR = 18462; // 1
+static const uint64_t SH_FLD_VC_FATAL_ERROR_0_1 = 18463; // 1
+static const uint64_t SH_FLD_VC_FATAL_ERROR_0_1_LEN = 18464; // 1
+static const uint64_t SH_FLD_VC_INFO_ERROR_0_1 = 18465; // 1
+static const uint64_t SH_FLD_VC_INFO_ERROR_0_1_LEN = 18466; // 1
+static const uint64_t SH_FLD_VC_PRIORITY_LIMIT_0_3 = 18467; // 1
+static const uint64_t SH_FLD_VC_PRIORITY_LIMIT_0_3_LEN = 18468; // 1
+static const uint64_t SH_FLD_VC_RECOV_ERROR_0_1 = 18469; // 1
+static const uint64_t SH_FLD_VC_RECOV_ERROR_0_1_LEN = 18470; // 1
+static const uint64_t SH_FLD_VDD2VIO_LVL_FENCE_DC = 18471; // 3
+static const uint64_t SH_FLD_VDD_NEST_OBSERVE = 18472; // 1
+static const uint64_t SH_FLD_VDD_PFET_ENABLE_VALUE = 18473; // 30
+static const uint64_t SH_FLD_VDD_PFET_ENABLE_VALUE_LEN = 18474; // 30
+static const uint64_t SH_FLD_VDD_PFET_FORCE_STATE = 18475; // 30
+static const uint64_t SH_FLD_VDD_PFET_FORCE_STATE_LEN = 18476; // 30
+static const uint64_t SH_FLD_VDD_PFET_REGULATION_FINGER_EN = 18477; // 30
+static const uint64_t SH_FLD_VDD_PFET_REGULATION_FINGER_VALUE = 18478; // 30
+static const uint64_t SH_FLD_VDD_PFET_SEL_OVERRIDE = 18479; // 30
+static const uint64_t SH_FLD_VDD_PFET_SEL_VALUE = 18480; // 30
+static const uint64_t SH_FLD_VDD_PFET_SEL_VALUE_LEN = 18481; // 30
+static const uint64_t SH_FLD_VDD_PFET_VAL_OVERRIDE = 18482; // 30
+static const uint64_t SH_FLD_VDD_PG_SEL = 18483; // 30
+static const uint64_t SH_FLD_VDD_PG_SEL_LEN = 18484; // 30
+static const uint64_t SH_FLD_VDD_PG_STATE = 18485; // 30
+static const uint64_t SH_FLD_VDD_PG_STATE_LEN = 18486; // 30
+static const uint64_t SH_FLD_VDD_VOFF_SEL = 18487; // 30
+static const uint64_t SH_FLD_VDD_VOFF_SEL_LEN = 18488; // 30
+static const uint64_t SH_FLD_VDM_DISABLE = 18489; // 30
+static const uint64_t SH_FLD_VDM_DROOP_LARGE = 18490; // 6
+static const uint64_t SH_FLD_VDM_DROOP_LARGE_LEN = 18491; // 6
+static const uint64_t SH_FLD_VDM_DROOP_SMALL = 18492; // 6
+static const uint64_t SH_FLD_VDM_DROOP_SMALL_LEN = 18493; // 6
+static const uint64_t SH_FLD_VDM_DROOP_XTREME = 18494; // 6
+static const uint64_t SH_FLD_VDM_DROOP_XTREME_LEN = 18495; // 6
+static const uint64_t SH_FLD_VDM_EXTREME_DROOP_CTR = 18496; // 12
+static const uint64_t SH_FLD_VDM_EXTREME_DROOP_CTR_LEN = 18497; // 12
+static const uint64_t SH_FLD_VDM_EXTREME_DROOP_THRESHOLD = 18498; // 12
+static const uint64_t SH_FLD_VDM_EXTREME_DROOP_THRESHOLD_LEN = 18499; // 12
+static const uint64_t SH_FLD_VDM_LARGE_DROOP_CTR = 18500; // 12
+static const uint64_t SH_FLD_VDM_LARGE_DROOP_CTR_LEN = 18501; // 12
+static const uint64_t SH_FLD_VDM_LARGE_DROOP_THRESHOLD = 18502; // 12
+static const uint64_t SH_FLD_VDM_LARGE_DROOP_THRESHOLD_LEN = 18503; // 12
+static const uint64_t SH_FLD_VDM_LCL_SAMPLE_EN = 18504; // 12
+static const uint64_t SH_FLD_VDM_NO_DROOP_CTR = 18505; // 12
+static const uint64_t SH_FLD_VDM_NO_DROOP_CTR_LEN = 18506; // 12
+static const uint64_t SH_FLD_VDM_OVERVOLT = 18507; // 6
+static const uint64_t SH_FLD_VDM_OVERVOLT_CTR = 18508; // 12
+static const uint64_t SH_FLD_VDM_OVERVOLT_CTR_LEN = 18509; // 12
+static const uint64_t SH_FLD_VDM_OVERVOLT_LEN = 18510; // 6
+static const uint64_t SH_FLD_VDM_POWERON = 18511; // 30
+static const uint64_t SH_FLD_VDM_SMALL_DROOP_CTR = 18512; // 12
+static const uint64_t SH_FLD_VDM_SMALL_DROOP_CTR_LEN = 18513; // 12
+static const uint64_t SH_FLD_VDM_SMALL_DROOP_THRESHOLD = 18514; // 12
+static const uint64_t SH_FLD_VDM_SMALL_DROOP_THRESHOLD_LEN = 18515; // 12
+static const uint64_t SH_FLD_VDM_VID_COMPARE = 18516; // 6
+static const uint64_t SH_FLD_VDM_VID_COMPARE_LEN = 18517; // 6
+static const uint64_t SH_FLD_VECTOR_GROUP_EPSILON = 18518; // 8
+static const uint64_t SH_FLD_VECTOR_GROUP_EPSILON_LEN = 18519; // 8
+static const uint64_t SH_FLD_VG = 18520; // 1
+static const uint64_t SH_FLD_VG_COUNT = 18521; // 2
+static const uint64_t SH_FLD_VG_COUNT_LEN = 18522; // 2
+static const uint64_t SH_FLD_VG_TARGE = 18523; // 1
+static const uint64_t SH_FLD_VG_TARGET_SEL = 18524; // 24
+static const uint64_t SH_FLD_VG_TARGE_LEN = 18525; // 1
+static const uint64_t SH_FLD_VID_COMPARE_MAX = 18526; // 6
+static const uint64_t SH_FLD_VID_COMPARE_MAX_LEN = 18527; // 6
+static const uint64_t SH_FLD_VID_COMPARE_MIN = 18528; // 6
+static const uint64_t SH_FLD_VID_COMPARE_MIN_LEN = 18529; // 6
+static const uint64_t SH_FLD_VITAL_AL = 18530; // 43
+static const uint64_t SH_FLD_VITAL_PHASE = 18531; // 43
+static const uint64_t SH_FLD_VITAL_SCAN = 18532; // 43
+static const uint64_t SH_FLD_VITAL_SCAN_IN = 18533; // 43
+static const uint64_t SH_FLD_VITAL_THOLD = 18534; // 43
+static const uint64_t SH_FLD_VITL = 18535; // 43
+static const uint64_t SH_FLD_VITL_CLKOFF = 18536; // 43
+static const uint64_t SH_FLD_VOFF_CFG = 18537; // 6
+static const uint64_t SH_FLD_VOFF_CFG_LEN = 18538; // 6
+static const uint64_t SH_FLD_VOLT_MODEREG_PARITY_MASK = 18539; // 43
+static const uint64_t SH_FLD_VP = 18540; // 1
+static const uint64_t SH_FLD_VPC_DMA_ORDERING_TAG = 18541; // 1
+static const uint64_t SH_FLD_VPC_DMA_ORDERING_TAG_LEN = 18542; // 1
+static const uint64_t SH_FLD_VPC_LD_RMT_ORDERING_TAG = 18543; // 1
+static const uint64_t SH_FLD_VPC_LD_RMT_ORDERING_TAG_LEN = 18544; // 1
+static const uint64_t SH_FLD_VPC_LD_RSP_ORDERING_TAG = 18545; // 1
+static const uint64_t SH_FLD_VPC_LD_RSP_ORDERING_TAG_LEN = 18546; // 1
+static const uint64_t SH_FLD_VPC_ST_RMT_ORDERING_TAG = 18547; // 1
+static const uint64_t SH_FLD_VPC_ST_RMT_ORDERING_TAG_LEN = 18548; // 1
+static const uint64_t SH_FLD_VPC_ST_RMT_VC_ORDERING_TAG = 18549; // 1
+static const uint64_t SH_FLD_VPC_ST_RMT_VC_ORDERING_TAG_LEN = 18550; // 1
+static const uint64_t SH_FLD_VPD_DMA_READ = 18551; // 1
+static const uint64_t SH_FLD_VPD_DMA_READ_LEN = 18552; // 1
+static const uint64_t SH_FLD_VPD_DMA_WRITE = 18553; // 1
+static const uint64_t SH_FLD_VPD_DMA_WRITE_LEN = 18554; // 1
+static const uint64_t SH_FLD_VPROTH = 18555; // 8
+static const uint64_t SH_FLD_VPROTH_CTL = 18556; // 8
+static const uint64_t SH_FLD_VPROTH_CTL_LEN = 18557; // 8
+static const uint64_t SH_FLD_VPROTH_PSEL_MODE = 18558; // 8
+static const uint64_t SH_FLD_VREF = 18559; // 9
+static const uint64_t SH_FLD_VREFDQ0D = 18560; // 8
+static const uint64_t SH_FLD_VREFDQ0DSGN = 18561; // 8
+static const uint64_t SH_FLD_VREFDQ0D_LEN = 18562; // 8
+static const uint64_t SH_FLD_VREFDQ1D = 18563; // 8
+static const uint64_t SH_FLD_VREFDQ1DSGN = 18564; // 8
+static const uint64_t SH_FLD_VREFDQ1D_LEN = 18565; // 8
+static const uint64_t SH_FLD_VREFTUNE = 18566; // 3
+static const uint64_t SH_FLD_VREFTUNE_LEN = 18567; // 3
+static const uint64_t SH_FLD_VREF_LEN = 18568; // 1
+static const uint64_t SH_FLD_VREGBYP = 18569; // 6
+static const uint64_t SH_FLD_VREGBYPASS = 18570; // 4
+static const uint64_t SH_FLD_VREGENABLE_N = 18571; // 4
+static const uint64_t SH_FLD_VREG_S = 18572; // 8
+static const uint64_t SH_FLD_VSEL = 18573; // 10
+static const uint64_t SH_FLD_VSEL_LEN = 18574; // 10
+static const uint64_t SH_FLD_VST_TYPE = 18575; // 1
+static const uint64_t SH_FLD_VST_TYPE_LEN = 18576; // 1
+static const uint64_t SH_FLD_VTARGET = 18577; // 4
+static const uint64_t SH_FLD_VTARGET_LEN = 18578; // 4
+static const uint64_t SH_FLD_V_TARG = 18579; // 1
+static const uint64_t SH_FLD_V_TARG_LEN = 18580; // 1
+static const uint64_t SH_FLD_W0_COUNT = 18581; // 12
+static const uint64_t SH_FLD_W0_COUNT_LEN = 18582; // 12
+static const uint64_t SH_FLD_W1_COUNT = 18583; // 12
+static const uint64_t SH_FLD_W1_COUNT_LEN = 18584; // 12
+static const uint64_t SH_FLD_WAITING = 18585; // 2
+static const uint64_t SH_FLD_WAIT_ALLWAYS = 18586; // 129
+static const uint64_t SH_FLD_WAIT_CYCLES = 18587; // 172
+static const uint64_t SH_FLD_WAIT_CYCLES_LEN = 18588; // 172
+static const uint64_t SH_FLD_WANT_CACHE_DISABLE = 18589; // 4
+static const uint64_t SH_FLD_WANT_INVALIDATE = 18590; // 3
+static const uint64_t SH_FLD_WARB_INVALID_CASE_ERROR = 18591; // 2
+static const uint64_t SH_FLD_WARM_START_COMPLETED = 18592; // 2
+static const uint64_t SH_FLD_WAT0_EVENT_SELECT = 18593; // 8
+static const uint64_t SH_FLD_WAT0_EVENT_SELECT_LEN = 18594; // 8
+static const uint64_t SH_FLD_WAT0_EVENT_SELECT_MCA = 18595; // 8
+static const uint64_t SH_FLD_WAT0_EVENT_SELECT_MCA_LEN = 18596; // 8
+static const uint64_t SH_FLD_WAT0_EVENT_SELECT_NEST = 18597; // 8
+static const uint64_t SH_FLD_WAT0_EVENT_SELECT_NEST_LEN = 18598; // 8
+static const uint64_t SH_FLD_WAT1_EVENT_SELECT = 18599; // 8
+static const uint64_t SH_FLD_WAT1_EVENT_SELECT_LEN = 18600; // 8
+static const uint64_t SH_FLD_WAT1_EVENT_SELECT_MCA = 18601; // 8
+static const uint64_t SH_FLD_WAT1_EVENT_SELECT_MCA_LEN = 18602; // 8
+static const uint64_t SH_FLD_WAT1_EVENT_SELECT_NEST = 18603; // 8
+static const uint64_t SH_FLD_WAT1_EVENT_SELECT_NEST_LEN = 18604; // 8
+static const uint64_t SH_FLD_WATCHDOG = 18605; // 1
+static const uint64_t SH_FLD_WATCHDOG_ENABLE = 18606; // 43
+static const uint64_t SH_FLD_WATCHDOG_SEL = 18607; // 17
+static const uint64_t SH_FLD_WATCHDOG_SEL_LEN = 18608; // 17
+static const uint64_t SH_FLD_WATERMARK_REG_0 = 18609; // 2
+static const uint64_t SH_FLD_WATERMARK_REG_0_LEN = 18610; // 2
+static const uint64_t SH_FLD_WATERMARK_REG_1 = 18611; // 1
+static const uint64_t SH_FLD_WATERMARK_REG_1_LEN = 18612; // 1
+static const uint64_t SH_FLD_WATERMARK_REG_2 = 18613; // 1
+static const uint64_t SH_FLD_WATERMARK_REG_2_LEN = 18614; // 1
+static const uint64_t SH_FLD_WATERMARK_REG_3 = 18615; // 1
+static const uint64_t SH_FLD_WATERMARK_REG_3_LEN = 18616; // 1
+static const uint64_t SH_FLD_WAT_ACTION_DIS_ALL_SPEC = 18617; // 4
+static const uint64_t SH_FLD_WAT_ACTION_DIS_ALL_SPEC_LEN = 18618; // 4
+static const uint64_t SH_FLD_WAT_ACTION_DIS_FASTPATH = 18619; // 4
+static const uint64_t SH_FLD_WAT_ACTION_DIS_FASTPATH_LEN = 18620; // 4
+static const uint64_t SH_FLD_WAT_ACTION_DIS_PREFETCH = 18621; // 4
+static const uint64_t SH_FLD_WAT_ACTION_DIS_PREFETCH_LEN = 18622; // 4
+static const uint64_t SH_FLD_WAT_ACTION_DIS_READ_BYP = 18623; // 4
+static const uint64_t SH_FLD_WAT_ACTION_DIS_READ_BYP_LEN = 18624; // 4
+static const uint64_t SH_FLD_WAT_ACTION_FORCE_MDI = 18625; // 4
+static const uint64_t SH_FLD_WAT_ACTION_FORCE_MDI_LEN = 18626; // 4
+static const uint64_t SH_FLD_WAT_ACTION_FORCE_SFSTAT = 18627; // 4
+static const uint64_t SH_FLD_WAT_ACTION_FORCE_SFSTAT_LEN = 18628; // 4
+static const uint64_t SH_FLD_WAT_ACTION_SEL = 18629; // 8
+static const uint64_t SH_FLD_WAT_ACTION_SEL_LEN = 18630; // 8
+static const uint64_t SH_FLD_WAT_CNTL_REG_SEL = 18631; // 4
+static const uint64_t SH_FLD_WAT_CNTL_REG_SEL_LEN = 18632; // 4
+static const uint64_t SH_FLD_WAT_DEBUG_ATTN = 18633; // 2
+static const uint64_t SH_FLD_WAT_DEBUG_REG_PE = 18634; // 2
+static const uint64_t SH_FLD_WAT_ERROR = 18635; // 16
+static const uint64_t SH_FLD_WAT_EVENT_ENABLE = 18636; // 8
+static const uint64_t SH_FLD_WAT_EVENT_ENABLE_MCA = 18637; // 8
+static const uint64_t SH_FLD_WAT_EVENT_ENABLE_NEST = 18638; // 8
+static const uint64_t SH_FLD_WAT_EVENT_SEL = 18639; // 4
+static const uint64_t SH_FLD_WAT_EVENT_SEL_LEN = 18640; // 4
+static const uint64_t SH_FLD_WAT_EXT_EVENT_TO_INT_SEL = 18641; // 4
+static const uint64_t SH_FLD_WAT_EXT_EVENT_TO_INT_SEL_LEN = 18642; // 4
+static const uint64_t SH_FLD_WAT_EXT_SEL = 18643; // 4
+static const uint64_t SH_FLD_WAT_EXT_SEL_LEN = 18644; // 4
+static const uint64_t SH_FLD_WAT_GLOB_EVENT0_SEL = 18645; // 4
+static const uint64_t SH_FLD_WAT_GLOB_EVENT0_SEL_LEN = 18646; // 4
+static const uint64_t SH_FLD_WAT_GLOB_EVENT1_SEL = 18647; // 4
+static const uint64_t SH_FLD_WAT_GLOB_EVENT1_SEL_LEN = 18648; // 4
+static const uint64_t SH_FLD_WAT_GLOB_EVENT2_SEL = 18649; // 4
+static const uint64_t SH_FLD_WAT_GLOB_EVENT2_SEL_LEN = 18650; // 4
+static const uint64_t SH_FLD_WAT_GLOB_EVENT3_SEL = 18651; // 4
+static const uint64_t SH_FLD_WAT_GLOB_EVENT3_SEL_LEN = 18652; // 4
+static const uint64_t SH_FLD_WAT_LOCAL_EVENT_SEL = 18653; // 4
+static const uint64_t SH_FLD_WAT_LOCAL_EVENT_SEL_LEN = 18654; // 4
+static const uint64_t SH_FLD_WAT_SPARE1 = 18655; // 8
+static const uint64_t SH_FLD_WAT_SPARE1_LEN = 18656; // 8
+static const uint64_t SH_FLD_WAT_SPARE1_MCA = 18657; // 8
+static const uint64_t SH_FLD_WAT_SPARE1_MCA_LEN = 18658; // 8
+static const uint64_t SH_FLD_WAT_SPARE1_NEST = 18659; // 8
+static const uint64_t SH_FLD_WAT_SPARE1_NEST_LEN = 18660; // 8
+static const uint64_t SH_FLD_WAT_STALL_ACTION = 18661; // 8
+static const uint64_t SH_FLD_WAT_STALL_ACTION_LEN = 18662; // 8
+static const uint64_t SH_FLD_WBMGR_DBG_0_SELECT = 18663; // 8
+static const uint64_t SH_FLD_WBMGR_DBG_1_SELECT = 18664; // 8
+static const uint64_t SH_FLD_WBRD_DEBUG_0_SELECT = 18665; // 8
+static const uint64_t SH_FLD_WBRD_DEBUG_1_SELECT = 18666; // 8
+static const uint64_t SH_FLD_WC = 18667; // 8
+static const uint64_t SH_FLD_WC_BS_BAR = 18668; // 1
+static const uint64_t SH_FLD_WC_BS_BAR_LEN = 18669; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT10 = 18670; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT11 = 18671; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT12 = 18672; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT13 = 18673; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT14 = 18674; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT15 = 18675; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT16 = 18676; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT17 = 18677; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT18 = 18678; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT19 = 18679; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT20 = 18680; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT21 = 18681; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT22 = 18682; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT23 = 18683; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT4 = 18684; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT5 = 18685; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT6 = 18686; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT7 = 18687; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT8 = 18688; // 1
+static const uint64_t SH_FLD_WC_CERR_BIT9 = 18689; // 1
+static const uint64_t SH_FLD_WC_CERR_RESET = 18690; // 1
+static const uint64_t SH_FLD_WC_ECC_CE_ERROR = 18691; // 2
+static const uint64_t SH_FLD_WC_ECC_SUE_ERROR = 18692; // 2
+static const uint64_t SH_FLD_WC_ECC_UE_ERROR = 18693; // 2
+static const uint64_t SH_FLD_WC_LOGIC_HW_ERROR = 18694; // 2
+static const uint64_t SH_FLD_WC_MASK = 18695; // 8
+static const uint64_t SH_FLD_WC_TRACE_GROUP_SEL_HI = 18696; // 1
+static const uint64_t SH_FLD_WC_TRACE_GROUP_SEL_HI_LEN = 18697; // 1
+static const uint64_t SH_FLD_WC_TRACE_GROUP_SEL_LO = 18698; // 1
+static const uint64_t SH_FLD_WC_TRACE_GROUP_SEL_LO_LEN = 18699; // 1
+static const uint64_t SH_FLD_WC_TRACE_INT_DATA_HI = 18700; // 1
+static const uint64_t SH_FLD_WC_TRACE_INT_DATA_LO = 18701; // 1
+static const uint64_t SH_FLD_WC_TRACE_INT_TRIG_01 = 18702; // 1
+static const uint64_t SH_FLD_WC_TRACE_INT_TRIG_23 = 18703; // 1
+static const uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_01 = 18704; // 1
+static const uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_01_LEN = 18705; // 1
+static const uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_23 = 18706; // 1
+static const uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_23_LEN = 18707; // 1
+static const uint64_t SH_FLD_WDATA = 18708; // 1
+static const uint64_t SH_FLD_WDATA_LEN = 18709; // 1
+static const uint64_t SH_FLD_WDFCFG_PE = 18710; // 8
+static const uint64_t SH_FLD_WDF_ASYNC_ERROR = 18711; // 8
+static const uint64_t SH_FLD_WDF_ASYNC_INTERFACE_ERROR = 18712; // 8
+static const uint64_t SH_FLD_WDF_BUFFER_CE = 18713; // 8
+static const uint64_t SH_FLD_WDF_BUFFER_SUE = 18714; // 8
+static const uint64_t SH_FLD_WDF_BUFFER_UE = 18715; // 8
+static const uint64_t SH_FLD_WDF_ERR_INJECT0 = 18716; // 8
+static const uint64_t SH_FLD_WDF_ERR_INJECT0_LEN = 18717; // 8
+static const uint64_t SH_FLD_WDF_MISC_REGISTER_PARITY_ERROR = 18718; // 8
+static const uint64_t SH_FLD_WDF_OVERRUN_ERROR_0 = 18719; // 8
+static const uint64_t SH_FLD_WDF_OVERRUN_ERROR_1 = 18720; // 8
+static const uint64_t SH_FLD_WDF_SCOM_SEQUENCE_ERROR = 18721; // 8
+static const uint64_t SH_FLD_WDF_STATE_MACHINE_ERROR = 18722; // 8
+static const uint64_t SH_FLD_WECR_PE = 18723; // 8
+static const uint64_t SH_FLD_WHICH_8BECK = 18724; // 8
+static const uint64_t SH_FLD_WHICH_8BECK_LEN = 18725; // 8
+static const uint64_t SH_FLD_WILDCARD = 18726; // 6
+static const uint64_t SH_FLD_WINDOW_SELECT = 18727; // 3
+static const uint64_t SH_FLD_WINDOW_SELECT_LEN = 18728; // 3
+static const uint64_t SH_FLD_WIRETEST_DONE = 18729; // 4
+static const uint64_t SH_FLD_WIRETEST_FAILED = 18730; // 4
+static const uint64_t SH_FLD_WITH_ADDRESS_0 = 18731; // 2
+static const uint64_t SH_FLD_WITH_ADDRESS_1 = 18732; // 1
+static const uint64_t SH_FLD_WITH_ADDRESS_2 = 18733; // 1
+static const uint64_t SH_FLD_WITH_ADDRESS_3 = 18734; // 1
+static const uint64_t SH_FLD_WITH_START_0 = 18735; // 2
+static const uint64_t SH_FLD_WITH_START_1 = 18736; // 1
+static const uint64_t SH_FLD_WITH_START_2 = 18737; // 1
+static const uint64_t SH_FLD_WITH_START_3 = 18738; // 1
+static const uint64_t SH_FLD_WITH_STOP_0 = 18739; // 2
+static const uint64_t SH_FLD_WITH_STOP_1 = 18740; // 1
+static const uint64_t SH_FLD_WITH_STOP_2 = 18741; // 1
+static const uint64_t SH_FLD_WITH_STOP_3 = 18742; // 1
+static const uint64_t SH_FLD_WI_MACHINE_HANG = 18743; // 12
+static const uint64_t SH_FLD_WI_MACHINE_W4DT_HANG = 18744; // 12
+static const uint64_t SH_FLD_WI_UNSOLICITED_DATA = 18745; // 12
+static const uint64_t SH_FLD_WKUP_NOTIFY_SELECT = 18746; // 24
+static const uint64_t SH_FLD_WL = 18747; // 8
+static const uint64_t SH_FLD_WL_ONE_DQS_PULSE = 18748; // 8
+static const uint64_t SH_FLD_WM_MULTIHIT_ERR = 18749; // 2
+static const uint64_t SH_FLD_WM_WIN_NOT_OPEN_ERR = 18750; // 2
+static const uint64_t SH_FLD_WOF = 18751; // 5
+static const uint64_t SH_FLD_WOF_COUNTER = 18752; // 1
+static const uint64_t SH_FLD_WOF_COUNTER_LEN = 18753; // 1
+static const uint64_t SH_FLD_WOF_LEN = 18754; // 5
+static const uint64_t SH_FLD_WOF_LOW_ORDER_STEP_COUNTER_PARITY = 18755; // 4
+static const uint64_t SH_FLD_WORD = 18756; // 8
+static const uint64_t SH_FLD_WORD_LEN = 18757; // 8
+static const uint64_t SH_FLD_WORK1 = 18758; // 3
+static const uint64_t SH_FLD_WORK1_LEN = 18759; // 3
+static const uint64_t SH_FLD_WORK2 = 18760; // 3
+static const uint64_t SH_FLD_WORK2_LEN = 18761; // 3
+static const uint64_t SH_FLD_WRAP_0 = 18762; // 2
+static const uint64_t SH_FLD_WRAP_1 = 18763; // 1
+static const uint64_t SH_FLD_WRAP_2 = 18764; // 1
+static const uint64_t SH_FLD_WRAP_3 = 18765; // 1
+static const uint64_t SH_FLD_WRCMP = 18766; // 2
+static const uint64_t SH_FLD_WRCMP_LEN = 18767; // 2
+static const uint64_t SH_FLD_WRCNTL_DBG_SELECT = 18768; // 8
+static const uint64_t SH_FLD_WRDM_DLY = 18769; // 8
+static const uint64_t SH_FLD_WRDM_DLY_LEN = 18770; // 8
+static const uint64_t SH_FLD_WRD_MCBIST_OUT_OF_SYNC_HOLD_OUT = 18771; // 2
+static const uint64_t SH_FLD_WRITE = 18772; // 9
+static const uint64_t SH_FLD_WRITE_CMD = 18773; // 1
+static const uint64_t SH_FLD_WRITE_COMPLETE = 18774; // 1
+static const uint64_t SH_FLD_WRITE_COUNT = 18775; // 8
+static const uint64_t SH_FLD_WRITE_COUNTER = 18776; // 1
+static const uint64_t SH_FLD_WRITE_COUNTER_LEN = 18777; // 1
+static const uint64_t SH_FLD_WRITE_COUNT_LEN = 18778; // 8
+static const uint64_t SH_FLD_WRITE_CRD_POOL = 18779; // 1
+static const uint64_t SH_FLD_WRITE_CRD_POOL_LEN = 18780; // 1
+static const uint64_t SH_FLD_WRITE_CTR = 18781; // 8
+static const uint64_t SH_FLD_WRITE_ECC_DATAPATH_ERROR = 18782; // 8
+static const uint64_t SH_FLD_WRITE_ENABLE = 18783; // 129
+static const uint64_t SH_FLD_WRITE_ERR_INJECT0 = 18784; // 8
+static const uint64_t SH_FLD_WRITE_ERR_INJECT0_LEN = 18785; // 8
+static const uint64_t SH_FLD_WRITE_INVALID_FACES = 18786; // 1
+static const uint64_t SH_FLD_WRITE_INVALID_PIB = 18787; // 1
+static const uint64_t SH_FLD_WRITE_LATENCY_OFFSET = 18788; // 8
+static const uint64_t SH_FLD_WRITE_LATENCY_OFFSET_LEN = 18789; // 8
+static const uint64_t SH_FLD_WRITE_NOT_READ = 18790; // 3
+static const uint64_t SH_FLD_WRITE_NVLD = 18791; // 1
+static const uint64_t SH_FLD_WRITE_ON_RUN = 18792; // 90
+static const uint64_t SH_FLD_WRITE_POOL = 18793; // 1
+static const uint64_t SH_FLD_WRITE_POOL_LEN = 18794; // 1
+static const uint64_t SH_FLD_WRITE_RMW_CE = 18795; // 8
+static const uint64_t SH_FLD_WRITE_RMW_SUE = 18796; // 8
+static const uint64_t SH_FLD_WRITE_RMW_UE = 18797; // 8
+static const uint64_t SH_FLD_WRITE_RST_INTERRUPT_FACES = 18798; // 1
+static const uint64_t SH_FLD_WRITE_RST_INTERRUPT_PIB = 18799; // 1
+static const uint64_t SH_FLD_WRITE_TSIZE = 18800; // 4
+static const uint64_t SH_FLD_WRITE_TSIZE_LEN = 18801; // 4
+static const uint64_t SH_FLD_WRITE_TTYPE = 18802; // 4
+static const uint64_t SH_FLD_WRITE_TTYPE_LEN = 18803; // 4
+static const uint64_t SH_FLD_WRITE_WHILE_BRIDGE_BUSY_ERR = 18804; // 1
+static const uint64_t SH_FLD_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN = 18805; // 1
+static const uint64_t SH_FLD_WRMON_BAR0_BA = 18806; // 1
+static const uint64_t SH_FLD_WRMON_BAR0_BA_LEN = 18807; // 1
+static const uint64_t SH_FLD_WRMON_BAR0_SIZE = 18808; // 1
+static const uint64_t SH_FLD_WRMON_BAR0_SIZE_LEN = 18809; // 1
+static const uint64_t SH_FLD_WRMON_BAR1_BA = 18810; // 1
+static const uint64_t SH_FLD_WRMON_BAR1_BA_LEN = 18811; // 1
+static const uint64_t SH_FLD_WRMON_BAR1_SIZE = 18812; // 1
+static const uint64_t SH_FLD_WRMON_BAR1_SIZE_LEN = 18813; // 1
+static const uint64_t SH_FLD_WRMON_BAR2_BA = 18814; // 1
+static const uint64_t SH_FLD_WRMON_BAR2_BA_LEN = 18815; // 1
+static const uint64_t SH_FLD_WRMON_BAR2_SIZE = 18816; // 1
+static const uint64_t SH_FLD_WRMON_BAR2_SIZE_LEN = 18817; // 1
+static const uint64_t SH_FLD_WRMON_BAR3_BA = 18818; // 1
+static const uint64_t SH_FLD_WRMON_BAR3_BA_LEN = 18819; // 1
+static const uint64_t SH_FLD_WRMON_BAR3_SIZE = 18820; // 1
+static const uint64_t SH_FLD_WRMON_BAR3_SIZE_LEN = 18821; // 1
+static const uint64_t SH_FLD_WRMON_BAR4_BA = 18822; // 1
+static const uint64_t SH_FLD_WRMON_BAR4_BA_LEN = 18823; // 1
+static const uint64_t SH_FLD_WRMON_BAR4_SIZE = 18824; // 1
+static const uint64_t SH_FLD_WRMON_BAR4_SIZE_LEN = 18825; // 1
+static const uint64_t SH_FLD_WRMON_BAR5_BA = 18826; // 1
+static const uint64_t SH_FLD_WRMON_BAR5_BA_LEN = 18827; // 1
+static const uint64_t SH_FLD_WRMON_BAR5_SIZE = 18828; // 1
+static const uint64_t SH_FLD_WRMON_BAR5_SIZE_LEN = 18829; // 1
+static const uint64_t SH_FLD_WRMON_BAR6_BA = 18830; // 1
+static const uint64_t SH_FLD_WRMON_BAR6_BA_LEN = 18831; // 1
+static const uint64_t SH_FLD_WRMON_BAR6_SIZE = 18832; // 1
+static const uint64_t SH_FLD_WRMON_BAR6_SIZE_LEN = 18833; // 1
+static const uint64_t SH_FLD_WRMON_BAR7_BA = 18834; // 1
+static const uint64_t SH_FLD_WRMON_BAR7_BA_LEN = 18835; // 1
+static const uint64_t SH_FLD_WRMON_BAR7_SIZE = 18836; // 1
+static const uint64_t SH_FLD_WRMON_BAR7_SIZE_LEN = 18837; // 1
+static const uint64_t SH_FLD_WRMON_CMP0_ENADTTYPE = 18838; // 1
+static const uint64_t SH_FLD_WRMON_CMP0_TSIZE = 18839; // 1
+static const uint64_t SH_FLD_WRMON_CMP0_TSIZEMSK = 18840; // 1
+static const uint64_t SH_FLD_WRMON_CMP0_TSIZEMSK_LEN = 18841; // 1
+static const uint64_t SH_FLD_WRMON_CMP0_TSIZE_LEN = 18842; // 1
+static const uint64_t SH_FLD_WRMON_CMP0_TTYPE = 18843; // 1
+static const uint64_t SH_FLD_WRMON_CMP0_TTYPEDIS = 18844; // 1
+static const uint64_t SH_FLD_WRMON_CMP0_TTYPEDIS_LEN = 18845; // 1
+static const uint64_t SH_FLD_WRMON_CMP0_TTYPEMSK = 18846; // 1
+static const uint64_t SH_FLD_WRMON_CMP0_TTYPEMSK_LEN = 18847; // 1
+static const uint64_t SH_FLD_WRMON_CMP0_TTYPE_LEN = 18848; // 1
+static const uint64_t SH_FLD_WRMON_CMP0_UNUSED = 18849; // 1
+static const uint64_t SH_FLD_WRMON_CMP0_VAL = 18850; // 1
+static const uint64_t SH_FLD_WRMON_CMP1_ENADTTYPE = 18851; // 1
+static const uint64_t SH_FLD_WRMON_CMP1_TSIZE = 18852; // 1
+static const uint64_t SH_FLD_WRMON_CMP1_TSIZEMSK = 18853; // 1
+static const uint64_t SH_FLD_WRMON_CMP1_TSIZEMSK_LEN = 18854; // 1
+static const uint64_t SH_FLD_WRMON_CMP1_TSIZE_LEN = 18855; // 1
+static const uint64_t SH_FLD_WRMON_CMP1_TTYPE = 18856; // 1
+static const uint64_t SH_FLD_WRMON_CMP1_TTYPEDIS = 18857; // 1
+static const uint64_t SH_FLD_WRMON_CMP1_TTYPEDIS_LEN = 18858; // 1
+static const uint64_t SH_FLD_WRMON_CMP1_TTYPEMSK = 18859; // 1
+static const uint64_t SH_FLD_WRMON_CMP1_TTYPEMSK_LEN = 18860; // 1
+static const uint64_t SH_FLD_WRMON_CMP1_TTYPE_LEN = 18861; // 1
+static const uint64_t SH_FLD_WRMON_CMP1_UNUSED = 18862; // 1
+static const uint64_t SH_FLD_WRMON_CMP1_VAL = 18863; // 1
+static const uint64_t SH_FLD_WRMON_CMP2_ENADTTYPE = 18864; // 1
+static const uint64_t SH_FLD_WRMON_CMP2_TSIZE = 18865; // 1
+static const uint64_t SH_FLD_WRMON_CMP2_TSIZEMSK = 18866; // 1
+static const uint64_t SH_FLD_WRMON_CMP2_TSIZEMSK_LEN = 18867; // 1
+static const uint64_t SH_FLD_WRMON_CMP2_TSIZE_LEN = 18868; // 1
+static const uint64_t SH_FLD_WRMON_CMP2_TTYPE = 18869; // 1
+static const uint64_t SH_FLD_WRMON_CMP2_TTYPEDIS = 18870; // 1
+static const uint64_t SH_FLD_WRMON_CMP2_TTYPEDIS_LEN = 18871; // 1
+static const uint64_t SH_FLD_WRMON_CMP2_TTYPEMSK = 18872; // 1
+static const uint64_t SH_FLD_WRMON_CMP2_TTYPEMSK_LEN = 18873; // 1
+static const uint64_t SH_FLD_WRMON_CMP2_TTYPE_LEN = 18874; // 1
+static const uint64_t SH_FLD_WRMON_CMP2_UNUSED = 18875; // 1
+static const uint64_t SH_FLD_WRMON_CMP2_VAL = 18876; // 1
+static const uint64_t SH_FLD_WRMON_CMP3_ENADTTYPE = 18877; // 1
+static const uint64_t SH_FLD_WRMON_CMP3_TSIZE = 18878; // 1
+static const uint64_t SH_FLD_WRMON_CMP3_TSIZEMSK = 18879; // 1
+static const uint64_t SH_FLD_WRMON_CMP3_TSIZEMSK_LEN = 18880; // 1
+static const uint64_t SH_FLD_WRMON_CMP3_TSIZE_LEN = 18881; // 1
+static const uint64_t SH_FLD_WRMON_CMP3_TTYPE = 18882; // 1
+static const uint64_t SH_FLD_WRMON_CMP3_TTYPEDIS = 18883; // 1
+static const uint64_t SH_FLD_WRMON_CMP3_TTYPEDIS_LEN = 18884; // 1
+static const uint64_t SH_FLD_WRMON_CMP3_TTYPEMSK = 18885; // 1
+static const uint64_t SH_FLD_WRMON_CMP3_TTYPEMSK_LEN = 18886; // 1
+static const uint64_t SH_FLD_WRMON_CMP3_TTYPE_LEN = 18887; // 1
+static const uint64_t SH_FLD_WRMON_CMP3_UNUSED = 18888; // 1
+static const uint64_t SH_FLD_WRMON_CMP3_VAL = 18889; // 1
+static const uint64_t SH_FLD_WRMON_CMP4_ENADTTYPE = 18890; // 1
+static const uint64_t SH_FLD_WRMON_CMP4_TSIZE = 18891; // 1
+static const uint64_t SH_FLD_WRMON_CMP4_TSIZEMSK = 18892; // 1
+static const uint64_t SH_FLD_WRMON_CMP4_TSIZEMSK_LEN = 18893; // 1
+static const uint64_t SH_FLD_WRMON_CMP4_TSIZE_LEN = 18894; // 1
+static const uint64_t SH_FLD_WRMON_CMP4_TTYPE = 18895; // 1
+static const uint64_t SH_FLD_WRMON_CMP4_TTYPEDIS = 18896; // 1
+static const uint64_t SH_FLD_WRMON_CMP4_TTYPEDIS_LEN = 18897; // 1
+static const uint64_t SH_FLD_WRMON_CMP4_TTYPEMSK = 18898; // 1
+static const uint64_t SH_FLD_WRMON_CMP4_TTYPEMSK_LEN = 18899; // 1
+static const uint64_t SH_FLD_WRMON_CMP4_TTYPE_LEN = 18900; // 1
+static const uint64_t SH_FLD_WRMON_CMP4_UNUSED = 18901; // 1
+static const uint64_t SH_FLD_WRMON_CMP4_VAL = 18902; // 1
+static const uint64_t SH_FLD_WRMON_CMP5_ENADTTYPE = 18903; // 1
+static const uint64_t SH_FLD_WRMON_CMP5_TSIZE = 18904; // 1
+static const uint64_t SH_FLD_WRMON_CMP5_TSIZEMSK = 18905; // 1
+static const uint64_t SH_FLD_WRMON_CMP5_TSIZEMSK_LEN = 18906; // 1
+static const uint64_t SH_FLD_WRMON_CMP5_TSIZE_LEN = 18907; // 1
+static const uint64_t SH_FLD_WRMON_CMP5_TTYPE = 18908; // 1
+static const uint64_t SH_FLD_WRMON_CMP5_TTYPEDIS = 18909; // 1
+static const uint64_t SH_FLD_WRMON_CMP5_TTYPEDIS_LEN = 18910; // 1
+static const uint64_t SH_FLD_WRMON_CMP5_TTYPEMSK = 18911; // 1
+static const uint64_t SH_FLD_WRMON_CMP5_TTYPEMSK_LEN = 18912; // 1
+static const uint64_t SH_FLD_WRMON_CMP5_TTYPE_LEN = 18913; // 1
+static const uint64_t SH_FLD_WRMON_CMP5_UNUSED = 18914; // 1
+static const uint64_t SH_FLD_WRMON_CMP5_VAL = 18915; // 1
+static const uint64_t SH_FLD_WRMON_CMP6_ENADTTYPE = 18916; // 1
+static const uint64_t SH_FLD_WRMON_CMP6_TSIZE = 18917; // 1
+static const uint64_t SH_FLD_WRMON_CMP6_TSIZEMSK = 18918; // 1
+static const uint64_t SH_FLD_WRMON_CMP6_TSIZEMSK_LEN = 18919; // 1
+static const uint64_t SH_FLD_WRMON_CMP6_TSIZE_LEN = 18920; // 1
+static const uint64_t SH_FLD_WRMON_CMP6_TTYPE = 18921; // 1
+static const uint64_t SH_FLD_WRMON_CMP6_TTYPEDIS = 18922; // 1
+static const uint64_t SH_FLD_WRMON_CMP6_TTYPEDIS_LEN = 18923; // 1
+static const uint64_t SH_FLD_WRMON_CMP6_TTYPEMSK = 18924; // 1
+static const uint64_t SH_FLD_WRMON_CMP6_TTYPEMSK_LEN = 18925; // 1
+static const uint64_t SH_FLD_WRMON_CMP6_TTYPE_LEN = 18926; // 1
+static const uint64_t SH_FLD_WRMON_CMP6_UNUSED = 18927; // 1
+static const uint64_t SH_FLD_WRMON_CMP6_VAL = 18928; // 1
+static const uint64_t SH_FLD_WRMON_CMP7_ENADTTYPE = 18929; // 1
+static const uint64_t SH_FLD_WRMON_CMP7_TSIZE = 18930; // 1
+static const uint64_t SH_FLD_WRMON_CMP7_TSIZEMSK = 18931; // 1
+static const uint64_t SH_FLD_WRMON_CMP7_TSIZEMSK_LEN = 18932; // 1
+static const uint64_t SH_FLD_WRMON_CMP7_TSIZE_LEN = 18933; // 1
+static const uint64_t SH_FLD_WRMON_CMP7_TTYPE = 18934; // 1
+static const uint64_t SH_FLD_WRMON_CMP7_TTYPEDIS = 18935; // 1
+static const uint64_t SH_FLD_WRMON_CMP7_TTYPEDIS_LEN = 18936; // 1
+static const uint64_t SH_FLD_WRMON_CMP7_TTYPEMSK = 18937; // 1
+static const uint64_t SH_FLD_WRMON_CMP7_TTYPEMSK_LEN = 18938; // 1
+static const uint64_t SH_FLD_WRMON_CMP7_TTYPE_LEN = 18939; // 1
+static const uint64_t SH_FLD_WRMON_CMP7_UNUSED = 18940; // 1
+static const uint64_t SH_FLD_WRMON_CMP7_VAL = 18941; // 1
+static const uint64_t SH_FLD_WRMON_WID0 = 18942; // 1
+static const uint64_t SH_FLD_WRMON_WID0_LEN = 18943; // 1
+static const uint64_t SH_FLD_WRMON_WID1 = 18944; // 1
+static const uint64_t SH_FLD_WRMON_WID1_LEN = 18945; // 1
+static const uint64_t SH_FLD_WRMON_WID2 = 18946; // 1
+static const uint64_t SH_FLD_WRMON_WID2_LEN = 18947; // 1
+static const uint64_t SH_FLD_WRMON_WID3 = 18948; // 1
+static const uint64_t SH_FLD_WRMON_WID3_LEN = 18949; // 1
+static const uint64_t SH_FLD_WRMON_WID4 = 18950; // 1
+static const uint64_t SH_FLD_WRMON_WID4_LEN = 18951; // 1
+static const uint64_t SH_FLD_WRMON_WID5 = 18952; // 1
+static const uint64_t SH_FLD_WRMON_WID5_LEN = 18953; // 1
+static const uint64_t SH_FLD_WRMON_WID6 = 18954; // 1
+static const uint64_t SH_FLD_WRMON_WID6_LEN = 18955; // 1
+static const uint64_t SH_FLD_WRMON_WID7 = 18956; // 1
+static const uint64_t SH_FLD_WRMON_WID7_LEN = 18957; // 1
+static const uint64_t SH_FLD_WRQ0_EMPTY = 18958; // 4
+static const uint64_t SH_FLD_WRQ1_EMPTY = 18959; // 4
+static const uint64_t SH_FLD_WRQ_BAD_CRESP = 18960; // 1
+static const uint64_t SH_FLD_WRQ_CAPACITY_LIMIT = 18961; // 4
+static const uint64_t SH_FLD_WRQ_CAPACITY_LIMIT_LEN = 18962; // 4
+static const uint64_t SH_FLD_WRQ_FSM_PERR = 18963; // 1
+static const uint64_t SH_FLD_WRQ_HANG = 18964; // 8
+static const uint64_t SH_FLD_WRQ_OP_HANG = 18965; // 1
+static const uint64_t SH_FLD_WRQ_OVERFLOW = 18966; // 1
+static const uint64_t SH_FLD_WRQ_PE = 18967; // 8
+static const uint64_t SH_FLD_WRQ_RRQ_HANG_ERR = 18968; // 16
+static const uint64_t SH_FLD_WRSBG_DLY = 18969; // 8
+static const uint64_t SH_FLD_WRSBG_DLY_LEN = 18970; // 8
+static const uint64_t SH_FLD_WRSMDR_DLY = 18971; // 8
+static const uint64_t SH_FLD_WRSMDR_DLY_LEN = 18972; // 8
+static const uint64_t SH_FLD_WRSMSR_DLY = 18973; // 8
+static const uint64_t SH_FLD_WRSMSR_DLY_LEN = 18974; // 8
+static const uint64_t SH_FLD_WRTCFG_PE = 18975; // 8
+static const uint64_t SH_FLD_WRTO_AMO_COLLISION_RULES = 18976; // 8
+static const uint64_t SH_FLD_WRTO_AMO_COLLISION_RULES_LEN = 18977; // 8
+static const uint64_t SH_FLD_WRT_BUFFER_CE = 18978; // 8
+static const uint64_t SH_FLD_WRT_BUFFER_SUE = 18979; // 8
+static const uint64_t SH_FLD_WRT_BUFFER_UE = 18980; // 8
+static const uint64_t SH_FLD_WRT_MISC_REGISTER_PARITY_ERROR = 18981; // 8
+static const uint64_t SH_FLD_WRT_RST_INTRPT_FACES = 18982; // 1
+static const uint64_t SH_FLD_WRT_RST_INTRPT_PIB = 18983; // 1
+static const uint64_t SH_FLD_WRT_SCOM_SEQUENCE_ERROR = 18984; // 8
+static const uint64_t SH_FLD_WR_BUFFER_STATUS = 18985; // 2
+static const uint64_t SH_FLD_WR_BUFFER_STATUS_LEN = 18986; // 2
+static const uint64_t SH_FLD_WR_BYTE_COUNT = 18987; // 2
+static const uint64_t SH_FLD_WR_BYTE_COUNT_LEN = 18988; // 2
+static const uint64_t SH_FLD_WR_CNTL = 18989; // 8
+static const uint64_t SH_FLD_WR_CNTL_MASK = 18990; // 8
+static const uint64_t SH_FLD_WR_DATA_PARITY_ERROR = 18991; // 3
+static const uint64_t SH_FLD_WR_ECC_CE = 18992; // 1
+static const uint64_t SH_FLD_WR_ECC_UE = 18993; // 1
+static const uint64_t SH_FLD_WR_EPSILON_VALUE = 18994; // 2
+static const uint64_t SH_FLD_WR_EPSILON_VALUE_LEN = 18995; // 2
+static const uint64_t SH_FLD_WR_FIFO_STAB = 18996; // 8
+static const uint64_t SH_FLD_WR_GATHER_TIMEOUT = 18997; // 4
+static const uint64_t SH_FLD_WR_GATHER_TIMEOUT_LEN = 18998; // 4
+static const uint64_t SH_FLD_WR_LEVEL = 18999; // 8
+static const uint64_t SH_FLD_WR_MON_NOT_DISABLED_ERR = 19000; // 2
+static const uint64_t SH_FLD_WR_PAR_ERR = 19001; // 8
+static const uint64_t SH_FLD_WR_PAR_ERR_MASK = 19002; // 8
+static const uint64_t SH_FLD_WR_PRE_DLY = 19003; // 8
+static const uint64_t SH_FLD_WR_PRE_DLY_LEN = 19004; // 8
+static const uint64_t SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT = 19005; // 8
+static const uint64_t SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN = 19006; // 8
+static const uint64_t SH_FLD_WR_RSVD_UPPER_LIMIT = 19007; // 8
+static const uint64_t SH_FLD_WR_RSVD_UPPER_LIMIT_LEN = 19008; // 8
+static const uint64_t SH_FLD_WR_SCOPE = 19009; // 24
+static const uint64_t SH_FLD_WR_SLVNUM = 19010; // 2
+static const uint64_t SH_FLD_WR_SLVNUM_LEN = 19011; // 2
+static const uint64_t SH_FLD_WR_SPLIT_UT0_ENA = 19012; // 6
+static const uint64_t SH_FLD_WR_SPLIT_UT1_ENA = 19013; // 6
+static const uint64_t SH_FLD_WR_TIER_1_CNT_VAL = 19014; // 1
+static const uint64_t SH_FLD_WR_TIER_1_CNT_VAL_LEN = 19015; // 1
+static const uint64_t SH_FLD_WR_TIER_1_DIV_VAL = 19016; // 1
+static const uint64_t SH_FLD_WR_TIER_1_DIV_VAL_LEN = 19017; // 1
+static const uint64_t SH_FLD_WR_TIER_2_CNT_VAL = 19018; // 1
+static const uint64_t SH_FLD_WR_TIER_2_CNT_VAL_LEN = 19019; // 1
+static const uint64_t SH_FLD_WR_TIER_2_DIV_VAL = 19020; // 1
+static const uint64_t SH_FLD_WR_TIER_2_DIV_VAL_LEN = 19021; // 1
+static const uint64_t SH_FLD_WR_VALID = 19022; // 1
+static const uint64_t SH_FLD_WSIZE = 19023; // 1
+static const uint64_t SH_FLD_WSIZE_LEN = 19024; // 1
+static const uint64_t SH_FLD_WT4CR_TIER0_EPS_VAL = 19025; // 12
+static const uint64_t SH_FLD_WT4CR_TIER0_EPS_VAL_LEN = 19026; // 12
+static const uint64_t SH_FLD_WT4CR_TIER1_EPS_VAL = 19027; // 24
+static const uint64_t SH_FLD_WT4CR_TIER1_EPS_VAL_LEN = 19028; // 24
+static const uint64_t SH_FLD_WT4CR_TIER2_EPS_VAL = 19029; // 24
+static const uint64_t SH_FLD_WT4CR_TIER2_EPS_VAL_LEN = 19030; // 24
+static const uint64_t SH_FLD_WTL_SM_STATUS = 19031; // 4
+static const uint64_t SH_FLD_WTL_SM_STATUS_LEN = 19032; // 4
+static const uint64_t SH_FLD_WTL_TEST_CLOCK = 19033; // 4
+static const uint64_t SH_FLD_WTL_TEST_DATA = 19034; // 4
+static const uint64_t SH_FLD_WTR_MAX_BAD_LANES = 19035; // 4
+static const uint64_t SH_FLD_WTR_MAX_BAD_LANES_LEN = 19036; // 4
+static const uint64_t SH_FLD_WT_ALL_DONE_GCRMSG = 19037; // 4
+static const uint64_t SH_FLD_WT_BS_CLOCK_EN_BYP = 19038; // 4
+static const uint64_t SH_FLD_WT_BS_DATA_EN_BYP = 19039; // 4
+static const uint64_t SH_FLD_WT_CHECK_COUNT = 19040; // 4
+static const uint64_t SH_FLD_WT_CHECK_COUNT_LEN = 19041; // 4
+static const uint64_t SH_FLD_WT_CLK_LANE_BAD_CODE = 19042; // 4
+static const uint64_t SH_FLD_WT_CLK_LANE_BAD_CODE_LEN = 19043; // 4
+static const uint64_t SH_FLD_WT_CLK_LANE_INVERTED = 19044; // 4
+static const uint64_t SH_FLD_WT_CU_BYP_PLL_LOCK = 19045; // 4
+static const uint64_t SH_FLD_WT_CU_PLL_PGOOD = 19046; // 4
+static const uint64_t SH_FLD_WT_EN_ALL_CLK_SEGS_GCRMSG = 19047; // 4
+static const uint64_t SH_FLD_WT_EN_ALL_DATA_SEGS_GCRMSG = 19048; // 4
+static const uint64_t SH_FLD_WT_LANE_BAD_CODE = 19049; // 96
+static const uint64_t SH_FLD_WT_LANE_BAD_CODE_LEN = 19050; // 96
+static const uint64_t SH_FLD_WT_LANE_DISABLED = 19051; // 96
+static const uint64_t SH_FLD_WT_PATTERN_LENGTH = 19052; // 8
+static const uint64_t SH_FLD_WT_PATTERN_LENGTH_LEN = 19053; // 8
+static const uint64_t SH_FLD_WT_PLL_REFCLKSEL = 19054; // 4
+static const uint64_t SH_FLD_WT_PREV_DONE_GCRMSG = 19055; // 4
+static const uint64_t SH_FLD_WT_TIMEOUT_SEL = 19056; // 4
+static const uint64_t SH_FLD_WT_TIMEOUT_SEL_LEN = 19057; // 4
+static const uint64_t SH_FLD_WWDM_DLY = 19058; // 8
+static const uint64_t SH_FLD_WWDM_DLY_LEN = 19059; // 8
+static const uint64_t SH_FLD_WWOP_DLY = 19060; // 8
+static const uint64_t SH_FLD_WWOP_DLY_LEN = 19061; // 8
+static const uint64_t SH_FLD_WWSMDR_DLY = 19062; // 8
+static const uint64_t SH_FLD_WWSMDR_DLY_LEN = 19063; // 8
+static const uint64_t SH_FLD_WWSMSR_DLY = 19064; // 8
+static const uint64_t SH_FLD_WWSMSR_DLY_LEN = 19065; // 8
+static const uint64_t SH_FLD_X0_ACT = 19066; // 1
+static const uint64_t SH_FLD_X0_HI = 19067; // 1
+static const uint64_t SH_FLD_X0_HI_LEN = 19068; // 1
+static const uint64_t SH_FLD_X0_LO = 19069; // 1
+static const uint64_t SH_FLD_X0_LO_LEN = 19070; // 1
+static const uint64_t SH_FLD_X0_TX_ENABLE = 19071; // 4
+static const uint64_t SH_FLD_X0_TX_SELECT = 19072; // 4
+static const uint64_t SH_FLD_X0_TX_SELECT_LEN = 19073; // 4
+static const uint64_t SH_FLD_X1_ACT = 19074; // 1
+static const uint64_t SH_FLD_X1_HI = 19075; // 1
+static const uint64_t SH_FLD_X1_HI_LEN = 19076; // 1
+static const uint64_t SH_FLD_X1_LO = 19077; // 1
+static const uint64_t SH_FLD_X1_LO_LEN = 19078; // 1
+static const uint64_t SH_FLD_X1_TX_ENABLE = 19079; // 4
+static const uint64_t SH_FLD_X1_TX_SELECT = 19080; // 4
+static const uint64_t SH_FLD_X1_TX_SELECT_LEN = 19081; // 4
+static const uint64_t SH_FLD_X2_ACT = 19082; // 1
+static const uint64_t SH_FLD_X2_HI = 19083; // 1
+static const uint64_t SH_FLD_X2_HI_LEN = 19084; // 1
+static const uint64_t SH_FLD_X2_LO = 19085; // 1
+static const uint64_t SH_FLD_X2_LO_LEN = 19086; // 1
+static const uint64_t SH_FLD_X2_TX_ENABLE = 19087; // 4
+static const uint64_t SH_FLD_X2_TX_SELECT = 19088; // 4
+static const uint64_t SH_FLD_X2_TX_SELECT_LEN = 19089; // 4
+static const uint64_t SH_FLD_X3_TX_ENABLE = 19090; // 4
+static const uint64_t SH_FLD_X3_TX_SELECT = 19091; // 4
+static const uint64_t SH_FLD_X3_TX_SELECT_LEN = 19092; // 4
+static const uint64_t SH_FLD_X4_TX_ENABLE = 19093; // 4
+static const uint64_t SH_FLD_X4_TX_SELECT = 19094; // 4
+static const uint64_t SH_FLD_X4_TX_SELECT_LEN = 19095; // 4
+static const uint64_t SH_FLD_X5_TX_ENABLE = 19096; // 4
+static const uint64_t SH_FLD_X5_TX_SELECT = 19097; // 4
+static const uint64_t SH_FLD_X5_TX_SELECT_LEN = 19098; // 4
+static const uint64_t SH_FLD_X6_TX_ENABLE = 19099; // 4
+static const uint64_t SH_FLD_X6_TX_SELECT = 19100; // 4
+static const uint64_t SH_FLD_X6_TX_SELECT_LEN = 19101; // 4
+static const uint64_t SH_FLD_X7_TX_ENABLE = 19102; // 4
+static const uint64_t SH_FLD_X7_TX_SELECT = 19103; // 4
+static const uint64_t SH_FLD_X7_TX_SELECT_LEN = 19104; // 4
+static const uint64_t SH_FLD_XARS = 19105; // 3
+static const uint64_t SH_FLD_XARSP = 19106; // 12
+static const uint64_t SH_FLD_XATS = 19107; // 12
+static const uint64_t SH_FLD_XCR = 19108; // 21
+static const uint64_t SH_FLD_XCR_LEN = 19109; // 21
+static const uint64_t SH_FLD_XIMEM_MEM_IFETCH_PENDING = 19110; // 21
+static const uint64_t SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 19111; // 21
+static const uint64_t SH_FLD_XIRAMGA_IR = 19112; // 21
+static const uint64_t SH_FLD_XIRAMGA_IR_LEN = 19113; // 21
+static const uint64_t SH_FLD_XIRAMRA_SPRG0 = 19114; // 42
+static const uint64_t SH_FLD_XIRAMRA_SPRG0_LEN = 19115; // 42
+static const uint64_t SH_FLD_XISIB_PIB_IFETCH_PENDING = 19116; // 1
+static const uint64_t SH_FLD_XIXCR_XCR = 19117; // 21
+static const uint64_t SH_FLD_XIXCR_XCR_LEN = 19118; // 21
+static const uint64_t SH_FLD_XLAT = 19119; // 16
+static const uint64_t SH_FLD_XLATE_TO_ADDR_ID_ENABLE = 19120; // 2
+static const uint64_t SH_FLD_XLAT_LEN = 19121; // 16
+static const uint64_t SH_FLD_XPT_ERROR_INJECT_ENABLE = 19122; // 2
+static const uint64_t SH_FLD_XPT_ERROR_INJECT_TARGET = 19123; // 2
+static const uint64_t SH_FLD_XPT_ERROR_INJECT_TARGET_LEN = 19124; // 2
+static const uint64_t SH_FLD_XPT_ERROR_TYPE = 19125; // 2
+static const uint64_t SH_FLD_XPT_ERROR_TYPE_LEN = 19126; // 2
+static const uint64_t SH_FLD_XPT_INJECT_CONTINUOUS_ERROR = 19127; // 2
+static const uint64_t SH_FLD_XPT_POWERBUS_CE = 19128; // 4
+static const uint64_t SH_FLD_XPT_POWERBUS_SUE = 19129; // 4
+static const uint64_t SH_FLD_XPT_POWERBUS_UE = 19130; // 4
+static const uint64_t SH_FLD_XPT_RECOVERABLE_ERROR = 19131; // 4
+static const uint64_t SH_FLD_XPT_SYS_XSTOP_ERROR = 19132; // 4
+static const uint64_t SH_FLD_XSCOM_DONE = 19133; // 96
+static const uint64_t SH_FLD_XSCOM_FAIL = 19134; // 96
+static const uint64_t SH_FLD_XSCOM_STATUS = 19135; // 96
+static const uint64_t SH_FLD_XSCOM_STATUS_LEN = 19136; // 96
+static const uint64_t SH_FLD_XSC_CMD_OVERRUN = 19137; // 1
+static const uint64_t SH_FLD_XSTOP = 19138; // 5
+static const uint64_t SH_FLD_XSTOP_GATE = 19139; // 1
+static const uint64_t SH_FLD_XTS_CONFIG_P = 19140; // 1
+static const uint64_t SH_FLD_XTS_INT = 19141; // 1
+static const uint64_t SH_FLD_XTS_PBUS_PROTOCOL = 19142; // 1
+static const uint64_t SH_FLD_XTS_PROTOCOL_CE = 19143; // 1
+static const uint64_t SH_FLD_XTS_PROTOCOL_UE = 19144; // 1
+static const uint64_t SH_FLD_XTS_RSVD_10 = 19145; // 1
+static const uint64_t SH_FLD_XTS_RSVD_11 = 19146; // 1
+static const uint64_t SH_FLD_XTS_RSVD_12 = 19147; // 1
+static const uint64_t SH_FLD_XTS_RSVD_13 = 19148; // 1
+static const uint64_t SH_FLD_XTS_RSVD_14 = 19149; // 1
+static const uint64_t SH_FLD_XTS_RSVD_15 = 19150; // 1
+static const uint64_t SH_FLD_XTS_RSVD_16 = 19151; // 1
+static const uint64_t SH_FLD_XTS_RSVD_17 = 19152; // 1
+static const uint64_t SH_FLD_XTS_RSVD_18 = 19153; // 1
+static const uint64_t SH_FLD_XTS_RSVD_19 = 19154; // 1
+static const uint64_t SH_FLD_XTS_RSVD_6 = 19155; // 1
+static const uint64_t SH_FLD_XTS_RSVD_7 = 19156; // 1
+static const uint64_t SH_FLD_XTS_RSVD_8 = 19157; // 1
+static const uint64_t SH_FLD_XTS_RSVD_9 = 19158; // 1
+static const uint64_t SH_FLD_XTS_SRAM_CE = 19159; // 1
+static const uint64_t SH_FLD_XTS_SRAM_UE = 19160; // 1
+static const uint64_t SH_FLD_Z = 19161; // 1
+static const uint64_t SH_FLD_ZCAL = 19162; // 12
+static const uint64_t SH_FLD_ZCAL_CYA_DATA_INV = 19163; // 4
+static const uint64_t SH_FLD_ZCAL_LEN = 19164; // 4
+static const uint64_t SH_FLD_ZCAL_N = 19165; // 4
+static const uint64_t SH_FLD_ZCAL_N_LEN = 19166; // 4
+static const uint64_t SH_FLD_ZCAL_P = 19167; // 4
+static const uint64_t SH_FLD_ZCAL_P_LEN = 19168; // 4
+static const uint64_t SH_FLD_ZCAL_RANGE_CHECK = 19169; // 4
+static const uint64_t SH_FLD_ZCAL_SM_MAX_VAL = 19170; // 4
+static const uint64_t SH_FLD_ZCAL_SM_MAX_VAL_LEN = 19171; // 4
+static const uint64_t SH_FLD_ZCAL_SM_MIN_VAL = 19172; // 4
+static const uint64_t SH_FLD_ZCAL_SM_MIN_VAL_LEN = 19173; // 4
+static const uint64_t SH_FLD_ZCAL_SWO_CAL_SEGS = 19174; // 4
+static const uint64_t SH_FLD_ZCAL_SWO_CMP_INV = 19175; // 4
+static const uint64_t SH_FLD_ZCAL_SWO_CMP_OFFSET = 19176; // 4
+static const uint64_t SH_FLD_ZCAL_SWO_CMP_RESET = 19177; // 4
+static const uint64_t SH_FLD_ZCAL_SWO_EN = 19178; // 4
+static const uint64_t SH_FLD_ZCAL_SWO_POWERDOWN = 19179; // 4
+static const uint64_t SH_FLD_ZCAL_SWO_TCOIL = 19180; // 4
+static const uint64_t SH_FLD_ZCAL_TEST_CLK_DIV = 19181; // 4
+static const uint64_t SH_FLD_ZCAL_TEST_OVR_1R = 19182; // 4
+static const uint64_t SH_FLD_ZCAL_TEST_OVR_2R = 19183; // 4
+static const uint64_t SH_FLD_ZCAL_TEST_OVR_4X_SEG = 19184; // 4
+
+#endif
diff --git a/src/import/chips/p9/common/include/p9_xbus_scom_addresses.H b/src/import/chips/p9/common/include/p9_xbus_scom_addresses.H
new file mode 100644
index 00000000..14edd5be
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_xbus_scom_addresses.H
@@ -0,0 +1,16124 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_xbus_scom_addresses.H $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_xbus_scom_addresses.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+/*---------------------------------------------------------------
+ *
+ *---------------------------------------------------------------
+ *
+ *  Issues:
+ *
+ * Closed
+ *    TOD reg same address.             HW323439
+ *       - Issue was closed with the explaination "same as p8"
+ *    IO0 registers need fixed.         HW320437
+ *    PHB registers need fixed.         HW320416  ( all regs commented out now )
+ *    OSC/perv regs same address.       HW323437
+ *    MC regs with same address.        HW323435 (matteo)
+ *         Duplicate IOM registers.          HW320456 (designers)
+ *    PEC Sat_id issue                  HW329652
+ *    PB.PB_PPE registers need fixed.   HW320435
+ *    EX05 registers need fixed.        HW320427  (9020) - L2 ring id's are incorrect
+ *    IOFPPE registers need fixed.      HW320424  (9020) - Investigate NULL scope
+ *    PEC addresses are wrong.          HW322598  (9020)
+ *    MC registers need fixed.          HW320433
+ *    VA.VA_NORTH registers need fixed. HW320436
+ *
+ * Format:
+ *
+ *  <UNIT>_<SUBUNIT>_<INSTANCE>_<REGISTER>_<ACCESS/TYPE>
+ *
+ *  Notes: Subunits are only added to make names unique when
+ *  there are name collisions.
+ *  Only units with more than one instance has instance numbers.
+ *  If there is only one, the instance number is omitted.
+ *
+ *  Instance numbers are chiplet id's for the PERV unit.  The
+ *  chiplet id's are mapped to their name and used instead of
+ *  instance numbers.  See bellow.
+ *
+ *  For registers with a single access type the type and access
+ *  methods are omitted.
+ *
+ *  For access types where all bits have the same access methods, the
+ *  access method is appended to the name.  If the access methods
+ *  are different for some bits, the access type is appended to the
+ *  name _SCOM instead of _RO.  The _RW(X) access method is omitted
+ *  and assumed to be default.
+ *
+ *  Valid units / subunits
+ *    PU                    : No unit chip level
+ *        MCD0[0..1]        : mcd subunit
+ *        PIB2OPB[0..1]     : PIB2OPB subunit
+ *        OTPROM[0..1]      : otprom subunit
+ *        NPU               : common npu subunit
+ *        NPU[0..2]         : Npu stacks 0 to 2
+ *          CTL             : Npu CTL subunit
+ *          DAT             : Npu DAT subunit
+ *          SM[0..3]        : Npu SM subunits
+ *          NTL[0..1]       : Npu NTL subunit
+ *    PERV                  : Pervasive
+ *        FSI2PIB           : subunit
+ *        FSISHIFT          : subunit
+ *        FSII2C            : subunit
+ *        FSB               : subunit
+ *    EX                    : Ex unit (1/2 quad, 2 cores)
+ *        L2                : L2 subunit
+ *        L3                : L3 subunit
+ *    PEC                   : PCI Pec unit
+ *        STACK0            : subunit
+ *        STACK1            : subunit
+ *        STACK2            : subunit
+ *    C                     : core
+ *    EQ                    : quad
+ *    OBUS                  : obus
+ *    CAPP                  : capp
+ *    MCBIST                : mcbist
+ *    MCA                   : mca
+ *    NVBUS                 : (not implemented yet)
+ *    PHB                   : (not implemented yet)
+ *    MI                    : (not implemented yet)
+ *    DMI                   : (not implemented yet)
+ *    MCS                   : (not implemented yet)
+ *    OCC                   : (not implemented yet)
+ *    PPE                   : (not implemented yet)
+ *    SBE                   : (not implemented yet)
+ *    XBUS                  : (not implemented yet)
+ *
+ * Pervasive instance names follow chiplet id.
+ *
+ * Instance/  | Chiplet
+ * Chiplet    | name
+ * -----------+-----------
+ * 0x00       | PIB
+ * 0x01       | TP
+ * 0x02       | N0
+ * 0x03       | N1
+ * 0x04       | N2
+ * 0x05       | N3
+ * 0x06       | XB
+ * 0x07       | MC01
+ * 0x08       | MC23
+ * 0x09       | OB0
+ * 0x0A       | OB1
+ * 0x0B       | OB2
+ * 0x0C       | OB3
+ * 0x0D       | PCI0
+ * 0x0E       | PCI1
+ * 0x0F       | PCI2
+ * 0x10       | EP00
+ * 0x11       | EP01
+ * 0x12       | EP02
+ * 0x13       | EP03
+ * 0x14       | EP04
+ * 0x15       | EP05
+ * 0x20       | EC00
+ * 0x21       | EC01
+ * 0x22       | EC02
+ * 0x23       | EC03
+ * 0x24       | EC04
+ * 0x25       | EC05
+ * 0x26       | EC06
+ * 0x27       | EC07
+ * 0x28       | EC08
+ * 0x29       | EC09
+ * 0x2A       | EC10
+ * 0x2B       | EC11
+ * 0x2C       | EC12
+ * 0x2D       | EC13
+ * 0x2E       | EC14
+ * 0x2F       | EC15
+ * 0x30       | EC16
+ * 0x31       | EC17
+ * 0x32       | EC18
+ * 0x33       | EC19
+ * 0x34       | EC20
+ * 0x35       | EC21
+ * 0x36       | EC22
+ * 0x37       | EC23
+ *
+ *
+ *---------------------------------------------------------------
+ *
+ * NOTES:
+ *
+ * there is a SPR ring that goes around the chip with an
+ * address(0:9)/tid(0:1) (thread id)/mfspr_data(0:63) and return mfspr_data_v/mfspr_data(0:63)
+ *
+ *    Add PU_<SUBUNITS>  (only if there are conflicts on these registers)
+ *       0x0001XXXX OTPROM
+ *       0x0002XXXX FSIM0
+ *       0x0003XXXX FSIM1
+ *       0x0004XXXX TOD
+ *       0x0005XXXX FSI_MBOX
+ *       0x0006XXXX OCI_BRIDGE
+ *       0x0007XXXX SPI_ADC
+ *       0x0008XXXX PIBMEM
+ *       0x0009XXXX ADU
+ *       0x000AXXXX I2CM
+ *       0x000BXXXX SBE_FIFO
+ *       0x000DXXXX PSU
+ *       0x000EXXXX SBE
+ *
+ * 0x0000100A for FSI2PIB  => PERV_FSI2PIB
+ * 0x00000Cxx for FSISHIFT =>  PERV_FSISHIFT
+ * 0x000018xx for FSI I2C =>  PERV_FSII2C
+ * 0x000024xx for FSI SBEFIFO => PERV_FSB
+ *
+ * 0x00000400 PEEK_TABLE
+ * 0x00000800 FSI_SLAVE
+ * 0x00000C00 FSI_SHIFT
+ * 0x00001000 FSI2PIB
+ * 0x00001400 FSI_SCRATCHPAD
+ * 0x00001800 FSI_I2CM
+ * 0x00002400 FSI_SBE_FIFO
+ *
+ * address fields
+ * 0xCCRPxxxx
+ *
+ * CC=chiplet
+ * R=always 0?
+ * P=port
+ *   0=gpregs
+ *   1=normal unit scom ring (exclude)
+ *   3=clock controller
+ *   4=firs
+ *   5=cpm
+ *
+ * =============================================================================
+ * Compiling
+ *
+ * Precompile the header to save time on subsquent compiles:
+ * g++ -I. -c scom_addresses.H
+ *
+ * Use these options to help reduce the binary size
+ * g++ -I. -Os -fdata-sections -ffunction-sections <file>.C -o <output> -Wl,--gc-sections
+ *
+ *
+ *---------------------------------------------------------------
+ */
+
+#include <p9_const_common.H>
+
+
+#ifndef __P9_XBUS_SCOM_ADDRESSES_H
+#define __P9_XBUS_SCOM_ADDRESSES_H
+
+
+#include <p9_scom_template_consts.H>
+#include <p9_xbus_scom_addresses_fixes.H>
+
+
+REG64( XBUS_IOPPE_CSAR                                         , RULL(0x06010858), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM_RW   );
+
+REG64( XBUS_IOPPE_CSCR                                         , RULL(0x06010855), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM_RW   );
+REG64( XBUS_IOPPE_CSCR_CLEAR                                   , RULL(0x06010801), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM1_CLEAR );
+REG64( XBUS_IOPPE_CSCR_OR                                      , RULL(0x06010802), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM2_OR  );
+
+REG64( XBUS_IOPPE_CSDR                                         , RULL(0x06010859), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM_RW   );
+
+REG64( XBUS_PERV_DBG_INST1_COND_REG_1                          , RULL(0x060107C1), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_DBG_INST1_COND_REG_2                          , RULL(0x060107C2), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_DBG_INST1_COND_REG_3                          , RULL(0x060107C3), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_DBG_INST2_COND_REG_1                          , RULL(0x060107C4), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_DBG_INST2_COND_REG_2                          , RULL(0x060107C5), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_DBG_INST2_COND_REG_3                          , RULL(0x060107C6), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_DBG_MODE_REG                                  , RULL(0x060107C0), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_DBG_TRACE_MODE_REG_2                          , RULL(0x060107CF), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_DBG_TRACE_REG_0                               , RULL(0x060107CD), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_DBG_TRACE_REG_1                               , RULL(0x060107CE), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_DEBUG_TRACE_CONTROL                           , RULL(0x060107D0), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_LL0_IOEL_CONFIG                                    , RULL(0x0601180A), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_0_LL0_IOEL_CONFIG                                  , RULL(0x0601180A), SH_UNT_XBUS_0   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL0_IOEL_CONTROL                                   , RULL(0x0601180B), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_0_LL0_IOEL_CONTROL                                 , RULL(0x0601180B), SH_UNT_XBUS_0   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL0_IOEL_DLL_STATUS                                , RULL(0x06011828), SH_UNT_XBUS     , SH_ACS_SCOM_RO   );
+REG64( XBUS_0_LL0_IOEL_DLL_STATUS                              , RULL(0x06011828), SH_UNT_XBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_LL0_IOEL_ERR_INJ_LFSR                              , RULL(0x0601181B), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_0_LL0_IOEL_ERR_INJ_LFSR                            , RULL(0x0601181B), SH_UNT_XBUS_0   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL0_IOEL_FIR_ACTION0_REG                           , RULL(0x06011806), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_0_LL0_IOEL_FIR_ACTION0_REG                         , RULL(0x06011806), SH_UNT_XBUS_0   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_LL0_IOEL_FIR_ACTION1_REG                           , RULL(0x06011807), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_0_LL0_IOEL_FIR_ACTION1_REG                         , RULL(0x06011807), SH_UNT_XBUS_0   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_LL0_IOEL_LAT_MEASURE                               , RULL(0x0601180E), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_0_LL0_IOEL_LAT_MEASURE                             , RULL(0x0601180E), SH_UNT_XBUS_0   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL0_IOEL_LINK0_EDPL_STATUS                         , RULL(0x06011824), SH_UNT_XBUS     , SH_ACS_SCOM_RO   );
+REG64( XBUS_0_LL0_IOEL_LINK0_EDPL_STATUS                       , RULL(0x06011824), SH_UNT_XBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_LL0_IOEL_LINK0_ERROR_STATUS                        , RULL(0x06011816), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_0_LL0_IOEL_LINK0_ERROR_STATUS                      , RULL(0x06011816), SH_UNT_XBUS_0   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL0_IOEL_LINK0_INFO                                , RULL(0x06011814), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_0_LL0_IOEL_LINK0_INFO                              , RULL(0x06011814), SH_UNT_XBUS_0   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL0_IOEL_LINK0_QUALITY                             , RULL(0x06011826), SH_UNT_XBUS     , SH_ACS_SCOM_RO   );
+REG64( XBUS_0_LL0_IOEL_LINK0_QUALITY                           , RULL(0x06011826), SH_UNT_XBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE                         , RULL(0x06011822), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_0_LL0_IOEL_LINK0_SYN_CAPTURE                       , RULL(0x06011822), SH_UNT_XBUS_0   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_LL0_IOEL_LINK1_EDPL_STATUS                         , RULL(0x06011825), SH_UNT_XBUS     , SH_ACS_SCOM_RO   );
+REG64( XBUS_0_LL0_IOEL_LINK1_EDPL_STATUS                       , RULL(0x06011825), SH_UNT_XBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_LL0_IOEL_LINK1_ERROR_STATUS                        , RULL(0x06011817), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_0_LL0_IOEL_LINK1_ERROR_STATUS                      , RULL(0x06011817), SH_UNT_XBUS_0   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL0_IOEL_LINK1_INFO                                , RULL(0x06011815), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_0_LL0_IOEL_LINK1_INFO                              , RULL(0x06011815), SH_UNT_XBUS_0   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL0_IOEL_LINK1_QUALITY                             , RULL(0x06011827), SH_UNT_XBUS     , SH_ACS_SCOM_RO   );
+REG64( XBUS_0_LL0_IOEL_LINK1_QUALITY                           , RULL(0x06011827), SH_UNT_XBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE                         , RULL(0x06011823), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_0_LL0_IOEL_LINK1_SYN_CAPTURE                       , RULL(0x06011823), SH_UNT_XBUS_0   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_LL0_IOEL_PERF_COUNTERS_0                           , RULL(0x0601181E), SH_UNT_XBUS     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( XBUS_0_LL0_IOEL_PERF_COUNTERS_0                         , RULL(0x0601181E), SH_UNT_XBUS_0   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( XBUS_LL0_IOEL_PERF_COUNTERS_1                           , RULL(0x0601181F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( XBUS_0_LL0_IOEL_PERF_COUNTERS_1                         , RULL(0x0601181F), SH_UNT_XBUS_0   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( XBUS_LL0_IOEL_PERF_COUNT_LSB_0                          , RULL(0x06011820), SH_UNT_XBUS     , SH_ACS_SCOM_RO   );
+REG64( XBUS_0_LL0_IOEL_PERF_COUNT_LSB_0                        , RULL(0x06011820), SH_UNT_XBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_LL0_IOEL_PERF_COUNT_LSB_1                          , RULL(0x06011821), SH_UNT_XBUS     , SH_ACS_SCOM_RO   );
+REG64( XBUS_0_LL0_IOEL_PERF_COUNT_LSB_1                        , RULL(0x06011821), SH_UNT_XBUS_0   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_LL0_IOEL_PERF_SEL_CONFIG                           , RULL(0x0601181D), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_0_LL0_IOEL_PERF_SEL_CONFIG                         , RULL(0x0601181D), SH_UNT_XBUS_0   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_LL0_IOEL_PERF_TRACE_CONFIG                         , RULL(0x0601181C), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_0_LL0_IOEL_PERF_TRACE_CONFIG                       , RULL(0x0601181C), SH_UNT_XBUS_0   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_LL0_IOEL_REPLAY_THRESHOLD                          , RULL(0x06011818), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_0_LL0_IOEL_REPLAY_THRESHOLD                        , RULL(0x06011818), SH_UNT_XBUS_0   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL0_IOEL_SEC_CONFIG                                , RULL(0x0601180D), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_0_LL0_IOEL_SEC_CONFIG                              , RULL(0x0601180D), SH_UNT_XBUS_0   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_LL0_IOEL_SL_ECC_THRESHOLD                          , RULL(0x06011819), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_0_LL0_IOEL_SL_ECC_THRESHOLD                        , RULL(0x06011819), SH_UNT_XBUS_0   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG                      , RULL(0x06011803), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_AND                  , RULL(0x06011804), SH_UNT_XBUS     , SH_ACS_SCOM1_AND );
+REG64( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_OR                   , RULL(0x06011805), SH_UNT_XBUS     , SH_ACS_SCOM2_OR  );
+REG64( XBUS_0_LL0_LL0_LL0_IOEL_FIR_MASK_REG                    , RULL(0x06011803), SH_UNT_XBUS_0   , SH_ACS_SCOM_RW   );
+REG64( XBUS_0_LL0_LL0_LL0_IOEL_FIR_MASK_REG_AND                , RULL(0x06011804), SH_UNT_XBUS_0   , SH_ACS_SCOM1_AND );
+REG64( XBUS_0_LL0_LL0_LL0_IOEL_FIR_MASK_REG_OR                 , RULL(0x06011805), SH_UNT_XBUS_0   , SH_ACS_SCOM2_OR  );
+
+REG64( XBUS_LL0_LL0_LL0_IOEL_FIR_REG                           , RULL(0x06011800), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_AND                       , RULL(0x06011801), SH_UNT_XBUS     , SH_ACS_SCOM1_AND );
+REG64( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_OR                        , RULL(0x06011802), SH_UNT_XBUS     , SH_ACS_SCOM2_OR  );
+REG64( XBUS_0_LL0_LL0_LL0_IOEL_FIR_REG                         , RULL(0x06011800), SH_UNT_XBUS_0   , SH_ACS_SCOM_RW   );
+REG64( XBUS_0_LL0_LL0_LL0_IOEL_FIR_REG_AND                     , RULL(0x06011801), SH_UNT_XBUS_0   , SH_ACS_SCOM1_AND );
+REG64( XBUS_0_LL0_LL0_LL0_IOEL_FIR_REG_OR                      , RULL(0x06011802), SH_UNT_XBUS_0   , SH_ACS_SCOM2_OR  );
+
+REG64( XBUS_LL1_IOEL_CONFIG                                    , RULL(0x06010C0A), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_1_LL1_IOEL_CONFIG                                  , RULL(0x06011C0A), SH_UNT_XBUS_1   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL1_IOEL_CONTROL                                   , RULL(0x06010C0B), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_1_LL1_IOEL_CONTROL                                 , RULL(0x06011C0B), SH_UNT_XBUS_1   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL1_IOEL_DLL_STATUS                                , RULL(0x06010C28), SH_UNT_XBUS     , SH_ACS_SCOM_RO   );
+REG64( XBUS_1_LL1_IOEL_DLL_STATUS                              , RULL(0x06011C28), SH_UNT_XBUS_1   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_LL1_IOEL_ERR_INJ_LFSR                              , RULL(0x06010C1B), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_1_LL1_IOEL_ERR_INJ_LFSR                            , RULL(0x06011C1B), SH_UNT_XBUS_1   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL1_IOEL_FIR_ACTION0_REG                           , RULL(0x06010C06), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_1_LL1_IOEL_FIR_ACTION0_REG                         , RULL(0x06011C06), SH_UNT_XBUS_1   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_LL1_IOEL_FIR_ACTION1_REG                           , RULL(0x06010C07), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_1_LL1_IOEL_FIR_ACTION1_REG                         , RULL(0x06011C07), SH_UNT_XBUS_1   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_LL1_IOEL_LAT_MEASURE                               , RULL(0x06010C0E), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_1_LL1_IOEL_LAT_MEASURE                             , RULL(0x06011C0E), SH_UNT_XBUS_1   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL1_IOEL_LINK0_EDPL_STATUS                         , RULL(0x06010C24), SH_UNT_XBUS     , SH_ACS_SCOM_RO   );
+REG64( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS                       , RULL(0x06011C24), SH_UNT_XBUS_1   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_LL1_IOEL_LINK0_ERROR_STATUS                        , RULL(0x06010C16), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_1_LL1_IOEL_LINK0_ERROR_STATUS                      , RULL(0x06011C16), SH_UNT_XBUS_1   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL1_IOEL_LINK0_INFO                                , RULL(0x06010C14), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_1_LL1_IOEL_LINK0_INFO                              , RULL(0x06011C14), SH_UNT_XBUS_1   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL1_IOEL_LINK0_QUALITY                             , RULL(0x06010C26), SH_UNT_XBUS     , SH_ACS_SCOM_RO   );
+REG64( XBUS_1_LL1_IOEL_LINK0_QUALITY                           , RULL(0x06011C26), SH_UNT_XBUS_1   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_LL1_IOEL_LINK0_SYN_CAPTURE                         , RULL(0x06010C22), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE                       , RULL(0x06011C22), SH_UNT_XBUS_1   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_LL1_IOEL_LINK1_EDPL_STATUS                         , RULL(0x06010C25), SH_UNT_XBUS     , SH_ACS_SCOM_RO   );
+REG64( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS                       , RULL(0x06011C25), SH_UNT_XBUS_1   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_LL1_IOEL_LINK1_ERROR_STATUS                        , RULL(0x06010C17), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_1_LL1_IOEL_LINK1_ERROR_STATUS                      , RULL(0x06011C17), SH_UNT_XBUS_1   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL1_IOEL_LINK1_INFO                                , RULL(0x06010C15), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_1_LL1_IOEL_LINK1_INFO                              , RULL(0x06011C15), SH_UNT_XBUS_1   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL1_IOEL_LINK1_QUALITY                             , RULL(0x06010C27), SH_UNT_XBUS     , SH_ACS_SCOM_RO   );
+REG64( XBUS_1_LL1_IOEL_LINK1_QUALITY                           , RULL(0x06011C27), SH_UNT_XBUS_1   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_LL1_IOEL_LINK1_SYN_CAPTURE                         , RULL(0x06010C23), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE                       , RULL(0x06011C23), SH_UNT_XBUS_1   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_LL1_IOEL_PERF_COUNTERS_0                           , RULL(0x06010C1E), SH_UNT_XBUS     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( XBUS_1_LL1_IOEL_PERF_COUNTERS_0                         , RULL(0x06011C1E), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( XBUS_LL1_IOEL_PERF_COUNTERS_1                           , RULL(0x06010C1F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM_WCLRREG );
+REG64( XBUS_1_LL1_IOEL_PERF_COUNTERS_1                         , RULL(0x06011C1F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( XBUS_LL1_IOEL_PERF_COUNT_LSB_0                          , RULL(0x06010C20), SH_UNT_XBUS     , SH_ACS_SCOM_RO   );
+REG64( XBUS_1_LL1_IOEL_PERF_COUNT_LSB_0                        , RULL(0x06011C20), SH_UNT_XBUS_1   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_LL1_IOEL_PERF_COUNT_LSB_1                          , RULL(0x06010C21), SH_UNT_XBUS     , SH_ACS_SCOM_RO   );
+REG64( XBUS_1_LL1_IOEL_PERF_COUNT_LSB_1                        , RULL(0x06011C21), SH_UNT_XBUS_1   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_LL1_IOEL_PERF_SEL_CONFIG                           , RULL(0x06010C1D), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG                         , RULL(0x06011C1D), SH_UNT_XBUS_1   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_LL1_IOEL_PERF_TRACE_CONFIG                         , RULL(0x06010C1C), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG                       , RULL(0x06011C1C), SH_UNT_XBUS_1   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_LL1_IOEL_REPLAY_THRESHOLD                          , RULL(0x06010C18), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD                        , RULL(0x06011C18), SH_UNT_XBUS_1   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL1_IOEL_SEC_CONFIG                                , RULL(0x06010C0D), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_1_LL1_IOEL_SEC_CONFIG                              , RULL(0x06011C0D), SH_UNT_XBUS_1   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_LL1_IOEL_SL_ECC_THRESHOLD                          , RULL(0x06010C19), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD                        , RULL(0x06011C19), SH_UNT_XBUS_1   , SH_ACS_SCOM      );
+
+REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_MASK_REG                      , RULL(0x06010C03), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG                    , RULL(0x06011C03), SH_UNT_XBUS_1   , SH_ACS_SCOM_RW   );
+REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_MASK_REG_AND                  , RULL(0x06010C04), SH_UNT_XBUS     , SH_ACS_SCOM1_AND );
+REG64( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_AND                , RULL(0x06011C04), SH_UNT_XBUS_1   , SH_ACS_SCOM1_AND );
+REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_MASK_REG_OR                   , RULL(0x06010C05), SH_UNT_XBUS     , SH_ACS_SCOM2_OR  );
+REG64( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_OR                 , RULL(0x06011C05), SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR  );
+
+REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_REG                           , RULL(0x06010C00), SH_UNT_XBUS     , SH_ACS_SCOM_RW   );
+REG64( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG                         , RULL(0x06011C00), SH_UNT_XBUS_1   , SH_ACS_SCOM_RW   );
+REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_REG_AND                       , RULL(0x06010C01), SH_UNT_XBUS     , SH_ACS_SCOM1_AND );
+REG64( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_AND                     , RULL(0x06011C01), SH_UNT_XBUS_1   , SH_ACS_SCOM1_AND );
+REG64( XBUS_LL1_LL1_LL1_IOEL_FIR_REG_OR                        , RULL(0x06010C02), SH_UNT_XBUS     , SH_ACS_SCOM2_OR  );
+REG64( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_OR                      , RULL(0x06011C02), SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR  );
+
+REG64( XBUS_2_LL2_IOEL_CONFIG                                  , RULL(0x0601200A), SH_UNT_XBUS_2   , SH_ACS_SCOM      );
+
+REG64( XBUS_2_LL2_IOEL_CONTROL                                 , RULL(0x0601200B), SH_UNT_XBUS_2   , SH_ACS_SCOM      );
+
+REG64( XBUS_2_LL2_IOEL_DLL_STATUS                              , RULL(0x06012028), SH_UNT_XBUS_2   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_2_LL2_IOEL_ERR_INJ_LFSR                            , RULL(0x0601201B), SH_UNT_XBUS_2   , SH_ACS_SCOM      );
+
+REG64( XBUS_2_LL2_IOEL_FIR_ACTION0_REG                         , RULL(0x06012006), SH_UNT_XBUS_2   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_2_LL2_IOEL_FIR_ACTION1_REG                         , RULL(0x06012007), SH_UNT_XBUS_2   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_2_LL2_IOEL_LAT_MEASURE                             , RULL(0x0601200E), SH_UNT_XBUS_2   , SH_ACS_SCOM      );
+
+REG64( XBUS_2_LL2_IOEL_LINK0_EDPL_STATUS                       , RULL(0x06012024), SH_UNT_XBUS_2   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_2_LL2_IOEL_LINK0_ERROR_STATUS                      , RULL(0x06012016), SH_UNT_XBUS_2   , SH_ACS_SCOM      );
+
+REG64( XBUS_2_LL2_IOEL_LINK0_INFO                              , RULL(0x06012014), SH_UNT_XBUS_2   , SH_ACS_SCOM      );
+
+REG64( XBUS_2_LL2_IOEL_LINK0_QUALITY                           , RULL(0x06012026), SH_UNT_XBUS_2   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_2_LL2_IOEL_LINK0_SYN_CAPTURE                       , RULL(0x06012022), SH_UNT_XBUS_2   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_2_LL2_IOEL_LINK1_EDPL_STATUS                       , RULL(0x06012025), SH_UNT_XBUS_2   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_2_LL2_IOEL_LINK1_ERROR_STATUS                      , RULL(0x06012017), SH_UNT_XBUS_2   , SH_ACS_SCOM      );
+
+REG64( XBUS_2_LL2_IOEL_LINK1_INFO                              , RULL(0x06012015), SH_UNT_XBUS_2   , SH_ACS_SCOM      );
+
+REG64( XBUS_2_LL2_IOEL_LINK1_QUALITY                           , RULL(0x06012027), SH_UNT_XBUS_2   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_2_LL2_IOEL_LINK1_SYN_CAPTURE                       , RULL(0x06012023), SH_UNT_XBUS_2   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_2_LL2_IOEL_PERF_COUNTERS_0                         , RULL(0x0601201E), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( XBUS_2_LL2_IOEL_PERF_COUNTERS_1                         , RULL(0x0601201F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM_WCLRREG );
+
+REG64( XBUS_2_LL2_IOEL_PERF_COUNT_LSB_0                        , RULL(0x06012020), SH_UNT_XBUS_2   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_2_LL2_IOEL_PERF_COUNT_LSB_1                        , RULL(0x06012021), SH_UNT_XBUS_2   , SH_ACS_SCOM_RO   );
+
+REG64( XBUS_2_LL2_IOEL_PERF_SEL_CONFIG                         , RULL(0x0601201D), SH_UNT_XBUS_2   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_2_LL2_IOEL_PERF_TRACE_CONFIG                       , RULL(0x0601201C), SH_UNT_XBUS_2   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_2_LL2_IOEL_REPLAY_THRESHOLD                        , RULL(0x06012018), SH_UNT_XBUS_2   , SH_ACS_SCOM      );
+
+REG64( XBUS_2_LL2_IOEL_SEC_CONFIG                              , RULL(0x0601200D), SH_UNT_XBUS_2   , SH_ACS_SCOM_RW   );
+
+REG64( XBUS_2_LL2_IOEL_SL_ECC_THRESHOLD                        , RULL(0x06012019), SH_UNT_XBUS_2   , SH_ACS_SCOM      );
+
+REG64( XBUS_2_LL2_LL2_LL2_IOEL_FIR_MASK_REG                    , RULL(0x06012003), SH_UNT_XBUS_2   , SH_ACS_SCOM_RW   );
+REG64( XBUS_2_LL2_LL2_LL2_IOEL_FIR_MASK_REG_AND                , RULL(0x06012004), SH_UNT_XBUS_2   , SH_ACS_SCOM1_AND );
+REG64( XBUS_2_LL2_LL2_LL2_IOEL_FIR_MASK_REG_OR                 , RULL(0x06012005), SH_UNT_XBUS_2   , SH_ACS_SCOM2_OR  );
+
+REG64( XBUS_2_LL2_LL2_LL2_IOEL_FIR_REG                         , RULL(0x06012000), SH_UNT_XBUS_2   , SH_ACS_SCOM_RW   );
+REG64( XBUS_2_LL2_LL2_LL2_IOEL_FIR_REG_AND                     , RULL(0x06012001), SH_UNT_XBUS_2   , SH_ACS_SCOM1_AND );
+REG64( XBUS_2_LL2_LL2_LL2_IOEL_FIR_REG_OR                      , RULL(0x06012002), SH_UNT_XBUS_2   , SH_ACS_SCOM2_OR  );
+
+REG64( XBUS_IOPPE_MIB_XIICAC                                   , RULL(0x06010853), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM_RO   );
+
+REG64( XBUS_IOPPE_MIB_XIMEM                                    , RULL(0x06010851), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM_RO   );
+
+REG64( XBUS_IOPPE_MIB_XISGB                                    , RULL(0x06010852), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM_RO   );
+
+REG64( XBUS_IOPPE_PPE_XIDBGPRO                                 , RULL(0x0601084F), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_IOPPE_PPE_XIRAMDBG                                 , RULL(0x0601084D), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_IOPPE_PPE_XIRAMEDR                                 , RULL(0x0601084E), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_IOPPE_PPE_XIRAMGA                                  , RULL(0x0601084C), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM_WO   );
+
+REG64( XBUS_IOPPE_PPE_XIRAMRA                                  , RULL(0x0601084B), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM_WO   );
+
+REG64( XBUS_IOPPE_PPE_XIXCR                                    , RULL(0x0601084A), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM_WO   );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL              , RULL(0x8003000D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x8003000D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x8003000D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL              , RULL(0x8003080D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x8003080D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x8003080D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL              , RULL(0x8003100D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x8003100D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x8003100D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL             , RULL(0x8002200D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x8002200D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x8002200D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL              , RULL(0x8002C00D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C00D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C00D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL             , RULL(0x8002280D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x8002280D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x8002280D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL              , RULL(0x8002C80D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C80D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C80D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL             , RULL(0x8002300D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x8002300D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x8002300D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL             , RULL(0x8002680D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x8002680D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x8002680D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL             , RULL(0x8002700D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x8002700D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x8002700D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL             , RULL(0x8002780D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x8002780D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x8002780D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL              , RULL(0x8000800D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x8000800D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x8000800D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL              , RULL(0x8000880D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x8000880D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x8000880D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL              , RULL(0x8000900D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x8000900D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x8000900D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL              , RULL(0x8000980D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x8000980D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x8000980D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A00D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A00D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A80D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A80D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B00D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B00D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B80D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B80D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C00D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C00D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL                 , RULL(0x8002100D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL               , RULL(0x8002100D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL               , RULL(0x8002100D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_FIR_PL                      , RULL(0x8002080D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_FIR_PL                    , RULL(0x8002080D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_FIR_PL                    , RULL(0x8002080D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL               , RULL(0x8002000D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL             , RULL(0x8002000D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL             , RULL(0x8002000D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL              , RULL(0x8003000F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x8003000F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x8003000F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL              , RULL(0x8003080F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x8003080F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x8003080F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL              , RULL(0x8003100F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x8003100F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x8003100F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL             , RULL(0x8002200F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x8002200F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x8002200F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL              , RULL(0x8002C00F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C00F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C00F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL             , RULL(0x8002280F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x8002280F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x8002280F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL              , RULL(0x8002C80F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C80F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C80F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL             , RULL(0x8002300F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x8002300F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x8002300F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL             , RULL(0x8002680F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x8002680F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x8002680F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL             , RULL(0x8002700F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x8002700F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x8002700F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL             , RULL(0x8002780F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x8002780F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x8002780F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL              , RULL(0x8000800F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x8000800F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x8000800F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL              , RULL(0x8000880F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x8000880F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x8000880F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL              , RULL(0x8000900F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x8000900F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x8000900F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL              , RULL(0x8000980F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x8000980F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x8000980F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A00F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A00F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A80F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A80F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B00F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B00F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B80F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B80F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C00F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C00F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL                 , RULL(0x8002100F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL               , RULL(0x8002100F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL               , RULL(0x8002100F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_FIR_PL                      , RULL(0x8002080F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_FIR_PL                    , RULL(0x8002080F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_FIR_PL                    , RULL(0x8002080F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL               , RULL(0x8002000F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL             , RULL(0x8002000F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL             , RULL(0x8002000F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL              , RULL(0x8003000E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x8003000E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x8003000E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL              , RULL(0x8003080E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x8003080E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x8003080E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL              , RULL(0x8003100E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x8003100E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x8003100E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL             , RULL(0x8002200E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x8002200E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x8002200E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL              , RULL(0x8002C00E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C00E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C00E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL             , RULL(0x8002280E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x8002280E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x8002280E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL              , RULL(0x8002C80E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C80E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C80E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL             , RULL(0x8002300E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x8002300E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x8002300E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL             , RULL(0x8002680E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x8002680E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x8002680E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL             , RULL(0x8002700E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x8002700E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x8002700E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL             , RULL(0x8002780E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x8002780E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x8002780E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL              , RULL(0x8000800E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x8000800E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x8000800E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL              , RULL(0x8000880E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x8000880E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x8000880E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL              , RULL(0x8000900E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x8000900E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x8000900E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL              , RULL(0x8000980E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x8000980E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x8000980E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A00E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A00E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A80E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A80E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B00E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B00E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B80E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B80E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C00E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C00E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL                 , RULL(0x8002100E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL               , RULL(0x8002100E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL               , RULL(0x8002100E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_FIR_PL                      , RULL(0x8002080E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_FIR_PL                    , RULL(0x8002080E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_FIR_PL                    , RULL(0x8002080E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL               , RULL(0x8002000E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL             , RULL(0x8002000E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL             , RULL(0x8002000E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL              , RULL(0x8003001006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x800300100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x800300100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL             , RULL(0x8002481006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL              , RULL(0x8003081006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x800308100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x800308100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL             , RULL(0x8002501006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL              , RULL(0x8003101006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x800310100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x800310100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL             , RULL(0x8002581006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL             , RULL(0x8002601006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002401006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL             , RULL(0x8002201006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL              , RULL(0x8002C01006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C0100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C0100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL             , RULL(0x8002281006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL              , RULL(0x8002C81006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C8100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C8100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL             , RULL(0x8002301006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL             , RULL(0x8002681006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL             , RULL(0x8002701006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL             , RULL(0x8002781006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL             , RULL(0x8000081006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL              , RULL(0x8000801006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x800080100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x800080100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL             , RULL(0x8000101006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL              , RULL(0x8000881006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x800088100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x800088100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL             , RULL(0x8000181006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL              , RULL(0x8000901006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x800090100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x800090100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL             , RULL(0x8000201006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL              , RULL(0x8000981006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x800098100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x800098100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL             , RULL(0x8000281006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL              , RULL(0x8000A01006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL             , RULL(0x8000301006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL              , RULL(0x8000A81006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL             , RULL(0x8000381006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL              , RULL(0x8000B01006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL             , RULL(0x8000401006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL              , RULL(0x8000B81006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL              , RULL(0x8000C01006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000001006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002181006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL                 , RULL(0x8002101006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_FIR_PL                      , RULL(0x8002081006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_FIR_PL                    , RULL(0x800208100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_FIR_PL                    , RULL(0x800208100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL               , RULL(0x8002001006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL              , RULL(0x8003000B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x8003000B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x8003000B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL              , RULL(0x8003080B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x8003080B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x8003080B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL              , RULL(0x8003100B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x8003100B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x8003100B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL             , RULL(0x8002200B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x8002200B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x8002200B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL              , RULL(0x8002C00B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C00B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C00B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL             , RULL(0x8002280B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x8002280B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x8002280B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL              , RULL(0x8002C80B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C80B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C80B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL             , RULL(0x8002300B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x8002300B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x8002300B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL             , RULL(0x8002680B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x8002680B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x8002680B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL             , RULL(0x8002700B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x8002700B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x8002700B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL             , RULL(0x8002780B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x8002780B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x8002780B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL              , RULL(0x8000800B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x8000800B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x8000800B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL              , RULL(0x8000880B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x8000880B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x8000880B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL              , RULL(0x8000900B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x8000900B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x8000900B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL              , RULL(0x8000980B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x8000980B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x8000980B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A00B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A00B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A80B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A80B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B00B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B00B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B80B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B80B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C00B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C00B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL                 , RULL(0x8002100B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL               , RULL(0x8002100B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL               , RULL(0x8002100B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_FIR_PL                      , RULL(0x8002080B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_FIR_PL                    , RULL(0x8002080B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_FIR_PL                    , RULL(0x8002080B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL               , RULL(0x8002000B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL             , RULL(0x8002000B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL             , RULL(0x8002000B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL              , RULL(0x8003000906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x800300090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x800300090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x800248090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x800248090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL              , RULL(0x8003080906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x800308090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x800308090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x800250090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x800250090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL              , RULL(0x8003100906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x800310090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x800310090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x800258090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x800258090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x800260090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x800260090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL             , RULL(0x8002200906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x800220090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x800220090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL              , RULL(0x8002C00906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C0090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C0090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL             , RULL(0x8002280906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x800228090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x800228090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL              , RULL(0x8002C80906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C8090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C8090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL             , RULL(0x8002300906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x800230090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x800230090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL             , RULL(0x8002680906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x800268090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x800268090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL             , RULL(0x8002700906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x800270090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x800270090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL             , RULL(0x8002780906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x800278090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x800278090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x800008090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x800008090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL              , RULL(0x8000800906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x800080090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x800080090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x800010090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x800010090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL              , RULL(0x8000880906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x800088090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x800088090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x800018090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x800018090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL              , RULL(0x8000900906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x800090090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x800090090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x800020090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x800020090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL              , RULL(0x8000980906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x800098090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x800098090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x800028090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x800028090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x800030090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x800030090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x800038090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x800038090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x800040090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x800040090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL                 , RULL(0x8002100906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL               , RULL(0x800210090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL               , RULL(0x800210090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_FIR_PL                      , RULL(0x8002080906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_FIR_PL                    , RULL(0x800208090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_FIR_PL                    , RULL(0x800208090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL               , RULL(0x8002000906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL             , RULL(0x800200090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL             , RULL(0x800200090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL              , RULL(0x8003000C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x8003000C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x8003000C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL              , RULL(0x8003080C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x8003080C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x8003080C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL              , RULL(0x8003100C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x8003100C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x8003100C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL             , RULL(0x8002200C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x8002200C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x8002200C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL              , RULL(0x8002C00C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C00C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C00C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL             , RULL(0x8002280C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x8002280C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x8002280C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL              , RULL(0x8002C80C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C80C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C80C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL             , RULL(0x8002300C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x8002300C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x8002300C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL             , RULL(0x8002680C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x8002680C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x8002680C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL             , RULL(0x8002700C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x8002700C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x8002700C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL             , RULL(0x8002780C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x8002780C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x8002780C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL              , RULL(0x8000800C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x8000800C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x8000800C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL              , RULL(0x8000880C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x8000880C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x8000880C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL              , RULL(0x8000900C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x8000900C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x8000900C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL              , RULL(0x8000980C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x8000980C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x8000980C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A00C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A00C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A80C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A80C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B00C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B00C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B80C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B80C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C00C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C00C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL                 , RULL(0x8002100C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL               , RULL(0x8002100C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL               , RULL(0x8002100C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_FIR_PL                      , RULL(0x8002080C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_FIR_PL                    , RULL(0x8002080C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_FIR_PL                    , RULL(0x8002080C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL               , RULL(0x8002000C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL             , RULL(0x8002000C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL             , RULL(0x8002000C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL              , RULL(0x8003000A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x8003000A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x8003000A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x8002480A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL              , RULL(0x8003080A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x8003080A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x8003080A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x8002500A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL              , RULL(0x8003100A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x8003100A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x8003100A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x8002580A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x8002600A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002400A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL             , RULL(0x8002200A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x8002200A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x8002200A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL              , RULL(0x8002C00A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C00A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C00A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL             , RULL(0x8002280A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x8002280A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x8002280A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL              , RULL(0x8002C80A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C80A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C80A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL             , RULL(0x8002300A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x8002300A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x8002300A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL             , RULL(0x8002680A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x8002680A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x8002680A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL             , RULL(0x8002700A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x8002700A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x8002700A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL             , RULL(0x8002780A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x8002780A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x8002780A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x8000080A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL              , RULL(0x8000800A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x8000800A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x8000800A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x8000100A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL              , RULL(0x8000880A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x8000880A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x8000880A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x8000180A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL              , RULL(0x8000900A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x8000900A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x8000900A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x8000200A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL              , RULL(0x8000980A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x8000980A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x8000980A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x8000280A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A00A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A00A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x8000300A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A80A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A80A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x8000380A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B00A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B00A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x8000400A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B80A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B80A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C00A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C00A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000000A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002180A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL                 , RULL(0x8002100A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL               , RULL(0x8002100A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL               , RULL(0x8002100A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_FIR_PL                      , RULL(0x8002080A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_FIR_PL                    , RULL(0x8002080A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_FIR_PL                    , RULL(0x8002080A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL               , RULL(0x8002000A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL             , RULL(0x8002000A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL             , RULL(0x8002000A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL              , RULL(0x8003000706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x800300070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x800300070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x800248070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x800248070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL              , RULL(0x8003080706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x800308070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x800308070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x800250070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x800250070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL              , RULL(0x8003100706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x800310070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x800310070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x800258070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x800258070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x800260070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x800260070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL             , RULL(0x8002200706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x800220070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x800220070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL              , RULL(0x8002C00706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C0070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C0070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL             , RULL(0x8002280706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x800228070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x800228070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL              , RULL(0x8002C80706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C8070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C8070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL             , RULL(0x8002300706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x800230070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x800230070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL             , RULL(0x8002680706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x800268070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x800268070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL             , RULL(0x8002700706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x800270070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x800270070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL             , RULL(0x8002780706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x800278070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x800278070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x800008070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x800008070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL              , RULL(0x8000800706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x800080070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x800080070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x800010070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x800010070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL              , RULL(0x8000880706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x800088070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x800088070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x800018070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x800018070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL              , RULL(0x8000900706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x800090070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x800090070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x800020070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x800020070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL              , RULL(0x8000980706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x800098070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x800098070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x800028070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x800028070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x800030070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x800030070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x800038070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x800038070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x800040070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x800040070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL                 , RULL(0x8002100706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL               , RULL(0x800210070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL               , RULL(0x800210070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_FIR_PL                      , RULL(0x8002080706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_FIR_PL                    , RULL(0x800208070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_FIR_PL                    , RULL(0x800208070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL               , RULL(0x8002000706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL             , RULL(0x800200070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL             , RULL(0x800200070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL              , RULL(0x8003001106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x800300110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x800300110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL             , RULL(0x8002481106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x800248110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x800248110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL              , RULL(0x8003081106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x800308110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x800308110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL             , RULL(0x8002501106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x800250110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x800250110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL              , RULL(0x8003101106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x800310110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x800310110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL             , RULL(0x8002581106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x800258110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x800258110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL             , RULL(0x8002601106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x800260110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x800260110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002401106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL             , RULL(0x8002201106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x800220110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x800220110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL              , RULL(0x8002C01106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C0110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C0110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL             , RULL(0x8002281106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x800228110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x800228110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL              , RULL(0x8002C81106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C8110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C8110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL             , RULL(0x8002301106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x800230110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x800230110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL             , RULL(0x8002681106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x800268110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x800268110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL             , RULL(0x8002701106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x800270110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x800270110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL             , RULL(0x8002781106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x800278110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x800278110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL             , RULL(0x8000081106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x800008110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x800008110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL              , RULL(0x8000801106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x800080110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x800080110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL             , RULL(0x8000101106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x800010110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x800010110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL              , RULL(0x8000881106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x800088110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x800088110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL             , RULL(0x8000181106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x800018110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x800018110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL              , RULL(0x8000901106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x800090110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x800090110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL             , RULL(0x8000201106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x800020110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x800020110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL              , RULL(0x8000981106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x800098110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x800098110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL             , RULL(0x8000281106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x800028110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x800028110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL              , RULL(0x8000A01106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL             , RULL(0x8000301106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x800030110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x800030110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL              , RULL(0x8000A81106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL             , RULL(0x8000381106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x800038110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x800038110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL              , RULL(0x8000B01106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL             , RULL(0x8000401106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x800040110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x800040110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL              , RULL(0x8000B81106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL              , RULL(0x8000C01106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000001106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002181106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL                 , RULL(0x8002101106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL               , RULL(0x800210110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL               , RULL(0x800210110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_FIR_PL                      , RULL(0x8002081106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_FIR_PL                    , RULL(0x800208110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_FIR_PL                    , RULL(0x800208110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL               , RULL(0x8002001106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL             , RULL(0x800200110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL             , RULL(0x800200110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL              , RULL(0x8003000606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x800300060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x800300060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x800248060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x800248060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL              , RULL(0x8003080606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x800308060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x800308060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x800250060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x800250060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL              , RULL(0x8003100606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x800310060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x800310060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x800258060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x800258060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x800260060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x800260060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL             , RULL(0x8002200606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x800220060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x800220060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL              , RULL(0x8002C00606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C0060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C0060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL             , RULL(0x8002280606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x800228060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x800228060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL              , RULL(0x8002C80606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C8060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C8060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL             , RULL(0x8002300606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x800230060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x800230060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL             , RULL(0x8002680606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x800268060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x800268060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL             , RULL(0x8002700606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x800270060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x800270060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL             , RULL(0x8002780606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x800278060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x800278060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x800008060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x800008060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL              , RULL(0x8000800606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x800080060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x800080060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x800010060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x800010060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL              , RULL(0x8000880606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x800088060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x800088060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x800018060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x800018060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL              , RULL(0x8000900606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x800090060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x800090060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x800020060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x800020060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL              , RULL(0x8000980606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x800098060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x800098060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x800028060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x800028060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x800030060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x800030060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x800038060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x800038060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x800040060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x800040060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL                 , RULL(0x8002100606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL               , RULL(0x800210060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL               , RULL(0x800210060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_FIR_PL                      , RULL(0x8002080606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_FIR_PL                    , RULL(0x800208060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_FIR_PL                    , RULL(0x800208060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL               , RULL(0x8002000606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL             , RULL(0x800200060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL             , RULL(0x800200060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL              , RULL(0x8003000806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x800300080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x800300080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL              , RULL(0x8003080806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x800308080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x800308080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL              , RULL(0x8003100806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x800310080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x800310080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL             , RULL(0x8002200806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL              , RULL(0x8002C00806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C0080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C0080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL             , RULL(0x8002280806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL              , RULL(0x8002C80806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C8080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C8080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL             , RULL(0x8002300806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL             , RULL(0x8002680806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL             , RULL(0x8002700806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL             , RULL(0x8002780806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL              , RULL(0x8000800806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x800080080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x800080080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL              , RULL(0x8000880806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x800088080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x800088080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL              , RULL(0x8000900806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x800090080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x800090080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL              , RULL(0x8000980806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x800098080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x800098080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL                 , RULL(0x8002100806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_FIR_PL                      , RULL(0x8002080806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_FIR_PL                    , RULL(0x800208080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_FIR_PL                    , RULL(0x800208080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL               , RULL(0x8002000806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL              , RULL(0x8003000406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x800300040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x800300040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x800248040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x800248040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL              , RULL(0x8003080406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x800308040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x800308040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x800250040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x800250040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL              , RULL(0x8003100406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x800310040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x800310040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x800258040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x800258040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x800260040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x800260040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL             , RULL(0x8002200406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x800220040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x800220040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL              , RULL(0x8002C00406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C0040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C0040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL             , RULL(0x8002280406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x800228040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x800228040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL              , RULL(0x8002C80406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C8040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C8040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL             , RULL(0x8002300406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x800230040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x800230040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL             , RULL(0x8002680406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x800268040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x800268040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL             , RULL(0x8002700406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x800270040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x800270040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL             , RULL(0x8002780406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x800278040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x800278040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x800008040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x800008040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL              , RULL(0x8000800406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x800080040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x800080040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x800010040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x800010040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL              , RULL(0x8000880406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x800088040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x800088040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x800018040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x800018040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL              , RULL(0x8000900406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x800090040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x800090040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x800020040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x800020040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL              , RULL(0x8000980406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x800098040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x800098040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x800028040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x800028040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x800030040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x800030040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x800038040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x800038040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x800040040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x800040040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL                 , RULL(0x8002100406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL               , RULL(0x800210040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL               , RULL(0x800210040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_FIR_PL                      , RULL(0x8002080406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_FIR_PL                    , RULL(0x800208040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_FIR_PL                    , RULL(0x800208040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL               , RULL(0x8002000406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL             , RULL(0x800200040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL             , RULL(0x800200040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL              , RULL(0x8003000206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x800300020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x800300020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x800248020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x800248020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL              , RULL(0x8003080206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x800308020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x800308020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x800250020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x800250020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL              , RULL(0x8003100206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x800310020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x800310020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x800258020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x800258020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x800260020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x800260020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL             , RULL(0x8002200206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x800220020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x800220020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL              , RULL(0x8002C00206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C0020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C0020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL             , RULL(0x8002280206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x800228020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x800228020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL              , RULL(0x8002C80206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C8020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C8020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL             , RULL(0x8002300206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x800230020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x800230020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL             , RULL(0x8002680206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x800268020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x800268020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL             , RULL(0x8002700206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x800270020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x800270020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL             , RULL(0x8002780206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x800278020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x800278020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x800008020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x800008020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL              , RULL(0x8000800206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x800080020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x800080020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x800010020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x800010020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL              , RULL(0x8000880206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x800088020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x800088020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x800018020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x800018020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL              , RULL(0x8000900206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x800090020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x800090020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x800020020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x800020020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL              , RULL(0x8000980206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x800098020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x800098020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x800028020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x800028020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x800030020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x800030020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x800038020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x800038020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x800040020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x800040020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL                 , RULL(0x8002100206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL               , RULL(0x800210020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL               , RULL(0x800210020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_FIR_PL                      , RULL(0x8002080206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_FIR_PL                    , RULL(0x800208020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_FIR_PL                    , RULL(0x800208020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL               , RULL(0x8002000206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL             , RULL(0x800200020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL             , RULL(0x800200020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL              , RULL(0x8003000506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x800300050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x800300050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x800248050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x800248050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL              , RULL(0x8003080506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x800308050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x800308050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x800250050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x800250050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL              , RULL(0x8003100506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x800310050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x800310050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x800258050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x800258050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x800260050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x800260050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL             , RULL(0x8002200506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x800220050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x800220050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL              , RULL(0x8002C00506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C0050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C0050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL             , RULL(0x8002280506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x800228050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x800228050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL              , RULL(0x8002C80506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C8050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C8050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL             , RULL(0x8002300506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x800230050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x800230050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL             , RULL(0x8002680506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x800268050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x800268050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL             , RULL(0x8002700506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x800270050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x800270050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL             , RULL(0x8002780506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x800278050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x800278050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x800008050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x800008050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL              , RULL(0x8000800506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x800080050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x800080050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x800010050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x800010050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL              , RULL(0x8000880506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x800088050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x800088050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x800018050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x800018050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL              , RULL(0x8000900506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x800090050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x800090050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x800020050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x800020050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL              , RULL(0x8000980506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x800098050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x800098050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x800028050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x800028050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x800030050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x800030050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x800038050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x800038050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x800040050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x800040050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL                 , RULL(0x8002100506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL               , RULL(0x800210050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL               , RULL(0x800210050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_FIR_PL                      , RULL(0x8002080506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_FIR_PL                    , RULL(0x800208050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_FIR_PL                    , RULL(0x800208050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL               , RULL(0x8002000506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL             , RULL(0x800200050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL             , RULL(0x800200050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL              , RULL(0x8003000306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x800300030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x800300030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL              , RULL(0x8003080306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x800308030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x800308030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL              , RULL(0x8003100306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x800310030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x800310030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL             , RULL(0x8002200306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL              , RULL(0x8002C00306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C0030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C0030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL             , RULL(0x8002280306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL              , RULL(0x8002C80306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C8030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C8030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL             , RULL(0x8002300306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL             , RULL(0x8002680306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL             , RULL(0x8002700306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL             , RULL(0x8002780306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL              , RULL(0x8000800306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x800080030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x800080030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL              , RULL(0x8000880306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x800088030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x800088030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL              , RULL(0x8000900306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x800090030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x800090030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL              , RULL(0x8000980306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x800098030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x800098030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL                 , RULL(0x8002100306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_FIR_PL                      , RULL(0x8002080306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_FIR_PL                    , RULL(0x800208030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_FIR_PL                    , RULL(0x800208030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL               , RULL(0x8002000306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL              , RULL(0x8003000006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL            , RULL(0x800300000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL            , RULL(0x800300000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL           , RULL(0x800248000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL           , RULL(0x800248000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL              , RULL(0x8003080006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL            , RULL(0x800308000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL            , RULL(0x800308000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL           , RULL(0x800250000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL           , RULL(0x800250000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL              , RULL(0x8003100006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL            , RULL(0x800310000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL            , RULL(0x800310000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL           , RULL(0x800258000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL           , RULL(0x800258000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL           , RULL(0x800260000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL           , RULL(0x800260000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL             , RULL(0x8002200006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL           , RULL(0x800220000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL           , RULL(0x800220000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL              , RULL(0x8002C00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL            , RULL(0x8002C0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL            , RULL(0x8002C0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL             , RULL(0x8002280006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL           , RULL(0x800228000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL           , RULL(0x800228000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL              , RULL(0x8002C80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL            , RULL(0x8002C8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL            , RULL(0x8002C8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL             , RULL(0x8002300006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL           , RULL(0x800230000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL           , RULL(0x800230000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL             , RULL(0x8002680006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL           , RULL(0x800268000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL           , RULL(0x800268000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL             , RULL(0x8002700006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL           , RULL(0x800270000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL           , RULL(0x800270000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL             , RULL(0x8002780006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL           , RULL(0x800278000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL           , RULL(0x800278000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL           , RULL(0x800008000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL           , RULL(0x800008000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL              , RULL(0x8000800006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL            , RULL(0x800080000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL            , RULL(0x800080000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL           , RULL(0x800010000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL           , RULL(0x800010000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL              , RULL(0x8000880006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL            , RULL(0x800088000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL            , RULL(0x800088000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL           , RULL(0x800018000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL           , RULL(0x800018000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL              , RULL(0x8000900006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL            , RULL(0x800090000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL            , RULL(0x800090000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL           , RULL(0x800020000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL           , RULL(0x800020000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL              , RULL(0x8000980006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL            , RULL(0x800098000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL            , RULL(0x800098000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL           , RULL(0x800028000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL           , RULL(0x800028000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL           , RULL(0x800030000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL           , RULL(0x800030000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL           , RULL(0x800038000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL           , RULL(0x800038000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL           , RULL(0x800040000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL           , RULL(0x800040000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_FIR_MASK_PL                 , RULL(0x8002100006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_FIR_MASK_PL               , RULL(0x800210000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_FIR_MASK_PL               , RULL(0x800210000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_FIR_PL                      , RULL(0x8002080006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_FIR_PL                    , RULL(0x800208000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_FIR_PL                    , RULL(0x800208000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL               , RULL(0x8002000006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL             , RULL(0x800200000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL             , RULL(0x800200000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL              , RULL(0x8003000106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL            , RULL(0x800300010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL            , RULL(0x800300010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL             , RULL(0x8002480106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL           , RULL(0x800248010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL           , RULL(0x800248010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL              , RULL(0x8003080106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL            , RULL(0x800308010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL            , RULL(0x800308010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL             , RULL(0x8002500106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL           , RULL(0x800250010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL           , RULL(0x800250010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL              , RULL(0x8003100106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL            , RULL(0x800310010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL            , RULL(0x800310010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL             , RULL(0x8002580106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL           , RULL(0x800258010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL           , RULL(0x800258010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL             , RULL(0x8002600106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL           , RULL(0x800260010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL           , RULL(0x800260010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002400106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL             , RULL(0x8002200106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL           , RULL(0x800220010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL           , RULL(0x800220010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL              , RULL(0x8002C00106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL            , RULL(0x8002C0010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL            , RULL(0x8002C0010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL             , RULL(0x8002280106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL           , RULL(0x800228010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL           , RULL(0x800228010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL              , RULL(0x8002C80106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL            , RULL(0x8002C8010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL            , RULL(0x8002C8010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL             , RULL(0x8002300106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL           , RULL(0x800230010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL           , RULL(0x800230010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL             , RULL(0x8002680106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL           , RULL(0x800268010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL           , RULL(0x800268010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL             , RULL(0x8002700106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL           , RULL(0x800270010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL           , RULL(0x800270010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL             , RULL(0x8002780106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL           , RULL(0x800278010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL           , RULL(0x800278010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL             , RULL(0x8000080106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL           , RULL(0x800008010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL           , RULL(0x800008010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL              , RULL(0x8000800106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL            , RULL(0x800080010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL            , RULL(0x800080010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL             , RULL(0x8000100106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL           , RULL(0x800010010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL           , RULL(0x800010010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL              , RULL(0x8000880106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL            , RULL(0x800088010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL            , RULL(0x800088010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL             , RULL(0x8000180106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL           , RULL(0x800018010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL           , RULL(0x800018010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL              , RULL(0x8000900106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL            , RULL(0x800090010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL            , RULL(0x800090010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL             , RULL(0x8000200106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL           , RULL(0x800020010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL           , RULL(0x800020010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL              , RULL(0x8000980106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL            , RULL(0x800098010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL            , RULL(0x800098010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL             , RULL(0x8000280106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL           , RULL(0x800028010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL           , RULL(0x800028010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL              , RULL(0x8000A00106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL             , RULL(0x8000300106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL           , RULL(0x800030010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL           , RULL(0x800030010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL              , RULL(0x8000A80106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL             , RULL(0x8000380106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL           , RULL(0x800038010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL           , RULL(0x800038010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL              , RULL(0x8000B00106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL             , RULL(0x8000400106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL           , RULL(0x800040010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL           , RULL(0x800040010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL              , RULL(0x8000B80106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL              , RULL(0x8000C00106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000000106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002180106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_FIR_MASK_PL                 , RULL(0x8002100106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_FIR_MASK_PL               , RULL(0x800210010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_FIR_MASK_PL               , RULL(0x800210010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_FIR_PL                      , RULL(0x8002080106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_FIR_PL                    , RULL(0x800208010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_FIR_PL                    , RULL(0x800208010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL               , RULL(0x8002000106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL             , RULL(0x800200010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL             , RULL(0x800200010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL10_EO_PG                            , RULL(0x8009200006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL10_EO_PG                          , RULL(0x800920000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL10_EO_PG                          , RULL(0x800920000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL11_EO_PG                            , RULL(0x8009280006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL11_EO_PG                          , RULL(0x800928000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL11_EO_PG                          , RULL(0x800928000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL12_EO_PG                            , RULL(0x8009300006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL12_EO_PG                          , RULL(0x800930000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL12_EO_PG                          , RULL(0x800930000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL13_EO_PG                            , RULL(0x8009380006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL13_EO_PG                          , RULL(0x800938000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL13_EO_PG                          , RULL(0x800938000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL14_EO_PG                            , RULL(0x8009400006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL14_EO_PG                          , RULL(0x800940000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL14_EO_PG                          , RULL(0x800940000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL15_EO_PG                            , RULL(0x8009480006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL15_EO_PG                          , RULL(0x800948000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL15_EO_PG                          , RULL(0x800948000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL1_EO_PG                             , RULL(0x8008D80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL1_EO_PG                           , RULL(0x8008D8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL1_EO_PG                           , RULL(0x8008D8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL1_E_PG                              , RULL(0x8009F00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL1_E_PG                            , RULL(0x8009F0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL1_E_PG                            , RULL(0x8009F0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL2_EO_PG                             , RULL(0x8008E00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL2_EO_PG                           , RULL(0x8008E0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL2_EO_PG                           , RULL(0x8008E0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL3_EO_PG                             , RULL(0x8008E80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL3_EO_PG                           , RULL(0x8008E8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL3_EO_PG                           , RULL(0x8008E8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL4_EO_PG                             , RULL(0x8008F00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL4_EO_PG                           , RULL(0x8008F0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL4_EO_PG                           , RULL(0x8008F0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL4_E_PG                              , RULL(0x8009F80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL4_E_PG                            , RULL(0x8009F8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL4_E_PG                            , RULL(0x8009F8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL5_EO_PG                             , RULL(0x8008F80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL5_EO_PG                           , RULL(0x8008F8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL5_EO_PG                           , RULL(0x8008F8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL6_EO_PG                             , RULL(0x8009000006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL6_EO_PG                           , RULL(0x800900000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL6_EO_PG                           , RULL(0x800900000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL8_EO_PG                             , RULL(0x8009100006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL8_EO_PG                           , RULL(0x800910000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL8_EO_PG                           , RULL(0x800910000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTL9_EO_PG                             , RULL(0x8009180006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTL9_EO_PG                           , RULL(0x800918000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTL9_EO_PG                           , RULL(0x800918000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTLX10_E_PG                            , RULL(0x800A280006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG                          , RULL(0x800A28000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTLX10_E_PG                          , RULL(0x800A28000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTLX11_E_PG                            , RULL(0x800A300006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTLX11_E_PG                          , RULL(0x800A30000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTLX11_E_PG                          , RULL(0x800A30000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTLX5_E_PG                             , RULL(0x800A000006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTLX5_E_PG                           , RULL(0x800A00000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTLX5_E_PG                           , RULL(0x800A00000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_CNTLX7_EO_PG                            , RULL(0x8009080006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_CNTLX7_EO_PG                          , RULL(0x800908000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_CNTLX7_EO_PG                          , RULL(0x800908000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE10_EO_PG                            , RULL(0x8008580006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE10_EO_PG                          , RULL(0x800858000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE10_EO_PG                          , RULL(0x800858000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE10_E_PG                             , RULL(0x8009D80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE10_E_PG                           , RULL(0x8009D8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE10_E_PG                           , RULL(0x8009D8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE11_EO_PG                            , RULL(0x8008600006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE11_EO_PG                          , RULL(0x800860000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE11_EO_PG                          , RULL(0x800860000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE11_E_PG                             , RULL(0x8009E00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE11_E_PG                           , RULL(0x8009E0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE11_E_PG                           , RULL(0x8009E0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE12_EO_PG                            , RULL(0x8008680006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE12_EO_PG                          , RULL(0x800868000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE12_EO_PG                          , RULL(0x800868000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE12_E_PG                             , RULL(0x8009E80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE12_E_PG                           , RULL(0x8009E8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE12_E_PG                           , RULL(0x8009E8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE13_EO_PG                            , RULL(0x8008700006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE13_EO_PG                          , RULL(0x800870000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE13_EO_PG                          , RULL(0x800870000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE14_EO_PG                            , RULL(0x8008780006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE14_EO_PG                          , RULL(0x800878000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE14_EO_PG                          , RULL(0x800878000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE15_EO_PG                            , RULL(0x8008800006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE15_EO_PG                          , RULL(0x800880000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE15_EO_PG                          , RULL(0x800880000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE16_EO_PG                            , RULL(0x8008880006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE16_EO_PG                          , RULL(0x800888000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE16_EO_PG                          , RULL(0x800888000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE17_EO_PG                            , RULL(0x8008900006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE17_EO_PG                          , RULL(0x800890000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE17_EO_PG                          , RULL(0x800890000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE18_EO_PG                            , RULL(0x8008980006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE18_EO_PG                          , RULL(0x800898000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE18_EO_PG                          , RULL(0x800898000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE19_EO_PG                            , RULL(0x8008A00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE19_EO_PG                          , RULL(0x8008A0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE19_EO_PG                          , RULL(0x8008A0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE1_EO_PG                             , RULL(0x8008100006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE1_EO_PG                           , RULL(0x800810000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE1_EO_PG                           , RULL(0x800810000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE1_E_PG                              , RULL(0x8009900006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE1_E_PG                            , RULL(0x800990000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE1_E_PG                            , RULL(0x800990000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE20_EO_PG                            , RULL(0x8008A80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE20_EO_PG                          , RULL(0x8008A8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE20_EO_PG                          , RULL(0x8008A8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE21_EO_PG                            , RULL(0x8008B00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE21_EO_PG                          , RULL(0x8008B0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE21_EO_PG                          , RULL(0x8008B0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE22_EO_PG                            , RULL(0x8008B80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE22_EO_PG                          , RULL(0x8008B8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE22_EO_PG                          , RULL(0x8008B8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE23_EO_PG                            , RULL(0x8008C00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE23_EO_PG                          , RULL(0x8008C0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE23_EO_PG                          , RULL(0x8008C0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE24_EO_PG                            , RULL(0x8008C80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE24_EO_PG                          , RULL(0x8008C8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE24_EO_PG                          , RULL(0x8008C8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE26_EO_PG                            , RULL(0x8009680006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE26_EO_PG                          , RULL(0x800968000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE26_EO_PG                          , RULL(0x800968000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE27_EO_PG                            , RULL(0x8009700006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE27_EO_PG                          , RULL(0x800970000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE27_EO_PG                          , RULL(0x800970000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE28_EO_PG                            , RULL(0x8009780006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE28_EO_PG                          , RULL(0x800978000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE28_EO_PG                          , RULL(0x800978000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE29_EO_PG                            , RULL(0x8008D00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE29_EO_PG                          , RULL(0x8008D0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE29_EO_PG                          , RULL(0x8008D0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE2_EO_PG                             , RULL(0x8008180006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE2_EO_PG                           , RULL(0x800818000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE2_EO_PG                           , RULL(0x800818000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE2_E_PG                              , RULL(0x8009980006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE2_E_PG                            , RULL(0x800998000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE2_E_PG                            , RULL(0x800998000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE3_EO_PG                             , RULL(0x8008200006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE3_EO_PG                           , RULL(0x800820000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE3_EO_PG                           , RULL(0x800820000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE3_E_PG                              , RULL(0x8009A00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE3_E_PG                            , RULL(0x8009A0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE3_E_PG                            , RULL(0x8009A0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE4_EO_PG                             , RULL(0x8008280006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE4_EO_PG                           , RULL(0x800828000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE4_EO_PG                           , RULL(0x800828000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE4_E_PG                              , RULL(0x8009A80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE4_E_PG                            , RULL(0x8009A8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE4_E_PG                            , RULL(0x8009A8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE5_EO_PG                             , RULL(0x8008300006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE5_EO_PG                           , RULL(0x800830000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE5_EO_PG                           , RULL(0x800830000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE5_E_PG                              , RULL(0x8009B00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE5_E_PG                            , RULL(0x8009B0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE5_E_PG                            , RULL(0x8009B0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE6_EO_PG                             , RULL(0x8008380006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE6_EO_PG                           , RULL(0x800838000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE6_EO_PG                           , RULL(0x800838000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE6_E_PG                              , RULL(0x8009B80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE6_E_PG                            , RULL(0x8009B8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE6_E_PG                            , RULL(0x8009B8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE7_EO_PG                             , RULL(0x8008400006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE7_EO_PG                           , RULL(0x800840000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE7_EO_PG                           , RULL(0x800840000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE7_E_PG                              , RULL(0x8009C00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE7_E_PG                            , RULL(0x8009C0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE7_E_PG                            , RULL(0x8009C0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE8_EO_PG                             , RULL(0x8008480006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE8_EO_PG                           , RULL(0x800848000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE8_EO_PG                           , RULL(0x800848000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE8_E_PG                              , RULL(0x8009C80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE8_E_PG                            , RULL(0x8009C8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE8_E_PG                            , RULL(0x8009C8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE9_EO_PG                             , RULL(0x8008500006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE9_EO_PG                           , RULL(0x800850000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE9_EO_PG                           , RULL(0x800850000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_MODE9_E_PG                              , RULL(0x8009D00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_MODE9_E_PG                            , RULL(0x8009D0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_MODE9_E_PG                            , RULL(0x8009D0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_STAT1_EO_PG                             , RULL(0x8009500006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_STAT1_EO_PG                           , RULL(0x800950000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_STAT1_EO_PG                           , RULL(0x800950000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_STAT1_E_PG                              , RULL(0x800A380006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_STAT1_E_PG                            , RULL(0x800A38000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_STAT1_E_PG                            , RULL(0x800A38000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_STAT2_EO_PG                             , RULL(0x8009580006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_STAT2_EO_PG                           , RULL(0x800958000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_STAT2_EO_PG                           , RULL(0x800958000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_STAT2_E_PG                              , RULL(0x800A400006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_STAT2_E_PG                            , RULL(0x800A40000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_STAT2_E_PG                            , RULL(0x800A40000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_STAT3_EO_PG                             , RULL(0x8009600006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_STAT3_EO_PG                           , RULL(0x800960000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_STAT3_EO_PG                           , RULL(0x800960000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_STAT4_E_PG                              , RULL(0x800A500006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_STAT4_E_PG                            , RULL(0x800A50000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_STAT4_E_PG                            , RULL(0x800A50000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_STAT5_E_PG                              , RULL(0x800A580006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_STAT5_E_PG                            , RULL(0x800A58000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_STAT5_E_PG                            , RULL(0x800A58000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_STAT6_E_PG                              , RULL(0x800A600006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_STAT6_E_PG                            , RULL(0x800A60000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_STAT6_E_PG                            , RULL(0x800A60000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_CTL_STATX8_E_PG                             , RULL(0x800A680006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_CTL_STATX8_E_PG                           , RULL(0x800A68000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_CTL_STATX8_E_PG                           , RULL(0x800A68000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_CNTL1_E_PG                           , RULL(0x800BE80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_CNTL1_E_PG                         , RULL(0x800BE8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_CNTL1_E_PG                         , RULL(0x800BE8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_CNTLX1_EO_PG                         , RULL(0x800B880006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_CNTLX1_EO_PG                       , RULL(0x800B88000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_CNTLX1_EO_PG                       , RULL(0x800B88000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_SPARE_MODE_PG                        , RULL(0x800B800006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_SPARE_MODE_PG                      , RULL(0x800B80000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_SPARE_MODE_PG                      , RULL(0x800B80000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_STAT10_EO_PG                         , RULL(0x800BD80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_STAT10_EO_PG                       , RULL(0x800BD8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_STAT10_EO_PG                       , RULL(0x800BD8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_STAT11_EO_PG                         , RULL(0x800BE00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_STAT11_EO_PG                       , RULL(0x800BE0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_STAT11_EO_PG                       , RULL(0x800BE0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_STAT12_EO_PG                         , RULL(0x800BF00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_STAT12_EO_PG                       , RULL(0x800BF0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_STAT12_EO_PG                       , RULL(0x800BF0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_STAT13_E_PG                          , RULL(0x800BF80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_STAT13_E_PG                        , RULL(0x800BF8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_STAT13_E_PG                        , RULL(0x800BF8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_STAT1_EO_PG                          , RULL(0x800B900006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_STAT1_EO_PG                        , RULL(0x800B90000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_STAT1_EO_PG                        , RULL(0x800B90000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_STAT2_EO_PG                          , RULL(0x800B980006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_STAT2_EO_PG                        , RULL(0x800B98000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_STAT2_EO_PG                        , RULL(0x800B98000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_STAT3_EO_PG                          , RULL(0x800BA00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_STAT3_EO_PG                        , RULL(0x800BA0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_STAT3_EO_PG                        , RULL(0x800BA0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_STAT4_EO_PG                          , RULL(0x800BA80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_STAT4_EO_PG                        , RULL(0x800BA8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_STAT4_EO_PG                        , RULL(0x800BA8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_STAT5_EO_PG                          , RULL(0x800BB00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_STAT5_EO_PG                        , RULL(0x800BB0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_STAT5_EO_PG                        , RULL(0x800BB0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_STAT6_EO_PG                          , RULL(0x800BB80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_STAT6_EO_PG                        , RULL(0x800BB8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_STAT6_EO_PG                        , RULL(0x800BB8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_STAT7_EO_PG                          , RULL(0x800BC00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_STAT7_EO_PG                        , RULL(0x800BC0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_STAT7_EO_PG                        , RULL(0x800BC0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_STAT8_EO_PG                          , RULL(0x800BC80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_STAT8_EO_PG                        , RULL(0x800BC8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_STAT8_EO_PG                        , RULL(0x800BC8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_DATASM_STAT9_EO_PG                          , RULL(0x800BD00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_DATASM_STAT9_EO_PG                        , RULL(0x800BD0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_DATASM_STAT9_EO_PG                        , RULL(0x800BD0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_FIR1_ERROR_INJECT_PG                        , RULL(0x800A980006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_FIR1_ERROR_INJECT_PG                      , RULL(0x800A98000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_FIR1_ERROR_INJECT_PG                      , RULL(0x800A98000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_FIR1_MASK_PG                                , RULL(0x800A900006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_FIR1_MASK_PG                              , RULL(0x800A90000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_FIR1_MASK_PG                              , RULL(0x800A90000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_FIR1_PG                                     , RULL(0x800A880006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_FIR1_PG                                   , RULL(0x800A88000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_FIR1_PG                                   , RULL(0x800A88000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_FIR2_ERROR_INJECT_PG                        , RULL(0x800B100006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_FIR2_ERROR_INJECT_PG                      , RULL(0x800B10000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_FIR2_ERROR_INJECT_PG                      , RULL(0x800B10000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_FIR2_MASK_PG                                , RULL(0x800B080006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_FIR2_MASK_PG                              , RULL(0x800B08000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_FIR2_MASK_PG                              , RULL(0x800B08000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_FIR2_PG                                     , RULL(0x800B000006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_FIR2_PG                                   , RULL(0x800B00000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_FIR2_PG                                   , RULL(0x800B00000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_FIR_TRAINING_MASK_PG                        , RULL(0x800AA80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_FIR_TRAINING_MASK_PG                      , RULL(0x800AA8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_FIR_TRAINING_MASK_PG                      , RULL(0x800AA8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_FIR_TRAINING_PG                             , RULL(0x800AA00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_FIR_TRAINING_PG                           , RULL(0x800AA0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_FIR_TRAINING_PG                           , RULL(0x800AA0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_CNTL2_EO_PG                           , RULL(0x800AE00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_CNTL2_EO_PG                         , RULL(0x800AE0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_CNTL2_EO_PG                         , RULL(0x800AE0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_CNTL3_EO_PG                           , RULL(0x800AE80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_CNTL3_EO_PG                         , RULL(0x800AE8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_CNTL3_EO_PG                         , RULL(0x800AE8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_CNTLX1_EO_PG                          , RULL(0x800AB00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_CNTLX1_EO_PG                        , RULL(0x800AB0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_CNTLX1_EO_PG                        , RULL(0x800AB0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_SPARE_MODE_PG                         , RULL(0x800A800006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_SPARE_MODE_PG                       , RULL(0x800A80000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_SPARE_MODE_PG                       , RULL(0x800A80000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_STAT10_E_PG                           , RULL(0x800B600006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_STAT10_E_PG                         , RULL(0x800B60000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_STAT10_E_PG                         , RULL(0x800B60000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_STAT1_EO_PG                           , RULL(0x800AB80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_STAT1_EO_PG                         , RULL(0x800AB8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_STAT1_EO_PG                         , RULL(0x800AB8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_STAT1_E_PG                            , RULL(0x800B180006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_STAT1_E_PG                          , RULL(0x800B18000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_STAT1_E_PG                          , RULL(0x800B18000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_STAT2_EO_PG                           , RULL(0x800AC00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_STAT2_EO_PG                         , RULL(0x800AC0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_STAT2_EO_PG                         , RULL(0x800AC0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_STAT2_E_PG                            , RULL(0x800B200006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_STAT2_E_PG                          , RULL(0x800B20000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_STAT2_E_PG                          , RULL(0x800B20000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_STAT3_EO_PG                           , RULL(0x800AC80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_STAT3_EO_PG                         , RULL(0x800AC8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_STAT3_EO_PG                         , RULL(0x800AC8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_STAT3_E_PG                            , RULL(0x800B280006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_STAT3_E_PG                          , RULL(0x800B28000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_STAT3_E_PG                          , RULL(0x800B28000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_STAT4_EO_PG                           , RULL(0x800AD00006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_STAT4_EO_PG                         , RULL(0x800AD0000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_STAT4_EO_PG                         , RULL(0x800AD0000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_STAT4_E_PG                            , RULL(0x800B300006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_STAT4_E_PG                          , RULL(0x800B30000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_STAT4_E_PG                          , RULL(0x800B30000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_STAT5_EO_PG                           , RULL(0x800AD80006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_STAT5_EO_PG                         , RULL(0x800AD8000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_STAT5_EO_PG                         , RULL(0x800AD8000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_STAT7_E_PG                            , RULL(0x800B480006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_STAT7_E_PG                          , RULL(0x800B48000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_STAT7_E_PG                          , RULL(0x800B48000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_STAT8_E_PG                            , RULL(0x800B500006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_STAT8_E_PG                          , RULL(0x800B50000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_STAT8_E_PG                          , RULL(0x800B50000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_GLBSM_STAT9_E_PG                            , RULL(0x800B580006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_GLBSM_STAT9_E_PG                          , RULL(0x800B58000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_GLBSM_STAT9_E_PG                          , RULL(0x800B58000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_ID1_PG                                      , RULL(0x8008080006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_ID1_PG                                    , RULL(0x800808000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_ID1_PG                                    , RULL(0x800808000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_ID2_PG                                      , RULL(0x8009800006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_ID2_PG                                    , RULL(0x800980000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_ID2_PG                                    , RULL(0x800980000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_RX_SPARE_MODE_PG                               , RULL(0x8008000006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_RX_SPARE_MODE_PG                             , RULL(0x800800000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_RX_SPARE_MODE_PG                             , RULL(0x800800000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE0_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE0_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE0_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE0_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE0_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE0_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE0_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE0_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003800606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE10_RX_WORK_STAT1_EO_PL                    , RULL(0x8003880606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL                  , RULL(0x800388060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE10_RX_WORK_STAT1_EO_PL                  , RULL(0x800388060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE10_RX_WORK_STAT2_EO_PL                    , RULL(0x8003900606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE10_RX_WORK_STAT2_EO_PL                  , RULL(0x800390060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE10_RX_WORK_STAT2_EO_PL                  , RULL(0x800390060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE10_RX_WORK_STAT3_EO_PL                    , RULL(0x8003980606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE10_RX_WORK_STAT3_EO_PL                  , RULL(0x800398060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE10_RX_WORK_STAT3_EO_PL                  , RULL(0x800398060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003800806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE11_RX_WORK_STAT1_EO_PL                    , RULL(0x8003880806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL                  , RULL(0x800388080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE11_RX_WORK_STAT1_EO_PL                  , RULL(0x800388080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE11_RX_WORK_STAT2_EO_PL                    , RULL(0x8003900806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE11_RX_WORK_STAT2_EO_PL                  , RULL(0x800390080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE11_RX_WORK_STAT2_EO_PL                  , RULL(0x800390080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE11_RX_WORK_STAT3_EO_PL                    , RULL(0x8003980806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE11_RX_WORK_STAT3_EO_PL                  , RULL(0x800398080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE11_RX_WORK_STAT3_EO_PL                  , RULL(0x800398080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003800406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE12_RX_WORK_STAT1_EO_PL                    , RULL(0x8003880406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL                  , RULL(0x800388040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE12_RX_WORK_STAT1_EO_PL                  , RULL(0x800388040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE12_RX_WORK_STAT2_EO_PL                    , RULL(0x8003900406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE12_RX_WORK_STAT2_EO_PL                  , RULL(0x800390040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE12_RX_WORK_STAT2_EO_PL                  , RULL(0x800390040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE12_RX_WORK_STAT3_EO_PL                    , RULL(0x8003980406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE12_RX_WORK_STAT3_EO_PL                  , RULL(0x800398040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE12_RX_WORK_STAT3_EO_PL                  , RULL(0x800398040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003800206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE13_RX_WORK_STAT1_EO_PL                    , RULL(0x8003880206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL                  , RULL(0x800388020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE13_RX_WORK_STAT1_EO_PL                  , RULL(0x800388020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE13_RX_WORK_STAT2_EO_PL                    , RULL(0x8003900206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE13_RX_WORK_STAT2_EO_PL                  , RULL(0x800390020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE13_RX_WORK_STAT2_EO_PL                  , RULL(0x800390020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE13_RX_WORK_STAT3_EO_PL                    , RULL(0x8003980206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE13_RX_WORK_STAT3_EO_PL                  , RULL(0x800398020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE13_RX_WORK_STAT3_EO_PL                  , RULL(0x800398020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003800506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE14_RX_WORK_STAT1_EO_PL                    , RULL(0x8003880506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL                  , RULL(0x800388050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE14_RX_WORK_STAT1_EO_PL                  , RULL(0x800388050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE14_RX_WORK_STAT2_EO_PL                    , RULL(0x8003900506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE14_RX_WORK_STAT2_EO_PL                  , RULL(0x800390050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE14_RX_WORK_STAT2_EO_PL                  , RULL(0x800390050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE14_RX_WORK_STAT3_EO_PL                    , RULL(0x8003980506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE14_RX_WORK_STAT3_EO_PL                  , RULL(0x800398050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE14_RX_WORK_STAT3_EO_PL                  , RULL(0x800398050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003800306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE15_RX_WORK_STAT1_EO_PL                    , RULL(0x8003880306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL                  , RULL(0x800388030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE15_RX_WORK_STAT1_EO_PL                  , RULL(0x800388030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE15_RX_WORK_STAT2_EO_PL                    , RULL(0x8003900306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE15_RX_WORK_STAT2_EO_PL                  , RULL(0x800390030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE15_RX_WORK_STAT2_EO_PL                  , RULL(0x800390030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE15_RX_WORK_STAT3_EO_PL                    , RULL(0x8003980306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE15_RX_WORK_STAT3_EO_PL                  , RULL(0x800398030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE15_RX_WORK_STAT3_EO_PL                  , RULL(0x800398030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003800006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE16_RX_WORK_STAT1_EO_PL                    , RULL(0x8003880006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL                  , RULL(0x800388000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE16_RX_WORK_STAT1_EO_PL                  , RULL(0x800388000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE16_RX_WORK_STAT2_EO_PL                    , RULL(0x8003900006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE16_RX_WORK_STAT2_EO_PL                  , RULL(0x800390000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE16_RX_WORK_STAT2_EO_PL                  , RULL(0x800390000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE16_RX_WORK_STAT3_EO_PL                    , RULL(0x8003980006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE16_RX_WORK_STAT3_EO_PL                  , RULL(0x800398000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE16_RX_WORK_STAT3_EO_PL                  , RULL(0x800398000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003800106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE17_RX_WORK_STAT1_EO_PL                    , RULL(0x8003880106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL                  , RULL(0x800388010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE17_RX_WORK_STAT1_EO_PL                  , RULL(0x800388010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE17_RX_WORK_STAT2_EO_PL                    , RULL(0x8003900106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE17_RX_WORK_STAT2_EO_PL                  , RULL(0x800390010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE17_RX_WORK_STAT2_EO_PL                  , RULL(0x800390010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE17_RX_WORK_STAT3_EO_PL                    , RULL(0x8003980106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE17_RX_WORK_STAT3_EO_PL                  , RULL(0x800398010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE17_RX_WORK_STAT3_EO_PL                  , RULL(0x800398010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003801206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380120601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380120601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE18_RX_WORK_STAT1_EO_PL                    , RULL(0x8003881206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL                  , RULL(0x800388120601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE18_RX_WORK_STAT1_EO_PL                  , RULL(0x800388120601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE18_RX_WORK_STAT2_EO_PL                    , RULL(0x8003901206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE18_RX_WORK_STAT2_EO_PL                  , RULL(0x800390120601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE18_RX_WORK_STAT2_EO_PL                  , RULL(0x800390120601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE18_RX_WORK_STAT3_EO_PL                    , RULL(0x8003981206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE18_RX_WORK_STAT3_EO_PL                  , RULL(0x800398120601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE18_RX_WORK_STAT3_EO_PL                  , RULL(0x800398120601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003801306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380130601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380130601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE19_RX_WORK_STAT1_EO_PL                    , RULL(0x8003881306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL                  , RULL(0x800388130601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE19_RX_WORK_STAT1_EO_PL                  , RULL(0x800388130601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE19_RX_WORK_STAT2_EO_PL                    , RULL(0x8003901306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE19_RX_WORK_STAT2_EO_PL                  , RULL(0x800390130601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE19_RX_WORK_STAT2_EO_PL                  , RULL(0x800390130601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE19_RX_WORK_STAT3_EO_PL                    , RULL(0x8003981306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE19_RX_WORK_STAT3_EO_PL                  , RULL(0x800398130601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE19_RX_WORK_STAT3_EO_PL                  , RULL(0x800398130601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE1_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE1_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE1_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE1_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE1_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE1_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE1_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE1_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003801406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380140601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380140601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE20_RX_WORK_STAT1_EO_PL                    , RULL(0x8003881406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL                  , RULL(0x800388140601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE20_RX_WORK_STAT1_EO_PL                  , RULL(0x800388140601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE20_RX_WORK_STAT2_EO_PL                    , RULL(0x8003901406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE20_RX_WORK_STAT2_EO_PL                  , RULL(0x800390140601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE20_RX_WORK_STAT2_EO_PL                  , RULL(0x800390140601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE20_RX_WORK_STAT3_EO_PL                    , RULL(0x8003981406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE20_RX_WORK_STAT3_EO_PL                  , RULL(0x800398140601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE20_RX_WORK_STAT3_EO_PL                  , RULL(0x800398140601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003801506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380150601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380150601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE21_RX_WORK_STAT1_EO_PL                    , RULL(0x8003881506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL                  , RULL(0x800388150601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE21_RX_WORK_STAT1_EO_PL                  , RULL(0x800388150601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE21_RX_WORK_STAT2_EO_PL                    , RULL(0x8003901506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE21_RX_WORK_STAT2_EO_PL                  , RULL(0x800390150601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE21_RX_WORK_STAT2_EO_PL                  , RULL(0x800390150601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE21_RX_WORK_STAT3_EO_PL                    , RULL(0x8003981506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE21_RX_WORK_STAT3_EO_PL                  , RULL(0x800398150601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE21_RX_WORK_STAT3_EO_PL                  , RULL(0x800398150601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003801606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380160601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380160601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE22_RX_WORK_STAT1_EO_PL                    , RULL(0x8003881606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL                  , RULL(0x800388160601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE22_RX_WORK_STAT1_EO_PL                  , RULL(0x800388160601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE22_RX_WORK_STAT2_EO_PL                    , RULL(0x8003901606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE22_RX_WORK_STAT2_EO_PL                  , RULL(0x800390160601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE22_RX_WORK_STAT2_EO_PL                  , RULL(0x800390160601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE22_RX_WORK_STAT3_EO_PL                    , RULL(0x8003981606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE22_RX_WORK_STAT3_EO_PL                  , RULL(0x800398160601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE22_RX_WORK_STAT3_EO_PL                  , RULL(0x800398160601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003801706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380170601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380170601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE23_RX_WORK_STAT1_EO_PL                    , RULL(0x8003881706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL                  , RULL(0x800388170601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE23_RX_WORK_STAT1_EO_PL                  , RULL(0x800388170601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE23_RX_WORK_STAT2_EO_PL                    , RULL(0x8003901706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE23_RX_WORK_STAT2_EO_PL                  , RULL(0x800390170601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE23_RX_WORK_STAT2_EO_PL                  , RULL(0x800390170601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE23_RX_WORK_STAT3_EO_PL                    , RULL(0x8003981706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE23_RX_WORK_STAT3_EO_PL                  , RULL(0x800398170601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE23_RX_WORK_STAT3_EO_PL                  , RULL(0x800398170601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE2_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE2_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE2_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE2_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE2_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE2_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE2_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE2_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003801006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE3_RX_WORK_STAT1_EO_PL                     , RULL(0x8003881006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL                   , RULL(0x800388100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE3_RX_WORK_STAT1_EO_PL                   , RULL(0x800388100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE3_RX_WORK_STAT2_EO_PL                     , RULL(0x8003901006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE3_RX_WORK_STAT2_EO_PL                   , RULL(0x800390100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE3_RX_WORK_STAT2_EO_PL                   , RULL(0x800390100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE3_RX_WORK_STAT3_EO_PL                     , RULL(0x8003981006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE3_RX_WORK_STAT3_EO_PL                   , RULL(0x800398100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE3_RX_WORK_STAT3_EO_PL                   , RULL(0x800398100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE4_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE4_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE4_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE4_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE4_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE4_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE4_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE4_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE5_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL                   , RULL(0x800388090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE5_RX_WORK_STAT1_EO_PL                   , RULL(0x800388090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE5_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE5_RX_WORK_STAT2_EO_PL                   , RULL(0x800390090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE5_RX_WORK_STAT2_EO_PL                   , RULL(0x800390090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE5_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE5_RX_WORK_STAT3_EO_PL                   , RULL(0x800398090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE5_RX_WORK_STAT3_EO_PL                   , RULL(0x800398090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE6_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE6_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE6_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE6_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE6_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE6_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE6_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE6_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003800A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE7_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE7_RX_WORK_STAT1_EO_PL                   , RULL(0x8003880A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE7_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE7_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE7_RX_WORK_STAT2_EO_PL                   , RULL(0x8003900A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE7_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE7_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE7_RX_WORK_STAT3_EO_PL                   , RULL(0x8003980A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003800706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE8_RX_WORK_STAT1_EO_PL                     , RULL(0x8003880706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL                   , RULL(0x800388070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE8_RX_WORK_STAT1_EO_PL                   , RULL(0x800388070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE8_RX_WORK_STAT2_EO_PL                     , RULL(0x8003900706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE8_RX_WORK_STAT2_EO_PL                   , RULL(0x800390070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE8_RX_WORK_STAT2_EO_PL                   , RULL(0x800390070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE8_RX_WORK_STAT3_EO_PL                     , RULL(0x8003980706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE8_RX_WORK_STAT3_EO_PL                   , RULL(0x800398070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE8_RX_WORK_STAT3_EO_PL                   , RULL(0x800398070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003801106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE9_RX_WORK_STAT1_EO_PL                     , RULL(0x8003881106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL                   , RULL(0x800388110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE9_RX_WORK_STAT1_EO_PL                   , RULL(0x800388110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE9_RX_WORK_STAT2_EO_PL                     , RULL(0x8003901106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE9_RX_WORK_STAT2_EO_PL                   , RULL(0x800390110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE9_RX_WORK_STAT2_EO_PL                   , RULL(0x800390110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX0_SLICE9_RX_WORK_STAT3_EO_PL                     , RULL(0x8003981106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX0_SLICE9_RX_WORK_STAT3_EO_PL                   , RULL(0x800398110601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX0_SLICE9_RX_WORK_STAT3_EO_PL                   , RULL(0x800398110601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL              , RULL(0x8003002106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x800300210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x800300210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x800248210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x800248210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL              , RULL(0x8003082106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x800308210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x800308210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x800250210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x800250210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL              , RULL(0x8003102106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x800310210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x800310210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x800258210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x800258210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x800260210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x800260210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL             , RULL(0x8002202106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x800220210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x800220210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL              , RULL(0x8002C02106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C0210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C0210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL             , RULL(0x8002282106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x800228210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x800228210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL              , RULL(0x8002C82106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C8210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C8210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL             , RULL(0x8002302106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x800230210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x800230210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL             , RULL(0x8002682106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x800268210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x800268210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL             , RULL(0x8002702106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x800270210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x800270210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL             , RULL(0x8002782106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x800278210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x800278210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x800008210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x800008210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL              , RULL(0x8000802106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x800080210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x800080210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x800010210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x800010210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL              , RULL(0x8000882106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x800088210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x800088210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x800018210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x800018210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL              , RULL(0x8000902106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x800090210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x800090210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x800020210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x800020210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL              , RULL(0x8000982106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x800098210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x800098210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x800028210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x800028210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x800030210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x800030210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x800038210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x800038210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x800040210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x800040210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_FIR_MASK_PL                 , RULL(0x8002102106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_FIR_MASK_PL               , RULL(0x800210210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_FIR_MASK_PL               , RULL(0x800210210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_FIR_PL                      , RULL(0x8002082106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_FIR_PL                    , RULL(0x800208210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_FIR_PL                    , RULL(0x800208210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL               , RULL(0x8002002106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL             , RULL(0x800200210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL             , RULL(0x800200210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL              , RULL(0x8003002306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x800300230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x800300230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x800248230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x800248230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL              , RULL(0x8003082306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x800308230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x800308230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x800250230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x800250230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL              , RULL(0x8003102306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x800310230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x800310230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x800258230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x800258230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x800260230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x800260230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL             , RULL(0x8002202306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x800220230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x800220230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL              , RULL(0x8002C02306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C0230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C0230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL             , RULL(0x8002282306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x800228230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x800228230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL              , RULL(0x8002C82306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C8230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C8230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL             , RULL(0x8002302306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x800230230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x800230230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL             , RULL(0x8002682306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x800268230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x800268230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL             , RULL(0x8002702306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x800270230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x800270230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL             , RULL(0x8002782306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x800278230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x800278230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x800008230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x800008230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL              , RULL(0x8000802306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x800080230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x800080230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x800010230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x800010230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL              , RULL(0x8000882306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x800088230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x800088230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x800018230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x800018230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL              , RULL(0x8000902306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x800090230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x800090230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x800020230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x800020230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL              , RULL(0x8000982306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x800098230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x800098230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x800028230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x800028230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x800030230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x800030230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x800038230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x800038230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x800040230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x800040230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_FIR_MASK_PL                 , RULL(0x8002102306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_FIR_MASK_PL               , RULL(0x800210230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_FIR_MASK_PL               , RULL(0x800210230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_FIR_PL                      , RULL(0x8002082306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_FIR_PL                    , RULL(0x800208230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_FIR_PL                    , RULL(0x800208230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL               , RULL(0x8002002306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL             , RULL(0x800200230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL             , RULL(0x800200230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL              , RULL(0x8003002006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x800300200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x800300200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x800248200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x800248200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL              , RULL(0x8003082006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x800308200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x800308200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x800250200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x800250200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL              , RULL(0x8003102006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x800310200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x800310200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x800258200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x800258200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x800260200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x800260200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL             , RULL(0x8002202006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x800220200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x800220200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL              , RULL(0x8002C02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL             , RULL(0x8002282006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x800228200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x800228200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL              , RULL(0x8002C82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL             , RULL(0x8002302006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x800230200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x800230200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL             , RULL(0x8002682006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x800268200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x800268200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL             , RULL(0x8002702006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x800270200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x800270200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL             , RULL(0x8002782006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x800278200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x800278200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x800008200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x800008200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL              , RULL(0x8000802006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x800080200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x800080200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x800010200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x800010200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL              , RULL(0x8000882006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x800088200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x800088200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x800018200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x800018200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL              , RULL(0x8000902006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x800090200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x800090200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x800020200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x800020200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL              , RULL(0x8000982006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x800098200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x800098200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x800028200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x800028200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x800030200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x800030200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x800038200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x800038200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x800040200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x800040200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_FIR_MASK_PL                 , RULL(0x8002102006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_FIR_MASK_PL               , RULL(0x800210200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_FIR_MASK_PL               , RULL(0x800210200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_FIR_PL                      , RULL(0x8002082006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_FIR_PL                    , RULL(0x800208200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_FIR_PL                    , RULL(0x800208200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL               , RULL(0x8002002006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL             , RULL(0x800200200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL             , RULL(0x800200200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL              , RULL(0x8003002206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x800300220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x800300220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL              , RULL(0x8003082206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x800308220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x800308220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL              , RULL(0x8003102206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x800310220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x800310220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL             , RULL(0x8002202206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL              , RULL(0x8002C02206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C0220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C0220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL             , RULL(0x8002282206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL              , RULL(0x8002C82206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C8220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C8220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL             , RULL(0x8002302206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL             , RULL(0x8002682206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL             , RULL(0x8002702206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL             , RULL(0x8002782206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL              , RULL(0x8000802206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x800080220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x800080220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL              , RULL(0x8000882206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x800088220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x800088220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL              , RULL(0x8000902206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x800090220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x800090220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL              , RULL(0x8000982206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x800098220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x800098220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_FIR_MASK_PL                 , RULL(0x8002102206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_FIR_PL                      , RULL(0x8002082206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_FIR_PL                    , RULL(0x800208220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_FIR_PL                    , RULL(0x800208220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL               , RULL(0x8002002206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL              , RULL(0x8003002706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x800300270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x800300270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x800248270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x800248270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL              , RULL(0x8003082706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x800308270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x800308270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x800250270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x800250270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL              , RULL(0x8003102706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x800310270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x800310270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x800258270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x800258270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x800260270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x800260270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL             , RULL(0x8002202706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x800220270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x800220270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL              , RULL(0x8002C02706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C0270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C0270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL             , RULL(0x8002282706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x800228270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x800228270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL              , RULL(0x8002C82706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C8270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C8270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL             , RULL(0x8002302706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x800230270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x800230270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL             , RULL(0x8002682706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x800268270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x800268270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL             , RULL(0x8002702706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x800270270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x800270270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL             , RULL(0x8002782706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x800278270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x800278270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x800008270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x800008270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL              , RULL(0x8000802706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x800080270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x800080270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x800010270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x800010270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL              , RULL(0x8000882706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x800088270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x800088270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x800018270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x800018270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL              , RULL(0x8000902706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x800090270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x800090270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x800020270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x800020270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL              , RULL(0x8000982706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x800098270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x800098270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x800028270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x800028270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x800030270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x800030270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x800038270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x800038270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x800040270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x800040270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_FIR_MASK_PL                 , RULL(0x8002102706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_FIR_MASK_PL               , RULL(0x800210270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_FIR_MASK_PL               , RULL(0x800210270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_FIR_PL                      , RULL(0x8002082706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_FIR_PL                    , RULL(0x800208270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_FIR_PL                    , RULL(0x800208270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL               , RULL(0x8002002706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL             , RULL(0x800200270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL             , RULL(0x800200270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL              , RULL(0x8003002506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x800300250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x800300250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x800248250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x800248250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL              , RULL(0x8003082506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x800308250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x800308250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x800250250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x800250250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL              , RULL(0x8003102506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x800310250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x800310250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x800258250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x800258250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x800260250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x800260250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL             , RULL(0x8002202506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x800220250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x800220250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL              , RULL(0x8002C02506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C0250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C0250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL             , RULL(0x8002282506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x800228250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x800228250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL              , RULL(0x8002C82506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C8250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C8250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL             , RULL(0x8002302506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x800230250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x800230250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL             , RULL(0x8002682506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x800268250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x800268250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL             , RULL(0x8002702506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x800270250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x800270250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL             , RULL(0x8002782506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x800278250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x800278250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x800008250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x800008250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL              , RULL(0x8000802506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x800080250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x800080250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x800010250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x800010250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL              , RULL(0x8000882506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x800088250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x800088250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x800018250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x800018250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL              , RULL(0x8000902506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x800090250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x800090250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x800020250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x800020250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL              , RULL(0x8000982506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x800098250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x800098250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x800028250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x800028250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x800030250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x800030250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x800038250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x800038250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x800040250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x800040250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_FIR_MASK_PL                 , RULL(0x8002102506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_FIR_MASK_PL               , RULL(0x800210250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_FIR_MASK_PL               , RULL(0x800210250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_FIR_PL                      , RULL(0x8002082506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_FIR_PL                    , RULL(0x800208250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_FIR_PL                    , RULL(0x800208250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL               , RULL(0x8002002506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL             , RULL(0x800200250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL             , RULL(0x800200250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL              , RULL(0x8003002606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x800300260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x800300260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x800248260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x800248260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL              , RULL(0x8003082606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x800308260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x800308260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x800250260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x800250260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL              , RULL(0x8003102606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x800310260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x800310260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x800258260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x800258260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x800260260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x800260260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL             , RULL(0x8002202606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x800220260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x800220260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL              , RULL(0x8002C02606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C0260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C0260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL             , RULL(0x8002282606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x800228260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x800228260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL              , RULL(0x8002C82606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C8260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C8260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL             , RULL(0x8002302606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x800230260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x800230260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL             , RULL(0x8002682606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x800268260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x800268260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL             , RULL(0x8002702606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x800270260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x800270260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL             , RULL(0x8002782606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x800278260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x800278260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x800008260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x800008260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL              , RULL(0x8000802606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x800080260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x800080260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x800010260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x800010260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL              , RULL(0x8000882606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x800088260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x800088260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x800018260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x800018260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL              , RULL(0x8000902606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x800090260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x800090260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x800020260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x800020260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL              , RULL(0x8000982606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x800098260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x800098260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x800028260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x800028260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x800030260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x800030260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x800038260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x800038260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x800040260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x800040260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_FIR_MASK_PL                 , RULL(0x8002102606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_FIR_MASK_PL               , RULL(0x800210260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_FIR_MASK_PL               , RULL(0x800210260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_FIR_PL                      , RULL(0x8002082606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_FIR_PL                    , RULL(0x800208260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_FIR_PL                    , RULL(0x800208260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL               , RULL(0x8002002606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL             , RULL(0x800200260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL             , RULL(0x800200260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL              , RULL(0x8003002406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x800300240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x800300240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL              , RULL(0x8003082406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x800308240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x800308240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL              , RULL(0x8003102406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x800310240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x800310240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL             , RULL(0x8002202406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL              , RULL(0x8002C02406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C0240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C0240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL             , RULL(0x8002282406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL              , RULL(0x8002C82406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C8240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C8240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL             , RULL(0x8002302406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL             , RULL(0x8002682406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL             , RULL(0x8002702406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL             , RULL(0x8002782406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL              , RULL(0x8000802406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x800080240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x800080240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL              , RULL(0x8000882406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x800088240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x800088240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL              , RULL(0x8000902406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x800090240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x800090240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL              , RULL(0x8000982406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x800098240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x800098240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_FIR_MASK_PL                 , RULL(0x8002102406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_FIR_PL                      , RULL(0x8002082406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_FIR_PL                    , RULL(0x800208240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_FIR_PL                    , RULL(0x800208240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL               , RULL(0x8002002406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL              , RULL(0x8003002806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x800300280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x800300280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x800248280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x800248280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL              , RULL(0x8003082806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x800308280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x800308280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x800250280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x800250280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL              , RULL(0x8003102806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x800310280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x800310280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x800258280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x800258280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x800260280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x800260280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL             , RULL(0x8002202806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x800220280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x800220280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL              , RULL(0x8002C02806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C0280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C0280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL             , RULL(0x8002282806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x800228280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x800228280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL              , RULL(0x8002C82806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C8280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C8280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL             , RULL(0x8002302806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x800230280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x800230280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL             , RULL(0x8002682806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x800268280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x800268280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL             , RULL(0x8002702806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x800270280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x800270280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL             , RULL(0x8002782806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x800278280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x800278280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x800008280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x800008280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL              , RULL(0x8000802806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x800080280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x800080280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x800010280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x800010280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL              , RULL(0x8000882806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x800088280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x800088280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x800018280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x800018280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL              , RULL(0x8000902806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x800090280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x800090280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x800020280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x800020280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL              , RULL(0x8000982806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x800098280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x800098280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x800028280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x800028280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x800030280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x800030280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x800038280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x800038280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x800040280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x800040280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_FIR_MASK_PL                 , RULL(0x8002102806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_FIR_MASK_PL               , RULL(0x800210280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_FIR_MASK_PL               , RULL(0x800210280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_FIR_PL                      , RULL(0x8002082806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_FIR_PL                    , RULL(0x800208280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_FIR_PL                    , RULL(0x800208280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL               , RULL(0x8002002806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL             , RULL(0x800200280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL             , RULL(0x800200280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL              , RULL(0x8003002A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x8003002A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x8003002A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x8002482A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x8002482A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL              , RULL(0x8003082A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x8003082A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x8003082A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x8002502A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x8002502A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL              , RULL(0x8003102A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x8003102A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x8003102A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x8002582A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x8002582A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x8002602A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x8002602A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002402A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002402A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL             , RULL(0x8002202A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x8002202A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x8002202A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL              , RULL(0x8002C02A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C02A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C02A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL             , RULL(0x8002282A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x8002282A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x8002282A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL              , RULL(0x8002C82A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C82A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C82A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL             , RULL(0x8002302A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x8002302A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x8002302A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL             , RULL(0x8002682A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x8002682A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x8002682A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL             , RULL(0x8002702A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x8002702A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x8002702A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL             , RULL(0x8002782A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x8002782A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x8002782A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x8000082A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x8000082A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL              , RULL(0x8000802A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x8000802A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x8000802A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x8000102A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x8000102A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL              , RULL(0x8000882A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x8000882A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x8000882A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x8000182A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x8000182A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL              , RULL(0x8000902A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x8000902A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x8000902A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x8000202A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x8000202A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL              , RULL(0x8000982A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x8000982A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x8000982A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x8000282A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x8000282A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A02A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A02A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x8000302A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x8000302A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A82A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A82A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x8000382A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x8000382A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B02A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B02A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x8000402A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x8000402A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B82A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B82A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C02A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C02A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000002A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000002A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002182A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002182A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_FIR_MASK_PL                 , RULL(0x8002102A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_FIR_MASK_PL               , RULL(0x8002102A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_FIR_MASK_PL               , RULL(0x8002102A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_FIR_PL                      , RULL(0x8002082A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_FIR_PL                    , RULL(0x8002082A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_FIR_PL                    , RULL(0x8002082A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL               , RULL(0x8002002A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL             , RULL(0x8002002A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL             , RULL(0x8002002A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL              , RULL(0x8003002906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x800300290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x800300290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x800248290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x800248290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL              , RULL(0x8003082906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x800308290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x800308290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x800250290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x800250290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL              , RULL(0x8003102906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x800310290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x800310290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x800258290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x800258290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x800260290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x800260290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL             , RULL(0x8002202906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x800220290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x800220290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL              , RULL(0x8002C02906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C0290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C0290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL             , RULL(0x8002282906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x800228290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x800228290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL              , RULL(0x8002C82906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C8290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C8290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL             , RULL(0x8002302906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x800230290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x800230290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL             , RULL(0x8002682906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x800268290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x800268290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL             , RULL(0x8002702906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x800270290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x800270290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL             , RULL(0x8002782906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x800278290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x800278290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x800008290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x800008290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL              , RULL(0x8000802906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x800080290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x800080290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x800010290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x800010290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL              , RULL(0x8000882906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x800088290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x800088290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x800018290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x800018290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL              , RULL(0x8000902906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x800090290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x800090290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x800020290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x800020290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL              , RULL(0x8000982906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x800098290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x800098290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x800028290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x800028290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x800030290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x800030290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x800038290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x800038290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x800040290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x800040290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_FIR_MASK_PL                 , RULL(0x8002102906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_FIR_MASK_PL               , RULL(0x800210290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_FIR_MASK_PL               , RULL(0x800210290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_FIR_PL                      , RULL(0x8002082906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_FIR_PL                    , RULL(0x800208290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_FIR_PL                    , RULL(0x800208290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL               , RULL(0x8002002906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL             , RULL(0x800200290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL             , RULL(0x800200290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL              , RULL(0x8003003106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x800300310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x800300310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL             , RULL(0x8002483106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x800248310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL              , RULL(0x8003083106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x800308310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x800308310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL             , RULL(0x8002503106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x800250310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL              , RULL(0x8003103106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x800310310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x800310310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL             , RULL(0x8002583106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x800258310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL             , RULL(0x8002603106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x800260310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002403106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL             , RULL(0x8002203106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x800220310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL              , RULL(0x8002C03106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C0310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C0310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL             , RULL(0x8002283106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x800228310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL              , RULL(0x8002C83106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C8310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C8310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL             , RULL(0x8002303106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x800230310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL             , RULL(0x8002683106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x800268310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL             , RULL(0x8002703106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x800270310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL             , RULL(0x8002783106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x800278310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL             , RULL(0x8000083106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x800008310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL              , RULL(0x8000803106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x800080310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x800080310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL             , RULL(0x8000103106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x800010310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL              , RULL(0x8000883106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x800088310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x800088310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL             , RULL(0x8000183106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x800018310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL              , RULL(0x8000903106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x800090310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x800090310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL             , RULL(0x8000203106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x800020310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL              , RULL(0x8000983106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x800098310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x800098310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL             , RULL(0x8000283106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x800028310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL              , RULL(0x8000A03106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL             , RULL(0x8000303106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x800030310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL              , RULL(0x8000A83106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL             , RULL(0x8000383106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x800038310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL              , RULL(0x8000B03106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL             , RULL(0x8000403106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x800040310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL              , RULL(0x8000B83106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL              , RULL(0x8000C03106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000003106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002183106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_FIR_MASK_PL                 , RULL(0x8002103106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_FIR_MASK_PL               , RULL(0x800210310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_FIR_PL                      , RULL(0x8002083106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_FIR_PL                    , RULL(0x800208310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_FIR_PL                    , RULL(0x800208310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL               , RULL(0x8002003106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL             , RULL(0x800200310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL              , RULL(0x8003002E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x8003002E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL1_E_PL            , RULL(0x8003002E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x8002482E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL           , RULL(0x8002482E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL              , RULL(0x8003082E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x8003082E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL            , RULL(0x8003082E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x8002502E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL           , RULL(0x8002502E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL              , RULL(0x8003102E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x8003102E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_E_PL            , RULL(0x8003102E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x8002582E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL           , RULL(0x8002582E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x8002602E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL5_EO_PL           , RULL(0x8002602E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002402E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002402E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL             , RULL(0x8002202E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x8002202E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL           , RULL(0x8002202E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL              , RULL(0x8002C02E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C02E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL            , RULL(0x8002C02E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL             , RULL(0x8002282E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x8002282E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL           , RULL(0x8002282E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL              , RULL(0x8002C82E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C82E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL            , RULL(0x8002C82E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL             , RULL(0x8002302E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x8002302E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL           , RULL(0x8002302E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL             , RULL(0x8002682E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x8002682E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_STAT1_EO_PL           , RULL(0x8002682E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL             , RULL(0x8002702E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x8002702E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_STAT2_EO_PL           , RULL(0x8002702E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL             , RULL(0x8002782E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x8002782E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL           , RULL(0x8002782E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x8000082E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL           , RULL(0x8000082E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL              , RULL(0x8000802E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x8000802E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL            , RULL(0x8000802E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x8000102E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL           , RULL(0x8000102E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL              , RULL(0x8000882E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x8000882E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL            , RULL(0x8000882E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x8000182E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL           , RULL(0x8000182E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL              , RULL(0x8000902E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x8000902E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL            , RULL(0x8000902E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x8000202E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL           , RULL(0x8000202E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL              , RULL(0x8000982E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x8000982E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL            , RULL(0x8000982E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x8000282E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL           , RULL(0x8000282E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A02E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL            , RULL(0x8000A02E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x8000302E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL           , RULL(0x8000302E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A82E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL            , RULL(0x8000A82E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x8000382E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL           , RULL(0x8000382E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B02E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL            , RULL(0x8000B02E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x8000402E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL           , RULL(0x8000402E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B82E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL            , RULL(0x8000B82E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C02E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL            , RULL(0x8000C02E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000002E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000002E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002182E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002182E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_FIR_MASK_PL                 , RULL(0x8002102E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_FIR_MASK_PL               , RULL(0x8002102E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_FIR_MASK_PL               , RULL(0x8002102E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_FIR_PL                      , RULL(0x8002082E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_FIR_PL                    , RULL(0x8002082E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_FIR_PL                    , RULL(0x8002082E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL               , RULL(0x8002002E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL             , RULL(0x8002002E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL             , RULL(0x8002002E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL              , RULL(0x8003002C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x8003002C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL1_E_PL            , RULL(0x8003002C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x8002482C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL           , RULL(0x8002482C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL              , RULL(0x8003082C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x8003082C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL            , RULL(0x8003082C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x8002502C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL           , RULL(0x8002502C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL              , RULL(0x8003102C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x8003102C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_E_PL            , RULL(0x8003102C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x8002582C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL           , RULL(0x8002582C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x8002602C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL5_EO_PL           , RULL(0x8002602C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002402C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002402C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL             , RULL(0x8002202C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x8002202C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL           , RULL(0x8002202C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL              , RULL(0x8002C02C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C02C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL            , RULL(0x8002C02C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL             , RULL(0x8002282C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x8002282C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL           , RULL(0x8002282C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL              , RULL(0x8002C82C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C82C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL            , RULL(0x8002C82C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL             , RULL(0x8002302C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x8002302C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL           , RULL(0x8002302C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL             , RULL(0x8002682C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x8002682C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_STAT1_EO_PL           , RULL(0x8002682C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL             , RULL(0x8002702C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x8002702C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_STAT2_EO_PL           , RULL(0x8002702C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL             , RULL(0x8002782C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x8002782C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL           , RULL(0x8002782C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x8000082C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL           , RULL(0x8000082C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL              , RULL(0x8000802C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x8000802C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL            , RULL(0x8000802C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x8000102C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL           , RULL(0x8000102C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL              , RULL(0x8000882C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x8000882C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL            , RULL(0x8000882C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x8000182C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL           , RULL(0x8000182C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL              , RULL(0x8000902C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x8000902C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL            , RULL(0x8000902C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x8000202C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL           , RULL(0x8000202C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL              , RULL(0x8000982C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x8000982C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL            , RULL(0x8000982C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x8000282C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL           , RULL(0x8000282C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A02C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL            , RULL(0x8000A02C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x8000302C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL           , RULL(0x8000302C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A82C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL            , RULL(0x8000A82C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x8000382C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL           , RULL(0x8000382C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B02C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL            , RULL(0x8000B02C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x8000402C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL           , RULL(0x8000402C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B82C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL            , RULL(0x8000B82C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C02C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL            , RULL(0x8000C02C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000002C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000002C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002182C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002182C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_FIR_MASK_PL                 , RULL(0x8002102C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_FIR_MASK_PL               , RULL(0x8002102C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_FIR_MASK_PL               , RULL(0x8002102C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_FIR_PL                      , RULL(0x8002082C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_FIR_PL                    , RULL(0x8002082C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_FIR_PL                    , RULL(0x8002082C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL               , RULL(0x8002002C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL             , RULL(0x8002002C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL             , RULL(0x8002002C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL              , RULL(0x8003002D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x8003002D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL1_E_PL            , RULL(0x8003002D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x8002482D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL           , RULL(0x8002482D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL              , RULL(0x8003082D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x8003082D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL            , RULL(0x8003082D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x8002502D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL           , RULL(0x8002502D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL              , RULL(0x8003102D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x8003102D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_E_PL            , RULL(0x8003102D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x8002582D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL           , RULL(0x8002582D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x8002602D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL5_EO_PL           , RULL(0x8002602D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002402D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002402D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL             , RULL(0x8002202D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x8002202D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL           , RULL(0x8002202D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL              , RULL(0x8002C02D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C02D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL            , RULL(0x8002C02D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL             , RULL(0x8002282D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x8002282D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL           , RULL(0x8002282D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL              , RULL(0x8002C82D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C82D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL            , RULL(0x8002C82D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL             , RULL(0x8002302D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x8002302D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL           , RULL(0x8002302D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL             , RULL(0x8002682D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x8002682D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_STAT1_EO_PL           , RULL(0x8002682D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL             , RULL(0x8002702D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x8002702D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_STAT2_EO_PL           , RULL(0x8002702D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL             , RULL(0x8002782D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x8002782D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL           , RULL(0x8002782D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x8000082D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL           , RULL(0x8000082D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL              , RULL(0x8000802D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x8000802D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL            , RULL(0x8000802D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x8000102D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL           , RULL(0x8000102D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL              , RULL(0x8000882D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x8000882D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL            , RULL(0x8000882D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x8000182D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL           , RULL(0x8000182D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL              , RULL(0x8000902D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x8000902D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL            , RULL(0x8000902D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x8000202D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL           , RULL(0x8000202D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL              , RULL(0x8000982D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x8000982D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL            , RULL(0x8000982D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x8000282D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL           , RULL(0x8000282D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A02D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL            , RULL(0x8000A02D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x8000302D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL           , RULL(0x8000302D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A82D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL            , RULL(0x8000A82D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x8000382D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL           , RULL(0x8000382D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B02D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL            , RULL(0x8000B02D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x8000402D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL           , RULL(0x8000402D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B82D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL            , RULL(0x8000B82D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C02D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL            , RULL(0x8000C02D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000002D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000002D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002182D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002182D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_FIR_MASK_PL                 , RULL(0x8002102D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_FIR_MASK_PL               , RULL(0x8002102D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_FIR_MASK_PL               , RULL(0x8002102D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_FIR_PL                      , RULL(0x8002082D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_FIR_PL                    , RULL(0x8002082D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_FIR_PL                    , RULL(0x8002082D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL               , RULL(0x8002002D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL             , RULL(0x8002002D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL             , RULL(0x8002002D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL              , RULL(0x8003002B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x8003002B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL1_E_PL            , RULL(0x8003002B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x8002482B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL           , RULL(0x8002482B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL              , RULL(0x8003082B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x8003082B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL            , RULL(0x8003082B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x8002502B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL           , RULL(0x8002502B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL              , RULL(0x8003102B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x8003102B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_E_PL            , RULL(0x8003102B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x8002582B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL           , RULL(0x8002582B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x8002602B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL5_EO_PL           , RULL(0x8002602B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002402B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002402B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL             , RULL(0x8002202B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x8002202B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL           , RULL(0x8002202B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL              , RULL(0x8002C02B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C02B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL            , RULL(0x8002C02B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL             , RULL(0x8002282B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x8002282B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL           , RULL(0x8002282B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL              , RULL(0x8002C82B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C82B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL            , RULL(0x8002C82B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL             , RULL(0x8002302B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x8002302B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL           , RULL(0x8002302B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL             , RULL(0x8002682B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x8002682B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_STAT1_EO_PL           , RULL(0x8002682B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL             , RULL(0x8002702B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x8002702B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_STAT2_EO_PL           , RULL(0x8002702B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL             , RULL(0x8002782B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x8002782B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL           , RULL(0x8002782B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x8000082B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL           , RULL(0x8000082B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL              , RULL(0x8000802B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x8000802B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL            , RULL(0x8000802B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x8000102B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL           , RULL(0x8000102B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL              , RULL(0x8000882B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x8000882B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL            , RULL(0x8000882B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x8000182B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL           , RULL(0x8000182B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL              , RULL(0x8000902B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x8000902B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL            , RULL(0x8000902B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x8000202B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL           , RULL(0x8000202B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL              , RULL(0x8000982B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x8000982B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL            , RULL(0x8000982B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x8000282B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL           , RULL(0x8000282B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A02B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL            , RULL(0x8000A02B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x8000302B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL           , RULL(0x8000302B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A82B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL            , RULL(0x8000A82B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x8000382B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL           , RULL(0x8000382B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B02B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL            , RULL(0x8000B02B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x8000402B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL           , RULL(0x8000402B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B82B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL            , RULL(0x8000B82B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C02B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL            , RULL(0x8000C02B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000002B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000002B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002182B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002182B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_FIR_MASK_PL                 , RULL(0x8002102B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_FIR_MASK_PL               , RULL(0x8002102B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_FIR_MASK_PL               , RULL(0x8002102B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_FIR_PL                      , RULL(0x8002082B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_FIR_PL                    , RULL(0x8002082B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_FIR_PL                    , RULL(0x8002082B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL               , RULL(0x8002002B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL             , RULL(0x8002002B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL             , RULL(0x8002002B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL              , RULL(0x8003002F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL            , RULL(0x8003002F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL1_E_PL            , RULL(0x8003002F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL             , RULL(0x8002482F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL           , RULL(0x8002482F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL           , RULL(0x8002482F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL              , RULL(0x8003082F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL            , RULL(0x8003082F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL            , RULL(0x8003082F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL             , RULL(0x8002502F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL           , RULL(0x8002502F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL           , RULL(0x8002502F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL              , RULL(0x8003102F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL            , RULL(0x8003102F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_E_PL            , RULL(0x8003102F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL             , RULL(0x8002582F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL           , RULL(0x8002582F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL           , RULL(0x8002582F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL             , RULL(0x8002602F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL           , RULL(0x8002602F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL5_EO_PL           , RULL(0x8002602F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002402F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002402F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL          , RULL(0x8002402F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL             , RULL(0x8002202F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL           , RULL(0x8002202F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL           , RULL(0x8002202F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL              , RULL(0x8002C02F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL            , RULL(0x8002C02F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL            , RULL(0x8002C02F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL             , RULL(0x8002282F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL           , RULL(0x8002282F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL           , RULL(0x8002282F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL              , RULL(0x8002C82F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL            , RULL(0x8002C82F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL            , RULL(0x8002C82F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL             , RULL(0x8002302F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL           , RULL(0x8002302F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL           , RULL(0x8002302F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL             , RULL(0x8002682F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL           , RULL(0x8002682F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_STAT1_EO_PL           , RULL(0x8002682F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL             , RULL(0x8002702F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL           , RULL(0x8002702F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_STAT2_EO_PL           , RULL(0x8002702F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL             , RULL(0x8002782F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL           , RULL(0x8002782F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL           , RULL(0x8002782F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL             , RULL(0x8000082F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL           , RULL(0x8000082F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL           , RULL(0x8000082F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL              , RULL(0x8000802F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL            , RULL(0x8000802F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL            , RULL(0x8000802F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL             , RULL(0x8000102F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL           , RULL(0x8000102F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL           , RULL(0x8000102F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL              , RULL(0x8000882F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL            , RULL(0x8000882F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL            , RULL(0x8000882F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL             , RULL(0x8000182F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL           , RULL(0x8000182F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL           , RULL(0x8000182F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL              , RULL(0x8000902F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL            , RULL(0x8000902F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL            , RULL(0x8000902F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL             , RULL(0x8000202F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL           , RULL(0x8000202F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL           , RULL(0x8000202F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL              , RULL(0x8000982F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL            , RULL(0x8000982F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL            , RULL(0x8000982F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL             , RULL(0x8000282F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL           , RULL(0x8000282F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL           , RULL(0x8000282F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL              , RULL(0x8000A02F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL            , RULL(0x8000A02F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL            , RULL(0x8000A02F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL             , RULL(0x8000302F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL           , RULL(0x8000302F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL           , RULL(0x8000302F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL              , RULL(0x8000A82F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL            , RULL(0x8000A82F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL            , RULL(0x8000A82F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL             , RULL(0x8000382F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL           , RULL(0x8000382F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL           , RULL(0x8000382F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL              , RULL(0x8000B02F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL            , RULL(0x8000B02F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL            , RULL(0x8000B02F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL             , RULL(0x8000402F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL           , RULL(0x8000402F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL           , RULL(0x8000402F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL              , RULL(0x8000B82F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL            , RULL(0x8000B82F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL            , RULL(0x8000B82F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL              , RULL(0x8000C02F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL            , RULL(0x8000C02F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL            , RULL(0x8000C02F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000002F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000002F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x8000002F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002182F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002182F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL       , RULL(0x8002182F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_FIR_MASK_PL                 , RULL(0x8002102F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_FIR_MASK_PL               , RULL(0x8002102F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_FIR_MASK_PL               , RULL(0x8002102F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_FIR_PL                      , RULL(0x8002082F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_FIR_PL                    , RULL(0x8002082F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_FIR_PL                    , RULL(0x8002082F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL               , RULL(0x8002002F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL             , RULL(0x8002002F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL             , RULL(0x8002002F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL              , RULL(0x8003003006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL            , RULL(0x800300300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL1_E_PL            , RULL(0x800300300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL             , RULL(0x8002483006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL           , RULL(0x800248300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL           , RULL(0x800248300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL              , RULL(0x8003083006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL            , RULL(0x800308300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL            , RULL(0x800308300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL             , RULL(0x8002503006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL           , RULL(0x800250300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL           , RULL(0x800250300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL              , RULL(0x8003103006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL            , RULL(0x800310300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_E_PL            , RULL(0x800310300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL             , RULL(0x8002583006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL           , RULL(0x800258300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL           , RULL(0x800258300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL             , RULL(0x8002603006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL           , RULL(0x800260300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL5_EO_PL           , RULL(0x800260300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL            , RULL(0x8002403006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL          , RULL(0x800240300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL             , RULL(0x8002203006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL           , RULL(0x800220300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL           , RULL(0x800220300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL              , RULL(0x8002C03006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL            , RULL(0x8002C0300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL            , RULL(0x8002C0300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL             , RULL(0x8002283006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL           , RULL(0x800228300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL           , RULL(0x800228300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL              , RULL(0x8002C83006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL            , RULL(0x8002C8300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL            , RULL(0x8002C8300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL             , RULL(0x8002303006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL           , RULL(0x800230300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL           , RULL(0x800230300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL             , RULL(0x8002683006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL           , RULL(0x800268300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_STAT1_EO_PL           , RULL(0x800268300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL             , RULL(0x8002703006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL           , RULL(0x800270300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_STAT2_EO_PL           , RULL(0x800270300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL             , RULL(0x8002783006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL           , RULL(0x800278300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL           , RULL(0x800278300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL             , RULL(0x8000083006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL           , RULL(0x800008300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL           , RULL(0x800008300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL              , RULL(0x8000803006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL            , RULL(0x800080300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL            , RULL(0x800080300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL             , RULL(0x8000103006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL           , RULL(0x800010300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL           , RULL(0x800010300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL              , RULL(0x8000883006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL            , RULL(0x800088300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL            , RULL(0x800088300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL             , RULL(0x8000183006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL           , RULL(0x800018300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL           , RULL(0x800018300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL              , RULL(0x8000903006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL            , RULL(0x800090300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL            , RULL(0x800090300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL             , RULL(0x8000203006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL           , RULL(0x800020300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL           , RULL(0x800020300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL              , RULL(0x8000983006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL            , RULL(0x800098300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL            , RULL(0x800098300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL             , RULL(0x8000283006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL           , RULL(0x800028300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL           , RULL(0x800028300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL              , RULL(0x8000A03006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL            , RULL(0x8000A0300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL             , RULL(0x8000303006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL           , RULL(0x800030300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL           , RULL(0x800030300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL              , RULL(0x8000A83006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL            , RULL(0x8000A8300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL             , RULL(0x8000383006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL           , RULL(0x800038300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL           , RULL(0x800038300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL              , RULL(0x8000B03006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL            , RULL(0x8000B0300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL             , RULL(0x8000403006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL           , RULL(0x800040300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL           , RULL(0x800040300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL              , RULL(0x8000B83006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL            , RULL(0x8000B8300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL              , RULL(0x8000C03006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL            , RULL(0x8000C0300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL      , RULL(0x8000003006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL    , RULL(0x800000300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL         , RULL(0x8002183006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL       , RULL(0x800218300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_FIR_MASK_PL                 , RULL(0x8002103006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_FIR_MASK_PL               , RULL(0x800210300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_FIR_MASK_PL               , RULL(0x800210300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_FIR_PL                      , RULL(0x8002083006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_FIR_PL                    , RULL(0x800208300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_FIR_PL                    , RULL(0x800208300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL               , RULL(0x8002003006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL             , RULL(0x800200300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL             , RULL(0x800200300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL10_EO_PG                            , RULL(0x8009202006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL10_EO_PG                          , RULL(0x800920200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL10_EO_PG                          , RULL(0x800920200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL11_EO_PG                            , RULL(0x8009282006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL11_EO_PG                          , RULL(0x800928200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL11_EO_PG                          , RULL(0x800928200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL12_EO_PG                            , RULL(0x8009302006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL12_EO_PG                          , RULL(0x800930200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL12_EO_PG                          , RULL(0x800930200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL13_EO_PG                            , RULL(0x8009382006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL13_EO_PG                          , RULL(0x800938200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL13_EO_PG                          , RULL(0x800938200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL14_EO_PG                            , RULL(0x8009402006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL14_EO_PG                          , RULL(0x800940200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL14_EO_PG                          , RULL(0x800940200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL15_EO_PG                            , RULL(0x8009482006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL15_EO_PG                          , RULL(0x800948200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL15_EO_PG                          , RULL(0x800948200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL1_EO_PG                             , RULL(0x8008D82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL1_EO_PG                           , RULL(0x8008D8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL1_EO_PG                           , RULL(0x8008D8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL1_E_PG                              , RULL(0x8009F02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL1_E_PG                            , RULL(0x8009F0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL1_E_PG                            , RULL(0x8009F0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL2_EO_PG                             , RULL(0x8008E02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL2_EO_PG                           , RULL(0x8008E0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL2_EO_PG                           , RULL(0x8008E0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL3_EO_PG                             , RULL(0x8008E82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL3_EO_PG                           , RULL(0x8008E8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL3_EO_PG                           , RULL(0x8008E8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL4_EO_PG                             , RULL(0x8008F02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL4_EO_PG                           , RULL(0x8008F0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL4_EO_PG                           , RULL(0x8008F0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL4_E_PG                              , RULL(0x8009F82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL4_E_PG                            , RULL(0x8009F8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL4_E_PG                            , RULL(0x8009F8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL5_EO_PG                             , RULL(0x8008F82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL5_EO_PG                           , RULL(0x8008F8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL5_EO_PG                           , RULL(0x8008F8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL6_EO_PG                             , RULL(0x8009002006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL6_EO_PG                           , RULL(0x800900200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL6_EO_PG                           , RULL(0x800900200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL8_EO_PG                             , RULL(0x8009102006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL8_EO_PG                           , RULL(0x800910200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL8_EO_PG                           , RULL(0x800910200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTL9_EO_PG                             , RULL(0x8009182006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTL9_EO_PG                           , RULL(0x800918200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTL9_EO_PG                           , RULL(0x800918200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTLX10_E_PG                            , RULL(0x800A282006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG                          , RULL(0x800A28200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTLX10_E_PG                          , RULL(0x800A28200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTLX11_E_PG                            , RULL(0x800A302006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTLX11_E_PG                          , RULL(0x800A30200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTLX11_E_PG                          , RULL(0x800A30200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTLX5_E_PG                             , RULL(0x800A002006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTLX5_E_PG                           , RULL(0x800A00200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTLX5_E_PG                           , RULL(0x800A00200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_CNTLX7_EO_PG                            , RULL(0x8009082006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_CNTLX7_EO_PG                          , RULL(0x800908200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_CNTLX7_EO_PG                          , RULL(0x800908200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE10_EO_PG                            , RULL(0x8008582006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE10_EO_PG                          , RULL(0x800858200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE10_EO_PG                          , RULL(0x800858200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE10_E_PG                             , RULL(0x8009D82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE10_E_PG                           , RULL(0x8009D8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE10_E_PG                           , RULL(0x8009D8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE11_EO_PG                            , RULL(0x8008602006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE11_EO_PG                          , RULL(0x800860200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE11_EO_PG                          , RULL(0x800860200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE11_E_PG                             , RULL(0x8009E02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE11_E_PG                           , RULL(0x8009E0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE11_E_PG                           , RULL(0x8009E0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE12_EO_PG                            , RULL(0x8008682006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE12_EO_PG                          , RULL(0x800868200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE12_EO_PG                          , RULL(0x800868200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE12_E_PG                             , RULL(0x8009E82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE12_E_PG                           , RULL(0x8009E8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE12_E_PG                           , RULL(0x8009E8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE13_EO_PG                            , RULL(0x8008702006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE13_EO_PG                          , RULL(0x800870200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE13_EO_PG                          , RULL(0x800870200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE14_EO_PG                            , RULL(0x8008782006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE14_EO_PG                          , RULL(0x800878200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE14_EO_PG                          , RULL(0x800878200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE15_EO_PG                            , RULL(0x8008802006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE15_EO_PG                          , RULL(0x800880200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE15_EO_PG                          , RULL(0x800880200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE16_EO_PG                            , RULL(0x8008882006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE16_EO_PG                          , RULL(0x800888200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE16_EO_PG                          , RULL(0x800888200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE17_EO_PG                            , RULL(0x8008902006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE17_EO_PG                          , RULL(0x800890200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE17_EO_PG                          , RULL(0x800890200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE18_EO_PG                            , RULL(0x8008982006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE18_EO_PG                          , RULL(0x800898200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE18_EO_PG                          , RULL(0x800898200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE19_EO_PG                            , RULL(0x8008A02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE19_EO_PG                          , RULL(0x8008A0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE19_EO_PG                          , RULL(0x8008A0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE1_EO_PG                             , RULL(0x8008102006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE1_EO_PG                           , RULL(0x800810200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE1_EO_PG                           , RULL(0x800810200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE1_E_PG                              , RULL(0x8009902006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE1_E_PG                            , RULL(0x800990200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE1_E_PG                            , RULL(0x800990200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE20_EO_PG                            , RULL(0x8008A82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE20_EO_PG                          , RULL(0x8008A8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE20_EO_PG                          , RULL(0x8008A8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE21_EO_PG                            , RULL(0x8008B02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE21_EO_PG                          , RULL(0x8008B0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE21_EO_PG                          , RULL(0x8008B0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE22_EO_PG                            , RULL(0x8008B82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE22_EO_PG                          , RULL(0x8008B8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE22_EO_PG                          , RULL(0x8008B8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE23_EO_PG                            , RULL(0x8008C02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE23_EO_PG                          , RULL(0x8008C0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE23_EO_PG                          , RULL(0x8008C0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE24_EO_PG                            , RULL(0x8008C82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE24_EO_PG                          , RULL(0x8008C8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE24_EO_PG                          , RULL(0x8008C8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE26_EO_PG                            , RULL(0x8009682006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE26_EO_PG                          , RULL(0x800968200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE26_EO_PG                          , RULL(0x800968200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE27_EO_PG                            , RULL(0x8009702006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE27_EO_PG                          , RULL(0x800970200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE27_EO_PG                          , RULL(0x800970200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE28_EO_PG                            , RULL(0x8009782006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE28_EO_PG                          , RULL(0x800978200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE28_EO_PG                          , RULL(0x800978200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE29_EO_PG                            , RULL(0x8008D02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE29_EO_PG                          , RULL(0x8008D0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE29_EO_PG                          , RULL(0x8008D0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE2_EO_PG                             , RULL(0x8008182006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE2_EO_PG                           , RULL(0x800818200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE2_EO_PG                           , RULL(0x800818200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE2_E_PG                              , RULL(0x8009982006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE2_E_PG                            , RULL(0x800998200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE2_E_PG                            , RULL(0x800998200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE3_EO_PG                             , RULL(0x8008202006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE3_EO_PG                           , RULL(0x800820200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE3_EO_PG                           , RULL(0x800820200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE3_E_PG                              , RULL(0x8009A02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE3_E_PG                            , RULL(0x8009A0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE3_E_PG                            , RULL(0x8009A0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE4_EO_PG                             , RULL(0x8008282006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE4_EO_PG                           , RULL(0x800828200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE4_EO_PG                           , RULL(0x800828200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE4_E_PG                              , RULL(0x8009A82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE4_E_PG                            , RULL(0x8009A8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE4_E_PG                            , RULL(0x8009A8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE5_EO_PG                             , RULL(0x8008302006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE5_EO_PG                           , RULL(0x800830200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE5_EO_PG                           , RULL(0x800830200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE5_E_PG                              , RULL(0x8009B02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE5_E_PG                            , RULL(0x8009B0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE5_E_PG                            , RULL(0x8009B0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE6_EO_PG                             , RULL(0x8008382006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE6_EO_PG                           , RULL(0x800838200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE6_EO_PG                           , RULL(0x800838200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE6_E_PG                              , RULL(0x8009B82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE6_E_PG                            , RULL(0x8009B8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE6_E_PG                            , RULL(0x8009B8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE7_EO_PG                             , RULL(0x8008402006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE7_EO_PG                           , RULL(0x800840200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE7_EO_PG                           , RULL(0x800840200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE7_E_PG                              , RULL(0x8009C02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE7_E_PG                            , RULL(0x8009C0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE7_E_PG                            , RULL(0x8009C0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE8_EO_PG                             , RULL(0x8008482006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE8_EO_PG                           , RULL(0x800848200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE8_EO_PG                           , RULL(0x800848200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE8_E_PG                              , RULL(0x8009C82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE8_E_PG                            , RULL(0x8009C8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE8_E_PG                            , RULL(0x8009C8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE9_EO_PG                             , RULL(0x8008502006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE9_EO_PG                           , RULL(0x800850200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE9_EO_PG                           , RULL(0x800850200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_MODE9_E_PG                              , RULL(0x8009D02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_MODE9_E_PG                            , RULL(0x8009D0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_MODE9_E_PG                            , RULL(0x8009D0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_STAT1_EO_PG                             , RULL(0x8009502006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_STAT1_EO_PG                           , RULL(0x800950200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_STAT1_EO_PG                           , RULL(0x800950200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_STAT1_E_PG                              , RULL(0x800A382006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_STAT1_E_PG                            , RULL(0x800A38200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_STAT1_E_PG                            , RULL(0x800A38200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_STAT2_EO_PG                             , RULL(0x8009582006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_STAT2_EO_PG                           , RULL(0x800958200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_STAT2_EO_PG                           , RULL(0x800958200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_STAT2_E_PG                              , RULL(0x800A402006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_STAT2_E_PG                            , RULL(0x800A40200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_STAT2_E_PG                            , RULL(0x800A40200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_STAT3_EO_PG                             , RULL(0x8009602006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_STAT3_EO_PG                           , RULL(0x800960200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_STAT3_EO_PG                           , RULL(0x800960200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_STAT4_E_PG                              , RULL(0x800A502006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_STAT4_E_PG                            , RULL(0x800A50200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_STAT4_E_PG                            , RULL(0x800A50200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_STAT5_E_PG                              , RULL(0x800A582006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_STAT5_E_PG                            , RULL(0x800A58200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_STAT5_E_PG                            , RULL(0x800A58200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_STAT6_E_PG                              , RULL(0x800A602006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_STAT6_E_PG                            , RULL(0x800A60200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_STAT6_E_PG                            , RULL(0x800A60200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_CTL_STATX8_E_PG                             , RULL(0x800A682006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_CTL_STATX8_E_PG                           , RULL(0x800A68200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_CTL_STATX8_E_PG                           , RULL(0x800A68200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_CNTL1_E_PG                           , RULL(0x800BE82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_CNTL1_E_PG                         , RULL(0x800BE8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_CNTL1_E_PG                         , RULL(0x800BE8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_CNTLX1_EO_PG                         , RULL(0x800B882006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_CNTLX1_EO_PG                       , RULL(0x800B88200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_CNTLX1_EO_PG                       , RULL(0x800B88200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_SPARE_MODE_PG                        , RULL(0x800B802006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_SPARE_MODE_PG                      , RULL(0x800B80200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_SPARE_MODE_PG                      , RULL(0x800B80200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_STAT10_EO_PG                         , RULL(0x800BD82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_STAT10_EO_PG                       , RULL(0x800BD8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_STAT10_EO_PG                       , RULL(0x800BD8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_STAT11_EO_PG                         , RULL(0x800BE02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_STAT11_EO_PG                       , RULL(0x800BE0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_STAT11_EO_PG                       , RULL(0x800BE0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_STAT12_EO_PG                         , RULL(0x800BF02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_STAT12_EO_PG                       , RULL(0x800BF0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_STAT12_EO_PG                       , RULL(0x800BF0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_STAT13_E_PG                          , RULL(0x800BF82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_STAT13_E_PG                        , RULL(0x800BF8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_STAT13_E_PG                        , RULL(0x800BF8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_STAT1_EO_PG                          , RULL(0x800B902006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_STAT1_EO_PG                        , RULL(0x800B90200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_STAT1_EO_PG                        , RULL(0x800B90200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_STAT2_EO_PG                          , RULL(0x800B982006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_STAT2_EO_PG                        , RULL(0x800B98200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_STAT2_EO_PG                        , RULL(0x800B98200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_STAT3_EO_PG                          , RULL(0x800BA02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_STAT3_EO_PG                        , RULL(0x800BA0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_STAT3_EO_PG                        , RULL(0x800BA0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_STAT4_EO_PG                          , RULL(0x800BA82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_STAT4_EO_PG                        , RULL(0x800BA8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_STAT4_EO_PG                        , RULL(0x800BA8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_STAT5_EO_PG                          , RULL(0x800BB02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_STAT5_EO_PG                        , RULL(0x800BB0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_STAT5_EO_PG                        , RULL(0x800BB0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_STAT6_EO_PG                          , RULL(0x800BB82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_STAT6_EO_PG                        , RULL(0x800BB8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_STAT6_EO_PG                        , RULL(0x800BB8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_STAT7_EO_PG                          , RULL(0x800BC02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_STAT7_EO_PG                        , RULL(0x800BC0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_STAT7_EO_PG                        , RULL(0x800BC0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_STAT8_EO_PG                          , RULL(0x800BC82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_STAT8_EO_PG                        , RULL(0x800BC8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_STAT8_EO_PG                        , RULL(0x800BC8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_DATASM_STAT9_EO_PG                          , RULL(0x800BD02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_DATASM_STAT9_EO_PG                        , RULL(0x800BD0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_DATASM_STAT9_EO_PG                        , RULL(0x800BD0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_FIR1_ERROR_INJECT_PG                        , RULL(0x800A982006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_FIR1_ERROR_INJECT_PG                      , RULL(0x800A98200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_FIR1_ERROR_INJECT_PG                      , RULL(0x800A98200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_FIR1_MASK_PG                                , RULL(0x800A902006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_FIR1_MASK_PG                              , RULL(0x800A90200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_FIR1_MASK_PG                              , RULL(0x800A90200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_FIR1_PG                                     , RULL(0x800A882006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_FIR1_PG                                   , RULL(0x800A88200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_FIR1_PG                                   , RULL(0x800A88200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_FIR2_ERROR_INJECT_PG                        , RULL(0x800B102006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_FIR2_ERROR_INJECT_PG                      , RULL(0x800B10200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_FIR2_ERROR_INJECT_PG                      , RULL(0x800B10200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_FIR2_MASK_PG                                , RULL(0x800B082006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_FIR2_MASK_PG                              , RULL(0x800B08200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_FIR2_MASK_PG                              , RULL(0x800B08200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_FIR2_PG                                     , RULL(0x800B002006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_FIR2_PG                                   , RULL(0x800B00200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_FIR2_PG                                   , RULL(0x800B00200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_FIR_TRAINING_MASK_PG                        , RULL(0x800AA82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_FIR_TRAINING_MASK_PG                      , RULL(0x800AA8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_FIR_TRAINING_MASK_PG                      , RULL(0x800AA8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_FIR_TRAINING_PG                             , RULL(0x800AA02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_FIR_TRAINING_PG                           , RULL(0x800AA0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_FIR_TRAINING_PG                           , RULL(0x800AA0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_CNTL2_EO_PG                           , RULL(0x800AE02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_CNTL2_EO_PG                         , RULL(0x800AE0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_CNTL2_EO_PG                         , RULL(0x800AE0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_CNTL3_EO_PG                           , RULL(0x800AE82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_CNTL3_EO_PG                         , RULL(0x800AE8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_CNTL3_EO_PG                         , RULL(0x800AE8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_CNTLX1_EO_PG                          , RULL(0x800AB02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_CNTLX1_EO_PG                        , RULL(0x800AB0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_CNTLX1_EO_PG                        , RULL(0x800AB0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_SPARE_MODE_PG                         , RULL(0x800A802006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_SPARE_MODE_PG                       , RULL(0x800A80200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_SPARE_MODE_PG                       , RULL(0x800A80200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_STAT10_E_PG                           , RULL(0x800B602006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_STAT10_E_PG                         , RULL(0x800B60200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_STAT10_E_PG                         , RULL(0x800B60200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_STAT1_EO_PG                           , RULL(0x800AB82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_STAT1_EO_PG                         , RULL(0x800AB8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_STAT1_EO_PG                         , RULL(0x800AB8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_STAT1_E_PG                            , RULL(0x800B182006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_STAT1_E_PG                          , RULL(0x800B18200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_STAT1_E_PG                          , RULL(0x800B18200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_STAT2_EO_PG                           , RULL(0x800AC02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_STAT2_EO_PG                         , RULL(0x800AC0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_STAT2_EO_PG                         , RULL(0x800AC0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_STAT2_E_PG                            , RULL(0x800B202006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_STAT2_E_PG                          , RULL(0x800B20200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_STAT2_E_PG                          , RULL(0x800B20200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_STAT3_EO_PG                           , RULL(0x800AC82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_STAT3_EO_PG                         , RULL(0x800AC8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_STAT3_EO_PG                         , RULL(0x800AC8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_STAT3_E_PG                            , RULL(0x800B282006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_STAT3_E_PG                          , RULL(0x800B28200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_STAT3_E_PG                          , RULL(0x800B28200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_STAT4_EO_PG                           , RULL(0x800AD02006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_STAT4_EO_PG                         , RULL(0x800AD0200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_STAT4_EO_PG                         , RULL(0x800AD0200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_STAT4_E_PG                            , RULL(0x800B302006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_STAT4_E_PG                          , RULL(0x800B30200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_STAT4_E_PG                          , RULL(0x800B30200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_STAT5_EO_PG                           , RULL(0x800AD82006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_STAT5_EO_PG                         , RULL(0x800AD8200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_STAT5_EO_PG                         , RULL(0x800AD8200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_STAT7_E_PG                            , RULL(0x800B482006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_STAT7_E_PG                          , RULL(0x800B48200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_STAT7_E_PG                          , RULL(0x800B48200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_STAT8_E_PG                            , RULL(0x800B502006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_STAT8_E_PG                          , RULL(0x800B50200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_STAT8_E_PG                          , RULL(0x800B50200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_GLBSM_STAT9_E_PG                            , RULL(0x800B582006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_GLBSM_STAT9_E_PG                          , RULL(0x800B58200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_GLBSM_STAT9_E_PG                          , RULL(0x800B58200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_ID1_PG                                      , RULL(0x8008082006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_ID1_PG                                    , RULL(0x800808200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_ID1_PG                                    , RULL(0x800808200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_ID2_PG                                      , RULL(0x8009802006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_ID2_PG                                    , RULL(0x800980200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_ID2_PG                                    , RULL(0x800980200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_RX_SPARE_MODE_PG                               , RULL(0x8008002006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_RX_SPARE_MODE_PG                             , RULL(0x800800200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_RX_SPARE_MODE_PG                             , RULL(0x800800200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003802106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE0_RX_WORK_STAT1_EO_PL                     , RULL(0x8003882106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL                   , RULL(0x800388210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE0_RX_WORK_STAT1_EO_PL                   , RULL(0x800388210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE0_RX_WORK_STAT2_EO_PL                     , RULL(0x8003902106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE0_RX_WORK_STAT2_EO_PL                   , RULL(0x800390210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE0_RX_WORK_STAT2_EO_PL                   , RULL(0x800390210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE0_RX_WORK_STAT3_EO_PL                     , RULL(0x8003982106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE0_RX_WORK_STAT3_EO_PL                   , RULL(0x800398210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE0_RX_WORK_STAT3_EO_PL                   , RULL(0x800398210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003802906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE10_RX_WORK_STAT1_EO_PL                    , RULL(0x8003882906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL                  , RULL(0x800388290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE10_RX_WORK_STAT1_EO_PL                  , RULL(0x800388290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE10_RX_WORK_STAT2_EO_PL                    , RULL(0x8003902906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE10_RX_WORK_STAT2_EO_PL                  , RULL(0x800390290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE10_RX_WORK_STAT2_EO_PL                  , RULL(0x800390290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE10_RX_WORK_STAT3_EO_PL                    , RULL(0x8003982906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE10_RX_WORK_STAT3_EO_PL                  , RULL(0x800398290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE10_RX_WORK_STAT3_EO_PL                  , RULL(0x800398290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003803106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE11_RX_WORK_STAT1_EO_PL                    , RULL(0x8003883106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL                  , RULL(0x800388310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE11_RX_WORK_STAT1_EO_PL                  , RULL(0x800388310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE11_RX_WORK_STAT2_EO_PL                    , RULL(0x8003903106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE11_RX_WORK_STAT2_EO_PL                  , RULL(0x800390310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE11_RX_WORK_STAT2_EO_PL                  , RULL(0x800390310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE11_RX_WORK_STAT3_EO_PL                    , RULL(0x8003983106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE11_RX_WORK_STAT3_EO_PL                  , RULL(0x800398310601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE11_RX_WORK_STAT3_EO_PL                  , RULL(0x800398310601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003802E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003802E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003802E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE12_RX_WORK_STAT1_EO_PL                    , RULL(0x8003882E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL                  , RULL(0x8003882E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE12_RX_WORK_STAT1_EO_PL                  , RULL(0x8003882E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE12_RX_WORK_STAT2_EO_PL                    , RULL(0x8003902E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE12_RX_WORK_STAT2_EO_PL                  , RULL(0x8003902E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE12_RX_WORK_STAT2_EO_PL                  , RULL(0x8003902E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE12_RX_WORK_STAT3_EO_PL                    , RULL(0x8003982E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE12_RX_WORK_STAT3_EO_PL                  , RULL(0x8003982E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE12_RX_WORK_STAT3_EO_PL                  , RULL(0x8003982E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003802C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003802C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003802C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE13_RX_WORK_STAT1_EO_PL                    , RULL(0x8003882C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL                  , RULL(0x8003882C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE13_RX_WORK_STAT1_EO_PL                  , RULL(0x8003882C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE13_RX_WORK_STAT2_EO_PL                    , RULL(0x8003902C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE13_RX_WORK_STAT2_EO_PL                  , RULL(0x8003902C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE13_RX_WORK_STAT2_EO_PL                  , RULL(0x8003902C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE13_RX_WORK_STAT3_EO_PL                    , RULL(0x8003982C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE13_RX_WORK_STAT3_EO_PL                  , RULL(0x8003982C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE13_RX_WORK_STAT3_EO_PL                  , RULL(0x8003982C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003802D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003802D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003802D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE14_RX_WORK_STAT1_EO_PL                    , RULL(0x8003882D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL                  , RULL(0x8003882D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE14_RX_WORK_STAT1_EO_PL                  , RULL(0x8003882D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE14_RX_WORK_STAT2_EO_PL                    , RULL(0x8003902D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE14_RX_WORK_STAT2_EO_PL                  , RULL(0x8003902D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE14_RX_WORK_STAT2_EO_PL                  , RULL(0x8003902D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE14_RX_WORK_STAT3_EO_PL                    , RULL(0x8003982D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE14_RX_WORK_STAT3_EO_PL                  , RULL(0x8003982D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE14_RX_WORK_STAT3_EO_PL                  , RULL(0x8003982D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003802B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003802B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003802B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE15_RX_WORK_STAT1_EO_PL                    , RULL(0x8003882B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL                  , RULL(0x8003882B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE15_RX_WORK_STAT1_EO_PL                  , RULL(0x8003882B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE15_RX_WORK_STAT2_EO_PL                    , RULL(0x8003902B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE15_RX_WORK_STAT2_EO_PL                  , RULL(0x8003902B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE15_RX_WORK_STAT2_EO_PL                  , RULL(0x8003902B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE15_RX_WORK_STAT3_EO_PL                    , RULL(0x8003982B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE15_RX_WORK_STAT3_EO_PL                  , RULL(0x8003982B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE15_RX_WORK_STAT3_EO_PL                  , RULL(0x8003982B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003802F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003802F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x8003802F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE16_RX_WORK_STAT1_EO_PL                    , RULL(0x8003882F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL                  , RULL(0x8003882F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE16_RX_WORK_STAT1_EO_PL                  , RULL(0x8003882F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE16_RX_WORK_STAT2_EO_PL                    , RULL(0x8003902F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE16_RX_WORK_STAT2_EO_PL                  , RULL(0x8003902F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE16_RX_WORK_STAT2_EO_PL                  , RULL(0x8003902F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE16_RX_WORK_STAT3_EO_PL                    , RULL(0x8003982F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE16_RX_WORK_STAT3_EO_PL                  , RULL(0x8003982F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE16_RX_WORK_STAT3_EO_PL                  , RULL(0x8003982F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003803006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE17_RX_WORK_STAT1_EO_PL                    , RULL(0x8003883006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL                  , RULL(0x800388300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE17_RX_WORK_STAT1_EO_PL                  , RULL(0x800388300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE17_RX_WORK_STAT2_EO_PL                    , RULL(0x8003903006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE17_RX_WORK_STAT2_EO_PL                  , RULL(0x800390300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE17_RX_WORK_STAT2_EO_PL                  , RULL(0x800390300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE17_RX_WORK_STAT3_EO_PL                    , RULL(0x8003983006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE17_RX_WORK_STAT3_EO_PL                  , RULL(0x800398300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE17_RX_WORK_STAT3_EO_PL                  , RULL(0x800398300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003803206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380320601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380320601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE18_RX_WORK_STAT1_EO_PL                    , RULL(0x8003883206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL                  , RULL(0x800388320601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE18_RX_WORK_STAT1_EO_PL                  , RULL(0x800388320601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE18_RX_WORK_STAT2_EO_PL                    , RULL(0x8003903206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE18_RX_WORK_STAT2_EO_PL                  , RULL(0x800390320601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE18_RX_WORK_STAT2_EO_PL                  , RULL(0x800390320601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE18_RX_WORK_STAT3_EO_PL                    , RULL(0x8003983206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE18_RX_WORK_STAT3_EO_PL                  , RULL(0x800398320601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE18_RX_WORK_STAT3_EO_PL                  , RULL(0x800398320601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003803306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380330601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380330601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE19_RX_WORK_STAT1_EO_PL                    , RULL(0x8003883306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL                  , RULL(0x800388330601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE19_RX_WORK_STAT1_EO_PL                  , RULL(0x800388330601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE19_RX_WORK_STAT2_EO_PL                    , RULL(0x8003903306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE19_RX_WORK_STAT2_EO_PL                  , RULL(0x800390330601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE19_RX_WORK_STAT2_EO_PL                  , RULL(0x800390330601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE19_RX_WORK_STAT3_EO_PL                    , RULL(0x8003983306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE19_RX_WORK_STAT3_EO_PL                  , RULL(0x800398330601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE19_RX_WORK_STAT3_EO_PL                  , RULL(0x800398330601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003802306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE1_RX_WORK_STAT1_EO_PL                     , RULL(0x8003882306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL                   , RULL(0x800388230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE1_RX_WORK_STAT1_EO_PL                   , RULL(0x800388230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE1_RX_WORK_STAT2_EO_PL                     , RULL(0x8003902306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE1_RX_WORK_STAT2_EO_PL                   , RULL(0x800390230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE1_RX_WORK_STAT2_EO_PL                   , RULL(0x800390230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE1_RX_WORK_STAT3_EO_PL                     , RULL(0x8003982306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE1_RX_WORK_STAT3_EO_PL                   , RULL(0x800398230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE1_RX_WORK_STAT3_EO_PL                   , RULL(0x800398230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003803406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380340601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380340601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE20_RX_WORK_STAT1_EO_PL                    , RULL(0x8003883406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL                  , RULL(0x800388340601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE20_RX_WORK_STAT1_EO_PL                  , RULL(0x800388340601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE20_RX_WORK_STAT2_EO_PL                    , RULL(0x8003903406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE20_RX_WORK_STAT2_EO_PL                  , RULL(0x800390340601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE20_RX_WORK_STAT2_EO_PL                  , RULL(0x800390340601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE20_RX_WORK_STAT3_EO_PL                    , RULL(0x8003983406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE20_RX_WORK_STAT3_EO_PL                  , RULL(0x800398340601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE20_RX_WORK_STAT3_EO_PL                  , RULL(0x800398340601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003803506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380350601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380350601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE21_RX_WORK_STAT1_EO_PL                    , RULL(0x8003883506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL                  , RULL(0x800388350601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE21_RX_WORK_STAT1_EO_PL                  , RULL(0x800388350601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE21_RX_WORK_STAT2_EO_PL                    , RULL(0x8003903506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE21_RX_WORK_STAT2_EO_PL                  , RULL(0x800390350601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE21_RX_WORK_STAT2_EO_PL                  , RULL(0x800390350601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE21_RX_WORK_STAT3_EO_PL                    , RULL(0x8003983506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE21_RX_WORK_STAT3_EO_PL                  , RULL(0x800398350601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE21_RX_WORK_STAT3_EO_PL                  , RULL(0x800398350601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003803606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380360601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380360601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE22_RX_WORK_STAT1_EO_PL                    , RULL(0x8003883606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL                  , RULL(0x800388360601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE22_RX_WORK_STAT1_EO_PL                  , RULL(0x800388360601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE22_RX_WORK_STAT2_EO_PL                    , RULL(0x8003903606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE22_RX_WORK_STAT2_EO_PL                  , RULL(0x800390360601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE22_RX_WORK_STAT2_EO_PL                  , RULL(0x800390360601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE22_RX_WORK_STAT3_EO_PL                    , RULL(0x8003983606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE22_RX_WORK_STAT3_EO_PL                  , RULL(0x800398360601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE22_RX_WORK_STAT3_EO_PL                  , RULL(0x800398360601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL             , RULL(0x8003803706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380370601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL           , RULL(0x800380370601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE23_RX_WORK_STAT1_EO_PL                    , RULL(0x8003883706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL                  , RULL(0x800388370601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE23_RX_WORK_STAT1_EO_PL                  , RULL(0x800388370601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE23_RX_WORK_STAT2_EO_PL                    , RULL(0x8003903706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE23_RX_WORK_STAT2_EO_PL                  , RULL(0x800390370601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE23_RX_WORK_STAT2_EO_PL                  , RULL(0x800390370601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE23_RX_WORK_STAT3_EO_PL                    , RULL(0x8003983706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE23_RX_WORK_STAT3_EO_PL                  , RULL(0x800398370601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE23_RX_WORK_STAT3_EO_PL                  , RULL(0x800398370601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003802006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE2_RX_WORK_STAT1_EO_PL                     , RULL(0x8003882006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL                   , RULL(0x800388200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE2_RX_WORK_STAT1_EO_PL                   , RULL(0x800388200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE2_RX_WORK_STAT2_EO_PL                     , RULL(0x8003902006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE2_RX_WORK_STAT2_EO_PL                   , RULL(0x800390200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE2_RX_WORK_STAT2_EO_PL                   , RULL(0x800390200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE2_RX_WORK_STAT3_EO_PL                     , RULL(0x8003982006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE2_RX_WORK_STAT3_EO_PL                   , RULL(0x800398200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE2_RX_WORK_STAT3_EO_PL                   , RULL(0x800398200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003802206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE3_RX_WORK_STAT1_EO_PL                     , RULL(0x8003882206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL                   , RULL(0x800388220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE3_RX_WORK_STAT1_EO_PL                   , RULL(0x800388220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE3_RX_WORK_STAT2_EO_PL                     , RULL(0x8003902206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE3_RX_WORK_STAT2_EO_PL                   , RULL(0x800390220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE3_RX_WORK_STAT2_EO_PL                   , RULL(0x800390220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE3_RX_WORK_STAT3_EO_PL                     , RULL(0x8003982206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE3_RX_WORK_STAT3_EO_PL                   , RULL(0x800398220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE3_RX_WORK_STAT3_EO_PL                   , RULL(0x800398220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003802706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE4_RX_WORK_STAT1_EO_PL                     , RULL(0x8003882706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL                   , RULL(0x800388270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE4_RX_WORK_STAT1_EO_PL                   , RULL(0x800388270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE4_RX_WORK_STAT2_EO_PL                     , RULL(0x8003902706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE4_RX_WORK_STAT2_EO_PL                   , RULL(0x800390270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE4_RX_WORK_STAT2_EO_PL                   , RULL(0x800390270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE4_RX_WORK_STAT3_EO_PL                     , RULL(0x8003982706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE4_RX_WORK_STAT3_EO_PL                   , RULL(0x800398270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE4_RX_WORK_STAT3_EO_PL                   , RULL(0x800398270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003802506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE5_RX_WORK_STAT1_EO_PL                     , RULL(0x8003882506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL                   , RULL(0x800388250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE5_RX_WORK_STAT1_EO_PL                   , RULL(0x800388250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE5_RX_WORK_STAT2_EO_PL                     , RULL(0x8003902506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE5_RX_WORK_STAT2_EO_PL                   , RULL(0x800390250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE5_RX_WORK_STAT2_EO_PL                   , RULL(0x800390250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE5_RX_WORK_STAT3_EO_PL                     , RULL(0x8003982506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE5_RX_WORK_STAT3_EO_PL                   , RULL(0x800398250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE5_RX_WORK_STAT3_EO_PL                   , RULL(0x800398250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003802606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE6_RX_WORK_STAT1_EO_PL                     , RULL(0x8003882606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL                   , RULL(0x800388260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE6_RX_WORK_STAT1_EO_PL                   , RULL(0x800388260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE6_RX_WORK_STAT2_EO_PL                     , RULL(0x8003902606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE6_RX_WORK_STAT2_EO_PL                   , RULL(0x800390260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE6_RX_WORK_STAT2_EO_PL                   , RULL(0x800390260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE6_RX_WORK_STAT3_EO_PL                     , RULL(0x8003982606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE6_RX_WORK_STAT3_EO_PL                   , RULL(0x800398260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE6_RX_WORK_STAT3_EO_PL                   , RULL(0x800398260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003802406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE7_RX_WORK_STAT1_EO_PL                     , RULL(0x8003882406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL                   , RULL(0x800388240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE7_RX_WORK_STAT1_EO_PL                   , RULL(0x800388240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE7_RX_WORK_STAT2_EO_PL                     , RULL(0x8003902406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE7_RX_WORK_STAT2_EO_PL                   , RULL(0x800390240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE7_RX_WORK_STAT2_EO_PL                   , RULL(0x800390240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE7_RX_WORK_STAT3_EO_PL                     , RULL(0x8003982406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE7_RX_WORK_STAT3_EO_PL                   , RULL(0x800398240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE7_RX_WORK_STAT3_EO_PL                   , RULL(0x800398240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003802806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x800380280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE8_RX_WORK_STAT1_EO_PL                     , RULL(0x8003882806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL                   , RULL(0x800388280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE8_RX_WORK_STAT1_EO_PL                   , RULL(0x800388280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE8_RX_WORK_STAT2_EO_PL                     , RULL(0x8003902806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE8_RX_WORK_STAT2_EO_PL                   , RULL(0x800390280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE8_RX_WORK_STAT2_EO_PL                   , RULL(0x800390280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE8_RX_WORK_STAT3_EO_PL                     , RULL(0x8003982806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE8_RX_WORK_STAT3_EO_PL                   , RULL(0x800398280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE8_RX_WORK_STAT3_EO_PL                   , RULL(0x800398280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL              , RULL(0x8003802A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003802A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL            , RULL(0x8003802A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE9_RX_WORK_STAT1_EO_PL                     , RULL(0x8003882A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL                   , RULL(0x8003882A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE9_RX_WORK_STAT1_EO_PL                   , RULL(0x8003882A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE9_RX_WORK_STAT2_EO_PL                     , RULL(0x8003902A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE9_RX_WORK_STAT2_EO_PL                   , RULL(0x8003902A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE9_RX_WORK_STAT2_EO_PL                   , RULL(0x8003902A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX1_SLICE9_RX_WORK_STAT3_EO_PL                     , RULL(0x8003982A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX1_SLICE9_RX_WORK_STAT3_EO_PL                   , RULL(0x8003982A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX1_SLICE9_RX_WORK_STAT3_EO_PL                   , RULL(0x8003982A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX_FIR_ERROR_INJECT_PB                             , RULL(0x800F980006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX_FIR_ERROR_INJECT_PB                           , RULL(0x800F98000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX_FIR_ERROR_INJECT_PB                           , RULL(0x800F98000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX_FIR_MASK_PB                                     , RULL(0x800F900006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX_FIR_MASK_PB                                   , RULL(0x800F90000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX_FIR_MASK_PB                                   , RULL(0x800F90000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX_FIR_PB                                          , RULL(0x800F880006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX_FIR_PB                                        , RULL(0x800F88000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX_FIR_PB                                        , RULL(0x800F88000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_RX_FIR_RESET_PB                                    , RULL(0x800F800006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_RX_FIR_RESET_PB                                  , RULL(0x800F80000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_RX_FIR_RESET_PB                                  , RULL(0x800F80000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_SCOM_MODE_PB                                       , RULL(0x06010C20), SH_UNT_XBUS     , SH_ACS_SCOM      );
+REG64( XBUS_1_SCOM_MODE_PB                                     , RULL(0x06011020), SH_UNT_XBUS_1   , SH_ACS_SCOM      );
+REG64( XBUS_2_SCOM_MODE_PB                                     , RULL(0x06011420), SH_UNT_XBUS_2   , SH_ACS_SCOM      );
+
+REG64( XBUS_IOPPE_SCOM_PPE_CNTL                                , RULL(0x06010860), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_IOPPE_SCOM_PPE_FLAGS                               , RULL(0x06010863), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM_RW   );
+REG64( XBUS_IOPPE_SCOM_PPE_FLAGS_OR                            , RULL(0x06010864), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM1_OR  );
+REG64( XBUS_IOPPE_SCOM_PPE_FLAGS_CLEAR                         , RULL(0x06010865), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM2_CLEAR );
+
+REG64( XBUS_IOPPE_SCOM_PPE_WORK_REG1                           , RULL(0x06010861), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_IOPPE_SCOM_PPE_WORK_REG2                           , RULL(0x06010862), SH_UNT_XBUS_IOPPE,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_SPARE_MODE_PB                                      , RULL(0x800F340006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_SPARE_MODE_PB                                    , RULL(0x800F34000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_SPARE_MODE_PB                                    , RULL(0x800F34000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR0_TRACE_HI_DATA_REG               , RULL(0x06010400), SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO   );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR0_TRACE_LO_DATA_REG               , RULL(0x06010401), SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO   );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG             , RULL(0x06010402), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_0           , RULL(0x06010403), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_1           , RULL(0x06010404), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_2           , RULL(0x06010405), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_3           , RULL(0x06010406), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_4           , RULL(0x06010407), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_5           , RULL(0x06010408), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9           , RULL(0x06010409), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR1_TRACE_HI_DATA_REG               , RULL(0x06010440), SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO   );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR1_TRACE_LO_DATA_REG               , RULL(0x06010441), SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO   );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG             , RULL(0x06010442), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_0           , RULL(0x06010443), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_1           , RULL(0x06010444), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_2           , RULL(0x06010445), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_3           , RULL(0x06010446), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_4           , RULL(0x06010447), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_5           , RULL(0x06010448), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9           , RULL(0x06010449), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA1_TR0_TRACE_HI_DATA_REG               , RULL(0x06010480), SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO   );
+
+REG64( XBUS_PERV_TCXB_TRA1_TR0_TRACE_LO_DATA_REG               , RULL(0x06010481), SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO   );
+
+REG64( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG             , RULL(0x06010482), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_0           , RULL(0x06010483), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_1           , RULL(0x06010484), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_2           , RULL(0x06010485), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_3           , RULL(0x06010486), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_4           , RULL(0x06010487), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_5           , RULL(0x06010488), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9           , RULL(0x06010489), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL              , RULL(0x80043C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL              , RULL(0x8004440006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x800444000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x800444000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL                   , RULL(0x8004140006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL                 , RULL(0x8004540006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL                 , RULL(0x80042C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE0_TX_FIR_PL                      , RULL(0x8004240006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE0_TX_FIR_PL                    , RULL(0x800424000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE0_TX_FIR_PL                    , RULL(0x800424000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE0_TX_MODE1_PL                    , RULL(0x8004040006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL                  , RULL(0x800404000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE0_TX_MODE1_PL                  , RULL(0x800404000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE0_TX_MODE2_PL                    , RULL(0x80040C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL                  , RULL(0x80040C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE0_TX_MODE2_PL                  , RULL(0x80040C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE0_TX_STAT1_PL                    , RULL(0x80041C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL                  , RULL(0x80041C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE0_TX_STAT1_PL                  , RULL(0x80041C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL              , RULL(0x80043C0106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL              , RULL(0x8004440106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x800444010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x800444010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL                   , RULL(0x8004140106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL                 , RULL(0x8004540106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL                 , RULL(0x80042C0106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE1_TX_FIR_PL                      , RULL(0x8004240106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE1_TX_FIR_PL                    , RULL(0x800424010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE1_TX_FIR_PL                    , RULL(0x800424010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE1_TX_MODE1_PL                    , RULL(0x8004040106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL                  , RULL(0x800404010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE1_TX_MODE1_PL                  , RULL(0x800404010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE1_TX_MODE2_PL                    , RULL(0x80040C0106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL                  , RULL(0x80040C010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE1_TX_MODE2_PL                  , RULL(0x80040C010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE1_TX_STAT1_PL                    , RULL(0x80041C0106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL                  , RULL(0x80041C010601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE1_TX_STAT1_PL                  , RULL(0x80041C010601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL              , RULL(0x80043C0206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL              , RULL(0x8004440206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x800444020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x800444020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL                   , RULL(0x8004140206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL                 , RULL(0x800414020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE2_TX_CNTL1G_PL                 , RULL(0x800414020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL                 , RULL(0x8004540206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL               , RULL(0x800454020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL               , RULL(0x800454020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL                 , RULL(0x80042C0206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE2_TX_FIR_PL                      , RULL(0x8004240206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE2_TX_FIR_PL                    , RULL(0x800424020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE2_TX_FIR_PL                    , RULL(0x800424020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE2_TX_MODE1_PL                    , RULL(0x8004040206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL                  , RULL(0x800404020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE2_TX_MODE1_PL                  , RULL(0x800404020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE2_TX_MODE2_PL                    , RULL(0x80040C0206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL                  , RULL(0x80040C020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE2_TX_MODE2_PL                  , RULL(0x80040C020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE2_TX_STAT1_PL                    , RULL(0x80041C0206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL                  , RULL(0x80041C020601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE2_TX_STAT1_PL                  , RULL(0x80041C020601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL              , RULL(0x80043C0306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL              , RULL(0x8004440306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x800444030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x800444030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL                   , RULL(0x8004140306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL                 , RULL(0x800414030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE3_TX_CNTL1G_PL                 , RULL(0x800414030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL                 , RULL(0x8004540306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL               , RULL(0x800454030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL               , RULL(0x800454030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL                 , RULL(0x80042C0306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE3_TX_FIR_PL                      , RULL(0x8004240306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE3_TX_FIR_PL                    , RULL(0x800424030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE3_TX_FIR_PL                    , RULL(0x800424030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE3_TX_MODE1_PL                    , RULL(0x8004040306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL                  , RULL(0x800404030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE3_TX_MODE1_PL                  , RULL(0x800404030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE3_TX_MODE2_PL                    , RULL(0x80040C0306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL                  , RULL(0x80040C030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE3_TX_MODE2_PL                  , RULL(0x80040C030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS0_SLICE3_TX_STAT1_PL                    , RULL(0x80041C0306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL                  , RULL(0x80041C030601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS0_SLICE3_TX_STAT1_PL                  , RULL(0x80041C030601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL              , RULL(0x80043C0406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL              , RULL(0x8004440406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x800444040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x800444040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL                   , RULL(0x8004140406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL                 , RULL(0x8004540406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL                 , RULL(0x80042C0406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE0_TX_FIR_PL                      , RULL(0x8004240406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE0_TX_FIR_PL                    , RULL(0x800424040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE0_TX_FIR_PL                    , RULL(0x800424040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE0_TX_MODE1_PL                    , RULL(0x8004040406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL                  , RULL(0x800404040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE0_TX_MODE1_PL                  , RULL(0x800404040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE0_TX_MODE2_PL                    , RULL(0x80040C0406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL                  , RULL(0x80040C040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE0_TX_MODE2_PL                  , RULL(0x80040C040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE0_TX_STAT1_PL                    , RULL(0x80041C0406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL                  , RULL(0x80041C040601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE0_TX_STAT1_PL                  , RULL(0x80041C040601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL              , RULL(0x80043C0506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL              , RULL(0x8004440506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x800444050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x800444050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL                   , RULL(0x8004140506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL                 , RULL(0x8004540506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL                 , RULL(0x80042C0506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE1_TX_FIR_PL                      , RULL(0x8004240506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE1_TX_FIR_PL                    , RULL(0x800424050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE1_TX_FIR_PL                    , RULL(0x800424050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE1_TX_MODE1_PL                    , RULL(0x8004040506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL                  , RULL(0x800404050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE1_TX_MODE1_PL                  , RULL(0x800404050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE1_TX_MODE2_PL                    , RULL(0x80040C0506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL                  , RULL(0x80040C050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE1_TX_MODE2_PL                  , RULL(0x80040C050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE1_TX_STAT1_PL                    , RULL(0x80041C0506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL                  , RULL(0x80041C050601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE1_TX_STAT1_PL                  , RULL(0x80041C050601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL              , RULL(0x80043C0606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL              , RULL(0x8004440606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x800444060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x800444060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL                   , RULL(0x8004140606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL                 , RULL(0x800414060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE2_TX_CNTL1G_PL                 , RULL(0x800414060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL                 , RULL(0x8004540606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL               , RULL(0x800454060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL               , RULL(0x800454060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL                 , RULL(0x80042C0606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE2_TX_FIR_PL                      , RULL(0x8004240606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE2_TX_FIR_PL                    , RULL(0x800424060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE2_TX_FIR_PL                    , RULL(0x800424060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE2_TX_MODE1_PL                    , RULL(0x8004040606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL                  , RULL(0x800404060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE2_TX_MODE1_PL                  , RULL(0x800404060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE2_TX_MODE2_PL                    , RULL(0x80040C0606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL                  , RULL(0x80040C060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE2_TX_MODE2_PL                  , RULL(0x80040C060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE2_TX_STAT1_PL                    , RULL(0x80041C0606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL                  , RULL(0x80041C060601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE2_TX_STAT1_PL                  , RULL(0x80041C060601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL              , RULL(0x80043C0706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL              , RULL(0x8004440706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x800444070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x800444070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL                   , RULL(0x8004140706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL                 , RULL(0x800414070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE3_TX_CNTL1G_PL                 , RULL(0x800414070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL                 , RULL(0x8004540706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL               , RULL(0x800454070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL               , RULL(0x800454070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL                 , RULL(0x80042C0706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE3_TX_FIR_PL                      , RULL(0x8004240706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE3_TX_FIR_PL                    , RULL(0x800424070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE3_TX_FIR_PL                    , RULL(0x800424070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE3_TX_MODE1_PL                    , RULL(0x8004040706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL                  , RULL(0x800404070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE3_TX_MODE1_PL                  , RULL(0x800404070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE3_TX_MODE2_PL                    , RULL(0x80040C0706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL                  , RULL(0x80040C070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE3_TX_MODE2_PL                  , RULL(0x80040C070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS1_SLICE3_TX_STAT1_PL                    , RULL(0x80041C0706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL                  , RULL(0x80041C070601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS1_SLICE3_TX_STAT1_PL                  , RULL(0x80041C070601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL              , RULL(0x80043C0806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL              , RULL(0x8004440806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x800444080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x800444080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL                   , RULL(0x8004140806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL                 , RULL(0x8004540806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL                 , RULL(0x80042C0806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE0_TX_FIR_PL                      , RULL(0x8004240806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE0_TX_FIR_PL                    , RULL(0x800424080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE0_TX_FIR_PL                    , RULL(0x800424080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE0_TX_MODE1_PL                    , RULL(0x8004040806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL                  , RULL(0x800404080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE0_TX_MODE1_PL                  , RULL(0x800404080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE0_TX_MODE2_PL                    , RULL(0x80040C0806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL                  , RULL(0x80040C080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE0_TX_MODE2_PL                  , RULL(0x80040C080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE0_TX_STAT1_PL                    , RULL(0x80041C0806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL                  , RULL(0x80041C080601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE0_TX_STAT1_PL                  , RULL(0x80041C080601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL              , RULL(0x80043C0906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL              , RULL(0x8004440906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x800444090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x800444090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL                   , RULL(0x8004140906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL                 , RULL(0x8004540906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL                 , RULL(0x80042C0906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE1_TX_FIR_PL                      , RULL(0x8004240906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE1_TX_FIR_PL                    , RULL(0x800424090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE1_TX_FIR_PL                    , RULL(0x800424090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE1_TX_MODE1_PL                    , RULL(0x8004040906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL                  , RULL(0x800404090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE1_TX_MODE1_PL                  , RULL(0x800404090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE1_TX_MODE2_PL                    , RULL(0x80040C0906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL                  , RULL(0x80040C090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE1_TX_MODE2_PL                  , RULL(0x80040C090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE1_TX_STAT1_PL                    , RULL(0x80041C0906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL                  , RULL(0x80041C090601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE1_TX_STAT1_PL                  , RULL(0x80041C090601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL              , RULL(0x80043C0A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C0A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C0A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL              , RULL(0x8004440A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x8004440A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x8004440A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL                   , RULL(0x8004140A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004140A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004140A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL                 , RULL(0x8004540A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004540A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004540A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL                 , RULL(0x80042C0A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C0A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C0A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE2_TX_FIR_PL                      , RULL(0x8004240A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE2_TX_FIR_PL                    , RULL(0x8004240A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE2_TX_FIR_PL                    , RULL(0x8004240A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE2_TX_MODE1_PL                    , RULL(0x8004040A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL                  , RULL(0x8004040A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE2_TX_MODE1_PL                  , RULL(0x8004040A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE2_TX_MODE2_PL                    , RULL(0x80040C0A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL                  , RULL(0x80040C0A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE2_TX_MODE2_PL                  , RULL(0x80040C0A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE2_TX_STAT1_PL                    , RULL(0x80041C0A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL                  , RULL(0x80041C0A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE2_TX_STAT1_PL                  , RULL(0x80041C0A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL              , RULL(0x80043C0B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C0B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C0B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL              , RULL(0x8004440B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x8004440B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x8004440B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL                   , RULL(0x8004140B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004140B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004140B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL                 , RULL(0x8004540B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004540B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004540B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL                 , RULL(0x80042C0B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C0B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C0B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE3_TX_FIR_PL                      , RULL(0x8004240B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE3_TX_FIR_PL                    , RULL(0x8004240B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE3_TX_FIR_PL                    , RULL(0x8004240B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE3_TX_MODE1_PL                    , RULL(0x8004040B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL                  , RULL(0x8004040B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE3_TX_MODE1_PL                  , RULL(0x8004040B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE3_TX_MODE2_PL                    , RULL(0x80040C0B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL                  , RULL(0x80040C0B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE3_TX_MODE2_PL                  , RULL(0x80040C0B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS2_SLICE3_TX_STAT1_PL                    , RULL(0x80041C0B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL                  , RULL(0x80041C0B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS2_SLICE3_TX_STAT1_PL                  , RULL(0x80041C0B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL              , RULL(0x80043C0C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C0C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C0C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL              , RULL(0x8004440C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x8004440C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x8004440C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL                   , RULL(0x8004140C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL                 , RULL(0x8004140C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE0_TX_CNTL1G_PL                 , RULL(0x8004140C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL                 , RULL(0x8004540C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL               , RULL(0x8004540C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL               , RULL(0x8004540C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL                 , RULL(0x80042C0C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C0C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C0C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE0_TX_FIR_PL                      , RULL(0x8004240C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE0_TX_FIR_PL                    , RULL(0x8004240C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE0_TX_FIR_PL                    , RULL(0x8004240C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE0_TX_MODE1_PL                    , RULL(0x8004040C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL                  , RULL(0x8004040C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE0_TX_MODE1_PL                  , RULL(0x8004040C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE0_TX_MODE2_PL                    , RULL(0x80040C0C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL                  , RULL(0x80040C0C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE0_TX_MODE2_PL                  , RULL(0x80040C0C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE0_TX_STAT1_PL                    , RULL(0x80041C0C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL                  , RULL(0x80041C0C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE0_TX_STAT1_PL                  , RULL(0x80041C0C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL              , RULL(0x80043C0D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C0D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C0D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL              , RULL(0x8004440D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x8004440D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x8004440D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL                   , RULL(0x8004140D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL                 , RULL(0x8004140D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE1_TX_CNTL1G_PL                 , RULL(0x8004140D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL                 , RULL(0x8004540D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL               , RULL(0x8004540D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL               , RULL(0x8004540D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL                 , RULL(0x80042C0D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C0D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C0D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE1_TX_FIR_PL                      , RULL(0x8004240D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE1_TX_FIR_PL                    , RULL(0x8004240D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE1_TX_FIR_PL                    , RULL(0x8004240D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE1_TX_MODE1_PL                    , RULL(0x8004040D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL                  , RULL(0x8004040D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE1_TX_MODE1_PL                  , RULL(0x8004040D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE1_TX_MODE2_PL                    , RULL(0x80040C0D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL                  , RULL(0x80040C0D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE1_TX_MODE2_PL                  , RULL(0x80040C0D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE1_TX_STAT1_PL                    , RULL(0x80041C0D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL                  , RULL(0x80041C0D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE1_TX_STAT1_PL                  , RULL(0x80041C0D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL              , RULL(0x80043C0E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C0E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C0E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL              , RULL(0x8004440E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x8004440E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x8004440E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL                   , RULL(0x8004140E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004140E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004140E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL                 , RULL(0x8004540E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004540E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004540E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL                 , RULL(0x80042C0E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C0E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C0E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE2_TX_FIR_PL                      , RULL(0x8004240E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE2_TX_FIR_PL                    , RULL(0x8004240E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE2_TX_FIR_PL                    , RULL(0x8004240E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE2_TX_MODE1_PL                    , RULL(0x8004040E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL                  , RULL(0x8004040E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE2_TX_MODE1_PL                  , RULL(0x8004040E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE2_TX_MODE2_PL                    , RULL(0x80040C0E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL                  , RULL(0x80040C0E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE2_TX_MODE2_PL                  , RULL(0x80040C0E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE2_TX_STAT1_PL                    , RULL(0x80041C0E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL                  , RULL(0x80041C0E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE2_TX_STAT1_PL                  , RULL(0x80041C0E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL              , RULL(0x80043C0F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C0F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C0F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL              , RULL(0x8004440F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x8004440F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x8004440F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL                   , RULL(0x8004140F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004140F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004140F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL                 , RULL(0x8004540F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004540F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004540F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004340F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004340F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL                 , RULL(0x80042C0F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C0F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C0F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE3_TX_FIR_PL                      , RULL(0x8004240F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE3_TX_FIR_PL                    , RULL(0x8004240F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE3_TX_FIR_PL                    , RULL(0x8004240F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE3_TX_MODE1_PL                    , RULL(0x8004040F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL                  , RULL(0x8004040F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE3_TX_MODE1_PL                  , RULL(0x8004040F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE3_TX_MODE2_PL                    , RULL(0x80040C0F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL                  , RULL(0x80040C0F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE3_TX_MODE2_PL                  , RULL(0x80040C0F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE3_TX_STAT1_PL                    , RULL(0x80041C0F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL                  , RULL(0x80041C0F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE3_TX_STAT1_PL                  , RULL(0x80041C0F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL              , RULL(0x80043C1006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL            , RULL(0x80043C100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL            , RULL(0x80043C100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL              , RULL(0x8004441006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL            , RULL(0x800444100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL            , RULL(0x800444100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL                   , RULL(0x8004141006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL                 , RULL(0x800414100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE4_TX_CNTL1G_PL                 , RULL(0x800414100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE4_TX_CNTL3_EO_PL                 , RULL(0x8004541006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE4_TX_CNTL3_EO_PL               , RULL(0x800454100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE4_TX_CNTL3_EO_PL               , RULL(0x800454100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004341006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE4_TX_FIR_MASK_PL                 , RULL(0x80042C1006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE4_TX_FIR_MASK_PL               , RULL(0x80042C100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE4_TX_FIR_MASK_PL               , RULL(0x80042C100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE4_TX_FIR_PL                      , RULL(0x8004241006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE4_TX_FIR_PL                    , RULL(0x800424100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE4_TX_FIR_PL                    , RULL(0x800424100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE4_TX_MODE1_PL                    , RULL(0x8004041006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL                  , RULL(0x800404100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE4_TX_MODE1_PL                  , RULL(0x800404100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE4_TX_MODE2_PL                    , RULL(0x80040C1006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL                  , RULL(0x80040C100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE4_TX_MODE2_PL                  , RULL(0x80040C100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TXPACKS3_SLICE4_TX_STAT1_PL                    , RULL(0x80041C1006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL                  , RULL(0x80041C100601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TXPACKS3_SLICE4_TX_STAT1_PL                  , RULL(0x80041C100601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTLSM_CNTL1_EO_PG                           , RULL(0x800D340006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTLSM_CNTL1_EO_PG                         , RULL(0x800D34000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTLSM_CNTL1_EO_PG                         , RULL(0x800D34000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTLSM_CNTL2_EO_PG                           , RULL(0x800D3C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTLSM_CNTL2_EO_PG                         , RULL(0x800D3C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTLSM_CNTL2_EO_PG                         , RULL(0x800D3C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTLSM_CNTL3_EO_PG                           , RULL(0x800D440006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTLSM_CNTL3_EO_PG                         , RULL(0x800D44000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTLSM_CNTL3_EO_PG                         , RULL(0x800D44000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTLSM_CNTL4_EO_PG                           , RULL(0x800D4C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTLSM_CNTL4_EO_PG                         , RULL(0x800D4C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTLSM_CNTL4_EO_PG                         , RULL(0x800D4C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTLSM_CNTL5_EO_PG                           , RULL(0x800D540006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTLSM_CNTL5_EO_PG                         , RULL(0x800D54000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTLSM_CNTL5_EO_PG                         , RULL(0x800D54000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTLSM_CNTL6_EO_PG                           , RULL(0x800D5C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTLSM_CNTL6_EO_PG                         , RULL(0x800D5C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTLSM_CNTL6_EO_PG                         , RULL(0x800D5C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTLSM_CNTL7_EO_PG                           , RULL(0x800D640006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTLSM_CNTL7_EO_PG                         , RULL(0x800D64000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTLSM_CNTL7_EO_PG                         , RULL(0x800D64000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTLSM_CNTLG1_E_PG                           , RULL(0x800D840006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTLSM_CNTLG1_E_PG                         , RULL(0x800D84000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTLSM_CNTLG1_E_PG                         , RULL(0x800D84000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTLSM_MODE1_EO_PG                           , RULL(0x800D2C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTLSM_MODE1_EO_PG                         , RULL(0x800D2C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTLSM_MODE1_EO_PG                         , RULL(0x800D2C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTLSM_SPARE_MODE_PG                         , RULL(0x800D240006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTLSM_SPARE_MODE_PG                       , RULL(0x800D24000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTLSM_SPARE_MODE_PG                       , RULL(0x800D24000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTLSM_STAT1_EO_PG                           , RULL(0x800D6C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTLSM_STAT1_EO_PG                         , RULL(0x800D6C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTLSM_STAT1_EO_PG                         , RULL(0x800D6C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTLSM_STAT1_E_PG                            , RULL(0x800D8C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTLSM_STAT1_E_PG                          , RULL(0x800D8C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTLSM_STAT1_E_PG                          , RULL(0x800D8C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_CNTL10_EO_PG                            , RULL(0x800CDC0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_CNTL10_EO_PG                          , RULL(0x800CDC000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_CNTL10_EO_PG                          , RULL(0x800CDC000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_CNTL2_EO_PG                             , RULL(0x800C2C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_CNTL2_EO_PG                           , RULL(0x800C2C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_CNTL2_EO_PG                           , RULL(0x800C2C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_CNTL2_E_PG                              , RULL(0x800C9C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_CNTL2_E_PG                            , RULL(0x800C9C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_CNTL2_E_PG                            , RULL(0x800C9C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_CNTL3_EO_PG                             , RULL(0x800C340006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_CNTL3_EO_PG                           , RULL(0x800C34000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_CNTL3_EO_PG                           , RULL(0x800C34000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_CNTL8_EO_PG                             , RULL(0x800CCC0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_CNTL8_EO_PG                           , RULL(0x800CCC000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_CNTL8_EO_PG                           , RULL(0x800CCC000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_CNTL9_EO_PG                             , RULL(0x800CD40006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_CNTL9_EO_PG                           , RULL(0x800CD4000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_CNTL9_EO_PG                           , RULL(0x800CD4000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_CNTLG1_EO_PG                            , RULL(0x800C240006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_CNTLG1_EO_PG                          , RULL(0x800C24000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_CNTLG1_EO_PG                          , RULL(0x800C24000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_CNTLG3_E_PG                             , RULL(0x800CA40006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_CNTLG3_E_PG                           , RULL(0x800CA4000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_CNTLG3_E_PG                           , RULL(0x800CA4000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_CNTLG4_E_PG                             , RULL(0x800CAC0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_CNTLG4_E_PG                           , RULL(0x800CAC000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_CNTLG4_E_PG                           , RULL(0x800CAC000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_CNTLG5_E_PG                             , RULL(0x800CB40006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_CNTLG5_E_PG                           , RULL(0x800CB4000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_CNTLG5_E_PG                           , RULL(0x800CB4000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_CNTLG6_E_PG                             , RULL(0x800CBC0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG                           , RULL(0x800CBC000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_CNTLG6_E_PG                           , RULL(0x800CBC000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_CNTLG7_E_PG                             , RULL(0x800CC40006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_CNTLG7_E_PG                           , RULL(0x800CC4000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_CNTLG7_E_PG                           , RULL(0x800CC4000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_MODE1_EO_PG                             , RULL(0x800C140006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_MODE1_EO_PG                           , RULL(0x800C14000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_MODE1_EO_PG                           , RULL(0x800C14000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_MODE1_E_PG                              , RULL(0x800C8C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_MODE1_E_PG                            , RULL(0x800C8C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_MODE1_E_PG                            , RULL(0x800C8C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_MODE2_EO_PG                             , RULL(0x800C1C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_MODE2_EO_PG                           , RULL(0x800C1C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_MODE2_EO_PG                           , RULL(0x800C1C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_MODE2_E_PG                              , RULL(0x800CEC0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_MODE2_E_PG                            , RULL(0x800CEC000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_MODE2_E_PG                            , RULL(0x800CEC000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_MODE3_E_PG                              , RULL(0x800CF40006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_MODE3_E_PG                            , RULL(0x800CF4000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_MODE3_E_PG                            , RULL(0x800CF4000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_CTL_STATG1_E_PG                             , RULL(0x800CE40006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_CTL_STATG1_E_PG                           , RULL(0x800CE4000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_CTL_STATG1_E_PG                           , RULL(0x800CE4000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_FIR_ERROR_INJECT_PG                         , RULL(0x800D1C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_FIR_ERROR_INJECT_PG                       , RULL(0x800D1C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_FIR_ERROR_INJECT_PG                       , RULL(0x800D1C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_FIR_MASK_PG                                 , RULL(0x800D0C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_FIR_MASK_PG                               , RULL(0x800D0C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_FIR_MASK_PG                               , RULL(0x800D0C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_FIR_PG                                      , RULL(0x800D040006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_FIR_PG                                    , RULL(0x800D04000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_FIR_PG                                    , RULL(0x800D04000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_FIR_RESET_PG                                , RULL(0x800D140006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_FIR_RESET_PG                              , RULL(0x800D14000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_FIR_RESET_PG                              , RULL(0x800D14000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_ID1_PG                                      , RULL(0x800C0C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_ID1_PG                                    , RULL(0x800C0C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_ID1_PG                                    , RULL(0x800C0C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_ID2_PG                                      , RULL(0x800C840006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_ID2_PG                                    , RULL(0x800C84000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_ID2_PG                                    , RULL(0x800C84000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX0_TX_SPARE_MODE_PG                               , RULL(0x800C040006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX0_TX_SPARE_MODE_PG                             , RULL(0x800C04000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX0_TX_SPARE_MODE_PG                             , RULL(0x800C04000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL              , RULL(0x80043C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL              , RULL(0x8004442006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x800444200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x800444200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL                   , RULL(0x8004142006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE0_TX_CNTL3_EO_PL                 , RULL(0x8004542006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE0_TX_FIR_MASK_PL                 , RULL(0x80042C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE0_TX_FIR_PL                      , RULL(0x8004242006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE0_TX_FIR_PL                    , RULL(0x800424200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE0_TX_FIR_PL                    , RULL(0x800424200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE0_TX_MODE1_PL                    , RULL(0x8004042006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL                  , RULL(0x800404200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE0_TX_MODE1_PL                  , RULL(0x800404200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE0_TX_MODE2_PL                    , RULL(0x80040C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL                  , RULL(0x80040C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE0_TX_MODE2_PL                  , RULL(0x80040C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE0_TX_STAT1_PL                    , RULL(0x80041C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL                  , RULL(0x80041C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE0_TX_STAT1_PL                  , RULL(0x80041C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL              , RULL(0x80043C2106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL              , RULL(0x8004442106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x800444210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x800444210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL                   , RULL(0x8004142106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE1_TX_CNTL3_EO_PL                 , RULL(0x8004542106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE1_TX_FIR_MASK_PL                 , RULL(0x80042C2106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE1_TX_FIR_PL                      , RULL(0x8004242106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE1_TX_FIR_PL                    , RULL(0x800424210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE1_TX_FIR_PL                    , RULL(0x800424210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE1_TX_MODE1_PL                    , RULL(0x8004042106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL                  , RULL(0x800404210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE1_TX_MODE1_PL                  , RULL(0x800404210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE1_TX_MODE2_PL                    , RULL(0x80040C2106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL                  , RULL(0x80040C210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE1_TX_MODE2_PL                  , RULL(0x80040C210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE1_TX_STAT1_PL                    , RULL(0x80041C2106010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL                  , RULL(0x80041C210601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE1_TX_STAT1_PL                  , RULL(0x80041C210601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL              , RULL(0x80043C2206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL              , RULL(0x8004442206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x800444220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x800444220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL                   , RULL(0x8004142206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL                 , RULL(0x800414220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE2_TX_CNTL1G_PL                 , RULL(0x800414220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE2_TX_CNTL3_EO_PL                 , RULL(0x8004542206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE2_TX_CNTL3_EO_PL               , RULL(0x800454220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE2_TX_CNTL3_EO_PL               , RULL(0x800454220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE2_TX_FIR_MASK_PL                 , RULL(0x80042C2206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE2_TX_FIR_PL                      , RULL(0x8004242206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE2_TX_FIR_PL                    , RULL(0x800424220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE2_TX_FIR_PL                    , RULL(0x800424220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE2_TX_MODE1_PL                    , RULL(0x8004042206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL                  , RULL(0x800404220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE2_TX_MODE1_PL                  , RULL(0x800404220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE2_TX_MODE2_PL                    , RULL(0x80040C2206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL                  , RULL(0x80040C220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE2_TX_MODE2_PL                  , RULL(0x80040C220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE2_TX_STAT1_PL                    , RULL(0x80041C2206010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL                  , RULL(0x80041C220601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE2_TX_STAT1_PL                  , RULL(0x80041C220601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL              , RULL(0x80043C2306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL              , RULL(0x8004442306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x800444230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x800444230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL                   , RULL(0x8004142306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL                 , RULL(0x800414230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE3_TX_CNTL1G_PL                 , RULL(0x800414230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE3_TX_CNTL3_EO_PL                 , RULL(0x8004542306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE3_TX_CNTL3_EO_PL               , RULL(0x800454230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE3_TX_CNTL3_EO_PL               , RULL(0x800454230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE3_TX_FIR_MASK_PL                 , RULL(0x80042C2306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE3_TX_FIR_PL                      , RULL(0x8004242306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE3_TX_FIR_PL                    , RULL(0x800424230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE3_TX_FIR_PL                    , RULL(0x800424230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE3_TX_MODE1_PL                    , RULL(0x8004042306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL                  , RULL(0x800404230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE3_TX_MODE1_PL                  , RULL(0x800404230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE3_TX_MODE2_PL                    , RULL(0x80040C2306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL                  , RULL(0x80040C230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE3_TX_MODE2_PL                  , RULL(0x80040C230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS0_SLICE3_TX_STAT1_PL                    , RULL(0x80041C2306010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL                  , RULL(0x80041C230601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS0_SLICE3_TX_STAT1_PL                  , RULL(0x80041C230601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL              , RULL(0x80043C2406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL              , RULL(0x8004442406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x800444240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x800444240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL                   , RULL(0x8004142406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE0_TX_CNTL3_EO_PL                 , RULL(0x8004542406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE0_TX_FIR_MASK_PL                 , RULL(0x80042C2406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE0_TX_FIR_PL                      , RULL(0x8004242406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE0_TX_FIR_PL                    , RULL(0x800424240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE0_TX_FIR_PL                    , RULL(0x800424240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE0_TX_MODE1_PL                    , RULL(0x8004042406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL                  , RULL(0x800404240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE0_TX_MODE1_PL                  , RULL(0x800404240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE0_TX_MODE2_PL                    , RULL(0x80040C2406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL                  , RULL(0x80040C240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE0_TX_MODE2_PL                  , RULL(0x80040C240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE0_TX_STAT1_PL                    , RULL(0x80041C2406010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL                  , RULL(0x80041C240601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE0_TX_STAT1_PL                  , RULL(0x80041C240601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL              , RULL(0x80043C2506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL              , RULL(0x8004442506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x800444250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x800444250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL                   , RULL(0x8004142506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE1_TX_CNTL3_EO_PL                 , RULL(0x8004542506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE1_TX_FIR_MASK_PL                 , RULL(0x80042C2506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE1_TX_FIR_PL                      , RULL(0x8004242506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE1_TX_FIR_PL                    , RULL(0x800424250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE1_TX_FIR_PL                    , RULL(0x800424250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE1_TX_MODE1_PL                    , RULL(0x8004042506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL                  , RULL(0x800404250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE1_TX_MODE1_PL                  , RULL(0x800404250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE1_TX_MODE2_PL                    , RULL(0x80040C2506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL                  , RULL(0x80040C250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE1_TX_MODE2_PL                  , RULL(0x80040C250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE1_TX_STAT1_PL                    , RULL(0x80041C2506010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL                  , RULL(0x80041C250601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE1_TX_STAT1_PL                  , RULL(0x80041C250601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL              , RULL(0x80043C2606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL              , RULL(0x8004442606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x800444260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x800444260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL                   , RULL(0x8004142606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL                 , RULL(0x800414260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE2_TX_CNTL1G_PL                 , RULL(0x800414260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE2_TX_CNTL3_EO_PL                 , RULL(0x8004542606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE2_TX_CNTL3_EO_PL               , RULL(0x800454260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE2_TX_CNTL3_EO_PL               , RULL(0x800454260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE2_TX_FIR_MASK_PL                 , RULL(0x80042C2606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE2_TX_FIR_PL                      , RULL(0x8004242606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE2_TX_FIR_PL                    , RULL(0x800424260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE2_TX_FIR_PL                    , RULL(0x800424260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE2_TX_MODE1_PL                    , RULL(0x8004042606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL                  , RULL(0x800404260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE2_TX_MODE1_PL                  , RULL(0x800404260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE2_TX_MODE2_PL                    , RULL(0x80040C2606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL                  , RULL(0x80040C260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE2_TX_MODE2_PL                  , RULL(0x80040C260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE2_TX_STAT1_PL                    , RULL(0x80041C2606010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL                  , RULL(0x80041C260601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE2_TX_STAT1_PL                  , RULL(0x80041C260601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL              , RULL(0x80043C2706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL              , RULL(0x8004442706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x800444270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x800444270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL                   , RULL(0x8004142706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL                 , RULL(0x800414270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE3_TX_CNTL1G_PL                 , RULL(0x800414270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE3_TX_CNTL3_EO_PL                 , RULL(0x8004542706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE3_TX_CNTL3_EO_PL               , RULL(0x800454270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE3_TX_CNTL3_EO_PL               , RULL(0x800454270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE3_TX_FIR_MASK_PL                 , RULL(0x80042C2706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE3_TX_FIR_PL                      , RULL(0x8004242706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE3_TX_FIR_PL                    , RULL(0x800424270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE3_TX_FIR_PL                    , RULL(0x800424270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE3_TX_MODE1_PL                    , RULL(0x8004042706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL                  , RULL(0x800404270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE3_TX_MODE1_PL                  , RULL(0x800404270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE3_TX_MODE2_PL                    , RULL(0x80040C2706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL                  , RULL(0x80040C270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE3_TX_MODE2_PL                  , RULL(0x80040C270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS1_SLICE3_TX_STAT1_PL                    , RULL(0x80041C2706010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL                  , RULL(0x80041C270601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS1_SLICE3_TX_STAT1_PL                  , RULL(0x80041C270601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL              , RULL(0x80043C2806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL              , RULL(0x8004442806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x800444280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x800444280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL                   , RULL(0x8004142806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE0_TX_CNTL1G_PL                 , RULL(0x800414280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE0_TX_CNTL3_EO_PL                 , RULL(0x8004542806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE0_TX_CNTL3_EO_PL               , RULL(0x800454280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE0_TX_FIR_MASK_PL                 , RULL(0x80042C2806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE0_TX_FIR_PL                      , RULL(0x8004242806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE0_TX_FIR_PL                    , RULL(0x800424280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE0_TX_FIR_PL                    , RULL(0x800424280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE0_TX_MODE1_PL                    , RULL(0x8004042806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL                  , RULL(0x800404280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE0_TX_MODE1_PL                  , RULL(0x800404280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE0_TX_MODE2_PL                    , RULL(0x80040C2806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL                  , RULL(0x80040C280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE0_TX_MODE2_PL                  , RULL(0x80040C280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE0_TX_STAT1_PL                    , RULL(0x80041C2806010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL                  , RULL(0x80041C280601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE0_TX_STAT1_PL                  , RULL(0x80041C280601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL              , RULL(0x80043C2906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL              , RULL(0x8004442906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x800444290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x800444290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL                   , RULL(0x8004142906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE1_TX_CNTL1G_PL                 , RULL(0x800414290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE1_TX_CNTL3_EO_PL                 , RULL(0x8004542906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE1_TX_CNTL3_EO_PL               , RULL(0x800454290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE1_TX_FIR_MASK_PL                 , RULL(0x80042C2906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE1_TX_FIR_PL                      , RULL(0x8004242906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE1_TX_FIR_PL                    , RULL(0x800424290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE1_TX_FIR_PL                    , RULL(0x800424290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE1_TX_MODE1_PL                    , RULL(0x8004042906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL                  , RULL(0x800404290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE1_TX_MODE1_PL                  , RULL(0x800404290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE1_TX_MODE2_PL                    , RULL(0x80040C2906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL                  , RULL(0x80040C290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE1_TX_MODE2_PL                  , RULL(0x80040C290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE1_TX_STAT1_PL                    , RULL(0x80041C2906010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL                  , RULL(0x80041C290601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE1_TX_STAT1_PL                  , RULL(0x80041C290601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL              , RULL(0x80043C2A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C2A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C2A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL              , RULL(0x8004442A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x8004442A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x8004442A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL                   , RULL(0x8004142A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004142A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004142A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE2_TX_CNTL3_EO_PL                 , RULL(0x8004542A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004542A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004542A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004342A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004342A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE2_TX_FIR_MASK_PL                 , RULL(0x80042C2A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C2A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C2A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE2_TX_FIR_PL                      , RULL(0x8004242A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE2_TX_FIR_PL                    , RULL(0x8004242A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE2_TX_FIR_PL                    , RULL(0x8004242A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE2_TX_MODE1_PL                    , RULL(0x8004042A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL                  , RULL(0x8004042A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE2_TX_MODE1_PL                  , RULL(0x8004042A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE2_TX_MODE2_PL                    , RULL(0x80040C2A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL                  , RULL(0x80040C2A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE2_TX_MODE2_PL                  , RULL(0x80040C2A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE2_TX_STAT1_PL                    , RULL(0x80041C2A06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL                  , RULL(0x80041C2A0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE2_TX_STAT1_PL                  , RULL(0x80041C2A0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL              , RULL(0x80043C2B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C2B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C2B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL              , RULL(0x8004442B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x8004442B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x8004442B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL                   , RULL(0x8004142B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004142B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004142B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE3_TX_CNTL3_EO_PL                 , RULL(0x8004542B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004542B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004542B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004342B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004342B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE3_TX_FIR_MASK_PL                 , RULL(0x80042C2B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C2B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C2B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE3_TX_FIR_PL                      , RULL(0x8004242B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE3_TX_FIR_PL                    , RULL(0x8004242B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE3_TX_FIR_PL                    , RULL(0x8004242B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE3_TX_MODE1_PL                    , RULL(0x8004042B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL                  , RULL(0x8004042B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE3_TX_MODE1_PL                  , RULL(0x8004042B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE3_TX_MODE2_PL                    , RULL(0x80040C2B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL                  , RULL(0x80040C2B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE3_TX_MODE2_PL                  , RULL(0x80040C2B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS2_SLICE3_TX_STAT1_PL                    , RULL(0x80041C2B06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL                  , RULL(0x80041C2B0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS2_SLICE3_TX_STAT1_PL                  , RULL(0x80041C2B0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL              , RULL(0x80043C2C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C2C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL            , RULL(0x80043C2C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL              , RULL(0x8004442C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x8004442C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL            , RULL(0x8004442C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL                   , RULL(0x8004142C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL                 , RULL(0x8004142C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE0_TX_CNTL1G_PL                 , RULL(0x8004142C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE0_TX_CNTL3_EO_PL                 , RULL(0x8004542C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE0_TX_CNTL3_EO_PL               , RULL(0x8004542C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE0_TX_CNTL3_EO_PL               , RULL(0x8004542C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004342C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004342C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE0_TX_FIR_MASK_PL                 , RULL(0x80042C2C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C2C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE0_TX_FIR_MASK_PL               , RULL(0x80042C2C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE0_TX_FIR_PL                      , RULL(0x8004242C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE0_TX_FIR_PL                    , RULL(0x8004242C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE0_TX_FIR_PL                    , RULL(0x8004242C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE0_TX_MODE1_PL                    , RULL(0x8004042C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL                  , RULL(0x8004042C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE0_TX_MODE1_PL                  , RULL(0x8004042C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE0_TX_MODE2_PL                    , RULL(0x80040C2C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL                  , RULL(0x80040C2C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE0_TX_MODE2_PL                  , RULL(0x80040C2C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE0_TX_STAT1_PL                    , RULL(0x80041C2C06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL                  , RULL(0x80041C2C0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE0_TX_STAT1_PL                  , RULL(0x80041C2C0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL              , RULL(0x80043C2D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C2D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL            , RULL(0x80043C2D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL              , RULL(0x8004442D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x8004442D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL            , RULL(0x8004442D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL                   , RULL(0x8004142D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL                 , RULL(0x8004142D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE1_TX_CNTL1G_PL                 , RULL(0x8004142D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE1_TX_CNTL3_EO_PL                 , RULL(0x8004542D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE1_TX_CNTL3_EO_PL               , RULL(0x8004542D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE1_TX_CNTL3_EO_PL               , RULL(0x8004542D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004342D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004342D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE1_TX_FIR_MASK_PL                 , RULL(0x80042C2D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C2D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE1_TX_FIR_MASK_PL               , RULL(0x80042C2D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE1_TX_FIR_PL                      , RULL(0x8004242D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE1_TX_FIR_PL                    , RULL(0x8004242D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE1_TX_FIR_PL                    , RULL(0x8004242D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE1_TX_MODE1_PL                    , RULL(0x8004042D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL                  , RULL(0x8004042D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE1_TX_MODE1_PL                  , RULL(0x8004042D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE1_TX_MODE2_PL                    , RULL(0x80040C2D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL                  , RULL(0x80040C2D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE1_TX_MODE2_PL                  , RULL(0x80040C2D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE1_TX_STAT1_PL                    , RULL(0x80041C2D06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL                  , RULL(0x80041C2D0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE1_TX_STAT1_PL                  , RULL(0x80041C2D0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL              , RULL(0x80043C2E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C2E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL            , RULL(0x80043C2E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL              , RULL(0x8004442E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x8004442E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL            , RULL(0x8004442E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL                   , RULL(0x8004142E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004142E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE2_TX_CNTL1G_PL                 , RULL(0x8004142E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE2_TX_CNTL3_EO_PL                 , RULL(0x8004542E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004542E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE2_TX_CNTL3_EO_PL               , RULL(0x8004542E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004342E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004342E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE2_TX_FIR_MASK_PL                 , RULL(0x80042C2E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C2E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE2_TX_FIR_MASK_PL               , RULL(0x80042C2E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE2_TX_FIR_PL                      , RULL(0x8004242E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE2_TX_FIR_PL                    , RULL(0x8004242E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE2_TX_FIR_PL                    , RULL(0x8004242E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE2_TX_MODE1_PL                    , RULL(0x8004042E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL                  , RULL(0x8004042E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE2_TX_MODE1_PL                  , RULL(0x8004042E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE2_TX_MODE2_PL                    , RULL(0x80040C2E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL                  , RULL(0x80040C2E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE2_TX_MODE2_PL                  , RULL(0x80040C2E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE2_TX_STAT1_PL                    , RULL(0x80041C2E06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL                  , RULL(0x80041C2E0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE2_TX_STAT1_PL                  , RULL(0x80041C2E0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL              , RULL(0x80043C2F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C2F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL            , RULL(0x80043C2F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL              , RULL(0x8004442F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x8004442F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL            , RULL(0x8004442F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL                   , RULL(0x8004142F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004142F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE3_TX_CNTL1G_PL                 , RULL(0x8004142F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE3_TX_CNTL3_EO_PL                 , RULL(0x8004542F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004542F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE3_TX_CNTL3_EO_PL               , RULL(0x8004542F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004342F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004342F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL       , RULL(0x8004342F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE3_TX_FIR_MASK_PL                 , RULL(0x80042C2F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C2F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE3_TX_FIR_MASK_PL               , RULL(0x80042C2F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE3_TX_FIR_PL                      , RULL(0x8004242F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE3_TX_FIR_PL                    , RULL(0x8004242F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE3_TX_FIR_PL                    , RULL(0x8004242F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE3_TX_MODE1_PL                    , RULL(0x8004042F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL                  , RULL(0x8004042F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE3_TX_MODE1_PL                  , RULL(0x8004042F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE3_TX_MODE2_PL                    , RULL(0x80040C2F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL                  , RULL(0x80040C2F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE3_TX_MODE2_PL                  , RULL(0x80040C2F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE3_TX_STAT1_PL                    , RULL(0x80041C2F06010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL                  , RULL(0x80041C2F0601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE3_TX_STAT1_PL                  , RULL(0x80041C2F0601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL              , RULL(0x80043C3006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL            , RULL(0x80043C300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL            , RULL(0x80043C300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL              , RULL(0x8004443006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL            , RULL(0x800444300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL            , RULL(0x800444300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL                   , RULL(0x8004143006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL                 , RULL(0x800414300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE4_TX_CNTL1G_PL                 , RULL(0x800414300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE4_TX_CNTL3_EO_PL                 , RULL(0x8004543006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE4_TX_CNTL3_EO_PL               , RULL(0x800454300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE4_TX_CNTL3_EO_PL               , RULL(0x800454300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL         , RULL(0x8004343006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL       , RULL(0x800434300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE4_TX_FIR_MASK_PL                 , RULL(0x80042C3006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE4_TX_FIR_MASK_PL               , RULL(0x80042C300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE4_TX_FIR_MASK_PL               , RULL(0x80042C300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE4_TX_FIR_PL                      , RULL(0x8004243006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE4_TX_FIR_PL                    , RULL(0x800424300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE4_TX_FIR_PL                    , RULL(0x800424300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE4_TX_MODE1_PL                    , RULL(0x8004043006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL                  , RULL(0x800404300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE4_TX_MODE1_PL                  , RULL(0x800404300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE4_TX_MODE2_PL                    , RULL(0x80040C3006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL                  , RULL(0x80040C300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE4_TX_MODE2_PL                  , RULL(0x80040C300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TXPACKS3_SLICE4_TX_STAT1_PL                    , RULL(0x80041C3006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL                  , RULL(0x80041C300601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TXPACKS3_SLICE4_TX_STAT1_PL                  , RULL(0x80041C300601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTLSM_CNTL1_EO_PG                           , RULL(0x800D342006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTLSM_CNTL1_EO_PG                         , RULL(0x800D34200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTLSM_CNTL1_EO_PG                         , RULL(0x800D34200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTLSM_CNTL2_EO_PG                           , RULL(0x800D3C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTLSM_CNTL2_EO_PG                         , RULL(0x800D3C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTLSM_CNTL2_EO_PG                         , RULL(0x800D3C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTLSM_CNTL3_EO_PG                           , RULL(0x800D442006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTLSM_CNTL3_EO_PG                         , RULL(0x800D44200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTLSM_CNTL3_EO_PG                         , RULL(0x800D44200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTLSM_CNTL4_EO_PG                           , RULL(0x800D4C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTLSM_CNTL4_EO_PG                         , RULL(0x800D4C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTLSM_CNTL4_EO_PG                         , RULL(0x800D4C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTLSM_CNTL5_EO_PG                           , RULL(0x800D542006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTLSM_CNTL5_EO_PG                         , RULL(0x800D54200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTLSM_CNTL5_EO_PG                         , RULL(0x800D54200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTLSM_CNTL6_EO_PG                           , RULL(0x800D5C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTLSM_CNTL6_EO_PG                         , RULL(0x800D5C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTLSM_CNTL6_EO_PG                         , RULL(0x800D5C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTLSM_CNTL7_EO_PG                           , RULL(0x800D642006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTLSM_CNTL7_EO_PG                         , RULL(0x800D64200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTLSM_CNTL7_EO_PG                         , RULL(0x800D64200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTLSM_CNTLG1_E_PG                           , RULL(0x800D842006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTLSM_CNTLG1_E_PG                         , RULL(0x800D84200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTLSM_CNTLG1_E_PG                         , RULL(0x800D84200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTLSM_MODE1_EO_PG                           , RULL(0x800D2C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTLSM_MODE1_EO_PG                         , RULL(0x800D2C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTLSM_MODE1_EO_PG                         , RULL(0x800D2C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTLSM_SPARE_MODE_PG                         , RULL(0x800D242006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTLSM_SPARE_MODE_PG                       , RULL(0x800D24200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTLSM_SPARE_MODE_PG                       , RULL(0x800D24200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTLSM_STAT1_EO_PG                           , RULL(0x800D6C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTLSM_STAT1_EO_PG                         , RULL(0x800D6C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTLSM_STAT1_EO_PG                         , RULL(0x800D6C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTLSM_STAT1_E_PG                            , RULL(0x800D8C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTLSM_STAT1_E_PG                          , RULL(0x800D8C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTLSM_STAT1_E_PG                          , RULL(0x800D8C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_CNTL10_EO_PG                            , RULL(0x800CDC2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_CNTL10_EO_PG                          , RULL(0x800CDC200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_CNTL10_EO_PG                          , RULL(0x800CDC200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_CNTL2_EO_PG                             , RULL(0x800C2C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_CNTL2_EO_PG                           , RULL(0x800C2C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_CNTL2_EO_PG                           , RULL(0x800C2C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_CNTL2_E_PG                              , RULL(0x800C9C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_CNTL2_E_PG                            , RULL(0x800C9C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_CNTL2_E_PG                            , RULL(0x800C9C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_CNTL3_EO_PG                             , RULL(0x800C342006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_CNTL3_EO_PG                           , RULL(0x800C34200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_CNTL3_EO_PG                           , RULL(0x800C34200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_CNTL8_EO_PG                             , RULL(0x800CCC2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_CNTL8_EO_PG                           , RULL(0x800CCC200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_CNTL8_EO_PG                           , RULL(0x800CCC200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_CNTL9_EO_PG                             , RULL(0x800CD42006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_CNTL9_EO_PG                           , RULL(0x800CD4200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_CNTL9_EO_PG                           , RULL(0x800CD4200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_CNTLG1_EO_PG                            , RULL(0x800C242006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_CNTLG1_EO_PG                          , RULL(0x800C24200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_CNTLG1_EO_PG                          , RULL(0x800C24200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_CNTLG3_E_PG                             , RULL(0x800CA42006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_CNTLG3_E_PG                           , RULL(0x800CA4200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_CNTLG3_E_PG                           , RULL(0x800CA4200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_CNTLG4_E_PG                             , RULL(0x800CAC2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_CNTLG4_E_PG                           , RULL(0x800CAC200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_CNTLG4_E_PG                           , RULL(0x800CAC200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_CNTLG5_E_PG                             , RULL(0x800CB42006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_CNTLG5_E_PG                           , RULL(0x800CB4200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_CNTLG5_E_PG                           , RULL(0x800CB4200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_CNTLG6_E_PG                             , RULL(0x800CBC2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG                           , RULL(0x800CBC200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_CNTLG6_E_PG                           , RULL(0x800CBC200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_CNTLG7_E_PG                             , RULL(0x800CC42006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_CNTLG7_E_PG                           , RULL(0x800CC4200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_CNTLG7_E_PG                           , RULL(0x800CC4200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_MODE1_EO_PG                             , RULL(0x800C142006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_MODE1_EO_PG                           , RULL(0x800C14200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_MODE1_EO_PG                           , RULL(0x800C14200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_MODE1_E_PG                              , RULL(0x800C8C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_MODE1_E_PG                            , RULL(0x800C8C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_MODE1_E_PG                            , RULL(0x800C8C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_MODE2_EO_PG                             , RULL(0x800C1C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_MODE2_EO_PG                           , RULL(0x800C1C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_MODE2_EO_PG                           , RULL(0x800C1C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_MODE2_E_PG                              , RULL(0x800CEC2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_MODE2_E_PG                            , RULL(0x800CEC200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_MODE2_E_PG                            , RULL(0x800CEC200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_MODE3_E_PG                              , RULL(0x800CF42006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_MODE3_E_PG                            , RULL(0x800CF4200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_MODE3_E_PG                            , RULL(0x800CF4200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_CTL_STATG1_E_PG                             , RULL(0x800CE42006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_CTL_STATG1_E_PG                           , RULL(0x800CE4200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_CTL_STATG1_E_PG                           , RULL(0x800CE4200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_FIR_ERROR_INJECT_PG                         , RULL(0x800D1C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_FIR_ERROR_INJECT_PG                       , RULL(0x800D1C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_FIR_ERROR_INJECT_PG                       , RULL(0x800D1C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_FIR_MASK_PG                                 , RULL(0x800D0C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_FIR_MASK_PG                               , RULL(0x800D0C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_FIR_MASK_PG                               , RULL(0x800D0C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_FIR_PG                                      , RULL(0x800D042006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_FIR_PG                                    , RULL(0x800D04200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_FIR_PG                                    , RULL(0x800D04200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_FIR_RESET_PG                                , RULL(0x800D142006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_FIR_RESET_PG                              , RULL(0x800D14200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_FIR_RESET_PG                              , RULL(0x800D14200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_ID1_PG                                      , RULL(0x800C0C2006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_ID1_PG                                    , RULL(0x800C0C200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_ID1_PG                                    , RULL(0x800C0C200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_ID2_PG                                      , RULL(0x800C842006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_ID2_PG                                    , RULL(0x800C84200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_ID2_PG                                    , RULL(0x800C84200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX1_TX_SPARE_MODE_PG                               , RULL(0x800C042006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX1_TX_SPARE_MODE_PG                             , RULL(0x800C04200601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX1_TX_SPARE_MODE_PG                             , RULL(0x800C04200601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX_IMPCAL2_PB                                      , RULL(0x800F3C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX_IMPCAL2_PB                                    , RULL(0x800F3C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX_IMPCAL2_PB                                    , RULL(0x800F3C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX_IMPCAL_NVAL_PB                                  , RULL(0x800F0C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX_IMPCAL_NVAL_PB                                , RULL(0x800F0C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX_IMPCAL_NVAL_PB                                , RULL(0x800F0C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX_IMPCAL_PB                                       , RULL(0x800F040006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX_IMPCAL_PB                                     , RULL(0x800F04000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX_IMPCAL_PB                                     , RULL(0x800F04000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX_IMPCAL_PVAL_PB                                  , RULL(0x800F140006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX_IMPCAL_PVAL_PB                                , RULL(0x800F14000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX_IMPCAL_PVAL_PB                                , RULL(0x800F14000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX_IMPCAL_P_4X_PB                                  , RULL(0x800F1C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX_IMPCAL_P_4X_PB                                , RULL(0x800F1C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX_IMPCAL_P_4X_PB                                , RULL(0x800F1C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX_IMPCAL_SWO1_PB                                  , RULL(0x800F240006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX_IMPCAL_SWO1_PB                                , RULL(0x800F24000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX_IMPCAL_SWO1_PB                                , RULL(0x800F24000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_TX_IMPCAL_SWO2_PB                                  , RULL(0x800F2C0006010C3F), SH_UNT_XBUS     ,
+       SH_ACS_SCOM      );
+REG64( XBUS_1_TX_IMPCAL_SWO2_PB                                , RULL(0x800F2C000601103F), SH_UNT_XBUS_1   ,
+       SH_ACS_SCOM      );
+REG64( XBUS_2_TX_IMPCAL_SWO2_PB                                , RULL(0x800F2C000601143F), SH_UNT_XBUS_2   ,
+       SH_ACS_SCOM      );
+
+REG64( XBUS_PERV_XTRA_TRACE_MODE                               , RULL(0x060107D1), SH_UNT_XBUS_PERV, SH_ACS_SCOM      );
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9_xbus_scom_addresses_fixes.H b/src/import/chips/p9/common/include/p9_xbus_scom_addresses_fixes.H
new file mode 100644
index 00000000..8c7cc415
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_xbus_scom_addresses_fixes.H
@@ -0,0 +1,50 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_xbus_scom_addresses_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file xbus_scom_addresses_fixes.H
+/// @brief The *scom_addresses.H files are  generated form figtree, but
+///        the figree can be wrong.  This file is included at the end
+///        of scom_addresses.H and allows incorrect constants to be
+///        fixed manually.
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SAO
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __P9_XBUS_SCOM_ADDRESSES_FIXES_H
+#define __P9_XBUS_SCOM_ADDRESSES_FIXES_H
+
+//Example,
+//Copy the whole line from the *scom_addresses.H file.  Then add
+//FIX in front of REG, and add another paramter that is the new
+//corrected value.
+//FIXREG64( PU_ALTD_ADDR_REG,
+//          RULL(0x05022800), SH_UNT, SH_ACS_SCOM,
+//          RULL(0x00090000)
+//        );
+
+#endif
diff --git a/src/import/chips/p9/common/include/p9_xbus_scom_addresses_fld.H b/src/import/chips/p9/common/include/p9_xbus_scom_addresses_fld.H
new file mode 100644
index 00000000..df6fab4f
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_xbus_scom_addresses_fld.H
@@ -0,0 +1,23424 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_xbus_scom_addresses_fld.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_xbus_scom_addresses_fld.H
+/// @brief  Defines constants for scom addresses
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: SOA
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#include <p9_const_common.H>
+
+#ifndef __P9_XBUS_SCOM_ADDRESSES_FLD_H
+#define __P9_XBUS_SCOM_ADDRESSES_FLD_H
+
+
+#include <p9_scom_template_consts.H>
+#include <p9_xbus_scom_addresses_fld_fixes.H>
+
+REG64_FLD( XBUS_IOPPE_CSAR_SRAM_ADDRESS                            , 16  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_ADDRESS );
+REG64_FLD( XBUS_IOPPE_CSAR_SRAM_ADDRESS_LEN                        , 13  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_ADDRESS_LEN );
+
+REG64_FLD( XBUS_IOPPE_CSCR_SRAM_ACCESS_MODE                        , 0   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_ACCESS_MODE );
+REG64_FLD( XBUS_IOPPE_CSCR_SRAM_SCRUB_ENABLE                       , 1   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SCRUB_ENABLE );
+REG64_FLD( XBUS_IOPPE_CSCR_ECC_CORRECT_DIS                         , 2   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_CORRECT_DIS );
+REG64_FLD( XBUS_IOPPE_CSCR_ECC_DETECT_DIS                          , 3   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_DETECT_DIS );
+REG64_FLD( XBUS_IOPPE_CSCR_ECC_INJECT_TYPE                         , 4   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_INJECT_TYPE );
+REG64_FLD( XBUS_IOPPE_CSCR_ECC_INJECT_ERR                          , 5   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR ,
+           SH_FLD_ECC_INJECT_ERR );
+REG64_FLD( XBUS_IOPPE_CSCR_SPARE_6_7                               , 6   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_6_7  );
+REG64_FLD( XBUS_IOPPE_CSCR_SPARE_6_7_LEN                           , 2   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR ,
+           SH_FLD_SPARE_6_7_LEN );
+REG64_FLD( XBUS_IOPPE_CSCR_SRAM_SCRUB_INDEX                        , 47  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SCRUB_INDEX );
+REG64_FLD( XBUS_IOPPE_CSCR_SRAM_SCRUB_INDEX_LEN                    , 13  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_OR ,
+           SH_FLD_SRAM_SCRUB_INDEX_LEN );
+
+REG64_FLD( XBUS_IOPPE_CSDR_SRAM_DATA                               , 0   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_DATA  );
+REG64_FLD( XBUS_IOPPE_CSDR_SRAM_DATA_LEN                           , 64  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RW  ,
+           SH_FLD_SRAM_DATA_LEN );
+
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_COND1_SEL_A              , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN          , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_COND1_SEL_B              , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN          , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_COND2_SEL_A              , 16  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN          , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_COND2_SEL_B              , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN          , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_C1_INAROW_MODE           , 32  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1        , 33  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1        , 34  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1       , 35  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_UNUSED                   , 36  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_UNUSED_LEN               , 3   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_C2_INAROW_MODE           , 39  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2        , 40  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2        , 41  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2       , 42  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_UNUSED_2                 , 43  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_UNUSED_2_LEN             , 3   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET       , 46  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_EXACT_TO_MODE            , 47  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1      , 48  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_RESET_C3_ON_C0           , 49  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_SLOW_TO_MODE             , 50  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO     , 51  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_C1_COUNT_LT              , 52  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN          , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_C2_COUNT_LT              , 56  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN          , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_RESET_C3_SELECT          , 60  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN      , 3   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A  , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B  , 5   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A    , 10  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B    , 15  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_2_TO_CMP_LT                , 20  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN            , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_2_FORCE_TEST_MODE          , 44  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_3_SP_COUNT_LT              , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( XBUS_PERV_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN          , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_COND1_SEL_A              , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN          , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_A_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_COND1_SEL_B              , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN          , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND1_SEL_B_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_COND2_SEL_A              , 16  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN          , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_A_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_COND2_SEL_B              , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN          , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND2_SEL_B_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_C1_INAROW_MODE           , 32  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_C1_INAROW_MODE );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1        , 33  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE1 );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1        , 34  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE1 );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1       , 35  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE1 );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_UNUSED                   , 36  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED     );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_UNUSED_LEN               , 3   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_C2_INAROW_MODE           , 39  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_C2_INAROW_MODE );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2        , 40  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_AND_TRIGGER_MODE2 );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2        , 41  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_NOT_TRIGGER_MODE2 );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2       , 42  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_EDGE_TRIGGER_MODE2 );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_UNUSED_2                 , 43  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2   );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_UNUSED_2_LEN             , 3   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_UNUSED_2_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET       , 46  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_COND3_ENABLE_RESET );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_EXACT_TO_MODE            , 47  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_EXACT_TO_MODE );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1      , 48  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_RESET_C2TIMER_ON_C1 );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_RESET_C3_ON_C0           , 49  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_ON_C0 );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_SLOW_TO_MODE             , 50  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_SLOW_TO_MODE );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO     , 51  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_EXACT_RESET_C3_ON_TO );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_C1_COUNT_LT              , 52  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN          , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_C1_COUNT_LT_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_C2_COUNT_LT              , 56  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN          , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_C2_COUNT_LT_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_RESET_C3_SELECT          , 60  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN      , 3   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_RESET_C3_SELECT_LEN );
+
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A  , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B  , 5   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A    , 10  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_A_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B    , 15  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CROSS_COUPLE_SELECT_B_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_2_TO_CMP_LT                , 20  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT  );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN            , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TO_CMP_LT_LEN );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_2_FORCE_TEST_MODE          , 44  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST_MODE );
+
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_3_SP_COUNT_LT              , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT );
+REG64_FLD( XBUS_PERV_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN          , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_SP_COUNT_LT_LEN );
+
+REG64_FLD( XBUS_PERV_DBG_MODE_REG_GLB_BRCST                        , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST  );
+REG64_FLD( XBUS_PERV_DBG_MODE_REG_GLB_BRCST_LEN                    , 3   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_GLB_BRCST_LEN );
+REG64_FLD( XBUS_PERV_DBG_MODE_REG_TRACE_SEL                        , 5   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRACE_SEL  );
+REG64_FLD( XBUS_PERV_DBG_MODE_REG_TRIG_SEL                         , 7   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG_SEL   );
+REG64_FLD( XBUS_PERV_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION          , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_XSTOP_SELECTION );
+REG64_FLD( XBUS_PERV_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION      , 9   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_RECOV_ERR_SELECTION );
+REG64_FLD( XBUS_PERV_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION         , 10  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_SPATTN_SELECTION );
+REG64_FLD( XBUS_PERV_DBG_MODE_REG_FREEZE_SEL                       , 11  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_FREEZE_SEL );
+
+REG64_FLD( XBUS_PERV_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE );
+REG64_FLD( XBUS_PERV_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_MODE_REG_2_IMM_FREEZE               , 16  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_IMM_FREEZE );
+REG64_FLD( XBUS_PERV_DBG_TRACE_MODE_REG_2_STOP_ON_ERR              , 17  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_STOP_ON_ERR );
+REG64_FLD( XBUS_PERV_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH       , 18  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_BANK_ON_RUNN_MATCH );
+REG64_FLD( XBUS_PERV_DBG_TRACE_MODE_REG_2_FORCE_TEST               , 19  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_FORCE_TEST );
+REG64_FLD( XBUS_PERV_DBG_TRACE_MODE_REG_2_ACCUM_HIST               , 20  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_ACCUM_HIST );
+REG64_FLD( XBUS_PERV_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ         , 21  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_FRZ_COUNT_ON_FRZ );
+
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST1_COND3_ENABLE            , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_COND3_ENABLE );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST2_COND3_ENABLE            , 1   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_COND3_ENABLE );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST3_COND3_ENABLE            , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST3_COND3_ENABLE );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST4_COND3_ENABLE            , 3   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST4_COND3_ENABLE );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE          , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_SLOW_LFSR_MODE );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE          , 5   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_SLOW_LFSR_MODE );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE          , 6   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST3_SLOW_LFSR_MODE );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE          , 7   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST4_SLOW_LFSR_MODE );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL     , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL     , 10  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL     , 12  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL     , 14  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL     , 16  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL     , 18  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP              , 32  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_STOP );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE            , 33  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_EXT_TRIG_ON_FREEZE );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL            , 34  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN        , 5   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS0_TRIG_SEL_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL            , 39  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN        , 5   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CORE_RAS1_TRIG_SEL_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_PC_TP_TRIG_SEL                , 44  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN            , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PC_TP_TRIG_SEL_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_ARM_SEL                       , 46  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL    );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_ARM_SEL_LEN                   , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_ARM_SEL_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL               , 50  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN           , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_LEVEL_SEL_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL               , 54  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN           , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_LEVEL_SEL_LEN );
+
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO    , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO    , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO    , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO    , 6   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_DO_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO    , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_DO_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO    , 10  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_WAITN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_WAITN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_WAITN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_WAITN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK  , 36  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION1_ACTION_BANK );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK  , 37  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_CONDITION2_ACTION_BANK );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK  , 38  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK  , 39  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION1_ACTION_BANK );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK  , 40  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_CONDITION2_ACTION_BANK );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK  , 41  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT       , 48  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN   , 3   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT       , 52  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN   , 3   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN );
+REG64_FLD( XBUS_PERV_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR );
+
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_LINK_PAIR                          , 0   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK_PAIR  );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_DISABLE_SL_ECC                     , 1   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_SL_ECC );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_CRC_LANE_ID                        , 2   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CRC_LANE_ID );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_EDPL_LANE_ID                       , 3   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_EDPL_LANE_ID );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_SL_UE_CRC_ERR                      , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_SL_UE_CRC_ERR );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_REPORT_SL_CHKBIT_ERR               , 5   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPORT_SL_CHKBIT_ERR );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_BW_SAMPLE_SIZE                     , 6   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BW_SAMPLE_SIZE );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_BW_WINDOW_SIZE                     , 7   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_BW_WINDOW_SIZE );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_UNUSED1                            , 8   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1    );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_UNUSED1_LEN                        , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1_LEN );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_PACKET_DELAY_LIMIT                 , 12  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PACKET_DELAY_LIMIT );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_PACKET_DELAY_LIMIT_LEN             , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_PACKET_DELAY_LIMIT_LEN );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_TDM_DELAY                          , 16  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDM_DELAY  );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_TDM_DELAY_LEN                      , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TDM_DELAY_LEN );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_AUTO_TDM_TX                        , 20  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_TX );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_AUTO_TDM_RX                        , 21  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_RX );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_AUTO_TDM_AND_NOT_OR                , 22  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_AND_NOT_OR );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_UNUSED2                            , 23  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2    );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_AUTO_TDM_BW_DIFF                   , 24  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_BW_DIFF );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_AUTO_TDM_BW_DIFF_LEN               , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_BW_DIFF_LEN );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_AUTO_TDM_ERROR_RATE                , 28  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_ERROR_RATE );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_AUTO_TDM_ERROR_RATE_LEN            , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_ERROR_RATE_LEN );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_UNUSED3                            , 32  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED3    );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_UNUSED3_LEN                        , 16  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED3_LEN );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_TIMEOUT                            , 48  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT    );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_TIMEOUT_LEN                        , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_LEN );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_TIMER_1US                          , 52  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_1US  );
+REG64_FLD( XBUS_LL0_IOEL_CONFIG_TIMER_1US_LEN                      , 12  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_1US_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_UNUSED0A                          , 0   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED0A   );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_LINK0_STARTUP                     , 1   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_STARTUP );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_UNUSED0B                          , 2   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED0B   );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_UNUSED0B_LEN                      , 6   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED0B_LEN );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND             , 8   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ERR_INJ_COMMAND );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LEN         , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ERR_INJ_COMMAND_LEN );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES       , 12  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ERR_INJ_COMMAND_LANES );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES_LEN   , 16  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ERR_INJ_COMMAND_LANES_LEN );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_LINK0_COMMAND                     , 28  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_COMMAND );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_LINK0_COMMAND_LEN                 , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_COMMAND_LEN );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_UNUSED1A                          , 32  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1A   );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_LINK1_STARTUP                     , 33  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_STARTUP );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_UNUSED1B                          , 34  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1B   );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_UNUSED1B_LEN                      , 6   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1B_LEN );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND             , 40  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ERR_INJ_COMMAND );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LEN         , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ERR_INJ_COMMAND_LEN );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES       , 44  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ERR_INJ_COMMAND_LANES );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES_LEN   , 16  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ERR_INJ_COMMAND_LANES_LEN );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_LINK1_COMMAND                     , 60  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_COMMAND );
+REG64_FLD( XBUS_LL0_IOEL_CONTROL_LINK1_COMMAND_LEN                 , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_COMMAND_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_DLL_STATUS_LINK0_CURRENT_STATE            , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_CURRENT_STATE );
+REG64_FLD( XBUS_LL0_IOEL_DLL_STATUS_LINK0_CURRENT_STATE_LEN        , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_CURRENT_STATE_LEN );
+REG64_FLD( XBUS_LL0_IOEL_DLL_STATUS_LINK0_PRIOR_STATE              , 12  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_PRIOR_STATE );
+REG64_FLD( XBUS_LL0_IOEL_DLL_STATUS_LINK0_PRIOR_STATE_LEN          , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_PRIOR_STATE_LEN );
+REG64_FLD( XBUS_LL0_IOEL_DLL_STATUS_LINK0_MAX_PKT_TIMER            , 19  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_MAX_PKT_TIMER );
+REG64_FLD( XBUS_LL0_IOEL_DLL_STATUS_LINK0_MAX_PKT_TIMER_LEN        , 5   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_MAX_PKT_TIMER_LEN );
+REG64_FLD( XBUS_LL0_IOEL_DLL_STATUS_LINK1_CURRENT_STATE            , 28  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_CURRENT_STATE );
+REG64_FLD( XBUS_LL0_IOEL_DLL_STATUS_LINK1_CURRENT_STATE_LEN        , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_CURRENT_STATE_LEN );
+REG64_FLD( XBUS_LL0_IOEL_DLL_STATUS_LINK1_PRIOR_STATE              , 36  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_PRIOR_STATE );
+REG64_FLD( XBUS_LL0_IOEL_DLL_STATUS_LINK1_PRIOR_STATE_LEN          , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_PRIOR_STATE_LEN );
+REG64_FLD( XBUS_LL0_IOEL_DLL_STATUS_LINK1_MAX_PKT_TIMER            , 43  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_MAX_PKT_TIMER );
+REG64_FLD( XBUS_LL0_IOEL_DLL_STATUS_LINK1_MAX_PKT_TIMER_LEN        , 5   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_MAX_PKT_TIMER_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_ERR_INJ_LFSR_LFSR                         , 0   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LFSR       );
+REG64_FLD( XBUS_LL0_IOEL_ERR_INJ_LFSR_LFSR_LEN                     , 61  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LFSR_LEN   );
+
+REG64_FLD( XBUS_LL0_IOEL_FIR_ACTION0_REG_ACTION0                   , 0   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( XBUS_LL0_IOEL_FIR_ACTION0_REG_ACTION0_LEN               , 64  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_FIR_ACTION1_REG_ACTION1                   , 0   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( XBUS_LL0_IOEL_FIR_ACTION1_REG_ACTION1_LEN               , 64  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP_VALID        , 0   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ROUND_TRIP_VALID );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP              , 2   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ROUND_TRIP );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP_LEN          , 10  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ROUND_TRIP_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP_VALID        , 12  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ROUND_TRIP_VALID );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP              , 14  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ROUND_TRIP );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP_LEN          , 10  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ROUND_TRIP_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_VALID , 24  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LOCAL_LATENCY_DIFFERENCE_VALID );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LOCAL_LATENCY_LONGER_LINK     , 25  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LOCAL_LATENCY_LONGER_LINK );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE      , 29  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LOCAL_LATENCY_DIFFERENCE );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_LEN  , 7   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LOCAL_LATENCY_DIFFERENCE_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_VALID , 36  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REMOTE_LATENCY_DIFFERENCE_VALID );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_REMOTE_LATENCY_LONGER_LINK    , 37  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REMOTE_LATENCY_LONGER_LINK );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE     , 41  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REMOTE_LATENCY_DIFFERENCE );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_LEN , 7   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REMOTE_LATENCY_DIFFERENCE_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LINK0_TOD_LATENCY             , 49  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_TOD_LATENCY );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LINK0_TOD_LATENCY_LEN         , 7   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_TOD_LATENCY_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LINK1_TOD_LATENCY             , 57  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_TOD_LATENCY );
+REG64_FLD( XBUS_LL0_IOEL_LAT_MEASURE_LINK1_TOD_LATENCY_LEN         , 7   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_TOD_LATENCY_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_0           , 0   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_0 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_0_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_0_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_1           , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_1 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_1_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_1_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_2           , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_2 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_2_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_2_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_3           , 12  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_3 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_3_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_3_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_4           , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_4 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_4_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_4_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_5           , 20  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_5 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_5_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_5_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_6           , 24  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_6 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_6_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_6_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_7           , 28  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_7 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_7_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_7_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_8           , 32  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_8 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_8_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_8_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_9           , 36  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_9 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_9_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_9_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_10          , 40  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_10 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_10_LEN      , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_10_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_11          , 44  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_11 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_11_LEN      , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_11_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_LINK0_ERROR_STATUS_RESET_KEEPER           , 0   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESET_KEEPER );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_ERROR_STATUS_CE                     , 1   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CE         );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_ERROR_STATUS_CE_LEN                 , 3   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CE_LEN     );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_ERROR_STATUS_UE                     , 8   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UE         );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_ERROR_STATUS_UE_LEN                 , 2   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UE_LEN     );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_ERROR_STATUS_TRAIN                  , 16  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAIN      );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_ERROR_STATUS_TRAIN_LEN              , 2   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAIN_LEN  );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_ERROR_STATUS_UNRECOV                , 24  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNRECOV    );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_ERROR_STATUS_UNRECOV_LEN            , 11  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNRECOV_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_ERROR_STATUS_INTERNAL               , 44  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INTERNAL   );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_ERROR_STATUS_INTERNAL_LEN           , 18  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INTERNAL_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_MAX_TIMEOUT                    , 0   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MAX_TIMEOUT );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_MAX_TIMEOUT_LEN                , 16  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MAX_TIMEOUT_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_FRAME_CAP_VALID                , 16  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_VALID );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_FRAME_CAP_INST                 , 17  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_INST );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_FRAME_CAP_ADDR                 , 19  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_ADDR );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_FRAME_CAP_ADDR_LEN             , 5   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_ADDR_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_FRAME_CAP_SYN                  , 24  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_SYN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_FRAME_CAP_SYN_LEN              , 8   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_SYN_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_REPLAY_CAP_VALID               , 32  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_VALID );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_REPLAY_CAP_INST                , 34  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_INST );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_REPLAY_CAP_ADDR                , 37  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_ADDR );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_REPLAY_CAP_ADDR_LEN            , 7   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_ADDR_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_REPLAY_CAP_SYN                 , 44  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_SYN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_REPLAY_CAP_SYN_LEN             , 8   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_SYN_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_ACK_FIFO_CAP_VALID             , 52  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_VALID );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_ACK_FIFO_CAP_ADDR              , 57  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_ADDR );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_INFO_ACK_FIFO_CAP_ADDR_LEN          , 7   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_ADDR_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_LINK0_QUALITY_TX_BW                       , 1   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_TX_BW      );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_QUALITY_TX_BW_LEN                   , 11  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_TX_BW_LEN  );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_QUALITY_RX_BW                       , 13  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_RX_BW      );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_QUALITY_RX_BW_LEN                   , 11  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_RX_BW_LEN  );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_QUALITY_ERROR_RATE                  , 25  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_RATE );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_QUALITY_ERROR_RATE_LEN              , 23  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_RATE_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC            , 0   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LEN        , 28  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1    , 28  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED1 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1_LEN , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED1_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0     , 36  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN0 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN0_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1     , 44  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN1 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN1_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2    , 52  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED2 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2_LEN , 3   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED2_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_VALID          , 55  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_VALID );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3    , 56  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED3 );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3_LEN , 3   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED3_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE       , 59  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LANE );
+REG64_FLD( XBUS_LL0_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN   , 5   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LANE_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_0           , 0   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_0 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_0_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_0_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_1           , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_1 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_1_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_1_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_2           , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_2 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_2_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_2_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_3           , 12  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_3 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_3_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_3_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_4           , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_4 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_4_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_4_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_5           , 20  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_5 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_5_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_5_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_6           , 24  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_6 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_6_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_6_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_7           , 28  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_7 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_7_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_7_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_8           , 32  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_8 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_8_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_8_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_9           , 36  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_9 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_9_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_9_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_10          , 40  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_10 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_10_LEN      , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_10_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_11          , 44  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_11 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_11_LEN      , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_11_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_LINK1_ERROR_STATUS_RESET_KEEPER           , 0   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_RESET_KEEPER );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_ERROR_STATUS_CE                     , 1   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CE         );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_ERROR_STATUS_CE_LEN                 , 3   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_CE_LEN     );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_ERROR_STATUS_UE                     , 8   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UE         );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_ERROR_STATUS_UE_LEN                 , 2   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UE_LEN     );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_ERROR_STATUS_TRAIN                  , 16  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAIN      );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_ERROR_STATUS_TRAIN_LEN              , 2   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_TRAIN_LEN  );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_ERROR_STATUS_UNRECOV                , 24  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNRECOV    );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_ERROR_STATUS_UNRECOV_LEN            , 11  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_UNRECOV_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_ERROR_STATUS_INTERNAL               , 44  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INTERNAL   );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_ERROR_STATUS_INTERNAL_LEN           , 18  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_INTERNAL_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_MAX_TIMEOUT                    , 0   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MAX_TIMEOUT );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_MAX_TIMEOUT_LEN                , 16  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_MAX_TIMEOUT_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_FRAME_CAP_VALID                , 16  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_VALID );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_FRAME_CAP_INST                 , 17  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_INST );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_FRAME_CAP_ADDR                 , 19  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_ADDR );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_FRAME_CAP_ADDR_LEN             , 5   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_ADDR_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_FRAME_CAP_SYN                  , 24  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_SYN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_FRAME_CAP_SYN_LEN              , 8   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_SYN_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_REPLAY_CAP_VALID               , 32  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_VALID );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_REPLAY_CAP_INST                , 34  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_INST );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_REPLAY_CAP_ADDR                , 37  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_ADDR );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_REPLAY_CAP_ADDR_LEN            , 7   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_ADDR_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_REPLAY_CAP_SYN                 , 44  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_SYN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_REPLAY_CAP_SYN_LEN             , 8   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_SYN_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_ACK_FIFO_CAP_VALID             , 52  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_VALID );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_ACK_FIFO_CAP_ADDR              , 57  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_ADDR );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_INFO_ACK_FIFO_CAP_ADDR_LEN          , 7   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_ADDR_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_LINK1_QUALITY_TX_BW                       , 1   , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_TX_BW      );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_QUALITY_TX_BW_LEN                   , 11  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_TX_BW_LEN  );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_QUALITY_RX_BW                       , 13  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_RX_BW      );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_QUALITY_RX_BW_LEN                   , 11  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_RX_BW_LEN  );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_QUALITY_ERROR_RATE                  , 25  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_RATE );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_QUALITY_ERROR_RATE_LEN              , 23  , SH_UNT_XBUS     , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_RATE_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC            , 0   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LEN        , 28  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1    , 28  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED1 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1_LEN , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED1_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0     , 36  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN0 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN0_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1     , 44  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN1 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN1_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2    , 52  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED2 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2_LEN , 3   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED2_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_VALID          , 55  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_VALID );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3    , 56  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED3 );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3_LEN , 3   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED3_LEN );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE       , 59  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LANE );
+REG64_FLD( XBUS_LL0_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN   , 5   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LANE_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER           , 0   , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER );
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_LEN       , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_1         , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_1 );
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_1_LEN     , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_1_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_2         , 32  , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_2 );
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_2_LEN     , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_2_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_3         , 48  , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_3 );
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_3_LEN     , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_3_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_4         , 0   , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_4 );
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_4_LEN     , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_4_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_5         , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_5 );
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_5_LEN     , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_5_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_6         , 32  , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_6 );
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_6_LEN     , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_6_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_7         , 48  , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_7 );
+REG64_FLD( XBUS_LL0_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_7_LEN     , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_7_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_0                  , 0   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_0   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_0_LEN              , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_0_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_1                  , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_1   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_1_LEN              , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_1_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_2                  , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_2   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_2_LEN              , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_2_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_3                  , 24  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_3   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_3_LEN              , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_3_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_4                  , 32  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_4   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_4_LEN              , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_4_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_5                  , 40  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_5   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_5_LEN              , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_5_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_6                  , 48  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_6   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_6_LEN              , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_6_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_7                  , 56  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_7   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_SEL_CONFIG_SELECT_7_LEN              , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_7_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_0                , 0   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_0   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_0_LEN            , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_0_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_1                , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_1   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_1_LEN            , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_1_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_2                , 4   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_2   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_2_LEN            , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_2_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_3                , 6   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_3   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_3_LEN            , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_3_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_4                , 8   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_4   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_4_LEN            , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_4_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_5                , 10  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_5   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_5_LEN            , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_5_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_6                , 12  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_6   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_6_LEN            , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_6_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_7                , 14  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_7   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_ENABLE_7_LEN            , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_7_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_0                  , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_0     );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_0_LEN              , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_0_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_1                  , 18  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_1     );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_1_LEN              , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_1_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_2                  , 20  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_2     );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_2_LEN              , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_2_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_3                  , 22  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_3     );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_3_LEN              , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_3_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_4                  , 24  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_4     );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_4_LEN              , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_4_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_5                  , 26  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_5     );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_5_LEN              , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_5_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_6                  , 28  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_6     );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_6_LEN              , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_6_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_7                  , 30  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_7     );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_SIZE_7_LEN              , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_7_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_PMULET_FREEZE_MODE      , 32  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMULET_FREEZE_MODE );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_COMMON_FREEZE_MODE      , 33  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_COMMON_FREEZE_MODE );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_RESET_MODE              , 34  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESET_MODE );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_PERFTRACE_ENABLE        , 35  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFTRACE_ENABLE );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_PERFTRACE_FIXED_WINDOW  , 36  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFTRACE_FIXED_WINDOW );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_PERFTRACE_PRESCALE      , 37  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFTRACE_PRESCALE );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_PERFTRACE_MODE          , 38  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFTRACE_MODE );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_PERFTRACE_MODE_LEN      , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFTRACE_MODE_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_CONFIG_0                , 40  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIG_0   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_CONFIG_0_LEN            , 12  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIG_0_LEN );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_CONFIG_1                , 52  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIG_1   );
+REG64_FLD( XBUS_LL0_IOEL_PERF_TRACE_CONFIG_CONFIG_1_LEN            , 12  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIG_1_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_TB_SEL            , 0   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TB_SEL );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_TB_SEL_LEN        , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TB_SEL_LEN );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_TAP_SEL           , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TAP_SEL );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_TAP_SEL_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TAP_SEL_LEN );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_ENABLE            , 8   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_ENABLE );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_ENABLE_LEN        , 3   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_ENABLE_LEN );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED1           , 11  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED1 );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED1_LEN       , 15  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED1_LEN );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_CLEAR       , 26  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_CLEAR );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_CLEAR       , 27  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_CLEAR );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TB_CLEAR      , 28  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TB_CLEAR );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TAP_CLEAR     , 29  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TAP_CLEAR );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TAP_STOP      , 30  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TAP_STOP );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED2           , 31  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED2 );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT       , 32  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_COUNT );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT_LEN   , 16  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_COUNT_LEN );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT       , 48  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_COUNT );
+REG64_FLD( XBUS_LL0_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT_LEN   , 16  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_COUNT_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_SEC_CONFIG_ENABLE_ERR_INJ                 , 0   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_ERR_INJ );
+REG64_FLD( XBUS_LL0_IOEL_SEC_CONFIG_UNUSED4                        , 1   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNUSED4    );
+REG64_FLD( XBUS_LL0_IOEL_SEC_CONFIG_UNUSED4_LEN                    , 15  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNUSED4_LEN );
+REG64_FLD( XBUS_LL0_IOEL_SEC_CONFIG_SBE_ERROR_RATE                 , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SBE_ERROR_RATE );
+REG64_FLD( XBUS_LL0_IOEL_SEC_CONFIG_SBE_ERROR_RATE_LEN             , 2   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_SBE_ERROR_RATE_LEN );
+REG64_FLD( XBUS_LL0_IOEL_SEC_CONFIG_RAND_ERROR_RATE                , 18  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RAND_ERROR_RATE );
+REG64_FLD( XBUS_LL0_IOEL_SEC_CONFIG_RAND_ERROR_RATE_LEN            , 6   , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_RAND_ERROR_RATE_LEN );
+REG64_FLD( XBUS_LL0_IOEL_SEC_CONFIG_UNUSED5                        , 24  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNUSED5    );
+REG64_FLD( XBUS_LL0_IOEL_SEC_CONFIG_UNUSED5_LEN                    , 24  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNUSED5_LEN );
+REG64_FLD( XBUS_LL0_IOEL_SEC_CONFIG_EDPL_RATE                      , 48  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_EDPL_RATE  );
+REG64_FLD( XBUS_LL0_IOEL_SEC_CONFIG_EDPL_RATE_LEN                  , 16  , SH_UNT_XBUS     , SH_ACS_SCOM_RW  ,
+           SH_FLD_EDPL_RATE_LEN );
+
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_TB_SEL            , 0   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TB_SEL );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_TB_SEL_LEN        , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TB_SEL_LEN );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_TAP_SEL           , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TAP_SEL );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_TAP_SEL_LEN       , 4   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TAP_SEL_LEN );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_ENABLE            , 8   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_ENABLE );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_ENABLE_LEN        , 2   , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_ENABLE_LEN );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED1           , 10  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED1 );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED1_LEN       , 16  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED1_LEN );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_CLEAR       , 26  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_CLEAR );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_CLEAR       , 27  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_CLEAR );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TB_CLEAR      , 28  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TB_CLEAR );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_CLEAR     , 29  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TAP_CLEAR );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_STOP      , 30  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TAP_STOP );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED2           , 31  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED2 );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT       , 32  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_COUNT );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT_LEN   , 16  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_COUNT_LEN );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT       , 48  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_COUNT );
+REG64_FLD( XBUS_LL0_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT_LEN   , 16  , SH_UNT_XBUS     , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_COUNT_LEN );
+
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_TRAINED        , 0   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TRAINED );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_TRAINED        , 1   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TRAINED );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_REPLAY_THRESHOLD , 4   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_REPLAY_THRESHOLD );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_REPLAY_THRESHOLD , 5   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_REPLAY_THRESHOLD );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_CRC_ERROR      , 6   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_CRC_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_CRC_ERROR      , 7   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_CRC_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_NAK_RECEIVED   , 8   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_NAK_RECEIVED );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_NAK_RECEIVED   , 9   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_NAK_RECEIVED );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_REPLAY_BUFFER_FULL , 10  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_REPLAY_BUFFER_FULL );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_REPLAY_BUFFER_FULL , 11  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_REPLAY_BUFFER_FULL );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_SL_ECC_THRESHOLD , 12  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_THRESHOLD );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_SL_ECC_THRESHOLD , 13  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_THRESHOLD );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_SL_ECC_CORRECTABLE , 14  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_CORRECTABLE );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_SL_ECC_CORRECTABLE , 15  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_CORRECTABLE );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_SL_ECC_UE      , 16  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_UE );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_SL_ECC_UE      , 17  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_UE );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_TCOMPLETE_BAD  , 40  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TCOMPLETE_BAD );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_TCOMPLETE_BAD  , 41  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TCOMPLETE_BAD );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_SPARE_DONE     , 44  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SPARE_DONE );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_SPARE_DONE     , 45  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SPARE_DONE );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_TOO_MANY_CRC_ERRORS , 46  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TOO_MANY_CRC_ERRORS );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_TOO_MANY_CRC_ERRORS , 47  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TOO_MANY_CRC_ERRORS );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_PSAVE_INVALID_STATE  , 51  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSAVE_INVALID_STATE );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_CORRECTABLE_ARRAY_ERROR , 52  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_CORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_CORRECTABLE_ARRAY_ERROR , 53  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_CORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR , 54  , SH_UNT_XBUS     ,
+           SH_ACS_SCOM2_OR , SH_FLD_LINK0_UNCORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR , 55  , SH_UNT_XBUS     ,
+           SH_ACS_SCOM2_OR , SH_FLD_LINK1_UNCORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_TRAINING_FAILED , 56  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TRAINING_FAILED );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_TRAINING_FAILED , 57  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TRAINING_FAILED );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_UNRECOVERABLE_ERROR , 58  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_UNRECOVERABLE_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_UNRECOVERABLE_ERROR , 59  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_UNRECOVERABLE_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK0_INTERNAL_ERROR , 60  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_INTERNAL_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_LINK1_INTERNAL_ERROR , 61  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_INTERNAL_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_SCOM_ERR_DUP         , 62  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_MASK_REG_SCOM_ERR             , 63  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_TRAINED             , 0   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TRAINED );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_TRAINED             , 1   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TRAINED );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_REPLAY_THRESHOLD    , 4   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_REPLAY_THRESHOLD );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_REPLAY_THRESHOLD    , 5   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_REPLAY_THRESHOLD );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_CRC_ERROR           , 6   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_CRC_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_CRC_ERROR           , 7   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_CRC_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_NAK_RECEIVED        , 8   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_NAK_RECEIVED );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_NAK_RECEIVED        , 9   , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_NAK_RECEIVED );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_REPLAY_BUFFER_FULL  , 10  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_REPLAY_BUFFER_FULL );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_REPLAY_BUFFER_FULL  , 11  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_REPLAY_BUFFER_FULL );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_SL_ECC_THRESHOLD    , 12  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_THRESHOLD );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_SL_ECC_THRESHOLD    , 13  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_THRESHOLD );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_SL_ECC_CORRECTABLE  , 14  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_CORRECTABLE );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_SL_ECC_CORRECTABLE  , 15  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_CORRECTABLE );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_SL_ECC_UE           , 16  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_UE );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_SL_ECC_UE           , 17  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_UE );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_TCOMPLETE_BAD       , 40  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TCOMPLETE_BAD );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_TCOMPLETE_BAD       , 41  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TCOMPLETE_BAD );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_SPARE_DONE          , 44  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SPARE_DONE );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_SPARE_DONE          , 45  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SPARE_DONE );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_TOO_MANY_CRC_ERRORS , 46  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TOO_MANY_CRC_ERRORS );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_TOO_MANY_CRC_ERRORS , 47  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TOO_MANY_CRC_ERRORS );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_PSAVE_INVALID_STATE       , 51  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSAVE_INVALID_STATE );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_CORRECTABLE_ARRAY_ERROR , 52  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_CORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_CORRECTABLE_ARRAY_ERROR , 53  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_CORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR , 54  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_UNCORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR , 55  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_UNCORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_TRAINING_FAILED     , 56  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TRAINING_FAILED );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_TRAINING_FAILED     , 57  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TRAINING_FAILED );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_UNRECOVERABLE_ERROR , 58  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_UNRECOVERABLE_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_UNRECOVERABLE_ERROR , 59  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_UNRECOVERABLE_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK0_INTERNAL_ERROR      , 60  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_INTERNAL_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_LINK1_INTERNAL_ERROR      , 61  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_INTERNAL_ERROR );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_SCOM_ERR_DUP              , 62  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+REG64_FLD( XBUS_LL0_LL0_LL0_IOEL_FIR_REG_SCOM_ERR                  , 63  , SH_UNT_XBUS     , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_LINK_PAIR                        , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK_PAIR  );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_DISABLE_SL_ECC                   , 1   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_SL_ECC );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_CRC_LANE_ID                      , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CRC_LANE_ID );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_EDPL_LANE_ID                     , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_EDPL_LANE_ID );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_SL_UE_CRC_ERR                    , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SL_UE_CRC_ERR );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_REPORT_SL_CHKBIT_ERR             , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPORT_SL_CHKBIT_ERR );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_BW_SAMPLE_SIZE                   , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BW_SAMPLE_SIZE );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_BW_WINDOW_SIZE                   , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BW_WINDOW_SIZE );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_UNUSED1                          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1    );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_UNUSED1_LEN                      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_PACKET_DELAY_LIMIT               , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PACKET_DELAY_LIMIT );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_PACKET_DELAY_LIMIT_LEN           , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PACKET_DELAY_LIMIT_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_TDM_DELAY                        , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDM_DELAY  );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_TDM_DELAY_LEN                    , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDM_DELAY_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_AUTO_TDM_TX                      , 20  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_TX );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_AUTO_TDM_RX                      , 21  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_RX );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_AUTO_TDM_AND_NOT_OR              , 22  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_AND_NOT_OR );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_UNUSED2                          , 23  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED2    );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_AUTO_TDM_BW_DIFF                 , 24  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_BW_DIFF );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_AUTO_TDM_BW_DIFF_LEN             , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_BW_DIFF_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_AUTO_TDM_ERROR_RATE              , 28  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_ERROR_RATE );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_AUTO_TDM_ERROR_RATE_LEN          , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AUTO_TDM_ERROR_RATE_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_UNUSED3                          , 32  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED3    );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_UNUSED3_LEN                      , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED3_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_TIMEOUT                          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT    );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_TIMEOUT_LEN                      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_TIMER_1US                        , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_1US  );
+REG64_FLD( XBUS_1_LL1_IOEL_CONFIG_TIMER_1US_LEN                    , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TIMER_1US_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_UNUSED0A                        , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED0A   );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_LINK0_STARTUP                   , 1   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_STARTUP );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_UNUSED0B                        , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED0B   );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_UNUSED0B_LEN                    , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED0B_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND           , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ERR_INJ_COMMAND );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LEN       , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ERR_INJ_COMMAND_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES     , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ERR_INJ_COMMAND_LANES );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_LINK0_ERR_INJ_COMMAND_LANES_LEN , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ERR_INJ_COMMAND_LANES_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_LINK0_COMMAND                   , 28  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_COMMAND );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_LINK0_COMMAND_LEN               , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_COMMAND_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_UNUSED1A                        , 32  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1A   );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_LINK1_STARTUP                   , 33  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_STARTUP );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_UNUSED1B                        , 34  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1B   );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_UNUSED1B_LEN                    , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNUSED1B_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND           , 40  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ERR_INJ_COMMAND );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LEN       , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ERR_INJ_COMMAND_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES     , 44  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ERR_INJ_COMMAND_LANES );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_LINK1_ERR_INJ_COMMAND_LANES_LEN , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ERR_INJ_COMMAND_LANES_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_LINK1_COMMAND                   , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_COMMAND );
+REG64_FLD( XBUS_1_LL1_IOEL_CONTROL_LINK1_COMMAND_LEN               , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_COMMAND_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_DLL_STATUS_LINK0_CURRENT_STATE          , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_CURRENT_STATE );
+REG64_FLD( XBUS_1_LL1_IOEL_DLL_STATUS_LINK0_CURRENT_STATE_LEN      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_CURRENT_STATE_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_DLL_STATUS_LINK0_PRIOR_STATE            , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_PRIOR_STATE );
+REG64_FLD( XBUS_1_LL1_IOEL_DLL_STATUS_LINK0_PRIOR_STATE_LEN        , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_PRIOR_STATE_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_DLL_STATUS_LINK0_MAX_PKT_TIMER          , 19  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_MAX_PKT_TIMER );
+REG64_FLD( XBUS_1_LL1_IOEL_DLL_STATUS_LINK0_MAX_PKT_TIMER_LEN      , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK0_MAX_PKT_TIMER_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_DLL_STATUS_LINK1_CURRENT_STATE          , 28  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_CURRENT_STATE );
+REG64_FLD( XBUS_1_LL1_IOEL_DLL_STATUS_LINK1_CURRENT_STATE_LEN      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_CURRENT_STATE_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_DLL_STATUS_LINK1_PRIOR_STATE            , 36  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_PRIOR_STATE );
+REG64_FLD( XBUS_1_LL1_IOEL_DLL_STATUS_LINK1_PRIOR_STATE_LEN        , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_PRIOR_STATE_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_DLL_STATUS_LINK1_MAX_PKT_TIMER          , 43  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_MAX_PKT_TIMER );
+REG64_FLD( XBUS_1_LL1_IOEL_DLL_STATUS_LINK1_MAX_PKT_TIMER_LEN      , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_LINK1_MAX_PKT_TIMER_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_ERR_INJ_LFSR_LFSR                       , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LFSR       );
+REG64_FLD( XBUS_1_LL1_IOEL_ERR_INJ_LFSR_LFSR_LEN                   , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LFSR_LEN   );
+
+REG64_FLD( XBUS_1_LL1_IOEL_FIR_ACTION0_REG_ACTION0                 , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0    );
+REG64_FLD( XBUS_1_LL1_IOEL_FIR_ACTION0_REG_ACTION0_LEN             , 64  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION0_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_FIR_ACTION1_REG_ACTION1                 , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1    );
+REG64_FLD( XBUS_1_LL1_IOEL_FIR_ACTION1_REG_ACTION1_LEN             , 64  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ACTION1_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP_VALID      , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ROUND_TRIP_VALID );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ROUND_TRIP );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LINK0_ROUND_TRIP_LEN        , 10  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_ROUND_TRIP_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP_VALID      , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ROUND_TRIP_VALID );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP            , 14  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ROUND_TRIP );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LINK1_ROUND_TRIP_LEN        , 10  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_ROUND_TRIP_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_VALID , 24  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LOCAL_LATENCY_DIFFERENCE_VALID );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LOCAL_LATENCY_LONGER_LINK   , 25  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LOCAL_LATENCY_LONGER_LINK );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE    , 29  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LOCAL_LATENCY_DIFFERENCE );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LOCAL_LATENCY_DIFFERENCE_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LOCAL_LATENCY_DIFFERENCE_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_VALID , 36  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REMOTE_LATENCY_DIFFERENCE_VALID );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_REMOTE_LATENCY_LONGER_LINK  , 37  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REMOTE_LATENCY_LONGER_LINK );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE   , 41  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REMOTE_LATENCY_DIFFERENCE );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_REMOTE_LATENCY_DIFFERENCE_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REMOTE_LATENCY_DIFFERENCE_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LINK0_TOD_LATENCY           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_TOD_LATENCY );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LINK0_TOD_LATENCY_LEN       , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK0_TOD_LATENCY_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LINK1_TOD_LATENCY           , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_TOD_LATENCY );
+REG64_FLD( XBUS_1_LL1_IOEL_LAT_MEASURE_LINK1_TOD_LATENCY_LEN       , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LINK1_TOD_LATENCY_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_0         , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_0 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_0_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_0_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_1         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_1 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_1_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_1_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_2         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_2 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_2_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_2_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_3         , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_3 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_3_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_3_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_4         , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_4 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_4_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_4_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_5         , 20  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_5 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_5_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_5_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_6         , 24  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_6 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_6_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_6_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_7         , 28  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_7 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_7_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_7_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_8         , 32  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_8 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_8_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_8_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_9         , 36  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_9 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_9_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_9_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_10        , 40  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_10 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_10_LEN    , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_10_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_11        , 44  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_11 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_EDPL_STATUS_ERROR_COUNT_11_LEN    , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_11_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_ERROR_STATUS_RESET_KEEPER         , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET_KEEPER );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_ERROR_STATUS_CE                   , 1   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CE         );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_ERROR_STATUS_CE_LEN               , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CE_LEN     );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_ERROR_STATUS_UE                   , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UE         );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_ERROR_STATUS_UE_LEN               , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UE_LEN     );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_ERROR_STATUS_TRAIN                , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAIN      );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_ERROR_STATUS_TRAIN_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAIN_LEN  );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_ERROR_STATUS_UNRECOV              , 24  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNRECOV    );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_ERROR_STATUS_UNRECOV_LEN          , 11  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNRECOV_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_ERROR_STATUS_INTERNAL             , 44  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INTERNAL   );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_ERROR_STATUS_INTERNAL_LEN         , 18  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INTERNAL_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_MAX_TIMEOUT                  , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MAX_TIMEOUT );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_MAX_TIMEOUT_LEN              , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MAX_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_FRAME_CAP_VALID              , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_VALID );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_FRAME_CAP_INST               , 17  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_INST );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_FRAME_CAP_ADDR               , 19  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_ADDR );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_FRAME_CAP_ADDR_LEN           , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_ADDR_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_FRAME_CAP_SYN                , 24  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_SYN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_FRAME_CAP_SYN_LEN            , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_SYN_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_REPLAY_CAP_VALID             , 32  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_VALID );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_REPLAY_CAP_INST              , 34  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_INST );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_REPLAY_CAP_ADDR              , 37  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_ADDR );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_REPLAY_CAP_ADDR_LEN          , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_ADDR_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_REPLAY_CAP_SYN               , 44  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_SYN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_REPLAY_CAP_SYN_LEN           , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_SYN_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_ACK_FIFO_CAP_VALID           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_VALID );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_ACK_FIFO_CAP_ADDR            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_ADDR );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_INFO_ACK_FIFO_CAP_ADDR_LEN        , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_ADDR_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_QUALITY_TX_BW                     , 1   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_TX_BW      );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_QUALITY_TX_BW_LEN                 , 11  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_TX_BW_LEN  );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_QUALITY_RX_BW                     , 13  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_RX_BW      );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_QUALITY_RX_BW_LEN                 , 11  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_RX_BW_LEN  );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_QUALITY_ERROR_RATE                , 25  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_RATE );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_QUALITY_ERROR_RATE_LEN            , 23  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_RATE_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC          , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LEN      , 28  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1  , 28  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED1 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED1_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0   , 36  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN0 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN0_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1   , 44  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN1 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN1_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED2 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED2_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_VALID        , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_VALID );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED3 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED3_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE     , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LANE );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK0_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LANE_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_0         , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_0 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_0_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_0_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_1         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_1 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_1_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_1_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_2         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_2 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_2_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_2_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_3         , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_3 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_3_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_3_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_4         , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_4 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_4_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_4_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_5         , 20  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_5 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_5_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_5_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_6         , 24  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_6 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_6_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_6_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_7         , 28  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_7 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_7_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_7_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_8         , 32  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_8 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_8_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_8_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_9         , 36  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_9 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_9_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_9_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_10        , 40  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_10 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_10_LEN    , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_10_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_11        , 44  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_11 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_EDPL_STATUS_ERROR_COUNT_11_LEN    , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_COUNT_11_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_ERROR_STATUS_RESET_KEEPER         , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET_KEEPER );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_ERROR_STATUS_CE                   , 1   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CE         );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_ERROR_STATUS_CE_LEN               , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CE_LEN     );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_ERROR_STATUS_UE                   , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UE         );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_ERROR_STATUS_UE_LEN               , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UE_LEN     );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_ERROR_STATUS_TRAIN                , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAIN      );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_ERROR_STATUS_TRAIN_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRAIN_LEN  );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_ERROR_STATUS_UNRECOV              , 24  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNRECOV    );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_ERROR_STATUS_UNRECOV_LEN          , 11  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNRECOV_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_ERROR_STATUS_INTERNAL             , 44  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INTERNAL   );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_ERROR_STATUS_INTERNAL_LEN         , 18  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INTERNAL_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_MAX_TIMEOUT                  , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MAX_TIMEOUT );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_MAX_TIMEOUT_LEN              , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MAX_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_FRAME_CAP_VALID              , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_VALID );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_FRAME_CAP_INST               , 17  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_INST );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_FRAME_CAP_ADDR               , 19  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_ADDR );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_FRAME_CAP_ADDR_LEN           , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_ADDR_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_FRAME_CAP_SYN                , 24  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_SYN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_FRAME_CAP_SYN_LEN            , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FRAME_CAP_SYN_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_REPLAY_CAP_VALID             , 32  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_VALID );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_REPLAY_CAP_INST              , 34  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_INST );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_REPLAY_CAP_ADDR              , 37  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_ADDR );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_REPLAY_CAP_ADDR_LEN          , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_ADDR_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_REPLAY_CAP_SYN               , 44  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_SYN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_REPLAY_CAP_SYN_LEN           , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPLAY_CAP_SYN_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_ACK_FIFO_CAP_VALID           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_VALID );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_ACK_FIFO_CAP_ADDR            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_ADDR );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_INFO_ACK_FIFO_CAP_ADDR_LEN        , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACK_FIFO_CAP_ADDR_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_QUALITY_TX_BW                     , 1   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_TX_BW      );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_QUALITY_TX_BW_LEN                 , 11  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_TX_BW_LEN  );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_QUALITY_RX_BW                     , 13  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_RX_BW      );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_QUALITY_RX_BW_LEN                 , 11  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_RX_BW_LEN  );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_QUALITY_ERROR_RATE                , 25  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_RATE );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_QUALITY_ERROR_RATE_LEN            , 23  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RO  ,
+           SH_FLD_ERROR_RATE_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC          , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LEN      , 28  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1  , 28  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED1 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED1_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED1_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0   , 36  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN0 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN0_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN0_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1   , 44  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN1 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_SLECC_SYN1_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_SLECC_SYN1_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED2 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED2_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED2_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_VALID        , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_VALID );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED3 );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_UNUSED3_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_UNUSED3_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE     , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LANE );
+REG64_FLD( XBUS_1_LL1_IOEL_LINK1_SYN_CAPTURE_LINK_CAP_CRC_LANE_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_LINK_CAP_CRC_LANE_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER         , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_LEN     , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_1       , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_1 );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_1_LEN   , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_1_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_2       , 32  , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_2 );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_2_LEN   , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_2_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_3       , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_3 );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_0_PERFMON_COUNTER_3_LEN   , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_3_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_4       , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_4 );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_4_LEN   , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_4_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_5       , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_5 );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_5_LEN   , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_5_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_6       , 32  , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_6 );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_6_LEN   , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_6_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_7       , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_7 );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_COUNTERS_1_PERFMON_COUNTER_7_LEN   , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_WCLRREG,
+           SH_FLD_PERFMON_COUNTER_7_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_0                , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_0   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_0_LEN            , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_0_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_1                , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_1   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_1_LEN            , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_1_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_2                , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_2   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_2_LEN            , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_2_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_3                , 24  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_3   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_3_LEN            , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_3_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_4                , 32  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_4   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_4_LEN            , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_4_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_5                , 40  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_5   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_5_LEN            , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_5_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_6                , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_6   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_6_LEN            , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_6_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_7                , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_7   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_SEL_CONFIG_SELECT_7_LEN            , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SELECT_7_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_0              , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_0   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_0_LEN          , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_0_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_1              , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_1   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_1_LEN          , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_1_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_2              , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_2   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_2_LEN          , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_2_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_3              , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_3   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_3_LEN          , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_3_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_4              , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_4   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_4_LEN          , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_4_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_5              , 10  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_5   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_5_LEN          , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_5_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_6              , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_6   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_6_LEN          , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_6_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_7              , 14  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_7   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_ENABLE_7_LEN          , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_7_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_0                , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_0     );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_0_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_0_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_1                , 18  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_1     );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_1_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_1_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_2                , 20  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_2     );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_2_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_2_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_3                , 22  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_3     );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_3_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_3_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_4                , 24  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_4     );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_4_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_4_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_5                , 26  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_5     );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_5_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_5_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_6                , 28  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_6     );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_6_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_6_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_7                , 30  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_7     );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_SIZE_7_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SIZE_7_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_PMULET_FREEZE_MODE    , 32  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PMULET_FREEZE_MODE );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_COMMON_FREEZE_MODE    , 33  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_COMMON_FREEZE_MODE );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_RESET_MODE            , 34  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RESET_MODE );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_PERFTRACE_ENABLE      , 35  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFTRACE_ENABLE );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_PERFTRACE_FIXED_WINDOW , 36  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFTRACE_FIXED_WINDOW );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_PERFTRACE_PRESCALE    , 37  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFTRACE_PRESCALE );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_PERFTRACE_MODE        , 38  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFTRACE_MODE );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_PERFTRACE_MODE_LEN    , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_PERFTRACE_MODE_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_CONFIG_0              , 40  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIG_0   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_CONFIG_0_LEN          , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIG_0_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_CONFIG_1              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIG_1   );
+REG64_FLD( XBUS_1_LL1_IOEL_PERF_TRACE_CONFIG_CONFIG_1_LEN          , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_CONFIG_1_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_TB_SEL          , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TB_SEL );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_TB_SEL_LEN      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TB_SEL_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_TAP_SEL         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TAP_SEL );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_TAP_SEL_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TAP_SEL_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_ENABLE          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_ENABLE );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_ENABLE_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_ENABLE_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED1         , 11  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED1 );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED1_LEN     , 15  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED1_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_CLEAR     , 26  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_CLEAR );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_CLEAR     , 27  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_CLEAR );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TB_CLEAR    , 28  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TB_CLEAR );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TAP_CLEAR   , 29  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TAP_CLEAR );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_DIS_TAP_STOP    , 30  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TAP_STOP );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_UNUSED2         , 31  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED2 );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT     , 32  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_COUNT );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK0_COUNT_LEN , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_COUNT_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_COUNT );
+REG64_FLD( XBUS_1_LL1_IOEL_REPLAY_THRESHOLD_THRESH_LINK1_COUNT_LEN , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_COUNT_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_SEC_CONFIG_ENABLE_ERR_INJ               , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_ENABLE_ERR_INJ );
+REG64_FLD( XBUS_1_LL1_IOEL_SEC_CONFIG_UNUSED4                      , 1   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNUSED4    );
+REG64_FLD( XBUS_1_LL1_IOEL_SEC_CONFIG_UNUSED4_LEN                  , 15  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNUSED4_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_SEC_CONFIG_SBE_ERROR_RATE               , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SBE_ERROR_RATE );
+REG64_FLD( XBUS_1_LL1_IOEL_SEC_CONFIG_SBE_ERROR_RATE_LEN           , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_SBE_ERROR_RATE_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_SEC_CONFIG_RAND_ERROR_RATE              , 18  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RAND_ERROR_RATE );
+REG64_FLD( XBUS_1_LL1_IOEL_SEC_CONFIG_RAND_ERROR_RATE_LEN          , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_RAND_ERROR_RATE_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_SEC_CONFIG_UNUSED5                      , 24  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNUSED5    );
+REG64_FLD( XBUS_1_LL1_IOEL_SEC_CONFIG_UNUSED5_LEN                  , 24  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_UNUSED5_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_SEC_CONFIG_EDPL_RATE                    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_EDPL_RATE  );
+REG64_FLD( XBUS_1_LL1_IOEL_SEC_CONFIG_EDPL_RATE_LEN                , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM_RW  ,
+           SH_FLD_EDPL_RATE_LEN );
+
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_TB_SEL          , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TB_SEL );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_TB_SEL_LEN      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TB_SEL_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_TAP_SEL         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TAP_SEL );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_TAP_SEL_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_TAP_SEL_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_ENABLE          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_ENABLE );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_ENABLE_LEN      , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_ENABLE_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED1         , 10  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED1 );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED1_LEN     , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED1_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_CLEAR     , 26  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_CLEAR );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_CLEAR     , 27  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_CLEAR );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TB_CLEAR    , 28  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TB_CLEAR );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_CLEAR   , 29  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TAP_CLEAR );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_DIS_TAP_STOP    , 30  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_DIS_TAP_STOP );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_UNUSED2         , 31  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_UNUSED2 );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT     , 32  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_COUNT );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK0_COUNT_LEN , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK0_COUNT_LEN );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_COUNT );
+REG64_FLD( XBUS_1_LL1_IOEL_SL_ECC_THRESHOLD_THRESH_LINK1_COUNT_LEN , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_THRESH_LINK1_COUNT_LEN );
+
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_TRAINED      , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TRAINED );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_TRAINED      , 1   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TRAINED );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_REPLAY_THRESHOLD , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_REPLAY_THRESHOLD );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_REPLAY_THRESHOLD , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_REPLAY_THRESHOLD );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_CRC_ERROR    , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_CRC_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_CRC_ERROR    , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_CRC_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_NAK_RECEIVED , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_NAK_RECEIVED );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_NAK_RECEIVED , 9   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_NAK_RECEIVED );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_REPLAY_BUFFER_FULL , 10  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_REPLAY_BUFFER_FULL );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_REPLAY_BUFFER_FULL , 11  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_REPLAY_BUFFER_FULL );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_SL_ECC_THRESHOLD , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_THRESHOLD );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_SL_ECC_THRESHOLD , 13  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_THRESHOLD );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_SL_ECC_CORRECTABLE , 14  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_CORRECTABLE );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_SL_ECC_CORRECTABLE , 15  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_CORRECTABLE );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_SL_ECC_UE    , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_UE );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_SL_ECC_UE    , 17  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_UE );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_TCOMPLETE_BAD , 40  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TCOMPLETE_BAD );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_TCOMPLETE_BAD , 41  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TCOMPLETE_BAD );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_SPARE_DONE   , 44  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SPARE_DONE );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_SPARE_DONE   , 45  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SPARE_DONE );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_TOO_MANY_CRC_ERRORS , 46  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TOO_MANY_CRC_ERRORS );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_TOO_MANY_CRC_ERRORS , 47  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TOO_MANY_CRC_ERRORS );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_PSAVE_INVALID_STATE , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSAVE_INVALID_STATE );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_CORRECTABLE_ARRAY_ERROR , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM2_OR , SH_FLD_LINK0_CORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_CORRECTABLE_ARRAY_ERROR , 53  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM2_OR , SH_FLD_LINK1_CORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM2_OR , SH_FLD_LINK0_UNCORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR , 55  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM2_OR , SH_FLD_LINK1_UNCORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_TRAINING_FAILED , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TRAINING_FAILED );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_TRAINING_FAILED , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TRAINING_FAILED );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_UNRECOVERABLE_ERROR , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_UNRECOVERABLE_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_UNRECOVERABLE_ERROR , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_UNRECOVERABLE_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK0_INTERNAL_ERROR , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_INTERNAL_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_LINK1_INTERNAL_ERROR , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_INTERNAL_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_SCOM_ERR_DUP       , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_MASK_REG_SCOM_ERR           , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_TRAINED           , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TRAINED );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_TRAINED           , 1   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TRAINED );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_REPLAY_THRESHOLD  , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_REPLAY_THRESHOLD );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_REPLAY_THRESHOLD  , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_REPLAY_THRESHOLD );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_CRC_ERROR         , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_CRC_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_CRC_ERROR         , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_CRC_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_NAK_RECEIVED      , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_NAK_RECEIVED );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_NAK_RECEIVED      , 9   , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_NAK_RECEIVED );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_REPLAY_BUFFER_FULL , 10  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_REPLAY_BUFFER_FULL );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_REPLAY_BUFFER_FULL , 11  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_REPLAY_BUFFER_FULL );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_SL_ECC_THRESHOLD  , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_THRESHOLD );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_SL_ECC_THRESHOLD  , 13  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_THRESHOLD );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_SL_ECC_CORRECTABLE , 14  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_CORRECTABLE );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_SL_ECC_CORRECTABLE , 15  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_CORRECTABLE );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_SL_ECC_UE         , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SL_ECC_UE );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_SL_ECC_UE         , 17  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SL_ECC_UE );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_TCOMPLETE_BAD     , 40  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TCOMPLETE_BAD );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_TCOMPLETE_BAD     , 41  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TCOMPLETE_BAD );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_SPARE_DONE        , 44  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_SPARE_DONE );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_SPARE_DONE        , 45  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_SPARE_DONE );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_TOO_MANY_CRC_ERRORS , 46  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TOO_MANY_CRC_ERRORS );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_TOO_MANY_CRC_ERRORS , 47  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TOO_MANY_CRC_ERRORS );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_PSAVE_INVALID_STATE     , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_PSAVE_INVALID_STATE );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_CORRECTABLE_ARRAY_ERROR , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_CORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_CORRECTABLE_ARRAY_ERROR , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_CORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_UNCORRECTABLE_ARRAY_ERROR , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_UNCORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_UNCORRECTABLE_ARRAY_ERROR , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_UNCORRECTABLE_ARRAY_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_TRAINING_FAILED   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_TRAINING_FAILED );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_TRAINING_FAILED   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_TRAINING_FAILED );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_UNRECOVERABLE_ERROR , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_UNRECOVERABLE_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_UNRECOVERABLE_ERROR , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_UNRECOVERABLE_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK0_INTERNAL_ERROR    , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK0_INTERNAL_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_LINK1_INTERNAL_ERROR    , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_LINK1_INTERNAL_ERROR );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_SCOM_ERR_DUP            , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR_DUP );
+REG64_FLD( XBUS_1_LL1_LL1_LL1_IOEL_FIR_REG_SCOM_ERR                , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM2_OR ,
+           SH_FLD_SCOM_ERR   );
+
+REG64_FLD( XBUS_IOPPE_MIB_XIICAC_ICACHE_TAG_ADDR                   , 0   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR );
+REG64_FLD( XBUS_IOPPE_MIB_XIICAC_ICACHE_TAG_ADDR_LEN               , 27  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_TAG_ADDR_LEN );
+REG64_FLD( XBUS_IOPPE_MIB_XIICAC_ICACHE_ERR                        , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_ERR );
+REG64_FLD( XBUS_IOPPE_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING          , 35  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IFETCH_PENDING );
+REG64_FLD( XBUS_IOPPE_MIB_XIICAC_ICACHE_VALID                      , 36  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID );
+REG64_FLD( XBUS_IOPPE_MIB_XIICAC_ICACHE_VALID_LEN                  , 4   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_ICACHE_VALID_LEN );
+
+REG64_FLD( XBUS_IOPPE_MIB_XIMEM_MEM_ADDR                           , 0   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR   );
+REG64_FLD( XBUS_IOPPE_MIB_XIMEM_MEM_ADDR_LEN                       , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ADDR_LEN );
+REG64_FLD( XBUS_IOPPE_MIB_XIMEM_MEM_R_NW                           , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_R_NW   );
+REG64_FLD( XBUS_IOPPE_MIB_XIMEM_MEM_BUSY                           , 33  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BUSY   );
+REG64_FLD( XBUS_IOPPE_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING        , 34  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( XBUS_IOPPE_MIB_XIMEM_MEM_BYTE_ENABLE                    , 35  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE );
+REG64_FLD( XBUS_IOPPE_MIB_XIMEM_MEM_BYTE_ENABLE_LEN                , 8   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_BYTE_ENABLE_LEN );
+REG64_FLD( XBUS_IOPPE_MIB_XIMEM_MEM_LINE_MODE                      , 43  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_LINE_MODE );
+REG64_FLD( XBUS_IOPPE_MIB_XIMEM_MEM_ERROR                          , 49  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR  );
+REG64_FLD( XBUS_IOPPE_MIB_XIMEM_MEM_ERROR_LEN                      , 3   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_ERROR_LEN );
+REG64_FLD( XBUS_IOPPE_MIB_XIMEM_MEM_IFETCH_PENDING                 , 62  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_IFETCH_PENDING );
+REG64_FLD( XBUS_IOPPE_MIB_XIMEM_MEM_DATAOP_PENDING                 , 63  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_MEM_DATAOP_PENDING );
+
+REG64_FLD( XBUS_IOPPE_MIB_XISGB_STORE_ADDRESS                      , 0   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS );
+REG64_FLD( XBUS_IOPPE_MIB_XISGB_STORE_ADDRESS_LEN                  , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_STORE_ADDRESS_LEN );
+REG64_FLD( XBUS_IOPPE_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING  , 35  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING );
+REG64_FLD( XBUS_IOPPE_MIB_XISGB_SGB_BYTE_VALID                     , 36  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID );
+REG64_FLD( XBUS_IOPPE_MIB_XISGB_SGB_BYTE_VALID_LEN                 , 4   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_BYTE_VALID_LEN );
+REG64_FLD( XBUS_IOPPE_MIB_XISGB_SGB_FLUSH_PENDING                  , 63  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_RO  ,
+           SH_FLD_SGB_FLUSH_PENDING );
+
+REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_NULL_MSR_SIBRC                  , 9   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN              , 3   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_NULL_MSR_WE                     , 14  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( XBUS_IOPPE_PPE_XIDBGPRO_NULL_MSR_LP                     , 20  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_NULL_MSR_SIBRC                  , 9   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC );
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN              , 3   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_SIBRC_LEN );
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_NULL_MSR_WE                     , 14  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_WE );
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_NULL_MSR_LP                     , 20  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_NULL_MSR_LP );
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XIRAMRA_SPRG0                   , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN               , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMEDR_XIRAMGA_IR                      , 0   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR );
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMEDR_XIRAMGA_IR_LEN                  , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_XIRAMGA_IR_LEN );
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMEDR_EDR                             , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_EDR        );
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMEDR_EDR_LEN                         , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_EDR_LEN    );
+
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMGA_IR                               , 0   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WO  ,
+           SH_FLD_IR         );
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMGA_IR_LEN                           , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WO  ,
+           SH_FLD_IR_LEN     );
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMGA_XIRAMRA_SPRG0                    , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0 );
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN                , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WO  ,
+           SH_FLD_XIRAMRA_SPRG0_LEN );
+
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMRA_XIXCR_XCR                        , 1   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR  );
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMRA_XIXCR_XCR_LEN                    , 3   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WO  ,
+           SH_FLD_XIXCR_XCR_LEN );
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMRA_SPRG0                            , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0      );
+REG64_FLD( XBUS_IOPPE_PPE_XIRAMRA_SPRG0_LEN                        , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WO  ,
+           SH_FLD_SPRG0_LEN  );
+
+REG64_FLD( XBUS_IOPPE_PPE_XIXCR_XCR                                , 1   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR        );
+REG64_FLD( XBUS_IOPPE_PPE_XIXCR_XCR_LEN                            , 3   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM_WO  ,
+           SH_FLD_XCR_LEN    );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME      , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PRBS_TEST_TIME );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME_LEN  , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PRBS_TEST_TIME_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL10_EO_PG_BIST_BUS_DATA_MODE       , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_BUS_DATA_MODE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME      , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PRBS_PROP_TIME );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME_LEN  , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PRBS_PROP_TIME_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PLL_LOCK_TIMEOUT    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PLL_LOCK_TIMEOUT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL10_EO_PG_BIST_PLL_LOCK_TIMEOUT_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PLL_LOCK_TIMEOUT_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_LLMT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT_LEN         , 9   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_LLMT_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_RESET            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_RESET );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL11_EO_PG_DACTEST_START            , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_START );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_HLMT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT_LEN         , 9   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_HLMT_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_VALID , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_VALID );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_LANE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_LANE_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH       , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LEN   , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_VALID , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_VALID );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_LANE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_LANE_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT      , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LEN  , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL15_EO_PG_WTL_TEST_CLOCK           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WTL_TEST_CLOCK );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL15_EO_PG_WTL_TEST_DATA            , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WTL_TEST_DATA );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL15_EO_PG_WT_BS_CLOCK_EN_BYP       , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_BS_CLOCK_EN_BYP );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL15_EO_PG_WT_BS_DATA_EN_BYP        , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_BS_DATA_EN_BYP );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL1_EO_PG_BER_EN                    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_EN     );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_FREEZE_EN       , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_TIMER_FREEZE_EN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_FREEZE_EN       , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_COUNT_FREEZE_EN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL             , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_COUNT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_COUNT_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL             , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_TIMER_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL_LEN         , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_TIMER_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL1_EO_PG_BER_CLR_COUNT_ON_READ_EN  , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CLR_COUNT_ON_READ_EN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL1_EO_PG_BER_CLR_TIMER_ON_READ_EN  , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CLR_TIMER_ON_READ_EN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL1_E_PG_START_WIRETEST             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_WIRETEST );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL1_E_PG_START_DESKEW               , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_DESKEW );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL1_E_PG_START_EYE_OPT              , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_EYE_OPT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL1_E_PG_START_REPAIR               , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_REPAIR );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL1_E_PG_START_FUNC_MODE            , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_FUNC_MODE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL1_E_PG_START_DC_CALIBRATE         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_DC_CALIBRATE );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL2_EO_PG_TRC_MODE                  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRC_MODE   );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL2_EO_PG_TRC_MODE_LEN              , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRC_MODE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL3_EO_PG_INT_MODE                  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_MODE   );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL3_EO_PG_INT_MODE_LEN              , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_CURRENT_STATE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE_LEN     , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_CURRENT_STATE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_ENABLE_ENC );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC_LEN        , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_ENABLE_ENC_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE            , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_NEXT_STATE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE_LEN        , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_NEXT_STATE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL4_E_PG_WT_CU_PLL_PGOOD            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_CU_PLL_PGOOD );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL4_E_PG_WT_CU_BYP_PLL_LOCK         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_CU_BYP_PLL_LOCK );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL4_E_PG_WT_PLL_REFCLKSEL           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_PLL_REFCLKSEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL4_E_PG_PLL_REFCLKSEL_SCOM_EN      , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PLL_REFCLKSEL_SCOM_EN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL4_E_PG_IORESET                    , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE            , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_GOTO_STATE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE_LEN        , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_GOTO_STATE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_RETURN_STATE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE_LEN      , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_RETURN_STATE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL8_EO_PG_SERVO_OP                  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_OP   );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL8_EO_PG_SERVO_OP_LEN              , 15  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_OP_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL8_EO_PG_SERVO_DONE                , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_DONE );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL9_EO_PG_BIST_EN                   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EN    );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL9_EO_PG_BIST_EXT_START_MODE       , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EXT_START_MODE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_INIT_DISABLE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE_LEN     , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_INIT_DISABLE_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL9_EO_PG_BIST_CUPLL_LOCK_CHECK_EN  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_CUPLL_LOCK_CHECK_EN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_STORE_EYES_LANE_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_STORE_EYES_LANE_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL  , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_STORE_EYES_BANK_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_STORE_EYES_BANK_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTL9_EO_PG_PERVASIVE_CAPT            , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PERVASIVE_CAPT );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_SHDW_DONE_FIN_GCRMSG , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_SHDW_DONE_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_SHDW_NOP_FIN_GCRMSG  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_SHDW_NOP_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_SHDW_RPR_DONE_FIN_GCRMSG , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_SHDW_RPR_DONE_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_SHDW_RPR_NOP_FIN_GCRMSG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_SHDW_RPR_NOP_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_DONE_FIN_GCRMSG , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_UNSHDW_DONE_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_NOP_FIN_GCRMSG , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_UNSHDW_NOP_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_RPR_DONE_FIN_GCRMSG , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_UNSHDW_RPR_DONE_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_RPR_NOP_FIN_GCRMSG , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_UNSHDW_RPR_NOP_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_RECAL_DONE_NOP_FIN_GCRMSG , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_RECAL_DONE_NOP_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_RECAL_FAIL_NOP_FIN_GCRMSG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_RECAL_FAIL_NOP_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_RECAL_FRESULTS_FIN_GCRMSG , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_RECAL_FRESULTS_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_RECAL_ABORT_ACK_FIN_GCRMSG , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_RECAL_ABORT_ACK_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_RECAL_ABORT_MNOP_FIN_GCRMSG , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_RECAL_ABORT_MNOP_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX10_E_PG_SLV_RECAL_ABORT_SNOP_FIN_GCRMSG , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_RECAL_ABORT_SNOP_FIN_GCRMSG );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_SEQ_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG_LEN    , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_SEQ_GCRMSG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SKMIN_GCRMSG      , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_SKMIN_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SKMIN_GCRMSG_LEN  , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_SKMIN_GCRMSG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG      , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_SKMAX_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG_LEN  , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_SKMAX_GCRMSG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX5_E_PG_DYN_RPR_REQ_GCRMSG        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_REQ_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX5_E_PG_DYN_RPR_LANE2RPR_GCRMSG   , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_LANE2RPR_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX5_E_PG_DYN_RPR_LANE2RPR_GCRMSG_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_LANE2RPR_GCRMSG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX5_E_PG_DYN_RPR_IP_GCRMSG         , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_IP_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX5_E_PG_DYN_RPR_COMPLETE_GCRMSG   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_COMPLETE_GCRMSG );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG_LEN      , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_GCRMSG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_VAL_GCRMSG      , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_VAL_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG      , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_PHY_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG_LEN  , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_PHY_GCRMSG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_INIT_CFG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG_LEN         , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_INIT_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG            , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_RECAL_CFG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG_LEN        , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_RECAL_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG            , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_INIT_CFG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG_LEN        , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_INIT_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG           , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_RECAL_CFG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG_LEN       , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_RECAL_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE10_EO_PG_AMP_CFG                  , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_CFG    );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE10_EO_PG_AMP_CFG_LEN              , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE10_E_PG_DESKEW_MAX_LIMIT          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_MAX_LIMIT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE10_E_PG_DESKEW_MAX_LIMIT_LEN      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_MAX_LIMIT_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_INIT_CFG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG_LEN         , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_INIT_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG            , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_RECAL_CFG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG_LEN        , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_RECAL_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE11_EO_PG_CM_CFG                   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CFG     );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE11_EO_PG_CM_CFG_LEN               , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE11_EO_PG_AMIN_CFG                 , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMIN_CFG   );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE11_EO_PG_AMIN_CFG_LEN             , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMIN_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE11_EO_PG_USERDEF_CFG              , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USERDEF_CFG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE11_EO_PG_USERDEF_CFG_LEN          , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USERDEF_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE11_E_PG_LANE_DISABLED_VEC_0_15    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_0_15 );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE11_E_PG_LANE_DISABLED_VEC_0_15_LEN , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_CHG_CFG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG_LEN        , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_CHG_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE12_EO_PG_DAC_BO_CFG               , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DAC_BO_CFG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE12_EO_PG_DAC_BO_CFG_LEN           , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DAC_BO_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE12_EO_PG_FILTER_MODE              , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FILTER_MODE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE12_EO_PG_FILTER_MODE_LEN          , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FILTER_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE12_EO_PG_MISC_CFG                 , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CFG   );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE12_EO_PG_MISC_CFG_LEN             , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE12_EO_PG_DISABLE_H1_CLEAR         , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_H1_CLEAR );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE12_EO_PG_VOFF_CFG                 , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_VOFF_CFG   );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE12_EO_PG_VOFF_CFG_LEN             , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_VOFF_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE12_EO_PG_LOFF_AMP_EN              , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LOFF_AMP_EN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE12_E_PG_LANE_DISABLED_VEC_16_23   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_16_23 );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE12_E_PG_LANE_DISABLED_VEC_16_23_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_16_23_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL            , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_OFFSET_VAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL_LEN        , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_OFFSET_VAL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH1            , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH1 );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH1_LEN        , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH1_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH2            , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH2 );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE13_EO_PG_SERVO_THRESH2_LEN        , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH2_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_INIT_TIMEOUT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_INIT_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT        , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_RECAL_TIMEOUT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT_LEN    , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_RECAL_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT        , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_INIT_TIMEOUT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT_LEN    , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_INIT_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT       , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_RECAL_TIMEOUT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT_LEN   , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_RECAL_TIMEOUT_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_INIT_TIMEOUT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_INIT_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT        , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_RECAL_TIMEOUT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT_LEN    , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_RECAL_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE15_EO_PG_CM_TIMEOUT               , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_TIMEOUT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE15_EO_PG_CM_TIMEOUT_LEN           , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT             , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMIN_TIMEOUT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMIN_TIMEOUT_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_TIMEOUT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT_LEN          , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USERDEF_TIMEOUT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT_LEN      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USERDEF_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE16_EO_PG_BER_TIMEOUT              , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_TIMEOUT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE16_EO_PG_BER_TIMEOUT_LEN          , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT           , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE4_TIMEOUT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT_LEN       , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE4_TIMEOUT_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE17_EO_PG_AMAX_HIGH                , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMAX_HIGH  );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE17_EO_PG_AMAX_HIGH_LEN            , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMAX_HIGH_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE17_EO_PG_AMAX_LOW                 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMAX_LOW   );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE17_EO_PG_AMAX_LOW_LEN             , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMAX_LOW_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP0_FILTER_MASK );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK_LEN     , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP0_FILTER_MASK_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK         , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP1_FILTER_MASK );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK_LEN     , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP1_FILTER_MASK_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTLE_GAIN_MAX );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX_LEN        , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTLE_GAIN_MAX_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE19_EO_PG_AMP_START_VAL            , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_START_VAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE19_EO_PG_AMP_START_VAL_LEN        , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_START_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_EO_PG_CLKDIST_PDWN              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLKDIST_PDWN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH        , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_MIN_EYE_WIDTH );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH_LEN    , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_MIN_EYE_WIDTH_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_EO_PG_A_BIST_EN                 , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BIST_EN  );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_MASTER_MODE                , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_MODE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_DISABLE_FENCE_RESET        , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_FENCE_RESET );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_ACT_CHECK_TIMEOUT_SEL      , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACT_CHECK_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_ACT_CHECK_TIMEOUT_SEL_LEN  , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACT_CHECK_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_BIST_JITTER_PULSE_SEL      , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_JITTER_PULSE_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_BIST_JITTER_PULSE_SEL_LEN  , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_JITTER_PULSE_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_FENCE                      , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FENCE      );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_PDWN_LITE_DISABLE          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_DISABLE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_USE_SLS_AS_SPR             , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USE_SLS_AS_SPR );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_DYN_RECAL_SUSPEND          , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_SUSPEND );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_WT_PATTERN_LENGTH          , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_PATTERN_LENGTH );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE1_E_PG_WT_PATTERN_LENGTH_LEN      , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_PATTERN_LENGTH_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_CONVERGED_CNT_MAX );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_CONVERGED_CNT_MAX_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX    , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AP110_AP010_DELTA_MAX );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AP110_AP010_DELTA_MAX_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_INTEG_LATCH_OFFSET_CAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_INTEG_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_COARSE_CAL   , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CTLE_COARSE_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DAC_H1_CAL        , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DAC_H1_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_VGA_CAL           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_VGA_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DFE_H1_CAL        , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DFE_H1_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_H1AP_TWEAK        , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_H1AP_TWEAK );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DDC               , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DDC );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CM_COARSE_CAL     , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CM_COARSE_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CM_FINE_CAL       , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CM_FINE_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_BER_TEST          , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_BER_TEST );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_RESULT_CHECK      , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_RESULT_CHECK );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_EDGE_TRACK_ONLY , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CTLE_EDGE_TRACK_ONLY );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DFE_H2_H12_CAL    , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DFE_H2_H12_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DAC_H1_TO_A_CAL   , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DAC_H1_TO_A_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_FINAL_L2U_ADJ     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_FINAL_L2U_ADJ );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE21_EO_PG_ENABLE_DONE_SIGNALING    , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DONE_SIGNALING );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_INTEG_LATCH_OFFSET_CAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_INTEG_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_COARSE_CAL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_CTLE_COARSE_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DAC_H1_CAL     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DAC_H1_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_VGA_CAL        , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_VGA_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DFE_H1_CAL     , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DFE_H1_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_H1AP_TWEAK     , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_H1AP_TWEAK );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DDC            , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DDC );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_COARSE_CAL  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_CM_COARSE_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_FINE_CAL    , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_CM_FINE_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_BER_TEST       , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_BER_TEST );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_RESULT_CHECK   , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_RESULT_CHECK );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_EDGE_TRACK_ONLY , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_CTLE_EDGE_TRACK_ONLY );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DFE_H2_H12_CAL , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DFE_H2_H12_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE22_EO_PG_RC_ENABLE_DAC_H1_TO_A_CAL , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DAC_H1_TO_A_CAL );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE23_EO_PG_QUAD_SEL                 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_QUAD_SEL   );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE23_EO_PG_QUAD_SEL_LEN             , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_QUAD_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE23_EO_PG_PEAK_TUNE                , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_TUNE  );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE23_EO_PG_LTE_EN                   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LTE_EN     );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE23_EO_PG_IQSPD_CFG                , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IQSPD_CFG  );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE23_EO_PG_IQSPD_CFG_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IQSPD_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE23_EO_PG_DFEHISPD_EN              , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFEHISPD_EN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE23_EO_PG_DFE12_EN                 , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE12_EN   );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE24_EO_PG_H1AP_CFG                 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_H1AP_CFG   );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE24_EO_PG_H1AP_CFG_LEN             , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_H1AP_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE24_EO_PG_CTLE_UPDATE_MODE         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTLE_UPDATE_MODE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK         , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USER_FILTER_MASK );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK_LEN     , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USER_FILTER_MASK_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_VGA_AMAX_MODE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_VGA_AMAX_MODE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H2_H12_SUBSTEP , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H2_H12_SUBSTEP_LEN , 11  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_DFE_VOLTAGE_MODE  , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DFE_VOLTAGE_MODE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H6_H12_FAST_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DFE_H6_H12_FAST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL , 49  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_VGA_AMAX_MODE  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_VGA_AMAX_MODE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H2_H12_SUBSTEP , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H2_H12_SUBSTEP_LEN , 11  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_VOLTAGE_MODE , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DFE_VOLTAGE_MODE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H6_H12_FAST_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DFE_H6_H12_FAST_MODE );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_COARSE_CAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DC_ENABLE_CM_COARSE_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_FINE_CAL    , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DC_ENABLE_CM_FINE_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL , 50  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL , 51  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_INTEG_LATCH_OFFSET_CAL , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DC_ENABLE_INTEG_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_DAC_H1_CAL     , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DC_ENABLE_DAC_H1_CAL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE28_EO_PG_DC_ENABLE_DAC_H1_TO_A_CAL , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DC_ENABLE_DAC_H1_TO_A_CAL );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE29_EO_PG_APX111_HIGH              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_APX111_HIGH );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE29_EO_PG_APX111_HIGH_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_APX111_HIGH_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE29_EO_PG_APX111_LOW               , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_APX111_LOW );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE29_EO_PG_APX111_LOW_LEN           , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_APX111_LOW_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE2_EO_PG_DFE_CA_CFG                , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_CA_CFG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE2_EO_PG_DFE_CA_CFG_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_CA_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL             , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_CONTROL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_CONTROL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE2_EO_PG_DATA_PIPE_CLR_ON_READ_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DATA_PIPE_CLR_ON_READ_MODE );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE2_E_PG_WTR_MAX_BAD_LANES          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WTR_MAX_BAD_LANES );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE2_E_PG_WTR_MAX_BAD_LANES_LEN      , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WTR_MAX_BAD_LANES_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE2_E_PG_SLS_EXTEND_SEL             , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_EXTEND_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE2_E_PG_SLS_EXTEND_SEL_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_EXTEND_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE2_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE2_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_EO_PG_SERVO_THRESH3             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH3 );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_EO_PG_SERVO_THRESH3_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH3_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_EO_PG_DFE_HTAP_CFG              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_HTAP_CFG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_EO_PG_DFE_HTAP_CFG_LEN          , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_HTAP_CFG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_EO_PG_DFE_INIT_TIMEOUT          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_INIT_TIMEOUT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_EO_PG_DFE_INIT_TIMEOUT_LEN      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_INIT_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_EO_PG_DFE_RECAL_TIMEOUT         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_RECAL_TIMEOUT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_EO_PG_DFE_RECAL_TIMEOUT_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_RECAL_TIMEOUT_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_E_PG_SLS_TIMEOUT_SEL            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_E_PG_SLS_TIMEOUT_SEL_LEN        , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_E_PG_CL_TIMEOUT_SEL             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CL_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_E_PG_CL_TIMEOUT_SEL_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CL_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_E_PG_DS_SKEW_TIMEOUT_SEL        , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DS_SKEW_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_E_PG_DS_SKEW_TIMEOUT_SEL_LEN    , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DS_SKEW_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_E_PG_DS_TIMEOUT_SEL             , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DS_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE3_E_PG_DS_TIMEOUT_SEL_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DS_TIMEOUT_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE4_EO_PG_DISABLE_2TO12_CLEAR       , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_2TO12_CLEAR );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE4_EO_PG_PEAK_ENABLE_DAC_CFG       , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_ENABLE_DAC_CFG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE4_EO_PG_AMIN_ENABLE_HDAC          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMIN_ENABLE_HDAC );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE4_EO_PG_USE_PREV_COARSE_VAL       , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USE_PREV_COARSE_VAL );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE4_E_PG_WT_CHECK_COUNT             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_CHECK_COUNT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE4_E_PG_WT_CHECK_COUNT_LEN         , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_CHECK_COUNT_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE4_E_PG_PGOOD_TIMEOUT_SEL          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PGOOD_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE4_E_PG_PGOOD_TIMEOUT_SEL_LEN      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PGOOD_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE4_E_PG_PLL_LOCK_TIMEOUT_SEL       , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PLL_LOCK_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE4_E_PG_PLL_LOCK_TIMEOUT_SEL_LEN   , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PLL_LOCK_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE4_E_PG_PSAVE_TIMER_WAKEUP_MODE    , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_TIMER_WAKEUP_MODE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE4_E_PG_PSAVE_WAKEUP_LANE0_ENABLE  , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_WAKEUP_LANE0_ENABLE );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE5_EO_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE5_EO_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE5_EO_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE5_EO_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL      , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRACKING_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL_LEN  , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRACKING_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE5_EO_PG_PUP_LITE_WAIT_SEL         , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PUP_LITE_WAIT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE5_EO_PG_PUP_LITE_WAIT_SEL_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PUP_LITE_WAIT_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE5_E_PG_FIFO_INITIAL_L2U_DLY       , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_INITIAL_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE5_E_PG_FIFO_INITIAL_L2U_DLY_LEN   , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_INITIAL_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE5_E_PG_FIFO_FINAL_L2U_DLY         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_FINAL_L2U_DLY );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE5_E_PG_FIFO_FINAL_L2U_DLY_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_FINAL_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE5_E_PG_WT_TIMEOUT_SEL             , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE5_E_PG_WT_TIMEOUT_SEL_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_TIMEOUT_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT       , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CONVERGED_END_COUNT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT_LEN   , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CONVERGED_END_COUNT_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE   , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_MODE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX          , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_GAIN_CNT_MAX );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX_LEN      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_GAIN_CNT_MAX_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE6_E_PG_TX_BUS_WIDTH               , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TX_BUS_WIDTH );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE6_E_PG_TX_BUS_WIDTH_LEN           , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TX_BUS_WIDTH_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE6_E_PG_RX_BUS_WIDTH               , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RX_BUS_WIDTH );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE6_E_PG_RX_BUS_WIDTH_LEN           , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RX_BUS_WIDTH_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_CHECK_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_CHECK_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL       , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_POLLING_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL_LEN   , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_POLLING_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_EO_PG_PSAVE_MODE_TIMEOUT_SEL    , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_EO_PG_PSAVE_MODE_TIMEOUT_SEL_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_EO_PG_DYN_RECAL_OVERALL_TIMEOUT_SEL , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_EO_PG_DYN_RECAL_OVERALL_TIMEOUT_SEL_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_SLS_DISABLE                , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_DISABLE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_TX_SLS_DISABLE             , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TX_SLS_DISABLE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_SLS_CNTR_TAP_PTS           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_CNTR_TAP_PTS );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_SLS_CNTR_TAP_PTS_LEN       , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_CNTR_TAP_PTS_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS        , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NONSLS_CNTR_TAP_PTS );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS_LEN    , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NONSLS_CNTR_TAP_PTS_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_SR_FINAL_NOP_TIMEOUT_SEL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_SR_FINAL_NOP_TIMEOUT_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_SLS_EXCEPTION2_CS          , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_EXCEPTION2_CS );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_DYN_RPR_ERR_CNTR1_FILTER_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ERR_CNTR1_FILTER_MODE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE7_E_PG_DYN_RPR_ERR_CNTR1_FILTER_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ERR_CNTR1_FILTER_MODE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE8_EO_PG_MAX_BER_CHECK_COUNT       , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MAX_BER_CHECK_COUNT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE8_EO_PG_MAX_BER_CHECK_COUNT_LEN   , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MAX_BER_CHECK_COUNT_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_BAD_LANE_MAX       , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_BAD_LANE_MAX );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_BAD_LANE_MAX_LEN   , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_BAD_LANE_MAX_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_ERR_CNTR1_DURATION , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ERR_CNTR1_DURATION );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_ERR_CNTR1_DURATION_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ERR_CNTR1_DURATION_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_CLR_ERR_CNTR1      , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_CLR_ERR_CNTR1 );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_DISABLE            , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_DISABLE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE8_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH             , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MIN_EYE_WIDTH );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH_LEN         , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MIN_EYE_WIDTH_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT            , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MIN_EYE_HEIGHT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT_LEN        , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MIN_EYE_HEIGHT_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_BAD_BUS_MAX        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_BAD_BUS_MAX );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_BAD_BUS_MAX_LEN    , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_BAD_BUS_MAX_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_ERR_CNTR2_DURATION , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ERR_CNTR2_DURATION );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_ERR_CNTR2_DURATION_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ERR_CNTR2_DURATION_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_CLR_ERR_CNTR2      , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_CLR_ERR_CNTR2 );
+REG64_FLD( XBUS_1_RX0_RX_CTL_MODE9_E_PG_DYN_RPR_DISABLE2           , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_DISABLE2 );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT1_EO_PG_SERVO_RESULT              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_RESULT );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT1_EO_PG_SERVO_RESULT_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_RESULT_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT1_E_PG_WIRETEST_DONE              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WIRETEST_DONE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT1_E_PG_DESKEW_DONE                , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_DONE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT1_E_PG_EYE_OPT_DONE               , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_EYE_OPT_DONE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT1_E_PG_REPAIR_DONE                , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPAIR_DONE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT1_E_PG_FUNC_MODE_DONE             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FUNC_MODE_DONE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT1_E_PG_DC_CALIBRATE_DONE          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DC_CALIBRATE_DONE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT1_E_PG_WIRETEST_FAILED            , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WIRETEST_FAILED );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT1_E_PG_DESKEW_FAILED              , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_FAILED );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT1_E_PG_EYE_OPT_FAILED             , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_EYE_OPT_FAILED );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT1_E_PG_REPAIR_FAILED              , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPAIR_FAILED );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT2_EO_PG_BIST_INIT_DONE            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_INIT_DONE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT2_EO_PG_BIST_DONE                 , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_DONE  );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT2_EO_PG_BIST_CU_PLL_ERR           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_CU_PLL_ERR );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT2_EO_PG_BIST_NO_EDGE_DET          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_NO_EDGE_DET );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EYE_A_WIDTH );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH_LEN      , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EYE_A_WIDTH_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EYE_B_WIDTH );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH_LEN      , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EYE_B_WIDTH_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT2_E_PG_LANE_BAD_VEC_0_15          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BAD_VEC_0_15 );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT2_E_PG_LANE_BAD_VEC_0_15_LEN      , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BAD_VEC_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT3_EO_PG_WTL_SM_STATUS             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WTL_SM_STATUS );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT3_EO_PG_WTL_SM_STATUS_LEN         , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WTL_SM_STATUS_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT4_E_PG_LANE_BAD_VEC_16_23         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BAD_VEC_16_23 );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT4_E_PG_LANE_BAD_VEC_16_23_LEN     , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BAD_VEC_16_23_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT5_E_PG_WT_CLK_LANE_INVERTED       , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_CLK_LANE_INVERTED );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT5_E_PG_WT_CLK_LANE_BAD_CODE       , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_CLK_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT5_E_PG_WT_CLK_LANE_BAD_CODE_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_CLK_LANE_BAD_CODE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT6_E_PG_DESKEW_MINSKEW_GRP         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_MINSKEW_GRP );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT6_E_PG_DESKEW_MINSKEW_GRP_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_MINSKEW_GRP_LEN );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT6_E_PG_DESKEW_MAXSKEW_GRP         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_MAXSKEW_GRP );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STAT6_E_PG_DESKEW_MAXSKEW_GRP_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_MAXSKEW_GRP_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_CTL_STATX8_E_PG_WT_PREV_DONE_GCRMSG       , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_PREV_DONE_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STATX8_E_PG_WT_ALL_DONE_GCRMSG        , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_ALL_DONE_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STATX8_E_PG_CD_PREV_DONE_GCRMSG       , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CD_PREV_DONE_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STATX8_E_PG_CD_ALL_DONE_GCRMSG        , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CD_ALL_DONE_GCRMSG );
+REG64_FLD( XBUS_1_RX0_RX_CTL_STATX8_E_PG_CNTLS_PREV_LDED_GCRMSG    , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CNTLS_PREV_LDED_GCRMSG );
+
+REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SCRAMBLE_MODE      , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SCRAMBLE_MODE_LEN  , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SEED_MODE          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_MODE );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTL1_E_PG_DESKEW_RATE             , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_RATE );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTL1_E_PG_RUN_DYN_RECAL_TIMER     , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DYN_RECAL_TIMER );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTL1_E_PG_DESKEW_PATTCHK_TIMEOUT_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_PATTCHK_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTL1_E_PG_DESKEW_PATTCHK_TIMEOUT_SEL_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_PATTCHK_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SLS_EXPECT );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT_LEN     , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SLS_EXPECT_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_DATASM_SPARE_MODE_PG_0                    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_SPARE_MODE_PG_1                    , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_SPARE_MODE_PG_2                    , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_SPARE_MODE_PG_3                    , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_SPARE_MODE_PG_4                    , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_SPARE_MODE_PG_5                    , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_SPARE_MODE_PG_6                    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_SPARE_MODE_PG_7                    , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG         , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_CONFIG );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_CONFIG_LEN );
+REG64_FLD( XBUS_1_RX0_RX_DATASM_SPARE_MODE_PG_CTL_CLKDIST_PDWN     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_CLKDIST_PDWN );
+
+REG64_FLD( XBUS_1_RX0_RX_DATASM_STAT13_E_PG_BAD_BUS_LANE_ERR_CNTR_DIS_CLR , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BUS_LANE_ERR_CNTR_DIS_CLR );
+
+REG64_FLD( XBUS_1_RX0_RX_FIR1_ERROR_INJECT_PG_ERR_INJ              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RX_FIR1_ERROR_INJECT_PG_ERR_INJ_LEN          , 15  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_FIR1_MASK_PG_ERRS                         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RX_FIR1_MASK_PG_ERRS_LEN                     , 15  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RX_FIR2_ERROR_INJECT_PG_ERR_INJ              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX0_RX_FIR2_ERROR_INJECT_PG_ERR_INJ_LEN          , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_FIR2_MASK_PG_ERRS                         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX0_RX_FIR2_MASK_PG_ERRS_LEN                     , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_MASK_PG_ERROR                , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERROR      );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_MASK_PG_STATIC_SPARE_DEPLOYED , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATIC_SPARE_DEPLOYED );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_MASK_PG_STATIC_MAX_SPARES_EXCEEDED , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATIC_MAX_SPARES_EXCEEDED );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_MASK_PG_DYNAMIC_REPAIR_ERROR , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYNAMIC_REPAIR_ERROR );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_MASK_PG_DYNAMIC_SPARE_DEPLOYED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYNAMIC_SPARE_DEPLOYED );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_MASK_PG_DYNAMIC_MAX_SPARES_EXCEEDED , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYNAMIC_MAX_SPARES_EXCEEDED );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_MASK_PG_RECAL_ERROR          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ERROR );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_MASK_PG_RECAL_SPARE_DEPLOYED , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_SPARE_DEPLOYED );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_MASK_PG_RECAL_MAX_SPARES_EXCEEDED , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_MAX_SPARES_EXCEEDED );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_MASK_PG_TOO_MANY_BUS_ERRORS  , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TOO_MANY_BUS_ERRORS );
+
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_PG_ERROR                     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERROR      );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_PG_STATIC_SPARE_DEPLOYED     , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATIC_SPARE_DEPLOYED );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_PG_STATIC_MAX_SPARES_EXCEEDED , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATIC_MAX_SPARES_EXCEEDED );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_PG_DYNAMIC_REPAIR_ERROR      , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYNAMIC_REPAIR_ERROR );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_PG_DYNAMIC_SPARE_DEPLOYED    , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYNAMIC_SPARE_DEPLOYED );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_PG_DYNAMIC_MAX_SPARES_EXCEEDED , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYNAMIC_MAX_SPARES_EXCEEDED );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_PG_RECAL_ERROR               , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ERROR );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_PG_RECAL_SPARE_DEPLOYED      , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_SPARE_DEPLOYED );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_PG_RECAL_MAX_SPARES_EXCEEDED , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_MAX_SPARES_EXCEEDED );
+REG64_FLD( XBUS_1_RX0_RX_FIR_TRAINING_PG_TOO_MANY_BUS_ERRORS       , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TOO_MANY_BUS_ERRORS );
+
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL2_EO_PG_DYN_RPR_REQ_MANUAL      , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_REQ_MANUAL );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL2_EO_PG_CNT_SINGLE_LANE_RECAL   , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CNT_SINGLE_LANE_RECAL );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_LANE_TO_MONITOR );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_LANE_TO_MONITOR_LEN );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL2_EO_PG_DYN_RPR_SM_MANUAL       , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_SM_MANUAL );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL2_EO_PG_DIS_SYND_TALLYING       , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DIS_SYND_TALLYING );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL2_EO_PG_ENC_BUS_LANE2RPR_MANUAL , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENC_BUS_LANE2RPR_MANUAL );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL2_EO_PG_ENC_BUS_LANE2RPR_MANUAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENC_BUS_LANE2RPR_MANUAL_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_REQUEST    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MANUAL_RECAL_REQUEST );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE       , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MANUAL_RECAL_LANE );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE_LEN   , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MANUAL_RECAL_LANE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTLX1_EO_PG_CLR_PAR_ERRS           , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLR_PAR_ERRS );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_CNTLX1_EO_PG_FIR_RESET              , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIR_RESET  );
+
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_SPARE_MODE_PG_0                     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_SPARE_MODE_PG_1                     , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_SPARE_MODE_PG_2                     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_SPARE_MODE_PG_3                     , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_SPARE_MODE_PG_4                     , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_SPARE_MODE_PG_5                     , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_SPARE_MODE_PG_6                     , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_SPARE_MODE_PG_7                     , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_SPARE_MODE_PG_DESKEW_BUMP_AFTER     , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_BUMP_AFTER );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_SPARE_MODE_PG_SLS_RCVY_DISABLE      , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_RCVY_DISABLE );
+
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT10_E_PG_SERVO_RECAL_IP          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_RECAL_IP );
+
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE1                , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE1  );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE1_LEN            , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE1_LEN );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE2                , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE2  );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE2_LEN            , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE2_LEN );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE_CODE            , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE_CODE );
+REG64_FLD( XBUS_1_RX0_RX_GLBSM_STAT9_E_PG_BAD_LANE_CODE_LEN        , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE_CODE_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_ID1_PG_BUS_ID                             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ID     );
+REG64_FLD( XBUS_1_RX0_RX_ID1_PG_BUS_ID_LEN                         , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ID_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_ID2_PG_START_LANE_ID                      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_LANE_ID );
+REG64_FLD( XBUS_1_RX0_RX_ID2_PG_START_LANE_ID_LEN                  , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_LANE_ID_LEN );
+REG64_FLD( XBUS_1_RX0_RX_ID2_PG_END_LANE_ID                        , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_END_LANE_ID );
+REG64_FLD( XBUS_1_RX0_RX_ID2_PG_END_LANE_ID_LEN                    , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_END_LANE_ID_LEN );
+
+REG64_FLD( XBUS_1_RX0_RX_SPARE_MODE_PG_0                           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_RX_SPARE_MODE_PG_1                           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_RX_SPARE_MODE_PG_2                           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_RX_SPARE_MODE_PG_3                           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_RX_SPARE_MODE_PG_4                           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX0_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE0_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE1_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE2_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS0_SLICE3_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE0_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE1_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE2_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS1_SLICE3_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE0_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE1_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE2_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS2_SLICE3_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE0_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE1_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE2_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE3_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE4_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_EDGE_TRACK_CNTL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_EDGE_TRACK_CNTL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_EDGE_TRACK_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_WOBBLE_A , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_WOBBLE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_DDC_A  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DDC_A   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_EDGE_A , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_EDGE_A );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_TO_CENTER , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_TO_CENTER );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_SL_1UI , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SL_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_BUMP_SR_1UI , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_BUMP_SR_1UI );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_EO_PL_PR_USE_DFE_CLOCK_A , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_USE_DFE_CLOCK_A );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL2_E_PL_FIFO_L2U_DLY_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_DATA_A_OFFSET );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_DATA_A_OFFSET_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_DATA_A_OFFSET_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_LOCK_DONE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_LOCK_DONE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_FILTER_EN , 61  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_FILTER_EN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL3_EO_PL_PR_INVALID_LOCK_BUMP_SIZE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_STOP , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_DDC_SM_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_DDC_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_STOP , 54  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_TRACE_WOBBLE_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_PR_TRACE_WOBBLE_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PR_TRACE_WOBBLE_SM_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_STOP , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM , 59  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTL4_EO_PL_DDC_DFE_OFFSET_SWITCH_SM_LEN , 3   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_CAL_LANE_SEL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_LANE_INVERT , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_LANE_INVALID , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVALID );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PIPE_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PIPE_SEL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PDWN_LITE , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_CHECK_SYNC , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_CHECK_SYNC );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DDC , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DDC );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PRBS_SEED_DFE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_DFE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_DFE_FORCE_LOAD_SEED , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DFE_FORCE_LOAD_SEED );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PSAVE_MODE_DISABLE , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_IOCLK_SLIP_STROBE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IOCLK_SLIP_STROBE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_HISTORY_PRBS_POWER_UP , 62  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_HISTORY_PRBS_POWER_UP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_CNTLX1_EO_PL_PSAVE_RESYNC_DISABLE , 63  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PSAVE_RESYNC_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_LANE_DIG_PDWN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DIG_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_BER_DPIPE_MUX_SEL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_DPIPE_MUX_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_LANE_SCRAMBLE_DISABLE , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_FIFO_HALF_WIDTH_MODE , 58  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_FIFO_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_SYNC_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SYNC_MODE );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_EO_PL_PRBS_RXBIST_MODE , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_RXBIST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_EO_PL_PR_PHASE_STEP_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_PHASE_STEP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_BER_CFG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_BER_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_FIFO_DLY_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_DLY_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_DDC_CFG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DDC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_MODE3_EO_PL_INIT_TMR_CFG_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INIT_TMR_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_BIT_STAT3_EO_PL_A_PR_DFE_CLKADJ_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PR_DFE_CLKADJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PDWN_LITE_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PDWN_LITE_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_LANE_ANA_PDWN , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_ANA_PDWN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_EO_PL_PRBS_TEST_DATA_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_TEST_DATA_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2E_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL1_E_PL_A_H2O_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H2O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_A_CONTROLS , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_A_CONTROLS_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CONTROLS_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_CM_CNTL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CNTL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_EO_PL_PR_IQ_RES_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PR_IQ_RES_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL2_E_PL_A_H3O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H3O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_EO_PL_A_OFFSET_E1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_E1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL3_E_PL_A_H4O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H4O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O0_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O0_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1 );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_EO_PL_A_OFFSET_O1_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_OFFSET_O1_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5E_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5E_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5O_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL4_E_PL_A_H5O_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H5O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_INTEG_COARSE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_INTEG_COARSE_GAIN_LEN , 4   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_INTEG_COARSE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN , 52  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_EVEN_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN , 57  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_EO_PL_A_ODD_INTEG_FINE_GAIN_LEN , 5   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H6_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H6_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H6_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H7_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL5_E_PL_A_H7_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H7_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_PEAK_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_PEAK_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_EO_PL_A_CTLE_GAIN_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_CTLE_GAIN_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H8_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H8_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H8_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H9_VAL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL   );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL6_E_PL_A_H9_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H9_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1E_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1E_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1E_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1O_VAL , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_EO_PL_A_H1O_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1O_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H10_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H10_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H10_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H11_VAL  , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL7_E_PL_A_H11_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H11_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL_AMP_VAL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_EO_PL_AMP_VAL_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL_A_H12_VAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL  );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL8_E_PL_A_H12_VAL_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H12_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1ARATIO_VAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1ARATIO_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_VAL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DAC_CNTL9_E_PL_A_H1CAL_EN , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1CAL_EN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_0  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_1  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_2  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_3  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_4  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_5  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_6  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_DATA_DAC_SPARE_MODE_PL_7  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_FIR_ERROR_INJECT_PL_ERR_INJ_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_FIR_MASK_PL_ERRS_LEN      , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_0           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_1           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_2           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_3           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_4           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_5           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_6           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RXPACKS3_SLICE5_RX_SPARE_MODE_PL_7           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME      , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PRBS_TEST_TIME );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PRBS_TEST_TIME_LEN  , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PRBS_TEST_TIME_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL10_EO_PG_BIST_BUS_DATA_MODE       , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_BUS_DATA_MODE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME      , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PRBS_PROP_TIME );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PRBS_PROP_TIME_LEN  , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PRBS_PROP_TIME_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PLL_LOCK_TIMEOUT    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PLL_LOCK_TIMEOUT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL10_EO_PG_BIST_PLL_LOCK_TIMEOUT_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_PLL_LOCK_TIMEOUT_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_LLMT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL11_EO_PG_DACTEST_LLMT_LEN         , 9   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_LLMT_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL11_EO_PG_DACTEST_RESET            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_RESET );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL11_EO_PG_DACTEST_START            , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_START );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_HLMT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL12_EO_PG_DACTEST_HLMT_LEN         , 9   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DACTEST_HLMT_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_VALID , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_VALID );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_LANE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LANE_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_LANE_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH       , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL13_EO_PG_HIST_MIN_EYE_WIDTH_LEN   , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_VALID , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_VALID );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_LANE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LANE_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_LANE_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT      , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL14_EO_PG_HIST_MIN_EYE_HEIGHT_LEN  , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL15_EO_PG_WTL_TEST_CLOCK           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WTL_TEST_CLOCK );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL15_EO_PG_WTL_TEST_DATA            , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WTL_TEST_DATA );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL15_EO_PG_WT_BS_CLOCK_EN_BYP       , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_BS_CLOCK_EN_BYP );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL15_EO_PG_WT_BS_DATA_EN_BYP        , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_BS_DATA_EN_BYP );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL1_EO_PG_BER_EN                    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_EN     );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL1_EO_PG_BER_TIMER_FREEZE_EN       , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_TIMER_FREEZE_EN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL1_EO_PG_BER_COUNT_FREEZE_EN       , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_COUNT_FREEZE_EN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL             , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_COUNT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL1_EO_PG_BER_COUNT_SEL_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_COUNT_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL             , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_TIMER_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL1_EO_PG_BER_TIMER_SEL_LEN         , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_TIMER_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL1_EO_PG_BER_CLR_COUNT_ON_READ_EN  , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CLR_COUNT_ON_READ_EN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL1_EO_PG_BER_CLR_TIMER_ON_READ_EN  , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_CLR_TIMER_ON_READ_EN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL1_E_PG_START_WIRETEST             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_WIRETEST );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL1_E_PG_START_DESKEW               , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_DESKEW );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL1_E_PG_START_EYE_OPT              , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_EYE_OPT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL1_E_PG_START_REPAIR               , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_REPAIR );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL1_E_PG_START_FUNC_MODE            , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_FUNC_MODE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL1_E_PG_START_DC_CALIBRATE         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_DC_CALIBRATE );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL2_EO_PG_TRC_MODE                  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRC_MODE   );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL2_EO_PG_TRC_MODE_LEN              , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRC_MODE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL3_EO_PG_INT_MODE                  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_MODE   );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL3_EO_PG_INT_MODE_LEN              , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_CURRENT_STATE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL3_EO_PG_INT_CURRENT_STATE_LEN     , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_CURRENT_STATE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_ENABLE_ENC );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL4_EO_PG_INT_ENABLE_ENC_LEN        , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_ENABLE_ENC_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE            , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_NEXT_STATE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL4_EO_PG_INT_NEXT_STATE_LEN        , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_NEXT_STATE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL4_E_PG_WT_CU_PLL_PGOOD            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_CU_PLL_PGOOD );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL4_E_PG_WT_CU_BYP_PLL_LOCK         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_CU_BYP_PLL_LOCK );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL4_E_PG_WT_PLL_REFCLKSEL           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_PLL_REFCLKSEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL4_E_PG_PLL_REFCLKSEL_SCOM_EN      , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PLL_REFCLKSEL_SCOM_EN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL4_E_PG_IORESET                    , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE            , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_GOTO_STATE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL5_EO_PG_INT_GOTO_STATE_LEN        , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_GOTO_STATE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_RETURN_STATE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL6_EO_PG_INT_RETURN_STATE_LEN      , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_INT_RETURN_STATE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL8_EO_PG_SERVO_OP                  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_OP   );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL8_EO_PG_SERVO_OP_LEN              , 15  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_OP_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL8_EO_PG_SERVO_DONE                , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_DONE );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL9_EO_PG_BIST_EN                   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EN    );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL9_EO_PG_BIST_EXT_START_MODE       , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EXT_START_MODE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_INIT_DISABLE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL9_EO_PG_BIST_INIT_DISABLE_LEN     , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_INIT_DISABLE_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL9_EO_PG_BIST_CUPLL_LOCK_CHECK_EN  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_CUPLL_LOCK_CHECK_EN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_STORE_EYES_LANE_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_LANE_SEL_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_STORE_EYES_LANE_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL  , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_STORE_EYES_BANK_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL9_EO_PG_BIST_STORE_EYES_BANK_SEL_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_STORE_EYES_BANK_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTL9_EO_PG_PERVASIVE_CAPT            , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PERVASIVE_CAPT );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_SHDW_DONE_FIN_GCRMSG , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_SHDW_DONE_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_SHDW_NOP_FIN_GCRMSG  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_SHDW_NOP_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_SHDW_RPR_DONE_FIN_GCRMSG , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_SHDW_RPR_DONE_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_SHDW_RPR_NOP_FIN_GCRMSG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_SHDW_RPR_NOP_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_DONE_FIN_GCRMSG , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_UNSHDW_DONE_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_NOP_FIN_GCRMSG , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_UNSHDW_NOP_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_RPR_DONE_FIN_GCRMSG , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_UNSHDW_RPR_DONE_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_UNSHDW_RPR_NOP_FIN_GCRMSG , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_UNSHDW_RPR_NOP_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_RECAL_DONE_NOP_FIN_GCRMSG , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_RECAL_DONE_NOP_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_RECAL_FAIL_NOP_FIN_GCRMSG , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_RECAL_FAIL_NOP_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_RECAL_FRESULTS_FIN_GCRMSG , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_RECAL_FRESULTS_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_RECAL_ABORT_ACK_FIN_GCRMSG , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_RECAL_ABORT_ACK_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_RECAL_ABORT_MNOP_FIN_GCRMSG , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_RECAL_ABORT_MNOP_FIN_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX10_E_PG_SLV_RECAL_ABORT_SNOP_FIN_GCRMSG , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_RECAL_ABORT_SNOP_FIN_GCRMSG );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_SEQ_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SEQ_GCRMSG_LEN    , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_SEQ_GCRMSG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SKMIN_GCRMSG      , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_SKMIN_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SKMIN_GCRMSG_LEN  , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_SKMIN_GCRMSG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG      , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_SKMAX_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX11_E_PG_DESKEW_SKMAX_GCRMSG_LEN  , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_SKMAX_GCRMSG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX5_E_PG_DYN_RPR_REQ_GCRMSG        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_REQ_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX5_E_PG_DYN_RPR_LANE2RPR_GCRMSG   , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_LANE2RPR_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX5_E_PG_DYN_RPR_LANE2RPR_GCRMSG_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_LANE2RPR_GCRMSG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX5_E_PG_DYN_RPR_IP_GCRMSG         , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_IP_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX5_E_PG_DYN_RPR_COMPLETE_GCRMSG   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_COMPLETE_GCRMSG );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_GCRMSG_LEN      , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_GCRMSG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_VAL_GCRMSG      , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_VAL_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG      , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_PHY_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_CNTLX7_EO_PG_CAL_LANE_PHY_GCRMSG_LEN  , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_PHY_GCRMSG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_INIT_CFG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE10_EO_PG_AMP_INIT_CFG_LEN         , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_INIT_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG            , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_RECAL_CFG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE10_EO_PG_AMP_RECAL_CFG_LEN        , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_RECAL_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG            , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_INIT_CFG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE10_EO_PG_PEAK_INIT_CFG_LEN        , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_INIT_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG           , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_RECAL_CFG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE10_EO_PG_PEAK_RECAL_CFG_LEN       , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_RECAL_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE10_EO_PG_AMP_CFG                  , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_CFG    );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE10_EO_PG_AMP_CFG_LEN              , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE10_E_PG_DESKEW_MAX_LIMIT          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_MAX_LIMIT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE10_E_PG_DESKEW_MAX_LIMIT_LEN      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_MAX_LIMIT_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_INIT_CFG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE11_EO_PG_OFF_INIT_CFG_LEN         , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_INIT_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG            , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_RECAL_CFG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE11_EO_PG_OFF_RECAL_CFG_LEN        , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_RECAL_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE11_EO_PG_CM_CFG                   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CFG     );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE11_EO_PG_CM_CFG_LEN               , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE11_EO_PG_AMIN_CFG                 , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMIN_CFG   );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE11_EO_PG_AMIN_CFG_LEN             , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMIN_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE11_EO_PG_USERDEF_CFG              , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USERDEF_CFG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE11_EO_PG_USERDEF_CFG_LEN          , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USERDEF_CFG_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE11_E_PG_LANE_DISABLED_VEC_0_15    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_0_15 );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE11_E_PG_LANE_DISABLED_VEC_0_15_LEN , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_CHG_CFG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE12_EO_PG_SERVO_CHG_CFG_LEN        , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_CHG_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE12_EO_PG_DAC_BO_CFG               , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DAC_BO_CFG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE12_EO_PG_DAC_BO_CFG_LEN           , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DAC_BO_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE12_EO_PG_FILTER_MODE              , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FILTER_MODE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE12_EO_PG_FILTER_MODE_LEN          , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FILTER_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE12_EO_PG_MISC_CFG                 , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CFG   );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE12_EO_PG_MISC_CFG_LEN             , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MISC_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE12_EO_PG_DISABLE_H1_CLEAR         , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_H1_CLEAR );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE12_EO_PG_VOFF_CFG                 , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_VOFF_CFG   );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE12_EO_PG_VOFF_CFG_LEN             , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_VOFF_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE12_EO_PG_LOFF_AMP_EN              , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LOFF_AMP_EN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE12_E_PG_LANE_DISABLED_VEC_16_23   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_16_23 );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE12_E_PG_LANE_DISABLED_VEC_16_23_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_16_23_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL            , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_OFFSET_VAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE13_EO_PG_CM_OFFSET_VAL_LEN        , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_OFFSET_VAL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE13_EO_PG_SERVO_THRESH1            , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH1 );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE13_EO_PG_SERVO_THRESH1_LEN        , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH1_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE13_EO_PG_SERVO_THRESH2            , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH2 );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE13_EO_PG_SERVO_THRESH2_LEN        , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH2_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_INIT_TIMEOUT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE14_EO_PG_AMP_INIT_TIMEOUT_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_INIT_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT        , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_RECAL_TIMEOUT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE14_EO_PG_AMP_RECAL_TIMEOUT_LEN    , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_RECAL_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT        , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_INIT_TIMEOUT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE14_EO_PG_PEAK_INIT_TIMEOUT_LEN    , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_INIT_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT       , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_RECAL_TIMEOUT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE14_EO_PG_PEAK_RECAL_TIMEOUT_LEN   , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_RECAL_TIMEOUT_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_INIT_TIMEOUT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE15_EO_PG_OFF_INIT_TIMEOUT_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_INIT_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT        , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_RECAL_TIMEOUT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE15_EO_PG_OFF_RECAL_TIMEOUT_LEN    , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_OFF_RECAL_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE15_EO_PG_CM_TIMEOUT               , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_TIMEOUT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE15_EO_PG_CM_TIMEOUT_LEN           , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CM_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT             , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMIN_TIMEOUT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE15_EO_PG_AMIN_TIMEOUT_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMIN_TIMEOUT_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_TIMEOUT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE16_EO_PG_AMP_TIMEOUT_LEN          , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USERDEF_TIMEOUT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE16_EO_PG_USERDEF_TIMEOUT_LEN      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USERDEF_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE16_EO_PG_BER_TIMEOUT              , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_TIMEOUT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE16_EO_PG_BER_TIMEOUT_LEN          , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BER_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT           , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE4_TIMEOUT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE16_EO_PG_SPARE4_TIMEOUT_LEN       , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE4_TIMEOUT_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE17_EO_PG_AMAX_HIGH                , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMAX_HIGH  );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE17_EO_PG_AMAX_HIGH_LEN            , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMAX_HIGH_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE17_EO_PG_AMAX_LOW                 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMAX_LOW   );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE17_EO_PG_AMAX_LOW_LEN             , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMAX_LOW_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP0_FILTER_MASK );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE18_EO_PG_AMP0_FILTER_MASK_LEN     , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP0_FILTER_MASK_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK         , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP1_FILTER_MASK );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE18_EO_PG_AMP1_FILTER_MASK_LEN     , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP1_FILTER_MASK_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTLE_GAIN_MAX );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE19_EO_PG_CTLE_GAIN_MAX_LEN        , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTLE_GAIN_MAX_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE19_EO_PG_AMP_START_VAL            , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_START_VAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE19_EO_PG_AMP_START_VAL_LEN        , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_START_VAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_EO_PG_CLKDIST_PDWN              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLKDIST_PDWN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH        , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_MIN_EYE_WIDTH );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_EO_PG_BIST_MIN_EYE_WIDTH_LEN    , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_MIN_EYE_WIDTH_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_EO_PG_A_BIST_EN                 , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BIST_EN  );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_MASTER_MODE                , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MASTER_MODE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_DISABLE_FENCE_RESET        , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_FENCE_RESET );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_ACT_CHECK_TIMEOUT_SEL      , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACT_CHECK_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_ACT_CHECK_TIMEOUT_SEL_LEN  , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ACT_CHECK_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_BIST_JITTER_PULSE_SEL      , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_JITTER_PULSE_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_BIST_JITTER_PULSE_SEL_LEN  , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_JITTER_PULSE_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_FENCE                      , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FENCE      );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_PDWN_LITE_DISABLE          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_DISABLE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_USE_SLS_AS_SPR             , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USE_SLS_AS_SPR );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_DYN_RECAL_SUSPEND          , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_SUSPEND );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_WT_PATTERN_LENGTH          , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_PATTERN_LENGTH );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE1_E_PG_WT_PATTERN_LENGTH_LEN      , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_PATTERN_LENGTH_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_CONVERGED_CNT_MAX );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE20_EO_PG_DFE_CONVERGED_CNT_MAX_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_CONVERGED_CNT_MAX_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX    , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AP110_AP010_DELTA_MAX );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE20_EO_PG_AP110_AP010_DELTA_MAX_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AP110_AP010_DELTA_MAX_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_INTEG_LATCH_OFFSET_CAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_INTEG_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_COARSE_CAL   , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CTLE_COARSE_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DAC_H1_CAL        , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DAC_H1_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_VGA_CAL           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_VGA_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DFE_H1_CAL        , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DFE_H1_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_H1AP_TWEAK        , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_H1AP_TWEAK );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DDC               , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DDC );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_CM_COARSE_CAL     , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CM_COARSE_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_CM_FINE_CAL       , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CM_FINE_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_BER_TEST          , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_BER_TEST );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_RESULT_CHECK      , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_RESULT_CHECK );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_CTLE_EDGE_TRACK_ONLY , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CTLE_EDGE_TRACK_ONLY );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DFE_H2_H12_CAL    , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DFE_H2_H12_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DAC_H1_TO_A_CAL   , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DAC_H1_TO_A_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_FINAL_L2U_ADJ     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_FINAL_L2U_ADJ );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE21_EO_PG_ENABLE_DONE_SIGNALING    , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DONE_SIGNALING );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_INTEG_LATCH_OFFSET_CAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_INTEG_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_COARSE_CAL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_CTLE_COARSE_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_DAC_H1_CAL     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DAC_H1_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_VGA_CAL        , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_VGA_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_DFE_H1_CAL     , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DFE_H1_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_H1AP_TWEAK     , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_H1AP_TWEAK );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_DDC            , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DDC );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_COARSE_CAL  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_CM_COARSE_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_CM_FINE_CAL    , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_CM_FINE_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_BER_TEST       , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_BER_TEST );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_RESULT_CHECK   , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_RESULT_CHECK );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_CTLE_EDGE_TRACK_ONLY , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_CTLE_EDGE_TRACK_ONLY );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_DFE_H2_H12_CAL , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DFE_H2_H12_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE22_EO_PG_RC_ENABLE_DAC_H1_TO_A_CAL , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DAC_H1_TO_A_CAL );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE23_EO_PG_QUAD_SEL                 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_QUAD_SEL   );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE23_EO_PG_QUAD_SEL_LEN             , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_QUAD_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE23_EO_PG_PEAK_TUNE                , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_TUNE  );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE23_EO_PG_LTE_EN                   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LTE_EN     );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE23_EO_PG_IQSPD_CFG                , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IQSPD_CFG  );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE23_EO_PG_IQSPD_CFG_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IQSPD_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE23_EO_PG_DFEHISPD_EN              , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFEHISPD_EN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE23_EO_PG_DFE12_EN                 , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE12_EN   );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE24_EO_PG_H1AP_CFG                 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_H1AP_CFG   );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE24_EO_PG_H1AP_CFG_LEN             , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_H1AP_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE24_EO_PG_CTLE_UPDATE_MODE         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTLE_UPDATE_MODE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK         , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USER_FILTER_MASK );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE24_EO_PG_USER_FILTER_MASK_LEN     , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USER_FILTER_MASK_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_VGA_AMAX_MODE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_VGA_AMAX_MODE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H2_H12_SUBSTEP , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H2_H12_SUBSTEP_LEN , 11  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_DFE_VOLTAGE_MODE  , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DFE_VOLTAGE_MODE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE26_EO_PG_ENABLE_DFE_H6_H12_FAST_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_DFE_H6_H12_FAST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL , 49  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_VGA_AMAX_MODE  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_VGA_AMAX_MODE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H2_H12_SUBSTEP , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H2_H12_SUBSTEP_LEN , 11  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_VOLTAGE_MODE , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DFE_VOLTAGE_MODE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE27_EO_PG_RC_ENABLE_DFE_H6_H12_FAST_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RC_ENABLE_DFE_H6_H12_FAST_MODE );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_COARSE_CAL  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DC_ENABLE_CM_COARSE_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_CM_FINE_CAL    , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DC_ENABLE_CM_FINE_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL , 50  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL , 51  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_INTEG_LATCH_OFFSET_CAL , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DC_ENABLE_INTEG_LATCH_OFFSET_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_DAC_H1_CAL     , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DC_ENABLE_DAC_H1_CAL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE28_EO_PG_DC_ENABLE_DAC_H1_TO_A_CAL , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DC_ENABLE_DAC_H1_TO_A_CAL );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE29_EO_PG_APX111_HIGH              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_APX111_HIGH );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE29_EO_PG_APX111_HIGH_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_APX111_HIGH_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE29_EO_PG_APX111_LOW               , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_APX111_LOW );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE29_EO_PG_APX111_LOW_LEN           , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_APX111_LOW_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE2_EO_PG_DFE_CA_CFG                , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_CA_CFG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE2_EO_PG_DFE_CA_CFG_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_CA_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL             , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_CONTROL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE2_EO_PG_SCOPE_CONTROL_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SCOPE_CONTROL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE2_EO_PG_DATA_PIPE_CLR_ON_READ_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DATA_PIPE_CLR_ON_READ_MODE );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE2_E_PG_WTR_MAX_BAD_LANES          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WTR_MAX_BAD_LANES );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE2_E_PG_WTR_MAX_BAD_LANES_LEN      , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WTR_MAX_BAD_LANES_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE2_E_PG_SLS_EXTEND_SEL             , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_EXTEND_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE2_E_PG_SLS_EXTEND_SEL_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_EXTEND_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE2_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE2_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_EO_PG_SERVO_THRESH3             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH3 );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_EO_PG_SERVO_THRESH3_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_THRESH3_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_EO_PG_DFE_HTAP_CFG              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_HTAP_CFG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_EO_PG_DFE_HTAP_CFG_LEN          , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_HTAP_CFG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_EO_PG_DFE_INIT_TIMEOUT          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_INIT_TIMEOUT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_EO_PG_DFE_INIT_TIMEOUT_LEN      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_INIT_TIMEOUT_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_EO_PG_DFE_RECAL_TIMEOUT         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_RECAL_TIMEOUT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_EO_PG_DFE_RECAL_TIMEOUT_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DFE_RECAL_TIMEOUT_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_E_PG_SLS_TIMEOUT_SEL            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_E_PG_SLS_TIMEOUT_SEL_LEN        , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_E_PG_CL_TIMEOUT_SEL             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CL_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_E_PG_CL_TIMEOUT_SEL_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CL_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_E_PG_DS_SKEW_TIMEOUT_SEL        , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DS_SKEW_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_E_PG_DS_SKEW_TIMEOUT_SEL_LEN    , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DS_SKEW_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_E_PG_DS_TIMEOUT_SEL             , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DS_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE3_E_PG_DS_TIMEOUT_SEL_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DS_TIMEOUT_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE4_EO_PG_DISABLE_2TO12_CLEAR       , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_2TO12_CLEAR );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE4_EO_PG_PEAK_ENABLE_DAC_CFG       , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PEAK_ENABLE_DAC_CFG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE4_EO_PG_AMIN_ENABLE_HDAC          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMIN_ENABLE_HDAC );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE4_EO_PG_USE_PREV_COARSE_VAL       , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_USE_PREV_COARSE_VAL );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE4_E_PG_WT_CHECK_COUNT             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_CHECK_COUNT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE4_E_PG_WT_CHECK_COUNT_LEN         , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_CHECK_COUNT_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE4_E_PG_PGOOD_TIMEOUT_SEL          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PGOOD_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE4_E_PG_PGOOD_TIMEOUT_SEL_LEN      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PGOOD_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE4_E_PG_PLL_LOCK_TIMEOUT_SEL       , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PLL_LOCK_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE4_E_PG_PLL_LOCK_TIMEOUT_SEL_LEN   , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PLL_LOCK_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE4_E_PG_PSAVE_TIMER_WAKEUP_MODE    , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_TIMER_WAKEUP_MODE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE4_E_PG_PSAVE_WAKEUP_LANE0_ENABLE  , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_WAKEUP_LANE0_ENABLE );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE5_EO_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE5_EO_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE5_EO_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE5_EO_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN , 2   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL      , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRACKING_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE5_EO_PG_TRACKING_TIMEOUT_SEL_LEN  , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TRACKING_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE5_EO_PG_PUP_LITE_WAIT_SEL         , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PUP_LITE_WAIT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE5_EO_PG_PUP_LITE_WAIT_SEL_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PUP_LITE_WAIT_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE5_E_PG_FIFO_INITIAL_L2U_DLY       , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_INITIAL_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE5_E_PG_FIFO_INITIAL_L2U_DLY_LEN   , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_INITIAL_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE5_E_PG_FIFO_FINAL_L2U_DLY         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_FINAL_L2U_DLY );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE5_E_PG_FIFO_FINAL_L2U_DLY_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_FINAL_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE5_E_PG_WT_TIMEOUT_SEL             , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE5_E_PG_WT_TIMEOUT_SEL_LEN         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_TIMEOUT_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT       , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CONVERGED_END_COUNT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE6_EO_PG_CONVERGED_END_COUNT_LEN   , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CONVERGED_END_COUNT_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE   , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_MODE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_WIDTH_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_WIDTH_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_MODE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE6_EO_PG_HIST_MIN_EYE_HEIGHT_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_HIST_MIN_EYE_HEIGHT_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX          , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_GAIN_CNT_MAX );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE6_EO_PG_AMP_GAIN_CNT_MAX_LEN      , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_AMP_GAIN_CNT_MAX_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE6_E_PG_TX_BUS_WIDTH               , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TX_BUS_WIDTH );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE6_E_PG_TX_BUS_WIDTH_LEN           , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TX_BUS_WIDTH_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE6_E_PG_RX_BUS_WIDTH               , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RX_BUS_WIDTH );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE6_E_PG_RX_BUS_WIDTH_LEN           , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RX_BUS_WIDTH_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_CHECK_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_EO_PG_ABORT_CHECK_TIMEOUT_SEL_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ABORT_CHECK_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL       , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_POLLING_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_EO_PG_POLLING_TIMEOUT_SEL_LEN   , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_POLLING_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_EO_PG_PSAVE_MODE_TIMEOUT_SEL    , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_EO_PG_PSAVE_MODE_TIMEOUT_SEL_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_EO_PG_DYN_RECAL_OVERALL_TIMEOUT_SEL , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_EO_PG_DYN_RECAL_OVERALL_TIMEOUT_SEL_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_SLS_DISABLE                , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_DISABLE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_TX_SLS_DISABLE             , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TX_SLS_DISABLE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_SLS_CNTR_TAP_PTS           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_CNTR_TAP_PTS );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_SLS_CNTR_TAP_PTS_LEN       , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_CNTR_TAP_PTS_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS        , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NONSLS_CNTR_TAP_PTS );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_NONSLS_CNTR_TAP_PTS_LEN    , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NONSLS_CNTR_TAP_PTS_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_SR_FINAL_NOP_TIMEOUT_SEL   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_SR_FINAL_NOP_TIMEOUT_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_SLS_EXCEPTION2_CS          , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_EXCEPTION2_CS );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_DYN_RPR_ERR_CNTR1_FILTER_MODE , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ERR_CNTR1_FILTER_MODE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE7_E_PG_DYN_RPR_ERR_CNTR1_FILTER_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ERR_CNTR1_FILTER_MODE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE8_EO_PG_MAX_BER_CHECK_COUNT       , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MAX_BER_CHECK_COUNT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE8_EO_PG_MAX_BER_CHECK_COUNT_LEN   , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MAX_BER_CHECK_COUNT_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_BAD_LANE_MAX       , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_BAD_LANE_MAX );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_BAD_LANE_MAX_LEN   , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_BAD_LANE_MAX_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_ERR_CNTR1_DURATION , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ERR_CNTR1_DURATION );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_ERR_CNTR1_DURATION_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ERR_CNTR1_DURATION_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_CLR_ERR_CNTR1      , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_CLR_ERR_CNTR1 );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_DISABLE            , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_DISABLE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE8_E_PG_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH             , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MIN_EYE_WIDTH );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE9_EO_PG_MIN_EYE_WIDTH_LEN         , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MIN_EYE_WIDTH_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT            , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MIN_EYE_HEIGHT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE9_EO_PG_MIN_EYE_HEIGHT_LEN        , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MIN_EYE_HEIGHT_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_BAD_BUS_MAX        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_BAD_BUS_MAX );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_BAD_BUS_MAX_LEN    , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_BAD_BUS_MAX_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_ERR_CNTR2_DURATION , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ERR_CNTR2_DURATION );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_ERR_CNTR2_DURATION_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_ERR_CNTR2_DURATION_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_CLR_ERR_CNTR2      , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_CLR_ERR_CNTR2 );
+REG64_FLD( XBUS_1_RX1_RX_CTL_MODE9_E_PG_DYN_RPR_DISABLE2           , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_DISABLE2 );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT1_EO_PG_SERVO_RESULT              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_RESULT );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT1_EO_PG_SERVO_RESULT_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_RESULT_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT1_E_PG_WIRETEST_DONE              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WIRETEST_DONE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT1_E_PG_DESKEW_DONE                , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_DONE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT1_E_PG_EYE_OPT_DONE               , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_EYE_OPT_DONE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT1_E_PG_REPAIR_DONE                , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPAIR_DONE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT1_E_PG_FUNC_MODE_DONE             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FUNC_MODE_DONE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT1_E_PG_DC_CALIBRATE_DONE          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DC_CALIBRATE_DONE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT1_E_PG_WIRETEST_FAILED            , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WIRETEST_FAILED );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT1_E_PG_DESKEW_FAILED              , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_FAILED );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT1_E_PG_EYE_OPT_FAILED             , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_EYE_OPT_FAILED );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT1_E_PG_REPAIR_FAILED              , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_REPAIR_FAILED );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT2_EO_PG_BIST_INIT_DONE            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_INIT_DONE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT2_EO_PG_BIST_DONE                 , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_DONE  );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT2_EO_PG_BIST_CU_PLL_ERR           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_CU_PLL_ERR );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT2_EO_PG_BIST_NO_EDGE_DET          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_NO_EDGE_DET );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EYE_A_WIDTH );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT2_EO_PG_BIST_EYE_A_WIDTH_LEN      , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EYE_A_WIDTH_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EYE_B_WIDTH );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT2_EO_PG_BIST_EYE_B_WIDTH_LEN      , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EYE_B_WIDTH_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT2_E_PG_LANE_BAD_VEC_0_15          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BAD_VEC_0_15 );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT2_E_PG_LANE_BAD_VEC_0_15_LEN      , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BAD_VEC_0_15_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT3_EO_PG_WTL_SM_STATUS             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WTL_SM_STATUS );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT3_EO_PG_WTL_SM_STATUS_LEN         , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WTL_SM_STATUS_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT4_E_PG_LANE_BAD_VEC_16_23         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BAD_VEC_16_23 );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT4_E_PG_LANE_BAD_VEC_16_23_LEN     , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BAD_VEC_16_23_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT5_E_PG_WT_CLK_LANE_INVERTED       , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_CLK_LANE_INVERTED );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT5_E_PG_WT_CLK_LANE_BAD_CODE       , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_CLK_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT5_E_PG_WT_CLK_LANE_BAD_CODE_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_CLK_LANE_BAD_CODE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT6_E_PG_DESKEW_MINSKEW_GRP         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_MINSKEW_GRP );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT6_E_PG_DESKEW_MINSKEW_GRP_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_MINSKEW_GRP_LEN );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT6_E_PG_DESKEW_MAXSKEW_GRP         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_MAXSKEW_GRP );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STAT6_E_PG_DESKEW_MAXSKEW_GRP_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_MAXSKEW_GRP_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_CTL_STATX8_E_PG_WT_PREV_DONE_GCRMSG       , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_PREV_DONE_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STATX8_E_PG_WT_ALL_DONE_GCRMSG        , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_ALL_DONE_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STATX8_E_PG_CD_PREV_DONE_GCRMSG       , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CD_PREV_DONE_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STATX8_E_PG_CD_ALL_DONE_GCRMSG        , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CD_ALL_DONE_GCRMSG );
+REG64_FLD( XBUS_1_RX1_RX_CTL_STATX8_E_PG_CNTLS_PREV_LDED_GCRMSG    , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CNTLS_PREV_LDED_GCRMSG );
+
+REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SCRAMBLE_MODE      , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SCRAMBLE_MODE_LEN  , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SEED_MODE          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_MODE );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTL1_E_PG_DESKEW_RATE             , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_RATE );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTL1_E_PG_RUN_DYN_RECAL_TIMER     , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RUN_DYN_RECAL_TIMER );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTL1_E_PG_DESKEW_PATTCHK_TIMEOUT_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_PATTCHK_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTL1_E_PG_DESKEW_PATTCHK_TIMEOUT_SEL_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_PATTCHK_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SLS_EXPECT );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_CNTL1_E_PG_PRBS_SLS_EXPECT_LEN     , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SLS_EXPECT_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_DATASM_SPARE_MODE_PG_0                    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_SPARE_MODE_PG_1                    , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_SPARE_MODE_PG_2                    , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_SPARE_MODE_PG_3                    , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_SPARE_MODE_PG_4                    , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_SPARE_MODE_PG_5                    , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_SPARE_MODE_PG_6                    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_SPARE_MODE_PG_7                    , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG         , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_CONFIG );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_SPARE_MODE_PG_SERVO_CONFIG_LEN     , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_CONFIG_LEN );
+REG64_FLD( XBUS_1_RX1_RX_DATASM_SPARE_MODE_PG_CTL_CLKDIST_PDWN     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_CLKDIST_PDWN );
+
+REG64_FLD( XBUS_1_RX1_RX_DATASM_STAT13_E_PG_BAD_BUS_LANE_ERR_CNTR_DIS_CLR , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BUS_LANE_ERR_CNTR_DIS_CLR );
+
+REG64_FLD( XBUS_1_RX1_RX_FIR1_ERROR_INJECT_PG_ERR_INJ              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RX_FIR1_ERROR_INJECT_PG_ERR_INJ_LEN          , 15  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_FIR1_MASK_PG_ERRS                         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RX_FIR1_MASK_PG_ERRS_LEN                     , 15  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RX_FIR2_ERROR_INJECT_PG_ERR_INJ              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_RX1_RX_FIR2_ERROR_INJECT_PG_ERR_INJ_LEN          , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_FIR2_MASK_PG_ERRS                         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX1_RX_FIR2_MASK_PG_ERRS_LEN                     , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_MASK_PG_ERROR                , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERROR      );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_MASK_PG_STATIC_SPARE_DEPLOYED , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATIC_SPARE_DEPLOYED );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_MASK_PG_STATIC_MAX_SPARES_EXCEEDED , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATIC_MAX_SPARES_EXCEEDED );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_MASK_PG_DYNAMIC_REPAIR_ERROR , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYNAMIC_REPAIR_ERROR );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_MASK_PG_DYNAMIC_SPARE_DEPLOYED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYNAMIC_SPARE_DEPLOYED );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_MASK_PG_DYNAMIC_MAX_SPARES_EXCEEDED , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYNAMIC_MAX_SPARES_EXCEEDED );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_MASK_PG_RECAL_ERROR          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ERROR );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_MASK_PG_RECAL_SPARE_DEPLOYED , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_SPARE_DEPLOYED );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_MASK_PG_RECAL_MAX_SPARES_EXCEEDED , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_MAX_SPARES_EXCEEDED );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_MASK_PG_TOO_MANY_BUS_ERRORS  , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TOO_MANY_BUS_ERRORS );
+
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_PG_ERROR                     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERROR      );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_PG_STATIC_SPARE_DEPLOYED     , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATIC_SPARE_DEPLOYED );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_PG_STATIC_MAX_SPARES_EXCEEDED , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_STATIC_MAX_SPARES_EXCEEDED );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_PG_DYNAMIC_REPAIR_ERROR      , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYNAMIC_REPAIR_ERROR );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_PG_DYNAMIC_SPARE_DEPLOYED    , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYNAMIC_SPARE_DEPLOYED );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_PG_DYNAMIC_MAX_SPARES_EXCEEDED , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYNAMIC_MAX_SPARES_EXCEEDED );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_PG_RECAL_ERROR               , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_ERROR );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_PG_RECAL_SPARE_DEPLOYED      , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_SPARE_DEPLOYED );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_PG_RECAL_MAX_SPARES_EXCEEDED , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_MAX_SPARES_EXCEEDED );
+REG64_FLD( XBUS_1_RX1_RX_FIR_TRAINING_PG_TOO_MANY_BUS_ERRORS       , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TOO_MANY_BUS_ERRORS );
+
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL2_EO_PG_DYN_RPR_REQ_MANUAL      , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_REQ_MANUAL );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL2_EO_PG_CNT_SINGLE_LANE_RECAL   , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CNT_SINGLE_LANE_RECAL );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_LANE_TO_MONITOR );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL2_EO_PG_RECAL_LANE_TO_MONITOR_LEN , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RECAL_LANE_TO_MONITOR_LEN );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL2_EO_PG_DYN_RPR_SM_MANUAL       , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RPR_SM_MANUAL );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL2_EO_PG_DIS_SYND_TALLYING       , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DIS_SYND_TALLYING );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL2_EO_PG_ENC_BUS_LANE2RPR_MANUAL , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENC_BUS_LANE2RPR_MANUAL );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL2_EO_PG_ENC_BUS_LANE2RPR_MANUAL_LEN , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENC_BUS_LANE2RPR_MANUAL_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_REQUEST    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MANUAL_RECAL_REQUEST );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE       , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MANUAL_RECAL_LANE );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTL3_EO_PG_MANUAL_RECAL_LANE_LEN   , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MANUAL_RECAL_LANE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTLX1_EO_PG_CLR_PAR_ERRS           , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLR_PAR_ERRS );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_CNTLX1_EO_PG_FIR_RESET              , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIR_RESET  );
+
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_SPARE_MODE_PG_0                     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_SPARE_MODE_PG_1                     , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_SPARE_MODE_PG_2                     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_SPARE_MODE_PG_3                     , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_SPARE_MODE_PG_4                     , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_SPARE_MODE_PG_5                     , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_SPARE_MODE_PG_6                     , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_SPARE_MODE_PG_7                     , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_SPARE_MODE_PG_DESKEW_BUMP_AFTER     , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_BUMP_AFTER );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_SPARE_MODE_PG_SLS_RCVY_DISABLE      , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_RCVY_DISABLE );
+
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT10_E_PG_SERVO_RECAL_IP          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SERVO_RECAL_IP );
+
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE1                , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE1  );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE1_LEN            , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE1_LEN );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE2                , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE2  );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE2_LEN            , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE2_LEN );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE_CODE            , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE_CODE );
+REG64_FLD( XBUS_1_RX1_RX_GLBSM_STAT9_E_PG_BAD_LANE_CODE_LEN        , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE_CODE_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_ID1_PG_BUS_ID                             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ID     );
+REG64_FLD( XBUS_1_RX1_RX_ID1_PG_BUS_ID_LEN                         , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ID_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_ID2_PG_START_LANE_ID                      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_LANE_ID );
+REG64_FLD( XBUS_1_RX1_RX_ID2_PG_START_LANE_ID_LEN                  , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_LANE_ID_LEN );
+REG64_FLD( XBUS_1_RX1_RX_ID2_PG_END_LANE_ID                        , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_END_LANE_ID );
+REG64_FLD( XBUS_1_RX1_RX_ID2_PG_END_LANE_ID_LEN                    , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_END_LANE_ID_LEN );
+
+REG64_FLD( XBUS_1_RX1_RX_SPARE_MODE_PG_0                           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_RX_SPARE_MODE_PG_1                           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_RX_SPARE_MODE_PG_2                           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_RX_SPARE_MODE_PG_3                           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_RX_SPARE_MODE_PG_4                           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE0_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE10_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE11_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE12_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE13_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE14_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE15_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE16_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE17_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE18_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE19_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE1_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE20_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE21_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE22_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_0         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_1         , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_2         , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_3         , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_4         , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_5         , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_6         , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_DATA_WORK_SPARE_MODE_PL_7         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK   , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_SKEW         , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BAD_DESKEW       , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT1_EO_PL_BIST_ERR         , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT2_EO_PL_A_AP             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT2_EO_PL_A_AP_LEN         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD   , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE23_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE2_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE3_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE4_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE5_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE6_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE7_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE8_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_0          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_1          , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_2          , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_3          , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_4          , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_5          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_6          , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_DATA_WORK_SPARE_MODE_PL_7          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_BER   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_BER );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_WIDTH , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_WIDTH );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_HEIGHT , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_HEIGHT );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_EYE_OPT_DDC   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_EYE_OPT_DDC );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_DISABLED  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_DISABLED );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_WT_LANE_BAD_CODE_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_LANE_BAD_CODE_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_BLOCK_LOCK    , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_BLOCK_LOCK );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_SKEW          , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_SKEW   );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BAD_DESKEW        , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_DESKEW );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT1_EO_PL_BIST_ERR          , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_ERR   );
+
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT2_EO_PL_A_BAD_DFE_CONV    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_BAD_DFE_CONV );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT2_EO_PL_A_H1AP_AT_LIMIT   , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_H1AP_AT_LIMIT );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT2_EO_PL_A_AP              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP       );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT2_EO_PL_A_AP_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_AP_LEN   );
+
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_EVEN_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_EVEN_LEN );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD    , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD );
+REG64_FLD( XBUS_1_RX1_SLICE9_RX_WORK_STAT3_EO_PL_A_PATH_OFF_ODD_LEN , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_A_PATH_OFF_ODD_LEN );
+
+REG64_FLD( XBUS_1_RX_FIR_ERROR_INJECT_PB_ERRS_INJ                  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_INJ   );
+REG64_FLD( XBUS_1_RX_FIR_ERROR_INJECT_PB_ERRS_INJ_LEN              , 10  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_INJ_LEN );
+
+REG64_FLD( XBUS_1_RX_FIR_MASK_PB_ERRS                              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_RX_FIR_MASK_PB_ERRS_LEN                          , 10  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+
+REG64_FLD( XBUS_1_RX_FIR_RESET_PB_CLR_PAR_ERRS                     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLR_PAR_ERRS );
+REG64_FLD( XBUS_1_RX_FIR_RESET_PB_RESET                            , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET      );
+
+REG64_FLD( XBUS_1_SCOM_MODE_PB_GCR_TEST                            , 0   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_GCR_TEST   );
+REG64_FLD( XBUS_1_SCOM_MODE_PB_ENABLE_GCR_OFL_BUFF                 , 1   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ENABLE_GCR_OFL_BUFF );
+REG64_FLD( XBUS_1_SCOM_MODE_PB_IORESET_HARD_BUS0                   , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IORESET_HARD_BUS0 );
+REG64_FLD( XBUS_1_SCOM_MODE_PB_MMIO_PG_REG_ACCESS                  , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MMIO_PG_REG_ACCESS );
+REG64_FLD( XBUS_1_SCOM_MODE_PB_SPARES1                             , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARES1    );
+REG64_FLD( XBUS_1_SCOM_MODE_PB_SPARES1_LEN                         , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARES1_LEN );
+REG64_FLD( XBUS_1_SCOM_MODE_PB_GCR_HANG_DET_SEL                    , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_GCR_HANG_DET_SEL );
+REG64_FLD( XBUS_1_SCOM_MODE_PB_GCR_HANG_DET_SEL_LEN                , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_GCR_HANG_DET_SEL_LEN );
+REG64_FLD( XBUS_1_SCOM_MODE_PB_GCR_BUFFER_ENABLED_RO_SIGNAL        , 11  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_GCR_BUFFER_ENABLED_RO_SIGNAL );
+REG64_FLD( XBUS_1_SCOM_MODE_PB_GCR_HANG_ERROR_MASK                 , 12  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_GCR_HANG_ERROR_MASK );
+REG64_FLD( XBUS_1_SCOM_MODE_PB_GCR_HANG_ERROR_INJ                  , 13  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_GCR_HANG_ERROR_INJ );
+REG64_FLD( XBUS_1_SCOM_MODE_PB_PPE_GCR                             , 14  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PPE_GCR    );
+REG64_FLD( XBUS_1_SCOM_MODE_PB_CHAN_FAIL_MASK                      , 15  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CHAN_FAIL_MASK );
+REG64_FLD( XBUS_1_SCOM_MODE_PB_CHAN_FAIL_MASK_LEN                  , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CHAN_FAIL_MASK_LEN );
+REG64_FLD( XBUS_1_SCOM_MODE_PB_SPARES2                             , 23  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARES2    );
+REG64_FLD( XBUS_1_SCOM_MODE_PB_SPARES2_LEN                         , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARES2_LEN );
+
+REG64_FLD( XBUS_IOPPE_SCOM_PPE_CNTL_IORESET                        , 0   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+REG64_FLD( XBUS_IOPPE_SCOM_PPE_CNTL_PDWN                           , 1   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_PDWN       );
+REG64_FLD( XBUS_IOPPE_SCOM_PPE_CNTL_INTERRUPT                      , 2   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_INTERRUPT  );
+REG64_FLD( XBUS_IOPPE_SCOM_PPE_CNTL_ARB_ECC_INJECT_ERR             , 3   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_ARB_ECC_INJECT_ERR );
+REG64_FLD( XBUS_IOPPE_SCOM_PPE_CNTL_SPARES                         , 4   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_SPARES     );
+REG64_FLD( XBUS_IOPPE_SCOM_PPE_CNTL_SPARES_LEN                     , 12  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_SPARES_LEN );
+
+REG64_FLD( XBUS_IOPPE_SCOM_PPE_FLAGS_FIELD                         , 0   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FIELD      );
+REG64_FLD( XBUS_IOPPE_SCOM_PPE_FLAGS_FIELD_LEN                     , 16  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM2_CLEAR,
+           SH_FLD_FIELD_LEN  );
+
+REG64_FLD( XBUS_IOPPE_SCOM_PPE_WORK_REG1_WORK1                     , 0   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_WORK1      );
+REG64_FLD( XBUS_IOPPE_SCOM_PPE_WORK_REG1_WORK1_LEN                 , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_WORK1_LEN  );
+
+REG64_FLD( XBUS_IOPPE_SCOM_PPE_WORK_REG2_WORK2                     , 0   , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_WORK2      );
+REG64_FLD( XBUS_IOPPE_SCOM_PPE_WORK_REG2_WORK2_LEN                 , 32  , SH_UNT_XBUS_IOPPE, SH_ACS_SCOM     ,
+           SH_FLD_WORK2_LEN  );
+
+REG64_FLD( XBUS_1_SPARE_MODE_PB_0                                  , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_SPARE_MODE_PB_1                                  , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_SPARE_MODE_PB_2                                  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_SPARE_MODE_PB_3                                  , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_SPARE_MODE_PB_4                                  , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_SPARE_MODE_PB_5                                  , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_SPARE_MODE_PB_6                                  , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_SPARE_MODE_PB_7                                  , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_HI_DATA_REG_DATA          , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN      , 64  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_DATA          , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN      , 32  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS       , 32  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN   , 10  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK     , 42  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9   , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN  , 52  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING       , 53  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS  , 54  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_XBUS_PERV,
+           SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_XBUS_PERV,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_XBUS_PERV,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_XBUS_PERV,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA  , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB  , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC  , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND  , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA     , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB     , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC     , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD     , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_XBUS_PERV,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_HI_DATA_REG_DATA          , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN      , 64  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_DATA          , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN      , 32  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS       , 32  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN   , 10  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK     , 42  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9   , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN  , 52  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING       , 53  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS  , 54  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_XBUS_PERV,
+           SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_XBUS_PERV,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_XBUS_PERV,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_XBUS_PERV,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA  , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB  , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC  , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND  , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA     , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB     , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC     , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD     , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_XBUS_PERV,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( XBUS_PERV_TCXB_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_HI_DATA_REG_DATA          , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN      , 64  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_LO_DATA_REG_DATA          , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA       );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN      , 32  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_DATA_LEN   );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS       , 32  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS    );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN   , 10  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_ADDRESS_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK     , 42  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK  );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9   , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_LAST_BANK_VALID );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN  , 52  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_WRITE_ON_RUN );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_LO_DATA_REG_RUNNING       , 53  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_RUNNING    );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS  , 54  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10  , SH_UNT_XBUS_PERV, SH_ACS_SCOM_RO  ,
+           SH_FLD_HOLD_ADDRESS_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_STORE_ON_TRIG_MODE );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22  , SH_UNT_XBUS_PERV,
+           SH_ACS_SCOM     , SH_FLD_STORE_ON_TRIG_MODE_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_CMP_MSK_LT_B_TO_63 );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64  , SH_UNT_XBUS_PERV,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_TO_63_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0   , SH_UNT_XBUS_PERV,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87 );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24  , SH_UNT_XBUS_PERV,
+           SH_ACS_SCOM     , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA  , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA   );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNA_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB  , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB   );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNB_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC  , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC   );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERNC_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND  , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERND   );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_PATTERND_LEN );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA     , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKA      );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKA_LEN  );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB     , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKB      );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKB_LEN  );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC     , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKC      );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKC_LEN  );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD     , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKD      );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MASKD_LEN  );
+
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_DISABLE_COMPRESSION );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1   , SH_UNT_XBUS_PERV,
+           SH_ACS_SCOM     , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHA_MUXSEL_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHB_MUXSEL_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHC_MUXSEL_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCHD_MUXSEL_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_OR_MASK_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_AND_MASK_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_OR_MASK_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_AND_MASK_LEN );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG0_NOT_MODE );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_TRIG1_NOT_MODE );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE );
+REG64_FLD( XBUS_PERV_TCXB_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_MATCH_NOT_MODE_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX0_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN             , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_PRE_EN );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN_LEN         , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_PRE_EN_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL            , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_PRE_SEL );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL_LEN        , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_PRE_SEL_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN             , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_PRE_EN );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN_LEN         , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_PRE_EN_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL            , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_PRE_SEL );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL_LEN        , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_PRE_SEL_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MARGINPU_EN );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN_LEN    , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MARGINPU_EN_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN        , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MARGINPD_EN );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN_LEN    , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MARGINPD_EN_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MARGINPU_EN );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN_LEN    , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MARGINPU_EN_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN        , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MARGINPD_EN );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN_LEN    , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MARGINPD_EN_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MARGINPU_SEL );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL_LEN        , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MARGINPU_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL            , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MARGINPD_SEL );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL_LEN        , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MARGINPD_SEL_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN            , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MAIN_EN );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN_LEN        , 13  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MAIN_EN_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN            , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MAIN_EN );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN_LEN        , 13  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MAIN_EN_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_MODE1_EO_PG_PSAVE_WAKEUP_LANE0_ENABLE , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_WAKEUP_LANE0_ENABLE );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_MODE1_EO_PG_PSAVE_FENCE_ENABLE      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_FENCE_ENABLE );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_MODE );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE_LEN       , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_MODE1_EO_PG_FFE_BOOST_EN            , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FFE_BOOST_EN );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_MODE1_EO_PG_SEG_TEST_LEAKAGE_CTRL   , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_LEAKAGE_CTRL );
+
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_0              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_0   );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_1              , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_1   );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_2              , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_2   );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_3              , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_3   );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_4              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_4   );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_5              , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_5   );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_6              , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_6   );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_SPARE_MODE_PG_CTL_SM_7              , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_7   );
+
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ERR            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_BIST_ERR );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ACTIVITY_DET   , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_BIST_ACTIVITY_DET );
+
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_STAT1_E_PG_SEG_TEST_CLK_STATUS      , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_CLK_STATUS );
+REG64_FLD( XBUS_1_TX0_TX_CTLSM_STAT1_E_PG_SEG_TEST_CLK_STATUS_LEN  , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_CLK_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_PULSE_WIDTH );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH_LEN      , 9   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_PULSE_WIDTH_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_FINE_SEL );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL_LEN    , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_FINE_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL      , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_COARSE_SEL );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL_LEN  , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_COARSE_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_BER_SEL );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL_LEN     , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_BER_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_ENABLE            , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_ENABLE );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL2_EO_PG_ERR_INJ_CLOCK_ENABLE      , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_CLOCK_ENABLE );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL2_E_PG_IORESET                    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_MODE           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_SLS_MODE );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_ALL_CMD        , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_SLS_ALL_CMD );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_RECAL          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_SLS_RECAL );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_CMD            , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_SLS_CMD );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_CMD_LEN        , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_SLS_CMD_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_FINE_SEL );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL_LEN    , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_FINE_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL      , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_COARSE_SEL );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL_LEN  , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_COARSE_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_BER_SEL );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL_LEN     , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_BER_SEL_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_DAC_CNTL );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_DAC_CNTL_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL8_EO_PG_TDR_PHASE_SEL             , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_PHASE_SEL );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_PULSE_OFFSET );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET_LEN      , 14  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_PULSE_OFFSET_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG1_EO_PG_DRV_CLK_PATTERN_GCRMSG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DRV_CLK_PATTERN_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG1_EO_PG_DRV_CLK_PATTERN_GCRMSG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DRV_CLK_PATTERN_GCRMSG_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DRV_DATA_PATTERN_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DRV_DATA_PATTERN_GCRMSG_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG3_E_PG_SND_SLS_CMD_GCRMSG        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SND_SLS_CMD_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG3_E_PG_DYN_RECAL_TSR_IGNORE_GCRMSG , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_TSR_IGNORE_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG3_E_PG_SLS_CMD_GCRMSG            , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_CMD_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG3_E_PG_SLS_CMD_GCRMSG_LEN        , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_CMD_GCRMSG_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG3_E_PG_SND_SLS_CMD_PREV_GCRMSG   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SND_SLS_CMD_PREV_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG3_E_PG_SND_SLS_USING_REG_SCRAMBLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SND_SLS_USING_REG_SCRAMBLE );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG4_E_PG_SLS_LANE_GCRMSG           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_LANE_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG4_E_PG_SLS_LANE_GCRMSG_LEN       , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_LANE_GCRMSG_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG4_E_PG_SLS_LANE_VAL_GCRMSG       , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_LANE_VAL_GCRMSG );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG5_E_PG_SLS_LANE_SHDW_GCRMSG      , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_LANE_SHDW_GCRMSG );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SHDW_REQ_GCRMSG , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_MV_SLS_SHDW_REQ_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SHDW_RPR_REQ_GCRMSG , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_MV_SLS_SHDW_RPR_REQ_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_REQ_GCRMSG , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_MV_SLS_UNSHDW_REQ_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_RPR_REQ_GCRMSG , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_MV_SLS_RPR_REQ_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SLS_LANE_SEL_LG_GCRMSG    , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_LANE_SEL_LG_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SLS_LANE_UNSEL_LG_GCRMSG  , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_LANE_UNSEL_LG_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SPR_LNS_PDWN_LITE_GCRMSG  , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPR_LNS_PDWN_LITE_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG6_E_PG_SLV_LGL_RPR_REQ_GCRMSG    , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_LGL_RPR_REQ_GCRMSG );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG7_E_PG_WT_EN_ALL_CLK_SEGS_GCRMSG , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_EN_ALL_CLK_SEGS_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_CNTLG7_E_PG_WT_EN_ALL_DATA_SEGS_GCRMSG , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_EN_ALL_DATA_SEGS_GCRMSG );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_EO_PG_CLKDIST_PDWN              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLKDIST_PDWN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_EO_PG_BIST_EN                   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EN    );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_EO_PG_EXBIST_MODE               , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_EXBIST_MODE );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_EO_PG_MAX_BAD_LANES             , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MAX_BAD_LANES );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_EO_PG_MAX_BAD_LANES_LEN         , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MAX_BAD_LANES_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_EO_PG_MSBSWAP                   , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MSBSWAP    );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_EO_PG_PDWN_LITE_DISABLE         , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_DISABLE );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_EO_PG_WT_PATTERN_LENGTH         , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_PATTERN_LENGTH );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_EO_PG_WT_PATTERN_LENGTH_LEN     , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_PATTERN_LENGTH_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_EO_PG_DESKEW_RATE               , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_RATE );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_E_PG_CLK_INVERT                 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_INVERT );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_E_PG_CLK_QUIESCE                , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_QUIESCE );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_E_PG_CLK_QUIESCE_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_E_PG_CLK_RATE                   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_RATE   );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_E_PG_CLK_RATE_LEN               , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_RATE_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_E_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_E_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_E_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE1_E_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE2_EO_PG_SLS_SCRAMBLE_MODE         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE2_EO_PG_SLS_SCRAMBLE_MODE_LEN     , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_CLK_DISABLE    , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE2_EO_PG_CLK_RUN_COUNT             , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_RUN_COUNT );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_SEL            , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_SEL_LEN        , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE2_EO_PG_CLK_HALF_WIDTH_MODE       , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE2_EO_PG_BUS_WIDTH                 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BUS_WIDTH  );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE2_EO_PG_BUS_WIDTH_LEN             , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BUS_WIDTH_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE2_E_PG_LANE_DISABLED_VEC_0_15     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_0_15 );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE2_E_PG_LANE_DISABLED_VEC_0_15_LEN , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE3_E_PG_LANE_DISABLED_VEC_16_23    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_16_23 );
+REG64_FLD( XBUS_1_TX0_TX_CTL_MODE3_E_PG_LANE_DISABLED_VEC_16_23_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_16_23_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE1_GCRMSG          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE1_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE1_GCRMSG_LEN      , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE1_GCRMSG_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE2_GCRMSG          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE2_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE2_GCRMSG_LEN      , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE2_GCRMSG_LEN );
+REG64_FLD( XBUS_1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE_CODE_GCRMSG      , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE_CODE_GCRMSG );
+REG64_FLD( XBUS_1_TX0_TX_CTL_STATG1_E_PG_BAD_LANE_CODE_GCRMSG_LEN  , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE_CODE_GCRMSG_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_FIR_ERROR_INJECT_PG_ERR_INJ               , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_TX0_TX_FIR_ERROR_INJECT_PG_ERR_INJ_LEN           , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_FIR_MASK_PG_ERRS                          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_TX0_TX_FIR_MASK_PG_ERRS_LEN                      , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+REG64_FLD( XBUS_1_TX0_TX_FIR_MASK_PG_PL_ERR                        , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PL_ERR     );
+
+REG64_FLD( XBUS_1_TX0_TX_FIR_RESET_PG_CLR_PAR_ERRS                 , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLR_PAR_ERRS );
+REG64_FLD( XBUS_1_TX0_TX_FIR_RESET_PG_RESET                        , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET      );
+
+REG64_FLD( XBUS_1_TX0_TX_ID1_PG_BUS_ID                             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ID     );
+REG64_FLD( XBUS_1_TX0_TX_ID1_PG_BUS_ID_LEN                         , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ID_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_ID2_PG_START_LANE_ID                      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_LANE_ID );
+REG64_FLD( XBUS_1_TX0_TX_ID2_PG_START_LANE_ID_LEN                  , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_LANE_ID_LEN );
+REG64_FLD( XBUS_1_TX0_TX_ID2_PG_END_LANE_ID                        , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_END_LANE_ID );
+REG64_FLD( XBUS_1_TX0_TX_ID2_PG_END_LANE_ID_LEN                    , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_END_LANE_ID_LEN );
+
+REG64_FLD( XBUS_1_TX0_TX_SPARE_MODE_PG_0                           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_TX0_TX_SPARE_MODE_PG_1                           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_TX0_TX_SPARE_MODE_PG_2                           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_TX0_TX_SPARE_MODE_PG_3                           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_TX0_TX_SPARE_MODE_PG_4                           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_TX0_TX_SPARE_MODE_PG_5                           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_TX0_TX_SPARE_MODE_PG_6                           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_TX0_TX_SPARE_MODE_PG_7                           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+REG64_FLD( XBUS_1_TX0_TX_SPARE_MODE_PG_8_9                         , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_8_9        );
+REG64_FLD( XBUS_1_TX0_TX_SPARE_MODE_PG_8_9_LEN                     , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_8_9_LEN    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS0_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS1_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS2_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE0_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE1_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE2_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE3_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SEED_VALUE_0_15 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE1_E_PL_PRBS_SEED_VALUE_0_15_LEN , 16  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22 , 48  , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_BIT_MODE2_E_PL_PRBS_SEED_VALUE_16_22_LEN , 7   , SH_UNT_XBUS_1   ,
+           SH_ACS_SCOM     , SH_FLD_PRBS_SEED_VALUE_16_22_LEN );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_CNTL3_EO_PL_TDR_ENABLE    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_FIR_ERROR_INJECT_PL_ERR_INJ , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_FIR_MASK_PL_ERRS          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_PDWN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_PDWN  );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_INVERT      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_INVERT );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_QUIESCE     , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_QUIESCE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_LANE_SCRAMBLE_DISABLE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_SCRAMBLE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_A_ENABLE , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_ERR_INJ_B_ENABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_ENABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_PSAVE_MODE_DISABLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_MODE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_0     , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_0 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_1     , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_1 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_2     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_2 );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE1_PL_SPARE_MODE_3     , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPARE_MODE_3 );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_L2U_DLY     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_L2U_DLY_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_L2U_DLY_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_NEXT_CAL_LANE_SEL , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NEXT_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_PRBS_SCRAMBLE_MODE , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_PRBS_SCRAMBLE_MODE_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PRBS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_CLK_DISABLE , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_RXCAL            , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RXCAL      );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL       , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_UNLOAD_SEL_LEN   , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_PDWN_LITE        , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE  );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_CAL_LANE_SEL     , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CAL_LANE_SEL );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_MODE2_PL_FIFO_HALF_WIDTH_MODE , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FIFO_HALF_WIDTH_MODE );
+
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_LANE_BIST_ERR    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_LANE_BIST_ACTVITY_DET , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_BIST_ACTVITY_DET );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS );
+REG64_FLD( XBUS_1_TX1_TXPACKS3_SLICE4_TX_STAT1_PL_SEG_TEST_STATUS_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN             , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_PRE_EN );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_EN_LEN         , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_PRE_EN_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL            , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_PRE_SEL );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL1_EO_PG_PSEG_PRE_SEL_LEN        , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_PRE_SEL_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN             , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_PRE_EN );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_EN_LEN         , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_PRE_EN_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL            , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_PRE_SEL );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL2_EO_PG_NSEG_PRE_SEL_LEN        , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_PRE_SEL_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MARGINPU_EN );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPU_EN_LEN    , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MARGINPU_EN_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN        , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MARGINPD_EN );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL3_EO_PG_PSEG_MARGINPD_EN_LEN    , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MARGINPD_EN_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MARGINPU_EN );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPU_EN_LEN    , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MARGINPU_EN_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN        , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MARGINPD_EN );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL4_EO_PG_NSEG_MARGINPD_EN_LEN    , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MARGINPD_EN_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MARGINPU_SEL );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL5_EO_PG_MARGINPU_SEL_LEN        , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MARGINPU_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL            , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MARGINPD_SEL );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL5_EO_PG_MARGINPD_SEL_LEN        , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MARGINPD_SEL_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN            , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MAIN_EN );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL6_EO_PG_PSEG_MAIN_EN_LEN        , 13  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSEG_MAIN_EN_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN            , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MAIN_EN );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_CNTL7_EO_PG_NSEG_MAIN_EN_LEN        , 13  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_NSEG_MAIN_EN_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_MODE1_EO_PG_PSAVE_WAKEUP_LANE0_ENABLE , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_WAKEUP_LANE0_ENABLE );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_MODE1_EO_PG_PSAVE_FENCE_ENABLE      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PSAVE_FENCE_ENABLE );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_MODE );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_MODE1_EO_PG_SEG_TEST_MODE_LEN       , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_MODE1_EO_PG_FFE_BOOST_EN            , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_FFE_BOOST_EN );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_MODE1_EO_PG_SEG_TEST_LEAKAGE_CTRL   , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_LEAKAGE_CTRL );
+
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_0              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_0   );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_1              , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_1   );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_2              , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_2   );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_3              , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_3   );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_4              , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_4   );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_5              , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_5   );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_6              , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_6   );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_SPARE_MODE_PG_CTL_SM_7              , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CTL_SM_7   );
+
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ERR            , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_BIST_ERR );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_STAT1_EO_PG_CLK_BIST_ACTIVITY_DET   , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_BIST_ACTIVITY_DET );
+
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_STAT1_E_PG_SEG_TEST_CLK_STATUS      , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_CLK_STATUS );
+REG64_FLD( XBUS_1_TX1_TX_CTLSM_STAT1_E_PG_SEG_TEST_CLK_STATUS_LEN  , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SEG_TEST_CLK_STATUS_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_PULSE_WIDTH );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL10_EO_PG_TDR_PULSE_WIDTH_LEN      , 9   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_PULSE_WIDTH_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_FINE_SEL );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_FINE_SEL_LEN    , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_FINE_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL      , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_COARSE_SEL );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_COARSE_SEL_LEN  , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_COARSE_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_BER_SEL );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_A_BER_SEL_LEN     , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_A_BER_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_ENABLE            , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_ENABLE );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL2_EO_PG_ERR_INJ_CLOCK_ENABLE      , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_CLOCK_ENABLE );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL2_E_PG_IORESET                    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_IORESET    );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_MODE           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_SLS_MODE );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_ALL_CMD        , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_SLS_ALL_CMD );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_RECAL          , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_SLS_RECAL );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_CMD            , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_SLS_CMD );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL2_E_PG_ERR_INJ_SLS_CMD_LEN        , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_SLS_CMD_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_FINE_SEL );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_FINE_SEL_LEN    , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_FINE_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL      , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_COARSE_SEL );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_COARSE_SEL_LEN  , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_COARSE_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL         , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_BER_SEL );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL3_EO_PG_ERR_INJ_B_BER_SEL_LEN     , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_B_BER_SEL_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_DAC_CNTL );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL8_EO_PG_TDR_DAC_CNTL_LEN          , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_DAC_CNTL_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL8_EO_PG_TDR_PHASE_SEL             , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_PHASE_SEL );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_PULSE_OFFSET );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTL9_EO_PG_TDR_PULSE_OFFSET_LEN      , 14  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_TDR_PULSE_OFFSET_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG1_EO_PG_DRV_CLK_PATTERN_GCRMSG   , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DRV_CLK_PATTERN_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG1_EO_PG_DRV_CLK_PATTERN_GCRMSG_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DRV_CLK_PATTERN_GCRMSG_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG  , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DRV_DATA_PATTERN_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG1_EO_PG_DRV_DATA_PATTERN_GCRMSG_LEN , 4   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DRV_DATA_PATTERN_GCRMSG_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG3_E_PG_SND_SLS_CMD_GCRMSG        , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SND_SLS_CMD_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG3_E_PG_DYN_RECAL_TSR_IGNORE_GCRMSG , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_TSR_IGNORE_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG3_E_PG_SLS_CMD_GCRMSG            , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_CMD_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG3_E_PG_SLS_CMD_GCRMSG_LEN        , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_CMD_GCRMSG_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG3_E_PG_SND_SLS_CMD_PREV_GCRMSG   , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SND_SLS_CMD_PREV_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG3_E_PG_SND_SLS_USING_REG_SCRAMBLE , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SND_SLS_USING_REG_SCRAMBLE );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG4_E_PG_SLS_LANE_GCRMSG           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_LANE_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG4_E_PG_SLS_LANE_GCRMSG_LEN       , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_LANE_GCRMSG_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG4_E_PG_SLS_LANE_VAL_GCRMSG       , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_LANE_VAL_GCRMSG );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG5_E_PG_SLS_LANE_SHDW_GCRMSG      , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_LANE_SHDW_GCRMSG );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SHDW_REQ_GCRMSG , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_MV_SLS_SHDW_REQ_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_SHDW_RPR_REQ_GCRMSG , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_MV_SLS_SHDW_RPR_REQ_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_REQ_GCRMSG , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_MV_SLS_UNSHDW_REQ_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SLV_MV_SLS_RPR_REQ_GCRMSG , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_MV_SLS_RPR_REQ_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SLS_LANE_SEL_LG_GCRMSG    , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_LANE_SEL_LG_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SLS_LANE_UNSEL_LG_GCRMSG  , 61  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_LANE_UNSEL_LG_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SPR_LNS_PDWN_LITE_GCRMSG  , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SPR_LNS_PDWN_LITE_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG6_E_PG_SLV_LGL_RPR_REQ_GCRMSG    , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLV_LGL_RPR_REQ_GCRMSG );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG7_E_PG_WT_EN_ALL_CLK_SEGS_GCRMSG , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_EN_ALL_CLK_SEGS_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_CNTLG7_E_PG_WT_EN_ALL_DATA_SEGS_GCRMSG , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_EN_ALL_DATA_SEGS_GCRMSG );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_EO_PG_CLKDIST_PDWN              , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLKDIST_PDWN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_EO_PG_BIST_EN                   , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BIST_EN    );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_EO_PG_EXBIST_MODE               , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_EXBIST_MODE );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_EO_PG_MAX_BAD_LANES             , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MAX_BAD_LANES );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_EO_PG_MAX_BAD_LANES_LEN         , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MAX_BAD_LANES_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_EO_PG_MSBSWAP                   , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_MSBSWAP    );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_EO_PG_PDWN_LITE_DISABLE         , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PDWN_LITE_DISABLE );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_EO_PG_WT_PATTERN_LENGTH         , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_PATTERN_LENGTH );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_EO_PG_WT_PATTERN_LENGTH_LEN     , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_WT_PATTERN_LENGTH_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_EO_PG_DESKEW_RATE               , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DESKEW_RATE );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_E_PG_CLK_INVERT                 , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_INVERT );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_E_PG_CLK_QUIESCE                , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_QUIESCE );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_E_PG_CLK_QUIESCE_LEN            , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_QUIESCE_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_E_PG_CLK_RATE                   , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_RATE   );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_E_PG_CLK_RATE_LEN               , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_RATE_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_E_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_E_PG_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_E_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE1_E_PG_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE2_EO_PG_SLS_SCRAMBLE_MODE         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_SCRAMBLE_MODE );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE2_EO_PG_SLS_SCRAMBLE_MODE_LEN     , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_SLS_SCRAMBLE_MODE_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_CLK_DISABLE    , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_UNLOAD_CLK_DISABLE );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE2_EO_PG_CLK_RUN_COUNT             , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_RUN_COUNT );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_SEL            , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_UNLOAD_SEL );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE2_EO_PG_CLK_UNLOAD_SEL_LEN        , 3   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_UNLOAD_SEL_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE2_EO_PG_CLK_HALF_WIDTH_MODE       , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLK_HALF_WIDTH_MODE );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE2_EO_PG_BUS_WIDTH                 , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BUS_WIDTH  );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE2_EO_PG_BUS_WIDTH_LEN             , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BUS_WIDTH_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE2_E_PG_LANE_DISABLED_VEC_0_15     , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_0_15 );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE2_E_PG_LANE_DISABLED_VEC_0_15_LEN , 16  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_0_15_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE3_E_PG_LANE_DISABLED_VEC_16_23    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_16_23 );
+REG64_FLD( XBUS_1_TX1_TX_CTL_MODE3_E_PG_LANE_DISABLED_VEC_16_23_LEN , 8   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_LANE_DISABLED_VEC_16_23_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE1_GCRMSG          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE1_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE1_GCRMSG_LEN      , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE1_GCRMSG_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE2_GCRMSG          , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE2_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE2_GCRMSG_LEN      , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE2_GCRMSG_LEN );
+REG64_FLD( XBUS_1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE_CODE_GCRMSG      , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE_CODE_GCRMSG );
+REG64_FLD( XBUS_1_TX1_TX_CTL_STATG1_E_PG_BAD_LANE_CODE_GCRMSG_LEN  , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BAD_LANE_CODE_GCRMSG_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_FIR_ERROR_INJECT_PG_ERR_INJ               , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ    );
+REG64_FLD( XBUS_1_TX1_TX_FIR_ERROR_INJECT_PG_ERR_INJ_LEN           , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERR_INJ_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_FIR_MASK_PG_ERRS                          , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS       );
+REG64_FLD( XBUS_1_TX1_TX_FIR_MASK_PG_ERRS_LEN                      , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ERRS_LEN   );
+REG64_FLD( XBUS_1_TX1_TX_FIR_MASK_PG_PL_ERR                        , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_PL_ERR     );
+
+REG64_FLD( XBUS_1_TX1_TX_FIR_RESET_PG_CLR_PAR_ERRS                 , 62  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_CLR_PAR_ERRS );
+REG64_FLD( XBUS_1_TX1_TX_FIR_RESET_PG_RESET                        , 63  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_RESET      );
+
+REG64_FLD( XBUS_1_TX1_TX_ID1_PG_BUS_ID                             , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ID     );
+REG64_FLD( XBUS_1_TX1_TX_ID1_PG_BUS_ID_LEN                         , 6   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_BUS_ID_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_ID2_PG_START_LANE_ID                      , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_LANE_ID );
+REG64_FLD( XBUS_1_TX1_TX_ID2_PG_START_LANE_ID_LEN                  , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_START_LANE_ID_LEN );
+REG64_FLD( XBUS_1_TX1_TX_ID2_PG_END_LANE_ID                        , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_END_LANE_ID );
+REG64_FLD( XBUS_1_TX1_TX_ID2_PG_END_LANE_ID_LEN                    , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_END_LANE_ID_LEN );
+
+REG64_FLD( XBUS_1_TX1_TX_SPARE_MODE_PG_0                           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_0          );
+REG64_FLD( XBUS_1_TX1_TX_SPARE_MODE_PG_1                           , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_1          );
+REG64_FLD( XBUS_1_TX1_TX_SPARE_MODE_PG_2                           , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_2          );
+REG64_FLD( XBUS_1_TX1_TX_SPARE_MODE_PG_3                           , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_3          );
+REG64_FLD( XBUS_1_TX1_TX_SPARE_MODE_PG_4                           , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_4          );
+REG64_FLD( XBUS_1_TX1_TX_SPARE_MODE_PG_5                           , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_5          );
+REG64_FLD( XBUS_1_TX1_TX_SPARE_MODE_PG_6                           , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_6          );
+REG64_FLD( XBUS_1_TX1_TX_SPARE_MODE_PG_7                           , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_7          );
+REG64_FLD( XBUS_1_TX1_TX_SPARE_MODE_PG_8_9                         , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_8_9        );
+REG64_FLD( XBUS_1_TX1_TX_SPARE_MODE_PG_8_9_LEN                     , 2   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_8_9_LEN    );
+
+REG64_FLD( XBUS_1_TX_IMPCAL_NVAL_PB_ZCAL_N                         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_N     );
+REG64_FLD( XBUS_1_TX_IMPCAL_NVAL_PB_ZCAL_N_LEN                     , 9   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_N_LEN );
+
+REG64_FLD( XBUS_1_TX_IMPCAL_PVAL_PB_ZCAL_P                         , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_P     );
+REG64_FLD( XBUS_1_TX_IMPCAL_PVAL_PB_ZCAL_P_LEN                     , 9   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_P_LEN );
+
+REG64_FLD( XBUS_1_TX_IMPCAL_P_4X_PB_ZCAL                           , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL       );
+REG64_FLD( XBUS_1_TX_IMPCAL_P_4X_PB_ZCAL_LEN                       , 5   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_LEN   );
+
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_EN                    , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SWO_EN );
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CAL_SEGS              , 49  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SWO_CAL_SEGS );
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_INV               , 50  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SWO_CMP_INV );
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_OFFSET            , 51  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SWO_CMP_OFFSET );
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_CMP_RESET             , 52  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SWO_CMP_RESET );
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_POWERDOWN             , 53  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SWO_POWERDOWN );
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO1_PB_ZCAL_SWO_TCOIL                 , 54  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SWO_TCOIL );
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO1_PB_ZCAL_RANGE_CHECK               , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_RANGE_CHECK );
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO1_PB_ZCAL_CYA_DATA_INV              , 56  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_CYA_DATA_INV );
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_2R               , 57  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_TEST_OVR_2R );
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_1R               , 58  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_TEST_OVR_1R );
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO1_PB_ZCAL_TEST_OVR_4X_SEG           , 59  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_TEST_OVR_4X_SEG );
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO1_PB_ZCAL_TEST_CLK_DIV              , 60  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_TEST_CLK_DIV );
+
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO2_PB_ZCAL_SM_MIN_VAL                , 48  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SM_MIN_VAL );
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO2_PB_ZCAL_SM_MIN_VAL_LEN            , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SM_MIN_VAL_LEN );
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO2_PB_ZCAL_SM_MAX_VAL                , 55  , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SM_MAX_VAL );
+REG64_FLD( XBUS_1_TX_IMPCAL_SWO2_PB_ZCAL_SM_MAX_VAL_LEN            , 7   , SH_UNT_XBUS_1   , SH_ACS_SCOM     ,
+           SH_FLD_ZCAL_SM_MAX_VAL_LEN );
+
+REG64_FLD( XBUS_PERV_XTRA_TRACE_MODE_DATA                          , 0   , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_DATA       );
+REG64_FLD( XBUS_PERV_XTRA_TRACE_MODE_DATA_LEN                      , 38  , SH_UNT_XBUS_PERV, SH_ACS_SCOM     ,
+           SH_FLD_DATA_LEN   );
+
+#endif
+
diff --git a/src/import/chips/p9/common/include/p9_xbus_scom_addresses_fld_fixes.H b/src/import/chips/p9/common/include/p9_xbus_scom_addresses_fld_fixes.H
new file mode 100644
index 00000000..8d352fb9
--- /dev/null
+++ b/src/import/chips/p9/common/include/p9_xbus_scom_addresses_fld_fixes.H
@@ -0,0 +1,49 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/common/include/p9_xbus_scom_addresses_fld_fixes.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file xbus_scom_addresses_fld_fixes.H
+/// @brief The *scom_addresses_fld.H files are generated form figtree,
+///        but the figree can be wrong.  This file is included in
+///        *_scom_addresses_fld.H and allows incorrect constants to be
+///        fixed manually.
+///
+// *HWP HWP Owner: Ben Gass <bgass@us.ibm.com>
+// *HWP FW Owner: ? <?>
+// *HWP Team: SAO
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE
+
+#ifndef __P9_XBUS_SCOM_ADDRESSES_FLD_FIXES_H
+#define __P9_XBUS_SCOM_ADDRESSES_FLD_FIXES_H
+
+//Example
+//Copy the whole line from the *scom_addresses_fld.H file.  Then add FIX in front of REG
+//and add another paramter that is the new value you want.
+//
+//FIXREG64_FLD( PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE, 24, SH_UNT, SH_ACS_SCOM, SH_FLD_FBC_WITH_TM_QUIESCE,
+//              12);
+
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/cache/Makefile b/src/import/chips/p9/procedures/hwp/cache/Makefile
new file mode 100644
index 00000000..a95923ab
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/Makefile
@@ -0,0 +1,55 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/hwp/cache/Makefile $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+# This Makefile compiles all of the cache hardware procedure code. See the
+# "cachehcdfiles.mk" file in this directory.
+
+#all generated files from this makefile will end up in obj/cache
+export SUB_OBJDIR = /cache
+
+include img_defs.mk
+include cachehcdfiles.mk
+
+GCC-CFLAGS += -mlongcall
+
+OBJS := $(addprefix $(OBJDIR)/, $(CACHE_OBJECTS))
+
+libcache.a: cache
+	$(AR) crs $(OBJDIR)/libcache.a $(OBJDIR)/*.o
+
+.PHONY: clean cache
+cache: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+clean:
+	rm -fr $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d)
+endif
diff --git a/src/import/chips/p9/procedures/hwp/cache/cachehcdfiles.mk b/src/import/chips/p9/procedures/hwp/cache/cachehcdfiles.mk
new file mode 100644
index 00000000..f8ae915e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/cachehcdfiles.mk
@@ -0,0 +1,56 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/hwp/cache/cachehcdfiles.mk $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file cachehcdfiles.mk
+#
+#  @brief mk for including cache hcode object files
+#
+##########################################################################
+# Object Files
+##########################################################################
+
+CACHE-CPP-SOURCES += p9_hcd_cache_arrayinit.C
+CACHE-CPP-SOURCES += p9_hcd_cache_chiplet_init.C
+CACHE-CPP-SOURCES += p9_hcd_cache_chiplet_reset.C
+CACHE-CPP-SOURCES += p9_hcd_cache_dpll_setup.C
+CACHE-CPP-SOURCES += p9_hcd_cache_gptr_time_initf.C
+CACHE-CPP-SOURCES += p9_hcd_cache_initf.C
+CACHE-CPP-SOURCES += p9_hcd_cache_occ_runtime_scom.C
+CACHE-CPP-SOURCES += p9_hcd_cache_poweron.C
+CACHE-CPP-SOURCES += p9_hcd_cache_ras_runtime_scom.C
+CACHE-CPP-SOURCES += p9_hcd_cache_repair_initf.C
+CACHE-CPP-SOURCES += p9_hcd_cache_runinit.C
+CACHE-CPP-SOURCES += p9_hcd_cache_scomcust.C
+CACHE-CPP-SOURCES += p9_hcd_cache_scominit.C
+CACHE-CPP-SOURCES += p9_hcd_cache_startclocks.C
+CACHE-CPP-SOURCES += p9_hcd_cache_chiplet_l3_dcc_setup.C
+CACHE-CPP-SOURCES += p9_hcd_cache_dpll_initf.C
+
+CACHE-C-SOURCES   +=
+CACHE-S-SOURCES   +=
+
+CACHE_OBJECTS     += $(CACHE-CPP-SOURCES:.C=.o)
+CACHE_OBJECTS     += $(CACHE-C-SOURCES:.c=.o)
+CACHE_OBJECTS     += $(CACHE-S-SOURCES:.S=.o)
+
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache.H
new file mode 100644
index 00000000..d73007e7
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache.H
@@ -0,0 +1,53 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache.H $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_hcd_cache.H
+/// @brief Cache Chiplet Procedure Includes
+///
+/// *HWP HWP Owner   : David Du       <daviddu@us.ibm.com>
+/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
+/// *HWP Team        : PM
+/// *HWP Consumed by : SBE:SGPE
+/// *HWP Level       : 2
+///
+
+#ifndef __P9_HCD_CACHE_H__
+#define __P9_HCD_CACHE_H__
+
+#include <p9_hcd_cache_arrayinit.H>
+#include <p9_hcd_cache_chiplet_init.H>
+#include <p9_hcd_cache_chiplet_reset.H>
+#include <p9_hcd_cache_dpll_setup.H>
+#include <p9_hcd_cache_gptr_time_initf.H>
+#include <p9_hcd_cache_initf.H>
+#include <p9_hcd_cache_occ_runtime_scom.H>
+#include <p9_hcd_cache_poweron.H>
+#include <p9_hcd_cache_ras_runtime_scom.H>
+#include <p9_hcd_cache_repair_initf.H>
+#include <p9_hcd_cache_scomcust.H>
+#include <p9_hcd_cache_scominit.H>
+#include <p9_hcd_cache_startclocks.H>
+
+#endif  // __P9_HCD_CACHE_H__
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C
new file mode 100644
index 00000000..3b2887c4
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C
@@ -0,0 +1,147 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_arrayinit.C
+/// @brief EX Initialize arrays
+///
+/// Procedure Summary:
+///   Use ABIST engine to zero out all arrays
+///   Upon completion, scan0 flush all rings
+///     except Vital, Repair, GPTR, TIME and DPLL
+
+// *HWP HWP Owner          : David Du      <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still    <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+
+#include <p9_quad_scom_addresses.H>
+#include <p9_misc_scom_addresses.H>
+#include <p9_perv_sbe_cmn.H>
+#include <p9_hcd_common.H>
+#include "p9_hcd_cache_arrayinit.H"
+
+//-----------------------------------------------------------------------------
+// Constant Definitions
+//-----------------------------------------------------------------------------
+
+enum P9_HCD_CACHE_ARRAYINIT_Private_Constants
+{
+    LOOP_COUNTER = 0x0000000000042FFF,
+    SELECT_SRAM = 0x1,
+    SELECT_EDRAM = 0x0,
+    START_ABIST_MATCH_VALUE = 0x0000000F00000000
+};
+
+//-----------------------------------------------------------------------------
+// Procedure: Initialize Cache Arrays
+//-----------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_cache_arrayinit(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+{
+    FAPI_INF(">>p9_hcd_cache_arrayinit");
+    fapi2::buffer<uint64_t>                     l_data64;
+    uint16_t                                    l_region_array;
+    uint16_t                                    l_region_scan0;
+    uint8_t                                     l_attr_chip_unit_pos = 0;
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
+        i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+    fapi2::Target<fapi2::TARGET_TYPE_PERV>      l_perv =
+        i_target.getParent<fapi2::TARGET_TYPE_PERV>();
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv,
+                           l_attr_chip_unit_pos));
+    l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_EQ_POS_OFFSET;
+
+    FAPI_TRY(getScom(l_chip, PU_OCB_OCI_QCSR_SCOM, l_data64));
+    FAPI_DBG("Working on cache[%d] good EXs in QCSR[%016llX]",
+             l_attr_chip_unit_pos, l_data64);
+
+    l_region_array = p9hcd::SCAN0_REGION_ALL_BUT_EX_DPLL;
+    l_region_scan0 = p9hcd::SCAN0_REGION_ALL_BUT_EX_ANEP_DPLL;
+
+    if (l_data64 & BIT64(l_attr_chip_unit_pos << 1))
+    {
+        l_region_array |= p9hcd::SCAN0_REGION_EX0_L2_L3_REFR;
+        l_region_scan0 |= p9hcd::SCAN0_REGION_EX0_L2_L3_REFR;
+    }
+
+    if (l_data64 & BIT64((l_attr_chip_unit_pos << 1) + 1))
+    {
+        l_region_array |= p9hcd::SCAN0_REGION_EX1_L2_L3_REFR;
+        l_region_scan0 |= p9hcd::SCAN0_REGION_EX1_L2_L3_REFR;
+    }
+
+    /// @todo add DD1 attribute control
+    FAPI_DBG("DD1 only: set sdis_n(flushing LCBES condition workaround");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CONF0_OR, MASK_SET(34)));
+
+#ifndef P9_HCD_STOP_SKIP_ARRAYINIT
+
+    FAPI_DBG("Arrayinit all regions except vital/DPLL");
+    FAPI_TRY(p9_perv_sbe_cmn_array_init_module(l_perv,
+             l_region_array,
+             LOOP_COUNTER,
+             SELECT_SRAM,
+             SELECT_EDRAM,
+             START_ABIST_MATCH_VALUE));
+
+#endif
+
+#ifndef P9_HCD_STOP_SKIP_FLUSH
+
+    //--------------------------------------------
+    // perform scan0 module for pervasive chiplet
+    //--------------------------------------------
+    // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest
+    // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has
+    // all stumps less than 8191, the loop can be removed.
+
+    FAPI_DBG("Scan0 region:all_but_anep_dpll type:all_but_gptr_repr_time rings");
+
+    for(uint32_t l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++)
+        FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
+                                              l_region_scan0,
+                                              p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME));
+
+#endif
+
+    /// @todo add DD1 attribute control
+    FAPI_DBG("DD1 only: reset sdis_n(flushing LCBES condition workaround");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CONF0_CLEAR, MASK_SET(34)));
+
+fapi_try_exit:
+
+    FAPI_INF("<<p9_hcd_cache_arrayinit");
+    return fapi2::current_err;
+}
+
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H
new file mode 100644
index 00000000..16b97e5b
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_arrayinit.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_arrayinit.H
+/// @brief EX Initialize arrays
+///
+
+// *HWP HWP Owner          : David Du      <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still    <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CACHE_ARRAYINIT_H__
+#define __P9_HCD_CACHE_ARRAYINIT_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_cache_arrayinit_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_cache_arrayinit_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+extern "C"
+{
+
+/// @brief EX Initialize arrays
+///
+/// @param [in] i_target TARGET_TYPE_EQ target
+///
+/// @attr
+/// @attritem NONE
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_cache_arrayinit(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+
+}
+
+#endif  // __P9_HCD_CACHE_ARRAYINIT_H__
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C
new file mode 100644
index 00000000..2978337b
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C
@@ -0,0 +1,88 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_chiplet_init.C
+/// @brief Cache Flush/Initialize
+///
+/// Procedure Summary:
+///   Scan0 flush all configured chiplet rings except Vital, GPTR, TIME and DPLL
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+
+#include <p9_quad_scom_addresses.H>
+#include <p9_perv_sbe_cmn.H>
+#include <p9_hcd_common.H>
+#include "p9_hcd_cache_chiplet_init.H"
+
+//-----------------------------------------------------------------------------
+// Constant Definitions
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Procedure: Cache Flush/Initialize
+//-----------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_cache_chiplet_init(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+{
+    FAPI_INF(">>p9_hcd_cache_chiplet_init");
+    /*
+    #ifndef P9_HCD_STOP_SKIP_FLUSH
+
+        //--------------------------------------------
+        // perform scan0 module for pervasive chiplet
+        //--------------------------------------------
+        // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest
+        // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has
+        // all stumps less than 8191, the loop can be removed.
+
+        fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv =
+            i_target.getParent<fapi2::TARGET_TYPE_PERV>();
+
+        FAPI_DBG("Scan0 region:all_but_anep_dpll type:all_but_gptr_repr_time rings");
+
+        for(uint32_t l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++)
+            FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
+                                                  p9hcd::SCAN0_REGION_ALL_BUT_ANEP_DPLL,
+                                                  p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME));
+
+    fapi_try_exit:
+
+    #endif
+    */
+    FAPI_INF("<<p9_hcd_cache_chiplet_init");
+    return fapi2::current_err;
+}
+
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H
new file mode 100644
index 00000000..7b55f9ee
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_init.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_chiplet_init.H
+/// @brief Cache Flush/Initialize
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CACHE_CHIPLET_INIT_H__
+#define __P9_HCD_CACHE_CHIPLET_INIT_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_cache_chiplet_init_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_cache_chiplet_init_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+extern "C"
+{
+
+/// @brief Cache Flush/Initialize
+/// @param [in] i_target TARGET_TYPE_EQ target
+/// @return FAPI2_RC_SUCCESS if success, else error code
+    fapi2::ReturnCode
+    p9_hcd_cache_chiplet_init(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+
+}
+
+#endif  // __P9_HCD_CACHE_CHIPLET_INIT_H__
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C
new file mode 100644
index 00000000..0cf09244
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C
@@ -0,0 +1,83 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_hcd_cache_chiplet_l3_dcc_setup.C
+///
+/// @brief Setup L3 DCC, Drop L3 DCC bypass
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_hcd_cache_chiplet_l3_dcc_setup.H"
+
+#include <p9_quad_scom_addresses.H>
+#include <p9_quad_scom_addresses_fld.H>
+
+
+fapi2::ReturnCode p9_hcd_cache_chiplet_l3_dcc_setup(const
+        fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target_chiplet)
+{
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+    fapi2::buffer<uint64_t> l_data64;
+    uint8_t l_read_attr = 0;
+    FAPI_DBG("Entering ...");
+
+    FAPI_DBG("Scan eq_ana_bndy_l3dcc_bucket_26 ring");
+    FAPI_TRY(fapi2::putRing(i_target_chiplet, eq_ana_bndy_l3dcc_bucket_26, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_l3dcc_bucket_26)");
+
+    FAPI_DBG("Drop L3 DCC bypass");
+    //Setting NET_CTRL1 register value
+    l_data64.flush<1>();
+    //NET_CTRL1.CLK_DCC_BYPASS_EN = 0
+    l_data64.clearBit<C_NET_CTRL1_CLK_DCC_BYPASS_EN>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, EQ_NET_CTRL1_WAND, l_data64));
+
+    FAPI_DBG("Check if VDMs are to be enabled. If so, power them on");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_ENABLE, FAPI_SYSTEM,
+                           l_read_attr));
+
+    if( l_read_attr )
+    {
+
+        l_data64.flush<0>();
+        l_data64.setBit<0>();
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, EQ_PPM_VDMCR_OR, l_data64));
+
+    }
+
+    FAPI_DBG("Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H
new file mode 100644
index 00000000..2033f38f
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H
@@ -0,0 +1,60 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_hcd_cache_chiplet_l3_dcc_setup.H
+///
+/// @brief Setup L3 DCC, Drop L3 DCC bypass
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_HCD_CACHE_CHIPLET_L3_DCC_SETUP_H_
+#define _P9_HCD_CACHE_CHIPLET_L3_DCC_SETUP_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_hcd_cache_chiplet_l3_dcc_setup_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+/// @brief * Setup L3 DCC (scan with setpulse, scan region = ANEP), attribute dependency Nimbus/Cumulus
+/// * Drop L3 DCC bypass
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_EQ target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_hcd_cache_chiplet_l3_dcc_setup(const
+            fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target_chiplet);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C
new file mode 100644
index 00000000..8f35b4ed
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C
@@ -0,0 +1,237 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_chiplet_reset.C
+/// @brief Cache Chiplet Reset
+///
+/// Procedure Summary:
+///   Reset quad chiplet logic
+///   Clocking:
+///    - setup cache sector buffer strength,
+///      pulse mode and pulsed mode enable values
+///      (attribute dependency Nimbus/Cumulus)
+///    - Drop glsmux async reset
+///   Scan0 flush entire cache chiplet
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <p9_misc_scom_addresses.H>
+#include <p9_quad_scom_addresses.H>
+#include <p9_perv_sbe_cmn.H>
+#include <p9_hcd_common.H>
+#include "p9_hcd_cache_chiplet_reset.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions
+//------------------------------------------------------------------------------
+
+enum P9_HCD_CACHE_CHIPLET_RESET_CONSTANTS
+{
+    // (1)PCB_EP_RESET
+    // (2)CLK_ASYNC_RESET
+    // (3)PLL_TEST_EN
+    // (4)PLLRST
+    // (5)PLLBYP
+    // (11)EDIS
+    // (12)VITL_MPW1
+    // (13)VITL_MPW2
+    // (14)VITL_MPW3
+    // (16)VITL_THOLD
+    // (18)FENCE_EN
+    // (22)FUNC_CLKSEL
+    // (25)PCB_FENCE
+    // (26)LVLTRANS_FENCE
+    Q_NET_CTRL0_INIT_VECTOR = (BITS64(1, 5) | BITS64(11, 4) | BIT64(16) |
+                               BIT64(18) | BIT64(22) | BITS64(25, 2)),
+    CACHE_GLSMUX_RESET_DELAY_REF_CYCLES = 40
+};
+
+//------------------------------------------------------------------------------
+// Procedure: Cache Chiplet Reset
+//------------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_cache_chiplet_reset(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+{
+    FAPI_INF(">>p9_hcd_cache_chiplet_reset");
+    fapi2::buffer<uint64_t>                     l_data64;
+    uint16_t                                    l_region_scan0;
+    uint64_t                                    l_l2gmux_input       = 0;
+    uint64_t                                    l_l2gmux_reset       = 0;
+    uint8_t                                     l_attr_chip_unit_pos = 0;
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
+        i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+    fapi2::Target<fapi2::TARGET_TYPE_PERV>      l_perv =
+        i_target.getParent<fapi2::TARGET_TYPE_PERV>();
+    auto l_core_functional_vector =
+        i_target.getChildren<fapi2::TARGET_TYPE_CORE>
+        (fapi2::TARGET_STATE_FUNCTIONAL);
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv,
+                           l_attr_chip_unit_pos));
+    l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_EQ_POS_OFFSET;
+
+    FAPI_TRY(getScom(l_chip, PU_OCB_OCI_QCSR_SCOM, l_data64));
+    FAPI_DBG("Working on cache[%d], good EXs in QCSR[%016llX]",
+             l_attr_chip_unit_pos, l_data64);
+
+    l_region_scan0 = p9hcd::SCAN0_REGION_ALL_BUT_EX;
+
+    if (l_data64 & BIT64(l_attr_chip_unit_pos << 1))
+    {
+        l_region_scan0 |= p9hcd::SCAN0_REGION_EX0_L2_L3_REFR;
+        l_l2gmux_reset |= BIT64(32);
+        l_l2gmux_input |= BIT64(34);
+    }
+
+    if (l_data64 & BIT64((l_attr_chip_unit_pos << 1) + 1))
+    {
+        l_region_scan0 |= p9hcd::SCAN0_REGION_EX1_L2_L3_REFR;
+        l_l2gmux_reset |= BIT64(33);
+        l_l2gmux_input |= BIT64(35);
+    }
+
+    //--------------------------
+    // Reset cache chiplet logic
+    //--------------------------
+    // If there is an unused, powered-off cache chiplet which needs to be
+    // configured in the following steps to setup the PCB endpoint.
+
+    for(auto it : l_core_functional_vector)
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,
+                               it.getParent<fapi2::TARGET_TYPE_PERV>(),
+                               l_attr_chip_unit_pos));
+        FAPI_DBG("Assert core[%d] DCC reset via NET_CTRL0[2]",
+                 (l_attr_chip_unit_pos - p9hcd::PERV_TO_CORE_POS_OFFSET));
+        FAPI_TRY(putScom(l_chip, (C_NET_CTRL0_WOR + (0x1000000 *
+                                  (l_attr_chip_unit_pos - p9hcd::PERV_TO_CORE_POS_OFFSET))),
+                         MASK_SET(2)));
+    }
+
+    /// @todo needs to revisit this sim workaround
+    FAPI_DBG("Init heartbeat hang counter via HANG_PULSE_6[2]");
+    FAPI_TRY(putScom(i_target, EQ_HANG_PULSE_6_REG, MASK_SET(2)));
+
+    FAPI_DBG("Init NET_CTRL0[1-5,11-14,16,18,22,25,26],step needed for hotplug");
+    l_data64 = Q_NET_CTRL0_INIT_VECTOR;
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0, l_data64));
+
+    FAPI_DBG("Assert progdly/DCC bypass,L2 DCC reset via NET_CTRL1[1,2,23,24]");
+    l_data64.flush<0>().insertFromRight<1, 2>(0x3).insertFromRight<23, 2>(0x3);
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL1_WOR, l_data64));
+
+    FAPI_DBG("Flip cache glsmux to DPLL input via PPM_CGCR[3]");
+    FAPI_TRY(putScom(i_target, EQ_PPM_CGCR, MASK_OR(0, 4, 0x9)));
+
+    FAPI_DBG("Flip L2 glsmux to DPLL input via QPPM_EXCGCR[34:35]");
+    FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_OR, l_l2gmux_input));
+
+    FAPI_DBG("Assert DPLL ff_bypass via QPPM_DPLL_CTRL[2]");
+    FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_OR, MASK_SET(2)));
+
+    FAPI_DBG("Drop vital thold via NET_CTRL0[16]");
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(16)));
+
+    /// @todo optional setup sector buffer strength, pulse mode and pulsed mode enable
+
+    FAPI_DBG("Drop cache glsmux reset via PPM_CGCR[0]");
+    FAPI_TRY(putScom(i_target, EQ_PPM_CGCR, MASK_SET(3)));
+
+    FAPI_DBG("Drop L2 glsmux reset via QPPM_EXCGCR[32:33]");
+    FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_CLEAR, l_l2gmux_reset));
+
+    FAPI_TRY(fapi2::delay(
+                 CACHE_GLSMUX_RESET_DELAY_REF_CYCLES * p9hcd::CLK_PERIOD_10NS,
+                 CACHE_GLSMUX_RESET_DELAY_REF_CYCLES * p9hcd::SIM_CYCLE_200UD));
+
+    FAPI_DBG("Assert chiplet enable via NET_CTRL0[0]");
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(0)));
+
+    FAPI_DBG("Drop PCB endpoint reset via NET_CTRL0[1]");
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(1)));
+
+    FAPI_DBG("Drop chiplet electrical fence via NET_CTRL0[26]");
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(26)));
+
+    FAPI_DBG("Drop PCB fence via NET_CTRL0[25]");
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(25)));
+
+    FAPI_DBG("Set scan ratio to 1:1 in bypass mode via OPCG_ALIGN[47-51]");
+    FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64));
+    l_data64.insertFromRight<47, 5>(0x0);
+    FAPI_TRY(putScom(i_target, EQ_OPCG_ALIGN, l_data64));
+
+#ifndef P9_HCD_STOP_SKIP_FLUSH
+    //--------------------------------------------
+    // perform scan0 module for pervasive chiplet
+    //--------------------------------------------
+    // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest
+    // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has
+    // all stumps less than 8191, the loop can be removed.
+
+    // Putting in block to avoid c++ crosses initialization compile error
+    {
+        uint32_t l_loop;
+
+        FAPI_DBG("Scan0 region:all_but_vital type:gptr_repr_time rings");
+
+        for(l_loop = 0; l_loop < P9_HCD_SCAN_GPTR_REPEAT; l_loop++)
+            FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
+                                                  l_region_scan0,
+                                                  p9hcd::SCAN0_TYPE_GPTR_REPR_TIME));
+
+        FAPI_DBG("Scan0 region:all_but_vital type:all_but_gptr_repr_time rings");
+
+        for(l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++)
+            FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
+                                                  l_region_scan0,
+                                                  p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME));
+    }
+#endif
+
+    /// @todo scan_with_setpulse_module(L3 DCC)
+    //FAPI_DBG("Drop L3 DCC bypass via NET_CTRL1[1]");
+    //FAPI_TRY(putScom(i_target, EQ_NET_CTRL1_WAND, MASK_UNSET(1)));
+    /// @todo add VDM_ENABLE attribute control
+    //FAPI_DBG("Assert vdm enable via CPPM_VDMCR[0]");
+    //FAPI_TRY(putScom(i_target, EQ_PPM_VDMCR_OR, MASK_SET(0)));
+
+fapi_try_exit:
+
+    FAPI_INF("<<p9_hcd_cache_chiplet_reset");
+    return fapi2::current_err;
+}
+
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H
new file mode 100644
index 00000000..1582c76d
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_chiplet_reset.H
+/// @brief Cache Chiplet Reset
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CACHE_CHIPLET_RESET_H__
+#define __P9_HCD_CACHE_CHIPLET_RESET_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_cache_chiplet_reset_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_cache_chiplet_reset_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+extern "C"
+{
+
+/// @brief Cache Chiplet Reset
+/// @param [in] i_target TARGET_TYPE_EQ target
+/// @return FAPI2_RC_SUCCESS if success, else error code
+    fapi2::ReturnCode
+    p9_hcd_cache_chiplet_reset(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+
+}
+
+#endif  // __P9_HCD_CACHE_CHIPLET_RESET_H__
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C
new file mode 100644
index 00000000..64b30d93
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C
@@ -0,0 +1,71 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_dpll_initf.C
+/// @brief Load DPLL ring for EX non-core
+///
+/// Procedure Summary:
+///   Load cache ring images from MVPD
+///   These rings must contain ALL chip customization data.
+///   This includes the following:  DPLL Power headers, and DTS
+///   Historically this was stored in MVPD keywords are #R, #G. Still stored in
+///     MVPD, but SBE image is customized with rings for booting cores
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <p9_ring_id.h>
+#include "p9_hcd_cache_dpll_initf.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Procedure: Load DPLL ring for cache
+//------------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_cache_dpll_initf(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+{
+    FAPI_INF(">>p9_hcd_cache_dpll_initf");
+
+    FAPI_DBG("Scan eq_dpll_func ring");
+    FAPI_TRY(fapi2::putRing(i_target, eq_dpll_func),
+             "Error from putRing (eq_dpll_func)");
+
+fapi_try_exit:
+    FAPI_INF("<<p9_hcd_cache_dpll_initf");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H
new file mode 100644
index 00000000..3c48f52a
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H
@@ -0,0 +1,65 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_initf.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_dpll_initf.H
+/// @brief Load DPLL ring for EX non-core
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CACHE_DPLL_INITF_H__
+#define __P9_HCD_CACHE_DPLL_INITF_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_cache_dpll_initf_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_cache_dpll_initf_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+extern "C"
+{
+
+/// @brief Load DPLL ring for EX non-core
+///
+/// @param [in] i_target TARGET_TYPE_EQ target
+///
+/// @attr
+/// @attritem ATTR_CACHE_DPLL_RING - EX target, uint32
+///               pointer to RS4 content, VPD #R Keyword content(RS4)<br>
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_cache_dpll_initf(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+
+}
+
+#endif  // __P9_HCD_CACHE_DPLL_INITF_H__
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C
new file mode 100644
index 00000000..744f0ae9
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C
@@ -0,0 +1,206 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_dpll_setup.C
+/// @brief Quad DPLL Setup
+///
+/// Procedure Summary:
+///   Note:
+///     Initfiles in procedure defined on VBU ENGD wiki (TODO add link)
+///     DPLL tune bits are not dependent on frequency
+///     Frequency is controlled by the Quad PPM
+///       Actual frequency value for boot is stored into the Quad PPM by
+///         p9_hcd_setup_evid.C in istep 2
+///       In real cache STOP exit, the frequency value is persistent
+///
+///   Pre-Scan:
+///
+///   Scan:
+///     (TODO) Set clock controller scan ratio to 1:1 as this is done at refclk
+///     (TODO) scan0 (region = DPLL and ANEP, scan_type = GPTR)
+///     (TODO) scan0 (region = DPLL and ANEP, scan_type = FUNC)
+///     (TODO) Set clock controller scan ratio to 8:1 for future scans
+///
+///   Setup:
+///     (TODO) set DPLL FREQ CTRL regitster
+///     (TODO) set DPLL CTRL register
+///     (Done) Drop DPLL test mode;
+///     (Done) Drop DPLL into Reset;
+///     (Done) Start DPLL clock via quad clock controller
+///     (Done) Check for DPLL lock, Timeout: 200us
+///     (Done) Remove DPLL bypass
+///     (Done) Switch cache glitchless mux to use the DPLL
+///     (Done) Drop ff_bypass to enable slewing
+///
+/// 1) reset, dpll_func_clksel, and all SL_HLD inputs are asserted
+/// 2) If grid clock connected to dpll clkout,
+///    bypass also has to be asserted to allow refclk on grid
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+
+#include <p9_quad_scom_addresses.H>
+#include <p9_perv_sbe_cmn.H>
+#include <p9_hcd_common.H>
+#include "p9_hcd_cache_dpll_setup.H"
+
+//-----------------------------------------------------------------------------
+// Constant Definitions
+//-----------------------------------------------------------------------------
+
+enum P9_HCD_CACHE_DPLL_SETUP_CONSTANTS
+{
+    CACHE_DPLL_LOCK_TIMEOUT_IN_MS      = 1,
+    CACHE_DPLL_CLK_START_TIMEOUT_IN_MS = 1,
+    CACHE_ANEP_CLK_START_TIMEOUT_IN_MS = 1
+};
+
+//-----------------------------------------------------------------------------
+// Procedure: Quad DPLL Setup
+//-----------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_cache_dpll_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+{
+    FAPI_INF(">>p9_hcd_cache_dpll_setup");
+    fapi2::buffer<uint64_t>                  l_data64;
+    uint32_t                                 l_timeout;
+
+    //----------------------------
+    // Prepare to start DPLL clock
+    //----------------------------
+
+    FAPI_DBG("Assert DPLL in mode 1,set slew rate via QPPM_DPLL_CTRL[2,6-15]");
+    l_data64.flush<0>().setBit<2>().insertFromRight<6, 10>(0x40);
+    FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_OR, l_data64));
+
+    FAPI_DBG("Drop flushmode_inhibit via CPLT_CTRL0[2]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_SET(2)));
+
+    FAPI_DBG("Drop DPLL test mode and reset via NET_CTRL0[3,4]");
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_AND(3, 2, 0)));
+
+    FAPI_DBG("Drop DPLL clock region fence via NET_CTRL1[14]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(14)));
+
+    // ----------------
+    // Start DPLL clock
+    // ----------------
+
+    FAPI_DBG("Clear all bits prior start DPLL clock via SCAN_REGION_TYPE");
+    FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO));
+
+    FAPI_DBG("Start DPLL clock via CLK_REGION");
+    l_data64 = (p9hcd::CLK_START_CMD   |
+                p9hcd::CLK_REGION_DPLL |
+                p9hcd::CLK_THOLD_ALL);
+    FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64));
+
+    FAPI_DBG("Poll for DPLL clock running via CPLT_STAT0[8]");
+    l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
+                CACHE_DPLL_CLK_START_TIMEOUT_IN_MS;
+
+    do
+    {
+        FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64));
+    }
+    while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0));
+
+    FAPI_ASSERT((l_timeout != 0),
+                fapi2::PMPROC_DPLLCLKSTART_TIMEOUT().set_EQCPLTSTAT(l_data64),
+                "DPLL Clock Start Timeout");
+
+    FAPI_DBG("Check DPLL clock running via CLOCK_STAT_SL[14]");
+    FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64));
+
+    FAPI_ASSERT((l_data64.getBit<14>() == 0),
+                fapi2::PMPROC_DPLLCLKSTART_FAILED().set_EQCLKSTAT(l_data64),
+                "DPLL Clock Start Failed");
+    FAPI_DBG("DPLL clock running now");
+
+    // This is necessary to ensure that the DPLL is in Mode 1(ff_bypass = 1)
+    // If not, the lock times will go from ~30us to 3-5ms
+    FAPI_DBG("Poll for DPLL to lock via QPPM_DPLL_STAT");
+    l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
+                CACHE_DPLL_LOCK_TIMEOUT_IN_MS;
+
+    do
+    {
+        FAPI_TRY(getScom(i_target, EQ_QPPM_DPLL_STAT, l_data64));
+        ///@todo disable poll for DPLL lock until model setting in place
+        break;
+    }
+    while ((l_data64.getBit<63>() != 1 ) && (--l_timeout != 0));
+
+    FAPI_ASSERT((l_timeout != 0),
+                fapi2::PMPROC_DPLL_LOCK_TIMEOUT()
+                .set_EQQPPMDPLLSTAT(l_data64),
+                "DPLL Lock Timeout");
+    FAPI_DBG("DPLL is locked now");
+
+    //--------------------------
+    // Cleaning up
+    //--------------------------
+
+    FAPI_DBG("Drop DPLL bypass via NET_CTRL0[5]");
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(5)));
+
+    FAPI_DBG("Drop DPLL ff_bypass via QPPM_DPLL_CTRL[2]");
+    FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_CLEAR, MASK_SET(2)));
+
+    FAPI_DBG("Assert flushmode_inhibit via CPLT_CTRL0[2]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_OR, MASK_SET(2)));
+
+    FAPI_DBG("Set scan ratio to 4:1 in non-bypass mode via OPCG_ALIGN[47-51]");
+    FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64));
+    l_data64.insertFromRight<47, 5>(0x3);
+    FAPI_TRY(putScom(i_target, EQ_OPCG_ALIGN, l_data64));
+
+    FAPI_DBG("Drop ANEP clock region fence via CPLT_CTRL1[10]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(10)));
+
+    FAPI_DBG("Drop skew/duty cycle adjust func_clksel via NET_CTRL0[22]");
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(22)));
+
+    FAPI_DBG("Drop skew adjust reset via NET_CTRL0[2]");
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(2)));
+
+fapi_try_exit:
+
+    FAPI_INF("<<p9_hcd_cache_dpll_setup");
+    return fapi2::current_err;
+}
+
+
+
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H
new file mode 100644
index 00000000..0da2ea3b
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H
@@ -0,0 +1,65 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_dpll_setup.H
+/// @brief Quad DPLL Setup
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CACHE_DPLL_SETUP_H__
+#define __P9_HCD_CACHE_DPLL_SETUP_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_cache_dpll_setup_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_cache_dpll_setup_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+extern "C"
+{
+/// @brief Quad DPLL Setup
+///
+/// @param [in] i_target TARGET_TYPE_EQ target
+///
+/// @attr
+/// @attritem ATTR_DPLL_REPAIR_RING - EQ target, uint32
+///               repair dpll ring content<br>
+///
+/// @retval FAPI2_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_cache_dpll_setup(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+
+
+} // extern C
+
+#endif  // __P9_HCD_CACHE_DPLL_SETUP_H__
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C
new file mode 100644
index 00000000..4a2e620f
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C
@@ -0,0 +1,126 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_gptr_time_initf.C
+/// @brief Load GPTR and Time for EX non-core
+///
+/// Procedure Summary:
+///   Initfiles in procedure defined on VBU ENGD wiki (TODO add link)
+///     to produce #G VPD contents
+///   Check for the presence of core override GPTR ring from image
+///     (this is new fvor P9)
+///   if found, apply;  if not, apply core GPTR from image
+///     Check for the presence of core override TIME ring from image;
+///   if found, apply;  if not, apply core base TIME from image
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <p9_ring_id.h>
+#include "p9_hcd_cache_gptr_time_initf.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Procedure: Load GPTR and Time for EX non-core
+//------------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_cache_gptr_time_initf(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+{
+    FAPI_INF(">>p9_hcd_cache_gptr_time_initf");
+
+    auto l_ex_targets = i_target.getChildren<fapi2::TARGET_TYPE_EX>();
+
+    FAPI_DBG("Scan eq_gptr ring");
+    FAPI_TRY(fapi2::putRing(i_target, eq_gptr,
+                            fapi2::RING_MODE_HEADER_CHECK),
+             "Error from putRing (eq_gptr)");
+
+    FAPI_DBG("Scan eq_time ring");
+    FAPI_TRY(fapi2::putRing(i_target, eq_time,
+                            fapi2::RING_MODE_HEADER_CHECK),
+             "Error from putRing (eq_time)");
+
+    for (auto l_ex : l_ex_targets)
+    {
+        FAPI_DBG("Scan ex_l3_gptr ring");
+        FAPI_TRY(fapi2::putRing(l_ex, ex_l3_gptr,
+                                fapi2::RING_MODE_HEADER_CHECK),
+                 "Error from putRing (ex_l3_gptr)");
+
+        FAPI_DBG("Scan ex_l2_gptr ring");
+        FAPI_TRY(fapi2::putRing(l_ex, ex_l2_gptr,
+                                fapi2::RING_MODE_HEADER_CHECK),
+                 "Error from putRing (ex_l2_gptr)");
+
+        FAPI_DBG("Scan ex_l3_refr_gptr ring");
+        FAPI_TRY(fapi2::putRing(l_ex, ex_l3_refr_gptr,
+                                fapi2::RING_MODE_HEADER_CHECK),
+                 "Error from putRing (ex_l3_refr_gptr)");
+
+        FAPI_DBG("Scan ex_l3_time ring");
+        FAPI_TRY(fapi2::putRing(l_ex, ex_l3_time,
+                                fapi2::RING_MODE_HEADER_CHECK),
+                 "Error from putRing (ex_l3_time)");
+
+        FAPI_DBG("Scan ex_l2_time ring");
+        FAPI_TRY(fapi2::putRing(l_ex, ex_l2_time,
+                                fapi2::RING_MODE_HEADER_CHECK),
+                 "Error from putRing (ex_l2_time)");
+
+        FAPI_DBG("Scan ex_l3_refr_time ring");
+        FAPI_TRY(fapi2::putRing(l_ex, ex_l3_refr_time,
+                                fapi2::RING_MODE_HEADER_CHECK),
+                 "Error from putRing (ex_l3_refr_time)");
+    }
+
+    FAPI_DBG("Scan eq_dpll_gptr ring");
+    FAPI_TRY(fapi2::putRing(i_target, eq_dpll_gptr,
+                            fapi2::RING_MODE_HEADER_CHECK),
+             "Error from putRing (eq_dpll_gptr)");
+
+    FAPI_DBG("Scan eq_ana_gptr ring");
+    FAPI_TRY(fapi2::putRing(i_target, eq_ana_gptr,
+                            fapi2::RING_MODE_HEADER_CHECK),
+             "Error from putRing (eq_ana_gptr)");
+
+fapi_try_exit:
+
+    FAPI_INF("<<p9_hcd_cache_gptr_time_initf");
+    return fapi2::current_err;
+}
+
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H
new file mode 100644
index 00000000..714395cf
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H
@@ -0,0 +1,65 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_gptr_time_initf.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_gptr_time_initf.H
+/// @brief Load GPTR and Time for EX non-core
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CACHE_GPTR_TIME_INIT_H__
+#define __P9_HCD_CACHE_GPTR_TIME_INIT_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_cache_gptr_time_initf_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_cache_gptr_time_initf_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+extern "C"
+{
+
+/// @brief Load GPTR and Time for EX non-core
+///
+/// @param [in] i_target TARGET_TYPE_EQ target
+///
+/// @attr
+/// @attritem ATTR_CACHE_GPTR_TIME_RING - EX target, uint32
+///               pointer to RS4 content.<br>
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_cache_gptr_time_initf(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+
+}
+
+#endif  // __P9_HCD_CACHE_GPTR_TIME_INIT_H__
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
new file mode 100644
index 00000000..3eb56747
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C
@@ -0,0 +1,88 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.C $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_initf.C
+/// @brief EX (non-core) scan init
+///
+/// Procedure Summary:
+///   Initfiles in procedure defined on VBU ENGD wiki (TODO add link)
+///   Check for the presence of cache FUNC override rings from image;
+///   if found, apply;  if not, apply cache base FUNC rings from image
+///   Note:  FASTINIT ring (eg CMSK ring) is setup at this point to limit the
+///   stumps that participate in FUNC ring scanning (this is new for P9).
+///   (TODO to make sure the image build support is in place)
+///   Note: all caches that are in the Cache Multicast group will be
+///   initialized to the same values via multicast scans
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include "p9_hcd_cache_initf.H"
+
+//------------------------------------------------------------------------------
+// Procedure: EX (non-core) scan init
+//------------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_cache_initf(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+{
+    FAPI_INF(">>p9_hcd_cache_initf");
+
+    FAPI_DBG("Scan eq_fure ring");
+    FAPI_TRY(fapi2::putRing(i_target, eq_fure),
+             "Error from putRing (eq_fure)");
+    FAPI_DBG("Scan eq_ana_func ring");
+    FAPI_TRY(fapi2::putRing(i_target, eq_ana_func),
+             "Error from putRing (eq_ana_func)");
+
+    for (auto l_ex_target : i_target.getChildren<fapi2::TARGET_TYPE_EX>())
+    {
+        FAPI_DBG("Scan ex_l2_fure ring");
+        FAPI_TRY(fapi2::putRing(l_ex_target, ex_l2_fure),
+                 "Error from putRing (ex_l2_fure)");
+        FAPI_DBG("Scan ex_l2_mode ring");
+        FAPI_TRY(fapi2::putRing(l_ex_target, ex_l2_mode),
+                 "Error from putRing (ex_l2_mode)");
+        FAPI_DBG("Scan ex_l3_fure ring");
+        FAPI_TRY(fapi2::putRing(l_ex_target, ex_l3_fure),
+                 "Error from putRing (ex_l3_fure)");
+        FAPI_DBG("Scan ex_l3_refr_fure ring");
+        FAPI_TRY(fapi2::putRing(l_ex_target, ex_l3_refr_fure),
+                 "Error from putRing (ex_l3_refr_fure)");
+    }
+
+fapi_try_exit:
+    FAPI_INF("<<p9_hcd_cache_initf");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H
new file mode 100644
index 00000000..1754c690
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H
@@ -0,0 +1,65 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_initf.H $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_initf.H
+/// @brief EX (non-core) scan init
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CACHE_INITF_H__
+#define __P9_HCD_CACHE_INITF_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_cache_initf_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_cache_initf_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+extern "C"
+{
+
+/// @brief EX (non-core) scan init
+///
+/// @param [in] i_target TARGET_TYPE_EQ target
+///
+/// @attr
+/// @attritem ATTR_CACHE_L2_FUNC_RING - EX target, uint32
+/// @attritem ATTR_CACHE_L3_FUNC_RING - EX target, uint32
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_cache_initf(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+
+}
+
+#endif  // __P9_HCD_CACHE_INITF_H__
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C
new file mode 100644
index 00000000..d0e592a4
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C
@@ -0,0 +1,93 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_occ_runtime_scom.C
+/// @brief EX OCC runtime scoms
+///
+/// *HWP HWP Owner   : David Du       <daviddu@us.ibm.com>
+/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
+/// *HWP Team        : PM
+/// *HWP Consumed by : SBE:SGPE
+/// *HWP Level       : 1
+///
+/// Procedure Summary:
+///   Run-time updates from OCC code that are put  somewhere TBD
+///     (TODO . revisit with OCC FW team)
+///   OCC FW sets up value in the TBD SCOM section
+///   This was not leverage in P8 with the demise of CPMs
+///   Placeholder at this point
+///
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi2.H>
+//#include <common_scom_addresses.H>
+//will be replaced with real scom address header file
+#include "p9_hcd_cache_occ_runtime_scom.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions
+//------------------------------------------------------------------------------
+#define host_runtime_scom 0
+
+//------------------------------------------------------------------------------
+// Procedure: EX OCC runtime SCOMS
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+    fapi2::ReturnCode
+    p9_hcd_cache_occ_runtime_scom(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+    {
+
+#if 0
+        fapi2::buffer<uint64_t> data;
+
+        // Run the SCOM sequence if the SCOM procedure is defined
+        // -   la      A0, occ_runtime_scom
+        // -   ld      D0, 0, A0
+        // -   braz    D0, 1f
+        FAPI_INF("Launching OCC Runtime SCOM routine")
+        // -   bsrd    D0
+        // -   1:
+
+        return fapi2::FAPI2_RC_SUCCESS;
+
+        FAPI_CLEANUP();
+        return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
+
+#endif
+
+        return fapi2::FAPI2_RC_SUCCESS;
+
+    } // Procedure
+
+
+} // extern C
+
+
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H
new file mode 100644
index 00000000..24c329f8
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H
@@ -0,0 +1,63 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_occ_runtime_scom.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_occ_runtime_scom.H
+/// @brief EX OCC runtime scoms
+///
+/// *HWP HWP Owner   : David Du       <daviddu@us.ibm.com>
+/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
+/// *HWP Team        : PM
+/// *HWP Consumed by : SBE:SGPE
+/// *HWP Level       : 1
+///
+
+#ifndef __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__
+#define __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__
+
+extern "C"
+{
+
+/// @typedef p9_hcd_cache_occ_runtime_scom_FP_t
+/// function pointer typedef definition for HWP call support
+    typedef fapi2::ReturnCode (*p9_hcd_cache_occ_runtime_scom_FP_t) (
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+
+/// @brief EX OCC runtime scoms
+///
+/// @param [in] i_target TARGET_TYPE_EQ target
+///
+/// @attr
+/// @attritem ATTR_CACHE_OCC_SCOM_LOC - EX target, uint32
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_cache_occ_runtime_scom(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+
+
+} // extern C
+
+#endif  // __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C
new file mode 100644
index 00000000..c5193803
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C
@@ -0,0 +1,92 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_poweron.C
+/// @brief Cache Chiplet Power-on
+///
+/// Procedure Summary:
+///   Set glsmux async reset
+///   Set DPLL ff_bypass
+///   Command the cache PFET controller to power-on
+///   Check for valid power on completion
+///   Polled Timeout:  100us
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <p9_quad_scom_addresses.H>
+#include <p9_hcd_common.H>
+#include <p9_common_poweronoff.H>
+#include <p9_common_poweronoff.C>
+#include "p9_hcd_cache_poweron.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Procedure: Cache Chiplet Power-on
+//------------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_cache_poweron(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+{
+    FAPI_INF(">>p9_hcd_cache_poweron");
+    fapi2::buffer<uint64_t> l_data64;
+
+    //--------------------------
+    // Prepare to power on cache
+    //--------------------------
+
+    FAPI_DBG("Drop chiplet enable via NET_CTRL0[0]");
+    FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(0)));
+
+    FAPI_DBG("Assert L2 glsmux reset via EXCLK_GRID_CTRL[32:33]");
+    FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_OR, MASK_OR(32, 2, 0x3)));
+
+    FAPI_DBG("Assert cache glsmux reset via CLOCK_GRID_CTRL[0]");
+    FAPI_TRY(putScom(i_target, EQ_PPM_CGCR, MASK_SET(0)));
+
+    //-----------------------
+    // Power on cache chiplet
+    //-----------------------
+
+    FAPI_DBG("Power on cache chiplet");
+    FAPI_TRY(p9_common_poweronoff<fapi2::TARGET_TYPE_EQ>(i_target, p9power::POWER_ON));
+
+fapi_try_exit:
+
+    FAPI_INF("<<p9_hcd_cache_poweron");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H
new file mode 100644
index 00000000..656616f4
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H
@@ -0,0 +1,63 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_poweron.H
+/// @brief Cache Chiplet Power-on
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Level              : 2
+// *HWP Consumed by        : SBE:SGPE
+
+#ifndef __P9_HCD_CACHE_POWERON_H__
+#define __P9_HCD_CACHE_POWERON_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_cache_poweron_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_cache_poweron_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+extern "C"
+{
+/// @brief Cache Chiplet Power-on
+/// @param [in] i_target    TARGET_TYPE_EQ target
+/// @param [in] i_operation ENUM(ON,OFF)
+///
+/// @attr
+/// @attritem ATTR_PFET_*
+///
+/// @retval FAPI2_RC_SUCCESS if success, else error code
+
+    fapi2::ReturnCode
+    p9_hcd_cache_poweron(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+}
+
+#endif  // __P9_HCD_CACHE_POWERON_H__
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C
new file mode 100644
index 00000000..5398597e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C
@@ -0,0 +1,171 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_ras_runtime_scom.C
+/// @brief EX FSP/Host runtime scoms
+///
+/// *HWP HWP Owner   : David Du       <daviddu@us.ibm.com>
+/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
+/// *HWP Team        : PM
+/// *HWP Consumed by : SGPE
+/// *HWP Level       : 1
+///
+/// Procedure Summary:
+///   Run-time updates by FSP/Host(including HostServices and Hypervisors)
+///     that are put on the cache image by STOP API calls
+///   Dynamically built pointer where a NULL is checked before execution
+///   If NULL (the SBE case), return
+///   Else call the function at the pointer;  pointer is filled in by
+///     STOP image build
+///   Powerbus (MCD) and L3 BAR settings
+///   Runtime FIR mask updates from PRD
+///   L2/L3 Repairs
+///
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi2.H>
+//#include <common_scom_addresses.H>
+//will be replaced with real scom address header file
+#include "p9_hcd_cache_ras_runtime_scom.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions
+//------------------------------------------------------------------------------
+#define host_runtime_scom 0
+
+//------------------------------------------------------------------------------
+// Procedure: EX FSP/HOST runtime scoms
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+    fapi2::ReturnCode
+    p9_hcd_cache_ras_runtime_scom(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+    {
+
+#if 0
+        fapi2::buffer<uint64_t> data;
+
+        // Run the SCOM sequence if the SCOM procedure is defined
+        // -   la      A0, sp_runtime_scom
+        // -   ld      D0, 0, A0
+        // -   braz    D0, 1f
+        //FAPI_INF("Launching SP Runtime SCOM routine")
+        // -   bsrd    D0
+        // -   1:
+        //
+
+        // Run the SCOM sequence if the SCOM procedure is defined.
+        // -   la      A0, host_runtime_scom
+        // -   ld      D1, 0, A0
+        // -   braz    D1, 1f
+
+        // Prep P1
+        // -   setp1_mcreadand D0
+
+#if 0
+        // Disable the AISS to allow the override
+        // =   ld      D0, EX_OHA_MODE_REG_RWx1002000D, P1
+        // =   andi    D0, D0, ~(BIT(1))
+        // =   std     D0, EX_OHA_MODE_REG_RWx1002000D, P0
+        // Drop PSCOM fence to allow SCOM and set pm_wake-up to PC to accepts
+        // RAMs (SCOMs actually) in the IPL "Nap" state
+        // =   ld      D0, EX_OHA_AISS_IO_REG_0x10020014, P1
+        // =   ori     D0, D0, (BIT(15))
+        // =   andi    D0, D0, ~(BIT(21))
+        // =   std     D0, EX_OHA_AISS_IO_REG_0x10020014, P0
+#endif
+
+        // Branch to sub_slw_runtime_scom()
+        FAPI_INF("Launching Host Runtime SCOM routine")
+        // -   bsrd    D1
+
+        // Prep P1
+        // -   setp1_mcreadand D0
+
+#if 0
+        // Clear regular wake-up and restore PSCOM fence in OHA
+        // These were established in p9_sbe_ex_scominit.S
+        // =   ld      D0, EX_OHA_AISS_IO_REG_0x10020014, P1
+        // =   andi    D0, D0, ~(BIT(15))
+        // =   ori     D0, D0, BIT(21)
+        // =   std     D0, EX_OHA_AISS_IO_REG_0x10020014, P0
+        // Enable the AISS to allow further operation
+        // =   ld      D0, EX_OHA_MODE_REG_RWx1002000D, P1
+        // =   ori     D0, D0, (BIT(1))
+        // =   std     D0, EX_OHA_MODE_REG_RWx1002000D, P0
+#endif
+
+        // -   bra     2f
+        // -   1:
+
+        // To accomodate IPL flow, where sub_slw_runtime_scom() is skipped
+        // - setp1_mcreadand D0
+
+#if 0
+        // Clear regular wake-up and restore PSCOM fence in OHA
+        // These were established in p9_sbe_ex_scominit.S
+        // =   ld      D0, EX_OHA_MODE_REG_RWx1002000D, P1
+        // =   andi    D0, D0, ~BIT(1)
+        // =   std     D0, EX_OHA_MODE_REG_RWx1002000D, P0
+        // =   ld      D0, EX_OHA_AISS_IO_REG_0x10020014, P1
+        // =   andi    D0, D0, ~(BIT(15))
+        // =   ori     D0, D0, BIT(21)
+        // =   std     D0, EX_OHA_AISS_IO_REG_0x10020014, P0
+        // Enable the AISS to allow further operation
+        // =   ld      D0, EX_OHA_MODE_REG_RWx1002000D, P1
+        // =   ori     D0, D0, (BIT(1))
+        // =   std     D0, EX_OHA_MODE_REG_RWx1002000D, P0
+#endif
+        // -   2:
+
+        // If using cv_multicast, we need to set the magic istep number here
+        // -   la      A0, p9_sbe_select_ex_control
+        // -   ldandi  D0, 0, A0, P9_CONTROL_INIT_ALL_EX
+        // -   braz    D0, 3f
+        FAPI_DBG("Setting istep num to magic number because cv_multicast is set")
+        // -   lpcs    P1, MBOX_SBEVITAL_0x0005001C
+        // -   sti     MBOX_SBEVITAL_0x0005001C, P1, (P9_SBE_EX_RAS_RUNTIME_SCOM_MAGIC_ISTEP_NUM << (4+32))
+        // -   3:
+
+        return fapi2::FAPI2_RC_SUCCESS;
+
+        FAPI_CLEANUP();
+        return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
+
+#endif
+
+        return fapi2::FAPI2_RC_SUCCESS;
+
+    } // Procedure
+
+
+} // extern C
+
+
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H
new file mode 100644
index 00000000..394fb6f6
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H
@@ -0,0 +1,63 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_ras_runtime_scom.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_ras_runtime_scom.H
+/// @brief EX FSP/Host runtime scoms
+///
+/// *HWP HWP Owner   : David Du       <daviddu@us.ibm.com>
+/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
+/// *HWP Team        : PM
+/// *HWP Consumed by : SBE:SGPE
+/// *HWP Level       : 1
+///
+
+
+#ifndef __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__
+#define __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__
+
+extern "C"
+{
+
+/// @typedef p9_hcd_cache_ras_runtime_scom_FP_t
+/// function pointer typedef definition for HWP call support
+    typedef fapi2::ReturnCode (*p9_hcd_cache_ras_runtime_scom_FP_t) (
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+/// @brief EX FSP/Host runtime scoms
+///
+/// @param [in] i_target TARGET_TYPE_EQ target
+///
+/// @attr
+/// @attritem ATTR_CACHE_RAS_SCOM_LOC - EX target, uint32
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_cache_ras_runtime_scom(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+
+
+} // extern C
+
+#endif  // __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C
new file mode 100644
index 00000000..b34ae956
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C
@@ -0,0 +1,96 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_repair_initf.C
+/// @brief Load Repair ring for EX non-core
+///
+/// Procedure Summary:
+///   Load cache ring images from MVPD
+///   These rings must contain ALL chip customization data.
+///   This includes the following:  Repair Power headers, and DTS
+///   Historically this was stored in MVPD keywords are #R, #G. Still stored in
+///     MVPD, but SBE image is customized with rings for booting cores
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <p9_ring_id.h>
+#include "p9_hcd_cache_repair_initf.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Procedure: Load Repair ring for cache
+//------------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_cache_repair_initf(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+{
+    FAPI_INF(">>p9_hcd_cache_repair_initf");
+
+    auto l_ex_targets = i_target.getChildren<fapi2::TARGET_TYPE_EX>();
+
+    FAPI_DBG("Scan eq_repr ring");
+    FAPI_TRY(fapi2::putRing(i_target, eq_repr,
+                            fapi2::RING_MODE_HEADER_CHECK),
+             "Error from putRing (eq_repr)");
+
+    for (auto l_ex : l_ex_targets)
+    {
+        FAPI_DBG("Scan ex_l3_repr ring");
+        FAPI_TRY(fapi2::putRing(l_ex, ex_l3_repr,
+                                fapi2::RING_MODE_HEADER_CHECK),
+                 "Error from putRing (ex_l3_repr)");
+
+        FAPI_DBG("Scan ex_l2_repr ring");
+        FAPI_TRY(fapi2::putRing(l_ex, ex_l2_repr,
+                                fapi2::RING_MODE_HEADER_CHECK),
+                 "Error from putRing (ex_l2_repr)");
+
+        FAPI_DBG("Scan ex_l3_refr_repr ring");
+        FAPI_TRY(fapi2::putRing(l_ex, ex_l3_refr_repr,
+                                fapi2::RING_MODE_HEADER_CHECK),
+                 "Error from putRing (ex_l3_refr_repr)");
+    }
+
+fapi_try_exit:
+
+    FAPI_INF("<<p9_hcd_cache_repair_initf");
+    return fapi2::current_err;
+}
+
+
+
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H
new file mode 100644
index 00000000..3712cafb
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H
@@ -0,0 +1,65 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_repair_initf.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_repair_initf.H
+/// @brief Load Repair ring for EX non-core
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CACHE_REPAIR_INITF_H__
+#define __P9_HCD_CACHE_REPAIR_INITF_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_cache_repair_initf_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_cache_repair_initf_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+extern "C"
+{
+
+/// @brief Load Repair ring for EX non-core
+///
+/// @param [in] i_target TARGET_TYPE_EQ target
+///
+/// @attr
+/// @attritem ATTR_CACHE_REPAIR_RING - EX target, uint32
+///               pointer to RS4 content, VPD #R Keyword content(RS4)<br>
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_cache_repair_initf(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+
+}
+
+#endif  // __P9_HCD_CACHE_REPAIR_INITF_H__
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C
new file mode 100644
index 00000000..96ce825d
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C
@@ -0,0 +1,93 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_scomcust.C
+/// @brief Core Chiplet PCB Arbitration
+///
+/// *HWP HWP Owner   : David Du       <daviddu@us.ibm.com>
+/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
+/// *HWP Team        : PM
+/// *HWP Consumed by : SBE:SGPE
+/// *HWP Level       : 1
+///
+/// Procedure Summary:
+///   If CME, request PCB Mux.
+///     Poll for PCB Mux grant
+///   Else (SBE)
+///     Nop (as the CME is not running in bringing up the first Core)
+///
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi2.H>
+//#include <common_scom_addresses.H>
+//will be replaced with real scom address header file
+#include "p9_hcd_cache_scomcust.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions: Core Chiplet PCB Arbitration
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+    fapi2::ReturnCode
+    p9_hcd_cache_scomcust(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+    {
+
+#if 0
+
+        fapi2::buffer<uint64_t> data;
+
+        //Dynamically built (and installed) routine that is inserted by the .XIP
+        //Customization. process. (New for P9)
+        //(TODO:  this part of the process is a placeholder at this point)
+        //Dynamically built pointer where a NULL is checked before execution
+        //If NULL (a potential early value); return
+        //Else call the function at the pointer;
+        //pointer is filled in by XIP Customization
+        //Customization items:
+        //Epsilon settings scan flush to super safe
+        //Customize Epsilon settings for system config
+        //LCO setup (chiplet specific)
+        //FW setups up based victim caches
+
+        return fapi2::FAPI2_RC_SUCCESS;
+
+        FAPI_CLEANUP();
+        return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
+
+#endif
+
+        return fapi2::FAPI2_RC_SUCCESS;
+
+    } // Procedure
+
+
+} // extern C
+
+
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H
new file mode 100644
index 00000000..cc3e8884
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H
@@ -0,0 +1,62 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scomcust.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_scomcust.H
+/// @brief Core Chiplet PCB Arbitration
+///
+/// *HWP HWP Owner   : David Du       <daviddu@us.ibm.com>
+/// *HWP FW Owner    : Sangeetha T S  <sangeet2@in.ibm.com>
+/// *HWP Team        : PM
+/// *HWP Consumed by : SBE:SGPE
+/// *HWP Level       : 1
+///
+
+#ifndef __P9_HCD_CACHE_SCOMCUST_H__
+#define __P9_HCD_CACHE_SCOMCUST_H__
+extern "C"
+{
+
+/// @typedef p9_hcd_cache_scomcust_FP_t
+/// function pointer typedef definition for HWP call support
+    typedef fapi2::ReturnCode (*p9_hcd_cache_scomcust_FP_t) (
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+
+/// @brief Core Chiplet PCB Arbitration
+///
+/// @param [in] i_target TARGET_TYPE_EQ target
+///
+/// @attr
+/// @attritem NONE
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_cache_scomcust(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+
+
+} // extern C
+
+#endif  // __P9_HCD_CACHE_SCOMCUST_H__
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C
new file mode 100644
index 00000000..38ee4977
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C
@@ -0,0 +1,119 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_scominit.C
+/// @brief  Cache Customization SCOMs
+///
+/// Procedure Summary:
+///   Apply any SCOM initialization to the cache
+///   Stop L3 configuration mode
+///   Configure Trace Stop on Xstop
+///   DTS Initialization sequense
+///
+
+// *HWP HWP Owner          : David Du      <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still    <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <p9_quad_scom_addresses.H>
+#include <p9_hcd_common.H>
+#include <p9_l2_scom.H>
+#include <p9_l3_scom.H>
+#include <p9_ncu_scom.H>
+#include "p9_hcd_cache_scominit.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Procedure: Cache Customization SCOMs
+//------------------------------------------------------------------------------
+
+
+fapi2::ReturnCode
+p9_hcd_cache_scominit(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+{
+    FAPI_INF(">>p9_hcd_cache_scominit");
+    fapi2::buffer<uint64_t> l_data64;
+
+    fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+    auto l_ex_targets = i_target.getChildren<fapi2::TARGET_TYPE_EX>();
+    fapi2::ReturnCode l_rc;
+
+    for (auto l_iter = l_ex_targets.begin(); l_iter != l_ex_targets.end(); l_iter++)
+    {
+        FAPI_EXEC_HWP(l_rc, p9_l2_scom, *l_iter, FAPI_SYSTEM);
+
+        if (l_rc)
+        {
+            FAPI_ERR("Error from p9_l2_scom (p9.l2.scom.initfile)");
+            fapi2::current_err = l_rc;
+            goto fapi_try_exit;
+        }
+
+        FAPI_EXEC_HWP(l_rc, p9_l3_scom, *l_iter, FAPI_SYSTEM);
+
+        if (l_rc)
+        {
+            FAPI_ERR("Error from p9_l3_scom (p9.l3.scom.initfile)");
+            fapi2::current_err = l_rc;
+            goto fapi_try_exit;
+        }
+
+        FAPI_EXEC_HWP(l_rc, p9_ncu_scom, *l_iter, FAPI_SYSTEM);
+
+        if (l_rc)
+        {
+            FAPI_ERR("Error from p9_ncu_scom (p9.ncu.scom.initfile)");
+            fapi2::current_err = l_rc;
+            goto fapi_try_exit;
+        }
+    }
+
+    /// @todo set the sample pulse count (bit 6:9)
+    /// enable the appropriate loops
+    /// (needs investigation with the Perv team on the EC wiring).
+    FAPI_DBG("Enable DTS sampling via THERM_MODE_REG[5]");
+    FAPI_TRY(getScom(i_target, EQ_THERM_MODE_REG, l_data64));
+    FAPI_TRY(putScom(i_target, EQ_THERM_MODE_REG, DATA_SET(5)));
+
+fapi_try_exit:
+
+    FAPI_INF("<<p9_hcd_cache_scominit");
+    return fapi2::current_err;
+}
+
+
+
+
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H
new file mode 100644
index 00000000..ded02249
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_scominit.H
+/// @brief  Cache Customization SCOMs
+///
+
+// *HWP HWP Owner          : David Du      <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still    <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CACHE_SCOMINIT_H__
+#define __P9_HCD_CACHE_SCOMINIT_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_cache_scominit_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_cache_scominit_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+extern "C"
+{
+
+/// @brief  Cache Customization SCOMs
+///
+/// @param [in] i_target TARGET_TYPE_EQ target
+///
+/// @attr
+/// @attritem NONE
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_cache_scominit(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+
+}
+
+#endif  // __P9_HCD_CACHE_SCOMINIT_H__
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C
new file mode 100644
index 00000000..a7bc1510
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C
@@ -0,0 +1,334 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_startclocks.C
+/// @brief Quad Clock Start
+///
+/// Procedure Summary:
+///   (Done) Setup L3 EDRAM/LCO
+///   (Done) Setup OPCG_ALIGN
+///   (Done) Drop partial good regional fences(always drop vital and pervasive)
+///   (Done) Drop Vital fence
+///   (Done) Reset abst clock muxsel, sync muxsel
+///   (TODO) Set fabric node/chip ID from the nest version
+///   (Done) module align_chiplets
+///   (Done)  - set flushmode_inh to exit flush mode
+///   (Done)  - set force align
+///   (Done)  - set chiplet_is_aligned
+///   (Done)  - clear chiplet_is_aligned
+///   (Done)  - wait
+///   (Done)  - check chiplet is aligned
+///   (Done)  - clear force align
+///   (Done) module start_clocks
+///   (Done)  - Clear clock controller scan register before start
+///   (Done)  - Start arrays + nsl regions
+///   (Done)  - Start sl + refresh clock regions
+///   (Done) Check for clocks started. If not, error
+///   (Done) Drop the cache to PowerBus logical fence
+///   (Done) Check for cache xstop, If so, error
+///   (Done) Clear flushmode_inh to go into flush mode
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <p9_misc_scom_addresses.H>
+#include <p9_quad_scom_addresses.H>
+#include <p9_hcd_common.H>
+#include "p9_hcd_cache_startclocks.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions
+//------------------------------------------------------------------------------
+
+enum P9_HCD_CACHE_STARTCLOCKS_CONSTANTS
+{
+    CACHE_CLK_SYNC_TIMEOUT_IN_MS        = 1,
+    CACHE_CLK_START_TIMEOUT_IN_MS       = 1,
+    CACHE_CLK_ALIGN_DELAY_CACHE_CYCLES  = 255
+};
+
+//------------------------------------------------------------------------------
+// Procedure: Quad Clock Start
+//------------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_cache_startclocks(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target)
+{
+    FAPI_INF(">>p9_hcd_cache_startclocks");
+    fapi2::buffer<uint64_t>                     l_qcsr;
+    fapi2::buffer<uint64_t>                     l_data64;
+    uint64_t                                    l_region_clock;
+    uint64_t                                    l_l2sync_clock;
+    uint64_t                                    l_l2pscom_mask;
+    uint64_t                                    l_l3pscom_mask;
+    uint32_t                                    l_timeout;
+    uint32_t                                    l_attr_system_id     = 0;
+    uint8_t                                     l_attr_group_id      = 0;
+    uint8_t                                     l_attr_chip_id       = 0;
+    uint8_t                                     l_attr_chip_unit_pos = 0;
+    uint8_t                                     l_attr_system_ipl_phase;
+    uint32_t                                    l_attr_pg;
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
+        i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+    fapi2::Target<fapi2::TARGET_TYPE_PERV>      l_perv =
+        i_target.getParent<fapi2::TARGET_TYPE_PERV>();
+    fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>    l_sys;
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE,      l_sys,
+                           l_attr_system_ipl_phase));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID,  l_chip,
+                           l_attr_group_id));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID,   l_chip,
+                           l_attr_chip_id));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, l_chip,
+                           l_attr_system_id));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG,                    l_perv,
+                           l_attr_pg));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,         l_perv,
+                           l_attr_chip_unit_pos));
+    l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_EQ_POS_OFFSET;
+
+    FAPI_TRY(getScom(l_chip, PU_OCB_OCI_QCSR_SCOM, l_qcsr));
+    FAPI_DBG("Working on cache[%d], good EXs in QCSR[%016llX]",
+             l_attr_chip_unit_pos, l_qcsr);
+
+    // -----------------------------
+    // Prepare to start cache clocks
+    // -----------------------------
+    // QCCR[0/4] EDRAM_ENABLE_DC
+    // QCCR[1/5] EDRAM_VWL_ENABLE_DC
+    // QCCR[2/6] L3_EX0/1_EDRAM_VROW_VBLH_ENABLE_DC
+    // QCCR[3/7] EDRAM_VPP_ENABLE_DC
+    // 0x0 -> 0x8 -> 0xC -> 0xE -> 0xF to turn on edram
+    // stagger EDRAM turn-on per EX (not both at same time)
+
+    l_region_clock = p9hcd::CLK_REGION_ALL_BUT_EX_ANEP_DPLL;
+    l_l2sync_clock = 0;
+    l_l2pscom_mask = 0;
+    l_l3pscom_mask = 0;
+
+    if (l_qcsr & BIT64(l_attr_chip_unit_pos << 1))
+    {
+        l_region_clock |= p9hcd::CLK_REGION_EX0_L2_L3_REFR;
+        l_l2sync_clock |= BIT64(36);
+        FAPI_DBG("Sequence EX0 EDRAM enables via QPPM_QCCR[0-3]");
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(0)));
+        FAPI_TRY(fapi2::delay(12000, 200));
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(1)));
+        FAPI_TRY(fapi2::delay(1000, 200));
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(2)));
+        FAPI_TRY(fapi2::delay(4000, 200));
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(3)));
+        FAPI_TRY(fapi2::delay(1000, 200));
+    }
+    else
+    {
+        l_l2pscom_mask |= (BIT64(2) | BIT64(10));
+        l_l3pscom_mask |= (BIT64(4) | BIT64(6) | BIT64(8));
+    }
+
+    if (l_qcsr & BIT64((l_attr_chip_unit_pos << 1) + 1))
+    {
+        l_region_clock |= p9hcd::CLK_REGION_EX1_L2_L3_REFR;
+        l_l2sync_clock |= BIT64(37);
+        FAPI_DBG("Sequence EX1 EDRAM enables via QPPM_QCCR[4-7]");
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(4)));
+        FAPI_TRY(fapi2::delay(12000, 200));
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(5)));
+        FAPI_TRY(fapi2::delay(1000, 200));
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(6)));
+        FAPI_TRY(fapi2::delay(4000, 200));
+        FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(7)));
+        FAPI_TRY(fapi2::delay(1000, 200));
+    }
+    else
+    {
+        l_l2pscom_mask |= (BIT64(3) | BIT64(11));
+        l_l3pscom_mask |= (BIT64(5) | BIT64(7) | BIT64(9));
+    }
+
+    FAPI_DBG("Assert cache EX1 ID bit2 via CPLT_CTRL0[6]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_OR, MASK_SET(6)));
+
+    FAPI_DBG("Set inop_align/wait/wait_cycles via OPCG_ALIGN[0-3,12-19,52-63]");
+    FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64));
+    l_data64.insertFromRight<0, 4>(0x5).
+    insertFromRight<12, 8>(0x0).
+    insertFromRight<52, 12>(0x10);
+    FAPI_TRY(putScom(i_target, EQ_OPCG_ALIGN, l_data64));
+
+    FAPI_DBG("Drop partial good fences via CPLT_CTRL1[4,5,6/7,8/9,10,11,12/13]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR,
+                     (l_region_clock | p9hcd::CLK_REGION_ANEP)));
+
+    FAPI_DBG("Drop vital fence via CPLT_CTRL1[3]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_CLEAR, MASK_SET(3)));
+
+    FAPI_DBG("Assert EX-L2 clock sync enables via QPPM_EXCGCR[36,37]");
+    FAPI_TRY(putScom(i_target, EQ_QPPM_EXCGCR_OR, l_l2sync_clock));
+
+    FAPI_DBG("Poll for EX-L2 clock sync dones via QPPM_QACSR[36,37]");
+    l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
+                CACHE_CLK_SYNC_TIMEOUT_IN_MS;
+
+    do
+    {
+        FAPI_TRY(getScom(i_target, EQ_QPPM_QACSR, l_data64));
+    }
+    while(((l_data64 & l_l2sync_clock) != l_l2sync_clock) &&
+          ((--l_timeout) != 0));
+
+    FAPI_ASSERT((l_timeout != 0),
+                fapi2::PMPROC_CACHECLKSYNC_TIMEOUT().set_EQPPMQACSR(l_data64),
+                "EX-L2 Clock Sync Timeout");
+    FAPI_DBG("EX-L2 clock sync done");
+
+    FAPI_DBG("Reset abstclk & syncclk muxsel(io_clk_sel) via CPLT_CTRL0[0:1]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_CLR(0, 2, 3)));
+
+    FAPI_DBG("Set fabric group ID[%x] chip ID[%x] system ID[%x]",
+             l_attr_group_id, l_attr_chip_id, l_attr_system_id);
+    FAPI_TRY(getScom(i_target, EQ_CPLT_CONF0, l_data64));
+    l_data64.insertFromRight<48, 4>(l_attr_group_id).
+    insertFromRight<52, 3>(l_attr_chip_id).
+    insertFromRight<56, 5>(l_attr_system_id);
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CONF0, l_data64));
+
+    // -------------------------------
+    // Align chiplets
+    // -------------------------------
+
+    FAPI_DBG("Assert flushmode_inhibit via CPLT_CTRL0[2]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_OR, MASK_SET(2)));
+
+    FAPI_DBG("Assert force_align via CPLT_CTRL0[3]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_OR, MASK_SET(3)));
+
+    FAPI_DBG("Set then unset clear_chiplet_is_aligned via SYNC_CONFIG[7]");
+    FAPI_TRY(getScom(i_target, EQ_SYNC_CONFIG, l_data64));
+    FAPI_TRY(putScom(i_target, EQ_SYNC_CONFIG, DATA_SET(7)));
+    FAPI_TRY(putScom(i_target, EQ_SYNC_CONFIG, DATA_UNSET(7)));
+
+    FAPI_TRY(fapi2::delay(
+                 CACHE_CLK_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE *
+                 p9hcd::CLK_PERIOD_250PS / 1000,
+                 CACHE_CLK_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE *
+                 p9hcd::SIM_CYCLE_4U4D));
+
+    FAPI_DBG("Poll for cache chiplet aligned");
+    l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
+                CACHE_CLK_START_TIMEOUT_IN_MS;
+
+    do
+    {
+        FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64));
+    }
+    while((l_data64.getBit<9>() != 1) && ((--l_timeout) != 0));
+
+    FAPI_ASSERT((l_timeout != 0),
+                fapi2::PMPROC_CACHECPLTALIGN_TIMEOUT()
+                .set_EQCPLTSTAT0(l_data64),
+                "Cache Chiplets Aligned Timeout");
+    FAPI_DBG("Cache chiplets aligned now");
+
+    FAPI_DBG("Drop force_align via CPLT_CTRL0[3]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_SET(3)));
+
+    // -------------------------------
+    // Start cache clocks
+    // -------------------------------
+
+    FAPI_DBG("Clear all bits prior start cache clocks via SCAN_REGION_TYPE");
+    FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO));
+
+    FAPI_DBG("Start cache clocks(all but anep+dpll) via CLK_REGION");
+    l_data64 = (p9hcd::CLK_START_CMD |
+                l_region_clock       |
+                p9hcd::CLK_THOLD_ALL);
+    FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64));
+
+    FAPI_DBG("Poll for cache clocks running via CPLT_STAT0[8]");
+    l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
+                CACHE_CLK_START_TIMEOUT_IN_MS;
+
+    do
+    {
+        FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64));
+    }
+    while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0));
+
+    FAPI_ASSERT((l_timeout != 0),
+                fapi2::PMPROC_CACHECLKSTART_TIMEOUT().set_EQCPLTSTAT(l_data64),
+                "Cache Clock Start Timeout");
+
+    FAPI_DBG("Check cache clocks running");
+    FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64));
+
+    FAPI_ASSERT(((l_data64 & l_region_clock) == 0),
+                fapi2::PMPROC_CACHECLKSTART_FAILED().set_EQCLKSTAT(l_data64),
+                "Cache Clock Start Failed");
+    FAPI_DBG("Cache clocks running now");
+
+    // -------------------------------
+    // Cleaning up
+    // -------------------------------
+
+    if (((~l_attr_pg) & BITS32(4, 11)) && l_attr_system_ipl_phase != 4)
+    {
+        FAPI_DBG("Drop chiplet fence via NET_CTRL0[18]");
+        FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WAND, MASK_UNSET(18)));
+    }
+
+    /// @todo ignore xstop checkstop in sim, review for lab
+    /*
+    FAPI_DBG("Check the Global Checkstop FIR");
+    FAPI_TRY(getScom(i_target, EQ_XFIR, l_data64));
+    FAPI_ASSERT(((l_data64 & BITS64(0, 27)) != 0),
+                fapi2::PMPROC_CACHE_XSTOP().set_EQXFIR(l_data64),
+                "Cache Chiplet Checkstop");
+    */
+
+    FAPI_DBG("Drop flushmode_inhibit via CPLT_CTRL0[2]");
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_SET(2)));
+
+    FAPI_DBG("Drop partial good and assert partial bad L2/L3 pscom masks");
+    l_data64 = (l_l2pscom_mask | l_l3pscom_mask);
+    FAPI_TRY(putScom(i_target, EQ_RING_FENCE_MASK_LATCH_REG, l_data64));
+
+fapi_try_exit:
+
+    FAPI_INF("<<p9_hcd_cache_startclocks");
+    return fapi2::current_err;
+}
+
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H
new file mode 100644
index 00000000..d0ad61d6
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_cache_startclocks.H
+/// @brief Quad Clock Start
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CACHE_STARTCLOCKS_H__
+#define __P9_HCD_CACHE_STARTCLOCKS_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_cache_startclocks_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_cache_startclocks_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+extern "C"
+{
+
+/// @brief Quad Clock Start
+/// @param [in] i_target TARGET_TYPE_EQ target
+/// @return FAPI2_RC_SUCCESS if success, else error code
+    fapi2::ReturnCode
+    p9_hcd_cache_startclocks(
+        const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target);
+
+}
+
+#endif  // __P9_HCD_CACHE_STARTCLOCKS_H__
diff --git a/src/import/chips/p9/procedures/hwp/core/Makefile b/src/import/chips/p9/procedures/hwp/core/Makefile
new file mode 100644
index 00000000..15ace37d
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/Makefile
@@ -0,0 +1,55 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/hwp/core/Makefile $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+# This Makefile compiles all of the core hardware procedure code. See the
+# "corehcdfiles.mk" file in this directory.
+
+#all generated files from this makefile will end up in obj/cache
+export SUB_OBJDIR = /core
+
+GCC-CFLAGS += -mlongcall
+include img_defs.mk
+include corehcdfiles.mk
+
+
+OBJS := $(addprefix $(OBJDIR)/, $(CORE_OBJECTS))
+
+libcore.a: core
+	$(AR) crs $(OBJDIR)/libcore.a $(OBJDIR)/*.o
+
+.PHONY: clean core
+core: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+clean:
+	rm -fr $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d)
+endif
diff --git a/src/import/chips/p9/procedures/hwp/core/corehcdfiles.mk b/src/import/chips/p9/procedures/hwp/core/corehcdfiles.mk
new file mode 100644
index 00000000..b7c2abcc
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/corehcdfiles.mk
@@ -0,0 +1,56 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/hwp/core/corehcdfiles.mk $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file corehcdfiles.mk
+#
+#  @brief mk for including core hcode object files
+#
+##########################################################################
+# Object Files
+##########################################################################
+
+CORE-CPP-SOURCES += p9_hcd_core_arrayinit.C
+CORE-CPP-SOURCES += p9_hcd_core_chiplet_init.C
+CORE-CPP-SOURCES += p9_hcd_core_chiplet_reset.C
+CORE-CPP-SOURCES += p9_hcd_core_gptr_time_initf.C
+CORE-CPP-SOURCES += p9_hcd_core_initf.C
+CORE-CPP-SOURCES += p9_hcd_core_occ_runtime_scom.C
+CORE-CPP-SOURCES += p9_hcd_core_pcb_arb.C
+CORE-CPP-SOURCES += p9_hcd_core_poweron.C
+CORE-CPP-SOURCES += p9_hcd_core_ras_runtime_scom.C
+CORE-CPP-SOURCES += p9_hcd_core_repair_initf.C
+CORE-CPP-SOURCES += p9_hcd_core_runinit.C
+CORE-CPP-SOURCES += p9_hcd_core_scomcust.C
+CORE-CPP-SOURCES += p9_hcd_core_scominit.C
+CORE-CPP-SOURCES += p9_hcd_core_startclocks.C
+CORE-CPP-SOURCES += p9_thread_control.C
+CORE-CPP-SOURCES += p9_sbe_instruct_start.C
+
+CORE-C-SOURCES   +=
+CORE-S-SOURCES   +=
+
+CORE_OBJECTS     += $(CORE-CPP-SOURCES:.C=.o)
+CORE_OBJECTS     += $(CORE-C-SOURCES:.c=.o)
+CORE_OBJECTS     += $(CORE-S-SOURCES:.S=.o)
+
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core.H
new file mode 100644
index 00000000..1c766fb3
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core.H
@@ -0,0 +1,53 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core.H $           */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_hcd_core.H
+/// @brief Core Chiplet Procedure Includes
+///
+/// *HWP HWP Owner   : David Du      <daviddu@us.ibm.com>
+/// *HWP FW Owner    : Reshmi Nair   <resnair5@in.ibm.com>
+/// *HWP Team        : PM
+/// *HWP Consumed by : SBE:CME
+/// *HWP Level       : 2
+///
+
+#ifndef __P9_HCD_CORE_H__
+#define __P9_HCD_CORE_H__
+
+#include <p9_hcd_core_arrayinit.H>
+#include <p9_hcd_core_chiplet_init.H>
+#include <p9_hcd_core_chiplet_reset.H>
+#include <p9_hcd_core_gptr_time_initf.H>
+#include <p9_hcd_core_initf.H>
+#include <p9_hcd_core_occ_runtime_scom.H>
+#include <p9_hcd_core_pcb_arb.H>
+#include <p9_hcd_core_poweron.H>
+#include <p9_hcd_core_ras_runtime_scom.H>
+#include <p9_hcd_core_repair_initf.H>
+#include <p9_hcd_core_scomcust.H>
+#include <p9_hcd_core_scominit.H>
+#include <p9_hcd_core_startclocks.H>
+
+#endif  // __P9_HCD_CORE_H__
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C
new file mode 100644
index 00000000..0706e244
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C
@@ -0,0 +1,123 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_arrayinit.C
+/// @brief Core Initialize arrays
+///
+/// Procedure Summary:
+///   Use ABIST engine to zero out all arrays
+///   Upon completion, scan0 flush all rings except Vital,Repair,GPTR,and TIME
+
+// *HWP HWP Owner          : David Du      <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still    <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <p9_quad_scom_addresses.H>
+#include <p9_perv_sbe_cmn.H>
+#include <p9_hcd_common.H>
+#include "p9_hcd_core_arrayinit.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions
+//------------------------------------------------------------------------------
+
+enum P9_HCD_CORE_ARRAYINIT_Private_Constants
+{
+    REGIONS_EXCEPT_VITAL = 0x7FF,
+    LOOP_COUNTER = 0x0000000000042FFF,
+    SELECT_SRAM = 0x1,
+    SELECT_EDRAM = 0x0,
+    START_ABIST_MATCH_VALUE = 0x0000000F00000000
+};
+
+//------------------------------------------------------------------------------
+// Procedure: Core Initialize arrays
+//------------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_core_arrayinit(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+{
+    FAPI_INF(">>p9_hcd_core_arrayinit");
+    fapi2::buffer<uint64_t>                     l_data64;
+
+#if not defined(P9_HCD_STOP_SKIP_FLUSH) || not defined(P9_HCD_STOP_SKIP_ARRAYINIT)
+    fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv =
+        i_target.getParent<fapi2::TARGET_TYPE_PERV>();
+#endif
+
+    /// @todo add DD1 attribute control
+    FAPI_DBG("DD1 only: set sdis_n(flushing LCBES condition workaround");
+    FAPI_TRY(putScom(i_target, C_CPLT_CONF0_OR, MASK_SET(34)));
+
+#ifndef P9_HCD_STOP_SKIP_ARRAYINIT
+
+    FAPI_DBG("Arrayinit all regions except vital");
+    FAPI_TRY(p9_perv_sbe_cmn_array_init_module(l_perv,
+             REGIONS_EXCEPT_VITAL,
+             LOOP_COUNTER,
+             SELECT_SRAM,
+             SELECT_EDRAM,
+             START_ABIST_MATCH_VALUE));
+
+#endif
+
+#ifndef P9_HCD_STOP_SKIP_FLUSH
+
+    //--------------------------------------------
+    // perform scan0 module for pervasive chiplet
+    //--------------------------------------------
+    // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest
+    // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has
+    // all stumps less than 8191, the loop can be removed.
+
+    FAPI_DBG("Scan0 region:all_but_pll type:all_but_gptr_repr_time rings");
+
+    for(uint32_t l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++)
+        FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
+                                              p9hcd::SCAN0_REGION_ALL_BUT_PLL,
+                                              p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME));
+
+#endif
+
+    /// @todo add DD1 attribute control
+    FAPI_DBG("DD1 only: reset sdis_n(flushing LCBES condition workaround");
+    FAPI_TRY(putScom(i_target, C_CPLT_CONF0_CLEAR, MASK_SET(34)));
+
+//#if not defined(P9_HCD_STOP_SKIP_FLUSH) || not defined(P9_HCD_STOP_SKIP_ARRAYINIT)
+fapi_try_exit:
+//#endif
+
+    FAPI_INF("<<p9_hcd_core_arrayinit");
+    return fapi2::current_err;
+}
+
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.H
new file mode 100644
index 00000000..dde880ee
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.H
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_arrayinit.H
+/// @brief Core Initialize arrays
+///
+
+// *HWP HWP Owner          : David Du      <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still    <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CORE_ARRAYINIT_H__
+#define __P9_HCD_CORE_ARRAYINIT_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_core_arrayinit_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_core_arrayinit_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
+
+extern "C"
+{
+
+/// @brief Core Initialize arrays
+///
+/// @param [in] i_target TARGET_TYPE_CORE target
+///
+/// @attr
+/// @attritem NONE
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_core_arrayinit(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+
+}
+
+#endif  // __P9_HCD_CORE_ARRAYINIT_H__
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.C
new file mode 100644
index 00000000..9007a7f8
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.C
@@ -0,0 +1,94 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_chiplet_init.C
+/// @brief Core Flush/Initialize
+///
+/// Procedure Summary:
+///   Switch the core glitchless mux to allow DPLL clocks on the clock grid
+///   Clocking:
+///    - setup controls based on DPLL frequency
+///    - assert PM sync_enable (4x core, 2 x L2),
+///      DCCs and SkewAdjust starts aligning clocks
+///   Scan0 flush all chiplet rings except VITAL, GPTR and TIME
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <p9_quad_scom_addresses.H>
+#include <p9_perv_sbe_cmn.H>
+#include <p9_hcd_common.H>
+#include "p9_hcd_core_chiplet_init.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Procedure: Core Flush/Initialize
+//------------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_core_chiplet_init(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+{
+    FAPI_INF(">>p9_hcd_core_chiplet_init");
+    /*
+    #ifndef P9_HCD_STOP_SKIP_FLUSH
+        //--------------------------------------------
+        // perform scan0 module for pervasive chiplet
+        //--------------------------------------------
+        // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest
+        // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has
+        // all stumps less than 8191, the loop can be removed.
+
+        fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv =
+            i_target.getParent<fapi2::TARGET_TYPE_PERV>();
+
+        FAPI_DBG("Scan0 region:all_but_vital type:all_but_gptr_repr_time rings");
+
+        for(uint32_t l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++)
+            FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
+                                                  p9hcd::SCAN0_REGION_PERV_CORE,
+                                                  p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME));
+
+    fapi_try_exit:
+
+    #endif
+    */
+    FAPI_INF("<<p9_hcd_core_chiplet_init");
+    return fapi2::current_err;
+}
+
+
+
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.H
new file mode 100644
index 00000000..c86b128c
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_chiplet_init.H
+/// @brief Core Flush/Initialize
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CORE_CHIPLET_INIT_H__
+#define __P9_HCD_CORE_CHIPLET_INIT_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_core_chiplet_init_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_core_chiplet_init_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
+
+extern "C"
+{
+
+/// @brief Core Flush/Initialize
+/// @param [in] i_target TARGET_TYPE_CORE target
+/// @return FAPI2_RC_SUCCESS if success, else error code
+    fapi2::ReturnCode
+    p9_hcd_core_chiplet_init(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+
+}
+
+#endif  // __P9_HCD_CORE_CHIPLET_INIT_H__
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C
new file mode 100644
index 00000000..c3bd9567
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C
@@ -0,0 +1,176 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_chiplet_reset.C
+/// @brief Core Chiplet Reset
+///
+/// Procedure Summary:
+///   Reset core chiplet logic
+///     (TODO: check with Andreas on the effect of a CME based Endpoint reset
+///            relative to the CorePPM path)
+///   Clocking:
+///    - setup cache sector buffer strength,
+///      pulse mode and pulsed mode enable values
+///      (attribute dependency Nimbus/Cumulus)
+///    - Drop glsmux async reset
+///   Scan0 flush entire core chiplet
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <p9_quad_scom_addresses.H>
+#include <p9_perv_sbe_cmn.H>
+#include <p9_hcd_common.H>
+#include "p9_hcd_core_chiplet_reset.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions
+//------------------------------------------------------------------------------
+
+enum P9_HCD_CORE_CHIPLET_RESET_CONSTANTS
+{
+    // (1)PCB_EP_RESET
+    // (2)CLK_ASYNC_RESET
+    // (3)PLL_TEST_EN
+    // (4)PLLRST
+    // (5)PLLBYP
+    // (11)EDIS
+    // (12)VITL_MPW1
+    // (13)VITL_MPW2
+    // (14)VITL_MPW3
+    // (16)VITL_THOLD
+    // (18)FENCE_EN
+    // (22)FUNC_CLKSEL
+    // (25)PCB_FENCE
+    // (26)LVLTRANS_FENCE
+    C_NET_CTRL0_INIT_VECTOR = (BIT64(1) | BITS64(3, 3) | BITS64(11, 4) |
+                               BIT64(16) | BIT64(18) | BIT64(22) | BITS64(25, 2)),
+    CORE_GLSMUX_RESET_DELAY_CORE_CYCLES = 200
+};
+
+//------------------------------------------------------------------------------
+// Procedure: Core Chiplet Reset
+//------------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_core_chiplet_reset(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+{
+    FAPI_INF(">>p9_hcd_core_chiplet_reset");
+    fapi2::buffer<uint64_t> l_data64;
+
+    //--------------------------
+    // Reset core chiplet logic
+    //--------------------------
+    // If there is an unused, powered-off core chiplet which needs to be
+    // configured in the following steps to setup the PCB endpoint.
+
+    FAPI_DBG("Init NET_CTRL0[1,3-5,11-14,16,18,22,25,26],step needed for hotplug");
+    l_data64 = C_NET_CTRL0_INIT_VECTOR;
+    FAPI_TRY(putScom(i_target, C_NET_CTRL0_WOR, l_data64));
+    l_data64 |= BIT64(2); // make sure bit 2 is untouched
+    FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, l_data64));
+
+    FAPI_DBG("Flip core glsmux to refclk via PPM_CGCR[3]");
+    FAPI_TRY(putScom(i_target, C_PPM_CGCR, MASK_SET(0)));
+
+    FAPI_DBG("Assert core progdly and DCC bypass via NET_CTRL1[1,2]");
+    FAPI_TRY(putScom(i_target, C_NET_CTRL1_WOR, MASK_OR(1, 2, 3)));
+
+    FAPI_DBG("Drop vital thold via NET_CTRL0[16]");
+    FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(16)));
+
+    /// @todo optional setup sector buffer strength, pulse mode and pulsed mode enable
+
+    FAPI_DBG("Drop core glsmux reset via PPM_CGCR[0]");
+    FAPI_TRY(putScom(i_target, C_PPM_CGCR, 0));
+
+    FAPI_TRY(fapi2::delay(
+                 CORE_GLSMUX_RESET_DELAY_CORE_CYCLES * p9hcd::CLK_PERIOD_250PS / 1000,
+                 CORE_GLSMUX_RESET_DELAY_CORE_CYCLES * p9hcd::SIM_CYCLE_4U4D));
+
+    FAPI_DBG("Flip core glsmux to DPLL via PPM_CGCR[3]");
+    FAPI_TRY(putScom(i_target, C_PPM_CGCR, MASK_SET(3)));
+
+    FAPI_DBG("Assert chiplet enable via NET_CTRL0[0]");
+    FAPI_TRY(putScom(i_target, C_NET_CTRL0_WOR, MASK_SET(0)));
+
+    FAPI_DBG("Drop PCB endpoint reset via NET_CTRL0[1]");
+    FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(1)));
+
+    FAPI_DBG("Drop chiplet electrical fence via NET_CTRL0[26]");
+    FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(26)));
+
+    FAPI_DBG("Drop PCB fence via NET_CTRL0[25]");
+    FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(25)));
+
+#ifndef P9_HCD_STOP_SKIP_FLUSH
+    //--------------------------------------------
+    // perform scan0 module for pervasive chiplet
+    //--------------------------------------------
+    // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest
+    // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has
+    // all stumps less than 8191, the loop can be removed.
+
+    // Putting in block to avoid c++ crosses initialization compile error
+    {
+        uint32_t l_loop;
+        fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv =
+            i_target.getParent<fapi2::TARGET_TYPE_PERV>();
+
+        FAPI_DBG("Scan0 region:all_but_vital type:gptr_repr_time rings");
+
+        for(l_loop = 0; l_loop < P9_HCD_SCAN_GPTR_REPEAT; l_loop++)
+            FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
+                                                  p9hcd::SCAN0_REGION_ALL,
+                                                  p9hcd::SCAN0_TYPE_GPTR_REPR_TIME));
+
+        FAPI_DBG("Scan0 region:all_but_vital type:all_but_gptr_repr_time rings");
+
+        for(l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++)
+            FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
+                                                  p9hcd::SCAN0_REGION_ALL,
+                                                  p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME));
+    }
+#endif
+
+    /// @todo add VDM_ENABLE attribute control
+    FAPI_DBG("Assert vdm enable via CPPM_VDMCR[0]");
+    FAPI_TRY(putScom(i_target, C_PPM_VDMCR_OR, MASK_SET(0)));
+
+fapi_try_exit:
+
+    FAPI_INF("<<p9_hcd_core_chiplet_reset");
+    return fapi2::current_err;
+}
+
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.H
new file mode 100644
index 00000000..9db24521
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_chiplet_reset.H
+/// @brief Core Chiplet Reset
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CORE_CHIPLET_RESET_H__
+#define __P9_HCD_CORE_CHIPLET_RESET_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_core_chiplet_reset_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_core_chiplet_reset_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
+
+extern "C"
+{
+
+/// @brief Core Chiplet Reset
+/// @param [in] i_target TARGET_TYPE_CORE target
+/// @return FAPI2_RC_SUCCESS if success, else error code
+    fapi2::ReturnCode
+    p9_hcd_core_chiplet_reset(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+
+}
+
+#endif  // __P9_HCD_CORE_CHIPLET_RESET_H__
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.C
new file mode 100644
index 00000000..fa147a3d
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.C
@@ -0,0 +1,81 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_gptr_time_initf.C
+/// @brief Load Core GPTR and Time rings
+///
+/// Procedure Summary:
+///   initfiles in procedure defined on VBU ENGD wiki (TODO add link)
+///     to produce #G VPD contents
+///   Check for the presence of core override GPTR ring from image
+///     (this is new for P9)
+///   if found, apply;  if not, apply core GPTR from image
+///   Check for the presence of core override TIME ring from image;
+///   if found, apply;  if not, apply core base TIME from image
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+
+#include <p9_ring_id.h>
+#include "p9_hcd_core_gptr_time_initf.H"
+
+//-----------------------------------------------------------------------------
+// Constant Definitions
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Procedure: Load Core GPTR and Time rings
+//-----------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_core_gptr_time_initf(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+{
+    FAPI_INF(">>p9_hcd_core_gptr_time_initf");
+
+    FAPI_DBG("Scan ec_gptr ring");
+    FAPI_TRY(fapi2::putRing(i_target, ec_gptr,
+                            fapi2::RING_MODE_HEADER_CHECK),
+             "Error from putRing (ec_gptr)");
+
+    FAPI_DBG("Scan ec_time ring");
+    FAPI_TRY(fapi2::putRing(i_target, ec_time,
+                            fapi2::RING_MODE_HEADER_CHECK),
+             "Error from putRing (ec_time)");
+
+fapi_try_exit:
+
+    FAPI_INF("<<p9_hcd_core_gptr_time_initf");
+    return fapi2::current_err;
+}
+
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.H
new file mode 100644
index 00000000..22c88c3f
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.H
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_gptr_time_initf.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_gptr_time_initf.H
+/// @brief Load Core GPTR and Time rings
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CORE_GPTR_TIME_INIT_H__
+#define __P9_HCD_CORE_GPTR_TIME_INIT_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_core_gptr_time_initf_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_core_gptr_time_initf_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
+
+extern "C"
+{
+
+/// @brief Load Core GPTR and Time rings
+///
+/// @param [in] i_target TARGET_TYPE_CORE target
+/// @attr
+/// @attritem ATTR_CORE_GPTR_TIME_RING - EC target, uint32
+///               pointer to RS4 content<br>
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_core_gptr_time_initf(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+
+}
+
+#endif  // __P9_HCD_CORE_GPTR_TIME_INIT_H__
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.C
new file mode 100644
index 00000000..86e72aac
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.C
@@ -0,0 +1,72 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.C $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_initf.C
+/// @brief Core scan init
+///
+/// Procedure Summary:
+///   Initfiles in procedure defined on VBU ENGD wiki (TODO add link)
+///   Check for the presence of core FUNC override rings from image;
+///   if found, apply;  if not, apply core base FUNC rings from image
+///   Note:  FASTINIT ring (eg CMSK ring) is setup at this point to limit the
+///   stumps that participate in FUNC ring scanning (this is new for P9).
+///   (TODO to make sure the image build support is in place)
+///   Note : if in fused mode, both core rings will be initialized to the same
+///   values via multicast scans
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+
+#include "p9_hcd_core_initf.H"
+
+//-----------------------------------------------------------------------------
+// Procedure: Core scan init
+//-----------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_core_initf(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+{
+    FAPI_INF(">>p9_hcd_core_initf");
+
+    FAPI_DBG("Scan ec_func ring");
+    FAPI_TRY(putRing(i_target, ec_func),
+             "Error from putRing (ec_func)");
+    FAPI_DBG("Scan ec_mode ring");
+    FAPI_TRY(putRing(i_target, ec_mode),
+             "Error from putRing (ec_mode)");
+
+fapi_try_exit:
+    FAPI_INF("<<p9_hcd_core_initf");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.H
new file mode 100644
index 00000000..accbf0ea
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.H
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_initf.H $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_initf.H
+/// @brief Core scan init
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CORE_INITF_H__
+#define __P9_HCD_CORE_INITF_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_core_initf_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_core_initf_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
+
+extern "C"
+{
+
+/// @brief Core scan init
+///
+/// @param [in] i_target TARGET_TYPE_CORE target
+/// @attr
+/// @attritem ATTR_CORE_FUNC_RING - EC target, uint32
+///               pointer to RS4 content<br>
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_core_initf(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+
+}
+
+#endif  // __P9_HCD_CORE_INITF_H__
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.C
new file mode 100644
index 00000000..9211d7fc
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.C
@@ -0,0 +1,94 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_occ_runtime_scom.C
+/// @brief Core OCC runtime SCOMS
+///
+/// *HWP HWP Owner   : David Du      <daviddu@us.ibm.com>
+/// *HWP FW Owner    : Reshmi Nair   <resnair5@in.ibm.com>
+/// *HWP Team        : PM
+/// *HWP Consumed by : SBE:CME
+/// *HWP Level       : 1
+///
+/// Procedure Summary:
+///   Run-time updates from OCC code that are put  somewhere TBD
+///   (TODO . revisit with OCC FW team)
+///   OCC FW sets up value in the TBD SCOM section
+///   This was not leverage in P8 with the demise of CPMs
+///   Placeholder at this point
+///
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+#include <fapi2.H>
+//#include <common_scom_addresses.H>
+//will be replaced with real scom address header file
+#include "p9_hcd_core_occ_runtime_scom.H"
+
+//-----------------------------------------------------------------------------
+// Constant Definitions
+//-----------------------------------------------------------------------------
+#define host_runtime_scom 0
+
+//-----------------------------------------------------------------------------
+// Procedure: Core OCC runtime SCOMS
+//-----------------------------------------------------------------------------
+
+extern "C"
+{
+
+    fapi2::ReturnCode
+    p9_hcd_core_occ_runtime_scom(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+    {
+
+#if 0
+
+        fapi2::buffer<uint64_t> data;
+
+        // Run the SCOM sequence if the SCOM procedure is defined
+        // -   la      A0, occ_runtime_scom
+        // -   ld      D0, 0, A0
+        // -   braz    D0, 1f
+        //FAPI_INF("Launching OCC Runtime SCOM routine")
+        // -   bsrd    D0
+        // -   1:
+
+        return fapi2::FAPI2_RC_SUCCESS;
+
+        FAPI_CLEANUP();
+        return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
+
+#endif
+
+        return fapi2::FAPI2_RC_SUCCESS;
+
+    } // Procedure
+
+
+} // extern C
+
+
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.H
new file mode 100644
index 00000000..7dad1c6e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.H
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_occ_runtime_scom.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_occ_runtime_scom.H
+/// @brief Core OCC runtime SCOMS
+///
+/// *HWP HWP Owner   : David Du      <daviddu@us.ibm.com>
+/// *HWP FW Owner    : Reshmi Nair   <resnair5@in.ibm.com>
+/// *HWP Team        : PM
+/// *HWP Consumed by : SBE:CME
+/// *HWP Level       : 1
+///
+
+
+#ifndef __P9_HCD_CORE_OCC_RUNTIME_SCOM_H__
+#define __P9_HCD_CORE_OCC_RUNTIME_SCOM_H__
+
+extern "C"
+{
+
+/// @typedef p9_hcd_core_occ_runtime_scom_FP_t
+/// function pointer typedef definition for HWP call support
+    typedef fapi2::ReturnCode (*p9_hcd_core_occ_runtime_scom_FP_t) (
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
+
+
+/// @brief Core OCC runtime SCOMS
+///
+/// @param [in] i_target TARGET_TYPE_CORE target
+///
+/// @attr
+/// @attritem ATTR_CORE_OCC_SCOM_LOC - EC target, uint32
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_core_occ_runtime_scom(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+
+
+} // extern C
+
+#endif  // __P9_HCD_CORE_OCC_RUNTIME_SCOM_H__
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.C
new file mode 100644
index 00000000..729f98b7
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.C
@@ -0,0 +1,115 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.C $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_pcb_arb.C
+/// @brief Core Chiplet PCB Arbitration
+///
+/// Procedure Summary:
+///   If CME,
+///     1.Request PCB Mux, via write to PCB_MUX_REQ_C0 @ CCSCR_OR
+///       - setBit(5) @ CME_LOCAL_CORE_STOP_CONTROL_REGISTER_OR_0510
+///     2.Poll for PCB Mux grant, via read from
+///       Polled Timeout: ns
+///       - getBit() @
+///   Else (SBE),
+///     Nop (as the CME is not running in bringing up the first Core)
+///
+
+// *HWP HWP Owner          : David Du      <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still    <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+#include <p9_quad_scom_addresses.H>
+#include <p9_hcd_common.H>
+#include "p9_hcd_core_pcb_arb.H"
+
+//-----------------------------------------------------------------------------
+// Constant Definitions: Core Chiplet PCB Arbitration
+//-----------------------------------------------------------------------------
+
+
+fapi2::ReturnCode
+p9_hcd_core_pcb_arb(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target,
+    const p9hcd::P9_HCD_CME_CORE_MASKS i_core_mask,
+    const p9hcd::P9_HCD_PCB_ARBITER_CTRL i_request)
+{
+    FAPI_INF(">>p9_hcd_core_pcb_arb: Core[%d] Req[%d]", i_core_mask, i_request);
+
+#ifdef P9_HCD_CME_BUILD
+
+    FAPI_DBG("Request or Release the PCB Arbiter");
+    out32((i_request ? CME_LCL_SICR_OR : CME_LCL_SICR_CLR),
+          (i_core_mask << SHIFT32(11)));
+
+    FAPI_DBG("Poll for PCB Arbiter Granted");
+    uint32_t l_sisr;
+
+    do
+    {
+        l_sisr = (in32(CME_LCL_SISR) >> SHIFT32(11));
+
+        if((  i_request  && ((i_core_mask &   l_sisr)  == i_core_mask)) ||
+           ((!i_request) && ((i_core_mask & (~l_sisr)) == i_core_mask)))
+        {
+            break;
+        }
+    }
+    while(1);
+
+#else
+
+    FAPI_DBG("Check for PCB Arbiter Granted to Core");
+
+    /// @todo require core to cme target conversion
+    /*
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_TRY(getScom(i_target, EX_0_CME_LCL_SISR_SCOM, l_data64));
+
+    FAPI_ASSERT(((l_data64 & (i_core_mask << SHIFT64(11))) !=
+                             (i_core_mask << SHIFT64(11))),
+                fapi2::PMPROC_COREPCBARB_GRANTCME().set_CMESISR(l_data64),
+                "PCB Arbiter is Granted to CME");
+    */
+    FAPI_DBG("PCB Arbiter is Granted to Core");
+
+    /// @todo MPIPL: if check grant to cme, consider to overide it back to core
+
+//fapi_try_exit:
+
+#endif
+
+    FAPI_INF("<<p9_hcd_core_pcb_arb");
+
+    return fapi2::current_err;
+}
+
+
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.H
new file mode 100644
index 00000000..f3bfad93
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.H
@@ -0,0 +1,68 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_pcb_arb.H $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_pcb_arb.H
+/// @brief Core Chiplet PCB Arbitration
+///
+
+// *HWP HWP Owner          : David Du      <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still    <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CORE_PCB_ARB_H__
+#define __P9_HCD_CORE_PCB_ARB_H__
+
+#include <fapi2.H>
+#include <p9_hcd_common.H>
+
+/// @typedef p9_hcd_core_pcb_arb_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_core_pcb_arb_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&,
+    const p9hcd::P9_HCD_CME_CORE_MASKS i_core_mask,
+    const p9hcd::P9_HCD_PCB_ARBITER_CTRL i_request);
+
+extern "C"
+{
+
+/// @brief Core Chiplet PCB Arbitration
+///
+/// @param [in] i_target TARGET_TYPE_CORE target
+/// @attr
+/// @attritem NONE
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_core_pcb_arb(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target,
+        const p9hcd::P9_HCD_CME_CORE_MASKS i_core_mask,
+        const p9hcd::P9_HCD_PCB_ARBITER_CTRL i_request);
+
+}
+
+#endif  // __P9_HCD_CORE_PCB_ARB_H__
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C
new file mode 100644
index 00000000..5e66f673
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C
@@ -0,0 +1,88 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.C $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_poweron.C
+/// @brief Core Chiplet Power-on
+///
+/// Procedure Summary:
+///   Set glsmux async reset
+///   Command the core PFET controller to power-on, via putscom to CPPM
+///   Check for valid power on completion, via getscom from CPPM
+///     Polled Timeout:  100us
+
+// *HWP HWP Owner          : David Du          <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still        <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S     <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+
+#include <p9_quad_scom_addresses.H>
+#include <p9_hcd_common.H>
+#include <p9_common_poweronoff.H>
+#include <p9_common_poweronoff.C>
+#include "p9_hcd_core_poweron.H"
+
+//-----------------------------------------------------------------------------
+// Constant Definitions
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Procedure: Core Chiplet Power-on
+//-----------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_core_poweron(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+{
+    FAPI_INF(">>p9_hcd_core_poweron");
+    fapi2::buffer<uint64_t> l_data64;
+
+    //-------------------------
+    // Prepare to power on core
+    //-------------------------
+
+    FAPI_DBG("Drop chiplet enable via NET_CTRL0[0]");
+    FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(0)));
+
+    FAPI_DBG("Assert core glsmux reset via PPM_CGCR[0]");
+    FAPI_TRY(putScom(i_target, C_PPM_CGCR, MASK_SET(0)));
+
+    //----------------------
+    // Power on core chiplet
+    //----------------------
+
+    FAPI_DBG("Power on core chiplet");
+    FAPI_TRY(p9_common_poweronoff<fapi2::TARGET_TYPE_CORE>(i_target, p9power::POWER_ON_VDD));
+
+fapi_try_exit:
+
+    FAPI_INF("<<p9_hcd_core_poweron");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.H
new file mode 100644
index 00000000..91b73cf9
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.H
@@ -0,0 +1,63 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_poweron.H $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_poweron.H
+/// @brief Core Chiplet Power-on
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CORE_POWERON_H__
+#define __P9_HCD_CORE_POWERON_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_core_poweron_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_core_poweron_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
+
+extern "C"
+{
+/// @brief Core Chiplet Power-on
+///
+/// @param [in] i_target    TARGET_TYPE_CORE target
+/// @param [in] i_operation ENUM(ON,OFF)
+///
+/// @attr
+/// @attritem ATTR_PFET_*
+///
+/// @retval FAPI2_RC_SUCCESS if success, else error code
+    fapi2::ReturnCode
+    p9_hcd_core_poweron(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+}
+
+#endif  // __P9_HCD_CORE_POWERON_H__
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.C
new file mode 100644
index 00000000..6ad7100f
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.C
@@ -0,0 +1,165 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_ras_runtime_scom.C
+/// @brief FSP/Host run-time SCOMS
+///
+/// *HWP HWP Owner   : David Du      <daviddu@us.ibm.com>
+/// *HWP FW Owner    : Reshmi Nair   <resnair5@in.ibm.com>
+/// *HWP Team        : PM
+/// *HWP Consumed by : SBE:CME
+/// *HWP Level       : 1
+///
+/// Procedure Summary:
+///   Run-time updates from FSP based PRD, etc that are put on the core image
+///   by STOP API calls
+///   Dynamically built pointer where a NULL is checked before execution
+///   If NULL (the SBE case), return
+///   Else call the function at the pointer;
+///   pointer is filled in by STOP image build
+///   Run-time updates from Host code that are put on the core image by
+///   STOP API calls
+///     Restore Hypervisor, Host PRD, etc. SCOMs
+///
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+#include <fapi2.H>
+//#include <common_scom_addresses.H>
+//will be replaced with real scom address header file
+#include "p9_hcd_core_ras_runtime_scom.H"
+
+//-----------------------------------------------------------------------------
+// Constant Definitions
+//-----------------------------------------------------------------------------
+#define host_runtime_scom 0
+
+//-----------------------------------------------------------------------------
+// Procedure: FSP/Host run-time SCOMS
+//-----------------------------------------------------------------------------
+
+extern "C"
+{
+
+    fapi2::ReturnCode
+    p9_hcd_core_ras_runtime_scom(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+    {
+
+#if 0
+        fapi2::buffer<uint64_t> data;
+
+        // Run the SCOM sequence if the SCOM procedure is defined
+        // -   la      A0, sp_runtime_scom
+        // -   ld      D0, 0, A0
+        // -   braz    D0, 1f
+        //FAPI_INF("Launching SP Runtime SCOM routine")
+        // -   bsrd    D0
+        // -   1:
+        //
+
+        // Run the SCOM sequence if the SCOM procedure is defined.
+        // -   la      A0, host_runtime_scom
+        // -   ld      D1, 0, A0
+        // -   braz    D1, 1f
+
+        // Prep P1
+        // -   setp1_mcreadand D0
+#if 0
+        // Disable the AISS to allow the override
+        // -   ld      D0, EX_OHA_MODE_REG_RWx1002000D, P1
+        // -   andi    D0, D0, ~(BIT(1))
+        // - std     D0, EX_OHA_MODE_REG_RWx1002000D, P0
+        // Drop PSCOM fence to allow SCOM and set pm_wake-up to PC to accepts
+        // RAMs (SCOMs actually) in the IPL "Nap" state
+        // -   ld      D0, EX_OHA_AISS_IO_REG_0x10020014, P1
+        // -   ori     D0, D0, (BIT(15))
+        // -   andi    D0, D0, ~(BIT(21))
+        // -   std     D0, EX_OHA_AISS_IO_REG_0x10020014, P0
+#endif
+        // Branch to sub_slw_runtime_scom()
+        FAPI_INF("Launching Host Runtime SCOM routine")
+        // -   bsrd    D1
+
+        // Prep P1
+        // -   setp1_mcreadand D0
+#if 0
+        // Clear regular wake-up and restore PSCOM fence in OHA
+        // These were established in p9_sbe_ex_scominit.S
+        // -   ld      D0, EX_OHA_AISS_IO_REG_0x10020014, P1
+        // -   andi    D0, D0, ~(BIT(15))
+        // -   ori     D0, D0, BIT(21)
+        // -   std     D0, EX_OHA_AISS_IO_REG_0x10020014, P0
+        // Enable the AISS to allow further operation
+        // -   ld      D0, EX_OHA_MODE_REG_RWx1002000D, P1
+        // -   ori     D0, D0, (BIT(1))
+        // -   std     D0, EX_OHA_MODE_REG_RWx1002000D, P0
+#endif
+        // -   bra     2f
+        // -   1:
+        // To accomodate IPL flow, where sub_slw_runtime_scom() is skipped
+        // - setp1_mcreadand D0
+#if 0
+        // Clear regular wake-up and restore PSCOM fence in OHA
+        // These were established in p9_sbe_ex_scominit.S
+        // -   ld      D0, EX_OHA_MODE_REG_RWx1002000D, P1
+        // -   andi    D0, D0, ~BIT(1)
+        // -   std     D0, EX_OHA_MODE_REG_RWx1002000D, P0
+        // -   ld      D0, EX_OHA_AISS_IO_REG_0x10020014, P1
+        // -   andi    D0, D0, ~(BIT(15))
+        // -   ori     D0, D0, BIT(21)
+        // -   std     D0, EX_OHA_AISS_IO_REG_0x10020014, P0
+        // Enable the AISS to allow further operation
+        // -   ld      D0, EX_OHA_MODE_REG_RWx1002000D, P1
+        // -   ori     D0, D0, (BIT(1))
+        // -   std     D0, EX_OHA_MODE_REG_RWx1002000D, P0
+#endif
+        // -   2:
+
+        // If using cv_multicast, we need to set the magic istep number here
+        // -   la      A0, p9_sbe_select_ex_control
+        // -   ldandi  D0, 0, A0, P9_CONTROL_INIT_ALL_EX
+        // -   braz    D0, 3f
+        FAPI_DBG("Setting istep num to magic number because cv_multicast is set")
+        // -   lpcs    P1, MBOX_SBEVITAL_0x0005001C
+        // -   sti     MBOX_SBEVITAL_0x0005001C, P1, (P9_SBE_EX_RAS_RUNTIME_SCOM_MAGIC_ISTEP_NUM << (4+32))
+        // -   3:
+
+        return fapi2::FAPI2_RC_SUCCESS;
+
+        FAPI_CLEANUP();
+        return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
+
+#endif
+
+        return fapi2::FAPI2_RC_SUCCESS;
+
+    } // Procedure
+
+
+} // extern C
+
+
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.H
new file mode 100644
index 00000000..511b35c4
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.H
@@ -0,0 +1,63 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_ras_runtime_scom.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_ras_runtime_scom.H
+/// @brief FSP/Host run-time SCOMS
+///
+/// *HWP HWP Owner   : David Du      <daviddu@us.ibm.com>
+/// *HWP FW Owner    : Reshmi Nair   <resnair5@in.ibm.com>
+/// *HWP Team        : PM
+/// *HWP Consumed by : SBE:CME
+/// *HWP Level       : 1
+///
+
+#ifndef __P9_HCD_CORE_RAS_RUNTIME_SCOM_H__
+#define __P9_HCD_CORE_RAS_RUNTIME_SCOM_H__
+
+extern "C"
+{
+
+/// @typedef p9_hcd_core_ras_runtime_scom_FP_t
+/// function pointer typedef definition for HWP call support
+    typedef fapi2::ReturnCode (*p9_hcd_core_ras_runtime_scom_FP_t) (
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
+
+
+/// @brief FSP/Host run-time SCOMS
+///
+/// @param [in] i_target TARGET_TYPE_CORE target
+//
+/// @attr
+/// @attritem ATTR_CORE_RAS_SCOM_LOC - EC target, uint32
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_core_ras_runtime_scom(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+
+
+} // extern C
+
+#endif  // __P9_HCD_CORE_RAS_RUNTIME_SCOM_H__
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.C
new file mode 100644
index 00000000..b8f6be7e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.C
@@ -0,0 +1,76 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_repair_initf.C
+/// @brief Load Repair ring for core
+///
+/// Procedure Summary:
+///   Load core ring images from that came from MVPD into the image
+///     These rings must contain ALL chip customization data. This includes the
+///     following:  Array Repair and DTS calibration settings
+///     Historically this was stored in MVPD keywords are #R, #G.  Still stored
+///     in MVPD, but SBE image is customized with rings for booting cores
+///     at build time
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+
+#include <p9_ring_id.h>
+#include "p9_hcd_core_repair_initf.H"
+
+//-----------------------------------------------------------------------------
+// Constant Definitions
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Procedure: Load Repair ring for core
+//-----------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_core_repair_initf(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+{
+    FAPI_INF(">>p9_hcd_core_repair_initf");
+
+    FAPI_DBG("Scan ec_repr ring");
+    FAPI_TRY(fapi2::putRing(i_target, ec_repr,
+                            fapi2::RING_MODE_HEADER_CHECK),
+             "Error from putRing (ec_repr)");
+
+fapi_try_exit:
+
+    FAPI_INF("<<p9_hcd_core_repair_initf");
+    return fapi2::current_err;
+}
+
+
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.H
new file mode 100644
index 00000000..a998c4bd
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.H
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_repair_initf.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_repair_initf.H
+/// @brief Load Repair ring for core
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CORE_REPAIR_INITF_H__
+#define __P9_HCD_CORE_REPAIR_INITF_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_core_repair_initf_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_core_repair_initf_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
+
+extern "C"
+{
+
+/// @brief Load Repair ring for core
+///
+/// @param [in] i_target TARGET_TYPE_CORE target
+/// @attr
+/// @attritem ATTR_CORE_REPAIR_RING - EC target, uint32
+///               pointer to RS4 content
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_core_repair_initf(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+
+}
+
+#endif  // __P9_HCD_CORE_REPAIR_INITF_H__
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.C
new file mode 100644
index 00000000..54ed6dd5
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.C
@@ -0,0 +1,83 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.C $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_scomcust.C
+/// @brief Core Customization SCOMs
+///
+/// *HWP HWP Owner   : David Du      <daviddu@us.ibm.com>
+/// *HWP FW Owner    : Reshmi Nair   <resnair5@in.ibm.com>
+/// *HWP Team        : PM
+/// *HWP Consumed by : SBE:CME
+/// *HWP Level       : 1
+///
+/// Procedure Summary:
+///   Dynamically built (and installed) routine that is inserted by the .XIP
+///   Customization. process. (New for P9) (TODO: this part of the process is
+///   a placeholder at this point)
+///   Dynamically built pointer where a NULL is checked before execution
+///   If NULL (a potential early value); return
+///   Else call the function at the pointer;
+///   pointer is filled in by XIP Customization
+///
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+#include <fapi2.H>
+//#include <common_scom_addresses.H>
+//will be replaced with real scom address header file
+#include "p9_hcd_core_scomcust.H"
+
+//-----------------------------------------------------------------------------
+// Constant Definitions: Core Customization SCOMs
+//-----------------------------------------------------------------------------
+
+extern "C"
+{
+
+    fapi2::ReturnCode
+    p9_hcd_core_scomcust(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+    {
+
+#if 0
+
+        fapi2::buffer<uint64_t> data;
+
+        return fapi2::FAPI2_RC_SUCCESS;
+
+        FAPI_CLEANUP();
+        return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
+
+#endif
+
+        return fapi2::FAPI2_RC_SUCCESS;
+
+    } // Procedure
+
+
+} // extern C
+
+
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.H
new file mode 100644
index 00000000..f69ce528
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.H
@@ -0,0 +1,63 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_scomcust.H $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_scomcust.H
+/// @brief Core Customization SCOMs
+///
+/// *HWP HWP Owner   : David Du      <daviddu@us.ibm.com>
+/// *HWP FW Owner    : Reshmi Nair   <resnair5@in.ibm.com>
+/// *HWP Team        : PM
+/// *HWP Consumed by : SBE:CME
+/// *HWP Level       : 1
+///
+
+
+#ifndef __P9_HCD_CORE_SCOMCUST_H__
+#define __P9_HCD_CORE_SCOMCUST_H__
+
+extern "C"
+{
+
+/// @typedef p9_hcd_core_scomcust_FP_t
+/// function pointer typedef definition for HWP call support
+    typedef fapi2::ReturnCode (*p9_hcd_core_scomcust_FP_t) (
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
+
+
+/// @brief Core Customization SCOMs
+///
+/// @param [in] i_target TARGET_TYPE_CORE target
+///
+/// @attr
+/// @attritem NONE
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_core_scomcust(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+
+} // extern C
+
+#endif  // __P9_HCD_CORE_SCOMCUST_H__
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C
new file mode 100644
index 00000000..c05caed4
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C
@@ -0,0 +1,85 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_scominit.C
+/// @brief Core SCOM Inits
+///
+/// Procedure Summary:
+/// Apply any coded SCOM initialization to core
+///
+
+// *HWP HWP Owner          : David Du      <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still    <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+
+#include <p9_quad_scom_addresses.H>
+#include <p9_hcd_common.H>
+#include "p9_hcd_core_scominit.H"
+
+//-----------------------------------------------------------------------------
+// Constant Definitions
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Procedure: Core SCOM Inits
+//-----------------------------------------------------------------------------
+
+
+fapi2::ReturnCode
+p9_hcd_core_scominit(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+{
+    FAPI_INF(">>p9_hcd_core_scominit");
+    fapi2::buffer<uint64_t> l_data64;
+
+    /// @todo how about bit 6?
+    FAPI_DBG("Restore SYNC_CONFIG[8] for stop1");
+    FAPI_TRY(getScom(i_target, C_SYNC_CONFIG, l_data64));
+    FAPI_TRY(putScom(i_target, C_SYNC_CONFIG, DATA_SET(8)));
+
+    /// @todo set the sample pulse count (bit 6:9)
+    /// enable the appropriate loops
+    /// (needs investigation with the Perv team on the EC wiring).
+    FAPI_DBG("Enable DTS sampling via THERM_MODE_REG[5]");
+    FAPI_TRY(getScom(i_target, C_THERM_MODE_REG, l_data64));
+    FAPI_TRY(putScom(i_target, C_THERM_MODE_REG, DATA_SET(5)));
+
+    FAPI_DBG("Set core as ready to run in STOP history register");
+    FAPI_TRY(putScom(i_target, C_PPM_SSHSRC, 0));
+
+fapi_try_exit:
+
+    FAPI_INF("<<p9_hcd_core_scominit");
+    return fapi2::current_err;
+}
+
+
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.H
new file mode 100644
index 00000000..7065028e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.H
@@ -0,0 +1,63 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.H $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_scominit.H
+/// @brief Core SCOM Inits
+///
+
+// *HWP HWP Owner          : David Du      <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still    <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CORE_SCOMINIT_H__
+#define __P9_HCD_CORE_SCOMINIT_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_core_scominit_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_core_scominit_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
+
+extern "C"
+{
+
+/// @brief Core SCOM Inits
+///
+/// @param [in] i_target TARGET_TYPE_CORE target
+/// @attr
+/// @attritem NONE
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_hcd_core_scominit(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+
+} // extern C
+
+#endif  // __P9_HCD_CORE_SCOMINIT_H__
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C
new file mode 100644
index 00000000..3cccb8b5
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C
@@ -0,0 +1,285 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_startclocks.C
+/// @brief Core Clock Start
+///
+/// Procedure Summary:
+///   (Done) Drop partial good regional fences(always drop vital and pervasive)
+///   (Done) Drop vital fence
+///   (Done) Reset abst clock muxsel, sync muxsel
+///   (TODO) +set fabric node/chip ID (read from nest chiplet)
+///   (Done) module align_chiplets
+///   (Done)  - set flushmode_inh to exit flush mode
+///   (Done)  - set force_align
+///   (Done)  - set clear_chiplet_is_aligned
+///   (Done)  - unset clear_chiplet_is_aligned
+///   (Done)  - wait
+///   (Done)  - check chiplet_is_aligned
+///   (Done)  - clear force_align
+///   (Done) module start_clocks
+///   (Done)  - set flush mode(alerady set in align_chiplets)
+///   (Done)  - Clear scan region type register
+///   (Done)  - Start arrays + nsl regions
+///   (Done)  - Start sl + refresh clock regions
+///   (Done) Check for clocks started, If not, error
+///   (Done) Drop the core to cache logical fence
+///   (Done) Check for core xstop, If so, error
+///   (Done) Clear flushmode_inh to go into flush mode
+///   (Done) Check cache/core chiplet_is_aligned
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <p9_quad_scom_addresses.H>
+#include <p9_hcd_common.H>
+#include "p9_hcd_core_startclocks.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions
+//------------------------------------------------------------------------------
+
+enum P9_HCD_CORE_STARTCLOCKS_CONSTANTS
+{
+    CORE_CLK_SYNC_TIMEOUT_IN_MS       = 1,
+    CORE_CLK_START_TIMEOUT_IN_MS      = 1,
+    CORE_CLK_ALIGN_DELAY_CACHE_CYCLES = 255
+};
+
+//------------------------------------------------------------------------------
+// Procedure: Core Clock Start
+//------------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_hcd_core_startclocks(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+{
+    FAPI_INF(">>p9_hcd_core_startclocks");
+    fapi2::buffer<uint64_t>                     l_data64;
+    uint32_t                                    l_timeout;
+    uint32_t                                    l_attr_pg;
+    uint8_t                                     l_attr_chip_unit_pos;
+    uint8_t                                     l_attr_system_ipl_phase;
+    uint8_t                                     l_attr_runn_mode;
+    fapi2::Target<fapi2::TARGET_TYPE_EQ>        l_quad =
+        i_target.getParent<fapi2::TARGET_TYPE_EQ>();
+    fapi2::Target<fapi2::TARGET_TYPE_PERV>      l_perv =
+        i_target.getParent<fapi2::TARGET_TYPE_PERV>();
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys;
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RUNN_MODE,        l_sys,
+                           l_attr_runn_mode));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, l_sys,
+                           l_attr_system_ipl_phase));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG,               l_perv,
+                           l_attr_pg));
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,    l_perv,
+                           l_attr_chip_unit_pos));
+    l_attr_chip_unit_pos = (l_attr_chip_unit_pos -
+                            p9hcd::PERV_TO_CORE_POS_OFFSET) % 4;
+
+    // ----------------------------
+    // Prepare to start core clocks
+    // ----------------------------
+
+    if (l_attr_system_ipl_phase ==
+        fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED)
+    {
+        FAPI_DBG("Set CPLT_CTRL0[AVP_MODE] for cache-contained execution");
+        FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_OR, MASK_SET(5)));
+    }
+
+    /// @todo add DD1 attribute control
+    FAPI_DBG("DD1 only: set sdis_n(flushing LCBES condition workaround");
+    FAPI_TRY(putScom(i_target, C_CPLT_CONF0_OR, MASK_SET(34)));
+
+    FAPI_DBG("Set inop_align/wait/wait_cycles via OPCG_ALIGN[0-3,12-19,52-63]");
+    FAPI_TRY(getScom(i_target, C_OPCG_ALIGN, l_data64));
+    l_data64.insertFromRight<0, 4>(0x5).
+    insertFromRight<12, 8>(0x0).
+    insertFromRight<52, 12>(0x10);
+    FAPI_TRY(putScom(i_target, C_OPCG_ALIGN, l_data64));
+
+    /// @todo partial good information via attribute, drop all fences for now
+    FAPI_DBG("Drop partial good fences via CPLT_CTRL1[4-13]");
+    FAPI_TRY(putScom(i_target, C_CPLT_CTRL1_CLEAR, MASK_CLR(4, 11, 0x7FF)));
+
+    FAPI_DBG("Drop vital fence via CPLT_CTRL1[3]");
+    FAPI_TRY(putScom(i_target, C_CPLT_CTRL1_CLEAR, MASK_SET(3)));
+
+    FAPI_DBG("Drop skew sense to skew adjust fence via NET_CTRL0[22]");
+    FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(22)));
+
+    FAPI_DBG("Assert core clock sync enable via CPPM_CACCR[15]");
+    FAPI_TRY(putScom(i_target, C_CPPM_CACCR_OR, MASK_SET(15)));
+
+    FAPI_DBG("Poll for core clock sync done via CPPM_CACSR[13]");
+    l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
+                CORE_CLK_START_TIMEOUT_IN_MS;
+
+    do
+    {
+        FAPI_TRY(getScom(i_target, C_CPPM_CACSR, l_data64));
+    }
+    while((l_data64.getBit<13>() != 1) && ((--l_timeout) != 0));
+
+    FAPI_ASSERT((l_timeout != 0),
+                fapi2::PMPROC_CORECLKSYNC_TIMEOUT().set_COREPPMCACSR(l_data64),
+                "Core Clock Sync Timeout");
+    FAPI_DBG("Core clock sync done");
+
+    FAPI_DBG("Reset abstclk & syncclk muxsel(io_clk_sel) via CPLT_CTRL0[0:1]");
+    FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_CLEAR, MASK_CLR(0, 2, 3)));
+
+    // -------------------------------
+    // Align chiplets
+    // -------------------------------
+
+    FAPI_DBG("Assert flushmode_inhibit via CPLT_CTRL0[2]");
+    FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_OR, MASK_SET(2)));
+
+    FAPI_DBG("Assert force_align via CPLT_CTRL0[3]");
+    FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_OR, MASK_SET(3)));
+
+    FAPI_DBG("Set then unset clear_chiplet_is_aligned via SYNC_CONFIG[7]");
+    FAPI_TRY(getScom(i_target, C_SYNC_CONFIG, l_data64));
+    FAPI_TRY(putScom(i_target, C_SYNC_CONFIG, DATA_SET(7)));
+    FAPI_TRY(putScom(i_target, C_SYNC_CONFIG, DATA_UNSET(7)));
+
+    FAPI_TRY(fapi2::delay(
+                 CORE_CLK_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE *
+                 p9hcd::CLK_PERIOD_250PS / 1000,
+                 CORE_CLK_ALIGN_DELAY_CACHE_CYCLES * p9hcd::CLK_PERIOD_CORE2CACHE *
+                 p9hcd::SIM_CYCLE_4U4D));
+
+    FAPI_DBG("Poll for core chiplet aligned");
+    l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
+                CORE_CLK_START_TIMEOUT_IN_MS;
+
+    do
+    {
+        FAPI_TRY(getScom(i_target, C_CPLT_STAT0, l_data64));
+    }
+    while((l_data64.getBit<9>() != 1) && ((--l_timeout) != 0));
+
+    FAPI_ASSERT((l_timeout != 0),
+                fapi2::PMPROC_CORECPLTALIGN_TIMEOUT()
+                .set_CORECPLTSTAT0(l_data64),
+                "Core Chiplets Aligned Timeout");
+    FAPI_DBG("Core chiplets aligned now");
+
+    FAPI_DBG("Drop force_align via CPLT_CTRL0[3]");
+    FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_CLEAR, MASK_SET(3)));
+
+    // -------------------------------
+    // Start core clocks
+    // -------------------------------
+
+    FAPI_DBG("Clear all bits prior start core clocks via SCAN_REGION_TYPE");
+    FAPI_TRY(putScom(i_target, C_SCAN_REGION_TYPE, MASK_ZERO));
+
+    if (!l_attr_runn_mode)
+    {
+
+        FAPI_DBG("Start core clocks(all but pll) via CLK_REGION");
+        l_data64 = (p9hcd::CLK_START_CMD          |
+                    p9hcd::CLK_REGION_ALL_BUT_PLL |
+                    p9hcd::CLK_THOLD_ALL);
+        FAPI_TRY(putScom(i_target, C_CLK_REGION, l_data64));
+
+        FAPI_DBG("Poll for core clocks running via CPLT_STAT0[8]");
+        l_timeout = (p9hcd::CYCLES_PER_MS / p9hcd::INSTS_PER_POLL_LOOP) *
+                    CORE_CLK_START_TIMEOUT_IN_MS;
+
+        do
+        {
+            FAPI_TRY(getScom(i_target, C_CPLT_STAT0, l_data64));
+        }
+        while((l_data64.getBit<8>() != 1) && ((--l_timeout) != 0));
+
+        FAPI_ASSERT((l_timeout != 0),
+                    fapi2::PMPROC_CORECLKSTART_TIMEOUT().set_CORECPLTSTAT(l_data64),
+                    "Core Clock Start Timeout");
+
+        FAPI_DBG("Check core clocks running via CLOCK_STAT_SL[4-13]");
+        FAPI_TRY(getScom(i_target, C_CLOCK_STAT_SL, l_data64));
+
+        FAPI_ASSERT(((l_data64 & p9hcd::CLK_REGION_ALL_BUT_PLL) == 0),
+                    fapi2::PMPROC_CORECLKSTART_FAILED().set_CORECLKSTAT(l_data64),
+                    "Core Clock Start Failed");
+        FAPI_DBG("Core clocks running now");
+
+    }
+
+    // -------------------------------
+    // Cleaning up
+    // -------------------------------
+
+    if ((~l_attr_pg) & BITS32(4, 11))
+    {
+        FAPI_DBG("Drop chiplet fence via NET_CTRL0[18]");
+        FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(18)));
+    }
+
+    /// @todo ignore xstop checkstop in sim, review for lab
+    /*
+    FAPI_DBG("Check the Global Checkstop FIR");
+    FAPI_TRY(getScom(i_target, C_XFIR, l_data64));
+    FAPI_ASSERT(((l_data64 & BITS64(0, 27)) != 0),
+                fapi2::PMPROC_CORE_XSTOP().set_COREXFIR(l_data64),
+                "Core Chiplet Checkstop");
+    */
+
+    FAPI_DBG("Drop flushmode_inhibit via CPLT_CTRL0[2]");
+    FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_CLEAR, MASK_SET(2)));
+
+    if (!l_attr_runn_mode && l_attr_system_ipl_phase !=
+        fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED)
+    {
+        FAPI_DBG("Drop Core-L2/CC Quiesces via CME_SCOM_SICR[6,8]/[7,9]");
+        FAPI_TRY(putScom(l_quad,
+                         (l_attr_chip_unit_pos < 2) ?
+                         EX_0_CME_SCOM_SICR_CLEAR : EX_1_CME_SCOM_SICR_CLEAR,
+                         (BIT64(6 + (l_attr_chip_unit_pos % 2)) |
+                          BIT64(8 + (l_attr_chip_unit_pos % 2)))));
+    }
+
+fapi_try_exit:
+
+    FAPI_INF("<<p9_hcd_core_startclocks");
+    return fapi2::current_err;
+}
+
+
+
+
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.H
new file mode 100644
index 00000000..75e94909
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_hcd_core_startclocks.H
+/// @brief Core Clock Start
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:CME
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_CORE_STARTCLOCKS_H__
+#define __P9_HCD_CORE_STARTCLOCKS_H__
+
+#include <fapi2.H>
+
+/// @typedef p9_hcd_core_startclocks_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_hcd_core_startclocks_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
+
+extern "C"
+{
+
+/// @brief Quad Clock Start
+/// @param [in] i_target TARGET_TYPE_EX target
+/// @return FAPI2_RC_SUCCESS if success, else error code
+    fapi2::ReturnCode
+    p9_hcd_core_startclocks(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+
+}
+
+#endif  // __P9_HCD_CORE_STARTCLOCKS_H__
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.C b/src/import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.C
new file mode 100644
index 00000000..fb6affa0
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.C
@@ -0,0 +1,67 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_sbe_instruct_start.C
+/// @brief
+///    Starts instructions on 1 core, thread 0.
+///    Thread 0 will be started at CIA scan flush value of 0.
+//
+// *HWP HWP Owner: Nick Klazynski <jklazyns@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: HB
+//
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <p9_sbe_instruct_start.H>
+
+extern "C"
+{
+
+///
+/// p9_sbe_instruct_start HWP entry point (Defined in .H file)
+///
+    fapi2::ReturnCode p9_sbe_instruct_start(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+    {
+        fapi2::buffer<uint64_t> l_rasStatusReg(0);
+        uint64_t l_state = 0;
+        FAPI_DBG("Entering ...");
+
+        FAPI_INF("Starting instruction on thread 0");
+        FAPI_TRY(p9_thread_control(i_target, 0b1000, PTC_CMD_START, false,
+                                   l_rasStatusReg, l_state),
+                 "p9_sbe_instruct_start: p9_thread_control() returns an error");
+
+    fapi_try_exit:
+        FAPI_DBG("Exiting ...");
+        return fapi2::current_err;
+    }
+
+} // extern "C"
+/* End: */
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.H b/src/import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.H
new file mode 100644
index 00000000..d143fd43
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.H
@@ -0,0 +1,70 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_sbe_instruct_start.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_sbe_instruct_start.C
+/// @brief  Placeholder for overrides needed to step the core from cache-contained execution to expand to memory
+///
+// *HWP HWP Owner: Nick Klazynski <jklazyns@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: HB
+
+#ifndef _PROC_SBE_INSTRUCT_START_H_
+#define _PROC_SBE_INSTRUCT_START_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <fapi2.H>
+#include <p9_thread_control.H>
+
+// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode
+(*p9_sbe_instruct_start_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+extern "C"
+{
+//------------------------------------------------------------------------------
+// Hardware Procedure
+//------------------------------------------------------------------------------
+///
+/// @brief Calls thread_control to start instruction on thread 0.
+///        This is to be called during IPL (istep 5.2)
+///
+/// @param[in] i_target   Reference to core target
+///
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code
+///
+    fapi2::ReturnCode p9_sbe_instruct_start(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+
+} // extern "C"
+
+#endif // _PROC_SBE_INSTRUCT_START_H_
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_thread_control.C b/src/import/chips/p9/procedures/hwp/core/p9_thread_control.C
new file mode 100644
index 00000000..529fd829
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_thread_control.C
@@ -0,0 +1,703 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_thread_control.C $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_thread_control.C
+/// @brief Implementation of sreset, start, stop and step
+///
+
+// *HWP HWP Owner: Nick Klazynski <jklazyns@us.ibm.com>
+// *HWP FW Owner:  Thi Tran <thi@us.ibm.com>
+// *HWP Team:  Quad
+// *HWP Level: 2
+// Current Status: Only start function tested as working
+// *HWP Consumed by: FSP:HB:HS
+
+#include <fapi2.H>
+#include <p9_thread_control.H>
+
+using fapi2::TARGET_TYPE_EX;
+using fapi2::TARGET_TYPE_CORE;
+
+using fapi2::FAPI2_RC_SUCCESS;
+
+// The control bits for each thread are contained in DIRECT_CONTROLS
+// in regular offsets. This map allows us to go from a thread_bitset
+// to a generic register with the proper bits set. We can then shift
+// this result to align with the actual operation bit in the reg.
+// PS. this map works for C_RAS_STATUS as well.
+static const uint64_t g_control_reg_map[] =
+{
+    0x0000000000000000, // b0000, no threads
+    0x0000008000000000, // b0001, thread 3
+    0x0000800000000000, // b0010, thread 2
+    0x0000808000000000, // b0011, thread 2,3
+    0x0080000000000000, // b0100, thread 1
+    0x0080008000000000, // b0101, thread 1,3
+    0x0080800000000000, // b0110
+    0x0080808000000000, // b0111
+    0x8000000000000000, // b1000
+    0x8000008000000000, // b1001
+    0x8000800000000000, // b1010
+    0x8000808000000000, // b1011
+    0x8080000000000000, // b1100
+    0x8080008000000000, // b1101
+    0x8080800000000000, // b1110
+    0x8080808000000000, // b1111
+};
+
+//--------------------------------------------------------------------------
+// Function definitions
+//--------------------------------------------------------------------------
+
+fapi2::ReturnCode p9_thread_control_sreset(
+    const fapi2::Target<TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads, const bool i_warncheck,
+    fapi2::buffer<uint64_t>& o_rasStatusReg);
+
+fapi2::ReturnCode p9_thread_control_start(
+    const fapi2::Target<TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads, const bool i_warncheck,
+    fapi2::buffer<uint64_t>& o_rasStatusReg);
+
+fapi2::ReturnCode p9_thread_control_stop(
+    const fapi2::Target<TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads, const bool i_warncheck,
+    fapi2::buffer<uint64_t>& o_rasStatusReg);
+
+fapi2::ReturnCode p9_thread_control_step(
+    const fapi2::Target<TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads, const bool i_warncheck,
+    fapi2::buffer<uint64_t>& o_rasStatusReg);
+
+fapi2::ReturnCode p9_thread_control_query(
+    const fapi2::Target<TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads,
+    fapi2::buffer<uint64_t>& o_rasStatusReg,
+    uint64_t& o_state);
+
+//--------------------------------------------------------------------------
+/// @brief threads_running : static funtion to encapsulate the running state
+/// @param[in] i_target core target
+/// @param[in] i_thread normal core thread bitset (0b0000..0b1111)
+/// @param[out] o_rasStatusReg  Complete RAS status reg 64-bit buffer.
+/// @param[out] o_ok true if the threads are running
+/// @return FAPI2_RC_SUCCESS if the underlying hw operations succeeded
+//--------------------------------------------------------------------------
+static inline fapi2::ReturnCode threads_running(
+    const fapi2::Target<TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads,
+    fapi2::buffer<uint64_t>& o_rasStatusReg,
+    bool& o_ok)
+{
+    // Running is defined as not in maint mode and not quiesced.
+    uint64_t l_state = 0;
+    FAPI_TRY(p9_thread_control_query(i_target, i_threads, o_rasStatusReg, l_state),
+             "threads_running(): p9_thread_control_query() returns an error.");
+    o_ok = (l_state & THREAD_STATE_RUNNING);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+//--------------------------------------------------------------------------
+/// @brief threads_in_maint : static funtion to encapsulate the maint state
+/// @param[in] i_target core target
+/// @param[in] i_thread normal core thread bitset (0b0000..0b1111)
+/// @param[out] o_rasStatusReg  Complete RAS status reg 64-bit buffer.
+/// @param[out] o_ok true if the threads are in maint mode
+/// @return FAPI2_RC_SUCCESS if the underlying hw operations succeeded
+//--------------------------------------------------------------------------
+static inline fapi2::ReturnCode threads_in_maint(
+    const fapi2::Target<TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads,
+    fapi2::buffer<uint64_t>& o_rasStatusReg,
+    bool& o_ok)
+{
+    uint64_t l_state = 0;
+    FAPI_TRY(p9_thread_control_query(i_target, i_threads, o_rasStatusReg, l_state),
+             "threads_in_maint(): p9_thread_control_query() returns an error.");
+    o_ok = (l_state & THREAD_STATE_MAINT);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+//--------------------------------------------------------------------------
+/// @brief all_threads_stopped : static funtion to encapsulate the stopped state
+/// @param[in] i_target core target
+/// @param[in] i_thread normal core thread bitset (0b0000..0b1111)
+/// @param[out] o_rasStatusReg  Complete RAS status reg 64-bit buffer.
+/// @param[out] o_ok true if the threads are stopped
+/// @return FAPI2_RC_SUCCESS if the underlying hw operations succeeded
+//--------------------------------------------------------------------------
+static inline fapi2::ReturnCode threads_stopped(
+    const fapi2::Target<TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads,
+    fapi2::buffer<uint64_t>& o_rasStatusReg,
+    bool& o_ok)
+{
+    // Running is defined as not in maint mode and not quiesced.
+    uint64_t l_state = 0;
+    FAPI_TRY(p9_thread_control_query(i_target, i_threads, o_rasStatusReg, l_state),
+             "threads_stopped(): p9_thread_control_query() returns an error.");
+    o_ok = (l_state & THREAD_STATE_STOP);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+//--------------------------------------------------------------------------
+/// @brief all_threads_step_done : static funtion to encapsulate the step
+/// complete state
+/// @param[in] i_target core target
+/// @param[in] i_thread normal core thread bitset (0b0000..0b1111)
+/// @param[out] o_rasStatusReg  Complete RAS status reg 64-bit buffer.
+/// @param[out] o_ok true if the threads are done stepping
+/// @return FAPI2_RC_SUCCESS if the underlying hw operations succeeded
+//--------------------------------------------------------------------------
+static inline fapi2::ReturnCode threads_step_done(
+    const fapi2::Target<TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads,
+    fapi2::buffer<uint64_t>& o_rasStatusReg,
+    bool& o_ok)
+{
+    uint64_t l_state = 0;
+    FAPI_TRY(p9_thread_control_query(i_target, i_threads, o_rasStatusReg, l_state),
+             "threads_step_done(): p9_thread_control_query() returns an error.");
+    o_ok = (l_state & THREAD_STATE_ISTEP_SUCCESS);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+//--------------------------------------------------------------------------
+/// @brief threads_step_ready : static funtion to encapsulate the step
+/// ready state
+/// @param[in] i_target core target
+/// @param[in] i_thread normal core thread bitset (0b0000..0b1111)
+/// @param[out] o_rasStatusReg  Complete RAS status reg 64-bit buffer.
+/// @param[out] o_ok true if the threads are ready to step
+/// @return FAPI2_RC_SUCCESS if the underlying hw operations succeeded
+//--------------------------------------------------------------------------
+static inline fapi2::ReturnCode threads_step_ready(
+    const fapi2::Target<TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads,
+    fapi2::buffer<uint64_t>& o_rasStatusReg,
+    bool& o_ok)
+{
+    uint64_t l_state = 0;
+    FAPI_TRY(p9_thread_control_query(i_target, i_threads, o_rasStatusReg, l_state),
+             "threads_step_ready(): p9_thread_control_query() returns an error.");
+    o_ok = (l_state & THREAD_STATE_ISTEP_READY);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+//--------------------------------------------------------------------------
+/// @brief p9_thread_control: utility subroutine to control thread state
+//--------------------------------------------------------------------------
+fapi2::ReturnCode p9_thread_control(
+    const fapi2::Target<TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads, const ThreadCommands i_command,
+    const bool i_warncheck,
+    fapi2::buffer<uint64_t>& o_rasStatusReg,
+    uint64_t& o_state)
+{
+    FAPI_INF("p9_thread_control : Core threads: 0x%x, Command %u", i_threads, i_command);
+
+    // Output state is only valid for PTC_CMD_QUERY command
+    o_state = 0;
+
+    switch(i_command)
+    {
+        case PTC_CMD_SRESET:
+            FAPI_TRY(p9_thread_control_sreset(i_target, i_threads, i_warncheck,
+                                              o_rasStatusReg));
+            break;
+
+        case PTC_CMD_START:
+            FAPI_TRY(p9_thread_control_start(i_target, i_threads, i_warncheck,
+                                             o_rasStatusReg));
+            break;
+
+        case PTC_CMD_STOP:
+            FAPI_TRY(p9_thread_control_stop(i_target, i_threads, i_warncheck,
+                                            o_rasStatusReg));
+            break;
+
+        case PTC_CMD_STEP:
+            FAPI_TRY(p9_thread_control_step(i_target, i_threads, i_warncheck,
+                                            o_rasStatusReg));
+            break;
+
+        case PTC_CMD_QUERY:
+            FAPI_TRY(p9_thread_control_query(i_target, i_threads,
+                                             o_rasStatusReg, o_state));
+            break;
+    };
+
+fapi_try_exit:
+    FAPI_INF("p9_thread_control : Exit (core)");
+
+    return fapi2::current_err;
+
+}
+
+//--------------------------------------------------------------------------
+/// @brief Utility subroutine to query the state of a thread(s).
+///
+/// @param[in] i_target      Reference to core target
+/// @param[in] i_threads     Desired thread bits set
+///                             0b0000         No thread (No-op)
+///                             0b1000         Thread 0
+///                             0b0100         Thread 1
+///                             0b0010         Thread 2
+///                             0b0001         Thread 3
+/// @param[out] o_rasStatusReg  Complete RAS status reg 64-bit buffer.
+///                             Only valid for PTC_CMD_QUERY command.
+/// @param[out] o_state      Current thread state. See THREAD_STATE bit
+///                          definitions in header file.
+///
+/// @return FAPI2_RC_SUCCESS if operation was successful, else error.
+//--------------------------------------------------------------------------
+fapi2::ReturnCode p9_thread_control_query(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads,
+    fapi2::buffer<uint64_t>& o_rasStatusReg,
+    uint64_t& o_state)
+{
+    FAPI_DBG("Entering: Thread bit set %u", i_threads);
+
+    // Initializing
+    o_state = 0;
+
+    // Setup mask values
+    const uint64_t l_running_mask =
+        (g_control_reg_map[i_threads] >> CORE_MAINT_MODE) |
+        (g_control_reg_map[i_threads] >> THREAD_QUIESCED);
+    const uint64_t l_step_ready_mask =
+        (g_control_reg_map[i_threads] >> CORE_MAINT_MODE) |
+        (g_control_reg_map[i_threads] >> THREAD_QUIESCED) |
+        (g_control_reg_map[i_threads] >> ICT_EMPTY);
+
+    // Get C_RAS_STATUS reg
+    FAPI_TRY(fapi2::getScom(i_target, C_RAS_STATUS, o_rasStatusReg),
+             "p9_thread_control_query(): getScom() returns an error, "
+             "Addr C_RAS_STATUS 0x%.16llX", C_RAS_STATUS);
+
+    // Note: all threads must meet a given condition in order for the
+    //       bit to be set.
+    // Set THREAD_STATE_RUNNING
+    // Running is defined as not in maint mode and not quiesced.
+    if ( ((o_rasStatusReg & l_running_mask) == 0) )
+    {
+        o_state |= THREAD_STATE_RUNNING;
+    }
+    // Stop is defined as in maint mode and in quiesced.
+    else if ( ((o_rasStatusReg & l_running_mask) == l_running_mask) )
+    {
+        o_state |= THREAD_STATE_STOP;
+    }
+
+    // Check for THREAD_STATE_MAINT
+    if ( o_rasStatusReg &
+         g_control_reg_map[i_threads] >> CORE_MAINT_MODE )
+    {
+        o_state |= THREAD_STATE_MAINT;
+    }
+
+    // Check for THREAD_STATE_QUIESCED
+    if ( o_rasStatusReg &
+         g_control_reg_map[i_threads] >> THREAD_QUIESCED )
+    {
+        o_state |= THREAD_STATE_QUIESCED;
+    }
+
+    // Check for THREAD_STATE_ICT_EMPTY
+    if ( o_rasStatusReg &
+         g_control_reg_map[i_threads] >> ICT_EMPTY )
+    {
+        o_state |= THREAD_STATE_ICT_EMPTY;
+    }
+
+    // Check for THREAD_STATE_LSU_QUIESCED
+    if ( o_rasStatusReg &
+         g_control_reg_map[i_threads] >> LSU_QUIESCED )
+    {
+        o_state |= THREAD_STATE_LSU_QUIESCED;
+    }
+
+    // Check for THREAD_STATE_ISTEP_SUCCESS
+    if ( o_rasStatusReg &
+         g_control_reg_map[i_threads] >> STEP_SUCCESS )
+    {
+        o_state |= THREAD_STATE_ISTEP_SUCCESS;
+    }
+
+    // Check for THREAD_STATE_ISTEP_READY
+    // All maint, quiesced and ICT empty must be set.
+    if ( ((o_rasStatusReg & l_step_ready_mask) == l_step_ready_mask) )
+    {
+        o_state |= THREAD_STATE_ISTEP_READY;
+    }
+
+    FAPI_DBG("C_RAS_STATUS: 0x%.16llX, Thread state 0x%.16llX",
+             o_rasStatusReg, o_state);
+
+fapi_try_exit:
+    FAPI_DBG("Exiting");
+    return fapi2::current_err;
+}
+
+//--------------------------------------------------------------------------
+/// @brief p9_thread_control: utility subroutine to control thread state
+//-------------------------------------------------------------------------
+fapi2::ReturnCode p9_thread_control(
+    const fapi2::Target<TARGET_TYPE_EX>& i_target,
+    const uint8_t i_threads,
+    const ThreadCommands i_command,
+    fapi2::buffer<uint64_t>& o_rasStatusReg,
+    const bool i_warncheck)
+{
+    uint64_t l_state = 0;
+    FAPI_INF("p9_thread_control : Start (ex) threads: 0x%x)", i_threads);
+
+    // Grab the normal core children and iterate over them.
+    // TODO: Assumes core 0 is l_cores[0]
+    auto l_cores = i_target.getChildren<TARGET_TYPE_CORE>();
+    uint8_t l_ordinal = 0;
+
+    for( auto coreItr = l_cores.begin(); coreItr != l_cores.end(); ++coreItr, ++l_ordinal )
+    {
+        // It is quite possible that this fused core bitset only has thread-bits set
+        // for one core or the other. Don't bother to call the control function if
+        // we don't have any threads to control.
+        const uint8_t l_thread_set = fapi2::thread_bitset_f2n(l_ordinal, i_threads);
+
+        if (l_thread_set != 0)
+        {
+            FAPI_TRY(p9_thread_control(*coreItr, l_thread_set, i_command,
+                                       i_warncheck, o_rasStatusReg, l_state));
+        }
+    }
+
+fapi_try_exit:
+    FAPI_INF("p9_thread_control : Exit (ex)");
+    return fapi2::current_err;
+}
+
+//--------------------------------------------------------------------------
+/// @brief p9_thread_control_sreset: utility subroutine to sreset a thread
+/// @param[in] i_target core target
+/// @param[in] i_threads normal core thread bitset (0b0000..0b1111)
+/// @param[in] i_warncheck convert pre/post checks errors to warnings
+/// @param[out] o_rasStatusReg  Complete RAS status reg 64-bit buffer.
+/// @return FAPI2_RC_SUCCESS if operation was successful,
+///         RC_P9_THREAD_CONTROL_SRESET_FAIL if the threads aren't running,
+///         else error
+//--------------------------------------------------------------------------
+fapi2::ReturnCode p9_thread_control_sreset(
+    const fapi2::Target<TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads, const bool i_warncheck,
+    fapi2::buffer<uint64_t>& o_rasStatusReg)
+{
+    FAPI_DBG("p9_thread_control_sreset : Initiating sreset command to core PC logic for threads 0x%x",
+             i_threads);
+    // No Precondition for Sreset; power management is handled by platform
+    // Setup & Initiate SReset Command
+    {
+        fapi2::buffer<uint64_t> l_scom_data(
+            g_control_reg_map[i_threads] >> SRESET_REQUEST);
+
+        FAPI_TRY(fapi2::putScom(i_target, C_DIRECT_CONTROLS, l_scom_data),
+                 "p9_thread_control_sreset: putScom error when issuing sp_sreset for threads 0x%x",
+                 i_threads);
+    }
+
+    // Post-conditions check
+    // TODO: Check for instructions having been executed?
+    {
+        bool l_running = false;
+        FAPI_TRY(threads_running(i_target, i_threads, o_rasStatusReg, l_running),
+                 "p9_thread_control_sreset: unable to determine if threads are running. threads: 0x%x",
+                 i_threads);
+
+        PTC_ASSERT_WARN(l_running == true,
+                        i_warncheck,
+                        fapi2::P9_THREAD_CONTROL_SRESET_FAIL()
+                        .set_CORE_TARGET(i_target)
+                        .set_THREAD(i_threads),
+                        "p9_thread_control_sreset: ERROR: Thread SRESET issued, but the threads aren't running. "
+                        "SReset might have failed for threads 0x%x", i_threads);
+    }
+
+    FAPI_INF("p9_thread_control_sreset : sreset command issued for threads 0x%x",
+             i_threads);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+//--------------------------------------------------------------------------
+/// @brief p9_thread_control_start: utility subroutine to start a thread
+/// @param[in] i_target core target
+/// @param[in] i_threads normal core thread bitset (0b0000..0b1111)
+/// @param[in] i_warncheck convert pre/post checks errors to warnings
+/// @param[out] o_rasStatusReg  Complete RAS status reg 64-bit buffer.
+/// @return FAPI2_RC_SUCCESS if operation was successful,
+///          RC_P9_THREAD_CONTROL_START_FAIL if start command failed,
+///         else error
+//--------------------------------------------------------------------------
+fapi2::ReturnCode p9_thread_control_start(
+    const fapi2::Target<TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads, const bool i_warncheck,
+    fapi2::buffer<uint64_t>& o_rasStatusReg)
+{
+    FAPI_DBG("p9_thread_control_start : Initiating start command to core PC logic for threads 0x%x",
+             i_threads);
+
+    // Preconditions: Only valid when in maint mode
+    {
+        bool l_in_maint = false;
+        FAPI_TRY(threads_in_maint(i_target, i_threads, o_rasStatusReg, l_in_maint),
+                 "p9_thread_control_start: unable to determine if threads are in maint mode. threads: 0x%x",
+                 i_threads);
+
+        PTC_ASSERT_WARN(l_in_maint == true,
+                        i_warncheck,
+                        fapi2::P9_THREAD_CONTROL_START_PRE_NOMAINT()
+                        .set_CORE_TARGET(i_target)
+                        .set_THREAD(i_threads),
+                        "p9_thread_control_start: ERROR: Cannot issue Thread Start because the threads aren't in maint mode (threads=%x).",
+                        i_threads);
+    }
+
+    // Start the threads
+    {
+        fapi2::buffer<uint64_t> l_scom_data(g_control_reg_map[i_threads] >> CORE_START);
+
+        FAPI_TRY(fapi2::putScom(i_target, C_DIRECT_CONTROLS, l_scom_data),
+                 "p9_thread_control_start: putScom error when issuing sp_start for threads 0x%x",
+                 i_threads);
+    }
+
+    // Post-conditions check
+    // TODO: Perhaps only run this section if i_warncheck==true to save an extranious scom
+    //       Verify understanding and desire for this funtionality before implementing in all thread_control functions
+    {
+        bool l_running = false;
+        FAPI_TRY(threads_running(i_target, i_threads, o_rasStatusReg, l_running),
+                 "p9_thread_control_start: unable to determine if threads are running. threads: 0x%x",
+                 i_threads);
+
+        PTC_ASSERT_WARN(l_running == true,
+                        i_warncheck,
+                        fapi2::P9_THREAD_CONTROL_START_FAIL()
+                        .set_CORE_TARGET(i_target)
+                        .set_THREAD(i_threads),
+                        "p9_thread_control_start: ERROR: Thread Start issued, but the threads aren't running. "
+                        "Start might have failed for threads 0x%x", i_threads);
+    }
+
+    FAPI_INF("p9_thread_control_start : start command issued for threads 0x%x",
+             i_threads);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+//--------------------------------------------------------------------------
+/// @brief p9_thread_control_stop: utility subroutine to stop a thread
+/// @param[in] i_target core target
+/// @param[in] i_threads normal core thread bitset (0b0000..0b1111)
+/// @param[in] i_warncheck convert pre/post checks errors to warnings
+/// @param[out] o_rasStatusReg  Complete RAS status reg 64-bit buffer.
+/// @return FAPI2_RC_SUCCESS if operation was successful,
+///          RC_P9_THREAD_CONTROL_STOP_FAIL if start command failed,
+///         else error
+//--------------------------------------------------------------------------
+fapi2::ReturnCode p9_thread_control_stop(
+    const fapi2::Target<TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads, const bool i_warncheck,
+    fapi2::buffer<uint64_t>& o_rasStatusReg)
+{
+    FAPI_DBG("p9_thread_control_stop : Initiating stop command to core PC logic for threads 0x%x",
+             i_threads);
+
+    // Pre-condition for stopping is that the threads are running (see figure 5.3 in the workbook)
+    // How to reconcile with 5.5.1 which says "invalid in maint mode?" Is that just a sub-precondition?
+    // TODO: Do we want to check to see if all threads are stopped and just bypass this if they are?
+    {
+        bool l_running = false;
+        FAPI_TRY(threads_running(i_target, i_threads, o_rasStatusReg, l_running),
+                 "p9_thread_control_stop: unable to determine if threads are running. threads: 0x%x",
+                 i_threads);
+
+        PTC_ASSERT_WARN(l_running == true,
+                        i_warncheck,
+                        fapi2::P9_THREAD_CONTROL_STOP_PRE_NOTRUNNING()
+                        .set_CORE_TARGET(i_target)
+                        .set_THREAD(i_threads),
+                        "p9_thread_control_stop: ERROR: Threads cannot be stopped because they aren't running (threads=%x).", i_threads);
+    }
+
+    // Stop the threads
+    {
+        fapi2::buffer<uint64_t> l_scom_data(g_control_reg_map[i_threads] >> CORE_STOP);
+
+        FAPI_TRY(fapi2::putScom(i_target, C_DIRECT_CONTROLS, l_scom_data),
+                 "p9_thread_control_stop: putScom error when issuing sp_stop for threads 0x%x",
+                 i_threads);
+    }
+
+    // Post-conditions check
+    {
+        bool l_stopped = false;
+        FAPI_TRY(threads_stopped(i_target, i_threads, o_rasStatusReg, l_stopped),
+                 "p9_thread_control_stop: unable to determine if threads are stopped. threads: 0x%x",
+                 i_threads);
+
+        PTC_ASSERT_WARN(l_stopped == true,
+                        i_warncheck,
+                        fapi2::P9_THREAD_CONTROL_STOP_FAIL()
+                        .set_CORE_TARGET(i_target)
+                        .set_THREAD(i_threads),
+                        "p9_thread_control_stop: ERROR: Thread Stop issued, but the threads are running. "
+                        "Stop might have failed for threads 0x%x", i_threads);
+    }
+
+    FAPI_INF("p9_thread_control_stop : stop command issued for threads 0x%x",
+             i_threads);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+//--------------------------------------------------------------------------
+/// @brief p9_thread_control_step: utility subroutine to single-instruction
+/// step a thread
+/// @param[in] i_target core target
+/// @param[in] i_threads normal core thread bitset (0b0000..0b1111)
+/// @param[in] i_warncheck convert pre/post checks errors to warnings
+/// @param[out] o_rasStatusReg  Complete RAS status reg 64-bit buffer.
+/// @return FAPI2_RC_SUCCESS if operation was successful,
+///          RC_P9_THREAD_CONTROL_STEP_FAIL if start command failed,
+///         else error
+//--------------------------------------------------------------------------
+fapi2::ReturnCode p9_thread_control_step(
+    const fapi2::Target<TARGET_TYPE_CORE>& i_target,
+    const uint8_t i_threads, const bool i_warncheck,
+    fapi2::buffer<uint64_t>& o_rasStatusReg)
+{
+    FAPI_DBG("p9_thread_control_stop : Initiating step command to core PC logic for threads 0x%x",
+             i_threads);
+
+    // Preconditions
+    {
+        bool l_step_ready = false;
+        FAPI_TRY(threads_step_ready(i_target, i_threads, o_rasStatusReg, l_step_ready),
+                 "p9_thread_control_step: unable to determine if threads are ready to step. threads: 0x%x",
+                 i_threads);
+
+        PTC_ASSERT_WARN(l_step_ready == true,
+                        i_warncheck,
+                        fapi2::P9_THREAD_CONTROL_STEP_PRE_NOTSTOPPING()
+                        .set_CORE_TARGET(i_target)
+                        .set_THREAD(i_threads),
+                        "p9_thread_control_step: ERROR: Thread cannot be stepped because they are not ready to step (threads=%x).", i_threads);
+    }
+
+
+    // Setup single step mode and issue step.
+    {
+        fapi2::buffer<uint64_t> l_mode_data;
+        fapi2::buffer<uint64_t> l_step_data(g_control_reg_map[i_threads] >> CORE_STEP);
+
+        // Set single step mode.
+        FAPI_TRY(fapi2::getScom(i_target, C_RAS_MODEREG, l_mode_data),
+                 "p9_thread_control_step: getScom error when reading ras_modreg for threads 0x%x",
+                 i_threads);
+
+        // i_threads is right aligned
+        l_mode_data |=
+            fapi2::buffer<uint64_t>().insertFromRight<RAS_MODE_STEP_SHIFT, 4>(i_threads);
+        FAPI_TRY(fapi2::putScom(i_target, C_RAS_MODEREG, l_mode_data),
+                 "p9_thread_control_step: putScom error when issuing ras_modreg step mode for threads 0x%x",
+                 i_threads);
+
+        // Set issue the step
+        FAPI_TRY(fapi2::putScom(i_target, C_DIRECT_CONTROLS, l_step_data),
+                 "p9_thread_control_step: putScom error when issuing step command for threads 0x%x",
+                 i_threads);
+    }
+
+
+    // Poll for completion.
+    {
+        bool l_step_done = false;
+        uint8_t l_governor = PTC_STEP_COMP_POLL_LIMIT;
+
+        do
+        {
+            FAPI_DBG("polling for step done. governor: %d", l_governor);
+            FAPI_TRY(threads_step_done(i_target, i_threads, o_rasStatusReg, l_step_done),
+                     "p9_thread_control_step: thread step issued but something went wrong polling for step_done for threads 0x%x",
+                     i_threads);
+        }
+        while((l_step_done != true) && l_governor--);
+
+        // We ran out of tries. If the scom failed, fapi_try kicked us out long ago.
+        PTC_ASSERT_WARN(l_governor != 0,
+                        i_warncheck,
+                        fapi2::P9_THREAD_CONTROL_STEP_FAIL()
+                        .set_CORE_TARGET(i_target)
+                        .set_THREAD(i_threads)
+                        .set_PTC_STEP_COMP_POLL_LIMIT(PTC_STEP_COMP_POLL_LIMIT),
+                        "p9_thread_control_stop: ERROR: Thread Step failed. Complete bits aren't set after %d poll atempts. WARNING: C_RAS_STATUS "
+                        "bit still in single instruction mode. Threads 0x%x", PTC_STEP_COMP_POLL_LIMIT,
+                        i_threads);
+    }
+
+
+    // Reset single step mode
+    {
+        fapi2::buffer<uint64_t> l_mode_data;
+
+        FAPI_TRY(fapi2::getScom(i_target, C_RAS_MODEREG, l_mode_data),
+                 "p9_thread_control_step: getScom error when reading ras_modreg for threads 0x%x",
+                 i_threads);
+
+        // i_threads is right aligned
+        l_mode_data &= ~
+                       (fapi2::buffer<uint64_t>().insertFromRight<RAS_MODE_STEP_SHIFT, 4>(i_threads));
+        FAPI_TRY(fapi2::putScom(i_target, C_RAS_MODEREG, l_mode_data),
+                 "p9_thread_control_step: putScom error when issuing ras_modreg step mode for threads 0x%x",
+                 i_threads);
+    }
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_thread_control.H b/src/import/chips/p9/procedures/hwp/core/p9_thread_control.H
new file mode 100755
index 00000000..14821a5c
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/core/p9_thread_control.H
@@ -0,0 +1,183 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/core/p9_thread_control.H $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+// *! TITLE       : p9_thread_control
+// *! DESCRIPTION : Core Thread start/stop/step/query/activate operations
+// *!               Use to start (start or sreset) thread instruction execution,
+// *!                 stop instruction execution, or single instruction step.
+// *!               Also used to query the state of a thread.
+//------------------------------------------------------------------------------
+
+// *HWP HWP Owner: Nick Klazynski <dyem@us.ibm.com>
+// *HWP FW Owner:  Thi Tran <thi@us.ibm.com>
+// *HWP Team:  Quad
+// *HWP Level: 2
+// *HWP Consumed by: FSP:HB:HS
+
+#ifndef _P9_THREAD_CONTROL_H_
+#define _P9_THREAD_CONTROL_H_
+
+#include <fapi2.H>
+#include <return_code.H>
+#include <error_scope.H>
+
+#include "p9_quad_scom_addresses.H"
+
+extern "C"
+{
+
+//------------------------------------------------------------------------------
+// Constants
+//------------------------------------------------------------------------------
+    const uint8_t MAX_NUM_OF_THREADS = 4;
+
+// THREAD_STATE bit definitions
+    const uint64_t THREAD_STATE_RUNNING            = 0x8000000000000000ULL;
+    const uint64_t THREAD_STATE_STOP               = 0x4000000000000000ULL;
+    const uint64_t THREAD_STATE_QUIESCED           = 0x2000000000000000ULL;
+    const uint64_t THREAD_STATE_MAINT              = 0x1000000000000000ULL;
+    const uint64_t THREAD_STATE_ICT_EMPTY          = 0x0800000000000000ULL;
+    const uint64_t THREAD_STATE_LSU_QUIESCED       = 0x0400000000000000ULL;
+    const uint64_t THREAD_STATE_ISTEP_SUCCESS      = 0x0200000000000000ULL;
+    const uint64_t THREAD_STATE_ISTEP_READY        = 0x0100000000000000ULL;
+
+// A macro to wrap the warning check boiler plate
+// If the action failed and i_warncheck is set add a trace and continue anyway
+#define PTC_ASSERT_WARN( __conditional__, __warning__, __ffdc__, ... )  \
+    if (! (__conditional__))                                            \
+    {                                                                   \
+        if (__warning__)                                                \
+        {                                                               \
+            FAPI_INF(__VA_ARGS__);                                      \
+        }                                                               \
+        else                                                            \
+        {                                                               \
+            (__ffdc__).execute();                                       \
+            FAPI_ERR(__VA_ARGS__);                                      \
+            goto fapi_try_exit;                                         \
+        }                                                               \
+    }                                                                   \
+
+
+// ProcThreadControl input commands
+// If you make this an enum, the compiler can
+// check that a case statement has all the elements
+// covered.
+    enum ThreadCommands
+    {
+        PTC_CMD_SRESET            = 0,
+        PTC_CMD_STEP              = 1,
+        PTC_CMD_START             = 2,
+        PTC_CMD_STOP              = 3,
+        PTC_CMD_QUERY             = 4,
+    };
+
+    enum ThreadRasStatus
+    {
+        CORE_MAINT_MODE = 0,
+        THREAD_QUIESCED = 1,
+        ICT_EMPTY       = 2,
+        LSU_QUIESCED    = 3,
+        STEP_SUCCESS    = 4,
+    };
+
+    enum PTC_Constants
+    {
+        RAS_MODE_STEP_SHIFT       = 52,
+        PTC_STEP_COMP_POLL_LIMIT  = 10,
+    };
+
+// Bit positions in the DIRECT_CONTROL register
+    enum ThreadControl
+    {
+        CLEAR_MAINT      = 3,
+        SRESET_REQUEST   = 4,
+        CORE_STEP        = 5,
+        CORE_START       = 6,
+        CORE_STOP        = 7,
+    };
+
+/// @typedef p9_thread_control_FP_t
+/// function pointer typedef definition for HWP call support
+    typedef fapi2::ReturnCode (*p9_thread_control_FP_t) (
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>&,
+        const uint8_t, const ThreadCommands, const bool,
+        fapi2::buffer<uint64_t>&, uint64_t&);
+
+//--------------------------------------------------------------------------
+/// @brief p9_thread_control: utility subroutine to control thread state
+/// @param[in] i_target ex target
+/// @param[in] i_threads fused thread bitset (0b00000000..0b11111111)
+/// @param[in] i_command  one of
+///               PTC_CMD_SRESET => initiate sreset thread command
+///               PTC_CMD_START  => initiate start thread command
+///               PTC_CMD_STOP   => initiate stop thread command
+///               PTC_CMD_STEP   => initiate step thread command
+///               PTC_CMD_QUERY  => query and return thread state
+/// @param[in] i_warncheck convert pre/post checks errors to warnings
+/// @return FAPI_RC_SUCCESS if operation was successful,
+///         function-specific fail codes (see function definitions),
+///         else error
+//-------------------------------------------------------------------------
+//fapi2::ReturnCode p9_thread_control(const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target,
+//        const uint8_t i_threads, const ThreadCommands i_command,
+//        const bool i_warncheck);
+
+//--------------------------------------------------------------------------
+/// @brief p9_thread_control: utility subroutine to control thread state
+///
+/// @param[in] i_target core target
+/// @param[in] i_threads     Desired thread bit set, multiple thread settings
+///                          are allowed.
+///                             0b0000         No thread (No-op)
+///                             0b1000         Thread 0
+///                             0b0100         Thread 1
+///                             0b0010         Thread 2
+///                             0b0001         Thread 3
+/// @param[in] i_command  one of
+///               PTC_CMD_SRESET => initiate sreset thread command
+///               PTC_CMD_START  => initiate start thread command
+///               PTC_CMD_STOP   => initiate stop thread command
+///               PTC_CMD_STEP   => initiate step thread command
+///               PTC_CMD_QUERY  => query and return thread state
+/// @param[in] i_warncheck convert pre/post checks errors to warnings
+/// @param[out] o_rasStatusReg  Complete RAS status reg 64-bit buffer after
+///                             executing command.
+/// @param[out] o_state Thread state, only valid for PTC_CMD_QUERY command.
+///                    See p9_thread_control.H for THREAD_STATE bit definitions.
+///
+/// @return FAPI_RC_SUCCESS if operation was successful,
+///         function-specific fail codes (see function definitions),
+///         else error
+//--------------------------------------------------------------------------
+    fapi2::ReturnCode p9_thread_control(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target,
+                                        const uint8_t i_threads, const ThreadCommands i_command,
+                                        const bool i_warncheck,
+                                        fapi2::buffer<uint64_t>& o_rasStatusReg,
+                                        uint64_t& o_state);
+
+} // extern
+
+#endif // _P9_THREAD_CONTROL_H_
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/Makefile b/src/import/chips/p9/procedures/hwp/initfiles/Makefile
new file mode 100644
index 00000000..123518a1
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/initfiles/Makefile
@@ -0,0 +1,54 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/hwp/initfiles/Makefile $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+# This Makefile compiles all of the initfiles hardware procedure code. See the
+# "initfiles.mk" file in this directory.
+
+#all generated files from this makefile will end up in obj/initfiles
+export SUB_OBJDIR = /initfiles
+
+include img_defs.mk
+include initfiles.mk
+
+
+OBJS := $(addprefix $(OBJDIR)/, $(INITFILES_OBJECTS))
+
+libinitfiles.a: initfiles
+	$(AR) crs $(OBJDIR)/libinitfiles.a $(OBJDIR)/*.o
+
+.PHONY: clean initfiles
+initfiles: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+clean:
+	rm -fr $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d)
+endif
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/initfiles.mk b/src/import/chips/p9/procedures/hwp/initfiles/initfiles.mk
new file mode 100644
index 00000000..9703f3e3
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/initfiles/initfiles.mk
@@ -0,0 +1,43 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/hwp/initfiles/initfiles.mk $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file initfiles.mk
+#
+#  @brief mk for including initfile object files
+#
+##########################################################################
+# Object Files
+##########################################################################
+
+INITFILES-CPP-SOURCES += p9_ncu_scom.C
+INITFILES-CPP-SOURCES += p9_l2_scom.C
+INITFILES-CPP-SOURCES += p9_l3_scom.C
+
+INITFILES-C-SOURCES   +=
+INITFILES-S-SOURCES   +=
+
+INITFILES_OBJECTS     += $(INITFILES-CPP-SOURCES:.C=.o)
+INITFILES_OBJECTS     += $(INITFILES-C-SOURCES:.c=.o)
+INITFILES_OBJECTS     += $(INITFILES-S-SOURCES:.S=.o)
+
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.C
new file mode 100644
index 00000000..e85d8585
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.C
@@ -0,0 +1,294 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.C $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#include "p9_l2_scom.H"
+#include <stdint.h>
+#include <stddef.h>
+#include <fapi2.H>
+
+using namespace fapi2;
+
+constexpr auto literal_0b0001 = 0b0001;
+constexpr auto literal_0b0100 = 0b0100;
+constexpr auto literal_0 = 0;
+constexpr auto literal_0x001 = 0x001;
+constexpr auto literal_0b0000 = 0b0000;
+
+fapi2::ReturnCode p9_l2_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
+                             const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1)
+{
+    fapi2::ReturnCode l_rc = 0;
+
+    do
+    {
+        fapi2::buffer<uint64_t> l_scom_buffer;
+        fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE_Type l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE;
+        l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE);
+
+        if (l_rc)
+        {
+            FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_FABRIC_ADDR_BAR_MODE)");
+            break;
+        }
+
+        fapi2::ATTR_SYSTEM_IPL_PHASE_Type l_TGT1_ATTR_SYSTEM_IPL_PHASE;
+        l_rc = FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, TGT1, l_TGT1_ATTR_SYSTEM_IPL_PHASE);
+
+        if (l_rc)
+        {
+            FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_SYSTEM_IPL_PHASE)");
+            break;
+        }
+
+        {
+            l_rc = fapi2::getScom( TGT0, 0x1001080aull, l_scom_buffer );
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: getScom (0x1001080aull)");
+                break;
+            }
+
+            {
+                if ((l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_SMALL_SYSTEM))
+                {
+                    constexpr auto l_EXP_L2_L2MISC_L2CERRS_CFG_SYSMAP_SM_NOT_LG_SEL_ON = 0x1;
+                    l_scom_buffer.insert<uint64_t> (l_EXP_L2_L2MISC_L2CERRS_CFG_SYSMAP_SM_NOT_LG_SEL_ON, 23, 1, 63 );
+                }
+                else if ((l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_LARGE_SYSTEM))
+                {
+                    constexpr auto l_EXP_L2_L2MISC_L2CERRS_CFG_SYSMAP_SM_NOT_LG_SEL_OFF = 0x0;
+                    l_scom_buffer.insert<uint64_t> (l_EXP_L2_L2MISC_L2CERRS_CFG_SYSMAP_SM_NOT_LG_SEL_OFF, 23, 1, 63 );
+                }
+            }
+
+            {
+                if ((l_TGT1_ATTR_SYSTEM_IPL_PHASE == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_RUNTIME))
+                {
+                    constexpr auto l_EXP_L2_L2MISC_L2CERRS_CFG_HASH_L3_ADDR_EN_ON = 0x1;
+                    l_scom_buffer.insert<uint64_t> (l_EXP_L2_L2MISC_L2CERRS_CFG_HASH_L3_ADDR_EN_ON, 21, 1, 63 );
+                }
+            }
+
+            {
+                if ((l_TGT1_ATTR_SYSTEM_IPL_PHASE == ENUM_ATTR_SYSTEM_IPL_PHASE_HB_RUNTIME))
+                {
+                    constexpr auto l_EXP_L2_L2MISC_L2CERRS_CFG_CAC_ERR_REPAIR_EN_ON = 0x1;
+                    l_scom_buffer.insert<uint64_t> (l_EXP_L2_L2MISC_L2CERRS_CFG_CAC_ERR_REPAIR_EN_ON, 15, 1, 63 );
+                }
+            }
+
+            l_rc = fapi2::putScom(TGT0, 0x1001080aull, l_scom_buffer);
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: putScom (0x1001080aull)");
+                break;
+            }
+        }
+
+        {
+            l_rc = fapi2::getScom( TGT0, 0x1001080bull, l_scom_buffer );
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: getScom (0x1001080bull)");
+                break;
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0b0001, 4, 4, 60 );
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0b0100, 8, 4, 60 );
+            }
+
+            l_rc = fapi2::putScom(TGT0, 0x1001080bull, l_scom_buffer);
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: putScom (0x1001080bull)");
+                break;
+            }
+        }
+
+        fapi2::ATTR_PROC_EPS_READ_CYCLES_T0_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0;
+        l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0);
+
+        if (l_rc)
+        {
+            FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_READ_CYCLES_T0)");
+            break;
+        }
+
+        fapi2::ATTR_PROC_EPS_READ_CYCLES_T1_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1;
+        l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T1, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1);
+
+        if (l_rc)
+        {
+            FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_READ_CYCLES_T1)");
+            break;
+        }
+
+        fapi2::ATTR_PROC_EPS_READ_CYCLES_T2_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2;
+        l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2);
+
+        if (l_rc)
+        {
+            FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_READ_CYCLES_T2)");
+            break;
+        }
+
+        {
+            l_rc = fapi2::getScom( TGT0, 0x10010810ull, l_scom_buffer );
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: getScom (0x10010810ull)");
+                break;
+            }
+
+            {
+                if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0 != literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0, 0, 12, 52 );
+                }
+                else if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0 == literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (literal_0x001, 0, 12, 52 );
+                }
+            }
+
+            {
+                if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1 != literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1, 12, 12, 52 );
+                }
+                else if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1 == literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (literal_0x001, 12, 12, 52 );
+                }
+            }
+
+            {
+                if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2 != literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2, 24, 12, 52 );
+                }
+                else if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2 == literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (literal_0x001, 24, 12, 52 );
+                }
+            }
+
+            l_rc = fapi2::putScom(TGT0, 0x10010810ull, l_scom_buffer);
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: putScom (0x10010810ull)");
+                break;
+            }
+        }
+
+        fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1_Type l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1;
+        l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1, TGT1, l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1);
+
+        if (l_rc)
+        {
+            FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_WRITE_CYCLES_T1)");
+            break;
+        }
+
+        fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2_Type l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2;
+        l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2, TGT1, l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2);
+
+        if (l_rc)
+        {
+            FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_WRITE_CYCLES_T2)");
+            break;
+        }
+
+        {
+            l_rc = fapi2::getScom( TGT0, 0x10010811ull, l_scom_buffer );
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: getScom (0x10010811ull)");
+                break;
+            }
+
+            {
+                if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1 != literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1, 0, 12, 52 );
+                }
+                else if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1 == literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (literal_0x001, 0, 12, 52 );
+                }
+            }
+
+            {
+                if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2 != literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2, 12, 12, 52 );
+                }
+                else if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2 == literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (literal_0x001, 12, 12, 52 );
+                }
+            }
+
+            {
+                constexpr auto l_EXP_L2_L2MISC_L2CERRS_EPS_CNT_USE_L2_DIVIDER_EN_OFF = 0x0;
+                l_scom_buffer.insert<uint64_t> (l_EXP_L2_L2MISC_L2CERRS_EPS_CNT_USE_L2_DIVIDER_EN_OFF, 29, 1, 63 );
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0b0000, 30, 4, 60 );
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0b0001, 24, 4, 60 );
+            }
+
+            {
+                constexpr auto l_EXP_L2_L2MISC_L2CERRS_EPS_MODE_SEL_MODE1 = 0x0;
+                l_scom_buffer.insert<uint64_t> (l_EXP_L2_L2MISC_L2CERRS_EPS_MODE_SEL_MODE1, 28, 1, 63 );
+            }
+
+            l_rc = fapi2::putScom(TGT0, 0x10010811ull, l_scom_buffer);
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: putScom (0x10010811ull)");
+                break;
+            }
+        }
+    }
+    while (0);
+
+    return l_rc;
+}
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.H b/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.H
new file mode 100644
index 00000000..69653c03
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.H
@@ -0,0 +1,45 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/initfiles/p9_l2_scom.H $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef _INIT_P9_L2_SCOM_PROCEDURE_H_
+#define _INIT_P9_L2_SCOM_PROCEDURE_H_
+
+
+#include <stddef.h>
+#include <stdint.h>
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_l2_scom_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_EX>&,
+        const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&);
+
+extern "C"
+{
+
+    fapi2::ReturnCode p9_l2_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
+                                 const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1);
+
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C
new file mode 100644
index 00000000..1186e9d2
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C
@@ -0,0 +1,279 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#include "p9_l3_scom.H"
+#include <stdint.h>
+#include <stddef.h>
+#include <fapi2.H>
+
+using namespace fapi2;
+
+constexpr auto literal_0 = 0;
+constexpr auto literal_0x001 = 0x001;
+constexpr auto literal_0b0 = 0b0;
+constexpr auto literal_0b0000 = 0b0000;
+constexpr auto literal_0b0001 = 0b0001;
+constexpr auto literal_0b0100 = 0b0100;
+
+fapi2::ReturnCode p9_l3_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
+                             const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1)
+{
+    fapi2::ReturnCode l_rc = 0;
+
+    do
+    {
+        fapi2::buffer<uint64_t> l_scom_buffer;
+        fapi2::ATTR_PROC_EPS_READ_CYCLES_T0_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0;
+        l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0);
+
+        if (l_rc)
+        {
+            FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_READ_CYCLES_T0)");
+            break;
+        }
+
+        fapi2::ATTR_PROC_EPS_READ_CYCLES_T1_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1;
+        l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T1, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1);
+
+        if (l_rc)
+        {
+            FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_READ_CYCLES_T1)");
+            break;
+        }
+
+        fapi2::ATTR_PROC_EPS_READ_CYCLES_T2_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2;
+        l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2);
+
+        if (l_rc)
+        {
+            FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_READ_CYCLES_T2)");
+            break;
+        }
+
+        {
+            l_rc = fapi2::getScom( TGT0, 0x10011829ull, l_scom_buffer );
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: getScom (0x10011829ull)");
+                break;
+            }
+
+            {
+                if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0 != literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0, 0, 12, 52 );
+                }
+                else if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0 == literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (literal_0x001, 0, 12, 52 );
+                }
+            }
+
+            {
+                if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1 != literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1, 12, 12, 52 );
+                }
+                else if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1 == literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (literal_0x001, 12, 12, 52 );
+                }
+            }
+
+            {
+                if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2 != literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2, 24, 12, 52 );
+                }
+                else if ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2 == literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (literal_0x001, 24, 12, 52 );
+                }
+            }
+
+            l_rc = fapi2::putScom(TGT0, 0x10011829ull, l_scom_buffer);
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: putScom (0x10011829ull)");
+                break;
+            }
+        }
+
+        fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1_Type l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1;
+        l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T1, TGT1, l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1);
+
+        if (l_rc)
+        {
+            FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_WRITE_CYCLES_T1)");
+            break;
+        }
+
+        fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2_Type l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2;
+        l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_WRITE_CYCLES_T2, TGT1, l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2);
+
+        if (l_rc)
+        {
+            FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_EPS_WRITE_CYCLES_T2)");
+            break;
+        }
+
+        {
+            l_rc = fapi2::getScom( TGT0, 0x1001182aull, l_scom_buffer );
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: getScom (0x1001182aull)");
+                break;
+            }
+
+            {
+                if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1 != literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1, 0, 12, 52 );
+                }
+                else if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T1 == literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (literal_0x001, 0, 12, 52 );
+                }
+            }
+
+            {
+                if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2 != literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2, 12, 12, 52 );
+                }
+                else if ((l_TGT1_ATTR_PROC_EPS_WRITE_CYCLES_T2 == literal_0))
+                {
+                    l_scom_buffer.insert<uint64_t> (literal_0x001, 12, 12, 52 );
+                }
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0b0, 34, 1, 63 );
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0b0000, 26, 4, 60 );
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0b0001, 30, 4, 60 );
+            }
+
+            l_rc = fapi2::putScom(TGT0, 0x1001182aull, l_scom_buffer);
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: putScom (0x1001182aull)");
+                break;
+            }
+        }
+
+        fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE_Type l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE;
+        l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE);
+
+        if (l_rc)
+        {
+            FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_FABRIC_ADDR_BAR_MODE)");
+            break;
+        }
+
+        fapi2::ATTR_SYSTEM_IPL_PHASE_Type l_TGT1_ATTR_SYSTEM_IPL_PHASE;
+        l_rc = FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, TGT1, l_TGT1_ATTR_SYSTEM_IPL_PHASE);
+
+        if (l_rc)
+        {
+            FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_SYSTEM_IPL_PHASE)");
+            break;
+        }
+
+        {
+            l_rc = fapi2::getScom( TGT0, 0x1001182bull, l_scom_buffer );
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: getScom (0x1001182bull)");
+                break;
+            }
+
+            {
+                if ((l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_SMALL_SYSTEM))
+                {
+                    constexpr auto l_EXP_L3_L3_MISC_L3CERRS_L3_SYSMAP_SM_NOT_LG_SEL_ON = 0x1;
+                    l_scom_buffer.insert<uint64_t> (l_EXP_L3_L3_MISC_L3CERRS_L3_SYSMAP_SM_NOT_LG_SEL_ON, 22, 1, 63 );
+                }
+                else if ((l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_LARGE_SYSTEM))
+                {
+                    constexpr auto l_EXP_L3_L3_MISC_L3CERRS_L3_SYSMAP_SM_NOT_LG_SEL_OFF = 0x0;
+                    l_scom_buffer.insert<uint64_t> (l_EXP_L3_L3_MISC_L3CERRS_L3_SYSMAP_SM_NOT_LG_SEL_OFF, 22, 1, 63 );
+                }
+            }
+
+            {
+                if ((l_TGT1_ATTR_SYSTEM_IPL_PHASE == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_RUNTIME))
+                {
+                    constexpr auto l_EXP_L3_L3_MISC_L3CERRS_L3_ADDR_HASH_EN_CFG_ON = 0x1;
+                    l_scom_buffer.insert<uint64_t> (l_EXP_L3_L3_MISC_L3CERRS_L3_ADDR_HASH_EN_CFG_ON, 11, 1, 63 );
+                }
+            }
+
+            {
+                if ((l_TGT1_ATTR_SYSTEM_IPL_PHASE == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_RUNTIME))
+                {
+                    constexpr auto l_EXP_L3_L3_MISC_L3CERRS_L3_RDSN_LINEDEL_UE_EN_ON = 0x1;
+                    l_scom_buffer.insert<uint64_t> (l_EXP_L3_L3_MISC_L3CERRS_L3_RDSN_LINEDEL_UE_EN_ON, 2, 1, 63 );
+                }
+            }
+
+            {
+                if ((l_TGT1_ATTR_SYSTEM_IPL_PHASE == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_RUNTIME))
+                {
+                    constexpr auto l_EXP_L3_L3_MISC_L3CERRS_L3_DMAP_CI_EN_CFG_OFF = 0x0;
+                    l_scom_buffer.insert<uint64_t> (l_EXP_L3_L3_MISC_L3CERRS_L3_DMAP_CI_EN_CFG_OFF, 1, 1, 63 );
+                }
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0b0001, 14, 4, 60 );
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0b0100, 18, 4, 60 );
+            }
+
+            l_rc = fapi2::putScom(TGT0, 0x1001182bull, l_scom_buffer);
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: putScom (0x1001182bull)");
+                break;
+            }
+        }
+    }
+    while (0);
+
+    return l_rc;
+}
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.H b/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.H
new file mode 100644
index 00000000..8f8edb08
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.H
@@ -0,0 +1,45 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.H $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef _INIT_P9_L3_SCOM_PROCEDURE_H_
+#define _INIT_P9_L3_SCOM_PROCEDURE_H_
+
+
+#include <stddef.h>
+#include <stdint.h>
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_l3_scom_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_EX>&,
+        const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&);
+
+extern "C"
+{
+
+    fapi2::ReturnCode p9_l3_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
+                                 const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1);
+
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C
new file mode 100644
index 00000000..950a088d
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C
@@ -0,0 +1,130 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.C $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#include "p9_ncu_scom.H"
+#include <stdint.h>
+#include <stddef.h>
+#include <fapi2.H>
+
+using namespace fapi2;
+
+constexpr auto literal_0b0001 = 0b0001;
+constexpr auto literal_0b0100 = 0b0100;
+constexpr auto literal_0x8 = 0x8;
+constexpr auto literal_0x10 = 0x10;
+
+fapi2::ReturnCode p9_ncu_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
+                              const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1)
+{
+    fapi2::ReturnCode l_rc = 0;
+
+    do
+    {
+        fapi2::buffer<uint64_t> l_scom_buffer;
+        fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE_Type l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE;
+        l_rc = FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE);
+
+        if (l_rc)
+        {
+            FAPI_ERR("ERROR executing: FAPI_ATTR_GET (ATTR_PROC_FABRIC_ADDR_BAR_MODE)");
+            break;
+        }
+
+        {
+            l_rc = fapi2::getScom( TGT0, 0x1001100aull, l_scom_buffer );
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: getScom (0x1001100aull)");
+                break;
+            }
+
+            {
+                if ((l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_SMALL_SYSTEM))
+                {
+                    constexpr auto l_EXP_NC_NCMISC_NCSCOMS_SYSMAP_SM_NOT_LG_SEL_ON = 0x1;
+                    l_scom_buffer.insert<uint64_t> (l_EXP_NC_NCMISC_NCSCOMS_SYSMAP_SM_NOT_LG_SEL_ON, 9, 1, 63 );
+                }
+                else if ((l_TGT1_ATTR_PROC_FABRIC_ADDR_BAR_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_LARGE_SYSTEM))
+                {
+                    constexpr auto l_EXP_NC_NCMISC_NCSCOMS_SYSMAP_SM_NOT_LG_SEL_OFF = 0x0;
+                    l_scom_buffer.insert<uint64_t> (l_EXP_NC_NCMISC_NCSCOMS_SYSMAP_SM_NOT_LG_SEL_OFF, 9, 1, 63 );
+                }
+            }
+
+            l_rc = fapi2::putScom(TGT0, 0x1001100aull, l_scom_buffer);
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: putScom (0x1001100aull)");
+                break;
+            }
+        }
+
+        {
+            l_rc = fapi2::getScom( TGT0, 0x1001100bull, l_scom_buffer );
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: getScom (0x1001100bull)");
+                break;
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0b0001, 0, 4, 60 );
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0b0100, 4, 4, 60 );
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0x8, 8, 10, 54 );
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0x10, 26, 10, 54 );
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0x8, 18, 4, 60 );
+            }
+
+            {
+                l_scom_buffer.insert<uint64_t> (literal_0x8, 22, 4, 60 );
+            }
+
+            l_rc = fapi2::putScom(TGT0, 0x1001100bull, l_scom_buffer);
+
+            if (l_rc)
+            {
+                FAPI_ERR("ERROR executing: putScom (0x1001100bull)");
+                break;
+            }
+        }
+    }
+    while (0);
+
+    return l_rc;
+}
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.H b/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.H
new file mode 100644
index 00000000..bc56a154
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.H
@@ -0,0 +1,45 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/initfiles/p9_ncu_scom.H $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef _INIT_P9_NCU_SCOM_PROCEDURE_H_
+#define _INIT_P9_NCU_SCOM_PROCEDURE_H_
+
+
+#include <stddef.h>
+#include <stdint.h>
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_ncu_scom_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_EX>&,
+        const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&);
+
+extern "C"
+{
+
+    fapi2::ReturnCode p9_ncu_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0,
+                                  const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1);
+
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/lib/Makefile b/src/import/chips/p9/procedures/hwp/lib/Makefile
new file mode 100644
index 00000000..059fb2f3
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/lib/Makefile
@@ -0,0 +1,54 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/hwp/lib/Makefile $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+# This Makefile compiles all of the common library hardware procedure code.
+# See the "libcommonfiles.mk" file in this directory.
+
+#all generated files from this makefile will end up in obj/lib
+export SUB_OBJDIR = /lib
+
+include img_defs.mk
+include libcommonfiles.mk
+
+
+OBJS := $(addprefix $(OBJDIR)/, $(LIB_OBJECTS))
+
+libcommon.a: lib
+	$(AR) crs $(OBJDIR)/libcommon.a $(OBJDIR)/*.o
+
+.PHONY: clean lib
+lib: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+clean:
+	rm -fr $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d)
+endif
diff --git a/src/import/chips/p9/procedures/hwp/lib/libcommonfiles.mk b/src/import/chips/p9/procedures/hwp/lib/libcommonfiles.mk
new file mode 100644
index 00000000..cbcd12ee
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/lib/libcommonfiles.mk
@@ -0,0 +1,42 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/hwp/lib/libcommonfiles.mk $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file libcommonfiles.mk
+#
+#  @brief mk for including library common object files
+#
+##########################################################################
+# Object Files
+##########################################################################
+
+LIB-CPP-SOURCES += p9_common_poweronoff.C
+LIB-CPP-SOURCES += p9_common_pro_epi_log.C
+
+LIB-C-SOURCES   +=
+LIB-S-SOURCES   +=
+
+LIB_OBJECTS     += $(LIB-CPP-SOURCES:.C=.o)
+LIB_OBJECTS     += $(LIB-C-SOURCES:.c=.o)
+LIB_OBJECTS     += $(LIB-S-SOURCES:.S=.o)
+
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C
new file mode 100644
index 00000000..52916b7f
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C
@@ -0,0 +1,527 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.C $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_common_poweronoff.C
+/// @brief common procedure for power on/off
+///
+/// Procedure Summary:
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE:CME
+// *HWP Level              : 2
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <p9_quad_scom_addresses.H>
+#include "p9_hcd_common.H"
+#include "p9_common_poweronoff.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions:
+//------------------------------------------------------------------------------
+// Define only address offset to be compatible with both core and cache domain
+
+const uint64_t NET_CTRL0_WOR[2] = { C_NET_CTRL0_WOR,
+                                    EQ_NET_CTRL0_WOR
+                                  };
+
+const uint64_t PPM_PFCS[2]     = { C_PPM_PFCS_SCOM,
+                                   EQ_PPM_PFCS_SCOM
+                                 };
+
+const uint64_t PPM_PFCS_CLR[2] = { C_PPM_PFCS_SCOM1,
+                                   EQ_PPM_PFCS_SCOM1
+                                 };
+
+const uint64_t PPM_PFCS_OR[2] = { C_PPM_PFCS_SCOM2,
+                                  EQ_PPM_PFCS_SCOM2
+                                };
+
+const uint64_t PPM_PFDLY[2] =   { C_PPM_PFDLY,
+                                  EQ_PPM_PFDLY
+                                };
+
+const uint64_t PPM_PFSNS[2] =   { C_PPM_PFSNS,
+                                  EQ_PPM_PFSNS
+                                };
+
+enum { FSM_IDLE_POLLING_HW_NS_DELAY = 10000,
+       FSM_IDLE_POLLING_SIM_CYCLE_DELAY = 80000,
+       PFET_STATE_LENGTH = 2,
+       VXX_PG_SEL_LEN = 4
+     };
+
+enum pfetRegField { PFET_NOP = 0,
+                    PFET_FORCE_VOFF = 1,
+                    PFET_NOP_RESERVERD = 2,
+                    PFET_FORCE_VON = 3
+                  };
+
+enum pgStateOffset { PG_STATE_IDLE_OFFSET = 0,
+                     PG_STATE_INC_OFFSET = 1,
+                     PG_STATE_DEC_OFFSET = 2,
+                     PG_STATE_WAIT_OFFSET = 3
+                   };
+
+
+enum PFCS_Bits { VDD_PFET_FORCE_STATE_BIT = 0,
+                 VCS_PFET_FORCE_STATE_BIT = 2,
+                 VDD_PFET_VAL_OVERRIDE_BIT = 4,
+                 VDD_PFET_SEL_OVERRIDE_BIT = 5,
+                 VCS_PFET_VAL_OVERRIDE_BIT = 6,
+                 VCS_PFET_SEL_OVERRIDE_BIT = 7,
+                 VDD_PFET_REGULATION_FINGER_EN_BIT = 8,
+                 VDD_PFET_REGULATION_FINGER_VALUE_BIT = 9,
+                 RESERVED1_BIT = 10,
+                 VDD_PFET_ENABLE_VALUE_BIT = 12,
+                 VDD_PFET_SEL_VALUE_BIT = 20,
+                 VCS_PFET_ENABLE_VALUE_BIT = 24,
+                 VCS_PFET_SEL_VALUE_BIT = 32,
+                 RESERVED2_BIT = 36,
+                 VDD_PG_STATE_BIT = 42,
+                 VDD_PG_SEL_BIT = 46,
+                 VCS_PG_STATE_BIT = 50,
+                 VCS_PG_SEL_BIT = 54,
+                 RESERVED3_BIT = 58
+               };
+
+
+enum { VDD_PFETS_ENABLED_SENSE_BIT = 0,
+       VDD_PFETS_DISABLED_SENSE_BIT = 1,
+       VCS_PFETS_ENABLED_SENSE_BIT = 2,
+       VCS_PFETS_DISABLED_SENSE_BIT = 3
+     };
+
+enum { POWDN_DLY_BIT = 0,
+       POWUP_DLY_BIT = 4,
+       TP_VDD_PFET_ENABLE_ACTUAL_BIT = 16,
+       TP_VCS_PFET_ENABLE_ACTUAL_BIT = 24
+     };
+
+enum { POWDN_DLY_LENGTH = 4,
+       POWUP_DLY_LENGTH = 4,
+       TP_VDD_PFET_ENABLE_ACTUAL_LENGTH = 8,
+       TP_VCS_PFET_ENABLE_ACTUAL_LENGTH = 8
+     };
+
+// i_operation defines
+
+
+//------------------------------------------------------------------------------
+// Procedure:
+//------------------------------------------------------------------------------
+template <fapi2::TargetType K>
+fapi2::ReturnCode
+p9_common_poweronoff(
+    const fapi2::Target<K>& i_target,
+    const p9power::powerOperation_t i_operation)
+{
+    uint32_t l_loopsPerMs;
+
+    FAPI_INF(">>p9_common_poweronoff: %d",  i_operation);
+    uint32_t l_type = 0;  // Assumes core
+
+    if((i_target.getType() & fapi2::TARGET_TYPE_EQ))
+    {
+        l_type = 1;
+    }
+
+    fapi2::buffer<uint64_t> l_data;
+    fapi2::buffer<uint64_t> l_temp;  // extractToRight seems the require space to write into.
+    ///////////////////////////////////////////////////////////////////////////
+    // lambda functions for poweronoff procedure
+    ///////////////////////////////////////////////////////////////////////////
+    auto pollVddFSMIdle = [&] ()
+    {
+        //   Poll for PFETCNTLSTAT_REG[VDD_PG_STATE] for 0b1000 (FSM idle)
+        //      – Timeout value = 1ms
+        FAPI_DBG("Polling for power gate sequencer state: FSM idle");
+        l_loopsPerMs = 1E6 / FSM_IDLE_POLLING_HW_NS_DELAY;
+
+        // Note that the Lamda assumes that l_data already contains the
+        do
+        {
+            fapi2::delay(FSM_IDLE_POLLING_HW_NS_DELAY,
+                         FSM_IDLE_POLLING_SIM_CYCLE_DELAY);
+
+            FAPI_TRY(fapi2::getScom(i_target, PPM_PFCS[l_type], l_data),
+                     "getScom failed for address PPM_PFCS"); // poll
+            FAPI_DBG("timeout l_loopsPerMs. %x", l_loopsPerMs);
+        }
+        while ((l_data.getBit < VDD_PG_STATE_BIT + PG_STATE_IDLE_OFFSET > ()
+                == 0 ) && (--l_loopsPerMs != 0));
+
+        /*
+                do
+                {
+                    FAPI_TRY(fapi2::getScom(i_target, PPM_PFSNS[l_type], l_data),
+                             "getScom failed for address PPM_PFSNS"); // poll
+                }
+                while ((l_data.getBit<0>() == 0 ) && (--l_loopsPerMs != 0));
+        */
+        FAPI_ASSERT((l_loopsPerMs != 0),
+                    fapi2::PMPROC_PFETLIB_TIMEOUT()
+                    .set_ADDRESS(PPM_PFCS[l_type]),
+                    "VDD FSM idle timeout");
+
+        ///  (Optional) Check PFETCNTLSTAT_REG[VDD_PG_SEL]being 0x8
+        //              (Off encode point)
+#if 0  // this field does not get set yet
+        l_data.extractToRight<VDD_PG_SEL_BIT, VXX_PG_SEL_LEN>(l_temp);
+        FAPI_ASSERT((l_temp == 8),
+                    fapi2::PROCPM_PFET_CODE_BAD_MODE(),
+                    "VDD_PG_SEL != 8: l_temp %0x", l_temp);
+
+#endif
+    fapi_try_exit:
+        return fapi2::current_err;
+    };
+
+    auto pollVcsFSMIdle = [&] ()
+    {
+        //   Poll for PFETCNTLSTAT_REG[VCS_PG_STATE] for 0b1000 (FSM idle)
+        //      – Timeout value = 1ms
+        FAPI_DBG("Polling for power gate sequencer state: FSM idle");
+        l_loopsPerMs = 1E6 / FSM_IDLE_POLLING_HW_NS_DELAY;
+
+        do
+        {
+            fapi2::delay(FSM_IDLE_POLLING_HW_NS_DELAY,
+                         FSM_IDLE_POLLING_SIM_CYCLE_DELAY);
+
+            FAPI_TRY(fapi2::getScom(i_target, PPM_PFCS[l_type], l_data),
+                     "getScom failed for address PPM_PFCS");  // poll
+            //FAPI_DBG("timeout l_loopsPerMs. %x", l_loopsPerMs);
+        }
+        while ((l_data.getBit < VCS_PG_STATE_BIT + PG_STATE_IDLE_OFFSET > ()
+                == 0 ) && (--l_loopsPerMs != 0));
+
+        /*
+                do
+                {
+                    FAPI_TRY(fapi2::getScom(i_target, PPM_PFSNS[l_type], l_data),
+                             "getScom failed for address PPM_PFSNS");  // poll
+                }
+                while ((l_data.getBit<2>() == 0 ) && (--l_loopsPerMs != 0));
+        */
+        FAPI_ASSERT((l_loopsPerMs != 0),
+                    fapi2::PMPROC_PFETLIB_TIMEOUT()
+                    .set_ADDRESS(PPM_PFCS[l_type]),
+                    "VCS FSM idle timeout");
+
+        //   (Optional) Check PFETCNTLSTAT_REG[VDD_PG_SEL]
+        //              being 0x8 (Off encode point)
+
+
+#if 0  // this field does not get set yet
+        l_data.extractToRight<VCS_PG_SEL_BIT, VXX_PG_SEL_LEN>(l_temp);
+        FAPI_ASSERT((l_temp == 8),
+                    fapi2::PROCPM_PFET_CODE_BAD_MODE(),
+                    "VCS_PG_SEL != 8: l_temp %0x", l_temp);
+
+#endif
+    fapi_try_exit:
+        return fapi2::current_err;
+
+    };
+
+
+    auto powerOnVdd = [&] ()
+    {
+        // Command the cache PFET controller to power-on
+        //   Write PFETCNTLSTAT_REG:
+        //     vdd_pfet_force_state = 11 (Force Von)
+        //     vdd_pfet_val_override = 0 (Override disabled)
+        //     vdd_pfet_sel_override = 0 (Override disabled)
+        //     vdd_pfet_enable_regulation_finger = 0
+        //         (Regulation finger controlled by FSM)
+        FAPI_DBG("Clear VDD PFET stage select and value override bits");
+        l_data.flush<0>().
+        setBit<VDD_PFET_VAL_OVERRIDE_BIT>().
+        setBit<VDD_PFET_SEL_OVERRIDE_BIT>().
+        setBit<VDD_PFET_REGULATION_FINGER_EN_BIT>();
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data),
+                 "putScom failed for address PPM_PFCS");
+
+        FAPI_DBG("Force VDD on");
+        l_data.flush<0>().insertFromRight
+        <VDD_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(PFET_FORCE_VON);
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_OR[l_type], l_data),
+                 "putScom failed for address PPM_PFCS_OR");
+
+        // Check for valid power on completion
+        //     Polled Timeout:  100us
+        FAPI_TRY(pollVddFSMIdle());
+
+        //    Write PFETCNTLSTAT_REG_WCLEAR
+        //      vdd_pfet_force_state = 00 (No Operation);
+        //      all fields set to 1 for WAND
+        //    Use PPM_PFCS_CLR,
+        //      vdd_pfet_force_state = 0b11
+        FAPI_DBG("vdd_pfet_force_state = 00, or Idle");
+        l_data.flush<0>().insertFromRight
+        <VDD_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(~PFET_NOP);
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data),
+                 "putScom failed for address PPM_PFCS_CLR");
+
+    fapi_try_exit:
+        return fapi2::current_err;
+
+    };
+
+    auto powerOnVcs = [&] ()
+    {
+        // Command the PFET controller to power-on
+        //    Write PFETCNTLSTAT_REG_OR with values defined below
+        //      vcs_pfet_force_state = 11 (Force Von)
+        //    Write to PFETCNTLSTAT_REG_CLR
+        //      vcs_pfet_val_override = 0 (Override disabled)
+        //      vcs_pfet_sel_override = 0 (Override disabled)
+        //      Note there is no vcs_pfet_enable_regulation_finger
+        FAPI_DBG("Clear VCS PFET stage select and value override bits");
+        l_data.flush<0>().
+        setBit<VCS_PFET_VAL_OVERRIDE_BIT>().
+        setBit<VCS_PFET_SEL_OVERRIDE_BIT>();
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data),
+                 "putScom failed for address PPM_PFCS_CLR");
+
+        FAPI_DBG("Force VCS on");
+        l_data.flush<0>().insertFromRight
+        <VCS_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(PFET_FORCE_VON);
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_OR[l_type], l_data),
+                 "putScom failed for address PPM_PFCS_OR");
+
+        // Check for valid power on completion
+        //     Polled Timeout:  100us
+        FAPI_TRY(pollVcsFSMIdle());
+
+        //   Write PFETCNTLSTAT_REG_WCLEAR
+        //      vcs_pfet_force_state = 00 (No Operation);
+        //      all fields set to 1 for WAND
+        //   Use PPM_PFCS_CLR,  vdd_pfet_force_state = ~(0b00)
+        FAPI_DBG("vcs_pfet_force_state = 00, or Idle");
+        l_data.flush<0>().insertFromRight
+        <VCS_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(~PFET_NOP);
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data),
+                 "putScom failed for address PPM_PFCS_CLR");
+
+    fapi_try_exit:
+        return fapi2::current_err;
+    };
+
+    auto powerOffVdd = [&] ()
+    {
+        // Command the PFET controller to power-off
+        //   Write PFETCNTLSTAT_REG:
+        //     vdd_pfet_force_state = 01 (Force Voff)
+        //     vdd_pfet_val_override = 0 (Override disabled)
+        //     vdd_pfet_sel_override = 0 (Override disabled)
+        //     vdd_pfet_enable_regulation_finger = 0
+        //                   (Regulation finger controlled by FSM)
+        FAPI_DBG("Clear VDD PFET stage select and value override bits");
+        l_data.flush<0>().
+        setBit<VDD_PFET_VAL_OVERRIDE_BIT>().
+        setBit<VDD_PFET_SEL_OVERRIDE_BIT>().
+        setBit<VDD_PFET_REGULATION_FINGER_EN_BIT>();
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data),
+                 "putScom failed for address PPM_PFCS");
+
+        FAPI_DBG("Force VDD off");
+        l_data.flush<0>().insertFromRight
+        <VDD_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(PFET_FORCE_VOFF);
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_OR[l_type], l_data),
+                 "putScom failed for address PPM_PFCS");
+
+        // Check for valid power off completion
+        //     Polled Timeout:  100us
+        FAPI_TRY(pollVddFSMIdle());
+
+        //    Write PFETCNTLSTAT_REG_WCLEAR
+        //      vdd_pfet_force_state = 00 (No Operation);
+        //      all fields set to 1 for WAND
+        //    Use PPM_PFCS_CLR,  vdd_pfet_force_state = 0b11
+        FAPI_DBG("vdd_pfet_force_state = 00, or Idle");
+        l_data.flush<0>().insertFromRight
+        <VDD_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(~PFET_NOP);
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data),
+                 "putScom failed for address PPM_PFCS_CLR");
+
+    fapi_try_exit:
+        return fapi2::current_err;
+    };
+
+    auto powerOffVcs = [&] ()
+    {
+        // Command the PFET controller to power-off
+        //    Write PFETCNTLSTAT_REG_OR with values defined below
+        //      vcs_pfet_force_state = 11 (Force Voff)
+        //    DOC BUG: ?? Write to PFETCNTLSTAT_REG_CLR
+        //      vcs_pfet_val_override = 0 (Override disabled)
+        //      vcs_pfet_sel_override = 0 (Override disabled)
+        //      Note there is no vcs_pfet_enable_regulation_finger
+        FAPI_DBG("Clear VCS PFET stage select and value override bits");
+        l_data.flush<0>().
+        setBit<VCS_PFET_VAL_OVERRIDE_BIT>().
+        setBit<VCS_PFET_SEL_OVERRIDE_BIT>();
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data),
+                 "putScom failed for address PPM_PFCS_CLR");
+
+        FAPI_DBG("Force VCS off");
+        l_data.flush<0>().
+        insertFromRight
+        <VCS_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(PFET_FORCE_VOFF);
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_OR[l_type], l_data),
+                 "putScom failed for address PPM_PFCS_OR");
+
+        // Check for valid power off completion
+        //     Polled Timeout:  100us
+        FAPI_TRY(pollVcsFSMIdle());
+
+        //   Write PFETCNTLSTAT_REG_WCLEAR
+        //      vcs_pfet_force_state = 00 (No Operation);
+        //          all fields set to 1 for WAND
+        //   Use PPM_PFCS_CLR,  vcs_pfet_force_state = ~(0b00)
+        FAPI_DBG("vcs_pfet_force_state = 00, or Idle");
+        l_data.flush<0>().insertFromRight
+        <VCS_PFET_FORCE_STATE_BIT, PFET_STATE_LENGTH>(~PFET_NOP);
+        FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data),
+                 "putScom failed for address PPM_PFCS_CLR");
+
+    fapi_try_exit:
+        return fapi2::current_err;
+    };
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Initialization code
+    ///////////////////////////////////////////////////////////////////////////
+#if 0  // unneeded for AWAN operation.  Also, fails if delay field is > 8
+    l_data.flush<0>().insertFromRight<POWDN_DLY_BIT, POWDN_DLY_LENGTH>(0x8).
+    insertFromRight<POWUP_DLY_BIT, POWUP_DLY_LENGTH>(0x8);
+
+    FAPI_TRY(fapi2::putScom(i_target, PPM_PFDLY, l_data),
+             "putScom failed for address PPM_PFDLY");
+#endif
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_DBG("Assert PCB fence via NET_CTRL0[25]");
+    FAPI_TRY(putScom(i_target, NET_CTRL0_WOR[l_type], MASK_SET(25)));
+
+    FAPI_DBG("Assert chiplet electrical fence via NET_CTRL0[26]");
+    FAPI_TRY(putScom(i_target, NET_CTRL0_WOR[l_type], MASK_SET(26)));
+
+    FAPI_DBG("Assert vital thold via NET_CTRL0[16]");
+    FAPI_TRY(putScom(i_target, NET_CTRL0_WOR[l_type], MASK_SET(16)));
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Procedure code
+    ///////////////////////////////////////////////////////////////////////////
+    switch(i_operation)
+    {
+        case p9power::POWER_ON:
+        case p9power::POWER_ON_VDD:
+            {
+                // 4.3.8.1 Power-on via Hardware FSM
+
+                // VDD first, VCS second
+
+                // 1)  Read  PFETCNTLSTAT_REG:  check for bits 0:3 being 0b0000
+                l_data.flush<0>().
+                setBit<VCS_PFET_VAL_OVERRIDE_BIT>().
+                setBit<VCS_PFET_SEL_OVERRIDE_BIT>();
+                FAPI_TRY(fapi2::putScom(i_target, PPM_PFCS_CLR[l_type], l_data),
+                         "putScom failed for address PPM_PFCS_CLR");
+
+                FAPI_DBG("Make sure that we are not forcing PFET for VCS or VDD off");
+                FAPI_TRY(fapi2::getScom(i_target, PPM_PFCS[l_type], l_data),
+                         "getScom failed for address PPM_PFCS");
+                l_data.extractToRight
+                <VDD_PFET_FORCE_STATE_BIT, 2 * PFET_STATE_LENGTH>
+                (l_temp);
+                FAPI_ASSERT((l_temp == 0),
+                            fapi2::PMPROC_PFETLIB_BAD_SCOM()
+                            .set_ADDRESS(PPM_PFCS[l_type]),
+                            "PFET_FORCE_STATE not 0");
+
+                // 2) Set bits to program HW to enable VDD PFET, and
+                // 3) Poll state bit until Pfet sequence is complete
+                FAPI_TRY(powerOnVdd());
+
+                // 4) Set bits to program HW to enable VCS PFET, and
+                // 5) Poll state bit until Pfet sequence is complete
+
+                // Note: if (i_target.getType() & fapi2::TARGET_TYPE_EQ) doesn't work.
+                //   Created a  POWER_*_VDD label to delineate Vcs and Vdd
+                if (i_operation == p9power::POWER_ON)
+                {
+                    FAPI_TRY(powerOnVcs());
+                }
+
+            }
+            break;
+
+        case p9power::POWER_OFF:
+        case p9power::POWER_OFF_VDD:
+            {
+                // 4.3.8.2 Power-off via Hardware FSM
+                // 1)  Read  PFETCNTLSTAT_REG:  check for bits 0:3 being 0b0000
+                FAPI_DBG("Make sure that we are not forcing PFET for VCS or VDD off");
+                FAPI_TRY(fapi2::getScom(i_target, PPM_PFCS[l_type], l_data),
+                         "getScom failed for address PPM_PFCS");
+
+                l_data.extractToRight
+                <VDD_PFET_FORCE_STATE_BIT, 2 * PFET_STATE_LENGTH>
+                (l_temp);
+                FAPI_ASSERT((l_temp == 0),
+                            fapi2::PMPROC_PFETLIB_BAD_SCOM()
+                            .set_ADDRESS(PPM_PFCS[l_type]),
+                            "PFET_FORCE_STATE not 0");
+
+                // 2) Set bits to program HW to turn off VCS PFET, and
+                // 3) Poll state bit until Pfet sequence is complete
+
+                // Note: if (i_target.getType() & fapi2::TARGET_TYPE_EQ) doesn't work.
+                //   Created a  POWER_*_VDD label to delineate Vcs and Vdd
+                if (i_operation == p9power::POWER_OFF)
+                {
+                    FAPI_TRY(powerOffVcs());
+                }
+
+                // 4) Set bits to program HW to turn off VDD PFET, and
+                // 5) Poll state bit until Pfet sequence is complete
+                FAPI_TRY(powerOffVdd());
+
+            }
+            break;
+    }
+
+    FAPI_INF("<<p9_common_poweronoff");
+fapi_try_exit:
+    return fapi2::current_err;
+} // Procedure
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H
new file mode 100644
index 00000000..9bb01bce
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H
@@ -0,0 +1,140 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_common_poweronoff.H
+/// @brief common procedure for power on/off
+///
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE:CME
+// *HWP Level              : 2
+
+#ifndef __P9_COMMON_POWERONOFF_H__
+#define __P9_COMMON_POWERONOFF_H__
+
+#include <fapi2.H>
+
+namespace p9power
+{
+enum powerOperation_t
+{
+    POWER_ON      = 0x0,
+    POWER_OFF     = 0xFF,
+    POWER_ON_VDD  = 0x1,
+    POWER_OFF_VDD = 0xFE
+};
+
+
+
+// For SBE, the initial power-on times are not overly time critical so they are
+// hardcoded for the delay necessary when running with the fastest nest (2.4GHz).
+// When these same values are used with slower nest frequencies, the delays will
+// get longer (more conservative).
+//
+// For istep 15, the delay settings are computed based on the setting of
+// ATTR_FREQ_PB
+//
+// pfet_delay = (1/nest_frequency_mhz)*1000*4 (PPM clock period in ns) *
+//               2^(15-pfet_delay_value).
+//
+// or
+//
+//                                                pfet_delay
+// 2^(15-pfet_delay_value) =           ------------------------------
+//                                     (1/nest_frequency_mhz)*1000*4
+//
+//                                     pfet_delay * nest_frequency_mhz
+// 2^(15-pfet_delay_value  =           ------------------------------
+//                                                1000*4
+//
+//                                    ( pfet_delay * nest_frequency_mhz)
+// 15-pfet_delay_value     =      log2(  ------------------------------)
+//                                    (             1000*4             )
+//
+//                                    ( pfet_delay * nest_frequency_mhz)
+// pfet_delay_value        = 15 - log2(  ------------------------------)
+//                                    (             1000*4             )
+//
+//            ( pfet_delay * nest_frequency_mhz)
+// logexp   = (  ------------------------------)
+//            (             1000*4             )
+//
+//          = pfet_delay * nest_frequency_mhz / (1000 * 4)
+//          = pfet_delay * (nest_frequency_mhz / (1000 * 4))
+//          = pfet_delay * (2400 / (1000 * 4))
+//          = pfet_delay * (.6)
+//
+// For core delay of 250ns per step, logexp = 250 * .6 = 150
+//   --> log2(150) = 8 (rounded up to next integer)
+//  -- > pfet_delay_value = 15 - 8 = 7
+//
+// For EQ delay of 500ns per step, logexp = 500 * .6 = 300
+//   --> log2(150) = 9 (rounded up to next integer)
+//  -- > pfet_delay_value = 15 - 9 = 6
+
+
+enum pfetDelays
+{
+    PFET_DELAY_POWERDOWN_EQ     = 0x1,
+    PFET_DELAY_POWERDOWN_CORE   = 0x1,
+#ifndef PRODUCT_DEFAULT_PFET_DELAYS
+    PFET_DELAY_POWERUP_EQ       = 0x1,
+    PFET_DELAY_POWERUP_CORE     = 0x1
+#else
+    PFET_DELAY_POWERUP_EQ       = 0x6,
+    PFET_DELAY_POWERUP_CORE     = 0x7
+#endif
+};
+
+
+} // namespace
+
+/// @typedef p9_common_poweronoff_FP_t
+/// function pointer typedef definition for HWP call support
+/// @todo: consider template solution here
+typedef fapi2::ReturnCode (*p9_common_poweronoff_FP_t) (
+    const fapi2::Target < fapi2::TARGET_TYPE_EQ |
+    fapi2::TARGET_TYPE_CORE > &,
+    const p9power::powerOperation_t i_operation);
+
+/// @brief common procedure for power on/off
+///
+/// @param [in] i_target    TARGET_TYPE_EQ|TARGET_TYPE_CORE target
+/// @param [in] i_operation ENUM(ON,OFF)
+///
+/// @attr
+/// @attritem ATTR_PFET_TIMING - EX target, uint32
+///
+/// @retval FAPI_RC_SUCCESS
+template <fapi2::TargetType K>
+fapi2::ReturnCode
+p9_common_poweronoff(
+    const fapi2::Target<K>& i_target,
+    const p9power::powerOperation_t i_operation);
+
+#endif  // __P9_COMMON_POWERONOFF_H__
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.C b/src/import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.C
new file mode 100644
index 00000000..05cd69e7
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.C
@@ -0,0 +1,69 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.C $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_common_pro_epi_log.C
+/// @brief common procedure prologue/epilogue routines
+///
+/// *HWP HWP Owner          : David Du      <daviddu@us.ibm.com>
+/// *HWP Backup HWP Owner   : Greg Still    <stillgs@us.ibm.com>
+/// *HWP FW Owner           : Reshmi Nair   <resnair5@in.ibm.com>
+/// *HWP Team               : PM
+/// *HWP Consumed by        : SBE:SGPE
+/// *HWP Level              : 1
+///
+/// Procedure Summary:
+///
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi2.H>
+#include "p9_common_pro_epi_log.H"
+
+//------------------------------------------------------------------------------
+// Constant Definitions:
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Procedure:
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+    fapi2::ReturnCode
+    p9_common_pro_epi_log(
+        const fapi2::Target < fapi2::TARGET_TYPE_EQ |
+        fapi2::TARGET_TYPE_CORE > & i_target,
+        int i_operation)
+    {
+        return fapi2::FAPI2_RC_SUCCESS;
+
+    } // Procedure
+
+
+} // extern C
+
+
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.H b/src/import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.H
new file mode 100644
index 00000000..f119bfaf
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.H
@@ -0,0 +1,69 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/lib/p9_common_pro_epi_log.H $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_common_pro_epi_log.H
+/// @brief common procedure prologue/epilogue routines
+///
+/// *HWP HWP Owner          : David Du      <daviddu@us.ibm.com>
+/// *HWP Backup HWP Owner   : Greg Still    <stillgs@us.ibm.com>
+/// *HWP FW Owner           : Reshmi Nair   <resnair5@in.ibm.com>
+/// *HWP Team               : PM
+/// *HWP Consumed by        : SBE:SGPE
+/// *HWP Level              : 1
+///
+
+#ifndef __P9_COMMON_PRO_EPI_LOG_H__
+#define __P9_COMMON_PRO_EPI_LOG_H__
+
+extern "C"
+{
+
+/// @typedef p9_common_pro_epi_log_FP_t
+/// function pointer typedef definition for HWP call support
+    typedef fapi2::ReturnCode (*p9_common_pro_epi_log_FP_t) (
+        const fapi2::Target < fapi2::TARGET_TYPE_EQ |
+        fapi2::TARGET_TYPE_CORE > &,
+        int);
+
+
+/// @brief common procedure prologue/epilogue routines
+///
+/// @param [in] i_target    TARGET_TYPE_EQ|TARGET_TYPE_CORE target
+/// @param [in] i_operation ENUM(PROLOG, EPILOG)
+///
+/// @attr
+/// @attritem ATTR_EX_PARIAL_GOOD - EX target, uint32
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_common_pro_epi_log(
+        const fapi2::Target < fapi2::TARGET_TYPE_EQ |
+        fapi2::TARGET_TYPE_CORE > & i_target,
+        int i_operation);
+
+
+} // extern C
+
+#endif  // __P9_COMMON_PRO_EPI_LOG_H__
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H
new file mode 100644
index 00000000..d09b7014
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H
@@ -0,0 +1,257 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/lib/p9_hcd_common.H $          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_hcd_common.H
+/// @brief common hcode includes
+
+// *HWP HWP Owner          : David Du       <daviddu@us.ibm.com>
+// *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:SGPE:CME
+// *HWP Level              : 2
+
+#ifndef __P9_HCD_COMMON_H__
+#define __P9_HCD_COMMON_H__
+
+//-------------------------
+// Macros
+//-------------------------
+
+// Create a multi-bit mask of \a n bits starting at bit \a b
+#define BITS64(b, n) ((0xffffffffffffffffull << (64 - (n))) >> (b))
+#define BITS32(b, n) ((0xffffffff            << (32 - (n))) >> (b))
+#define BITS16(b, n) ((0xffff                << (16 - (n))) >> (b))
+#define BITS8(b, n)  ((0xff                  << (8  - (n))) >> (b))
+
+// Create a single bit mask at bit \a b
+#define BIT64(b) BITS64((b), 1)
+#define BIT32(b) BITS32((b), 1)
+#define BIT16(b) BITS16((b), 1)
+#define BIT8(b)  BITS8((b), 1)
+
+// Create a amount of shift to bit location \a b
+#define SHIFT64(b) (63-b)
+#define SHIFT32(b) (31-b)
+#define SHIFT16(b) (15-b)
+#define SHIFT8(b)  (7-b)
+
+
+// The BUF_* macros apply operations to a newly constructed buffer
+#define BUF_SET(bit)   fapi2::buffer<uint64_t>().setBit<bit>()
+#define BUF_UNSET(bit) fapi2::buffer<uint64_t>().flush<1>().clearBit<bit>()
+#define BUF_INSERT(start,size,val) \
+    fapi2::buffer<uint64_t>().insertFromRight<start,size>(val)
+#define BUF_REPLACE(start,size,val) \
+    fapi2::buffer<uint64_t>().flush<1>().insertFromRight<start,size>(val)
+// The following DATA_* and MASK_* macros assume you have
+// "fapi2::buffer<uint64_t> l_data64" declared
+
+// The DATA_* macros apply operations to a buffer contains existing data
+#define DATA_BIT(buf,op,bit)             buf.op##Bit<bit>()
+#define DATA_SET(bit)                    DATA_BIT(l_data64,set,bit)
+#define DATA_UNSET(bit)                  DATA_BIT(l_data64,clear,bit)
+#define DATA_FIELD(buf,start,size,val)   buf.insertFromRight<start,size>(val)
+#define DATA_INSERT(start,size,val)      DATA_FIELD(l_data64,start,size,val)
+
+// The MASK_* macros apply operations to a buffer to create a new data mask
+// data previously stored in the buffer will be overwritten.
+#define MASK_FLUSH(buf,mask)             buf.flush<mask>()
+#define MASK_ZERO                        MASK_FLUSH(l_data64,0)
+#define MASK_ALL                         MASK_FLUSH(l_data64,1)
+#define MASK_BIT(buf,mask,op,bit)        buf.flush<mask>().op##Bit<bit>()
+#define MASK_SET(bit)                    MASK_BIT(l_data64,0,set,bit)
+#define MASK_UNSET(bit)                  MASK_BIT(l_data64,1,clear,bit)
+#define MASK_FIELD(buf,mask,start,size,val) \
+    buf.flush<mask>().insertFromRight<start,size>(val)
+#define MASK_OR(start,size,val)          MASK_FIELD(l_data64,0,start,size,val)
+#define MASK_AND(start,size,val)         MASK_FIELD(l_data64,1,start,size,val)
+#define MASK_CLR(start,size,val)         MASK_FIELD(l_data64,0,start,size,val)
+
+//-------------------------
+// Constants
+//-------------------------
+
+namespace p9hcd
+{
+
+// Bit masks used by CME hcode
+enum P9_HCD_CME_CORE_MASKS
+{
+    LEFT_CORE  = 0x2,
+    RIGHT_CORE = 0x1,
+    BOTH_CORES = 0x3,
+    NO_CORE    = 0x0
+};
+
+// Control parameters for PCB Aribter
+enum P9_HCD_PCB_ARBITER_CTRL
+{
+    REQUEST_ARBITER = 1,
+    RELEASE_ARBITER = 0
+};
+
+// Constants to calculate hcd poll timeout intervals
+enum P9_HCD_TIMEOUT_CONSTANTS
+{
+    CYCLES_PER_MS       = 500000, // PPE FREQ 500MHZ
+    INSTS_PER_POLL_LOOP = 8       //
+};
+
+// Constants to calculate the delay in nanoseconds or simcycles
+// Source | Domain | Freq    | cyc/ns | Period |
+// DPLL   | Core   | 4GHz    | 4      | 250ps  |
+//        | Cache  | 2GHz    | 2      | 500ps  |
+//        | PPE    | 500MHz  | 0.5    | 2ns    |
+// Refclk | Refclk | 100Mhz  | 0.1    | 10ns   |
+enum P9_HCD_DELAY_CONSTANTS
+{
+    SIM_CYCLE_1U1D        = 2,   // fastest internal oscillator
+    SIM_CYCLE_4U4D        = 8,   // 4Ghz   ideal dpll
+    SIM_CYCLE_150UD       = 300, // 133Mhz refclk
+    SIM_CYCLE_200UD       = 400, // 100Mhz refclk external oscillator
+    CLK_PERIOD_250PS      = 250, // 4GHZ dpll
+    CLK_PERIOD_10NS       = 10,  // 100Mhz refclk
+    CLK_PERIOD_CORE2CACHE = 2,
+    CLK_PERIOD_CORE2PPE   = 8,
+    CLK_PERIOD_CORE2REF   = 40
+};
+
+// Chip Position Constants
+enum P9_HCD_CHIP_POS_CONSTANTS
+{
+    PERV_TO_EQ_POS_OFFSET   = 0x10,
+    PERV_TO_CORE_POS_OFFSET = 0x20
+};
+
+// EX Constants
+enum P9_HCD_EX_CTRL_CONSTANTS
+{
+    ODD_EX                  = 1,
+    EVEN_EX                 = 2,
+    BOTH_EX                 = 3,
+    QCSR_MASK_EX0           = (BIT64(0) | BIT64(2) | BIT64(4) |
+                               BIT64(6) | BIT64(8) | BIT64(10)),
+    QCSR_MASK_EX1           = (BIT64(1) | BIT64(3) | BIT64(5) |
+                               BIT64(7) | BIT64(9) | BIT64(11))
+};
+
+// Multicast Constants
+enum P9_HCD_MULTICAST_CONSTANTS
+{
+    MULTICAST_GROUP_4       = 4, // QUAD
+    MULTICAST_GROUP_5       = 5, // EX0
+    MULTICAST_GROUP_6       = 6  // EX1
+};
+
+// Clock Control Constants
+enum P9_HCD_CLK_CTRL_CONSTANTS
+{
+    CLK_STOP_CMD                             = BIT64(0),
+    CLK_START_CMD                            = BIT64(1),
+    CLK_REGION_ANEP                          = BIT64(10),
+    CLK_REGION_DPLL                          = BIT64(14),
+    CLK_REGION_REFR                          = BITS64(12, 2),
+    CLK_REGION_L3_REFR                       = BITS64(6, 2) | BITS64(12, 2),
+    CLK_REGION_EX0_L3                        = BIT64(6),
+    CLK_REGION_EX1_L3                        = BIT64(7),
+    CLK_REGION_EX0_L2                        = BIT64(8),
+    CLK_REGION_EX1_L2                        = BIT64(9),
+    CLK_REGION_EX0_REFR                      = BIT64(12),
+    CLK_REGION_EX1_REFR                      = BIT64(13),
+    CLK_REGION_EX0_L2_L3_REFR                = BIT64(6) | BIT64(8) | BIT64(12),
+    CLK_REGION_EX1_L2_L3_REFR                = BIT64(7) | BIT64(9) | BIT64(13),
+    CLK_REGION_ALL_BUT_L3_REFR               = BITS64(4, 2) | BITS64(8, 4) | BIT64(14),
+    CLK_REGION_ALL_BUT_L3_REFR_DPLL          = BITS64(4, 2) | BITS64(8, 4),
+    CLK_REGION_ALL_BUT_EX                    = BITS64(4, 2) | BITS64(10, 2) | BIT64(14),
+    CLK_REGION_ALL_BUT_EX_DPLL               = BITS64(4, 2) | BITS64(10, 2),
+    CLK_REGION_ALL_BUT_EX_ANEP_DPLL          = BITS64(4, 2) | BIT64(11),
+    CLK_REGION_ALL_BUT_PLL                   = BITS64(4, 10),
+    CLK_REGION_ALL_BUT_PLL_REFR              = BITS64(4, 8),
+    CLK_REGION_ALL                           = BITS64(4, 11),
+    CLK_THOLD_ALL                            = BITS64(48, 3)
+};
+
+// Scan Flush Constants
+enum P9_HCD_SCAN0_CONSTANTS
+{
+    SCAN0_REGION_ALL                         = 0x7FF,
+    SCAN0_REGION_ALL_BUT_PLL                 = 0x7FE,
+    SCAN0_REGION_ALL_BUT_EX                  = 0x619,
+    SCAN0_REGION_ALL_BUT_EX_DPLL             = 0x618,
+    SCAN0_REGION_ALL_BUT_EX_ANEP_DPLL        = 0x608,
+    SCAN0_REGION_EX0_L2_L3_REFR              = 0x144,
+    SCAN0_REGION_EX1_L2_L3_REFR              = 0x0A2,
+    SCAN0_TYPE_GPTR_REPR_TIME                = 0x230,
+    SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME        = 0xDCF
+};
+
+//OCC FLag defines
+enum PM_GPE_OCCFLG_DEFS
+{
+    SGPE_ACTIVE    = 8
+};
+
+// XSR defines
+enum XSR_DEFS
+{
+    HALTED_STATE    = 0
+};
+
+// XCR defines
+enum XCR_DEFS
+{
+    CLEAR_DEBUG_STATUS = 0,
+    HALT               = 1,
+    RESUME             = 2,
+    SINGLE_STEP        = 3,
+    TOGGLE_XSR_TRH     = 4,
+    SOFT_RESET         = 5,
+    HARD_RESET         = 6,
+    FORCE_HALT         = 7
+};
+
+
+} // END OF NAMESPACE p9hcd
+
+
+#define P9_HCD_SCAN_FUNC_REPEAT 1
+#define P9_HCD_SCAN_GPTR_REPEAT 1
+
+/// @todo remove these once correct header contains them
+/// Scom addresses missing from p9_quad_scom_addresses.H
+#define PU_OCB_OCI_QSSR_CLEAR            PU_OCB_OCI_QSSR_SCOM1
+#define PU_OCB_OCI_QSSR_OR               PU_OCB_OCI_QSSR_SCOM2
+#define EQ_QPPM_QCCR_WCLEAR              EQ_QPPM_QCCR_SCOM1
+#define EQ_QPPM_QCCR_WOR                 EQ_QPPM_QCCR_SCOM2
+#define EX_0_CME_SCOM_SICR_CLEAR         EX_0_CME_SCOM_SICR_SCOM1
+#define EX_1_CME_SCOM_SICR_CLEAR         EX_1_CME_SCOM_SICR_SCOM1
+#define EX_0_CME_SCOM_SICR_OR            EX_0_CME_SCOM_SICR_SCOM2
+#define EX_1_CME_SCOM_SICR_OR            EX_1_CME_SCOM_SICR_SCOM2
+#define CME_LCL_SICR_OR                  0xc0000510
+#define CME_LCL_SICR_CLR                 0xc0000518
+#define CME_LCL_SISR                     0xc0000520
+
+#endif  // __P9_HCD_COMMON_H__
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pm_stop_history.H b/src/import/chips/p9/procedures/hwp/lib/p9_pm_stop_history.H
new file mode 100644
index 00000000..38e94226
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_pm_stop_history.H
@@ -0,0 +1,76 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/lib/p9_pm_stop_history.H $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_hcd_common.H
+/// @brief common hcode includes
+///
+
+// *HWP HWP Owner          : Greg Still     <stillgs@us.ibm.com>
+// *HWP HWP BackupeOwner   : David Du       <daviddu@us.ibm.com>
+// *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
+// *HWP Team               : PM
+// *HWP Consumed by        : SBE:HS:CRO
+
+#ifndef __P9_SSH_H__
+#define __P9_SSH_H__
+
+
+namespace p9ssh
+{
+
+// Note: these are not autogenerated as multiple registers have the
+// same bit layout
+static const uint32_t STOP_GATED_START           = 0;
+static const uint32_t STOP_GATED_LEN             = 1;
+
+static const uint32_t STOP_TRANSITION_START      = 2;
+static const uint32_t STOP_TRANSITION_LEN        = 2;
+
+static const uint32_t STOP_REQUESTED_LEVEL_START = 4;
+static const uint32_t STOP_REQUESTED_LEVEL_LEN   = 4;
+
+static const uint32_t STOP_ACTUAL_LEVEL_START    = 8;
+static const uint32_t STOP_ACTUAL_LEVEL_LEN      = 4;
+
+static const uint32_t STOP_REQ_WRITE_EN          = 12;
+static const uint32_t STOP_ACT_WRITE_EN          = 13;
+
+enum STOP_HISTORY_GATED
+{
+    SSH_RUNNING = 0,
+    SSH_GATED = 1
+};
+
+enum STOP_HISTORY_TRANSITION
+{
+    SSH_COMPLETE = 0,
+    SSH_CORE_COMPLETE = 1,
+    SSH_ENTERING = 2,
+    SSH_EXITING = 3,
+    SSH_UNDEFINED = 255
+};
+
+} // namespace
+#endif  // __P9_SSH_H__
diff --git a/src/import/chips/p9/procedures/hwp/nest/Makefile b/src/import/chips/p9/procedures/hwp/nest/Makefile
new file mode 100644
index 00000000..8c4adc0b
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/Makefile
@@ -0,0 +1,58 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/hwp/nest/Makefile $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+# This Makefile compiles all of the nest hardware procedure code. See the
+# "nestfiles.mk" file in this directory.
+
+#all generated files from this makefile will end up in obj/nest
+export SUB_OBJDIR = /nest
+
+include img_defs.mk
+include nestfiles.mk
+
+# TODO via RTC 152424
+# Adding VPATH as there are few procedures which are in
+# perv folder but we are compiling them here. Refer to
+# nestfiles.mk for details.
+export VPATH = $(PERV_SRCDIR):$(NEST_SRCDIR)
+OBJS := $(addprefix $(OBJDIR)/, $(NEST_OBJECTS))
+
+libnest.a: nest
+	$(AR) crs $(OBJDIR)/libnest.a $(OBJDIR)/*.o
+
+.PHONY: clean nest
+nest: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+clean:
+	rm -fr $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d)
+endif
diff --git a/src/import/chips/p9/procedures/hwp/nest/nestfiles.mk b/src/import/chips/p9/procedures/hwp/nest/nestfiles.mk
new file mode 100644
index 00000000..b3ddbdff
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/nestfiles.mk
@@ -0,0 +1,59 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/hwp/nest/nestfiles.mk $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file nestfiles.mk
+#
+#  @brief mk for including nest object files
+#
+##########################################################################
+# Object Files
+##########################################################################
+
+NEST-CPP-SOURCES = p9_sbe_mcs_setup.C
+NEST-CPP-SOURCES +=p9_sbe_scominit.C
+NEST-CPP-SOURCES +=p9_sbe_fabricinit.C
+NEST-CPP-SOURCES +=p9_fbc_utils.C
+NEST-CPP-SOURCES +=p9_sbe_load_bootloader.C
+NEST-CPP-SOURCES +=p9_pba_access.C
+NEST-CPP-SOURCES +=p9_pba_coherent_utils.C
+NEST-CPP-SOURCES +=p9_pba_setup.C
+NEST-CPP-SOURCES +=p9_adu_access.C
+NEST-CPP-SOURCES +=p9_adu_setup.C
+NEST-CPP-SOURCES +=p9_adu_coherent_utils.C
+# TODO via RTC 152424
+# p9_ram_core.C will go to runtime makefile. Currently this procedure is in
+# perv directory. As we are putting perv procedures currently in SEEPROM.
+# So compiling p9_ram_core.C in nest makefile.
+NEST-CPP-SOURCES +=p9_ram_core.C
+# TODO via RTC 152424
+# swicth gear proecdures are in perv directory. But these procedures needs to
+# be executed from PIBMEM. So compiling these is nest makefile.
+NEST-CPP-SOURCES +=p9_sbe_gear_switcher.C
+NEST-CPP-SOURCES +=p9_sbe_tp_switch_gears.C
+NEST-C-SOURCES =
+NEST-S-SOURCES =
+
+NEST_OBJECTS += $(NEST-CPP-SOURCES:.C=.o)
+NEST_OBJECTS += $(NEST-C-SOURCES:.c=.o)
+NEST_OBJECTS += $(NEST-S-SOURCES:.S=.o)
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.C b/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.C
new file mode 100644
index 00000000..360c5837
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.C
@@ -0,0 +1,130 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_adu_access.C $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//--------------------------------------------------------------------------
+//
+//
+/// @file p9_adu_access.C
+/// @brief Read coherent state of memory via the ADU (FAPI)
+///
+// *HWP HWP Owner Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+//
+//--------------------------------------------------------------------------
+
+
+//--------------------------------------------------------------------------
+// Includes
+//--------------------------------------------------------------------------
+#include <p9_adu_access.H>
+#include <p9_adu_coherent_utils.H>
+
+extern "C" {
+
+//--------------------------------------------------------------------------
+//  HWP entry point
+//--------------------------------------------------------------------------
+    fapi2::ReturnCode p9_adu_access(const
+                                    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+                                    const uint64_t i_address,
+                                    const bool i_rnw,
+                                    const uint32_t i_flags,
+                                    const bool i_firstGranule,
+                                    const bool i_lastGranule,
+                                    uint8_t io_data[])
+    {
+
+        bool l_busyBitStatus = false;
+        adu_status_busy_handler l_busyHandling;
+
+        // mark HWP entry
+        FAPI_DBG("Entering ...\n");
+
+        // Process input flag
+        p9_ADU_oper_flag l_myAduFlag;
+        l_myAduFlag.getFlag(i_flags);
+
+        if( i_lastGranule && l_myAduFlag.getAutoIncrement() )
+        {
+            //call this function to clear the altd_auto_inc bit before the last iteration
+            FAPI_TRY(p9_adu_coherent_clear_autoinc(i_target), "Error from p9_adu_coherent_clear_autoinc");
+        }
+
+        if (i_rnw)
+        {
+            //read the data
+            FAPI_TRY(p9_adu_coherent_adu_read(i_target, i_firstGranule, i_address, l_myAduFlag, io_data),
+                     "Error from p9_adu_coherent_adu_read");
+        }
+        else
+        {
+            //write the data
+            FAPI_TRY(p9_adu_coherent_adu_write(i_target, i_firstGranule, i_address, l_myAduFlag, io_data),
+                     "Error from p9_adu_coherent_adu_write");
+        }
+
+        //If we are not in fastmode or this is the last granule, we want to check the status
+        if ( (i_lastGranule) || (l_myAduFlag.getFastMode() == false) )
+        {
+            if ( (l_myAduFlag.getAutoIncrement()) && !i_lastGranule )
+            {
+                // Only expect ADU busy if in AUTOINC AND it's not the last granule
+                l_busyHandling = EXPECTED_BUSY_BIT_SET;
+            }
+            else
+            {
+                l_busyHandling = EXPECTED_BUSY_BIT_CLEAR;
+            }
+
+            FAPI_TRY(p9_adu_coherent_status_check(i_target, l_busyHandling, false,
+                                                  l_busyBitStatus),
+                     "Error from p9_adu_coherent_status_check");
+
+            //If it's the last read/write
+            if (i_lastGranule)
+            {
+                FAPI_TRY(p9_adu_coherent_cleanup_adu(i_target),
+                         "Error doing p9_adu_coherent_cleanup_adu");
+            }
+        }
+
+    fapi_try_exit:
+        fapi2::ReturnCode saveError = fapi2::current_err;
+
+        if ( fapi2::current_err && l_myAduFlag.getOperFailCleanup() )
+        {
+            (void) p9_adu_coherent_utils_reset_adu(i_target);
+            uint32_t num_attempts = l_myAduFlag.getNumLockAttempts();
+            (void) p9_adu_coherent_manage_lock(i_target, false, false, num_attempts);
+        }
+
+        FAPI_DBG("Exiting...");
+        return saveError;
+    }
+
+} // extern "C"
+
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.H
new file mode 100644
index 00000000..0b8e1a15
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_access.H
@@ -0,0 +1,105 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_adu_access.H $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------------
+//
+/// @file p9_adu_access.H
+/// @brief Read coherent state of memory via the ADU (FAPI)
+///
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 1
+// *HWP Consumed by:
+// ----------------------------------------------------------------------------------
+//
+// *! ADDITIONAL COMMENTS :
+// *!
+// *! The purpose of this procedure is to perform a coherent read from system
+// *! memory via fabric commands issued from the ADU.
+// *!
+// *! Succcessful operation assumes that:
+// *!   o System clocks are running
+// *!   o Fabric is initalized
+// *!
+// *!
+//-----------------------------------------------------------------------------------
+
+#ifndef _P9_ADU_ACCESS_H_
+#define _P9_ADU_ACCESS_H_
+
+//-----------------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------------
+
+#include <fapi2.H>
+#include <p9_adu_constants.H>
+#include <p9_pba_constants.H>
+
+//-----------------------------------------------------------------------------------
+// Structure definitions
+//-----------------------------------------------------------------------------------
+
+//function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode
+(*p9_adu_access_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
+                       const uint64_t,
+                       const bool,
+                       const uint32_t,
+                       const bool,
+                       const bool,
+                       uint8_t[] );
+
+//-----------------------------------------------------------------------------------
+// Constant definitions
+//-----------------------------------------------------------------------------------
+
+extern "C" {
+
+//-----------------------------------------------------------------------------------
+// Function prototype
+//-----------------------------------------------------------------------------------
+
+/// @brief do the actual read/write from the ADU
+/// @param[in] i_target       => P9 chip target
+/// @param[in] i_address      => base real address for read/write operation (expected to be 8B aligned)
+/// @param[in] i_rnw          => if the operation is a read not write (1 for read, 0 for write)
+/// @param[in] i_flags        => other information that is needed - see the p9_adu_constants adu_flags enums for bit definitions
+//                               Note: To construct the flag you can use p9_ADU_oper_flag class
+/// @param[in] i_lastGranule  => if this is the last 8B of data that we are collecting (true = last granule, false = not last granule)
+/// @param[in] i_firstGranule => if this is the first 8B of data that we are collecting (true = first granule, false = not first granule)
+/// @param[in, out] io_data   => The data is read/written
+/// @return FAPI_RC_SUCCESS if the read/write completes successfully
+    fapi2::ReturnCode p9_adu_access(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_address,
+        const bool i_rnw,
+        const uint32_t i_flags,
+        const bool i_firstGranule,
+        const bool i_lastGranule,
+        uint8_t io_data[]);
+} //extern "C"
+
+#endif //_P9_ADU_ACCESS_H_
+
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C
new file mode 100644
index 00000000..7782cae2
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C
@@ -0,0 +1,986 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------------
+//
+/// @file p9_adu_coherent_utils.C
+/// @brief ADU alter/display library functions (FAPI)
+///
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+//
+//-----------------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------------
+#include <p9_adu_coherent_utils.H>
+#include <p9_misc_scom_addresses.H>
+#include <p9_fbc_utils.H>
+
+extern "C"
+{
+    //---------------------------------------------------------------------------------
+    // Constant definitions
+    //---------------------------------------------------------------------------------
+
+    //ADU Delay Constants
+
+    //ADU register field/bit definitions
+
+    // ADU Option Register field/bit definitions
+    const uint32_t FBC_ALTD_WITH_PRE_QUIESCE = 23;
+    const uint32_t FBC_ALTD_PRE_QUIESCE_COUNT_START_BIT = 28;  // Bits 28:47
+    const uint32_t FBC_ALTD_PRE_QUIESCE_COUNT_NUM_OF_BITS = 20;
+
+    const uint32_t FBC_ALTD_WITH_POST_INIT = 51;
+    const uint32_t FBC_ALTD_POST_INIT_COUNT_START_BIT = 54;    // Bits 54:63
+    const uint32_t FBC_ALTD_POST_INIT_COUNT_NUM_OF_BITS = 10;
+
+    // ADU Command Register field/bit definitions
+    const uint32_t ALTD_CMD_START_OP_BIT = 2;
+    const uint32_t ALTD_CMD_CLEAR_STATUS_BIT = 3;
+    const uint32_t ALTD_CMD_RESET_FSM_BIT = 4;
+    const uint32_t ALTD_CMD_RNW_BIT = 5;
+    const uint32_t ALTD_CMD_ADDRESS_ONLY_BIT = 6;
+    const uint32_t ALTD_CMD_LOCK_PICK_BIT = 10;
+    const uint32_t ALTD_CMD_LOCK_BIT = 11;
+    const uint32_t ALTD_CMD_LOCK_ID_START_BIT = 12;
+    const uint32_t ALTD_CMD_LOCK_ID_END_BIT = 15;
+    const uint32_t ALTD_CMD_SCOPE_START_BIT = 16;
+    const uint32_t ALTD_CMD_SCOPE_END_BIT = 18;
+    const uint32_t ALTD_CMD_AUTO_INC_BIT = 19;
+    const uint32_t ALTD_CMD_DROP_PRIORITY_BIT = 20;
+    const uint32_t ALTD_CMD_DROP_PRIORITY_MAX_BIT = 21;
+    const uint32_t ALTD_CMD_OVERWRITE_PBINIT_BIT = 22;
+    const uint32_t ALTD_CMD_PIB_DIRECT_BIT = 23;
+    const uint32_t ALTD_CMD_WITH_TM_QUIESCE_BIT = 24;
+    const uint32_t ALTD_CMD_TTYPE_START_BIT = 25;
+    const uint32_t ALTD_CMD_TTYPE_END_BIT = 31;
+    const uint32_t ALTD_CMD_TSIZE_START_BIT = 32;
+    const uint32_t ALTD_CMD_TSIZE_END_BIT = 39;
+
+    const uint32_t ALTD_CMD_SCOPE_NUM_BITS = (ALTD_CMD_SCOPE_END_BIT -
+            ALTD_CMD_SCOPE_START_BIT) + 1;
+    const uint32_t ALTD_CMD_TTYPE_NUM_BITS = (ALTD_CMD_TTYPE_END_BIT -
+            ALTD_CMD_TTYPE_START_BIT) + 1;
+    const uint32_t ALTD_CMD_TSIZE_NUM_BITS = (ALTD_CMD_TSIZE_END_BIT -
+            ALTD_CMD_TSIZE_START_BIT) + 1;
+
+    const uint32_t ALTD_CMD_TTYPE_CL_DMA_RD   = 6;  //0b0000110
+    const uint32_t ALTD_CMD_TTYPE_DMA_PR_WR   = 38; //0b0100110
+    const uint32_t ALTD_CMD_TTYPE_CI_PR_RD    = 52; //0b0110100
+    const uint32_t ALTD_CMD_TTYPE_CI_PR_WR    = 55; //0b0110111
+    const uint32_t ALTD_CMD_TTYPE_PB_OPER     = 0b0111111;
+    const uint32_t ALTD_CMD_TTYPE_PMISC_OPER  = 0b0110001;
+
+    //these should be 1, 2, 3, 4 but they are shifted over one to the left because for
+    //ci_pr_rd and ci_pr_w the secondary encode is 0ttt ssss0
+    const uint32_t ALTD_CMD_CI_TSIZE_1 = 2;
+    const uint32_t ALTD_CMD_CI_TSIZE_2 = 4;
+    const uint32_t ALTD_CMD_CI_TSIZE_4 = 6;
+    const uint32_t ALTD_CMD_CI_TSIZE_8 = 8;
+    //these should be 1, 2, 4, 8 but they are shifted over one to the left because for
+    //dma_pr_w the secondary encode is tSize & '0'
+    const uint32_t ALTD_CMD_DMAW_TSIZE_1 = 2;
+    const uint32_t ALTD_CMD_DMAW_TSIZE_2 = 4;
+    const uint32_t ALTD_CMD_DMAW_TSIZE_4 = 8;
+    const uint32_t ALTD_CMD_DMAW_TSIZE_8 = 16;
+    //I think that the secondary encoding should always be 0 for cl_dma_rd
+    const uint32_t ALTD_CMD_DMAR_TSIZE = 0;
+
+    // Values for PB operations
+    const uint32_t ALTD_CMD_PB_OPERATION_TSIZE  = 0b00001000;
+    const uint32_t ALTD_CMD_SCOPE_SYSTEM        = 0b00000101;
+
+    // Values for PMISC operations
+    const uint32_t ALTD_CMD_PMISC_TSIZE_1  = 0b00000010;    // PMISC SWITCH
+    const uint32_t ALTD_CMD_PMISC_TSIZE_2  = 0b01000000;    // PMISC HTM
+
+    // OPTION reg values for SWITCH operation
+    const uint32_t QUIESCE_SWITCH_WAIT_COUNT = 128;
+    const uint32_t INIT_SWITCH_WAIT_COUNT = 128;
+
+    // ADU Status Register field/bit definitions
+    const uint32_t ALTD_STATUS_BUSY_BIT = 0;
+    const uint32_t ALTD_STATUS_WAIT_CMD_ARBIT = 1;
+    const uint32_t ALTD_STATUS_ADDR_DONE_BIT = 2;
+    const uint32_t ALTD_STATUS_DATA_DONE_BIT = 3;
+    const uint32_t ALTD_STATUS_WAIT_RESP_BIT = 4;
+    const uint32_t ALTD_STATUS_OVERRUN_ERROR_BIT = 5;
+    const uint32_t ALTD_STATUS_AUTOINC_ERR_BIT = 6;
+    const uint32_t ALTD_STATUS_COMMAND_ERR_BIT = 7;
+    const uint32_t ALTD_STATUS_ADDRESS_ERR_BIT = 8;
+    const uint32_t ALTD_STATUS_PB_OP_HANG_ERR_BIT = 9;
+    const uint32_t ALTD_STATUS_PB_DATA_HANG_ERR_BIT = 10;
+    const uint32_t ALTD_STATUS_PB_UNEXPECT_CRESP_ERR_BIT = 11;
+    const uint32_t ALTD_STATUS_WAIT_PIB_DIRECT = 16;
+    const uint32_t ALTD_STATUS_PIB_DIRECT_DONE = 17;
+    const uint32_t ALTD_STATUS_PBINIT_MISSING_BIT = 18;
+    const uint32_t ALTD_STATUS_ECC_CE_BIT = 48;
+    const uint32_t ALTD_STATUS_ECC_UE_BIT = 49;
+    const uint32_t ALTD_STATUS_ECC_SUE_BIT = 50;
+    const uint32_t ALTD_STATUS_CRESP_START_BIT = 59;
+    const uint32_t ALTD_STATUS_CRESP_END_BIT = 63;
+
+    const uint32_t ALTD_STATUS_CRESP_NUM_BITS = (ALTD_STATUS_CRESP_END_BIT
+            - ALTD_STATUS_CRESP_START_BIT + 1);
+
+    //FORCE ECC Register field/bit definitions
+    const uint32_t ALTD_DATA_ITAG_BIT = 0;
+    const uint32_t ALTD_DATA_TX_ECC_START_BIT = 1;
+    const uint32_t ALTD_DATA_TX_ECC_END_BIT = 16;
+    const uint32_t ALTD_DATA_TX_ECC_OVERWRITE_BIT = 17;
+
+    const uint32_t ALTD_DATA_ECC_MASK = 0xFFFFull;
+
+    // ADU operation delay times for HW/sim
+    const uint32_t PROC_ADU_UTILS_ADU_HW_NS_DELAY = 100000;
+    const uint32_t PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY = 50000;
+    const uint32_t PROC_ADU_UTILS_ADU_STATUS_SIM_CYCLE_DELAY = 20000;
+
+    //---------------------------------------------------------------------------------
+    // Function definitions
+    //---------------------------------------------------------------------------------
+
+    //---------------------------------------------------------------------------------
+    // NOTE: description in header
+    //---------------------------------------------------------------------------------
+    fapi2::ReturnCode p9_adu_coherent_utils_check_args(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_address,
+        const uint32_t i_flags)
+    {
+        FAPI_DBG("Start");
+
+        p9_ADU_oper_flag l_myAduFlag;
+        p9_ADU_oper_flag::Transaction_size_t l_transSize;
+        uint32_t l_actualTransSize;
+
+        l_transSize = l_myAduFlag.getTransactionSize();
+
+        if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 )
+        {
+            l_actualTransSize = 1;
+        }
+        else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 )
+        {
+            l_actualTransSize = 2;
+        }
+        else if ( l_transSize == p9_ADU_oper_flag::TSIZE_4 )
+        {
+            l_actualTransSize = 4;
+        }
+        else
+        {
+            l_actualTransSize = 8;
+        }
+
+        //Check the address alignment
+        FAPI_ASSERT(!(i_address & (l_actualTransSize - 1)),
+                    fapi2::P9_ADU_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS(
+                        i_address),
+                    "Address is not cacheline aligned");
+
+        //Make sure the address is within the ADU bounds
+        FAPI_ASSERT(i_address <= P9_FBC_UTILS_FBC_MAX_ADDRESS,
+                    fapi2::P9_ADU_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS(
+                        i_address),
+                    "Address exceeds supported fabric real address range");
+
+
+    fapi_try_exit:
+        FAPI_DBG("Exiting...");
+        return fapi2::current_err;
+    }
+
+    //---------------------------------------------------------------------------------
+    // NOTE: description in header
+    //---------------------------------------------------------------------------------
+    fapi2::ReturnCode p9_adu_coherent_utils_check_fbc_state(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+    {
+        bool fbc_initialized = false;
+        bool fbc_running = false;
+        FAPI_DBG("Start");
+
+        //Make sure the fabric is initialized and running
+        FAPI_TRY(p9_fbc_utils_get_fbc_state(i_target, fbc_initialized, fbc_running),
+                 "Error from p9_fbc_utils_get_fbc_state");
+        FAPI_ASSERT(fbc_initialized
+                    && fbc_running, fapi2::P9_ADU_FBC_NOT_INITIALIZED_ERR().set_TARGET(i_target).set_INITIALIZED(
+                        fbc_initialized).set_RUNNING(
+                        fbc_running), "Fabric is not initialized or running");
+
+    fapi_try_exit:
+        FAPI_DBG("End");
+        return fapi2::current_err;
+
+    }
+
+    //---------------------------------------------------------------------------------
+    // NOTE: description in header
+    //---------------------------------------------------------------------------------
+    fapi2::ReturnCode p9_adu_coherent_utils_get_num_granules(
+        const uint64_t i_address,
+        uint32_t& o_numGranules)
+    {
+        fapi2::ReturnCode rc;
+        FAPI_DBG("Start");
+        //From the address figure out when it is going to no longer be within the ADU bound by
+        //doing the max fbc address minus the address and then divide by 8 to get number of bytes
+        //and by 8 to get number of 8 byte granules that can be sent
+        o_numGranules = ((P9_FBC_UTILS_FBC_MAX_ADDRESS - i_address) / 8) / 8;
+        FAPI_DBG("Exiting");
+        return rc;
+    }
+
+
+
+    ///
+    /// @brief Setup the value for ADU option register to enable
+    ///        quiesce & init around a switch operation.
+    ///
+    /// @param [in] i_target   Proc target
+    ///
+    /// @return FAPI2_RC_SUCCESS if OK
+    ///
+    fapi2::ReturnCode setQuiesceInit(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+    {
+        FAPI_DBG("Start");
+        fapi2::ReturnCode l_rc;
+        fapi2::buffer<uint64_t> altd_option_reg_data(0);
+
+        // Set up quiesce
+        altd_option_reg_data.setBit<FBC_ALTD_WITH_PRE_QUIESCE>();
+        altd_option_reg_data.insertFromRight<FBC_ALTD_PRE_QUIESCE_COUNT_START_BIT,
+                                             FBC_ALTD_PRE_QUIESCE_COUNT_NUM_OF_BITS>
+                                             (QUIESCE_SWITCH_WAIT_COUNT);
+
+        // Setup Post-command init
+        altd_option_reg_data.setBit<FBC_ALTD_WITH_POST_INIT>();
+        altd_option_reg_data.insertFromRight<FBC_ALTD_POST_INIT_COUNT_START_BIT,
+                                             FBC_ALTD_POST_INIT_COUNT_NUM_OF_BITS>
+                                             (INIT_SWITCH_WAIT_COUNT);
+
+        // Write to ADU option reg
+        FAPI_DBG("OPTION reg value 0x%016llX", altd_option_reg_data);
+        FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_OPTION_REG, altd_option_reg_data),
+                 "Error writing to PU_ALTD_OPTION_REG register");
+
+    fapi_try_exit:
+        FAPI_DBG("Exiting...");
+        return fapi2::current_err;
+    }
+
+    //---------------------------------------------------------------------------------
+    // NOTE: description in header
+    //---------------------------------------------------------------------------------
+    fapi2::ReturnCode p9_adu_coherent_setup_adu(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_address,
+        const bool i_rnw,
+        const uint32_t i_flags)
+    {
+        FAPI_DBG("Start Addr 0x%.16llX, Flag 0x%.8X", i_address, i_flags);
+
+        fapi2::ReturnCode rc;
+        fapi2::buffer<uint64_t> altd_cmd_reg_data(0x0);
+        fapi2::buffer<uint64_t> altd_addr_reg_data(i_address);
+        fapi2::buffer<uint64_t> altd_data_reg_data(0x0);
+        fapi2::buffer<uint64_t> altd_option_reg(0x0);
+        p9_ADU_oper_flag l_myAduFlag;
+        p9_ADU_oper_flag::OperationType_t l_operType;
+        p9_ADU_oper_flag::Transaction_size_t l_transSize;
+
+        // Write to the altd_cmd_reg to set the fbc_locked bit
+        altd_cmd_reg_data.setBit<ALTD_CMD_LOCK_BIT>();
+        FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data),
+                 "Error writing the lock bit to ALTD_CMD Register");
+
+        //Write the address into altd_addr_reg
+        FAPI_DBG("Write PU_ALTD_ADDR_REG 0x%.16llX, Value 0x%.16llX",
+                 PU_ALTD_ADDR_REG, altd_addr_reg_data);
+        FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_ADDR_REG, altd_addr_reg_data),
+                 "Error writing to ALTD_ADDR Register");
+
+        // Process input flag
+        l_myAduFlag.getFlag(i_flags);
+        l_operType = l_myAduFlag.getOperationType();
+        l_transSize = l_myAduFlag.getTransactionSize();
+
+        // ---------------------------------------------
+        // Setting for DMA and CI operations
+        // ---------------------------------------------
+        if ( (l_operType == p9_ADU_oper_flag::CACHE_INHIBIT) ||
+             (l_operType == p9_ADU_oper_flag::DMA_PARTIAL) )
+        {
+
+            // ---------------------------------------------
+            // DMA & CI common settings
+            // ---------------------------------------------
+            // Write the altd_cmd_reg
+            // Set fbc_altd_rnw if it's a read
+            if (i_rnw)
+            {
+                altd_cmd_reg_data.setBit<ALTD_CMD_RNW_BIT>();
+            }
+            // Clear fbc_altd_rnw if it's a write
+            else
+            {
+                altd_cmd_reg_data.clearBit<ALTD_CMD_RNW_BIT>();
+            }
+
+            // If auto-inc set the auto-inc bit
+            if (l_myAduFlag.getAutoIncrement() == true)
+            {
+                altd_cmd_reg_data.setBit<ALTD_CMD_AUTO_INC_BIT>();
+            }
+
+            // ---------------------------------------------------
+            // Cache Inhibit specific: TTYPE & TSIZE
+            // ---------------------------------------------------
+            if (l_operType == p9_ADU_oper_flag::CACHE_INHIBIT)
+            {
+                FAPI_DBG("ADU operation type: Cache Inhibited");
+
+                // Set TTYPE
+                if (i_rnw)
+                {
+                    altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_CI_PR_RD);
+                }
+                else
+                {
+                    altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_CI_PR_WR);
+                }
+
+                // Set TSIZE
+                if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 )
+                {
+                    altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
+                                                      ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_CI_TSIZE_1);
+                }
+                else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 )
+                {
+                    altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
+                                                      ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_CI_TSIZE_2);
+                }
+                else if ( l_transSize == p9_ADU_oper_flag::TSIZE_4 )
+                {
+                    altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
+                                                      ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_CI_TSIZE_4);
+                }
+                else
+                {
+                    altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
+                                                      ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_CI_TSIZE_8);
+                }
+            }
+
+            // ---------------------------------------------------
+            // DMA specific: TTYPE & TSIZE
+            // ---------------------------------------------------
+            else if (l_operType == p9_ADU_oper_flag::DMA_PARTIAL)
+            {
+                FAPI_DBG("ADU operation type: DMA");
+
+                // If a read, set ALTD_CMD_TTYPE_CL_DMA_RD
+                // Set the tsize to ALTD_CMD_DMAR_TSIZE
+                if (i_rnw)
+                {
+                    altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_CL_DMA_RD);
+                    altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
+                                                      ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAR_TSIZE);
+                }
+                // If a write set ALTD_CMD_TTYPE_DMA_PR_WR
+                // Set the tsize according to flag setting
+                else
+                {
+                    altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT,
+                                                      ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_DMA_PR_WR);
+
+                    // Set TSIZE
+                    if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 )
+                    {
+                        altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
+                                                          ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAW_TSIZE_1);
+                    }
+                    else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 )
+                    {
+                        altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
+                                                          ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAW_TSIZE_2);
+                    }
+                    else if ( l_transSize == p9_ADU_oper_flag::TSIZE_4 )
+                    {
+                        altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
+                                                          ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAW_TSIZE_4);
+                    }
+                    else
+                    {
+                        altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
+                                                          ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_DMAW_TSIZE_8);
+                    }
+                }
+            }
+        }
+
+        // ---------------------------------------------
+        // Setting for PB and PMISC operations
+        // ---------------------------------------------
+        if ( (l_operType == p9_ADU_oper_flag::PB_OPER) ||
+             (l_operType == p9_ADU_oper_flag::PMISC_OPER) )
+        {
+
+            // ---------------------------------------------
+            // PB & PMISC common settings
+            // ---------------------------------------------
+
+            // Set the start op bit
+            altd_cmd_reg_data.setBit<ALTD_CMD_START_OP_BIT>();
+
+            // Set operation scope
+            altd_cmd_reg_data.insertFromRight<ALTD_CMD_SCOPE_START_BIT,
+                                              ALTD_CMD_SCOPE_NUM_BITS>(ALTD_CMD_SCOPE_SYSTEM);
+
+            // Set DROP_PRIORITY = HIGH
+            altd_cmd_reg_data.setBit<ALTD_CMD_DROP_PRIORITY_BIT>();
+
+            // Set AXTYPE = Address only
+            altd_cmd_reg_data.setBit<ALTD_CMD_ADDRESS_ONLY_BIT>();
+
+            // Set OVERWRITE_PBINIT
+            altd_cmd_reg_data.setBit<ALTD_CMD_OVERWRITE_PBINIT_BIT>();
+
+            // Set TM_QUIESCE
+            altd_cmd_reg_data.setBit<ALTD_CMD_WITH_TM_QUIESCE_BIT>();
+
+
+            // ---------------------------------------------------
+            // PB specific: TTYPE & TSIZE
+            // ---------------------------------------------------
+            if (l_operType == p9_ADU_oper_flag::PB_OPER)
+            {
+                FAPI_DBG("ADU operation type: PB");
+
+                // Set TTYPE
+                altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT,
+                                                  ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_PB_OPER);
+
+                // TSIZE for PB operation is fixed value: 0b00001000
+                altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
+                                                  ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PB_OPERATION_TSIZE);
+            }
+
+            // ---------------------------------------------------
+            // PMISC specific: TTYPE & TSIZE
+            // ---------------------------------------------------
+            else if (l_operType == p9_ADU_oper_flag::PMISC_OPER)
+            {
+                FAPI_DBG("ADU operation type: PMISC");
+
+                // Set TTYPE
+                altd_cmd_reg_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT,
+                                                  ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_PMISC_OPER);
+
+                // Set TSIZE
+                if ( l_transSize == p9_ADU_oper_flag::TSIZE_1 )
+                {
+                    altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
+                                                      ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PMISC_TSIZE_1);
+                }
+                else if ( l_transSize == p9_ADU_oper_flag::TSIZE_2 )
+                {
+                    altd_cmd_reg_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT,
+                                                      ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_PMISC_TSIZE_2);
+                }
+
+                // Set quiesce and init around a switch operation in option reg
+                FAPI_TRY(setQuiesceInit(i_target), "setQuiesceInit() returns error");
+            }
+        }
+
+        //This sets everything that should be set for the ALTD_CMD_Register
+        FAPI_DBG("CMD reg value 0x%016llX", altd_cmd_reg_data);
+
+        FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data),
+                 "Error writing to ALTD_CMD Register");
+
+    fapi_try_exit:
+        FAPI_DBG("Exiting...");
+        return fapi2::current_err;
+    }
+
+    //---------------------------------------------------------------------------------
+    // NOTE: description in header
+    //---------------------------------------------------------------------------------
+    fapi2::ReturnCode p9_adu_coherent_adu_write(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const bool i_firstGranule,
+        const uint64_t i_address,
+        p9_ADU_oper_flag& i_aduOper,
+        const uint8_t i_write_data[])
+    {
+        FAPI_DBG("Start");
+
+        fapi2::buffer<uint64_t> altd_cmd_reg_data;
+        fapi2::buffer<uint64_t> altd_status_reg_data;
+        fapi2::buffer<uint64_t> force_ecc_reg_data;
+        uint64_t write_data = 0x0ull;
+        int eccIndex = 8;
+
+        // Get ADU operation info from flag
+        bool l_itagMode          = i_aduOper.getItagMode();
+        bool l_eccMode           = i_aduOper.getEccMode();
+        bool l_overrideEccMode   = i_aduOper.getEccItagOverrideMode();
+        bool l_autoIncMode       = i_aduOper.getAutoIncrement();
+        bool l_accessForceEccReg = (l_itagMode | l_eccMode | l_overrideEccMode);
+
+        // Dump ADU write settings
+        FAPI_DBG("Modes: ITAG 0x%.8X, ECC 0x%.8X, OVERRIDE_ECC 0x%.8X",
+                 l_itagMode, l_eccMode, l_overrideEccMode);
+        FAPI_DBG("       AUTOINC 0x%.8X", l_autoIncMode);
+
+        for (int i = 0; i < 8; i++)
+        {
+            write_data |= ( static_cast<uint64_t>(i_write_data[i]) << (56 - (8 * i)) );
+        }
+
+        fapi2::buffer<uint64_t> altd_data_reg_data(write_data);
+
+        if (l_accessForceEccReg == true)
+        {
+            FAPI_TRY(fapi2::getScom(i_target, PU_FORCE_ECC_REG, force_ecc_reg_data), "Error reading the FORCE_ECC Register");
+        }
+
+        //if we want to write the itag bit set it
+        if (l_itagMode == true)
+        {
+            eccIndex++;
+            force_ecc_reg_data.setBit<ALTD_DATA_ITAG_BIT>();
+        }
+
+        //if we want to write the ecc data get the data
+        if (l_eccMode == true)
+        {
+            force_ecc_reg_data.insertFromRight < ALTD_DATA_TX_ECC_START_BIT,
+                                               (ALTD_DATA_TX_ECC_END_BIT - ALTD_DATA_TX_ECC_START_BIT) + 1 >
+                                               ((uint64_t)i_write_data[eccIndex]);
+        }
+
+        //if we want to overwrite the ecc data
+        if (l_overrideEccMode == true)
+        {
+            force_ecc_reg_data.setBit<ALTD_DATA_TX_ECC_OVERWRITE_BIT>();
+        }
+
+        if (l_accessForceEccReg == true)
+        {
+            FAPI_TRY(fapi2::putScom(i_target, PU_FORCE_ECC_REG, force_ecc_reg_data), "Error writing to the FORCE_ECC Register");
+        }
+
+        //write the data into the altd_data_reg
+        FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_DATA_REG, altd_data_reg_data),
+                 "Error writing to ALTD_DATA Register");
+
+        //Set the ALTD_CMD_START_OP bit to start the write(first granule for autoinc case or not autoinc)
+        if ( i_firstGranule || (l_autoIncMode == false) )
+        {
+            //read the altd_cmd_register
+            FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error reading from the ALTD_CMD_REG");
+            //set the start op bit
+            altd_cmd_reg_data.setBit<ALTD_CMD_START_OP_BIT>();
+            //write the altd_cmd_register
+            FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error writing to the ALTD_CMD_REG");
+        }
+
+        //delay to allow time for the write to go through before we check the status
+        FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_HW_NS_DELAY,
+                              PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY),
+                 "fapiDelay error");
+
+    fapi_try_exit:
+        FAPI_DBG("Exiting...");
+        return fapi2::current_err;
+    }
+
+    //---------------------------------------------------------------------------------
+    // NOTE: description in header
+    //---------------------------------------------------------------------------------
+    fapi2::ReturnCode p9_adu_coherent_adu_read(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const bool i_firstGranule,
+        const uint64_t i_address,
+        p9_ADU_oper_flag& i_aduOper,
+        uint8_t o_read_data[])
+    {
+        FAPI_DBG("Start");
+
+        fapi2::buffer<uint64_t> altd_cmd_reg_data;
+        fapi2::buffer<uint64_t> altd_status_reg_data;
+        fapi2::buffer<uint64_t> altd_data_reg_data;
+        fapi2::buffer<uint64_t> force_ecc_reg_data;
+        int eccIndex = 8;
+
+        // Get ADU operation info from flag
+        bool l_itagMode          = i_aduOper.getItagMode();
+        bool l_eccMode           = i_aduOper.getEccMode();
+        bool l_autoIncMode       = i_aduOper.getAutoIncrement();
+
+        // Dump ADU read settings
+        FAPI_DBG("Modes: ITAG 0x%.8X, ECC 0x%.8X, AUTOINC 0x%.8X",
+                 l_itagMode, l_eccMode, l_autoIncMode);
+
+        //Set the ALTD_CMD_START_OP bit to start the read(first granule for autoinc case or not autoinc)
+        if ( i_firstGranule || (l_autoIncMode == false) )
+        {
+            //read the altd_cmd_register
+            FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error reading from the ALTD_CMD_REG");
+            //set the start op bit
+            altd_cmd_reg_data.setBit<ALTD_CMD_START_OP_BIT>();
+            //write the altd_cmd_register
+            FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error writing to the ALTD_CMD_REG");
+        }
+
+        //delay to allow time for the read to go through before we get the data
+        FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_HW_NS_DELAY,
+                              PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY),
+                 "fapiDelay error");
+
+
+        //if we want to include the itag and ecc data collect them before the read
+        if ( l_itagMode || l_eccMode )
+        {
+            FAPI_TRY(fapi2::getScom(i_target, PU_FORCE_ECC_REG, force_ecc_reg_data),
+                     "Error reading from the FORCE_ECC Register");
+        }
+
+        if (l_itagMode)
+        {
+            eccIndex = 9;
+            o_read_data[8] = force_ecc_reg_data.getBit<ALTD_DATA_ITAG_BIT>();
+        }
+
+        if (l_eccMode)
+        {
+            o_read_data[eccIndex] = (force_ecc_reg_data >> (63 - ALTD_DATA_TX_ECC_END_BIT)) & ALTD_DATA_ECC_MASK;
+        }
+
+        //read data from altd_data_reg
+        FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_DATA_REG, altd_data_reg_data),
+                 "Error reading from the ALTD_DATA Register");
+
+        for (int i = 0; i < 8; i++)
+        {
+            o_read_data[i] = (altd_data_reg_data >> (56 - (i * 8))) & 0xFFull;
+        }
+
+        FAPI_DBG("o_read_data[8] = %8X", o_read_data[8]);
+        //o_read_data[0] = altd_data_reg_data;
+        FAPI_DBG("altd_data_reg_data = %lu\n", altd_data_reg_data);
+
+    fapi_try_exit:
+        FAPI_DBG("Exiting...");
+        return fapi2::current_err;
+    }
+
+    fapi2::ReturnCode p9_adu_coherent_utils_reset_adu(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+    {
+        FAPI_DBG("Start");
+
+        fapi2::buffer<uint64_t> altd_cmd_reg_data(0x0);
+
+        FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data), "Error reading from ALTD_CMD Register");
+
+        //write altd_cmd_reg to set the reset_fsm bit
+        altd_cmd_reg_data.setBit<ALTD_CMD_RESET_FSM_BIT>();
+        altd_cmd_reg_data.setBit<ALTD_CMD_CLEAR_STATUS_BIT>();
+        altd_cmd_reg_data.setBit<ALTD_CMD_LOCK_BIT>();
+        FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data),
+                 "Error setting the reset_fsm bit from the ALTD_CMD Register");
+
+    fapi_try_exit:
+        FAPI_DBG("Exiting...");
+        return fapi2::current_err;
+    }
+
+    //---------------------------------------------------------------------------------
+    // NOTE: description in header
+    //---------------------------------------------------------------------------------
+    fapi2::ReturnCode p9_adu_coherent_cleanup_adu(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+    {
+        FAPI_DBG("Start");
+
+        fapi2::buffer<uint64_t> altd_cmd_reg_data(0x0);
+
+        FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data),
+                 "Error reading from ALTD_CMD Register");
+
+        //write altd_cmd_reg to clear the fbc_locked bit
+        altd_cmd_reg_data.clearBit<ALTD_CMD_LOCK_BIT>();
+        FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data),
+                 "Error clearing the fbc_locked bit from the ALTD_CMD Register");
+
+    fapi_try_exit:
+        FAPI_DBG("Exiting...");
+        return fapi2::current_err;
+    }
+
+    fapi2::ReturnCode p9_adu_coherent_status_check(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const adu_status_busy_handler i_busyBitHandler,
+        const bool i_addressOnlyOper,
+        bool& o_busyBitStatus)
+    {
+        FAPI_DBG("Start");
+
+        fapi2::buffer<uint64_t> l_statusReg(0x0);
+        bool l_statusError = false;
+
+        for (int i = 0; i < 10; i++)
+        {
+            l_statusError = false;
+            // Check the ALTD_STATUS_REG
+            FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_STATUS_REG, l_statusReg),
+                     "Error reading from ALTD_STATUS Register");
+            FAPI_DBG("PU_ALTD_STATUS_REG reg value 0x%016llX", l_statusReg);
+
+            // ---- Handle busy options ----
+
+            // Get busy bit output
+            o_busyBitStatus = l_statusReg.getBit<ALTD_STATUS_BUSY_BIT>();
+
+            // Handle busy bit according to specified input
+            if (o_busyBitStatus == true)
+            {
+                // Exit if busy
+                if (i_busyBitHandler == EXIT_ON_BUSY)
+                {
+                    goto fapi_try_exit;
+                }
+                else if (i_busyBitHandler == EXPECTED_BUSY_BIT_CLEAR)
+                {
+                    l_statusError = true;
+                }
+            }
+            else if (i_busyBitHandler == EXPECTED_BUSY_BIT_SET)
+            {
+                l_statusError = true;
+            }
+
+            // ---- Check for other errors ----
+            // Check the WAIT_CMD_ARBIT bit and make sure it's 0
+            // Check the ADDR_DONE bit and make sure it's set
+            // Check the DATA_DONE bit and make sure it's set
+            // Check the WAIT_RESP bit to make sure it's clear
+            // Check the OVERRUN_ERR to make sure it's clear
+            // Check the AUTOINC_ERR to make sure it's clear
+            // Check the COMMAND_ERR to make sure it's clear
+            // Check the ADDRESS_ERR to make sure it's clear
+            // Check the COMMAND_HANG_ERR to make sure it's clear
+            // Check the DATA_HANG_ERR to make sure it's clear
+            // Check the PBINIT_MISSING to make sure it's clear
+            // Check the ECC_CE to make sure it's clear
+            // Check the ECC_UE to make sure it's clear
+            // Check the ECC_SUE to make sure it's clear
+            l_statusError =
+                ( l_statusError ||
+                  l_statusReg.getBit<ALTD_STATUS_WAIT_CMD_ARBIT>()        ||
+                  !l_statusReg.getBit<ALTD_STATUS_ADDR_DONE_BIT>()        ||
+                  l_statusReg.getBit<ALTD_STATUS_WAIT_RESP_BIT>()         ||
+                  l_statusReg.getBit<ALTD_STATUS_OVERRUN_ERROR_BIT>()     ||
+                  l_statusReg.getBit<ALTD_STATUS_AUTOINC_ERR_BIT>()       ||
+                  l_statusReg.getBit<ALTD_STATUS_COMMAND_ERR_BIT>()       ||
+                  l_statusReg.getBit<ALTD_STATUS_ADDRESS_ERR_BIT>()       ||
+                  l_statusReg.getBit<ALTD_STATUS_PB_OP_HANG_ERR_BIT>()    ||
+                  l_statusReg.getBit<ALTD_STATUS_PB_DATA_HANG_ERR_BIT>()  ||
+                  l_statusReg.getBit<ALTD_STATUS_PBINIT_MISSING_BIT>()    ||
+                  l_statusReg.getBit<ALTD_STATUS_ECC_CE_BIT>()            ||
+                  l_statusReg.getBit<ALTD_STATUS_ECC_UE_BIT>()            ||
+                  l_statusReg.getBit<ALTD_STATUS_ECC_SUE_BIT>()
+                );
+
+            // If Address only operation, do not check for ALTD_STATUS_DATA_DONE_BIT
+            if ( i_addressOnlyOper == false )
+            {
+                l_statusError |= !l_statusReg.getBit<ALTD_STATUS_DATA_DONE_BIT>();
+            }
+
+            if (!l_statusError)
+            {
+                break;
+            }
+
+            FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_HW_NS_DELAY,
+                                  PROC_ADU_UTILS_ADU_STATUS_SIM_CYCLE_DELAY),
+                     "fapiDelay error");
+        }
+
+        // If error, display trace
+        if (l_statusError)
+        {
+            FAPI_ERR("Status mismatch detected");
+
+            FAPI_ERR("FBC_ALTD_BUSY = %d", (o_busyBitStatus ? 1 : 0));
+            FAPI_ERR("ALTD_STATUS_REG = %016llX", l_statusReg);
+        }
+
+        FAPI_ASSERT( (l_statusError == false), fapi2::P9_ADU_STATUS_REG_ERR()
+                     .set_TARGET(i_target)
+                     .set_STATUSREG(l_statusReg),
+                     "Status Register check error");
+
+    fapi_try_exit:
+        FAPI_DBG("Exiting...");
+        return fapi2::current_err;
+    }
+
+    fapi2::ReturnCode p9_adu_coherent_clear_autoinc(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+    {
+        FAPI_DBG("Start");
+
+        fapi2::buffer<uint64_t> altd_cmd_reg_data;
+
+        FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data),
+                 "Error reading from ALTD_CMD Register");
+
+        altd_cmd_reg_data.clearBit<ALTD_CMD_AUTO_INC_BIT>();
+        FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, altd_cmd_reg_data),
+                 "Error clearing the auto_inc bit from the ALTD_CMD Register");
+
+    fapi_try_exit:
+        FAPI_DBG("Exiting...");
+        return fapi2::current_err;
+    }
+
+    fapi2::ReturnCode p9_adu_coherent_manage_lock(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+            const bool i_lock_pick,
+            const bool i_lock,
+            const uint32_t i_num_attempts)
+    {
+        FAPI_DBG("Start");
+
+        fapi2::ReturnCode rc;
+        fapi2::buffer<uint64_t> lock_control(0x0);
+        uint32_t attempt_count = 1;
+        bool lock_pick_first_time = true;
+
+        // validate input parameters
+        if (i_num_attempts == 0)
+        {
+            FAPI_ERR("Invalid value %d for number of lock manipulation attempts",
+                     i_num_attempts);
+        }
+
+        // set up data buffer to perform desired lock manipulation operation
+        if (i_lock)
+        {
+            FAPI_DBG("Configuring lock manipulation control data buffer to perform lock acquisition");
+            lock_control.setBit(ALTD_CMD_LOCK_BIT);
+        }
+        else
+        {
+            FAPI_DBG("Configuring lock manipulation control data buffer to perform lock release");
+        }
+
+        // try to lock/unlock the lock the number of times specified with i_num_attempts
+        while (1)
+        {
+            // write ADU command register to attempt lock manipulation
+            FAPI_DBG("Writing ADU Command register to attempt lock manipulation");
+            rc = fapi2::putScom(i_target, PU_ALTD_CMD_REG, lock_control);
+
+            // pass back return code to caller unless it specifically indicates
+            // that the ADU lock manipulation was unsuccessful and we're going
+            // to try again
+            if ((rc != fapi2::FAPI2_RC_PLAT_ERR_ADU_LOCKED)
+                || (attempt_count == i_num_attempts))
+            {
+                // rc does not indicate success
+                if (rc)
+                {
+                    // rc does not indicate lock held, exit
+                    if (rc != fapi2::FAPI2_RC_PLAT_ERR_ADU_LOCKED)
+                    {
+                        FAPI_ERR("fapiPutScom error (PU_ALTD_CMD_REG)");
+                        break;
+                    }
+
+                    // rc indicates lock held, out of attempts
+                    if (attempt_count == i_num_attempts)
+                    {
+                        //if out of attempts but lock pick is desired try to pick the lock once and see if it works
+                        if (i_lock_pick && i_lock && lock_pick_first_time)
+                        {
+                            lock_control.setBit(ALTD_CMD_LOCK_PICK_BIT);
+                            attempt_count--;
+                            lock_pick_first_time = false;
+                            FAPI_DBG("Trying to do a lock pick as desired");
+                        }
+                        else
+                        {
+                            FAPI_ERR("Desired ADU lock manipulation was not successful after %d attempts",
+                                     i_num_attempts);
+                            break;
+                        }
+                    }
+                }
+
+                // rc clean, lock management operation successful
+                FAPI_DBG("Lock manipulation successful or going to try a lock pick");
+                break;
+            }
+
+            // delay to provide time for ADU lock to be released
+            FAPI_TRY(fapi2::delay(PROC_ADU_UTILS_ADU_HW_NS_DELAY,
+                                  PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY),
+                     "fapiDelay error");
+
+            // increment attempt count, loop again
+            attempt_count++;
+            FAPI_DBG("Attempt %d of %d", attempt_count,
+                     i_num_attempts);
+        }
+
+    fapi_try_exit:
+
+        //if there is an error from trying to lock/unlock
+        if(rc)
+        {
+            fapi2::current_err = rc;
+        }
+
+        FAPI_DBG("End");
+        return fapi2::current_err;
+
+    }
+
+} // extern "C
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H
new file mode 100644
index 00000000..667e3f6b
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H
@@ -0,0 +1,666 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_adu_coherent_utils.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------------
+// *!
+/// @file p9_adu_coherent_utils.H
+/// @brief Common Code to support ADU get/putmem procedures (FAPI)
+///
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by:
+// ---------------------------------------------------------------------------------
+// *! ADDITIONAL COMMENTS :
+// *!
+// *!
+//-----------------------------------------------------------------------------------
+
+#ifndef _P9_ADU_COHERENT_UTILS_H_
+#define _P9_ADU_COHERENT_UTILS_H_
+
+//-----------------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------------
+
+#include <fapi2.H>
+#include <p9_adu_constants.H>
+
+// Definitions of how to handle Busy state of the ADU when
+// checking its status.
+enum adu_status_busy_handler
+{
+    EXPECTED_BUSY_BIT_CLEAR = 0,  // Expect to be clear, error if not
+    EXPECTED_BUSY_BIT_SET   = 1,  // Expect to be set, error if not
+    EXIT_ON_BUSY            = 2   // Return Busy status without checking
+                              // any other errors.
+};
+
+extern"C"
+{
+
+//-----------------------------------------------------------------------------------
+// Constant definitions
+//-----------------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------------
+// Classes
+//-----------------------------------------------------------------------------------
+///
+/// @brief  Manage ADU operation flag that is used to program the
+//          ADU CMD register, PU_ALTD_CMD_REG (Addr: 0x00090001)
+///
+    class p9_ADU_oper_flag
+    {
+        public:
+
+            // Type of ADU operations
+            enum OperationType_t
+            {
+                CACHE_INHIBIT = 0,
+                DMA_PARTIAL   = 1,
+                PB_OPER       = 2,
+                PMISC_OPER    = 3
+            };
+
+            // Transaction size
+            enum Transaction_size_t
+            {
+                TSIZE_1 = 1,
+                TSIZE_2 = 2,
+                TSIZE_4 = 4,
+                TSIZE_8 = 8
+            };
+
+            // Constructor
+            inline p9_ADU_oper_flag()
+                : iv_operType(CACHE_INHIBIT), iv_autoInc(false), iv_lockPick(false),
+                  iv_numLockAttempts(1), iv_cleanUp(true), iv_fastMode(false),
+                  iv_itag(false), iv_ecc(false), iv_eccItagOverwrite(false),
+                  iv_transSize(TSIZE_1)
+            {
+            }
+
+            ///
+            /// @brief Set the ADU operation type
+            ///
+            /// @param[in] i_type     ADU operation type
+            ///
+            /// @return void.
+            ///
+            inline void setOperationType(const OperationType_t i_type)
+            {
+                iv_operType = i_type;
+                return;
+            }
+
+            ///
+            /// @brief Get the ADU operation type setting.
+            ///
+            /// @return iv_operType.
+            ///
+            inline const OperationType_t getOperationType(void)
+            {
+                return iv_operType;
+            }
+
+            /// @brief Set the Auto Increment option, for CI/DMA operations only.
+            ///
+            /// @param[in] i_value     True: Enable auto inc; False: Disable
+            ///
+            /// @return void.
+            ///
+            inline void setAutoIncrement(bool i_value)
+            {
+                if ( (iv_operType != CACHE_INHIBIT) &&
+                     (iv_operType != DMA_PARTIAL) )
+                {
+                    FAPI_ERR("WARNING: Set AUTOINC for non CI/DMA operation, Operation type 0x%.8X",
+                             iv_operType);
+                }
+
+                iv_autoInc = i_value;
+                return;
+            }
+
+            /// @brief Get the Auto Increment setting, for CI/DMA operations only.
+            ///
+            /// @return iv_autoInc.
+            ///
+            inline const bool getAutoIncrement(void)
+            {
+                if ( (iv_operType != CACHE_INHIBIT) &&
+                     (iv_operType != DMA_PARTIAL) )
+                {
+                    FAPI_ERR("WARNING: AUTOINC value is invalid for non CI/DMA operation, Operation type 0x%.8X",
+                             iv_operType);
+                }
+
+                return iv_autoInc;
+            }
+
+            ///
+            /// @brief Set ADU lock control
+            ///
+            /// @param[in] i_value     True: Attempt lock ADU before operation
+            ///                        False: No lock attempt
+            ///
+            /// @return void
+            ///
+            inline void setLockControl(bool i_value)
+            {
+                iv_lockPick = i_value;
+                return;
+            }
+
+            ///
+            /// @brief Get the ADU lock control setting.
+            ///
+            /// @return iv_lockPick.
+            ///
+            inline const bool getLockControl(void)
+            {
+                return iv_lockPick;
+            }
+
+            ///
+            /// @brief Set number of lock attempts
+            ///
+            /// @param[in] i_value     Num of lock attempts to try. If still can't lock
+            ///                        ADU, return an error.
+            ///
+            /// @return void
+            ///
+            inline void setNumLockAttempts(uint8_t i_value)
+            {
+                iv_numLockAttempts = i_value;
+                return;
+            }
+
+            ///
+            /// @brief Get number of lock attempts setting.
+            ///
+            /// @return iv_numLockAttempts.
+            ///
+            inline const uint8_t getNumLockAttempts(void)
+            {
+                return iv_numLockAttempts;
+            }
+
+            ///
+            /// @brief Clean up if operation fails
+            ///
+            /// @param[in] i_value     True: Clean up and release lock if oper fails.
+            ///                        False: Leave ADU in fail state.
+            ///
+            /// @return void.
+            ///
+            inline void setOperFailCleanup(bool i_value)
+            {
+                iv_cleanUp = i_value;
+                return;
+            }
+
+            ///
+            /// @brief Get the clean up for failed operation setting.
+            ///
+            /// @return iv_cleanUp.
+            ///
+            inline const bool getOperFailCleanup(void)
+            {
+                return iv_cleanUp;
+            }
+
+            ///
+            /// @brief Set fast read/write mode.
+            ///        For fast read/write mode, no status check.  Otherwise,
+            ///        do status check after every read/write.
+            ///
+            /// @param[in] i_value     True: Enable fast read/write mode.
+            ///                        False: Disable fast read/write mode.
+            ///
+            /// @return void.
+            ///
+            inline void setFastMode(bool i_value)
+            {
+                iv_fastMode = i_value;
+                return;
+            }
+
+            ///
+            /// @brief Get the Fast mode setting.
+            ///
+            /// @return iv_fastMode.
+            ///
+            inline const bool getFastMode(void)
+            {
+                return iv_fastMode;
+            }
+
+            ///
+            /// @brief Set itag collection mode.
+            ///        Collect/set itag with each 8B read/write
+            ///        For a write only set if itag data should be 1
+            ///
+            /// @param[in] i_value     True: Collect itag
+            ///                        False: Don't collect itag.
+            ///
+            /// @return void.
+            ///
+            inline void setItagMode(bool i_value)
+            {
+                iv_itag = i_value;
+                return;
+            }
+
+            ///
+            /// @brief the ITAG collection mode.
+            ///
+            /// @return iv_itag.
+            ///
+            inline const bool getItagMode(void)
+            {
+                return iv_itag;
+            }
+
+            ///
+            /// @brief Set Ecc mode.
+            ///        Collect/set ecc with each 8B read/write
+            ///
+            /// @param[in] i_value     True: Collect ECC
+            ///                        False: Don't collect ECC.
+            ///
+            /// @return void.
+            ///
+            inline void setEccMode(bool i_value)
+            {
+                iv_ecc = i_value;
+                return;
+            }
+
+            ///
+            /// @brief Get the Ecc mode setting.
+            ///
+            /// @return iv_ecc.
+            ///
+            inline const bool getEccMode(void)
+            {
+                return iv_ecc;
+            }
+
+            ///
+            /// @brief Overwrite ECC/ITAG data mode.
+            ///
+            /// @param[in] i_value     Overwrite ECC
+            ///                        False: Don't overwrite ECC
+            ///
+            /// @return void.
+            ///
+            inline void setEccItagOverrideMode(bool i_value)
+            {
+                iv_eccItagOverwrite = i_value;
+                return;
+            }
+
+            ///
+            /// @brief Get the Overwrite ECC/ITAG data mode.
+            ///
+            /// @return iv_eccItagOverwrite.
+            ///
+            inline const bool getEccItagOverrideMode(void)
+            {
+                return iv_eccItagOverwrite;
+            }
+
+            ///
+            /// @brief Set transaction size
+            ///
+            /// @param[in] i_value     Transaction size
+            ///
+            /// @return void.
+            ///
+            inline void setTransactionSize(Transaction_size_t i_value)
+            {
+                iv_transSize = i_value;
+                return;
+            }
+
+            ///
+            /// @brief Get the transaction size
+            ///
+            /// @return iv_transSize.
+            ///
+            inline const Transaction_size_t getTransactionSize(void)
+            {
+                return iv_transSize;
+            }
+
+            ///
+            /// @brief Assemble the 32-bit ADU flag based on current
+            ///        info contained in this class.
+            ///        This flag is to be used in ADU interface call
+            ///        See flag bit definitions in p9_adu_constants.H
+            ///
+            /// @return uint32_t
+            ///
+            inline uint32_t setFlag();
+
+            ///
+            /// @brief Update the class instant variables with info
+            ///        embedded in the passed in flag value.
+            ///
+            /// @return void.
+            ///
+            inline void getFlag(uint32_t i_flag);
+
+        private:
+
+            // Class variables
+            OperationType_t iv_operType;         // Operation type
+            bool iv_autoInc;                     // Auto increment
+            bool iv_lockPick;                    // Lock ADU before operation
+            uint8_t iv_numLockAttempts;          // Number of lock attempts
+            bool iv_cleanUp;
+            bool iv_fastMode;                    // Fast ADU read/write mode
+            bool iv_itag;                        // Itag mode
+            bool iv_ecc;                         // ECC mode
+            bool iv_eccItagOverwrite;            // ECC/ITAG overwrite mode
+            Transaction_size_t iv_transSize;     // Transaction size
+    };
+
+///
+/// See doxygen in class definition
+///
+    uint32_t p9_ADU_oper_flag::setFlag()
+    {
+        uint32_t l_aduFlag = 0;
+
+        // Operation type
+        l_aduFlag |= (iv_operType << FLAG_ADU_TTYPE_SHIFT);
+
+        // Auto Inc
+        if (iv_autoInc == true)
+        {
+            l_aduFlag |= FLAG_AUTOINC;
+        }
+
+        // Lock pick
+        if (iv_lockPick == true)
+        {
+            l_aduFlag |= FLAG_LOCK_PICK;
+        }
+
+        // Lock attempts
+        l_aduFlag |= (iv_numLockAttempts << FLAG_LOCK_TRIES_SHIFT);
+
+        // Leave dirty
+        if (iv_cleanUp == false)
+        {
+            l_aduFlag |= FLAG_LEAVE_DIRTY;
+        }
+
+        // Fast mode
+        if (iv_fastMode == true)
+        {
+            l_aduFlag |= FLAG_ADU_FASTMODE;
+        }
+
+        // Itag
+        if (iv_itag == true)
+        {
+            l_aduFlag |= FLAG_ITAG;
+        }
+
+        // ECC
+        if (iv_ecc == true)
+        {
+            l_aduFlag |= FLAG_ECC;
+        }
+
+        // Overwrite ECC
+        if (iv_eccItagOverwrite == true)
+        {
+            l_aduFlag |= FLAG_OVERWRITE_ECC;
+        }
+
+        // Transaction size
+        if (iv_transSize == TSIZE_1)
+        {
+            l_aduFlag |= FLAG_SIZE_TSIZE_1;
+        }
+        else if (iv_transSize == TSIZE_2)
+        {
+            l_aduFlag |= FLAG_SIZE_TSIZE_2;
+        }
+        else if (iv_transSize == TSIZE_4)
+        {
+            l_aduFlag |= FLAG_SIZE_TSIZE_4;
+        }
+        else if (iv_transSize == TSIZE_8)
+        {
+            l_aduFlag |= FLAG_SIZE_TSIZE_8;
+        }
+        else
+        {
+            FAPI_ERR("Invalid transaction size: iv_transSize %d",  iv_transSize);
+        }
+
+        // Debug trace
+        FAPI_DBG("p9_ADU_oper_flag::setFlag()");
+        FAPI_DBG("    iv_operType 0x%.8X, iv_autoInc 0x%.8X, iv_lockPick 0x%.8X, iv_numLockAttempts 0x%.8X",
+                 iv_operType, iv_autoInc, iv_lockPick, iv_numLockAttempts);
+        FAPI_DBG("    iv_cleanUp 0x%.8X, iv_fastMode 0x%.8X, iv_itag 0x%.8X, iv_ecc 0x%.8X",
+                 iv_cleanUp, iv_fastMode, iv_itag, iv_ecc);
+        FAPI_DBG("    iv_eccItagOverwrite 0x%.8X, iv_transSize 0x%.8X",
+                 iv_eccItagOverwrite, iv_transSize);
+        FAPI_DBG("   ADU Flag value: 0x%.8X", l_aduFlag);
+
+        return l_aduFlag;
+    }
+
+///
+/// See doxygen in class definition
+///
+    void p9_ADU_oper_flag::getFlag(const uint32_t i_flag)
+    {
+        // Decode Operation type
+        iv_operType = static_cast<OperationType_t>
+                      ( (i_flag & FLAG_ADU_TTYPE) >> FLAG_ADU_TTYPE_SHIFT);
+
+        // Auto Inc
+        iv_autoInc = (i_flag & FLAG_AUTOINC);
+
+        // Lock pick
+        iv_lockPick = (i_flag & FLAG_LOCK_PICK);
+
+        // Lock attempts
+        iv_numLockAttempts = ( (i_flag & FLAG_LOCK_TRIES) >> FLAG_LOCK_TRIES_SHIFT);
+
+        // Leave dirty
+        iv_cleanUp = ~(i_flag & FLAG_LEAVE_DIRTY);
+
+        // Fast mode
+        iv_fastMode = (i_flag & FLAG_ADU_FASTMODE);
+
+        // Itag
+        iv_itag = (i_flag & FLAG_ITAG);
+
+        // ECC
+        iv_ecc = (i_flag & FLAG_ECC);
+
+        // Overwrite ECC
+        iv_eccItagOverwrite = (i_flag & FLAG_OVERWRITE_ECC);
+
+        // Transaction size
+        if ( (i_flag & FLAG_SIZE) == FLAG_SIZE_TSIZE_1 )
+        {
+            iv_transSize = TSIZE_1;
+        }
+        else if ( (i_flag & FLAG_SIZE) == FLAG_SIZE_TSIZE_2 )
+        {
+            iv_transSize = TSIZE_2;
+        }
+        else if ( (i_flag & FLAG_SIZE) == FLAG_SIZE_TSIZE_4 )
+        {
+            iv_transSize = TSIZE_4;
+        }
+        else if ( (i_flag & FLAG_SIZE) == FLAG_SIZE_TSIZE_8 )
+        {
+            iv_transSize = TSIZE_8;
+        }
+        else
+        {
+            FAPI_ERR("Invalid transaction size: iv_transSize %d",  iv_transSize);
+        }
+
+        // Debug trace
+        FAPI_DBG("p9_ADU_oper_flag::getFlag() - Flag value 0x%.8X", i_flag);
+        FAPI_DBG("    iv_operType 0x%.8X, iv_autoInc 0x%.8X, iv_lockPick 0x%.8X, iv_numLockAttempts 0x%.8X",
+                 iv_operType, iv_autoInc, iv_lockPick, iv_numLockAttempts);
+        FAPI_DBG("    iv_cleanUp 0x%.8X, iv_fastMode 0x%.8X, iv_itag 0x%.8X, iv_ecc 0x%.8X",
+                 iv_cleanUp, iv_fastMode, iv_itag, iv_ecc);
+        FAPI_DBG("    iv_eccItagOverwrite 0x%.8X, iv_transSize 0x%.8X",
+                 iv_eccItagOverwrite, iv_transSize);
+        return;
+    }
+
+//-----------------------------------------------------------------------------------
+// Function prototypes
+//-----------------------------------------------------------------------------------
+
+/// @brief check that the address is cacheline aligned and within the fabric real address range
+/// @param[in] i_target  => P9 chip target
+/// @param[in] i_address => starting address for ADU operation
+/// @return FAPI_RC_SUCCESS if arguments are valid
+    fapi2::ReturnCode p9_adu_coherent_utils_check_args(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_address,
+        const uint32_t i_flags);
+
+/// @brief ensure that fabric is initialized and stop control is not set
+///           (by checkstop/mode switch), which if set would prohibit fabric
+///           commands from being broadcasted
+/// @param[in] i_target => P9 chip target
+/// @return FAPI_RC_SUCCESS if fabric is not stopped
+    fapi2::ReturnCode p9_adu_coherent_utils_check_fbc_state(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target
+    );
+
+/// @brief calculates the number of 8 byte granules that can be read/written before setup needs to be run again
+/// @param[in] i_target  => P9 chip target
+/// @param[in] i_address => starting address for ADU operation
+/// @return number of 8 byte granules that can be read/written before setup needs to be run again
+    fapi2::ReturnCode p9_adu_coherent_utils_get_num_granules(
+        const uint64_t i_address,
+        uint32_t& o_numGranules);
+
+/// @brief does the setup for the ADU to set up the initial registers for a read/write
+/// @param[in] i_target  => P9 chip target
+/// @param[in] i_address => starting address for ADU operation
+/// @param[in] i_rnw     => whether the operation is a read or write
+/// @param[in] i_flags   => flags that contain information that the ADU needs to know to set up registers
+/// @return FAPI_RC_SUCCESS if setting up the adu registers is a success
+    fapi2::ReturnCode p9_adu_coherent_setup_adu(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_address,
+        const bool i_rnw,
+        const uint32_t i_flags);
+
+/// @brief does the write for the ADU
+/// @param[in] i_target       => P9 chip target
+/// @param[in] i_firstGranule => the first 8B granule that we are writing
+/// @param[in] i_address      => address for this write
+/// @param[in] i_aduOper      => Contains information that the ADU needs to know to set up registers
+/// @param[in] i_write_data   => the data that is to be written to the ADU
+/// @return FAPI_RC_SUCCESS if writing the ADU is a success
+    fapi2::ReturnCode p9_adu_coherent_adu_write(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const bool i_firstGranule,
+        const uint64_t i_address,
+        p9_ADU_oper_flag& i_aduOper,
+        const uint8_t i_write_data[]);
+
+/// @brief does the read for the ADU
+/// @param[in] i_target       => P9 chip target
+/// @param[in] i_firstGranule => the first 8B granule that we are reading
+/// @param[in] i_address      => address for this read
+/// @param[in] i_aduOper      => Contains information that the ADU needs to know to set up registers
+/// @param[out] o_read_data   => the data that is read from the ADU
+/// @return FAPI_RC_SUCCESS if reading the ADU is a success
+    fapi2::ReturnCode p9_adu_coherent_adu_read(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const bool i_firstGranule,
+        const uint64_t i_address,
+        p9_ADU_oper_flag& i_aduOper,
+        uint8_t o_read_data[]);
+
+/// @brief this does a reset for the ADU
+/// @param[in] i_target => P9 chip target
+/// @return FAPI_RC_SUCCESS if the reset is a success
+    fapi2::ReturnCode p9_adu_coherent_utils_reset_adu(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+/// @brief this does any cleanup for the ADU after all reads/writes have been done
+/// @param[in] i_target => P9 chip target
+/// @return FAPI_RC_SUCCESS if cleaning up the ADU is a success
+    fapi2::ReturnCode p9_adu_coherent_cleanup_adu(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+/// @brief this will remove the auto increment bit before the last iteration
+/// @param[in] i_target => P9 chip target
+/// @return FAPI_RC_SUCCESS if removing the auto inc bit is a success
+    fapi2::ReturnCode p9_adu_coherent_clear_autoinc(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+/// @brief This function checks the status of the adu.
+///        If ADU is busy, it will handle
+///
+/// @param[in] i_target            P9 chip target
+/// @param[in] i_busyBitHandler    Instruction on how to handle the ADU busy
+/// @param[in] i_addressOnlyOper   Indicate the check is called after an Address
+///                                only operation
+/// @param[out] o_busyStatus       ADU status busy bit.
+///
+/// @return FAPI_RC_SUCCESS if the status check is a success
+    fapi2::ReturnCode p9_adu_coherent_status_check(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const adu_status_busy_handler i_busyBitHandler,
+        const bool i_addressOnlyOper,
+        bool& o_busyBitStatus);
+
+/// @brief this will acquire and release a lock as well as deal with any lock picking
+/// @param[in] i_target       => P9 chip target
+/// @param[in] i_lock_pick    => If the lock does not go through should we set a lock pick
+/// @param[in] i_lock         => true if this is to lock the ADU false if this is to unlock the ADU
+/// @param[in] i_num_attempts => number of times to try locking the ADU
+    fapi2::ReturnCode p9_adu_coherent_manage_lock(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const bool i_lock_pick,
+        const bool i_lock,
+        const uint32_t i_num_attempts);
+
+} // extern "C"
+
+#endif //_P9_ADU_COHERENT_UTILS_H_
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H
new file mode 100644
index 00000000..d0449e0d
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_constants.H
@@ -0,0 +1,130 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_adu_constants.H $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file p9_adu_constants.H
+/// @brief Constant enums to support ADU get/putmem procedures (FAPI)
+///
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWp Consumed by: SBE
+
+#ifndef _P9_ADU_CONSTANTS_H_
+#define _P9_ADU_CONSTANTS_H_
+
+//---------------------------------------------------------------------------------------------
+// Includes
+//---------------------------------------------------------------------------------------------
+
+extern "C"
+{
+
+//----------------------------------------------------------------------------------------------
+// Constant definitions
+//----------------------------------------------------------------------------------------------
+
+//if the flag is more than 1 bit there will be a start and end bit for the flag
+//these give the bit position that is expected for the flags
+    enum adu_flags
+    {
+        // Operation type
+        // 0b000: DMA partial
+        // 0b001: Cache-inhibited
+        // 0b010: PB op
+        // 0b011: PMISC op
+        FLAG_ADU_TTYPE = 0xE0000000ull,                        // Bits 0:2
+
+        // Utilize ADU HW auto-increment function
+        // 0: Don't use autoinc
+        // 1: Use autoinc
+        FLAG_AUTOINC = 0x10000000ull,                          // Bit 3
+
+        // Pick ADU lock (if required)
+        // 0: Don't use lock pick
+        // 1: Use lock pick
+        FLAG_LOCK_PICK = 0x08000000ull,                        // Bit 4
+
+        // In case of a fail with lock held, reset
+        // ADU and release lock
+        // 0: Reset & release
+        // 1: Leave dirty
+        FLAG_LEAVE_DIRTY = 0x04000000ull,                      // Bit 5
+
+        // Check status only at the end of read/write stream
+        // 0:  Do status check after every read/write
+        // 1:  Don't do status check
+        FLAG_ADU_FASTMODE = 0x02000000ull,                     // Bit 6
+
+        // Collect/set itag with each 8B read/write
+        // For a write only set if itag data should be 1
+        // 0: Don't collect itag
+        // 1: Collect itag
+        FLAG_ITAG = 0x01000000ull,                             // Bit 7
+
+        // Collect/set ecc with each 8B read/write
+        // 0: Don't collect ecc
+        // 1: Collect ecc
+        FLAG_ECC = 0x00800000ull,                              // Bit 8
+
+        // Overwrite the ecc/itag data
+        // 0: Don't overwrite ECC
+        // 1: Overwrite ECC
+        FLAG_OVERWRITE_ECC = 0x00400000ull,                    // Bit 9
+
+        // Transaction size (choice is 1, 2, 4, or 8)
+        // 0b00: TSIZE_1
+        // 0b01: TSIZE_2
+        // 0b10: TSIZE_4
+        // 0b11: TSIZE_8
+        FLAG_SIZE = 0x00300000ull,                             // Bits 10:11
+
+        // Number of ADU lock acquisitions to attempt
+        // before giving up or attempting lock pick
+        FLAG_LOCK_TRIES       = 0x000F0000,                    // Bit 12:15
+
+        // Reserved bits
+        FLAG_NOT_USED_BITS    = 0x0000FFFF,                    // Bit 16:31
+    };
+
+// Operation type values
+    const uint32_t FLAG_ADU_TTYPE_DMA   = 0x00000000ull;   // DMA partial
+    const uint32_t FLAG_ADU_TTYPE_CI    = 0x20000000ull;   // Cache inhibit
+    const uint32_t FLAG_ADU_TTYPE_PB    = 0x40000000ull;   // PB operation
+    const uint32_t FLAG_ADU_TTYPE_PMISC = 0x60000000ull;   // Switch operation
+
+// Flag size values
+    const uint32_t FLAG_SIZE_TSIZE_1   = 0x00000000ull;
+    const uint32_t FLAG_SIZE_TSIZE_2   = 0x00100000ull;
+    const uint32_t FLAG_SIZE_TSIZE_4   = 0x00200000ull;
+    const uint32_t FLAG_SIZE_TSIZE_8   = 0x00300000ull;
+
+// Shift positions
+    const uint64_t FLAG_ADU_TTYPE_SHIFT  = 29;
+    const uint64_t FLAG_LOCK_TRIES_SHIFT = 16;
+    const uint64_t FLAG_ADU_SIZE_SHIFT  = 20;
+
+} //extern "C"
+
+#endif //_P9_ADU_CONSTANTS_H_
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.C
new file mode 100644
index 00000000..e270772a
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.C
@@ -0,0 +1,112 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_adu_setup.C $          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//--------------------------------------------------------------------------
+//
+/// @file p9_adu_setup.C
+/// @brief Setup the registers for a read/write to the ADU
+//
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+//
+//--------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------
+// Includes
+//--------------------------------------------------------------------------
+#include <p9_adu_setup.H>
+#include <p9_adu_coherent_utils.H>
+
+extern "C"
+{
+
+//--------------------------------------------------------------------------
+//  HWP entry point
+//--------------------------------------------------------------------------
+    fapi2::ReturnCode p9_adu_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>
+                                   & i_target,
+                                   const uint64_t i_address,
+                                   const bool i_rnw,
+                                   const uint32_t i_flags,
+                                   uint32_t& o_numGranules)
+    {
+        //return code
+        uint32_t num_attempts = 1;
+        bool lock_pick = false;
+
+        // mark HWP entry
+        FAPI_DBG("Entering ...\n");
+
+        //ADU status/control information
+        bool adu_is_dirty = false;
+        bool adu_leave_dirty = i_flags & FLAG_LEAVE_DIRTY;
+
+        //check arguments
+        FAPI_TRY(p9_adu_coherent_utils_check_args(i_target, i_address, i_flags),
+                 "Error from p9_adu_coherent_utils_check_args");
+
+        //ensure fabric is running
+        FAPI_TRY(p9_adu_coherent_utils_check_fbc_state(i_target),
+                 "Error from p9_adu_coherent_utils_check_fbc_status");
+
+        //reset ADU state machines and status register
+        FAPI_TRY(p9_adu_coherent_utils_reset_adu(i_target), "p9_adu_setup: Error from p9_adu_coherent_utils_reset_adu");
+
+        //acquire ADU lock to guarantee exclusive use of the ADU resources
+        lock_pick = i_flags & FLAG_LOCK_PICK;
+        num_attempts = i_flags & FLAG_LOCK_TRIES;
+        FAPI_TRY(p9_adu_coherent_manage_lock(i_target, lock_pick, true, num_attempts),
+                 "Error from p9_adu_coherent_manage_lock");
+
+        //figure out how many granules can be requested before setup needs to be run again
+        FAPI_TRY(p9_adu_coherent_utils_get_num_granules(i_address, o_numGranules),
+                 "Error from p9_adu_coherent_utils_get_num_granules");
+
+        //Set dirty since we need to attempt to cleanup/release the lock so the ADU is not in a locked state if operation fails from this point
+        adu_is_dirty = true;
+
+        //setup the ADU registers for the read/write
+        FAPI_TRY(p9_adu_coherent_setup_adu(i_target, i_address, i_rnw, i_flags),
+                 "Error from p9_adu_coherent_setup_registers");
+
+    fapi_try_exit:
+        fapi2::ReturnCode saveError = fapi2::current_err;
+
+        //if an error has occurred, ADU is dirty, and instructed to clean up,
+        //attempt to reset ADU and free lock (propogate rc of original fail)
+        if (fapi2::current_err && adu_is_dirty && !adu_leave_dirty)
+        {
+            (void) p9_adu_coherent_utils_reset_adu(i_target);
+            (void) p9_adu_coherent_manage_lock(i_target, false, false, num_attempts);
+        }
+
+        FAPI_DBG("Exiting...");
+        return saveError;
+    }
+
+} // extern "C"
+
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.H b/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.H
new file mode 100644
index 00000000..ffdd38b0
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_adu_setup.H
@@ -0,0 +1,99 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_adu_setup.H $          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------------
+//
+/// @file p9_adu_setup.H
+/// @brief Setup the adu to do reads/writes
+//
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 1
+// *HWP Consumed by:
+//-----------------------------------------------------------------------------------
+// *! ADDITIONAL COMMENTS:
+// *!
+// *! The purpose of this procedure is to setup the ADU to do reads/writes
+// *! and to return the number of granules (number of 8B reads/writes) that
+// *! can be done before setup needs to be called again
+// *!
+// *! Successful operation assumes that:
+// *!
+// *! High-level procedure flow:
+// *!
+// *!
+//------------------------------------------------------------------------------------
+
+#ifndef _P9_ADU_SETUP_H_
+#define _P9_ADU_SETUP_H_
+
+//-----------------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------------
+
+#include <fapi2.H>
+#include <p9_adu_constants.H>
+
+//-----------------------------------------------------------------------------------
+// Structure definitions
+//-----------------------------------------------------------------------------------
+
+//function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode
+(*p9_adu_setup_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
+                      const uint64_t,
+                      const bool,
+                      const uint32_t,
+                      uint32_t&);
+
+//-----------------------------------------------------------------------------------
+// Constant definitions
+//-----------------------------------------------------------------------------------
+
+extern "C" {
+
+//-----------------------------------------------------------------------------------
+// Function prototype
+//-----------------------------------------------------------------------------------
+
+/// @brief setup for reads/writes from the ADU
+/// @param[in] i_target       => P9 chip target
+/// @param[in] i_address      => base real address for read/write operation (expected to be 8B aligned)
+/// @param[in] i_rnw          => if the operation is read not write (1 for read, 0 for write)
+/// @param[in] i_flags        => other information that is needed - see the p9_adu_constants adu_flags enums for bit definitions
+///                              Note: To construct the flag you can use p9_ADU_oper_flag class
+/// @param[out] o_numGranules  => number of 8B granules that can be read/written before setup needs to be called again
+//
+/// @return FAPI_RC_SUCCESS if the setup completes successfully,
+//
+    fapi2::ReturnCode p9_adu_setup(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_address,
+        const bool i_rnw,
+        const uint32_t i_flags,
+        uint32_t& o_numGranules);
+} //extern "C"
+
+#endif //_P9_ADU_SETUP_H_
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C
new file mode 100644
index 00000000..4c9e3a12
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C
@@ -0,0 +1,264 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C $          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_fbc_utils.C
+/// @brief Fabric library functions/constants (FAPI2)
+///
+/// The functions in this file provide:
+/// - Information about the instantaneous state of the fabric
+/// - Means to restart the fabric after a checkstop condition
+/// - Determination of the chip's base address in the real address map
+///
+/// @author Joe McGill <jmcgill@us.ibm.com>
+/// @author Christy Graves <clgraves@us.ibm.com>
+///
+
+//
+// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE,HB,FSP
+//
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <p9_fbc_utils.H>
+#include <p9_misc_scom_addresses.H>
+
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+// ADU PMisc Register field/bit definitions
+const uint32_t ALTD_SND_MODE_DISABLE_CHECKSTOP_BIT = 19;
+const uint32_t ALTD_SND_MODE_MANUAL_CLR_PB_STOP_BIT = 21;
+const uint32_t ALTD_SND_MODE_PB_STOP_BIT = 22;
+
+// FBC Mode Register field/bit definitions
+const uint32_t PU_FBC_MODE_PB_INITIALIZED_BIT = 0;
+
+// FBC base address determination constants
+// system ID (large system)
+const uint8_t FABRIC_ADDR_LS_SYSTEM_ID_START_BIT = 8;
+const uint8_t FABRIC_ADDR_LS_SYSTEM_ID_END_BIT = 12;
+// system ID (small system)
+const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD0_START_BIT = 8;
+const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD0_END_BIT = 12;
+const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD0_SHIFT = 5;
+const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD0_MASK = 0x1F;
+const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD1_START_BIT = 15;
+const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD1_END_BIT = 16;
+const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD1_SHIFT = 3;
+const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD1_MASK = 0x3;
+const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD2_START_BIT = 19;
+const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD2_END_BIT = 21;
+const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD2_SHIFT = 0;
+const uint8_t FABRIC_ADDR_SS_SYSTEM_ID_FLD2_MASK = 0x7;
+// group ID (large system)
+const uint8_t FABRIC_ADDR_LS_GROUP_ID_START_BIT = 15;
+const uint8_t FABRIC_ADDR_LS_GROUP_ID_END_BIT = 18;
+// group ID (small system)
+const uint8_t FABRIC_ADDR_SS_GROUP_ID_START_BIT = 17;
+const uint8_t FABRIC_ADDR_SS_GROUP_ID_END_BIT = 18;
+// chip ID (large system)
+const uint8_t FABRIC_ADDR_LS_CHIP_ID_START_BIT = 19;
+const uint8_t FABRIC_ADDR_LS_CHIP_ID_END_BIT = 21;
+// msel bits (large & small system)
+const uint8_t FABRIC_ADDR_MSEL_START_BIT = 13;
+const uint8_t FABRIC_ADDR_MSEL_END_BIT = 14;
+
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+fapi2::ReturnCode p9_fbc_utils_get_fbc_state(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    bool& o_is_initialized,
+    bool& o_is_running)
+{
+    FAPI_DBG("Start");
+
+    // TODO: HW328175
+    // fapi2::buffer<uint64_t> l_fbc_mode_data;
+    // FAPI_TRY(fapi2::getScom(i_target, PU_FBC_MODE_REG, l_fbc_mode_data),
+    //          "Error reading FBC Mode Register");
+    // // fabric is initialized if PB_INITIALIZED bit is one/set
+    // o_is_initialized = l_fbc_mode_data.getBit<PU_FBC_MODE_PB_INITIALIZED_BIT>();
+
+    // currently, sampling FBC init from PB Mode register is unreliable
+    // as init can drop perodically at runtime (based on legacy sleep backoff)
+    // until this issue is fixed, just return true to caller
+    o_is_initialized = true;
+
+    // read ADU PMisc Mode Register state
+    fapi2::buffer<uint64_t> l_pmisc_mode_data;
+    FAPI_TRY(fapi2::getScom(i_target, PU_SND_MODE_REG, l_pmisc_mode_data),
+             "Error reading ADU PMisc Mode register");
+
+    // fabric is running if FBC_STOP bit is zero/clear
+    o_is_running = !(l_pmisc_mode_data.getBit<ALTD_SND_MODE_PB_STOP_BIT>());
+
+fapi_try_exit:
+    FAPI_DBG("End");
+    return fapi2::current_err;
+}
+
+
+fapi2::ReturnCode p9_fbc_utils_override_fbc_stop(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+    FAPI_DBG("Start");
+
+    // read ADU PMisc Mode Register state
+    fapi2::buffer<uint64_t> l_pmisc_mode_data;
+    FAPI_TRY(fapi2::getScom(i_target, PU_SND_MODE_REG, l_pmisc_mode_data),
+             "Error reading ADU PMisc Mode register");
+
+    // set bit to disable checkstop forwarding and write back
+    l_pmisc_mode_data.setBit<ALTD_SND_MODE_DISABLE_CHECKSTOP_BIT>();
+    FAPI_TRY(fapi2::putScom(i_target, PU_SND_MODE_REG, l_pmisc_mode_data),
+             "Error writing ADU PMisc Mode register to disable checkstop forwarding to FBC");
+
+    // set bit to manually clear stop control and write back
+    l_pmisc_mode_data.setBit<ALTD_SND_MODE_MANUAL_CLR_PB_STOP_BIT>();
+    FAPI_TRY(fapi2::putScom(i_target, PU_SND_MODE_REG, l_pmisc_mode_data),
+             "Error writing ADU PMisc Mode register to manually clear FBC stop control");
+
+fapi_try_exit:
+    FAPI_DBG("End");
+    return fapi2::current_err;
+}
+
+
+fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    uint64_t& o_base_address_nm0,
+    uint64_t& o_base_address_nm1,
+    uint64_t& o_base_address_m,
+    uint64_t& o_base_address_mmio)
+{
+    uint32_t l_fabric_system_id;
+    uint8_t l_fabric_group_id;
+    uint8_t l_fabric_chip_id;
+    uint8_t l_fabric_addr_bar_mode;
+    uint8_t l_mirror_policy;
+    fapi2::buffer<uint64_t> l_base_address;
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+
+
+    FAPI_DBG("Start");
+
+    // retreive attributes which statically determine chip's position in memory map
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, i_target, l_fabric_system_id),
+             "Error from FAPI_ATTR_GET (ATTR_FABRIC_SYSTEM_ID)");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target, l_fabric_group_id),
+             "Error from FAPI_ATTR_GET (ATTR_FABRIC_GROUP_ID)");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target, l_fabric_chip_id),
+             "Error from FAPI_ATTR_GET (ATTR_FABRIC_CHIP_ID)");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_ADDR_BAR_MODE, FAPI_SYSTEM, l_fabric_addr_bar_mode),
+             "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_ADDR_BAR_MODE)");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY, FAPI_SYSTEM, l_mirror_policy),
+             "Error from FAPI_ATTR_GET (ATTR_MEM_MIRROR_PLACEMENT_POLICY)");
+
+    // apply system ID
+    // occupies one field for large system map, split into three fields for small system map
+    if (l_fabric_addr_bar_mode == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_LARGE_SYSTEM)
+    {
+        l_base_address.insertFromRight < FABRIC_ADDR_LS_SYSTEM_ID_START_BIT,
+                                       (FABRIC_ADDR_LS_SYSTEM_ID_END_BIT - FABRIC_ADDR_LS_SYSTEM_ID_START_BIT + 1) > (l_fabric_system_id);
+    }
+    else
+    {
+        uint32_t l_fabric_system_id_fld = (l_fabric_system_id >> FABRIC_ADDR_SS_SYSTEM_ID_FLD0_SHIFT) &
+                                          FABRIC_ADDR_SS_SYSTEM_ID_FLD0_MASK;
+        l_base_address.insertFromRight < FABRIC_ADDR_SS_SYSTEM_ID_FLD0_START_BIT,
+                                       (FABRIC_ADDR_SS_SYSTEM_ID_FLD0_END_BIT - FABRIC_ADDR_SS_SYSTEM_ID_FLD0_START_BIT + 1) > (l_fabric_system_id_fld);
+
+        l_fabric_system_id_fld = (l_fabric_system_id >> FABRIC_ADDR_SS_SYSTEM_ID_FLD1_SHIFT) &
+                                 FABRIC_ADDR_SS_SYSTEM_ID_FLD1_MASK;
+        l_base_address.insertFromRight < FABRIC_ADDR_SS_SYSTEM_ID_FLD1_START_BIT,
+                                       (FABRIC_ADDR_SS_SYSTEM_ID_FLD1_END_BIT - FABRIC_ADDR_SS_SYSTEM_ID_FLD1_START_BIT + 1) > (l_fabric_system_id_fld);
+
+        l_fabric_system_id_fld = (l_fabric_system_id >> FABRIC_ADDR_SS_SYSTEM_ID_FLD2_SHIFT) &
+                                 FABRIC_ADDR_SS_SYSTEM_ID_FLD2_MASK;
+        l_base_address.insertFromRight < FABRIC_ADDR_SS_SYSTEM_ID_FLD2_START_BIT,
+                                       (FABRIC_ADDR_SS_SYSTEM_ID_FLD2_END_BIT - FABRIC_ADDR_SS_SYSTEM_ID_FLD2_START_BIT + 1) > (l_fabric_system_id_fld);
+    }
+
+    // apply group ID
+    if (l_fabric_addr_bar_mode == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_LARGE_SYSTEM)
+    {
+        l_base_address.insertFromRight < FABRIC_ADDR_LS_GROUP_ID_START_BIT,
+                                       (FABRIC_ADDR_LS_GROUP_ID_END_BIT - FABRIC_ADDR_LS_GROUP_ID_START_BIT + 1) > (l_fabric_group_id);
+    }
+    else
+    {
+        l_base_address.insertFromRight < FABRIC_ADDR_SS_GROUP_ID_START_BIT,
+                                       (FABRIC_ADDR_SS_GROUP_ID_END_BIT - FABRIC_ADDR_SS_GROUP_ID_START_BIT + 1) > (l_fabric_group_id);
+    }
+
+    // apply chip ID (relevant for large system map only)
+    if (l_fabric_addr_bar_mode == fapi2::ENUM_ATTR_PROC_FABRIC_ADDR_BAR_MODE_LARGE_SYSTEM)
+    {
+        l_base_address.insertFromRight < FABRIC_ADDR_LS_CHIP_ID_START_BIT,
+                                       (FABRIC_ADDR_LS_CHIP_ID_END_BIT - FABRIC_ADDR_LS_CHIP_ID_START_BIT + 1) > (l_fabric_chip_id);
+    }
+
+    // set output addresses based on application of msel
+    if (l_mirror_policy == fapi2::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL)
+    {
+        // nm = 0b00/01, m = 0b10, mmio = 0b11
+        o_base_address_nm0 = l_base_address();               // 00
+        l_base_address.setBit<FABRIC_ADDR_MSEL_END_BIT>();
+        o_base_address_nm1 = l_base_address();               // 01
+        l_base_address.setBit<FABRIC_ADDR_MSEL_START_BIT>();
+        l_base_address.clearBit<FABRIC_ADDR_MSEL_END_BIT>();
+        o_base_address_m = l_base_address();                 // 10
+        l_base_address.setBit(FABRIC_ADDR_MSEL_END_BIT);
+        o_base_address_mmio = l_base_address();              // 11
+    }
+    else
+    {
+        // nm = 0b01/10, m = 0b00, mmio = 0b11
+        o_base_address_m = l_base_address();                 // 00
+        l_base_address.setBit<FABRIC_ADDR_MSEL_END_BIT>();
+        o_base_address_nm0 = l_base_address();               // 01
+        l_base_address.setBit<FABRIC_ADDR_MSEL_START_BIT>();
+        l_base_address.clearBit<FABRIC_ADDR_MSEL_END_BIT>();
+        o_base_address_nm1 = l_base_address();               // 10
+        l_base_address.setBit<FABRIC_ADDR_MSEL_END_BIT>();
+        o_base_address_mmio = l_base_address();              // 11
+    }
+
+fapi_try_exit:
+    FAPI_DBG("End");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
new file mode 100644
index 00000000..af73102e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H
@@ -0,0 +1,108 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H $          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_fbc_utils.H
+/// @brief Fabric library functions/constants (FAPI2)
+///
+/// @author Joe McGill <jmcgill@us.ibm.com>
+/// @author Christy Graves <clgraves@us.ibm.com>
+///
+
+//
+// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE,HB,FSP
+//
+
+#ifndef _P9_FBC_UTILS_H_
+#define _P9_FBC_UTILS_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi2.H>
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+// address range definitions
+const uint64_t P9_FBC_UTILS_FBC_MAX_ADDRESS = ((1ULL << 56) - 1ULL);
+const uint64_t P9_FBC_UTILS_CACHELINE_MASK = 0x7FULL;
+const uint64_t P9_FBC_UTILS_LAST_ADDR_IN_CACHELINE = 0x78ULL;
+
+// cacheline size = 128B
+const uint64_t FABRIC_CACHELINE_SIZE = 0x80;
+
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+///
+/// @brief Read FBC/ADU registers to determine state of fabric init and stop
+/// control signals
+///
+/// @param[in] i_target           Reference to processor chip target
+/// @param[out] o_is_initialized  State of fabric init signal
+/// @param[out] o_is_running      State of fabric pervasive stop control
+/// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode p9_fbc_utils_get_fbc_state(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    bool& o_is_initialized,
+    bool& o_is_running);
+
+///
+/// @brief Use ADU pMisc Mode register to clear fabric stop signal, overriding
+/// a stop condition caused by a checkstop
+///
+/// @param[in] i_target            Reference to processor chip target
+/// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode p9_fbc_utils_override_fbc_stop(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+///
+/// @brief Return base address origin (non-mirrored/mirrored/MMIO) for this chip
+///
+/// @param[in] i_target Reference to processor chip target
+/// @param[out] o_base_address_nm0 Non-mirrored base address (range 0) for this chip
+/// @param[out] o_base_address_nm1 Non-mirrored base address (range 1) for this chip
+/// @param[out] o_base_address_m Mirrored base address for this chip
+/// @param[out] o_base_address_mmio MMIO base address for this chip
+/// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode p9_fbc_utils_get_chip_base_address(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    uint64_t& o_base_address_nm0,
+    uint64_t& o_base_address_nm1,
+    uint64_t& o_base_address_m,
+    uint64_t& o_base_address_mmio);
+
+
+#endif // _P9_FBC_UTILS_H_
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.C b/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.C
new file mode 100644
index 00000000..5a3970b3
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.C
@@ -0,0 +1,117 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_pba_access.C $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//--------------------------------------------------------------------------
+//
+/// @file p9_pba_access.C
+/// @brief Read coherent state of memory via the PBA (FAPI)
+///
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+//--------------------------------------------------------------------------
+
+
+//--------------------------------------------------------------------------
+// Includes
+//--------------------------------------------------------------------------
+#include <p9_pba_setup.H>
+#include <p9_pba_coherent_utils.H>
+
+extern "C" {
+
+//--------------------------------------------------------------------------
+//  HWP entry point
+//--------------------------------------------------------------------------
+    fapi2::ReturnCode p9_pba_access(const
+                                    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+                                    const uint64_t i_address,
+                                    const bool i_rnw,
+                                    const uint32_t i_flags,
+                                    const bool i_firstGranule,
+                                    const bool i_lastGranule,
+                                    uint8_t io_data[])
+    {
+        //return codes
+        fapi2::ReturnCode rc;
+        fapi2::ReturnCode rc1;
+
+        // mark HWP entry
+        FAPI_DBG("Entering ...\n");
+
+        // Process input flag
+        p9_PBA_oper_flag l_myPbaFlag;
+        l_myPbaFlag.getFlag(i_flags);
+
+        //if read
+        if (i_rnw)
+        {
+            rc1 = p9_pba_coherent_pba_read(i_target, i_address, io_data);
+        }
+        //else if write
+        else
+        {
+            rc1 = p9_pba_coherent_pba_write(i_target, i_address, io_data);
+        }
+
+        //If we are not in fastmode or this is the last granule, we want to check the status
+        if (!rc1)
+        {
+            if ( i_lastGranule || (l_myPbaFlag.getFastMode() == false) )
+            {
+                rc1 = p9_pba_coherent_status_check(i_target);
+
+                if (i_lastGranule)
+                {
+                    //Clean up the PBA since it's the last read/write and it has been finished
+                    FAPI_TRY(p9_pba_coherent_cleanup_pba(i_target),
+                             "Error doing p9_pba_coherent_cleanup_pba");
+                }
+            }
+        }
+
+        // mark HWP exit
+    fapi_try_exit:
+
+        //Handling error. PBA access is the main error if there's one.
+        if (rc1)
+        {
+            //Commit error from clean up (secondary)
+            if (rc)
+            {
+                //fapi2::fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED);
+            }
+
+            //Set return error to pba access error
+            fapi2::current_err = rc1;
+        }
+
+        FAPI_DBG("Exit ...\n");
+        return fapi2::current_err;
+    }
+
+} // extern "C"
+
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.H b/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.H
new file mode 100644
index 00000000..7e02c926
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.H
@@ -0,0 +1,104 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_pba_access.H $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------------
+//
+/// @file p9_pba_access.H
+/// @brief Read coherent state of memory via the PBA (FAPI)
+///
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+// ----------------------------------------------------------------------------------
+//
+// *! ADDITIONAL COMMENTS :
+// *!
+// *! The purpose of this procedure is to perform a coherent read or write from system
+// *! memory via fabric commands issued from the PBA.
+// *!
+// *! Succcessful operation assumes that:
+// *!   o System clocks are running
+// *!   o Fabric is initalized
+// *!
+// *!
+//-----------------------------------------------------------------------------------
+
+#ifndef _P9_PBA_ACCESS_H_
+#define _P9_PBA_ACCESS_H_
+
+//-----------------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------------
+
+#include <fapi2.H>
+#include <p9_pba_constants.H>
+//-----------------------------------------------------------------------------------
+// Structure definitions
+//-----------------------------------------------------------------------------------
+
+//function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode
+(*p9_pba_access_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
+                       const uint64_t,
+                       const bool,
+                       const uint32_t,
+                       const bool,
+                       const bool,
+                       uint8_t[]);
+
+//-----------------------------------------------------------------------------------
+// Constant definitions
+//-----------------------------------------------------------------------------------
+
+extern "C" {
+
+//-----------------------------------------------------------------------------------
+// Function prototype
+//-----------------------------------------------------------------------------------
+
+/// @brief setup for reads/writes from the PBA
+/// @param[in]  i_target       => P9 chip target
+/// @param[in]  i_address      => base real address for read/write operation (expected to be 128B aligned)
+/// @param[in]  i_rnw          => if the operation is read not write (1 for read, 0 for write)
+/// @param[in]  i_flags        => other information that is needed - see the p9_pba_constants pba_flags enums for bit definitions
+///                               Note: to construct the flag you can use the p9_PBA_oper_flag class
+/// @param[in]  i_lastGranule  => is this the last granule that is to be read/written
+/// @param[in]  i_firstGranule => first granule that is to be read/written NOT USED FOR PBA
+/// @param[in, out] io_data    => The data that is read/written
+/// @return FAPI_RC_SUCCESS if the setup completes successfully,
+
+    fapi2::ReturnCode p9_pba_access(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_address,
+        const bool i_rnw,
+        const uint32_t i_flags,
+        const bool i_firstGranule,
+        const bool i_lastGranule,
+        uint8_t io_data[]);
+} //extern "C"
+
+#endif //_P9_PBA_ACCESS_H_
+
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C
new file mode 100644
index 00000000..c4f32d8c
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C
@@ -0,0 +1,491 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------------
+//
+/// @file p9_pba_coherent_utils.C
+/// @brief PBA alter/display library functions (FAPI)
+///
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+//
+//-----------------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------------
+#include <p9_pba_coherent_utils.H>
+#include <p9_misc_scom_addresses.H>
+#include <p9_quad_scom_addresses.H>
+#include <p9_fbc_utils.H>
+
+extern "C"
+{
+    //---------------------------------------------------------------------------------
+    // Constant definitions
+    //---------------------------------------------------------------------------------
+
+    //PBA Delay Constants
+    const uint32_t PBA_SLVRST_DELAY_HW_NS = 1000;
+    const uint32_t PBA_SLVRST_DELAY_SIM_CYCLES = 200;
+    const uint32_t WRITE_DELAY_HW_NS = 100;
+    const uint32_t WRITE_DELAY_SIM_CYCLES = 20;
+    const uint32_t PBA_BAR_SCOPE_LOCAL_NODE = 0;
+
+//PBA Slave Control register field/bit definitions
+    const uint32_t PBA_SLVCTL_ENABLE_BIT = 0;
+    const uint32_t PBA_SLVCTL_MASTER_ID_MATCH_START_BIT = 1;
+    const uint32_t PBA_SLVCTL_MASTER_ID_MATCH_END_BIT = 3;
+    const uint32_t PBA_SLVCTL_MASTER_ID_CARE_MASK_START_BIT = 5;
+    const uint32_t PBA_SLVCTL_MASTER_ID_CARE_MASK_END_BIT = 7;
+    const uint32_t PBA_SLVCTL_WRITE_TTYPE_START_BIT = 8;
+    const uint32_t PBA_SLVCTL_WRITE_TTYPE_END_BIT = 10;
+    const uint32_t PBA_SLVCTL_READ_TTYPE_BIT = 15;
+    const uint32_t PBA_SLVCTL_READ_PREFETCH_CTL_START_BIT = 16;
+    const uint32_t PBA_SLVCTL_READ_PREFETCH_CTL_END_BIT = 17;
+    const uint32_t PBA_SLVCTL_READ_BUF_INVALIDATE_CTL_BIT = 18;
+    const uint32_t PBA_SLVCTL_WRITE_BUF_PAIR_ALLOCATION_BIT = 19;
+    const uint32_t PBA_SLVCTL_READ_BUF_PAIR_A_ALLOCATION_BIT = 20;
+    const uint32_t PBA_SLVCTL_READ_BUF_PAIR_B_ALLOCATION_BIT = 21;
+    const uint32_t PBA_SLVCTL_READ_BUF_PAIR_C_ALLOCATION_BIT = 22;
+    const uint32_t PBA_SLVCTL_DISABLE_WRITE_GATHER_BIT = 24;
+    const uint32_t PBA_SLVCTL_WRITE_GATHER_TIMEOUT_START_BIT = 25;
+    const uint32_t PBA_SLVCTL_WRITE_GATHER_TIMEOUT_END_BIT = 27;
+    const uint32_t PBA_SLVCTL_WRITE_TSIZE_START_BIT = 28;
+    const uint32_t PBA_SLVCTL_WRITE_TSIZE_END_BIT = 35;
+    const uint32_t PBA_SLVCTL_EXT_ADDR_START_BIT = 36;
+    const uint32_t PBA_SLVCTL_EXT_ADDR_END_BIT = 49;
+
+    const uint32_t PBA_SLVCTL_EXTADDR_SHIFT = 27;
+    const uint32_t PBA_SLVCTL_EXTADDR_MASK = 0x3fff;
+
+//PBA Slave Reset register field/bit definitions
+    const uint32_t PBA_SLVRST_SET_START_BIT = 0;
+    const uint32_t PBA_SLVRST_SET_END_BIT = 2;
+    const uint32_t PBA_SLVRST_SLVCTL0_IN_PROG = 4;
+    const uint32_t PBA_SLVRST_SLVCTL1_IN_PROG = 5;
+    const uint32_t PBA_SLVRST_SLVCTL2_IN_PROG = 6;
+    const uint32_t PBA_SLVRST_SLVCTL3_IN_PROG = 7;
+    const uint32_t PBA_SLVRST_IN_PROG_START_BIT = 4;
+    const uint32_t PBA_SLVRST_IN_PROG_END_BIT = 7;
+    const uint32_t PBA_SLVRST_BUSY_START_BIT = 8;
+    const uint32_t PBA_SLVRST_BUSY_END_BIT = 11;
+    //mask to check if there is a PBA slave rest in progress and if the PBA Slave Control is busy
+    //if it is not all these bits 4:11 should be set to 0
+    const uint64_t PBA_SLVRST_BUSY_IN_PROG_MASK = 0xFF0000000000000ull;
+
+//PBA Read Buffer Valid Status field/bit definitions
+    const uint32_t PBA_RD_BUF_VALID_START_BIT = 33;
+    const uint32_t PBA_RD_BUF_VALID_END_BIT = 39;
+    const uint64_t PBA_RD_BUF_VALID_MASK = 0x7F000000ull;
+    const uint64_t PBA_RD_BUF_EMPTY =  0x1000000ull;
+    const uint64_t PBA_RD_BUF_VALID =  0x4000000ull;
+    const uint64_t PBA_RD_BUF_VALIDWFP = 0x8000000ull;
+
+//PBA Write Buffer Valid Status field/bit definitions
+    const uint32_t PBA_WR_BUF_VALID_START_BIT = 35;
+    const uint32_t PBA_WR_BUF_VALID_END_BIT = 39;
+    const uint64_t PBA_WR_BUF_VALID_MASK = 0x1F000000ull;
+    const uint64_t PBA_WR_BUF_EMPTY = 0x1000000ull;
+
+//PBA BAR register field/bit definitions
+    const uint32_t PBA_BAR_SCOPE_START_BIT = 0;
+    const uint32_t PBA_BAR_SCOPE_END_BIT = 2;
+    const uint32_t PBA_BAR_BASE_ADDRESS_START_BIT = 8;
+    const uint32_t PBA_BAR_BASE_ADDRESS_END_BIT = 43;
+    const uint32_t PBA_BAR_BASE_ADDRESS_SHIFT = 20;
+    const uint64_t PBA_BAR_BASE_ADDRESS_MASK = 0xFFFFFFFFFull;
+
+//PBA BAR Mask register field/bit definitions
+    const uint32_t PBA_BAR_MASK_START_BIT = 23;
+    const uint32_t PBA_BAR_MASK_END_BIT = 43;
+
+//OCB3_ADDRESS field/bit definitions
+    const uint32_t OCB3_ADDRESS_REG_ADDR_SHIFT = 32;
+
+    //---------------------------------------------------------------------------------
+    // Function definitions
+    //---------------------------------------------------------------------------------
+
+    fapi2::ReturnCode p9_pba_coherent_utils_check_args(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_address)
+    {
+
+        FAPI_DBG("Start");
+
+        //Check the address alignment
+        FAPI_ASSERT(!(i_address & P9_FBC_UTILS_CACHELINE_MASK),
+                    fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS(
+                        i_address),
+                    "Address is not cacheline aligned");
+
+        //Make sure the address is within the PBA bounds
+        FAPI_ASSERT(i_address <= P9_FBC_UTILS_FBC_MAX_ADDRESS,
+                    fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS(
+                        i_address),
+                    "Address exceeds supported fabric real address range");
+
+    fapi_try_exit:
+        FAPI_DBG("End");
+        return fapi2::current_err;
+    }
+
+    fapi2::ReturnCode p9_pba_coherent_utils_check_fbc_state(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+    {
+        bool fbc_initialized = false;
+        bool fbc_running = false;
+        FAPI_DBG("Start");
+
+        //Make sure the fabric is initialized and running
+        FAPI_TRY(p9_fbc_utils_get_fbc_state(i_target, fbc_initialized, fbc_running),
+                 "Error from p9_fbc_utils_get_fbc_state");
+        FAPI_ASSERT(fbc_initialized
+                    && fbc_running, fapi2::P9_PBA_FBC_NOT_INITIALIZED_ERR().set_TARGET(i_target).set_INITIALIZED(
+                        fbc_initialized).set_RUNNING(
+                        fbc_running), "Fabric is not initialized or running");
+
+    fapi_try_exit:
+        FAPI_DBG("End");
+        return fapi2::current_err;
+    }
+
+    fapi2::ReturnCode p9_pba_coherent_utils_get_num_granules(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_address,
+        uint32_t& o_numGranules)
+    {
+        uint64_t oci_address_mask;
+        uint64_t maximumAddress;
+        //First set up the pba_bar_mask
+        fapi2::buffer<uint64_t> pba_bar_mask_data;
+        //Set the PBA BAR mask to allow as much of the OCI address to pass through directly as possible
+        //by setting bits 23:43 to 0b1.
+        uint64_t pba_bar_mask_attr = 0x1FFFFF00000ull;
+
+        FAPI_DBG("Start");
+
+        pba_bar_mask_data.insertFromRight<0, 64>(pba_bar_mask_attr);
+
+        //write the PBA Bar Mask Register
+        FAPI_TRY(fapi2::putScom(i_target, PU_PBABARMSK3, pba_bar_mask_data),
+                 "Error writing to the PBA Bar Mask Attribute");
+
+
+        //maximum size before we need to rerun setup - this is the number if the PBA Bar Mask is set with bits 23:43 to 0b1
+        maximumAddress = 0x8000000ull;
+        //mask to mask away bits 37:63 of the input address
+        oci_address_mask = 0x7FFFFFFull;
+
+        //subtract the oci part of the address from this maximum number and divide by 8 to get the number of bytes
+        //then divide by 128 to get the number of 128 bye granules that can be sent
+        o_numGranules = ((maximumAddress - (i_address & oci_address_mask)) / 8) / 128;
+        FAPI_DBG("o_numGranules = %016x", o_numGranules);
+
+    fapi_try_exit:
+        FAPI_DBG("End");
+        return fapi2::current_err;
+    }
+
+    fapi2::ReturnCode p9_pba_coherent_setup_pba(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_ex_target,
+        const uint64_t i_address,
+        const bool i_rnw,
+        const uint32_t i_flags)
+    {
+        uint32_t extaddr;
+        uint64_t ocb3_addr_data;
+        uint64_t chiplet_number = 0x0ull;
+        fapi2::buffer<uint64_t> ocb_status_ctl_data;
+        fapi2::buffer<uint64_t> ocb3_addr;
+        fapi2::buffer<uint64_t> pba_slave_ctl_data;
+        fapi2::buffer<uint64_t> l3_mode_reg1;
+
+        p9_PBA_oper_flag l_myPbaFlag;
+        p9_PBA_oper_flag::OperationType_t l_operType;
+
+        FAPI_DBG("Start");
+
+        // Process input flag
+        l_myPbaFlag.getFlag(i_flags);
+        l_operType = l_myPbaFlag.getOperationType();
+
+        //Write the OCB3 Status Control Register
+        //Configure linear stream mode (auto-increment +8 with each data register read/write)
+        //set bit 4 and unset bit 5 of OCB3 Status Control Register
+        ocb_status_ctl_data.flush<0>().setBit<5>();
+        FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBCSR3_CLEAR,
+                                ocb_status_ctl_data),
+                 "Error writing to the OCB3 Status Control Register with and mask");
+        ocb_status_ctl_data.flush<0>().setBit<4>();
+        FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBCSR3_OR,
+                                ocb_status_ctl_data),
+                 "Error writing to the OCB3 Status Control Register with or mask");
+
+        //Write the address to OCB3_ADDRESS Register
+        ocb3_addr_data = 0xB000000000000000 | ((i_address & 0x7FFFFFFull) << OCB3_ADDRESS_REG_ADDR_SHIFT);
+        ocb3_addr.insertFromRight<0, 64>(ocb3_addr_data);
+
+        FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBAR3, ocb3_addr),
+                 "Error writing the OCB3_ADDRESS Register");
+
+        //Write the PBA Slave Control Register that controls the tsize, fastmode, etc
+        //set bit 0 to enable OCI Base Address Range Enabled
+        pba_slave_ctl_data.setBit<PBA_SLVCTL_ENABLE_BIT>();
+        //set bits 1:3 to 110 for setting MasterID Match = OCB
+        pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_MASTER_ID_MATCH_START_BIT,
+                                           (PBA_SLVCTL_MASTER_ID_MATCH_END_BIT - PBA_SLVCTL_MASTER_ID_MATCH_START_BIT) + 1 >
+                                           (6);
+        //set bits 5:7 to 111 so that MasterID Care Match limits to ONLY the OCB
+        pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_MASTER_ID_CARE_MASK_START_BIT,
+                                           (PBA_SLVCTL_MASTER_ID_CARE_MASK_END_BIT -
+                                            PBA_SLVCTL_MASTER_ID_CARE_MASK_START_BIT) + 1 > (7);
+
+        //set the write ttype bits 8:10 to whatever is in the flags
+        pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_WRITE_TTYPE_START_BIT,
+                                           (PBA_SLVCTL_WRITE_TTYPE_END_BIT - PBA_SLVCTL_WRITE_TTYPE_START_BIT) + 1 > (l_operType);
+
+        //it's not cache-inhibited so set bit 15 to cl_rd_nc (0)
+        pba_slave_ctl_data.clearBit<PBA_SLVCTL_READ_TTYPE_BIT>();
+        //set bits 16:17 to No prefetch 01 TODO May need to change this later if we want to use prefetch
+        pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_READ_PREFETCH_CTL_START_BIT,
+                                           (PBA_SLVCTL_READ_PREFETCH_CTL_END_BIT - PBA_SLVCTL_READ_PREFETCH_CTL_START_BIT)
+                                           + 1 > (1);
+        //unset bit 18 - no auto-invalidate
+        pba_slave_ctl_data.clearBit<PBA_SLVCTL_READ_BUF_INVALIDATE_CTL_BIT>();
+        //set bit 19 - write buffer pair allocation bit to 1
+        pba_slave_ctl_data.setBit<PBA_SLVCTL_WRITE_BUF_PAIR_ALLOCATION_BIT>();
+        //set bit 21 - read buffer pair b allocation bit to 1
+        pba_slave_ctl_data.setBit<PBA_SLVCTL_READ_BUF_PAIR_B_ALLOCATION_BIT>();
+        //unset bits 20, 22, and 23
+        pba_slave_ctl_data.clearBit<PBA_SLVCTL_READ_BUF_PAIR_A_ALLOCATION_BIT>().clearBit<PBA_SLVCTL_READ_BUF_PAIR_C_ALLOCATION_BIT>().clearBit<PBA_SLVCTL_READ_BUF_PAIR_C_ALLOCATION_BIT>();
+        //unset bit 24 to allow write gather
+        pba_slave_ctl_data.clearBit<PBA_SLVCTL_DISABLE_WRITE_GATHER_BIT>();
+        //set bits 25:27 to 000 for write gather timeout NA
+        pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_WRITE_GATHER_TIMEOUT_START_BIT,
+                                           (PBA_SLVCTL_WRITE_GATHER_TIMEOUT_END_BIT -
+                                            PBA_SLVCTL_WRITE_GATHER_TIMEOUT_START_BIT) + 1 > (0);
+
+        //set bits 28:35 for the tsize to 0 - when this is an lco_m write need to do the chiplet ID of the L3 cache in the form of 00cc_ccc0
+        if (l_operType == p9_PBA_oper_flag::LCO && !i_rnw)
+        {
+            FAPI_TRY(fapi2::getScom(i_ex_target, EX_L3_MODE_REG1, l3_mode_reg1), "Error reading from the L3 Mode Register");
+            l3_mode_reg1.extractToRight(chiplet_number, 1, 5);
+        }
+
+        pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_WRITE_TSIZE_START_BIT,
+                                           (PBA_SLVCTL_WRITE_TSIZE_END_BIT - PBA_SLVCTL_WRITE_TSIZE_START_BIT) + 1 > (chiplet_number);
+        //set bits 36:49 to the ext addr
+        extaddr = ((uint32_t) (i_address >> PBA_SLVCTL_EXTADDR_SHIFT)) &
+                  PBA_SLVCTL_EXTADDR_MASK;
+
+        pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_EXT_ADDR_START_BIT,
+                                           (PBA_SLVCTL_EXT_ADDR_END_BIT - PBA_SLVCTL_EXT_ADDR_START_BIT) + 1 > (extaddr);
+
+        FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVCTL3_SCOM, pba_slave_ctl_data),
+                 "Error writing the PBA Slave Control Register");
+
+    fapi_try_exit:
+        FAPI_DBG("End");
+        return fapi2::current_err;
+    }
+
+    fapi2::ReturnCode p9_pba_coherent_setup_pba_bar(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_baseAddress)
+    {
+        fapi2::buffer<uint64_t> pba_bar_data;
+
+        FAPI_DBG("Start");
+
+        //Validate the input parameters
+        //Check the address alignment
+        FAPI_ASSERT(!(i_baseAddress & P9_FBC_UTILS_CACHELINE_MASK),
+                    fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS(
+                        i_baseAddress),
+                    "Base Address is not cacheline aligned");
+        //Make sure the address is within the PBA bounds
+        FAPI_ASSERT(i_baseAddress <= P9_FBC_UTILS_FBC_MAX_ADDRESS,
+                    fapi2::P9_PBA_COHERENT_UTILS_INVALID_ARGS().set_TARGET(i_target).set_ADDRESS(
+                        i_baseAddress),
+                    "Base Address exceeds supported fabric real address range");
+
+        //set command scope to local node scope
+        pba_bar_data.insertFromRight < PBA_BAR_SCOPE_START_BIT,
+                                     (PBA_BAR_SCOPE_END_BIT - PBA_BAR_SCOPE_START_BIT) + 1 >
+                                     (PBA_BAR_SCOPE_LOCAL_NODE);
+
+        //set base address bits 8:43
+        pba_bar_data.insertFromRight < PBA_BAR_BASE_ADDRESS_START_BIT,
+                                     (PBA_BAR_BASE_ADDRESS_END_BIT - PBA_BAR_BASE_ADDRESS_START_BIT) + 1 > ((
+                                             i_baseAddress >> PBA_BAR_BASE_ADDRESS_SHIFT) & PBA_BAR_BASE_ADDRESS_MASK);
+
+        //write the register
+        FAPI_TRY(fapi2::putScom(i_target, PU_PBABAR3, pba_bar_data),
+                 "Error writing the PBA Bar Register");
+
+    fapi_try_exit:
+        FAPI_DBG("End");
+        return fapi2::current_err;
+
+    }
+
+    fapi2::ReturnCode p9_pba_coherent_pba_write(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_address,
+        const uint8_t i_write_data[])
+    {
+        fapi2::ReturnCode rc;
+        uint64_t write_data = 0x0ull;
+        FAPI_DBG("Start");
+
+        //Perform a 128B write -- need to do 16 8B writes since it's in linear mode which can only do 8B...
+        for (int i = 0; i < 16; i++)
+        {
+            write_data = 0x0ull;
+
+            for (int j = 0; j < 8; j++)
+            {
+                write_data = write_data + ((uint64_t)(i_write_data[(i * 8) + j]) << (56 - (8 * j)));
+            }
+
+            fapi2::buffer<uint64_t> data(write_data);
+            FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBDR3, data),
+                     "Error writing to the PBA via the OCB");
+        }
+
+    fapi_try_exit:
+        FAPI_DBG("End");
+        return fapi2::current_err;
+    }
+
+    fapi2::ReturnCode p9_pba_coherent_pba_read(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_address,
+        uint8_t o_read_data[])
+    {
+        fapi2::buffer<uint64_t> data;
+
+        FAPI_DBG("Start");
+
+        //Perform a 128B read -- need to do 16 8B reads since it's in linear mode which can only do 8B...
+        for (int i = 0; i < 16; i++)
+        {
+            FAPI_TRY(fapi2::getScom(i_target, PU_OCB_PIB_OCBDR3, data),
+                     "Error reading from the PBA via the OCB");
+
+            for (int j = 0; j < 8; j++)
+            {
+                o_read_data[(i * 8) + j] = (data >> (56 - (j * 8))) & 0xFFull;;
+            }
+        }
+
+    fapi_try_exit:
+        FAPI_DBG("End");
+        return fapi2::current_err;
+    }
+
+    fapi2::ReturnCode p9_pba_coherent_cleanup_pba(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+    {
+        FAPI_DBG("Start");
+
+        fapi2::buffer<uint64_t> data;
+
+        //Clean up the PBA register by resetting PBASLVCTL3 by writing to the PBASLVRST
+        data.insertFromRight < PBA_SLVRST_SET_START_BIT,
+                             (PBA_SLVRST_SET_END_BIT - PBA_SLVRST_SET_START_BIT) + 1 > (7);
+        FAPI_TRY(fapi2::putScom(i_target, PU_PBASLVRST_SCOM, data),
+                 "Error writing to the PBA Slave Reset register");
+
+        //Wait a little bit and make sure that the reset is no longer in progress
+        FAPI_TRY(fapi2::delay(PBA_SLVRST_DELAY_HW_NS, PBA_SLVRST_DELAY_SIM_CYCLES),
+                 "Error from PBA Slave Reset delay");
+
+        FAPI_TRY(fapi2::getScom(i_target, PU_PBASLVRST_SCOM, data),
+                 "Error reading from the PBA Slave Reset register");
+
+        FAPI_ASSERT(!data.getBit<PBA_SLVRST_SLVCTL3_IN_PROG>(),
+                    fapi2::P9_PBA_COHERENT_UTILS_RESET_ERR().set_TARGET(i_target).set_RDDATA(
+                        data),
+                    "Error in resetting the PBA Slave Reset register");
+
+    fapi_try_exit:
+        FAPI_DBG("End");
+        return fapi2::current_err;
+    }
+
+    fapi2::ReturnCode p9_pba_coherent_status_check(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+    {
+        FAPI_DBG("Start");
+
+        fapi2::buffer<uint64_t> rd_buf2_valid;
+        fapi2::buffer<uint64_t> rd_buf3_valid;
+        fapi2::buffer<uint64_t> wr_buf0_valid;
+        fapi2::buffer<uint64_t> wr_buf1_valid;
+        fapi2::buffer<uint64_t> reset_buf;
+
+        //Check the 2 PBA Read Buffer Valid Status (2 and 3 since we set Buffer pair "B")by reading the read buffer status (bits 33:39) and making sure it's 1
+        FAPI_TRY(fapi2::getScom(i_target, PU_PBARBUFVAL2, rd_buf2_valid),
+                 "Error reading from the PBA Read Buffer Valid 2 Status Register");
+        FAPI_TRY(fapi2::getScom(i_target, PU_PBARBUFVAL3, rd_buf3_valid),
+                 "Error reading from the PBA Read Buffer Valid 3 Status Register");
+
+        //Check the 2 PBA Write Buffer Valid Status by reading the write buffer status (bits 35:39) and making sure it's 1
+        FAPI_TRY(fapi2::getScom(i_target, PU_PBAWBUFVAL0, wr_buf0_valid),
+                 "Error reading from the PBA Write Buffer Valid 0 Status Register");
+        FAPI_TRY(fapi2::getScom(i_target, PU_PBAWBUFVAL1, wr_buf1_valid),
+                 "Error reading from the PBA Write Buffer Valid 1 Status Register");
+
+        //Check the PBA Slave Reset Register for if things are still in progress
+        FAPI_TRY(fapi2::getScom(i_target, PU_PBASLVRST_SCOM, reset_buf),
+                 "Error reading from the PBA Slave Reset Register");
+
+        //If there are any errors in the Status registers that we got above, collect all of the data and send an error
+        FAPI_ASSERT((((((rd_buf2_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_EMPTY)
+                       || ((rd_buf2_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_VALID)
+                       || ((rd_buf2_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_VALIDWFP)) )
+                     && (((rd_buf3_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_EMPTY)
+                         || ((rd_buf3_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_VALID)
+                         || ((rd_buf3_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_VALIDWFP)  )
+                     && ((wr_buf0_valid & PBA_WR_BUF_VALID_MASK) == PBA_WR_BUF_EMPTY)
+                     && ((wr_buf1_valid & PBA_WR_BUF_VALID_MASK) == PBA_WR_BUF_EMPTY)
+                     && ((reset_buf & PBA_SLVRST_BUSY_IN_PROG_MASK) == 0)),
+                    fapi2::P9_PBA_STATUS_ERR().set_TARGET(i_target).set_RDBUF2(
+                        rd_buf2_valid).set_RDBUF3(rd_buf3_valid).set_WRBUF0(
+                        wr_buf0_valid).set_WRBUF1(wr_buf1_valid).set_SLVRSTDATA(reset_buf),
+                    "Error in checking the PBA Reset, PBA Read Buffer, or PBA Write Buffer Registers");
+
+    fapi_try_exit:
+        FAPI_DBG("End");
+        return fapi2::current_err;
+    }
+
+} //extern "C"
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H
new file mode 100644
index 00000000..e4be1c65
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H
@@ -0,0 +1,285 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------------
+// *!
+/// @file p9_pba_coherent_utils.H
+/// @brief Common Code to support PBA get/putmem procedures (FAPI)
+///
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+// ---------------------------------------------------------------------------------
+// *! ADDITIONAL COMMENTS :
+// *!
+// *!
+//-----------------------------------------------------------------------------------
+
+#ifndef _P9_PBA_COHERENT_UTILS_H_
+#define _P9_PBA_COHERENT_UTILS_H_
+
+//-----------------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------------
+
+#include <fapi2.H>
+#include <p9_pba_constants.H>
+
+extern "C"
+{
+
+//-----------------------------------------------------------------------------------
+// Constant definitions
+//-----------------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------------
+// Classes
+//-----------------------------------------------------------------------------------
+
+///
+/// @brief  Manage PBA operation flag that is used to program the
+///         PU_PBASLVCTL3_SCOM register.
+///
+    class p9_PBA_oper_flag
+    {
+        public:
+
+            // Type of PBA operations
+            enum OperationType_t
+            {
+                DMA            = 0,
+                LCO            = 1,
+                ATOMIC         = 2,
+                INJ            = 3,
+                CI             = 4,
+            };
+
+            // Constructor
+            inline p9_PBA_oper_flag(): iv_operType(DMA), iv_fastMode(false)
+            {
+            }
+
+            ///
+            /// @brief Set the PBA operation type
+            ///
+            /// @param[in] i_type     PBA operation type
+            ///
+            /// @return void.
+            ///
+            inline void setOperationType(const OperationType_t i_type)
+            {
+                iv_operType = i_type;
+                return;
+            }
+
+            ///
+            /// @brief Get the PBA operation type setting.
+            ///
+            /// @return iv_operType.
+            ///
+            inline const OperationType_t getOperationType(void)
+            {
+                return iv_operType;
+            }
+
+            ///
+            /// @brief Set fast read/write mode.
+            ///        For fast read/write mode, no error check until
+            ///        last granule.
+            ///
+            /// @param[in] i_value     True: Enable fast read/write mode.
+            ///                        False: Disable fast read/write mode.
+            ///
+            /// @return void.
+            ///
+            inline void setFastMode(bool i_value)
+            {
+                iv_fastMode = i_value;
+                return;
+            }
+
+            ///
+            /// @brief Get the PBA operation fast mode setting.
+            ///
+            /// @return iv_fastMode.
+            ///
+            inline const bool getFastMode(void)
+            {
+                return iv_fastMode;
+            }
+
+            ///
+            /// @brief Assemble the 32-bit PBA flag based on current
+            ///        info contained in this class.
+            ///        This flag is to be used in PBA interface call
+            ///        See flag bit definitions in p9_pba_constants.H
+            ///
+            /// @return uint32_t
+            ///
+            inline uint32_t setFlag();
+
+            ///
+            /// @brief Update the PBA class instant variables with info
+            ///        embedded in the passed in flag value.
+            ///
+            /// @return void.
+            ///
+            inline void getFlag(uint32_t i_flag);
+
+        private:
+
+            // Class variables
+            OperationType_t iv_operType;         // Operation type
+            bool iv_fastMode;                    // Fast PBA read/write mode
+    };
+
+///
+/// See doxygen in class definition
+///
+    uint32_t p9_PBA_oper_flag::setFlag()
+    {
+        uint32_t l_pbaFlag = 0;
+
+        // Operation type
+        l_pbaFlag |= (iv_operType << FLAG_PBA_TTYPE_SHIFT);
+
+        // Fast mode
+        if (iv_fastMode == true)
+        {
+            l_pbaFlag |= FLAG_PBA_FASTMODE;
+        }
+
+        // Debug trace
+        FAPI_DBG("p9_PBA_oper_flag::setFlag()");
+        FAPI_DBG("    iv_operType 0x%.8X, iv_fastMode 0x%.8X", iv_operType, iv_fastMode);
+        FAPI_DBG("   PBA Flag value: 0x%.8X", l_pbaFlag);
+
+        return l_pbaFlag;
+    }
+
+///
+/// See doxygen in class definition
+///
+    void p9_PBA_oper_flag::getFlag(const uint32_t i_flag)
+    {
+        // Decode Operation type
+        iv_operType = static_cast<OperationType_t>
+                      ( (i_flag & FLAG_PBA_TTYPE) >> FLAG_PBA_TTYPE_SHIFT);
+
+        // Fast mode
+        iv_fastMode = (i_flag & FLAG_PBA_FASTMODE);
+
+        // Debug trace
+        FAPI_DBG("p9_PBA_oper_flag::getFlag() - Flag value 0x%.8X", i_flag);
+        FAPI_DBG("    iv_operType 0x%.8X, iv_fastMode 0x%.8X",
+                 iv_operType, iv_fastMode);
+        return;
+    }
+
+//-----------------------------------------------------------------------------------
+// Function prototypes
+//-----------------------------------------------------------------------------------
+
+/// @brief does the setup for the PBA to set up the initial registers for a read/write
+/// @param[in] i_target => P9 chip target
+/// @param[in] i_ex_target => Ex target for which L3 we are targeting
+/// @param[in] i_address => starting address for PBA operation
+/// @param[in] i_rnw => whether the operation is a read or write
+/// @param[in] i_flags => flags that contain information that the PBA needs to know to set up registers
+/// @return FAPI_RC_SUCCESS if setting up the pba registers is a success
+    fapi2::ReturnCode p9_pba_coherent_setup_pba(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_ex_target,
+        const uint64_t i_address,
+        const bool i_rnw,
+        const uint32_t i_flags);
+
+/// @brief does the write for the PBA
+/// @param[in] i_target => P9 chip target
+/// @param[in] i_address => address for this write
+/// @param[in] i_write_data => the data that is to be written to the PBA
+/// @return FAPI_RC_SUCCESS if writing the PBA is a success
+    fapi2::ReturnCode p9_pba_coherent_pba_write(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_address,
+        const uint8_t i_write_data[]);
+
+/// @brief does the read for the PBA
+/// @param[in] i_target => P9 chip target
+/// @param[in] i_address => address for this write
+/// @param[out] o_read_data => the data that is read from the PBA
+/// @return FAPI_RC_SUCCESS if reading the PBA is a success
+    fapi2::ReturnCode p9_pba_coherent_pba_read(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_address,
+        uint8_t o_read_data[]);
+
+/// @brief calculates the number of 128 byte granules that can be read/written before setup needs to be run again
+/// @param[in] i_target => P9 chip target
+/// @param[in] i_address => starting address for PBA operation
+/// @return number of 128 byte granules that can be read/written before setup needs to be run again
+    fapi2::ReturnCode p9_pba_coherent_utils_get_num_granules(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_address,
+        uint32_t& o_numGranules);
+
+/// @brief ensure that fabric is initialized and stop control is not set
+///           (by checkstop/mode switch), which if set would prohibit fabric
+///           commands from being broadcasted
+/// @param[in] i_target => P9 chip target
+/// @return FAPI_RC_SUCCESS if fabric is not stopped
+    fapi2::ReturnCode p9_pba_coherent_utils_check_fbc_state(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+/// @brief check that the address is cacheline aligned and within the fabric real address range
+/// @param[in] i_target => P9 chip target
+/// @param[in] i_address => starting address for PBA operation
+/// @return FAPI_RC_SUCCESS if arguments are valid
+    fapi2::ReturnCode p9_pba_coherent_utils_check_args(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_address);
+/// @brief this checks the PBA/OCB status registers - this is for use at the end of each write/read or at the end of each stream
+/// @return FAPI_RC_SUCCESS if the status check is a success
+    fapi2::ReturnCode p9_pba_coherent_status_check(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+/// @brief this does any cleanup for the PBA after all reads/writes have been done
+/// @param[in] i_target => P9 chip target
+/// @return FAPI_RC_SUCCESS if cleaning up the PBA is a success
+    fapi2::ReturnCode p9_pba_coherent_cleanup_pba(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+///@brief sets up the PBA Bar
+///@param[in] i_target => P9 chip target
+///@param[in] i_address => address for this read/write
+///@return FAPI_RC_SUCCESS if writing the PBA is a success
+    fapi2::ReturnCode p9_pba_coherent_setup_pba_bar(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const uint64_t i_baseAddress);
+
+} //extern "C"
+
+#endif //_P9_PBA_COHERENT_UTILS_H_
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_constants.H b/src/import/chips/p9/procedures/hwp/nest/p9_pba_constants.H
new file mode 100644
index 00000000..f7914672
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_constants.H
@@ -0,0 +1,71 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_pba_constants.H $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file p9_pba_constants.H
+/// @brief Constant enums to support PBA get/putmem procedures (FAPI)
+///
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWp Consumed by: SBE
+
+#ifndef _P9_PBA_CONSTANTS_H_
+#define _P9_PBA_CONSTANTS_H_
+
+//---------------------------------------------------------------------------------------------
+// Includes
+//---------------------------------------------------------------------------------------------
+
+extern "C"
+{
+
+//----------------------------------------------------------------------------------------------
+// Constant definitions
+//----------------------------------------------------------------------------------------------
+    enum pba_flags
+    {
+        // Fastmode flag
+        // If this flag is set it means we will not check for errors until
+        // the very last granule for the read/write
+        FLAG_PBA_FASTMODE = 0x80000000ull,
+
+        // TTYPE flag
+        // PBA operation type
+        // 0b000: DMA
+        // 0b001: LCO_M
+        // 0b010: ATOMIC
+        // 0b011: CACHE_INJ
+        // 0b100: CI_PR_W
+        // Same as in the documentation and how they will be passed to the register
+        FLAG_PBA_TTYPE    = 0x70000000ull
+    };
+
+// TTYPE shift position
+    const uint64_t FLAG_PBA_TTYPE_SHIFT = 28;
+    const uint64_t FLAG_PBA_TTYPE_MASK = 0b111;
+
+} //extern "C"
+
+#endif //_P9_PBA_CONSTANTS_H_
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C
new file mode 100644
index 00000000..32df239e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C
@@ -0,0 +1,95 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_pba_setup.C $          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//--------------------------------------------------------------------------
+//
+//
+/// @file p9_pba_setup.C
+/// @brief Setup the registers for a read/write to the PBA
+///
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+//
+//--------------------------------------------------------------------------
+
+
+//--------------------------------------------------------------------------
+// Includes
+//--------------------------------------------------------------------------
+#include <p9_pba_setup.H>
+#include "p9_pba_coherent_utils.H"
+
+extern "C"
+{
+
+//--------------------------------------------------------------------------
+//  HWP entry point
+//--------------------------------------------------------------------------
+    fapi2::ReturnCode p9_pba_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>
+                                   & i_target,
+                                   const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_ex_target,
+                                   const uint64_t i_address,
+                                   const bool i_rnw,
+                                   const uint32_t i_flags,
+                                   uint32_t& o_numGranules)
+    {
+        // mark HWP entry
+        FAPI_DBG("Entering ...\n");
+
+        //check arguments
+        FAPI_TRY(p9_pba_coherent_utils_check_args(i_target, i_address),
+                 "Error from p9_pba_coherent_utils_check_args");
+
+        //ensure fabric is running
+        FAPI_TRY(p9_pba_coherent_utils_check_fbc_state(i_target),
+                 "Error from p9_pba_coherent_utils_check_fbc_state");
+
+        //reset the ADU - cleanup just calls reset
+        //TODO Joe had made a comment on this about resetting the PBA as part of the setup process - I need to test
+        //this more before I'm willing to actually put this in - I got some errors when I had it in earlier.
+        //FAPI_TRY(p9_pba_coherent_cleanup_pba(i_target), "p9_pba_setup: Error from p9_pba_cleanup_pba");
+
+        //The PBA Bar and PBA Bar Mask need to be setup before getting the number of granules because how they get setup affects the number of granules that can be read/written
+        //setup the PBA Bar
+        FAPI_TRY(p9_pba_coherent_setup_pba_bar(i_target, i_address),
+                 "Error from p9_pba_coherent_setup_pba_bar");
+
+        //setup the PBA for reading/writing
+        FAPI_TRY(p9_pba_coherent_setup_pba(i_target, i_ex_target, i_address, i_rnw, i_flags),
+                 "Error from p9_pba_coherent_setup_pba");
+
+        //figure out the number of 128B granules that can be read/written
+        FAPI_TRY(p9_pba_coherent_utils_get_num_granules(i_target, i_address,
+                 o_numGranules),
+                 "Error from p9_pba_coherent_utils_get_num_granules");
+
+    fapi_try_exit:
+        FAPI_DBG("Exiting...");
+        return fapi2::current_err;
+    }
+} // extern "C"
+
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.H b/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.H
new file mode 100644
index 00000000..96ce4025
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.H
@@ -0,0 +1,100 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_pba_setup.H $          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------------
+//
+/// @file p9_pba_setup.H
+/// @brief Setup the PBA to do reads/writes
+///
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+// ----------------------------------------------------------------------------------
+// *!
+// *! ADDITIONAL COMMENTS:
+// *!
+// *! The purpose of this procedure is to setup the PBA to do reads/writes
+// *! and to return the number of granules (number of 128B reads/writes) that
+// *! can be done before setup needs to be called again
+// *!
+// *! Successful operation assumes that:
+// *!
+// *! High-level procedure flow:
+// *!
+// *!
+// *!---------------------------------------------------------------------------------
+
+#ifndef _P9_PBA_SETUP_H_
+#define _P9_PBA_SETUP_H_
+
+//-----------------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------------
+
+#include <fapi2.H>
+#include <p9_pba_constants.H>
+
+//-----------------------------------------------------------------------------------
+// Structure definitions
+//-----------------------------------------------------------------------------------
+typedef fapi2::ReturnCode
+(*p9_pba_setup_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
+                      const fapi2::Target<fapi2::TARGET_TYPE_EX>&,
+                      const uint64_t,
+                      const bool,
+                      const uint32_t,
+                      uint32_t&);
+
+// Constant definitions
+//-----------------------------------------------------------------------------------
+
+extern "C" {
+
+//-----------------------------------------------------------------------------------
+// Function prototype
+//-----------------------------------------------------------------------------------
+
+/// @brief setup for reads/writes from the PBA
+/// @param[in]  i_target  => P9 chip target
+/// @param[in]  i_ex_target => P9 EX Target for use with lco_m operations
+/// @param[in]  i_address => base real address for read/write operation (expected to be 128B aligned)
+/// @param[in]  i_rnw     => if the operation is read not write (1 for read, 0 for write)
+/// @param[in]  i_flags   => other information that is needed - see the p9_pba_constants pba_flags enums for bit definitions
+///                          Note: to construct the flag you can use the p9_PBA_oper_flag class
+/// @param[out] o_numGranules => number of 128B granules that can be read/written before setup needs to be called again
+//
+/// @return FAPI_RC_SUCCESS if the setup completes successfully,
+//
+    fapi2::ReturnCode p9_pba_setup(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_ex_target,
+        const uint64_t i_address,
+        const bool i_rnw,
+        const uint32_t i_flags,
+        uint32_t& o_numGranules);
+} //extern "C"
+
+#endif //_P9_PBA_SETUP_H_
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C
new file mode 100755
index 00000000..840ad79b
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C
@@ -0,0 +1,186 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.C $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_sbe_fabricinit.C
+/// @brief Initialize island-mode fabric configuration (FAPI2)
+///
+/// @author Joe McGill <jmcgill@us.ibm.com>
+/// @author Christy Graves <clgraves@us.ibm.com>
+///
+
+//
+// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+//
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <p9_sbe_fabricinit.H>
+#include <p9_fbc_utils.H>
+#include <p9_misc_scom_addresses.H>
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+// FBC SCOM register address definitions
+// TODO: these are currently not present in the generated SCOM adddress header
+//       including locally defined address constants here for testing purposes
+const uint64_t PU_FBC_MODE_REG = 0x05011C0A;
+
+// ADU delay/polling constants
+const uint64_t FABRICINIT_DELAY_HW_NS = 1000; // 1us
+const uint64_t FABRICINIT_DELAY_SIM_CYCLES = 200;
+
+// ADU Command Register field/bit definitions
+const uint32_t ALTD_CMD_START_OP_BIT = 2;
+const uint32_t ALTD_CMD_CLEAR_STATUS_BIT = 3;
+const uint32_t ALTD_CMD_RESET_FSM_BIT = 4;
+const uint32_t ALTD_CMD_ADDRESS_ONLY_BIT = 6;
+const uint32_t ALTD_CMD_LOCK_BIT = 11;
+const uint32_t ALTD_CMD_SCOPE_START_BIT = 16;
+const uint32_t ALTD_CMD_SCOPE_END_BIT = 18;
+const uint32_t ALTD_CMD_DROP_PRIORITY_BIT = 20;
+const uint32_t ALTD_CMD_OVERWRITE_PBINIT_BIT = 22;
+const uint32_t ALTD_CMD_TTYPE_START_BIT = 25;
+const uint32_t ALTD_CMD_TTYPE_END_BIT = 31;
+const uint32_t ALTD_CMD_TSIZE_START_BIT = 32;
+const uint32_t ALTD_CMD_TSIZE_END_BIT = 39;
+
+const uint32_t ALTD_CMD_TTYPE_NUM_BITS = (ALTD_CMD_TTYPE_END_BIT - ALTD_CMD_TTYPE_START_BIT + 1);
+const uint32_t ALTD_CMD_TSIZE_NUM_BITS = (ALTD_CMD_TSIZE_END_BIT - ALTD_CMD_TSIZE_START_BIT + 1);
+const uint32_t ALTD_CMD_SCOPE_NUM_BITS = (ALTD_CMD_SCOPE_END_BIT - ALTD_CMD_SCOPE_START_BIT + 1);
+
+const uint32_t ALTD_CMD_TTYPE_PBOP_EN_ALL = 0x3F;
+const uint32_t ALTD_CMD_TSIZE_PBOP_EN_ALL = 0x0B;
+const uint32_t ALTD_CMD_SCOPE_GROUP = 0x3;
+
+// ADU Status Register field/bit definitions
+const uint32_t ALTD_STATUS_ADDR_DONE_BIT = 2;
+const uint32_t ALTD_STATUS_PBINIT_MISSING_BIT = 18;
+const uint32_t ALTD_STATUS_CRESP_START_BIT = 59;
+const uint32_t ALTD_STATUS_CRESP_END_BIT = 63;
+
+const uint32_t ALTD_STATUS_CRESP_NUM_BITS = (ALTD_STATUS_CRESP_END_BIT - ALTD_STATUS_CRESP_START_BIT + 1);
+
+const uint32_t ALTD_STATUS_CRESP_ACK_DONE = 0x04;
+
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+
+fapi2::ReturnCode
+p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+    FAPI_INF("Start");
+
+    fapi2::buffer<uint64_t> l_cmd_data;
+    fapi2::buffer<uint64_t> l_status_data_act;
+    fapi2::buffer<uint64_t> l_status_data_exp;
+    bool l_fbc_is_initialized, l_fbc_is_running;
+
+    // check state of fabric pervasive stop control signal
+    // if set, this would prohibit all fabric commands from being broadcast
+    FAPI_DBG("Checking status of FBC stop ...");
+    FAPI_TRY(p9_fbc_utils_get_fbc_state(i_target, l_fbc_is_initialized, l_fbc_is_running),
+             "Error from p9_fbc_utils_get_fbc_state");
+    FAPI_ASSERT(l_fbc_is_running,
+                fapi2::P9_SBE_FABRICINIT_FBC_STOPPED_ERR().
+                set_TARGET(i_target).
+                set_FBC_RUNNING(l_fbc_is_running),
+                "Pervasive stop control is asserted, so fabricinit will not run!");
+
+    // write ADU Command Register to attempt lock acquisition
+    // hold lock until finished with sequence
+    FAPI_DBG("Lock and reset ADU ...");
+    l_cmd_data.setBit<ALTD_CMD_LOCK_BIT>();
+    FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, l_cmd_data),
+             "Error writing ADU Command Register to acquire lock");
+
+    // clear ADU status/reset state machine
+    l_cmd_data.setBit<ALTD_CMD_CLEAR_STATUS_BIT>()
+    .setBit<ALTD_CMD_RESET_FSM_BIT>();
+    FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, l_cmd_data),
+             "Error writing ADU Command Register to clear status and reset state machine");
+
+    // launch init command
+    FAPI_INF("Launching fabric init command via ADU ...");
+    l_cmd_data.setBit<ALTD_CMD_START_OP_BIT>()
+    .clearBit<ALTD_CMD_CLEAR_STATUS_BIT>()
+    .clearBit<ALTD_CMD_RESET_FSM_BIT>()
+    .setBit<ALTD_CMD_ADDRESS_ONLY_BIT>()
+    .setBit<ALTD_CMD_DROP_PRIORITY_BIT>()
+    .setBit<ALTD_CMD_OVERWRITE_PBINIT_BIT>();
+    l_cmd_data.insertFromRight<ALTD_CMD_SCOPE_START_BIT, ALTD_CMD_SCOPE_NUM_BITS>(ALTD_CMD_SCOPE_GROUP);
+    l_cmd_data.insertFromRight<ALTD_CMD_TTYPE_START_BIT, ALTD_CMD_TTYPE_NUM_BITS>(ALTD_CMD_TTYPE_PBOP_EN_ALL);
+    l_cmd_data.insertFromRight<ALTD_CMD_TSIZE_START_BIT, ALTD_CMD_TSIZE_NUM_BITS>(ALTD_CMD_TSIZE_PBOP_EN_ALL);
+    FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, l_cmd_data),
+             "Error writing ADU Command Register to launch init operation");
+
+    // delay prior to checking for completion
+    FAPI_TRY(fapi2::delay(FABRICINIT_DELAY_HW_NS, FABRICINIT_DELAY_SIM_CYCLES),
+             "Error from delay");
+
+    // read ADU Status Register and check for expected pattern
+    FAPI_DBG("Checking status of ADU operation ...");
+    FAPI_TRY(fapi2::getScom(i_target, PU_ALTD_STATUS_REG, l_status_data_act),
+             "Error polling ADU Status Register");
+
+    l_status_data_exp.setBit<ALTD_STATUS_ADDR_DONE_BIT>();
+    l_status_data_exp.insertFromRight<ALTD_STATUS_CRESP_START_BIT, ALTD_STATUS_CRESP_NUM_BITS>(ALTD_STATUS_CRESP_ACK_DONE);
+
+    FAPI_ASSERT(l_status_data_exp == l_status_data_act,
+                fapi2::P9_SBE_FABRICINIT_FAILED_ERR().set_TARGET(i_target).
+                set_ADU_STATUS_EXP(l_status_data_act).
+                set_ADU_STATUS_ACT(l_status_data_act),
+                "Fabric init failed, or mismatch in expected ADU status!");
+
+    // clear ADU Command Register to release lock
+    FAPI_DBG("Success! Releasing ADU lock ...");
+    l_cmd_data = 0;
+    FAPI_TRY(fapi2::putScom(i_target, PU_ALTD_CMD_REG, l_cmd_data),
+             "Error writing ADU Command Register to release lock");
+
+    // confirm that fabric was successfully initialized
+    FAPI_DBG("Verifying status of FBC init/stop ...");
+    FAPI_TRY(p9_fbc_utils_get_fbc_state(i_target, l_fbc_is_initialized, l_fbc_is_running),
+             "Error from p9_fbc_utils_get_fbc_state");
+    FAPI_ASSERT(l_fbc_is_initialized && l_fbc_is_running,
+                fapi2::P9_SBE_FABRICINIT_NO_INIT_ERR().
+                set_TARGET(i_target).
+                set_FBC_INITIALIZED(l_fbc_is_initialized).
+                set_FBC_RUNNING(l_fbc_is_running),
+                "ADU command succeded, but fabric was not cleanly initialized!");
+
+fapi_try_exit:
+    FAPI_INF("End");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.H
new file mode 100755
index 00000000..ee1acf4a
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.H
@@ -0,0 +1,109 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_fabricinit.H $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_sbe_fabricinit.H
+/// @brief Initialize island-mode fabric configuration (FAPI2)
+///
+/// The purpose of this procedure is to initalize the fabric.
+///
+/// In the post scan flush/init state, the fabric command/data init lines on
+/// each chip are held de-asserted; this stops all local arbitration for
+/// command/data requests from attached units.  At the conclusion of this
+/// procedure, the fabric command/data init lines on the target chip
+/// will be asserted.  Units on the target chip may make fabric requests that
+/// will be processed and broadcast out to the SMP (consisting of the target
+/// chip only), based upon the defined fabric broadcast protocols.
+///
+/// The initialization is accomplished by injecting an init command (special
+/// ttype/tsize) into the fabric from the Alter Display Unit (ADU). This
+/// command is permitted to be broadcast (even though the target chip is not
+/// yet initialized), because the ADU is considered a trusted unit allowed
+/// to broadcast commands at any time.
+///
+/// When the init reflected command is observed by the fabric snooper logic
+/// (with target chip configured as fabric master), it will provide an
+/// lpc_ack partial response that generates a clean combined response
+/// (ack_done). Upon observation of the clean combined response broadcast,
+/// the fabric snooper logic will assert its command/data init lines to
+/// permit locally mastered requests to be arbitrated.
+///
+/// High-level procedure flow:
+/// - Check state of tc_pb_stop (set by checkstop), which if
+///   set would prohibit the init command from being broadcast
+/// - Acquire the ADU lock to guarantee exclusive use of ADU resources
+/// - Clear the ADU status register, reset ADU state machine
+/// - Program the ADU to issue & launch the init command
+/// - Check the status of the init command
+/// - Release the ADU lock
+/// - Confirm state of fabric init control
+///
+/// @author Joe McGill <jmcgill@us.ibm.com>
+/// @author Christy Graves <clgraves@us.ibm.com>
+///
+
+//
+// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+//
+
+#ifndef _P9_SBE_FABRICINIT_H_
+#define _P9_SBE_FABRICINIT_H_
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi2.H>
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_sbe_fabricinit_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+///
+/// @brief Initialize fabric (in single chip 'island mode' configuration) by mastering
+/// an init command (ttype=pbop.init_all) from the Alter Display Unit (ADU)
+///
+/// @param[in] i_target Reference to processor chip target
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+    fapi2::ReturnCode p9_sbe_fabricinit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+} // extern "C"
+
+#endif // _P9_SBE_FABRICINIT_H_
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
new file mode 100644
index 00000000..0fd5b531
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
@@ -0,0 +1,62 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------------
+//
+/// @file p9_sbe_hb_structures.H
+/// @brief Structures that the SBE and HB will both use
+//
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE, HB
+//-----------------------------------------------------------------------------------
+
+#ifndef _SBE_HB_STRUCTURES_H_
+#define _SBE_HB_STRUCTURES_H_
+
+//-----------------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------------
+// Structure definitions
+//-----------------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------------
+// Constant definitions
+//-----------------------------------------------------------------------------------
+
+// Structure starts at the bootloader zero address
+struct BootloaderConfigData_t
+{
+    uint32_t version;  // Some kind of version field so we know if there is new data being added
+    uint8_t sbeBootSide;  // 0=SBE side 0, 1=SBE side 1   [ATTR_SBE_BOOT_SIDE]
+    uint8_t pnorBootSide;  // 0=PNOR side A, 1=PNOR side B  [ATTR_PNOR_BOOT_SIDE]
+    uint16_t pnorSizeMB;  // Size of PNOR in MB  [ATTR_PNOR_SIZE]
+    uint64_t blLoadSize;  // Size of Load (Exception vectors and Bootloader)
+};
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C
new file mode 100644
index 00000000..10380058
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C
@@ -0,0 +1,327 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//--------------------------------------------------------------------------
+//
+// @file p9_sbe_load_bootloader.C
+// @brief Shift HB bootloader payload from SEEPROM to L3 cache of master core via PBA
+//
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP HWP Writer: Murey A Luna Torres malunato@us.ibm.com, Joseph McGill jmcgill@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+//
+//--------------------------------------------------------------------------
+
+//--------------------------------------------------------------------------
+// Includes
+//--------------------------------------------------------------------------
+#include <p9_sbe_load_bootloader.H>
+#include <p9_pba_setup.H>
+#include <p9_pba_access.H>
+#include <p9_fbc_utils.H>
+#include <p9_pba_coherent_utils.H>
+#include <p9_quad_scom_addresses.H>
+#include <p9_quad_scom_addresses_fld.H>
+#include <p9_ram_core.H>
+
+//-----------------------------------------------------------------------------------
+// Constant definitions
+//-----------------------------------------------------------------------------------
+
+// PBA setup/access HWP call constants
+const bool PBA_HWP_WRITE_OP = false;
+const int EXCEPTION_VECTOR_NUM_CACHELINES = 96;
+const uint32_t SBE_BOOTLOADER_VERSION = 0x901;
+const uint8_t PERV_TO_CORE_POS_OFFSET = 0x20;
+//-----------------------------------------------------------------------------------
+// Function definitions
+//-----------------------------------------------------------------------------------
+
+fapi2::ReturnCode p9_sbe_load_bootloader(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_master_chip_target,
+    const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_master_ex_target,
+    const uint64_t i_payload_size,
+    uint8_t* i_payload_data)
+{
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+    //the branching instruction for 12KB past where it currently is (1024 * 12 = 12288 = 0x3000)
+    //The branch instruction is 0100 10_address to branch to_ 0  0
+    //                      0      6                   29 30 31
+    //bit 30 is for absolute address (since it is not set this is relative)
+    const uint32_t l_branch_to_12 = 0x48003000ull;
+    const uint32_t C_0_THREAD_INFO_RAM_THREAD_ACTIVE_T0 = 18;
+    uint64_t l_bootloader_offset;
+    uint64_t l_hostboot_hrmor_offset;
+    uint64_t l_chip_base_address_nm0, l_chip_base_address_nm1;
+    uint64_t l_chip_base_address_m;
+    uint64_t l_chip_base_address_mmio;
+    uint64_t l_target_address;
+    uint32_t l_exception_instruction;
+    bool l_firstAccess = true;
+    uint32_t l_num_cachelines_to_roll;
+    uint8_t l_data_to_pass_to_pba_array[FABRIC_CACHELINE_SIZE];
+    uint32_t l_exception_vector_size = 0;
+    uint8_t l_master_core = 0;
+    int l_cacheline_num = 0;
+    p9_PBA_oper_flag l_myPbaFlag;
+    fapi2::buffer<uint64_t> l_dataBuf;
+    fapi2::Target<fapi2::TARGET_TYPE_CORE> l_coreTarget;
+    bool l_coreFoundMatch = false;
+
+    FAPI_DBG("Start");
+
+    //Find the master core for writing the HRMOR later
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MASTER_CORE, i_master_chip_target, l_master_core), "Error getting ATTR_MASTER_CORE");
+
+    for ( auto l_current_core : i_master_ex_target.getChildren<fapi2::TARGET_TYPE_CORE>())
+    {
+        uint8_t l_attr_chip_unit_pos = 0;
+        fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = l_current_core.getParent<fapi2::TARGET_TYPE_PERV>();
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, l_attr_chip_unit_pos),
+                 "Error getting ATTR_CHIP_UNIT_POS");
+        l_attr_chip_unit_pos = l_attr_chip_unit_pos - PERV_TO_CORE_POS_OFFSET;
+        FAPI_DBG("l_attr_chip_unit_pos = %d, l_attr_chip_unit_pos = %d, l_master_core = %d", l_attr_chip_unit_pos,
+                 l_attr_chip_unit_pos, l_master_core);
+
+        if (l_attr_chip_unit_pos == l_master_core)
+        {
+            l_coreTarget = l_current_core;
+            l_coreFoundMatch = true;
+            break;
+        }
+    }
+
+    FAPI_ASSERT(l_coreFoundMatch, fapi2::P9_MASTER_CORE_NOT_FOUND().set_CHIP_TARGET(i_master_chip_target).set_EX_TARGET(
+                    i_master_ex_target).set_MASTER_CORE(l_master_core) , "Error in finding the master core");
+
+    // read platform initialized attributes needed to determine target base address
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_BOOTLOADER_OFFSET, FAPI_SYSTEM, l_bootloader_offset),
+             "Error from FAPI_ATTR_GET (ATTR_SBE_BOOTLOADER_OFFSET)");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HOSTBOOT_HRMOR_OFFSET, FAPI_SYSTEM, l_hostboot_hrmor_offset),
+             "Error from FAPI_ATTR_GET (ATTR_HOSTBOOT_HRMOR_OFFSET)");
+
+    // target base address = (chip non-mirrored base address) +
+    //                       (hostboot HRMOR offset) +
+    //                       (bootloader offset)
+    FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_master_chip_target,
+             l_chip_base_address_nm0,
+             l_chip_base_address_nm1,
+             l_chip_base_address_m,
+             l_chip_base_address_mmio),
+             "Error from p9_fbc_utils_get_chip_base_address");
+
+    // add hostboot HRMOR offset and bootloader offset contributions
+    l_chip_base_address_nm0 += l_hostboot_hrmor_offset;
+    l_chip_base_address_nm0 += l_bootloader_offset;
+
+    // check that base address is cacheline aligned
+    FAPI_ASSERT(!(l_chip_base_address_nm0 % FABRIC_CACHELINE_SIZE),
+                fapi2::P9_SBE_LOAD_BOOTLOADER_INVALID_TARGET_ADDRESS().
+                set_CHIP_TARGET(i_master_chip_target).
+                set_EX_TARGET(i_master_ex_target).
+                set_TARGET_BASE_ADDRESS(l_chip_base_address_nm0).
+                set_HRMOR_OFFSET(l_hostboot_hrmor_offset).
+                set_BOOTLOADER_OFFSET(l_bootloader_offset),
+                "Target base address is not cacheline aligned!");
+
+    //Check to see if we need to populate the exception vectors
+    //Check the SBE_HBBL_EXCEPTION_INSTRUCT attribute
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_HBBL_EXCEPTION_INSTRUCT, FAPI_SYSTEM, l_exception_instruction),
+             "fapiGetAttribute of ATTR_SBE_HBBL_EXCEPTION_INSTRUCT failed!");
+
+    l_target_address = l_chip_base_address_nm0;
+
+    BootloaderConfigData_t l_bootloader_config_data;
+
+    l_bootloader_config_data.version = SBE_BOOTLOADER_VERSION;
+
+    //At address X + 0x8 put whatever is in ATTR_SBE_BOOT_SIDE
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_BOOT_SIDE, FAPI_SYSTEM, l_bootloader_config_data.sbeBootSide),
+             "fapiGetAttribute of ATTR_SBE_BOOT_SIDE failed!");
+
+    //At address X + 0x9 put whatever is in ATTR_PNOR_BOOT_SIDE
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PNOR_BOOT_SIDE, FAPI_SYSTEM, l_bootloader_config_data.pnorBootSide),
+             "fapiGetAttribute of ATTR_PNOR_BOOT_SIDE failed!");
+
+    //At address X + 0xA put whatever is in ATTR_PNOR_SIZE
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PNOR_SIZE, FAPI_SYSTEM, l_bootloader_config_data.pnorSizeMB),
+             "fapiGetAttribute of ATTR_PNOR_SIZE failed!");
+
+    // check that the payload size is non-zero and evenly divisible into cachelines
+    FAPI_ASSERT(i_payload_size && !(i_payload_size % FABRIC_CACHELINE_SIZE),
+                fapi2::P9_SBE_LOAD_BOOTLOADER_INVALID_PAYLOAD_SIZE().
+                set_CHIP_TARGET(i_master_chip_target).
+                set_EX_TARGET(i_master_ex_target).
+                set_PAYLOAD_SIZE(i_payload_size),
+                "Payload size is invalid!");
+
+    // adjust exception vector size
+    if (l_exception_instruction != 0x0)
+    {
+        l_exception_vector_size = EXCEPTION_VECTOR_NUM_CACHELINES * FABRIC_CACHELINE_SIZE;
+    }
+
+    // Pass size of load including exception vectors and Bootloader
+    l_bootloader_config_data.blLoadSize = l_exception_vector_size + i_payload_size;
+
+    // move data using PBA setup/access HWPs
+    l_myPbaFlag.setFastMode(true);  // FASTMODE
+    l_myPbaFlag.setOperationType(p9_PBA_oper_flag::LCO); // LCO operation
+
+    while (l_target_address < (l_chip_base_address_nm0 + i_payload_size + l_exception_vector_size))
+    {
+        // invoke PBA setup HWP to prep stream
+        FAPI_TRY(p9_pba_setup( i_master_chip_target,
+                               i_master_ex_target,
+                               l_target_address,
+                               PBA_HWP_WRITE_OP,
+                               l_myPbaFlag.setFlag(),
+                               l_num_cachelines_to_roll), "Error from p9_pba_setup");
+
+        l_firstAccess = true;
+
+        // call PBA access HWP per cacheline to move payload data
+        while (l_num_cachelines_to_roll &&
+               (l_target_address < (l_chip_base_address_nm0 + i_payload_size + l_exception_vector_size)))
+        {
+            if ((l_cacheline_num == 0) && (l_exception_instruction != 0))
+            {
+                //This is for the first cacheline of data that has the branch, pnor_size, and pnor_boot_side in it
+                //The rest of the exception vector is what was in SBE_HBBL_EXCEPTION_INSTRUCT replicated multiple times (until the end of 12KB of exception vector data)
+                for (uint32_t i = 0; i < FABRIC_CACHELINE_SIZE; i++)
+                {
+                    //At address X put whatever is in l_branch_to_12
+                    if (i < 4)
+                    {
+                        l_data_to_pass_to_pba_array[i] = (l_branch_to_12 >> (24 - 8 * i )) & 0xFF;
+                    }
+                    //At address X + 0x4 put the HBBL_STRUCT_VERSION
+                    else if (i < 8)
+                    {
+                        l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.version >> (24 - 8 * ((i - 4) % 4))) & 0xFF;
+                    }
+                    //At address X + 0x8 put the SBE_BOOT_SIDE
+                    else if (i == 8)
+                    {
+                        l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.sbeBootSide;
+                    }
+                    //At address X + 0x9 put the PNOR_BOOT_SIDE
+                    else if (i  == 9)
+                    {
+                        l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.pnorBootSide;
+                    }
+                    //At address X + 0xA pu the PNOR_SIZE
+                    else if (i == 10)
+                    {
+                        l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.pnorSizeMB >> 8 & 0xFF;
+                    }
+                    else if (i == 11)
+                    {
+                        l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.pnorSizeMB & 0xFF;
+                    }
+                    //At address X + 0xC put the total load size
+                    else if (i < 20)
+                    {
+                        l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.blLoadSize >> (56 - 8 * ((i - 12) % 8))) & 0xFF;
+                    }
+                    //Fill the rest with the exception vector instruction
+                    else
+                    {
+                        l_data_to_pass_to_pba_array[i] = (l_exception_instruction >> (24 - 8 * (i % 4))) & 0xFF;
+                    }
+                }
+            }
+            else if ((l_cacheline_num  == 1) && (l_exception_instruction != 0))
+            {
+                //This is for the other 95 cachelines that we are sending
+                for (uint32_t i = 0; i < FABRIC_CACHELINE_SIZE; i++)
+                {
+                    l_data_to_pass_to_pba_array[i] = (l_exception_instruction >> (24 - 8 * (i % 4))) & 0xFF;
+                }
+            }
+            else if ((l_cacheline_num >= EXCEPTION_VECTOR_NUM_CACHELINES) || (l_exception_instruction == 0))
+            {
+                //This is for the data after the exception vector
+                for (uint32_t i = 0; i < FABRIC_CACHELINE_SIZE; i++)
+                {
+                    l_data_to_pass_to_pba_array[i] = i_payload_data[((l_cacheline_num - (l_exception_vector_size / FABRIC_CACHELINE_SIZE)) *
+                                                     FABRIC_CACHELINE_SIZE)
+                                                     + i];
+                }
+            }
+
+            FAPI_TRY(p9_pba_access(i_master_chip_target,
+                                   l_target_address,
+                                   PBA_HWP_WRITE_OP,
+                                   l_myPbaFlag.setFlag(),
+                                   l_firstAccess,
+                                   (l_num_cachelines_to_roll == 1) ||
+                                   ((l_target_address + FABRIC_CACHELINE_SIZE) >=
+                                    (l_chip_base_address_nm0 + i_payload_size + l_exception_vector_size)),
+                                   l_data_to_pass_to_pba_array), "Error from p9_pba_access");
+            l_firstAccess = false;
+            // decrement count of cachelines remaining in current stream
+            l_num_cachelines_to_roll--;
+
+            // stride address/payload data pointer offset to next cacheline
+            l_target_address += FABRIC_CACHELINE_SIZE;
+            l_cacheline_num++;
+        }
+    }
+
+    {
+        //instantiate the basic RamCore class
+        RamCore ram(l_coreTarget, 0);
+
+        //Set the HRMOR
+        //Override PM_EXIT on master core bit 4 is for core 0 bit 5 is for core 1
+        if (l_master_core % 2 == 0)
+        {
+            l_dataBuf.flush<0>().setBit<EQ_CME_SCOM_SICR_PM_EXIT_C0>();
+        }
+        else
+        {
+            l_dataBuf.flush<0>().setBit<EQ_CME_SCOM_SICR_PM_EXIT_C1>();
+        }
+
+        FAPI_TRY(fapi2::putScom(i_master_ex_target, EX_0_CME_SCOM_SICR_SCOM2, l_dataBuf),
+                 "Error overriding PM_EXIT");
+        //Set ram_thread_active for t0
+        l_dataBuf.flush<0>().setBit<C_0_THREAD_INFO_RAM_THREAD_ACTIVE_T0>();
+        FAPI_TRY(fapi2::putScom(l_coreTarget, C_0_THREAD_INFO, l_dataBuf),
+                 "Error setting thread active for t0");
+        l_dataBuf.flush<0>().insertFromRight<0, 64>(l_chip_base_address_nm0);
+        //call RamCore put_reg method
+        FAPI_TRY(ram.put_reg(REG_SPR, 313, &l_dataBuf), "Error ramming HRMOR");
+    }
+
+fapi_try_exit:
+    FAPI_DBG("End");
+    return fapi2::current_err;
+}
+
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H
new file mode 100644
index 00000000..e5536789
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H
@@ -0,0 +1,99 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------------
+//
+/// @file p9_sbe_load_bootloader.H
+/// @brief Shift HB bootloader payload from SEEPROM to L3 cache of master core via PBA
+//
+// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
+// *HWP HWP Writer: Murey A Luna Torres malunato@us.ibm.com, Joseph McGill jmcgill@us.ibm.com
+// *HWP FW Owner: Thi Tran thi@us.ibm.com
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+//-----------------------------------------------------------------------------------
+// *! ADDITIONAL COMMENTS:
+// *!
+// *! This hardware procedure is used to load a bootloader image from seeprom into
+// *! L3 of master core via PBA unit.
+// *!
+// *! Successful operation assumes that:
+// *! PBA communication is available
+// *!
+// *! High-level procedure flow:
+// *!
+//------------------------------------------------------------------------------------
+
+#ifndef _SBE_BOOTLOADER_H_
+#define _SBE_BOOTLOADER_H_
+
+//-----------------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------------
+
+#include <fapi2.H>
+#include <p9_sbe_hb_structures.H>
+//-----------------------------------------------------------------------------------
+// Structure definitions
+//-----------------------------------------------------------------------------------
+
+//function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode(*p9_sbe_load_bootloader_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
+    const fapi2::Target<fapi2::TARGET_TYPE_EX>&,
+    const uint64_t,
+    uint8_t*);
+
+//-----------------------------------------------------------------------------------
+// Constant definitions
+//-----------------------------------------------------------------------------------
+
+extern "C" {
+
+    //-----------------------------------------------------------------------------------
+    // Function prototype
+    //-----------------------------------------------------------------------------------
+    //
+/// @brief Shift HB bootloader payload from SEEPROM to L3 cache of master core via PBA
+/// @param[in] i_master_chip_target Reference to master processor chip target
+/// @param[in] i_master_ex_target Reference to master ex unit target
+/// @param[in] i_payload_size Size of image payload load to load, in B
+/// @param[in] i_payload_data Pointer to image payload data
+///
+/// @return FAPI_RC_SUCCESS if success, else error code
+///
+    fapi2::ReturnCode p9_sbe_load_bootloader(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_master_chip_target,
+        const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_master_eq_target,
+        const uint64_t i_payload_size,
+        uint8_t* i_payload_data);
+
+} //extern "C"
+
+#endif //_SBE_BOOTLOADER_H_
+
+
+
+
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C
new file mode 100644
index 00000000..1fe5dc4f
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C
@@ -0,0 +1,197 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.C $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_sbe_mcs_setup.C
+/// @brief Configure MC unit to support HB execution (FAPI2)
+///
+
+///
+/// @author Joe McGill <jmcgill@us.ibm.com>
+///
+
+//
+// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+//
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <p9_sbe_mcs_setup.H>
+#include <p9_fbc_utils.H>
+#include <p9_mc_scom_addresses.H>
+#include <p9_mc_scom_addresses_fld.H>
+
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+const uint8_t MCS_MCFGP_BASE_ADDRESS_START_BIT = 8;
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+///
+/// @brief Set hostboot dcbz MC configuration for one unit target
+///
+/// @param[in] i_target Reference to an MC target (MCS/MI)
+/// @param[in] i_chip_base_address Chip non-mirrored base address
+////// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+template<fapi2::TargetType T>
+fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target<T>& i_target,
+                                     const uint64_t i_chip_base_address);
+
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+
+// specialization for MCS target type
+template<>
+fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+                                     const uint64_t i_chip_base_address)
+{
+    FAPI_DBG("Start");
+    fapi2::buffer<uint64_t> l_mcfgp;
+    fapi2::buffer<uint64_t> l_mcmode1;
+    fapi2::buffer<uint64_t> l_mcfirmask_and;
+
+    // MCFGP -- set BAR valid, configure single MC group with minimum size at chip base address
+    FAPI_TRY(fapi2::getScom(i_target, MCS_MCFGP, l_mcfgp),
+             "Error from getScom (MCS_MCFGP)");
+    l_mcfgp.setBit<MCS_MCFGP_VALID>();
+    l_mcfgp.clearBit<MCS_MCFGP_MC_CHANNELS_PER_GROUP,
+                     MCS_MCFGP_MC_CHANNELS_PER_GROUP_LEN>();
+    l_mcfgp.clearBit<MCS_MCFGP_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION,
+                     MCS_MCFGP_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION_LEN>();
+    l_mcfgp.clearBit<MCS_MCFGP_GROUP_SIZE, MCS_MCFGP_GROUP_SIZE_LEN>();
+    // group base address field covers RA 8:31
+    l_mcfgp.insert(i_chip_base_address,
+                   MCS_MCFGP_GROUP_BASE_ADDRESS,
+                   MCS_MCFGP_GROUP_BASE_ADDRESS_LEN,
+                   MCS_MCFGP_BASE_ADDRESS_START_BIT);
+    FAPI_TRY(fapi2::putScom(i_target, MCS_MCFGP, l_mcfgp),
+             "Error from putScom (MCS_MCFGP)");
+
+    // MCMODE1 -- disable speculation
+    FAPI_TRY(fapi2::getScom(i_target, MCS_MCMODE1, l_mcmode1),
+             "Error from getScom (MCS_MCMODE1)");
+    l_mcmode1.setBit<MCS_MCMODE1_DISABLE_ALL_SPEC_OPS>();
+    l_mcmode1.setBit<MCS_MCMODE1_DISABLE_SPEC_OP,
+                     MCS_MCMODE1_DISABLE_SPEC_OP_LEN>();
+    FAPI_TRY(fapi2::putScom(i_target, MCS_MCMODE1, l_mcmode1),
+             "Error from putScom (MCS_MCMODE1)");
+
+    // MCFIRMASK -- unmask command list/channel timeout errors (so a checkstop will
+    //              occur if we break cache containment, but hit against the BAR)
+    l_mcfirmask_and.flush<1>();
+    l_mcfirmask_and.clearBit<MCS_MCFIR_COMMAND_LIST_TIMEOUT>();
+    l_mcfirmask_and.clearBit<MCS_MCFIR_COMMAND_LIST_TIMEOUT_SPEC>();
+    l_mcfirmask_and.clearBit<MCS_MCFIR_CHANNEL_0_TIMEOUT_ERROR>();
+    FAPI_TRY(fapi2::putScom(i_target, MCS_MCFIRMASK_AND, l_mcfirmask_and),
+             "Error from putScom (MCS_MCFIRMASK_AND)");
+
+fapi_try_exit:
+    FAPI_DBG("End");
+    return fapi2::current_err;
+}
+
+
+// specialization for MI target type
+template<>
+fapi2::ReturnCode set_hb_dcbz_config(const fapi2::Target<fapi2::TARGET_TYPE_MI>& i_target,
+                                     const uint64_t i_chip_base_address)
+{
+    // TODO: implement for Cumulus (MI target)
+    return fapi2::current_err;
+}
+
+
+// HWP entry point
+fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+    FAPI_INF("Start");
+
+    uint8_t l_is_master_sbe;
+    uint8_t l_is_mpipl;
+    uint8_t l_ipl_type;
+    uint64_t l_chip_base_address_nm0, l_chip_base_address_nm1, l_chip_base_address_m, l_chip_base_address_mmio;
+
+    auto l_mcs_chiplets = i_target.getChildren<fapi2::TARGET_TYPE_MCS>();
+    auto l_mi_chiplets = i_target.getChildren<fapi2::TARGET_TYPE_MI>();
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+
+    // configure one MC on master chip (only if IPL is loading hostboot, and is not memory
+    // preserving)
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_SBE_MASTER_CHIP, i_target, l_is_master_sbe),
+             "Error from FAPI_ATTR_GET (ATTR_PROC_SBE_MASTER_CHIP)");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_is_mpipl),
+             "Error from FAPI_ATTR_GET (ATTR_IS_MPIPL)");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_ipl_type),
+             "Error from FAPI_ATTR_GET (ATTR_SYSTEM_IPL_PHASE)");
+
+    if ((l_ipl_type == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_IPL) &&
+        l_is_master_sbe &&
+        !l_is_mpipl)
+    {
+        FAPI_ASSERT(l_mcs_chiplets.size() || l_mi_chiplets.size(),
+                    fapi2::P9_SBE_MCS_SETUP_NO_MC_FOUND_ERR().set_CHIP(i_target),
+                    "No functional MC unit target found");
+
+        // determine base address
+        FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
+                 l_chip_base_address_nm0,
+                 l_chip_base_address_nm1,
+                 l_chip_base_address_m,
+                 l_chip_base_address_mmio),
+                 "Error from p9_fbc_utils_get_chip_base_addrs");
+
+        if (l_mcs_chiplets.size())
+        {
+            FAPI_TRY(set_hb_dcbz_config(l_mcs_chiplets.front(),
+                                        l_chip_base_address_nm0),
+                     "Error from set_hb_dcbz_config (MCS)");
+        }
+        else
+        {
+            FAPI_TRY(set_hb_dcbz_config(l_mi_chiplets.front(),
+                                        l_chip_base_address_nm0),
+                     "Error from set_hb_dcbz_config (MI)");
+        }
+    }
+
+fapi_try_exit:
+    FAPI_INF("End");
+    return fapi2::current_err;
+
+}
+
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.H
new file mode 100644
index 00000000..d3017dcf
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.H
@@ -0,0 +1,77 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_mcs_setup.H $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_sbe_mcs_setup.H
+/// @brief Configure MC unit to support HB execution (FAPI2)
+///
+/// Configure MC unit on the master chip to lpc_ack dcbz operations
+/// executed by hostboot code (while still running cache contained prior
+/// to configuration of system memory)
+///
+/// @author Joe McGill <jmcgill@us.ibm.com>
+///
+
+//
+// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+//
+
+#ifndef _P9_SBE_MCS_SETUP_H_
+#define _P9_SBE_MCS_SETUP_H_
+
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi2.H>
+
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_sbe_mcs_setup_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+///
+/// @brief Set MC configuration to enable initial phase of hostboot execution
+///
+/// @param[in] i_target Reference to processor chip target
+/// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code.
+
+    fapi2::ReturnCode p9_sbe_mcs_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+} // extern "C"
+
+#endif // _P9_SBE_MCS_SETUP_H_
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
new file mode 100644
index 00000000..a2510582
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
@@ -0,0 +1,405 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+///
+/// @file p9_sbe_scominit.C
+/// @brief Peform SCOM initialization required for fabric & HBI operation (FAPI2)
+///
+/// @author Joe McGill <jmcgill@us.ibm.com>
+/// @author Christy Graves <clgraves@us.ibm.com>
+///
+
+//
+// *HWP HWP Owner: Joe McGill <jmcgill@us.ibm.com>
+// *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+// *HWP Team: Nest
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+//
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <p9_sbe_scominit.H>
+#include <p9_fbc_utils.H>
+
+#include <p9_misc_scom_addresses.H>
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
+
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+// XSCOM/LPC BAR constants
+const uint64_t XSCOM_BAR_MASK = 0xFF000003FFFFFFFFULL;
+const uint64_t LPC_BAR_MASK = 0xFF000000FFFFFFFFULL;
+
+// FBC FIR constants
+const uint64_t FBC_CENT_FIR_ACTION0 = 0x0000000000000000ULL;
+const uint64_t FBC_CENT_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL;
+const uint64_t FBC_CENT_FIR_MASK    = 0xFFFFFFFFFFFFFFFFULL;
+const uint64_t FBC_WEST_FIR_ACTION0 = 0x0000000000000000ULL;
+const uint64_t FBC_WEST_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL;
+const uint64_t FBC_WEST_FIR_MASK    = 0xFFFFFFFFFFFFFFFFULL;
+const uint64_t FBC_EAST_FIR_ACTION0 = 0x0000000000000000ULL;
+const uint64_t FBC_EAST_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL;
+const uint64_t FBC_EAST_FIR_MASK    = 0xFFFFFFFFFFFFFFFFULL;
+
+// PBA FIR constants
+const uint64_t PBA_FIR_ACTION0 = 0x0000000000000000ULL;
+const uint64_t PBA_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL;
+const uint64_t PBA_FIR_MASK = 0xFFFFFFFFFFFFFFFFULL;
+
+// chiplet pervasive FIR constants
+const uint64_t PERV_LFIR_ACTION0[15] =
+{
+    0x0000000000000000ULL, // TP
+    0x0000000000000000ULL, // N0
+    0x0000000000000000ULL, // N1
+    0x0000000000000000ULL, // N2
+    0x0000000000000000ULL, // N3
+    0x0000000000000000ULL, // X
+    0x0000000000000000ULL, // -
+    0x0000000000000000ULL, // -
+    0x0000000000000000ULL, // OB0
+    0x0000000000000000ULL, // OB1
+    0x0000000000000000ULL, // OB2
+    0x0000000000000000ULL, // OB3
+    0x0000000000000000ULL, // PCI0
+    0x0000000000000000ULL, // PCI1
+    0x0000000000000000ULL  // PCI2
+};
+
+const uint64_t PERV_LFIR_ACTION1[15] =
+{
+    0x0000000000000000ULL, // TP
+    0xFFFFFFFFFFFFFFFFULL, // N0
+    0xFFFFFFFFFFFFFFFFULL, // N1
+    0xFFFFFFFFFFFFFFFFULL, // N2
+    0xFFFFFFFFFFFFFFFFULL, // N3
+    0xFFFFFFFFFFFFFFFFULL, // X
+    0xFFFFFFFFFFFFFFFFULL, // -
+    0xFFFFFFFFFFFFFFFFULL, // -
+    0xFFFFFFFFFFFFFFFFULL, // OB0
+    0xFFFFFFFFFFFFFFFFULL, // OB1
+    0xFFFFFFFFFFFFFFFFULL, // OB2
+    0xFFFFFFFFFFFFFFFFULL, // OB3
+    0xFFFFFFFFFFFFFFFFULL, // PCI0
+    0xFFFFFFFFFFFFFFFFULL, // PCI1
+    0xFFFFFFFFFFFFFFFFULL  // PCI2
+};
+
+const uint64_t PERV_LFIR_MASK[15] =
+{
+    0xFFFFFFFFFFFFFFFFULL, // TP
+    0xFFFFFFFFFFFFFFFFULL, // N0
+    0xFFFFFFFFFFFFFFFFULL, // N1
+    0xFFFFFFFFFFFFFFFFULL, // N2
+    0xFFFFFFFFFFFFFFFFULL, // N3
+    0xFFFFFFFFFFFFFFFFULL, // X
+    0xFFFFFFFFFFFFFFFFULL, // -
+    0xFFFFFFFFFFFFFFFFULL, // -
+    0xFFFFFFFFFFFFFFFFULL, // OB0
+    0xFFFFFFFFFFFFFFFFULL, // OB1
+    0xFFFFFFFFFFFFFFFFULL, // OB2
+    0xFFFFFFFFFFFFFFFFULL, // OB3
+    0xFFFFFFFFFFFFFFFFULL, // PCI0
+    0xFFFFFFFFFFFFFFFFULL, // PCI1
+    0xFFFFFFFFFFFFFFFFULL  // PCI2
+};
+
+// chiplet XIR constants
+const uint64_t PERV_XFIR_MASK[15] =
+{
+    0xFFFFFFFFFFFFFFFFULL, // TP
+    0xFFFFFFFFFFFFFFFFULL, // N0
+    0xFFFFFFFFFFFFFFFFULL, // N1
+    0xFFFFFFFFFFFFFFFFULL, // N2
+    0xFFFFFFFFFFFFFFFFULL, // N3
+    0xFFFFFFFFFFFFFFFFULL, // X
+    0xFFFFFFFFFFFFFFFFULL, // -
+    0xFFFFFFFFFFFFFFFFULL, // -
+    0xFFFFFFFFFFFFFFFFULL, // OB0
+    0xFFFFFFFFFFFFFFFFULL, // OB1
+    0xFFFFFFFFFFFFFFFFULL, // OB2
+    0xFFFFFFFFFFFFFFFFULL, // OB3
+    0xFFFFFFFFFFFFFFFFULL, // PCI0
+    0xFFFFFFFFFFFFFFFFULL, // PCI1
+    0xFFFFFFFFFFFFFFFFULL  // PCI2
+};
+
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+
+{
+    FAPI_DBG("Entering ...");
+    fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+    uint64_t l_base_addr_nm0;
+    uint64_t l_base_addr_nm1;
+    uint64_t l_base_addr_m;
+    uint64_t l_base_addr_mmio;
+
+    // set fabric topology information in each pervasive chiplet (outside of EC/EP)
+    {
+        // read fabric topology attributes
+        uint32_t l_fbc_system_id;
+        uint8_t l_fbc_group_id;
+        uint8_t l_fbc_chip_id;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_SYSTEM_ID, i_target, l_fbc_system_id),
+                 "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_SYSTEM_ID)");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target, l_fbc_group_id),
+                 "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_GROUP_ID)");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target, l_fbc_chip_id),
+                 "Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_CHIP_ID)");
+
+        for (auto l_chplt_target : i_target.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_TP |
+                                               fapi2::TARGET_FILTER_ALL_NEST |
+                                               fapi2::TARGET_FILTER_XBUS |
+                                               fapi2::TARGET_FILTER_ALL_OBUS |
+                                               fapi2::TARGET_FILTER_ALL_PCI),
+              fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            fapi2::buffer<uint64_t> l_cplt_conf0;
+            FAPI_TRY(fapi2::getScom(l_chplt_target, PERV_CPLT_CONF0, l_cplt_conf0),
+                     "Error from getScom (PERV_CPLT_CONF0)");
+            l_cplt_conf0.insertFromRight<PERV_1_CPLT_CONF0_TC_UNIT_SYS_ID_DC, PERV_1_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN>
+            (l_fbc_system_id)
+            .insertFromRight<PERV_1_CPLT_CONF0_TC_UNIT_GROUP_ID_DC, PERV_1_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN>(l_fbc_group_id)
+            .insertFromRight<PERV_1_CPLT_CONF0_TC_UNIT_CHIP_ID_DC, PERV_1_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN>(l_fbc_chip_id);
+            FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_CPLT_CONF0, l_cplt_conf0),
+                     "Error from putScom (PERV_CPLT_CONF0)");
+        }
+    }
+
+    // determine base address of chip nm/m/mmmio regions in real address space
+    FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target,
+             l_base_addr_nm0,
+             l_base_addr_nm1,
+             l_base_addr_m,
+             l_base_addr_mmio),
+             "Error from p9_fbc_utils_get_chip_base_address");
+
+    // set XSCOM BAR
+    {
+        fapi2::buffer<uint64_t> l_xscom_bar;
+        uint64_t l_xscom_bar_offset;
+
+        FAPI_DBG("Configuring XSCOM BAR");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET, FAPI_SYSTEM, l_xscom_bar_offset),
+                 "Error from FAPI_ATTR_GET (ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET)");
+
+        l_xscom_bar = l_base_addr_mmio;
+        l_xscom_bar += l_xscom_bar_offset;
+
+        FAPI_ASSERT((l_xscom_bar & XSCOM_BAR_MASK) == 0,
+                    fapi2::P9_SBE_SCOMINIT_XSCOM_BAR_ATTR_ERR().
+                    set_TARGET(i_target).
+                    set_XSCOM_BAR(l_xscom_bar).
+                    set_XSCOM_BAR_OFFSET(l_xscom_bar_offset).
+                    set_BASE_ADDR_MMIO(l_base_addr_mmio),
+                    "Invalid XSCOM BAR configuration!");
+
+        FAPI_TRY(fapi2::putScom(i_target, PU_XSCOM_BASE_REG, l_xscom_bar),
+                 "Error from putScom (PU_XSCOM_BASE_REG)");
+    }
+
+    // set LPC BAR
+    {
+        fapi2::buffer<uint64_t> l_lpc_bar;
+        uint64_t l_lpc_bar_offset;
+
+        FAPI_DBG("Configuring LPC BAR");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET, FAPI_SYSTEM, l_lpc_bar_offset),
+                 "Error from FAPI_ATTR_GET (ATRR_PROC_LPC_BAR_BASE_ADDR_OFFSET");
+
+        l_lpc_bar = l_base_addr_mmio;
+        l_lpc_bar += l_lpc_bar_offset;
+
+        FAPI_ASSERT((l_lpc_bar & LPC_BAR_MASK) == 0,
+                    fapi2::P9_SBE_SCOMINIT_LPC_BAR_ATTR_ERR().
+                    set_TARGET(i_target).
+                    set_LPC_BAR(l_lpc_bar).
+                    set_LPC_BAR_OFFSET(l_lpc_bar_offset).
+                    set_BASE_ADDR_MMIO(l_base_addr_mmio),
+                    "Invalid LPC BAR configuration!");
+
+        FAPI_TRY(fapi2::putScom(i_target, PU_LPC_BASE_REG, l_lpc_bar),
+                 "Error from putScom (PU_LPC_BASE_REG)");
+    }
+
+    // configure FBC FIRs
+    {
+        fapi2::buffer<uint64_t> l_scom_data;
+
+        // CENT
+        FAPI_DBG("Configuring FBC CENT FIR");
+        // clear FIR
+        l_scom_data = 0;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_FIR_REG, l_scom_data),
+                 "Error from putScom (PU_PB_CENT_SM0_PB_CENT_FIR_REG)");
+
+        // configure action/mask
+        l_scom_data = FBC_CENT_FIR_ACTION0;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG, l_scom_data),
+                 "Error from putScom (PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG)");
+
+        l_scom_data = FBC_CENT_FIR_ACTION1;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG, l_scom_data),
+                 "Error from putScom (PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG)");
+
+        l_scom_data = FBC_CENT_FIR_MASK;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG, l_scom_data),
+                 "Error from putScom (PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG)");
+
+        // WEST
+        FAPI_DBG("Configuring FBC WEST FIR");
+        // clear FIR
+        l_scom_data = 0;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_FIR_REG, l_scom_data),
+                 "Error from putScom (PU_PB_WEST_SM0_PB_WEST_FIR_REG)");
+
+        // configure action/mask
+        l_scom_data = FBC_WEST_FIR_ACTION0;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG, l_scom_data),
+                 "Error from putScom (PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG)");
+
+        l_scom_data = FBC_WEST_FIR_ACTION1;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG, l_scom_data),
+                 "Error from putScom (PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG)");
+
+        l_scom_data = FBC_WEST_FIR_MASK;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG, l_scom_data),
+                 "Error from putScom (PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG)");
+
+        // EAST
+        FAPI_DBG("Configuring FBC EAST FIR");
+        // clear FIR
+        l_scom_data = 0;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PB_EAST_FIR_REG, l_scom_data),
+                 "Error from putScom (PU_PB_EAST_FIR_REG)");
+
+        // configure action/mask
+        l_scom_data = FBC_EAST_FIR_ACTION0;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PB_EAST_FIR_ACTION0_REG, l_scom_data),
+                 "Error from putScom (PU_PB_EAST_FIR_ACTION0_REG)");
+
+        l_scom_data = FBC_EAST_FIR_ACTION1;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PB_EAST_FIR_ACTION1_REG, l_scom_data),
+                 "Error from putScom (PU_PB_EAST_FIR_ACTION1_REG)");
+
+        l_scom_data = FBC_EAST_FIR_MASK;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PB_EAST_FIR_MASK_REG, l_scom_data),
+                 "Error from putScom (PU_PB_EAST_FIR_MASK_REG)");
+    }
+
+    // configure PBA FIRs
+    {
+        fapi2::buffer<uint64_t> l_scom_data;
+
+        // clear FIR
+        FAPI_DBG("Configuring PBA FIR");
+        l_scom_data = 0;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIR, l_scom_data),
+                 "Error from putScom (PU_PBAFIR)");
+
+        // configure action/mask
+        l_scom_data = PBA_FIR_ACTION0;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIRACT0, l_scom_data),
+                 "Error from putScom (PU_PBAFIRACT0)");
+
+        l_scom_data = PBA_FIR_ACTION1;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIRACT1, l_scom_data),
+                 "Error from putScom (PU_PBAFIRACT1)");
+
+        l_scom_data = PBA_FIR_MASK;
+        FAPI_TRY(fapi2::putScom(i_target, PU_PBAFIRMASK, l_scom_data),
+                 "Error from putScom (PU_PBAFIRMASK)");
+    }
+
+    // configure chiplet pervasive FIRs / XFIRs
+    {
+        for (auto l_chplt_target : i_target.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_TP |
+                                               fapi2::TARGET_FILTER_ALL_NEST |
+                                               fapi2::TARGET_FILTER_XBUS |
+                                               fapi2::TARGET_FILTER_ALL_OBUS |
+                                               fapi2::TARGET_FILTER_ALL_PCI),
+              fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            uint8_t l_unit_idx;
+            fapi2::buffer<uint64_t> l_scom_data;
+
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_target, l_unit_idx),
+                     "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)");
+            l_unit_idx--;
+
+
+            // PERV LFIR
+            FAPI_DBG("Configuring PERV LFIR (chiplet ID: %02X)", l_unit_idx + 1);
+            // reset pervasive FIR
+            l_scom_data = 0;
+            FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR, l_scom_data),
+                     "Error from putScom (PERV_LOCAL_FIR)");
+
+            // configure pervasive FIR action/mask
+            l_scom_data = PERV_LFIR_ACTION0[l_unit_idx];
+            FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR_ACTION0, l_scom_data),
+                     "Error from putScom (PERV_LOCAL_FIR_ACTION0)");
+
+            l_scom_data = PERV_LFIR_ACTION1[l_unit_idx];
+            FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR_ACTION1, l_scom_data),
+                     "Error from putScom (PERV_LOCAL_FIR_ACTION1)");
+
+            l_scom_data = PERV_LFIR_MASK[l_unit_idx];
+            FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR_MASK, l_scom_data),
+                     "Error from putScom (PERV_LOCAL_FIR_MASK)");
+
+            // XFIR
+            FAPI_DBG("Configuring chiplet XFIR (chiplet ID: %02X)", l_unit_idx + 1);
+            // reset XFIR
+            l_scom_data = 0;
+            FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_XFIR, l_scom_data),
+                     "Error from putScom (PERV_XFIR)");
+
+            // configure XFIR mask
+            l_scom_data = PERV_XFIR_MASK[l_unit_idx];
+            FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_FIR_MASK, l_scom_data),
+                     "Error from putScom (PERV_FIR_MASK");
+        }
+    }
+
+fapi_try_exit:
+    FAPI_DBG("Exiting ...");
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.H
new file mode 100644
index 00000000..4129098e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.H
@@ -0,0 +1,78 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.H $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_sbe_scominit.H
+/// @brief Peform SCOM initialization required for fabric & HBI operation (FAPI2)
+///
+/// @author Joe McGill <jmcgill@us.ibm.com>
+/// @author Christy Graves <clgraves@us.ibm.com>
+///
+
+//
+// *HWP HWP Owner : Joe McGill <jmcgill@us.ibm.com>
+// *HWP FW Owner : Thi N. Tran <thi@us.ibm.com>
+// *HWP Team : Nest
+// *HWP Level : 2
+// *HWP Consumed by : SBE
+//
+
+#ifndef _P9_SBE_SCOMINIT_H_
+#define _P9_SBE_SCOMINIT_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi2.H>
+
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_sbe_scominit_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+///
+/// @brief Set fabric topology IDs for all configured chipets (outside of EC/EP),
+/// performs BAR setup needed for HBI (XSCOM/LPC), configures selected FIRs in
+/// preparation for fabric init
+/// an init command (ttype=pbop.init_all) from the Alter Display Unit (ADU)
+///
+/// @param[in] i_target Reference to processor chip target
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+    fapi2::ReturnCode p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+} // extern "C"
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/Makefile b/src/import/chips/p9/procedures/hwp/perv/Makefile
new file mode 100644
index 00000000..ac2ee6de
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/Makefile
@@ -0,0 +1,55 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/hwp/perv/Makefile $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+# This Makefile compiles all of the core hardware procedure code. See the
+# "pervfiles.mk" file in this directory.
+
+#all generated files from this makefile will end up in obj/perv
+export SUB_OBJDIR = /perv
+
+include img_defs.mk
+include pervfiles.mk
+
+GCC-CFLAGS += -mlongcall
+
+OBJS := $(addprefix $(OBJDIR)/, $(PERV_OBJECTS))
+
+libperv.a: perv
+	$(AR) crs $(OBJDIR)/libperv.a $(OBJDIR)/*.o
+
+.PHONY: clean perv
+perv: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+clean:
+	rm -fr $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d)
+endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C
new file mode 100644
index 00000000..e850723f
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C
@@ -0,0 +1,173 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_hcd_cache_dcc_skewadjust_setup.C
+///
+/// @brief Drop DCCs reset and bypass, Drop skewadjust reset and bypass
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE:SGPE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_hcd_cache_dcc_skewadjust_setup.H"
+#include <p9_perv_scom_addresses.H>
+#include <p9_quad_scom_addresses.H>
+
+
+
+
+fapi2::ReturnCode p9_hcd_cache_dcc_skewadjust_setup(const
+        fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_cache)
+{
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip = i_cache.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+    fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = i_cache.getParent<fapi2::TARGET_TYPE_PERV>();
+    auto l_core_functional_vector = i_cache.getChildren<fapi2::TARGET_TYPE_CORE>(fapi2::TARGET_STATE_FUNCTIONAL);
+    uint8_t l_attr_chip_unit_pos = 0;
+    fapi2::buffer<uint64_t> l_data64;
+
+
+    FAPI_DBG("Entering ...");
+
+    FAPI_DBG("Release L2-0, L2-1 DC Adjust reset");
+    l_data64.flush<1>();
+    l_data64.clearBit<23>();
+    l_data64.clearBit<24>();
+    FAPI_TRY(fapi2::putScom(l_perv, PERV_NET_CTRL1_WAND, l_data64));
+
+    for(auto it : l_core_functional_vector)
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,
+                               it.getParent<fapi2::TARGET_TYPE_PERV>(),
+                               l_attr_chip_unit_pos));
+
+        FAPI_DBG("Release CORE DC Adjust reset");
+        l_data64.flush<1>();
+        l_data64.clearBit<2>();
+        FAPI_TRY(fapi2::putScom(l_chip, (C_NET_CTRL0_WAND + (0x1000000 * (l_attr_chip_unit_pos - 0x20))) ,
+                                l_data64));
+    }
+
+    FAPI_DBG("Scan eq_ana_bndy_bucket_0 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_0, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_0)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_1 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_1, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_1)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_2 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_2, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_2)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_3 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_3, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_3)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_4 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_4, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_4)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_5 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_5, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_5)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_6 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_6, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_6)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_7 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_7, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_7)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_8 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_8, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_8)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_9 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_9, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_9)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_10 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_10, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_10)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_11 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_11, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_11)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_12 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_12, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_12)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_13 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_13, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_13)");
+
+    FAPI_DBG("Release DCC bypass");
+    l_data64.flush<1>();
+    l_data64.clearBit<1>();
+    FAPI_TRY(fapi2::putScom(l_perv, PERV_NET_CTRL1_WAND, l_data64));
+
+    FAPI_DBG("Scan eq_ana_bndy_bucket_14 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_14, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_14)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_15 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_15, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_15)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_16 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_16, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_16)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_17 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_17, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_17)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_18 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_18, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_18)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_19 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_19, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_19)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_20 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_20, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_20)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_21 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_21, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_21)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_22 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_22, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_22)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_23 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_23, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_23)");
+
+    FAPI_DBG("Release Progdly bypass");
+    l_data64.flush<1>();
+    l_data64.clearBit<2>();
+    FAPI_TRY(fapi2::putScom(l_perv, PERV_NET_CTRL1_WAND, l_data64));
+
+    FAPI_DBG("Scan eq_ana_bndy_bucket_24 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_24, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_24)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_25 ring");
+    FAPI_TRY(fapi2::putRing(i_cache, eq_ana_bndy_bucket_25, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_25)");
+
+    FAPI_DBG("Exiting ...");
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.H b/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.H
new file mode 100644
index 00000000..c6a0c6f2
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.H
@@ -0,0 +1,67 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_hcd_cache_dcc_skewadjust_setup.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_hcd_cache_dcc_skewadjust_setup.H
+///
+/// @brief Drop DCCs reset and bypass, Drop skewadjust reset and bypass
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 1
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_HCD_CACHE_DCC_SKEWADJUST_SETUP_H_
+#define _P9_HCD_CACHE_DCC_SKEWADJUST_SETUP_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_hcd_cache_dcc_skewadjust_setup_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_EQ>&);
+
+/// @brief * Start Clocks clock region = AN only
+/// * Drop DCCs reset
+///   Setup 6 DCCs in parallel (commands over scan with setpulse, scan region = ANEP)
+/// * Drop DCCs bypass
+/// * Additional DCC setup step (commands over scan with setpulse, scan region = ANEP)
+/// * Drop SkewAdjust reset
+/// * Setup Skewadjust (commands over scan with setpulse, scan region = ANEP)
+/// * Drop SkewAdjust bypass
+/// * Additional SkewAdjust setup step (commands over scan with setpulse, scan region = ANEP)
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_EQ target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_hcd_cache_dcc_skewadjust_setup(const
+            fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target_chiplet);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C
new file mode 100644
index 00000000..364d4013
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C
@@ -0,0 +1,479 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.C $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_perv_sbe_cmn.C
+///
+/// @brief Modules for scan 0 and array init
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_perv_sbe_cmn.H"
+//## auto_generated
+#include "p9_const_common.H"
+
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
+#include <p9_quad_scom_addresses_fld.H>
+#include <p9_const_common.H>
+
+
+enum P9_PERV_SBE_CMN_Private_Constants
+{
+    P9_OPCG_DONE_SCAN0_POLL_COUNT = 200, // Scan0 Poll count
+    P9_OPCG_DONE_SCAN0_HW_NS_DELAY = 16000, // unit is nano seconds [min : 8k cycles x 4 = 8000/2 x 4 = 16000 x 10(-9) = 16 us
+    //                       max : 8k cycles  =  (8000/25) x 10 (-6) = 320 us]
+    P9_OPCG_DONE_SCAN0_SIM_CYCLE_DELAY = 800000, // unit is cycles, to match the poll count change ( 10000 * 8 )
+    P9_OPCG_DONE_ARRAYINIT_HW_NS_DELAY = 200000, // unit is nano seconds [min : 400k/2 = 200k ns = 200 us
+    //                       max : 200k /25 = 8000 us = 8 ms]
+    P9_OPCG_DONE_ARRAYINIT_POLL_COUNT = 400, // Arrayinit Poll count
+    P9_OPCG_DONE_ARRAYINIT_SIM_CYCLE_DELAY = 1120000 // unit is cycles,to match the poll count change ( 280000 * 4 )
+};
+
+/// @brief Seeprom array Init Module
+/// --ABISTCLK_MUXSEL
+/// --ABIST modes
+/// --Setup BIST regions
+/// --Setup all Clock Regions and Types
+/// --Setup:
+///    - loopcount
+///    - OPCG engine start ABIST
+///    - run-N mode
+/// --Setup IDLE count
+/// --OPCG go
+/// --Poll OPCG done bit to check for completeness
+/// --Clear:
+///    - loopcount
+///    - OPCG engine start ABIST
+///    - run-N mode
+/// --Clear all Clock Regions and Types
+/// --Clear ABISTCLK_MUXSEL
+/// --Clear BIST register
+///
+///
+///
+/// @param[in]     i_target_chiplets           Reference to TARGET_TYPE_PERV target Targets all chiplets
+/// @param[in]     i_regions                   select clk regions
+/// @param[in]     i_loop_counter              loop count value to set opcg run-N mode
+/// @param[in]     i_select_sram               select sram abist mode
+/// @param[in]     i_select_edram              Set edram abist mode
+/// @param[in]     i_start_abist_match_value   match setup idle count value
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_perv_sbe_cmn_array_init_module(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets,
+        const fapi2::buffer<uint16_t> i_regions,
+        const fapi2::buffer<uint64_t> i_loop_counter,
+        const bool i_select_sram,
+        const bool i_select_edram,
+        const fapi2::buffer<uint64_t> i_start_abist_match_value)
+{
+    fapi2::buffer<uint16_t> l_scan_count;
+    fapi2::buffer<uint16_t> l_misr_a_value;
+    fapi2::buffer<uint16_t> l_misr_b_value;
+    fapi2::buffer<uint16_t> l_regions;
+    fapi2::buffer<uint64_t> l_read_reg;
+    bool l_abist_check = false;
+    fapi2::buffer<uint64_t> l_data64;
+    int l_timeout = 0;
+    fapi2::buffer<uint64_t> l_data64_clk_region;
+    FAPI_INF("p9_perv_sbe_cmn_array_init_module: Entering ...");
+
+    i_regions.extractToRight<5, 11>(l_regions);
+
+    FAPI_DBG("Drop vital fence (moved to arrayinit from sacn0 module)");
+    //Setting CPLT_CTRL1 register value
+    l_data64.flush<0>();
+    //CPLT_CTRL1.TC_VITL_REGION_FENCE = 0
+    l_data64.setBit<C_CPLT_CTRL1_TC_VITL_REGION_FENCE>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL1_CLEAR, l_data64));
+
+    FAPI_DBG("Setup ABISTMUX_SEL");
+    //Setting CPLT_CTRL0 register value
+    l_data64.flush<0>();
+    //CPLT_CTRL0.CTRL_CC_ABSTCLK_MUXSEL_DC = 1
+    l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_OR, l_data64));
+
+    FAPI_DBG("setup ABIST modes , BIST REGIONS:%#018lX", i_regions);
+    //Setting BIST register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_BIST, l_data64));
+    l_data64.clearBit<0>();  //BIST.TC_BIST_START_TEST_DC = 0
+    //BIST.TC_SRAM_ABIST_MODE_DC = i_select_sram
+    l_data64.writeBit<PERV_1_BIST_TC_SRAM_ABIST_MODE_DC>(i_select_sram);
+    //BIST.TC_EDRAM_ABIST_MODE_DC = i_select_edram
+    l_data64.writeBit<PERV_1_BIST_TC_EDRAM_ABIST_MODE_DC>(i_select_edram);
+    l_data64.insertFromRight<4, 11>(l_regions);  //BIST.BIST_ALL_UNITS = l_regions
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_BIST, l_data64));
+    FAPI_DBG("l_data64 value:%#018lX", l_data64);
+
+    FAPI_DBG("Setup all Clock Domains and Clock Types");
+    //Setting CLK_REGION register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CLK_REGION,
+                            l_data64_clk_region));
+    //CLK_REGION.CLOCK_REGION_ALL_UNITS = l_regions
+    l_data64_clk_region.insertFromRight<4, 11>(l_regions);
+    l_data64_clk_region.setBit<48, 3>();  //CLK_REGION.SEL_THOLD_ALL = 0b111
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CLK_REGION,
+                            l_data64_clk_region));
+
+    FAPI_DBG("Drop Region fences");
+    //Setting CPLT_CTRL1 register value
+    l_data64.flush<0>();
+    //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = l_regions
+    l_data64.insertFromRight<4, 11>(l_regions);
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL1_CLEAR, l_data64));
+
+    FAPI_DBG("Setup: loopcount , OPCG engine start ABIST, run-N mode");
+    //Setting OPCG_REG0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG0, l_data64));
+    l_data64.setBit<PERV_1_OPCG_REG0_RUNN_MODE>();  //OPCG_REG0.RUNN_MODE = 1
+    l_data64.setBit<14>();  //OPCG_REG0.OPCG_STARTS_BIST = 1
+    l_data64.insertFromRight<PERV_1_OPCG_REG0_LOOP_COUNT, PERV_1_OPCG_REG0_LOOP_COUNT_LEN>((
+                uint64_t)(i_loop_counter));  //OPCG_REG0.LOOP_COUNT = i_loop_counter
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG0, l_data64));
+
+    i_start_abist_match_value.extractToRight<0, 12>(l_scan_count);
+    i_start_abist_match_value.extractToRight<12, 12>(l_misr_a_value);
+    i_start_abist_match_value.extractToRight<24, 12>(l_misr_b_value);
+
+    FAPI_DBG("Setup IDLE count");
+    //Setting OPCG_REG1 register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG1, l_data64));
+    l_data64.insertFromRight<PERV_1_OPCG_REG1_SCAN_COUNT, PERV_1_OPCG_REG1_SCAN_COUNT_LEN>
+    (l_scan_count);  //OPCG_REG1.SCAN_COUNT = l_scan_count
+    l_data64.insertFromRight<PERV_1_OPCG_REG1_MISR_A_VAL, PERV_1_OPCG_REG1_MISR_A_VAL_LEN>
+    (l_misr_a_value);  //OPCG_REG1.MISR_A_VAL = l_misr_a_value
+    l_data64.insertFromRight<PERV_1_OPCG_REG1_MISR_B_VAL, PERV_1_OPCG_REG1_MISR_B_VAL_LEN>
+    (l_misr_b_value);  //OPCG_REG1.MISR_B_VAL = l_misr_b_value
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG1, l_data64));
+
+    FAPI_DBG("opcg go");
+    //Setting OPCG_REG0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG0, l_data64));
+    l_data64.setBit<1>();  //OPCG_REG0.OPCG_GO = 1
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG0, l_data64));
+
+    FAPI_DBG("Poll OPCG done bit to check for run-N completeness");
+    l_timeout = P9_OPCG_DONE_ARRAYINIT_POLL_COUNT;
+
+    //UNTIL CPLT_STAT0.CC_CTRL_OPCG_DONE_DC == 1
+    while (l_timeout != 0)
+    {
+        //Getting CPLT_STAT0 register value
+        FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CPLT_STAT0, l_data64));
+        bool l_poll_data =
+            l_data64.getBit<PERV_1_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC>();  //bool l_poll_data = CPLT_STAT0.CC_CTRL_OPCG_DONE_DC
+
+        if (l_poll_data == 1)
+        {
+            break;
+        }
+
+        fapi2::delay(P9_OPCG_DONE_ARRAYINIT_HW_NS_DELAY,
+                     P9_OPCG_DONE_ARRAYINIT_SIM_CYCLE_DELAY);
+        --l_timeout;
+    }
+
+    FAPI_DBG("Loop Count :%d", l_timeout);
+
+    FAPI_ASSERT(l_timeout > 0,
+                fapi2::SBE_ARRAYINIT_POLL_THRESHOLD_ERR(),
+                "ERROR:OPCG DONE BIT NOT SET");
+
+    //Getting CPLT_STAT0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CPLT_STAT0,
+                            l_read_reg)); //l_read_reg = CPLT_STAT0
+
+    if ( i_select_sram )
+    {
+        FAPI_DBG("Checking sram abist done");
+        FAPI_ASSERT(l_read_reg.getBit<0>() == 1,
+                    fapi2::SRAM_ABIST_DONE_BIT_ERR()
+                    .set_READ_ABIST_DONE(l_abist_check),
+                    "ERROR:SRAM_ABIST_DONE_BIT_NOT_SET");
+    }
+
+    if ( i_select_edram )
+    {
+        FAPI_DBG("Checking edram abist done");
+        FAPI_ASSERT(l_read_reg.getBit<1>() == 1,
+                    fapi2::EDRAM_ABIST_DONE_BIT_ERR()
+                    .set_READ_ABIST_DONE(l_abist_check),
+                    "ERROR:EDRAM_ABIST_DONE_BIT_NOT_SET");
+    }
+
+    //oaim_poll_done
+    {
+        FAPI_DBG("OPCG done, clear Run-N mode");
+        //Setting OPCG_REG0 register value
+        FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG0, l_data64));
+        l_data64.clearBit<PERV_1_OPCG_REG0_RUNN_MODE>();  //OPCG_REG0.RUNN_MODE = 0
+        l_data64.clearBit<14>();  //OPCG_REG0.OPCG_STARTS_BIST = 0
+        l_data64.clearBit<PERV_1_OPCG_REG0_LOOP_COUNT, PERV_1_OPCG_REG0_LOOP_COUNT_LEN>();  //OPCG_REG0.LOOP_COUNT = 0
+        FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG0, l_data64));
+
+        FAPI_DBG("clear all clock REGIONS and type");
+        //Setting CLK_REGION register value
+        //CLK_REGION = 0
+        l_data64_clk_region = 0;  //using variable to keep register data
+        FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CLK_REGION,
+                                l_data64_clk_region));
+
+        FAPI_DBG("clear ABISTCLK_MUXSEL");
+        //Setting CPLT_CTRL0 register value
+        l_data64.flush<0>();
+        //CPLT_CTRL0.CTRL_CC_ABSTCLK_MUXSEL_DC = 0
+        l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_CLEAR, l_data64));
+
+        FAPI_DBG("clear BIST REGISTER");
+        //Setting BIST register value
+        //BIST = 0
+        FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_BIST, 0));
+    }
+
+    FAPI_INF("p9_perv_sbe_cmn_array_init_module: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Region value settings
+///
+/// @param[in]     i_target_chip     Reference to TARGET_TYPE_PERV target ATTR_PG of the corresponding chiplet
+/// @param[in]     i_regions_value   regions except vital and pll
+/// @param[out]    o_regions_value   regions value
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_perv_sbe_cmn_regions_setup_16(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip,
+        const fapi2::buffer<uint16_t> i_regions_value,
+        fapi2::buffer<uint16_t>& o_regions_value)
+{
+    fapi2::buffer<uint32_t> l_read_attr = 0;
+    fapi2::buffer<uint32_t> l_read_attr_invert = 0;
+    fapi2::buffer<uint32_t> l_read_attr_shift1_right = 0;
+    FAPI_INF("p9_perv_sbe_cmn_regions_setup_16: Entering ...");
+
+    FAPI_DBG("Reading ATTR_PG");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chip, l_read_attr));
+    FAPI_DBG("ATTR_PG Value : %#018lX", l_read_attr);
+
+    FAPI_DBG("i_regions_value input from calling function: %#018lX",
+             i_regions_value);
+
+    if ( l_read_attr == 0x0 )
+    {
+        o_regions_value = i_regions_value;
+    }
+    else
+    {
+        l_read_attr_invert = l_read_attr.invert();
+        FAPI_DBG("ATTR_PG inverted: %#018lX", l_read_attr_invert);
+        l_read_attr_shift1_right = (l_read_attr_invert >> 1);
+        FAPI_DBG("ATTR_PG inverted and shifted right by 1 %#018lX",
+                 l_read_attr_shift1_right);
+
+        o_regions_value = (i_regions_value & l_read_attr_shift1_right);
+    }
+
+    FAPI_INF("p9_perv_sbe_cmn_regions_setup_16: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Region value settings
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_regions_value    regions except vital and pll
+/// @param[out]    o_regions_value    Regions value
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_perv_sbe_cmn_regions_setup_64(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+        const fapi2::buffer<uint16_t> i_regions_value,
+        fapi2::buffer<uint64_t>& o_regions_value)
+{
+    fapi2::buffer<uint32_t> l_read_attr = 0;
+    fapi2::buffer<uint32_t> l_read_attr_invert = 0;
+    fapi2::buffer<uint32_t> l_read_attr_shift1_right = 0;
+    fapi2::buffer<uint64_t> l_temp = 0;
+    FAPI_INF("p9_perv_sbe_cmn_regions_setup_64: Entering ...");
+
+    FAPI_DBG("Reading ATTR_PG");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, l_read_attr));
+    FAPI_DBG("ATTR_PG Value : %#018lX", l_read_attr);
+
+    FAPI_DBG("i_regions_value input from calling function: %#018lX",
+             i_regions_value);
+
+    if ( l_read_attr == 0x0 )
+    {
+        o_regions_value = (i_regions_value | l_temp);
+    }
+    else
+    {
+        l_read_attr_invert = l_read_attr.invert();
+        FAPI_DBG("ATTR_PG inverted: %#018lX", l_read_attr_invert);
+        l_read_attr_shift1_right = (l_read_attr_invert >> 1);
+        FAPI_DBG("ATTR_PG inverted and shifted right by 1 %#018lX",
+                 l_read_attr_shift1_right);
+
+        o_regions_value = (i_regions_value & l_read_attr_shift1_right);
+    }
+
+    FAPI_INF("p9_perv_sbe_cmn_regions_setup_64: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Seeprom scan0 module
+/// --Raise VITAL clock region fence
+/// --Write Clock Region Register
+/// --Write Scan Select Register
+/// --set OPCG_REG0 register bit 0='0'
+/// --set OPCG_REG0 register bit 2 = '1'
+/// --Poll OPCG done bit to check for scan0 completeness
+/// --clear clock region register
+/// --clear scan select register
+/// --Drop VITAL fence
+///
+///
+/// @param[in]     i_target_chiplets   Reference to TARGET_TYPE_PERV target Targets for all chiplets
+/// @param[in]     i_regions           set the clk region
+/// @param[in]     i_scan_types        set scan types region
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_perv_sbe_cmn_scan0_module(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets,
+        const fapi2::buffer<uint16_t> i_regions,
+        const fapi2::buffer<uint16_t> i_scan_types)
+{
+    fapi2::buffer<uint16_t> l_regions;
+    fapi2::buffer<uint16_t> l_scan_types;
+    fapi2::buffer<uint64_t> l_data64;
+    int l_timeout = 0;
+    FAPI_INF("p9_perv_sbe_cmn_scan0_module: Entering ...");
+
+    i_regions.extractToRight<5, 11>(l_regions);
+    i_scan_types.extractToRight<4, 12>(l_scan_types);
+
+    FAPI_DBG("raise Vital clock region fence");
+    //Setting CPLT_CTRL1 register value
+    l_data64.flush<0>();
+    //CPLT_CTRL1.TC_VITL_REGION_FENCE = 1
+    l_data64.setBit<C_CPLT_CTRL1_TC_VITL_REGION_FENCE>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL1_OR, l_data64));
+
+    FAPI_DBG("Raise region fences for scanned regions");
+    //Setting CPLT_CTRL1 register value
+    l_data64.flush<0>();
+    l_data64.setBit<4, 11>();  //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = 0b11111111111
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL1_OR, l_data64));
+
+    FAPI_DBG("Setup all Clock Domains and Clock Types");
+    //Setting CLK_REGION register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CLK_REGION, l_data64));
+    //CLK_REGION.CLOCK_REGION_ALL_UNITS = l_regions
+    l_data64.insertFromRight<4, 11>(l_regions);
+    l_data64.setBit<48, 3>();  //CLK_REGION.SEL_THOLD_ALL = 0b111
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CLK_REGION, l_data64));
+
+    FAPI_DBG("Write scan select register");
+    //Setting SCAN_REGION_TYPE register value
+    l_data64.flush<0>();  //SCAN_REGION_TYPE = 0
+    //SCAN_REGION_TYPE.SCAN_REGION_ALL_UNITS = l_regions
+    l_data64.insertFromRight<4, 11>(l_regions);
+    //SCAN_REGION_TYPE.SCAN_ALL_TYPES = l_scan_types
+    l_data64.insertFromRight<48, 12>(l_scan_types);
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SCAN_REGION_TYPE, l_data64));
+
+    FAPI_DBG("set OPCG_REG0 register bit 0='0'");
+    //Setting OPCG_REG0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG0, l_data64));
+    l_data64.clearBit<PERV_1_OPCG_REG0_RUNN_MODE>();  //OPCG_REG0.RUNN_MODE = 0
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG0, l_data64));
+
+    FAPI_DBG("trigger Scan0");
+    //Setting OPCG_REG0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_REG0, l_data64));
+    l_data64.setBit<PERV_1_OPCG_REG0_RUN_SCAN0>();  //OPCG_REG0.RUN_SCAN0 = 1
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_REG0, l_data64));
+
+    FAPI_DBG("Poll OPCG done bit to check for run-N completeness");
+    l_timeout = P9_OPCG_DONE_SCAN0_POLL_COUNT;
+
+    //UNTIL CPLT_STAT0.CC_CTRL_OPCG_DONE_DC == 1
+    while (l_timeout != 0)
+    {
+        //Getting CPLT_STAT0 register value
+        FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CPLT_STAT0, l_data64));
+        bool l_poll_data =
+            l_data64.getBit<PERV_1_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC>();  //bool l_poll_data = CPLT_STAT0.CC_CTRL_OPCG_DONE_DC
+
+        if (l_poll_data == 1)
+        {
+            break;
+        }
+
+        fapi2::delay(P9_OPCG_DONE_SCAN0_HW_NS_DELAY,
+                     P9_OPCG_DONE_SCAN0_SIM_CYCLE_DELAY);
+        --l_timeout;
+    }
+
+    FAPI_DBG("Loop Count :%d", l_timeout);
+
+    FAPI_ASSERT(l_timeout > 0,
+                fapi2::SBE_SCAN0_DONE_POLL_THRESHOLD_ERR(),
+                "ERROR:OPCG DONE BIT NOT SET");
+
+    //os0m_poll_done
+    {
+        FAPI_DBG("clear all clock REGIONS and type");
+        //Setting CLK_REGION register value
+        //CLK_REGION = 0
+        FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CLK_REGION, 0));
+
+        FAPI_DBG("Clear Scan Select Register");
+        //Setting SCAN_REGION_TYPE register value
+        //SCAN_REGION_TYPE = 0
+        FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SCAN_REGION_TYPE, 0));
+    }
+
+    FAPI_INF("p9_perv_sbe_cmn_scan0_module: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H
new file mode 100644
index 00000000..b2472eb3
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H
@@ -0,0 +1,69 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_perv_sbe_cmn.H $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_perv_sbe_cmn.H
+///
+/// @brief Modules for scan 0 and array init
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_PERV_SBE_CMN_H_
+#define _P9_PERV_SBE_CMN_H_
+
+
+#include <fapi2.H>
+
+
+fapi2::ReturnCode p9_perv_sbe_cmn_array_init_module(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets,
+        const fapi2::buffer<uint16_t> i_regions,
+        const fapi2::buffer<uint64_t> i_loop_counter,
+        const bool i_select_sram,
+        const bool i_select_edram,
+        const fapi2::buffer<uint64_t> i_start_abist_match_value);
+
+fapi2::ReturnCode p9_perv_sbe_cmn_regions_setup_16(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip,
+        const fapi2::buffer<uint16_t> i_regions_value,
+        fapi2::buffer<uint16_t>& o_regions_value);
+
+fapi2::ReturnCode p9_perv_sbe_cmn_regions_setup_64(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+        const fapi2::buffer<uint16_t> i_regions_value,
+        fapi2::buffer<uint64_t>& o_regions_value);
+
+fapi2::ReturnCode p9_perv_sbe_cmn_scan0_module(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets,
+        const fapi2::buffer<uint16_t> i_regions,
+        const fapi2::buffer<uint16_t> i_scan_types);
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C
new file mode 100644
index 00000000..d11fe6bf
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C
@@ -0,0 +1,950 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_ram_core.C $           */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------------
+///
+/// @file p9_ram_core.C
+/// @brief Class that implements the base ramming capability
+///
+//-----------------------------------------------------------------------------------
+// *HWP HWP Owner        : Liu Yang Fan <shliuyf@cn.ibm.com>
+// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com>
+// *HWP FW Owner         : Thi Tran <thi@us.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
+//-----------------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------------
+#include <p9_ram_core.H>
+#include "p9_quad_scom_addresses.H"
+#include "p9_quad_scom_addresses_fld.H"
+
+// identifiers for special registers
+const uint32_t RAM_REG_NIA   = 2000;
+const uint32_t RAM_REG_MSR   = 2001;
+const uint32_t RAM_REG_CR    = 2002;
+const uint32_t RAM_REG_FPSCR = 2003;
+
+// opcode for ramming
+const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_SPRD      = 0x7C1543A6;
+const uint32_t OPCODE_MTSPR_FROM_GPR1_TO_SPRD      = 0x7C3543A6;
+const uint32_t OPCODE_MFSPR_FROM_SPRD_TO_GPR0      = 0x7C1542A6;
+const uint32_t OPCODE_MFSPR_FROM_SPRD_TO_GPR1      = 0x7C3542A6;
+const uint32_t OPCODE_MFSPR_FROM_SPR0_TO_GPR0      = 0x7C0002A6;
+const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_SPR0      = 0x7C0003A6;
+const uint32_t OPCODE_MFFPRD_FROM_FPR0_TO_GPR0     = 0x7C000066;
+const uint32_t OPCODE_MTFPRD_FROM_GPR0_TO_FPR0     = 0x7C000166;
+const uint32_t OPCODE_MFVSRD_FROM_VSR0_TO_GPR0     = 0x7C000066;
+const uint32_t OPCODE_MFVSRD_FROM_VSR32_TO_GPR0    = 0x7C000067;
+const uint32_t OPCODE_MFVSRLD_FROM_VSR0_TO_GPR0    = 0x7C000266;
+const uint32_t OPCODE_MFVSRLD_FROM_VSR32_TO_GPR0   = 0x7C000267;
+const uint32_t OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR0  = 0x7C010366;
+const uint32_t OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR32 = 0x7C010367;
+const uint32_t OPCODE_MFSPR_FROM_LR_TO_GPR0        = 0x7C0802A6;
+const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_LR        = 0x7C0803A6;
+const uint32_t OPCODE_MTMSR_L0                     = 0x7C000124;
+const uint32_t OPCODE_MTMSRD_L0                    = 0x7C000164;
+const uint32_t OPCODE_MTSPR_IAMR                   = 0x7C1D0BA6;
+const uint32_t OPCODE_MTSPR_PIDR                   = 0x7C100BA6;
+const uint32_t OPCODE_MTSPR_LPIDR                  = 0x7C1F4BA6;
+const uint32_t OPCODE_MTSPR_LPCR                   = 0x7C1E4BA6;
+const uint32_t OPCODE_MTSPR_MMCRA                  = 0x7C12C3A6;
+const uint32_t OPCODE_MTSPR_MMCR1                  = 0x7C1EC3A6;
+const uint32_t OPCODE_MTSPR_SEIDBAR                = 0x7C1F7BA6;
+const uint32_t OPCODE_MTSPR_XER                    = 0x7C0103A6;
+const uint32_t OPCODE_MFSPR_XER                    = 0x7C0102A6;
+const uint32_t OPCODE_MFFS                         = 0xFC00048E;
+const uint32_t OPCODE_SLBMFEE                      = 0x7C000726;
+const uint32_t OPCODE_SLBMFEV                      = 0x7C0006A6;
+const uint32_t OPCODE_DCBZ                         = 0x7C0007EC;
+const uint32_t OPCODE_DCBF                         = 0x7C0000AC;
+const uint32_t OPCODE_LD                           = 0xE8000000;
+const uint32_t OPCODE_STD                          = 0xF8000000;
+const uint32_t OPCODE_LFD                          = 0xC8000000;
+const uint32_t OPCODE_STFD                         = 0xD8000000;
+const uint32_t OPCODE_LVX                          = 0x7C0000CE;
+const uint32_t OPCODE_STVX                         = 0x7C0001CE;
+const uint32_t OPCODE_LXVD2X                       = 0x7C000698;
+const uint32_t OPCODE_STXVD2X                      = 0x7C000798;
+const uint32_t OPCODE_MFMSR_TO_GPR0                = 0x7C0000A6;
+const uint32_t OPCODE_MFCR_TO_GPR0                 = 0x7C000026;
+const uint32_t OPCODE_MTCRF_FROM_GPR0              = 0x7C0FF120;
+const uint32_t OPCODE_MTFSF_FROM_GPR0              = 0xFE00058E;
+
+// TODO: make sure these special PPC are final version in PC workbook table 9-2
+const uint32_t OPCODE_MFNIA_RT                     = 0x001ac804;
+const uint32_t OPCODE_MTNIA_LR                     = 0x4c1e00a4;
+const uint32_t OPCODE_GPR_MOVE                     = 0x00000010;
+const uint32_t OPCODE_VSR_MOVE_HI                  = 0x00000110;
+const uint32_t OPCODE_VSR_MOVE_LO                  = 0x00000210;
+const uint32_t OPCODE_XER_MOVE                     = 0x00000310;
+const uint32_t OPCODE_CR_MOVE                      = 0x00000410;
+
+// poll count for check ram status
+const uint32_t RAM_CORE_STAT_POLL_CNT = 10;
+
+// Scom register field
+// TODO: replace the const with FLD macro define when it's ready
+const uint32_t C_RAM_MODEREG_ENABLE                = 0;
+const uint32_t C_RAS_STATUS_CORE_MAINT             = 0;
+const uint32_t C_THREAD_INFO_VTID0_ACTIVE          = 0;
+const uint32_t C_RAM_CTRL_VTID                     = 0;
+const uint32_t C_RAM_CTRL_VTID_LEN                 = 2;
+const uint32_t C_RAM_CTRL_PREDECODE                = 2;
+const uint32_t C_RAM_CTRL_PREDECODE_LEN            = 4;
+const uint32_t C_RAM_CTRL_INSTRUCTION              = 8;
+const uint32_t C_RAM_CTRL_INSTRUCTION_LEN          = 32;
+const uint32_t C_RAM_STATUS_ACCESS_DURING_RECOVERY = 0;
+const uint32_t C_RAM_STATUS_COMPLETION             = 1;
+const uint32_t C_RAM_STATUS_EXCEPTION              = 2;
+const uint32_t C_RAM_STATUS_LSU_EMPTY              = 3;
+
+//-----------------------------------------------------------------------------------
+// Function definitions
+//-----------------------------------------------------------------------------------
+RamCore::RamCore(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, const uint8_t i_thread)
+{
+    iv_target = i_target;
+    iv_thread = i_thread;
+    iv_ram_enable    = false;
+    iv_ram_scr0_save = false;
+    iv_ram_setup     = false;
+    iv_ram_err       = false;
+    iv_write_gpr0    = false;
+    iv_write_gpr1    = false;
+    iv_backup_buf0   = 0;
+    iv_backup_buf1   = 0;
+    iv_backup_buf2   = 0;
+}
+
+RamCore::~RamCore()
+{
+    if(iv_ram_setup)
+    {
+        FAPI_ERR("RamCore Destructor error: Ram is still in active state!!!");
+    }
+}
+
+//-----------------------------------------------------------------------------------
+fapi2::ReturnCode RamCore::ram_setup()
+{
+    FAPI_DBG("Start ram setup");
+    fapi2::buffer<uint64_t> l_data = 0;
+    uint32_t l_opcode = 0;
+    bool l_thread_active = false;
+    uint8_t l_thread_stop = 0;
+
+    // set RAM_MODEREG Scom to enable RAM mode
+    FAPI_TRY(fapi2::getScom(iv_target, C_RAM_MODEREG, l_data));
+    l_data.setBit<C_RAM_MODEREG_ENABLE>();
+    FAPI_TRY(fapi2::putScom(iv_target, C_RAM_MODEREG, l_data));
+
+    // read RAS_STATUS Scom to check the thread is stopped for ramming
+    l_data.flush<0>();
+    FAPI_TRY(fapi2::getScom(iv_target, C_RAS_STATUS, l_data));
+    FAPI_DBG("RAS_STATUS:%#lx", l_data());
+    FAPI_TRY(l_data.extractToRight(l_thread_stop, C_RAS_STATUS_CORE_MAINT + 8 * iv_thread, 2));
+
+    FAPI_ASSERT(l_thread_stop == 3,
+                fapi2::P9_RAM_THREAD_NOT_STOP_ERR()
+                .set_THREAD(iv_thread),
+                "Thread to perform ram is not stopped");
+
+    // read THREAD_INFO Scom to check the thread is active for ramming
+    l_data.flush<0>();
+    FAPI_TRY(fapi2::getScom(iv_target, C_THREAD_INFO, l_data));
+    FAPI_DBG("THREAD_INFO:%#lx", l_data());
+    FAPI_TRY(l_data.extractToRight(l_thread_active, C_THREAD_INFO_VTID0_ACTIVE + iv_thread, 1));
+
+    FAPI_ASSERT(l_thread_active,
+                fapi2::P9_RAM_THREAD_INACTIVE_ERR()
+                .set_THREAD(iv_thread),
+                "Thread to perform ram is inactive");
+
+    iv_ram_enable = true;
+
+    // backup registers SCR0/GPR0/GPR1/LR
+    //SCR0->iv_backup_buf0
+    FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, iv_backup_buf0));
+    iv_ram_scr0_save = true;
+
+    //GPR0->iv_backup_buf1
+    //1.setup SPRC to use SCRO as SPRD
+    l_data.flush<0>();
+    FAPI_TRY(fapi2::getScom(iv_target, C_SPR_MODE, l_data));
+    FAPI_TRY(l_data.setBit(C_SPR_MODE_MODEREG_SPRC_LT0_SEL + iv_thread));
+    FAPI_TRY(fapi2::putScom(iv_target, C_SPR_MODE, l_data));
+    l_data.flush<0>();
+    FAPI_TRY(fapi2::getScom(iv_target, C_SCOMC, l_data));
+    l_data.insertFromRight<C_SCOMC_MODE, C_SCOMC_MODE_LEN>(0);
+    FAPI_TRY(fapi2::putScom(iv_target, C_SCOMC, l_data));
+
+    //2.create mtsprd<gpr0> opcode, ram into thread to get GPR0
+    l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD;
+    FAPI_TRY(ram_opcode(l_opcode, true));
+
+    //3.get GPR0 from SCR0
+    FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, iv_backup_buf1));
+
+    //GPR1->iv_backup_buf2
+    //1.create mtsprd<gpr1> opcode, ram into thread to get GPR1
+    l_opcode = OPCODE_MTSPR_FROM_GPR1_TO_SPRD;
+    FAPI_TRY(ram_opcode(l_opcode, true));
+
+    //2.get GPR1 from SCR0
+    FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, iv_backup_buf2));
+
+    iv_ram_setup = true;
+
+fapi_try_exit:
+
+    // Error happened and SCR0 saved, to restore SCR0
+    // Do not use "FAPI_TRY" to avoid endless loop
+    if((fapi2::current_err != fapi2::FAPI2_RC_SUCCESS) && iv_ram_scr0_save)
+    {
+        fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0);
+    }
+
+    FAPI_DBG("Exiting ram setup");
+    return fapi2::current_err;
+}
+
+//-----------------------------------------------------------------------------------
+fapi2::ReturnCode RamCore::ram_cleanup()
+{
+    FAPI_DBG("Start ram cleanup");
+    uint32_t l_opcode = 0;
+    fapi2::buffer<uint64_t> l_data = 0;
+
+    FAPI_ASSERT(iv_ram_setup,
+                fapi2::P9_RAM_NOT_SETUP_ERR(),
+                "Attempting to cleanup ram without setup before");
+
+    // setup SPRC to use SCRO as SPRD
+    FAPI_TRY(fapi2::getScom(iv_target, C_SPR_MODE, l_data));
+    FAPI_TRY(l_data.setBit(C_SPR_MODE_MODEREG_SPRC_LT0_SEL + iv_thread));
+    FAPI_TRY(fapi2::putScom(iv_target, C_SPR_MODE, l_data));
+    l_data.flush<0>();
+    FAPI_TRY(fapi2::getScom(iv_target, C_SCOMC, l_data));
+    l_data.insertFromRight<C_SCOMC_MODE, C_SCOMC_MODE_LEN>(0);
+    FAPI_TRY(fapi2::putScom(iv_target, C_SCOMC, l_data));
+
+    // restore GPR1
+    if(!iv_write_gpr1)
+    {
+        //iv_backup_buf2->GPR1
+        //1.put restore data into SCR0
+        FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf2));
+
+        //2.create mfsprd<gpr1> opcode, ram into thread to restore GPR1
+        l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR1;
+        FAPI_TRY(ram_opcode(l_opcode, true));
+    }
+
+    // restore GPR0
+    if(!iv_write_gpr0)
+    {
+        //iv_backup_buf1->GPR0
+        //1.put restore data into SCR0
+        FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf1));
+
+        //2.create mfsprd<gpr0> opcode, ram into thread to restore GPR0
+        l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0;
+        FAPI_TRY(ram_opcode(l_opcode, true));
+    }
+
+    //iv_backup_buf0->SCR0
+    FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, iv_backup_buf0));
+
+    // set RAM_MODEREG Scom to clear RAM mode
+    l_data.flush<0>();
+    FAPI_TRY(fapi2::getScom(iv_target, C_RAM_MODEREG, l_data));
+    l_data.clearBit<C_RAM_MODEREG_ENABLE>();
+    FAPI_TRY(fapi2::putScom(iv_target, C_RAM_MODEREG, l_data));
+
+    iv_ram_enable    = false;
+    iv_ram_scr0_save = false;
+    iv_ram_setup     = false;
+    iv_write_gpr0    = false;
+    iv_write_gpr1    = false;
+
+fapi_try_exit:
+    FAPI_DBG("Exiting ram cleanup");
+    return fapi2::current_err;
+}
+
+//-----------------------------------------------------------------------------------
+fapi2::ReturnCode RamCore::ram_opcode(const uint32_t i_opcode, const bool i_allow_mult)
+{
+    FAPI_DBG("Start ram opcode");
+    fapi2::buffer<uint64_t> l_data = 0;
+    uint8_t  l_predecode = 0;
+    uint32_t l_poll_count = RAM_CORE_STAT_POLL_CNT;
+    bool l_is_load_store = false;
+
+    // check the opcode for load/store
+    l_is_load_store = is_load_store(i_opcode);
+
+    // ram_setup
+    if(!i_allow_mult)
+    {
+        FAPI_TRY(ram_setup());
+    }
+
+    FAPI_ASSERT(iv_ram_enable,
+                fapi2::P9_RAM_NOT_SETUP_ERR(),
+                "Attempting to ram opcode without enable RAM mode before");
+
+    // write RAM_CTRL Scom for ramming the opcode
+    l_data.insertFromRight<C_RAM_CTRL_VTID, C_RAM_CTRL_VTID_LEN>(iv_thread);
+    l_predecode = gen_predecode(i_opcode);
+    l_data.insertFromRight<C_RAM_CTRL_PREDECODE, C_RAM_CTRL_PREDECODE_LEN>(l_predecode);
+    l_data.insertFromRight<C_RAM_CTRL_INSTRUCTION, C_RAM_CTRL_INSTRUCTION_LEN>(i_opcode);
+    FAPI_TRY(fapi2::putScom(iv_target, C_RAM_CTRL, l_data));
+
+    // poll RAM_STATUS_REG Scom for the completion
+    l_data.flush<0>();
+
+    while(1)
+    {
+        FAPI_TRY(fapi2::getScom(iv_target, C_RAM_STATUS, l_data));
+
+        // attempting to ram during recovery
+        FAPI_ASSERT(!l_data.getBit<C_RAM_STATUS_ACCESS_DURING_RECOVERY>(),
+                    fapi2::P9_RAM_STATUS_IN_RECOVERY_ERR(),
+                    "Attempting to ram during recovery");
+
+        // exception or interrupt
+        FAPI_ASSERT(!l_data.getBit<C_RAM_STATUS_EXCEPTION>(),
+                    fapi2::P9_RAM_STATUS_EXCEPTION_ERR(),
+                    "Exception or interrupt happened during ramming");
+
+        // load/store opcode need to check LSU empty and PPC complete
+        if (l_is_load_store)
+        {
+            if(l_data.getBit<C_RAM_STATUS_COMPLETION>() && l_data.getBit<C_RAM_STATUS_LSU_EMPTY>())
+            {
+                FAPI_DBG("ram_opcode:: RAM is done");
+                break;
+            }
+        }
+        else
+        {
+            if(l_data.getBit<C_RAM_STATUS_COMPLETION>())
+            {
+                FAPI_DBG("ram_opcode:: RAM is done");
+                break;
+            }
+        }
+
+        --l_poll_count;
+
+        FAPI_ASSERT(l_poll_count > 0,
+                    fapi2::P9_RAM_STATUS_POLL_THRESHOLD_ERR(),
+                    "Timeout for ram to complete, poll count expired");
+    }
+
+    // ram_cleanup
+    if(!i_allow_mult)
+    {
+        FAPI_TRY(ram_cleanup());
+    }
+
+fapi_try_exit:
+
+    if(fapi2::current_err != fapi2::FAPI2_RC_SUCCESS)
+    {
+        iv_ram_err = true;
+    }
+
+    FAPI_DBG("Exiting ram opcode");
+    return fapi2::current_err;
+}
+
+//-----------------------------------------------------------------------------------
+uint8_t RamCore::gen_predecode(const uint32_t i_opcode)
+{
+    //TODO: make sure they are final version in PC workbook table 9-1 and 9-2
+    uint8_t  l_predecode = 0;
+    uint32_t l_opcode_pattern0 = i_opcode & 0xFC0007FE;
+    uint32_t l_opcode_pattern1 = i_opcode & 0xFC1FFFFE;
+
+    if((i_opcode == OPCODE_MFNIA_RT)    ||
+       (i_opcode == OPCODE_GPR_MOVE)    ||
+       (i_opcode == OPCODE_VSR_MOVE_HI) ||
+       (i_opcode == OPCODE_VSR_MOVE_LO) ||
+       (i_opcode == OPCODE_XER_MOVE)    ||
+       (i_opcode == OPCODE_CR_MOVE))
+    {
+        l_predecode = 2;
+    }
+    else if((i_opcode == OPCODE_MTNIA_LR)             ||
+            (l_opcode_pattern0 == OPCODE_MTMSR_L0)    ||
+            (l_opcode_pattern0 == OPCODE_MTMSRD_L0))
+    {
+        l_predecode = 8;
+    }
+    else if((l_opcode_pattern1 == OPCODE_MTSPR_IAMR)    ||
+            (l_opcode_pattern1 == OPCODE_MTSPR_PIDR)    ||
+            (l_opcode_pattern1 == OPCODE_MTSPR_LPIDR)   ||
+            (l_opcode_pattern1 == OPCODE_MTSPR_LPCR)    ||
+            (l_opcode_pattern1 == OPCODE_MTSPR_MMCRA)   ||
+            (l_opcode_pattern1 == OPCODE_MTSPR_MMCR1)   ||
+            (l_opcode_pattern1 == OPCODE_MTSPR_SEIDBAR) ||
+            (l_opcode_pattern1 == OPCODE_MTSPR_XER)     ||
+            (l_opcode_pattern1 == OPCODE_MFSPR_XER)     ||
+            (l_opcode_pattern0 == OPCODE_MFFS)          ||
+            (l_opcode_pattern0 == OPCODE_SLBMFEE)       ||
+            (l_opcode_pattern0 == OPCODE_SLBMFEV))
+    {
+        l_predecode = 4;
+    }
+
+    return l_predecode;
+}
+
+//-----------------------------------------------------------------------------------
+bool RamCore::is_load_store(const uint32_t i_opcode)
+{
+    //TODO: make sure they are final version in PC workbook table 9-1
+    bool l_load_store = false;
+    uint32_t l_opcode_pattern0 = i_opcode & 0xFC0007FE;
+    uint32_t l_opcode_pattern1 = i_opcode & 0xFC000000;
+
+    if((l_opcode_pattern0 == OPCODE_DCBZ)   ||
+       (l_opcode_pattern0 == OPCODE_DCBF)   ||
+       (l_opcode_pattern1 == OPCODE_LD)     ||
+       (l_opcode_pattern1 == OPCODE_LFD)    ||
+       (l_opcode_pattern1 == OPCODE_STD)    ||
+       (l_opcode_pattern1 == OPCODE_LFD)    ||
+       (l_opcode_pattern1 == OPCODE_STFD)   ||
+       (l_opcode_pattern0 == OPCODE_LVX)    ||
+       (l_opcode_pattern0 == OPCODE_STVX)   ||
+       (l_opcode_pattern0 == OPCODE_LXVD2X) ||
+       (l_opcode_pattern0 == OPCODE_STXVD2X))
+    {
+        l_load_store = true;
+    }
+
+    return l_load_store;
+}
+
+//-----------------------------------------------------------------------------------
+fapi2::ReturnCode RamCore::get_reg(const Enum_RegType i_type, const uint32_t i_reg_num,
+                                   fapi2::buffer<uint64_t>* o_buffer, const bool i_allow_mult)
+{
+    FAPI_DBG("Start get register");
+    uint32_t l_opcode = 0;
+    uint32_t l_spr_regnum_lo = 0;
+    uint32_t l_spr_regnum_hi = 0;
+    fapi2::buffer<uint64_t> l_backup_gpr0 = 0;
+    fapi2::buffer<uint64_t> l_backup_fpr0 = 0;
+
+    // ram_setup
+    if(!i_allow_mult)
+    {
+        FAPI_TRY(ram_setup());
+    }
+
+    FAPI_ASSERT(iv_ram_setup,
+                fapi2::P9_RAM_NOT_SETUP_ERR(),
+                "Attempting to get register without setup before");
+
+    //backup GPR0 if it is written
+    if(iv_write_gpr0)
+    {
+        l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD;
+        FAPI_TRY(ram_opcode(l_opcode, true));
+        FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_gpr0));
+    }
+
+    // get register value
+    if(i_type == REG_GPR)
+    {
+        //1.create mtsprd<i_reg_num> opcode, ram into thread
+        l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD;
+        l_opcode += (i_reg_num << 21);
+        FAPI_TRY(ram_opcode(l_opcode, true));
+
+        //2.get GPR value from SCR0
+        FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0]));
+    }
+    else if(i_type == REG_SPR)
+    {
+        if(i_reg_num == RAM_REG_NIA)
+        {
+            //1.ram MFNIA_RT opcode
+            l_opcode = OPCODE_MFNIA_RT;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            //2.get NIA from GPR0
+            l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0]));
+        }
+        else if(i_reg_num == RAM_REG_MSR)
+        {
+            //1.create mfmsr opcode, ram into thread
+            l_opcode = OPCODE_MFMSR_TO_GPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            //2.get MSR value from SCR0
+            l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0]));
+        }
+        else if(i_reg_num == RAM_REG_CR)
+        {
+            //1.create mfcr opcode, ram into thread
+            l_opcode = OPCODE_MFCR_TO_GPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            //2.get MSR value from SCR0
+            l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0]));
+        }
+        else if(i_reg_num == RAM_REG_FPSCR)
+        {
+            //1.backup FPR0
+            l_opcode = OPCODE_MFFPRD_FROM_FPR0_TO_GPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_fpr0));
+
+            //2.create mffs opcode, ram into thread
+            l_opcode = OPCODE_MFFS;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            //3.get FPSCR value from SCR0
+            l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0]));
+
+            //4.restore FPR0
+            FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_fpr0));
+            l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            l_opcode = OPCODE_MTFPRD_FROM_GPR0_TO_FPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+        }
+        else
+        {
+            //1.create mfspr<gpr0, i_reg_num> opcode, ram into thread
+            l_opcode = OPCODE_MFSPR_FROM_SPR0_TO_GPR0;
+            l_spr_regnum_lo = i_reg_num & 0x0000001F;
+            l_spr_regnum_hi = i_reg_num & 0x000003E0;
+            l_opcode += (l_spr_regnum_lo << 16);
+            l_opcode += (l_spr_regnum_hi << 6);
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            //2.create mtsprd<gpr0> opcode, ram into thread
+            l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            //3.get GPR value from SCR0
+            FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0]));
+        }
+    }
+    else if(i_type == REG_FPR)
+    {
+        //1.create mffprd<gpr0, i_reg_num>#SX=0 opcode, ram into thread
+        l_opcode = OPCODE_MFFPRD_FROM_FPR0_TO_GPR0;
+        l_opcode += (i_reg_num << 21);
+        FAPI_TRY(ram_opcode(l_opcode, true));
+
+        //2.create mtsprd<gpr0> opcode, ram into thread
+        l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD;
+        FAPI_TRY(ram_opcode(l_opcode, true));
+
+        //3.get GPR value from SCR0
+        FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0]));
+    }
+
+#ifndef __PPE__
+    else if(i_type == REG_VSR)
+    {
+        //1.create mfvsrd<gpr0, i_reg_num> opcode, ram into thread to get dw0
+        if(i_reg_num < 32)
+        {
+            l_opcode = OPCODE_MFVSRD_FROM_VSR0_TO_GPR0;
+            l_opcode += (i_reg_num << 21);
+        }
+        else
+        {
+            l_opcode = OPCODE_MFVSRD_FROM_VSR32_TO_GPR0;
+            l_opcode += ((i_reg_num - 32) << 21);
+        }
+
+        FAPI_TRY(ram_opcode(l_opcode, true));
+
+        //2.create mtsprd<gpr0> opcode, ram into thread
+        l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD;
+        FAPI_TRY(ram_opcode(l_opcode, true));
+
+        //3.get VSR dw0 value from SCR0
+        FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[0]));
+
+        //4.create mfvrld<gpr0, i_reg_num> opcode, ram into thread to get dw1
+        if(i_reg_num < 32)
+        {
+            l_opcode = OPCODE_MFVSRLD_FROM_VSR0_TO_GPR0;
+            l_opcode += (i_reg_num << 21);
+        }
+        else
+        {
+            l_opcode = OPCODE_MFVSRLD_FROM_VSR32_TO_GPR0;
+            l_opcode += ((i_reg_num - 32) << 21);
+        }
+
+        FAPI_TRY(ram_opcode(l_opcode, true));
+
+        //5.create mtsprd<gpr0> opcode, ram into thread
+        l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD;
+        FAPI_TRY(ram_opcode(l_opcode, true));
+
+        //6.get VSR dw1 value from SCR0
+        FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, o_buffer[1]));
+    }
+
+#endif
+    else
+    {
+        FAPI_ASSERT(false,
+                    fapi2::P9_RAM_INVALID_REG_TYPE_ACCESS_ERR()
+                    .set_REGTYPE(i_type),
+                    "Type of reg is not supported");
+    }
+
+    //restore GPR0 if necessary
+    if(iv_write_gpr0)
+    {
+        FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_gpr0));
+        l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0;
+        FAPI_TRY(ram_opcode(l_opcode, true));
+    }
+
+    // ram_cleanup
+    if(!i_allow_mult)
+    {
+        FAPI_TRY(ram_cleanup());
+    }
+
+fapi_try_exit:
+    // Error happened and it's not ram error, call ram_cleanup to restore the backup registers
+    // If it is ram error, do not call ram_cleanup, so that no new ramming will be executed
+    // Do not use "FAPI_TRY" to avoid endless loop
+    fapi2::ReturnCode first_err = fapi2::current_err;
+
+    if((fapi2::current_err != fapi2::FAPI2_RC_SUCCESS) && !iv_ram_err && iv_ram_setup)
+    {
+        ram_cleanup();
+    }
+
+    FAPI_DBG("Exiting get register");
+    return first_err;
+}
+
+//-----------------------------------------------------------------------------------
+fapi2::ReturnCode RamCore::put_reg(const Enum_RegType i_type, const uint32_t i_reg_num,
+                                   const fapi2::buffer<uint64_t>* i_buffer, const bool i_allow_mult)
+{
+    FAPI_DBG("Start put register");
+    uint32_t l_opcode = 0;
+    uint32_t l_spr_regnum_lo = 0;
+    uint32_t l_spr_regnum_hi = 0;
+    bool l_write_gpr0 = false;
+    fapi2::buffer<uint64_t> l_backup_lr   = 0;
+    fapi2::buffer<uint64_t> l_backup_gpr0 = 0;
+    fapi2::buffer<uint64_t> l_backup_gpr1 = 0;
+    fapi2::buffer<uint64_t> l_backup_fpr0 = 0;
+
+    // ram_setup
+    if(!i_allow_mult)
+    {
+        FAPI_TRY(ram_setup());
+    }
+
+    FAPI_ASSERT(iv_ram_setup,
+                fapi2::P9_RAM_NOT_SETUP_ERR(),
+                "Attempting to put register without setup before");
+
+    //backup GPR0 if it is written
+    if(iv_write_gpr0)
+    {
+        l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD;
+        FAPI_TRY(ram_opcode(l_opcode, true));
+        FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_gpr0));
+    }
+
+#ifndef __PPE__
+
+    //backup GPR1 if it is written
+    if(iv_write_gpr1 && (i_type == REG_VSR))
+    {
+        l_opcode = OPCODE_MTSPR_FROM_GPR1_TO_SPRD;
+        FAPI_TRY(ram_opcode(l_opcode, true));
+        FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_gpr1));
+    }
+
+#endif
+
+    // put register value
+    if(i_type == REG_GPR)
+    {
+        //1.put GPR value into SCR0
+        FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0]));
+
+        //2.create mfsprd<i_reg_num> opcode, ram into thread
+        l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0;
+        l_opcode += (i_reg_num << 21);
+        FAPI_TRY(ram_opcode(l_opcode, true));
+
+        if(i_reg_num == 0)
+        {
+            iv_write_gpr0 = true;
+            l_write_gpr0  = true;
+        }
+
+        if(i_reg_num == 1)
+        {
+            iv_write_gpr1 = true;
+        }
+    }
+    else if(i_type == REG_SPR)
+    {
+        if(i_reg_num == RAM_REG_NIA)
+        {
+            //1.backup LR
+            l_opcode = OPCODE_MFSPR_FROM_LR_TO_GPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_lr));
+
+            //2.put NIA value into LR
+            FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0]));
+
+            l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_LR;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            //3.ram MTNIA_LR opcode
+            l_opcode = OPCODE_MTNIA_LR;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            //4.restore LR
+            FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_lr));
+
+            l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_LR;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+        }
+        else if(i_reg_num == RAM_REG_MSR)
+        {
+            //1.put SPR value into SCR0
+            FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0]));
+
+            //2.create mfsprd<gpr0> opcode, ram into thread
+            l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            //3.create mtmsrd opcode, ram into thread
+            l_opcode = OPCODE_MTMSRD_L0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+        }
+        else if(i_reg_num == RAM_REG_CR)
+        {
+            //1.put SPR value into SCR0
+            FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0]));
+
+            //2.create mfsprd<gpr0> opcode, ram into thread
+            l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            //3.create mtcrf opcode, ram into thread
+            l_opcode = OPCODE_MTCRF_FROM_GPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+        }
+        else if(i_reg_num == RAM_REG_FPSCR)
+        {
+            //1.backup FPR0
+            l_opcode = OPCODE_MFFPRD_FROM_FPR0_TO_GPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPRD;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            FAPI_TRY(fapi2::getScom(iv_target, C_SCR0, l_backup_fpr0));
+
+            //2.put SPR value into GPR0
+            FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0]));
+
+            l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            //3.create mtfsf opcode, ram into thread
+            l_opcode = OPCODE_MTFSF_FROM_GPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            //4.restore FPR0
+            FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_fpr0));
+            l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            l_opcode = OPCODE_MTFPRD_FROM_GPR0_TO_FPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+        }
+        else
+        {
+            //1.put SPR value into SCR0
+            FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0]));
+
+            //2.create mfsprd<gpr0> opcode, ram into thread
+            l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0;
+            FAPI_TRY(ram_opcode(l_opcode, true));
+
+            //3.create mtspr<i_reg_num, gpr0> opcode, ram into thread
+            l_opcode = OPCODE_MTSPR_FROM_GPR0_TO_SPR0;
+            l_spr_regnum_lo = i_reg_num & 0x0000001F;
+            l_spr_regnum_hi = i_reg_num & 0x000003E0;
+            l_opcode += (l_spr_regnum_lo << 16);
+            l_opcode += (l_spr_regnum_hi << 6);
+            FAPI_TRY(ram_opcode(l_opcode, true));
+        }
+    }
+    else if(i_type == REG_FPR)
+    {
+        //1.put FPR value into SCR0
+        FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0]));
+
+        //2.create mfsprd<gpr0> opcode, ram into thread
+        l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0;
+        FAPI_TRY(ram_opcode(l_opcode, true));
+
+        //3.create mtfprd<i_reg_num, gpr0>#TX=0 opcode, ram into thread
+        l_opcode = OPCODE_MTFPRD_FROM_GPR0_TO_FPR0;
+        l_opcode += (i_reg_num << 21);
+        FAPI_TRY(ram_opcode(l_opcode, true));
+    }
+
+#ifndef __PPE__
+    else if(i_type == REG_VSR)
+    {
+        //1.put VSR dw1 value into SCR0
+        FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[1]));
+
+        //2.create mfsprd<gpr0> opcode, ram into thread
+        l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0;
+        FAPI_TRY(ram_opcode(l_opcode, true));
+
+        //3.put VSR dw0 value into SCR0
+        FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, i_buffer[0]));
+
+        //4.create mfsprd<gpr1> opcode, ram into thread
+        l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0;
+        l_opcode += (1 << 21);
+        FAPI_TRY(ram_opcode(l_opcode, true));
+
+        //5.create mtvsrdd<i_reg_num, gpr0, gpr1> opcode, ram into thread
+        if(i_reg_num < 32)
+        {
+            l_opcode = OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR0;
+            l_opcode += (i_reg_num << 21);
+        }
+        else
+        {
+            l_opcode = OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR32;
+            l_opcode += ((i_reg_num - 32) << 21);
+        }
+
+        FAPI_TRY(ram_opcode(l_opcode, true));
+    }
+
+#endif
+    else
+    {
+        FAPI_ASSERT(false,
+                    fapi2::P9_RAM_INVALID_REG_TYPE_ACCESS_ERR()
+                    .set_REGTYPE(i_type),
+                    "Type of reg is not supported");
+    }
+
+    //restore GPR0 if necessary
+    if(iv_write_gpr0 && !l_write_gpr0)
+    {
+        FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_gpr0));
+        l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR0;
+        FAPI_TRY(ram_opcode(l_opcode, true));
+    }
+
+#ifndef __PPE__
+
+    //restore GPR1 if necessary
+    if(iv_write_gpr1 && (i_type == REG_VSR))
+    {
+        FAPI_TRY(fapi2::putScom(iv_target, C_SCR0, l_backup_gpr1));
+        l_opcode = OPCODE_MFSPR_FROM_SPRD_TO_GPR1;
+        FAPI_TRY(ram_opcode(l_opcode, true));
+    }
+
+#endif
+
+    // ram_cleanup
+    if(!i_allow_mult)
+    {
+        FAPI_TRY(ram_cleanup());
+    }
+
+fapi_try_exit:
+    // Error happened and it's not ram error, call ram_cleanup to restore the backup registers
+    // If it is ram error, do not call ram_cleanup, so that no new ramming will be executed
+    // Do not use "FAPI_TRY" to avoid endless loop
+    fapi2::ReturnCode first_err = fapi2::current_err;
+
+    if((fapi2::current_err != fapi2::FAPI2_RC_SUCCESS) && !iv_ram_err && iv_ram_setup)
+    {
+        ram_cleanup();
+    }
+
+    FAPI_DBG("Exiting put register");
+    return first_err;
+}
+
+
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H
new file mode 100644
index 00000000..46f0eaf7
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.H
@@ -0,0 +1,153 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_ram_core.H $           */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------------
+///
+/// @file p9_ram_core.H
+/// @brief Class that implements the base ramming capability
+///
+//-----------------------------------------------------------------------------------
+// *HWP HWP Owner        : Liu Yang Fan <shliuyf@cn.ibm.com>
+// *HWP HWP Backup Owner : Gou Peng Fei <shgoupf@cn.ibm.com>
+// *HWP FW Owner         : Thi Tran <thi@us.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
+//-----------------------------------------------------------------------------------
+
+#ifndef _P9_RAM_CORE_H_
+#define _P9_RAM_CORE_H_
+
+//-----------------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------------
+#include <fapi2.H>
+
+//-----------------------------------------------------------------------------------
+// Structure definitions
+//-----------------------------------------------------------------------------------
+// register access type
+enum Enum_RegType
+{
+    REG_GPR,
+    REG_SPR,
+    REG_FPR,
+    REG_VSR
+};
+
+
+class RamCore
+{
+    public:
+//-----------------------------------------------------------------------------------
+// Function prototype
+//-----------------------------------------------------------------------------------
+/// @brief Constructor of the class that implements the base ramming capability
+/// @param[in] i_target => core target
+/// @param[in] i_thread => thread number
+//
+        RamCore(const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, const uint8_t i_thread);
+
+//-----------------------------------------------------------------------------------
+/// @brief Destructor of the class that implements the base ramming capability
+//
+        ~RamCore();
+
+//-----------------------------------------------------------------------------------
+/// @brief Enable RAM mode and backup the registers(SCR0/GPR0/GPR1) that will be destroyed later during ramming
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+//
+        fapi2::ReturnCode ram_setup();
+
+//-----------------------------------------------------------------------------------
+/// @brief Perform the ram and check ram is done
+/// @param[in] i_opcode     => opcode to ram
+/// @param[in] i_allow_mult => indicate whether to setup and cleanup
+///                            true: only perform ram, not to call ram_setup and ram_cleanup
+///                            false: call ram_setup and ram_cleanup
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+//
+        fapi2::ReturnCode ram_opcode(const uint32_t i_opcode, const bool i_allow_mult = false);
+
+//-----------------------------------------------------------------------------------
+/// @brief Clear RAM mode and restore the backup registers
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+//
+        fapi2::ReturnCode ram_cleanup();
+
+//-----------------------------------------------------------------------------------
+/// @brief Get a register value by ramming
+/// @param[in] i_type       => register type (REG_SPR/REG_GPR/REG_FPR/REG_VSR)
+/// @param[in] i_reg_num    => register nubmer
+/// @param[out] o_buffer    => register value
+/// @param[in] i_allow_mult => indicate whether to setup and cleanup
+///                            true: only perform ram, not to call ram_setup and ram_cleanup
+///                            false: call ram_setup and ram_cleanup
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+//
+        fapi2::ReturnCode get_reg(const Enum_RegType i_type, const uint32_t i_reg_num, fapi2::buffer<uint64_t>* o_buffer,
+                                  const bool i_allow_mult = false);
+
+//-----------------------------------------------------------------------------------
+/// @brief Put a register value by ramming
+/// @param[in] i_type       => register type (REG_SPR/REG_GPR/REG_FPR/REG_VSR)
+/// @param[in] i_reg_num    => register nubmer
+/// @param[in] i_buffer     => register value
+/// @param[in] i_allow_mult => indicate whether to setup and cleanup
+///                            true: only perform ram, not to call ram_setup and ram_cleanup
+///                            false: call ram_setup and ram_cleanup
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+//
+        fapi2::ReturnCode put_reg(const Enum_RegType i_type, const uint32_t i_reg_num, const fapi2::buffer<uint64_t>* i_buffer,
+                                  const bool i_allow_mult = false);
+
+//-----------------------------------------------------------------------------------
+/// @brief Generate predecode for the opcode to ramming
+/// @param[in] i_opcode => opcode to ram
+/// @return the predecode
+//
+        uint8_t gen_predecode(const uint32_t i_opcode);
+
+//-----------------------------------------------------------------------------------
+/// @brief Check the opcode is load/store or not
+/// @param[in] i_opcode => opcode to ram
+/// @return TRUE if it is load/store
+//
+        bool is_load_store(const uint32_t i_opcode);
+
+    private:
+        fapi2::Target<fapi2::TARGET_TYPE_CORE> iv_target;  // core target
+        uint8_t iv_thread;     // thread number
+        bool iv_ram_enable;    // ram mode is enabled
+        bool iv_ram_scr0_save; // SCR0 is saved when setup
+        bool iv_ram_setup;     // ram mode is enabled and register backup is done
+        bool iv_ram_err;       // error happened during ram
+        bool iv_write_gpr0;    // putGPR0 operation is executed
+        bool iv_write_gpr1;    // putGPR1 operatoin is executed
+        fapi2::buffer<uint64_t> iv_backup_buf0;  // register backup data
+        fapi2::buffer<uint64_t> iv_backup_buf1;  // register backup data
+        fapi2::buffer<uint64_t> iv_backup_buf2;  // register backup data
+};
+
+#endif //_P9_RAM_CORE_H_
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C
new file mode 100644
index 00000000..79046f0e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C
@@ -0,0 +1,185 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.C $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_arrayinit.C
+///
+/// @brief array init procedure to be called with any chiplet target except TP,EP,EC
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_arrayinit.H"
+//## auto_generated
+#include "p9_const_common.H"
+
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
+#include <p9_perv_sbe_cmn.H>
+
+
+enum P9_SBE_ARRAYINIT_Private_Constants
+{
+    LOOP_COUNTER = 0x0000000000042FFF,
+    REGIONS_EXCEPT_VITAL_AND_PLL = 0x7FE,
+    SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCF,
+    SELECT_EDRAM = 0x0,
+    SELECT_SRAM = 0x1,
+    START_ABIST_MATCH_VALUE = 0x0000000F00000000
+};
+
+static fapi2::ReturnCode p9_sbe_arrayinit_scan0_and_arrayinit_module_function(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint16_t> i_regions);
+
+static fapi2::ReturnCode p9_sbe_arrayinit_sdisn_setup(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip,
+        const fapi2::buffer<uint8_t> i_attr,
+        const bool i_set);
+
+fapi2::ReturnCode p9_sbe_arrayinit(const
+                                   fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    fapi2::buffer<uint16_t> l_regions;
+    fapi2::buffer<uint32_t> l_attr_pg;
+    fapi2::buffer<uint8_t> l_attr_read;
+    FAPI_INF("p9_sbe_arrayinit: Entering ...");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, i_target_chip, l_attr_read));
+
+    for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                           fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS |
+                                           fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
+          fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("set sdis_n");
+        FAPI_TRY(p9_sbe_arrayinit_sdisn_setup(l_chplt_trgt, l_attr_read, true));
+
+        FAPI_DBG("Region setup");
+        FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(l_chplt_trgt,
+                 REGIONS_EXCEPT_VITAL_AND_PLL, l_regions));
+        FAPI_DBG("l_regions value: %#018lX ", l_regions);
+
+        FAPI_DBG("Call proc_sbe_arryinit_scan0_and_arrayinit_module_function");
+        FAPI_TRY(p9_sbe_arrayinit_scan0_and_arrayinit_module_function(l_chplt_trgt,
+                 l_regions));
+
+        FAPI_DBG("clear sdis_n");
+        FAPI_TRY(p9_sbe_arrayinit_sdisn_setup(l_chplt_trgt, l_attr_read, false));
+    }
+
+    FAPI_INF("p9_sbe_arrayinit: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief --Run arrayinit on all enabled chiplets
+/// --Scan flush 0 to all rings except GPTR, Time, Repair on all enabled chiplets
+///
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_regions          region value settings
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_arrayinit_scan0_and_arrayinit_module_function(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint16_t> i_regions)
+{
+    bool l_read_reg = false;
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_arrayinit_scan0_and_arrayinit_module_function: Entering ...");
+
+    FAPI_DBG("Check for chiplet enable");
+    //Getting NET_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL0, l_data64));
+    //l_read_reg = NET_CTRL0.CHIPLET_ENABLE
+    l_read_reg = l_data64.getBit<PERV_1_NET_CTRL0_CHIPLET_ENABLE>();
+
+    if ( l_read_reg )
+    {
+        FAPI_DBG("run array_init module for all chiplet except TP, EC, EP");
+        FAPI_TRY(p9_perv_sbe_cmn_array_init_module(i_target_chiplet, i_regions,
+                 LOOP_COUNTER, SELECT_SRAM, SELECT_EDRAM, START_ABIST_MATCH_VALUE));
+
+        FAPI_DBG("run scan0 module for region except vital and pll, scan types except GPTR TIME REPR all chiplets except TP, EC, EP");
+        FAPI_TRY(p9_perv_sbe_cmn_scan0_module(i_target_chiplet, i_regions,
+                                              SCAN_TYPES_EXCEPT_TIME_GPTR_REPR));
+    }
+
+    FAPI_INF("p9_sbe_arrayinit_scan0_and_arrayinit_module_function: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Sdis_n setup
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_attr          Attribute to decide the sdis setup
+/// @param[in]     i_set           set or clear the LCBES condition
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_arrayinit_sdisn_setup(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip,
+        const fapi2::buffer<uint8_t> i_attr,
+        const bool i_set)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_arrayinit_sdisn_setup: Entering ...");
+
+    if ( i_attr )
+    {
+        if ( i_set )
+        {
+            //Setting CPLT_CONF0 register value
+            l_data64.flush<0>();
+            //CPLT_CONF0.CTRL_CC_SDIS_DC_N = 1
+            l_data64.setBit<PERV_1_CPLT_CONF0_CTRL_CC_SDIS_DC_N>();
+            FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF0_OR, l_data64));
+        }
+        else
+        {
+            //Setting CPLT_CONF0 register value
+            l_data64.flush<0>();
+            //CPLT_CONF0.CTRL_CC_SDIS_DC_N = 0
+            l_data64.setBit<PERV_1_CPLT_CONF0_CTRL_CC_SDIS_DC_N>();
+            FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF0_CLEAR, l_data64));
+        }
+    }
+
+    FAPI_INF("p9_sbe_arrayinit_sdisn_setup: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.H
new file mode 100644
index 00000000..9fc72c1b
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.H
@@ -0,0 +1,60 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_arrayinit.H $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_arrayinit.H
+///
+/// @brief array init procedure to be called with any chiplet target except TP,EP,EC
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_ARRAYINIT_H_
+#define _P9_SBE_ARRAYINIT_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_arrayinit_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief Array Init function call for any chiplet Target except TP,EP,EC
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_arrayinit(const
+                                       fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
new file mode 100644
index 00000000..ee741b8c
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
@@ -0,0 +1,244 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_attr_setup.C
+///
+/// @brief Read scratch Regs, update ATTR
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_attr_setup.H"
+
+#include <p9_perv_scom_addresses.H>
+
+fapi2::ReturnCode p9_sbe_attr_setup(const
+                                    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_read_scratch_reg = 0;
+    fapi2::buffer<uint64_t> l_read_scratch8 = 0;
+    fapi2::buffer<uint8_t> l_read_1 = 0;
+    fapi2::buffer<uint8_t> l_read_2 = 0;
+    fapi2::buffer<uint8_t> l_read_3 = 0;
+    fapi2::buffer<uint16_t> l_read_4 = 0;
+    fapi2::buffer<uint32_t> l_read_5 = 0;
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+    fapi2::buffer<uint64_t> l_data64;
+    bool sbe_slave_chip = false;
+    fapi2::buffer<uint64_t> l_read_device_reg = 0;
+    FAPI_INF("p9_sbe_attr_setup: Entering ...");
+
+    FAPI_DBG("Read Scratch8 for validity of Scratch register");
+    //Getting SCRATCH_REGISTER_8 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_8_SCOM,
+                            l_read_scratch8)); //l_read_scratch8 = PIB.SCRATCH_REGISTER_8
+
+    //set_security_acess
+    {
+        fapi2::buffer<uint64_t> l_read_reg;
+
+        FAPI_DBG("Reading ATTR_SECURITY_MODE");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SECURITY_MODE, FAPI_SYSTEM, l_read_1));
+
+        if ( l_read_1.getBit<7>() == 0 )
+        {
+            FAPI_DBG("Clear Security Access Bit");
+            //Setting CBS_CS register value
+            FAPI_TRY(fapi2::getScom(i_target_chip, PERV_CBS_CS_SCOM, l_data64));
+            l_data64.clearBit<4>();  //PIB.CBS_CS.CBS_CS_SECURE_ACCESS_BIT = 0
+            FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CBS_CS_SCOM, l_data64));
+        }
+
+        //Getting CBS_CS register value
+        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_CBS_CS_SCOM,
+                                l_read_reg)); //l_read_reg = PIB.CBS_CS
+
+        l_read_1 = 0;
+        l_read_1.writeBit<7>(l_read_reg.getBit<4>());
+
+        FAPI_DBG("Setting ATTR_SECURITY_ENABLE with the SAB state");
+        FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SECURITY_ENABLE, FAPI_SYSTEM, l_read_1));
+
+    }
+    //read_scratch1_reg
+    {
+        if ( l_read_scratch8.getBit<0>() )
+        {
+            FAPI_DBG("Reading Scratch_reg1");
+            //Getting SCRATCH_REGISTER_1 register value
+            FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_1_SCOM,
+                                    l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_1
+
+            l_read_scratch_reg.extract<0, 6>(l_read_1);
+            l_read_scratch_reg.extract<8, 24>(l_read_5);
+
+            FAPI_DBG("Setting up ATTR_EQ_GARD, ATTR_EC_GARD");
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_EQ_GARD, i_target_chip, l_read_1));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_EC_GARD, i_target_chip, l_read_5));
+
+            l_read_1 = 0;
+            l_read_4 = 0;
+        }
+    }
+    //read_scratch2_reg
+    {
+        if ( l_read_scratch8.getBit<1>() )
+        {
+            FAPI_DBG("Reading Scratch_reg2");
+            //Getting SCRATCH_REGISTER_2 register value
+            FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM,
+                                    l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_2
+
+            l_read_scratch_reg.extractToRight<0, 16>(l_read_4);
+
+            FAPI_DBG("Setting up ATTR_I2C_BUS_DIV_REF");
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4));
+        }
+    }
+
+    //read_scratch4_reg
+    {
+        if ( l_read_scratch8.getBit<3>() )
+        {
+            FAPI_DBG("Reading Scratch_Reg4");
+            //Getting SCRATCH_REGISTER_4 register value
+            FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_4_SCOM,
+                                    l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_4
+
+            l_read_scratch_reg.extractToRight<0, 16>(l_read_4);
+            l_read_scratch_reg.extractToRight<24, 8>(l_read_1);
+
+            FAPI_DBG("Setting up ATTR_BOOT_FREQ_MULT, ATTR_NEST_PLL_BUCKET");
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_BOOT_FREQ_MULT, i_target_chip, l_read_4));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1));
+
+            l_read_1 = 0;
+            l_read_4 = 0;
+        }
+    }
+    //read_scratch5_reg
+    {
+        if ( l_read_scratch8.getBit<4>() )
+        {
+            FAPI_DBG("Reading Scratch_reg5");
+            //Getting SCRATCH_REGISTER_5 register value
+            FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_5_SCOM,
+                                    l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_5
+
+            if (l_read_scratch_reg.getBit<0>())
+            {
+                l_read_1 = fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED;
+            }
+            else
+            {
+                l_read_1 = fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_HB_IPL;
+            }
+
+            l_read_2.writeBit<7>(l_read_scratch_reg.getBit<1>());
+
+            if (l_read_scratch_reg.getBit<2>())
+            {
+                l_read_3 = fapi2::ENUM_ATTR_RISK_LEVEL_TRUE;
+            }
+            else
+            {
+                l_read_3 = fapi2::ENUM_ATTR_RISK_LEVEL_FALSE;
+            }
+
+            FAPI_DBG("Setting up SYSTEM_IPL_PHASE, RISK_LEVEL, SYS_FORCE_ALL_CORES");
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_read_1));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM,
+                                   l_read_2));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_read_3));
+
+            l_read_1 = 0;
+            l_read_2  = 0;
+            l_read_3 = 0;
+
+            if (l_read_scratch_reg.getBit<3>())
+            {
+                l_read_1 = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_TRUE;
+            }
+            else
+            {
+                l_read_1 = fapi2::ENUM_ATTR_DISABLE_HBBL_VECTORS_FALSE;
+            }
+
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM,
+                                   l_read_1));
+
+            l_read_1 = 0;
+        }
+    }
+    //read_scratch6_reg
+    {
+        if ( l_read_scratch8.getBit<5>() )
+        {
+            FAPI_DBG("Reading Scratch_reg6");
+            //Getting SCRATCH_REGISTER_6 register value
+            FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_6_SCOM,
+                                    l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_6
+
+            l_read_1 = 0;
+            sbe_slave_chip = l_read_scratch_reg.getBit<24>();
+
+            if ( !sbe_slave_chip )  // 0b0 == master
+            {
+                FAPI_DBG("Reading DEVICE_ID_REG value");
+                FAPI_TRY(fapi2::getScom(i_target_chip, PERV_DEVICE_ID_REG, l_read_device_reg));
+
+                if (!l_read_device_reg.getBit<40>())
+                {
+                    l_read_1.setBit<7>();
+                }
+            }
+
+            l_read_scratch_reg.extractToRight<26, 3>(l_read_2);
+            l_read_scratch_reg.extractToRight<29, 3>(l_read_3);
+
+            FAPI_DBG("Setting up MASTER_CHIP, FABRIC_GROUP_ID and CHIP_ID");
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_SBE_MASTER_CHIP, i_target_chip,
+                                   l_read_1));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target_chip,
+                                   l_read_2));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target_chip,
+                                   l_read_3));
+
+        }
+    }
+
+    FAPI_INF("p9_sbe_attr_setup: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H
new file mode 100644
index 00000000..0a5e2a09
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H
@@ -0,0 +1,61 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_attr_setup.H
+///
+/// @brief Read scratch Regs, update ATTR
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_ATTR_SETUP_H_
+#define _P9_SBE_ATTR_SETUP_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_attr_setup_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief HWP will read the contents of Byte 0 of scratch register 8 indicates validity of mailbox register
+/// and call FAPI2 APIs to set the values into the corresponding platform ATTR
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_attr_setup(const
+                                        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.C
new file mode 100644
index 00000000..1cd61c93
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.C
@@ -0,0 +1,52 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.C $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_check_master.C
+///
+/// @brief Deremine if this is master SBE -- External FSI/GP bitIf master continue, else enable runtime chipOps
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_check_master.H"
+fapi2::ReturnCode p9_sbe_check_master(const
+                                      fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    FAPI_DBG("p9_sbe_check_master: Entering ...");
+
+    FAPI_DBG("p9_sbe_check_master: Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.H
new file mode 100644
index 00000000..88c3bf21
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.H
@@ -0,0 +1,61 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_check_master.H $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_check_master.H
+///
+/// @brief Deremine if this is master SBE -- External FSI/GP bitIf master continue, else enable runtime chipOps
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_CHECK_MASTER_H_
+#define _P9_SBE_CHECK_MASTER_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_check_master_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief If master continue, else enable runtime chipOps
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_check_master(const
+                                          fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C
new file mode 100644
index 00000000..4d28bdbd
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C
@@ -0,0 +1,134 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_sbe_check_master_stop15.H
+/// @brief Check if the targeted core (master) is fully in STOP15
+///
+// *HWP HWP Owner   : Greg Still <stillgsg@us.ibm.com>
+// *HWP FW Owner    : Bilicon Patil <bilpatil@in.ibm.com>
+// *HWP Team        : PM
+// *HWP Level       : 2
+// *HWP Consumed by : SBE
+///
+/// High-level procedure flow:
+/// @verbatim
+///    - Read the STOP History Register from the target core
+///    - Return SUCCESS if::
+///        - STOP_GATED is set (indicating it is stopped)
+///        - STOP_TRANSITION is clear (indicating it is stable)
+///        - ACT_STOP_LEVEL is at the appropriate value (either 11 (0xB) or 15 (0x15)
+///    - Return PENDING if
+///        - STOP_TRANSITION is set (indicating transtion is progress)
+///    - Return ERROR if
+///        - STOP_GATED is set, STOP_TRANSITION is clear and ACT_STOP_LEVEL is not
+///          appropriate
+///        - STOP_TRANSITION is clear but STOP_GATED is clear
+///        - Hardware access errors
+/// @endverbatim
+
+// -----------------------------------------------------------------------------
+//  Includes
+// -----------------------------------------------------------------------------
+#include <p9_sbe_check_master_stop15.H>
+#include <p9_pm_stop_history.H>
+#include <p9_quad_scom_addresses.H>
+
+// -----------------------------------------------------------------------------
+//  Function definitions
+// -----------------------------------------------------------------------------
+
+// See .H for documentation
+fapi2::ReturnCode p9_sbe_check_master_stop15(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+{
+    FAPI_IMP("> p9_sbe_check_master_stop15");
+
+    fapi2::buffer<uint64_t> l_data64;
+    uint32_t l_stop_gated = 0;
+    uint32_t l_stop_transition = p9ssh::SSH_UNDEFINED;
+    uint32_t l_stop_requested_level = 0; // Running Level
+    uint32_t l_stop_actual_level = 0;    // Running Level
+
+    // Read the "Other" STOP History Register
+    FAPI_TRY(fapi2::getScom(i_target, C_PPM_SSHOTR, l_data64));
+
+    // Extract the field values
+    l_data64.extractToRight<p9ssh::STOP_GATED_START,
+                            p9ssh::STOP_GATED_LEN>(l_stop_gated);
+
+    l_data64.extractToRight<p9ssh::STOP_TRANSITION_START,
+                            p9ssh::STOP_TRANSITION_LEN>(l_stop_transition);
+
+    // Testing showed the above operation was sign extending into
+    // the l_stop_transition variable.
+    l_stop_transition &= 0x3;
+
+    l_data64.extractToRight<p9ssh::STOP_REQUESTED_LEVEL_START,
+                            p9ssh::STOP_REQUESTED_LEVEL_LEN>(l_stop_requested_level);
+
+    l_data64.extractToRight<p9ssh::STOP_ACTUAL_LEVEL_START,
+                            p9ssh::STOP_ACTUAL_LEVEL_LEN>(l_stop_actual_level);
+
+#ifndef __PPE__
+    FAPI_DBG("GATED = %d; TRANSITION = %d (0x%X); REQUESTED_LEVEL = %d; ACTUAL_LEVEL = %d",
+             l_stop_gated,
+             l_stop_transition, l_stop_transition,
+             l_stop_requested_level,
+             l_stop_actual_level);
+#endif
+
+    // Check for valide reguest level
+    FAPI_ASSERT((l_stop_requested_level == 11 || l_stop_requested_level == 15),
+                fapi2::CHECK_MASTER_STOP15_INVALID_REQUEST_LEVEL()
+                .set_REQUESTED_LEVEL(l_stop_requested_level),
+                "Invalid requested STOP Level");
+
+    // Check for valid pending condition
+    FAPI_ASSERT(!(l_stop_transition == p9ssh::SSH_CORE_COMPLETE ||
+                  l_stop_transition == p9ssh::SSH_ENTERING        ),
+                fapi2::CHECK_MASTER_STOP15_PENDING(),
+                "STOP 15 is still pending");
+
+    // Assert completion and the core gated condition.  If not, something is off.
+    FAPI_ASSERT((l_stop_transition == p9ssh::SSH_COMPLETE &&
+                 l_stop_gated == p9ssh::SSH_GATED         ),
+                fapi2::CHECK_MASTER_STOP15_INVALID_STATE()
+                .set_STOP_HISTORY(l_data64),
+                "STOP 15 error");
+
+    // Check for valid actual level
+    FAPI_ASSERT((l_stop_actual_level == 11 || l_stop_actual_level == 15),
+                fapi2::CHECK_MASTER_STOP15_INVALID_ACTUAL_LEVEL()
+                .set_ACTUAL_LEVEL(l_stop_actual_level),
+                "Invalid actual STOP Level");
+
+    FAPI_INF("SUCCESS!!  Valid STOP entry state has been achieved.")
+
+fapi_try_exit:
+    FAPI_INF("< p9_sbe_check_master_stop15");
+
+    return fapi2::current_err;
+} // END p9_sbe_check_master_stop15
+
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.H
new file mode 100644
index 00000000..575536d9
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.H
@@ -0,0 +1,62 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_check_master_stop15.H
+///
+///------------------------------------------------------------------------------
+// *HWP HWP Owner   : Greg Still <stillgsg@us.ibm.com>
+// *HWP FW Owner    : Bilicon Patil <bilpatil@in.ibm.com>
+// *HWP Team        : PM
+// *HWP Level       : 2
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_CHECK_MASTER_STOP15_H_
+#define _P9_SBE_CHECK_MASTER_STOP15_H_
+
+#include <fapi2.H>
+
+typedef fapi2::ReturnCode (*p9_sbe_check_master_stop15_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
+
+
+/// @brief Check if the targeted core (master) is fully in STOP15
+///
+/// @param[in]  i_target   Reference to TARGET_TYPE_CORE target
+///
+/// @return     FAPI2_RC_SUCCESS if success
+/// @return     STOP15_PENDING  STOP 15 not reached, but no error
+///             HW state (still in progress)
+/// @return     Others indicate hardware failur
+///
+extern "C"
+{
+    fapi2::ReturnCode
+    p9_sbe_check_master_stop15(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+}
+
+#endif  // _P9_SBE_CHECK_MASTER_STOP15_H_
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C
new file mode 100644
index 00000000..521078bd
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C
@@ -0,0 +1,70 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.C $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_init.C
+///
+/// @brief init procedure for all enabled chiplets
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_chiplet_init.H"
+
+#include "p9_perv_scom_addresses.H"
+
+
+fapi2::ReturnCode p9_sbe_chiplet_init(const
+                                      fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    bool l_read_reg = false;
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_init: Entering..");
+
+    FAPI_DBG("Check  for XSTOP Bit");
+    //Getting INTERRUPT_TYPE_REG register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PIB_INTERRUPT_TYPE_REG, l_data64));
+    //l_read_reg = PIB.INTERRUPT_TYPE_REG.CHECKSTOP
+    l_read_reg = l_data64.getBit<2>();
+
+    FAPI_ASSERT(!(l_read_reg),
+                fapi2::CHECKSTOP_ERR()
+                .set_READ_CHECKSTOP(l_read_reg),
+                "ERROR:CHECKSTOP BIT GET SET ");
+
+    FAPI_INF("p9_sbe_chiplet_init: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H
new file mode 100644
index 00000000..72d20577
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_init.H $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_init.H
+///
+/// @brief init procedure for all enabled chiplets
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_CHIPLET_INIT_H_
+#define _P9_SBE_CHIPLET_INIT_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_chiplet_init_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief chiplet init function call on all enabled chiplets
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_chiplet_init(const
+                                          fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C
new file mode 100644
index 00000000..a36fa629
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C
@@ -0,0 +1,123 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_pll_initf.C
+///
+/// @brief procedure for scan initializing PLL config bits for XBus, OBus, PCIe, MC Chiplets
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : srinivas naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_chiplet_pll_initf.H"
+#include "p9_perv_scom_addresses.H"
+
+fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    FAPI_INF("p9_sbe_chiplet_pll_initf: Entering ...");
+
+    for (auto l_chplt_trgt :  i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_XBUS |
+                                           fapi2::TARGET_FILTER_ALL_OBUS |
+                                           fapi2::TARGET_FILTER_ALL_PCI), fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        uint8_t l_unit_pos;
+        RingID l_ring_id = xb_pll_bndy;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_unit_pos),
+                 "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)");
+
+        switch (l_unit_pos)
+        {
+            case 0x6:
+                FAPI_DBG("Scan xb_pll_bndy_ring");
+                l_ring_id = xb_pll_bndy;
+                break;
+
+            case 0x9:
+                FAPI_DBG("Scan ob0_pll_bndy ring");
+                l_ring_id = ob0_pll_bndy;
+                break;
+
+            case 0xa:
+                FAPI_DBG("Scan ob1_pll_bndy ring");
+                l_ring_id = ob1_pll_bndy;
+                break;
+
+            case 0xb:
+                FAPI_DBG("Scan ob2_pll_bndy ring");
+                l_ring_id = ob2_pll_bndy;
+                break;
+
+            case 0xc:
+                FAPI_DBG("Scan ob3_pll_bndy ring");
+                l_ring_id = ob3_pll_bndy;
+                break;
+
+            case 0xd:
+                FAPI_DBG("Scan pci0_pll_bndy ring");
+                l_ring_id = pci0_pll_bndy;
+                break;
+
+            case 0xe:
+                FAPI_DBG("Scan pci1_pll_bndy ring");
+                l_ring_id = pci1_pll_bndy;
+                break;
+
+            case 0xf:
+                FAPI_DBG("Scan pci2_pll_bndy ring");
+                l_ring_id = pci2_pll_bndy;
+                break;
+
+            default:
+                FAPI_ASSERT(false,
+                            fapi2::P9_SBE_CHIPLET_PLL_INITF_INVALID_CHIPLET().
+                            set_TARGET(l_chplt_trgt).
+                            set_UNIT_POS(l_unit_pos),
+                            "Unexpected chiplet!");
+        }
+
+        FAPI_TRY(fapi2::putRing(i_target_chip, l_ring_id, fapi2::RING_MODE_SET_PULSE_NSL),
+                 "Error from putRing (ringID: %d)", l_ring_id);
+
+    }
+
+    for (auto l_chplt_trgt :  i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST>(fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Scan mc_pll_bndy_bucket_1 ring");
+        FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_pll_bndy_bucket_1, fapi2::RING_MODE_SET_PULSE_NSL),
+                 "Error from putRing (mc_pll_bndy)");
+    }
+
+fapi_try_exit:
+    FAPI_INF("p9_sbe_chiplet_pll_initf: Exiting ...");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H
new file mode 100644
index 00000000..a45218b9
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H
@@ -0,0 +1,62 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_pll_initf.H
+///
+/// @brief procedure for scan initializing PLL config bits for XBus, OBus, PCIe, MC Chiplets
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : srinivas naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_CHIPLET_PLL_INITF_H_
+#define _P9_SBE_CHIPLET_PLL_INITF_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_chiplet_pll_initf_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief If TRUE then skip MC chiplet
+/// run scan0 module  (scan region = PLL, scan_types = GPTR)
+/// run scan0 module  (scan region = PLL, scan_types = BNDY/FUNC)
+/// Scan initialize PLL BNDY chain (chiplet =[CPLT], scan ring = PLL, scan type = BNDY)
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C
new file mode 100644
index 00000000..a152c465
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C
@@ -0,0 +1,427 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_pll_setup.C
+///
+/// @brief Setup PLL for Obus, Xbus, PCIe, DMI
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_chiplet_pll_setup.H"
+//## auto_generated
+#include "p9_const_common.H"
+
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
+#include <p9_sbe_common.H>
+
+
+enum P9_SBE_CHIPLET_PLL_SETUP_Private_Constants
+{
+    NS_DELAY = 5000000, // unit is nano seconds
+    SIM_CYCLE_DELAY = 100000, // unit is sim cycles
+    CLOCK_CMD = 0x1,
+    CLOCK_TYPES = 0x2,
+    DONT_STARTMASTER = 0x0,
+    DONT_STARTSLAVE = 0x0,
+    REGIONS = 0x001
+};
+
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pci_pll_lock(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip);
+
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pll_lock(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip);
+
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_function(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_dcc_bypass(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip);
+
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_pdly_bypass(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_reset(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip);
+
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_test_enable(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    uint8_t l_read_attr = 0;
+    FAPI_INF("p9_sbe_chiplet_pll_setup: Entering ...");
+
+    for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Drop PDLY bypass");
+        FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_pdly_bypass(l_chplt_trgt));
+    }
+
+    FAPI_DBG("Reading ATTR_mc_sync_mode");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr));
+
+    if ( l_read_attr )
+    {
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("call clock start stop module and drop syncclk muxsel");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
+                                               fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("release pll test enable for except pcie");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
+                                               fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
+              fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("Release PLL reset");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("Check pll lock for PCIe");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pci_pll_lock(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
+                                               fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("Check pll lock for Xb,Ob");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
+                                               fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
+              fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_function(l_chplt_trgt));
+        }
+    }
+    else
+    {
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("Drop MCC bypass");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_dcc_bypass(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("call clock start stop module and drop syncclk_muxsel");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                               fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS),
+              fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("release pll test enable for except pcie");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                               fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI |
+                                               fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("Release PLL reset");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("Check pll lock for pcie");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pci_pll_lock(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                               fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_XBUS),
+              fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("check pll lock for Mc,Xb,Ob");
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(l_chplt_trgt));
+        }
+
+        for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                               fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI |
+                                               fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_TRY(p9_sbe_chiplet_pll_setup_function(l_chplt_trgt));
+        }
+    }
+
+    FAPI_INF("p9_sbe_chiplet_pll_setup: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief check pll lock for pcie chiplet
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pci_pll_lock(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_read_reg;
+    FAPI_INF("p9_sbe_chiplet_pll_setup_check_pci_pll_lock: Entering ...");
+
+    FAPI_DBG("Check  PLL lock");
+    //Getting PLL_LOCK_REG register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PLL_LOCK_REG,
+                            l_read_reg)); //l_read_reg = PLL_LOCK_REG
+
+    FAPI_ASSERT(l_read_reg.getBit<0>() == 1 && l_read_reg.getBit<1>() == 1,
+                fapi2::PLL_LOCK_ERR()
+                .set_PLL_READ(l_read_reg),
+                "ERROR:PLL LOCK NOT SET");
+
+    FAPI_INF("p9_sbe_chiplet_pll_setup_check_pci_pll_lock: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief check pll lock for OB,XB,MC
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_check_pll_lock(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_read_reg;
+    FAPI_INF("p9_sbe_chiplet_pll_setup_check_pll_lock: Entering ...");
+
+    FAPI_DBG("Check  PLL lock");
+    //Getting PLL_LOCK_REG register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PLL_LOCK_REG,
+                            l_read_reg)); //l_read_reg = PLL_LOCK_REG
+
+    FAPI_ASSERT(l_read_reg.getBit<0>() == 1 ,
+                fapi2::PLL_LOCK_ERR()
+                .set_PLL_READ(l_read_reg),
+                "ERROR:PLL LOCK NOT SET");
+
+    FAPI_INF("p9_sbe_chiplet_pll_setup_check_pll_lock: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Setup PLL for XBus, OBus, PCIe, (MC) chiplets
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_function(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_pll_setup_function: Entering ...");
+
+    FAPI_DBG("Drop PLL Bypass");
+    //Setting NET_CTRL0 register value
+    l_data64.flush<1>();
+    l_data64.clearBit<PERV_1_NET_CTRL0_PLL_BYPASS>();  //NET_CTRL0.PLL_BYPASS = 0
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64));
+
+    FAPI_DBG("Set scan ratio to 4:1 as soon as PLL is out of bypass mode");
+    //Setting OPCG_ALIGN register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_OPCG_ALIGN, l_data64));
+    l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN>
+    (0x3);  //OPCG_ALIGN.SCAN_RATIO = 0x3
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_ALIGN, l_data64));
+
+    FAPI_DBG("Reset PCB Slave error register");
+    //Setting ERROR_REG register value
+    //ERROR_REG = 0xFFFFFFFFFFFFFFFF
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_ERROR_REG, 0xFFFFFFFFFFFFFFFF));
+
+    FAPI_INF("p9_sbe_chiplet_pll_setup_function: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Drop Mc DCC bypass
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_dcc_bypass(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_pll_setup_mc_dcc_bypass: Entering ...");
+
+    FAPI_DBG("Drop DCC bypass");
+    //Setting NET_CTRL1 register value
+    l_data64.flush<1>();
+    //NET_CTRL1.CLK_DCC_BYPASS_EN = 0
+    l_data64.clearBit<PERV_1_NET_CTRL1_CLK_DCC_BYPASS_EN>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL1_WAND, l_data64));
+
+    FAPI_INF("p9_sbe_chiplet_pll_setup_mc_dcc_bypass: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Drop Mc PDLY bypass
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_mc_pdly_bypass(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_pll_setup_mc_pdly_bypass: Entering ...");
+
+    FAPI_DBG("Drop PDLY bypass");
+    //Setting NET_CTRL1 register value
+    l_data64.flush<1>();
+    //NET_CTRL1.CLK_PDLY_BYPASS_EN = 0
+    l_data64.clearBit<PERV_1_NET_CTRL1_CLK_PDLY_BYPASS_EN>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1_WAND, l_data64));
+
+    FAPI_INF("p9_sbe_chiplet_pll_setup_mc_pdly_bypass: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief release pll reset and wait
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_reset(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_pll_setup_pll_reset: Entering ...");
+
+    FAPI_DBG("Drop PLL Reset");
+    //Setting NET_CTRL0 register value
+    l_data64.flush<1>();
+    l_data64.clearBit<PERV_1_NET_CTRL0_PLL_RESET>();  //NET_CTRL0.PLL_RESET = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL0_WAND, l_data64));
+
+    fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
+
+    FAPI_INF("p9_sbe_chiplet_pll_setup_pll_reset: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Release pll test enable except for pcie
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_pll_test_enable(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_pll_setup_pll_test_enable: Entering ...");
+
+    FAPI_DBG("Release PLL test enable for except pcie");
+    //Setting NET_CTRL0 register value
+    l_data64.flush<1>();
+    l_data64.clearBit<PERV_1_NET_CTRL0_PLL_TEST_EN>();  //NET_CTRL0.PLL_TEST_EN = 0
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64));
+
+    FAPI_INF("p9_sbe_chiplet_pll_setup_pll_test_enable: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief start PLL clock region, NSL latches only , call module clock_start_stop
+/// Drop syncclk_muxsel
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux: Entering ...");
+
+    FAPI_DBG("call module clock start stop");
+    FAPI_TRY(p9_sbe_common_clock_start_stop(i_target_chiplet, CLOCK_CMD,
+                                            DONT_STARTSLAVE, DONT_STARTMASTER, REGIONS, CLOCK_TYPES));
+
+    FAPI_DBG("Drop syncclk muxsel for pcie chiplet");
+    //Setting CPLT_CTRL0 register value
+    l_data64.flush<0>();
+    //CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 0
+    l_data64.setBit<PERV_1_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64));
+
+    FAPI_INF("p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.H
new file mode 100644
index 00000000..c2b1caad
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.H
@@ -0,0 +1,62 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_pll_setup.H
+///
+/// @brief Setup PLL for Obus, Xbus, PCIe, DMI
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_CHIPLET_PLL_SETUP_H_
+#define _P9_SBE_CHIPLET_PLL_SETUP_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_chiplet_pll_setup_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief Checks that the PLL locked
+/// Start the VAR OSCs / Config the TANK PLLs & lock
+/// In certain configs these chiplets are potentially not used
+/// Must run at system frequency
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
new file mode 100644
index 00000000..951b4696
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
@@ -0,0 +1,1330 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_reset.C
+///
+/// @brief Steps:-
+///     1) Identify Partical good chiplet and configure Multicasting register
+///     2) Similar way, Configure hang pulse counter for Nest/MC/OBus/XBus/PCIe
+///     3) Similar way,  set fence for Nest and MC chiplet
+///     4) Similar way,  Reset sys.config and OPCG setting for Nest and MC chiplet in sync mode
+///
+/// Done
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V. Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_chiplet_reset.H"
+//## auto_generated
+#include "p9_const_common.H"
+
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
+#include <p9_perv_sbe_cmn.H>
+
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt,
+    const uint8_t i_reg0_val = 0xff,
+    const uint8_t i_reg1_val = 0xff,
+    const uint8_t i_reg2_val = 0xff,
+    const uint8_t i_reg3_val = 0xff,
+    const uint8_t i_reg4_val = 0xff,
+    const uint8_t i_reg5_val = 0xff,
+    const uint8_t i_reg6_val = 0xff);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_net_cntl_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_MC(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint32_t> i_clk_mux_value);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_call(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_obus(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint32_t> i_clk_mux_value);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_pcie(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint32_t> i_clk_mux_value);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_xbus(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint32_t> i_clk_mux_value);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_div_clk_bypass(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_enable_listen_to_sync(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const bool i_enable);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_hsspowergate(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_async_reset_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip,
+    const bool i_drop);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+        const uint64_t i_mc_grp1_val,
+        const uint64_t i_mc_grp2_val = 0x0,
+        const uint64_t i_mc_grp3_val = 0x0);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup_cache(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_nest_hang_cnt_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_nest_ob_async_reset(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+static fapi2::ReturnCode
+p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_opcg_cnfg(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_pll_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const bool i_enable);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_scan0_call(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_setup(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+static fapi2::ReturnCode p9_sbe_chiplet_reset_setup_iop_logic(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip);
+
+fapi2::ReturnCode p9_sbe_chiplet_reset(const
+                                       fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    // Local variable
+    //uint8_t l_mc_sync_mode = 0;
+    fapi2::buffer<uint8_t> l_attr_vitl_setup;
+    fapi2::buffer<uint8_t> l_attr_hang_cnt6_setup;
+    fapi2::TargetState l_target_state = fapi2::TARGET_STATE_FUNCTIONAL;
+    FAPI_INF("p9_sbe_chiplet_reset: Entering ...");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_VITL_CLK_SETUP, i_target_chip,
+                           l_attr_vitl_setup));
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_NEST |
+                                           fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI |
+                                           fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        // Configuring chiplet multicasting registers.
+        FAPI_DBG("Configuring multicasting registers for Nest,Xb,Obus,pcie chiplets" );
+        FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(l_target_cplt,
+                                               p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Configuring multicast registers for MC01,MC23");
+        FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(l_target_cplt,
+                                               p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0,
+                                               p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP2));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_CACHES, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        // Configuring chiplet multicasting registers..
+        FAPI_DBG("Configuring cache chiplet multicasting registers");
+        FAPI_TRY(p9_sbe_chiplet_reset_mc_setup_cache(l_target_cplt));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_CORES, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        // Configuring chiplet multicasting registers..
+        FAPI_DBG("Configuring core chiplet multicasting registers");
+        FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(l_target_cplt,
+                                               p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0,
+                                               p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP1,
+                                               p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP3));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_CACHES |
+                                           fapi2::TARGET_FILTER_ALL_CORES | fapi2::TARGET_FILTER_ALL_MC |
+                                           fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS |
+                                           fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
+          fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        // Configuring NET control registers into Default required value
+        FAPI_DBG("Restore NET_CTRL0&1 init value - for all chiplets except TP");
+        FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_net_cntl_setup(l_target_cplt));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        // Setting up hang pulse counter for register 0 and register 6
+        FAPI_DBG("Setup hang pulse counter for Mc");
+        FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(l_target_cplt,
+                 p9SbeChipletReset::HANG_PULSE_0X10, 0xff, 0xff, 0xff, 0xff, 0xff,
+                 p9SbeChipletReset::HANG_PULSE_0X08));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        // Setting up hang pulse counter for register 0 and register 6
+        FAPI_DBG("Setup hang pulse counter for Pcie - increase in hang_pulse value");
+        FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(l_target_cplt,
+                 p9SbeChipletReset::HANG_PULSE_0X10, 0xff, 0xff, 0xff, 0xff, 0xff,
+                 p9SbeChipletReset::HANG_PULSE_0X08));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
+                                           fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        // Setting up hang pulse counter for register 0 and register 6
+        FAPI_DBG("Setup hang pulse counter for Xbus,Obus");
+        FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(l_target_cplt,
+                 p9SbeChipletReset::HANG_PULSE_0X10, p9SbeChipletReset::HANG_PULSE_0X04, 0xff,
+                 0xff, 0xff, 0xff, p9SbeChipletReset::HANG_PULSE_0X08));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_NEST, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        // Setting up hang pulse counter for register 5
+        FAPI_DBG("Setup hang pulse counter for nest chiplet");
+        FAPI_TRY(p9_sbe_chiplet_reset_nest_hang_cnt_setup(l_target_cplt));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_CORES, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        // Setting up hang pulse counter for register 5
+        FAPI_DBG("Setup hang pulse counter for core chiplet");
+        FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(l_target_cplt,
+                 p9SbeChipletReset::HANG_PULSE_0X10, p9SbeChipletReset::HANG_PULSE_0X1A, 0xff,
+                 0xff, 0xff, p9SbeChipletReset::HANG_PULSE_0X06,
+                 p9SbeChipletReset::HANG_PULSE_0X08));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_CACHES, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        // Setting up hang pulse counter for register 5
+        FAPI_DBG("Setup hang pulse counter for cache chiplet");
+        FAPI_TRY(p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(l_target_cplt,
+                 p9SbeChipletReset::HANG_PULSE_0X10, p9SbeChipletReset::HANG_PULSE_0X01,
+                 p9SbeChipletReset::HANG_PULSE_0X01, p9SbeChipletReset::HANG_PULSE_0X04,
+                 p9SbeChipletReset::HANG_PULSE_0X00, p9SbeChipletReset::HANG_PULSE_0X06,
+                 p9SbeChipletReset::HANG_PULSE_0X08));
+    }
+
+    FAPI_DBG("Clock mux settings");
+    FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_call(i_target_chip));
+
+    if ( l_attr_vitl_setup )
+    {
+        l_target_state = fapi2::TARGET_STATE_PRESENT;
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_CACHES |
+                                           fapi2::TARGET_FILTER_ALL_CORES | fapi2::TARGET_FILTER_ALL_MC |
+                                           fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS |
+                                           fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), l_target_state))
+    {
+        // Setting up partial good fence drop and resetting chiplet.
+        FAPI_DBG("PLL Setup : Enable pll");
+        FAPI_TRY(p9_sbe_chiplet_reset_pll_setup(l_target_cplt, true));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_NEST_WEST, l_target_state))
+    {
+        FAPI_DBG("Drop clk async reset for N3 chiplet");
+        FAPI_TRY(p9_sbe_chiplet_reset_nest_ob_async_reset(l_target_cplt));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_MC, l_target_state))
+    {
+        FAPI_DBG("Drop clk async reset for Mc chiplet");
+        FAPI_TRY(p9_sbe_chiplet_reset_mc_async_reset_setup(l_target_cplt, true));
+    }
+
+    fapi2::delay(10000, (40 * 400));
+
+    if ( l_attr_vitl_setup )
+    {
+        l_target_state = fapi2::TARGET_STATE_PRESENT;
+
+        for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_CACHES |
+                                               fapi2::TARGET_FILTER_ALL_CORES | fapi2::TARGET_FILTER_ALL_MC |
+                                               fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS |
+                                               fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS), l_target_state))
+        {
+            // Setting up partial good fence drop and resetting chiplet.
+            FAPI_DBG("PLL setup : Disable pll");
+            FAPI_TRY(p9_sbe_chiplet_reset_pll_setup(l_target_cplt, false));
+        }
+
+        for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (fapi2::TARGET_FILTER_ALL_MC, l_target_state))
+        {
+            FAPI_DBG("Raise clk async reset for Mc chiplet");
+            FAPI_TRY(p9_sbe_chiplet_reset_mc_async_reset_setup(l_target_cplt, false));
+        }
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_OBUS, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Drop clk async reset for N3, Mc  and Obus chiplets");
+        FAPI_TRY(p9_sbe_chiplet_reset_nest_ob_async_reset(l_target_cplt));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Drop clk_div_bypass for Mc chiplet");
+        FAPI_TRY(p9_sbe_chiplet_reset_div_clk_bypass(l_target_cplt));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_CACHES |
+                                           fapi2::TARGET_FILTER_ALL_CORES | fapi2::TARGET_FILTER_ALL_MC |
+                                           fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS |
+                                           fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
+          fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Enable chiplet and reset error register");
+        FAPI_TRY(p9_sbe_chiplet_reset_setup(l_target_cplt));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                           fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS |
+                                           fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
+          fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Drop lvltrans fence and endpoint reset");
+        FAPI_TRY(p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset(
+                     l_target_cplt));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                           fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS |
+                                           fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
+          fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Initialize OPCG registers for Nest,MC,XB,OB,PCIe");
+        FAPI_TRY(p9_sbe_chiplet_reset_opcg_cnfg(l_target_cplt));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_NEST |
+                                           fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI |
+                                           fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Enable listen to sync for NEST,OB,XB,PCIe");
+        FAPI_TRY(p9_sbe_chiplet_reset_enable_listen_to_sync(l_target_cplt, true));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                           fapi2::TARGET_FILTER_ALL_OBUS | fapi2::TARGET_FILTER_ALL_PCI |
+                                           fapi2::TARGET_FILTER_XBUS), fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Disable listen_to_sync for Nest,MC,XB,OB,PCIe");
+        FAPI_TRY(p9_sbe_chiplet_reset_enable_listen_to_sync(l_target_cplt, false));
+    }
+
+    FAPI_DBG("Set Chip-wide HSSPORWREN gate");
+    FAPI_TRY(p9_sbe_chiplet_reset_hsspowergate(i_target_chip));
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Setup IOP Logic for PCIe");
+        FAPI_TRY(p9_sbe_chiplet_reset_setup_iop_logic(l_target_cplt));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                           fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS |
+                                           fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
+          fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("set scan ratio to 1:1 ");
+        FAPI_TRY(p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio(l_target_cplt));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                                           fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_ALL_OBUS |
+                                           fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
+          fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_TRY(p9_sbe_chiplet_reset_scan0_call(l_target_cplt));
+    }
+
+    FAPI_INF("p9_sbe_chiplet_reset: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Setting up hang pulse counter for all parital good chiplet except for Tp,nest, core and cache
+///
+/// @param[in]     i_target_cplt   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_reg0_val      value for HANG_PULSE_0_REG
+/// @param[in]     i_reg1_val      value for HANG_PULSE_1_REG
+/// @param[in]     i_reg2_val      value for HANG_PULSE_2_REG
+/// @param[in]     i_reg3_val      value for HANG_PULSE_3_REG
+/// @param[in]     i_reg4_val      value for HANG_PULSE_4_REG
+/// @param[in]     i_reg5_val      value for HANG_PULSE_5_REG
+/// @param[in]     i_reg6_val      Hang pulse reg 6 value - for heartbeat
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt,
+    const uint8_t i_reg0_val,
+    const uint8_t i_reg1_val,
+    const uint8_t i_reg2_val,
+    const uint8_t i_reg3_val,
+    const uint8_t i_reg4_val,
+    const uint8_t i_reg5_val,
+    const uint8_t i_reg6_val)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup: Entering ...");
+
+    //Setting HANG_PULSE_0_REG register value (Setting all fields)
+    if (i_reg0_val != 0xff)
+    {
+        //HANG_PULSE_0_REG.HANG_PULSE_REG_0 = (i_reg0_val != 0xff) ? i_reg0_val
+        l_data64.insertFromRight<0, 6>(i_reg0_val);
+        //HANG_PULSE_0_REG.SUPPRESS_HANG_0 = (i_reg0_val != 0xff) ? 0
+        l_data64.clearBit<6>();
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_0_REG, l_data64));
+    }
+
+    //Setting HANG_PULSE_1_REG register value (Setting all fields)
+    if (i_reg1_val != 0xff)
+    {
+        //HANG_PULSE_1_REG.HANG_PULSE_REG_1 = (i_reg1_val != 0xff) ? i_reg1_val
+        l_data64.insertFromRight<0, 6>(i_reg1_val);
+        //HANG_PULSE_1_REG.SUPPRESS_HANG_1 = (i_reg1_val != 0xff) ? 0
+        l_data64.clearBit<6>();
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_1_REG, l_data64));
+    }
+
+    //Setting HANG_PULSE_2_REG register value (Setting all fields)
+    if (i_reg2_val != 0xff)
+    {
+        //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = (i_reg2_val != 0xff) ? i_reg2_val
+        l_data64.insertFromRight<0, 6>(i_reg2_val);
+        //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = (i_reg2_val != 0xff) ? 0
+        l_data64.clearBit<6>();
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64));
+    }
+
+    //Setting HANG_PULSE_3_REG register value (Setting all fields)
+    if (i_reg3_val != 0xff)
+    {
+        //HANG_PULSE_3_REG.HANG_PULSE_REG_3 = (i_reg3_val != 0xff) ? i_reg3_val
+        l_data64.insertFromRight<0, 6>(i_reg3_val);
+        //HANG_PULSE_3_REG.SUPPRESS_HANG_3 = (i_reg3_val != 0xff) ? 0
+        l_data64.clearBit<6>();
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64));
+    }
+
+    //Setting HANG_PULSE_4_REG register value (Setting all fields)
+    if (i_reg4_val != 0xff)
+    {
+        //HANG_PULSE_4_REG.HANG_PULSE_REG_4 = (i_reg4_val != 0xff) ? i_reg4_val
+        l_data64.insertFromRight<0, 6>(i_reg4_val);
+        //HANG_PULSE_4_REG.SUPPRESS_HANG_4 = (i_reg4_val != 0xff) ? 0
+        l_data64.clearBit<6>();
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_4_REG, l_data64));
+    }
+
+    //Setting HANG_PULSE_5_REG register value (Setting all fields)
+    if (i_reg5_val != 0xff)
+    {
+        //HANG_PULSE_5_REG.HANG_PULSE_REG_5 = (i_reg5_val != 0xff) ? i_reg5_val
+        l_data64.insertFromRight<0, 6>(i_reg5_val);
+        //HANG_PULSE_5_REG.SUPPRESS_HANG_5 = (i_reg5_val != 0xff) ? 0
+        l_data64.clearBit<6>();
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_5_REG, l_data64));
+    }
+
+    //Setting HANG_PULSE_6_REG register value (Setting all fields)
+    if (i_reg6_val != 0xff)
+    {
+        //HANG_PULSE_6_REG.HANG_PULSE_REG_6 = (i_reg6_val != 0xff) ? i_reg6_val
+        l_data64.insertFromRight<0, 6>(i_reg6_val);
+        //HANG_PULSE_6_REG.SUPPRESS_HANG_6 = (i_reg6_val != 0xff) ? 0
+        l_data64.clearBit<6>();
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_6_REG, l_data64));
+    }
+
+    FAPI_INF("p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Configuring NET control registers into Default required value
+///
+/// @param[in]     i_target_cplt   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_net_cntl_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt)
+{
+    fapi2::buffer<uint8_t> l_read_attr;
+    FAPI_INF("p9_sbe_chiplet_reset_all_cplt_net_cntl_setup: Entering ...");
+
+    //Setting NET_CTRL0 register value
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip =
+        i_target_cplt.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+    FAPI_DBG("Disable local clock gating VITAL");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING,
+                           l_chip, l_read_attr));
+
+    if (l_read_attr)
+    {
+        //NET_CTRL0 = p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE_FOR_DD1
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL0,
+                                p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE_FOR_DD1));
+    }
+    else
+    {
+        //NET_CTRL0 = p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL0,
+                                p9SbeChipletReset::NET_CNTL0_HW_INIT_VALUE));
+    }
+
+    //Setting NET_CTRL1 register value
+    //NET_CTRL1 = p9SbeChipletReset::NET_CNTL1_HW_INIT_VALUE
+    FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_NET_CTRL1,
+                            p9SbeChipletReset::NET_CNTL1_HW_INIT_VALUE));
+
+    FAPI_INF("p9_sbe_chiplet_reset_all_cplt_net_cntl_setup:Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief clock mux settings for Mc chiplet
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_clk_mux_value    clock mux value
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_MC(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint32_t> i_clk_mux_value)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_reset_clk_mux_MC: Entering ...");
+
+    //Setting NET_CTRL1 register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
+    //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<3>()
+    l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<3>());
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
+
+    FAPI_INF("p9_sbe_chiplet_reset_clk_mux_MC: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief call all the related mux settings on chiplets
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_call(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet)
+{
+    fapi2::buffer<uint32_t> l_read_attr;
+    FAPI_INF("p9_sbe_chiplet_reset_clk_mux_call: Entering ...");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CLOCK_PLL_MUX, i_target_chiplet,
+                           l_read_attr));
+
+    for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Mux settings for Mc chiplet");
+        FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_MC(l_target_cplt, l_read_attr));
+    }
+
+    for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_OBUS, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Mux settings for OB chiplet");
+        FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_obus(l_target_cplt, l_read_attr));
+    }
+
+    for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_XBUS, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Mux settings for XB chiplet");
+        FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_xbus(l_target_cplt, l_read_attr));
+    }
+
+    for (auto l_target_cplt : i_target_chiplet.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Mux settings for Pcie chiplet");
+        FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_pcie(l_target_cplt, l_read_attr));
+    }
+
+    FAPI_INF("p9_sbe_chiplet_reset_clk_mux_call: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief clock mux settings for OB chiplet
+///
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_clk_mux_value    Clock mux value
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_obus(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint32_t> i_clk_mux_value)
+{
+    uint8_t l_attr_unit_pos = 0;
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_reset_clk_mux_obus: Entering ...");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chiplet,
+                           l_attr_unit_pos));
+
+    if ( l_attr_unit_pos == 0x09 )
+    {
+        //Setting NET_CTRL1 register value
+        FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
+        //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<6>()
+        l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<6>());
+        l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL>
+        (i_clk_mux_value.getBit<13>());  //NET_CTRL1.REFCLK_CLKMUX0_SEL = i_clk_mux_value.getBit<13>()
+        l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL>
+        (i_clk_mux_value.getBit<15>());  //NET_CTRL1.REFCLK_CLKMUX1_SEL = i_clk_mux_value.getBit<15>()
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
+    }
+
+    if ( l_attr_unit_pos == 0x0A )
+    {
+        //Setting NET_CTRL1 register value
+        FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
+        l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>
+        (i_clk_mux_value.getBit<16>());  //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<16>()
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
+    }
+
+    if ( l_attr_unit_pos == 0x0B )
+    {
+        //Setting NET_CTRL1 register value
+        FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
+        l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>
+        (i_clk_mux_value.getBit<17>());  //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<17>()
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
+    }
+
+    if ( l_attr_unit_pos == 0x0C )
+    {
+        //Setting NET_CTRL1 register value
+        FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
+        //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<7>()
+        l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<7>());
+        l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL>
+        (i_clk_mux_value.getBit<9>());  //NET_CTRL1.REFCLK_CLKMUX0_SEL = i_clk_mux_value.getBit<9>()
+        l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL>
+        (i_clk_mux_value.getBit<14>());  //NET_CTRL1.REFCLK_CLKMUX1_SEL = i_clk_mux_value.getBit<14>()
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
+    }
+
+    FAPI_INF("p9_sbe_chiplet_reset_clk_mux_obus: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief clock mux settings for Pcie chiplet
+///
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_clk_mux_value    clock mux value
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_pcie(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint32_t> i_clk_mux_value)
+{
+    uint8_t l_attr_unit_pos = 0;
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_reset_clk_mux_pcie: Entering ...");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chiplet,
+                           l_attr_unit_pos));
+
+    if ( l_attr_unit_pos != 0x0E )
+    {
+        //Setting NET_CTRL1 register value
+        FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
+        l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>((l_attr_unit_pos == 0x0D) ?
+                i_clk_mux_value.getBit<5>() :
+                i_clk_mux_value.getBit<4>());  //NET_CTRL1.PLL_CLKIN_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<5>() :  i_clk_mux_value.getBit<4>()
+
+        if (l_attr_unit_pos == 0x0D)
+        {
+            l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL>
+            (i_clk_mux_value.getBit<10>());  //NET_CTRL1.REFCLK_CLKMUX0_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<10>()
+            l_data64.writeBit<PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL>
+            (i_clk_mux_value.getBit<11>());  //NET_CTRL1.REFCLK_CLKMUX1_SEL = (l_attr_unit_pos == 0x0D)? i_clk_mux_value.getBit<11>()
+        }
+
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
+    }
+
+    FAPI_INF("p9_sbe_chiplet_reset_clk_mux_pcie: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief clock mux settings for XB chiplet
+///
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_clk_mux_value    clock mux value
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_xbus(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint32_t> i_clk_mux_value)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_reset_clk_mux_xbus: Entering ...");
+
+    //Setting NET_CTRL1 register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
+    //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<8>()
+    l_data64.writeBit<PERV_1_NET_CTRL1_PLL_CLKIN_SEL>(i_clk_mux_value.getBit<8>());
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1, l_data64));
+
+    FAPI_INF("p9_sbe_chiplet_reset_clk_mux_xbus: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Drop clk div bypass for Mc chiplet
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_div_clk_bypass(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_reset_div_clk_bypass: Entering ...");
+
+    FAPI_DBG("drop clk_div_bypass_en");
+    //Setting NET_CTRL1 register value
+    l_data64.flush<1>();
+    //NET_CTRL1.CLK_DIV_BYPASS_EN = 0
+    l_data64.clearBit<PERV_1_NET_CTRL1_CLK_DIV_BYPASS_EN>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL1_WAND, l_data64));
+
+    FAPI_INF("p9_sbe_chiplet_reset_div_clk_bypass: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Enable listen_to_sync mode for all chiplets except MC
+///
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_enable           if TRUE - enable, FALSE - disable
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_enable_listen_to_sync(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const bool i_enable)
+{
+    FAPI_INF("p9_sbe_chiplet_reset_enable_listen_to_sync: Entering ...");
+
+    //Setting SYNC_CONFIG register value
+    //SYNC_CONFIG = i_enable? p9SbeChipletReset::SYNC_CONFIG_DEFAULT : p9SbeChipletReset::SYNC_CONFIG_4TO1
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_SYNC_CONFIG,
+                            i_enable ? p9SbeChipletReset::SYNC_CONFIG_DEFAULT :
+                            p9SbeChipletReset::SYNC_CONFIG_4TO1));
+
+    FAPI_INF("p9_sbe_chiplet_reset_enable_listen_to_sync: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Set Chip-wide HSSPORWREN gate
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_hsspowergate(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_read_reg;
+    FAPI_INF("p9_sbe_chiplet_reset_hsspowergate: Entering ...");
+
+    //Getting ROOT_CTRL2 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL2_SCOM,
+                            l_read_reg)); //l_read_reg = PIB.ROOT_CTRL2
+
+    l_read_reg.setBit<20>();
+
+    FAPI_DBG("Set Chip-wide HSSPORWREN gate");
+    //Setting ROOT_CTRL2 register value
+    //PIB.ROOT_CTRL2 = l_read_reg
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL2_SCOM, l_read_reg));
+
+    FAPI_INF("p9_sbe_chiplet_reset_hsspowergate: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Drop/ raise MC async reset
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_drop          Raise/drop mc async reset
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_async_reset_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip,
+    const bool i_drop)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_reset_mc_async_reset_setup: Entering ...");
+
+    if ( i_drop )
+    {
+        FAPI_DBG("Drop mc async reset");
+        //Setting NET_CTRL0 register value
+        l_data64.flush<1>();
+        //NET_CTRL0.CLK_ASYNC_RESET = 0
+        l_data64.clearBit<PERV_1_NET_CTRL0_CLK_ASYNC_RESET>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL0_WAND, l_data64));
+    }
+    else
+    {
+        if ( !(i_target_chip.isFunctional()) )
+        {
+            FAPI_DBG("Raise mc async reset");
+            //Setting NET_CTRL0 register value
+            l_data64.flush<0>();
+            //NET_CTRL0.CLK_ASYNC_RESET = 1
+            l_data64.setBit<PERV_1_NET_CTRL0_CLK_ASYNC_RESET>();
+            FAPI_TRY(fapi2::putScom(i_target_chip, PERV_NET_CTRL0_WOR, l_data64));
+        }
+    }
+
+    FAPI_INF("p9_sbe_chiplet_reset_mc_async_reset_setup: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Configuring multicast registers for nest, cache, core
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_mc_grp1_val      value for MULTICAST_GROUP1 register
+/// @param[in]     i_mc_grp2_val      value for MULTICAST_GROUP2 register
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+        const uint64_t i_mc_grp1_val,
+        const uint64_t i_mc_grp2_val,
+        const uint64_t i_mc_grp3_val)
+{
+    FAPI_INF("p9_sbe_chiplet_reset_mc_setup: Entering ...");
+
+    //Setting MULTICAST_GROUP_1 register value
+    //MULTICAST_GROUP_1 (register) = i_mc_grp1_val
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_1,
+                            i_mc_grp1_val));
+
+    //Setting MULTICAST_GROUP_2 register value
+    if (i_mc_grp2_val != 0x0)
+    {
+        //MULTICAST_GROUP_2 (register) = (i_mc_grp2_val != 0x0) ? i_mc_grp2_val
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_2,
+                                i_mc_grp2_val));
+    }
+
+    //Setting MULTICAST_GROUP_3 register value
+    if (i_mc_grp3_val != 0x0)
+    {
+        //MULTICAST_GROUP_REGISTER_3 = (i_mc_grp3_val != 0x0) ? i_mc_grp3_val
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_3,
+                                i_mc_grp3_val));
+    }
+
+    FAPI_INF("p9_sbe_chiplet_reset_mc_setup: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Multicast register setup for Cache chiplets
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup_cache(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    uint32_t l_attr_pg = 0;
+    FAPI_INF("p9_sbe_chiplet_reset_mc_setup_cache: Entering ...");
+
+    FAPI_DBG("Reading ATTR_PG");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, l_attr_pg));
+
+    FAPI_DBG("Setting Multicast register 1&2 for cache chiplet");
+    //Setting MULTICAST_GROUP_1 register value
+    //MULTICAST_GROUP_1 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_1,
+                            p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0));
+    //Setting MULTICAST_GROUP_2 register value
+    //MULTICAST_GROUP_2 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP4
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_2,
+                            p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP4));
+
+    if ( ( l_attr_pg & 0x1EBA ) == 0x0 ) // Check good EP chiplet clockdomains excluding l31, l21, refr1
+    {
+        FAPI_DBG("Setting up multicast register 3 for even cache chiplet");
+        //Setting MULTICAST_GROUP_3 register value
+        //MULTICAST_GROUP_3 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP5
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_3,
+                                p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP5));
+    }
+
+    if ( ( l_attr_pg & 0x1D76 ) == 0x0 ) // Check good EP chiplet clockdomains excluding l30, l20, refr0
+    {
+        FAPI_DBG("Setting up multicast register 4 for odd cache chiplet");
+        //Setting MULTICAST_GROUP_4 register value
+        //MULTICAST_GROUP_4 (register) = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP6
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_MULTICAST_GROUP_4,
+                                p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP6));
+    }
+
+    FAPI_INF("p9_sbe_chiplet_reset_mc_setup_cache: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Setting up hang pulse counter for partial good Nest chiplet
+///
+/// @param[in]     i_target_cplt   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_nest_hang_cnt_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt)
+{
+    // Local variables
+    //
+    uint8_t   l_attr_chipunit_pos = 0;
+    const uint8_t l_n0 = 0x02;
+    const uint8_t l_n1 = 0x03;
+    const uint8_t l_n2 = 0x04;
+    const uint8_t l_n3 = 0x05;
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_reset_nest_hang_cnt_setup: Entering ...");
+
+    // Collecting partial good and chiplet unit position attribute
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_cplt,
+                           l_attr_chipunit_pos));
+
+    //Setting HANG_PULSE_0_REG register value (Setting all fields)
+    //HANG_PULSE_0_REG.HANG_PULSE_REG_0 = p9SbeChipletReset::HANG_PULSE_0X10
+    l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X10);
+    l_data64.clearBit<6>();  //HANG_PULSE_0_REG.SUPPRESS_HANG_0 = 0
+    FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_0_REG, l_data64));
+    //Setting HANG_PULSE_5_REG register value (Setting all fields)
+    //HANG_PULSE_5_REG.HANG_PULSE_REG_5 = p9SbeChipletReset::HANG_PULSE_0X06
+    l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X06);
+    l_data64.clearBit<6>();  //HANG_PULSE_5_REG.SUPPRESS_HANG_5 = 0
+    FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_5_REG, l_data64));
+    //Setting HANG_PULSE_6_REG register value (Setting all fields)
+    //HANG_PULSE_6_REG.HANG_PULSE_REG_6 = p9SbeChipletReset::HANG_PULSE_0X08
+    l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X08);
+    l_data64.clearBit<6>();  //HANG_PULSE_6_REG.SUPPRESS_HANG_6 = 0
+    FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_6_REG, l_data64));
+
+    if ( l_attr_chipunit_pos == l_n0 )
+    {
+        //Setting HANG_PULSE_1_REG register value (Setting all fields)
+        //HANG_PULSE_1_REG.HANG_PULSE_REG_1 = p9SbeChipletReset::HANG_PULSE_0X18
+        l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X18);
+        l_data64.clearBit<6>();  //HANG_PULSE_1_REG.SUPPRESS_HANG_1 = 0
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_1_REG, l_data64));
+        //Setting HANG_PULSE_2_REG register value (Setting all fields)
+        //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X23
+        l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X23);
+        l_data64.clearBit<6>();  //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 0
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64));
+        //Setting HANG_PULSE_3_REG register value (Setting all fields)
+        //HANG_PULSE_3_REG.HANG_PULSE_REG_3 = p9SbeChipletReset::HANG_PULSE_0X12
+        l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X12);
+        l_data64.clearBit<6>();  //HANG_PULSE_3_REG.SUPPRESS_HANG_3 = 0
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64));
+    }
+
+    if ( l_attr_chipunit_pos == l_n1 )
+    {
+        //Setting HANG_PULSE_2_REG register value (Setting all fields)
+        //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X0F
+        l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X0F);
+        l_data64.clearBit<6>();  //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 0
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64));
+    }
+
+    if ( l_attr_chipunit_pos == l_n2 )
+    {
+        //Setting HANG_PULSE_3_REG register value (Setting all fields)
+        //HANG_PULSE_3_REG.HANG_PULSE_REG_3 = p9SbeChipletReset::HANG_PULSE_0X12
+        l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X12);
+        l_data64.clearBit<6>();  //HANG_PULSE_3_REG.SUPPRESS_HANG_3 = 0
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64));
+    }
+
+    if ( l_attr_chipunit_pos == l_n3 )
+    {
+        //Setting HANG_PULSE_1_REG register value (Setting all fields)
+        //HANG_PULSE_1_REG.HANG_PULSE_REG_1 = p9SbeChipletReset::HANG_PULSE_0X17
+        l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X17);
+        l_data64.clearBit<6>();  //HANG_PULSE_1_REG.SUPPRESS_HANG_1 = 0
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_1_REG, l_data64));
+        //Setting HANG_PULSE_2_REG register value (Setting all fields)
+        //HANG_PULSE_2_REG.HANG_PULSE_REG_2 = p9SbeChipletReset::HANG_PULSE_0X13
+        l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X13);
+        l_data64.clearBit<6>();  //HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 0
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_2_REG, l_data64));
+        //Setting HANG_PULSE_3_REG register value (Setting all fields)
+        //HANG_PULSE_3_REG.HANG_PULSE_REG_3 = p9SbeChipletReset::HANG_PULSE_0X0F
+        l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X0F);
+        l_data64.clearBit<6>();  //HANG_PULSE_3_REG.SUPPRESS_HANG_3 = 0
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_3_REG, l_data64));
+        //Setting HANG_PULSE_4_REG register value (Setting all fields)
+        //HANG_PULSE_4_REG.HANG_PULSE_REG_4 = p9SbeChipletReset::HANG_PULSE_0X1C
+        l_data64.insertFromRight<0, 6>(p9SbeChipletReset::HANG_PULSE_0X1C);
+        l_data64.clearBit<6>();  //HANG_PULSE_4_REG.SUPPRESS_HANG_4 = 0
+        FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_HANG_PULSE_4_REG, l_data64));
+    }
+
+    FAPI_INF("p9_sbe_chiplet_reset_nest_hang_cnt_setup: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Dropping the net_ctrl0 clock_async_reset
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_nest_ob_async_reset(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_reset_nest_ob_async_reset: Entering ...");
+
+    //Setting NET_CTRL0 register value
+    l_data64.flush<1>();
+    //NET_CTRL0.CLK_ASYNC_RESET = 0
+    l_data64.clearBit<PERV_1_NET_CTRL0_CLK_ASYNC_RESET>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64));
+
+    FAPI_INF("p9_sbe_chiplet_reset_nest_ob_async_reset: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Drop Endpoint reset
+/// Drop lvltrans fence
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode
+p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset: Entering ...");
+
+    FAPI_DBG("Drop lvltrans fence");
+    //Setting NET_CTRL0 register value
+    l_data64.flush<1>();
+    //NET_CTRL0.LVLTRANS_FENCE = 0b0
+    l_data64.clearBit<PERV_1_NET_CTRL0_LVLTRANS_FENCE>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64));
+
+    FAPI_DBG("Drop endpoint reset");
+    //Setting NET_CTRL0 register value
+    l_data64.flush<1>();
+    //NET_CTRL0.PCB_EP_RESET = 0b0
+    l_data64.clearBit<PERV_1_NET_CTRL0_PCB_EP_RESET>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64));
+
+    FAPI_INF("p9_sbe_chiplet_reset_net_ctrl_lvltrans_fence_pcb_ep_reset: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief configuring Nest chiplet OPCG registers
+///
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_opcg_cnfg(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_reset_opcg_cnfg: Entering ...");
+
+    //Setting OPCG_ALIGN register value
+    l_data64 =
+        p9SbeChipletReset::OPCG_ALIGN_SETTING;  //OPCG_ALIGN = p9SbeChipletReset::OPCG_ALIGN_SETTING
+    //OPCG_ALIGN.INOP_ALIGN = p9SbeChipletReset::INOP_ALIGN_SETTING_0X5
+    l_data64.insertFromRight<0, 4>(p9SbeChipletReset::INOP_ALIGN_SETTING_0X5);
+    l_data64.clearBit<PERV_1_OPCG_ALIGN_INOP_WAIT, PERV_1_OPCG_ALIGN_INOP_WAIT_LEN>();  //OPCG_ALIGN.INOP_WAIT = 0
+    //OPCG_ALIGN.OPCG_WAIT_CYCLES = p9SbeChipletReset::OPCG_WAIT_CYCLE_0X020
+    l_data64.insertFromRight<52, 12>(p9SbeChipletReset::OPCG_WAIT_CYCLE_0X020);
+    l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN>
+    (p9SbeChipletReset::SCAN_RATIO_0X3);  //OPCG_ALIGN.SCAN_RATIO = p9SbeChipletReset::SCAN_RATIO_0X3
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_ALIGN, l_data64));
+
+    FAPI_INF("p9_sbe_chiplet_reset_opcg_cnfg: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief set scan ratio to 1:1 as long as PLL is in bypass mode
+///
+/// @param[in]     i_target_cplt   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio: Entering ...");
+
+    FAPI_DBG("Set scan ratio to 1:1 as long as PLL is in bypass mode");
+    //Setting OPCG_ALIGN register value
+    FAPI_TRY(fapi2::getScom(i_target_cplt, PERV_OPCG_ALIGN, l_data64));
+    l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN>
+    (p9SbeChipletReset::SCAN_RATIO_0X0);  //OPCG_ALIGN.SCAN_RATIO = p9SbeChipletReset::SCAN_RATIO_0X0
+    FAPI_TRY(fapi2::putScom(i_target_cplt, PERV_OPCG_ALIGN, l_data64));
+
+    FAPI_INF("p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Enable PLL
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_enable           enable/disable pll
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_pll_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const bool i_enable)
+{
+    fapi2::buffer<uint64_t> l_data;;
+    FAPI_INF("p9_sbe_chiplet_reset_pll_setup: Entering ...");
+
+    if ( i_enable )
+    {
+        l_data.flush<0>();
+        l_data.setBit<31>();
+
+        FAPI_DBG("Enable pll");
+        //Setting NET_CTRL0 register value
+        //NET_CTRL0 = l_data
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WOR, l_data));
+    }
+    else
+    {
+        if ( !(i_target_chiplet.isFunctional()) )
+        {
+            l_data.flush<1>();
+            l_data.clearBit<31>();
+
+            FAPI_DBG("Disable PLL");
+            //Setting NET_CTRL0 register value
+            //NET_CTRL0 = l_data
+            FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data));
+        }
+    }
+
+    FAPI_INF("p9_sbe_chiplet_reset_pll_setup: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Scan0 module call
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_scan0_call(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip)
+{
+    fapi2::buffer<uint16_t> l_regions;
+    FAPI_INF("p9_sbe_chiplet_reset_scan0_call: Entering ...");
+
+    FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(i_target_chip,
+             p9SbeChipletReset::REGIONS_EXCEPT_VITAL, l_regions));
+
+    FAPI_DBG("run scan0 module for region except vital and pll, scan types GPTR, TIME, REPR");
+    FAPI_TRY(p9_perv_sbe_cmn_scan0_module(i_target_chip, l_regions,
+                                          p9SbeChipletReset::SCAN_TYPES_TIME_GPTR_REPR));
+
+    FAPI_DBG("run scan0 module for region except vital and pll, scan types except GPTR, TIME, REPR");
+    FAPI_TRY(p9_perv_sbe_cmn_scan0_module(i_target_chip, l_regions,
+                                          p9SbeChipletReset::SCAN_TYPES_EXCEPT_TIME_GPTR_REPR));
+
+    FAPI_INF("p9_sbe_chiplet_reset_scan0_call: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Dorping fence on Partial good chiplet and resetting it.
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_setup(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    // Local variable and constant definition
+    const uint64_t l_error_default_value = 0xFFFFFFFFFFFFFFFFull;
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_reset_setup: Entering ...");
+
+    // EP Reset all chiplet with in multicasting group
+    //Setting NET_CTRL0 register value
+    l_data64.flush<0>();
+    //NET_CTRL0.CHIPLET_ENABLE = 0b1
+    l_data64.setBit<PERV_1_NET_CTRL0_CHIPLET_ENABLE>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WOR, l_data64));
+
+    //Setting ERROR_REG register value
+    //ERROR_REG = l_error_default_value
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_ERROR_REG,
+                            l_error_default_value));
+
+    FAPI_INF("p9_sbe_chiplet_reset_setup: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Setup IOP Logic for PCIe
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_chiplet_reset_setup_iop_logic(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_chiplet_reset_setup_iop_logic: Entering ...");
+
+    //Setting CPLT_CONF1 register value
+    l_data64.flush<0>();
+    l_data64.setBit<30>();  //CPLT_CONF1.TC_IOP_HSSPORWREN = 0b1
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF1_OR, l_data64));
+
+    fapi2::delay(p9SbeChipletReset::HW_NS_DELAY,
+                 p9SbeChipletReset::SIM_CYCLE_DELAY);
+
+    //Setting CPLT_CONF1 register value
+    l_data64.flush<0>();
+    l_data64.setBit<28>();  //CPLT_CONF1.TC_IOP_SYS_RESET_PCS = 0b1
+    l_data64.setBit<29>();  //CPLT_CONF1.TC_IOP_SYS_RESET_PMA = 0b1
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF1_OR, l_data64));
+
+    FAPI_INF("p9_sbe_chiplet_reset_setup_iop_logic:Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H
new file mode 100644
index 00000000..feeec54b
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H
@@ -0,0 +1,125 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_chiplet_reset.H
+///
+/// @brief Steps:-
+///     1) Identify Partical good chiplet and configure Multicasting register
+///     2) Similar way, Configure hang pulse counter for Nest/MC/OBus/XBus/PCIe
+///     3) Similar way,  set fence for Nest and MC chiplet
+///     4) Similar way,  Reset sys.config and OPCG setting for Nest and MC chiplet in sync mode
+///
+/// Done
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V. Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_CHIPLET_RESET_H_
+#define _P9_SBE_CHIPLET_RESET_H_
+
+
+#include <fapi2.H>
+
+
+namespace p9SbeChipletReset
+{
+enum P9_SBE_CHIPLET_RESET_Public_Constants
+{
+    MCGR_CNFG_SETTING_GROUP0 = 0xE0001C0000000000ull,
+    MCGR_CNFG_SETTING_GROUP1 = 0xE4001C0000000000ull,
+    MCGR_CNFG_SETTING_GROUP2 = 0xE8001C0000000000ull,
+    MCGR_CNFG_SETTING_GROUP3 = 0xEC001C0000000000ull,
+    MCGR_CNFG_SETTING_GROUP4 = 0xF0001C0000000000ull,
+    MCGR_CNFG_SETTING_GROUP5 = 0xF4001C0000000000ull,
+    MCGR_CNFG_SETTING_GROUP6 = 0xF8001C0000000000ull,
+    NET_CNTL0_HW_INIT_VALUE = 0x7C06222000000000ull,
+    NET_CNTL0_HW_INIT_VALUE_FOR_DD1 = 0x7C16222000000000ull,
+    HANG_PULSE_0X10 = 0x10,
+    HANG_PULSE_0X0F = 0x0F,
+    HANG_PULSE_0X06 = 0x06,
+    HANG_PULSE_0X17 = 0x17,
+    HANG_PULSE_0X18 = 0x18,
+    HANG_PULSE_0X22 = 0x22,
+    HANG_PULSE_0X23 = 0x23,
+    HANG_PULSE_0X13 = 0x13,
+    HANG_PULSE_0X03 = 0x03,
+    OPCG_ALIGN_SETTING = 0x5000000000003020ull,
+    INOP_ALIGN_SETTING_0X5 = 0x5,
+    OPCG_WAIT_CYCLE_0X020 = 0x020,
+    SCAN_RATIO_0X3 = 0x3,
+    SYNC_PULSE_DELAY_0X0 = 0X00,
+    SYNC_CONFIG_DEFAULT = 0X0000000000000000,
+    HANG_PULSE_0X00 = 0x00,
+    HANG_PULSE_0X01 = 0x01,
+    HANG_PULSE_0X04 = 0x04,
+    HANG_PULSE_0X1A = 0x1A,
+    NET_CNTL1_HW_INIT_VALUE = 0x7200000000000000ull,
+    REGIONS_EXCEPT_VITAL = 0x7FF,
+    SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCE,
+    SCAN_TYPES_TIME_GPTR_REPR = 0x230,
+    SCAN_RATIO_0X0 = 0x0,
+    SYNC_CONFIG_4TO1 = 0X0800000000000000,
+    HW_NS_DELAY = 200000, // unit is nano seconds
+    SIM_CYCLE_DELAY = 10000, // unit is cycles
+    HANG_PULSE_0X12 = 0x12,
+    HANG_PULSE_0X1C = 0x1C,
+    HANG_PULSE_0X08 = 0x08
+};
+}
+
+typedef fapi2::ReturnCode (*p9_sbe_chiplet_reset_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief Identify all good chiplets excluding EQ/EC
+///  -- All chiplets will be reset and PLLs started
+///  -- Partial bad - All nest Chiplets must be good, MC, IO can be partial bad
+/// Setup multicast groups for all chiplets
+///  -- Can't use the multicast for all non-nest chiplets
+///  -- This is intended to be the eventual product setting
+///  -- This includes the core/cache chiplets
+/// For all good chiplets excluding EQ/EC
+/// -- Setup Chiplet GP3 regs
+///  -- Reset to default state
+///  -- Set chiplet enable on all all good chiplets excluding EQ/EC
+/// For all enabled chiplets excluding EQ/EC/Buses
+///  -- Start vital clocks and release endpoint reset
+///  -- PCB Slave error register Reset
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_chiplet_reset(const
+                                           fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.C
new file mode 100644
index 00000000..3a8a765c
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.C
@@ -0,0 +1,53 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.C $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_clock_test2.C
+///
+/// @brief sbe_clock_test2 for enabling osc-check
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumarj8@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 1
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_clock_test2.H"
+
+
+
+fapi2::ReturnCode p9_sbe_clock_test2(const
+                                     fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet)
+{
+    FAPI_INF("Entering ...");
+
+    FAPI_INF("Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.H
new file mode 100644
index 00000000..180d8c66
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_clock_test2.H $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_clock_test2.H
+///
+/// @brief sbe_clock_test2 for enabling osc-check
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumarj8@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 1
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_CLOCK_TEST2_H_
+#define _P9_SBE_CLOCK_TEST2_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_clock_test2_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief enable osc checking
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_clock_test2(const
+                                         fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C
new file mode 100644
index 00000000..c9586829
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C
@@ -0,0 +1,658 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_common.C $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_common.C
+///
+/// @brief Common Modules for SBE
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_common.H"
+//## auto_generated
+#include "p9_const_common.H"
+
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
+#include <p9_const_common.H>
+
+
+enum P9_SBE_COMMON_Private_Constants
+{
+    NS_DELAY = 100000, // unit in nano seconds
+    SIM_CYCLE_DELAY = 1000, // unit in cycles
+    CPLT_ALIGN_CHECK_POLL_COUNT = 10, // count to wait for chiplet aligned
+    CPLT_OPCG_DONE_DC_POLL_COUNT = 10 // count to wait for chiplet opcg done
+};
+
+/// @brief --For all chiplets exit flush
+/// --For all chiplets enable alignment
+/// --For all chiplets disable alignemnt
+///
+/// @param[in]     i_target_chiplets   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_sbe_common_align_chiplets(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    int l_timeout = 0;
+    FAPI_INF("p9_sbe_common_align_chiplets: Entering ...");
+
+    FAPI_DBG("For all chiplets: exit flush");
+    //Setting CPLT_CTRL0 register value
+    l_data64.flush<0>();
+    //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 1
+    l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_OR, l_data64));
+
+    FAPI_DBG("For all chiplets: enable alignement");
+    //Setting CPLT_CTRL0 register value
+    l_data64.flush<0>();
+    //CPLT_CTRL0.CTRL_CC_FORCE_ALIGN_DC = 1
+    l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_OR, l_data64));
+
+    FAPI_DBG("Clear chiplet is aligned");
+    //Setting SYNC_CONFIG register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64));
+    //SYNC_CONFIG.CLEAR_CHIPLET_IS_ALIGNED = 0b1
+    l_data64.setBit<PERV_1_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64));
+
+    FAPI_DBG("Unset Clear chiplet is aligned");
+    //Setting SYNC_CONFIG register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64));
+    //SYNC_CONFIG.CLEAR_CHIPLET_IS_ALIGNED = 0b0
+    l_data64.clearBit<PERV_1_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_SYNC_CONFIG, l_data64));
+
+    fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
+
+    FAPI_DBG("Poll OPCG done bit to check for run-N completeness");
+    l_timeout = CPLT_ALIGN_CHECK_POLL_COUNT;
+
+    //UNTIL CPLT_STAT0.CC_CTRL_CHIPLET_IS_ALIGNED_DC == 1
+    while (l_timeout != 0)
+    {
+        //Getting CPLT_STAT0 register value
+        FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_CPLT_STAT0, l_data64));
+        bool l_poll_data =
+            l_data64.getBit<PERV_1_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC>();  //bool l_poll_data = CPLT_STAT0.CC_CTRL_CHIPLET_IS_ALIGNED_DC
+
+        if (l_poll_data == 1)
+        {
+            break;
+        }
+
+        fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
+        --l_timeout;
+    }
+
+    FAPI_DBG("Loop Count :%d", l_timeout);
+
+    FAPI_ASSERT(l_timeout > 0,
+                fapi2::CPLT_NOT_ALIGNED_ERR(),
+                "ERROR:CHIPLET NOT ALIGNED");
+
+    FAPI_DBG("For all chiplets: disable alignement");
+    //Setting CPLT_CTRL0 register value
+    l_data64.flush<0>();
+    //CPLT_CTRL0.CTRL_CC_FORCE_ALIGN_DC = 0
+    l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_CPLT_CTRL0_CLEAR, l_data64));
+
+    FAPI_INF("p9_sbe_common_align_chiplets: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief To do check on Clock controller status for chiplets
+///
+/// @param[in]     i_target        Reference to TARGET_TYPE_PERV target Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_clock_cmd     Issue clock controller command (START/STOP)
+/// @param[in]     i_regions       Enable required REGIONS
+/// @param[in]     i_clock_types   Clock Types to be selected (SL/NSL/ARY)
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_sbe_common_check_cc_status_function(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target,
+    const fapi2::buffer<uint8_t> i_clock_cmd,
+    const fapi2::buffer<uint16_t> i_regions,
+    const fapi2::buffer<uint8_t> i_clock_types)
+{
+    bool l_reg_sl = false;
+    bool l_reg_nsl = false;
+    bool l_reg_ary = false;
+    fapi2::buffer<uint64_t> l_sl_clock_status;
+    fapi2::buffer<uint64_t> l_nsl_clock_status;
+    fapi2::buffer<uint64_t> l_ary_clock_status;
+    fapi2::buffer<uint16_t> l_sl_clkregion_status;
+    fapi2::buffer<uint16_t> l_nsl_clkregion_status;
+    fapi2::buffer<uint16_t> l_ary_clkregion_status;
+    fapi2::buffer<uint16_t> l_regions;
+    FAPI_INF("p9_sbe_common_check_cc_status_function: Entering ...");
+
+    l_reg_sl = i_clock_types.getBit<5>();
+    l_reg_nsl = i_clock_types.getBit<6>();
+    l_reg_ary = i_clock_types.getBit<7>();
+    i_regions.extractToRight<5, 11>(l_regions);
+
+    if ( l_reg_sl )
+    {
+        FAPI_DBG("Check for Clocks running SL");
+        //Getting CLOCK_STAT_SL register value
+        FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL,
+                                l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL
+        FAPI_DBG("SL Clock status register is %#018lX", l_sl_clock_status);
+
+        if ( i_clock_cmd == 0b01 )
+        {
+            FAPI_DBG("Checking for clock start command");
+            l_sl_clkregion_status.flush<1>();
+            l_sl_clock_status.extractToRight<4, 11>(l_sl_clkregion_status);
+            l_sl_clkregion_status.invert();
+            l_sl_clkregion_status &= l_regions;
+
+            FAPI_ASSERT(l_sl_clkregion_status == l_regions,
+                        fapi2::NEST_SL_ERR()
+                        .set_READ_CLK_SL(l_sl_clock_status),
+                        "Clock running for sl type not matching with expected values");
+        }
+
+        if ( i_clock_cmd == 0b10 )
+        {
+            FAPI_DBG("Checking for clock stop command");
+            l_sl_clkregion_status.flush<0>();
+            l_sl_clock_status.extractToRight<4, 11>(l_sl_clkregion_status);
+            l_sl_clkregion_status &= l_regions;
+
+            FAPI_ASSERT(l_sl_clkregion_status == l_regions,
+                        fapi2::NEST_SL_ERR()
+                        .set_READ_CLK_SL(l_sl_clock_status),
+                        "Clock running for sl type not matching with expected values");
+        }
+    }
+
+    if ( l_reg_nsl )
+    {
+        FAPI_DBG("Check for clocks running NSL");
+        //Getting CLOCK_STAT_NSL register value
+        FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_NSL,
+                                l_nsl_clock_status)); //l_nsl_clock_status = CLOCK_STAT_NSL
+        FAPI_DBG("NSL Clock status register is %#018lX", l_nsl_clock_status);
+
+        if ( i_clock_cmd == 0b01 )
+        {
+            FAPI_DBG("Checking for clock start command");
+            l_nsl_clkregion_status.flush<1>();
+            l_nsl_clock_status.extractToRight<4, 11>(l_nsl_clkregion_status);
+            l_nsl_clkregion_status.invert();
+            l_nsl_clkregion_status &= l_regions;
+
+            FAPI_ASSERT(l_nsl_clkregion_status == l_regions,
+                        fapi2::NEST_NSL_ERR()
+                        .set_READ_CLK_NSL(l_nsl_clock_status),
+                        "Clock running for nsl type not matching with expected values");
+        }
+
+        if ( i_clock_cmd == 0b10 )
+        {
+            FAPI_DBG("Checking for clock stop command");
+            l_nsl_clkregion_status.flush<0>();
+            l_nsl_clock_status.extractToRight<4, 11>(l_nsl_clkregion_status);
+            l_nsl_clkregion_status &= l_regions;
+
+            FAPI_ASSERT(l_nsl_clkregion_status == l_regions,
+                        fapi2::NEST_NSL_ERR()
+                        .set_READ_CLK_NSL(l_nsl_clock_status),
+                        "Clock running for nsl type not matching with expected values");
+        }
+    }
+
+    if ( l_reg_ary )
+    {
+        FAPI_DBG("Check for clocks running ARY");
+        //Getting CLOCK_STAT_ARY register value
+        FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY,
+                                l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY
+        FAPI_DBG("ARY Clock status register is %#018lX", l_ary_clock_status);
+
+        if ( i_clock_cmd == 0b01 )
+        {
+            FAPI_DBG("Checking for clock start command");
+            l_ary_clkregion_status.flush<1>();
+            l_ary_clock_status.extractToRight<4, 11>(l_ary_clkregion_status);
+            l_ary_clkregion_status.invert();
+            l_ary_clkregion_status &= l_regions;
+
+            FAPI_ASSERT(l_ary_clkregion_status == l_regions,
+                        fapi2::NEST_ARY_ERR()
+                        .set_READ_CLK_ARY(l_ary_clock_status),
+                        "Clock running for ary type not matching with expected values");
+        }
+
+        if ( i_clock_cmd == 0b10 )
+        {
+            FAPI_DBG("Checking for clock stop command");
+            l_ary_clkregion_status.flush<0>();
+            l_ary_clock_status.extractToRight<4, 11>(l_ary_clkregion_status);
+            l_ary_clkregion_status &= l_regions;
+
+            FAPI_ASSERT(l_ary_clkregion_status == l_regions,
+                        fapi2::NEST_ARY_ERR()
+                        .set_READ_CLK_ARY(l_ary_clock_status),
+                        "Clock running for ary type not matching with expected values");
+        }
+    }
+
+    FAPI_INF("p9_sbe_common_check_cc_status_function: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief --check checkstop register
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_sbe_common_check_checkstop_function(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    fapi2::buffer<uint64_t> l_read_reg;
+    FAPI_INF("p9_sbe_common_check_checkstop_function: Entering ...");
+
+    FAPI_DBG("Check checkstop register");
+    //Getting XFIR register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_XFIR,
+                            l_read_reg)); //l_read_reg = XFIR
+
+    FAPI_ASSERT(l_read_reg == 0,
+                fapi2::READ_ALL_CHECKSTOP_ERR()
+                .set_READ_ALL_CHECKSTOP(l_read_reg),
+                "ERROR: COMBINE ALL CHECKSTOP ERROR");
+
+    FAPI_INF("p9_sbe_common_check_checkstop_function: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief check clocks status
+///
+/// @param[in]     i_regions            regions from upper level input
+/// @param[in]     i_clock_status       clock status
+/// @param[in]     i_reg                bit status
+/// @param[in]     i_clock_cmd          clock command
+/// @param[out]    o_exp_clock_status   expected clock status
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_sbe_common_check_status(const fapi2::buffer<uint64_t>
+        i_regions,
+        const fapi2::buffer<uint64_t> i_clock_status,
+        const bool i_reg,
+        const fapi2::buffer<uint8_t> i_clock_cmd,
+        fapi2::buffer<uint64_t>& o_exp_clock_status)
+{
+    FAPI_INF("p9_sbe_common_check_status: Entering ...");
+
+    if ( (i_reg) && (i_clock_cmd == 0b01) )
+    {
+        o_exp_clock_status = i_clock_status & (~(i_regions << 49));
+    }
+    else
+    {
+        if ( (i_reg) && (i_clock_cmd == 0b10) )
+        {
+            o_exp_clock_status = i_clock_status | (i_regions << 49);
+        }
+        else
+        {
+            o_exp_clock_status = i_clock_status;
+        }
+    }
+
+    FAPI_INF("p9_sbe_common_check_status: Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
+
+/// @brief -- Utility function that can be used to start clocks for a specific input regions
+/// -- i_regions is to input regions
+///
+///
+/// @param[in]     i_target        Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_clock_cmd     Issue clock controller command (START/STOP)
+/// @param[in]     i_startslave    Bit to configure to start Slave
+/// @param[in]     i_startmaster   Bit to configure to start Master
+/// @param[in]     i_regions       Enable required REGIONS
+/// @param[in]     i_clock_types   Clock Types to be selected (SL/NSL/ARY)
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_sbe_common_clock_start_stop(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target,
+        const fapi2::buffer<uint8_t> i_clock_cmd,
+        const bool i_startslave,
+        const bool i_startmaster,
+        const fapi2::buffer<uint64_t> i_regions,
+        const fapi2::buffer<uint8_t> i_clock_types)
+{
+    fapi2::buffer<uint64_t> l_sl_clock_status;
+    fapi2::buffer<uint64_t> l_nsl_clock_status;
+    fapi2::buffer<uint64_t> l_ary_clock_status;
+    fapi2::buffer<uint64_t> l_exp_sl_clock_status;
+    fapi2::buffer<uint64_t> l_exp_nsl_clock_status;
+    fapi2::buffer<uint64_t> l_exp_ary_clock_status;
+    fapi2::buffer<uint8_t> l_clk_cmd;
+    fapi2::buffer<uint16_t> l_regions;
+    fapi2::buffer<uint8_t> l_reg_all;
+    bool l_reg_sl = false;
+    bool l_reg_nsl = false;
+    bool l_reg_ary = false;
+    fapi2::buffer<uint64_t> l_data64;
+    int l_timeout = 0;
+    FAPI_INF("p9_sbe_common_clock_start_stop: Entering ...");
+
+    i_regions.extractToRight<53, 11>(l_regions);
+    i_clock_types.extractToRight<5, 3>(l_reg_all);
+    l_reg_sl = i_clock_types.getBit<5>();
+    l_reg_nsl = i_clock_types.getBit<6>();
+    l_reg_ary = i_clock_types.getBit<7>();
+
+    FAPI_DBG("Chiplet exit flush");
+    //Setting CPLT_CTRL0 register value
+    l_data64.flush<0>();
+    //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 1
+    l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC>();
+    FAPI_TRY(fapi2::putScom(i_target, PERV_CPLT_CTRL0_OR, l_data64));
+
+    FAPI_DBG("Clear Scan region type register");
+    //Setting SCAN_REGION_TYPE register value
+    //SCAN_REGION_TYPE = 0
+    FAPI_TRY(fapi2::putScom(i_target, PERV_SCAN_REGION_TYPE, 0));
+
+    FAPI_DBG("Reading the initial status of clock controller");
+    //Getting CLOCK_STAT_SL register value
+    FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL,
+                            l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL
+    //Getting CLOCK_STAT_NSL register value
+    FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_NSL,
+                            l_nsl_clock_status)); //l_nsl_clock_status = CLOCK_STAT_NSL
+    //Getting CLOCK_STAT_ARY register value
+    FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY,
+                            l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY
+    FAPI_DBG("Clock status of SL_Register:%#018lX NSL_Register:%#018lX ARY_Register:%#018lX",
+             l_sl_clock_status, l_nsl_clock_status, l_ary_clock_status);
+
+    i_clock_cmd.extractToRight<6, 2>(l_clk_cmd);
+
+    FAPI_DBG("Setup all Clock Domains and Clock Types");
+    //Setting CLK_REGION register value
+    FAPI_TRY(fapi2::getScom(i_target, PERV_CLK_REGION, l_data64));
+    l_data64.insertFromRight<PERV_1_CLK_REGION_CLOCK_CMD, PERV_1_CLK_REGION_CLOCK_CMD_LEN>
+    (l_clk_cmd);  //CLK_REGION.CLOCK_CMD = l_clk_cmd
+    //CLK_REGION.SLAVE_MODE = i_startslave
+    l_data64.writeBit<PERV_1_CLK_REGION_SLAVE_MODE>(i_startslave);
+    //CLK_REGION.MASTER_MODE = i_startmaster
+    l_data64.writeBit<PERV_1_CLK_REGION_MASTER_MODE>(i_startmaster);
+    //CLK_REGION.CLOCK_REGION_ALL_UNITS = l_regions
+    l_data64.insertFromRight<4, 11>(l_regions);
+    //CLK_REGION.SEL_THOLD_ALL = l_reg_all
+    l_data64.insertFromRight<48, 3>(l_reg_all);
+    FAPI_TRY(fapi2::putScom(i_target, PERV_CLK_REGION, l_data64));
+
+    // To wait until OPCG Done - CPLT_STAT0.cc_cplt_opcg_done_dc = 1
+    FAPI_DBG("Poll OPCG done bit to check for completeness");
+    l_data64.flush<0>();
+    l_timeout = CPLT_OPCG_DONE_DC_POLL_COUNT;
+
+    while (l_timeout != 0)
+    {
+        //Getting CPLT_STAT0 register value
+        FAPI_TRY(fapi2::getScom(i_target, PERV_CPLT_STAT0, l_data64));
+        bool l_poll_data =
+            l_data64.getBit<PERV_1_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC>();
+
+        if (l_poll_data == 1)
+        {
+            break;
+        }
+
+        fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
+        --l_timeout;
+    }
+
+    FAPI_DBG("Loop Count after CPLT_OPCG_DONE_DC polling:%d", l_timeout);
+
+    FAPI_ASSERT(l_timeout > 0,
+                fapi2::CPLT_OPCG_DONE_NOT_SET_ERR(),
+                "ERROR:CHIPLET OPCG DONE NOT SET AFTER CLOCK START STOP CMD");
+
+    //To do do checking only for chiplets that dont have Master-slave mode enabled
+
+    if ( !i_startslave && !i_startmaster )
+    {
+        // Calculating the Expected clock status
+
+        FAPI_TRY(p9_sbe_common_check_status(i_regions, l_sl_clock_status, l_reg_sl,
+                                            i_clock_cmd, l_exp_sl_clock_status));
+
+        FAPI_TRY(p9_sbe_common_check_status(i_regions, l_nsl_clock_status, l_reg_nsl,
+                                            i_clock_cmd, l_exp_nsl_clock_status));
+
+        FAPI_TRY(p9_sbe_common_check_status(i_regions, l_ary_clock_status, l_reg_ary,
+                                            i_clock_cmd, l_exp_ary_clock_status));
+
+        FAPI_DBG("Check for clocks running SL");
+        //Getting CLOCK_STAT_SL register value
+        FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_SL,
+                                l_sl_clock_status)); //l_sl_clock_status = CLOCK_STAT_SL
+        FAPI_DBG("Expected value is %#018lX, Actaul value is %#018lX",
+                 l_exp_sl_clock_status, l_sl_clock_status);
+
+        FAPI_ASSERT(l_sl_clock_status == l_exp_sl_clock_status,
+                    fapi2::SL_ERR()
+                    .set_READ_CLK_SL(l_sl_clock_status),
+                    "CLOCK RUNNING STATUS FOR SL TYPE NOT MATCHING WITH EXPECTED VALUES");
+
+        FAPI_DBG("Check for clocks running NSL");
+        //Getting CLOCK_STAT_NSL register value
+        FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_NSL,
+                                l_nsl_clock_status)); //l_nsl_clock_status = CLOCK_STAT_NSL
+        FAPI_DBG("Expected value is %#018lX, Actaul value is %#018lX",
+                 l_exp_nsl_clock_status, l_nsl_clock_status);
+
+        FAPI_ASSERT(l_nsl_clock_status == l_exp_nsl_clock_status,
+                    fapi2::NSL_ERR()
+                    .set_READ_CLK_NSL(l_nsl_clock_status),
+                    "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR NSL TYPE");
+
+        FAPI_DBG("Check for clocks running ARY");
+        //Getting CLOCK_STAT_ARY register value
+        FAPI_TRY(fapi2::getScom(i_target, PERV_CLOCK_STAT_ARY,
+                                l_ary_clock_status)); //l_ary_clock_status = CLOCK_STAT_ARY
+        FAPI_DBG("Expected value is %#018lX, Actaul value is %#018lX",
+                 l_exp_ary_clock_status, l_ary_clock_status);
+
+        FAPI_ASSERT(l_ary_clock_status == l_exp_ary_clock_status,
+                    fapi2::ARY_ERR()
+                    .set_READ_CLK_ARY(l_ary_clock_status),
+                    "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR ARRAY TYPE");
+    }
+
+    FAPI_INF("p9_sbe_common_clock_start_stop: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief --drop vital fence
+/// --reset abstclk muxsel,syncclk_muxsel
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_attr_pg          ATTR_PG for the corresponding chiplet
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_sbe_common_cplt_ctrl_action_function(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint32_t> i_attr_pg)
+{
+    // Local variable and constant definition
+    fapi2::buffer <uint16_t> l_cplt_ctrl_init;
+    fapi2::buffer<uint32_t> l_attr_pg;
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_common_cplt_ctrl_action_function: Entering ...");
+
+    l_attr_pg = i_attr_pg;
+    l_attr_pg.invert();
+    l_attr_pg.extractToRight<20, 11>(l_cplt_ctrl_init);
+
+    // Not needed as have only nest chiplet (no dual clock controller) Bit 62 ->0
+    //
+    FAPI_DBG("Drop partial good fences");
+    //Setting CPLT_CTRL1 register value
+    l_data64.flush<0>();
+    l_data64.writeBit<PERV_1_CPLT_CTRL1_TC_VITL_REGION_FENCE>
+    (l_attr_pg.getBit<19>());  //CPLT_CTRL1.TC_VITL_REGION_FENCE = l_attr_pg.getBit<19>()
+    //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = l_cplt_ctrl_init
+    l_data64.insertFromRight<4, 11>(l_cplt_ctrl_init);
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL1_CLEAR, l_data64));
+
+    FAPI_DBG("reset abistclk_muxsel and syncclk_muxsel");
+    //Setting CPLT_CTRL0 register value
+    l_data64.flush<0>();
+    //CPLT_CTRL0.CTRL_CC_ABSTCLK_MUXSEL_DC = 1
+    l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC>();
+    //CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 1
+    l_data64.setBit<PERV_1_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64));
+
+    FAPI_INF("p9_sbe_common_cplt_ctrl_action_function: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief will force all chiplets out of flush
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_sbe_common_flushmode(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_common_flushmode: Entering ...");
+
+    FAPI_DBG("Clear flush_inhibit to go in to flush mode");
+    //Setting CPLT_CTRL0 register value
+    l_data64.flush<0>();
+    //CPLT_CTRL0.CTRL_CC_FLUSHMODE_INH_DC = 0
+    l_data64.setBit<PERV_1_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL0_CLEAR, l_data64));
+
+    FAPI_INF("p9_sbe_common_flushmode: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief get children for all chiplets : Perv, Nest
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PERV target
+/// @param[out]    o_pg_vector     vector of targets
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_sbe_common_get_pg_vector(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip,
+        fapi2::buffer<uint64_t>& o_pg_vector)
+{
+    fapi2::buffer<uint8_t> l_read_attrunitpos;
+    FAPI_INF("p9_sbe_common_get_pg_vector: Entering ...");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chip,
+                           l_read_attrunitpos));
+
+    if (    l_read_attrunitpos == 0x01 )
+    {
+        o_pg_vector.setBit<0>();
+    }
+
+    if ( l_read_attrunitpos == 0x02 )
+    {
+        o_pg_vector.setBit<1>();
+    }
+
+    if (    l_read_attrunitpos == 0x03 )
+    {
+        o_pg_vector.setBit<2>();
+    }
+
+    if (    l_read_attrunitpos == 0x04 )
+    {
+        o_pg_vector.setBit<3>();
+    }
+
+    if (    l_read_attrunitpos == 0x05 )
+    {
+        o_pg_vector.setBit<4>();
+    }
+
+    FAPI_INF("p9_sbe_common_get_pg_vector: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief --Setting Scan ratio
+///
+/// @param[in]     i_target_chiplets   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_sbe_common_set_scan_ratio(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_common_set_scan_ratio: Entering ...");
+
+    //Setting OPCG_ALIGN register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplets, PERV_OPCG_ALIGN, l_data64));
+    l_data64.insertFromRight<PERV_1_OPCG_ALIGN_SCAN_RATIO, PERV_1_OPCG_ALIGN_SCAN_RATIO_LEN>
+    (0xE0);  //OPCG_ALIGN.SCAN_RATIO = 0xE0
+    FAPI_TRY(fapi2::putScom(i_target_chiplets, PERV_OPCG_ALIGN, l_data64));
+
+    FAPI_INF("p9_sbe_common_set_scan_ratio: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H
new file mode 100644
index 00000000..f3876594
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.H
@@ -0,0 +1,90 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_common.H $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_common.H
+///
+/// @brief Common Modules for SBE
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_COMMON_H_
+#define _P9_SBE_COMMON_H_
+
+
+#include <fapi2.H>
+
+
+fapi2::ReturnCode p9_sbe_common_align_chiplets(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets);
+
+fapi2::ReturnCode p9_sbe_common_check_cc_status_function(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target,
+    const fapi2::buffer<uint8_t> i_clock_cmd,
+    const fapi2::buffer<uint16_t> i_regions,
+    const fapi2::buffer<uint8_t> i_clock_types);
+
+fapi2::ReturnCode p9_sbe_common_check_checkstop_function(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+fapi2::ReturnCode p9_sbe_common_check_status(const fapi2::buffer<uint64_t>
+        i_regions,
+        const fapi2::buffer<uint64_t> i_clock_status,
+        const bool i_reg,
+        const fapi2::buffer<uint8_t> i_clock_cmd,
+        fapi2::buffer<uint64_t>& o_exp_clock_status);
+
+fapi2::ReturnCode p9_sbe_common_clock_start_allRegions(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_anychiplet);
+
+fapi2::ReturnCode p9_sbe_common_clock_start_stop(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target,
+        const fapi2::buffer<uint8_t> i_clock_cmd,
+        const bool i_startslave,
+        const bool i_startmaster,
+        const fapi2::buffer<uint64_t> i_regions,
+        const fapi2::buffer<uint8_t> i_clock_types);
+
+fapi2::ReturnCode p9_sbe_common_cplt_ctrl_action_function(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint32_t> i_attr_pg);
+
+fapi2::ReturnCode p9_sbe_common_flushmode(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+fapi2::ReturnCode p9_sbe_common_get_pg_vector(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip,
+        fapi2::buffer<uint64_t>& o_pg_vector);
+
+fapi2::ReturnCode p9_sbe_common_set_scan_ratio(const
+        fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplets);
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.C
new file mode 100644
index 00000000..d9a3f2d5
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.C
@@ -0,0 +1,53 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_enable_seeprom.C
+///
+/// @brief SBE enable SEEPROM (runs from OTPROM)
+///
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_enable_seeprom.H"
+fapi2::ReturnCode p9_sbe_enable_seeprom(const
+                                        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    FAPI_DBG("p9_sbe_enable_seeprom: Entering ...");
+
+    FAPI_DBG("p9_sbe_enable_seeprom: Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.H
new file mode 100644
index 00000000..00a5ebc6
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.H
@@ -0,0 +1,67 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_enable_seeprom.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_enable_seeprom.H
+///
+/// @brief SBE enable SEEPROM (runs from OTPROM)
+///
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_ENABLE_SEEPROM_H_
+#define _P9_SBE_ENABLE_SEEPROM_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_enable_seeprom_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief  -- Check SBE Vital Register for selected SEEPROM image
+///  -- Update SBE FI2C_E0_PARAM register
+///  -- Check for valid SEEPROM image
+///  -- Branch to SEEPROM
+///
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_enable_seeprom(const
+                                            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C
new file mode 100644
index 00000000..25d61ad0
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C
@@ -0,0 +1,154 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_gear_switcher.C
+///
+/// @brief Modules for I2C Bit rate divisor setting
+/// And stop sequence on I2C
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_gear_switcher.H"
+
+#include "p9_misc_scom_addresses.H"
+#include "p9_perv_scom_addresses.H"
+
+
+enum P9_SBE_GEAR_SWITCHER_Private_Constants
+{
+    DEFAULT_MB_BIT_RATE_DIVISOR = 0x00000000,
+    BUS_STATUS_BUSY_POLL_COUNT = 64
+};
+
+/// @brief --adjust I2C bit rate divisor setting in I2CM B mode reg
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_read_scratch_reg = 0;
+    uint16_t l_mb_bit_rate_divisor = 0;
+    FAPI_DBG("Entering ...");
+
+    FAPI_INF("Check Mailbox for Valid I2C bit rate divisor setting");
+    //Getting SCRATCH_REGISTER_2 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM,
+                            l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_2
+
+    if ( !l_read_scratch_reg )
+    {
+        FAPI_INF("Set with Default value if Mailbox empty");
+        //Setting MODE_REGISTER_B register value
+        //PIB.MODE_REGISTER_B = DEFAULT_MB_BIT_RATE_DIVISOR
+        FAPI_TRY(fapi2::putScom(i_target_chip, PU_MODE_REGISTER_B,
+                                DEFAULT_MB_BIT_RATE_DIVISOR));
+    }
+    else
+    {
+        l_read_scratch_reg.extractToRight<0, 16>(l_mb_bit_rate_divisor);
+
+        FAPI_INF("Adjust I2C bit rate divisor setting in I2CM B Mode Reg");
+        //Setting MODE_REGISTER_B register value
+        //PIB.MODE_REGISTER_B = l_mb_bit_rate_divisor
+        FAPI_TRY(fapi2::putScom(i_target_chip, PU_MODE_REGISTER_B,
+                                l_mb_bit_rate_divisor));
+    }
+
+    FAPI_DBG("Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief --send a stop sequence on I2C
+/// --poll for stop command completion
+/// --check for magic number
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_sbe_gear_switcher_i2c_stop_sequence(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    uint8_t l_read_attr = 0;
+    fapi2::buffer<uint64_t> l_data64;
+    int l_timeout = 0;
+    FAPI_DBG("Entering ...");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BACKUP_SEEPROM_SELECT, i_target_chip,
+                           l_read_attr));
+
+    // WRITE Control register
+    // enable enhance mode
+    // Point to port_0 where the Primary SEEPROM Sits
+    FAPI_INF("Send a STOP sequence on I2C");
+    //Setting CONTROL_REGISTER_B register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PU_CONTROL_REGISTER_B, l_data64));
+    l_data64.setBit<3>();  //PIB.CONTROL_REGISTER_B.PIB_CNTR_REG_BIT_WITHSTOP_0 = 1
+    //PIB.CONTROL_REGISTER_B.PIB_CNTR_REG_PORT_NUMBER_0 = l_read_attr
+    l_data64.insertFromRight<18, 5>(l_read_attr);
+    l_data64.setBit<26>();  //PIB.CONTROL_REGISTER_B.ENH_MODE_0 = 1
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_CONTROL_REGISTER_B, l_data64));
+
+    FAPI_INF("Poll for stop command completion");
+    l_timeout = BUS_STATUS_BUSY_POLL_COUNT;
+
+    //UNTIL STATUS_REGISTER_B.BUS_STATUS_BUSY_0 == 0
+    while (l_timeout != 0)
+    {
+        //Getting STATUS_REGISTER_B register value
+        FAPI_TRY(fapi2::getScom(i_target_chip, PU_STATUS_REGISTER_B, l_data64));
+        //bool l_poll_data = PIB.STATUS_REGISTER_B.BUS_STATUS_BUSY_0
+        bool l_poll_data = l_data64.getBit<44>();
+
+        if (l_poll_data == 0)
+        {
+            break;
+        }
+
+        --l_timeout;
+    }
+
+    FAPI_INF("Loop Count :%d", l_timeout);
+
+    FAPI_ASSERT(l_timeout > 0,
+                fapi2::BUS_STATUS_BUSY_0(),
+                "ERROR:BUS_STSTUS_BUSY_0 NOT SET TO 0");
+
+    FAPI_DBG("Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.H
new file mode 100644
index 00000000..845b68e9
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.H
@@ -0,0 +1,53 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.H $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_gear_switcher.H
+///
+/// @brief Modules for I2C Bit rate divisor setting
+/// And stop sequence on I2C
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_GEAR_SWITCHER_H_
+#define _P9_SBE_GEAR_SWITCHER_H_
+
+
+#include <fapi2.H>
+
+
+fapi2::ReturnCode p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+
+fapi2::ReturnCode p9_sbe_gear_switcher_i2c_stop_sequence(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.C
new file mode 100644
index 00000000..ce8302a9
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.C
@@ -0,0 +1,288 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_gptr_time_initf.C
+///
+/// @brief Load time and GPTR rings for all enabled chiplets
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+#include "p9_sbe_gptr_time_initf.H"
+
+#include "p9_perv_scom_addresses.H"
+
+
+fapi2::ReturnCode p9_sbe_gptr_time_initf(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below
+
+    FAPI_INF("p9_sbe_gptr_time_initf: Entering ...");
+
+    for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST>
+         (fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Scan mc_gptr ring");
+        FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_gptr),
+                 "Error from putRing (mc_gptr)");
+        FAPI_DBG("Scan mc_iom01_gptr ring");
+        FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom01_gptr),
+                 "Error from putRing (mc_iom01_gptr)");
+        FAPI_DBG("Scan mc_iom23_gptr ring");
+        FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom23_gptr),
+                 "Error from putRing (mc_iom23_gptr)");
+        FAPI_DBG("Scan mc_pll_gptr ring");
+        FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_pll_gptr),
+                 "Error from putRing (mc_pll_gptr)");
+        FAPI_DBG("Scan mc_time ring");
+        FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_time),
+                 "Error from putRing (mc_time)");
+    }
+
+    for( auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         ( fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_attr_chip_unit_pos));
+
+        if ((l_attr_chip_unit_pos == 0x9))/* OBUS0 Chiplet */
+        {
+            FAPI_DBG("Scan ob0_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob0_gptr),
+                     "Error from putRing (ob0_gptr)");
+            FAPI_DBG("Scan ob0_pll_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob0_pll_gptr),
+                     "Error from putRing (ob0_pll_gptr)");
+            FAPI_DBG("Scan ob0_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob0_time),
+                     "Error from putRing (ob0_time)");
+        }
+
+        if ((l_attr_chip_unit_pos == 0xA))/* OBUS1 Chiplet */
+        {
+            FAPI_DBG("Scan ob1_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob1_gptr),
+                     "Error from putRing (ob1_gptr)");
+            FAPI_DBG("Scan ob1_pll_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob1_pll_gptr),
+                     "Error from putRing (ob1_pll_gptr)");
+            FAPI_DBG("Scan ob1_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob1_time),
+                     "Error from putRing (ob1_time)");
+        }
+
+        if ((l_attr_chip_unit_pos == 0xB))/* OBUS2 Chiplet */
+        {
+            FAPI_DBG("Scan ob2_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob2_gptr),
+                     "Error from putRing (ob2_gptr)");
+            FAPI_DBG("Scan ob2_pll_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob2_pll_gptr),
+                     "Error from putRing (ob2_pll_gptr)");
+            FAPI_DBG("Scan ob2_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob2_time),
+                     "Error from putRing (ob2_time)");
+        }
+
+        if ((l_attr_chip_unit_pos == 0xC))/* OBUS3 Chiplet */
+        {
+            FAPI_DBG("Scan ob3_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob3_gptr),
+                     "Error from putRing (ob3_gptr)");
+            FAPI_DBG("Scan ob3_pll_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob3_pll_gptr),
+                     "Error from putRing (ob3_pll_gptr)");
+            FAPI_DBG("Scan ob3_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob3_time),
+                     "Error from putRing (ob3_time)");
+        }
+
+        if ((l_attr_chip_unit_pos == 0x6))/* XBUS Chiplet */
+        {
+            FAPI_DBG("Scan xb_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, xb_gptr),
+                     "Error from putRing (xb_gptr)");
+            FAPI_DBG("Scan xb_io1_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, xb_io1_gptr),
+                     "Error from putRing (xb_io1_gptr)");
+            FAPI_DBG("Scan xb_io2_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, xb_io2_gptr),
+                     "Error from putRing (xb_io2_gptr)");
+            FAPI_DBG("Scan xb_pll_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, xb_pll_gptr),
+                     "Error from putRing (xb_pll_gptr)");
+            FAPI_DBG("Scan xb_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, xb_time),
+                     "Error from putRing (xb_time)");
+            FAPI_DBG("Scan xb_io1_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, xb_io1_time),
+                     "Error from putRing (xb_io1_time)");
+            FAPI_DBG("Scan xb_io2_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, xb_io2_time),
+                     "Error from putRing (xb_io2_time)");
+        }
+
+        if ((l_attr_chip_unit_pos == 0xD))/* PCI0 Chiplet */
+        {
+            FAPI_DBG("Scan pci0_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, pci0_gptr),
+                     "Error from putRing (pci0_gptr)");
+            FAPI_DBG("Scan pci0_pll_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, pci0_pll_gptr),
+                     "Error from putRing (pci0_pll_gptr)");
+            FAPI_DBG("Scan pci0_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, pci0_time),
+                     "Error from putRing (pci0_time)");
+        }
+
+        if ((l_attr_chip_unit_pos == 0xE))/* PCI1 Chiplet */
+        {
+            FAPI_DBG("Scan pci1_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, pci1_gptr),
+                     "Error from putRing (pci1_gptr)");
+            FAPI_DBG("Scan pci1_pll_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, pci1_pll_gptr),
+                     "Error from putRing (pci1_pll_gptr)");
+            FAPI_DBG("Scan pci1_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, pci1_time),
+                     "Error from putRing (pci1_time)");
+        }
+
+        if ((l_attr_chip_unit_pos == 0xF))/* PCI2 Chiplet */
+        {
+            FAPI_DBG("Scan pci2_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, pci2_gptr),
+                     "Error from putRing (pci2_gptr)");
+            FAPI_DBG("Scan pci2_pll_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, pci2_pll_gptr),
+                     "Error from putRing (pci2_pll_gptr)");
+            FAPI_DBG("Scan pci2_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, pci2_time),
+                     "Error from putRing (pci2_time)");
+        }
+
+        if ((l_attr_chip_unit_pos == 0x2))/* N0 Chiplet */
+        {
+            FAPI_DBG("Scan n0_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n0_gptr),
+                     "Error from putRing (n0_gptr)");
+            FAPI_DBG("Scan n0_nx_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n0_nx_gptr),
+                     "Error from putRing (n0_nx_gptr)");
+            FAPI_DBG("Scan n0_cxa0_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n0_cxa0_gptr),
+                     "Error from putRing (n0_cxa0_gptr)");
+            FAPI_DBG("Scan n0_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n0_time),
+                     "Error from putRing (n0_time)");
+            FAPI_DBG("Scan n0_nx_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n0_nx_time),
+                     "Error from putRing (n0_nx_time)");
+            FAPI_DBG("Scan n0_cxa0_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n0_cxa0_time),
+                     "Error from putRing (n0_cxa0_time)");
+        }
+
+        if ((l_attr_chip_unit_pos == 0x3))/* N1 Chiplet */
+        {
+            FAPI_DBG("Scan n1_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_gptr),
+                     "Error from putRing (n1_gptr)");
+            FAPI_DBG("Scan n1_ioo0_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo0_gptr),
+                     "Error from putRing (n1_ioo0_gptr)");
+            FAPI_DBG("Scan n1_ioo1_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo1_gptr),
+                     "Error from putRing (n1_ioo1_gptr)");
+            FAPI_DBG("Scan n1_mcs23_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_mcs23_gptr),
+                     "Error from putRing (n1_mcs23_gptr)");
+            FAPI_DBG("Scan n1_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_time),
+                     "Error from putRing (n1_time)");
+            FAPI_DBG("Scan n1_ioo0_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo0_time),
+                     "Error from putRing (n1_ioo0_time)");
+            FAPI_DBG("Scan n1_ioo1_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo1_time),
+                     "Error from putRing (n1_ioo1_time)");
+            FAPI_DBG("Scan n1_mcs23_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_mcs23_time),
+                     "Error from putRing (n1_mcs23_time)");
+        }
+
+        if ((l_attr_chip_unit_pos == 0x4))/* N2 Chiplet */
+        {
+            FAPI_DBG("Scan n2_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n2_gptr),
+                     "Error from putRing (n2_gptr)");
+            FAPI_DBG("Scan n2_psi_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n2_psi_gptr),
+                     "Error from putRing (n2_psi_gptr)");
+            FAPI_DBG("Scan n2_cxa1_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n2_cxa1_gptr),
+                     "Error from putRing (n2_cxa1_gptr)");
+            FAPI_DBG("Scan n2_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n2_time),
+                     "Error from putRing (n2_time)");
+            FAPI_DBG("Scan n2_cxa1_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n2_cxa1_time),
+                     "Error from putRing (n2_cxa1_time)");
+        }
+
+        if ((l_attr_chip_unit_pos == 0x5))/* N3 Chiplet */
+        {
+            FAPI_DBG("Scan n3_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n3_gptr),
+                     "Error from putRing (n3_gptr)");
+            FAPI_DBG("Scan n3_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n3_time),
+                     "Error from putRing (n3_time)");
+            FAPI_DBG("Scan n3_np_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n3_np_gptr),
+                     "Error from putRing (n3_np_gptr)");
+            FAPI_DBG("Scan n3_mcs01_gptr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n3_mcs01_gptr),
+                     "Error from putRing (n3_mcs01_gptr)");
+            FAPI_DBG("Scan n3_mcs01_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n3_mcs01_time),
+                     "Error from putRing (n3_mcs01_time)");
+            FAPI_DBG("Scan n3_np_time ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n3_np_time),
+                     "Error from putRing (n3_np_time)");
+        }
+    }
+
+fapi_try_exit:
+    FAPI_INF("p9_sbe_gptr_time_initf: Exiting ...");
+    return fapi2::current_err;
+
+}
+
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H
new file mode 100644
index 00000000..5a048f1d
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H
@@ -0,0 +1,60 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_initf.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_gptr_time_initf.H
+///
+/// @brief Load time and GPTR rings for all enabled chiplets
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+#ifndef _P9_SBE_GPTR_TIME_INITF_H_
+#define _P9_SBE_GPTR_TIME_INITF_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_gptr_time_initf_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief Scan  all rings on all enabled chiplets (except for TP)
+/// Load Time and GPTR rings for all enabled chiplets
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_gptr_time_initf(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.C
new file mode 100644
index 00000000..ff4bde17
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.C
@@ -0,0 +1,130 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_gptr_time_repr_initf.C
+///
+/// @brief Scan0 and Load repair, time and GPTR rings for all enabled chiplets
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_gptr_time_repr_initf.H"
+
+#include "p9_perv_scom_addresses.H"
+#include "p9_perv_sbe_cmn.H"
+
+
+enum P9_SBE_GPTR_TIME_REPR_INITF_Private_Constants
+{
+    REGIONS_EXCEPT_VITAL = 0x7FF,
+    SCAN_TYPES_TIME_GPTR_REPR = 0x230
+};
+
+static fapi2::ReturnCode
+p9_sbe_gptr_time_repr_initf_scan0_and_ring_module_function(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+fapi2::ReturnCode p9_sbe_gptr_time_repr_initf(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    auto l_perv_functional_vector =
+        i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+        (fapi2::TARGET_STATE_FUNCTIONAL);
+    FAPI_DBG("Entering ...");
+
+    for (auto l_chplt_trgt : l_perv_functional_vector)
+    {
+        uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt,
+                               l_attr_chip_unit_pos));
+
+        if (!((l_attr_chip_unit_pos == 0x07
+               || l_attr_chip_unit_pos == 0x08/* McChiplet */) ||
+              (l_attr_chip_unit_pos == 0x02 || l_attr_chip_unit_pos == 0x03
+               || l_attr_chip_unit_pos == 0x04
+               || l_attr_chip_unit_pos == 0x05/* NestChiplet */) ||
+              (l_attr_chip_unit_pos == 0x09 || l_attr_chip_unit_pos == 0x0A
+               || l_attr_chip_unit_pos == 0x0B
+               || l_attr_chip_unit_pos == 0x0C/* ObusChiplet */) ||
+              (l_attr_chip_unit_pos == 0x0D || l_attr_chip_unit_pos == 0x0E
+               || l_attr_chip_unit_pos == 0x0F/* PcieChiplet */) ||
+              (l_attr_chip_unit_pos == 0x06/* XbusChiplet */)))
+        {
+            continue;
+        }
+
+        FAPI_INF("Call sbe_gptr_time_repr_initf_scan0_and_ring_module_function");
+        FAPI_TRY(p9_sbe_gptr_time_repr_initf_scan0_and_ring_module_function(
+                     l_chplt_trgt));
+    }
+
+    FAPI_DBG("Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Scan 0 on time, repair, gptr on all enabled chiplets
+/// scan initialize GPTR,TIME and REPR Rings
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode
+p9_sbe_gptr_time_repr_initf_scan0_and_ring_module_function(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    bool l_read_reg = false;
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_DBG("Entering ...");
+
+    FAPI_INF("Check for chiplet enable");
+    //Getting NET_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL0, l_data64));
+    l_read_reg = l_data64.getBit<0>();  //l_read_reg = NET_CTRL0.CHIPLET_ENABLE
+
+    if ( l_read_reg )
+    {
+        FAPI_INF("run scan0 module for regions except vital scan types GPTR, TIME, REPR");
+        FAPI_TRY(p9_perv_sbe_cmn_scan0_module(i_target_chiplet, REGIONS_EXCEPT_VITAL,
+                                              SCAN_TYPES_TIME_GPTR_REPR));
+
+
+        //TODO:Load Ring Module : Scan initialize PLL BNDY chain
+    }
+
+    FAPI_DBG("Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.H
new file mode 100644
index 00000000..da24195e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.H
@@ -0,0 +1,61 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_gptr_time_repr_initf.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_gptr_time_repr_initf.H
+///
+/// @brief Scan0 and Load repair, time and GPTR rings for all enabled chiplets
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_GPTR_TIME_REPR_INITF_H_
+#define _P9_SBE_GPTR_TIME_REPR_INITF_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_gptr_time_repr_initf_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief Scan 0 all rings on all enabled chiplets (except for TP)
+/// Load Repair, Time and GPTR rings for all enabled chiplets
+///       -- All chip customization data is within the repair and time rings -- array repair, DTS setting
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_gptr_time_repr_initf(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.C
new file mode 100644
index 00000000..00e00d24
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.C
@@ -0,0 +1,134 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.C $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_io_initf.C
+///
+/// @brief Initialize necessary latches in IP chiplets
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_io_initf.H"
+#include "p9_perv_scom_addresses.H"
+#include "p9_perv_scom_addresses_fld.H"
+
+fapi2::ReturnCode p9_sbe_io_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    FAPI_INF("p9_sbe_io_initf: Entering ...");
+    uint8_t l_attr_chip_unit_pos = 0;
+
+    for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_attr_chip_unit_pos));
+
+#if 0
+        {
+            // PCIx FURE rings require deterministic scan enable
+            // no current plan to scan these during mainline IPL, but recipe is below if needed
+            fapi2::buffer<uint64_t> l_data64;
+            l_data64.setBit<PERV_1_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC>();
+
+            if (l_attr_chip_unit_pos == 0xD)/* PCI0 Chiplet */
+            {
+                FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI0_CPLT_CTRL0_OR, l_data64));
+                FAPI_DBG("Scan pci0_fure ring");
+                FAPI_TRY(fapi2::putRing(i_target_chip, pci0_fure),
+                         "Error from putRing (pci0_fure)");
+                FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI0_CPLT_CTRL0_CLEAR, l_data64));
+            }
+
+            if (l_attr_chip_unit_pos == 0xE)/* PCI1 Chiplet */
+            {
+                FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI1_CPLT_CTRL0_OR, l_data64));
+                FAPI_DBG("Scan pci1_fure ring");
+                FAPI_TRY(fapi2::putRing(i_target_chip, pci1_fure),
+                         "Error from putRing (pci1_fure)");
+                FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI1_CPLT_CTRL0_CLEAR, l_data64));
+            }
+
+            if (l_attr_chip_unit_pos == 0xF)/* PCI2 Chiplet */
+            {
+                FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI2_CPLT_CTRL0_OR, l_data64));
+                FAPI_DBG("Scan pci2_fure ring");
+                FAPI_TRY(fapi2::putRing(i_target_chip, pci2_fure),
+                         "Error from putRing (pci2_fure)");
+                FAPI_TRY(fapi2::putScom(l_target_chip, PERV_PCI2_CPLT_CTRL0_CLEAR, l_data64));
+            }
+        }
+#endif
+
+        if (l_attr_chip_unit_pos == 0x9)/* OBUS0 Chiplet */
+        {
+            FAPI_DBG("Scan ob0_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob0_fure),
+                     "Error from putRing (ob0_fure)");
+        }
+
+        if (l_attr_chip_unit_pos == 0xA)/* OBUS1 Chiplet */
+        {
+            FAPI_DBG("Scan ob1_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob1_fure),
+                     "Error from putRing (ob1_fure)");
+        }
+
+        if (l_attr_chip_unit_pos == 0xB)/* OBUS2 Chiplet */
+        {
+            FAPI_DBG("Scan ob2_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob2_fure),
+                     "Error from putRing (ob2_fure)");
+        }
+
+        if (l_attr_chip_unit_pos == 0xC)/* OBUS3 Chiplet */
+        {
+            FAPI_DBG("Scan ob3_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob3_fure),
+                     "Error from putRing (ob3_fure)");
+        }
+
+        if (l_attr_chip_unit_pos == 0x6)/* XBUS Chiplet */
+        {
+            FAPI_DBG("Scan xb_io1_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, xb_io1_fure),
+                     "Error from putRing (xb_io1_fure)");
+            FAPI_DBG("Scan xb_io2_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, xb_io2_fure),
+                     "Error from putRing (xb_io2_fure)");
+            FAPI_DBG("Scan xb_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, xb_fure),
+                     "Error from putRing (xb_fure)");
+        }
+    }
+
+fapi_try_exit:
+    FAPI_INF("p9_sbe_io_initf: Exiting ...");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.H
new file mode 100644
index 00000000..c1f186bd
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.H
@@ -0,0 +1,58 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_io_initf.H $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_io_initf.H
+///
+/// @brief Initialize necessary latches in IP chiplets
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 1
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_IO_INITF_H_
+#define _P9_SBE_IO_INITF_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_io_initf_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief Apply init file for IO (Xbus, Abus and Pcie) chiplets.
+///
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_io_initf(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplet);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C
new file mode 100644
index 00000000..25336c49
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C
@@ -0,0 +1,73 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_lpc_init.C
+///
+/// @brief procedure to initialize LPC to enable communictation to PNOR
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_lpc_init.H"
+
+#include "p9_perv_scom_addresses.H"
+#include "p9_perv_scom_addresses_fld.H"
+
+fapi2::ReturnCode p9_sbe_lpc_init(const
+                                  fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_DBG("p9_sbe_lpc_init: Entering ...");
+
+    // set LPC clock mux select to internal clock
+    //Setting CPLT_CTRL0 register value
+    l_data64.flush<0>();
+    l_data64.setBit<1>();  //PERV.CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 1
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_CPLT_CTRL0_OR, l_data64));
+
+    // set LPC clock mux select to external clock
+    //Setting CPLT_CTRL0 register value
+    l_data64.flush<0>();
+    l_data64.setBit<1>();  //PERV.CPLT_CTRL0.TC_UNIT_SYNCCLK_MUXSEL_DC = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_CPLT_CTRL0_CLEAR, l_data64));
+
+    //Settting registers to do an LPC functional reset
+    l_data64.flush<0>().setBit<CPLT_CONF1_TC_LP_RESET>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_N3_CPLT_CONF1_OR, l_data64));
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_N3_CPLT_CONF1_CLEAR, l_data64));
+
+    FAPI_DBG("p9_sbe_lpc_init: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H
new file mode 100644
index 00000000..eabe73f1
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.H $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_lpc_init.H
+///
+/// @brief procedure to initialize LPC to enable communictation to PNOR
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_LPC_INIT_H_
+#define _P9_SBE_LPC_INIT_H_
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_lpc_init_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief LPC init to enable connection to PNOR
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    const uint32_t CPLT_CONF1_TC_LP_RESET = 12;
+    fapi2::ReturnCode p9_sbe_lpc_init(const
+                                      fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.C
new file mode 100644
index 00000000..63bbe75e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.C
@@ -0,0 +1,113 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_nest_enable_ridi.C
+///
+/// @brief Enable ridi controls for NEST logic
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_nest_enable_ridi.H"
+
+#include "p9_perv_scom_addresses.H"
+
+static fapi2::ReturnCode p9_sbe_nest_enable_ridi_net_ctrl_action_function(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+fapi2::ReturnCode p9_sbe_nest_enable_ridi(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    auto l_perv_functional_vector =
+        i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+        (fapi2::TARGET_STATE_FUNCTIONAL);
+    FAPI_DBG("p9_sbe_nest_enable_ridi: Entering ...");
+
+    for (auto l_chplt_trgt : l_perv_functional_vector)
+    {
+        uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt,
+                               l_attr_chip_unit_pos));
+
+        if (!((l_attr_chip_unit_pos == 0x07
+               || l_attr_chip_unit_pos == 0x08/* McChiplet */) ||
+              (l_attr_chip_unit_pos == 0x02 || l_attr_chip_unit_pos == 0x03
+               || l_attr_chip_unit_pos == 0x04
+               || l_attr_chip_unit_pos == 0x05/* NestChiplet */)))
+        {
+            continue;
+        }
+
+        FAPI_INF("Call p9_sbe_nest_enable_ridi_net_ctrl_action_function");
+        FAPI_TRY(p9_sbe_nest_enable_ridi_net_ctrl_action_function(l_chplt_trgt));
+    }
+
+    FAPI_DBG("p9_sbe_nest_enable_ridi: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Enable Drivers/Recievers of Nest chiplet
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_nest_enable_ridi_net_ctrl_action_function(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    bool l_read_reg = false;
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_DBG("p9_sbe_nest_enable_ridi_net_ctrl_action_function: Entering ...");
+
+    FAPI_INF("Check for chiplet enable");
+    //Getting NET_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL0, l_data64));
+    l_read_reg = l_data64.getBit<0>();  //l_read_reg = NET_CTRL0.CHIPLET_ENABLE
+
+    if ( l_read_reg )
+    {
+        FAPI_INF("Enable Recievers, Drivers DI1 & DI2");
+        //Setting NET_CTRL0 register value
+        l_data64.flush<0>();
+        l_data64.setBit<19>();  //NET_CTRL0.RI_N = 1
+        l_data64.setBit<20>();  //NET_CTRL0.DI1_N = 1
+        l_data64.setBit<21>();  //NET_CTRL0.DI2_N = 1
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WOR, l_data64));
+    }
+
+    FAPI_DBG("p9_sbe_nest_enable_ridi_net_ctrl_action_function: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.H
new file mode 100644
index 00000000..6c7b2dfb
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_enable_ridi.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_nest_enable_ridi.H
+///
+/// @brief Enable ridi controls for NEST logic
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_NEST_ENABLE_RIDI_H_
+#define _P9_SBE_NEST_ENABLE_RIDI_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_nest_enable_ridi_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief Enable Drivers/Receivers of Nest Chiplet
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_nest_enable_ridi(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C
new file mode 100644
index 00000000..434e0137
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C
@@ -0,0 +1,135 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.C $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_nest_initf.C
+///
+/// @brief Scan rings for Nest and Mc chiplets
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_nest_initf.H"
+#include "p9_perv_scom_addresses.H"
+#include "p9_perv_scom_addresses_fld.H"
+
+fapi2::ReturnCode p9_sbe_nest_initf(const
+                                    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    FAPI_INF("Entering ...");
+    uint8_t l_attr_chip_unit_pos = 0;
+
+    for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_attr_chip_unit_pos));
+
+        if (l_attr_chip_unit_pos == 0x2)/* N0 Chiplet */
+        {
+            FAPI_DBG("Scan n0_cxa_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n0_cxa0_fure),
+                     "Error from putRing (n0_cxa0_fure)");
+            FAPI_DBG("Scan n0_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n0_fure),
+                     "Error from putRing (n0_fure)");
+            FAPI_DBG("Scan n0_nx_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n0_nx_fure),
+                     "Error from putRing (n0_nx_fure)");
+        }
+
+        if (l_attr_chip_unit_pos == 0x3)/* N1 Chiplet */
+        {
+            FAPI_DBG("Scan n1_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_fure),
+                     "Error from putRing (n1_fure)");
+            FAPI_DBG("Scan n1_ioo0_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo0_fure),
+                     "Error from putRing (n1_ioo0_fure)");
+            FAPI_DBG("Scan n1_ioo1_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo1_fure),
+                     "Error from putRing (n1_ioo1_fure)");
+            FAPI_DBG("Scan n1_mcs23_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_mcs23_fure),
+                     "Error from putRing (n1_mcs23_fure)");
+        }
+
+        if (l_attr_chip_unit_pos == 0x4)/* N2 Chiplet */
+        {
+            FAPI_DBG("Scan n2_cxa1_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n2_cxa1_fure),
+                     "Error from putRing (n2_cxa1_fure)");
+            FAPI_DBG("Scan n2_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n2_fure),
+                     "Error from putRing (n2_fure)");
+            FAPI_DBG("Scan n2_psi_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n2_psi_fure),
+                     "Error from putRing (n2_psi_fure)");
+        }
+
+        if (l_attr_chip_unit_pos == 0x05)/* N3 Chiplet */
+        {
+            FAPI_DBG("Scan n3_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n3_fure),
+                     "Error from putRing (n3_fure)");
+            FAPI_DBG("Scan n3_mcs01_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n3_mcs01_fure),
+                     "Error from putRing (n3_mcs01_fure)");
+            FAPI_DBG("Scan n3_np_fure ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n3_np_fure),
+                     "Error from putRing (n3_np_fure)");
+        }
+    }
+
+    for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST>(fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_fure));
+#if 0
+        {
+            // MC IOMxx FURE rings require deterministic scan enable
+            // no current plan to scan these during mainline IPL, but recipe is below if needed
+            fapi2::buffer<uint64_t> l_data64;
+            l_data64.setBit<PERV_1_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC>();
+            FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_MC01_CPLT_CTRL0_OR, l_data64));
+            FAPI_DBG("Scan mc_iom01_fure ring");
+            FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom01_fure),
+                     "Error from putRing (mc_iom01_fure)");
+            FAPI_DBG("Scan mc_iom23_fure ring");
+            FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_iom23_fure),
+                     "Error from putRing (mc_iom23_fure)");
+            FAPI_TRY(fapi2::putScom(l_chplt_trgt, PERV_MC01_CPLT_CTRL0_CLEAR, l_data64));
+        }
+#endif
+
+    }
+
+fapi_try_exit:
+    FAPI_INF("Exiting ...");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.H
new file mode 100644
index 00000000..90a8321e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.H
@@ -0,0 +1,58 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_initf.H $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_nest_initf.C
+///
+/// @brief Scan rings for Nest and Mc chiplets
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+#ifndef _P9_SBE_NEST_INITF_H_
+#define _P9_SBE_NEST_INITF_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_nest_initf_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief apply init file
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_nest_initf(const
+                                        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C
new file mode 100644
index 00000000..d0737f78
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C
@@ -0,0 +1,388 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_nest_startclocks.C
+///
+/// @brief start PB and Nest clocks
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_nest_startclocks.H"
+//## auto_generated
+#include "p9_const_common.H"
+
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
+#include <p9_perv_sbe_cmn.H>
+#include <p9_sbe_common.H>
+
+
+enum P9_SBE_NEST_STARTCLOCKS_Private_Constants
+{
+    CLOCK_CMD = 0x1,
+    STARTSLAVE = 0x1,
+    STARTMASTER = 0x1,
+    REGIONS_ALL_EXCEPT_VITAL_NESTPLL = 0x7FE,
+    CLOCK_TYPES = 0x7,
+    DONT_STARTMASTER = 0x0,
+    DONT_STARTSLAVE = 0x0
+};
+
+static fapi2::ReturnCode p9_sbe_nest_startclocks_N3_fence_drop(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint64_t> i_pg_vector);
+
+static fapi2::ReturnCode p9_sbe_nest_startclocks_get_attr_pg(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    fapi2::buffer<uint32_t>& o_attr_pg);
+
+static fapi2::ReturnCode p9_sbe_nest_startclocks_mc_fence_drop(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint64_t> i_pg_vector);
+
+static fapi2::ReturnCode p9_sbe_nest_startclocks_nest_fence_drop(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint64_t> i_pg_vector);
+
+fapi2::ReturnCode p9_sbe_nest_startclocks(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    uint8_t l_read_attr = 0;
+    fapi2::buffer<uint8_t> l_read_flush_attr;
+    fapi2::buffer<uint32_t> l_attr_pg;
+    fapi2::buffer<uint64_t> l_pg_vector;
+    fapi2::buffer<uint64_t> l_clock_regions;
+    fapi2::buffer<uint64_t> l_n3_clock_regions;
+    fapi2::buffer<uint16_t> l_ccstatus_regions;
+    fapi2::buffer<uint16_t> l_n3_ccstatus_regions;
+    FAPI_INF("p9_sbe_nest_startclocks: Entering ...");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_N3_FLUSH_MODE, i_target_chip,
+                           l_read_flush_attr));
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_NEST |
+                                           fapi2::TARGET_FILTER_TP), fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_TRY(p9_sbe_common_get_pg_vector(l_target_cplt, l_pg_vector));
+        FAPI_DBG("pg targets vector: %#018lX", l_pg_vector);
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_NEST_WEST, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_target_cplt,
+                 REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_n3_clock_regions));
+        FAPI_DBG("pg targets vector: %#018lX", l_pg_vector);
+
+        FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(l_target_cplt,
+                 REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_n3_ccstatus_regions));
+        FAPI_DBG("pg targets vector: %#018lX", l_pg_vector);
+    }
+
+    FAPI_INF("Reading ATTR_MC_SYNC_MODE");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr));
+
+    fapi2::TargetFilter l_nest_filter, l_nest_tp_filter, l_dd1_filter_without_N3;
+
+    if (l_read_attr)
+    {
+        l_nest_filter = static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC |
+                        fapi2::TARGET_FILTER_ALL_NEST);
+        l_nest_tp_filter = static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_MC
+                           | fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_TP);
+        l_dd1_filter_without_N3 = static_cast<fapi2::TargetFilter>
+                                  (fapi2::TARGET_FILTER_ALL_MC | fapi2::TARGET_FILTER_NEST_NORTH |
+                                   fapi2::TARGET_FILTER_NEST_SOUTH | fapi2::TARGET_FILTER_NEST_EAST |
+                                   fapi2::TARGET_FILTER_TP);
+    }
+    else
+    {
+        l_nest_filter = fapi2::TARGET_FILTER_ALL_NEST;
+        l_nest_tp_filter = static_cast<fapi2::TargetFilter>
+                           (fapi2::TARGET_FILTER_ALL_NEST | fapi2::TARGET_FILTER_TP);
+        l_dd1_filter_without_N3 = static_cast<fapi2::TargetFilter>
+                                  (fapi2::TARGET_FILTER_NEST_NORTH | fapi2::TARGET_FILTER_NEST_SOUTH |
+                                   fapi2::TARGET_FILTER_NEST_EAST | fapi2::TARGET_FILTER_TP);
+    }
+
+    for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_NEST_WEST, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Drop chiplet fence for N3");
+        FAPI_TRY(p9_sbe_nest_startclocks_N3_fence_drop(l_trgt_chplt, l_pg_vector));
+    }
+
+    for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_NEST_NORTH |
+                                           fapi2::TARGET_FILTER_NEST_SOUTH | fapi2::TARGET_FILTER_NEST_EAST),
+          fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Drop chiplet fence for N0,N1,N2");
+        FAPI_TRY(p9_sbe_nest_startclocks_nest_fence_drop(l_trgt_chplt, l_pg_vector));
+    }
+
+    if ( l_read_attr )
+    {
+        for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("Drop chiplet fence for MC");
+            FAPI_TRY(p9_sbe_nest_startclocks_mc_fence_drop(l_trgt_chplt, l_pg_vector));
+        }
+    }
+
+    for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (l_nest_filter, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_TRY(p9_sbe_nest_startclocks_get_attr_pg(l_trgt_chplt, l_attr_pg));
+
+        FAPI_DBG("Call common_cplt_ctrl_action_function for Nest and Mc chiplets");
+        FAPI_TRY(p9_sbe_common_cplt_ctrl_action_function(l_trgt_chplt, l_attr_pg));
+    }
+
+    for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (l_nest_tp_filter, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Call module align chiplets for Nest and Mc chiplets");
+        FAPI_TRY(p9_sbe_common_align_chiplets(l_trgt_chplt));
+    }
+
+    for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_NEST_NORTH |
+                                           fapi2::TARGET_FILTER_NEST_SOUTH | fapi2::TARGET_FILTER_NEST_EAST),
+          fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Regions value: %#018lX", l_clock_regions);
+        FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_trgt_chplt,
+                 REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_clock_regions));
+
+        FAPI_DBG("Call module clock start stop for N0, N1, N2");
+        FAPI_TRY(p9_sbe_common_clock_start_stop(l_trgt_chplt, CLOCK_CMD, STARTSLAVE,
+                                                DONT_STARTMASTER, l_clock_regions, CLOCK_TYPES));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_NEST_WEST, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_TRY(p9_sbe_common_clock_start_stop(l_target_cplt, CLOCK_CMD,
+                                                DONT_STARTSLAVE, STARTMASTER, l_n3_clock_regions, CLOCK_TYPES));
+        FAPI_DBG("pg targets vector: %#018lX", l_pg_vector);
+    }
+
+    for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_NEST_NORTH |
+                                           fapi2::TARGET_FILTER_NEST_SOUTH | fapi2::TARGET_FILTER_NEST_EAST),
+          fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(l_trgt_chplt,
+                 REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_ccstatus_regions));
+        FAPI_DBG("Regions value: %#018lX", l_ccstatus_regions);
+
+        FAPI_DBG("Call clockstatus check function for N0,N1,N2");
+        FAPI_TRY(p9_sbe_common_check_cc_status_function(l_trgt_chplt, CLOCK_CMD,
+                 l_ccstatus_regions, CLOCK_TYPES));
+    }
+
+    for (auto l_target_cplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_NEST_WEST, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Call clockstatus check function for N3");
+        FAPI_TRY(p9_sbe_common_check_cc_status_function(l_target_cplt, CLOCK_CMD,
+                 l_n3_ccstatus_regions, CLOCK_TYPES));
+        FAPI_DBG("pg targets vector: %#018lX", l_pg_vector);
+    }
+
+    if ( l_read_attr )
+    {
+        for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (fapi2::TARGET_FILTER_ALL_MC, fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_trgt_chplt,
+                     REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_clock_regions));
+            FAPI_DBG("Regions value: %#018lX", l_clock_regions);
+
+            FAPI_DBG("Call module clock start stop for MC01, MC23.");
+            FAPI_TRY(p9_sbe_common_clock_start_stop(l_trgt_chplt, CLOCK_CMD,
+                                                    DONT_STARTSLAVE, DONT_STARTMASTER, l_clock_regions, CLOCK_TYPES));
+        }
+    }
+
+    if ( l_read_flush_attr )
+    {
+        for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (l_dd1_filter_without_N3, fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("clear  flush_inhibit to go into flush mode");
+            FAPI_TRY(p9_sbe_common_flushmode(l_trgt_chplt));
+        }
+    }
+    else
+    {
+        for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+             (l_nest_tp_filter, fapi2::TARGET_STATE_FUNCTIONAL))
+        {
+            FAPI_DBG("clear  flush_inhibit to go into flush mode");
+            FAPI_TRY(p9_sbe_common_flushmode(l_trgt_chplt));
+        }
+    }
+
+    FAPI_INF("p9_sbe_nest_startclocks: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Drop chiplet fence for OB chiplet
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_pg_vector     Pg vector of targets
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_nest_startclocks_N3_fence_drop(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint64_t> i_pg_vector)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_nest_startclocks_N3_fence_drop: Entering ...");
+
+    if ( i_pg_vector.getBit<0>() == 1 )
+    {
+        FAPI_DBG("Drop chiplet fence");
+        //Setting NET_CTRL0 register value
+        l_data64.flush<1>();
+        l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>();  //NET_CTRL0.FENCE_EN = 0
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64));
+    }
+
+    FAPI_INF("p9_sbe_nest_startclocks_N3_fence_drop: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief get attr_pg for the chiplet
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[out]    o_attr_pg       ATTR_PG for the chiplet
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_nest_startclocks_get_attr_pg(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    fapi2::buffer<uint32_t>& o_attr_pg)
+{
+    FAPI_INF("p9_sbe_nest_startclocks_get_attr_pg: Entering ...");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, o_attr_pg));
+
+    FAPI_INF("p9_sbe_nest_startclocks_get_attr_pg: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Drop chiplet fence for MC
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_pg_vector     Pg vector of targets
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_nest_startclocks_mc_fence_drop(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint64_t> i_pg_vector)
+{
+    uint8_t l_read_attrunitpos = 0;
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_nest_startclocks_mc_fence_drop: Entering ...");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_chiplet,
+                           l_read_attrunitpos));
+
+    if ( l_read_attrunitpos == 0x07 )
+    {
+        if ( i_pg_vector.getBit<4>() == 1 )
+        {
+            FAPI_DBG("Drop chiplet fence");
+            //Setting NET_CTRL0 register value
+            l_data64.flush<1>();
+            l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>();  //NET_CTRL0.FENCE_EN = 0
+            FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64));
+        }
+    }
+
+    if ( l_read_attrunitpos == 0x08 )
+    {
+        if ( i_pg_vector.getBit<2>() == 1 )
+        {
+            FAPI_DBG("Drop chiplet fence");
+            //Setting NET_CTRL0 register value
+            l_data64.flush<1>();
+            l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>();  //NET_CTRL0.FENCE_EN = 0
+            FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64));
+        }
+    }
+
+    FAPI_INF("p9_sbe_nest_startclocks_mc_fence_drop: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Drop chiplet fence for pcie chiplet
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_pg_vector     Pg vector of targets
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_nest_startclocks_nest_fence_drop(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint64_t> i_pg_vector)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_nest_startclocks_nest_fence_drop: Entering ...");
+
+    if ( i_pg_vector.getBit<4>() == 1 )
+    {
+        FAPI_DBG("Drop chiplet fence");
+        //Setting NET_CTRL0 register value
+        l_data64.flush<1>();
+        l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>();  //NET_CTRL0.FENCE_EN = 0
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64));
+    }
+
+    FAPI_INF("p9_sbe_nest_startclocks_nest_fence_drop: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.H
new file mode 100644
index 00000000..efc40a97
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.H
@@ -0,0 +1,66 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_nest_startclocks.H
+///
+/// @brief start PB and Nest clocks
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_NEST_STARTCLOCKS_H_
+#define _P9_SBE_NEST_STARTCLOCKS_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_nest_startclocks_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief --drop vital fence
+/// --reset abstclk muxsel and syncclk muxsel
+/// --Module align chiplets
+/// --Module clock start stop
+/// --Check clock stat SL, NSL , ARY
+/// --drop chiplet fence
+/// --check checkstop register
+/// --clear flush inhibit to go into flush mode
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_nest_startclocks(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C
new file mode 100644
index 00000000..79e0c0e3
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C
@@ -0,0 +1,91 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.C $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_npll_initf.C
+///
+/// @brief apply initfile for level 0 & 1 PLLs
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_npll_initf.H"
+
+fapi2::ReturnCode p9_sbe_npll_initf(const
+                                    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    FAPI_INF("p9_sbe_npll_initf: Entering ...");
+
+    uint8_t l_read_attr = 0;
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+    RingID ringID = perv_pll_bndy_bucket_1;
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM , l_read_attr),
+             "Error from FAPI_ATTR_GET (ATTR_NEST_PLL_BUCKET)");
+
+    switch(l_read_attr)
+    {
+        case 1:
+            ringID = perv_pll_bndy_bucket_1;
+            break;
+
+        case 2:
+            ringID = perv_pll_bndy_bucket_2;
+            break;
+
+        case 3:
+            ringID = perv_pll_bndy_bucket_3;
+            break;
+
+        case 4:
+            ringID = perv_pll_bndy_bucket_4;
+            break;
+
+        case 5:
+            ringID = perv_pll_bndy_bucket_5;
+            break;
+
+        default:
+            FAPI_ASSERT(false,
+                        fapi2::P9_SBE_NPLL_INITF_UNSUPPORTED_BUCKET().
+                        set_TARGET(i_target_chip).
+                        set_BUCKET_INDEX(l_read_attr),
+                        "Unsupported Nest PLL bucket value!");
+    }
+
+    FAPI_DBG("Scan perv_pll_bndy_bucket_%d ring", l_read_attr);
+    FAPI_TRY(fapi2::putRing(i_target_chip, ringID, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (perv_pll_bndy, ringID: %d)", ringID);
+
+fapi_try_exit:
+    FAPI_INF("p9_sbe_npll_initf: Exiting ...");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.H
new file mode 100644
index 00000000..025d2377
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.H
@@ -0,0 +1,62 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_npll_initf.H $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_npll_initf.H
+///
+/// @brief apply initfile for level 0 & 1 PLLs
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_NPLL_INITF_H_
+#define _P9_SBE_NPLL_INITF_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_npll_initf_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief --run scan0 module  (scan region = PLL, scan_types = GPTR)
+/// --run scan0 module  (scan region = PLL, scan_types = BNDY/FUNC)
+/// --Scan initialize PLL BNDY chain (chiplet = PERV, scan ring = PLL, scan type = BNDY)
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_npll_initf(const
+                                        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C
new file mode 100644
index 00000000..331fa528
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C
@@ -0,0 +1,242 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_npll_setup.C
+///
+/// @brief scan initialize level 0 & 1 PLLs
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_npll_setup.H"
+//## auto_generated
+#include "p9_const_common.H"
+
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
+
+
+enum P9_SBE_NPLL_SETUP_Private_Constants
+{
+    NS_DELAY = 5000000, // unit is nano seconds
+    SIM_CYCLE_DELAY = 1000 // unit is sim cycles
+};
+
+fapi2::ReturnCode p9_sbe_npll_setup(const
+                                    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_read_reg;
+    uint8_t l_read_attr = 0;
+    fapi2::buffer<uint64_t> l_data64_root_ctrl8;
+    fapi2::buffer<uint64_t> l_data64_perv_ctrl0;
+    FAPI_INF("p9_sbe_npll_setup: Entering ...");
+
+    FAPI_DBG("Reading ROOT_CTRL8 register value");
+    //Getting ROOT_CTRL8 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                            l_data64_root_ctrl8)); //l_data64_root_ctrl8 = PIB.ROOT_CTRL8
+
+
+    FAPI_DBG("Reading ATTR_SS_FILTER_BYPASS");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SS_FILTER_BYPASS, i_target_chip,
+                           l_read_attr));
+
+    if ( l_read_attr == 0x0 )
+    {
+        FAPI_DBG("Drop PLL test enable for Spread Spectrum PLL");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_SS0_PLL_TEST_EN = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_TEST_EN>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+
+        FAPI_DBG("Release SS PLL reset");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_SS0_PLL_RESET = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_RESET>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+
+        fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
+
+        FAPI_DBG("check SS PLL lock");
+        //Getting PLL_LOCK_REG register value
+        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG,
+                                l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG
+
+        FAPI_ASSERT(l_read_reg.getBit<0>(),
+                    fapi2::SS_PLL_LOCK_ERR()
+                    .set_SS_PLL_READ(l_read_reg),
+                    "ERROR:SS PLL LOCK NOT SET");
+
+        FAPI_DBG("Release SS PLL Bypass");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_SS0_PLL_BYPASS = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_BYPASS>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+    }
+
+    FAPI_DBG("Reading ATTR_CP_FILTER_BYPASS");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CP_FILTER_BYPASS, i_target_chip,
+                           l_read_attr));
+
+    if ( l_read_attr == 0x0 )
+    {
+        FAPI_DBG("Drop PLL test enable for CP Filter PLL");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_FILT1_PLL_TEST_EN = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_TEST_EN>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+
+        FAPI_DBG("Release CP Filter PLL reset");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_FILT1_PLL_RESET = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_RESET>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+
+        fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
+
+        FAPI_DBG("check  PLL lock for CP Filter PLL , Check PLL lock fir IO Filter PLL");
+        //Getting PLL_LOCK_REG register value
+        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG,
+                                l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG
+
+        FAPI_ASSERT(l_read_reg.getBit<1>(),
+                    fapi2::CP_FILTER_PLL_LOCK_ERR()
+                    .set_CP_FILTER_PLL_READ(l_read_reg),
+                    "ERROR:CP FILTER PLL LOCK NOT SET");
+
+        FAPI_DBG("Release CP filter PLL Bypass Signal");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_FILT1_PLL_BYPASS = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_BYPASS>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+    }
+
+    FAPI_DBG("Reading ATTR_IO_FILTER_BYPASS");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_FILTER_BYPASS, i_target_chip,
+                           l_read_attr));
+
+    if ( l_read_attr == 0x0 )
+    {
+        FAPI_DBG("Drop PLL test enable for IO Filter PLL");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_FILT0_PLL_TEST_EN = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_TEST_EN>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+
+        FAPI_DBG("Release IO Filter PLL reset");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_FILT0_PLL_RESET = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_RESET>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+
+        fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
+
+        FAPI_DBG("check  PLL lock for CP Filter PLL , Check PLL lock fir IO Filter PLL");
+        //Getting PLL_LOCK_REG register value
+        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG,
+                                l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG
+
+        FAPI_ASSERT(l_read_reg.getBit<2>(),
+                    fapi2::IO_FILTER_PLL_LOCK_ERR()
+                    .set_IO_FILTER_PLL_READ(l_read_reg),
+                    "ERROR:IO FILTER PLL LOCK NOT SET");
+
+        FAPI_DBG("Release IO filter PLL Bypass Signal");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_FILT0_PLL_BYPASS = 0
+        l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_BYPASS>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+    }
+
+    FAPI_DBG("Drop PLL test enable for Nest PLL");
+    //Setting PERV_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
+                            l_data64_perv_ctrl0));
+    //PIB.PERV_CTRL0.TP_PLL_TEST_EN_DC = 0
+    l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLL_TEST_EN_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
+                            l_data64_perv_ctrl0));
+
+    FAPI_DBG("Reading ATTR_MC_SYNC_MODE");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr));
+
+    if ( l_read_attr == 1 )
+    {
+        FAPI_DBG("Set MUX to Nest Clock input");
+        //Setting ROOT_CTRL8 register value
+        //PIB.ROOT_CTRL8.TP_PLL_CLKIN_SEL4_DC = 1
+        l_data64_root_ctrl8.setBit<PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL4_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
+                                l_data64_root_ctrl8));
+    }
+
+    FAPI_DBG("Release Nest PLL  reset");
+    //Setting PERV_CTRL0 register value
+    //PIB.PERV_CTRL0.TP_PLLRST_DC = 0
+    l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLLRST_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
+                            l_data64_perv_ctrl0));
+
+    fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
+
+    FAPI_DBG("check  NEST PLL lock");
+    //Getting PLL_LOCK_REG register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG,
+                            l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG
+
+    FAPI_ASSERT(l_read_reg.getBit<3>(),
+                fapi2::NEST_PLL_ERR()
+                .set_NEST_PLL_READ(l_read_reg),
+                "ERROR:NEST PLL LOCK NOT SET");
+
+    FAPI_DBG("Release PLL bypass2");
+    //Setting PERV_CTRL0 register value
+    //PIB.PERV_CTRL0.TP_PLLBYP_DC = 0
+    l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLLBYP_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
+                            l_data64_perv_ctrl0));
+
+    FAPI_INF("p9_sbe_npll_setup: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.H
new file mode 100644
index 00000000..b05c7db1
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.H
@@ -0,0 +1,71 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.H $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_npll_setup.H
+///
+/// @brief scan initialize level 0 & 1 PLLs
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_NPLL_SETUP_H_
+#define _P9_SBE_NPLL_SETUP_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_npll_setup_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief --Release PLL test enable for SS,  Filt & NEST PLLs
+/// --Release SS PLL reset0
+/// --check SS PLL lock
+/// --Release SS PLL bypass0
+/// --Release Filter PLL reset1
+/// --check PLL lock for Filter PLLs
+/// --Release Filter PLL bypass signals
+/// --Switch MC meshs to Nest mesh
+/// --Release test_pll_bypass2
+/// --Release Tank PLL reset2
+/// --check Nest PLL lock
+/// --Release Tank PLL bypass2
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_npll_setup(const
+                                        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.C
new file mode 100644
index 00000000..9dc91da6
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.C
@@ -0,0 +1,177 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.C $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_repr_initf.C
+///
+/// @brief Load Repair rings for all enabled chiplets
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+#include "p9_sbe_repr_initf.H"
+#include "p9_perv_scom_addresses.H"
+
+
+fapi2::ReturnCode p9_sbe_repr_initf(const
+                                    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    uint8_t l_attr_chip_unit_pos = 0;
+    FAPI_INF("p9_sbe_repr_initf: Entering ...");
+
+    for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST>(fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_repr));
+    }
+
+    for (auto l_chplt_trgt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_chplt_trgt, l_attr_chip_unit_pos));
+
+        if (l_attr_chip_unit_pos == 0x9)/* OBUS0 Chiplet */
+        {
+            FAPI_DBG("Scan ob0_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob0_repr),
+                     "Error from putRing (ob0_repr)");
+        }
+
+        if (l_attr_chip_unit_pos == 0xA)/* OBUS1 Chiplet */
+        {
+            FAPI_DBG("Scan ob1_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob1_repr),
+                     "Error from putRing (ob1_repr)");
+        }
+
+        if (l_attr_chip_unit_pos == 0xB)/* OBUS2 Chiplet */
+        {
+            FAPI_DBG("Scan ob2_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob2_repr),
+                     "Error from putRing (ob2_repr)");
+        }
+
+        if (l_attr_chip_unit_pos == 0xC)/* OBUS3 Chiplet */
+        {
+            FAPI_DBG("Scan ob3_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, ob3_repr),
+                     "Error from putRing (ob3_repr)");
+        }
+
+        if (l_attr_chip_unit_pos == 0x6)/* XBUS Chiplet */
+        {
+            FAPI_DBG("Scan xb_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, xb_repr),
+                     "Error from putRing (xb_repr)");
+            FAPI_DBG("Scan xb_io1_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, xb_io1_repr),
+                     "Error from putRing (xb_io1_repr)");
+            FAPI_DBG("Scan xb_io2_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, xb_io2_repr),
+                     "Error from putRing (xb_io2_repr)");
+        }
+
+        if (l_attr_chip_unit_pos == 0xD)/* PCI0 Chiplet */
+        {
+            FAPI_DBG("Scan pci0_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, pci0_repr),
+                     "Error from putRing (pci0_repr)");
+        }
+
+        if (l_attr_chip_unit_pos == 0xE)/* PCI1 Chiplet */
+        {
+            FAPI_DBG("Scan pci1_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, pci1_repr),
+                     "Error from putRing (pci1_repr)");
+        }
+
+        if (l_attr_chip_unit_pos == 0xF)/* PCI2 Chiplet */
+        {
+            FAPI_DBG("Scan pci2_repr_ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, pci2_repr),
+                     "Error from putRing (pci2_repr)");
+        }
+
+        if (l_attr_chip_unit_pos == 0x2)/* N0 Chiplet */
+        {
+            FAPI_DBG("Scan n0_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n0_repr),
+                     "Error from putRing (n0_repr)");
+            FAPI_DBG("Scan n0_nx_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n0_nx_repr),
+                     "Error from putRing (n0_nx_repr)");
+            FAPI_DBG("Scan n0_cxa0_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n0_cxa0_repr),
+                     "Error from putRing (n0_cxa0_repr)");
+        }
+
+        if (l_attr_chip_unit_pos == 0x3)/* N1 Chiplet */
+        {
+            FAPI_DBG("Scan n1_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_repr),
+                     "Error from putRing (n1_repr)");
+            FAPI_DBG("Scan n1_ioo0_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo0_repr),
+                     "Error from putRing (n1_ioo0_repr)");
+            FAPI_DBG("Scan n1_ioo1_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_ioo1_repr),
+                     "Error from putRing (n1_ioo1_repr)");
+            FAPI_DBG("Scan n1_mcs23_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n1_mcs23_repr),
+                     "Error from putRing (n1_mcs23_repr)");
+        }
+
+        if (l_attr_chip_unit_pos == 0x4)/* N2 Chiplet */
+        {
+            FAPI_DBG("Scan n2_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n2_repr),
+                     "Error from putRing (n2_repr)");
+            FAPI_DBG("Scan n2_cxa1_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n2_cxa1_repr),
+                     "Error from putRing (n2_cxa1_repr)");
+        }
+
+        if (l_attr_chip_unit_pos == 0x5)/* N3 Chiplet */
+        {
+            FAPI_DBG("Scan n3_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n3_repr),
+                     "Error from putRing (n3_repr)");
+            FAPI_DBG("Scan n3_mcs01_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n3_mcs01_repr),
+                     "Error from putRing (n3_mcs01_repr)");
+            FAPI_DBG("Scan n3_np_repr ring");
+            FAPI_TRY(fapi2::putRing(i_target_chip, n3_np_repr),
+                     "Error from putRing (n3_np_repr)");
+        }
+    }
+
+fapi_try_exit:
+    FAPI_INF("p9_sbe_repr_initf: Exiting ...");
+    return fapi2::current_err;
+
+}
+
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H
new file mode 100644
index 00000000..b5dbbe99
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H
@@ -0,0 +1,60 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_repr_initf.H $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_repr_initf.C
+///
+/// @brief Initialize REPR for PERV chiplet
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+#ifndef _P9_SBE_REPR_INITF_H_
+#define _P9_SBE_REPR_INITF_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_repr_initf_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief --Scan Repair for all Perv Chiplets except TP, EC, EP
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_repr_initf(const
+                                        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C
new file mode 100644
index 00000000..af7c2299
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C
@@ -0,0 +1,494 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_sbe_select_ex.C
+/// @brief Select the Hostboot core from the available cores on the chip
+///
+// *HWP HWP Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team: PM
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+///
+///
+///
+/// High-level procedure flow:
+/// @verbatim
+///   Following MC groups are needed to be setup for istep 4 use:
+///     - MC group 3:  Core(s) (eg ECs);  use EC MC group register 3
+///     - MC group 4:  EQ(s);             use EQ MC group register 2
+///     - MC group 5:  Even EXs;          use EQ MC group register 3
+///     - MC group 6:  Odd Exs;           use EQ MC group register 4
+///
+///   Prerequisite:  istep 2 will setup the above groups with ALL the good
+///                  elements represented.
+///
+///   This procedure will REMOVE entities from these groups in SINGLE mode;
+///   in ALL mode, the groups are not changed.  In either case, the OCC
+///   registers are written with the valid configuration.  Additionally,
+///   default PFET controller delays are written into all configured
+///   EC and EQ chiplets so that istep 4 power-on operations will
+///   succeed.
+///
+///   Parameter indicates single core or all (controlled by Cronus/SBE)
+///
+///     loop over functional cores {
+///         if mode == SINGLE {
+///             if first one {
+///                 Record the master core, EX and EQ number
+///             }
+///             else {
+///                 Remove from MC Group 3
+///             }
+///         }
+///         Set bits in core and EX scoreboard for later updating the OCC
+///         Set default PFET controller delay values into Core
+///       }
+///
+///     loop over functional EQs {
+///         if mode == SINGLE {
+///             if not master EQ {
+///                 Remove from MC Groups 4
+///             for the EXs in the EQ {
+///                 if not master EX && bit is set in EX scoreboard
+///                     Remove from MC Group 5 if Even (EX0)
+///                     Remove from MC Group 6 if Odd (EX1)
+///         }
+///         Set default PFET controller delay values into EQ
+///     }
+///
+///   Write resultant scoreboard EQ/Core mask into OCC complex
+///     - This is the "master record " of the enabled cores/quad in the system
+///         - This is only for during the IPL (will be updated later in step 15)
+/// @endverbatim
+
+// -----------------------------------------------------------------------------
+//  Includes
+// -----------------------------------------------------------------------------
+#include "p9_sbe_select_ex.H"
+#include "p9_common_poweronoff.H"
+
+// -----------------------------------------------------------------------------
+//  Definitions
+// -----------------------------------------------------------------------------
+
+static const uint32_t NUM_EX_PER_EQ = 2;
+
+static const uint8_t CORE_CHIPLET_START     = 0x20;
+static const uint8_t CORE_CHIPLET_COUNT     = 24;
+
+static const uint8_t CORE_STOP_MC_GROUP     = 3;
+static const uint8_t EQ_STOP_MC_GROUP       = 4;
+static const uint8_t EX_EVEN_STOP_MC_GROUP  = 5;
+static const uint8_t EX_ODD_STOP_MC_GROUP   = 6;
+static const uint8_t BROADCAST_GROUP        = 7;
+
+// Use PERV addressses as the accesses to the cores and EQ use PERV targets
+static const uint64_t CORE_MC_REG           = PERV_MULTICAST_GROUP_3;
+static const uint64_t EQ_MC_REG             = PERV_MULTICAST_GROUP_2;
+static const uint64_t EX_EVEN_MC_REG        = PERV_MULTICAST_GROUP_3;
+static const uint64_t EX_ODD_MC_REG         = PERV_MULTICAST_GROUP_4;
+
+// Note: in the above, the EX MC groups really live in the EQ chiplet, not the
+// core!
+
+static const uint8_t PERV_EQ_START      = 0x10;
+static const uint8_t PERV_EQ_COUNT      = 6;
+static const uint8_t PERV_CORE_START    = 0x20;
+static const uint8_t PERV_CORE_COUNT    = 24;
+
+// -----------------------------------------------------------------------------
+//  Function prototypes
+// -----------------------------------------------------------------------------
+
+fapi2::ReturnCode select_ex_remove_core_from_mc_group(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt);
+
+fapi2::ReturnCode select_ex_remove_ex_from_mc_group(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt,
+    const uint32_t i_ex_num);
+
+fapi2::ReturnCode select_ex_remove_eq_from_mc_group(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt);
+
+// -----------------------------------------------------------------------------
+//  Function definitions
+// -----------------------------------------------------------------------------
+
+// See .H for documentation
+fapi2::ReturnCode p9_sbe_select_ex(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const p9selectex::MODE i_mode)
+{
+    FAPI_IMP("> p9_sbe_select_ex");
+
+    fapi2::buffer<uint64_t> l_core_config = 0;
+    fapi2::buffer<uint64_t> l_quad_config = 0;
+    fapi2::buffer<uint64_t> l_data64 = 0;
+    uint8_t attr_force_all = 0;
+    bool b_single = true;
+    bool b_host_core_found = false;
+    bool b_processing_host_core = false;
+
+    uint32_t l_master_ex_num = 0xFF;  // invalid EX number initialized
+    uint32_t l_master_eq_num = 0xFF;  // invalid EQ number initialized
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+
+    auto l_core_functional_vector = i_target.getChildren<fapi2::TARGET_TYPE_PERV>
+                                    (fapi2::TARGET_FILTER_ALL_CORES,
+                                     fapi2::TARGET_STATE_FUNCTIONAL );
+
+    auto l_eq_functional_vector = i_target.getChildren<fapi2::TARGET_TYPE_PERV>
+                                  (fapi2::TARGET_FILTER_ALL_CACHES,
+                                   fapi2::TARGET_STATE_FUNCTIONAL );
+
+    // Read the "FORCE_ALL" attribute
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES,
+                           FAPI_SYSTEM,
+                           attr_force_all));
+
+    // Set the flow mode and respect the force mode
+    if (attr_force_all || i_mode == p9selectex::ALL)
+    {
+        b_single = false;
+        FAPI_DBG("All cores mode");
+    }
+    else
+    {
+        FAPI_DBG("Single core mode:  Number of candidate cores = %d, Number of candidate caches = %d",
+                 l_core_functional_vector.size(),
+                 l_eq_functional_vector.size());
+    }
+
+    // Loop through the core functional vector.  The first core in the vector
+    // is going to be the hostboot core as the FAPI platform code is expected
+    // to return the vector elements in acsending order; thus, the first vector
+    // entry is the lowest numbered, valid core.
+    //
+    // Two buffers track the core and EX configuration as though "ALL" is the
+    // mode chosen.  This is done to reduce conditional processing within the
+    // vector loop to allow for better prefetch utilization.
+
+    for (auto core : l_core_functional_vector)
+    {
+        uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,
+                               core,
+                               l_attr_chip_unit_pos));
+
+        // Needed as core is a PERV target
+        uint32_t l_core_num = static_cast<uint32_t>(l_attr_chip_unit_pos - PERV_CORE_START);
+
+        FAPI_DBG("Functional core l_attr_chip_unit_pos 0x%02X, l_core_num =  0x%02X",
+                 l_attr_chip_unit_pos, l_core_num);
+
+        uint32_t l_ex_num = l_core_num / 2;
+        uint32_t l_eq_num = l_core_num / 4;
+
+        if (b_single)
+        {
+            b_processing_host_core = false;
+
+            if (!b_host_core_found)
+            {
+
+                l_master_ex_num = l_ex_num;
+                l_master_eq_num = l_eq_num;
+
+                uint8_t l_short_core_num = static_cast<uint8_t>(l_core_num);
+                FAPI_TRY(FAPI_ATTR_SET( fapi2::ATTR_MASTER_CORE,
+                                        i_target,
+                                        l_short_core_num));
+
+                uint8_t l_short_ex_num = static_cast<uint8_t>(l_ex_num);
+                FAPI_TRY(FAPI_ATTR_SET( fapi2::ATTR_MASTER_EX,
+                                        i_target,
+                                        l_short_ex_num));
+
+                FAPI_DBG("MASTER core chiplet %d 0x%02X; EX %d 0x%02X",
+                         l_core_num, l_core_num,
+                         l_master_ex_num, l_master_ex_num);
+
+                b_host_core_found = true;
+                b_processing_host_core = true;
+
+            } // host_core_found
+
+            // Remove the core from the apppropriate multicast group if not
+            // the host core
+            if (!b_processing_host_core)
+            {
+                FAPI_TRY(select_ex_remove_core_from_mc_group(core));
+            }
+
+        } // Single
+
+        // To save code space in the SBE, the assumption is made that if the core
+        // is good (eg in the core functional vector), then the EX associated with
+        // it is also good.  No checking is performed on the associated the EX
+        // targets to check this.
+        //
+        // Thus, set the bits in the buffers for the OCC configuration register
+        // update
+        FAPI_DBG("core num = %d, ex num = %d",
+                 l_core_num, l_ex_num);
+        l_core_config.setBit(l_core_num);
+        l_quad_config.setBit(l_ex_num);
+
+        FAPI_DBG("Scoreboard values for OCC: Core 0x%016llX  EX 0x%016llX",
+                 l_core_config, l_quad_config);
+
+        // Write the default PFET Controller Delay values for the Core
+        // as it will be used for istep 4
+        FAPI_DBG("Setting PFET Delays in core %d", l_core_num);
+
+        l_data64.flush<0>()
+        .insertFromRight<0, 4>(p9power::PFET_DELAY_POWERDOWN_CORE)
+        .insertFromRight<4, 4>(p9power::PFET_DELAY_POWERUP_CORE);
+
+        FAPI_TRY(fapi2::putScom(core,
+                                C_PPM_PFDLY - 0x20000000,  // Create chip address base
+                                l_data64),
+                 "Error: Core PFET Delay register");
+
+    } // Core loop
+
+    // Process the good EQs
+    for (auto eq : l_eq_functional_vector)
+    {
+        uint8_t l_attr_chip_unit_pos = 0; //actual value is read in FAPI_ATTR_GET below
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,
+                               eq,
+                               l_attr_chip_unit_pos));
+
+        // Needed as eq is a PERV target
+        uint32_t l_eq_num = static_cast<uint32_t>(l_attr_chip_unit_pos - PERV_EQ_START);
+
+        FAPI_DBG("Functional EQ l_attr_chip_unit_pos 0x%02X, l_eq_num =  0x%02X",
+                 l_attr_chip_unit_pos, l_eq_num);
+
+        if (b_single)
+        {
+            if (l_eq_num != l_master_eq_num)
+            {
+                FAPI_TRY(select_ex_remove_eq_from_mc_group(eq));
+            }
+
+            for (auto i = l_eq_num * NUM_EX_PER_EQ; i < (l_eq_num + 1)*NUM_EX_PER_EQ; ++i)
+            {
+                FAPI_DBG("ex = %d, master ex = %d, quad bit[%d] = %d",
+                         i, l_master_ex_num, i, l_quad_config.getBit(i));
+
+                // Remove from MC group if not master EX and configured
+                if ((i != l_master_ex_num) && l_quad_config.getBit(i))
+                {
+                    FAPI_TRY(select_ex_remove_ex_from_mc_group(eq, i));
+                }
+            }
+
+        } // Single
+
+        FAPI_DBG("Setting PFET Delays in EQ %d", l_eq_num);
+
+        // Write the default PFET Controller Delay values for the EQs
+        // that will be used for istep 4
+        l_data64.flush<0>()
+        .insertFromRight<0, 4>(p9power::PFET_DELAY_POWERDOWN_EQ)
+        .insertFromRight<4, 4>(p9power::PFET_DELAY_POWERUP_EQ);
+
+        FAPI_TRY(fapi2::putScom(eq,
+                                EQ_PPM_PFDLY - 0x10000000,  // Create chip address base
+                                l_data64),
+                 "Error: EQ PFET Delay register, rc 0x%.8X",
+                 (uint32_t)fapi2::current_err);
+
+
+    } // EQ loop
+
+
+    // Write to the OCC Core Configuration Status Register
+    FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_CCSR_SCOM2, l_core_config));
+
+    // Write to the OCC Quad Configuration Status Register
+    FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_QCSR_SCOM2, l_quad_config));
+
+    // Write default value the OCC Quad Status Status Register
+    l_data64.flush<0>()
+    .setBit<0, 12>()       // L2 Stopped
+    .setBit<14, 6>();      // Quad Stopped
+    FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_QSSR_SCOM2, l_data64));
+
+fapi_try_exit:
+    FAPI_INF("< p9_sbe_select_ex");
+
+    return fapi2::current_err;
+} // END p9_sbe_select_ex
+
+///-----------------------------------------------------------------------------
+/// @brief Remve core chiplet from Dynamic cores multicast group
+///
+/// @param[in]     i_target_cplt   Reference to TARGET_TYPE_PERV target
+///                                     that is a core
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode select_ex_remove_core_from_mc_group(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt)
+{
+    FAPI_INF("> remove_from_core_mc_group...");
+
+    fapi2::buffer<uint64_t> l_data64 = 0;
+
+    // Entering group
+    l_data64.insertFromRight<0, 3>(0x7);
+    l_data64.insertFromRight<3, 3>(BROADCAST_GROUP);
+    // Removed group
+    l_data64.insertFromRight<19, 3>(CORE_STOP_MC_GROUP);
+
+#ifndef __PPE__
+    uint8_t l_attr_chip_unit_pos = 0;
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,
+                           i_target_cplt,
+                           l_attr_chip_unit_pos));
+
+    FAPI_DBG("Removing Core %d from MC group %d",
+             l_attr_chip_unit_pos - PERV_CORE_START,
+             CORE_STOP_MC_GROUP );
+#endif
+
+    FAPI_TRY(fapi2::putScom(i_target_cplt,
+                            CORE_MC_REG,
+                            l_data64),
+             "Error: Core MC group register, rc 0x%.8X",
+             (uint32_t)fapi2::current_err);
+
+fapi_try_exit:
+    FAPI_INF("< remove_from_core_mc_group...");
+    return fapi2::current_err;
+
+}
+
+///-----------------------------------------------------------------------------
+/// @brief Remove EX from multicast group
+///
+/// @param[in]     i_ex_num  EX number that needs to be removed from an MC group
+///
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode select_ex_remove_ex_from_mc_group(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt,
+    const uint32_t i_ex_num)
+{
+    FAPI_INF("> select_ex_remove_ex_from_mc_group...");
+
+    // If the Core is in a even EX, then put the EQ chiplet in the EQ MC group
+    // and the EX Even MC group.
+
+    // If the Core is in a odd EX, then put the EQ chiplet in the EQ MC group
+    // and the EX Odd MC group.
+
+    fapi2::buffer<uint64_t> l_data64 = 0;
+
+    // Entering group
+    l_data64.insertFromRight<0, 3>(0x7);
+    l_data64.insertFromRight<3, 3>(BROADCAST_GROUP);
+
+    if (i_ex_num % 2)   // Odd EX
+    {
+        FAPI_DBG("Removing EX %d (Odd) from MC group %d",
+                 i_ex_num,
+                 EX_ODD_STOP_MC_GROUP);
+
+        // Removed group
+        l_data64.insertFromRight<19, 3>(EX_ODD_STOP_MC_GROUP);
+
+        FAPI_TRY(fapi2::putScom(i_target_cplt,
+                                EX_ODD_MC_REG,
+                                l_data64),
+                 "Error: EX Odd MC group register, rc 0x%.8X",
+                 (uint32_t)fapi2::current_err);
+
+    }
+    else                // Even EX
+    {
+        FAPI_DBG("Removing EX %d (Even) from MC group %d",
+                 i_ex_num,
+                 EX_EVEN_STOP_MC_GROUP);
+
+
+        // Removed group
+        l_data64.insertFromRight<19, 3>(EX_EVEN_STOP_MC_GROUP);
+
+        FAPI_TRY(fapi2::putScom(i_target_cplt,
+                                EX_EVEN_MC_REG,
+                                l_data64),
+                 "Error: EX Even MC group register, rc 0x%.16X",
+                 (uint32_t)fapi2::current_err);
+    }
+
+fapi_try_exit:
+    FAPI_INF("< select_ex_remove_ex_from_mc_group...");
+    return fapi2::current_err;
+
+}
+
+///-----------------------------------------------------------------------------
+/// @brief Remove EX from multicast group
+///
+/// @param[in]     i_ex_num  EX number for which the EQ needs to be in MC group
+///
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode select_ex_remove_eq_from_mc_group(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_cplt)
+{
+    FAPI_INF("> select_ex_remove_eq_from_mc_group...");
+
+    fapi2::buffer<uint64_t> l_data64;
+
+    // Entering group
+    l_data64.insertFromRight<0, 3>(0x7);
+    l_data64.insertFromRight<3, 3>(BROADCAST_GROUP);
+    // Removed group
+    l_data64.insertFromRight<19, 3>(EQ_STOP_MC_GROUP);
+
+#ifndef __PPE__
+    uint8_t l_attr_chip_unit_pos = 0;
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,
+                           i_target_cplt,
+                           l_attr_chip_unit_pos));
+
+    FAPI_DBG("Removing EQ %d from MC group %d",
+             l_attr_chip_unit_pos - PERV_EQ_START,
+             EQ_STOP_MC_GROUP );
+#endif
+
+    FAPI_TRY(fapi2::putScom(i_target_cplt,
+                            EQ_MC_REG,
+                            l_data64),
+             "Error: EQ MC group register, rc 0x%.8X",
+             (uint32_t)fapi2::current_err);
+
+fapi_try_exit:
+    FAPI_INF("< select_ex_remove_eq_from_mc_group...");
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H
new file mode 100644
index 00000000..3c40e9aa
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H
@@ -0,0 +1,85 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_sbe_select_ex.H
+/// @brief Select the Hostboot core from the available cores on the chip
+///
+// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com>
+// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team: PM
+// *HWP Level: 2
+// *HWP Consumed by: SBE
+///
+
+#ifndef _P9_SBE_SELECT_EX_H_
+#define _P9_SBE_SELECT_EX_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <fapi2.H>
+#include <p9_misc_scom_addresses.H>
+#include <p9_quad_scom_addresses.H>
+#include <p9_perv_scom_addresses.H>
+
+
+namespace p9selectex
+{
+// valid domain options
+enum  MODE
+{
+    SINGLE,       // Only the first core
+    ALL           // All Core
+};
+
+} // namespace p9selectex
+
+
+// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_sbe_select_ex_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
+    p9selectex::MODE);
+
+extern "C" {
+
+// -----------------------------------------------------------------------------
+//  Function prototype
+// -----------------------------------------------------------------------------
+
+/// @brief Select the Hostboot core from the available cores on the chip
+///
+/// @param [in] i_target    Chip target
+/// @param [in] i_mode      SINGLE core (enable only the first core found);
+///                         ALL cores (enable all configured cores found)
+///
+    fapi2::ReturnCode p9_sbe_select_ex(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        p9selectex::MODE i_mode);
+
+} // extern "C"
+
+#endif // _P9_SBE_SELECT_EX_H_
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.C
new file mode 100644
index 00000000..420680f7
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.C
@@ -0,0 +1,151 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file  p9_sbe_setup_boot_freq.C
+/// @brief Setup Boot Frequency
+///
+// *HW Owner    : Sudheendra K Srivathsa <sudheendraks@in.ibm.com>
+// *FW Owner    : Sangeetha T S <sangeet2@in.ibm.com>
+// *Team        : PM
+// *Consumed by : SBE
+// *Level       : 2
+///
+/// @verbatim
+///
+/// Procedure Summary:
+///   - Read frequency ATTR and write to the Quad PPM DPLL Freq Ctrl register
+///
+/// @endverbatim
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+#include <fapi2.H>
+#include "p9_sbe_setup_boot_freq.H"
+#include "p9_quad_scom_addresses.H"
+
+enum P9_SBE_SETUP_BOOT_FREQ_CONSTANTS
+{
+
+// Default configuration settings
+
+// Default boot_frequency in terms of a multiplier of the refclk frequency/8
+// This is value used if the mailbox value is zero
+//
+// Value implemented is 3.0GHz, @todo, RTC 140053 - Should it be 2 GHz for P9 ?
+//
+// 3000MHz / 16.667MHz = ~180 => 0xB4
+//
+// Note:  the above is aligned, as a value, to 0:10, written as bits 17:27 of PPM DPLL freq ctrl register
+// Bits 0:7 are DPLL.MULT_INTG(0:7), and Bits 8:10 are DPLL.MULT_FRAC(0:2)
+//
+    DEFAULT_BOOT_FREQUENCY_MULTIPLIER =  0x00B4,
+
+};
+
+//-----------------------------------------------------------------------------
+// Procedure
+//-----------------------------------------------------------------------------
+
+fapi2::ReturnCode
+BootFreqInitAttributes(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+                       uint16_t& i_boot_frequency_multiplier)
+{
+
+    i_boot_frequency_multiplier = DEFAULT_BOOT_FREQUENCY_MULTIPLIER;
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BOOT_FREQ_MULT, i_target, i_boot_frequency_multiplier));
+
+    // If attribute values are zero, use the default values (hardcoded)
+
+    // check BOOT FREQ MULT
+    if (i_boot_frequency_multiplier == 0)
+    {
+        // Default voltage if mailbox value is not set
+
+        // @todo, L3 phase Eventually, this should replaced with an error point
+        // to indicate that the mailbox -> attributes haven't been setup
+
+        i_boot_frequency_multiplier  = DEFAULT_BOOT_FREQUENCY_MULTIPLIER;
+        FAPI_INF("DPLL boot frequency not set in attributes.  Setting to default of %d (%x)",
+                 i_boot_frequency_multiplier, i_boot_frequency_multiplier);
+    }
+    else
+    {
+        FAPI_INF("DPLL boot frequency = %d (%x)",
+                 i_boot_frequency_multiplier, i_boot_frequency_multiplier);
+    }
+
+fapi_try_exit:
+    return fapi2::current_err;
+} // BootFreqInitAttributes
+
+
+fapi2::ReturnCode
+setDPLLFrequency(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+                 const uint16_t i_DpllBootFreqMult
+                )
+{
+    fapi2::buffer<uint64_t> l_data;
+
+
+    auto l_present_eqs = i_target.getChildren<fapi2::TARGET_TYPE_EQ>(fapi2::TARGET_STATE_FUNCTIONAL);
+
+    l_data.insertFromRight<17, 11>(i_DpllBootFreqMult);
+
+    for(auto l_tlst : l_present_eqs)
+    {
+        FAPI_TRY(fapi2::putScom(l_tlst,  EQ_QPPM_DPLL_FREQ, l_data));
+        //@todo,Determine ff_slew rate value RTC 140053
+        FAPI_TRY(fapi2::putScom(l_tlst,  EQ_QPPM_DPLL_CTRL,  0));
+
+    }
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+
+// Hardware procedure
+fapi2::ReturnCode
+p9_sbe_setup_boot_freq(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+    // Boot frequency variable
+    uint16_t l_boot_frequency_multiplier;
+
+    // Read Boot freq mult attribute
+    FAPI_TRY(BootFreqInitAttributes(i_target, l_boot_frequency_multiplier));
+
+    // Set Boot Frequency
+
+    FAPI_TRY(setDPLLFrequency(i_target,
+                              l_boot_frequency_multiplier),
+             "Setting Boot Frequency");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+} // Procedure
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.H
new file mode 100644
index 00000000..c41909ae
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_setup_boot_freq.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file  p9_sbe_setup_boot_freq.H
+/// @brief Setup Boot Frequency
+///
+/// *HW Owner    : Sudheendra K Srivathsa <sudheendraks@in.ibm.com>
+/// *FW Owner    : Sangeetha T S <sangeet2@in.ibm.com>
+/// *Team        : PM
+/// *Consumed by : SBE
+/// *Level       : 2
+///
+
+#ifndef __P9_SBE_SETUP_BOOT_FREQ_H__
+#define __P9_SBE_SETUP_BOOT_FREQ_H__
+
+/// @typedef p9_sbe_setup_boot_freq_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_sbe_setup_boot_freq_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+extern "C"
+{
+
+/// @brief Read an attribute containing the boot frequency and set that
+///        into each configured EQ chiplet.
+/// @param [in] i_target TARGET_TYPE_PROC_CHIP
+/// @attr
+/// @attritem ATTR_BOOT_FREQ_MULT - 11 bit frequency multiplier of refclk
+/// @return FAPI2_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_sbe_setup_boot_freq(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+} // extern C
+
+#endif  // __P9_SBE_SETUP_BOOT_FREQ_H__
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C
new file mode 100644
index 00000000..e7797e75
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C
@@ -0,0 +1,82 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.C $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_sbe_setup_evid.C
+/// @brief Setup External Voltage IDs and Boot Frequency
+///
+// *HW Owner    : Greg Still <stillgs@us.ibm.com>
+// *FW Owner    : Sangeetha T S <sangeet2@in.ibm.com>
+// *Team        : PM
+// *Consumed by : SBE
+// *Level       : 1
+///
+/// @verbatim
+/// Procedure Summary:
+///   - Use Attributes to send VDD, VCS via the AVS bus to VRMs
+///   - Use Attributes to adjust the VDN and send via I2C to VRM
+///   - Read core frequency ATTR and write to the Quad PPM
+/// @endverbatim
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+#include <fapi2.H>
+#include "p9_sbe_setup_evid.H"
+
+//-----------------------------------------------------------------------------
+// Procedure
+//-----------------------------------------------------------------------------
+
+fapi2::ReturnCode
+p9_sbe_setup_evid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+
+    //fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS;
+
+    // Substep indicators
+
+    // commented out in Level 1 to not have "unused variable" warnings
+    // until the SBE substep management "macro" or "call" is defined.
+
+    // const uint32_t STEP_SBE_EVID_START              = 0x1;
+    // const uint32_t STEP_SBE_EVID_CONFIG             = 0x2;
+    // const uint32_t STEP_SBE_EVID_WRITE_VDN          = 0x3;
+    // const uint32_t STEP_SBE_EVID_POLL_VDN_STATUS    = 0x4;
+    // const uint32_t STEP_SBE_EVID_WRITE_VDD          = 0x5;
+    // const uint32_t STEP_SBE_EVID_POLL_VDD_STATUS    = 0x6;
+    // const uint32_t STEP_SBE_EVID_WRITE_VCS          = 0x7;
+    // const uint32_t STEP_SBE_EVID_POLL_VCS_STATUS    = 0x8;
+    // const uint32_t STEP_SBE_EVID_TIMEOUT            = 0x9;
+    // const uint32_t STEP_SBE_EVID_BOOT_FREQ          = 0xA;
+    // const uint32_t STEP_SBE_EVID_COMPLETE           = 0xB;
+
+// The inclusion of the following will cause a "label 'fapi_try_exit' defined but not used"
+// compile error in Cronus.  This will be uncommented when FAPI_TRY functions are added
+// during the real procedure development.  However, this is NOT needed for Level 1.
+//fapi_try_exit:
+    return fapi2::current_err;
+
+} // Procedure
+
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H
new file mode 100644
index 00000000..a1ab2263
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H
@@ -0,0 +1,65 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_setup_evid.H $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_sbe_setup_evid.H
+/// @brief Setup External Voltage IDs and Boot Frequency
+///
+/// *HW Owner    : Greg Still <stillgs@us.ibm.com>
+/// *FW Owner    : Sangeetha T S <sangeet2@in.ibm.com>
+/// *Team        : PM
+/// *Consumed by : SBE
+/// *Level       : 1
+///
+
+#ifndef __P9_SBE_SETUP_EVID_H__
+#define __P9_SBE_SETUP_EVID_H__
+
+extern "C"
+{
+
+/// @typedef p9_sbe_setup_evid_FP_t
+/// function pointer typedef definition for HWP call support
+    typedef fapi2::ReturnCode (*p9_sbe_setup_evid_FP_t) (
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief Read attributes containing this part's boot voltages (VDD, VCS and VDN)
+///        and set these voltage using the AVSBUS interface (VDD, VCS) an I2C (VDN).
+///        Also reads a differnt attribute containing the boot frequency and set that
+///        into each configured EQ chiplet.
+/// @param [in] i_target TARGET_TYPE_PROC_CHIP
+/// @attr
+/// @attritem   ATTR_BOOT_FREQ          uint16_t - 9 bit frequency multiplier of the refclk right justified
+/// @attritem   ATTR_VCS_BOOT_VOLTAGE   uint16_t - 1mV grandularity setting for the VCS rail
+/// @attritem   ATTR_VDD_BOOT_VOLTAGE   uint16_t - 1mV grandularity setting for the VDD rail
+/// @attritem   ATTR_VDN_BOOT_VOLTAGE   uint16_t - 1mV grandularity setting for the VDN rail
+///
+/// @retval FAPI_RC_SUCCESS
+    fapi2::ReturnCode
+    p9_sbe_setup_evid(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+
+} // extern C
+
+#endif  // __P9_SBE_SETUP_EVID_H__
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C
new file mode 100644
index 00000000..f55ae68d
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C
@@ -0,0 +1,327 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_startclock_chiplets.C
+///
+/// @brief Start clock procedure for XBUS, OBUS, PCIe
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_startclock_chiplets.H"
+//## auto_generated
+#include "p9_const_common.H"
+
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
+#include <p9_perv_sbe_cmn.H>
+#include <p9_sbe_common.H>
+
+
+enum P9_SBE_STARTCLOCK_CHIPLETS_Private_Constants
+{
+    DONT_STARTMASTER = 0x0,
+    DONT_STARTSLAVE = 0x0,
+    CLOCK_CMD = 0x1,
+    CLOCK_TYPES = 0x7,
+    REGIONS_ALL_EXCEPT_VITAL_NESTPLL = 0x7FE
+};
+
+static fapi2::ReturnCode p9_sbe_startclock_chiplets_get_attr_pg(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    fapi2::buffer<uint32_t>& o_attr_pg);
+
+static fapi2::ReturnCode p9_sbe_startclock_chiplets_ob_fence_drop(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint64_t> i_pg_vector);
+
+static fapi2::ReturnCode p9_sbe_startclock_chiplets_pci_fence_drop(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint64_t> i_pg_vector);
+
+static fapi2::ReturnCode p9_sbe_startclock_chiplets_set_ob_ratio(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const uint8_t i_attr);
+
+static fapi2::ReturnCode p9_sbe_startclock_chiplets_sync_config(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+static fapi2::ReturnCode p9_sbe_startclock_chiplets_xb_fence_drop(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint64_t> i_pg_vector);
+
+fapi2::ReturnCode p9_sbe_startclock_chiplets(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_pg_vector;
+    fapi2::buffer<uint64_t> l_regions;
+    fapi2::buffer<uint8_t> l_attr_obus_ratio;
+    fapi2::buffer<uint32_t> l_attr_pg;
+    FAPI_INF("p9_sbe_startclock_chiplets: Entering ...");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OBUS_RATIO_VALUE, i_target_chip,
+                           l_attr_obus_ratio));
+
+    for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_OBUS, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_TRY(p9_sbe_startclock_chiplets_set_ob_ratio(l_trgt_chplt,
+                 l_attr_obus_ratio));
+    }
+
+    for (auto l_target_cplt :
+         i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_NEST |
+                                           fapi2::TARGET_FILTER_TP), fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_TRY(p9_sbe_common_get_pg_vector(l_target_cplt, l_pg_vector));
+        FAPI_DBG("partial good targets vector: %#018lX", l_pg_vector);
+    }
+
+    for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
+                                           fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
+          fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_TRY(p9_sbe_startclock_chiplets_get_attr_pg(l_trgt_chplt, l_attr_pg));
+
+        FAPI_DBG("Call p9_sbe_common_cplt_ctrl_action_function for xbus, obus, pcie chiplets");
+        FAPI_TRY(p9_sbe_common_cplt_ctrl_action_function(l_trgt_chplt, l_attr_pg));
+
+        FAPI_DBG("Disable listen to sync for all non-master/slave chiplets");
+        FAPI_TRY(p9_sbe_startclock_chiplets_sync_config(l_trgt_chplt));
+
+        FAPI_DBG("call module align chiplets for xbus, obus, pcie chiplets");
+        FAPI_TRY(p9_sbe_common_align_chiplets(l_trgt_chplt));
+
+        FAPI_DBG("Region setup ");
+        FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_trgt_chplt,
+                 REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_regions));
+        FAPI_DBG("Regions value: %#018lX", l_regions);
+
+        FAPI_DBG("Call module clock start stop for xbus, obus, pcie chiplets");
+        FAPI_TRY(p9_sbe_common_clock_start_stop(l_trgt_chplt, CLOCK_CMD,
+                                                DONT_STARTSLAVE, DONT_STARTMASTER, l_regions, CLOCK_TYPES));
+    }
+
+    for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_XBUS, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Drop chiplet fence for Xbus");
+        FAPI_TRY(p9_sbe_startclock_chiplets_xb_fence_drop(l_trgt_chplt, l_pg_vector));
+    }
+
+    for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_OBUS, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Drop Chiplet fence for Obus");
+        FAPI_TRY(p9_sbe_startclock_chiplets_ob_fence_drop(l_trgt_chplt, l_pg_vector));
+    }
+
+    for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (fapi2::TARGET_FILTER_ALL_PCI, fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("Drop chiplet fence for PCIe");
+        FAPI_TRY(p9_sbe_startclock_chiplets_pci_fence_drop(l_trgt_chplt, l_pg_vector));
+    }
+
+    for (auto l_trgt_chplt : i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>
+         (static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_ALL_OBUS |
+                                           fapi2::TARGET_FILTER_ALL_PCI | fapi2::TARGET_FILTER_XBUS),
+          fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+        FAPI_DBG("call  sbe_common_flushmode for xbus, obus, pcie chiplets");
+        FAPI_TRY(p9_sbe_common_flushmode(l_trgt_chplt));
+    }
+
+    FAPI_INF("p9_sbe_startclock_chiplets: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief get attr_pg for the chiplet
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[out]    o_attr_pg       ATTR_PG for the chiplet
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_startclock_chiplets_get_attr_pg(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    fapi2::buffer<uint32_t>& o_attr_pg)
+{
+    FAPI_INF("p9_sbe_startclock_chiplets_get_attr_pg: Entering ...");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, o_attr_pg));
+
+    FAPI_INF("p9_sbe_startclock_chiplets_get_attr_pg: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Drop chiplet fence for OB chiplet
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_pg_vector     Pg vector of targets
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_startclock_chiplets_ob_fence_drop(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint64_t> i_pg_vector)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_startclock_chiplets_ob_fence_drop: Entering ...");
+
+    FAPI_INF("Drop chiplet fence");
+
+    //Setting NET_CTRL0 register value
+    if (i_pg_vector.getBit<2>() == 1)
+    {
+        l_data64.flush<1>();
+        //NET_CTRL0.FENCE_EN = (i_pg_vector.getBit<2>() == 1) ? 0
+        l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>();
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64));
+    }
+
+    FAPI_INF("p9_sbe_startclock_chiplets_ob_fence_drop: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Drop chiplet fence for pcie chiplet
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_pg_vector     Pg vector of targets
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_startclock_chiplets_pci_fence_drop(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint64_t> i_pg_vector)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_startclock_chiplets_pci_fence_drop: Entering ...");
+
+    FAPI_INF("Drop chiplet fence");
+
+    //Setting NET_CTRL0 register value
+    if (i_pg_vector.getBit<3>() == 1)
+    {
+        l_data64.flush<1>();
+        //NET_CTRL0.FENCE_EN = (i_pg_vector.getBit<3>() == 1) ? 0
+        l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>();
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64));
+    }
+
+    FAPI_INF("p9_sbe_startclock_chiplets_pci_fence_drop: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief set obus ratio
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_attr          Attribute that holds the OBUS ratio value
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_startclock_chiplets_set_ob_ratio(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const uint8_t i_attr)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_startclock_chiplets_set_ob_ratio: Entering ...");
+
+    //Setting CPLT_CONF1 register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_CPLT_CONF1, l_data64));
+    l_data64.insertFromRight<16, 2>(i_attr);  //CPLT_CONF1.TC_OB_RATIO_DC = i_attr
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CONF1, l_data64));
+
+    FAPI_INF("p9_sbe_startclock_chiplets_set_ob_ratio: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Disable listen to sync for all non-master / slave chiplets
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_startclock_chiplets_sync_config(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_startclock_chiplets_sync_config: Entering ...");
+
+    //Setting SYNC_CONFIG register value
+    FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_SYNC_CONFIG, l_data64));
+    l_data64.setBit<4>();  //SYNC_CONFIG.LISTEN_TO_SYNC_PULSE_DIS = 0b1
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_SYNC_CONFIG, l_data64));
+
+    FAPI_INF("p9_sbe_startclock_chiplets_sync_config: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Drop chiplet fence for XB chiplet
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_pg_vector     vector of targets
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_startclock_chiplets_xb_fence_drop(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
+    const fapi2::buffer<uint64_t> i_pg_vector)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_startclock_chiplets_xb_fence_drop: Entering ...");
+
+    FAPI_INF("Drop chiplet fence");
+
+    //Setting NET_CTRL0 register value
+    if (i_pg_vector.getBit<1>() == 1)
+    {
+        l_data64.flush<1>();
+        //NET_CTRL0.FENCE_EN = (i_pg_vector.getBit<1>() == 1) ? 0
+        l_data64.clearBit<PERV_1_NET_CTRL0_FENCE_EN>();
+        FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WAND, l_data64));
+    }
+
+    FAPI_INF("p9_sbe_startclock_chiplets_xb_fence_drop: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.H
new file mode 100644
index 00000000..a9e777f6
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.H
@@ -0,0 +1,60 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_startclock_chiplets.H
+///
+/// @brief Start clock procedure for XBUS, OBUS, PCIe
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_STARTCLOCK_CHIPLETS_H_
+#define _P9_SBE_STARTCLOCK_CHIPLETS_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_startclock_chiplets_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief Start Xbus, Obus, PCIe clocks
+/// Start clocks on configured chiplets for all chips (master and slaves)
+///
+/// @param[in]     i_target_chiplets   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_startclock_chiplets(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chiplets);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C
new file mode 100644
index 00000000..151aa89d
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C
@@ -0,0 +1,159 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.C $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_arrayinit.C
+///
+/// @brief SBE PRV Array Init Procedure
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_tp_arrayinit.H"
+//## auto_generated
+#include "p9_const_common.H"
+
+#include <p9_misc_scom_addresses.H>
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
+#include <p9_perv_sbe_cmn.H>
+
+
+enum P9_SBE_TP_ARRAYINIT_Private_Constants
+{
+    REGIONS_EXCEPT_PIB_NET_PLL = 0x4FE,
+    SCAN_TYPES = 0xDCF,
+    LOOP_COUNTER = 0x0000000000042FFF,
+    START_ABIST_MATCH_VALUE = 0x0000000F00000000,
+    SELECT_SRAM = 0x1,
+    SELECT_EDRAM = 0x0,
+    PIBMEM_EXCLUDE_ABIST = 0xC000000000000000,
+    PIBMEM_INCLUDE_ABIST = 0x8000000000000000
+};
+
+static fapi2::ReturnCode p9_sbe_tp_arrayinit_sdisn_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip,
+    const fapi2::buffer<uint8_t> i_attr,
+    const bool i_set);
+
+fapi2::ReturnCode p9_sbe_tp_arrayinit(const
+                                      fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    fapi2::buffer<uint16_t> l_regions;
+    fapi2::buffer<uint8_t> l_attr_read;
+
+    FAPI_INF("p9_sbe_tp_arrayinit: Entering ...");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SDISN_SETUP, i_target_chip, l_attr_read));
+
+    FAPI_DBG("Exclude PIBMEM from TP array init");
+    //Setting PIBMEM_REPAIR_REGISTER_0 register value
+    //PIB.PIBMEM_REPAIR_REGISTER_0 = 0xC000000000000000
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_PIBMEM_REPAIR_REGISTER_0, PIBMEM_EXCLUDE_ABIST ));
+
+    FAPI_DBG("set sdis_n");
+    FAPI_TRY(p9_sbe_tp_arrayinit_sdisn_setup(
+                 i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
+                         fapi2::TARGET_STATE_FUNCTIONAL)[0], l_attr_read, true));
+
+    FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(
+                 i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
+                         fapi2::TARGET_STATE_FUNCTIONAL)[0], REGIONS_EXCEPT_PIB_NET_PLL, l_regions));
+    FAPI_DBG("l_regions value: %#018lX", l_regions);
+
+    FAPI_DBG("Call ARRAY INIT Module for Pervasive Chiplet");
+    FAPI_TRY(p9_perv_sbe_cmn_array_init_module(
+                 i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
+                         fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions, LOOP_COUNTER, SELECT_SRAM,
+                 SELECT_EDRAM, START_ABIST_MATCH_VALUE));
+
+    FAPI_DBG("Call SCAN0 Module for Pervasive Chiplet");
+    FAPI_TRY(p9_perv_sbe_cmn_scan0_module(
+                 i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
+                         fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions, SCAN_TYPES));
+
+    FAPI_DBG("clear sdis_n");
+    FAPI_TRY(p9_sbe_tp_arrayinit_sdisn_setup(
+                 i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
+                         fapi2::TARGET_STATE_FUNCTIONAL)[0], l_attr_read, false));
+
+    FAPI_DBG("Add PIBMEM back to TP array init");
+    //Setting PIBMEM_REPAIR_REGISTER_0 register value
+    //PIB.PIBMEM_REPAIR_REGISTER_0 = 0x8000000000000000
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_PIBMEM_REPAIR_REGISTER_0, PIBMEM_INCLUDE_ABIST));
+
+    FAPI_INF("p9_sbe_tp_arrayinit: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief Sdis_n set or clear
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PERV target
+/// @param[in]     i_attr          Attribute to decide to sdis_n setup
+/// @param[in]     i_set           set or clear the LCBES condition
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_tp_arrayinit_sdisn_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chip,
+    const fapi2::buffer<uint8_t> i_attr,
+    const bool i_set)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_tp_arrayinit_sdisn_setup: Entering ...");
+
+    if ( i_attr )
+    {
+        if ( i_set )
+        {
+            //Setting CPLT_CONF0 register value
+            l_data64.flush<0>();
+            //CPLT_CONF0.CTRL_CC_SDIS_DC_N = 1
+            l_data64.setBit<PERV_1_CPLT_CONF0_CTRL_CC_SDIS_DC_N>();
+            FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF0_OR, l_data64));
+        }
+        else
+        {
+            //Setting CPLT_CONF0 register value
+            l_data64.flush<0>();
+            //CPLT_CONF0.CTRL_CC_SDIS_DC_N = 0
+            l_data64.setBit<PERV_1_CPLT_CONF0_CTRL_CC_SDIS_DC_N>();
+            FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CPLT_CONF0_CLEAR, l_data64));
+        }
+    }
+
+    FAPI_INF("p9_sbe_tp_arrayinit_sdisn_setup: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H
new file mode 100644
index 00000000..9ab5e359
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H
@@ -0,0 +1,61 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_arrayinit.H
+///
+/// @brief SBE PRV Array Init Procedure
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_TP_ARRAYINIT_H_
+#define _P9_SBE_TP_ARRAYINIT_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_tp_arrayinit_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief -- Array Init for PRV Cplt
+/// -- Scan0 of PRV Chiplet (except PIB/PCB)
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_tp_arrayinit(const
+                                          fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C
new file mode 100644
index 00000000..c953c3cf
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C
@@ -0,0 +1,134 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_chiplet_init1.C
+///
+/// @brief Initial steps of PIB AND PCB
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_tp_chiplet_init1.H"
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
+#include <p9_perv_sbe_cmn.H>
+
+
+enum P9_SBE_TP_CHIPLET_INIT1_Private_Constants
+{
+    SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCE,
+    REGIONS_EXCEPT_VITAL_PIB_NET = 0x4FF, // Regions excluding VITAL, PIB and NET
+    SCAN_TYPES_TIME_GPTR_REPR = 0x230
+};
+
+fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    fapi2::buffer<uint16_t> l_regions;
+    fapi2::buffer<uint64_t> l_data64;
+    fapi2::buffer<uint8_t> l_read_attr;
+    FAPI_INF("p9_sbe_tp_chiplet_init1: Entering ...");
+
+    FAPI_DBG("Disable local clock gating VITAL");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING,
+                           i_target_chip, l_read_attr));
+    FAPI_DBG("l_read_attr is %d", l_read_attr);
+
+    if (l_read_attr)
+    {
+        //Getting PERV_CTRL0 register value
+        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
+                                l_data64))
+        //PERV_PERV_CTRL0_SET_TP_VITL_ACT_DIS_DC = 1
+        l_data64.setBit<PERV_PERV_CTRL0_SET_TP_VITL_ACT_DIS_DC>();
+        FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
+                                l_data64));
+    }
+
+    FAPI_DBG("Release PCB Reset");
+    //Setting ROOT_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    //PIB.ROOT_CTRL0.PCB_RESET_DC = 0
+    l_data64.clearBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+
+    FAPI_DBG("Set Chiplet Enable");
+    //Setting PERV_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+    //PIB.PERV_CTRL0.TP_CHIPLET_EN_DC = 1
+    l_data64.setBit<PERV_PERV_CTRL0_SET_TP_CHIPLET_EN_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+
+    FAPI_DBG("Drop TP Chiplet Fence Enable");
+    //Setting PERV_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+    //PIB.PERV_CTRL0.TP_FENCE_EN_DC = 0
+    l_data64.clearBit<PERV_PERV_CTRL0_SET_TP_FENCE_EN_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+
+    FAPI_DBG("Drop Global Endpoint reset");
+    //Setting ROOT_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    //PIB.ROOT_CTRL0.GLOBAL_EP_RESET_DC = 0
+    l_data64.clearBit<PERV_ROOT_CTRL0_SET_GLOBAL_EP_RESET_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    FAPI_DBG("Switching PIB trace bus to SBE tracing");
+
+    FAPI_DBG("Drop OOB Mux");
+    //Setting ROOT_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    l_data64.clearBit<PERV_ROOT_CTRL0_SET_OOB_MUX>();  //PIB.ROOT_CTRL0.OOB_MUX = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+
+    FAPI_DBG("Region setup call");
+    FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(
+                 i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
+                         fapi2::TARGET_STATE_FUNCTIONAL)[0], REGIONS_EXCEPT_VITAL_PIB_NET, l_regions));
+    FAPI_DBG("l_regions value : %#018lX", l_regions);
+
+    FAPI_DBG("run scan0 module for region except vital,PIB,net, scan types GPTR, TIME, REPR");
+    FAPI_TRY(p9_perv_sbe_cmn_scan0_module(
+                 i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
+                         fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions, SCAN_TYPES_TIME_GPTR_REPR));
+
+    FAPI_DBG("run scan0 module for region except vital,PIB,net, scan types except GPTR, TIME, REPR");
+    FAPI_TRY(p9_perv_sbe_cmn_scan0_module(
+                 i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
+                         fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions,
+                 SCAN_TYPES_EXCEPT_TIME_GPTR_REPR));
+
+    FAPI_INF("p9_sbe_tp_chiplet_init1: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H
new file mode 100644
index 00000000..39383792
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H
@@ -0,0 +1,62 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_chiplet_init1.H
+///
+/// @brief Initial steps of PIB AND PCB
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_TP_CHIPLET_INIT1_H_
+#define _P9_SBE_TP_CHIPLET_INIT1_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init1_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief Releases the Pervasive Control Bus (PCB) reset
+/// Sets TP chiplet enable
+/// Drops pervasive chiplet fences
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.C
new file mode 100644
index 00000000..69c6f6c3
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.C
@@ -0,0 +1,53 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_chiplet_init2.C
+///
+/// @brief Run scan 0 module for pervasive
+//------------------------------------------------------------------------------
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_tp_chiplet_init2.H"
+
+
+fapi2::ReturnCode p9_sbe_tp_chiplet_init2(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+
+    FAPI_INF("p9_sbe_tp_chiplet_init2: Entering ...");
+
+
+    FAPI_INF("p9_sbe_tp_chiplet_init2: Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.H
new file mode 100644
index 00000000..34d94425
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.H
@@ -0,0 +1,60 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init2.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_chiplet_init2.H
+///
+/// @brief Run scan 0 module for pervasive
+//------------------------------------------------------------------------------
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_TP_CHIPLET_INIT2_H_
+#define _P9_SBE_TP_CHIPLET_INIT2_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init2_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief -- Initialize TP Hangcounter 6
+/// -- Scan Repair, Time and GPTR for PRV Chiplet
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_tp_chiplet_init2(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C
new file mode 100644
index 00000000..c7af39d3
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C
@@ -0,0 +1,371 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_chiplet_init3.C
+///
+/// @brief TP Chiplet Start Clocks
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_tp_chiplet_init3.H"
+//## auto_generated
+#include "p9_const_common.H"
+
+#include <p9_misc_scom_addresses.H>
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
+#include <p9_perv_sbe_cmn.H>
+#include <p9_sbe_common.H>
+
+
+enum P9_SBE_TP_CHIPLET_INIT3_Private_Constants
+{
+    START_CMD = 0x1,
+    REGIONS_ALL_EXCEPT_PIB_NET = 0x4FF,
+    CLOCK_TYPES = 0x7,
+    HW_NS_DELAY = 100000, // unit is nano seconds
+    SIM_CYCLE_DELAY = 1000, // unit is sim cycles
+    POLL_COUNT = 300, // Observed Number of times CBS read for CBS_INTERNAL_STATE_VECTOR
+    OSC_ERROR_MASK = 0xF700000000000000, // Mask OSC errors
+    LFIR_ACTION0_VALUE = 0x0000000000000000,
+    LFIR_ACTION1_VALUE = 0xFFFFBC2BFC7FFFFF,
+    FIR_MASK_VALUE = 0x0000000000000000
+};
+
+static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_clock_test2(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+
+static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_region_fence_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet);
+
+fapi2::ReturnCode p9_sbe_tp_chiplet_init3(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    bool l_read_reg = 0;
+    fapi2::buffer<uint32_t> l_pfet_value;
+    fapi2::buffer<uint32_t> l_attr_pfet;
+    fapi2::buffer<uint64_t> l_regions;
+    fapi2::buffer<uint64_t> l_kvref_reg;
+    fapi2::Target<fapi2::TARGET_TYPE_PERV> l_tpchiplet =
+        i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP,
+                fapi2::TARGET_STATE_FUNCTIONAL)[0];
+    fapi2::buffer<uint64_t> l_data64;
+    int l_timeout = 0;
+    FAPI_INF("p9_sbe_tp_chiplet_init3: Entering ...");
+
+    FAPI_DBG("Reading ATTR_PFET_OFF_CONTROLS");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PFET_OFF_CONTROLS, i_target_chip,
+                           l_pfet_value));
+
+    FAPI_DBG("Switch pervasive chiplet OOB mux");
+    //Setting ROOT_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    l_data64.clearBit<PERV_ROOT_CTRL0_SET_OOB_MUX>();  //PIB.ROOT_CTRL0.OOB_MUX = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+
+    FAPI_DBG("Reset PCB Master Interrupt Register");
+    //Setting INTERRUPT_TYPE_REG register value
+    //PIB.INTERRUPT_TYPE_REG = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PIB_INTERRUPT_TYPE_REG, 0));
+
+    FAPI_DBG("Clear pervasive chiplet region fence");
+    FAPI_TRY(p9_sbe_tp_chiplet_init3_region_fence_setup(l_tpchiplet));
+
+    FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_tpchiplet,
+             REGIONS_ALL_EXCEPT_PIB_NET, l_regions));
+    FAPI_DBG("l_regions value: %#018lX", l_regions);
+
+    FAPI_TRY(p9_sbe_common_clock_start_stop(l_tpchiplet, START_CMD, 0, 0, l_regions,
+                                            CLOCK_TYPES));
+
+    FAPI_DBG("Calling clock_test2");
+    FAPI_TRY(p9_sbe_tp_chiplet_init3_clock_test2(i_target_chip));
+
+    FAPI_DBG("Drop FSI fence 5");
+    //Setting ROOT_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    //PIB.ROOT_CTRL0.FENCE5_DC = 0
+    l_data64.clearBit<PERV_ROOT_CTRL0_SET_FENCE5_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+
+    l_pfet_value.extractToRight<0, 30>(l_attr_pfet);
+
+    FAPI_DBG("Set pfet off controls");
+    //Setting DISABLE_FORCE_PFET_OFF register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PU_DISABLE_FORCE_PFET_OFF, l_data64));
+    //PIB.DISABLE_FORCE_PFET_OFF.DISABLE_FORCE_PFET_OFF_REG = l_attr_pfet
+    l_data64.insertFromRight<0, 30>(l_attr_pfet);
+    FAPI_TRY(fapi2::putScom(i_target_chip, PU_DISABLE_FORCE_PFET_OFF, l_data64));
+
+    FAPI_DBG("Drop EDRAM control gate and pfet_force_off");
+    //Setting ROOT_CTRL2 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL2_SCOM, l_data64));
+    l_data64.clearBit<16>();  //PIB.ROOT_CTRL2.ROOT_CTRL2_16_FREE_USAGE = 0
+    //PIB.ROOT_CTRL2.TPFSI_TP_PFET_FORCE_OFF_DC = 0
+    l_data64.clearBit<PERV_ROOT_CTRL2_SET_TPFSI_TP_PFET_FORCE_OFF_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL2_SCOM, l_data64));
+
+    //TOD error reg;
+    //config TOD error mask reg;
+    //clear TOD error reg;
+
+    FAPI_DBG("Clear pervasive LFIR");
+    //Setting LOCAL_FIR register value
+    //PERV.LOCAL_FIR = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_LOCAL_FIR_AND, 0));
+
+    FAPI_DBG("Configure pervasive LFIR" );
+    //Setting LOCAL_FIR_ACTION0 register value
+    //PERV.LOCAL_FIR_ACTION0 = LFIR_ACTION0_VALUE
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_LOCAL_FIR_ACTION0,
+                            LFIR_ACTION0_VALUE));
+    //Setting LOCAL_FIR_ACTION1 register value
+    //PERV.LOCAL_FIR_ACTION1 = LFIR_ACTION1_VALUE
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_LOCAL_FIR_ACTION1,
+                            LFIR_ACTION1_VALUE));
+    //Setting LOCAL_FIR_MASK register value
+    //PERV.LOCAL_FIR_MASK = FIR_MASK_VALUE
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_LOCAL_FIR_MASK, FIR_MASK_VALUE));
+
+    // Enables any checkstop if set, to propogate to FSP and get notified
+    //
+    FAPI_DBG("p9_sbe_tp_chiplet_init3: Unmask CFIR Mask");
+    //Setting FIR_MASK register value
+    //PERV.FIR_MASK = FIR_MASK_VALUE
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_FIR_MASK, FIR_MASK_VALUE));
+
+    FAPI_DBG("Setup Pervasive Hangcounter 0:Thermal, 1:OCC/SBE, 2:PBA hang, 3:Nest freq for TOD hang, 5:malefunction alert");
+    //Setting HANG_PULSE_0_REG register value (Setting all fields)
+    //PERV.HANG_PULSE_0_REG.HANG_PULSE_REG_0 = 0b010000
+    l_data64.insertFromRight<0, 6>(0b010000);
+    l_data64.clearBit<6>();  //PERV.HANG_PULSE_0_REG.SUPPRESS_HANG_0 = 0b0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_0_REG, l_data64));
+    //Setting HANG_PULSE_1_REG register value (Setting all fields)
+    //PERV.HANG_PULSE_1_REG.HANG_PULSE_REG_1 = 0b000100
+    l_data64.insertFromRight<0, 6>(0b000100);
+    l_data64.setBit<6>();  //PERV.HANG_PULSE_1_REG.SUPPRESS_HANG_1 = 0b1
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_1_REG, l_data64));
+    //Setting HANG_PULSE_2_REG register value (Setting all fields)
+    //PERV.HANG_PULSE_2_REG.HANG_PULSE_REG_2 = 0b010010
+    l_data64.insertFromRight<0, 6>(0b010010);
+    l_data64.clearBit<6>();  //PERV.HANG_PULSE_2_REG.SUPPRESS_HANG_2 = 0b0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_2_REG, l_data64));
+    //Setting HANG_PULSE_3_REG register value (Setting all fields)
+    //PERV.HANG_PULSE_3_REG.HANG_PULSE_REG_3 = 0b000001
+    l_data64.insertFromRight<0, 6>(0b000001);
+    l_data64.clearBit<6>();  //PERV.HANG_PULSE_3_REG.SUPPRESS_HANG_3 = 0b0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_3_REG, l_data64));
+    //Setting HANG_PULSE_5_REG register value (Setting all fields)
+    //PERV.HANG_PULSE_5_REG.HANG_PULSE_REG_5 = 0b000110
+    l_data64.insertFromRight<0, 6>(0b000110);
+    l_data64.clearBit<6>();  //PERV.HANG_PULSE_5_REG.SUPPRESS_HANG_5 = 0b0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_5_REG, l_data64));
+
+    FAPI_DBG("CHECK FOR XSTOP");
+    //Getting INTERRUPT_TYPE_REG register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PIB_INTERRUPT_TYPE_REG, l_data64));
+    //l_read_reg = PIB.INTERRUPT_TYPE_REG.CHECKSTOP
+    l_read_reg = l_data64.getBit<PERV_INTERRUPT_TYPE_REG_CHECKSTOP>();
+
+    FAPI_ASSERT(l_read_reg == 0,
+                fapi2::XSTOP_ERR()
+                .set_READ_XSTOP(l_read_reg),
+                "XSTOP BIT GET SET");
+
+    FAPI_DBG("Start  calibration");
+    //Setting KVREF_AND_VMEAS_MODE_STATUS_REG register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_KVREF_AND_VMEAS_MODE_STATUS_REG, l_data64));
+    l_data64.setBit<0>();  //KVREF_AND_VMEAS_MODE_STATUS_REG.KVREF_START_CAL = 0b1
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_KVREF_AND_VMEAS_MODE_STATUS_REG, l_data64));
+
+    FAPI_DBG("Check for calibration done");
+    l_timeout = POLL_COUNT;
+
+    //UNTIL KVREF_AND_VMEAS_MODE_STATUS_REG.KVREF_CAL_DONE == 1
+    while (l_timeout != 0)
+    {
+        //Getting KVREF_AND_VMEAS_MODE_STATUS_REG register value
+        FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_KVREF_AND_VMEAS_MODE_STATUS_REG, l_data64));
+        //bool l_poll_data = KVREF_AND_VMEAS_MODE_STATUS_REG.KVREF_CAL_DONE
+        bool l_poll_data = l_data64.getBit<16>();
+
+        if (l_poll_data == 1)
+        {
+            break;
+        }
+
+        fapi2::delay(HW_NS_DELAY, SIM_CYCLE_DELAY);
+        --l_timeout;
+    }
+
+    FAPI_DBG("Loop Count :%d", l_timeout);
+
+    FAPI_ASSERT(l_timeout > 0,
+                fapi2::CALIBRATION_NOT_DONE(),
+                "Calibration not done, bit16 not set");
+
+    FAPI_INF("p9_sbe_tp_chiplet_init3: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief clock test
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_clock_test2(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_read ;
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_tp_chiplet_init3_clock_test2: Entering ...");
+
+    FAPI_DBG("unfence 281D");
+    //Setting ROOT_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+    l_data64.clearBit<0>();  //PIB.ROOT_CTRL0.TPFSI_SBE_FENCE_VTLIO_DC_UNUSED = 0
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64));
+
+    //Getting ROOT_CTRL3 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL3_SCOM,
+                            l_read)); //l_read = PIB.ROOT_CTRL3
+
+    l_read.setBit<27>();
+
+    FAPI_DBG("Set osc_ok latch active");
+    //Setting ROOT_CTRL3 register value
+    //PIB.ROOT_CTRL3 = l_read
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL3_SCOM, l_read));
+
+    FAPI_DBG("Turn on oscilate pgood");
+    //Setting ROOT_CTRL6 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL6_SCOM, l_data64));
+    //PIB.ROOT_CTRL6.TPFSI_OSCSW1_PGOOD = 1
+    l_data64.setBit<PERV_ROOT_CTRL6_SET_TPFSI_OSCSW1_PGOOD>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL6_SCOM, l_data64));
+
+    //Getting ROOT_CTRL3 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL3_SCOM,
+                            l_read)); //l_read = PIB.ROOT_CTRL3
+
+    l_read.clearBit<17>();
+
+    FAPI_DBG("turn off use_osc_1_0");
+    //Setting ROOT_CTRL3 register value
+    //PIB.ROOT_CTRL3 = l_read
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL3_SCOM, l_read));
+
+    FAPI_DBG("Mask OSC err");
+    //Setting OSCERR_MASK register value
+    //PIB.OSCERR_MASK = OSC_ERROR_MASK
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_OSCERR_MASK, OSC_ERROR_MASK));
+
+    FAPI_DBG("reset osc-error_reg");
+    //Setting OSCERR_HOLD register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_OSCERR_HOLD, l_data64));
+    l_data64.clearBit<4, 4>();  //PERV.OSCERR_HOLD.OSCERR_MEM = 0000
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_OSCERR_HOLD, l_data64));
+
+    FAPI_DBG("Resets FIR");
+    //Setting LOCAL_FIR register value
+    l_data64.flush<1>();
+    l_data64.clearBit<36>();
+    l_data64.clearBit<37>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_LOCAL_FIR_AND, l_data64));
+
+#ifndef SIM_ONLY_OSC_SWC_CHK
+
+    FAPI_DBG("check for OSC ok");
+    //Getting SNS1LTH register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SNS1LTH_SCOM,
+                            l_read)); //l_read = PIB.SNS1LTH
+
+    FAPI_ASSERT(l_read.getBit<21>() == 0 && l_read.getBit<28>() == 1,
+                fapi2::MF_OSC_NOT_TOGGLE()
+                .set_READ_SNS1LTH(l_read),
+                "MF oscillator not toggling");
+
+    FAPI_DBG("Osc error active");
+    //Getting OSCERR_HOLD register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_OSCERR_HOLD,
+                            l_read)); //l_read = PERV.OSCERR_HOLD
+
+    FAPI_ASSERT(l_read.getBit<4>() == 0,
+                fapi2::MF_OSC_ERR()
+                .set_READ_OSCERR_HOLD(l_read),
+                "MF oscillator error active");
+
+#endif
+
+    FAPI_INF("p9_sbe_tp_chiplet_init3_clock_test2: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
+
+/// @brief region fence setup
+///
+/// @param[in]     i_target_chiplet   Reference to TARGET_TYPE_PERV target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_region_fence_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet)
+{
+    // Local variable and constant definition
+    fapi2::buffer <uint32_t> l_attr_pg;
+    fapi2::buffer <uint16_t> l_attr_pg_data;
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_tp_chiplet_init3_region_fence_setup: Entering ...");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, l_attr_pg));
+
+    l_attr_pg.invert();
+    l_attr_pg.extractToRight<20, 11>(l_attr_pg_data);
+
+    FAPI_DBG("Drop partial good fences");
+    //Setting CPLT_CTRL1 register value
+    l_data64.flush<0>();
+    l_data64.writeBit<PERV_1_CPLT_CTRL1_TC_VITL_REGION_FENCE>
+    (l_attr_pg.getBit<19>());  //CPLT_CTRL1.TC_VITL_REGION_FENCE = l_attr_pg.getBit<19>()
+    //CPLT_CTRL1.TC_ALL_REGIONS_FENCE = l_attr_pg_data
+    l_data64.insertFromRight<4, 11>(l_attr_pg_data);
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CPLT_CTRL1_CLEAR, l_data64));
+
+    FAPI_INF("p9_sbe_tp_chiplet_init3_region_fence_setup: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.H
new file mode 100644
index 00000000..c5367d97
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.H
@@ -0,0 +1,66 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_chiplet_init3.H
+///
+/// @brief TP Chiplet Start Clocks
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_TP_CHIPLET_INIT3_H_
+#define _P9_SBE_TP_CHIPLET_INIT3_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_init3_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief -- Switches PRV Chiplet OOB mux
+/// -- Reset PCB Master Interrupt Register
+/// -- Drop Pervasive and OCC2PIB Fence in GP0 (bits 19 & 63)
+/// --"Clock Start" command (all other clk domains)
+/// -- Clear force_align in chiplet GP0
+/// -- Clear flushmode_inhibit in chiplet GP0
+/// -- Drop FSI fence 5 (checkstop, interrupt conditions)
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_tp_chiplet_init3(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.C
new file mode 100644
index 00000000..f7960207
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.C
@@ -0,0 +1,61 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_chiplet_reset.C
+///
+/// @brief setup hangcounter 6 for TP chiplet
+//------------------------------------------------------------------------------
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_tp_chiplet_reset.H"
+
+#include "p9_perv_scom_addresses.H"
+
+
+fapi2::ReturnCode p9_sbe_tp_chiplet_reset(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    FAPI_DBG("p9_sbe_tp_chiplet_reset: Entering ...");
+
+    FAPI_DBG("Initializing Hangcounter 6 for PRV Cplt");
+    //Setting HANG_PULSE_6_REG register value
+    //PERV.HANG_PULSE_6_REG = HANG_PULSE_VALUE
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_6_REG,
+                            HANG_PULSE_VALUE));
+
+    FAPI_DBG("p9_sbe_tp_chiplet_reset: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.H
new file mode 100644
index 00000000..441a7a6e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.H
@@ -0,0 +1,65 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_reset.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_chiplet_reset.H
+///
+/// @brief setup hangcounter 6 for TP chiplet
+//------------------------------------------------------------------------------
+// *HWP HWP Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HWP Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_TP_CHIPLET_RESET_H_
+#define _P9_SBE_TP_CHIPLET_RESET_H_
+
+
+#include <fapi2.H>
+
+
+enum P9_SBE_TP_CHIPLET_RESET_Constants
+{
+    HANG_PULSE_VALUE = 0x1400000000000000
+};
+
+typedef fapi2::ReturnCode (*p9_sbe_tp_chiplet_reset_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief Setup hang counter for PCB slaves/master
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_tp_chiplet_reset(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C
new file mode 100644
index 00000000..b8c22322
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_enable_ridi.C
+///
+/// @brief enables ridi bits in RC regs after scan initialize and start clock the pervasive chiplet
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_tp_enable_ridi.H"
+
+#include "p9_perv_scom_addresses.H"
+
+
+fapi2::ReturnCode p9_sbe_tp_enable_ridi(const
+                                        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_DBG("p9_sbe_tp_enable_ridi: Entering ...");
+
+    FAPI_INF("Enable Recievers, Drivers DI1 & DI2");
+    //Setting ROOT_CTRL1 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL1_SCOM, l_data64));
+    l_data64.setBit<19>();  //PIB.ROOT_CTRL1.TP_RI_DC_B = 1
+    l_data64.setBit<20>();  //PIB.ROOT_CTRL1.TP_DI1_DC_B = 1
+    l_data64.setBit<21>();  //PIB.ROOT_CTRL1.TP_DI2_DC_B = 1
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL1_SCOM, l_data64));
+
+    FAPI_DBG("p9_sbe_tp_enable_ridi: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.H
new file mode 100644
index 00000000..c18e9a7f
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.H
@@ -0,0 +1,59 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_enable_ridi.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_enable_ridi.H
+///
+/// @brief enables ridi bits in RC regs after scan initialize and start clock the pervasive chiplet
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner         : sunil kumar <skumar8j@in.ibm.com>
+// *HWP Team             : Perv
+// *HWP Level            : 2
+// *HWP Consumed by      : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_TP_ENABLE_RIDI_H_
+#define _P9_SBE_TP_ENABLE_RIDI_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_tp_enable_ridi_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief Enable drivers/receivers for PRV chiplet
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_tp_enable_ridi(const
+                                            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.C
new file mode 100644
index 00000000..42957145
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.C
@@ -0,0 +1,69 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_gptr_time_initf.C
+///
+/// @brief Scan initialize GPTR, TIME for PERV chiplet
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+
+#include "p9_sbe_tp_gptr_time_initf.H"
+
+fapi2::ReturnCode p9_sbe_tp_gptr_time_initf(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    FAPI_INF("p9_sbe_tp_gptr_time_initf: Entering ...");
+
+    FAPI_DBG("Scan perv_gptr ring");
+    FAPI_TRY(fapi2::putRing(i_target_chip, perv_gptr),
+             "Error from putRing (perv_gptr)");
+    FAPI_DBG("Scan perv_ana_gptr ring");
+    FAPI_TRY(fapi2::putRing(i_target_chip, perv_ana_gptr),
+             "Error from putRing (perv_ana_gptr)");
+    FAPI_DBG("Scan perv_pll_gptr ring");
+    FAPI_TRY(fapi2::putRing(i_target_chip, perv_pll_gptr),
+             "Error from putRing (perv_pll_gptr)");
+    FAPI_DBG("Scan occ_gptr ring");
+    FAPI_TRY(fapi2::putRing(i_target_chip, occ_gptr),
+             "Error from putRing (occ_gptr)");
+    FAPI_DBG("Scan occ_time ring");
+    FAPI_TRY(fapi2::putRing(i_target_chip, occ_time),
+             "Error from putRing (occ_time)");
+    FAPI_DBG("Scan perv_time ring");
+    FAPI_TRY(fapi2::putRing(i_target_chip, perv_time),
+             "Error from putRing (perv_time)");
+
+fapi_try_exit:
+    FAPI_INF("p9_sbe_tp_gptr_time_initf: Exiting ...");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H
new file mode 100644
index 00000000..2b99ade3
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H
@@ -0,0 +1,60 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_initf.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_gptr_time_initf.C
+///
+/// @brief Scan initialize GPTR, TIME for PERV chiplet
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+#ifndef _P9_SBE_TP_GPTR_TIME_INITF_H_
+#define _P9_SBE_TP_GPTR_TIME_INITF_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_tp_gptr_time_initf_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief --Load Scan Repair, Time and GPTR for TP Chiplet
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_tp_gptr_time_initf(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C
new file mode 100644
index 00000000..2c351d74
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C
@@ -0,0 +1,52 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_gptr_time_repr_initf.C
+///
+/// @brief proc sbe tp gptr time repr initf
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_tp_gptr_time_repr_initf.H"
+fapi2::ReturnCode p9_sbe_tp_gptr_time_repr_initf(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    FAPI_DBG("p9_sbe_tp_gptr_time_repr_initf: Entering ...");
+
+    FAPI_DBG("p9_sbe_tp_gptr_time_repr_initf: Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H
new file mode 100644
index 00000000..27ba211c
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H
@@ -0,0 +1,62 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_gptr_time_repr_initf.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_gptr_time_repr_initf.H
+///
+/// @brief proc sbe tp gptr time repr initf
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_TP_GPTR_TIME_REPR_INITF_H_
+#define _P9_SBE_TP_GPTR_TIME_REPR_INITF_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_tp_gptr_time_repr_initf_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief --Load Scan Repair, Time and GPTR for TP Chiplet
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_tp_gptr_time_repr_initf(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.C
new file mode 100644
index 00000000..f1150966
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.C
@@ -0,0 +1,63 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.C $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_initf.C
+///
+/// @brief TP chiplet scaninits for the TP rings
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_tp_initf.H"
+#include "p9_ring_id.h"
+
+fapi2::ReturnCode p9_sbe_tp_initf(const
+                                  fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    FAPI_INF("p9_sbe_tp_initf: Entering ...");
+
+    FAPI_DBG("Scan perv_fure ring");
+    FAPI_TRY(fapi2::putRing(i_target_chip, perv_fure),
+             "Error from putRing (perv_fure)");
+
+    FAPI_DBG("Scan occ_fure ring");
+    FAPI_TRY(fapi2::putRing(i_target_chip, occ_fure),
+             "Error from putRing (occ_fure)");
+
+    FAPI_DBG("Scan perv_ana_func ring");
+    FAPI_TRY(fapi2::putRing(i_target_chip, perv_ana_func),
+             "Error from putRing (perv_ana_func)");
+
+fapi_try_exit:
+    FAPI_INF("p9_sbe_tp_initf: Exiting ...");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H
new file mode 100644
index 00000000..abf1f54c
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H
@@ -0,0 +1,65 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_initf.H $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_initf.H
+///
+/// @brief TP chiplet scaninits for the TP rings
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 2
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_TP_INITF_H_
+#define _P9_SBE_TP_INITF_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_tp_initf_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief -- This doesn't include the gptr/time/repair rings,
+/// -- since they are scanned in tp_chiplet_init2.
+/// -- This doesn't include the net/pib/fuse rings,
+/// -- since they are used by the SBE hardware itself.
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_tp_initf(const
+                                      fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.C
new file mode 100644
index 00000000..7c933122
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.C
@@ -0,0 +1,52 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.C $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_ld_image.C
+///
+/// @brief Proc SBE load Image
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_tp_ld_image.H"
+fapi2::ReturnCode p9_sbe_tp_ld_image(const
+                                     fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    FAPI_DBG("p9_sbe_tp_ld_image: Entering ...");
+
+    FAPI_DBG("p9_sbe_tp_ld_image: Exiting ...");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.H
new file mode 100644
index 00000000..e458d2be
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.H
@@ -0,0 +1,65 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_ld_image.H $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_ld_image.H
+///
+/// @brief Proc SBE load Image
+// *!
+// *! OWNER NAME  : Abhishek Agarwal  Email: abagarw8@in.ibm.com
+// *! BACKUP NAME :                   Email:
+//------------------------------------------------------------------------------
+// *HWP HWP Owner   : Abhishek Agarwal <abagarw8@in.ibm.com>
+// *HWP FW Owner    : Brian Silver <bsilver@us.ibm.com>
+// *HWP Team        : Perv
+// *HWP Level       : 1
+// *HWP Consumed by : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_TP_LD_IMAGE_H_
+#define _P9_SBE_TP_LD_IMAGE_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_tp_ld_image_FP_t)(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief This procedure copies the .pibmem0 section of image from SEEPROM to the PIBMEM.
+/// The pibmem0 section contains the PORE branch table (error handlers) used for the majority of the SEEPROM IPL as well as
+/// performance sensitive routines such as the decompression-scan routine and the LCO loader.
+/// Once the image is loaded then the error handlers are switched to
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_tp_ld_image(const
+                                         fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.C
new file mode 100644
index 00000000..53aed3bb
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.C
@@ -0,0 +1,58 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.C $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_repr_initf.C
+///
+/// @brief Scan initialize REPR for PERV chiplet
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+
+#include "p9_sbe_tp_repr_initf.H"
+
+fapi2::ReturnCode p9_sbe_tp_repr_initf(const
+                                       fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    FAPI_INF("p9_sbe_tp_repr_initf: Entering ...");
+
+    FAPI_DBG("Scan perv_repr ring");
+    FAPI_TRY(fapi2::putRing(i_target_chip, perv_repr),
+             "Error from putRing (perv_repr)");
+
+    FAPI_DBG("Scan occ_repr ring");
+    FAPI_TRY(fapi2::putRing(i_target_chip, occ_repr),
+             "Error from putRing (occ_repr)");
+
+fapi_try_exit:
+    FAPI_INF("p9_sbe_tp_repr_initf: Exiting ...");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H
new file mode 100644
index 00000000..134fc853
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H
@@ -0,0 +1,60 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_repr_initf.H $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_repr_initf.C
+///
+/// @brief Scan initialize REPR for PERV chiplet
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+#ifndef _P9_SBE_TP_REPR_INITF_H_
+#define _P9_SBE_TP_REPR_INITF_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_tp_repr_initf_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief --Scan Repair for TP Chiplet
+///
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_tp_repr_initf(const
+                                           fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C
new file mode 100644
index 00000000..828c855c
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C
@@ -0,0 +1,161 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_switch_gears.C
+///
+/// @brief Switch from refclock to PLL AND adjust I2C
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumarj8@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+//## auto_generated
+#include "p9_sbe_tp_switch_gears.H"
+//## auto_generated
+#include "p9_const_common.H"
+
+#include <p9_misc_scom_addresses.H>
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
+#include <p9_sbe_gear_switcher.H>
+
+
+enum P9_SBE_TP_SWITCH_GEARS_Private_Constants
+{
+    BACKUP_SEEPROM_MAGIC_NUM_ADDRESS = 0xD8A9029000000000, // Magic number value from Backup SEEPROM
+    BUS_STATUS_BUSY_POLL_COUNT = 256,
+    MAGIC_NUMBER = 0x584950205345504D,
+    NORMAL_SEEPROM_MAGIC_NUM_ADDRESS = 0xD8A9009000000000 // Magic number value from SEEPROM
+};
+
+fapi2::ReturnCode p9_sbe_tp_switch_gears(const
+        fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_tp_switch_gears: Entering ...");
+
+#ifdef __PPE__
+
+    FAPI_DBG("switch from refclock to PLL speed");
+    //Setting PERV_CTRL0 register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+    //PIB.PERV_CTRL0.TP_PLLBYP_DC = 0
+    l_data64.clearBit<PERV_PERV_CTRL0_SET_TP_PLLBYP_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64));
+
+    FAPI_TRY(p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting(
+                 i_target_chip));
+
+    FAPI_TRY(p9_sbe_gear_switcher_i2c_stop_sequence(i_target_chip));
+
+    FAPI_DBG("Checking Magic number");
+    FAPI_TRY(p9_sbe_tp_switch_gears_check_magicnumber(i_target_chip));
+fapi_try_exit:
+#endif
+
+    FAPI_INF("p9_sbe_tp_switch_gears: Exiting ...");
+
+    return fapi2::current_err;
+
+}
+
+/// @brief check for magic number
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode p9_sbe_tp_switch_gears_check_magicnumber(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
+{
+    fapi2::buffer<uint64_t> l_read_reg;
+    fapi2::buffer<uint8_t> l_read_attr = 0;
+    int l_timeout = 0;
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_INF("p9_sbe_tp_switch_gears_check_magicnumber: Entering ...");
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BACKUP_SEEPROM_SELECT, i_target_chip,
+                           l_read_attr));
+
+    if ( l_read_attr.getBit<7>() == 1 )
+    {
+        FAPI_DBG("Read magic number from Backup SEEPROM");
+        //Setting CONTROL_REGISTER_B register value
+        //PIB.CONTROL_REGISTER_B = BACKUP_SEEPROM_MAGIC_NUM_ADDRESS
+        FAPI_TRY(fapi2::putScom(i_target_chip, PU_CONTROL_REGISTER_B,
+                                BACKUP_SEEPROM_MAGIC_NUM_ADDRESS));
+    }
+    else
+    {
+        FAPI_DBG("Read magic number from SEEPROM");
+        //Setting CONTROL_REGISTER_B register value
+        //PIB.CONTROL_REGISTER_B = NORMAL_SEEPROM_MAGIC_NUM_ADDRESS
+        FAPI_TRY(fapi2::putScom(i_target_chip, PU_CONTROL_REGISTER_B,
+                                NORMAL_SEEPROM_MAGIC_NUM_ADDRESS));
+    }
+
+    FAPI_DBG("Poll for stop command completion");
+    l_timeout = BUS_STATUS_BUSY_POLL_COUNT;
+
+    //UNTIL STATUS_REGISTER_B.BUS_STATUS_BUSY_0 == 0
+    while (l_timeout != 0)
+    {
+        //Getting STATUS_REGISTER_B register value
+        FAPI_TRY(fapi2::getScom(i_target_chip, PU_STATUS_REGISTER_B, l_data64));
+        //bool l_poll_data = PIB.STATUS_REGISTER_B.BUS_STATUS_BUSY_0
+        bool l_poll_data = l_data64.getBit<44>();
+
+        if (l_poll_data == 0)
+        {
+            break;
+        }
+
+        --l_timeout;
+    }
+
+    FAPI_DBG("Loop Count :%d", l_timeout);
+
+    FAPI_ASSERT(l_timeout > 0,
+                fapi2::BUS_STATUS_BUSY0(),
+                "ERROR:BUS_STSTUS_BUSY_0 NOT SET TO 0");
+
+    FAPI_DBG("Reading the value of DATA0TO7_REGISTER_B");
+    //Getting DATA0TO7_REGISTER_B register value
+    FAPI_TRY(fapi2::getScom(i_target_chip, PU_DATA0TO7_REGISTER_B,
+                            l_read_reg)); //l_read_reg = PIB.DATA0TO7_REGISTER_B
+
+    FAPI_ASSERT(l_read_reg == MAGIC_NUMBER,
+                fapi2::MAGIC_NUMBER_NOT_VALID(),
+                "ERROR: Magic number not matching");
+
+    FAPI_INF("p9_sbe_tp_switch_gears_check_magicnumber: Exiting ...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.H
new file mode 100644
index 00000000..a53d025f
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.H
@@ -0,0 +1,67 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//------------------------------------------------------------------------------
+/// @file  p9_sbe_tp_switch_gears.H
+///
+/// @brief Switch from refclock to PLL AND adjust I2C
+//------------------------------------------------------------------------------
+// *HWP HW Owner        : Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
+// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
+// *HWP FW Owner        : sunil kumar <skumarj8@in.ibm.com>
+// *HWP Team            : Perv
+// *HWP Level           : 2
+// *HWP Consumed by     : SBE
+//------------------------------------------------------------------------------
+
+
+#ifndef _P9_SBE_TP_SWITCH_GEARS_H_
+#define _P9_SBE_TP_SWITCH_GEARS_H_
+
+
+#include <fapi2.H>
+
+
+typedef fapi2::ReturnCode (*p9_sbe_tp_switch_gears_FP_t)(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&);
+
+/// @brief Switch from refclcok to PLL speed (leave bypass)
+/// Read new I2C Bit Rate Divisor setting from mailbox
+/// Adjust I2C bit rate divisor setting in I2CM B mode reg
+/// Send a stop sequence on I2C
+/// Poll for stop command completion
+/// Check for magic number
+///
+/// @param[in]     i_target_chip   Reference to TARGET_TYPE_PROC_CHIP target
+/// @return  FAPI2_RC_SUCCESS if success, else error code.
+extern "C"
+{
+    fapi2::ReturnCode p9_sbe_tp_switch_gears(const
+            fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+}
+
+fapi2::ReturnCode p9_sbe_tp_switch_gears_check_magicnumber(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/perv/pervfiles.mk b/src/import/chips/p9/procedures/hwp/perv/pervfiles.mk
new file mode 100644
index 00000000..d4b77bb7
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/perv/pervfiles.mk
@@ -0,0 +1,76 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/hwp/perv/pervfiles.mk $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file pervfiles.mk
+#
+#  @brief mk for including perv object files
+#
+##########################################################################
+# Object Files
+##########################################################################
+
+PERV-CPP-SOURCES =p9_sbe_arrayinit.C
+PERV-CPP-SOURCES +=p9_sbe_attr_setup.C
+PERV-CPP-SOURCES +=p9_sbe_check_master.C
+PERV-CPP-SOURCES +=p9_sbe_chiplet_init.C
+PERV-CPP-SOURCES +=p9_sbe_chiplet_pll_initf.C
+PERV-CPP-SOURCES +=p9_sbe_chiplet_pll_setup.C
+PERV-CPP-SOURCES +=p9_sbe_chiplet_reset.C
+PERV-CPP-SOURCES +=p9_sbe_enable_seeprom.C
+PERV-CPP-SOURCES +=p9_sbe_gptr_time_repr_initf.C
+PERV-CPP-SOURCES +=p9_sbe_lpc_init.C
+PERV-CPP-SOURCES +=p9_sbe_nest_enable_ridi.C
+PERV-CPP-SOURCES +=p9_sbe_nest_initf.C
+PERV-CPP-SOURCES +=p9_sbe_nest_startclocks.C
+PERV-CPP-SOURCES +=p9_sbe_npll_initf.C
+PERV-CPP-SOURCES +=p9_sbe_npll_setup.C
+PERV-CPP-SOURCES +=p9_sbe_select_ex.C
+PERV-CPP-SOURCES +=p9_sbe_startclock_chiplets.C
+PERV-CPP-SOURCES +=p9_sbe_tp_arrayinit.C
+PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init1.C
+PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init2.C
+PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_init3.C
+PERV-CPP-SOURCES +=p9_sbe_tp_chiplet_reset.C
+PERV-CPP-SOURCES +=p9_sbe_tp_enable_ridi.C
+PERV-CPP-SOURCES +=p9_sbe_tp_initf.C
+PERV-CPP-SOURCES +=p9_sbe_tp_ld_image.C
+PERV-CPP-SOURCES +=p9_sbe_setup_evid.C
+PERV-CPP-SOURCES +=p9_perv_sbe_cmn.C
+PERV-CPP-SOURCES +=p9_sbe_common.C
+PERV-CPP-SOURCES +=p9_sbe_check_master_stop15.C
+PERV-CPP-SOURCES +=p9_hcd_cache_dcc_skewadjust_setup.C
+PERV-CPP-SOURCES +=p9_sbe_setup_boot_freq.C
+PERV-CPP-SOURCES +=p9_sbe_io_initf.C
+PERV-CPP-SOURCES +=p9_sbe_gptr_time_initf.C
+PERV-CPP-SOURCES +=p9_sbe_repr_initf.C
+PERV-CPP-SOURCES +=p9_sbe_tp_gptr_time_initf.C
+PERV-CPP-SOURCES +=p9_sbe_tp_repr_initf.C
+PERV-CPP-SOURCES +=p9_sbe_clock_test2.C
+
+PERV-C-SOURCES =
+PERV-S-SOURCES =
+
+PERV_OBJECTS += $(PERV-CPP-SOURCES:.C=.o)
+PERV_OBJECTS += $(PERV-C-SOURCES:.c=.o)
+PERV_OBJECTS += $(PERV-S-SOURCES:.S=.o)
diff --git a/src/import/chips/p9/procedures/hwp/pm/Makefile b/src/import/chips/p9/procedures/hwp/pm/Makefile
new file mode 100644
index 00000000..65f3170a
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/Makefile
@@ -0,0 +1,54 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/hwp/pm/Makefile $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+# This Makefile compiles all of the pm hardware procedure code. See the
+# "pmfiles.mk" file in this directory.
+
+#all generated files from this makefile will end up in obj/pm
+export SUB_OBJDIR = /pm
+
+include img_defs.mk
+include pmfiles.mk
+
+
+OBJS := $(addprefix $(OBJDIR)/, $(PM_OBJECTS))
+
+libpm.a: pm
+	$(AR) crs $(OBJDIR)/libpm.a $(OBJDIR)/*.o
+
+.PHONY: clean pm
+pm: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+clean:
+	rm -fr $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d)
+endif
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.C b/src/import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.C
new file mode 100644
index 00000000..fce9dea9
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.C
@@ -0,0 +1,179 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.C $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_block_wakeup_intr.C
+/// @brief Set/reset the BLOCK_REG_WKUP_SOURCES bit in the PCBS-PM associated
+///          with an EX chiplet
+///
+//  *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com>
+//  *HWP FW Owner: Prem Jha <premjha1@in.ibm.com>
+//  *HWP Team: PM
+//  *HWP Level: 2
+//  *HWP Consumed by: FSP:HS
+///
+/// @verbatim
+/// High-level procedure flow:
+///
+///   With set/reset enum parameter, either set or clear PMGP0(53)
+///
+/// Procedure Prereq:
+///    - System clocks are running
+/// @endverbatim
+///
+//------------------------------------------------------------------------------
+
+
+// ----------------------------------------------------------------------
+// Includes
+// ----------------------------------------------------------------------
+
+#include <p9_block_wakeup_intr.H>
+#include <p9_hcd_common.H>
+
+
+
+// This must stay in sync with enum OP_TYPE enum in header file
+const char* OP_TYPE_STRING[] =
+{
+    "SET",
+    "CLEAR"
+};
+
+
+// ----------------------------------------------------------------------
+// Procedure Function
+// ----------------------------------------------------------------------
+
+/// @brief @brief Set/reset the BLOCK_INTR_INPUTS bit in the Core PPM
+///         associated with an EX chiplet
+
+fapi2::ReturnCode
+p9_block_wakeup_intr(
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_core_target,
+    const p9pmblockwkup::OP_TYPE i_operation)
+{
+    FAPI_INF("> p9_block_wakeup_intr...");
+
+    fapi2::buffer<uint64_t> l_data64 = 0;
+
+    // Get the core number
+    uint8_t l_attr_chip_unit_pos = 0;
+
+    fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv =
+        i_core_target.getParent<fapi2::TARGET_TYPE_PERV>();
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,
+                           l_perv,
+                           l_attr_chip_unit_pos),
+             "fapiGetAttribute of ATTR_CHIP_UNIT_POS failed");
+    l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_CORE_POS_OFFSET;
+
+    // Read for trace
+    {
+        fapi2::buffer<uint64_t> l_cpmmr = 0;
+        fapi2::buffer<uint64_t> l_gpmmr = 0;
+
+        // Read the CPMMR and GPMMR as a trace
+        FAPI_TRY(fapi2::getScom(i_core_target,
+                                C_CPPM_CPMMR,
+                                l_cpmmr),
+                 "getScom of CPMMR failed");
+
+        FAPI_TRY(fapi2::getScom(i_core_target,
+                                C_PPM_GPMMR,
+                                l_gpmmr),
+                 "getScom of GPMMR failed");
+
+        FAPI_DBG("Debug: before setting PPM_WRITE_OVERRIDE on Core %d - CPPMR: 0x%016llX GPMMR: 0x%016llX",
+                 l_attr_chip_unit_pos, l_cpmmr, l_gpmmr);
+    }
+
+    // Ensure access to the GPMMR is in place using CPMMR Write Access
+    // Override.  This will not affect the CME functionality as only the
+    // Block Wake-up bit is being manipulated -- a bit that the CME does
+    // not control but does react upon.
+
+    FAPI_INF("Set the CPPM PPM Write Override");
+    l_data64.flush<0>().setBit<C_CPPM_CPMMR_PPM_WRITE_OVERRIDE>();
+    FAPI_TRY(fapi2::putScom(i_core_target,
+                            C_CPPM_CPMMR_OR,
+                            l_data64),
+             "putScom of CPMMR to set PMM Write Override failed");
+
+    l_data64.flush<0>().setBit<BLOCK_REG_WKUP_EVENTS>();
+
+    switch (i_operation)
+    {
+        case p9pmblockwkup::SET:
+
+            // @todo RTC 144905 Add Special Wakeup setting here when available
+
+            FAPI_INF("Setting GPMMR[Block Interrupt Sources] on Core %d",
+                     l_attr_chip_unit_pos);
+
+            FAPI_TRY(fapi2::putScom(i_core_target,
+                                    C_PPM_GPMMR_OR,
+                                    l_data64),
+                     "Setting GPMMR failed");
+
+            // @todo RTC 144905 Add Special Wakeup clearing here when available
+
+            break;
+
+        case p9pmblockwkup::SET_NOSPWUP:
+            FAPI_INF("Setting GPMMR[Block Interrupt Sources] without Special Wake-up on Core %d",
+                     l_attr_chip_unit_pos);
+
+            FAPI_TRY(fapi2::putScom(i_core_target,
+                                    C_PPM_GPMMR_OR,
+                                    l_data64),
+                     "Setting GPMMR failed");
+            break;
+
+        case p9pmblockwkup::CLEAR:
+            FAPI_INF("Clearing GPMMR[Block Interrupt Sources] on Core %d",
+                     l_attr_chip_unit_pos);
+
+            FAPI_TRY(fapi2::putScom(i_core_target,
+                                    C_PPM_GPMMR_CLEAR,
+                                    l_data64),
+                     "Clearing GPMMR failed");
+            break;
+
+        default:
+            ;
+    }
+
+    FAPI_INF("Clear the CPPM PPM Write Override");
+    l_data64.flush<0>().setBit<C_CPPM_CPMMR_PPM_WRITE_OVERRIDE>();
+    FAPI_TRY(fapi2::putScom(i_core_target,
+                            C_CPPM_CPMMR_CLEAR,
+                            l_data64),
+             "putScom of CPMMR to clear PMM Write Override failed");
+
+fapi_try_exit:
+    FAPI_INF("< p9_block_wakeup_intr...");
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.H b/src/import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.H
new file mode 100644
index 00000000..f4aaaf44
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.H
@@ -0,0 +1,106 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/pm/p9_block_wakeup_intr.H $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+/// @file  p9_block_wakeup_intr.H
+/// @brief Set/reset the BLOCK_REG_WKUP_SOURCES bit in the PPM
+///         associated with an EX chiplet
+///
+// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com>
+// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP FW Owner: Bilicon Patil <bilpatil@in.ibm.com>
+// *HWP Team: PM
+// *HWP Level: 1
+// *HWP Consumed by: FSP:HS
+///
+///-----------------------------------------------------------------------------
+
+#ifndef _P9_BLKWKUP_H_
+#define _P9_BLKWKUP_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <fapi2.H>
+#include <p9_quad_scom_addresses.H>
+#include <p9_quad_scom_addresses_fld.H>
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+namespace p9pmblockwkup
+{
+
+enum OP_TYPE
+{
+    SET = 0,
+    SET_NOSPWUP = 1,
+    CLEAR = 2
+};
+
+// Used by checking infrasture checking code
+static const uint32_t END_OP = CLEAR;
+
+} // namespace p9pmblockwkup
+
+
+//
+// CPMMR Bit definitions
+const uint32_t      BLOCK_REG_WKUP_EVENTS = 6;
+
+// GPMMR Address mappings (for clarity)
+static const uint64_t C_PPM_GPMMR       = C_PPM_GPMMR_SCOM;
+static const uint64_t C_PPM_GPMMR_CLEAR = C_PPM_GPMMR_SCOM1;
+static const uint64_t C_PPM_GPMMR_OR    = C_PPM_GPMMR_SCOM2;
+
+// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_block_wakeup_intr_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&,
+    const p9pmblockwkup::OP_TYPE);
+
+extern "C"
+{
+
+//------------------------------------------------------------------------------
+// Function prototype
+//------------------------------------------------------------------------------
+
+/// @brief @brief Set/reset the BLOCK_REG_WKUP_SOURCES bit in the PPM
+///         associated with an EX chiplet
+///
+/// @param[in] i_core_target    Core target
+/// @param[in] i_operation      SET, CLEAR
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+
+    fapi2::ReturnCode
+    p9_block_wakeup_intr(
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_core_target,
+        const p9pmblockwkup::OP_TYPE i_operation);
+
+} // extern "C"
+
+#endif // _P9_BLKWKUP_H_
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm.H
new file mode 100644
index 00000000..d14c021a
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm.H
@@ -0,0 +1,102 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm.H $                   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_pm.H
+/// @brief Common header for Power Manangement procedures
+///
+
+// *HWP HWP Owner       : Amit Kumar <akumar3@us.ibm.com>
+// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP FW Owner        : Bilicon Patil <bilpatil@in.ibm.com>
+// *HWP Team            : PM
+// *HWP Level           : 2
+// *HWP Consumed by     : HS
+
+#ifndef _P9_PM_H_
+#define _P9_PM_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Macro Defintions
+//------------------------------------------------------------------------------
+
+// Create a multi-bit mask of @a n bits starting at bit @a b
+#ifndef BITS
+    #define BITS(b, n) ((0xffffffffffffffffull << (64 - (n))) >> (b))
+#endif
+
+// Create a single bit mask at bit @a b
+#ifndef BIT
+    #define BIT(b) BITS((b), 1)
+#endif
+
+extern const char* p9_PM_FLOW_MODE_NAME[];
+
+#define PM_FLOW_MODE_NAME   \
+    {                           \
+        "PM_RESET",             \
+        "PM_INIT",              \
+        "PM_SETUP",             \
+        "PM_SETUP_PIB",         \
+        "PM_SETUP_ALL",         \
+        "PM_RESET_SOFT",        \
+        "PM_INIT_SOFT",         \
+        "PM_INIT_SPECIAL"       \
+    }
+
+#define PM_MODE_NAME_VAR p9_PM_FLOW_MODE_NAME[] = PM_FLOW_MODE_NAME
+
+#define PM_MODE_NAME(_mi_mode)(         \
+                                        p9_PM_FLOW_MODE_NAME[_mi_mode-1]    \
+                              )
+
+
+
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+namespace p9pm
+{
+
+enum PM_FLOW_MODE
+{
+    PM_RESET        = 0x1,
+    PM_INIT         = 0x2,
+    PM_SETUP        = 0x3,
+    PM_SETUP_PIB    = 0x4,
+    PM_SETUP_ALL    = 0x5,
+    PM_RESET_SOFT   = 0x6,
+    PM_INIT_SOFT    = 0x7,
+    PM_INIT_SPECIAL = 0x8,
+};
+
+} // end of namespace p9pm
+
+
+#endif // _P9_PM_H_
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C
new file mode 100644
index 00000000..c88407cd
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C
@@ -0,0 +1,237 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.C $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file p9_pm_ocb_indir_access.C
+/// @brief Performs the data transfer to/from an OCB indirect channel
+
+// *HWP HWP Owner       : Amit Kumar <akumar3@us.ibm.com>
+// *HWP HWP Backup Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP FW Owner        : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team            : PM
+// *HWP Level           : 2
+// *HWP Consumed by     : FSP:HS
+
+///
+/// High-level procedure flow:
+/// @verbatim
+///     1) Check if the channel for access is valid.
+///     2) For the PUT operation, the data from the buffer will be written
+///        into the OCB Data register in blocks of 64bits;
+///        from where eventually the data will be written to SRAM.
+///     3) For GET operation, the data read from the SRAM will be retrieved from
+///        the DATA register and written into the buffer in blocks of 64bits.
+/// @endverbatim
+///
+
+// ----------------------------------------------------------------------
+// Includes
+// ----------------------------------------------------------------------
+#include <p9_pm_ocb_indir_access.H>
+
+// ----------------------------------------------------------------------
+// Constant definitions
+// ----------------------------------------------------------------------
+
+enum
+{
+    OCB_FULL_POLL_MAX = 4,
+    OCB_FULL_POLL_DELAY_HDW = 0,
+    OCB_FULL_POLL_DELAY_SIM = 0
+};
+
+fapi2::ReturnCode p9_pm_ocb_indir_access(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const p9ocb::PM_OCB_CHAN_NUM  i_ocb_chan,
+    const p9ocb::PM_OCB_ACCESS_OP i_ocb_op,
+    const uint32_t                i_ocb_req_length,
+    const bool                    i_oci_address_valid,
+    const uint32_t                i_oci_address,
+    uint32_t&                     o_ocb_act_length,
+    uint64_t*                     io_ocb_buffer)
+{
+    FAPI_IMP("Enter p9_pm_ocb_indir_access...");
+    FAPI_DBG("Channel : %d, Operation : %d, No.of 8B Blocks of Data: %d",
+             i_ocb_chan, i_ocb_op, i_ocb_req_length);
+
+    uint64_t l_OCBAR_address   = 0;
+    uint64_t l_OCBDR_address   = 0;
+    uint64_t l_OCBCSR_address  = 0;
+    uint64_t l_OCBSHCS_address = 0;
+    o_ocb_act_length = 0;
+
+    FAPI_DBG("Checking channel validity");
+
+    switch ( i_ocb_chan )
+    {
+        case p9ocb::OCB_CHAN0:
+            l_OCBAR_address   = PU_OCB_PIB_OCBAR0;
+            l_OCBDR_address   = PU_OCB_PIB_OCBDR0;
+            l_OCBCSR_address  = PU_OCB_PIB_OCBCSR0_RO;
+            l_OCBSHCS_address = PU_OCB_OCI_OCBSHCS0_SCOM;
+            break;
+
+        case p9ocb::OCB_CHAN1:
+            l_OCBAR_address   = PU_OCB_PIB_OCBAR1;
+            l_OCBDR_address   = PU_OCB_PIB_OCBDR1;
+            l_OCBCSR_address  = PU_OCB_PIB_OCBCSR1_RO;
+            l_OCBSHCS_address = PU_OCB_OCI_OCBSHCS1_SCOM;
+            break;
+
+        case p9ocb::OCB_CHAN2:
+            l_OCBAR_address   = PU_OCB_PIB_OCBAR2;
+            l_OCBDR_address   = PU_OCB_PIB_OCBDR2;
+            l_OCBCSR_address  = PU_OCB_PIB_OCBCSR2_RO;
+            l_OCBSHCS_address = PU_OCB_OCI_OCBSHCS2_SCOM;
+            break;
+
+        case p9ocb::OCB_CHAN3:
+            l_OCBAR_address   = PU_OCB_PIB_OCBAR3;
+            l_OCBDR_address   = PU_OCB_PIB_OCBDR3;
+            l_OCBCSR_address  = PU_OCB_PIB_OCBCSR3_RO;
+            l_OCBSHCS_address = PU_OCB_OCI_OCBSHCS3_SCOM;
+            break;
+    }
+
+    // Verify if a valid valid address provided
+    // If the address is provided
+    //     Use it for the Get / Put operation
+    //     The following cases apply:
+    //     Circular      : OCBAR is irrelevant; write it anyway
+    //     Linear        : OCBAR will set the accessed location
+    //     Linear Stream : OCBAR will establish the address from which
+    //                     auto-increment will commence after the first access
+    // Else
+    //     Circular      : OCBAR is irrelevant
+    //     Linear        : OCBAR will continue to access the same location
+    //     Linear Stream : OCBAR will auto-increment
+    if ( i_oci_address_valid )
+    {
+        FAPI_DBG(" OCI Address : 0x%08X", i_oci_address);
+        fapi2::buffer<uint64_t> l_data64;
+        l_data64.insert<0, 32>(i_oci_address);
+
+        FAPI_TRY(fapi2::putScom(i_target, l_OCBAR_address, l_data64));
+    }
+
+    // PUT Operation
+    if ( i_ocb_op == p9ocb::OCB_PUT )
+    {
+        FAPI_INF("OCB access for data write operation");
+        FAPI_ASSERT(io_ocb_buffer != NULL,
+                    fapi2::PM_OCB_PUT_NO_DATA_ERROR(),
+                    "No data provided for PUT operation");
+
+        fapi2::buffer<uint64_t> l_data64;
+        FAPI_TRY(fapi2::getScom(i_target, l_OCBCSR_address, l_data64));
+
+        // The following check for circular mode is an additional check
+        // performed to ensure a valid data access.
+        if (l_data64.getBit<4>() && l_data64.getBit<5>())
+        {
+            FAPI_DBG("Circular mode detected.");
+            // Check if push queue is enabled. If not, let the store occur
+            // anyway to let the PIB error response return occur. (that is
+            // what will happen if this checking code were not here)
+            FAPI_TRY(fapi2::getScom(i_target, l_OCBSHCS_address, l_data64));
+
+            if (l_data64.getBit<31>())
+            {
+                FAPI_DBG("Poll for a non-full condition to a push queue to "
+                         "avoid data corruption problem");
+                bool l_push_ok_flag = false;
+                uint8_t l_counter = 0;
+
+                do
+                {
+                    // If the OCB_OCI_OCBSHCS0_PUSH_FULL bit (bit 0) is clear,
+                    // proceed. Otherwise, poll
+                    if (!l_data64.getBit<0>())
+                    {
+                        l_push_ok_flag = true;
+                        FAPI_DBG("Push queue not full. Proceeding");
+                        break;
+                    }
+
+                    // Delay, before next polling.
+                    fapi2::delay(OCB_FULL_POLL_DELAY_HDW,
+                                 OCB_FULL_POLL_DELAY_SIM);
+
+                    FAPI_TRY(fapi2::getScom(i_target,
+                                            l_OCBSHCS_address,
+                                            l_data64));
+                    l_counter++;
+                }
+                while (l_counter < OCB_FULL_POLL_MAX);
+
+                FAPI_ASSERT((true == l_push_ok_flag),
+                            fapi2::PM_OCB_PUT_DATA_POLL_NOT_FULL_ERROR().
+                            set_PUSHQ_STATE(l_data64),
+                            "Polling timeout waiting on push non-full");
+            }
+        }
+
+        // Walk the input buffer (io_ocb_buffer) 8B (64bits) at a time to write
+        // the channel data register
+        for(uint32_t l_index = 0; l_index < i_ocb_req_length; l_index++)
+        {
+            l_data64.insertFromRight(io_ocb_buffer[l_index], 0, 64);
+            FAPI_TRY(fapi2::putScom(i_target, l_OCBDR_address, l_data64),
+                     "ERROR:Failed to complete write to channel data register");
+            o_ocb_act_length++;
+            FAPI_DBG("data(64 bits): 0x%016lX written to channel data register",
+                     io_ocb_buffer[l_index]);
+        }
+
+        FAPI_DBG("%d blocks(64bits each) of data put", o_ocb_act_length);
+    }
+    // GET Operation
+    else if( i_ocb_op == p9ocb::OCB_GET )
+    {
+        FAPI_INF("OCB access for data read operation");
+
+        fapi2::buffer<uint64_t> l_data64;
+        uint64_t l_data = 0;
+
+        for (uint32_t l_loopCount = 0; l_loopCount < i_ocb_req_length;
+             l_loopCount++)
+        {
+            FAPI_TRY(fapi2::getScom(i_target, l_OCBDR_address, l_data64),
+                     "ERROR: Failed to read data from channel %d", i_ocb_chan);
+            l_data64.extract(l_data, 0, 64);
+            io_ocb_buffer[l_loopCount] = l_data;
+            o_ocb_act_length++;
+            FAPI_DBG("data(64 bits): 0x%016lX read from channel data register",
+                     io_ocb_buffer[l_loopCount]);
+        }
+
+        FAPI_DBG("%d blocks(64bits each) of data retrieved",
+                 o_ocb_act_length);
+    }
+
+    FAPI_IMP("Exit p9_pm_ocb_indir_access...");
+
+fapi_try_exit:
+    return fapi2::current_err;
+
+}
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.H
new file mode 100644
index 00000000..e5b548fb
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.H
@@ -0,0 +1,114 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_access.H $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_pm_ocb_indir_access.H
+/// @brief Access procedure to the OCC OCB indirect channels
+///
+
+// *HWP HWP Owner       : Amit Kumar <akumar3@us.ibm.com>
+// *HWP HWP Backup Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP FW Owner        : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team            : PM
+// *HWP Level           : 2
+// *HWP Consumed by     : FSP:HS
+
+#ifndef _P9_PM_OCB_INDIR_ACCESS_H_
+#define _P9_PM_OCB_INDIR_ACCESS_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <fapi2.H>
+#include <p9_pm.H>
+#include <p9_pm_ocb_init.H>
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+namespace p9ocb
+{
+enum PM_OCB_ACCESS_OP
+{
+    OCB_GET = 0x1,
+    OCB_PUT = 0x2
+};
+}
+
+// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_pm_ocb_indir_access_FP_t)
+(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
+ const p9ocb::PM_OCB_CHAN_NUM,
+ const p9ocb::PM_OCB_ACCESS_OP,
+ const uint32_t,
+ const bool,
+ const uint32_t,
+ uint32_t&,
+ uint64_t*);
+
+//------------------------------------------------------------------------------
+// Function prototype
+//------------------------------------------------------------------------------
+
+extern "C"
+{
+
+/// @brief Provides for the abstract access to an OCB indirect channel that has
+/// been configured previously via p9_pm_ocb_indir_setup_[linear/circular]
+/// procedures
+///
+/// @param[in]     &i_target           Chip target
+/// @param[in]     i_ocb_chan          OCB channel number (0, 1, 2, 3)
+/// @param[in]     i_ocb_op            Operation (Get, Put)
+/// @param[in]     i_ocb_req_length    Requested length in the number of 8B
+///                                    elements to be accessed (unit origin)
+///                                    Number of bytes = (i_ocb_req_length) *
+///                                    8B
+/// @param[in]     i_oci_address_valid Indicator that oci_address is to be used
+/// @param[in]     i_oci_address       OCI Address to be used for the operation
+/// @param[out]    &o_ocb_act_length   Address containing the actual length
+///                                    in the number of 8B elements to be
+///                                    accessed (zero origin)
+///                                    Number of bytes = (o_ocb_act_length+1) *
+///                                    8B
+/// @param[in/out] io_ocb_buffer       Pointer to a container of type uint64_t
+///                                    to store the data to be written into or
+///                                    obtained from OCC SRAM
+///
+/// @return FAPI2_RC_SUCCESS on success, else error.
+
+    fapi2::ReturnCode p9_pm_ocb_indir_access(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const p9ocb::PM_OCB_CHAN_NUM  i_ocb_chan,
+        const p9ocb::PM_OCB_ACCESS_OP i_ocb_op,
+        const uint32_t                i_ocb_req_length,
+        const bool                    i_oci_address_valid,
+        const uint32_t                i_oci_address,
+        uint32_t&                     o_ocb_act_length,
+        uint64_t*                     io_ocb_buffer);
+
+} // extern "C"
+
+#endif // _P9_PM_OCB_INDIR_ACCESS_H_
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.C
new file mode 100644
index 00000000..ef7f0138
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.C
@@ -0,0 +1,90 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file  p9_pm_ocb_indir_setup_circular.C
+/// @brief  Configure OCB Channels for Circular Push or Pull Mode
+///
+// *HWP HWP Owner       : Amit Kumar <akumar@us.ibm.com>
+// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP FW Owner        : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team            : PM
+// *HWP Level           : 2
+// *HWP Consumed by     : HS
+
+/// High-level procedure flow:
+/// @verbatim
+///  Setup specified channel to push or pull circular mode by calling
+///  p9_pm_ocb_init
+///
+///  Procedure Prereq:
+///     - System clocks are running
+/// @endverbatim
+///
+
+// ----------------------------------------------------------------------
+// Includes
+// ----------------------------------------------------------------------
+
+#include <p9_pm_ocb_indir_setup_circular.H>
+
+fapi2::ReturnCode p9_pm_ocb_indir_setup_circular(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const p9ocb::PM_OCB_CHAN_NUM i_ocb_chan,
+    const p9ocb::PM_OCB_CHAN_TYPE i_ocb_type,
+    const uint32_t i_ocb_bar,
+    const uint8_t i_ocb_q_len,
+    const p9ocb::PM_OCB_CHAN_OUFLOW i_ocb_flow,
+    const p9ocb::PM_OCB_ITPTYPE i_ocb_itp)
+{
+    FAPI_IMP("p9_pm_ocb_indir_setup_circular Enter");
+    FAPI_DBG("Channel: %d; Mode: %d; OCB BAR: 0x%08X; Queue length: %d;",
+             i_ocb_chan, i_ocb_type, i_ocb_bar, i_ocb_q_len);
+    FAPI_DBG("Flow Notification Mode: %d; Interrupt Behaviour: %d", i_ocb_flow,
+             i_ocb_itp);
+
+    fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS;
+    FAPI_EXEC_HWP(l_rc,
+                  p9_pm_ocb_init,
+                  i_target,
+                  p9pm::PM_SETUP_ALL,
+                  i_ocb_chan,
+                  i_ocb_type,
+                  i_ocb_bar,
+                  i_ocb_q_len,
+                  i_ocb_flow,
+                  i_ocb_itp);
+
+    if (l_rc == fapi2::FAPI2_RC_SUCCESS)
+    {
+        FAPI_INF("Circular setup of channel %d successful.", i_ocb_chan);
+    }
+    else
+    {
+        FAPI_ERR("ERROR: Failed to setup channel %d to circular mode.",
+                 i_ocb_chan);
+    }
+
+    FAPI_IMP("p9_pm_ocb_indir_setup_circular Exit");
+    return l_rc;
+}
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.H
new file mode 100644
index 00000000..a366bbd8
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.H
@@ -0,0 +1,73 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_circular.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file  p9_pm_ocb_indir_setup_circular.H
+/// @brief  Configure OCB Channels for Circular Push or Pull Mode
+// *HWP HWP Owner       : Amit Kumar <akumar@us.ibm.com>
+// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP FW Owner        : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team            : PM
+// *HWP Level           : 2
+// *HWP Consumed by     : HS
+
+#ifndef _P9_PM_OCB_INDIR_SETUP_CIRCULAR_H_
+#define _P9_PM_OCB_INDIR_SETUP_CIRCULAR_H_
+
+#include <fapi2.H>
+#include <p9_pm_ocb_init.H>
+
+// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_pm_ocb_indir_setup_circular_FP_t)
+(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
+ const p9ocb::PM_OCB_CHAN_NUM,
+ const p9ocb::PM_OCB_CHAN_TYPE,
+ const uint32_t,
+ const uint8_t,
+ const p9ocb::PM_OCB_CHAN_OUFLOW,
+ const p9ocb::PM_OCB_ITPTYPE);
+
+extern "C"
+{
+
+//------------------------------------------------------------------------------
+// Function prototype
+//------------------------------------------------------------------------------
+/// @brief Configure OCB Channels for Circular Push or Pull Mode
+/// @param[in] i_target Chip Target
+/// @param[in] i_ocb_chan Select channel 0-3 to set up
+/// @param[in] i_ocb_type Circular push;  circular pull
+/// @return FAPI2_RC_SUCCESS on success, error otherwise
+
+    fapi2::ReturnCode p9_pm_ocb_indir_setup_circular(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const p9ocb::PM_OCB_CHAN_NUM i_ocb_chan,
+        const p9ocb::PM_OCB_CHAN_TYPE i_ocb_type,
+        const uint32_t i_ocb_bar,
+        const uint8_t i_ocb_q_len,
+        const p9ocb::PM_OCB_CHAN_OUFLOW i_ocb_flow,
+        const p9ocb::PM_OCB_ITPTYPE i_ocb_itp);
+
+} // extern "C"
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.C
new file mode 100644
index 00000000..292659cb
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.C
@@ -0,0 +1,91 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file p8_ocb_indir_setup_linear.C
+/// @brief  Configure OCB Channel for Linear Streaming or Non-streaming mode
+
+// *HWP HWP Owner       : Amit Kumar <akumar3@us.ibm.com>
+// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP FW Owner        : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team            : PM
+// *HWP Level           : 2
+// *HWP Consumed by     : HS
+
+/// High-level procedure flow:
+/// @verbatim
+///  Setup specified channel to linear streaming or non-streaming mode by
+///  calling proc proc_ocb_init
+///
+///  Procedure Prereq:
+///     - System clocks are running
+/// @endverbatim
+///
+//------------------------------------------------------------------------------
+
+// ----------------------------------------------------------------------
+// Includes
+// ----------------------------------------------------------------------
+
+#include <p9_pm.H>
+#include <p9_pm_ocb_indir_setup_linear.H>
+
+// ----------------------------------------------------------------------
+// Function definitions
+// ----------------------------------------------------------------------
+fapi2::ReturnCode p9_pm_ocb_indir_setup_linear(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const p9ocb::PM_OCB_CHAN_NUM  i_ocb_chan,
+    const p9ocb::PM_OCB_CHAN_TYPE i_ocb_type,
+    const uint32_t      i_ocb_bar)
+{
+    FAPI_IMP("p9_pm_ocb_indir_setup_linear Enter");
+    FAPI_DBG("For channel %d as type %d, OCB Bar 0x%x",
+             i_ocb_chan, i_ocb_type, i_ocb_bar);
+
+    fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS;
+    FAPI_EXEC_HWP(l_rc,
+                  p9_pm_ocb_init,
+                  i_target,
+                  p9pm::PM_SETUP_PIB,
+                  i_ocb_chan,
+                  i_ocb_type,
+                  i_ocb_bar,
+                  0, // ocb_q_len
+                  p9ocb::OCB_Q_OUFLOW_NULL,
+                  p9ocb::OCB_Q_ITPTYPE_NULL);
+
+    if (l_rc == fapi2::FAPI2_RC_SUCCESS)
+    {
+        FAPI_INF("Linear setup of channel %d successful.", i_ocb_chan);
+    }
+    else
+    {
+        FAPI_ERR("ERROR: Failed to setup channel %d to linear mode.",
+                 i_ocb_chan);
+    }
+
+    FAPI_IMP("p9_pm_ocb_indir_setup_linear Exit");
+    return l_rc;
+}
+
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.H
new file mode 100644
index 00000000..27adcc48
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.H
@@ -0,0 +1,68 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_indir_setup_linear.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file p9_pm_ocb_indir_setup_linear.C
+/// @brief  Configure OCB Channel for Linear Streaming or Non-streaming mode
+
+// *HWP HWP Owner       : Amit Kumar <akumar3@us.ibm.com>
+// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP FW Owner        : Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team            : PM
+// *HWP Level           : 2
+// *HWP Consumed by     : HS
+
+#ifndef _P9_PM_OCB_INDIR_SETUP_LINEAR_H_
+#define _P9_PM_OCB_INDIR_SETUP_LINEAR_H_
+
+#include <fapi2.H>
+#include <p9_pm_ocb_init.H>
+
+typedef fapi2::ReturnCode (*p9_pm_ocb_indir_setup_linear_FP_t)
+(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
+ const p9ocb::PM_OCB_CHAN_NUM,
+ const p9ocb::PM_OCB_CHAN_TYPE,
+ const uint32_t);
+
+extern "C"
+{
+
+//------------------------------------------------------------------------------
+// Function prototype
+//------------------------------------------------------------------------------
+/// @brief  Configure OCB Channel for Linear Streaming or Non-streaming mode
+/// @param[in]  i_target   Chip Target
+/// @param[in]  i_ocb_chan select channel 0-3 to set up      (see p8_ocb_init.H)
+/// @param[in]  i_ocb_type linear streaming or non-streaming (see p8_ocb_init.H)
+/// @param[in]  i_ocb_bar  32-bit channel base address (29 bits + "000")
+/// @return FAPI2_RC_SUCCESS on success, else error.
+
+    fapi2::ReturnCode p9_pm_ocb_indir_setup_linear(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const p9ocb::PM_OCB_CHAN_NUM  i_ocb_chan,
+        const p9ocb::PM_OCB_CHAN_TYPE i_ocb_type,
+        const uint32_t      i_ocb_bar);
+
+} // extern "C"
+
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C
new file mode 100644
index 00000000..2ac813d6
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C
@@ -0,0 +1,674 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C $          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_pm_ocb_init.C
+/// @brief Setup and configure OCB channels
+///
+// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com>
+// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team: PM
+// *HWP Level: 2
+// *HWP Consumed by: FSP:HS
+
+///   Add support for linear window mode
+///
+///   High-level procedure flow:
+///
+///   - if mode = PM_INIT
+///   - placeholder - currently do nothing
+///   - if mode = PM_RESET
+///     - reset each register in each OCB channel to its scan0-flush state
+///   - if mode = PM_SETUP_PIB or PM_SETUP_ALL
+///     - process parameters passed to procedure
+///     - Set up channel control/status register based on passed parameters
+///       (OCBCSRn)
+///     - Set Base Address Register
+///       - linear streaming & non-streaming => OCBARn
+///       - push queue                       => OCBSHBRn  (only if PM_SETUP_ALL)
+///       - pull queue                       => OCBSLBRn  (only if PM_SETUP_ALL)
+///     - Set up queue control and status register (only if PM_SETUP_ALL)
+///       - push queue  => OCBSHCSn
+///       - pull queue  => OCBSLCSn
+///
+///   Procedure Prerequisite:
+///   - System clocks are running
+///
+
+//------------------------------------------------------------------------------
+//  Includes
+//------------------------------------------------------------------------------
+
+#include <p9_pm_ocb_init.H>
+
+//------------------------------------------------------------------------------
+// CONSTANTS
+//------------------------------------------------------------------------------
+enum PM_OCB_CONST
+{
+    MAX_OCB_QUE_LEN = 31, // Max length of PULL/PUSH queue
+    INTERRUPT_SRC_MASK_REG = 0xFFFFFFFF, // Mask for interrupt source register
+    MAX_OCB_CHANNELS = 3 // Max no. of OCB channels
+};
+
+// channel register arrrays
+const uint64_t OCBARn[4]       = {PU_OCB_PIB_OCBAR0,
+                                  PU_OCB_PIB_OCBAR1,
+                                  PU_OCB_PIB_OCBAR2,
+                                  PU_OCB_PIB_OCBAR3
+                                 };
+
+const uint64_t OCBCSRn_CLEAR[4]  = {PU_OCB_PIB_OCBCSR0_CLEAR,
+                                    PU_OCB_PIB_OCBCSR1_CLEAR,
+                                    PU_OCB_PIB_OCBCSR2_CLEAR,
+                                    PU_OCB_PIB_OCBCSR3_CLEAR
+                                   };
+
+const uint64_t OCBCSRn_OR[4]   = {PU_OCB_PIB_OCBCSR0_OR,
+                                  PU_OCB_PIB_OCBCSR1_OR,
+                                  PU_OCB_PIB_OCBCSR2_OR,
+                                  PU_OCB_PIB_OCBCSR3_OR
+                                 };
+
+const uint64_t OCBESRn[4]      = {PU_OCB_PIB_OCBESR0,
+                                  PU_OCB_PIB_OCBESR1,
+                                  PU_OCB_PIB_OCBESR2,
+                                  PU_OCB_PIB_OCBESR3
+                                 };
+
+const uint64_t OCBSLBRn[4]     = {PU_OCB_OCI_OCBSLBR0_SCOM,
+                                  PU_OCB_OCI_OCBSLBR1_SCOM,
+                                  PU_OCB_OCI_OCBSLBR2_SCOM,
+                                  PU_OCB_OCI_OCBSLBR3_SCOM
+                                 };
+
+const uint64_t OCBSHBRn[4]     = {PU_OCB_OCI_OCBSHBR0_SCOM,
+                                  PU_OCB_OCI_OCBSHBR1_SCOM,
+                                  PU_OCB_OCI_OCBSHBR2_SCOM,
+                                  PU_OCB_OCI_OCBSHBR3_SCOM
+                                 };
+
+const uint64_t OCBSLCSn[4]     = {PU_OCB_OCI_OCBSLCS0_SCOM,
+                                  PU_OCB_OCI_OCBSLCS1_SCOM,
+                                  PU_OCB_OCI_OCBSLCS2_SCOM,
+                                  PU_OCB_OCI_OCBSLCS3_SCOM
+                                 };
+
+const uint64_t OCBSHCSn[4]     = {PU_OCB_OCI_OCBSHCS0_SCOM,
+                                  PU_OCB_OCI_OCBSHCS1_SCOM,
+                                  PU_OCB_OCI_OCBSHCS2_SCOM,
+                                  PU_OCB_OCI_OCBSHCS3_SCOM
+                                 };
+
+const uint64_t OCBSESn[4]      = {PU_OCB_OCI_OCBSES0_SCOM,
+                                  PU_OCB_OCI_OCBSES1_SCOM,
+                                  PU_OCB_OCI_OCBSES2_SCOM,
+                                  PU_OCB_OCI_OCBSES3_SCOM
+                                 };
+
+const uint64_t OCBLWCRn[4]     = {PU_OCB_OCI_OCBLWCR0_SCOM,
+                                  PU_OCB_OCI_OCBLWCR1_SCOM,
+                                  PU_OCB_OCI_OCBLWCR2_SCOM,
+                                  PU_OCB_OCI_OCBLWCR3_SCOM
+                                 };
+
+const uint64_t OCBLWSBRn[4]    = {PU_OCB_OCI_OCBLWSBR0_SCOM,
+                                  PU_OCB_OCI_OCBLWSBR1_SCOM,
+                                  PU_OCB_OCI_OCBLWSBR2_SCOM,
+                                  PU_OCB_OCI_OCBLWSBR3_SCOM
+                                 };
+
+//------------------------------------------------------------------------------
+//  Function prototypes
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+///
+/// @brief Reset OCB Channels to default state (ie. scan-0 flush state)
+///
+/// @param [in]   i_target          Chip Target
+///
+/// @return FAPI2_RC_SUCCESS on success, else error.
+///
+fapi2::ReturnCode pm_ocb_reset(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
+
+//------------------------------------------------------------------------------
+///
+/// @brief Init specified channel to type specified
+///
+/// @param [in]   i_target         Chip Target
+///
+/// @param [in]   i_ocb_chan       Channel to setup from enum PM_OCB_CHAN_NUM.
+///                                OCB_CHAN0 : OCB  Channel 0
+///                                OCB_CHAN1 : OCB  Channel 1
+///                                OCB_CHAN2 : OCB  Channel 2
+///                                OCB_CHAN3 : OCB  Channel 3
+///
+/// @param [in]   i_ocb_type       Type of channel from PM_OCB_CHAN_TYPE.
+///                                OCB_TYPE_LIN:Linear w/o address increment
+///                                OCB_TYPE_LINSTR:Linear with address increment
+///                                OCB_TYPE_CIRC:Circular mode
+///                                OCB_TYPE_PUSHQ:Circular Push Queue
+///                                OCB_TYPE_PULLQ:Circular Pull Queue
+///
+/// @param [in]   i_ocb_bar        32-bit channel base address(29 bits + "000")
+///
+/// @param [in]   i_ocb_upd_reg    Type of register to init 'PM_OCB_CHAN_REG'
+///                                OCB_UPD_PIB_REG:Update PIB Register
+///                                OCB_UPD_PIB_OCI_REG:Update OCI+PIB Registers
+///
+/// @param [in]   i_ocb_q_len      0-31 length of push or pull queue in
+///                                (queue_length + 1) * 8B
+///
+/// @param [in]   i_ocb_ouflow_en  Channel flow control from PM_OCB_CHAN_OUFLOW
+///                                OCB_Q_OUFLOW_EN:Overflow/Underflow Enable
+///                                OCB_Q_OUFLOW_DIS:Overflow/Underflow Disable
+///
+/// @param [in]   i_ocb_itp_type   Channel interrupt control from PM_OCB_ITPTYPE
+///                                OCB_Q_ITPTYPE_FULL:Interrupt on Full
+///                                OCB_Q_ITPTYPE_NOTFULL:Interrupt on Not Full
+///                                OCB_Q_ITPTYPE_EMPTY:Interrupt on Empty
+///                                OCB_Q_ITPTYPE_NOTEMPTY:Interrupt on Not Empty
+/// @return FAPI2_RC_SUCCESS on success, else error.
+///
+fapi2::ReturnCode pm_ocb_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const p9ocb::PM_OCB_CHAN_NUM    i_ocb_chan,
+    const p9ocb::PM_OCB_CHAN_TYPE   i_ocb_type,
+    const uint32_t                  i_ocb_bar,
+    const p9ocb::PM_OCB_CHAN_REG    i_ocb_upd_reg,
+    const uint8_t                   i_ocb_q_len,
+    const p9ocb::PM_OCB_CHAN_OUFLOW i_ocb_ouflow_en,
+    const p9ocb::PM_OCB_ITPTYPE     i_ocb_itp_type);
+
+//------------------------------------------------------------------------------
+//  Function definitions
+//------------------------------------------------------------------------------
+
+fapi2::ReturnCode p9_pm_ocb_init(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const p9pm::PM_FLOW_MODE      i_mode,
+    const p9ocb::PM_OCB_CHAN_NUM     i_ocb_chan,
+    const p9ocb::PM_OCB_CHAN_TYPE    i_ocb_type,
+    const uint32_t                   i_ocb_bar,
+    const uint8_t                    i_ocb_q_len,
+    const p9ocb::PM_OCB_CHAN_OUFLOW  i_ocb_ouflow_en,
+    const p9ocb::PM_OCB_ITPTYPE      i_ocb_itp_type)
+{
+    FAPI_IMP("p9_pm_ocb_init Enter");
+
+    // -------------------------------------------------------------------------
+    // INIT mode: Placeholder; NOOP at present
+    // -------------------------------------------------------------------------
+    if (i_mode == p9pm::PM_INIT)
+    {
+        FAPI_DBG(" Channel initialization is a no-op.");
+    }
+    // -------------------------------------------------------------------------
+    // RESET mode: Change the OCB channel registers to scan-0 flush state
+    // -------------------------------------------------------------------------
+    else if (i_mode == p9pm::PM_RESET)
+    {
+        FAPI_INF(" *** Resetting OCB Indirect Channels 0-3");
+        FAPI_TRY(pm_ocb_reset(i_target), "ERROR: OCB Reset failed.");
+    }
+    // -------------------------------------------------------------------------
+    // SETUP mode: Perform user setup of an indirect channel
+    // -------------------------------------------------------------------------
+    else if (i_mode == p9pm::PM_SETUP_ALL || i_mode == p9pm::PM_SETUP_PIB)
+    {
+        FAPI_INF("*** Setup OCB Indirect Channel %d ", i_ocb_chan);
+        p9ocb::PM_OCB_CHAN_REG l_upd_reg = p9ocb::OCB_UPD_PIB_REG;
+
+        if (i_mode == p9pm::PM_SETUP_ALL)
+        {
+            l_upd_reg = p9ocb::OCB_UPD_PIB_OCI_REG;
+        }
+
+        FAPI_TRY(pm_ocb_setup(i_target, i_ocb_chan, i_ocb_type, i_ocb_bar,
+                              l_upd_reg, i_ocb_q_len, i_ocb_ouflow_en,
+                              i_ocb_itp_type),
+                 "ERROR: OCB Setup failed.");
+    }
+    // Invalid Mode
+    else
+    {
+        FAPI_ASSERT(false, fapi2::PM_OCBINIT_BAD_MODE().set_BADMODE(i_mode),
+                    "ERROR; Unknown mode passed to proc_ocb_init. Mode %x",
+                    i_mode);
+    }
+
+fapi_try_exit:
+    FAPI_IMP("p9_pm_ocb_init EXIT");
+    return fapi2::current_err;
+}
+
+
+fapi2::ReturnCode pm_ocb_setup(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const p9ocb::PM_OCB_CHAN_NUM    i_ocb_chan,
+    const p9ocb::PM_OCB_CHAN_TYPE   i_ocb_type,
+    const uint32_t                  i_ocb_bar,
+    const p9ocb::PM_OCB_CHAN_REG    i_ocb_upd_reg,
+    const uint8_t                   i_ocb_q_len,
+    const p9ocb::PM_OCB_CHAN_OUFLOW i_ocb_ouflow_en,
+    const p9ocb::PM_OCB_ITPTYPE     i_ocb_itp_type)
+{
+    FAPI_IMP("pm_ocb_setup Enter");
+
+    uint32_t l_ocbase = 0x0;
+    fapi2::buffer<uint64_t> l_mask_or(0);
+    fapi2::buffer<uint64_t> l_mask_clear(0);
+    fapi2::buffer<uint64_t> l_data64;
+
+    // Verify input queue length is valid
+    if ((i_ocb_type == p9ocb::OCB_TYPE_PUSHQ) ||
+        (i_ocb_type == p9ocb::OCB_TYPE_PULLQ))
+    {
+        // check queue_len
+        if (i_ocb_q_len > MAX_OCB_QUE_LEN)
+        {
+            FAPI_ASSERT(
+                false,
+                fapi2::PM_OCBINIT_BAD_Q_LENGTH_PARM().
+                set_BADQLENGTH(i_ocb_q_len),
+                "ERROR: Bad Queue Length Passed to Procedure => %d",
+                i_ocb_q_len);
+        }
+    }
+
+    // -------------------------------------------------------------------------
+    // Init Status and Control Register (OCBCSRn, OCBCSRn_CLEAR, OCBCSRn_OR)
+    //    bit 2 => pull_read_underflow_en (0=disabled 1=enabled)
+    //    bit 3 => push_write_overflow_en (0=disabled 1=enabled)
+    //    bit 4 => ocb_stream_mode        (0=disabled 1=enabled)
+    //    bit 5 => ocb_stream_type        (0=linear   1=circular)
+    // -------------------------------------------------------------------------
+
+    if (i_ocb_type == p9ocb::OCB_TYPE_LIN) // linear non-streaming
+    {
+        l_mask_clear.setBit<4, 2>();
+    }
+    else if (i_ocb_type == p9ocb::OCB_TYPE_LINSTR) // linear streaming
+    {
+        l_mask_or.setBit<4>();
+        l_mask_clear.setBit<5>();
+    }
+    else if (i_ocb_type == p9ocb::OCB_TYPE_CIRC) // circular
+    {
+        l_mask_or.setBit<4, 2>();
+    }
+    else if (i_ocb_type == p9ocb::OCB_TYPE_PUSHQ) // push queue
+    {
+        l_mask_or.setBit<4, 2>();
+
+        if (i_ocb_ouflow_en == p9ocb::OCB_Q_OUFLOW_EN)
+        {
+            l_mask_or.setBit<3>();
+        }
+        else if (i_ocb_ouflow_en == p9ocb::OCB_Q_OUFLOW_DIS)
+        {
+            l_mask_clear.setBit<3>();
+        }
+    }
+    else if (i_ocb_type == p9ocb::OCB_TYPE_PULLQ) // pull queue
+    {
+        l_mask_or.setBit<4, 2>();
+
+        if (i_ocb_ouflow_en == p9ocb::OCB_Q_OUFLOW_EN)
+        {
+            l_mask_or.setBit<2>();
+        }
+        else if (i_ocb_ouflow_en == p9ocb::OCB_Q_OUFLOW_DIS)
+        {
+            l_mask_clear.setBit<2>();
+        }
+    }
+
+    FAPI_DBG("Writing to Channel %d Register : OCB Channel Status & Control",
+             i_ocb_chan);
+
+    // write using OR mask
+    FAPI_TRY(fapi2::putScom(i_target, OCBCSRn_OR[i_ocb_chan], l_mask_or),
+             "ERROR: Unexpected error encountered in write to OCB Channel "
+             "Status & Control using OR mask");
+    // write using AND mask
+    FAPI_TRY(fapi2::putScom(i_target, OCBCSRn_CLEAR[i_ocb_chan], l_mask_clear),
+             "ERROR: Unexpected error encountered in write to OCB Channel "
+             "Status & Control using and mask");
+
+    //--------------------------------------------------------------------------
+    // set address base register for linear, pull queue or push queue
+    //--------------------------------------------------------------------------
+    //don't update bar if type null or circular
+    if (!(i_ocb_type == p9ocb::OCB_TYPE_NULL ||
+          i_ocb_type == p9ocb::OCB_TYPE_CIRC))
+    {
+        // BAR for linear (streaming / non-streaming)
+        if ((i_ocb_type == p9ocb::OCB_TYPE_LIN) ||
+            (i_ocb_type == p9ocb::OCB_TYPE_LINSTR))
+        {
+            l_ocbase = OCBARn[i_ocb_chan];
+        }
+        // BAR for push queue
+        else if (i_ocb_type == p9ocb::OCB_TYPE_PUSHQ)
+        {
+            l_ocbase = OCBSHBRn[i_ocb_chan];
+        }
+        // BAR for pull queue
+        else
+        {
+            l_ocbase = OCBSLBRn[i_ocb_chan];
+        }
+
+        l_data64.flush<0>().insertFromRight<0, 32>(i_ocb_bar);
+
+        FAPI_DBG("Writing to Channel %d Register : OCB Channel Base Address",
+                 i_ocb_chan);
+
+        FAPI_TRY(fapi2::putScom(i_target, l_ocbase, l_data64),
+                 "ERROR: Unexpected encountered in write to OCB Channel "
+                 "Base Address");
+
+    }
+
+    // -------------------------------------------------------------------------
+    // set up push queue control register
+    //    bits 4:5  => push interrupt action
+    //                   00=full
+    //                   01=not full
+    //                   10=empty
+    //                   11=not empty
+    //    bits 6:10 => push queue length
+    //    bit  31   => push queue enable
+    // -------------------------------------------------------------------------
+    if ((i_ocb_type == p9ocb::OCB_TYPE_PUSHQ) &&
+        (i_ocb_upd_reg == p9ocb::OCB_UPD_PIB_OCI_REG))
+    {
+        l_data64.flush<0>().insertFromRight<6, 5>(i_ocb_q_len);
+        l_data64.insertFromRight<4, 2>(i_ocb_itp_type);
+        l_data64.setBit<31>();
+
+        FAPI_DBG("Writing to Channel %d Register : OCB Channel Push "
+                 "Control/Status Address", i_ocb_chan);
+        FAPI_TRY(fapi2::putScom(i_target, OCBSHCSn[i_ocb_chan], l_data64),
+                 "ERROR : Unexpected error encountered in write to OCB "
+                 "Channel Push Address");
+    }
+
+    // -------------------------------------------------------------------------
+    // set up pull queue control register
+    //    bits 4:5  => pull interrupt action
+    //                   00=full
+    //                   01=not full
+    //                   10=empty
+    //                   11=not empty
+    //    bits 6:10 => pull queue length
+    //    bit  31   => pull queue enable
+    // -------------------------------------------------------------------------
+    if ((i_ocb_type == p9ocb::OCB_TYPE_PULLQ) &&
+        (i_ocb_upd_reg == p9ocb::OCB_UPD_PIB_OCI_REG))
+    {
+        l_data64.flush<0>().insertFromRight<6, 5>(i_ocb_q_len);
+        l_data64.insertFromRight<4, 2>(i_ocb_itp_type);
+        l_data64.setBit<31>();
+
+        FAPI_DBG("Writing to Channel %d ,"
+                 "Register : OCB Channel Pull Control/Status Address",
+                 i_ocb_chan);
+        FAPI_TRY(fapi2::putScom(i_target, OCBSLCSn[i_ocb_chan], l_data64),
+                 "ERROR : Unexpected error encountered in write to OCB "
+                 "Channel Pull Address");
+    }
+
+    // -------------------------------------------------------------------------
+    // Print Channel Configuration Info
+    // -------------------------------------------------------------------------
+    FAPI_IMP("-----------------------------------------------------");
+    FAPI_IMP("OCB Channel Configuration                            ");
+    FAPI_IMP("-----------------------------------------------------");
+    FAPI_IMP("  channel number             => %d ", i_ocb_chan);
+    FAPI_IMP("  channel type               => %d ", i_ocb_type);
+
+    if ((i_ocb_type == p9ocb::OCB_TYPE_PUSHQ) ||
+        (i_ocb_type == p9ocb::OCB_TYPE_PULLQ))
+    {
+        FAPI_IMP("  queue length               => %d ", i_ocb_q_len);
+        FAPI_IMP("  interrupt type             => %d ", i_ocb_itp_type);
+
+        if (i_ocb_type == p9ocb::OCB_TYPE_PUSHQ)
+        {
+            FAPI_IMP("  push write overflow enable => %d ", i_ocb_ouflow_en);
+        }
+        else
+        {
+            FAPI_IMP("  pull write underflow enable => %d ", i_ocb_ouflow_en);
+        }
+    }
+
+    FAPI_IMP("  channel base address       => 0x%08X ", i_ocb_bar);
+    FAPI_IMP("-----------------------------------------------------");
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+
+fapi2::ReturnCode pm_ocb_reset(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
+{
+    FAPI_IMP("p9_pm_ocb_reset Enter");
+    fapi2::buffer<uint64_t> l_buf64;
+
+    // vector of reset channels
+    std::vector<uint8_t> v_reset_chan;
+    v_reset_chan.push_back(1);
+
+    // -------------------------------------------------------------------------
+    // Loop over PIB Registers
+    // -------------------------------------------------------------------------
+    for (auto chan : v_reset_chan)
+    {
+        fapi2::buffer<uint64_t> l_data64;
+        // Clear out OCB Channel BAR registers
+        FAPI_TRY(fapi2::putScom(i_target, OCBARn[chan], 0),
+                 "**** ERROR : Unexpected error encountered in write to OCB "
+                 "Channel %d BAR Register", chan);
+
+        // Clear out OCB Channel control and status registers
+        l_data64.flush<1>();
+        FAPI_TRY(fapi2::putScom(i_target, OCBCSRn_CLEAR[chan], l_data64),
+                 "**** ERROR : Unexpected error encountered in write to OCB "
+                 "Channel %d Control & Status Register Clear", chan);
+
+        // Put channels in Circular mode
+        //  - set bits 4,5 (circular mode) using OR
+        l_data64.flush<0>().setBit<4>().setBit<5>();
+        FAPI_TRY(fapi2::putScom(i_target, OCBCSRn_OR[chan], l_data64),
+                 "**** ERROR : Unexpected error encountered in write to OCB "
+                 "Channel %d Control & Status OR Register Set", chan);
+
+        // Clear out OCB Channel Error Status registers
+        FAPI_TRY(fapi2::putScom(i_target, OCBESRn[chan], 0),
+                 "**** ERROR : Unexpected error encountered in write to OCB "
+                 "Channel %d Error Status Register", chan);
+    }
+
+    // -------------------------------------------------------------------------
+    // Loop over OCI Registers
+    // -------------------------------------------------------------------------
+    for (auto chan : v_reset_chan)
+    {
+        fapi2::buffer<uint64_t> l_data64;
+        // Clear out Pull Base
+        FAPI_TRY(fapi2::putScom(i_target, OCBSLBRn[chan], 0),
+                 "**** ERROR : Unexpected error encountered in write to OCB "
+                 "Channel %d Pull Base Register", chan);
+
+        // Clear out Push Base
+        FAPI_TRY(fapi2::putScom(i_target, OCBSHBRn[chan], 0),
+                 "**** ERROR : Unexpected error encountered in write to OCB "
+                 "Channel %d Push Base Register", chan);
+
+        // Clear out Pull Control & Status
+        FAPI_TRY(fapi2::putScom(i_target, OCBSLCSn[chan], 0),
+                 "**** ERROR : Unexpected error encountered in write to OCB "
+                 "Channel %d Pull Control & Status Register", chan);
+
+        // Clear out Push Control & Status
+        FAPI_TRY(fapi2::putScom(i_target, OCBSHCSn[chan], 0),
+                 "**** ERROR : Unexpected error encountered in write to OCB "
+                 "Channel %d Push Control & Status Register", chan);
+
+        // Clear out Stream Error Status
+        FAPI_TRY(fapi2::putScom(i_target, OCBSESn[chan], 0),
+                 "**** ERROR : Unexpected error encountered in write to OCB "
+                 "Channel %d Stream Error Status Register", chan);
+
+        // Clear out Linear Window Control
+        FAPI_TRY(fapi2::putScom(i_target, OCBLWCRn[chan], 0),
+                 "**** ERROR : Unexpected error encountered in write to OCB "
+                 "Channel %d Linear Window Control Register", chan);
+
+        // Clear out Linear Window Base
+        //  - set bits 3:9
+        l_data64.setBit<3, 7>();
+        FAPI_TRY(fapi2::putScom(i_target, OCBLWSBRn[chan], l_data64),
+                 "**** ERROR : Unexpected error encountered in write to OCB "
+                 "Channel %d Linear Window Base Register", chan);
+    }
+
+    // Set Interrupt Source Mask Registers 0 & 1
+    //  - keep word1 0's for simics
+    l_buf64.flush<0>().insertFromRight<0, 32>(INTERRUPT_SRC_MASK_REG);
+    FAPI_TRY(fapi2::putScom(i_target,
+                            PU_OCB_OCI_OIMR0_SCOM2,
+                            l_buf64),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt Source Mask Register0 (OIMR0)");
+
+    FAPI_TRY(fapi2::putScom(i_target,
+                            PU_OCB_OCI_OIMR1_SCOM2,
+                            l_buf64),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt Source Mask Register1 (OIMR1)");
+
+    // Clear OCC Interrupt Type Registers 0 & 1
+    FAPI_TRY(fapi2::putScom(i_target,
+                            PU_OCB_OCI_OITR0_SCOM2,
+                            0),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt Type Register0 (OITR0)");
+
+    FAPI_TRY(fapi2::putScom(i_target,
+                            PU_OCB_OCI_OITR1_SCOM2,
+                            0),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt Type Register1 (OITR1)");
+
+    // Clear OCC Interupt Edge/Polarity Registers 0 & 1
+    FAPI_TRY(fapi2::putScom(i_target,
+                            PU_OCB_OCI_OIEPR0_SCOM2,
+                            0),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt Edge Polarity Register0 (OIEPR0)");
+
+    FAPI_TRY(fapi2::putScom(i_target,
+                            PU_OCB_OCI_OIEPR1_SCOM2,
+                            0),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt Edge Polarity Register1 (OIEPR1)");
+
+    // Clear OCC Interrupt Source Registers 0 & 1
+    FAPI_TRY(fapi2::putScom(i_target,
+                            PU_OCB_OCI_OISR0_SCOM2,
+                            0),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt Source Register0 (OISR0)");
+
+    FAPI_TRY(fapi2::putScom(i_target,
+                            PU_OCB_OCI_OISR1_SCOM2,
+                            0),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt Source Register1 (OISR1)");
+
+    // Clear Interrupt Route (A, B, C) Registers 0 & 1
+    FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OIRR0A_SCOM, 0),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt 0 Route A Register (OIRR0A)");
+
+    FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OIRR0B_SCOM, 0),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt 0 Route B Register (OIRR0A)");
+
+    FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OIRR0C_SCOM, 0),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt 0 Route C Register (OIRR0A)");
+
+    FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OIRR1A_SCOM, 0),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt 1 Route A Register (OIRR1A)");
+
+    FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OIRR1B_SCOM, 0),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt 1 Route B Register (OIRR1B)");
+
+    FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OIRR1C_SCOM, 0),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt 1 Route C Register (OIRR1C)");
+
+    // Clear OCC Interrupt Timer Registers 0 & 1
+    //  - need bits 0&1 set to clear register
+    l_buf64.flush<0>().setBit<0, 2>();
+
+    FAPI_TRY(fapi2::putScom(i_target,
+                            PU_OCB_OCI_OTR0_SCOM,
+                            l_buf64),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt Timer0 Register (OTR0)");
+
+    FAPI_TRY(fapi2::putScom(i_target,
+                            PU_OCB_OCI_OTR1_SCOM,
+                            l_buf64),
+             "**** ERROR : Unexpected error encountered in write to OCC "
+             "Interrupt Timer1 Register (OTR1)");
+
+    // Clear PBA Enable Marker Acknowledgement mode to remove collisions
+    // with any accesses to the OCB DCR registers (eg OSTOESR).
+    // This function is only enabled by OCC firmware and is not via
+    // hardware procedures.
+    FAPI_TRY(fapi2::getScom(i_target, PU_PBAMODE_SCOM, l_buf64),
+             "**** ERROR : Failed to fetch PBA mode control status");
+    l_buf64.clearBit<8>();
+    FAPI_TRY(fapi2::putScom(i_target, PU_PBAMODE_SCOM, l_buf64),
+             "**** ERROR : Failed to write PBA mode control");
+
+    // Clear OCC special timeout error status register
+    FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OSTOESR, 0),
+             "**** ERROR : Failed to write OSTESR");
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H
new file mode 100644
index 00000000..1130fcaa
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H
@@ -0,0 +1,164 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.H $          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_pm_ocb_init.H
+/// @brief Setup and configure OCB channels
+///
+// *HWP HWP Owner: Amit Kumar <akumar3@us.ibm.com>
+// *HWP FW Owner: Sangeetha T S <sangeet2@in.ibm.com>
+// *HWP Team: PM
+// *HWP Level: 2
+// *HWP Consumed by: FSP:HS
+
+#ifndef _P9_PM_OCB_INIT_H_
+#define _P9_PM_OCB_INIT_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+
+#include <p9_pm.H>
+#include <fapi2.H>
+#include <p9_misc_scom_addresses.H>
+
+//------------------------------------------------------------------------------
+// Constants definitions
+//------------------------------------------------------------------------------
+namespace p9ocb
+{
+/// @enum PM_OCB_CHAN_NUM
+enum PM_OCB_CHAN_NUM
+{
+    OCB_CHAN0 = 0x00,           ///< OCB  Channel 0
+    OCB_CHAN1 = 0x01,           ///< OCB  Channel 1
+    OCB_CHAN2 = 0x02,           ///< OCB  Channel 2
+    OCB_CHAN3 = 0x03            ///< OCB  Channel 3
+};
+
+/// @enum PM_OCB_CHAN_TYPE
+enum PM_OCB_CHAN_TYPE
+{
+    OCB_TYPE_NULL,              ///< Do nothing
+    OCB_TYPE_LIN,               ///< Linear w/o address incrementation
+    OCB_TYPE_LINSTR,            ///< Linear with address incrementation
+    OCB_TYPE_LINWIN,            ///< Linear window mode
+    OCB_TYPE_CIRC,              ///< Circular mode
+    OCB_TYPE_PUSHQ,             ///< Circular Push Queue
+    OCB_TYPE_PULLQ              ///< Circular Pull Queue
+};
+
+/// @enum PM_OCB_CHAN_REG
+enum PM_OCB_CHAN_REG
+{
+    OCB_UPD_PIB_REG,            ///< Update PIB Register
+    OCB_UPD_PIB_OCI_REG         ///< Update OCI Register
+};
+
+/// @enum PM_OCB_CHAN_OUFLOW
+enum PM_OCB_CHAN_OUFLOW
+{
+    OCB_Q_OUFLOW_NULL,          ///< Do nothing
+    OCB_Q_OUFLOW_EN,            ///< Overflow/Underflow Enable
+    OCB_Q_OUFLOW_DIS            ///< Overflow/Underflow Disable
+};
+
+/// @enum PM_OCB_ITPTYPE
+enum PM_OCB_ITPTYPE
+{
+    OCB_Q_ITPTYPE_NULL,         ///< Overflow/Underflow Disable
+    OCB_Q_ITPTYPE_FULL,         ///< Interrupt on Full
+    OCB_Q_ITPTYPE_NOTFULL,      ///< Interrupt on Not Full
+    OCB_Q_ITPTYPE_EMPTY,        ///< Interrupt on Empty
+    OCB_Q_ITPTYPE_NOTEMPTY      ///< Interrupt on Not Empty
+};
+} // END OF NAMESPACE p9ocb
+
+typedef fapi2::ReturnCode (*p9_pm_ocb_init_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
+    const p9pm::PM_FLOW_MODE,
+    const p9ocb::PM_OCB_CHAN_NUM,
+    const p9ocb::PM_OCB_CHAN_TYPE,
+    const uint32_t,
+    const uint8_t,
+    const p9ocb::PM_OCB_CHAN_OUFLOW,
+    const p9ocb::PM_OCB_ITPTYPE);
+
+extern "C"
+{
+//------------------------------------------------------------------------------
+// Function prototype
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+///
+/// @brief Configure OCB Channels based on mode and parameters passed
+///
+/// @param [in]   i_target         Chip Target
+///
+/// @param [in]   i_mode           Mode of operation from enum PM_FLOW_MODE.
+///                                PM_RESET/PM_INIT/PM_SETUP_ALL
+///
+/// @param [in]   i_ocb_chan       Channel to setup from enum PM_OCB_CHAN_NUM.
+///                                OCB_CHAN0 : OCB  Channel 0
+///                                OCB_CHAN1 : OCB  Channel 1
+///                                OCB_CHAN2 : OCB  Channel 2
+///                                OCB_CHAN3 : OCB  Channel 3
+///
+/// @param [in]   i_ocb_type       Type of channel from PM_OCB_CHAN_TYPE.
+///                                OCB_TYPE_LIN:Linear w/o address increment
+///                                OCB_TYPE_LINSTR:Linear with address increment
+///                                OCB_TYPE_CIRC:Circular mode
+///                                OCB_TYPE_PUSHQ:Circular Push Queue
+///                                OCB_TYPE_PULLQ:Circular Pull Queue
+///
+/// @param [in]   i_ocb_bar        32-bit channel base address(29 bits + "000")
+///
+/// @param [in]   i_ocb_q_len      0-31 length of push or pull queue in
+///                                (queue_length + 1) * 8B
+///
+/// @param [in]   i_ocb_ouflow_en  Channel flow control from PM_OCB_CHAN_OUFLOW
+///                                OCB_Q_OUFLOW_EN:Overflow/Underflow Enable
+///                                OCB_Q_OUFLOW_DIS:Overflow/Underflow Disable
+///
+/// @param [in]   i_ocb_itp_type   Channel interrupt control from PM_OCB_ITPTYPE
+///                                OCB_Q_ITPTYPE_FULL:Interrupt on Full
+///                                OCB_Q_ITPTYPE_NOTFULL:Interrupt on Not Full
+///                                OCB_Q_ITPTYPE_EMPTY:Interrupt on Empty
+///                                OCB_Q_ITPTYPE_NOTEMPTY:Interrupt on Not Empty
+///
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+    fapi2::ReturnCode p9_pm_ocb_init(
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+        const p9pm::PM_FLOW_MODE      i_mode,
+        const p9ocb::PM_OCB_CHAN_NUM     i_ocb_chan,
+        const p9ocb::PM_OCB_CHAN_TYPE    i_ocb_type,
+        const uint32_t                   i_ocb_bar,
+        const uint8_t                    i_ocb_q_len,
+        const p9ocb::PM_OCB_CHAN_OUFLOW  i_ocb_ouflow_en,
+        const p9ocb::PM_OCB_ITPTYPE      i_ocb_itp_type);
+} // extern "C"
+
+#endif // _P9_PM_OCB_INIT_H_
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.C
new file mode 100644
index 00000000..4809d65e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.C
@@ -0,0 +1,148 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_utils.C $             */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_pm_utils.C
+/// @brief Utility functions for PM FAPIs
+///
+
+// *HWP HWP Owner       : Amit Kumar <akumar3@us.ibm.com>
+// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP FW Owner        : Bilicon Patil <bilpatil@in.ibm.com>
+// *HWP Team            : PM
+// *HWP Level           : 1
+// *HWP Consumed by     : HS
+
+// ----------------------------------------------------------------------
+// Includes
+// ----------------------------------------------------------------------
+#include <p9_pm.H>
+#include <p9_pm_utils.H>
+#include <p9_const_common.H>
+
+fapi2::ReturnCode p9_pm_glob_fir_trace(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const char* i_msg)
+{
+    FAPI_INF("p9_pm_glob_fir_trace Enter");
+
+#if 0 // The CONST_UINT64_T definition in P9 const_common.H takes 4 arguments -
+    // CONST_UINT64_T(name, expr, unit, meth). Need to figure out the values
+    // for "unit" and "meth" for the below declarations.
+    CONST_UINT64_T( GLOB_XSTOP_FIR_0x01040000, ULL(0x01040000) );
+    CONST_UINT64_T( GLOB_RECOV_FIR_0x01040001, ULL(0x01040001) );
+    CONST_UINT64_T( TP_LFIR_0x0104000A, ULL(0x0104000A) );
+#endif
+
+    //  Note: i_msg is put on on each record to allow for trace "greps"
+    //  so as to see the "big picture" across when
+
+    uint8_t l_traceEnFlag = false;
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+    fapi2::buffer<uint64_t> l_data64;
+
+#if 0 // Uncomment when attribute ATTR_PM_GLOBAL_FIR_TRACE_EN is ready
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PM_GLOBAL_FIR_TRACE_EN,
+                           FAPI_SYSTEM,
+                           l_traceEnFlag),
+             "FAPI_ATTR_GET for attribute ATTR_PM_GLOBAL_FIR_TRACE_EN");
+#endif
+
+    // Continue if trace is enabled.
+    if (false == l_traceEnFlag)
+    {
+        goto fapi_try_exit;
+    }
+
+    //  ******************************************************************
+    //  Check for xstops and recoverables and put in the trace
+    //  ******************************************************************
+    {
+#if 0 // Uncomment when the scom address is defined
+        FAPI_TRY(fapi2::getScom(i_target,
+                                READ_GLOBAL_XSTOP_FIR_0x570F001B,
+                                l_data64));
+#endif
+
+        if(l_data64)
+        {
+            FAPI_INF("Xstop is **ACTIVE** %s", i_msg);
+        }
+    }
+
+    {
+#if 0 // Uncomment when the scom address is defined
+        FAPI_TRY(fapi2::getScom(i_target,
+                                READ_GLOBAL_RECOV_FIR_0x570F001C,
+                                l_data64));
+#endif
+
+        if(l_data64)
+        {
+            FAPI_INF("Recoverable attention is **ACTIVE** %s", i_msg);
+        }
+    }
+
+    {
+#if 0 // Uncomment when the scom address is defined
+        FAPI_TRY(fapi2::getScom(i_target,
+                                GLOB_XSTOP_FIR_0x01040000,
+                                l_data64));
+#endif
+
+        if(l_data64)
+        {
+            FAPI_INF("Glob Xstop FIR is **ACTIVE** %s", i_msg);
+        }
+    }
+
+    {
+#if 0 // Uncomment when the scom address is defined
+        FAPI_TRY(fapi2::getScom(i_target,
+                                GLOB_RECOV_FIR_0x01040001,
+                                l_data64));
+#endif
+
+        if(l_data64)
+        {
+            FAPI_INF("Glob Recov FIR is **ACTIVE** %s", i_msg);
+        }
+    }
+
+    {
+#if 0 // Uncomment when the scom address is defined
+        FAPI_TRY(fapi2::getScom(i_target,
+                                TP_LFIR_0x0104000A,
+                                l_data64));
+#endif
+
+        if(l_data64)
+        {
+            FAPI_INF("TP LFIR is **ACTIVE** %s", i_msg);
+        }
+    }
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.H
new file mode 100644
index 00000000..3524991e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_utils.H
@@ -0,0 +1,105 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/hwp/pm/p9_pm_utils.H $             */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file p9_pm_utils.H
+/// @brief Utility functions for PM FAPIs
+///
+
+// *HWP HWP Owner       : Amit Kumar <akumar3@us.ibm.com>
+// *HWP Backup HWP Owner: Greg Still <stillgs@us.ibm.com>
+// *HWP FW Owner        : Bilicon Patil <bilpatil@in.ibm.com>
+// *HWP Team            : PM
+// *HWP Level           : 1
+// *HWP Consumed by     : HS
+
+#ifndef _P9_PM_UTILS_H_
+#define _P9_PM_UTILS_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi2.H>
+
+//------------------------------------------------------------------------------
+// Common macros
+//------------------------------------------------------------------------------
+
+#define SET_FIR_ACTION(b, x, y)  \
+    action_0.writeBit<b>(x); \
+    action_1.writeBit<b>(y);
+
+#define SET_CHECK_STOP(b){SET_FIR_ACTION(b, 0, 0);}
+#define SET_RECOV_ATTN(b){SET_FIR_ACTION(b, 0, 1);}
+#define SET_RECOV_INTR(b){SET_FIR_ACTION(b, 1, 0);}
+#define SET_MALF_ALERT(b){SET_FIR_ACTION(b, 1, 1);}
+#define SET_FIR_MASKED(b){mask.setBit<b>();}
+#define CLEAR_FIR_MASK(b){mask.clearBit<b>()}
+
+
+/**
+ * @brief  helper function to swizzle given input data
+ * @note   swizles bytes to handle endianess issue.
+ */
+#if( __BYTE_ORDER == __BIG_ENDIAN )
+
+// NOP if it is a big endian system
+#define RevLe16(WORD) WORD
+#define RevLe32(WORD) WORD
+#define RevLe64(WORD) WORD
+
+#else
+#define RevLe16(WORD) \
+    ( (((WORD) >> 8) & 0x00FF) | (((WORD) << 8) & 0xFF00) )
+
+#define RevLe32(WORD) \
+    ( (((WORD) >> 24) & 0x000000FF) | (((WORD) >>  8) & 0x0000FF00) | \
+      (((WORD) <<  8) & 0x00FF0000) | (((WORD) << 24) & 0xFF000000) )
+
+#define RevLe64(WORD) \
+    ( (((WORD) >> 56) & 0x00000000000000FF) |  \
+      (((WORD) >> 40) & 0x000000000000FF00)| \
+      (((WORD) >> 24) & 0x0000000000FF0000) |  \
+      (((WORD) >>  8) & 0x00000000FF000000) |  \
+      (((WORD) <<  8) & 0x000000FF00000000) |  \
+      (((WORD) << 24) & 0x0000FF0000000000) | \
+      (((WORD) << 40) & 0x00FF000000000000) |  \
+      (((WORD) << 56) & 0xFF00000000000000) )
+#endif
+
+//------------------------------------------------------------------------------
+// Function prototype
+//------------------------------------------------------------------------------
+
+///
+/// @brief Trace a set of FIRs (Globals and select Locals)
+/// @param[in] i_target Chip target
+/// @param[in] i_msg String to put out in the trace
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode p9_pm_glob_fir_trace(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const char* i_msg);
+
+#endif // _P9_PM_UTILS_H_
diff --git a/src/import/chips/p9/procedures/hwp/pm/pmfiles.mk b/src/import/chips/p9/procedures/hwp/pm/pmfiles.mk
new file mode 100644
index 00000000..e34a62c4
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/pm/pmfiles.mk
@@ -0,0 +1,44 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/hwp/pm/pmfiles.mk $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file pmfiles.mk
+#
+#  @brief mk for including pm object files
+#
+##########################################################################
+# Object Files
+##########################################################################
+
+PM-CPP-SOURCES +=p9_pm_ocb_indir_access.C
+PM-CPP-SOURCES +=p9_pm_ocb_indir_setup_circular.C
+PM-CPP-SOURCES +=p9_pm_ocb_indir_setup_linear.C
+PM-CPP-SOURCES +=p9_pm_ocb_init.C
+PM-CPP-SOURCES +=p9_pm_utils.C
+PM-CPP-SOURCES +=p9_block_wakeup_intr.C
+PM-C-SOURCES =
+PM-S-SOURCES =
+
+PM_OBJECTS += $(PM-CPP-SOURCES:.C=.o)
+PM_OBJECTS += $(PM-C-SOURCES:.c=.o)
+PM_OBJECTS += $(PM-S-SOURCES:.S=.o)
diff --git a/src/import/chips/p9/procedures/ppe/include/std/algorithm b/src/import/chips/p9/procedures/ppe/include/std/algorithm
new file mode 100644
index 00000000..6e96dd96
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/include/std/algorithm
@@ -0,0 +1,762 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/include/std/algorithm $        */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef ALGORITHM
+#define ALGORITHM
+
+#include <iterator>
+#include <util/impl/qsort.H>
+#include <type_traits>
+
+#ifdef __cplusplus
+namespace std
+{
+    /**
+     * Copy a range of elements
+     * @param[in] first InputIterator to the initial position in the source sequence.
+     * @param[in] last  InputIterator to last position + 1 in the source sequence.
+     * @param[in] result OutputIterator to initial position in the destination sequence.
+     * @return an iterator to the last element in the destination range
+     * @note If both ranges overlap in such a way that result points to an elmenent in the source
+     * range then fuction copy_backward should be used.
+     */
+    template <class InputIterator, class OutputIterator>
+    inline OutputIterator
+    copy (InputIterator first, InputIterator last, OutputIterator result )
+    {
+        while(first!=last)
+        {
+            *result = *first;
+            ++result;
+            ++first;
+        }
+        return result;
+    }
+
+    /**
+     * Copy a range of elements backwards
+     * @param[in] first Bidirectional iterator to the initial source position
+     * @param[in] last  Bidirectional iterator to the final source position + 1
+     * @param[in] result Bidirectional iterator to end of the destination sequence + 1.
+     * @return an iterator to the first element in the destination sequence.
+     * @note If both ranges overlap in such a way that result points to an element in the  source
+     * range, the function copy should be used instead.
+     */
+    template <class BidirectionalIterator1, class BidirectionalIterator2>
+    inline BidirectionalIterator2 
+    copy_backward (  BidirectionalIterator1 first,
+                     BidirectionalIterator1 last,
+                     BidirectionalIterator2 result )
+    {
+        while(last!=first)
+        {
+            --result;
+            --last;
+            *result = *last;
+        }
+        return result;
+    }
+
+    /**
+     * Exchange values of two objects
+     * @param[in] a reference to an object to be swaped with b
+     * @param[in] b reference to an object to be swaped with a
+     * @note this function may not be an efficient way to swap large objects.
+     */
+    template <class T> 
+        inline void 
+        swap(T& a, T&b )
+    {
+        T c(a);
+        a=b;
+        b=c;
+    }
+
+    /**
+     * Fill a range with value
+     * @param[in] first ForwardIterator to the first position in the source range.
+     * @param[in] last  ForwardIterator to the last position +1 in the source range.
+     * @param[in] value reference to the object used to fill the sequence.
+     */
+    template < class ForwardIterator, class T >
+    inline void
+    fill (ForwardIterator first, ForwardIterator last, const T& value )
+    {
+        while (first != last)
+        {
+            *first = value;
+            ++first;
+        }
+    }
+
+    /**
+     * Fill a sequence with value
+     * @param[in] first OutputIterator to the first position in the sequence.
+     * @param[in] n number of elements in the sequence
+     * @param[in] value reference to the value used to fill the sequence.
+     */
+    template < class OutputIterator, class Size, class T >
+    inline void
+    fill_n( OutputIterator first, Size n, const T& value )
+    {
+        for(; n>0; --n)
+        {
+            *first = value;
+            ++first;
+        }
+    }
+
+    /**
+     * Fill a sequence with a generated value
+     * @param[in] first OutputIterator to the first position in the sequence.
+     * @param[in] n number of elements in the sequence
+     * @param[in] gen functor to create values used to fill the sequence.
+     */
+    template <typename OutputIterator, typename Size, typename Generator>
+    OutputIterator generate_n(OutputIterator first, Size n, Generator gen)
+    {
+        for(; n>0; --n)
+        {
+            *first = gen();
+            ++first;
+        }
+
+        return first;
+    }
+
+    /**
+     * Return the lesser of two arguments
+     * @param[in] a object reference
+     * @param[in] b object reference
+     * @return reference to te lesser object
+     */
+    template <class T>
+    inline const T& 
+    min(const T& a, const T& b)
+    {
+        if( b < a) return b;
+        return a;
+    }
+
+    /**
+     * Return the greater of two arguments
+     * @param[in] a object reference
+     * @param[in] b object reference
+     * @return reference to te greater object
+     */    
+    template <class T>
+    inline const T&
+    max(const T& a, const T& b)
+    {
+        if(a < b) return b;
+        return a;
+    }
+
+    /**
+     * Find the location of an element within a range.
+     * @param[in] first InputIterator to the first position in the range.
+     * @param[in] last  InputIterator to the last position in the range.
+     * @param[in] value Value to use for comparison.
+     *
+     * Returns the first iterator i in the range [first,last) such that
+     *     (*i == value) or else last if no element is found.
+     *
+     * @return An iterator in the range [first,last].  last implies that no
+     *         matching element was found.
+     */
+    template <typename InputIterator, typename EqualityComparable>
+    inline InputIterator
+    find(InputIterator first, InputIterator last,
+         const EqualityComparable& value)
+    {
+        while(first != last)
+        {
+            if ((*first) == value)
+                return first;
+
+            ++first;
+        }
+
+        return last;
+    }
+
+    /**
+     * Find the location of an element within a range.
+     * @param[in] first InputIterator to the first position in the range.
+     * @param[in] last  InputIterator to the last position in the range.
+     * @param[in] pred  Predicate used to compare equality.
+     *
+     * Returns the first iterator i in the range [first,last) such that
+     *     pred(*i) is true or else last if no element is found.
+     *
+     * @return An iterator in the range [first,last].  last implies that no
+     *         matching element was found.
+     */
+    template <typename InputIterator, typename Predicate>
+    inline InputIterator
+    find_if(InputIterator first, InputIterator last,
+            Predicate pred)
+    {
+        while(first != last)
+        {
+            if (pred(*first))
+                return first;
+
+            ++first;
+        }
+
+        return last;
+    }
+
+    /**
+     * Find the minimum element within a range.
+     * @param[in] first - FwdIterator to the first position in the range.
+     * @param[in] last - FwdIterator to the last position in the range.
+     *
+     * Returns the first element (i) such that (*j) < (*i) is false for all
+     * other iterators.
+     *
+     * The iterator last is returned only when the range contains no elements.
+     *
+     * @return An iterator in [first, last) containing the minimum element.
+     *
+     */
+    template <typename FwdIterator>
+    inline FwdIterator min_element(FwdIterator first, FwdIterator last)
+    {
+        if (first == last) return last;
+        FwdIterator e = first++;
+        while(first != last)
+        {
+            if ((*first) < (*e)) 
+            {
+                e = first;
+            }
+            ++first;
+        }
+        return e;
+    }
+
+    /**
+     * Find the minimum element within a range.
+     * @param[in] first - FwdIterator to the first position in the range.
+     * @param[in] last - FwdIterator to the last position in the range.
+     * @param[in] comp - BinaryPredicate used to perform comparison.
+     *
+     * Returns the first element (i) such that comp(*j,*i) is false for all
+     * other iterators.
+     *
+     * The iterator last is returned only when the range contains no elements.
+     *
+     * @return An iterator in [first, last) containing the minimum element.
+     *
+     */
+    template <typename FwdIterator, typename BinaryPredicate>
+    inline FwdIterator min_element(FwdIterator first, FwdIterator last, 
+                                   BinaryPredicate comp)
+    {
+        if (first == last) return last;
+        FwdIterator e = first++;
+        while(first != last)
+        {
+            if (comp((*first),(*e)))
+            {
+                e = first;
+            }
+            ++first;
+        }
+        return e;
+    }
+
+    /**
+     * Find the maximum element within a range.
+     * @param[in] first - FwdIterator to the first position in the range.
+     * @param[in] last - FwdIterator to the last position in the range.
+     *
+     * Returns the first element (i) such that (*i) < (*j) is false for all
+     * other iterators.
+     *
+     * The iterator last is returned only when the range contains no elements.
+     *
+     * @return An iterator in [first, last) containing the minimum element.
+     *
+     */
+    template <typename FwdIterator>
+    inline FwdIterator max_element(FwdIterator first, FwdIterator last)
+    {
+        if (first == last) return last;
+        FwdIterator e = first++;
+        while(first != last)
+        {
+            if ((*e) < (*first)) 
+            {
+                e = first;
+            }
+            ++first;
+        }
+        return e;
+    }
+
+    /**
+     * Find the maximum element within a range.
+     * @param[in] first - FwdIterator to the first position in the range.
+     * @param[in] last - FwdIterator to the last position in the range.
+     * @param[in] comp - BinaryPredicate used to perform comparison.
+     *
+     * Returns the first element (i) such that comp(*i,*j) is false for all
+     * other iterators.
+     *
+     * The iterator last is returned only when the range contains no elements.
+     *
+     * @return An iterator in [first, last) containing the minimum element.
+     *
+     */
+    template <typename FwdIterator, typename BinaryPredicate>
+    inline FwdIterator max_element(FwdIterator first, FwdIterator last, 
+                                   BinaryPredicate comp)
+    {
+        if (first == last) return last;
+        FwdIterator e = first++;
+        while(first != last)
+        {
+            if (comp((*e),(*first)))
+            {
+                e = first;
+            }
+            ++first;
+        }
+        return e;
+    }
+
+
+    /**
+     * Find the element value in an ordered range [first, last].  Specifically,
+     * it returns the first position where value could be inserted without
+     * violating the ordering.
+     *
+     * @param[in] first ForwardIterator to the first position in the range.
+     * @param[in] last  ForwardIterator to the last position in the range.
+     * @param[in] value Value to use for comparison.
+     */
+
+    template <class ForwardIterator, class LessThanComparable>
+    inline ForwardIterator
+    lower_bound ( ForwardIterator first,
+                  ForwardIterator last,
+                  const LessThanComparable& value )
+    {
+        ForwardIterator it;
+        int num = 0x0;
+        int range = std::distance<ForwardIterator>( first,
+                                                    last );
+
+        while( range > 0 )
+        {
+            it = first;
+            num = range / 2;
+            std::advance( it, num );
+
+            if( (*it) < value )
+            {
+                first = ++it;
+                range = (range - (num+1));
+            }
+            else
+            {
+                range = num;
+            }
+        }
+
+        return first;
+    }
+
+    /**
+     * Find the element value in an ordered range [first, last].  Specifically,
+     * it returns the first position where value could be inserted without
+     * violating the ordering.  This is done using the comparison function
+     * parameter that is passed in.
+     *
+     * @param[in] first ForwardIterator to the first position in the range.
+     * @param[in] last  ForwardIterator to the last position in the range.
+     * @param[in] value Value to use for comparison.
+     * @param[in] comp  Function to do the comparison
+     */
+    template <class ForwardIterator, class T, class StrictWeakOrdering>
+    inline ForwardIterator
+    lower_bound ( ForwardIterator first,
+                  ForwardIterator last,
+                  const T& value,
+                  StrictWeakOrdering comp )
+    {
+        ForwardIterator it;
+        int num = 0x0;
+        int range = std::distance<ForwardIterator>( first,
+                                                    last );
+
+        while( range > 0 )
+        {
+            it = first;
+            num = range / 2;
+            std::advance( it, num );
+
+            if( comp( (*it), value ) )
+            {
+                first = ++it;
+                range = (range - (num+1));
+            }
+            else
+            {
+                range = num;
+            }
+        }
+
+        return first;
+    }
+
+    /**
+     * Apply a functor to each element in a range.
+     *
+     * Applies functor 'f' to each element in [first, last).
+     *
+     * @param[in] first - The beginning of the range.
+     * @param[in] last - The end of the range.
+     * @param[in] f - The functor.
+     *
+     * @return The functor after being having been applied.
+     */
+    template <typename InputIterator, typename UnaryFunction>
+    UnaryFunction for_each(InputIterator first, InputIterator last,
+                           UnaryFunction f)
+    {
+        while(first != last)
+        {
+            f(*first);
+            ++first;
+        }
+        return f;
+    }
+
+    /**
+     * Remove a value from a range.
+     *
+     * Removes all instances matching 'value' in the range [first, last)
+     * and returns an iterator to the end of the new range [first, new_last)
+     * where nothing in the new range has 'value'.
+     *
+     * Remove does not decrease the size of the container.
+     *
+     * @param[in] first - The beginning of the range.
+     * @param[in] last - The end of the range.
+     * @param[in] value - The value to remove.
+     *
+     * @return An iterator 'new_last' from [first, new_last).
+     */
+    template <typename ForwardIterator, typename T>
+    ForwardIterator remove(ForwardIterator first, ForwardIterator last,
+                           const T& value)
+    {
+        // Find first match.
+        first = find(first, last, value);
+
+        if (first == last) // No match found, return un-changed 'last'.
+        {
+            return last;
+        }
+
+        // Match was found.  'new_last' is now the first removed element.
+        ForwardIterator new_last = first;
+        ++first;
+
+        // Iterate through all the others.
+        while(first != last)
+        {
+            // If 'first' is a desired value, we need to copy it and move
+            // 'new_last'.
+            if (!(*first == value))
+            {
+                *new_last = *first;
+                ++new_last;
+            }
+
+            ++first;
+        }
+
+        return new_last;
+
+    }
+
+    /**
+     * Remove a value from a range using a predicate.
+     *
+     * Removes all instances pred(*i) is true in the range [first, last)
+     * and returns an iterator to the end of the new range [first, new_last)
+     * where nothing in the new range has pred(*i) true.
+     *
+     * Remove does not decrease the size of the container.
+     *
+     * @param[in] first - The beginning of the range.
+     * @param[in] last - The end of the range.
+     * @param[in] pred - The predicate to use for comparison.
+     *
+     * @return An iterator 'new_last' from [first, new_last).
+     */
+    template <typename ForwardIterator, typename Predicate>
+    ForwardIterator remove_if(ForwardIterator first, ForwardIterator last,
+                              Predicate pred)
+    {
+        // Find first match.
+        first = find_if(first, last, pred);
+
+        if (first == last) // No match found, return un-changed 'last'.
+        {
+            return last;
+        }
+
+        // Match was found.  'new_last' is now the first removed element.
+        ForwardIterator new_last = first;
+        ++first;
+
+        // Iterate through all the others.
+        while(first != last)
+        {
+            // If 'first' is a desired value, we need to copy it and move
+            // 'new_last'.
+            if (!(pred(*first)))
+            {
+                *new_last = *first;
+                ++new_last;
+            }
+
+            ++first;
+        }
+
+        return new_last;
+
+    }
+
+    /**
+     * Removes consecutive duplicate entries from a range.
+     *
+     * Removes all instances where (*i == *(i-1)) in the range [first, last)
+     * and returns an iterator to the end of the new range [first, new_last)
+     * where nothing in the new range is a consecutive duplicate.
+     *
+     * Unique does not decrease the size of the container.
+     *
+     * @param[in] first - The beginning of the range.
+     * @param[in] last - The end of the range.
+     *
+     * @return An iterator 'new_last' from [first, new_last).
+     *
+     */
+    template <typename ForwardIterator>
+    ForwardIterator unique(ForwardIterator first, ForwardIterator last)
+    {
+        // Trivial case of 0 items, return.
+        if (first == last) return last;
+
+        // The algorithm keeps 3 iterators 'prev', 'first', and 'last'.  The
+        // 'prev' iterator is always the last instance to be kept.  'last' is
+        // the end of the original range.  'first' is kept to be the item
+        // being compared.
+
+        // Point 'prev' at the first element of the range since first item is 
+        // a keeper.
+        ForwardIterator prev = first;
+        ++first;
+
+        while (first != last)
+        {
+            // If the two items are not the same, we found a new item to keep.
+            if (!(*prev == *first))
+            {
+                // Increment the "keep slot".
+                ++prev;
+
+                // If the "keep slot" is not the element being compared, we
+                // need to move the new item down to that keep slot.
+                if (prev != first)
+                {
+                    *prev = *first;
+                }
+            }
+
+            // Advance to the next element.
+            ++first;
+        }
+
+        // 'prev' points to the last item to be kept.  Increment it to make 
+        // it point to the one past.
+        ++prev;
+        return prev;
+    }
+
+    /**
+     * Removes consecutive duplicate entries from a range by predicate.
+     *
+     * Removes all instances where pred(*i,*(i-1)) is true in the
+     * range [first, last) and returns an iterator to the end of the new 
+     * range [first, new_last) where nothing in the new range is a 
+     * consecutive duplicate.
+     *
+     * Unique does not decrease the size of the container.
+     *
+     * @param[in] first - The beginning of the range.
+     * @param[in] last - The end of the range.
+     * @param[in] pred - The predicate.
+     *
+     * @return An iterator 'new_last' from [first, new_last).
+     *
+     */
+    template <typename ForwardIterator, typename BinaryPredicate>
+    ForwardIterator unique(ForwardIterator first, ForwardIterator last,
+                           BinaryPredicate pred)
+    {
+        // Trivial case of 0 items, return.
+        if (first == last) return last;
+
+        // The algorithm keeps 3 iterators 'prev', 'first', and 'last'.  The
+        // 'prev' iterator is always the last instance to be kept.  'last' is
+        // the end of the original range.  'first' is kept to be the item
+        // being compared.
+
+        // Point 'prev' at the first element of the range since first item is 
+        // a keeper.
+        ForwardIterator prev = first;
+        ++first;
+
+        while (first != last)
+        {
+            // If the two items are not the same, we found a new item to keep.
+            if (!(pred(*prev,*first)))
+            {
+                // Increment the "keep slot".
+                ++prev;
+
+                // If the "keep slot" is not the element being compared, we
+                // need to move the new item down to that keep slot.
+                if (prev != first)
+                {
+                    *prev = *first;
+                }
+            }
+
+            // Advance to the next element.
+            ++first;
+        }
+
+        // 'prev' points to the last item to be kept.  Increment it to make 
+        // it point to the one past.
+        ++prev;
+        return prev;
+    }
+
+    /** Sort a range.
+     *
+     *  Sorts all the elements in [first, last) using such that *i < *(i+1)
+     *  for all items in the range.
+     *
+     *  @param[in] first - The beginning of the range.
+     *  @param[in] last - The end of the range.
+     */
+    template <typename RandomAccessIterator>
+    void sort(RandomAccessIterator first, RandomAccessIterator last)
+    {
+        Util::__Util_QSort_Impl::sort(first, last);
+    }
+
+    /** Sort a range using a predicate
+     *
+     *  Sorts all the elements in [first, last) using such that 
+     *  pred(*i, *(i+1)) is true for all items in the range.
+     *
+     *  @param[in] first - The beginning of the range.
+     *  @param[in] last - The end of the range.
+     *  @param[in] pred - The predicate to use for comparison.
+     */
+    template <typename RandomAccessIterator, typename StrictWeakOrdering>
+    void sort(RandomAccessIterator first, RandomAccessIterator last,
+              StrictWeakOrdering pred)
+    {
+        Util::__Util_QSort_Impl::sort(first, last, pred);
+    }
+
+    /** Transform one sequence into another. 
+     *
+     *  Executes an operator against all elements in [first, last) and writes
+     *  the result to another sequence.
+     *
+     *  @param first - Beginning of the input range.
+     *  @param last - Ending of the input range.
+     *  @param result - Beginning of the output range.
+     *  @param op - The transformation operator.
+     */
+    template <typename InputIterator, typename OutputIterator, 
+              typename UnaryFunction>
+    OutputIterator transform(InputIterator first, InputIterator last,
+                             OutputIterator result, UnaryFunction op)
+    {
+        while (first != last)
+        {
+            *result = op(*first);
+            ++result;
+            ++first;
+        }
+        return result;
+    }
+
+    /** Transform two sequences into another. 
+     *
+     *  Executes an operator against all elements in [first1, last1) along
+     *  with the peer from [first2, ...) and writes the result to 
+     *  another sequence.
+     *
+     *  @param first1 - Beginning of the first input range.
+     *  @param last1 - Ending of the first input range.
+     *  @param first2 - Beginning of the second input range.
+     *  @param result - Beginning of the output range.
+     *  @param op - The transformation operator.
+     */
+    template <typename InputIterator1, typename InputIterator2,
+              typename OutputIterator, typename BinaryFunction>
+    OutputIterator transform(InputIterator1 first1, InputIterator1 last1,
+                             InputIterator2 first2, OutputIterator result, 
+                             BinaryFunction op)
+    {
+        while (first1 != last1)
+        {
+            *result = op(*first1, *first2);
+            ++result;
+            ++first1; ++first2;
+        }
+        return result;
+    }
+
+
+
+};
+#endif
+
+#endif
+/* vim: set filetype=cpp : */
diff --git a/src/import/chips/p9/procedures/ppe/include/std/iterator b/src/import/chips/p9/procedures/ppe/include/std/iterator
new file mode 100644
index 00000000..45e0386e
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/include/std/iterator
@@ -0,0 +1,187 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/include/std/iterator $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __STL_ITERATOR
+#define __STL_ITERATOR
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+
+#include <util/impl/iterator.h>
+
+namespace std
+{
+
+/** @struct iterator_traits
+ *  Template class defining a mapping typenames to ones defined in an iterator.
+ */
+template <typename Iterator>
+struct iterator_traits
+{
+    typedef typename Iterator::value_type value_type;
+    typedef typename Iterator::difference_type difference_type;
+    typedef typename Iterator::pointer pointer;
+    typedef typename Iterator::reference reference;
+};
+
+/** @struct iterator_traits
+ *  Template specialization of iterator traits for treating pointer types
+ *  as an iterator.
+ */
+template <typename T>
+struct iterator_traits<T*>
+{
+    typedef T value_type;
+    typedef ptrdiff_t difference_type;
+    typedef T* pointer;
+    typedef T& reference;
+};
+
+/** Advance an iterator.
+ *
+ * @param[in] i - The iterator to advance.
+ * @param[in] n - The distance to advance the iterator.
+ *
+ * This function is equivalent to calling (++i) n times.  
+ *
+ * If the iterator supports random access then this function will be 
+ * implemented in linear time with respect to n.
+ * 
+ */
+template <typename InputIterator, typename Distance>
+void advance(InputIterator& i, Distance n)
+{
+    Util::__Util_Iterator_Impl::advance<InputIterator, Distance>(i, n);
+}
+
+/** Determine the distance between two iterators.
+ *
+ *  @param[in] first - The first iterator.
+ *  @param[in] last - The last iterator.
+ *
+ *  @return The distance between the two iterators.
+ *
+ *  The distance between two iterators is the number of times first would
+ *  need to be incremented so that it is equal to last.
+ *
+ *  If the iterator supports random access then this function will be
+ *  implemented in linear time with respect to the distance between the
+ *  two iterators.  A negative distance can only be obtained with random
+ *  access iterators.
+ */
+template <typename InputIterator>
+typename iterator_traits<InputIterator>::difference_type 
+    distance(InputIterator first, InputIterator last)
+{
+    return Util::__Util_Iterator_Impl::distance<
+                InputIterator, 
+                typename iterator_traits<InputIterator>::difference_type>
+        (first, last);
+}
+
+/** A OutputIterator which operates by push_back onto a container.
+ *
+ *  See public std::back_insert_iterator documentation.
+ */
+template <typename BackInsertionSequence>
+class back_insert_iterator
+{
+    public:
+            // Common iterator typedefs.
+        typedef typename BackInsertionSequence::value_type value_type;
+        typedef typename BackInsertionSequence::difference_type difference_type;
+        typedef typename BackInsertionSequence::pointer pointer;
+        typedef typename BackInsertionSequence::reference reference;
+
+            /** Default constructor from a container reference. */
+        back_insert_iterator(BackInsertionSequence& s) : sequence(s) {};
+            /** Copy constructor.  Reuses container reference. */
+        back_insert_iterator(const back_insert_iterator& i)
+            : sequence(i.sequence) {};
+
+            /** Assignment (copy) operator. */
+        back_insert_iterator& operator=(const back_insert_iterator& i)
+        {
+            sequence = i.sequence;
+            return *this;
+        }
+
+        /** Dereference operator.
+         *
+         *  This is used to make the standard pattern '*i = x' work on
+         *  an iterator.  Since we need to 'push_back' into the 
+         *  container we don't actually return anything except ourself,
+         *  which allows the operator= to be called.
+         */
+        back_insert_iterator& operator*() { return *this; }
+
+        /** Assignment operator.
+         *
+         *  This is the second part of the standard pattern '*i = x'.
+         *
+         *  Adds the value to the container by calling push_back.
+         *
+         *  @param[in] v - The value to insert to the container.
+         */
+        back_insert_iterator& operator=(const value_type& v)
+        {
+            sequence.push_back(v);
+            return *this;
+        }
+
+            /** Preincrement operator - no-op */
+        back_insert_iterator& operator++() { return *this; };
+            /** Postincrement operator - no-op */
+        back_insert_iterator& operator++(int unused) { return *this; };
+
+    private:
+            /** The container to insert into. */
+        BackInsertionSequence& sequence;
+};
+
+/** Create a back_insert_iterator from a container.
+ *
+ *  Utility function to allow back_insert_iterators to be created without
+ *  needing to specify the underlying container type.
+ *
+ *  Example:  Reverse copy elements from one vector into a new vector.
+ *      copy(v.rbegin(), v.rend(), back_inserter(v2));
+ *
+ *  @param[in] s - Sequence to create an iterator for.
+ *  
+ *  @return The back_insert_iterator.
+ */
+template <typename BackInsertionSequence>
+back_insert_iterator<BackInsertionSequence> 
+    back_inserter(BackInsertionSequence& s)
+{
+    return back_insert_iterator<BackInsertionSequence>(s);
+}
+
+}; // namespace std.
+#endif
+
+#endif
+/* vim: set filetype=cpp : */
diff --git a/src/import/chips/p9/procedures/ppe/include/std/new b/src/import/chips/p9/procedures/ppe/include/std/new
new file mode 100755
index 00000000..4d323cf7
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/include/std/new
@@ -0,0 +1,42 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/include/std/new $              */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __NEW_H
+#define __NEW_H
+
+#ifdef __cplusplus
+inline
+void *operator new(size_t, void* place)
+{
+    return place;
+}
+
+inline
+void *operator new[](size_t, void* place)
+{
+    return place;
+}
+#endif
+
+#endif
diff --git a/src/import/chips/p9/procedures/ppe/include/std/type_traits b/src/import/chips/p9/procedures/ppe/include/std/type_traits
new file mode 100644
index 00000000..1d2e3f0a
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/include/std/type_traits
@@ -0,0 +1,110 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/include/std/type_traits $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#if !defined(_TYPE_TRAITS)
+#define _TYPE_TRAITS
+
+namespace std
+{
+    /// integral_constant
+    template<typename _Tp, _Tp __v>
+        struct integral_constant
+        {
+            static const _Tp                      value = __v;
+            typedef _Tp                           value_type;
+            typedef integral_constant<_Tp, __v>   type;
+        };
+
+    /// typedef for true_type
+    typedef integral_constant<bool, true>     true_type;
+
+    /// typedef for false_type
+    typedef integral_constant<bool, false>    false_type;
+
+    template<typename _Tp, _Tp __v>
+        const _Tp integral_constant<_Tp, __v>::value;
+
+    /// remove_const
+    template<typename _Tp>
+        struct remove_const
+        { typedef _Tp     type; };
+
+    /// remove_volatile
+    template<typename _Tp>
+        struct remove_volatile
+        { typedef _Tp     type; };
+
+    /// remove_cv
+    template<typename _Tp>
+        struct remove_cv
+        {
+            typedef typename
+                remove_const<typename remove_volatile<_Tp>::type>::type     type;
+        };
+
+    template<typename> struct _is_integral_type : public false_type { };
+    template<> struct _is_integral_type<bool>: public integral_constant<bool,true> {};
+    template<> struct _is_integral_type<char>: public integral_constant<bool,true> {};
+    template<> struct _is_integral_type<signed char>: public integral_constant<bool,true> {};
+    template<> struct _is_integral_type<unsigned char>: public integral_constant<bool,true> {};
+    template<> struct _is_integral_type<short>: public integral_constant<bool,true> {};
+    template<> struct _is_integral_type<unsigned short>: public integral_constant<bool,true> {};
+    template<> struct _is_integral_type<int>: public integral_constant<bool,true> {};
+    template<> struct _is_integral_type<unsigned int>: public integral_constant<bool,true> {};
+    template<> struct _is_integral_type<long>: public integral_constant<bool,true> {};
+    template<> struct _is_integral_type<unsigned long>: public integral_constant<bool,true> {};
+    template<> struct _is_integral_type<long long>: public integral_constant<bool,true> {};
+    template<> struct _is_integral_type<unsigned long long>: public integral_constant<bool,true> {};
+
+    /// is_integral
+    template<typename _Tp>
+        struct is_integral
+        : public integral_constant<bool, (_is_integral_type<typename
+                                          remove_cv<_Tp>::type>::value)>
+    { };
+  /// is_same
+  template<typename, typename>
+    struct is_same
+    : public false_type { };
+
+  template<typename _Tp>
+    struct is_same<_Tp, _Tp>
+    : public true_type { };
+
+  template<typename>
+    struct __is_pointer_helper
+    : public false_type { };
+
+  template<typename _Tp>
+    struct __is_pointer_helper<_Tp*>
+    : public true_type { };
+
+  /// is_pointer
+  template<typename _Tp>
+    struct is_pointer
+    : public integral_constant<bool, (__is_pointer_helper<typename
+                      remove_cv<_Tp>::type>::value)>
+    { };
+}
+#endif
diff --git a/src/import/chips/p9/procedures/ppe/include/std/util/impl/iterator.h b/src/import/chips/p9/procedures/ppe/include/std/util/impl/iterator.h
new file mode 100644
index 00000000..6b2794f5
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/include/std/util/impl/iterator.h
@@ -0,0 +1,153 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/include/std/util/impl/iterator.h $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef __UTIL_IMPL_ITERATOR_H
+#define __UTIL_IMPL_ITERATOR_H
+
+/** @file iterator.h
+ *
+ *  Contains the internal implementation details of the stl <iterator> header.
+ */
+
+#include <util/traits/has_plusequals.H>
+#include <util/traits/has_minus.H>
+
+namespace Util
+{
+namespace __Util_Iterator_Impl
+{
+
+/**
+ *  Template definition of an iterator advance functor.
+ */
+template <typename InputIterator, typename Distance,
+          bool HasPlusEquals> struct AdvanceImpl;
+
+/**
+ *  Template specialization of the advance functor for iterators
+ *  which do not support random access.
+ */
+template <typename InputIterator, typename Distance>
+struct AdvanceImpl<InputIterator, Distance, false>
+{
+    static void advance(InputIterator& i, Distance n)
+    {
+        while(n--)
+        {
+            ++i;
+        }
+    }
+};
+
+/**
+ *  Template specialization of the advance functor for iterators
+ *  which do support random access.
+ */
+template <typename RandomIterator, typename Distance>
+struct AdvanceImpl<RandomIterator, Distance, true>
+{
+    static void advance(RandomIterator& i, Distance n)
+    {
+        i += n;
+    }
+};
+
+/**
+ *  Template wrapper function for the iterator advance.
+ *
+ *  Uses the existence of a += operator on the iterator to determine
+ *  if the random-access or non-random-access version should be used.
+ */
+template <typename InputIterator, typename Distance>
+void advance(InputIterator& i, Distance n)
+{
+    AdvanceImpl<InputIterator, Distance,
+                Util::Traits::has_plusequals<InputIterator, Distance,
+                InputIterator>::value
+                >::advance(i, n);
+}
+
+/**
+ *  Template definition of an iterator distance functor.
+ */
+template <typename InputIterator, typename Distance,
+          bool HasMinus> struct DistanceImpl;
+
+/**
+ *  Template specialization of the distance functor for iterators
+ *  which do not support random access.
+ */
+template <typename InputIterator, typename Distance>
+struct DistanceImpl<InputIterator, Distance, false>
+{
+    static Distance distance(InputIterator& first,
+                             InputIterator& last)
+    {
+        Distance i = 0;
+
+        while (first != last)
+        {
+            ++i;
+            ++first;
+        }
+
+        return i;
+    }
+};
+
+/**
+ *  Template specialization of the distance functor for iterators
+ *  which do support random access.
+ */
+template <typename RandomIterator, typename Distance>
+struct DistanceImpl<RandomIterator, Distance, true>
+{
+    static Distance distance(RandomIterator& first,
+                             RandomIterator& last)
+    {
+        return last - first;
+    }
+};
+
+/**
+ *  Template wrapper function for the iterator distance.
+ *
+ *  Uses the existence of a - operator on the iterator to determine
+ *  if the random-access or non-random-access version should be used.
+ */
+template <typename InputIterator, typename Distance>
+Distance distance(InputIterator& first,
+                  InputIterator& last)
+{
+    return DistanceImpl<InputIterator, Distance,
+           Util::Traits::has_minus<InputIterator, InputIterator,
+           Distance>::value
+           >::distance(first, last);
+}
+
+};
+};
+
+#endif
diff --git a/src/import/chips/p9/procedures/ppe/include/std/util/impl/qsort.H b/src/import/chips/p9/procedures/ppe/include/std/util/impl/qsort.H
new file mode 100644
index 00000000..1bb0e10e
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/include/std/util/impl/qsort.H
@@ -0,0 +1,197 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/include/std/util/impl/qsort.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef __UTIL_IMPL_QSORT_H
+#define __UTIL_IMPL_QSORT_H
+
+/** @file qsort.H
+ *
+ *  Contains the internal implementation details of std::sort implemented as
+ *  quick-sort.
+ */
+
+#include <iterator>
+
+// Forward declaration due to 'swap' being defined in <algorithm> which is
+// including this file itself.
+namespace std
+{
+template <typename T> void swap(T& a, T& b);
+};
+
+namespace Util
+{
+namespace __Util_QSort_Impl
+{
+template <typename RandomAccessIterator>
+void sort(RandomAccessIterator first, RandomAccessIterator last)
+{
+    size_t length = std::distance(first, last);
+
+    // A range of length 0 or 1 is already sort.
+    if ((length == 0) || (length == 1))
+    {
+        return;
+    }
+
+    // A range of length 2 has a trivial sort.
+    if (length == 2)
+    {
+        RandomAccessIterator next = first;
+        std::advance(next, 1);
+
+        if (*next < *first)
+        {
+            std::swap(*first, *next);
+        }
+
+        return;
+    }
+
+    // Choose pivot as middle and move pivot to end.
+    //     This is done to eliminate the O(n^2) behavior when the
+    //     range is already sorted.
+    RandomAccessIterator pivot = first;
+    std::advance(pivot, length - 1);
+    RandomAccessIterator middle = first;
+    std::advance(middle, length / 2);
+    std::swap(*pivot, *middle);
+
+    // Perform partitioning...
+
+    // Division points to the first element greater than the pivot or
+    // else the farthest point partitioned if no elements greater than
+    // the pivot have been found yet.
+    RandomAccessIterator division = first;
+    RandomAccessIterator pos = first;
+
+    while(pos != pivot)
+    {
+        // Element less than the pivot is found, so move it to the
+        // "less than" side of the division line.
+        if (*pos < *pivot)
+        {
+            if (pos != division)
+            {
+                std::swap(*pos, *division);
+            }
+
+            ++division;
+        }
+
+        ++pos;
+    }
+
+    // Move the pivot down to the division line, which is its sorted
+    // position in the range.
+    if (pivot != division)
+    {
+        std::swap(*pivot, *division);
+    }
+
+    // Sort each partition
+    __Util_QSort_Impl::sort(first, division);
+    std::advance(division, 1);
+    __Util_QSort_Impl::sort(division, last);
+};
+
+
+template <typename RandomAccessIterator, typename StrictWeakOrdering>
+void sort(RandomAccessIterator first, RandomAccessIterator last,
+          StrictWeakOrdering pred)
+{
+    size_t length = std::distance(first, last);
+
+    // A range of length 0 or 1 is already sort.
+    if ((length == 0) || (length == 1))
+    {
+        return;
+    }
+
+    // A range of length 2 has a trivial sort.
+    if (length == 2)
+    {
+        RandomAccessIterator next = first;
+        std::advance(next, 1);
+
+        if (pred(*next, *first))
+        {
+            std::swap(*first, *next);
+        }
+
+        return;
+    }
+
+    // Choose pivot as middle and move pivot to end.
+    //     This is done to eliminate the O(n^2) behavior when the
+    //     range is already sorted.
+    RandomAccessIterator pivot = first;
+    std::advance(pivot, length - 1);
+    RandomAccessIterator middle = first;
+    std::advance(middle, length / 2);
+    std::swap(*pivot, *middle);
+
+    // Perform partitioning...
+
+    // Division points to the first element greater than the pivot or
+    // else the farthest point partitioned if no elements greater than
+    // the pivot have been found yet.
+    RandomAccessIterator division = first;
+    RandomAccessIterator pos = first;
+
+    while(pos != pivot)
+    {
+        // Element less than the pivot is found, so move it to the
+        // "less than" side of the division line.
+        if (pred(*pos, *pivot))
+        {
+            if (pos != division)
+            {
+                std::swap(*pos, *division);
+            }
+
+            ++division;
+        }
+
+        ++pos;
+    }
+
+    // Move the pivot down to the division line, which is its sorted
+    // position in the range.
+    if (pivot != division)
+    {
+        std::swap(*pivot, *division);
+    }
+
+    // Sort each partition.
+    __Util_QSort_Impl::sort(first, division, pred);
+    std::advance(division, 1);
+    __Util_QSort_Impl::sort(division, last, pred);
+};
+
+};
+};
+
+#endif
diff --git a/src/import/chips/p9/procedures/ppe/include/std/util/traits/has_lessthan.H b/src/import/chips/p9/procedures/ppe/include/std/util/traits/has_lessthan.H
new file mode 100644
index 00000000..f289ea5d
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/include/std/util/traits/has_lessthan.H
@@ -0,0 +1,42 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/include/std/util/traits/has_lessthan.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef __UTIL_TRAITS_HAS_LESSTHAN
+#define __UTIL_TRAITS_HAS_LESSTHAN
+
+/** @file has_lessthan.H
+ *  Creates a template class has_lessthan<T> who's value variable will tell
+ *  if T has a valid < comparison operation.
+ */
+
+#define UTIL_COMPARISON_OPERATOR <
+#define UTIL_COMPARISON_OPERATOR_NAME lessthan
+
+#include <util/traits/impl/has_comparison.H>
+
+#undef UTIL_COMPARISON_OPERATOR
+#undef UTIL_COMPARISON_OPERATOR_NAME
+
+#endif
diff --git a/src/import/chips/p9/procedures/ppe/include/std/util/traits/has_minus.H b/src/import/chips/p9/procedures/ppe/include/std/util/traits/has_minus.H
new file mode 100644
index 00000000..5d8778c9
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/include/std/util/traits/has_minus.H
@@ -0,0 +1,42 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/include/std/util/traits/has_minus.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef __UTIL_TRAITS_HAS_MINUS
+#define __UTIL_TRAITS_HAS_MINUS
+
+/** @file has_minus.H
+ *  Creates a template class has_minus<T> who's value variable will tell
+ *  if T has a valid - operation.
+ */
+
+#define UTIL_COMPARISON_OPERATOR -
+#define UTIL_COMPARISON_OPERATOR_NAME minus
+
+#include <util/traits/impl/has_comparison.H>
+
+#undef UTIL_COMPARISON_OPERATOR
+#undef UTIL_COMPARISON_OPERATOR_NAME
+
+#endif
diff --git a/src/import/chips/p9/procedures/ppe/include/std/util/traits/has_plusequals.H b/src/import/chips/p9/procedures/ppe/include/std/util/traits/has_plusequals.H
new file mode 100644
index 00000000..a26d34ae
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/include/std/util/traits/has_plusequals.H
@@ -0,0 +1,42 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/include/std/util/traits/has_plusequals.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef __UTIL_TRAITS_HAS_PLUSEQUALS
+#define __UTIL_TRAITS_HAS_PLUSEQUALS
+
+/** @file has_plusequals.H
+ *  Creates a template class has_plusequals<T> who's value variable will tell
+ *  if T has a valid += operation.
+ */
+
+#define UTIL_COMPARISON_OPERATOR +=
+#define UTIL_COMPARISON_OPERATOR_NAME plusequals
+
+#include <util/traits/impl/has_comparison.H>
+
+#undef UTIL_COMPARISON_OPERATOR
+#undef UTIL_COMPARISON_OPERATOR_NAME
+
+#endif
diff --git a/src/import/chips/p9/procedures/ppe/include/std/util/traits/impl/has_comparison.H b/src/import/chips/p9/procedures/ppe/include/std/util/traits/impl/has_comparison.H
new file mode 100644
index 00000000..07ea589a
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/include/std/util/traits/impl/has_comparison.H
@@ -0,0 +1,137 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/include/std/util/traits/impl/has_comparison.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+/** @file has_comparison.H
+ *
+ *  Defines the guts of a has_foo<T> template where 'foo' is a binary
+ *  comparison operator on a type T.  This template can be used for
+ *  template meta-programming purposes.
+ *
+ *  The macros UTIL_COMPARISON_OPERATOR and UTIL_COMPARISON_OPERATOR_NAME
+ *  can be defined to create a template. For instance (<, lessthan) will
+ *  create a template has_lessthan that allows determination to be made on
+ *  if T has a valid < operator.
+ *
+ *  This file purposefully omits an include-guard to allow multiple templates
+ *  to be defined for all the various comparison operators.
+ *
+ *  Notice that a heavy dose of SFINAE techniques follow.
+ */
+
+// Ensure UTIL_COMPARISON_OPERATOR has been defined.
+#ifndef UTIL_COMPARISON_OPERATOR
+    #error Comparison operator is not defined.
+#endif
+
+// Ensure UTIL_COMPARISON_OPERATOR_NAME has been defined.
+#ifndef UTIL_COMPARISON_OPERATOR_NAME
+    #error Comparison operator name is not defined.
+#endif
+
+// Macro magic to make well-formed variable names from existing #defines.
+#define __UTIL_TRAIT_COMPARISON_MAKENAME(X,Y)   X ## Y
+#define _UTIL_TRAIT_COMPARISON_MAKENAME(X,Y)    \
+    __UTIL_TRAIT_COMPARISON_MAKENAME(X,Y)
+#define UTIL_TRAIT_COMPARISON_MAKENAME(X) \
+    _UTIL_TRAIT_COMPARISON_MAKENAME(X,\
+                                    UTIL_COMPARISON_OPERATOR_NAME)
+
+namespace Util
+{
+
+// Creates a namespace of the form Util::__Util_Trait_Impl_OPERATOR_NAME to
+// hide the template implementation in.
+namespace UTIL_TRAIT_COMPARISON_MAKENAME(__Util_Trait_Impl_)
+{
+// If "T op S" is valid, it is going to return a type R.  If it is not
+// valid, we still need it to compile cleanly.  So what we do is
+// create a type (convert_from_any_type) that causes implicit type
+// conversion from any other type.  We ensure that the operator against
+// convert_from_any_type returns a special type (bad_type).
+//
+// If "T op S" is valid then the implicit type conversion to
+// convert_from_any_type will not happen because the native "T op S" takes
+// precidence.  So "T op S" has type not equal to bad_type.  If "T op S"
+// is invalid then the implicit type conversion will cause "T op S" to have
+// type bad_type.
+
+struct bad_type {};
+struct convert_from_any_type
+{
+    template <class C> convert_from_any_type(C const&);
+};
+bad_type operator UTIL_COMPARISON_OPERATOR (const convert_from_any_type&,
+        const convert_from_any_type&);
+
+
+// Now, "T op S" is going to return either bad_type or something else.  We
+// define a function 'has_comparison' that returns a character array of
+// different size based on the input parameter type.  Then the "sizeof"
+// can be used to tell if "T op S" returns bad_type or something else.
+//
+// The only additional oddity is the get_instance function.  Since some
+// classes cannot be directly constructed, this is a level of indirection
+// to get a type of T and S to apply the operator against.
+template <typename _T, typename _S, typename _R>
+struct UTIL_TRAIT_COMPARISON_MAKENAME(has_)
+{
+    typedef char yes[1];
+    typedef char no[2];
+
+    static no& has_comparison(bad_type);
+    static yes& has_comparison(_R);
+
+    template <typename C> static C& get_instance();
+
+    static const bool value =
+        sizeof(has_comparison(get_instance<_T>() UTIL_COMPARISON_OPERATOR
+                              get_instance<_S>())) == sizeof(yes);
+};
+
+};
+
+
+// Since the implementation was hidden in a __Util_Trait_Impl_OPERATOR_NAME
+// namespace, we expose just the main comparison class (with the value variable)
+// by defining a class in the Traits namespace that inherits from the one in
+// the __Util_Trait_Impl_OPERATOR_NAME namespace.
+namespace Traits
+{
+template <typename _T, typename _S = _T,
+          typename _R = typename
+          UTIL_TRAIT_COMPARISON_MAKENAME(Util::__Util_Trait_Impl_)::
+          convert_from_any_type>
+struct UTIL_TRAIT_COMPARISON_MAKENAME(has_) :
+    public UTIL_TRAIT_COMPARISON_MAKENAME(Util::__Util_Trait_Impl_)::
+    UTIL_TRAIT_COMPARISON_MAKENAME(has_)<_T, _S, _R>
+{};
+};
+
+};
+
+#undef __UTIL_TRAIT_COMPARISON_MAKENAME
+#undef _UTIL_TRAIT_COMPARISON_MAKENAME
+#undef UTIL_TRAIT_COMPARISON_MAKENAME
+
diff --git a/src/import/chips/p9/procedures/ppe/include/std/util/traits/remove_const.H b/src/import/chips/p9/procedures/ppe/include/std/util/traits/remove_const.H
new file mode 100644
index 00000000..b447ff83
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/include/std/util/traits/remove_const.H
@@ -0,0 +1,73 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/include/std/util/traits/remove_const.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef __UTIL_TRAITS_REMOVE_CONST
+#define __UTIL_TRAITS_REMOVE_CONST
+
+/** @file remove_const.H
+ *  Creates a template class remove_const who's type typedef will strip the
+ *  "const" from another type.
+ *
+ *  Example:
+ *      remove_const<const int>::type == int
+ *      remove_const<int>::type == int
+ *      remove_const<const int*>::type == int*
+ *
+ */
+
+namespace Util
+{
+namespace Traits
+{
+template <typename T> struct remove_const;
+
+template <typename T>
+struct remove_const<const T>
+{
+    typedef T type;
+};
+
+template <typename T>
+struct remove_const<const T*>
+{
+    typedef T* type;
+};
+
+template <typename T>
+struct remove_const<const T&>
+{
+    typedef T& type;
+};
+
+template <typename T>
+struct remove_const
+{
+    typedef T type;
+};
+
+};
+};
+
+#endif
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/Makefile b/src/import/chips/p9/procedures/ppe/pk/kernel/Makefile
new file mode 100644
index 00000000..9494348f
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/Makefile
@@ -0,0 +1,50 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/ppe/pk/kernel/Makefile $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+# This Makefile is designed to be invoked with the -I argument set to
+# the location of the "pk.mk" for the build
+
+include img_defs.mk
+include pkkernelfiles.mk
+
+ifeq "$(PK_TIMER_SUPPORT)" "1"
+PK_OBJECTS += ${PK-TIMER-C-SOURCES:.c=.o}
+endif
+
+ifeq "$(PK_THREAD_SUPPORT)" "1"
+PK_OBJECTS += ${PK-THREAD-C-SOURCES:.c=.o} 
+endif
+
+OBJS := $(addprefix $(OBJDIR)/, $(PK_OBJECTS))
+
+all: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d)
+endif
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk.h b/src/import/chips/p9/procedures/ppe/pk/kernel/pk.h
new file mode 100644
index 00000000..7d063b75
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk.h
@@ -0,0 +1,149 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk.h $               */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PK_H__
+#define __PK_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk.h
+/// \brief The combined header of the PK kernel.
+///
+/// This header will be included in any C or assembler source file that
+/// requires any of the PK API.  All headers defined by PK and co-compiled
+/// code should be protected such that they can be included without error into
+/// assembly.
+
+#ifndef __ASSEMBLER__
+    #include <stdint.h>
+    #include <stddef.h>
+#endif  /* __ASSEMBLER__ */
+
+#ifndef __PK__
+    #define __PK__ 1
+#endif
+
+/// The application environment specifies whether or not it will provide an
+/// application configuration file, which must be named "pk_app_cfg.h".
+
+#ifndef USE_PK_APP_CFG_H
+    #define USE_PK_APP_CFG_H 0
+#endif
+
+#if USE_PK_APP_CFG_H
+    #include "pk_app_cfg.h"
+#endif
+
+#include "pk_macros.h"
+#include "pk_api.h"
+#include "pk_port.h"
+#include "pk_kernel.h"
+//#include "pk_io.h"
+
+#ifndef __ASSEMBLER__
+
+#define MIN(X, Y)                               \
+    ({                                          \
+        typeof (X) __x = (X);                   \
+        typeof (Y) __y = (Y);                   \
+        (__x < __y) ? __x : __y; })
+
+#define MAX(X, Y)                               \
+    ({                                          \
+        typeof (X) __x = (X);                   \
+        typeof (Y) __y = (Y);                   \
+        (__x > __y) ? __x : __y;                \
+    })
+
+/// \todo These don't require 32/64 bit versions, can always promote 32->64.
+
+#define FLOOR_LOG2_32(x) (32 - 1 - cntlz32(x))
+#define FLOOR_LOG2_64(x) (64 - 1 - cntlz64(x))
+
+#define CEILING_LOG2(x)                         \
+    ({                                          \
+        uint64_t __x = (uint64_t)(x);           \
+        int __y;                                \
+        __y = FLOOR_LOG2_64(__x);               \
+        if ((__x & (__x - 1)) != 0) {           \
+            __y++;                              \
+        }                                       \
+        __y;})
+
+
+#define POW2_32(x) ((uint32_t)1 << (x))
+#define POW2_64(x) ((uint64_t)1 << (x))
+
+/// Cast a pointer to another type
+///
+/// This macro is necessary when casting a pointer to a longer integer type.
+/// The pointer is first cast to the equivalent integer type 'unsigned long',
+/// then cast to the final type. You can also use this to cast integers longer
+/// than pointers back to pointers.
+
+#define CAST_POINTER(t, p) ((t)((unsigned long)(p)))
+
+
+/// Create an alignment attribute.
+#define ALIGNED_ATTRIBUTE(alignment) __attribute__ ((aligned (alignment)))
+
+/// Create a specific-section attribute
+///
+/// Note that the section \a s here must be a string. Also note that data
+/// specified to reside in specific sections must always be
+/// initialized. Otherwise it confuses the linker which wants to put
+/// uninitialized data into .bss sections.
+///
+/// \code
+///
+/// int foo     SECTION_ATTRIBUTE(".noncacheable") = 0;
+/// int bar[10] SECTION_ATTRIBUTE(".noncacheable") = {0};
+///
+/// \endcode
+#define SECTION_ATTRIBUTE(s) __attribute__ ((section (s)))
+
+/// Create a 'used' attribute
+///
+/// This is required for example to avoid "function unused" warnings when a
+/// function is declared static but only referenced by inline assembler:
+///
+/// \code
+///
+/// static USED_ATTRIBUTE void
+/// _checkstop(void* arg, PkIrqId irq, int priority)
+/// {
+///     PK_PANIC(VALIDATION_CHECKSTOP);
+/// }
+///
+/// PK_IRQ_FAST2FULL(_validationCheckstopHandler, _checkstop);
+///
+/// \endcode
+#define USED_ATTRIBUTE __attribute__ ((used))
+
+#endif  /* __ASSEMBLER__ */
+
+#endif /* __PK_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_api.h b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_api.h
new file mode 100644
index 00000000..b094519c
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_api.h
@@ -0,0 +1,1029 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_api.h $           */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PK_API_H__
+#define __PK_API_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_api.h
+/// \brief Macros and declarations for the PK API.
+
+//  Basic constants
+
+/// Although the number of threads is defined as a manifest constant,
+/// numerous parts of the PK code assume this definition. The number of
+/// supported threads _can not_ be changed simply by changing this constant.
+
+#define PK_THREADS 32
+
+#define PK_IDLE_THREAD_PRIORITY PK_THREADS
+
+//  Interrupt API
+
+#define PK_IRQ_POLARITY_ACTIVE_LOW  0
+#define PK_IRQ_POLARITY_ACTIVE_HIGH 1
+
+#define PK_IRQ_TRIGGER_LEVEL_SENSITIVE 0
+#define PK_IRQ_TRIGGER_EDGE_SENSITIVE  1
+
+// API return codes
+
+#define PK_OK                                 0
+
+/// @see pk_panic_codes.h for valid return/panic codes
+
+/// \defgroup pk_thread_states PK Thread States
+///
+/// Threads are created in the state PK_THREAD_STATE_SUSPENDED_RUNNABLE.
+/// When the thread is mapped it transitions to state PK_THREAD_STATE_MAPPED.
+/// A mapped thread is runnable if it appears in the run queue; there is no
+/// other flag or status to indicate a runnable thread.  If a blocked thread
+/// is suspended it goes into state PK_THREAD_STATE_SUSPENDED_BLOCKED.  For
+/// all threads the reason for blockage is detailed in the \a flags field of
+/// the thread; See \ref pk_thread_flags.  PK_THREAD_STATE_DELETED and
+/// PK_THREAD_STATE_COMPLETED are effectively equivalent but named
+/// individually for reporting purposes.
+///
+/// \note This separation of the thread \a state and \a flags allows the use
+/// of an PK semaphore as a thread barrier, as it supports a non-iterative
+/// implementation of pk_semaphore_release_all() in which all threads blocked
+/// on the semaphore are simultaneously inserted into the run queue with an
+/// atomic operation, followed by each individual thread readjusting its flags
+/// appropriately once the thread runs again.
+///
+/// @{
+
+#define PK_THREAD_STATE_SUSPENDED_RUNNABLE 1
+#define PK_THREAD_STATE_MAPPED             2
+#define PK_THREAD_STATE_SUSPENDED_BLOCKED  3
+#define PK_THREAD_STATE_COMPLETED          4
+#define PK_THREAD_STATE_DELETED            5
+
+/// @}
+
+
+/// \defgroup pk_thread_flags PK Thread Flags
+///
+/// The \a flag field of the thread extends the information contained in the
+/// \a state field; See \ref pk_thread_states.  Blocked threads will show
+/// PK_THREAD_FLAG_SEMAPHORE_PEND, PK_THREAD_FLAG_TIMER_PEND or both (if
+/// blocked on a semaphore with timeout). The flag PK_THREAD_FLAG_TIMED_OUT
+/// indicates that a thread timer timed out before the thread became
+/// runnable.  Currently only the semaphore-pend-with-timeout code uses this
+/// flag.
+///
+/// Note that a thread can be mapped and runnable (in the run queue) even
+/// though PK_THREAD_FLAG_SEMAPHORE_PEND and/or PK_THREAD_FLAG_TIMER_PEND
+/// are set. These flags are always cleared by the thread itself, not the code
+/// that unblocks the thread. This allows the implementation of the
+/// pk_semaphore_release_all() as explained in \ref pk_thread_states.
+///
+/// @{
+
+#define PK_THREAD_FLAG_SEMAPHORE_PEND 0x1
+#define PK_THREAD_FLAG_TIMER_PEND     0x2
+#define PK_THREAD_FLAG_TIMED_OUT      0x4
+
+/// @}
+
+
+//  Critical Sections
+
+/// Enter a critical section, saving the current machine
+/// context.
+
+#define pk_critical_section_enter(pctx) \
+    pk_interrupt_disable(pctx)
+
+/// Exit a critical section by restoring the previous machine context.
+
+#define pk_critical_section_exit(pctx) \
+    pk_machine_context_set(pctx)
+
+
+/// Execute a statement atomically
+
+#define PK_ATOMIC(stmt) \
+    do { \
+        PkMachineContext __ctx; \
+        pk_critical_section_enter(&__ctx); \
+        stmt; \
+        pk_critical_section_exit(&__ctx); \
+    } while (0)
+
+
+// Application-overrideable definitions
+
+/// Control whether or not the API functions check for errors.
+///
+/// This definition can be overriden by the application.
+
+#ifndef PK_ERROR_CHECK_API
+    #define PK_ERROR_CHECK_API 1
+#endif
+
+/// Control whether API errors cause kernel panics or return negative error
+/// codes.
+///
+/// This selection is only valid if \c PK_ERROR_CHECK_API is defined
+/// non-0. This definition can be overriden by the application.
+
+#ifndef PK_ERROR_PANIC
+    #define PK_ERROR_PANIC 1
+#endif
+
+/// Control whether or not the PK kernel checks key invariants.
+///
+/// Violations of kernel invariants always cause kernel panics.  This
+/// definition can be overriden by the application.
+
+#ifndef PK_ERROR_CHECK_KERNEL
+    #define PK_ERROR_CHECK_KERNEL 1
+#endif
+
+/// Define the time interval type, which must be an unsigned type of a size
+/// less then or equal to the size of \c PkTimebase.  This definition can be
+/// overridden by the application.
+
+#ifndef PK_TIME_INTERVAL_TYPE
+    #define PK_TIME_INTERVAL_TYPE uint32_t
+#endif
+
+/// Provide support for the PkTimer APIs in addition to the default
+/// initerrupt APIs.  This definition can be overridden by the application.
+
+#ifndef PK_TIMER_SUPPORT
+    #define PK_TIMER_SUPPORT 1
+#endif
+
+/// Provide support for the all PK APIs. Thread support requires/implies
+/// support for time services and semaphores.  This definition can be
+/// overridden by the application.
+
+#ifndef PK_THREAD_SUPPORT
+    #define PK_THREAD_SUPPORT 1
+#endif
+
+/// Control the level of stack checking.
+///
+/// This definition can be overriden by the application.
+///
+/// 0 : No stack prepatterning or checking is made for thread and kernel
+/// stacks.
+///
+/// 1 : Kernel interrupt stacks are prepatterned during
+/// \c pk_initialize(). Thread stacks are prepatterned during
+/// \c pk_thread_create().
+///
+/// 2 : (\b Default - Currently Unimplemented) In addition to prepatterning,
+/// stack utilization is computed at the exit of context switches and
+/// interrupt processing.  The maximum utilization is stored in
+/// the thread data structure.  The kernel will panic if stack overflow is
+/// detected. Stack utilization is not computed for the idle thread.
+
+#ifndef PK_STACK_CHECK
+    #define PK_STACK_CHECK 1
+#endif
+
+/// A hook for main()
+///
+/// This hook macro is expanded in the body of __pk_main() prior to the call
+/// of the application main().  The application can redefine this hook macro
+/// in (or in headers referred to in) the application header
+/// pk_app_cfg.h. The PK_MAIN_HOOK will run on the stack of main().
+
+#ifndef PK_MAIN_HOOK
+    #define PK_MAIN_HOOK do {} while (0)
+#endif
+
+/// A hook for pk_start_threads()
+///
+/// This hook macro is expanded in the call-tree of pk_start_threads() before
+/// threads are actually started.  The application can redefine this hook
+/// macro in (or in headers referred to in) the application header
+/// pk_app_cfg.h.
+///
+/// The PK_START_THREADS_HOOK runs as a pseudo-interrupt handler on the
+/// kernel stack, with external interrupts disabled.
+
+#ifndef PK_START_THREADS_HOOK
+    #define PK_START_THREADS_HOOK do {} while (0)
+#endif
+
+/// The maximum value of the \c PkTimebase type.
+
+#define PK_TIMEBASE_MAX ((PkTimebase)-1)
+
+/// A special value that specifies that the timebase will not be reset during
+/// pk_init().
+
+#define PK_TIMEBASE_CONTINUES PK_TIMEBASE_MAX
+
+/// By convention, a timeout value indicating 'no waiting' in a call of \c
+/// pk_semaphore_pend().
+
+#define PK_NO_WAIT 0
+
+/// By convention, a timeout value indicating 'wait forever' in a call of \c
+/// pk_semaphore_pend().
+
+#define PK_WAIT_FOREVER ((PkInterval)-1)
+
+/// The PK timebase frequency in Hz
+///
+/// Earlier version of PK defined the timbase frequency as a preprocessor
+/// macro. Now, the timebase frequency is specified as a parameter of the
+/// pk_initialize() API. The macro remains defined for backwards
+/// compatibility, however all kernel uses of the timebase frequency are now
+/// optimized around the timebase parameter.
+
+#define PK_TIMEBASE_FREQUENCY_HZ __pk_timebase_frequency_hz
+
+/// This is the unscaled timebase frequency in Hz.
+#ifndef PK_BASE_FREQ_HZ
+    #ifdef APPCFG_USE_EXT_TIMEBASE
+        #define PK_BASE_FREQ_HZ     (uint32_t)25000000
+    #else
+        #define PK_BASE_FREQ_HZ     (uint32_t)400000000
+    #endif /* APPCFG_USE_EXT_TIMEBASE */
+#endif
+#define PK_BASE_FREQ_KHZ    (PK_BASE_FREQ_HZ / 1000)
+#define PK_BASE_FREQ_MHZ    (PK_BASE_FREQ_HZ / 1000000)
+
+/// Scale a time interval to be _closer_ to what was actually requested
+/// base on the actual timebase frequency.
+#define PK_INTERVAL_SCALE(interval) ((interval) + ((interval) >> __pk_timebase_rshift))
+
+/// Convert a time in integral seconds to a time interval - overflows are
+/// ignored. The application can redefine this macro.
+
+#ifndef PK_SECONDS
+    #define PK_SECONDS(s) ((PkInterval)(PK_BASE_FREQ_HZ * (s)))
+#endif
+
+/// Convert a time in integral milliseconds to a time interval - overflows are
+/// ignored, and a frequency evenly (or closely) divisible by 1000 is
+/// assumed. The application can redefine this macro.
+
+#ifndef PK_MILLISECONDS
+    #define PK_MILLISECONDS(m) ( (PkInterval)(PK_BASE_FREQ_KHZ * (m)) )
+#endif
+
+/// Convert a time in integral microseconds to a time interval - overflows are
+/// ignored, and a frequncy evenly (or closely) divisible by 1,000,000 is
+/// assumed. The application can redefine this macro.
+
+#ifndef PK_MICROSECONDS
+    #define PK_MICROSECONDS(u)  ( (PkInterval)(PK_BASE_FREQ_MHZ * (u)) )
+#endif
+
+/// Convert a time in integral nanoseconds to a time interval - overflows are
+/// ignored, and a frequeyncy evenly (or closely) divisible by 1,000,000 is
+/// assumed. The application can redefine this macro.
+
+#ifndef PK_NANOSECONDS
+    #define PK_NANOSECONDS(n) ( (PkInterval)( ( ((PK_BASE_FREQ_MHZ<<10)/1000) * (n) ) >> 10) )
+#endif
+
+
+/// Enable PK application tracing (enabled by default)
+#ifndef PK_TRACE_ENABLE
+    #define PK_TRACE_ENABLE 1
+#endif
+
+/// Enable PK crit  (disabled by default)
+#ifndef PK_TRACE_CRIT_ENABLE
+    #define PK_TRACE_CRIT_ENABLE 0
+#endif
+
+/// Enable Debug suppress  (disabled by default)
+// a.k.a. enabled means turn off PK_TRACE(), but keep crit trace
+#ifndef PK_TRACE_DBG_SUPPRESS
+    #define PK_TRACE_DBG_SUPPRESS 0
+#endif
+
+/// Enable PK kernel tracing (disabled by default)
+#ifndef PK_KERNEL_TRACE_ENABLE
+    #define PK_KERNEL_TRACE_ENABLE 0
+#endif
+
+/// pk trace disabled implies no tracing at all
+//   override any other trace settings
+#if !PK_TRACE_ENABLE
+    #undef PK_TRACE_DBG_SUPPRESS
+    #undef PK_TRACE_CRIT_ENABLE
+
+    #define PK_TRACE_DBG_SUPPRESS 1
+    #define PK_TRACE_CRIT_ENABLE 0
+#endif
+
+// PK TRACE enabled & PK CRIT enabled implies all tracing on.
+// PK TRACE enabled & PK DBUG disabled implies   PK CRIT INFO tracing only.
+// PK TRACE enable & pK CRIT INFO disabled  && PK DBUG disabled implies
+//          PK TRACE disabled
+#if PK_TRACE_ENABLE &&  PK_TRACE_DBG_SUPPRESS && !PK_TRACE_CRIT_ENABLE
+    #undef PK_TRACE_ENABLE
+    #define PK_TRACE_ENABLE 0
+#endif
+
+
+//Application trace macros
+#if PK_TRACE_DBG_SUPPRESS
+    #define PK_TRACE(...)
+    #define PK_TRACE_BIN(str, bufp, buf_size)
+#else
+    #define PK_TRACE(...) PKTRACE(__VA_ARGS__)
+    #define PK_TRACE_BIN(str, bufp, buf_size) PKTRACE_BIN(str, bufp, buf_size)
+#endif
+
+#if !PK_TRACE_CRIT_ENABLE
+    #define PK_TRACE_INF(...)
+#else
+    #define PK_TRACE_INF(...) PKTRACE(__VA_ARGS__)
+#endif
+
+//Kernel trace macros
+#if !PK_KERNEL_TRACE_ENABLE
+    #define PK_KERN_TRACE(...)
+    #define PK_KERN_TRACE_ASM16(...)
+#else
+    #define PK_KERN_TRACE(...) PK_TRACE(__VA_ARGS__)
+    #define PK_KERN_TRACE_ASM16(...) PK_TRACE_ASM16(__VA_ARGS__)
+#endif  /* PK_KERNEL_TRACE_ENABLE */
+
+
+/// Add a string to the trace buffer with an optional register holding a 16bit value
+/// WARNING: This calls a c function which may clobber any of the volatile registers
+#if (PK_TRACE_SUPPORT && PK_TIMER_SUPPORT)
+    #define PK_TRACE_ASM16(...) TRACE_ASM_HELPER16(VARG_COUNT(__VA_ARGS__), __VA_ARGS__)
+#else
+    #define PK_TRACE_ASM16(...)
+#endif /* PK_TRACE_SUPPORT */
+
+/// The following macros are helper macros for tracing.  They should not be called
+/// directly.
+#define VARG_COUNT_HELPER(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N
+#define VARG_COUNT(...) VARG_COUNT_HELPER(, ##__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0)
+
+#ifdef __ASSEMBLER__
+// *INDENT-OFF*
+#define TRACE_ASM_HELPER16_CALL(count, ...) TINY_TRACE_ASM ## count (__VA_ARGS__)
+#define TRACE_ASM_HELPER16(count, ...) TRACE_ASM_HELPER16_CALL(count, __VA_ARGS__)
+
+#define TINY_TRACE_ASM0()   .error "format string required"
+#define TINY_TRACE_ASM1(str) \
+    .tiny_trace_asm1 trace_ppe_hash(str, PK_TRACE_HASH_PREFIX)
+#define TINY_TRACE_ASM2(str, reg) \
+    .tiny_trace_asm2 trace_ppe_hash(str, PK_TRACE_HASH_PREFIX), reg
+#define TINY_TRACE_ASM3()   .error "too many parameters"
+#define TINY_TRACE_ASM4()   .error "too many parameters"
+#define TINY_TRACE_ASM5()   .error "too many parameters"
+#define TINY_TRACE_ASM6()   .error "too many parameters"
+#define TINY_TRACE_ASM7()   .error "too many parameters"
+
+//Possible enhancement: add support for tracing more than 1 parameter and binary data in assembly
+
+    .global pk_trace_tiny
+
+    .macro  .tiny_trace_asm1 hash16
+        lis     %r3, \hash16
+        bl      pk_trace_tiny
+    .endm
+
+    .macro .tiny_trace_asm2 hash16, parm16
+        clrlwi  %r3, \parm16, 16
+        oris    %r3, %r3, \hash16
+        bl      pk_trace_tiny
+    .endm
+
+// *INDENT-ON*
+#endif /*__ASSEMBLER__*/
+
+
+
+#ifndef __ASSEMBLER__
+
+#include <stddef.h>
+#include <stdint.h>
+
+/// The timebase frequency in Hz; A parameter to pk_initialize()
+extern uint32_t __pk_timebase_frequency_hz;
+
+extern uint8_t __pk_timebase_rshift;
+
+/// The timebase frequency in KHz
+extern uint32_t __pk_timebase_frequency_khz;  //never set or used. Delete?
+
+/// The timebase frequency in Mhz
+extern uint32_t __pk_timebase_frequency_mhz;  //never set or used. Delete?
+
+
+typedef unsigned long int PkAddress;
+
+typedef uint8_t PkThreadState;
+
+typedef uint8_t PkThreadPriority;
+
+typedef uint8_t PkThreadFlags;
+
+typedef uint32_t PkSemaphoreCount;
+
+typedef uint64_t PkTimebase;
+
+typedef PK_TIME_INTERVAL_TYPE PkInterval;
+
+#include "pk_port_types.h"
+
+typedef struct
+{
+
+    /// A priority queue of threads pending on the semaphore.
+    PkThreadQueue pending_threads;
+
+    /// The current semaphore count.
+    PkSemaphoreCount count;
+
+    /// The maximum allowable count - for error checking.
+    PkSemaphoreCount max_count;
+
+} PkSemaphore;
+
+
+/// Compile-time initialize a PkSemaphore structure
+///
+/// This low-level macro creates a structure initializatin of an PkSemaphore
+/// structure. This can be used for example to create compile-time initialized
+/// arrays of semaphores.
+#define PK_SEMAPHORE_INITIALIZATION(_initial_count, _max_count)        \
+    {.pending_threads = 0,                                              \
+                        .count = (_initial_count),                                  \
+                                 .max_count = (_max_count)}
+
+
+/// Declare and initialize a semaphore
+#define PK_SEMAPHORE(sem, initial_count, max_count)                    \
+    PkSemaphore sem = PK_SEMAPHORE_INITIALIZATION(initial_count, max_count)
+
+
+/// Trace macros for C functions
+#define HASH_ARG_COMBO(str, arg) \
+    ((((uint32_t)trace_ppe_hash(str, PK_TRACE_HASH_PREFIX)) << 16) | ((uint32_t)(arg) & 0x0000ffff))
+
+#define PKTRACE0(...) pk_trace_tiny() //will fail at compile time
+
+#define PKTRACE1(str) \
+    pk_trace_tiny((trace_ppe_hash(str, PK_TRACE_HASH_PREFIX) << 16))
+
+#define PKTRACE2(str, parm0) \
+    ((sizeof(parm0) <= 2)? \
+     pk_trace_tiny(HASH_ARG_COMBO(str, parm0)): \
+     pk_trace_big(HASH_ARG_COMBO(str, 1), ((uint64_t)parm0) << 32, 0))
+
+#define PKTRACE3(str, parm0, parm1) \
+    pk_trace_big(HASH_ARG_COMBO(str, 2), ((((uint64_t)parm0) << 32) | parm1), 0)
+
+#define PKTRACE4(str, parm0, parm1, parm2) \
+    pk_trace_big(HASH_ARG_COMBO(str, 3), ((((uint64_t)parm0) << 32) | parm1),\
+                 ((uint64_t)parm2) << 32 )
+
+#define PKTRACE5(str, parm0, parm1, parm2, parm3) \
+    pk_trace_big(HASH_ARG_COMBO(str, 4), ((((uint64_t)parm0) << 32) | parm1),\
+                 ((((uint64_t)parm2) << 32) | parm3) )
+
+#define PKTRACE6(...) pk_trace_tiny() //will fail at compile time
+#define PKTRACE7(...) pk_trace_tiny() //will fail at compile time
+
+#define PKTRACE_HELPER2(count, ...) PKTRACE ## count (__VA_ARGS__)
+#define PKTRACE_HELPER(count, ...) PKTRACE_HELPER2(count, __VA_ARGS__)
+
+#if (PK_TRACE_SUPPORT && PK_TIMER_SUPPORT)
+#define PKTRACE(...) PKTRACE_HELPER(VARG_COUNT(__VA_ARGS__), __VA_ARGS__)
+#define PKTRACE_BIN(str, bufp, buf_size) \
+    pk_trace_binary(((buf_size < 255)? HASH_ARG_COMBO(str, buf_size): HASH_ARG_COMBO(str, 255)), bufp)
+#else
+#define PKTRACE(...)
+#define PKTRACE_BIN(str, bufp, buf_size)
+#endif //PK_TRACE_SUPPORT
+
+
+
+/// A generic doubly-linked list object
+///
+/// This object functions both as a sentinel mode for a deque as well as a
+/// pointer container for elements in deques.  The PK API assumes that
+/// queueable structures will be defined with an PkDeque structure as the
+/// initial 'data member' of the structure.  This allows a pointer to a queue
+/// element to be cast to a pointer to an PkDeque and vice-versa.
+
+typedef struct PkDeque
+{
+
+    /// Pointer to the head or the next element in a deque.
+    ///
+    /// When an PkDeque is used as the sentinel node for a queue, \a next
+    /// points to the head of the queue, and the condition (next == \<self\>)
+    /// indicates an empty PkDeque. By convention the condition (\a next ==
+    /// 0) is used to indicate that a queue element is not enqueued.
+    struct PkDeque* next;
+
+    /// Pointer to the tail or previous element in a deque.
+    ///
+    /// When a DQueue is used as the sentinel node for a queue, \a previous
+    /// points to the tail of the queue.
+    struct PkDeque* previous;
+
+} PkDeque;
+
+
+typedef void (*PkTimerCallback)(void*);
+
+#define PK_TIMER_CALLBACK(callback) void callback(void *)
+
+struct PkTimer;
+
+/// The PK timer object
+
+typedef struct PkTimer
+{
+
+    /// The time queue management pointers
+    ///
+    /// This pointer container is defined as the first element of the
+    /// structure to allow the PkTimer to be cast to an PkDeque and
+    /// vice-versa.
+    PkDeque deque;
+
+    /// The absolute timeout of the timer.
+    PkTimebase timeout;
+
+    /// The timer callback
+    ///
+    /// For PK thread timers used to implement Sleep and semaphore pend
+    /// timeouts this field is initialized to __pk_thread_timeout().
+    PkTimerCallback callback;
+
+    /// Private data passed to the callback.
+    ///
+    /// For PK thread timers used to implement Sleep and semaphore pend this
+    /// field is initialized to a pointer to the thread.
+    void* arg;
+
+} PkTimer;
+
+
+// Threads
+
+typedef void (*PkThreadRoutine)(void* arg);
+
+#define PK_THREAD_ROUTINE(f) void f(void *arg);
+
+typedef struct
+{
+
+    /// Stack pointer saved during context switches.  Assembler code expects
+    /// this to always be at address offset 0 from the thread pointer.
+    PkAddress saved_stack_pointer;
+
+    /// This is 1 past the last valid byte address of the thread stack.
+    /// Assembler code expects this to always be at address offset (sizeof
+    /// PkAddress) from the thread pointer.
+    PkAddress stack_limit;
+
+    /// This is the original base of the stack.
+    /// Assembler code expects this to always be at address offset 2 * (sizeof
+    /// PkAddress) from the thread pointer.
+    PkAddress stack_base;
+
+    /// If the thread is blocked on a semaphore, then this is the semaphore the
+    /// thread is blocked on.
+    PkSemaphore* semaphore;
+
+    /// The thread priority.
+    PkThreadPriority priority;
+
+    /// The thread state; See \ref pk_thread_states
+    PkThreadState state;
+
+    /// Thread flags; See \ref pk_thread_flags
+    PkThreadFlags flags;
+
+    /// The timer structure handles Sleep and blocking on a semaphore with
+    /// timeout.
+    PkTimer timer;
+
+} PkThread;
+
+
+typedef void (*PkBhHandler)(void*);
+
+#define PK_BH_HANDLER(handler) void handler(void *)
+
+typedef struct
+{
+
+    /// The bottom half queue management pointers
+    ///
+    /// This pointer container is defined as the first element of the
+    /// structure to allow the PkBottomHalf to be cast to a PkDeque and
+    /// vice-versa.
+    PkDeque deque;
+
+    /// The bottom half handler
+    PkBhHandler bh_handler;
+
+    /// Private data passed to the handler.
+    void* arg;
+
+} PkBottomHalf;
+
+
+// Initialization APIs
+
+int
+pk_initialize(PkAddress  kernel_stack,
+              size_t      kernel_stack_size,
+              PkTimebase initial_timebase,
+              uint32_t    timebase_frequency_hz);
+
+/**
+ * Set the timebase frequency.
+ * @param[in] The frequency in HZ
+ * @return PK_OK
+ * @pre  pk_initialize
+ * @Note This interface is intended for SBE. The timebase frequency value is
+ *       used by PK to calcate timed events. Any existing timeouts,
+ *       sleeps, or time based pending semaphores are not recalculated.
+ */
+int
+pk_timebase_freq_set(uint32_t timebase_frequency_hz);
+
+// Timebase APIs
+
+PkTimebase
+pk_timebase_get(void);
+
+
+// Timer APIs
+
+int
+pk_timer_create(PkTimer*         timer,
+                PkTimerCallback callback,
+                void*             arg);
+
+
+int
+pk_timer_schedule(PkTimer*    timer,
+                  PkInterval interval);
+
+int
+pk_timer_cancel(PkTimer* timer);
+
+int
+pk_timer_info_get(PkTimer*    timer,
+                  PkTimebase* timeout,
+                  int*         active);
+
+// Thread APIs
+
+int
+pk_thread_create(PkThread*         thread,
+                 PkThreadRoutine  thread_routine,
+                 void*              arg,
+                 PkAddress        stack,
+                 size_t            stack_size,
+                 PkThreadPriority priority);
+
+int
+pk_start_threads(void);
+
+int
+pk_thread_resume(PkThread* thread);
+
+int
+pk_thread_suspend(PkThread* thread);
+
+int
+pk_thread_delete(PkThread* thread);
+
+int
+pk_complete(void);
+
+int
+pk_sleep(PkInterval interval);
+
+int
+pk_thread_info_get(PkThread*         thread,
+                   PkThreadState*    state,
+                   PkThreadPriority* priority,
+                   int*               runnable);
+
+int
+pk_thread_priority_change(PkThread*         thread,
+                          PkThreadPriority new_priority,
+                          PkThreadPriority* old_priority);
+
+int
+pk_thread_at_priority(PkThreadPriority priority,
+                      PkThread**         thread);
+
+int
+pk_thread_priority_swap(PkThread* thread_a, PkThread* thread_b);
+
+
+// Semaphore APIs
+
+int
+pk_semaphore_create(PkSemaphore*      semaphore,
+                    PkSemaphoreCount initial_count,
+                    PkSemaphoreCount max_count);
+
+int
+pk_semaphore_post(PkSemaphore* semaphore);
+
+int
+pk_semaphore_pend(PkSemaphore* semaphore,
+                  PkInterval  timeout);
+
+int
+pk_semaphore_release_all(PkSemaphore* semaphore);
+
+
+int
+pk_semaphore_info_get(PkSemaphore*      semaphore,
+                      PkSemaphoreCount* count,
+                      int*               pending);
+
+void
+pk_semaphore_post_handler(void* arg,
+                          PkIrqId irq);
+
+// Misc. APIs
+
+void
+pk_halt() __attribute__ ((noreturn));
+
+// Deque APIs
+
+int
+pk_deque_sentinel_create(PkDeque* deque);
+
+#define PK_DEQUE_SENTINEL_INIT(dq_addr) \
+    {\
+        .next = dq_addr, \
+                .previous = dq_addr \
+    }
+
+#define PK_DEQUE_SENTINEL_STATIC_CREATE(deque) \
+    PkDeque deque = PK_DEQUE_SENTINEL_INIT(&deque)
+
+int
+pk_deque_element_create(PkDeque* element);
+
+#define PK_DEQUE_ELEMENT_INIT() \
+    {\
+        .next = 0, \
+                .previous = 0 \
+    }
+
+#define PK_DEQUE_ELEMENT_STATIC_CREATE(deque) \
+    PkDeque deque = PK_DEQUE_ELEMENT_INIT()
+
+/// Check for an empty PkDeque
+///
+/// \param deque The sentinel node of a deque
+///
+/// \retval 0 The PkDeque is not empty
+///
+/// \retval 1 The PkDeque is empty
+
+static inline int
+pk_deque_is_empty(PkDeque* deque)
+{
+    return (deque == deque->next);
+}
+
+
+/// Check if an PkDeque element is currently enqueued
+///
+/// \param element Typically the PkDeque object of a queable structure
+///
+/// \retval 0 The element is not currently enqueued
+///
+/// \retval 1 The element is currently enqueued
+
+static inline int
+pk_deque_is_queued(PkDeque* element)
+{
+    return (element->next != 0);
+}
+
+
+/// Append an element to the tail of a deque (FIFO order)
+///
+/// \param deque The sentinel node of a deque
+///
+/// \param element Typically the PkDeque object of a queable structure
+///
+/// It is an error to call this API on an element that is already enqueued,
+/// but the API does not check for this error.
+
+static inline void
+pk_deque_push_back(PkDeque* deque, PkDeque* element)
+{
+    deque->previous->next = element;
+    element->previous = deque->previous;
+    element->next = deque;
+    deque->previous = element;
+}
+
+
+/// Push an element at the head of a deque (LIFO order)
+///
+/// \param deque The sentinel node of a deque
+///
+/// \param element Typically the PkDeque object of a queable structure
+///
+/// It is an error to call this API on an element that is already enqueued,
+/// but the API does not check for this error.
+
+static inline void
+pk_deque_push_front(PkDeque* deque, PkDeque* element)
+{
+    deque->next->previous = element;
+    element->next = deque->next;
+    element->previous = deque;
+    deque->next = element;
+}
+
+/// Pop an element from the head of a deque
+///
+/// \param deque The sentinel node of a deque
+///
+/// \retval 0 The PkDeque was empty prior to the call
+///
+/// \retval non-0 A pointer to the previous head of the deque, which has been
+/// removed from the deque and marked as no longer queued.
+
+// The cast of 'head' is used to remove the 'volatile' attribute.
+
+static inline PkDeque*
+pk_deque_pop_front(PkDeque* deque)
+{
+    PkDeque* head;
+
+    if (pk_deque_is_empty(deque))
+    {
+        return 0;
+    }
+    else
+    {
+        head = (PkDeque*)(deque->next);
+        deque->next = head->next;
+        deque->next->previous = deque;
+        head->next = 0;
+        return head;
+    }
+}
+
+
+/// Remove a deque element from any position in the deque
+///
+/// \param element Typically the PkDeque object of a queable structure
+///
+/// It is an error to call this API on an element that is not currently
+/// enqueued, but the API does not check for this error.
+
+static inline void
+pk_deque_delete(PkDeque* element)
+{
+    element->previous->next = element->next;
+    element->next->previous = element->previous;
+    element->next = 0;
+}
+
+// Bottom Half APIs
+
+extern PkDeque _pk_bh_queue;
+
+static inline void
+pk_bh_schedule(PkBottomHalf* bottom_half)
+{
+    pk_deque_push_back(&_pk_bh_queue, (PkDeque*)bottom_half);
+}
+
+#define PK_BH_INIT(_handler, _arg) \
+    {\
+        .deque = PK_DEQUE_ELEMENT_INIT(), \
+                 .bh_handler = _handler, \
+                               .arg = _arg \
+    }
+
+#define PK_BH_STATIC_CREATE(bh_name, handler, arg) \
+    PkBottomHalf bh_name = PK_BH_INIT(handler, arg)
+
+
+//Trace function prototypes
+void pk_trace_tiny(uint32_t i_parm);
+void pk_trace_big(uint32_t i_hash_and_count,
+                  uint64_t i_parm1, uint64_t i_parm2);
+void pk_trace_binary(uint32_t i_hash_and_size, void* bufp);
+void pk_trace_set_timebase(PkTimebase timebase);
+
+
+/// Cast a pointer to another type, in a way that won't cause warnings
+
+#define PK_CAST_POINTER(t, p) ((t)((PkAddress)(p)))
+
+// Static Assert Macro for Compile time assertions.
+//   - This macro can be used both inside and outside of a function.
+//   - A value of false will cause the ASSERT to produce this error
+//   - This will show up on a compile fail as:
+//      <file>:<line> error: size of array '_static_assert' is negative
+//   - It would be trivial to use the macro to paste a more descriptive
+//     array name for each assert, but we will leave it like this for now.
+#define PK_STATIC_ASSERT(cond) extern uint8_t _static_assert[(cond) ? 1 : -1]  __attribute__ ((unused))
+
+/// \page pk_errors PK API and Kernel Error Handling
+///
+/// Error checking in the PK API consumes a significant amount of code space.
+/// Approximately 20% of the object code in the PPC405 port is devoted to
+/// error checking. Presumably a like amount of time overhead is also added to
+/// PK API calls by this checking.
+///
+/// API error checking can be disabled to save space and time in the kernel.
+/// API errors can also be configured to cause kernel panics, allowing
+/// applications to be coded without the overhead of error checking but still
+/// providing an escape in the event of application errors or (unlikely)
+/// hardware failures. The PK default is to check for API errors and kernel
+/// invariants, and panic should errors occur.
+///
+/// PK follows the Unix convention that a successful call of an API returns 0
+/// (PK_OK), but returns a negative code in the event of failure, or to
+/// provide further information. The error codes are all defined as manifest
+/// constants.
+///
+/// Some negative codes returned by PK APIs are not considered errors.  These
+/// conditions are always checked, never cause a panic if they occur, and
+/// their interpretation is always left to the application.  See the detailed
+/// documentation for each API for lists of error and non-error codes returned
+/// by the API.
+///
+/// There are three configuration options that control error handling in the
+/// PK API and kernel:
+///
+/// \c PK_ERROR_CHECK_API
+///
+///    \arg \b 0 - No PK API error checking.  APIs that potentially return error
+///    codes will always return 0 (PK_OK) instead of an error code.  Those
+///    APIs that return negative codes that are not errors (see Table 1.5)
+///    always return the negative non-error codes when appropriate.
+///
+///    \arg \b 1 - (Default) All PK API errors are checked.  The behavior in
+///    the event of an error is defined by the configuration option
+///    PK_ERROR_PANIC.
+///
+/// \c PK_ERROR_CHECK_KERNEL
+///
+///   \arg \b 0 - No kernel invariant error checking is done.
+///
+///   \arg \b 1 - (Default) Selected kernel invariants are checked.  The overhead
+///   for these checks should be  minimal.
+///
+/// \c PK_ERROR_PANIC
+///
+///  \arg \b 0 - PK API calls return negative error codes in the event of
+///  errors. Note that PK kernel invariants always cause a panic if
+///  violations occur.
+///
+///  \arg \b 1 - (Default) In the event of errors PK APIs invoke PK_PANIC(code),
+///  where code is a positive error code.  Kernel invariant checks always
+///  cause a panic if violations are detected.
+
+#endif  /* __ASSEMBLER__ */
+
+#endif  /* __PK_API_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_bh_core.c b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_bh_core.c
new file mode 100644
index 00000000..734d529c
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_bh_core.c
@@ -0,0 +1,55 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_bh_core.c $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_bh_core.c
+/// \brief PK bottom half APIs
+///
+///  The entry points in this file are considered 'core' routines that will
+///  always be present at runtime in any PK application.
+
+#include "pk.h"
+
+/// Statically initialize the bottom half queue
+PK_DEQUE_SENTINEL_STATIC_CREATE(_pk_bh_queue);
+
+void _pk_process_bh(void)
+{
+    PkBottomHalf* bh;
+
+    while((bh = (PkBottomHalf*)pk_deque_pop_front(&_pk_bh_queue)) != 0)
+    {
+        bh->bh_handler(bh->arg);
+    }
+
+    return;
+}
+
+
+#undef __PK_THREAD_CORE_C__
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_core.c b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_core.c
new file mode 100644
index 00000000..2f91d94e
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_core.c
@@ -0,0 +1,105 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_core.c $          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_core.c
+/// \brief Core routines for the PK kernel.
+///
+///  The entry points in this file are routines that are expected to be needed
+///  at runtime by all PK applications.  This file also serves as a place for
+///  kernel global variables to be realized.
+
+#define __PK_CORE_C__
+
+#include "pk.h"
+
+#if !PK_TIMER_SUPPORT
+
+/// If there is no timer support, then any call of the timer interrupt handler
+/// is considered a fatal error.
+
+void
+__pk_timer_handler()
+{
+    PK_PANIC(PK_NO_TIMER_SUPPORT);
+}
+
+#endif  /* PK_TIMER_SUPPORT */
+
+
+/// Initialize an PkDeque sentinel node
+///
+/// \param deque The sentinel node of the deque
+///
+/// PK has no way of knowing whether the \a deque is currently in use, so
+/// this API must only be called on unitialized or otherwise unused sentinel
+/// nodes.
+///
+/// \retval 0 success
+///
+/// \retval -PK_INVALID_DEQUE_SENTINEL The \a deque pointer was null
+
+int
+pk_deque_sentinel_create(PkDeque* deque)
+{
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(deque == 0, PK_INVALID_DEQUE_SENTINEL);
+    }
+
+    deque->next = deque->previous = deque;
+    return 0;
+}
+
+
+/// Initialize an PkDeque element
+///
+/// \param element Typically the PkDeque object of a queable structure
+///
+/// PK has no way of knowing whether the \a element is currently in use, so
+/// this API must only be called on unitialized or otherwise unused deque
+/// elements.
+///
+/// \retval 0 success
+///
+/// \retval -PK_INVALID_DEQUE_ELEMENT The \a element pointer was null
+
+int
+pk_deque_element_create(PkDeque* element)
+{
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(element == 0, PK_INVALID_DEQUE_ELEMENT);
+    }
+
+    element->next = 0;
+    return 0;
+}
+
+#undef __PK_CORE_C__
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_debug_ptrs.c b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_debug_ptrs.c
new file mode 100644
index 00000000..76a05508
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_debug_ptrs.c
@@ -0,0 +1,77 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_debug_ptrs.c $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_debug_ptrs.c
+/// \brief Defines a table of pointers to important kernel debug data.
+///
+/// This table is placed in a special section named .debug_ptrs which can be
+/// placed at a well-known memory location for tools to find.
+///
+
+#include "pk.h"
+#include "pk_trace.h"
+#include "pk_debug_ptrs.h"
+
+extern PkTimebase  ppe42_64bit_timebase;
+
+#if PK_TRACE_SUPPORT
+    extern PkTraceBuffer g_pk_trace_buf;
+#endif
+
+pk_debug_ptrs_t pk_debug_ptrs SECTION_ATTRIBUTE(".debug_ptrs") =
+{
+    .debug_ptrs_size            = sizeof(pk_debug_ptrs),
+    .debug_ptrs_version         = PK_DEBUG_PTRS_VERSION,
+
+#if PK_TRACE_SUPPORT
+    .debug_trace_ptr            = &g_pk_trace_buf,
+    .debug_trace_size           = sizeof(g_pk_trace_buf),
+#else
+    .debug_trace_ptr            = 0,
+    .debug_trace_size           = 0,
+#endif /* PK_TRACE_SUPPORT */
+
+#if PK_THREAD_SUPPORT
+    .debug_thread_table_ptr     = &__pk_priority_map,
+    .debug_thread_table_size    = sizeof(__pk_priority_map),
+    .debug_thread_runq_ptr      = (void*)& __pk_run_queue,
+    .debug_thread_runq_size     = sizeof(__pk_run_queue),
+#else
+    .debug_thread_table_ptr     = 0,
+    .debug_thread_table_size    = 0,
+    .debug_thread_runq_ptr      = 0,
+    .debug_thread_runq_size     = 0,
+#endif /* PK_THREAD_SUPPORT */
+
+    .debug_timebase_ptr         = &ppe42_64bit_timebase,
+    .debug_timebase_size        = sizeof(ppe42_64bit_timebase),
+
+};
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_debug_ptrs.h b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_debug_ptrs.h
new file mode 100644
index 00000000..02ef948d
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_debug_ptrs.h
@@ -0,0 +1,63 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_debug_ptrs.h $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PK_DEBUG_PTRS_H__
+#define __PK_DEBUG_PTRS_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_debug_ptrs.h
+/// \brief Structure for a table of pointers to kernel debug data
+///
+
+#define PK_DEBUG_PTRS_VERSION  1
+
+typedef struct
+{
+    // The size and version of this structure
+    unsigned short   debug_ptrs_size;
+    unsigned short   debug_ptrs_version;
+
+    // Trace buffer location and size
+    void*           debug_trace_ptr;
+    unsigned long   debug_trace_size;
+
+    // Thread table location and size
+    void*           debug_thread_table_ptr;
+    unsigned long   debug_thread_table_size;
+
+    // Thread run queue location and size
+    void*           debug_thread_runq_ptr;
+    unsigned long   debug_thread_runq_size;
+
+    // Emulated timebase location and size
+    void*           debug_timebase_ptr;
+    unsigned long   debug_timebase_size;
+
+} pk_debug_ptrs_t;
+
+#endif /*__PK_DEBUG_PTRS_H__*/
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_init.c b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_init.c
new file mode 100644
index 00000000..056bf270
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_init.c
@@ -0,0 +1,240 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_init.c $          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_init.c
+/// \brief PK initialization
+///
+/// The entry points in this file are initialization routines - they are never
+/// needed after PK initialization and their code space could be reclaimed by
+/// the application after initialization if required.
+
+#include "pk.h"
+#include "pk_trace.h"
+
+uint32_t __pk_timebase_frequency_hz;
+
+/// The timebase frequency is passed into PK during initialization.  It cannot
+/// be set statically because there is a requirement to support a frequency
+/// that can change from one IPL to the next.  On the 405, scaling of time
+/// intervals is accomplished by doing a 32x32 bit multiplication which is
+/// supported by the ppc405 instruction set.  PPE42 does not support 32x32 bit
+/// multiplication directly and some applications can not afford to use a
+/// function call to emulate the operation.  Instead we scale the time
+/// interval by shifting the value X bits to the right and adding it to itself.
+/// This can scale the value by 2, 1.5, 1.25, 1.125, etc.
+///
+/// This is the right shift value.
+/// NOTE: shifting by 0 gives a 2x scale factor, shifting by 32 gives a 1x
+/// scale factor.
+uint8_t  __pk_timebase_rshift = 32;
+
+void pk_set_timebase_rshift(uint32_t timebase_freq_hz)
+{
+    //Use 1.0 scale if less than halfway between 1.0 and 1.25
+    if(timebase_freq_hz <= (PK_BASE_FREQ_HZ + (PK_BASE_FREQ_HZ >> 3)))
+    {
+        __pk_timebase_rshift = 32;
+    }
+
+    //use 1.25 scale if less than halfway between 1.25 and 1.5
+    else if(timebase_freq_hz <= (PK_BASE_FREQ_HZ + (PK_BASE_FREQ_HZ >> 3) + (PK_BASE_FREQ_HZ >> 2)))
+    {
+        __pk_timebase_rshift = 2;
+    }
+    //use 1.5 scale if less than halfway between 1.5 and 2.0
+    else if(timebase_freq_hz <= (PK_BASE_FREQ_HZ + (PK_BASE_FREQ_HZ >> 2) + (PK_BASE_FREQ_HZ >> 1)))
+    {
+        __pk_timebase_rshift = 1;
+    }
+    //use 2.0 scale if greater than 1.5
+    else
+    {
+        __pk_timebase_rshift = 0;
+    }
+}
+
+/// Initialize PK.
+///
+/// \param kernel_stack A stack area for interrupt and bottom-half handlers.
+///
+/// \param kernel_stack_size The size (in bytes) of the stack area for
+/// interrupt and bottom-half handlers.
+///
+/// \param initial_timebase The initial value of the PK timebase.
+/// If the argument is given as the special value \c PK_TIMEBASE_CONTINUES, then the
+/// timebase is not reset.
+///
+/// \param timebase_frequency_hz The frequency of the PK timebase in Hz.
+///
+/// This routine \e must be called before any other PK / routines, and \e
+/// should be called before any interrupts are enabled.
+///
+/// Return values other than PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_INVALID_ARGUMENT_INIT A stack pointer is 0 or is given
+/// a 0 size.
+///
+/// \retval -PK_STACK_OVERFLOW One or both stacks are not large enough to
+/// support a minimum context save in the event of an interrupt.
+
+// Note that PK does not rely on any static initialization of dynamic
+// variables. In debugging sessions using RAM-resident PK images it is
+// assumed that the processor may be reset at any time, so we always need to
+// reset everything at initialization.
+
+int
+pk_initialize(PkAddress     kernel_stack,
+              size_t       kernel_stack_size,
+              PkTimebase   initial_timebase,
+              uint32_t     timebase_frequency_hz)
+{
+    int rc;
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF((kernel_stack == 0) ||
+                    (kernel_stack_size == 0),
+                    PK_INVALID_ARGUMENT_INIT);
+    }
+
+    __pk_timebase_frequency_hz = timebase_frequency_hz;
+
+    __pk_thread_machine_context_default = PK_THREAD_MACHINE_CONTEXT_DEFAULT;
+
+    //set the shift adjustment to get us closer to the true
+    //timebase frequency (versus what was hardcoded)
+    pk_set_timebase_rshift(timebase_frequency_hz);
+
+    rc = __pk_stack_init(&kernel_stack, &kernel_stack_size);
+
+    if (rc)
+    {
+        return rc;
+    }
+
+    __pk_kernel_stack = kernel_stack;
+    __pk_kernel_stack_size = kernel_stack_size;
+
+#if PK_TIMER_SUPPORT
+
+    // Initialize the time queue sentinel as a circular queue, set the next
+    // timeout and clear the cursor.
+
+    pk_deque_sentinel_create((PkDeque*)&__pk_time_queue);
+    __pk_time_queue.cursor = 0;
+    __pk_time_queue.next_timeout = PK_TIMEBASE_MAX;
+
+#if PK_TRACE_SUPPORT
+    extern PkTimer       g_pk_trace_timer;
+    extern PkTraceBuffer g_pk_trace_buf;
+
+    //set the trace timebase HZ
+    g_pk_trace_buf.hz = timebase_frequency_hz;
+
+    if(initial_timebase != PK_TIMEBASE_CONTINUES)
+    {
+        //set the timebase ajdustment for trace synchronization
+        pk_trace_set_timebase(initial_timebase);
+    }
+
+    // Schedule the timer that puts a 64bit timestamp in the trace buffer
+    // periodically.  This allows us to use 32bit timestamps.
+    pk_timer_schedule(&g_pk_trace_timer,
+                      PK_TRACE_TIMER_PERIOD);
+
+#endif  /* PK_TRACE_SUPPORT */
+
+#endif  /* PK_TIMER_SUPPORT */
+
+#if PK_THREAD_SUPPORT
+
+    // Clear the priority map. The final entry [PK_THREADS] is for the idle
+    // thread.
+
+    int i;
+
+    for (i = 0; i <= PK_THREADS; i++)
+    {
+        __pk_priority_map[i] = 0;
+    }
+
+    // Initialize the thread scheduler
+
+    __pk_thread_queue_clear(&__pk_run_queue);
+    __pk_current_thread = 0;
+    __pk_next_thread    = 0;
+    __pk_delayed_switch = 0;
+
+#endif  /* PK_THREAD_SUPPORT */
+
+    return PK_OK;
+}
+
+
+// Set the timebase frequency.
+int
+pk_timebase_freq_set(uint32_t timebase_frequency_hz)
+{
+    __pk_timebase_frequency_hz = timebase_frequency_hz;
+    pk_set_timebase_rshift(timebase_frequency_hz);
+
+#if PK_TRACE_SUPPORT
+    g_pk_trace_buf.hz = timebase_frequency_hz;
+#endif
+    // Does the initial_timebase need to be reset?
+    return PK_OK;
+}
+
+
+/// Call the application main()
+///
+/// __pk_main() is called from the bootloader.  It's only purpose is to
+/// provide a place for the PK_MAIN_HOOK to be called before main() is
+/// called.
+
+void
+__pk_main(int argc, char** argv)
+{
+    PK_MAIN_HOOK;
+
+    int main(int argc, char** argv);
+    main(argc, argv);
+}
+
+
+
+
+
+
+
+
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_kernel.h b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_kernel.h
new file mode 100644
index 00000000..2afd184f
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_kernel.h
@@ -0,0 +1,271 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_kernel.h $        */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PK_KERNEL_H__
+#define __PK_KERNEL_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_kernel.h
+/// \brief PK portable kernel (non-API) data and data structures
+///
+/// \todo In theory, as long as the critical section entry/exit macros use GCC
+/// memory barriers, we should be able to eliminate all of the 'volatile'
+/// declarations in PK code.  These have been added to the port, so
+/// we should try it.
+
+#ifdef __PK_CORE_C__
+    #define IF__PK_CORE_C__(x) x
+    #define UNLESS__PK_CORE_C__(x)
+#else
+    #define IF__PK_CORE_C__(x)
+    #define UNLESS__PK_CORE_C__(x) x
+#endif
+
+#if PK_MINIMIZE_KERNEL_CODE_SPACE
+    #define IF_PK_MINIMIZE_KERNEL_CODE_SPACE(x) x
+    #define UNLESS_PK_MINIMIZE_KERNEL_CODE_SPACE(x)
+#else
+    #define IF_PK_MINIMIZE_KERNEL_CODE_SPACE(x)
+    #define UNLESS_PK_MINIMIZE_KERNEL_CODE_SPACE(x) x
+#endif
+
+
+#ifndef __ASSEMBLER__
+
+/// This is the stack pointer saved when switching from a thread context to an
+/// interrupt context.
+
+UNLESS__PK_CORE_C__(extern)
+volatile
+PkAddress __pk_saved_sp;
+
+/// The kernel stack; constant once defined by the call of
+/// pk_initialize().
+
+UNLESS__PK_CORE_C__(extern)
+volatile
+PkAddress __pk_kernel_stack;
+
+/// This is the run queue - the queue of mapped runnable tasks.
+UNLESS__PK_CORE_C__(extern)
+volatile
+PkThreadQueue __pk_run_queue;
+
+/// This flag is set by \c __pk_schedule() if a new highest-priority thread
+/// becomes runnable during an interrupt handler.  The context switch will
+/// take place at the end of interrupt processing, and the
+/// interrupt handling code will clear the flag.
+
+UNLESS__PK_CORE_C__(extern)
+volatile
+int __pk_delayed_switch;
+
+/// The currently running thread, or NULL (0) to indicate the idle thread
+///
+/// \a __pk_current_thread holds a pointer to the currently executing
+/// thread.  This pointer will be NULL (0) under the following conditions:
+///
+/// - After pk_initialize() but prior to pk_start_threads()
+///
+/// - After pk_start_threads(), when no threads are runnable.  In this case
+/// the NULL (0) value indicates that the PK idle thread is 'running'.
+///
+/// - After pk_start_threads(), when the current (non-idle) thread has
+/// completed or been deleted.
+///
+/// If \a __pk_current_thread == 0 then there is no requirement to save any
+/// register state on a context switch, either because the PK idle thread has
+/// no permanent context, or because any thread context on the kernel stack is
+/// associated with a deleted thread.
+///
+/// If \a __pk_current_thread != 0 then \a __pk_current_thread is a pointer
+/// to the currently executing thread.  In an interrupt handler \a
+/// pk_current_thread is a pointer to the thread whose context is saved on
+/// the kernel stack.
+UNLESS__PK_CORE_C__(extern)
+volatile
+PkThread* __pk_current_thread;
+
+/// The thread to switch to during the next context switch, or NULL (0).
+///
+/// \a __pk_next_thread is computed by __pk_schedule().  \a
+/// __pk_next_thread holds a pointer to the thread to switch to at the next
+/// context switch.  In a thread context the switch happens immediately if \a
+/// __pk_next_thread == 0 or \a __pk_next_thread != \a __pk_current_thread.
+/// In an interrupt context the check happens at the end of processing all
+/// interrupts.
+///
+/// \a __pk_next_thread may be NULL (0) under the following
+/// conditions:
+///
+/// - After pk_initialize() but prior to pk_start_threads(), assuming no
+/// threads have been made runnable.
+///
+/// - After pk_start_threads(), when no threads are runnable.  In this case
+/// the NULL (0) value indicates that the PK idle thread is the next thread
+/// to 'run'.
+///
+/// If \a __pk_next_thread == 0 then there is no requirement to restore
+/// any register state on a context switch, because the PK idle thread has
+/// no permanent context.
+///
+/// If \a __pk_next_thread != 0 then \a __pk_next_thread is a pointer
+/// to the thread whose context will be restored at the next context switch.
+UNLESS__PK_CORE_C__(extern)
+volatile
+PkThread* __pk_next_thread;
+
+/// The priority of \a __pk_next_thread
+///
+/// If \a __pk_next_thread == 0, the \a __pk_next_priority == PK_THREADS.
+UNLESS__PK_CORE_C__(extern)
+volatile
+PkThreadPriority __pk_next_priority;
+
+/// This variable holds the default thread machine context for newly created
+/// threads. The idle thread also uses this context. This variable is normally
+/// constant after the call of \c pk_initialize().
+
+UNLESS__PK_CORE_C__(extern)
+volatile
+PkMachineContext __pk_thread_machine_context_default;
+
+
+/// The size of the kernel stack (bytes).
+
+UNLESS__PK_CORE_C__(extern)
+volatile
+size_t __pk_kernel_stack_size;
+
+/// This table maps priorities to threads, and contains PK_THREADS + 1
+/// entries. The final entry is for the idle thread and will always be null
+/// after initizlization.
+
+UNLESS__PK_CORE_C__(extern)
+volatile
+PkThread* __pk_priority_map[PK_THREADS + 1];
+
+/// The PK time queue structure
+///
+/// This structure is defined for use by the kernel, however applications
+/// could also use this structure to define their own time queues.
+
+typedef struct
+{
+
+    /// A sentinel node for the time queue.
+    ///
+    /// The time queue is an PkDeque managed as a FIFO queue for queue
+    /// management purpose, although events time out in time order.
+    ///
+    /// This pointer container is defined as the first element of the
+    /// structure to allow the PkTimeQueue to be cast to an PkDeque.
+    PkDeque queue;
+
+    /// The next timeout in absolute time.
+    PkTimebase next_timeout;
+
+    /// A pointer to allow preemption of time queue processing
+    ///
+    /// If non-0, then this is the next timer in the time queue to handle, or
+    /// a pointer to the \a queue object indicating no more timers to handle.
+    ///
+    /// \a cursor != 0 implies that time queue handler is in the midst of
+    /// processing the time queue, but has enabled interrupt preemption for
+    /// processing a timer handler. This means that 1) if the timer pointed to
+    /// by \a cursor is deleted then the cursor must be assigned to the
+    /// next timer in the queue; and 2) if a new timer is scheduled then
+    /// activating the next timeout will be handled by the timer handler.
+    PkDeque* cursor;
+
+} PkTimeQueue;
+
+UNLESS__PK_CORE_C__(extern)
+PkTimeQueue __pk_time_queue;
+
+/// Return a pointer to the PkThread object of the currently running thread,
+/// or NULL (0) if PK is idle or has not been started.
+///
+/// In this API the current thread is not volatile - it will never change
+/// inside application code - thus the 'volatile' is cast away. The PK kernel
+/// does not (must not) use this API.
+
+UNLESS__PK_CORE_C__(extern)
+inline PkThread*
+pk_current(void)
+{
+    return (PkThread*)__pk_current_thread;
+}
+
+/// Schedule the next timeout in a machine-specific way.
+
+void
+__pk_schedule_hardware_timeout(PkTimebase timeout);
+
+/// The thread timeout handler. Portable.
+
+PK_TIMER_CALLBACK(__pk_thread_timeout);
+
+/// Generic stack initialization. Portable.
+
+int
+__pk_stack_init(PkAddress* stack,
+                size_t*     size);
+
+/// Machine-specific thread context initialization.
+
+void
+__pk_thread_context_initialize(PkThread*        thread,
+                               PkThreadRoutine thread_routine,
+                               void*             arg);
+
+/// Machine specific resumption of __pk_next_thread at __pk_next_priority
+/// without saving the current context.
+void
+__pk_next_thread_resume(void);
+
+/// Schedule a timer in the time queue. Portable.
+void
+__pk_timer_schedule(PkTimer* timer);
+
+/// Remove a timer from the time queue. Portable.
+int
+__pk_timer_cancel(PkTimer* timer);
+
+void
+__pk_schedule(void);
+
+
+// Call the application main(). Portable.
+
+void
+__pk_main(int argc, char** argv);
+
+#endif  /* __ASSEMBLER__ */
+
+#endif /* __PK_KERNEL_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_macros.h b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_macros.h
new file mode 100644
index 00000000..61155679
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_macros.h
@@ -0,0 +1,134 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_macros.h $        */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PK_MACROS_H__
+#define __PK_MACROS_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_macros.h
+/// \brief Boilerplate macros for PK
+
+/// This macro encapsulates error handling boilerplate for code that uses the
+/// PK API-type error handling, for errors that do not occur in critical
+/// sections.
+
+#define PK_ERROR(code) \
+    do { \
+        if (PK_ERROR_PANIC) {                  \
+            PK_PANIC(code);                    \
+        } else {                                \
+            return -(code);                     \
+        }                                       \
+    } while (0)
+
+
+/// This macro encapsulates error handling boilerplate in the PK API
+/// functions, for errors that do not occur in critical sections.
+
+#define PK_ERROR_IF(condition, code) \
+    do { \
+        if (condition) {                        \
+            PK_ERROR(code);                    \
+        }                                       \
+    } while (0)
+
+
+/// This macro encapsulates error handling boilerplate in the PK API
+/// functions, for errors that do not occur in critical sections and always
+/// force a kernel panic, indicating a kernel or API bug.
+
+#define PK_PANIC_IF(condition, code)           \
+    do {                                        \
+        if (condition) {                        \
+            PK_PANIC(code);                    \
+        }                                       \
+    } while (0)
+
+
+/// This macro encapsulates error handling boilerplate in the PK API
+/// functions, for errors that do not occur in critical sections.
+/// The error handling will only be enabled when PK_ERROR_CHECK_API
+/// is enabled.
+
+#define PK_ERROR_IF_CHECK_API(condition, code) \
+    do { \
+        if (PK_ERROR_CHECK_API) {              \
+            PK_ERROR_IF(condition, code);       \
+        }                                       \
+    } while (0)
+
+/// This macro encapsulates error handling boilerplate in the PK API
+/// functions, for errors that occur in critical sections.
+
+#define PK_ERROR_IF_CRITICAL(condition, code, context) \
+    do { \
+        if (condition) {                                \
+            if (PK_ERROR_PANIC) {                      \
+                PK_PANIC(code);                        \
+                pk_critical_section_exit(context);     \
+            } else {                                    \
+                pk_critical_section_exit(context);     \
+                return -(code);                         \
+            }                                           \
+        }                                               \
+    } while (0)
+
+
+/// This is a general macro for errors that require cleanup before returning
+/// the error code.
+
+#define PK_ERROR_IF_CLEANUP(condition, code, cleanup) \
+    do { \
+        if (condition) {                        \
+            if (PK_ERROR_PANIC) {              \
+                PK_PANIC(code);                \
+                cleanup;                        \
+            } else {                            \
+                cleanup;                        \
+                return -(code);                 \
+            }                                   \
+        }                                       \
+    } while (0)
+
+
+
+/// Some PK APIs can only be called from thread contexts - these are APIs
+/// that threads call on 'themselves'.
+
+#define PK_ERROR_UNLESS_THREAD_CONTEXT() \
+    PK_ERROR_IF(!__pk_kernel_context_thread(), \
+                PK_ILLEGAL_CONTEXT_THREAD_CONTEXT)
+
+
+/// Some PK APIs must be called from an interrupt context only.
+
+#define PK_ERROR_UNLESS_ANY_INTERRUPT_CONTEXT() \
+    PK_ERROR_IF(!__pk_kernel_context_any_interrupt(), \
+                PK_ILLEGAL_CONTEXT_INTERRUPT_CONTEXT)
+
+#endif /* __PK_MACROS_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_semaphore_core.c b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_semaphore_core.c
new file mode 100644
index 00000000..5b1e3374
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_semaphore_core.c
@@ -0,0 +1,365 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_semaphore_core.c $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_semaphore_core.c
+/// \brief PK semaphore APIs
+///
+///  The entry points in this file are considered 'core' routines that will
+///  always be present at runtime in any PK application that enables
+///  semaphores.
+
+#include "pk.h"
+
+/// Post a count to a semaphore
+///
+/// \param semaphore A pointer to the semaphore
+///
+/// If any thread is pending on the semaphore, the highest priority thread
+/// will be made runnable and the internal count will remain 0.
+///
+/// If no thread is pending on the semaphore then the internal count will be
+/// incremented by 1, with overflow wrapping the internal count through 0. If
+/// the \a max_count argument supplied when the semaphore was created is
+/// non-zero and the new internal count is greater than the \a max_count, an
+/// overflow error will be signalled.
+///
+/// Return values other than PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_INVALID_SEMAPHORE_AT_POST The \a semaphore is a null (0) pointer.
+///
+/// \retval -PK_SEMAPHORE_OVERFLOW The \a max_count argument supplied when
+/// the semaphore was created is non-zero and the new internal count is
+/// greater than the \a max_count.
+
+int
+pk_semaphore_post(PkSemaphore* semaphore)
+{
+    PkMachineContext ctx;
+    PkThreadPriority priority;
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(semaphore == 0, PK_INVALID_SEMAPHORE_AT_POST);
+    }
+
+    pk_critical_section_enter(&ctx);
+
+    priority = __pk_thread_queue_min(&(semaphore->pending_threads));
+
+    if (priority != PK_IDLE_THREAD_PRIORITY)
+    {
+
+        __pk_thread_queue_delete(&(semaphore->pending_threads), priority);
+        __pk_thread_queue_insert(&__pk_run_queue, priority);
+
+        PK_KERN_TRACE("THREAD_SEMAPHORE_POST(%d)", priority);
+
+        __pk_schedule();
+
+    }
+    else
+    {
+
+        semaphore->count++;
+
+        if (PK_ERROR_CHECK_API)
+        {
+            PK_ERROR_IF((semaphore->max_count > 0) &&
+                        (semaphore->count > semaphore->max_count),
+                        PK_SEMAPHORE_OVERFLOW);
+        }
+    }
+
+    pk_critical_section_exit(&ctx);
+
+    return PK_OK;
+}
+
+
+/// Pend on a semaphore with timeout
+///
+/// \param semaphore A pointer to the semaphore
+///
+/// \param timeout A relative timeout in PK timebase ticks, including the
+/// special values PK_NO_WAIT and PK_WAIT_FOREVER
+///
+/// This API is normally called from threads, and can only be successfully
+/// called from interupt handlers under special conditions.
+///
+/// If the internal count of the \a semaphore is non-zero, the internal count
+/// is decremented by one and execution of the caller continues.
+///
+/// If the internal count of the \a semaphore is zero and the \a timeout is
+/// PK_NO_WAIT (0) then the call returns immediately with the informational
+/// code -PK_SEMAPHORE_PEND_NO_WAIT.
+///
+/// If the internal count of the \a semaphore is zero and the \a timeout is
+/// non-zero then a thread will block until either a semaphore count is
+/// acquired or the relative timeout expires.  If this condition occurs in a
+/// call from an interrupt context or before threads have been started then
+/// the call will fail with the error \c -PK_SEMAPHORE_PEND_WOULD_BLOCK.
+///
+/// Once timed out the thread is removed from the semaphore pending queue and
+/// made runnable, and the pk_semaphore_pend() operation will fail, even if
+/// the semaphore count becomes available before the thread runs again. The
+/// pk_semaphore_pend() API returns the informational code
+/// -PK_SEMAPHORE_PEND_TIMED_OUT in this case.
+///
+/// By convention, a timeout interval equal to the maximum possible value of
+/// the \c PkInterval type is taken to mean "wait forever".  A thread blocked
+/// on a semaphore in this mode will never time out. PK provides this
+/// constant as \c PK_WAIT_FOREVER.
+///
+/// Return values other than PK_OK (0) are not necessarily errors; see \ref
+/// pk_errors
+///
+/// The following return codes are non-error codes:
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_SEMAPHORE_PEND_NO_WAIT timeout is set to PK_NO_WAIT
+///
+/// \retval -PK_SEMAPHORE_PEND_TIMED_OUT The semaphore was not acquired
+/// before the timeout expired.
+///
+/// The following return codes are error codes:
+///
+/// \retval -PK_INVALID_SEMAPHORE_AT_PEND The \a semaphore is a null (0)
+/// pointer.
+///
+/// \retval -PK_SEMAPHORE_PEND_WOULD_BLOCK The call was made from an
+/// interrupt context (or before threads have been started), the semaphore
+/// internal count was 0 and a non-zero timeout was specified.
+
+// Note: Casting __pk_current_thread removes the 'volatile' attribute.
+
+int
+pk_semaphore_pend(PkSemaphore* semaphore,
+                  PkInterval  timeout)
+{
+    PkMachineContext ctx;
+    PkThreadPriority priority;
+    PkThread*         thread;
+    PkTimer*          timer = 0;
+    PkInterval       scaled_timeout = PK_INTERVAL_SCALE(timeout);
+
+    int rc = PK_OK;
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(semaphore == 0, PK_INVALID_SEMAPHORE_AT_PEND);
+    }
+
+    pk_critical_section_enter(&ctx);
+
+    if (semaphore->count != 0)
+    {
+
+        semaphore->count--;
+
+    }
+    else if (timeout == PK_NO_WAIT)
+    {
+
+        rc = -PK_SEMAPHORE_PEND_NO_WAIT;
+
+    }
+    else
+    {
+
+        if (PK_ERROR_CHECK_API)
+        {
+            PK_ERROR_IF_CRITICAL(!__pk_kernel_context_thread(),
+                                 PK_SEMAPHORE_PEND_WOULD_BLOCK,
+                                 &ctx);
+        }
+
+        thread = (PkThread*)__pk_current_thread;
+        priority = thread->priority;
+
+        __pk_thread_queue_insert(&(semaphore->pending_threads), priority);
+
+        thread->semaphore = semaphore;
+        thread->flags |= PK_THREAD_FLAG_SEMAPHORE_PEND;
+
+        PK_KERN_TRACE("THREAD_SEMAPHORE_PEND(%d)", priority);
+
+        if (timeout != PK_WAIT_FOREVER)
+        {
+            timer = &(thread->timer);
+            timer->timeout = pk_timebase_get() + scaled_timeout;
+            __pk_timer_schedule(timer);
+            thread->flags |= PK_THREAD_FLAG_TIMER_PEND;
+        }
+
+        __pk_thread_queue_delete(&__pk_run_queue, priority);
+        __pk_schedule();
+
+        thread->flags &= ~PK_THREAD_FLAG_SEMAPHORE_PEND;
+
+        if (thread->flags & PK_THREAD_FLAG_TIMER_PEND)
+        {
+            if (thread->flags & PK_THREAD_FLAG_TIMED_OUT)
+            {
+                rc = -PK_SEMAPHORE_PEND_TIMED_OUT;
+                __pk_thread_queue_delete(&(semaphore->pending_threads), thread->priority);
+            }
+            else
+            {
+                __pk_timer_cancel(timer);
+            }
+
+            thread->flags &=
+                ~(PK_THREAD_FLAG_TIMER_PEND | PK_THREAD_FLAG_TIMED_OUT);
+        }
+    }
+
+    pk_critical_section_exit(&ctx);
+
+    return rc;
+}
+
+
+/// Release all threads blocked on a semaphore
+///
+/// \param semaphore A pointer to a semaphore
+///
+/// This API is provided to allow an PK semaphore to be used as a thread
+/// barrier. pk_semaphore_release_all() simultaneously unblocks all threads
+/// (if any) currently pending on a semaphore. A semaphore to be used as a
+/// thread barrier will typically be initialized with
+/// pk_semaphore_create(\a sem, 0, 0), and sxx_semaphore_post() would never be
+/// called on the \a sem.
+///
+/// This API never modifies the \a count field of the semaphore; If any
+/// threads are blocked on a semaphore the semaphore count is 0 by definition.
+///
+/// Return values other than PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_INVALID_SEMAPHORE_AT_RELEASE The \a semaphore is a null (0)
+/// pointer.
+
+int
+pk_semaphore_release_all(PkSemaphore* semaphore)
+{
+    PkMachineContext ctx;
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(semaphore == 0, PK_INVALID_SEMAPHORE_AT_RELEASE);
+    }
+
+    pk_critical_section_enter(&ctx);
+
+    __pk_thread_queue_union(&__pk_run_queue, &(semaphore->pending_threads));
+    __pk_thread_queue_clear(&(semaphore->pending_threads));
+    __pk_schedule();
+
+    pk_critical_section_exit(&ctx);
+
+    return PK_OK;
+}
+
+
+/// Get information about a semaphore.
+///
+/// \param semaphore A pointer to the PkSemaphore to query
+///
+/// \param count The value returned through this pointer is the current count
+/// of the semaphore.  The caller can set this parameter to the null pointer
+/// (0) if this information is not required.
+///
+/// \param pending The value returned through this pointer is the current
+/// number of threads pending on the semaphore. The caller can set this
+/// parameter to the null pointer (0) if this information is not required.
+///
+/// The information returned by this API can only be guaranteed consistent if
+/// the API is called from a critical section.
+///
+/// Return values other than PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_INVALID_SEMAPHORE_AT_INFO The \a semaphore is a null (0)
+/// pointer.
+
+int
+pk_semaphore_info_get(PkSemaphore*      semaphore,
+                      PkSemaphoreCount* count,
+                      int*               pending)
+
+{
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(semaphore == 0, PK_INVALID_SEMAPHORE_AT_INFO);
+    }
+
+    if (count)
+    {
+        *count = semaphore->count;
+    }
+
+    if (pending)
+    {
+        *pending = __pk_thread_queue_count(&(semaphore->pending_threads));
+    }
+
+    return PK_OK;
+}
+
+
+/// An simple interrupt handler that posts to a semaphore.
+///
+/// To implement basic event-driven blocking of a thread, install
+/// pk_semaphore_post_handler() as the handler for an interrupt
+/// and provide a pointer to the semaphore as the \a arg argument in
+/// pk_irq_handler_set().  The semaphore should be initialized with
+/// pk_semaphore_create(&sem, 0, 1).  This handler simply disables (masks)
+/// the interrupt, clears the status and calls pk_semaphore_post() on the
+/// semaphore.
+///
+/// Note that clearing the status in the interrupt controller as done here is
+/// effectively a no-op for level-sensitive interrupts. In the level-sensitive
+/// case any thread pending on the semaphore must reset the interrupt
+/// condition in the device before re-enabling the interrupt.
+#if 0
+void
+pk_semaphore_post_handler(void* arg, PkIrqId irq, int priority)
+{
+    pk_irq_disable(irq);
+    pk_irq_status_clear(irq);
+    pk_semaphore_post((PkSemaphore*)arg);
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_semaphore_init.c b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_semaphore_init.c
new file mode 100644
index 00000000..821acd62
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_semaphore_init.c
@@ -0,0 +1,107 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_semaphore_init.c $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_semaphore_init.c
+/// \brief PK semaphore API initialization routines
+///
+/// The entry points in this file are routines that are typically used during
+/// initialization, and their code space could be deallocated and recovered if
+/// no longer needed by the application after initialization.
+
+#include "pk.h"
+
+/// Create (initialize) a semaphore
+///
+/// \param semaphore A pointer to an PkSemaphore structure to initialize
+///
+/// \param initial_count The initial count of the semaphore
+///
+/// \param max_count The maximum count allowed in the semaphore, for error
+/// checking
+///
+/// Semaphores are created (initialized) by a call of \c
+/// pk_semaphore_create(), using an application-provided instance of an \c
+/// PkSemaphore structure.  This structure \e is the semaphore, so the
+/// application must never modify the structure if the semaphore is in use.
+/// PK has no way to know if an \c PkSemaphore structure provided to
+/// \c pk_semaphore_create() is safe to use as a semaphore, and will silently
+/// modify whatever memory is provided.
+///
+/// PK provides two simple overflow semantics based on the value of max_count
+/// in the call of \c pk_semaphore_create().
+///
+/// If \a max_count = 0, then posting to the semaphore first increments the
+/// internal count by 1.  Overflows are ignored and will wrap the internal
+/// count through 0.
+///
+/// If \a max_count != 0, then posting to the semaphore first increments the
+/// internal count by 1, wrapping through 0 in the event of overflow. If the
+/// resulting count is greater than max_count, \c pk_semaphore_post() will
+/// return the error \c -PK_SEMAPHORE_POST_OVERFLOW to the caller.
+///
+/// In most applications it is probably best to use the \a max_count != 0
+/// semantics to trap programming errors, unless there is a specific
+/// application where overflow is expected and ignorable. As a fine point of
+/// the specification, a \a max_count of 0 is equivalent to a max_count of
+/// 0xFFFFFFFF.
+///
+/// Return values other then PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_INVALID_SEMAPHORE_AT_CREATE The \a semaphore is a null (0)
+/// pointer.
+///
+/// \retval -PK_INVALID_ARGUMENT_SEMAPHORE The \a max_count is non-zero
+/// and less than the \a initial_count.
+
+int
+pk_semaphore_create(PkSemaphore*      semaphore,
+                    PkSemaphoreCount initial_count,
+                    PkSemaphoreCount max_count)
+{
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(semaphore == 0, PK_INVALID_SEMAPHORE_AT_CREATE);
+        PK_ERROR_IF((max_count != 0) && (initial_count > max_count),
+                    PK_INVALID_ARGUMENT_SEMAPHORE);
+    }
+
+    __pk_thread_queue_clear(&(semaphore->pending_threads));
+    semaphore->count = initial_count;
+    semaphore->max_count = max_count;
+
+    return PK_OK;
+}
+
+
+
+
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_stack_init.c b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_stack_init.c
new file mode 100644
index 00000000..8df26c4c
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_stack_init.c
@@ -0,0 +1,119 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_stack_init.c $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_stack_init.c
+/// \brief PK stack initialization
+///
+/// The entry points in this file are initialization routines - they are never
+/// needed after PK initialization and their code space could be reclaimed by
+/// the application after initialization if required.
+///
+/// This code was split out from "pk_init.c" because it may be needed in a
+/// thread configuration if threads are being created dynamically. in an
+/// interrupt-only configuration it is not needed after \c pk_initialize().
+
+#include "pk.h"
+
+/// Initialize a stack area.
+///
+/// \param stack A pointer to the smallest legal address of the stack.  The
+/// stack address is modified as the stack is aligned and initialized.
+///
+/// \param size A pointer to the size of the stack (in bytes).  The size is
+/// modified as the stack is aligned and initialized.  At exit this is the
+/// final usable stack area size aligned to the size of the PK_STACK_TYPE.
+///
+/// PK makes no assumptions about size or alignment of the area provided as a
+/// stack, and carefully aligns and initializes the stack.  Regardless of how
+/// the stack grows, the \a stack parameter is considered to be the lowest
+/// legal address of the stack.
+
+int
+__pk_stack_init(PkAddress* stack,
+                size_t*     size)
+{
+    PkAddress mask;
+    size_t excess, i, count;
+    PK_STACK_TYPE* p;
+
+    if (PK_STACK_DIRECTION < 0)
+    {
+
+        // Stacks grow down.  The initial stack pointer is set to just above
+        // the last allocated stack address.  This is legal for pre-decrement
+        // stacks, otherwise the initial address is first brought into range
+        // before alignment.  The stack is aligned downward, then the size is
+        // adjusted to a multiple of the stack type.  Stacks are optionally
+        // prepatterned. Alignment is assumed to be a power of 2.
+
+        *stack += *size;
+
+        if (!PK_STACK_PRE_DECREMENT)
+        {
+            *stack -= sizeof(PK_STACK_TYPE);
+            *size -= sizeof(PK_STACK_TYPE);
+        }
+
+        mask = PK_STACK_ALIGNMENT - 1;
+        excess = *stack & mask;
+        *stack -= excess;
+        *size -= excess;
+        *size = (*size / sizeof(PK_STACK_TYPE)) * sizeof(PK_STACK_TYPE);
+
+        if (PK_STACK_CHECK)
+        {
+            p = (PK_STACK_TYPE*)(*stack);
+            count = *size / sizeof(PK_STACK_TYPE);
+
+            for (i = 0; i < count; i++)
+            {
+                if (PK_STACK_PRE_DECREMENT)
+                {
+                    *(--p) = PK_STACK_PATTERN;
+                }
+                else
+                {
+                    *(p--) = PK_STACK_PATTERN;
+                }
+            }
+        }
+
+        __pk_stack_create_initial_frame(stack, size);
+
+    }
+    else
+    {
+
+        PK_PANIC(PK_UNIMPLEMENTED);
+    }
+
+    return PK_OK;
+}
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_thread.h b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_thread.h
new file mode 100644
index 00000000..13b6a215
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_thread.h
@@ -0,0 +1,80 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_thread.h $        */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PK_THREAD_H__
+#define __PK_THREAD_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_thread.h
+/// \brief Contains private declarations and definitions needed for threads
+///
+
+void
+__pk_thread_map(PkThread* thread);
+
+void
+__pk_thread_unmap(PkThread* thread);
+
+
+// Interrupts must be disabled at entry.
+
+static inline int
+__pk_thread_is_active(PkThread* thread)
+{
+    return ((thread->state != PK_THREAD_STATE_COMPLETED) &&
+            (thread->state != PK_THREAD_STATE_DELETED));
+}
+
+
+// Interrupts must be disabled at entry.
+
+static inline int
+__pk_thread_is_mapped(PkThread* thread)
+{
+    return (thread->state == PK_THREAD_STATE_MAPPED);
+}
+
+
+// Interrupts must be disabled at entry. This is only called on mapped threads.
+
+static inline int
+__pk_thread_is_runnable(PkThread* thread)
+{
+    return __pk_thread_queue_member(&__pk_run_queue, thread->priority);
+}
+
+
+// Interrupts must be disabled at entry.
+
+static inline PkThread*
+__pk_thread_at_priority(PkThreadPriority priority)
+{
+    return (PkThread*)__pk_priority_map[priority];
+}
+
+#endif /* __PK_THREAD_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_thread_core.c b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_thread_core.c
new file mode 100644
index 00000000..c57ff970
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_thread_core.c
@@ -0,0 +1,645 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_thread_core.c $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_thread_core.c
+/// \brief PK thread APIs
+///
+///  The entry points in this file are considered 'core' routines that will
+///  always be present at runtime in any PK application that enables threads.
+
+#include "pk.h"
+#include "pk_thread.h"
+
+#define __PK_THREAD_CORE_C__
+
+
+// This routine is only used locally.  Interrupts must be disabled
+// at entry.  The caller must also have checked that the priority is free.
+// This routine is only called on threads known to be in a suspended state,
+// either PK_THREAD_STATE_SUSPENDED_RUNNABLE or
+// PK_THREAD_STATE_SUSPENDED_BLOCKED.  Mapping a runnable thread adds it to
+// the run queue.  Mapping a thread pending on a semaphore either takes the
+// count and becomes runnable or adds the thread to the pending queue for the
+// semaphore.  Mapping a sleeping thread requires no further action
+// here. Scheduling after the map must be handled by the caller.
+
+void
+__pk_thread_map(PkThread* thread)
+{
+    PkThreadPriority priority;
+
+    priority = thread->priority;
+    __pk_priority_map[priority] = thread;
+
+    if (thread->state == PK_THREAD_STATE_SUSPENDED_RUNNABLE)
+    {
+
+        __pk_thread_queue_insert(&__pk_run_queue, priority);
+
+    }
+    else if (thread->flags & PK_THREAD_FLAG_SEMAPHORE_PEND)
+    {
+
+        if (thread->semaphore->count)
+        {
+
+            thread->semaphore->count--;
+            __pk_thread_queue_insert(&__pk_run_queue, priority);
+
+        }
+        else
+        {
+
+            __pk_thread_queue_insert(&(thread->semaphore->pending_threads),
+                                     priority);
+        }
+    }
+
+    thread->state = PK_THREAD_STATE_MAPPED;
+
+    if (PK_KERNEL_TRACE_ENABLE)
+    {
+        if (__pk_thread_is_runnable(thread))
+        {
+            PK_KERN_TRACE("THREAD_MAPPED_RUNNABLE(%d)", priority);
+        }
+        else if (thread->flags & PK_THREAD_FLAG_SEMAPHORE_PEND)
+        {
+            PK_KERN_TRACE("THREAD_MAPPED_SEMAPHORE_PEND(%d)", priority);
+        }
+        else
+        {
+            PK_KERN_TRACE("THREAD_MAPPED_SLEEPING(%d)", priority);
+        }
+    }
+}
+
+
+// This routine is only used locally.  Interrupts must be disabled
+// at entry.  This routine is only ever called on threads in the
+// PK_THREAD_STATE_MAPPED. Unmapping a thread removes it from the priority
+// map, the run queue and any semaphore pend, but does not cancel any
+// timers. Scheduling must be handled by the code calling
+// __pk_thread_unmap().
+
+void
+__pk_thread_unmap(PkThread* thread)
+{
+    PkThreadPriority priority;
+
+    priority = thread->priority;
+    __pk_priority_map[priority] = 0;
+
+    if (__pk_thread_is_runnable(thread))
+    {
+
+        thread->state = PK_THREAD_STATE_SUSPENDED_RUNNABLE;
+        __pk_thread_queue_delete(&__pk_run_queue, priority);
+
+    }
+    else
+    {
+
+        thread->state = PK_THREAD_STATE_SUSPENDED_BLOCKED;
+
+        if (thread->flags & PK_THREAD_FLAG_SEMAPHORE_PEND)
+        {
+            __pk_thread_queue_delete(&(thread->semaphore->pending_threads),
+                                     priority);
+        }
+    }
+}
+
+
+// Schedule and run the highest-priority mapped runnable thread.
+//
+// The priority of the next thread to run is first computed.  This may be
+// PK_THREADS, indicating that the only thread to run is the idle thread.
+// This will always cause (or defer) a 'context switch' to the idle thread.
+// Otherwise, if the new thread is not equal to the current thread this will
+// also cause (or defer) a context switch. Note that scheduling is defined in
+// terms of priorities but actually implemented in terms of PkThread pointers.
+//
+// If we are not yet in thread mode we're done - threads will be started by
+// pk_start_threads() later. If we're in thread context a context switch
+// happens immediately. In an interrupt context the switch is deferred to the
+// end of interrupt processing.
+
+void
+__pk_schedule(void)
+{
+    __pk_next_priority = __pk_thread_queue_min(&__pk_run_queue);
+    __pk_next_thread = __pk_priority_map[__pk_next_priority];
+
+    if ((__pk_next_thread == 0) ||
+        (__pk_next_thread != __pk_current_thread))
+    {
+
+        if (__pk_kernel_mode_thread())
+        {
+            if (__pk_kernel_context_thread())
+            {
+                if (__pk_current_thread != 0)
+                {
+                    __pk_switch();
+                }
+                else
+                {
+                    __pk_next_thread_resume();
+                }
+            }
+            else
+            {
+                __pk_delayed_switch = 1;
+            }
+        }
+    }
+}
+
+
+// This routine is only used locally.
+//
+// Completion and deletion are pretty much the same thing.  Completion is
+// simply self-deletion of the current thread (which is mapped by
+// definition.) The complete/delete APIs have slightly different error
+// conditions but are otherwise the same.
+//
+// Deleting a mapped thread first unmaps (suspends) the thread, which takes
+// care of removing the thread from any semaphores it may be pending on.  Then
+// any outstanding timer is also cancelled.
+//
+// If the current thread is being deleted we install the idle thread as
+// __pk_current_thread, so scheduling is forced and no context is saved on
+// the context switch.
+//
+// Note that we do not create trace events for unmapped threads since the trace
+// tag only encodes the priority, which may be in use by a mapped thread.
+
+void
+__pk_thread_delete(PkThread* thread, PkThreadState final_state)
+{
+    PkMachineContext ctx;
+    int mapped;
+
+    pk_critical_section_enter(&ctx);
+
+    mapped = __pk_thread_is_mapped(thread);
+
+    if (mapped)
+    {
+        __pk_thread_unmap(thread);
+    }
+
+    __pk_timer_cancel(&(thread->timer));
+    thread->state = final_state;
+
+    if (mapped)
+    {
+
+        if (PK_KERNEL_TRACE_ENABLE)
+        {
+            if (final_state == PK_THREAD_STATE_DELETED)
+            {
+                PK_KERN_TRACE("THREAD_DELETED(%d)", thread->priority);
+            }
+            else
+            {
+                PK_KERN_TRACE("THREAD_COMPLETED(%d)", thread->priority);
+            }
+        }
+
+        if (thread == __pk_current_thread)
+        {
+            __pk_current_thread = 0;
+        }
+
+        __pk_schedule();
+    }
+
+    pk_critical_section_exit(&ctx);
+}
+
+
+// Generic thread timeout
+//
+// This routine is called as a timer callback either because a sleeping thread
+// has timed out or a thread pending on a semaphore has timed out.  If the
+// thread is not already runnable then the the timeout flag is set, and if the
+// thread is mapped it is scheduled.
+//
+// This implementation allows that a thread blocked on a timer may have been
+// made runnable by some other mechanism, such as acquiring a semaphore.  In
+// order to provide an iteration-free implementation of
+// pk_semaphore_release_all(), cancelling any semaphore timeouts is deferred
+// until the thread runs again.
+//
+// Note that we do not create trace events for unmapped threads since the trace
+// tag only encodes the priority, which may be in use by a mapped thread.
+
+void
+__pk_thread_timeout(void* arg)
+{
+    PkMachineContext ctx;
+    PkThread* thread = (PkThread*)arg;
+
+    pk_critical_section_enter(&ctx);
+
+    switch (thread->state)
+    {
+
+        case PK_THREAD_STATE_MAPPED:
+            if (!__pk_thread_is_runnable(thread))
+            {
+                thread->flags |= PK_THREAD_FLAG_TIMED_OUT;
+                __pk_thread_queue_insert(&__pk_run_queue, thread->priority);
+                __pk_schedule();
+            }
+
+            break;
+
+        case PK_THREAD_STATE_SUSPENDED_RUNNABLE:
+            break;
+
+        case PK_THREAD_STATE_SUSPENDED_BLOCKED:
+            thread->flags |= PK_THREAD_FLAG_TIMED_OUT;
+            thread->state = PK_THREAD_STATE_SUSPENDED_RUNNABLE;
+            break;
+
+        default:
+            PK_PANIC(PK_THREAD_TIMEOUT_STATE);
+    }
+
+    pk_critical_section_exit(&ctx);
+}
+
+
+// This routine serves as a container for the PK_START_THREADS_HOOK and
+// actually starts threads.  The helper routine __pk_call_pk_start_threads()
+// arranges this routine to be called with interrupts disabled while running
+// on the kernel stack.
+//
+// The reason for this roundabout is that we want to be able to run a hook
+// routine (transparent to the application) that can hand over every last byte
+// of free memory to "malloc()" - including the stack of main().  Since we
+// always need to run on some stack, we chose to run the hook on the kernel
+// stack. However to do this safely we need to make sure
+// that no interrupts will happen during this time. When __pk_thread_resume()
+// is finally called all stack-based context is lost but it doesn't matter at
+// that point - it's a one-way street into thread execution.
+//
+// This is considered part of pk_start_threads() and so is also considered a
+// 'core' routine.
+
+void
+__pk_start_threads(void)
+{
+    PK_START_THREADS_HOOK;
+
+    __pk_next_thread_resume();
+
+    PK_PANIC(PK_START_THREADS_RETURNED);
+}
+
+
+/// Start PK threads
+///
+/// This routine starts the PK thread scheduler infrastructure. This routine
+/// must be called after a call of \c pk_initialize().  This routine never
+/// returns. Interrupt (+ timer) only configurations of PK need not call this
+/// routine.
+///
+/// Note: This tiny routine is considered a 'core' routine so that the
+/// initialziation code can safely recover all 'init' code space before
+/// starting threads.
+///
+/// This routine typically does not return - any return value indicates an
+/// error; see \ref pk_errors
+///
+/// \retval -PK_ILLEGAL_CONTEXT_THREAD The API was called twice.
+
+int
+pk_start_threads(void)
+{
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(__pk_kernel_mode_thread(), PK_ILLEGAL_CONTEXT_THREAD);
+    }
+
+    __pk_call_pk_start_threads();
+
+    return 0;
+}
+
+
+/// Resume a suspended thread
+///
+/// \param thread The thread to resume
+///
+/// PK only allows one thread at a time to run at a given priority, and
+/// implements the notion of a thread \e claiming a priority.  A suspended
+/// thread claims a priority when it is mapped by a call of
+/// pk_thread_resume().  This API will succeed only if no other active thread
+/// is currently mapped at the priority assigned to the thread.  PK provides
+/// the pk_thread_at_priority() API which allows an application-level
+/// scheduler to correctly manage multiple threads running at the same
+/// priority.
+///
+/// If the thread was sleeping while suspended it remains asleep. However if
+/// the sleep timer timed out while the thread was suspended it will be
+/// resumed runnable.
+///
+/// If the thread was blocked on a semaphore when it was suspended, then when
+/// the thread is resumed it will attempt to reacquire the semaphore.
+/// However, if the thread was blocked on a semaphore with timeout while
+/// suspended and the timeout interval has passed, the thread will be resumed
+/// runnable and see that the semaphore pend timed out.
+///
+/// It is not an error to call pk_thread_resume() on a mapped
+/// thread.  However it is an error to call pk_thread_resume() on a completed
+/// or deleted thread.
+///
+/// Return values other than PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion, including calls on a \a thread that is
+/// already mapped.
+///
+/// \retval -PK_INVALID_THREAD_AT_RESUME1 The \a thread is a null (0) pointer.
+///
+/// \retval -PK_INVALID_THREAD_AT_RESUME2 The \a thread is not active,
+/// i.e. has completed or been deleted.
+///
+/// \retval -PK_PRIORITY_IN_USE_AT_RESUME Another thread is already mapped at
+/// the priority of the \a thread.
+
+int
+pk_thread_resume(PkThread* thread)
+{
+    PkMachineContext ctx;
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(thread == 0, PK_INVALID_THREAD_AT_RESUME1);
+    }
+
+    pk_critical_section_enter(&ctx);
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF_CRITICAL(!__pk_thread_is_active(thread),
+                             PK_INVALID_THREAD_AT_RESUME2,
+                             &ctx);
+    }
+
+    if (!__pk_thread_is_mapped(thread))
+    {
+
+        if (PK_ERROR_CHECK_API)
+        {
+            PK_ERROR_IF_CRITICAL(__pk_priority_map[thread->priority] != 0,
+                                 PK_PRIORITY_IN_USE_AT_RESUME,
+                                 &ctx);
+        }
+
+        __pk_thread_map(thread);
+        __pk_schedule();
+    }
+
+    pk_critical_section_exit(&ctx);
+
+    return PK_OK;
+}
+
+
+/// Suspend a thread
+///
+/// Any active thread can be suspended.  A suspended thread 1) remains active
+/// but will not be scheduled; 2) relinquishes its priority assignment,
+/// allowing another thread to be resumed at the suspended thread's priority;
+/// and 3) disassociates from any semaphore mutual exclusion it may have been
+/// participating in.
+///
+/// If a sleeping thread is suspended, the sleep timer remains active but a
+/// timeout of the timer simply marks the thread as runnable, but does not
+/// resume the thread.
+///
+/// If a thread blocked on a semaphore is suspended, the thread no longer
+/// participates in the semaphore mutual exclusion. If the thread is later
+/// resumed it will attempt to acquire the semaphore again the next time it
+/// runs (unless it was blocked with a timeout and the timeout has expired).
+///
+/// If a thread blocked on a semaphore with timeout is suspended, the
+/// semaphore timeout timer continues to run. If the timer times out while the
+/// thread is suspended the thread is simply marked runnable. If the thread is
+/// later resumed, the suspended call of \c pk_semaphore_pend() will return the
+/// timeout code -PK_SEMAPHORE_PEND_TIMED_OUT.
+///
+/// Return values other than PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion, including calls on a \a thread that is
+/// already suspended.
+///
+/// \retval -PK_INVALID_THREAD_AT_SUSPEND1 The \a thread is a null (0) pointer
+///
+/// \retval -PK_INVALID_THREAD_AT_SUSPEND2 The \a thread is not active,
+/// i.e. has completed or been deleted.
+
+int
+pk_thread_suspend(PkThread* thread)
+{
+    PkMachineContext ctx;
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF((thread == 0), PK_INVALID_THREAD_AT_SUSPEND1);
+    }
+
+    pk_critical_section_enter(&ctx);
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF_CRITICAL(!__pk_thread_is_active(thread),
+                             PK_INVALID_THREAD_AT_SUSPEND2,
+                             &ctx);
+    }
+
+    if (__pk_thread_is_mapped(thread))
+    {
+
+        PK_KERN_TRACE("THREAD_SUSPENDED(%d)", thread->priority);
+        __pk_thread_unmap(thread);
+        __pk_schedule();
+    }
+
+    pk_critical_section_exit(&ctx);
+
+    return PK_OK;
+}
+
+
+/// Delete a thread
+///
+/// Any active thread can be deleted.  If a thread is deleted it is removed
+/// from the run queue, deleted from the timer queue (if sleeping or blocked
+/// on a semaphore with timeout), and deleted from the semaphore mutual
+/// exclusion if blocked on a semaphore. The thread control block is then
+/// marked as deleted.
+///
+/// Once a thread has completed or been deleted the thread structure and
+/// thread stack areas can be used for other purposes.
+///
+/// \param thread The thread to delete
+///
+/// Return values other than PK_OK (0) are errors; see \ref pk_errors.  If a
+/// thread deletes itself this API does not return at all.
+///
+/// \retval 0 Successful completion, including calls on a \a thread that has
+/// completed or had already been deleted.
+///
+///
+/// \retval -PK_INVALID_THREAD_AT_DELETE The \a thread is a null (0) pointer.
+
+int
+pk_thread_delete(PkThread* thread)
+{
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(thread == 0, PK_INVALID_THREAD_AT_DELETE);
+    }
+
+    __pk_thread_delete(thread, PK_THREAD_STATE_DELETED);
+
+    return PK_OK;
+}
+
+
+/// Complete a thread
+///
+/// If a thread ever returns from the subroutine defining the thread entry
+/// point, the thread is removed from all PK kernel data structures and
+/// marked completed. The thread routine can also use the API pk_complete()
+/// to make this more explicit if desired. PK makes no distinction between
+/// completed and deleted threads, but provides these indications for
+/// the benefit of the application.
+///
+/// Note that this API is only available from the current thread to mark its
+/// own completion.
+///
+/// Once a thread has completed or been deleted the thread structure and
+/// thread stack areas can be used for other purposes.
+///
+/// Any return value indicates an error; see \ref pk_errors.  In the event of
+/// a successful completion this API does not return to the caller, which is
+/// always the thread context being completed.
+///
+/// \retval -PK_ILLEGAL_CONTEXT_THREAD The API was not called from a thread
+/// context.
+
+// Note: Casting __pk_current_thread removes the 'volatile' attribute.
+
+int
+pk_complete(void)
+{
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_UNLESS_THREAD_CONTEXT();
+    }
+
+    __pk_thread_delete((PkThread*)__pk_current_thread,
+                       PK_THREAD_STATE_COMPLETED);
+
+    return PK_OK;
+}
+
+/// Sleep a thread for an interval relative to the current time.
+///
+/// \param interval A time interval relative to the current timebase.
+///
+/// Threads can use this API to sleep for a time relative to the current
+/// timebase.  The absolute timeout is \c pk_timebase_get() + \a interval.
+///
+///  Sleeping threads are not scheduled, although they maintain their
+/// priorities.  This differs from thread suspension, where the suspended
+/// thread relinquishes its priority.  When the sleep timer times out the
+/// thread becomes runnable again, and will run as soon as it becomes the
+/// highest-priority mapped runnable thread.
+///
+/// Sleeping threads may also be later suspended. In this case the Sleep timer
+/// continues to run, and if it times out before the thread is resumed the
+/// thread will be immediately runnable when it is resumed.
+///
+/// See the PK specification for a full discussion of how PK handles
+/// scheduling events at absolute times "in the past". Briefly stated, if the
+/// \a interval is 0 or is so small that the absolute time becomes a "past"
+/// time before the Sleep is actually scheduled, the thread will Sleep for the
+/// briefest possible period supported by the hardware.
+///
+/// Return values other than PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion.
+///
+/// \retval -PK_ILLEGAL_CONTEXT_THREAD The API was not called from a thread
+/// context.
+
+int
+pk_sleep(PkInterval interval)
+{
+    PkTimebase  time;
+    PkMachineContext ctx;
+    PkThread* current;
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_UNLESS_THREAD_CONTEXT();
+    }
+
+    time = pk_timebase_get() + PK_INTERVAL_SCALE(interval);
+
+    pk_critical_section_enter(&ctx);
+
+    current = (PkThread*)__pk_current_thread;
+
+    current->timer.timeout = time;
+    __pk_timer_schedule(&(current->timer));
+
+    current->flags |= PK_THREAD_FLAG_TIMER_PEND;
+
+    PK_KERN_TRACE("THREAD_SLEEP(%d)", current->priority);
+
+    __pk_thread_queue_delete(&__pk_run_queue, current->priority);
+    __pk_schedule();
+
+    current->flags &= ~(PK_THREAD_FLAG_TIMER_PEND | PK_THREAD_FLAG_TIMED_OUT);
+
+    pk_critical_section_exit(&ctx);
+
+    return PK_OK;
+}
+
+#undef __PK_THREAD_CORE_C__
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_thread_init.c b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_thread_init.c
new file mode 100644
index 00000000..a0a8b956
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_thread_init.c
@@ -0,0 +1,168 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_thread_init.c $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_thread_init.c
+/// \brief PK thread API initialization routines
+///
+/// The entry points in this file are routines that are typically used during
+/// initialization, and their code space could be deallocated and recovered if
+/// no longer needed by the application after initialization.
+
+#include "pk.h"
+
+/// Create (initialize) a thread
+///
+/// \param thread A pointer to an PkThread structure to initialize
+///
+/// \param thread_routine The subroutine that implements the thread
+///
+/// \param arg Private data to be passed as the argument to the thread
+/// routine when it begins execution
+///
+/// \param stack The stack space of the thread
+///
+/// \param stack_size The size of the stack in bytes
+///
+/// \param priority The initial priority of the thread
+///
+/// The \a thread argument must be a pointer to an uninitialized or completed
+/// or deleted thread.  This \c PkThread structure \em is the thread, so this
+/// memory area must not be modified by the application until the thread
+/// completes or is deleted.  PK can not tell if an PkThread structure is
+/// currently in use as a thread control block.pk_thread_create() will
+/// silently overwrite an PkThread structure that is currently in use.
+///
+/// The stack area must be large enough to hold the dynamic stack requirements
+/// of the entry point routine, and all subroutines and functions that might
+/// be invoked on any path from the entry point.  The stack must also always
+/// be able to hold the thread context in the event the thread is preempted,
+/// plus other critical context.  PK aligns stack areas in machine-specific
+/// ways, so that the actual stack area may reduced in size slightly if it is
+/// not already aligned.
+///
+/// Threads are created runnable but unmapped.  A newly created thread will
+/// not be eligible to run until a call of pk_thread_resume() targets the
+/// thread.
+///
+/// Return values other than PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_INVALID_THREAD_AT_CREATE The \a thread is a null (0) pointer.
+///
+/// \retval -PK_INVALID_ARGUMENT_THREAD1 the \a thread_routine is null (0)
+///
+/// \retval -PK_INVALID_ARGUMENT_THREAD2 the \a priority is invalid,
+///
+/// \retval -PK_INVALID_ARGUMENT_THREAD3 the stack area wraps around
+/// the end of memory.
+///
+/// \retval -PK_STACK_OVERFLOW The stack area at thread creation is smaller
+/// than the minimum safe size.
+
+int
+pk_thread_create(PkThread*         thread,
+                 PkThreadRoutine  thread_routine,
+                 void*              arg,
+                 PkAddress        stack,
+                 size_t            stack_size,
+                 PkThreadPriority priority)
+{
+    int rc;
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(thread == 0, PK_INVALID_THREAD_AT_CREATE);
+        PK_ERROR_IF((thread_routine == 0) ||
+                    (priority >= PK_THREADS),
+                    PK_INVALID_ARGUMENT_THREAD1);
+    }
+
+    rc = __pk_stack_init(&stack, &stack_size);
+
+    if (rc)
+    {
+        return rc;
+    }
+
+    thread->saved_stack_pointer = stack;
+    thread->stack_base = stack;
+
+    if (PK_STACK_DIRECTION < 0)
+    {
+
+        thread->stack_limit = stack - stack_size;
+
+        if (PK_ERROR_CHECK_API)
+        {
+            PK_ERROR_IF(thread->stack_limit > thread->stack_base,
+                        PK_INVALID_ARGUMENT_THREAD2);
+        }
+
+    }
+    else
+    {
+
+        thread->stack_limit = stack + stack_size;
+
+        if (PK_ERROR_CHECK_API)
+        {
+            PK_ERROR_IF(thread->stack_limit < thread->stack_base,
+                        PK_INVALID_ARGUMENT_THREAD3);
+        }
+    }
+
+    thread->semaphore = 0;
+    thread->priority = priority;
+    thread->state = PK_THREAD_STATE_SUSPENDED_RUNNABLE;
+    thread->flags = 0;
+
+    pk_timer_create(&(thread->timer),
+                    __pk_thread_timeout,
+                    (void*)thread);
+
+    __pk_thread_context_initialize(thread, thread_routine, arg);
+
+    return rc;
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_thread_util.c b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_thread_util.c
new file mode 100644
index 00000000..670a89a0
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_thread_util.c
@@ -0,0 +1,342 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_thread_util.c $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_thread_util.c
+/// \brief PK thread utility APIs
+///
+///  The entry points in this file are considered extra routines that will
+///  only be included in a PK application that enables threads and uses at
+///  least one of these interfaces.
+
+#include "pk.h"
+#include "pk_thread.h"
+
+/// Get information about a thread.
+///
+/// \param thread A pointer to the PkThread to query
+///
+/// \param state The value returned through this pointer is the current state
+/// of the thread; See \ref pk_thread_states. The caller can set this
+/// parameter to the null pointer (0) if this information is not required.
+///
+/// \param priority The value returned through this pointer is the current
+/// priority of the thread.  The caller can set this parameter to the null
+/// pointer (0) if this information is not required.
+///
+/// \param runnable The value returned through this pointer is 1 if the thread
+/// is in state PK_THREAD_STATE_MAPPED and is currently in the run queue
+/// (i.e., neither blocked on a semaphore nor sleeping), otherwise 0. The
+/// caller can set this parameter to the null pointer (0) if this information
+/// is not required.
+///
+/// The information returned by this API can only be guaranteed consistent if
+/// the API is called from a critical section.
+///
+/// Return values other than PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_INVALID_THREAD_AT_INFO The \a thread is a null (0) pointer.
+
+int
+pk_thread_info_get(PkThread*         thread,
+                   PkThreadState*    state,
+                   PkThreadPriority* priority,
+                   int*               runnable)
+{
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(thread == 0, PK_INVALID_THREAD_AT_INFO);
+    }
+
+    if (state)
+    {
+        *state = thread->state;
+    }
+
+    if (priority)
+    {
+        *priority = thread->priority;
+    }
+
+    if (runnable)
+    {
+        *runnable = ((thread->state == PK_THREAD_STATE_MAPPED) &&
+                     __pk_thread_queue_member(&__pk_run_queue,
+                                              thread->priority));
+    }
+
+    return PK_OK;
+}
+
+
+/// Change the priority of a thread.
+///
+/// \param thread The thread whose priority will be changed
+///
+/// \param new_priority The new priority of the thread
+///
+/// \param old_priority The value returned through this pointer is the
+/// old priority of the thread prior to the change. The caller can set
+/// this parameter to the null pointer (0) if this information is not
+/// required.
+///
+/// Thread priorities can be changed by the \c pk_thread_priority_change()
+/// API. This call will fail if the thread pointer is invalid or if the thread
+/// is mapped and the new priority is currently in use.  The call will succeed
+/// even if the \a thread is suspended, completed or deleted.  The
+/// application-level scheduling algorithm is completely responsible for the
+/// correctness of the application in the event of suspended, completed or
+/// deleted threads.
+///
+/// Return values other than PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion, including the redundant case of
+/// attempting to change the priority of the thread to its current priority.
+///
+/// \retval -PK_INVALID_THREAD_AT_CHANGE The \a thread is null (0) or
+/// otherwise invalid.
+///
+/// \retval -PK_INVALID_ARGUMENT_THREAD_CHANGE The \a new_priority is invalid.
+///
+/// \retval -PK_PRIORITY_IN_USE_AT_CHANGE The \a thread is mapped and the \a
+/// new_priority is currently in use by another thread.
+
+int
+pk_thread_priority_change(PkThread*         thread,
+                          PkThreadPriority new_priority,
+                          PkThreadPriority* old_priority)
+{
+    PkMachineContext ctx;
+    PkThreadPriority priority;
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(thread == 0, PK_INVALID_THREAD_AT_CHANGE);
+        PK_ERROR_IF(new_priority > PK_THREADS,
+                    PK_INVALID_ARGUMENT_THREAD_CHANGE);
+    }
+
+    pk_critical_section_enter(&ctx);
+
+    priority = thread->priority;
+
+    if (priority != new_priority)
+    {
+
+        if (!__pk_thread_is_mapped(thread))
+        {
+
+            thread->priority = new_priority;
+
+        }
+        else
+        {
+
+            if (PK_ERROR_CHECK_API)
+            {
+                PK_ERROR_IF_CRITICAL(__pk_priority_map[new_priority] != 0,
+                                     PK_PRIORITY_IN_USE_AT_CHANGE,
+                                     &ctx);
+            }
+
+            __pk_thread_unmap(thread);
+            thread->priority = new_priority;
+            __pk_thread_map(thread);
+            __pk_schedule();
+        }
+    }
+
+    if (old_priority)
+    {
+        *old_priority = priority;
+    }
+
+    pk_critical_section_exit(&ctx);
+
+    return PK_OK;
+}
+
+
+/// Return a pointer to the thread (if any) mapped at a given priority.
+///
+/// \param priority The thread priority of interest
+///
+/// \param thread The value returned through this pointer is a pointer to the
+/// thread currently mapped at the given priority level.  If no thread is
+/// mapped, or if the \a priority is the priority of the idle thread, the
+/// pointer returned will be null (0).
+///
+/// The information returned by this API can only be guaranteed consistent if
+/// the API is called from a critical section.
+///
+/// Return values other than PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion.
+///
+/// \retval -PK_INVALID_ARGUMENT_THREAD_PRIORITY The \a priority is invalid
+/// or the \a thread parameter is null (0).
+
+int
+pk_thread_at_priority(PkThreadPriority priority,
+                      PkThread**         thread)
+{
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF((priority > PK_THREADS) || (thread == 0),
+                    PK_INVALID_ARGUMENT_THREAD_PRIORITY);
+    }
+
+    *thread = __pk_thread_at_priority(priority);
+
+    return PK_OK;
+}
+
+
+/// Swap thread priorities
+///
+/// \param thread_a A pointer to an initialized PkThread
+///
+/// \param thread_b A pointer to an initialized PkThread
+///
+/// This API swaps the priorities of \a thread_a and \a thread_b.  The API is
+/// provided to support general and efficient application-directed scheduling
+/// algorithms.  The requirements on the \a thread_a and \a thread_b arguments
+/// are that they are valid pointers to initialized PkThread structures, that
+/// the current thread priorities of both threads are legal, and that if a
+/// thread is currently mapped, that the new thread priority is not otherwise
+/// in use.
+///
+/// The API does not require either thread to be mapped, or even to be active.
+/// It is legal for one or both of the swap partners to be suspended, deleted
+/// or completed threads.  The application is completely responsible for the
+/// correctness of scheduling algorithms that might operate on inactive or
+/// suspended threads.
+///
+/// The API does not change the mapped status of a thread.  A thread will be
+/// mapped after the call of pk_thread_priority_swap() if and only if it was
+/// mapped prior to the call.  If the new priority of a mapped thread is
+/// currently in use (by a thread other than the swap partner), then the
+/// PK_PRIORITY_IN_USE_AT_SWAP error is signalled and the swap does not take
+/// place. This could only happen if the swap partner is not currently mapped.
+///
+/// It is legal for a thread to swap its own priority with another thread. The
+/// degenerate case that \a thread_a and \a thread_b are equal is also legal -
+/// but has no effect.
+///
+/// Return values other than PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion, including the redundant cases that do not
+/// actually change priorities, or the cases that assign new priorities to
+/// suspended, completed or deleted threads.
+///
+/// \retval -PK_INVALID_THREAD_AT_SWAP1 One or both of \a thread_a and
+/// \a thread_b is null (0) or otherwise invalid,
+///
+/// \retval -PK_INVALID_THREAD_AT_SWAP2 the priorities of One or both of
+/// \a thread_a and \a thread_b are invalid.
+///
+/// \retval -PK_INVALID_ARGUMENT One or both of the priorities
+/// of \a thread_a and \a thread_b is invalid.
+///
+/// \retval -PK_PRIORITY_IN_USE_AT_SWAP Returned if a thread is mapped and the
+/// new thread priority is currently in use by another thread (other than the
+/// swap partner).
+
+int
+pk_thread_priority_swap(PkThread* thread_a, PkThread* thread_b)
+{
+    PkMachineContext ctx;
+    PkThreadPriority priority_a, priority_b;
+    int mapped_a, mapped_b;
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF((thread_a == 0) ||  (thread_b == 0),
+                    PK_INVALID_THREAD_AT_SWAP1);
+    }
+
+    pk_critical_section_enter(&ctx);
+
+    if (thread_a != thread_b)
+    {
+
+        mapped_a = __pk_thread_is_mapped(thread_a);
+        mapped_b = __pk_thread_is_mapped(thread_b);
+        priority_a = thread_a->priority;
+        priority_b = thread_b->priority;
+
+        if (PK_ERROR_CHECK_API)
+        {
+            int priority_in_use;
+            PK_ERROR_IF_CRITICAL((priority_a > PK_THREADS) ||
+                                 (priority_b > PK_THREADS),
+                                 PK_INVALID_THREAD_AT_SWAP2,
+                                 &ctx);
+            priority_in_use =
+                (mapped_a && !mapped_b &&
+                 (__pk_thread_at_priority(priority_b) != 0)) ||
+                (!mapped_a && mapped_b &&
+                 (__pk_thread_at_priority(priority_a) != 0));
+            PK_ERROR_IF_CRITICAL(priority_in_use,
+                                 PK_PRIORITY_IN_USE_AT_SWAP, &ctx);
+        }
+
+        if (mapped_a)
+        {
+            __pk_thread_unmap(thread_a);
+        }
+
+        if (mapped_b)
+        {
+            __pk_thread_unmap(thread_b);
+        }
+
+        thread_a->priority = priority_b;
+        thread_b->priority = priority_a;
+
+        if (mapped_a)
+        {
+            __pk_thread_map(thread_a);
+        }
+
+        if (mapped_b)
+        {
+            __pk_thread_map(thread_b);
+        }
+
+        __pk_schedule();
+    }
+
+    pk_critical_section_exit(&ctx);
+
+    return PK_OK;
+}
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_timer_core.c b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_timer_core.c
new file mode 100644
index 00000000..2b812963
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_timer_core.c
@@ -0,0 +1,450 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_timer_core.c $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_timer_core.c
+/// \brief PK portable kernel timer handler
+///
+/// This file contains core routines that would be needed by any application
+/// that requires PK timer support at runtime.
+///
+/// PK implements a 'tickless' kernel - all events are scheduled at absolute
+/// times of the PK timebase.  This approach gives the application full
+/// control over granularity of event scheduling.  Scheduling in absolute time
+/// opens up the possibility of scheduling events "in the past".  PK
+/// uniformly handles this case by scheduling "past" events to occur 1
+/// timebase tick in the future, so that timer callbacks are always run in the
+/// expected interrupt context.
+///
+/// PK implements the time queue as a simple unordered list of events, plus a
+/// dedicated variable that holds the earliest timeout of any event in the
+/// list.  This is thought to be an appropriate data structure for the
+/// following reasons:
+///
+/// - PK applications will be small and will not schedule a large number of
+/// events.  Therefore the cost of scanning the list each time an event times
+/// out is balanced against the cost of maintaining the list as a sorted data
+/// structure each time an event is added or removed from the event queue.
+///
+/// - PK applications may schedule and cancel many, many more events (safety
+/// timeouts) than are ever allowed to expire. Events can be added and deleted
+/// from the simple DEQUE very quickly since there is no sorting
+/// overhead.
+///
+/// Events are added to the queue simply by placing them at the end of the
+/// queue.  If the new event times out earlier than the previous earliest
+/// event, the hardware timeout is rescheduled for the new event time.  Events
+/// are deleted from the queue (cancelled) simply by deleting them.  Deletion
+/// does not affect the hardware timeout, even if the deleted event would have
+/// been the next to time out.  It is not an error for the timer handler to
+/// take a timer interrupt and find no events pending.  Pending events can
+/// also be rescheduled in place.
+///
+/// When a timeout occurs the event list is scanned from the beginning, and
+/// any event that has timed out has its callback processed.
+/// Since event and callback processing take
+/// time, the list is potentially scanned multiple times until there are no
+/// more timed-out events in the list.
+///
+/// Note that callbacks are not necessarily processed in time-order.  In this
+/// sense the PK time queue is like a traditional tick-based time queue in
+/// that events are effectively lumped into groups of events that time out
+/// together.  In a tick-based kernel the 'lump' is the tick interval; here
+/// the 'lump' is a variable interval that corresponds to the time it takes to
+/// process the entire event list.
+///
+/// Timer callbacks are typically run with interrupt preemption enabled.
+/// Special callbacks may run without preemption.  This is the only part of
+/// the PK kernel where data structures of indeterminate size are processed.
+/// During processing of the event list by the timer interrupt handler, the
+/// consideration of each event always includes a window of preemptability.
+
+#define __PK_TIMER_CORE_C__
+
+#include "pk.h"
+
+// Declare the timer bottom half handler
+static PK_BH_HANDLER(__pk_timer_bh_handler);
+
+// Define the timer bottom half handler that the interrupt handler will
+// schedule
+PK_BH_STATIC_CREATE(pk_timer_bh, __pk_timer_bh_handler, 0);
+
+
+// This routine is only used in this file, and will always be called in a
+// critical section.
+
+static inline int
+timer_active(PkTimer* timer)
+{
+    return pk_deque_is_queued((PkDeque*)timer);
+}
+
+
+// This is the kernel version of pk_timer_cancel().
+//
+// This routine is used here and by thread and semaphore routines.
+// External interrupts must be disabled at entry.
+//
+// If the timer is active, then there is a special case if we are going to
+// delete the 'cursor' - that is the timer that __pk_timer_handler() is going
+// to handle next.  In this case we need to move the cursor to the next timer
+// in the queue.
+//
+//  Note that cancelling a timer does not cause a re-evaluation of the next
+//  timeout.  This will happen naturally when the current timeout expires.
+
+int
+__pk_timer_cancel(PkTimer* timer)
+{
+    int rc;
+    PkDeque* timer_deque = (PkDeque*)timer;
+    PkTimeQueue* tq = &__pk_time_queue;
+
+    if (!timer_active(timer))
+    {
+
+        rc = -PK_TIMER_NOT_ACTIVE;
+
+    }
+    else
+    {
+
+        if (timer_deque == tq->cursor)
+        {
+            tq->cursor = tq->cursor->next;
+        }
+
+        pk_deque_delete(timer_deque);
+        rc = 0;
+    }
+
+    return rc;
+}
+
+
+// This is the kernel version of pk_timer_schedule().
+//
+// This routine is used here and by thread and semaphore routines.
+// interrupts must be disabled at entry.
+//
+// Unless the timer is already active it is enqueued in the doubly-linked
+// timer list by inserting the timer at the end of the queue. Then the
+// hardware timeout is scheduled if necessary. If the time queue 'cursor' != 0
+// we are in the midst of processing the time queue, and the end of time queue
+// processing will schedule the next hardware timemout.
+
+void
+__pk_timer_schedule(PkTimer* timer)
+{
+    PkTimeQueue* tq = &__pk_time_queue;
+
+    if (!timer_active(timer))
+    {
+        pk_deque_push_back((PkDeque*)tq, (PkDeque*)timer);
+    }
+
+    if (timer->timeout < tq->next_timeout)
+    {
+        tq->next_timeout = timer->timeout;
+
+        if (tq->cursor == 0)
+        {
+            __pk_schedule_hardware_timeout(tq->next_timeout);
+        }
+    }
+}
+
+
+// The tickless timer mechanism has timed out.  Note that due to timer
+// deletions and other factors, there may not actually be a timer in the queue
+// that has timed out - but it doesn't matter (other than for efficiency).
+//
+// This routine must not be entered reentrantly.
+//
+// First, time out any timers that have expired.  Timers in the queue are
+// unordered, so we have to check every one.  Since passing through the
+// loop takes time, we may have to make multiple passes until we know
+// that there are no timers in the queue that have already timed
+// out. Note that it would also work to only go through the loop once and
+// let the hardware scheduler take care of looping, but that would imply
+// more overhead than the current implementation.
+//
+// On each pass through the loop tq->next_timeout computes the minimum timeout
+// of events remaining in the queue.  This is the only part of the kernel that
+// searches a list of indefinite length. Kernel interrupt latency is mitigated
+// by running this function as a bottom half.  As such, interrupts are only
+// disabled when explicitly requested.
+//
+// Because interrupt preemption is enabled during processing, and preempting
+// handlers may invoke time queue operations, we need to establish a pointer
+// to the next entry to be examined (tq->cursor) before enabling interupts.
+// It's possible that this pointer will be changed by other interrupt handlers
+// that cancel the timer pointed to by tq->cursor.
+//
+// The main loop iterates on the PkDeque form of the time queue, casting each
+// element back up to the PkTimer as it is processed.
+
+static void
+__pk_timer_bh_handler(void* arg)
+{
+    PkMachineContext ctx;
+    PkTimeQueue* tq;
+    PkTimebase now;
+    PkTimer* timer;
+    PkDeque* timer_deque;
+    PkTimerCallback callback;
+
+    tq = &__pk_time_queue;
+
+    // Check if we entered the function while it was running in another context.
+    if (PK_ERROR_CHECK_KERNEL)
+    {
+        if (tq->cursor != 0)
+        {
+            PK_PANIC(PK_TIMER_HANDLER_INVARIANT);
+        }
+    }
+
+    pk_critical_section_enter(&ctx);
+
+    while ((now = pk_timebase_get()) >= tq->next_timeout)
+    {
+        tq->next_timeout = PK_TIMEBASE_MAX;
+        timer_deque = ((PkDeque*)tq)->next;
+
+        // Iterate through the entire timer list, calling the callback of
+        // timed-out elements and finding the timer that will timeout next,
+        // which is stored in tq->next_timeout.
+        while (timer_deque != (PkDeque*)tq)
+        {
+
+            timer = (PkTimer*)timer_deque;
+
+            // Setting this to a non-zero value indicates we are in the middle
+            // of processing the time queue.
+            tq->cursor = timer_deque->next;
+
+            if (timer->timeout <= now)
+            {
+
+                // The timer timed out.  It is removed from the queue.
+                //
+                // The callback may be made with interrupt preemption enabled
+                // or disabled.  However to mitigate kernel interrupt latency
+                // we go ahead and open up to interrupts after the callback if
+                // the callback itself was not preemptible.
+
+                pk_deque_delete(timer_deque);
+
+                pk_critical_section_exit(&ctx);
+
+                callback = timer->callback;
+
+                if (callback)
+                {
+                    callback(timer->arg);
+                }
+
+            }
+            else
+            {
+
+                // This timer has not timed out.  Its timeout will simply
+                // participate in the computation of the next timeout.
+                tq->next_timeout = MIN(timer->timeout, tq->next_timeout);
+                pk_critical_section_exit(&ctx);
+            }
+
+            timer_deque = tq->cursor;
+            pk_critical_section_enter(&ctx);
+        }
+
+        // Time has passed since we checked the time.  Loop back
+        // to check the time again and see if enough time has passed
+        // that the next timer has timed out too.
+    }
+
+    pk_critical_section_exit(&ctx);
+
+    // This marks that we are no longer processing the time queue
+    tq->cursor = 0;
+
+    // Finally, reschedule the next timeout
+    __pk_schedule_hardware_timeout(tq->next_timeout);
+}
+
+
+void
+__pk_timer_handler(void)
+{
+    //schedule the timer bottom half handler which
+    //is preemptible.
+    pk_bh_schedule(&pk_timer_bh);
+}
+
+
+/// Schedule a timer for an interval relative to the current time.
+///
+/// \param timer The PkTimer to schedule.
+///
+/// \param interval The timer will be scheduled to time out at the current
+/// time (pk_timebase_get()) plus this \a interval.
+///
+/// Once created with pk_timer_create() a timer can be \e scheduled, which
+/// queues the timer in the kernel time queue.  It is not an error to call \c
+/// pk_timer_schedule() on a timer that is already scheduled in the time
+/// queue - the timer is simply rescheduled with the new characteristics.
+///
+/// Return values other than PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_INVALID_TIMER_AT_SCHEDULE A a null (0) pointer was provided as
+/// the \a timer argument.
+///
+
+int
+pk_timer_schedule(PkTimer*    timer,
+                  PkInterval interval)
+{
+    PkMachineContext ctx;
+    PkTimebase  timeout = pk_timebase_get() + PK_INTERVAL_SCALE(interval);
+
+    pk_critical_section_enter(&ctx);
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(timer == 0, PK_INVALID_TIMER_AT_SCHEDULE);
+    }
+
+    timer->timeout = timeout;
+    __pk_timer_schedule(timer);
+
+    pk_critical_section_exit(&ctx);
+
+    return PK_OK;
+}
+
+
+/// Cancel (dequeue) a timer.
+///
+/// \param timer The PkTimer to cancel.
+///
+/// Timers can be canceled at any time.  It is never an error to call
+/// pk_timer_cancel() on an PkTimer object after it is created. Memory used
+/// by an PkTimer can be safely reused for another purpose after a successful
+/// call ofpk_timer_cancel().
+///
+/// Return values other than PK_OK (0) are not necessarily errors; see \ref
+/// pk_errors
+///
+/// The following return codes are non-error codes:
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_TIMER_NOT_ACTIVE The \a timer is not currently scheduled,
+/// i.e. it was never scheduled or has timed out.  This code is returned for
+/// information only and is not considered an error.
+///
+/// The following return codes are  error codes:
+///
+/// \retval -PK_INVALID_TIMER_AT_CANCEL The \a timer is a null (0) pointer.
+///
+
+int
+pk_timer_cancel(PkTimer* timer)
+{
+    PkMachineContext ctx;
+    int rc = PK_OK;
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(timer == 0, PK_INVALID_TIMER_AT_CANCEL);
+    }
+
+    pk_critical_section_enter(&ctx);
+
+    rc = __pk_timer_cancel(timer);
+
+    pk_critical_section_exit(&ctx);
+
+    return rc;
+}
+
+
+/// Get information about a timer.
+///
+/// \param timer The PkTimer to query
+///
+/// \param timeout The API returns the absolute timeout of the timer through
+/// this pointer.  If the timer is active, this is the current timeout.  If
+/// the timer has timed out then this is the previous absolute timeout.  If
+/// the timer was never scheduled this will be 0.  The caller can set this
+/// parameter to the null pointer (0) if this information is not required.
+///
+/// \param active If the value returned through this pointer is 1 then the
+/// timer is active (currently scheduled), otherwise the value will be 0
+/// indicating an inactive timer. The caller can set this parameter to the
+/// null pointer (0) if this information is not required.
+///
+/// The information returned by this API can only be guaranteed consistent if
+/// the API is called from a critical section.
+///
+/// Return values other than PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_INVALID_TIMER_AT_INFO The \a timer is a null (0) pointer.
+
+int
+pk_timer_info_get(PkTimer*    timer,
+                  PkTimebase* timeout,
+                  int*         active)
+
+{
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(timer == 0, PK_INVALID_TIMER_AT_INFO);
+    }
+
+    if (timeout)
+    {
+        *timeout = timer->timeout;
+    }
+
+    if (active)
+    {
+        *active = timer_active(timer);
+    }
+
+    return PK_OK;
+}
+
+#undef __PK_TIMER_CORE_C__
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pk_timer_init.c b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_timer_init.c
new file mode 100644
index 00000000..595fb376
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pk_timer_init.c
@@ -0,0 +1,87 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/kernel/pk_timer_init.c $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_timer_init.c
+/// \brief PK timer initialization
+///
+/// The entry points in this file might only be used during initialization of
+/// the application.  In this case the code space for these routines could be
+/// recovered and reused after initialization.
+
+#include "pk.h"
+
+
+/// Create (initialize) a timer.
+///
+/// \param timer The PkTimer to initialize.
+///
+/// \param callback The timer callback
+///
+/// \param arg Private data provided to the callback.
+///
+/// Once created with pk_timer_create() a timer can be scheduled with
+/// pk_timer_schedule() or pk_timer_schedule_absolute(), which queues the
+/// timer in the kernel time queue.  Timers can be cancelled by a call of
+/// pk_timer_cancel().
+///
+/// Timers created with pk_timer_create() are always run as
+/// bottom-half handlers with interrupt preemption enabled. Timer callbacks are
+/// free to enter critical sections if required, but must
+/// always exit with interrupts enabled.
+///
+/// Caution: PK has no way to know if an PkTimer structure provided to
+/// pk_timer_create() is safe to use as a timer, and will silently modify
+/// whatever memory is provided.
+///
+/// Return values other then PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_INVALID_TIMER_AT_CREATE The \a timer is a null (0) pointer.
+
+int
+pk_timer_create(PkTimer*         timer,
+                PkTimerCallback callback,
+                void*             arg)
+{
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF((timer == 0), PK_INVALID_TIMER_AT_CREATE);
+    }
+
+    pk_deque_element_create((PkDeque*)timer);
+    timer->timeout = 0;
+    timer->callback = callback;
+    timer->arg = arg;
+
+    return PK_OK;
+}
+
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/kernel/pkkernelfiles.mk b/src/import/chips/p9/procedures/ppe/pk/kernel/pkkernelfiles.mk
new file mode 100644
index 00000000..58c758e0
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/kernel/pkkernelfiles.mk
@@ -0,0 +1,58 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/ppe/pk/kernel/pkkernelfiles.mk $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file pkkernelfiles.mk
+#
+#  @brief mk for including architecture independent pk object files
+#
+#  @page ChangeLogs Change Logs
+#  @section pkkernelfiles.mk
+#  @verbatim
+#
+#
+# Change Log ******************************************************************
+# Flag     Defect/Feature  User        Date         Description
+# ------   --------------  ----------  ------------ -----------
+#
+# @endverbatim
+#
+##########################################################################
+# Include
+##########################################################################
+
+
+##########################################################################
+# Object Files 
+##########################################################################
+PK-C-SOURCES = pk_core.c pk_init.c pk_stack_init.c pk_bh_core.c pk_debug_ptrs.c
+
+PK-TIMER-C-SOURCES = pk_timer_core.c pk_timer_init.c
+
+PK-THREAD-C-SOURCES = pk_thread_init.c pk_thread_core.c pk_thread_util.c \
+	 pk_semaphore_init.c pk_semaphore_core.c
+
+PK_TIMER_OBJECTS=$(PK-TIMER-C-SOURCES:.c=.o)
+PK_THREAD_OBJECTS=$(PK-THREAD-C-SOURCES:.c=.o)
+PK_OBJECTS = $(PK-C-SOURCES:.c=.o)
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/Makefile b/src/import/chips/p9/procedures/ppe/pk/ppe42/Makefile
new file mode 100644
index 00000000..60f8d7f8
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/Makefile
@@ -0,0 +1,50 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/ppe/pk/ppe42/Makefile $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+# This Makefile is designed to be invoked with the -I argument set to
+#  the location of the "pk.mk" for the build
+
+include img_defs.mk
+include pkppe42files.mk
+
+ifeq "$(PK_TIMER_SUPPORT)" "1"
+PPE42_OBJECTS += ${PPE42-TIMER-C-SOURCES:.c=.o} ${PPE42-TIMER-S-SOURCES:.S=.o}
+endif
+
+ifeq "$(PK_THREAD_SUPPORT)" "1"
+PPE42_OBJECTS += ${PPE42-THREAD-C-SOURCES:.c=.o} ${PPE42-THREAD-S-SOURCES:.S=.o}
+endif
+
+OBJS := $(addprefix $(OBJDIR)/, $(PPE42_OBJECTS))
+
+all: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d) 
+endif
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/div64.S b/src/import/chips/p9/procedures/ppe/pk/ppe42/div64.S
new file mode 100644
index 00000000..cf19fa6e
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/div64.S
@@ -0,0 +1,272 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/div64.S $             */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved --  Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+                
+/// \file div64.S
+/// \brief Unsigned 64/64 bit division
+///
+/// This is IBM code, originally part of OS Open.  The code has been slightly
+/// modified from its original form, both to be compatible with PK and to
+/// change the function prototype slightly.
+///
+/// The code was provided by Matt Tyrlik in Raleigh.
+
+/* @#START#@
+**
+**      PSCN (Power Service and Control Network)
+**      Cage Controller OS Open Code
+**
+**      (C) Copyright International Business Machines Corporation 2002
+**      All Rights Reserved
+**      Licensed Material  -  Program Property of I B M
+**      Refer to copyright instructions: Form G120-2083
+**
+** Module:
+**      div64.s
+**
+** Description:
+**      Divide 64 bit unsigned values on 32 bit CPU
+**      div64(uint64_t dividen, uint64_t divisor, 
+**            uint64_t *quotient, uint64_t *remainder)
+**      
+**      Original source from:
+**      "The PowerPC Compiler Writer's Guide", pp62-65 by
+**      Steve Hoxey, Faraydon Karim, Bill Hay, Hank Warray,
+**      published by Warthman Associates, 240 Hamilton Avenue,
+**      Palo Alto, CA 94301, USA, 1996 for IBM.
+**      ISBN 0-9649654-0-2.
+**
+**      This version checks for divisor equal to zero.
+**
+** Environment:
+**      OS Open (XCOFF)
+**
+** Linkage:
+**      AIX 4.3.3
+**
+** @author
+**      Thomas Richter
+**
+** History:
+** Date      Author      Description
+** -----------------------------------------------------------------------------
+** 23-Sep-02 Richter     Created
+**
+** @#END#@*/
+
+        .nolist
+#include "pk.h"
+        .list
+        
+        .global_function __ppe42_udiv64
+
+        /*
+        ** Code comment notation: 
+        ** msw = most-significant (high-order) word, i.e. bits 0..31 
+        ** lsw = least-significant (low-order) word, i.e. bits 32..63
+        ** LZ = Leading Zeroes 
+        ** SD = Significant Digits 
+        ** 
+        ** R3:R4 = Input parameter, dividend.
+        ** R5:R6 = Input parameter, divisor.
+        ** R7 = Output parameter, pointer to quotient.
+        ** R8 = Output parameter, pointer to remainder.
+        **
+        ** Pointer arguments point to a uint64_t.
+        **
+        ** Division is achieved using a shift/rotate/substract algorithsm
+        ** described above.
+        ** The registers are used as follows:
+        ** R3:R4 = dividend (upper 32bits:lower 32bits)
+        ** R5:R6 = divisor (upper 32bits:lower 32bits)
+        ** 
+        ** R7:R8 = temporary 64 bit register (upper 32bits:lower 32bits)
+        ** count the number of leading 0s in the dividend 
+        **
+        ** Here is the description from the book. The dividend is placed
+        ** in the low order part of a 4 (32bit) register sequence named
+        ** tmp-high:tmp-low:dividend-high:dividend:low or tmp:dvd for short.
+        ** 
+        ** Each iteration includes the following steps:
+        ** 1. Shift tmp:dvd by one bit to the left.
+        ** 2. Subtract the divisor from tmp. This is a 64 bit operation.
+        ** 3. If result is greater than or equal, place result in tmp and
+        **    set the low order bit of dividend
+        ** 4. If result is negative, do not modify tmp and
+        **    clear the low order bit of dividend
+        ** 5. If the number of iterations is less than the width of the
+        **    dividend, goto step 1.
+        **
+        ** Now the algorithm can be improved by reducing the number of
+        ** iterations to be executed.
+        ** 1. Calculate the leading zeroes of the dividend.
+        ** 2. Calculate the leading zeroes of the divisor.
+        ** 3. Calculate the significant ones of the dividend.
+        ** 4. Calculate the significant ones of the divisor.
+        **
+        ** Initial tmp := dvd >> (dvd.SD - dvs.SD)
+        ** Initial dvd := dvd << (dvd.LZ + dvs.SD)
+        ** Loops: dvd.SD - dvs.SD.
+        **
+        ** Warning: Special care must be taken if dvd.LZ == dvs.LZ. The code
+        ** below does so by reducing the number of dvs.SD by one. This leads
+        ** to the loop being executed 1 more time than really necessary,
+        ** but avoids to check for the case when dvd.LZ == dvs.LZ.
+        ** This case (dvd.LZ == dvs.LZ) only checks for the number of leading
+        ** zeroes, but does not check if dividend is really greater than the
+        ** divisor.
+        ** Consider 16/17, both have an LZ value of 59. The code sets dvs.LZ
+        ** 60. This resutls in dvs.SD to 4, thus one iteration after which
+        ** tmp is the remainder 16.
+        */
+
+__ppe42_udiv64: // PK
+       
+        /* push R30 & R31 onto the stack */
+        stwu    r1, -16(r1)
+        stvd    r30, 8(r1)
+
+        /* Save result pointers on volatile spare registers */
+        ori     r31, r8, 0              /* Save remainder address */
+        ori     r30, r7, 0              /* Save quotient address */
+
+        /* count the number of leading 0s in the dividend */
+        cmpwi   cr0, r3, 0      /* dvd.msw == 0? */
+        cntlzw  r0, r3          /* R0 = dvd.msw.LZ */
+        cntlzw  r9, r4          /* R9 = dvd.lsw.LZ */
+        bne     cr0, lab1       /* if(dvd.msw == 0) dvd.LZ = dvd.msw.LZ */
+        addi    r0, r9, 32      /* dvd.LZ = dvd.lsw.LZ + 32 */
+lab1: 
+        /* count the number of leading 0s in the divisor */
+        cmpwi   cr0, r5, 0      /* dvd.msw == 0? */
+        cntlzw  r9, r5          /* R9 = dvs.msw.LZ */
+        cntlzw  r10, r6         /* R10 = dvs.lsw.LZ */
+        bne     cr0, lab2       /* if(dvs.msw == 0) dvs.LZ = dvs.msw.LZ */
+        cmpwi   cr0, r6, 0      /* dvd.lsw == 0? */
+        beq     cr0, lab10      /* dvs.msw == 0 */
+        addi    r9, r10, 32     /* dvs.LZ = dvs.lsw.LZ + 32 */
+
+lab2:
+        /* Determine shift amounts to minimize the number of iterations  */
+        cmpw    cr0, r0, r9     /* Compare dvd.LZ to dvs.LZ */
+        subfic  r10, r0, 64     /* R10 = dvd.SD */
+        bgt     cr0, lab9       /* if(dvs > dvd) quotient = 0 */
+        addi    r9, r9, 1       /* See comment above. ++dvs.LZ (or --dvs.SD) */
+        subfic  r9, r9, 64      /* R9 = dvs.SD */
+        add     r0, r0, r9      /* (dvd.LZ + dvs.SD) = left shift of dvd for */
+                                /* initial dvd */
+        subf    r9, r9, r10     /* (dvd.SD - dvs.SD) = right shift of dvd for */
+                                /* initial tmp */
+        mtctr   r9              /* Number of iterations = dvd.SD - dvs.SD */
+        
+        /* R7:R8 = R3:R4 >> R9 */
+        cmpwi   cr0, r9, 32     /* compare R9 to 32 */
+        addi    r7, r9, -32
+        blt     cr0, lab3       /* if(R9 < 32) jump to lab3 */
+        srw     r8, r3, r7      /* tmp.lsw = dvd.msw >> (R9 - 32) */
+        addi    r7, r0, 0       /* tmp.msw = 0 */
+        b       lab4 
+
+lab3: 
+        srw     r8, r4, r9      /* R8 = dvd.lsw >> R9 */
+        subfic  r7, r9, 32 
+        slw     r7,r3,r7        /* R7 = dvd.msw << 32 - R9 */
+        or      r8, r8,r7       /* tmp.lsw = R8 | R7 */
+        srw     r7,r3,r9        /* tmp.msw = dvd.msw >> R9 */
+lab4:
+        /* R3:R4 = R3:R4 << R0 */
+        cmpwi   cr0, r0, 32     /* Compare R0 to 32 */
+        addic   r9, r0, -32 
+        blt     cr0, lab5       /* if(R0 < 32) jump to lab5 */
+        slw     r3, r4, r9      /* dvd.msw = dvd.lsw << R9 */
+        addi    r4, r0, 0       /* dvd.lsw = 0 */
+        b       lab6 
+
+lab5: 
+        slw     r3, r3, r0      /* r3 = dvd.msw << r0 */
+        subfic  r9, r0, 32 
+        srw     r9, r4, r9      /* r9 = dvd.lsw >> 32 - r0 */
+        or      r3, r3, r9      /* dvd.msw = r3 | r9 */
+        slw     r4, r4, r0      /* dvd.lsw = dvd.lsw << r0 */
+lab6: 
+        /* Restoring division shift and subtract loop */
+        addi    r10, r0, -1     /* r10 = -1 */
+        addic   r7, r7, 0       /* Clear carry bit before loop starts */
+lab7: 
+        /*
+        ** tmp:dvd is considered one large register 
+        ** each portion is shifted left 1 bit by adding it to itself 
+        ** adde sums the carry from the previous and creates a new carry 
+        */
+        adde    r4, r4, r4      /* Shift dvd.lsw left 1 bit */
+        adde    r3, r3, r3      /* Shift dvd.msw to left 1 bit */
+        adde    r8, r8, r8      /* Shift tmp.lsw to left 1 bit */
+        adde    r7, r7, r7      /* Shift tmp.msw to left 1 bit */
+        subfc   r0, r6, r8      /* tmp.lsw - dvs.lsw */
+        subfe.  r9, r5, r7      /* tmp.msw - dvs.msw */
+        blt     cr0, lab8       /* if(result < 0) clear carry bit */
+        or      r8, r0, r0      /* Move lsw */
+        or      r7, r9, r9      /* Move msw */
+        addic   r0, r10, 1      /* Set carry bit */
+
+lab8: 
+        bdnz    lab7 
+
+        /* Write quotient and remainder */
+        adde    r4, r4, r4      /* quo.lsw (lsb = CA) */
+        adde    r3, r3, r3      /* quo.msw (lsb from lsw) */
+        stw     r4, 4(r30)
+        stw     r3, 0(r30)
+        stw     r8, 4(r31)      /* rem.lsw */
+        stw     r7, 0(r31)      /* rem.msw */
+        b       lab11
+
+lab9:
+        /* Qoutient is 0, divisor > dividend */
+        addi    r0, r0, 0
+        stw     r3, 0(r31)      /* Store remainder */
+        stw     r4, 4(r31)
+        stw     r0, 0(r30)      /* Set quotient to zero */
+        stw     r0, 4(r30)
+        b       lab11
+
+lab10:
+        /* Divisor is 0 */
+        addi    r0, r0, -1
+        stw     r0, 0(r31)      /* Set remainder to zero */
+        stw     r0, 4(r31)
+        stw     r0, 0(r30)      /* Set quotient to zero */
+        stw     r0, 4(r30)
+
+lab11:
+        //pop r30 & r31 from stack
+        lvd     r30, 8(r1)
+        lwz     r1, 0(r1)
+        blr
+        .epilogue __ppe42_udiv64 
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/eabi.c b/src/import/chips/p9/procedures/ppe/pk/ppe42/eabi.c
new file mode 100644
index 00000000..140cc2be
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/eabi.c
@@ -0,0 +1,46 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/eabi.c $              */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// assuming link script instructs the c++ compiler to put
+// ctor_start_address and ctor_end_address in .rodata
+
+//extern void (*ctor_start_address)() __attribute__ ((section (".rodata")));
+//extern void (*ctor_end_address)() __attribute__((section(".rodata")));
+#ifdef __cplusplus
+    extern "C"
+#endif
+__attribute__((weak)) void __eabi()
+{
+    // This is the default eabi and can be overridden.
+    // eabi environment is already set up by the PK kernel
+    // Call static C++ constructors if you use C++ global/static objects
+
+    //void(**ctors)() = &ctor_start_address;
+    //while(ctors != &ctor_end_address)
+    //{
+    //    (*ctors)();
+    //    ctors++;
+    //}
+}
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/endian.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/endian.h
new file mode 100644
index 00000000..dade05cf
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/endian.h
@@ -0,0 +1,48 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/endian.h $            */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __ENDIAN_H__
+#define __ENDIAN_H__
+
+#ifndef __PPE42__
+    #include_next <endian.h>
+#else
+    // Currently not provided with PPE42 native compiler as PPE42
+    // is compiled with no clib support.
+    // endian.h provides:
+    //  htobe16,
+    //  htole16,
+    //  be16toh,
+    //  le16toh,
+    //  htobe32,
+    //  htole32,
+    //  be32toh,
+    //  le32toh,
+    //  htobe64,
+    //  htole64,
+    //  be64toh,
+    //  le64toh
+#endif
+
+#endif
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/math.c b/src/import/chips/p9/procedures/ppe/pk/ppe42/math.c
new file mode 100644
index 00000000..1cddc624
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/math.c
@@ -0,0 +1,206 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/math.c $              */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#include "ppe42math.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+unsigned long
+udivmodsi4(unsigned long num, unsigned long den, int modwanted)
+{
+    unsigned long bit = 1;
+    unsigned long res = 0;
+
+    while (den < num && bit && !(den & (1L << 31)))
+    {
+        den <<= 1;
+        bit <<= 1;
+    }
+
+    while (bit)
+    {
+        if (num >= den)
+        {
+            num -= den;
+            res |= bit;
+        }
+
+        bit >>= 1;
+        den >>= 1;
+    }
+
+    if (modwanted)
+    {
+        return num;
+    }
+
+    return res;
+}
+
+// 64 bit divide.  Note: TBD add when needed
+//unsigned long long __udivdi3(unsigned long long a, unsigned long long b)
+//{
+//    unsigned long long c = 0;
+//    return c;
+//}
+
+// 32 bit unsigned integer divide
+unsigned long __udivsi3(unsigned long a, unsigned long b)
+{
+    return udivmodsi4(a, b, 0);
+}
+
+// 32 bit modulus
+unsigned long __umodsi3(unsigned long a, unsigned long b)
+{
+    return udivmodsi4(a, b, 1);
+}
+
+// 32 bit signed divide
+int __divsi3(int _a, int _b)
+{
+    register unsigned long neg = 0;
+
+    if(_a & 0x80000000)
+    {
+        neg = !neg;
+        _a = (~_a) + 1;
+    }
+
+    if(_b & 0x80000000)
+    {
+        _b = (~_b) + 1;
+        neg = !neg;
+    }
+
+    int c = __udivsi3((unsigned long)_a, (unsigned long)_b);
+
+    if(neg)
+    {
+        c = (~c) + 1;
+    }
+
+    return c;
+}
+
+// 32 bit unsigned mutiply
+unsigned long __umulsi3(unsigned long _a, unsigned long _b)
+{
+    register unsigned long a = _a;
+    register unsigned long b = _b;
+    register unsigned long c;
+    register unsigned long d;
+    asm volatile("mullhwu %0, %1, %2" : "=r"(c) : "r"(a), "r"(b));
+    d = c;
+    c = a >> 16;
+    asm volatile("mullhwu %0, %1, %2" : "=r"(c) : "r"(c), "r"(b));
+    d += (c << 16);
+    c = b >> 16;
+    asm volatile("mullhwu %0, %1, %2" : "=r"(c) : "r"(c), "r"(a));
+    d += (c << 16);
+    return d;
+}
+
+// 32 bit signed multiply
+unsigned int __mulsi3(unsigned int _a, unsigned int _b)
+{
+    register unsigned long neg = 0;
+    register unsigned long a = _a;
+    register unsigned long b = _b;
+    register unsigned long c;
+    register unsigned long d;
+
+    if(a & 0x80000000)
+    {
+        a = (~a) + 1;
+        neg = !neg;
+    }
+
+    if(b & 0x80000000)
+    {
+        b = (~b) + 1;
+        neg = !neg;
+    }
+
+    asm volatile("mullhwu %0, %1, %2" : "=r"(c) : "r"(a), "r"(b));
+    d = c;
+    c = a >> 16;
+    asm volatile("mullhwu %0, %1, %2" : "=r"(c) : "r"(c), "r"(b));
+    d += (c << 16);
+    c = b >> 16;
+    asm volatile("mullhwu %0, %1, %2" : "=r"(c) : "r"(c), "r"(a));
+    d += (c << 16);
+
+    if(neg)
+    {
+        d = (~d) + 1;
+    }
+
+    return d;
+}
+
+// 64 bit signed multiply
+unsigned long long __muldi3(unsigned long long _a, unsigned long long _b)
+{
+    unsigned long long sum = 0;
+
+    while(_a)
+    {
+        if(_a & 1)
+        {
+            sum += _b;
+        }
+
+        _a >>= 1;
+        _b <<= 1;
+    }
+
+    return sum;
+}
+
+//float __mulsf3(float _a , float _b)
+//{
+//    // floating point math
+//    return 0.0;
+//}
+
+//float __subsf3(float _a, float _b)
+//{
+//    // floating point sub
+//    return 0.0;
+//}
+
+//unsigned long __fixsfsi (float _a)
+//{
+//    // float to int
+//    return 0;
+//}
+
+#ifdef __cplusplus
+};
+#endif
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/pk_panic_codes.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/pk_panic_codes.h
new file mode 100644
index 00000000..0e079657
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/pk_panic_codes.h
@@ -0,0 +1,340 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/pk_panic_codes.h $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PK_PANIC_CODES_H__
+#define __PK_PANIC_CODES_H__
+
+// On PPE42, PANIC codes are stored as part of the trap word instruction.
+// tw 31, RA, RB  Where RA and RB would used to encode the trap code.
+// There are 16 valid gprs on PP42, so this gives 256 possible trap codes.
+// The trap code is defined as a two byte code defined as 0xYYZZ where YY
+// is encoded into the RA field and ZZ is incoded into the RB field
+// YY and ZZ are limited to the values:
+//   00,01,02,03,04,05,06,07,08,09,0a,0d,1c,1d,1e,1f (valid gpr ids)
+//
+// To add a new panic code, select an unused values and rename it.
+// This enum contains all the valid values that can be used. Using a
+// panic code not in this list will result in a compiler/assembler error.
+#ifndef __ASSEMBLER__
+
+typedef enum
+{
+    PPE42_MACHINE_CHECK_PANIC           = 0x0001,
+    PPE42_DATA_STORAGE_PANIC            = 0x0002,
+    PPE42_INSTRUCTION_STORAGE_PANIC     = 0x0003,
+    PPE42_DATA_ALIGNMENT_PANIC          = 0x0004,
+    PK_BOOT_VECTORS_NOT_ALIGNED         = 0x0005,
+    PK_DEFAULT_IRQ_HANDLER              = 0x0006,
+    PK_DEFAULT_SPECIAL_HANDLER          = 0x0007,
+    PPE42_PHANTOM_INTERRUPT             = 0x0008,
+    PPE42_ILLEGAL_INSTRUCTION           = 0x0009,
+    PK_UNUSED_000a                      = 0x000a,
+    PK_UNUSED_000d                      = 0x000d,
+    PK_UNUSED_001c                      = 0x001c,
+    PK_UNUSED_001d                      = 0x001d,
+    PK_UNUSED_001e                      = 0x001e,
+    PK_UNUSED_001f                      = 0x001f,
+
+    // API return codes
+    PK_ILLEGAL_CONTEXT_THREAD_CONTEXT   = 0x0100,
+    PK_ILLEGAL_CONTEXT_INTERRUPT_CONTEXT = 0x0101,
+    PK_ILLEGAL_CONTEXT_THREAD           = 0x0102,
+    PK_ILLEGAL_CONTEXT_TIMER            = 0x0103,
+    PK_INVALID_THREAD_AT_RESUME1        = 0x0104,
+    PK_INVALID_THREAD_AT_RESUME2        = 0x0105,
+    PK_INVALID_THREAD_AT_SUSPEND1       = 0x0106,
+    PK_INVALID_THREAD_AT_SUSPEND2       = 0x0107,
+    PK_INVALID_THREAD_AT_DELETE         = 0x0108,
+    PK_INVALID_THREAD_AT_INFO           = 0x0109,
+    PK_INVALID_THREAD_AT_CHANGE         = 0x010a,
+    PK_INVALID_THREAD_AT_SWAP1          = 0x010d,
+    PK_INVALID_THREAD_AT_SWAP2          = 0x011c,
+    PK_INVALID_THREAD_AT_CREATE         = 0x011d,
+    PK_INVALID_SEMAPHORE_AT_POST        = 0x011e,
+    PK_INVALID_SEMAPHORE_AT_PEND        = 0x011f,
+    PK_INVALID_SEMAPHORE_AT_RELEASE     = 0x0200,
+    PK_INVALID_SEMAPHORE_AT_INFO        = 0x0201,
+    PK_INVALID_SEMAPHORE_AT_CREATE      = 0x0202,
+    PK_INVALID_TIMER_AT_SCHEDULE        = 0x0203,
+    PK_INVALID_TIMER_AT_CANCEL          = 0x0204,
+    PK_INVALID_TIMER_AT_INFO            = 0x0205,
+    PK_INVALID_TIMER_AT_CREATE          = 0x0206,
+    PK_INVALID_ARGUMENT_IRQ_SETUP       = 0x0207,
+    PK_INVALID_ARGUMENT_IRQ_HANDLER     = 0x0208,
+    PK_INVALID_ARGUMENT_INTERRUPT       = 0x0209,
+    PK_INVALID_ARGUMENT_CONTEXT_SET     = 0x020a,
+    PK_INVALID_ARGUMENT_CONTEXT_GET     = 0x020d,
+    PK_INVALID_ARGUMENT_FIT             = 0x021c,
+    PK_INVALID_ARGUMENT_WATCHDOG        = 0x021d,
+    PK_INVALID_ARGUMENT_INIT            = 0x021e,
+    PK_INVALID_ARGUMENT_SEMAPHORE       = 0x021f,
+    PK_INVALID_ARGUMENT_THREAD_CHANGE   = 0x0300,
+    PK_INVALID_ARGUMENT_THREAD_PRIORITY = 0x0301,
+    PK_INVALID_ARGUMENT_THREAD1         = 0x0302,
+    PK_INVALID_ARGUMENT_THREAD2         = 0x0303,
+    PK_INVALID_ARGUMENT_THREAD3         = 0x0304,
+    PK_STACK_OVERFLOW                   = 0x0305,
+    PK_TIMER_ACTIVE                     = 0x0306,
+    PK_TIMER_NOT_ACTIVE                 = 0x0307,
+    PK_PRIORITY_IN_USE_AT_RESUME        = 0x0308,
+    PK_PRIORITY_IN_USE_AT_CHANGE        = 0x0309,
+    PK_PRIORITY_IN_USE_AT_SWAP          = 0x030a,
+    PK_SEMAPHORE_OVERFLOW               = 0x030d,
+    PK_SEMAPHORE_PEND_NO_WAIT           = 0x031c,
+    PK_SEMAPHORE_PEND_TIMED_OUT         = 0x031d,
+    PK_SEMAPHORE_PEND_WOULD_BLOCK       = 0x031e,
+    PK_INVALID_DEQUE_SENTINEL           = 0x031f,
+    PK_INVALID_DEQUE_ELEMENT            = 0x0400,
+    PK_INVALID_OBJECT                   = 0x0401,
+
+    // PK Kernel panics
+    PK_NO_TIMER_SUPPORT                 = 0x0402,
+    PK_START_THREADS_RETURNED           = 0x0403,
+    PK_UNIMPLEMENTED                    = 0x0404,
+    PK_SCHEDULING_INVARIANT             = 0x0405,
+    PK_TIMER_HANDLER_INVARIANT          = 0x0406,
+    PK_THREAD_TIMEOUT_STATE             = 0x0407,
+
+    // PK
+    PK_UNUSED_0408                      = 0x0408,
+    PK_UNUSED_0409                      = 0x0409,
+    PK_UNUSED_040a                      = 0x040a,
+    PK_UNUSED_040d                      = 0x040d,
+    PK_UNUSED_041c                      = 0x041c,
+    PK_UNUSED_041d                      = 0x041d,
+    PK_UNUSED_041e                      = 0x041e,
+    PK_UNUSED_041f                      = 0x041f,
+
+    // Sync panic codes
+    SYNC_INVALID_OBJECT                 = 0x0500,
+    SYNC_INVALID_ARGUMENT               = 0x0501,
+    SYNC_BARRIER_PEND_TIMED_OUT         = 0x0502,
+    SYNC_BARRIER_OVERFLOW               = 0x0503,
+    SYNC_BARRIER_UNDERFLOW              = 0x0504,
+    SYNC_BARRIER_INVARIANT              = 0x0505,
+    SYNC_SHARED_UNDERFLOW               = 0x0506,
+
+    OCCHW_INSTANCE_MISMATCH             = 0x0507,
+    OCCHW_IRQ_ROUTING_ERROR             = 0x0508,
+    OCCHW_XIR_INVALID_POINTER           = 0x0509,
+    OCCHW_XIR_INVALID_GPE               = 0x050a,
+
+    PK_UNUSED_050d                      = 0x050d,
+    PK_UNUSED_051c                      = 0x051c,
+    PK_UNUSED_051d                      = 0x051d,
+    PK_UNUSED_051e                      = 0x051e,
+    PK_UNUSED_051f                      = 0x051f,
+
+    PK_UNUSED_0600                      = 0x0600,
+    PK_UNUSED_0601                      = 0x0601,
+    PK_UNUSED_0602                      = 0x0602,
+    PK_UNUSED_0603                      = 0x0603,
+    PK_UNUSED_0604                      = 0x0604,
+    PK_UNUSED_0605                      = 0x0605,
+    PK_UNUSED_0606                      = 0x0606,
+    PK_UNUSED_0607                      = 0x0607,
+    PK_UNUSED_0608                      = 0x0608,
+    PK_UNUSED_0609                      = 0x0609,
+    PK_UNUSED_060a                      = 0x060a,
+    PK_UNUSED_060d                      = 0x060d,
+    PK_UNUSED_061c                      = 0x061c,
+    PK_UNUSED_061d                      = 0x061d,
+    PK_UNUSED_061e                      = 0x061e,
+    PK_UNUSED_061f                      = 0x061f,
+
+    PK_UNUSED_0700                      = 0x0700,
+    PK_UNUSED_0701                      = 0x0701,
+    PK_UNUSED_0702                      = 0x0702,
+    PK_UNUSED_0703                      = 0x0703,
+    PK_UNUSED_0704                      = 0x0704,
+    PK_UNUSED_0705                      = 0x0705,
+    PK_UNUSED_0706                      = 0x0706,
+    PK_UNUSED_0707                      = 0x0707,
+    PK_UNUSED_0708                      = 0x0708,
+    PK_UNUSED_0709                      = 0x0709,
+    PK_UNUSED_070a                      = 0x070a,
+    PK_UNUSED_070d                      = 0x070d,
+    PK_UNUSED_071c                      = 0x071c,
+    PK_UNUSED_071d                      = 0x071d,
+    PK_UNUSED_071e                      = 0x071e,
+    PK_UNUSED_071f                      = 0x071f,
+
+    PK_UNUSED_0800                      = 0x0800,
+    PK_UNUSED_0801                      = 0x0801,
+    PK_UNUSED_0802                      = 0x0802,
+    PK_UNUSED_0803                      = 0x0803,
+    PK_UNUSED_0804                      = 0x0804,
+    PK_UNUSED_0805                      = 0x0805,
+    PK_UNUSED_0806                      = 0x0806,
+    PK_UNUSED_0807                      = 0x0807,
+    PK_UNUSED_0808                      = 0x0808,
+    PK_UNUSED_0809                      = 0x0809,
+    PK_UNUSED_080a                      = 0x080a,
+    PK_UNUSED_080d                      = 0x080d,
+    PK_UNUSED_081c                      = 0x081c,
+    PK_UNUSED_081d                      = 0x081d,
+    PK_UNUSED_081e                      = 0x081e,
+    PK_UNUSED_081f                      = 0x081f,
+
+    PK_UNUSED_0900                      = 0x0900,
+    PK_UNUSED_0901                      = 0x0901,
+    PK_UNUSED_0902                      = 0x0902,
+    PK_UNUSED_0903                      = 0x0903,
+    PK_UNUSED_0904                      = 0x0904,
+    PK_UNUSED_0905                      = 0x0905,
+    PK_UNUSED_0906                      = 0x0906,
+    PK_UNUSED_0907                      = 0x0907,
+    PK_UNUSED_0908                      = 0x0908,
+    PK_UNUSED_0909                      = 0x0909,
+    PK_UNUSED_090a                      = 0x090a,
+    PK_UNUSED_090d                      = 0x090d,
+    PK_UNUSED_091c                      = 0x091c,
+    PK_UNUSED_091d                      = 0x091d,
+    PK_UNUSED_091e                      = 0x091e,
+    PK_UNUSED_091f                      = 0x091f,
+
+    PK_UNUSED_0a00                      = 0x0a00,
+    PK_UNUSED_0a01                      = 0x0a01,
+    PK_UNUSED_0a02                      = 0x0a02,
+    PK_UNUSED_0a03                      = 0x0a03,
+    PK_UNUSED_0a04                      = 0x0a04,
+    PK_UNUSED_0a05                      = 0x0a05,
+    PK_UNUSED_0a06                      = 0x0a06,
+    PK_UNUSED_0a07                      = 0x0a07,
+    PK_UNUSED_0a08                      = 0x0a08,
+    PK_UNUSED_0a09                      = 0x0a09,
+    PK_UNUSED_0a0a                      = 0x0a0a,
+    PK_UNUSED_0a0d                      = 0x0a0d,
+    PK_UNUSED_0a1c                      = 0x0a1c,
+    PK_UNUSED_0a1d                      = 0x0a1d,
+    PK_UNUSED_0a1e                      = 0x0a1e,
+    PK_UNUSED_0a1f                      = 0x0a1f,
+
+    PK_UNUSED_0d00                      = 0x0d00,
+    PK_UNUSED_0d01                      = 0x0d01,
+    PK_UNUSED_0d02                      = 0x0d02,
+    PK_UNUSED_0d03                      = 0x0d03,
+    PK_UNUSED_0d04                      = 0x0d04,
+    PK_UNUSED_0d05                      = 0x0d05,
+    PK_UNUSED_0d06                      = 0x0d06,
+    PK_UNUSED_0d07                      = 0x0d07,
+    PK_UNUSED_0d08                      = 0x0d08,
+    PK_UNUSED_0d09                      = 0x0d09,
+    PK_UNUSED_0d0a                      = 0x0d0a,
+    PK_UNUSED_0d0d                      = 0x0d0d,
+    PK_UNUSED_0d1c                      = 0x0d1c,
+    PK_UNUSED_0d1d                      = 0x0d1d,
+    PK_UNUSED_0d1e                      = 0x0d1e,
+    PK_UNUSED_0d1f                      = 0x0d1f,
+
+    // The following are reserved for instance specific use.
+    // Each engine must define its own XXX_panic_codes.h
+    // Where XXX = SBE, CME, GPE0, GPE1, PGPE, SGPE
+    // They are listed here to show the valid trap values that
+    // can be used.
+
+    //_UNUSED_1c00                      = 0x1c00,
+    //_UNUSED_1c01                      = 0x1c01,
+    //_UNUSED_1c02                      = 0x1c02,
+    //_UNUSED_1c03                      = 0x1c03,
+    //_UNUSED_1c04                      = 0x1c04,
+    //_UNUSED_1c05                      = 0x1c05,
+    //_UNUSED_1c06                      = 0x1c06,
+    //_UNUSED_1c07                      = 0x1c07,
+    //_UNUSED_1c08                      = 0x1c08,
+    //_UNUSED_1c09                      = 0x1c09,
+    //_UNUSED_1c0a                      = 0x1c0a,
+    //_UNUSED_1c0d                      = 0x1c0d,
+    //_UNUSED_1c1c                      = 0x1c1c,
+    //_UNUSED_1c1d                      = 0x1c1d,
+    //_UNUSED_1c1e                      = 0x1c1e,
+    //_UNUSED_1c1f                      = 0x1c1f,
+
+    //_UNUSED_1d00                      = 0x1d00,
+    //_UNUSED_1d01                      = 0x1d01,
+    //_UNUSED_1d02                      = 0x1d02,
+    //_UNUSED_1d03                      = 0x1d03,
+    //_UNUSED_1d04                      = 0x1d04,
+    //_UNUSED_1d05                      = 0x1d05,
+    //_UNUSED_1d06                      = 0x1d06,
+    //_UNUSED_1d07                      = 0x1d07,
+    //_UNUSED_1d08                      = 0x1d08,
+    //_UNUSED_1d09                      = 0x1d09,
+    //_UNUSED_1d0a                      = 0x1d0a,
+    //_UNUSED_1d0d                      = 0x1d0d,
+    //_UNUSED_1d1c                      = 0x1d1c,
+    //_UNUSED_1d1d                      = 0x1d1d,
+    //_UNUSED_1d1e                      = 0x1d1e,
+    //_UNUSED_1d1f                      = 0x1d1f,
+
+    //_UNUSED_1e00                      = 0x1e00,
+    //_UNUSED_1e01                      = 0x1e01,
+    //_UNUSED_1e02                      = 0x1e02,
+    //_UNUSED_1e03                      = 0x1e03,
+    //_UNUSED_1e04                      = 0x1e04,
+    //_UNUSED_1e05                      = 0x1e05,
+    //_UNUSED_1e06                      = 0x1e06,
+    //_UNUSED_1e07                      = 0x1e07,
+    //_UNUSED_1e08                      = 0x1e08,
+    //_UNUSED_1e09                      = 0x1e09,
+    //_UNUSED_1e0a                      = 0x1e0a,
+    //_UNUSED_1e0d                      = 0x1e0d,
+    //_UNUSED_1e1c                      = 0x1e1c,
+    //_UNUSED_1e1d                      = 0x1e1d,
+    //_UNUSED_1e1e                      = 0x1e1e,
+    //_UNUSED_1e1f                      = 0x1e1f,
+
+    //_UNUSED_1f00                      = 0x1f00,
+    //_UNUSED_1f01                      = 0x1f01,
+    //_UNUSED_1f02                      = 0x1f02,
+    //_UNUSED_1f03                      = 0x1f03,
+    //_UNUSED_1f04                      = 0x1f04,
+    //_UNUSED_1f05                      = 0x1f05,
+    //_UNUSED_1f06                      = 0x1f06,
+    //_UNUSED_1f07                      = 0x1f07,
+    //_UNUSED_1f08                      = 0x1f08,
+    //_UNUSED_1f09                      = 0x1f09,
+    //_UNUSED_1f0a                      = 0x1f0a,
+    //_UNUSED_1f0d                      = 0x1f0d,
+    //_UNUSED_1f1c                      = 0x1f1c,
+    //_UNUSED_1f1d                      = 0x1f1d,
+    //_UNUSED_1f1e                      = 0x1f1e,
+    //_UNUSED_1f1f                      = 0x1f1f
+} pkPanicCode_t;
+
+#else
+
+/// Assembler specific panic codes
+#define PPE42_MACHINE_CHECK_PANIC           0x0001
+#define PPE42_DATA_STORAGE_PANIC            0x0002
+#define PPE42_INSTRUCTION_STORAGE_PANIC     0x0003
+#define PPE42_DATA_ALIGNMENT_PANIC          0x0004
+
+#define PK_BOOT_VECTORS_NOT_ALIGNED         0x0005
+#define PPE42_ILLEGAL_INSTRUCTION           0x001c
+
+
+
+#endif  // __ASSEMBLER__
+#endif
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/pk_port_types.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/pk_port_types.h
new file mode 100644
index 00000000..7a368d4e
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/pk_port_types.h
@@ -0,0 +1,65 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/pk_port_types.h $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PK_PORT_TYPES_H__
+#define __PK_PORT_TYPES_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved --  Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_port_types.h
+/// \brief Type definitions required by the PK port.
+///
+/// \todo GCC provides a portable version of cntlzw called __builtin_clz().
+/// We should make the PK priority queues portable by using this facility.
+///
+/// \todo I think that if more of the port-dependent types were moved here, we
+/// could break the circular dependencies in some of the header inclusion and
+/// simplify the way the PK/port/chip headers are included.
+
+/// An PkIrqId is an integer in the range of valid interrupts defined by the
+/// interrupt controller.
+
+typedef uint8_t PkIrqId;
+
+/// PK requires the port to define the type PkThreadQueue, which is a
+/// priority queue (where 0 is the highest priority).  This queue must be able
+/// to handle PK_THREADS + 1 priorities (the last for the idle thread). The
+/// port must also define methods for clearing, insertion, deletion and min
+/// (with assumed legal priorities).  The min operation returns PK_THREADS if
+/// the queue is empty. (Or a queue could be initialized with the PK_THREADS
+/// entry always present - PK code never tries to delete the idle thread from
+/// a thread queue).
+///
+/// These queues are used both for the run queue and the pending queue
+/// associated with every semaphore.
+///
+/// On PPE42 with 32 threads (implied), this is a job for a uint32_t and
+/// cntlzw().
+
+typedef uint32_t PkThreadQueue;
+
+#endif  /* __PK_PORT_TYPES_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/pkppe42files.mk b/src/import/chips/p9/procedures/ppe/pk/ppe42/pkppe42files.mk
new file mode 100644
index 00000000..accca3f4
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/pkppe42files.mk
@@ -0,0 +1,72 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/ppe/pk/ppe42/pkppe42files.mk $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file  pkppe42files.mk
+#
+#  @brief mk for including ppe42 object files
+#
+#  @page ChangeLogs Change Logs
+#  @section pkppe42files.mk
+#  @verbatim
+#
+#
+# Change Log ******************************************************************
+# Flag     Defect/Feature  User        Date         Description
+# ------   --------------  ----------  ------------ -----------
+#
+# @endverbatim
+#
+##########################################################################
+# Include Files
+##########################################################################
+
+			
+
+##########################################################################
+# Object Files
+##########################################################################
+PPE42-C-SOURCES = ppe42_core.c \
+		  ppe42_init.c \
+		  ppe42_irq_core.c\
+		  ppe42_gcc.c\
+		  ppe42_scom.c\
+		  eabi.c\
+		  math.c\
+		  ppe42_string.c
+
+PPE42-S-SOURCES =  ppe42_boot.S \
+		   ppe42_exceptions.S\
+		   div64.S\
+		   ppe42_timebase.S
+
+PPE42-TIMER-C-SOURCES =
+PPE42-TIMER-S-SOURCES =
+
+PPE42-THREAD-C-SOURCES =
+PPE42-THREAD-S-SOURCES = ppe42_thread_init.S
+
+PPE42_THREAD_OBJECTS= $(PPE42-THREAD-S-SOURCES:.S=.o)
+PPE42_OBJECTS = $(PPE42-C-SOURCES:.c=.o)
+PPE42_OBJECTS += $(PPE42-S-SOURCES:.S=.o)
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h
new file mode 100644
index 00000000..6857ce10
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h
@@ -0,0 +1,813 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42.h $             */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PPE42_H__
+#define __PPE42_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved --  Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ppe42.h
+/// \brief PPE42 port header for PK
+
+// Macros to define where declared code is actually compiled
+
+#ifdef __PPE42_CORE_C__
+    #define IF__PPE42_CORE_C__(x) x
+    #define UNLESS__PPE42_CORE_C__(x)
+#else
+    #define IF__PPE42_CORE_C__(x)
+    #define UNLESS__PPE42_CORE_C__(x) x
+#endif
+
+#ifdef __PPE42_IRQ_CORE_C__
+    #define IF__PPE42_IRQ_CORE_C__(x) x
+    #define UNLESS__PPE42_IRQ_CORE_C__(x)
+#else
+    #define IF__PPE42_IRQ_CORE_C__(x)
+    #define UNLESS__PPE42_IRQ_CORE_C__(x) x
+#endif
+
+#ifdef HWMACRO_GPE
+    #include "gpe.h"
+#elif defined(HWMACRO_STD)
+    #include "std.h"
+#elif defined(HWMACRO_PPE)
+    #include "ppe.h"
+#else
+    #error "Macro Type not specified.  Are you building from the correct directory?"
+#endif
+
+
+#include "ppe42_asm.h"
+#include "ppe42_gcc.h"
+#include "ppe42_spr.h"
+#include "ppe42_msr.h"
+
+
+///start
+
+/// The synchronization macros defined here all create a compiler
+/// memory barrier that will cause GCC to flush/invalidate all memory data
+/// held in registers before the macro. This is consistent with other systems,
+/// e.g., the PowerPC Linux kernel, and is the safest way to define these
+/// macros.
+
+
+// Condition register fields
+
+#define CR_LT(n) (0x80000000u >> (4 * (n)))
+#define CR_GT(n) (0x40000000u >> (4 * (n)))
+#define CR_EQ(n) (0x20000000u >> (4 * (n)))
+#define CR_SO(n) (0x10000000u >> (4 * (n)))
+
+
+#ifndef __ASSEMBLER__
+
+#include "stdint.h"
+
+/// ssize_t is defined explictly rather than bringing in all of <unistd.h>
+#ifndef __ssize_t_defined
+    #define __ssize_t_defined
+    typedef int ssize_t;
+#endif
+
+/// A memory barrier
+#define barrier() asm volatile ("" : : : "memory")
+
+/// Ensure In-order Execution of Input/Output
+#define eieio() asm volatile ("sync" : : : "memory")
+
+/// Memory barrier
+#define sync() asm volatile ("sync" : : : "memory")
+
+/// Instruction barrier
+#define isync() asm volatile ("sync" : : : "memory")
+
+/// CouNT Leading Zeros Word
+#define cntlzw(x) \
+    ({uint32_t __x = (x); \
+        uint32_t __lzw; \
+        asm volatile ("cntlzw %0, %1" : "=r" (__lzw) : "r" (__x)); \
+        __lzw;})
+
+/// CouNT Leading Zeros : uint32_t
+static inline int
+cntlz32(uint32_t x)
+{
+    return cntlzw(x);
+}
+
+/// CouNT Leading Zeros : uint64_t
+static inline int
+cntlz64(uint64_t x)
+{
+    if (x > 0xffffffff)
+    {
+        return cntlz32(x >> 32);
+    }
+    else
+    {
+        return 32 + cntlz32(x);
+    }
+}
+
+
+/// 32-bit population count
+static inline int
+popcount32(uint32_t x)
+{
+    return __builtin_popcount(x);
+}
+
+
+/// 64-bit population count
+static inline int
+popcount64(uint64_t x)
+{
+    return __builtin_popcountll(x);
+}
+
+
+// NB: Normally we wouldn't like to force coercion inside a macro because it
+// can mask programming errors, but for the MMIO macros the addresses are
+// typically manifest constants or 32-bit unsigned integer expressions so we
+// embed the coercion to avoid warnings.
+
+/// 8-bit MMIO Write
+#define out8(addr, data) \
+    do {*(volatile uint8_t *)(addr) = (data);} while(0)
+
+/// 8-bit MMIO Read
+#define in8(addr) \
+    ({uint8_t __data = *(volatile uint8_t *)(addr); __data;})
+
+/// 16-bit MMIO Write
+#define out16(addr, data) \
+    do {*(volatile uint16_t *)(addr) = (data);} while(0)
+
+/// 16-bit MMIO Read
+#define in16(addr) \
+    ({uint16_t __data = *(volatile uint16_t *)(addr); __data;})
+
+/// 32-bit MMIO Write
+#define out32(addr, data) \
+    do {*(volatile uint32_t *)(addr) = (data);} while(0)
+
+/// 32-bit MMIO Read
+#define in32(addr) \
+    ({uint32_t __data = *(volatile uint32_t *)(addr); __data;})
+
+#ifdef HWMACRO_GPE
+
+/// 64-bit MMIO Write
+#define out64(addr, data) \
+    do { \
+        uint64_t __data = (data);                               \
+        volatile uint32_t *__addr_hi = (uint32_t *)(addr);      \
+        volatile uint32_t *__addr_lo = __addr_hi + 1;           \
+        *__addr_hi = (__data >> 32);                            \
+        *__addr_lo = (__data & 0xffffffff);                     \
+    } while(0)
+
+#else /* standard PPE's require a 64 bit write */
+
+/// 64-bit MMIO Write
+#define out64(addr, data) \
+    {\
+        uint64_t __d = (data); \
+        uint32_t* __a = (uint32_t*)(addr); \
+        asm volatile \
+        (\
+         "stvd %1, %0 \n" \
+         : "=o"(*__a) \
+         : "r"(__d) \
+        ); \
+    }
+
+#endif /* HWMACRO_GPE */
+
+#ifdef HWMACRO_GPE
+/// 64-bit MMIO Read
+#define in64(addr) \
+    ({                                                     \
+        uint64_t __data;                                   \
+        volatile uint32_t *__addr_hi = (uint32_t *)(addr); \
+        volatile uint32_t *__addr_lo = __addr_hi + 1;      \
+        __data = *__addr_hi;                               \
+        __data = (__data << 32) | *__addr_lo;              \
+        __data;})
+
+#else /* Standard PPE's require a 64 bit read */
+
+#define in64(addr) \
+    ({\
+        uint64_t __d; \
+        uint32_t* __a = (uint32_t*)(addr); \
+        asm volatile \
+        (\
+         "lvd %0, %1 \n" \
+         :"=r"(__d) \
+         :"o"(*__a) \
+        ); \
+        __d; \
+    })
+
+#endif  /* HWMACRO_GPE */
+
+#endif  /* __ASSEMBLER__ */
+
+#include "ppe42_irq.h"
+
+#ifndef __ASSEMBLER__
+
+/// Store revision information as a (global) string constant
+#define REVISION_STRING(symbol, rev) const char* symbol = rev;
+
+#else // __ASSEMBLER__
+// *INDENT-OFF*
+
+/// Store revision information as a global string constant
+        .macro  .revision_string, symbol:req, rev:req
+        .pushsection .rodata
+        .balign 4
+        .global \symbol
+\symbol\():
+        .asciz  "\rev"
+        .balign 4
+        .popsection
+        .endm
+
+// *INDENT-ON*
+#endif  // __ASSEMBLER__
+
+
+
+#include "ppe42_context.h"
+#include "pk_panic_codes.h"
+
+// PPE42 stack characteristics for PK.  The pre-pattern pattern is selected
+// to be easily recognizable yet be an illegal instruction.
+
+#define PK_STACK_DIRECTION     -1
+#define PK_STACK_PRE_DECREMENT 1
+#define PK_STACK_ALIGNMENT     8
+#define PK_STACK_TYPE          unsigned int
+#define PK_STACK_PATTERN       0x03abcdef
+
+// Kernel data structure offsets for assembler code
+
+#define PK_THREAD_OFFSET_SAVED_STACK_POINTER 0
+#define PK_THREAD_OFFSET_STACK_LIMIT         4
+#define PK_THREAD_OFFSET_STACK_BASE          8
+
+
+// Application-overrideable definitions
+
+/// The default thread machine context has MSR[CE], MSR[EE] and MSR[ME] set,
+/// and all other MSR bits cleared.
+///
+/// The default definition allows external and machine check exceptions.  This
+/// definition can be overriden by the application.
+
+#ifndef PK_THREAD_MACHINE_CONTEXT_DEFAULT
+#define PK_THREAD_MACHINE_CONTEXT_DEFAULT \
+    (MSR_UIE | MSR_EE | MSR_ME)
+
+#endif
+
+
+#ifndef __ASSEMBLER__
+
+/// The PK kernel default panic sequence for C code is to issue a trap
+/// instruction with DBCR[TRAP] set, which causes XSR[TRAP] <- 1
+/// and causes the PPE to halt.
+///
+///
+/// The Simics environment does not model Debug events correctly. It executes
+/// the TRAP as an illegal instruction and branches to the Program Interrupt
+/// handler, destroying the contents of SRR0 and SRR1. Therefore we always
+/// insert a special Simics magic breakpoint (which is an effective NOP)
+/// before the hardware trap.  The special-form magic instruction is
+/// recognized by our Simics support scripts which decode the kernel state and
+/// try to help the user interpret what happened based on the TRAP code.
+///   NOTE! SIMICS does not seem to recognize the "magic breakpoint" on PPE!
+
+
+#ifndef PK_PANIC
+
+#if SIMICS_ENVIRONMENT
+#define PK_PANIC(code)                  \
+    do {                                \
+        asm volatile ("stw     %r3, __pk_panic_save_r3@sda21(0)");      \
+        asm volatile ("lwz     %r3, __pk_panic_dbcr@sda21(0)");         \
+        asm volatile ("mtdbcr  %r3");                                   \
+        asm volatile (".long %0" : : "i" (code));                       \
+    } while(0)
+#else
+#define PK_PANIC(code)                                                  \
+    do {                                                                \
+        asm volatile ("tw 31, %0, %1" : : "i" (code/256) , "i" (code%256)); \
+    } while (0)
+#endif
+#endif // SIMICS_ENVIRONMENT
+
+// These variables are used by the PK_PANIC() definition above to save and
+// restore state. __pk_panic_dbcr is the value loaded into DBCR to force
+// traps to halt the PPE and freeze the timers.
+
+#if SIMICS_ENVIRONMENT
+#ifdef __PPE42_CORE_C__
+uint32_t __pk_panic_save_r3;
+uint32_t __pk_panic_dbcr = DBCR_RST_HALT;
+#define __PK_PANIC_DEFS__
+#else
+#define __PK_PANIC_DEFS__                                               \
+        extern uint32_t __pk_panic_save_r3;                             \
+        extern uint32_t __pk_panic_dbcr;
+#endif //SIMICS_ENVIRONMENT
+
+#endif // PK_PANIC
+
+/// This is the Simics 'magic breakpoint' instruction.
+///
+/// Note that this form does not include a memory barrier, as doing so might
+/// change the semantics of the program.  There is an alternative form
+/// SIMICS_MAGIC_BREAKPOINT_BARRIER that does include a barrier.
+
+//#define SIMICS_MAGIC_BREAKPOINT asm volatile ("rlwimi 0,0,0,0,0")
+
+/// This is the Simics 'magic breakpoint' instruction including a memory
+/// barrier.
+///
+/// Note that the memory barrier guarantees that all variables held in
+/// registers are flushed to memory before the breakpoint, however this might
+/// change the semantics of the program.  There is an alternative form of
+/// SIMICS_MAGIC_BREAKPOINT that does not include a barrier.  If the idea is
+/// to use the breakpoint for tracing code execution in Simics, the barrier
+/// form may be preferred so that variable values will be visible in memory.
+
+/*#define SIMICS_MAGIC_BREAKPOINT_BARRIER \
+             asm volatile ("rlwimi 0,0,0,0,0" : : : "memory")
+*/
+
+#else // __ASSEMBLER__
+// *INDENT-OFF*
+
+/// This is the Simics 'magic breakpoint' instruction.  An assembler macro
+/// form is also provided for use within macros.
+
+//#define SIMICS_MAGIC_BREAKPOINT rlwimi 0,0,0,0,0
+
+//        .macro _simics_magic_breakpoint
+//        rlwimi  0,0,0,0,0
+//        .endm
+
+/// The PK kernel panic default panic sequence for assembler code
+///
+/// By default a kernel panic from assembler forces external debug mode then
+/// generates a \c trap instruction followed by the error code.  The \a code
+/// argument must be a compile-time integer immediate. This definition can be
+/// overriden by the application.
+///
+/// See the comments for the non-ASSEMBLER version for further details.  Note
+/// that the code space reserved for exception handlers is only 8
+/// instructions, so in the assembler context we don't save DBCR0 as doing so
+/// would require 10.
+
+#ifndef PK_PANIC
+
+#define PK_PANIC(code) _pk_panic code
+#if SIMICS_ENVIRONMENT
+        .macro _pk_panic, code
+            stw     %r3, __pk_panic_save_r3@sda21(0)
+            lwz     %r3, __pk_panic_dbcr@sda21(0)
+            mtdbcr  %r3,
+            .long   (\code)
+        .endm
+#else
+        .macro  _pk_panic, code
+            tw  31,(\code)/256, (\code)%256
+        .endm
+#endif // SIMICS_ENVIRONMENT
+#endif // PK_PANIC
+
+// *INDENT-ON*
+#endif // __ASSEMBLER__
+
+
+//  Application-overridible definitions for the PK boot loader
+
+/// In order to enable the default kernel panic (a trap) to halt the machine,
+/// the Debug Control Register 0 (DBCR0) is initialized in externel debug
+/// mode, with the Trap Debug Event enabled so that the trap will not cause a
+/// program exception, and the FT bit set so that the timers will freeze.
+/// This definition can be overridden by the application.
+///
+/// NB: It is expected that a reliable production system will redefine all of
+/// the 'panic' macros and the default DBCR0 setup.
+
+#ifndef PPE42_DBCR_INITIAL
+#define PPE42_DBCR_INITIAL DBCR_TRAP
+#endif
+
+/// This is the value of the MSR used during initialization.  Once PK threads
+/// are started (with \c pk_start_threads()), all machine contexts derive
+/// from the default thread context \c
+/// PK_THREAD_MACHINE_CONTEXT_DEFAULT. This definition can be overriden by
+/// the application.
+///
+/// The default is to enable machine checks only.
+
+#ifndef PPE42_MSR_INITIAL
+#define PPE42_MSR_INITIAL MSR_ME
+#endif
+
+/// The \a argc argument passed to \c main(). This definition can be overriden
+/// by the application.
+
+#ifndef PPE42_ARGC_INITIAL
+#define PPE42_ARGC_INITIAL 0
+#endif
+
+/// The \a argv argument passed to \c main(). This definition can be overriden
+/// by the application.
+
+#ifndef PPE42_ARGV_INITIAL
+#define PPE42_ARGV_INITIAL 0
+#endif
+
+/// Optionally trap the reset for the debugger, which means that the PPE42
+/// will simply spin at the symbol \c __reset_trap after a chip reset. Set R0
+/// to a non-zero value in the debugger to continue execution. This definition
+/// can be overriden by the application.
+
+#ifndef PPE42_RESET_TRAP
+#define PPE42_RESET_TRAP 0
+#endif
+
+#ifndef __ASSEMBLER__
+
+/// The PPE42 PK machine context is simply the MSR, a 32-bit integer.
+
+typedef uint32_t PkMachineContext;
+
+/// Disable interrupts and return the current
+/// context.
+///
+/// \param context A pointer to an PkMachineContext, this is the context that
+///                existed before interrupts were disabled. Typically this
+///                context is restored at the end of a critical section.
+///
+/// Return values other then PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_INVALID_ARGUMENT_INTERRUPT An illegal priority was specified.
+
+UNLESS__PPE42_CORE_C__(extern)
+inline int
+pk_interrupt_disable(PkMachineContext* context)
+{
+*context = mfmsr();
+
+wrteei(0);
+
+return PK_OK;
+}
+
+/// Set the machine context.
+///
+/// \param context A pointer to an PkMachineContext
+///
+/// Return values other then PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_INVALID_ARGUMENT_CONTEXT_SET A null pointer was provided as
+/// the \a context argument or an illegal machine context was specified.
+
+UNLESS__PPE42_CORE_C__(extern)
+inline int
+pk_machine_context_set(PkMachineContext* context)
+{
+if (PK_ERROR_CHECK_API)
+{
+PK_ERROR_IF(context == 0, PK_INVALID_ARGUMENT_CONTEXT_SET);
+}
+
+mtmsr(*context);
+
+return PK_OK;
+}
+
+/// Get the machine context.
+///
+/// \param context A pointer to an PkMachineContext.
+///
+/// Return values other then PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_INVALID_ARGUMENT_CONTEXT_GET A null pointer was provided as
+/// the \a context argument.
+
+UNLESS__PPE42_CORE_C__(extern)
+inline int
+pk_machine_context_get(PkMachineContext* context)
+{
+if (PK_ERROR_CHECK_API)
+{
+PK_ERROR_IF(context == 0, PK_INVALID_ARGUMENT_CONTEXT_GET);
+}
+
+*context = mfmsr();
+
+return PK_OK;
+}
+
+extern void __ctx_switch();
+/// The PK context switch for the PPE kernel
+//  There is no protected mode in PPE42 so just call kernel code
+#define __pk_switch() __ctx_switch()
+
+
+/// In the PowerPC EABI all initial stack frames require 8 bytes - the 4 bytes
+/// at the SP are zeroed to indicate the end of the stack, and the 4 bytes
+/// behind the SP are for the initial subroutine's LR.
+
+static inline void
+__pk_stack_create_initial_frame(PkAddress* stack, size_t* size)
+{
+*stack -= 8;
+* size -= 8;
+* ((PK_STACK_TYPE*)(*stack)) = 0;
+}
+
+/// The PK Kernel Context for PPE42
+///
+/// The PK portable kernel does not define how the kernel keeps track of
+/// whether PK is running, interrupt levels, and other debug
+/// information. Instead it defines an API that the port must provide to the
+/// portable kernel.
+///
+/// In the PPE42 port, the kernel context is maintained in SPRG0.  This
+/// 32-bit value is treated as 6 distinct fields as indicated in the structure
+/// definition.
+typedef union
+{
+
+uint32_t value;
+
+struct
+{
+
+/// A flag indicating that PK is in thread mode after a call of
+/// pk_start_threads().
+unsigned thread_mode : 1;
+
+/// If this field is non-zero then PK is processing an interrupt
+/// and the \c irq field will contain the PkIrqId of the interrupt
+/// that kicked off interrupt processing.
+unsigned processing_interrupt : 1;
+
+/// The priority of the currently running thread.  In an interrupt
+/// context, this is the priority of the thread that was interrupted.
+unsigned thread_priority : 6;
+
+/// This bit tracks whether the current context can be discarded or
+/// if the context must be saved.  If the processor takes an interrupt
+/// and this bit is set, then the current context will be discarded.
+/// This bit is set at the end of handling an interrupt and prior
+/// to entering the wait enabled state.
+unsigned discard_ctx : 1;
+
+/// The PkIrqId of the currently running (or last run) handler.  If
+/// \c processing_interrupt is set, then this is the
+/// PkIrqId of the IRQ that is currently executing.
+unsigned irq : 7;
+
+/// Each PPE application will define (or not) the interpretation of
+/// this field.  Since SPRG0 is saved and restored during during thread
+/// context switches, this field can be used to record the progress of
+/// individual threads.  The kernel and/or application will provide
+/// APIs or macros to read and write this field.
+unsigned app_specific : 16;
+
+} fields;
+
+} __PkKernelContext;
+
+// These APIs are provided for applications to get and set the app_specific
+// field of the kernel context which is held in sprg0.
+
+static inline uint16_t ppe42_app_ctx_get(void)
+{
+__PkKernelContext __ctx;
+__ctx.value = mfspr(SPRN_SPRG0);
+return __ctx.fields.app_specific;
+}
+
+static inline void ppe42_app_ctx_set(uint16_t app_ctx)
+{
+PkMachineContext    mctx;
+__PkKernelContext   __ctx;
+mctx = mfmsr();
+wrteei(0);
+__ctx.value = mfspr(SPRN_SPRG0);
+__ctx.fields.app_specific = app_ctx;
+mtspr(SPRN_SPRG0, __ctx.value);
+mtmsr(mctx);
+}
+
+// These APIs are provided to the PK portable kernel by the port.
+
+/// PK threads have been started by a call of pk_start_threads().
+
+#define __pk_kernel_mode_thread() \
+    ({ \
+        __PkKernelContext __ctx; \
+        __ctx.value = mfspr(SPRN_SPRG0); \
+        __ctx.fields.thread_mode;})
+
+
+///  PK is executing in a thread context (not an interrupt handler).
+
+#define __pk_kernel_context_thread() \
+    ({ \
+        __PkKernelContext __ctx; \
+        __ctx.value = mfspr(SPRN_SPRG0); \
+        __ctx.fields.thread_mode && !__ctx.fields.processing_interrupt;})
+
+
+///  PK is executing an interrupt handler of any priority.
+
+#define __pk_kernel_context_any_interrupt() \
+    ({ \
+        __PkKernelContext __ctx; \
+        __ctx.value = mfspr(SPRN_SPRG0); \
+        __ctx.fields.processing_interrupt;})
+
+
+// PK requires the port to define the type PkThreadQueue, which is a
+// priority queue (where 0 is the highest priority).  This queue must be able
+// to handle PK_THREADS + 1 priorities (the last for the idle thread) The
+// port must also define methods for clearing, insertion, deletion and min
+// (with assumed legal priorities).  The min operation returns PK_THREADS if
+// the queue is empty (or a queue could be initialized with that entry always
+// present - PK code never tries to delete the idle thread from a thread
+// queue).
+//
+// These queues are used both for the run queue and the pending queue
+// associated with every semaphore.
+//
+// On PPE42 with 32 threads (implied), this is a job for a uint32_t and
+// cntlzw().
+
+static inline void
+__pk_thread_queue_clear(volatile PkThreadQueue* queue)
+{
+*queue = 0;
+}
+
+static inline void
+__pk_thread_queue_insert(volatile PkThreadQueue* queue, PkThreadPriority priority)
+{
+*queue |= (0x80000000u >> priority);
+}
+
+static inline void
+__pk_thread_queue_delete(volatile PkThreadQueue* queue, PkThreadPriority priority)
+{
+*queue &= ~(0x80000000u >> priority);
+}
+
+static inline PkThreadPriority
+__pk_thread_queue_min(volatile PkThreadQueue* queue)
+{
+return cntlzw(*queue);
+}
+
+static inline int
+__pk_thread_queue_member(volatile PkThreadQueue* queue, PkThreadPriority priority)
+{
+return ((*queue >> (31 - priority)) & 1);
+}
+
+static inline void
+__pk_thread_queue_union(volatile PkThreadQueue* queue0,
+volatile PkThreadQueue* queue1)
+{
+*queue0 |= *queue1;
+}
+
+static inline int
+__pk_thread_queue_count(volatile PkThreadQueue* queue)
+{
+return __builtin_popcount(*queue);
+}
+
+
+/// This macro is used to call __pk_start_threads() using the kernel stack,
+/// in a critical section.
+
+#define __pk_call_pk_start_threads()                          \
+    do {                                                        \
+        PkMachineContext ctx;                                  \
+        pk_critical_section_enter(&ctx);      \
+        asm volatile ("mr 1, %0; mtlr %1; blrl" : :             \
+                      "r" (__pk_kernel_stack),            \
+                      "r" (__pk_start_threads));               \
+        PK_PANIC(PK_START_THREADS_RETURNED);                  \
+    } while (0)
+
+
+#endif  /* __ASSEMBLER__ */
+
+/// The __PkKernelContext 'thread_mode' bit as a flag
+
+#define PPE42_THREAD_MODE   0x8000
+#define PPE42_PROC_IRQ      0x4000
+#define PPE42_DISCARD_CTX   0x0080
+
+#define PPE42_THREAD_MODE_BIT   0
+#define PPE42_PROC_IRQ_BIT      1
+#define PPE42_DISCARD_CTX_BIT   8
+
+#ifndef __ASSEMBLER__
+
+/// Code breakpoints for PPE42
+///
+/// This macro inserts a special PPE42-only breakpoint into the object code
+/// at the place the macro invocation appears.  This facility is designed for
+/// VBU/VPO procedure debugging. This type of breakpoint may not be required
+/// on real hardware as we will then have the full power of RISCWatch, gdb,
+/// etc. Once inserted into the code, code breakpoints can be enabled or
+/// disabled by manipulating the global variable _code_breakpoint_enable,
+/// which defaults to 1.
+///
+/// The code breakpoint is implemented as a setup routine and a teardown
+/// routine, executed in an critical section.  The actual break
+/// will occur at the address of the call of the teardown routine, in the
+/// context of the calling code.  The setup routine saves the state of DBCR0/1
+/// and IAC4, then programs the DBCR for an external debug mode, IAC4
+/// breakpoint.  The IAC4 breakpoint is set for the address of the call of the
+/// teardown routine.  The teardown routine simply restores the state of the
+/// debug registers that existed before the code breakpoint.
+///
+/// Once hit, restarting from the break requires clearing IAC4 and restarting
+/// instructions:
+///
+/// \code
+///
+/// putspr pu.occ iac4 0
+/// cipinstruct pu.occ start
+///
+/// \endcode
+///
+/// The above restart processes is also encapsulated as the p8_tclEcmd
+/// procedure 'unbreakOcc'.
+///
+/// In code built for the Simics environment (i.e., with the preprocessor
+/// macro SIMICS_ENVIRONMENT=1) this macro simply expands into
+/// SIMICS_MAGIC_BREAKPOINT, and simulation can be continued from the break as
+/// normal. This Simics magic breakpoint is also under the control of
+/// _code_breakpoint_enable.  In code not built with SIMICS_ENVIROMENT=1, note
+/// that the CODE_BREAKPOINT is ignored by the Simics PPE42 model as it does
+/// not model debug events.
+
+//void
+//_code_breakpoint_prologue(void);
+
+//void
+//_code_breakpoint_epilogue(void);
+
+//extern uint32_t _code_breakpoint_enable;
+
+#endif // __ASSEMBLER__
+
+
+#endif /* __PPE42_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_asm.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_asm.h
new file mode 100644
index 00000000..6f3923aa
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_asm.h
@@ -0,0 +1,634 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_asm.h $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PPE42_ASM_H__
+#define __PPE42_ASM_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ppe42_asm.h
+/// \brief Generic assembler macros for 32-bit PPE42
+
+// Doxygen is confused by assembler; the best I know how to make it
+// work is to put all of the documentation at the beginning like below
+// and effectively comment out the code using Doxygen cond/endcond.
+
+/// \page ppe42_asm Generic assembler macros for 32-bit PPE42
+///
+///
+/// \section _lxzi _l<w,h,b>zi - Load register and Zero from Immediate address
+///
+/// These macros encapsulate the 2-instruction sequence required to
+/// load from a 32-bit immediate address.
+///
+/// \arg \c dreg A register to receive the load data.
+/// \arg \c areg A register to hold the immediate address.  This can \e
+///              not be register 0. Note that if \a areg != \a dreg
+///              then \a areg will contain the address at the end of
+///              the macro sequence.
+/// \arg \c addr A 32-bit immediate address, which may be either an
+///         absolute or relocatable expression.
+///
+/// Forms:
+///
+/// \b _lbzi \a dreg, \a areg, \a addr - Load Byte and Zero from Immediate address \n
+/// \b _lhzi \a dreg, \a areg, \a addr - Load Halfword and Zero from Immediate address \n
+/// \b _lwzi \a dreg, \a areg, \a addr - Load Word and Zero from Immediate address \n
+///
+///
+/// \section _stxi _st<w,h,b>i - STore register to Immediate address
+///
+/// These macros encapsulate the 2-instruction sequence required to
+/// store to a 32-bit immediate address.
+///
+/// \arg \c dreg The register to store.
+/// \arg \c areg A register to hold the immediate address.  This can \e
+///              not be register 0, and can not be the same as \a dreg.
+///              Note that \a areg will contain the address at the end of
+///              the macro sequence.
+/// \arg \c addr A 32-bit immediate address, which may be either an
+///         absolute or relocatable expression.
+///
+/// Forms:
+///
+/// \b _stbi \a dreg, \a areg, \a addr - STore Byte to Immediate address \n
+/// \b _sthi \a dreg, \a areg, \a addr - STore Halfword to Immediate address \n
+/// \b _stwi \a dreg, \a areg, \a addr - STore Word to Immediate address \n
+///
+///
+/// \section _lstzsd _<l,st><w,h,b><z>sd - Load/STore register from/to Small Data area
+///
+/// These macros encapulate the small data area relocations for access
+/// to storage in the small data sections .sbss, .sdata, .sbss2 and
+/// .sdata2.  Use of these macros implies small data area support in
+/// the compile environment (for variables shared between compiled and
+/// assembled code) and initialization code that sets up the small data
+/// area registers R13 (and optionally R2).
+///
+/// The relocations generated by this macro will work for both SVR4 ABI
+/// and EABI environments.  In particular, for EABI environments
+/// the link editor will insert offsets to either R13 or R2 depending
+/// on the section of the symbol.
+///
+/// \arg \c dreg The register to load or store.
+/// \arg \c addr A 32-bit immediate address, assumed to be a
+///              relocatable address in one of the small data sections.
+///
+/// Forms:
+///
+/// \b _lbzsd \a dreg, \a addr  - Load Byte and Zero from Small Data area \n
+/// \b _lhzsd \a dreg, \a addr  - Load Halfword and Zero from Small Data area \n
+/// \b _lwzsd \a dreg, \a addr  - Load Word and Zero from Small Data area \n
+/// \b _stbsd \a dreg, \a addr  - STore Byte to Small Data area \n
+/// \b _sthsd \a dreg, \a addr  - STore Halfword to Small Data area \n
+/// \b _stwsd \a dreg, \a addr  - STore Word to Small Data area \n
+///
+///
+/// \section _liw _liw<a> - Load Immediate Word (Absolute)
+///
+/// These macros encapsulate the two instructions required to load a
+/// 32-bit immediate value into a register.  If the immediate is an
+/// absolute expression, then the \c 'a' form may be able to optimize
+/// to a single instruction depending on whether only the high- or
+/// low-order bits of the immediate are non-zero.
+///
+/// Forms:
+///
+/// \b _liw  \a rd, \a imm - Load register \a rd with the 32-bit immediate \a imm \n
+/// \b _liwa \a rd, \a imm - Load register \a rd with the 32-bit absolute immediate \a imm \n
+///
+///
+/// \section _oriwa _oriwa - OR Immediate Word Absolute
+///
+/// This macro encapsulates the logical OR of a 32-bit immediate with a
+/// register. The immediate value must be an absolute expression.
+///
+/// The PowerPC has instructions for OR-ing 16-bit immediates into the
+/// upper (\c oris) and lower (\c ori) portions of a register.  This
+/// macro optimizes the generated code based on which bits (if any) of
+/// the absolte immediate are non-zero.
+///
+/// This special macro is only provided for the OR function. For other
+/// logical operations and recording forms it is necessary in general
+/// to first load the 32-bit immediate into a register (e.g., with \c
+/// _liwa) then perform the logical operation.
+///
+/// \arg \c rd The destination register; at the end will contain \c rs
+///            OR \a imm
+/// \arg \c rs The source register.
+/// \arg \c imm 32-bit absolute expression.
+///
+/// Forms:
+///
+/// \b _oriwa \a rd, \a rs, \a imm - \a rd gets \a rs OR \a imm \n
+///
+///
+/// \section _incr64_fast - 64-bit increment for fast interrupt handlers
+///
+/// This macros implements 64-bit counter update in fast interrupt handlers
+/// which are forbidden from using the carry-bit in the XER (without
+/// saving/restoring it.)
+///
+/// \arg \c rs Scratch register
+/// \arg \c ra Register containing the counter address at entry
+///
+/// \a rs and \a ra must be unique.  At the end of the macro the count
+/// is updated to memory and \a ra is unmodified.
+///
+///
+/// \section _setclear_bits Set/Clear/Copy Bits from Immediate Positions
+///
+///  There are situations where it is easier/faster to clear individual bits
+///  and bit fields, set bits or copy fields, based on immediate bit numbers
+///  and locations, rather than loading masks, since setting up a mask
+///  requires 2 instruction in general, whereas these macros generate a single
+///  instruction.
+///
+/// \arg \c rd - The destination register
+/// \arg \c rs - The source register
+/// \arg \c n - An immediate size of a bit field, in the range 0 to 32
+/// \arg \c b - An immediate big-endian bit number in the range 0 to 31
+///
+/// Forms:
+///
+/// \b _clrfield \a rd, \a rs, \a n, \a b - Clear an \a n bit field from \a rs
+/// to \a rd starting from bit \a b \n
+/// \b _clrbit \a rd, \a rs, \a b - Clear bit \a b \n
+/// \b _setbit \a rd, \a rs, \a b - Set bit \a b \n
+/// \b _copyfield \a rd, \a rs, \a n, \a b - Copy an n-bit field from \a rs to
+/// \a rd starting from bit \a b \n
+///
+///
+/// \section pseudo_ops Assembler Pseudo-Ops Macros
+///
+/// Several macros define new 'pseudo-ops'.
+///
+/// \subsection cache_align .cache_align
+///
+/// The \c .cache_align pseudo-op is used to force alignment on a
+/// cache-line boundary.  It requires a preprocessor symbol definition for
+/// \c LOG_CACHE_LINE_SIZE
+///
+/// Forms:
+///
+/// \b .cache_align \n
+///
+///
+/// \subsection global_function Local and Global Functions
+///
+/// The \c .function and \c .global_function pseudo-ops define function
+/// symbols in the \c .text section.
+///
+/// Forms:
+///
+/// \b .function \a symbol - Define a local function \a symbol \n
+/// \b .global_function \a symbol - Define a global function \a symbol \n
+///
+///
+/// \subsection epilogue .epilogue
+///
+/// The \c .epilogue pseudo-op adds size and type information for
+/// functions defined in assembler.
+///
+/// \arg \c symbol - Assembler epilogue for the function \a symbol.
+///
+/// Forms:
+///
+/// \b .epilogue \a symbol \n
+///
+///
+/// \cond
+
+#ifdef __ASSEMBLER__
+// *INDENT-OFF*
+
+
+### ****************************************************************************
+### _l<b,h,w>zi
+### _st<b,h,w>i
+### ****************************************************************************
+
+        .macro  _lbzi dreg, areg, addr
+        lis     \areg, \addr@ha
+        .ifc    \areg, \dreg
+        lbz     \dreg, \addr@l(\areg)
+        .else
+        lbzu    \dreg, \addr@l(\areg)
+        .endif
+        .endm
+
+        .macro  _lhzi dreg, areg, addr
+        lis     \areg, \addr@ha
+        .ifc    \areg, \dreg
+        lhz     \dreg, \addr@l(\areg)
+        .else
+        lhzu    \dreg, \addr@l(\areg)
+        .endif
+        .endm
+
+        .macro  _lwzi dreg, areg, addr
+        lis     \areg, \addr@ha
+        .ifc    \areg, \dreg
+        lwz     \dreg, \addr@l(\areg)
+        .else
+        lwzu    \dreg, \addr@l(\areg)
+        .endif
+        .endm
+
+        .macro  _stbi dreg, areg, addr
+        .ifc    \areg, \dreg
+        .err
+        .endif
+        lis     \areg, \addr@ha
+        stbu    \dreg, \addr@l(\areg)
+        .endm
+
+        .macro  _sthi dreg, areg, addr
+        .ifc    \areg, \dreg
+        .err
+        .endif
+        lis     \areg, \addr@ha
+        sthu    \dreg, \addr@l(\areg)
+        .endm
+
+        .macro  _stwi dreg, areg, addr
+        .ifc    \areg, \dreg
+        .err
+        .endif
+        lis     \areg, \addr@ha
+        stwu    \dreg, \addr@l(\areg)
+        .endm
+
+
+### ****************************************************************************
+### _l<b,h,w>zsd
+### _st<b,h,w>sd
+### ****************************************************************************
+
+        .macro  _lbzsd  dreg, addr
+        lbz     \dreg, \addr@sda21(0)
+        .endm
+
+        .macro  _lhzsd  dreg, addr
+        lhz     \dreg, \addr@sda21(0)
+        .endm
+
+        .macro  _lwzsd  dreg, addr
+        lwz     \dreg, \addr@sda21(0)
+        .endm
+
+        .macro  _stbsd  dreg, addr
+        stb     \dreg, \addr@sda21(0)
+        .endm
+
+        .macro  _sthsd  dreg, addr
+        sth     \dreg, \addr@sda21(0)
+        .endm
+
+        .macro  _stwsd  dreg, addr
+        stw     \dreg, \addr@sda21(0)
+        .endm
+
+
+### ****************************************************************************
+### _liw<a>
+### _oriwa
+### ****************************************************************************
+
+        .macro  _liw    rd, imm
+        lis     \rd, \imm@h
+        ori     \rd, \rd, \imm@l
+        .endm
+
+        .macro  _liwa   rd, imm
+        .if     (\imm & 0xffff0000)
+        lis     \rd, \imm@h
+                .if     (\imm & 0xffff)
+                ori     \rd, \rd, \imm@l
+                .endif
+        .else
+        li      \rd, \imm@l
+        .endif
+        .endm
+
+        .macro  _oriwa  rd, rs, imm
+        .if     (\imm & 0xffff0000)
+        oris    \rd, \rs, \imm@h
+                .if     (\imm & 0xffff)
+                ori     \rd, \rd, \imm@l
+                .endif
+        .else
+        ori     \rd, \rs, \imm@l
+        .endif
+        .endm
+
+### ****************************************************************************
+### _incr64_fast
+### ****************************************************************************
+
+        .macro  _incr64_fast, rs:req, ra:req
+
+        lwz     \rs, 4(\ra)
+        addi    \rs, \rs, 1
+        cmpwi   \rs, 0
+        stw     \rs, 4(\ra)
+        bne     233643278f
+
+        lwz     \rs, 0(\ra)
+        addi    \rs, \rs, 1
+        stw     \rs, 0(\ra)
+233643278:              
+
+        .endm        
+
+### ****************************************************************************
+### _clrfield
+### _clrbit
+### _setbit
+### _copyfield
+### ****************************************************************************
+
+        .macro  _clrfield, rd, rs, n, b
+        rlwinm   \rd, \rs, 0, (\b + \n) & 0x1f, (\b - 1) & 0x1f
+        .endm           
+
+        .macro  _clrbit, rd, rs, b
+        _clrfield \rd, \rs, 1, \b
+        .endm
+
+        .macro  _setbit, rd, rs, b
+        .ifle   \b - 15
+        oris    \rd, \rs, 1 << (15 - \b)
+        .else
+        ori     \rd, \rs, 1 << (31 - \b)
+        .endif
+        .endm
+
+        .macro  _copyfield, rd, rs, n, b
+        rlwimi  \rd, \rs, 0, \b , (\b + \n - 1)
+        .endm
+
+### ****************************************************************************
+### .cache_align
+### .<global_>function
+### .epilogue
+### ****************************************************************************
+
+        .set    _log_cache_line_size, LOG_CACHE_LINE_SIZE
+
+        .macro  .cache_align
+        .align  _log_cache_line_size
+        .endm
+
+        .macro  .function symbol
+        .text
+        .align  2
+        .endm
+
+        .macro  .global_function symbol
+        .text
+        .align  2
+        .global \symbol
+        .endm
+
+        .macro .epilogue symbol
+        .type   \symbol, @function
+        .size   \symbol, . - \symbol
+        .endm           
+
+### ***************************************************************************
+###                                 64-bit macros
+### ***************************************************************************
+
+### ***************************************************************************
+### Using symbols for register names makes the code more readable and allows
+### us to do register arithmetic within macros.
+### ***************************************************************************
+
+.equiv  r0, 0
+.equiv  r1, 1
+.equiv  sp, 1
+.equiv  r3, 3
+.equiv  r4, 4
+.equiv  r5, 5
+.equiv  r6, 6
+.equiv  r7, 7
+.equiv  r8, 8
+.equiv  r9, 9
+.equiv  r10, 10
+
+.equiv  r28, 28
+.equiv  r29, 29
+.equiv  r30, 30
+.equiv  r31, 31
+
+.equiv  d3, 3
+.equiv  d4, 4
+.equiv  d5, 5
+.equiv  d6, 6
+.equiv  d7, 7
+.equiv  d8, 8
+.equiv  d9, 9
+.equiv  d10, 10
+.equiv  d28, 28
+.equiv  d29, 29
+.equiv  d30, 30
+.equiv  d31, 31
+
+### ***************************************************************************
+### Load virtual doubleword generic. Load a virtual doubleword from a relocatable
+### address expression. If the optional RA is specified, the address remains in
+### RA.
+### ***************************************************************************
+.macro _lvdg DT:req addr:req RA=-1
+    .if \RA == -1
+        lis     \DT, (\addr)@ha
+        lvd     \DT, (\addr)@l(\DT)
+    .else
+        lis     \RA, (\addr)@ha
+        lvdu    \DT, (\addr)@l(\RA)
+    .endif
+.endm
+
+### ***************************************************************************
+### Load virtual doubleword from a relocatable small data area address
+### ***************************************************************************
+.macro _lvdsd DT:req addr:req
+    lvd     \DT, (\addr)@sda21(0)
+.endm
+
+### ***************************************************************************
+### Store virtual doubleword generic. Store a virtual doubleword based on a
+### relocatable address expression. The address remains in RA.
+### ***************************************************************************
+.macro _stvdg DS:req addr:req RA:req
+    lis     \RA, (\addr)@ha
+    stvdu   \DS, (\addr)@l(\RA)
+.endm
+
+### ***************************************************************************
+### Store virtual doubleword to a relocatable small data address expression
+### ***************************************************************************
+.macro _stvdsd DS:req addr:req
+    stvd    \DS, (\addr)@sda21(0)
+.endm
+
+### ***************************************************************************
+###  Load virtual doubleword absolute. Set DT to an absolute 64-bit constant
+### ***************************************************************************
+.macro _lvda DT, cvalue
+    lwa (\DT + 1)%32, (\cvalue) & 0x00000000ffffffff
+    lwa \DT, (\cvalue) >> 32
+.endm
+
+### ***************************************************************************
+###
+###                         64-bit arithmetic macros
+###
+### ***************************************************************************
+
+.macro check_overlap2 DA, DB
+    .if ((\DA - \DB) % 32) == 1 || ((\DA - \DB) % 32) == -1
+        .error "virtual doubleword registers must be identical or non-overlapping"
+    .endif
+.endm
+
+.macro check_overlap3 DA, DB, DC
+    check_overlap2 \DA, \DB
+    check_overlap2 \DA, \DC
+    check_overlap2 \DB, \DC
+.endm
+
+### ***************************************************************************
+###  Add virtual doubleword carrying
+### ***************************************************************************
+.macro _addvdc   DT, DA, DB
+    check_overlap3 \DT, \DA, \DB
+    addc    (\DT+1)%32, (\DA+1)%32, (\DB+1)%32
+    adde    \DT, \DA, \DB
+.endm
+
+### ***************************************************************************
+###  Add virtual doubleword to signed 16-bit immediate carrying
+### ***************************************************************************
+.macro _addvdic  DT, DA, SI
+    .if \DA == 31
+        .error "d31 for addend register is not supported"
+    .endif
+    check_overlap2 \DT, \DA
+    addi    (\DT+1)%32, \DA+1, SI
+    addze   \DT, \DA
+.endm
+
+### ***************************************************************************
+###  Add virtual doubleword to unsigned word carrying
+### ***************************************************************************
+.macro _addvdwuc DT, DA, RB
+    check_overlap2 \DT, \DA
+    addc    (\DT+1)%32, (\DA+1)%32, \RB
+    addze   \DT, \DA
+.endm
+
+### ***************************************************************************
+###  Subtract virtual doubleword carrying
+### ***************************************************************************
+.macro _subvdc   DT, DA, DB
+    check_overlap3 \DT, \DA, \DB
+    subfc   (\DT+1)%32, (\DA+1)%32, (\DB+1)%32
+    subfe   \DT, \DA, \DB
+.endm
+
+### ***************************************************************************
+### 
+###                             64-bit logic macros
+### 
+### ***************************************************************************
+
+### ***************************************************************************
+###  AND virtual doubleword
+### ***************************************************************************
+.macro _andvd DT, DA, DB
+    check_overlap3 \DT, \DA, \DB
+    and (\DT+1)%32, (\DA+1)%32, (\DB+1)%32
+    and \DT, \DA, \DB
+.endm
+
+### ***************************************************************************
+###  ANDC virtual doubleword
+### ***************************************************************************
+.macro _andcvd DT, DA, DB
+    check_overlap3 \DT, \DA, \DB
+    andc    (\DT+1)%32, (\DA+1)%32, (\DB+1)%32
+    andc    \DT, \DA, \DB
+.endm
+
+### ***************************************************************************
+###  EQV virtual doubleword
+### ***************************************************************************
+.macro _eqvvd DT, DA, DB
+    check_overlap3 \DT, \DA, \DB
+    eqv (\DT+1)%32, (\DA+1)%32, (\DB+1)%32
+    eqv \DT, \DA, \DB
+.endm
+
+### ***************************************************************************
+###  OR virtual doubleword
+### ***************************************************************************
+.macro _orvd DT, DA, DB
+    check_overlap3 \DT, \DA, \DB
+    or (\DT+1)%32, (\DA+1)%32, (\DB+1)%32
+    or \DT, \DA, \DB
+.endm
+
+### ***************************************************************************
+###  ORC virtual doubleword
+### ***************************************************************************
+.macro _orcvd DT, DA, DB
+    check_overlap3 \DT, \DA, \DB
+    orc (\DT+1)%32, (\DA+1)%32, (\DB+1)%32
+    orc \DT, \DA, \DB
+.endm
+
+### ***************************************************************************
+###  XOR virtual doubleword
+### ***************************************************************************
+.macro _xorvd DT, DA, DB
+    check_overlap3 \DT, \DA, \DB
+    xor (\DT+1)%32, (\DA+1)%32, (\DB+1)%32
+    xor \DT, \DA, \DB
+.endm
+
+// *INDENT-ON*
+#endif /* __ASSEMBLER__ */
+
+/// \endcond
+
+// Local Variables:
+// mode:asm
+// End:
+
+#endif /* __PPE42_ASM_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_boot.S b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_boot.S
new file mode 100644
index 00000000..6c3424f5
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_boot.S
@@ -0,0 +1,193 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_boot.S $        */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+        
+/// \file ppe42_boot.S
+/// \brief PK bootloader for PPE42
+
+        .nolist
+#include "pk.h"
+        .list
+        
+### PK Bootloader for PPE42
+###
+### This is the basic restart initialization of the processor.  
+### Parts of this code were derived from examples in the IBM OSopen
+### OpenBIOS for the 405GP written by James Burke.
+###
+### This code does not really do very much, just makes sure that there will
+### be a reasonable state in the machine when control is turned over to
+### the PK application.  Any core setup that requires SPR access will be done
+### here. All other setup is expected to take place in system-specific
+### routines. 
+###
+### From the PowerPC 405-S Embedded Core User's manual:
+###
+### "In general, the contents of SPRs are undefined after a core, chip or
+### system reset. Some SPRs retain the content they had before the reset
+### occurred."
+###
+### Registers fully reset:
+###     DBCR1 - Data compares disabled
+###     DCWR  - Data cache write-through disabled
+###     ESR   - No exception syndromes
+###     MSR   - No exceptions/interrupts are allowed
+### 
+### Registers partially reset:
+###     CCR0        = 0x00700000 - Sets ICU and DCU PLB Priority
+###     DBCR0 [EDM] = 0          - External debug mode disabled
+###           [RST] = 0          - No reset action
+###     DBSR  [MRR] = x          - x indicates most recent reset action
+###     SGR         = 0xffffffff - Storage is guarded
+###     TCR   [WRC] = 0          - Watchdog timer reset disabled
+###     TSR   [WRS] = x          - x is a copy of TCR[WRC] Watchdog reset status
+###           [PIS] = x          - undefined
+
+        .global_function __pk_boot
+        .global __reset_trap
+        
+__pk_boot:
+        
+        ## Trap the reset for the debugger.  Set R0 to a non-zero value in the
+        ## debugger to continue.
+
+        .if     PPE42_RESET_TRAP
+        li      %r0, 0
+__reset_trap:   
+        cmpwi   %r0, 0          
+        beq     __reset_trap
+        .endif
+        
+        ## Set up PowerPC EABI constant registers.  These registers are never
+        ## again touched by the PK kernel or the application (if they are
+        ## behaving).
+
+        _liw    %r2, _SDA2_BASE_
+        _liw    %r13, _SDA_BASE_
+
+        ## Clear the timer control register.  This masks all timer interrupts.
+
+        li      %r3, 0
+        mttcr   %r3
+
+        ## The stack pointer is initialized for use by the remainder of the 
+        ## initialization, including the application main(). The linker script
+        ## defines the initial stack area.
+        ## 
+        ## Stacks are always 8-byte aligned.  A '0' is stored at the
+        ## stack pointer to indicate the end of the stack chain. Stack frames
+        ## always consist of at least 8 bytes - the backchain pointer and the
+        ## slot above the backchain pointer for the callee's LR.
+        
+        _liw    %r1, _PK_INITIAL_STACK
+        _clrfield %r1, %r1, 3, 29 # 8-byte align
+        li      %r3, 0
+        stwu    %r3, -8(%r1)
+        
+        ## SPRG0 (__PkKernelContext) is initialized to 0
+        ## indicating that the PK kernel is not in thread mode, and no
+        ## interrupts are active.
+
+        li      %r3, 0
+        mtsprg0 %r3
+
+        ## Set up the initial value of Debug Control Register 0.  Note that
+        ## DBCR1 is specified to be cleared at reset.  VBU simulation requested
+        ## an option that this register not be modified so that they could
+        ## completely control debug behavior from reset of the PPE42.
+
+#ifndef NO_INIT_DBCR0
+        _liwa   %r3, PPE42_DBCR_INITIAL
+        mtdbcr  %r3
+#endif
+
+        ## The exception vector prefix is set - it must be 512 byte aligned.
+        ## NOTE: for PPE42, the IVPR is read only, but can be changed through scoms
+        
+        #_liw    %r3, __vectors
+        #andi.   %r4, %r3, 0x01ff
+        #beq     1f
+        #_pk_panic PK_BOOT_VECTORS_NOT_ALIGNED
+#1:      
+        #mtivpr  %r3
+        #sync
+
+        ## The MSR to be used during the rest of intialization is
+        ## established.  This MSR should NOT enable 
+        ## interrupts, but could enable machine check exceptions.
+
+        _liwa   %r3, PPE42_MSR_INITIAL
+        mtmsr   %r3
+        sync
+
+#ifdef PK_BOOT_FROM_ROM
+
+        ## NB:  I don't think the old linker scripts were necessarily the most
+        ## optimal.  We need to revisit this if we actually do ROM boots in PK
+        ## Version 2. Not sure the comments are correct.
+
+        ## Data is copied from the initial ROM image to the RAM.  The 
+        ## address symbols are defined in the linker command file. The linker 
+        ## will have zeroed this area in the ROM image.
+
+        liw     %r3, __pk_ram_lma - 4 # src
+        liw     %r4, __pk_ram_vma - 4 # dest
+        liw     %r5, __pk_ram_size
+        liw     %r6, 2
+        srw     %r5, %r5, %r6   # Number of word transfers
+        mtctr   %r5
+
+copy_loop:
+        lwzu    %r5, 4(%r3)
+        stwu    %r5, 4(%r4)
+        bdnz    copy_loop
+
+#endif /* PK_BOOT_FROM_ROM */
+        
+
+        ## Call the system setup code.
+        
+        bl      __ppe42_system_setup
+        
+        ## Call the application. If for some reason we return from
+        ## the call of the application we call an alternate entry point of the
+        ## idle thread.
+        ##      
+        ## An initial argc/argv can be passed into main(). argc is expected to
+        ## be a 32-bit immediate integer, and argv is expected to be a 32-bit
+        ## absolute or relocatable expression. 
+
+        _liwa   %r3, PPE42_ARGC_INITIAL
+        _liw    %r4, PPE42_ARGV_INITIAL
+        bl      __pk_main
+
+        b       __pk_idle_thread_from_bootloader
+
+        .epilogue __pk_boot
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_cache.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_cache.h
new file mode 100644
index 00000000..cb06196d
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_cache.h
@@ -0,0 +1,126 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_cache.h $       */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PPE42_CACHE_H__
+#define __PPE42_CACHE_H__
+
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ppe42_cache.h
+/// \brief PowerPC-lite (PPE) cache management header for PK
+///
+/// The data cache flush/invalidate macros defined here create a compiler
+/// memory barrier that will cause GCC to flush/invalidate all memory data
+/// held in registers before the macro.
+
+#ifndef __ASSEMBLER__
+
+/// Determine cache-alignment of a pointer or byte-count
+#define cache_aligned(x) \
+    ((((unsigned long)(x)) & (POW2_32(LOG_CACHE_LINE_SIZE) - 1)) == 0)
+
+/// Cache-align a pointer or byte count. If the 'direction' is <= 0 then we
+/// round down, else round up.
+#define cache_align(x, direction)                                       \
+    ({                                                                  \
+        unsigned long __x = (unsigned long)(x);                         \
+        unsigned long __r;                                              \
+        if ((direction) <= 0) {                                         \
+            __r = __x & ~(((unsigned long)CACHE_LINE_SIZE) - 1);        \
+        } else {                                                        \
+            if (__x % CACHE_LINE_SIZE) {                                \
+                __r = __x + (CACHE_LINE_SIZE - (__x % CACHE_LINE_SIZE)); \
+            }                                                           \
+        }                                                               \
+        (void *)__r;                                                    \
+    })
+
+/// Data Cache Block Flush
+#define dcbf(p) asm volatile ("dcbf 0, %0" : : "r" (p) : "memory")
+
+/// Data Cache Block Touch
+#define dcbt(p) asm volatile ("dcbt 0, %0" : : "r" (p) : "memory")
+
+/// Data Cache Block Invalidate (Privileged)
+#define dcbi(p) asm volatile ("dcbi 0, %0" : : "r" (p) : "memory")
+
+void
+dcache_invalidate_all(void);
+
+void
+dcache_flush_all(void);
+
+void
+dcache_invalidate(void* p, size_t bytes);
+
+void
+dcache_flush(void* p, size_t bytes);
+
+/// Invalidate a line in the D-cache
+///
+/// \param p An address withing the cache line to be invalidated.
+///
+/// The dcache_invalidate_line() API is used to invalidate a single cache line
+/// containing the address \a p.  Note that invalidation is a destructive
+/// operation that may cause the loss of information.  It is the caller's
+/// responsibility to insure that no useful data is inadverdently invalidated.
+/// D-cache invalidation is more-or-less a no-op for data either not in the
+/// cache or marked as non-cacheable.
+///
+/// This API always issues a sync() after the invalidation.
+
+static inline void
+dcache_invalidate_line(void* p)
+{
+    dcbi(p);
+    sync();
+}
+
+/// Flush and invalidate a line from the D-cache
+///
+/// \param p An address within the cache line to be flushed.
+///
+/// The dcache_flush_line() API can be used as a shortcut to flush and
+/// invalidate a single cache line. Note that flushing is not a destructive
+/// operation in the sense that no information is lost, however the caller
+/// must make sure that the entirity of the data to be flushed is contained in
+/// the line that includes the address \a p. D-cache flush is more-or-less a
+/// no-op for data either not in the cache or marked as non-cacheable.
+///
+/// This API always issues a sync() after the flush.
+
+static inline void
+dcache_flush_line(void* p)
+{
+    dcbf(p);
+    sync();
+}
+
+#endif  /* __ASSEMBLER__ */
+
+#endif  /* __PPE42_CAHE_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_context.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_context.h
new file mode 100644
index 00000000..e54f255d
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_context.h
@@ -0,0 +1,228 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_context.h $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PPE42_CONTEXT_H__
+#define __PPE42_CONTEXT_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ppe42_context.h
+/// \brief PPE42 Machine and Thread context for PK
+
+/// \page ppe42_machine_context PPE42 Assembler Macros for PK Machine
+/// Context (Critical Sections)
+///
+/// \section _pk_enter_critical \b _pk_critical_section_enter/exit
+///
+/// These macro encapsulates the instruction sequences required to enter and
+/// exit critical sections, along with the machine context save for later
+/// exiting the critical section.
+///
+/// \arg \c ctxreg A register that will hold (holds) the machine context (MSR)
+/// prior to entering the critical section (to be restored) for \c
+/// _pk_critical_section_enter (\c _pk_critical_section_exit).
+///
+/// \arg \c scrreg A scratch register required for the computation of
+/// \c _pk_critical_section_enter.
+///
+/// Forms:
+///
+/// \b _pk_critical_section_enter \a priority, \a ctxreg, \a scrreg - Enter a
+/// critical section \n
+/// \b _pk_critical_section_exit \a ctxreg - Exit a critical section
+
+#ifdef __ASSEMBLER__
+// *INDENT-OFF*
+
+        .set    _msr_ee_bit, MSR_EE_BIT
+
+        .macro  _pk_critical_section_enter ctxreg, scrreg
+        mfmsr   \ctxreg
+        wrteei  0
+        .endm
+
+        .macro  _pk_critical_section_exit ctxreg
+        mtmsr   \ctxreg
+        .endm
+
+// ****************************************************************************
+// PK context save/restore macros for 32-bit Embedded PowerPC
+// ****************************************************************************
+
+// All stack frames are 8-byte aligned in conformance with the EABI.  PK
+// never saves or restores GPR2 or GPR13.  GPR13 is constant in (E)ABI
+// applications - the base of the read-write small data area.  GPR2 is
+// system-reserved in ABI applications, and is the base for read-only small data
+// in EABI applications.
+
+// USPRG0 holds the __PkKernelContext structure (defined in ppe42.h) that
+// represents the current kernel context.  The layout is as follows:
+//
+// Bits   Meaning
+// ==============
+// 0     The 'thread_mode' flag
+// 1     The 'processing_interrupt" flag
+// 2:7   The thread priority of the running thread
+// 8     The 'discard_ctx' flag
+// 9:15  The IRQ currently being processed
+// 16:31 The application specific data
+//
+// When PK is initialized USPRG0 is initialized to 0.  When thread-mode is
+// entered (by pk_start_threads()) bit 0 is set to 1.  If desired,
+// once initialized (with pk_initialize()) PK can simply
+// handle interrupts, reverting back to the non-thread-mode idle loop when
+// there's nothing to do.
+//      
+
+        ## ------------------------------------------------------------
+        ## Unused registers for embedded PPE42`
+        ## ------------------------------------------------------------
+
+        ## Registers GPR2 and GPR13 are never saved or restored.  In ABI and 
+        ## EABI applications these registers are constant.
+
+        .set    UNUSED_GPR2,  0x2 # Dedicated; EABI read-only small data area
+        .set    UNUSED_GPR13, 0xd # Dedicated; (E)ABI read-write small data area
+
+        ## ------------------------------------------------------------
+        ## The PK context layout for Embedded PPE42
+        ## ------------------------------------------------------------
+
+        .set    PK_CTX_GPR1,        0x00 # Dedicated; Stack pointer
+        .set    PK_CTX_LINKAGE,     0x04 # Slot for handler to store LR 
+        .set    PK_CTX_GPR3,        0x08 # Volatile;  Parameter; Return Value
+        .set    PK_CTX_GPR4,        0x0c # Volatile;  Parameter
+        .set    PK_CTX_GPR5,        0x10 # Volatile;  Parameter
+        .set    PK_CTX_GPR6,        0x14 # Volatile;  Parameter
+        .set    PK_CTX_CR,          0x18 # Condition register 
+        .set    PK_CTX_LR,          0x1c # Link register
+
+        .set    PK_CTX_GPR7,        0x20 # Volatile;  Parameter
+        .set    PK_CTX_GPR8,        0x24 # Volatile;  Parameter
+        .set    PK_CTX_GPR9,        0x28 # Volatile;  Parameter
+        .set    PK_CTX_GPR10,       0x2c # Volatile;  Parameter
+        .set    PK_CTX_GPR28,       0x30 # Non-volatile
+        .set    PK_CTX_GPR29,       0x34 # Non-volatile
+        .set    PK_CTX_GPR30,       0x38 # Non-volatile
+        .set    PK_CTX_GPR31,       0x3c # Non-volatile
+
+        .set    PK_CTX_XER,         0x40 # Fixed-point exception register
+        .set    PK_CTX_CTR,         0x44 # Count register
+        .set    PK_CTX_SRR0,        0x48 # Save/restore register 0
+        .set    PK_CTX_SRR1,        0x4c # Save/restore register 1
+        .set    PK_CTX_GPR0,        0x50 # Volatile;  Language specific
+        .set    PK_CTX_KERNEL_CTX,  0x54 # Saved __PkKernelContext for IRQ
+
+        .set    PK_CTX_SIZE,        0x58  # Must be 8-byte aligned
+
+        ## ------------------------------------------------------------
+        ## Push the interrupted context if necessary
+        ##
+        ## This macro saves off some context in preparation for calling
+        ## the pk_ctx_check_discard routine.  This is an attempt to use
+        ## the 32 byte cache more efficiently.
+        ## 
+        ## 8 Instructions
+        ## ------------------------------------------------------------
+        ##
+
+        .macro _pk_ctx_push_as_needed branch_addr:req
+
+        stwu    %r1,    -PK_CTX_SIZE(%r1)
+        stvd    %d3,    PK_CTX_GPR3(%r1)
+        mfcr    %r3
+        mflr    %r4
+        stvd    %d3,    PK_CTX_CR(%r1)
+        _liw    %r3,    \branch_addr
+        b       ctx_check_discard
+        .endm
+
+
+        ## ------------------------------------------------------------
+        ## update the kernel context in response to an interrupt.
+        ## ------------------------------------------------------------
+
+        ## The kernel context is updated with the currently active
+        ## IRQ in bits 9:15.  
+
+        .macro  _update_kernel_context irqreg, ctxreg
+        rlwimi  \ctxreg, \irqreg, 16, 9, 15 //set the irq #
+        oris    \ctxreg, \ctxreg, 0x4000 //set the 'processing_interrupt' flag
+        mtsprg0 \ctxreg
+
+#if PK_KERNEL_TRACE_ENABLE
+        mr      %r31, \irqreg
+        srwi    \ctxreg, \ctxreg, 16
+        PK_KERN_TRACE_ASM16("INTERRUPT_CONTEXT(0x%04x)", \ctxreg)
+        mr      \irqreg, %r31
+#endif        
+
+        .endm
+// *INDENT-ON*
+
+#else /* __ASSEMBLER__ */
+
+/// PK thread context layout as a C structure.
+///
+/// This is the structure of the stack area pointed to by
+/// thread->saved_stack_pointer when a thread is fully context-switched out.
+
+typedef struct
+{
+    uint32_t r1;
+    uint32_t linkage;
+    uint32_t r3;
+    uint32_t r4;
+    uint32_t r5;
+    uint32_t r6;
+    uint32_t cr;
+    uint32_t lr;
+
+    uint32_t r7;
+    uint32_t r8;
+    uint32_t r9;
+    uint32_t r10;
+    uint32_t r28;
+    uint32_t r29;
+    uint32_t r30;
+    uint32_t r31;
+
+    uint32_t xer;
+    uint32_t ctr;
+    uint32_t srr0;
+    uint32_t srr1;
+    uint32_t r0;
+    uint32_t sprg0;
+
+} PkThreadContext;
+
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __PPE42_CONTEXT_H__ */
+
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_core.c b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_core.c
new file mode 100644
index 00000000..ec8aec6d
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_core.c
@@ -0,0 +1,157 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_core.c $        */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ppe42_core.c
+/// \brief The final bits of PK runtime code required to complete the PPE42
+/// port.
+///
+/// The entry points in this file are considered 'core' routines that will
+/// always be present during runtime in any PK application.
+
+#define __PPE42_CORE_C__
+
+#include "pk.h"
+
+typedef union
+{
+    uint64_t    value;
+    struct
+    {
+        uint32_t dec_start;
+        uint32_t dec_change_tag;
+    };
+} ppe42_timebase_data_t;
+
+ppe42_timebase_data_t ppe42_tb_data = {0};
+PkTimebase  ppe42_64bit_timebase = 0;
+
+
+#if PK_TIMER_SUPPORT
+
+// The tickless kernel timer mechanism for PPE42
+//
+// This routine must be called from a critical section.
+//
+// Tickless timeouts are provided by programming the PIT timer based on when
+// the next timeout will occur.  If the timeout is for the end of time there's
+// nothing to do - PK does not use auto-reload mode so no more PIT interrupts
+// will be arriving.  Otherwise, if the timeout is longer than the 32-bit PIT
+// timer can handle, we simply schedule the timeout for 2**32 - 1 and
+// __pk_timer_handler() will keep rescheduling it until it finally occurs.
+// If the \a timeout is in the past, we schedule the PIT interrupt for 1 tick
+// in the future in accordance with the PK specification.
+
+#ifndef APPCFG_USE_EXT_TIMEBASE
+void
+__pk_schedule_hardware_timeout(PkTimebase timeout)
+{
+    PkTimebase       now;
+    uint32_t         new_dec;
+    uint32_t         dec;
+
+    if (timeout != PK_TIMEBASE_MAX)
+    {
+
+        now = pk_timebase_get();
+
+        if (timeout <= now)
+        {
+            new_dec = 1;
+        }
+        else if ((timeout - now) > 0xffff0000)
+        {
+            new_dec = 0xffff0000;
+        }
+        else
+        {
+            new_dec = timeout - now;
+        }
+
+        //read and write the DEC back-to-back so that we lose as little time
+        //as possible
+        dec = mfspr(SPRN_DEC);
+        mtspr(SPRN_DEC, new_dec);
+
+        //update our 64bit accumulator with how much time has advanced since
+        //we last changed it.
+        ppe42_64bit_timebase += ppe42_tb_data.dec_start - dec;
+
+        //update our start time so we know how much time has advanced since
+        //this update of the accumulator
+        ppe42_tb_data.dec_start = new_dec;
+        ppe42_tb_data.dec_change_tag++;
+    }
+}
+
+#else
+
+void
+__pk_schedule_hardware_timeout(PkTimebase timeout)
+{
+    PkTimebase       now;
+    PkTimebase       diff;
+    uint32_t         new_dec;
+
+    if (timeout != PK_TIMEBASE_MAX)
+    {
+
+        now = pk_timebase_get();
+
+        //update our 64bit accumulator with the current snapshot
+        ppe42_64bit_timebase = now;
+
+        if (timeout <= now)
+        {
+            new_dec = 1;
+        }
+        else
+        {
+            diff = (timeout - now);
+
+            if (diff > 0xfffffffful)
+            {
+                new_dec = 0xffffffff;
+            }
+            else
+            {
+                new_dec = diff;
+            }
+        }
+
+        mtspr(SPRN_DEC, new_dec);
+
+    }
+}
+
+#endif  /* APPCFG_USE_EXT_TIMEBASE */
+
+#endif  /* PK_TIMER_SUPPORT */
+
+#undef __PPE42_CORE_C__
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S
new file mode 100644
index 00000000..9c89284c
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S
@@ -0,0 +1,525 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S $  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+        
+/// \file ppe42_exceptions.S
+/// \brief PPE42 exception vector area.
+///
+/// \cond
+
+        .nolist
+#include "pk.h"
+        .list
+
+## declare and initializes global variables that hold external irq config data
+## Each PPE macro type (GPE, CME, and SBE) will have it's own implementation of this macro
+## defined in (gpe, cme, sbe)_common.h
+        .hwmacro_irq_cfg_bitmaps
+
+### ****************************************************************************
+### .vectors - This section contains all ppe42 exception vectors
+### 
+### ****************************************************************************
+
+        .section .vectors, "ax", @progbits
+
+        .global __vectors
+
+__vectors:
+
+        ############################################################
+        # 0x0000 : Machine Check
+        ############################################################
+
+        ### Unmaskable interrupts (including program interrupts) are promoted
+        ### to machine check interrupts if MSR[UIE] = 0 and MSR[ME] = 1.
+        ### If the machine check was caused by a program interrupt it
+        ### will be forwarded to the program exception handler.
+__machine_check:
+
+        PPE42_MACHINE_CHECK_HANDLER
+
+        ############################################################
+        # 0x0040 : System Reset
+        ############################################################
+        .global __system_reset
+        .org __vectors + 0x0040
+__system_reset:
+        b   __pk_boot
+
+        ############################################################
+        # 0x0060 : Data Storage Interrupt
+        ############################################################
+
+        .org __vectors + 0x0060
+__data_storage:
+
+        PPE42_DATA_STORAGE_HANDLER
+
+        ############################################################
+        # 0x0080 : Instruction Storage Interrupt
+        ############################################################
+
+        .org __vectors + 0x0080
+__instruction_storage:
+
+        PPE42_INSTRUCTION_STORAGE_HANDLER
+
+
+        ############################################################
+        # 0x00A0 : External Interrupt
+        ############################################################
+
+        .org __vectors + 0x00A0
+__external_interrupt_vector:
+        _pk_ctx_push_as_needed __get_ext_irq
+
+        ############################################################
+        # 0x00C0 : Alignment Exception
+        ############################################################
+
+        .org __vectors + 0x00C0
+__alignment_exception:
+
+        PPE42_ALIGNMENT_HANDLER
+
+
+        ############################################################
+        # 0x00E0 : Program Interrupt
+        ############################################################
+
+        .org __vectors + 0x00E0
+
+        ### Program exceptions are utilized for emulating the system call
+        ### instruction (0x44000002) which is used for doing context
+        ### switches between threads.  They can also be used by the code
+        ### to signal an exception in an error scenario.
+__program_exception:
+        _pk_ctx_push_as_needed  program_exception_handler 
+
+
+        ############################################################
+        # 0x0100 : DEC Interrupts
+        ############################################################
+
+        .org __vectors + 0x0100
+__dec_interrupt:
+        _pk_ctx_push_as_needed  dec_handler
+
+        ############################################################
+        # 0x0120 : FIT Interrupts
+        ############################################################
+        .org __vectors + 0x0120
+__fit_interrupt:        
+
+        _pk_ctx_push_as_needed  fit_handler
+
+        ############################################################
+        # 0x0140 : Watchdog Interrupts
+        ############################################################
+        .org __vectors + 0x0140
+__watchdog_interrupt:   
+
+        _pk_ctx_push_as_needed  watchdog_handler
+
+
+### ****************************************************************************
+### The rest of the code in this file doesn't have to be placed anywhere
+### special, so just place it in the .text section.
+### ****************************************************************************
+
+        .section .text, "ax", @progbits
+
+
+        ## The idle thread has no permanent register context.  The idle thread
+        ## entry point is re-entered whenever the idle thread is scheduled.
+
+        .global __pk_idle_thread
+        .global __pk_idle_thread_from_bootloader
+
+__pk_idle_thread:
+
+        ## The idle thread 'uses' the kernel stack.  Any register context
+        ## pushed here is redundant and is wiped out/ignored every time the
+        ## idle thread is re-scheduled. 
+        
+        ## The idle thread simply establishes a default machine context and
+        ## enters the wait-enable state.  The idle thread is always entered
+        ## with interrupts disabled.  
+        ##
+        ## The kernel context is initialized to indicate that the idle thread
+        ## is running - the idle thread priority is PK_THREADS, the
+        ## 'thread-mode' bit is asserted and so is the 'discard-ctx" bit.
+        ## In addition, the previous kernel context is stored in the lower
+        ## 16 bits.
+        ##
+        ## This loop can also be called from the PK bootloader if main()
+        ## returns - in which case we don't muck with the SPRG0 or the stack
+        ## pointer. 
+        mfsprg0 %r3         
+        srwi    %r3, %r3, 16
+        oris    %r3, %r3, (PK_THREADS << 8) | PPE42_THREAD_MODE | PPE42_DISCARD_CTX
+        mtsprg0        %r3
+        _lwzsd  %r1, __pk_kernel_stack
+                
+__pk_idle_thread_from_bootloader:
+
+        PK_KERN_TRACE_ASM16("ENTER_IDLE_STATE")
+
+        _lwzsd  %r3, __pk_thread_machine_context_default
+        _oriwa  %r3, %r3, MSR_WE
+        mtmsr   %r3
+        b       .
+
+        ## pk_halt() is implemented on the ppe42 by writing a value of 0x3 to
+        ## the RST field of the DBCR.
+        .global pk_halt
+pk_halt:
+        lis     %r31, 0x3000
+        mtdbcr  %r31
+        .long   0
+
+
+dec_handler:            
+
+        ## The portable timer handler of PK is a full-mode handler with the prototype:
+        ## void (*pk_timer_handler)(void).
+        ##
+        ## To support the portable specification, the kernel clears the
+        ## interrupt by writing the DIS back into the TSR before calling the
+        ## handler.  The timer handler does not take any arguments.
+
+        li      %r4, PPE42_IRQ_DEC
+        _update_kernel_context %r4, %r3
+        
+        _liwa   %r3, TSR_DIS
+        mttsr   %r3
+
+        bl      __pk_timer_handler
+        b       check_for_ext_interrupt
+
+program_exception_handler:
+        _pk_panic   PPE42_ILLEGAL_INSTRUCTION
+
+        .global __pk_next_thread_resume
+__pk_next_thread_resume:
+        
+        _lwzsd  %r3, __pk_next_thread
+        _stwsd  %r3, __pk_current_thread
+
+        ## Enter the wait enabled state if the thread pointer is null
+        bwz     %r3, __pk_idle_thread
+        
+        ## switch to the new thread stack 
+        lwz     %r1, PK_THREAD_OFFSET_SAVED_STACK_POINTER(%r3)
+
+        ## load sprg0 from the stack and update the thread priority
+        ## in case it changed.
+restore_and_update_sprg0:
+        _lbzsd  %r31, __pk_next_priority
+
+        PK_KERN_TRACE_ASM16("RESUME_THREAD(%d)", %r31)
+
+        lwz     %r3, PK_CTX_KERNEL_CTX(%r1)
+        rlwimi  %r3, %r31, 24, 2, 7
+        mtsprg0 %r3
+
+        b       ctx_pop
+ 
+fit_handler:
+        
+        ## The FIT handler is user defined. By
+        ## convention the kernel clears the interrupt by writing the FIS back
+        ## into the TSR.
+        
+        li      %r4, PPE42_IRQ_FIT
+                
+        _update_kernel_context %r4, %r3
+
+        _lwzsd  %r3, __ppe42_fit_arg
+
+        _liwa   %r6, TSR_FIS
+        mttsr   %r6
+
+        _lwzsd  %r6, __ppe42_fit_routine
+        mtlr    %r6
+        blrl
+        
+        b       check_for_ext_interrupt
+
+watchdog_handler:
+        ## Watchdog setup is described in the PK Specification. 
+        ## The kernel clears TSR[WIS] prior to calling the handler.  
+
+        li      %r4, PPE42_IRQ_WATCHDOG
+        
+        _update_kernel_context %r4, %r3
+
+        _liwa   %r6, TSR_WIS
+        mttsr   %r6
+
+        _lwzsd  %r6, __ppe42_watchdog_routine
+        mtlr    %r6
+        blrl
+
+        b       check_for_ext_interrupt
+
+
+        ## Check if we can disard the interrupted context.
+        ## This routine expects r3, r4, lr, and cr to already be pushed.
+        ## It also expects r3 to hold the address of the function to jump
+        ## to after the interrupted context has been pushed (if necessary).
+
+        .align 5
+ctx_check_discard:
+
+        ## Prepare to jump to the branch function that was passed in
+        mtlr    %r3 
+
+        ## Check if the DISCARD_CTX bit is set in the kernel context
+        mfsprg0 %r3
+        bb0wi   %r3, PPE42_DISCARD_CTX_BIT, ctx_continue_push
+
+ctx_discard:        
+        ## DISCARD_CTX bit was set.  Discard stack and branch to interrupt
+        ## handler code
+        addi    %r1, %r1, PK_CTX_SIZE
+        blr
+
+        ## DISCARD_CTX bit was not set.  Continue saving full context.
+        ## (r3, r4, lr, and cr have already been saved for us) and
+        ## r3 contains the interrupted kernel context
+
+        .global __ctx_switch
+__ctx_switch:
+        stwu    %r1,    -PK_CTX_SIZE(%r1)
+        stvd    %d3,    PK_CTX_GPR3(%r1)
+        mfcr    %r3
+        mflr    %r4
+        stvd    %d3,    PK_CTX_CR(%r1)
+        _liw    %r3     __pk_next_thread_resume
+        mtlr    %r3
+        ## emulate what interrupt would do
+        mtsrr0  %r4
+        mfmsr   %r3
+        mtsrr1  %r3
+
+        ## ctx_continue_push expects r3 to be value of sprg0
+        mfsprg0 %r3
+        
+ctx_continue_push:
+
+        stvd    %d5,    PK_CTX_GPR5(%r1)
+        stvd    %d7,    PK_CTX_GPR7(%r1)
+        stvd    %d9,    PK_CTX_GPR9(%r1)
+        stvd    %d28,   PK_CTX_GPR28(%r1)
+        stvd    %d30,   PK_CTX_GPR30(%r1)
+        mfxer   %r5
+        mfctr   %r6
+        stvd    %d5,    PK_CTX_XER(%r1)
+        mfsrr0  %r7
+        mfsrr1  %r8
+        stvd    %d7,    PK_CTX_SRR0(%r1)
+        stw     %r0,    PK_CTX_GPR0(%r1)
+        stw     %r3,    PK_CTX_KERNEL_CTX(%r1)
+        
+        ## If the 'processing interrupt' bit is set then we were already
+        ## using the kernel stack and don't need to modify or save the current
+        ## stack pointer.
+        bb1wi   %r3, PPE42_PROC_IRQ_BIT, ctx_push_completed
+
+        ## load the pointer to the current thread control block
+        _lwzsd  %r4, __pk_current_thread
+        
+        ## don't save the stack pointer in the thread control block
+        ## if the current thread was the idle thread (null pointer)
+        bwz     %r4, switch_to_kernel_stack
+
+        ## we interrupted a bonafide thread, so save off the stack
+        ## pointer
+        stw     %r1, PK_THREAD_OFFSET_SAVED_STACK_POINTER(%r4)
+
+switch_to_kernel_stack:
+        _stwsd  %r1, __pk_saved_sp
+        _lwzsd  %r1, __pk_kernel_stack
+       
+ctx_push_completed:      
+        blr
+
+__get_ext_irq:   
+        
+        ## Entry invariants:
+        ## 1. external interupts are disabled;
+        ## 2. previous context has ben saved off
+        ## 3. r3 contains the kernel context
+        ## 4. r1 points to the kernel stack
+
+        ## This is HW Macro specific code that is responsible for finding the
+        ## IRQ # and storing it in r4 (phantom IRQ's are assigned a value of EXTERNAL_IRQS).
+        
+        hwmacro_get_ext_irq        
+
+        ## An active or phantom IRQ was found. 
+        ## R3 has the context of the interrupted thread or bottom half
+        ## R4 has the IRQ number.
+        ## The IRQ is converted into a pointer to an 8-byte handler
+        ## structure, and the handler is dispatched. The call is made with the
+        ## parameters:
+
+        ## R3 = private data ptr
+        ## R4 = irq
+
+call_external_irq_handler:  
+
+        _update_kernel_context %r4, %r3
+        slwi    %r3, %r4, 3                 //multiply the irq# by 8
+        _liw    %r6, __ppe42_irq_handlers
+        lwzx    %r5, %r6, %r3
+        addi    %r3, %r3, 4
+        lwzx    %r3, %r6, %r3
+        mtlr    %r5
+        blrl
+                
+        ## Once the interrupt handler returns, check if any interrupts are
+        ## waiting and handle them now.
+
+check_for_ext_interrupt:
+
+        ## Set the CTX_DISCARD bit in the kernel context so that if there is
+        ## an interrupt it will not bother saving the full context.
+        mfsprg0 %r31
+        oris    %r31, %r31, PPE42_DISCARD_CTX
+        mtsprg0 %r31
+
+        ###### Enable/Disable External Interrupts #####
+        wrteei  1
+        wrteei  0
+
+        ## If we made it this far, there must not be any interrupts pending.
+        ## If bottom half processing was interrupted we need to restore it
+check_interrupted_bh:
+
+        ## If the thread ID is 33 then the bottom half handler was interrupted
+        ## and needs to be restored.
+        extrwi      %r4, %r31, 6, 2
+        cmpwi       %r4, 33
+        beq         ctx_pop_with_sprg0
+
+check_for_bh:
+        ## if the bottom half queue is pointing to itself then the queue is
+        ## empty and there are no bottom halves that need processing.
+        _lwzsd      %r4, _pk_bh_queue
+        lwz         %r5, 0(%r4)
+        cmplwbeq    %r4, %r5, restore_interrupted_sp
+
+process_bottom_halves:
+        ## Clear the CTX_DISCARD bit so that interrupted bottom half context
+        ## will be saved in case an interrupt occurs after this point.  Also
+        ## set the thread ID to 33 so that we know to restore the bottom half
+        ## context that was interrupted.
+        rlwinm  %r3, %r31, 0, 9, 1   //clear thread id + discard bit
+        oris    %r3, %r3, 0x2100    //set thread id to 33
+        mtsprg0 %r3                 //set bottom half context
+        
+        ## branch to a C function that processes bottom halves
+        wrteei  1
+        bl      _pk_process_bh
+        wrteei  0
+
+        ## restore the previous kernel context (with discard bit set)
+        mtsprg0 %r31
+
+restore_interrupted_sp:
+        ## restore the interrupted thread stack pointer
+        _lwzsd  %r1,   __pk_saved_sp
+
+        ## If we are not in thread mode (i.e., we took an interrupt in an
+        ## interupt-only configuration of PK or after pk_initialize() but
+        ## before pk_start_threads) simply pop the context and RFI - in this
+        ## case we'll most likely be returning to main() or the non-thread-mode
+        ## idle thread.
+
+check_thread_mode:
+        bb0wi   %r31, PPE42_THREAD_MODE_BIT, ctx_pop_with_sprg0
+
+        ## Check if external interrupt activated a delayed context switch.  The
+        ## C-level code has taken care of the scheduling decisions - we simply
+        ## need to implement them here.
+check_for_ctx_switch:
+
+        _lwzsd  %r3, __pk_delayed_switch
+        bwz     %r3, check_for_idle_thread
+
+        ## Clear the delayed switch flag and go to the context switch code to
+        ## finish the switch. 
+
+        li      %r3, 0
+        _stwsd  %r3, __pk_delayed_switch
+        
+        b       __pk_next_thread_resume
+
+        ## check if we should switch to the wait enabled state (idle)
+check_for_idle_thread:
+        _lwzsd  %r3, __pk_current_thread
+        bwz     %r3, __pk_idle_thread
+
+ctx_pop_with_sprg0:
+        ## we must ensure that interrupts are disabled while restoring context
+        ##
+        ## restore sprg0 from the saved context
+        lwz     %r0,    PK_CTX_KERNEL_CTX(%r1)
+        mtsprg0 %r0
+
+#if PK_KERNEL_TRACE_ENABLE
+        srwi    %r0, %r0, 16
+        PK_KERN_TRACE_ASM16("RESUME_CONTEXT(0x%04x)", %r0)
+#endif
+
+ctx_pop:
+        lwz     %r0,    PK_CTX_GPR0(%r1)
+        lvd     %d7,    PK_CTX_SRR0(%r1)
+        mtsrr1  %r8
+        mtsrr0  %r7
+        lvd     %d5,    PK_CTX_XER(%r1)
+        mtctr   %r6
+        mtxer   %r5
+        lvd     %d30,   PK_CTX_GPR30(%r1)
+        lvd     %d28,   PK_CTX_GPR28(%r1)
+        lvd     %d9,    PK_CTX_GPR9(%r1)
+        lvd     %d7,    PK_CTX_GPR7(%r1)
+        lvd     %d5,    PK_CTX_GPR5(%r1)
+        lvd     %d3,    PK_CTX_CR(%r1)
+        mtlr    %r4
+        mtcr0   %r3
+        lvd     %d3,    PK_CTX_GPR3(%r1)
+        addi    %r1,    %r1, PK_CTX_SIZE
+
+        rfi
+        
+/// \endcond
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_gcc.c b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_gcc.c
new file mode 100644
index 00000000..9b7aa8a8
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_gcc.c
@@ -0,0 +1,369 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_gcc.c $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ppe42_gcc.h
+/// \brief 32-bit PowerPC functions expected by GCC
+///
+/// GCC expects certain built-in functions to be defined in the environment.
+/// Since PK applications are statically linked, we must define these
+/// functions ourselves to avoid a static link with the GCC libraries, which
+/// would legaly require us to distribute (at least) the binary forms of PK
+/// applications.
+///
+/// We obviously had to look at some GCC library code to understand the
+/// specifications of these routines.  However, all of the code here is new -
+/// no structure definitions or lines of executable code were copied from the
+/// GCC sources.
+
+#include "pk.h"
+#include "ppe42_gcc.h"
+
+/// A 64-bit logical right shift.
+///
+/// Note that shifts with negative shift counts or shifts with shift counts
+/// longer than 63 bits are undefined.
+
+uint64_t
+__lshrdi3(uint64_t x, int i)
+{
+    Uint64 input, result;
+
+    if (i == 0)
+    {
+        return x;
+    }
+
+    input.value = x;
+
+    if (i >= 32)
+    {
+        result.word[0] = 0;
+        result.word[1] = input.word[0] >> (i - 32);
+    }
+    else
+    {
+        result.word[0] = input.word[0] >> i;
+        result.word[1] = (input.word[1] >> i) | (input.word[0] << (32 - i));
+    }
+
+    return result.value;
+}
+
+
+/// A 64 bit arithmetic left shift.
+///
+/// Note that shifts with negative shift counts or shifts with shift counts
+/// longer than 63 bits are undefined.
+
+uint64_t
+__ashldi3(uint64_t x, int i)
+{
+    Uint64 input, result;
+
+    if (i == 0)
+    {
+        return x;
+    }
+
+    input.value = x;
+
+    if (i >= 32)
+    {
+        result.word[1] = 0;
+        result.word[0] = input.word[1] << (i - 32);
+    }
+    else
+    {
+        result.word[1] = input.word[1] << i;
+        result.word[0] = (input.word[0] << i) | (input.word[1] >> (32 - i));
+    }
+
+    return result.value ;
+
+}
+
+
+/// A 64 bit arithmetic right shift.
+///
+/// Note that shifts with negative shift counts or shifts with shift counts
+/// longer than 63 bits are undefined.
+
+uint64_t
+__ashrdi3(uint64_t x, int i)
+{
+    Int64 input, result;
+
+    if (i == 0)
+    {
+        return x;
+    }
+
+    input.value = x;
+
+    if (i >= 32)
+    {
+        result.word[0] = input.word[0] >> 31;
+        result.word[1] = input.word[0] >> (i - 32);
+    }
+    else
+    {
+        result.word[0] = input.word[0] >> i;
+        result.word[1] =
+            (((uint32_t)input.word[1]) >> i) |
+            (input.word[0] << (32 - i));
+    }
+
+    return result.value ;
+
+}
+
+
+/// 32-bit Population count
+
+// This is a well-known divide-and-conquer algorithm, e.g. look on Wikipedia
+// under "Hamming Weight". The idea is to compute sums of adjacent bit
+// segments in parallel, in place.
+
+int
+__popcountsi2(uint32_t x)
+{
+    uint32_t m1 = 0x55555555;
+    uint32_t m2 = 0x33333333;
+    uint32_t m4 = 0x0f0f0f0f;
+    x -= (x >> 1) & m1;            /* Sum pairs of bits */
+    x = (x & m2) + ((x >> 2) & m2);/* Sum 4-bit segments */
+    x = (x + (x >> 4)) & m4;       /* Sum 8-bit segments */
+    x += x >>  8;                  /* Sum 16-bit segments */
+    return (x + (x >> 16)) & 0x3f; /* Final sum */
+}
+
+
+/// 64-bit Population count
+
+int
+__popcountdi2(uint64_t x)
+{
+    return __popcountsi2(x >> 32) + __popcountsi2(x & 0xffffffff);
+}
+
+
+// 64-bit divides
+//
+// For the unsigned case, note that divide by 0 returns quotient = remainder =
+// 0.
+//
+// For the signed case, in general we perform the division on the absolute
+// values and fix the signs of the quotient and remainder at the end.
+//
+// For the signed case, the convention in other libraries seems to be to
+// ignore the case of the most-negative integer.  Although it seems "wrong" to
+// return the wrong answer when the right answer can be easily computed, in
+// the interest of code size we follow the convention here and ignore the most
+// negative integer.
+//
+// The assembler routine __ppe42_udiv64() assembles to ??? bytes.  The full C
+// routine __ppc_sdiv64 compiles to ??? bytes with the most-negative checks,
+// but only ??? bytes as configured here.
+
+// For the signed cases, we need to handle the special case that the dividend
+// or divisor is the most negative integer.
+//
+// If the dividend is the most negative integer, then dividing this integer by
+// -1 would overflow as a positive quotient, so we set quotient and remainder
+// to 0 in this case.  For divide by 1, the quotient is the most negative
+// integer. Otherwise we adjust the dividend by the absolute value of the
+// divisor, then fix up the quotient later by adding or subtracting 1.
+//
+// If the divisor is the most negative integer, then the quotient is always 0
+// unless the dividend is also the most negative integer, in which case the
+// quotient is 1 and the remainder is 0.
+//
+
+uint64_t
+__udivdi3(uint64_t u, uint64_t v)
+{
+    uint64_t quotient, remainder;
+
+    __ppe42_udiv64(u, v, &quotient, &remainder);
+    return quotient;
+}
+
+
+uint64_t
+__umoddi3(uint64_t u, uint64_t v)
+{
+    uint64_t quotient, remainder;
+
+    __ppe42_udiv64(u, v, &quotient, &remainder);
+    return remainder;
+}
+
+
+#if 0
+    #define INT64_T_MIN ((int64_t)(0x8000000000000000ull))
+#endif
+
+void
+__ppe42_sdiv64(int64_t u, int64_t v,
+               int64_t* quotient, int64_t* remainder)
+{
+    int q_negate, r_negate;
+    uint64_t uu, uv;
+#if 0
+    int fixup = 0;
+#endif
+
+    q_negate = (u < 0) ^ (v < 0);
+    r_negate = (u < 0);
+    uu = (u < 0 ? -u : u);
+    uv = (v < 0 ? -v : v);
+
+#if 0
+
+    if (u == INT64_T_MIN)
+    {
+        if (v == -1)
+        {
+            *quotient = 0;
+            *remainder = 0;
+            return;
+        }
+        else if (v == 1)
+        {
+            *quotient = INT64_T_MIN;
+            *remainder = 0;
+            return;
+        }
+        else if (v == INT64_T_MIN)
+        {
+            *quotient = 1;
+            *remainder = 0;
+            return;
+        }
+        else
+        {
+            fixup = 1;
+            u += (v < 0 ? -v : v);
+        }
+    }
+    else if (v == INT64_T_MIN)
+    {
+        *quotient = 0;
+        *remainder = u;
+        return;
+    }
+
+#endif
+
+    __ppe42_udiv64(uu, uv, (uint64_t*)quotient, (uint64_t*)remainder);
+
+#if 0
+
+    if (fixup)
+    {
+        *quotient += 1;
+    }
+
+#endif
+
+    if (q_negate)
+    {
+        *quotient = -(*quotient);
+    }
+
+    if (r_negate)
+    {
+        *remainder = -(*remainder);
+    }
+}
+
+
+int64_t
+__divdi3(int64_t u, int64_t v)
+{
+    int64_t quotient, remainder;
+
+    __ppe42_sdiv64(u, v, &quotient, &remainder);
+    return quotient;
+}
+
+
+int64_t
+__moddi3(int64_t u, int64_t v)
+{
+    int64_t quotient, remainder;
+
+    __ppe42_sdiv64(u, v, &quotient, &remainder);
+    return remainder;
+}
+
+
+/// 64-bit unsigned compare as a function, returning 0 (<), 1 (==) or 2 (>).
+
+int
+__ucmpdi2(uint64_t i_a, uint64_t i_b)
+{
+    Uint64 a, b;
+    int rv;
+
+    a.value = i_a;
+    b.value = i_b;
+
+    if (a.word[0] < b.word[0])
+    {
+        rv = 0;
+    }
+    else if (a.word[0] > b.word[0])
+    {
+        rv = 2;
+    }
+    else if (a.word[1] < b.word[1])
+    {
+        rv = 0;
+    }
+    else if (a.word[1] > b.word[1])
+    {
+        rv = 2;
+    }
+    else
+    {
+        rv = 1;
+    }
+
+    return rv;
+}
+
+
+
+
+
+
+
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_gcc.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_gcc.h
new file mode 100644
index 00000000..7b9d37e1
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_gcc.h
@@ -0,0 +1,98 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_gcc.h $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PPE42_GCC_H__
+#define __PPE42_GCC_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ppe42_gcc.h
+/// \brief 32-bit functions expected by GCC
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+/// A 64-bit unsigned integer type
+
+typedef union
+{
+    uint64_t value;
+    uint32_t word[2];
+} Uint64;
+
+/// A 64-bit signed integer type
+
+typedef union
+{
+    int64_t value;
+    int32_t word[2];
+} Int64;
+
+uint64_t
+__lshrdi3(uint64_t x, int i);
+
+uint64_t
+__ashldi3(uint64_t x, int i);
+
+uint64_t
+__ashrdi3(uint64_t x, int i);
+
+int
+__popcountsi2(uint32_t x);
+
+int
+__popcountdi2(uint64_t x);
+
+/// Unsigned 64/64 bit divide, returning quotient and remainder via pointers.
+
+void
+__ppe42_udiv64(uint64_t u, uint64_t v, uint64_t* q, uint64_t* r);
+
+/// Signed 64/64 bit divide, returning quotient and remainder via pointers.
+
+void
+__ppe42_sdiv64(int64_t u, int64_t v, int64_t* q, int64_t* r);
+
+uint64_t
+__udivdi3(uint64_t u, uint64_t v);
+
+int64_t
+__divdi3(int64_t u, int64_t v);
+
+int64_t
+__moddi3(int64_t u, int64_t v);
+
+uint64_t
+__umoddi3(uint64_t u, uint64_t v);
+
+int
+__ucmpdi2(uint64_t a, uint64_t b);
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __PPE42_GCC_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_init.c b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_init.c
new file mode 100644
index 00000000..f81b5863
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_init.c
@@ -0,0 +1,102 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_init.c $        */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ppe42_init.c
+/// \brief PPE42 initialization routines
+///
+/// The entry points in this file are routines that are typically used during
+/// initialization, and their code space could be deallocated and recovered if
+/// no longer needed by the application after initialization.
+
+#include "pk.h"
+#include "pk_trace.h"
+
+// Note that __ppe42_system_setup() is called from the PK bootloader early
+// in the initialization, at a point before the aplication has enabled
+// interrupts.
+
+// This function is expected to be defined by the macro specific code (GPE, CME, SBE)
+void __hwmacro_setup(void);
+
+
+void
+__ppe42_system_setup()
+{
+    //Only do this if the application hasn't provided a static table definition
+#ifndef STATIC_IRQ_TABLE
+    PkIrqId irq;
+
+    // Initialize the interrupt vectors.
+    for (irq = 0; irq < EXTERNAL_IRQS; irq++)
+    {
+        __ppe42_irq_handlers[irq].handler = __ppe42_default_irq_handler;
+    }
+
+    //NOTE: EXTERNAL_IRQS is the phantom interrupt assigned irq
+    __ppe42_irq_handlers[irq].handler = __ppe42_phantom_irq_handler;
+
+    // Initialize special interrupt handlers
+
+    __ppe42_fit_routine = __ppe42_default_irq_handler;
+    __ppe42_fit_arg = 0;
+
+    __ppe42_watchdog_routine = __ppe42_default_irq_handler;
+    __ppe42_watchdog_arg = 0;
+
+    /*
+        __ppe42_debug_routine = __ppe42_default_irq_handler;
+        __ppe42_debug_arg = 0;
+    */
+#endif /*STATIC_IRQ_TABLE*/
+
+    //Clear all status bits in the TSR
+    mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
+
+#ifdef APPCFG_USE_EXT_TIMEBASE
+    //Enable the DEC interrupt and configure it to use the external dec_timer signal
+    mtspr(SPRN_TCR, TCR_DIE | TCR_DS);
+#else
+    //Enable the DEC interrupt and configure it to use the internal clock signal
+    mtspr(SPRN_TCR, TCR_DIE);
+#endif /* APPCFG_USE_EXT_TIMEBASE */
+
+#if PK_TIMER_SUPPORT
+#if PK_TRACE_SUPPORT
+    extern PkTraceBuffer g_pk_trace_buf;
+    //set the ppe instance id
+    g_pk_trace_buf.instance_id = (uint16_t)(mfspr(SPRN_PIR) & PIR_PPE_INSTANCE_MASK);
+#endif  /* PK_TRACE_SUPPORT */
+#endif  /* PK_TIMER_SUPPORT */
+
+    //call macro-specific setup
+    __hwmacro_setup();
+}
+
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq.h
new file mode 100644
index 00000000..24f30fa1
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq.h
@@ -0,0 +1,244 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq.h $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PPE42_IRQ_H__
+#define __PPE42_IRQ_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ppe42_irq.h
+/// \brief PPE42 interrupt handling for PK
+///
+/// Interrupt handling protocols and interrupt controller programming are
+/// inherently non-portable, however PK defines APIs that may be useful among
+/// different machines.
+///
+
+
+// Define pseudo-IRQ numbers for PPE42 built-in interrupts.  These numbers
+// will appear in bits 16:23 of SPRG0 (__PkKernelContext) when the handlers
+// are active
+
+#define PPE42_EXC_MACHINE_CHECK         0x50
+#define PPE42_EXC_DATA_STORAGE          0x53
+#define PPE42_EXC_INSTRUCTION_STORAGE   0x54
+#define PPE42_EXC_ALIGNMENT             0x56
+#define PPE42_EXC_PROGRAM               0x57
+#define PPE42_IRQ_DEC                   0x58
+#define PPE42_IRQ_FIT                   0x59
+#define PPE42_IRQ_WATCHDOG              0x5A
+
+
+//  Unhandled exceptions default to a kernel panic, but the application can
+//  override these definition.  Note that the exception area only allocates 32
+//  bytes (8 instructions) to an unhandled exception, so any redefinition
+//  would most likely be a branch to an application-defined handler.
+
+#ifndef PPE42_MACHINE_CHECK_HANDLER
+    #define PPE42_MACHINE_CHECK_HANDLER PK_PANIC( PPE42_MACHINE_CHECK_PANIC)
+#endif
+
+#ifndef PPE42_DATA_STORAGE_HANDLER
+    #define PPE42_DATA_STORAGE_HANDLER  PK_PANIC(PPE42_DATA_STORAGE_PANIC)
+#endif
+
+#ifndef PPE42_INSTRUCTION_STORAGE_HANDLER
+#define PPE42_INSTRUCTION_STORAGE_HANDLER \
+    PK_PANIC(PPE42_INSTRUCTION_STORAGE_PANIC)
+#endif
+
+#ifndef PPE42_ALIGNMENT_HANDLER
+    #define PPE42_ALIGNMENT_HANDLER     PK_PANIC(PPE42_DATA_ALIGNMENT_PANIC)
+#endif
+
+
+////////////////////////////////////////////////////////////////////////////
+//  PK API
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __ASSEMBLER__
+
+/// An IRQ handler takes 2 arguments:
+/// \arg \c arg - Private handler data installed by \c ssx_irq_setup() or
+///                   \c ssx_irq_handler_set().
+/// \arg \c irq     - The IRQ id; to enable a generic handler to manipulate
+///                   its own interrupt status .
+
+typedef void (*PkIrqHandler)(void* arg, PkIrqId irq);
+
+/// Declare a subroutine as an IRQ handler
+
+#define PK_IRQ_HANDLER(f) void f(void* arg, PkIrqId irq)
+
+int pk_irq_setup(PkIrqId irq,
+                 int      polarity,
+                 int      trigger);
+
+int pk_irq_handler_set(PkIrqId      irq,
+                       PkIrqHandler handler,
+                       void*         arg);
+
+void pk_irq_enable(PkIrqId irq);
+void pk_irq_disable(PkIrqId irq);
+void pk_irq_statusclear(PkIrqId irq);
+
+PK_IRQ_HANDLER(__ppe42_default_irq_handler);
+PK_IRQ_HANDLER(__ppe42_phantom_irq_handler);
+
+
+int
+ppe42_fit_setup(int tcr_fp, PkIrqHandler handler, void* arg);
+
+
+///  The address of the optional FIT interrupt handler
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+volatile
+PkIrqHandler __ppe42_fit_routine;
+
+
+/// The private data of the optional FIT interrupt handler
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+volatile
+void* __ppe42_fit_arg;
+
+
+int
+ppe42_watchdog_setup(int tcr_wp, int tcr_wrc,
+                     PkIrqHandler handler, void* arg);
+
+
+///  The address of the optional Watchdog interrupt handler
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+volatile
+PkIrqHandler __ppe42_watchdog_routine;
+
+
+/// The private data of the optional Watchdog interrupt handler
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+volatile
+void* __ppe42_watchdog_arg;
+
+
+int
+ppe42_debug_setup(PkIrqHandler handler, void* arg);
+
+
+///  The address of the optional Debug interrupt handler
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+volatile
+PkIrqHandler __ppe42_debug_routine;
+
+
+/// The private data of the optional Watchdog interrupt handler
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+volatile
+void* __ppe42_debug_arg;
+
+#endif  /* __ASSEMBLER__ */
+
+//  It's hard to be portable and get all of the definitions and headers in the
+//  correct order.  We need to bring in the system IRQ header here.
+
+#ifdef HWMACRO_GPE
+    #include "gpe_irq.h"
+#else
+    #ifdef HWMACRO_STD
+        #include "std_irq.h"
+    #endif
+#endif
+
+/// \page ppe42_irq_macros_page PPE42 PK IRQ Assembler Macros
+///
+///
+
+#ifndef __ASSEMBLER__
+
+
+///  This structure holds the interrupt handler routine addresses and private
+///  data.  Assembler code assumes the given structure layout, so any changes
+///  to this structure will need to be reflected down into the interrupt
+///  dispatch assembler code.
+
+typedef struct
+{
+    PkIrqHandler handler;
+    void*         arg;
+} Ppe42IrqHandler;
+
+
+#ifdef STATIC_IRQ_TABLE
+
+#define IRQ_HANDLER(func, arg) \
+    {func, arg},
+
+#define IRQ_HANDLER_DEFAULT \
+    {__ppe42_default_irq_handler, 0},
+
+#define EXTERNAL_IRQ_TABLE_END \
+    {__ppe42_phantom_irq_handler, 0}\
+    };
+
+#define EXTERNAL_IRQ_TABLE_START \
+    Ppe42IrqHandler __ppe42_irq_handlers[EXTERNAL_IRQS + 1] = \
+            {
+
+#else
+
+#define EXTERNAL_IRQ_TABLE_START
+
+#define IRQ_HANDLER(func, arg)
+
+#define IRQ_HANDLER_DEFAULT
+
+#define EXTERNAL_IRQ_TABLE_END
+
+#endif /*STATIC_IRQ_TABLE*/
+
+/// Interrupt handlers for real (implemented interrupts) plus one for the phantom interrupt handler
+extern Ppe42IrqHandler __ppe42_irq_handlers[EXTERNAL_IRQS + 1];
+
+
+/// The 'phantom interrupt' handler
+///
+/// A 'phantom' interrupt occurs when the interrupt handling code in the
+/// kernel is entered, but no interrupt is found pending in the controller.
+/// This is considered a serious bug, as it indictates a short window
+/// condition where a level-sensitive interrupt has been asserted and then
+/// quickly deasserted before it can be handled.
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+Ppe42IrqHandler __ppe42_phantom_irq;
+
+#endif  /* __ASSEMBLER__ */
+
+#endif  /* __PPE42_IRQ_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq_core.c b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq_core.c
new file mode 100644
index 00000000..0021457f
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq_core.c
@@ -0,0 +1,71 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_irq_core.c $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ppe42_irq_core.c
+/// \brief Core IRQ routines required of any PPE42 configuration of PK
+///
+///  This file is mostly only a placeholder - where 'extern inline' API
+///  functions and 'extern' variables are realized.  A couple of default
+///  handlers are also installed here.  The entry points in this file are
+///  considered 'core' routines that will always be present at runtime in any
+///  PK application.
+
+#define __PPE42_IRQ_CORE_C__
+
+#include "pk.h"
+
+#ifndef STATIC_IRQ_TABLE
+    Ppe42IrqHandler __ppe42_irq_handlers[EXTERNAL_IRQS + 1];
+#endif
+
+/// This function is installed by default for interrupts not explicitly set up
+/// by the application.  These interrupts should never fire.
+
+void
+__ppe42_default_irq_handler(void* arg, PkIrqId irq)
+{
+    PK_PANIC(PK_DEFAULT_IRQ_HANDLER);
+}
+
+
+/// This function is installed by default to handle the case that the
+/// interrupt dispatch code is entered in response to an external
+/// interrupt, but no interrupt is found pending in the interrupt
+/// controller.  This should never happen, as it would indicate that a
+/// 'glitch' occurred on the external interrupt input
+/// to the PPE42 core.
+
+void __ppe42_phantom_irq_handler(void* arg, PkIrqId irq)
+{
+    PK_PANIC(PPE42_PHANTOM_INTERRUPT);
+}
+
+
+#undef __PPE42_IRQ_CORE_C__
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h
new file mode 100644
index 00000000..8660f20d
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h
@@ -0,0 +1,112 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_msr.h $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PPE42_MSR_H__
+#define __PPE42_MSR_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ppe42_msr.h
+/// \brief Everything related to the PPE42 Machine State Register
+///
+/// All of the macros defined here that \e modify the MSR create a compiler
+/// memory barrier that will cause GCC to flush/invalidate all memory data
+/// held in registers before the macro. This is consistent with other systems,
+/// e.g., the PowerPC Linux kernel, and is the safest way to define these
+/// macros as it guarantess for example that kernel data structure updates
+/// have completed before exiting a critical section.
+
+#define MSR_SEM     0x7f000000      /* SIB Error Mask */
+#define MSR_IS0     0x00800000      /* Instance-Specific Field 0 */
+#define MSR_SIBRC   0x00700000      /* Last SIB return code */
+#define MSR_LP      0x00080000      /* Low Priority */
+#define MSR_WE      0x00040000      /* Wait State Enable */
+#define MSR_IS1     0x00020000      /* Instance-Specific Field 1 */
+#define MSR_UIE     0x00010000      /* Unmaskable Interrupt Enable */
+#define MSR_EE      0x00008000      /* External Interrupt Enable */
+#define MSR_ME      0x00001000      /* Machine Check Exception Enable */
+#define MSR_IPE     0x00000100      /* Imprecise Mode Enable */
+#define MSR_SIBRCA  0x000000ff      /* SIB Return Code Accumulator */
+
+//#define MSR_CE_BIT 14
+#define MSR_EE_BIT 16
+//#define MSR_IR_BIT 26
+//#define MSR_DR_BIT 27
+
+
+#define MSR_SEM_START_BIT       1
+#define MSR_SEM_LEN             7
+#define MSR_SIBRC_START_BIT     9
+#define MSR_SIBRC_LEN           3
+
+
+#ifndef __ASSEMBLER__
+
+/// Move From MSR
+
+#define mfmsr()                               \
+    ({uint32_t __msr;                          \
+        asm volatile ("mfmsr %0" : "=r" (__msr)); \
+        __msr;})
+
+
+/// Move to MSR
+
+#define mtmsr(value) \
+    asm volatile ("mtmsr %0" : : "r" (value) : "memory")
+
+
+/// Read-Modify-Write the MSR with OR (Set MSR bits).  This operation is only
+/// guaranteed atomic in a critical section.
+
+#define or_msr(x) \
+    mtmsr(mfmsr() | (x))
+
+
+/// Read-Modify-Write the MSR with AND complement (Clear MSR bits). This
+/// operation is only guaranteed atomic in a critical section.
+
+#define andc_msr(x) \
+    mtmsr(mfmsr() & ~(x))
+
+
+/// Write MSR[EE] with an immediate value (0/1)
+///
+/// Note that the immediate value \a i must be a compile-time constant.
+
+#define wrteei(i) \
+    asm volatile ("wrteei %0" : : "i" (i) : "memory")
+
+
+/// Write MSR[EE] from the EE bit of another MSR
+
+#define wrtee(other_msr) \
+    asm volatile ("wrtee %0" : : "r" (other_msr) : "memory")
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __PPE42_MSR_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.c b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.c
new file mode 100755
index 00000000..1dffcef4
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.c
@@ -0,0 +1,103 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.c $        */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file   ppe42_scom.c
+/// \brief  Lowest level PK SCOM definitions.
+///
+/// Currently these SCOM functions are only optimized for functionality, not
+/// speed. Speed optimization will be done when we have full compiler support
+/// for the low-level stvd and lvd SCOM OPs.
+///
+/// A FAPI-lite SCOM can call these PK SCOM functions.
+///
+/// Comment:
+/// - No need to poll for SCOM completion, nor return error code of SCOM fails.
+///   A SCOM fail will cause the GPE to hang if configured to do so. But do we
+///   necessarily have to do this?  Wouldn't a gentle recovery from a SCOM fail
+///   be preferred?
+
+#include "pk.h"
+#include "ppe42_scom.h"
+#include "ppe42_msr.h"
+
+
+uint32_t putscom_abs(const uint32_t i_address, uint64_t i_data)
+{
+
+    // Perform the Store Virtual Double instruction
+    PPE_STVD(i_address, i_data);
+
+    // Get the MSR[SIBRC] as the return code
+    uint32_t rc = mfmsr();
+    rc = ((rc & MSR_SIBRC) >> (32 - (MSR_SIBRC_START_BIT + MSR_SIBRC_LEN)));
+    return (rc);
+
+}
+
+uint32_t _putscom( uint32_t i_chiplet_id, uint32_t i_address, uint64_t i_data)
+{
+
+    // Perform the Store Virtual Double Index instruction
+    PPE_STVDX(i_chiplet_id, i_address, i_data);
+
+    // Get the MSR[SIBRC] as the return code
+    uint32_t rc = mfmsr();
+    rc = ((rc & MSR_SIBRC) >> (32 - (MSR_SIBRC_START_BIT + MSR_SIBRC_LEN)));
+    return (rc);
+
+}
+
+uint32_t getscom_abs( const uint32_t i_address, uint64_t* o_data)
+{
+    uint64_t temp;
+    // Perform the Load Virtual Double instruction
+    PPE_LVD(i_address, temp);
+    PPE_STVD(o_data, temp);
+
+    // Get the MSR[SIBRC] as the return code
+    uint32_t rc = mfmsr();
+    rc = ((rc & MSR_SIBRC) >> (32 - (MSR_SIBRC_START_BIT + MSR_SIBRC_LEN)));
+    return (rc);
+}
+
+
+uint32_t _getscom( const uint32_t i_chiplet_id, const uint32_t i_address, uint64_t* o_data)
+{
+    uint64_t temp;
+    // Perform the Load Virtual Double Index instruction
+    PPE_LVDX(i_chiplet_id, i_address, temp);
+    PPE_STVD(o_data, temp);
+
+    // Get the MSR[SIBRC] as the return code
+    uint32_t rc = mfmsr();
+    rc = ((rc & MSR_SIBRC) >> (32 - (MSR_SIBRC_START_BIT + MSR_SIBRC_LEN)));
+    return (rc);
+
+}
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.h
new file mode 100755
index 00000000..d3a8d2a7
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.h
@@ -0,0 +1,158 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_scom.h $        */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file  ppe42_scom.h
+/// \brief Include file for PK SCOMs
+///
+
+#ifndef __PK_SCOM_H__
+#define __PK_SCOM_H__
+
+/// SCOM operations return non-zero error codes that may or may not indicate
+/// an actual error, depending on which SCOM is begin accessed.  This error
+/// code will appear in the MSR[SIBRC] field, bits[9:11] right after the
+/// SCOM OP returns.  The error code value increases with the severity of the
+/// error.
+#define PCB_ERROR_NONE              0
+#define PCB_ERROR_RESOURCE_OCCUPIED 1
+#define PCB_ERROR_CHIPLET_OFFLINE   2
+#define PCB_ERROR_PARTIAL_GOOD      3
+#define PCB_ERROR_ADDRESS_ERROR     4
+#define PCB_ERROR_CLOCK_ERROR       5
+#define PCB_ERROR_PACKET_ERROR      6
+#define PCB_ERROR_TIMEOUT           7
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/// PPE Load Virtual Double operation
+#define PPE_LVD(_m_address, _m_data) \
+    asm volatile \
+    ( \
+      "lvd %[data], 0(%[address]) \n" \
+      :  [data]"=r"(_m_data) \
+      :  [address]"b"(_m_address) \
+    );
+
+
+// PPE Store Virtual Double operation
+#define PPE_STVD(_m_address, _m_data) \
+    asm volatile \
+    ( \
+      "stvd %[data], 0(%[address]) \n" \
+      : [data]"=&r"(_m_data) \
+      : "[data]"(_m_data), \
+      [address]"b"(_m_address) \
+      : "memory" \
+    );
+
+/// PPE Load Virtual Double Indexed operation
+#define PPE_LVDX(_m_base, _m_offset, _m_data) \
+    asm volatile \
+    ( \
+      "lvdx %[data], %[base], %[offset] \n" \
+      :  [data]"=r"(_m_data) \
+      :  [base]"b"(_m_base), \
+      [offset]"r"(_m_offset) \
+    );
+
+
+// PPE Store Virtual Double Indexed operation
+#define PPE_STVDX(_m_base, _m_offset, _m_data) \
+    asm volatile \
+    ( \
+      "stvdx %[data], %[base], %[offset] \n" \
+      : [data]"=&r"(_m_data) \
+      : "[data]"(_m_data), \
+      [base]"b"(_m_base), \
+      [offset]"r"(_m_offset) \
+      : "memory" \
+    );
+
+#define PPE_MFMSR(_m_data) \
+    asm volatile \
+    ( \
+      "mfmsr %[data] \n" \
+      :  [data]"=&r"(*_m_data) \
+      :  "[data]"(*_m_data) \
+    );
+
+/// @brief putscom with absolute address
+/// @param [in] i_address    Fully formed SCOM address
+/// @param [in] i_data       Pointer to uint64_t data to be written.  A pointer is used
+///                          to optimize the underlying hardware execution
+///
+/// @retval     On PPE42 platform, unmasked errors will take machine check interrupts
+uint32_t putscom_abs(const uint32_t i_address, uint64_t i_data);
+
+/// @brief getscom with absolute address
+/// @param [in]  i_address   Fully formed SCOM address
+/// @param [in] *o_data      Pointer to uint64_t data read
+///
+/// @retval     On PPE42 platform, unmasked errors will take machine check interrupts
+
+uint32_t getscom_abs( const uint32_t i_address, uint64_t* o_data);
+
+/// @brief Implementation of PPE putscom functionality
+/// @param [in] i_chiplet   Chiplet ID (@todo Should only be right justified)
+/// @param [in] i_address   Base SCOM address
+/// @param [in] i_data      Pointer to uint64_t data to be written.  A pointer is used
+///                         to optimize the underlying hardware execution
+///
+/// @retval     On PPE42 platform, unmasked errors will take machine check interrupts
+uint32_t _putscom( const uint32_t i_chiplet, const uint32_t i_address, uint64_t i_data);
+
+
+/// @brief Implementation of PPE getscom functionality
+/// @param [in] i_chiplet   Chiplet ID (@todo Should only be right justified)
+/// @param [in] i_address   Base SCOM address
+/// @param [in] i_data      Pointer to uint64_t data read
+///
+/// @retval     On PPE42 platform, unmasked errors will take machine check interrupts
+uint32_t _getscom( uint32_t i_chiplet, uint32_t i_address, uint64_t* o_data);
+
+extern inline uint32_t putscom(const uint32_t i_chiplet, const uint32_t i_address, uint64_t i_data)
+{
+    return _putscom(i_chiplet, i_address, i_data);
+}
+
+
+extern inline uint32_t getscom(const uint32_t i_chiplet, const uint32_t i_address, uint64_t* o_data)
+{
+    return _getscom(i_chiplet, i_address, o_data);
+}
+
+#ifdef __cplusplus
+} // extern C
+#endif
+
+#endif  // __PK_SCOM_H__
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_spr.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_spr.h
new file mode 100644
index 00000000..f95139bd
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_spr.h
@@ -0,0 +1,205 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_spr.h $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PPE42_SPR_H__
+#define __PPE42_SPR_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file ppe42_spr.h
+/// \brief Everything related to PPE42-specific SPRs
+
+/// \defgroup ppe42_sprs PPE42 SPRs
+///
+/// These are the documented SPRs of the PPE42.  Most of these SPRs are
+/// available in RISCWatch and eCmd using the defined names (minus SPRN_). In
+/// some cases RISCWatch/eCMD use different names, which appear in square
+/// brackets in the brief comments for each register. RISCWatch/eCMD also
+/// allow CR, MSR and IAR (Instruction Address Register) to be accessed as
+/// SPRs.
+///
+/// @{
+
+#define SPRN_XER         0x001 /// Fixed-point exception register    
+#define SPRN_LR          0x008 /// Link register                     
+#define SPRN_CTR         0x009 /// Count register
+#define SPRN_DEC         0x016 /// Decrementer
+#define SPRN_SRR0        0x01a /// Save/restore register 0           
+#define SPRN_SRR1        0x01b /// Save/restore register 1           
+#define SPRN_EDR         0x03d /// Error Data Register
+#define SPRN_ISR         0x03e /// Interrupt Status Register
+#define SPRN_IVPR        0x03f /// Interrupt Vector Prefix Register
+#define SPRN_SPRG0       0x110 /// SPR general register 0            
+#define SPRN_PIR         0x11e /// Processor Identification Register
+#define SPRN_PVR         0x11f /// Processor version register        
+#define SPRN_DBCR        0x134 /// Debug Control Register
+#define SPRN_DACR        0x13c /// Debug Address Compare Register
+#define SPRN_TSR         0x150 /// Timer Status Register
+#define SPRN_TCR         0x154 /// Timer Control Register
+
+/* DBCR - Debug Control Register */
+
+#define DBCR_RST_SOFT    0x10000000 /* Reset: 01=Soft Reset */
+#define DBCR_RST_HARD    0x20000000 /* Reset: 10=Hard Reset */
+#define DBCR_RST_HALT    0x30000000 /* Reset: 11=Halt */
+#define DBCR_TRAP        0x01000000 /* Trap Instruction Enable */
+#define DBCR_IACE        0x00800000 /* Instruction Address Compare Enable */
+#define DBCR_DACE_ST     0x00040000 /* Data Address Compare Enable: 01=store */
+#define DBCR_DACE_LD     0x00080000 /* Data Address Compare Enable: 10=load */
+#define DBCR_DACE_STLD   0x000C0000 /* Data Address Compare Enable: 11=both */
+
+/* TCR - Timer Control Register */
+
+#define TCR_WP_MASK    0xc0000000 /* Watchdog timer select bits */
+#define TCR_WP_0       0x00000000 /* WDT uses timer 0 */
+#define TCR_WP_1       0x40000000 /* WDT uses timer 1 */
+#define TCR_WP_2       0x80000000 /* WDT uses timer 2 */
+#define TCR_WP_3       0xc0000000 /* WDT uses timer 3 */
+#define TCR_WRC_MASK   0x30000000 /* Watchdog Reset Control mask */
+#define TCR_WRC_NONE   0x00000000 /* WDT results in no action */
+#define TCR_WRC_SOFT   0x10000000 /* WDT results in Soft reset */
+#define TCR_WRC_HARD   0x20000000 /* WDT results in Hard reset */
+#define TCR_WRC_HALT   0x30000000 /* WDT results in Halt */
+#define TCR_WIE        0x08000000 /* Watchdog Interrupt Enable */
+#define TCR_DIE        0x04000000 /* Decrementer Interrupt Enable */
+#define TCR_FP_MASK    0x03000000 /* FIT Timer Select bits*/
+#define TCR_FP_0       0x00000000 /* FIT uses timer 0 */
+#define TCR_FP_1       0x01000000 /* FIT uses timer 1 */
+#define TCR_FP_2       0x02000000 /* FIT uses timer 2 */
+#define TCR_FP_3       0x03000000 /* FIT uses timer 3 */
+#define TCR_FIE        0x00800000 /* FIT Interrupt Enable */
+#define TCR_DS         0x00400000 /* Decrementer timer select: 0=every cycle, 1=use dec_timer input signal */
+
+#ifndef __ASSEMBLER__
+
+typedef union
+{
+    uint32_t value;
+    struct
+    {
+        unsigned int wp       : 2;
+        unsigned int wrc      : 2;
+        unsigned int wie      : 1;
+        unsigned int die      : 1;
+        unsigned int fp       : 2;
+        unsigned int fie      : 1;
+        unsigned int ds       : 1;
+        unsigned int reserved : 22;
+    } fields;
+} Ppe42TCR;
+
+#endif /* __ASSEMBLER__ */
+
+/* TSR - Timer Status Register */
+
+#define TSR_ENW        0x80000000 /* Enable Next Watchdog */
+#define TSR_WIS        0x40000000 /* Watchdog Interrupt Status */
+#define TSR_WRS_MASK   0x30000000 /* Watchdog Reset Status */
+#define TSR_WRS_NONE   0x00000000 /* No watchdog reset has occurred */
+#define TSR_WRS_SOFT   0x10000000 /* Soft reset was forced by the watchdog */
+#define TSR_WRS_HARD   0x20000000 /* Hard reset was forced by the watchdog */
+#define TSR_WRS_HALT   0x30000000 /* Halt was forced by the watchdog */
+#define TSR_DIS        0x08000000 /* Decrementer Interrupt Status */
+#define TSR_FIS        0x04000000 /* FIT Interrupt Status */
+
+/* PIR - Processor Identification Register */
+#define PIR_PPE_TYPE_MASK       0x000000E0
+#define PIR_PPE_TYPE_GPE        0x00000020
+#define PIR_PPE_TYPE_CME        0x00000040
+#define PIR_PPE_INSTANCE_MASK   0x0000001F
+
+#ifndef __ASSEMBLER__
+
+/// Move From SPR
+///
+///  Note that \a sprn must be a compile-time constant.
+
+#define mfspr(sprn)                                             \
+    ({uint32_t __value;                                          \
+        asm volatile ("mfspr %0, %1" : "=r" (__value) : "i" (sprn)); \
+        __value;})
+
+
+/// Move to SPR
+///
+///  Note that \a sprn must be a compile-time constant.
+
+#define mtspr(sprn, value)                                        \
+    ({uint32_t __value = (value);                                  \
+        asm volatile ("mtspr %0, %1" : : "i" (sprn), "r" (__value)); \
+    })
+
+
+/// Read-Modify-Write an SPR with OR (Set SPR bits)
+///
+///  Note that \a sprn must be a compile-time constant. This operation is only
+///  guaranteed atomic in a critical section.
+
+#define or_spr(sprn, x) \
+    mtspr(sprn, mfspr(sprn) | (x))
+
+
+/// Read-Modify-Write an SPR with AND complement (Clear SPR bits)
+///
+///  Note that \a sprn must be a compile-time constant.  This operation is only
+///  guaranteed atomic in a critical section.
+
+#define andc_spr(sprn, x) \
+    mtspr(sprn, mfspr(sprn) & ~(x))
+
+#endif  /* __ASSEMBLER__ */
+
+#ifdef __ASSEMBLER__
+// *INDENT-OFF*
+
+        /// \cond
+
+        // Use this macro to define new mt<spr> and mf<spr> instructions that
+        // may not exist in the assembler.
+
+        .macro _sprinstrs, name, num 
+        .macro mt\name, reg
+        mtspr   \num, \reg
+        .endm
+        .macro mf\name, reg
+        mfspr   \reg, \num
+        .endm
+        .endm
+
+        _sprinstrs      dbcr,   SPRN_DBCR
+        _sprinstrs      tcr,    SPRN_TCR
+        _sprinstrs      tsr,    SPRN_TSR
+        _sprinstrs      sprg0,  SPRN_SPRG0
+        _sprinstrs      ivpr,   SPRN_IVPR
+        _sprinstrs      dec,    SPRN_DEC
+
+        /// \endcond
+
+// *INDENT-ON*
+#endif  /* __ASSEMBLER__ */
+
+#endif /* __PPE42_SPR_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_string.c b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_string.c
new file mode 100644
index 00000000..4f0e954c
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_string.c
@@ -0,0 +1,351 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_string.c $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+// Note: this code does not compile under the ppc2ppe backend.
+// It emits illegal ppe42 asm instructions.
+// __PPE42__ is set by the ppe42 compiler
+#ifdef __PPE42__
+
+#include <ppe42_string.h>
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+void* memset(void* vdest, int ch, size_t len)
+{
+    uint32_t addr = (uint32_t)vdest;
+
+    while(len && (addr & 0x7)) // not 8 byte aligned
+    {
+        uint8_t* p = (uint8_t*)addr;
+        *p = ch;
+        ++addr;
+        --len;
+    }
+
+    if(len >= sizeof(uint64_t))
+    {
+        uint64_t lch = ch & 0xff;
+        lch |= lch << 8;
+        lch |= lch << 16;
+        lch |= lch << 32;
+
+        while(len >= sizeof(uint64_t))
+        {
+            uint64_t* p = (uint64_t*)addr;
+            *p = lch;
+            len -= sizeof(uint64_t);
+            addr += sizeof(uint64_t);
+        }
+    }
+
+    while(len)
+    {
+        uint8_t* p = (uint8_t*)addr;
+        *p = ch;
+        ++addr;
+        --len;
+    }
+
+    return vdest;
+}
+
+
+void* memcpy(void* vdest, const void* vsrc, size_t len)
+{
+
+    // Loop, copying 4 bytes
+    long* ldest = (long*)vdest;
+    const long* lsrc = (const long*)vsrc;
+
+    while (len >= sizeof(long))
+    {
+        *ldest++ = *lsrc++;
+        len -= sizeof(long);
+    }
+
+    // Loop, copying 1 byte
+    char* cdest = (char*)ldest;
+    const char* csrc = (const char*)lsrc;
+    size_t i = 0;
+
+    for (; i < len; ++i)
+    {
+        cdest[i] = csrc[i];
+    }
+
+    return vdest;
+}
+
+void* memmove(void* vdest, const void* vsrc, size_t len)
+{
+    // Copy first-to-last
+    if (vdest <= vsrc)
+    {
+        return memcpy(vdest, vsrc, len);
+    }
+
+    // Copy last-to-first (TO_DO: optimize)
+    char* dest = (char*)(vdest);
+    const char* src = (const char*)(vsrc);
+    size_t i = len;
+
+    for (; i > 0;)
+    {
+        --i;
+        dest[i] = src[i];
+    }
+
+    return vdest;
+}
+
+int memcmp(const void* p1, const void* p2, size_t len)
+{
+    const char* c1 = (const char*)(p1);
+    const char* c2 = (const char*)(p2);
+
+    size_t i = 0;
+
+    for (; i < len; ++i)
+    {
+        long n = (long)(c1[i]) - (long)(c2[i]);
+
+        if (n != 0)
+        {
+            return n;
+        }
+    }
+
+    return 0;
+}
+
+void* memmem(const void* haystack, size_t haystacklen,
+             const void* needle, size_t needlelen)
+{
+    const void* result = NULL;
+
+    if (haystacklen >= needlelen)
+    {
+        const char* c_haystack = (const char*)(haystack);
+        const char* c_needle = (const char*)(needle);
+        bool match = false;
+
+        size_t i = 0;
+
+        for (; i <= (haystacklen - needlelen); i++)
+        {
+            match = true;
+
+            size_t j = 0;
+
+            for (; j < needlelen; j++)
+            {
+                if (*(c_haystack + i + j) != *(c_needle + j))
+                {
+                    match = false;
+                    break;
+                }
+            }
+
+            if (match)
+            {
+                result = (c_haystack + i);
+                break;
+            }
+        }
+    }
+
+    return (void*)(result);
+}
+
+
+char* strcpy(char* d, const char* s)
+{
+    char* d1 = d;
+
+    do
+    {
+        *d1 = *s;
+
+        if (*s == '\0')
+        {
+            return d;
+        }
+
+        d1++;
+        s++;
+    }
+    while(1);
+}
+
+char* strncpy(char* d, const char* s, size_t l)
+{
+    char* d1 = d;
+    size_t len = 0;
+
+    do
+    {
+        if (len++ >= l)
+        {
+            break;
+        }
+
+        *d1 = *s;
+
+        if (*s == '\0')
+        {
+            break;
+        }
+
+        d1++;
+        s++;
+    }
+    while(1);
+
+    // pad the remainder
+    while( len < l )
+    {
+        d1[len++] = '\0';
+    }
+
+    return d;
+}
+
+int strcmp(const char* a, const char* b)
+{
+    while((*a != '\0') && (*b != '\0'))
+    {
+        if (*a == *b)
+        {
+            a++;
+            b++;
+        }
+        else
+        {
+            return (*a > *b) ? 1 : -1;
+        }
+    }
+
+    if (*a == *b)
+    {
+        return 0;
+    }
+
+    if (*a == '\0')
+    {
+        return -1;
+    }
+    else
+    {
+        return 1;
+    }
+}
+
+size_t strlen(const char* a)
+{
+    size_t length = 0;
+
+    while(*a++)
+    {
+        length++;
+    }
+
+    return length;
+}
+
+size_t strnlen(const char* s, size_t n)
+{
+    size_t length = 0;
+
+    while((length < n) && (*s++))
+    {
+        length++;
+    }
+
+    return length;
+}
+
+char* strcat(char* d, const char* s)
+{
+    char* _d = d;
+
+    while(*_d)
+    {
+        _d++;
+    }
+
+    while(*s)
+    {
+        *_d = *s;
+        _d++;
+        s++;
+    }
+
+    *_d = '\0';
+
+    return d;
+}
+
+char* strncat(char* d, const char* s, size_t n)
+{
+    char* _d = d;
+
+    while(*_d)
+    {
+        _d++;
+    }
+
+    while((*s) && (0 != n))
+    {
+        *_d = *s;
+        _d++;
+        s++;
+        n--;
+    }
+
+    *_d = '\0';
+
+    return d;
+}
+
+
+char* strchr(const char* s, int c)
+{
+    while((*s != '\0') && (*s != c))
+    {
+        s++;
+    }
+
+    if (*s == c)
+    {
+        return (char*)s;
+    }
+
+    return NULL;
+}
+#ifdef __cplusplus
+};
+#endif
+#endif
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_string.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_string.h
new file mode 100644
index 00000000..dfa79c26
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_string.h
@@ -0,0 +1,73 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_string.h $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __STRING_H
+#define __STRING_H
+
+#include <stdint.h>
+typedef uint32_t size_t;
+
+#ifndef NULL
+    #ifdef __cplusplus
+        #define NULL 0
+    #else
+        #define NULL ((void*)0)
+    #endif
+#endif
+
+#ifndef __cplusplus
+    typedef int bool;
+    #define false 0
+    #define true 1
+#endif
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+void* memset(void* s, int c, size_t n) __attribute__ ((weak));
+//    void bzero(void *vdest, size_t len);   USE memset
+void* memcpy(void* dest, const void* src, size_t num) __attribute__ ((weak));
+void* memmove(void* vdest, const void* vsrc, size_t len)  __attribute__ ((weak));
+int memcmp(const void* p1, const void* p2, size_t len) __attribute__((weak, pure));
+void* memmem(const void* haystack, size_t haystacklen,
+             const void* needle, size_t needlelen) __attribute__((weak, pure));
+
+char* strcpy(char* d, const char* s)  __attribute__ ((weak));
+char* strncpy(char* d, const char* s, size_t l)  __attribute__ ((weak));
+int strcmp(const char* s1, const char* s2) __attribute__((weak, pure));
+size_t strlen(const char* s1) __attribute__((weak, pure));
+size_t strnlen(const char* s1, size_t n) __attribute__((weak, pure));
+
+char* strcat(char* d, const char* s)  __attribute__ ((weak));
+char* strncat(char* d, const char* s, size_t n)  __attribute__ ((weak));
+
+char* strchr(const char* s, int c) __attribute__((weak, pure));
+
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_thread_init.S b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_thread_init.S
new file mode 100644
index 00000000..1bed7882
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_thread_init.S
@@ -0,0 +1,134 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_thread_init.S $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+/// \file ppe42_thread_init.S
+/// \brief PPE42-specific thread initialization
+///
+/// The entry points in this file are routines that are typically used during
+/// initialization, and their code space could be deallocated and recovered if
+/// no longer needed by the application after initialization.
+
+        .nolist
+#include "pk.h"
+        .list
+        
+/// \fn void __pk_thread_context_initialize(PkThread *thread, PkThreadRoutine thread_routine, void *private)
+/// \brief Create the initial thread context on the stack
+///
+/// The non-reserved GPRs are prepatterned with 0x0000\<rn\>\<rn\> where \<rn\> is
+/// the register number (as decimal).  The initial context is set up with the
+/// thread running in the default machine context, and when the thread is
+/// switched in it will begin executing at the entry point of the thread
+/// routine with the \c private parameter in R3.  The LR is initialized such
+/// that when the thread returns, it will return to the entry point of \c
+/// pk_complete().
+#ifdef DOXYGEN_ONLY
+void 
+__pk_thread_context_initialize(PkThread        *thread, 
+                                PkThreadRoutine thread_routine, 
+                                void             *private);
+#endif
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+        
+/// \cond
+
+        .global_function __pk_thread_context_initialize
+
+__pk_thread_context_initialize:
+
+        ## R3 = thread (param)
+        ## R4 = thread_routine (param)
+        ## R5 = private (param)
+        ## R6 = thread stack pointer (computed)
+        ## R7 = scratch
+
+        .macro  _gpr_init, prefix, reg, val
+        li      %r7, \val
+        stw     %r7, \prefix\reg(%r6)
+        .endm
+
+        ## Initialize volatile context on the thread stack. The CR is cleared,
+        ## the LR = pk_complete(), R3 has the private parameter.
+
+        lwz     %r6, PK_THREAD_OFFSET_SAVED_STACK_POINTER(%r3)
+        
+        stwu    %r6, -PK_CTX_SIZE(%r6)
+
+        li      %r7, 0
+        stw     %r7, PK_CTX_CR(%r6)
+
+        _liw    %r7, pk_complete
+        stw     %r7, PK_CTX_LR(%r6)
+
+        stw     %r5, PK_CTX_GPR3(%r6)
+
+        _gpr_init PK_CTX_GPR, 4, 0x0404
+        _gpr_init PK_CTX_GPR, 5, 0x0505
+        _gpr_init PK_CTX_GPR, 6, 0x0606
+
+        ## XER and CTR are clear, SRR0 = thread_routine, SRR1 = default machine
+        ## context.
+
+        li      %r7, 0
+        stw     %r7, PK_CTX_XER(%r6)
+        stw     %r7, PK_CTX_CTR(%r6)
+
+        stw     %r4, PK_CTX_SRR0(%r6)
+
+        _lwzsd  %r7, __pk_thread_machine_context_default
+        stw     %r7, PK_CTX_SRR1(%r6)
+
+        _gpr_init PK_CTX_GPR, 0,  0x0000
+        _gpr_init PK_CTX_GPR, 7,  0x0707
+        _gpr_init PK_CTX_GPR, 8,  0x0808
+        _gpr_init PK_CTX_GPR, 9,  0x0909
+        _gpr_init PK_CTX_GPR, 10, 0x1010
+
+        ## Initialize the non-volatile context on the thread stack.
+
+        _gpr_init PK_CTX_GPR, 28, 0x2828       
+        _gpr_init PK_CTX_GPR, 29, 0x2929       
+        _gpr_init PK_CTX_GPR, 30, 0x3030       
+        _gpr_init PK_CTX_GPR, 31, 0x3131
+
+        ## Initialize the kernel context on the thread stack.
+        ## Note: Thread priority is set later each time the thread is
+        ##       resumed.
+
+        lis     %r7, PPE42_THREAD_MODE
+        stw     %r7, PK_CTX_KERNEL_CTX(%r6)
+
+        ## Initialization is done - the stack pointer is stored back in the
+        ## thread.
+
+        stw     %r6, PK_THREAD_OFFSET_SAVED_STACK_POINTER(%r3)
+        blr
+
+        .epilogue __pk_thread_context_initialize
+
+/// \endcond
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_timebase.S b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_timebase.S
new file mode 100644
index 00000000..cc40bce4
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_timebase.S
@@ -0,0 +1,140 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42_timebase.S $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// \file ppe42_timebase.S
+/// \brief PPE42-specific 64 bit timebase emulation
+///
+        .nolist
+#include "pk.h"
+        .list
+        
+/// \fn PkTimebase pk_timebase_get(void)
+/// \brief Returns a 64 bit timebase
+///
+#ifdef DOXYGEN_ONLY
+PkTimebase 
+pk_timebase_get(void);
+#endif
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+        
+/// \cond
+        .global ppe42_64bit_timebase
+        .global ppe42_tb_data
+        .global_function pk_timebase_get
+
+#ifndef APPCFG_USE_EXT_TIMEBASE
+
+        /// Note that it is ok to use this function in a fast interrupt
+        /// context
+        .align 5
+        .global_function pk_timebase32_get
+pk_timebase32_get:
+
+        //load the decrementer start time and change tag
+        lvd     %r4, ppe42_tb_data@sda21(0)
+
+        //load the lower 32 bits of the 64bit timebase accumulator
+        lwz     %r3, ppe42_64bit_timebase+4@sda21(0)
+
+        //load the current decrementer value
+        mfdec   %r0
+
+        //load the change tag again (should already be in the cache)
+        lwz     %r6, ppe42_tb_data+4@sda21(0)
+
+        //loop until the change tag is the same (typically should be same)
+        cmplwbne %r5, %r6, pk_timebase32_get
+
+        //calculate how much time has passed since the decrementer was started and store in r6
+        subf    %r5, %r0, %r4
+
+        //add the 32bit difference to our 32bit timebase accumulator
+        add     %r3, %r5, %r3
+
+        blr
+
+
+/// Use the DEC for our timebase until we have a real timebase register (uses
+/// 9 instructions).
+/// Note: It is not ok to use this function in a fast interrupt context due to
+///       its use of r7
+        .align 5
+pk_timebase_get:
+
+        //load the decrementer start time and change tag
+        lvd     %r5, ppe42_tb_data@sda21(0)
+
+        //load 64bit timebase accumulator
+        lvd     %r3, ppe42_64bit_timebase@sda21(0)
+
+
+        //load the current decrementer value
+        mfdec   %r0
+
+        //load the change tag again (should already be in the cache)
+        lwz     %r7, ppe42_tb_data+4@sda21(0)
+
+        //loop until the change tag is the same
+        cmplwbne %r6, %r7, pk_timebase_get
+
+        //calculate how much time has passed since the decrementer was started and store in r6
+        subf    %r6, %r0, %r5
+
+        //add the 32bit difference to the 64bit timebase accumulator
+        addc    %r4, %r6, %r4
+        addze   %r3, %r3
+
+        blr
+
+//enable this once we have a local timebase register in the model
+#else
+
+// use the local timebase register to keep more accurate time with just 6 instructions
+// in the common case and 7 otherwise.
+        .align 5
+pk_timebase_get:
+
+        //load the 64bit timebase accumulator
+        lvd         r3, ppe42_64bit_timebase@sda21(0)
+
+        //read the local timebase register (2 instructions)
+        _pk_timebase32_get r5, r5
+
+        //increment the upper 32 bits if the lower 32 bits have flipped
+        cmplwbge r5, r4, update_lower_32
+
+        //increment the upper 32 bits
+        addi        r3, r3, 1
+
+update_lower_32:
+        //replace the lower 32bits with what we read from the local timebase register
+        mr          r4, r5
+
+        blr
+#endif /* APPCFG_USE_EXT_TIMEBASE */
+/// \endcond
diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42math.h b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42math.h
new file mode 100644
index 00000000..e4f98cdd
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42math.h
@@ -0,0 +1,84 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/ppe42/ppe42math.h $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef _MATH_H
+#define _MATH_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+// These names are emitted by the ppe42 compiler.
+// Implement the ones that will be used.
+
+// 64 bit unsigned divide. Implement if needed
+// unsigned long long __udivdi3(unsigned long long a, unsigned long long b);
+
+/** 32 bit unsigned divide
+ *  @param[in] Dividend
+ *  @param[in] Divisor
+ *  @return quotient
+ */
+unsigned long __udivsi3(unsigned long a, unsigned long b);
+
+/** 32 bit signed divide
+ * @param[in] Dividend
+ * @param[in] Divisor
+ * @return quotient
+ */
+int __divsi3(int _a, int _b);
+
+/** 32 bit unsigned modulus
+ * @param[in] Dividend
+ * @param[in] Divisor
+ * @return modulus
+ */
+unsigned long __umodsi3(unsigned long a, unsigned long b);
+
+/** 32 bit unsigned multiply
+ * @param[in] multiplier
+ * @param[in] multiplier
+ * @return product
+ */
+unsigned long __umulsi3(unsigned long _a, unsigned long _b);
+
+/** 32 bit signed multiply
+ * @param[in] multiplier
+ * @param[in] multiplier
+ * @return product
+ */
+unsigned int __mulsi3(unsigned int _a, unsigned int _b);
+
+/** 64 bit signed multiply
+ * @param[in] multiplier
+ * @param[in] multiplier
+ * @return product
+ */
+unsigned long long __muldi3(unsigned long long _a, unsigned long long _b);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
diff --git a/src/import/chips/p9/procedures/ppe/pk/std/Makefile b/src/import/chips/p9/procedures/ppe/pk/std/Makefile
new file mode 100644
index 00000000..7d4613ed
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/std/Makefile
@@ -0,0 +1,74 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/ppe/pk/std/Makefile $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+# This Makefile compiles all of the PK code required for the STD (standard PPE) port
+# of PK.  See the "pk.mk" file in this directory.
+
+#all generated files from this makefile will end up in obj/$(IMAGE_NAME)/pk
+export SUB_OBJDIR = /pk
+
+include img_defs.mk
+include pkstdfiles.mk
+
+ifeq "$(PK_TIMER_SUPPORT)" "1"
+STD_OBJECTS += ${STD-TIMER-C-SOURCES:.c=.o} ${STD-TIMER-S-SOURCES:.S=.o}
+endif
+
+ifeq "$(PK_THREAD_SUPPORT)" "1"
+STD_OBJECTS += ${STD-THREAD-C-SOURCES:.c=.o} ${STD-THREAD-S-SOURCES:.S=.o}
+endif
+
+ifeq "$(STD_ASYNC_SUPPORT)" "1"
+STD_OBJECTS += ${STD-ASYNC-C-SOURCES:.c=.o} ${STD-ASYNC-S-SOURCES:.S=.o}
+endif
+
+OBJS := $(addprefix $(OBJDIR)/, $(STD_OBJECTS))
+
+libpk.a: kernel ppe42 trace std
+	$(AR) crs $(OBJDIR)/libpk.a $(OBJDIR)/*.o
+
+.PHONY: clean std kernel ppe42 trace
+std: $(OBJS)
+
+trace:
+	$(MAKE) -I $(BUILD_DIR) -C ../trace
+
+kernel:
+	$(MAKE) -I $(BUILD_DIR) -C ../kernel
+
+ppe42:
+	$(MAKE) -I $(BUILD_DIR) -C ../ppe42
+
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+clean:
+	rm -fr $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d) 
+endif
diff --git a/src/import/chips/p9/procedures/ppe/pk/std/pk_port.h b/src/import/chips/p9/procedures/ppe/pk/std/pk_port.h
new file mode 100644
index 00000000..d214ba1f
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/std/pk_port.h
@@ -0,0 +1,41 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/std/pk_port.h $             */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PK_PORT_H__
+#define __PK_PORT_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_port.h
+/// \brief The top-level standard PPE environment header for PK.
+
+#define HWMACRO_STD
+
+#include "ppe42.h"
+#include "std_timebase.h"
+
+#endif /* __PK_PORT_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/std/pkstdfiles.mk b/src/import/chips/p9/procedures/ppe/pk/std/pkstdfiles.mk
new file mode 100644
index 00000000..71b8521f
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/std/pkstdfiles.mk
@@ -0,0 +1,57 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/ppe/pk/std/pkstdfiles.mk $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file pkstdfiles.mk
+#
+#  @brief mk for including std object files
+#
+#  @page ChangeLogs Change Logs
+#  @section pkstdfiles.mk
+#  @verbatim
+#
+#
+# Change Log ******************************************************************
+# Flag     Defect/Feature  User        Date         Description
+# ------   --------------  ----------  ------------ -----------
+#
+# @endverbatim
+#
+##########################################################################
+# Object Files
+##########################################################################
+
+STD-C-SOURCES = std_init.c std_irq_init.c
+STD-S-SOURCES =
+
+STD-TIMER-C-SOURCES = 
+STD-TIMER-S-SOURCES = 
+
+STD-THREAD-C-SOURCES = 
+STD-THREAD-S-SOURCES = 
+
+STD-ASYNC-C-SOURCES =
+STD-ASYNC-S-SOURCES =
+
+STD_OBJECTS += $(STD-C-SOURCES:.c=.o) $(STD-S-SOURCES:.S=.o)
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/std/std.h b/src/import/chips/p9/procedures/ppe/pk/std/std.h
new file mode 100644
index 00000000..61b554bd
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/std/std.h
@@ -0,0 +1,44 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/std/std.h $                 */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __STD_H__
+#define __STD_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pgp.h
+/// \brief The STD environment for PK.
+
+#ifndef HWMACRO_STD
+    #define HWMACRO_STD
+    #include "ppe42.h"
+#endif
+
+#include "std_register_addresses.h"
+#include "std_common.h"
+
+#endif  /* __STD_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/std/std_common.h b/src/import/chips/p9/procedures/ppe/pk/std/std_common.h
new file mode 100644
index 00000000..a1f52eda
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/std/std_common.h
@@ -0,0 +1,90 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/std/std_common.h $          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __STD_COMMON_H__
+#define __STD_COMMON_H__
+
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file cme_common.h
+/// \brief Common header for standard PPE's
+///
+
+#ifndef __ASSEMBLER__
+    #include <stdint.h>
+#endif
+
+//#include "cmehw_interrupts.h"
+#include "pk.h"
+#include "std_irq_config.h"
+
+#ifdef __ASSEMBLER__
+// *INDENT-OFF*
+/// This macro contains standard PPE code for determining what IRQ caused the
+/// external exception handler to be invoked by the PPE
+
+/// Check for interrupts pending in the interrupt status register while the IRQ
+/// is computed.  The IRQ is expected to be stored in r4. If no IRQ is
+/// pending then load the phantom irq # (EXTERNAL_IRQS).
+/// 
+/// r1, r2, r3, and r13 must not be modified.  All other registers may be used.
+///
+/// The pk_unified_irq_prty_mask_handler routine MUST return the task priority
+/// interrupt vector in d5.
+///
+    .macro hwmacro_get_ext_irq
+
+#ifdef UNIFIED_IRQ_HANDLER_CME
+        // Unified approach.
+        _liw        r5, pk_unified_irq_prty_mask_handler
+        mtlr        r5
+        blrl            // On return, d5 contains task prty irq vec.
+#else
+        _lvdg       d5, STD_LCL_EISTR    #load the 64bit interrupt status into d5
+#endif        
+        cntlzw      r4, r5
+        cmpwible    r4, 31, call_external_irq_handler   #branch if irq is lt or eq to 31
+
+        ## No IRQ pending in r5.  Try r6.
+        ## Note: irq # will be 64 (phantom irq) if no bits were set in either register
+
+        cntlzw  r4, r6
+        addi    r4, r4, 32
+
+    .endm
+
+/// Redirect the .hwmacro_irq_cfg_bitmaps macro to call our standard PPE implementation
+/// This is called from the ppe42_exceptions.S file.
+    .macro .hwmacro_irq_cfg_bitmaps
+        .std_irq_cfg_bitmaps
+    .endm
+
+// *INDENT-ON*
+#endif /* __ASSEMBLER__ */
+
+#endif  /* __STD_COMMON_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/std/std_init.c b/src/import/chips/p9/procedures/ppe/pk/std/std_init.c
new file mode 100644
index 00000000..d2ea8c0b
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/std/std_init.c
@@ -0,0 +1,74 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/std/std_init.c $            */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file std_init.c
+/// \brief PK initialization for a standard PPE.
+///
+/// The entry points in this routine are used during initialization.  This
+/// code space can be deallocated and reassigned after application
+/// initialization if required.
+
+#include "pk.h"
+
+/// Standard PPE environment initial setup.
+///
+/// This is setup common to all standard PPE Macro applications.  This setup takes place
+/// during boot, before main() is called.
+
+void
+__hwmacro_setup(void)
+{
+    //mask all interrupts
+    out64(STD_LCL_EIMR_OR, 0xffffffffffffffffull);
+
+    //Set all interrupts to active low, level sensitive by default
+    out64(STD_LCL_EIPR_CLR, 0xffffffffffffffffull);
+    out64(STD_LCL_EITR_CLR, 0xffffffffffffffffull);
+
+    //set up the configured type
+    out64(STD_LCL_EITR_OR, g_ext_irqs_type);
+
+    //set up the configured polarity
+    out64(STD_LCL_EIPR_OR, g_ext_irqs_polarity);
+
+    //clear the status of all active-high interrupts (has no affect on
+    //level sensitive interrupts)
+    out64(STD_LCL_EISR_CLR, g_ext_irqs_polarity);
+
+    //clear the status of all active-low interrupts (has no affect on
+    //level sensitive interrupts)
+    out64(STD_LCL_EISR_OR, ~g_ext_irqs_polarity);
+
+    //unmask the interrupts that are to be enabled by default
+    out64(STD_LCL_EIMR_CLR, g_ext_irqs_enable);
+
+    //wait for the last operation to complete
+    sync();
+}
diff --git a/src/import/chips/p9/procedures/ppe/pk/std/std_irq.h b/src/import/chips/p9/procedures/ppe/pk/std/std_irq.h
new file mode 100644
index 00000000..4af55745
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/std/std_irq.h
@@ -0,0 +1,140 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/std/std_irq.h $             */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __STD_IRQ_H__
+#define __STD_IRQ_H__
+
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file occhw_irq.h
+/// \brief Standard PPE Externnal Interrupt handling for PK
+///
+/// The standard PPE interrupt controller supports a maximum of 64 interrupts with
+/// simple OR combining of the interrupt signals.
+///
+/// The standard PPE interrupt controller allows interrupt status to be set directly by
+/// software.  It contains a 'mask' register, unlike most 405 interrupt
+/// controllers that have an 'enable' register.  The standard PPE mask and status
+/// registers also have atomic CLR/OR function so that it is never necessary
+/// to enter a critical section to enable/disable/clear interrupts and
+/// interrupt status.
+
+#include "std_common.h"
+#include "std_register_addresses.h"
+#include "ppe42.h"
+
+#ifndef __ASSEMBLER__
+
+/// Enable an interrupt by clearing the mask bit.
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+inline void
+pk_irq_enable(PkIrqId irq)
+{
+    out64(STD_LCL_EIMR_CLR, STD_IRQ_MASK64(irq));
+}
+
+/// Enable a vector of interrupts by clearing the mask bits.
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+inline void
+pk_irq_vec_enable(uint64_t irq_vec_mask)
+{
+    out64(STD_LCL_EIMR_CLR, irq_vec_mask);
+}
+
+/// Disable an interrupt by setting the mask bit.
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+inline void
+pk_irq_disable(PkIrqId irq)
+{
+    out64(STD_LCL_EIMR_OR, STD_IRQ_MASK64(irq));
+}
+
+/// Disable a vector of interrupts by setting the mask bits.
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+inline void
+pk_irq_vec_disable(uint64_t irq_vec_mask)
+{
+    out64(STD_LCL_EIMR_OR, irq_vec_mask);
+}
+
+
+/// Clear interrupt status with an CLR mask.  Only meaningful for
+/// edge-triggered interrupts.
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+inline void
+pk_irq_status_clear(PkIrqId irq)
+{
+    out64(STD_LCL_EISR_CLR, STD_IRQ_MASK64(irq));
+}
+
+
+/// Clear a vector of interrupts status with an CLR mask.  Only meaningful for
+/// edge-triggered interrupts.
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+inline void
+pk_irq_vec_status_clear(uint64_t irq_vec_mask)
+{
+    out64(STD_LCL_EISR_CLR, irq_vec_mask);
+}
+
+/// Get IRQ status as a 0 or non-0 integer
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+inline int
+pk_irq_status_get(PkIrqId irq)
+{
+    return (in64(STD_LCL_EISR) & STD_IRQ_MASK64(irq)) != 0;
+}
+
+
+/// Set or clear interrupt status explicitly.
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+inline void
+pk_irq_status_set(PkIrqId irq, int value)
+{
+    if (value)
+    {
+        out64(STD_LCL_EISR_OR, STD_IRQ_MASK64(irq));
+    }
+    else
+    {
+        out64(STD_LCL_EISR_CLR, STD_IRQ_MASK64(irq));
+    }
+}
+
+
+#endif  /* __ASSEMBLER__ */
+
+#endif /* __STD_IRQ_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/std/std_irq_config.h b/src/import/chips/p9/procedures/ppe/pk/std/std_irq_config.h
new file mode 100644
index 00000000..66b8b018
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/std/std_irq_config.h
@@ -0,0 +1,169 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/std/std_irq_config.h $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __STD_IRQ_CONFIG_H__
+#define __STD_IRQ_CONFIG_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file std_irq_config.h
+/// \brief Contains data and macros pertaining to external interrupt
+/// configuration for a standard PPE.
+///
+
+#include "pk_app_cfg.h"
+
+/// This constant is used to define the size of the table of interrupt handler
+/// structures as well as a limit for error checking.
+#define EXTERNAL_IRQS 64
+
+// Standard interrupt type values (level or edge)
+#define STD_IRQ_TYPE_LEVEL            0
+#define STD_IRQ_TYPE_EDGE             1
+
+// Standard interrupt polarity values (high or low, rising falling)
+#define STD_IRQ_POLARITY_LO           0
+#define STD_IRQ_POLARITY_FALLING      0
+#define STD_IRQ_POLARITY_HI           1
+#define STD_IRQ_POLARITY_RISING       1
+
+// Standard interrupt mask values (masked or enabled)
+#define STD_IRQ_MASKED                0
+#define STD_IRQ_ENABLED               1
+
+// Fail to compile if the application does not define this
+#ifndef APPCFG_EXT_IRQS_CONFIG
+    #error "APPCFG_EXT_IRQS_CONFIG must be defined in pk_app_cfg.h"
+#endif
+
+// Fail to compile if the application does not define this
+#ifndef APPCFG_IRQ_INVALID_MASK
+    #error "APPCFG_IRQ_INVALID_MASK must be defined in pk_app_cfg.h"
+#endif
+
+#ifndef __ASSEMBLER__
+
+/// This expression recognizes only those IRQ numbers that have named
+/// (non-reserved) interrupts in the standard PPE interrupt controller.
+#define STD_IRQ_VALID(irq) \
+    ({unsigned __irq = (unsigned)(irq);         \
+        ((__irq < EXTERNAL_IRQS) &&             \
+         ((STD_IRQ_MASK64(__irq) &              \
+           APPCFG_IRQ_INVALID_MASK) == 0));})
+
+/// This is a 64-bit mask, with big-endian bit 'irq' set.
+#define STD_IRQ_MASK64(irq) (0x8000000000000000ull >> (irq))
+
+#else
+
+//Untyped assembler version of STD_IRQ_MASK64
+#define STD_IRQ_MASK64(irq) (0x8000000000000000 >> (irq))
+
+#endif  /* __ASSEMBLER__ */
+
+#ifndef __ASSEMBLER__
+    /// These globals are statically initialized elsewhere
+    extern uint64_t g_ext_irqs_type;
+    extern uint64_t g_ext_irqs_valid;
+    extern uint64_t g_ext_irqs_polarity;
+    extern uint64_t g_ext_irqs_enable;
+#endif
+
+#ifdef __ASSEMBLER__
+// *INDENT-OFF*
+/// These macros aid in the initialization of the external interrupt globals.  I would
+/// prefer to use CPP macros, but they don't support recursive macros which I use to
+/// convert the variable number of interrupts that a processor can control into static
+/// bitmaps used by __hwmacro_setup() at runtime.
+
+
+    //helper macro for setting up the irq configuration bitmaps for a standard PPE
+    .macro .std_irq_config irq_num=-1 irq_type=-1 irq_polarity=-1 irq_mask=-1 parms:vararg
+        .if (( \irq_num == -1 ) && ( \irq_type == -1 ) && ( \irq_polarity == -1 ) && ( \irq_mask == -1 ))
+#.if ( .ext_irqs_defd != .ext_irqs_valid )
+#.error "###### .std_irq_config: Missing configuration for one or more interrupts ######"
+#.endif
+
+            .section .sdata
+            .align 3
+            .global g_ext_irqs_type
+            .global g_ext_irqs_polarity
+            .global g_ext_irqs_enable
+            g_ext_irqs_polarity:
+            .quad .ext_irqs_polarity
+            g_ext_irqs_type:
+            .quad .ext_irqs_type
+            g_ext_irqs_enable:
+            .quad .ext_irqs_enable
+        .else
+            .if (( \irq_num < 0 ) || ( \irq_num > (EXTERNAL_IRQS - 1)))
+                .error "###### .std_irq_config: invalid irq number \irq_num ######"
+            .elseif ((.ext_irqs_valid & (1 << ( EXTERNAL_IRQS - 1 - \irq_num ))) == 0 )
+                .error "###### .std_irq_config: Attempt to configure invalid irq number \irq_num ######" 
+            .elseif (.ext_irqs_defd & (1 << ( EXTERNAL_IRQS - 1 - \irq_num )))
+                .error "###### .std_irq_config: duplicate definition for irq \irq_num ######"
+            .else
+                .ext_irqs_defd = .ext_irqs_defd | (1 << ( EXTERNAL_IRQS - 1 - \irq_num ))
+            .endif
+
+            .if (( \irq_type < 0 ) || ( \irq_type > 1 ))
+                .error "###### .std_irq_config: invalid/unspecified irq type \irq_type for irq \irq_num ######" 
+            .else
+                .ext_irqs_type = .ext_irqs_type | ( \irq_type << ( EXTERNAL_IRQS - 1 - \irq_num ))
+            .endif
+
+            .if (( \irq_polarity < 0 ) || ( \irq_polarity > 1 ))
+                .error "###### .std_irq_config: invalid/unspecified irq polarity ( \irq_polarity ) for irq \irq_num ######" 
+            .else
+                .ext_irqs_polarity = .ext_irqs_polarity | ( \irq_polarity << ( EXTERNAL_IRQS - 1 - \irq_num ))
+            .endif
+
+            .if (( \irq_mask < 0 ) || ( \irq_mask > 1 ))
+                .error "###### .std_irq_config: invalid/unspecified irq mask ( \irq_mask ) for irq \irq_num ######" 
+            .else
+                .ext_irqs_enable = .ext_irqs_enable | ( \irq_mask << ( EXTERNAL_IRQS - 1 - \irq_num ))
+            .endif
+
+            .std_irq_config \parms
+        .endif
+    .endm
+
+    //Top level macro for generating interrupt configuration globals for a standard PPE
+    .macro .std_irq_cfg_bitmaps
+        .ext_irqs_valid = ~(APPCFG_IRQ_INVALID_MASK)
+        .ext_irqs_type = 0
+        .ext_irqs_polarity = 0
+        .ext_irqs_enable = 0
+        .irq_mask = 0
+        .ext_irqs_defd = 0
+        .std_irq_config APPCFG_EXT_IRQS_CONFIG
+    .endm
+
+// *INDENT-ON*
+#endif /*__ASSEMBLER__*/
+
+#endif /*__STD_IRQ_CONFIG_H__*/
diff --git a/src/import/chips/p9/procedures/ppe/pk/std/std_irq_init.c b/src/import/chips/p9/procedures/ppe/pk/std/std_irq_init.c
new file mode 100644
index 00000000..1115c4bb
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/std/std_irq_init.c
@@ -0,0 +1,137 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/std/std_irq_init.c $        */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file std_irq_init.c
+/// \brief Standard PPE IRQ initialization code for PK
+///
+///  The entry points in this file are initialization routines that could be
+///  eliminated/deallocated by the application to free up storage if they are
+///  no longer needed after initialization.
+
+#include "pk.h"
+
+/// Define the polarity and trigger condition for an interrupt.
+///
+/// It is up to the application to take care of any side effects that may
+/// occur from programming or reprogramming the interrupt controller.  For
+/// example, changing edge/level sensitivity or active level may set or clear
+/// interrupt status in the controller.
+///
+/// Note that PK allows this API to be called from any context, and changes
+/// to the interrupt controller are made from a critical section.
+///
+/// Return values other then PK_OK (0) are errors; see \ref pk_errors
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_INVALID_ARGUMENT_IRQ_SETUP One or more arguments are invalid,
+/// including an invalid \a irq, or invalid \a polarity or \a trigger parameters.
+
+int
+pk_irq_setup(PkIrqId irq,
+             int      polarity,
+             int      trigger)
+{
+    PkMachineContext ctx;
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(!STD_IRQ_VALID(irq) ||
+                    !((polarity == PK_IRQ_POLARITY_ACTIVE_HIGH) ||
+                      (polarity == PK_IRQ_POLARITY_ACTIVE_LOW)) ||
+                    !((trigger == PK_IRQ_TRIGGER_LEVEL_SENSITIVE) ||
+                      (trigger == PK_IRQ_TRIGGER_EDGE_SENSITIVE)),
+                    PK_INVALID_ARGUMENT_IRQ_SETUP);
+    }
+
+    pk_critical_section_enter(&ctx);
+
+    if (polarity == PK_IRQ_POLARITY_ACTIVE_HIGH)
+    {
+        out64(STD_LCL_EIPR_OR, STD_IRQ_MASK64(irq));
+    }
+    else
+    {
+        out64(STD_LCL_EIPR_CLR, STD_IRQ_MASK64(irq));
+    }
+
+    if (trigger == PK_IRQ_TRIGGER_EDGE_SENSITIVE)
+    {
+        out64(STD_LCL_EITR_OR, STD_IRQ_MASK64(irq));
+    }
+    else
+    {
+        out64(STD_LCL_EITR_CLR, STD_IRQ_MASK64(irq));
+    }
+
+    pk_critical_section_exit(&ctx);
+
+    return PK_OK;
+}
+
+
+/// (Re)define the IRQ handler and priority for an interrupt.
+/// Return values other then PK_OK (0) are errors; see \ref pk_errors
+///
+/// Note that PK allows this API to be called from any context, and changes
+/// to the interrupt controller are made from a critical section.
+///
+/// \retval 0 Successful completion
+///
+/// \retval -PK_INVALID_ARGUMENT_IRQ_HANDLER One or more arguments are
+/// invalid, including an invalid \a irq, a  null (0) \a handler,
+/// or invalid \a priority.
+
+int
+pk_irq_handler_set(PkIrqId      irq,
+                   PkIrqHandler handler,
+                   void*          arg)
+{
+    PkMachineContext ctx;
+
+    if (PK_ERROR_CHECK_API)
+    {
+        PK_ERROR_IF(!STD_IRQ_VALID(irq) ||
+                    (handler == 0),
+                    PK_INVALID_ARGUMENT_IRQ_HANDLER);
+    }
+
+    pk_critical_section_enter(&ctx);
+
+    __ppe42_irq_handlers[irq].handler = handler;
+    __ppe42_irq_handlers[irq].arg = arg;
+
+    pk_critical_section_exit(&ctx);
+
+    return PK_OK;
+}
+
+
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/std/std_register_addresses.h b/src/import/chips/p9/procedures/ppe/pk/std/std_register_addresses.h
new file mode 100644
index 00000000..1a6b56fc
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/std/std_register_addresses.h
@@ -0,0 +1,73 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/std/std_register_addresses.h $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __STD_REGISTER_ADDRESSES_H__
+#define __STD_REGISTER_ADDRESSES_H__
+
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file std_register_addresses.h
+/// \brief Symbolic addresses for a standard PPE
+
+#include "pk.h"
+
+// Define the base address for the external interrupt controller registers
+// This can be overridden in the pk_app_cfg.h file
+#ifndef STD_EIC_BASE
+    #define STD_EIC_BASE 0xC0000000
+#endif
+
+// Define the base address for the PPE mode registers
+// This can be overridden in the pk_app_cfg.h file
+#ifndef STD_PMR_BASE
+    #define STD_PMR_BASE 0xC0000100
+#endif
+
+// Note: This list only contains registers that are needed by PK.  If
+// an application requires other registers, it should define them
+// elsewhere (i.e., cme_register_addresses.h)
+#define STD_LCL_EISR        (STD_EIC_BASE + 0x0000)
+#define STD_LCL_EISR_OR     (STD_EIC_BASE + 0x0010)
+#define STD_LCL_EISR_CLR    (STD_EIC_BASE + 0x0018)
+#define STD_LCL_EIMR        (STD_EIC_BASE + 0x0020)
+#define STD_LCL_EIMR_OR     (STD_EIC_BASE + 0x0030)
+#define STD_LCL_EIMR_CLR    (STD_EIC_BASE + 0x0038)
+#define STD_LCL_EIPR        (STD_EIC_BASE + 0x0040)
+#define STD_LCL_EIPR_OR     (STD_EIC_BASE + 0x0050)
+#define STD_LCL_EIPR_CLR    (STD_EIC_BASE + 0x0058)
+#define STD_LCL_EITR        (STD_EIC_BASE + 0x0060)
+#define STD_LCL_EITR_OR     (STD_EIC_BASE + 0x0070)
+#define STD_LCL_EITR_CLR    (STD_EIC_BASE + 0x0078)
+#define STD_LCL_EISTR       (STD_EIC_BASE + 0x0080)
+#define STD_LCL_EINR        (STD_EIC_BASE + 0x00a0)
+
+#define STD_LCL_TSEL        (STD_PMR_BASE + 0x0000)
+#define STD_LCL_TBR         (STD_PMR_BASE + 0x0040)
+
+#endif // __STD_REGISTER_ADDRESSES_H__
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/std/std_timebase.h b/src/import/chips/p9/procedures/ppe/pk/std/std_timebase.h
new file mode 100644
index 00000000..f3f07448
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/std/std_timebase.h
@@ -0,0 +1,66 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/std/std_timebase.h $        */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __STD_TIMEBASE_H__
+#define __STD_TIMEBASE_H__
+
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2015
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file std_timebase.h
+/// \brief support for using the standard PPE 32 bit timebase register
+///
+/// Each standard PPE has it's own timebase register that runs at a constant
+/// frequency.
+
+#include "pk.h"
+
+#ifndef __ASSEMBLER__
+
+#ifndef APPCFG_USE_EXT_TIMEBASE
+static inline
+uint32_t pk_timebase32_get(void)
+{
+    return (uint32_t)((in64(STD_LCL_TBR)) >> 32);
+}
+
+#else
+//assembly function is defined in ppe42_timebase.S
+uint32_t pk_timebase32_get(void);
+
+#endif  /* APPCFG_USE_EXT_TIMEBASE */
+
+#else
+
+.macro _pk_timebase32_get rT, rA
+lis \rA, STD_LCL_TBR@ha
+lvd \rT, STD_LCL_TBR@l(\rA)
+.endm
+
+#endif  /* __ASSEMBLER__ */
+
+#endif /* __STD_TIMEBASE_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/trace/Makefile b/src/import/chips/p9/procedures/ppe/pk/trace/Makefile
new file mode 100644
index 00000000..846076a9
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/trace/Makefile
@@ -0,0 +1,50 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/ppe/pk/trace/Makefile $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+# This Makefile is designed to be invoked with the -I argument set to
+# the location of the "pk.mk" for the build
+
+include img_defs.mk
+include pktracefiles.mk
+
+ifeq "$(PK_TIMER_SUPPORT)" "1"
+PKTRACE_OBJECTS += ${PKTRACE-TIMER-C-SOURCES:.c=.o} ${PKTRACE-TIMER-S-SOURCES:.S=.o}
+endif
+
+ifeq "$(PK_THREAD_SUPPORT)" "1"
+PKTRACE_OBJECTS += ${PKTRACE-THREAD-C-SOURCES:.c=.o} ${PKTRACE-THREAD-S-SOURCES:.S=.o}
+endif
+
+OBJS := $(addprefix $(OBJDIR)/, $(PKTRACE_OBJECTS))
+
+all: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d) 
+endif
diff --git a/src/import/chips/p9/procedures/ppe/pk/trace/pk_trace.h b/src/import/chips/p9/procedures/ppe/pk/trace/pk_trace.h
new file mode 100644
index 00000000..21d8ceb4
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/trace/pk_trace.h
@@ -0,0 +1,309 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/trace/pk_trace.h $          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __PK_TRACE_H__
+#define __PK_TRACE_H__
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_trace.h
+/// \brief Macros and declarations for the PK Firmware Tracing Facility.
+///
+
+#include <stdint.h>
+
+#define PK_TRACE_VERSION 2
+
+#ifndef PK_TRACE_SZ
+    #define PK_TRACE_SZ 256
+#endif
+
+//Fail compilation if size is not a power of 2
+#if ((PK_TRACE_SZ - 1) & PK_TRACE_SZ)
+    #error "PK_TRACE_SZ is not a power of two!!!"
+#endif
+
+//Fail compilation if size is smaller than 64 bytes
+#if (PK_TRACE_SZ < 64)
+    #error "PK_TRACE_SZ must be at least 64 bytes!!!"
+#endif
+
+//Mask for calculating offsets into the trace circular buffer
+#define PK_TRACE_CB_MASK (PK_TRACE_SZ - 1)
+
+#define STRINGIFY_HELPER(x) #x
+#define STRINGIFY(x) STRINGIFY_HELPER(x)
+
+#define PPE_IMG_STRING STRINGIFY(IMAGE_NAME)
+
+#ifdef PK_TRACE_HASH_PREFIX
+    #if (PK_TRACE_HASH_PREFIX > 0xffff)
+        #error PK_TRACE_HASH_PREFIX must be defined as a 16 bit constant value
+    #endif
+#endif //PK_TRACE_HASH_PREFIX
+
+//This provides a 128ns tick (assuming a 32ns clock period)
+//and 4 different format values
+#define PK_TRACE_TS_BITS 30
+
+#define PK_TRACE_FORMAT_BITS (32 - PK_TRACE_TS_BITS)
+
+#define PK_TRACE_TS_MASK (0xfffffffful << PK_TRACE_FORMAT_BITS)
+#define PK_TRACE_FORMAT_MASK (~PK_TRACE_TS_MASK)
+
+#define PK_GET_TRACE_FORMAT(w32) (PK_TRACE_FORMAT_MASK & w32)
+#define PK_GET_TRACE_TIME(w32) (PK_TRACE_TS_MASK & w32)
+
+//Set the trace timer period to be the maximum
+//32 bit time minus 2 seconds (assuming a 32ns tick)
+//This allows for up to 1 second of interrupt latency +
+//1 second for PK_TRACE_MTBT while only requiring a trace
+//every 135 seconds in order to maintain the 64bit timebase.
+#define PK_TRACE_TIMER_PERIOD (0xfffffffful - 62500000)
+
+//The Maximum Time Between Traces. In order to reduce the time that interrupts
+//are disabled for tracing, reading of the time stamp is not done atomically
+//with alocating an entry in the circular buffer.  This means that the
+//timestamps might not appear in order in the trace buffer. This is a
+//problem because our calculation of the 64 bit timebase uses the unsigned
+//difference of the current 32bit timestamp and the previous one and if they
+//are out of order it will result in a very large difference.  To solve this
+//problem, any time that the parser code sees a very large difference (larger
+//than PK_TRACE_MTBT) it will treat it as a negative number.
+#define PK_TRACE_MTBT (0xfffffffful - 31250000)
+
+#define PK_TRACE_MAX_PARMS  4
+
+//This is the maximum number of bytes allowed to be traced in a binary trace
+//entry.
+//The trace version needs to change if this changes.
+#define PK_TRACE_MAX_BINARY 256
+
+//clip the largest binary trace according to the trace buffer size.
+//(The trace version does not need to change if this changes as long
+// as it remains less than PK_TRACE_MAX_BINARY)
+#if (PK_TRACE_SZ <= 256)
+    #define PK_TRACE_CLIPPED_BINARY_SZ PK_TRACE_SZ / 2
+#else
+    #define PK_TRACE_CLIPPED_BINARY_SZ PK_TRACE_MAX_BINARY
+#endif
+
+//Trace formats that are supported
+typedef enum
+{
+    PK_TRACE_FORMAT_EMPTY,
+    PK_TRACE_FORMAT_TINY,
+    PK_TRACE_FORMAT_BIG,
+    PK_TRACE_FORMAT_BINARY,
+} PkTraceFormat; //pk_trace_format_t;
+
+//This combines the timestamp and the format bits into a
+//single 32 bit word.
+typedef union
+{
+    struct
+    {
+    uint32_t    timestamp   :
+        PK_TRACE_TS_BITS;
+    uint32_t    format      :
+        PK_TRACE_FORMAT_BITS;
+    };
+    uint32_t word32;
+} PkTraceTime; //pk_trace_time_t;
+
+//PK trace uses a 16 bit string format hash value
+typedef uint16_t PkTraceHash; //pk_trace_hash_t;
+
+//The constant 16 bit hash value is combined with a
+//16 bit parameter value when doing a tiny trace
+typedef union
+{
+    struct
+    {
+        PkTraceHash         string_id;
+        uint16_t            parm;
+    };
+    uint32_t    word32;
+} PkTraceTinyParms; //pk_trace_tiny_parms_t;
+
+//A tiny trace fits within a single 8 byte word. This includes
+//the timestamp, format bits, hash id, and a 16 bit parameter.
+typedef union
+{
+    struct
+    {
+        PkTraceTinyParms   parms;
+        PkTraceTime        time_format;
+    };
+    uint64_t    word64;
+} PkTraceTiny; //pk_trace_tiny_t;
+
+//Larger traces that require a 32 bit parameter or more than one
+//parameter use the big trace format.  The number of parms and
+//the 'complete' flag are combined with the hash id. 'complete'
+//is set to 0 initially and set to one only after all of the trace
+//data has been written.
+typedef union
+{
+    struct
+    {
+        PkTraceHash         string_id;
+        uint8_t             complete;
+        uint8_t             num_parms;
+    };
+    uint32_t    word32;
+} PkTraceBigParms; //pk_trace_big_parms_t;
+
+typedef union
+{
+    struct
+    {
+        PkTraceBigParms    parms;
+        PkTraceTime        time_format;
+    };
+    uint64_t    word64;
+} PkTraceBig; //pk_trace_big_t;
+
+//Binary traces are handled in a similar fashion to big traces, except
+//that instead of having a number of parameters, we have number of bytes.
+typedef union
+{
+    struct
+    {
+        PkTraceHash         string_id;
+        uint8_t             complete;
+        uint8_t             num_bytes;
+    };
+    uint32_t    word32;
+} PkTraceBinaryParms; //pk_trace_binary_parms_t;
+
+typedef union
+{
+    struct
+    {
+        PkTraceBinaryParms  parms;
+        PkTraceTime         time_format;
+    };
+    uint64_t    word64;
+} PkTraceBinary; //pk_trace_binary_t;
+
+//This is a generic structure that can be used to retrieve data
+//for tiny, big, and binary formatted entries.
+typedef union
+{
+    struct
+    {
+        PkTraceHash         string_id;
+        union
+        {
+            uint16_t        parm16;
+            struct
+            {
+                uint8_t     complete;
+                uint8_t     bytes_or_parms_count;
+            };
+        };
+        PkTraceTime         time_format;
+    };
+    uint64_t    word64;
+} PkTraceGeneric; //pk_trace_generic_t;
+
+//This is a format that might be used in the future for tracing
+//a 64 bit timestamp so that we don't fill up the buffer with periodic
+//timer traces.  It is not currently used.
+#if 0
+typedef union
+{
+    struct
+    {
+        uint32_t            upper32;
+        PkTraceTime         time_format;
+    };
+    uint64_t    word64;
+} PkTraceTime64; //pk_trace_time64_t;
+#endif
+
+//It would probably be more accurate to call this a footer since it
+//actually resides at the highest address of each trace entry. These eight
+//bytes contain information that allow us to walk the trace buffer from the
+//most recent entry to the oldest entry.
+typedef union
+{
+    PkTraceGeneric      generic;
+    PkTraceBinary       binary;
+    PkTraceBig          big;
+    PkTraceTiny         small;
+} PkTraceEntryFooter; //pk_trace_entry_header_t;
+
+
+//This is the data that is updated (in the buffer header) every time we add
+//a new entry to the buffer.
+typedef union
+{
+    struct
+    {
+        uint32_t  tbu32;
+        uint32_t  offset;
+    };
+    uint64_t word64;
+} PkTraceState; //pk_trace_state_t;
+
+#define PK_TRACE_IMG_STR_SZ 16
+
+//Header data for the trace buffer that is used for parsing the data.
+//Note: pk_trace_state_t contains a uint64_t which is required to be
+//placed on an 8-byte boundary according to the EABI Spec.  This also
+//causes cb to start on an 8-byte boundary.
+typedef struct
+{
+    //these values are needed by the parser
+    uint16_t            version;
+    uint16_t            rsvd;
+    char                image_str[PK_TRACE_IMG_STR_SZ];
+    uint16_t            instance_id;
+    uint16_t            partial_trace_hash;
+    uint16_t            hash_prefix;
+    uint16_t            size;
+    uint32_t            max_time_change;
+    uint32_t            hz;
+    uint32_t            pad;
+    uint64_t            time_adj64;
+
+    //updated with each new trace entry
+    PkTraceState        state;
+
+    //circular trace buffer
+    uint8_t             cb[PK_TRACE_SZ];
+} PkTraceBuffer; //pk_trace_buffer_t;
+
+extern PkTraceBuffer g_pk_trace_buf;
+
+#ifdef PK_TRACE_BUFFER_WRAP_MARKER
+    extern uint32_t G_wrap_mask;
+#endif
+
+#endif /* __PK_TRACE_H__ */
diff --git a/src/import/chips/p9/procedures/ppe/pk/trace/pk_trace_big.c b/src/import/chips/p9/procedures/ppe/pk/trace/pk_trace_big.c
new file mode 100644
index 00000000..a76ae7e7
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/trace/pk_trace_big.c
@@ -0,0 +1,128 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/trace/pk_trace_big.c $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_trace_big.c
+/// \brief PK Trace function that supports up to four 32-bit parameters
+///
+/// The pk_trace_big function is only called (via some macro magic) if the
+/// caller passes in a single parameter (not including the format string)
+/// that is larger than 16 bits to the PK_TRACE(...) macro.
+///
+
+#include "pk.h"
+#include "pk_trace.h"
+
+#if (PK_TRACE_SUPPORT && PK_TIMER_SUPPORT)
+void pk_trace_big(uint32_t i_hash_and_count,
+                  uint64_t i_parm1, uint64_t i_parm2)
+{
+    PkTraceBig          footer;
+    PkTraceBig*         footer_ptr;
+    PkTraceState        state;
+    uint64_t*           ptr64;
+    uint64_t            tb64;
+    PkMachineContext    ctx;
+    uint32_t            parm_size;
+    uint32_t            cur_offset;
+    uint32_t            footer_offset;
+
+    //fill in the footer data
+    tb64 = pk_timebase_get();
+    footer.parms.word32 = i_hash_and_count; //this has the parm count and hash
+    state.tbu32 = tb64 >> 32;
+    footer.time_format.word32 = tb64 & 0x00000000ffffffffull;
+    footer.time_format.format = PK_TRACE_FORMAT_BIG;
+
+    //round up to 8 byte boundary
+    if(footer.parms.num_parms <= 2)
+    {
+        parm_size = 8;
+    }
+    else
+    {
+        parm_size = 16;
+    }
+
+    //*****The following operations must be done atomically*****
+    pk_critical_section_enter(&ctx);
+
+    //load in the offset in the cb for the entry we are adding
+    cur_offset = g_pk_trace_buf.state.offset;
+
+    //Find the offset for the footer (at the end of the entry)
+    footer_offset = cur_offset + parm_size;
+
+    //calculate the address of the footer
+    ptr64 = (uint64_t*)&g_pk_trace_buf.cb[footer_offset & PK_TRACE_CB_MASK];
+
+    //calculate the offset for the next entry in the cb
+    state.offset = footer_offset + sizeof(PkTraceBig);
+
+#ifdef PK_TRACE_BUFFER_WRAP_MARKER
+
+    //insert marker to indicate when circular buffer wraps
+    if ((state.offset & PK_TRACE_SZ) ^ G_wrap_mask)
+    {
+        G_wrap_mask = state.offset & PK_TRACE_SZ;
+        asm volatile ("tw 0, 31, 31");
+    }
+
+#endif
+
+    //update the cb state (tbu and offset)
+    g_pk_trace_buf.state.word64 = state.word64;
+
+    //write the data to the circular buffer including the
+    //timesamp, string hash, and 16bit parameter
+    *ptr64 = footer.word64;
+
+    //*******************exit the critical section***************
+    pk_critical_section_exit(&ctx);
+
+
+    //write parm values to the circular buffer
+    footer_ptr = (PkTraceBig*)ptr64;
+    ptr64 = (uint64_t*)&g_pk_trace_buf.cb[cur_offset & PK_TRACE_CB_MASK];
+    *ptr64 = i_parm1;
+
+    if(parm_size > 8)
+    {
+        ptr64 = (uint64_t*)&g_pk_trace_buf.cb[(cur_offset + 8) & PK_TRACE_CB_MASK];
+        *ptr64 = i_parm2;
+    }
+
+    //Mark the trace entry update as being completed
+    footer_ptr->parms.complete = 1;
+
+}
+
+#endif
+
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/trace/pk_trace_binary.c b/src/import/chips/p9/procedures/ppe/pk/trace/pk_trace_binary.c
new file mode 100644
index 00000000..c6680a32
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/trace/pk_trace_binary.c
@@ -0,0 +1,126 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/trace/pk_trace_binary.c $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_trace_binary.c
+/// \brief PK Trace function for dumping memory contents
+///
+/// The pk_trace_binary function is called by the PK_TRACE_BINARY() macro.
+///
+
+
+#include "pk.h"
+#include "pk_trace.h"
+
+#if (PK_TRACE_SUPPORT && PK_TIMER_SUPPORT)
+void pk_trace_binary(uint32_t i_hash_and_size, void* bufp)
+{
+    PkTraceBinary           footer;
+    PkTraceBinary*          footer_ptr;
+    PkTraceState            state;
+    uint64_t*               ptr64;
+    uint64_t                tb64;
+    PkMachineContext        ctx;
+    uint32_t                data_size;
+    uint32_t                cb_offset;
+    uint32_t                footer_offset;
+    uint8_t*                dest;
+    uint8_t*                src;
+    uint32_t                index;
+
+    //fill in the footer data
+    tb64 = pk_timebase_get();
+    footer.parms.word32 = i_hash_and_size; //this has the size and hash
+    state.tbu32 = tb64 >> 32;
+    footer.time_format.word32 = tb64 & 0x00000000ffffffffull;
+    footer.time_format.format = PK_TRACE_FORMAT_BINARY;
+
+    //round up to 8 byte boundary
+    data_size = (footer.parms.num_bytes + 7) & ~0x00000007ul;
+
+    //limit data size
+    if(data_size > PK_TRACE_CLIPPED_BINARY_SZ)
+    {
+        data_size = PK_TRACE_CLIPPED_BINARY_SZ;
+    }
+
+    //*****The following operations must be done atomically*****
+    pk_critical_section_enter(&ctx);
+
+    //load in the offset in the cb for the entry we are adding
+    cb_offset = g_pk_trace_buf.state.offset;
+
+    //Find the offset for the footer (at the end of the entry)
+    footer_offset = cb_offset + data_size;
+
+    //calculate the address of the footer
+    ptr64 = (uint64_t*)&g_pk_trace_buf.cb[footer_offset & PK_TRACE_CB_MASK];
+
+    //calculate the offset for the next entry in the cb
+    state.offset = footer_offset + sizeof(PkTraceBinary);
+
+#ifdef PK_TRACE_BUFFER_WRAP_MARKER
+
+    //insert marker to indicate when circular buffer wraps
+    if ((state.offset & PK_TRACE_SZ) ^ G_wrap_mask)
+    {
+        G_wrap_mask = state.offset & PK_TRACE_SZ;
+        asm volatile ("tw 0, 31, 31");
+    }
+
+#endif
+
+    //update the cb state (tbu and offset)
+    g_pk_trace_buf.state.word64 = state.word64;
+
+    //write the footer data to the circular buffer including the
+    //timesamp, string hash and data size
+    *ptr64 = footer.word64;
+
+    //*******************exit the critical section***************
+    pk_critical_section_exit(&ctx);
+
+    //write data to the circular buffer
+    for(src = bufp, index = 0;
+        index < data_size;
+        index++)
+    {
+        dest = &g_pk_trace_buf.cb[(cb_offset + index) & PK_TRACE_CB_MASK];
+        *dest = *(src++);
+    }
+
+    //Mark the trace entry update as being completed
+    footer_ptr = (PkTraceBinary*)ptr64;
+    footer_ptr->parms.complete = 1;
+
+}
+
+#endif
+
+
diff --git a/src/import/chips/p9/procedures/ppe/pk/trace/pk_trace_core.c b/src/import/chips/p9/procedures/ppe/pk/trace/pk_trace_core.c
new file mode 100644
index 00000000..5cd5051f
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/trace/pk_trace_core.c
@@ -0,0 +1,159 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/procedures/ppe/pk/trace/pk_trace_core.c $     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+//-----------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2014
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//-----------------------------------------------------------------------------
+
+/// \file pk_trace_core.c
+/// \brief PK Trace core data and code.
+///
+/// This file includes the minimal code/data required to do minimal tracing.
+/// This includes the periodic timer initialization and the pk_trace_tiny
+/// function.  The pk_trace_tiny function is called by the PK_TRACE() macro
+/// when there is one or less parameters (not including the format string)
+/// and the parameter size is 16 bits or smaller.
+///
+
+#include "pk.h"
+#include "pk_trace.h"
+
+void pk_trace_timer_callback(void* arg);
+
+#if (PK_TRACE_SUPPORT && PK_TIMER_SUPPORT)
+
+//Static initialization of the trace timer
+PkTimer g_pk_trace_timer =
+{
+    .deque = PK_DEQUE_ELEMENT_INIT(),
+    .timeout = 0,
+    .callback = pk_trace_timer_callback,
+    .arg = 0,
+};
+
+//Static initialization of the pk trace buffer
+PkTraceBuffer g_pk_trace_buf =
+{
+    .version            = PK_TRACE_VERSION,
+    .image_str          = PPE_IMG_STRING,
+    .hash_prefix        = PK_TRACE_HASH_PREFIX,
+    .partial_trace_hash = trace_ppe_hash("PARTIAL TRACE ENTRY. HASH_ID = %d", PK_TRACE_HASH_PREFIX),
+    .size               = PK_TRACE_SZ,
+    .max_time_change    = PK_TRACE_MTBT,
+    .hz                 = 500000000, //default value. Actual value is set in pk_init.c
+    .time_adj64         = 0,
+    .state.word64       = 0,
+    .cb                 = {0}
+};
+
+//Needed for buffer extraction in simics for now
+PkTraceBuffer* g_pk_trace_buf_ptr = &g_pk_trace_buf;
+
+#ifdef PK_TRACE_BUFFER_WRAP_MARKER
+    uint32_t G_wrap_mask = 0;
+#endif
+
+// Creates an 8 byte entry in the trace buffer that includes a timestamp,
+// a format string hash value and a 16 bit parameter.
+//
+// i_parm has the hash value combined with the 16 bit parameter
+void pk_trace_tiny(uint32_t i_parm)
+{
+    PkTraceTiny         footer;
+    PkTraceState        state;
+    uint64_t*           ptr64;
+    uint64_t            tb64;
+    PkMachineContext    ctx;
+
+    //fill in the footer data
+    footer.parms.word32 = i_parm;
+    tb64 = pk_timebase_get();
+    state.tbu32 = tb64 >> 32;
+    footer.time_format.word32 = tb64 & 0x00000000ffffffffull;
+
+    footer.time_format.format = PK_TRACE_FORMAT_TINY;
+
+    //The following operations must be done atomically
+    pk_critical_section_enter(&ctx);
+
+    //load the current byte count and calculate the address for this
+    //entry in the cb
+    ptr64 = (uint64_t*)&g_pk_trace_buf.cb[g_pk_trace_buf.state.offset & PK_TRACE_CB_MASK];
+
+    //calculate the offset for the next entry in the cb
+    state.offset = g_pk_trace_buf.state.offset + sizeof(PkTraceTiny);
+
+#ifdef PK_TRACE_BUFFER_WRAP_MARKER
+
+    //insert marker to indicate when circular buffer wraps
+    if ((state.offset & PK_TRACE_SZ) ^ G_wrap_mask)
+    {
+        G_wrap_mask = state.offset & PK_TRACE_SZ;
+        asm volatile ("tw 0, 31, 31");
+    }
+
+#endif
+
+    //update the cb state (tbu and offset)
+    g_pk_trace_buf.state.word64 = state.word64;
+
+    //write the data to the circular buffer including the
+    //timesamp, string hash, and 16bit parameter
+    *ptr64 = footer.word64;
+
+    //exit the critical section
+    pk_critical_section_exit(&ctx);
+}
+
+
+// This function is called periodically in order to ensure that the max ticks
+// between trace entries is no more than what will fit inside a 32bit value.
+#ifndef PK_TRACE_TIMER_OUTPUT
+    #define PK_TRACE_TIMER_OUTPUT 1
+#endif
+void pk_trace_timer_callback(void* arg)
+{
+#if PK_TRACE_TIMER_OUTPUT
+    // guarantee at least one trace before the lower 32bit timebase flips
+    PK_TRACE("PERIODIC TIMESTAMPING TRACE");
+#endif
+    // restart the timer
+    pk_timer_schedule(&g_pk_trace_timer,
+                      PK_TRACE_TIMER_PERIOD);
+}
+
+// Use this function to synchronize the timebase between multiple PPEs.
+// PPE A can send PPE B it's current timebase and then PPE B can set that
+// as the current timebase for tracing purposes.  It can also be used
+// to set the current time to 0.  This function changes the timebase for
+// all entries that are currently in the trace buffer.  Setting the current
+// timebase to 0 will cause previous traces to have very large timestamps.
+void pk_trace_set_timebase(PkTimebase timebase)
+{
+    g_pk_trace_buf.time_adj64 = timebase - pk_timebase_get();
+}
+
+#endif
diff --git a/src/import/chips/p9/procedures/ppe/pk/trace/pktracefiles.mk b/src/import/chips/p9/procedures/ppe/pk/trace/pktracefiles.mk
new file mode 100644
index 00000000..4e8ffa57
--- /dev/null
+++ b/src/import/chips/p9/procedures/ppe/pk/trace/pktracefiles.mk
@@ -0,0 +1,63 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/ppe/pk/trace/pktracefiles.mk $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file pkppe42files.mk
+#
+#  @brief mk for including ppe42 object files
+#
+#  @page ChangeLogs Change Logs
+#  @section pkppe42files.mk
+#  @verbatim
+#
+#
+# Change Log ******************************************************************
+# Flag     Defect/Feature  User        Date         Description
+# ------   --------------  ----------  ------------ -----------
+#
+# @endverbatim
+#
+##########################################################################
+# Include Files
+##########################################################################
+
+			
+
+##########################################################################
+# Object Files
+##########################################################################
+PKTRACE-C-SOURCES = pk_trace_core.c pk_trace_big.c pk_trace_binary.c
+				   
+PKTRACE-S-SOURCES = 
+
+PKTRACE-TIMER-C-SOURCES = 
+PKTRACE-TIMER-S-SOURCES = 
+
+PKTRACE-THREAD-C-SOURCES += 
+PKTRACE-THREAD-S-SOURCES += 
+
+
+PKTRACE_OBJECTS = $(PKTRACE-C-SOURCES:.c=.o) $(PKTRACE-S-SOURCES:.S=.o)
+
+
+
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
new file mode 100644
index 00000000..724a5c97
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -0,0 +1,184 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!--
+    XML file specifying HWPF attributes.
+    These are example Chip EC Feature attributes that specify chip features
+    based on the EC level of a chip
+-->
+
+<attributes>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Returns true if the core trace arrays are dumpable via SCOM.
+      Nimbus EC 0x20 or greater
+    </description>
+    <chipEcFeature>
+      <chip>
+	<name>ENUM_ATTR_NAME_NIMBUS</name>
+	<ec>
+	  <value>0x20</value>
+	  <test>GREATER_THAN_OR_EQUAL</test>
+	</ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_TEST1</id>
+    <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+      Returns if a chip contains the TEST1 feature. True if either:
+      Centaur EC 10
+      Cumulus EC greater than 30
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x10</value>
+          <test>EQUAL</test>
+        </ec>
+      </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_CUMULUS</name>
+        <ec>
+          <value>0x30</value>
+          <test>GREATER_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_TEST2</id>
+    <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+      Returns if a chip contains the TEST2 feature. True if:
+      Murano EC less than 20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_VITL_CLK_SETUP</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Nimbus DD1 for differentiating present/functional targets. True if:
+      Nimbus EC less than 20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_FSI_GP_SHADOWS_OVERWRITE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      DD1 attribute for assigning flushvalues to root_ctrl and perv_ctrl registers. True if:
+      Nimbus EC less than 20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_N3_FLUSH_MODE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      DD1 update : Flush mode not initiated for N3. True if:
+      Nimbus EC less than 20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_SDISN_SETUP</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Sdis_n set or clear : flushing LCBES condition woraround. True if:
+      Nimbus EC less than 20
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      DD1 only: disable local clock gating VITAL. This is used by the 
+      procedure for p9_sbe_tp_chiplet_init1 and p9_Sbe_chiplet_reset.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+</attributes>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/core_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/core_attributes.xml
new file mode 100644
index 00000000..11c98683
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/attribute_info/core_attributes.xml
@@ -0,0 +1,61 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/attribute_info/core_attributes.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- $Id: proc_pll_ring_attributes.xml,v 1.17 2014/11/13 20:14:02 szhong Exp $ -->
+<!-- proc_pll_ring_attributes.xml -->
+<attributes>
+  <attribute>
+    <id>ATTR_CORE_REPR_RING</id>
+    <targetType>TARGET_TYPE_CORE</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_CORE_TIME_RING</id>
+    <targetType>TARGET_TYPE_CORE</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+   <attribute>
+    <id>ATTR_CORE_GPTR_RING</id>
+    <targetType>TARGET_TYPE_CORE</targetType>
+    <description>
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <writeable/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+</attributes>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
new file mode 100644
index 00000000..c3bd81b8
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
@@ -0,0 +1,1158 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!--nest_attributes.xml-->
+<attributes>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_FREQ_PB_MHZ</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    The frequency of a processor's nest mesh clock, in MHz.
+    This is the same for all chips in the system.
+    Provided by the MRW.
+  </description>
+  <valueType>uint32</valueType>
+  <writeable/>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_FREQ_A_MHZ</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    The frequency of a processor's A link clocks, in MHz.
+    This is the same for all chips in the system.
+    Provided by the MRW.
+  </description>
+  <valueType>uint32</valueType>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_FREQ_X_MHZ</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    The frequency of a processor's X link clocks, in MHz.
+    This is the same for all chips in the system.
+    Provided by the MRW.
+  </description>
+  <valueType>uint32</valueType>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_FREQ_CORE_FLOOR_MHZ</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    The lowest frequency that a core can be set to in MHz.
+    This is the same for all cores in the system.
+    Provided by the MVPD #V and is calculated as the max of the
+    Power Save frequencies.
+  </description>
+  <valueType>uint32</valueType>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_FREQ_CORE_NOMINAL_MHZ</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    The nominal core frequency in MHz.
+    This is the same for all cores in the system.
+    Provided by the #V bucket of module VPD.
+  </description>
+  <valueType>uint32</valueType>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_FREQ_CORE_CEILING_MHZ</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    The maximum core frequency in MHz.
+    This is the same for all cores in the system.
+    Provided by the #V bucket of module VPD and is calculated
+    as the minimum of the turbo frequencies.
+  </description>
+  <valueType>uint32</valueType>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PM_SAFE_FREQUENCY_MHZ</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Frequency (in MHz) to move to if the Power Management function fails.
+    This is the same for all cores in the system.
+    Provided by the MRW.
+  </description>
+  <valueType>uint32</valueType>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_FREQ_PCIE_MHZ</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    The frequency of a processor's PCI-e bus in MHz.
+    This is the same for all PCI-e busses in the system.
+    Provided by the MRW.
+  </description>
+  <valueType>uint32</valueType>
+  <platInit/>
+ </attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_ASYNC_SAFE_MODE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Set to force all fabric asynchronous boundary crossings into safe mode.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    PERFORMANCE_MODE = 0x0,
+    SAFE_MODE = 0x1
+  </enum>
+  <writeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_A_BUS_WIDTH</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Processor SMP A bus width.
+    Provided by the MRW.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    2_BYTE = 0x01,
+    4_BYTE = 0x02
+  </enum>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_X_BUS_WIDTH</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Processor SMP X bus width.
+    Provided by the MRW.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    2_BYTE = 0x01,
+    4_BYTE = 0x02
+  </enum>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_CORE_FLOOR_RATIO</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Processor SMP core floor/nest frequency ratio
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    RATIO_8_8 = 0x0,
+    RATIO_7_8 = 0x1,
+    RATIO_6_8 = 0x2,
+    RATIO_5_8 = 0x3,
+    RATIO_4_8 = 0x4,
+    RATIO_2_8 = 0x5
+  </enum>
+  <writeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_CORE_CEILING_RATIO</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Processor SMP core celing/nest frequency ratio
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    RATIO_8_8 = 0x0,
+    RATIO_7_8 = 0x1,
+    RATIO_6_8 = 0x2,
+    RATIO_5_8 = 0x3,
+    RATIO_4_8 = 0x4,
+    RATIO_2_8 = 0x5
+  </enum>
+  <writeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_PUMP_MODE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Processor SMP Fabric broadcast scope configuration.
+    CHIP_IS_NODE = MODE1 = default
+    CHIP_IS_GROUP = MODE2
+    Provided by the MRW.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    CHIP_IS_NODE = 0x01,
+    CHIP_IS_GROUP = 0x02
+  </enum>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_CCSM_MODE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Processor SMP topology configuration.
+    0 = default = 1 or 2 hop topology (PHYP image spans system)
+    1 = 3 hop topology (PHYP image spans group).
+    Provided by the MRW.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    OFF = 0x0,
+    ON = 0x1
+  </enum>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_OPTICS_CONFIG_MODE</id>
+  <targetType>TARGET_TYPE_OBUS</targetType>
+  <description>
+    Per-link optics configuration
+    0 = default = SMP
+    1 = CAPI 2.0
+    2 = NV 2.0
+    Provided by the MRW.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    SMP = 0x0,
+    CAPI = 0x1,
+    NV = 0x2
+  </enum>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_SMP_OPTICS_MODE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Processor SMP optics mode.
+    0 = default = Optics_is_X_bus
+    1 = Optics_is_A_bus
+    Provided by the MRW.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    OPTICS_IS_X_BUS = 0x0,
+    OPTICS_IS_A_BUS = 0x1
+  </enum>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_OPTICS_CONFIG_MODE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    Per-link optics configuration
+    0 = default = SMP
+    1 = CAPI 2.0
+    2 = NV 2.0
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    SMP = 0x0,
+    CAPI = 0x1,
+    NV = 0x2
+  </enum>
+  <array>4</array>
+  <writeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_CAPI_MODE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Processor CAPI attachement protocol mode.
+    0 = default = no: SMPA CAPI attachement
+    1 = yes: SMPA CAPI attachement
+    Provided by the MRW.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    OFF = 0x0,
+    ON = 0x1
+  </enum>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_ADDR_BAR_MODE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Processor memory map configuration.
+    0 = default = large system address map
+    1 = small system address map
+    Provided by the MRW.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    LARGE_SYSTEM = 0x0,
+    SMALL_SYSTEM = 0x1
+  </enum>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_SYSTEM_ID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    Logical fabric system ID associated with this chip.Provided by the MRW.
+  </description>
+  <valueType>uint32</valueType>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_GROUP_ID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    Logical fabric group ID associated with this chip.
+    Provided by the MRW.
+  </description>
+  <valueType>uint8</valueType>
+  <platInit/>
+  <!-- TODO: Story 155081
+       Not supposed to be writeable, PPE needs to resolve this issue in
+       p9_sbe_attr_setup.C -->
+  <writeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_CHIP_ID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    Logical fabric chip ID associated with this chip.
+    Provided by the MRW.
+  </description>
+  <valueType>uint8</valueType>
+  <platInit/>
+  <!-- TODO: Story 155081
+       Not supposed to be writeable, PPE needs to resolve this issue in
+       p9_sbe_attr_setup.C -->
+  <writeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_SYSTEM_MASTER_CHIP</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    Indicates if the given chip should serve as the fabric system master.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    FALSE = 0x0,
+    TRUE = 0x1
+  </enum>
+  <writeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_GROUP_MASTER_CHIP</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    Indicates if the given chip should serve as the fabric group master.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    FALSE = 0x0,
+    TRUE = 0x1
+  </enum>
+  <writeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    For each fabric X link on this chip, specifies whether or not the chip at the
+    receiving end of the link is present and configured
+  </description>
+  <valueType>uint8</valueType>
+  <array>7</array>
+  <enum>
+    FALSE = 0x0,
+    TRUE = 0x1
+  </enum>
+  <writeable/>
+  <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    For each fabric A link on this chip, specifies whether or not the chip at the
+    receiving end of the link is present and configured
+  </description>
+  <valueType>uint8</valueType>
+  <array>4</array>
+  <enum>
+    FALSE = 0x0,
+    TRUE = 0x1
+  </enum>
+  <writeable/>
+  <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_X_ATTACHED_CHIP_ID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    For each fabric X link on this chip, specifies the fabric ID of the chip at the
+    receiving end of the link.  Should be considered valid only if corresponding
+    ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG index is true.
+  </description>
+  <valueType>uint8</valueType>
+  <array>7</array>
+  <writeable/>
+  <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_X_ATTACHED_LINK_ID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    For each fabric X link on this chip, specifies the link ID of the chip at the
+    receiving end of the link.  Should be considered valid only if corresponding
+    ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG index is true.
+  </description>
+  <valueType>uint8</valueType>
+  <array>7</array>
+  <writeable/>
+  <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_A_ATTACHED_CHIP_ID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    For each fabric A link on this chip, specifies the fabric ID of the chip at the
+    receiving end of the link.  Should be considered valid only if corresponding
+    ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG index is true.
+  </description>
+  <valueType>uint8</valueType>
+  <array>4</array>
+  <writeable/>
+  <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_A_ATTACHED_LINK_ID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    For each fabric A link on this chip, specifies the link ID of the chip at the
+    receiving end of the link.  Should be considered valid only if corresponding
+    ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG index is true.
+  </description>
+  <valueType>uint8</valueType>
+  <array>4</array>
+  <writeable/>
+  <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_X_AGGREGATE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    Indicates if X links on this chip should be configured in aggregate mode.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    OFF = 0x0,
+    ON = 0x1
+  </enum>
+  <writeable/>
+  <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_X_ADDR_DIS</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    Indicates if link should be used to carry data only (in aggregate configurations).
+    Should be considered valid only if corresponding ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG
+    index is true.
+  </description>
+  <valueType>uint8</valueType>
+  <array>7</array>
+  <enum>
+    OFF = 0x0,
+    ON = 0x1
+  </enum>
+  <writeable/>
+  <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_X_LINK_DELAY</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    Average of local/remote end link delay counter values.
+    Used to designate coherent link in aggregate configurations.
+    Should be considered valid only if corresponding ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG
+    index is true.
+  </description>
+  <valueType>uint32</valueType>
+  <array>7</array>
+  <enum>
+    OFF = 0x0,
+    ON = 0x1
+  </enum>
+  <writeable/>
+  <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_A_AGGREGATE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    Indicates if A links on this chip should be configured in aggregate mode.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    OFF = 0x0,
+    ON = 0x1
+  </enum>
+  <writeable/>
+  <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_A_ADDR_DIS</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    Indicates if link should be used to carry data only (in aggregate configurations).
+    Should be considered valid only if corresponding ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG
+    index is true.
+  </description>
+  <valueType>uint8</valueType>
+  <array>4</array>
+  <enum>
+    OFF = 0x0,
+    ON = 0x1
+  </enum>
+  <writeable/>
+  <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_FABRIC_A_LINK_DELAY</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>
+    Average of local/remote end link delay counter values.
+    Used to designate coherent link in aggregate configurations.
+    Should be considered valid only if corresponding ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG
+    index is true.
+  </description>
+  <valueType>uint32</valueType>
+  <array>4</array>
+  <enum>
+    OFF = 0x0,
+    ON = 0x1
+  </enum>
+  <writeable/>
+  <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_EPS_GB_PERCENTAGE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Guardband percentage to apply to baseline epsilon calculations
+    Set by p9_fbc_eff_config.
+  </description>
+  <valueType>int8</valueType>
+  <writeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_EPS_TABLE_TYPE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Processor epsilon table type.
+    Used to calculate the processor nest epsilon register values.
+    Provided by the MRW.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    EPS_TYPE_LE = 0x01,
+    EPS_TYPE_HE = 0x02
+  </enum>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_EPS_READ_CYCLES_T0</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Calculated read tier0 epsilon protection count.
+  </description>
+  <valueType>uint32</valueType>
+  <writeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_EPS_READ_CYCLES_T1</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Calculated read tier1 epsilon protection count.
+  </description>
+  <valueType>uint32</valueType>
+  <writeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_EPS_READ_CYCLES_T2</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Calculated read tier2 epsilon protection count.
+  </description>
+  <valueType>uint32</valueType>
+  <writeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_EPS_WRITE_CYCLES_T1</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Calculated write tier1 epsilon protection count.
+  </description>
+  <valueType>uint32</valueType>
+  <writeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_EPS_WRITE_CYCLES_T2</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Calculated write tier2 epsilon protection count.
+  </description>
+  <valueType>uint32</valueType>
+  <writeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_DMI_REFCLOCK_SWIZZLE</id>
+  <targetType>TARGET_TYPE_MCS</targetType>
+  <description>Define DMI Ref clock/Swizzle for Centaur.
+   Provided by the MRW</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_SYSTEM_IPL_PHASE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Define context for current phase of system IPL.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>HB_IPL = 0x1,HB_RUNTIME = 0x2,CACHE_CONTAINED = 0x4, CHIP_CONTAINED = 0x8</enum>
+  <persistRuntime/>
+  <platInit/>
+  <!-- TODO: Story 155081
+       Not supposed to be writeable, PPE needs to resolve this issue in
+       p9_sbe_attr_setup.C -->
+  <writeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_IS_MPIPL</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Indicates if current IPL is memory-preserving
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    FALSE = 0x0,
+    TRUE = 0x1
+  </enum>
+  <platInit/>
+  <!-- TODO: Story 155081
+       Not supposed to be writeable, PPE needs to resolve this issue in
+       sberegaccess.C -->
+  <writeable/>
+  <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>XSCOM BAR base address offset
+    creator: platform
+    consumer: p9_sbe_scominit
+    firmware notes:
+      Defines 16GB range (size implied) mapped for XSCOM usage
+      Attribute holds offset (relative to chip MMIO origin) to program into
+      chip address range field of BAR -- RA bits 22:29
+      (excludes system/memory select/group/chip fields)
+  </description>
+  <valueType>uint64</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>LPC BAR base address offset
+    creator: platform
+    consumer: p9_sbe_scominit
+    firmware notes:
+      Defines 4GB range (size implied) mapped for LPC usage
+      Attribute holds offset (relative to chip MMIO origin) to program into
+      chip address range field of BAR -- RA bits 22:31
+      (excludes system/memory select/group/chip fields)
+  </description>
+  <valueType>uint64</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_MEM_MIRROR_PLACEMENT_POLICY</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Define placement policy/scheme for non-mirrored/mirrored memory
+               layout
+               NORMAL = non-mirrored start: 0, mirrored start: 1024TB
+               FLIPPED = mirrored start: 0, non-mirrored start: 512TB
+               Set by platform.
+               Used by mss_eff_grouping.
+  </description>
+  <valueType>uint8</valueType>
+  <enum>
+    NORMAL    = 0x0,
+    FLIPPED   = 0x1
+  </enum>
+  <platInit/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_MEM_BASE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The location where the stacking of non-mirrored memory groups
+                of the chip starts.  This address is determined in a fixed
+                manner from the chip's position in the fabric topology (i.e.
+                each chip will consume a fixed portion of the system address
+                map).
+                Set by p9_mss_eff_grouping.
+  </description>
+  <valueType>uint64</valueType>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_MEM_BASES</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The address where each memory group starts in the non-mirrored
+                memory groups stack.  This address is determined by the memory
+                grouping process based on the sizes of the memory groups formed
+                in each processor.
+                Set by p9_mss_eff_grouping.
+  </description>
+  <valueType>uint64</valueType>
+  <array>8</array>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_MEM_SIZES</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The memory size of each non-mirrored memory group in the
+                non-mirrored memory groups stack.  This size is determined by
+                the memory grouping process based on the amount of memory
+                behind the ports that are grouped together.
+                Set by p9_mss_eff_grouping.
+  </description>
+  <valueType>uint64</valueType>
+  <array>8</array>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************* -->
+<attribute>
+  <id>ATTR_PROC_MIRROR_BASE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The location where the stacking of mirrored memory groups
+                of the chip starts.  This address is determined in a fixed
+                manner from the chip's position in the fabric topology (i.e.
+                each chip will consume a fixed portion of the system address
+                map).
+                Set by p9_mss_eff_grouping.
+  </description>
+  <valueType>uint64</valueType>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_MIRROR_BASES</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The address where each memory group starts in the mirrored
+                memory groups stack.  This address is determined by
+                the memory grouping process based on the sizes of the memory
+                groups formed in each processor.
+                Set by p9_mss_eff_grouping.
+  </description>
+  <valueType>uint64</valueType>
+  <array>4</array>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_MIRROR_SIZES</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The memory size of each memory group in the mirrored memory
+                groups stack.  This size is determined by the memory grouping
+                process based on the amount of memory behind the ports that are
+                grouped together.
+                Set by p9_mss_eff_grouping.
+  </description>
+  <valueType>uint64</valueType>
+  <array>4</array>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+    <id>ATTR_MSS_INTERLEAVE_ENABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      Used in the setting of groups.  It is a bit vector.  If the value
+      BITWISE_AND  0x01 = 0x01 then groups of 1 are enabled,
+      if the value BITWISE_AND  0x02 = 0x02, then groups of 2 are possible,
+      if the value BITWISE_AND  0x04 = 0x04, then group of 3 are possible,
+      if the value BITWISE_AND  0x08 = 0x08, then groups of 4 are possible,
+      if the value BITWISE_AND 0x20 = 0x20, then groups of 6 are possible,
+      if the value BITWISE_AND 0x80 = 0x80, then groups of 8 are possible.
+      If no groups can formed according to this input, then an error will
+      be thrown.
+      Provided by the MRW
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+    <id>ATTR_MSS_MEM_MC_IN_GROUP</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      An 8 bit vector that would be a designation of which MC (Nimbus MCS or
+      Cumulus MI) are involved in the group.
+      So the bits would represent
+                  Nimbus   Cumulus
+        Bit 0     MCS0     MI0
+        Bit 1     MCS1     MI1
+        .....
+        Bit 7     MCS7     MI7
+      Set by p9_mss_eff_grouping
+    </description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array>8</array>
+    <persistRuntime/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+    <id>ATTR_MSS_MCS_GROUP_32</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+       creator:- mss_eff_grouping
+       consumer:- mss_setup_bars
+       Data Structure from eff grouping to setup bars to help determine
+       different groups
+       Non-Mirroring array[0-7]  [0.17]:  0-- Port size; 1-- No of ports in group; 2-- Total group size of non-mirroring;
+                                          3-- Base address; 4-11-- PortID number in group;
+                                         12-- Alt Memory valid(0); 13-- Alt Memory valid (1);
+                                         14-- Alt Group size (0); 15-- Alt Group size(1);
+                                         16-- Alt Base address (0); 17-- Alt Base address (1);
+
+                                         13-- Alternate Group Size; 14-- Alternate Base address
+       Mirroring     array[8-15] [0:17]:  0-- Port size; 1-- No of ports in group; 2-- Total group size of mirroring;
+                                          3-- Base address; 4-11-- PortID number;
+                                         12-- Alt Memory valid(0); 13-- Alt Memory valid (1);
+                                         14-- Alt Group size (0); 15-- Alt Group size(1);
+                                         16-- Alt Base address (0); 17-- Alt Base address (1);
+       Measured in GB
+     </description>
+    <valueType>uint32</valueType>
+    <array>16,18</array>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+    <id>ATTR_MSS_MEM_IPL_COMPLETE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+       Creator:- mss_setup_bars
+       A numerical number indicating if the memory procedures are complete.
+       written by mss_setup_bars when the bars are now functional in the
+       processor.
+    </description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+    <initToZero/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+    <id>ATTR_MRW_HW_MIRRORING_ENABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+       TRUE : HW mirroring is enabled.
+       FALSE : HW mirroring is disabled.
+       Provided by the MRW.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <enum>FALSE = 0, TRUE = 1</enum>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_NHTM_BAR_BASE_ADDR</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The base address where the NHTM traces start.  They are
+                calculated based on the NHTM trace size requested by user.
+                This address in memory will be the location where NHTM0/1
+                traces are output.
+                Set by p9_mss_eff_grouping.
+                Used by p9_setup_bars and p9_htm_setup.
+  </description>
+  <valueType>uint64</valueType>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************* -->
+<attribute>
+  <id>ATTR_PROC_NHTM_BAR_SIZE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The amount of memory a user can reserve to store NHTM traces.
+                This amount will be used to store both NHTM0 and NHTM1 traces.
+                Used by p9_mss_eff_grouping.
+  </description>
+  <valueType>uint64</valueType>
+  <enum>
+    256_GB = 0x0000004000000000,
+    128_GB = 0x0000002000000000,
+     64_GB = 0x0000001000000000,
+     32_GB = 0x0000000800000000,
+     16_GB = 0x0000000400000000,
+      8_GB = 0x0000000200000000,
+      4_GB = 0x0000000100000000,
+      2_GB = 0x0000000080000000,
+      1_GB = 0x0000000040000000,
+    512_MB = 0x0000000020000000,
+    256_MB = 0x0000000010000000,
+    128_MB = 0x0000000008000000,
+     64_MB = 0x0000000004000000,
+     32_MB = 0x0000000002000000,
+     16_MB = 0x0000000001000000,
+      ZERO = 0x0000000000000000
+  </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_CHTM_BAR_BASE_ADDR</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The base addresses where the CHTM traces start.  They are
+                calculated based on the CHTM trace sizes requested by users.
+                There are 24 different CHTM regions, thus 24 different sizes.
+                Each region is to store HTM trace for a core.
+                Set by p9_mss_eff_grouping.
+                Used by p9_setup_bars.
+  </description>
+  <valueType>uint64</valueType>
+  <array>24</array>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************* -->
+<attribute>
+  <id>ATTR_PROC_CHTM_BAR_SIZES</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The amount of memory a user can reserve to store CHTM traces.
+                There are 24 cores, thus 24 different sizes.
+                Used by p9_mss_eff_grouping.
+  </description>
+  <valueType>uint64</valueType>
+  <enum>
+    256_GB = 0x0000004000000000,
+    128_GB = 0x0000002000000000,
+     64_GB = 0x0000001000000000,
+     32_GB = 0x0000000800000000,
+     16_GB = 0x0000000400000000,
+      8_GB = 0x0000000200000000,
+      4_GB = 0x0000000100000000,
+      2_GB = 0x0000000080000000,
+      1_GB = 0x0000000040000000,
+    512_MB = 0x0000000020000000,
+    256_MB = 0x0000000010000000,
+    128_MB = 0x0000000008000000,
+     64_MB = 0x0000000004000000,
+     32_MB = 0x0000000002000000,
+     16_MB = 0x0000000001000000,
+      ZERO = 0x0000000000000000
+  </enum>
+  <array>24</array>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_OCC_SANDBOX_BASE_ADDR</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The base address where the OCC sandbox starts.  It is
+                calculated based on the OCC sandbox size requested by users.
+                Set by p9_mss_eff_grouping.
+  </description>
+  <valueType>uint64</valueType>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************* -->
+<attribute>
+  <id>ATTR_PROC_OCC_SANDBOX_SIZE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The amount of memory a user can reserve to store OCC sandbox
+                functions.
+                Used by p9_mss_eff_grouping.
+  </description>
+  <valueType>uint64</valueType>
+  <enum>
+    256_GB = 0x0000004000000000,
+    128_GB = 0x0000002000000000,
+     64_GB = 0x0000001000000000,
+     32_GB = 0x0000000800000000,
+     16_GB = 0x0000000400000000,
+      8_GB = 0x0000000200000000,
+      4_GB = 0x0000000100000000,
+      2_GB = 0x0000000080000000,
+      1_GB = 0x0000000040000000,
+    512_MB = 0x0000000020000000,
+    256_MB = 0x0000000010000000,
+    128_MB = 0x0000000008000000,
+     64_MB = 0x0000000004000000,
+     32_MB = 0x0000000002000000,
+     16_MB = 0x0000000001000000,
+      ZERO = 0x0000000000000000
+  </enum>
+  <initToZero/>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_MEM_BASES_ACK</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The actual non-mirrored base addresses of the groups formed
+                by the memory grouping process.  These values correspond to
+                the BAR programming and would be acknowleged on the fabric.
+                Set by p9_mss_eff_grouping.
+                Used by p9_setup_bars.
+  </description>
+  <valueType>uint64</valueType>
+  <array>8</array>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_PROC_MEM_SIZES_ACK</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The actual non-mirrored memory sizes of the groups formed
+                by the memory grouping process.  These values correspond to
+                the BAR programming.
+                Set by p9_mss_eff_grouping.
+                Used by p9_setup_bars.
+  </description>
+  <valueType>uint64</valueType>
+  <array>8</array>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************* -->
+<attribute>
+  <id>ATTR_PROC_MIRROR_BASES_ACK</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The actual mirrored base addresses of the groups formed
+                by the memory grouping process.  These values correspond to
+                the BAR programming and would be acknowleged on the fabric.
+                Set by p9_mss_eff_grouping.
+                Used by p9_setup_bars.
+  </description>
+  <valueType>uint64</valueType>
+  <array>4</array>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************* -->
+<attribute>
+  <id>ATTR_PROC_MIRROR_SIZES_ACK</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description> The actual mirrored memory sizes of the groups formed
+                by the memory grouping process.  These values correspond to
+                the BAR programming.
+                Set by p9_mss_eff_grouping.
+                Used by p9_setup_bars.
+  </description>
+  <valueType>uint64</valueType>
+  <array>4</array>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+<!-- ********************************************************************* -->
+
+</attributes>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_cache_contained_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_cache_contained_attributes.xml
new file mode 100644
index 00000000..9caa1a92
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_cache_contained_attributes.xml
@@ -0,0 +1,52 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/attribute_info/p9_cache_contained_attributes.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<attributes>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_RUNN_MODE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>
+    Set to indicate clock-start/instruction execution in cache-contained
+    mode will be managed by runn
+    Provided by: platform (FW platforms init to OFF)
+  </description>
+  <valueType>uint8</valueType>
+  <platInit/>
+  <enum>OFF=0, ON=1</enum>
+</attribute>
+<!-- ********************************************************************** -->
+<attribute>
+  <id>ATTR_RUNN_CYCLE_COUNT</id>
+  <targetType>TARGET_TYPE_EQ</targetType>
+  <description>
+    Number of clock cycles to execute in runn mode
+    Consumed by: p9_runn HWP (Cronus platform only, cache-contained mode)
+    Provided by: platform (FW platforms init to 0)
+  </description>
+  <valueType>uint64</valueType>
+  <platInit/>
+</attribute>
+<!-- ********************************************************************** -->
+</attributes>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
new file mode 100644
index 00000000..4972e342
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -0,0 +1,525 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- p9_sbe_attributes.xml -->
+<!--    This file defines the subset of attributes from the larger pool of  -->
+<!--    defined attributes that will be included in the SBE platform.       -->
+<!--    Additionally, build time initial values can also be optionally      -->
+<!--    defined.                                                            -->
+<entries>
+  <!-- ********************************************************************* -->
+  <entry>
+    <name>ATTR_PIBMEM_REPAIR0</name>
+    <value>0x0000000000000000</value>
+  </entry>
+  <entry>
+    <name>ATTR_PIBMEM_REPAIR1</name>
+    <value>0x0000000000000000</value>
+  </entry>
+  <entry>
+    <name>ATTR_PIBMEM_REPAIR2</name>
+    <value>0x0000000000000000</value>
+  </entry>
+  <entry>
+    <name>ATTR_I2C_BUS_DIV_REF</name>
+    <value>0x0001</value>
+  </entry>
+  <entry>
+    <name>ATTR_FUNCTIONAL_EQ_EC_VALID</name>
+    <value>0x00</value>
+  </entry>
+  <entry>
+    <name>ATTR_EQ_GARD</name>
+    <value>0x01</value>
+  </entry>
+  <entry>
+     <name>ATTR_EC_GARD</name>
+     <value>0x01</value>
+  </entry>
+  <entry>
+    <name>ATTR_I2C_BUS_DIV_REF_VALID</name>
+    <value>0x00</value>
+  </entry>
+  <entry>
+     <name>ATTR_IS_MPIPL</name>
+     <value>0x0</value>
+  </entry>
+  <entry>
+     <name>ATTR_BOOT_FREQUENCY_VALID</name>
+     <value>0x00</value>
+  </entry>
+  <entry>
+     <name>ATTR_NEST_PLL_BUCKET</name>
+     <value>0x05</value>
+  </entry>
+  <entry>
+     <name>ATTR_BOOT_FREQ_MULT</name>
+     <value>0x00B4</value>
+  </entry>
+  <entry>
+     <name>ATTR_HWP_CONTROL_FLAGS_VALID</name>
+     <value>0x00</value>
+  </entry>
+  <entry>
+      <name>ATTR_SYSTEM_IPL_PHASE</name>
+      <value>0x1</value>
+  </entry>
+  <entry>
+      <name>ATTR_RISK_LEVEL</name>
+      <value>0x0</value>
+  </entry>
+  <entry>
+      <name>ATTR_DISABLE_HBBL_VECTORS</name>
+      <value>0x1</value>
+  </entry>
+  <entry>
+      <name>ATTR_CHIP_SELECTION_VALID</name>
+      <value>0x0</value>
+  </entry>
+  <entry>
+      <name>ATTR_CHIP_SELECTION</name>
+      <value>0x1</value>
+  </entry>
+  <entry>
+     <name>ATTR_NODE_POS</name>
+     <value>0x01</value>
+  </entry>
+  <entry>
+     <name>ATTR_CHIP_POS</name>
+     <value>0x01</value>
+  </entry> 
+  <entry>
+    <name>ATTR_SCRATCH_UINT8_1</name>
+    <value>0x8</value>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_UINT8_2</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_UINT32_1</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_UINT32_2</name>
+    <value>0xaffeaffe</value>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_UINT64_1</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_UINT64_2</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_INT8_1</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_INT8_2</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_INT32_1</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_INT32_2</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_INT64_1</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_INT64_2</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_UINT32_ARRAY</name>
+  </entry>
+  <entry>
+    <name>ATTR_SCRATCH_UINT32_PERV_ARRAY</name>
+  </entry>
+   <entry>
+    <name>ATTR_REPR_RING</name>
+    <value>0xcafe</value>
+    <value>0xdead</value>
+  </entry>
+  <entry>
+    <name>ATTR_TIME_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_GPTR_RING</name>
+    <value>0xcafe</value>
+    <value>0xaffe</value>
+  </entry>
+  <entry>
+    <name>ATTR_PLL_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_CORE_REPR_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_CORE_TIME_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_CORE_GPTR_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_L2_REPR_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_L2_TIME_RING</name>
+    <value>0xcafe</value>
+    <value>0xaffe</value>
+  </entry>
+  <entry>
+    <name>ATTR_L2_GPTR_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_L3_REPR_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_L3_TIME_RING</name>
+    <value>0xcafe</value>
+    <value>0xaffe</value>
+  </entry>
+  <entry>
+    <name>ATTR_L3_GPTR_RING</name>
+  </entry>
+  <entry>
+    <name>ATTR_DPLL_RING</name>
+  </entry>
+  <entry>
+      <name>ATTR_CHIP_UNIT_POS</name>
+      <value>0x01</value> <!-- PERV -->
+      <value>0x02</value> <!-- N0 -->
+      <value>0x03</value> <!-- N1 -->
+      <value>0x04</value> <!-- N2 -->
+      <value>0x05</value> <!-- N3 -->
+      <value>0x06</value> <!-- XB -->
+      <value>0x07</value> <!-- MC01 -->
+      <value>0x08</value> <!-- MC23 -->
+      <value>0x09</value> <!-- OB0 -->
+      <value>0x0A</value> <!-- OB1 -->
+      <value>0x0B</value> <!-- OB2 -->
+      <value>0x0C</value> <!-- OB3 -->
+      <value>0x0D</value> <!-- PCI0 -->
+      <value>0x0E</value> <!-- PCI1 -->
+      <value>0x0F</value> <!-- PCI2 -->
+      <value>0x10</value> <!-- EP0 -->
+      <value>0x11</value> <!-- EP1 -->
+      <value>0x12</value> <!-- EP2 -->
+      <value>0x13</value> <!-- EP3 -->
+      <value>0x14</value> <!-- EP4 -->
+      <value>0x15</value> <!-- EP5 -->
+      <value>0x20</value> <!-- EC00 -->
+      <value>0x21</value> <!-- EC01 -->
+      <value>0x22</value> <!-- EC02 -->
+      <value>0x23</value> <!-- EC03 -->
+      <value>0x24</value> <!-- EC04 -->
+      <value>0x25</value> <!-- EC05 -->
+      <value>0x26</value> <!-- EC06 -->
+      <value>0x27</value> <!-- EC07 -->
+      <value>0x28</value> <!-- EC08 -->
+      <value>0x29</value> <!-- EC09 -->
+      <value>0x2A</value> <!-- EC10 -->
+      <value>0x2B</value> <!-- EC11 -->
+      <value>0x2C</value> <!-- EC12 -->
+      <value>0x2D</value> <!-- EC13 -->
+      <value>0x2E</value> <!-- EC14 -->
+      <value>0x2F</value> <!-- EC15 -->
+      <value>0x30</value> <!-- EC16 -->
+      <value>0x31</value> <!-- EC17 -->
+      <value>0x32</value> <!-- EC18 -->
+      <value>0x33</value> <!-- EC19 -->
+      <value>0x34</value> <!-- EC20 -->
+      <value>0x35</value> <!-- EC21 -->
+      <value>0x36</value> <!-- EC22 -->
+      <value>0x37</value> <!-- EC23 -->
+  </entry>
+
+  <entry>
+      <name>ATTR_BACKUP_SEEPROM_SELECT</name>
+      <value>0x0</value>
+  </entry>
+  <entry>
+       <name>ATTR_MC_SYNC_MODE</name>
+       <value>0x01</value>
+  </entry>
+  <entry>
+         <name>ATTR_BOOT_FLAGS</name>
+         <value>0x80000000</value>
+  </entry>
+  <entry>
+         <name>ATTR_BOOT_FREQ</name>
+         <value>0x0</value>
+  </entry>
+  <entry>
+          <name>ATTR_VCS_BOOT_VOLTAGE</name>
+          <value>0x0</value>
+  </entry>
+  <entry>
+           <name>ATTR_VDD_BOOT_VOLTAGE</name>
+           <value>0x0</value>
+  </entry>
+  <entry>
+      <!-- The values here are per pervasive chiplet in the order of the chiplet
+      numbers Bit 3 (in the 16-bit representation) is used to indicate
+      partial good. If this bit is 1, the region is bad, else it is good.
+      Bits 0,1,2 are don't care. For nimbus, pervasive chiplets 10 and 11 are
+      not used (OB1 and OB2), therefore the value for them is 0xFFFF -->
+            <name>ATTR_PG</name>
+            <value>0xE07D</value> <!-- PERV -->
+            <value>0xE03F</value> <!-- N0 -->
+            <value>0xE03F</value> <!-- N1 -->
+            <value>0xE03F</value> <!-- N2 -->
+            <value>0xE01F</value> <!-- N3 -->
+            <value>0xE00D</value> <!-- XB -->
+            <value>0xE0FD</value> <!-- MC01 -->
+            <value>0xE0FD</value> <!-- MC23 -->
+            <value>0xE1FD</value> <!-- OB0 -->
+            <value>0xFFFF</value> <!-- OB1 -->
+            <value>0xFFFF</value> <!-- OB2 -->
+            <value>0xE1FD</value> <!-- OB3 -->
+            <value>0xE1FD</value> <!-- PCI0 -->
+            <value>0xE0FD</value> <!-- PCI1 -->
+            <value>0xE07D</value> <!-- PCI2 -->
+            <value>0xE001</value> <!-- EP0 -->
+            <value>0xE001</value> <!-- EP1 -->
+            <value>0xE001</value> <!-- EP2 -->
+            <value>0xE288</value> <!-- EP3 -->
+            <value>0xE001</value> <!-- EP4 -->
+            <value>0xE001</value> <!-- EP5 -->
+            <value>0xE1FF</value> <!-- EC00 -->
+            <value>0xE1FF</value> <!-- EC01 -->
+            <value>0xE1FF</value> <!-- EC02 -->
+            <value>0xE1FF</value> <!-- EC03 -->
+            <value>0xE1FF</value> <!-- EC04 -->
+            <value>0xE1FF</value> <!-- EC05 -->
+            <value>0xE1FF</value> <!-- EC06 -->
+            <value>0xE1FF</value> <!-- EC07 -->
+            <value>0xE1FF</value> <!-- EC08 -->
+            <value>0xE1FF</value> <!-- EC09 -->
+            <value>0xE1FF</value> <!-- EC10 -->
+            <value>0xE1FF</value> <!-- EC11 -->
+            <value>0xE1FF</value> <!-- EC12 -->
+            <value>0xE1FF</value> <!-- EC13 -->
+            <value>0xE1FF</value> <!-- EC14 -->
+            <value>0xE1FF</value> <!-- EC15 -->
+            <value>0xE1FF</value> <!-- EC16 -->
+            <value>0xE1FF</value> <!-- EC17 -->
+            <value>0xE1FF</value> <!-- EC18 -->
+            <value>0xE1FF</value> <!-- EC19 -->
+            <value>0xE1FF</value> <!-- EC20 -->
+            <value>0xE1FF</value> <!-- EC21 -->
+            <value>0xE1FF</value> <!-- EC22 -->
+            <value>0xE1FF</value> <!-- EC23 -->
+  </entry>
+  <entry>
+           <name>ATTR_ADU_XSCOM_BAR_BASE_ADDR</name>
+           <value>0x000603FC00000000</value>
+  </entry>
+  <entry>
+           <name>ATTR_LPC_BASE_ADDR</name>
+           <value>0x0006030000000000</value>
+  </entry>
+  <entry>
+         <name>ATTR_SUN_ID</name>
+         <value>0x01</value>
+  </entry>
+  <entry>
+         <name>ATTR_PROC_SBE_MASTER_CHIP</name>
+         <value>0x01</value>
+  </entry>
+  <entry>
+          <name>ATTR_PROC_FABRIC_SYSTEM_ID</name>
+          <value>0x00</value>
+  </entry>
+  <entry>
+          <name>ATTR_PROC_FABRIC_GROUP_ID</name>
+          <value>0x00</value>
+  </entry>
+  <entry>
+          <name>ATTR_PROC_FABRIC_CHIP_ID</name>
+          <value>0x00</value>
+  </entry>
+  <entry>
+          <name>ATTR_PROC_FABRIC_ADDR_BAR_MODE</name>
+          <value>0x01</value>
+  </entry>
+  <entry>
+          <name>ATTR_MEM_MIRROR_PLACEMENT_POLICY</name>
+          <value>0x00</value>
+  </entry>
+  <entry>
+          <name>ATTR_SBE_BOOTLOADER_OFFSET</name>
+          <value>0x200000</value>
+  </entry>
+  <entry>
+           <name>ATTR_HOSTBOOT_HRMOR_OFFSET</name>
+           <value>0x8000000</value>
+  </entry>
+  <entry>
+           <name>ATTR_SYS_FORCE_ALL_CORES</name>
+           <value>0x00</value>
+  </entry>
+  <entry>
+           <name>ATTR_MASTER_CORE</name>
+  </entry>
+  <entry>
+           <name>ATTR_MASTER_EX</name>
+  </entry>
+  <entry>
+           <name>ATTR_PNOR_SIZE</name>
+           <value>0x00</value>
+  </entry>
+  <entry>
+           <name>ATTR_PNOR_BOOT_SIDE</name>
+           <value>0x00</value>
+  </entry>
+  <entry>
+           <name>ATTR_SBE_BOOT_SIDE</name>
+           <value>0x00</value>
+  </entry>
+  <!-- TODO we need to change this once the absolute address is known -->
+  <entry>
+           <name>ATTR_SBE_HBBL_EXCEPTION_INSTRUCT</name>
+           <value>0x48000000</value>
+  </entry>
+  <entry>
+           <name>ATTR_CLOCK_PLL_MUX</name>
+           <value>0x80010800</value>
+  </entry>
+   <entry>
+           <name>ATTR_CLOCK_PLL_MUX0</name>
+           <value>0x3</value>
+  </entry>
+  <entry>
+  	<name>ATTR_PROC_EPS_READ_CYCLES_T0</name>
+  	<value>0x00000FFF</value>
+  </entry>
+  <entry>
+  	<name>ATTR_PROC_EPS_READ_CYCLES_T1</name>
+  	<value>0x00000FFF</value>
+  </entry>
+  <entry>
+  	<name>ATTR_PROC_EPS_READ_CYCLES_T2</name>
+  	<value>0x00000FFF</value>
+  </entry>
+  <entry>
+  	<name>ATTR_PROC_EPS_WRITE_CYCLES_T1</name>
+  	<value>0x00000FFF</value>
+  </entry>
+  <entry>
+  	<name>ATTR_PROC_EPS_WRITE_CYCLES_T2</name>
+  	<value>0x00000FFF</value>
+  </entry>
+  <entry>
+           <name>ATTR_SECURITY_MODE</name>
+           <value>0x0</value>
+  </entry>
+  <entry>
+           <name>ATTR_SECURITY_ENABLE</name>
+           <value>0x0</value>
+  </entry>
+  <entry>
+           <name>ATTR_PFET_OFF_CONTROLS</name>
+           <value>0x00000000</value>
+  </entry>
+  <entry>
+           <name>ATTR_OBUS_RATIO_VALUE</name>
+           <value>0x0</value>
+  </entry>
+  <entry>
+           <name>ATTR_ECID</name>
+  </entry>
+  <entry>
+           <name>ATTR_RUNN_MODE</name>
+           <value>0x0</value>
+  </entry>
+  <entry>
+           <name>ATTR_SS_FILTER_BYPASS</name>
+           <value>0x1</value>
+  </entry>
+  <entry>
+           <name>ATTR_CP_FILTER_BYPASS</name>
+           <value>0x1</value>
+  </entry>
+  <entry>
+           <name>ATTR_IO_FILTER_BYPASS</name>
+           <value>0x1</value>
+  </entry>
+  <entry>
+           <name>ATTR_VDM_ENABLE</name>
+           <value>0x0</value>
+  </entry>
+  <!-- See chip_attributes.xml for a description of ATTR_EC -->
+  <entry>
+           <name>ATTR_EC</name>
+           <!-- The value needs to be changed as per the EC level  -->
+           <value>0x10</value>
+  </entry>
+  <!-- See chip_attributes.xml for a description of ATTR_NAME -->
+  <entry>
+           <name>ATTR_NAME</name>
+           <!-- NIMBUS -->
+           <value>0x5</value>
+  </entry>
+<!--
+This is an example of how to add a CHIP EC feature attribute to this file
+The virtual tag indicates to the SBE plat to not attach storage in the
+attribute tank
+  <entry>
+           <name>ATTR_CHIP_EC_FEATURE_TEST1</name>
+           <virtual/>
+  </entry>
+-->
+
+<!-- Pervasive EC attributes -->
+  <entry>
+           <name>ATTR_CHIP_EC_FEATURE_FSI_GP_SHADOWS_OVERWRITE</name>
+           <virtual/>
+  </entry>
+  <entry>
+           <name>ATTR_CHIP_EC_FEATURE_N3_FLUSH_MODE</name>
+           <virtual/>
+  </entry>
+  <entry>
+           <name>ATTR_CHIP_EC_FEATURE_VITL_CLK_SETUP</name>
+            <virtual/>
+  </entry>
+  <entry>
+           <name>ATTR_CHIP_EC_FEATURE_SDISN_SETUP</name>
+           <virtual/>
+  </entry>
+  <entry>
+           <name>ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING</name>
+           <virtual/>
+  </entry>
+
+  <entry>
+        <name>ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET</name>
+        <value>0x000003FC00000000</value>
+  </entry>
+
+  <entry>
+        <name>ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET</name>
+        <value>0x000003FB00000000</value>
+  </entry>
+
+
+</entries>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml
new file mode 100644
index 00000000..7330b468
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml
@@ -0,0 +1,89 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: nest_attributes.xml. -->
+<!-- XML file specifying attributes used by HW Procedures. -->
+<!-- Attributes are taken from model nest -->
+<!--nest_attributes.xml-->
+<attributes>
+<attribute>
+  <id>ATTR_SBE_BOOTLOADER_OFFSET</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Defines offset to be applied to SBE bootloader installation
+  this will be added with the base address and hostboot HRMOR offset to get the target
+  base address</description>
+  <valueType>uint64</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <initToZero/>
+</attribute>
+<attribute>
+  <id>ATTR_HOSTBOOT_HRMOR_OFFSET</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Defines offset to be applied to SBE bootloader installation
+  this will be added with the bootloader offset and the base address to get the
+  target base addres</description>
+  <valueType>uint64</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <initToZero/>
+</attribute>
+<attribute>
+  <id>ATTR_PNOR_SIZE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Defines size of PNOR that will be put into the exception vector if written</description>
+  <valueType>uint16</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <initToZero/>
+</attribute>
+<attribute>
+  <id>ATTR_SBE_BOOT_SIDE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Defines sbe boot side that will be put into the exception vector if written</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <initToZero/>
+</attribute>
+<attribute>
+  <id>ATTR_PNOR_BOOT_SIDE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Defines boot side of PNOR that will be put into the exception vector if written</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <initToZero/>
+</attribute>
+<attribute>
+  <id>ATTR_SBE_HBBL_EXCEPTION_INSTRUCT</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Instruction for exception vector that will be put into the exception vector if not 0</description>
+  <valueType>uint32</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <initToZero/>
+</attribute>
+</attributes>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
new file mode 100644
index 00000000..22a063c5
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml
@@ -0,0 +1,683 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: pervasive_attributes.xml. -->
+<!-- XML file specifying attributes used by HW Procedures. Attributes are taken from model pervasive -->
+<!--pervasive_attributes.xml-->
+<attributes>
+
+<attribute>
+  <id>ATTR_CLOCK_PLL_MUX</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>setup clock mux settings</description>
+  <valueType>uint32</valueType>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_CLOCK_PLL_MUX0</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Clock Mux#0 settings</description>
+  <valueType>uint8</valueType>
+  <platInit/> 
+</attribute>
+
+<attribute>
+  <id>ATTR_I2C_BUS_DIV_REF</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Ref clock I2C bus divider consumed by code running out of OTPROM</description>
+  <valueType>uint16</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_FUNCTIONAL_EQ_EC_VALID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicates the validitiy of FW functional EQ/EQ register</description>
+  <valueType>uint8</valueType>
+  <enum>FALSE = 0x0,TRUE = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_EQ_GARD</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Capturing EQ Gard value</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_EC_GARD</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Capturing EC Gard Value</description>
+  <valueType>uint32</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_I2C_BUS_DIV_REF_VALID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicates the validity of ref clock I2C bus divider consumed by
+      code running out of OTPROM</description>
+  <valueType>uint8</valueType>
+  <enum>FALSE = 0x0,TRUE = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_FW_MODE_FLAGS_VALID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicates the validity of FW flags. Ex: ISTEP_MODE,
+      SBE_RUNTIME_MODE, MPIPL_MODE, SP_MODE, SBE_FFDC_ENABLE</description>
+  <valueType>uint8</valueType>
+  <enum>FALSE = 0x0,TRUE = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_ISTEP_MODE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicates istep IPL</description>
+  <valueType>uint8</valueType>
+  <enum>NON_IPL = 0x0,IPL = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_SBE_RUNTIME_MODE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicates that SBE should go directly to runtime functionality</description>
+  <valueType>uint8</valueType>
+  <enum>FALSE = 0x0,TRUE = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_IS_SP_MODE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicates whether we are connected to FSP or not</description>
+  <valueType>uint8</valueType>
+  <enum>FSP_LESS = 0x0,FSP = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_SBE_FFDC_ENABLE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicates whether SBE should collect FFDC</description>
+  <valueType>uint8</valueType>
+  <enum>FALSE = 0x0,TRUE = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_SBE_INTERNAL_FFDC_ENABLE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicates that the SBE should send back internal FFDC on any
+      chipOp failure response</description>
+  <valueType>uint8</valueType>
+  <enum>FALSE = 0x0,TRUE = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_BOOT_FREQUENCY_VALID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicates if BOOT_FREQ_MULT and NEST_PLL_BUCKET
+      are valid</description>
+  <valueType>uint8</valueType>
+  <enum>FALSE = 0x0,TRUE = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NEST_PLL_BUCKET</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Select Nest I2C and pll setting from one of the supported frequencies</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_BOOT_FREQ_MULT</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>EQ boot frequency multiplier</description>
+  <valueType>uint16</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_HWP_CONTROL_FLAGS_VALID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicates if HWP control flags
+      are valid</description>
+  <valueType>uint8</valueType>
+  <enum>FALSE = 0x0,TRUE = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_RISK_LEVEL</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>HWP/Init "risk level" enabled. Used by HB to pass to HB driven
+      HWPs</description>
+  <valueType>uint8</valueType>
+  <enum>FALSE = 0x0,TRUE = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_DISABLE_HBBL_VECTORS</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>BootLoader HWP flag to not place 12K exception vectors.
+  This flag is only applicable when security is disabled.</description>
+  <valueType>uint8</valueType>
+  <enum>FALSE = 0x0,TRUE = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_CHIP_SELECTION_VALID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicates that master/slave, node/chip selection attributes
+  are valid</description>
+  <valueType>uint8</valueType>
+  <enum>FALSE = 0x0,TRUE = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_CHIP_SELECTION</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>master/slave bit</description>
+  <valueType>uint8</valueType>
+  <enum>MASTER = 0x0,SLAVE = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_NODE_POS</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicate the node position in FSP based systems (unused in Spless systems)</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_CHIP_POS</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicate the chip position</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_SCRATCH6_VALID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicate if scratch reg6 bits are valid</description>
+  <valueType>uint8</valueType>
+  <enum>FALSE = 0x0,TRUE = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_SCRATCH7_VALID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicate if scratch reg7 bits are valid</description>
+  <valueType>uint8</valueType>
+  <enum>FALSE = 0x0,TRUE = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_BACKUP_SEEPROM_SELECT</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Set with Primary SEEPROM</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_BOOT_FLAGS</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Switch to using a flag to indicate SEEPROM side SBE</description>
+  <valueType>uint32</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_BOOT_FREQ_MHZ</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>EQ boot frequency</description>
+  <valueType>uint32</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_BRANCH_PIBMEM_ADDR</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_CHIP_REGIONS_TO_ENABLE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint32</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_DEVICE_ID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_ECID</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1
+  Created from running the mss_get_cen_ecid.C
+  Firmware shares some code with the processor, 
+  so the attribute is named so they can point at a target and have common function.</description>
+  <valueType>uint64</valueType>
+  <writeable/>
+  <odmVisable/>
+  <odmChangeable/>
+  <array> 2</array>
+</attribute>
+
+<attribute>
+  <id>ATTR_I2C_BUS_DIV_NEST</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>I2C Bus speed based on nest freq, ref clock</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_LEN_OF_SEEPROM_DATA</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_MB_BIT_RATE_DIVISOR_PLL</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_MB_BIT_RATE_DIVISOR_REFCLK</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_MC_SYNC_MODE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>MC mesh to use Nest mesh or not</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_PG</id>
+  <targetType>TARGET_TYPE_PERV</targetType>
+  <description>
+      Chiplet Partial good info attribute. Provided by Ring scans.
+      This should be a direct copy of the data from the PG keyword of VPD.
+      (Note : the 16-bit vpd data is right-justified into attribute)
+  </description>
+  <valueType>uint32</valueType>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_PROC_PB_BNDY_DMIPLL_DATA</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Ring image for pb_bndy_dmipll ring creator: platform firmware notes:</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Ring image for pb_bndy_dmipll ring for DC cal creator: platform firmware notes:</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_PROC_PERV_BNDY_PLL_DATA</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Ring image for perv_bndy_pll ring containing filter plls and xb_pll,nest_pll creator: platform firmware notes:</description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_PROC_SBE_MASTER_CHIP</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicates if SBE on this chip is serving as hosboot drawer master</description>
+  <valueType>uint8</valueType>
+  <enum>FALSE = 0x0,TRUE = 0x1</enum>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint64</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_SBE_SEEPROM_I2C_PORT</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint64</valueType>
+</attribute>
+
+<attribute>
+  <id>ATTR_START_PIBMEM_ADDR</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_START_SEEPROM_ADDR</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_WAIT_N0</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_WAIT_N1</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_WAIT_N2</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_WAIT_N3</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description></description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_SYS_FORCE_ALL_CORES</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Indicate that p9_sbe_select_ex should force selection to ALL good
+    EX chiplets having good cores even if only a single EX chiplet mode is executed.
+  </description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_MASTER_CORE</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicates the master boot core chiplet selected by p9_sbe_select_ex.
+  </description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_MASTER_EX</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>Indicates the EX targert associated with the master boot core selected
+    by p9_sbe_select_ex.
+  </description>
+  <valueType>uint8</valueType>
+  <persistRuntime/>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_SECURITY_ENABLE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>Holds the state of Security Access Bit (SAB)</description>
+  <valueType>uint8</valueType>
+  <platInit/>
+  <writeable/>
+</attribute> 
+
+<attribute>
+  <id>ATTR_SECURITY_MODE</id>
+  <targetType>TARGET_TYPE_SYSTEM</targetType>
+  <description>If SBE image has ATTR_SECURITY_MODE == 0b1, then leave SAB bit as is
+  Else ATTR_SECURITY_MODE == 0b0, then clear the SAB bit</description>
+  <valueType>uint8</valueType>
+  <platInit/>
+  <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_PFET_OFF_CONTROLS</id>
+  <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+  <description>To disable force pfet off control from fuse status</description>
+  <valueType>uint32</valueType>
+  <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_OBUS_RATIO_VALUE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Holds Obus ratio value</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_PIBMEM_REPAIR0</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Pibmem repair attribute 0</description>
+    <valueType>uint64</valueType>
+    <persistRuntime/>
+    <platInit/>
+    <writeable/>
+</attribute>
+
+ <attribute>
+     <id>ATTR_PIBMEM_REPAIR1</id>
+     <targetType>TARGET_TYPE_SYSTEM</targetType>
+     <description>Pibmem repair attribute 1</description>
+     <valueType>uint64</valueType>
+     <persistRuntime/>
+     <platInit/>
+     <writeable/>
+</attribute>
+
+ <attribute>
+     <id>ATTR_PIBMEM_REPAIR2</id>
+     <targetType>TARGET_TYPE_SYSTEM</targetType>
+     <description>Pibmem repair attribute 2</description>
+     <valueType>uint64</valueType>
+     <persistRuntime/>
+     <platInit/>
+     <writeable/>
+</attribute>
+
+<attribute>
+  <id>ATTR_SENSEADJ_STEP</id>
+  <targetType>TARGET_TYPE_EQ</targetType>
+  <description>IPL for skew adjust and duty cycle adjust</description>
+  <valueType>uint8</valueType> 
+  <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_CP_FILTER_BYPASS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>To skip the locking sequence and check for lock of CP PLL</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SS_FILTER_BYPASS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>To skip the locking sequence and check for lock of SS PLL</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_IO_FILTER_BYPASS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>To skip the locking sequence and check for lock of IO PLL</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
+  <id>ATTR_TARGET_HAS_POWER</id>
+  <targetType>TARGET_TYPE_PERV</targetType>
+  <description>Functional Target has power</description>
+  <initToZero></initToZero>
+  <valueType>uint8</valueType>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_TARGET_HAS_CLOCK</id>
+  <targetType>TARGET_TYPE_PERV</targetType>
+  <description>Functional Target has clock</description>
+  <initToZero></initToZero>
+  <valueType>uint8</valueType>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+<attribute>
+  <id>ATTR_TARGET_IS_SCOMMABLE</id>
+  <targetType>TARGET_TYPE_PERV</targetType>
+  <initToZero></initToZero>
+  <description>Functional Target is scommable</description>
+  <valueType>uint8</valueType>
+  <writeable/>
+  <persistRuntime/>
+</attribute>
+
+</attributes>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
new file mode 100644
index 00000000..164c5ce9
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml
@@ -0,0 +1,1426 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- pm_plat_attributes.xml -->
+<!--                                                                        -->
+<!-- XML file specifying Power Management HWPF attributes.                  -->
+<!-- These attributes are initialized by the platform.                      -->
+<attributes>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_EXTERNAL_VRM_STEPSIZE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <!-- <<<<<<< PROC_CHIP POSSIBLE -->
+    <description>
+      Step size (binary in microvolts) to take upon external VRM voltage
+      transitions. The value set here must take into account where internal
+      VRMs are enabled or not as, when they are enabled, the step size must
+      account for the tracking (eg PFET strength recalculation) for the step.
+
+      Consumer: p9_pstate_parameter_block ->
+                        Pstate Parameter Block (PSPB) for PGPE
+
+      Provided by the Machine Readable Workbook after system characterization.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_EXTERNAL_VRM_STEPDELAY</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <!-- <<<<<<< PROC_CHIP POSSIBLE -->
+    <description>
+      Step delay (binary in microseconds) after a voltage change
+
+      Consumer: p9_pstate_parameter_block ->
+                        Pstate Parameter Block (PSPB) for PGPE
+
+      Provided by the Machine Readable Workbook after system characterization.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_AVSBUS_FREQUENCY</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <!-- <<<<<<< PROC_CHIP POSSIBLE -->
+    <description>
+      AVSBus Clock Frequency (binary in KHz)
+
+      Consumer: p9_ocb_init.C
+
+      Overridden by the Machine Readable Workbook.
+
+      If default of 0 is read, HWP will set AVSBus frequency to 1MHz.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VDD_AVSBUS_BUSNUM</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Defines the AVSBus (0 or 1) which has the core VDD rail VRM
+
+      Producer:  Machine Readable Workbook
+      Consumers: p9_set_evid;
+                 p9_set_voltage (tool);
+                 p9_build_pstate_datablock ->
+                        Pstate Parameter Block (PSPB) for PGPE
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VDN_AVSBUS_BUSNUM</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Defines the AVSBus (0 or 1) which has the chip VDN rail VRM
+
+      Producer:  Machine Readable Workbook
+      Consumers: p9_set_evid;
+                 p9_set_voltage (tool);
+                 p9_build_pstate_datablock ->
+                        Pstate Parameter Block (PSPB) for PGPE
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VCS_AVSBUS_BUSNUM</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Defines the AVSBus (0 or 1) which has the chip VCS rail VRM
+
+      Producer:  Machine Readable Workbook
+      Consumers: p9_set_evid;
+                 p9_set_voltage (tool);
+                 p9_build_pstate_datablock ->
+                        Pstate Parameter Block (PSPB) for PGPE
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VDD_AVSBUS_RAIL</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     Defines the AVSBus rail selector number (0 - 15) for the VDD VRM on the bus
+     defined by ATTR_AVSBUS_VDD_BUSNUM.
+
+      Producer:  Machine Readable Workbook
+      Consumers: p9_set_evid;
+                 p9_set_voltage (tool);
+                 p9_build_pstate_datablock ->
+                        Pstate Parameter Block (PSPB) for PGPE
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VDN_AVSBUS_RAIL</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     Defines the AVSBus rail selector number (0 - 15) for the VDN VRM on the bus
+     defined by ATTR_AVSBUS_VDN_BUSNUM.
+
+      Producer:  Machine Readable Workbook
+      Consumers:
+      p9_set_avsbus_voltage (tool);
+                 p9_build_pstate_datablock ->
+                        Pstate Parameter Block (PSPB) for PGPE
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+ <attribute>
+   <id>ATTR_VCS_AVSBUS_RAIL</id>
+   <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+   <description>
+    Defines the AVSBus rail selector number (0 - 15) for the VCS VRM on the bus
+    defined by ATTR_AVSBUS_VDN_BUSNUM.
+
+     Producer:  Machine Readable Workbook
+     Consumers:
+     p9_set_avsbus_voltage (tool);
+ 	       p9_build_pstate_datablock ->
+ 		      Pstate Parameter Block (PSPB) for PGPE
+   </description>
+   <valueType>uint8</valueType>
+   <platInit/>
+ </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VCS_I2C_BUSNUM</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Defines the I2C bus number (0 - 15) that has the VCS VRM.
+
+      Producer:  Machine Readable Workbook
+      Consumers: p9_set_evid;
+                 p9_set_voltage (tool)
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VCS_I2C_RAIL</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Defines the I2C rail selector number (0 - 15) for the VCS VRM on the
+      bus defined by ATTR_VCS_I2C_BUSNUM.
+
+      Producer:  Machine Readable Workbook
+      Consumers: p9_set_evid;
+                 p9_set_voltage (tool)
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VDD_BOOT_VOLTAGE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Voltage (binary in 1mV units) to apply to the VDD VRM for booting.  Value
+      chosen is system dependent and is a combination of the part's Vital Product
+      Data (VPD) (typically the PowerSave value) and the minimum allowed for
+      correct operation of the fabric bus.
+
+      Producer: p9_setup_evid (first pass)
+
+      Consumer: p9_setup_evid (second pass)
+    </description>
+    <valueType>uint32</valueType>
+    <writeable/>
+  </attribute>
+    <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VDN_BOOT_VOLTAGE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Voltage (binary in 1mV units) to apply to the VDN VRM for booting.  Value
+      chosen is system dependent and is a combination of the part's Vital Product
+      Data (VPD) (typically the PowerSave value) and the minimum allowed for
+      correct operation of the fabric bus.
+
+      Producer: p9_setup_evid (first pass)
+
+      Consumer: p9_setup_evid (second pass)
+    </description>
+    <valueType>uint32</valueType>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VCS_BOOT_VOLTAGE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Voltage (binary in 1mV units) to apply to the VCS VRM for booting.  Value
+      chosen is system dependent and is a combination of the part's Vital Product
+      Data (VPD) (typically the PowerSave value) and the minimum allowed for
+      correct operation of the fabric bus.
+
+      Producer: p9_setup_evid (first pass)
+
+      Consumer: p9_setup_evid (second pass)
+    </description>
+    <valueType>uint32</valueType>
+    <writeable/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_SPIPSS_FREQUENCY</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      SPIPSS Clock Frequency (binary in KHz)
+
+      Valid range: 500KHz to 2500KHz
+
+      Consumer: p8_pss_init
+
+      Overridden by the Machine Readable Workbook.
+
+      If default of 0 is read, HWP will set SPIPSS frequency to 10MHz.
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_APSS_CHIP_SELECT</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Defines which of the PSS chip selects (0 or 1) that the APSS is connected
+
+      Provided by the Machine Readable Workbook.
+      Consumer: p8_pss_init
+    </description>
+    <valueType>uint8</valueType>
+    <enum>NONE = 0xFF, CS0 = 0x00, CS1 = 0x01</enum>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_R_LOADLINE_VDD_UOHM</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Impedance (binary microOhms) of the load line from a processor VDD VRM to the
+      Processor Module pins.  This value is applied to each processor instance.
+
+      Producer: Machine Readable Workbook (per the power subsystem design)
+
+      Consumers: p9_pstate_parameter_block
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_R_DISTLOSS_VDD_UOHM</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Impedance (binary in microOhms) of the VDD distribution loss sense point
+      to the circuit. This value is applied to each processor instance.
+
+      Producer: Machine Readable Workbook (per the power subsystem design)
+
+      Consumers: p9_pstate_parameter_block
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_VRM_VOFFSET_VDD_UV</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Offset voltage (binary in microvolts) to apply to the VDD VRM distribution
+      to the processor module.  This value is applied to each processor instance.
+
+      Note:  no loadline may be present in the system; thus, a value of 0 is
+      legal.
+
+      Producer: Machine Readable Workbook (per the power subsystem design)
+
+      Consumers: p9_pstate_parameter_block
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_R_LOADLINE_VDN_UOHM</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Impedance (binary microOhms) of the load line from a processor VDN VRM to
+      the Processor Module pins.  This value is applied to each processor
+      instance.
+
+      Note:  no loadline may be present in the system; thus, a value of 0 is
+      legal.
+
+      Producer: Machine Readable Workbook (per the power subsystem design)
+
+      Consumers: p9_pstate_parameter_block
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_R_DISTLOSS_VDN_UOHM</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Impedance (binary in microOhms) of the VDN distribution loss sense point
+      to the circuit. This value is applied to each processor instance.
+
+      Producer: Machine Readable Workbook (per the power subsystem design)
+
+      Consumers: p9_pstate_parameter_block
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_VRM_VOFFSET_VDN_UV</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Offset voltage (binary in microvolts) to apply to the VDN VRM distribution
+      to the processor module.  This value is applied to each processor instance.
+
+      Producer: Machine Readable Workbook (per the power subsystem design)
+
+      Consumers: p9_pstate_parameter_block
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_R_LOADLINE_VCS_UOHM</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Impedance (binary microOhms) of the load line from a processor VCS VRM to
+      the Processor Module pins.  This value is applied to each processor
+      instance.
+
+      Note:  no loadline may be present in the system; thus, a value of 0 is
+      legal.
+
+      Producer: Machine Readable Workbook (per the power subsystem design)
+
+      Consumers: p9_pstate_parameter_block
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_R_DISTLOSS_VCS_UOHM</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Impedance (binary in microOhms) of the VCS distribution loss sense point
+      to the circuit. This value is applied to each processor instance.
+
+      Producer:  Machine Readable Workbook (via the power subsystem design per
+      system)
+
+      Consumer: p9_pstate_parameter_block
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_VRM_VOFFSET_VCS_UV</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Offset voltage (binary in microvolts) to apply to the VCS VRM distribution
+      to the processor module.  This value is applied to each processor instance.
+
+      Producer:  Machine Readable Workbook (via the power subsystem design per
+      system)
+
+      Consumer: FSP
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_FREQ_BIAS_ULTRATURBO</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     UltraTurbo Frequency Bias - % of bias (signed twos complement in 0.5
+     percent steps) used in calculating the frequency associated with a Pstate
+     - both Global and Local.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumer: p9_pstate_parameter_block
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_FREQ_BIAS_TURBO</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     Turbo Frequency Bias - % of bias (signed twos complement in 0.5 percent
+     steps) used in calculating the frequency associated with a Pstate - both
+     Global and Local.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumer: p9_pstate_parameter_block
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_FREQ_BIAS_NOMINAL</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     Nominal Frequency Bias - % of bias (signed twos complement in 0.5 percent
+     steps) used in calculating the frequency associated with a Pstate - both
+     Global and Local.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumer: p9_pstate_parameter_block
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_FREQ_BIAS_POWERSAVE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     PowerSave Frequency Bias - % of bias (signed twos complement in 0.5 percent
+     steps) used in calculating the frequency associated with a Pstate - both
+     Global and Local.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumer: p9_pstate_parameter_block
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VOLTAGE_EXT_VDD_BIAS_ULTRATURBO</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     UltraTurbo VDD Voltage Bias - % of bias (signed twos complement in 0.5
+     percent steps) that is applied to the UltraTurbo VPD point used in
+     calculating the Global Pstate values.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumer: p9_pstate_parameter_block
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VOLTAGE_EXT_VDD_BIAS_TURBO</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     Turbo VDD Voltage Bias - % of bias (signed twos complement in 0.5 percent
+     steps) that is applied to the UltraTurbo VPD point used in calculating the
+     Global Pstate values.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumer: p9_pstate_parameter_block
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VOLTAGE_EXT_VDD_BIAS_NOMINAL</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     Nominal VDD Voltage Bias - % of bias (signed twos complement in 0.5 percent
+     steps) that is applied to the UltraTurbo VPD point used in calculating the
+     Global Pstate values.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumer: p9_pstate_parameter_block
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+    <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VOLTAGE_EXT_VDD_BIAS_POWERSAVE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     PowerSave VDD Voltage Bias - % of bias (signed twos complement in 0.5
+     percent steps) that is applied to the UltraTurbo VPD point used in
+     calculating the Global Pstate values.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumer: p9_pstate_parameter_block
+
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+    <initToZero/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VOLTAGE_EXT_VCS_BIAS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     VCS Voltage Bias - % of bias (signed twos complement in 0.5 percent
+     steps) that is applied to the VCS value stored in the UltraTurbo VPD
+     point for setting the VCS rail.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumer: p9_pstate_parameter_block
+
+     Platform default:  0
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VOLTAGE_EXT_VDN_BIAS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     VDN Voltage Bias - % of bias (signed twos complement in 0.5 percent
+     steps) that is applied to the VDN value stored in the VPD for setting the
+     VDN rail.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumer: p9_pstate_parameter_block
+
+     Platform default:  0
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VOLTAGE_INT_VDD_BIAS_ULTRATURBO</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS
+     WELL AS THE IVRM VOLTAGE CALCULATION PROCESS
+     UltraTurbo Internal VDD Voltage Bias - % of bias (signed twos complement in
+     0.5 percent steps) that is applied to the voltage computed (Vout) as part
+     of the Local Pstate.  Note: the Vin Effective that models the Vin to the
+     PFETs (i.e  accounting for system parameter losses) may include biassing
+     based on ATTR_VOLTAGE_VDD_BIAS_ULTRATURBO.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumer: p9_pstate_parameter_block
+
+     Platform default:  0
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+  </attribute>
+    <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VOLTAGE_INT_VDD_BIAS_TURBO</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS
+     WELL AS THE IVRM VOLTAGE CALCULATION PROCESS
+     TURBO Internal VDD Voltage Bias - % of bias (signed twos complement in 0.5
+     percent steps) that is applied to the voltage computed (Vout) as part of
+     the Local Pstate.  Note: the Vin Effective that models the Vin to the PFETs
+     (i.e  accounting for system parameter losses) may include biassing based on
+     ATTR_VOLTAGE_VDD_BIAS_TURBO.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumer: p9_pstate_parameter_block
+
+     Platform default:  0
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VOLTAGE_INT_VDD_BIAS_NOMINAL</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS
+     WELL AS THE IVRM VOLTAGE CALCULATION PROCESS
+     Nominal Internal VDD Voltage Bias - % of bias (signed twos complement in
+     0.5 percent steps) that is applied to the voltage computed (Vout) as part
+     of the Local Pstate.  Note: the Vin Effective that models the Vin to the
+     PFETs (i.e  accounting for system parameter losses) may include biassing
+     based on ATTR_VOLTAGE_VDD_BIAS_NOMINAL.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumer: p9_pstate_parameter_block
+
+     Platform default:  0
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+  </attribute>
+    <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_VOLTAGE_INT_VDD_BIAS_POWERSAVE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+     TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS
+     WELL AS THE IVRM VOLTAGE CALCULATION PROCESS
+     PowerSave Internal VDD Voltage Bias - % of bias (signed twos complement in
+     0.5 percent steps) that is applied to the voltage computed (Vout) as part of
+     the Local Pstate.  Note: the Vin Effective that models the Vin to the PFETs
+     (i.e  accounting for system parameter losses) may include biassing based on
+     ATTR_VOLTAGE_VDD_BIAS_POWERSAVE.
+
+     Producer:  Attribute Overrides by Lab/Mfg Characterization Team
+
+     Consumer: p9_pstate_parameter_block
+
+     Platform default:  0
+    </description>
+    <valueType>int8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_STOP4_DISABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Control CME response to execution of PowerPC STOP instruction
+
+    if OFF, treat STOP4 as STOP4
+    if ON, treat STOP4 as STOP2
+
+    Producer: ???
+
+    Consumer:  p8_hcode_image_build.C
+
+    Platform default:  OFF
+    </description>
+    <valueType>uint8</valueType>
+    <enum>OFF=0, ON=1</enum>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_STOP8_DISABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Control CME response to execution of PowerPC STOP instruction
+
+    if OFF, treat STOP8 as STOP8
+    if ON, treat STOP8 as STOP4
+
+    Producer: ???
+
+    Consumer:  p8_hcode_image_build.C
+
+    Platform default:  OFF
+    </description>
+    <valueType>uint8</valueType>
+    <enum>OFF=0, ON=1</enum>
+    <platInit/>
+  </attribute>
+    <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_STOP11_DISABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Control CME response to execution of PowerPC STOP instruction
+
+    if OFF, treat STOP11 as STOP11
+    if ON, treat STOP11 as STOP8
+
+    Producer: ???
+
+    Consumer:  p8_hcode_image_build.C
+
+    Platform default:  OFF
+    </description>
+    <valueType>uint8</valueType>
+    <enum>OFF=0, ON=1</enum>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_SYSTEM_IVRMS_ENABLED</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>System control to allow (if all other attribute tests yield
+    true values) or categorically disallow IVRM enablement
+
+    Producer: MRWB
+
+    Consumers: p9_build_pstate_datablock ->
+                      Pstate Parameter Block (PSPB) for PGPE/OCC
+                      CME Quad Pstate Region (CQPR) for CM Quad Manager
+
+    Platform default: FALSE
+    </description>
+    <valueType>uint8</valueType>
+    <enum>FALSE=0, TRUE=1</enum>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_SYSTEM_WOF_ENABLED</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>System control to allow Work Load Optimized Frequency (WOF)
+    algorithms to modify frequency based on active core count and other inputs.
+
+    Producer: MRWB
+
+    Consumers: p9_build_pstate_datablock ->
+                      Pstate Parameter Block (PSPB) for PGPE/OCC
+
+    Platform default:   FALSE
+    </description>
+    <valueType>uint8</valueType>
+    <enum>FALSE=0, TRUE=1</enum>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PFET_POWERUP_DELAY_NS</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+    Time (in nanoseconds) between PFET controller steps (7 of them) when turning
+    the PFETS ON
+
+    Producer: MRWB
+
+    Consumers: p9_pm_pfet_init
+
+    Platform default:
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PFET_POWERDOWN_DELAY_NS</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+    Time (in nanoseconds) between PFET controller steps (7 of them) when turning
+    the PFETS OFF
+
+    Producer: MRWB
+
+    Consumers: p9_pm_pfet_init
+
+    Platform default:
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PFET_VDD_VOFF_SEL</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+    Selection of the OFF setting for the core and cache chiplet VDD PFET controllers
+
+    Producer: MRWB
+
+    Consumers: p9_pm_pfet_init
+
+    Platform default:
+    </description>
+    <valueType>uint8</valueType>
+    <enum>
+    NOOFF = 0x00,
+    ALLBUT1TO7OFF = 0x01,
+    ALLBUT2TO7OFF = 0x02,
+    ALLBUT3TO7OFF = 0x03,
+    ALLBUT4TO7OFF = 0x04,
+    ALLBUT5TO7OFF = 0x05,
+    ALLBUT6TO7OFF = 0x06,
+    ALLBUT7OFF = 0x7,
+    ALLOFF = 0x08
+    </enum>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PFET_VCS_VOFF_SEL</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+    Selection of the OFF setting for the core and cache chiplet VCS PFET
+    controllers
+
+    Producer: MRWB
+
+    Consumers: p9_pm_pfet_init
+
+    Platform default:
+    </description>
+    <valueType>uint8</valueType>
+    <enum>
+    NOOFF = 0x00,
+    ALLBUT1TO7OFF = 0x01,
+    ALLBUT2TO7OFF = 0x02,
+    ALLBUT3TO7OFF = 0x03,
+    ALLBUT4TO7OFF = 0x04,
+    ALLBUT5TO7OFF = 0x05,
+    ALLBUT6TO7OFF = 0x06,
+    ALLBUT7OFF = 0x7,
+    ALLOFF = 0x08
+    </enum>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PBAX_GROUPID</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Receive PBAX Groupid. Value that indicates this PBA's PBAX Group affinity.
+      This is matched to pbax_groupid of the PMISC Address phase.
+
+      Provided by the Machine Readable Workbook.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PBAX_CHIPID</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Receive PBAX Chipid. Value that indicates this PBA's PBAX Chipid within
+      the PBAX node.  Is matched to pbax_chipid of the Address phase if
+      pbax_type=unicast.
+
+      Provided by the Machine Readable Workbook.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PBAX_BRDCST_ID_VECTOR</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    Receive PBAX Broadcast Group. Vector that is indexed when decoded PMISC
+    pbax_type=broadcast with the decoded PMISC pbax_chipid value.  If the
+    bit in this vector at the decoded bit location is a 1, then this receive
+    engine will participate in the broadcast operation.
+
+    Provided by the Machine Readable Workbook.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+     <id>ATTR_POUNDV_BUCKET_NUM_OVERRIDE</id>
+    <targetType>TARGET_TYPE_EQ</targetType>
+    <description>
+        1 if override of poundv bucket num is available.
+        0 if override is unavailable.
+    </description>
+    <initToZero/>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_POUNDV_BUCKET_NUM</id>
+      <targetType>TARGET_TYPE_EQ</targetType>
+      <description>
+          Attribute in place to allow override of which POUNDV
+          bucket to use to set power management data.
+          1 = Bucket A
+          2 = Bucket B
+          3 = Bucket C
+          4 = Bucket D
+          5 = Bucket E
+          6 = Bucket F
+      </description>
+      <initToZero/>
+      <valueType>uint8</valueType>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_POUNDV_BUCKET_DATA</id>
+      <targetType>TARGET_TYPE_EQ</targetType>
+      <description>
+      Power Management data for Quad targets. Stored as an array of bytes.
+      The data is read directly from VPD and stored in this attribute without
+      being altered.
+
+      NOTE: you may need to handle correcting endiannessif you are using this
+      attribute.
+      </description>
+      <valueType>uint8</valueType>
+      <initToZero/>
+      <array>61</array>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_DUMP_STOP_INFO_SUPPRESS_ERROR_TRACE</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          if set to 1, FAPI_ERR records are suppressed from being produced by
+          p9_dump_stop_info.
+      </description>
+      <valueType>uint8</valueType>
+      <initToZero/>
+      <platInit/>
+  </attribute>
+   <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_DUMP_STOP_INFO_ENABLE_ERRORLOG</id>
+      <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+      <description>
+          if set to 1, p9_dump_stop_info output will be written to error logs
+      </description>
+      <valueType>uint8</valueType>
+      <initToZero/>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_VDM_ENABLE</id>
+      <targetType>TARGET_TYPE_SYSTEM</targetType>
+      <description>
+      Controls the enablement of Voltage Droop Monitors (VDM) in the system.
+
+      Producer:  Machine Readable Workbook
+
+      Consumers:
+        p9_pstate_parameter_block to set flag for CME QuadManager Hcode
+            reaction
+        p9_hcd_cache procedures to power on VDMs before CME booting
+      </description>
+      <valueType>uint8</valueType>
+      <enum>OFF = 0x00, ON = 0x01</enum>
+      <initToZero/>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_VDM_DROOP_SMALL_OVERRIDE</id>
+      <targetType>TARGET_TYPE_SYSTEM</targetType>
+      <description>
+          Voltage Droop Monitor (VDM) Small Threshold Select Value per VPD point
+          The enum indicates a negative value below the VDM setting that will
+          trigger a small droop event.
+
+          Array of 5 entries:
+            0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable
+
+          If index 4 is non-zero, the other entries are considered valid.
+
+          Producer: MRWB.
+      </description>
+      <valueType>uint8</valueType>
+      <enum>
+          OFF  = 0x00,
+          8mV  = 0x01,
+          16mV = 0x02,
+          24mV = 0x03,
+          32mV = 0x04,
+          40mV = 0x05,
+          48mV = 0x06,
+          56mV = 0x07,
+          64mV = 0x08,
+          72mV = 0x09,
+          80mV = 0x0A,
+          88mV = 0x0B,
+          92mV = 0x0C,
+          96mV = 0x0D
+      </enum>
+      <array>5</array>
+      <initToZero/>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_VDM_DROOP_LARGE_OVERRIDE</id>
+      <targetType>TARGET_TYPE_SYSTEM</targetType>
+      <description>
+      Voltage Droop Monitor (VDM) Large Threshold Select Value per VPD point
+      The enum indicates a negative value below the VDM setting that will
+      trigger a large droop event.
+
+      Array of 5 entries:
+        0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable
+
+      If index 4 is non-zero, the other entries are considered valid.
+
+      Producer: Firmware override
+      </description>
+      <valueType>uint8</valueType>
+      <enum>
+          OFF  = 0x00,
+          8mV  = 0x01,
+          16mV = 0x02,
+          24mV = 0x03,
+          32mV = 0x04,
+          40mV = 0x05,
+          48mV = 0x06,
+          56mV = 0x07,
+          64mV = 0x08,
+          72mV = 0x09,
+          80mV = 0x0A,
+          88mV = 0x0B,
+          92mV = 0x0C,
+          96mV = 0x0D
+      </enum>
+      <array>5</array>
+      <initToZero/>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_VDM_DROOP_EXTREME_OVERRIDE</id>
+      <targetType>TARGET_TYPE_SYSTEM</targetType>
+      <description>
+      Voltage Droop Monitor (VDM) Extreme Threshold Select Value per VPD point.
+      The enum indicates a negative value below the VDM setting that will
+      trigger an extreme droop event.
+
+      Array of 5 entries:
+        0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable
+
+      If index 4 is non-zero, the other entries are considered valid.
+
+      Producer: MRWB.
+      </description>
+      <valueType>uint8</valueType>
+      <enum>
+          OFF  = 0x00,
+          8mV  = 0x01,
+          16mV = 0x02,
+          24mV = 0x03,
+          32mV = 0x04,
+          40mV = 0x05,
+          48mV = 0x06,
+          56mV = 0x07,
+          64mV = 0x08,
+          72mV = 0x09,
+          80mV = 0x0A,
+          88mV = 0x0B,
+          92mV = 0x0C,
+          96mV = 0x0D
+      </enum>
+      <array>5</array>
+      <initToZero/>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_VDM_OVERVOLT_OVERRIDE</id>
+      <targetType>TARGET_TYPE_SYSTEM</targetType>
+      <description>
+      Voltage Droop Monitor (VDM) OverVoltage Threshold Select Value per VPD
+      point. The enum indicates a positive value above the VDM setting that will
+      indicate an overvolt droop condition.
+
+      Array of 5 entries:
+        0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable
+
+      If index 4 is non-zero, the other entries are considered valid.
+
+      Producer: MRWB.
+      </description>
+      <valueType>uint8</valueType>
+      <enum>
+          FORCE = 0x00,
+          8mV   = 0x01,
+          16mV  = 0x02,
+          24mV  = 0x03,
+          32mV  = 0x04,
+          40mV  = 0x05,
+          48mV  = 0x06,
+          56mV  = 0x07,
+          64mV  = 0x08
+      </enum>
+      <array>5</array>
+      <initToZero/>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_VDM_FMAX_OVERRIDE_KHZ</id>
+      <targetType>TARGET_TYPE_SYSTEM</targetType>
+      <description>
+
+          Producer: MRWB.
+      </description>
+      <valueType>uint16</valueType>
+      <array>5</array>
+      <initToZero/>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_VDM_FMIN_OVERRIDE_KHZ</id>
+      <targetType>TARGET_TYPE_SYSTEM</targetType>
+      <description>
+
+
+          Producer: MRWB.
+      </description>
+      <valueType>uint16</valueType>
+      <array>5</array>
+      <initToZero/>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_VDM_VID_COMPARE_OVERRIDE_MV</id>
+      <targetType>TARGET_TYPE_SYSTEM</targetType>
+      <description>
+      Voltage Droop Monitor (VDM) Voltage Compare Voltage to expect when no
+      droop is present (binary in mV)
+
+      Array of 5 entries:
+        0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable
+
+      If index 4 is non-zero, the other entries are considered valid.
+
+      Producer: MRWB.
+      </description>
+      <valueType>uint8</valueType>
+      <array>5</array>
+      <initToZero/>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_DPLL_DYNAMIC_FMAX_ENABLE</id>
+      <description>
+      Allow increased dynamic frequency in response to excess voltage margin
+      Controlled by VDM_OVERVOLT threshold value in VDM Configuration Register.
+
+      Producer: MRWB.
+      </description>
+      <targetType>TARGET_TYPE_SYSTEM</targetType>
+      <valueType>uint8</valueType>
+      <enum>
+          OFF = 0x00,ON = 0x01
+      </enum>
+      <initToZero/>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_DPLL_DYNAMIC_FMIN_ENABLE</id>
+      <description>
+      Allow decreased dynamic frequency in response to loss of voltage margin.
+      Controlled by VDM_DROOP_SMALL threshold value in VDM Configuration
+      Register.
+
+      Producer: MRWB.
+      </description>
+      <targetType>TARGET_TYPE_SYSTEM</targetType>
+      <valueType>uint8</valueType>
+      <enum>
+          OFF = 0x00,ON = 0x01
+      </enum>
+      <initToZero/>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_DPLL_DROOP_PROTECT_ENABLE</id>
+      <description>
+      Enable instantaneous frequency reduction in response to droop events
+      Controlled by VDM_DROOP_SMALL, _LARGE and _XTREME threshold values in VDM
+      Configuration Register. The amount of reduction is controlled by chip
+      initialization values
+
+      Producer: MRWB.
+      </description>
+      <targetType>TARGET_TYPE_SYSTEM</targetType>
+      <valueType>uint8</valueType>
+      <enum>
+          OFF = 0x00,ON = 0x01
+      </enum>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_DPLL_VDM_RESPONSE</id>
+      <targetType>TARGET_TYPE_SYSTEM</targetType>
+      <description>
+      Indicates the response of the DPLL frequency upon VDM events.  This
+      control will only apply if ATTR_DPLL_VDM_JUMP_ENABLE is ON;
+      Hardware WOF =  DROOP_PROTECT_OVERVOLT (slew to Fmax if margin exists)
+
+      Producer: MRWB.
+      </description>
+      <valueType>uint8</valueType>
+      <enum>
+          STATIC_FREQ = 0x00,
+          STATIC_DROOP_PROTECT = 0x01,
+          DROOP_PROTECT_OVERVOLT = 0x02,
+          DYNAMIC_FREQ = 0x04
+      </enum>
+      <initToZero/>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+      <id>ATTR_IVRM_DEADZONE_MV</id>
+      <targetType>TARGET_TYPE_SYSTEM</targetType>
+      <description>
+          Indicates the size of the deadzone where the iVRM cannot regulate
+          (binary in millivolts)
+
+          Producer: MRWB.
+      </description>
+      <valueType>uint8</valueType>
+      <initToZero/>
+      <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_TDP_RDP_CURRENT_FACTOR</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description> TODO RTC 157943 -- Placeholder description
+    Consumers: p9_pstate_parameter_block
+    </description>
+    <valueType>uint32</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_SYSTEM_RESCLK_STEP_DELAY</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+    Minimum delay (in nanoseconds) between clock grid management transition
+    steps
+
+    Producer: MRWB
+
+    Consumers: p9_build_pstate_datablock ->
+                      CME Quad Pstate Region (CQPR) for CM Quad Manager
+
+    Platform default:   0
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_SYSTEM_RESCLK_FREQ_REGIONS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    Frequency discontinuity region points that defines the lower edge of a
+    Resonant Region and where F[i] LT F[i+1] and 0 LE i LE 7.
+    This yields:
+       ATTR_RESCLK_FREQ_REGIONS[0] LE Region 0 LT ATTR_RESCLK_FREQ_REGIONS[1]
+       ATTR_RESCLK_FREQ_REGIONS[1] LE Region 1 LT ATTR_RESCLK_FREQ_REGIONS[2]
+       ATTR_RESCLK_FREQ_REGIONS[2] LE Region 2 LT ATTR_RESCLK_FREQ_REGIONS[3]
+       etc.
+
+    Consumers: p9_pstate_parameter_block
+    </description>
+    <valueType>uint8</valueType>
+    <array>8</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_SYSTEM_RESCLK_FREQ_REGION_INDEX</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    Defines the index into ATTR_RESCLK_VALUE[] to use for the frequency region.
+
+    The frequency associated with the region is defined by
+    ATTR_RESCLK_FREQ_REGIONS[i] and ATTR_RESCLK_FREQ_REGIONS[i+1] for
+    0 LE i LE 7.
+
+    Consumers: p9_pstate_parameter_block
+    </description>
+    <valueType>uint8</valueType>
+    <array>8</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_SYSTEM_RESCLK_VALUE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    Array of Clock strength values that will we written in QACCR by CME Hcode
+
+    Consumers: p9_pstate_parameter_block
+    </description>
+    <valueType>uint16</valueType>
+    <array>64</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_SYSTEM_RESCLK_L3_VALUE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    Array of L3 Clock strength values to be used going between "High and Normal
+    Voltage" and "Low Voltage" mode.   Low Voltage mode is define by
+    ATTR_RESCLK_L3_VOLTAGE_THRESHOLD_MV.
+
+    Entry 0 = "High and Normal Voltage" setting
+    Entry 3 = "High and Normal Voltage" setting
+
+    Entry 1 = transitional setting defined by the clock team
+    Entry 2 = transitional setting defined by the clock team
+
+    Contents of each entry will be written directly into L3 control bits in the
+    QACCR(16:23) a RMW operations.  If the circuits demand a grey code whereby
+    only 1 bit of this field can change at a time, the entries must be deal with
+    such encoding.  The Hcode that these values does not perform that function;
+    it merely steps from 0->3 when going below the voltage defined by
+    ATTR_RESCLK_L3_VOLTAGE_THRESHOLD_MV and then steps 3->0 when going at or
+    above the voltage defined by ATTR_RESCLK_L3_VOLTAGE_THRESHOLD_MV.
+
+    Consumers: p9_pstate_parameter_block
+    </description>
+    <valueType>uint8</valueType>
+    <array>4</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_SYSTEM_RESCLK_L3_VOLTAGE_THRESHOLD_MV</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+    Voltage value (in millivolts) whereby voltage below this value will have
+    the L3 clock strength moved to "Low" mode while values at or above this
+    value will have the L3 clock strength moved to "High" mode.  The L3 clock
+    strength values put in the hardware for this mode transtion are defined by
+    ATTR_RESCLK_L3_VALUE.
+
+    Consumers: p9_pstate_parameter_block
+    </description>
+    <valueType>uint16</valueType>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+</attributes>
diff --git a/src/import/chips/p9/procedures/xml/error_info/hwpErrors.mk b/src/import/chips/p9/procedures/xml/error_info/hwpErrors.mk
new file mode 100644
index 00000000..790cdd44
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/hwpErrors.mk
@@ -0,0 +1,66 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/procedures/xml/error_info/hwpErrors.mk $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file hwpErrors.mk
+#
+#  @brief mk for including library common error files
+#
+##########################################################################
+# Error Files
+##########################################################################
+
+PERV_CURR_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST))))
+
+# This variable name must not change
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_perv_sbe_cmn_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_arrayinit_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_chiplet_init_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_chiplet_pll_setup_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_common_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_fabricinit_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_gear_switcher_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_nest_startclocks_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_npll_setup_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_tp_arrayinit_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_tp_chiplet_init3_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_mcs_setup_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_hcd_cache_dpll_setup_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_common_poweronoff_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_hcd_cache_startclocks_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_hcd_core_startclocks_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_pba_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_load_bootloader_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_thread_control_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_startclock_chiplets_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_select_ex_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_check_master_stop15_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_pm_ocb_indir_access_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_pm_ocb_init_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_block_wakeup_intr_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_ram_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_tp_switch_gears_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_adu_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_npll_initf_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_chiplet_pll_initf_errors.xml
+ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_scominit_errors.xml
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_adu_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_adu_errors.xml
new file mode 100644
index 00000000..7915500c
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_adu_errors.xml
@@ -0,0 +1,72 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_adu_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_ADU_COHERENT_UTILS_INVALID_ARGS</rc>
+    <description>
+      Procedure: p9_adu_coherent_utils
+      ADU access or setup not attempted, ADU access or setup is stopped
+    </description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>ADDRESS</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_ADU_COHERENT_UTILS_RESET_ERR</rc>
+    <description>
+      Procedure: p9_adu_coherent_utils
+      ADU Reset had a problem, the ADU was not actually reset
+    </description>
+    <ffdc>TARGET</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_ADU_FBC_NOT_INITIALIZED_ERR</rc>
+    <description>
+      Procedure: p9_adu_coherent_utils
+      The fabric was not initialized or not running
+    </description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>INITIALIZED</ffdc>
+    <ffdc>RUNNING</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc> RC_P9_ADU_STATUS_REG_ERR</rc>
+    <description>
+      Procedure: p9_adu_coherent_utils
+      The ALTD_STATUS_REGISTER has something high or low that was not expected 
+    </description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>STATUSREG</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
+
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_block_wakeup_intr_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_block_wakeup_intr_errors.xml
new file mode 100644
index 00000000..e3c1b5e1
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_block_wakeup_intr_errors.xml
@@ -0,0 +1,44 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_block_wakeup_intr_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for p9_block_wakeup_intr procedure -->
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_BLOCK_WAKEUP_INTR_OP</rc>
+    <description>Unknown operation passed to p9_block_wakeup_intr
+    </description>
+    <ffdc>OPERATION</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+   <hwpError>
+    <sbeError/>
+    <rc>RC_BLOCK_WAKEUP_INTR_CHECK_FAIL</rc>
+    <description>Test of p9_block_wakeup_intr failed.  Note: this is NOT
+    a production error definition; used by test infrastructure.
+    </description>
+  </hwpError>
+  <!-- ********************************************************************* -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_common_poweronoff_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_common_poweronoff_errors.xml
new file mode 100644
index 00000000..b87937af
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_common_poweronoff_errors.xml
@@ -0,0 +1,139 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_common_poweronoff_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for p9_pfet_init and p9_pfet_lib procedures -->
+<hwpErrors>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_PFETLIB_BAD_DOMAIN</rc>
+    <description>Invalid domain value passed to p9_pfet_control.</description>
+    <ffdc>EX</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_PFETLIB_BAD_SCOM</rc>
+    <description>SCOM request failed.</description>
+    <ffdc>EX</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <ffdc>ADDRESS</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_PFETLIB_BAD_OP</rc>
+    <description>Invalid operation value passed to p9_pfet_control.</description>
+    <ffdc>EX</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <ffdc>OPERATION</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_PFETLIB_RAIL_ON</rc>
+    <description>Error returned turning PFETs on in p9_pfet_control.</description>
+    <ffdc>EX</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <ffdc>OPERATION</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_PFETLIB_RAIL_OFF</rc>
+    <description>Error returned turning PFETs off in p9_pfet_control.</description>
+    <ffdc>EX</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <ffdc>OPERATION</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_PFETLIB_TIMEOUT</rc>
+    <description>
+        PFET sequencer timed out in p9_pfet_control.
+        Bad EX Chiplet
+    </description>
+    <ffdc>ADDRESS</ffdc>
+    <ffdc>PFETCONTROLVALUE</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_PFET_CODE_BAD_MODE</rc>
+    <description>Unknown mode passed to p9_pfet_init</description>
+    <ffdc>EX</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_PFET_GET_ATTR</rc>
+    <description>p9_pfet_init could not get an attribute.</description>   
+    <ffdc>EX</ffdc>
+    <ffdc>DOMAIN</ffdc>
+    <ffdc>OPERATION</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml
new file mode 100644
index 00000000..aeaa5873
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml
@@ -0,0 +1,130 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for p9 dpll_setup procedures -->
+<hwpErrors>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_DPLL_LOCK_TIMEOUT</rc>
+    <description>
+        DPLL is not locking.
+    </description>
+    <ffdc>EQQPPMDPLLSTAT</ffdc>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_DPLLCLKSTART_TIMEOUT</rc>
+    <description>
+        dpll clock start timed out.
+    </description>
+    <ffdc>EQCPLTSTAT</ffdc>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_DPLLCLKSTART_FAILED</rc>
+    <description>
+        dpll clock start failed.
+    </description>
+    <ffdc>EQCLKSTAT</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_ANEPCLKSTART_TIMEOUT</rc>
+    <description>
+        anep clock start timed out.
+    </description>
+    <ffdc>EQCPLTSTAT</ffdc>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
+  </hwpError>
+  <!-- ********************************************************************* -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml
new file mode 100644
index 00000000..ff244a07
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml
@@ -0,0 +1,95 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_hcd_cache_startclocks_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for p9_hcd_cache_startclocks procedures -->
+<hwpErrors>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_CACHECPLTALIGN_TIMEOUT</rc>
+    <description>
+        cache chiplets alignment timed out.
+    </description>
+    <ffdc>EQCPLTSTAT0</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_CACHE_XSTOP</rc>
+    <description>
+        cache checkstops.
+    </description>
+    <ffdc>EQXFIR</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_CACHECLKSYNC_TIMEOUT</rc>
+    <description>
+        L2 EXs clock sync done timed out.
+    </description>
+    <ffdc>EQPPMQACSR</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_CACHECLKSTART_FAILED</rc>
+    <description>
+        cache clock start failed.
+    </description>
+    <ffdc>EQCLKSTAT</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_CACHECLKSTART_TIMEOUT</rc>
+    <description>
+        cache clock start timed out.
+    </description>
+    <ffdc>EQCPLTSTAT</ffdc>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
+  </hwpError>
+  <!-- ********************************************************************* -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml
new file mode 100644
index 00000000..fe5c5833
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml
@@ -0,0 +1,113 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for p9_hcd_cache_startclocks procedures -->
+<hwpErrors>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_CORECPLTALIGN_TIMEOUT</rc>
+    <description>
+        core chiplets alignment timed out.
+    </description>
+    <ffdc>CORECPLTSTAT0</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_QUADCPLTALIGN_FAILED</rc>
+    <description>
+        quad chiplets alignment failed.
+    </description>
+    <ffdc>QUADCPLTSTAT0</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_CORECPLTALIGN_FAILED</rc>
+    <description>
+        core chiplets alignment failed.
+    </description>
+    <ffdc>CORECPLTSTAT0</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_CORE_XSTOP</rc>
+    <description>
+        core checkstops.
+    </description>
+    <ffdc>COREXFIR</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_CORECLKSYNC_TIMEOUT</rc>
+    <description>
+        core clock sync done timed out.
+    </description>
+    <ffdc>COREPPMCACSR</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_CORECLKSTART_FAILED</rc>
+    <description>
+        core clock start failed.
+    </description>
+    <ffdc>CORECLKSTAT</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PMPROC_CORECLKSTART_TIMEOUT</rc>
+    <description>
+        core clock start timed out.
+    </description>
+    <ffdc>CORECPLTSTAT</ffdc>
+    <callout>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </deconfigure>
+    <gard>
+      <childTargets>
+        <parent>PROC_CHIP_IN_ERROR</parent>
+        <childType>TARGET_TYPE_EX_CHIPLET</childType>
+        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
+      </childTargets>
+    </gard>
+  </hwpError>
+  <!-- ********************************************************************* -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pba_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pba_errors.xml
new file mode 100644
index 00000000..d82615d6
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pba_errors.xml
@@ -0,0 +1,78 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_pba_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- TODO add callout, gard, deconfig info wherever applicable --> 
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_PBA_COHERENT_UTILS_INVALID_ARGS</rc>
+    <description>
+      Procedure: p9_pba_coherent_utils
+      PBA access or setup not attempted, PBA access or setup is stopped
+    </description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>ADDRESS</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_PBA_COHERENT_UTILS_RESET_ERR</rc>
+    <description>
+      Procedure: p9_pba_coherent_utils
+      PBA Reset had a problem, the PBA was not actually reset
+    </description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>RDDATA</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_PBA_STATUS_ERR</rc>
+    <description>
+      Procedure: p9_pba_coherent_utils
+      PBA Read Status, Write Status, or Reset Register had a problem, the PBA was still busy
+    </description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>RDBUF2</ffdc>
+    <ffdc>RDBUF3</ffdc>
+    <ffdc>WRBUF0</ffdc>
+    <ffdc>WRBUF1</ffdc>
+    <ffdc>SLVRSTDATA</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_PBA_FBC_NOT_INITIALIZED_ERR</rc>
+    <description>
+      Procedure: p9_pba_coherent_utils
+      The fabric was not initialized or not running
+    </description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>INITIALIZED</ffdc>
+    <ffdc>RUNNING</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
+
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_perv_sbe_cmn_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_perv_sbe_cmn_errors.xml
new file mode 100644
index 00000000..dd8464d3
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_perv_sbe_cmn_errors.xml
@@ -0,0 +1,57 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_perv_sbe_cmn_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_perv_sbe_cmn_errors.xml. -->
+<!-- Halt codes for p9_perv_sbe_cmn -->
+
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_SBE_SCAN0_DONE_POLL_THRESHOLD_ERR</rc>
+    <description>Timeout waiting for scan0 to complete , loop count expired that polls for OPCG_DONE</description>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_SBE_ARRAYINIT_POLL_THRESHOLD_ERR</rc>
+    <description>Polling for OPCG_DONE for arrayInit reached threshold , count expired.</description>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_SRAM_ABIST_DONE_BIT_ERR</rc>
+    <description>SRAM abist done bit is not set</description>
+    <ffdc>READ_ABIST_DONE</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_EDRAM_ABIST_DONE_BIT_ERR</rc>
+    <description>EDRAM abist done bit is not set</description>
+    <ffdc>READ_ABIST_DONE</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_ocb_indir_access_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_ocb_indir_access_errors.xml
new file mode 100644
index 00000000..c7007a72
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_ocb_indir_access_errors.xml
@@ -0,0 +1,47 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_pm_ocb_indir_access_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for p9_pm_ocb_indir_access procedure -->
+<hwpErrors>
+    <!-- ******************************************************************* -->
+    <hwpError>
+    <sbeError/>
+    <rc>RC_PM_OCB_PUT_NO_DATA_ERROR</rc>
+    <description>
+    No data passed for Put operation.
+    </description>
+    </hwpError>
+    <!-- ******************************************************************* -->
+    <hwpError>
+    <sbeError/>
+    <rc>RC_PM_OCB_PUT_DATA_POLL_NOT_FULL_ERROR</rc>
+    <description>
+    Indicates that a timeout occured waiting for a push queue to be non-full
+    before writing data. Is likely due to OCC firmware not pulling entries off
+    of the queue in a timely manner.
+    </description>
+    <ffdc>PUSHQ_STATE</ffdc>
+    </hwpError>
+    <!-- ******************************************************************* -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_ocb_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_ocb_init_errors.xml
new file mode 100644
index 00000000..36ed53f6
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_ocb_init_errors.xml
@@ -0,0 +1,44 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_pm_ocb_init_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for p9_pm_ocb_init procedure -->
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PM_OCBINIT_BAD_MODE</rc>
+    <description>Unknown mode passed to p9_pm_ocb_init.
+    </description>
+    <ffdc>BADMODE</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PM_OCBINIT_BAD_Q_LENGTH_PARM</rc>
+    <description>Bad Queue Length Passed to p9_pm_ocb_init.
+    </description>
+    <ffdc>BADQLENGTH</ffdc>
+  </hwpError>
+  <!-- ********************************************************************* -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_ram_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_ram_errors.xml
new file mode 100644
index 00000000..4d92902c
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_ram_errors.xml
@@ -0,0 +1,141 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_ram_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for p9 ram procedures                                --> 
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_SPR_NAME_MAP_INIT_ERR</rc>
+    <description>
+      SPR name map is not empty while try to initialize
+    </description>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_SPR_NAME_MAP_ACCESS_ERR</rc>
+    <description>
+      Illegal SPR name or read/write mode access
+    </description>
+    <ffdc>REGNAME</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>MEDIUM</priority>
+    </callout>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_RAM_NOT_SETUP_ERR</rc>
+    <description>
+      RAM is not setup as active before doing ram or cleanup
+    </description>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_RAM_THREAD_NOT_STOP_ERR</rc>
+    <description>
+      The thread to perform ramming is not stopped
+    </description>
+    <ffdc>THREAD</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_RAM_THREAD_INACTIVE_ERR</rc>
+    <description>
+      The thread to perform ramming is not active
+    </description>
+    <ffdc>THREAD</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_RAM_STATUS_IN_RECOVERY_ERR</rc>
+    <description>
+      Attempt to perform ramming during recovery
+    </description>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_RAM_STATUS_EXCEPTION_ERR</rc>
+    <description>
+      Exception or interrupt happened during ramming
+    </description>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_RAM_STATUS_POLL_THRESHOLD_ERR</rc>
+    <description>
+      Polling for ram done reached threshold
+    </description>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_RAM_INVALID_REG_TYPE_ACCESS_ERR</rc>
+    <description>
+      Illegal reg type access
+    </description>
+    <ffdc>REGTYPE</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>MEDIUM</priority>
+    </callout>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
+
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_arrayinit_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_arrayinit_errors.xml
new file mode 100644
index 00000000..0e8763ca
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_arrayinit_errors.xml
@@ -0,0 +1,31 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_arrayinit_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_sbe_arrayinit_errors.xml. -->
+<!-- Halt codes for p9_sbe_arrayinit -->
+
+<hwpErrors>
+ 
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml
new file mode 100644
index 00000000..228ddea7
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml
@@ -0,0 +1,71 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_CHECK_MASTER_STOP15_PENDING</rc>
+    <description>
+      Procedure: p9_sbe_check_master_stop15
+      Indicates the targeted core is in a valid pending entering either a STOP
+      11 or STOP1.  This return code would be used by the caller (SBE control
+      loop) to determine whether to continue polling for a completed transition.
+
+       Note: STOP 11 and STOP 15 are equivalent for POWER9.
+    </description>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_CHECK_MASTER_STOP15_INVALID_REQUEST_LEVEL</rc>
+    <description>
+      Procedure: p9_sbe_check_master_stop15
+      Indicates the requested stop level was invalid..
+    </description>
+    <ffdc>REQUESTED_LEVEL</ffdc>
+  </hwpError>
+ <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_CHECK_MASTER_STOP15_INVALID_ACTUAL_LEVEL</rc>
+    <description>
+      Procedure: p9_sbe_check_master_stop15
+      Indicates the actual stop level was invalid..
+    </description>
+    <ffdc>ACTUAL_LEVEL</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_CHECK_MASTER_STOP15_INVALID_STATE</rc>
+    <description>
+      Procedure: p9_sbe_check_master_stop15
+      Indicates the targeted core is no longer pending entering a STOP state
+      but the achieved level is not appropriate.
+    </description>
+    <ffdc>STOP_HISTORY</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_init_errors.xml
new file mode 100644
index 00000000..4d7ca4ec
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_init_errors.xml
@@ -0,0 +1,38 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_init_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_sbe_chiplet_init_errors.xml. -->
+<!-- Halt codes for p9_sbe_chiplet_init -->
+
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_CHECKSTOP_ERR</rc>
+    <description>Checkstop error after scan0</description>
+    <ffdc>READ_CHECKSTOP</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml
new file mode 100755
index 00000000..6521c6e5
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml
@@ -0,0 +1,36 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_initf_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Halt codes for p9_sbe_chiplet_pll_initf -->
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_SBE_CHIPLET_PLL_INITF_INVALID_CHIPLET</rc>
+    <description>Unsupported/unexpected pervasive chiplet instance</description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>UNIT_POS</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_setup_errors.xml
new file mode 100644
index 00000000..de377e1c
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_setup_errors.xml
@@ -0,0 +1,38 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_chiplet_pll_setup_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_sbe_chiplet_pll_setup_errors.xml. -->
+<!-- Halt codes for p9_sbe_chiplet_pll_setup -->
+
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_PLL_LOCK_ERR</rc>
+    <description>PLL Lock Not set</description>
+    <ffdc>PLL_READ</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml
new file mode 100644
index 00000000..6ccb7fff
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml
@@ -0,0 +1,92 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_sbe_common_errors.xml. -->
+<!-- Halt codes for p9_sbe_common -->
+
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_ARY_ERR</rc>
+    <description>ary_thold status not matching the expected value in clock start stop sequence</description>
+    <ffdc>READ_CLK_ARY</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_NSL_ERR</rc>
+    <description>nsl_thold status not matching the expected value in clock start stop sequence</description>
+    <ffdc>READ_CLK_NSL</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_SL_ERR</rc>
+    <description>sl_thold status not matching the expected value in clock start stop sequence</description>
+    <ffdc>READ_CLK_SL</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_CPLT_NOT_ALIGNED_ERR</rc>
+    <description>Chiplet not aligned</description>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_CPLT_OPCG_DONE_NOT_SET_ERR</rc>
+    <description>Chiplet OPCG_DONE not set after clock start/stop command</description>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_NEST_ARY_ERR</rc>
+    <description>ary_thold status not matching the expected value in clock start stop sequence</description>
+    <ffdc>READ_CLK_ARY</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_NEST_NSL_ERR</rc>
+    <description>nsl_thold status not matching the expected value in clock start stop sequence</description>
+    <ffdc>READ_CLK_NSL</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_NEST_SL_ERR</rc>
+    <description>sl_thold status not matching the expected value in clock start stop sequence</description>
+    <ffdc>READ_CLK_SL</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_READ_ALL_CHECKSTOP_ERR</rc>
+    <description>Read and or all Checkstop error</description>
+    <ffdc>READ_ALL_CHECKSTOP</ffdc>
+  </hwpError> 
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_fabricinit_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_fabricinit_errors.xml
new file mode 100755
index 00000000..a4cf028d
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_fabricinit_errors.xml
@@ -0,0 +1,63 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_fabricinit_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Halt codes for p9_sbe_fabricinit -->
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_SBE_FABRICINIT_FBC_STOPPED_ERR</rc>
+    <description>
+      Procedure: p9_sbe_fabricinit
+      Fabric init sequence not attempted, fabric arbitration is stopped.
+    </description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>FBC_RUNNING</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_SBE_FABRICINIT_FAILED_ERR</rc>
+    <description>
+      Procedure: p9_sbe_fabricinit
+      Fabric init failed, or mismatch in expected ADU status.
+    </description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>ADU_STATUS_EXP</ffdc>
+    <ffdc>ADU_STATUS_ACT</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_SBE_FABRICINIT_NO_INIT_ERR</rc>
+    <description>
+      Procedure: p9_sbe_fabricinit
+      ADU operation completed successfully, but fabric was not initialized.
+    </description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>FBC_INITIALIZED</ffdc>
+    <ffdc>FBC_RUNNING</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_gear_switcher_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_gear_switcher_errors.xml
new file mode 100644
index 00000000..a1260b90
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_gear_switcher_errors.xml
@@ -0,0 +1,37 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_gear_switcher_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_sbe_gear_switcher_errors.xml. -->
+<!-- Halt codes for p9_sbe_gear_switcher -->
+
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_BUS_STATUS_BUSY_0</rc>
+    <description>Status busy check</description>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_load_bootloader_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_load_bootloader_errors.xml
new file mode 100755
index 00000000..e3e46eeb
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_load_bootloader_errors.xml
@@ -0,0 +1,67 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_load_bootloader_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Halt codes for p9_sbe_load_bootloader -->
+<!-- TODO Add in the callout, gard, and deconfig info wherever applicable  -->
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_SBE_LOAD_BOOTLOADER_INVALID_TARGET_ADDRESS</rc>
+    <description>
+      Procedure: p9_sbe_load_bootloader
+      Target base address is not cacheline aligned.
+    </description>
+    <ffdc>CHIP_TARGET</ffdc>
+    <ffdc>EX_TARGET</ffdc>
+    <ffdc>TARGET_BASE_ADDRESS</ffdc>
+    <ffdc>HRMOR_OFFSET</ffdc>
+    <ffdc>BOOTLOADER_OFFSET</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_SBE_LOAD_BOOTLOADER_INVALID_PAYLOAD_SIZE</rc>
+    <description>
+      Procedure: p9_sbe_load_bootloader
+      Payload size is invalid.
+    </description>
+    <ffdc>CHIP_TARGET</ffdc>
+    <ffdc>EX_TARGET</ffdc>
+    <ffdc>PAYLOAD_SIZE</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_MASTER_CORE_NOT_FOUND</rc>
+    <description>
+      Procedure: p9_sbe_load_bootloader
+      The master core is not found from the ex master target 
+    </description>
+    <ffdc>CHIP_TARGET</ffdc>
+    <ffdc>EX_TARGET</ffdc>
+    <ffdc>MASTER_CORE</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** --> 
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_mcs_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_mcs_setup_errors.xml
new file mode 100644
index 00000000..3e011755
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_mcs_setup_errors.xml
@@ -0,0 +1,35 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_mcs_setup_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_SBE_MCS_SETUP_NO_MC_FOUND_ERR</rc>
+    <description>There is no functional MC chiplet (MCS/MI) present on the master chip</description>
+    <ffdc>CHIP</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
+
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_nest_startclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_nest_startclocks_errors.xml
new file mode 100644
index 00000000..7b5d51d1
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_nest_startclocks_errors.xml
@@ -0,0 +1,31 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_nest_startclocks_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_sbe_nest_startclocks_errors.xml. -->
+<!-- Halt codes for p9_sbe_nest_startclocks -->
+
+<hwpErrors>
+  
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_initf_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_initf_errors.xml
new file mode 100755
index 00000000..ee2b5059
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_initf_errors.xml
@@ -0,0 +1,36 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_npll_initf_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Halt codes for p9_sbe_npll_initf -->
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_SBE_NPLL_INITF_UNSUPPORTED_BUCKET</rc>
+    <description>Unsupported Nest PLL bucket value</description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>BUCKET_INDEX</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml
new file mode 100644
index 00000000..a45c8f56
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml
@@ -0,0 +1,59 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_npll_setup_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_sbe_npll_setup_errors.xml. -->
+<!-- Halt codes for p9_sbe_npll_setup -->
+
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_SS_PLL_LOCK_ERR</rc>
+    <description>Spectrum pll not locked</description>
+    <ffdc>SS_PLL_READ</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_CP_FILTER_PLL_LOCK_ERR</rc>
+    <description>CP Filter PLL not locked</description>
+    <ffdc>CP_FILTER_PLL_READ</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_NEST_PLL_ERR</rc>
+    <description>Nest PLL not locked</description>
+    <ffdc>NEST_PLL_READ</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_IO_FILTER_PLL_LOCK_ERR</rc>
+    <description>IO Filter PLL not locked</description>
+    <ffdc>IO_FILTER_PLL_READ</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_scominit_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_scominit_errors.xml
new file mode 100644
index 00000000..97226c2d
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_scominit_errors.xml
@@ -0,0 +1,52 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_scominit_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Halt codes for p9_sbe_scominit -->
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_P9_SBE_SCOMINIT_XSCOM_BAR_ATTR_ERR</rc>
+    <description>
+      Procedure: p9_sbe_scominit
+      Invalid XSCOM BAR attribute configuration
+    </description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>XSCOM_BAR</ffdc>
+    <ffdc>XSCOM_BAR_OFFSET</ffdc>
+    <ffdc>BASE_ADDR_MMIO</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <rc>RC_P9_SBE_SCOMINIT_LPC_BAR_ATTR_ERR</rc>
+    <description>
+      Procedure: p9_sbe_scominit
+      Invalid LPC BAR attribute configuration
+    </description>
+    <ffdc>TARGET</ffdc>
+    <ffdc>LPC_BAR</ffdc>
+    <ffdc>LPC_BAR_OFFSET</ffdc>
+    <ffdc>BASE_ADDR_MMIO</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_select_ex_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_select_ex_errors.xml
new file mode 100644
index 00000000..8bff680f
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_select_ex_errors.xml
@@ -0,0 +1,57 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_select_ex_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_sbe_tp_arrayinit_errors.xml. -->
+<!-- Halt codes for p9_sbe_tp_arrayinit -->
+
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_SBE_SELECT_EX_NO_CORES</rc>
+    <description>No good cores were found in the Partial Good attribures</description>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_SBE_SELECT_EX_NO_EQS</rc>
+    <description>No good cache chiplets were found in the Partial Good attribures</description>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_SBE_SELECT_EX_CORE_EQ_CONFIG_ERROR</rc>
+    <description>Did not find the matching EQ for the first core</description>
+    <ffdc>CORE_NUM</ffdc>
+    <ffdc>EQ_NUM</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_SBE_SELECT_EX_NO_CORE_AVAIL_ERROR</rc>
+    <description>No cores are configurable with current partial good and gard settings</description>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_startclock_chiplets_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_startclock_chiplets_errors.xml
new file mode 100644
index 00000000..6a5e2cb5
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_startclock_chiplets_errors.xml
@@ -0,0 +1,31 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_startclock_chiplets_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_sbe_startclock_chiplets_errors.xml. -->
+<!-- Halt codes for p9_sbe_startclock_chiplets -->
+
+<hwpErrors>
+ 
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_arrayinit_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_arrayinit_errors.xml
new file mode 100644
index 00000000..a8e23e1d
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_arrayinit_errors.xml
@@ -0,0 +1,31 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_tp_arrayinit_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_sbe_tp_arrayinit_errors.xml. -->
+<!-- Halt codes for p9_sbe_tp_arrayinit -->
+
+<hwpErrors>
+  
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_chiplet_init3_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_chiplet_init3_errors.xml
new file mode 100644
index 00000000..9249bda2
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_chiplet_init3_errors.xml
@@ -0,0 +1,58 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_tp_chiplet_init3_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_sbe_tp_chiplet_init3_errors.xml. -->
+<!-- Halt codes for p9_sbe_tp_chiplet_init3 -->
+
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_XSTOP_ERR</rc>
+    <description>Checkstop bit set in interrupt type reg</description>
+    <ffdc>READ_XSTOP</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_CALIBRATION_NOT_DONE</rc>
+    <description>Precision Reference Voltage : Calibration not done</description>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_MF_OSC_ERR</rc>
+    <description>MF Oscillator error active</description>
+    <ffdc>READ_OSCERR_HOLD</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_MF_OSC_NOT_TOGGLE</rc>
+    <description>MF Oscillator not toggling</description>
+    <ffdc>READ_SNS1LTH</ffdc>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_switch_gears_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_switch_gears_errors.xml
new file mode 100644
index 00000000..f1f33966
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_tp_switch_gears_errors.xml
@@ -0,0 +1,43 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_tp_switch_gears_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- This is an automatically generated file. -->
+<!-- File: p9_sbe_tp_switch_gears_errors.xml. -->
+<!-- Halt codes for p9_sbe_tp_switch_gears -->
+
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_BUS_STATUS_BUSY0</rc>
+    <description>Status busy check</description>
+  </hwpError>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_MAGIC_NUMBER_NOT_VALID</rc>
+    <description>Magic number not matching</description>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_thread_control_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_thread_control_errors.xml
new file mode 100644
index 00000000..715538a4
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_thread_control_errors.xml
@@ -0,0 +1,147 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_thread_control_errors.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- @brief Error definitions for p9_thread_control procedure               -->
+<hwpErrors>
+
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_THREAD_CONTROL_SRESET_PRE_FAIL</rc>
+    <description>SReset command precondition not met: Not all threads are running.</description>
+    <ffdc>CORE_TARGET</ffdc>
+    <ffdc>THREAD</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_THREAD_CONTROL_SRESET_FAIL</rc>
+    <ffdc>CORE_TARGET</ffdc>
+    <ffdc>THREAD</ffdc>
+    <description>SReset command failed: Not all threads are running after sreset command.</description>
+    <callout>
+      <target>CORE_TARGET</target>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
+    <deconfigure>
+      <target>CORE_TARGET</target>
+    </deconfigure>
+    <gard>
+      <target>CORE_TARGET</target>
+    </gard>
+  </hwpError>
+
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_THREAD_CONTROL_START_PRE_NOMAINT</rc>
+    <description>Start command precondition not met: RAS STAT Maintenance bit is not set.</description>
+    <ffdc>CORE_TARGET</ffdc>
+    <ffdc>THREAD</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_THREAD_CONTROL_START_FAIL</rc>
+    <description>Start command failed: RAS STAT instruction completed bit was not set after start command.</description>
+    <ffdc>CORE_TARGET</ffdc>
+    <ffdc>THREAD</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_THREAD_CONTROL_STOP_PRE_NOTRUNNING</rc>
+    <description>Stop command precondition not met: Not all threads are running.</description>
+    <ffdc>CORE_TARGET</ffdc>
+    <ffdc>THREAD</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_THREAD_CONTROL_STOP_FAIL</rc>
+    <description>Stop command issued to core PC, but RAS STAT maintenance bit is not set.</description>
+    <ffdc>CORE_TARGET</ffdc>
+    <ffdc>THREAD</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_THREAD_CONTROL_STEP_PRE_NOTSTOPPING</rc>
+    <description>Step command precondition not met: Not all threads are stopped.</description>
+    <ffdc>CORE_TARGET</ffdc>
+    <ffdc>THREAD</ffdc>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>HIGH</priority>
+    </callout>
+  </hwpError>
+
+  <!-- ********************************************************************* -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_P9_THREAD_CONTROL_STEP_FAIL</rc>
+    <description>Step command issued to core PC, but RAS STAT run bit is still set.</description>
+    <ffdc>CORE_TARGET</ffdc>
+    <ffdc>THREAD</ffdc>
+    <ffdc>PTC_STEP_COMP_POLL_LIMIT</ffdc>
+    <callout>
+      <target>CORE_TARGET</target>
+      <priority>HIGH</priority>
+    </callout>
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
+  </hwpError>
+
+</hwpErrors>
diff --git a/src/import/chips/p9/sw_simulation/chip.act b/src/import/chips/p9/sw_simulation/chip.act
new file mode 100644
index 00000000..1abe32a4
--- /dev/null
+++ b/src/import/chips/p9/sw_simulation/chip.act
@@ -0,0 +1,283 @@
+# This file will contain all the Chip Actions
+# =============================================================================
+# Simics action for p9_sbe_fabricinit
+# =============================================================================
+CAUSE_EFFECT {
+LABEL=[Fabric Init via ADU]
+WATCH=[REG(0x00090001] #PU_ALTD_CMD_REG
+CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #PU_ALTD_CMD_REG, ALTD_CMD_START_OP_BIT
+EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #PU_ALTD_STATUS_REG, ALTD_STATUS_ADDR_DONE_BIT
+EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[61] #PU_ALTD_STATUS_REG, ALTD_STATUS_CRESP_ACK_DONE
+#EFFECT: TARGET=[REG(0x05011C0A)] OP=[BIT,ON] BIT=[0] #PU_FBC_MODE_REG, PU_FBC_MODE_PB_INITIALIZED_BIT
+}
+
+# =============================================================================
+# Action file not necessary for procedures:
+# p9_sbe_scominit
+# p9_sbe_mcs_setup
+# p9_sbe_instruct_start (default 0's work)
+# =============================================================================
+
+# =============================================================================
+# Actions for p9_pba_access and p9_pba_setup procedures
+# =============================================================================
+#If a reset is done need to unset the PBA_SLVRST_SLVCTL3_IN_PROG bit
+CAUSE_EFFECT{
+  LABEL=[PBA Reset set]
+  # Watch the PBASLVRST register for bits 0:2 to go to 0b111
+  WATCH=[REG(0x068001)] #PBASLVRST
+
+  CAUSE: TARGET=[REG(0x068001)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x068001)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x068001)] OP=[BIT,ON] BIT=[2]
+
+  #If the reset is set unset bit 7 to show that the PBA Slave reset is no longer in progress
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[7]
+
+}
+
+#If a read or write is done need to set the PBARBUFVAL[0,1,2,3,4,5] bits 33:39 to 0b0000001
+#set the PBAWBUFVAL[0,1] bits 35:39 to 0b00001
+#set the PBASLVRST to appropriate value
+CAUSE_EFFECT {
+  LABEL=[PBA Read or Write to set the PBARBUFVAL, PBAWBUFVAL, and PBASLVRST]
+  #If the data register is read or write 
+  WATCH_READ=[REG(0x0006D075)] #OCBDR3
+  WATCH=[REG(0x0006D075)] 
+  CAUSE: TARGET=[REG(0x00068001)] OP=[BIT,OFF] BIT=[11]
+
+  #set PBARBUFVAL0[buffer_status] to 0b0000001
+  EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[33]
+  EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[34]
+  EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012850)] OP=[BIT,ON] BIT=[39]
+  #set PBARBUFVAL1[buffer_status] to 0b0000001
+  EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[33]
+  EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[34]
+  EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012851)] OP=[BIT,ON] BIT=[39]
+  #set PBARBUFVAL2[buffer_status] to 0b0000001
+  EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[33]
+  EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[34]
+  EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012852)] OP=[BIT,ON] BIT=[39]
+
+  #set PBARBUFVAL3[buffer_status] to 0b0000001
+  EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[33]
+  EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[34]
+  EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012853)] OP=[BIT,ON] BIT=[39]
+  #set PBARBUFVAL4[buffer_status] to 0b0000001
+  EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[33]
+  EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[34]
+  EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012854)] OP=[BIT,ON] BIT=[39]
+  #set PBARBUFVAL5[buffer_status] to 0b0000001
+  EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[33]
+  EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[34]
+  EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012855)] OP=[BIT,ON] BIT=[39]
+
+  #set PBAWBUFVAL0[buffer_status] to 0b00001
+  EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012858)] OP=[BIT,ON] BIT=[39]
+
+  #set PBAWBUFVAL0[buffer_status] to 0b00001
+  EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,OFF] BIT=[35]
+  EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,OFF] BIT=[36]
+  EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,OFF] BIT=[37]
+  EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,OFF] BIT=[38]
+  EFFECT: TARGET=[REG(0x05012859)] OP=[BIT,ON] BIT=[39]
+
+  #unset PBASLVRST[in_prog] bit
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[7]
+  #set PBASLVRST[busy_status] to 0b0000 bits 8:11
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[8]
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[9]
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x068001)] OP=[BIT,OFF] BIT=[11]
+}
+
+#Basabjit had me separate these into the read and write because of their read/writeMainstore modules 
+#If a read is done do the read from memory 
+CAUSE_EFFECT{
+  LABEL=[PBA Read to set the PBARBUFVAL PBAWBUFVAL and PBASLVRST]
+  #If the data register is read
+  WATCH_READ=[REG(0x0006D075)] #OCBDR3
+  CAUSE: TARGET=[REG(0x00068001)] OP=[BIT,OFF] BIT=[11]
+
+  #Basabjit had me add these
+  # Read from the Memory
+  EFFECT: TARGET=[REG(0x00068FFE)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,80000000 00000000)] #Force refresh of address
+  EFFECT: TARGET=[MODULE(readMainstore, 0x00068FFF)] OP=[MODULECALL]  DATA=[REG(0x0006D075)]
+  EFFECT: TARGET=[REG(0x0006D070)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64, 07FFFFFF 00000000)]
+}
+
+#If a write is done do the write into memory 
+CAUSE_EFFECT{
+  LABEL=[PBA Write to set the PBARBUFVAL, PBAWBUFVAL, and PBASLVRST]
+  #If the data register is written
+  WATCH=[REG(0x0006D075)] #OCBDR3
+  CAUSE: TARGET=[REG(0x00068001)] OP=[BIT,OFF] BIT=[11]
+
+  # Write into from the Memory
+  EFFECT: TARGET=[REG(0x00068FFE)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,80000000 00000000)] #Force refresh of PBA address
+  EFFECT: TARGET=[MODULE(writeMainstore, 0x00068FFF)] OP=[MODULECALL]  DATA=[REG(0x0006D075)]
+  EFFECT: TARGET=[REG(0x0006D070)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64, 07FFFFFF 00000000)]
+}
+
+# PBA ADDRESS CALC
+CAUSE_EFFECT{
+  LABEL=[PBA ADDR Calculation]
+  #If the data register is read
+  WATCH=[REG(0x00068FFE)]
+
+  #Determine PBA Address
+  EFFECT: TARGET=[REG(0x00068FFF)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+  EFFECT: TARGET=[REG(0x00068FFF)] OP=[EQUALTO,BUF,MASK,SHIFT] DATA=[REG(0x0006D070)] MASK=[LITERAL(64,00000000 000FFFFF)] SHIFT=[32]
+
+  #bits 37:43 if PBA mask set
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[EQUALTO,BUF,SHIFT] DATA=[REG(0x0006D070)] SHIFT=[32] 
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[AND,BUF] DATA=[REG(0x05012B07)]
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[AND,BUF] DATA=[LITERAL(64,00000000 07F00000)]
+  EFFECT: TARGET=[REG(0x00068FFF)] OP=[OR,BUF] DATA=[PBAADDR(0x1)]
+
+  #bits 23:43 if PBA mask set
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[EQUALTO,BUF,MASK,SHIFT] DATA=[REG(0x00068007)] MASK=[LITERAL(64,00000000 0FFFC000)] SHIFT=[-13]
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[AND,BUF] DATA=[REG(0x05012B07)]
+  EFFECT: TARGET=[REG(0x00068FFF))] OP=[OR,BUF] DATA=[PBAADDR(0x1)]
+
+  #bits 23:43 if PBA mask clear
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[EQUALTO,BUF] DATA=[REG(0x05012B03)]
+  EFFECT: TARGET=[PBAADDR(0x0)] OP=[EQUALTO,BUF,INVERT] DATA=[REG(0x05012B07)]
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[AND,BUF] DATA=[PBAADDR(0x0)]
+  EFFECT: TARGET=[PBAADDR(0x1)] OP=[AND,BUF] DATA=[LITERAL(64,000001FF FFF00000)]
+  EFFECT: TARGET=[REG(0x00068FFF)] OP=[OR,BUF] DATA=[PBAADDR(0x1)]
+
+  #bits 8:22 always based on PBA BAR
+  EFFECT: TARGET=[PBAADDR(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x05012B03)]
+  EFFECT: TARGET=[PBAADDR(0x0)] OP=[AND,BUF] DATA=[LITERAL(64,00FFFE00 00000000)]
+  EFFECT: TARGET=[REG(0x00068FFF)] OP=[OR,BUF] DATA=[PBAADDR(0x1)]
+}
+
+# ==========================================================================
+# Actions for p9_adu_access and p9_adu_setup procedures 
+# ==========================================================================
+#If a read/write is done to the ALTD_DATA Register set the ALTD_STATUS Register so things are as expected
+CAUSE_EFFECT{
+  LABEL=[ADU Read or write to set ALTD_STATUS Register]
+  #If the data register is read
+  WATCH_READ=[REG(0x00090004)]
+  #If the data register is written
+  WATCH=[REG(0x00090004)]
+
+  #Set the ALTD_STATUS Register so these bits are set: 
+  #FBC_ALTD_BUSY = WAIT_CMD_ARBIT = WAIT_RESP = OVERRUN_ERR = AUTOINC_ERR = COMMAND_ERR = ADDRESS_ERR = COMMAND_HANG_ERR = DATA_HANG_ERR = PBINIT_MISSING = ECC_CE = ECC_UE = ECC_SUE = 0
+  EFFECT: TARGET=[REG(0x00090003)] OP=[BUF,AND] DATA=[LITERAL(64,001FDFFF FFFF1FFF)] 
+  EFFECT: TARGET=[REG(0x00090003)] OP=[BUF,OR] DATA=[LITERAL(64,30000000 00000000)]
+}
+
+#If a read/write is done to the ALTD_DATA Register and the Address only bit is not set then set the DATA_DONE bit to 1 
+CAUSE_EFFECT{
+  LABEL=[ADU Read or write to set ALTD_STATUS[DATA_DONE] bit]
+  #If the data register is read
+  WATCH_READ=[REG(0x00090004)]
+  #If the data register is written
+  WATCH=[REG(0x00090004)]
+  CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6]
+
+  #Set the DATA_DONE bit         
+  EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3]
+}
+
+#If a read/write is done to the ALTD_DATA Register and the Data only bit is not set then set the ADDR_DONE bit to 1 
+CAUSE_EFFECT{
+  LABEL=[ADU Read or write to set ALTD_STATUS[ADDR_DONE] bit]
+  #If the data register is read
+  WATCH_READ=[REG(0x00090004)]
+  #If the data register is written
+  WATCH=[REG(0x00090004)]
+  CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7]
+
+  #Set the ADDR_DONE bit 
+  EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2]
+}
+
+#If a read is done to the ALTD_CMD Register and it sets the lock set the ALTD_STATUS Register so the ALTD_STATUS_BUSY bit is set 
+CAUSE_EFFECT{
+  LABEL=[ADU Write to set ALTD_STATUS_BUSY]
+  WATCH=[REG(0x00090001)]
+  CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[11]
+
+  #Set the ALTD_STATUS Register so the ALTD_STATUS_BUSY bit is set
+  EFFECT: TARGET=[REG(0x090003)] OP=[BIT,ON] BIT=[0] 
+}
+#If a write is done to the ALD_CMD_REG to set the FBC_ALTD_START_OP bit it should turn FBC_ALTD_BUSY off
+CAUSE_EFFECT{
+  LABEL=[ADU Write to ALTD_CMD_REG to unset set ALTD_STATUS FBC_ALTD_BUSY bit]
+  WATCH=[REG(0x00090001)]
+  CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2]
+
+  #Unset the ALTD_STATUS Register so the ALTD_STATUS_BUSY is unset
+  EFFECT: TARGET=[REG(0x090003)] OP=[BIT,OFF] BIT=[0]
+}
+
+
+# =============================================================================
+# Actions for p9_ram_core procedures
+# =============================================================================
+# TODO: RTC 150507
+# MYCHIPLET is supposed to work, but for core chiplets, it only works on core 0
+# because of a bug in SUET.  Infrastructure team will fix it using the above RTC.
+CAUSE_EFFECT CHIPLETS ec {
+  LABEL=[p9_ram_core reads Thread Info Register]
+  # If bit 0 of C_RAM_MODEREG is set (Enable RAM)
+  WATCH=[REG(MYCHIPLET,0x00010A4E)]
+  CAUSE: TARGET=[REG(MYCHIPLET, 0x00010A4E)]  OP=[BIT,ON] BIT=[0]
+  # Set all threads active in C_THREAD_INFO
+  EFFECT: TARGET=[REG(MYCHIPLET, 0x00010A9B)]  OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xFFFFFFFF 0xFFFFFFFF)]
+}
+
+CAUSE_EFFECT CHIPLETS ec {
+  LABEL=[p9_ram_core - C_RAM_CTRL write]
+  # Any write to RAM CTRL reg (thread, opcode, etc...)
+  WATCH=[REG(MYCHIPLET, 0x00010A4F)]
+  # Set C_RAM_STATUS
+  #   - Clear RAM recovery status  bit 0
+  #   - Clear RAM exception status bit 2
+  #   - Set PPC complete status bit 1
+  #   - Set LSU is empty status bit 3
+  EFFECT: TARGET=[REG(MYCHIPLET, 0x00010A50)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0x50000000 0x00000000)]
+}
+
+# =============================================================================
+# Actions for p9_tod_setup and p9_tod_init 
+# =============================================================================
+#If a write is done to start the state machine set the FSM_REG_IS_RUNNING bit 
+CAUSE_EFFECT{
+  LABEL=[TOD statem machine is running]
+  WATCH=[REG(0x00040022)]
+  CAUSE: TARGET[REG(0x00040022)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x00040024)] OP=[BIT,ON] BIT=[4]
+}
diff --git a/src/import/chips/p9/sw_simulation/pervasive.act b/src/import/chips/p9/sw_simulation/pervasive.act
new file mode 100644
index 00000000..4c1d3130
--- /dev/null
+++ b/src/import/chips/p9/sw_simulation/pervasive.act
@@ -0,0 +1,211 @@
+# This file will contain all the Pervasive Actions
+# Simics action file for istep 2/3/4 procedures.
+
+CAUSE_EFFECT CHIPLETS tp nest xbus mc obus pcie cache ec {
+LABEL=[SEEPROM ARRAY INIT ]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(MYCHIPLET,0x00030002)]
+# OPCG_REG0.RUNN_MODE = 1
+CAUSE: TARGET=[REG(MYCHIPLET, 0x00030002)]  OP=[BIT,ON] BIT=[0]
+# OPCG_REG0.OPCG_STARTS_BIST = 1
+CAUSE: TARGET=[REG(MYCHIPLET, 0x00030002)]  OP=[BIT,ON] BIT=[14]
+# OPCG_REG0.OPCG_GO = 1
+CAUSE: TARGET=[REG(MYCHIPLET, 0x00030002)] OP=[BIT,ON] BIT=[1]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(MYCHIPLET, 0x00000100)] OP=[BIT,ON] BIT=[8]
+# SRAM Abist Done
+EFFECT: TARGET=[REG(MYCHIPLET, 0x00000100)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT CHIPLETS tp nest xbus mc obus pcie cache ec {
+LABEL=[SEEPROM SCAN0 MODULE ]
+# Watch PERV_OPCG_REG0
+WATCH=[REG(MYCHIPLET, 0x00030002)]
+# OPCG_REG0.RUN_SCAN0 = 1
+CAUSE: TARGET=[REG(MYCHIPLET, 0x00030002)]  OP=[BIT,ON] BIT=[2]
+# OPCG_DONE for CPLT_STAT0 register
+EFFECT: TARGET=[REG(MYCHIPLET, 0x00000100)] OP=[BIT,ON] BIT=[8]
+}
+
+# =============================================================================
+# Simics action for p9_sbe_tp_chiplet_init3
+# =============================================================================
+
+CAUSE_EFFECT CHIPLETS tp nest mc{
+LABEL=[Common_Clock_Start_AllRegions]
+# Watch PERV_CLK_REGION register
+WATCH=[REG(MYCHIPLET,0x00030006)]
+# Setup all Clock Domains and Clock Types
+CAUSE: TARGET=[REG(MYCHIPLET,0x00030006)]  OP=[EQUALTO,BUF] DATA=[LITERAL(64,0x69FE0000 0000E000)]
+# Clock running status for SL type should match with expected values.
+EFFECT: TARGET=[REG(MYCHIPLET,0x00030008)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xF601FFFF FFFFFFFF)]
+# Clock running status for NSL type should match with expected values.
+EFFECT: TARGET=[REG(MYCHIPLET,0x00030009)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xF601FFFF FFFFFFFF)]
+# Clock running status for ARY type should match with expected values.
+EFFECT: TARGET=[REG(MYCHIPLET,0x0003000A)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xF601FFFF FFFFFFFF)]
+}
+
+CAUSE_EFFECT{
+LABEL=[Start Calibration]
+# Watch KVREF_AND_VMEAS_MODE_STATUS_REG register
+WATCH=[REG(0x01020007)]
+# KVREF_AND_VMEAS_MODE_STATUS_REG.KVREF_START_CAL = 0b1
+CAUSE: TARGET=[REG(0x01020007)]  OP=[BIT,ON] BIT=[0]
+# Check KVREF_AND_VMEAS_MODE_STATUS_REG.KVREF_CAL_DONE
+EFFECT: TARGET=[REG(0x01020007)] OP=[BIT,ON] BIT=[16]
+}
+
+CAUSE_EFFECT{
+LABEL=[Check for OSC ok]
+# Setting LOCAL_FIR register value
+WATCH=[REG(0x0104000B)]
+# PERV.LOCAL_FIR.FIR_IN35 = 0
+CAUSE: TARGET=[REG(0x0104000B)]  OP=[BIT,OFF] BIT=[35]
+# PERV.LOCAL_FIR.FIR_IN36 = 0
+CAUSE: TARGET=[REG(0x0104000B)]  OP=[BIT,OFF] BIT=[36]
+# Check for OSC ok
+EFFECT: TARGET=[REG(0x0005001D)] OP=[BIT,OFF] BIT=[21]
+EFFECT: TARGET=[REG(0x0005001D)] OP=[BIT,ON] BIT=[28]
+# Osc error active
+EFFECT: TARGET=[REG(0x01020019)] OP=[BIT,OFF] BIT=[4]
+}
+
+# =============================================================================
+# Simics action for p9_sbe_npll_setup
+# =============================================================================
+
+CAUSE_EFFECT{
+LABEL=[SS PLL lock]
+#Watch PERV_ROOT_CTRL8_SCOM register
+WATCH=[REG(0x00050018)]
+# PIB.ROOT_CTRL8.TP_PLL_TEST_ENABLE_DC = 0
+CAUSE: TARGET=[REG(0x00050018)]  OP=[BIT,OFF] BIT=[12]
+# PIB.ROOT_CTRL8.TP_SSPLL_PLL_RESET0_DC = 0
+CAUSE: TARGET=[REG(0x00050018)]  OP=[BIT,OFF] BIT=[0]
+# Check SS PLL lock
+EFFECT: TARGET=[REG(0x010F0019)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT{
+LABEL=[CP and IO PLL lock]
+# Watch PERV_ROOT_CTRL8_SCOM register
+WATCH=[REG(0x00050018)]
+# PIB.ROOT_CTRL8.TP_FILTPLL_PLL_RESET1_DC = 0
+CAUSE: TARGET=[REG(0x00050018)]  OP=[BIT,OFF] BIT=[4]
+# Check PLL_LOCK_REG register value
+EFFECT: TARGET=[REG(0x010F0019)] OP=[BIT,ON] BIT=[1]
+EFFECT: TARGET=[REG(0x010F0019)] OP=[BIT,ON] BIT=[2]
+}
+
+CAUSE_EFFECT{
+LABEL=[NEST PLL LOCK]
+# Watch PERV_ROOT_CTRL8_SCOM register
+WATCH=[REG(0x00050018)]
+# PIB.PERV_CTRL0.TP_PLLRST_DC = 0
+CAUSE: TARGET=[REG(0x00050018)]  OP=[BIT,OFF] BIT=[4]
+# Check NEST PLL lock
+EFFECT: TARGET=[REG(0x010F0019)] OP=[BIT,ON] BIT=[3]
+}
+
+# =============================================================================
+# Simics action for p9_sbe_nest_startclocks
+# =============================================================================
+
+CAUSE_EFFECT CHIPLETS nest mc {
+LABEL=[Check checkstop Register]
+# Watch PERV_NET_CTRL0_WAND register
+WATCH=[REG(MYCHIPLET,0x000F0041)]
+# NET_CTRL0.FENCE_EN = 0
+CAUSE: TARGET=[REG(MYCHIPLET,0x000F0041)]  OP=[BIT,OFF] BIT=[18]
+# Check checkstop register
+EFFECT: TARGET=[REG(MYCHIPLET,0x00040000)]  OP=[EQUALTO,BUF] DATA=[LITERAL(64,0x00000000 00000000)] 
+}
+
+CAUSE_EFFECT CHIPLETS tp nest xbus mc obus pcie cache ec {
+LABEL=[SYNC_CONFIG.CLEAR_CHIPLET_IS_ALIGNED]
+# Watch PERV_SYNC_CONFIG
+WATCH=[REG(MYCHIPLET,0x00030000)]
+# SYNC_CONFIG.CLEAR_CHIPLET_IS_ALIGNED = 0b0
+CAUSE: TARGET=[REG(MYCHIPLET,0x00030000)]  OP=[BIT,OFF] BIT=[7]
+# Getting CPLT_STAT0 register value
+EFFECT: TARGET=[REG(MYCHIPLET,0x00000100)]  OP=[BIT,ON] BIT=[9]
+}
+
+
+# =============================================================================
+# Simics action for p9_sbe_tp_switchgear
+# =============================================================================
+CAUSE_EFFECT {
+LABEL=[I2C Stop Sequence]
+# Watch PU_CONTROL_REGISTER_B
+WATCH=[REG(0x000A0000)]
+# PIB.CONTROL_REGISTER_B.PIB_CNTR_REG_BIT_WITHSTOP_0 = 1
+CAUSE: TARGET=[REG(0x000A0000)]  OP=[BIT,ON] BIT=[3]
+# PIB.CONTROL_REGISTER_B.ENH_MODE_0 = 1
+CAUSE: TARGET=[REG(0x000A0000)]  OP=[BIT,ON] BIT=[26]
+# PIB.STATUS_REGISTER_B.BUS_STATUS_BUSY_0
+EFFECT: TARGET=[REG(0x000A0002)] OP=[BIT,OFF] BIT=[44]
+}
+
+CAUSE_EFFECT {
+LABEL=[Backup Seeprom Magic Num]
+# Watch PU_CONTROL_REGISTER_B
+WATCH=[REG(0x000A0000)]
+CAUSE: TARGET=[REG(0x000A0000)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xD8A90290 00000000)]
+# PIB.STATUS_REGISTER_B.BUS_STATUS_BUSY_0
+EFFECT: TARGET=[REG(0x000A0002)] OP=[BIT,OFF] BIT=[44]
+EFFECT: TARGET=[REG(0x000A0003)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0x58495020 5345504D)]
+}
+
+CAUSE_EFFECT {
+LABEL=[Normal Seeprom Sequnce Num]
+# Watch PU_CONTROL_REGISTER_B
+WATCH=[REG(0x000A0000)]
+CAUSE: TARGET=[REG(0x000A0000)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0xD8A90090 00000000)]
+# PIB.STATUS_REGISTER_B.BUS_STATUS_BUSY_0
+EFFECT: TARGET=[REG(0x000A0002)] OP=[BIT,OFF] BIT=[44]
+EFFECT: TARGET=[REG(0x000A0003)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,0x58495020 5345504D)]
+}
+# =============================================================================
+# Simics action for p9_sbe_chiplet_pll_setup
+# =============================================================================
+CAUSE_EFFECT CHIPLETS nest xbus mc obus{
+LABEL=[PLL lock]
+# Watch PERV_NET_CTRL0_WAND Register
+WATCH=[REG(MYCHIPLET,0x000F0041)]
+# NET_CTRL0.PLL_RESET = 0
+CAUSE: TARGET=[REG(MYCHIPLET,0x000F0041)]  OP=[BIT,OFF] BIT=[4]
+# Getting PLL_LOCK_REG register value
+EFFECT: TARGET=[REG(MYCHIPLET,0x000F0019)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT CHIPLETS pcie{
+LABEL=[PLL lock]
+# Watch PERV_NET_CTRL0_WAND Register
+WATCH=[REG(MYCHIPLET,0x000F0041)]
+# NET_CTRL0.PLL_RESET = 0
+CAUSE: TARGET=[REG(MYCHIPLET,0x000F0041)]  OP=[BIT,OFF] BIT=[4]
+# Getting PLL_LOCK_REG register value
+EFFECT: TARGET=[REG(MYCHIPLET,0x000F0019)] OP=[BIT,ON] BIT=[0]
+EFFECT: TARGET=[REG(MYCHIPLET,0x000F0019)] OP=[BIT,ON] BIT=[1]
+}
+
+# =============================================================================
+# Simics action for p9_start_cbs
+# =============================================================================
+CAUSE_EFFECT {
+LABEL=[CBS_CS_START_BOOT_SEQUENCER]
+#Watch PERV_CBS_CS_FSI
+WATCH=[CFAM_REG(0x00002801)]
+# CFAM.CBS_CS.CBS_CS_START_BOOT_SEQUENCER = 1
+CAUSE: TARGET=[CFAM_REG(0x00002801)]  OP=[BIT,ON] BIT=[0]
+# CFAM.CBS_CS.CBS_CS_INTERNAL_STATE_VECTOR 
+EFFECT: TARGET=[CFAM_REG(0x00002801)] OP=[AND,BUF] DATA=[LITERAL(32,0xFFFF0000)]
+EFFECT: TARGET=[CFAM_REG(0x00002801)] OP=[OR,BUF] DATA=[LITERAL(32,0x00000002)]
+}
+
+
+
+
+
+
diff --git a/src/import/chips/p9/sw_simulation/powermgmt.act b/src/import/chips/p9/sw_simulation/powermgmt.act
new file mode 100644
index 00000000..0cfd5c41
--- /dev/null
+++ b/src/import/chips/p9/sw_simulation/powermgmt.act
@@ -0,0 +1,3497 @@
+# This file will contain all the Power MGMT Actions
+
+##
+# Actions for Procedure - p9_hcd_cache_startclocks
+##
+
+CAUSE_EFFECT {
+  LABEL=[Raise clock sync enable before switch to dpll on EX L2s]
+  WATCH=[REG(0x100F0162)]
+  CAUSE: TARGET=[REG(0x100F0162)] OP=[BIT,ON] BIT=[33]
+  EFFECT: TARGET=[REG(0x100F0163)] OP=[BIT,ON] BIT=[62]
+  EFFECT: TARGET=[REG(0x100F0163)] OP=[BIT,ON] BIT=[63]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Start clock(sl+refresh clock region) via CLK_REGION]
+  WATCH=[REG(0x10030006)]
+  CAUSE: TARGET=[REG(0x10030006)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,5FFE0000 0000E000)]
+  EFFECT: TARGET=[REG(0x10030008)] OP=[AND,BUF,MASK] MASK=[LITERAL(64, 0FFE0000 00000000)] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+
+##
+## Actions for Procedure - p9_hcd_core_startclocks
+##
+
+CAUSE_EFFECT {
+  LABEL=[Raise clock sync enable before switch to dpll]
+  WATCH=[REG(0x200F016A)]
+  CAUSE: TARGET=[REG(0x200F016A)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x200F016B)] OP=[BIT,ON] BIT=[13]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Start clock(sl+refresh clock region) via CLK_REGION]
+  WATCH=[REG(0x20030006)]
+  CAUSE: TARGET=[REG(0x20030006)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,5FFE0000 0000E000)]
+  EFFECT: TARGET=[REG(0x20030008)] OP=[AND,BUF,MASK] MASK=[LITERAL(64, 0FFE0000 00000000)] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+
+##
+## Actions for Procedure - p9_pm_occ_control
+##
+# Upon writing the PU_OCB_PIB_OCR[DBG_HALT} bit, set the OCCLFIR_PPC405_DBGSTOPACK_BIT.
+CAUSE_EFFECT {
+  LABEL=[PPC405 SAFE_HALT]
+  WATCH=[REG(0x0006D002)]
+  CAUSE: TARGET=[REG(0x0006D002)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00200000 00000000)]
+  EFFECT: TARGET=[REG(0x01010800)] OP=[BIT,ON] BIT=[31]
+}
+
+CAUSE_EFFECT {
+  LABEL=[PPC405 ENSURE_SAFE_HALT]
+  WATCH=[REG(0x01010801)]
+  CAUSE: TARGET=[REG(0x0006D002)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00200000 00000000)]
+  EFFECT: TARGET=[REG(0x01010800)] OP=[EQUALTO,BUF] DATA=[REG(0x01010801)]
+  EFFECT: TARGET=[REG(0x01010800)] OP=[BIT,ON] BIT=[31]
+  ELSE: TARGET=[REG(0x01010800)] OP=[EQUALTO,BUF] DATA=[REG(0x01010801)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Clear halt]
+  WATCH=[REG(0x0006D001)]
+  CAUSE: TARGET=[REG(0x0006D001)] OP=[BIT,ON] BIT=[10]
+  EFFECT: TARGET=[REG(0x0006D000)] OP=[BIT,OFF] BIT=[10]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Clear reset]
+  WATCH=[REG(0x0006D001)]
+  CAUSE: TARGET=[REG(0x0006D001)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x0006D000)] OP=[BIT,OFF] BIT=[0]
+}
+
+##
+## Actions for Procedure - p9_pm_occ_gpe_init
+##
+
+CAUSE_EFFECT {
+  LABEL=[OCC GPE0 HALT]
+  WATCH=[REG(0x00060010)]
+  CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[1]
+  CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[2]
+  CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,ON] BIT=[3]
+  #suet OCCGPE0_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[OCC GPE1 HALT]
+  WATCH=[REG(0x00062010)]
+  CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[1]
+  CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[2]
+  CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,ON] BIT=[3]
+  #suet OCCGPE1_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,ON] BIT=[0]
+}
+
+
+##
+## Actions for Procedure - p9_pm_pba_init
+##
+
+CAUSE_EFFECT {
+  LABEL=[BCDE STOP]
+  WATCH=[REG(0x00068010)]
+  CAUSE: TARGET=[REG(0x00068010)] OP=[BIT,ON] BIT=[0]
+  #suet BCDE_UNHALT:tc1- EFFECT: TARGET=[REG(0x00068012)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x00068012)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[BCUE STOP]
+  WATCH=[REG(0x00068015)]
+  CAUSE: TARGET=[REG(0x00068015)] OP=[BIT,ON] BIT=[0]
+  #suet BCUE_UNHALT:tc1- EFFECT: TARGET=[REG(0x00068017)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x00068017)] OP=[BIT,OFF] BIT=[0]
+}
+
+## Actions for Procedure - p9_sbe_check_master_stop15 and others
+##
+
+## Core0 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x200F0110)]
+  CAUSE: TARGET=[REG(0x200F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)]
+  EFFECT: TARGET=[REG(0x200F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x200F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x200F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x200F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core0 End
+
+## Core1 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x210F0110)]
+  CAUSE: TARGET=[REG(0x210F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x210F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x210F0110)]
+  EFFECT: TARGET=[REG(0x210F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x210F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x210F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x210F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core1 End
+
+## Core2 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x220F0110)]
+  CAUSE: TARGET=[REG(0x220F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x220F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)]
+  EFFECT: TARGET=[REG(0x220F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x220F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x220F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x220F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core2 End
+
+## Core3 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x230F0110)]
+  CAUSE: TARGET=[REG(0x230F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x230F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x230F0110)]
+  EFFECT: TARGET=[REG(0x230F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x230F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x230F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x230F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core3 End
+
+## Core4 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x240F0110)]
+  CAUSE: TARGET=[REG(0x240F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x240F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x240F0110)]
+  EFFECT: TARGET=[REG(0x240F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x240F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x240F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x240F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core4 End
+
+## Core5 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x250F0110)]
+  CAUSE: TARGET=[REG(0x250F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x250F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x250F0110)]
+  EFFECT: TARGET=[REG(0x250F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x250F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x250F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x250F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core5 End
+
+## Core6 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x260F0110)]
+  CAUSE: TARGET=[REG(0x260F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x260F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)]
+  EFFECT: TARGET=[REG(0x260F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x260F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x260F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x260F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core6 End
+
+## Core7 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x270F0110)]
+  CAUSE: TARGET=[REG(0x270F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x270F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x270F0110)]
+  EFFECT: TARGET=[REG(0x270F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x270F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x270F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x270F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core7 End
+
+## Core8 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x280F0110)]
+  CAUSE: TARGET=[REG(0x280F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x280F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x280F0110)]
+  EFFECT: TARGET=[REG(0x280F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x280F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x280F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x200F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core8 End
+
+## Core9 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x290F0110)]
+  CAUSE: TARGET=[REG(0x290F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x290F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x290F0110)]
+  EFFECT: TARGET=[REG(0x290F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x290F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x290F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x290F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core9 End
+
+## Core10 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x2A0F0110)]
+  CAUSE: TARGET=[REG(0x2A0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2A0F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2A0F0110)]
+  EFFECT: TARGET=[REG(0x2A0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2A0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2A0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2A0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core10 End
+
+## Core11 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x2B0F0110)]
+  CAUSE: TARGET=[REG(0x2B0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2B0F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2B0F0110)]
+  EFFECT: TARGET=[REG(0x2B0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2B0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2B0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2B0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core11 End
+
+## Core12 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x2C0F0110)]
+  CAUSE: TARGET=[REG(0x2C0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2C0F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2C0F0110)]
+  EFFECT: TARGET=[REG(0x2C0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2C0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2C0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2C0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core12 End
+
+## Core13 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x2D0F0110)]
+  CAUSE: TARGET=[REG(0x2D0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2D0F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2D0F0110)]
+  EFFECT: TARGET=[REG(0x2D0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2D0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2D0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2D0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core13 End
+
+## Core14 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x2E0F0110)]
+  CAUSE: TARGET=[REG(0x2E0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2E0F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2E0F0110)]
+  EFFECT: TARGET=[REG(0x2E0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2E0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2E0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2E0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core14 End
+
+## Core15 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x2F0F0110)]
+  CAUSE: TARGET=[REG(0x2F0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2F0F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2F0F0110)]
+  EFFECT: TARGET=[REG(0x2F0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2F0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2F0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x2F0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core15 End
+
+## Core16 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x300F0110)]
+  CAUSE: TARGET=[REG(0x300F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x300F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x300F0110)]
+  EFFECT: TARGET=[REG(0x300F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x300F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x300F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x300F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core16 End
+
+## Core17 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x310F0110)]
+  CAUSE: TARGET=[REG(0x310F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x310F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x310F0110)]
+  EFFECT: TARGET=[REG(0x310F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x310F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x310F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x310F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core17 End
+
+## Core18 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x320F0110)]
+  CAUSE: TARGET=[REG(0x320F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x320F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x320F0110)]
+  EFFECT: TARGET=[REG(0x320F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x320F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x320F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x320F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core18 End
+
+## Core19 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x330F0110)]
+  CAUSE: TARGET=[REG(0x330F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x330F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x330F0110)]
+  EFFECT: TARGET=[REG(0x330F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x330F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x330F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x330F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core19 End
+
+## Core20 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x340F0110)]
+  CAUSE: TARGET=[REG(0x340F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x340F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x340F0110)]
+  EFFECT: TARGET=[REG(0x340F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x340F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x340F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x340F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core20 End
+
+## Core21 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x350F0110)]
+  CAUSE: TARGET=[REG(0x350F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x350F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x350F0110)]
+  EFFECT: TARGET=[REG(0x350F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x350F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x350F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x350F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core21 End
+
+## Core22 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x360F0110)]
+  CAUSE: TARGET=[REG(0x360F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x360F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x360F0110)]
+  EFFECT: TARGET=[REG(0x360F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x360F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x360F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x360F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core22 End
+
+## Core23 Start
+CAUSE_EFFECT {
+  LABEL=[SSH_SRC_WRITE]
+  WATCH=[REG(0x370F0110)]
+  CAUSE: TARGET=[REG(0x370F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x370F0110)]
+  EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x370F0110)]
+  EFFECT: TARGET=[REG(0x370F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x370F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x370F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+  EFFECT: TARGET=[REG(0x370F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+}
+## Core23 End
+
+##
+# Actions for Procedure - p9_block_wakeup_intr
+##
+
+# Core Power Management Mode Register
+CAUSE_EFFECT {
+  LABEL=[CPMMR Write OR of PPM Write Override]
+  WATCH=[REG(0x290F0108)]
+  CAUSE: TARGET=[REG(0x290F0108)] OP=[BIT,ON] BIT=[1]
+  EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,ON] BIT=[1]
+}
+
+CAUSE_EFFECT {
+  LABEL=[CPMMR Write CLEAR of PPM Write Override]
+  WATCH=[REG(0x290F0107)]
+  CAUSE: TARGET=[REG(0x290F0107)] OP=[BIT,ON] BIT=[1]
+  EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,OFF] BIT=[1]
+}
+
+# General Power Management Mode Register
+CAUSE_EFFECT {
+  LABEL=[GPMMR Write OR of Block Wakeup Events]
+  WATCH=[REG(0x290F0102)]
+  CAUSE: TARGET=[REG(0x290F0102)] OP=[BIT,ON] BIT=[6]
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[6]
+}
+
+CAUSE_EFFECT {
+  LABEL=[GPMMR Write CLEAR of PPM Write Override]
+  WATCH=[REG(0x290F0101)]
+  CAUSE: TARGET=[REG(0x290F0101)] OP=[BIT,ON] BIT=[6]
+  EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[6]
+}
+
+##
+## Actions for Procedure - p9_pm_stop_gpe_init
+##
+
+CAUSE_EFFECT {
+  LABEL=[SGPE_HALT]
+  WATCH=[REG(0x00066010)]
+  CAUSE: TARGET=[REG(0x00066010)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 10000000 00000000)]
+  #suet SGPE_HALT:tc1- EFFECT: TARGET=[REG(0x00066021)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x00066021)] OP=[BIT,ON] BIT=[0]
+}
+
+# SRESET is a pulse in the hardware that will start the GPE (removed it from halted state)
+CAUSE_EFFECT {
+  LABEL=[SGPE_ACTIVE_SRESET]
+  WATCH=[REG(0x00066010)]
+  CAUSE: TARGET=[REG(0x00066010)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 50000000 00000000)]
+  #suet SGPE_ACTIVE_SRESET:tc1- EFFECT: TARGET=[REG(0x00066021)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x00066021)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x006C08A)] OP=[BIT,ON] BIT=[8]
+}
+
+# HRESET is a pulse in the hardware that will start the GPE (removed it from halted state)
+CAUSE_EFFECT {
+  LABEL=[SGPE_ACTIVE_HRESET]
+  WATCH=[REG(0x00066010)]
+  CAUSE: TARGET=[REG(0x00066010)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 60000000 00000000)]
+  #suet SGPE_ACTIVE:tc1- EFFECT: TARGET=[REG(0x00066021)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x00066021)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x0006C08A)] OP=[BIT,ON] BIT=[8]
+}
+
+#Set the OCC FLAG
+CAUSE_EFFECT {
+  LABEL=[SGPE_ACTIVE_OCCFLAG]
+  WATCH=[REG(0x0006C08B)]
+  EFFECT: TARGET=[REG(0x0006C08A)] OP=[EQUALTO,BUF,INVERT] DATA=[REG(0x0006C08B)]
+}
+
+##
+## Actions for p9_pm_ocb_init
+##
+
+CAUSE_EFFECT {
+  LABEL=[Channel 0 linear stream]
+  WATCH=[REG(0x0006D013)]
+  WATCH=[REG(0x0006D012)]
+  CAUSE: TARGET=[REG(0x0006D013)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x0006D012)] OP=[BIT,ON] BIT=[5]
+  EFFECT: TARGET=[REG(0x0006D011)] OP=[BIT,ON] BIT=[4]
+  EFFECT: TARGET=[REG(0x0006D011)] OP=[BIT,OFF] BIT=[5]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Channel 1 linear stream]
+  WATCH=[REG(0x0006D033)]
+  WATCH=[REG(0x0006D032)]
+  CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x0006D032)] OP=[BIT,ON] BIT=[5]
+  EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4]
+  EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,OFF] BIT=[5]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Channel 1 circular push interupt enable]
+  WATCH=[REG(0x0006D033)]
+  CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[3]
+  CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[5]
+  EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[3]
+  EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4]
+  EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[5]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Channel 1 circular push interrupt disable]
+  WATCH=[REG(0x0006D033)]
+  WATCH=[REG(0x0006D032)]
+  CAUSE: TARGET=[REG(0x0006D032)] OP=[BIT,ON] BIT=[3]
+  CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[5]
+  EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,OFF] BIT=[3]
+  EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4]
+  EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[5]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Channel 2 linear stream]
+  WATCH=[REG(0x0006D053)]
+  WATCH=[REG(0x0006D052)]
+  CAUSE: TARGET=[REG(0x0006D053)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x0006D052)] OP=[BIT,ON] BIT=[5]
+  EFFECT: TARGET=[REG(0x0006D051)] OP=[BIT,ON] BIT=[4]
+  EFFECT: TARGET=[REG(0x0006D051)] OP=[BIT,OFF] BIT=[5]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Channel 3 linear stream]
+  WATCH=[REG(0x0006D073)]
+  WATCH=[REG(0x0006D072)]
+  CAUSE: TARGET=[REG(0x0006D073)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x0006D072)] OP=[BIT,ON] BIT=[5]
+  EFFECT: TARGET=[REG(0x0006D071)] OP=[BIT,ON] BIT=[4]
+  EFFECT: TARGET=[REG(0x0006D071)] OP=[BIT,OFF] BIT=[5]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Channel 0 circular stream]
+  WATCH=[REG(0x0006D013)]
+  CAUSE: TARGET=[REG(0x0006D013)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x0006D013)] OP=[BIT,ON] BIT=[5]
+  EFFECT: TARGET=[REG(0x0006D011)] OP=[BIT,ON] BIT=[4]
+  EFFECT: TARGET=[REG(0x0006D011)] OP=[BIT,ON] BIT=[5]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Channel 1 circular stream]
+  WATCH=[REG(0x0006D033)]
+  CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[5]
+  EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4]
+  EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[5]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Channel 2 circular stream]
+  WATCH=[REG(0x0006D053)]
+  CAUSE: TARGET=[REG(0x0006D053)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x0006D053)] OP=[BIT,ON] BIT=[5]
+  EFFECT: TARGET=[REG(0x0006D051)] OP=[BIT,ON] BIT=[4]
+  EFFECT: TARGET=[REG(0x0006D051)] OP=[BIT,ON] BIT=[5]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Channel 3 circular stream]
+  WATCH=[REG(0x0006D073)]
+  CAUSE: TARGET=[REG(0x0006D073)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x0006D073)] OP=[BIT,ON] BIT=[5]
+  EFFECT: TARGET=[REG(0x0006D071)] OP=[BIT,ON] BIT=[4]
+  EFFECT: TARGET=[REG(0x0006D071)] OP=[BIT,ON] BIT=[5]
+}
+
+
+## Actions for Procedure - p9_setup_evid
+##
+
+CAUSE_EFFECT {
+ LABEL=[AVSBus Write data register 0B]
+ WATCH=[REG(0x0006C718)]
+ CAUSE: TARGET=[REG(0x0006C718)] OP=[BIT,ON] BIT=[1] 
+ EFFECT: TARGET=[REG(0x0006C716)] OP=[BIT,ON] BIT=[0] 
+}
+
+CAUSE_EFFECT {
+ LABEL=[AVSBus Status register 0B]
+ WATCH_READ=[REG(0x0006C716)]
+ CAUSE: TARGET=[REG(0x0006C716)] OP=[BIT,ON] BIT=[0] 
+ EFFECT: TARGET=[REG(0x0006C716)] OP=[BIT,OFF] BIT=[0] 
+}
+
+CAUSE_EFFECT {
+ LABEL=[AVSBus Write data register 1B]
+ WATCH=[REG(0x0006C738)]
+ CAUSE: TARGET=[REG(0x0006C738)] OP=[BIT,ON] BIT=[1] 
+ EFFECT: TARGET=[REG(0x0006C736)] OP=[BIT,ON] BIT=[0] 
+}
+
+CAUSE_EFFECT {
+ LABEL=[AVSBus Status register 1B]
+ WATCH_READ=[REG(0x0006C736)]
+ CAUSE: TARGET=[REG(0x0006C736)] OP=[BIT,ON] BIT=[0] 
+ EFFECT: TARGET=[REG(0x0006C736)] OP=[BIT,OFF] BIT=[0] 
+}
+
+## Core 0 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x200F011A)]
+  CAUSE: TARGET=[REG(0x200F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x200F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x200F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 0 End
+## Core 1 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x210F011A)]
+  CAUSE: TARGET=[REG(0x210F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x210F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x210F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 1 End
+## Core 2 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x220F011A)]
+  CAUSE: TARGET=[REG(0x220F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x220F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x220F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 2 End
+## Core 3 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x230F011A)]
+  CAUSE: TARGET=[REG(0x230F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x230F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x230F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 3 End
+## Core 4 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x240F011A)]
+  CAUSE: TARGET=[REG(0x240F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x240F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x240F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 4 End
+## Core 5 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x250F011A)]
+  CAUSE: TARGET=[REG(0x250F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x250F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x250F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 5 End
+## Core 6 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x260F011A)]
+  CAUSE: TARGET=[REG(0x260F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x260F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x260F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 6 End
+## Core 7 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x270F011A)]
+  CAUSE: TARGET=[REG(0x270F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x270F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x270F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 7 End
+## Core 8 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x280F011A)]
+  CAUSE: TARGET=[REG(0x280F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x280F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x280F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 8 End
+## Core 9 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x290F011A)]
+  CAUSE: TARGET=[REG(0x290F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x290F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x290F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 9 End
+## Core 10 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x2a0F011A)]
+  CAUSE: TARGET=[REG(0x2a0F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2a0F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x2a0F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 10 End
+## Core 11 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x2b0F011A)]
+  CAUSE: TARGET=[REG(0x2b0F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2b0F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x2b0F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 11 End
+## Core 12 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x2c0F011A)]
+  CAUSE: TARGET=[REG(0x2c0F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2c0F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x2c0F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 12 End
+## Core 13 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x2d0F011A)]
+  CAUSE: TARGET=[REG(0x2d0F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2d0F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x2d0F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 13 End
+## Core 14 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x2e0F011A)]
+  CAUSE: TARGET=[REG(0x2e0F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2e0F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x2e0F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 14 End
+## Core 15 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x2f0F011A)]
+  CAUSE: TARGET=[REG(0x2f0F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2f0F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x2f0F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 15 End
+## Core 16 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x300F011A)]
+  CAUSE: TARGET=[REG(0x300F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x300F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x300F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 16 End
+## Core 17 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x310F011A)]
+  CAUSE: TARGET=[REG(0x310F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x310F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x310F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 17 End
+## Core 18 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x320F011A)]
+  CAUSE: TARGET=[REG(0x320F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x320F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x320F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 18 End
+## Core 19 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x330F011A)]
+  CAUSE: TARGET=[REG(0x330F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x330F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x330F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 19 End
+## Core 20 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x340F011A)]
+  CAUSE: TARGET=[REG(0x340F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x340F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x340F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 20 End
+## Core 21 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x350F011A)]
+  CAUSE: TARGET=[REG(0x350F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x350F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x350F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 21 End
+## Core 22 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x360F011A)]
+  CAUSE: TARGET=[REG(0x360F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x360F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x360F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 22 End
+## Core 23 Start
+
+##
+# Actions for Procedure - p9_hcd_core_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x370F011A)]
+  CAUSE: TARGET=[REG(0x370F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x370F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x370F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+# Core 23 End
+## EQ 0 Start
+
+##
+# Actions for Procedure - p9_hcd_cache_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x100F011A)]
+  CAUSE: TARGET=[REG(0x100F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x100F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x100F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x100F011A)]
+  CAUSE: TARGET=[REG(0x100F011A)] OP=[BIT,ON] BIT=[2]
+  EFFECT: TARGET=[REG(0x100F0118)] OP=[BIT,ON] BIT=[50]
+  EFFECT: TARGET=[REG(0x100F011C)] OP=[BIT,ON] BIT=[2]
+}
+
+## EQ 0 End
+
+## EQ 1 Start
+
+##
+# Actions for Procedure - p9_hcd_cache_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x110F011A)]
+  CAUSE: TARGET=[REG(0x110F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x110F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x110F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x110F011A)]
+  CAUSE: TARGET=[REG(0x110F011A)] OP=[BIT,ON] BIT=[2]
+  EFFECT: TARGET=[REG(0x110F0118)] OP=[BIT,ON] BIT=[50]
+  EFFECT: TARGET=[REG(0x110F011C)] OP=[BIT,ON] BIT=[2]
+}
+
+## EQ 1 End
+
+## EQ 2 Start
+
+##
+# Actions for Procedure - p9_hcd_cache_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x120F011A)]
+  CAUSE: TARGET=[REG(0x120F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x120F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x120F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x120F011A)]
+  CAUSE: TARGET=[REG(0x120F011A)] OP=[BIT,ON] BIT=[2]
+  EFFECT: TARGET=[REG(0x120F0118)] OP=[BIT,ON] BIT=[50]
+  EFFECT: TARGET=[REG(0x120F011C)] OP=[BIT,ON] BIT=[2]
+}
+
+## EQ 2 End
+
+## EQ 3 Start
+
+##
+# Actions for Procedure - p9_hcd_cache_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x130F011A)]
+  CAUSE: TARGET=[REG(0x130F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x130F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x130F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x130F011A)]
+  CAUSE: TARGET=[REG(0x130F011A)] OP=[BIT,ON] BIT=[2]
+  EFFECT: TARGET=[REG(0x130F0118)] OP=[BIT,ON] BIT=[50]
+  EFFECT: TARGET=[REG(0x130F011C)] OP=[BIT,ON] BIT=[2]
+}
+
+## EQ 3 End
+
+## EQ 4 Start
+
+##
+# Actions for Procedure - p9_hcd_cache_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x140F011A)]
+  CAUSE: TARGET=[REG(0x140F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x140F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x140F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x140F011A)]
+  CAUSE: TARGET=[REG(0x140F011A)] OP=[BIT,ON] BIT=[2]
+  EFFECT: TARGET=[REG(0x140F0118)] OP=[BIT,ON] BIT=[50]
+  EFFECT: TARGET=[REG(0x140F011C)] OP=[BIT,ON] BIT=[2]
+}
+
+## EQ 4 End
+
+## EQ 5 Start
+
+##
+# Actions for Procedure - p9_hcd_cache_poweron
+##
+
+CAUSE_EFFECT {
+  LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x150F011A)]
+  CAUSE: TARGET=[REG(0x150F011A)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x150F0118)] OP=[BIT,ON] BIT=[42]
+  EFFECT: TARGET=[REG(0x150F011C)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled]
+  WATCH=[REG(0x150F011A)]
+  CAUSE: TARGET=[REG(0x150F011A)] OP=[BIT,ON] BIT=[2]
+  EFFECT: TARGET=[REG(0x150F0118)] OP=[BIT,ON] BIT=[50]
+  EFFECT: TARGET=[REG(0x150F011C)] OP=[BIT,ON] BIT=[2]
+}
+
+## EQ 5 End
+
+##
+## Actions for Procedure - p9_pm_corequad_init
+##
+
+# Quad PPM Mode Setup
+
+CAUSE_EFFECT {
+  LABEL=[Q0 PPM Mode Setup]
+  WATCH=[REG(0x100F0104)]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[2]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[3]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[5]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[6]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[7]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[8]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[9]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[18]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[19]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[20]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[22]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[24]
+  CAUSE: TARGET=[REG(0x100F0104)] OP=[BIT,ON] BIT=[26]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[2]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[3]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[4]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[5]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[6]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[7]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[8]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[9]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[13]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[18]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[19]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[20]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[22]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[24]
+  EFFECT: TARGET=[REG(0x100F0103)] OP=[BIT,OFF] BIT=[26]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Q1 PPM Mode Setup]
+  WATCH=[REG(0x110F0104)]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[2]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[3]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[5]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[6]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[7]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[8]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[9]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[18]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[19]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[20]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[22]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[24]
+  CAUSE: TARGET=[REG(0x110F0104)] OP=[BIT,ON] BIT=[26]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[2]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[3]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[4]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[5]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[6]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[7]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[8]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[9]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[13]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[18]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[19]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[20]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[22]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[24]
+  EFFECT: TARGET=[REG(0x110F0103)] OP=[BIT,OFF] BIT=[26]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Q2 PPM Mode Setup]
+  WATCH=[REG(0x120F0104)]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[2]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[3]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[5]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[6]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[7]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[8]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[9]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[18]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[19]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[20]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[22]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[24]
+  CAUSE: TARGET=[REG(0x120F0104)] OP=[BIT,ON] BIT=[26]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[2]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[3]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[4]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[5]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[6]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[7]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[8]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[9]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[13]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[18]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[19]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[20]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[22]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[24]
+  EFFECT: TARGET=[REG(0x120F0103)] OP=[BIT,OFF] BIT=[26]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Q3 PPM Mode Setup]
+  WATCH=[REG(0x130F0104)]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[2]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[3]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[5]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[6]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[7]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[8]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[9]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[18]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[19]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[20]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[22]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[24]
+  CAUSE: TARGET=[REG(0x130F0104)] OP=[BIT,ON] BIT=[26]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[2]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[3]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[4]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[5]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[6]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[7]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[8]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[9]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[13]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[18]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[19]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[20]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[22]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[24]
+  EFFECT: TARGET=[REG(0x130F0103)] OP=[BIT,OFF] BIT=[26]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Q4 PPM Mode Setup]
+  WATCH=[REG(0x140F0104)]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[2]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[3]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[5]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[6]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[7]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[8]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[9]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[18]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[19]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[20]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[22]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[24]
+  CAUSE: TARGET=[REG(0x140F0104)] OP=[BIT,ON] BIT=[26]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[2]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[3]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[4]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[5]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[6]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[7]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[8]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[9]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[13]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[18]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[19]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[20]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[22]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[24]
+  EFFECT: TARGET=[REG(0x140F0103)] OP=[BIT,OFF] BIT=[26]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Q5 PPM Mode Setup]
+  WATCH=[REG(0x150F0104)]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[2]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[3]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[4]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[5]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[6]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[7]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[8]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[9]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[18]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[19]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[20]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[22]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[24]
+  CAUSE: TARGET=[REG(0x150F0104)] OP=[BIT,ON] BIT=[26]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[2]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[3]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[4]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[5]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[6]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[7]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[8]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[9]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[13]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[18]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[19]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[20]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[22]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[24]
+  EFFECT: TARGET=[REG(0x150F0103)] OP=[BIT,OFF] BIT=[26]
+}
+
+# CME flags clear
+CAUSE_EFFECT {
+  LABEL=[Q0 - CME FLAG Clear]
+  WATCH=[REG(0x10012421)]
+  CAUSE: TARGET=[REG(0x10012421)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x10012420)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Q1 - CME FLAG Clear]
+  WATCH=[REG(0x11012421)]
+  CAUSE: TARGET=[REG(0x11012421)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x11012420)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Q2 - CME FLAG Clear]
+  WATCH=[REG(0x12012421)]
+  CAUSE: TARGET=[REG(0x12012421)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x12012420)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Q3 - CME FLAG Clear]
+  WATCH=[REG(0x13012421)]
+  CAUSE: TARGET=[REG(0x13012421)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x13012420)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Q4 - CME FLAG Clear]
+  WATCH=[REG(0x14012421)]
+  CAUSE: TARGET=[REG(0x14012421)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x14012420)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Q5 - CME FLAG Clear]
+  WATCH=[REG(0x15012421)]
+  CAUSE: TARGET=[REG(0x15012421)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x15012420)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00000000 00000000)]
+}
+
+# CME SRAM SCRUB
+CAUSE_EFFECT {
+  LABEL=[EX0 CME SRAM SCRUB Setup]
+  WATCH=[REG(0x1001200C)]
+  WATCH=[REG(0x1001200B)]
+  CAUSE: TARGET=[REG(0x1001200C)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x1001200B)] OP=[BIT,ON] BIT=[49]
+  CAUSE: TARGET=[REG(0x1001200B)] OP=[BIT,ON] BIT=[50]
+  CAUSE: TARGET=[REG(0x1001200B)] OP=[BIT,ON] BIT=[51]
+  CAUSE: TARGET=[REG(0x1001200B)] OP=[BIT,ON] BIT=[52]
+  CAUSE: TARGET=[REG(0x1001200B)] OP=[BIT,ON] BIT=[53]
+  CAUSE: TARGET=[REG(0x1001200B)] OP=[BIT,ON] BIT=[54]
+  CAUSE: TARGET=[REG(0x1001200B)] OP=[BIT,ON] BIT=[55]
+  CAUSE: TARGET=[REG(0x1001200B)] OP=[BIT,ON] BIT=[56]
+  CAUSE: TARGET=[REG(0x1001200B)] OP=[BIT,ON] BIT=[57]
+  CAUSE: TARGET=[REG(0x1001200B)] OP=[BIT,ON] BIT=[58]
+  CAUSE: TARGET=[REG(0x1001200B)] OP=[BIT,ON] BIT=[59]
+  EFFECT: TARGET=[REG(0x1001200A)] OP=[BIT,ON] BIT=[1]
+  EFFECT: TARGET=[REG(0x1001200A)] OP=[BIT,OFF] BIT=[49]
+  EFFECT: TARGET=[REG(0x1001200A)] OP=[BIT,OFF] BIT=[50]
+  EFFECT: TARGET=[REG(0x1001200A)] OP=[BIT,OFF] BIT=[51]
+  EFFECT: TARGET=[REG(0x1001200A)] OP=[BIT,OFF] BIT=[52]
+  EFFECT: TARGET=[REG(0x1001200A)] OP=[BIT,OFF] BIT=[53]
+  EFFECT: TARGET=[REG(0x1001200A)] OP=[BIT,OFF] BIT=[54]
+  EFFECT: TARGET=[REG(0x1001200A)] OP=[BIT,OFF] BIT=[55]
+  EFFECT: TARGET=[REG(0x1001200A)] OP=[BIT,OFF] BIT=[56]
+  EFFECT: TARGET=[REG(0x1001200A)] OP=[BIT,OFF] BIT=[57]
+  EFFECT: TARGET=[REG(0x1001200A)] OP=[BIT,OFF] BIT=[58]
+  EFFECT: TARGET=[REG(0x1001200A)] OP=[BIT,OFF] BIT=[59]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX1 CME SRAM SCRUB Setup]
+  WATCH=[REG(0x1001240C)]
+  WATCH=[REG(0x1001240B)]
+  CAUSE: TARGET=[REG(0x1001240C)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x1001240B)] OP=[BIT,ON] BIT=[49]
+  CAUSE: TARGET=[REG(0x1001240B)] OP=[BIT,ON] BIT=[50]
+  CAUSE: TARGET=[REG(0x1001240B)] OP=[BIT,ON] BIT=[51]
+  CAUSE: TARGET=[REG(0x1001240B)] OP=[BIT,ON] BIT=[52]
+  CAUSE: TARGET=[REG(0x1001240B)] OP=[BIT,ON] BIT=[53]
+  CAUSE: TARGET=[REG(0x1001240B)] OP=[BIT,ON] BIT=[54]
+  CAUSE: TARGET=[REG(0x1001240B)] OP=[BIT,ON] BIT=[55]
+  CAUSE: TARGET=[REG(0x1001240B)] OP=[BIT,ON] BIT=[56]
+  CAUSE: TARGET=[REG(0x1001240B)] OP=[BIT,ON] BIT=[57]
+  CAUSE: TARGET=[REG(0x1001240B)] OP=[BIT,ON] BIT=[58]
+  CAUSE: TARGET=[REG(0x1001240B)] OP=[BIT,ON] BIT=[59]
+  EFFECT: TARGET=[REG(0x1001240A)] OP=[BIT,ON] BIT=[1]
+  EFFECT: TARGET=[REG(0x1001240A)] OP=[BIT,OFF] BIT=[49]
+  EFFECT: TARGET=[REG(0x1001240A)] OP=[BIT,OFF] BIT=[50]
+  EFFECT: TARGET=[REG(0x1001240A)] OP=[BIT,OFF] BIT=[51]
+  EFFECT: TARGET=[REG(0x1001240A)] OP=[BIT,OFF] BIT=[52]
+  EFFECT: TARGET=[REG(0x1001240A)] OP=[BIT,OFF] BIT=[53]
+  EFFECT: TARGET=[REG(0x1001240A)] OP=[BIT,OFF] BIT=[54]
+  EFFECT: TARGET=[REG(0x1001240A)] OP=[BIT,OFF] BIT=[55]
+  EFFECT: TARGET=[REG(0x1001240A)] OP=[BIT,OFF] BIT=[56]
+  EFFECT: TARGET=[REG(0x1001240A)] OP=[BIT,OFF] BIT=[57]
+  EFFECT: TARGET=[REG(0x1001240A)] OP=[BIT,OFF] BIT=[58]
+  EFFECT: TARGET=[REG(0x1001240A)] OP=[BIT,OFF] BIT=[59]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX2 CME SRAM SCRUB Setup]
+  WATCH=[REG(0x1101200C)]
+  WATCH=[REG(0x1101200B)]
+  CAUSE: TARGET=[REG(0x1101200C)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x1101200B)] OP=[BIT,ON] BIT=[49]
+  CAUSE: TARGET=[REG(0x1101200B)] OP=[BIT,ON] BIT=[50]
+  CAUSE: TARGET=[REG(0x1101200B)] OP=[BIT,ON] BIT=[51]
+  CAUSE: TARGET=[REG(0x1101200B)] OP=[BIT,ON] BIT=[52]
+  CAUSE: TARGET=[REG(0x1101200B)] OP=[BIT,ON] BIT=[53]
+  CAUSE: TARGET=[REG(0x1101200B)] OP=[BIT,ON] BIT=[54]
+  CAUSE: TARGET=[REG(0x1101200B)] OP=[BIT,ON] BIT=[55]
+  CAUSE: TARGET=[REG(0x1101200B)] OP=[BIT,ON] BIT=[56]
+  CAUSE: TARGET=[REG(0x1101200B)] OP=[BIT,ON] BIT=[57]
+  CAUSE: TARGET=[REG(0x1101200B)] OP=[BIT,ON] BIT=[58]
+  CAUSE: TARGET=[REG(0x1101200B)] OP=[BIT,ON] BIT=[59]
+  EFFECT: TARGET=[REG(0x1101200A)] OP=[BIT,ON] BIT=[1]
+  EFFECT: TARGET=[REG(0x1101200A)] OP=[BIT,OFF] BIT=[49]
+  EFFECT: TARGET=[REG(0x1101200A)] OP=[BIT,OFF] BIT=[50]
+  EFFECT: TARGET=[REG(0x1101200A)] OP=[BIT,OFF] BIT=[51]
+  EFFECT: TARGET=[REG(0x1101200A)] OP=[BIT,OFF] BIT=[52]
+  EFFECT: TARGET=[REG(0x1101200A)] OP=[BIT,OFF] BIT=[53]
+  EFFECT: TARGET=[REG(0x1101200A)] OP=[BIT,OFF] BIT=[54]
+  EFFECT: TARGET=[REG(0x1101200A)] OP=[BIT,OFF] BIT=[55]
+  EFFECT: TARGET=[REG(0x1101200A)] OP=[BIT,OFF] BIT=[56]
+  EFFECT: TARGET=[REG(0x1101200A)] OP=[BIT,OFF] BIT=[57]
+  EFFECT: TARGET=[REG(0x1101200A)] OP=[BIT,OFF] BIT=[58]
+  EFFECT: TARGET=[REG(0x1101200A)] OP=[BIT,OFF] BIT=[59]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX3 CME SRAM SCRUB Setup]
+  WATCH=[REG(0x1101240C)]
+  WATCH=[REG(0x1101240B)]
+  CAUSE: TARGET=[REG(0x1101240C)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x1101240B)] OP=[BIT,ON] BIT=[49]
+  CAUSE: TARGET=[REG(0x1101240B)] OP=[BIT,ON] BIT=[50]
+  CAUSE: TARGET=[REG(0x1101240B)] OP=[BIT,ON] BIT=[51]
+  CAUSE: TARGET=[REG(0x1101240B)] OP=[BIT,ON] BIT=[52]
+  CAUSE: TARGET=[REG(0x1101240B)] OP=[BIT,ON] BIT=[53]
+  CAUSE: TARGET=[REG(0x1101240B)] OP=[BIT,ON] BIT=[54]
+  CAUSE: TARGET=[REG(0x1101240B)] OP=[BIT,ON] BIT=[55]
+  CAUSE: TARGET=[REG(0x1101240B)] OP=[BIT,ON] BIT=[56]
+  CAUSE: TARGET=[REG(0x1101240B)] OP=[BIT,ON] BIT=[57]
+  CAUSE: TARGET=[REG(0x1101240B)] OP=[BIT,ON] BIT=[58]
+  CAUSE: TARGET=[REG(0x1101240B)] OP=[BIT,ON] BIT=[59]
+  EFFECT: TARGET=[REG(0x1101240A)] OP=[BIT,ON] BIT=[1]
+  EFFECT: TARGET=[REG(0x1101240A)] OP=[BIT,OFF] BIT=[49]
+  EFFECT: TARGET=[REG(0x1101240A)] OP=[BIT,OFF] BIT=[50]
+  EFFECT: TARGET=[REG(0x1101240A)] OP=[BIT,OFF] BIT=[51]
+  EFFECT: TARGET=[REG(0x1101240A)] OP=[BIT,OFF] BIT=[52]
+  EFFECT: TARGET=[REG(0x1101240A)] OP=[BIT,OFF] BIT=[53]
+  EFFECT: TARGET=[REG(0x1101240A)] OP=[BIT,OFF] BIT=[54]
+  EFFECT: TARGET=[REG(0x1101240A)] OP=[BIT,OFF] BIT=[55]
+  EFFECT: TARGET=[REG(0x1101240A)] OP=[BIT,OFF] BIT=[56]
+  EFFECT: TARGET=[REG(0x1101240A)] OP=[BIT,OFF] BIT=[57]
+  EFFECT: TARGET=[REG(0x1101240A)] OP=[BIT,OFF] BIT=[58]
+  EFFECT: TARGET=[REG(0x1101240A)] OP=[BIT,OFF] BIT=[59]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX4 CME SRAM SCRUB Setup]
+  WATCH=[REG(0x1201200C)]
+  WATCH=[REG(0x1201200B)]
+  CAUSE: TARGET=[REG(0x1201200C)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x1201200B)] OP=[BIT,ON] BIT=[49]
+  CAUSE: TARGET=[REG(0x1201200B)] OP=[BIT,ON] BIT=[50]
+  CAUSE: TARGET=[REG(0x1201200B)] OP=[BIT,ON] BIT=[51]
+  CAUSE: TARGET=[REG(0x1201200B)] OP=[BIT,ON] BIT=[52]
+  CAUSE: TARGET=[REG(0x1201200B)] OP=[BIT,ON] BIT=[53]
+  CAUSE: TARGET=[REG(0x1201200B)] OP=[BIT,ON] BIT=[54]
+  CAUSE: TARGET=[REG(0x1201200B)] OP=[BIT,ON] BIT=[55]
+  CAUSE: TARGET=[REG(0x1201200B)] OP=[BIT,ON] BIT=[56]
+  CAUSE: TARGET=[REG(0x1201200B)] OP=[BIT,ON] BIT=[57]
+  CAUSE: TARGET=[REG(0x1201200B)] OP=[BIT,ON] BIT=[58]
+  CAUSE: TARGET=[REG(0x1201200B)] OP=[BIT,ON] BIT=[59]
+  EFFECT: TARGET=[REG(0x1201200A)] OP=[BIT,ON] BIT=[1]
+  EFFECT: TARGET=[REG(0x1201200A)] OP=[BIT,OFF] BIT=[49]
+  EFFECT: TARGET=[REG(0x1201200A)] OP=[BIT,OFF] BIT=[50]
+  EFFECT: TARGET=[REG(0x1201200A)] OP=[BIT,OFF] BIT=[51]
+  EFFECT: TARGET=[REG(0x1201200A)] OP=[BIT,OFF] BIT=[52]
+  EFFECT: TARGET=[REG(0x1201200A)] OP=[BIT,OFF] BIT=[53]
+  EFFECT: TARGET=[REG(0x1201200A)] OP=[BIT,OFF] BIT=[54]
+  EFFECT: TARGET=[REG(0x1201200A)] OP=[BIT,OFF] BIT=[55]
+  EFFECT: TARGET=[REG(0x1201200A)] OP=[BIT,OFF] BIT=[56]
+  EFFECT: TARGET=[REG(0x1201200A)] OP=[BIT,OFF] BIT=[57]
+  EFFECT: TARGET=[REG(0x1201200A)] OP=[BIT,OFF] BIT=[58]
+  EFFECT: TARGET=[REG(0x1201200A)] OP=[BIT,OFF] BIT=[59]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX5 CME SRAM SCRUB Setup]
+  WATCH=[REG(0x1201240C)]
+  WATCH=[REG(0x1201240B)]
+  CAUSE: TARGET=[REG(0x1201240C)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x1201240B)] OP=[BIT,ON] BIT=[49]
+  CAUSE: TARGET=[REG(0x1201240B)] OP=[BIT,ON] BIT=[50]
+  CAUSE: TARGET=[REG(0x1201240B)] OP=[BIT,ON] BIT=[51]
+  CAUSE: TARGET=[REG(0x1201240B)] OP=[BIT,ON] BIT=[52]
+  CAUSE: TARGET=[REG(0x1201240B)] OP=[BIT,ON] BIT=[53]
+  CAUSE: TARGET=[REG(0x1201240B)] OP=[BIT,ON] BIT=[54]
+  CAUSE: TARGET=[REG(0x1201240B)] OP=[BIT,ON] BIT=[55]
+  CAUSE: TARGET=[REG(0x1201240B)] OP=[BIT,ON] BIT=[56]
+  CAUSE: TARGET=[REG(0x1201240B)] OP=[BIT,ON] BIT=[57]
+  CAUSE: TARGET=[REG(0x1201240B)] OP=[BIT,ON] BIT=[58]
+  CAUSE: TARGET=[REG(0x1201240B)] OP=[BIT,ON] BIT=[59]
+  EFFECT: TARGET=[REG(0x1201240A)] OP=[BIT,ON] BIT=[1]
+  EFFECT: TARGET=[REG(0x1201240A)] OP=[BIT,OFF] BIT=[49]
+  EFFECT: TARGET=[REG(0x1201240A)] OP=[BIT,OFF] BIT=[50]
+  EFFECT: TARGET=[REG(0x1201240A)] OP=[BIT,OFF] BIT=[51]
+  EFFECT: TARGET=[REG(0x1201240A)] OP=[BIT,OFF] BIT=[52]
+  EFFECT: TARGET=[REG(0x1201240A)] OP=[BIT,OFF] BIT=[53]
+  EFFECT: TARGET=[REG(0x1201240A)] OP=[BIT,OFF] BIT=[54]
+  EFFECT: TARGET=[REG(0x1201240A)] OP=[BIT,OFF] BIT=[55]
+  EFFECT: TARGET=[REG(0x1201240A)] OP=[BIT,OFF] BIT=[56]
+  EFFECT: TARGET=[REG(0x1201240A)] OP=[BIT,OFF] BIT=[57]
+  EFFECT: TARGET=[REG(0x1201240A)] OP=[BIT,OFF] BIT=[58]
+  EFFECT: TARGET=[REG(0x1201240A)] OP=[BIT,OFF] BIT=[59]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX6 CME SRAM SCRUB Setup]
+  WATCH=[REG(0x1301200C)]
+  WATCH=[REG(0x1301200B)]
+  CAUSE: TARGET=[REG(0x1301200C)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x1301200B)] OP=[BIT,ON] BIT=[49]
+  CAUSE: TARGET=[REG(0x1301200B)] OP=[BIT,ON] BIT=[50]
+  CAUSE: TARGET=[REG(0x1301200B)] OP=[BIT,ON] BIT=[51]
+  CAUSE: TARGET=[REG(0x1301200B)] OP=[BIT,ON] BIT=[52]
+  CAUSE: TARGET=[REG(0x1301200B)] OP=[BIT,ON] BIT=[53]
+  CAUSE: TARGET=[REG(0x1301200B)] OP=[BIT,ON] BIT=[54]
+  CAUSE: TARGET=[REG(0x1301200B)] OP=[BIT,ON] BIT=[55]
+  CAUSE: TARGET=[REG(0x1301200B)] OP=[BIT,ON] BIT=[56]
+  CAUSE: TARGET=[REG(0x1301200B)] OP=[BIT,ON] BIT=[57]
+  CAUSE: TARGET=[REG(0x1301200B)] OP=[BIT,ON] BIT=[58]
+  CAUSE: TARGET=[REG(0x1301200B)] OP=[BIT,ON] BIT=[59]
+  EFFECT: TARGET=[REG(0x1301200A)] OP=[BIT,ON] BIT=[1]
+  EFFECT: TARGET=[REG(0x1301200A)] OP=[BIT,OFF] BIT=[49]
+  EFFECT: TARGET=[REG(0x1301200A)] OP=[BIT,OFF] BIT=[50]
+  EFFECT: TARGET=[REG(0x1301200A)] OP=[BIT,OFF] BIT=[51]
+  EFFECT: TARGET=[REG(0x1301200A)] OP=[BIT,OFF] BIT=[52]
+  EFFECT: TARGET=[REG(0x1301200A)] OP=[BIT,OFF] BIT=[53]
+  EFFECT: TARGET=[REG(0x1301200A)] OP=[BIT,OFF] BIT=[54]
+  EFFECT: TARGET=[REG(0x1301200A)] OP=[BIT,OFF] BIT=[55]
+  EFFECT: TARGET=[REG(0x1301200A)] OP=[BIT,OFF] BIT=[56]
+  EFFECT: TARGET=[REG(0x1301200A)] OP=[BIT,OFF] BIT=[57]
+  EFFECT: TARGET=[REG(0x1301200A)] OP=[BIT,OFF] BIT=[58]
+  EFFECT: TARGET=[REG(0x1301200A)] OP=[BIT,OFF] BIT=[59]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX7 CME SRAM SCRUB Setup]
+  WATCH=[REG(0x1301240C)]
+  WATCH=[REG(0x1301240B)]
+  CAUSE: TARGET=[REG(0x1301240C)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x1301240B)] OP=[BIT,ON] BIT=[49]
+  CAUSE: TARGET=[REG(0x1301240B)] OP=[BIT,ON] BIT=[50]
+  CAUSE: TARGET=[REG(0x1301240B)] OP=[BIT,ON] BIT=[51]
+  CAUSE: TARGET=[REG(0x1301240B)] OP=[BIT,ON] BIT=[52]
+  CAUSE: TARGET=[REG(0x1301240B)] OP=[BIT,ON] BIT=[53]
+  CAUSE: TARGET=[REG(0x1301240B)] OP=[BIT,ON] BIT=[54]
+  CAUSE: TARGET=[REG(0x1301240B)] OP=[BIT,ON] BIT=[55]
+  CAUSE: TARGET=[REG(0x1301240B)] OP=[BIT,ON] BIT=[56]
+  CAUSE: TARGET=[REG(0x1301240B)] OP=[BIT,ON] BIT=[57]
+  CAUSE: TARGET=[REG(0x1301240B)] OP=[BIT,ON] BIT=[58]
+  CAUSE: TARGET=[REG(0x1301240B)] OP=[BIT,ON] BIT=[59]
+  EFFECT: TARGET=[REG(0x1301240A)] OP=[BIT,ON] BIT=[1]
+  EFFECT: TARGET=[REG(0x1301240A)] OP=[BIT,OFF] BIT=[49]
+  EFFECT: TARGET=[REG(0x1301240A)] OP=[BIT,OFF] BIT=[50]
+  EFFECT: TARGET=[REG(0x1301240A)] OP=[BIT,OFF] BIT=[51]
+  EFFECT: TARGET=[REG(0x1301240A)] OP=[BIT,OFF] BIT=[52]
+  EFFECT: TARGET=[REG(0x1301240A)] OP=[BIT,OFF] BIT=[53]
+  EFFECT: TARGET=[REG(0x1301240A)] OP=[BIT,OFF] BIT=[54]
+  EFFECT: TARGET=[REG(0x1301240A)] OP=[BIT,OFF] BIT=[55]
+  EFFECT: TARGET=[REG(0x1301240A)] OP=[BIT,OFF] BIT=[56]
+  EFFECT: TARGET=[REG(0x1301240A)] OP=[BIT,OFF] BIT=[57]
+  EFFECT: TARGET=[REG(0x1301240A)] OP=[BIT,OFF] BIT=[58]
+  EFFECT: TARGET=[REG(0x1301240A)] OP=[BIT,OFF] BIT=[59]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX8 CME SRAM SCRUB Setup]
+  WATCH=[REG(0x1401200C)]
+  WATCH=[REG(0x1401200B)]
+  CAUSE: TARGET=[REG(0x1401200C)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x1401200B)] OP=[BIT,ON] BIT=[49]
+  CAUSE: TARGET=[REG(0x1401200B)] OP=[BIT,ON] BIT=[50]
+  CAUSE: TARGET=[REG(0x1401200B)] OP=[BIT,ON] BIT=[51]
+  CAUSE: TARGET=[REG(0x1401200B)] OP=[BIT,ON] BIT=[52]
+  CAUSE: TARGET=[REG(0x1401200B)] OP=[BIT,ON] BIT=[53]
+  CAUSE: TARGET=[REG(0x1401200B)] OP=[BIT,ON] BIT=[54]
+  CAUSE: TARGET=[REG(0x1401200B)] OP=[BIT,ON] BIT=[55]
+  CAUSE: TARGET=[REG(0x1401200B)] OP=[BIT,ON] BIT=[56]
+  CAUSE: TARGET=[REG(0x1401200B)] OP=[BIT,ON] BIT=[57]
+  CAUSE: TARGET=[REG(0x1401200B)] OP=[BIT,ON] BIT=[58]
+  CAUSE: TARGET=[REG(0x1401200B)] OP=[BIT,ON] BIT=[59]
+  EFFECT: TARGET=[REG(0x1401200A)] OP=[BIT,ON] BIT=[1]
+  EFFECT: TARGET=[REG(0x1401200A)] OP=[BIT,OFF] BIT=[49]
+  EFFECT: TARGET=[REG(0x1401200A)] OP=[BIT,OFF] BIT=[50]
+  EFFECT: TARGET=[REG(0x1401200A)] OP=[BIT,OFF] BIT=[51]
+  EFFECT: TARGET=[REG(0x1401200A)] OP=[BIT,OFF] BIT=[52]
+  EFFECT: TARGET=[REG(0x1401200A)] OP=[BIT,OFF] BIT=[53]
+  EFFECT: TARGET=[REG(0x1401200A)] OP=[BIT,OFF] BIT=[54]
+  EFFECT: TARGET=[REG(0x1401200A)] OP=[BIT,OFF] BIT=[55]
+  EFFECT: TARGET=[REG(0x1401200A)] OP=[BIT,OFF] BIT=[56]
+  EFFECT: TARGET=[REG(0x1401200A)] OP=[BIT,OFF] BIT=[57]
+  EFFECT: TARGET=[REG(0x1401200A)] OP=[BIT,OFF] BIT=[58]
+  EFFECT: TARGET=[REG(0x1401200A)] OP=[BIT,OFF] BIT=[59]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX9 CME SRAM SCRUB Setup]
+  WATCH=[REG(0x1401240C)]
+  WATCH=[REG(0x1401240B)]
+  CAUSE: TARGET=[REG(0x1401240C)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x1401240B)] OP=[BIT,ON] BIT=[49]
+  CAUSE: TARGET=[REG(0x1401240B)] OP=[BIT,ON] BIT=[50]
+  CAUSE: TARGET=[REG(0x1401240B)] OP=[BIT,ON] BIT=[51]
+  CAUSE: TARGET=[REG(0x1401240B)] OP=[BIT,ON] BIT=[52]
+  CAUSE: TARGET=[REG(0x1401240B)] OP=[BIT,ON] BIT=[53]
+  CAUSE: TARGET=[REG(0x1401240B)] OP=[BIT,ON] BIT=[54]
+  CAUSE: TARGET=[REG(0x1401240B)] OP=[BIT,ON] BIT=[55]
+  CAUSE: TARGET=[REG(0x1401240B)] OP=[BIT,ON] BIT=[56]
+  CAUSE: TARGET=[REG(0x1401240B)] OP=[BIT,ON] BIT=[57]
+  CAUSE: TARGET=[REG(0x1401240B)] OP=[BIT,ON] BIT=[58]
+  CAUSE: TARGET=[REG(0x1401240B)] OP=[BIT,ON] BIT=[59]
+  EFFECT: TARGET=[REG(0x1401240A)] OP=[BIT,ON] BIT=[1]
+  EFFECT: TARGET=[REG(0x1401240A)] OP=[BIT,OFF] BIT=[49]
+  EFFECT: TARGET=[REG(0x1401240A)] OP=[BIT,OFF] BIT=[50]
+  EFFECT: TARGET=[REG(0x1401240A)] OP=[BIT,OFF] BIT=[51]
+  EFFECT: TARGET=[REG(0x1401240A)] OP=[BIT,OFF] BIT=[52]
+  EFFECT: TARGET=[REG(0x1401240A)] OP=[BIT,OFF] BIT=[53]
+  EFFECT: TARGET=[REG(0x1401240A)] OP=[BIT,OFF] BIT=[54]
+  EFFECT: TARGET=[REG(0x1401240A)] OP=[BIT,OFF] BIT=[55]
+  EFFECT: TARGET=[REG(0x1401240A)] OP=[BIT,OFF] BIT=[56]
+  EFFECT: TARGET=[REG(0x1401240A)] OP=[BIT,OFF] BIT=[57]
+  EFFECT: TARGET=[REG(0x1401240A)] OP=[BIT,OFF] BIT=[58]
+  EFFECT: TARGET=[REG(0x1401240A)] OP=[BIT,OFF] BIT=[59]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX10 CME SRAM SCRUB Setup]
+  WATCH=[REG(0x1501200C)]
+  WATCH=[REG(0x1501200B)]
+  CAUSE: TARGET=[REG(0x1501200C)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x1501200B)] OP=[BIT,ON] BIT=[49]
+  CAUSE: TARGET=[REG(0x1501200B)] OP=[BIT,ON] BIT=[50]
+  CAUSE: TARGET=[REG(0x1501200B)] OP=[BIT,ON] BIT=[51]
+  CAUSE: TARGET=[REG(0x1501200B)] OP=[BIT,ON] BIT=[52]
+  CAUSE: TARGET=[REG(0x1501200B)] OP=[BIT,ON] BIT=[53]
+  CAUSE: TARGET=[REG(0x1501200B)] OP=[BIT,ON] BIT=[54]
+  CAUSE: TARGET=[REG(0x1501200B)] OP=[BIT,ON] BIT=[55]
+  CAUSE: TARGET=[REG(0x1501200B)] OP=[BIT,ON] BIT=[56]
+  CAUSE: TARGET=[REG(0x1501200B)] OP=[BIT,ON] BIT=[57]
+  CAUSE: TARGET=[REG(0x1501200B)] OP=[BIT,ON] BIT=[58]
+  CAUSE: TARGET=[REG(0x1501200B)] OP=[BIT,ON] BIT=[59]
+  EFFECT: TARGET=[REG(0x1501200A)] OP=[BIT,ON] BIT=[1]
+  EFFECT: TARGET=[REG(0x1501200A)] OP=[BIT,OFF] BIT=[49]
+  EFFECT: TARGET=[REG(0x1501200A)] OP=[BIT,OFF] BIT=[50]
+  EFFECT: TARGET=[REG(0x1501200A)] OP=[BIT,OFF] BIT=[51]
+  EFFECT: TARGET=[REG(0x1501200A)] OP=[BIT,OFF] BIT=[52]
+  EFFECT: TARGET=[REG(0x1501200A)] OP=[BIT,OFF] BIT=[53]
+  EFFECT: TARGET=[REG(0x1501200A)] OP=[BIT,OFF] BIT=[54]
+  EFFECT: TARGET=[REG(0x1501200A)] OP=[BIT,OFF] BIT=[55]
+  EFFECT: TARGET=[REG(0x1501200A)] OP=[BIT,OFF] BIT=[56]
+  EFFECT: TARGET=[REG(0x1501200A)] OP=[BIT,OFF] BIT=[57]
+  EFFECT: TARGET=[REG(0x1501200A)] OP=[BIT,OFF] BIT=[58]
+  EFFECT: TARGET=[REG(0x1501200A)] OP=[BIT,OFF] BIT=[59]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX11 CME SRAM SCRUB Setup]
+  WATCH=[REG(0x1501240C)]
+  WATCH=[REG(0x1501240B)]
+  CAUSE: TARGET=[REG(0x1501240C)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x1501240B)] OP=[BIT,ON] BIT=[49]
+  CAUSE: TARGET=[REG(0x1501240B)] OP=[BIT,ON] BIT=[50]
+  CAUSE: TARGET=[REG(0x1501240B)] OP=[BIT,ON] BIT=[51]
+  CAUSE: TARGET=[REG(0x1501240B)] OP=[BIT,ON] BIT=[52]
+  CAUSE: TARGET=[REG(0x1501240B)] OP=[BIT,ON] BIT=[53]
+  CAUSE: TARGET=[REG(0x1501240B)] OP=[BIT,ON] BIT=[54]
+  CAUSE: TARGET=[REG(0x1501240B)] OP=[BIT,ON] BIT=[55]
+  CAUSE: TARGET=[REG(0x1501240B)] OP=[BIT,ON] BIT=[56]
+  CAUSE: TARGET=[REG(0x1501240B)] OP=[BIT,ON] BIT=[57]
+  CAUSE: TARGET=[REG(0x1501240B)] OP=[BIT,ON] BIT=[58]
+  CAUSE: TARGET=[REG(0x1501240B)] OP=[BIT,ON] BIT=[59]
+  EFFECT: TARGET=[REG(0x1501240A)] OP=[BIT,ON] BIT=[1]
+  EFFECT: TARGET=[REG(0x1501240A)] OP=[BIT,OFF] BIT=[49]
+  EFFECT: TARGET=[REG(0x1501240A)] OP=[BIT,OFF] BIT=[50]
+  EFFECT: TARGET=[REG(0x1501240A)] OP=[BIT,OFF] BIT=[51]
+  EFFECT: TARGET=[REG(0x1501240A)] OP=[BIT,OFF] BIT=[52]
+  EFFECT: TARGET=[REG(0x1501240A)] OP=[BIT,OFF] BIT=[53]
+  EFFECT: TARGET=[REG(0x1501240A)] OP=[BIT,OFF] BIT=[54]
+  EFFECT: TARGET=[REG(0x1501240A)] OP=[BIT,OFF] BIT=[55]
+  EFFECT: TARGET=[REG(0x1501240A)] OP=[BIT,OFF] BIT=[56]
+  EFFECT: TARGET=[REG(0x1501240A)] OP=[BIT,OFF] BIT=[57]
+  EFFECT: TARGET=[REG(0x1501240A)] OP=[BIT,OFF] BIT=[58]
+  EFFECT: TARGET=[REG(0x1501240A)] OP=[BIT,OFF] BIT=[59]
+}
+
+# CME FIR MASK
+CAUSE_EFFECT {
+  LABEL=[EX0 CME FIR MASK Setup]
+  WATCH=[REG(0x10012005)]
+  EFFECT: TARGET=[REG(0x10012003)] OP=[EQUALTO,BUF] DATA=[REG(0x10012005)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX1 CME FIR MASK Setup]
+  WATCH=[REG(0x10012405)]
+  EFFECT: TARGET=[REG(0x10012403)] OP=[EQUALTO,BUF] DATA=[REG(0x10012405)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX2 CME FIR MASK Setup]
+  WATCH=[REG(0x11012005)]
+  EFFECT: TARGET=[REG(0x11012003)] OP=[EQUALTO,BUF] DATA=[REG(0x11012005)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX3 CME FIR MASK Setup]
+  WATCH=[REG(0x11012405)]
+  EFFECT: TARGET=[REG(0x11012403)] OP=[EQUALTO,BUF] DATA=[REG(0x11012405)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX4 CME FIR MASK Setup]
+  WATCH=[REG(0x12012005)]
+  EFFECT: TARGET=[REG(0x12012003)] OP=[EQUALTO,BUF] DATA=[REG(0x12012005)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX5 CME FIR MASK Setup]
+  WATCH=[REG(0x12012405)]
+  EFFECT: TARGET=[REG(0x12012403)] OP=[EQUALTO,BUF] DATA=[REG(0x12012405)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX6 CME FIR MASK Setup]
+  WATCH=[REG(0x13012005)]
+  EFFECT: TARGET=[REG(0x13012003)] OP=[EQUALTO,BUF] DATA=[REG(0x13012005)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX7 CME FIR MASK Setup]
+  WATCH=[REG(0x13012405)]
+  EFFECT: TARGET=[REG(0x13012403)] OP=[EQUALTO,BUF] DATA=[REG(0x13012405)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX8 CME FIR MASK Setup]
+  WATCH=[REG(0x14012005)]
+  EFFECT: TARGET=[REG(0x14012003)] OP=[EQUALTO,BUF] DATA=[REG(0x14012005)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX9 CME FIR MASK Setup]
+  WATCH=[REG(0x14012405)]
+  EFFECT: TARGET=[REG(0x14012403)] OP=[EQUALTO,BUF] DATA=[REG(0x14012405)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX10 CME FIR MASK Setup]
+  WATCH=[REG(0x15012005)]
+  EFFECT: TARGET=[REG(0x15012003)] OP=[EQUALTO,BUF] DATA=[REG(0x15012005)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX11 CME FIR MASK Setup]
+  WATCH=[REG(0x15012405)]
+  EFFECT: TARGET=[REG(0x15012403)] OP=[EQUALTO,BUF] DATA=[REG(0x15012405)]
+}
+
+
+# Clear Doorbells 0
+CAUSE_EFFECT {
+  LABEL=[Core0 Doorbell0 clear]
+  WATCH=[REG(0x200F0191)]
+  CAUSE: TARGET=[REG(0x200F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x200F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core1 Doorbell0 clear]
+  WATCH=[REG(0x210F0191)]
+  CAUSE: TARGET=[REG(0x210F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x210F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core2 Doorbell0 clear]
+  WATCH=[REG(0x220F0191)]
+  CAUSE: TARGET=[REG(0x220F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x220F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core3 Doorbell0 clear]
+  WATCH=[REG(0x230F0191)]
+  CAUSE: TARGET=[REG(0x230F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x230F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core4 Doorbell0 clear]
+  WATCH=[REG(0x240F0191)]
+  CAUSE: TARGET=[REG(0x240F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x240F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core5 Doorbell0 clear]
+  WATCH=[REG(0x250F0191)]
+  CAUSE: TARGET=[REG(0x250F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x250F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core6 Doorbell0 clear]
+  WATCH=[REG(0x260F0191)]
+  CAUSE: TARGET=[REG(0x260F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x260F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core7 Doorbell0 clear]
+  WATCH=[REG(0x270F0191)]
+  CAUSE: TARGET=[REG(0x270F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x270F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core8 Doorbell0 clear]
+  WATCH=[REG(0x280F0191)]
+  CAUSE: TARGET=[REG(0x280F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x280F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core9 Doorbell0 clear]
+  WATCH=[REG(0x290F0191)]
+  CAUSE: TARGET=[REG(0x290F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x290F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core10 Doorbell0 clear]
+  WATCH=[REG(0x2A0F0191)]
+  CAUSE: TARGET=[REG(0x2A0F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2A0F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core11 Doorbell0 clear]
+  WATCH=[REG(0x2B0F0191)]
+  CAUSE: TARGET=[REG(0x2B0F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2B0F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core12 Doorbell0 clear]
+  WATCH=[REG(0x2C0F0191)]
+  CAUSE: TARGET=[REG(0x2C0F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2C0F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core13 Doorbell0 clear]
+  WATCH=[REG(0x2D0F0191)]
+  CAUSE: TARGET=[REG(0x2D0F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2D0F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core14 Doorbell0 clear]
+  WATCH=[REG(0x2E0F0191)]
+  CAUSE: TARGET=[REG(0x2E0F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2E0F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core15 Doorbell0 clear]
+  WATCH=[REG(0x2F0F0191)]
+  CAUSE: TARGET=[REG(0x2F0F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2F0F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core16 Doorbell0 clear]
+  WATCH=[REG(0x300F0191)]
+  CAUSE: TARGET=[REG(0x300F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x300F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core17 Doorbell0 clear]
+  WATCH=[REG(0x310F0191)]
+  CAUSE: TARGET=[REG(0x310F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x310F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core18 Doorbell0 clear]
+  WATCH=[REG(0x320F0191)]
+  CAUSE: TARGET=[REG(0x320F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x320F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core19 Doorbell0 clear]
+  WATCH=[REG(0x330F0191)]
+  CAUSE: TARGET=[REG(0x330F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x330F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core20 Doorbell0 clear]
+  WATCH=[REG(0x340F0191)]
+  CAUSE: TARGET=[REG(0x340F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x340F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core21 Doorbell0 clear]
+  WATCH=[REG(0x350F0191)]
+  CAUSE: TARGET=[REG(0x350F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x350F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core22 Doorbell0 clear]
+  WATCH=[REG(0x360F0191)]
+  CAUSE: TARGET=[REG(0x360F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x360F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core23 Doorbell0 clear]
+  WATCH=[REG(0x370F0191)]
+  CAUSE: TARGET=[REG(0x370F0191)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x370F0190)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+# Clear Doorbells 1
+CAUSE_EFFECT {
+  LABEL=[Core0 Doorbell1 clear]
+  WATCH=[REG(0x200F0195)]
+  CAUSE: TARGET=[REG(0x200F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x200F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core1 Doorbell1 clear]
+  WATCH=[REG(0x210F0195)]
+  CAUSE: TARGET=[REG(0x210F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x210F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core2 Doorbell1 clear]
+  WATCH=[REG(0x220F0195)]
+  CAUSE: TARGET=[REG(0x220F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x220F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core3 Doorbell1 clear]
+  WATCH=[REG(0x230F0195)]
+  CAUSE: TARGET=[REG(0x230F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x230F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core4 Doorbell1 clear]
+  WATCH=[REG(0x240F0195)]
+  CAUSE: TARGET=[REG(0x240F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x240F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core5 Doorbell1 clear]
+  WATCH=[REG(0x250F0195)]
+  CAUSE: TARGET=[REG(0x250F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x250F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core6 Doorbell1 clear]
+  WATCH=[REG(0x260F0195)]
+  CAUSE: TARGET=[REG(0x260F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x260F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core7 Doorbell1 clear]
+  WATCH=[REG(0x270F0195)]
+  CAUSE: TARGET=[REG(0x270F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x270F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core8 Doorbell1 clear]
+  WATCH=[REG(0x280F0195)]
+  CAUSE: TARGET=[REG(0x280F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x280F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core9 Doorbell1 clear]
+  WATCH=[REG(0x290F0195)]
+  CAUSE: TARGET=[REG(0x290F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x290F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core10 Doorbell1 clear]
+  WATCH=[REG(0x2A0F0195)]
+  CAUSE: TARGET=[REG(0x2A0F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2A0F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core11 Doorbell1 clear]
+  WATCH=[REG(0x2B0F0195)]
+  CAUSE: TARGET=[REG(0x2B0F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2B0F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core12 Doorbell1 clear]
+  WATCH=[REG(0x2C0F0195)]
+  CAUSE: TARGET=[REG(0x2C0F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2C0F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core13 Doorbell1 clear]
+  WATCH=[REG(0x2D0F0195)]
+  CAUSE: TARGET=[REG(0x2D0F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2D0F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core14 Doorbell1 clear]
+  WATCH=[REG(0x2E0F0195)]
+  CAUSE: TARGET=[REG(0x2E0F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2E0F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core15 Doorbell1 clear]
+  WATCH=[REG(0x2F0F0195)]
+  CAUSE: TARGET=[REG(0x2F0F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2F0F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core16 Doorbell1 clear]
+  WATCH=[REG(0x300F0195)]
+  CAUSE: TARGET=[REG(0x300F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x300F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core17 Doorbell1 clear]
+  WATCH=[REG(0x310F0195)]
+  CAUSE: TARGET=[REG(0x310F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x310F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core18 Doorbell1 clear]
+  WATCH=[REG(0x320F0195)]
+  CAUSE: TARGET=[REG(0x320F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x320F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core19 Doorbell1 clear]
+  WATCH=[REG(0x330F0195)]
+  CAUSE: TARGET=[REG(0x330F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x330F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core20 Doorbell1 clear]
+  WATCH=[REG(0x340F0195)]
+  CAUSE: TARGET=[REG(0x340F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x340F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core21 Doorbell1 clear]
+  WATCH=[REG(0x350F0195)]
+  CAUSE: TARGET=[REG(0x350F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x350F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core22 Doorbell1 clear]
+  WATCH=[REG(0x360F0195)]
+  CAUSE: TARGET=[REG(0x360F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x360F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core23 Doorbell1 clear]
+  WATCH=[REG(0x370F0195)]
+  CAUSE: TARGET=[REG(0x370F0195)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x370F0194)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+# Clear Doorbells 2
+CAUSE_EFFECT {
+  LABEL=[Core0 Doorbell2 clear]
+  WATCH=[REG(0x200F0199)]
+  CAUSE: TARGET=[REG(0x200F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x200F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core1 Doorbell2 clear]
+  WATCH=[REG(0x210F0199)]
+  CAUSE: TARGET=[REG(0x210F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x210F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core2 Doorbell2 clear]
+  WATCH=[REG(0x220F0199)]
+  CAUSE: TARGET=[REG(0x220F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x220F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core3 Doorbell2 clear]
+  WATCH=[REG(0x230F0199)]
+  CAUSE: TARGET=[REG(0x230F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x230F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core4 Doorbell2 clear]
+  WATCH=[REG(0x240F0199)]
+  CAUSE: TARGET=[REG(0x240F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x240F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core5 Doorbell2 clear]
+  WATCH=[REG(0x250F0199)]
+  CAUSE: TARGET=[REG(0x250F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x250F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core6 Doorbell2 clear]
+  WATCH=[REG(0x260F0199)]
+  CAUSE: TARGET=[REG(0x260F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x260F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core7 Doorbell2 clear]
+  WATCH=[REG(0x270F0199)]
+  CAUSE: TARGET=[REG(0x270F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x270F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core8 Doorbell2 clear]
+  WATCH=[REG(0x280F0199)]
+  CAUSE: TARGET=[REG(0x280F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x280F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core9 Doorbell2 clear]
+  WATCH=[REG(0x290F0199)]
+  CAUSE: TARGET=[REG(0x290F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x290F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core10 Doorbell2 clear]
+  WATCH=[REG(0x2A0F0199)]
+  CAUSE: TARGET=[REG(0x2A0F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2A0F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core11 Doorbell2 clear]
+  WATCH=[REG(0x2B0F0199)]
+  CAUSE: TARGET=[REG(0x2B0F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2B0F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core12 Doorbell2 clear]
+  WATCH=[REG(0x2C0F0199)]
+  CAUSE: TARGET=[REG(0x2C0F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2C0F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core13 Doorbell2 clear]
+  WATCH=[REG(0x2D0F0199)]
+  CAUSE: TARGET=[REG(0x2D0F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2D0F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core14 Doorbell2 clear]
+  WATCH=[REG(0x2E0F0199)]
+  CAUSE: TARGET=[REG(0x2E0F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2E0F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core15 Doorbell2 clear]
+  WATCH=[REG(0x2F0F0199)]
+  CAUSE: TARGET=[REG(0x2F0F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2F0F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core16 Doorbell2 clear]
+  WATCH=[REG(0x300F0199)]
+  CAUSE: TARGET=[REG(0x300F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x300F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core17 Doorbell2 clear]
+  WATCH=[REG(0x310F0199)]
+  CAUSE: TARGET=[REG(0x310F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x310F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core18 Doorbell2 clear]
+  WATCH=[REG(0x320F0199)]
+  CAUSE: TARGET=[REG(0x320F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x320F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core19 Doorbell2 clear]
+  WATCH=[REG(0x330F0199)]
+  CAUSE: TARGET=[REG(0x330F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x330F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core20 Doorbell2 clear]
+  WATCH=[REG(0x340F0199)]
+  CAUSE: TARGET=[REG(0x340F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x340F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core21 Doorbell2 clear]
+  WATCH=[REG(0x350F0199)]
+  CAUSE: TARGET=[REG(0x350F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x350F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core22 Doorbell2 clear]
+  WATCH=[REG(0x360F0199)]
+  CAUSE: TARGET=[REG(0x360F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x360F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core23 Doorbell2 clear]
+  WATCH=[REG(0x370F0199)]
+  CAUSE: TARGET=[REG(0x370F0199)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x370F0198)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+# Clear Doorbells 3
+
+
+CAUSE_EFFECT {
+  LABEL=[Core0 Doorbell3 clear]
+  WATCH=[REG(0x200F019D)]
+  CAUSE: TARGET=[REG(0x200F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x200F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core1 Doorbell3 clear]
+  WATCH=[REG(0x210F019D)]
+  CAUSE: TARGET=[REG(0x210F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x210F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core2 Doorbell3 clear]
+  WATCH=[REG(0x220F019D)]
+  CAUSE: TARGET=[REG(0x220F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x220F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core3 Doorbell3 clear]
+  WATCH=[REG(0x230F019D)]
+  CAUSE: TARGET=[REG(0x230F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x230F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core4 Doorbell3 clear]
+  WATCH=[REG(0x240F019D)]
+  CAUSE: TARGET=[REG(0x240F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x240F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core5 Doorbell3 clear]
+  WATCH=[REG(0x250F019D)]
+  CAUSE: TARGET=[REG(0x250F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x250F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core6 Doorbell3 clear]
+  WATCH=[REG(0x260F019D)]
+  CAUSE: TARGET=[REG(0x260F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x260F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core7 Doorbell3 clear]
+  WATCH=[REG(0x270F019D)]
+  CAUSE: TARGET=[REG(0x270F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x270F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core8 Doorbell3 clear]
+  WATCH=[REG(0x280F019D)]
+  CAUSE: TARGET=[REG(0x280F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x280F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core9 Doorbell3 clear]
+  WATCH=[REG(0x290F019D)]
+  CAUSE: TARGET=[REG(0x290F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x290F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core10 Doorbell3 clear]
+  WATCH=[REG(0x2A0F019D)]
+  CAUSE: TARGET=[REG(0x2A0F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2A0F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core11 Doorbell3 clear]
+  WATCH=[REG(0x2B0F019D)]
+  CAUSE: TARGET=[REG(0x2B0F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2B0F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core12 Doorbell3 clear]
+  WATCH=[REG(0x2C0F019D)]
+  CAUSE: TARGET=[REG(0x2C0F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2C0F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core13 Doorbell3 clear]
+  WATCH=[REG(0x2D0F019D)]
+  CAUSE: TARGET=[REG(0x2D0F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2D0F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core14 Doorbell3 clear]
+  WATCH=[REG(0x2E0F019D)]
+  CAUSE: TARGET=[REG(0x2E0F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2E0F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core15 Doorbell3 clear]
+  WATCH=[REG(0x2F0F019D)]
+  CAUSE: TARGET=[REG(0x2F0F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x2F0F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core16 Doorbell3 clear]
+  WATCH=[REG(0x300F019D)]
+  CAUSE: TARGET=[REG(0x300F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x300F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core17 Doorbell3 clear]
+  WATCH=[REG(0x310F019D)]
+  CAUSE: TARGET=[REG(0x310F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x310F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core18 Doorbell3 clear]
+  WATCH=[REG(0x320F019D)]
+  CAUSE: TARGET=[REG(0x320F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x320F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core19 Doorbell3 clear]
+  WATCH=[REG(0x330F019D)]
+  CAUSE: TARGET=[REG(0x330F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x330F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core20 Doorbell3 clear]
+  WATCH=[REG(0x340F019D)]
+  CAUSE: TARGET=[REG(0x340F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x340F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core21 Doorbell3 clear]
+  WATCH=[REG(0x350F019D)]
+  CAUSE: TARGET=[REG(0x350F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x350F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core22 Doorbell3 clear]
+  WATCH=[REG(0x360F019D)]
+  CAUSE: TARGET=[REG(0x360F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x360F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core23 Doorbell3 clear]
+  WATCH=[REG(0x370F019D)]
+  CAUSE: TARGET=[REG(0x370F019D)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,FFFFFFFF FFFFFFFF)]
+  EFFECT: TARGET=[REG(0x370F019C)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+# Setup Core PPM Mode
+CAUSE_EFFECT {
+  LABEL=[Core0 PPM Mode Setup]
+  WATCH=[REG(0x200F0108)]
+  WATCH=[REG(0x200F0107)]
+  CAUSE: TARGET=[REG(0x200F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x200F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x200F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x200F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x200F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x200F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x200F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x200F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x200F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x200F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x200F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x200F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x200F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x200F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x200F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x200F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core1 PPM Mode Setup]
+  WATCH=[REG(0x210F0108)]
+  WATCH=[REG(0x210F0107)]
+  CAUSE: TARGET=[REG(0x210F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x210F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x210F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x210F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x210F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x210F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x210F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x210F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x210F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x210F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x210F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x210F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x210F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x210F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x210F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x210F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core2 PPM Mode Setup]
+  WATCH=[REG(0x220F0108)]
+  WATCH=[REG(0x220F0107)]
+  CAUSE: TARGET=[REG(0x220F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x220F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x220F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x220F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x220F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x220F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x220F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x220F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x220F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x220F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x220F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x220F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x220F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x220F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x220F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x220F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core3 PPM Mode Setup]
+  WATCH=[REG(0x230F0108)]
+  WATCH=[REG(0x230F0107)]
+  CAUSE: TARGET=[REG(0x230F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x230F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x230F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x230F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x230F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x230F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x230F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x230F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x230F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x230F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x230F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x230F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x230F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x230F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x230F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x230F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core4 PPM Mode Setup]
+  WATCH=[REG(0x240F0108)]
+  WATCH=[REG(0x240F0107)]
+  CAUSE: TARGET=[REG(0x240F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x240F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x240F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x240F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x240F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x240F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x240F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x240F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x240F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x240F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x240F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x240F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x240F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x240F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x240F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x240F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core5 PPM Mode Setup]
+  WATCH=[REG(0x250F0108)]
+  WATCH=[REG(0x250F0107)]
+  CAUSE: TARGET=[REG(0x250F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x250F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x250F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x250F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x250F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x250F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x250F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x250F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x250F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x250F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x250F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x250F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x250F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x250F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x250F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x250F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core6 PPM Mode Setup]
+  WATCH=[REG(0x260F0108)]
+  WATCH=[REG(0x260F0107)]
+  CAUSE: TARGET=[REG(0x260F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x260F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x260F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x260F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x260F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x260F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x260F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x260F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x260F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x260F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x260F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x260F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x260F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x260F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x260F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x260F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core7 PPM Mode Setup]
+  WATCH=[REG(0x270F0108)]
+  WATCH=[REG(0x270F0107)]
+  CAUSE: TARGET=[REG(0x270F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x270F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x270F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x270F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x270F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x270F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x270F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x270F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x270F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x270F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x270F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x270F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x270F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x270F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x270F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x270F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core8 PPM Mode Setup]
+  WATCH=[REG(0x280F0108)]
+  WATCH=[REG(0x280F0107)]
+  CAUSE: TARGET=[REG(0x280F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x280F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x280F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x280F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x280F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x280F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x280F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x280F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x280F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x280F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x280F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x280F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x280F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x280F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x280F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x280F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core9 PPM Mode Setup]
+  WATCH=[REG(0x290F0108)]
+  WATCH=[REG(0x290F0107)]
+  CAUSE: TARGET=[REG(0x290F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x290F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x290F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x290F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x290F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x290F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x290F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x290F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core10 PPM Mode Setup]
+  WATCH=[REG(0x2A0F0108)]
+  WATCH=[REG(0x2A0F0107)]
+  CAUSE: TARGET=[REG(0x2A0F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x2A0F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x2A0F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x2A0F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x2A0F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x2A0F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x2A0F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x2A0F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x2A0F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x2A0F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2A0F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x2A0F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x2A0F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x2A0F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x2A0F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x2A0F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core11 PPM Mode Setup]
+  WATCH=[REG(0x2B0F0108)]
+  WATCH=[REG(0x2B0F0107)]
+  CAUSE: TARGET=[REG(0x2B0F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x2B0F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x2B0F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x2B0F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x2B0F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x2B0F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x2B0F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x2B0F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x2B0F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x2B0F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2B0F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x2B0F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x2B0F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x2B0F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x2B0F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x2B0F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core12 PPM Mode Setup]
+  WATCH=[REG(0x2C0F0108)]
+  WATCH=[REG(0x2C0F0107)]
+  CAUSE: TARGET=[REG(0x2C0F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x2C0F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x2C0F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x2C0F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x2C0F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x2C0F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x2C0F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x2C0F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x2C0F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x2C0F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2C0F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x2C0F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x2C0F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x2C0F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x2C0F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x2C0F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core13 PPM Mode Setup]
+  WATCH=[REG(0x2D0F0108)]
+  WATCH=[REG(0x2D0F0107)]
+  CAUSE: TARGET=[REG(0x2D0F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x2D0F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x2D0F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x2D0F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x2D0F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x2D0F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x2D0F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x2D0F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x2D0F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x2D0F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2D0F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x2D0F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x2D0F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x2D0F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x2D0F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x2D0F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core14 PPM Mode Setup]
+  WATCH=[REG(0x2E0F0108)]
+  WATCH=[REG(0x2E0F0107)]
+  CAUSE: TARGET=[REG(0x2E0F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x2E0F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x2E0F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x2E0F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x2E0F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x2E0F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x2E0F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x2E0F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x2E0F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x2E0F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2E0F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x2E0F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x2E0F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x2E0F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x2E0F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x2E0F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core15 PPM Mode Setup]
+  WATCH=[REG(0x2F0F0108)]
+  WATCH=[REG(0x2F0F0107)]
+  CAUSE: TARGET=[REG(0x2F0F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x2F0F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x2F0F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x2F0F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x2F0F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x2F0F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x2F0F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x2F0F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x2F0F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x2F0F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x2F0F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x2F0F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x2F0F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x2F0F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x2F0F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x2F0F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core16 PPM Mode Setup]
+  WATCH=[REG(0x300F0108)]
+  WATCH=[REG(0x300F0107)]
+  CAUSE: TARGET=[REG(0x300F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x300F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x300F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x300F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x300F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x300F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x300F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x300F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x300F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x300F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x300F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x300F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x300F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x300F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x300F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x300F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core17 PPM Mode Setup]
+  WATCH=[REG(0x310F0108)]
+  WATCH=[REG(0x310F0107)]
+  CAUSE: TARGET=[REG(0x310F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x310F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x310F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x310F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x310F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x310F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x310F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x310F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x310F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x310F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x310F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x310F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x310F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x310F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x310F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x310F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core18 PPM Mode Setup]
+  WATCH=[REG(0x320F0108)]
+  WATCH=[REG(0x320F0107)]
+  CAUSE: TARGET=[REG(0x320F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x320F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x320F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x320F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x320F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x320F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x320F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x320F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x320F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x320F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x320F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x320F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x320F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x320F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x320F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x320F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core19 PPM Mode Setup]
+  WATCH=[REG(0x330F0108)]
+  WATCH=[REG(0x330F0107)]
+  CAUSE: TARGET=[REG(0x330F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x330F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x330F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x330F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x330F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x330F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x330F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x330F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x330F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x330F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x330F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x330F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x330F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x330F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x330F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x330F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core20 PPM Mode Setup]
+  WATCH=[REG(0x340F0108)]
+  WATCH=[REG(0x340F0107)]
+  CAUSE: TARGET=[REG(0x340F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x340F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x340F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x340F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x340F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x340F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x340F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x340F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x340F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x340F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x340F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x340F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x340F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x340F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x340F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x340F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core21 PPM Mode Setup]
+  WATCH=[REG(0x350F0108)]
+  WATCH=[REG(0x350F0107)]
+  CAUSE: TARGET=[REG(0x350F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x350F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x350F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x350F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x350F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x350F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x350F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x350F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x350F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x350F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x350F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x350F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x350F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x350F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x350F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x350F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core22 PPM Mode Setup]
+  WATCH=[REG(0x360F0108)]
+  WATCH=[REG(0x360F0107)]
+  CAUSE: TARGET=[REG(0x360F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x360F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x360F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x360F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x360F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x360F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x360F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x360F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x360F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x360F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x360F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x360F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x360F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x360F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x360F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x360F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core23 PPM Mode Setup]
+  WATCH=[REG(0x370F0108)]
+  WATCH=[REG(0x370F0107)]
+  CAUSE: TARGET=[REG(0x370F0108)] OP=[BIT,ON] BIT=[13]
+  CAUSE: TARGET=[REG(0x370F0107)] OP=[BIT,ON] BIT=[0]
+  CAUSE: TARGET=[REG(0x370F0107)] OP=[BIT,ON] BIT=[1]
+  CAUSE: TARGET=[REG(0x370F0107)] OP=[BIT,ON] BIT=[10]
+  CAUSE: TARGET=[REG(0x370F0107)] OP=[BIT,ON] BIT=[11]
+  CAUSE: TARGET=[REG(0x370F0107)] OP=[BIT,ON] BIT=[12]
+  CAUSE: TARGET=[REG(0x370F0107)] OP=[BIT,ON] BIT=[14]
+  CAUSE: TARGET=[REG(0x370F0107)] OP=[BIT,ON] BIT=[15]
+  EFFECT: TARGET=[REG(0x370F0106)] OP=[BIT,ON] BIT=[13]
+  EFFECT: TARGET=[REG(0x370F0106)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x370F0106)] OP=[BIT,OFF] BIT=[1]
+  EFFECT: TARGET=[REG(0x370F0106)] OP=[BIT,OFF] BIT=[10]
+  EFFECT: TARGET=[REG(0x370F0106)] OP=[BIT,OFF] BIT=[11]
+  EFFECT: TARGET=[REG(0x370F0106)] OP=[BIT,OFF] BIT=[12]
+  EFFECT: TARGET=[REG(0x370F0106)] OP=[BIT,OFF] BIT=[14]
+  EFFECT: TARGET=[REG(0x370F0106)] OP=[BIT,OFF] BIT=[15]
+}
+
+# Stop CMEs
+CAUSE_EFFECT {
+  LABEL=[EX0 CME STOP]
+  WATCH=[REG(0x10012010)]
+  CAUSE: TARGET=[REG(0x10012010)] OP=[BIT,OFF] BIT=[1]
+  CAUSE: TARGET=[REG(0x10012010)] OP=[BIT,OFF] BIT=[2]
+  CAUSE: TARGET=[REG(0x10012010)] OP=[BIT,ON] BIT=[3]
+  #suet EX0_CME_STOP:tc1- EFFECT: TARGET=[REG(0x10012013)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x10012013)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX1 CME STOP]
+  WATCH=[REG(0x10012410)]
+  CAUSE: TARGET=[REG(0x10012410)] OP=[BIT,OFF] BIT=[1]
+  CAUSE: TARGET=[REG(0x10012410)] OP=[BIT,OFF] BIT=[2]
+  CAUSE: TARGET=[REG(0x10012410)] OP=[BIT,ON] BIT=[3]
+  #suet EX1_CME_STOP:tc1- EFFECT: TARGET=[REG(0x10012413)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x10012413)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX2 CME STOP]
+  WATCH=[REG(0x11012010)]
+  CAUSE: TARGET=[REG(0x11012010)] OP=[BIT,OFF] BIT=[1]
+  CAUSE: TARGET=[REG(0x11012010)] OP=[BIT,OFF] BIT=[2]
+  CAUSE: TARGET=[REG(0x11012010)] OP=[BIT,ON] BIT=[3]
+  #suet EX2_CME_STOP:tc1- EFFECT: TARGET=[REG(0x11012013)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x11012013)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX3 CME STOP]
+  WATCH=[REG(0x11012410)]
+  CAUSE: TARGET=[REG(0x11012410)] OP=[BIT,OFF] BIT=[1]
+  CAUSE: TARGET=[REG(0x11012410)] OP=[BIT,OFF] BIT=[2]
+  CAUSE: TARGET=[REG(0x11012410)] OP=[BIT,ON] BIT=[3]
+  #suet EX3_CME_STOP:tc1- EFFECT: TARGET=[REG(0x11012413)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x11012413)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX4 CME STOP]
+  WATCH=[REG(0x12012010)]
+  CAUSE: TARGET=[REG(0x12012010)] OP=[BIT,OFF] BIT=[1]
+  CAUSE: TARGET=[REG(0x12012010)] OP=[BIT,OFF] BIT=[2]
+  CAUSE: TARGET=[REG(0x12012010)] OP=[BIT,ON] BIT=[3]
+  #suet EX4_CME_STOP:tc1- EFFECT: TARGET=[REG(0x12012013)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x12012013)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX5 CME STOP]
+  WATCH=[REG(0x12012410)]
+  CAUSE: TARGET=[REG(0x12012410)] OP=[BIT,OFF] BIT=[1]
+  CAUSE: TARGET=[REG(0x12012410)] OP=[BIT,OFF] BIT=[2]
+  CAUSE: TARGET=[REG(0x12012410)] OP=[BIT,ON] BIT=[3]
+  #suet EX5_CME_STOP:tc1- EFFECT: TARGET=[REG(0x12012413)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x12012413)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX6 CME STOP]
+  WATCH=[REG(0x13012010)]
+  CAUSE: TARGET=[REG(0x13012010)] OP=[BIT,OFF] BIT=[1]
+  CAUSE: TARGET=[REG(0x13012010)] OP=[BIT,OFF] BIT=[2]
+  CAUSE: TARGET=[REG(0x13012010)] OP=[BIT,ON] BIT=[3]
+  #suet EX6_CME_STOP:tc1- EFFECT: TARGET=[REG(0x13012013)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x13012013)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX7 CME STOP]
+  WATCH=[REG(0x13012410)]
+  CAUSE: TARGET=[REG(0x13012410)] OP=[BIT,OFF] BIT=[1]
+  CAUSE: TARGET=[REG(0x13012410)] OP=[BIT,OFF] BIT=[2]
+  CAUSE: TARGET=[REG(0x13012410)] OP=[BIT,ON] BIT=[3]
+  #suet EX7_CME_STOP:tc1- EFFECT: TARGET=[REG(0x13012413)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x13012413)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX8 CME STOP]
+  WATCH=[REG(0x14012010)]
+  CAUSE: TARGET=[REG(0x14012010)] OP=[BIT,OFF] BIT=[1]
+  CAUSE: TARGET=[REG(0x14012010)] OP=[BIT,OFF] BIT=[2]
+  CAUSE: TARGET=[REG(0x14012010)] OP=[BIT,ON] BIT=[3]
+  #suet EX8_CME_STOP:tc1- EFFECT: TARGET=[REG(0x14012013)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x14012013)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX9 CME STOP]
+  WATCH=[REG(0x14012410)]
+  CAUSE: TARGET=[REG(0x14012410)] OP=[BIT,OFF] BIT=[1]
+  CAUSE: TARGET=[REG(0x14012410)] OP=[BIT,OFF] BIT=[2]
+  CAUSE: TARGET=[REG(0x14012410)] OP=[BIT,ON] BIT=[3]
+  #suet EX9_CME_STOP:tc1- EFFECT: TARGET=[REG(0x14012413)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x14012413)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX10 CME STOP]
+  WATCH=[REG(0x15012010)]
+  CAUSE: TARGET=[REG(0x15012010)] OP=[BIT,OFF] BIT=[1]
+  CAUSE: TARGET=[REG(0x15012010)] OP=[BIT,OFF] BIT=[2]
+  CAUSE: TARGET=[REG(0x15012010)] OP=[BIT,ON] BIT=[3]
+  #suet EX10_CME_STOP:tc1- EFFECT: TARGET=[REG(0x15012013)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x15012013)] OP=[BIT,ON] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX11 CME STOP]
+  WATCH=[REG(0x15012410)]
+  CAUSE: TARGET=[REG(0x15012410)] OP=[BIT,OFF] BIT=[1]
+  CAUSE: TARGET=[REG(0x15012410)] OP=[BIT,OFF] BIT=[2]
+  CAUSE: TARGET=[REG(0x15012410)] OP=[BIT,ON] BIT=[3]
+  #suet EX11_CME_STOP:tc1- EFFECT: TARGET=[REG(0x15012413)] OP=[BIT,OFF] BIT=[0]
+  EFFECT: TARGET=[REG(0x15012413)] OP=[BIT,ON] BIT=[0]
+}
+
+# CME FIR Clear
+CAUSE_EFFECT {
+  LABEL=[EX0 CME FIR clear]
+  WATCH=[REG(0x10012001)]
+  CAUSE: TARGET=[REG(0x10012001)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+  EFFECT: TARGET=[REG(0x10012000)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX1 CME FIR clear]
+  WATCH=[REG(0x10012401)]
+  CAUSE: TARGET=[REG(0x10012401)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+  EFFECT: TARGET=[REG(0x10012400)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX2 CME FIR clear]
+  WATCH=[REG(0x11012001)]
+  CAUSE: TARGET=[REG(0x11012001)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+  EFFECT: TARGET=[REG(0x11012000)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX3 CME FIR clear]
+  WATCH=[REG(0x11012401)]
+  CAUSE: TARGET=[REG(0x11012401)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+  EFFECT: TARGET=[REG(0x11012400)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX4 CME FIR clear]
+  WATCH=[REG(0x12012001)]
+  CAUSE: TARGET=[REG(0x12012001)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+  EFFECT: TARGET=[REG(0x12012000)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX5 CME FIR clear]
+  WATCH=[REG(0x12012401)]
+  CAUSE: TARGET=[REG(0x12012401)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+  EFFECT: TARGET=[REG(0x12012400)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX6 CME FIR clear]
+  WATCH=[REG(0x13012001)]
+  CAUSE: TARGET=[REG(0x13012001)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+  EFFECT: TARGET=[REG(0x13012000)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX7 CME FIR clear]
+  WATCH=[REG(0x13012401)]
+  CAUSE: TARGET=[REG(0x13012401)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+  EFFECT: TARGET=[REG(0x13012400)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX8 CME FIR clear]
+  WATCH=[REG(0x14012001)]
+  CAUSE: TARGET=[REG(0x14012001)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+  EFFECT: TARGET=[REG(0x14012000)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX9 CME FIR clear]
+  WATCH=[REG(0x14012401)]
+  CAUSE: TARGET=[REG(0x14012401)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+  EFFECT: TARGET=[REG(0x14012400)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX10 CME FIR clear]
+  WATCH=[REG(0x15012001)]
+  CAUSE: TARGET=[REG(0x15012001)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+  EFFECT: TARGET=[REG(0x15012000)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+CAUSE_EFFECT {
+  LABEL=[EX11 CME FIR clear]
+  WATCH=[REG(0x15012401)]
+  CAUSE: TARGET=[REG(0x15012401)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+  EFFECT: TARGET=[REG(0x15012400)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+}
+
+# Allow PCB Access
+CAUSE_EFFECT {
+  LABEL=[Core0 PPM Mode Setup]
+  WATCH=[REG(0x200F0107)]
+  CAUSE: TARGET=[REG(0x200F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x200F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core1 PPM Mode Setup]
+  WATCH=[REG(0x210F0107)]
+  CAUSE: TARGET=[REG(0x210F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x210F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core2 PPM Mode Setup]
+  WATCH=[REG(0x220F0107)]
+  CAUSE: TARGET=[REG(0x220F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x220F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core3 PPM Mode Setup]
+  WATCH=[REG(0x230F0107)]
+  CAUSE: TARGET=[REG(0x230F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x230F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core4 PPM Mode Setup]
+  WATCH=[REG(0x240F0107)]
+  CAUSE: TARGET=[REG(0x240F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x240F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core5 PPM Mode Setup]
+  WATCH=[REG(0x250F0107)]
+  CAUSE: TARGET=[REG(0x250F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x250F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core6 PPM Mode Setup]
+  WATCH=[REG(0x260F0107)]
+  CAUSE: TARGET=[REG(0x260F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x260F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core7 PPM Mode Setup]
+  WATCH=[REG(0x270F0107)]
+  CAUSE: TARGET=[REG(0x270F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x270F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core8 PPM Mode Setup]
+  WATCH=[REG(0x280F0107)]
+  CAUSE: TARGET=[REG(0x280F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x280F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core9 PPM Mode Setup]
+  WATCH=[REG(0x290F0107)]
+  CAUSE: TARGET=[REG(0x290F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core10 PPM Mode Setup]
+  WATCH=[REG(0x2A0F0107)]
+  CAUSE: TARGET=[REG(0x2A0F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2A0F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core11 PPM Mode Setup]
+  WATCH=[REG(0x2B0F0107)]
+  CAUSE: TARGET=[REG(0x2B0F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2B0F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core12 PPM Mode Setup]
+  WATCH=[REG(0x2C0F0107)]
+  CAUSE: TARGET=[REG(0x2C0F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2C0F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core13 PPM Mode Setup]
+  WATCH=[REG(0x2D0F0107)]
+  CAUSE: TARGET=[REG(0x2D0F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2D0F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core14 PPM Mode Setup]
+  WATCH=[REG(0x2E0F0107)]
+  CAUSE: TARGET=[REG(0x2E0F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2E0F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core15 PPM Mode Setup]
+  WATCH=[REG(0x2F0F0107)]
+  CAUSE: TARGET=[REG(0x2F0F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x2F0F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core16 PPM Mode Setup]
+  WATCH=[REG(0x300F0107)]
+  CAUSE: TARGET=[REG(0x300F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x300F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core17 PPM Mode Setup]
+  WATCH=[REG(0x310F0107)]
+  CAUSE: TARGET=[REG(0x310F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x310F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core18 PPM Mode Setup]
+  WATCH=[REG(0x320F0107)]
+  CAUSE: TARGET=[REG(0x320F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x320F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core19 PPM Mode Setup]
+  WATCH=[REG(0x330F0107)]
+  CAUSE: TARGET=[REG(0x330F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x330F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core20 PPM Mode Setup]
+  WATCH=[REG(0x340F0107)]
+  CAUSE: TARGET=[REG(0x340F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x340F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core21 PPM Mode Setup]
+  WATCH=[REG(0x350F0107)]
+  CAUSE: TARGET=[REG(0x350F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x350F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core22 PPM Mode Setup]
+  WATCH=[REG(0x360F0107)]
+  CAUSE: TARGET=[REG(0x360F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x360F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+CAUSE_EFFECT {
+  LABEL=[Core23 PPM Mode Setup]
+  WATCH=[REG(0x370F0107)]
+  CAUSE: TARGET=[REG(0x370F0107)] OP=[BIT,ON] BIT=[0]
+  EFFECT: TARGET=[REG(0x370F0106)] OP=[BIT,OFF] BIT=[0]
+}
+
+
+
diff --git a/src/import/chips/p9/utils/Makefile b/src/import/chips/p9/utils/Makefile
new file mode 100644
index 00000000..07432cd1
--- /dev/null
+++ b/src/import/chips/p9/utils/Makefile
@@ -0,0 +1,53 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/utils/Makefile $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+# @brief This Makefile compiles all of the PutRing Utils code.
+# All the generated files from this makefile will end up in obj/utils
+#
+#
+export SUB_OBJDIR = /utils
+
+include img_defs.mk
+include utils.mk
+
+OBJS := $(addprefix $(OBJDIR)/, $(UTILS_OBJECTS))
+
+libutils.a: utils
+	$(AR) crs $(OBJDIR)/libutils.a $(OBJDIR)/*.o
+
+.PHONY: clean utils
+utils: $(OBJS)
+
+$(OBJS) $(OBJS:.o=.d): | $(OBJDIR)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+clean:
+	rm -fr $(OBJDIR)
+
+ifneq ($(MAKECMDGOALS),clean)
+include $(OBJS:.o=.d)
+endif
diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.H b/src/import/chips/p9/utils/imageProcs/p9_ringId.H
new file mode 100644
index 00000000..f39b29d4
--- /dev/null
+++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.H
@@ -0,0 +1,1284 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/utils/imageProcs/p9_ringId.H $                */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef _P9_RINGID_H_
+#define _P9_RINGID_H_
+
+#include <stdint.h>
+#include <p9_ring_id.h>
+
+// General Ring ID list structure
+typedef struct
+{
+    const char*  ringName;
+    uint8_t      ringId;
+    uint8_t      instanceIdMin;    // the min instanceId
+    uint8_t      instanceIdMax;    // the max instanceId
+    const char*  ringNameImg; // Ring name in image: ringName + "_ring"
+    uint8_t      vpdKeyword;
+    uint8_t      pllCopy;     // 0,1,2,3,4,5 -- No of PLL copies required
+    uint64_t     scanRegionType;
+} GenRingIdList;
+
+typedef enum RingVariant   // Base variables
+{
+    BASE     = 0x00,
+    CC       = 0x01,
+    RL       = 0x02,
+    OVERRIDE = 0x03,
+    OVERLAY  = 0x04,
+    NUM_RING_VARIANTS = 0x05,
+    NOT_VALID = 0xff
+} RingVariant_t;
+
+typedef struct
+{
+    uint8_t  variant[3];
+} RingVariantOrder;
+
+
+namespace PERV
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace N0
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace N1
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace N2
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace N3
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace XB
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace MC
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace OB0
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace OB1
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace OB2
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace OB3
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace PCI0
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace PCI1
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace PCI2
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace EQ
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace EC
+{
+extern const GenRingIdList RING_ID_LIST_COMMON[];
+extern const GenRingIdList RING_ID_LIST_INSTANCE[];
+extern const RingVariantOrder RING_VARIANT_ORDER[];
+}
+
+namespace RING_TYPES
+{
+enum RINGTYPE
+{
+    COMMON_RING = 0,
+    INSTANCE_RING = 1
+};
+
+}; //end of RS4 namespace
+enum CHIPLET_TYPE
+{
+    PERV_TYPE,
+    N0_TYPE,
+    N1_TYPE,
+    N2_TYPE,
+    N3_TYPE,
+    MC_TYPE,
+    PCI0_TYPE,
+    PCI1_TYPE,
+    PCI2_TYPE,
+    OB0_TYPE,
+    OB1_TYPE,
+    OB2_TYPE,
+    OB3_TYPE,
+    XB_TYPE,
+    EQ_TYPE,
+    EC_TYPE,
+};
+
+struct CHIPLET_DATA
+{
+    // This is the chiplet-ID of the first instance of the Chiplet
+    uint8_t iv_base_chiplet_number;
+
+    // The no.of common rings for the Chiplet
+    uint8_t iv_num_common_rings;
+
+    // The no.of instance rings for the Chiplet
+    uint8_t iv_num_instance_rings;
+};
+
+// This is used to Set (Mark) the left-most bit
+const uint8_t INSTANCE_RING_MARK = 0x80;
+//
+// This is used to Set (Mark) the left-most bit
+const uint8_t INSTANCE_RING_MASK = 0x7F;
+
+namespace PERV
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    perv_fure     = 0,
+    perv_gptr     = 1,
+    perv_time     = 2,
+    occ_fure      = 3,
+    occ_gptr      = 4,
+    occ_time      = 5,
+    perv_ana_func = 6,
+    perv_ana_gptr = 7,
+    perv_pll_gptr = 8,
+    perv_pll_bndy = 9,
+    // The values for this and the following constant are purposefully made
+    // identical. The idea is to enable the user to specify directly the bucket
+    // number or use the Attribute. Giving same number here will enable
+    // evaluating to the same offset.
+    perv_pll_bndy_bucket_1 = 9,
+    perv_pll_bndy_bucket_2 = 10,
+    perv_pll_bndy_bucket_3 = 11,
+    perv_pll_bndy_bucket_4 = 12,
+    perv_pll_bndy_bucket_5 = 13,
+    perv_pll_func   = 14,
+    perv_pibnet_gptr = 15,
+    perv_pibnet_time = 16,
+    // Instance Rings
+    perv_repr     = (0 | INSTANCE_RING_MARK),
+    occ_repr      = (1 | INSTANCE_RING_MARK),
+    perv_pibnet_repr = (2 | INSTANCE_RING_MARK)
+};
+
+static const CHIPLET_DATA g_pervData =
+{
+    1,  // Pervasive Chiplet ID is 1
+    17, // 17 common rings for pervasive chiplet
+    3   // 3 instance specific rings for pervasive chiplet
+};
+}; // end of namespace PERV
+
+namespace N0
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    n0_fure      = 0,
+    n0_gptr      = 1,
+    n0_time      = 2,
+    n0_nx_fure   = 3,
+    n0_nx_gptr   = 4,
+    n0_nx_time   = 5,
+    n0_cxa0_fure = 6,
+    n0_cxa0_gptr = 7,
+    n0_cxa0_time = 8,
+    // Instance Rings
+    n0_repr      = (0 | INSTANCE_RING_MARK),
+    n0_nx_repr   = (1 | INSTANCE_RING_MARK),
+    n0_cxa0_repr = (2 | INSTANCE_RING_MARK)
+};
+
+static const CHIPLET_DATA g_n0Data =
+{
+    2, // N0 Chiplet ID is 2.
+    9, // 9 common rings for N0 Chiplet
+    3  // 3 instance specific rings for N0 chiplet
+};
+};
+
+namespace N1
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    n1_fure       = 0,
+    n1_gptr       = 1,
+    n1_time       = 2,
+    n1_ioo0_fure  = 3,
+    n1_ioo0_gptr  = 4,
+    n1_ioo0_time  = 5,
+    n1_ioo1_fure  = 6,
+    n1_ioo1_gptr  = 7,
+    n1_ioo1_time  = 8,
+    n1_mcs23_fure = 9,
+    n1_mcs23_gptr = 10,
+    n1_mcs23_time = 11,
+    // Instance Rings
+    n1_repr       = (0 | INSTANCE_RING_MARK),
+    n1_ioo0_repr  = (1 | INSTANCE_RING_MARK),
+    n1_ioo1_repr  = (2 | INSTANCE_RING_MARK),
+    n1_mcs23_repr = (3 | INSTANCE_RING_MARK),
+};
+
+static const CHIPLET_DATA g_n1Data =
+{
+    3,  // N1 Chiplet ID is 3.
+    12, // 12 common rings for N1 Chiplet
+    4   // 4 instance specific rings for N1 chiplet
+};
+};
+
+namespace N2
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    n2_fure      = 0,
+    n2_gptr      = 1,
+    n2_time      = 2,
+    n2_cxa1_fure = 3,
+    n2_cxa1_gptr = 4,
+    n2_cxa1_time = 5,
+    n2_psi_fure = 6,
+    n2_psi_gptr = 7,
+    n2_psi_time = 8,
+    // Instance Rings
+    n2_repr      = (0 | INSTANCE_RING_MARK),
+    n2_cxa1_repr = (1 | INSTANCE_RING_MARK),
+    n2_psi_repr  = (2 | INSTANCE_RING_MARK)
+};
+
+static const CHIPLET_DATA g_n2Data =
+{
+    4, // N2 Chiplet ID is 4.
+    9, // 9 common rings for N2 Chiplet
+    3  // 3 instance specific rings for N2 chiplet
+};
+};
+
+namespace N3
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    n3_fure       = 0,
+    n3_gptr       = 1,
+    n3_time       = 2,
+    n3_mcs01_fure = 3,
+    n3_mcs01_gptr = 4,
+    n3_mcs01_time = 5,
+    n3_np_fure = 6,
+    n3_np_gptr = 7,
+    n3_np_time = 8,
+    // Instance Rings
+    n3_repr       = (0 | INSTANCE_RING_MARK),
+    n3_mcs01_repr = (1 | INSTANCE_RING_MARK),
+    n3_np_repr = (2 | INSTANCE_RING_MARK),
+};
+
+static const CHIPLET_DATA g_n3Data =
+{
+    5, // N3 Chiplet ID is 5
+    9, // 9 common rings for N3 Chiplet
+    3  // 3 instance specific rings for N3 chiplet
+};
+};
+
+namespace XB
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    xb_fure      = 0,
+    xb_gptr      = 1,
+    xb_time      = 2,
+    xb_io0_fure  = 3,
+    xb_io0_gptr  = 4,
+    xb_io0_time  = 5,
+    xb_io1_fure  = 6,
+    xb_io1_gptr  = 7,
+    xb_io1_time  = 8,
+    xb_io2_fure  = 9,
+    xb_io2_gptr  = 10,
+    xb_io2_time  = 11,
+    xb_pll_gptr  = 12,
+    xb_pll_bndy  = 13,
+    xb_pll_func  = 14,
+    // Instance Rings
+    xb_repr      = (0 | INSTANCE_RING_MARK),
+    xb_io0_repr  = (1 | INSTANCE_RING_MARK),
+    xb_io1_repr  = (2 | INSTANCE_RING_MARK),
+    xb_io2_repr  = (3 | INSTANCE_RING_MARK)
+};
+
+static const CHIPLET_DATA g_xbData =
+{
+    6,  // X-Bus Chiplet ID is 6
+    15, // 15 common rings for X-Bus Chiplet
+    4   // 4 instance specific rings for XB chiplet
+};
+}; // end of namespace XB
+
+namespace MC
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    mc_fure       = 0,
+    mc_gptr       = 1,
+    mc_time       = 2,
+    mc_iom01_fure = 3,
+    mc_iom01_gptr = 4,
+    mc_iom01_time = 5,
+    mc_iom23_fure = 6,
+    mc_iom23_gptr = 7,
+    mc_iom23_time = 8,
+    mc_pll_gptr   = 9,
+    mc_pll_bndy = 10,
+    mc_pll_bndy_bucket_1 = 10,
+    mc_pll_bndy_bucket_2 = 11,
+    mc_pll_bndy_bucket_3 = 12,
+    mc_pll_bndy_bucket_4 = 13,
+    mc_pll_bndy_bucket_5 = 14,
+    mc_pll_func = 15,
+    // Instance Rings
+    mc_repr       = (0 | INSTANCE_RING_MARK),
+    mc_iom01_repr = (1 | INSTANCE_RING_MARK),
+    mc_iom23_repr = (2 | INSTANCE_RING_MARK)
+};
+
+static const CHIPLET_DATA g_mcData =
+{
+    7,  // MC Chiplet ID range is 7 - 8. The base ID is 7.
+    16, // 16 common rings for MC Chiplet
+    3   // 3 instance specific rings for each MC instance
+};
+}; // end of namespace MC
+
+namespace OB0
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    ob0_fure      = 0,
+    ob0_gptr      = 1,
+    ob0_time      = 2,
+    ob0_pll_gptr  = 3,
+    ob0_pll_bndy  = 4,
+    ob0_pll_func  = 5,
+    // Instance Rings
+    ob0_repr      = (0 | INSTANCE_RING_MARK)
+};
+
+static const CHIPLET_DATA g_ob0Data =
+{
+    9,  // O-Bus Chiplet ID range is 9 - 12. The base ID is 9.
+    6,  // 6 common rings for OB Chiplet
+    1   // 1 instance specific rings for each OB chiplet
+};
+}; // end of namespace OB0
+
+namespace OB1
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    ob1_fure      = 0,
+    ob1_gptr      = 1,
+    ob1_time      = 2,
+    ob1_pll_gptr  = 3,
+    ob1_pll_bndy  = 4,
+    ob1_pll_func  = 5,
+    // Instance Rings
+    ob1_repr      = (0 | INSTANCE_RING_MARK)
+};
+
+static const CHIPLET_DATA g_ob1Data =
+{
+    10,  // O-Bus Chiplet ID range is 9 - 12. The base ID is 9.
+    6,   // 6 common rings for OB Chiplet
+    1    // 1 instance specific rings for each OB chiplet
+};
+}; // end of namespace OB1
+
+
+namespace OB2
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    ob2_fure      = 0,
+    ob2_gptr      = 1,
+    ob2_time      = 2,
+    ob2_pll_gptr  = 3,
+    ob2_pll_bndy  = 4,
+    ob2_pll_func  = 5,
+    // Instance Rings
+    ob2_repr      = (0 | INSTANCE_RING_MARK)
+};
+
+static const CHIPLET_DATA g_ob2Data =
+{
+    11,  // O-Bus Chiplet ID range is 9 - 12. The base ID is 9.
+    6,   // 6 common rings for OB Chiplet
+    1    // 1 instance specific rings for each OB chiplet
+};
+}; // end of namespace OB2
+
+namespace OB3
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    ob3_fure      = 0,
+    ob3_gptr      = 1,
+    ob3_time      = 2,
+    ob3_pll_gptr  = 3,
+    ob3_pll_bndy  = 4,
+    ob3_pll_func  = 5,
+    // Instance Rings
+    ob3_repr      = (0 | INSTANCE_RING_MARK)
+};
+
+static const CHIPLET_DATA g_ob3Data =
+{
+    12,  // O-Bus Chiplet ID range is 9 - 12. The base ID is 9.
+    6,   // 10 common rings for OB Chiplet
+    1    // 1 instance specific rings for each OB chiplet
+};
+}; // end of namespace OB2
+namespace PCI0
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    pci0_fure = 0,
+    pci0_gptr = 1,
+    pci0_time = 2,
+    pci0_pll_bndy = 3,
+    pci0_pll_gptr = 4,
+    // Instance Rings
+    pci0_repr = (0 | INSTANCE_RING_MARK)
+};
+
+static const CHIPLET_DATA g_pci0Data =
+{
+    13, // PCI0 Chiplet Chiplet ID is 13
+    5,  // 5 common rings for PCI0 chiplet
+    1,  // 1 instance specific rings for PCI0 chiplet
+};
+};
+
+namespace PCI1
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    pci1_fure = 0,
+    pci1_gptr = 1,
+    pci1_time = 2,
+    pci1_pll_bndy = 3,
+    pci1_pll_gptr = 4,
+    // Instance Rings
+    pci1_repr = (0 | INSTANCE_RING_MARK)
+};
+
+static const CHIPLET_DATA g_pci1Data =
+{
+    14, // PCI1 Chiplet Chiplet ID is 14
+    5,  // 5 common rings for PCI1 chiplet
+    1,  // 1 instance specific rings for PCI1 chiplet
+};
+};
+
+namespace PCI2
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    pci2_fure = 0,
+    pci2_gptr = 1,
+    pci2_time = 2,
+    pci2_pll_bndy = 3,
+    pci2_pll_gptr = 4,
+    // Instance Rings
+    pci2_repr = (0 | INSTANCE_RING_MARK)
+};
+
+static const CHIPLET_DATA g_pci2Data =
+{
+    15, // PCI2 Chiplet Chiplet ID is 15
+    5,  // 5 common rings for PCI2 chiplet
+    1,  // 1 instance specific rings for PCI2 chiplet
+};
+
+};
+
+namespace EQ
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_cacheContained;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    eq_fure         = 0,
+    eq_gptr         = 1,
+    eq_time         = 2,
+    eq_mode         = 3,
+    ex_l3_fure      = 4,
+    ex_l3_gptr      = 5,
+    ex_l3_time      = 6,
+    ex_l2_mode      = 7,
+    ex_l2_fure      = 8,
+    ex_l2_gptr      = 9,
+    ex_l2_time      = 10,
+    ex_l3_refr_fure = 11,
+    ex_l3_refr_gptr = 12,
+    eq_ana_func     = 13,
+    eq_ana_gptr     = 14,
+    eq_dpll_func    = 15,
+    eq_dpll_gptr    = 16,
+    eq_dpll_mode    = 17,
+    eq_ana_bndy     = 18,
+    eq_ana_bndy_bucket_0   = 18,
+    eq_ana_bndy_bucket_1   = 19,
+    eq_ana_bndy_bucket_2   = 20,
+    eq_ana_bndy_bucket_3   = 21,
+    eq_ana_bndy_bucket_4   = 22,
+    eq_ana_bndy_bucket_5   = 23,
+    eq_ana_bndy_bucket_6   = 24,
+    eq_ana_bndy_bucket_7   = 25,
+    eq_ana_bndy_bucket_8   = 26,
+    eq_ana_bndy_bucket_9   = 27,
+    eq_ana_bndy_bucket_10  = 28,
+    eq_ana_bndy_bucket_11  = 29,
+    eq_ana_bndy_bucket_12  = 30,
+    eq_ana_bndy_bucket_13  = 31,
+    eq_ana_bndy_bucket_14  = 32,
+    eq_ana_bndy_bucket_15  = 33,
+    eq_ana_bndy_bucket_16  = 34,
+    eq_ana_bndy_bucket_17  = 35,
+    eq_ana_bndy_bucket_18  = 36,
+    eq_ana_bndy_bucket_19  = 37,
+    eq_ana_bndy_bucket_20  = 38,
+    eq_ana_bndy_bucket_21  = 39,
+    eq_ana_bndy_bucket_22  = 40,
+    eq_ana_bndy_bucket_23  = 41,
+    eq_ana_bndy_bucket_24  = 42,
+    eq_ana_bndy_bucket_25  = 43,
+    eq_ana_bndy_l3dcc_bucket_26  = 44,
+    eq_ana_mode     = 45,
+    // Instance Rings
+    eq_repr         = (0 | INSTANCE_RING_MARK),
+    ex_l3_repr      = (1 | INSTANCE_RING_MARK),
+    ex_l2_repr      = (2 | INSTANCE_RING_MARK),
+    ex_l3_refr_repr = (3 | INSTANCE_RING_MARK),
+    ex_l3_refr_time = (4 | INSTANCE_RING_MARK)
+};
+
+static const CHIPLET_DATA g_eqData =
+{
+    16, // Quad Chiplet ID range is 16 - 21. The base ID is 16.
+    46, // 46 common rings for Quad chiplet.
+    5,  // 5 instance specific rings for each EQ chiplet
+};
+}; // end of namespace EQ
+
+namespace EC
+{
+struct RingVariants
+{
+    uint16_t iv_base;
+    uint16_t iv_cacheContained;
+    uint16_t iv_riskLevel;
+};
+
+enum RingOffset
+{
+    // Common Rings
+    ec_func = 0,
+    ec_gptr = 1,
+    ec_time = 2,
+    ec_mode = 3,
+    // Instance Rings
+    ec_repr = (0 | INSTANCE_RING_MARK)
+};
+
+static const CHIPLET_DATA g_ecData =
+{
+    32, // Core Chiplet ID range is 32-55. The base ID is 32.
+    4,  // 4 common rings for Core chiplet
+    1   // 1 instance specific ring for each Core chiplet
+};
+}; // end of namespace EC
+
+static const uint8_t INVALID_RING = 0xFF;
+
+// This structure is needed for mapping a RingID to it's corresponding name.
+// The names will be used by the build scripts when generating the TOR.
+#ifndef __PPE__
+struct ringProperties_t
+{
+    uint8_t iv_torOffSet;
+    char iv_name[50];
+    CHIPLET_TYPE iv_type;
+};
+#endif
+#ifdef __PPE__
+struct ringProperties_t
+{
+    uint8_t iv_torOffSet;
+    CHIPLET_TYPE iv_type;
+};
+#endif
+
+#ifndef __PPE__
+static const ringProperties_t RING_PROPERTIES[P9_NUM_RINGS] =
+{
+    { PERV::perv_fure                    , "perv_fure"                   , PERV_TYPE  }, // 0
+    { PERV::perv_gptr                    , "perv_gptr"                   , PERV_TYPE  }, // 1
+    { PERV::perv_time                    , "perv_time"                   , PERV_TYPE  }, // 2
+    { PERV::occ_fure                     , "occ_fure"                    , PERV_TYPE  }, // 3
+    { PERV::occ_gptr                     , "occ_gptr"                    , PERV_TYPE  }, // 4
+    { PERV::occ_time                     , "occ_time"                    , PERV_TYPE  }, // 5
+    { PERV::perv_ana_func                , "perv_ana_func"               , PERV_TYPE  }, // 6
+    { PERV::perv_ana_gptr                , "perv_ana_gptr"               , PERV_TYPE  }, // 7
+    { PERV::perv_pll_gptr                , "perv_pll_gptr"               , PERV_TYPE  }, // 8
+    { PERV::perv_pll_bndy                , "perv_pll_bndy"               , PERV_TYPE  }, // 9
+    { PERV::perv_pll_bndy_bucket_1       , "perv_pll_bndy_bucket_1"      , PERV_TYPE  }, // 10
+    { PERV::perv_pll_bndy_bucket_2       , "perv_pll_bndy_bucket_2"      , PERV_TYPE  }, // 11
+    { PERV::perv_pll_bndy_bucket_3       , "perv_pll_bndy_bucket_3"      , PERV_TYPE  }, // 12
+    { PERV::perv_pll_bndy_bucket_4       , "perv_pll_bndy_bucket_4"      , PERV_TYPE  }, // 13
+    { PERV::perv_pll_bndy_bucket_5       , "perv_pll_bndy_bucket_5"      , PERV_TYPE  }, // 14
+    { PERV::perv_pll_func                , "perv_pll_func"               , PERV_TYPE  }, // 15
+    { PERV::perv_pibnet_gptr             , "perv_pibnet_gptr"            , PERV_TYPE  }, // 16
+    { PERV::perv_pibnet_time             , "perv_pibnet_time"            , PERV_TYPE  }, // 17
+    { PERV::perv_repr                    , "perv_repr"                   , PERV_TYPE  }, // 18
+    { PERV::occ_repr                     , "occ_repr"                    , PERV_TYPE  }, // 19
+    { PERV::perv_pibnet_repr             , "perv_pibnet_repr"            , PERV_TYPE  }, // 20
+    { N0::n0_fure                        , "n0_fure"                     , N0_TYPE    }, // 21
+    { N0::n0_gptr                        , "n0_gptr"                     , N0_TYPE    }, // 22
+    { N0::n0_time                        , "n0_time"                     , N0_TYPE    }, // 23
+    { N0::n0_nx_fure                     , "n0_nx_fure"                  , N0_TYPE    }, // 24
+    { N0::n0_nx_gptr                     , "n0_nx_gptr"                  , N0_TYPE    }, // 25
+    { N0::n0_nx_time                     , "n0_nx_time"                  , N0_TYPE    }, // 26
+    { N0::n0_cxa0_fure                   , "n0_cxa0_fure"                , N0_TYPE    }, // 27
+    { N0::n0_cxa0_gptr                   , "n0_cxa0_gptr"                , N0_TYPE    }, // 28
+    { N0::n0_cxa0_time                   , "n0_cxa0_time"                , N0_TYPE    }, // 29
+    { N0::n0_repr                        , "n0_repr"                     , N0_TYPE    }, // 30
+    { N0::n0_nx_repr                     , "n0_nx_repr"                  , N0_TYPE    }, // 31
+    { N0::n0_cxa0_repr                   , "n0_cxa0_repr"                , N0_TYPE    }, // 32
+    { N1::n1_fure                        , "n1_fure"                     , N1_TYPE    }, // 33
+    { N1::n1_gptr                        , "n1_gptr"                     , N1_TYPE    }, // 34
+    { N1::n1_time                        , "n1_time"                     , N1_TYPE    }, // 35
+    { N1::n1_ioo0_fure                   , "n1_ioo0_fure"                , N1_TYPE    }, // 36
+    { N1::n1_ioo0_gptr                   , "n1_ioo0_gptr"                , N1_TYPE    }, // 37
+    { N1::n1_ioo0_time                   , "n1_ioo0_time"                , N1_TYPE    }, // 38
+    { N1::n1_ioo1_fure                   , "n1_ioo1_fure"                , N1_TYPE    }, // 39
+    { N1::n1_ioo1_gptr                   , "n1_ioo1_gptr"                , N1_TYPE    }, // 40
+    { N1::n1_ioo1_time                   , "n1_ioo1_time"                , N1_TYPE    }, // 41
+    { N1::n1_mcs23_fure                  , "n1_mcs23_fure"               , N1_TYPE    }, // 42
+    { N1::n1_mcs23_gptr                  , "n1_mcs23_gptr"               , N1_TYPE    }, // 43
+    { N1::n1_mcs23_time                  , "n1_mcs23_time"               , N1_TYPE    }, // 44
+    { N1::n1_repr                        , "n1_repr"                     , N1_TYPE    }, // 45
+    { N1::n1_ioo0_repr                   , "n1_ioo0_repr"                , N1_TYPE    }, // 46
+    { N1::n1_ioo1_repr                   , "n1_ioo1_repr"                , N1_TYPE    }, // 47
+    { N1::n1_mcs23_repr                  , "n1_mcs23_repr"               , N1_TYPE    }, // 48
+    { N2::n2_fure                        , "n2_fure"                     , N2_TYPE    }, // 49
+    { N2::n2_gptr                        , "n2_gptr"                     , N2_TYPE    }, // 50
+    { N2::n2_time                        , "n2_time"                     , N2_TYPE    }, // 51
+    { N2::n2_cxa1_fure                   , "n2_cxa1_fure"                , N2_TYPE    }, // 52
+    { N2::n2_cxa1_gptr                   , "n2_cxa1_gptr"                , N2_TYPE    }, // 53
+    { N2::n2_cxa1_time                   , "n2_cxa1_time"                , N2_TYPE    }, // 54
+    { N2::n2_psi_fure                    , "n2_psi_fure"                 , N2_TYPE    }, // 55
+    { N2::n2_psi_gptr                    , "n2_psi_gptr"                 , N2_TYPE    }, // 56
+    { N2::n2_psi_time                    , "n2_psi_time"                 , N2_TYPE    }, // 57
+    { N2::n2_repr                        , "n2_repr"                     , N2_TYPE    }, // 58
+    { N2::n2_cxa1_repr                   , "n2_cxa1_repr"                , N2_TYPE    }, // 59
+    { N2::n2_psi_repr                    , "n2_psi_repr"                 , N2_TYPE    }, // 60
+    { INVALID_RING                       , "invalid"                     , N2_TYPE    }, // 61
+    { N3::n3_fure                        , "n3_fure"                     , N3_TYPE    }, // 62
+    { N3::n3_gptr                        , "n3_gptr"                     , N3_TYPE    }, // 63
+    { N3::n3_time                        , "n3_time"                     , N3_TYPE    }, // 64
+    { N3::n3_mcs01_fure                  , "n3_mcs01_fure"               , N3_TYPE    }, // 65
+    { N3::n3_mcs01_gptr                  , "n3_mcs01_gptr"               , N3_TYPE    }, // 66
+    { N3::n3_mcs01_time                  , "n3_mcs01_time"               , N3_TYPE    }, // 67
+    { N3::n3_np_fure                     , "n3_np_fure"                  , N3_TYPE    }, // 68
+    { N3::n3_np_gptr                     , "n3_np_gptr"                  , N3_TYPE    }, // 69
+    { N3::n3_np_time                     , "n3_np_time"                  , N3_TYPE    }, // 70
+    { N3::n3_repr                        , "n3_repr"                     , N3_TYPE    }, // 71
+    { N3::n3_mcs01_repr                  , "n3_mcs01_repr"               , N3_TYPE    }, // 72
+    { N3::n3_np_repr                     , "n3_np_repr"                  , N3_TYPE    }, // 73
+    { INVALID_RING                       , "invalid"                     , N3_TYPE    }, // 74
+    { XB::xb_fure                        , "xb_fure"                     , XB_TYPE    }, // 75
+    { XB::xb_gptr                        , "xb_gptr"                     , XB_TYPE    }, // 76
+    { XB::xb_time                        , "xb_time"                     , XB_TYPE    }, // 77
+    { XB::xb_io0_fure                    , "xb_io0_fure"                 , XB_TYPE    }, // 78
+    { XB::xb_io0_gptr                    , "xb_io0_gptr"                 , XB_TYPE    }, // 79
+    { XB::xb_io0_time                    , "xb_io0_time"                 , XB_TYPE    }, // 80
+    { XB::xb_io1_fure                    , "xb_io1_fure"                 , XB_TYPE    }, // 81
+    { XB::xb_io1_gptr                    , "xb_io1_gptr"                 , XB_TYPE    }, // 82
+    { XB::xb_io1_time                    , "xb_io1_time"                 , XB_TYPE    }, // 83
+    { XB::xb_io2_fure                    , "xb_io2_fure"                 , XB_TYPE    }, // 84
+    { XB::xb_io2_gptr                    , "xb_io2_gptr"                 , XB_TYPE    }, // 85
+    { XB::xb_io2_time                    , "xb_io2_time"                 , XB_TYPE    }, // 86
+    { XB::xb_pll_gptr                    , "xb_pll_gptr"                 , XB_TYPE    }, // 87
+    { XB::xb_pll_bndy                    , "xb_pll_bndy"                 , XB_TYPE    }, // 88
+    { XB::xb_pll_func                    , "xb_pll_func"                 , XB_TYPE    }, // 89
+    { XB::xb_repr                        , "xb_repr"                     , XB_TYPE    }, // 90
+    { XB::xb_io0_repr                    , "xb_io0_repr"                 , XB_TYPE    }, // 91
+    { XB::xb_io1_repr                    , "xb_io1_repr"                 , XB_TYPE    }, // 92
+    { XB::xb_io2_repr                    , "xb_io2_repr"                 , XB_TYPE    }, // 93
+    { INVALID_RING                       , "invalid"                     , XB_TYPE    }, // 94
+    { INVALID_RING                       , "invalid"                     , XB_TYPE    }, // 95
+    { MC::mc_fure                        , "mc_fure"                     , MC_TYPE    }, // 96
+    { MC::mc_gptr                        , "mc_gptr"                     , MC_TYPE    }, // 97
+    { MC::mc_time                        , "mc_time"                     , MC_TYPE    }, // 98
+    { MC::mc_iom01_fure                  , "mc_iom01_fure"               , MC_TYPE    }, // 99
+    { MC::mc_iom01_gptr                  , "mc_iom01_gptr"               , MC_TYPE    }, // 100
+    { MC::mc_iom01_time                  , "mc_iom01_time"               , MC_TYPE    }, // 101
+    { MC::mc_iom23_fure                  , "mc_iom23_fure"               , MC_TYPE    }, // 102
+    { MC::mc_iom23_gptr                  , "mc_iom23_gptr"               , MC_TYPE    }, // 103
+    { MC::mc_iom23_time                  , "mc_iom23_time"               , MC_TYPE    }, // 104
+    { MC::mc_pll_gptr                    , "mc_pll_gptr"                 , MC_TYPE    }, // 105
+    { MC::mc_pll_bndy                    , "mc_pll_bndy"                 , MC_TYPE    }, // 106
+    { MC::mc_pll_bndy_bucket_1           , "mc_pll_bndy_bucket_1"        , MC_TYPE    }, // 107
+    { MC::mc_pll_bndy_bucket_2           , "mc_pll_bndy_bucket_2"        , MC_TYPE    }, // 108
+    { MC::mc_pll_bndy_bucket_3           , "mc_pll_bndy_bucket_3"        , MC_TYPE    }, // 109
+    { MC::mc_pll_bndy_bucket_4           , "mc_pll_bndy_bucket_4"        , MC_TYPE    }, // 110
+    { MC::mc_pll_bndy_bucket_5           , "mc_pll_bndy_bucket_5"        , MC_TYPE    }, // 111
+    { MC::mc_pll_func                    , "mc_pll_func"                 , MC_TYPE    }, // 112
+    { MC::mc_repr                        , "mc_repr"                     , MC_TYPE    }, // 113
+    { MC::mc_iom01_repr                  , "mc_iom01_repr"               , MC_TYPE    }, // 114
+    { MC::mc_iom23_repr                  , "mc_iom23_repr"               , MC_TYPE    }, // 115
+    { INVALID_RING                       , "invalid"                     , MC_TYPE    }, // 116
+    { INVALID_RING                       , "invalid"                     , MC_TYPE    }, // 117
+    { OB0::ob0_fure                      , "ob0_fure"                    , OB0_TYPE   }, // 118
+    { OB0::ob0_gptr                      , "ob0_gptr"                    , OB0_TYPE   }, // 119
+    { OB0::ob0_time                      , "ob0_time"                    , OB0_TYPE   }, // 120
+    { OB0::ob0_pll_gptr                  , "ob0_pll_gptr"                , OB0_TYPE   }, // 121
+    { OB0::ob0_pll_bndy                  , "ob0_pll_bndy"                , OB0_TYPE   }, // 122
+    { OB0::ob0_pll_func                  , "ob0_pll_func"                , OB0_TYPE   }, // 123
+    { OB0::ob0_repr                      , "ob0_repr"                    , OB0_TYPE   }, // 124
+    { INVALID_RING                       , "invalid"                     , OB0_TYPE   }, // 125
+    { INVALID_RING                       , "invalid"                     , OB0_TYPE   }, // 126
+    { OB1::ob1_fure                      , "ob1_fure"                    , OB1_TYPE   }, // 127
+    { OB1::ob1_gptr                      , "ob1_gptr"                    , OB1_TYPE   }, // 128
+    { OB1::ob1_time                      , "ob1_time"                    , OB1_TYPE   }, // 129
+    { OB1::ob1_pll_gptr                  , "ob1_pll_gptr"                , OB1_TYPE   }, // 130
+    { OB1::ob1_pll_bndy                  , "ob1_pll_bndy"                , OB1_TYPE   }, // 131
+    { OB1::ob1_pll_func                  , "ob1_pll_func"                , OB1_TYPE   }, // 132
+    { OB1::ob1_repr                      , "ob1_repr"                    , OB1_TYPE   }, // 133
+    { INVALID_RING                       , "invalid"                     , OB1_TYPE   }, // 134
+    { INVALID_RING                       , "invalid"                     , OB1_TYPE   }, // 135
+    { OB2::ob2_fure                      , "ob2_fure"                    , OB2_TYPE   }, // 136
+    { OB2::ob2_gptr                      , "ob2_gptr"                    , OB2_TYPE   }, // 137
+    { OB2::ob2_time                      , "ob2_time"                    , OB2_TYPE   }, // 138
+    { OB2::ob2_pll_gptr                  , "ob2_pll_gptr"                , OB2_TYPE   }, // 139
+    { OB2::ob2_pll_bndy                  , "ob2_pll_bndy"                , OB2_TYPE   }, // 140
+    { OB2::ob2_pll_func                  , "ob2_pll_func"                , OB2_TYPE   }, // 141
+    { OB2::ob2_repr                      , "ob2_repr"                    , OB2_TYPE   }, // 142
+    { INVALID_RING                       , "invalid"                     , OB2_TYPE   }, // 143
+    { INVALID_RING                       , "invalid"                     , OB2_TYPE   }, // 144
+    { OB3::ob3_fure                      , "ob3_fure"                    , OB3_TYPE   }, // 145
+    { OB3::ob3_gptr                      , "ob3_gptr"                    , OB3_TYPE   }, // 146
+    { OB3::ob3_time                      , "ob3_time"                    , OB3_TYPE   }, // 147
+    { OB3::ob3_pll_gptr                  , "ob3_pll_gptr"                , OB3_TYPE   }, // 148
+    { OB3::ob3_pll_bndy                  , "ob3_pll_bndy"                , OB3_TYPE   }, // 149
+    { OB3::ob3_pll_func                  , "ob3_pll_func"                , OB3_TYPE   }, // 150
+    { OB3::ob3_repr                      , "ob3_repr"                    , OB3_TYPE   }, // 151
+    { INVALID_RING                       , "invalid"                     , OB3_TYPE   }, // 152
+    { INVALID_RING                       , "invalid"                     , OB3_TYPE   }, // 153
+    { PCI0::pci0_fure                    , "pci0_fure"                   , PCI0_TYPE  }, // 154
+    { PCI0::pci0_gptr                    , "pci0_gptr"                   , PCI0_TYPE  }, // 155
+    { PCI0::pci0_time                    , "pci0_time"                   , PCI0_TYPE  }, // 156
+    { PCI0::pci0_pll_bndy                , "pci0_pll_bndy"               , PCI0_TYPE  }, // 157
+    { PCI0::pci0_pll_gptr                , "pci0_pll_gptr"               , PCI0_TYPE  }, // 158
+    { PCI0::pci0_repr                    , "pci0_repr"                   , PCI0_TYPE  }, // 159
+    { PCI1::pci1_fure                    , "pci1_fure"                   , PCI1_TYPE  }, // 160
+    { PCI1::pci1_gptr                    , "pci1_gptr"                   , PCI1_TYPE  }, // 161
+    { PCI1::pci1_time                    , "pci1_time"                   , PCI1_TYPE  }, // 162
+    { PCI1::pci1_pll_bndy                , "pci1_pll_bndy"               , PCI1_TYPE  }, // 163
+    { PCI1::pci1_pll_gptr                , "pci1_pll_gptr"               , PCI1_TYPE  }, // 164
+    { PCI1::pci1_repr                    , "pci1_repr"                   , PCI1_TYPE  }, // 165
+    { PCI2::pci2_fure                    , "pci2_fure"                   , PCI2_TYPE  }, // 166
+    { PCI2::pci2_gptr                    , "pci2_gptr"                   , PCI2_TYPE  }, // 167
+    { PCI2::pci2_time                    , "pci2_time"                   , PCI2_TYPE  }, // 168
+    { PCI2::pci2_pll_bndy                , "pci2_pll_bndy"               , PCI2_TYPE  }, // 169
+    { PCI2::pci2_pll_gptr                , "pci2_pll_gptr"               , PCI2_TYPE  }, // 170
+    { PCI2::pci2_repr                    , "pci2_repr"                   , PCI2_TYPE  }, // 171
+    { EQ::eq_fure                        , "eq_fure"                     , EQ_TYPE    }, // 172
+    { EQ::eq_gptr                        , "eq_gptr"                     , EQ_TYPE    }, // 173
+    { EQ::eq_time                        , "eq_time"                     , EQ_TYPE    }, // 174
+    { EQ::eq_mode                        , "eq_mode"                     , EQ_TYPE    }, // 175
+    { EQ::ex_l3_fure                     , "ex_l3_fure"                  , EQ_TYPE    }, // 176
+    { EQ::ex_l3_gptr                     , "ex_l3_gptr"                  , EQ_TYPE    }, // 177
+    { EQ::ex_l3_time                     , "ex_l3_time"                  , EQ_TYPE    }, // 178
+    { EQ::ex_l2_mode                     , "ex_l2_mode"                  , EQ_TYPE    }, // 179
+    { EQ::ex_l2_fure                     , "ex_l2_fure"                  , EQ_TYPE    }, // 180
+    { EQ::ex_l2_gptr                     , "ex_l2_gptr"                  , EQ_TYPE    }, // 181
+    { EQ::ex_l2_time                     , "ex_l2_time"                  , EQ_TYPE    }, // 182
+    { EQ::ex_l3_refr_fure                , "ex_l3_refr_fure"             , EQ_TYPE    }, // 183
+    { EQ::ex_l3_refr_gptr                , "ex_l3_refr_gptr"             , EQ_TYPE    }, // 184
+    { EQ::ex_l3_refr_time                , "ex_l3_refr_time"             , EQ_TYPE    }, // 185
+    { EQ::eq_ana_func                    , "eq_ana_func"                 , EQ_TYPE    }, // 186
+    { EQ::eq_ana_gptr                    , "eq_ana_gptr"                 , EQ_TYPE    }, // 187
+    { EQ::eq_dpll_func                   , "eq_dpll_func"                , EQ_TYPE    }, // 188
+    { EQ::eq_dpll_gptr                   , "eq_dpll_gptr"                , EQ_TYPE    }, // 189
+    { EQ::eq_dpll_mode                   , "eq_dpll_mode"                , EQ_TYPE    }, // 190
+    { EQ::eq_ana_bndy                    , "eq_ana_bndy"                 , EQ_TYPE    }, // 191
+    { EQ::eq_ana_bndy_bucket_0           , "eq_ana_bndy_bucket_0"        , EQ_TYPE    }, // 192
+    { EQ::eq_ana_bndy_bucket_1           , "eq_ana_bndy_bucket_1"        , EQ_TYPE    }, // 193
+    { EQ::eq_ana_bndy_bucket_2           , "eq_ana_bndy_bucket_2"        , EQ_TYPE    }, // 194
+    { EQ::eq_ana_bndy_bucket_3           , "eq_ana_bndy_bucket_3"        , EQ_TYPE    }, // 195
+    { EQ::eq_ana_bndy_bucket_4           , "eq_ana_bndy_bucket_4"        , EQ_TYPE    }, // 196
+    { EQ::eq_ana_bndy_bucket_5           , "eq_ana_bndy_bucket_5"        , EQ_TYPE    }, // 197
+    { EQ::eq_ana_bndy_bucket_6           , "eq_ana_bndy_bucket_6"        , EQ_TYPE    }, // 198
+    { EQ::eq_ana_bndy_bucket_7           , "eq_ana_bndy_bucket_7"        , EQ_TYPE    }, // 199
+    { EQ::eq_ana_bndy_bucket_8           , "eq_ana_bndy_bucket_8"        , EQ_TYPE    }, // 200
+    { EQ::eq_ana_bndy_bucket_9           , "eq_ana_bndy_bucket_9"        , EQ_TYPE    }, // 201
+    { EQ::eq_ana_bndy_bucket_10          , "eq_ana_bndy_bucket_10"       , EQ_TYPE    }, // 202
+    { EQ::eq_ana_bndy_bucket_11          , "eq_ana_bndy_bucket_11"       , EQ_TYPE    }, // 203
+    { EQ::eq_ana_bndy_bucket_12          , "eq_ana_bndy_bucket_12"       , EQ_TYPE    }, // 204
+    { EQ::eq_ana_bndy_bucket_13          , "eq_ana_bndy_bucket_13"       , EQ_TYPE    }, // 205
+    { EQ::eq_ana_bndy_bucket_14          , "eq_ana_bndy_bucket_14"       , EQ_TYPE    }, // 206
+    { EQ::eq_ana_bndy_bucket_15          , "eq_ana_bndy_bucket_15"       , EQ_TYPE    }, // 207
+    { EQ::eq_ana_bndy_bucket_16          , "eq_ana_bndy_bucket_16"       , EQ_TYPE    }, // 208
+    { EQ::eq_ana_bndy_bucket_17          , "eq_ana_bndy_bucket_17"       , EQ_TYPE    }, // 209
+    { EQ::eq_ana_bndy_bucket_18          , "eq_ana_bndy_bucket_18"       , EQ_TYPE    }, // 210
+    { EQ::eq_ana_bndy_bucket_19          , "eq_ana_bndy_bucket_19"       , EQ_TYPE    }, // 211
+    { EQ::eq_ana_bndy_bucket_20          , "eq_ana_bndy_bucket_20"       , EQ_TYPE    }, // 212
+    { EQ::eq_ana_bndy_bucket_21          , "eq_ana_bndy_bucket_21"       , EQ_TYPE    }, // 213
+    { EQ::eq_ana_bndy_bucket_22          , "eq_ana_bndy_bucket_22"       , EQ_TYPE    }, // 214
+    { EQ::eq_ana_bndy_bucket_23          , "eq_ana_bndy_bucket_23"       , EQ_TYPE    }, // 215
+    { EQ::eq_ana_bndy_bucket_24          , "eq_ana_bndy_bucket_24"       , EQ_TYPE    }, // 216
+    { EQ::eq_ana_bndy_bucket_25          , "eq_ana_bndy_bucket_25"       , EQ_TYPE    }, // 217
+    { EQ::eq_ana_bndy_l3dcc_bucket_26    , "eq_ana_bndy_l3dcc_bucket_26" , EQ_TYPE    }, // 218
+    { EQ::eq_ana_mode                    , "eq_ana_mode"                 , EQ_TYPE    }, // 219
+    { EQ::eq_repr                        , "eq_repr"                     , EQ_TYPE    }, // 220
+    { EQ::ex_l3_repr                     , "ex_l3_repr"                  , EQ_TYPE    }, // 221
+    { EQ::ex_l2_repr                     , "ex_l2_repr"                  , EQ_TYPE    }, // 222
+    { EQ::ex_l3_refr_repr                , "ex_l3_refr_repr"             , EQ_TYPE    }, // 223
+    { EC::ec_func                        , "ec_func"                     , EC_TYPE    }, // 224
+    { EC::ec_gptr                        , "ec_gptr"                     , EC_TYPE    }, // 225
+    { EC::ec_time                        , "ec_time"                     , EC_TYPE    }, // 226
+    { EC::ec_mode                        , "ec_mode"                     , EC_TYPE    }, // 227
+    { EC::ec_repr                        , "ec_repr"                     , EC_TYPE    }, // 228
+};
+#endif
+#ifdef __PPE__
+static const ringProperties_t RING_PROPERTIES[P9_NUM_RINGS] =
+{
+    { PERV::perv_fure                    , PERV_TYPE  }, // 0
+    { PERV::perv_gptr                    , PERV_TYPE  }, // 1
+    { PERV::perv_time                    , PERV_TYPE  }, // 2
+    { PERV::occ_fure                     , PERV_TYPE  }, // 3
+    { PERV::occ_gptr                     , PERV_TYPE  }, // 4
+    { PERV::occ_time                     , PERV_TYPE  }, // 5
+    { PERV::perv_ana_func                , PERV_TYPE  }, // 6
+    { PERV::perv_ana_gptr                , PERV_TYPE  }, // 7
+    { PERV::perv_pll_gptr                , PERV_TYPE  }, // 8
+    { PERV::perv_pll_bndy                , PERV_TYPE  }, // 9
+    { PERV::perv_pll_bndy_bucket_1       , PERV_TYPE  }, // 10
+    { PERV::perv_pll_bndy_bucket_2       , PERV_TYPE  }, // 11
+    { PERV::perv_pll_bndy_bucket_3       , PERV_TYPE  }, // 12
+    { PERV::perv_pll_bndy_bucket_4       , PERV_TYPE  }, // 13
+    { PERV::perv_pll_bndy_bucket_5       , PERV_TYPE  }, // 14
+    { PERV::perv_pll_func                , PERV_TYPE  }, // 15
+    { PERV::perv_pibnet_gptr             , PERV_TYPE  }, // 16
+    { PERV::perv_pibnet_time             , PERV_TYPE  }, // 17
+    { PERV::perv_repr                    , PERV_TYPE  }, // 18
+    { PERV::occ_repr                     , PERV_TYPE  }, // 19
+    { PERV::perv_pibnet_repr             , PERV_TYPE  }, // 20
+    { N0::n0_fure                        , N0_TYPE    }, // 21
+    { N0::n0_gptr                        , N0_TYPE    }, // 22
+    { N0::n0_time                        , N0_TYPE    }, // 23
+    { N0::n0_nx_fure                     , N0_TYPE    }, // 24
+    { N0::n0_nx_gptr                     , N0_TYPE    }, // 25
+    { N0::n0_nx_time                     , N0_TYPE    }, // 26
+    { N0::n0_cxa0_fure                   , N0_TYPE    }, // 27
+    { N0::n0_cxa0_gptr                   , N0_TYPE    }, // 28
+    { N0::n0_cxa0_time                   , N0_TYPE    }, // 29
+    { N0::n0_repr                        , N0_TYPE    }, // 30
+    { N0::n0_nx_repr                     , N0_TYPE    }, // 31
+    { N0::n0_cxa0_repr                   , N0_TYPE    }, // 32
+    { N1::n1_fure                        , N1_TYPE    }, // 33
+    { N1::n1_gptr                        , N1_TYPE    }, // 34
+    { N1::n1_time                        , N1_TYPE    }, // 35
+    { N1::n1_ioo0_fure                   , N1_TYPE    }, // 36
+    { N1::n1_ioo0_gptr                   , N1_TYPE    }, // 37
+    { N1::n1_ioo0_time                   , N1_TYPE    }, // 38
+    { N1::n1_ioo1_fure                   , N1_TYPE    }, // 39
+    { N1::n1_ioo1_gptr                   , N1_TYPE    }, // 40
+    { N1::n1_ioo1_time                   , N1_TYPE    }, // 41
+    { N1::n1_mcs23_fure                  , N1_TYPE    }, // 42
+    { N1::n1_mcs23_gptr                  , N1_TYPE    }, // 43
+    { N1::n1_mcs23_time                  , N1_TYPE    }, // 44
+    { N1::n1_repr                        , N1_TYPE    }, // 45
+    { N1::n1_ioo0_repr                   , N1_TYPE    }, // 46
+    { N1::n1_ioo1_repr                   , N1_TYPE    }, // 47
+    { N1::n1_mcs23_repr                  , N1_TYPE    }, // 48
+    { N2::n2_fure                        , N2_TYPE    }, // 49
+    { N2::n2_gptr                        , N2_TYPE    }, // 50
+    { N2::n2_time                        , N2_TYPE    }, // 51
+    { N2::n2_cxa1_fure                   , N2_TYPE    }, // 52
+    { N2::n2_cxa1_gptr                   , N2_TYPE    }, // 53
+    { N2::n2_cxa1_time                   , N2_TYPE    }, // 54
+    { N2::n2_psi_fure                    , N2_TYPE    }, // 55
+    { N2::n2_psi_gptr                    , N2_TYPE    }, // 56
+    { N2::n2_psi_time                    , N2_TYPE    }, // 57
+    { N2::n2_repr                        , N2_TYPE    }, // 58
+    { N2::n2_cxa1_repr                   , N2_TYPE    }, // 59
+    { N2::n2_psi_repr                    , N2_TYPE    }, // 60
+    { INVALID_RING                       , N2_TYPE    }, // 61
+    { N3::n3_fure                        , N3_TYPE    }, // 62
+    { N3::n3_gptr                        , N3_TYPE    }, // 63
+    { N3::n3_time                        , N3_TYPE    }, // 64
+    { N3::n3_mcs01_fure                  , N3_TYPE    }, // 65
+    { N3::n3_mcs01_gptr                  , N3_TYPE    }, // 66
+    { N3::n3_mcs01_time                  , N3_TYPE    }, // 67
+    { N3::n3_np_fure                     , N3_TYPE    }, // 68
+    { N3::n3_np_gptr                     , N3_TYPE    }, // 69
+    { N3::n3_np_time                     , N3_TYPE    }, // 70
+    { N3::n3_repr                        , N3_TYPE    }, // 71
+    { N3::n3_mcs01_repr                  , N3_TYPE    }, // 72
+    { N3::n3_np_repr                     , N3_TYPE    }, // 73
+    { INVALID_RING                       , N3_TYPE    }, // 74
+    { XB::xb_fure                        , XB_TYPE    }, // 75
+    { XB::xb_gptr                        , XB_TYPE    }, // 76
+    { XB::xb_time                        , XB_TYPE    }, // 77
+    { XB::xb_io0_fure                    , XB_TYPE    }, // 78
+    { XB::xb_io0_gptr                    , XB_TYPE    }, // 79
+    { XB::xb_io0_time                    , XB_TYPE    }, // 80
+    { XB::xb_io1_fure                    , XB_TYPE    }, // 81
+    { XB::xb_io1_gptr                    , XB_TYPE    }, // 82
+    { XB::xb_io1_time                    , XB_TYPE    }, // 83
+    { XB::xb_io2_fure                    , XB_TYPE    }, // 84
+    { XB::xb_io2_gptr                    , XB_TYPE    }, // 85
+    { XB::xb_io2_time                    , XB_TYPE    }, // 86
+    { XB::xb_pll_gptr                    , XB_TYPE    }, // 87
+    { XB::xb_pll_bndy                    , XB_TYPE    }, // 88
+    { XB::xb_pll_func                    , XB_TYPE    }, // 89
+    { XB::xb_repr                        , XB_TYPE    }, // 90
+    { XB::xb_io0_repr                    , XB_TYPE    }, // 91
+    { XB::xb_io1_repr                    , XB_TYPE    }, // 92
+    { XB::xb_io2_repr                    , XB_TYPE    }, // 93
+    { INVALID_RING                       , XB_TYPE    }, // 94
+    { INVALID_RING                       , XB_TYPE    }, // 95
+    { MC::mc_fure                        , MC_TYPE    }, // 96
+    { MC::mc_gptr                        , MC_TYPE    }, // 97
+    { MC::mc_time                        , MC_TYPE    }, // 98
+    { MC::mc_iom01_fure                  , MC_TYPE    }, // 99
+    { MC::mc_iom01_gptr                  , MC_TYPE    }, // 100
+    { MC::mc_iom01_time                  , MC_TYPE    }, // 101
+    { MC::mc_iom23_fure                  , MC_TYPE    }, // 102
+    { MC::mc_iom23_gptr                  , MC_TYPE    }, // 103
+    { MC::mc_iom23_time                  , MC_TYPE    }, // 104
+    { MC::mc_pll_gptr                    , MC_TYPE    }, // 105
+    { MC::mc_pll_bndy                    , MC_TYPE    }, // 106
+    { MC::mc_pll_bndy_bucket_1           , MC_TYPE    }, // 107
+    { MC::mc_pll_bndy_bucket_2           , MC_TYPE    }, // 108
+    { MC::mc_pll_bndy_bucket_3           , MC_TYPE    }, // 109
+    { MC::mc_pll_bndy_bucket_4           , MC_TYPE    }, // 110
+    { MC::mc_pll_bndy_bucket_5           , MC_TYPE    }, // 111
+    { MC::mc_pll_func                    , MC_TYPE    }, // 112
+    { MC::mc_repr                        , MC_TYPE    }, // 113
+    { MC::mc_iom01_repr                  , MC_TYPE    }, // 114
+    { MC::mc_iom23_repr                  , MC_TYPE    }, // 115
+    { INVALID_RING                       , MC_TYPE    }, // 116
+    { INVALID_RING                       , MC_TYPE    }, // 117
+    { OB0::ob0_fure                      , OB0_TYPE   }, // 118
+    { OB0::ob0_gptr                      , OB0_TYPE   }, // 119
+    { OB0::ob0_time                      , OB0_TYPE   }, // 120
+    { OB0::ob0_pll_gptr                  , OB0_TYPE   }, // 121
+    { OB0::ob0_pll_bndy                  , OB0_TYPE   }, // 122
+    { OB0::ob0_pll_func                  , OB0_TYPE   }, // 123
+    { OB0::ob0_repr                      , OB0_TYPE   }, // 124
+    { INVALID_RING                       , OB0_TYPE   }, // 125
+    { INVALID_RING                       , OB0_TYPE   }, // 126
+    { OB1::ob1_fure                      , OB1_TYPE   }, // 127
+    { OB1::ob1_gptr                      , OB1_TYPE   }, // 128
+    { OB1::ob1_time                      , OB1_TYPE   }, // 129
+    { OB1::ob1_pll_gptr                  , OB1_TYPE   }, // 130
+    { OB1::ob1_pll_bndy                  , OB1_TYPE   }, // 131
+    { OB1::ob1_pll_func                  , OB1_TYPE   }, // 132
+    { OB1::ob1_repr                      , OB1_TYPE   }, // 133
+    { INVALID_RING                       , OB1_TYPE   }, // 134
+    { INVALID_RING                       , OB1_TYPE   }, // 135
+    { OB2::ob2_fure                      , OB2_TYPE   }, // 136
+    { OB2::ob2_gptr                      , OB2_TYPE   }, // 137
+    { OB2::ob2_time                      , OB2_TYPE   }, // 138
+    { OB2::ob2_pll_gptr                  , OB2_TYPE   }, // 139
+    { OB2::ob2_pll_bndy                  , OB2_TYPE   }, // 140
+    { OB2::ob2_pll_func                  , OB2_TYPE   }, // 141
+    { OB2::ob2_repr                      , OB2_TYPE   }, // 142
+    { INVALID_RING                       , OB2_TYPE   }, // 143
+    { INVALID_RING                       , OB2_TYPE   }, // 144
+    { OB3::ob3_fure                      , OB3_TYPE   }, // 145
+    { OB3::ob3_gptr                      , OB3_TYPE   }, // 146
+    { OB3::ob3_time                      , OB3_TYPE   }, // 147
+    { OB3::ob3_pll_gptr                  , OB3_TYPE   }, // 148
+    { OB3::ob3_pll_bndy                  , OB3_TYPE   }, // 149
+    { OB3::ob3_pll_func                  , OB3_TYPE   }, // 150
+    { OB3::ob3_repr                      , OB3_TYPE   }, // 151
+    { INVALID_RING                       , OB3_TYPE   }, // 152
+    { INVALID_RING                       , OB3_TYPE   }, // 153
+    { PCI0::pci0_fure                    , PCI0_TYPE  }, // 154
+    { PCI0::pci0_gptr                    , PCI0_TYPE  }, // 155
+    { PCI0::pci0_time                    , PCI0_TYPE  }, // 156
+    { PCI0::pci0_pll_bndy                , PCI0_TYPE  }, // 157
+    { PCI0::pci0_pll_gptr                , PCI0_TYPE  }, // 158
+    { PCI0::pci0_repr                    , PCI0_TYPE  }, // 159
+    { PCI1::pci1_fure                    , PCI1_TYPE  }, // 160
+    { PCI1::pci1_gptr                    , PCI1_TYPE  }, // 161
+    { PCI1::pci1_time                    , PCI1_TYPE  }, // 162
+    { PCI1::pci1_pll_bndy                , PCI1_TYPE  }, // 163
+    { PCI1::pci1_pll_gptr                , PCI1_TYPE  }, // 164
+    { PCI1::pci1_repr                    , PCI1_TYPE  }, // 165
+    { PCI2::pci2_fure                    , PCI2_TYPE  }, // 166
+    { PCI2::pci2_gptr                    , PCI2_TYPE  }, // 167
+    { PCI2::pci2_time                    , PCI2_TYPE  }, // 168
+    { PCI2::pci2_pll_bndy                , PCI2_TYPE  }, // 169
+    { PCI2::pci2_pll_gptr                , PCI2_TYPE  }, // 170
+    { PCI2::pci2_repr                    , PCI2_TYPE  }, // 171
+    { EQ::eq_fure                        , EQ_TYPE    }, // 172
+    { EQ::eq_gptr                        , EQ_TYPE    }, // 173
+    { EQ::eq_time                        , EQ_TYPE    }, // 174
+    { EQ::eq_mode                        , EQ_TYPE    }, // 175
+    { EQ::ex_l3_fure                     , EQ_TYPE    }, // 176
+    { EQ::ex_l3_gptr                     , EQ_TYPE    }, // 177
+    { EQ::ex_l3_time                     , EQ_TYPE    }, // 178
+    { EQ::ex_l2_mode                     , EQ_TYPE    }, // 179
+    { EQ::ex_l2_fure                     , EQ_TYPE    }, // 180
+    { EQ::ex_l2_gptr                     , EQ_TYPE    }, // 181
+    { EQ::ex_l2_time                     , EQ_TYPE    }, // 182
+    { EQ::ex_l3_refr_fure                , EQ_TYPE    }, // 183
+    { EQ::ex_l3_refr_gptr                , EQ_TYPE    }, // 184
+    { EQ::ex_l3_refr_time                , EQ_TYPE    }, // 185
+    { EQ::eq_ana_func                    , EQ_TYPE    }, // 186
+    { EQ::eq_ana_gptr                    , EQ_TYPE    }, // 187
+    { EQ::eq_dpll_func                   , EQ_TYPE    }, // 188
+    { EQ::eq_dpll_gptr                   , EQ_TYPE    }, // 189
+    { EQ::eq_dpll_mode                   , EQ_TYPE    }, // 190
+    { EQ::eq_ana_bndy                    , EQ_TYPE    }, // 191
+    { EQ::eq_ana_bndy_bucket_0           , EQ_TYPE    }, // 192
+    { EQ::eq_ana_bndy_bucket_1           , EQ_TYPE    }, // 193
+    { EQ::eq_ana_bndy_bucket_2           , EQ_TYPE    }, // 194
+    { EQ::eq_ana_bndy_bucket_3           , EQ_TYPE    }, // 195
+    { EQ::eq_ana_bndy_bucket_4           , EQ_TYPE    }, // 196
+    { EQ::eq_ana_bndy_bucket_5           , EQ_TYPE    }, // 197
+    { EQ::eq_ana_bndy_bucket_6           , EQ_TYPE    }, // 198
+    { EQ::eq_ana_bndy_bucket_7           , EQ_TYPE    }, // 199
+    { EQ::eq_ana_bndy_bucket_8           , EQ_TYPE    }, // 200
+    { EQ::eq_ana_bndy_bucket_9           , EQ_TYPE    }, // 201
+    { EQ::eq_ana_bndy_bucket_10          , EQ_TYPE    }, // 202
+    { EQ::eq_ana_bndy_bucket_11          , EQ_TYPE    }, // 203
+    { EQ::eq_ana_bndy_bucket_12          , EQ_TYPE    }, // 204
+    { EQ::eq_ana_bndy_bucket_13          , EQ_TYPE    }, // 205
+    { EQ::eq_ana_bndy_bucket_14          , EQ_TYPE    }, // 206
+    { EQ::eq_ana_bndy_bucket_15          , EQ_TYPE    }, // 207
+    { EQ::eq_ana_bndy_bucket_16          , EQ_TYPE    }, // 208
+    { EQ::eq_ana_bndy_bucket_17          , EQ_TYPE    }, // 209
+    { EQ::eq_ana_bndy_bucket_18          , EQ_TYPE    }, // 210
+    { EQ::eq_ana_bndy_bucket_19          , EQ_TYPE    }, // 211
+    { EQ::eq_ana_bndy_bucket_20          , EQ_TYPE    }, // 212
+    { EQ::eq_ana_bndy_bucket_21          , EQ_TYPE    }, // 213
+    { EQ::eq_ana_bndy_bucket_22          , EQ_TYPE    }, // 214
+    { EQ::eq_ana_bndy_bucket_23          , EQ_TYPE    }, // 215
+    { EQ::eq_ana_bndy_bucket_24          , EQ_TYPE    }, // 216
+    { EQ::eq_ana_bndy_bucket_25          , EQ_TYPE    }, // 217
+    { EQ::eq_ana_bndy_l3dcc_bucket_26    , EQ_TYPE    }, // 218
+    { EQ::eq_ana_mode                    , EQ_TYPE    }, // 219
+    { EQ::eq_repr                        , EQ_TYPE    }, // 220
+    { EQ::ex_l3_repr                     , EQ_TYPE    }, // 221
+    { EQ::ex_l2_repr                     , EQ_TYPE    }, // 222
+    { EQ::ex_l3_refr_repr                , EQ_TYPE    }, // 223
+    { EC::ec_func                        , EC_TYPE    }, // 224
+    { EC::ec_gptr                        , EC_TYPE    }, // 225
+    { EC::ec_time                        , EC_TYPE    }, // 226
+    { EC::ec_mode                        , EC_TYPE    }, // 227
+    { EC::ec_repr                        , EC_TYPE    }, // 228
+};
+#endif
+
+#endif
diff --git a/src/import/chips/p9/utils/imageProcs/p9_ring_id.h b/src/import/chips/p9/utils/imageProcs/p9_ring_id.h
new file mode 100644
index 00000000..55f9ad75
--- /dev/null
+++ b/src/import/chips/p9/utils/imageProcs/p9_ring_id.h
@@ -0,0 +1,331 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/utils/imageProcs/p9_ring_id.h $               */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef _P9_RINGID_ENUM_H_
+#define _P9_RINGID_ENUM_H_
+
+///
+/// @enum RingID
+/// @brief Enumeration of Ring ID values. These values are used to traverse
+///        an image having Ring Containers.
+// NOTE: Do not change the numbering, the sequence or add new constants to
+//       the below enum, unless you know the effect it has on the traversing
+//       of the image for Ring Containers.
+enum RingID
+{
+    //*****************************
+    // Rings needed for SBE - Start
+    //*****************************
+    // Perv Chiplet Rings
+    perv_fure = 0,
+    perv_gptr = 1,
+    perv_time = 2,
+    occ_fure = 3,
+    occ_gptr = 4,
+    occ_time = 5,
+    perv_ana_func = 6,
+    perv_ana_gptr = 7,
+    perv_pll_gptr = 8,
+    perv_pll_bndy = 9,
+    perv_pll_bndy_bucket_1 = 10,
+    perv_pll_bndy_bucket_2 = 11,
+    perv_pll_bndy_bucket_3 = 12,
+    perv_pll_bndy_bucket_4 = 13,
+    perv_pll_bndy_bucket_5 = 14,
+    perv_pll_func = 15,
+    perv_pibnet_gptr = 16,
+    perv_pibnet_time = 17,
+    perv_repr = 18,
+    occ_repr = 19,
+    perv_pibnet_repr = 20,
+
+    // Nest Chiplet Rings - N0
+    n0_fure = 21,
+    n0_gptr = 22,
+    n0_time = 23,
+    n0_nx_fure = 24,
+    n0_nx_gptr = 25,
+    n0_nx_time = 26,
+    n0_cxa0_fure = 27,
+    n0_cxa0_gptr = 28,
+    n0_cxa0_time = 29,
+    n0_repr = 30,
+    n0_nx_repr = 31,
+    n0_cxa0_repr = 32,
+
+    // Nest Chiplet Rings - N1
+    n1_fure = 33,
+    n1_gptr = 34,
+    n1_time = 35,
+    n1_ioo0_fure = 36,
+    n1_ioo0_gptr = 37,
+    n1_ioo0_time = 38,
+    n1_ioo1_fure = 39,
+    n1_ioo1_gptr = 40,
+    n1_ioo1_time = 41,
+    n1_mcs23_fure = 42,
+    n1_mcs23_gptr = 43,
+    n1_mcs23_time = 44,
+    n1_repr = 45,
+    n1_ioo0_repr = 46,
+    n1_ioo1_repr = 47,
+    n1_mcs23_repr = 48,
+
+    // Nest Chiplet Rings - N2
+    n2_fure = 49,
+    n2_gptr = 50,
+    n2_time = 51,
+    n2_cxa1_fure = 52,
+    n2_cxa1_gptr = 53,
+    n2_cxa1_time = 54,
+    n2_psi_fure = 55,
+    n2_psi_gptr = 56,
+    n2_psi_time = 57,
+    n2_repr = 58,
+    n2_cxa1_repr = 59,
+    n2_psi_repr = 60,
+    // values 61 unused
+
+    // Nest Chiplet Rings - N3
+    n3_fure = 62,
+    n3_gptr = 63,
+    n3_time = 64,
+    n3_mcs01_fure = 65,
+    n3_mcs01_gptr = 66,
+    n3_mcs01_time = 67,
+    n3_np_fure = 68,
+    n3_np_gptr = 69,
+    n3_np_time = 70,
+    n3_repr = 71,
+    n3_mcs01_repr = 72,
+    n3_np_repr = 73,
+    // values 74 unused
+
+    // X-Bus Chiplet Rings
+    // Common - apply to all instances of X-Bus
+    xb_fure = 75,
+    xb_gptr = 76,
+    xb_time = 77,
+    xb_io0_fure = 78,
+    xb_io0_gptr = 79,
+    xb_io0_time = 80,
+    xb_io1_fure = 81,
+    xb_io1_gptr = 82,
+    xb_io1_time = 83,
+    xb_io2_fure = 84,
+    xb_io2_gptr = 85,
+    xb_io2_time = 86,
+    xb_pll_gptr = 87,
+    xb_pll_bndy  = 88,
+    xb_pll_func = 89,
+
+    // X-Bus Chiplet Rings
+    // X0, X1 and X2 instance specific Rings
+    xb_repr = 90,
+    xb_io0_repr = 91,
+    xb_io1_repr = 92,
+    xb_io2_repr = 93,
+    // values 94-95 unused
+
+    // MC Chiplet Rings
+    // Common - apply to all instances of MC
+    mc_fure = 96,
+    mc_gptr = 97,
+    mc_time = 98,
+    mc_iom01_fure = 99,
+    mc_iom01_gptr = 100,
+    mc_iom01_time = 101,
+    mc_iom23_fure = 102,
+    mc_iom23_gptr = 103,
+    mc_iom23_time = 104,
+    mc_pll_gptr = 105,
+    mc_pll_bndy  = 106,
+    mc_pll_bndy_bucket_1 = 107,
+    mc_pll_bndy_bucket_2 = 108,
+    mc_pll_bndy_bucket_3 = 109,
+    mc_pll_bndy_bucket_4 = 110,
+    mc_pll_bndy_bucket_5 = 111,
+    mc_pll_func = 112,
+
+    // MC Chiplet Rings
+    // MC01 and MC23 instance specific Rings
+    mc_repr = 113,
+    mc_iom01_repr = 114,
+    mc_iom23_repr = 115,
+    // values 116-117 unused
+
+    // OB Chiplet Rings
+    // Common - apply to all instances of O-Bus
+    ob0_fure = 118,
+    ob0_gptr = 119,
+    ob0_time = 120,
+    ob0_pll_gptr = 121,
+    ob0_pll_bndy  = 122,
+    ob0_pll_func = 123,
+
+    // OB Chiplet Rings
+    // OB0, OB1, OB2 and OB3 instance specific Ring
+    ob0_repr = 124,
+    // values 125-126 unused
+
+    ob1_fure = 127,
+    ob1_gptr = 128,
+    ob1_time = 129,
+    ob1_pll_gptr = 130,
+    ob1_pll_bndy  = 131,
+    ob1_pll_func = 132,
+
+    // OB Chiplet Rings
+    // OB0, OB1, OB2 and OB3 instance specific Ring
+    ob1_repr = 133,
+    // values 134-135 unused
+
+    ob2_fure = 136,
+    ob2_gptr = 137,
+    ob2_time = 138,
+    ob2_pll_gptr = 139,
+    ob2_pll_bndy  = 140,
+    ob2_pll_func = 141,
+
+    // OB Chiplet Rings
+    // OB0, OB1, OB2 and OB3 instance specific Ring
+    ob2_repr = 142,
+    // values 143-144 unused
+
+    ob3_fure = 145,
+    ob3_gptr = 146,
+    ob3_time = 147,
+    ob3_pll_gptr = 148,
+    ob3_pll_bndy  = 149,
+    ob3_pll_func = 150,
+
+    // OB Chiplet Rings
+    // OB0, OB1, OB2 and OB3 instance specific Ring
+    ob3_repr = 151,
+    // values 152-153 unused
+
+    // PCI Chiplet Rings
+    // PCI0 Common Rings
+    pci0_fure = 154,
+    pci0_gptr = 155,
+    pci0_time = 156,
+    pci0_pll_bndy = 157,
+    pci0_pll_gptr = 158,
+    // Instance specific Rings
+    pci0_repr = 159,
+
+    // PCI1 Common Rings
+    pci1_fure = 160,
+    pci1_gptr = 161,
+    pci1_time = 162,
+    pci1_pll_bndy = 163,
+    pci1_pll_gptr = 164,
+    // Instance specific Rings
+    pci1_repr = 165,
+
+    // PCI2 Common Rings
+    pci2_fure = 166,
+    pci2_gptr = 167,
+    pci2_time = 168,
+    pci2_pll_bndy = 169,
+    pci2_pll_gptr = 170,
+    // Instance specific Rings
+    pci2_repr = 171,
+
+    // Quad Chiplet Rings
+    // Common - apply to all Quad instances
+    eq_fure = 172,
+    eq_gptr = 173,
+    eq_time = 174,
+    eq_mode = 175,
+    ex_l3_fure = 176,
+    ex_l3_gptr = 177,
+    ex_l3_time = 178,
+    ex_l2_mode = 179,
+    ex_l2_fure = 180,
+    ex_l2_gptr = 181,
+    ex_l2_time = 182,
+    ex_l3_refr_fure = 183,
+    ex_l3_refr_gptr = 184,
+    ex_l3_refr_time = 185,
+    eq_ana_func = 186,
+    eq_ana_gptr = 187,
+    eq_dpll_func = 188,
+    eq_dpll_gptr = 189,
+    eq_dpll_mode = 190,
+    eq_ana_bndy = 191,
+    eq_ana_bndy_bucket_0 = 192,
+    eq_ana_bndy_bucket_1 = 193,
+    eq_ana_bndy_bucket_2 = 194,
+    eq_ana_bndy_bucket_3 = 195,
+    eq_ana_bndy_bucket_4 = 196,
+    eq_ana_bndy_bucket_5 = 197,
+    eq_ana_bndy_bucket_6 = 198,
+    eq_ana_bndy_bucket_7 = 199,
+    eq_ana_bndy_bucket_8 = 200,
+    eq_ana_bndy_bucket_9 = 201,
+    eq_ana_bndy_bucket_10 = 202,
+    eq_ana_bndy_bucket_11 = 203,
+    eq_ana_bndy_bucket_12 = 204,
+    eq_ana_bndy_bucket_13 = 205,
+    eq_ana_bndy_bucket_14 = 206,
+    eq_ana_bndy_bucket_15 = 207,
+    eq_ana_bndy_bucket_16 = 208,
+    eq_ana_bndy_bucket_17 = 209,
+    eq_ana_bndy_bucket_18 = 210,
+    eq_ana_bndy_bucket_19 = 211,
+    eq_ana_bndy_bucket_20 = 212,
+    eq_ana_bndy_bucket_21 = 213,
+    eq_ana_bndy_bucket_22 = 214,
+    eq_ana_bndy_bucket_23 = 215,
+    eq_ana_bndy_bucket_24 = 216,
+    eq_ana_bndy_bucket_25 = 217,
+    eq_ana_bndy_l3dcc_bucket_26 = 218,
+    eq_ana_mode = 219,
+
+    // Quad Chiplet Rings
+    // EQ0 - EQ5 instance specific Rings
+    eq_repr = 220,
+    ex_l3_repr = 221,
+    ex_l2_repr = 222,
+    ex_l3_refr_repr = 223,
+
+    // Core Chiplet Rings
+    // Common - apply to all Core instances
+    ec_func = 224,
+    ec_gptr = 225,
+    ec_time = 226,
+    ec_mode = 227,
+
+    // Core Chiplet Rings
+    // EC0 - EC23 instance specific Ring
+    ec_repr = 228,
+    //***************************
+    // Rings needed for SBE - End
+    //***************************
+
+    P9_NUM_RINGS // This shoud always be the last constant
+}; // end of enum RingID
+
+#endif  // _P9_RINGID_ENUM_H_
diff --git a/src/import/chips/p9/utils/imageProcs/p9_scan_compression.H b/src/import/chips/p9/utils/imageProcs/p9_scan_compression.H
new file mode 100644
index 00000000..d20c2f04
--- /dev/null
+++ b/src/import/chips/p9/utils/imageProcs/p9_scan_compression.H
@@ -0,0 +1,393 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/utils/imageProcs/p9_scan_compression.H $      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __P9_SCAN_COMPRESSION_H__
+#define __P9_SCAN_COMPRESSION_H__
+
+/// This header declares and documents the entry points defined in
+/// p9_scan_compression.C.  Some constants are also required by the scan
+/// decompression HOMER assembly procedures.
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+/// Compressed Scan Chain Data Structure Format
+///
+/// The compressed scan ring data structure must be 8-byte aligned in
+/// memory. The container data structure consists of this 24-byte header
+/// followed by an arbitrary number of 8 byte doublewords containing the
+/// compressed scan data.  Images are always stored and processed in
+/// big-endian byte order.  This container format is common across all
+/// decompression algorithms.
+///
+/// Bytes - Content
+///
+/// 0:3 - A 32-bit "magic number" that identifies and validates the
+/// compression algorithm and algorithm version used to compress the data.
+///
+/// 4:7 - The 32-bit size of the entire data structure in \e bytes.  Thi
+/// consists of this 24-byte header plus the compressed scan data.  This value
+/// is always a multiple of 8.
+///
+/// 8:11 - This 32-bit value is reserved to the compression
+/// algorithm. Typically this field is used to record the 'size' of the
+/// compressed string in units specific to each algorithm.
+///
+/// 12:15 - The length of the original scan chain in \e bits.
+///
+/// 16:23 - The 64 bit scan Region and type details
+///
+///
+/// 24:27 - The 32 high-order bits of the value written to the Scan Select
+/// register to set up the scan.  The Scan Select register only defines these
+/// bits. (Planned to use scan scom register value)
+///
+/// 28 - The Scan Chain Data Structure version number
+///
+/// 29 - Flush-optimize : Is this byte is non-zero, the ring state to be
+/// modified is the flush state of the ring.
+///
+/// 30 - The ring ID uniquely identifying the repair ring name.
+///
+/// 31 - The 7-bit pervasive chiplet Id + Multicast bit of the chiplet to
+/// scan.  This value is loaded directly into P0.  The decompression
+/// algorithms provide two entry points - one that uses this value as the
+/// chiplet Id, and another that allows the caller to specify the chiplet Id
+/// in the call.
+
+typedef struct
+{
+
+    /// Magic number - See \ref scan_compression_magic
+    uint32_t iv_magic;
+
+    /// Total size in bytes, including the container header
+    uint32_t iv_size;
+
+    /// Reserved to the algorithm
+    uint32_t iv_algorithmReserved;
+
+    /// Length of the original scan chain in bits
+    uint32_t iv_length;
+
+    /// 64 bit scan select register value
+    uint64_t iv_scanSelect;
+
+    /// Data structure (header) version
+    uint8_t iv_headerVersion;
+
+    /// Flush-state optimization
+    ///
+    /// Normally, modifying the state of the ring requires XOR-ing the
+    /// difference state (the compressed state) with the current ring state as
+    /// it will appear in the Scan Data Register. If the current state of the
+    /// ring is the scan-0 flush state, then by definition the Scan Data
+    /// Register is always 0. Therefore we can simply write the difference to
+    /// the Scan Data Register rather than using a read-XOR-write.
+    uint8_t iv_flushOptimization;
+
+    /// Ring ID uniquely identifying the repair name. (See the list of ring
+    /// name vs ring IDs in p8_ring_identification.c).
+    uint8_t iv_ringId;
+
+    /// 7-bit pervasive chiplet Id + Multicast bit
+    ///
+    /// This field is right-justified in an 8-byte aligned doubleword so that
+    /// the P0 register can be directly updated from the doubelword value in a
+    /// data register.
+    uint8_t iv_chipletId;
+
+} CompressedScanData;
+
+
+/// Endian-translate a CompressedScanData structure
+///
+/// \param o_data A pointer to a CompressedScanData structure to receive the
+/// endian-translated form of \a i_data.
+///
+/// \param i_data A pointer to the original CompressedScanData structure.
+///
+/// This API performs an endian-converting copy of a CompressedScanData
+/// structure. This copy is guaranteed to be done in such a way that \a i_data
+/// and \a o_data may be the same pointer for in-place conversion.  Due to the
+/// symmetry of reverse, translating a structure twice is always guaranteed to
+/// return the origial structure to its original byte order.
+void
+compressed_scan_data_translate(CompressedScanData* o_data,
+                               CompressedScanData* i_data);
+
+
+/// Compress a scan string using the RS4 compression algorithm
+///
+/// \param[in,out] io_data This is a pointer to a memory area which must be
+/// large enough to hold the worst-case result of compressing \a i_string (see
+/// below).  Note that the CompressedScanData is always created in big-endian
+/// format, however the caller can use compresed_scan_data_translate() to
+/// create a copy of the header in host format.
+///
+/// \param[in] i_dataSize The size of \a io_data in bytes.
+///
+/// \param[out] o_imageSize The effective size of the entire compressed scan
+/// data structure (header + compressed data) created in \a io_data, in bytes.
+/// This value will always be a multiple of 8.
+///
+/// \param[in] i_data_str The string to compress.  Scan data to compress is
+/// left-justified in this input string.
+///
+/// \param[in] i_care_str The care mask that identifies which bits in the
+/// i_data_str that need to be scanned (written). String is left-justified.
+///
+/// \param[in] i_length The length of the input string in \e bits.  It is
+/// assumed the \a i_string contains at least (\a i_length + 7) / 8 bytes.
+///
+/// \param[in] i_scanSelect The 64-bit value written to the Scan Select
+/// register to set up for the scan.
+///
+/// \param[in] i_ringId The ring ID that uniquely identifies the ring name of
+/// a repair ring. (See p8_ring_identification.c for more info.)
+///
+/// \param[in] i_chipletId The 7-bit value for the iv_chipletId field of the
+/// CompressedScanData.
+///
+/// \param[in] i_flushOptimization This input parameter should be set to a
+/// non-0 value if it is known that this ring difference will be applied to a
+/// scan-0 flush state.  This will improve the performance of the
+/// decompress-scan routine. If the initial state of the ring is unknown, set
+/// this parameter to 0.
+///
+/// This API is required for integration with PHYP which does not support
+/// malloc().  Applications in environments supporting malloc() can use
+/// rs4_compress() instead.
+///
+/// The worst-case compression for RS4 requires 2 nibbles of control overhead
+/// per 15 nibbles of data (17/15), plus a maximum of 2 nibbles of termination.
+/// We always require this worst-case amount of memory including the header and
+/// any rounding required to guarantee that the data size is a multiple of 8
+/// bytes.  The final image size is also rounded up to a multiple of 8 bytes.
+/// If the \a i_dataSize is less than this amount (based on \a i_length) the
+/// call will fail.
+///
+/// \returns See \ref scan_compression_codes
+int
+_rs4_compress(CompressedScanData* io_data,
+              uint32_t i_dataSize,
+              uint32_t* o_imageSize,
+              const uint8_t* i_data_str,
+              const uint8_t* i_care_str,
+              const uint32_t i_length,
+              const uint64_t i_scanSelect,
+              const uint8_t i_ringId,
+              const uint8_t i_chipletId,
+              const uint8_t i_flushOptimization);
+
+
+/// Compress a scan string using the RS4 compression algorithm
+///
+/// \param[out] o_data This algorithm uses malloc() to allocate memory for the
+/// compresed data, and returns a pointer to this memory in \a o_data. After
+/// the call this memory is owned by the caller who is responsible for
+/// free()-ing the data area once it is no longer required. Note that the
+/// CompressedScanData is always created in big-endian format, however the
+/// caller can use compresed_scan_data_translate() to create a copy of the
+/// header in host format.
+///
+/// \param[out] o_size The effective size of the entire compressed scan data
+/// structure (header + compressed data) pointed to by \a o_data, in bytes.
+/// This value will always be a multiple of 8.
+///
+/// \param[in] i_data_str The string to compress.  Scan data to compress is
+/// left-justified in this input string.
+///
+/// \param[in] i_care_str The care mask that identifies which bits in the
+/// i_data_str that need to be scanned (written). String is left-justified.
+///
+/// \param[in] i_length The length of the input string in \e bits.  It is
+/// assumed the \a i_string contains at least (\a i_length + 7) / 8 bytes.
+///
+/// \param[in] i_scanSelect The 64-bit value written to the Scan Select
+/// register to set up for the scan. Only the 32 high-order bits are actually
+/// stored.
+///
+/// \param[in] i_ringId The ring ID that uniquely identifies the ring name of
+/// a repair ring. (See p8_ring_identification.c for more info.)
+///
+/// \param[in] i_chipletId The 7-bit value for the iv_chipletId field of the
+/// CompressedScanData.
+///
+/// \param[in] i_flushOptimization This input parameter should be set to a
+/// non-0 value if it is known that this ring difference will be applied to a
+/// scan-0 flush state.  This will improve the performance of the
+/// decompress-scan routine. If the initial state of the ring is unknown, set
+/// this parameter to 0.
+///
+/// \returns See \ref scan_compression_codes
+int
+rs4_compress(CompressedScanData** o_data,
+             uint32_t* o_size,
+             const uint8_t* i_data_str,
+             const uint8_t* i_care_str,
+             const uint32_t i_length,
+             const uint64_t i_scanSelect,
+             const uint8_t i_ringId,
+             const uint8_t i_chipletId,
+             const uint8_t i_flushOptimization);
+
+
+/// Decompress a scan string compressed using the RS4 compression algorithm
+///
+/// \param[in,out] io_data_str A caller-supplied data area to contain the
+/// decompressed string. The \a i_stringSize must be large enough to contain
+/// the decompressed string, which is the size of the original string in bits
+/// rounded up to the nearest byte.
+///
+/// \param[in,out] io_care_str A caller-supplied data area to contain the
+/// decompressed care mask. The \a i_stringSize must be large enough to contain
+/// the decompressed care mask, which is the size of the original string in
+/// bits rounded up to the nearest byte.
+///
+/// \param[in] i_stringSize The size (in bytes) of \a io_data_str and
+/// \a io_care_str.
+///
+/// \param[out] o_length The length of the decompressed string in \e bits.
+///
+/// \param[in] i_rs4 A pointer to the CompressedScanData header + data to be
+/// decompressed.
+///
+/// This API is required for integration with PHYP which does not support
+/// malloc().  Applications in environments supporting malloc() can use
+/// rs4_decompress() instead.
+///
+/// \returns See \ref scan_compression_codes
+int
+_rs4_decompress(uint8_t* io_data_str,
+                uint8_t* io_care_str,
+                uint32_t i_stringSize,
+                uint32_t* o_length,
+                const CompressedScanData* i_rs4);
+
+
+/// Decompress a scan string compressed using the RS4 compression algorithm
+///
+/// \param[out] o_data_str The API malloc()-s this data area to contain the
+/// decompressed string. After this call the caller owns \a o_data_str and is
+/// responsible for free()-ing this data area once it is no longer required.
+///
+/// \param[out] o_care_str The API malloc()-s this data area to contain the
+/// decompressed care mask. After this call the caller owns \a o_care_str and
+/// is responsible for free()-ing this data area once it is no longer required.
+///
+/// \param[out] o_length The length of the decompressed string and care mask
+/// in \e bits. The caller may assume that \a o_data_str and o_care_str each
+/// contain at least (\a o_length + 7) / 8 \e bytes.
+///
+/// \param[in] i_rs4 A pointer to the CompressedScanData header + data to be
+/// decompressed.
+///
+/// \returns See \ref scan_compression_codes
+int
+rs4_decompress(uint8_t** o_data_str,
+               uint8_t** o_care_str,
+               uint32_t* o_length,
+               const CompressedScanData* i_rs4);
+
+
+/// Determine if an RS4 compressed scan string is all 0
+///
+/// \param[in] i_data A pointer to the CompressedScanData header + data to be
+///
+/// \param[out] o_redundant Set to 1 if the RS4 string is the compressed form
+/// of a scan string that is all 0; Otherwise set to 0.
+///
+/// \returns See \ref scan _compression_code
+int
+rs4_redundant(const CompressedScanData* i_data, int* o_redundant);
+
+
+#endif  // __ASSEMBLER__
+
+
+/// The current version of the CompressedScanData structure
+///
+/// This constant is required to be a #define to guarantee consistency between
+/// the header format and cmopiled code.
+#define COMPRESSED_SCAN_DATA_VERSION 2
+
+/// The size of the CompressedScanData  structure
+#define COMPRESSED_SCAN_DATA_SIZE (uint8_t)24
+
+
+/// \defgroup scan_compression_magic Scan Compression Magic Numbers
+/////
+/// @ {
+
+/// RS4 Magic
+#define RS4_MAGIC (uint32_t)0x52533402       /* "RS4" + Version 0x02 */
+
+/// @}
+
+
+/// \defgroup scan_compression_codes Scan Compression Return Codes
+///
+/// @{
+
+/// Normal return code
+#define SCAN_COMPRESSION_OK (uint8_t)0
+
+/// The (de)compression algorithm could not allocate enough memory for the
+/// (de)compression.
+#define SCAN_COMPRESSION_NO_MEMORY (uint8_t)1
+
+/// Magic number mismatch on scan decompression
+#define SCAN_DECOMPRESSION_MAGIC_ERROR (uint8_t)2
+
+/// Decompression size error
+///
+/// Decompression produced a string of a size different than indicated in the
+/// header, indicating either a bug or data corruption.  Note that the entire
+/// application should be considered corrupted if this error occurs since it
+/// may not be discovered until after the decompression buffer is
+/// overrun. This error may also be returned by rs4_redundant() in the event
+/// of inconsistencies in the compressed string.
+#define SCAN_DECOMPRESSION_SIZE_ERROR (uint8_t)3
+
+/// A buffer would overflow
+///
+/// Either the caller-supplied memory buffer to _rs4_decompress() was too
+/// small to contain the decompressed string, or a caller-supplied buffer to
+/// _rs4_compress() was not large enough to hold the worst-case compressed
+/// string.
+#define SCAN_COMPRESSION_BUFFER_OVERFLOW (uint8_t)4
+
+/// Inconsistent input data
+///
+/// 1 in data is masked by 0 in care mask
+#define SCAN_COMPRESSION_INPUT_ERROR 5
+
+/// Invalid transition in state machine
+#define SCAN_COMPRESSION_STATE_ERROR 6
+
+/// @}
+
+#endif  //  __P9_SCAN_COMPRESSION_H__
diff --git a/src/import/chips/p9/utils/p9_putRingUtils.C b/src/import/chips/p9/utils/p9_putRingUtils.C
new file mode 100644
index 00000000..2fe6ed0e
--- /dev/null
+++ b/src/import/chips/p9/utils/p9_putRingUtils.C
@@ -0,0 +1,1697 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/utils/p9_putRingUtils.C $                     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file p9_putRingUtils.C
+/// @brief Provide the service of decompressing the rs4 encoded string.
+///
+// *HWP HWP Owner: Bilicon Patil <bilpatil@in.ibm.com>
+// *HWP FW Owner: Prasad Ranganath <prasadbgr@in.ibm.com>
+// *HWP Team: PM
+// *HWP Level: 2
+// *HWP Consumed by: SBE:CME:SGPE:PGPE
+
+#include <p9_putRingUtils.H>
+#include <p9_scan_compression.H>
+
+using namespace RING_TYPES;
+namespace RS4
+{
+//
+// Function Definitions
+//
+
+///
+/// @brief Return a big-endian-indexed nibble from a byte string
+/// @param[in] i_rs4Str The RS4 scan string
+/// @param[in] i_nibbleIndx Index into i_rs4Str that need to converted
+///                         into a nibble
+/// @return big-endian-indexed nibble
+///
+uint8_t rs4_get_nibble(const uint8_t* i_rs4Str, const uint32_t i_nibbleIndx)
+{
+    uint8_t l_byte;
+    uint8_t l_nibble;
+
+    l_byte = i_rs4Str[i_nibbleIndx / 2];
+
+
+    if(i_nibbleIndx % 2)
+    {
+        l_nibble = (l_byte & 0x0f);
+    }
+    else
+    {
+        l_nibble = (l_byte >> 4);
+    }
+
+    return l_nibble;
+}
+
+///
+/// @brief Return verbatim data from the RS4 string
+/// @param[in] i_rs4Str The RS4 scan string
+/// @param[in] i_nibbleIndx Index into i_rs4Str that need to converted
+///                         into a nibble
+/// @param[in] i_nibbleCount The count of nibbles that need to be put
+///                          in the return value.
+/// @return big-endian-indexed double word
+///
+uint64_t rs4_get_verbatim(const uint8_t* i_rs4Str,
+                          const uint32_t i_nibbleIndx,
+                          const uint8_t i_nibbleCount)
+{
+    uint8_t l_byte;
+    uint8_t l_nibble;
+    uint64_t l_doubleWord = 0;
+
+    uint32_t l_index = i_nibbleIndx;
+
+    for(uint8_t i = 1; i <= i_nibbleCount; i++, l_index++)
+    {
+        l_byte = i_rs4Str[l_index / 2];
+
+        if(l_index % 2)
+        {
+            l_nibble = (l_byte & 0x0f);
+        }
+        else
+        {
+            l_nibble = (l_byte >> 4);
+        }
+
+        uint64_t l_tempDblWord = l_nibble;
+        l_tempDblWord <<= (64 - (4 * i));
+
+        l_doubleWord |= l_tempDblWord;
+    }
+
+    return l_doubleWord;
+}
+
+///
+/// @brief Decode an unsigned integer from a 4-bit octal stop code.
+/// @param[in] i_rs4Str The RS4 scan string
+/// @param[in] i_nibbleIndx Index into i_rs4Str that has the stop-code
+/// @param[out] o_numRotate No.of rotates decoded from the stop-code.
+/// @return The number of nibbles decoded.
+///
+uint64_t stop_decode(const uint8_t* i_rs4Str,
+                     uint32_t i_nibbleIndx,
+                     uint64_t& o_numRotate)
+{
+    uint64_t l_numNibblesParsed = 0; // No.of nibbles that make up the stop-code
+    uint64_t l_numNonZeroNibbles = 0;
+    uint8_t l_nibble;
+
+    do
+    {
+        l_nibble = rs4_get_nibble(i_rs4Str, i_nibbleIndx);
+
+        l_numNonZeroNibbles = (l_numNonZeroNibbles * 8) + (l_nibble & 0x07);
+
+        i_nibbleIndx++;
+        l_numNibblesParsed++;
+    }
+    while((l_nibble & 0x08) == 0);
+
+    o_numRotate = l_numNonZeroNibbles;
+
+    return l_numNibblesParsed;
+}
+
+/// @brief Byte-reverse a 64-bit integer
+/// @param[in] i_x 64-bit word that need to be byte reversed
+/// @return Byte reversed 64-bit word
+uint64_t rs4_revle64(const uint64_t i_x)
+{
+    uint64_t rx;
+
+#ifndef _BIG_ENDIAN
+    uint8_t* pix = (uint8_t*)(&i_x);
+    uint8_t* prx = (uint8_t*)(&rx);
+
+    prx[0] = pix[7];
+    prx[1] = pix[6];
+    prx[2] = pix[5];
+    prx[3] = pix[4];
+    prx[4] = pix[3];
+    prx[5] = pix[2];
+    prx[6] = pix[1];
+    prx[7] = pix[0];
+#else
+    rx = i_x;
+#endif
+
+    return rx;
+}
+}; //end of namespace
+
+void getRingProperties(const RingID i_ringId,
+                       uint32_t& o_torOffset,
+                       RINGTYPE& o_ringType,
+                       CHIPLET_TYPE& o_chipletType)
+{
+    do
+    {
+        // Determine the TOR ID
+        o_torOffset =
+            (INSTANCE_RING_MASK & (RING_PROPERTIES[i_ringId].iv_torOffSet));
+        o_chipletType = RING_PROPERTIES[i_ringId].iv_type;
+
+        if(INVALID_RING == o_torOffset)
+        {
+            break;
+        }
+
+        // Determine Ring Type
+        if(INSTANCE_RING_MARK & (RING_PROPERTIES[i_ringId].iv_torOffSet))
+        {
+            o_ringType = INSTANCE_RING;
+        }
+        else
+        {
+            o_ringType = COMMON_RING;
+        }
+    }
+    while(0);
+}
+/// @brief Function to apply the Ring data using the standard-scan method
+/// @param[in] i_target Chiplet Target of Scan
+//  @param[in] i_chipletId data from RS4
+/// @param[in] i_operation Type of operation to perform - ROTATE/SCAN
+/// @param[in] i_opVal Number of bits for the operation
+/// @param[in] i_scanData This value has to be scanned when i_operation is SCAN
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode standardScan(
+    const fapi2::Target<fapi2::TARGET_TYPE_ALL>& i_target,
+    const uint8_t i_chipletId,
+    opType_t i_operation,
+    uint64_t i_opVal,
+    uint64_t i_scanData)
+{
+    FAPI_INF(">> standardScan");
+
+    fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS;
+    // @TODO: getChipletNumber is only supported on SBE plat.
+    //        Need to have it supported in the eKB code.
+    uint32_t l_chiplet = i_chipletId << 24;
+#ifdef __PPE__
+    uint32_t l_chipletID = i_target.getChipletNumber();
+
+    if ( l_chipletID )
+    {
+        l_chiplet = (l_chipletID << 24);
+    }
+
+#endif
+
+#ifndef __PPE__
+
+    // Non-PPE platform - Cronus need a Chip target to be used
+    // in putScom/getScom.
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_parent;
+
+    if (i_target.getType() == fapi2::TARGET_TYPE_CORE)
+    {
+        l_parent = i_target.template getParent<fapi2::TARGET_TYPE_PROC_CHIP> ();
+    }
+
+#endif
+
+    do
+    {
+        // **************
+        // Scan or Rotate
+        // **************
+        if(ROTATE == i_operation)
+        {
+            // Setup Scom Address for rotate operation
+            uint32_t l_scomAddress = 0x00039000;
+
+            // Add the chiplet ID in the Scom Address
+            l_scomAddress |= l_chiplet;
+
+            const uint64_t l_maxRotates = 0x100000;
+            uint64_t l_rotateCount = i_opVal;
+            uint32_t l_numRotateScoms = 1; // 1 - We need to do atleast one scom
+
+            if(i_opVal > l_maxRotates)
+            {
+                l_numRotateScoms = (i_opVal / l_maxRotates);
+                l_rotateCount = l_maxRotates;
+            }
+
+
+            // Scom Data needs to have the no.of rotates in the bits 12-31
+            l_rotateCount <<= 32;
+
+            for(uint32_t i = 0; i < (l_numRotateScoms + 1); i++)
+            {
+                if(i == l_numRotateScoms)
+                {
+                    if(i_opVal <= l_maxRotates)
+                    {
+                        break;
+                    }
+
+                    l_rotateCount = (i_opVal % l_maxRotates);
+                    l_rotateCount <<= 32;
+                }
+
+                FAPI_INF("l_rotateCount %u", l_rotateCount);
+                fapi2::buffer<uint64_t> l_scomData(l_rotateCount);
+
+#ifndef __PPE__
+                l_rc = fapi2::putScom(l_parent, l_scomAddress, l_scomData);
+#else
+                l_rc = fapi2::putScom(i_target, l_scomAddress, l_scomData);
+#endif
+
+                if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+                {
+                    FAPI_ERR("ROTATE for %d, failed", i_opVal);
+                    break;
+                }
+
+                // Check OPCG_DONE status
+                l_scomAddress = 0x00000100;
+
+                // Add the chiplet ID in the Scom Address
+                l_scomAddress |= l_chiplet;
+
+                // @TODO: Value 300 is a random number to start with.
+                uint32_t l_attempts = 300;
+
+                while(l_attempts > 0)
+                {
+                    l_attempts--;
+
+                    fapi2::buffer<uint64_t> l_opcgStatus;
+#ifndef __PPE__
+                    l_rc = fapi2::getScom(l_parent, l_scomAddress, l_opcgStatus);
+#else
+                    l_rc = fapi2::getScom(i_target, l_scomAddress, l_opcgStatus);
+#endif
+
+                    if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+                    {
+                        FAPI_ERR("Failure during OPCG Check");
+                        break;
+                    }
+
+                    if(l_opcgStatus.getBit<8>())
+                    {
+                        FAPI_INF("OPCG_DONE set");
+                        break;
+                    }
+
+                    // @TODO: 1 micro second is a number that works now.
+                    //        Need to derive the real delay number.
+                    fapi2::delay(1000, 1000000);
+
+                }
+
+                if(l_attempts == 0 )
+                {
+                    l_rc = fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA;
+                    FAPI_ERR("Max attempts exceeded checking OPCG_DONE");
+                    break;
+                }
+            }// end of for loop
+        }
+        else if(SCAN == i_operation)
+        {
+            // Setting Scom Address for a 64-bit scan
+            uint32_t l_scomAddress = 0x0003E000;
+
+            // Add the chiplet ID in the Scom Address
+            l_scomAddress |= l_chiplet;
+
+            uint32_t l_scanCount = i_opVal;
+
+            fapi2::buffer<uint64_t> l_scomData(i_scanData);
+
+            // Set the scan count to the actual value
+            l_scomAddress |= l_scanCount;
+
+#ifndef __PPE__
+            l_rc = fapi2::putScom(l_parent, l_scomAddress, l_scomData);
+#else
+            l_rc = fapi2::putScom(i_target, l_scomAddress, l_scomData);
+#endif
+
+            if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+            {
+                FAPI_ERR("SCAN for %d, failed", i_opVal);
+                break;
+            }
+        } // end of if(SCAN == i_operation)
+    }
+    while(0);
+
+    FAPI_INF("<< standardScan");
+    return l_rc;
+}
+
+/// @brief Function to set the Scan Region
+/// @param[in] i_target Chiplet Target of Scan
+/// @param[in] i_scanRegion Value to be set to select a Scan Region
+//  @param[in] i_chipletId data from RS4
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode setupScanRegion(const fapi2::Target<fapi2::TARGET_TYPE_ALL>&
+                                  i_target,
+                                  uint64_t i_scanRegion,
+                                  const uint8_t i_chipletId)
+{
+    fapi2::ReturnCode l_rc;
+    uint32_t l_chiplet =  i_chipletId << 24;
+    uint64_t l_scan_region = i_scanRegion;
+#ifdef __PPE__
+    uint32_t l_chipletID = i_target.getChipletNumber();
+
+    if ( l_chipletID )
+    {
+        l_chiplet = (l_chipletID << 24);
+    }
+
+    if (fapi2::TARGET_TYPE_EX & (i_target.get().getFapiTargetType()))
+    {
+        // this gives position of ex (0 or 1)
+        uint32_t l_ex_number = i_target.getTargetNumber();
+
+        // We are in odd EX and it's placed in bottom half of the EQ
+        if (l_ex_number % 2)
+        {
+            uint32_t l_type = (uint32_t)i_scanRegion;
+            // need to shift one bit.
+            uint32_t l_ex_region = i_scanRegion >> 32;
+            l_ex_region = l_ex_region >> 1;
+
+            l_scan_region = l_ex_region;
+            l_scan_region = l_scan_region << 32;
+            l_scan_region = l_scan_region | l_type;
+
+        }
+
+        // for even ex, the data from RS4 hold good.
+    }
+
+#endif
+
+
+
+#ifndef __PPE__
+    // Non-PPE platform - Cronus need a Chip target to be used
+    // in putScom/getScom.
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_parent(
+        i_target.template getParent<fapi2::TARGET_TYPE_PROC_CHIP>());
+#endif
+
+    do
+    {
+        // **************************
+        // Setup Scan-Type and Region
+        // **************************
+        uint32_t l_scomAddress = 0x00030005;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+        // Do the scom
+        fapi2::buffer<uint64_t> l_scanRegion(l_scan_region);
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, l_scanRegion);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, l_scanRegion);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("Setup Scan-Type and Region failed");
+            break;
+        }
+    }
+    while(0);
+
+    return l_rc;
+}
+
+/// @brief Function to write the header data to the ring.
+/// @param[in] i_target Chiplet Target of Scan
+/// @param[in] i_header The header data that is to be written.
+//  @param[in] i_chipletId data from RS4
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode writeHeader(const fapi2::Target<fapi2::TARGET_TYPE_ALL>&
+                              i_target,
+                              const uint64_t i_header,
+                              const uint8_t i_chipletId)
+{
+    fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS;
+
+    do
+    {
+        // @TODO: getChipletNumber is only supported on SBE plat.
+        //        Need to have it supported in the eKB code.
+        uint32_t l_chiplet = i_chipletId << 24;
+#ifdef __PPE__
+        uint32_t l_chipletID = i_target.getChipletNumber();
+
+        if ( l_chipletID )
+        {
+            l_chiplet = (l_chipletID << 24);
+        }
+
+#endif
+
+        uint32_t l_scomAddress = 0x0003E040; // 64-bit scan
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+// I think we won't require this
+#ifndef __PPE__
+        l_rc = fapi2::putScom(
+                   i_target.template getParent<fapi2::TARGET_TYPE_PROC_CHIP>(),
+                   l_scomAddress,
+                   i_header);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, i_header);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("Error during writing header %016x", i_header);
+            break;
+        }
+    }
+    while(0);
+
+    return l_rc;
+
+}
+
+/// @brief Function to reader the header data from the ring and verify it.
+/// @param[in] i_target Chiplet Target of Scan
+/// @param[in] i_header The header data that is expected.
+//  @param[in] i_chipletId data from RS4
+//  @param[in] i_ringMode different ring mode operations
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode verifyHeader(const fapi2::Target<fapi2::TARGET_TYPE_ALL>&
+                               i_target,
+                               const uint64_t i_header,
+                               const uint8_t i_chipletId,
+                               const fapi2::RingMode i_ringMode)
+{
+    fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS;
+
+    do
+    {
+        // @TODO: getChipletNumber is only supported on SBE plat.
+        //        Need to have it supported in the eKB code.
+        uint32_t l_chiplet = i_chipletId << 24;
+#ifdef __PPE__
+        uint32_t l_chipletID = i_target.getChipletNumber();
+
+        if ( l_chipletID )
+        {
+            l_chiplet = (l_chipletID << 24);
+        }
+
+#endif
+
+        uint32_t l_scomAddress = 0x0003E000; // 64-bit scan
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+        fapi2::buffer<uint64_t> l_readHeader;
+
+#ifndef __PPE__
+        l_rc = fapi2::getScom(
+                   i_target.template getParent<fapi2::TARGET_TYPE_PROC_CHIP>(),
+                   l_scomAddress,
+                   l_readHeader);
+#else
+        l_rc = fapi2::getScom(i_target, l_scomAddress, l_readHeader);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("Error during reading header %016x", i_header);
+            break;
+        }
+
+        FAPI_INF("Got header - %016x", uint64_t(l_readHeader));
+
+        if(l_readHeader != i_header)
+        {
+            FAPI_ERR("Read header(%016x) data incorrect", uint64_t(l_readHeader));
+            l_rc = fapi2::FAPI2_RC_PLAT_ERR_RING_HEADER_CHECK;
+            break;
+        }
+
+        if ((i_ringMode &  fapi2::RING_MODE_SET_PULSE_NSL))
+        {
+            const uint64_t l_header = 0xa5a5a5a500000000;
+            uint32_t l_address = 0x0003A000; // 64-bit scan
+            // Add the chiplet ID in the Scom Address
+            l_address |= l_chiplet;
+
+#ifndef __PPE__
+            l_rc = fapi2::putScom(
+                       i_target.template getParent<fapi2::TARGET_TYPE_PROC_CHIP>(),
+                       l_address,
+                       l_header);
+#else
+            l_rc = fapi2::putScom(i_target, l_address, l_header);
+#endif
+
+            if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+            {
+                FAPI_ERR("Error during writing header %016x", l_header);
+                break;
+            }
+
+        }
+    }
+    while(0);
+
+    return l_rc;
+
+}
+
+/// @brief Function to set the Scan Region for set pulse mode
+/// @param[in] i_target Chiplet Target of Scan
+/// @param[in] i_scanRegion Value to be set to select a Scan Region
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode setupScanRegionForSetPulse(
+    const fapi2::Target<fapi2::TARGET_TYPE_ALL>& i_target,
+    uint64_t i_scanRegion,
+    const fapi2::RingMode i_ringMode,
+    const uint8_t i_chipletId)
+{
+    fapi2::ReturnCode l_rc;
+
+    uint32_t l_chiplet = (i_chipletId << 24);
+#ifdef __PPE__
+    uint32_t l_chipletID = i_target.getChipletNumber();
+
+    if ( l_chipletID )
+    {
+        l_chiplet = (l_chipletID << 24);
+    }
+
+#endif
+
+#ifndef __PPE__
+    // Non-PPE platform - Cronus need a Chip target to be used
+    // in putScom/getScom.
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_parent(
+        i_target.template getParent<fapi2::TARGET_TYPE_PROC_CHIP>());
+#endif
+
+    do
+    {
+        // **************************
+        // Setup OPCG_ALIGN – SNOP Align=5 and SNOP Wait=7
+        // **************************
+        uint32_t l_scomAddress = 0x00030001;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+        fapi2::buffer<uint64_t> l_opcgAlign;
+
+#ifndef __PPE__
+        l_rc = fapi2::getScom(l_parent, l_scomAddress, l_opcgAlign);
+#else
+        l_rc = fapi2::getScom(i_target, l_scomAddress, l_opcgAlign);
+#endif
+        //set SNOP Align=8:1 and SNOP Wait=7
+        // bits: 4:7   SNOP_ALIGN(0:3) 5: 8:1
+        // bits: 20:31 SNOP_WAIT(0:11)
+        l_opcgAlign.setBit<5>();
+        l_opcgAlign.setBit<7>();
+
+        l_opcgAlign.setBit<29>();
+        l_opcgAlign.setBit<30>();
+        l_opcgAlign.setBit<31>();
+
+        // Do the scom
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, l_opcgAlign);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, l_opcgAlign);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("Setup OPCG Algin failed");
+            break;
+        }
+
+        // **************************
+        // Setup Scan-Type and Region
+        // **************************
+        l_scomAddress = 0x00030005;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+        // Do the scom
+        fapi2::buffer<uint64_t> l_scanRegion(i_scanRegion);
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, l_scanRegion);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, l_scanRegion);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("Setup Scan-Type and Region failed");
+            break;
+        }
+
+        ////////////////////////////
+        //prepare clk_region register
+        ////////////////////////////
+        l_scomAddress = 0x00030006;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+        //First 32 bits tells clock region
+        uint64_t l_clk_region = i_scanRegion & 0xFFFFFFFF00000000;
+
+        fapi2::buffer<uint64_t> l_clkRegion(l_clk_region);
+
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, l_clkRegion);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, l_clkRegion);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("Setup NSL mode failed");
+            break;
+        }
+
+        //////////////////////
+        //prepare opcg_reg0
+        //////////////////////
+        l_scomAddress = 0x00030002;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+        //bit 11 -- RUN_OPCG_ON_UPDATE_DR
+        uint64_t l_opcg_reg0 = 0x0010000000000000;
+
+        fapi2::buffer<uint64_t> l_opcgReg0(l_opcg_reg0);
+
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, l_opcgReg0);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, l_opcgReg0);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("Setup NSL mode failed");
+            break;
+        }
+
+        uint64_t l_opcg_reg1 = 0x0;
+        uint64_t l_opcg_reg2 = 0x0;
+        // NSL for slow regions
+        uint64_t l_opcg_capt1 = 0x0;
+        // NSL for fast regions
+        uint64_t l_opcg_capt2 = 0x0;
+        uint64_t l_opcg_capt3 = 0x0;
+
+        // setup NSL mode
+        if (i_ringMode &  fapi2::RING_MODE_SET_PULSE_NSL)
+        {
+            l_opcg_reg1 = 0x0;
+            l_opcg_reg2 = 0x0;
+            // NSL for slow regions
+            l_opcg_capt1 = 0x1400000000000000;
+            // NSL for fast regions
+            l_opcg_capt2 = 0x0400000000000000;
+            l_opcg_capt3 = 0x0;
+
+        }
+        else if ((i_ringMode &  fapi2::RING_MODE_SET_PULSE_SL))
+        {
+            l_opcg_reg1 = 0x0;
+            l_opcg_reg2 = 0x0;
+            // NSL for slow regions
+            l_opcg_capt1 = 0x1800000000000000;
+            // NSL for fast regions
+            l_opcg_capt2 = 0x0800000000000000;
+            l_opcg_capt3 = 0x0;
+        }
+        else   //set pulse all
+        {
+            l_opcg_reg1 = 0x0;
+            l_opcg_reg2 = 0x0;
+            // NSL for slow regions
+            l_opcg_capt1 = 0x1E00000000000000;
+            // NSL for fast regions
+            l_opcg_capt2 = 0x0E00000000000000;
+            l_opcg_capt3 = 0x0;
+
+        }
+
+        //prepare opcg_reg1
+        l_scomAddress = 0x00030003;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+        fapi2::buffer<uint64_t> l_opcgReg1(l_opcg_reg1);
+
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, l_opcgReg1);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, l_opcgReg1);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("Setup opcg reg1 failed");
+            break;
+        }
+
+        //prepare opcg_reg2
+        l_scomAddress = 0x00030004;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+
+        fapi2::buffer<uint64_t> l_opcgReg2(l_opcg_reg2);
+
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, l_opcgReg2);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, l_opcgReg2);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("Setup opcg reg2 failed");
+            break;
+        }
+
+        //prepare opcg_capt1
+        l_scomAddress = 0x00030010;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+
+        fapi2::buffer<uint64_t> l_opcgCapt1(l_opcg_capt1);
+
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, l_opcgCapt1);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, l_opcgCapt1);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("Setup opcg capture 1 failed");
+            break;
+        }
+
+        //prepare opcg_capt2
+        l_scomAddress = 0x00030011;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+
+        fapi2::buffer<uint64_t> l_opcgCapt2(l_opcg_capt2);
+
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, l_opcgCapt2);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, l_opcgCapt2);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("Setup opcg capture 2 failed");
+            break;
+        }
+
+        //prepare opcg_capt3
+        l_scomAddress = 0x00030012;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+
+        fapi2::buffer<uint64_t> l_opcgCapt3(l_opcg_capt3);
+
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, l_opcgCapt3);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, l_opcgCapt3);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("Setup opcg capture 3 failed");
+            break;
+        }
+
+    }
+    while(0);
+
+    return l_rc;
+}
+/// @brief Function to restore the opcg registers
+/// @param[in] i_target Chiplet Target of Scan
+/// @param[out]o_OPCGData Structure that contains opcg data
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode storeOPCGRegData(
+    const fapi2::Target<fapi2::TARGET_TYPE_ALL>& i_target,
+    struct restoreOpcgRegisters& o_OPCGData,
+    const uint8_t i_chipletId)
+{
+    fapi2::ReturnCode l_rc;
+    uint32_t l_chiplet = i_chipletId << 24;
+#ifdef __PPE__
+    uint32_t l_chipletID = i_target.getChipletNumber();
+
+    if ( l_chipletID )
+    {
+        l_chiplet = (l_chipletID << 24);
+    }
+
+#endif
+
+#ifndef __PPE__
+    // Non-PPE platform - Cronus need a Chip target to be used
+    // in putScom/getScom.
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_parent(
+        i_target.template getParent<fapi2::TARGET_TYPE_PROC_CHIP>());
+#endif
+
+    do
+    {
+        //////////////////////
+        //prepare opcg_reg0
+        //////////////////////
+        uint32_t l_scomAddress = 0x00030002;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+
+#ifndef __PPE__
+        l_rc = fapi2::getScom(l_parent, l_scomAddress, o_OPCGData.l_opcgReg0);
+#else
+        l_rc = fapi2::getScom(i_target, l_scomAddress, o_OPCGData.l_opcgReg0);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("OPCG_REG0 read op failed");
+            break;
+        }
+
+        //prepare opcg_reg1
+        l_scomAddress = 0x00030003;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+#ifndef __PPE__
+        l_rc = fapi2::getScom(l_parent, l_scomAddress, o_OPCGData.l_opcgReg1);
+#else
+        l_rc = fapi2::getScom(i_target, l_scomAddress, o_OPCGData.l_opcgReg1);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("OPCG_REG1 read op failed");
+            break;
+        }
+
+        //prepare opcg_reg2
+        l_scomAddress = 0x00030004;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+#ifndef __PPE__
+        l_rc = fapi2::getScom(l_parent, l_scomAddress, o_OPCGData.l_opcgReg2);
+#else
+        l_rc = fapi2::getScom(i_target, l_scomAddress, o_OPCGData.l_opcgReg2);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("OPCG_REG2 read op failed");
+            break;
+        }
+
+        //prepare opcg_capt1
+        l_scomAddress = 0x00030010;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+
+#ifndef __PPE__
+        l_rc = fapi2::getScom(l_parent, l_scomAddress, o_OPCGData.l_opcgCapt1);
+#else
+        l_rc = fapi2::getScom(i_target, l_scomAddress, o_OPCGData.l_opcgCapt1);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("OPCG_CAPT1 read op failed");
+            break;
+        }
+
+        //prepare opcg_capt2
+        l_scomAddress = 0x00030011;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+#ifndef __PPE__
+        l_rc = fapi2::getScom(l_parent, l_scomAddress, o_OPCGData.l_opcgCapt2);
+#else
+        l_rc = fapi2::getScom(i_target, l_scomAddress, o_OPCGData.l_opcgCapt2);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("OPCG_CAPT2 read op failed");
+            break;
+        }
+
+        //prepare opcg_capt3
+        l_scomAddress = 0x00030012;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+#ifndef __PPE__
+        l_rc = fapi2::getScom(l_parent, l_scomAddress, o_OPCGData.l_opcgCapt3);
+#else
+        l_rc = fapi2::getScom(i_target, l_scomAddress, o_OPCGData.l_opcgCapt3);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("OPCG_CAPT3 read op failed");
+            break;
+        }
+    }
+    while(0);
+
+    return l_rc;
+}
+/// @brief Function to restore the opcg registers
+/// @param[in] i_target Chiplet Target of Scan
+/// @param[in] i_OPCGData opcg register data to restore original values
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode restoreOPCGRegData(
+    const fapi2::Target<fapi2::TARGET_TYPE_ALL>& i_target,
+    struct restoreOpcgRegisters i_OPCGData,
+    const uint8_t i_chipletId)
+{
+    fapi2::ReturnCode l_rc;
+    uint32_t l_chiplet = i_chipletId << 24;
+#ifdef __PPE__
+    uint32_t l_chipletID = i_target.getChipletNumber();
+
+    if ( l_chipletID )
+    {
+        l_chiplet = (l_chipletID << 24);
+    }
+
+#endif
+
+#ifndef __PPE__
+    // Non-PPE platform - Cronus need a Chip target to be used
+    // in putScom/getScom.
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_parent(
+        i_target.template getParent<fapi2::TARGET_TYPE_PROC_CHIP>());
+#endif
+
+    do
+    {
+        //////////////////////
+        //clear clk region
+        //////////////////////
+        uint32_t l_scomAddress = 0x00030006;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+        fapi2::buffer<uint64_t> l_clkReg(0);
+
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, l_clkReg);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, l_clkReg);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("OPCG_REG0 write op failed");
+            break;
+        }
+
+        //////////////////////
+        //prepare opcg_reg0
+        //////////////////////
+        l_scomAddress = 0x00030002;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, i_OPCGData.l_opcgReg0);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, i_OPCGData.l_opcgReg0);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("OPCG_REG0 write op failed");
+            break;
+        }
+
+        //prepare opcg_reg1
+        l_scomAddress = 0x00030003;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, i_OPCGData.l_opcgReg1);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, i_OPCGData.l_opcgReg1);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("OPCG_REG1 write op failed");
+            break;
+        }
+
+        //prepare opcg_reg2
+        l_scomAddress = 0x00030004;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, i_OPCGData.l_opcgReg2);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, i_OPCGData.l_opcgReg2);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("OPCG_REG2 write op failed");
+            break;
+        }
+
+        //prepare opcg_capt1
+        l_scomAddress = 0x00030010;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, i_OPCGData.l_opcgCapt1);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, i_OPCGData.l_opcgCapt1);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("OPCG_CAPT1 write op failed");
+            break;
+        }
+
+        //prepare opcg_capt2
+        l_scomAddress = 0x00030011;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, i_OPCGData.l_opcgCapt2);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, i_OPCGData.l_opcgCapt2);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("OPCG_CAPT2 write op failed");
+            break;
+        }
+
+        //prepare opcg_capt3
+        l_scomAddress = 0x00030012;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, i_OPCGData.l_opcgCapt3);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, i_OPCGData.l_opcgCapt3);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("OPCG_CAPT3 write op failed");
+            break;
+        }
+    }
+    while(0);
+
+    return l_rc;
+}
+
+/// @brief Function to decompress the RS4 and apply the Ring data
+/// @param[in] i_target Chiplet Target of Scan
+/// @param[in] i_rs4 The RS4 compressed string
+/// @param[in] i_applyOverride: state of override mode
+/// @param[in] i_ringMode: different ring modes
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode rs4DecompressionSvc(
+    const fapi2::Target<fapi2::TARGET_TYPE_ALL>& i_target,
+    const uint8_t* i_rs4,
+    const bool i_applyOverride,
+    const fapi2::RingMode i_ringMode)
+{
+    FAPI_INF(">> rs4DecompressionSvc");
+    CompressedScanData* l_rs4Header = (CompressedScanData*) i_rs4;
+    const uint8_t* l_rs4Str = (i_rs4 + sizeof(CompressedScanData));
+
+    opType_t l_opType = ROTATE;
+    uint64_t l_nibbleIndx = 0;
+    uint64_t l_bitsDecoded = 0;
+    bool l_decompressionDone = false;
+    uint64_t l_scanRegion = rs4_revle64(l_rs4Header->iv_scanSelect);
+    uint8_t l_chipletId = l_rs4Header->iv_chipletId;
+    fapi2::ReturnCode l_rc;
+    struct restoreOpcgRegisters l_opcgData;
+    uint8_t l_mask = 0x08;
+    uint64_t l_scomData = 0x0;
+
+    do
+    {
+        if (l_rs4Header->iv_length == 0)
+        {
+            FAPI_ERR("Invalid ring length in RS4 image");
+            break;
+        }
+
+        if ((i_ringMode &  fapi2::RING_MODE_SET_PULSE_NSL) ||
+            (i_ringMode &  fapi2::RING_MODE_SET_PULSE_SL) ||
+            (i_ringMode &  fapi2::RING_MODE_SET_PULSE_ALL))
+        {
+            l_rc =  storeOPCGRegData (i_target, l_opcgData, l_chipletId);
+
+            if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+            {
+                break;
+            }
+
+            l_rc = setupScanRegionForSetPulse(i_target, l_scanRegion, i_ringMode
+                                              , l_chipletId);
+
+            if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+            {
+                break;
+            }
+        }
+        else
+        {
+            // Set up the scan region for the ring.
+            l_rc = setupScanRegion(i_target, l_scanRegion, l_chipletId);
+
+            if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+            {
+                break;
+            }
+        }
+
+        // Write a 64 bit value for header.
+        const uint64_t l_header = 0xa5a5a5a5a5a5a5a5;
+        l_rc = writeHeader(i_target, l_header, l_chipletId);
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            break;
+        }
+
+        //if the ring length is not 8bit aligned, then we need to skip the
+        //padding bits
+        uint8_t l_padding_bits = 0;
+
+        if (l_rs4Header->iv_length % 4)
+        {
+            l_padding_bits = (4 - (l_rs4Header->iv_length % 4));
+        }
+
+        bool l_skip_64bits = true;
+
+        // Decompress the RS4 string and scan
+        do
+        {
+            if (l_opType == ROTATE)
+            {
+                // Determine the no.of ROTATE operations encoded in stop-code
+                uint64_t l_count = 0;
+                l_nibbleIndx += stop_decode(l_rs4Str, l_nibbleIndx, l_count);
+
+                // Determine the no.of rotates in bits
+                uint64_t l_bitRotates = (4 * l_count);
+
+                //Need to skip 64bits , because we have already written header
+                //data.
+                if (l_skip_64bits)
+                {
+                    l_bitRotates -= SIXTYFOUR_BIT_HEADER;
+                    l_skip_64bits = false;
+                }
+
+                l_bitsDecoded += l_bitRotates;
+
+                if(l_bitsDecoded > l_rs4Header->iv_length)
+                {
+                    FAPI_ERR("Rotate decompression done."
+                             "l_bitsDecoded = %d, length = %d",
+                             l_bitsDecoded, l_rs4Header->iv_length);
+                    l_decompressionDone = true;
+                    l_rc = fapi2::FAPI2_RC_PLAT_RING_DECODE_LENGTH_EXCEEDED;
+                    break;
+                }
+
+                // Do the ROTATE operation
+                if (l_bitRotates != 0)
+                {
+                    l_rc = standardScan(i_target,
+                                        l_chipletId,
+                                        ROTATE,
+                                        l_bitRotates);
+
+                    if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+                    {
+                        break;
+                    }
+                }
+
+                l_opType = SCAN;
+            }
+            else if(l_opType == SCAN)
+            {
+                uint8_t l_scanCount = rs4_get_nibble(l_rs4Str, l_nibbleIndx);
+                l_nibbleIndx++;
+
+                if (l_scanCount == 0)
+                {
+                    FAPI_INF("SCAN COUNT %u", l_scanCount);
+                    break;
+                }
+
+                if (!i_applyOverride)
+                {
+                    l_bitsDecoded += (4 * l_scanCount);
+
+                    if(l_bitsDecoded > l_rs4Header->iv_length)
+                    {
+                        FAPI_ERR("Scan decompression done."
+                                 "l_bitsDecoded = %d, length = %d",
+                                 l_bitsDecoded, l_rs4Header->iv_length);
+                        l_decompressionDone = true;
+                        l_rc = fapi2::FAPI2_RC_PLAT_RING_DECODE_LENGTH_EXCEEDED;
+                        break;
+                    }
+
+                    // Parse the non-zero nibbles of the RS4 string and
+                    // scan them into the ring
+                    l_scomData = rs4_get_verbatim(l_rs4Str,
+                                                  l_nibbleIndx,
+                                                  l_scanCount);
+                    l_nibbleIndx += l_scanCount;
+
+                    l_rc = standardScan(i_target,
+                                        l_chipletId,
+                                        SCAN,
+                                        (l_scanCount * 4),
+                                        l_scomData);
+
+                    if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+                    {
+                        break;
+                    }
+                }
+                else
+                {
+                    if(0xF == l_scanCount) // We are parsing RS4 for override rings
+                    {
+                        uint8_t l_careMask =
+                            rs4_get_nibble(l_rs4Str, l_nibbleIndx);
+                        l_nibbleIndx++;
+                        uint8_t l_spyData =
+                            rs4_get_nibble(l_rs4Str, l_nibbleIndx);
+                        l_nibbleIndx++;
+
+                        for(uint8_t i = 0; i < 4; i++)
+                        {
+                            l_bitsDecoded += 1;
+                            l_scomData = 0x0;
+
+                            if((l_careMask & (l_mask >> i)))
+                            {
+                                if((l_spyData & (l_mask >> i)))
+                                {
+                                    l_scomData = 0xFFFFFFFFFFFFFFFF;
+                                }
+
+                                l_opType = SCAN;
+                            }
+                            else
+                            {
+                                l_opType = ROTATE;
+                            }
+
+                            l_rc = standardScan(i_target,
+                                                l_chipletId,
+                                                l_opType,
+                                                1, // Insert 1 bit
+                                                l_scomData);
+
+                            if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+                            {
+                                break;
+                            }
+                        } // end of looper for bit-parsing a non-zero nibble
+                    }
+                    else // We are parsing RS4 for base rings
+                    {
+                        for (uint8_t x = 0; x < l_scanCount; x++)
+                        {
+                            // Parse the non-zero nibbles of the RS4 string and
+                            // scan them into the ring
+                            uint8_t l_data =
+                                rs4_get_nibble(l_rs4Str, l_nibbleIndx);
+                            l_nibbleIndx += 1;
+
+                            FAPI_INF ("VERBATIm l_nibbleIndx %u l_scanCount %u "
+                                      "l_bitsDecoded %u", l_nibbleIndx, l_scanCount, l_bitsDecoded);
+
+                            for(uint8_t i = 0; i < 4; i++)
+                            {
+                                l_scomData = 0x0;
+
+                                if((l_data & (l_mask >> i)))
+                                {
+                                    l_opType = SCAN;
+                                    l_scomData = 0xFFFFFFFFFFFFFFFF;
+                                }
+                                else
+                                {
+                                    l_opType = ROTATE;
+                                }
+
+                                l_rc = standardScan(i_target,
+                                                    l_chipletId,
+                                                    l_opType,
+                                                    1, // Insert 1 bit
+                                                    l_scomData);
+
+                                if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+                                {
+                                    break;
+                                }
+                            }
+
+                            if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+                            {
+                                break;
+                            }
+                        } // end of looper for bit-parsing a non-zero nibble
+                    }
+                }
+
+                l_opType = ROTATE;
+            } // end of - if(l_opType == SCAN)
+
+            if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+            {
+                break;
+            }
+        }
+        while(1);
+
+        if((l_rc != fapi2::FAPI2_RC_SUCCESS) || (true == l_decompressionDone))
+        {
+            break;
+        }
+
+        // Handle the string termination
+        uint8_t l_nibble = rs4_get_nibble(l_rs4Str, l_nibbleIndx);
+        l_nibbleIndx++;
+
+        if (l_nibble != 0)
+        {
+            // Parse the non-zero nibbles of the RS4 string and
+            // scan them into the ring
+            if((l_bitsDecoded + l_nibble) > l_rs4Header->iv_length)
+            {
+                FAPI_ERR("Decompression Done."
+                         "l_bitsDecoded = %d, l_nibble= %d, length = %d",
+                         l_bitsDecoded, l_nibble, l_rs4Header->iv_length);
+                l_rc = fapi2::FAPI2_RC_PLAT_RING_DECODE_LENGTH_EXCEEDED;
+                break;
+            }
+            else
+            {
+                if (!i_applyOverride)
+                {
+                    l_bitsDecoded += l_nibble;
+                    l_scomData = rs4_get_verbatim(l_rs4Str,
+                                                  l_nibbleIndx,
+                                                  1); // return 1 nibble
+
+                    l_rc = standardScan(i_target,
+                                        l_chipletId,
+                                        SCAN,
+                                        (4 - l_padding_bits) , // scan 4 bits
+                                        l_scomData);
+                }
+                else
+                {
+                    if(0x8 & l_nibble) // We are parsing RS4 for override rings
+                    {
+                        uint8_t l_careMask = rs4_get_nibble(l_rs4Str, l_nibbleIndx);
+                        l_nibbleIndx++;
+                        uint8_t l_spyData = rs4_get_nibble(l_rs4Str, l_nibbleIndx);
+                        l_nibbleIndx++;
+
+                        for(uint8_t i = 0; i < 4; i++)
+                        {
+                            l_bitsDecoded += 1;
+                            l_scomData = 0x0;
+
+                            if((l_careMask & (l_mask >> i)))
+                            {
+                                if((l_spyData & (l_mask >> i)))
+                                {
+                                    l_scomData = 0xFFFFFFFFFFFFFFFF;
+                                }
+
+                                l_opType = SCAN;
+                            }
+                            else
+                            {
+                                l_opType = ROTATE;
+                            }
+
+                            l_rc = standardScan(i_target,
+                                                l_chipletId,
+                                                l_opType,
+                                                1, // Insert 1 bit
+                                                l_scomData);
+
+                            if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+                            {
+                                break;
+                            }
+                        } // end of looper for bit-parsing a non-zero nibble
+                    }
+                    else // We are parsing RS4 for base rings
+                    {
+                        // scan them into the ring
+                        uint8_t l_data = rs4_get_nibble(l_rs4Str, l_nibbleIndx);
+
+                        l_nibbleIndx += 1;
+
+                        for(uint8_t i = 0; i < l_nibble; i++)
+                        {
+                            l_scomData = 0x0;
+                            l_bitsDecoded += 1;
+
+                            if((l_data & (l_mask >> i)))
+                            {
+                                l_opType = SCAN;
+                                l_scomData = 0xFFFFFFFFFFFFFFFF;
+
+                            }
+                            else
+                            {
+                                l_opType = ROTATE;
+
+                            }
+
+                            l_rc = standardScan(i_target,
+                                                l_chipletId,
+                                                l_opType,
+                                                1, // Insert 1 bit
+                                                l_scomData);
+
+                            if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+                            {
+                                break;
+                            }
+                        } //end of for
+                    }
+                }
+            }
+        } // end of if(l_nibble != 0)
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            break;
+        }
+
+        // Verify header
+        l_rc = verifyHeader(i_target, l_header, l_chipletId, i_ringMode);
+
+        if(l_rc)
+        {
+            break;
+        }
+
+        // Clean scan region and type data
+        l_rc = cleanScanRegionandTypeData(i_target, l_chipletId);
+
+        if(l_rc)
+        {
+            break;
+        }
+
+        if ((i_ringMode &  fapi2::RING_MODE_SET_PULSE_NSL) ||
+            (i_ringMode &  fapi2::RING_MODE_SET_PULSE_SL) ||
+            (i_ringMode &  fapi2::RING_MODE_SET_PULSE_ALL))
+        {
+            l_rc = restoreOPCGRegData (i_target, l_opcgData, l_chipletId);
+
+            if (l_rc)
+            {
+                break;
+            }
+        }
+
+    }
+    while(0);
+
+    FAPI_INF("<< rs4DecompressionSvc");
+    return l_rc;
+}
+/// @brief Function to clean up the scan region and type
+/// @param[in] i_target Chiplet Target of Scan
+//  @param[in] chipletId data from RS4
+//  @param[in] i_chipletId data from RS4
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode cleanScanRegionandTypeData(
+    const fapi2::Target<fapi2::TARGET_TYPE_ALL>& i_target,
+    const uint8_t i_chipletId)
+{
+    fapi2::ReturnCode l_rc;
+    uint32_t l_chiplet = i_chipletId << 24;
+#ifdef __PPE__
+    uint32_t l_chipletID = i_target.getChipletNumber();
+
+    if ( l_chipletID )
+    {
+        l_chiplet = (l_chipletID << 24);
+    }
+
+#endif
+
+#ifndef __PPE__
+    // Non-PPE platform - Cronus need a Chip target to be used
+    // in putScom/getScom.
+    fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_parent(
+        i_target.template getParent<fapi2::TARGET_TYPE_PROC_CHIP>());
+#endif
+
+    do
+    {
+        //////////////////////
+        //cleanup opcg_reg0
+        //////////////////////
+        uint32_t l_scomAddress = 0x00030005;
+
+        // Add the chiplet ID in the Scom Address
+        l_scomAddress |= l_chiplet;
+
+        fapi2::buffer<uint64_t> l_data(0);
+
+#ifndef __PPE__
+        l_rc = fapi2::putScom(l_parent, l_scomAddress, l_data);
+#else
+        l_rc = fapi2::putScom(i_target, l_scomAddress, l_data);
+#endif
+
+        if(l_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("OPCG_REG0 write op failed");
+            break;
+        }
+    }
+    while(0);
+
+    return l_rc;
+}
+
+
diff --git a/src/import/chips/p9/utils/p9_putRingUtils.H b/src/import/chips/p9/utils/p9_putRingUtils.H
new file mode 100644
index 00000000..2eee9c00
--- /dev/null
+++ b/src/import/chips/p9/utils/p9_putRingUtils.H
@@ -0,0 +1,232 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/utils/p9_putRingUtils.H $                     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file p9_putRingUtils.H
+/// @brief Headers and Constants used by rs4 decompression and
+/// ring SCAN/ROTATE functionality
+///
+// *HWP HWP Owner: Bilicon Patil <bilpatil@in.ibm.com>
+// *HWP FW Owner: Prasad Ranganath <prasadbgr@in.ibm.com>
+// *HWP Team: PM
+// *HWP Level: 2
+// *HWP Consumed by: SBE:CME:SGPE:PGPE
+
+#ifndef _P9_PUTRINGUTILS_H_
+#define _P9_PUTRINGUTILS_H_
+
+#include <return_code.H>
+#include <fapi2.H>
+
+namespace RS4
+{
+
+//
+// Forward Declarations
+//
+
+/// @brief Byte-reverse a 64-bit integer
+/// @param[in] i_x 64-bit word that need to be byte reversed
+/// @return Byte reversed 64-bit word
+uint64_t rs4_revle64(const uint64_t i_x);
+
+///
+/// @brief Decode an unsigned integer from a 4-bit octal stop code.
+/// @param[in] i_rs4Str The RS4 scan string
+/// @param[in] i_nibbleIndx Index into i_rs4Str that has the stop-code
+/// @param[out] o_numRotate No.of rotates decoded from the stop-code.
+/// @return The number of nibbles decoded.
+///
+uint64_t stop_decode(const uint8_t* i_rs4Str,
+                     uint32_t i_nibbleIndx,
+                     uint64_t& o_numRotate);
+
+///
+/// @brief Return a big-endian-indexed nibble from a byte string
+/// @param[in] i_rs4Str The RS4 scan string
+/// @param[in] i_nibbleIndx Index into i_rs4Str that need to converted
+///                         into a nibble
+/// @return big-endian-indexed nibble
+///
+uint8_t rs4_get_nibble(const uint8_t* i_rs4Str, const uint32_t i_nibbleIndx);
+
+///
+/// @brief Return verbatim data from the RS4 string
+/// @param[in] i_rs4Str The RS4 scan string
+/// @param[in] i_nibbleIndx Index into i_rs4Str that need to converted
+///                         into a nibble
+/// @param[in] i_nibbleCount The count of nibbles that need to be put
+///                          in the return value.
+/// @return big-endian-indexed double word
+///
+uint64_t rs4_get_verbatim(const uint8_t* i_rs4Str,
+                          const uint32_t i_nibbleIndx,
+                          const uint8_t i_nibbleCount);
+
+}; // end of RS4 namespace
+
+using namespace RS4;
+//
+// Constants and Structures
+//
+struct restoreOpcgRegisters
+{
+    fapi2::buffer<uint64_t> l_opcgReg0;
+    fapi2::buffer<uint64_t> l_opcgReg1;
+    fapi2::buffer<uint64_t> l_opcgReg2;
+    fapi2::buffer<uint64_t> l_opcgCapt1;
+    fapi2::buffer<uint64_t> l_opcgCapt2;
+    fapi2::buffer<uint64_t> l_opcgCapt3;
+};
+
+
+#define SIXTYFOUR_BIT_HEADER 64
+
+/// @brief Constants for operations performed by putRing function.
+enum opType_t
+{
+    ROTATE = 0,  ///< Indicates a Rotate operation on the ring
+    SCAN = 1     ///< Indicates a Scan operation on the ring
+};
+
+/// @brief Constants for the type of Scans supported by putRing
+enum scanType_t
+{
+    STANDARD_SCAN = 1,  ///< used in SBE Plat
+    QUEUED_SCAN   = 2,  ///< used in CME plat
+    POLLED_SCAN   = 3   ///< used in SGPE plat
+};
+
+//
+// Function Definitions
+//
+using namespace RING_TYPES;
+void getRingProperties(const RingID i_ringId,
+                       uint32_t& o_torOffset,
+                       RINGTYPE& o_ringType,
+                       CHIPLET_TYPE& o_type);
+
+/// @brief Function to apply the Ring data using the standard-scan method
+/// @param[in] i_target Chiplet Target of Scan
+//  @param[in] i_chipletId data from RS4
+/// @param[in] i_operation Type of operation to perform - ROTATE/SCAN
+/// @param[in] i_opVal Number of bits for the operation
+/// @param[in] i_scanData This value has to be scanned when i_operation is SCAN
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode standardScan(
+    const fapi2::Target<fapi2::TARGET_TYPE_ALL>& i_target,
+    const uint8_t i_chipletId,
+    opType_t i_operation,
+    uint64_t i_opVal,
+    uint64_t i_scanData = 0);
+
+/// @brief Function to set the Scan Region
+/// @param[in] i_target Chiplet Target of Scan
+/// @param[in] i_scanRegion Value to be set to select a Scan Region
+//  @param[in] i_chipletId data from RS4
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode setupScanRegion(const fapi2::Target<fapi2::TARGET_TYPE_ALL>&
+                                  i_target,
+                                  uint64_t i_scanRegion,
+                                  const uint8_t i_chipletId);
+
+
+/// @brief Function to write the header data to the ring.
+/// @param[in] i_target Chiplet Target of Scan
+/// @param[in] i_header The header data that is to be written.
+//  @param[in] i_chipletId data from RS4
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode writeHeader(const fapi2::Target<fapi2::TARGET_TYPE_ALL>&
+                              i_target,
+                              const uint64_t i_header,
+                              const uint8_t i_chipletId);
+
+
+/// @brief Function to reader the header data from the ring and verify it.
+/// @param[in] i_target Chiplet Target of Scan
+/// @param[in] i_header The header data that is expected.
+//  @param[in] i_chipletId data from RS4
+//  @param[in] i_ringMode differnet ring mode operations
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode verifyHeader(const fapi2::Target<fapi2::TARGET_TYPE_ALL>&
+                               i_target,
+                               const uint64_t i_header,
+                               const uint8_t i_chipletId,
+                               const fapi2::RingMode i_ringMode);
+
+
+/// @brief Function to decompress the RS4 and apply the Ring data
+/// @param[in] i_target Chiplet Target of Scan
+/// @param[in] i_rs4 The RS4 compressed string
+//  @param[in] i_applyOverride: state of the override mode
+//  @param[in] i_ringMode differnet ring modes operations
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode rs4DecompressionSvc(
+    const fapi2::Target<fapi2::TARGET_TYPE_ALL>& i_target,
+    const uint8_t* i_rs4,
+    const bool i_applyOverride,
+    const fapi2::RingMode i_ringMode);
+
+
+/// @brief Function to clean up the scan region and type
+/// @param[in] i_target Chiplet Target of Scan
+//  @param[in] chipletId data from RS4
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode cleanScanRegionandTypeData(
+    const fapi2::Target<fapi2::TARGET_TYPE_ALL>& i_target,
+    const uint8_t i_chipletId);
+
+/// @brief Function to restore the opcg registers
+/// @param[in] i_target Chiplet Target of Scan
+/// @param[in] i_OPCGData opcg register data to restore original values
+//  @param[in] chipletId data from RS4
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode restoreOPCGRegData(
+    const fapi2::Target<fapi2::TARGET_TYPE_ALL>& i_target,
+    struct restoreOpcgRegisters i_OPCGData,
+    const uint8_t i_chipletId);
+
+/// @brief Function to restore the opcg registers
+/// @param[in] i_target Chiplet Target of Scan
+/// @param[out]o_OPCGData Structure that contains opcg data
+//  @param[in] i_chipletId data from RS4
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode storeOPCGRegData(
+    const fapi2::Target<fapi2::TARGET_TYPE_ALL>& i_target,
+    struct restoreOpcgRegisters& o_OPCGData,
+    const uint8_t i_chipletId);
+
+/// @brief Function to set the Scan Region for set pulse mode
+/// @param[in] i_target Chiplet Target of Scan
+/// @param[in] i_scanRegion Value to be set to select a Scan Region
+//  @param[in] i_ringMode differnet ring mode operations
+//  @param[in] i_chipletId data from RS4
+/// @return FAPI2_RC_SUCCESS if success, else error code.
+fapi2::ReturnCode setupScanRegionForSetPulse(
+    const fapi2::Target<fapi2::TARGET_TYPE_ALL>& i_target,
+    uint64_t i_scanRegion,
+    const fapi2::RingMode i_ringMode,
+    const uint8_t i_chipletId);
+
+
+#endif
diff --git a/src/import/chips/p9/utils/p9_putRingUtils.mk b/src/import/chips/p9/utils/p9_putRingUtils.mk
new file mode 100644
index 00000000..d0490344
--- /dev/null
+++ b/src/import/chips/p9/utils/p9_putRingUtils.mk
@@ -0,0 +1,28 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/utils/p9_putRingUtils.mk $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+PROCEDURE=p9_putRingUtils
+$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/utils/imageProcs)
+$(call BUILD_PROCEDURE)
diff --git a/src/import/chips/p9/utils/utils.mk b/src/import/chips/p9/utils/utils.mk
new file mode 100644
index 00000000..03c22ba7
--- /dev/null
+++ b/src/import/chips/p9/utils/utils.mk
@@ -0,0 +1,35 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/utils/utils.mk $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#  @file utils.mk
+#
+#  @brief mk for including Utils object files
+#
+##########################################################################
+# Object Files
+##########################################################################
+
+UTILS-CPP-SOURCES = p9_putRingUtils.C
+
+UTILS_OBJECTS = $(UTILS-CPP-SOURCES:.C=.o)
diff --git a/src/import/chips/p9/xip/Makefile b/src/import/chips/p9/xip/Makefile
new file mode 100644
index 00000000..b97ffc15
--- /dev/null
+++ b/src/import/chips/p9/xip/Makefile
@@ -0,0 +1,85 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/chips/p9/xip/Makefile $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+############################################################################
+# Makefile for P9-XIP image code and tools; works on X86 Linux hosts.
+# Make targets:
+# all          : Builds P9-XIP code and tools in $(OBJ_DIR)/
+# clean        : Removes the $(OBJ_DIR)/ directory
+# BINDIR can be passed in to determine the ouput directory
+############################################################################
+
+#  Locations of required headers.
+INCLUDES += -I.
+INCLUDES += -I../../../hwpf/fapi2/include/plat          # ekb: define path variable covering ekb and ppe
+INCLUDES += -I../../../../hwpf/include/plat/            # ppe: define path variable covering ekb and ppe
+
+XIP_FLAGS += -DDEBUG_P9_XIP_IMAGE=1
+XIP_FLAGS += -DFAPI2_NO_FFDC
+
+CXX_FLAGS += -std=c++11
+
+ifdef BINDIR
+OBJ_DIR = $(BINDIR)
+else
+OBJ_DIR = bin
+endif
+
+# Under Linux the scheme is to use a common compiler to create procedures.
+# However, the common compiler can be VERY slow, so if the system compiler is
+# also 4.1.2 we're using that one instead.  Also, the Linux FAPI libraries we
+# link with are 32-bit only so we need to force 32-bit mode.
+
+CXX  = g++
+
+CXX_RELEASE = 4.8.2
+CXX_VERSION = $(shell $(CXX) -v 2>&1 | grep "$(CXX_RELEASE)")
+ifeq ($(CXX_VERSION),)
+$(error wrong compiler version. Use $(CXX_RELEASE) compiler. Try: "scl enable devtoolset-2 bash")
+endif
+
+XIP_UTILS = p9_xip_tool
+
+#  Utility targets
+XIP_EXECUTABLES  = $(patsubst %,$(OBJ_DIR)/%,$(XIP_UTILS))
+
+.PHONY : all clean
+
+all: $(OBJ_DIR) $(XIP_EXECUTABLES)
+
+$(OBJ_DIR):
+	mkdir -p $(OBJ_DIR)
+
+$(OBJ_DIR)/%.o: %.c
+	$(CXX) $(CXX_FLAGS) $(INCLUDES) $(XIP_FLAGS) -c -o $@ $<
+
+$(OBJ_DIR)/%.o: %.C
+	$(CXX) $(CXX_FLAGS) $(INCLUDES) $(XIP_FLAGS) -c -o $@ $<
+
+$(OBJ_DIR)/p9_xip_tool: $(OBJ_DIR)/p9_xip_image.o  $(OBJ_DIR)/p9_xip_tool.o
+	$(CXX) -o $@ $^
+
+clean:
+	rm -rf $(OBJ_DIR)
diff --git a/src/import/chips/p9/xip/p9_xip_image.c b/src/import/chips/p9/xip/p9_xip_image.c
new file mode 100644
index 00000000..0f9ce1f7
--- /dev/null
+++ b/src/import/chips/p9/xip/p9_xip_image.c
@@ -0,0 +1,3223 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/xip/p9_xip_image.c $                          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+/// \file p9_xip_image.c
+/// \brief APIs for validating, normalizing, searching and manipulating
+/// P9-XIP images.
+///
+/// The background, APIs and implementation details are documented in the
+/// document "P9-XIP Binary format" currently available at this link:
+///
+/// - https://mcdoc.boeblingen.de.ibm.com/out/out.ViewDocument.php?documentid=2678
+///
+/// \bug The p9_xip_validate() API should be carefully reviewed to ensure
+/// that validating even a corrupt image can not lead to a segfault, i.e., to
+/// ensure that no memory outside of the putative bounds of the image is ever
+/// referenced during validation.
+
+#ifndef PLIC_MODULE
+    #include <stddef.h>
+    #include <stdint.h>
+    #include <stdlib.h>
+    #include <string.h>
+#endif // PLIC_MODULE
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <endian.h>
+#include "p9_xip_image.h"
+
+////////////////////////////////////////////////////////////////////////////
+// Local Functions
+////////////////////////////////////////////////////////////////////////////
+
+#ifdef DEBUG_P9_XIP_IMAGE
+
+// Debugging support, normally disabled. All of the formatted I/O you see in
+// the code is effectively under this switch.
+
+#ifdef __FAPI
+
+    #include "fapi.H"
+    #define fprintf(stream, ...) FAPI_ERR(__VA_ARGS__)
+    #define printf(...) FAPI_INF(__VA_ARGS__)
+    #define TRACE_NEWLINE ""
+
+#else // __FAPI
+
+    #include <stdio.h>
+    #define TRACE_NEWLINE "\n"
+
+#endif // __FAPI
+
+// Portable formatting of uint64_t.  The ISO C99 standard requires
+// __STDC_FORMAT_MACROS to be defined in order for PRIx64 etc. to be defined.
+
+#define __STDC_FORMAT_MACROS
+#include <inttypes.h>
+
+#define F0x016llx "0x%016" PRIx64
+#define F0x012llx "0x%012" PRIx64
+
+XIP_STATIC P9_XIP_ERROR_STRINGS(p9_xip_error_strings);
+
+#define TRACE_ERROR(x)                                                  \
+    ({                                                                  \
+        fprintf(stderr, "%s:%d : Returning error code %d : %s" TRACE_NEWLINE, \
+                __FILE__, __LINE__, (x),                                \
+                P9_XIP_ERROR_STRING(p9_xip_error_strings, (x)));      \
+        (x);                                                            \
+    })
+
+#define TRACE_ERRORX(x, ...)                    \
+    ({                                          \
+        TRACE_ERROR(x);                         \
+        fprintf(stderr, ##__VA_ARGS__);         \
+        (x);                                    \
+    })
+
+// Uncomment these if required for debugging, otherwise we get warnings from
+// GCC as they are not otherwise used.
+
+#if 0
+
+XIP_STATIC P9_XIP_TYPE_STRINGS(type_strings);
+
+XIP_STATIC void
+dumpToc(int index, P9XipToc* toc)
+{
+    printf("TOC entry %d @ %p\n"
+           "    iv_id       = 0x%08x\n"
+           "    iv_data     = 0x%08x\n"
+           "    iv_type     = %s\n"
+           "    iv_section  = 0x%02x\n"
+           "    iv_elements = %d\n",
+           index, toc,
+           htobe32(toc->iv_id),
+           htobe32(toc->iv_data),
+           P9_XIP_TYPE_STRING(type_strings, toc->iv_type),
+           toc->iv_section,
+           toc->iv_elements);
+}
+
+#endif
+
+#if 0
+
+XIP_STATIC void
+dumpItem(P9XipItem* item)
+{
+    printf("P9XipItem @ %p\n"
+           "    iv_toc       = %p\n"
+           "    iv_address   = " F0x016llx "\n"
+           "    iv_imageData = %p\n"
+           "    iv_id        = %s\n"
+           "    iv_type      = %s\n"
+           "    iv_elements  = %d\n",
+           item,
+           item->iv_toc,
+           item->iv_address,
+           item->iv_imageData,
+           item->iv_id,
+           P9_XIP_TYPE_STRING(type_strings, item->iv_type),
+           item->iv_elements);
+    dumpToc(-1, item->iv_toc);
+}
+
+#endif  /* 0 */
+
+XIP_STATIC void
+dumpSectionTable(const void* i_image)
+{
+    int i, rc;
+    P9XipSection section;
+
+    printf("Section table dump of image @ %p\n"
+           "  Entry    Offset        Size\n"
+           "-------------------------------\n",
+           i_image);
+
+    for (i = 0; i < P9_XIP_SECTIONS; i++)
+    {
+        rc = p9_xip_get_section(i_image, i, &section);
+
+        if (rc)
+        {
+            printf(">>> dumpSectionTable got error at entry %d : %s\n",
+                   i, P9_XIP_ERROR_STRING(p9_xip_error_strings, rc));
+            break;
+        }
+
+        printf("%7d  0x%08x  0x%08x\n",
+               i, section.iv_offset, section.iv_size);
+    }
+}
+
+#else
+
+#define TRACE_ERROR(x) (x)
+#define TRACE_ERRORX(x, ...) (x)
+#define dumpToc(...)
+#define dumpItem(...)
+#define dumpSectionTable(...)
+
+#endif
+
+
+XIP_STATIC uint64_t
+xipLinkAddress(const void* i_image)
+{
+    return htobe64(((P9XipHeader*)i_image)->iv_linkAddress);
+}
+
+
+/// What is the image size?
+
+XIP_STATIC uint32_t
+xipImageSize(const void* i_image)
+{
+    return htobe32(((P9XipHeader*)i_image)->iv_imageSize);
+}
+
+
+/// Set the image size
+
+XIP_STATIC void
+xipSetImageSize(void* io_image, const size_t i_size)
+{
+    ((P9XipHeader*)io_image)->iv_imageSize = htobe32(i_size);
+}
+
+
+/// Re-establish the required final alignment
+
+XIP_STATIC void
+xipFinalAlignment(void* io_image)
+{
+    uint32_t size;
+
+    size = xipImageSize(io_image);
+
+    if ((size % P9_XIP_FINAL_ALIGNMENT) != 0)
+    {
+        xipSetImageSize(io_image,
+                        size + (P9_XIP_FINAL_ALIGNMENT -
+                                (size % P9_XIP_FINAL_ALIGNMENT)));
+    }
+}
+
+
+/// Compute a host address from an image address and offset
+
+XIP_STATIC void*
+xipHostAddressFromOffset(const void* i_image, const uint32_t offset)
+{
+    return (void*)((unsigned long)i_image + offset);
+}
+
+
+/// Convert a IMAGE address to a host address
+
+XIP_STATIC void*
+xipImage2Host(const void* i_image, const uint64_t i_imageAddress)
+{
+    return xipHostAddressFromOffset(i_image,
+                                    i_imageAddress - xipLinkAddress(i_image));
+}
+
+
+XIP_STATIC int
+xipValidateImageAddress(const void* i_image,
+                        const uint64_t i_imageAddress,
+                        const uint32_t size)
+{
+    int rc;
+
+    if ((i_imageAddress < xipLinkAddress(i_image)) ||
+        (i_imageAddress > (xipLinkAddress(i_image) +
+                           xipImageSize(i_image) -
+                           size)))
+    {
+        rc = TRACE_ERRORX(P9_XIP_INVALID_ARGUMENT,
+                          "The IMAGE address " F0x012llx
+                          " is outside the bounds "
+                          "of the image ("
+                          F0x012llx ":" F0x012llx
+                          ") for %u-byte access.\n",
+                          i_imageAddress,
+                          xipLinkAddress(i_image),
+                          xipLinkAddress(i_image) + xipImageSize(i_image) - 1,
+                          size);
+    }
+    else
+    {
+        rc = 0;
+    }
+
+    return rc;
+}
+
+
+/// Get the magic number from the image
+
+XIP_STATIC uint64_t
+xipMagic(const void* i_image)
+{
+    return htobe64(((P9XipHeader*)i_image)->iv_magic);
+}
+
+
+/// Get the header version from the image
+
+XIP_STATIC uint8_t
+xipHeaderVersion(const void* i_image)
+{
+    return ((P9XipHeader*)i_image)->iv_headerVersion;
+}
+
+
+/// Has the image been normalized?
+
+XIP_STATIC uint8_t
+xipNormalized(const void* i_image)
+{
+    return ((P9XipHeader*)i_image)->iv_normalized;
+}
+
+
+/// Has the image TOC been sorted?
+
+XIP_STATIC uint8_t
+xipSorted(const void* i_image)
+{
+    return ((P9XipHeader*)i_image)->iv_tocSorted;
+}
+
+
+/// A quick check that the image exists, has the correct magic and header
+/// version, and optionally is normalized.
+
+XIP_STATIC int
+xipQuickCheck(const void* i_image, const int i_normalizationRequired)
+{
+    int rc;
+
+    do
+    {
+        rc = 0;
+
+        if (i_image == 0)
+        {
+            rc = TRACE_ERRORX(P9_XIP_IMAGE_ERROR,
+                              "Image pointer is NULL (0)\n");
+            break;
+        }
+
+        if ((xipMagic(i_image) >> 32) != P9_XIP_MAGIC)
+        {
+            rc = TRACE_ERRORX(P9_XIP_IMAGE_ERROR,
+                              "Magic number mismatch; Found "
+                              "" F0x016llx ", expected 0x%08x........\n",
+                              xipMagic(i_image), P9_XIP_MAGIC);
+            break;
+        }
+
+        if ((xipHeaderVersion(i_image)) != P9_XIP_HEADER_VERSION)
+        {
+            rc = TRACE_ERRORX(P9_XIP_IMAGE_ERROR,
+                              "Header version mismatch; Expecting %d, "
+                              "found %d\n",
+                              P9_XIP_HEADER_VERSION,
+                              xipHeaderVersion(i_image));
+            break;
+        }
+
+        if (i_normalizationRequired && !xipNormalized(i_image))
+        {
+            rc = TRACE_ERRORX(P9_XIP_NOT_NORMALIZED,
+                              "Image not normalized\n");
+            break;
+        }
+    }
+    while(0);
+
+    return rc;
+}
+
+
+/// Convert a 32-bit relocatable offset to a full IMAGE 48-bit address
+
+XIP_STATIC uint64_t
+xipFullAddress(const void* i_image, uint32_t offset)
+{
+    return (xipLinkAddress(i_image) & 0x0000ffff00000000ull) + offset;
+}
+
+
+/// Translate a section table entry
+
+XIP_STATIC void
+xipTranslateSection(P9XipSection* o_dest, const P9XipSection* i_src)
+{
+#ifndef _BIG_ENDIAN
+
+#if P9_XIP_HEADER_VERSION != 9
+#error This code assumes the P9-XIP header version 9 layout
+#endif
+
+    o_dest->iv_offset = htobe32(i_src->iv_offset);
+    o_dest->iv_size = htobe32(i_src->iv_size);
+    o_dest->iv_alignment = i_src->iv_alignment;
+    o_dest->iv_reserved8[0] = 0;
+    o_dest->iv_reserved8[1] = 0;
+    o_dest->iv_reserved8[2] = 0;
+#else
+
+    if (o_dest != i_src)
+    {
+        *o_dest = *i_src;
+    }
+
+#endif  /* _BIG_ENDIAN */
+}
+
+
+/// Translate a TOC entry
+
+XIP_STATIC void
+xipTranslateToc(P9XipToc* o_dest, P9XipToc* i_src)
+{
+#ifndef _BIG_ENDIAN
+
+#if P9_XIP_HEADER_VERSION != 9
+#error This code assumes the P9-XIP header version 9 layout
+#endif
+
+    o_dest->iv_id = htobe32(i_src->iv_id);
+    o_dest->iv_data = htobe32(i_src->iv_data);
+    o_dest->iv_type = i_src->iv_type;
+    o_dest->iv_section = i_src->iv_section;
+    o_dest->iv_elements = i_src->iv_elements;
+    o_dest->iv_pad = 0;
+#else
+
+    if (o_dest != i_src)
+    {
+        *o_dest = *i_src;
+    }
+
+#endif  /* _BIG_ENDIAN */
+}
+
+
+/// Find the final (highest-address) section of the image
+
+XIP_STATIC int
+xipFinalSection(const void* i_image, int* o_sectionId)
+{
+    int i, rc, found;
+    uint32_t offset;
+    P9XipHeader hostHeader;
+
+    p9_xip_translate_header(&hostHeader, (P9XipHeader*)i_image);
+
+    found = 0;
+    offset = 0;
+    *o_sectionId = 0;           /* Make GCC -O3 happy */
+
+    for (i = 0; i < P9_XIP_SECTIONS; i++)
+    {
+        if ((hostHeader.iv_section[i].iv_size != 0) &&
+            (hostHeader.iv_section[i].iv_offset >= offset))
+        {
+            *o_sectionId = i;
+            offset = hostHeader.iv_section[i].iv_offset;
+            found = 1;
+        }
+    }
+
+    if (!found)
+    {
+        rc = TRACE_ERRORX(P9_XIP_IMAGE_ERROR, "The image is empty\n");
+    }
+    else
+    {
+        rc = 0;
+    }
+
+    return rc;
+}
+
+
+/// Return a pointer to an image-format section table entry
+
+XIP_STATIC int
+xipGetSectionPointer(const void* i_image,
+                     const int i_sectionId,
+                     P9XipSection** o_imageSection)
+{
+    int rc;
+
+    if ((i_sectionId < 0) || (i_sectionId >= P9_XIP_SECTIONS))
+    {
+        rc = TRACE_ERROR(P9_XIP_INVALID_ARGUMENT);
+    }
+    else
+    {
+        *o_imageSection =
+            &(((P9XipHeader*)i_image)->iv_section[i_sectionId]);
+        rc = 0;
+    }
+
+    return rc;
+}
+
+
+/// Restore a section table entry from host format to image format.
+
+XIP_STATIC int
+xipPutSection(const void* i_image,
+              const int i_sectionId,
+              P9XipSection* i_hostSection)
+{
+    int rc;
+    P9XipSection* imageSection;
+
+    rc = xipGetSectionPointer(i_image, i_sectionId, &imageSection);
+
+    if (!rc)
+    {
+        xipTranslateSection(imageSection, i_hostSection);
+    }
+
+    return rc;
+}
+
+
+/// Set the offset of a section
+
+XIP_STATIC int
+xipSetSectionOffset(void* io_image, const int i_section,
+                    const uint32_t i_offset)
+{
+    P9XipSection* section;
+    int rc;
+
+    rc = xipGetSectionPointer(io_image, i_section, &section);
+
+    if (!rc)
+    {
+        section->iv_offset = htobe32(i_offset);
+    }
+
+    return rc;
+}
+
+
+/// Set the size of a section
+
+XIP_STATIC int
+xipSetSectionSize(void* io_image, const int i_section, const uint32_t i_size)
+{
+    P9XipSection* section;
+    int rc;
+
+    rc = xipGetSectionPointer(io_image, i_section, &section);
+
+    if (!rc)
+    {
+        section->iv_size = htobe32(i_size);
+    }
+
+    return rc;
+}
+
+
+/// Translate a IMAGE address in the image to a section and offset
+
+// We first check to be sure that the IMAGE address is contained in the image,
+// using the full 48-bit form.  Then we scan the section table to see which
+// section contains the address - if none then the image is corrupted. We can
+// (must) use the 32-bit offset form of the address here.
+
+XIP_STATIC int
+xipImage2Section(const void* i_image,
+                 const uint64_t i_imageAddress,
+                 int* o_section,
+                 uint32_t* o_offset)
+{
+    int rc, sectionId;
+    P9XipSection section;
+    uint32_t addressOffset;
+
+    do
+    {
+        rc = 0;
+
+        if ((i_imageAddress < xipLinkAddress(i_image)) ||
+            (i_imageAddress >
+             (xipLinkAddress(i_image) + xipImageSize(i_image))))
+        {
+            rc = TRACE_ERRORX(P9_XIP_INVALID_ARGUMENT,
+                              "image2section: The i_imageAddress argument "
+                              "(" F0x016llx ")\nis outside the bounds of the "
+                              "image (" F0x016llx ":" F0x016llx ")\n",
+                              i_imageAddress,
+                              xipLinkAddress(i_image),
+                              xipLinkAddress(i_image) + xipImageSize(i_image));
+            break;
+        }
+
+        addressOffset = (i_imageAddress - xipLinkAddress(i_image)) & 0xffffffff;
+
+        for (sectionId = 0; sectionId < P9_XIP_SECTIONS; sectionId++)
+        {
+            rc = p9_xip_get_section(i_image, sectionId, &section);
+
+            if (rc)
+            {
+                rc = TRACE_ERROR(P9_XIP_BUG); /* Can't happen */
+                break;
+            }
+
+            if ((section.iv_size != 0) &&
+                (addressOffset >= section.iv_offset) &&
+                (addressOffset < (section.iv_offset + section.iv_size)))
+            {
+                break;
+            }
+        }
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (sectionId == P9_XIP_SECTIONS)
+        {
+            rc = TRACE_ERRORX(P9_XIP_IMAGE_ERROR,
+                              "Error processing IMAGE address " F0x016llx ". "
+                              "The address is not mapped in any section.\n"
+                              "A section table dump appears below\n",
+                              i_imageAddress);
+            dumpSectionTable(i_image);
+            break;
+        }
+
+        *o_section = sectionId;
+        *o_offset = addressOffset - section.iv_offset;
+
+    }
+    while(0);
+
+    return rc;
+}
+
+
+// Delete the last, i.e., final, section of the image.
+
+XIP_STATIC int
+xipDeleteLastSection(void* io_image,
+                     const int i_sectionId)
+{
+    int rc, final;
+    P9XipSection section;
+
+    do
+    {
+
+        xipSetSectionOffset(io_image, i_sectionId, 0);
+        xipSetSectionSize(io_image, i_sectionId, 0);
+
+
+        // For cleanliness we also remove any alignment padding that had been
+        // appended between the now-last section and the deleted section, then
+        // re-establish the final alignment. The assumption is that all images
+        // always have the correct final alignment, so there is no way this
+        // could overflow a designated buffer space since the image size is
+        // the same or has been reduced.
+
+        rc = xipFinalSection(io_image, &final);
+
+        if (rc)
+        {
+            break;
+        }
+
+        rc = p9_xip_get_section(io_image, final, &section);
+
+        if (rc)
+        {
+            break;
+        }
+
+        xipSetImageSize(io_image, section.iv_offset + section.iv_size);
+        xipFinalAlignment(io_image);
+
+    }
+    while (0);
+
+    return rc;
+}
+
+
+/// Get the information required to search the TOC.
+///
+/// All return values are optional.
+
+int
+p9_xip_get_toc(void* i_image,
+               P9XipToc** o_toc,
+               size_t* o_entries,
+               int* o_sorted,
+               char** o_strings)
+{
+    int rc;
+    P9XipSection tocSection, stringsSection;
+
+    do
+    {
+        rc = p9_xip_get_section(i_image, P9_XIP_SECTION_TOC, &tocSection);
+
+        if (rc)
+        {
+            break;
+        }
+
+        rc = p9_xip_get_section(i_image, P9_XIP_SECTION_STRINGS,
+                                &stringsSection);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (o_toc)
+        {
+            *o_toc = (P9XipToc*)((uint8_t*)i_image + tocSection.iv_offset);
+        }
+
+        if (o_entries)
+        {
+            *o_entries = tocSection.iv_size / sizeof(P9XipToc);
+        }
+
+        if (o_sorted)
+        {
+            *o_sorted = xipSorted(i_image);
+        }
+
+        if (o_strings)
+        {
+            *o_strings = (char*)i_image + stringsSection.iv_offset;
+        }
+    }
+    while (0);
+
+    return rc;
+}
+
+
+/// Compare two normalized TOC entries for sorting.
+
+XIP_STATIC int
+xipCompareToc(const P9XipToc* i_a, const P9XipToc* i_b,
+              const char* i_strings)
+{
+    return strcmp(i_strings + htobe32(i_a->iv_id),
+                  i_strings + htobe32(i_b->iv_id));
+}
+
+
+/// Iterative quicksort of the TOC
+
+// Note: The stack requirement is limited to 256 bytes + minor local storage.
+
+XIP_STATIC void
+xipQuickSort(P9XipToc* io_toc, int i_left, int i_right,
+             const char* i_strings)
+{
+    int i, j, left, right, sp;
+    P9XipToc pivot, temp;
+    uint32_t stack[64];
+
+    sp = 0;
+    stack[sp++] = i_left;
+    stack[sp++] = i_right;
+
+    while (sp)
+    {
+
+        right = stack[--sp];
+        left = stack[--sp];
+
+        i = left;
+        j = right;
+
+        pivot = io_toc[(i + j) / 2];
+
+        while (i <= j)
+        {
+            while (xipCompareToc(&(io_toc[i]), &pivot, i_strings) < 0)
+            {
+                i++;
+            }
+
+            while (xipCompareToc(&(io_toc[j]), &pivot, i_strings) > 0)
+            {
+                j--;
+            }
+
+            if (i <= j)
+            {
+                temp = io_toc[i];
+                io_toc[i] = io_toc[j];
+                io_toc[j] = temp;
+                i++;
+                j--;
+            }
+        }
+
+        if (left < j)
+        {
+            stack[sp++] = left;
+            stack[sp++] = j;
+        }
+
+        if (i < right)
+        {
+            stack[sp++] = i;
+            stack[sp++] = right;
+        }
+    }
+}
+
+
+/// TOC linear search
+
+XIP_STATIC int
+xipLinearSearch(void* i_image, const char* i_id, P9XipToc** o_entry)
+{
+    int rc;
+    P9XipToc* imageToc, hostToc;
+    size_t entries;
+    char* strings;
+
+    *o_entry = 0;
+    rc = p9_xip_get_toc(i_image, &imageToc, &entries, 0, &strings);
+
+    if (!rc)
+    {
+        for (; entries; entries--, imageToc++)
+        {
+            xipTranslateToc(&hostToc, imageToc);
+
+            if (strcmp(i_id, strings + hostToc.iv_id) == 0)
+            {
+                break;
+            }
+        }
+
+        if (entries)
+        {
+            *o_entry = imageToc;
+            rc = 0;
+        }
+        else
+        {
+            *o_entry = 0;
+            rc = TRACE_ERROR(P9_XIP_ITEM_NOT_FOUND);
+        }
+    }
+
+    return rc;
+}
+
+
+/// A classic binary search of a (presumed) sorted array
+
+XIP_STATIC int
+xipBinarySearch(void* i_image, const char* i_id, P9XipToc** o_entry)
+{
+    int rc;
+    P9XipToc* imageToc;
+    size_t entries;
+    char* strings;
+    int sorted, left, right, next, sort;
+
+    do
+    {
+        *o_entry = 0;
+
+        rc = p9_xip_get_toc(i_image, &imageToc, &entries, &sorted, &strings);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (!sorted)
+        {
+            rc = TRACE_ERROR(P9_XIP_BUG);
+            break;
+        }
+
+        left = 0;
+        right = entries - 1;
+
+        while (left <= right)
+        {
+            next = (left + right) / 2;
+            sort = strcmp(i_id, strings + htobe32(imageToc[next].iv_id));
+
+            if (sort == 0)
+            {
+                *o_entry = &(imageToc[next]);
+                break;
+            }
+            else if (sort < 0)
+            {
+                right = next - 1;
+            }
+            else
+            {
+                left = next + 1;
+            }
+        }
+
+        if (*o_entry == 0)
+        {
+            rc = TRACE_ERROR(P9_XIP_ITEM_NOT_FOUND);
+            break;
+        }
+    }
+    while (0);
+
+    return rc;
+}
+
+
+/// Validate a TOC entry as a mapping function
+///
+/// The TOC is validated by searching for the entry, which will uncover
+/// duplicate entries or problems with sorting/searching.
+
+XIP_STATIC int
+xipValidateTocEntry(void* io_image, const P9XipItem* i_item, void* io_arg)
+{
+    int rc;
+    P9XipItem found;
+
+    do
+    {
+        rc = p9_xip_find(io_image, i_item->iv_id, &found);
+
+        if (rc)
+        {
+            rc = TRACE_ERRORX(rc, "TOC entry for %s not found\n",
+                              i_item->iv_id);
+        }
+        else if (found.iv_toc != i_item->iv_toc)
+        {
+            rc = TRACE_ERRORX(P9_XIP_TOC_ERROR,
+                              "Duplicate TOC entry for '%s'\n", i_item->iv_id);
+        }
+
+        break;
+    }
+    while (0);
+
+    return rc;
+}
+
+
+// This is the FNV-1a hash, used for hashing symbol names in the .fixed
+// section into 32-bit hashes for the mini-TOC.
+
+// According to the authors:
+
+// "FNV hash algorithms and source code have been released into the public
+// domain. The authors of the FNV algorithmm look deliberate steps to disclose
+// the algorhtm (sic) in a public forum soon after it was invented. More than
+// a year passed after this public disclosure and the authors deliberatly took
+// no steps to patent the FNV algorithm. Therefore it is safe to say that the
+// FNV authors have no patent claims on the FNV algorithm as published."
+
+#define FNV_OFFSET_BASIS 2166136261u
+#define FNV_PRIME32 16777619u
+
+uint32_t
+xipHash32(const char* s)
+{
+    uint32_t hash;
+
+    hash = FNV_OFFSET_BASIS;
+
+    while (*s)
+    {
+        hash ^= *s++;
+        hash *= FNV_PRIME32;
+    }
+
+    return hash;
+}
+
+
+// Normalize a TOC entry
+
+// Normalize the TOC entry by converting relocatable pointers into 32-bit
+// offsets from the beginning of the section containing the data. All
+// addresses in the TOC are actually 32-bit offsets in the address space named
+// in bits 16:31 of the link address of the image.
+
+XIP_STATIC int
+xipNormalizeToc(void* io_image, P9XipToc* io_imageToc,
+                P9XipHashedToc** io_fixedTocEntry,
+                size_t* io_fixedEntriesRemaining)
+{
+    P9XipToc hostToc;
+    int idSection, dataSection;
+    uint32_t idOffset, dataOffset;
+    char* hostString;
+    int rc;
+
+    do
+    {
+
+        // Translate the TOC entry to host format.  Then locate the
+        // sections/offsets of the Id string (which must be in .strings) and
+        // the data.
+
+        xipTranslateToc(&hostToc, io_imageToc);
+
+        hostString =
+            (char*)xipImage2Host(io_image,
+                                 xipFullAddress(io_image, hostToc.iv_id));
+
+        rc = xipImage2Section(io_image,
+                              xipFullAddress(io_image, hostToc.iv_id),
+                              &idSection,
+                              &idOffset);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (idSection != P9_XIP_SECTION_STRINGS)
+        {
+            rc = TRACE_ERROR(P9_XIP_IMAGE_ERROR);
+            break;
+        }
+
+        rc = xipImage2Section(io_image,
+                              xipFullAddress(io_image, hostToc.iv_data),
+                              &dataSection,
+                              &dataOffset);
+
+        if (rc)
+        {
+            break;
+        }
+
+        // Now replace the Id and data pointers with their offsets, and update
+        // the data section in the TOC entry.
+
+        hostToc.iv_id = idOffset;
+        hostToc.iv_data = dataOffset;
+        hostToc.iv_section = dataSection;
+
+        // If this TOC entry is from .fixed, create a new record in .fixed_toc
+
+        if (hostToc.iv_section == P9_XIP_SECTION_FIXED)
+        {
+
+            if (*io_fixedEntriesRemaining == 0)
+            {
+                rc = TRACE_ERRORX(P9_XIP_TOC_ERROR,
+                                  "Too many TOC entries for .fixed\n");
+                break;
+            }
+
+            if (hostToc.iv_data != (uint16_t)hostToc.iv_data)
+            {
+                rc = TRACE_ERRORX(P9_XIP_IMAGE_ERROR,
+                                  "The .fixed section is too big to index\n");
+                break;
+            }
+
+            (*io_fixedTocEntry)->iv_hash = htobe32(xipHash32(hostString));
+            (*io_fixedTocEntry)->iv_offset = htobe16(hostToc.iv_data);
+            (*io_fixedTocEntry)->iv_type = hostToc.iv_type;
+            (*io_fixedTocEntry)->iv_elements = hostToc.iv_elements;
+
+            (*io_fixedTocEntry)++;
+            (*io_fixedEntriesRemaining)--;
+        }
+
+        // Finally update the TOC entry
+
+        xipTranslateToc(io_imageToc, &hostToc);
+
+    }
+    while (0);
+
+    return rc;
+}
+
+
+// Check for hash collisions in the .fixed mini-TOC.  Note that endianness is
+// not an issue here, as we're comparing for equality.
+
+XIP_STATIC int
+xipHashCollision(P9XipHashedToc* i_fixedToc, size_t i_entries)
+{
+    int rc;
+    size_t i, j;
+
+    rc = 0;
+
+    for (i = 0; i < i_entries; i++)
+    {
+        for (j = i + 1; j < i_entries; j++)
+        {
+            if (i_fixedToc[i].iv_hash == i_fixedToc[j].iv_hash)
+            {
+                rc = TRACE_ERRORX(P9_XIP_HASH_COLLISION,
+                                  "Hash collision at index %zd\n",
+                                  i);
+                break;
+            }
+        }
+
+        if (rc)
+        {
+            break;
+        }
+    }
+
+    return rc;
+}
+
+
+/// Decode a normalized image-format TOC entry into a host-format P9XipItem
+/// structure
+
+XIP_STATIC int
+xipDecodeToc(void* i_image,
+             P9XipToc* i_imageToc,
+             P9XipItem* o_item)
+{
+    int rc;
+    P9XipToc hostToc;
+    P9XipSection dataSection, stringsSection;
+
+    do
+    {
+        if (!xipNormalized(i_image))
+        {
+            rc = TRACE_ERROR(P9_XIP_NOT_NORMALIZED);
+            break;
+        }
+
+
+        // Translate the TOC entry and set the TOC pointer, data type and
+        // number of elements in the outgoing structure. The Id string is
+        // always located in the TOC_STRINGS section.
+
+        xipTranslateToc(&hostToc, i_imageToc);
+
+        o_item->iv_toc = i_imageToc;
+        o_item->iv_type = hostToc.iv_type;
+        o_item->iv_elements = hostToc.iv_elements;
+
+        p9_xip_get_section(i_image, P9_XIP_SECTION_STRINGS, &stringsSection);
+        o_item->iv_id =
+            (char*)i_image + stringsSection.iv_offset + hostToc.iv_id;
+
+
+        // The data (or text address) are addressed by relative offsets from
+        // the beginning of their section.  The TOC entry may remain in the TOC
+        // even though the section has been removed from the image, so this
+        // case needs to be covered.
+
+        rc = p9_xip_get_section(i_image, hostToc.iv_section, &dataSection);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (dataSection.iv_size == 0)
+        {
+            rc = TRACE_ERROR(P9_XIP_DATA_NOT_PRESENT);
+            break;
+        }
+
+        o_item->iv_imageData =
+            (void*)((uint8_t*)i_image +
+                    dataSection.iv_offset + hostToc.iv_data);
+
+        o_item->iv_address =
+            xipLinkAddress(i_image) + dataSection.iv_offset + hostToc.iv_data;
+
+        o_item->iv_partial = 0;
+
+    }
+    while (0);
+
+    return rc;
+}
+
+int
+p9_xip_decode_toc_dump(void* i_image, void* i_dump,
+                       P9XipToc* i_imageToc,
+                       P9XipItem* o_item)
+{
+    int rc = 0;
+    P9XipToc hostToc = {0};
+    P9XipSection stringsSection = {0};
+
+    if (!xipNormalized(i_image))
+    {
+        rc = TRACE_ERROR(P9_XIP_NOT_NORMALIZED);
+        return rc;
+    }
+
+    // Translate the TOC entry and set the TOC pointer, data type and
+    // number of elements in the outgoing structure. The Id string is
+    // always located in the TOC_STRINGS section.
+
+    xipTranslateToc(&hostToc, i_imageToc);
+
+    o_item->iv_toc = i_imageToc;
+    o_item->iv_type = hostToc.iv_type;
+    o_item->iv_elements = hostToc.iv_elements;
+
+    p9_xip_get_section(i_image, P9_XIP_SECTION_STRINGS, &stringsSection);
+    o_item->iv_id =
+        (char*)i_image + stringsSection.iv_offset + hostToc.iv_id;
+
+    //Print only the attributes present in fixed section of SEEPROM image
+    if (hostToc.iv_section == P9_XIP_SECTION_FIXED)
+    {
+        //get the attribute value from dump file
+        o_item->iv_imageData = (void*)((uint8_t*)i_dump + hostToc.iv_data);
+        o_item->iv_address = xipLinkAddress(i_image) + hostToc.iv_data;
+        o_item->iv_partial = 0;
+    }
+    else
+    {
+        o_item->iv_address = 0;
+    }
+
+    return rc;
+}
+
+/// Sort the TOC
+
+XIP_STATIC int
+xipSortToc(void* io_image)
+{
+    int rc;
+    P9XipToc* hostToc;
+    size_t entries;
+    char* strings;
+
+    do
+    {
+        rc = xipQuickCheck(io_image, 1);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (xipSorted(io_image))
+        {
+            break;
+        }
+
+        rc = p9_xip_get_toc(io_image, &hostToc, &entries, 0, &strings);
+
+        if (rc)
+        {
+            break;
+        }
+
+        xipQuickSort(hostToc, 0, entries - 1, strings);
+
+        ((P9XipHeader*)io_image)->iv_tocSorted = 1;
+
+    }
+    while (0);
+
+    return rc;
+}
+
+
+// Pad the image with 0 to a given power-of-2 alignment.  The image size is
+// modified to reflect the pad, but the caller must modify the section size to
+// reflect the pad.
+
+XIP_STATIC int
+xipPadImage(void* io_image, uint32_t i_allocation,
+            uint32_t i_align, uint32_t* pad)
+{
+    int rc;
+
+    do
+    {
+        rc = 0;
+
+        if ((i_align == 0) || ((i_align & (i_align - 1)) != 0))
+        {
+            rc = TRACE_ERRORX(P9_XIP_INVALID_ARGUMENT,
+                              "Alignment specification (%u) "
+                              "not a power-of-2\n",
+                              i_align);
+            break;
+        }
+
+        *pad = xipImageSize(io_image) % i_align;
+
+        if (*pad != 0)
+        {
+            *pad = i_align - *pad;
+
+            if ((xipImageSize(io_image) + *pad) > i_allocation)
+            {
+                rc = TRACE_ERROR(P9_XIP_WOULD_OVERFLOW);
+                break;
+            }
+
+            memset((void*)((unsigned long)io_image + xipImageSize(io_image)),
+                   0, *pad);
+            xipSetImageSize(io_image, xipImageSize(io_image) + *pad);
+        }
+    }
+    while (0);
+
+    return rc;
+}
+
+
+//  Get the .fixed_toc section
+
+XIP_STATIC int
+xipGetFixedToc(void* io_image,
+               P9XipHashedToc** o_imageToc,
+               size_t* o_entries)
+{
+    int rc;
+    P9XipSection section;
+
+    rc = p9_xip_get_section(io_image, P9_XIP_SECTION_FIXED_TOC, &section);
+
+    if (!rc)
+    {
+
+        *o_imageToc =
+            (P9XipHashedToc*)((unsigned long)io_image + section.iv_offset);
+
+        *o_entries = section.iv_size / sizeof(P9XipHashedToc);
+    }
+
+    return rc;
+}
+
+
+// Search for an item in the fixed TOC, and populate a partial TOC entry if
+// requested. This table is small and unsorted so a linear search is
+// adequate. The TOC structures are also small so all byte-reversal is done
+// 'by hand' rather than with a translate-type API.
+
+XIP_STATIC int
+xipFixedFind(void* i_image, const char* i_id, P9XipItem* o_item)
+{
+    int rc;
+    P9XipHashedToc* toc;
+    size_t entries;
+    uint32_t hash;
+    P9XipSection fixedSection;
+    uint32_t offset;
+
+    do
+    {
+        rc = xipGetFixedToc(i_image, &toc, &entries);
+
+        if (rc)
+        {
+            break;
+        }
+
+        for (hash = htobe32(xipHash32(i_id)); entries != 0; entries--, toc++)
+        {
+            if (toc->iv_hash == hash)
+            {
+                break;
+            }
+        }
+
+        if (entries == 0)
+        {
+            rc = P9_XIP_ITEM_NOT_FOUND;
+            break;
+        }
+        else
+        {
+            rc = 0;
+        }
+
+        // The caller may have requested a lookup only (o_item == 0), in which
+        // case we're done.  Otherwise we create a partial P9XipItem and
+        // populate the non-0 fields analogously to the xipDecodeToc()
+        // routine. The data resides in the .fixed section in this case.
+
+        if (o_item == 0)
+        {
+            break;
+        }
+
+        o_item->iv_partial = 1;
+        o_item->iv_toc = 0;
+        o_item->iv_id = 0;
+
+        o_item->iv_type = toc->iv_type;
+        o_item->iv_elements = toc->iv_elements;
+
+        rc = p9_xip_get_section(i_image, P9_XIP_SECTION_FIXED, &fixedSection);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (fixedSection.iv_size == 0)
+        {
+            rc = TRACE_ERROR(P9_XIP_DATA_NOT_PRESENT);
+            break;
+        }
+
+        offset = fixedSection.iv_offset + htobe16(toc->iv_offset);
+
+        o_item->iv_imageData = (void*)((uint8_t*)i_image + offset);
+        o_item->iv_address = xipLinkAddress(i_image) + offset;
+
+    }
+    while (0);
+
+    return rc;
+}
+
+
+// Search for an item in the special built-in TOC of header fields, and
+// populate a partial TOC entry if requested.
+//
+// This facility was added to allow header data to be searched by name even
+// when the TOC has been stripped. This API will only be used in the case of a
+// stripped TOC since the header fields are also indexed in the main TOC.
+//
+// The table is allocated on the stack in order to make this code concurrently
+// patchable in PHYP (although PHYP applications will never use this code).
+// The table is small and unsorted so a linear search is adequate, and the
+// stack requirememts are small.
+
+XIP_STATIC int
+xipHeaderFind(void* i_image, const char* i_id, P9XipItem* o_item)
+{
+    int rc;
+    unsigned i;
+    uint32_t offset;
+    P9XipSection headerSection;
+
+#define HEADER_TOC(id, field, type)             \
+    {#id, offsetof(P9XipHeader, field), type}
+
+    struct HeaderToc
+    {
+
+        const char* iv_id;
+        uint16_t iv_offset;
+        uint8_t iv_type;
+
+    } toc[] =
+    {
+
+        HEADER_TOC(magic,        iv_magic,       P9_XIP_UINT64),
+        HEADER_TOC(link_address, iv_linkAddress, P9_XIP_UINT64),
+
+        HEADER_TOC(image_size, iv_imageSize, P9_XIP_UINT32),
+        HEADER_TOC(build_date, iv_buildDate, P9_XIP_UINT32),
+        HEADER_TOC(build_time, iv_buildTime, P9_XIP_UINT32),
+
+        HEADER_TOC(header_version, iv_headerVersion, P9_XIP_UINT8),
+        HEADER_TOC(toc_normalized, iv_normalized,    P9_XIP_UINT8),
+        HEADER_TOC(toc_sorted,     iv_tocSorted,     P9_XIP_UINT8),
+
+        HEADER_TOC(build_user, iv_buildUser, P9_XIP_STRING),
+        HEADER_TOC(build_host, iv_buildHost, P9_XIP_STRING),
+
+    };
+
+    do
+    {
+
+        rc = P9_XIP_ITEM_NOT_FOUND;
+
+        for (i = 0; i < (sizeof(toc) / sizeof(struct HeaderToc)); i++)
+        {
+            if (strcmp(i_id, toc[i].iv_id) == 0)
+            {
+                rc = 0;
+                break;
+            }
+        }
+
+        if (rc)
+        {
+            break;
+        }
+
+        // The caller may have requested a lookup only (o_item == 0), in which
+        // case we're done.  Otherwise we create a partial P9XipItem and
+        // populate the non-0 fields analogously to the xipDecodeToc()
+        // routine. The data resides in the .fixed section in this case.
+
+        if (o_item == 0)
+        {
+            break;
+        }
+
+        o_item->iv_partial = 1;
+        o_item->iv_toc = 0;
+        o_item->iv_id = 0;
+
+        o_item->iv_type = toc[i].iv_type;
+        o_item->iv_elements = 1; /* True for now... */
+
+        rc = p9_xip_get_section(i_image, P9_XIP_SECTION_HEADER,
+                                &headerSection);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (headerSection.iv_size == 0)
+        {
+            rc = TRACE_ERROR(P9_XIP_DATA_NOT_PRESENT);
+            break;
+        }
+
+        offset = headerSection.iv_offset + toc[i].iv_offset;
+
+        o_item->iv_imageData = (void*)((uint8_t*)i_image + offset);
+        o_item->iv_address = xipLinkAddress(i_image) + offset;
+
+    }
+    while (0);
+
+    return rc;
+}
+
+
+////////////////////////////////////////////////////////////////////////////
+// Published API
+////////////////////////////////////////////////////////////////////////////
+
+int
+p9_xip_validate(void* i_image, const uint32_t i_size)
+{
+    P9XipHeader hostHeader;
+    int rc = 0, i;
+    uint32_t linkAddress, imageSize, extent, offset, size;
+    uint8_t alignment;
+
+    p9_xip_translate_header(&hostHeader, (P9XipHeader*)i_image);
+
+    do
+    {
+
+        // Validate C/Assembler constraints.
+
+        if (sizeof(P9XipSection) != SIZE_OF_P9_XIP_SECTION)
+        {
+            rc = TRACE_ERRORX(P9_XIP_BUG,
+                              "C/Assembler size mismatch(%ld/%d) "
+                              "for P9XipSection\n",
+                              sizeof(P9XipSection), SIZE_OF_P9_XIP_SECTION);
+            break;
+        }
+
+        if (sizeof(P9XipToc) != SIZE_OF_P9_XIP_TOC)
+        {
+            rc = TRACE_ERRORX(P9_XIP_BUG,
+                              "C/Assembler size mismatch(%ld/%d) "
+                              "for P9XipToc\n",
+                              sizeof(P9XipToc), SIZE_OF_P9_XIP_TOC);
+            break;
+        }
+
+        if (sizeof(P9XipHashedToc) != SIZE_OF_P9_XIP_HASHED_TOC)
+        {
+            rc = TRACE_ERRORX(P9_XIP_BUG,
+                              "C/Assembler size mismatch(%ld/%d) "
+                              "for P9XipHashedToc\n",
+                              sizeof(P9XipHashedToc),
+                              SIZE_OF_P9_XIP_HASHED_TOC);
+            break;
+        }
+
+        // Validate the image pointer and magic number
+
+        rc = xipQuickCheck(i_image, 0);
+
+        if (rc)
+        {
+            break;
+        }
+
+        // Validate the image size
+
+        linkAddress = hostHeader.iv_linkAddress;
+        imageSize = hostHeader.iv_imageSize;
+        extent = linkAddress + imageSize;
+
+        if (imageSize < sizeof(P9XipHeader))
+        {
+            rc = TRACE_ERRORX(P9_XIP_IMAGE_ERROR,
+                              "p9_xip_validate(%p, %u) : "
+                              "The image size recorded in the image "
+                              "(%u) is smaller than the header size.\n",
+                              i_image, i_size, imageSize);
+            break;
+        }
+
+        if (imageSize != i_size)
+        {
+            rc = TRACE_ERRORX(P9_XIP_IMAGE_ERROR,
+                              "p9_xip_validate(%p, %u) : "
+                              "The image size recorded in the image "
+                              "(%u) does not match the i_size parameter.\n",
+                              i_image, i_size, imageSize);
+            break;
+        }
+
+        if (extent <= linkAddress)
+        {
+            rc = TRACE_ERRORX(P9_XIP_IMAGE_ERROR,
+                              "p9_xip_validate(%p, %u) : "
+                              "Given the link address (%u) and the "
+                              "image size, the image wraps the address space\n",
+                              i_image, i_size, linkAddress);
+            break;
+        }
+
+        if ((imageSize % P9_XIP_FINAL_ALIGNMENT) != 0)
+        {
+            rc = TRACE_ERRORX(P9_XIP_ALIGNMENT_ERROR,
+                              "p9_xip_validate(%p, %u) : "
+                              "The image size (%u) is not a multiple of %u\n",
+                              i_image, i_size, imageSize,
+                              P9_XIP_FINAL_ALIGNMENT);
+            break;
+        }
+
+        // Validate that all sections appear to be within the image
+        // bounds, and are aligned correctly.
+
+        for (i = 0; i < P9_XIP_SECTIONS; i++)
+        {
+
+            offset = hostHeader.iv_section[i].iv_offset;
+            size = hostHeader.iv_section[i].iv_size;
+            alignment = hostHeader.iv_section[i].iv_alignment;
+
+            if ((offset > imageSize) ||
+                ((offset + size) > imageSize) ||
+                ((offset + size) < offset))
+            {
+                rc = TRACE_ERRORX(P9_XIP_IMAGE_ERROR,
+                                  "Section %d does not appear to be within "
+                                  "the bounds of the image\n"
+                                  "offset = %u, size = %u, image size = %u\n",
+                                  i, offset, size, imageSize);
+                break;
+            }
+
+            if ((offset % alignment) != 0)
+            {
+                rc = TRACE_ERRORX(P9_XIP_ALIGNMENT_ERROR,
+                                  "Section %d requires %d-byte initial "
+                                  "alignment but the section offset is %u\n",
+                                  i, alignment, offset);
+                break;
+            }
+        }
+
+        if (rc)
+        {
+            break;
+        }
+
+        // If the TOC exists and the image is normalized, validate each TOC
+        // entry.
+
+        size = hostHeader.iv_section[P9_XIP_SECTION_TOC].iv_size;
+
+        if (size != 0)
+        {
+            if (xipNormalized(i_image))
+            {
+                rc = p9_xip_map_toc(i_image, xipValidateTocEntry, 0);
+
+                if (rc)
+                {
+                    break;
+                }
+            }
+        }
+    }
+    while (0);
+
+    return rc;
+}
+
+
+int
+p9_xip_validate2(void* i_image, const uint32_t i_size, const uint32_t i_maskIgnores)
+{
+    P9XipHeader hostHeader;
+    int rc = 0, i;
+    uint32_t linkAddress, imageSize, extent, offset, size;
+    uint8_t alignment;
+
+    p9_xip_translate_header(&hostHeader, (P9XipHeader*)i_image);
+
+    do
+    {
+
+        // Validate C/Assembler constraints.
+
+        if (sizeof(P9XipSection) != SIZE_OF_P9_XIP_SECTION)
+        {
+            rc = TRACE_ERRORX(P9_XIP_BUG,
+                              "C/Assembler size mismatch(%ld/%d) "
+                              "for P9XipSection\n",
+                              sizeof(P9XipSection), SIZE_OF_P9_XIP_SECTION);
+            break;
+        }
+
+        if (sizeof(P9XipToc) != SIZE_OF_P9_XIP_TOC)
+        {
+            rc = TRACE_ERRORX(P9_XIP_BUG,
+                              "C/Assembler size mismatch(%ld/%d) "
+                              "for P9XipToc\n",
+                              sizeof(P9XipToc), SIZE_OF_P9_XIP_TOC);
+            break;
+        }
+
+        if (sizeof(P9XipHashedToc) != SIZE_OF_P9_XIP_HASHED_TOC)
+        {
+            rc = TRACE_ERRORX(P9_XIP_BUG,
+                              "C/Assembler size mismatch(%ld/%d) "
+                              "for P9XipHashedToc\n",
+                              sizeof(P9XipHashedToc),
+                              SIZE_OF_P9_XIP_HASHED_TOC);
+            break;
+        }
+
+        // Validate the image pointer and magic number
+
+        rc = xipQuickCheck(i_image, 0);
+
+        if (rc)
+        {
+            break;
+        }
+
+        // Validate the image size
+
+        linkAddress = hostHeader.iv_linkAddress;
+        imageSize = hostHeader.iv_imageSize;
+        extent = linkAddress + imageSize;
+
+        if (imageSize < sizeof(P9XipHeader))
+        {
+            rc = TRACE_ERRORX(P9_XIP_IMAGE_ERROR,
+                              "p9_xip_validate2(%p, %u) : "
+                              "The image size recorded in the image "
+                              "(%u) is smaller than the header size.\n",
+                              i_image, i_size, imageSize);
+            break;
+        }
+
+        if (imageSize != i_size && !(i_maskIgnores & P9_XIP_IGNORE_FILE_SIZE))
+        {
+            rc = TRACE_ERRORX(P9_XIP_IMAGE_ERROR,
+                              "p9_xip_validate2(%p, %u) : "
+                              "The image size recorded in the image "
+                              "(%u) does not match the i_size parameter.\n",
+                              i_image, i_size, imageSize);
+            break;
+        }
+
+        if (extent <= linkAddress)
+        {
+            rc = TRACE_ERRORX(P9_XIP_IMAGE_ERROR,
+                              "p9_xip_validate2(%p, %u) : "
+                              "Given the link address (%u) and the "
+                              "image size, the image wraps the address space\n",
+                              i_image, i_size, linkAddress);
+            break;
+        }
+
+        if ((imageSize % P9_XIP_FINAL_ALIGNMENT) != 0)
+        {
+            rc = TRACE_ERRORX(P9_XIP_ALIGNMENT_ERROR,
+                              "p9_xip_validate2(%p, %u) : "
+                              "The image size (%u) is not a multiple of %u\n",
+                              i_image, i_size, imageSize,
+                              P9_XIP_FINAL_ALIGNMENT);
+            break;
+        }
+
+        // Validate that all sections appear to be within the image
+        // bounds, and are aligned correctly.
+
+        for (i = 0; i < P9_XIP_SECTIONS; i++)
+        {
+
+            offset = hostHeader.iv_section[i].iv_offset;
+            size = hostHeader.iv_section[i].iv_size;
+            alignment = hostHeader.iv_section[i].iv_alignment;
+
+            if ((offset > imageSize) ||
+                ((offset + size) > imageSize) ||
+                ((offset + size) < offset))
+            {
+                rc = TRACE_ERRORX(P9_XIP_IMAGE_ERROR,
+                                  "Section %d does not appear to be within "
+                                  "the bounds of the image\n"
+                                  "offset = %u, size = %u, image size = %u\n",
+                                  i, offset, size, imageSize);
+                break;
+            }
+
+            if ((offset % alignment) != 0)
+            {
+                rc = TRACE_ERRORX(P9_XIP_ALIGNMENT_ERROR,
+                                  "Section %d requires %d-byte initial "
+                                  "alignment but the section offset is %u\n",
+                                  i, alignment, offset);
+                break;
+            }
+        }
+
+        if (rc)
+        {
+            break;
+        }
+
+        // If the TOC exists and the image is normalized, validate each TOC
+        // entry.
+
+        size = hostHeader.iv_section[P9_XIP_SECTION_TOC].iv_size;
+
+        if (size != 0)
+        {
+            if (xipNormalized(i_image))
+            {
+                rc = p9_xip_map_toc(i_image, xipValidateTocEntry, 0);
+
+                if (rc)
+                {
+                    break;
+                }
+            }
+        }
+    }
+    while (0);
+
+    return rc;
+}
+
+
+// Normalization:
+//
+// 1. Normalize the TOC, unless the image is already normalized.  The image
+// must be marked as normalized before sorting.
+//
+// 2. Sort the TOC.
+//
+// 3. Clear the section offsets of any empty sections to make the section
+// table reports less confusing.
+//
+// 4. Clear normalization status on any failure.
+
+int
+p9_xip_normalize(void* io_image)
+{
+    int rc, i;
+    P9XipSection section;
+    P9XipToc* imageToc;
+    P9XipHashedToc* fixedImageToc;
+    P9XipHashedToc* fixedTocEntry;
+    size_t tocEntries, fixedTocEntries, fixedEntriesRemaining;
+
+    do
+    {
+        rc = xipQuickCheck(io_image, 0);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (!xipNormalized(io_image))
+        {
+
+            rc = p9_xip_get_toc(io_image, &imageToc, &tocEntries, 0, 0);
+
+            if (rc)
+            {
+                break;
+            }
+
+            rc = xipGetFixedToc(io_image, &fixedImageToc, &fixedTocEntries);
+
+            if (rc)
+            {
+                break;
+            }
+
+            fixedTocEntry = fixedImageToc;
+            fixedEntriesRemaining = fixedTocEntries;
+
+            for (; tocEntries--; imageToc++)
+            {
+                rc = xipNormalizeToc(io_image, imageToc,
+                                     &fixedTocEntry, &fixedEntriesRemaining);
+
+                if (rc)
+                {
+                    break;
+                }
+
+            }
+
+            if (rc)
+            {
+                break;
+            }
+
+            if (fixedEntriesRemaining != 0)
+            {
+                rc = TRACE_ERRORX(P9_XIP_TOC_ERROR,
+                                  "Not enough TOC entries for .fixed");
+                break;
+            }
+
+            rc = xipHashCollision(fixedImageToc, fixedTocEntries);
+
+            if (rc)
+            {
+                break;
+            }
+
+            ((P9XipHeader*)io_image)->iv_normalized = 1;
+        }
+
+        rc = xipSortToc(io_image);
+
+        if (rc)
+        {
+            break;
+        }
+
+        for (i = 0; i < P9_XIP_SECTIONS; i++)
+        {
+            rc = p9_xip_get_section(io_image, i, &section);
+
+            if (rc)
+            {
+                break;
+            }
+
+            if (section.iv_size == 0)
+            {
+                xipSetSectionOffset(io_image, i, 0);
+            }
+        }
+
+        if (rc)
+        {
+            break;
+        }
+
+    }
+    while(0);
+
+    ((P9XipHeader*)io_image)->iv_normalized = (rc == 0);
+
+    return rc;
+}
+
+
+int
+p9_xip_image_size(void* io_image, uint32_t* o_size)
+{
+    int rc;
+
+    rc = xipQuickCheck(io_image, 0);
+
+    if (!rc)
+    {
+        *o_size = xipImageSize(io_image);
+    }
+
+    return rc;
+}
+
+
+int
+p9_xip_get_section(const void* i_image,
+                   const int i_sectionId,
+                   P9XipSection* o_hostSection)
+{
+    int rc;
+    P9XipSection* imageSection;
+
+    rc = xipGetSectionPointer(i_image, i_sectionId, &imageSection);
+
+    if (!rc)
+    {
+        xipTranslateSection(o_hostSection, imageSection);
+    }
+
+    return rc;
+}
+
+
+// If the 'big' TOC is not present, search the mini-TOCs that only index the
+// .fixed and .header sections.
+
+int
+p9_xip_find(void* i_image,
+            const char* i_id,
+            P9XipItem* o_item)
+{
+    int rc;
+    P9XipToc* toc;
+    P9XipItem item, *pitem;
+    P9XipSection* tocSection;
+
+    do
+    {
+        rc = xipQuickCheck(i_image, 1);
+
+        if (rc)
+        {
+            break;
+        }
+
+        rc = xipGetSectionPointer(i_image, P9_XIP_SECTION_TOC, &tocSection);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (tocSection->iv_size == 0)
+        {
+            rc = xipFixedFind(i_image, i_id, o_item);
+
+            if (rc)
+            {
+                rc = xipHeaderFind(i_image, i_id, o_item);
+            }
+
+            break;
+        }
+
+        if (xipSorted(i_image))
+        {
+            rc = xipBinarySearch(i_image, i_id, &toc);
+        }
+        else
+        {
+            rc = xipLinearSearch(i_image, i_id, &toc);
+        }
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (o_item)
+        {
+            pitem = o_item;
+        }
+        else
+        {
+            pitem = &item;
+        }
+
+        rc = xipDecodeToc(i_image, toc, pitem);
+
+        if (rc)
+        {
+            break;
+        }
+
+    }
+    while (0);
+
+    return rc;
+}
+
+int
+p9_xip_get_item(const P9XipItem* i_item, uint64_t* o_data)
+{
+    switch (i_item->iv_type)
+    {
+        case P9_XIP_UINT8:
+            *o_data = *((uint8_t*)(i_item->iv_imageData));
+            break;
+
+        case P9_XIP_UINT16:
+            *o_data = htobe16(*((uint16_t*)(i_item->iv_imageData)));
+            break;
+
+        case P9_XIP_UINT32:
+            *o_data = htobe32(*((uint32_t*)(i_item->iv_imageData)));
+            break;
+
+        case P9_XIP_UINT64:
+            *o_data = htobe64(*((uint64_t*)(i_item->iv_imageData)));
+            break;
+
+        case P9_XIP_INT8:
+            *o_data = *((int8_t*)(i_item->iv_imageData));
+            break;
+
+        case P9_XIP_INT16:
+            *o_data = htobe16(*((int16_t*)(i_item->iv_imageData)));
+            break;
+
+        case P9_XIP_INT32:
+            *o_data = htobe32(*((int32_t*)(i_item->iv_imageData)));
+            break;
+
+        case P9_XIP_INT64:
+            *o_data = htobe64(*((int64_t*)(i_item->iv_imageData)));
+            break;
+
+        case P9_XIP_ADDRESS:
+            *o_data = i_item->iv_address;
+            break;
+
+        case P9_XIP_STRING:
+            //Nothing to do in case of string, but making sure rc is valid
+            break;
+
+        default:
+            return TRACE_ERROR(P9_XIP_TYPE_ERROR);
+            break;
+    }
+
+    return 0;
+}
+
+int
+p9_xip_get_scalar(void* i_image, const char* i_id, uint64_t* o_data)
+{
+    int rc;
+    P9XipItem item;
+
+    rc = p9_xip_find(i_image, i_id, &item);
+
+    if (!rc)
+    {
+        rc = p9_xip_get_item(&item, o_data);
+    }
+
+    return rc;
+}
+
+int
+p9_xip_get_element(void* i_image,
+                   const char* i_id,
+                   const uint32_t i_index,
+                   uint64_t* o_data)
+{
+    int rc;
+    P9XipItem item;
+
+    do
+    {
+        rc = p9_xip_find(i_image, i_id, &item);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if ((item.iv_elements != 0) && (i_index >= item.iv_elements))
+        {
+            rc = TRACE_ERROR(P9_XIP_BOUNDS_ERROR);
+            break;
+        }
+
+        switch (item.iv_type)
+        {
+            case P9_XIP_UINT8:
+                *o_data = ((uint8_t*)(item.iv_imageData))[i_index];
+                break;
+
+            case P9_XIP_UINT16:
+                *o_data = htobe16(((uint16_t*)(item.iv_imageData))[i_index]);
+                break;
+
+            case P9_XIP_UINT32:
+                *o_data = htobe32(((uint32_t*)(item.iv_imageData))[i_index]);
+                break;
+
+            case P9_XIP_UINT64:
+                *o_data = htobe64(((uint64_t*)(item.iv_imageData))[i_index]);
+                break;
+
+            case P9_XIP_INT8:
+                *o_data = ((int8_t*)(item.iv_imageData))[i_index];
+                break;
+
+            case P9_XIP_INT16:
+                *o_data = htobe16(((int16_t*)(item.iv_imageData))[i_index]);
+                break;
+
+            case P9_XIP_INT32:
+                *o_data = htobe32(((int32_t*)(item.iv_imageData))[i_index]);
+                break;
+
+            case P9_XIP_INT64:
+                *o_data = htobe64(((int64_t*)(item.iv_imageData))[i_index]);
+                break;
+
+            default:
+                rc = TRACE_ERROR(P9_XIP_TYPE_ERROR);
+                break;
+        }
+
+        if (rc)
+        {
+            break;
+        }
+
+    }
+    while (0);
+
+    return rc;
+}
+
+
+int
+p9_xip_get_string(void* i_image, const char* i_id, char** o_data)
+{
+    int rc;
+    P9XipItem item;
+
+    rc = p9_xip_find(i_image, i_id, &item);
+
+    if (!rc)
+    {
+        switch (item.iv_type)
+        {
+            case P9_XIP_STRING:
+                *o_data = (char*)(item.iv_imageData);
+                break;
+
+            default:
+                rc = TRACE_ERROR(P9_XIP_TYPE_ERROR);
+                break;
+        }
+    }
+
+    return rc;
+}
+
+
+int
+p9_xip_read_uint64(const void* i_image,
+                   const uint64_t i_imageAddress,
+                   uint64_t* o_data)
+{
+    int rc;
+
+    do
+    {
+        rc = xipQuickCheck(i_image, 0);
+
+        if (rc)
+        {
+            break;
+        }
+
+        rc = xipValidateImageAddress(i_image, i_imageAddress, 8);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (i_imageAddress % 8)
+        {
+            rc = TRACE_ERROR(P9_XIP_ALIGNMENT_ERROR);
+            break;
+        }
+
+        *o_data =
+            htobe64(*((uint64_t*)xipImage2Host(i_image, i_imageAddress)));
+
+    }
+    while(0);
+
+    return rc;
+}
+
+
+int
+p9_xip_set_scalar(void* io_image, const char* i_id, const uint64_t i_data)
+{
+    int rc;
+    P9XipItem item;
+
+    rc = p9_xip_find(io_image, i_id, &item);
+
+    if (!rc)
+    {
+        switch(item.iv_type)
+        {
+            case P9_XIP_UINT8:
+                *((uint8_t*)(item.iv_imageData)) = (uint8_t)i_data;
+                break;
+
+            case P9_XIP_UINT16:
+                *((uint16_t*)(item.iv_imageData)) = htobe16((uint16_t)i_data);
+                break;
+
+            case P9_XIP_UINT32:
+                *((uint32_t*)(item.iv_imageData)) = htobe32((uint32_t)i_data);
+                break;
+
+            case P9_XIP_UINT64:
+                *((uint64_t*)(item.iv_imageData)) = htobe64((uint64_t)i_data);
+                break;
+
+            case P9_XIP_INT8:
+                *((int8_t*)(item.iv_imageData)) = (int8_t)i_data;
+                break;
+
+            case P9_XIP_INT16:
+                *((int16_t*)(item.iv_imageData)) = htobe16((int16_t)i_data);
+                break;
+
+            case P9_XIP_INT32:
+                *((int32_t*)(item.iv_imageData)) = htobe32((int32_t)i_data);
+                break;
+
+            case P9_XIP_INT64:
+                *((int64_t*)(item.iv_imageData)) = htobe64((int64_t)i_data);
+                break;
+
+            default:
+                rc = TRACE_ERROR(P9_XIP_TYPE_ERROR);
+                break;
+        }
+    }
+
+    return rc;
+}
+
+
+int
+p9_xip_set_element(void* i_image,
+                   const char* i_id,
+                   const uint32_t i_index,
+                   const uint64_t i_data)
+{
+    int rc;
+    P9XipItem item;
+
+    do
+    {
+        rc = p9_xip_find(i_image, i_id, &item);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if ((item.iv_elements != 0) && (i_index >= item.iv_elements))
+        {
+            rc = TRACE_ERROR(P9_XIP_BOUNDS_ERROR);
+            break;
+        }
+
+        switch (item.iv_type)
+        {
+            case P9_XIP_UINT8:
+                ((uint8_t*)(item.iv_imageData))[i_index] = (uint8_t)i_data;
+                break;
+
+            case P9_XIP_UINT16:
+                ((uint16_t*)(item.iv_imageData))[i_index] =
+                    htobe16((uint16_t)i_data);
+                break;
+
+            case P9_XIP_UINT32:
+                ((uint32_t*)(item.iv_imageData))[i_index] =
+                    htobe32((uint32_t)i_data);
+                break;
+
+            case P9_XIP_UINT64:
+                ((uint64_t*)(item.iv_imageData))[i_index] =
+                    htobe64((uint64_t)i_data);
+                break;
+
+            case P9_XIP_INT8:
+                ((int8_t*)(item.iv_imageData))[i_index] = (int8_t)i_data;
+                break;
+
+            case P9_XIP_INT16:
+                ((int16_t*)(item.iv_imageData))[i_index] =
+                    htobe16((uint16_t)i_data);
+                break;
+
+            case P9_XIP_INT32:
+                ((int32_t*)(item.iv_imageData))[i_index] =
+                    htobe32((uint32_t)i_data);
+                break;
+
+            case P9_XIP_INT64:
+                ((int64_t*)(item.iv_imageData))[i_index] =
+                    htobe64((uint64_t)i_data);
+                break;
+
+            default:
+                rc = TRACE_ERROR(P9_XIP_TYPE_ERROR);
+                break;
+        }
+
+        if (rc)
+        {
+            break;
+        }
+
+    }
+    while (0);
+
+    return rc;
+}
+
+
+int
+p9_xip_set_string(void* i_image, const char* i_id, const char* i_data)
+{
+    int rc;
+    P9XipItem item;
+    char* dest;
+
+    rc = p9_xip_find(i_image, i_id, &item);
+
+    if (!rc)
+    {
+        switch (item.iv_type)
+        {
+            case P9_XIP_STRING:
+                dest = (char*)(item.iv_imageData);
+
+                if (strlen(dest) < strlen(i_data))
+                {
+                    memcpy(dest, i_data, strlen(dest));
+                }
+                else
+                {
+                    strcpy(dest, i_data);
+                }
+
+                break;
+
+            default:
+                rc = TRACE_ERROR(P9_XIP_TYPE_ERROR);
+                break;
+        }
+    }
+
+    return rc;
+}
+
+
+int
+p9_xip_write_uint64(void* io_image,
+                    const uint64_t i_imageAddress,
+                    const uint64_t i_data)
+{
+    int rc;
+
+    do
+    {
+        rc = xipQuickCheck(io_image, 0);
+
+        if (rc)
+        {
+            break;
+        }
+
+        rc = xipValidateImageAddress(io_image, i_imageAddress, 8);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (i_imageAddress % 8)
+        {
+            rc = TRACE_ERROR(P9_XIP_ALIGNMENT_ERROR);
+            break;
+        }
+
+        *((uint64_t*)xipImage2Host(io_image, i_imageAddress)) =
+            htobe64(i_data);
+
+    }
+    while(0);
+
+    return rc;
+}
+
+
+int
+p9_xip_delete_section(void* io_image,
+                      void* o_imageBuf,
+                      const uint32_t i_imageBufSize,
+                      const int i_sectionId)
+{
+    int rc, final;
+    P9XipSection section;
+    size_t imageSize;
+    uint8_t bImageChanged = 0; // Tracks if io_image has been modified.
+
+    do
+    {
+
+        // Get image size. We'll need it a lot.
+
+        imageSize = xipImageSize(io_image);
+
+        // Parm check 1: imageBufSize
+        // - Must be >=imageSize for a valid imageBuf buffer
+
+        if (i_imageBufSize < imageSize && o_imageBuf != NULL)
+        {
+            rc = TRACE_ERRORX(P9_XIP_WOULD_OVERFLOW,
+                              "xip_delete_section(): imageBufSize too small");
+            break;
+        }
+
+        // Parm check 2: sectionId
+        // - It is illegal to remove the .header. It would kill the image.
+
+        if (i_sectionId == P9_XIP_SECTION_HEADER)
+        {
+            rc = TRACE_ERRORX(P9_XIP_SECTION_ERROR,
+                              "xip_delete_section(): It is illegal to remove .header");
+            break;
+        }
+
+        // Copy io_image to o_imageBuf if a valid imageBuf ptr is
+        //   supplied, i.e., imageBuf!=NULL.  We'll need a reference copy
+        //   of any delected section to be re-appended after the section
+        //   delete process is done.
+        if (o_imageBuf != NULL)
+        {
+            // We always return a copy of the original input image.
+            memcpy(o_imageBuf, io_image, imageSize);
+        }
+
+        // Check the image
+
+        rc = xipQuickCheck(io_image, 1);
+
+        if (rc)
+        {
+            break;
+        }
+
+        // Deleting an empty section is a NOP.  Otherwise the section must be
+        // the final section of the image. Update the sizes and re-establish
+        // the final image alignment.
+
+        rc = p9_xip_get_section(io_image, i_sectionId, &section);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (section.iv_size == 0)
+        {
+            break;
+        }
+
+        // Determine last image section.
+
+        rc = xipFinalSection(io_image, &final);
+
+        if (rc)
+        {
+            break;
+        }
+
+        // Now, delete necessary sections in order of highest section offset
+        //   to the offset of the section, i_sectionId, to be removed.
+
+        if (final == i_sectionId)
+        {
+            rc = xipDeleteLastSection(io_image, i_sectionId);
+
+            bImageChanged = 1;
+
+            break;
+        }
+        else
+        {
+            // Check for imageBuf ptr violation. If this fails, this is
+            //   catastrophic since we don't have a reference copy of the input
+            //   image (i.e, the memcpy of the image earlier wasn't executed.)
+
+            if (o_imageBuf == NULL)
+            {
+                rc = TRACE_ERRORX(P9_XIP_NULL_BUFFER,
+                                  "xip_delete_section(): Can't copy image into NULL buffer\n");
+                break;
+            }
+
+            // Delete sections, in order, that have offset addresses higher
+            //   than i_sectionId and make a note of the order which is to
+            //   be used when re-appending.  Then delete i_sectionId.
+
+            uint8_t sectionOrder[P9_XIP_SECTIONS];
+            uint8_t orderIdx = 0;
+
+            do
+            {
+
+                rc = xipFinalSection(io_image, &final);
+
+                if (rc)
+                {
+                    break;
+                }
+
+                // It is illegal to remove .header. It would kill the image.
+                if (final == P9_XIP_SECTION_HEADER)
+                {
+                    rc = TRACE_ERRORX(P9_XIP_SECTION_ERROR,
+                                      "xip_delete_section(): Code bug: Attempt to remove .header");
+                    break;
+                }
+
+                if (final != i_sectionId)
+                {
+                    sectionOrder[orderIdx] = final;
+                    orderIdx++;
+                }
+
+                rc = xipDeleteLastSection(io_image, final);
+
+                bImageChanged = 1;
+
+                if (rc)
+                {
+                    break;
+                }
+
+            }
+            while (final != i_sectionId);
+
+            if (rc)
+            {
+                break;
+            }
+
+            // Reappend previously deleted sections in original order
+
+            do
+            {
+
+                orderIdx--;
+                rc = p9_xip_get_section(o_imageBuf, sectionOrder[orderIdx], &section);
+
+                if (rc)
+                {
+                    break;
+                }
+
+                rc = p9_xip_append( io_image,
+                                    sectionOrder[orderIdx],
+                                    (void*)(((uint8_t*)o_imageBuf) + section.iv_offset),
+                                    (const uint32_t)section.iv_size,
+                                    (const uint32_t)imageSize,
+                                    NULL );
+
+                if (rc)
+                {
+                    break;
+                }
+
+            }
+            while (orderIdx);
+
+            break;
+        }
+
+    }
+    while (0);
+
+    // Restore broken input image in case of rc!=0. But only do so if input
+    //   image has changed.
+
+    if (rc && bImageChanged)
+    {
+        memcpy(io_image, o_imageBuf, imageSize);
+    }
+
+    return rc;
+}
+
+
+#ifndef PPC_HYP
+
+// This API is not needed by PHYP procedures, and is elided since PHYP does
+// not support malloc().
+
+int
+p9_xip_duplicate_section(const void* i_image,
+                         const int i_sectionId,
+                         void** o_duplicate,
+                         uint32_t* o_size)
+{
+    P9XipSection section;
+    int rc;
+
+    *o_duplicate = 0;
+
+    do
+    {
+        rc = xipQuickCheck(i_image, 0);
+
+        if (rc)
+        {
+            break;
+        }
+
+        rc = p9_xip_get_section(i_image, i_sectionId, &section);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (section.iv_size == 0)
+        {
+            rc = TRACE_ERRORX(P9_XIP_SECTION_ERROR,
+                              "Attempt to duplicate empty section %d\n",
+                              i_sectionId);
+            break;
+        }
+
+        *o_duplicate = malloc(section.iv_size);
+        *o_size = section.iv_size;
+
+        if (*o_duplicate == 0)
+        {
+            rc = TRACE_ERROR(P9_XIP_NO_MEMORY);
+            break;
+        }
+
+        memcpy(*o_duplicate,
+               xipHostAddressFromOffset(i_image, section.iv_offset),
+               section.iv_size);
+
+
+    }
+    while (0);
+
+    if (rc)
+    {
+        free(*o_duplicate);
+        *o_duplicate = 0;
+        *o_size = 0;
+    }
+
+    return rc;
+}
+
+#endif // PPC_HYP
+
+
+// The append must be done in such a way that if the append fails, the image
+// is not modified. This behavior is required by applications that
+// speculatively append until the allocation fails, but still require the
+// final image to be valid. To accomplish this the initial image size and
+// section statistics are captured at entry, and restored in the event of an
+// error.
+
+int
+p9_xip_append(void* io_image,
+              const int i_sectionId,
+              const void* i_data,
+              const uint32_t i_size,
+              const uint32_t i_allocation,
+              uint32_t* o_sectionOffset)
+{
+    P9XipSection section, initialSection;
+    int rc, final, restoreOnError;
+    void* hostAddress;
+    uint32_t pad, initialSize;
+
+    do
+    {
+        restoreOnError = 0;
+
+        rc = xipQuickCheck(io_image, 1);
+
+        if (rc)
+        {
+            break;
+        }
+
+        rc = p9_xip_get_section(io_image, i_sectionId, &section);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (i_size == 0)
+        {
+            break;
+        }
+
+        initialSection = section;
+        initialSize = xipImageSize(io_image);
+        restoreOnError = 1;
+
+        if (section.iv_size == 0)
+        {
+
+            // The section is empty, and now becomes the final section. Pad
+            // the image to the specified section alignment.  Note that the
+            // size of the previously final section does not change.
+
+            rc = xipPadImage(io_image, i_allocation, section.iv_alignment,
+                             &pad);
+
+            if (rc)
+            {
+                break;
+            }
+
+            section.iv_offset = xipImageSize(io_image);
+
+        }
+        else
+        {
+
+            // Otherwise, the section must be the final section in order to
+            // continue. Remove any padding from the image.
+
+            rc = xipFinalSection(io_image, &final);
+
+            if (rc)
+            {
+                break;
+            }
+
+            if (final != i_sectionId)
+            {
+                rc = TRACE_ERRORX(P9_XIP_SECTION_ERROR,
+                                  "Attempt to append to non-final section "
+                                  "%d\n", i_sectionId);
+                break;
+            }
+
+            xipSetImageSize(io_image, section.iv_offset + section.iv_size);
+        }
+
+
+        // Make sure the allocated space won't overflow. Set the return
+        // parameter o_sectionOffset and copy the new data into the image (or
+        // simply clear the space).
+
+        if ((xipImageSize(io_image) + i_size) > i_allocation)
+        {
+            rc = TRACE_ERROR(P9_XIP_WOULD_OVERFLOW);
+            break;
+        }
+
+        if (o_sectionOffset != 0)
+        {
+            *o_sectionOffset = section.iv_size;
+        }
+
+        hostAddress =
+            xipHostAddressFromOffset(io_image, xipImageSize(io_image));
+
+        if (i_data == 0)
+        {
+            memset(hostAddress, 0, i_size);
+        }
+        else
+        {
+            memcpy(hostAddress, i_data, i_size);
+        }
+
+
+        // Update the image size and section table. Note that the final
+        // alignment may push out of the allocation.
+
+        xipSetImageSize(io_image, xipImageSize(io_image) + i_size);
+        xipFinalAlignment(io_image);
+
+        if (xipImageSize(io_image) > i_allocation)
+        {
+            rc = TRACE_ERROR(P9_XIP_WOULD_OVERFLOW);
+            break;
+        }
+
+        section.iv_size += i_size;
+
+        if (xipPutSection(io_image, i_sectionId, &section) != 0)
+        {
+            rc = TRACE_ERROR(P9_XIP_BUG); /* Can't happen */
+            break;
+        }
+
+
+        // Special case
+
+        if (i_sectionId == P9_XIP_SECTION_TOC)
+        {
+            ((P9XipHeader*)io_image)->iv_tocSorted = 0;
+        }
+
+    }
+    while (0);
+
+    if (rc && restoreOnError)
+    {
+        if (xipPutSection(io_image, i_sectionId, &initialSection) != 0)
+        {
+            rc = TRACE_ERROR(P9_XIP_BUG); /* Can't happen */
+        }
+
+        xipSetImageSize(io_image, initialSize);
+    }
+
+    return rc;
+}
+
+
+int
+p9_xip_section2image(const void* i_image,
+                     const int i_sectionId,
+                     const uint32_t i_offset,
+                     uint64_t* o_imageAddress)
+{
+    int rc;
+    P9XipSection section;
+
+    do
+    {
+        rc = xipQuickCheck(i_image, 0);
+
+        if (rc)
+        {
+            break;
+        }
+
+        rc = p9_xip_get_section(i_image, i_sectionId, &section);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (section.iv_size == 0)
+        {
+            rc = TRACE_ERROR(P9_XIP_SECTION_ERROR);
+            break;
+        }
+
+        if (i_offset > (section.iv_offset + section.iv_size))
+        {
+            rc = TRACE_ERROR(P9_XIP_INVALID_ARGUMENT);
+            break;
+        }
+
+        *o_imageAddress = xipLinkAddress(i_image) + section.iv_offset + i_offset;
+
+        if (*o_imageAddress % 4)
+        {
+            rc = TRACE_ERROR(P9_XIP_ALIGNMENT_ERROR);
+            break;
+        }
+
+    }
+    while(0);
+
+    return rc;
+}
+
+
+int
+p9_xip_image2section(const void* i_image,
+                     const uint64_t i_imageAddress,
+                     int* i_section,
+                     uint32_t* i_offset)
+{
+    int rc;
+
+    do
+    {
+        rc = xipQuickCheck(i_image, 0);
+
+        if (rc)
+        {
+            break;
+        }
+
+        rc = xipImage2Section(i_image, i_imageAddress, i_section, i_offset);
+
+    }
+    while(0);
+
+    return rc;
+}
+
+
+int
+p9_xip_image2host(const void* i_image,
+                  const uint64_t i_imageAddress,
+                  void** o_hostAddress)
+{
+    int rc;
+
+    do
+    {
+        rc = xipQuickCheck(i_image, 0);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if ((i_imageAddress < xipLinkAddress(i_image)) ||
+            (i_imageAddress >
+             (xipLinkAddress(i_image) + xipImageSize(i_image))))
+        {
+            rc = TRACE_ERROR(P9_XIP_INVALID_ARGUMENT);
+            break;
+        }
+
+        *o_hostAddress =
+            xipHostAddressFromOffset(i_image,
+                                     i_imageAddress - xipLinkAddress(i_image));
+    }
+    while(0);
+
+    return rc;
+}
+
+
+int
+p9_xip_host2image(const void* i_image,
+                  void* i_hostAddress,
+                  uint64_t* o_imageAddress)
+{
+    int rc;
+
+    do
+    {
+        rc = xipQuickCheck(i_image, 0);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if ((i_hostAddress < i_image) ||
+            (i_hostAddress >
+             xipHostAddressFromOffset(i_image, xipImageSize(i_image))))
+        {
+            rc = TRACE_ERROR(P9_XIP_INVALID_ARGUMENT);
+            break;
+        }
+
+        *o_imageAddress = xipLinkAddress(i_image) +
+                          ((unsigned long)i_hostAddress - (unsigned long)i_image);
+
+        if (*o_imageAddress % 4)
+        {
+            rc = TRACE_ERROR(P9_XIP_ALIGNMENT_ERROR);
+            break;
+        }
+    }
+    while(0);
+
+    return rc;
+}
+
+
+void
+p9_xip_translate_header(P9XipHeader* o_dest, const P9XipHeader* i_src)
+{
+#ifndef _BIG_ENDIAN
+    int i;
+    P9XipSection* destSection;
+    const P9XipSection* srcSection;
+
+#if P9_XIP_HEADER_VERSION != 9
+#error This code assumes the P9-XIP header version 9 layout
+#endif
+
+    o_dest->iv_magic = htobe64(i_src->iv_magic);
+    o_dest->iv_L1LoaderAddr = htobe64(i_src->iv_L1LoaderAddr);
+    o_dest->iv_L2LoaderAddr = htobe64(i_src->iv_L2LoaderAddr);
+    o_dest->iv_kernelAddr   = htobe64(i_src->iv_kernelAddr);
+    o_dest->iv_linkAddress = htobe64(i_src->iv_linkAddress);
+
+    for (i = 0; i < 3; i++)
+    {
+        o_dest->iv_reserved64[i] = 0;
+    }
+
+    for (i = 0, destSection = o_dest->iv_section,
+         srcSection = i_src->iv_section;
+         i < P9_XIP_SECTIONS;
+         i++, destSection++, srcSection++)
+    {
+        xipTranslateSection(destSection, srcSection);
+    }
+
+    o_dest->iv_imageSize = htobe32(i_src->iv_imageSize);
+    o_dest->iv_buildDate = htobe32(i_src->iv_buildDate);
+    o_dest->iv_buildTime = htobe32(i_src->iv_buildTime);
+
+    for (i = 0; i < 5; i++)
+    {
+        o_dest->iv_reserved32[i] = 0;
+    }
+
+    o_dest->iv_headerVersion = i_src->iv_headerVersion;
+    o_dest->iv_normalized = i_src->iv_normalized;
+    o_dest->iv_tocSorted = i_src->iv_tocSorted;
+
+    for (i = 0; i < 3; i++)
+    {
+        o_dest->iv_reserved8[i] = 0;
+    }
+
+    memcpy(o_dest->iv_buildUser, i_src->iv_buildUser,
+           sizeof(i_src->iv_buildUser));
+    memcpy(o_dest->iv_buildHost, i_src->iv_buildHost,
+           sizeof(i_src->iv_buildHost));
+    memcpy(o_dest->iv_reservedChar, i_src->iv_reservedChar,
+           sizeof(i_src->iv_reservedChar));
+
+#else
+
+    if (o_dest != i_src)
+    {
+        *o_dest = *i_src;
+    }
+
+#endif  /* _BIG_ENDIAN */
+}
+
+
+int
+p9_xip_map_toc(void* io_image,
+               int (*i_fn)(void* io_image,
+                           const P9XipItem* i_item,
+                           void* io_arg),
+               void* io_arg)
+{
+    int rc;
+    P9XipToc* imageToc;
+    P9XipItem item;
+    size_t entries;
+
+    do
+    {
+        rc = xipQuickCheck(io_image, 0);
+
+        if (rc)
+        {
+            break;
+        }
+
+        rc = p9_xip_get_toc(io_image, &imageToc, &entries, 0, 0);
+
+        if (rc)
+        {
+            break;
+        }
+
+        for (; entries--; imageToc++)
+        {
+            rc = xipDecodeToc(io_image, imageToc, &item);
+
+            if (rc)
+            {
+                break;
+            }
+
+            rc = i_fn(io_image, &item, io_arg);
+
+            if (rc)
+            {
+                break;
+            }
+        }
+    }
+    while(0);
+
+    return rc;
+}
diff --git a/src/import/chips/p9/xip/p9_xip_image.h b/src/import/chips/p9/xip/p9_xip_image.h
new file mode 100644
index 00000000..09bc1aa5
--- /dev/null
+++ b/src/import/chips/p9/xip/p9_xip_image.h
@@ -0,0 +1,1925 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/xip/p9_xip_image.h $                          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+/// \file p9_xip_image.h
+/// \brief definition of structs in sections
+///
+/// Contains struct ProcSbeFixed which contains functions, rings and
+/// attributes whose pointers are stored in the fixed and fixed_toc section
+/// Everything related to creating and manipulating P9-XIP binary images
+
+// *INDENT-OFF*
+
+#ifndef __P9_XIP_IMAGE_H
+#define __P9_XIP_IMAGE_H
+
+/// Current version (fields, layout, sections) of the P9_XIP header
+///
+/// If any changes are made to this file or to p9_xip_header.H, please update
+/// the header version and follow-up on all of the error messages.
+
+#define P9_XIP_HEADER_VERSION 9
+
+/// \defgroup p9_xip_magic_numbers P9-XIP magic numbers
+///
+/// An P9-XIP magic number is a 64-bit constant.  The 4 high-order bytes
+/// contain the ASCII characters "XIP " and identify the image as a P9-XIP
+/// image, while the 4 low-order bytes identify the type of the image.
+///
+/// @{
+
+#ifdef __ASSEMBLER__
+    #define ULL(x) x
+#else
+    #define ULL(x) x##ull
+#endif
+
+#define P9_XIP_MAGIC             0x58495020           // "XIP "
+#define P9_XIP_MAGIC_BASE    ULL(0x5849502042415345)  // "XIP BASE"
+#define P9_XIP_MAGIC_SEEPROM ULL(0x584950205345504d)  // "XIP SEPM"
+#define P9_XIP_MAGIC_CENTAUR ULL(0x58495020434e5452)  // "XIP CNTR"
+#define P9_XIP_MAGIC_HW      ULL(0x5849502020204857)  // "XIP   HW"
+#define P9_XIP_MAGIC_SGPE    ULL(0x5849502053475045)  // "XIP SGPE"
+#define P9_XIP_MAGIC_RESTORE ULL(0x5849502052455354)  // "XIP REST"
+#define P9_XIP_MAGIC_CME     ULL(0x5849502020434d45)  // "XIP  CME"
+#define P9_XIP_MAGIC_PGPE    ULL(0x5849502050475045)  // "XIP PGPE"
+#define P9_XIP_MAGIC_IOPPE   ULL(0x5849502049505045)  // "XIP IPPE"
+#define P9_XIP_MAGIC_FPPE    ULL(0x5849502046505045)  // "XIP FPPE"
+
+/// @}
+
+
+/// \defgroup p9_xip_sections P9-XIP Image Section Indexes
+///
+/// These constants define the order that the P9XipSection structures appear
+/// in the header, which is not necessarily the order the sections appear in
+/// the binary image.  Given that P9-XIP image contents are tightly
+/// controlled, we use this simple indexing scheme for the allowed sections
+/// rather than a more general approach, e.g., allowing arbitrary sections
+/// identified by their names.
+///
+/// @{
+
+// fixed number of entries in section table including common and
+// image-specific sections
+#define P9_XIP_SECTIONS 15
+
+// this ensures that common sections go first followed by image-specific
+// sections, to be used to define image-specific sections
+#define P9_XIP_SECTIONS_PLUS(num) (P9_XIP_SECTIONS_COMMON + num)
+
+#ifndef __ASSEMBLER__
+
+// these are common P9-XIP sections defined for a images
+typedef enum {
+    P9_XIP_SECTION_HEADER    = 0,
+    P9_XIP_SECTION_FIXED     = 1,
+    P9_XIP_SECTION_FIXED_TOC = 2,
+    P9_XIP_SECTION_TOC       = 3,
+    P9_XIP_SECTION_STRINGS   = 4,
+    P9_XIP_SECTIONS_COMMON   = 5   // total number of common sections
+} p9_xip_section_common_t;
+
+/// Applications can expand this macro to create an array of section names.
+#define P9_XIP_SECTION_NAMES_COMMON \
+    ".header",                      \
+    ".fixed",                       \
+    ".fixedtoc",                    \
+    ".toc",                         \
+    ".strings"
+
+#define P9_XIP_SECTION_NAMES(var, ...) \
+    const char* var[] =  {             \
+        P9_XIP_SECTION_NAMES_COMMON,   \
+        __VA_ARGS__                    \
+                         }
+
+/// Applications can use this macro to safely index the array of section
+/// names.
+#define P9_XIP_SECTION_NAME(var, n)                               \
+    ((((n) < 0) || ((n) >= (int)(sizeof(var) / sizeof(char*)))) ? \
+     "" : var[n])
+
+#endif  /* __ASSEMBLER__ */
+
+/// @}
+
+
+/// \defgroup p9_xip_validate() ignore masks.
+///
+/// These defines, when matched in p9_xip_validate(), cause the validation
+/// to skip the check of the corresponding property. The purpose is to more
+/// effectively debug images that may be damaged and which have excess info
+/// before or after the image. The latter will be the case when dumping the
+/// image as a memory block without knowing where the image starts and ends.
+///
+/// @{
+
+#define P9_XIP_IGNORE_FILE_SIZE (uint32_t)0x00000001
+#define P9_XIP_IGNORE_ALL       (uint32_t)0x80000000
+
+/// @}
+
+/// Maximum section alignment for P9-XIP sections
+#define P9_XIP_MAX_SECTION_ALIGNMENT 128
+
+/// \defgroup p9_xip_toc_types P9-XIP Table of Contents data types
+///
+/// These are the data types stored in the \a iv_type field of the P9XipToc
+/// objects.  These must be defined as manifest constants because they are
+/// required to be recognized as manifest constants in C (as opposed to C++)
+/// code.
+///
+/// NB: The 0x0 code is purposefully left undefined to catch bugs.
+///
+/// @{
+
+/// Data is a single unsigned byte
+#define P9_XIP_UINT8 0x01
+
+/// Data is a 16-bit unsigned integer
+#define P9_XIP_UINT16 0x02
+
+/// Data is a 32-bit unsigned integer
+#define P9_XIP_UINT32 0x03
+
+/// Data is a 64-bit unsigned integer
+#define P9_XIP_UINT64 0x04
+
+/// Data is a single signed byte
+#define P9_XIP_INT8 0x05
+
+/// Data is a 16-bit signed integer
+#define P9_XIP_INT16 0x06
+
+/// Data is a 32-bit signed integer
+#define P9_XIP_INT32 0x07
+
+/// Data is a 64-bit signed integer
+#define P9_XIP_INT64 0x08
+
+/// Data is a 0-byte terminated ASCII string
+#define P9_XIP_STRING 0x09
+
+/// Data is an address
+#define P9_XIP_ADDRESS 0x0A
+
+/// The maximum type number
+#define P9_XIP_MAX_TYPE_INDEX 0x0A
+
+/// Applications can expand this macro to get access to string forms of the
+/// P9-XIP data types if desired.
+#define P9_XIP_TYPE_STRINGS(var) \
+    const char* var[] = {        \
+        "Illegal 0 Code",        \
+        "P9_XIP_UINT8",          \
+        "P9_XIP_UINT16",         \
+        "P9_XIP_UINT32",         \
+        "P9_XIP_UINT64",         \
+        "P9_XIP_INT8",           \
+        "P9_XIP_INT16",          \
+        "P9_XIP_INT32",          \
+        "P9_XIP_INT64",          \
+        "P9_XIP_STRING",         \
+        "P9_XIP_ADDRESS",        \
+    }
+
+/// Applications can expand this macro to get access to abbreviated string
+/// forms of the P9-XIP data types if desired.
+#define P9_XIP_TYPE_ABBREVS(var) \
+    const char* var[] = {        \
+        "Illegal 0 Code",        \
+        "u8 ",                   \
+        "u16",                   \
+        "u32",                   \
+        "u64",                   \
+        "i8 ",                   \
+        "i16",                   \
+        "i32",                   \
+        "i64",                   \
+        "str",                   \
+        "adr",                   \
+    }
+
+/// Applications can use this macro to safely index either array of P9-XIP
+/// type strings.
+#define P9_XIP_TYPE_STRING(var, n)                 \
+    (((n) > (sizeof(var) / sizeof(char*))) ?       \
+     "Invalid P9-XIP type specification" : var[n])
+
+/// @}
+
+
+/// Final alignment constraint for P9-XIP images.
+///
+/// images are required to be multiples of 8 bytes in length, to
+/// gaurantee that the something will be able to complete any 8-byte load/store.
+#define P9_XIP_FINAL_ALIGNMENT 8
+
+
+////////////////////////////////////////////////////////////////////////////
+// C Definitions
+////////////////////////////////////////////////////////////////////////////
+
+#ifndef __ASSEMBLER__
+#include <stddef.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if 0
+} /* So __cplusplus doesn't mess w/auto-indent */
+#endif
+
+/// P9-XIP Section information
+///
+/// This structure defines the data layout of section table entries in the
+/// P9-XIP image header.
+
+// -*- DO NOT REORDER OR EDIT THIS STRUCTURE DEFINITION WITHOUT ALSO    -*-
+// -*- EDITING THE ASSEMBLER LAYOUT IN p9_xip_header.H                 -*-
+
+typedef struct
+{
+
+    /// The offset (in bytes) of the section from the beginning of the image
+    ///
+    /// In normalized images the section offset will always be 0 if the
+    /// section size is also 0.
+    uint32_t iv_offset;
+
+    /// The size of the section in bytes, exclusive of alignment padding
+    ///
+    /// This is the size of the program-significant data in the section,
+    /// exclusive of any alignment padding or reserved or extra space.  The
+    /// alignment padding (reserved space) is not represented explicitly, but
+    /// is only implied by the offset of any subsequent non-empty section, or
+    /// in the case of the final section in the image, the image size.
+    ///
+    /// Regardless of the \a iv_offset, if the \a iv_size of a section is 0 it
+    /// should be considered "not present" in the image.  In normalized images
+    /// the section offset will always be 0 if the section size is also 0.
+    uint32_t iv_size;
+
+    /// The required initial alignment for the section offset
+    ///
+    /// The image and the applications using P9-XIP images have strict
+    /// alignment/padding requirements.  The image does not handle any type of
+    /// unaligned instruction or data fetches.  Some sections and subsections
+    /// must also be POWER cache-line aligned. The \a iv_alignment applies to
+    /// the first byte of the section. image images are also required to be
+    /// multiples of 8 bytes in length, to gaurantee that the something will be
+    /// able to complete any 8-byte load/store.  These constraints are checked
+    /// by p9_xip_validate() and enforced by p9_xip_append(). The alignment
+    /// constraints may force a section to be padded, which may create "holes"
+    /// in the image as explained in the comments for the \a iv_size field.
+    ///
+    /// Note that alignment constraints are always checked relative to the
+    /// first byte of the image for in-memory images, not relative to the host
+    /// address. Alignment specifications are required to be a power-of-2.
+    uint8_t iv_alignment;
+
+    /// Reserved structure alignment padding; Pad to 12 bytes
+    uint8_t iv_reserved8[3];
+
+} P9XipSection;
+
+/// The P9XipSection structure is created by assembler code and is expected
+/// to have the same size in C code.  This constraint is checked in
+/// p9_xip_validate().
+#define SIZE_OF_P9_XIP_SECTION 12
+
+
+/// P9-XIP binary image header
+///
+/// This header occupies the initial bytes of a P9-XIP binary image.
+/// The header contents are documented here, however the structure is actually
+/// defined in the file p9_xip_header.S, and these two definitions must be
+/// kept consistent.
+///
+/// The header is a fixed-format representation of the most critical
+/// information about the image.  The large majority of information about the
+/// image and its contents are available through the searchable table of
+/// contents. image code itself normally accesses the data directly through
+/// global symbols.
+///
+/// The header only contains information 1) required by OTPROM code (e.g., the
+/// entry point); 2) required by search and updating APIs (e.g., the
+/// locations and sizes of all of the sections.); a few pieces of critical
+/// meta-data (e.g., information about the image build process).
+///
+/// Any entries that are accessed by image code are required to be 64 bits, and
+/// will appear at the beginning of the header.
+///
+/// The header also contains bytewise offsets and sizes of all of the sections
+/// that are assembled to complete the image.  The offsets are relative to the
+/// start of the image (where the header is loaded).  The sizes include any
+/// padding inserted by the link editor to guarantee section alignment.
+///
+/// Every field of the header is also accesssible through the searchable table
+/// of contents as documented in p9_xip_header.S.
+
+// -*- DO NOT REORDER OR EDIT THIS STRUCTURE DEFINITION WITHOUT ALSO     -*-
+// -*- EDITING THE ASSEMBLER LAYOUT IN p9_xip_header.S, AND WITHOUT     -*-
+// -*- UPDATING THE p9_xip_translate_header() API IN p9_xip_image.c.   -*-
+
+typedef struct
+{
+
+    //////////////////////////////////////////////////////////////////////
+    // Identification - 8-byte aligned; 8 entries
+    //////////////////////////////////////////////////////////////////////
+
+    /// Contains P9_XIP_MAGIC to identify a P9-XIP image
+    uint64_t iv_magic;
+
+    /// The entry address of the L1 loader entry point in SEEPROM
+    uint64_t iv_L1LoaderAddr;
+
+    /// The entry address of the L2 loader entry point in SRAM
+    uint64_t iv_L2LoaderAddr;
+
+    /// The entry address of Kernel in SRAM
+    uint64_t iv_kernelAddr;
+
+    /// The base address used to link the image, as a full relocatable image
+    /// address
+    uint64_t iv_linkAddress;
+
+    /// Reserved for future expansion
+    uint64_t iv_reserved64[3];
+
+    //////////////////////////////////////////////////////////////////////
+    // Section Table - 4-byte aligned; 16 entries
+    //////////////////////////////////////////////////////////////////////
+
+    P9XipSection iv_section[P9_XIP_SECTIONS];
+
+    //////////////////////////////////////////////////////////////////////
+    // Other information - 4-byte aligned; 8 entries
+    //////////////////////////////////////////////////////////////////////
+
+    /// The size of the image (including padding) in bytes
+    uint32_t iv_imageSize;
+
+    /// Build date generated by `date +%Y%m%d`, e.g., 20110630
+    uint32_t iv_buildDate;
+
+    /// Build time generated by `date +%H%M`, e.g., 0756
+    uint32_t iv_buildTime;
+
+    /// Reserved for future expansion
+    uint32_t iv_reserved32[5];
+
+    //////////////////////////////////////////////////////////////////////
+    // Other Information - 1-byte aligned; 8 entries
+    //////////////////////////////////////////////////////////////////////
+
+    /// Header format version number
+    uint8_t iv_headerVersion;
+
+    /// Indicates whether the image has been normalized (0/1)
+    uint8_t iv_normalized;
+
+    /// Indicates whether the TOC has been sorted to speed searching (0/1)
+    uint8_t iv_tocSorted;
+
+    /// Reserved for future expansion
+    uint8_t iv_reserved8[5];
+
+    //////////////////////////////////////////////////////////////////////
+    // Strings; 64 characters allocated
+    //////////////////////////////////////////////////////////////////////
+
+    /// Build user, generated by `id -un`
+    char iv_buildUser[16];
+
+    /// Build host, generated by `hostname`
+    char iv_buildHost[40];
+
+    /// Reserved for future expansion
+    char iv_reservedChar[8];
+
+} P9XipHeader;
+
+
+
+/// A C-structure form of the P9-XIP Table of Contents (TOC) entries
+///
+/// The .toc section consists entirely of an array of these structures.
+/// TOC entries are never accessed by image code.
+///
+/// These structures store indexing information for global data required to be
+/// manipulated by external tools.  The actual data is usually allocated in a
+/// data section and manipulated by the SBE code using global or local symbol
+/// names.  Each TOC entry contains a pointer to a keyword string naming the
+/// data, the address of the data (or the data itself), the data type,
+/// meta-information about the data, and for vectors the vector size.
+
+// -*- DO NOT REORDER OR EDIT THIS STRUCTURE DEFINITION WITHOUT ALSO     -*-
+// -*- EDITING THE ASSEMBLER MACROS (BELOW) THAT CREATE THE TABLE OF     -*-
+// -*- CONTENTS ENTRIES.                                                 -*-
+
+typedef struct
+{
+
+    /// A pointer to a 0-byte terminated ASCII string identifying the data.
+    ///
+    /// When allocated by the .xip_toc macro this is a pointer to the string
+    /// form of the symbol name for the global or local symbol associated with
+    /// the data which is allocated in the .strings section. This pointer is
+    /// not aligned.
+    ///
+    /// When the image is normalized this pointer is replaced by the offset of
+    /// the string in the .strings section.
+    uint32_t iv_id;
+
+    /// A 32-bit pointer locating the data
+    ///
+    /// This field is initially populated by the link editor.  For scalar,
+    /// vector and string types this is the final relocated address of the
+    /// first byte of the data.  For address types, this is the relocated
+    /// address.  When the image is normalized, these addresses are converted
+    /// into the equivalent offsets from the beginning of the section holding
+    /// the data.
+    uint32_t iv_data;
+
+    /// The type of the data; See \ref p9_xip_toc_types.
+    uint8_t iv_type;
+
+    /// The section containing the data; See \ref p9_xip_sections.
+    uint8_t iv_section;
+
+    /// The number of elements for vector types, otherwise 1 for scalar types
+    /// and addresses.
+    ///
+    /// Vectors are naturally limited in size, e.g. to the number of cores,
+    /// chips in a node, DD-levels etc.  If \a iv_elements is 0 then no bounds
+    /// checking is done on get/set accesses of the data.
+    uint8_t iv_elements;
+
+    /// Structure alignment padding; Pad to 12 bytes
+    uint8_t iv_pad;
+
+} P9XipToc;
+
+/// The P9XipToc structure is created by assembler code and is expected
+/// to have the same size in C code.  This constraint is checked in
+/// p9_xip_validate().
+#define SIZE_OF_P9_XIP_TOC 12
+
+
+/// A C-structure form of hashed P9-XIP Table of Contents (TOC) entries
+///
+/// This structure was introduced in order to allow a small TOC for the .fixed
+/// section to support minimum-sized SEEPROM images in which the global TOC
+/// and all strings have been stripped out.  In this structure the index
+/// string has been replaced by a 32-bit hash, and there is no longer a record
+/// of the original data name other then the hash.  The section of the data is
+/// assumed to be .fixed, with a maximum 16-bit offset.
+///
+/// These structures are created when entries are made in the .fixed section.
+/// They are created empty, then filled in during image normalization.
+///
+/// This structure allows the p9_xip_get*() and p9_xip_set*() APIs to work
+/// even on highly-stripped SEEPROM images.
+
+typedef struct
+{
+
+    /// A 32-bit hash (FNV-1a) of the Id string.
+    uint32_t iv_hash;
+
+    /// The offset in bytes from the start of the (implied) section of the data
+    uint16_t iv_offset;
+
+    /// The type of the data; See \ref p9_xip_toc_types.
+    uint8_t iv_type;
+
+    /// The number of elements for vector types, otherwise 1 for scalar types
+    /// and addresses.
+    ///
+    /// Vectors are naturally limited in size, e.g. to the number of cores,
+    /// chips in a node, DD-levels etc.  If \a iv_elements is 0 then no bounds
+    /// checking is done on get/set accesses of the data.
+    uint8_t iv_elements;
+
+} P9XipHashedToc;
+
+/// The P9XipHashedToc structure is created by assembler code and is expected
+/// to have the same size in C code.  This constraint is checked in
+/// p9_xip_validate().
+#define SIZE_OF_P9_XIP_HASHED_TOC 8
+
+
+/// A decoded TOC entry for use by applications
+///
+/// This structure is a decoded form of a normalized TOC entry, filled in by
+/// the p9_xip_decode_toc() and p9_xip_find() APIs.  This structure is
+/// always returned with data elements in host-endian format.
+///
+/// In the event that the TOC has been removed from the image, this structure
+/// will also be returned by p9_xip_find() with information populated from
+/// the .fixed_toc section if possible.  In this case the field \a iv_partial
+/// will be set and only the fields \a iv_address, \a iv_imageData, \a iv_type
+/// and \a iv_elements will be populated (all other fields will be set to 0).
+///
+/// \note Only special-purpose applications will ever need to use this
+/// structure given that the higher-level APIs p9_xip_get_*() and
+/// p9_xip_set_*() are provided and should be used if possible, especially
+/// given that the information may be truncated as described above.
+
+typedef struct
+{
+
+    /// A pointer to the associated TOC entry as it exists in the image
+    ///
+    ///  If \a iv_partial is set this field is returned as 0.
+    P9XipToc* iv_toc;
+
+    /// The full relocatable image address
+    ///
+    /// All relocatable addresses are computed from the \a iv_linkAddress
+    /// stored in the header. For scalar and string data, this is the
+    /// relocatable address of the data.  For address-only entries, this is
+    /// the indexed address itself.
+    uint64_t iv_address;
+
+    /// A host pointer to the first byte of text or data within the image
+    ///
+    /// For scalar or string types this is a host pointer to the first byte of
+    /// the data.  For code pointers (addresses) this is host pointer to the
+    /// first byte of code.  Note that any use of this field requires the
+    /// caller to handle conversion of the data to host endian-ness if
+    /// required.  Only 8-bit and string data can be used directly on all
+    /// hosts.
+    void* iv_imageData;
+
+    /// The item name
+    ///
+    /// This is a pointer in host memory to a string that names the TOC entry
+    /// requested.  This field is set to a pointer to the ID string of the TOC
+    /// entry inside the image. If \a iv_partial is set this field is returned
+    /// as 0.
+    char* iv_id;
+
+    /// The data type, one of the P9_XIP_* constants
+    uint8_t iv_type;
+
+    /// The number of elements in a vector
+    ///
+    /// This field is set from the TOC entry when the TOC entry is
+    /// decoded. This value is stored as 1 for scalar declarations, and may be
+    /// set to 0 for vectors with large or undeclared sizes.  Otherwise it is
+    /// used to bounds check indexed accesses.
+    uint8_t iv_elements;
+
+    /// Is this record only partially populated?
+    ///
+    /// This field is set to 0 normally, and only set to 1 if a lookup is made
+    /// in an image that only has the fixed TOC and the requested Id hashes to
+    /// the fixed TOC.
+    uint8_t iv_partial;
+
+} P9XipItem;
+
+
+/// Validate a P9-XIP image
+///
+/// \param[in] i_image A pointer to a P9-XIP image in host memory.
+///
+/// \param[in] i_size The putative size of the image
+///
+/// \param[in] i_maskIgnores Array of ignore bits representing which properties
+/// should not be checked for in p9_xip_validate2().
+///
+/// This API should be called first by all applications that manipulate
+/// P9-XIP images in host memory.  The magic number is validated, and
+/// the image is checked for consistency of the section table and table of
+/// contents.  The \a iv_imageSize field of the header must also match the
+/// provided \a i_size parameter.  Validation does not modify the image.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_validate(void* i_image, const uint32_t i_size);
+
+int
+p9_xip_validate2(void* i_image, const uint32_t i_size,
+                 const uint32_t i_maskIgnores);
+
+
+/// Normalize the P9-XIP image
+///
+/// \param[in] io_image A pointer to a P9-XIP image in host memory.  The
+/// image is assumed to be consistent with the information contained in the
+/// header regarding the presence of and sizes of all sections.
+///
+/// P9-XIP images must be normalized before any other APIs are allowed to
+/// operate on the image.  Since normalization modifies the image, an explicit
+/// call to normalize the image is required.  Briefly, normalization modifies
+/// the TOC entries created by the final link to simplify search, updates,
+/// modification and relocation of the image.  Normalization is explained in
+/// the written documentation of the P9-XIP binary format. Normalization does
+/// not modify the size of the image.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_normalize(void* io_image);
+
+
+/// Return the size of a P9-XIP image from the image header
+///
+/// \param[in] i_image A pointer to a P9-XIP image in host memory.  The
+/// image is assumed to be consistent with the information contained in the
+/// header regarding the presence of and sizes of all sections.
+///
+/// \param[out] o_size A pointer to a variable returned as the size of the
+/// image in bytes, as recorded in the image header.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_image_size(void* i_image, uint32_t* o_size);
+
+
+/// Locate a section table entry and translate into host format
+///
+/// \param[in] i_image A pointer to a P9-XIP image in host memory.
+///
+/// \param[in] i_sectionId Identifies the section to be queried.  See \ref
+/// p9_xip_sections.
+///
+/// \param[out] o_hostSection Updated to contain the section table entry
+/// translated to host byte order.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_get_section(const void* i_image,
+                   const int i_sectionId,
+                   P9XipSection* o_hostSection);
+
+
+/// Endian translation of a P9XipHeader object
+///
+/// \param[out] o_hostHeader The destination object.
+///
+/// \param[in] i_imageHeader The source object.
+///
+/// Translation of a P9XipHeader includes translation of all data members
+/// including traslation of the embedded section table.  This translation
+/// works even if \a o_src == \a o_dest, i.e., in the destructive case.
+void
+p9_xip_translate_header(P9XipHeader* o_hostHeader,
+                        const P9XipHeader* i_imageHeader);
+
+
+/// Get scalar data from a P9-XIP image
+///
+/// \param[in] i_image A pointer to a P9-XIP image in host memory.  The
+/// image is assumed to be consistent with the information contained in the
+/// header regarding the presence of and sizes of all sections.  The image is
+/// also required to have been normalized.
+///
+/// \param[in] i_id A pointer to a 0-terminated ASCII string naming the item
+/// requested.
+///
+/// \param[out] o_data A pointer to an 8-byte integer to receive the scalar
+/// data. Assuming the item is located this variable is assigned by the call.
+/// In the event of an error the final state of \a o_data is not specified.
+///
+/// This API searches the P9-XIP Table of Contents (TOC) for the item named
+/// \a i_id, assigning \a o_data from the image if the item is found and is a
+/// scalar value.  Scalar values include 8- 32- and 64-bit integers and image
+/// addresses.  Image data smaller than 64 bits are extracted as unsigned
+/// types, and it is the caller's responsibility to cast or convert the
+/// returned data as appropriate.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_get_scalar(void* i_image, const char* i_id, uint64_t* o_data);
+
+
+/// Get endianness converted value from the P9-XIP image toc data
+///
+/// \param[in] i_item - decoded toc entry
+
+/// \param[out] o_data A pointer to an 8-byte integer to receive the scalar
+/// data. Assuming the item is located this variable is assigned by the call.
+/// In the event of an error the final state of \a o_data is not specified.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_get_item(const P9XipItem *i_item, uint64_t* o_data);
+
+
+/// Get an integral element from a vector held in a P9-XIP image
+///
+/// \param[in] i_image A pointer to a P9-XIP image in host memory.  The
+/// image is assumed to be consistent with the information contained in the
+/// header regarding the presence of and sizes of all sections.  The image is
+/// also required to have been normalized.
+///
+/// \param[in] i_id A pointer to a 0-terminated ASCII string naming the item
+/// requested.
+///
+/// \param[in] i_index  The index of the vector element to return.
+///
+/// \param[out] o_data A pointer to an 8-byte integer to receive the
+/// data. Assuming the item is located this variable is assigned by the call.
+/// In the event of an error the final state of \a o_data is not specified.
+///
+/// This API searches the P9-XIP Table of Contents (TOC) for the \a i_index
+/// element of the item named \a i_id, assigning \a o_data from the image if
+/// the item is found, is a vector of an integral type, and the \a i_index is
+/// in bounds.  Vector elements smaller than 64 bits are extracted as unsigned
+/// types, and it is the caller's responsibility to cast or convert the
+/// returned data as appropriate.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_get_element(void* i_image,
+                   const char* i_id,
+                   const uint32_t i_index,
+                   uint64_t* o_data);
+
+
+/// Get string data from a P9-XIP image
+///
+/// \param[in] i_image A pointer to a P9-XIP image in host memory.  The
+/// image is assumed to be consistent with the information contained in the
+/// header regarding the presence of and sizes of all sections.  The image is
+/// also required to have been normalized.
+///
+/// \param[in] i_id A pointer to a 0-terminated ASCII string naming the item
+/// requested.
+///
+/// \param[out] o_data A pointer to a character pointer.  Assuming the
+/// item is located this variable is assigned by the call to point to the
+/// string as it exists in the \a i_image.  In the event of an error the final
+/// state of \a o_data is not specified.
+///
+/// This API searches the P9-XIP Table of Contents (TOC) for the item named
+/// \a i_id, assigning \a o_data if the item is found and is a string.  It is
+/// the caller's responsibility to copy the string from the \a i_image memory
+/// space if necessary.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_get_string(void* i_image, const char* i_id, char** o_data);
+
+
+/// Directly read 64-bit data from the image based on a image address
+///
+/// \param[in] i_image A pointer to a P9-XIP image in host memory.  The
+/// image is assumed to be consistent with the information contained in the
+/// header regarding the presence of and sizes of all sections.
+///
+/// \param[in] i_imageAddress A relocatable IMAGE address contained in the
+/// image, presumably of an 8-byte data area.  The \a i_imageAddress is
+/// required to be 8-byte aligned, otherwise the P9_XIP_ALIGNMENT_ERROR code
+/// is returned.
+///
+/// \param[out] o_data The 64 bit data in host format that was found at \a
+/// i_imageAddress.
+///
+/// This API is provided for applications that need to manipulate P9-XIP
+/// images in terms of their relocatable IMAGE addresses.  The API checks that
+/// the \a i_imageAddress is properly aligned and contained in the image, then
+/// reads the contents of \a i_imageAddress into \a o_data, performing
+/// image-to-host endianess conversion if required.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_read_uint64(const void* i_image,
+                   const uint64_t i_imageAddress,
+                   uint64_t* o_data);
+
+
+/// Set scalar data in a P9-XIP image
+///
+/// \param[in,out] io_image A pointer to a P9-XIP image in host memory.
+/// The image is assumed to be consistent with the information contained in
+/// the header regarding the presence of and sizes of all sections.  The image
+/// is also required to have been normalized.
+///
+/// \param[in] i_id A pointer to a 0-terminated ASCII string naming the item
+/// to be modified.
+///
+/// \param[in] i_data The new scalar data.
+///
+/// This API searches the P9-XIP Table of Contents (TOC) for the item named
+/// by \a i_id, updating the image from \a i_data if the item is found, has
+/// a scalar type and can be modified.  For this API the scalar types include
+/// 8- 32- and 64-bit integers.  Although IMAGE addresses are considered a
+/// scalar type for p9_xip_get_scalar(), IMAGE addresses can not be modified
+/// by this API.  The caller is responsible for ensuring that the \a i_data is
+/// of the correct size for the underlying data element in the image.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_set_scalar(void* io_image, const char* i_id, const uint64_t i_data);
+
+
+/// Set an integral element in a vector held in a P9-XIP image
+///
+/// \param[in] i_image A pointer to a P9-XIP image in host memory.  The
+/// image is assumed to be consistent with the information contained in the
+/// header regarding the presence of and sizes of all sections.  The image is
+/// also required to have been normalized.
+///
+/// \param[in] i_id A pointer to a 0-terminated ASCII string naming the item
+/// to be updated.
+///
+/// \param[in] i_index  The index of the vector element to update.
+///
+/// \param[out] i_data The new vector element.
+///
+/// This API searches the P9-XIP Table of Contents (TOC) for the \a i_index
+/// element of the item named \a i_id, update the image from \a i_data if the
+/// item is found, is a vector of an integral type, and the \a i_index is in
+/// bounds.  The caller is responsible for ensuring that the \a i_data is of
+/// the correct size for the underlying data element in the image.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_set_element(void* i_image,
+                   const char* i_id,
+                   const uint32_t i_index,
+                   const uint64_t i_data);
+
+
+/// Set string data in a P9-XIP image
+///
+/// \param[in,out] io_image A pointer to a P9-XIP image in host memory.  The
+/// image is assumed to be consistent with the information contained in the
+/// header regarding the presence of and sizes of all sections.  The image is
+/// also required to have been normalized.
+///
+/// \param[in] i_id A pointer to a 0-terminated ASCII string naming the item
+/// to be modified.
+///
+/// \param[in] i_data A pointer to the new string data.
+///
+/// This API searches the P9-XIP Table of Contents (TOC) for the item named
+/// \a i_id, which must be a string variable.  If found, then the string data
+/// in the image is overwritten with \a i_data.  Strings are held 0-terminated
+/// in the image, and the P9-XIP format does not maintain a record of the
+/// amount of memory allocated for an individual string.  If a string is
+/// overwritten by a shorter string then the 'excess' storage is effectively
+/// lost.  If the length of \a i_data is longer that the current strlen() of
+/// the string data then \a i_data is silently truncated to the first
+/// strlen(old_string) characters.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_set_string(void* io_image, const char* i_id, const char* i_data);
+
+
+/// Directly write 64-bit data into the image based on a IMAGE address
+///
+/// \param[in, out] io_image A pointer to a P9-XIP image in host memory.  The
+/// image is assumed to be consistent with the information contained in the
+/// header regarding the presence of and sizes of all sections.
+///
+/// \param[in] i_imageAddress A relocatable IMAGE address contained in the
+/// image, presumably of an 8-byte data area.  The \a i_imageAddress is
+/// required to be 8-byte aligned, otherwise the P9_XIP_ALIGNMENT_ERROR code
+/// is returned.
+///
+/// \param[in] i_data The 64 bit data in host format to be written to \a
+/// i_imageAddress.
+///
+/// This API is provided for applications that need to manipulate P9-XIP
+/// images in terms of their relocatable IMAGE addresses.  The API checks that
+/// the \a i_imageAddress is properly aligned and contained in the image, then
+/// updates the contents of \a i_imageAddress with \a i_data, performing
+/// host-to-image endianess conversion if required.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_write_uint64(void* io_image,
+                    const uint64_t i_imageAddress,
+                    const uint64_t i_data);
+
+
+/// Map over a P9-XIP image Table of Contents
+///
+/// \param[in,out] io_image A pointer to a P9-XIP image in host memory.  The
+/// image is assumed to be consistent with the information contained in the
+/// header regarding the presence of and sizes of all sections.  The image is
+/// also required to have been normalized.
+///
+/// \param[in] i_fn A pointer to a function to call on each TOC entry.  The
+/// function has the prototype:
+///
+/// \code
+/// int (*i_fn)(void* io_image,
+///             const P9XipItem* i_item,
+///             void* io_arg)
+/// \endcode
+///
+/// \param[in,out] io_arg The private argument of \a i_fn.
+///
+/// This API iterates over each entry of the TOC, calling \a i_fn with
+/// pointers to the image, a P9XipItem* pointer, and a private argument. The
+/// iteration terminates either when all TOC entries have been mapped, or \a
+/// i_fn returns a non-zero code.
+///
+/// \retval 0 Success; All TOC entries were mapped, including the case that
+/// the .toc section is empty.
+///
+/// \retval non-0 May be either one of the P9-XIP image error codes (see \ref
+/// p9_xip_image_errors), or a non-zero code from \a i_fn. Since the standard
+/// P9_XIP return codes are > 0, application-defined codes should be < 0.
+int
+p9_xip_map_toc(void* io_image,
+               int (*i_fn)(void* io_image,
+                           const P9XipItem* i_item,
+                           void* io_arg),
+               void* io_arg);
+
+
+/// Find a P9-XIP TOC entry
+///
+/// \param[in] i_image A pointer to a P9-XIP image in host memory.  The
+/// image is assumed to be consistent with the information contained in the
+/// header regarding the presence of and sizes of all sections.  The image is
+/// also required to have been normalized.
+///
+/// \param[in] i_id A 0-byte terminated ASCII string naming the item to be
+/// searched for.
+///
+/// \param[out] o_item If the search is successful, then the object
+/// pointed to by \a o_item is filled in with the decoded form of the
+/// TOC entry for \a i_id.  If the API returns a non-0 error code then the
+/// final state of the storage at \a o_item is undefined.  This parameter may
+/// be suppied as 0, in which case p9_xip_find() serves as a simple predicate
+/// on whether an item is indexded in the TOC.
+///
+/// This API searches the TOC of a normalized P9-XIP image for the item named
+/// \a i_id, and if found, fills in the structure pointed to by \a
+/// o_item with a decoded form of the TOC entry.  If the item is not found,
+/// the following two return codes may be considered non-error codes:
+///
+/// - P9_XIP_ITEM_NOT_FOUND : No TOC record for \a i_id was found.
+///
+/// - P9_XIP_DATA_NOT_PRESENT : The item appears in the TOC, however the
+/// section containing the data is no longer present in the image.
+///
+/// If the TOC section has been deleted from the image, then the search is
+/// restricted to the abbreviated TOC that indexes data in the .fixed section.
+/// In this case the \a o_item structure is marked with a 1 in the \a
+/// iv_partial field since the abbreviated TOC can not populate the entire
+/// P9XipItem structure.
+///
+/// \note This API should typically only be used as a predicate, not as a way
+/// to access the image via the returned P9XipItem structure. To obtain data
+/// from the image or update data in the image use the p9_xip_get_*() and
+/// p9_xip_set_*() APIs respectively.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_find(void* i_image,
+            const char* i_id,
+            P9XipItem* o_item);
+
+
+
+/// Delete any section, except .header, from a P9-XIP image in host memory,
+/// even in-between sections, i.e. non-final sections.
+///
+/// \param[in,out] io_image A pointer to a P9-XIP image in host memory.  The
+/// image is assumed to be consistent with the information contained in the
+/// header regarding the presence of and sizes of all sections. The image is
+/// also required to have been normalized. In case of failure in this
+/// funtion, the io_image will get restored to its input value.
+///
+/// \param[out] o_imageBuf  A pointer to a pre-allocated buffer that MUST
+/// BE greater than or equal to the size of the \a io_image. The size of
+/// this buffer must be supplied in \a i_imageBufSize. If \a o_imageBuf
+/// is NULL, the supplied \a i_sectionId must be the final section in the
+/// image or this function will fail at deleting the section. On return
+/// from this function, o_imageBuf contains a copy of the initial input
+/// image \a io_image, but only if it's a valid buffer.
+///
+/// \param[in] i_imageBufSize The size of \a o_imageBuf buffer. It MUST
+/// BE greater than or equal to the size of \a io_image. However, if \a
+/// o_imageBuf is NULL, then this arg is ignored.
+///
+/// \param[in] i_sectionId Identifies the section to be deleted.  See \ref
+/// p9_xip_sections.
+///
+/// This API effectively deletes a section from a P9-XIP image held in host
+/// memory.  Deleting a section of the image means that the section size is
+/// set to 0, and the size of the image recorded in the header is reduced by
+/// the section size.  Any alignment padding of the in-between section is
+/// also handled, i.e. removed if final section and re-applied upon
+/// re-appending sections.  In the special case where \a o_imageBuf is
+/// NULL, unless the requested \a i_sectionId is already empty, only the final
+/// section (highest address offset) of the image may be deleted.
+///
+/// \note This API does not check for or warn if other sections in the image
+/// reference the deleted section.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_delete_section(void* io_image, 
+                      void* o_imageBuf,
+                      const uint32_t i_imageBufSize,
+                      const int i_sectionId);
+
+
+
+#ifndef PPC_HYP
+
+/// Duplicate a section from a P9-XIP image in host memory
+///
+/// \param[in,out] i_image A pointer to a P9-XIP image in host memory.  The
+/// image is assumed to be consistent with the information contained in the
+/// header regarding the presence of and sizes of all sections.
+///
+/// \param[in] i_sectionId Identifies the section to be duplicated.  See \ref
+/// p9_xip_sections.
+///
+/// \param[out] o_duplicate At exit, points to the newly allocated and
+/// initialized duplicate of the given section. The caller is responsible for
+/// free()-ing this memory when no longer required.
+///
+/// \param[out] o_size At exit, contains the size (in bytes) of the duplicated
+/// section.
+///
+/// This API creates a bytewise duplicate of a non-empty section into newly
+/// malloc()-ed memory. At exit \a o_duplicate points to the duplicate, and \a
+/// o_size is set the the size of the duplicated section. The caller is
+/// responsible for free()-ing the memory when no longer required.  The
+/// pointer at \a o_duplicate is set to NULL (0) and the \a o_size is set to 0
+/// in the event of any failure.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_duplicate_section(const void* i_image,
+                         const int i_sectionId,
+                         void** o_duplicate,
+                         uint32_t* o_size);
+
+#endif // PPC_HYP
+
+
+/// Append binary data to a P9-XIP image held in host memory
+///
+/// \param[in,out] io_image A pointer to a P9-XIP image in host memory.  The
+/// image is assumed to be consistent with the information contained in the
+/// header regarding the presence of and sizes of all sections. The image is
+/// also required to have been normalized.
+///
+/// \param[in] i_sectionId Identifies the section to contain the new data.
+///
+/// \param[in] i_data A pointer to the data to be appended to the image.  If
+/// this pointer is NULL (0), then the effect is as if \a i_data were a
+/// pointer to an \a i_size array of 0 bytes.
+///
+/// \param[in] i_size The size of the data to be appended in bytes.  If \a
+/// i_data is 0, then this is the number of bytes to clear.
+///
+/// \param[in] i_allocation The size of the memory region containing the
+/// image, measured from the first byte of the image.  The call will fail if
+/// appending the new data plus any alignment padding would overflow the
+/// allocated memory.
+///
+/// \param[out] o_sectionOffset If non-0 at entry, then the API updates the
+/// location pointed to by \a o_sectionOffset with the offset of the first
+/// byte of the appended data within the indicated section. This return value
+/// is invalid in the event of a non-0 return code.
+///
+/// This API copies data from \a i_data to the end of the indicated \a
+/// i_section.  The section \a i_section must either be empty, or must be the
+/// final (highest address) section in the image.  If the section is initially
+/// empty and \a i_size is non-0 then the section is created at the end of the
+/// image.  The size of \a i_section and the size of the image are always
+/// adjusted to reflect the newly added data.  This is a simple binary copy
+/// without any interpretation (e.g., endian-translation) of the copied data.
+/// The caller is responsible for insuring that the host memory area
+/// containing the P9-XIP image is large enough to hold the newly appended
+/// data without causing addressing errors or buffer overrun errors.
+///
+/// The final parameter \a o_sectionOffset is optional, and may be passed as
+/// NULL (0) if the application does not require the information.  This return
+/// value is provided to simplify typical use cases of this API:
+///
+/// - A scan program is appended to the image, or a run-time data area is
+/// allocated and cleared at the end of the image.
+///
+/// - Pointer variables in the image are updated with IMAGE addresses obtained
+/// via p9_xip_section2image(), or
+/// other procedure code initializes a newly allocated and cleared data area
+/// via host addresses obtained from p9_xip_section2host().
+///
+/// Regarding alignment, note that the P9-XIP format requires that sections
+/// maintain an initial alignment that varies by section, and the API will
+/// enforce these alignment constraints for all sections created by the API.
+/// All alignment is relative to the first byte of the image (\a io_image) -
+/// \e not to the current in-memory address of the image. By specification
+/// P9-XIP images must be loaded at a 4K alignment in order for IMAGE hardware
+/// relocation to work, however the APIs don't require this 4K alignment for
+/// in-memory manipulation of images.  Images to be executed on ImageVe will
+/// normally require at least 8-byte final aligment in order to guarantee that
+/// the ImageVe can execute an 8-byte fetch or load/store of the final
+/// doubleword.
+///
+/// \note If the TOC section is modified then the image is marked as having an
+/// unsorted TOC.
+///
+/// \note If the call fails for any reason (other than a bug in the API
+/// itself) then the \a io_image data is returned unmodified.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_append(void* io_image,
+              const int i_sectionId,
+              const void* i_data,
+              const uint32_t i_size,
+              const uint32_t i_allocation,
+              uint32_t* o_sectionOffset);
+
+
+/// Convert a P9-XIP section offset to a relocatable IMAGE address
+///
+/// \param[in] i_image A pointer to a P9-XIP image in host memory
+///
+/// \param[in] i_sectionId A valid P9-XIP section identifier; The section
+/// must be non-empty.
+///
+/// \param[in] i_offset An offset (in bytes) within the section.  At least one
+/// byte at \a i_offset must be currently allocated in the section.
+///
+/// \param[in] o_imageAddress The equivalent relocatable IMAGE address is
+/// returned via this pointer. Since valid IMAGE addresses are always either
+/// 4-byte (code) or 8-byte (data) aligned, this API checks the aligment of
+/// the translated address and returns P9_XIP_ALIGNMENT_ERROR if the IMAGE
+/// address is not at least 4-byte aligned.  Note that the translated address
+/// is still returned even if incorrectly aligned.
+///
+/// This API is typically used to translate section offsets returned from
+/// p9_xip_append() into relocatable IMAGE addresses.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_section2image(const void* i_image,
+                     const int i_sectionId,
+                     const uint32_t i_offset,
+                     uint64_t* o_imageAddress);
+
+
+/// Convert a P9-XIP relocatable image address to a host memory address
+///
+/// \param[in] i_image A pointer to a P9-XIP image in host memory.
+///
+/// \param[in] i_imageAddress A relocatable image address putatively addressing
+/// relocatable memory contained in the image.
+///
+/// \param[out] o_hostAddress The API updates the location pointed to by \a
+/// o_hostAddress with the host address of the memory addressed by \a
+/// i_imageAddress.  In the event of an error (non-0 return code) the final
+/// content of \a o_hostAddress is undefined.
+///
+/// This API is typically used to translate relocatable image addresses stored
+/// in the P9-XIP image into the equivalent host address of the in-memory
+/// image, allowing host-code to manipulate arbitrary data structures in the
+/// image. If the \a i_imageAddress does not refer to memory within the image
+/// (as determined by the link address and image size) then the
+/// P9_XIP_INVALID_ARGUMENT error code is returned.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_image2host(const void* i_image,
+                  const uint64_t i_imageAddress,
+                  void** o_hostAddress);
+
+
+/// Convert a P9-XIP relocatable image address to section Id and offset
+///
+/// \param[in] i_image A pointer to a P9-XIP image in host memory.
+///
+/// \param[in] i_imageAddress A relocatable image address putatively addressing
+/// relocatable memory contained in the image.
+///
+/// \param[out] o_section The API updates the location pointed to by \a
+/// o_section with the section Id of the memory addressed by \a
+/// i_imageAddress.  In the event of an error (non-0 return code) the final
+/// content of \a o_section is undefined.
+///
+/// \param[out] o_offset The API updates the location pointed to by \a
+/// o_offset with the byte offset of the memory addressed by \a i_imageAddress
+/// within \a o_section.  In the event of an error (non-0 return code) the
+/// final content of \a o_offset is undefined.
+///
+/// This API is typically used to translate relocatable image addresses stored
+/// in the P9-XIP image into the equivalent section + offset form, allowing
+/// host-code to manipulate arbitrary data structures in the image. If the \a
+/// i_imageAddress does not refer to memory within the image (as determined by
+/// the link address and image size) then the P9_XIP_INVALID_ARGUMENT error
+/// code is returned.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_image2section(const void* i_image,
+                     const uint64_t i_imageAddress,
+                     int* o_section,
+                     uint32_t* o_offset);
+
+
+/// Convert an in-memory P9-XIP host address to a relocatable image address
+///
+/// \param[in] i_image A pointer to a P9-XIP image in host memory
+///
+/// \param[in] i_hostAddress A host address addressing data within the image.
+///
+/// \param[out] o_imageAddress The API updates the location pointed to by \a
+/// o_imageAddress with the equivelent relocatable image address of the memory
+/// addressed by i_hostAddress.  Since valid image addresses are always either
+/// 4-byte (code) or 8-byte (data) aligned, this API checks the aligment of
+/// the translated address and returns P9_XIP_ALIGNMENT_ERROR if the image
+/// address is not at least 4-byte aligned.  Note that the translated address
+/// is still returned evn if incorrectly aligned.
+///
+/// This API is provided as a convenient way to convert host memory addresses
+/// for an in-memory P9-XIP image into image addresses correctly relocated for
+/// the image, for example to update pointer variables in the image.  If the
+/// \a i_hostAddress does not refer to memory within the image (as determined
+/// by the image address and image size) then the P9_XIP_INVALID_ARGUMENT
+/// error code is returned.
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_host2image(const void* i_image,
+                  void* i_hostAddress,
+                  uint64_t* o_imageAddress);
+
+/// Get all the information required to search and find the TOC
+///
+/// \param[in] i_image A pointer to a P9-XIP image in host memory
+///
+/// \param[out][optional] o_toc A pointer to TOC listing
+///
+/// \param[out][optional] o_entries Number of TOC entries located
+///
+/// \param[out][optional] o_sorted Indication if the TOC is sorted
+///
+/// \param[out][optional] o_strings A pointer to String section containing TOC
+///                                 names
+///
+/// \retval 0 Success
+///
+/// \retval non-0 See \ref p9_xip_image_errors
+int
+p9_xip_get_toc(void* i_image,
+               P9XipToc** o_toc,
+               size_t* o_entries,
+               int* o_sorted,
+               char** o_strings);
+
+
+/// \brief Decode a TOC entry from dump file
+///
+///\param[in] - i_image - seeprom image
+///\param[in] - i_dump - dump file
+///\param[in] - i_imageToc - TOC entry
+///\param[out] - o_item - decoded toc entry
+///
+///\return - 0 Success; non-0 See \ref p9_xip_image_errors
+int
+p9_xip_decode_toc_dump(void* i_image, void* i_dump,
+        P9XipToc* i_imageToc,
+        P9XipItem* o_item);
+
+// PHYP has their own way of implementing the <string.h> functions. PHYP also
+// does not allow static functions or data, so all of the XIP_STATIC functions
+// defined here are global to PHYP.
+
+#ifdef PPC_HYP
+
+    #ifdef PLIC_MODULE
+        #define strcpy(dest, src) hvstrcpy(dest, src)
+        #define strlen(s) hvstrlen(s)
+        #define strcmp(s1, s2) hvstrcmp(s1, s2)
+    #endif //PLIC_MODULE
+
+    #define XIP_STATIC
+
+#else // PPC_HYP
+
+    // #define XIP_STATIC static
+    #define XIP_STATIC
+
+#endif // PPC_HYP
+
+/// \defgroup p9_xip_image_errors Error codes from P9-XIP image APIs
+///
+/// @{
+
+/// A putative P9-XIP image does not have the correct magic number, or
+/// contains some other major inconsistency.
+#define P9_XIP_IMAGE_ERROR 1
+
+/// The TOC may be missing, partially present or may have an alignment problem.
+#define P9_XIP_TOC_ERROR 2
+
+/// A named item was not found in the P9-XIP TOC, or a putative HALT address
+/// is not associated with a halt code in .halt.
+#define P9_XIP_ITEM_NOT_FOUND 3
+
+/// A named item appears in the P9-XIP TOC, but the data is not present in
+/// the image.  This error can occur if sections have been deleted from the
+/// image.
+#define P9_XIP_DATA_NOT_PRESENT 4
+
+/// A named item appears in the P9-XIP TOC, but the data can not be
+/// modified. This error will occur if an attempt is made to modify an
+/// address-only entry.
+#define P9_XIP_CANT_MODIFY 5
+
+/// A direct or implied argument is invalid, e.g. an illegal data type or
+/// section identifier, or an address not contained within the image.
+#define P9_XIP_INVALID_ARGUMENT 6
+
+/// A data type mismatch or an illegal type was specified or implied for an
+/// operation.
+#define P9_XIP_TYPE_ERROR 7
+
+/// A bug in a P9-XIP image API
+#define P9_XIP_BUG 8
+
+/// The image must first be normalized with p9_xip_normalize().
+#define P9_XIP_NOT_NORMALIZED 9
+
+/// Attempt to delete a non-empty section that is not the final section of the
+/// image, or an attempt to append data to a non-empty section that is not the
+/// final section of the image, or an attempt to operate on an empty section
+/// for those APIs that prohibit this.
+#define P9_XIP_SECTION_ERROR 10
+
+/// An address translation API returned a image address that was not at least
+/// 4-byte aligned, or alignment violations were observed by
+/// p9_xip_validate() or p9_xip_append().
+#define P9_XIP_ALIGNMENT_ERROR 11
+
+/// An API that performs dynamic memory allocation was unable to allocate
+/// memory.
+#define P9_XIP_NO_MEMORY 12
+
+/// Attempt to get or set a vector element with an index that is outside of
+/// the declared bounds of the vector.
+#define P9_XIP_BOUNDS_ERROR 13
+
+/// Attempt to grow the image past its defined memory allocation
+#define P9_XIP_WOULD_OVERFLOW 14
+
+/// Error associated with the disassembler occured.
+#define P9_XIP_DISASSEMBLER_ERROR 15
+
+/// Hash collision creating the .fixed_toc section
+#define P9_XIP_HASH_COLLISION 16
+
+/// Invalid buffer. It had a NULL ptr.
+#define P9_XIP_NULL_BUFFER 17
+
+/// Image has been broken and unable to restore original image.
+#define P9_XIP_CANT_RESTORE_IMAGE 18
+
+/// Applications can expand this macro to declare an array of string forms of
+/// the error codes if desired.
+#define P9_XIP_ERROR_STRINGS(var)    \
+    const char* var[] = {            \
+        "Success",                   \
+        "P9_XIP_IMAGE_ERROR",        \
+        "P9_XIP_TOC_ERROR",          \
+        "P9_XIP_ITEM_NOT_FOUND",     \
+        "P9_XIP_DATA_NOT_PRESENT",   \
+        "P9_XIP_CANT_MODIFY",        \
+        "P9_XIP_INVALID_ARGUMENT",   \
+        "P9_XIP_TYPE_ERROR",         \
+        "P9_XIP_BUG",                \
+        "P9_XIP_NOT_NORMALIZED",     \
+        "P9_XIP_SECTION_ERROR",      \
+        "P9_XIP_ALIGNMENT_ERROR",    \
+        "P9_XIP_NO_MEMORY",          \
+        "P9_XIP_BOUNDS_ERROR",       \
+        "P9_XIP_WOULD_OVERFLOW",     \
+        "P9_XIP_DISASSEMBLER_ERROR", \
+        "P9_XIP_HASH_COLLISION",     \
+        "P9_XIP_NULL_BUFFER",        \
+        "P9_XIP_CANT_RESTORE_IMAGE", \
+    }
+
+/// Applications can use this macro to safely index the array of error
+/// strings.
+#define P9_XIP_ERROR_STRING(var, n)                              \
+    ((((n) < 0) || ((n) > (int)(sizeof(var) / sizeof(char*)))) ? \
+     "Bug : Invalid P9-XIP error code" : var[n])
+
+/// @}
+
+/// Disassembler error codes.
+#define DIS_IMAGE_ERROR                   1
+#define DIS_MEMORY_ERROR                  2
+#define DIS_DISASM_ERROR                  3
+#define DIS_RING_NAME_ADDR_MATCH_SUCCESS  4
+#define DIS_RING_NAME_ADDR_MATCH_FAILURE  5
+#define DIS_TOO_MANY_DISASM_WARNINGS      6
+#define DIS_DISASM_TROUBLES               7
+
+#define DIS_ERROR_STRINGS(var)              \
+    const char* var[] = {                   \
+        "Success",                          \
+        "DIS_IMAGE_ERROR",                  \
+        "DIS_MEMORY_ERROR",                 \
+        "DIS_DISASM_ERROR",                 \
+        "DIS_RING_NAME_ADDR_MATCH_SUCCESS", \
+        "DIS_RING_NAME_ADDR_MATCH_FAILURE", \
+        "DIS_TOO_MANY_DISASM_WARNINGS",     \
+        "DIS_DISASM_TROUBLES",              \
+    }
+
+#define DIS_ERROR_STRING(var, n)                                 \
+    ((((n) < 0) || ((n) > (int)(sizeof(var) / sizeof(char*)))) ? \
+     "Bug : Invalid DIS error code" : var[n])
+
+#if 0
+{
+    /* So __cplusplus doesn't mess w/auto-indent */
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // __ASSEMBLER__
+
+
+////////////////////////////////////////////////////////////////////////////
+// Assembler Definitions
+////////////////////////////////////////////////////////////////////////////
+
+#ifdef __ASSEMBLER__
+
+/// Create an XIP TOC entry
+///
+/// \param[in] index The string form of the \a index symbol is created and
+/// linked from the TOC entry to allow external search procedures to locate
+/// the \a address.
+///
+/// \param[in] type One of the P9_XIP_* type constants; See \ref
+/// p9_xip_toc_types.
+///
+/// \param[in] address The address of the idexed code or data; This will
+/// typically be a symbol.
+///
+/// \param[in] elements <Optional> For vector types, number of elements in the
+/// vector, which is limited to an 8-bit unsigned integer.  This parameter
+/// defaults to 1 which indicates a scalar type. Declaring a vector with 0
+/// elements disables bounds checking on vector accesses, and can be used if
+/// very large or indeterminate sized vectors are required. The TOC format
+/// does not support vectors of strings or addresses.
+///
+/// The \c .xip_toc macro creates a XIP Table of Contents (TOC) structure in
+/// the \c .toc section, as specified by the parameters.  This macro is
+/// typically not used directly in assembly code.  Instead programmers should
+/// use .xip_quad, .xip_quada, .xip_quadia, .xip_address or .xip_string
+
+    .macro .xip_toc, index:req, type:req, address:req, elements=1
+
+        .if (((\type) < 1) || ((\type) > P9_XIP_MAX_TYPE_INDEX))
+            .error ".xip_toc : Illegal type index"
+        .endif
+
+        // First push into the .strings section to lay down the
+        // string form of the index name under a local label.
+
+        .pushsection .strings
+7667862:
+        .asciz "\index"
+        .popsection
+
+        // Now the 12-byte TOC entry is created.  Push into the .toc section
+        // and lay down the first 4 bytes which are always a pointer to the
+        // string just declared.  The next 4 bytes are the address of the data
+        // (or the address itself in the case of address types). The final 4
+        // bytes are the type, section (always 0 prior to normalization),
+        // number of elements, and a padding byte.
+
+        .pushsection .toc
+
+        .long 7667862b, (\address)
+        .byte (\type), 0, (\elements), 0
+
+        .popsection
+
+    .endm
+
+
+/// Allocate and initialize 64-bit global scalar or vector data and create the
+/// TOC entry.
+///
+/// \param[in] symbol The name of the scalar or vector; this name is also used
+/// as the TOC index of the data.
+///
+/// \param[in] init The initial value of (each element of) the data.
+/// This is a 64-bit integer; To allocate address pointers use .xip_quada.
+///
+/// \param[in] elements The number of 64-bit elements in the data structure,
+/// defaulting to 1, with a maximum value of 255.
+///
+/// \param[in] section The section where the data will be allocated,
+/// default depends on the memory space
+
+    .macro .xip_quad, symbol:req, init:req, elements=1, section
+
+        ..xip_quad_helper .quad, \symbol, (\init), (\elements), \section
+
+    .endm
+
+
+/// Allocate and initialize 64-bit global scalar or vector data containing a
+/// relocatable address in and create the TOC entry.
+///
+/// \param[in] symbol The name of the scalar or vector; this name is also used
+/// as the TOC index of the data.
+///
+/// \param[in] init The initial value of (each element of) the data.  This
+/// will typically be a symbolic address. If the intention is to define an
+/// address that will always be filled in later by image manipulation tools,
+/// then use the .xip_quad macro with a 0 initial value.
+///
+/// \param[in] elements The number of 64-bit elements in the data structure,
+/// defaulting to 1, with a maximum value of 255.
+///
+/// \param[in] section The section where the data will be allocated,
+/// default depends on the memory space
+
+    .macro .xip_quada, symbol:req, offset:req, elements=1, section
+
+        ..xip_quad_helper .quada, \symbol, (\offset), (\elements), \section
+
+    .endm
+
+
+/// Helper for .xip_quad and .xip_quada
+
+    .macro ..xip_quad_helper, directive, symbol, init, elements, section
+
+        .if (((\elements) < 1) || ((\elements) > 255))
+            .error "The number of vector elements must be in the range 1..255"
+        .endif
+
+        ..xip_pushsection \section
+        .balign 8
+
+        .global \symbol
+\symbol\():
+        .rept (\elements)
+            \directive (\init)
+        .endr
+
+        .popsection
+
+        .xip_toc \symbol, P9_XIP_UINT64, \symbol, (\elements)
+
+    .endm
+
+
+/// Allocate and initialize 64-bit global scalar or vector data containing
+/// full 64-bit addresses and create a TOC entry
+///
+/// \param[in] symbol The name of the scalar or vector; this name is also used
+/// as the TOC index of the data.
+///
+/// \param[in] space A valid image memory space descriptor
+///
+/// \param[in] offset A 32-bit relocatable offset
+///
+/// \param[in] elements The number of 64-bit elements in the data structure,
+/// defaulting to 1, with a maximum value of 255.
+///
+/// \param[in] section The section where the data will be allocated,
+/// default depends on the memory space
+
+    .macro .xip_quadia, symbol:req, space:req, offset:req, elements=1, section
+
+        .if (((\elements) < 1) || ((\elements) > 255))
+            .error "The number of vector elements must be in the range 1..255"
+        .endif
+
+        ..xip_pushsection \section
+        .balign 8
+
+        .global \symbol
+\symbol\():
+        .rept (\elements)
+            .quadia (\space), (\offset)
+        .endr
+
+        .popsection
+
+        .xip_toc \symbol, P9_XIP_UINT64, \symbol, (\elements)
+
+    .endm
+
+/// Default push into .ipl_data unless in an OCI space, then .data
+
+    .macro ..xip_pushsection, section
+
+        .ifnb \section
+            .pushsection \section
+        .else
+            .if (_PGAS_DEFAULT_SPACE == PORE_SPACE_OCI)
+                .pushsection .data
+            .else
+                .pushsection .ipl_data
+            .endif
+        .endif
+
+        .balign 8
+
+    .endm
+
+/// Allocate and initialize a string in .strings
+///
+/// \param[in] index The string will be stored in the TOC using this index
+/// symbol.
+///
+/// \param[in] string The string to be allocated in .strings. String space is
+/// fixed once allocated.  Strings designed to be overwritten by external tools
+/// should be allocated to be as long as eventually needed (e.g., by a string
+/// of blanks.)
+
+    .macro .xip_string, index:req, string:req
+
+        .pushsection .strings
+7874647:
+        .asciz "\string"
+        .popsection
+
+        .xip_toc \index, P9_XIP_STRING, 7874647b
+
+    .endm
+
+
+/// Shorthand to create a TOC entry for an address
+///
+/// \param[in] index The symbol will be indexed as this name
+///
+/// \param[in] symbol <Optional> The symbol to index; by default the same as
+/// the index.
+
+    .macro .xip_address, index:req, symbol
+
+        .ifb \symbol
+            .xip_toc \index, P9_XIP_ADDRESS, \index
+        .else
+            .xip_toc \index, P9_XIP_ADDRESS, \symbol
+        .endif
+
+    .endm
+
+
+    .macro  .xip_section, s, alignment=1, empty=0
+        .ifnb \s
+_\s\()_section:
+            .if \empty
+                .long   0
+                .long   0
+            .else
+                .long   _\s\()_offset
+                .long   _\s\()_size
+            .endif
+        .else
+            .long   0
+            .long   0
+        .endif
+        .byte   (\alignment)
+        .byte   0, 0, 0
+    .endm
+
+#endif  // __ASSEMBLER__
+
+#ifndef __ASSEMBLER__
+
+/**************************************************************************/
+/* SBE Image                                                              */
+/**************************************************************************/
+
+typedef enum
+{
+    P9_XIP_SECTION_SBE_LOADERTEXT = P9_XIP_SECTIONS_PLUS(0),
+    P9_XIP_SECTION_SBE_LOADERDATA = P9_XIP_SECTIONS_PLUS(1),
+    P9_XIP_SECTION_SBE_TEXT       = P9_XIP_SECTIONS_PLUS(2),
+    P9_XIP_SECTION_SBE_DATA       = P9_XIP_SECTIONS_PLUS(3),
+    P9_XIP_SECTION_SBE_BASE       = P9_XIP_SECTIONS_PLUS(4),
+    P9_XIP_SECTION_SBE_BASELOADER = P9_XIP_SECTIONS_PLUS(5),
+    P9_XIP_SECTION_SBE_OVERRIDES  = P9_XIP_SECTIONS_PLUS(6),
+    P9_XIP_SECTION_SBE_RINGS      = P9_XIP_SECTIONS_PLUS(7),
+    P9_XIP_SECTION_SBE_OVERLAYS   = P9_XIP_SECTIONS_PLUS(8),
+    P9_XIP_SECTION_SBE_HBBL       = P9_XIP_SECTIONS_PLUS(9),
+    P9_XIP_SECTIONS_SBE           = P9_XIP_SECTIONS_PLUS(10) // # sections
+} p9_xip_section_sbe_t;
+
+#define P9_XIP_SECTION_NAMES_SBE(var)    \
+    P9_XIP_SECTION_NAMES(var,            \
+                         ".loader_text", \
+                         ".loader_data", \
+                         ".text",        \
+                         ".data",        \
+                         ".base",        \
+                         ".baseloader",  \
+                         ".overrides",   \
+                         ".rings",       \
+                         ".overlays",    \
+                         ".hbbl")
+
+/**************************************************************************/
+/* Hardware Image                                                         */
+/**************************************************************************/
+
+typedef enum
+{
+    P9_XIP_SECTION_HW_SGPE      = P9_XIP_SECTIONS_PLUS(0),
+    P9_XIP_SECTION_HW_RESTORE   = P9_XIP_SECTIONS_PLUS(1),
+    P9_XIP_SECTION_HW_CME       = P9_XIP_SECTIONS_PLUS(2),
+    P9_XIP_SECTION_HW_PGPE      = P9_XIP_SECTIONS_PLUS(3),
+    P9_XIP_SECTION_HW_IOPPE     = P9_XIP_SECTIONS_PLUS(4),
+    P9_XIP_SECTION_HW_FPPE      = P9_XIP_SECTIONS_PLUS(5),
+    P9_XIP_SECTION_HW_RINGS     = P9_XIP_SECTIONS_PLUS(6),
+    P9_XIP_SECTIONS_HW          = P9_XIP_SECTIONS_PLUS(7) // # sections
+} p9_xip_section_hw_t;
+
+#define P9_XIP_SECTION_NAMES_HW(var)      \
+    P9_XIP_SECTION_NAMES(var,             \
+                         ".sgpe",         \
+                         ".core_restore", \
+                         ".cme",          \
+                         ".pgpe",         \
+                         ".ioppe",        \
+                         ".fppe",         \
+                         ".rings")
+
+/**************************************************************************/
+/* SGPE Image                                                             */
+/**************************************************************************/
+
+typedef enum
+{
+    P9_XIP_SECTION_SGPE_QPMR     = P9_XIP_SECTIONS_PLUS(0),
+    P9_XIP_SECTION_SGPE_LVL1_BL  = P9_XIP_SECTIONS_PLUS(1),
+    P9_XIP_SECTION_SGPE_LVL2_BL  = P9_XIP_SECTIONS_PLUS(2),
+    P9_XIP_SECTION_SGPE_HCODE    = P9_XIP_SECTIONS_PLUS(3),
+    P9_XIP_SECTIONS_SGPE         = P9_XIP_SECTIONS_PLUS(4) // # sections
+} p9_xip_section_sgpe_t;
+
+#define P9_XIP_SECTION_NAMES_SGPE(var)         \
+    P9_XIP_SECTION_NAMES(var,                  \
+                         ".qpmr",              \
+                         ".lvl1_bl",           \
+                         ".lvl2_bl",           \
+                         ".hcode")
+
+/**************************************************************************/
+/* Core Restore Image                                                     */
+/**************************************************************************/
+
+typedef enum
+{
+    P9_XIP_SECTION_RESTORE_CPMR = P9_XIP_SECTIONS_PLUS(0),
+    P9_XIP_SECTION_RESTORE_SELF = P9_XIP_SECTIONS_PLUS(1),
+    P9_XIP_SECTIONS_RESTORE     = P9_XIP_SECTIONS_PLUS(2) // # sections
+} p9_xip_section_restore_t;
+
+#define P9_XIP_SECTION_NAMES_RESTORE(var)    \
+    P9_XIP_SECTION_NAMES(var,                \
+                         ".cpmr",            \
+                         ".self_restore")
+
+/**************************************************************************/
+/* CME Image                                                             */
+/**************************************************************************/
+
+typedef enum
+{
+    P9_XIP_SECTION_CME_HCODE     = P9_XIP_SECTIONS_PLUS(0),
+    P9_XIP_SECTIONS_CME          = P9_XIP_SECTIONS_PLUS(1) // # sections
+} p9_xip_section_cme_t;
+
+#define P9_XIP_SECTION_NAMES_CME(var)          \
+    P9_XIP_SECTION_NAMES(var,                  \
+                         ".hcode")
+
+/**************************************************************************/
+/* PGPE Image                                                             */
+/**************************************************************************/
+
+typedef enum
+{
+    P9_XIP_SECTION_PGPE_LVL1_BL  = P9_XIP_SECTIONS_PLUS(0),
+    P9_XIP_SECTION_PGPE_LVL2_BL  = P9_XIP_SECTIONS_PLUS(1),
+    P9_XIP_SECTION_PGPE_HCODE    = P9_XIP_SECTIONS_PLUS(2),
+    P9_XIP_SECTIONS_PGPE         = P9_XIP_SECTIONS_PLUS(3) // # sections
+} p9_xip_section_pgpe_t;
+
+#define P9_XIP_SECTION_NAMES_PGPE(var)         \
+    P9_XIP_SECTION_NAMES(var,                  \
+                         ".lvl1_bl",           \
+                         ".lvl2_bl",           \
+                         ".hcode")
+
+/**************************************************************************/
+/* IOPPE Image                                                            */
+/**************************************************************************/
+
+typedef enum
+{
+    P9_XIP_SECTIONS_IOPPE = P9_XIP_SECTIONS_PLUS(0) // # sections
+} p9_xip_section_ioppe_t;
+
+#define P9_XIP_SECTION_NAMES_IOPPE(var) \
+    P9_XIP_SECTION_NAMES(var)
+
+/**************************************************************************/
+/* FPPE Image                                                             */
+/**************************************************************************/
+
+typedef enum
+{
+    P9_XIP_SECTIONS_FPPE = P9_XIP_SECTIONS_PLUS(0) // # sections
+} p9_xip_section_fppe_t;
+
+#define P9_XIP_SECTION_NAMES_FPPE(var) \
+    P9_XIP_SECTION_NAMES(var)
+
+
+#endif  /* !__ASSEMBLER__ */
+
+#endif  // __P9_XIP_IMAGE_H
+
+// *INDENT-ON*
diff --git a/src/import/chips/p9/xip/p9_xip_tool.C b/src/import/chips/p9/xip/p9_xip_tool.C
new file mode 100644
index 00000000..dd48e250
--- /dev/null
+++ b/src/import/chips/p9/xip/p9_xip_tool.C
@@ -0,0 +1,2594 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/chips/p9/xip/p9_xip_tool.C $                           */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+/// \file p9_xip_tool.c
+/// \brief P9-XIP image search/edit tool
+///
+/// Note: This file was originally stored under .../procedures/ipl/sbe.  It
+/// was moved here at version 1.19.
+
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+
+#include <errno.h>
+#include <fcntl.h>
+#include <regex.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#define __PPE__
+
+#include "p9_xip_image.h"
+#ifdef XIP_TOOL_ENABLE_DISSECT
+    #include "p9_tor.H"
+    #include "p9_scan_compression.H"
+    using namespace P9_TOR;
+#endif
+
+#define LINE_SIZE_MAX  1024     // Max size of a single snprintf dump.
+#define RING_BUF_SIZE_MAX  1000000
+
+// Listing mode IDs:
+//
+enum LISTING_MODE_ID
+{
+    LMID_SHORT  = 0,
+    LMID_NORMAL = 1, // default
+    LMID_LONG   = 2
+};
+
+// Usage: p9_xip_tool <image> [-<flag> ...] normalize
+//        p9_xip_tool <image> [-<flag> ...] get <item>
+//        p9_xip_tool <image> [-<flag> ...] getv <item> <index>
+//        p9_xip_tool <image> [-<flag> ...] set <item> <value> [ <item1> <value1> ... ]
+//        p9_xip_tool <image> [-<flag> ...] setv <item> <index> <value> [ <item1> <index1> <value1> ... ]
+//        p9_xip_tool <image> [-<flag> ...] report [<regex>]
+//        p9_xip_tool <image> [-<flag> ...] attrdump <attr dump file>
+//        p9_xip_tool <image> [-<flag> ...] append <section> <file>
+//        p9_xip_tool <image> [-<flag> ...] extract <section> <file>
+//        p9_xip_tool <image> [-<flag> ...] delete <section> [ <section1> ... <sectionN> ]
+//        p9_xip_tool <image> [-<flag> ...] dissect <ring section> [short,normal(default),long]
+//        p9_xip_tool <image> [-<flag> ...] disasm <text section>
+//
+// This simple application uses the P9-XIP image APIs to normalize, search
+// update and edit P9-XIP images. This program encapsulates several commands
+// in a common command framework which requires an image to operate on, a
+// command name, and command arguments that vary by command.  Commands that
+// modify the image always rewrite the image in-place in the filesystem;
+// however the original image is only modified if the command has completed
+// without error.
+//
+// The program operates on a P9-XIP format binary image, which must be
+// normalized - unless the tool is being called to normalize the image in the
+// first place using the 'normalize' command. The tool also validates the
+// image prior to operating on the image.
+//
+// The 'get' command retrieves a scalar value from the image and prints its
+// representation on stdout (followed by a newline).  Scalar integer values
+// and image addresses are printed as hex numbers (0x...).  Strings are printed
+// verbatim.
+//
+// The 'getv' command retrieves a vector element from the image and prints its
+// representation on stdout (followed by a newline).  Integer values
+// and image addresses are printed as hex numbers (0x...).  Vectors of strings
+// are not supported.
+//
+// The 'set' command allows setting integer and string values in the image.
+// New integer values can be specified in decimal or hex (0x...).  Strings are
+// taken verbatim from the command line.  Note that new string values will be
+// silently truncated to the length of the current string if the new value is
+// longer than the current string. Updating address values is currently not
+// supported.  Any number of item/value pairs can be specified with a single
+// 'set' command.
+//
+// The 'setv' command is provided to set individual vector elements of
+// integral arrays.
+//
+// The 'report' command prints a report including a dump of the header and
+// section table, a listing of the types and values of all items that appear
+// in the TOC. The TOC listing includes the
+// sequence number of the entry in the TOC, the item name, the item type and
+// the item value.
+//
+// The 'attrdump' command prints a listing of the names, types and values
+// of all attribute items that appear in the TOC and their value from
+// the attribute dump file
+//
+// The 'append' command either creates or extends the section named by the
+// section argument, by appending the contents of the named file verbatim.
+// Currently the section must either be the final (highest address) section of
+// the image, or must be empty, in which case the append command creates the
+// section as the final section of the image. The 'append' command writes the
+// relocatable image address where the input file was loaded to stdout.
+//
+// The 'extract' command extracts a sections from the binary image.
+//
+// The 'delete' command deletes 0 or more sections, starting with <section0>.
+// Each section to be deleted must either be the final (highest address)
+// section of the image at the time it is deleted, or must be empty. The
+// 'delete' command writes the size of the final modified image to stdout.
+//
+// The 'dissect' command dissects the ring section named by the section argument
+// and summarizes the content of the ring section.  The second argument to
+// 'dissect', i.e. [short,normal(default),long], specifies how much information
+// is included in the listing:
+//   short:  The bare necessities.
+//   normal: Everything but a raw binary dump of the actual ring block.
+//   long:   Everything inclusing a raw binary dump of the actual ring block.
+// Note that iff the second argument is omitted, a 'normal' listing of the ring
+// section will occur.
+//
+// The 'disasm' command disassembles the section named by the section argument.
+//
+// The following -i<flag> are supported:
+// -ifs
+//    causes the validation step to ignore image size check against the file
+//    size.
+// -iv
+//    causes all validation checking to be ignored. (Skips validation step.)
+
+const char* g_usage =
+    "Usage: p9_xip_tool <image> [-i<flag> ...] normalize\n"
+    "       p9_xip_tool <image> [-i<flag> ...] get <item>\n"
+    "       p9_xip_tool <image> [-i<flag> ...] getv <item> <index>\n"
+    "       p9_xip_tool <image> [-i<flag> ...] set <item> <value> [ <item1> <value1> ... ]\n"
+    "       p9_xip_tool <image> [-i<flag> ...] setv <item> <index> <value> [ <item1> <index1> <value1> ... ]\n"
+    "       p9_xip_tool <image> [-i<flag> ...] report [<regex>]\n"
+    "       p9_xip_tool <image> [-i<flag> ...] attrdump <attr dump file>\n"
+    "       p9_xip_tool <image> [-i<flag> ...] append <section> <file>\n"
+    "       p9_xip_tool <image> [-i<flag> ...] extract <section> <file>\n"
+    "       p9_xip_tool <image> [-i<flag> ...] delete <section> [ <section1> ... <sectionN> ]\n"
+    "       p9_xip_tool <image> [-i<flag> ...] dis <section>\n"
+    "       p9_xip_tool <image> [-i<flag> ...] dissect <ring section> [short,normal(default),long]\n"
+    "       p9_xip_tool <image> [-i<flag> ...] disasm <text section>\n"
+    "\n"
+    "This simple application uses the P9-XIP image APIs to normalize, search\n"
+    "update and edit P9-XIP images. This program encapsulates several commands\n"
+    "in a common command framework which requires an image to operate on, a\n"
+    "command name, and command arguments that vary by command.  Commands that\n"
+    "modify the image always rewrite the image in-place in the filesystem;\n"
+    "however the original image is only modified if the command has completed\n"
+    "without error.\n"
+    "\n"
+    "The program operates on a P9-XIP format binary image, which must be\n"
+    "normalized - unless the tool is being called to normalize the image in the\n"
+    "first place using the 'normalize' command. The tool also validates the\n"
+    "image prior to operating on the image.\n"
+    "\n"
+    "The 'get' command retrieves a scalar value from the image and prints its\n"
+    "representation on stdout (followed by a newline).  Scalar integer values\n"
+    "and image addresses are printed as hex numbers (0x...).  Strings are printed\n"
+    "verbatim.\n"
+    "\n"
+    "The 'getv' command retrieves a vector element from the image and prints its\n"
+    "representation on stdout (followed by a newline).  Integer values\n"
+    "and image addresses are printed as hex numbers (0x...).  Vectors of strings\n"
+    "are not supported.\n"
+    "\n"
+    "The 'set' command allows setting integer and string values in the image.\n"
+    "New integer values can be specified in decimal or hex (0x...).  Strings are\n"
+    "taken verbatim from the command line.  Note that new string values will be\n"
+    "silently truncated to the length of the current string if the new value is\n"
+    "longer than the current string. Updating address values is currently not\n"
+    "supported.  Any number of item/value pairs can be specified with a single\n"
+    "'set' command.\n"
+    "\n"
+    "The 'setv' command is provided to set individual vector elements of\n"
+    "integral arrays.\n"
+    "\n"
+    "The 'report' command prints a report including a dump of the header and\n"
+    "section table, a listing of the types and values of all items that appear\n"
+    "in the TOC. The TOC listing includes the\n"
+    "sequence number of the entry in the TOC, the item name, the item type and\n"
+    "the item value.\n"
+    "\n"
+    "The 'attrdump' command prints a listing of the names, types and values\n"
+    "of all attribute items that appear in the TOC and their value from \n"
+    "the attribute dump file\n"
+    "\n"
+    "The 'append' command either creates or extends the section named by the\n"
+    "section argument, by appending the contents of the named file verbatim.\n"
+    "Currently the section must either be the final (highest address) section of\n"
+    "the image, or must be empty, in which case the append command creates the\n"
+    "section as the final section of the image. The 'append' command writes the\n"
+    "relocatable image address where the input file was loaded to stdout.\n"
+    "\n"
+    "The 'extract' command extracs a sections from a binary image.\n"
+    "\n"
+    "The 'delete' command deletes 0 or more sections, starting with <section0>.\n"
+    "Each section to be deleted must either be the final (highest address)\n"
+    "section of the image at the time it is deleted, or must be empty. The\n"
+    "'delete' command writes the size of the final modified image to stdout.\n"
+    "\n"
+    "The 'dissect' command dissects the ring section named by the section argument\n"
+    "and summarizes the content of the ring section.  The second argument to\n"
+    "'dissect', i.e. [short,normal(default),long], specifies how much information\n"
+    "is included in the listing:\n"
+    "   short:  The bare necessities.\n"
+    "   normal: Everything but a raw binary dump of the actual ring block.\n"
+    "   long:   Everything inclusing a raw binary dump of the actual ring block.\n"
+    "Note that iff the second argument is omitted, a 'normal' listing of the ring\n"
+    "section will occur.\n"
+    "\n"
+    "The 'disasm' command disassembles the text section named by the section\n"
+    "argument.\n"
+    "\n"
+    "-i<flag>:\n"
+    "\t-ifs  Causes the validation step to ignore image size check against the\n"
+    "\tfile size.\n"
+    "\t-iv   Causes all validation checking to be ignored.\n"
+    ;
+
+P9_XIP_ERROR_STRINGS(g_errorStrings);
+P9_XIP_TYPE_STRINGS(g_typeStrings);
+P9_XIP_TYPE_ABBREVS(g_typeAbbrevs);
+
+P9_XIP_SECTION_NAMES_HW(g_sectionNamesHw);
+P9_XIP_SECTION_NAMES_SGPE(g_sectionNamesSgpe);
+P9_XIP_SECTION_NAMES_RESTORE(g_sectionNamesRestore);
+P9_XIP_SECTION_NAMES_CME(g_sectionNamesCme);
+P9_XIP_SECTION_NAMES_PGPE(g_sectionNamesPgpe);
+P9_XIP_SECTION_NAMES_IOPPE(g_sectionNamesIoppe);
+P9_XIP_SECTION_NAMES_FPPE(g_sectionNamesFppe);
+P9_XIP_SECTION_NAMES_SBE(g_sectionNamesSbe);
+
+// Disassembler error support.
+DIS_ERROR_STRINGS(g_errorStringsDis);
+
+#define ERRBUF_SIZE 60
+
+typedef struct
+{
+    int index;
+    int regex;
+    regex_t preg;
+} ReportControl;
+
+off_t g_imageSize;
+
+
+// Determine name of section given by its index in section table
+
+static inline const char* get_sectionName(uint64_t magic, int index)
+{
+    switch (magic)
+    {
+//      case P9_XIP_MAGIC_BASE:
+//          FIXME
+//          break;
+//      case P9_XIP_MAGIC_CENTAUR:
+//          FIXME
+//          break;
+        case P9_XIP_MAGIC_SEEPROM:
+            return P9_XIP_SECTION_NAME(g_sectionNamesSbe, index);
+
+        case P9_XIP_MAGIC_HW:
+            return P9_XIP_SECTION_NAME(g_sectionNamesHw, index);
+
+        case P9_XIP_MAGIC_SGPE:
+            return P9_XIP_SECTION_NAME(g_sectionNamesSgpe, index);
+
+        case P9_XIP_MAGIC_RESTORE:
+            return P9_XIP_SECTION_NAME(g_sectionNamesRestore, index);
+
+        case P9_XIP_MAGIC_CME:
+            return P9_XIP_SECTION_NAME(g_sectionNamesCme, index);
+
+        case P9_XIP_MAGIC_PGPE:
+            return P9_XIP_SECTION_NAME(g_sectionNamesPgpe, index);
+
+        case P9_XIP_MAGIC_IOPPE:
+            return P9_XIP_SECTION_NAME(g_sectionNamesIoppe, index);
+
+        case P9_XIP_MAGIC_FPPE:
+            return P9_XIP_SECTION_NAME(g_sectionNamesFppe, index);
+    }
+
+    return "";
+}
+
+// Determine index of section given by its name in section table
+
+static inline int get_sectionId(uint64_t i_magic, const char* i_section)
+{
+    int i;
+
+    for (i = 0; i < P9_XIP_SECTIONS; i++)
+        if (strcmp(i_section, get_sectionName(i_magic, i)) == 0)
+        {
+            return i;
+        }
+
+    return -1;
+}
+
+// Normalize a P9-XIP image.  We normalize a copy of the image first so that
+// the original image will be available for debugging in case the
+// normalization fails, then validate and copy the normalized image back to
+// the mmap()-ed file.
+
+int
+normalize(void* io_image, const int i_argc, const char** i_argv, uint32_t i_maskIgnores)
+{
+    int rc;
+    void* copy;
+
+    do
+    {
+
+        // The 'normalize' command takes no arguments
+
+        if (i_argc != 0)
+        {
+            fprintf(stderr, g_usage);
+            exit(1);
+        }
+
+        copy = malloc(g_imageSize);
+
+        if (copy == 0)
+        {
+            perror("malloc() failed : ");
+            exit(1);
+        }
+
+        memcpy(copy, io_image, g_imageSize);
+
+        rc = p9_xip_normalize(copy);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if ( !(i_maskIgnores & P9_XIP_IGNORE_ALL) )
+        {
+            rc = p9_xip_validate2(copy, g_imageSize, i_maskIgnores);
+        }
+
+        if (rc)
+        {
+            break;
+        }
+
+        memcpy(io_image, copy, g_imageSize);
+
+    }
+    while (0);
+
+    return rc;
+}
+
+
+// Print a line of a report, listing the index, symbol, type and current
+// value.
+
+int
+tocListing(void* io_image,
+           const P9XipItem* i_item,
+           void* arg)
+{
+    int rc;
+    ReportControl* control;
+    uint64_t data;
+    char* s;
+
+    control = (ReportControl*)arg;
+
+    do
+    {
+        rc = 0;
+
+        if (control->regex)
+        {
+            if (regexec(&(control->preg), i_item->iv_id, 0, 0, 0))
+            {
+                break;
+            }
+        }
+
+        printf("0x%04x | %-42s | %s | ",
+               control->index, i_item->iv_id,
+               P9_XIP_TYPE_STRING(g_typeAbbrevs, i_item->iv_type));
+
+        switch (i_item->iv_type)
+        {
+            case P9_XIP_UINT8:
+                rc = p9_xip_get_scalar(io_image, i_item->iv_id, &data);
+
+                if (rc)
+                {
+                    break;
+                }
+
+                printf("0x%02x", (uint8_t)data);
+                break;
+
+            case P9_XIP_UINT16:
+                rc = p9_xip_get_scalar(io_image, i_item->iv_id, &data);
+
+                if (rc)
+                {
+                    break;
+                }
+
+                printf("0x%04x", (uint16_t)data);
+                break;
+
+            case P9_XIP_UINT32:
+                rc = p9_xip_get_scalar(io_image, i_item->iv_id, &data);
+
+                if (rc)
+                {
+                    break;
+                }
+
+                printf("0x%08x", (uint32_t)data);
+                break;
+
+            case P9_XIP_UINT64:
+                rc = p9_xip_get_scalar(io_image, i_item->iv_id, &data);
+
+                if (rc)
+                {
+                    break;
+                }
+
+                printf("0x%016lx", data);
+                break;
+
+            case P9_XIP_INT8:
+                rc = p9_xip_get_scalar(io_image, i_item->iv_id, &data);
+
+                if (rc)
+                {
+                    break;
+                }
+
+                printf("0x%02x", (uint8_t)data);
+                break;
+
+            case P9_XIP_INT16:
+                rc = p9_xip_get_scalar(io_image, i_item->iv_id, &data);
+
+                if (rc)
+                {
+                    break;
+                }
+
+                printf("0x%04x", (uint16_t)data);
+                break;
+
+            case P9_XIP_INT32:
+                rc = p9_xip_get_scalar(io_image, i_item->iv_id, &data);
+
+                if (rc)
+                {
+                    break;
+                }
+
+                printf("0x%08x", (uint32_t)data);
+                break;
+
+            case P9_XIP_INT64:
+                rc = p9_xip_get_scalar(io_image, i_item->iv_id, &data);
+
+                if (rc)
+                {
+                    break;
+                }
+
+                printf("0x%016lx", data);
+                break;
+
+            case P9_XIP_STRING:
+                rc = p9_xip_get_string(io_image, i_item->iv_id, &s);
+
+                if (rc)
+                {
+                    break;
+                }
+
+                printf("%s", s);
+                break;
+
+            case P9_XIP_ADDRESS:
+                rc = p9_xip_get_scalar(io_image, i_item->iv_id, &data);
+
+                if (rc)
+                {
+                    break;
+                }
+
+                printf("0x%04x:0x%08x",
+                       (uint16_t)((data >> 32) & 0xffff),
+                       (uint32_t)(data & 0xffffffff));
+                break;
+
+            default:
+                printf("unknown type\n");
+                rc = P9_XIP_BUG;
+                break;
+        }
+
+        printf("\n");
+    }
+    while (0);
+
+    control->index += 1;
+    return rc;
+}
+
+// Print a line of attribute report, listing the symbol, type and current
+// value.
+int
+attrListing(const P9XipItem* i_item)
+{
+    int rc = 0;
+    uint64_t data = 0;
+
+    if (i_item->iv_address == 0)
+    {
+        //TOC item not present in fixed section
+        return rc;
+    }
+
+    printf("%-42s | %s | ", i_item->iv_id,
+           P9_XIP_TYPE_STRING(g_typeAbbrevs, i_item->iv_type));
+
+    rc = p9_xip_get_item(i_item, &data);
+
+    if (rc)
+    {
+        return rc;
+    }
+
+    switch (i_item->iv_type)
+    {
+        case P9_XIP_UINT8:
+            printf("0x%02x", (uint8_t)data);
+            break;
+
+        case P9_XIP_UINT16:
+            printf("0x%04x", (uint16_t)data);
+            break;
+
+        case P9_XIP_UINT32:
+            printf("0x%08x", (uint32_t)data);
+            break;
+
+        case P9_XIP_UINT64:
+            printf("0x%016lx", data);
+            break;
+
+        case P9_XIP_INT8:
+            printf("0x%02x", (uint8_t)data);
+            break;
+
+        case P9_XIP_INT16:
+            printf("0x%04x", (uint16_t)data);
+            break;
+
+        case P9_XIP_INT32:
+            printf("0x%08x", (uint32_t)data);
+            break;
+
+        case P9_XIP_INT64:
+            printf("0x%016lx", data);
+            break;
+
+        case P9_XIP_STRING:
+            printf("%s", (char*)(i_item->iv_imageData));
+            break;
+
+        case P9_XIP_ADDRESS:
+            printf("0x%04x:0x%08x",
+                   (uint16_t)((data >> 32) & 0xffff),
+                   (uint32_t)(data & 0xffffffff));
+            break;
+
+        default:
+            printf("unknown type\n");
+            rc = P9_XIP_BUG;
+            break;
+    }
+
+    printf("\n");
+
+    return rc;
+}
+
+// Dump the image header, including the section table
+
+int
+dumpHeader(void* i_image)
+{
+    int i;
+    P9XipHeader header;
+    P9XipSection* section;
+    char magicString[9];
+
+    // Dump header information. Since the TOC may not exist we need to get
+    // the information from the header explicitly.
+
+    p9_xip_translate_header(&header, (P9XipHeader*)i_image);
+
+    memcpy(magicString, (char*)(&(((P9XipHeader*)i_image)->iv_magic)), 8);
+    magicString[8] = 0;
+
+    printf("Magic Number   : 0x%016lx \"%s\"\n",
+           header.iv_magic, magicString);
+    printf("Header Version : 0x%02x\n", header.iv_headerVersion);
+    printf("Link Address   : 0x%016lx\n", header.iv_linkAddress);
+    printf("L1 Loader Address   : 0x%08x\n", (uint32_t)header.iv_L1LoaderAddr);
+    printf("L2 Loader Address   : 0x%08x\n", (uint32_t)header.iv_L2LoaderAddr);
+    printf("Kernel Address   : 0x%08x\n", (uint32_t)header.iv_kernelAddr);
+    printf("Image Size     : 0x%08x (%d)\n",
+           header.iv_imageSize, header.iv_imageSize);
+    printf("Normalized     : %s\n", header.iv_normalized ? "Yes" : "No");
+    printf("TOC Sorted     : %s\n", header.iv_tocSorted ? "Yes" : "No");
+    printf("Build Date     : %02d/%02d/%04d\n",
+           (header.iv_buildDate / 100) % 100,
+           header.iv_buildDate % 100,
+           header.iv_buildDate / 10000);
+    printf("Build Time     : %02d:%02d\n",
+           header.iv_buildTime / 100,
+           header.iv_buildTime % 100);
+    printf("Build User     : %s\n", header.iv_buildUser);
+    printf("Build Host     : %s\n", header.iv_buildHost);
+    printf("\n");
+
+    printf("Section Table  :   Offset      Size\n");
+    printf("\n");
+
+    for (i = 0; i < P9_XIP_SECTIONS; i++)
+    {
+        section = &(header.iv_section[i]);
+        printf("%-16s 0x%08x 0x%08x (%d)\n",
+               get_sectionName(header.iv_magic, i),
+               section->iv_offset, section->iv_size, section->iv_size);
+    }
+
+    printf("\n");
+
+    return 0;
+}
+
+
+// Print a report
+
+int
+report(void* io_image, const int i_argc, const char** i_argv)
+{
+    int rc;
+    ReportControl control;
+    char errbuf[ERRBUF_SIZE];
+
+    do
+    {
+
+        // Basic syntax check : [<regexp>]
+
+        if (i_argc > 1)
+        {
+            fprintf(stderr, g_usage);
+            exit(1);
+        }
+
+        // Compile a regular expression if supplied
+
+        if (i_argc == 1)
+        {
+            rc = regcomp(&(control.preg), i_argv[0], REG_NOSUB);
+
+            if (rc)
+            {
+                regerror(rc, &(control.preg), errbuf, ERRBUF_SIZE);
+                fprintf(stderr, "Error from regcomp() : %s\n", errbuf);
+                exit(1);
+            }
+
+            control.regex = 1;
+        }
+        else
+        {
+            control.regex = 0;
+
+            dumpHeader(io_image);
+            printf("TOC Report\n\n");
+        }
+
+        // Map the TOC with the mapReport() function
+
+        control.index = 0;
+        rc = p9_xip_map_toc(io_image, tocListing, (void*)(&control));
+
+        if (rc)
+        {
+            break;
+        }
+
+    }
+    while (0);
+
+    return rc;
+}
+
+//Print attributes from dump image
+int
+reportAttr(void* io_image, size_t i_imageSize, void* io_dump)
+{
+    int rc = 0;
+    P9XipToc* imageToc = NULL;
+    P9XipItem item = {0};
+    size_t entries = 0;
+
+    //check for seeprom image validity
+    rc = p9_xip_validate(io_image, i_imageSize);
+
+    if (rc)
+    {
+        return rc;
+    }
+
+    //get toc listing from seeprom image
+    rc = p9_xip_get_toc(io_image, &imageToc, &entries, 0, 0);
+
+    if (rc)
+    {
+        return rc;
+    }
+
+    //loop through each toc listing and print its value from pibmem dump
+    for (; entries--; imageToc++)
+    {
+        rc = p9_xip_decode_toc_dump(io_image, io_dump, imageToc, &item);
+
+        if (!rc)
+        {
+            //helper function to print the attributes
+            attrListing(&item);
+        }
+    }
+
+    return rc;
+}
+
+// Set a scalar or vector element values in the image.  The 'i_setv' argument
+// indicates set/setv (0/1).
+
+int
+set(void* io_image, const int i_argc, const char** i_argv, int i_setv)
+{
+    int rc = P9_XIP_BUG, arg, base, clause_args, index_val;
+    P9XipItem item;
+    unsigned long long newValue;
+    const char* key, *index, *value;
+    char* endptr;
+
+    do
+    {
+
+        // Basic syntax check: <item> <value> [ <item1> <value1> ... ]
+        // Basic syntax check: <item> <index> <value> [ <item1> <index1> <value1> ... ]
+
+        clause_args = (i_setv ? 3 : 2);
+
+        if ((i_argc % clause_args) != 0)
+        {
+            fprintf(stderr, g_usage);
+            exit(1);
+        }
+
+        for (arg = 0; arg < i_argc; arg += clause_args)
+        {
+
+            key = i_argv[arg];
+
+            if (i_setv)
+            {
+                index = i_argv[arg + 1];
+                index_val = strtol(index, 0, 0);
+                value = i_argv[arg + 2];
+            }
+            else
+            {
+                index = "";
+                index_val = 0;
+                value = i_argv[arg + 1];
+            }
+
+            // Search for the item to see what type of data it expects, then
+            // case split on the type.
+
+            rc = p9_xip_find(io_image, key, &item);
+
+            if (rc)
+            {
+                break;
+            }
+
+            if (index_val < 0)
+            {
+                fprintf(stderr,
+                        "Illegal negative vector index %s for %s\n",
+                        index, key);
+                exit(1);
+            }
+            else if ((item.iv_elements != 0) &&
+                     (index_val >= item.iv_elements))
+            {
+                fprintf(stderr,
+                        "Index %s out-of-bounds for %s (%d elements)\n",
+                        index, key, item.iv_elements);
+                exit(1);
+            }
+
+            switch (item.iv_type)
+            {
+                case P9_XIP_UINT8:
+                case P9_XIP_UINT16:
+                case P9_XIP_UINT32:
+                case P9_XIP_UINT64:
+
+                    // We need to do a bit of preprocessing on the string to
+                    // determine its format and set the base for strtoull(),
+                    // otherwise strtoull() will be confused by leading zeros
+                    // e.g. in time strings generated by `date +%H%M`, and try to
+                    // process the string as octal.
+
+                    if ((strlen(value) >= 2) && (value[0] == '0') &&
+                        ((value[1] == 'x') || (value[1] == 'X')))
+                    {
+                        base = 16;
+                    }
+                    else
+                    {
+                        base = 10;
+                    }
+
+                    errno = 0;
+                    newValue = strtoull(value, &endptr, base);
+
+                    if ((errno != 0) || (endptr != (value + strlen(value))))
+                    {
+                        fprintf(stderr,
+                                "Error parsing putative integer value : %s\n",
+                                value);
+                        exit(1);
+                    }
+
+                    switch (item.iv_type)
+                    {
+
+                        case P9_XIP_UINT8:
+                            if ((uint8_t)newValue != newValue)
+                            {
+                                fprintf(stderr,
+                                        "Value 0x%016llx too large for 8-bit type\n",
+                                        newValue);
+                                exit(1);
+                            }
+
+                            break;
+
+                        case P9_XIP_UINT16:
+                            if ((uint16_t)newValue != newValue)
+                            {
+                                fprintf(stderr,
+                                        "Value 0x%016llx too large for 16-bit type\n",
+                                        newValue);
+                                exit(1);
+                            }
+
+                            break;
+
+                        case P9_XIP_UINT32:
+                            if ((uint32_t)newValue != newValue)
+                            {
+                                fprintf(stderr,
+                                        "Value 0x%016llx too large for 32-bit type\n",
+                                        newValue);
+                                exit(1);
+                            }
+
+                            break;
+
+                        case P9_XIP_UINT64:
+                            break;
+
+                        default:
+                            break;
+                    }
+
+                    rc = p9_xip_set_element(io_image, key, index_val, newValue);
+
+                    if (rc)
+                    {
+                        rc = P9_XIP_BUG;
+                    }
+
+                    break;
+
+                case P9_XIP_STRING:
+
+                    if (i_setv)
+                    {
+                        fprintf(stderr, "Can't use 'setv' for string data %s\n",
+                                key);
+                        exit(1);
+                    }
+
+                    rc = p9_xip_set_string(io_image, key, (char*)value);
+
+                    if (rc)
+                    {
+                        rc = P9_XIP_BUG;
+                    }
+
+                    break;
+
+                case P9_XIP_INT8:
+                case P9_XIP_INT16:
+                case P9_XIP_INT32:
+                case P9_XIP_INT64:
+                    fprintf(stderr,
+                            "Item %s has int type %s, "
+                            "which is not supported for '%s'.\n",
+                            i_argv[arg],
+                            P9_XIP_TYPE_STRING(g_typeStrings, item.iv_type),
+                            (i_setv ? "setv" : "set"));
+                    exit(1);
+                    break;
+
+                default:
+                    fprintf(stderr,
+                            "Item %s has type %s, "
+                            "which is not supported for '%s'.\n",
+                            i_argv[arg],
+                            P9_XIP_TYPE_STRING(g_typeStrings, item.iv_type),
+                            (i_setv ? "setv" : "set"));
+                    exit(1);
+                    break;
+            }
+
+            if (rc)
+            {
+                break;
+            }
+
+        }
+    }
+    while (0);
+
+    //if good rc, we need to msync the mmaped file to push contents to
+    //the actual file. Per man page this is required although some
+    //file systems (notably AFS) don't seem to require (GSA does)
+    if(!rc)
+    {
+        uint8_t i = 0;
+
+        do
+        {
+            rc = msync(io_image, g_imageSize , MS_SYNC);
+
+            if(rc)
+            {
+                i++;
+                fprintf(stderr,
+                        "msync failed with errno %d\n", errno);
+            }
+        }
+        while(rc && i < 5);
+
+        if(rc)
+        {
+            exit(3);
+        }
+    }
+
+    return rc;
+}
+
+
+// Get a value from the image, and return on stdout.  The 'i_getv' argument
+// indicates get/getv (0/1)
+
+int
+get(void* i_image, const int i_argc, const char** i_argv, int i_getv)
+{
+    int rc, nargs, index_val;
+    P9XipItem item;
+    const char* key, *index;
+    uint64_t data;
+    char* s;
+
+    do
+    {
+
+        // Basic syntax check: <item>
+        // Basic syntax check: <item> <index>
+
+        nargs = (i_getv ? 2 : 1);
+
+        if (i_argc != nargs)
+        {
+            fprintf(stderr, g_usage);
+            exit(1);
+        }
+
+        key = i_argv[0];
+
+        if (i_getv)
+        {
+            index = i_argv[1];
+            index_val = strtol(index, 0, 0);
+        }
+        else
+        {
+            index = "";
+            index_val = 0;
+        }
+
+        // Search for the item to determine its type, then case split on the
+        // type.
+
+        rc = p9_xip_find(i_image, key, &item);
+
+        if (rc)
+        {
+            break;
+        }
+
+        if (index_val < 0)
+        {
+            fprintf(stderr,
+                    "Illegal negative vector index %s for %s\n",
+                    index, key);
+            exit(1);
+        }
+        else if ((item.iv_elements != 0) &&
+                 (index_val >= item.iv_elements))
+        {
+            fprintf(stderr, "Index %s out-of-bounds for %s (%d elements)\n",
+                    index, key, item.iv_elements);
+            exit(1);
+        }
+
+        switch (item.iv_type)
+        {
+
+            case P9_XIP_UINT8:
+            case P9_XIP_UINT16:
+            case P9_XIP_UINT32:
+            case P9_XIP_UINT64:
+                rc = p9_xip_get_element(i_image, key, index_val, &data);
+
+                if (rc)
+                {
+                    rc = P9_XIP_BUG;
+                    break;
+                }
+
+                switch (item.iv_type)
+                {
+                    case P9_XIP_UINT8:
+                        printf("0x%02x\n", (uint8_t)data);
+                        break;
+
+                    case P9_XIP_UINT16:
+                        printf("0x%04x\n", (uint16_t)data);
+                        break;
+
+                    case P9_XIP_UINT32:
+                        printf("0x%08x\n", (uint32_t)data);
+                        break;
+
+                    case P9_XIP_UINT64:
+                        printf("0x%016lx\n", data);
+                        break;
+
+                    default:
+                        break;
+                }
+
+                break;
+
+            case P9_XIP_ADDRESS:
+                if (i_getv)
+                {
+                    fprintf(stderr, "Can't use 'getv' for address data : %s\n",
+                            key);
+                    exit(1);
+                }
+
+                rc = p9_xip_get_scalar(i_image, key, &data);
+
+                if (rc)
+                {
+                    rc = P9_XIP_BUG;
+                    break;
+                }
+
+                printf("0x%012lx\n", data);
+                break;
+
+            case P9_XIP_STRING:
+                if (i_getv)
+                {
+                    fprintf(stderr, "Can't use 'getv' for string data : %s\n",
+                            key);
+                    exit(1);
+                }
+
+                rc = p9_xip_get_string(i_image, key, &s);
+
+                if (rc)
+                {
+                    rc = P9_XIP_BUG;
+                    break;
+                }
+
+                printf("%s\n", s);
+                break;
+
+            default:
+                fprintf(stderr, "%s%d : Bug, unexpected type %d\n",
+                        __FILE__, __LINE__, item.iv_type);
+                exit(1);
+                break;
+        }
+    }
+    while (0);
+
+    return rc;
+}
+
+
+// strtoul() with application-specific error handling
+
+unsigned long
+localStrtoul(const char* s)
+{
+    unsigned long v;
+    char* endptr;
+
+    errno = 0;
+    v = strtoul(s, &endptr, 0);
+
+    if ((errno != 0) || (endptr != (s + strlen(s))))
+    {
+        fprintf(stderr,
+                "Error parsing putative integer value : %s\n",
+                s);
+        exit(1);
+    }
+
+    return v;
+}
+
+
+// Append a file to section
+int
+append(const char* i_imageFile, const int i_imageFd, void* io_image,
+       int i_argc, const char** i_argv)
+{
+    int fileFd, newImageFd, sectionId, rc;
+    struct stat buf;
+    const char* section;
+    const char* file;
+    void* appendImage;
+    void* newImage;
+    uint32_t size, newSize, sectionOffset;
+    uint64_t homerAddress;
+    P9XipHeader header;
+
+    do
+    {
+
+        // Basic syntax check: <section> <file>
+
+        if (i_argc != 2)
+        {
+            fprintf(stderr, g_usage);
+            exit(1);
+        }
+
+        section = i_argv[0];
+        file = i_argv[1];
+
+        p9_xip_translate_header(&header, (P9XipHeader*)io_image);
+
+        // Translate the section name to a section Id
+        sectionId = get_sectionId(header.iv_magic, section);
+
+        if (sectionId < 0)
+        {
+            fprintf(stderr, "Unrecognized section name : '%s;\n", section);
+            exit(1);
+        }
+
+        // Open and mmap the file to be appended
+
+        fileFd = open(file, O_RDONLY);
+
+        if (fileFd < 0)
+        {
+            perror("open() of the file to be appended failed : ");
+            exit(1);
+        }
+
+        rc = fstat(fileFd, &buf);
+
+        if (rc)
+        {
+            perror("fstat() of the file to be appended failed : ");
+            exit(1);
+        }
+
+        appendImage = mmap(0, buf.st_size, PROT_READ, MAP_SHARED, fileFd, 0);
+
+        if (appendImage == MAP_FAILED)
+        {
+            perror("mmap() of the file to be appended failed : ");
+            exit(1);
+        }
+
+
+        // malloc() a buffer for the new image, adding space for alignment
+
+        rc = p9_xip_image_size(io_image, &size);
+
+        if (rc)
+        {
+            break;
+        }
+
+        newSize = size + buf.st_size + P9_XIP_MAX_SECTION_ALIGNMENT;
+
+        newImage = malloc(newSize);
+
+        if (newImage == 0)
+        {
+            fprintf(stderr, "Can't malloc() a buffer for the new image\n");
+            exit(1);
+        }
+
+
+        // Copy the image.  At this point the original image file must be
+        // closed.
+
+        memcpy(newImage, io_image, size);
+
+        rc = close(i_imageFd);
+
+        if (rc)
+        {
+            perror("close() of the original image file failed : ");
+            exit(1);
+        }
+
+
+        // Do the append and print the image address where the data was loaded.
+        // We will not fail for unaligned addresses, as we have no knowledge
+        // of whether or why the user wants the final image address.
+
+        rc = p9_xip_append(newImage, sectionId,
+                           appendImage, buf.st_size,
+                           newSize, &sectionOffset);
+
+        if (rc)
+        {
+            break;
+        }
+
+        rc = p9_xip_section2image(newImage, sectionId, sectionOffset,
+                                  &homerAddress);
+
+        if (rc && (rc != P9_XIP_ALIGNMENT_ERROR))
+        {
+            break;
+        }
+
+        printf("0x%016lx\n", homerAddress);
+
+
+        // Now write the new image back to the filesystem
+
+        newImageFd = open(i_imageFile, O_WRONLY | O_TRUNC);
+
+        if (newImageFd < 0)
+        {
+            perror("re-open() of image file failed : ");
+            exit(1);
+        }
+
+        rc = p9_xip_image_size(newImage, &size);
+
+        if (rc)
+        {
+            break;
+        }
+
+        rc = write(newImageFd, newImage, size);
+
+        if ((rc < 0) || ((uint32_t)rc != size))
+        {
+            perror("write() of modified image failed : ");
+            exit(1);
+        }
+
+        rc = close(newImageFd);
+
+        if (rc)
+        {
+            perror("close() of modified image failed : ");
+            exit(1);
+        }
+    }
+    while (0);
+
+    return rc;
+}
+
+// Extract section from a file
+int
+extract(const char* i_imageFile, const int i_imageFd, void* io_image,
+        int i_argc, const char** i_argv)
+{
+    int fileFd, sectionId, rc;
+    void* newImage;
+    const char* section;
+    const char* file;
+    P9XipHeader header;
+    P9XipSection* xSection;
+    uint32_t size;
+    uint32_t offset;
+
+    do
+    {
+
+        if (i_argc != 2)
+        {
+            fprintf(stderr, g_usage);
+            exit(1);
+        }
+
+        section = i_argv[0];
+        file = i_argv[1];
+
+        printf("%s %s\n", section , file);
+
+        p9_xip_translate_header(&header, (P9XipHeader*)io_image);
+
+        sectionId = get_sectionId(header.iv_magic, section);
+
+        if (sectionId < 0)
+        {
+            fprintf(stderr, "Unrecognized section name : '%s;\n", section);
+            exit(1);
+        }
+
+        xSection = &(header.iv_section[sectionId]);
+
+        size = xSection->iv_size;
+        offset = xSection->iv_offset;
+
+        printf("%-16s 0x%08x 0x%08x (%d)\n",
+               section, offset, size, size);
+
+        newImage = malloc(size);
+
+        if (newImage == 0)
+        {
+            fprintf(stderr, "Can't malloc() a buffer for the new image\n");
+            exit(1);
+        }
+
+        memcpy(newImage, (void*)((uint64_t)io_image + offset), size);
+
+        fileFd = open(file, O_CREAT | O_WRONLY | O_TRUNC, 0755);
+
+        if (fileFd < 0)
+        {
+            perror("open() of the fixed section : ");
+            exit(1);
+        }
+
+        rc = write(fileFd, newImage, size);
+
+        if ((rc < 0) || ((uint32_t)rc != size))
+        {
+            perror("write() of fixed section : ");
+            exit(1);
+        }
+
+        rc = close(fileFd);
+
+        if (rc)
+        {
+            perror("close() of fixed section : ");
+            exit(1);
+        }
+
+    }
+    while (0);
+
+    return rc;
+
+}
+
+
+// Delete 0 or more sections in order.
+
+int
+deleteSection(const char* i_imageFile, const int i_imageFd, void* io_image,
+              int i_argc, const char** i_argv)
+{
+    int newImageFd, sectionId, rc, argc;
+    const char* section;
+    const char** argv;
+    void* newImage;
+    void* tempImage;
+    uint32_t size;
+    P9XipHeader header;
+
+    do
+    {
+
+        // malloc() a buffer for the new image
+
+        rc = p9_xip_image_size(io_image, &size);
+
+        if (rc)
+        {
+            break;
+        }
+
+        newImage = malloc(size);
+
+        if (newImage == 0)
+        {
+            fprintf(stderr, "Can't malloc() a buffer for the new image\n");
+            exit(1);
+        }
+
+
+        // Copy the image. At this point the original image file must be
+        // closed.
+
+        memcpy(newImage, io_image, size);
+
+        rc = close(i_imageFd);
+
+        if (rc)
+        {
+            perror("close() of the original image file failed : ");
+            exit(1);
+        }
+
+        // Create a temporary place holder for image
+
+        tempImage = malloc(size);
+
+        if (tempImage == 0)
+        {
+            fprintf(stderr, "Can't malloc() a buffer for the temporary image\n");
+            exit(1);
+        }
+
+
+        p9_xip_translate_header(&header, (P9XipHeader*)io_image);
+
+        // Delete the sections in argument order
+
+        for (argc = i_argc, argv = i_argv; argc != 0; argc--, argv++)
+        {
+
+            // Translate the section name to a section Id
+
+            section = *argv;
+
+            sectionId = get_sectionId(header.iv_magic, section);
+
+            if (sectionId < 0)
+            {
+                fprintf(stderr, "Unrecognized section name : '%s;\n", section);
+                exit(1);
+            }
+
+            // Delete the section
+
+            rc = p9_xip_delete_section(newImage, tempImage, size, sectionId);
+
+            if (rc)
+            {
+                break;
+            }
+        }
+
+        if (rc)
+        {
+            break;
+        }
+
+        // Print the final size of the new image
+
+        rc = p9_xip_image_size(newImage, &size);
+
+        if (rc)
+        {
+            break;
+        }
+
+        printf("%u\n", size);
+
+        // Now write the new image back to the filesystem
+
+        newImageFd = open(i_imageFile, O_WRONLY | O_TRUNC);
+
+        if (newImageFd < 0)
+        {
+            perror("re-open() of image file failed : ");
+            exit(1);
+        }
+
+        rc = write(newImageFd, newImage, size);
+
+        if ((rc < 0) || ((uint32_t)rc != size))
+        {
+            perror("write() of modified image failed : ");
+            exit(1);
+        }
+
+        rc = close(newImageFd);
+
+        if (rc)
+        {
+            perror("close() of modified image failed : ");
+            exit(1);
+        }
+    }
+    while (0);
+
+    return rc;
+}
+
+
+// 'TEST' is an undocumented command provided to test the APIs.  It searches
+// and modifies a copy of the image but puts the image back together as it
+// was, then verifies that the the original image and the copy are identical.
+
+#define BOMB_IF(test)                                   \
+    if (test) {                                         \
+        fprintf(stderr, "%s:%d : Error in TEST\n",      \
+                __FILE__, __LINE__);                    \
+        exit(1);                                        \
+    }
+
+#define BOMB_IF_RC                                              \
+    if (rc) {                                                   \
+        fprintf(stderr, "%s:%d : Error in TEST, rc = %s\n",     \
+                __FILE__, __LINE__,                             \
+                P9_XIP_ERROR_STRING(g_errorStrings, rc));      \
+        exit(1);                                                \
+    }
+
+
+int
+TEST(void* io_image, const int i_argc, const char** i_argv)
+{
+    int rc;
+    uint64_t linkAddress, entryPoint, data, data1, magicKey, L1_LoaderAddr[2];
+    char* key, *revision, *revdup, *longString, *shortString;
+    void* originalImage;
+    uint32_t imageSize;
+    P9XipItem item;
+    P9XipHeader header;
+    P9XipSection section;
+    //ProcSbeFixed* fixed;
+    uint32_t tocSize;
+
+    do
+    {
+        rc = p9_xip_image_size(io_image, &imageSize);
+        BOMB_IF_RC;
+        originalImage = malloc(imageSize);
+        BOMB_IF(originalImage == 0);
+        memcpy(originalImage, io_image, imageSize);
+
+        rc = p9_xip_get_scalar(io_image, "toc_sorted", &data);
+        BOMB_IF_RC;
+        BOMB_IF(data != 1);
+
+        rc = p9_xip_get_scalar(io_image, "image_size", &data);
+        BOMB_IF_RC;
+        BOMB_IF(data != (uint64_t)g_imageSize);
+
+        rc = p9_xip_get_scalar(io_image, "magic", &magicKey);
+        BOMB_IF_RC;
+
+        switch (magicKey)
+        {
+            case P9_XIP_MAGIC_BASE:
+                key = (char*)"proc_p9_fabricinit_revision";
+                rc = p9_xip_get_string(io_image, key, &revision);
+                BOMB_IF_RC;
+                BOMB_IF(strncmp(revision, "1.", 2) != 0);
+                break;
+
+            case P9_XIP_MAGIC_SEEPROM:
+                key = (char*)"";
+                // Can't do this test here as the TOC has been stripped
+                break;
+
+            case P9_XIP_MAGIC_CENTAUR:
+                key = (char*)"cen_p9_initf_revision";
+                rc = p9_xip_get_string(io_image, key, &revision);
+                BOMB_IF_RC;
+                BOMB_IF(strncmp(revision, "1.", 2) != 0);
+                break;
+
+            default:
+                BOMB_IF(1);
+                break;
+        }
+
+        rc = p9_xip_get_scalar(io_image, "link_address", &linkAddress);
+        BOMB_IF_RC;
+
+        if (magicKey != P9_XIP_MAGIC_SEEPROM)
+        {
+            rc = p9_xip_get_scalar(io_image, "entry_point", &entryPoint);
+            BOMB_IF_RC;
+        }
+
+        rc = p9_xip_get_scalar(io_image, "L1_LoaderAddr", &data);
+        BOMB_IF_RC;
+        BOMB_IF((magicKey != P9_XIP_MAGIC_SEEPROM) && (entryPoint != (linkAddress + data)));
+
+        rc =
+            p9_xip_set_scalar(io_image, "toc_sorted", 0) ||
+            p9_xip_set_scalar(io_image, "image_size", 0);
+        BOMB_IF_RC;
+
+        data = 0;
+        data += (rc = p9_xip_get_scalar(io_image, "toc_sorted", &data), data);
+        BOMB_IF_RC;
+        data += (rc = p9_xip_get_scalar(io_image, "image_size", &data), data);
+        BOMB_IF_RC;
+        BOMB_IF(data != 0);
+
+        // Write back keys found during read check.
+
+        rc =
+            p9_xip_set_scalar(io_image, "toc_sorted", 1) ||
+            p9_xip_set_scalar(io_image, "image_size", g_imageSize);
+        BOMB_IF_RC;
+
+        // We'll rewrite the revision keyword with a long string and a short
+        // string, and verify that rewriting is being done correctly.  In the
+        // end we copy the original revision string back in, which is safe
+        // because the memory allocation for strings does not change when they
+        // are modified.
+
+        revdup = strdup(revision);
+        longString = (char*)"A very long string";
+        shortString = (char*)"?";
+
+        if (magicKey != P9_XIP_MAGIC_SEEPROM)
+        {
+            rc =
+                p9_xip_set_string(io_image, key, longString) ||
+                p9_xip_get_string(io_image, key, &revision);
+            BOMB_IF_RC;
+            BOMB_IF((strlen(revision) != strlen(revdup)) ||
+                    (strncmp(revision, longString, strlen(revdup)) != 0));
+
+            rc =
+                p9_xip_set_string(io_image, key, shortString) ||
+                p9_xip_get_string(io_image, key, &revision);
+            BOMB_IF_RC;
+            BOMB_IF(strcmp(revision, shortString) != 0);
+
+            memcpy(revision, revdup, strlen(revdup) + 1);
+        }
+
+        // Use p9_xip_[read,write]_uint64 to modify the image and restore it
+        // to its original form.
+
+        rc = p9_xip_find(io_image, "L1_LoaderAddr", &item);
+        BOMB_IF_RC;
+        rc = p9_xip_get_scalar(io_image, "L1_LoaderAddr", &(L1_LoaderAddr[0]));
+        BOMB_IF_RC;
+
+        rc = p9_xip_read_uint64(io_image, item.iv_address, &(L1_LoaderAddr[1]));
+        BOMB_IF_RC;
+        BOMB_IF(L1_LoaderAddr[0] != L1_LoaderAddr[1]);
+
+        rc = p9_xip_write_uint64(io_image, item.iv_address,
+                                 0xdeadbeefdeadc0deull);
+        BOMB_IF_RC;
+        rc = p9_xip_read_uint64(io_image, item.iv_address, &(L1_LoaderAddr[1]));
+        BOMB_IF_RC;
+        BOMB_IF(L1_LoaderAddr[1] != 0xdeadbeefdeadc0deull);
+
+        rc = p9_xip_write_uint64(io_image, item.iv_address, L1_LoaderAddr[0]);
+        BOMB_IF_RC;
+
+        // Try p9_xip_get_section against the translated header
+
+        p9_xip_translate_header(&header, (P9XipHeader*)io_image);
+        rc = p9_xip_get_section(io_image, P9_XIP_SECTION_TOC, &section);
+        BOMB_IF_RC;
+        BOMB_IF((section.iv_size !=
+                 header.iv_section[P9_XIP_SECTION_TOC].iv_size));
+
+
+        // Make sure the .fixed section access compiles and seems to
+        // work. Modify an entry via the .fixed and verify it with normal TOC
+        // access.
+
+        if (magicKey == P9_XIP_MAGIC_SEEPROM)
+        {
+
+            BOMB_IF(0 != 0);
+
+            exit(1);
+
+            rc = p9_xip_get_scalar(io_image, "proc_p9_ex_dpll_initf_control",
+                                   &data);
+            BOMB_IF_RC;
+            //fixed =
+            //(ProcSbeFixed*)((unsigned long)io_image + P9_XIP_FIXED_OFFSET);
+            //fixed->proc_p9_ex_dpll_initf_control = 0xdeadbeefdeadc0deull;
+            rc = p9_xip_get_scalar(io_image, "proc_p9_ex_dpll_initf_control",
+                                   &data1);
+            BOMB_IF_RC;
+#ifdef _BIG_ENDIAN
+            BOMB_IF(data1 != 0xdeadbeefdeadc0deull);
+#else
+            BOMB_IF(data1 != 0xdec0addeefbeaddeull);
+#endif
+            rc = p9_xip_set_scalar(io_image, "proc_p9_ex_dpll_initf_control",
+                                   data);
+            BOMB_IF_RC;
+        }
+
+        // Temporarily "delete" the .toc section and try to get/set via the
+        // mini-TOC for .fixed, and make sure that we can't get things that
+        // are not in the mini-toc.
+
+        tocSize =
+            ((P9XipHeader*)io_image)->iv_section[P9_XIP_SECTION_TOC].iv_size;
+
+        ((P9XipHeader*)io_image)->iv_section[P9_XIP_SECTION_TOC].iv_size =
+            0;
+
+        rc = p9_xip_get_scalar(io_image, "proc_p9_ex_dpll_initf_control",
+                               &data);
+        rc = p9_xip_set_scalar(io_image, "proc_p9_ex_dpll_initf_control",
+                               0xdeadbeef);
+        rc = p9_xip_get_scalar(io_image, "proc_p9_ex_dpll_initf_control",
+                               &data1);
+        BOMB_IF(data1 != 0xdeadbeef);
+        rc = p9_xip_set_scalar(io_image, "proc_p9_ex_dpll_initf_control",
+                               data);
+        BOMB_IF_RC;
+
+        BOMB_IF(p9_xip_find(io_image, "proc_p9_ex_dpll_initf", 0) !=
+                P9_XIP_ITEM_NOT_FOUND);
+
+        ((P9XipHeader*)io_image)->iv_section[P9_XIP_SECTION_TOC].iv_size =
+            tocSize;
+
+        if (magicKey != P9_XIP_MAGIC_SEEPROM)
+        {
+            BOMB_IF(p9_xip_find(io_image, "proc_p9_ex_dpll_initf", 0) != 0);
+        }
+
+
+#ifdef DEBUG_P9_XIP_IMAGE
+        printf("\nYou will see an expected warning below "
+               "about P9_XIP_WOULD_OVERFLOW\n"
+               "It means the TEST is working (not failing)\n\n");
+#endif
+
+        // Finally compare against the original
+
+        BOMB_IF(memcmp(io_image, originalImage, imageSize));
+
+    }
+    while (0);
+
+    return rc;
+}
+
+
+
+#ifdef XIP_TOOL_ENABLE_DISSECT
+
+// This should be improved, though. Not really our responsibility defining this.
+#define CHIPLET_ID_MAX            (uint8_t)0x37
+
+/// Function:  dissectRingSectionTor()
+///
+/// Brief:  Dissects and summarizes content of a ring section.
+///
+/// \param[in] i_ringSection    A pointer to a TOR compliant ring section.
+///
+/// \param[in] i_imageMagicNo   The image's MAGIC number.
+///
+/// \param[in] i_listingModeId  The listing mode: {short, normal(default), long}.
+///
+/// Assumptions:
+///
+int dissectRingSectionTor( void*       i_ringSection,
+                           uint64_t    i_imageMagicNo,
+                           uint8_t     i_listingModeId )
+{
+    int         rc = 0;
+    uint32_t    i;
+    char*       disList = NULL;
+    uint32_t    sizeDisLine = 0, sizeList = 0, sizeListMax = 0, sizeListIncr;
+    char        lineDis[LINE_SIZE_MAX];
+    uint32_t    numDdLevels;
+    uint8_t     iDdLevel, ddLevel;
+    uint8_t     ppeType;
+    uint8_t     ringId;
+    RingType_t  ringType;
+    uint8_t     ringVariant;
+    uint8_t     instanceId;
+    void*       ringBlockPtr;
+    uint32_t    ringBlockSize;
+    char        ringName[32];
+    void*       hostRs4Container;
+    uint32_t    compressedBits = 0, ringLength = 0;
+    double      compressionPct = 0;
+    uint32_t    ringSeqNo  = 0; // Ring sequence number
+
+    //
+    // Allocate buffer to hold dissected ring info. (Start out with min 10kB buffer size.)
+    //
+    sizeListIncr = 10 * LINE_SIZE_MAX;
+    sizeListMax = sizeListIncr;
+    disList = (char*)malloc(sizeListMax);
+
+    if (disList == NULL)
+    {
+        fprintf( stderr, "ERROR : malloc() failed.\n");
+        fprintf( stderr, "\tMore info: %s\n", DIS_ERROR_STRING(g_errorStringsDis, DIS_MEMORY_ERROR));
+        return P9_XIP_DISASSEMBLER_ERROR;
+    }
+
+    *disList = '\0'; // Make sure the buffer is NULL terminated (though probably not needed.)
+    sizeList = 0;
+
+    sizeDisLine = snprintf( lineDis, LINE_SIZE_MAX,
+                            "-----------------------------\n"
+                            "*       Ring summary        *\n");
+
+    disList = strcat(disList, lineDis);
+    sizeList = sizeList + sizeDisLine;
+
+    //
+    // Allocate large buffer to hold max length ring block.
+    //
+    ringBlockSize = RING_BUF_SIZE_MAX;
+    ringBlockPtr = malloc(ringBlockSize);
+
+    //
+    // Get number of DD levels from TOR structure in ring section
+    //
+    if (i_imageMagicNo == P9_XIP_MAGIC_HW)
+    {
+        numDdLevels = htobe32( ( (TorNumDdLevels_t*)i_ringSection )->TorNumDdLevels );
+        fprintf( stdout, "numDdLevels (=%d) read from top of ring section.\n", numDdLevels);
+    }
+    else
+    {
+        numDdLevels = 1;
+        ddLevel = 0xff; // This means it's unknown.
+        fprintf( stdout, "Image contains only one DD level set of rings.\n");
+    }
+
+    //----------------
+    // DD level loop.
+    for (iDdLevel = 0; iDdLevel < numDdLevels; iDdLevel++)
+    {
+
+        if (i_imageMagicNo == P9_XIP_MAGIC_HW)
+        {
+            ddLevel = ( ( htobe32( ( ( (TorDdLevelBlock_t*)((uintptr_t)i_ringSection + sizeof(TorNumDdLevels_t)) ) +
+                                     iDdLevel )->TorDdLevelAndOffset ) & 0xff000000 ) >> 24 );
+        }
+
+        //----------------
+        // PPE type loop.
+        // - SBE, CME, SGPE
+        for (ppeType = 0; ppeType < NUM_PPE_TYPES; ppeType++)
+        {
+
+            //--------------------
+            // Ring variant loop.
+            // - Base, cache, risk, override, overlay
+            for (ringVariant = 0; ringVariant < NUM_RING_VARIANTS; ringVariant++)
+            {
+
+                //----------------------
+                // Unique ring ID loop.
+                for (ringId = 0; ringId < NUM_RING_IDS; ringId++)
+                {
+
+                    ringType = (RingType_t)(-1);
+
+                    //---------------------------
+                    // Chiplet instance ID loop.
+                    // - Only loop once if ringId is a common ring.
+                    for (instanceId = 0; instanceId <= CHIPLET_ID_MAX && ringType != COMMON; instanceId++)
+                    {
+
+                        fprintf( stdout, "Processing:  "
+                                 "DD=0x%02x  "
+                                 "PPE=%s "
+                                 "Variant=%s "
+                                 "RingID=%d  "
+                                 "InstanceID=0x%02x\n",
+                                 ddLevel, ppeTypeName[ppeType], ringVariantName[ringVariant], ringId, instanceId);
+
+                        ringBlockSize = RING_BUF_SIZE_MAX;
+                        rc = tor_access_ring( i_ringSection,
+                                              i_imageMagicNo,
+                                              (RingID)ringId,
+                                              ddLevel,
+                                              (PpeType_t)ppeType,
+                                              ringType,            // IO parm
+                                              (RingVariant_t)ringVariant,
+                                              instanceId,          // IO parm
+                                              GET_SINGLE_RING,
+                                              &ringBlockPtr,       // IO parm
+                                              ringBlockSize,       // IO parm
+                                              ringName,
+                                              0 );
+
+                        // Gather ring details and print it.
+                        //
+                        if (rc == IMGBUILD_TGR_RING_FOUND)
+                        {
+
+                            // Check ring block size.
+                            if ( htobe32(((RingLayout_t*)ringBlockPtr)->sizeOfThis) != ringBlockSize )
+                            {
+                                fprintf(stderr, "tor_access_ring() was successful and found a ring but "
+                                        "sizeOfThis(=0x%08x) != ringBlockSize(=0x%08x) is a bug.\n",
+                                        htobe32(((RingLayout_t*)ringBlockPtr)->sizeOfThis), ringBlockSize);
+                                exit(1);
+                            }
+
+                            ringSeqNo++;
+
+                            // Summarize a few key characteristics of the ring block if "short".
+                            if (i_listingModeId == LMID_SHORT)
+                            {
+                                sizeDisLine = snprintf( lineDis, LINE_SIZE_MAX,
+                                                        "-----------------------------\n"
+                                                        "%i.\n"
+                                                        "ddLevel = 0x%02x\n"
+                                                        "ppeType = %s\n"
+                                                        "ringName = %s\n"
+                                                        "ringVariant = %s\n"
+                                                        "instanceId = 0x%02x\n",
+                                                        ringSeqNo, ddLevel, ppeTypeName[ppeType], ringName,
+                                                        ringVariantName[ringVariant], instanceId );
+
+                                if (sizeDisLine >= LINE_SIZE_MAX)
+                                {
+                                    fprintf(stderr, "The max print line size, LINE_SIZE_MAX=%d, has been reached.(1)",
+                                            LINE_SIZE_MAX);
+                                    fprintf(stderr, "You should investigate why this happened before increasing "
+                                            "the value of LINE_SIZE_MAX since something might be wrong "
+                                            "with the RS4 ring content.");
+                                    exit(1);
+                                }
+
+                                // Update list buffer and readjust list buffer size, if needed.
+                                disList = strcat(disList, lineDis);
+                                sizeList = sizeList + sizeDisLine;
+
+                            }
+
+                            // Summarize all characteristics of the ring block if "normal" or "long" (default).
+                            if ( i_listingModeId == LMID_NORMAL || i_listingModeId == LMID_LONG )
+                            {
+                                // Calculate RS4 compression efficiency.
+                                hostRs4Container = (void*)( (uintptr_t)ringBlockPtr + sizeof(RingLayout_t) );
+                                compressedBits = htobe32(((CompressedScanData*)hostRs4Container)->iv_algorithmReserved) * 4;
+                                ringLength = htobe32(((CompressedScanData*)hostRs4Container)->iv_length);
+                                compressionPct = (double)compressedBits / (double)ringLength * 100.0;
+
+                                sizeDisLine = snprintf( lineDis, LINE_SIZE_MAX,
+                                                        "-----------------------------\n"
+                                                        "%i.\n"
+                                                        "ddLevel = 0x%02x\n"
+                                                        "ppeType = %s\n"
+                                                        "ringId = %u\n"
+                                                        "ringName = %s\n"
+                                                        "ringVariant = %s\n"
+                                                        "instanceId = 0x%02x\n"
+                                                        "ringBlockSize = 0x%08x\n"
+                                                        "RS4 ring size [bits] = %u\n"
+                                                        "Raw ring size [bits] = %u\n"
+                                                        "Compression [%%]      = %0.2f\n",
+                                                        ringSeqNo, ddLevel, ppeTypeName[ppeType], ringId, ringName,
+                                                        ringVariantName[ringVariant], instanceId,
+                                                        ringBlockSize, compressedBits, ringLength, compressionPct );
+
+                                if (sizeDisLine >= LINE_SIZE_MAX)
+                                {
+                                    fprintf(stderr, "The max print line size, LINE_SIZE_MAX=%d, has been reached.(2)",
+                                            LINE_SIZE_MAX);
+                                    fprintf(stderr, "You should investigate why this happened before increasing "
+                                            "the value of LINE_SIZE_MAX since something might be wrong "
+                                            "with the RS4 ring content.");
+                                    exit(1);
+                                }
+
+                                // Update list buffer and readjust list buffer size, if needed.
+                                disList = strcat(disList, lineDis);
+                                sizeList = sizeList + sizeDisLine;
+
+                            }
+
+                            // Dump ring block if "long".
+                            if (i_listingModeId == LMID_LONG)
+                            {
+                                sizeDisLine = snprintf( lineDis, LINE_SIZE_MAX,
+                                                        "Binary ring block dump (LE format):\n");
+                                disList = strcat(disList, lineDis);
+                                sizeList = sizeList + sizeDisLine;
+
+                                if (sizeDisLine >= LINE_SIZE_MAX)
+                                {
+                                    fprintf(stderr, "The max print line size, LINE_SIZE_MAX=%d, has been reached.(3)",
+                                            LINE_SIZE_MAX);
+                                    fprintf(stderr, "You should investigate why this happened before increasing "
+                                            "the value of LINE_SIZE_MAX since something might be wrong "
+                                            "with the RS4 ring content.");
+                                    exit(1);
+                                }
+
+                                for (i = 0; i < ringBlockSize / 8; i++)
+                                {
+                                    sizeDisLine = snprintf( lineDis, LINE_SIZE_MAX,
+                                                            "%04x: %04x %04x %04x %04x\n",
+                                                            i * 8,
+                                                            (uint16_t)( htobe64(*((uint64_t*)ringBlockPtr + i)) >> 48),
+                                                            (uint16_t)( htobe64(*((uint64_t*)ringBlockPtr + i)) >> 32),
+                                                            (uint16_t)( htobe64(*((uint64_t*)ringBlockPtr + i)) >> 16),
+                                                            (uint16_t)( htobe64(*((uint64_t*)ringBlockPtr + i))) );
+
+                                    disList = strcat(disList, lineDis);
+                                    sizeList = sizeList + sizeDisLine;
+
+                                }
+                            }
+
+                            if (sizeList > (sizeListMax - LINE_SIZE_MAX))
+                            {
+                                sizeListMax = sizeListMax + sizeListIncr;
+                                disList = (char*)realloc( (void*)(disList), sizeListMax);
+                            }
+
+                            fprintf(stdout, "%s\n", disList);
+
+                        }
+                        else if (rc == IMGBUILD_TGR_RING_NOT_FOUND)
+                        {
+                            fprintf(stdout, "tor_access_ring() returned rc=%d=IMGBUILD_TGR_RING_NOT_FOUND\n", rc);
+                        }
+                        else if (rc == IMGBUILD_INVALID_INSTANCEID)
+                        {
+                            fprintf(stdout, "tor_access_ring() returned rc=%d=IMGBUILD_INVALID_INSTANCEID\n", rc);
+                        }
+                        else if (rc == IMGBUILD_TGR_AMBIGUOUS_API_PARMS)
+                        {
+                            fprintf(stdout, "tor_access_ring() returned rc=%d=IMGBUILD_TGR_AMBIGUOUS_API_PARMS\n", rc);
+                        }
+                        else
+                        {
+                            fprintf(stderr, "tor_access_ring() returned error code rc=%d\n", rc);
+                            exit(1);
+                        }
+
+                    }  // End of for(instanceId)
+
+                }  // End of for(ringVariant)
+
+            }  // End of for(iRingId)
+
+        }  // End of for(ppeType)
+
+    }  // End of for(iDdLevel)
+
+
+    sizeDisLine = snprintf( lineDis, LINE_SIZE_MAX,
+                            "-----------------------------\n");
+
+    disList = strcat(disList, lineDis);
+    sizeList = sizeList + sizeDisLine;
+
+    // Adjust final buffer size, add 1 for NULL char and print it.
+    if (disList)
+    {
+        disList = (char*)realloc( (void*)(disList), sizeList + 1);
+        fprintf(stdout, "%s\n", disList);
+        free(disList);
+    }
+
+    return 0;
+
+}
+
+
+
+/// Function:  dissectRingSection()
+///
+/// Brief:  Processes XIP tool input parms and prepares parameters to be passed
+///         to dissectRingSectionTor which does the actual dissection and
+///         summarizing of the ring section.
+///
+/// \param[in] i_image  A pointer to a P9-XIP image in host memory.
+///
+/// \param[in] i_argc  Additional number of arguments beyond "dissect" keyword.
+///
+/// \param[in] i_argv  Additional arguments beyond "dissect" keyword.
+///
+/// Assumptions:
+///
+int dissectRingSection(void*          i_image,
+                       int            i_argc,
+                       const char**   i_argv)
+{
+    int             rc = 0;
+    const char*     sectionName;
+    const char*     listingModeName = NULL;
+    uint8_t         sectionId, listingModeId;
+    P9XipHeader     hostHeader;
+    P9XipSection    hostSection;
+    void*           ringSectionPtr;
+
+
+    if (i_argc != 1 && i_argc != 2)
+    {
+        fprintf(stderr, g_usage);
+        exit(1);
+    }
+
+    if (i_argc == 1)
+    {
+        sectionName = i_argv[0];
+    }
+    else
+    {
+        sectionName = i_argv[0];
+        listingModeName = i_argv[1];
+    }
+
+    p9_xip_translate_header(&hostHeader, (P9XipHeader*)i_image);
+
+    // Determine P9-XIP ring section ID from the section name, e.g.
+    //         .rings    =>  P9_XIP_SECTION_HW_RINGS
+    if (strcmp(sectionName, ".rings") == 0)
+    {
+        if (hostHeader.iv_magic == P9_XIP_MAGIC_SEEPROM)
+        {
+            sectionId = P9_XIP_SECTION_SBE_RINGS;
+        }
+        else if (hostHeader.iv_magic == P9_XIP_MAGIC_HW)
+        {
+            sectionId = P9_XIP_SECTION_HW_RINGS;
+        }
+        else
+        {
+            fprintf(stderr, "ERROR: .rings is not a valid section for image w/magic=0x%016lx\n",
+                    hostHeader.iv_magic);
+            exit(1);
+        }
+    }
+    else if (strcmp(sectionName, ".overrides") == 0)
+    {
+        if (hostHeader.iv_magic == P9_XIP_MAGIC_SEEPROM)
+        {
+            sectionId = P9_XIP_SECTION_SBE_OVERRIDES;
+        }
+        else
+        {
+            fprintf(stderr, "ERROR: .overrides is not a valid section for image w/magic=0x%016lx\n",
+                    hostHeader.iv_magic);
+            exit(1);
+        }
+    }
+    else if (strcmp(sectionName, ".overlays") == 0)
+    {
+        if (hostHeader.iv_magic == P9_XIP_MAGIC_SEEPROM)
+        {
+            sectionId = P9_XIP_SECTION_SBE_OVERLAYS;
+        }
+        else
+        {
+            fprintf(stderr, "ERROR: .overlays is not a valid section for image w/magic=0x%016lx\n",
+                    hostHeader.iv_magic);
+            exit(1);
+        }
+    }
+    else
+    {
+        fprintf(stderr, "ERROR : %s is an invalid ring section name.\n", sectionName);
+        fprintf(stderr, "Valid ring <section> names for the 'dissect' function are:\n");
+        fprintf(stderr, "\t.rings\n");
+        fprintf(stderr, "\t.overrides\n");
+        fprintf(stderr, "\t.overlays\n");
+        exit(1);
+    }
+
+    // Determine mode of listing.
+    //
+    if ( listingModeName == NULL )
+    {
+        listingModeId = LMID_NORMAL;
+    }
+    else if (strcmp(listingModeName, "short") == 0)
+    {
+        listingModeId = LMID_SHORT;
+    }
+    else if (strcmp(listingModeName, "normal") == 0)
+    {
+        listingModeId = LMID_NORMAL;
+    }
+    else if (strcmp(listingModeName, "long") == 0)
+    {
+        listingModeId = LMID_LONG;
+    }
+    else
+    {
+        fprintf(stderr, "ERROR : %s is an invalid listing mode name.\n", listingModeName);
+        fprintf(stderr, "Valid listing mode names the 'dissect' function are:\n");
+        fprintf(stderr, "\tshort\n");
+        fprintf(stderr, "\tnormal (default if omitted)\n");
+        fprintf(stderr, "\tlong\n");
+        exit(1);
+    }
+
+    // Get ring section.
+    //
+    rc = p9_xip_get_section( i_image, sectionId, &hostSection);
+
+    if (rc)
+    {
+        fprintf( stderr, "p9_xip_get_section() failed : %s\n", P9_XIP_ERROR_STRING(g_errorStrings, rc));
+        return P9_XIP_DISASSEMBLER_ERROR;
+    }
+
+    if (hostSection.iv_offset == 0)
+    {
+        fprintf( stdout, "Ring section (w/ID=%d) is empty. Nothing to do. Quitting.\n", sectionId);
+        exit(1);
+    }
+
+    ringSectionPtr = (void*)(hostSection.iv_offset + (uintptr_t)i_image);
+
+    rc = dissectRingSectionTor(ringSectionPtr, hostHeader.iv_magic, listingModeId);
+
+    return rc;
+
+}
+
+#endif
+
+
+
+/// Function:  openAndMap()
+///
+/// Brief:  Opens and mmaps the file.
+///
+void
+openAndMap(const char* i_fileName, int i_writable, int* o_fd, void** o_image, const uint32_t i_maskIgnores)
+{
+    int rc, openMode, mmapProt, mmapShared;
+    struct stat buf;
+
+    if (i_writable)
+    {
+        openMode = O_RDWR;
+        mmapProt = PROT_READ | PROT_WRITE;
+        mmapShared = MAP_SHARED;
+    }
+    else
+    {
+        openMode = O_RDONLY;
+        mmapProt = PROT_READ;
+        mmapShared = MAP_PRIVATE;
+    }
+
+    *o_fd = open(i_fileName, openMode);
+
+    if (*o_fd < 0)
+    {
+        perror("open() of the image failed : ");
+        exit(1);
+    }
+
+    rc = fstat(*o_fd, &buf);
+
+    if (rc)
+    {
+        perror("fstat() of the image failed : ");
+        exit(1);
+    }
+
+    g_imageSize = buf.st_size;
+
+    *o_image = mmap(0, g_imageSize, mmapProt, mmapShared, *o_fd, 0);
+
+    if (*o_image == MAP_FAILED)
+    {
+        perror("mmap() of the image failed : ");
+        exit(1);
+    }
+
+    if ( !(i_maskIgnores & P9_XIP_IGNORE_ALL) )
+    {
+        rc = p9_xip_validate2(*o_image, g_imageSize, i_maskIgnores);
+
+        if (rc)
+        {
+            fprintf(stderr, "p9_xip_validate2() failed : %s\n",
+                    P9_XIP_ERROR_STRING(g_errorStrings, rc));
+            exit(1);
+        }
+    }
+
+}
+
+
+static inline void
+openAndMapWritable(const char* i_imageFile, int* o_fd, void** o_image, const uint32_t i_maskIgnores)
+{
+    openAndMap(i_imageFile, 1, o_fd, o_image, i_maskIgnores);
+}
+
+
+static inline void
+openAndMapReadOnly(const char* i_imageFile, int* o_fd, void** o_image, const uint32_t i_maskIgnores)
+{
+    openAndMap(i_imageFile, 0, o_fd, o_image, i_maskIgnores);
+}
+
+
+// Parse and execute a pre-tokenized command
+
+void
+command(const char* i_imageFile, const int i_argc, const char** i_argv, const uint32_t i_maskIgnores)
+{
+    void* image;
+    void* attrDump;
+    int fd, rc = 0;
+
+    if (strcmp(i_argv[0], "normalize") == 0)
+    {
+
+        openAndMapWritable(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = normalize(image, i_argc - 1, &(i_argv[1]), i_maskIgnores);
+
+    }
+    else if (strcmp(i_argv[0], "set") == 0)
+    {
+
+        openAndMapWritable(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = set(image, i_argc - 1, &(i_argv[1]), 0);
+
+    }
+    else if (strcmp(i_argv[0], "setv") == 0)
+    {
+
+        openAndMapWritable(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = set(image, i_argc - 1, &(i_argv[1]), 1);
+
+    }
+    else if (strcmp(i_argv[0], "get") == 0)
+    {
+
+        openAndMapReadOnly(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = get(image, i_argc - 1, &(i_argv[1]), 0);
+
+    }
+    else if (strcmp(i_argv[0], "getv") == 0)
+    {
+
+        openAndMapReadOnly(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = get(image, i_argc - 1, &(i_argv[1]), 1);
+
+    }
+    else if (strcmp(i_argv[0], "report") == 0)
+    {
+
+        openAndMapReadOnly(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = report(image, i_argc - 1, &(i_argv[1]));
+
+    }
+    else if (strcmp(i_argv[0], "attrdump") == 0)
+    {
+
+        openAndMapReadOnly(i_imageFile, &fd, &image, i_maskIgnores);
+        //capture the g_imageSize size for validation, since the next
+        //openAndMapReadOnly will overwrite it
+        size_t imageSize = g_imageSize;
+        //first argument after command is dump file
+        openAndMapReadOnly(i_argv[1], &fd, &attrDump, P9_XIP_IGNORE_ALL);
+        rc = reportAttr(image, imageSize, attrDump);
+
+    }
+    else if (strcmp(i_argv[0], "append") == 0)
+    {
+
+        openAndMapWritable(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = append(i_imageFile, fd, image, i_argc - 1, &(i_argv[1]));
+
+    }
+    else if (strcmp(i_argv[0], "extract") == 0)
+    {
+
+        openAndMapWritable(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = extract(i_imageFile, fd, image, i_argc - 1, &(i_argv[1]));
+
+    }
+    else if (strcmp(i_argv[0], "delete") == 0)
+    {
+
+        openAndMapWritable(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = deleteSection(i_imageFile, fd, image, i_argc - 1,
+                           &(i_argv[1]));
+
+    }
+    else if (strcmp(i_argv[0], "dissect") == 0)
+    {
+
+        openAndMapReadOnly(i_imageFile, &fd, &image, i_maskIgnores);
+#ifdef XIP_TOOL_ENABLE_DISSECT
+        rc = dissectRingSection(image, i_argc - 1, &(i_argv[1]));
+#else
+        fprintf(stderr, "\n");
+        fprintf(stderr, "-------------------------------\n");
+        fprintf(stderr, " dissect feature not supported \n");
+        fprintf(stderr, "-------------------------------\n\n");
+        exit(1);
+#endif
+
+    }
+    else if (strcmp(i_argv[0], "disasm") == 0)
+    {
+
+        //openAndMapReadOnly(i_imageFile, &fd, &image, i_maskIgnores);
+        //rc = disassembleSection(image, i_argc - 1, &(i_argv[1]));
+        fprintf(stderr, "not supported\n");
+        exit(1);
+
+    }
+    else if (strcmp(i_argv[0], "TEST") == 0)
+    {
+
+        openAndMapWritable(i_imageFile, &fd, &image, i_maskIgnores);
+        rc = TEST(image, i_argc - 1, &(i_argv[1]));
+
+    }
+    else
+    {
+        fprintf(stderr, g_usage);
+        exit(1);
+    }
+
+    if (rc)
+    {
+        fprintf(stderr, "Command failed : %s\n",
+                P9_XIP_ERROR_STRING(g_errorStrings, rc));
+        exit(1);
+    }
+}
+
+
+// Open, map and validate the image, then parse and execute the command.  The
+// image is memory-mapped read/write, i.e, it may be modified in-place.
+// Commands that modify the size of the image will close and recreate the
+// file.
+
+int
+main(int argc, const char** argv)
+{
+    uint8_t   argcMin, idxArgvFlagsStart;
+    uint8_t   numFlags = 0, idxArgv, bMoreFlags;
+    uint32_t  maskIgnores = 0;
+
+    argcMin = 3;
+    idxArgvFlagsStart = argcMin - 1; // -i flags must start after image file name.
+
+    numFlags = 0;
+    bMoreFlags = 1;
+
+    do
+    {
+        idxArgv = idxArgvFlagsStart + numFlags;
+
+        if (idxArgv <= (argc - 1))
+        {
+            if (strncmp(argv[idxArgv], "-i", 1) == 0)
+            {
+                numFlags++;
+                bMoreFlags = 1;
+
+                if (strncmp(argv[idxArgv], "-ifs", 4) == 0)
+                {
+                    maskIgnores = maskIgnores | P9_XIP_IGNORE_FILE_SIZE;
+                }
+                else if (strncmp(argv[idxArgv], "-iv", 3) == 0)
+                {
+                    maskIgnores = maskIgnores | P9_XIP_IGNORE_ALL;
+                }
+                else
+                {
+                    fprintf(stderr, g_usage);
+                    fprintf(stderr, "\n");
+                    fprintf(stderr, "argv[%i]=%s is an unsupported flag.", idxArgv, argv[idxArgv]);
+                    fprintf(stderr, "See top of above help menu for supported flags.\n");
+                    exit(1);
+                }
+            }
+            else
+            {
+                bMoreFlags = 0;
+            }
+        }
+        else
+        {
+            bMoreFlags = 0;
+            break;
+        }
+    }
+    while (bMoreFlags);
+
+    if ((argc < (argcMin + numFlags)) ||
+        (strncmp(argv[1], "-h", 2) == 0) ||
+        (strncmp(argv[1], "--h", 3) == 0) )
+    {
+        fprintf(stderr, g_usage);
+        exit(1);
+    }
+
+    command(argv[1], argc - idxArgv, &(argv[idxArgv]), maskIgnores);
+
+    return 0;
+}
diff --git a/src/import/hwpf/fapi2/include/buffer.H b/src/import/hwpf/fapi2/include/buffer.H
new file mode 100644
index 00000000..7661a9cd
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/buffer.H
@@ -0,0 +1,781 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/buffer.H $                          */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file buffer.H
+ * @brief definitions for fapi2 variable integral buffers
+ */
+
+#ifndef __FAPI2_INTEGRAL_BUFFER__
+#define __FAPI2_INTEGRAL_BUFFER__
+
+#include <buffer_parameters.H>
+#include <buffer_traits.H>
+#include <plat_trace.H>
+#include <return_code_defs.H>
+
+namespace fapi2
+{
+/// @brief Class representing a FAPI buffer<T>
+/// @tparam T, the integral type of the buffer (uint16_t, uint64_t, etc.)
+template <typename T, typename TT = bufferTraits<T> >
+class buffer
+{
+    public:
+        /// Shortcut typedef to get to our traits class
+        typedef typename TT::bits_type bits_type;
+
+        ///
+        /// @brief Integral buffer assignment constructor
+        /// @param[in] i_value initial value of the buffer
+        /// Meaningless for variable types and thus protected.
+        ///
+        inline buffer(T i_value = 0):
+            iv_data(i_value)
+        {
+        }
+
+        ~buffer(void) = default;
+
+#if !defined(DOXYGEN) && defined(FAPI2_DEBUG)
+        /// @brief Print the contents of the buffer to stdout
+        inline void print(void) const
+        {
+            TT::print(iv_data);
+        }
+#endif
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline operator T() const
+        {
+            return iv_data;
+        }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline operator T& ()
+        {
+            return iv_data;
+        }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline T& operator()(void)
+        {
+            return iv_data;
+        }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return Reference to the contents of the buffer
+        ///
+        inline const T& operator()(void) const
+        {
+            return iv_data;
+        }
+
+        /// @name Buffer Manipulation Functions
+        ///@{
+
+        ///
+        /// @brief Set an OT of data in buffer
+        /// @param[in] i_value sizeof(OT) bits of data
+        /// @param[in] i_offset Start OT (start word, for example) in buffer
+        ///            - defaults to 0 (will by default write the left most element)
+        /// @return FAPI2_RC_SUCCESS on success, FAPI2_RC_OVERFLOW otherwise
+        /// @note This is is only available for integral types. To set a
+        ///    variable_buffer into a variable_buffer, use insert()
+        ///
+        template< typename OT>
+        inline fapi2::ReturnCodes set(OT i_value, const bits_type i_offset = 0)
+        {
+            // Compile time check to make sure OT is integral
+            static_assert( std::is_integral<OT>::value,
+                           "Input must be an integral type" );
+
+            const uint32_t length = TT:: template size<OT>(iv_data);
+            static const bits_type bits_in_value = parameterTraits<OT>::bit_length();
+            const bits_type bit_length = TT::bit_length(iv_data);
+
+            if (i_offset + bits_in_value > bit_length)
+            {
+                return FAPI2_RC_OVERFLOW;
+            }
+
+            // Create mask if part of this byte is not in the valid part of the buffer,
+            // Shift it left by the amount of unused bits,
+            // Clear the unused bits
+            if (((i_offset + 1) == length) && (bit_length % bits_in_value))
+            {
+                i_value &= parameterTraits<OT>::mask() << ((bits_in_value * length) -
+                           bit_length);
+            }
+
+            parameterTraits<OT>::template write_element<typename TT::unit_type>
+            (TT::get_address(iv_data), i_value, i_offset);
+            return FAPI2_RC_SUCCESS;
+        }
+
+        /// @name Bit/Word Manipulation Functions
+        ///@{
+
+        ///
+        /// @brief Return the length of the buffer in bits
+        /// @return Length in bits
+        ///
+        inline constexpr uint32_t getBitLength(void) const
+        {
+            return TT::bit_length(iv_data);
+        }
+
+        ///
+        /// @brief Return the length of the buffer in OT units
+        /// @return Length in OT units rounded up
+        /// @tparam OT the type to get the length of. For example, if one
+        /// wanted the length in double words, OT would be uint64_t
+        /// (getLength<uint64_t>().) Similarly, to get the length in words,
+        /// getLength<uin32_t>().
+        ///
+        template< typename OT >
+        inline constexpr uint32_t getLength(void) const
+        {
+            return TT::template size<OT>(iv_data);
+        }
+
+        ///
+        /// @brief Templated setBit for integral types
+        /// @tparam B the bit number to set.
+        /// @tparam C the count of bits to set, defaults to 1
+        /// @return buffer& Useful for method chaining
+        /// @note 0 is left-most
+        /// @note Example: fapi2::buffer<uint64_t>().setBit<3>();
+        ///
+        template< bits_type B, bits_type C = 1 >
+        inline buffer & setBit(void)
+        {
+            static_assert((B >= 0) &&
+                          ((B + C - 1) < TT::bits_per_unit()), "failed range check");
+
+            // This would be a candidate for a fast_mask (see variable_buffer) but
+            // we'd need tables for all the integral types which maybe we need to
+            // do ...
+            iv_data |= (T(~0) >> (TT::bits_per_unit() - C)) << (TT::bits_per_unit() - B -
+                       C);
+            return *this;
+        }
+
+        ///
+        /// @brief Set a bit in the buffer
+        /// @param[in] i_bit the bit number to set.
+        /// @param[in] i_count the count of bits to set, defaults to 1
+        /// @note 0 is left-most
+        /// @return FAPI2_RC_SUCCESS if OK
+        ///
+        inline fapi2::ReturnCodes setBit(const bits_type& i_bit,
+                                         const bits_type& i_count = 1)
+        {
+            if ((i_count + i_bit - 1) >= TT::bits_per_unit())
+            {
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            iv_data |= (T(~0) >> (TT::bits_per_unit() - i_count)) <<
+                       (TT::bits_per_unit() - i_bit - i_count);
+
+            return FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Clear a bit in buffer
+        /// @tparam B Bit in buffer to clear.
+        /// @tparam C the count of bits to clear, defaults to 1
+        /// @return buffer& Useful for method chaining
+        /// @note Asserting that all the parameters are known at
+        /// compile time so this can be templated only. If that is not
+        /// the case we can add a function parameter version.
+        ///
+        template< bits_type B, bits_type C = 1>
+        inline buffer & clearBit(void)
+        {
+            static_assert((B >= 0) &&
+                          ((B + C - 1) < TT::bits_per_unit()), "failed range check");
+
+            iv_data &= buffer<T>().setBit<B, C>().invert();
+            return *this;
+        }
+
+        ///
+        /// @brief Clear a bit in the buffer
+        /// @param[in] i_bit the bit number to clear.
+        /// @param[in] i_count the count of bits to clear, defaults to 1
+        /// @note 0 is left-most
+        /// @return FAPI2_RC_SUCCESS if OK
+        ///
+        inline fapi2::ReturnCodes clearBit(const bits_type& i_bit,
+                                           const bits_type& i_count = 1)
+        {
+            if ((i_count + i_bit - 1) >= TT::bits_per_unit())
+            {
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            fapi2::buffer<T> l_scratch;
+
+            if (l_scratch.setBit(i_bit, i_count) != FAPI2_RC_SUCCESS)
+            {
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            iv_data &= l_scratch.invert();
+
+            return FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Write a bit in buffer to a given value
+        /// @tparam B Bit in buffer to write
+        /// @tparam C the count of bits to write, defaults to 1
+        /// @return buffer& Useful for method chaining
+        /// @note Asserting that all the parameters are known at
+        /// compile time so this can be templated only. If that is not
+        /// the case we can add a function parameter version.
+        ///
+        template< bits_type B, bits_type C = 1 >
+        inline buffer & writeBit(const bool i_value)
+        {
+            static_assert((B >= 0) &&
+                          ((B + C - 1) < TT::bits_per_unit()), "failed range check");
+
+            (i_value == 0) ? clearBit<B, C>() : setBit<B, C>();
+            return *this;
+        }
+
+
+        ///
+        /// @brief Invert bit
+        /// @tparam B Bit in buffer to invert.
+        /// @tparam C the count of bits to flip, defaults to 1
+        /// @return buffer& Useful for method chaining
+        /// @note Asserting that all the parameters are known at
+        /// compile time so this can be templated only. If that is not
+        /// the case we can add a function parameter version.
+        ///
+        template< bits_type B, bits_type C = 1 >
+        inline buffer & flipBit(void)
+        {
+            static_assert((B >= 0) &&
+                          ((B + C - 1) < TT::bits_per_unit()), "failed range check");
+
+            iv_data ^= buffer<T>().setBit<B, C>();
+            return *this;
+        }
+
+        ///
+        /// @brief Get the value of a bit in the buffer
+        /// @tparam B Bit in buffer to get.
+        /// @tparam C the count of bits to get, defaults to 1
+        /// @return true if *any* bit is on, false if *every* bit is off
+        /// @note 0 is left-most
+        ///
+        template< bits_type B, bits_type C = 1>
+        inline bool getBit(void) const
+        {
+            return buffer<T>().setBit<B, C>() & iv_data;
+        }
+
+        ///
+        /// @brief Get the value of a bit in the buffer
+        /// @param[in] i_bit the bit number to set.
+        /// @param[in] i_count the count of bits to set, defaults to 1
+        /// @return true if *any* bit is on, false if *every* bit is off
+        /// @note 0 is left-most
+        ///
+        inline bool getBit(const bits_type& i_bit,
+                           const bits_type& i_count = 1)
+        {
+            buffer<T> l_temp;
+            l_temp.setBit(i_bit, i_count);
+            return l_temp & iv_data;
+        }
+
+        ///
+        /// @brief Set and entire buffer to X's
+        /// @tparam X {0,1} depending if you want to clear (0)
+        /// or fill (1) a buffer
+        /// @return buffer_base&, Useful for method chaining
+        ///
+        template< uint8_t X >
+        inline buffer& flush(void)
+        {
+            static_assert( (X == 1) || (X == 0), "bad argument to flush" );
+            (0 == X) ? TT::clear(iv_data) : TT::set(iv_data);
+            return *this;
+        }
+
+        ///
+        /// @brief Invert entire buffer
+        /// @return buffer_base&, Useful for method chaining
+        ///
+        inline buffer& invert(void)
+        {
+            TT::invert(iv_data);
+            return *this;
+        }
+
+        ///
+        /// @brief Bit reverse entire buffer
+        /// @return buffer_base&, Useful for method chaining
+        ///
+        inline buffer& reverse(void)
+        {
+            TT::reverse(iv_data);
+            return *this;
+        }
+
+
+        ///@}
+
+        /// @name Buffer Manipulation Functions
+        ///@{
+
+        ///
+        /// @brief Get a pointer to the buffer bits
+        /// @return Pointer to the buffer itself
+        ///
+        inline T* pointer(void)
+        {
+            return &iv_data;
+        }
+
+        // Note: Many (all?) of these are not needed and the compiler complains
+        // as the cast to T yields a better operator. There are here mainly for
+        // documenation purposes.
+
+        ///
+        /// @brief operator>>()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator>>(bits_type i_shiftnum);
+#endif
+
+        ///
+        /// @brief operator<<()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator<<(bits_type i_shiftnum);
+#endif
+
+        ///
+        /// @brief operator+()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator+(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator+=()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator+=(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator|=()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator|=(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator&=()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator&=(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator|()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator|(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator&()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator&(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator^=()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator^=(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator~()
+        ///
+#ifdef DOXYGEN
+        inline buffer<T>& operator~(const T& rhs) const;
+#endif
+
+        ///
+        /// @brief operator==()
+        ///
+#ifdef DOXYGEN
+        inline bool operator==(const T& rhs) const;
+#endif
+
+        ///
+        /// @brief operator!=()
+        ///
+#ifdef DOXYGEN
+        inline bool operator!=(const T& rhs) const;
+#endif
+
+        ///
+        /// @brief Copy part of a OT into the DataBuffer
+        /// @tparam TS Start bit to insert into (target start)
+        /// @tparam L Length of bits to insert
+        /// @tparam SS Start bit in source - defaults to bit 0
+        /// @tparam OT the type of the incoming (origin) data
+        /// @param[in] i_datain OT value to copy into DataBuffer
+        ///    - data is taken left aligned
+        /// @return buffer& Useful for method chaining
+        ///
+        template<bits_type TS, bits_type L, bits_type SS = 0, typename OT>
+        inline buffer & insert(const OT i_datain)
+        {
+            const bits_type target_length = parameterTraits<T>::bit_length();
+            const bits_type source_length = parameterTraits<OT>::bit_length();
+
+            // Error if input data don't make sense
+            static_assert((TS + L) <= target_length,
+                          "insert(): (Target Start + Len) is out of bounds");
+            static_assert((SS + L) <= source_length,
+                          "insert(): (Source Start + Len) is out of bounds");
+            static_assert(TS < target_length,
+                          "insert(): Target Start is out of bounds");
+            static_assert(SS < source_length,
+                          "insert(): Source Start is out of bounds");
+
+            // Normalize the input to 2 64 bit integers and adjust the starts accordingly
+            uint64_t source = static_cast<uint64_t>(i_datain);
+            const uint64_t target = static_cast<uint64_t>(iv_data);
+
+            const bits_type source_start = parameterTraits<uint64_t>::bit_length() -
+                                           (source_length - SS);
+            const bits_type target_start = parameterTraits<uint64_t>::bit_length() -
+                                           (target_length - TS);
+
+            // Get mask value for Target buffer
+            // Note: Need "& 0ULL" because bit shift left for Target buffer doesn't roll off
+            uint64_t mask = ((~0ULL << (parameterTraits<uint64_t>::bit_length() - L)) & ~0ULL)
+                            >> target_start;
+
+            // Align the source to the target. Make things signed so we know which way to shift.
+            int32_t shift = source_start - target_start;
+
+            if (shift > 0)
+            {
+                source <<= shift;
+            }
+            else
+            {
+                shift = target_start - source_start;
+                source >>= shift;
+            }
+
+            iv_data = ((target & ~mask) | (source & mask));
+            return *this;
+        }
+
+        ///
+        /// @brief Copy part of a OT into the DataBuffer
+        /// @tparam OT the type of the incoming (origin) data
+        /// @param[in] i_datain      OT value to copy into DataBuffer
+        ///                          - data is taken left aligned
+        /// @param[in] i_targetStart bit to insert into (target start)
+        /// @param[in] i_len         Length of bits to insert
+        /// @param[in] i_sourceStart Start bit in source - defaults to bit 0
+
+        /// @return FAPI2_RC_SUCCESS if successful
+        ///
+        template<typename OT>
+        fapi2::ReturnCodes insert(const OT i_datain, const bits_type i_targetStart,
+                                  const bits_type i_len, const bits_type i_sourceStart = 0)
+        {
+            const bits_type target_length = parameterTraits<T>::bit_length();
+            const bits_type source_length = parameterTraits<OT>::bit_length();
+
+            // Error if input data don't make sense
+            if ((i_targetStart + i_len) > target_length)
+            {
+                FAPI_ERR("insert(): (Target Start + Len) is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            if ((i_sourceStart + i_len) > source_length)
+            {
+                FAPI_ERR("insert(): (Source Start + Len) is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            if (i_targetStart >= target_length)
+            {
+                FAPI_ERR("insert(): Target Start is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            if (i_sourceStart >= source_length)
+            {
+                FAPI_ERR("insert(): Source Start is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            // Normalize the input to 2 64 bit integers and adjust the starts accordingly
+            uint64_t source = static_cast<uint64_t>(i_datain);
+            const uint64_t target = static_cast<uint64_t>(iv_data);
+
+            const bits_type source_start = parameterTraits<uint64_t>::bit_length() -
+                                           (source_length - i_sourceStart);
+            const bits_type target_start = parameterTraits<uint64_t>::bit_length() -
+                                           (target_length - i_targetStart);
+
+            // Get mask value for Target buffer
+            // Note: Need "& 0ULL" because bit shift left for Target buffer doesn't roll off
+            uint64_t mask = ((~0ULL << (parameterTraits<uint64_t>::bit_length() - i_len)) &
+                             ~0ULL) >> target_start;
+
+            // Align the source to the target. Make things signed so we know which way to shift.
+            int32_t shift = source_start - target_start;
+
+            if (shift > 0)
+            {
+                source <<= shift;
+            }
+            else
+            {
+                shift = target_start - source_start;
+                source >>= shift;
+            }
+
+            iv_data = ((target & ~mask) | (source & mask));
+            return FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Copy in a right aligned value
+        /// @tparam SB Start bit to insert into
+        /// @tparam L Length of bits to insert
+        /// @tparam OT the type of the incoming (origin) data
+        /// @param[in] i_datain OT value to copy into DataBuffer
+        ///    - data is taken right aligned
+        /// @return buffer& Useful for method chaining
+        /// @note Data is assumed to be aligned on the word boundary of L
+        ///
+        template<bits_type TS, bits_type L, typename OT>
+        inline buffer& insertFromRight(const OT i_datain)
+        {
+            // Error if input data don't make sense
+            static_assert(L <= parameterTraits<OT>::bit_length(),
+                          "insertFromRight(): Len > input buffer");
+            static_assert(TS < parameterTraits<T>::bit_length(),
+                          "insertFromRight(): Target Start is out of bounds");
+            static_assert((TS + L) <= parameterTraits<T>::bit_length(),
+                          "InsertFromRight(): (Target Start + Len) is out of bounds");
+
+            this->insert < TS, L, parameterTraits<OT>::bit_length() - L > (i_datain);
+            return *this;
+        }
+
+        ///
+        /// @brief Copy in a right aligned value
+        /// @tparam OT the type of the incoming (origin) data
+        /// @param[in] i_datain      OT value to copy into DataBuffer
+        ///                          - data is taken right aligned
+        /// @param[in] i_targetStart Start bit to insert into
+        /// @param[in] i_len         Length of bits to insert
+        /// @return FAPi2_RC_SUCCESS if no error
+        /// @note Data is assumed to be aligned on the word boundary of L
+        ///
+        template<typename OT>
+        fapi2::ReturnCodes insertFromRight(const OT i_datain,
+                                           const bits_type i_targetStart,
+                                           const bits_type i_len)
+        {
+            // Error if input data don't make sense
+            if ((i_targetStart + i_len) > parameterTraits<T>::bit_length())
+            {
+                FAPI_ERR("insertFromRight(): (Target Start + Len) is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            if (i_targetStart >= parameterTraits<T>::bit_length())
+            {
+                FAPI_ERR("insertFromRight(): Target Start is out of bounds");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            if (i_len > parameterTraits<OT>::bit_length())
+            {
+                FAPI_ERR("insertFromRight(): Len > input buffer");
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            return this->insert(i_datain, i_targetStart, i_len,
+                                parameterTraits<OT>::bit_length() - i_len);
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT
+        /// @tparam SS Start bit in source
+        /// @tparam L Length of bits to insert
+        /// @tparam TS Start bit to insert into (target start)
+        /// @tparam OT the type of the outgoing (target)
+        /// @param[out] o_out OT to copy into - data is placed left aligned
+        /// @return const buffer& Useful for method chaining
+        ///
+        template<bits_type SS, bits_type L, bits_type TS = 0, typename OT>
+        inline const buffer & extract(OT& o_out) const
+        {
+            // Extraction is just an insert into o_out
+
+            buffer<OT> out(o_out);
+            out.insert<TS, L, SS>(iv_data);
+            o_out = out;
+            return *this;
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT
+        /// @tparam SS Start bit in source
+        /// @tparam L Length of bits to insert
+        /// @tparam TS Start bit to insert into (target start)
+        /// @tparam OT the type of the outgoing (target)
+        /// @param[out] o_out OT to copy into - data is placed left aligned
+        /// @return buffer& Useful for method chaining
+        ///
+        template<bits_type SS, bits_type L, bits_type TS = 0, typename OT>
+        inline buffer & extract(OT& o_out)
+        {
+            // Extraction is just an insert into o_out
+
+            buffer<OT> out(o_out);
+            out.insert<TS, L, SS>(iv_data);
+            o_out = out;
+            return *this;
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT
+        /// @tparam OT the type of the outgoing (target)
+        /// @param[out] o_out        OT to copy into - data is placed left aligned
+        /// @param[in] i_sourceStart Start bit in source
+        /// @param[in] i_len         Length of bits to extract
+        /// @param[in] i_targetStart Start bit to insert into (target start)
+        /// @return FAPI2_RC_SUCCESS if ok
+        ///
+        template<typename OT>
+        fapi2::ReturnCodes extract(OT& o_out, const bits_type i_sourceStart,
+                                   const bits_type i_len, const bits_type i_targetStart = 0) const
+        {
+            // Extraction is just an insert into o_out
+
+            buffer<OT> out(o_out);
+
+            if (out.insert(iv_data, i_targetStart, i_len,
+                           i_sourceStart) != FAPI2_RC_SUCCESS)
+            {
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            o_out = out;
+            return FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT and right justify
+        /// @tparam SS Start bit to insert into (source start)
+        /// @tparam L Length of bits to extract
+        /// @tparam OT the type of the outgoing (target)
+        /// @param[out] o_out OT to copy into - data is placed right aligned
+        /// @return const buffer& Useful for method chaining
+        ///
+        template<bits_type SS, bits_type L, typename OT>
+        inline const buffer& extractToRight(OT& o_out) const
+        {
+            extract < SS, L, parameterTraits<OT>::bit_length() - L > (o_out);
+            return *this;
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT and right justify
+        /// @tparam SS Start bit to insert into (source start)
+        /// @tparam L Length of bits to extract
+        /// @tparam OT the type of the outgoing (target)
+        /// @param[out] o_out OT to copy into - data is placed right aligned
+        /// @return buffer& Useful for method chaining
+        ///
+        template<bits_type SS, bits_type L, typename OT>
+        inline buffer& extractToRight(OT& o_out)
+        {
+            extract < SS, L, parameterTraits<OT>::bit_length() - L > (o_out);
+            return *this;
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT and right justify
+        /// @tparam OT the type of the outgoing (target)
+        /// @param[out] o_out        OT to copy into - data is placed right aligned
+        /// @param[in] i_sourceStart Start bit to insert into (source start)
+        /// @param[in] i_len         Length of bits to insert
+        /// @return FAPI2_RC_SUCCESS if ok
+        ///
+        template<typename OT>
+        fapi2::ReturnCodes extractToRight(OT& o_out, const bits_type i_sourceStart,
+                                          const bits_type i_len) const
+        {
+            return extract(o_out, i_sourceStart, i_len,
+                           parameterTraits<OT>::bit_length() - i_len);
+        }
+
+        ///@}
+
+    private:
+        /// The contents of the buffer
+        T iv_data;
+};
+}
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/buffer_parameters.H b/src/import/hwpf/fapi2/include/buffer_parameters.H
new file mode 100644
index 00000000..aea03c66
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/buffer_parameters.H
@@ -0,0 +1,76 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/buffer_parameters.H $               */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file buffer_parameters.H
+ * @brief definitions for fapi2 buffer parameter types
+ */
+
+#ifndef __FAPI2_BUFFER_PARAM__
+#define __FAPI2_BUFFER_PARAM__
+
+#include <stdint.h>
+
+namespace fapi2
+{
+/// @cond
+/// @brief Traits of buffer parameters - things passed in
+/// @tparam T is the type of i_value (typically an integral type)
+template<typename T>
+class parameterTraits
+{
+    public:
+        // Why constexpr functions? Enums are hard to do math on, and
+        // static const doesn't work without -O1 (or greater.) That might
+        // be a bug in g++ but this works just the same.
+        constexpr static T mask(void)
+        {
+            return T(~0);
+        }
+
+        constexpr static uint32_t byte_length(void)
+        {
+            return sizeof(T);
+        }
+
+        constexpr static uint32_t bit_length(void)
+        {
+            return sizeof(T) * 8;
+        }
+
+        template<typename U>
+        inline static void write_element(void* i_data, T i_value, uint32_t i_offset)
+        {
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+            T* ptr = (T*)i_data + (i_offset ^ ((sizeof(U) / sizeof(T)) - 1));
+#else
+            T* ptr = (T*)i_data + i_offset;
+#endif
+            *ptr = i_value;
+        }
+};
+/// @endcond
+}
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/buffer_traits.H b/src/import/hwpf/fapi2/include/buffer_traits.H
new file mode 100644
index 00000000..b14df7ea
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/buffer_traits.H
@@ -0,0 +1,275 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/buffer_traits.H $                   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file buffer_traits.H
+ * @brief trait definitions for fapi2 buffer base class
+ */
+
+#ifndef __FAPI2_BUFFER_TRAITS__
+#define __FAPI2_BUFFER_TRAITS__
+
+#include <stdint.h>
+#include <vector>
+#include <algorithm>
+#include <buffer_parameters.H>
+
+#ifdef FAPI2_DEBUG
+    #include <iostream>
+#endif
+
+#include <iterator>
+
+namespace fapi2
+{
+/// @cond
+/// Types representing a container of bits. Used to create
+/// variable_buffer. container_unit must remain 32-bits
+/// for now - there will be a lot of code to change if it
+/// changes. There are assertions helping to enforce this
+/// in places in the code.
+typedef uint32_t container_unit;
+typedef std::vector<container_unit> bits_container;
+
+/// @brief Traits of buffers
+// In general, we try to give buffers traits reflecting integral types. If
+// this fails, the compiler will let someone know.
+///
+/// @tparam T is the type of iv_data (std::vector, etc)
+/// @tparam B is the type of the bit-specifier, typically uint32_t
+template<typename T, typename B = uint32_t>
+class bufferTraits
+{
+    public:
+
+#if !defined(DOXYGEN) && defined(FAPI2_DEBUG)
+        ///
+        /// @brief Print a container of bits
+        /// @param[in] i_data the container of bits
+        ///
+        static inline void print(const T& i_data)
+        {
+            // convert to uint64_t to prevent uint8_t from being
+            // printed as a char.
+            std::cout << "\tdata is "
+                      << std::hex
+                      << static_cast<uint64_t>(i_data)
+                      << std::dec << std::endl;
+        }
+#endif
+
+        ///
+        /// @brief Return the size of the buffer in E units
+        /// @tparam E, the element size.
+        /// @param[in] i_buffer the buffer which to size
+        /// @return The size of the buffer in E's rounded up
+        ///
+        template<typename E>
+        constexpr static B size(const T& i_buffer)
+        {
+            return (bit_length(i_buffer) +
+                    (parameterTraits<E>::bit_length() - 1)) /
+                   parameterTraits<E>::bit_length();
+        }
+
+        ///
+        /// @brief Return the size of the buffer itself
+        /// @param[in] i_buffer the buffer which to size
+        /// @return The size of the buffer in bits (not units)
+        ///
+        constexpr static B bit_length(const T&)
+        {
+            return sizeof(T) * 8;
+        }
+
+        ///
+        /// @brief Clear the buffer
+        /// @param[in,out] io_buffer the buffer which to clear
+        ///
+        static inline void clear(T& io_buffer)
+        {
+            io_buffer = static_cast<T>(0);
+        }
+
+        ///
+        /// @brief Set the buffer
+        /// @param[in,out] io_buffer the buffer which to set
+        ///
+        static inline void set(T& io_buffer)
+        {
+            io_buffer = static_cast<T>(~0);
+        }
+
+        ///
+        /// @brief Invert the buffer
+        /// @param[in,out] io_buffer the buffer which to invert
+        ///
+        static inline void invert(T& io_buffer)
+        {
+            io_buffer = ~io_buffer;
+        }
+
+        ///
+        /// @brief Reverse the buffer
+        /// @param[in,out] io_buffer the buffer which to reverse
+        //
+        //  @note from
+        //   http://stackoverflow.com/questions/746171/best-algorithm-for-bit-reversal-from-msb-lsb-to-lsb-msb-in-c
+        ///
+        static inline void reverse( T& io_buffer)
+        {
+            T l_result = io_buffer;
+            size_t l_s = sizeof(T) * 8 - 1;
+
+            for( io_buffer >>= 1; io_buffer; io_buffer >>= 1)
+            {
+                l_result <<= 1;
+                l_result |= io_buffer & 1;
+                l_s--;
+            }
+
+            l_result <<= l_s;
+
+            io_buffer = l_result;
+        }
+        ///
+        /// @brief Get the address of the buffer as an array
+        /// @param[in] i_buffer the buffer which to invert
+        /// @return The address of the first element of the buffer
+        ///
+        static inline void* get_address(T& i_buffer)
+        {
+            return (void*)&i_buffer;
+        }
+
+        typedef B bits_type;
+        typedef T unit_type;
+        constexpr static uint32_t bits_per_unit(void)
+        {
+            return sizeof(unit_type) * 8;
+        }
+};
+
+//
+//
+/// @brief Traits for buffers which are a container of bits
+//
+//
+template<>
+class bufferTraits<bits_container, uint32_t>
+{
+    public:
+#if !defined(DOXYGEN) && defined(FAPI2_DEBUG)
+        ///
+        /// @brief Print a container of bits
+        /// @param[in] i_data the container of bits
+        ///
+        static inline void print(const bits_container& i_data)
+        {
+            std::cout << "\tdata is " << std::hex;
+            std::copy(i_data.begin(), i_data.end(),
+                      std::ostream_iterator<container_unit>(std::cout, " "));
+            std::cout << std::dec << std::endl;
+        }
+#endif
+
+        ///
+        /// @brief Return the size of the buffer in E units
+        /// @tparam E, the element size.
+        /// @param[in] i_buffer the buffer which to size
+        /// @return The size of the buffer in E's rounded up
+        ///
+        template<typename E>
+        constexpr static uint32_t size(const bits_container& i_buffer)
+        {
+            return (bit_length(i_buffer) +
+                    (parameterTraits<E>::bit_length() - 1)) /
+                   parameterTraits<E>::bit_length();
+        }
+
+        ///
+        /// @brief Return the size of the buffer itself
+        /// @param[in] i_buffer the buffer which to size
+        /// @return The size of the buffer in bits (not units)
+        ///
+        static inline uint32_t bit_length(const bits_container& i_buffer)
+        {
+            return i_buffer.size() * sizeof(container_unit) * 8;
+        }
+
+        ///
+        /// @brief Clear the buffer
+        /// @param[in,out] io_buffer the buffer which to clear
+        ///
+        static inline void clear(bits_container& io_buffer)
+        {
+            io_buffer.assign(io_buffer.size(), 0);
+        }
+
+        ///
+        /// @brief Set the buffer
+        /// @param[in,out] io_buffer the buffer which to set
+        ///
+        static inline void set(bits_container& io_buffer)
+        {
+            io_buffer.assign(io_buffer.size(), ~0);
+        }
+
+        ///
+        /// @brief Invert the buffer
+        /// @param[in,out] io_buffer the buffer which to invert
+        ///
+        static inline void invert(bits_container& io_buffer)
+        {
+            std::transform(io_buffer.begin(), io_buffer.end(),
+                           io_buffer.begin(),
+                           [](container_unit u)
+            {
+                return ~u;
+            });
+        }
+
+        ///
+        /// @brief Get the address of the buffer as an array
+        /// @param[in] i_buffer the buffer which to invert
+        /// @return The address of the first element of the buffer
+        ///
+        static inline void* get_address(bits_container& i_buffer)
+        {
+            return (void*) & (i_buffer[0]);
+        }
+
+        typedef uint32_t bits_type;
+        typedef container_unit unit_type;
+        constexpr static uint32_t bits_per_unit(void)
+        {
+            return sizeof(unit_type) * 8;
+        }
+};
+/// @endcond
+}
+
+
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/error_info.H b/src/import/hwpf/fapi2/include/error_info.H
new file mode 100644
index 00000000..9f0e0419
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/error_info.H
@@ -0,0 +1,686 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/error_info.H $                      */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file error_info.H
+/// @brief Defines the Error Information structures and classes
+///
+
+#ifndef FAPI2_ERRORINFO_H_
+#define FAPI2_ERRORINFO_H_
+
+#include <stdint.h>
+#include <memory>
+#include <vector>
+#include <target.H>
+#include <error_info_defs.H>
+
+namespace fapi2
+{
+
+#if defined(MINIMUM_FFDC) && !defined(FAPI2_NO_FFDC)
+// convert generic type to uint64_t
+template<typename T>
+inline uint64_t convertType( T& i_value )
+{
+    // for simplicity sake, all FFDC chunks from the SBE
+    // are going to be sent as a uint64_t
+    return static_cast<uint64_t>(i_value);
+};
+
+// convert platform target handle to a uint64_t
+template<fapi2::TargetType T>
+inline uint64_t convertType( const fapi2::Target<T>& i_value)
+{
+    // send the target type and instance as ffdc they will be used
+    // to instantiate a target before logging the ffdc data
+    return static_cast<uint64_t>((static_cast<uint64_t>(
+                                      (i_value.get().getFapiTargetType())) << 32) |
+                                 i_value.get().getTargetInstance());
+};
+#endif
+
+#if !defined(FAPI2_NO_FFDC) && !defined(MINIMUM_FFDC)
+// forward fapi2::Assert()
+extern void Assert(bool);
+
+///
+/// @class ErrorInfoFfdc
+///
+/// This class contains a copy of some FFDC data
+///
+class ErrorInfoFfdc
+{
+    public:
+        ///
+        /// @brief Constructor
+        ///
+        /// @param[in] i_ffdcId FFDC Identifier (used to decode FFDC)
+        /// @param[in] i_pFfdc  Pointer to the FFDC to copy
+        /// @param[in] i_size   Size of the FFDC to copy
+        ///
+        ErrorInfoFfdc(const uint32_t i_ffdcId,
+                      const void*    i_pFfdc,
+                      const uint32_t i_size);
+
+        ///
+        /// @brief Get a pointer to the FfdcData
+        ///
+        /// @param[out] o_size Reference to uint32_t that is filled in with
+        /// the FFDC size
+        ///
+        /// @return void *. Pointer to the FFDC
+        ///
+        inline const void* getData(uint32_t& o_size) const
+        {
+            o_size = iv_size;
+            return iv_pFfdc.get();
+        }
+
+        ///
+        /// @brief Get a pointer to the FfdcData
+        /// @return void *. Pointer to the FFDC
+        ///
+        inline void* getData(void) const
+        {
+            return iv_pFfdc.get();
+        }
+
+        ///
+        /// @brief Get the FFDC Identifier
+        ///
+        /// @return uint32_t The FFDC Identifier
+        ///
+        inline uint32_t getFfdcId(void)
+        {
+            return iv_ffdcId;
+        }
+
+#ifdef FAPI_CUSTOM_MALLOC
+        ///
+        /// @brief Overload new operator to use platform-specific allocator
+        ///
+        /// @param[in] i_sz  Size of memory to allocate in bytes
+        ///
+        /// @return  Pointer to allocated memory
+        ///
+        static void* operator new(size_t i_sz);
+
+        ///
+        /// @brief Overload delete operator to use platform-specific deallocator
+        ///
+        /// @param[in] i_ptr Pointer to memory previously allocated with new
+        ///
+        static void operator delete(void* i_ptr);
+#endif
+
+    private:
+
+        // FFDC Identifier
+        uint32_t iv_ffdcId;
+
+        // Pointer to the FFDC
+        std::shared_ptr<uint8_t> iv_pFfdc;
+
+        // Size of the FFDC
+        uint32_t iv_size;
+
+        // Disabled
+        ErrorInfoFfdc(const ErrorInfoFfdc&) = delete;
+        ErrorInfoFfdc& operator=(const ErrorInfoFfdc&) = delete;
+};
+
+///
+/// @struct ErrorInfoHwCallout
+///
+/// This struct contains hardware to callout
+///
+struct ErrorInfoHwCallout
+{
+    ///
+    /// @brief Constructor.
+    ///
+    /// @param[in] i_hw              Hardware to callout
+    /// @param[in] i_calloutPriority Priority of callout
+    /// @param[in] i_refTarget       Reference to reference target
+    ///
+    ErrorInfoHwCallout(
+        const HwCallouts::HwCallout i_hw,
+        const CalloutPriorities::CalloutPriority i_calloutPriority,
+        const Target<TARGET_TYPE_ALL>& i_refTarget);
+
+#ifdef FAPI_CUSTOM_MALLOC
+    ///
+    /// @brief Overload new operator to use platform-specific allocator
+    ///
+    /// @param[in] i_sz  Size of memory to allocate in bytes
+    ///
+    /// @return  Pointer to allocated memory
+    ///
+    static void* operator new(size_t i_sz);
+
+    ///
+    /// @brief Overload delete operator to use platform-specific deallocator
+    ///
+    /// @param[in] i_ptr Pointer to memory previously allocated with new
+    ///
+    static void operator delete(void* i_ptr);
+#endif
+
+    // The hw to callout
+    HwCallouts::HwCallout iv_hw;
+
+    // The callout priority
+    CalloutPriorities::CalloutPriority iv_calloutPriority;
+
+    // The reference target (needed for some HW callouts to identify what to
+    // callout). The target handle is NULL if there is no reference target.
+    Target<TARGET_TYPE_ALL> iv_refTarget;
+};
+
+///
+/// @struct ErrorInfoProcedureCallout
+///
+/// This struct contains a procedure to callout
+///
+struct ErrorInfoProcedureCallout
+{
+    ///
+    /// @brief Constructor.
+    ///
+    /// @param[in] i_procedure        Procedure to callout
+    /// @param[in] i_calloutPriority  Priority of callout
+    ///
+    ErrorInfoProcedureCallout(
+        const ProcedureCallouts::ProcedureCallout i_procedure,
+        const CalloutPriorities::CalloutPriority i_calloutPriority);
+
+#ifdef FAPI_CUSTOM_MALLOC
+    ///
+    /// @brief Overload new operator to use platform-specific allocator
+    ///
+    /// @param[in] i_sz  Size of memory to allocate in bytes
+    ///
+    /// @return  Pointer to allocated memory
+    ///
+    static void* operator new(size_t i_sz);
+
+    ///
+    /// @brief Overload delete operator to use platform-specific deallocator
+    ///
+    /// @param[in] i_ptr Pointer to memory previously allocated with new
+    ///
+    static void operator delete(void* i_ptr);
+#endif
+
+    // The procedure to callout
+    ProcedureCallouts::ProcedureCallout iv_procedure;
+
+    // The callout priority
+    CalloutPriorities::CalloutPriority iv_calloutPriority;
+};
+
+///
+/// @struct ErrorInfoBusCallout
+///
+/// This struct contains a bus to callout
+///
+struct ErrorInfoBusCallout
+{
+    ///
+    /// @brief Constructor.
+    ///
+    /// @param[in] i_target1          Reference to target on one end of the bus
+    /// @param[in] i_target2          Reference to target on other end of the bus
+    /// @param[in] i_calloutPriority  Priority of callout
+    ///
+    ErrorInfoBusCallout(
+        const Target<TARGET_TYPE_ALL>& i_target1,
+        const Target<TARGET_TYPE_ALL>& i_target2,
+        const CalloutPriorities::CalloutPriority i_calloutPriority);
+
+#ifdef FAPI_CUSTOM_MALLOC
+    ///
+    /// @brief Overload new operator to use platform-specific allocator
+    ///
+    /// @param[in] i_sz  Size of memory to allocate in bytes
+    ///
+    /// @return  Pointer to allocated memory
+    ///
+    static void* operator new(size_t i_sz);
+
+    ///
+    /// @brief Overload delete operator to use platform-specific deallocator
+    ///
+    /// @param[in] i_ptr Pointer to memory previously allocated with new
+    ///
+    static void operator delete(void* i_ptr);
+#endif
+
+    // The targets on each end of the bus to callout
+    Target<TARGET_TYPE_ALL> iv_target1;
+    Target<TARGET_TYPE_ALL> iv_target2;
+
+    // The callout priority
+    CalloutPriorities::CalloutPriority iv_calloutPriority;
+};
+
+///
+/// @struct ErrorInfoCDG
+///
+/// This struct contains a target to callout/deconfigure/GARD
+///
+struct ErrorInfoCDG
+{
+    ///
+    /// @brief Constructor.
+    ///
+    /// @param[in] i_target      Reference to the target to c/d/g
+    /// @param[in] i_callout     True if Target should be called out
+    /// @param[in] i_deconfigure True if Target should be deconfigured
+    /// @param[in] i_gard        True if Target should be GARDed
+    /// @param[in] i_priority    The priority of any callout
+    ///
+    ErrorInfoCDG(const Target<TARGET_TYPE_ALL>& i_target,
+                 const bool i_callout,
+                 const bool i_deconfigure,
+                 const bool i_gard,
+                 const CalloutPriorities::CalloutPriority i_priority);
+
+#ifdef FAPI_CUSTOM_MALLOC
+    ///
+    /// @brief Overload new operator to use platform-specific allocator
+    ///
+    /// @param[in] i_sz  Size of memory to allocate in bytes
+    ///
+    /// @return  Pointer to allocated memory
+    ///
+    static void* operator new(size_t i_sz);
+
+    ///
+    /// @brief Overload delete operator to use platform-specific deallocator
+    ///
+    /// @param[in] i_ptr Pointer to memory previously allocated with new
+    ///
+    static void operator delete(void* i_ptr);
+#endif
+
+    // The target to callout/deconfigure/GARD
+    Target<TARGET_TYPE_ALL> iv_target;
+
+    // Callout Information
+    bool iv_callout;
+    CalloutPriorities::CalloutPriority iv_calloutPriority;
+
+    // Deconfigure Information
+    bool iv_deconfigure;
+
+    // GARD Information
+    bool iv_gard;
+};
+
+///
+/// @struct ErrorInfoChildrenCDG
+///
+/// This struct contains children targets to callout/deconfigure/GARD
+///
+/// Children by containment can be CDG (chiplets belonging to a parent chip)
+/// e.g.
+/// - PROC_CHIP -> EX_CHIPLET
+/// - MEMBUF_CHIP -> MBA_CHIPLET
+/// Children by affinity can be CDG.
+///   Any from PROC_CHIP->MCS_CHIPLET->MEMBUF_CHIP->MBA_CHIPLET->DIMM e.g.
+///   - PROC_CHIP->MEMBUF_CHIP
+///   - MEMBUF_CHIP->DIMM
+///   - MBA_CHIPLET->DIMM
+/// Port and Number criteria can be applied to the child target as
+/// detailed in the constructor
+///
+struct ErrorInfoChildrenCDG
+{
+    ///
+    /// @brief Constructor.
+    ///
+    /// @param[in] i_parentChip  Reference to the parent target
+    /// @param[in] i_childType   Child target type to c/d/g
+    /// @param[in] i_callout     True if Target should be called out
+    /// @param[in] i_deconfigure True if Target should be deconfigured
+    /// @param[in] i_gard        True if Target should be GARDed
+    /// @param[in] i_priority    The priority of any callout
+    /// @param[in] i_childPort   Child Port
+    ///                            For DIMM children, the MBA port number
+    /// @param[in] i_childNum    Child Number
+    ///                            For DIMM children, the dimm socket number
+    ///                            For Chip children, the chip position
+    ///                            For Chiplet children, the chiplet unit pos
+    ///
+    ErrorInfoChildrenCDG(const Target<TARGET_TYPE_ALL>& i_parentChip,
+                         const TargetType i_childType,
+                         const bool i_callout,
+                         const bool i_deconfigure,
+                         const bool i_gard,
+                         const CalloutPriorities::CalloutPriority i_priority,
+                         const uint8_t i_childPort, const uint8_t i_childNum);
+
+#ifdef FAPI_CUSTOM_MALLOC
+    ///
+    /// @brief Overload new operator to use platform-specific allocator
+    ///
+    /// @param[in] i_sz  Size of memory to allocate in bytes
+    ///
+    /// @return  Pointer to allocated memory
+    ///
+    static void* operator new(size_t i_sz);
+
+    ///
+    /// @brief Overload delete operator to use platform-specific deallocator
+    ///
+    /// @param[in] i_ptr Pointer to memory previously allocated with new
+    ///
+    static void operator delete(void* i_ptr);
+#endif
+
+    // The parent chip
+    Target<TARGET_TYPE_ALL> iv_parent;
+
+    // The child target types to c/d/g
+    TargetType iv_childType;
+
+    // Callout Information
+    bool iv_callout;
+    CalloutPriorities::CalloutPriority iv_calloutPriority;
+
+    // Deconfigure Information
+    bool iv_deconfigure;
+
+    // GARD Information
+    bool iv_gard;
+
+    // Child Port
+    static const uint8_t ALL_CHILD_PORTS = 0xff;
+    uint8_t iv_childPort;
+
+    // Child Number
+    static const uint8_t ALL_CHILD_NUMBERS = 0xff;
+    uint8_t iv_childNumber;
+};
+
+///
+/// @struct ErrorInfoCollectTrace
+///
+/// This struct contains trace ID to add to the error log
+///
+struct ErrorInfoCollectTrace
+{
+    ///
+    /// @brief Constructor.
+    ///
+    /// @param[in] i_traceId
+    ///
+    ErrorInfoCollectTrace(CollectTraces::CollectTrace i_traceId);
+
+
+#ifdef FAPI_CUSTOM_MALLOC
+    ///
+    /// @brief Overload new operator to use platform-specific allocator
+    ///
+    /// @param[in] i_sz  Size of memory to allocate in bytes
+    ///
+    /// @return  Pointer to allocated memory
+    ///
+    static void* operator new(size_t i_sz);
+
+    ///
+    /// @brief Overload delete operator to use platform-specific deallocator
+    ///
+    /// @param[in] i_ptr Pointer to memory previously allocated with new
+    ///
+    static void operator delete(void* i_ptr);
+#endif
+
+    // trace
+    CollectTraces::CollectTrace iv_eiTraceId;
+};
+
+///
+/// @struct ErrorInfo
+///
+/// This struct defines the error information associated with a fapi2::ffdc
+/// Users are allowed to access the data directly
+///
+struct ErrorInfo
+{
+
+#ifdef FAPI_CUSTOM_MALLOC
+    ///
+    /// @brief Overload new operator to use platform-specific allocator
+    ///
+    /// @param[in] i_sz  Size of memory to allocate in bytes
+    ///
+    /// @return  Pointer to allocated memory
+    ///
+    static void* operator new(size_t i_sz);
+
+    ///
+    /// @brief Overload delete operator to use platform-specific deallocator
+    ///
+    /// @param[in] i_ptr Pointer to memory previously allocated with new
+    ///
+    static void operator delete(void* i_ptr);
+#endif
+
+    // Vector of FFDC Data
+    std::vector<std::shared_ptr<ErrorInfoFfdc> > iv_ffdcs;
+
+    // Vector of Hardware to callout
+    std::vector<std::shared_ptr<ErrorInfoHwCallout> > iv_hwCallouts;
+
+    // Vector of procedures to callout
+    std::vector<std::shared_ptr<ErrorInfoProcedureCallout> >
+    iv_procedureCallouts;
+
+    // Vector of buses to callout
+    std::vector<std::shared_ptr<ErrorInfoBusCallout> > iv_busCallouts;
+
+    // Vector of targets to callout/deconfigure/GARD
+    std::vector<std::shared_ptr<ErrorInfoCDG> > iv_CDGs;
+
+    // Vector of children targets to callout/deconfigure/GARD
+    std::vector<std::shared_ptr<ErrorInfoChildrenCDG> > iv_childrenCDGs;
+
+    // Vector of traces to collect
+    std::vector<std::shared_ptr<ErrorInfoCollectTrace> > iv_traces;
+};
+///
+/// @brief Structure representing a single ErrorInfo entry.
+///
+/// An array of these is passed to the addErrorInfo function when a HWP
+/// generates an error by calling the FAPI_SET_HWP_ERROR macro
+// Why aren't these inherited classes? Saves on allocation overhead.
+// We create an array of ErrorInfoEntries as automatics when we start
+// FFDC collection. If we did this as inherited classes it would either
+// be allocating and deallocating or we'd need to allocate an array of
+// the largest and map each struct in to it. That's messy to do without
+// unions (that's what they're for) so we do it like this. The inherited
+// model would result in a jump table anyway, so we're basically doing
+// all of that by hand to avoid the mess.
+//
+struct ErrorInfoEntryFfdc
+{
+    uint8_t  iv_ffdcObjIndex;
+    uint16_t iv_ffdcSize;
+    uint32_t iv_ffdcId;
+    void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                      const void* const* i_object) const;
+};
+
+///
+/// @brief Structure representing a hardware callout
+///
+struct ErrorInfoEntryHwCallout
+{
+    uint8_t iv_hw;
+    uint8_t iv_calloutPriority;
+    uint8_t iv_refObjIndex;
+    void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                      const void* const* i_object) const;
+};
+
+///
+/// @brief Structure representing a procedure callout
+///
+struct ErrorInfoEntryProcCallout
+{
+    uint8_t iv_procedure;
+    uint8_t iv_calloutPriority;
+    void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                      const void* const* i_object) const;
+
+    ErrorInfoEntryProcCallout(uint8_t i_procedure, uint8_t i_calloutPriority):
+        iv_procedure(i_procedure),
+        iv_calloutPriority(i_calloutPriority)
+    {}
+
+    ErrorInfoEntryProcCallout(void) = default;
+};
+
+///
+/// @brief Structure representing a bus callout
+///
+struct ErrorInfoEntryBusCallout
+{
+    uint8_t iv_endpoint1ObjIndex;
+    uint8_t iv_endpoint2ObjIndex;
+    uint8_t iv_calloutPriority;
+    void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                      const void* const* i_object) const;
+};
+
+///
+/// @brief Structure representing a target callout
+///
+struct ErrorInfoEntryTargetCDG
+{
+    uint8_t iv_targetObjIndex;
+    uint8_t iv_callout;
+    uint8_t iv_deconfigure;
+    uint8_t iv_gard;
+    uint8_t iv_calloutPriority;
+    void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                      const void* const* i_object) const;
+};
+
+///
+/// @brief Structure representing a child callout
+///
+struct ErrorInfoEntryChildrenCDG
+{
+    uint8_t  iv_parentObjIndex;
+    uint8_t  iv_callout;
+    uint8_t  iv_deconfigure;
+    uint32_t iv_childType;
+    uint8_t  iv_childPort;
+    uint8_t  iv_childNumber;
+    uint8_t  iv_gard;
+    uint8_t  iv_calloutPriority;
+    void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                      const void* const* i_object) const;
+};
+
+///
+/// @brief Structure representing collected trace information
+///
+struct ErrorInfoEntryCollectTrace
+{
+    uint32_t  iv_eieTraceId;
+    void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                      const void* const* i_object) const;
+};
+
+///
+/// @brief Union of all the error info types
+///
+struct ErrorInfoEntry
+{
+    uint8_t iv_type; // Value from ErrorInfoType
+    union
+    {
+        ErrorInfoEntryFfdc ffdc;
+        ErrorInfoEntryHwCallout hw_callout;
+        ErrorInfoEntryProcCallout proc_callout;
+        ErrorInfoEntryBusCallout bus_callout;
+        ErrorInfoEntryTargetCDG target_cdg;
+        ErrorInfoEntryChildrenCDG children_cdg;
+        ErrorInfoEntryCollectTrace collect_trace;
+    };
+
+    ///
+    /// @brief Add error information to the FFDC object
+    /// @param[in] i_info a shared pointer to the error info
+    /// @param[in] i_object the list of ffdc objects being collected
+    ///
+    void addErrorInfo(std::shared_ptr<ErrorInfo> i_info,
+                      const void* const* i_object) const
+    {
+        // "unhandled error info type");
+        fapi2::Assert(iv_type < EI_LAST_TYPE);
+
+        switch(iv_type)
+        {
+            case EI_TYPE_FFDC:
+                ffdc.addErrorInfo(i_info, i_object);
+                break;
+
+            case EI_TYPE_HW_CALLOUT:
+                hw_callout.addErrorInfo(i_info, i_object);
+                break;
+
+            case EI_TYPE_PROCEDURE_CALLOUT:
+                proc_callout.addErrorInfo(i_info, i_object);
+                break;
+
+            case EI_TYPE_BUS_CALLOUT:
+                bus_callout.addErrorInfo(i_info, i_object);
+                break;
+
+            case EI_TYPE_CDG:
+                target_cdg.addErrorInfo(i_info, i_object);
+                break;
+
+            case EI_TYPE_CHILDREN_CDG:
+                children_cdg.addErrorInfo(i_info, i_object);
+                break;
+
+            case EI_TYPE_COLLECT_TRACE:
+                collect_trace.addErrorInfo(i_info, i_object);
+                break;
+        };
+
+        return;
+    }
+};
+#endif //  !defined(FAPI2_NO_FFDC) && !defined(MINIMUM_FFDC)
+}
+#endif // FAPI2_ERRORINFO_H_
diff --git a/src/import/hwpf/fapi2/include/error_info_defs.H b/src/import/hwpf/fapi2/include/error_info_defs.H
new file mode 100644
index 00000000..c67e4061
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/error_info_defs.H
@@ -0,0 +1,344 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/error_info_defs.H $                 */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file error_info_defs.H
+/// @brief Defines to support the Error Information class
+///
+
+#ifndef FAPI2_ERRORINFO_DEFS_H_
+#define FAPI2_ERRORINFO_DEFS_H_
+
+#include <stdint.h>
+#include <target.H>
+
+#if !defined(MINIMUM_FFDC) && !defined(FAPI2_NO_FFDC)
+    #include <variable_buffer.H>
+    #include <utility>
+#endif
+namespace fapi2
+{
+
+// $TEMP - funciton temp function to pass compiling
+template<TargetType T>
+Target<T>* getTarget(TargetType type, uint8_t instance)
+{
+    static_cast<void>(type);
+    static_cast<void>(instance);
+    return new Target<T>(0);
+}
+
+///
+/// @brief Type to hold the ffdc data to be sent to hostboot
+///
+/// Note: Typical data sent seems to be register/addresss info
+///       rather than use extra space converting stuff just
+///       send a uint64 always
+///
+struct sbeFfdc_t
+{
+    uint32_t  size;
+    uint64_t  data;
+};
+
+// 10 entries limits the size of SbeFfdcData_t to 128 bytes
+enum
+{
+    MAX_SBE_FFDC_ENTRIES = 10
+};
+
+// Data type for SBE ffdc buffer sent through fifo
+typedef struct
+{
+    uint32_t  fapiRc;      // Return code from failure
+    uint32_t  ffdcLength;  // length of Fapi FFDC data (in bytes)
+    struct sbeFfdc_t ffdcData[MAX_SBE_FFDC_ENTRIES]; // fapi FFDC data
+} SbeFfdcData_t; // 128 bytes
+
+///
+/// @brief Type to hold the ffdc element in the ffdc class
+/// Needed so that the size can be squirled away before the
+/// macro is called.
+///
+struct ffdc_struct
+{
+    const void* ptr;
+    int16_t size;
+};
+
+
+class ffdc_t
+{
+    public:
+        ffdc_t(void)
+        {}
+
+        void operator=(const ffdc_t& i )
+        {
+            iv_value.ptr  = i.ptr();
+            iv_value.size = i.size();
+        }
+
+        operator const void* () const
+        {
+            return iv_value.ptr;
+        }
+        operator uint8_t() const
+        {
+            return *(reinterpret_cast<const uint8_t*>(iv_value.ptr));
+        }
+
+        int16_t size(void) const
+        {
+            return iv_value.size;
+        }
+        int16_t& size(void)
+        {
+            return iv_value.size;
+        }
+
+        const void* ptr(void) const
+        {
+            return iv_value.ptr;
+        }
+        const void*& ptr(void)
+        {
+            return iv_value.ptr;
+        }
+
+    private:
+        struct ffdc_struct iv_value;
+};
+
+///
+/// @brief Enumeration of ErrorInfo FFDC sizes that are used to indicate a
+///        special type that cannot simply be memcopied
+enum ErrorInfoFfdcSize
+{
+    EI_FFDC_SIZE_BUF    = 0xffff,   // fapi2::buffer<T>
+    EI_FFDC_SIZE_TARGET = 0xfffe,   // fapi2::Target
+    EI_FFDC_SIZE_VBUF   = 0xfffd,   // fapi2::variable_buffer
+    EI_FFDC_MAX_SIZE    = 0x1000,   // Limit regular FFDC capture to 4kb
+};
+
+///
+/// @brief Enumeration of error log severity.
+///
+enum errlSeverity_t
+{
+    FAPI2_ERRL_SEV_UNDEFINED     = 0x00, /// Used internally by ffdc mechanism
+    FAPI2_ERRL_SEV_RECOVERED     = 0x10, /// Not seen by customer
+    FAPI2_ERRL_SEV_PREDICTIVE    = 0x20, /// Error recovered but customer will see
+    FAPI2_ERRL_SEV_UNRECOVERABLE = 0x40  /// Unrecoverable, general
+};
+
+///
+/// @brief Enumeration of ErrorInfo types
+///
+enum ErrorInfoType
+{
+    EI_TYPE_FFDC              = 0,
+    EI_TYPE_HW_CALLOUT        = 1,
+    EI_TYPE_PROCEDURE_CALLOUT = 2,
+    EI_TYPE_BUS_CALLOUT       = 3,
+    EI_TYPE_CDG               = 4, // Target Callout/Deconfig/GARD
+    EI_TYPE_CHILDREN_CDG      = 5, // Children Callout/Deconfig/GARD
+    EI_TYPE_COLLECT_TRACE     = 6,
+    EI_LAST_TYPE              = EI_TYPE_COLLECT_TRACE + 1,
+};
+
+#ifndef MINIMUM_FFDC
+///
+/// @enum HwCallout
+///
+/// This enumeration defines the possible Hardware Callouts that are not
+/// represented by fapi2::Targets
+///
+/// Note that platform code may depend on the enum values starting at 0 and
+/// incrementing in order to efficiently convert to a platform callout value
+/// so do not reorder without consulting all platforms
+///
+namespace HwCallouts
+{
+enum HwCallout
+{
+    // Where indicated, a HW Callout in FAPI Error XML must include a
+    // reference target that is used to identify the HW. e.g. for
+    // TOD_CLOCK, the proc chip that the clock is attached to must be
+    // specified
+    TOD_CLOCK           = 0, // Include proc-chip ref (or child chiplet)
+    MEM_REF_CLOCK       = 1, // Include membuf-chip ref (or child chiplet)
+    PROC_REF_CLOCK      = 2, // Include proc-chip ref (or child chiplet)
+    PCI_REF_CLOCK       = 3, // Include proc-chip ref (or child chiplet)
+    FLASH_CONTROLLER_PART      = 4,
+    PNOR_PART                  = 5,
+    SBE_SEEPROM_PART           = 6,
+    VPD_PART                   = 7,
+    LPC_SLAVE_PART             = 8,
+    GPIO_EXPANDER_PART         = 9,
+    SPIVID_SLAVE_PART          = 10,
+};
+}
+
+///
+/// @enum ProcedureCallout
+///
+/// This enumeration defines the possible Procedure Callouts
+/// These instruct the customer/customer-engineer what to do
+///
+/// Note that platform code may depend on the enum values starting at 0 and
+/// incrementing in order to efficiently convert to a platform callout value
+/// so do not reorder without consulting all platforms
+///
+namespace ProcedureCallouts
+{
+enum ProcedureCallout
+{
+    CODE                  = 0, // Code problem
+    LVL_SUPPORT           = 1, // Call next level of support
+    MEMORY_PLUGGING_ERROR = 2, // DIMM Plugging error
+    BUS_CALLOUT           = 3, // Bus Called Out
+};
+}
+
+///
+/// @enum CalloutPriority
+///
+/// This enumeration defines the possible Procedure and Target callout priorities
+///
+/// Note that platform code may depend on the enum values starting at 0 and
+/// incrementing in order to efficiently convert to a platform priority value
+/// so do not reorder without consulting all platforms
+///
+namespace CalloutPriorities
+{
+enum CalloutPriority
+{
+    LOW = 0,
+    MEDIUM = 1,
+    HIGH   = 2,
+};
+}
+
+///
+/// @enum CollectTrace
+///
+/// This enumeration defines the possible firmware traces to collect
+///
+namespace CollectTraces
+{
+const uint32_t TRACE_SIZE = 256; // limit collected trace size
+enum CollectTrace
+{
+    FSI              = 1,
+    SCOM             = 2,
+    SCAN             = 3,
+    MBOX             = 4,
+};
+}
+#endif
+
+// NOTE - this assumes no buffer_t or variable_buffers are passed
+//        data is converted to a uint64_t when placed into the sbe ffdc
+//        buffer
+inline fapi2::ffdc_t getFfdcData( sbeFfdc_t& i_sbeFfdc )
+{
+    fapi2::ffdc_t temp;
+
+    // passed in size is a uint32_t but, needs to be uint16_t
+    temp.size() = static_cast<uint16_t>(i_sbeFfdc.size);
+
+    if(temp.size() == EI_FFDC_SIZE_TARGET)
+    {
+        uint64_t targetData = i_sbeFfdc.data;
+        fapi2::TargetType type = static_cast<fapi2::TargetType>(targetData >> 32);
+        uint8_t instance = static_cast<uint8_t>(targetData & 0xFFFFFFFF);
+        // call hostboot to get the fapi2 target reference
+        temp.ptr() = static_cast<void*>(getTarget<TARGET_TYPE_ALL>(type, instance));
+    }
+    else
+    {
+        // adjust the pointer based on the data size.
+        temp.ptr() = static_cast<void*>(reinterpret_cast<uint8_t*>(&i_sbeFfdc.data) +
+                                        (sizeof(uint64_t) - i_sbeFfdc.size));
+    }
+
+    return temp;
+}
+///
+/// @brief Get FFDC Size
+///
+/// This is called by the FAPI_SET_HWP_ERROR macro to find out the size of
+/// FFDC data. If the data is of a special type that is handled differently
+/// than types that are simply memcopied then it is handled by a template
+/// specialization.
+/// If this function template is instantiated with a pointer, the compile
+/// will fail.
+///
+/// @return uint16_t. Size of the FFDC data
+///
+template<typename T>
+inline uint16_t getErrorInfoFfdcSize(const T&)
+{
+    static_assert(sizeof(T) <= EI_FFDC_MAX_SIZE,
+                  "FFDC too large to capture");
+    return sizeof(T);
+}
+#if !defined(MINIMUM_FFDC) && !defined(FAPI2_NO_FFDC)
+///
+/// @brief Compile error if caller tries to get the FFDC size of a pointer
+///
+template<typename T>
+inline uint16_t getErrorInfoFfdcSize(const T*)
+{
+    static_assert(std::is_pointer<T>::value,
+                  "pointer passed to getErrorInfoFfdcSize");
+    return 0;
+}
+#endif
+///
+/// @brief Get FFDC Size specialization for fapi2::Target
+///
+template<fapi2::TargetType T, typename V>
+inline uint16_t getErrorInfoFfdcSize(const fapi2::Target<T, V>&)
+{
+    return EI_FFDC_SIZE_TARGET;
+}
+
+#if !defined(MINIMUM_FFDC) && !defined(FAPI2_NO_FFDC)
+///
+/// @brief Get FFDC Size specialization for variable buffers
+///
+template<>
+inline uint16_t getErrorInfoFfdcSize(const fapi2::variable_buffer& i_thing)
+{
+    // Limit a variable buffer to 4kb bytes, and we can memcpy the storage.
+    return std::min(static_cast<uint32_t>(EI_FFDC_MAX_SIZE),
+                    i_thing.getLength<uint8_t>());
+}
+#endif
+};
+
+#endif // FAPI2_ERRORINFO_DEFS_H_
diff --git a/src/import/hwpf/fapi2/include/error_scope.H b/src/import/hwpf/fapi2/include/error_scope.H
new file mode 100644
index 00000000..1a00386c
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/error_scope.H
@@ -0,0 +1,37 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/error_scope.H $                     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file error_scope.H
+ * @brief platform specializations which create a scope for automatic error handling
+ */
+
+#ifndef __FAPI2_ERROR_SCOPE__
+#define __FAPI2_ERROR_SCOPE__
+
+#include <plat_error_scope.H>
+#include <fapi2_error_scope.H>
+
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/fapi2.H b/src/import/hwpf/fapi2/include/fapi2.H
new file mode 100644
index 00000000..9965e8e5
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/fapi2.H
@@ -0,0 +1,55 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/fapi2.H $                           */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file fapi2.H
+/// @brief top level header for fapi2
+///
+
+#ifndef __FAPI2_TOP_LEVEL__
+#define __FAPI2_TOP_LEVEL__
+
+#include <target.H>
+#include <return_code.H>
+#include <buffer.H>
+#include <hw_access.H>
+#include <utils.H>
+#include <plat_trace.H>
+
+// In turn includes the needed generated headers (hwp_ffd_classes, etc.)
+#include <error_scope.H>
+#include <set_sbe_error.H>      // Generated file
+
+#include <fapi2_hwp_executor.H>
+#include <fapi2_attribute_service.H>
+#include <fapi2_chip_ec_feature.H>
+
+#include <mvpd_access.H>
+
+// Block of headers not currently in fapi2
+#ifdef FAPI2_MISSING_HEADERS
+    #include <mbvpdAccess.H>
+#endif
+
+#endif // __FAPI2_TOP_LEVEL__
diff --git a/src/import/hwpf/fapi2/include/fapi2_attribute_service.H b/src/import/hwpf/fapi2/include/fapi2_attribute_service.H
new file mode 100644
index 00000000..78655961
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/fapi2_attribute_service.H
@@ -0,0 +1,148 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/fapi2_attribute_service.H $         */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file fapi2_attribute_service.H
+///
+/// @brief Defines the FAPI_ATTR_GET and FAPI_ATTR_SET macros that a user
+/// calls to get/set attributes and a check function that the macros use to
+/// verify correct usage
+///
+
+#ifndef FAPI2ATTRIBUTESERVICE_H_
+#define FAPI2ATTRIBUTESERVICE_H_
+#include <stdint.h>
+#include <attribute_ids.H>
+#include <return_code.H>
+#include <target.H>
+#include <target_types.H>
+#include <plat_attribute_service.H>
+
+/// @brief Macros called by user to get/set attributes for FAPI2 targets
+///
+/// Code must have a reference to a FAPI2 Target and an attribute ID (from
+/// XML file):
+///   fapi2::ReturnCode l_rc;
+///   fapi2::Target<target type>& l_target = ????;
+///          Ex: Target<TARGET_TYPE_PROC_CHIP>& l_target = ????;
+///
+/// To get a copy of an integer attribute and set the attribute
+///   uint64_t l_val = 0;
+///   l_rc = FAPI_ATTR_GET(<ID>, l_target, l_val);
+///   l_rc = FAPI_ATTR_SET(<ID>, l_target, l_val);
+///
+/// To get a copy of an integer array attribute and set the attribute
+///   uint32_t l_pVal[4] = {0};
+///   l_rc = FAPI_ATTR_GET(<ID>, l_target, l_pVal);
+///   l_rc = FAPI_ATTR_SET(<ID>, l_target, l_pVal);
+///
+/// A priveleged attribute is one that a HWP should not generally access,
+/// examples include ATTR_NAME and ATTR_EC, where usage can lead to a non
+/// data-driven design. A privileged attribute can be accessed with
+/// FAPI_ATTR_GET_PRIVILEGED and FAPI_ATTR_SET_PRIVILEGED
+///
+/// The non-PRIVILEGED macros first call a template function (compiler will
+/// optimize out) that will cause a compile failure if the attribute is
+/// privileged, they then call a PRIVILEGED macro to get/set the attribute
+///
+/// The PRIVILEGED macros call a template function (compiler will optimize out)
+/// that will cause a compile failure if the ID is not valid or VAL is not the
+/// correct type.
+//
+
+#define FAPI_ATTR_GET(ID, TARGET, VAL) \
+    (fapi2::failIfPrivileged<ID##_Privileged>(), \
+     fapi2::Target<ID##_TargetType>(TARGET), \
+     fapi2::checkIdType<ID##_Type>(ID, VAL), \
+     ID##_GETMACRO(ID, TARGET, VAL))
+
+#define FAPI_ATTR_SET(ID, TARGET, VAL) \
+    (fapi2::failIfPrivileged<ID##_Privileged>(), \
+     fapi2::Target<ID##_TargetType>(TARGET), \
+     fapi2::checkIdType<ID##_Type>(ID, VAL), \
+     ID##_SETMACRO(ID, TARGET, VAL))
+
+#define FAPI_ATTR_GET_PRIVILEGED(ID, TARGET, VAL) \
+    (fapi2::checkIdType<ID##_Type>(ID, VAL), \
+     ID##_GETMACRO(ID, TARGET, VAL))
+
+#define FAPI_ATTR_SET_PRIVILEGED(ID, TARGET, VAL) \
+    (fapi2::checkIdType<ID##_Type>(ID, VAL), \
+     ID##_SETMACRO(ID, TARGET, VAL))
+
+namespace fapi2
+{
+
+///
+/// @brief Get raw access to a FAPI2 Attribute.  This is used to dump FAPI2
+///        Attrs
+///
+/// This function gets a copy of an attribute. In the case of an array attribute,
+/// The value in the specified index is retrieved. This should be used by the
+/// InitFile HWP only, that HWP processes a binary InitFile and therefore needs
+/// to read a variable ID of a variable data type. Standard HWPs should use the
+/// FAPI2_ATTR_GET macro which automatically checks the type for correct usage.
+///
+/// If there are ever attributes with more than 4 dimensions then this function
+/// will need to be updated.
+///
+/// @tparam K template parameter, passed in target.
+/// @param[in]  i_id          AttributeID
+/// @param[in]  i_target      Reference to fapi2::Target (can be NULL for system)
+/// @param[out] o_val         Reference to uint64_t where attribute value is set
+/// @param[in]  i_arrayIndex1 If array attribute then index1
+/// @param[in]  i_arrayIndex2 If at least 2D array attribute then index2
+/// @param[in]  i_arrayIndex3 If at least 3D array attribute then index3
+/// @param[in]  i_arrayIndex4 If at least 4D array attribute then index4
+///
+/// @return ReturnCode. Zero if success
+///
+ReturnCode rawAccessAttr(const AttributeId i_id,
+                         const Target<TARGET_TYPE_ALL>& i_target,
+                         uint8_t* o_val);
+
+/**
+ * @brief Check the ID and TYPE
+ *
+ * This is called by FAPI code to check at compile time that a FAPI attribute
+ * access is using the correct data type and a valid AttributeId
+ */
+template<typename T> inline void checkIdType(AttributeId, T&) {}
+
+/**
+ * @brief Fail if attribute privileged
+ *
+ * This is called by FAPI code to check at compile time that a standard FAPI
+ * attribute access (FAPI_ATTR_GET) is not accessing a privileged attribute
+ */
+class ErrorAccessingPrivilegedAttribute;
+template<const bool PRIVILEGED> void failIfPrivileged()
+{
+    ErrorAccessingPrivilegedAttribute();
+}
+template <> inline void failIfPrivileged<false>() {}
+
+}
+
+#endif // FAPI2ATTRIBUTESERVICE_H_
diff --git a/src/import/hwpf/fapi2/include/fapi2_error_scope.H b/src/import/hwpf/fapi2/include/fapi2_error_scope.H
new file mode 100644
index 00000000..8a4833ac
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/fapi2_error_scope.H
@@ -0,0 +1,89 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/fapi2_error_scope.H $               */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file fapi2_error_scope.H
+ * @brief common definitions which create a scope for automatic error handling
+ */
+
+#ifndef __FAPI2_COMMON_ERROR_SCOPE__
+#define __FAPI2_COMMON_ERROR_SCOPE__
+
+#include <stdint.h>
+#include <plat_error_scope.H>
+#include <hwp_ffdc_classes.H>
+
+/// @cond
+#define FAPI_VA_NARGS_IMPL(_1, _2, _3, _4, _5, N, ...) N
+#define FAPI_VA_NARGS(...) FAPI_VA_NARGS_IMPL(__VA_ARGS__, 5, 4, 3, 2, 1)
+
+#define FAPI_TRY_IMPL2(count, ...) FAPI_TRY ## count (__VA_ARGS__)
+#define FAPI_TRY_IMPL(count, ...) FAPI_TRY_IMPL2(count, __VA_ARGS__)
+
+#define FAPI_TRY_NO_TRACE( __operation__ ) PLAT_FAPI_TRY_NO_TRACE( __operation__ )
+#define FAPI_TRY_TRACE( __operation__, ... ) PLAT_FAPI_TRY_TRACE( __operation__, __VA_ARGS__ )
+
+#define FAPI_TRY1 FAPI_TRY_NO_TRACE
+#define FAPI_TRY2 FAPI_TRY_TRACE
+#define FAPI_TRY3 FAPI_TRY_TRACE
+#define FAPI_TRY4 FAPI_TRY_TRACE
+#define FAPI_TRY5 FAPI_TRY_TRACE
+/// @endcond
+
+///
+/// @brief Wrapper to check an operation for an error state
+/// and jump to the label clean_up if there is an error.
+/// @param[in] \__operation__ an operation which returns a fapi::ReturnCode
+/// @param[in] ... vararg format/agruments for trace output (optional)
+/// @note This implementation does not support PIB error masks or
+/// FSP operational states.
+///
+#ifdef DOXYGEN
+    #define FAPI_TRY(__operation__, ...) FAPI_TRY_IMPL
+#else
+    #define FAPI_TRY(...) FAPI_TRY_IMPL(FAPI_VA_NARGS(__VA_ARGS__), __VA_ARGS__)
+#endif
+
+///
+/// @brief Assert a conditional is true.
+/// If it is not, the FFDC gathering function is called and the
+/// trace is output as a FAPI error trace.
+/// @param[in] \__conditional__ the condition to assert
+/// @param[in] \__ffdc__ the FFDC gathering function
+/// @param[in] ... varargs, as input to FAPI_ERR
+///
+#define FAPI_ASSERT( __conditional__, __ffdc__, ... ) \
+    PLAT_FAPI_ASSERT( __conditional__, __ffdc__, __VA_ARGS__ )
+
+///
+/// @brief Create an eror log, commit it, but do not exit the hwp because of
+///        the error condition.
+/// @param[in] \__conditional__ the condition to assert
+/// @param[in] \__ffdc__ the FFDC gathering function
+/// @param[in] ... varargs, as input to FAPI_ERR
+///
+#define FAPI_ASSERT_NOEXIT( __conditional__, __ffdc__, ... ) \
+    PLAT_FAPI_ASSERT_NOEXIT( __conditional__, __ffdc__, __VA_ARGS__ )
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/fapi2_hw_access.H b/src/import/hwpf/fapi2/include/fapi2_hw_access.H
new file mode 100644
index 00000000..8dc871bb
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/fapi2_hw_access.H
@@ -0,0 +1,428 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/fapi2_hw_access.H $                 */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file fapi2_hw_access.H
+/// @brief Common file that defines the hardware access functions that
+/// platform code must implement.
+///
+
+#ifndef _FAPI2_COMMON_HWACCESS_H_
+#define _FAPI2_COMMON_HWACCESS_H_
+
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+    #include <spy_ids.H>
+    typedef uint64_t spyId_t;
+#endif
+
+#include <stdint.h>
+#include <buffer.H>
+
+// variable_buffer isn't supported on PPE
+#ifndef __PPE__
+    #include <variable_buffer.H>
+#endif
+
+#include <return_code.H>
+#include <target.H>
+#include <hw_access_def.H>
+#include <plat_hw_access.H>
+#include <p9_ringId.H>
+
+namespace fapi2
+{
+//--------------------------------------------------------------------------
+// PIB Error Functions
+//--------------------------------------------------------------------------
+
+/// @brief Sets the PIB error mask - platform dependant
+/// @param[in]  i_mask     The new error mask
+inline void setPIBErrorMask(uint8_t i_mask);
+
+/// @brief Gets the PIB error mask - platform dependant
+/// @return uint8_t The current PIB error mask
+inline uint8_t getPIBErrorMask(void);
+
+//--------------------------------------------------------------------------
+// Operational Mode Error Functions
+//--------------------------------------------------------------------------
+
+/// @brief Sets the operational mode
+/// @param[in]  i_mode     The new mode
+inline void setOpMode(const OpModes i_mode);
+
+/// @brief Gets the operational mode
+/// @return the operational mode
+inline OpModes getOpMode(void);
+
+//--------------------------------------------------------------------------
+// HW Communication Functions
+//--------------------------------------------------------------------------
+
+/// @brief Reads a SCOM register from a chip.
+/// @tparam K template parameter, passed in target.
+/// @param[in]  i_target     HW target to operate on.
+/// @param[in]  i_address    SCOM register address to read from.
+/// @param[out] o_data       Buffer that holds data read from HW target.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+template< TargetType K, typename V >
+inline ReturnCode getScom(const Target<K, V>& i_target, const uint64_t i_address,
+                          buffer<uint64_t>& o_data);
+
+/// @brief Writes a SCOM register on a chip.
+/// @tparam K template parameter, passed in target.
+/// @param[in] i_target     HW target to operate on.
+/// @param[in] i_address    SCOM register address to write to.
+/// @param[in] i_data       Buffer that holds data to write into address.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+template< TargetType K, typename V >
+inline ReturnCode putScom(const Target<K, V>& i_target, const uint64_t i_address,
+                          const buffer<uint64_t> i_data);
+
+/// @brief Writes a SCOM register under mask on a chip
+/// @tparam K template parameter, passed in target.
+/// @param[in] i_target     HW target to operate on.
+/// @param[in] i_address    SCOM register address to write to.
+/// @param[in] i_data       Buffer that holds data to write into address.
+/// @param[in] i_mask       Buffer that holds the mask value.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+template< TargetType K, typename V >
+inline ReturnCode putScomUnderMask(const Target<K, V>& i_target,
+                                   const uint64_t i_address,
+                                   const buffer<uint64_t> i_data,
+                                   const buffer<uint64_t> i_mask);
+
+/// @brief Reads a CFAM register from a chip.
+///        CFAM register is 32-bit wide.
+/// @tparam K template parameter, passed in target.
+/// @param[in]  i_target  HW target to operate on.
+/// @param[in]  i_address CFAM register address to read from.
+/// @param[out] o_data    Buffer that holds data read from HW target.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+template< TargetType K, typename V >
+inline ReturnCode getCfamRegister(const Target<K, V>& i_target,
+                                  const uint32_t i_address,
+                                  buffer<uint32_t>& o_data);
+
+/// @brief Writes a CFAM register on a chip.
+///        CFAM register is 32-bit wide.
+/// @tparam K template parameter, passed in target.
+/// @param[in] i_target  HW target to operate on.
+/// @param[in] i_address CFAM register address to write to.
+/// @param[in] i_data    Buffer that holds data to write into address.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+template< TargetType K, typename V >
+inline ReturnCode putCfamRegister(const Target<K, V>& i_target,
+                                  const uint32_t i_address,
+                                  const buffer<uint32_t> i_data);
+
+/// @brief Read-modify-write a CFAM register on a chip.
+///        CFAM register is 32-bit wide.
+/// @tparam K template parameter, passed in target.
+/// @param[in] i_target     HW target to operate on.
+/// @param[in] i_address    CFAM register address to modify.
+/// @param[in] i_data       Buffer that holds data to be modified.
+/// @param[in] i_modifyMode The modify mode (or/and/xor).
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+template< TargetType K, typename V >
+inline ReturnCode modifyCfamRegister(const Target<K, V>& i_target,
+                                     const uint32_t i_address,
+                                     const buffer<uint32_t> i_data,
+                                     const ChipOpModifyMode i_modifyMode);
+
+/// @brief Writes a ring to a chip.
+/// @tparam K template parameter, passed in target.
+/// @param[in] i_target   Target to operate on.
+/// @param[in] i_ringID   Ring ID that will identify the Ring in the image.
+/// @param[in] i_ringMode Ring operation mode.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+template< TargetType K, typename V >
+ReturnCode putRing(const Target<K, V>& i_target,
+                   const RingID i_ringID,
+                   const RingMode i_ringMode = RING_MODE_HEADER_CHECK);
+
+// variable_buffer isn't supported on PPE
+#ifndef __PPE__
+/// @brief Reads a ring from a chip.
+/// @tparam K template parameter, passed in target.
+/// @param[in]  i_target   Target to operate on.
+/// @param[in]  i_address  Ring address to read from.
+/// @param[out] o_data     Buffer that holds data read from HW target.
+/// @param[in]  i_ringMode Ring operation mode.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+template< TargetType K, typename V >
+inline ReturnCode getRing(const Target<K, V>& i_target,
+                          const scanRingId_t i_address,
+                          variable_buffer& o_data,
+                          const RingMode i_ringMode = 0);
+
+/// @brief Read-modify-write a ring on a chip.
+/// @tparam K template parameter, passed in target.
+/// @param[in] i_target     Target to operate on.
+/// @param[in] i_address    Ring address to modify.
+/// @param[in] i_data       Buffer that contains RS4 compressed ring data
+///                         to be modified.
+/// @param[in] i_modifyMode The modify mode (or/and/xor)
+/// @param[in] i_ringMode   Ring operation mode.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+template< TargetType K, typename V >
+inline ReturnCode modifyRing(const Target<K, V>& i_target,
+                             const scanRingId_t i_address,
+                             const variable_buffer& i_data,
+                             const ChipOpModifyMode i_modifyMode,
+                             const RingMode i_ringMode = 0);
+#endif
+
+// --------------------------------------------------------------------------
+// NOTE:
+// Implement platform Spy access functions if platform supports them.
+// --------------------------------------------------------------------------
+
+// variable_buffer isn't supported on PPE
+#ifndef __PPE__
+/// @brief Reads a spy from a chip.
+/// @tparam K template parameter, passed in target.
+/// @param[in]  TARGET   Target to operate on.
+/// @param[in]  ID       Id of the spy whose data to be read.
+/// @param[out] DATA     Buffer that holds data read from HW target.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+/// @note:  The string version is only supported for cronus.
+///
+///         The fapi design to support both FSP and cronus use of get and
+///         put spy functions is dependant on the SPY names being expanded
+///         to resemble a valid C identifier. This design places some
+///         restrictions on the SPY names which can be used.
+///
+///         1. if the spy name contains a # procedure writers should replace
+///         it with an __P__ for example -
+///
+///         ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+///         becomes
+///         ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS
+///
+///         2. if the spy name has a number following a "." it must have an
+///         underscore prepended to the number.
+///
+///         EH.TPCHIP.2KX100_ARY_CLK_EDGES_DLY
+///         becomes
+///         EH.TPCHIP._2KX100_ARY_CLK_EDGES_DLY
+///
+///         Example SPY name:
+///         The hardware procedure should call the function like:
+///
+///          ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+///
+///          fapi2::ReturnCode rc = fapiGetSpy( targ,
+///                  ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS, data );
+///
+/// @note The ID is not in quotes the fapi code will handle adding
+///       the quotes for the cronus environment
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY(TARGET, ID, DATA) fapi2::getSpy(TARGET, FAPI_SPY_NAMES::ID.value, DATA)
+
+template< TargetType K, typename V >
+inline ReturnCode getSpy(const Target<K, V>& i_target,
+                         const spyId_t i_spyId,
+                         variable_buffer& o_data);
+
+template< TargetType K >
+inline ReturnCode getSpy(const Target<K>& i_target,
+                         const spyId_t i_spyId,
+                         variable_buffer& o_data,
+                         const RingMode i_ringMode);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY(TARGET, ID, DATA) fapi2::getSpy(TARGET, #ID, DATA)
+
+template< TargetType K, typename V >
+inline ReturnCode getSpy(const Target<K, V>& i_target,
+                         const char* const i_spyId,
+                         variable_buffer& o_data);
+
+template< TargetType K >
+inline ReturnCode getSpy(const Target<K>& i_target,
+                         const char* const i_spyId,
+                         variable_buffer& o_data,
+                         const RingMode i_ringMode);
+#endif
+
+/// @brief Writes a spy on a chip.
+/// @tparam K template parameter, passed in target.
+/// @param[in]  TARGET   Target to operate on.
+/// @param[in]  ID       Id of the spy to write data to.
+/// @param[out] DATA     Buffer that holds data to write into spy.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+/// @note:  The string version is only supported for cronus.
+///
+///         The fapi design to support both FSP and cronus use of get and
+///         put spy functions is dependent on the SPY names being expanded
+///         to resemble a valid C identifier. This design places some
+///         restrictions on the SPY names which can be used.
+///
+///         1. if the spy name contains a # procedure writers should replace
+///         is with an __P__ for example -
+///
+///         ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+///         becomes
+///         ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS
+///
+///         2. if the spy name has a number following a "." it must have an
+///         underscore prepended to the number.
+///
+///         EH.TPCHIP.2KX100_ARY_CLK_EDGES_DLY
+///         becomes
+///         EH.TPCHIP._2KX100_ARY_CLK_EDGES_DLY
+///
+///         Example SPY name:
+///         The hardware procedure should call the function like:
+///
+///          ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+///
+///          fapi2::ReturnCode rc = fapiPutSpy( targ,
+///                  ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS, data );
+///
+/// @note The ID is not in quotes the fapi code will handle adding
+///         the quotes for the cronus environment
+///
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY(TARGET, ID, DATA) fapi2::putSpy(TARGET, FAPI_SPY_NAMES::ID.value, DATA)
+
+template< TargetType K, typename V >
+inline ReturnCode putSpy(const Target<K, V>& i_target,
+                         const spyId_t i_spyId,
+                         const variable_buffer& i_data);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY(TARGET, ID, DATA) fapi2::putSpy(TARGET, #ID, DATA)
+
+template< TargetType K, typename V >
+inline ReturnCode putSpy(const Target<K, V>& i_target,
+                         const char* const i_spyId,
+                         const variable_buffer& i_data);
+
+template< TargetType K, typename V >
+inline ReturnCode putSpy(const Target<K, V>& i_target,
+                         const char* const i_spyId,
+                         const char* i_enum);
+#endif
+
+/// @brief Writes spy data into a buffer holding ring data image
+///        This API is used by L2/L3 repair to put column repair data
+///        into a ring buffer image.
+/// @tparam K template parameter, passed in target.
+/// @param[in]  TARGET Target to operate on.
+/// @param[in]  ID     Id of the spy.
+/// @param[in]  DATA1  Buffer that holds spy data to write into ring
+///                      image.
+/// @param[out] DATA2  Buffer that holds updated ring image.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+/// @note:  The string version is only supported for cronus.
+///
+///         The fapi design to support both FSP and cronus use of get and
+///         put spy functions is dependent on the SPY names being expanded
+///         to resemble a valid C identifier. This design places some
+///         restrictions on the SPY names which can be used.
+///
+///         See fapiPutSpy for details on spy id specifics.
+///
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY_IMAGE(TARGET, ID, DATA1, DATA2)                    \
+    fapi2::putSpyImage(TARGET, FAPI_SPY_NAMES::ID.value,                \
+                       DATA1, DATA2)
+
+template< TargetType K, typename V >
+inline ReturnCode putSpyImage(const Target<K, V>& i_target,
+                              const spyId_t i_spyId,
+                              const variable_buffer& i_data,
+                              variable_buffer& o_imageData);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_PUT_SPY_IMAGE(TARGET, ID, DATA1, DATA2) \
+    fapi2::putSpyImage(TARGET, #ID, DATA1,DATA2)
+
+template< TargetType K, typename V >
+inline ReturnCode putSpyImage(const Target<K, V>& i_target,
+                              const char* const i_spyId,
+                              const variable_buffer& i_data,
+                              variable_buffer& o_imageData);
+#endif
+
+/// @brief Reads spy data from a ring image buffer
+/// @param[in]   TARGET    Target to operate on
+/// @param[in]   ID        The spy's id
+/// @param[out]  DATA1     Buffer that holds data read from ring image.
+/// @param[in]   DATA2     Buffer that holds ring image to read data
+///                        from.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+/// @note:  The string version is only supported for cronus.
+///
+///         The fapi design to support both FSP and cronus use of get and
+///         put spy functions is dependent on the SPY names being expanded
+///         to resemble a valid C identifier. This design places some
+///         restrictions on the SPY names which can be used.
+///
+///         See fapiPutSpy for details on spy id specifics.
+///
+#if defined(FAPI_SUPPORT_SPY_AS_ENUM) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY_IMAGE(TARGET, ID, DATA1, DATA2)    \
+    fapi2:getSpyImage(TARGET, FAPI_SPY_NAMES::ID.value, \
+                      DATA1, DATA2)
+
+template< TargetType K, typename V >
+inline ReturnCode getSpyImage(const Target<K, V>& i_target,
+                              const spyId_t i_spyId,
+                              variable_buffer& o_data,
+                              const variable_buffer& i_imageData);
+#endif
+
+#if defined(FAPI_SUPPORT_SPY_AS_STRING) || defined(DOXYGEN)
+
+#define FAPI_GET_SPY_IMAGE(TARGET, ID, DATA1, DATA2) \
+    fapi2::getSpyImage(TARGET, #ID, DATA1,DATA2)
+
+template< TargetType K, typename V >
+inline ReturnCode getSpyImage(const Target<K, V>& i_target,
+                              const char* const i_spyId,
+                              variable_buffer& o_data,
+                              const variable_buffer& i_imageData);
+#endif
+
+#endif // PPE
+};
+
+#endif // _FAPI2_HWACCESS_H_
diff --git a/src/import/hwpf/fapi2/include/fapi2_hwp_executor.H b/src/import/hwpf/fapi2/include/fapi2_hwp_executor.H
new file mode 100644
index 00000000..78a18fba
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/fapi2_hwp_executor.H
@@ -0,0 +1,48 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/fapi2_hwp_executor.H $              */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file fapi2_hwp_executor.H
+///
+/// @brief Defines the FAPI2 HWP Executor Macro.
+///
+/// The FAPI2 HWP Executor macro is called when a PLAT invoker function or a HWP
+/// wants to execute a HWP.
+///
+
+#ifndef FAPI2HWPEXECUTOR_H_
+#define FAPI2HWPEXECUTOR_H_
+
+#include <hwp_executor.H>
+
+/**
+ * @brief HWP Executor macro
+ *
+ * This macro calls a PLAT macro which will do any platform specific work to
+ * execute the HWP (e.g. dlopening a shared library)
+ */
+#define FAPI_EXEC_HWP(RC, FUNC, _args_...) \
+    FAPI_PLAT_EXEC_HWP(RC, FUNC, ##_args_)
+
+#endif // FAPI2HWPEXECUTOR_H_
diff --git a/src/import/hwpf/fapi2/include/fapi2_multicast.H b/src/import/hwpf/fapi2/include/fapi2_multicast.H
new file mode 100644
index 00000000..c83be5bc
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/fapi2_multicast.H
@@ -0,0 +1,171 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/fapi2_multicast.H $                 */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file fapi2_multicast.H
+/// @brief Common definitions for fapi2 multicast target value wrapper class
+///
+
+#ifndef __FAPI2_COMMON_MULTICAST__
+#define __FAPI2_COMMON_MULTICAST__
+
+#include <target.H>
+#include <fapi2_multicast_defs.H>
+
+namespace fapi2
+{
+
+///
+/// @brief Class representing a FAPI2 Multicast target value wrapper
+/// @tparam M the type of multicast operation
+/// @tparam G the type of multicast group
+/// @tparam V the type of the target's Value this class is wrapping
+/// @remark This wrapper class defines how a handle will behave by
+///     type and group if internal to the handle mulitcast operation
+///     is enabled. If the handle used is not multicast enabled most
+///     function of this class will be ignored.
+///
+template<MulticastType M, MulticastGroup G, typename V = plat_target_handle_t >
+class Multicast
+{
+    public:
+        ///
+        /// @brief Delagate default constructor to constructor
+        ///        that takes in a value as a param
+        ///
+        Multicast() : Multicast(V()) {}
+
+        ///
+        /// @brief Create a Multicast value with a target value
+        /// @param[in] Value the value (i.e., specific element this
+        /// target represents, or pointer)
+        /// @note Platforms can will update the handle value with
+        /// information on the multicast type and group
+        ///
+        Multicast(const V& value) : iv_handle(value)
+        {
+            updateHandle<M, G>(iv_handle);
+        }
+
+        ///
+        /// @brief Create a Multicast value from another Multicast value
+        /// @param[in] other the value
+        /// @note Platforms can will update the handle value with
+        /// information on the multicast type and group
+        ///
+        template<MulticastType O, MulticastGroup N>
+        Multicast(const Multicast<O, N> other) :
+            iv_handle(static_cast<V>(other))
+        {
+            updateHandle<M, G>(iv_handle);
+        }
+
+        ///
+        /// @brief Get the handle as a V
+        /// @return V The Multicast wrapper's internal handle, or value
+        ///
+        inline operator V() const
+        {
+            return iv_handle;
+        }
+
+        ///
+        /// @brief Get the handle as a V
+        /// @return V The Multicast wrapper's internal handle, or value
+        ///
+        inline V& operator()() const
+        {
+            return iv_handle;
+        }
+
+        ///
+        /// @brief Has the handle been enabled for multicast operation
+        /// @return Return true if multicast, false otherwise
+        ///
+        inline bool isMulticast() const;
+
+    private:
+        ///
+        /// @brief update the handle with group and type given
+        /// @tparam O the type of multicast operation
+        /// @tparam N the type of multicast group
+        /// @param[in] Value the value/handle
+        ///
+        template<MulticastType O, MulticastGroup N>
+        inline void updateHandle(V& value);
+
+        V iv_handle;
+};
+
+// multicast from unicast
+template<MulticastType M, MulticastGroup G, TargetType K, typename V>
+inline Target<K, Multicast<M, G, V>> make_multicast(const Target<K, V>& t)
+{
+    return Target<K, Multicast<M, G, V>>(t.get());
+}
+
+// multicast from multicast -- changing type
+template<MulticastType M, MulticastType N, MulticastGroup G, TargetType K, typename V>
+inline Target<K, Multicast<M, G, V>> make_multicast(const Target<K, Multicast<N, G, V>>& t)
+{
+    return Target<K, Multicast<M, G, V>>(t.get());
+}
+
+// multicast from multicast -- changing type and group
+template<MulticastType M, MulticastGroup O, MulticastType N, MulticastGroup G, TargetType K, typename V>
+inline Target<K, Multicast<M, O, V>> make_multicast(const Target<K, Multicast<N, G, V>>& t)
+{
+    return Target<K, Multicast<M, O, V>>(t.get());
+}
+
+// unicast from multicast
+template<MulticastType M, MulticastGroup G, TargetType K, typename V>
+inline Target<K, V> make_unicast(const Target<K, Multicast<M, G, V>>& t)
+{
+    return Target<K, V>(t.get());
+}
+
+// test if a multicast target
+template<MulticastType M, MulticastGroup G, TargetType K, typename V>
+inline bool is_multicast(const Target<K, Multicast<M, G, V>>& t)
+{
+    const Multicast<M, G, V>& l_mref = t;
+    return l_mref.isMulticast();
+}
+
+// return false if testing a non-multicast target
+template<TargetType K, typename V>
+inline bool is_multicast(const Target<K, V>& t)
+{
+    return false;
+}
+
+template<MulticastType M1, MulticastType M2>
+constexpr bool is_same()
+{
+    return (M1 == M2);
+}
+}
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/fapi2_multicast_defs.H b/src/import/hwpf/fapi2/include/fapi2_multicast_defs.H
new file mode 100644
index 00000000..6199b4e0
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/fapi2_multicast_defs.H
@@ -0,0 +1,42 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/fapi2_multicast_defs.H $            */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+#ifndef __FAPI2_COMMON_MULTICAST_DEFS__
+#define __FAPI2_COMMON_MULTICAST_DEFS__
+
+namespace fapi2
+{
+enum MulticastType
+{
+    MULTICAST_WRITE,
+    MULTICAST_READAND,
+    MULTICAST_READOR,
+    MULTICAST_READBITX,
+    MULTICAST_READCOMPARE,
+};
+
+typedef uint32_t MulticastGroup;
+}
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/fapi2_target.H b/src/import/hwpf/fapi2/include/fapi2_target.H
new file mode 100644
index 00000000..b41eb477
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/fapi2_target.H
@@ -0,0 +1,549 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/fapi2_target.H $                    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file fapi2_target.H
+/// @brief Common definitions for fapi2 targets
+///
+
+#ifndef __FAPI2_COMMON_TARGET__
+#define __FAPI2_COMMON_TARGET__
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <vector>
+#include <target_types.H>
+#include <target_states.H>
+#include <plat_target.H>
+#include <return_code_defs.H>
+
+namespace fapi2
+{
+
+///
+/// @brief Class representing a FAPI2 Target
+/// @tparam K the type (Kind) of target
+/// @tparam V the type of the target's Value
+/// @remark TargetLite targets are uint64_t, Targets
+/// are uintptr_t (void*).
+///
+/// Assuming there are representations of a processor,
+/// a membuf and a system here are some examples:
+/// @code
+/// #define PROCESSOR_CHIP_A 0xFFFF0000
+/// #define MEMBUF_CHIP_B    0x0000FFFF
+/// #define SYSTEM_C         0x0000AAAA
+/// @endcode
+///
+/// * To define a target:
+/// @code
+/// fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> A(PROCESSOR_CHIP_A);
+/// fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> C(SYSTEM_C);
+/// fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP> B(MEMBUF_CHIP_B);
+/// @endcode
+///
+/// * Functions which take composite target types
+/// @code
+/// void takesProcOrMembuf(
+/// const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP |
+///                     fapi2::TARGET_TYPE_MEMBUF_CHIP>& V );
+///
+/// void takesAny(const fapi2::Target<fapi2::TARGET_TYPE_ALL>& V );
+///
+/// @endcode
+///
+/// * Traversing the target "tree"
+/// @code
+/// fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> A(PROCESSOR_CHIP_A);
+///
+/// // Get A's parent
+/// A.getParent<fapi2::TARGET_TYPE_SYSTEM>();
+///
+/// // Get the 0x53'd core
+/// fapi2::getTarget<fapi2::TARGET_TYPE_CORE>(0x53);
+///
+/// // Get all *my* present/functional children which are cores
+/// A.getChildren<fapi2::TARGET_TYPE_CORE>();
+///
+/// // Get all of the the cores relative to my base target
+/// fapi2::getChildren<fapi2::TARGET_TYPE_CORE>();
+/// @endcode
+///
+/// * Invalid casts
+/// @code
+/// // Can't cast to a specialized target
+/// fapi2::Target<fapi2::TARGET_TYPE_NONE> D(MEMBUF_CHIP_B);
+/// takesProcOrMembuf( D );
+///
+/// // Not one of the shared types
+/// fapi2::Target<fapi2::TARGET_TYPE_ABUS_ENDPOINT> E;
+/// takesProcOrMembuf( E );
+/// @endcode
+template<TargetType K, typename V = plat_target_handle_t>
+class Target
+{
+    public:
+
+        ///
+        /// @brief Delagate default constructor to constructor
+        ///        that takes in a value as a param
+        ///
+        Target(): Target(V())
+        {};
+
+        ///
+        /// @brief Create a Target, with a value
+        /// @param[in] Value the value (i.e., specific element this
+        /// target represents, or pointer)
+        /// @note Platforms can mangle the value and K to get a
+        /// single uint64_t in value which represents all the information
+        /// they might need. value( K | V ), for example
+        ///
+        Target(const V& Value):
+            iv_handle(Value)
+        {};
+
+
+        ///
+        /// @brief Assignment Operator.
+        /// @param[in] i_right Reference to Target to assign from.
+        /// @return Reference to 'this' Target
+        ///
+        Target& operator=(const Target& i_right);
+
+        ///
+        /// @brief Equality Comparison Operator
+        /// @param[in] i_right Reference to Target to compare.
+        /// @return bool. True if equal.
+        /// @note Platforms need to define this so that the physical
+        /// targets are determined to be equivilent rather than just the handles
+        ///
+        bool operator==(const Target& i_right) const;
+
+        ///
+        /// @brief Inquality Comparison Operator
+        /// @param[in] i_right Reference to Target to compare.
+        /// @return bool. True if not equal.
+        /// @note Platforms need to define this so that the physical
+        /// targets are determined to be equivilent rather than just the handles
+        ///
+        bool operator!=(const Target& i_right) const;
+
+        ///
+        /// @brief Less Than Comparison Operator
+        /// @param[in] i_right Reference to Target to compare.
+        /// @return bool. True if less than i_right.
+        /// @note Platforms need to define this so that the physical
+        /// targets are determined to be less than rather than just the handles
+        ///
+        bool operator<(const Target& i_right) const;
+
+        ///
+        /// @brief Get the handle.
+        /// @return V The target's handle, or value
+        ///
+        V get(void) const
+        {
+            return iv_handle;
+        }
+
+        ///
+        /// @brief Get the handle as a V
+        /// @return V The target's handle, or value
+        ///
+        inline operator V() const
+        {
+            return iv_handle;
+        }
+
+        ///
+        /// @brief Get a target's value
+        /// @return V The target's handle, or value
+        ///
+        inline V& operator()(void)
+        {
+            return iv_handle;
+        }
+
+        ///
+        /// @brief Get the target type
+        /// @return The type of target represented by this target
+        ///
+        inline TargetType getType(void) const
+        {
+            return iv_type;
+        }
+
+        ///
+        /// @brief Get this target's immediate parent
+        /// @tparam T The type of the parent
+        /// @return Target<T> a target representing the parent
+        ///
+        template< TargetType T >
+        inline Target<T, V> getParent(void) const;
+
+        ///
+        /// @brief Is this target a chip?
+        /// @return Return true if this target is a chip, false otherwise
+        ///
+        inline constexpr bool isChip(void) const
+        {
+            return (isChip(K));
+        }
+
+        ///
+        /// @brief Static function check if a Target type value is that of
+        ///        a chip. It will return false for compound types that
+        ///        include non-chip Target type bits
+        ///
+        /// @param[in] i_type  The value of the Target type.
+        /// @return Return true if this type is of a chip, false otherwise
+        ///
+        static inline bool isChip(const TargetType i_type)
+        {
+            bool l_retVal = false;
+
+            // Target type must have only chip type bits set
+            if ( ((i_type & TARGET_TYPE_CHIPS) != 0) &&
+                 ((i_type & ~TARGET_TYPE_CHIPS) == 0) )
+            {
+                l_retVal = true;
+            }
+
+            return l_retVal;
+        }
+
+        ///
+        /// @brief Is this target a chiplet?
+        /// @return Return true if this target is a chiplet, false otherwise
+        ///
+        inline constexpr bool isChiplet(void) const
+        {
+            return (isChiplet(K));
+        }
+
+        ///
+        /// @brief Static function check if a Target type value is that of
+        ///        a chiplet. It will return false for compound types that
+        ///        include non-chiplet Target type bits
+        ///
+        /// @param[in] i_type  The value of the Target type.
+        /// @return Return true if this type is of a chiplet, false otherwise
+        ///
+        static inline bool isChiplet(const TargetType i_type)
+        {
+            bool l_retVal = false;
+
+            // Target type must have only chiplet type bits set
+            if ( ((i_type & TARGET_TYPE_CHIPLETS) != 0) &&
+                 ((i_type & ~TARGET_TYPE_CHIPLETS) == 0) )
+            {
+                l_retVal = true;
+            }
+
+            return l_retVal;
+        }
+
+        ///
+        /// @brief Get this target's children
+        /// @tparam T The type of the parent
+        /// @param[in] i_state The desired TargetState of the children
+        /// @return std::vector<Target<T,V>> a vector of present/functional
+        /// children
+        /// @warning The children of EX's (cores) are expected to be returned
+        /// in order. That is, core 0 is std::vector[0].
+        ///
+        template< TargetType T>
+        inline std::vector<Target<T, V> >
+        getChildren(const TargetState i_state = TARGET_STATE_FUNCTIONAL) const;
+
+        ///
+        /// @brief Get this target's children, filtered
+        /// @tparam T The type of the parent
+        /// @param[in] i_filter The desired chiplet filter
+        /// @param[in] i_state The desired TargetState of the children
+        /// @return std::vector<Target<T,V>> a vector of present/functional
+        /// children
+        ///
+        template< TargetType T>
+        inline std::vector<Target<T, V> >
+        getChildren(const TargetFilter i_filter,
+                    const TargetState i_state = TARGET_STATE_FUNCTIONAL) const;
+
+        ///
+        /// @brief Get the target at the other end of a bus
+        /// @tparam T The type of the target on the other end
+        /// @param[out] o_target A target representing the thing on the other end
+        /// @param[in] i_state The desired TargetState of the other end
+        /// @return FAPI2_RC_SUCCESS if OK, platforms will return a non-success
+        /// ReturnCode in the event of failure
+        /// @note o_target is only valid if return is FAPI2_RC_SUCCESS
+        ///
+
+        template<TargetType T>
+        inline fapi2::ReturnCodes
+        getOtherEnd(Target<T, V>& o_target, const TargetState i_state = TARGET_STATE_FUNCTIONAL) const;
+
+        ///
+        /// @brief Is the target functional?
+        /// @return true if target is functional, false if non-functional
+        ///
+
+        inline bool
+        isFunctional(void) const;
+
+        ///
+        /// @brief Returns the chiplet number associated with the Target
+        /// @return The chiplet number for the Target. 0 is returned if the
+        /// Target does not have a chiplet number (for ex, the PROC_CHIP Target)
+        /// @note For logical targets such as the EX, the chiplet number of
+        /// their immediate parent chiplet is returned
+        ///
+        inline uint8_t
+        getChipletNumber(void) const;
+
+        ///
+        /// @brief Copy from a Target<O> to a Target<K>
+        /// @tparam O the target type of the other
+        ///
+        template<TargetType O, typename VO>
+        inline Target( const Target<O, VO>& Other ):
+            Target<K, V>(Other.get())
+        {
+            // In case of recursion depth failure, use -ftemplate-depth=
+            static_assert( (K & O) != 0,
+                           "unable to cast Target, no shared types");
+
+            static_assert( bitCount<K>::count >= bitCount<O>::count,
+                           "unable to cast to specialized Target");
+        }
+
+    private:
+        // Don't use enums here as it makes it hard to assign
+        // in the platform target cast constructor.
+        static const TargetType iv_type = K;
+        V iv_handle;
+
+};
+
+// EX threads map to CORE threads:
+// t0 / t2 / t4 / t6 fused = t0 / t1 / t2 / t3 normal (c0)
+// t1 / t3 / t5 / t7 fused = t0 / t1 / t2 / t3 normal (c1)
+// So when splitting the EX, we need to map from EX threads
+// to CORE threads.
+
+///
+/// @brief Given a normal core thread id, translate this to
+/// a fused core thread id. (normal to fused)
+/// @param[in] i_ordinal   the ordinal number of the normal core this thread belongs to
+/// @param[in] i_thread_id a normal core thread id - 0, ..., 3
+/// @return the fused core thread id
+///
+inline uint8_t thread_id_n2f(const uint8_t i_ordinal, const uint8_t i_thread_id)
+{
+    return (i_thread_id << 1) | i_ordinal;
+}
+
+///
+/// @brief Given a fused core thread id, translate this to
+/// a normal core thread id. (fused to normal)
+/// @param[in] i_thread_id a fused core thread id - 0, ..., 7
+/// @return the normal core thread id
+///
+inline uint8_t thread_id_f2n(const uint8_t i_thread_id)
+{
+    return i_thread_id >> 1;
+}
+
+///
+/// @brief Given a normal core thread id, translate this to a
+/// normal core bitset.
+/// @param[in] i_thread_id a normal core thread id - 0, ..., 3
+/// @return the normal core bitset
+/// @note to got from a fused core id to a normal core bitset,
+/// translate from a fused core thread id first.
+///
+inline uint8_t thread_id2bitset(const uint8_t i_thread_id)
+{
+    // 0xff means "set all bits"
+    static const uint8_t all_threads  = 0xff;
+    static const uint8_t all_normal_threads_bitset = 0x0f;
+
+    if (i_thread_id == all_threads)
+    {
+        return all_normal_threads_bitset;
+    }
+
+    // A thread_id is really just bit index.
+    return (1 << (4 - i_thread_id - 1));
+}
+
+///
+/// @brief Given a bitset of normal core thread ids, translate this to
+/// a bit mask of fused core thread id. (normal to fused)
+/// @param[in] i_ordinal the ordinal number of the normal core this thread belongs to
+/// @param[in] i_threads a normal core thread bitset - b0000, ..., b1111
+/// @return the corresponding fused core bitset
+///
+inline uint8_t thread_bitset_n2f(const uint8_t i_ordinal, const uint8_t i_threads)
+{
+    // Since we only have 4 bits I think this is better than a shift-type solution
+    // for interleaving bits
+    static uint8_t core_map[] =
+    {
+        0b00000000, // b0000
+        0b00000010, // b0001
+        0b00001000, // b0010
+        0b00001010, // b0011
+        0b00100000, // b0100
+        0b00100010, // b0101
+        0b00101000, // b0110
+        0b00101010, // b0111
+        0b10000000, // b1000
+        0b10000010, // b1001
+        0b10001000, // b1010
+        0b10001010, // b1011
+        0b10100000, // b1100
+        0b10100010, // b1101
+        0b10101000, // b1110
+        0b10101010, // b1111
+    };
+
+    return core_map[i_threads] >> i_ordinal;
+}
+
+///
+/// @brief Given a fused core thread bitset, translate this to
+/// a normal core thread bitset. (fused to normal)
+/// @param[in] i_ordinal the ordinal number of the normal core this thread belongs to
+/// @param[in] i_threads a fused core thread bitset - b00000000, ..., b11111111
+/// @return the corresponding normal core bitset
+///
+inline uint8_t thread_bitset_f2n(const uint8_t i_ordinal, const uint8_t i_threads)
+{
+    uint8_t normal_set = 0;
+
+    // core 0 is the left-most bit in the pair
+    uint8_t pair_mask = (i_ordinal == 0) ? 0x2 : 0x1;
+
+    // For each bit which can be set in the normal core bit_set ...
+    for( auto i = 0; i <= 3; ++i )
+    {
+        // ... grab the two fused bits which represent it ...
+        // ... and mask off the bit in the pair which represents this normal core ...
+        // (the << 1 shifts the masks over as we walk the pairs of bits)
+        uint8_t bits = (((3 << (i << 1)) & i_threads) & (pair_mask << (i << 1)));
+
+        // ... if either bit is set, set the corresponding bit in
+        // the normal core bitset.
+        normal_set |= (bits != 0) << i;
+    }
+
+    return normal_set;
+}
+
+///
+/// @brief Return the string interpretation of this target
+/// @tparam T The type of the target
+/// @param[in] i_target Target<T,V>
+/// @param[in] i_buffer buffer to write in to
+/// @param[in] i_bsize size of the buffer
+/// @return void
+/// @post The contents of the buffer is replaced with the string
+/// representation of the target
+///
+template< TargetType T, typename V >
+inline void toString(const Target<T, V>& i_target, char* i_buffer, size_t i_bsize);
+
+///
+/// @brief Return the string interpretation of this target
+/// @tparam T The type of the target
+/// @tparam B The type of the buffer
+/// @param[in] i_target A pointer to the Target<T,V>
+/// @param[in] i_buffer buffer to write in to
+/// @param[in] i_bsize  size of the buffer
+/// @return void
+/// @post The contents of the buffer is replaced with the string
+/// representation of the target
+///
+template< TargetType T, typename V >
+inline void toString(const Target<T, V>* i_target, char* i_buffer, size_t i_bsize);
+
+///
+/// @brief Get an enumerated target of a specific type
+/// @tparam T The type of the target
+/// @param[in] Ordinal representing the ordinal number of
+/// the desired target
+/// @return Target<T> the target requested
+///
+template<TargetType T, typename V = plat_target_handle_t>
+inline Target<T, V> getTarget(uint64_t Ordinal);
+
+// Why has the been removed? For starters, the API name
+// is probably wrong as it's already been confused with
+// Target::getChildren(). And if I'm going to change it
+// I really want to see if we need it. I'm still not
+// clear on whether we're alloing this traversal or not.
+#if 0
+///
+/// @brief Get the base target's children
+/// @tparam T The type of the target
+/// @return std::vector<Target<T,V>> a vector of present/functional
+/// children
+///
+template<TargetType T, typename V>
+inline std::vector<Target<T, V>> getChildren()
+{
+    // For testing
+    return {Target<T, V>(), Target<T, V>()};
+}
+#endif
+
+///
+/// @brief Return the string interpretation of this target
+/// @tparam T The type of the target
+/// @tparam B The type of the buffer
+/// @param[in] i_target Target<T,V>
+/// @param[in] i_buffer buffer
+/// @return void
+/// @post The contents of the buffer is replaced with the string
+/// representation of the target
+///
+template<TargetType T, typename V, typename B>
+inline void toString(const Target<T, V>& i_target, B& i_buffer);
+
+///
+/// @brief Check if the target is of a type, or in a type subset.
+/// @tparam K the TargetType to check
+/// @tparam T TargetType or TargetType composite to check against
+/// @return True, iff K is a proper T
+///
+template< TargetType K, TargetType T >
+inline constexpr bool is_same(void)
+{
+    return (K & T) != 0;
+}
+}
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/fapi2_vpd_access.H b/src/import/hwpf/fapi2/include/fapi2_vpd_access.H
new file mode 100644
index 00000000..d5b946b0
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/fapi2_vpd_access.H
@@ -0,0 +1,96 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/fapi2_vpd_access.H $                */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file fapi2_vpd_access.H
+/// @brief Common file that defines the vpd access functions that
+/// platform code must implement.
+///
+//
+
+#ifndef _FAPI2_VPDACCESS_H_
+#define _FAPI2_VPDACCESS_H_
+
+#include <return_code.H>
+#include <target_types.H>
+#include <vpd_access_defs.H>
+#include <plat_vpd_access.H>
+
+namespace fapi2
+{
+
+/// constants for VPD Info
+constexpr uint64_t VPD_INFO_INVALID  = 0xffffffffffffffff;
+
+/// @brief  Specialized class representing required VPDInfo to be used
+///         in collecting VPD for the MCS target type.
+/// @tparam T fapi2::TARGET_TYPE_MCS
+template<>
+class VPDInfo<TARGET_TYPE_MCS>
+{
+    public:
+        // @brief VPDInfo constructor
+        VPDInfo( const fapi2::MemVpdData& i_vpd_type)
+            : iv_vpd_type(i_vpd_type),
+              iv_size(VPD_INFO_INVALID),
+              iv_freq_mhz(VPD_INFO_INVALID),
+              iv_rank_count_dimm_0(VPD_INFO_INVALID),
+              iv_rank_count_dimm_1(VPD_INFO_INVALID)
+        {};
+        // type of vpd field to return
+        fapi2::MemVpdData_t iv_vpd_type;
+
+        // size of the vpd data
+        size_t   iv_size;
+        uint64_t iv_freq_mhz;
+        uint64_t iv_rank_count_dimm_0;
+        uint64_t iv_rank_count_dimm_1;
+
+};
+
+
+/// @brief Return a blob of memory VPD data associated with the input target
+/// @param[in] i_target     a valid fapi2 target
+/// @param[in] io_vpd_info  fapi2::VPDInfo class that specifies which piece of data to return
+/// @param[out] o_blob      the blob of raw data from the vpd
+/// @return FAPI2_RC_SUCCESS if there's no problem
+/// @note passing nullptr for o_blob will return the size of the keyword
+///
+/// Example:
+/// fapi2::VPDInfo<fapi2::TARGET_TYPE_MCS> vpdInfo(MR_keyword);
+/// vpdInfo.iv_freq = 2667;
+///
+/// uint8_t * blob = NULL;
+///
+/// FAPI_TRY(getVPD( mcs, vpdInfo, blob ));
+/// blob = static_cast<uint8_t *>(malloc(vpdInfo.iv_size));
+/// FAPI_TRY(getVPD( mcs, vpdInfo, blob ));
+/// blob now contains the VPD data for the MCS.
+///
+template<TargetType T, typename V>
+ReturnCode getVPD(const Target<T, V>& i_target,
+                  VPDInfo<T>& io_vpd_info,
+                  uint8_t* o_blob);
+
+};
+#endif
diff --git a/src/import/hwpf/fapi2/include/ffdc.H b/src/import/hwpf/fapi2/include/ffdc.H
new file mode 100644
index 00000000..82483d54
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/ffdc.H
@@ -0,0 +1,238 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/ffdc.H $                            */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ *  @file ffdc.H
+ *  @brief Defines the FirstFailureData class
+ */
+
+#ifndef FAPI2_FFDC_H_
+#define FAPI2_FFDC_H_
+
+#include <memory>
+#include <hwp_return_codes.H>
+#include <return_code_defs.H>
+#include <plat_trace.H>
+#include <error_info.H>
+#include <target.H>
+
+using fapi2::TARGET_TYPE_ALL;
+
+namespace fapi2
+{
+///
+/// @brief Check the type of a variable
+///
+/// This function can be called to check that a variable type is as expected
+/// @note This mechanism will allow for cast ctor's which other static type
+/// checking might not.
+///
+template<typename T>
+inline
+void checkType(const T&) {}
+
+class ReturnCode;
+
+///
+/// @class FirstFailureData
+///
+/// This class provides storage and methods for creating and manipulating
+/// FFDC.
+/// It is not needed on all platforms - platforms which need this class have
+/// specified this by forcing their fapi2::ReturnCode to be a subclass of
+/// this class.
+///
+template< class R = fapi2::ReturnCode >
+class FirstFailureData
+{
+    public:
+
+        ///
+        /// @brief Default constructor.
+        /// @note We don't create our error info by default. It will be created
+        /// when its needed in the setHwpError() method. Note that dereferencing
+        /// the error info without first calling setHwpError() will create a
+        //  problem.
+        ///
+        FirstFailureData(void):
+            iv_info( nullptr ), iv_platDataPtr(nullptr)
+        {}
+
+        ///
+        /// @brief Copy Constructor
+        ///
+        /// @param[in] i_right Reference to FirstFailureData to copy
+        /// @note Generates default copy constructor - no deep pointer
+        /// copies necessary.
+        ///
+        FirstFailureData(const FirstFailureData& i_right) = default;
+
+        ///
+        /// @brief Destructor
+        ///
+        ~FirstFailureData(void) = default;
+
+        ///
+        /// @brief Assignment Operator.
+        ///
+        /// @param[in] i_right Reference to FirstFailureData to assign from.
+        /// @return Reference to 'this' FirstFailureData
+        ///
+        FirstFailureData& operator=(const FirstFailureData& i_right) = default;
+
+        ///
+        /// @brief Sets a HWP error. Sets the rcValue to the supplied value (from
+        ///      the HwpFirstFailureData enumeration) and deletes any
+        /// associated data.
+        ///
+        /// HWP code must call the FAPI_SET_HWP_ERROR macro rather than this
+        /// function
+        /// directly to generate an error so that any error information is
+        /// automatically added to the FirstFailureData
+        ///
+        /// @param[in] i_rcValue Error value to set
+        ///
+        inline void _setHwpError(const fapi2::HwpReturnCode i_rcValue)
+        {
+            FAPI_ERR("_setHwpError: Creating HWP error 0x%x", i_rcValue);
+            static_cast<R*>(this)->operator=(i_rcValue);
+
+            // Forget about any associated data (this is a new error)
+            iv_info.reset( new ErrorInfo());
+
+        }
+
+        ///
+        /// @return void *. Pointer to error info data. If NULL then no data
+        ///
+        void* getData(void) const;
+
+        ///
+        /// @brief Get a pointer to any error info and release ownership from
+        ///      FirstFailureData. The caller is responsible for deletion.
+        ///
+        /// This is called by PLAT. The expected use-case is to retrieve a
+        /// platform error log.
+        ///
+        /// @return void*. Pointer to any Error data. If NULL then no data
+        ///
+        inline void* releaseData(void)
+        {
+            void* l_pData = iv_info;
+            iv_info = NULL;
+            return l_pData;
+        }
+
+        ///
+        /// @brief Add ErrorInfo
+        ///
+        /// This is called by the FAPI_SET_HWP_ERROR and macro to add ErrorInfo
+        /// to the FirstFailureData when a HWP generates an error. The function
+        /// is designed to add all the ErrorInfo at once rather than the
+        /// FAPI_SET_HWP_ERROR macro making multiple function calls to add each
+        /// piece of ErrorInfo individually in order to minimize code size
+        ///
+        /// @param[in] i_pObjects Pointer to array of const pointers to const
+        ///     objects that are referred to by ErrorInfoEntry objects
+        /// @param[in] i_pEntries Pointer to array of ErrorInfoEntry objects
+        ///     defining the ErrorInfo that needs to be added
+        /// @param[in] i_count    Number of ErrorInfoEntry entries
+        ///
+        void addErrorInfo(const void* const* i_pObjects,
+                          const ErrorInfoEntry* i_pEntries,
+                          const uint8_t i_count);
+
+
+        ///
+        /// @brief Add ErrorInfo
+        ///
+        /// This is called by the collectFfdc and collectRegFfdc functions
+        /// following the call to actually collect the ffdc data, the ffdc
+        /// collection functions return a vector of shared pointers to the
+        /// ErrorInfoFfdc objects
+        ///
+        /// @param[in] i_errorInfo - vector of shared pointers to
+        ///                          errorInfoFfdc objects
+        ///
+        inline void addErrorInfo(std::vector<std::shared_ptr<ErrorInfoFfdc>>& i_errorInfo)
+        {
+            for( auto p : i_errorInfo )
+            {
+                iv_info->iv_ffdcs.push_back(p);
+            }
+        };
+
+        ///
+        /// @brief Get a pointer to any ErrorInfo
+        ///
+        /// This is called by PLAT to find information about an error
+        ///
+        /// @return ErrorInfo *. Pointer to any ErrorInfo. If NULL then no info
+        ///
+        inline const fapi2::ErrorInfo* getErrorInfo(void) const
+        {
+            return iv_info.get();
+        }
+
+        ///
+        /// @brief Forgets about any associated data (PlatData and ErrorInfo)
+        ///
+        /// If this is the only FirstFailureData pointing to the data then the
+        /// data is deleted
+        ///
+        inline void forgetData(void)
+        {
+            iv_info = nullptr;
+        }
+
+        ///
+        /// @brief Returns the platform data pointer value to the caller.
+        ///
+        inline void* getPlatDataPtr()
+        {
+            return iv_platDataPtr;
+        };
+
+        ///
+        /// @brief Sets objects platform data pointer to the passed in value.
+        ///
+        ///
+        inline void  setPlatDataPtr( void* i_ptr )
+        {
+            static_cast<R*>(this)->operator=(FAPI2_RC_PLAT_ERR_SEE_DATA);
+            iv_platDataPtr = i_ptr;
+        };
+
+
+    protected:
+        // Pointer to the error info
+        std::shared_ptr<ErrorInfo> iv_info;
+
+    private:
+        // free format data, to be used by the platform
+        void*    iv_platDataPtr;
+};
+
+}
+#endif // FAPI2_FFDC_H_
diff --git a/src/import/hwpf/fapi2/include/hw_access_def.H b/src/import/hwpf/fapi2/include/hw_access_def.H
new file mode 100644
index 00000000..9d67961c
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/hw_access_def.H
@@ -0,0 +1,83 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/hw_access_def.H $                   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file hw_access_def.H
+/// @brief Hardware access definitions
+///
+
+#ifndef FAPI2_HWACCESSDEF_H_
+#define FAPI2_HWACCESSDEF_H_
+
+#include <stdint.h>
+
+/// @cond
+typedef uint64_t spyId_t;
+typedef uint64_t scanRingId_t;
+/// @endcond
+
+namespace fapi2
+{
+///
+/// @enum fapi2::ChipOpModifyMode
+/// @brief Enumeration of modify modes used in HW access modify operations
+///
+enum ChipOpModifyMode
+{
+    CHIP_OP_MODIFY_MODE_OR = 1,  ///< Modify or mode
+    CHIP_OP_MODIFY_MODE_AND = 2, ///< Modify and mode
+    CHIP_OP_MODIFY_MODE_XOR = 3, ///< Modify xor mode
+};
+
+///
+/// @enum fapi2::RingMode
+/// @brief Enumeration of Ring access operation modes
+///        This is a bitmap to allow the user to specify multiple modes.
+///
+enum RingMode
+{
+    RING_MODE_HEADER_CHECK              = 0x00000000, ///< Check header
+    RING_MODE_SET_PULSE_NO_OPCG_COND    = 0x00000001, ///< Set pulse with
+    ///  no OPCG conditioning
+    RING_MODE_NO_HEADER_CHECK           = 0x00000002, ///< Don't check header
+    RING_MODE_SET_PULSE_NSL             = 0x00000004, ///< Set pulse with NSL
+    ///  pulse
+    RING_MODE_SET_PULSE_SL              = 0x00000008, ///< Set pulse with SL
+    ///  pulse
+    RING_MODE_SET_PULSE_ALL             = 0x00000010, ///< Set pulse with pulse
+    ///  to all hold types
+};
+
+/// @enum OpModes operational Mode Error Functions
+enum OpModes
+{
+    // These are bit-masks in case they need to be or'd together
+    NORMAL           = 0x00,
+    IGNORE_HW_ERROR  = 0x01,
+    DO_NOT_DO_WAKEUP = 0x02,
+};
+
+}
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/mvpd_access.H b/src/import/hwpf/fapi2/include/mvpd_access.H
new file mode 100644
index 00000000..532b32ee
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/mvpd_access.H
@@ -0,0 +1,87 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/mvpd_access.H $                     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file mvpd_access.H
+///
+/// @brief Defines the Module VPD functions that platform must implement
+///
+
+#ifndef _FAPI2_MVPDACCESS_H_
+#define _FAPI2_MVPDACCESS_H_
+
+#include <stdint.h>
+#include <return_code.H>
+#include <target.H>
+#include <mvpd_access_defs.H>
+
+namespace fapi2
+{
+///
+/// @brief Get Module VPD field.
+///
+/// A Module VPD field is specified using a record and keyword enumerator
+///
+/// Suggested way to call this routine is to call it once with a NULL buffer
+/// pointer to to retrieve the size of the record, then allocate the proper
+/// size of the buffer and call again.
+///
+/// @param[in] i_record     Record enumerator
+/// @param[in] i_keyword    Keyword enumerator
+/// @param[in] i_target     Reference to processor chip target for the record
+/// @param[in] i_pBuffer    Pointer to buffer where record will be stored. If
+///                         NULL then the size of record will be stored in
+///                         io_fieldSize
+/// @param[in,out] io_fieldSize Size of i_pBuffer in bytes
+///
+/// @return fapi2::ReturnCode. FAPI_RC_SUCCESS, or failure value.
+///
+ReturnCode getMvpdField(const MvpdRecord i_record,
+                        const MvpdKeyword i_keyword,
+                        const Target<TARGET_TYPE_PROC_CHIP>& i_target,
+                        uint8_t* const i_pBuffer,
+                        uint32_t& io_fieldSize);
+
+///
+/// @brief Set Module VPD field.
+///
+/// A Module VPD field is specified using a record and keyword enumerator
+///
+/// @param[in] i_record     Record enumerator
+/// @param[in] i_keyword    Keyword enumerator
+/// @param[in] i_target     Reference to processor chip target for the record
+/// @param[in] i_pBuffer    Pointer to buffer where data to set is stored
+/// @param[in] i_fieldSize  Size of i_pBuffer in bytes
+///
+/// @return fapi2::ReturnCode. FAPI_RC_SUCCESS, or failure value.
+///
+ReturnCode setMvpdField(const MvpdRecord i_record,
+                        const MvpdKeyword i_keyword,
+                        const Target<TARGET_TYPE_PROC_CHIP>& i_target,
+                        const uint8_t* const i_pBuffer,
+                        const uint32_t i_fieldSize);
+}
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/mvpd_access_defs.H b/src/import/hwpf/fapi2/include/mvpd_access_defs.H
new file mode 100644
index 00000000..a1a4aaff
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/mvpd_access_defs.H
@@ -0,0 +1,121 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/mvpd_access_defs.H $                */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file mvpd_access_defs.H
+///
+/// @brief Defines the Module VPD Records and Keywords
+///
+
+#ifndef _FAPI2_MVPDACCESS_DEFS_H_
+#define _FAPI2_MVPDACCESS_DEFS_H_
+
+namespace fapi2
+{
+enum MvpdRecord
+{
+    MVPD_RECORD_CRP0 = 0x00,
+    MVPD_RECORD_CP00 = 0x01,
+    MVPD_RECORD_VINI = 0x02,
+    MVPD_RECORD_LRP0 = 0x03,
+    MVPD_RECORD_LRP1 = 0x04,
+    MVPD_RECORD_LRP2 = 0x05,
+    MVPD_RECORD_LRP3 = 0x06,
+    MVPD_RECORD_LRP4 = 0x07,
+    MVPD_RECORD_LRP5 = 0x08,
+    MVPD_RECORD_LRP6 = 0x09,
+    MVPD_RECORD_LRP7 = 0x0a,
+    MVPD_RECORD_LRP8 = 0x0b,
+    MVPD_RECORD_LRP9 = 0x0c,
+    MVPD_RECORD_LRPA = 0x0d,
+    MVPD_RECORD_LRPB = 0x0e,
+    MVPD_RECORD_LRPC = 0x0f,
+    MVPD_RECORD_LRPD = 0x10,
+    MVPD_RECORD_LRPE = 0x11,
+    MVPD_RECORD_LWP0 = 0x12,
+    MVPD_RECORD_LWP1 = 0x13,
+    MVPD_RECORD_LWP2 = 0x14,
+    MVPD_RECORD_LWP3 = 0x15,
+    MVPD_RECORD_LWP4 = 0x16,
+    MVPD_RECORD_LWP5 = 0x17,
+    MVPD_RECORD_LWP6 = 0x18,
+    MVPD_RECORD_LWP7 = 0x19,
+    MVPD_RECORD_LWP8 = 0x1a,
+    MVPD_RECORD_LWP9 = 0x1b,
+    MVPD_RECORD_LWPA = 0x1c,
+    MVPD_RECORD_LWPB = 0x1d,
+    MVPD_RECORD_LWPC = 0x1e,
+    MVPD_RECORD_LWPD = 0x1f,
+    MVPD_RECORD_LWPE = 0x20,
+    MVPD_RECORD_VWML = 0x21,
+    MVPD_RECORD_MER0 = 0x22,
+    MVPD_RECORD_LAST, //useful for testcases
+    MVPD_RECORD_FIRST = MVPD_RECORD_CRP0, //useful for testcases
+};
+
+enum MvpdKeyword
+{
+    MVPD_KEYWORD_VD  = 0x00,
+    MVPD_KEYWORD_ED  = 0x01,
+    MVPD_KEYWORD_TE  = 0x02,
+    MVPD_KEYWORD_DD  = 0x03,
+    MVPD_KEYWORD_PDP = 0x04,
+    MVPD_KEYWORD_ST  = 0x05,
+    MVPD_KEYWORD_DN  = 0x06,
+    MVPD_KEYWORD_PG  = 0x07,
+    MVPD_KEYWORD_PK  = 0x08,
+    MVPD_KEYWORD_PDR = 0x09,
+    MVPD_KEYWORD_PDV = 0x0a,
+    MVPD_KEYWORD_PDH = 0x0b,
+    MVPD_KEYWORD_SB  = 0x0c,
+    MVPD_KEYWORD_DR  = 0x0d,
+    MVPD_KEYWORD_VZ  = 0x0e,
+    MVPD_KEYWORD_CC  = 0x0f,
+    MVPD_KEYWORD_CE  = 0x10,
+    MVPD_KEYWORD_FN  = 0x11,
+    MVPD_KEYWORD_PN  = 0x12,
+    MVPD_KEYWORD_SN  = 0x13,
+    MVPD_KEYWORD_PR  = 0x14,
+    MVPD_KEYWORD_HE  = 0x15,
+    MVPD_KEYWORD_CT  = 0x16,
+    MVPD_KEYWORD_HW  = 0x17,
+    MVPD_KEYWORD_PDM = 0x18,
+    MVPD_KEYWORD_IN  = 0x19,
+    MVPD_KEYWORD_PD2 = 0x1a,
+    MVPD_KEYWORD_PD3 = 0x1b,
+    MVPD_KEYWORD_OC  = 0x1c,
+    MVPD_KEYWORD_FO  = 0x1d,
+    MVPD_KEYWORD_PDI = 0x1e,
+    MVPD_KEYWORD_PDG = 0x1f,
+    MVPD_KEYWORD_MK  = 0x20,
+    MVPD_KEYWORD_PB  = 0x21,
+    MVPD_KEYWORD_CH  = 0x22,
+    MVPD_KEYWORD_IQ  = 0x23,
+    MVPD_KEYWORD_LAST, //useful for testcases
+    MVPD_KEYWORD_FIRST = MVPD_KEYWORD_VD, //useful for testcases
+};
+}
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/plat/hw_access.H b/src/import/hwpf/fapi2/include/plat/hw_access.H
new file mode 100644
index 00000000..fbe8ae6e
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/plat/hw_access.H
@@ -0,0 +1,560 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/plat/hw_access.H $                  */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+/// @file hw_access.H
+///
+/// @brief Hardware access functions that needs to be specialized for
+/// platform implementation.
+///
+
+#ifndef _FAPI2_HWACCESS_H_
+#define _FAPI2_HWACCESS_H_
+
+// variable_buffer isn't supported on PPE
+#ifndef __PPE__
+    #include <variable_buffer.H>
+#endif
+
+#include <plat_hw_access.H>
+#include <fapi2_hw_access.H>
+
+namespace fapi2
+{
+//--------------------------------------------------------------------------
+// PIB Error Functions
+//--------------------------------------------------------------------------
+
+/// @brief Sets the PIB error mask - platform dependant
+/// @param[in]  i_mask     The new error mask
+// note: this can be moved  to a C file if desired
+inline void setPIBErrorMask(uint8_t i_mask)
+{
+    // Keeps the compiler from complaining about the unused i_mask
+    static_cast<void>(i_mask);
+
+    return;
+}
+
+/// @brief Gets the PIB error mask - platform dependant
+/// @return uint8_t The current PIB error mask
+// note: this can be moved  to a C file if desired
+inline uint8_t getPIBErrorMask(void)
+{
+    return 0;
+}
+
+//--------------------------------------------------------------------------
+// Operational Mode Error Functions
+//--------------------------------------------------------------------------
+
+/// @brief Sets the operational mode
+/// @param[in]  i_mode     The new mode
+// note: this can be moved  to a C file if desired
+inline void setOpMode(const OpModes i_mode)
+{
+    // Keeps the compiler from complaining about the unused i_mode
+    static_cast<void>(i_mode);
+
+    // No-op for now. Should set thread-local operational mode
+    return;
+}
+
+/// @brief Gets the operational mode
+/// @return the operational mode
+// note: this can be moved  to a C file if desired
+inline OpModes getOpMode(void)
+{
+    // No-op for now. Should read thread-local operational mode
+    return NORMAL;
+}
+
+//------------------------------------------------------------------------------
+// HW Communication Functions to be implemented at the platform layer.
+//------------------------------------------------------------------------------
+
+///
+/// @brief Platform-level implementation of getScom()
+/// @tparam K template parameter, passed in target.
+/// @param[in]  i_target   HW target to operate on.
+/// @param[in]  i_address  SCOM register address to read from.
+/// @param[out] o_data     Buffer that holds data read from HW target.
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+template< TargetType K, typename V >
+inline ReturnCode getScom(const Target<K, V>& i_target,
+                          const uint64_t i_address,
+                          buffer<uint64_t>& o_data)
+{
+    o_data = 0x0000FEEDFACE0000;
+    std::cout << std::hex << "   getScom "
+              << "target: {" << i_target.getType() << ","
+              << uint64_t(i_target) << "}; "
+              << "address: " << i_address << "; "
+              << "output data: " << uint64_t(o_data)
+              << std::dec << std::endl;
+
+    return FAPI2_RC_SUCCESS;
+}
+
+/// @brief Platform-level implementation of putScom()
+/// @tparam K template parameter, passed in target.
+/// @param[in] i_target     HW target to operate on.
+/// @param[in] i_address    SCOM register address to write to.
+/// @param[in] i_data       Buffer that holds data to write into address.
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+template< TargetType K, typename V >
+inline ReturnCode putScom(const Target<K, V>& i_target,
+                          const uint64_t i_address,
+                          const buffer<uint64_t> i_data)
+{
+    std::cout << std::hex << "   putScom "
+              << "target: {" << i_target.getType() << ","
+              << uint64_t(i_target) << "}; "
+              << "address: " << i_address << "; "
+              << "input data: " << uint64_t(i_data)
+              << std::dec << std::endl;
+    return FAPI2_RC_SUCCESS;
+}
+
+/// @brief Platform-level implementation of putScomUnderMask()
+/// @tparam K template parameter, passed in target.
+/// @param[in] i_target     HW target to operate on.
+/// @param[in] i_address    SCOM register address to write to.
+/// @param[in] i_data       Buffer that holds data to write into address.
+/// @param[in] i_mask       Buffer that holds the mask value.
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+template< TargetType K, typename V >
+inline ReturnCode putScomUnderMask(const Target<K, V>& i_target,
+                                   const uint64_t i_address,
+                                   const buffer<uint64_t> i_data,
+                                   const buffer<uint64_t> i_mask)
+{
+    std::cout << std::hex << "   putScomUnderMask "
+              << "target: {" << i_target.getType() << ","
+              << uint64_t(i_target) << "}; "
+              << "address: " << i_address << "; "
+              << "input data: " << uint64_t(i_data) << "; "
+              << "input mask: " << uint64_t(i_mask)
+              << std::dec << std::endl;
+    return FAPI2_RC_SUCCESS;
+}
+
+///
+/// @brief Platform-level implementation called by getCfamRegister()
+/// Hardware procedures writers will not call this function.
+/// @tparam K template parameter, passed in target.
+/// @param[in]  i_target   HW target to operate on.
+/// @param[in]  i_address  CFAM address to read from.
+/// @param[out] o_data     32-bit buffer that holds data read from HW target.
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+template< TargetType K, typename V >
+inline ReturnCode getCfamRegister(const Target<K, V>& i_target,
+                                  const uint32_t i_address,
+                                  buffer<uint32_t>& o_data)
+{
+    o_data = 0xFEED0CFA;
+    std::cout << std::hex << "   getCfamRegister "
+              << "target: {" << i_target.getType() << ","
+              << uint64_t(i_target) << "}; "
+              << "address: " << i_address << "; "
+              << "output data: " << uint32_t(o_data)
+              << std::dec << std::endl;
+    return FAPI2_RC_SUCCESS;
+}
+
+///
+/// @brief Platform-level implementation of putCfamRegister()
+/// Hardware procedures writers will not call this function.
+/// @tparam K template parameter, passed in target.
+/// @param[in]  i_target   HW target to operate on.
+/// @param[in]  i_address  CFAM address to write to.
+/// @param[out] i_data     32-bit buffer that holds data to write into address.
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+template< TargetType K, typename V >
+inline ReturnCode putCfamRegister(const Target<K, V>& i_target,
+                                  const uint32_t i_address,
+                                  const buffer<uint32_t> i_data)
+{
+    std::cout << std::hex << "   putCfamRegister "
+              << "target: {" << i_target.getType() << ","
+              << uint64_t(i_target) << "}; "
+              << "address: " << i_address << "; "
+              << "input data: " << uint32_t(i_data)
+              << std::dec << std::endl;
+    return FAPI2_RC_SUCCESS;
+}
+
+
+///
+/// @brief Platform-level implementation of modifyCfamRegister()
+/// Hardware procedures writers will not call this function.
+/// @tparam K template parameter, passed in target.
+/// @param[in]  i_target     HW target to operate on.
+/// @param[in]  i_address    CFAM register address to modify.
+/// @param[out] i_data       32-bit buffer that holds data to modify.
+/// @param[in]  i_modifyMode The modify mode (or/and/xor).
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+template< TargetType K, typename V >
+inline ReturnCode modifyCfamRegister(const Target<K, V>& i_target,
+                                     const uint32_t i_address,
+                                     const buffer<uint32_t> i_data,
+                                     const fapi2::ChipOpModifyMode i_modifyMode)
+{
+    std::cout << std::hex << "   modifyCfamRegister "
+              << "target: {" << i_target.getType() << ","
+              << uint64_t(i_target) << "}; "
+              << "address: " << i_address << "; "
+              << "input modifying data: " << uint32_t(i_data) << "; "
+              << "input ChipOpModifyMode: " << i_modifyMode
+              << std::dec << std::endl;
+    return FAPI2_RC_SUCCESS;
+}
+
+/// @brief Platform-level implementation  of putRing()
+/// Hardware procedures writers will not call this function.
+/// @tparam K template parameter, passed in target.
+/// @param[in] i_target   Target to operate on.
+/// @param[in] i_ringID   Ring ID that will identify the Ring in the image.
+/// @param[in] i_ringMode Ring operation mode.
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+template< TargetType K, typename V >
+ReturnCode putRing(const Target<K, V>& i_target,
+                   const RingID i_ringID,
+                   const RingMode i_ringMode)
+{
+    std::cout << std::hex << "   putRing "
+              << "target: {" << i_target.getType() << ","
+              << uint64_t(i_target) << "}; "
+              << "Ring ID: " << i_ringID << "; "
+              << "ring mode: " << i_ringMode
+              << std::endl;
+
+    return FAPI2_RC_SUCCESS;
+}
+
+// variable_buffer isn't supported on PPE
+#ifndef __PPE__
+///
+/// @brief Platform-level implementation of getRing()
+/// Hardware procedures writers will not call this function.
+/// @tparam K template parameter, passed in target.
+/// @param[in]  i_target   HW target to operate on.
+/// @param[in]  i_address  Ring address to read from.
+/// @param[out] o_data     Buffer that holds ring data read from HW target.
+/// @param[in]  i_ringMode Ring operation mode.
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+template< TargetType K, typename V >
+inline ReturnCode getRing(const Target<K, V>& i_target,
+                          const scanRingId_t i_address,
+                          variable_buffer& o_data,
+                          const RingMode i_ringMode)
+{
+    o_data.setBit(0);
+    o_data.setBit(3);
+    std::cout << std::hex << "   getRing "
+              << "target: {" << i_target.getType() << ","
+              << uint64_t(i_target) << "}; "
+              << "ring address: " << i_address << "; "
+              << "ring mode: " << i_ringMode << "; "
+              << "first element of output data: " << o_data()[0]
+              << std::endl;
+
+    return FAPI2_RC_SUCCESS;
+}
+
+/// @brief Platform-level implementation of modifyRing()
+/// @tparam K template parameter, passed in target.
+/// @param[in] i_target     Target to operate on.
+/// @param[in] i_address    Ring address to modify.
+/// @param[in] i_data       Buffer that contains RS4 compressed ring data
+///                         to be modified.
+/// @param[in] i_modifyMode The modify mode (or/and/xor)
+/// @param[in] i_ringMode   Ring operation mode.
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+template< TargetType K, typename V >
+inline ReturnCode modifyRing(const Target<K, V>& i_target,
+                             const scanRingId_t i_address,
+                             const variable_buffer& i_data,
+                             const ChipOpModifyMode i_modifyMode,
+                             const RingMode i_ringMode)
+{
+    std::cout << std::hex << "   modifyRing "
+              << "target: {" << i_target.getType() << ","
+              << uint64_t(i_target) << "}; "
+              << "address: " << i_address << "; "
+              << "input ChipOpModifyMode: " << i_modifyMode << "; "
+              << "ring mode: " << i_ringMode << "; "
+              << "first element of the input data: " << i_data()[0]
+              << std::endl;
+
+    return FAPI2_RC_SUCCESS;
+}
+#endif
+
+// --------------------------------------------------------------------------
+// NOTE:
+// Implement platform Spy access functions if platform supports them.
+// --------------------------------------------------------------------------
+
+// variable_buffer isn't supported on PPE
+#ifndef __PPE__
+/// @brief Reads a spy from a chip.
+/// @tparam K template parameter, passed in target.
+/// @param[in]  i_target   Target to operate on.
+/// @param[in]  i_spyId    Id of the spy whose data to be read.
+/// @param[out] o_data     Buffer that holds data read from HW target.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+/// @note:  The string version is only supported for cronus.
+///
+///         The fapi design to support both FSP and cronus use of get and
+///         put spy functions is dependant on the SPY names being expanded
+///         to resemble a valid C identifier. This design places some
+///         restrictions on the SPY names which can be used.
+///
+///         1. if the spy name contains a # procedure writers should replace
+///         it with an __P__ for example -
+///
+///         ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+///         becomes
+///         ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS
+///
+///         2. if the spy name has a number following a "." it must have an
+///         underscore prepended to the number.
+///
+///         EH.TPCHIP.2KX100_ARY_CLK_EDGES_DLY
+///         becomes
+///         EH.TPCHIP._2KX100_ARY_CLK_EDGES_DLY
+///
+///         Example SPY name:
+///         The hardware procedure should call the function like:
+///
+///          ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+///
+///          fapi2::ReturnCode rc = fapiGetSpy( targ,
+///                  ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS, data );
+///
+/// @note The ID is not in quotes the fapi code will handle adding
+///       the quotes for the cronus environment
+///
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+template< TargetType K, typename V >
+inline ReturnCode getSpy(const Target<K, V>& i_target,
+                         const spyId_t i_spyId,
+                         variable_buffer& o_data)
+{
+    static_assert(K == 0, "implement getSpy (enum)");
+    return ~FAPI2_RC_SUCCESS;
+}
+
+template< TargetType K >
+inline ReturnCode getSpy(const Target<K>& i_target,
+                         const spyId_t i_spyId,
+                         variable_buffer& o_data,
+                         const RingMode i_ringMode)
+{
+    static_assert(K == 0, "implement getSpy (enum)");
+    return ~FAPI2_RC_SUCCESS;
+}
+#endif
+#ifdef FAPI_SUPPORT_SPY_AS_STRING
+template< TargetType K, typename V >
+inline ReturnCode getSpy(const Target<K, V>& i_target,
+                         const char* const i_spyId,
+                         variable_buffer& o_data)
+{
+    static_assert(K == 0, "implement getSpy (string)");
+    return ~FAPI2_RC_SUCCESS;
+}
+
+template< TargetType K >
+inline ReturnCode getSpy(const Target<K>& i_target,
+                         const char* const i_spyId,
+                         variable_buffer& o_data,
+                         const RingMode i_ringMode)
+{
+    static_assert(K == 0, "implement getSpy (string)");
+    return ~FAPI2_RC_SUCCESS;
+}
+#endif
+/// @brief Writes a spy on a chip.
+/// @tparam K template parameter, passed in target.
+/// @param[in]  i_target   Target to operate on.
+/// @param[in]  i_spyId    Id of the spy to write data to.
+/// @param[out] i_data     Buffer that holds data to write into spy.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+/// @note:  The string version is only supported for cronus.
+///
+///         The fapi design to support both FSP and cronus use of get and
+///         put spy functions is dependent on the SPY names being expanded
+///         to resemble a valid C identifier. This design places some
+///         restrictions on the SPY names which can be used.
+///
+///         1. if the spy name contains a # procedure writers should replace
+///         is with an __P__ for example -
+///
+///         ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+///         becomes
+///         ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS
+///
+///         2. if the spy name has a number following a "." it must have an
+///         underscore prepended to the number.
+///
+///         EH.TPCHIP.2KX100_ARY_CLK_EDGES_DLY
+///         becomes
+///         EH.TPCHIP._2KX100_ARY_CLK_EDGES_DLY
+///
+///         Example SPY name:
+///         The hardware procedure should call the function like:
+///
+///          ABUS.RX0.RXPACKS#0.RXPACK.RD.LC.LC.ACT_DIS
+///
+///          fapi2::ReturnCode rc = fapiPutSpy( targ,
+///                  ABUS.RX0.RXPACKS__P__0.RXPACK.RD.LC.LC.ACT_DIS, data );
+///
+/// @note The ID is not in quotes the fapi code will handle adding
+///         the quotes for the cronus environment
+///
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+template< TargetType K, typename V >
+inline ReturnCode putSpy(const Target<K, V>& i_target,
+                         const spyId_t i_spyId,
+                         const variable_buffer& i_data)
+{
+    static_assert(K == 0, "implement putSpy (enum)");
+    return ~FAPI2_RC_SUCCESS;
+}
+#endif
+#ifdef FAPI_SUPPORT_SPY_AS_STRING
+template< TargetType K, typename V >
+inline ReturnCode putSpy(const Target<K, V>& i_target,
+                         const char* const i_spyId,
+                         const variable_buffer& i_data)
+{
+    static_assert(K == 0, "implement putSpy (string)");
+    return ~FAPI2_RC_SUCCESS;
+}
+
+template< TargetType K, typename V >
+inline ReturnCode putSpy(const Target<K, V>& i_target,
+                         const char* const i_spyId,
+                         const char* i_enum)
+{
+    static_assert(K == 0, "implement putSpy (string)");
+    return ~FAPI2_RC_SUCCESS;
+}
+#endif
+/// @brief Writes spy data into a buffer holding ring data image
+///        This API is used by L2/L3 repair to put column repair data
+///        into a ring buffer image.
+/// @tparam K template parameter, passed in target.
+/// @param[in]  i_target      Target to operate on.
+/// @param[in]  i_spyId       Id of the spy.
+/// @param[in]  i_data        Buffer that holds spy data to write into ring
+///                           image.
+/// @param[out] o_imageData   Buffer that holds updated ring image.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+/// @note:  The string version is only supported for cronus.
+///
+///         The fapi design to support both FSP and cronus use of get and
+///         put spy functions is dependent on the SPY names being expanded
+///         to resemble a valid C identifier. This design places some
+///         restrictions on the SPY names which can be used.
+///
+///         See fapiPutSpy for details on spy id specifics.
+///
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+template< TargetType K, typename V >
+inline ReturnCode putSpyImage(const Target<K, V>& i_target,
+                              const spyId_t i_spyId,
+                              const variable_buffer& i_data,
+                              variable_buffer& o_imageData)
+{
+    static_assert(K == 0, "implement putSpyImage (enum)");
+    return ~FAPI2_RC_SUCCESS;
+}
+#endif
+#ifdef FAPI_SUPPORT_SPY_AS_STRING
+template< TargetType K, typename V >
+inline ReturnCode putSpyImage(const Target<K, V>& i_target,
+                              const char* const i_spyId,
+                              const variable_buffer& i_data,
+                              variable_buffer& o_imageData)
+{
+    static_assert(K == 0, "implement putSpyImage (string)");
+    return ~FAPI2_RC_SUCCESS;
+}
+#endif
+/// @brief Reads spy data from a ring image buffer
+/// @param[in]   i_target      Target to operate on
+/// @param[in]   i_spyId       The spy's id
+/// @param[out]  o_data        Buffer that holds data read from ring image.
+/// @param[in]   i_imageData   Buffer that holds ring image to read data
+///                            from.
+/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+/// @note:  The string version is only supported for cronus.
+///
+///         The fapi design to support both FSP and cronus use of get and
+///         put spy functions is dependent on the SPY names being expanded
+///         to resemble a valid C identifier. This design places some
+///         restrictions on the SPY names which can be used.
+///
+///         See fapiPutSpy for details on spy id specifics.
+///
+#ifdef FAPI_SUPPORT_SPY_AS_ENUM
+template< TargetType K, typename V >
+inline ReturnCode getSpyImage(const Target<K, V>& i_target,
+                              const spyId_t i_spyId,
+                              variable_buffer& o_data,
+                              const variable_buffer& i_imageData)
+{
+    static_assert(K == 0, "implement getSpyImage (enum)");
+    return ~FAPI2_RC_SUCCESS;
+}
+#endif
+#ifdef FAPI_SUPPORT_SPY_AS_STRING
+template< TargetType K, typename V >
+inline ReturnCode getSpyImage(const Target<K, V>& i_target,
+                              const char* const i_spyId,
+                              variable_buffer& o_data,
+                              const variable_buffer& i_imageData)
+{
+    static_assert(K == 0, "implement getSpyImage (string)");
+    return ~FAPI2_RC_SUCCESS;
+}
+#endif
+
+#endif // PPE
+
+};
+
+#endif // _FAPI2_HWACCESS_H_
diff --git a/src/import/hwpf/fapi2/include/plat/plat_error_scope.H b/src/import/hwpf/fapi2/include/plat/plat_error_scope.H
new file mode 100644
index 00000000..4b198a10
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/plat/plat_error_scope.H
@@ -0,0 +1,89 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/plat/plat_error_scope.H $           */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file plat_error_scope.H
+ * @brief platform definitions which create a scope for automatic error handling
+ */
+
+#ifndef __FAPI2_PLAT_ERROR_SCOPE__
+#define __FAPI2_PLAT_ERROR_SCOPE__
+
+/// @cond
+#define PLAT_FAPI_TRY_NO_TRACE( __operation__ )                         \
+    if ((fapi2::current_err = (__operation__)) != fapi2::FAPI2_RC_SUCCESS) \
+    {                                                                   \
+        goto fapi_try_exit;                                             \
+    }
+
+#define PLAT_FAPI_TRY_TRACE( __operation__, ... )                       \
+    if ((fapi2::current_err = (__operation__)) != fapi2::FAPI2_RC_SUCCESS) \
+    {                                                                   \
+        FAPI_ERR(__VA_ARGS__);                                          \
+        goto fapi_try_exit;                                             \
+    }
+
+///
+/// @brief Assert a conditional is true.
+/// If it is not, the FFDC gathering function is called and the
+/// trace is output as a FAPI error trace.
+/// @param[in] __conditional__ the condition to assert
+/// @param[in] __ffdc__ the FFDC gathering function
+/// @param[in] ... varargs, as input to FAPI_ERR
+///
+#define PLAT_FAPI_ASSERT( __conditional__, __ffdc__, ... )      \
+    if (! (__conditional__))                                    \
+    {                                                           \
+        (__ffdc__).execute();                                   \
+        FAPI_ERR(__VA_ARGS__);                                  \
+        goto fapi_try_exit;                                     \
+    }
+
+///
+/// @brief Create an error log based on __conditional__,
+/// the FFDC gathering function is called and the
+/// trace is output as a FAPI error trace. An error log
+/// is created and returned to the caller via the platform
+/// log pointer of the fapi2::current_err return code object
+/// The caller is responsible for handling the error object.
+///
+/// @param[in] __conditional__ the condition to assert
+/// @param[in] __ffdc__ the FFDC gathering function
+/// @param[in] ... varargs, as input to FAPI_ERR
+///
+/// @note: Plat error, if supported, is stored in RC object. Failing
+///        the __conditional__ test does not cause a branch to fapi_try_exit
+///
+///
+#define PLAT_FAPI_ASSERT_NOEXIT( __conditional__, __ffdc__, ... )   \
+    if (! (__conditional__))                                        \
+    {                                                               \
+        __ffdc__.execute(                                           \
+                fapi2::FAPI2_ERRL_SEV_UNDEFINED, true);             \
+        FAPI_ERR(__VA_ARGS__); \
+    }
+/// @endcond
+
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/plat/plat_hw_access.H b/src/import/hwpf/fapi2/include/plat/plat_hw_access.H
new file mode 100644
index 00000000..10f162b4
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/plat/plat_hw_access.H
@@ -0,0 +1,39 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/plat/plat_hw_access.H $             */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+/// @file plat_hw_access.H
+///
+/// @brief Platform hardware-access definitions
+///
+
+#ifndef _FAPI2_PLAT_HWACCESS_H_
+#define _FAPI2_PLAT_HWACCESS_H_
+
+namespace fapi2
+{
+
+}
+
+#endif // _FAPI2_PLAT_HWACCESS_H_
diff --git a/src/import/hwpf/fapi2/include/plat/plat_target.H b/src/import/hwpf/fapi2/include/plat/plat_target.H
new file mode 100644
index 00000000..4712cda5
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/plat/plat_target.H
@@ -0,0 +1,45 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/plat/plat_target.H $                */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file plat_target.H
+ * @brief platform definitions for fapi2 targets
+ */
+
+#ifndef __FAPI2_PLAT_TARGET__
+#define __FAPI2_PLAT_TARGET__
+
+#include <stdint.h>
+
+//
+// Define what a platform handle looks like. For Hostboot,
+// for example, this might be a void*. For the SBE, this
+// will be a uint64_t ...
+//
+namespace fapi2
+{
+typedef uint64_t plat_target_handle_t;
+}
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/plat/plat_trace.H b/src/import/hwpf/fapi2/include/plat/plat_trace.H
new file mode 100644
index 00000000..fbd3aef6
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/plat/plat_trace.H
@@ -0,0 +1,73 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/plat/plat_trace.H $                 */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ *  @file plat_trace.H
+ *  @brief Defines the FAPI2 trace macros.
+ *
+ *  Note that platform code must provide the implementation.
+ *
+ *  FAPI has provided a default implementation. Platform code must
+ *  provide an alternate implementation if needed.
+ */
+
+#ifndef FAPI2_PLATTRACE_H_
+#define FAPI2_PLATTRACE_H_
+
+#include <stdio.h>
+#include <stdint.h>
+
+// Why not a #define, why is this in the fapi2 namespace?
+// To prevent problems with Cronus and the fapi1 definitions.
+namespace fapi2
+{
+static const uint32_t MAX_ECMD_STRING_LEN = 64;
+};
+
+// Information traces (go into fast trace buffer that can wrap often)
+#define FAPI_TRACE(_id_, _fmt_, _args_...)                              \
+    printf("%s: %s:%d ", _id_, __func__, __LINE__);                     \
+    printf(_fmt_, ##_args_);                                            \
+    printf("\n")
+
+#define FAPI_INF(_fmt_, _args_...) FAPI_TRACE("inf", _fmt_, ##_args_)
+
+// Important traces (go into slow trace buffer that should not wrap often)
+#define FAPI_IMP(_fmt_, _args_...) FAPI_TRACE("imp", _fmt_, ##_args_)
+
+// Error traces (go into slow trace buffer that should not wrap often)
+#define FAPI_ERR(_fmt_, _args_...) FAPI_TRACE("err", _fmt_, ##_args_)
+
+// Debug traces (go into fast trace buffer that can wrap often)
+#define FAPI_DBG(_fmt_, _args_...) FAPI_TRACE("dbg", _fmt_, ##_args_)
+
+// Scan traces
+#define FAPI_SCAN(_fmt_, _args_...) FAPI_TRACE("scan", _fmt_, ##_args_)
+
+#define FAPI_MFG(_fmt_, _args_...) FAPI_TRACE("mfg", _fmt_, ##_args_)
+
+#define FAPI_LAB(__fmt_, _args_...) \
+    printf(_fmt_, ##_args_);    \
+    printf("\n")
+#endif // FAPI2_PLATTRACE_H_
diff --git a/src/import/hwpf/fapi2/include/plat/plat_vpd_access.H b/src/import/hwpf/fapi2/include/plat/plat_vpd_access.H
new file mode 100644
index 00000000..5ca078a8
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/plat/plat_vpd_access.H
@@ -0,0 +1,64 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/plat/plat_vpd_access.H $            */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file plat_vpd_access.H
+///
+/// @brief Platform vpd-access definitions
+///
+
+#ifndef _FAPI2_PLAT_VPDACCESS_H_
+#define _FAPI2_PLAT_VPDACCESS_H_
+
+#include <fapi2_vpd_access.H>
+
+namespace fapi2
+{
+// -- platform specific getVPD implementation goes here --
+
+// platform specific for MCS target -- test code only
+inline fapi2::ReturnCode platGetVPD(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+                                    VPDInfo<fapi2::TARGET_TYPE_MCS>& io_vpd_info,
+                                    uint8_t* o_blob)
+{
+    fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS;
+
+    if( o_blob == nullptr )
+    {
+        io_vpd_info.iv_size = 2048;
+    }
+    else
+    {
+        o_blob[0] = 111;
+
+        io_vpd_info.iv_freq_mhz = 10000;
+        io_vpd_info.iv_rank_count_dimm_0 = 1;
+        io_vpd_info.iv_rank_count_dimm_1 = 8;
+
+    }
+
+    return l_rc;
+}
+
+};
+#endif // _FAPI2_PLAT_VPDACCESS_H_
diff --git a/src/import/hwpf/fapi2/include/plat/target.H b/src/import/hwpf/fapi2/include/plat/target.H
new file mode 100644
index 00000000..842d9d1f
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/plat/target.H
@@ -0,0 +1,242 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/plat/target.H $                     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file target.H
+ * @brief platform specializations for fapi2 targets
+ */
+
+#ifndef __FAPI2_TARGET__
+#define __FAPI2_TARGET__
+
+#include <plat_target.H>
+#include <fapi2_target.H>
+#include <multicast.H>
+#include <stdio.h>
+
+namespace fapi2
+{
+
+///
+/// @brief Assignment Operator.
+/// @param[in] i_right Reference to Target to assign from.
+/// @return Reference to 'this' Target
+///
+template<TargetType K, typename V>
+Target<K, V>& Target<K, V>::operator=(const Target& i_right)
+{
+    iv_handle = i_right.iv_handle;
+    return *this;
+}
+
+///
+/// @brief Equality Comparison Operator
+/// @param[in] i_right Reference to Target to compare.
+/// @return bool. True if equal.
+/// @note Platforms need to define this so that the physical
+/// targets are determined to be equivilent rather than just the handles
+///
+template<TargetType K, typename V>
+bool Target<K, V>::operator==(const Target& i_right) const
+{
+    return i_right.iv_handle == iv_handle;
+}
+
+///
+/// @brief Inquality Comparison Operator
+/// @param[in] i_right Reference to Target to compare.
+/// @return bool. True if not equal.
+/// @note Platforms need to define this so that the physical
+/// targets are determined to be equivilent rather than just the handles
+///
+template<TargetType K, typename V>
+bool Target<K, V>::operator!=(const Target& i_right) const
+{
+    return i_right.iv_handle != iv_handle;
+}
+
+///
+/// @brief Less Than Comparison Operator
+/// @param[in] i_right Reference to Target to compare.
+/// @return bool. True if less than i_right.
+/// @note Platforms need to define this so that the physical
+/// targets are determined to be less than rather than just the handles
+///
+template<TargetType K, typename V>
+bool Target<K, V>::operator<(const Target& i_right) const
+{
+    return i_right.iv_handle < iv_handle;
+}
+
+///
+/// @brief Get this target's immediate parent
+/// @tparam T The type of the parent
+/// @return Target<T> a target representing the parent
+///
+template<TargetType K, typename V>
+template<TargetType T>
+inline Target<T, V> Target<K, V>::getParent(void) const
+{
+    // For testing
+    return Target<T, V>(iv_handle);
+}
+
+///
+/// @brief Get this target's children
+/// @tparam T The type of the parent
+/// @param[in] i_state The desired TargetState of the children
+/// @return std::vector<Target<T> > a vector of present/functional
+/// children
+/// @warning The children of EX's (cores) are expected to be returned
+/// in order. That is, core 0 is std::vector[0].
+///
+template<TargetType K, typename V>
+template< TargetType T>
+inline std::vector<Target<T, V> >
+Target<K, V>::getChildren(const TargetState i_state) const
+{
+    // To keep the compiler quiet about unused variables
+    static_cast<void>(i_state);
+    // For testing
+    return {Target<T, V>(), Target<T, V>()};
+}
+// Specialization of getChildren, filtered for pervasive targets.
+template<>
+template<>
+inline std::vector<Target<TARGET_TYPE_PERV> >
+Target<TARGET_TYPE_PERV>::getChildren(const TargetFilter i_filter,
+                                      const TargetState i_state ) const
+{
+    // To keep the compiler quiet about unused variables
+    static_cast<void>(i_state);
+    static_cast<void>(i_filter);
+
+    // For testing
+    return {Target<TARGET_TYPE_PERV>(i_filter), Target<TARGET_TYPE_PERV>(i_filter)};
+}
+
+///
+/// @brief Get the target at the other end of a bus
+/// @tparam T The type of the target on the other end
+/// @param[out] o_target A target representing the thing on the other end
+/// @param[in] i_state The desired TargetState of the other end
+/// @return FAPI2_RC_SUCCESS if OK, platforms will return a non-success
+/// ReturnCode in the event of failure
+/// @note o_target is only valid if return is FAPI2_RC_SUCCESS
+///
+
+template<TargetType K, typename V>
+template<TargetType T>
+inline fapi2::ReturnCodes
+Target<K, V>::getOtherEnd(Target<T, V>& o_target,
+                          const TargetState i_state) const
+{
+    // To keep the compiler quiet about unused variables
+    static_cast<void>(i_state);
+
+    o_target = Target<T, V>();
+
+    return FAPI2_RC_SUCCESS;
+}
+
+///
+/// @brief Is the target functional?
+/// @return true if target is functional, false if non-functional
+///
+
+template<TargetType K, typename V>
+inline bool
+Target<K, V>::isFunctional(void) const
+{
+    // Platform check if target is good
+    // Could check ATTR_FUNCTIONAL or ATTR_PG_*
+    return true;
+}
+
+///
+/// @brief Returns the chiplet number associated with the Target
+/// @return The chiplet number for the Target. 0 is returned if the
+/// Target does not have a chiplet number (for ex, the PROC_CHIP Target)
+/// @note For logical targets such as the EX, the chiplet number of
+/// their immediate parent chiplet is returned
+///
+template<TargetType K, typename V>
+inline uint8_t
+Target<K, V>::getChipletNumber(void) const
+{
+    // Platform can return the chiplet number stored in it's Target handle
+    return 0;
+}
+
+///
+/// @brief Return the string interpretation of this target
+/// @tparam T The type of the target
+/// @param[in] i_target Target<T>
+/// @param[in] i_buffer buffer to write in to
+/// @param[in] i_bsize size of the buffer
+/// @return void
+/// @post The contents of the buffer is replaced with the string
+/// representation of the target
+///
+template< TargetType T, typename V >
+inline void toString(const Target<T, V>& i_target,
+                     char* i_buffer, size_t i_bsize)
+{
+    snprintf(i_buffer, i_bsize, "Target 0x%lx/0x%x", i_target.get(), T);
+}
+
+///
+/// @brief Return the string interpretation of this target
+/// @tparam T The type of the target
+/// @tparam B The type of the buffer
+/// @param[in] i_target A pointer to the Target<T>
+/// @param[in] i_buffer buffer to write in to
+/// @param[in] i_bsize  size of the buffer
+/// @return void
+/// @post The contents of the buffer is replaced with the string
+/// representation of the target
+///
+template< TargetType T, typename V >
+inline void toString(const Target<T, V>* i_target,
+                     char* i_buffer, size_t i_bsize)
+{
+    snprintf(i_buffer, i_bsize, "Target 0x%lx/0x%x", i_target->get(), T);
+}
+
+///
+/// @brief Get an enumerated target of a specific type
+/// @tparam T The type of the target
+/// @param[in] Ordinal representing the ordinal number of
+/// the desired target
+/// @return Target<T> the target requested
+///
+template<TargetType T, typename V>
+inline Target<T, V> getTarget(uint64_t Ordinal)
+{
+    // For testing
+    return Target<T, V>(Ordinal);
+}
+}
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/plat/vpd_access.H b/src/import/hwpf/fapi2/include/plat/vpd_access.H
new file mode 100644
index 00000000..554a3469
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/plat/vpd_access.H
@@ -0,0 +1,52 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/plat/vpd_access.H $                 */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file vpd_access.H
+///
+/// @brief VPD access functions that needs to be specialized for
+/// platform implementation.
+///
+
+#ifndef __VPDACCESS_H_
+#define __VPDACCESS_H_
+
+#include <target.H>
+#include <return_code.H>
+#include <plat_vpd_access.H>
+#include <fapi2_vpd_access.H>
+namespace fapi2
+{
+// -- platform specializations for getVPD go here --
+
+// specialization for MCS target
+template<> fapi2::ReturnCode getVPD(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+                                    VPDInfo<fapi2::TARGET_TYPE_MCS>& io_vpd_info,
+                                    uint8_t* o_blob)
+{
+    return platGetVPD( i_target, io_vpd_info, o_blob );
+}
+
+};
+
+#endif // _FAPI2_VPDACCESS_H_
diff --git a/src/import/hwpf/fapi2/include/return_code.H b/src/import/hwpf/fapi2/include/return_code.H
new file mode 100644
index 00000000..f5569dc2
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/return_code.H
@@ -0,0 +1,187 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/return_code.H $                     */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file return_code.H
+ * @brief definitions for fapi2 return codes
+ */
+
+#ifndef __FAPI2_RETURN_CODE__
+#define __FAPI2_RETURN_CODE__
+
+#include <stdint.h>
+
+#ifndef FAPI2_NO_FFDC
+    #include <ffdc.H>
+#endif
+
+namespace fapi2
+{
+///
+/// @brief Class representing a FAPI2 ReturnCode
+///
+// Remove the inheritance relationship with FirstFailureData if
+// the platform doesn't support FFDC.
+#ifdef FAPI2_NO_FFDC
+class ReturnCode
+#else
+class ReturnCode : public FirstFailureData<ReturnCode>
+#endif
+{
+    public:
+
+        ///
+        /// @brief Constructor.
+        /// @param[in] i_rc the rc to set
+        ///
+        ReturnCode(const uint32_t i_rc = FAPI2_RC_SUCCESS):
+            iv_rc(i_rc)
+        {};
+
+        ///
+        /// @brief integral type conversion function. Returns the error code
+        /// @return The error code
+        ///
+        inline operator uint32_t() const
+        {
+            return iv_rc;
+        }
+
+        ///
+        /// @brief integral type conversion function. Returns the error code
+        /// @return The error code
+        ///
+        inline operator uint64_t() const
+        {
+            return iv_rc;
+        }
+
+        ///
+        /// @brief Returns true iff iv_rc != SUCCESS
+        /// @return true or false
+        ///
+        inline operator bool() const
+        {
+            return iv_rc != FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Assignement operator
+        ///
+#ifdef DOXYGEN
+        inline ReturnCode& operator=(const uint32_t& rhs);
+        inline ReturnCode& operator=(const ReturnCodes& rhs);
+#endif
+
+        inline bool operator==(const uint32_t& rhs) const
+        {
+            return rhs == iv_rc;
+        }
+
+        inline bool operator==(const ReturnCodes& rhs) const
+        {
+            return rhs == iv_rc;
+        }
+
+        inline bool operator!=(const uint32_t& rhs) const
+        {
+            return rhs != iv_rc;
+        }
+
+        inline bool operator!=(const ReturnCodes& rhs) const
+        {
+            return rhs != iv_rc;
+        }
+
+        ///
+        /// @brief Enumeration of return code creators
+        ///
+        enum returnCodeCreator
+        {
+            CREATOR_FAPI = 1,
+            CREATOR_PLAT = 2,
+            CREATOR_HWP = 3,
+        };
+
+        ///
+        /// @brief Gets the creator of the return code
+        /// @return ReturnCodeCreator
+        ///
+        inline returnCodeCreator getCreator(void) const
+        {
+            returnCodeCreator l_creator = CREATOR_HWP;
+
+            if (iv_rc & FAPI2_RC_FAPI2_MASK)
+            {
+                l_creator = CREATOR_FAPI;
+            }
+            else if (iv_rc & FAPI2_RC_PLAT_MASK)
+            {
+                l_creator = CREATOR_PLAT;
+            }
+
+            return l_creator;
+        }
+
+
+        ///
+        /// @brief explicit check for RC value
+        /// @return true if this instance has a matching RC
+        ///
+        inline bool isRC(const ReturnCodes i_rc) const
+        {
+            return static_cast<uint32_t>(i_rc) == iv_rc;
+        }
+
+
+        ///
+        /// @brief explicit check for RC value
+        /// @return true if this instance has a matching RC
+        ///
+        inline bool isRC(const uint32_t i_rc) const
+        {
+            return i_rc == iv_rc;
+        }
+
+
+    private:
+        uint32_t iv_rc;
+};
+
+/// This implementation assumes no exception handling and leverages thread-local
+/// storage. For platforms without thread support, a global variable will
+/// suffice for the error state.
+
+
+extern thread_local uint64_t pib_error_mask;     /// the pib mask
+extern thread_local uint64_t operational_state;  /// the operational mode
+#ifndef PLAT_NO_THREAD_LOCAL_STORAGE
+    extern thread_local ReturnCode current_err;      /// the current error state
+#else
+    extern ReturnCode current_err;
+#endif
+
+}
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/return_code_defs.H b/src/import/hwpf/fapi2/include/return_code_defs.H
new file mode 100644
index 00000000..c7c95f09
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/return_code_defs.H
@@ -0,0 +1,121 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/return_code_defs.H $                */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file return_code.H
+ * @brief definitions for fapi2 return codes
+ */
+
+#ifndef __FAPI2_RETURN_CODE_DEFS_
+#define __FAPI2_RETURN_CODE_DEFS_
+
+#include <stdint.h>
+
+///
+/// @brief Set HWP Error macro
+///
+/// This macro should be used by a HWP to create an error. The ReturnCode's
+/// internal return code is set and any error information in the Error XML file
+/// is added to the ReturnCode
+///
+#define FAPI_SET_HWP_ERROR(RC, ERROR) \
+    RC._setHwpError(fapi2::ERROR); \
+    ERROR##_CALL_FUNCS_TO_COLLECT_FFDC(RC); \
+    ERROR##_CALL_FUNCS_TO_COLLECT_REG_FFDC(RC); \
+    ERROR##_ADD_ERROR_INFO(RC)
+
+///
+/// @brief Add info to HWP Error macro
+///
+/// This macro should be used by an FFDC HWP to add error information from an
+/// Error XML file to an existing error.
+///
+#define FAPI_ADD_INFO_TO_HWP_ERROR(RC, ERROR) \
+    ERROR##_CALL_FUNCS_TO_COLLECT_FFDC(RC); \
+    ERROR##_CALL_FUNCS_TO_COLLECT_REG_FFDC(RC); \
+    ERROR##_ADD_ERROR_INFO(RC)
+
+namespace fapi2
+{
+///
+/// @brief Enumeration of return codes
+///
+enum ReturnCodes : uint32_t
+{
+    ///< Success
+    FAPI2_RC_SUCCESS = 0,
+
+    // Flag bits indicating which code generated the error.
+    FAPI2_RC_FAPI2_MASK = 0x04000000, ///< FAPI2 mask
+    FAPI2_RC_PLAT_MASK =  0x02000000, ///< Platform mask
+    FAPI2_RC_HWP_MASK =   0x00000000, ///< HWP mask
+
+    //
+    // FAPI generated return codes
+    //
+
+    FAPI2_RC_INVALID_ATTR_GET            = FAPI2_RC_FAPI2_MASK | 0x01,
+    ///< Initfile requested an attribute with an invalid attribute ID
+
+    FAPI2_RC_INVALID_CHIP_EC_FEATURE_GET = FAPI2_RC_FAPI2_MASK | 0x02,
+    ///< HWP requested a chip EC feature with an invalid attribute ID
+
+    FAPI2_RC_INVALID_PARAMETER           = FAPI2_RC_FAPI2_MASK | 0x04,
+    ///< Invalid parameters to a FAPI2 function
+
+    FAPI2_RC_OVERFLOW                    = FAPI2_RC_FAPI2_MASK | 0x05,
+    ///< Overflow condition, typically a buffer operation
+
+    FAPI2_RC_FALSE                       = FAPI2_RC_FAPI2_MASK | 0x06,
+    ///< The logical opposite of SUCCESS. Needed where procedures want
+    ///< a multi-bool type of operation (e.g., true, false, scom error)
+
+    //
+    // PLAT generated return codes. Additional details may be contained in
+    // ReturnCode platData (this can only be looked at by PLAT code)
+    //
+
+    FAPI2_RC_PLAT_ERR_SEE_DATA   = FAPI2_RC_PLAT_MASK | 0x01,
+    ///< Generic platform error
+
+    FAPI2_RC_PLAT_ERR_ADU_LOCKED = FAPI2_RC_PLAT_MASK | 0x02,
+    ///< Operation to AlterDisplay unit failed because it is locked
+
+    FAPI2_RC_PLAT_NOT_SUPPORTED_AT_RUNTIME = FAPI2_RC_PLAT_MASK | 0x03,
+    ///< Operation not supported by HB runtime
+
+    FAPI2_RC_PLAT_ERR_RING_HEADER_CHECK = FAPI2_RC_PLAT_MASK | 0x04,
+    //Operation on putring fail because of header data mismatch
+    //
+    FAPI2_RC_PLAT_RING_DECODE_LENGTH_EXCEEDED = FAPI2_RC_PLAT_MASK | 0x05,
+    //Operation on putring fail because of decode length greater than actual
+    //ring length.
+
+    FAPI2_RC_PLAT_RING_ID_NOT_FOUND_IN_RS4_IMAGE = FAPI2_RC_PLAT_MASK | 0x06,
+    //Operation on putring fail because of ringId not found in RS4 image
+};
+
+}
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/target_states.H b/src/import/hwpf/fapi2/include/target_states.H
new file mode 100644
index 00000000..be29cb28
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/target_states.H
@@ -0,0 +1,45 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/target_states.H $                   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file target_states.H
+ * @brief common state for fapi2 targets
+ */
+
+#ifndef __FAPI2_TARGET_STATES__
+#define __FAPI2_TARGET_STATES__
+
+namespace fapi2
+{
+///
+/// @brief Enumeration of target state values (bitmask values)
+///
+enum TargetState
+{
+    TARGET_STATE_PRESENT    = 0x00000001,
+    TARGET_STATE_FUNCTIONAL = 0x00000002,
+};
+}
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/target_types.H b/src/import/hwpf/fapi2/include/target_types.H
new file mode 100644
index 00000000..3e852a1e
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/target_types.H
@@ -0,0 +1,277 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/target_types.H $                    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file target_types.H
+ * @brief definitions for fapi2 target types
+ */
+
+#ifndef __FAPI2_TARGET_TYPES__
+#define __FAPI2_TARGET_TYPES__
+#include <stdint.h>
+
+// File that plat uses to assign values to TargetFilter enum
+#include <plat_target_filter.H>
+
+
+/// FAPI namespace
+namespace fapi2
+{
+///
+/// @enum fapi::TargetType
+/// @brief Types, kinds, of targets
+/// @note TYPE_NONE is used to represent empty/NULL targets in lists
+/// or tables. TYPE_ALL is used to pass targets to methods which
+/// can act generally on any type of target
+///
+
+/// Target Kind
+enum TargetType
+{
+    TARGET_TYPE_NONE          = 0x00000000, ///< No type
+    TARGET_TYPE_SYSTEM        = 0x00000001, ///< System type
+    TARGET_TYPE_DIMM          = 0x00000002, ///< DIMM type
+    TARGET_TYPE_PROC_CHIP     = 0x00000004, ///< Processor type
+    TARGET_TYPE_MEMBUF_CHIP   = 0x00000008, ///< Membuf type
+    TARGET_TYPE_EX            = 0x00000010, ///< EX - 2x Core, L2, L3 - can be deconfigured
+    TARGET_TYPE_MBA           = 0x00000020, ///< MBA type
+    TARGET_TYPE_MCS           = 0x00000040, ///< MCS type
+    TARGET_TYPE_XBUS          = 0x00000080, ///< XBUS type
+    TARGET_TYPE_ABUS          = 0x00000100, ///< ABUS type
+    TARGET_TYPE_L4            = 0x00000200, ///< L4 type
+    TARGET_TYPE_CORE          = 0x00000400, ///< Core - 4x threads(?) - can be deconfigured
+    TARGET_TYPE_EQ            = 0x00000800, ///< EQ - 4x core, 2x L2, 2x L3 - can be deconfigured
+    TARGET_TYPE_MCA           = 0x00001000, ///< MCA type
+    TARGET_TYPE_MCBIST        = 0x00002000, ///< MCBIST type
+    TARGET_TYPE_MI            = 0x00004000, ///< MI Memory Interface (Cumulus)
+    TARGET_TYPE_CAPP          = 0x00008000, ///< CAPP target
+    TARGET_TYPE_DMI           = 0x00010000, ///< DMI type
+    TARGET_TYPE_OBUS          = 0x00020000, ///< OBUS type
+    TARGET_TYPE_NV            = 0x00040000, ///< NV bus type
+    TARGET_TYPE_SBE           = 0x00080000, ///< SBE type
+    TARGET_TYPE_PPE           = 0x00100000, ///< PPE type
+    TARGET_TYPE_PERV          = 0x00200000, ///< Pervasive type
+    TARGET_TYPE_PEC           = 0x00400000, ///< PEC type
+    TARGET_TYPE_PHB           = 0x00800000, ///< PHB type
+
+    TARGET_TYPE_ALL           = 0xFFFFFFFF, ///< Any/All types
+
+    // Compound target types
+    TARGET_TYPE_CHIPS         = TARGET_TYPE_PROC_CHIP |
+                                TARGET_TYPE_MEMBUF_CHIP,
+
+    TARGET_TYPE_CHIPLETS      = TARGET_TYPE_EX     |
+                                TARGET_TYPE_MBA    |
+                                TARGET_TYPE_MCS    |
+                                TARGET_TYPE_XBUS   |
+                                TARGET_TYPE_ABUS   |
+                                TARGET_TYPE_L4     |
+                                TARGET_TYPE_CORE   |
+                                TARGET_TYPE_EQ     |
+                                TARGET_TYPE_MCA    |
+                                TARGET_TYPE_MCBIST |
+                                TARGET_TYPE_MI     |
+                                TARGET_TYPE_DMI    |
+                                TARGET_TYPE_OBUS   |
+                                TARGET_TYPE_NV     |
+                                TARGET_TYPE_SBE    |
+                                TARGET_TYPE_PPE    |
+                                TARGET_TYPE_PERV   |
+                                TARGET_TYPE_PEC    |
+                                TARGET_TYPE_PHB,
+
+    // Mappings to target types found in the error xml files
+    TARGET_TYPE_EX_CHIPLET    = TARGET_TYPE_EX,
+    TARGET_TYPE_MBA_CHIPLET   = TARGET_TYPE_MBA,
+    TARGET_TYPE_MCS_CHIPLET   = TARGET_TYPE_MCS,
+    TARGET_TYPE_XBUS_ENDPOINT = TARGET_TYPE_XBUS,
+    TARGET_TYPE_ABUS_ENDPOINT = TARGET_TYPE_ABUS,
+};
+
+///
+/// @brief Enumeration of chiplet filters
+/// @note plat_target_filter.H assigns enum value using PlatTargetFilter namespace
+///
+
+enum TargetFilter : uint64_t
+{
+    TARGET_FILTER_NONE       = 0x0000000000000000,
+    TARGET_FILTER_TP         = PlatTargetFilter::PLAT_TARGET_FILTER_TP,         // Pervasive 1
+    TARGET_FILTER_NEST_NORTH = PlatTargetFilter::PLAT_TARGET_FILTER_NEST_NORTH, // Pervasive 2
+    TARGET_FILTER_NEST_EAST  = PlatTargetFilter::PLAT_TARGET_FILTER_NEST_EAST,  // Pervasive 3
+    TARGET_FILTER_NEST_SOUTH = PlatTargetFilter::PLAT_TARGET_FILTER_NEST_SOUTH, // Pervasive 4
+    TARGET_FILTER_NEST_WEST  = PlatTargetFilter::PLAT_TARGET_FILTER_NEST_WEST,  // Pervasive 5
+    TARGET_FILTER_XBUS       = PlatTargetFilter::PLAT_TARGET_FILTER_XBUS,       // Pervasive 6
+    TARGET_FILTER_MC_WEST    = PlatTargetFilter::PLAT_TARGET_FILTER_MC_WEST,    // Pervasive 7
+    TARGET_FILTER_MC_EAST    = PlatTargetFilter::PLAT_TARGET_FILTER_MC_EAST,    // Pervasive 8
+    TARGET_FILTER_OBUS0      = PlatTargetFilter::PLAT_TARGET_FILTER_OBUS0,      // Pervasive 9
+    TARGET_FILTER_OBUS1      = PlatTargetFilter::PLAT_TARGET_FILTER_OBUS1,      // Pervasive 10
+    TARGET_FILTER_OBUS2      = PlatTargetFilter::PLAT_TARGET_FILTER_OBUS2,      // Pervasive 11
+    TARGET_FILTER_OBUS3      = PlatTargetFilter::PLAT_TARGET_FILTER_OBUS3,      // Pervasive 12
+    TARGET_FILTER_PCI0       = PlatTargetFilter::PLAT_TARGET_FILTER_PCI0,       // Pervasive 13
+    TARGET_FILTER_PCI1       = PlatTargetFilter::PLAT_TARGET_FILTER_PCI1,       // Pervasive 14
+    TARGET_FILTER_PCI2       = PlatTargetFilter::PLAT_TARGET_FILTER_PCI2,       // Pervasive 15
+    TARGET_FILTER_CACHE0     = PlatTargetFilter::PLAT_TARGET_FILTER_CACHE0,     // Pervasive 16
+    TARGET_FILTER_CACHE1     = PlatTargetFilter::PLAT_TARGET_FILTER_CACHE1,     // Pervasive 17
+    TARGET_FILTER_CACHE2     = PlatTargetFilter::PLAT_TARGET_FILTER_CACHE2,     // Pervasive 18
+    TARGET_FILTER_CACHE3     = PlatTargetFilter::PLAT_TARGET_FILTER_CACHE3,     // Pervasive 19
+    TARGET_FILTER_CACHE4     = PlatTargetFilter::PLAT_TARGET_FILTER_CACHE4,     // Pervasive 20
+    TARGET_FILTER_CACHE5     = PlatTargetFilter::PLAT_TARGET_FILTER_CACHE5,     // Pervasive 21
+    TARGET_FILTER_CORE0      = PlatTargetFilter::PLAT_TARGET_FILTER_CORE0,      // Pervasive 32
+    TARGET_FILTER_CORE1      = PlatTargetFilter::PLAT_TARGET_FILTER_CORE1,      // Pervasive 33
+    TARGET_FILTER_CORE2      = PlatTargetFilter::PLAT_TARGET_FILTER_CORE2,      // Pervasive 34
+    TARGET_FILTER_CORE3      = PlatTargetFilter::PLAT_TARGET_FILTER_CORE3,      // Pervasive 35
+    TARGET_FILTER_CORE4      = PlatTargetFilter::PLAT_TARGET_FILTER_CORE4,      // Pervasive 36
+    TARGET_FILTER_CORE5      = PlatTargetFilter::PLAT_TARGET_FILTER_CORE5,      // Pervasive 37
+    TARGET_FILTER_CORE6      = PlatTargetFilter::PLAT_TARGET_FILTER_CORE6,      // Pervasive 38
+    TARGET_FILTER_CORE7      = PlatTargetFilter::PLAT_TARGET_FILTER_CORE7,      // Pervasive 39
+    TARGET_FILTER_CORE8      = PlatTargetFilter::PLAT_TARGET_FILTER_CORE8,      // Pervasive 20
+    TARGET_FILTER_CORE9      = PlatTargetFilter::PLAT_TARGET_FILTER_CORE9,      // Pervasive 41
+    TARGET_FILTER_CORE10     = PlatTargetFilter::PLAT_TARGET_FILTER_CORE10,     // Pervasive 42
+    TARGET_FILTER_CORE11     = PlatTargetFilter::PLAT_TARGET_FILTER_CORE11,     // Pervasive 43
+    TARGET_FILTER_CORE12     = PlatTargetFilter::PLAT_TARGET_FILTER_CORE12,     // Pervasive 44
+    TARGET_FILTER_CORE13     = PlatTargetFilter::PLAT_TARGET_FILTER_CORE13,     // Pervasive 45
+    TARGET_FILTER_CORE14     = PlatTargetFilter::PLAT_TARGET_FILTER_CORE14,     // Pervasive 46
+    TARGET_FILTER_CORE15     = PlatTargetFilter::PLAT_TARGET_FILTER_CORE15,     // Pervasive 47
+    TARGET_FILTER_CORE16     = PlatTargetFilter::PLAT_TARGET_FILTER_CORE16,     // Pervasive 48
+    TARGET_FILTER_CORE17     = PlatTargetFilter::PLAT_TARGET_FILTER_CORE17,     // Pervasive 49
+    TARGET_FILTER_CORE18     = PlatTargetFilter::PLAT_TARGET_FILTER_CORE18,     // Pervasive 50
+    TARGET_FILTER_CORE19     = PlatTargetFilter::PLAT_TARGET_FILTER_CORE19,     // Pervasive 51
+    TARGET_FILTER_CORE20     = PlatTargetFilter::PLAT_TARGET_FILTER_CORE20,     // Pervasive 52
+    TARGET_FILTER_CORE21     = PlatTargetFilter::PLAT_TARGET_FILTER_CORE21,     // Pervasive 53
+    TARGET_FILTER_CORE22     = PlatTargetFilter::PLAT_TARGET_FILTER_CORE22,     // Pervasive 54
+    TARGET_FILTER_CORE23     = PlatTargetFilter::PLAT_TARGET_FILTER_CORE23,     // Pervasive 55
+
+    // Composite filters follow
+
+    // Pervasive 32-55 (all cores)
+    TARGET_FILTER_ALL_CORES   = (TARGET_FILTER_CORE0 |
+                                 TARGET_FILTER_CORE1 | TARGET_FILTER_CORE2 |
+                                 TARGET_FILTER_CORE3 | TARGET_FILTER_CORE4 |
+                                 TARGET_FILTER_CORE5 | TARGET_FILTER_CORE6 |
+                                 TARGET_FILTER_CORE7 | TARGET_FILTER_CORE8 |
+                                 TARGET_FILTER_CORE9 | TARGET_FILTER_CORE10 |
+                                 TARGET_FILTER_CORE11 | TARGET_FILTER_CORE12 |
+                                 TARGET_FILTER_CORE13 | TARGET_FILTER_CORE14 |
+                                 TARGET_FILTER_CORE15 | TARGET_FILTER_CORE16 |
+                                 TARGET_FILTER_CORE17 | TARGET_FILTER_CORE18 |
+                                 TARGET_FILTER_CORE19 | TARGET_FILTER_CORE20 |
+                                 TARGET_FILTER_CORE21 | TARGET_FILTER_CORE22 |
+                                 TARGET_FILTER_CORE23),
+
+    // Pervasive 16-21 (all caches)
+    TARGET_FILTER_ALL_CACHES  = (TARGET_FILTER_CACHE0 |
+                                 TARGET_FILTER_CACHE1 | TARGET_FILTER_CACHE2 |
+                                 TARGET_FILTER_CACHE3 | TARGET_FILTER_CACHE4 |
+                                 TARGET_FILTER_CACHE5),
+
+    // Pervasive 2-5 (eg N0-N3) < req'd
+    TARGET_FILTER_ALL_NEST    = (TARGET_FILTER_NEST_NORTH |
+                                 TARGET_FILTER_NEST_SOUTH | TARGET_FILTER_NEST_EAST |
+                                 TARGET_FILTER_NEST_WEST),
+
+    // Pervasive 2-4 (eg N0-N2) < req'd
+    TARGET_FILTER_NEST_SLAVES =
+        (TARGET_FILTER_NEST_NORTH | TARGET_FILTER_NEST_SOUTH |
+         TARGET_FILTER_NEST_EAST),
+
+    // Pervasive 5 (eg N32) < req'd
+    TARGET_FILTER_NEST_MASTER = TARGET_FILTER_NEST_WEST,
+
+    // Pervasive 7-8 (eg MC0-MC1)
+    TARGET_FILTER_ALL_MC      =
+        (TARGET_FILTER_MC_WEST | TARGET_FILTER_MC_EAST),
+
+    // Pervasive 9-12 (OB0-OB3)
+    TARGET_FILTER_ALL_OBUS    =
+        (TARGET_FILTER_OBUS0 | TARGET_FILTER_OBUS1 | TARGET_FILTER_OBUS2 |
+         TARGET_FILTER_OBUS3),
+
+    // Pervasive 13-15 (PCI0-PCI2)
+    TARGET_FILTER_ALL_PCI =
+        (TARGET_FILTER_PCI0 | TARGET_FILTER_PCI1 | TARGET_FILTER_PCI2),
+
+    // Sync mode filter = All NEST + All MCS
+    TARGET_FILTER_SYNC_MODE_NEST =
+        (TARGET_FILTER_ALL_NEST | TARGET_FILTER_ALL_MC),
+
+    // All IO Targets except NEST
+    TARGET_FILTER_ALL_IO_EXCEPT_NEST =
+        (TARGET_FILTER_XBUS | TARGET_FILTER_ALL_PCI | TARGET_FILTER_ALL_OBUS),
+
+    // All sync mode IO except NEST
+    TARGET_FILTER_SYNC_MODE_ALL_IO_EXCEPT_NEST =
+        (TARGET_FILTER_ALL_MC | TARGET_FILTER_XBUS | TARGET_FILTER_ALL_PCI |
+         TARGET_FILTER_ALL_OBUS),
+
+    // All sync mode NEST slaves
+    TARGET_FILTER_SYNC_MODE_NEST_SLAVES =
+        (TARGET_FILTER_ALL_MC | TARGET_FILTER_NEST_SLAVES),
+
+    // All sync mode IO
+    TARGET_FILTER_SYNC_MODE_ALL_IO =
+        (TARGET_FILTER_ALL_MC | TARGET_FILTER_ALL_NEST |
+         TARGET_FILTER_ALL_OBUS | TARGET_FILTER_ALL_PCI |
+         TARGET_FILTER_XBUS),
+
+    // All IO
+    TARGET_FILTER_ALL_IO = (TARGET_FILTER_ALL_NEST |
+                            TARGET_FILTER_ALL_OBUS | TARGET_FILTER_ALL_PCI |
+                            TARGET_FILTER_XBUS),
+
+    // All sync mode except TP
+    TARGET_FILTER_SYNC_MODE_ALL_EXCEPT_TP =
+        (TARGET_FILTER_ALL_MC | TARGET_FILTER_ALL_NEST |
+         TARGET_FILTER_ALL_OBUS | TARGET_FILTER_ALL_PCI |
+         TARGET_FILTER_XBUS | TARGET_FILTER_ALL_CORES |
+         TARGET_FILTER_ALL_CACHES),
+};
+
+
+/// @cond
+constexpr TargetType operator|(TargetType x, TargetType y)
+{
+    return static_cast<TargetType>(static_cast<int>(x) |
+                                   static_cast<int>(y));
+}
+
+template<uint64_t V>
+class bitCount
+{
+    public:
+        // Don't use enums, too hard to compare
+        static const uint8_t count = bitCount < (V >> 1) >::count + (V & 1);
+};
+
+template<>
+class bitCount<0>
+{
+    public:
+        static const uint8_t count = 0;
+};
+/// @endcond
+
+}
+
+#endif
diff --git a/src/import/hwpf/fapi2/include/utils.H b/src/import/hwpf/fapi2/include/utils.H
new file mode 100644
index 00000000..e4f5fa09
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/utils.H
@@ -0,0 +1,171 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/utils.H $                           */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file utils.H
+ * @brief Defines common fapi2 utilities
+ */
+
+#ifndef FAPI2_UTILS_H_
+#define FAPI2_UTILS_H_
+
+#include <stdint.h>
+#include <return_code.H>
+#include <target_types.H>
+#include <plat_utils.H>
+
+
+namespace fapi2
+{
+
+///
+/// @brief Enable/Disable special wakeup on processor chip core(s)
+///
+/// Special Wakeup Enable must be done when a HWP is doing an operation that
+/// requires core(s) to be awake (e.g. modifying the Hcode image). For
+/// each Special Wakeup Enable call, there must be a subsequent Special Wakeup
+/// Disable call.
+///
+/// This does not apply to SCOM operations, platforms must handle Special Wakeup
+/// for SCOM operations internally.
+///
+/// If Special Wakeup is enabled, a core will not go to sleep (if already
+/// sleeping, it is woken up). If Special Wakeup is disabled, if there are no
+/// other active Enables, the core is allowed to sleep.
+///
+/// @note Implemented by platform code calling the cpu special wakeup HWP.
+///       This is a FAPI2 function because each platform may do different things
+///         Hostboot: Does nothing (cores cannot sleep while Hostboot running)
+///         FSP: Uses an algorithm to decide when to disable special wakeup
+///         Cronus: Does Special Wakeup enable/disable as requested
+///
+/// @param[in] i_target
+///              TARGET_TYPE_PROC_CHIP: Enables/Disables Special Wakeup on all
+///                cores (EX,EQ chiplets) of the specified chip target.
+///              TARGET_TYPE_CORE: Enables/Disables Special Wakeup on the
+///                specified core target (EX,EQ chiplets)
+///              TARGET_TYPE_EX: Enables/Disables Special Wakeup on the
+///                specified EX target.
+///              TARGET_TYPE_EQ: Enables/Disables Special Wakeup on the
+///                specified EQ target.
+///
+/// @param[in] i_enable true = enable. false = disable.
+///
+/// @return ReturnCode. FAPI2_RC_SUCCESS on success, else platform specified error.
+///
+///
+template<TargetType T, typename V>
+inline ReturnCode specialWakeup(const Target<T, V>& i_target,
+                                const bool i_enable)
+{
+    // enforce the allowed target types
+    static_assert( ((T == fapi2::TARGET_TYPE_PROC_CHIP) ||
+                    (T == fapi2::TARGET_TYPE_CORE)      ||
+                    (T == fapi2::TARGET_TYPE_EX)        ||
+                    (T == fapi2::TARGET_TYPE_EQ)),
+                   "Invalid target type for this function");
+
+    ReturnCode l_rc = platSpecialWakeup( i_target, i_enable );
+
+    return l_rc;
+}
+
+///
+/// @brief Log an error.
+///
+/// @param[in,out] io_rc Reference to ReturnCode (Any references to data and error
+///            target are removed and rc value is set to success after
+///            function ends.)
+/// @param[in] i_sev Fapi error log severity defaulted to unrecoverable
+/// @param[in] i_unitTestError - flag to log error which does not cause a unit
+///                              test to fail.
+///
+/// @note This function is called from the ffdc collection classes and no longer
+/// needs to be called directly.
+/// @note Implemented by platform code
+///
+void logError(
+    fapi2::ReturnCode& io_rc,
+    fapi2::errlSeverity_t i_sev = fapi2::FAPI2_ERRL_SEV_UNRECOVERABLE,
+    bool i_unitTestError = false );
+
+///
+/// @brief Create a platform error log
+///
+///  This function will create a platform error log from the passed in
+///  return code value and will populate the iv_platDataPtr of the return code
+///  with a pointer to the newly created log.
+///
+/// @param[in,out] io_rc - Reference to ReturnCode
+///
+/// @param[in] i_sev Fapi error log severity defaulted to unrecoverable
+//
+//
+/// @note Implemented by platform code
+///
+void createPlatLog(
+    fapi2::ReturnCode& io_rc,
+    fapi2::errlSeverity_t i_sev = fapi2::FAPI2_ERRL_SEV_UNRECOVERABLE
+);
+
+///
+/// @brief Delay this thread. Hostboot will use the nanoseconds parameter
+/// and make a syscall to nanosleep. While in the syscall, the hostboot
+/// kernel will continue to consume CPU cycles as it looks for a runnable
+/// task.  When the delay time expires, the task becomes runnable and will soon
+/// return from the syscall.  Callers of delay() in the hostboot environment
+/// will likely have to know the mHz clock speed they are running on and
+/// compute a non-zero value for i_nanoSeconds.
+///
+/// On the FSP, it was sometimes acceptable to just provide zero for the
+/// sleep delay time, causing the task to yield its time slice. By the
+/// time the calling task could run again, it was pretty certain enough
+/// host cycles had past.  This is probably not acceptable in
+/// the hostboot environment. Callers should calculate and provide a
+/// sleep value in nanoseconds relative to host clock speed.
+///
+/// On FSP when VBU is the target, then the i_simCycles parameter will be
+/// used instead.  The FSP needs to use the simdispatcher client/server
+/// API and issue a command to the awan to advance the simulation the
+/// specified number of cycles.
+///
+/// @param[in] i_nanoSeconds    nanoseconds to sleep
+/// @param[in] i_simCycles      count of Awan cycles to advance
+/// @param[in] i_fixed          Determination, for DFT, if this time is
+///                             fixed or not. Defaults to non-fixed
+///
+/// @return ReturnCode. Zero on success, else platform specified error.
+///
+ReturnCode delay(uint64_t i_nanoSeconds, uint64_t i_simCycles,
+                 bool i_fixed = false);
+
+///
+/// @brief Assert a condition, and halt
+///
+/// @param[in] i_expression a boolean representing the assertion
+///
+void Assert(bool i_expression);
+};
+
+#endif // FAPI2_UTILS_H_
diff --git a/src/import/hwpf/fapi2/include/variable_buffer.H b/src/import/hwpf/fapi2/include/variable_buffer.H
new file mode 100644
index 00000000..e32c69e7
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/variable_buffer.H
@@ -0,0 +1,1291 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/variable_buffer.H $                 */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/**
+ * @file variable_buffer.H
+ * @brief definitions for fapi2 variable length buffers
+ */
+
+#ifndef __FAPI2_VARIABLE_BUFFER__
+#define __FAPI2_VARIABLE_BUFFER__
+
+#include <buffer_parameters.H>
+#include <buffer_traits.H>
+#include <return_code_defs.H>
+#include <plat_trace.H>
+
+namespace fapi2
+{
+
+// forward fapi2::Assert()
+extern void Assert(bool);
+
+
+/// @brief Get a 32 bit mask quickly
+// This is one of the main reasons we static_assert in the ctor's
+// to ensure the unit_type is 32 bits.
+inline uint32_t fast_mask32(int32_t i_pos, int32_t i_len)
+{
+    // generates an arbitrary 32-bit mask using two operations, not too shabby
+
+    static const uint32_t l_mask32[] =
+    {
+        0x00000000,
+        0x80000000, 0xC0000000, 0xE0000000, 0xF0000000,
+        0xF8000000, 0xFC000000, 0xFE000000, 0xFF000000,
+        0xFF800000, 0xFFC00000, 0xFFE00000, 0xFFF00000,
+        0xFFF80000, 0xFFFC0000, 0xFFFE0000, 0xFFFF0000,
+        0xFFFF8000, 0xFFFFC000, 0xFFFFE000, 0xFFFFF000,
+        0xFFFFF800, 0xFFFFFC00, 0xFFFFFE00, 0xFFFFFF00,
+        0xFFFFFF80, 0xFFFFFFC0, 0xFFFFFFE0, 0xFFFFFFF0,
+        0xFFFFFFF8, 0xFFFFFFFC, 0xFFFFFFFE, 0xFFFFFFFF,
+    };
+    return l_mask32[i_len] >> i_pos;
+}
+
+//
+// General set a series of bits in the buffer.
+//
+
+///
+/// @cond
+/// @brief Internal bit inserting method.
+/// @tparam unit_type The type of a unit of the arrays
+/// @tparam bits_type The type of the bit counting values
+/// @param[in] i_source The incoming data
+/// @param[in] i_source_length The length in bits of the incoming data
+/// @param[in] i_target The outgoing data
+/// @param[in] i_target_length The length in bits of the outgoing data
+/// @param[in] i_source_start_bit The starting bit location in the
+///            incoming data
+/// @param[in] i_target_start_bit The starting bit position in this
+/// @param[in] i_length The length, in bits, the user wants copied.
+///
+template<typename unit_type, typename bits_type, typename output_type>
+inline fapi2::ReturnCodes _insert(const unit_type* i_source,
+                                  bits_type i_source_length,
+                                  output_type* i_target,
+                                  bits_type i_target_length,
+                                  bits_type i_source_start_bit,
+                                  bits_type i_target_start_bit,
+                                  bits_type i_length)
+{
+    const bits_type bits_per_input_unit = parameterTraits<unit_type>::bit_length();
+    const bits_type bits_per_output_unit = parameterTraits<output_type>::bit_length();
+
+    // targetStart is defaulted to the sizeof(target) - (sizeof(source) - i_source_start_bit)
+    // which makes this act like insert from right
+    if (i_target_start_bit == static_cast<bits_type>(~0))
+    {
+        i_target_start_bit = (i_target_length - (i_source_length - i_source_start_bit));
+    }
+
+    // len defaults to (sizeof(OT) * 8) - i_source_start_bit
+    if (i_length == static_cast<bits_type>(~0))
+    {
+        i_length = i_source_length - i_source_start_bit;
+    }
+
+    // Check for overflow
+    if ((i_length + i_target_start_bit > i_target_length) ||
+        (i_length + i_source_start_bit > i_source_length))
+    {
+        return fapi2::FAPI2_RC_OVERFLOW;
+    }
+
+    do
+    {
+        const bits_type src_idx = i_source_start_bit / bits_per_input_unit;
+        const bits_type trg_idx = i_target_start_bit / bits_per_output_unit;
+
+        // "slop" = unaligned bits
+        const bits_type src_slop = i_source_start_bit % bits_per_input_unit;
+        const bits_type trg_slop = i_target_start_bit % bits_per_output_unit;
+
+        // "cnt" = largest number of bits to be moved each pass
+        bits_type cnt = std::min(i_length, bits_per_input_unit);
+        cnt = std::min(cnt, bits_per_input_unit - src_slop);
+        cnt = std::min(cnt, bits_per_output_unit - trg_slop);
+
+        // generate the source mask only once
+        bits_type mask = fast_mask32(src_slop, cnt);
+
+        // read the source bits only once
+        bits_type src_bits = i_source[src_idx] & mask;
+
+        // "shift" = amount of shifting needed for target alignment
+        int32_t shift = trg_slop - src_slop;
+
+        if (shift < 0)
+        {
+            src_bits <<= -shift;
+            mask <<= -shift;
+        }
+        else
+        {
+            src_bits >>= shift;
+            mask >>= shift;
+        }
+
+        // clear source '0' bits in the target
+        i_target[trg_idx] &= ~mask;
+
+        // set source '1' bits in the target
+        i_target[trg_idx] |= src_bits;
+
+        i_source_start_bit += cnt;
+        i_target_start_bit += cnt;
+
+        i_length -= cnt;
+
+    }
+    while (0 < i_length);
+
+    return fapi2::FAPI2_RC_SUCCESS;
+}
+/// @endcond
+
+/// @brief Class representing a FAPI variable_buffer.
+/// @remark Variable buffers are buffers which can be variable in length
+/// (and "odd sized.") These best represent the FAPI 1.X ecmdDataBuffer,
+/// however they are implemented using the same template techniques
+/// as the new fapi::buffer.
+/// @note Variable buffers are not (presently) declared as std::bitset
+/// as bitsets' size is fixed at runtime. It is not clear if this is
+/// acceptable for variable_buffers at this time.
+/// @note Variable buffers are implemented as a std::vector of uint32_t
+/// as this keeps simple compatibility with ecmdDataBuffers. Cronus (at
+//  least) needs to interwork the two.
+class variable_buffer
+{
+
+    public:
+
+        /// Shortcut typedef to get to our traits class
+        typedef typename bufferTraits<bits_container>::bits_type bits_type;
+        /// Shortcut typedef to get to our traits class
+        typedef typename bufferTraits<bits_container>::unit_type unit_type;
+
+        ///
+        /// @brief Variable buffer constructor
+        /// @param[in] i_value number of *bits* (sizeof(uint_type) * 8)
+        /// needed.
+        inline variable_buffer(bits_type i_value = 0):
+            iv_data(_vector_size(i_value)),
+            iv_perceived_bit_length(i_value)
+        {
+            static_assert(std::is_same<unit_type, uint32_t>::value,
+                          "code currently needs unit_type to be a unit32_t");
+        }
+#ifndef NO_INITIALIZER_LIST
+        ///
+        /// @brief Variable buffer list constructor
+        /// @param[in] i_value an initializer list to initialize the container.
+        /// @warning Input data is assumed to be right-aligned and must be 32 bits
+        ///
+        inline variable_buffer(const std::initializer_list<unit_type>& i_value):
+            iv_data(i_value),
+            iv_perceived_bit_length(i_value.size() * sizeof(unit_type) * 8)
+        {
+            static_assert(std::is_same<unit_type, uint32_t>::value,
+                          "code currently needs unit_type to be a unit32_t");
+        }
+#endif
+        ///
+        /// @brief Variable buffer copy constructor
+        /// @param[in] i_buffer the buffer to copy from
+        ///
+        inline variable_buffer(const variable_buffer& i_buffer)
+        {
+            iv_perceived_bit_length = i_buffer.iv_perceived_bit_length;
+            iv_data = i_buffer.iv_data;
+        }
+
+        ///
+        /// @brief Variable buffer move constructor
+        /// @param[in] i_buffer the buffer to move
+        ///
+        inline variable_buffer(variable_buffer&& i_buffer)
+        {
+            iv_perceived_bit_length = i_buffer.iv_perceived_bit_length;
+            i_buffer.iv_perceived_bit_length = 0;
+            iv_data = std::move(i_buffer.iv_data);
+        }
+
+        ///
+        /// @brief Variable buffer array constructor
+        /// @param[in] i_value a uint32_t array to initialize the container.
+        /// @param[in] i_length the length of the array in 32-bit words
+        /// @param[in] i_bit_length the length of the resulting buffer in bits.
+        /// @warning This assumes the underlying container of a variable_buffer
+        /// is a uint32_t - which it is.
+        /// @note To use this constructor given an ecmdDataBuffer, you would
+        /// ecmd.memCopyOut( buffer, ... );
+        /// variable_buffer( buffer, ecmd.getCapacity(), ecmd.getBitLength());
+        ///
+        inline variable_buffer(const uint32_t* i_value, const uint32_t i_length,
+                               const uint32_t i_bit_length):
+            iv_perceived_bit_length(i_bit_length)
+        {
+            static_assert(std::is_same<unit_type, uint32_t>::value,
+                          "code currently needs unit_type to be a unit32_t");
+
+            // Copy the array in to our vector.
+            iv_data.insert(iv_data.end(), i_value, &i_value[i_length]);
+        }
+
+
+#if !defined(DOXYGEN) && defined(FAPI2_DEBUG)
+        /// @brief Print the contents of the buffer to stdout
+        inline void print(void) const
+        {
+            bufferTraits<bits_container>::print(iv_data);
+        }
+#endif
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline operator bits_container() const
+        {
+            return iv_data;
+        }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline operator bits_container& ()
+        {
+            return iv_data;
+        }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return The contents of the buffer
+        ///
+        inline bits_container& operator()(void)
+        {
+            return iv_data;
+        }
+
+        ///
+        /// @brief Get the contents of the buffer
+        /// @return Reference to the contents of the buffer
+        ///
+        inline const bits_container& operator()(void) const
+        {
+            return iv_data;
+        }
+
+        /// @name Buffer Manipulation Functions
+        ///@{
+
+        ///
+        /// @brief Set an OT of data in buffer.
+        ///
+        /// It is possible to write the incomplete last OT of a buffer that's not
+        /// an integer multiple of OT's size in bits; in that case, the value will
+        /// be treated left aligned and truncated.
+        ///
+        /// @param[in] i_value sizeof(OT) bits of data
+        /// @param[in] i_offset Start OT (start word, for example) in buffer
+        ///            - defaults to 0 (will by default write the left most element)
+        /// @return FAPI2_RC_SUCCESS on success, FAPI2_RC_OVERFLOW otherwise
+        ///
+        template< typename OT>
+        inline fapi2::ReturnCodes set(OT i_value, const bits_type i_offset = 0)
+        {
+            // Compile time check to make sure OT is integral
+            static_assert( std::is_integral<OT>::value,
+                           "Input must be an integral type" );
+
+            const bits_type bits_in_value = parameterTraits<OT>::bit_length();
+            const bits_type bit_offset = i_offset * bits_in_value;
+
+            if (bit_offset >= iv_perceived_bit_length)
+            {
+                return FAPI2_RC_OVERFLOW;
+            }
+
+            const bits_type available_space = iv_perceived_bit_length - bit_offset;
+
+            return insert<OT>( i_value, (i_offset * bits_in_value), std::min(available_space, bits_in_value), 0);
+
+        }
+
+        ///
+        /// @brief Get an OT of data from buffer
+        ///
+        /// It is possible to read the incomplete last OT of a buffer that's not
+        /// an integer multiple of OT's size in bits; in that case, the return
+        /// value will contain the remaining bits left-aligned.
+        ///
+        /// @tparam OT the type of the data to get
+        /// @param[in] i_offset Start OT (start word, for example) in buffer
+        ///            - defaults to 0 (will by default read the left most element)
+        /// @return OT
+        /// @note uint8_t b = get<uint8_t>(N) <- gets the N'th left byte from the buffer
+        ///
+        template< typename OT>
+        inline OT get(const bits_type i_offset = 0) const;
+
+        /// @name Bit/Word Manipulation Functions
+        ///@{
+
+        ///
+        /// @brief Return the length of the buffer in bits
+        /// @return Length in bits
+        ///
+        inline uint32_t getBitLength(void) const
+        {
+            return iv_perceived_bit_length;
+        }
+
+        ///
+        /// @brief Return the length of the buffer in OT units
+        /// @return Length in OT units rounded up
+        /// @tparam OT the type to get the length of. For example, if one
+        /// wanted the length in double words, OT would be uint64_t
+        /// (getLength<uint64_t>().) Similarly, to get the length in words,
+        /// getLength<uin32_t>().
+        ///
+        template< typename OT >
+        inline uint32_t getLength(void) const
+        {
+            static const uint32_t bits_in_ot = sizeof(OT) * 8;
+            return (getBitLength() + (bits_in_ot - 1)) / bits_in_ot;
+        }
+
+        ///
+        /// @brief  Set a bit in buffer
+        /// @tparam SB Start bit in buffer to clear.
+        /// @tparam L Number of consecutive bits from start bit to
+        /// clear
+        /// @return FAPI2_RC_SUCCESS on success
+        inline fapi2::ReturnCodes setBit( const bits_type SB, bits_type L = 1)
+        {
+
+            ReturnCodes rc;
+            // make sure we stay within our container
+            fapi2::Assert((L > 0) && ((SB + L) <= this->iv_perceived_bit_length) );
+
+            uint32_t mask   = 0;
+
+            // last bit to check
+            bits_type EB    = SB + L - 1;
+
+            // index where first bit to check is located
+            bits_type start_index = SB / bits_per_unit;
+
+            // index where last bit is located
+            bits_type end_index   = EB / bits_per_unit;
+
+            if( start_index == end_index )
+            {
+                // normalize our SB to be within a unit
+                bits_type TempSB = SB - (start_index * bits_per_unit);
+
+                // grab a mask from SB for L number of bits.
+                mask = fast_mask32(TempSB, L);
+
+                iv_data[start_index] |= mask;
+
+                rc = FAPI2_RC_SUCCESS;
+
+            }
+            else
+            {
+                // the bits span more than one internal unit, need to break
+                // it up to process it.
+
+                // make TempSB point to the start of the next unit, adjust the
+                // length and go again, process the bits in the previous index
+                // when we get back.
+                bits_type TempSB = (start_index + 1) * bits_per_unit;
+                bits_type TempL  = EB - TempSB + 1;
+
+                rc = this->setBit( TempSB, TempL );
+
+                if(rc == FAPI2_RC_SUCCESS)
+                {
+                    // now check the bits in the previous index up to the next index.
+                    // normalize our SB to be within a unit
+                    TempSB = SB - (start_index * bits_per_unit);
+
+                    // get a mask for the new SB location to the end of this unit.
+                    mask = fast_mask32(TempSB, L - TempL);
+
+                    // merge theses bits with the others.
+                    iv_data[start_index] |= mask;
+                }
+
+            }
+
+            return rc;
+        }
+
+        ///
+        /// @brief Clear a bit in buffer
+        /// @tparam SB Start bit in buffer to clear.
+        /// @tparam L Number of consecutive bits from start bit to
+        /// clear
+        /// @return FAPI2_RC_SUCCESS on success
+        /// @note Asserting that all the parameters are known at
+        /// compile time so this can be templated only. If that is not
+        /// the case we can add a function parameter version.
+        ///
+        inline fapi2::ReturnCodes clearBit(bits_type SB, bits_type L = 1)
+        {
+            ReturnCodes rc = invert().setBit(SB, L);
+
+            invert();
+
+            return rc;
+        }
+
+        ///
+        /// @brief  invert a bit or range of bits in a buffer
+        /// @tparam SB Start bit in buffer to invert.
+        /// @tparam L Number of consecutive bits from start bit to
+        /// invert, defaults to 1
+        /// @return FAPI2_RC_SUCCESS on success
+        ///
+        inline fapi2::ReturnCodes flipBit( bits_type SB, bits_type L = 1)
+        {
+            ReturnCodes rc;
+
+            // make sure we are within our container
+            if((SB + L) <= this->iv_perceived_bit_length)
+            {
+                // loop for L bits flipping as you go
+                for( bits_type i = 0; i < L; i++)
+                {
+                    bits_type bit = SB + i;
+
+                    if(this->isBitSet(bit))
+                    {
+                        rc = this->clearBit(bit);
+                    }
+                    else
+                    {
+                        rc = this->setBit(bit);
+                    }
+                }
+            }
+            else
+            {
+                rc = FAPI2_RC_OVERFLOW;
+            }
+
+            return rc;
+        }
+
+        ///
+        /// @brief Get the value of a bit in the buffer
+        /// @tparam B Bit in buffer to get.
+        /// @return true/1 if bit is on, false/0 if bit is off
+        /// @note Asserting that all the parameters are known at
+        /// compile time so this can be templated only. If that is not
+        /// the case we can add a function parameter version.
+        ///
+        template< bits_type B >
+        inline bool getBit(void) const
+        {
+            const bits_type index = B / bits_per_unit;
+            const unit_type mask = unit_type(1) <<
+                                   ((bits_per_unit - 1) - (B - (index * bits_per_unit)));
+            return iv_data[index] & mask;
+        }
+
+        ///
+        /// @brief Test if multiple bits are set
+        /// @param SB Start bit in buffer to test.
+        /// @param L Number of consecutive bits from start bit to
+        /// test, defaults to 1
+        /// @return true if all bits in range are set - false if any
+        /// bit is clear
+        /// @note Example: fapi2::buffer<uint64_t>().isBitSet(4,3);
+        inline bool isBitSet( bits_type SB, bits_type L = 1 ) const
+        {
+            // make sure we stay within our container
+            fapi2::Assert( ((L > 0) && ((SB + L) <= this->iv_perceived_bit_length)) );
+
+            bool is_set     = false;
+            uint32_t mask   = 0;
+
+            // last bit to check
+            bits_type EB    = SB + L - 1;
+
+            // index where first bit to check is located
+            bits_type start_index = SB / bits_per_unit;
+
+            // index where last bit is located
+            bits_type end_index   = EB / bits_per_unit;
+
+            if( start_index == end_index )
+            {
+                // normalize our SB to be within a unit
+                bits_type TempSB = SB - (start_index * bits_per_unit);
+
+                // grab a mask from SB for L number of bits.
+                mask = fast_mask32(TempSB, L);
+
+                is_set =
+                    (( iv_data[start_index] & mask) == mask ) ? true : false;
+
+            }
+            else
+            {
+                // the bits span more than one internal unit, need to break
+                // it up to process it.
+
+                // make TempSB point to the start of the next unit, adjust the
+                // length and go again, process the bits in the previous index
+                // when we get back.
+                bits_type TempSB = (start_index + 1) * bits_per_unit;
+                bits_type TempL  = EB - TempSB + 1;
+
+                is_set = this->isBitSet( TempSB, TempL );
+
+                // now check the bits in the previous index up to the next index.
+                // normalize our SB to be within a unit
+                TempSB = SB - (start_index * bits_per_unit);
+
+                // get a mask for the new SB location to the end of this unit.
+                mask = fast_mask32(TempSB, L - TempL);
+
+                // test these bits against the others..
+                is_set &=
+                    (( iv_data[start_index] & mask) == mask ) ? true : false;
+
+            }
+
+            return is_set;
+        }
+
+        ///
+        /// @brief Test if multiple bits are clear
+        /// @param SB Start bit in buffer to test.
+        /// @param L Number of consecutive bits from start bit to
+        /// test, defaults to 1
+        /// @return true if bit is clear - false if bit is set
+        ///
+        inline bool isBitClear( bits_type SB, bits_type L = 1 ) const
+        {
+            variable_buffer l_buf = *this;
+
+            return l_buf.invert().isBitSet(SB, L);
+        }
+
+        ///
+        /// @brief Count number of bits set in a range
+        /// @tparam SB Start bit in buffer to test.
+        /// @tparam L Number of consecutive bits from start bit to
+        /// test, defaults to 1
+        ///
+        inline bits_type getNumBitsSet(bits_type SB, bits_type L = 1) const
+        {
+            bits_type number_of_bits_set = 0;
+
+            for(bits_type i = 0; i < L; i++)
+            {
+                if( this->isBitSet(SB + i) )
+                {
+                    number_of_bits_set++;
+                }
+            }
+
+            return number_of_bits_set;
+        }
+
+        ///
+        /// @brief Set and entire buffer to X's
+        /// @tparam X {0,1} depending if you want to clear (0)
+        /// or fill (1) a buffer
+        /// @return variable_buffer&, Useful for method chaining
+        ///
+        template< uint8_t X >
+        inline variable_buffer& flush(void)
+        {
+            static_assert( (X == 1) || (X == 0), "bad argument to flush" );
+            (0 == X) ? bufferTraits<bits_container>::clear(iv_data) : bufferTraits<bits_container>::set(iv_data);
+            return *this;
+        }
+
+        ///
+        /// @brief Invert entire buffer
+        /// @return variable_buffer&, Useful for method chaining
+        ///
+        inline variable_buffer& invert(void)
+        {
+            bufferTraits<bits_container>::invert(iv_data);
+            return *this;
+        }
+
+        ///@}
+
+        /// @name Buffer Manipulation Functions
+        ///@{
+
+        ///
+        /// @brief Shift a buffer left a defined number of bits, from a start bit
+        /// @param[in] i_shiftNum number of bits to shift
+        /// @param[in] i_offset   offset from 0 to start shift, defaults to ~0 (see operator<<())
+        /// @note an offset of ~(0) implies "end of the buffer"
+        /// @warning there is no shiftLeftandResize - resizing the buffer is left to
+        /// the caller to alight the operations with integral buffers.
+        /// @return FAPI2_RC_SUCCESS on success
+        ///
+        inline ReturnCodes shiftLeft(bits_type i_shiftNum, bits_type i_offset = ~0);
+
+        ///
+        /// @brief Shift a buffer right a defined number of bits, from a start bit
+        /// @param[in] i_shiftNum number of bits to shift
+        /// @param[in] i_offset   offset from 0 to start shift, defaults to 0 (see operator>>())
+        /// @warning there is no shiftRightandResize - resizing the buffer is left to
+        /// the caller to alight the operations with integral buffers.
+        /// @return FAPI2_RC_SUCCESS on success
+        ///
+        inline ReturnCodes shiftRight(bits_type i_shiftNum, bits_type i_offset = 0);
+
+        ///
+        /// @brief move operator=()
+        /// @note To use: new_buffer = std::move(old_buffer). old_buffer will be
+        /// destroyed and no copy will be made (moved)
+        ///
+        inline variable_buffer& operator=(variable_buffer&& other)
+        {
+            iv_perceived_bit_length = other.iv_perceived_bit_length;
+            other.iv_perceived_bit_length = 0;
+            iv_data = std::move(other.iv_data);
+            return *this;
+        }
+
+        ///
+        /// @brief operator=()
+        ///
+        inline variable_buffer& operator=(const variable_buffer& other)
+        {
+            iv_perceived_bit_length = other.iv_perceived_bit_length;
+            iv_data = other.iv_data;
+            return *this;
+        }
+
+        ///
+        /// @brief operator>>()
+        ///
+        inline variable_buffer& operator>>(bits_type i_shiftnum)
+        {
+            // This is just a right shift from the begining of the buffer
+            // Why void? Well, there's no place to return the return
+            // code and in reality the only problem which can arise
+            // is the offset is out of bounds. But since we're hard-wiring it
+            // to 0, it can't be out of bounds. So there's no real problem
+            // which can arise here.
+            static_cast<void>(shiftRight(i_shiftnum));
+            return *this;
+        }
+
+        ///
+        /// @brief operator<<()
+        ///
+        inline variable_buffer& operator<<(bits_type i_shiftnum)
+        {
+            // This is just a left shift from the end of the buffer
+            // Why void? Well, there's no place to return the return
+            // code and in reality the only problem which can arise
+            // is the offset is out of bounds. But since we're hard-wiring it
+            // to 0, it can't be out of bounds. So there's no real problem
+            // which can arise here.
+            static_cast<void>(shiftLeft(i_shiftnum));
+            return *this;
+        }
+
+
+        ///
+        /// @brief operator+()
+        /// @param[in] rhs A variable_buffer to append to this
+        ///
+        inline variable_buffer& operator+(const variable_buffer& rhs)
+        {
+            iv_perceived_bit_length += rhs.iv_perceived_bit_length;
+            iv_data.insert(iv_data.end(), rhs.iv_data.begin(), rhs.iv_data.end());
+            return *this;
+        }
+
+        ///
+        /// @brief operator+()
+        /// @param[in] rhs A number of bits to add to this buffer
+        ///
+        inline variable_buffer& operator+(const bits_type& rhs)
+        {
+            if (rhs != 0)
+            {
+                iv_perceived_bit_length += rhs;
+                iv_data.resize(_vector_size(iv_perceived_bit_length));
+            }
+
+            return *this;
+        }
+
+        ///
+        /// @brief resize()
+        /// @param[in] rhs Desired resulting size of the buffer, in bits
+        ///
+        inline variable_buffer& resize(const bits_type& rhs)
+        {
+            return operator+(rhs - iv_perceived_bit_length);
+        }
+
+        ///
+        /// @brief operator+=()
+        ///
+#ifdef DOXYGEN
+        inline variable_buffer<T>& operator+=(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator|=()
+        ///
+#ifdef DOXYGEN
+        inline variable_buffer<T>& operator|=(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator&=()
+        ///
+#ifdef DOXYGEN
+        inline variable_buffer<T>& operator&=(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator|()
+        ///
+#ifdef DOXYGEN
+        inline variable_buffer<T>& operator|(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator&()
+        ///
+#ifdef DOXYGEN
+        inline variable_buffer<T>& operator&(const T& rhs);
+#endif
+
+        ///
+        /// @brief operator^=()
+        ///
+#ifdef DOXYGEN
+        inline variable_buffer<T>& operator^=(const T& rhs);
+#endif
+
+        ///
+        /// @brief Get a pointer to the buffer bits
+        /// @return Pointer to the buffer itself
+        ///
+        inline unit_type* pointer(void)
+        {
+            return &(iv_data[0]);
+        }
+
+        ///
+        /// @brief operator!=()
+        ///
+        inline bool operator!=(const variable_buffer& rhs) const
+        {
+            return ! operator==(rhs);
+        }
+
+        ///
+        /// @brief operator==()
+        /// @return true if and only if lhs == rhs
+        ///
+        inline bool operator==(const variable_buffer& rhs) const
+        {
+            if (&iv_data == &rhs.iv_data)
+            {
+                return true;
+            }
+
+            return (iv_data == rhs.iv_data) &&
+                   (iv_perceived_bit_length == rhs.iv_perceived_bit_length);
+        }
+
+        ///
+        /// @brief Copy part of an element into the DataBuffer
+        /// @param[in] i_data OT value to copy into DataBuffer
+        /// @param[in] i_targetStart The position in this where the copy starts
+        /// @param[in] i_len How many bits to copy
+        /// @param[in] i_sourceStart The start positon in i_data, defaults to 0
+        /// @return FAPI2_RC_SUCCESS on success, FAPI2_RC_OVERFLOW otherwise
+        ///
+        template<typename OT>
+        inline fapi2::ReturnCodes insert(const OT& i_data,
+                                         bits_type i_targetStart = 0,
+                                         bits_type i_len = ~0,
+                                         bits_type i_sourceStart = 0)
+        {
+            // Compile time check to make sure OT is integral
+            static_assert( std::is_integral<OT>::value,
+                           "Input must be an integral type" );
+
+            // _insert likes 32-bit sources. So lets make our source 32 bits.
+            uint32_t l_source = static_cast<uint32_t>(i_data);
+            bits_type l_sourceStart = i_sourceStart +
+                                      parameterTraits<uint32_t>::bit_length() -
+                                      parameterTraits<OT>::bit_length();
+
+            return _insert(&l_source, parameterTraits<uint32_t>::bit_length(),
+                           &(iv_data[0]), getBitLength(),
+                           l_sourceStart, i_targetStart, i_len);
+        }
+
+        ///
+        /// @brief Copy in a right aligned (decimal) element
+        /// @param[in] i_data the incoming data
+        ///    - data is taken right aligned
+        /// @param[in] i_targetStart The starting bit position in this
+        ///            - Defaults to 0
+        /// @param[in] i_len The length, in bits, the user wants copied.
+        ///            - Defaults to all of the bits in the source which fit
+        /// @return FAPI2_RC_SUCCESS on success, FAPI2_RC_OVERFLOW otherwise
+        ///
+        template<typename OT>
+        inline fapi2::ReturnCodes insertFromRight(const OT& i_data,
+                bits_type i_targetStart = 0,
+                bits_type i_len = ~0)
+        {
+            return _insertFromRight(i_data, parameterTraits<OT>::bit_length(),
+                                    i_targetStart, i_len);
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT
+        /// @tparam OT the type of the outgoing data
+        /// @param[out] o_out OT to copy into - data is placed left aligned
+        /// @param[in] i_start Start bit to copy from - defaults to 0
+        /// @param[in] i_len Length of bits to copy - defaults to filling o_out
+        /// @return FAPI2_RC_SUCCESS on success
+        /// @warning fapi2::extract() does not extend the argument buffer. The caller
+        /// should adjust the size proir to calling extract() (resize()). This is to
+        /// keep the semantics the same with integral buffers, which can't be resized.
+        ///
+        // Generic extract. Extract is an insert with the arguments reversed.
+        template< typename OT >
+        inline fapi2::ReturnCodes extract(OT& o_out,
+                                          bits_type i_start = 0,
+                                          bits_type i_len = ~0) const
+        {
+            // If they didn't pass an i_len, assume they want all the data
+            // which will fit.
+            if (i_len == static_cast<bits_type>(~0))
+            {
+                i_len = std::min(getBitLength(),
+                                 parameterTraits<OT>::bit_length());
+            }
+
+            if (i_len > getBitLength())
+            {
+                return FAPI2_RC_INVALID_PARAMETER;
+            }
+
+            // _insert likes 32-bit targets. So lets make our target 32 bits.
+            uint32_t l_data = static_cast<uint32_t>(o_out);
+
+            ReturnCodes rc;
+
+            if ((rc = _insert((container_unit*)&iv_data[0], getBitLength(),
+                              &l_data,
+                              parameterTraits<uint32_t>::bit_length(),
+                              i_start, 0U, i_len)) != FAPI2_RC_SUCCESS)
+            {
+                return rc;
+            }
+
+            // Shift back to the original bit width.
+            o_out = l_data >> (parameterTraits<uint32_t>::bit_length() -
+                               parameterTraits<OT>::bit_length());
+            return FAPI2_RC_SUCCESS;
+        }
+
+        ///
+        /// @brief Copy data from this buffer into an OT and right justify
+        /// @tparam OT the type of the outgoing data
+        /// @param[out] o_out OT to copy into - data is placed right aligned
+        /// @param[in] i_start Start bit to copy from - defaults to 0
+        /// @param[in] i_len Length of bits to copy - defaults to filling o_out
+        /// @return FAPI2_RC_SUCCESS on success
+        ///
+        // Extract is an insert with the arguments reversed.
+        template< typename OT >
+        inline fapi2::ReturnCodes extractToRight(OT& o_out,
+                bits_type i_start = 0,
+                bits_type i_len = ~0) const
+        {
+            // If thy didn't pass an i_len, assume they want all the data
+            // which will fit.
+            if ((i_len == static_cast<bits_type>(~0)) ||
+                (i_len > parameterTraits<OT>::bit_length()))
+            {
+                i_len = std::min(getBitLength(),
+                                 parameterTraits<OT>::bit_length());
+            }
+
+            // _insert likes 32-bit targets. So lets make our target 32 bits.
+            uint32_t l_data = static_cast<uint32_t>(o_out);
+
+            ReturnCodes rc;
+
+            if ((rc = _insert(
+                          reinterpret_cast<const container_unit*>(&iv_data[0]),
+                          getBitLength(),
+                          &l_data,
+                          parameterTraits<uint32_t>::bit_length(),
+                          i_start,
+                          parameterTraits<uint32_t>::bit_length() -
+                          i_len, i_len)) != FAPI2_RC_SUCCESS)
+            {
+                return rc;
+            }
+
+            o_out = l_data;
+            return FAPI2_RC_SUCCESS;
+        }
+
+        ///@}
+
+    private:
+        // Just shorthand ...
+        static const bits_type bits_per_unit = bufferTraits<bits_container>::bits_per_unit();
+
+        ///@cond
+        ///
+        /// @brief Return the size of the internal vector given a desired bit size
+        /// @param[in] The size in bits
+        /// @return The size in units.
+        ///
+        inline bits_type _vector_size(const bits_type& bits_size)
+        {
+            // If we fit in one unit, we allocate one unit.
+            if (bits_size < parameterTraits<unit_type>::bit_length())
+            {
+                return 1;
+            }
+
+            // Otherwise, the number of units is calculates - add one if
+            // we cross the unit boundary.
+            else
+            {
+                bits_type my_size = bits_type(bits_size / 8 / sizeof(unit_type));
+                my_size += (bits_size % parameterTraits<unit_type>::bit_length() == 0) ? 0 : 1;
+                return my_size;
+            }
+        }
+        ///@endcond
+
+        /// The contents of the buffer
+        bits_container iv_data;
+
+        // The number of bits the user asked for. The actual size of the
+        // container might be larger.
+        bits_type iv_perceived_bit_length;
+
+        ///
+        /// @brief Internal insertFromRight
+        /// @param[in] i_data, the incoming data
+        /// @param[in] i_data_length The length in bits of the incoming data
+        /// @param[in] i_target_start_bit The starting bit position in this
+        /// @param[in] i_length The length, in bits, the user wants copied.
+        ///
+        template<typename OT>
+        inline fapi2::ReturnCodes _insertFromRight(const OT& i_data,
+                bits_type i_data_length,
+                bits_type i_targetStart,
+                bits_type i_len)
+        {
+            // If they didn't pass in a length, assume they want all the i_data
+            // which will fit.
+            if( i_len == static_cast<bits_type>(~0) )
+            {
+                // The longest the length can be is the length of the data
+                // This is the miniumum of the length of the data or the
+                // number of available bits
+                i_len = std::min(i_data_length, getBitLength() - i_targetStart);
+            }
+
+            // Source start is the length, counted from the right
+            return insert(i_data, i_targetStart, i_len, i_data_length - i_len);
+        }
+
+};
+
+// If the source is 64-bits, treat that as 2x32
+template<>
+inline fapi2::ReturnCodes variable_buffer::insert(const uint64_t& i_source,
+        bits_type i_targetStart,
+        bits_type i_len,
+        bits_type i_sourceStart)
+{
+    // _insert wants 32 bit chunks, so lets turn our uint64_t into a
+    // uint32_t array (of 64 bits in length). Looks like a 64 bit
+    // variable_buffer.
+    uint32_t l_source[2] =
+    {
+        static_cast<uint32_t>((i_source & 0xFFFFFFFF00000000) >> 32),
+        static_cast<uint32_t>((i_source & 0x00000000FFFFFFFF))
+    };
+
+    return _insert(l_source, parameterTraits<uint64_t>::bit_length(),
+                   &(iv_data[0]), getBitLength(),
+                   i_sourceStart, i_targetStart, i_len);
+}
+
+// Insert another variable_buffer
+template<>
+inline fapi2::ReturnCodes variable_buffer::insert(
+    const variable_buffer& i_data,
+    bits_type i_targetStart,
+    bits_type i_len,
+    bits_type i_sourceStart)
+{
+    return _insert(reinterpret_cast<const unit_type*>(&(i_data()[0])),
+                   i_data.getBitLength(),
+                   &(iv_data[0]), getBitLength(),
+                   i_sourceStart, i_targetStart, i_len);
+}
+
+// variable_buffer insert from right
+template<>
+inline fapi2::ReturnCodes variable_buffer::insertFromRight(
+    const variable_buffer& i_data,
+    bits_type i_targetStart,
+    bits_type i_len)
+{
+    const bits_type bit_length_of_source = i_data.getBitLength();
+    return _insertFromRight(i_data, bit_length_of_source,
+                            i_targetStart, i_len);
+}
+
+template<>
+inline fapi2::ReturnCodes variable_buffer::extract(
+    uint64_t& i_data,
+    bits_type i_start,
+    bits_type i_len) const
+{
+    // If thy didn't pass an i_len, assume they want all the data
+    // which will fit.
+    if ((i_len == static_cast<bits_type>(~0)) ||
+        (i_len > parameterTraits<uint64_t>::bit_length()))
+    {
+        i_len = std::min(getBitLength(),
+                         parameterTraits<uint64_t>::bit_length());
+    }
+
+    // _insert wants 32 bit chunks, so lets turn our uint64_t into a
+    // uint32_t array (of 64 bits in length). Looks like a 64 bit
+    // variable_buffer.
+    uint32_t l_data[2] =
+    {
+        static_cast<uint32_t>((i_data & 0xFFFFFFFF00000000) >> 32),
+        static_cast<uint32_t>((i_data & 0x00000000FFFFFFFF))
+    };
+
+    ReturnCodes rc;
+
+    if ((rc = _insert((container_unit*)&iv_data[0], getBitLength(),
+                      l_data, parameterTraits<uint64_t>::bit_length(),
+                      i_start, 0U, i_len)) != FAPI2_RC_SUCCESS)
+    {
+        return rc;
+    }
+
+    i_data = static_cast<uint64_t>(l_data[0]) << 32;
+    i_data |= l_data[1];
+
+    return FAPI2_RC_SUCCESS;
+}
+
+// Extract in to another variable_bufer
+template<>
+inline fapi2::ReturnCodes variable_buffer::extract(
+    variable_buffer& i_data,
+    bits_type i_start,
+    bits_type i_len) const
+{
+    // If thy didn't pass an i_len, assume they want all the data
+    // which will fit.
+    if (i_len == static_cast<bits_type>(~0))
+    {
+        i_len = i_data.getBitLength();
+    }
+
+    return _insert(reinterpret_cast<const container_unit*>(
+                       &iv_data[0]),
+                   getBitLength(),
+                   &(i_data()[0]), i_data.getBitLength(),
+                   i_start, 0U, i_len);
+}
+
+template<>
+inline fapi2::ReturnCodes variable_buffer::extractToRight(
+    uint64_t& i_data,
+    bits_type i_start,
+    bits_type i_len) const
+{
+    // If thy didn't pass an i_len, assume they want all the data
+    // which will fit.
+    if ((i_len == static_cast<bits_type>(~0)) ||
+        (i_len > parameterTraits<uint64_t>::bit_length()))
+    {
+        i_len = std::min(getBitLength(),
+                         parameterTraits<uint64_t>::bit_length());
+    }
+
+    // _insert wants 32 bit chunks, so lets turn our uint64_t into a
+    // uint32_t array (of 64 bits in length).
+    uint32_t l_data[2] =
+    {
+        static_cast<uint32_t>((i_data & 0xFFFFFFFF00000000) >> 32),
+        static_cast<uint32_t>((i_data & 0x00000000FFFFFFFF))
+    };
+
+    ReturnCodes rc;
+
+    if ((rc = _insert(
+                  reinterpret_cast<const container_unit*>(&iv_data[0]),
+                  getBitLength(),
+                  l_data, parameterTraits<uint64_t>::bit_length(),
+                  i_start,
+                  parameterTraits<uint64_t>::bit_length() - i_len, i_len))
+        != FAPI2_RC_SUCCESS)
+    {
+        return rc;
+    }
+
+    i_data = static_cast<uint64_t>(l_data[0]) << 32;
+    i_data |= l_data[1];
+
+    return FAPI2_RC_SUCCESS;
+}
+
+inline fapi2::ReturnCodes variable_buffer::shiftLeft(
+    bits_type i_shiftNum,
+    bits_type i_offset)
+{
+    if (i_offset == 0)
+    {
+        return FAPI2_RC_SUCCESS;
+    }
+
+    if (i_offset == static_cast<bits_type>(~0))
+    {
+        i_offset = getBitLength();
+    }
+
+    else if (i_offset > getBitLength())
+    {
+        return FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    /* To shift the data, extact the piece being shifted and then re-insert it at the new location */
+    variable_buffer shiftData(i_offset);
+    ReturnCodes rc;
+
+    // Get the hunk of data
+    if ((rc = extract(shiftData, 0, i_offset)) != FAPI2_RC_SUCCESS)
+    {
+        return rc;
+    }
+
+    // Clear the hole that was opened
+    if ((rc = clearBit((i_offset - i_shiftNum), i_shiftNum)) != FAPI2_RC_SUCCESS)
+    {
+        return rc;
+    }
+
+    // Stick the data back in
+    rc = insert(shiftData, 0, (shiftData.getBitLength() - i_shiftNum), i_shiftNum);
+
+    return rc;
+}
+
+inline fapi2::ReturnCodes variable_buffer::shiftRight(
+    bits_type i_shiftNum,
+    bits_type i_offset)
+{
+    if (i_offset == getBitLength())
+    {
+        return FAPI2_RC_SUCCESS;
+    }
+
+    if (i_offset > getBitLength())
+    {
+        return FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    /* To shift the data, extact the piece being shifted and then re-insert it at the new location */
+    variable_buffer shiftData(getBitLength() - i_offset);
+    ReturnCodes rc;
+
+    // Get the hunk of data
+    if ((rc = extract(shiftData, i_offset, getBitLength() - i_offset)) != FAPI2_RC_SUCCESS)
+    {
+        return rc;
+    }
+
+    // Clear the hole that was opened
+    if ((rc = clearBit(i_offset, i_shiftNum)) != FAPI2_RC_SUCCESS)
+    {
+        return rc;
+    }
+
+    // Stick the data back in
+    rc = insert(shiftData, (i_offset + i_shiftNum), (shiftData.getBitLength() - i_shiftNum));
+
+    return rc;
+}
+
+template< typename OT>
+inline OT variable_buffer::get(const bits_type i_offset) const
+{
+    const bits_type bits_in_value = parameterTraits<OT>::bit_length();
+    const bits_type bit_offset = i_offset * bits_in_value;
+
+    if (bit_offset >= iv_perceived_bit_length)
+    {
+        FAPI_ERR("Overrun in variable_buffer::get<OT>() - bits_in_value=%d bit_offset=%d iv_perceived_bit_length=%d",
+                 bits_in_value, bit_offset, iv_perceived_bit_length);
+        fapi2::Assert(false);
+    }
+
+    // Get is just an extract.
+    OT l_tmp = OT(0);
+    const bits_type available_space = iv_perceived_bit_length - bit_offset;
+    extract(l_tmp, bit_offset, std::min(available_space, bits_in_value));
+    return l_tmp;
+}
+}
+#endif
diff --git a/src/import/hwpf/fapi2/include/variable_buffer_utils.H b/src/import/hwpf/fapi2/include/variable_buffer_utils.H
new file mode 100644
index 00000000..b1ae4664
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/variable_buffer_utils.H
@@ -0,0 +1,149 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/variable_buffer_utils.H $           */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2016                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef __FAPI2_VARIABLE_BUFFER_UTILS__
+#define __FAPI2_VARIABLE_BUFFER_UTILS__
+
+#include <inttypes.h>
+
+#include <ecmdDataBufferBase.H>
+#include <ecmdUtils.H>
+
+#include <variable_buffer.H>
+#include <return_code_defs.H>
+#include <plat_trace.H>
+
+namespace fapi2
+{
+/** @name Variable buffer utility functions for platforms that support eCMD **/
+//@{
+
+/**
+ * @brief Copies contents of fapi2::variable_buffer to a ecmdDataBufferBase
+ * @param[in] i_src fapi::variable_buffer to copy from
+ * @param[out] o_dest ecmdDataBufferBase to copy to
+ * @return uint32_t return code zero if success
+ */
+inline uint32_t bufferCopy(ecmdDataBufferBase& o_dest, const fapi2::variable_buffer& i_src)
+{
+    uint32_t rc = 0;
+    uint32_t l_ecmdRc = 0;
+    uint32_t l_bitLength = i_src.getBitLength();
+    const uint32_t l_bitsPerWord = sizeof(uint32_t) * 8;
+    uint32_t l_wordLength = l_bitLength / l_bitsPerWord;
+    uint32_t l_currentWord = 0;
+    uint32_t l_extractData = 0;
+    fapi2::ReturnCodes l_copy_rc = fapi2::FAPI2_RC_SUCCESS;
+
+    l_ecmdRc = o_dest.setBitLength(l_bitLength);
+
+    if (l_ecmdRc)
+    {
+        FAPI_ERR("Error calling o_dest.setBitLength(%d) rc = 0x%08X\n",
+                 l_bitLength, l_ecmdRc);
+        rc = l_ecmdRc;
+    }
+
+    while ((l_currentWord < l_wordLength) && (rc == 0))
+    {
+        l_copy_rc = i_src.extract(l_extractData, l_currentWord * l_bitsPerWord, l_bitsPerWord);
+
+        if (l_copy_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("Error calling i_src.extract(l_extractData, %d, %d) rc = 0x" UINT64_HEX16_FORMAT "\n",
+                     l_currentWord * l_bitsPerWord, l_bitsPerWord, static_cast<uint64_t>(l_copy_rc));
+            rc = static_cast<uint64_t>(l_copy_rc);
+            break;
+        }
+
+        l_ecmdRc = o_dest.insert(l_extractData, l_currentWord * l_bitsPerWord, l_bitsPerWord, 0);
+
+        if (l_ecmdRc)
+        {
+            FAPI_ERR("Error calling o_dest.insert(%08X, %d, %d, 0) rc = 0x%08X\n",
+                     l_extractData, l_currentWord * l_bitsPerWord, l_bitsPerWord, l_ecmdRc);
+            rc = l_ecmdRc;
+            break;
+        }
+
+        l_currentWord++;
+    }
+
+    if ((l_bitLength > (l_wordLength * l_bitsPerWord)) && (rc == 0))
+    {
+        uint32_t l_bitsRemaining = l_bitLength - (l_wordLength * l_bitsPerWord);
+        l_copy_rc = i_src.extract(l_extractData, l_wordLength * l_bitsPerWord, l_bitsRemaining);
+
+        if (l_copy_rc != fapi2::FAPI2_RC_SUCCESS)
+        {
+            FAPI_ERR("error calling i_src.extract(l_extractData, %d, %d) rc = 0x" UINT64_HEX16_FORMAT "\n",
+                     l_wordLength * l_bitsPerWord, l_bitsRemaining, static_cast<uint64_t>(l_copy_rc));
+            rc = static_cast<uint64_t>(l_copy_rc);
+        }
+        else
+        {
+            l_ecmdRc = o_dest.insert(l_extractData, l_wordLength * l_bitsPerWord, l_bitsRemaining, 0);
+
+            if (l_ecmdRc)
+            {
+                FAPI_ERR("Error calling o_dest.insert(%08X, %d, %d, 0) rc = 0x%08X\n",
+                         l_extractData, l_wordLength * l_bitsPerWord, l_bitsRemaining, l_ecmdRc);
+                rc = l_ecmdRc;
+            }
+        }
+    }
+
+    return rc;
+}
+
+/**
+ * @brief Copies contents of ecmdDataBufferBase to a fapi2::variable_buffer
+ * @param[in] i_src ecmdDataBufferBase to copy from
+ * @param[out] o_dest fapi::variable_buffer to copy to
+ * @return uint32_t return code zero if success
+ */
+inline uint32_t bufferCopy(fapi2::variable_buffer& o_dest, ecmdDataBufferBase& i_src)
+{
+    uint32_t rc = 0;
+    uint32_t* l_data = ecmdDataBufferBaseImplementationHelper::getDataPtr(&i_src);
+
+    if (l_data != NULL)
+    {
+        o_dest = fapi2::variable_buffer(l_data, i_src.getCapacity(), i_src.getBitLength());
+    }
+    else
+    {
+        FAPI_ERR("Error getting data pointer to ecmdDataBufferBase\n");
+        rc = 1;
+    }
+
+    return rc;
+}
+
+//@}
+
+} // namespace fapi2
+
+#endif /* __FAPI2_VARIABLE_BUFFER_UTILS__ */
diff --git a/src/import/hwpf/fapi2/include/vpd_access_defs.H b/src/import/hwpf/fapi2/include/vpd_access_defs.H
new file mode 100644
index 00000000..57d51e13
--- /dev/null
+++ b/src/import/hwpf/fapi2/include/vpd_access_defs.H
@@ -0,0 +1,58 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/hwpf/fapi2/include/vpd_access_defs.H $                 */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file vpd_access_defs.H
+///
+/// @brief VPD access definitions
+///
+
+#ifndef __VPDACCESSDEFS_H_
+#define __VPDACCESSDEFS_H_
+
+#include <stdint.h>
+
+namespace fapi2
+{
+
+// @brief VPD accesss enums
+enum MemVpdData
+{
+    MR, //! Memory phase rotator
+    MT, //! Memory Termination
+    MP, //! Memory Power related info
+};
+
+typedef MemVpdData MemVpdData_t;
+
+/// @brief  Class representing required VPDInfo to be used in vpd collection.
+/// @tparam T, the type of target this class is used with.
+///
+///  NOTE: to be defined by implementor
+//
+template<fapi2::TargetType T>
+class VPDInfo;
+
+}
+#endif
diff --git a/src/import/hwpf/fapi2/tools/parseErrorInfo.pl b/src/import/hwpf/fapi2/tools/parseErrorInfo.pl
new file mode 100755
index 00000000..8a431d1b
--- /dev/null
+++ b/src/import/hwpf/fapi2/tools/parseErrorInfo.pl
@@ -0,0 +1,1596 @@
+#!/usr/bin/perl
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: import/hwpf/fapi2/tools/parseErrorInfo.pl $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+#
+# @file   parseErrorInfo.pl
+# @brief  This perl script will parse HWP Error XML files and generate required
+#         FAPI code to create and error log and add FFDC to the error.
+#
+# *HWP HWP Owner: N/A
+# *HWP FW Owner: Thi Tran <thi@us.ibm.com>
+# *HWP Team: N/A
+# *HWP Level: 1
+# *HWP Consumed by: HB
+#
+# Usage:
+# parseErrorInfo.pl <output dir> <filename1> <filename2> ...
+
+use strict;
+
+#------------------------------------------------------------------------------
+# Set PREFERRED_PARSER to XML::Parser. Otherwise it uses XML::SAX which contains
+# bugs that result in XML parse errors that can be fixed by adjusting white-
+# space (i.e. parse errors that do not make sense).
+#------------------------------------------------------------------------------
+$XML::Simple::PREFERRED_PARSER = 'XML::Parser';
+
+#------------------------------------------------------------------------------
+# Specify perl modules to use
+#------------------------------------------------------------------------------
+use Digest::MD5 qw(md5_hex);
+use XML::Simple;
+my $xml = new XML::Simple (KeyAttr=>[]);
+
+# Uncomment to enable debug output
+use Data::Dumper;
+use Getopt::Long;
+
+
+my @eiObjects = ();
+my $target_ffdc_type = "fapi2::Target<T>";
+my $buffer_ffdc_type = "fapi2::buffer";
+my $variable_buffer_ffdc_type = "fapi2::variable_buffer";
+my $ffdc_type = "fapi2::ffdc_t";
+my $mcast_type = "fapi2::mcast_t";
+
+# We want to keep the signatures for the ffdc gathering hwp so that
+# we can create members of the proper types for the ffdc classes.
+my %signatures = ("proc_extract_pore_halt_ffdc" => ["por_base_state",
+                                                    "por_halt_type_t",
+                                                    "por_ffdc_offset_t"],
+                  "proc_example" => ["uint32_t","uint8_t"],
+                  "proc_extract_pore_base_ffdc" => ["por_base_state", "por_sbe_base_state"],
+                  "proc_tp_collect_dbg_data" => [$target_ffdc_type],
+                  "p9_collect_some_ffdc" => ["uint32_t","uint8_t"],
+    );
+
+# There are some names used in the XML files which exist in either
+# c++ keywords (case, for example) or macros (DOMAIN). The one's which
+# cause problems and need to be changed are here.
+#
+# DOMAIN is defined to 1 in math.h
+my %mangle_names = ("DOMAIN" => "FAPI2_DOMAIN");
+
+# A list of deprecated elements. These will report messages to the
+# user, and not define anything. They have not been found to be used,
+# but that doesn't mean they're not ...
+my %deprecated = ("RC_PROCPM_PMCINIT_TIMEOUT" => "CHIP_IN_ERROR is defined as a callout procedure");
+
+#------------------------------------------------------------------------------
+# Print Command Line Help
+#------------------------------------------------------------------------------
+my $arg_empty_ffdc = undef;
+my $arg_local_ffdc = undef;
+my $arg_output_dir = undef;
+my $arg_use_variable_buffers = undef;
+
+# Get the options from the command line - the rest of @ARGV will
+# be filenames
+GetOptions("empty-ffdc-classes" => \$arg_empty_ffdc,
+           "local-ffdc" => \$arg_local_ffdc,
+           "output-dir=s" => \$arg_output_dir,
+           "use-variable-buffers" => \$arg_use_variable_buffers);
+
+my $numArgs = $#ARGV + 1;
+if (($numArgs < 1) || ($arg_output_dir eq undef))
+{
+    print ("Usage: parseErrorInfo.pl [--empty-ffdc-classes] [--use-variable-buffers] --output-dir=<output dir> <filename1> <filename2> ...\n");
+    print ("  This perl script will parse HWP Error XML files and creates\n");
+    print ("  the following files:\n");
+    print ("  - hwp_return_codes.H.      HwpReturnCode enumeration (HWP generated errors)\n");
+    print ("  - hwp_error_info.H.        Error information (used by FAPI_SET_HWP_ERROR\n");
+    print ("                             when a HWP generates an error)\n");
+    print ("  - collect_reg_ffdc_regs.H. File containing registers used by collectRegFfdc() \n");
+    print ("  - set_sbe_error.H.    Macro to create an SBE error\n");
+    print ("  The --empty-ffdc-classes option is for platforms which don't collect ffdc.\n");
+    exit(1);
+}
+
+#------------------------------------------------------------------------------
+# Hashes containing error names/enum-values
+#------------------------------------------------------------------------------
+my %errNameToValueHash;
+my %errValuePresentHash;
+
+#------------------------------------------------------------------------------
+# Hashes containing ffdc names/enum-values
+#------------------------------------------------------------------------------
+my %ffdcNameToValueHash = ();
+my %ffdcValuePresentHash = ();
+
+#------------------------------------------------------------------------------
+# Subroutine that checks if an entry exists in an array. If it doesn't exist
+# then it is added. The index of the entry within the array is returned
+#------------------------------------------------------------------------------
+sub addEntryToArray
+{
+    my ($arrayref, $entry ) = @_;
+
+    my $match = 0;
+    my $index = 0;
+
+    foreach my $element (@$arrayref)
+    {
+        if ($element eq $entry)
+        {
+            $match = 1;
+            last;
+        }
+        else
+        {
+            $index++;
+        }
+    }
+
+    if (!($match))
+    {
+        push(@$arrayref, $entry);
+    }
+
+    return $index;
+}
+
+#------------------------------------------------------------------------------
+# Subroutine that figures out an error enum value from an error name and stores
+# it in global hashes
+#------------------------------------------------------------------------------
+sub setErrorEnumValue
+{
+    my $name = $_[0];
+
+    #--------------------------------------------------------------------------
+    # Check that the error name is not a duplicate
+    #--------------------------------------------------------------------------
+    if (exists($errNameToValueHash{$name}))
+    {
+        # Two different errors with the same name!
+        print ("fapiParseErrorInfo.pl ERROR. Duplicate error name ", $name, "\n");
+        exit(1);
+    }
+
+    #--------------------------------------------------------------------------
+    # Figure out the error enum-value. This is a hash value generated from
+    # the error name. A hash is used for Cronus so that if a HWP is not
+    # recompiled against a new eCMD/Cronus version where the errors have
+    # changed then there will not be a mismatch in error values.
+    # This is a 24bit hash value because FAPI has a requirement that the
+    # top byte of the 32 bit error value be zero to store flags indicating
+    # the creator of the error
+    #--------------------------------------------------------------------------
+    my $errHash128Bit = md5_hex($name);
+    my $errHash24Bit = substr($errHash128Bit, 0, 6);
+
+    #--------------------------------------------------------------------------
+    # Check that the error enum-value is not a duplicate
+    #--------------------------------------------------------------------------
+    if (exists($errValuePresentHash{$errHash24Bit}))
+    {
+        # Two different errors generate the same hash-value!
+        print ("fapiParseAttributeInfo.pl ERROR. Duplicate error hash value\n");
+        exit(1);
+    }
+
+    #--------------------------------------------------------------------------
+    # Update the hashes with the error name and ID
+    #--------------------------------------------------------------------------
+    $errValuePresentHash{$errHash24Bit} = 1;
+    $errNameToValueHash{$name} = $errHash24Bit;
+}
+
+#------------------------------------------------------------------------------
+# Subroutine that figures out an FFDC ID value from an FFDC name and stores it
+# in global hashes for use when creating the enumeration of FFDC IDs
+#------------------------------------------------------------------------------
+sub setFfdcIdValue
+{
+    my $name = $_[0];
+
+    #--------------------------------------------------------------------------
+    # Check that the FFDC name is not a duplicate
+    #--------------------------------------------------------------------------
+    if (exists($ffdcNameToValueHash{$name}))
+    {
+        # Two different FFDCs with the same name!
+        print ("fapiParseErrorInfo.pl ERROR. Duplicate FFDC name ", $name, "\n");
+        exit(1);
+    }
+
+    #--------------------------------------------------------------------------
+    # Figure out the FFDC enum-value. This is a hash value generated from
+    # the FFDC name.
+    #--------------------------------------------------------------------------
+    my $ffdcHash128Bit = md5_hex($name);
+    my $ffdcHash32Bit = substr($ffdcHash128Bit, 0, 8);
+
+    #--------------------------------------------------------------------------
+    # Check that the error enum-value is not a duplicate
+    #--------------------------------------------------------------------------
+    if (exists($ffdcValuePresentHash{$ffdcHash32Bit}))
+    {
+        # Two different FFDCs generate the same hash-value!
+        print ("fapiParseAttributeInfo.pl ERROR. Duplicate FFDC hash value\n");
+        exit(1);
+    }
+
+    #--------------------------------------------------------------------------
+    # Update the hashes with the error name and ID
+    #--------------------------------------------------------------------------
+    $ffdcValuePresentHash{$ffdcHash32Bit} = 1;
+    $ffdcNameToValueHash{$name} = $ffdcHash32Bit;
+}
+
+#------------------------------------------------------------------------------
+# Subroutine to create ffdc methods
+#------------------------------------------------------------------------------
+sub addFfdcMethod
+{
+    my $methods = shift;
+    my $ffdc_uc = shift;
+    my $class_name = shift;
+    my $type = shift;
+    my $objectNumber = shift;
+
+    # Remove the leading *_
+    $class_name = (split (/_/, $class_name, 2))[1];
+
+    # If we didn't get a type passed in, this element will get an ffdc_t pair.
+    $type = $ffdc_type if ($type eq undef);
+
+    # Mangle the uppercase name if needed
+    $ffdc_uc = $mangle_names{$ffdc_uc} if ($mangle_names{$ffdc_uc} ne undef);
+
+    my $key = $ffdc_uc.$type;
+    my $key_target = $ffdc_uc.$target_ffdc_type;
+    my $key_ffdc = $ffdc_uc.$ffdc_type;
+
+    # Check to see if this element already has been recorded with this
+    # type or a target type. Note the effect we're shooting for here is
+    # to define the member if it's not been defined before *or* it's
+    # changing from an ffdc_t to a target due to other information in the xml
+    return if ($methods->{$key}{type} eq $type);
+    return if ($methods->{$key_target}{type} eq $target_ffdc_type);
+
+    # Just leave if this is a variable_buffer as we're not supporting that.
+    return if (($type eq $variable_buffer_ffdc_type) && ($arg_use_variable_buffers eq undef));
+
+    # Set the proper type, and clear out any previous members/methods if
+    # we're going from an ffdc_t to a target.
+    $methods->{$key}{type} = $type;
+    delete $methods->{$key_ffdc} if ($type eq $target_ffdc_type);
+
+
+    my $method = "";
+    my $method_body = "";
+
+    # If we're generating empty classes, not using an argument name will avoid the unused parameter warnings
+    my $param = ($arg_empty_ffdc eq undef) ? "i_value" : "";
+
+    if ($type eq $ffdc_type)
+    {
+        $method =      "\ttemplate< typename T >\n";
+        $method  .=      "\tinline $class_name& set_$ffdc_uc(const T& $param)\n";
+
+        if($arg_local_ffdc eq undef)
+        {
+            $method_body  =  "    {$ffdc_uc.ptr() = &i_value; $ffdc_uc.size() =";
+            $method_body  .= " fapi2::getErrorInfoFfdcSize(i_value); return *this;}\n\n";
+            $methods->{$key}{member} = "$ffdc_type $ffdc_uc;";
+            $methods->{$objectNumber}{localvar} = "$ffdc_type $ffdc_uc = getFfdcData(FFDC_BUFFER[$objectNumber]);";
+            $methods->{$objectNumber}{assignment_string} = "l_obj.$ffdc_uc = $ffdc_uc;";
+        }
+        else
+        {
+           # need to use the objectNumber here so when we decode the info at the hwsv/hb side we have a reference,
+           # they will be copied into/out of the sbe buffer in the correct order
+           $method_body .= "\t{\n\t\tfapi2::g_FfdcData.ffdcData[$objectNumber].data= convertType(i_value);\n";
+           $method_body .= "\t\tfapi2::g_FfdcData.ffdcData[$objectNumber].size =";
+           $method_body .=" fapi2::getErrorInfoFfdcSize(i_value);\n";
+           $method_body .= "\t\tfapi2::g_FfdcData.ffdcLength += sizeof(sbeFfdc_t);\n";
+           $method_body .= "\t\treturn *this;\n\t};\n\n";
+       }
+
+    }
+    elsif ($type eq $buffer_ffdc_type)
+    {
+        # Two methods - one for integral buffers and one for variable_buffers
+        $method =      "\n    template< typename T >\n";
+        $method  .=      "    inline $class_name& set_$ffdc_uc(const fapi2::buffer<T>& $param)\n";
+        $method_body  =  "    {$ffdc_uc.ptr() = &i_value(); $ffdc_uc.size() = i_value.template getLength<uint8_t>(); return *this;}\n\n";
+        $methods->{$key}{member} = "$ffdc_type $ffdc_uc;";
+        $methods->{$objectNumber}{localvar} = "$buffer_ffdc_type $ffdc_uc = getFfdcData(FFDC_BUFFER[$objectNumber]);";
+        $methods->{$objectNumber}{assignment_string} = "l_obj.$ffdc_uc = $ffdc_uc;";
+    }
+
+    elsif ($type eq $variable_buffer_ffdc_type)
+    {
+        $method       =  "\n    inline $class_name& set_$ffdc_uc(const fapi2::variable_buffer& $param)\n";
+        $method_body  =    "    {$ffdc_uc.ptr() = &$param(); $ffdc_uc.size() = $param.template getLength<uint8_t>(); return *this;}\n\n";
+
+        # No need to add the member here, it was added with fapi2::buffer. And we can't have variable
+        # buffer support with out integral buffer support (can we?)
+    }
+
+    elsif ($type eq $target_ffdc_type)
+    {
+        $method =      "\n    template< TargetType T >\n";
+        $method .=       "    inline $class_name& set_$ffdc_uc(const $type& $param)\n";
+        $method_body .=  "    {$ffdc_uc.ptr() = &$param; $ffdc_uc.size() = fapi2::getErrorInfoFfdcSize($param); " .
+                              " return *this;}\n\n";
+
+        $methods->{$key}{member} = "$ffdc_type $ffdc_uc;";
+        $methods->{$objectNumber}{localvar} = "$ffdc_type $ffdc_uc = getFfdcData(FFDC_BUFFER[$objectNumber]);";
+        $methods->{$objectNumber}{assignment_string} = "l_obj.$ffdc_uc=$ffdc_uc";
+    }
+
+    else
+    {
+        $method  .=      "\tinline $class_name& set_$ffdc_uc($type $param)\n";
+
+        if($arg_local_ffdc eq undef)
+        {
+            $method_body  =  "    { $ffdc_uc = i_value; ";
+            $method_body  .= " return *this;}\n\n";
+            $methods->{$key}{member} = "$type $ffdc_uc;";
+            $methods->{$objectNumber}{localvar} = "$type $ffdc_uc = getFfdcData(FFDC_BUFFER[$objectNumber]);";
+            $methods->{$objectNumber}{assignment_string} = "l_obj.$ffdc_uc = $ffdc_uc;";
+        }
+        else
+        {
+           # need to use the objectNumber here so when we decode the info at the hwsv/hb side we have a point of
+           # reference and they will be copied into/out of the sbe buffer in the correct order
+           $method_body .= "\t{\n\t\tfapi2::g_FfdcData.ffdcData[$objectNumber].data= convertType(i_value);\n";
+           $method_body .= "\t\tfapi2::g_FfdcData.ffdcData[$objectNumber].size =";
+           $method_body .=" fapi2::getErrorInfoFfdcSize(i_value);\n";
+           $method_body .= "\t\tfapi2::g_FfdcData.ffdcLength += sizeof(sbeFfdc_t);\n";
+           $method_body .= "\t\treturn *this;\n\t};\n\n";
+       }
+    }
+
+    $method .= ($arg_empty_ffdc eq undef) ? $method_body : "    {return *this;}\n\n";
+    $methods->{$key}{method} = $method;
+}
+
+#------------------------------------------------------------------------------
+# Open output files for writing
+#------------------------------------------------------------------------------
+my $rcFile = $arg_output_dir;
+$rcFile .= "/";
+$rcFile .= "hwp_return_codes.H";
+open(RCFILE, ">", $rcFile);
+
+my $eiFile = $arg_output_dir;
+$eiFile .= "/";
+$eiFile .= "hwp_error_info.H";
+open(EIFILE, ">", $eiFile);
+
+my $ecFile = $arg_output_dir;
+$ecFile .= "/";
+$ecFile .= "hwp_ffdc_classes.H";
+open(ECFILE, ">", $ecFile);
+
+my $crFile = $arg_output_dir;
+$crFile .= "/";
+$crFile .= "collect_reg_ffdc_regs.C";
+open(CRFILE, ">", $crFile);
+
+my $sbFile = $arg_output_dir;
+$sbFile .= "/";
+$sbFile .= "set_sbe_error.H";
+open(SBFILE, ">", $sbFile);
+
+#------------------------------------------------------------------------------
+# Print start of file information to hwp_error_info.H
+#------------------------------------------------------------------------------
+print EIFILE "// hwp_error_info.H\n";
+print EIFILE "// This file is generated by the perl script parseErrorInfo.pl\n\n";
+print EIFILE "#ifndef FAPI2_HWPERRORINFO_H_\n";
+print EIFILE "#define FAPI2_HWPERRORINFO_H_\n\n";
+print EIFILE "#include <target.H>\n";
+print EIFILE "#include <plat_trace.H>\n";
+print EIFILE "#include <hwp_return_codes.H>\n";
+print EIFILE "#include <hwp_executor.H>\n";
+print EIFILE "#include <set_sbe_error.H>\n";
+
+print EIFILE "/**\n";
+print EIFILE " * \@brief Error Information macros and HwpFfdcId enumeration\n";
+print EIFILE " *\/\n";
+#------------------------------------------------------------------------------
+# Print start of file information to hwp_ffdc_classes.H
+#------------------------------------------------------------------------------
+print ECFILE "// hwp_ffdc_classes.H\n";
+print ECFILE "// This file is generated by the perl script parseErrorInfo.pl\n\n";
+print ECFILE "#ifndef FAPI2_HWP_FFDC_CLASSES_H_\n";
+print ECFILE "#define FAPI2_HWP_FFDC_CLASSES_H_\n\n";
+print ECFILE "#include <return_code.H>\n";
+print ECFILE "#include <fapi2_hwp_executor.H>\n";
+print ECFILE "#include <error_info.H>\n";
+print ECFILE "#include <buffer.H>\n";
+print ECFILE "#include <variable_buffer.H>\n" if ($arg_use_variable_buffers ne undef);
+print ECFILE "#include <hwp_error_info.H>\n";
+print ECFILE "#if !defined(FAPI2_NO_FFDC) && !defined(MINIMUM_FFDC)\n";
+print ECFILE "#include <ffdc_includes.H>\n";
+print ECFILE "#include <collect_reg_ffdc.H>\n";
+print ECFILE "#endif\n";
+print ECFILE "/**\n";
+print ECFILE " * \@brief FFDC gathering classes\n";
+print ECFILE " *\/\n";
+print ECFILE "namespace fapi2\n{\n";
+if($arg_local_ffdc)
+{
+    print ECFILE "extern SbeFfdcData_t g_FfdcData; \n";
+}
+#------------------------------------------------------------------------------
+# Print start of file information to collect_reg_ffdc_regs.C
+#------------------------------------------------------------------------------
+print CRFILE "// collect_reg_ffdc_regs.C\n";
+print CRFILE "// This file is generated by the perl script parseErrorInfo.pl\n\n";
+print CRFILE "#include <stdint.h>\n";
+print CRFILE "#include <vector>\n";
+print CRFILE "#include <plat_trace.H>\n";
+print CRFILE "#include <hwp_error_info.H>\n";
+print CRFILE "#include <p9_mc_scom_addresses.H>\n";
+print CRFILE "#include <p9_misc_scom_addresses.H>\n";
+print CRFILE "#include <p9_obus_scom_addresses.H>\n";
+print CRFILE "#include <p9_perv_scom_addresses.H>\n";
+print CRFILE "#include <p9_quad_scom_addresses.H>\n";
+print CRFILE "#include <p9_xbus_scom_addresses.H>\n";
+print CRFILE "namespace fapi2\n";
+print CRFILE "{\n";
+print CRFILE "void getAddressData(const fapi2::HwpFfdcId i_ffdcId,\n";
+print CRFILE "                        std::vector<uint64_t>& o_scomAddresses ,\n";
+print CRFILE "                        std::vector<uint32_t>& o_cfamAddresses ,\n";
+print CRFILE "                        uint32_t & o_ffdcSize )\n";
+print CRFILE "{\n";
+print CRFILE "    FAPI_INF(\"getAddresses. FFDC ID: 0x%x\", i_ffdcId);\n";
+print CRFILE "    o_ffdcSize = 0;\n\n";
+print CRFILE "    switch (i_ffdcId)\n";
+print CRFILE "    {\n";
+#------------------------------------------------------------------------------
+# Print start of file information to setSbeError.H
+#------------------------------------------------------------------------------
+print SBFILE "// setSbeError.H\n";
+print SBFILE "// This file is generated by the perl script parseErrorInfo.pl\n\n";
+print SBFILE "// When SBE code creates an error, it produces an error value\n";
+print SBFILE "// that matches a value in the HwpReturnCode enum in\n";
+print SBFILE "// fapiHwpReturnCodes.H. The SBE uses the __ASSEMBLER__\n";
+print SBFILE "// primitives in hwpReturnCodes.H to do this. The function\n";
+print SBFILE "// that extracts the error value from the SBE needs to call\n";
+print SBFILE "// FAPI_SET_HWP_ERROR to create the error and get all the\n";
+print SBFILE "// actions in the error XML file performed, but that macro can\n";
+print SBFILE "// only be called with the enumerator, not the value. This\n";
+print SBFILE "// FAPI_SET_SBE_ERROR macro can be called instead, it calls\n";
+print SBFILE "// FAPI_SET_HWP_ERROR with the correct error enumerator.\n";
+print SBFILE "// Errors containing <sbeError/> in their XML are supported\n";
+print SBFILE "// in this macro.\n\n";
+print SBFILE "// Note that it is expected that this macro will be called\n";
+print SBFILE "// in one place (the function that extracts the error from\n";
+print SBFILE "// the SBE), if this changes and it is called in multiple\n";
+print SBFILE "// places then the macro could be turned into a function to\n";
+print SBFILE "// avoid the code size increase of expanding the macro in\n";
+print SBFILE "// multiple places. The function approach is slightly more\n";
+print SBFILE "// complicated, there is an extra C file and the function\n";
+print SBFILE "// must take a parameter for the generic chip ID in the error\n";
+print SBFILE "// XML.\n\n";
+print SBFILE "#ifndef FAPI2_SETSBEERROR_H_\n";
+print SBFILE "#define FAPI2_SETSBEERROR_H_\n\n";
+print SBFILE "#define FAPI_SET_SBE_ERROR(RC,ERRVAL,FFDC_BUFFER)\\\n";
+print SBFILE "{\\\n";
+print SBFILE "switch (ERRVAL)\\\n";
+print SBFILE "{\\\n";
+
+
+#------------------------------------------------------------------------------
+# For each XML file
+#------------------------------------------------------------------------------
+foreach my $argnum (0 .. $#ARGV)
+{
+    my $infile = $ARGV[$argnum];
+    my $count = 0;
+
+    #--------------------------------------------------------------------------
+    # Read XML file. The ForceArray option ensures that there is an array of
+    # elements even if there is only one element
+    #--------------------------------------------------------------------------
+    my $errors = $xml->XMLin($infile, ForceArray =>
+        ['hwpError', 'collectFfdc', 'ffdc','mcastId', 'callout', 'deconfigure', 'gard',
+         'registerFfdc', 'collectRegisterFfdc', 'cfamRegister', 'scomRegister',
+         'id','collectTrace', 'buffer']);
+
+    # Uncomment to get debug output of all errors
+#    print "\nFile: ", $infile, "\n", Dumper($errors), "\n";
+
+    #--------------------------------------------------------------------------
+    # For each Error
+    #--------------------------------------------------------------------------
+    foreach my $err (@{$errors->{hwpError}})
+    {
+        my $objectStr = undef;
+        # Hash of methods for the ffdc-gathering class
+        my %methods;
+
+        # Array of EI Objects
+         @eiObjects = ();
+
+        #----------------------------------------------------------------------
+        # Check that expected fields are present
+        #----------------------------------------------------------------------
+        if (! exists $err->{rc})
+        {
+            print ("parseErrorInfo.pl ERROR. rc missing\n");
+            exit(1);
+        }
+
+        if (! exists $err->{description})
+        {
+            print ("parseErrorInfo.pl ERROR in $err->{rc}. description missing\n");
+            exit(1);
+        }
+
+        #----------------------------------------------------------------------
+        # Check that this rc hasn't been deprecated
+        #----------------------------------------------------------------------
+        if ($deprecated{$err->{rc}} ne undef)
+        {
+            print "WARNING: $err->{rc} has been deprecated because $deprecated{$err->{rc}}\n";
+            next;
+        }
+
+        #----------------------------------------------------------------------
+        # Set the error enum value in a global hash
+        #---------------------------------------------------------------------
+        setErrorEnumValue($err->{rc});
+
+
+        #----------------------------------------------------------------------
+        # Print the CALL_FUNCS_TO_COLLECT_FFDC macro to hwp_error_info.H
+        #----------------------------------------------------------------------
+        print EIFILE "#define $err->{rc}_CALL_FUNCS_TO_COLLECT_FFDC(RC)";
+
+        my $collectFfdcStr = undef;
+        $count = 0;
+        foreach my $collectFfdc (@{$err->{collectFfdc}})
+        {
+            if ($count == 0)
+            {
+                #this rc wont be used, except to indicate the FFDC collection failed
+                $collectFfdcStr =  "\tfapi2::ReturnCode l_rc; \\\n";
+                # each collect ffdc function needs to populate this so we can add it to i_rc;
+                $collectFfdcStr .= "\tstd::vector<std::shared_ptr<ErrorInfoFfdc>>ffdc; \\\n";
+            }
+            $count++;
+
+            # collectFfdc is a string we're going to stuff into FAPI_EXEC_HWP
+            # but we need to create the arguments in the ffdc class. The first
+            # element in the collectFfdc string is the function to call.
+            my @elements = split /,/, $collectFfdc;
+            my @signature = @{$signatures{@elements[0]}};
+
+            # build up the function call here
+            @elements[0] =~ s/^\s+|\s+$//g;
+            $collectFfdc =  "@elements[0]" .",ffdc";
+            for (my $i = 1; $i <= $#elements; $i++)
+            {
+                $collectFfdc .= ",";
+
+                # the parameters will be in the l_objects, unused, but need to be
+                # counted for the SBE implementation
+                my $parameter = "static_cast<void*>(&"."@elements[$i])";
+
+                # Add the parameter to the object list if it doesn't already exist
+                #
+                my $objNum = addEntryToArray(\@eiObjects, $parameter);
+
+                # add a set method for each parameter too..
+                @elements[$i] =~ s/^\s+|\s+$//g;
+                addFfdcMethod(\%methods, @elements[$i], $err->{rc}, @signature[$i-1],$objNum);
+
+                $collectFfdc .=  "@elements[$i]"
+
+            }
+
+            $collectFfdcStr .= "\tFAPI_EXEC_HWP(l_rc, $collectFfdc); \\\n";
+
+            print EIFILE "\\\n{ \\\n$collectFfdcStr";
+            print EIFILE "\tRC.addErrorInfo(ffdc); \\\n}";
+        } #end collectFfdc tag
+
+        print EIFILE "\n";
+
+        #----------------------------------------------------------------------
+        # Print the CALL_FUNCS_TO_COLLECT_REG_FFDC macro to hwp_error_info.H
+        #----------------------------------------------------------------------
+        print EIFILE "#define $err->{rc}_CALL_FUNCS_TO_COLLECT_REG_FFDC(RC)";
+
+        my $crffdcStr = undef;
+
+        my $crffdcCount =0;
+
+        if($arg_local_ffdc eq undef)
+        {
+            foreach my $collectRegisterFfdc (@{$err->{collectRegisterFfdc}})
+            {
+                #------------------------------------------------------------------
+                # Check that expected fields are present
+                #------------------------------------------------------------------
+                if (! exists $collectRegisterFfdc->{id}[0])
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. id(s) missing from collectRegisterFfdc $infile\n");
+                    exit(1);
+                }
+
+
+                foreach my $id (@{$collectRegisterFfdc->{id}})
+                {
+
+                    if( $crffdcCount eq 0 )
+                    {
+                        print EIFILE " \\\n{ \\\n";
+                        $crffdcStr =  "\tstd::vector<std::shared_ptr<ErrorInfoFfdc>> ffdc; \\\n";
+                    }
+                    else
+                    {
+                        $crffdcStr = "";
+                    }
+
+                    $crffdcCount++;
+                    #---------------------------------------------------------------------------------
+                    # Check FFDC register collection type: target, child, or based on present children
+                    #---------------------------------------------------------------------------------
+                    if (exists $collectRegisterFfdc->{target})
+                    {
+                        if(!(exists $collectRegisterFfdc->{targetType} ))
+                        {
+                           print ("parseErrorInfo.pl ERROR: target type missing from $collectRegisterFfdc->{target} in file $infile\n");
+                           exit(1);
+                        }
+                        $crffdcStr .=  "\tfapi2::collectRegFfdc<$collectRegisterFfdc->{targetType}>($collectRegisterFfdc->{target},";
+                        $crffdcStr .=  "fapi2::$id,ffdc); \\\n";
+
+                        addFfdcMethod(\%methods, $collectRegisterFfdc->{target},
+                            $err->{rc}, $target_ffdc_type);
+                    }
+                    elsif (exists $collectRegisterFfdc->{childTargets})
+                    {
+                        if(!(exists $collectRegisterFfdc->{childTargets}{parent} ))
+                        {
+                            print ("parseErrorInfo.pl ERROR:  parent missing from $collectRegisterFfdc->{id} in  $infile\n");
+                            exit(1);
+                        }
+
+                        if(!(exists $collectRegisterFfdc->{childTargets}{parentType} ))
+                        {
+                            print ("parseErrorInfo.pl ERROR: parent type missing from $collectRegisterFfdc->{id} in $infile\n");
+                            exit(1);
+                        }
+
+                        $crffdcStr .= "\tfapi2::collectRegFfdc<fapi2::$collectRegisterFfdc->{childTargets}->{childType},";
+                        $crffdcStr .= "$collectRegisterFfdc->{childTargets}->{parentType}>";
+                        $crffdcStr .= "($collectRegisterFfdc->{childTargets}->{parent}, ";
+                        $crffdcStr .= "fapi2::TARGET_STATE_FUNCTIONAL,fapi2::$id, ffdc); \\\n";
+
+                        addFfdcMethod(\%methods, $collectRegisterFfdc->{childTargets}->{parent},
+                            $err->{rc}, $target_ffdc_type);
+                    }
+                    elsif (exists $collectRegisterFfdc->{basedOnPresentChildren})
+                    {
+                        if ( exists $collectRegisterFfdc->{basedOnPresentChildren}->{target})
+                        {
+                            if (! exists $collectRegisterFfdc->{basedOnPresentChildren}->{childType})
+                            {
+                                die ("parseErrorInfo.pl ERROR: childType missing from collectRegisterFfdc $infile\n");
+                                exit(1);
+                            }
+                            if(!(exists $collectRegisterFfdc->{basedOnPresentChildren}{targetType} ))
+                            {
+                                print ("parseErrorInfo.pl ERROR:  type missing from ");
+                                print ("$collectRegisterFfdc->{basedOnPresentChildren}{parent} in file $infile\n");
+                                exit(1);
+                            }
+
+                            if (! exists $collectRegisterFfdc->{basedOnPresentChildren}->{childPosOffsetMultiplier})
+                            {
+                                print ("parseErrorInfo.pl ERROR: childPosOffsetMultiplier missing from collectRegisterFfdc $infile\n");
+                                exit(1);
+                            }
+                            $crffdcStr .= "\tfapi2::collectRegFfdc<fapi2::$collectRegisterFfdc->{basedOnPresentChildren}->{childType},";
+                            $crffdcStr .= "$collectRegisterFfdc->{basedOnPresentChildren}->{targetType}>";
+                            $crffdcStr .= "($collectRegisterFfdc->{basedOnPresentChildren}->{target},";
+                            $crffdcStr .= "fapi2::TARGET_STATE_PRESENT,";
+                            $crffdcStr .= "fapi2::$id, ffdc,";
+                            $crffdcStr .= "$collectRegisterFfdc->{basedOnPresentChildren}->{childPosOffsetMultiplier});\\\n";
+                            $crffdcCount++;
+
+                            addFfdcMethod(\%methods, $collectRegisterFfdc->{basedOnPresentChildren}->{target},
+                                $err->{rc}, $target_ffdc_type);
+                        }
+                        else
+                        {
+                            print ("parseErrorInfo.pl ERROR: Invalid collectRegisterFfdc configuration in $infile\n");
+                            exit(1);
+
+                        }
+                    }
+                    else
+                    {
+                        print ("parseErrorInfo.pl ERROR: Invalid collectRegisterFfdc configuration in $infile\n");
+                        exit(1);
+                    }
+
+                    #print the collectRegFfdc string to the info file
+                    print EIFILE "$crffdcStr";
+
+                } #end foreach register id
+
+            } # end foreach collectRegisterFfdc
+
+            if($crffdcCount > 0)
+            {
+                print EIFILE "\tRC.addErrorInfo(ffdc); \\\n}\n";
+            }
+
+        }
+        print EIFILE "\n";
+
+        #----------------------------------------------------------------------
+        # Print the ADD_ERROR_INFO macro to hwp_error_info.H
+        #----------------------------------------------------------------------
+        print EIFILE "#define $err->{rc}_ADD_ERROR_INFO(RC)";
+
+        my $eiEntryStr = undef;
+        my $eiObjectMap = undef;  #object names to buffer address mapping
+        my $eiObjectStr = "\tconst void * l_objects[] = {";
+        my $executeStr = undef;
+        my $eiEntryCount = 0;
+        my %cdgTargetHash; # Records the callout/deconfigure/gards for Targets
+        my %cdgChildHash;  # Records the callout/deconfigure/gards for Children
+
+        # collect firmware trace
+        foreach my $collectTrace (@{$err->{collectTrace}})
+        {
+            # Add an EI entry to eiEntryStr
+            $eiEntryStr .= "\tl_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_COLLECT_TRACE; \\\n";
+            $eiEntryStr .= "\tl_entries[$eiEntryCount].collect_trace.iv_eieTraceId =  fapi2::CollectTraces::$collectTrace; \\\n";
+            $eiEntryCount++;
+        } #end foreach $collectTrace
+
+        # Local FFDC
+        foreach my $ffdc (@{$err->{ffdc}})
+        {
+
+            # Set the FFDC ID value in a global hash. The name is <rc>_<ffdc>
+            my $ffdcName = $err->{rc} . "_";
+            $ffdcName = $ffdcName . $ffdc;
+            setFfdcIdValue($ffdcName);
+
+            # Add the FFDC data to the EI Object array if it doesn't already exist
+            my $objNum = addEntryToArray(\@eiObjects, $ffdc);
+
+            # Add a method to the ffdc-gathering class
+            addFfdcMethod(\%methods, $ffdc, $err->{rc},$ffdc_type,$objNum);
+
+            $ffdc = $mangle_names{$ffdc} if ($mangle_names{$ffdc} ne undef);
+
+            # Add an EI entry to eiEntryStr
+            $eiEntryStr .= "\tl_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_FFDC; \\\n";
+            $eiEntryStr .= "\tl_entries[$eiEntryCount].ffdc.iv_ffdcObjIndex = $objNum; \\\n";
+            $eiEntryStr .= "\tl_entries[$eiEntryCount].ffdc.iv_ffdcId = fapi2::$ffdcName; \\\n";
+            $eiEntryStr .= "\tl_entries[$eiEntryCount].ffdc.iv_ffdcSize = $ffdc.size(); \\\n";
+            $eiEntryCount++;
+        } #end foreach $ffdc
+
+        # Multicast ID
+        foreach my $mcast (@{$err->{mcastId}})
+        {
+            # Set the FFDC ID value in a global hash. The name is <rc>_<ffdc>
+            my $ffdcName = $err->{rc} . "_";
+            $ffdcName = $ffdcName . $mcast;
+            setFfdcIdValue($ffdcName);
+
+            # Add the FFDC data to the EI Object array if it doesn't already exist
+            my $objNum = addEntryToArray(\@eiObjects, $mcast);
+
+            # Add a method to the ffdc-gathering class
+            addFfdcMethod(\%methods, $mcast, $err->{rc},$mcast_type,$objNum);
+
+            $mcast = $mangle_names{$mcast} if ($mangle_names{$mcast} ne undef);
+
+            # Add an EI entry to eiEntryStr
+            $eiEntryStr .= "\tl_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_FFDC; \\\n";
+            $eiEntryStr .= "\tl_entries[$eiEntryCount].ffdc.iv_ffdcObjIndex = $objNum; \\\n";
+            $eiEntryStr .= "\tl_entries[$eiEntryCount].ffdc.iv_ffdcId = fapi2::$ffdcName; \\\n";
+            $eiEntryStr .= "\tl_entries[$eiEntryCount].ffdc.iv_ffdcSize = 4; \\\n";
+            $eiEntryCount++;
+        } #foreach mcastId
+
+        if($arg_local_ffdc eq undef)
+        {
+            # Buffers, looks a lot like local ffdc
+            foreach my $buffer (@{$err->{buffer}})
+            {
+                # Set the FFDC ID value in a global hash. The name is <rc>_<ffdc>
+                my $bufferName = $err->{rc} . "_";
+                $bufferName = $bufferName . $buffer;
+                setFfdcIdValue($bufferName);
+
+                # Add the FFDC data to the EI Object array if it doesn't already exist
+                my $objNum = addEntryToArray(\@eiObjects, $buffer);
+
+                # Add a method to the ffdc-gathering class - one for each buffer type
+                addFfdcMethod(\%methods, $buffer, $err->{rc}, $buffer_ffdc_type);
+                addFfdcMethod(\%methods, $buffer, $err->{rc}, $variable_buffer_ffdc_type);
+
+                # Add an EI entry to eiEntryStr
+                $eiEntryStr .= "\tl_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_FFDC; \\\n";
+                $eiEntryStr .= "\tl_entries[$eiEntryCount].ffdc.iv_ffdcObjIndex = $objNum; \\\n";
+                $eiEntryStr .= "\tl_entries[$eiEntryCount].ffdc.iv_ffdcId = fapi2::$bufferName; \\\n";
+                $eiEntryStr .= "\tl_entries[$eiEntryCount].ffdc.iv_ffdcSize = fapi2::getErrorInfoFfdcSize($buffer); \\\n";
+                $eiEntryCount++;
+            } #foreach $buffer
+
+            # Procedure/Target/Bus/Child callouts
+            foreach my $callout (@{$err->{callout}})
+            {
+                if (! exists $callout->{priority})
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. Callout priority missing\n");
+                    exit(1);
+                }
+
+                my $elementsFound = 0;
+                if (exists $callout->{hw})
+                {
+                    # HW Callout
+                    if (! exists $callout->{hw}->{hwid})
+                    {
+                        print ("parseErrorInfo.pl ERROR in $err->{rc}. HW Callout hwid missing\n");
+                        exit(1);
+                    }
+
+                    # Check that those HW callouts that need reference targets have them
+                    if (($callout->{hw}->{hwid} eq "TOD_CLOCK") ||
+                        ($callout->{hw}->{hwid} eq "MEM_REF_CLOCK") ||
+                        ($callout->{hw}->{hwid} eq "PROC_REF_CLOCK") ||
+                        ($callout->{hw}->{hwid} eq "PCI_REF_CLOCK"))
+                    {
+                        if (! exists $callout->{hw}->{refTarget})
+                        {
+                            print ("parseErrorInfo.pl ERROR in $err->{rc}. Callout missing refTarget\n");
+                            exit(1);
+                        }
+                    }
+
+                    # Add an EI entry to eiEntryStr
+                    $eiEntryStr .= "\tl_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_HW_CALLOUT; \\\n";
+                    $eiEntryStr .= "\tl_entries[$eiEntryCount].hw_callout.iv_hw = fapi2::HwCallouts::$callout->{hw}->{hwid}; \\\n";
+                    $eiEntryStr .= "\tl_entries[$eiEntryCount].hw_callout.iv_calloutPriority = fapi2::CalloutPriorities::$callout->{priority}; \\\n";
+                    if (exists $callout->{hw}->{refTarget})
+                    {
+                        # Add the Targets to the objectlist if they don't already exist
+                        my $objNum = addEntryToArray(\@eiObjects, $callout->{hw}->{refTarget});
+                        $eiEntryStr .= "\tl_entries[$eiEntryCount].hw_callout.iv_refObjIndex = $objNum; \\\n";
+
+                        # Add a method to the ffdc-gathering class
+                        addFfdcMethod(\%methods, $callout->{hw}->{refTarget}, $err->{rc});
+                    }
+                    else
+                    {
+                        $eiEntryStr .= "\tl_entries[$eiEntryCount].hw_callout.iv_refObjIndex = 0xff; \\\n";
+                    }
+                    $eiEntryCount++;
+                    $elementsFound++;
+                }
+                if (exists $callout->{procedure})
+                {
+                    # Procedure Callout
+                    # Add an EI entry to eiEntryStr
+                    $eiEntryStr .= "\tl_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_PROCEDURE_CALLOUT; \\\n";
+                    $eiEntryStr .= "\tl_entries[$eiEntryCount].proc_callout.iv_procedure = fapi2::ProcedureCallouts::$callout->{procedure}; \\\n";
+                    $eiEntryStr .= "\tl_entries[$eiEntryCount].proc_callout.iv_calloutPriority = fapi2::CalloutPriorities::$callout->{priority}; \\\n";
+                    $eiEntryCount++;
+                    $elementsFound++;
+                }
+                if (exists $callout->{bus})
+                {
+                    # A Bus Callout consists of two targets separated by
+                    # commas/spaces
+                    my @targets = split(/\s*,\s*|\s+/, $callout->{bus});
+
+                    if (scalar @targets != 2)
+                    {
+                        print ("parseErrorInfo.pl ERROR in $err->{rc}. did not find two targets in bus callout\n");
+                        exit(1);
+                    }
+
+                    # Add the Targets to the objectlist if they don't already exist
+                    my $objNum1 = addEntryToArray(\@eiObjects, $targets[0]);
+
+                    my $objNum2 = addEntryToArray(\@eiObjects, $targets[1]);
+
+                    # Add a method to the ffdc-gathering class
+                    addFfdcMethod(\%methods, $targets[0], $err->{rc}, $target_ffdc_type);
+                    addFfdcMethod(\%methods, $targets[1], $err->{rc}, $target_ffdc_type);
+
+                    # Add an EI entry to eiEntryStr
+                    $eiEntryStr .= "\tl_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_BUS_CALLOUT; \\\n";
+                    $eiEntryStr .= "\tl_entries[$eiEntryCount].bus_callout.iv_endpoint1ObjIndex = $objNum1; \\\n";
+                    $eiEntryStr .= "\tl_entries[$eiEntryCount].bus_callout.iv_endpoint2ObjIndex = $objNum2; \\\n";
+                    $eiEntryStr .= "\tl_entries[$eiEntryCount].bus_callout.iv_calloutPriority = fapi2::CalloutPriorities::$callout->{priority}; \\\n";
+                    $eiEntryCount++;
+                    $elementsFound++;
+                }
+                if (exists $callout->{target})
+                {
+                    # Add the Target to cdgTargetHash to be processed with any
+                    # deconfigure and GARD requests
+                    $cdgTargetHash{$callout->{target}}{callout} = 1;
+                    $cdgTargetHash{$callout->{target}}{priority} =
+                    $callout->{priority};
+
+                    $elementsFound++;
+                }
+                if (exists $callout->{childTargets})
+                {
+                    # Check that the parent and childType subelements exist
+                    if (! exists $callout->{childTargets}->{parent})
+                    {
+                        print ("parseErrorInfo.pl ERROR in $err->{rc}. Child Callout parent missing\n");
+                        exit(1);
+                    }
+
+                    if (! exists $callout->{childTargets}->{childType})
+                    {
+                        print ("parseErrorInfo.pl ERROR in $err->{rc}. Child Callout childType missing\n");
+                        exit(1);
+                    }
+
+                    # Add the child info to cdgChildHash to be processed with
+                    # any deconfigure and GARD requests
+                    my $parent = $callout->{childTargets}->{parent};
+                    my $childType = $callout->{childTargets}->{childType};
+                    $cdgChildHash{$parent}{$childType}{callout} = 1;
+                    $cdgChildHash{$parent}{$childType}{priority} =
+                    $callout->{priority};
+
+                    $elementsFound++;
+
+                    if (exists $callout->{childTargets}->{childPort})
+                    {
+                        my $childPort = $callout->{childTargets}->{childPort};
+
+                        $cdgChildHash{$parent}{$childType}{childPort} = $childPort;
+                    }
+
+                    if (exists $callout->{childTargets}->{childNumber})
+                    {
+                        my $childNum = $callout->{childTargets}->{childNumber};
+                        $cdgChildHash{$parent}{$childType}{childNumber} = $childNum;
+                    }
+
+                }
+                if ($elementsFound == 0)
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. Callout incomplete\n");
+                    exit(1);
+                }
+                elsif ($elementsFound > 1)
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. Callout has multiple elements\n");
+                    exit(1);
+                }
+            } # callout
+
+            # Target/Child deconfigures
+            foreach my $deconfigure (@{$err->{deconfigure}})
+            {
+                my $elementsFound = 0;
+                if (exists $deconfigure->{target})
+                {
+                    # Add the Target to cdgTargetHash to be processed with any
+                    # callout and GARD requests
+                    $cdgTargetHash{$deconfigure->{target}}{deconf} = 1;
+                    $elementsFound++;
+                }
+                if (exists $deconfigure->{childTargets})
+                {
+                    # Check that the parent and childType subelements exist
+                    if (! exists $deconfigure->{childTargets}->{parent})
+                    {
+                        print ("parseErrorInfo.pl ERROR in $err->{rc}. Child Deconfigure parent missing\n");
+                        exit(1);
+                    }
+                    if (! exists $deconfigure->{childTargets}->{childType})
+                    {
+                        print ("parseErrorInfo.pl ERROR in $err->{rc}. Child Deconfigure childType missing\n");
+                        exit(1);
+                    }
+
+                    # Add the child info to cdgChildHash to be processed with
+                    # any callout and GARD requests
+                    my $parent = $deconfigure->{childTargets}->{parent};
+                    my $childType = $deconfigure->{childTargets}->{childType};
+                    $cdgChildHash{$parent}{$childType}{deconf} = 1;
+
+                    $elementsFound++;
+
+                    if ( exists $deconfigure->{childTargets}->{childPort})
+                    {
+                        my $childPort = $deconfigure->{childTargets}->{childPort};
+
+                        $cdgChildHash{$parent}{$childType}{childPort} = $childPort;
+                    }
+
+                    if ( exists $deconfigure->{childTargets}->{childNumber})
+                    {
+                        my $childNum = $deconfigure->{childTargets}->{childNumber};
+                        $cdgChildHash{$parent}{$childType}{childNumber} = $childNum;
+
+                    }
+                }
+                if ($elementsFound == 0)
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. Deconfigure incomplete\n");
+                    exit(1);
+                }
+                elsif ($elementsFound > 1)
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. Deconfigure has multiple elements\n");
+                    exit(1);
+                }
+            } # deconfigure
+
+            # Target/Child Gards
+            foreach my $gard (@{$err->{gard}})
+            {
+                my $elementsFound = 0;
+                if (exists $gard->{target})
+                {
+                    # Add the Target to cdgTargetHash to be processed with any
+                    # callout and deconfigure requests
+                    $cdgTargetHash{$gard->{target}}{gard} = 1;
+                    $elementsFound++;
+                }
+                if (exists $gard->{childTargets})
+                {
+                    # Check that the parent and childType subelements exist
+                    if (! exists $gard->{childTargets}->{parent})
+                    {
+                        print ("parseErrorInfo.pl ERROR in $err->{rc}. Child GARD parent missing\n");
+                        exit(1);
+                    }
+                    if (! exists $gard->{childTargets}->{childType})
+                    {
+                        print ("parseErrorInfo.pl ERROR in $err->{rc}. Child GARD childType missing\n");
+                        exit(1);
+                    }
+
+                    # Add the child info to cdgChildHash to be processed with
+                    # any callout and deconfigure requests
+                    my $parent = $gard->{childTargets}->{parent};
+                    my $childType = $gard->{childTargets}->{childType};
+                    $cdgChildHash{$parent}{$childType}{gard} = 1;
+
+                    $elementsFound++;
+
+                    if ( exists $gard->{childTargets}->{childPort})
+                    {
+                        my $childPort = $gard->{childTargets}->{childPort};
+
+                        $cdgChildHash{$parent}{$childType}{childPort} = $childPort;
+
+                    }
+
+                    if ( exists $gard->{childTargets}->{childNumber})
+                    {
+                        my $childNum = $gard->{childTargets}->{childNumber};
+                        $cdgChildHash{$parent}{$childType}{childNumber} = $childNum;
+                    }
+                }
+                if ($elementsFound == 0)
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. GARD incomplete\n");
+                    exit(1);
+                }
+                elsif ($elementsFound > 1)
+                {
+                    print ("parseErrorInfo.pl ERROR in $err->{rc}. GARD has multiple elements\n");
+                    exit(1);
+                }
+            } # gard
+
+            # Process the callout, deconfigures and GARDs for each Target
+            foreach my $cdg (keys %cdgTargetHash)
+            {
+                my $callout = 0;
+                my $priority = 'LOW';
+                my $deconf = 0;
+                my $gard = 0;
+
+                if (exists $cdgTargetHash{$cdg}->{callout})
+                {
+                    $callout = 1;
+                }
+                if (exists $cdgTargetHash{$cdg}->{priority})
+                {
+                    $priority = $cdgTargetHash{$cdg}->{priority};
+                }
+                if (exists $cdgTargetHash{$cdg}->{deconf})
+                {
+                    $deconf = 1;
+                }
+                if (exists $cdgTargetHash{$cdg}->{gard})
+                {
+                    $gard = 1;
+                }
+
+                # Add the Target to the objectlist if it doesn't already exist
+                my $objNum = addEntryToArray(\@eiObjects, $cdg);
+
+                # Add a method to the ffdc-gathering class
+                addFfdcMethod(\%methods, $cdg, $err->{rc}, $target_ffdc_type);
+
+                # Add an EI entry to eiEntryStr
+                $eiEntryStr .= "\tl_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_CDG; \\\n";
+                $eiEntryStr .= "\tl_entries[$eiEntryCount].target_cdg.iv_targetObjIndex = $objNum; \\\n";
+                $eiEntryStr .= "\tl_entries[$eiEntryCount].target_cdg.iv_callout = $callout; \\\n";
+                $eiEntryStr .= "\tl_entries[$eiEntryCount].target_cdg.iv_deconfigure = $deconf; \\\n";
+                $eiEntryStr .= "\tl_entries[$eiEntryCount].target_cdg.iv_gard = $gard; \\\n";
+                $eiEntryStr .= "\tl_entries[$eiEntryCount].target_cdg.iv_calloutPriority = fapi2::CalloutPriorities::$priority; \\\n";
+                $eiEntryCount++;
+            }
+
+            # Process the callout, deconfigures and GARDs for Child Targets
+            foreach my $parent (keys %cdgChildHash)
+            {
+                foreach my $childType (keys %{$cdgChildHash{$parent}})
+                {
+                    my $callout = 0;
+                    my $priority = 'LOW';
+                    my $deconf = 0;
+                    my $gard = 0;
+                    my $childPort = 0xFF;
+                    my $childNumber = 0xFF;
+
+                    if (exists $cdgChildHash{$parent}{$childType}->{callout})
+                    {
+                        $callout = 1;
+                    }
+                    if (exists $cdgChildHash{$parent}->{$childType}->{priority})
+                    {
+                        $priority =
+                        $cdgChildHash{$parent}->{$childType}->{priority};
+                    }
+                    if (exists $cdgChildHash{$parent}->{$childType}->{deconf})
+                    {
+                        $deconf = 1;
+                    }
+                    if (exists $cdgChildHash{$parent}->{$childType}->{childPort})
+                    {
+                        $childPort =
+                        $cdgChildHash{$parent}->{$childType}->{childPort} ;
+                        addFfdcMethod(\%methods, $childPort, $err->{rc});
+                    }
+                    if (exists $cdgChildHash{$parent}->{$childType}->{childNumber})
+                    {
+                        $childNumber =
+                        $cdgChildHash{$parent}->{$childType}->{childNumber} ;
+                        addFfdcMethod(\%methods, $childNumber, $err->{rc});
+                    }
+                    if (exists $cdgChildHash{$parent}->{$childType}->{gard})
+                    {
+                        $gard = 1;
+                    }
+
+
+                    # Add the Target to the objectlist if it doesn't already exist
+                    my $objNum = addEntryToArray(\@eiObjects, $parent);
+                    addFfdcMethod(\%methods, $parent, $err->{rc}, $target_ffdc_type);
+
+                    # Add an EI entry to eiEntryStr
+                    $eiEntryStr .=
+                    "\tl_entries[$eiEntryCount].iv_type = fapi2::EI_TYPE_CHILDREN_CDG; \\\n";
+                    $eiEntryStr .=
+                    "\tl_entries[$eiEntryCount].children_cdg.iv_parentObjIndex = $objNum; \\\n";
+                    $eiEntryStr .=
+                    "\tl_entries[$eiEntryCount].children_cdg.iv_callout = $callout; \\\n";
+                    $eiEntryStr .=
+                    "\tl_entries[$eiEntryCount].children_cdg.iv_deconfigure = $deconf; \\\n";
+                    $eiEntryStr .=
+                    "\tl_entries[$eiEntryCount].children_cdg.iv_childType = fapi2::$childType; \\\n";
+                    $eiEntryStr .=
+                    "\tl_entries[$eiEntryCount].children_cdg.iv_childPort = $childPort; \\\n";
+                    $eiEntryStr .=
+                    "\tl_entries[$eiEntryCount].children_cdg.iv_childNumber = $childNumber; \\\n";
+                    $eiEntryStr .=
+                    "\tl_entries[$eiEntryCount].children_cdg.iv_gard = $gard; \\\n";
+                    $eiEntryStr .=
+                    "\tl_entries[$eiEntryCount].children_cdg.iv_calloutPriority = fapi2::CalloutPriorities::$priority; \\\n";
+                    $eiEntryCount++;
+                }
+            }
+        }
+        # Add all objects to $eiObjectStr
+        my $objCount = 0;
+
+        # add ordinary types to eiObjectStr here
+
+        foreach my $eiObject (@eiObjects)
+        {
+            if ($objCount > 0)
+            {
+                $eiObjectStr .= ", ";
+            }
+
+            if ($mangle_names{$eiObject} eq undef)
+            {
+                $eiObjectStr .= "$eiObject";
+
+                if ((exists $err->{sbeError}) )
+                {
+                   if((exists $methods{$objCount}{object}))
+                    {
+                        $objectStr .= "\t\t$methods{$objCount}{object} \\\n";
+
+                    }
+
+                   if((exists $methods{$objCount}{localvar}))
+                    {
+                        $objectStr .= "\t\t$methods{$objCount}{localvar} \\\n";
+                        $objectStr .= "\t\t$methods{$objCount}{assignment_string} \\\n";
+                    }
+                }
+            }
+            else
+            {
+                $eiObjectStr .= $mangle_names{$eiObject};
+            }
+
+            $objCount++;
+        }
+
+
+        $eiObjectStr .= "};";
+
+
+        # Print info to file
+        if ($eiEntryCount > 0)
+        {
+            print EIFILE " \\\n{ \\\n $eiObjectStr \\\n";
+            print EIFILE "\tfapi2::ErrorInfoEntry l_entries[$eiEntryCount]; \\\n";
+            print EIFILE "$eiEntryStr";
+            print EIFILE "\tRC.addErrorInfo(l_objects, l_entries, $eiEntryCount); \\\n}";
+        }
+
+        print EIFILE "\n";
+
+        #----------------------------------------------------------------------
+        # Print the return code class to hwp_error_info.H
+        #----------------------------------------------------------------------
+        # Remove the repeated whitespace and newlines other characters from the description
+        $err->{description} =~ s/^\s+|\s+$|"//g;
+        $err->{description} =~ tr{\n}{ };
+        $err->{description} =~ s/\h+/ /g;
+
+        #----------------------------------------------------------------------
+        # Print the return code class to hwp_error_info.H
+        #----------------------------------------------------------------------
+        my $class_name = $err->{rc};
+        # Remove everything upto and including the first _. This makes the ffdc class
+        # names different from the error code value enum names.
+        $class_name = (split (/_/, $class_name, 2))[1];
+
+        # Class declaration
+        print ECFILE "\nclass $class_name\n{\n  public:\n";
+
+        # Constructor. This traces the description. If this is too much, we can
+        # remove it.
+        if ($arg_empty_ffdc eq undef)
+        {
+            if($arg_local_ffdc eq undef)
+            {
+                print ECFILE "    $class_name(fapi2::errlSeverity_t i_sev = fapi2::FAPI2_ERRL_SEV_UNRECOVERABLE, fapi2::ReturnCode& i_rc = fapi2::current_err):\n";
+                print ECFILE "        iv_rc(i_rc),\n";
+                print ECFILE "        iv_sev(i_sev)\n";
+                print ECFILE "        { FAPI_ERR(\"$err->{description}\"); }\n\n";
+            }
+            else
+            {
+                print ECFILE "    $class_name()\n";
+                print ECFILE "    {\n\t\tfapi2::current_err = RC_$class_name;\n\t\tFAPI_ERR(\"$err->{description}\");\n";
+                print ECFILE "    \tfapi2::g_FfdcData.fapiRc = RC_$class_name;\n\t}\n\n";
+            }
+        }
+        else
+        {
+            # Void expression keeps the compiler from complaining about the unused arguments.
+            # We want to set the i_rc to the RC if we're empty. This otherwise gets done in _setHwpError()
+            print ECFILE "    $class_name(fapi2::errlSeverity_t i_sev = fapi2::FAPI2_ERRL_SEV_UNRECOVERABLE, fapi2::ReturnCode& i_rc = fapi2::current_err)\n";
+            print ECFILE "    {\n";
+            print ECFILE "        static_cast<void>(i_sev);\n";
+            print ECFILE "        i_rc = $err->{rc};\n";
+            print ECFILE "    }\n\n";
+        }
+
+        my $method_count = 0;
+        # Methods
+        foreach my $key (keys %methods)
+        {
+            print ECFILE $methods{$key}{method};
+            $method_count++;
+        }
+        if($arg_local_ffdc eq undef)
+        {
+            # add a method to adjust the severity if desired
+            print ECFILE "\tinline void setSev(const fapi2::errlSeverity_t i_sev)\n";
+            if ($arg_empty_ffdc eq undef)
+            {
+                print ECFILE "\t\t\t{ iv_sev = i_sev;};\n\n";
+            }
+            else
+            {
+                print ECFILE "\t\t\t{ static_cast<void>(i_sev);};\n\n";
+            }
+
+            # add a method to read the severity if desired
+            print ECFILE "\tinline fapi2::errlSeverity_t getSev() const\n";
+            if ($arg_empty_ffdc eq undef)
+            {
+                print ECFILE "\t\t\t{ return iv_sev; };\n\n";
+            }
+            else
+            {
+                print ECFILE "\t\t\t{ return fapi2::FAPI2_ERRL_SEV_UNDEFINED; };\n\n";
+            }
+
+        }
+
+        if( $arg_local_ffdc eq undef )
+        {
+
+
+
+            # Stick the execute method at the end of the other methods. We allow
+            # passing in of the severity so that macros which call execute() can over-ride
+            # the default severity.
+            print ECFILE "\tvoid execute(fapi2::errlSeverity_t " .
+            "i_sev = fapi2::FAPI2_ERRL_SEV_UNDEFINED," .
+            "bool commit = false )\n";
+            if ($arg_empty_ffdc eq undef )
+            {
+                print ECFILE "\t\t{\n";
+                print ECFILE "\t\t\tFAPI_SET_HWP_ERROR(iv_rc,$err->{rc});\n\n";
+                print ECFILE "\t\t\tif( commit )\n";
+                print ECFILE "\t\t\t{\n";
+                print ECFILE "\t\t\t\tfapi2::logError(iv_rc, " .
+                "(i_sev == fapi2::FAPI2_ERRL_SEV_UNDEFINED)" .
+                " ? iv_sev : i_sev);\n";
+                print ECFILE "\t\t\t}\n";
+                print ECFILE "\t\t}\n";
+
+            }
+            else
+            {
+                print ECFILE "    {\n";
+                print ECFILE "        static_cast<void>(i_sev);\n";
+                print ECFILE "        static_cast<void>(commit);\n";
+                print ECFILE "    }\n\n";
+            }
+
+            # Instance variables
+            if ($arg_empty_ffdc eq undef)
+            {
+                print ECFILE "\tpublic:\n";
+                foreach my $key (keys %methods)
+                {
+                    if( !($methods{$key}{member} eq undef) )
+                    {
+                        print ECFILE "\t\t$methods{$key}{member}\n";
+                    }
+
+                }
+
+                print ECFILE "\t\tfapi2::ReturnCode& iv_rc;\n";
+                print ECFILE "\t\tfapi2::errlSeverity_t iv_sev;\n";
+            }
+
+        }
+        else
+        {
+            print ECFILE "    void execute()\n";
+            print ECFILE "    {\n";
+            print ECFILE "$executeStr\n";
+            print ECFILE "    }\n";
+        }
+
+        print ECFILE "};\n\n";
+
+        #----------------------------------------------------------------------
+        # If this is an SBE error, add it to set_sbe_error.H
+        #----------------------------------------------------------------------
+        if (exists $err->{sbeError})
+        {
+            print SBFILE "\tcase fapi2::$err->{rc}: \\\n";
+            print SBFILE "\t{\\\n\t\t$class_name l_obj(";
+            print SBFILE "fapi2::FAPI2_ERRL_SEV_UNRECOVERABLE,RC);\\\n";
+
+            if(!($objectStr eq undef ))
+            {
+                print SBFILE "$objectStr";
+            }
+            print SBFILE "\t\tl_obj.execute(); \\\n";
+            print SBFILE "\t\tbreak; \\\n\t} \\\n";
+        }
+
+    } #for each hwpError tag
+    #
+    #--------------------------------------------------------------------------
+    # For each registerFfdc.
+    #--------------------------------------------------------------------------
+    foreach my $registerFfdc (@{$errors->{registerFfdc}})
+    {
+        #----------------------------------------------------------------------
+        # Check that expected fields are present
+        #----------------------------------------------------------------------
+        if (! exists $registerFfdc->{id}[0])
+        {
+            print ("parseErrorInfo.pl ERROR. id missing from registerFfdc\n");
+            exit(1);
+        }
+
+        if (scalar @{$registerFfdc->{id}} > 1)
+        {
+            print ("parseErrorInfo.pl ERROR. multiple ids in registerFfdc\n");
+            exit(1);
+        }
+
+        #----------------------------------------------------------------------
+        # Set the FFDC ID value in a global hash
+        #----------------------------------------------------------------------
+        setFfdcIdValue($registerFfdc->{id}[0]);
+
+        #----------------------------------------------------------------------
+        # Generate code to capture the registers in collect_reg_ffdc_regs.C
+        #----------------------------------------------------------------------
+        print CRFILE "        case $registerFfdc->{id}[0]:\n";
+
+        # Look for CFAM Register addresses
+        foreach my $cfamRegister (@{$registerFfdc->{cfamRegister}})
+        {
+            print CRFILE "            o_cfamAddresses.push_back($cfamRegister);\n";
+        }
+
+        # Look for SCOM Register addresses
+        foreach my $scomRegister (@{$registerFfdc->{scomRegister}})
+        {
+            print CRFILE "            o_scomAddresses.push_back($scomRegister);\n";
+        }
+
+        print CRFILE "            break;\n";
+    }
+
+
+}
+
+#------------------------------------------------------------------------------
+# Print end of file information to collect_reg_ffdc_regs.C
+#------------------------------------------------------------------------------
+print CRFILE "        default:\n";
+print CRFILE "            FAPI_ERR(\"collect_reg_ffdc_regs.C: Invalid FFDC ID 0x%x\", ";
+print CRFILE                     "i_ffdcId);\n";
+print CRFILE "            return;\n";
+print CRFILE "    }\n";
+print CRFILE "o_ffdcSize = o_scomAddresses.size() * sizeof(uint64_t);\n";
+print CRFILE "o_ffdcSize += o_cfamAddresses.size() * sizeof(uint32_t);\n";
+print CRFILE "}\n";
+print CRFILE "} // end namespace\n\n";
+
+#------------------------------------------------------------------------------
+# Print the fapiHwpReturnCodes.H file
+#------------------------------------------------------------------------------
+print RCFILE "// fapiHwpReturnCodes.H\n";
+print RCFILE "// This file is generated by perl script parseErrorInfo.pl\n\n";
+print RCFILE "#ifndef FAPI2_HWPRETURNCODES_H_\n";
+print RCFILE "#define FAPI2_HWPRETURNCODES_H_\n\n";
+print RCFILE "#ifndef __ASSEMBLER__\n";
+print RCFILE "namespace fapi2\n";
+print RCFILE "{\n\n";
+print RCFILE "/**\n";
+print RCFILE " * \@brief Enumeration of HWP return codes\n";
+print RCFILE " *\/\n";
+print RCFILE "enum HwpReturnCode\n";
+print RCFILE "{\n";
+foreach my $key (keys %errNameToValueHash)
+{
+    print RCFILE "    $key = 0x$errNameToValueHash{$key},\n";
+}
+print RCFILE "};\n\n";
+print RCFILE "}\n\n";
+print RCFILE "#else\n";
+foreach my $key (keys %errNameToValueHash)
+{
+    print RCFILE "    .set $key, 0x$errNameToValueHash{$key}\n";
+}
+print RCFILE "#endif\n";
+print RCFILE "#endif\n";
+
+#------------------------------------------------------------------------------
+# Print the HwpFfdcId enumeration to hwp_error_info.H
+#------------------------------------------------------------------------------
+print EIFILE "namespace fapi2\n";
+print EIFILE "{\n\n";
+if($arg_local_ffdc)
+{
+    print EIFILE "  extern SbeFfdcData_t g_FfdcData;\n";
+}
+print EIFILE "/**\n";
+print EIFILE " * \@brief Enumeration of FFDC identifiers\n";
+print EIFILE " *\/\n";
+print EIFILE "enum HwpFfdcId\n";
+print EIFILE "{\n";
+foreach my $key (keys %ffdcNameToValueHash)
+{
+    print EIFILE "    $key = 0x$ffdcNameToValueHash{$key},\n";
+}
+print EIFILE "};\n\n";
+print EIFILE "}\n\n";
+
+#------------------------------------------------------------------------------
+# Print end of file information to hwp_error_info.H
+#------------------------------------------------------------------------------
+print EIFILE "\n\n#endif\n";
+
+#------------------------------------------------------------------------------
+# Print end of file information to hwp_ffdc_classes.H
+#------------------------------------------------------------------------------
+print ECFILE "\n};\n"; # close the namespace
+print ECFILE "\n\n#endif\n";
+
+#------------------------------------------------------------------------------
+# Print end of file information to set_sbe_error.H
+#------------------------------------------------------------------------------
+print SBFILE "    default:\\\n";
+#print SBFILE "        FAPI_SET_HWP_ERROR(RC, RC_SBE_UNKNOWN_ERROR,0);\\\n";
+print SBFILE "        break;\\\n";
+print SBFILE "}\\\n";
+print SBFILE "}\n\n";
+print SBFILE "#endif\n";
+
+#------------------------------------------------------------------------------
+# Close output files
+#------------------------------------------------------------------------------
+close(RCFILE);
+close(EIFILE);
+close(ECFILE);
+close(CRFILE);
+close(SBFILE);
diff --git a/src/import/hwpf/fapi2/xml/attribute_info/chip_attributes.xml b/src/import/hwpf/fapi2/xml/attribute_info/chip_attributes.xml
new file mode 100644
index 00000000..116c209a
--- /dev/null
+++ b/src/import/hwpf/fapi2/xml/attribute_info/chip_attributes.xml
@@ -0,0 +1,59 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: import/hwpf/fapi2/xml/attribute_info/chip_attributes.xml $    -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<attributes>
+  <!-- ******************************************************************************** -->
+  <attribute>
+    <id>ATTR_NAME</id>
+    <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+      Product name of a chip target.
+      Provided by the MRW.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>
+      NONE = 0x0,
+      CENTAUR = 0x3,
+      NIMBUS = 0x5,
+      CUMULUS = 0x6
+    </enum>
+    <platInit/>
+    <privileged/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_EC</id>
+    <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        EC level of a chip target.
+        Read from the chip by the platform
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <!-- To make HWPs data driven, this is a privileged attribute that cannot
+         be accessed by normal HWPs. -->
+    <privileged/>
+  </attribute>
+  <!-- ********************************************************************* -->
+</attributes>
diff --git a/src/import/tools/imageProcs/fapi_sbe_common.H b/src/import/tools/imageProcs/fapi_sbe_common.H
new file mode 100644
index 00000000..3c29b7f4
--- /dev/null
+++ b/src/import/tools/imageProcs/fapi_sbe_common.H
@@ -0,0 +1,66 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: import/tools/imageProcs/fapi_sbe_common.H $                   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+/// \file fapi_sbe_common.H
+/// \brief provides several preprocessor macros used functions in fixed secion.
+///
+/// Several preprocessor macros are required to have different definitions in
+/// C, C++ and SBE assembly procedures.  These common forms are collected here.
+
+#ifndef __FAPI_SBE_COMMON_H
+#define __FAPI_SBE_COMMON_H
+
+/// Several preprocessor macros are required to have different definitions in
+/// C, C++ and SBE assembly procedures.  These common forms are collected here.
+
+#if defined __ASSEMBLER__
+
+    #define CONST_UINT8_T(name, expr) .set name, (expr)
+    #define CONST_UINT32_T(name, expr) .set name, (expr)
+    #define CONST_UINT64_T(name, expr) .set name, (expr)
+
+    #define ULL(x) x
+
+#elif defined __cplusplus
+
+    #include <stdint.h>
+
+    #define CONST_UINT8_T(name, expr) const uint8_t name = (expr);
+    #define CONST_UINT32_T(name, expr) const uint32_t name = (expr);
+    #define CONST_UINT64_T(name, expr) const uint64_t name = (expr);
+
+    #define ULL(x) x##ull
+
+#else // C code
+
+    // CONST_UINT[8,3,64]_T() can't be used in C code/headers; Use
+    //
+    //     #define <symbol> <value> [ or ULL(<value>) for 64-bit constants
+
+    #define ULL(x) x##ull
+
+#endif  // __ASSEMBLER__
+
+#endif  // __FAPI_SBE_COMMON_H